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Diffstat (limited to 'arch/blackfin/mach-bf527/include/mach/defBF52x_base.h')
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF52x_base.h2005
1 files changed, 2005 insertions, 0 deletions
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
new file mode 100644
index 000000000000..6ac2ed7026eb
--- /dev/null
+++ b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
@@ -0,0 +1,2005 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/defBF52x_base.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF52X_H
32#define _DEF_BF52X_H
33
34
35/* ************************************************************** */
36/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x */
37/* ************************************************************** */
38
39/* ==== begin from defBF534.h ==== */
40
41/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
42#define PLL_CTL 0xFFC00000 /* PLL Control Register */
43#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
44#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
45#define PLL_STAT 0xFFC0000C /* PLL Status Register */
46#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
47#define CHIPID 0xFFC00014 /* Device ID Register */
48
49
50/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
51#define SWRST 0xFFC00100 /* Software Reset Register */
52#define SYSCR 0xFFC00104 /* System Configuration Register */
53#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
54
55#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
56#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
57#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
58#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
59#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
60#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
61#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
62
63/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
64#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
65#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */
66#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */
67#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */
68#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */
69#define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */
70#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */
71
72
73/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
74#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
75#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
76#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
77
78
79/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
80#define RTC_STAT 0xFFC00300 /* RTC Status Register */
81#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
82#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
83#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
84#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
85#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
86#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
87
88
89/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
90#define UART0_THR 0xFFC00400 /* Transmit Holding register */
91#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
92#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
93#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
94#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
95#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
96#define UART0_LCR 0xFFC0040C /* Line Control Register */
97#define UART0_MCR 0xFFC00410 /* Modem Control Register */
98#define UART0_LSR 0xFFC00414 /* Line Status Register */
99#define UART0_MSR 0xFFC00418 /* Modem Status Register */
100#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
101#define UART0_GCTL 0xFFC00424 /* Global Control Register */
102
103
104/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
105#define SPI0_REGBASE 0xFFC00500
106#define SPI_CTL 0xFFC00500 /* SPI Control Register */
107#define SPI_FLG 0xFFC00504 /* SPI Flag register */
108#define SPI_STAT 0xFFC00508 /* SPI Status register */
109#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
110#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
111#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
112#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
113
114
115/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
116#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
117#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
118#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
119#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
120
121#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
122#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
123#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
124#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
125
126#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
127#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
128#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
129#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
130
131#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
132#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
133#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
134#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
135
136#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
137#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
138#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
139#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
140
141#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
142#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
143#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
144#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
145
146#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
147#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
148#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
149#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
150
151#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
152#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
153#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
154#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
155
156#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
157#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
158#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
159
160
161/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
162#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
163#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
164#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
165#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
166#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
167#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
168#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
169#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
170#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
171#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
172#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
173#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
174#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
175#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
176#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
177#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
178#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
179
180
181/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
182#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
183#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
184#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
185#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
186#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
187#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
188#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
189#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
190#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
191#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
192#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
193#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
194#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
195#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
196#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
197#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
198#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
199#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
200#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
201#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
202#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
203#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
204
205
206/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
207#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
208#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
209#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
210#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
211#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
212#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
213#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
214#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
215#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
216#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
217#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
218#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
219#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
220#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
221#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
222#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
223#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
224#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
225#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
226#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
227#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
228#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
229
230
231/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
232#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
233#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
234#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
235#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
236#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
237#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
238#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
239
240
241/* DMA Traffic Control Registers */
242#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
243#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
244
245/* Alternate deprecated register names (below) provided for backwards code compatibility */
246#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
247#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
248
249/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
250#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
251#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
252#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
253#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
254#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
255#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
256#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
257#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
258#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
259#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
260#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
261#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
262#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
263
264#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
265#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
266#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
267#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
268#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
269#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
270#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
271#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
272#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
273#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
274#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
275#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
276#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
277
278#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
279#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
280#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
281#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
282#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
283#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
284#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
285#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
286#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
287#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
288#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
289#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
290#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
291
292#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
293#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
294#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
295#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
296#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
297#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
298#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
299#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
300#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
301#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
302#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
303#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
304#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
305
306#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
307#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
308#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
309#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
310#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
311#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
312#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
313#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
314#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
315#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
316#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
317#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
318#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
319
320#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
321#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
322#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
323#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
324#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
325#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
326#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
327#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
328#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
329#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
330#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
331#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
332#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
333
334#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
335#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
336#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
337#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
338#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
339#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
340#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
341#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
342#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
343#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
344#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
345#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
346#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
347
348#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
349#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
350#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
351#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
352#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
353#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
354#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
355#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
356#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
357#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
358#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
359#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
360#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
361
362#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
363#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
364#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
365#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
366#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
367#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
368#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
369#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
370#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
371#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
372#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
373#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
374#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
375
376#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
377#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
378#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
379#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
380#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
381#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
382#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
383#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
384#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
385#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
386#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
387#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
388#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
389
390#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
391#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
392#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
393#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
394#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
395#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
396#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
397#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
398#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
399#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
400#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
401#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
402#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
403
404#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
405#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
406#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
407#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
408#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
409#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
410#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
411#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
412#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
413#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
414#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
415#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
416#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
417
418#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
419#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
420#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
421#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
422#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
423#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
424#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
425#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
426#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
427#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
428#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
429#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
430#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
431
432#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
433#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
434#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
435#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
436#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
437#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
438#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
439#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
440#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
441#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
442#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
443#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
444#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
445
446#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
447#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
448#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
449#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
450#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
451#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
452#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
453#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
454#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
455#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
456#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
457#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
458#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
459
460#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
461#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
462#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
463#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
464#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
465#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
466#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
467#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
468#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
469#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
470#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
471#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
472#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
473
474
475/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
476#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
477#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
478#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
479#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
480#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
481
482
483/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
484#define TWI0_REGBASE 0xFFC01400
485#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
486#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
487#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
488#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
489#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
490#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
491#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
492#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
493#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
494#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
495#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
496#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
497#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
498#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
499#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
500#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
501
502
503/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
504#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
505#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
506#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
507#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
508#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
509#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
510#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
511#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
512#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
513#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
514#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
515#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
516#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
517#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
518#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
519#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
520#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
521
522
523/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
524#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
525#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
526#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
527#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
528#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
529#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
530#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
531#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
532#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
533#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
534#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
535#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
536#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
537#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
538#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
539#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
540#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
541
542
543/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
544#define UART1_THR 0xFFC02000 /* Transmit Holding register */
545#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
546#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
547#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
548#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
549#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
550#define UART1_LCR 0xFFC0200C /* Line Control Register */
551#define UART1_MCR 0xFFC02010 /* Modem Control Register */
552#define UART1_LSR 0xFFC02014 /* Line Status Register */
553#define UART1_MSR 0xFFC02018 /* Modem Status Register */
554#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
555#define UART1_GCTL 0xFFC02024 /* Global Control Register */
556
557
558/* Omit CAN register sets from the defBF534.h (CAN is not in the ADSP-BF52x processor) */
559
560/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
561#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
562#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
563#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
564#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
565
566
567/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
568#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
569#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
570#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
571#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
572#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
573#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
574#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
575
576#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
577#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
578#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
579#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
580#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
581#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
582#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
583
584/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
585#define PORTF_MUX 0xFFC03210 /* Port F mux control */
586#define PORTG_MUX 0xFFC03214 /* Port G mux control */
587#define PORTH_MUX 0xFFC03218 /* Port H mux control */
588#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */
589#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */
590#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */
591#define PORTF_SLEW 0xFFC03230 /* Port F slew control */
592#define PORTG_SLEW 0xFFC03234 /* Port G slew control */
593#define PORTH_SLEW 0xFFC03238 /* Port H slew control */
594#define PORTF_HYSTERISIS 0xFFC03240 /* Port F Schmitt trigger control */
595#define PORTG_HYSTERISIS 0xFFC03244 /* Port G Schmitt trigger control */
596#define PORTH_HYSTERISIS 0xFFC03248 /* Port H Schmitt trigger control */
597#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */
598#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */
599#define MISCPORT_HYSTERISIS 0xFFC03288 /* Misc Port Schmitt trigger control */
600
601
602/***********************************************************************************
603** System MMR Register Bits And Macros
604**
605** Disclaimer: All macros are intended to make C and Assembly code more readable.
606** Use these macros carefully, as any that do left shifts for field
607** depositing will result in the lower order bits being destroyed. Any
608** macro that shifts left to properly position the bit-field should be
609** used as part of an OR to initialize a register and NOT as a dynamic
610** modifier UNLESS the lower order bits are saved and ORed back in when
611** the macro is used.
612*************************************************************************************/
613/*
614** ********************* PLL AND RESET MASKS ****************************************/
615/* PLL_CTL Masks */
616#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
617#define PLL_OFF 0x0002 /* PLL Not Powered */
618#define STOPCK 0x0008 /* Core Clock Off */
619#define PDWN 0x0020 /* Enter Deep Sleep Mode */
620#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
621#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
622#define BYPASS 0x0100 /* Bypass the PLL */
623#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
624/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
625#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
626
627/* PLL_DIV Masks */
628#define SSEL 0x000F /* System Select */
629#define CSEL 0x0030 /* Core Select */
630#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
631#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
632#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
633#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
634/* PLL_DIV Macros */
635#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
636
637/* VR_CTL Masks */
638#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */
639#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
640
641#define VLEV 0x00F0 /* Internal Voltage Level */
642#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
643#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
644#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
645#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
646#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
647#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
648#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
649#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
650#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
651#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
652
653#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
654#define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */
655#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
656#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
657#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */
658#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */
659
660/* PLL_STAT Masks */
661#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
662#define FULL_ON 0x0002 /* Processor In Full On Mode */
663#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
664#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
665
666/* CHIPID Masks */
667#define CHIPID_VERSION 0xF0000000
668#define CHIPID_FAMILY 0x0FFFF000
669#define CHIPID_MANUFACTURE 0x00000FFE
670
671/* SWRST Masks */
672#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
673#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
674#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
675#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
676#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
677
678/* SYSCR Masks */
679#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
680#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
681
682
683/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
684/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
685
686#if 0
687#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
688
689#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
690#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
691#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */
692#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */
693#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */
694#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */
695#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */
696
697#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */
698#define IRQ_TWI 0x00000200 /* TWI Interrupt */
699#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */
700#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */
701#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */
702#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */
703#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */
704#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */
705
706#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */
707#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */
708#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */
709#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */
710#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */
711#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */
712#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */
713#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */
714#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */
715#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */
716
717#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */
718#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */
719#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */
720#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */
721#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */
722#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */
723#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
724#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */
725#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
726#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */
727#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */
728#endif
729
730/* SIC_IAR0 Macros */
731#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
732#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
733#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
734#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
735#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
736#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
737#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
738#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
739
740/* SIC_IAR1 Macros */
741#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
742#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
743#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
744#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
745#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
746#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
747#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
748#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
749
750/* SIC_IAR2 Macros */
751#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
752#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
753#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
754#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
755#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
756#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
757#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
758#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
759
760/* SIC_IAR3 Macros */
761#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
762#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
763#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
764#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
765#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
766#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
767#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
768#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
769
770
771/* SIC_IMASK Masks */
772#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
773#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
774#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
775#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
776
777/* SIC_IWR Masks */
778#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
779#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
780#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
781#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
782
783
784/* ********* WATCHDOG TIMER MASKS ******************** */
785
786/* Watchdog Timer WDOG_CTL Register Masks */
787
788#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
789#define WDEV_RESET 0x0000 /* generate reset event on roll over */
790#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
791#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
792#define WDEV_NONE 0x0006 /* no event on roll over */
793#define WDEN 0x0FF0 /* enable watchdog */
794#define WDDIS 0x0AD0 /* disable watchdog */
795#define WDRO 0x8000 /* watchdog rolled over latch */
796
797/* depreciated WDOG_CTL Register Masks for legacy code */
798
799
800#define ICTL WDEV
801#define ENABLE_RESET WDEV_RESET
802#define WDOG_RESET WDEV_RESET
803#define ENABLE_NMI WDEV_NMI
804#define WDOG_NMI WDEV_NMI
805#define ENABLE_GPI WDEV_GPI
806#define WDOG_GPI WDEV_GPI
807#define DISABLE_EVT WDEV_NONE
808#define WDOG_NONE WDEV_NONE
809
810#define TMR_EN WDEN
811#define TMR_DIS WDDIS
812#define TRO WDRO
813#define ICTL_P0 0x01
814 #define ICTL_P1 0x02
815#define TRO_P 0x0F
816
817
818
819/* *************** REAL TIME CLOCK MASKS **************************/
820/* RTC_STAT and RTC_ALARM Masks */
821#define RTC_SEC 0x0000003F /* Real-Time Clock Seconds */
822#define RTC_MIN 0x00000FC0 /* Real-Time Clock Minutes */
823#define RTC_HR 0x0001F000 /* Real-Time Clock Hours */
824#define RTC_DAY 0xFFFE0000 /* Real-Time Clock Days */
825
826/* RTC_ALARM Macro z=day y=hr x=min w=sec */
827#define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
828
829/* RTC_ICTL and RTC_ISTAT Masks */
830#define STOPWATCH 0x0001 /* Stopwatch Interrupt Enable */
831#define ALARM 0x0002 /* Alarm Interrupt Enable */
832#define SECOND 0x0004 /* Seconds (1 Hz) Interrupt Enable */
833#define MINUTE 0x0008 /* Minutes Interrupt Enable */
834#define HOUR 0x0010 /* Hours Interrupt Enable */
835#define DAY 0x0020 /* 24 Hours (Days) Interrupt Enable */
836#define DAY_ALARM 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
837#define WRITE_PENDING 0x4000 /* Write Pending Status */
838#define WRITE_COMPLETE 0x8000 /* Write Complete Interrupt Enable */
839
840/* RTC_FAST / RTC_PREN Mask */
841#define PREN 0x0001 /* Enable Prescaler, RTC Runs @1 Hz */
842
843
844/* ************** UART CONTROLLER MASKS *************************/
845/* UARTx_LCR Masks */
846#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
847#define STB 0x04 /* Stop Bits */
848#define PEN 0x08 /* Parity Enable */
849#define EPS 0x10 /* Even Parity Select */
850#define STP 0x20 /* Stick Parity */
851#define SB 0x40 /* Set Break */
852#define DLAB 0x80 /* Divisor Latch Access */
853
854/* UARTx_MCR Mask */
855#define LOOP_ENA 0x10 /* Loopback Mode Enable */
856#define LOOP_ENA_P 0x04
857
858/* UARTx_LSR Masks */
859#define DR 0x01 /* Data Ready */
860#define OE 0x02 /* Overrun Error */
861#define PE 0x04 /* Parity Error */
862#define FE 0x08 /* Framing Error */
863#define BI 0x10 /* Break Interrupt */
864#define THRE 0x20 /* THR Empty */
865#define TEMT 0x40 /* TSR and UART_THR Empty */
866
867/* UARTx_IER Masks */
868#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
869#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
870#define ELSI 0x04 /* Enable RX Status Interrupt */
871
872/* UARTx_IIR Masks */
873#define NINT 0x01 /* Pending Interrupt */
874#define IIR_TX_READY 0x02 /* UART_THR empty */
875#define IIR_RX_READY 0x04 /* Receive data ready */
876#define IIR_LINE_CHANGE 0x06 /* Receive line status */
877#define IIR_STATUS 0x06 /* Highest Priority Pending Interrupt */
878
879/* UARTx_GCTL Masks */
880#define UCEN 0x01 /* Enable UARTx Clocks */
881#define IREN 0x02 /* Enable IrDA Mode */
882#define TPOLC 0x04 /* IrDA TX Polarity Change */
883#define RPOLC 0x08 /* IrDA RX Polarity Change */
884#define FPE 0x10 /* Force Parity Error On Transmit */
885#define FFE 0x20 /* Force Framing Error On Transmit */
886
887
888/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/
889/* SPI_CTL Masks */
890#define TIMOD 0x0003 /* Transfer Initiate Mode */
891#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
892#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
893#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
894#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
895#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
896#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
897#define PSSE 0x0010 /* Slave-Select Input Enable */
898#define EMISO 0x0020 /* Enable MISO As Output */
899#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
900#define LSBF 0x0200 /* LSB First */
901#define CPHA 0x0400 /* Clock Phase */
902#define CPOL 0x0800 /* Clock Polarity */
903#define MSTR 0x1000 /* Master/Slave* */
904#define WOM 0x2000 /* Write Open Drain Master */
905#define SPE 0x4000 /* SPI Enable */
906
907/* SPI_FLG Masks */
908#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */
909#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */
910#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */
911#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */
912#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */
913#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */
914#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */
915#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */
916#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */
917#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */
918#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */
919#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */
920#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */
921#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */
922
923/* SPI_STAT Masks */
924#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */
925#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */
926#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */
927#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */
928#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */
929#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */
930#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */
931
932
933/* **************** GENERAL PURPOSE TIMER MASKS **********************/
934/* TIMER_ENABLE Masks */
935#define TIMEN0 0x0001 /* Enable Timer 0 */
936#define TIMEN1 0x0002 /* Enable Timer 1 */
937#define TIMEN2 0x0004 /* Enable Timer 2 */
938#define TIMEN3 0x0008 /* Enable Timer 3 */
939#define TIMEN4 0x0010 /* Enable Timer 4 */
940#define TIMEN5 0x0020 /* Enable Timer 5 */
941#define TIMEN6 0x0040 /* Enable Timer 6 */
942#define TIMEN7 0x0080 /* Enable Timer 7 */
943
944/* TIMER_DISABLE Masks */
945#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
946#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
947#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
948#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
949#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
950#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
951#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
952#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
953
954/* TIMER_STATUS Masks */
955#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
956#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
957#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
958#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
959#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
960#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
961#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
962#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
963#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
964#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
965#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
966#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
967#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
968#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
969#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
970#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
971#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
972#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
973#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
974#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
975#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
976#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
977#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
978#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
979
980/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
981#define TOVL_ERR0 TOVF_ERR0
982#define TOVL_ERR1 TOVF_ERR1
983#define TOVL_ERR2 TOVF_ERR2
984#define TOVL_ERR3 TOVF_ERR3
985#define TOVL_ERR4 TOVF_ERR4
986#define TOVL_ERR5 TOVF_ERR5
987#define TOVL_ERR6 TOVF_ERR6
988#define TOVL_ERR7 TOVF_ERR7
989
990/* TIMERx_CONFIG Masks */
991#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
992#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
993#define EXT_CLK 0x0003 /* External Clock Mode */
994#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
995#define PERIOD_CNT 0x0008 /* Period Count */
996#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
997#define TIN_SEL 0x0020 /* Timer Input Select */
998#define OUT_DIS 0x0040 /* Output Pad Disable */
999#define CLK_SEL 0x0080 /* Timer Clock Select */
1000#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
1001#define EMU_RUN 0x0200 /* Emulation Behavior Select */
1002#define ERR_TYP 0xC000 /* Error Type */
1003
1004
1005/* ****************** GPIO PORTS F, G, H MASKS ***********************/
1006/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
1007/* Port F Masks */
1008#define PF0 0x0001
1009#define PF1 0x0002
1010#define PF2 0x0004
1011#define PF3 0x0008
1012#define PF4 0x0010
1013#define PF5 0x0020
1014#define PF6 0x0040
1015#define PF7 0x0080
1016#define PF8 0x0100
1017#define PF9 0x0200
1018#define PF10 0x0400
1019#define PF11 0x0800
1020#define PF12 0x1000
1021#define PF13 0x2000
1022#define PF14 0x4000
1023#define PF15 0x8000
1024
1025/* Port G Masks */
1026#define PG0 0x0001
1027#define PG1 0x0002
1028#define PG2 0x0004
1029#define PG3 0x0008
1030#define PG4 0x0010
1031#define PG5 0x0020
1032#define PG6 0x0040
1033#define PG7 0x0080
1034#define PG8 0x0100
1035#define PG9 0x0200
1036#define PG10 0x0400
1037#define PG11 0x0800
1038#define PG12 0x1000
1039#define PG13 0x2000
1040#define PG14 0x4000
1041#define PG15 0x8000
1042
1043/* Port H Masks */
1044#define PH0 0x0001
1045#define PH1 0x0002
1046#define PH2 0x0004
1047#define PH3 0x0008
1048#define PH4 0x0010
1049#define PH5 0x0020
1050#define PH6 0x0040
1051#define PH7 0x0080
1052#define PH8 0x0100
1053#define PH9 0x0200
1054#define PH10 0x0400
1055#define PH11 0x0800
1056#define PH12 0x1000
1057#define PH13 0x2000
1058#define PH14 0x4000
1059#define PH15 0x8000
1060
1061
1062/* ******************* SERIAL PORT MASKS **************************************/
1063/* SPORTx_TCR1 Masks */
1064#define TSPEN 0x0001 /* Transmit Enable */
1065#define ITCLK 0x0002 /* Internal Transmit Clock Select */
1066#define DTYPE_NORM 0x0004 /* Data Format Normal */
1067#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1068#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1069#define TLSBIT 0x0010 /* Transmit Bit Order */
1070#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */
1071#define TFSR 0x0400 /* Transmit Frame Sync Required Select */
1072#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */
1073#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
1074#define LATFS 0x2000 /* Late Transmit Frame Sync Select */
1075#define TCKFE 0x4000 /* Clock Falling Edge Select */
1076
1077/* SPORTx_TCR2 Masks and Macro */
1078#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
1079#define TXSE 0x0100 /* TX Secondary Enable */
1080#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
1081#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
1082
1083/* SPORTx_RCR1 Masks */
1084#define RSPEN 0x0001 /* Receive Enable */
1085#define IRCLK 0x0002 /* Internal Receive Clock Select */
1086#define DTYPE_NORM 0x0004 /* Data Format Normal */
1087#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1088#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1089#define RLSBIT 0x0010 /* Receive Bit Order */
1090#define IRFS 0x0200 /* Internal Receive Frame Sync Select */
1091#define RFSR 0x0400 /* Receive Frame Sync Required Select */
1092#define LRFS 0x1000 /* Low Receive Frame Sync Select */
1093#define LARFS 0x2000 /* Late Receive Frame Sync Select */
1094#define RCKFE 0x4000 /* Clock Falling Edge Select */
1095
1096/* SPORTx_RCR2 Masks */
1097#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
1098#define RXSE 0x0100 /* RX Secondary Enable */
1099#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
1100#define RRFST 0x0400 /* Right-First Data Order */
1101
1102/* SPORTx_STAT Masks */
1103#define RXNE 0x0001 /* Receive FIFO Not Empty Status */
1104#define RUVF 0x0002 /* Sticky Receive Underflow Status */
1105#define ROVF 0x0004 /* Sticky Receive Overflow Status */
1106#define TXF 0x0008 /* Transmit FIFO Full Status */
1107#define TUVF 0x0010 /* Sticky Transmit Underflow Status */
1108#define TOVF 0x0020 /* Sticky Transmit Overflow Status */
1109#define TXHRE 0x0040 /* Transmit Hold Register Empty */
1110
1111/* SPORTx_MCMC1 Macros */
1112#define SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
1113
1114/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
1115#define SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
1116
1117/* SPORTx_MCMC2 Masks */
1118#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
1119#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
1120#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
1121#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
1122#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
1123#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
1124#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
1125#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
1126#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
1127#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
1128#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
1129#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
1130#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
1131#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
1132#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
1133#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
1134#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
1135#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
1136#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
1137#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
1138#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
1139#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
1140#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
1141
1142
1143/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
1144/* EBIU_AMGCTL Masks */
1145#define AMCKEN 0x0001 /* Enable CLKOUT */
1146#define AMBEN_NONE 0x0000 /* All Banks Disabled */
1147#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
1148#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
1149#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
1150#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
1151
1152/* EBIU_AMBCTL0 Masks */
1153#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
1154#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
1155#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
1156#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
1157#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
1158#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
1159#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
1160#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
1161#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
1162#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
1163#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1164#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1165#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1166#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1167#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
1168#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
1169#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
1170#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
1171#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
1172#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
1173#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
1174#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
1175#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
1176#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
1177#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
1178#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
1179#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
1180#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
1181#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
1182#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
1183#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
1184#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
1185#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
1186#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
1187#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
1188#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
1189#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
1190#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
1191#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
1192#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
1193#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
1194#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
1195#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
1196#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
1197
1198#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
1199#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
1200#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
1201#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
1202#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
1203#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
1204#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
1205#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
1206#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
1207#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
1208#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1209#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1210#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1211#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1212#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
1213#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
1214#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
1215#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
1216#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
1217#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
1218#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
1219#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
1220#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
1221#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
1222#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
1223#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
1224#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
1225#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
1226#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
1227#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
1228#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
1229#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
1230#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
1231#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
1232#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
1233#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
1234#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
1235#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
1236#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
1237#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
1238#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
1239#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
1240#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
1241#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
1242
1243/* EBIU_AMBCTL1 Masks */
1244#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
1245#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
1246#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
1247#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
1248#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
1249#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
1250#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
1251#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
1252#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
1253#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
1254#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1255#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1256#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1257#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1258#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
1259#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
1260#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
1261#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
1262#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
1263#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
1264#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
1265#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
1266#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
1267#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
1268#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
1269#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
1270#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
1271#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
1272#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
1273#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
1274#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
1275#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
1276#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
1277#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
1278#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
1279#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
1280#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
1281#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
1282#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
1283#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
1284#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
1285#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
1286#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
1287#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
1288
1289#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
1290#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
1291#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
1292#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
1293#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
1294#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
1295#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
1296#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
1297#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
1298#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
1299#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1300#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1301#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1302#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1303#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
1304#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
1305#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
1306#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
1307#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
1308#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
1309#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
1310#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
1311#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
1312#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
1313#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
1314#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
1315#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
1316#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
1317#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
1318#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
1319#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
1320#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
1321#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
1322#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
1323#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
1324#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
1325#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
1326#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
1327#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
1328#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
1329#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
1330#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
1331#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
1332#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
1333
1334
1335/* ********************** SDRAM CONTROLLER MASKS **********************************************/
1336/* EBIU_SDGCTL Masks */
1337#define SCTLE 0x00000001 /* Enable SDRAM Signals */
1338#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
1339#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
1340#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
1341#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
1342#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
1343#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
1344#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
1345#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
1346#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
1347#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
1348#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
1349#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
1350#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
1351#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
1352#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
1353#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
1354#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
1355#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
1356#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
1357#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
1358#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
1359#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
1360#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
1361#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
1362#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
1363#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
1364#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
1365#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
1366#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
1367#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
1368#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
1369#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
1370#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
1371#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
1372#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
1373#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
1374#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
1375#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
1376#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
1377#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
1378#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
1379#define EBUFE 0x02000000 /* Enable External Buffering Timing */
1380#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
1381#define EMREN 0x10000000 /* Extended Mode Register Enable */
1382#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
1383#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
1384
1385/* EBIU_SDBCTL Masks */
1386#define EBE 0x0001 /* Enable SDRAM External Bank */
1387#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
1388#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
1389#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
1390#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
1391#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
1392#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
1393#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
1394#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
1395#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
1396#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
1397
1398/* EBIU_SDSTAT Masks */
1399#define SDCI 0x0001 /* SDRAM Controller Idle */
1400#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
1401#define SDPUA 0x0004 /* SDRAM Power-Up Active */
1402#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
1403#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
1404#define BGSTAT 0x0020 /* Bus Grant Status */
1405
1406
1407/* ************************** DMA CONTROLLER MASKS ********************************/
1408/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
1409#define DMAEN 0x0001 /* DMA Channel Enable */
1410#define WNR 0x0002 /* Channel Direction (W/R*) */
1411#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
1412#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
1413#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
1414#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
1415#define RESTART 0x0020 /* DMA Buffer Clear */
1416#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
1417#define DI_EN 0x0080 /* Data Interrupt Enable */
1418#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
1419#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
1420#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
1421#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
1422#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
1423#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
1424#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
1425#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
1426#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
1427#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
1428#define NDSIZE 0x0900 /* Next Descriptor Size */
1429#define DMAFLOW 0x7000 /* Flow Control */
1430#define DMAFLOW_STOP 0x0000 /* Stop Mode */
1431#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
1432#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
1433#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
1434#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
1435
1436/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
1437#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
1438#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
1439#define PMAP_PPI 0x0000 /* PPI Port DMA */
1440#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
1441#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
1442#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
1443#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
1444#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
1445#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
1446#define PMAP_SPI 0x7000 /* SPI Port DMA */
1447#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
1448#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
1449#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
1450#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
1451
1452/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
1453#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
1454#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
1455#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
1456#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
1457
1458
1459/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
1460/* PPI_CONTROL Masks */
1461#define PORT_EN 0x0001 /* PPI Port Enable */
1462#define PORT_DIR 0x0002 /* PPI Port Direction */
1463#define XFR_TYPE 0x000C /* PPI Transfer Type */
1464#define PORT_CFG 0x0030 /* PPI Port Configuration */
1465#define FLD_SEL 0x0040 /* PPI Active Field Select */
1466#define PACK_EN 0x0080 /* PPI Packing Mode */
1467#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
1468#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
1469#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
1470#define DLEN_8 0x0000 /* Data Length = 8 Bits */
1471#define DLEN_10 0x0800 /* Data Length = 10 Bits */
1472#define DLEN_11 0x1000 /* Data Length = 11 Bits */
1473#define DLEN_12 0x1800 /* Data Length = 12 Bits */
1474#define DLEN_13 0x2000 /* Data Length = 13 Bits */
1475#define DLEN_14 0x2800 /* Data Length = 14 Bits */
1476#define DLEN_15 0x3000 /* Data Length = 15 Bits */
1477#define DLEN_16 0x3800 /* Data Length = 16 Bits */
1478#define DLENGTH 0x3800 /* PPI Data Length */
1479#define POLC 0x4000 /* PPI Clock Polarity */
1480#define POLS 0x8000 /* PPI Frame Sync Polarity */
1481
1482/* PPI_STATUS Masks */
1483#define FLD 0x0400 /* Field Indicator */
1484#define FT_ERR 0x0800 /* Frame Track Error */
1485#define OVR 0x1000 /* FIFO Overflow Error */
1486#define UNDR 0x2000 /* FIFO Underrun Error */
1487#define ERR_DET 0x4000 /* Error Detected Indicator */
1488#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
1489
1490
1491/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
1492/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
1493#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
1494#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
1495
1496/* TWI_PRESCALE Masks */
1497#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
1498#define TWI_ENA 0x0080 /* TWI Enable */
1499#define SCCB 0x0200 /* SCCB Compatibility Enable */
1500
1501/* TWI_SLAVE_CTRL Masks */
1502#define SEN 0x0001 /* Slave Enable */
1503#define SADD_LEN 0x0002 /* Slave Address Length */
1504#define STDVAL 0x0004 /* Slave Transmit Data Valid */
1505#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
1506#define GEN 0x0010 /* General Call Adrress Matching Enabled */
1507
1508/* TWI_SLAVE_STAT Masks */
1509#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
1510#define GCALL 0x0002 /* General Call Indicator */
1511
1512/* TWI_MASTER_CTRL Masks */
1513#define MEN 0x0001 /* Master Mode Enable */
1514#define MADD_LEN 0x0002 /* Master Address Length */
1515#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
1516#define FAST 0x0008 /* Use Fast Mode Timing Specs */
1517#define STOP 0x0010 /* Issue Stop Condition */
1518#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
1519#define DCNT 0x3FC0 /* Data Bytes To Transfer */
1520#define SDAOVR 0x4000 /* Serial Data Override */
1521#define SCLOVR 0x8000 /* Serial Clock Override */
1522
1523/* TWI_MASTER_STAT Masks */
1524#define MPROG 0x0001 /* Master Transfer In Progress */
1525#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
1526#define ANAK 0x0004 /* Address Not Acknowledged */
1527#define DNAK 0x0008 /* Data Not Acknowledged */
1528#define BUFRDERR 0x0010 /* Buffer Read Error */
1529#define BUFWRERR 0x0020 /* Buffer Write Error */
1530#define SDASEN 0x0040 /* Serial Data Sense */
1531#define SCLSEN 0x0080 /* Serial Clock Sense */
1532#define BUSBUSY 0x0100 /* Bus Busy Indicator */
1533
1534/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
1535#define SINIT 0x0001 /* Slave Transfer Initiated */
1536#define SCOMP 0x0002 /* Slave Transfer Complete */
1537#define SERR 0x0004 /* Slave Transfer Error */
1538#define SOVF 0x0008 /* Slave Overflow */
1539#define MCOMP 0x0010 /* Master Transfer Complete */
1540#define MERR 0x0020 /* Master Transfer Error */
1541#define XMTSERV 0x0040 /* Transmit FIFO Service */
1542#define RCVSERV 0x0080 /* Receive FIFO Service */
1543
1544/* TWI_FIFO_CTRL Masks */
1545#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
1546#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
1547#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
1548#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
1549
1550/* TWI_FIFO_STAT Masks */
1551#define XMTSTAT 0x0003 /* Transmit FIFO Status */
1552#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
1553#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
1554#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
1555
1556#define RCVSTAT 0x000C /* Receive FIFO Status */
1557#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
1558#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
1559#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
1560
1561
1562/* Omit CAN masks from defBF534.h */
1563
1564/* ******************* PIN CONTROL REGISTER MASKS ************************/
1565/* PORT_MUX Masks */
1566#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
1567#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
1568#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
1569
1570#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
1571#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
1572#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
1573#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
1574
1575#define PFDE 0x0008 /* Port F DMA Request Enable */
1576#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
1577#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
1578
1579#define PFTE 0x0010 /* Port F Timer Enable */
1580#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
1581#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
1582
1583#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
1584#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
1585#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
1586
1587#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
1588#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
1589#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
1590
1591#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
1592#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
1593#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
1594
1595#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
1596#define PFFE_TIMER 0x0000 /* Enable TMR2 */
1597#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
1598
1599#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
1600#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
1601#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
1602
1603#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
1604#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
1605#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
1606
1607#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
1608#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
1609#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
1610
1611
1612/* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/
1613/* HDMAx_CTL Masks */
1614#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */
1615#define REP 0x0002 /* HDMA Request Polarity */
1616#define UTE 0x0004 /* Urgency Threshold Enable */
1617#define OIE 0x0010 /* Overflow Interrupt Enable */
1618#define BDIE 0x0020 /* Block Done Interrupt Enable */
1619#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */
1620#define DRQ 0x0300 /* HDMA Request Type */
1621#define DRQ_NONE 0x0000 /* No Request */
1622#define DRQ_SINGLE 0x0100 /* Channels Request Single */
1623#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */
1624#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */
1625#define RBC 0x1000 /* Reload BCNT With IBCNT */
1626#define PS 0x2000 /* HDMA Pin Status */
1627#define OI 0x4000 /* Overflow Interrupt Generated */
1628#define BDI 0x8000 /* Block Done Interrupt Generated */
1629
1630/* entry addresses of the user-callable Boot ROM functions */
1631
1632#define _BOOTROM_RESET 0xEF000000
1633#define _BOOTROM_FINAL_INIT 0xEF000002
1634#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
1635#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
1636#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
1637#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
1638#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
1639#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
1640#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
1641
1642/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
1643#define PGDE_UART PFDE_UART
1644#define PGDE_DMA PFDE_DMA
1645#define CKELOW SCKELOW
1646
1647/* ==== end from defBF534.h ==== */
1648
1649/* HOST Port Registers */
1650
1651#define HOST_CONTROL 0xffc03400 /* HOST Control Register */
1652#define HOST_STATUS 0xffc03404 /* HOST Status Register */
1653#define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */
1654
1655/* Counter Registers */
1656
1657#define CNT_CONFIG 0xffc03500 /* Configuration Register */
1658#define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */
1659#define CNT_STATUS 0xffc03508 /* Status Register */
1660#define CNT_COMMAND 0xffc0350c /* Command Register */
1661#define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */
1662#define CNT_COUNTER 0xffc03514 /* Counter Register */
1663#define CNT_MAX 0xffc03518 /* Maximal Count Register */
1664#define CNT_MIN 0xffc0351c /* Minimal Count Register */
1665
1666/* OTP/FUSE Registers */
1667
1668#define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */
1669#define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */
1670#define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */
1671#define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */
1672
1673/* Security Registers */
1674
1675#define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */
1676#define SECURE_CONTROL 0xffc03624 /* Secure Control */
1677#define SECURE_STATUS 0xffc03628 /* Secure Status */
1678
1679/* OTP Read/Write Data Buffer Registers */
1680
1681#define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1682#define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1683#define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1684#define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1685
1686/* NFC Registers */
1687
1688#define NFC_CTL 0xffc03700 /* NAND Control Register */
1689#define NFC_STAT 0xffc03704 /* NAND Status Register */
1690#define NFC_IRQSTAT 0xffc03708 /* NAND Interrupt Status Register */
1691#define NFC_IRQMASK 0xffc0370c /* NAND Interrupt Mask Register */
1692#define NFC_ECC0 0xffc03710 /* NAND ECC Register 0 */
1693#define NFC_ECC1 0xffc03714 /* NAND ECC Register 1 */
1694#define NFC_ECC2 0xffc03718 /* NAND ECC Register 2 */
1695#define NFC_ECC3 0xffc0371c /* NAND ECC Register 3 */
1696#define NFC_COUNT 0xffc03720 /* NAND ECC Count Register */
1697#define NFC_RST 0xffc03724 /* NAND ECC Reset Register */
1698#define NFC_PGCTL 0xffc03728 /* NAND Page Control Register */
1699#define NFC_READ 0xffc0372c /* NAND Read Data Register */
1700#define NFC_ADDR 0xffc03740 /* NAND Address Register */
1701#define NFC_CMD 0xffc03744 /* NAND Command Register */
1702#define NFC_DATA_WR 0xffc03748 /* NAND Data Write Register */
1703#define NFC_DATA_RD 0xffc0374c /* NAND Data Read Register */
1704
1705/* ********************************************************** */
1706/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
1707/* and MULTI BIT READ MACROS */
1708/* ********************************************************** */
1709
1710/* Bit masks for HOST_CONTROL */
1711
1712#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */
1713#define HOST_CNTR_nHOST_EN 0x0
1714#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */
1715#define HOST_CNTR_nHOST_END 0x0
1716#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */
1717#define HOST_CNTR_nDATA_SIZE 0x0
1718#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */
1719#define HOST_CNTR_nHOST_RST 0x0
1720#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */
1721#define HOST_CNTR_nHRDY_OVR 0x0
1722#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */
1723#define HOST_CNTR_nINT_MODE 0x0
1724#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */
1725#define HOST_CNTR_ nBT_EN 0x0
1726#define HOST_CNTR_EHW 0x100 /* Enable Host Write */
1727#define HOST_CNTR_nEHW 0x0
1728#define HOST_CNTR_EHR 0x200 /* Enable Host Read */
1729#define HOST_CNTR_nEHR 0x0
1730#define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */
1731#define HOST_CNTR_nBDR 0x0
1732
1733/* Bit masks for HOST_STATUS */
1734
1735#define HOST_STAT_READY 0x1 /* DMA Ready */
1736#define HOST_STAT_nREADY 0x0
1737#define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */
1738#define HOST_STAT_nFIFOFULL 0x0
1739#define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */
1740#define HOST_STAT_nFIFOEMPTY 0x0
1741#define HOST_STAT_COMPLETE 0x8 /* DMA Complete */
1742#define HOST_STAT_nCOMPLETE 0x0
1743#define HOST_STAT_HSHK 0x10 /* Host Handshake */
1744#define HOST_STAT_nHSHK 0x0
1745#define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */
1746#define HOST_STAT_nTIMEOUT 0x0
1747#define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */
1748#define HOST_STAT_nHIRQ 0x0
1749#define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */
1750#define HOST_STAT_nALLOW_CNFG 0x0
1751#define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */
1752#define HOST_STAT_nDMA_DIR 0x0
1753#define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */
1754#define HOST_STAT_nBTE 0x0
1755#define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */
1756#define HOST_STAT_nHOSTRD_DONE 0x0
1757
1758/* Bit masks for HOST_TIMEOUT */
1759
1760#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */
1761
1762/* Bit masks for CNT_CONFIG */
1763
1764#define CNTE 0x1 /* Counter Enable */
1765#define nCNTE 0x0
1766#define DEBE 0x2 /* Debounce Enable */
1767#define nDEBE 0x0
1768#define CDGINV 0x10 /* CDG Pin Polarity Invert */
1769#define nCDGINV 0x0
1770#define CUDINV 0x20 /* CUD Pin Polarity Invert */
1771#define nCUDINV 0x0
1772#define CZMINV 0x40 /* CZM Pin Polarity Invert */
1773#define nCZMINV 0x0
1774#define CNTMODE 0x700 /* Counter Operating Mode */
1775#define ZMZC 0x800 /* CZM Zeroes Counter Enable */
1776#define nZMZC 0x0
1777#define BNDMODE 0x3000 /* Boundary register Mode */
1778#define INPDIS 0x8000 /* CUG and CDG Input Disable */
1779#define nINPDIS 0x0
1780
1781/* Bit masks for CNT_IMASK */
1782
1783#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */
1784#define nICIE 0x0
1785#define UCIE 0x2 /* Up count Interrupt Enable */
1786#define nUCIE 0x0
1787#define DCIE 0x4 /* Down count Interrupt Enable */
1788#define nDCIE 0x0
1789#define MINCIE 0x8 /* Min Count Interrupt Enable */
1790#define nMINCIE 0x0
1791#define MAXCIE 0x10 /* Max Count Interrupt Enable */
1792#define nMAXCIE 0x0
1793#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */
1794#define nCOV31IE 0x0
1795#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */
1796#define nCOV15IE 0x0
1797#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */
1798#define nCZEROIE 0x0
1799#define CZMIE 0x100 /* CZM Pin Interrupt Enable */
1800#define nCZMIE 0x0
1801#define CZMEIE 0x200 /* CZM Error Interrupt Enable */
1802#define nCZMEIE 0x0
1803#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */
1804#define nCZMZIE 0x0
1805
1806/* Bit masks for CNT_STATUS */
1807
1808#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */
1809#define nICII 0x0
1810#define UCII 0x2 /* Up count Interrupt Identifier */
1811#define nUCII 0x0
1812#define DCII 0x4 /* Down count Interrupt Identifier */
1813#define nDCII 0x0
1814#define MINCII 0x8 /* Min Count Interrupt Identifier */
1815#define nMINCII 0x0
1816#define MAXCII 0x10 /* Max Count Interrupt Identifier */
1817#define nMAXCII 0x0
1818#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */
1819#define nCOV31II 0x0
1820#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */
1821#define nCOV15II 0x0
1822#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */
1823#define nCZEROII 0x0
1824#define CZMII 0x100 /* CZM Pin Interrupt Identifier */
1825#define nCZMII 0x0
1826#define CZMEII 0x200 /* CZM Error Interrupt Identifier */
1827#define nCZMEII 0x0
1828#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */
1829#define nCZMZII 0x0
1830
1831/* Bit masks for CNT_COMMAND */
1832
1833#define W1LCNT 0xf /* Load Counter Register */
1834#define W1LMIN 0xf0 /* Load Min Register */
1835#define W1LMAX 0xf00 /* Load Max Register */
1836#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */
1837#define nW1ZMONCE 0x0
1838
1839/* Bit masks for CNT_DEBOUNCE */
1840
1841#define DPRESCALE 0xf /* Load Counter Register */
1842
1843/* Bit masks for OTP_CONTROL */
1844
1845#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
1846#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */
1847#define nFIEN 0x0
1848#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */
1849#define nFTESTDEC 0x0
1850#define FWRTEST 0x2000 /* OTP/Fuse Write Test */
1851#define nFWRTEST 0x0
1852#define FRDEN 0x4000 /* OTP/Fuse Read Enable */
1853#define nFRDEN 0x0
1854#define FWREN 0x8000 /* OTP/Fuse Write Enable */
1855#define nFWREN 0x0
1856
1857/* Bit masks for OTP_BEN */
1858
1859#define FBEN 0xffff /* OTP/Fuse Byte Enable */
1860
1861/* Bit masks for OTP_STATUS */
1862
1863#define FCOMP 0x1 /* OTP/Fuse Access Complete */
1864#define nFCOMP 0x0
1865#define FERROR 0x2 /* OTP/Fuse Access Error */
1866#define nFERROR 0x0
1867#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */
1868#define nMMRGLOAD 0x0
1869#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */
1870#define nMMRGLOCK 0x0
1871#define FPGMEN 0x40 /* OTP/Fuse Program Enable */
1872#define nFPGMEN 0x0
1873
1874/* Bit masks for OTP_TIMING */
1875
1876#define USECDIV 0xff /* Micro Second Divider */
1877#define READACC 0x7f00 /* Read Access Time */
1878#define CPUMPRL 0x38000 /* Charge Pump Release Time */
1879#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */
1880#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */
1881#define PGMTIME 0xff000000 /* Program Time */
1882
1883/* Bit masks for SECURE_SYSSWT */
1884
1885#define EMUDABL 0x1 /* Emulation Disable. */
1886#define nEMUDABL 0x0
1887#define RSTDABL 0x2 /* Reset Disable */
1888#define nRSTDABL 0x0
1889#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
1890#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
1891#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
1892#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
1893#define nDMA0OVR 0x0
1894#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
1895#define nDMA1OVR 0x0
1896#define EMUOVR 0x4000 /* Emulation Override */
1897#define nEMUOVR 0x0
1898#define OTPSEN 0x8000 /* OTP Secrets Enable. */
1899#define nOTPSEN 0x0
1900#define L2DABL 0x70000 /* L2 Memory Disable. */
1901
1902/* Bit masks for SECURE_CONTROL */
1903
1904#define SECURE0 0x1 /* SECURE 0 */
1905#define nSECURE0 0x0
1906#define SECURE1 0x2 /* SECURE 1 */
1907#define nSECURE1 0x0
1908#define SECURE2 0x4 /* SECURE 2 */
1909#define nSECURE2 0x0
1910#define SECURE3 0x8 /* SECURE 3 */
1911#define nSECURE3 0x0
1912
1913/* Bit masks for SECURE_STATUS */
1914
1915#define SECMODE 0x3 /* Secured Mode Control State */
1916#define NMI 0x4 /* Non Maskable Interrupt */
1917#define nNMI 0x0
1918#define AFVALID 0x8 /* Authentication Firmware Valid */
1919#define nAFVALID 0x0
1920#define AFEXIT 0x10 /* Authentication Firmware Exit */
1921#define nAFEXIT 0x0
1922#define SECSTAT 0xe0 /* Secure Status */
1923
1924/* Bit masks for NFC_CTL */
1925
1926#define WR_DLY 0xf /* Write Strobe Delay */
1927#define RD_DLY 0xf0 /* Read Strobe Delay */
1928#define NWIDTH 0x100 /* NAND Data Width */
1929#define nNWIDTH 0x0
1930#define PG_SIZE 0x200 /* Page Size */
1931#define nPG_SIZE 0x0
1932
1933/* Bit masks for NFC_STAT */
1934
1935#define NBUSY 0x1 /* Not Busy */
1936#define nNBUSY 0x0
1937#define WB_FULL 0x2 /* Write Buffer Full */
1938#define nWB_FULL 0x0
1939#define PG_WR_STAT 0x4 /* Page Write Pending */
1940#define nPG_WR_STAT 0x0
1941#define PG_RD_STAT 0x8 /* Page Read Pending */
1942#define nPG_RD_STAT 0x0
1943#define WB_EMPTY 0x10 /* Write Buffer Empty */
1944#define nWB_EMPTY 0x0
1945
1946/* Bit masks for NFC_IRQSTAT */
1947
1948#define NBUSYIRQ 0x1 /* Not Busy IRQ */
1949#define nNBUSYIRQ 0x0
1950#define WB_OVF 0x2 /* Write Buffer Overflow */
1951#define nWB_OVF 0x0
1952#define WB_EDGE 0x4 /* Write Buffer Edge Detect */
1953#define nWB_EDGE 0x0
1954#define RD_RDY 0x8 /* Read Data Ready */
1955#define nRD_RDY 0x0
1956#define WR_DONE 0x10 /* Page Write Done */
1957#define nWR_DONE 0x0
1958
1959/* Bit masks for NFC_IRQMASK */
1960
1961#define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */
1962#define nMASK_BUSYIRQ 0x0
1963#define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */
1964#define nMASK_WBOVF 0x0
1965#define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */
1966#define nMASK_WBEMPTY 0x0
1967#define MASK_RDRDY 0x8 /* Mask Read Data Ready */
1968#define nMASK_RDRDY 0x0
1969#define MASK_WRDONE 0x10 /* Mask Write Done */
1970#define nMASK_WRDONE 0x0
1971
1972/* Bit masks for NFC_RST */
1973
1974#define ECC_RST 0x1 /* ECC (and NFC counters) Reset */
1975#define nECC_RST 0x0
1976
1977/* Bit masks for NFC_PGCTL */
1978
1979#define PG_RD_START 0x1 /* Page Read Start */
1980#define nPG_RD_START 0x0
1981#define PG_WR_START 0x2 /* Page Write Start */
1982#define nPG_WR_START 0x0
1983
1984/* Bit masks for NFC_ECC0 */
1985
1986#define ECC0 0x7ff /* Parity Calculation Result0 */
1987
1988/* Bit masks for NFC_ECC1 */
1989
1990#define ECC1 0x7ff /* Parity Calculation Result1 */
1991
1992/* Bit masks for NFC_ECC2 */
1993
1994#define ECC2 0x7ff /* Parity Calculation Result2 */
1995
1996/* Bit masks for NFC_ECC3 */
1997
1998#define ECC3 0x7ff /* Parity Calculation Result3 */
1999
2000/* Bit masks for NFC_COUNT */
2001
2002#define ECCCNT 0x3ff /* Transfer Count */
2003
2004
2005#endif /* _DEF_BF52X_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 10:33:12 -0500