1 files changed, 111 insertions, 151 deletions
diff --git a/arch/blackfin/mach-bf518/include/mach/irq.h b/arch/blackfin/mach-bf518/include/mach/irq.h
index 435e76e31aaa..edf8efd457dc 100644
--- a/arch/blackfin/mach-bf518/include/mach/irq.h
+++ b/arch/blackfin/mach-bf518/include/mach/irq.h
@@ -7,38 +7,9 @@
 #ifndef _BF518_IRQ_H_
 #define _BF518_IRQ_H_
-/*
+#include <mach-common/irq.h>
- * Interrupt source definitions
-        Event Source    Core Event Name
+#define NR_PERI_INTS            (2 * 32)
-        Core        Emulation               **
-        Events         (highest priority)  EMU         0
-        Reset                   RST         1
-        NMI                     NMI         2
-        Exception               EVX         3
-        Reserved                --          4
-        Hardware Error          IVHW        5
-        Core Timer              IVTMR       6 *
-        .....
-         Software Interrupt 1    IVG14       31
-         Software Interrupt 2    --
-         (lowest priority)  IVG15       32 *
-*/
-#define NR_PERI_INTS    (2 * 32)
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU                 0       /* Emulation */
-#define IRQ_RST                 1       /* reset */
-#define IRQ_NMI                 2       /* Non Maskable */
-#define IRQ_EVX                 3       /* Exception */
-#define IRQ_UNUSED              4       /* - unused interrupt */
-#define IRQ_HWERR               5       /* Hardware Error */
-#define IRQ_CORETMR             6       /* Core timer */
-#define BFIN_IRQ(x)             ((x) + 7)
 #define IRQ_PLL_WAKEUP          BFIN_IRQ(0)     /* PLL Wakeup Interrupt */
 #define IRQ_DMA0_ERROR          BFIN_IRQ(1)     /* DMA Error 0 (generic) */
@@ -54,23 +25,23 @@
 #define IRQ_UART0_ERROR         BFIN_IRQ(12)    /* UART0 Status */
 #define IRQ_UART1_ERROR         BFIN_IRQ(13)    /* UART1 Status */
 #define IRQ_RTC                 BFIN_IRQ(14)    /* RTC */
-#define IRQ_PPI                 BFIN_IRQ(15)    /* DMA Channel 0 (PPI) */
+#define IRQ_PPI                 BFIN_IRQ(15)    /* DMA Channel 0 (PPI) */
 #define IRQ_SPORT0_RX           BFIN_IRQ(16)    /* DMA 3 Channel (SPORT0 RX) */
 #define IRQ_SPORT0_TX           BFIN_IRQ(17)    /* DMA 4 Channel (SPORT0 TX) */
 #define IRQ_RSI                 BFIN_IRQ(17)    /* DMA 4 Channel (RSI) */
 #define IRQ_SPORT1_RX           BFIN_IRQ(18)    /* DMA 5 Channel (SPORT1 RX/SPI) */
 #define IRQ_SPI1                BFIN_IRQ(18)    /* DMA 5 Channel (SPI1) */
 #define IRQ_SPORT1_TX           BFIN_IRQ(19)    /* DMA 6 Channel (SPORT1 TX) */
-#define IRQ_TWI                 BFIN_IRQ(20)    /* TWI */
+#define IRQ_TWI                 BFIN_IRQ(20)    /* TWI */
-#define IRQ_SPI0                BFIN_IRQ(21)    /* DMA 7 Channel (SPI0) */
+#define IRQ_SPI0                BFIN_IRQ(21)    /* DMA 7 Channel (SPI0) */
-#define IRQ_UART0_RX            BFIN_IRQ(22)    /* DMA8 Channel (UART0 RX) */
+#define IRQ_UART0_RX            BFIN_IRQ(22)    /* DMA8 Channel (UART0 RX) */
-#define IRQ_UART0_TX            BFIN_IRQ(23)    /* DMA9 Channel (UART0 TX) */
+#define IRQ_UART0_TX            BFIN_IRQ(23)    /* DMA9 Channel (UART0 TX) */
-#define IRQ_UART1_RX            BFIN_IRQ(24)    /* DMA10 Channel (UART1 RX) */
+#define IRQ_UART1_RX            BFIN_IRQ(24)    /* DMA10 Channel (UART1 RX) */
-#define IRQ_UART1_TX            BFIN_IRQ(25)    /* DMA11 Channel (UART1 TX) */
+#define IRQ_UART1_TX            BFIN_IRQ(25)    /* DMA11 Channel (UART1 TX) */
-#define IRQ_OPTSEC              BFIN_IRQ(26)    /* OTPSEC Interrupt */
+#define IRQ_OPTSEC              BFIN_IRQ(26)    /* OTPSEC Interrupt */
-#define IRQ_CNT                 BFIN_IRQ(27)    /* GP Counter */
+#define IRQ_CNT                 BFIN_IRQ(27)    /* GP Counter */
-#define IRQ_MAC_RX              BFIN_IRQ(28)    /* DMA1 Channel (MAC RX) */
+#define IRQ_MAC_RX              BFIN_IRQ(28)    /* DMA1 Channel (MAC RX) */
-#define IRQ_PORTH_INTA          BFIN_IRQ(29)    /* Port H Interrupt A */
+#define IRQ_PORTH_INTA          BFIN_IRQ(29)    /* Port H Interrupt A */
 #define IRQ_MAC_TX              BFIN_IRQ(30)    /* DMA2 Channel (MAC TX) */
 #define IRQ_PORTH_INTB          BFIN_IRQ(31)    /* Port H Interrupt B */
 #define IRQ_TIMER0              BFIN_IRQ(32)    /* Timer 0 */
@@ -96,101 +67,90 @@
 #define IRQ_PWM_SYNC            BFIN_IRQ(54)    /* PWM Sync Interrupt */
 #define IRQ_PTP_STAT            BFIN_IRQ(55)    /* PTP Stat Interrupt */
-#define SYS_IRQS                BFIN_IRQ(63)    /* 70 */
+#define SYS_IRQS                BFIN_IRQ(63)    /* 70 */
-#define IRQ_PF0         71
+#define IRQ_PF0                 71
-#define IRQ_PF1         72
+#define IRQ_PF1                 72
-#define IRQ_PF2         73
+#define IRQ_PF2                 73
-#define IRQ_PF3         74
+#define IRQ_PF3                 74
-#define IRQ_PF4         75
+#define IRQ_PF4                 75
-#define IRQ_PF5         76
+#define IRQ_PF5                 76
-#define IRQ_PF6         77
+#define IRQ_PF6                 77
-#define IRQ_PF7         78
+#define IRQ_PF7                 78
-#define IRQ_PF8         79
+#define IRQ_PF8                 79
-#define IRQ_PF9         80
+#define IRQ_PF9                 80
-#define IRQ_PF10        81
+#define IRQ_PF10                81
-#define IRQ_PF11        82
+#define IRQ_PF11                82
-#define IRQ_PF12        83
+#define IRQ_PF12                83
-#define IRQ_PF13        84
+#define IRQ_PF13                84
-#define IRQ_PF14        85
+#define IRQ_PF14                85
-#define IRQ_PF15        86
+#define IRQ_PF15                86
-#define IRQ_PG0         87
+#define IRQ_PG0                 87
-#define IRQ_PG1         88
+#define IRQ_PG1                 88
-#define IRQ_PG2         89
+#define IRQ_PG2                 89
-#define IRQ_PG3         90
+#define IRQ_PG3                 90
-#define IRQ_PG4         91
+#define IRQ_PG4                 91
-#define IRQ_PG5         92
+#define IRQ_PG5                 92
-#define IRQ_PG6         93
+#define IRQ_PG6                 93
-#define IRQ_PG7         94
+#define IRQ_PG7                 94
-#define IRQ_PG8         95
+#define IRQ_PG8                 95
-#define IRQ_PG9         96
+#define IRQ_PG9                 96
-#define IRQ_PG10        97
+#define IRQ_PG10                97
-#define IRQ_PG11        98
+#define IRQ_PG11                98
-#define IRQ_PG12        99
+#define IRQ_PG12                99
-#define IRQ_PG13        100
+#define IRQ_PG13                100
-#define IRQ_PG14        101
+#define IRQ_PG14                101
-#define IRQ_PG15        102
+#define IRQ_PG15                102
-#define IRQ_PH0         103
+#define IRQ_PH0                 103
-#define IRQ_PH1         104
+#define IRQ_PH1                 104
-#define IRQ_PH2         105
+#define IRQ_PH2                 105
-#define IRQ_PH3         106
+#define IRQ_PH3                 106
-#define IRQ_PH4         107
+#define IRQ_PH4                 107
-#define IRQ_PH5         108
+#define IRQ_PH5                 108
-#define IRQ_PH6         109
+#define IRQ_PH6                 109
-#define IRQ_PH7         110
+#define IRQ_PH7                 110
-#define IRQ_PH8         111
+#define IRQ_PH8                 111
-#define IRQ_PH9         112
+#define IRQ_PH9                 112
-#define IRQ_PH10        113
+#define IRQ_PH10                113
-#define IRQ_PH11        114
+#define IRQ_PH11                114
-#define IRQ_PH12        115
+#define IRQ_PH12                115
-#define IRQ_PH13        116
+#define IRQ_PH13                116
-#define IRQ_PH14        117
+#define IRQ_PH14                117
-#define IRQ_PH15        118
+#define IRQ_PH15                118
-#define GPIO_IRQ_BASE   IRQ_PF0
+#define GPIO_IRQ_BASE           IRQ_PF0
-#define IRQ_MAC_PHYINT          119 /* PHY_INT Interrupt */
+#define IRQ_MAC_PHYINT          119     /* PHY_INT Interrupt */
-#define IRQ_MAC_MMCINT          120 /* MMC Counter Interrupt */
+#define IRQ_MAC_MMCINT          120     /* MMC Counter Interrupt */
-#define IRQ_MAC_RXFSINT         121 /* RX Frame-Status Interrupt */
+#define IRQ_MAC_RXFSINT         121     /* RX Frame-Status Interrupt */
-#define IRQ_MAC_TXFSINT         122 /* TX Frame-Status Interrupt */
+#define IRQ_MAC_TXFSINT         122     /* TX Frame-Status Interrupt */
-#define IRQ_MAC_WAKEDET         123 /* Wake-Up Interrupt */
+#define IRQ_MAC_WAKEDET         123     /* Wake-Up Interrupt */
-#define IRQ_MAC_RXDMAERR        124 /* RX DMA Direction Error Interrupt */
+#define IRQ_MAC_RXDMAERR        124     /* RX DMA Direction Error Interrupt */
-#define IRQ_MAC_TXDMAERR        125 /* TX DMA Direction Error Interrupt */
+#define IRQ_MAC_TXDMAERR        125     /* TX DMA Direction Error Interrupt */
-#define IRQ_MAC_STMDONE         126 /* Station Mgt. Transfer Done Interrupt */
+#define IRQ_MAC_STMDONE         126     /* Station Mgt. Transfer Done Interrupt */
-#define NR_MACH_IRQS    (IRQ_MAC_STMDONE + 1)
+#define NR_MACH_IRQS            (IRQ_MAC_STMDONE + 1)
-#define NR_IRQS         (NR_MACH_IRQS + NR_SPARE_IRQS)
-#define IVG7            7
-#define IVG8            8
-#define IVG9            9
-#define IVG10           10
-#define IVG11           11
-#define IVG12           12
-#define IVG13           13
-#define IVG14           14
-#define IVG15           15
 /* IAR0 BIT FIELDS */
 #define IRQ_PLL_WAKEUP_POS      0
 #define IRQ_DMA0_ERROR_POS      4
-#define IRQ_DMAR0_BLK_POS       8
+#define IRQ_DMAR0_BLK_POS       8
-#define IRQ_DMAR1_BLK_POS       12
+#define IRQ_DMAR1_BLK_POS       12
-#define IRQ_DMAR0_OVR_POS       16
+#define IRQ_DMAR0_OVR_POS       16
-#define IRQ_DMAR1_OVR_POS       20
+#define IRQ_DMAR1_OVR_POS       20
-#define IRQ_PPI_ERROR_POS       24
+#define IRQ_PPI_ERROR_POS       24
-#define IRQ_MAC_ERROR_POS       28
+#define IRQ_MAC_ERROR_POS       28
 /* IAR1 BIT FIELDS */
 #define IRQ_SPORT0_ERROR_POS    0
 #define IRQ_SPORT1_ERROR_POS    4
 #define IRQ_PTP_ERROR_POS       8
-#define IRQ_UART0_ERROR_POS     16
+#define IRQ_UART0_ERROR_POS     16
-#define IRQ_UART1_ERROR_POS     20
+#define IRQ_UART1_ERROR_POS     20
-#define IRQ_RTC_POS             24
+#define IRQ_RTC_POS             24
-#define IRQ_PPI_POS             28
+#define IRQ_PPI_POS             28
 /* IAR2 BIT FIELDS */
 #define IRQ_SPORT0_RX_POS       0
@@ -199,19 +159,19 @@
 #define IRQ_SPORT1_RX_POS       8
 #define IRQ_SPI1_POS            8
 #define IRQ_SPORT1_TX_POS       12
-#define IRQ_TWI_POS             16
+#define IRQ_TWI_POS             16
-#define IRQ_SPI0_POS            20
+#define IRQ_SPI0_POS            20
-#define IRQ_UART0_RX_POS        24
+#define IRQ_UART0_RX_POS        24
-#define IRQ_UART0_TX_POS        28
+#define IRQ_UART0_TX_POS        28
 /* IAR3 BIT FIELDS */
-#define IRQ_UART1_RX_POS        0
+#define IRQ_UART1_RX_POS        0
-#define IRQ_UART1_TX_POS        4
+#define IRQ_UART1_TX_POS        4
-#define IRQ_OPTSEC_POS          8
+#define IRQ_OPTSEC_POS          8
-#define IRQ_CNT_POS             12
+#define IRQ_CNT_POS             12
-#define IRQ_MAC_RX_POS          16
+#define IRQ_MAC_RX_POS          16
 #define IRQ_PORTH_INTA_POS      20
-#define IRQ_MAC_TX_POS          24
+#define IRQ_MAC_TX_POS          24
 #define IRQ_PORTH_INTB_POS      28
 /* IAR4 BIT FIELDS */
@@ -227,19 +187,19 @@
 /* IAR5 BIT FIELDS */
 #define IRQ_PORTG_INTA_POS      0
 #define IRQ_PORTG_INTB_POS      4
-#define IRQ_MEM_DMA0_POS        8
+#define IRQ_MEM_DMA0_POS        8
-#define IRQ_MEM_DMA1_POS        12
+#define IRQ_MEM_DMA1_POS        12
-#define IRQ_WATCH_POS           16
+#define IRQ_WATCH_POS           16
 #define IRQ_PORTF_INTA_POS      20
 #define IRQ_PORTF_INTB_POS      24
-#define IRQ_SPI0_ERROR_POS      28
+#define IRQ_SPI0_ERROR_POS      28
 /* IAR6 BIT FIELDS */
-#define IRQ_SPI1_ERROR_POS      0
+#define IRQ_SPI1_ERROR_POS      0
-#define IRQ_RSI_INT0_POS        12
+#define IRQ_RSI_INT0_POS        12
-#define IRQ_RSI_INT1_POS        16
+#define IRQ_RSI_INT1_POS        16
-#define IRQ_PWM_TRIP_POS        20
+#define IRQ_PWM_TRIP_POS        20
-#define IRQ_PWM_SYNC_POS        24
+#define IRQ_PWM_SYNC_POS        24
-#define IRQ_PTP_STAT_POS        28
+#define IRQ_PTP_STAT_POS        28
-#endif                          /* _BF518_IRQ_H_ */
+#endif

diff --git a/arch/blackfin/mach-bf518/include/mach/irq.h b/arch/blackfin/mach-bf518/include/mach/irq.h index 435e76e31aaa..edf8efd457dc 100644 --- a/arch/blackfin/mach-bf518/include/mach/irq.h +++ b/arch/blackfin/mach-bf518/include/mach/irq.h
@@ -7,38 +7,9 @@
7	#ifndef _BF518_IRQ_H_	7	#ifndef _BF518_IRQ_H_
8	#define _BF518_IRQ_H_	8	#define _BF518_IRQ_H_
9		9
10	/*	10	#include <mach-common/irq.h>
11	* Interrupt source definitions	11
12	Event Source Core Event Name	12	#define NR_PERI_INTS (2 * 32)
13	Core Emulation **
14	Events (highest priority) EMU 0
15	Reset RST 1
16	NMI NMI 2
17	Exception EVX 3
18	Reserved -- 4
19	Hardware Error IVHW 5
20	Core Timer IVTMR 6 *
21
22	.....
23
24	Software Interrupt 1 IVG14 31
25	Software Interrupt 2 --
26	(lowest priority) IVG15 32 *
27	*/
28
29	#define NR_PERI_INTS (2 * 32)
30
31	/* The ABSTRACT IRQ definitions */
32	/ the first seven of the following are fixed, the rest you change if you need to /
33	#define IRQ_EMU 0 /* Emulation */
34	#define IRQ_RST 1 /* reset */
35	#define IRQ_NMI 2 /* Non Maskable */
36	#define IRQ_EVX 3 /* Exception */
37	#define IRQ_UNUSED 4 /* - unused interrupt */
38	#define IRQ_HWERR 5 /* Hardware Error */
39	#define IRQ_CORETMR 6 /* Core timer */
40
41	#define BFIN_IRQ(x) ((x) + 7)
42		13
43	#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */	14	#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
44	#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */	15	#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
@@ -54,23 +25,23 @@
54	#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */	25	#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
55	#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */	26	#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
56	#define IRQ_RTC BFIN_IRQ(14) /* RTC */	27	#define IRQ_RTC BFIN_IRQ(14) /* RTC */
57	#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI) */	28	#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI) */
58	#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */	29	#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
59	#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */	30	#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
60	#define IRQ_RSI BFIN_IRQ(17) /* DMA 4 Channel (RSI) */	31	#define IRQ_RSI BFIN_IRQ(17) /* DMA 4 Channel (RSI) */
61	#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX/SPI) */	32	#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX/SPI) */
62	#define IRQ_SPI1 BFIN_IRQ(18) /* DMA 5 Channel (SPI1) */	33	#define IRQ_SPI1 BFIN_IRQ(18) /* DMA 5 Channel (SPI1) */
63	#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */	34	#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
64	#define IRQ_TWI BFIN_IRQ(20) /* TWI */	35	#define IRQ_TWI BFIN_IRQ(20) /* TWI */
65	#define IRQ_SPI0 BFIN_IRQ(21) /* DMA 7 Channel (SPI0) */	36	#define IRQ_SPI0 BFIN_IRQ(21) /* DMA 7 Channel (SPI0) */
66	#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */	37	#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
67	#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */	38	#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
68	#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */	39	#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
69	#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */	40	#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
70	#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */	41	#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
71	#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */	42	#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
72	#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX) */	43	#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX) */
73	#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */	44	#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
74	#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX) */	45	#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX) */
75	#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */	46	#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
76	#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */	47	#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */
@@ -96,101 +67,90 @@
96	#define IRQ_PWM_SYNC BFIN_IRQ(54) /* PWM Sync Interrupt */	67	#define IRQ_PWM_SYNC BFIN_IRQ(54) /* PWM Sync Interrupt */
97	#define IRQ_PTP_STAT BFIN_IRQ(55) /* PTP Stat Interrupt */	68	#define IRQ_PTP_STAT BFIN_IRQ(55) /* PTP Stat Interrupt */
98		69
99	#define SYS_IRQS BFIN_IRQ(63) /* 70 */	70	#define SYS_IRQS BFIN_IRQ(63) /* 70 */
100		71
101	#define IRQ_PF0 71	72	#define IRQ_PF0 71
102	#define IRQ_PF1 72	73	#define IRQ_PF1 72
103	#define IRQ_PF2 73	74	#define IRQ_PF2 73
104	#define IRQ_PF3 74	75	#define IRQ_PF3 74
105	#define IRQ_PF4 75	76	#define IRQ_PF4 75
106	#define IRQ_PF5 76	77	#define IRQ_PF5 76
107	#define IRQ_PF6 77	78	#define IRQ_PF6 77
108	#define IRQ_PF7 78	79	#define IRQ_PF7 78
109	#define IRQ_PF8 79	80	#define IRQ_PF8 79
110	#define IRQ_PF9 80	81	#define IRQ_PF9 80
111	#define IRQ_PF10 81	82	#define IRQ_PF10 81
112	#define IRQ_PF11 82	83	#define IRQ_PF11 82
113	#define IRQ_PF12 83	84	#define IRQ_PF12 83
114	#define IRQ_PF13 84	85	#define IRQ_PF13 84
115	#define IRQ_PF14 85	86	#define IRQ_PF14 85
116	#define IRQ_PF15 86	87	#define IRQ_PF15 86
117		88
118	#define IRQ_PG0 87	89	#define IRQ_PG0 87
119	#define IRQ_PG1 88	90	#define IRQ_PG1 88
120	#define IRQ_PG2 89	91	#define IRQ_PG2 89
121	#define IRQ_PG3 90	92	#define IRQ_PG3 90
122	#define IRQ_PG4 91	93	#define IRQ_PG4 91
123	#define IRQ_PG5 92	94	#define IRQ_PG5 92
124	#define IRQ_PG6 93	95	#define IRQ_PG6 93
125	#define IRQ_PG7 94	96	#define IRQ_PG7 94
126	#define IRQ_PG8 95	97	#define IRQ_PG8 95
127	#define IRQ_PG9 96	98	#define IRQ_PG9 96
128	#define IRQ_PG10 97	99	#define IRQ_PG10 97
129	#define IRQ_PG11 98	100	#define IRQ_PG11 98
130	#define IRQ_PG12 99	101	#define IRQ_PG12 99
131	#define IRQ_PG13 100	102	#define IRQ_PG13 100
132	#define IRQ_PG14 101	103	#define IRQ_PG14 101
133	#define IRQ_PG15 102	104	#define IRQ_PG15 102
134		105
135	#define IRQ_PH0 103	106	#define IRQ_PH0 103
136	#define IRQ_PH1 104	107	#define IRQ_PH1 104
137	#define IRQ_PH2 105	108	#define IRQ_PH2 105
138	#define IRQ_PH3 106	109	#define IRQ_PH3 106
139	#define IRQ_PH4 107	110	#define IRQ_PH4 107
140	#define IRQ_PH5 108	111	#define IRQ_PH5 108
141	#define IRQ_PH6 109	112	#define IRQ_PH6 109
142	#define IRQ_PH7 110	113	#define IRQ_PH7 110
143	#define IRQ_PH8 111	114	#define IRQ_PH8 111
144	#define IRQ_PH9 112	115	#define IRQ_PH9 112
145	#define IRQ_PH10 113	116	#define IRQ_PH10 113
146	#define IRQ_PH11 114	117	#define IRQ_PH11 114
147	#define IRQ_PH12 115	118	#define IRQ_PH12 115
148	#define IRQ_PH13 116	119	#define IRQ_PH13 116
149	#define IRQ_PH14 117	120	#define IRQ_PH14 117
150	#define IRQ_PH15 118	121	#define IRQ_PH15 118
151		122
152	#define GPIO_IRQ_BASE IRQ_PF0	123	#define GPIO_IRQ_BASE IRQ_PF0
153		124
154	#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */	125	#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
155	#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */	126	#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
156	#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */	127	#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
157	#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */	128	#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
158	#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */	129	#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
159	#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */	130	#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
160	#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */	131	#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
161	#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */	132	#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
162		133
163	#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)	134	#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
164	#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
165
166	#define IVG7 7
167	#define IVG8 8
168	#define IVG9 9
169	#define IVG10 10
170	#define IVG11 11
171	#define IVG12 12
172	#define IVG13 13
173	#define IVG14 14
174	#define IVG15 15
175		135
176	/* IAR0 BIT FIELDS */	136	/* IAR0 BIT FIELDS */
177	#define IRQ_PLL_WAKEUP_POS 0	137	#define IRQ_PLL_WAKEUP_POS 0
178	#define IRQ_DMA0_ERROR_POS 4	138	#define IRQ_DMA0_ERROR_POS 4
179	#define IRQ_DMAR0_BLK_POS 8	139	#define IRQ_DMAR0_BLK_POS 8
180	#define IRQ_DMAR1_BLK_POS 12	140	#define IRQ_DMAR1_BLK_POS 12
181	#define IRQ_DMAR0_OVR_POS 16	141	#define IRQ_DMAR0_OVR_POS 16
182	#define IRQ_DMAR1_OVR_POS 20	142	#define IRQ_DMAR1_OVR_POS 20
183	#define IRQ_PPI_ERROR_POS 24	143	#define IRQ_PPI_ERROR_POS 24
184	#define IRQ_MAC_ERROR_POS 28	144	#define IRQ_MAC_ERROR_POS 28
185		145
186	/* IAR1 BIT FIELDS */	146	/* IAR1 BIT FIELDS */
187	#define IRQ_SPORT0_ERROR_POS 0	147	#define IRQ_SPORT0_ERROR_POS 0
188	#define IRQ_SPORT1_ERROR_POS 4	148	#define IRQ_SPORT1_ERROR_POS 4
189	#define IRQ_PTP_ERROR_POS 8	149	#define IRQ_PTP_ERROR_POS 8
190	#define IRQ_UART0_ERROR_POS 16	150	#define IRQ_UART0_ERROR_POS 16
191	#define IRQ_UART1_ERROR_POS 20	151	#define IRQ_UART1_ERROR_POS 20
192	#define IRQ_RTC_POS 24	152	#define IRQ_RTC_POS 24
193	#define IRQ_PPI_POS 28	153	#define IRQ_PPI_POS 28
194		154
195	/* IAR2 BIT FIELDS */	155	/* IAR2 BIT FIELDS */
196	#define IRQ_SPORT0_RX_POS 0	156	#define IRQ_SPORT0_RX_POS 0
@@ -199,19 +159,19 @@
199	#define IRQ_SPORT1_RX_POS 8	159	#define IRQ_SPORT1_RX_POS 8
200	#define IRQ_SPI1_POS 8	160	#define IRQ_SPI1_POS 8
201	#define IRQ_SPORT1_TX_POS 12	161	#define IRQ_SPORT1_TX_POS 12
202	#define IRQ_TWI_POS 16	162	#define IRQ_TWI_POS 16
203	#define IRQ_SPI0_POS 20	163	#define IRQ_SPI0_POS 20
204	#define IRQ_UART0_RX_POS 24	164	#define IRQ_UART0_RX_POS 24
205	#define IRQ_UART0_TX_POS 28	165	#define IRQ_UART0_TX_POS 28
206		166
207	/* IAR3 BIT FIELDS */	167	/* IAR3 BIT FIELDS */
208	#define IRQ_UART1_RX_POS 0	168	#define IRQ_UART1_RX_POS 0
209	#define IRQ_UART1_TX_POS 4	169	#define IRQ_UART1_TX_POS 4
210	#define IRQ_OPTSEC_POS 8	170	#define IRQ_OPTSEC_POS 8
211	#define IRQ_CNT_POS 12	171	#define IRQ_CNT_POS 12
212	#define IRQ_MAC_RX_POS 16	172	#define IRQ_MAC_RX_POS 16
213	#define IRQ_PORTH_INTA_POS 20	173	#define IRQ_PORTH_INTA_POS 20
214	#define IRQ_MAC_TX_POS 24	174	#define IRQ_MAC_TX_POS 24
215	#define IRQ_PORTH_INTB_POS 28	175	#define IRQ_PORTH_INTB_POS 28
216		176
217	/* IAR4 BIT FIELDS */	177	/* IAR4 BIT FIELDS */
@@ -227,19 +187,19 @@
227	/* IAR5 BIT FIELDS */	187	/* IAR5 BIT FIELDS */
228	#define IRQ_PORTG_INTA_POS 0	188	#define IRQ_PORTG_INTA_POS 0
229	#define IRQ_PORTG_INTB_POS 4	189	#define IRQ_PORTG_INTB_POS 4
230	#define IRQ_MEM_DMA0_POS 8	190	#define IRQ_MEM_DMA0_POS 8
231	#define IRQ_MEM_DMA1_POS 12	191	#define IRQ_MEM_DMA1_POS 12
232	#define IRQ_WATCH_POS 16	192	#define IRQ_WATCH_POS 16
233	#define IRQ_PORTF_INTA_POS 20	193	#define IRQ_PORTF_INTA_POS 20
234	#define IRQ_PORTF_INTB_POS 24	194	#define IRQ_PORTF_INTB_POS 24
235	#define IRQ_SPI0_ERROR_POS 28	195	#define IRQ_SPI0_ERROR_POS 28
236		196
237	/* IAR6 BIT FIELDS */	197	/* IAR6 BIT FIELDS */
238	#define IRQ_SPI1_ERROR_POS 0	198	#define IRQ_SPI1_ERROR_POS 0
239	#define IRQ_RSI_INT0_POS 12	199	#define IRQ_RSI_INT0_POS 12
240	#define IRQ_RSI_INT1_POS 16	200	#define IRQ_RSI_INT1_POS 16
241	#define IRQ_PWM_TRIP_POS 20	201	#define IRQ_PWM_TRIP_POS 20
242	#define IRQ_PWM_SYNC_POS 24	202	#define IRQ_PWM_SYNC_POS 24
243	#define IRQ_PTP_STAT_POS 28	203	#define IRQ_PTP_STAT_POS 28
244		204
245	#endif /* _BF518_IRQ_H_ */	205	#endif