1 files changed, 63 insertions, 28 deletions

diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index ac71dc15cbdb..536bd9d7e0cf 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -29,6 +29,7 @@
 #include <asm/cpu.h>
 #include <asm/fixed_code.h>
 #include <asm/early_printk.h>
+#include <asm/irq_handler.h>
 
 u16 _bfin_swrst;
 EXPORT_SYMBOL(_bfin_swrst);
@@ -105,6 +106,8 @@ void __cpuinit bfin_setup_caches(unsigned int cpu)
         bfin_dcache_init(dcplb_tbl[cpu]);
 #endif
 
+        bfin_setup_cpudata(cpu);
+
         /*
          * In cache coherence emulation mode, we need to have the
          * D-cache enabled before running any atomic operation which
@@ -163,7 +166,6 @@ void __cpuinit bfin_setup_cpudata(unsigned int cpu)
 {
         struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu);
 
-        cpudata->idle = current;
         cpudata->imemctl = bfin_read_IMEM_CONTROL();
         cpudata->dmemctl = bfin_read_DMEM_CONTROL();
 }
@@ -215,11 +217,48 @@ void __init bfin_relocate_l1_mem(void)
 
         early_dma_memcpy_done();
 
+#if defined(CONFIG_SMP) && defined(CONFIG_ICACHE_FLUSH_L1)
+        blackfin_iflush_l1_entry[0] = (unsigned long)blackfin_icache_flush_range_l1;
+#endif
+
         /* if necessary, copy L2 text/data to L2 SRAM */
         if (L2_LENGTH && l2_len)
                 memcpy(_stext_l2, _l2_lma, l2_len);
 }
 
+#ifdef CONFIG_SMP
+void __init bfin_relocate_coreb_l1_mem(void)
+{
+        unsigned long text_l1_len = (unsigned long)_text_l1_len;
+        unsigned long data_l1_len = (unsigned long)_data_l1_len;
+        unsigned long data_b_l1_len = (unsigned long)_data_b_l1_len;
+
+        blackfin_dma_early_init();
+
+        /* if necessary, copy L1 text to L1 instruction SRAM */
+        if (L1_CODE_LENGTH && text_l1_len)
+                early_dma_memcpy((void *)COREB_L1_CODE_START, _text_l1_lma,
+                                text_l1_len);
+
+        /* if necessary, copy L1 data to L1 data bank A SRAM */
+        if (L1_DATA_A_LENGTH && data_l1_len)
+                early_dma_memcpy((void *)COREB_L1_DATA_A_START, _data_l1_lma,
+                                data_l1_len);
+
+        /* if necessary, copy L1 data B to L1 data bank B SRAM */
+        if (L1_DATA_B_LENGTH && data_b_l1_len)
+                early_dma_memcpy((void *)COREB_L1_DATA_B_START, _data_b_l1_lma,
+                                data_b_l1_len);
+
+        early_dma_memcpy_done();
+
+#ifdef CONFIG_ICACHE_FLUSH_L1
+        blackfin_iflush_l1_entry[1] = (unsigned long)blackfin_icache_flush_range_l1 -
+                        (unsigned long)_stext_l1 + COREB_L1_CODE_START;
+#endif
+}
+#endif
+
 #ifdef CONFIG_ROMKERNEL
 void __init bfin_relocate_xip_data(void)
 {
@@ -814,6 +853,7 @@ void __init native_machine_early_platform_add_devices(void)
 
 void __init setup_arch(char **cmdline_p)
 {
+        u32 mmr;
         unsigned long sclk, cclk;
 
         native_machine_early_platform_add_devices();
@@ -865,10 +905,10 @@ void __init setup_arch(char **cmdline_p)
         bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL);
 #endif
 #ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
-        bfin_write_PORTF_HYSTERISIS(HYST_PORTF_0_15);
-        bfin_write_PORTG_HYSTERISIS(HYST_PORTG_0_15);
-        bfin_write_PORTH_HYSTERISIS(HYST_PORTH_0_15);
-        bfin_write_MISCPORT_HYSTERISIS((bfin_read_MISCPORT_HYSTERISIS() &
+        bfin_write_PORTF_HYSTERESIS(HYST_PORTF_0_15);
+        bfin_write_PORTG_HYSTERESIS(HYST_PORTG_0_15);
+        bfin_write_PORTH_HYSTERESIS(HYST_PORTH_0_15);
+        bfin_write_MISCPORT_HYSTERESIS((bfin_read_MISCPORT_HYSTERESIS() &
                                         ~HYST_NONEGPIO_MASK) | HYST_NONEGPIO);
 #endif
 
@@ -884,17 +924,14 @@ void __init setup_arch(char **cmdline_p)
                 bfin_read_IMDMA_D1_IRQ_STATUS();
         }
 #endif
-        printk(KERN_INFO "Hardware Trace ");
-        if (bfin_read_TBUFCTL() & 0x1)
-                printk(KERN_CONT "Active ");
-        else
-                printk(KERN_CONT "Off ");
-        if (bfin_read_TBUFCTL() & 0x2)
-                printk(KERN_CONT "and Enabled\n");
-        else
-                printk(KERN_CONT "and Disabled\n");
 
-        printk(KERN_INFO "Boot Mode: %i\n", bfin_read_SYSCR() & 0xF);
+        mmr = bfin_read_TBUFCTL();
+        printk(KERN_INFO "Hardware Trace %s and %sabled\n",
+                (mmr & 0x1) ? "active" : "off",
+                (mmr & 0x2) ? "en" : "dis");
+
+        mmr = bfin_read_SYSCR();
+        printk(KERN_INFO "Boot Mode: %i\n", mmr & 0xF);
 
         /* Newer parts mirror SWRST bits in SYSCR */
 #if defined(CONFIG_BF53x) || defined(CONFIG_BF561) || \
@@ -902,7 +939,7 @@ void __init setup_arch(char **cmdline_p)
         _bfin_swrst = bfin_read_SWRST();
 #else
         /* Clear boot mode field */
-        _bfin_swrst = bfin_read_SYSCR() & ~0xf;
+        _bfin_swrst = mmr & ~0xf;
 #endif
 
 #ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
@@ -999,8 +1036,6 @@ void __init setup_arch(char **cmdline_p)
 static int __init topology_init(void)
 {
         unsigned int cpu;
-        /* Record CPU-private information for the boot processor. */
-        bfin_setup_cpudata(0);
 
         for_each_possible_cpu(cpu) {
                 register_cpu(&per_cpu(cpu_data, cpu).cpu, cpu);
@@ -1246,12 +1281,14 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                    dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS,
                    BFIN_DLINES);
 #ifdef __ARCH_SYNC_CORE_DCACHE
-        seq_printf(m, "SMP Dcache Flushes\t: %lu\n\n", dcache_invld_count[cpu_num]);
+        seq_printf(m, "dcache flushes\t: %lu\n", dcache_invld_count[cpu_num]);
 #endif
 #ifdef __ARCH_SYNC_CORE_ICACHE
-        seq_printf(m, "SMP Icache Flushes\t: %lu\n\n", icache_invld_count[cpu_num]);
+        seq_printf(m, "icache flushes\t: %lu\n", icache_invld_count[cpu_num]);
 #endif
 
+        seq_printf(m, "\n");
+
         if (cpu_num != num_possible_cpus() - 1)
                 return 0;
 
@@ -1275,13 +1312,11 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                               " in data cache\n");
         }
         seq_printf(m, "board name\t: %s\n", bfin_board_name);
-        seq_printf(m, "board memory\t: %ld kB (0x%p -> 0x%p)\n",
-                 physical_mem_end >> 10, (void *)0, (void *)physical_mem_end);
-        seq_printf(m, "kernel memory\t: %d kB (0x%p -> 0x%p)\n",
+        seq_printf(m, "board memory\t: %ld kB (0x%08lx -> 0x%08lx)\n",
+                physical_mem_end >> 10, 0ul, physical_mem_end);
+        seq_printf(m, "kernel memory\t: %d kB (0x%08lx -> 0x%08lx)\n",
                 ((int)memory_end - (int)_rambase) >> 10,
-                (void *)_rambase,
-                (void *)memory_end);
-        seq_printf(m, "\n");
+                _rambase, memory_end);
 
         return 0;
 }
@@ -1289,7 +1324,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
 static void *c_start(struct seq_file *m, loff_t *pos)
 {
         if (*pos == 0)
-                *pos = first_cpu(cpu_online_map);
+                *pos = cpumask_first(cpu_online_mask);
         if (*pos >= num_online_cpus())
                 return NULL;
 
@@ -1298,7 +1333,7 @@ static void *c_start(struct seq_file *m, loff_t *pos)
 
 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
 {
-        *pos = next_cpu(*pos, cpu_online_map);
+        *pos = cpumask_next(*pos, cpu_online_mask);
 
         return c_start(m, pos);
 }