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-rw-r--r--arch/blackfin/include/asm/bfin_rotary.h74
-rw-r--r--arch/blackfin/include/asm/bfin_sdh.h119
-rw-r--r--arch/blackfin/include/asm/bitops.h2
-rw-r--r--arch/blackfin/include/asm/cdef_LPBlackfin.h8
-rw-r--r--arch/blackfin/include/asm/def_LPBlackfin.h18
-rw-r--r--arch/blackfin/include/asm/dma.h1
-rw-r--r--arch/blackfin/include/asm/elf.h1
-rw-r--r--arch/blackfin/include/asm/ftrace.h16
-rw-r--r--arch/blackfin/include/asm/gpio.h111
-rw-r--r--arch/blackfin/include/asm/io.h8
-rw-r--r--arch/blackfin/include/asm/local64.h1
-rw-r--r--arch/blackfin/include/asm/mem_init.h18
-rw-r--r--arch/blackfin/include/asm/portmux.h10
13 files changed, 302 insertions, 85 deletions
diff --git a/arch/blackfin/include/asm/bfin_rotary.h b/arch/blackfin/include/asm/bfin_rotary.h
index abdb2af52902..0b6910bdc57f 100644
--- a/arch/blackfin/include/asm/bfin_rotary.h
+++ b/arch/blackfin/include/asm/bfin_rotary.h
@@ -2,7 +2,7 @@
2 * board initialization should put one of these structures into platform_data 2 * board initialization should put one of these structures into platform_data
3 * and place the bfin-rotary onto platform_bus named "bfin-rotary". 3 * and place the bfin-rotary onto platform_bus named "bfin-rotary".
4 * 4 *
5 * Copyright 2008 Analog Devices Inc. 5 * Copyright 2008-2010 Analog Devices Inc.
6 * 6 *
7 * Licensed under the GPL-2 or later. 7 * Licensed under the GPL-2 or later.
8 */ 8 */
@@ -40,4 +40,76 @@ struct bfin_rotary_platform_data {
40 unsigned short debounce; /* 0..17 */ 40 unsigned short debounce; /* 0..17 */
41 unsigned short mode; 41 unsigned short mode;
42}; 42};
43
44/* CNT_CONFIG bitmasks */
45#define CNTE (1 << 0) /* Counter Enable */
46#define DEBE (1 << 1) /* Debounce Enable */
47#define CDGINV (1 << 4) /* CDG Pin Polarity Invert */
48#define CUDINV (1 << 5) /* CUD Pin Polarity Invert */
49#define CZMINV (1 << 6) /* CZM Pin Polarity Invert */
50#define CNTMODE_SHIFT 8
51#define CNTMODE (0x7 << CNTMODE_SHIFT) /* Counter Operating Mode */
52#define ZMZC (1 << 1) /* CZM Zeroes Counter Enable */
53#define BNDMODE_SHIFT 12
54#define BNDMODE (0x3 << BNDMODE_SHIFT) /* Boundary register Mode */
55#define INPDIS (1 << 15) /* CUG and CDG Input Disable */
56
57#define CNTMODE_QUADENC (0 << CNTMODE_SHIFT) /* quadrature encoder mode */
58#define CNTMODE_BINENC (1 << CNTMODE_SHIFT) /* binary encoder mode */
59#define CNTMODE_UDCNT (2 << CNTMODE_SHIFT) /* up/down counter mode */
60#define CNTMODE_DIRCNT (4 << CNTMODE_SHIFT) /* direction counter mode */
61#define CNTMODE_DIRTMR (5 << CNTMODE_SHIFT) /* direction timer mode */
62
63#define BNDMODE_COMP (0 << BNDMODE_SHIFT) /* boundary compare mode */
64#define BNDMODE_ZERO (1 << BNDMODE_SHIFT) /* boundary compare and zero mode */
65#define BNDMODE_CAPT (2 << BNDMODE_SHIFT) /* boundary capture mode */
66#define BNDMODE_AEXT (3 << BNDMODE_SHIFT) /* boundary auto-extend mode */
67
68/* CNT_IMASK bitmasks */
69#define ICIE (1 << 0) /* Illegal Gray/Binary Code Interrupt Enable */
70#define UCIE (1 << 1) /* Up count Interrupt Enable */
71#define DCIE (1 << 2) /* Down count Interrupt Enable */
72#define MINCIE (1 << 3) /* Min Count Interrupt Enable */
73#define MAXCIE (1 << 4) /* Max Count Interrupt Enable */
74#define COV31IE (1 << 5) /* Bit 31 Overflow Interrupt Enable */
75#define COV15IE (1 << 6) /* Bit 15 Overflow Interrupt Enable */
76#define CZEROIE (1 << 7) /* Count to Zero Interrupt Enable */
77#define CZMIE (1 << 8) /* CZM Pin Interrupt Enable */
78#define CZMEIE (1 << 9) /* CZM Error Interrupt Enable */
79#define CZMZIE (1 << 10) /* CZM Zeroes Counter Interrupt Enable */
80
81/* CNT_STATUS bitmasks */
82#define ICII (1 << 0) /* Illegal Gray/Binary Code Interrupt Identifier */
83#define UCII (1 << 1) /* Up count Interrupt Identifier */
84#define DCII (1 << 2) /* Down count Interrupt Identifier */
85#define MINCII (1 << 3) /* Min Count Interrupt Identifier */
86#define MAXCII (1 << 4) /* Max Count Interrupt Identifier */
87#define COV31II (1 << 5) /* Bit 31 Overflow Interrupt Identifier */
88#define COV15II (1 << 6) /* Bit 15 Overflow Interrupt Identifier */
89#define CZEROII (1 << 7) /* Count to Zero Interrupt Identifier */
90#define CZMII (1 << 8) /* CZM Pin Interrupt Identifier */
91#define CZMEII (1 << 9) /* CZM Error Interrupt Identifier */
92#define CZMZII (1 << 10) /* CZM Zeroes Counter Interrupt Identifier */
93
94/* CNT_COMMAND bitmasks */
95#define W1LCNT 0xf /* Load Counter Register */
96#define W1LMIN 0xf0 /* Load Min Register */
97#define W1LMAX 0xf00 /* Load Max Register */
98#define W1ZMONCE (1 << 12) /* Enable CZM Clear Counter Once */
99
100#define W1LCNT_ZERO (1 << 0) /* write 1 to load CNT_COUNTER with zero */
101#define W1LCNT_MIN (1 << 2) /* write 1 to load CNT_COUNTER from CNT_MIN */
102#define W1LCNT_MAX (1 << 3) /* write 1 to load CNT_COUNTER from CNT_MAX */
103
104#define W1LMIN_ZERO (1 << 4) /* write 1 to load CNT_MIN with zero */
105#define W1LMIN_CNT (1 << 5) /* write 1 to load CNT_MIN from CNT_COUNTER */
106#define W1LMIN_MAX (1 << 7) /* write 1 to load CNT_MIN from CNT_MAX */
107
108#define W1LMAX_ZERO (1 << 8) /* write 1 to load CNT_MAX with zero */
109#define W1LMAX_CNT (1 << 9) /* write 1 to load CNT_MAX from CNT_COUNTER */
110#define W1LMAX_MIN (1 << 10) /* write 1 to load CNT_MAX from CNT_MIN */
111
112/* CNT_DEBOUNCE bitmasks */
113#define DPRESCALE 0xf /* Load Counter Register */
114
43#endif 115#endif
diff --git a/arch/blackfin/include/asm/bfin_sdh.h b/arch/blackfin/include/asm/bfin_sdh.h
index d61d5497c590..6a4cfe2d3367 100644
--- a/arch/blackfin/include/asm/bfin_sdh.h
+++ b/arch/blackfin/include/asm/bfin_sdh.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * bfin_sdh.h - Blackfin SDH definitions 2 * Blackfin Secure Digital Host (SDH) definitions
3 * 3 *
4 * Copyright 2008 Analog Devices Inc. 4 * Copyright 2008-2010 Analog Devices Inc.
5 * 5 *
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
@@ -9,6 +9,7 @@
9#ifndef __BFIN_SDH_H__ 9#ifndef __BFIN_SDH_H__
10#define __BFIN_SDH_H__ 10#define __BFIN_SDH_H__
11 11
12/* Platform resources */
12struct bfin_sd_host { 13struct bfin_sd_host {
13 int dma_chan; 14 int dma_chan;
14 int irq_int0; 15 int irq_int0;
@@ -16,4 +17,118 @@ struct bfin_sd_host {
16 u16 pin_req[7]; 17 u16 pin_req[7];
17}; 18};
18 19
20/* SDH_COMMAND bitmasks */
21#define CMD_IDX 0x3f /* Command Index */
22#define CMD_RSP (1 << 6) /* Response */
23#define CMD_L_RSP (1 << 7) /* Long Response */
24#define CMD_INT_E (1 << 8) /* Command Interrupt */
25#define CMD_PEND_E (1 << 9) /* Command Pending */
26#define CMD_E (1 << 10) /* Command Enable */
27
28/* SDH_PWR_CTL bitmasks */
29#define PWR_ON 0x3 /* Power On */
30#define SD_CMD_OD (1 << 6) /* Open Drain Output */
31#define ROD_CTL (1 << 7) /* Rod Control */
32
33/* SDH_CLK_CTL bitmasks */
34#define CLKDIV 0xff /* MC_CLK Divisor */
35#define CLK_E (1 << 8) /* MC_CLK Bus Clock Enable */
36#define PWR_SV_E (1 << 9) /* Power Save Enable */
37#define CLKDIV_BYPASS (1 << 10) /* Bypass Divisor */
38#define WIDE_BUS (1 << 11) /* Wide Bus Mode Enable */
39
40/* SDH_RESP_CMD bitmasks */
41#define RESP_CMD 0x3f /* Response Command */
42
43/* SDH_DATA_CTL bitmasks */
44#define DTX_E (1 << 0) /* Data Transfer Enable */
45#define DTX_DIR (1 << 1) /* Data Transfer Direction */
46#define DTX_MODE (1 << 2) /* Data Transfer Mode */
47#define DTX_DMA_E (1 << 3) /* Data Transfer DMA Enable */
48#define DTX_BLK_LGTH (0xf << 4) /* Data Transfer Block Length */
49
50/* SDH_STATUS bitmasks */
51#define CMD_CRC_FAIL (1 << 0) /* CMD CRC Fail */
52#define DAT_CRC_FAIL (1 << 1) /* Data CRC Fail */
53#define CMD_TIME_OUT (1 << 2) /* CMD Time Out */
54#define DAT_TIME_OUT (1 << 3) /* Data Time Out */
55#define TX_UNDERRUN (1 << 4) /* Transmit Underrun */
56#define RX_OVERRUN (1 << 5) /* Receive Overrun */
57#define CMD_RESP_END (1 << 6) /* CMD Response End */
58#define CMD_SENT (1 << 7) /* CMD Sent */
59#define DAT_END (1 << 8) /* Data End */
60#define START_BIT_ERR (1 << 9) /* Start Bit Error */
61#define DAT_BLK_END (1 << 10) /* Data Block End */
62#define CMD_ACT (1 << 11) /* CMD Active */
63#define TX_ACT (1 << 12) /* Transmit Active */
64#define RX_ACT (1 << 13) /* Receive Active */
65#define TX_FIFO_STAT (1 << 14) /* Transmit FIFO Status */
66#define RX_FIFO_STAT (1 << 15) /* Receive FIFO Status */
67#define TX_FIFO_FULL (1 << 16) /* Transmit FIFO Full */
68#define RX_FIFO_FULL (1 << 17) /* Receive FIFO Full */
69#define TX_FIFO_ZERO (1 << 18) /* Transmit FIFO Empty */
70#define RX_DAT_ZERO (1 << 19) /* Receive FIFO Empty */
71#define TX_DAT_RDY (1 << 20) /* Transmit Data Available */
72#define RX_FIFO_RDY (1 << 21) /* Receive Data Available */
73
74/* SDH_STATUS_CLR bitmasks */
75#define CMD_CRC_FAIL_STAT (1 << 0) /* CMD CRC Fail Status */
76#define DAT_CRC_FAIL_STAT (1 << 1) /* Data CRC Fail Status */
77#define CMD_TIMEOUT_STAT (1 << 2) /* CMD Time Out Status */
78#define DAT_TIMEOUT_STAT (1 << 3) /* Data Time Out status */
79#define TX_UNDERRUN_STAT (1 << 4) /* Transmit Underrun Status */
80#define RX_OVERRUN_STAT (1 << 5) /* Receive Overrun Status */
81#define CMD_RESP_END_STAT (1 << 6) /* CMD Response End Status */
82#define CMD_SENT_STAT (1 << 7) /* CMD Sent Status */
83#define DAT_END_STAT (1 << 8) /* Data End Status */
84#define START_BIT_ERR_STAT (1 << 9) /* Start Bit Error Status */
85#define DAT_BLK_END_STAT (1 << 10) /* Data Block End Status */
86
87/* SDH_MASK0 bitmasks */
88#define CMD_CRC_FAIL_MASK (1 << 0) /* CMD CRC Fail Mask */
89#define DAT_CRC_FAIL_MASK (1 << 1) /* Data CRC Fail Mask */
90#define CMD_TIMEOUT_MASK (1 << 2) /* CMD Time Out Mask */
91#define DAT_TIMEOUT_MASK (1 << 3) /* Data Time Out Mask */
92#define TX_UNDERRUN_MASK (1 << 4) /* Transmit Underrun Mask */
93#define RX_OVERRUN_MASK (1 << 5) /* Receive Overrun Mask */
94#define CMD_RESP_END_MASK (1 << 6) /* CMD Response End Mask */
95#define CMD_SENT_MASK (1 << 7) /* CMD Sent Mask */
96#define DAT_END_MASK (1 << 8) /* Data End Mask */
97#define START_BIT_ERR_MASK (1 << 9) /* Start Bit Error Mask */
98#define DAT_BLK_END_MASK (1 << 10) /* Data Block End Mask */
99#define CMD_ACT_MASK (1 << 11) /* CMD Active Mask */
100#define TX_ACT_MASK (1 << 12) /* Transmit Active Mask */
101#define RX_ACT_MASK (1 << 13) /* Receive Active Mask */
102#define TX_FIFO_STAT_MASK (1 << 14) /* Transmit FIFO Status Mask */
103#define RX_FIFO_STAT_MASK (1 << 15) /* Receive FIFO Status Mask */
104#define TX_FIFO_FULL_MASK (1 << 16) /* Transmit FIFO Full Mask */
105#define RX_FIFO_FULL_MASK (1 << 17) /* Receive FIFO Full Mask */
106#define TX_FIFO_ZERO_MASK (1 << 18) /* Transmit FIFO Empty Mask */
107#define RX_DAT_ZERO_MASK (1 << 19) /* Receive FIFO Empty Mask */
108#define TX_DAT_RDY_MASK (1 << 20) /* Transmit Data Available Mask */
109#define RX_FIFO_RDY_MASK (1 << 21) /* Receive Data Available Mask */
110
111/* SDH_FIFO_CNT bitmasks */
112#define FIFO_COUNT 0x7fff /* FIFO Count */
113
114/* SDH_E_STATUS bitmasks */
115#define SDIO_INT_DET (1 << 1) /* SDIO Int Detected */
116#define SD_CARD_DET (1 << 4) /* SD Card Detect */
117
118/* SDH_E_MASK bitmasks */
119#define SDIO_MSK (1 << 1) /* Mask SDIO Int Detected */
120#define SCD_MSK (1 << 6) /* Mask Card Detect */
121
122/* SDH_CFG bitmasks */
123#define CLKS_EN (1 << 0) /* Clocks Enable */
124#define SD4E (1 << 2) /* SDIO 4-Bit Enable */
125#define MWE (1 << 3) /* Moving Window Enable */
126#define SD_RST (1 << 4) /* SDMMC Reset */
127#define PUP_SDDAT (1 << 5) /* Pull-up SD_DAT */
128#define PUP_SDDAT3 (1 << 6) /* Pull-up SD_DAT3 */
129#define PD_SDDAT3 (1 << 7) /* Pull-down SD_DAT3 */
130
131/* SDH_RD_WAIT_EN bitmasks */
132#define RWR (1 << 0) /* Read Wait Request */
133
19#endif 134#endif
diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h
index 605ba8e9b2e4..d5872cd967ab 100644
--- a/arch/blackfin/include/asm/bitops.h
+++ b/arch/blackfin/include/asm/bitops.h
@@ -119,7 +119,7 @@ static inline unsigned int hweight32(unsigned int w)
119{ 119{
120 unsigned int res; 120 unsigned int res;
121 121
122 __asm__ ("%0.l = ONES %0;" 122 __asm__ ("%0.l = ONES %1;"
123 "%0 = %0.l (Z);" 123 "%0 = %0.l (Z);"
124 : "=d" (res) : "d" (w)); 124 : "=d" (res) : "d" (w));
125 return res; 125 return res;
diff --git a/arch/blackfin/include/asm/cdef_LPBlackfin.h b/arch/blackfin/include/asm/cdef_LPBlackfin.h
index 8778e0f03730..6c39d94b44d0 100644
--- a/arch/blackfin/include/asm/cdef_LPBlackfin.h
+++ b/arch/blackfin/include/asm/cdef_LPBlackfin.h
@@ -216,12 +216,16 @@
216#define bfin_write_EVT14(val) bfin_write32(EVT14,val) 216#define bfin_write_EVT14(val) bfin_write32(EVT14,val)
217#define bfin_read_EVT15() bfin_read32(EVT15) 217#define bfin_read_EVT15() bfin_read32(EVT15)
218#define bfin_write_EVT15(val) bfin_write32(EVT15,val) 218#define bfin_write_EVT15(val) bfin_write32(EVT15,val)
219#define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE)
220#define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE,val)
219#define bfin_read_IMASK() bfin_read32(IMASK) 221#define bfin_read_IMASK() bfin_read32(IMASK)
220#define bfin_write_IMASK(val) bfin_write32(IMASK,val) 222#define bfin_write_IMASK(val) bfin_write32(IMASK,val)
221#define bfin_read_IPEND() bfin_read32(IPEND) 223#define bfin_read_IPEND() bfin_read32(IPEND)
222#define bfin_write_IPEND(val) bfin_write32(IPEND,val) 224#define bfin_write_IPEND(val) bfin_write32(IPEND,val)
223#define bfin_read_ILAT() bfin_read32(ILAT) 225#define bfin_read_ILAT() bfin_read32(ILAT)
224#define bfin_write_ILAT(val) bfin_write32(ILAT,val) 226#define bfin_write_ILAT(val) bfin_write32(ILAT,val)
227#define bfin_read_IPRIO() bfin_read32(IPRIO)
228#define bfin_write_IPRIO(val) bfin_write32(IPRIO,val)
225 229
226/*Core Timer Registers*/ 230/*Core Timer Registers*/
227#define bfin_read_TCNTL() bfin_read32(TCNTL) 231#define bfin_read_TCNTL() bfin_read32(TCNTL)
@@ -299,8 +303,4 @@
299#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1) 303#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1)
300#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1,val) 304#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1,val)
301 305
302/*
303#define IPRIO 0xFFE02110
304*/
305
306#endif /* _CDEF_LPBLACKFIN_H */ 306#endif /* _CDEF_LPBLACKFIN_H */
diff --git a/arch/blackfin/include/asm/def_LPBlackfin.h b/arch/blackfin/include/asm/def_LPBlackfin.h
index f342ff0319df..e3f0f4c49819 100644
--- a/arch/blackfin/include/asm/def_LPBlackfin.h
+++ b/arch/blackfin/include/asm/def_LPBlackfin.h
@@ -50,6 +50,23 @@
50#define bfin_write16(addr, val) _bfin_writeX(addr, val, 16, w) 50#define bfin_write16(addr, val) _bfin_writeX(addr, val, 16, w)
51#define bfin_write32(addr, val) _bfin_writeX(addr, val, 32, ) 51#define bfin_write32(addr, val) _bfin_writeX(addr, val, 32, )
52 52
53#define bfin_read(addr) \
54({ \
55 sizeof(*(addr)) == 1 ? bfin_read8(addr) : \
56 sizeof(*(addr)) == 2 ? bfin_read16(addr) : \
57 sizeof(*(addr)) == 4 ? bfin_read32(addr) : \
58 ({ BUG(); 0; }); \
59})
60#define bfin_write(addr, val) \
61({ \
62 switch (sizeof(*(addr))) { \
63 case 1: bfin_write8(addr, val); break; \
64 case 2: bfin_write16(addr, val); break; \
65 case 4: bfin_write32(addr, val); break; \
66 default: BUG(); \
67 } \
68})
69
53#endif /* __ASSEMBLY__ */ 70#endif /* __ASSEMBLY__ */
54 71
55/************************************************** 72/**************************************************
@@ -377,6 +394,7 @@
377#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ 394#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
378#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ 395#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
379#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ 396#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
397#define EVT_OVERRIDE 0xFFE02100 /* Event Vector Override Register */
380#define IMASK 0xFFE02104 /* Interrupt Mask Register */ 398#define IMASK 0xFFE02104 /* Interrupt Mask Register */
381#define IPEND 0xFFE02108 /* Interrupt Pending Register */ 399#define IPEND 0xFFE02108 /* Interrupt Pending Register */
382#define ILAT 0xFFE0210C /* Interrupt Latch Register */ 400#define ILAT 0xFFE0210C /* Interrupt Latch Register */
diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h
index 2c09b1d50ec9..eedf3ca65ba2 100644
--- a/arch/blackfin/include/asm/dma.h
+++ b/arch/blackfin/include/asm/dma.h
@@ -276,6 +276,7 @@ static inline void clear_dma_irqstat(unsigned int channel)
276} 276}
277 277
278void *dma_memcpy(void *dest, const void *src, size_t count); 278void *dma_memcpy(void *dest, const void *src, size_t count);
279void *dma_memcpy_nocache(void *dest, const void *src, size_t count);
279void *safe_dma_memcpy(void *dest, const void *src, size_t count); 280void *safe_dma_memcpy(void *dest, const void *src, size_t count);
280void blackfin_dma_early_init(void); 281void blackfin_dma_early_init(void);
281void early_dma_memcpy(void *dest, const void *src, size_t count); 282void early_dma_memcpy(void *dest, const void *src, size_t count);
diff --git a/arch/blackfin/include/asm/elf.h b/arch/blackfin/include/asm/elf.h
index 117713adea7f..e6c6812a9abd 100644
--- a/arch/blackfin/include/asm/elf.h
+++ b/arch/blackfin/include/asm/elf.h
@@ -119,6 +119,7 @@ do { \
119#define ELF_CORE_COPY_REGS(pr_reg, regs) \ 119#define ELF_CORE_COPY_REGS(pr_reg, regs) \
120 memcpy((char *) &pr_reg, (char *)regs, \ 120 memcpy((char *) &pr_reg, (char *)regs, \
121 sizeof(struct pt_regs)); 121 sizeof(struct pt_regs));
122#define ELF_CORE_COPY_FPREGS(...) 0 /* Blackfin has no FPU */
122 123
123/* This yields a mask that user programs can use to figure out what 124/* This yields a mask that user programs can use to figure out what
124 instruction set this cpu supports. */ 125 instruction set this cpu supports. */
diff --git a/arch/blackfin/include/asm/ftrace.h b/arch/blackfin/include/asm/ftrace.h
index 4cfe2d9ba7e8..8a029505d7b7 100644
--- a/arch/blackfin/include/asm/ftrace.h
+++ b/arch/blackfin/include/asm/ftrace.h
@@ -12,6 +12,22 @@
12 12
13#ifndef __ASSEMBLY__ 13#ifndef __ASSEMBLY__
14 14
15#ifdef CONFIG_DYNAMIC_FTRACE
16
17extern void _mcount(void);
18#define MCOUNT_ADDR ((unsigned long)_mcount)
19
20static inline unsigned long ftrace_call_adjust(unsigned long addr)
21{
22 return addr;
23}
24
25struct dyn_arch_ftrace {
26 /* No extra data needed for Blackfin */
27};
28
29#endif
30
15#ifdef CONFIG_FRAME_POINTER 31#ifdef CONFIG_FRAME_POINTER
16#include <linux/mm.h> 32#include <linux/mm.h>
17 33
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
index 01b19d0cf509..1ef8417f5d27 100644
--- a/arch/blackfin/include/asm/gpio.h
+++ b/arch/blackfin/include/asm/gpio.h
@@ -7,63 +7,63 @@
7#ifndef __ARCH_BLACKFIN_GPIO_H__ 7#ifndef __ARCH_BLACKFIN_GPIO_H__
8#define __ARCH_BLACKFIN_GPIO_H__ 8#define __ARCH_BLACKFIN_GPIO_H__
9 9
10#define gpio_bank(x) ((x) >> 4) 10#define gpio_bank(x) ((x) >> 4)
11#define gpio_bit(x) (1<<((x) & 0xF)) 11#define gpio_bit(x) (1<<((x) & 0xF))
12#define gpio_sub_n(x) ((x) & 0xF) 12#define gpio_sub_n(x) ((x) & 0xF)
13 13
14#define GPIO_BANKSIZE 16 14#define GPIO_BANKSIZE 16
15#define GPIO_BANK_NUM DIV_ROUND_UP(MAX_BLACKFIN_GPIOS, GPIO_BANKSIZE) 15#define GPIO_BANK_NUM DIV_ROUND_UP(MAX_BLACKFIN_GPIOS, GPIO_BANKSIZE)
16 16
17#include <mach/gpio.h> 17#include <mach/gpio.h>
18 18
19#define GPIO_0 0 19#define GPIO_0 0
20#define GPIO_1 1 20#define GPIO_1 1
21#define GPIO_2 2 21#define GPIO_2 2
22#define GPIO_3 3 22#define GPIO_3 3
23#define GPIO_4 4 23#define GPIO_4 4
24#define GPIO_5 5 24#define GPIO_5 5
25#define GPIO_6 6 25#define GPIO_6 6
26#define GPIO_7 7 26#define GPIO_7 7
27#define GPIO_8 8 27#define GPIO_8 8
28#define GPIO_9 9 28#define GPIO_9 9
29#define GPIO_10 10 29#define GPIO_10 10
30#define GPIO_11 11 30#define GPIO_11 11
31#define GPIO_12 12 31#define GPIO_12 12
32#define GPIO_13 13 32#define GPIO_13 13
33#define GPIO_14 14 33#define GPIO_14 14
34#define GPIO_15 15 34#define GPIO_15 15
35#define GPIO_16 16 35#define GPIO_16 16
36#define GPIO_17 17 36#define GPIO_17 17
37#define GPIO_18 18 37#define GPIO_18 18
38#define GPIO_19 19 38#define GPIO_19 19
39#define GPIO_20 20 39#define GPIO_20 20
40#define GPIO_21 21 40#define GPIO_21 21
41#define GPIO_22 22 41#define GPIO_22 22
42#define GPIO_23 23 42#define GPIO_23 23
43#define GPIO_24 24 43#define GPIO_24 24
44#define GPIO_25 25 44#define GPIO_25 25
45#define GPIO_26 26 45#define GPIO_26 26
46#define GPIO_27 27 46#define GPIO_27 27
47#define GPIO_28 28 47#define GPIO_28 28
48#define GPIO_29 29 48#define GPIO_29 29
49#define GPIO_30 30 49#define GPIO_30 30
50#define GPIO_31 31 50#define GPIO_31 31
51#define GPIO_32 32 51#define GPIO_32 32
52#define GPIO_33 33 52#define GPIO_33 33
53#define GPIO_34 34 53#define GPIO_34 34
54#define GPIO_35 35 54#define GPIO_35 35
55#define GPIO_36 36 55#define GPIO_36 36
56#define GPIO_37 37 56#define GPIO_37 37
57#define GPIO_38 38 57#define GPIO_38 38
58#define GPIO_39 39 58#define GPIO_39 39
59#define GPIO_40 40 59#define GPIO_40 40
60#define GPIO_41 41 60#define GPIO_41 41
61#define GPIO_42 42 61#define GPIO_42 42
62#define GPIO_43 43 62#define GPIO_43 43
63#define GPIO_44 44 63#define GPIO_44 44
64#define GPIO_45 45 64#define GPIO_45 45
65#define GPIO_46 46 65#define GPIO_46 46
66#define GPIO_47 47 66#define GPIO_47 47
67 67
68#define PERIPHERAL_USAGE 1 68#define PERIPHERAL_USAGE 1
69#define GPIO_USAGE 0 69#define GPIO_USAGE 0
@@ -279,6 +279,11 @@ static inline int gpio_direction_output(unsigned gpio, int value)
279 return bfin_gpio_direction_output(gpio, value); 279 return bfin_gpio_direction_output(gpio, value);
280} 280}
281 281
282static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
283{
284 return -EINVAL;
285}
286
282static inline int gpio_get_value(unsigned gpio) 287static inline int gpio_get_value(unsigned gpio)
283{ 288{
284 return bfin_gpio_get_value(gpio); 289 return bfin_gpio_get_value(gpio);
diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h
index 29e55b9d88bc..234fbac17ec1 100644
--- a/arch/blackfin/include/asm/io.h
+++ b/arch/blackfin/include/asm/io.h
@@ -124,7 +124,13 @@ static inline unsigned int readl(const volatile void __iomem *addr)
124#define iowrite16(val, x) writew(val, x) 124#define iowrite16(val, x) writew(val, x)
125#define iowrite32(val, x) writel(val, x) 125#define iowrite32(val, x) writel(val, x)
126 126
127#define mmiowb() wmb() 127/**
128 * I/O write barrier
129 *
130 * Ensure ordering of I/O space writes. This will make sure that writes
131 * following the barrier will arrive after all previous writes.
132 */
133#define mmiowb() do { SSYNC(); wmb(); } while (0)
128 134
129#define IO_SPACE_LIMIT 0xffffffff 135#define IO_SPACE_LIMIT 0xffffffff
130 136
diff --git a/arch/blackfin/include/asm/local64.h b/arch/blackfin/include/asm/local64.h
new file mode 100644
index 000000000000..36c93b5cc239
--- /dev/null
+++ b/arch/blackfin/include/asm/local64.h
@@ -0,0 +1 @@
#include <asm-generic/local64.h>
diff --git a/arch/blackfin/include/asm/mem_init.h b/arch/blackfin/include/asm/mem_init.h
index 7c8fe834ff22..237579935e29 100644
--- a/arch/blackfin/include/asm/mem_init.h
+++ b/arch/blackfin/include/asm/mem_init.h
@@ -10,7 +10,6 @@
10#if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \ 10#if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
11 defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \ 11 defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
12 defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \ 12 defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
13 defined(CONFIG_MEM_GENERIC_BOARD) || \
14 defined(CONFIG_MEM_MT48LC32M8A2_75) || \ 13 defined(CONFIG_MEM_MT48LC32M8A2_75) || \
15 defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \ 14 defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \
16 defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \ 15 defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
@@ -178,7 +177,6 @@
178 177
179#if defined(CONFIG_MEM_MT48LC32M8A2_75) || \ 178#if defined(CONFIG_MEM_MT48LC32M8A2_75) || \
180 defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \ 179 defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
181 defined(CONFIG_MEM_GENERIC_BOARD) || \
182 defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \ 180 defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
183 defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \ 181 defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
184 defined(CONFIG_MEM_MT48LC32M8A2_75) 182 defined(CONFIG_MEM_MT48LC32M8A2_75)
@@ -248,22 +246,6 @@
248#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15)) 246#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
249#endif 247#endif
250 248
251#if defined(CONFIG_MEM_GENERIC_BOARD)
252#define DDR_SIZE DEVSZ_512
253#define DDR_WIDTH DEVWD_16
254#define DDR_MAX_tCK 13
255
256#define DDR_tRCD DDR_TRCD(3)
257#define DDR_tWTR DDR_TWTR(2)
258#define DDR_tWR DDR_TWR(2)
259#define DDR_tMRD DDR_TMRD(2)
260#define DDR_tRP DDR_TRP(3)
261#define DDR_tRAS DDR_TRAS(7)
262#define DDR_tRC DDR_TRC(10)
263#define DDR_tRFC DDR_TRFC(12)
264#define DDR_tREFI DDR_TREFI(1288)
265#endif
266
267#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK)) 249#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
268# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)." 250# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
269#elif(CONFIG_SCLK_HZ <= 133333333) 251#elif(CONFIG_SCLK_HZ <= 133333333)
diff --git a/arch/blackfin/include/asm/portmux.h b/arch/blackfin/include/asm/portmux.h
index edd8ef3a3788..9b1e2c37b324 100644
--- a/arch/blackfin/include/asm/portmux.h
+++ b/arch/blackfin/include/asm/portmux.h
@@ -1,9 +1,9 @@
1/* 1/*
2 * Common header file for Blackfin family of processors 2 * Common header file for Blackfin family of processors
3 * 3 *
4 * Copyright 2007-2008 Analog Devices Inc. 4 * Copyright 2007-2008 Analog Devices Inc.
5 * 5 *
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
9#ifndef _PORTMUX_H_ 9#ifndef _PORTMUX_H_
@@ -1042,8 +1042,8 @@ void peripheral_free_list(const unsigned short per[]);
1042#define P_NOR_CLK P_UNDEF 1042#define P_NOR_CLK P_UNDEF
1043#endif 1043#endif
1044 1044
1045#ifndef P_TMRCLK 1045#ifndef P_TMRCLK
1046#define P_TMRCLK P_UNDEF 1046#define P_TMRCLK P_UNDEF
1047#endif 1047#endif
1048 1048
1049#ifndef P_AMC_ARDY_NOR_WAIT 1049#ifndef P_AMC_ARDY_NOR_WAIT
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-30 00:19:12 -0400