47 files changed, 1764 insertions, 792 deletions

diff --git a/arch/blackfin/include/asm/asm-offsets.h b/arch/blackfin/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/blackfin/include/asm/asm-offsets.h
@@ -0,0 +1 @@
+#include <generated/asm-offsets.h>
diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h
index 10064f902d20..e6485c305ea6 100644
--- a/arch/blackfin/include/asm/bfin-global.h
+++ b/arch/blackfin/include/asm/bfin-global.h
@@ -11,9 +11,6 @@
 
 #ifndef __ASSEMBLY__
 
-#include <asm/sections.h>
-#include <asm/ptrace.h>
-#include <asm/user.h>
 #include <linux/linkage.h>
 #include <linux/types.h>
 
@@ -23,6 +20,12 @@
 # define DMA_UNCACHED_REGION (2 * 1024 * 1024)
 #elif defined(CONFIG_DMA_UNCACHED_1M)
 # define DMA_UNCACHED_REGION (1024 * 1024)
+#elif defined(CONFIG_DMA_UNCACHED_512K)
+# define DMA_UNCACHED_REGION (512 * 1024)
+#elif defined(CONFIG_DMA_UNCACHED_256K)
+# define DMA_UNCACHED_REGION (256 * 1024)
+#elif defined(CONFIG_DMA_UNCACHED_128K)
+# define DMA_UNCACHED_REGION (128 * 1024)
 #else
 # define DMA_UNCACHED_REGION (0)
 #endif
@@ -35,6 +38,7 @@ extern unsigned long get_sclk(void);
 extern unsigned long sclk_to_usecs(unsigned long sclk);
 extern unsigned long usecs_to_sclk(unsigned long usecs);
 
+struct pt_regs;
 extern void dump_bfin_process(struct pt_regs *regs);
 extern void dump_bfin_mem(struct pt_regs *regs);
 extern void dump_bfin_trace_buffer(void);
diff --git a/arch/blackfin/include/asm/bfin-lq035q1.h b/arch/blackfin/include/asm/bfin-lq035q1.h
new file mode 100644
index 000000000000..836895156b5b
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin-lq035q1.h
@@ -0,0 +1,40 @@
+/*
+ * Blackfin LCD Framebuffer driver SHARP LQ035Q1DH02
+ *
+ * Copyright 2008-2009 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef BFIN_LQ035Q1_H
+#define BFIN_LQ035Q1_H
+
+/*
+ * LCD Modes
+ */
+#define LQ035_RL        (0 << 8)        /* Right -> Left Scan */
+#define LQ035_LR        (1 << 8)        /* Left -> Right Scan */
+#define LQ035_TB        (1 << 9)        /* Top -> Botton Scan */
+#define LQ035_BT        (0 << 9)        /* Botton -> Top Scan */
+#define LQ035_BGR       (1 << 11)       /* Use BGR format */
+#define LQ035_RGB       (0 << 11)       /* Use RGB format */
+#define LQ035_NORM      (1 << 13)       /* Reversal */
+#define LQ035_REV       (0 << 13)       /* Reversal */
+
+/*
+ * PPI Modes
+ */
+
+#define USE_RGB565_16_BIT_PPI   1
+#define USE_RGB565_8_BIT_PPI    2
+#define USE_RGB888_8_BIT_PPI    3
+
+struct bfin_lq035q1fb_disp_info {
+
+        unsigned        mode;
+        unsigned        ppi_mode;
+        /* GPIOs */
+        int             use_bl;
+        unsigned        gpio_bl;
+};
+
+#endif /* BFIN_LQ035Q1_H */
diff --git a/arch/blackfin/include/asm/bfin_can.h b/arch/blackfin/include/asm/bfin_can.h
new file mode 100644
index 000000000000..eec0076a385b
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_can.h
@@ -0,0 +1,725 @@
+/*
+ * bfin_can.h - interface to Blackfin CANs
+ *
+ * Copyright 2004-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __ASM_BFIN_CAN_H__
+#define __ASM_BFIN_CAN_H__
+
+/*
+ * transmit and receive channels
+ */
+#define TRANSMIT_CHL            24
+#define RECEIVE_STD_CHL         0
+#define RECEIVE_EXT_CHL         4
+#define RECEIVE_RTR_CHL         8
+#define RECEIVE_EXT_RTR_CHL     12
+#define MAX_CHL_NUMBER          32
+
+/*
+ * All Blackfin system MMRs are padded to 32bits even if the register
+ * itself is only 16bits.  So use a helper macro to streamline this.
+ */
+#define __BFP(m) u16 m; u16 __pad_##m
+
+/*
+ * bfin can registers layout
+ */
+struct bfin_can_mask_regs {
+        __BFP(aml);
+        __BFP(amh);
+};
+
+struct bfin_can_channel_regs {
+        u16 data[8];
+        __BFP(dlc);
+        __BFP(tsv);
+        __BFP(id0);
+        __BFP(id1);
+};
+
+struct bfin_can_regs {
+        /*
+         * global control and status registers
+         */
+        __BFP(mc1);           /* offset 0x00 */
+        __BFP(md1);           /* offset 0x04 */
+        __BFP(trs1);          /* offset 0x08 */
+        __BFP(trr1);          /* offset 0x0c */
+        __BFP(ta1);           /* offset 0x10 */
+        __BFP(aa1);           /* offset 0x14 */
+        __BFP(rmp1);          /* offset 0x18 */
+        __BFP(rml1);          /* offset 0x1c */
+        __BFP(mbtif1);        /* offset 0x20 */
+        __BFP(mbrif1);        /* offset 0x24 */
+        __BFP(mbim1);         /* offset 0x28 */
+        __BFP(rfh1);          /* offset 0x2c */
+        __BFP(opss1);         /* offset 0x30 */
+        u32 __pad1[3];
+        __BFP(mc2);           /* offset 0x40 */
+        __BFP(md2);           /* offset 0x44 */
+        __BFP(trs2);          /* offset 0x48 */
+        __BFP(trr2);          /* offset 0x4c */
+        __BFP(ta2);           /* offset 0x50 */
+        __BFP(aa2);           /* offset 0x54 */
+        __BFP(rmp2);          /* offset 0x58 */
+        __BFP(rml2);          /* offset 0x5c */
+        __BFP(mbtif2);        /* offset 0x60 */
+        __BFP(mbrif2);        /* offset 0x64 */
+        __BFP(mbim2);         /* offset 0x68 */
+        __BFP(rfh2);          /* offset 0x6c */
+        __BFP(opss2);         /* offset 0x70 */
+        u32 __pad2[3];
+        __BFP(clock);         /* offset 0x80 */
+        __BFP(timing);        /* offset 0x84 */
+        __BFP(debug);         /* offset 0x88 */
+        __BFP(status);        /* offset 0x8c */
+        __BFP(cec);           /* offset 0x90 */
+        __BFP(gis);           /* offset 0x94 */
+        __BFP(gim);           /* offset 0x98 */
+        __BFP(gif);           /* offset 0x9c */
+        __BFP(control);       /* offset 0xa0 */
+        __BFP(intr);          /* offset 0xa4 */
+        u32 __pad3[1];
+        __BFP(mbtd);          /* offset 0xac */
+        __BFP(ewr);           /* offset 0xb0 */
+        __BFP(esr);           /* offset 0xb4 */
+        u32 __pad4[2];
+        __BFP(ucreg);         /* offset 0xc0 */
+        __BFP(uccnt);         /* offset 0xc4 */
+        __BFP(ucrc);          /* offset 0xc8 */
+        __BFP(uccnf);         /* offset 0xcc */
+        u32 __pad5[12];
+
+        /*
+         * channel(mailbox) mask and message registers
+         */
+        struct bfin_can_mask_regs msk[MAX_CHL_NUMBER];    /* offset 0x100 */
+        struct bfin_can_channel_regs chl[MAX_CHL_NUMBER]; /* offset 0x200 */
+};
+
+#undef __BFP
+
+/* CAN_CONTROL Masks */
+#define SRS                     0x0001  /* Software Reset */
+#define DNM                     0x0002  /* Device Net Mode */
+#define ABO                     0x0004  /* Auto-Bus On Enable */
+#define TXPRIO          0x0008  /* TX Priority (Priority/Mailbox*) */
+#define WBA                     0x0010  /* Wake-Up On CAN Bus Activity Enable */
+#define SMR                     0x0020  /* Sleep Mode Request */
+#define CSR                     0x0040  /* CAN Suspend Mode Request */
+#define CCR                     0x0080  /* CAN Configuration Mode Request */
+
+/* CAN_STATUS Masks */
+#define WT                      0x0001  /* TX Warning Flag */
+#define WR                      0x0002  /* RX Warning Flag */
+#define EP                      0x0004  /* Error Passive Mode */
+#define EBO                     0x0008  /* Error Bus Off Mode */
+#define SMA                     0x0020  /* Sleep Mode Acknowledge */
+#define CSA                     0x0040  /* Suspend Mode Acknowledge */
+#define CCA                     0x0080  /* Configuration Mode Acknowledge */
+#define MBPTR           0x1F00  /* Mailbox Pointer */
+#define TRM                     0x4000  /* Transmit Mode */
+#define REC                     0x8000  /* Receive Mode */
+
+/* CAN_CLOCK Masks */
+#define BRP                     0x03FF  /* Bit-Rate Pre-Scaler */
+
+/* CAN_TIMING Masks */
+#define TSEG1           0x000F  /* Time Segment 1 */
+#define TSEG2           0x0070  /* Time Segment 2 */
+#define SAM                     0x0080  /* Sampling */
+#define SJW                     0x0300  /* Synchronization Jump Width */
+
+/* CAN_DEBUG Masks */
+#define DEC                     0x0001  /* Disable CAN Error Counters */
+#define DRI                     0x0002  /* Disable CAN RX Input */
+#define DTO                     0x0004  /* Disable CAN TX Output */
+#define DIL                     0x0008  /* Disable CAN Internal Loop */
+#define MAA                     0x0010  /* Mode Auto-Acknowledge Enable */
+#define MRB                     0x0020  /* Mode Read Back Enable */
+#define CDE                     0x8000  /* CAN Debug Enable */
+
+/* CAN_CEC Masks */
+#define RXECNT          0x00FF  /* Receive Error Counter */
+#define TXECNT          0xFF00  /* Transmit Error Counter */
+
+/* CAN_INTR Masks */
+#define MBRIRQ  0x0001  /* Mailbox Receive Interrupt */
+#define MBTIRQ  0x0002  /* Mailbox Transmit Interrupt */
+#define GIRQ            0x0004  /* Global Interrupt */
+#define SMACK           0x0008  /* Sleep Mode Acknowledge */
+#define CANTX           0x0040  /* CAN TX Bus Value */
+#define CANRX           0x0080  /* CAN RX Bus Value */
+
+/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */
+#define DFC                     0xFFFF  /* Data Filtering Code (If Enabled) (ID0) */
+#define EXTID_LO        0xFFFF  /* Lower 16 Bits of Extended Identifier (ID0) */
+#define EXTID_HI        0x0003  /* Upper 2 Bits of Extended Identifier (ID1) */
+#define BASEID          0x1FFC  /* Base Identifier */
+#define IDE                     0x2000  /* Identifier Extension */
+#define RTR                     0x4000  /* Remote Frame Transmission Request */
+#define AME                     0x8000  /* Acceptance Mask Enable */
+
+/* CAN_MBxx_TIMESTAMP Masks */
+#define TSV                     0xFFFF  /* Timestamp */
+
+/* CAN_MBxx_LENGTH Masks */
+#define DLC                     0x000F  /* Data Length Code */
+
+/* CAN_AMxxH and CAN_AMxxL Masks */
+#define DFM                     0xFFFF  /* Data Field Mask (If Enabled) (CAN_AMxxL) */
+#define EXTID_LO        0xFFFF  /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */
+#define EXTID_HI        0x0003  /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */
+#define BASEID          0x1FFC  /* Base Identifier */
+#define AMIDE           0x2000  /* Acceptance Mask ID Extension Enable */
+#define FMD                     0x4000  /* Full Mask Data Field Enable */
+#define FDF                     0x8000  /* Filter On Data Field Enable */
+
+/* CAN_MC1 Masks */
+#define MC0                     0x0001  /* Enable Mailbox 0 */
+#define MC1                     0x0002  /* Enable Mailbox 1 */
+#define MC2                     0x0004  /* Enable Mailbox 2 */
+#define MC3                     0x0008  /* Enable Mailbox 3 */
+#define MC4                     0x0010  /* Enable Mailbox 4 */
+#define MC5                     0x0020  /* Enable Mailbox 5 */
+#define MC6                     0x0040  /* Enable Mailbox 6 */
+#define MC7                     0x0080  /* Enable Mailbox 7 */
+#define MC8                     0x0100  /* Enable Mailbox 8 */
+#define MC9                     0x0200  /* Enable Mailbox 9 */
+#define MC10            0x0400  /* Enable Mailbox 10 */
+#define MC11            0x0800  /* Enable Mailbox 11 */
+#define MC12            0x1000  /* Enable Mailbox 12 */
+#define MC13            0x2000  /* Enable Mailbox 13 */
+#define MC14            0x4000  /* Enable Mailbox 14 */
+#define MC15            0x8000  /* Enable Mailbox 15 */
+
+/* CAN_MC2 Masks */
+#define MC16            0x0001  /* Enable Mailbox 16 */
+#define MC17            0x0002  /* Enable Mailbox 17 */
+#define MC18            0x0004  /* Enable Mailbox 18 */
+#define MC19            0x0008  /* Enable Mailbox 19 */
+#define MC20            0x0010  /* Enable Mailbox 20 */
+#define MC21            0x0020  /* Enable Mailbox 21 */
+#define MC22            0x0040  /* Enable Mailbox 22 */
+#define MC23            0x0080  /* Enable Mailbox 23 */
+#define MC24            0x0100  /* Enable Mailbox 24 */
+#define MC25            0x0200  /* Enable Mailbox 25 */
+#define MC26            0x0400  /* Enable Mailbox 26 */
+#define MC27            0x0800  /* Enable Mailbox 27 */
+#define MC28            0x1000  /* Enable Mailbox 28 */
+#define MC29            0x2000  /* Enable Mailbox 29 */
+#define MC30            0x4000  /* Enable Mailbox 30 */
+#define MC31            0x8000  /* Enable Mailbox 31 */
+
+/* CAN_MD1 Masks */
+#define MD0                     0x0001  /* Enable Mailbox 0 For Receive */
+#define MD1                     0x0002  /* Enable Mailbox 1 For Receive */
+#define MD2                     0x0004  /* Enable Mailbox 2 For Receive */
+#define MD3                     0x0008  /* Enable Mailbox 3 For Receive */
+#define MD4                     0x0010  /* Enable Mailbox 4 For Receive */
+#define MD5                     0x0020  /* Enable Mailbox 5 For Receive */
+#define MD6                     0x0040  /* Enable Mailbox 6 For Receive */
+#define MD7                     0x0080  /* Enable Mailbox 7 For Receive */
+#define MD8                     0x0100  /* Enable Mailbox 8 For Receive */
+#define MD9                     0x0200  /* Enable Mailbox 9 For Receive */
+#define MD10            0x0400  /* Enable Mailbox 10 For Receive */
+#define MD11            0x0800  /* Enable Mailbox 11 For Receive */
+#define MD12            0x1000  /* Enable Mailbox 12 For Receive */
+#define MD13            0x2000  /* Enable Mailbox 13 For Receive */
+#define MD14            0x4000  /* Enable Mailbox 14 For Receive */
+#define MD15            0x8000  /* Enable Mailbox 15 For Receive */
+
+/* CAN_MD2 Masks */
+#define MD16            0x0001  /* Enable Mailbox 16 For Receive */
+#define MD17            0x0002  /* Enable Mailbox 17 For Receive */
+#define MD18            0x0004  /* Enable Mailbox 18 For Receive */
+#define MD19            0x0008  /* Enable Mailbox 19 For Receive */
+#define MD20            0x0010  /* Enable Mailbox 20 For Receive */
+#define MD21            0x0020  /* Enable Mailbox 21 For Receive */
+#define MD22            0x0040  /* Enable Mailbox 22 For Receive */
+#define MD23            0x0080  /* Enable Mailbox 23 For Receive */
+#define MD24            0x0100  /* Enable Mailbox 24 For Receive */
+#define MD25            0x0200  /* Enable Mailbox 25 For Receive */
+#define MD26            0x0400  /* Enable Mailbox 26 For Receive */
+#define MD27            0x0800  /* Enable Mailbox 27 For Receive */
+#define MD28            0x1000  /* Enable Mailbox 28 For Receive */
+#define MD29            0x2000  /* Enable Mailbox 29 For Receive */
+#define MD30            0x4000  /* Enable Mailbox 30 For Receive */
+#define MD31            0x8000  /* Enable Mailbox 31 For Receive */
+
+/* CAN_RMP1 Masks */
+#define RMP0            0x0001  /* RX Message Pending In Mailbox 0 */
+#define RMP1            0x0002  /* RX Message Pending In Mailbox 1 */
+#define RMP2            0x0004  /* RX Message Pending In Mailbox 2 */
+#define RMP3            0x0008  /* RX Message Pending In Mailbox 3 */
+#define RMP4            0x0010  /* RX Message Pending In Mailbox 4 */
+#define RMP5            0x0020  /* RX Message Pending In Mailbox 5 */
+#define RMP6            0x0040  /* RX Message Pending In Mailbox 6 */
+#define RMP7            0x0080  /* RX Message Pending In Mailbox 7 */
+#define RMP8            0x0100  /* RX Message Pending In Mailbox 8 */
+#define RMP9            0x0200  /* RX Message Pending In Mailbox 9 */
+#define RMP10           0x0400  /* RX Message Pending In Mailbox 10 */
+#define RMP11           0x0800  /* RX Message Pending In Mailbox 11 */
+#define RMP12           0x1000  /* RX Message Pending In Mailbox 12 */
+#define RMP13           0x2000  /* RX Message Pending In Mailbox 13 */
+#define RMP14           0x4000  /* RX Message Pending In Mailbox 14 */
+#define RMP15           0x8000  /* RX Message Pending In Mailbox 15 */
+
+/* CAN_RMP2 Masks */
+#define RMP16           0x0001  /* RX Message Pending In Mailbox 16 */
+#define RMP17           0x0002  /* RX Message Pending In Mailbox 17 */
+#define RMP18           0x0004  /* RX Message Pending In Mailbox 18 */
+#define RMP19           0x0008  /* RX Message Pending In Mailbox 19 */
+#define RMP20           0x0010  /* RX Message Pending In Mailbox 20 */
+#define RMP21           0x0020  /* RX Message Pending In Mailbox 21 */
+#define RMP22           0x0040  /* RX Message Pending In Mailbox 22 */
+#define RMP23           0x0080  /* RX Message Pending In Mailbox 23 */
+#define RMP24           0x0100  /* RX Message Pending In Mailbox 24 */
+#define RMP25           0x0200  /* RX Message Pending In Mailbox 25 */
+#define RMP26           0x0400  /* RX Message Pending In Mailbox 26 */
+#define RMP27           0x0800  /* RX Message Pending In Mailbox 27 */
+#define RMP28           0x1000  /* RX Message Pending In Mailbox 28 */
+#define RMP29           0x2000  /* RX Message Pending In Mailbox 29 */
+#define RMP30           0x4000  /* RX Message Pending In Mailbox 30 */
+#define RMP31           0x8000  /* RX Message Pending In Mailbox 31 */
+
+/* CAN_RML1 Masks */
+#define RML0            0x0001  /* RX Message Lost In Mailbox 0 */
+#define RML1            0x0002  /* RX Message Lost In Mailbox 1 */
+#define RML2            0x0004  /* RX Message Lost In Mailbox 2 */
+#define RML3            0x0008  /* RX Message Lost In Mailbox 3 */
+#define RML4            0x0010  /* RX Message Lost In Mailbox 4 */
+#define RML5            0x0020  /* RX Message Lost In Mailbox 5 */
+#define RML6            0x0040  /* RX Message Lost In Mailbox 6 */
+#define RML7            0x0080  /* RX Message Lost In Mailbox 7 */
+#define RML8            0x0100  /* RX Message Lost In Mailbox 8 */
+#define RML9            0x0200  /* RX Message Lost In Mailbox 9 */
+#define RML10           0x0400  /* RX Message Lost In Mailbox 10 */
+#define RML11           0x0800  /* RX Message Lost In Mailbox 11 */
+#define RML12           0x1000  /* RX Message Lost In Mailbox 12 */
+#define RML13           0x2000  /* RX Message Lost In Mailbox 13 */
+#define RML14           0x4000  /* RX Message Lost In Mailbox 14 */
+#define RML15           0x8000  /* RX Message Lost In Mailbox 15 */
+
+/* CAN_RML2 Masks */
+#define RML16           0x0001  /* RX Message Lost In Mailbox 16 */
+#define RML17           0x0002  /* RX Message Lost In Mailbox 17 */
+#define RML18           0x0004  /* RX Message Lost In Mailbox 18 */
+#define RML19           0x0008  /* RX Message Lost In Mailbox 19 */
+#define RML20           0x0010  /* RX Message Lost In Mailbox 20 */
+#define RML21           0x0020  /* RX Message Lost In Mailbox 21 */
+#define RML22           0x0040  /* RX Message Lost In Mailbox 22 */
+#define RML23           0x0080  /* RX Message Lost In Mailbox 23 */
+#define RML24           0x0100  /* RX Message Lost In Mailbox 24 */
+#define RML25           0x0200  /* RX Message Lost In Mailbox 25 */
+#define RML26           0x0400  /* RX Message Lost In Mailbox 26 */
+#define RML27           0x0800  /* RX Message Lost In Mailbox 27 */
+#define RML28           0x1000  /* RX Message Lost In Mailbox 28 */
+#define RML29           0x2000  /* RX Message Lost In Mailbox 29 */
+#define RML30           0x4000  /* RX Message Lost In Mailbox 30 */
+#define RML31           0x8000  /* RX Message Lost In Mailbox 31 */
+
+/* CAN_OPSS1 Masks */
+#define OPSS0           0x0001  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */
+#define OPSS1           0x0002  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */
+#define OPSS2           0x0004  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */
+#define OPSS3           0x0008  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */
+#define OPSS4           0x0010  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */
+#define OPSS5           0x0020  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */
+#define OPSS6           0x0040  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */
+#define OPSS7           0x0080  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */
+#define OPSS8           0x0100  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */
+#define OPSS9           0x0200  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */
+#define OPSS10          0x0400  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */
+#define OPSS11          0x0800  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */
+#define OPSS12          0x1000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */
+#define OPSS13          0x2000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */
+#define OPSS14          0x4000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */
+#define OPSS15          0x8000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */
+
+/* CAN_OPSS2 Masks */
+#define OPSS16          0x0001  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */
+#define OPSS17          0x0002  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */
+#define OPSS18          0x0004  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */
+#define OPSS19          0x0008  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */
+#define OPSS20          0x0010  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */
+#define OPSS21          0x0020  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */
+#define OPSS22          0x0040  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */
+#define OPSS23          0x0080  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */
+#define OPSS24          0x0100  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */
+#define OPSS25          0x0200  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */
+#define OPSS26          0x0400  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */
+#define OPSS27          0x0800  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */
+#define OPSS28          0x1000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */
+#define OPSS29          0x2000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */
+#define OPSS30          0x4000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */
+#define OPSS31          0x8000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */
+
+/* CAN_TRR1 Masks */
+#define TRR0            0x0001  /* Deny But Don't Lock Access To Mailbox 0 */
+#define TRR1            0x0002  /* Deny But Don't Lock Access To Mailbox 1 */
+#define TRR2            0x0004  /* Deny But Don't Lock Access To Mailbox 2 */
+#define TRR3            0x0008  /* Deny But Don't Lock Access To Mailbox 3 */
+#define TRR4            0x0010  /* Deny But Don't Lock Access To Mailbox 4 */
+#define TRR5            0x0020  /* Deny But Don't Lock Access To Mailbox 5 */
+#define TRR6            0x0040  /* Deny But Don't Lock Access To Mailbox 6 */
+#define TRR7            0x0080  /* Deny But Don't Lock Access To Mailbox 7 */
+#define TRR8            0x0100  /* Deny But Don't Lock Access To Mailbox 8 */
+#define TRR9            0x0200  /* Deny But Don't Lock Access To Mailbox 9 */
+#define TRR10           0x0400  /* Deny But Don't Lock Access To Mailbox 10 */
+#define TRR11           0x0800  /* Deny But Don't Lock Access To Mailbox 11 */
+#define TRR12           0x1000  /* Deny But Don't Lock Access To Mailbox 12 */
+#define TRR13           0x2000  /* Deny But Don't Lock Access To Mailbox 13 */
+#define TRR14           0x4000  /* Deny But Don't Lock Access To Mailbox 14 */
+#define TRR15           0x8000  /* Deny But Don't Lock Access To Mailbox 15 */
+
+/* CAN_TRR2 Masks */
+#define TRR16           0x0001  /* Deny But Don't Lock Access To Mailbox 16 */
+#define TRR17           0x0002  /* Deny But Don't Lock Access To Mailbox 17 */
+#define TRR18           0x0004  /* Deny But Don't Lock Access To Mailbox 18 */
+#define TRR19           0x0008  /* Deny But Don't Lock Access To Mailbox 19 */
+#define TRR20           0x0010  /* Deny But Don't Lock Access To Mailbox 20 */
+#define TRR21           0x0020  /* Deny But Don't Lock Access To Mailbox 21 */
+#define TRR22           0x0040  /* Deny But Don't Lock Access To Mailbox 22 */
+#define TRR23           0x0080  /* Deny But Don't Lock Access To Mailbox 23 */
+#define TRR24           0x0100  /* Deny But Don't Lock Access To Mailbox 24 */
+#define TRR25           0x0200  /* Deny But Don't Lock Access To Mailbox 25 */
+#define TRR26           0x0400  /* Deny But Don't Lock Access To Mailbox 26 */
+#define TRR27           0x0800  /* Deny But Don't Lock Access To Mailbox 27 */
+#define TRR28           0x1000  /* Deny But Don't Lock Access To Mailbox 28 */
+#define TRR29           0x2000  /* Deny But Don't Lock Access To Mailbox 29 */
+#define TRR30           0x4000  /* Deny But Don't Lock Access To Mailbox 30 */
+#define TRR31           0x8000  /* Deny But Don't Lock Access To Mailbox 31 */
+
+/* CAN_TRS1 Masks */
+#define TRS0            0x0001  /* Remote Frame Request For Mailbox 0 */
+#define TRS1            0x0002  /* Remote Frame Request For Mailbox 1 */
+#define TRS2            0x0004  /* Remote Frame Request For Mailbox 2 */
+#define TRS3            0x0008  /* Remote Frame Request For Mailbox 3 */
+#define TRS4            0x0010  /* Remote Frame Request For Mailbox 4 */
+#define TRS5            0x0020  /* Remote Frame Request For Mailbox 5 */
+#define TRS6            0x0040  /* Remote Frame Request For Mailbox 6 */
+#define TRS7            0x0080  /* Remote Frame Request For Mailbox 7 */
+#define TRS8            0x0100  /* Remote Frame Request For Mailbox 8 */
+#define TRS9            0x0200  /* Remote Frame Request For Mailbox 9 */
+#define TRS10           0x0400  /* Remote Frame Request For Mailbox 10 */
+#define TRS11           0x0800  /* Remote Frame Request For Mailbox 11 */
+#define TRS12           0x1000  /* Remote Frame Request For Mailbox 12 */
+#define TRS13           0x2000  /* Remote Frame Request For Mailbox 13 */
+#define TRS14           0x4000  /* Remote Frame Request For Mailbox 14 */
+#define TRS15           0x8000  /* Remote Frame Request For Mailbox 15 */
+
+/* CAN_TRS2 Masks */
+#define TRS16           0x0001  /* Remote Frame Request For Mailbox 16 */
+#define TRS17           0x0002  /* Remote Frame Request For Mailbox 17 */
+#define TRS18           0x0004  /* Remote Frame Request For Mailbox 18 */
+#define TRS19           0x0008  /* Remote Frame Request For Mailbox 19 */
+#define TRS20           0x0010  /* Remote Frame Request For Mailbox 20 */
+#define TRS21           0x0020  /* Remote Frame Request For Mailbox 21 */
+#define TRS22           0x0040  /* Remote Frame Request For Mailbox 22 */
+#define TRS23           0x0080  /* Remote Frame Request For Mailbox 23 */
+#define TRS24           0x0100  /* Remote Frame Request For Mailbox 24 */
+#define TRS25           0x0200  /* Remote Frame Request For Mailbox 25 */
+#define TRS26           0x0400  /* Remote Frame Request For Mailbox 26 */
+#define TRS27           0x0800  /* Remote Frame Request For Mailbox 27 */
+#define TRS28           0x1000  /* Remote Frame Request For Mailbox 28 */
+#define TRS29           0x2000  /* Remote Frame Request For Mailbox 29 */
+#define TRS30           0x4000  /* Remote Frame Request For Mailbox 30 */
+#define TRS31           0x8000  /* Remote Frame Request For Mailbox 31 */
+
+/* CAN_AA1 Masks */
+#define AA0                     0x0001  /* Aborted Message In Mailbox 0 */
+#define AA1                     0x0002  /* Aborted Message In Mailbox 1 */
+#define AA2                     0x0004  /* Aborted Message In Mailbox 2 */
+#define AA3                     0x0008  /* Aborted Message In Mailbox 3 */
+#define AA4                     0x0010  /* Aborted Message In Mailbox 4 */
+#define AA5                     0x0020  /* Aborted Message In Mailbox 5 */
+#define AA6                     0x0040  /* Aborted Message In Mailbox 6 */
+#define AA7                     0x0080  /* Aborted Message In Mailbox 7 */
+#define AA8                     0x0100  /* Aborted Message In Mailbox 8 */
+#define AA9                     0x0200  /* Aborted Message In Mailbox 9 */
+#define AA10            0x0400  /* Aborted Message In Mailbox 10 */
+#define AA11            0x0800  /* Aborted Message In Mailbox 11 */
+#define AA12            0x1000  /* Aborted Message In Mailbox 12 */
+#define AA13            0x2000  /* Aborted Message In Mailbox 13 */
+#define AA14            0x4000  /* Aborted Message In Mailbox 14 */
+#define AA15            0x8000  /* Aborted Message In Mailbox 15 */
+
+/* CAN_AA2 Masks */
+#define AA16            0x0001  /* Aborted Message In Mailbox 16 */
+#define AA17            0x0002  /* Aborted Message In Mailbox 17 */
+#define AA18            0x0004  /* Aborted Message In Mailbox 18 */
+#define AA19            0x0008  /* Aborted Message In Mailbox 19 */
+#define AA20            0x0010  /* Aborted Message In Mailbox 20 */
+#define AA21            0x0020  /* Aborted Message In Mailbox 21 */
+#define AA22            0x0040  /* Aborted Message In Mailbox 22 */
+#define AA23            0x0080  /* Aborted Message In Mailbox 23 */
+#define AA24            0x0100  /* Aborted Message In Mailbox 24 */
+#define AA25            0x0200  /* Aborted Message In Mailbox 25 */
+#define AA26            0x0400  /* Aborted Message In Mailbox 26 */
+#define AA27            0x0800  /* Aborted Message In Mailbox 27 */
+#define AA28            0x1000  /* Aborted Message In Mailbox 28 */
+#define AA29            0x2000  /* Aborted Message In Mailbox 29 */
+#define AA30            0x4000  /* Aborted Message In Mailbox 30 */
+#define AA31            0x8000  /* Aborted Message In Mailbox 31 */
+
+/* CAN_TA1 Masks */
+#define TA0                     0x0001  /* Transmit Successful From Mailbox 0 */
+#define TA1                     0x0002  /* Transmit Successful From Mailbox 1 */
+#define TA2                     0x0004  /* Transmit Successful From Mailbox 2 */
+#define TA3                     0x0008  /* Transmit Successful From Mailbox 3 */
+#define TA4                     0x0010  /* Transmit Successful From Mailbox 4 */
+#define TA5                     0x0020  /* Transmit Successful From Mailbox 5 */
+#define TA6                     0x0040  /* Transmit Successful From Mailbox 6 */
+#define TA7                     0x0080  /* Transmit Successful From Mailbox 7 */
+#define TA8                     0x0100  /* Transmit Successful From Mailbox 8 */
+#define TA9                     0x0200  /* Transmit Successful From Mailbox 9 */
+#define TA10            0x0400  /* Transmit Successful From Mailbox 10 */
+#define TA11            0x0800  /* Transmit Successful From Mailbox 11 */
+#define TA12            0x1000  /* Transmit Successful From Mailbox 12 */
+#define TA13            0x2000  /* Transmit Successful From Mailbox 13 */
+#define TA14            0x4000  /* Transmit Successful From Mailbox 14 */
+#define TA15            0x8000  /* Transmit Successful From Mailbox 15 */
+
+/* CAN_TA2 Masks */
+#define TA16            0x0001  /* Transmit Successful From Mailbox 16 */
+#define TA17            0x0002  /* Transmit Successful From Mailbox 17 */
+#define TA18            0x0004  /* Transmit Successful From Mailbox 18 */
+#define TA19            0x0008  /* Transmit Successful From Mailbox 19 */
+#define TA20            0x0010  /* Transmit Successful From Mailbox 20 */
+#define TA21            0x0020  /* Transmit Successful From Mailbox 21 */
+#define TA22            0x0040  /* Transmit Successful From Mailbox 22 */
+#define TA23            0x0080  /* Transmit Successful From Mailbox 23 */
+#define TA24            0x0100  /* Transmit Successful From Mailbox 24 */
+#define TA25            0x0200  /* Transmit Successful From Mailbox 25 */
+#define TA26            0x0400  /* Transmit Successful From Mailbox 26 */
+#define TA27            0x0800  /* Transmit Successful From Mailbox 27 */
+#define TA28            0x1000  /* Transmit Successful From Mailbox 28 */
+#define TA29            0x2000  /* Transmit Successful From Mailbox 29 */
+#define TA30            0x4000  /* Transmit Successful From Mailbox 30 */
+#define TA31            0x8000  /* Transmit Successful From Mailbox 31 */
+
+/* CAN_MBTD Masks */
+#define TDPTR           0x001F  /* Mailbox To Temporarily Disable */
+#define TDA                     0x0040  /* Temporary Disable Acknowledge */
+#define TDR                     0x0080  /* Temporary Disable Request */
+
+/* CAN_RFH1 Masks */
+#define RFH0            0x0001  /* Enable Automatic Remote Frame Handling For Mailbox 0 */
+#define RFH1            0x0002  /* Enable Automatic Remote Frame Handling For Mailbox 1 */
+#define RFH2            0x0004  /* Enable Automatic Remote Frame Handling For Mailbox 2 */
+#define RFH3            0x0008  /* Enable Automatic Remote Frame Handling For Mailbox 3 */
+#define RFH4            0x0010  /* Enable Automatic Remote Frame Handling For Mailbox 4 */
+#define RFH5            0x0020  /* Enable Automatic Remote Frame Handling For Mailbox 5 */
+#define RFH6            0x0040  /* Enable Automatic Remote Frame Handling For Mailbox 6 */
+#define RFH7            0x0080  /* Enable Automatic Remote Frame Handling For Mailbox 7 */
+#define RFH8            0x0100  /* Enable Automatic Remote Frame Handling For Mailbox 8 */
+#define RFH9            0x0200  /* Enable Automatic Remote Frame Handling For Mailbox 9 */
+#define RFH10           0x0400  /* Enable Automatic Remote Frame Handling For Mailbox 10 */
+#define RFH11           0x0800  /* Enable Automatic Remote Frame Handling For Mailbox 11 */
+#define RFH12           0x1000  /* Enable Automatic Remote Frame Handling For Mailbox 12 */
+#define RFH13           0x2000  /* Enable Automatic Remote Frame Handling For Mailbox 13 */
+#define RFH14           0x4000  /* Enable Automatic Remote Frame Handling For Mailbox 14 */
+#define RFH15           0x8000  /* Enable Automatic Remote Frame Handling For Mailbox 15 */
+
+/* CAN_RFH2 Masks */
+#define RFH16           0x0001  /* Enable Automatic Remote Frame Handling For Mailbox 16 */
+#define RFH17           0x0002  /* Enable Automatic Remote Frame Handling For Mailbox 17 */
+#define RFH18           0x0004  /* Enable Automatic Remote Frame Handling For Mailbox 18 */
+#define RFH19           0x0008  /* Enable Automatic Remote Frame Handling For Mailbox 19 */
+#define RFH20           0x0010  /* Enable Automatic Remote Frame Handling For Mailbox 20 */
+#define RFH21           0x0020  /* Enable Automatic Remote Frame Handling For Mailbox 21 */
+#define RFH22           0x0040  /* Enable Automatic Remote Frame Handling For Mailbox 22 */
+#define RFH23           0x0080  /* Enable Automatic Remote Frame Handling For Mailbox 23 */
+#define RFH24           0x0100  /* Enable Automatic Remote Frame Handling For Mailbox 24 */
+#define RFH25           0x0200  /* Enable Automatic Remote Frame Handling For Mailbox 25 */
+#define RFH26           0x0400  /* Enable Automatic Remote Frame Handling For Mailbox 26 */
+#define RFH27           0x0800  /* Enable Automatic Remote Frame Handling For Mailbox 27 */
+#define RFH28           0x1000  /* Enable Automatic Remote Frame Handling For Mailbox 28 */
+#define RFH29           0x2000  /* Enable Automatic Remote Frame Handling For Mailbox 29 */
+#define RFH30           0x4000  /* Enable Automatic Remote Frame Handling For Mailbox 30 */
+#define RFH31           0x8000  /* Enable Automatic Remote Frame Handling For Mailbox 31 */
+
+/* CAN_MBTIF1 Masks */
+#define MBTIF0          0x0001  /* TX Interrupt Active In Mailbox 0 */
+#define MBTIF1          0x0002  /* TX Interrupt Active In Mailbox 1 */
+#define MBTIF2          0x0004  /* TX Interrupt Active In Mailbox 2 */
+#define MBTIF3          0x0008  /* TX Interrupt Active In Mailbox 3 */
+#define MBTIF4          0x0010  /* TX Interrupt Active In Mailbox 4 */
+#define MBTIF5          0x0020  /* TX Interrupt Active In Mailbox 5 */
+#define MBTIF6          0x0040  /* TX Interrupt Active In Mailbox 6 */
+#define MBTIF7          0x0080  /* TX Interrupt Active In Mailbox 7 */
+#define MBTIF8          0x0100  /* TX Interrupt Active In Mailbox 8 */
+#define MBTIF9          0x0200  /* TX Interrupt Active In Mailbox 9 */
+#define MBTIF10         0x0400  /* TX Interrupt Active In Mailbox 10 */
+#define MBTIF11         0x0800  /* TX Interrupt Active In Mailbox 11 */
+#define MBTIF12         0x1000  /* TX Interrupt Active In Mailbox 12 */
+#define MBTIF13         0x2000  /* TX Interrupt Active In Mailbox 13 */
+#define MBTIF14         0x4000  /* TX Interrupt Active In Mailbox 14 */
+#define MBTIF15         0x8000  /* TX Interrupt Active In Mailbox 15 */
+
+/* CAN_MBTIF2 Masks */
+#define MBTIF16         0x0001  /* TX Interrupt Active In Mailbox 16 */
+#define MBTIF17         0x0002  /* TX Interrupt Active In Mailbox 17 */
+#define MBTIF18         0x0004  /* TX Interrupt Active In Mailbox 18 */
+#define MBTIF19         0x0008  /* TX Interrupt Active In Mailbox 19 */
+#define MBTIF20         0x0010  /* TX Interrupt Active In Mailbox 20 */
+#define MBTIF21         0x0020  /* TX Interrupt Active In Mailbox 21 */
+#define MBTIF22         0x0040  /* TX Interrupt Active In Mailbox 22 */
+#define MBTIF23         0x0080  /* TX Interrupt Active In Mailbox 23 */
+#define MBTIF24         0x0100  /* TX Interrupt Active In Mailbox 24 */
+#define MBTIF25         0x0200  /* TX Interrupt Active In Mailbox 25 */
+#define MBTIF26         0x0400  /* TX Interrupt Active In Mailbox 26 */
+#define MBTIF27         0x0800  /* TX Interrupt Active In Mailbox 27 */
+#define MBTIF28         0x1000  /* TX Interrupt Active In Mailbox 28 */
+#define MBTIF29         0x2000  /* TX Interrupt Active In Mailbox 29 */
+#define MBTIF30         0x4000  /* TX Interrupt Active In Mailbox 30 */
+#define MBTIF31         0x8000  /* TX Interrupt Active In Mailbox 31 */
+
+/* CAN_MBRIF1 Masks */
+#define MBRIF0          0x0001  /* RX Interrupt Active In Mailbox 0 */
+#define MBRIF1          0x0002  /* RX Interrupt Active In Mailbox 1 */
+#define MBRIF2          0x0004  /* RX Interrupt Active In Mailbox 2 */
+#define MBRIF3          0x0008  /* RX Interrupt Active In Mailbox 3 */
+#define MBRIF4          0x0010  /* RX Interrupt Active In Mailbox 4 */
+#define MBRIF5          0x0020  /* RX Interrupt Active In Mailbox 5 */
+#define MBRIF6          0x0040  /* RX Interrupt Active In Mailbox 6 */
+#define MBRIF7          0x0080  /* RX Interrupt Active In Mailbox 7 */
+#define MBRIF8          0x0100  /* RX Interrupt Active In Mailbox 8 */
+#define MBRIF9          0x0200  /* RX Interrupt Active In Mailbox 9 */
+#define MBRIF10         0x0400  /* RX Interrupt Active In Mailbox 10 */
+#define MBRIF11         0x0800  /* RX Interrupt Active In Mailbox 11 */
+#define MBRIF12         0x1000  /* RX Interrupt Active In Mailbox 12 */
+#define MBRIF13         0x2000  /* RX Interrupt Active In Mailbox 13 */
+#define MBRIF14         0x4000  /* RX Interrupt Active In Mailbox 14 */
+#define MBRIF15         0x8000  /* RX Interrupt Active In Mailbox 15 */
+
+/* CAN_MBRIF2 Masks */
+#define MBRIF16         0x0001  /* RX Interrupt Active In Mailbox 16 */
+#define MBRIF17         0x0002  /* RX Interrupt Active In Mailbox 17 */
+#define MBRIF18         0x0004  /* RX Interrupt Active In Mailbox 18 */
+#define MBRIF19         0x0008  /* RX Interrupt Active In Mailbox 19 */
+#define MBRIF20         0x0010  /* RX Interrupt Active In Mailbox 20 */
+#define MBRIF21         0x0020  /* RX Interrupt Active In Mailbox 21 */
+#define MBRIF22         0x0040  /* RX Interrupt Active In Mailbox 22 */
+#define MBRIF23         0x0080  /* RX Interrupt Active In Mailbox 23 */
+#define MBRIF24         0x0100  /* RX Interrupt Active In Mailbox 24 */
+#define MBRIF25         0x0200  /* RX Interrupt Active In Mailbox 25 */
+#define MBRIF26         0x0400  /* RX Interrupt Active In Mailbox 26 */
+#define MBRIF27         0x0800  /* RX Interrupt Active In Mailbox 27 */
+#define MBRIF28         0x1000  /* RX Interrupt Active In Mailbox 28 */
+#define MBRIF29         0x2000  /* RX Interrupt Active In Mailbox 29 */
+#define MBRIF30         0x4000  /* RX Interrupt Active In Mailbox 30 */
+#define MBRIF31         0x8000  /* RX Interrupt Active In Mailbox 31 */
+
+/* CAN_MBIM1 Masks */
+#define MBIM0           0x0001  /* Enable Interrupt For Mailbox 0 */
+#define MBIM1           0x0002  /* Enable Interrupt For Mailbox 1 */
+#define MBIM2           0x0004  /* Enable Interrupt For Mailbox 2 */
+#define MBIM3           0x0008  /* Enable Interrupt For Mailbox 3 */
+#define MBIM4           0x0010  /* Enable Interrupt For Mailbox 4 */
+#define MBIM5           0x0020  /* Enable Interrupt For Mailbox 5 */
+#define MBIM6           0x0040  /* Enable Interrupt For Mailbox 6 */
+#define MBIM7           0x0080  /* Enable Interrupt For Mailbox 7 */
+#define MBIM8           0x0100  /* Enable Interrupt For Mailbox 8 */
+#define MBIM9           0x0200  /* Enable Interrupt For Mailbox 9 */
+#define MBIM10          0x0400  /* Enable Interrupt For Mailbox 10 */
+#define MBIM11          0x0800  /* Enable Interrupt For Mailbox 11 */
+#define MBIM12          0x1000  /* Enable Interrupt For Mailbox 12 */
+#define MBIM13          0x2000  /* Enable Interrupt For Mailbox 13 */
+#define MBIM14          0x4000  /* Enable Interrupt For Mailbox 14 */
+#define MBIM15          0x8000  /* Enable Interrupt For Mailbox 15 */
+
+/* CAN_MBIM2 Masks */
+#define MBIM16          0x0001  /* Enable Interrupt For Mailbox 16 */
+#define MBIM17          0x0002  /* Enable Interrupt For Mailbox 17 */
+#define MBIM18          0x0004  /* Enable Interrupt For Mailbox 18 */
+#define MBIM19          0x0008  /* Enable Interrupt For Mailbox 19 */
+#define MBIM20          0x0010  /* Enable Interrupt For Mailbox 20 */
+#define MBIM21          0x0020  /* Enable Interrupt For Mailbox 21 */
+#define MBIM22          0x0040  /* Enable Interrupt For Mailbox 22 */
+#define MBIM23          0x0080  /* Enable Interrupt For Mailbox 23 */
+#define MBIM24          0x0100  /* Enable Interrupt For Mailbox 24 */
+#define MBIM25          0x0200  /* Enable Interrupt For Mailbox 25 */
+#define MBIM26          0x0400  /* Enable Interrupt For Mailbox 26 */
+#define MBIM27          0x0800  /* Enable Interrupt For Mailbox 27 */
+#define MBIM28          0x1000  /* Enable Interrupt For Mailbox 28 */
+#define MBIM29          0x2000  /* Enable Interrupt For Mailbox 29 */
+#define MBIM30          0x4000  /* Enable Interrupt For Mailbox 30 */
+#define MBIM31          0x8000  /* Enable Interrupt For Mailbox 31 */
+
+/* CAN_GIM Masks */
+#define EWTIM           0x0001  /* Enable TX Error Count Interrupt */
+#define EWRIM           0x0002  /* Enable RX Error Count Interrupt */
+#define EPIM            0x0004  /* Enable Error-Passive Mode Interrupt */
+#define BOIM            0x0008  /* Enable Bus Off Interrupt */
+#define WUIM            0x0010  /* Enable Wake-Up Interrupt */
+#define UIAIM           0x0020  /* Enable Access To Unimplemented Address Interrupt */
+#define AAIM            0x0040  /* Enable Abort Acknowledge Interrupt */
+#define RMLIM           0x0080  /* Enable RX Message Lost Interrupt */
+#define UCEIM           0x0100  /* Enable Universal Counter Overflow Interrupt */
+#define EXTIM           0x0200  /* Enable External Trigger Output Interrupt */
+#define ADIM            0x0400  /* Enable Access Denied Interrupt */
+
+/* CAN_GIS Masks */
+#define EWTIS           0x0001  /* TX Error Count IRQ Status */
+#define EWRIS           0x0002  /* RX Error Count IRQ Status */
+#define EPIS            0x0004  /* Error-Passive Mode IRQ Status */
+#define BOIS            0x0008  /* Bus Off IRQ Status */
+#define WUIS            0x0010  /* Wake-Up IRQ Status */
+#define UIAIS           0x0020  /* Access To Unimplemented Address IRQ Status */
+#define AAIS            0x0040  /* Abort Acknowledge IRQ Status */
+#define RMLIS           0x0080  /* RX Message Lost IRQ Status */
+#define UCEIS           0x0100  /* Universal Counter Overflow IRQ Status */
+#define EXTIS           0x0200  /* External Trigger Output IRQ Status */
+#define ADIS            0x0400  /* Access Denied IRQ Status */
+
+/* CAN_GIF Masks */
+#define EWTIF           0x0001  /* TX Error Count IRQ Flag */
+#define EWRIF           0x0002  /* RX Error Count IRQ Flag */
+#define EPIF            0x0004  /* Error-Passive Mode IRQ Flag */
+#define BOIF            0x0008  /* Bus Off IRQ Flag */
+#define WUIF            0x0010  /* Wake-Up IRQ Flag */
+#define UIAIF           0x0020  /* Access To Unimplemented Address IRQ Flag */
+#define AAIF            0x0040  /* Abort Acknowledge IRQ Flag */
+#define RMLIF           0x0080  /* RX Message Lost IRQ Flag */
+#define UCEIF           0x0100  /* Universal Counter Overflow IRQ Flag */
+#define EXTIF           0x0200  /* External Trigger Output IRQ Flag */
+#define ADIF            0x0400  /* Access Denied IRQ Flag */
+
+/* CAN_UCCNF Masks */
+#define UCCNF           0x000F  /* Universal Counter Mode */
+#define UC_STAMP        0x0001  /*  Timestamp Mode */
+#define UC_WDOG         0x0002  /*  Watchdog Mode */
+#define UC_AUTOTX       0x0003  /*  Auto-Transmit Mode */
+#define UC_ERROR        0x0006  /*  CAN Error Frame Count */
+#define UC_OVER         0x0007  /*  CAN Overload Frame Count */
+#define UC_LOST         0x0008  /*  Arbitration Lost During TX Count */
+#define UC_AA           0x0009  /*  TX Abort Count */
+#define UC_TA           0x000A  /*  TX Successful Count */
+#define UC_REJECT       0x000B  /*  RX Message Rejected Count */
+#define UC_RML          0x000C  /*  RX Message Lost Count */
+#define UC_RX           0x000D  /*  Total Successful RX Messages Count */
+#define UC_RMP          0x000E  /*  Successful RX W/Matching ID Count */
+#define UC_ALL          0x000F  /*  Correct Message On CAN Bus Line Count */
+#define UCRC            0x0020  /* Universal Counter Reload/Clear */
+#define UCCT            0x0040  /* Universal Counter CAN Trigger */
+#define UCE                     0x0080  /* Universal Counter Enable */
+
+/* CAN_ESR Masks */
+#define ACKE            0x0004  /* Acknowledge Error */
+#define SER                     0x0008  /* Stuff Error */
+#define CRCE            0x0010  /* CRC Error */
+#define SA0                     0x0020  /* Stuck At Dominant Error */
+#define BEF                     0x0040  /* Bit Error Flag */
+#define FER                     0x0080  /* Form Error Flag */
+
+/* CAN_EWR Masks */
+#define EWLREC          0x00FF  /* RX Error Count Limit (For EWRIS) */
+#define EWLTEC          0xFF00  /* TX Error Count Limit (For EWTIS) */
+
+#endif
diff --git a/arch/blackfin/include/asm/bfin_sport.h b/arch/blackfin/include/asm/bfin_sport.h
index b558908e1c79..9626cf7e4251 100644
--- a/arch/blackfin/include/asm/bfin_sport.h
+++ b/arch/blackfin/include/asm/bfin_sport.h
@@ -1,7 +1,7 @@
 /*
- * bfin_sport.h - userspace header for bfin sport driver
+ * bfin_sport.h - interface to Blackfin SPORTs
  *
- * Copyright 2004-2008 Analog Devices Inc.
+ * Copyright 2004-2009 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -9,16 +9,6 @@
 #ifndef __BFIN_SPORT_H__
 #define __BFIN_SPORT_H__
 
-#ifdef __KERNEL__
-#include <linux/cdev.h>
-#include <linux/mutex.h>
-#include <linux/sched.h>
-#include <linux/wait.h>
-#endif
-
-#define SPORT_MAJOR     237
-#define SPORT_NR_DEVS   2
-
 /* Sport mode: it can be set to TDM, i2s or others */
 #define NORM_MODE       0x0
 #define TDM_MODE        0x1
@@ -35,7 +25,7 @@ struct sport_config {
         unsigned int mode:3;
 
         /* if TDM mode is selected, channels must be set */
-        int channels;           /* Must be in 8 units */
+        int channels;   /* Must be in 8 units */
         unsigned int frame_delay:4;     /* Delay between frame sync pulse and first bit */
 
         /* I2S mode */
@@ -69,94 +59,137 @@ struct sport_config {
 
 #ifdef __KERNEL__
 
-struct sport_register {
-        unsigned short tcr1;
-        unsigned short reserved0;
-        unsigned short tcr2;
-        unsigned short reserved1;
-        unsigned short tclkdiv;
-        unsigned short reserved2;
-        unsigned short tfsdiv;
-        unsigned short reserved3;
-        unsigned long tx;
-        unsigned long reserved_l0;
-        unsigned long rx;
-        unsigned long reserved_l1;
-        unsigned short rcr1;
-        unsigned short reserved4;
-        unsigned short rcr2;
-        unsigned short reserved5;
-        unsigned short rclkdiv;
-        unsigned short reserved6;
-        unsigned short rfsdiv;
-        unsigned short reserved7;
-        unsigned short stat;
-        unsigned short reserved8;
-        unsigned short chnl;
-        unsigned short reserved9;
-        unsigned short mcmc1;
-        unsigned short reserved10;
-        unsigned short mcmc2;
-        unsigned short reserved11;
-        unsigned long mtcs0;
-        unsigned long mtcs1;
-        unsigned long mtcs2;
-        unsigned long mtcs3;
-        unsigned long mrcs0;
-        unsigned long mrcs1;
-        unsigned long mrcs2;
-        unsigned long mrcs3;
-};
-
-struct sport_dev {
-        struct cdev cdev;       /* Char device structure */
-
-        int sport_num;
+#include <linux/types.h>
 
-        int dma_rx_chan;
-        int dma_tx_chan;
-
-        int rx_irq;
-        unsigned char *rx_buf;  /* Buffer store the received data */
-        int rx_len;             /* How many bytes will be received */
-        int rx_received;        /* How many bytes has been received */
-
-        int tx_irq;
-        const unsigned char *tx_buf;
-        int tx_len;
-        int tx_sent;
-
-        int err_irq;
-
-        struct mutex mutex;     /* mutual exclusion semaphore */
-        struct task_struct *task;
-
-        wait_queue_head_t waitq;
-        int     wait_con;
-        struct sport_register *regs;
-        struct sport_config config;
+/*
+ * All Blackfin system MMRs are padded to 32bits even if the register
+ * itself is only 16bits.  So use a helper macro to streamline this.
+ */
+#define __BFP(m) u16 m; u16 __pad_##m
+struct sport_register {
+        __BFP(tcr1);
+        __BFP(tcr2);
+        __BFP(tclkdiv);
+        __BFP(tfsdiv);
+        union {
+                u32 tx32;
+                u16 tx16;
+        };
+        u32 __pad_tx;
+        union {
+                u32 rx32;       /* use the anomaly wrapper below */
+                u16 rx16;
+        };
+        u32 __pad_rx;
+        __BFP(rcr1);
+        __BFP(rcr2);
+        __BFP(rclkdiv);
+        __BFP(rfsdiv);
+        __BFP(stat);
+        __BFP(chnl);
+        __BFP(mcmc1);
+        __BFP(mcmc2);
+        u32 mtcs0;
+        u32 mtcs1;
+        u32 mtcs2;
+        u32 mtcs3;
+        u32 mrcs0;
+        u32 mrcs1;
+        u32 mrcs2;
+        u32 mrcs3;
 };
+#undef __BFP
+
+#define bfin_read_sport_rx32(base) \
+({ \
+        struct sport_register *__mmrs = (void *)base; \
+        u32 __ret; \
+        unsigned long flags; \
+        if (ANOMALY_05000473) \
+                local_irq_save(flags); \
+        __ret = __mmrs->rx32; \
+        if (ANOMALY_05000473) \
+                local_irq_restore(flags); \
+        __ret; \
+})
 
 #endif
 
-#define SPORT_TCR1      0
-#define SPORT_TCR2      1
-#define SPORT_TCLKDIV   2
-#define SPORT_TFSDIV    3
-#define SPORT_RCR1      8
-#define SPORT_RCR2      9
-#define SPORT_RCLKDIV   10
-#define SPORT_RFSDIV    11
-#define SPORT_CHANNEL   13
-#define SPORT_MCMC1     14
-#define SPORT_MCMC2     15
-#define SPORT_MTCS0     16
-#define SPORT_MTCS1     17
-#define SPORT_MTCS2     18
-#define SPORT_MTCS3     19
-#define SPORT_MRCS0     20
-#define SPORT_MRCS1     21
-#define SPORT_MRCS2     22
-#define SPORT_MRCS3     23
+/* Workaround defBF*.h SPORT MMRs till they get cleansed */
+#undef DTYPE_NORM
+#undef SLEN
+#undef SP_WOFF
+#undef SP_WSIZE
+
+/* SPORT_TCR1 Masks */
+#define TSPEN           0x0001  /* TX enable */
+#define ITCLK           0x0002  /* Internal TX Clock Select */
+#define TDTYPE          0x000C  /* TX Data Formatting Select */
+#define DTYPE_NORM      0x0000  /* Data Format Normal */
+#define DTYPE_ULAW      0x0008  /* Compand Using u-Law */
+#define DTYPE_ALAW      0x000C  /* Compand Using A-Law */
+#define TLSBIT          0x0010  /* TX Bit Order */
+#define ITFS            0x0200  /* Internal TX Frame Sync Select */
+#define TFSR            0x0400  /* TX Frame Sync Required Select */
+#define DITFS           0x0800  /* Data Independent TX Frame Sync Select */
+#define LTFS            0x1000  /* Low TX Frame Sync Select */
+#define LATFS           0x2000  /* Late TX Frame Sync Select */
+#define TCKFE           0x4000  /* TX Clock Falling Edge Select */
+
+/* SPORT_TCR2 Masks */
+#define SLEN            0x001F  /* SPORT TX Word Length (2 - 31) */
+#define DP_SLEN(x)      BFIN_DEPOSIT(SLEN, x)
+#define EX_SLEN(x)      BFIN_EXTRACT(SLEN, x)
+#define TXSE            0x0100  /* TX Secondary Enable */
+#define TSFSE           0x0200  /* TX Stereo Frame Sync Enable */
+#define TRFST           0x0400  /* TX Right-First Data Order */
+
+/* SPORT_RCR1 Masks */
+#define RSPEN           0x0001  /* RX enable */
+#define IRCLK           0x0002  /* Internal RX Clock Select */
+#define RDTYPE          0x000C  /* RX Data Formatting Select */
+/* DTYPE_* defined above */
+#define RLSBIT          0x0010  /* RX Bit Order */
+#define IRFS            0x0200  /* Internal RX Frame Sync Select */
+#define RFSR            0x0400  /* RX Frame Sync Required Select */
+#define LRFS            0x1000  /* Low RX Frame Sync Select */
+#define LARFS           0x2000  /* Late RX Frame Sync Select */
+#define RCKFE           0x4000  /* RX Clock Falling Edge Select */
+
+/* SPORT_RCR2 Masks */
+/* SLEN defined above */
+#define RXSE            0x0100  /* RX Secondary Enable */
+#define RSFSE           0x0200  /* RX Stereo Frame Sync Enable */
+#define RRFST           0x0400  /* Right-First Data Order */
+
+/* SPORT_STAT Masks */
+#define RXNE            0x0001  /* RX FIFO Not Empty Status */
+#define RUVF            0x0002  /* RX Underflow Status */
+#define ROVF            0x0004  /* RX Overflow Status */
+#define TXF             0x0008  /* TX FIFO Full Status */
+#define TUVF            0x0010  /* TX Underflow Status */
+#define TOVF            0x0020  /* TX Overflow Status */
+#define TXHRE           0x0040  /* TX Hold Register Empty */
+
+/* SPORT_MCMC1 Masks */
+#define SP_WOFF         0x03FF  /* Multichannel Window Offset Field */
+#define DP_SP_WOFF(x)   BFIN_DEPOSIT(SP_WOFF, x)
+#define EX_SP_WOFF(x)   BFIN_EXTRACT(SP_WOFF, x)
+#define SP_WSIZE        0xF000  /* Multichannel Window Size Field */
+#define DP_SP_WSIZE(x)  BFIN_DEPOSIT(SP_WSIZE, x)
+#define EX_SP_WSIZE(x)  BFIN_EXTRACT(SP_WSIZE, x)
+
+/* SPORT_MCMC2 Masks */
+#define MCCRM           0x0003  /* Multichannel Clock Recovery Mode */
+#define REC_BYPASS      0x0000  /* Bypass Mode (No Clock Recovery) */
+#define REC_2FROM4      0x0002  /* Recover 2 MHz Clock from 4 MHz Clock */
+#define REC_8FROM16     0x0003  /* Recover 8 MHz Clock from 16 MHz Clock */
+#define MCDTXPE         0x0004  /* Multichannel DMA Transmit Packing */
+#define MCDRXPE         0x0008  /* Multichannel DMA Receive Packing */
+#define MCMEN           0x0010  /* Multichannel Frame Mode Enable */
+#define FSDR            0x0080  /* Multichannel Frame Sync to Data Relationship */
+#define MFD             0xF000  /* Multichannel Frame Delay */
+#define DP_MFD(x)       BFIN_DEPOSIT(MFD, x)
+#define EX_MFD(x)       BFIN_EXTRACT(MFD, x)
 
 #endif
diff --git a/arch/blackfin/include/asm/bfin_watchdog.h b/arch/blackfin/include/asm/bfin_watchdog.h
new file mode 100644
index 000000000000..dce09829a095
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_watchdog.h
@@ -0,0 +1,30 @@
+/*
+ * bfin_watchdog.h - Blackfin watchdog definitions
+ *
+ * Copyright 2006-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _BFIN_WATCHDOG_H
+#define _BFIN_WATCHDOG_H
+
+/* Bit in SWRST that indicates boot caused by watchdog */
+#define SWRST_RESET_WDOG 0x4000
+
+/* Bit in WDOG_CTL that indicates watchdog has expired (WDR0) */
+#define WDOG_EXPIRED 0x8000
+
+/* Masks for WDEV field in WDOG_CTL register */
+#define ICTL_RESET   0x0
+#define ICTL_NMI     0x2
+#define ICTL_GPI     0x4
+#define ICTL_NONE    0x6
+#define ICTL_MASK    0x6
+
+/* Masks for WDEN field in WDOG_CTL register */
+#define WDEN_MASK    0x0FF0
+#define WDEN_ENABLE  0x0000
+#define WDEN_DISABLE 0x0AD0
+
+#endif
diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h
index a2ff3fb3568d..605ba8e9b2e4 100644
--- a/arch/blackfin/include/asm/bitops.h
+++ b/arch/blackfin/include/asm/bitops.h
@@ -7,22 +7,41 @@
 #ifndef _BLACKFIN_BITOPS_H
 #define _BLACKFIN_BITOPS_H
 
-#ifndef CONFIG_SMP
-# include <asm-generic/bitops.h>
-#else
+#include <linux/compiler.h>
+
+#include <asm-generic/bitops/__ffs.h>
+#include <asm-generic/bitops/ffz.h>
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/find.h>
 
 #ifndef _LINUX_BITOPS_H
 #error only <linux/bitops.h> can be included directly
 #endif
 
-#include <linux/compiler.h>
-#include <asm/byteorder.h>      /* swab32 */
-
-#include <asm-generic/bitops/ffs.h>
-#include <asm-generic/bitops/__ffs.h>
 #include <asm-generic/bitops/sched.h>
-#include <asm-generic/bitops/ffz.h>
+#include <asm-generic/bitops/ffs.h>
+#include <asm-generic/bitops/lock.h>
+#include <asm-generic/bitops/ext2-non-atomic.h>
+#include <asm-generic/bitops/ext2-atomic.h>
+#include <asm-generic/bitops/minix.h>
+
+#ifndef CONFIG_SMP
+#include <linux/irqflags.h>
+
+/*
+ * clear_bit may not imply a memory barrier
+ */
+#ifndef smp_mb__before_clear_bit
+#define smp_mb__before_clear_bit()      smp_mb()
+#define smp_mb__after_clear_bit()       smp_mb()
+#endif
+#include <asm-generic/bitops/atomic.h>
+#include <asm-generic/bitops/non-atomic.h>
+#else
 
+#include <asm/byteorder.h>      /* swab32 */
 #include <linux/linkage.h>
 
 asmlinkage int __raw_bit_set_asm(volatile unsigned long *addr, int nr);
@@ -89,19 +108,36 @@ static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
 
 #include <asm-generic/bitops/non-atomic.h>
 
-#include <asm-generic/bitops/find.h>
-#include <asm-generic/bitops/hweight.h>
-#include <asm-generic/bitops/lock.h>
+#endif /* CONFIG_SMP */
 
-#include <asm-generic/bitops/ext2-atomic.h>
-#include <asm-generic/bitops/ext2-non-atomic.h>
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
 
-#include <asm-generic/bitops/minix.h>
+static inline unsigned int hweight32(unsigned int w)
+{
+        unsigned int res;
 
-#include <asm-generic/bitops/fls.h>
-#include <asm-generic/bitops/__fls.h>
-#include <asm-generic/bitops/fls64.h>
+        __asm__ ("%0.l = ONES %0;"
+                "%0 = %0.l (Z);"
+                : "=d" (res) : "d" (w));
+        return res;
+}
 
-#endif /* CONFIG_SMP */
+static inline unsigned int hweight64(__u64 w)
+{
+        return hweight32((unsigned int)(w >> 32)) + hweight32((unsigned int)w);
+}
+
+static inline unsigned int hweight16(unsigned int w)
+{
+        return hweight32(w & 0xffff);
+}
+
+static inline unsigned int hweight8(unsigned int w)
+{
+        return hweight32(w & 0xff);
+}
 
 #endif                          /* _BLACKFIN_BITOPS_H */
diff --git a/arch/blackfin/include/asm/bug.h b/arch/blackfin/include/asm/bug.h
index 6f4548a13555..75f6dc336d46 100644
--- a/arch/blackfin/include/asm/bug.h
+++ b/arch/blackfin/include/asm/bug.h
@@ -47,7 +47,7 @@
 #define BUG()                                                           \
         do {                                                            \
                 _BUG_OR_WARN(0);                                        \
-                for (;;);                                               \
+                unreachable();                                          \
         } while (0)
 
 #define WARN_ON(condition)                                                      \
diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h
index af03a36c7a4e..2666ff8ea952 100644
--- a/arch/blackfin/include/asm/cacheflush.h
+++ b/arch/blackfin/include/asm/cacheflush.h
@@ -10,6 +10,7 @@
 #define _BLACKFIN_CACHEFLUSH_H
 
 #include <asm/blackfin.h>       /* for SSYNC() */
+#include <asm/sections.h>       /* for _ramend */
 
 extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address);
 extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address);
@@ -68,9 +69,11 @@ do { memcpy(dst, src, len);						\
 #endif
 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
 # define flush_dcache_range(start,end)          blackfin_dcache_flush_range((start), (end))
+#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
 # define flush_dcache_page(page)                blackfin_dflush_page(page_address(page))
 #else
 # define flush_dcache_range(start,end)          do { } while (0)
+#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
 # define flush_dcache_page(page)                do { } while (0)
 #endif
 
diff --git a/arch/blackfin/include/asm/checksum.h b/arch/blackfin/include/asm/checksum.h
index a23415be0de1..623cc7fb00bc 100644
--- a/arch/blackfin/include/asm/checksum.h
+++ b/arch/blackfin/include/asm/checksum.h
@@ -9,63 +9,12 @@
 #define _BFIN_CHECKSUM_H
 
 /*
- * computes the checksum of a memory block at buff, length len,
- * and adds in "sum" (32-bit)
- *
- * returns a 32-bit number suitable for feeding into itself
- * or csum_tcpudp_magic
- *
- * this function must be called with even lengths, except
- * for the last fragment, which may be odd
- *
- * it's best to have buff aligned on a 32-bit boundary
- */
-__wsum csum_partial(const void *buff, int len, __wsum sum);
-
-/*
- * the same as csum_partial, but copies from src while it
- * checksums
- *
- * here even more important to align src and dst on a 32-bit (or even
- * better 64-bit) boundary
- */
-
-__wsum csum_partial_copy(const void *src, void *dst,
-                               int len, __wsum sum);
-
-/*
- * the same as csum_partial_copy, but copies from user space.
- *
- * here even more important to align src and dst on a 32-bit (or even
- * better 64-bit) boundary
- */
-
-extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst,
-                                          int len, __wsum sum, int *csum_err);
-
-#define csum_partial_copy_nocheck(src, dst, len, sum)   \
-        csum_partial_copy((src), (dst), (len), (sum))
-
-__sum16 ip_fast_csum(unsigned char *iph, unsigned int ihl);
-
-/*
- *      Fold a partial checksum
- */
-
-static inline __sum16 csum_fold(__wsum sum)
-{
-        while (sum >> 16)
-                sum = (sum & 0xffff) + (sum >> 16);
-        return ((~(sum << 16)) >> 16);
-}
-
-/*
  * computes the checksum of the TCP/UDP pseudo-header
  * returns a 16-bit checksum, already complemented
  */
 
 static inline __wsum
-csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
+__csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
                    unsigned short proto, __wsum sum)
 {
         unsigned int carry;
@@ -88,19 +37,8 @@ csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
 
         return (sum);
 }
+#define csum_tcpudp_nofold __csum_tcpudp_nofold
 
-static inline __sum16
-csum_tcpudp_magic(__be32 saddr, __be32 daddr, unsigned short len,
-                  unsigned short proto, __wsum sum)
-{
-        return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum));
-}
-
-/*
- * this routine is used for miscellaneous IP-like checksums, mainly
- * in icmp.c
- */
-
-extern __sum16 ip_compute_csum(const void *buff, int len);
+#include <asm-generic/checksum.h>
 
-#endif                          /* _BFIN_CHECKSUM_H */
+#endif
diff --git a/arch/blackfin/include/asm/clocks.h b/arch/blackfin/include/asm/clocks.h
index f80dad5ff257..6f0b61852f58 100644
--- a/arch/blackfin/include/asm/clocks.h
+++ b/arch/blackfin/include/asm/clocks.h
@@ -9,6 +9,8 @@
 #ifndef _BFIN_CLOCKS_H
 #define _BFIN_CLOCKS_H
 
+#include <asm/dpmc.h>
+
 #ifdef CONFIG_CCLK_DIV_1
 # define CONFIG_CCLK_ACT_DIV   CCLK_DIV1
 # define CONFIG_CCLK_DIV 1
diff --git a/arch/blackfin/include/asm/context.S b/arch/blackfin/include/asm/context.S
index 5dffaf582a22..1f9060395a0a 100644
--- a/arch/blackfin/include/asm/context.S
+++ b/arch/blackfin/include/asm/context.S
@@ -73,6 +73,11 @@
 #else
         cli r0;
 #endif
+#ifdef CONFIG_TRACE_IRQFLAGS
+        sp += -12;
+        call _trace_hardirqs_off;
+        sp += 12;
+#endif
         [--sp] = RETI;  /*orig_pc*/
         /* Clear all L registers.  */
         r0 = 0 (x);
@@ -279,6 +284,13 @@
         RETN = [sp++];
         RETX = [sp++];
         RETI = [sp++];
+
+#ifdef CONFIG_TRACE_IRQFLAGS
+        sp += -12;
+        call _trace_hardirqs_on;
+        sp += 12;
+#endif
+
         RETS = [sp++];
 
 #ifdef CONFIG_SMP
@@ -374,3 +386,13 @@
 
         (R7:0, P5:0) = [SP++];
 .endm
+
+.macro pseudo_long_call func:req, scratch:req
+#ifdef CONFIG_ROMKERNEL
+        \scratch\().l = \func;
+        \scratch\().h = \func;
+        call (\scratch);
+#else
+        call \func;
+#endif
+.endm
diff --git a/arch/blackfin/include/asm/cpu.h b/arch/blackfin/include/asm/cpu.h
index b191dc662bd8..16883e582e3c 100644
--- a/arch/blackfin/include/asm/cpu.h
+++ b/arch/blackfin/include/asm/cpu.h
@@ -17,8 +17,6 @@ struct blackfin_cpudata {
         struct task_struct *idle;
         unsigned int imemctl;
         unsigned int dmemctl;
-        unsigned long dcache_invld_count;
-        unsigned long icache_invld_count;
 };
 
 DECLARE_PER_CPU(struct blackfin_cpudata, cpu_data);
diff --git a/arch/blackfin/include/asm/def_LPBlackfin.h b/arch/blackfin/include/asm/def_LPBlackfin.h
index 25906468622f..f342ff0319df 100644
--- a/arch/blackfin/include/asm/def_LPBlackfin.h
+++ b/arch/blackfin/include/asm/def_LPBlackfin.h
@@ -12,6 +12,8 @@
 #include <mach/anomaly.h>
 
 #define MK_BMSK_(x) (1<<x)
+#define BFIN_DEPOSIT(mask, x)   (((x) << __ffs(mask)) & (mask))
+#define BFIN_EXTRACT(mask, x)   (((x) & (mask)) >> __ffs(mask))
 
 #ifndef __ASSEMBLY__
 
@@ -23,62 +25,30 @@
 # define NOP_PAD_ANOMALY_05000198
 #endif
 
-#define bfin_read8(addr) ({ \
-        uint32_t __v; \
+#define _bfin_readX(addr, size, asm_size, asm_ext) ({ \
+        u32 __v; \
         __asm__ __volatile__( \
                 NOP_PAD_ANOMALY_05000198 \
-                "%0 = b[%1] (z);" \
+                "%0 = " #asm_size "[%1]" #asm_ext ";" \
                 : "=d" (__v) \
                 : "a" (addr) \
         ); \
         __v; })
-
-#define bfin_read16(addr) ({ \
-        uint32_t __v; \
-        __asm__ __volatile__( \
-                NOP_PAD_ANOMALY_05000198 \
-                "%0 = w[%1] (z);" \
-                : "=d" (__v) \
-                : "a" (addr) \
-        ); \
-        __v; })
-
-#define bfin_read32(addr) ({ \
-        uint32_t __v; \
-        __asm__ __volatile__( \
-                NOP_PAD_ANOMALY_05000198 \
-                "%0 = [%1];" \
-                : "=d" (__v) \
-                : "a" (addr) \
-        ); \
-        __v; })
-
-#define bfin_write8(addr, val) \
+#define _bfin_writeX(addr, val, size, asm_size) \
         __asm__ __volatile__( \
                 NOP_PAD_ANOMALY_05000198 \
-                "b[%0] = %1;" \
+                #asm_size "[%0] = %1;" \
                 : \
-                : "a" (addr), "d" ((uint8_t)(val)) \
+                : "a" (addr), "d" ((u##size)(val)) \
                 : "memory" \
         )
 
-#define bfin_write16(addr, val) \
-        __asm__ __volatile__( \
-                NOP_PAD_ANOMALY_05000198 \
-                "w[%0] = %1;" \
-                : \
-                : "a" (addr), "d" ((uint16_t)(val)) \
-                : "memory" \
-        )
-
-#define bfin_write32(addr, val) \
-        __asm__ __volatile__( \
-                NOP_PAD_ANOMALY_05000198 \
-                "[%0] = %1;" \
-                : \
-                : "a" (addr), "d" (val) \
-                : "memory" \
-        )
+#define bfin_read8(addr)  _bfin_readX(addr,  8, b, (z))
+#define bfin_read16(addr) _bfin_readX(addr, 16, w, (z))
+#define bfin_read32(addr) _bfin_readX(addr, 32,  ,    )
+#define bfin_write8(addr, val)  _bfin_writeX(addr, val,  8, b)
+#define bfin_write16(addr, val) _bfin_writeX(addr, val, 16, w)
+#define bfin_write32(addr, val) _bfin_writeX(addr, val, 32,  )
 
 #endif /* __ASSEMBLY__ */
 
diff --git a/arch/blackfin/include/asm/delay.h b/arch/blackfin/include/asm/delay.h
index c31f91cc1d5d..171d8deb04a5 100644
--- a/arch/blackfin/include/asm/delay.h
+++ b/arch/blackfin/include/asm/delay.h
@@ -30,10 +30,22 @@ __asm__ __volatile__ (
 
 #define HZSCALE         (268435456 / (1000000/HZ))
 
-static inline void udelay(unsigned long usecs)
+static inline unsigned long __to_delay(unsigned long scale)
 {
         extern unsigned long loops_per_jiffy;
-        __delay((((usecs * HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6);
+        return (((scale * HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6;
+}
+
+static inline void udelay(unsigned long usecs)
+{
+        __delay(__to_delay(usecs));
 }
 
+static inline void ndelay(unsigned long nsecs)
+{
+        __delay(__to_delay(1) * nsecs / 1000);
+}
+
+#define ndelay ndelay
+
 #endif
diff --git a/arch/blackfin/include/asm/dma-mapping.h b/arch/blackfin/include/asm/dma-mapping.h
index 7a23d824ac96..212cb80fd74b 100644
--- a/arch/blackfin/include/asm/dma-mapping.h
+++ b/arch/blackfin/include/asm/dma-mapping.h
@@ -7,9 +7,9 @@
 #ifndef _BLACKFIN_DMA_MAPPING_H
 #define _BLACKFIN_DMA_MAPPING_H
 
-#include <asm/scatterlist.h>
+#include <asm/cacheflush.h>
+struct scatterlist;
 
-void dma_alloc_init(unsigned long start, unsigned long end);
 void *dma_alloc_coherent(struct device *dev, size_t size,
                          dma_addr_t *dma_handle, gfp_t gfp);
 void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
@@ -20,22 +20,61 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
  */
 #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
 #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
+#define dma_supported(d, m)         (1)
+#define dma_get_cache_alignment()   (32)
+#define dma_is_consistent(d, h)     (1)
 
-static inline
-int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
+static inline int
+dma_set_mask(struct device *dev, u64 dma_mask)
 {
+        if (!dev->dma_mask || !dma_supported(dev, dma_mask))
+                return -EIO;
+
+        *dev->dma_mask = dma_mask;
+
         return 0;
 }
 
-/*
- * Map a single buffer of the indicated size for DMA in streaming mode.
- * The 32-bit bus address to use is returned.
- *
- * Once the device is given the dma address, the device owns this memory
- * until either pci_unmap_single or pci_dma_sync_single is performed.
- */
-extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
-                                 enum dma_data_direction direction);
+static inline int
+dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
+{
+        return 0;
+}
+
+extern void
+__dma_sync(dma_addr_t addr, size_t size, enum dma_data_direction dir);
+static inline void
+__dma_sync_inline(dma_addr_t addr, size_t size, enum dma_data_direction dir)
+{
+        switch (dir) {
+        case DMA_NONE:
+                BUG();
+        case DMA_TO_DEVICE:             /* writeback only */
+                flush_dcache_range(addr, addr + size);
+                break;
+        case DMA_FROM_DEVICE: /* invalidate only */
+        case DMA_BIDIRECTIONAL: /* flush and invalidate */
+                /* Blackfin has no dedicated invalidate (it includes a flush) */
+                invalidate_dcache_range(addr, addr + size);
+                break;
+        }
+}
+static inline void
+_dma_sync(dma_addr_t addr, size_t size, enum dma_data_direction dir)
+{
+        if (__builtin_constant_p(dir))
+                __dma_sync_inline(addr, size, dir);
+        else
+                __dma_sync(addr, size, dir);
+}
+
+static inline dma_addr_t
+dma_map_single(struct device *dev, void *ptr, size_t size,
+               enum dma_data_direction dir)
+{
+        _dma_sync((dma_addr_t)ptr, size, dir);
+        return (dma_addr_t) ptr;
+}
 
 static inline dma_addr_t
 dma_map_page(struct device *dev, struct page *page,
@@ -45,16 +84,12 @@ dma_map_page(struct device *dev, struct page *page,
         return dma_map_single(dev, page_address(page) + offset, size, dir);
 }
 
-/*
- * Unmap a single streaming mode DMA translation.  The dma_addr and size
- * must match what was provided for in a previous pci_map_single call.  All
- * other usages are undefined.
- *
- * After this call, reads by the cpu to the buffer are guarenteed to see
- * whatever the device wrote there.
- */
-extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
-                          enum dma_data_direction direction);
+static inline void
+dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
+                 enum dma_data_direction dir)
+{
+        BUG_ON(!valid_dma_direction(dir));
+}
 
 static inline void
 dma_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
@@ -63,55 +98,62 @@ dma_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
         dma_unmap_single(dev, dma_addr, size, dir);
 }
 
-/*
- * Map a set of buffers described by scatterlist in streaming
- * mode for DMA.  This is the scather-gather version of the
- * above pci_map_single interface.  Here the scatter gather list
- * elements are each tagged with the appropriate dma address
- * and length.  They are obtained via sg_dma_{address,length}(SG).
- *
- * NOTE: An implementation may be able to use a smaller number of
- *       DMA address/length pairs than there are SG table elements.
- *       (for example via virtual mapping capabilities)
- *       The routine returns the number of addr/length pairs actually
- *       used, at most nents.
- *
- * Device ownership issues as mentioned above for pci_map_single are
- * the same here.
- */
 extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
-                      enum dma_data_direction direction);
+                      enum dma_data_direction dir);
 
-/*
- * Unmap a set of streaming mode DMA translations.
- * Again, cpu read rules concerning calls here are the same as for
- * pci_unmap_single() above.
- */
-extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
-                      int nhwentries, enum dma_data_direction direction);
+static inline void
+dma_unmap_sg(struct device *dev, struct scatterlist *sg,
+             int nhwentries, enum dma_data_direction dir)
+{
+        BUG_ON(!valid_dma_direction(dir));
+}
+
+static inline void
+dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t handle,
+                              unsigned long offset, size_t size,
+                              enum dma_data_direction dir)
+{
+        BUG_ON(!valid_dma_direction(dir));
+}
+
+static inline void
+dma_sync_single_range_for_device(struct device *dev, dma_addr_t handle,
+                                 unsigned long offset, size_t size,
+                                 enum dma_data_direction dir)
+{
+        _dma_sync(handle + offset, size, dir);
+}
 
-static inline void dma_sync_single_for_cpu(struct device *dev,
-                                        dma_addr_t handle, size_t size,
-                                        enum dma_data_direction dir)
+static inline void
+dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle, size_t size,
+                        enum dma_data_direction dir)
 {
+        dma_sync_single_range_for_cpu(dev, handle, 0, size, dir);
 }
 
-static inline void dma_sync_single_for_device(struct device *dev,
-                                        dma_addr_t handle, size_t size,
-                                        enum dma_data_direction dir)
+static inline void
+dma_sync_single_for_device(struct device *dev, dma_addr_t handle, size_t size,
+                           enum dma_data_direction dir)
 {
+        dma_sync_single_range_for_device(dev, handle, 0, size, dir);
 }
 
-static inline void dma_sync_sg_for_cpu(struct device *dev,
-                                        struct scatterlist *sg,
-                                        int nents, enum dma_data_direction dir)
+static inline void
+dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nents,
+                    enum dma_data_direction dir)
 {
+        BUG_ON(!valid_dma_direction(dir));
 }
 
-static inline void dma_sync_sg_for_device(struct device *dev,
-                                        struct scatterlist *sg,
-                                        int nents, enum dma_data_direction dir)
+extern void
+dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
+                       int nents, enum dma_data_direction dir);
+
+static inline void
+dma_cache_sync(struct device *dev, void *vaddr, size_t size,
+               enum dma_data_direction dir)
 {
+        _dma_sync((dma_addr_t)vaddr, size, dir);
 }
 
 #endif                          /* _BLACKFIN_DMA_MAPPING_H */
diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h
index c9a59622e23f..2c09b1d50ec9 100644
--- a/arch/blackfin/include/asm/dma.h
+++ b/arch/blackfin/include/asm/dma.h
@@ -10,46 +10,70 @@
 
 #include <linux/interrupt.h>
 #include <mach/dma.h>
+#include <asm/atomic.h>
 #include <asm/blackfin.h>
 #include <asm/page.h>
-
-#define MAX_DMA_ADDRESS PAGE_OFFSET
-
-/*****************************************************************************
-*        Generic DMA  Declarations
-*
-****************************************************************************/
-enum dma_chan_status {
-        DMA_CHANNEL_FREE,
-        DMA_CHANNEL_REQUESTED,
-        DMA_CHANNEL_ENABLED,
-};
+#include <asm-generic/dma.h>
+
+/* DMA_CONFIG Masks */
+#define DMAEN                   0x0001  /* DMA Channel Enable */
+#define WNR                             0x0002  /* Channel Direction (W/R*) */
+#define WDSIZE_8                0x0000  /* Transfer Word Size = 8 */
+#define WDSIZE_16               0x0004  /* Transfer Word Size = 16 */
+#define WDSIZE_32               0x0008  /* Transfer Word Size = 32 */
+#define DMA2D                   0x0010  /* DMA Mode (2D/1D*) */
+#define RESTART                 0x0020  /* DMA Buffer Clear */
+#define DI_SEL                  0x0040  /* Data Interrupt Timing Select */
+#define DI_EN                   0x0080  /* Data Interrupt Enable */
+#define NDSIZE_0                0x0000  /* Next Descriptor Size = 0 (Stop/Autobuffer) */
+#define NDSIZE_1                0x0100  /* Next Descriptor Size = 1 */
+#define NDSIZE_2                0x0200  /* Next Descriptor Size = 2 */
+#define NDSIZE_3                0x0300  /* Next Descriptor Size = 3 */
+#define NDSIZE_4                0x0400  /* Next Descriptor Size = 4 */
+#define NDSIZE_5                0x0500  /* Next Descriptor Size = 5 */
+#define NDSIZE_6                0x0600  /* Next Descriptor Size = 6 */
+#define NDSIZE_7                0x0700  /* Next Descriptor Size = 7 */
+#define NDSIZE_8                0x0800  /* Next Descriptor Size = 8 */
+#define NDSIZE_9                0x0900  /* Next Descriptor Size = 9 */
+#define NDSIZE                  0x0f00  /* Next Descriptor Size */
+#define DMAFLOW                 0x7000  /* Flow Control */
+#define DMAFLOW_STOP    0x0000  /* Stop Mode */
+#define DMAFLOW_AUTO    0x1000  /* Autobuffer Mode */
+#define DMAFLOW_ARRAY   0x4000  /* Descriptor Array Mode */
+#define DMAFLOW_SMALL   0x6000  /* Small Model Descriptor List Mode */
+#define DMAFLOW_LARGE   0x7000  /* Large Model Descriptor List Mode */
+
+/* DMA_IRQ_STATUS Masks */
+#define DMA_DONE                0x0001  /* DMA Completion Interrupt Status */
+#define DMA_ERR                 0x0002  /* DMA Error Interrupt Status */
+#define DFETCH                  0x0004  /* DMA Descriptor Fetch Indicator */
+#define DMA_RUN                 0x0008  /* DMA Channel Running Indicator */
 
 /*-------------------------
  * config reg bits value
  *-------------------------*/
-#define DATA_SIZE_8             0
-#define DATA_SIZE_16            1
-#define DATA_SIZE_32            2
+#define DATA_SIZE_8                     0
+#define DATA_SIZE_16            1
+#define DATA_SIZE_32            2
 
-#define DMA_FLOW_STOP           0
-#define DMA_FLOW_AUTO           1
-#define DMA_FLOW_ARRAY          4
-#define DMA_FLOW_SMALL          6
-#define DMA_FLOW_LARGE          7
+#define DMA_FLOW_STOP           0
+#define DMA_FLOW_AUTO           1
+#define DMA_FLOW_ARRAY          4
+#define DMA_FLOW_SMALL          6
+#define DMA_FLOW_LARGE          7
 
-#define DIMENSION_LINEAR    0
-#define DIMENSION_2D           1
+#define DIMENSION_LINEAR        0
+#define DIMENSION_2D            1
 
-#define DIR_READ     0
-#define DIR_WRITE    1
+#define DIR_READ                        0
+#define DIR_WRITE                       1
 
-#define INTR_DISABLE   0
-#define INTR_ON_BUF    2
-#define INTR_ON_ROW    3
+#define INTR_DISABLE            0
+#define INTR_ON_BUF                     2
+#define INTR_ON_ROW                     3
 
 #define DMA_NOSYNC_KEEP_DMA_BUF 0
-#define DMA_SYNC_RESTART        1
+#define DMA_SYNC_RESTART                1
 
 struct dmasg {
         void *next_desc_addr;
@@ -104,11 +128,9 @@ struct dma_register {
 
 };
 
-struct mutex;
 struct dma_channel {
-        struct mutex dmalock;
         const char *device_id;
-        enum dma_chan_status chan_status;
+        atomic_t chan_status;
         volatile struct dma_register *regs;
         struct dmasg *sg;               /* large mode descriptor */
         unsigned int irq;
@@ -220,33 +242,30 @@ static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize
 
 static inline int dma_channel_active(unsigned int channel)
 {
-        if (dma_ch[channel].chan_status == DMA_CHANNEL_FREE)
-                return 0;
-        else
-                return 1;
+        return atomic_read(&dma_ch[channel].chan_status);
 }
 
 static inline void disable_dma(unsigned int channel)
 {
         dma_ch[channel].regs->cfg &= ~DMAEN;
         SSYNC();
-        dma_ch[channel].chan_status = DMA_CHANNEL_REQUESTED;
 }
 static inline void enable_dma(unsigned int channel)
 {
         dma_ch[channel].regs->curr_x_count = 0;
         dma_ch[channel].regs->curr_y_count = 0;
         dma_ch[channel].regs->cfg |= DMAEN;
-        dma_ch[channel].chan_status = DMA_CHANNEL_ENABLED;
 }
-void free_dma(unsigned int channel);
-int request_dma(unsigned int channel, const char *device_id);
 int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data);
 
 static inline void dma_disable_irq(unsigned int channel)
 {
         disable_irq(dma_ch[channel].irq);
 }
+static inline void dma_disable_irq_nosync(unsigned int channel)
+{
+        disable_irq_nosync(dma_ch[channel].irq);
+}
 static inline void dma_enable_irq(unsigned int channel)
 {
         enable_irq(dma_ch[channel].irq);
diff --git a/arch/blackfin/include/asm/dpmc.h b/arch/blackfin/include/asm/dpmc.h
index 925e66cb2d49..efcc3aebeae4 100644
--- a/arch/blackfin/include/asm/dpmc.h
+++ b/arch/blackfin/include/asm/dpmc.h
@@ -1,7 +1,7 @@
 /*
  * Miscellaneous IOCTL commands for Dynamic Power Management Controller Driver
  *
- * Copyright (C) 2004-2008 Analog Device Inc.
+ * Copyright (C) 2004-2009 Analog Device Inc.
  *
  * Licensed under the GPL-2
  */
@@ -9,7 +9,109 @@
 #ifndef _BLACKFIN_DPMC_H_
 #define _BLACKFIN_DPMC_H_
 
-#ifdef __KERNEL__
+/* PLL_CTL Masks */
+#define DF                      0x0001  /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
+#define PLL_OFF                 0x0002  /* PLL Not Powered */
+#define STOPCK                  0x0008  /* Core Clock Off */
+#define PDWN                    0x0020  /* Enter Deep Sleep Mode */
+#ifdef __ADSPBF539__
+# define IN_DELAY               0x0014  /* Add 200ps Delay To EBIU Input Latches */
+# define OUT_DELAY              0x00C0  /* Add 200ps Delay To EBIU Output Signals */
+#else
+# define IN_DELAY               0x0040  /* Add 200ps Delay To EBIU Input Latches */
+# define OUT_DELAY              0x0080  /* Add 200ps Delay To EBIU Output Signals */
+#endif
+#define BYPASS                  0x0100  /* Bypass the PLL */
+#define MSEL                    0x7E00  /* Multiplier Select For CCLK/VCO Factors */
+#define SPORT_HYST              0x8000  /* Enable Additional Hysteresis on SPORT Input Pins */
+#define SET_MSEL(x)             (((x)&0x3F) << 0x9)     /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
+
+/* PLL_DIV Masks */
+#define SSEL                    0x000F  /* System Select */
+#define CSEL                    0x0030  /* Core Select */
+#define CSEL_DIV1               0x0000  /* CCLK = VCO / 1 */
+#define CSEL_DIV2               0x0010  /* CCLK = VCO / 2 */
+#define CSEL_DIV4               0x0020  /* CCLK = VCO / 4 */
+#define CSEL_DIV8               0x0030  /* CCLK = VCO / 8 */
+
+#define CCLK_DIV1 CSEL_DIV1
+#define CCLK_DIV2 CSEL_DIV2
+#define CCLK_DIV4 CSEL_DIV4
+#define CCLK_DIV8 CSEL_DIV8
+
+#define SET_SSEL(x)     ((x) & 0xF)     /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
+#define SCLK_DIV(x)     (x)             /* SCLK = VCO / x */
+
+/* PLL_STAT Masks */
+#define ACTIVE_PLLENABLED       0x0001  /* Processor In Active Mode With PLL Enabled */
+#define FULL_ON                 0x0002  /* Processor In Full On Mode */
+#define ACTIVE_PLLDISABLED      0x0004  /* Processor In Active Mode With PLL Disabled */
+#define PLL_LOCKED              0x0020  /* PLL_LOCKCNT Has Been Reached */
+
+#define RTCWS                   0x0400  /* RTC/Reset Wake-Up Status */
+#define CANWS                   0x0800  /* CAN Wake-Up Status */
+#define USBWS                   0x2000  /* USB Wake-Up Status */
+#define KPADWS                  0x4000  /* Keypad Wake-Up Status */
+#define ROTWS                   0x8000  /* Rotary Wake-Up Status */
+#define GPWS                    0x1000  /* General-Purpose Wake-Up Status */
+
+/* VR_CTL Masks */
+#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
+#define FREQ                    0x3000  /* Switching Oscillator Frequency For Regulator */
+#define FREQ_1000               0x3000  /* Switching Frequency Is 1 MHz */
+#else
+#define FREQ                    0x0003  /* Switching Oscillator Frequency For Regulator */
+#define FREQ_333                0x0001  /* Switching Frequency Is 333 kHz */
+#define FREQ_667                0x0002  /* Switching Frequency Is 667 kHz */
+#define FREQ_1000               0x0003  /* Switching Frequency Is 1 MHz */
+#endif
+#define HIBERNATE               0x0000  /* Powerdown/Bypass On-Board Regulation */
+
+#define GAIN                    0x000C  /* Voltage Level Gain */
+#define GAIN_5                  0x0000  /* GAIN = 5 */
+#define GAIN_10                 0x0004  /* GAIN = 1 */
+#define GAIN_20                 0x0008  /* GAIN = 2 */
+#define GAIN_50                 0x000C  /* GAIN = 5 */
+
+#define VLEV                    0x00F0  /* Internal Voltage Level */
+#ifdef __ADSPBF52x__
+#define VLEV_085                0x0040  /* VLEV = 0.85 V (-5% - +10% Accuracy) */
+#define VLEV_090                0x0050  /* VLEV = 0.90 V (-5% - +10% Accuracy) */
+#define VLEV_095                0x0060  /* VLEV = 0.95 V (-5% - +10% Accuracy) */
+#define VLEV_100                0x0070  /* VLEV = 1.00 V (-5% - +10% Accuracy) */
+#define VLEV_105                0x0080  /* VLEV = 1.05 V (-5% - +10% Accuracy) */
+#define VLEV_110                0x0090  /* VLEV = 1.10 V (-5% - +10% Accuracy) */
+#define VLEV_115                0x00A0  /* VLEV = 1.15 V (-5% - +10% Accuracy) */
+#define VLEV_120                0x00B0  /* VLEV = 1.20 V (-5% - +10% Accuracy) */
+#else
+#define VLEV_085                0x0060  /* VLEV = 0.85 V (-5% - +10% Accuracy) */
+#define VLEV_090                0x0070  /* VLEV = 0.90 V (-5% - +10% Accuracy) */
+#define VLEV_095                0x0080  /* VLEV = 0.95 V (-5% - +10% Accuracy) */
+#define VLEV_100                0x0090  /* VLEV = 1.00 V (-5% - +10% Accuracy) */
+#define VLEV_105                0x00A0  /* VLEV = 1.05 V (-5% - +10% Accuracy) */
+#define VLEV_110                0x00B0  /* VLEV = 1.10 V (-5% - +10% Accuracy) */
+#define VLEV_115                0x00C0  /* VLEV = 1.15 V (-5% - +10% Accuracy) */
+#define VLEV_120                0x00D0  /* VLEV = 1.20 V (-5% - +10% Accuracy) */
+#define VLEV_125                0x00E0  /* VLEV = 1.25 V (-5% - +10% Accuracy) */
+#define VLEV_130                0x00F0  /* VLEV = 1.30 V (-5% - +10% Accuracy) */
+#endif
+
+#define WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate */
+#define CANWE                   0x0200  /* Enable CAN Wakeup From Hibernate */
+#define PHYWE                   0x0400  /* Enable PHY Wakeup From Hibernate */
+#define GPWE                    0x0400  /* General-Purpose Wake-Up Enable */
+#define MXVRWE                  0x0400  /* Enable MXVR Wakeup From Hibernate */
+#define KPADWE                  0x1000  /* Keypad Wake-Up Enable */
+#define ROTWE                   0x2000  /* Rotary Wake-Up Enable */
+#define CLKBUFOE                0x4000  /* CLKIN Buffer Output Enable */
+#define SCKELOW                 0x8000  /* Do Not Drive SCKE High During Reset After Hibernate */
+
+#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
+#define USBWE                   0x0200  /* Enable USB Wakeup From Hibernate */
+#else
+#define USBWE                   0x0800  /* Enable USB Wakeup From Hibernate */
+#endif
+
 #ifndef __ASSEMBLY__
 
 void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
@@ -54,6 +156,5 @@ struct bfin_dpmc_platform_data {
         w[P0 + (x - PLL_CTL)] = R0;\
 
 #endif
-#endif  /* __KERNEL__ */
 
 #endif  /*_BLACKFIN_DPMC_H_*/
diff --git a/arch/blackfin/include/asm/elf.h b/arch/blackfin/include/asm/elf.h
index 8e0764c81eaf..117713adea7f 100644
--- a/arch/blackfin/include/asm/elf.h
+++ b/arch/blackfin/include/asm/elf.h
@@ -22,12 +22,15 @@
 #define EF_BFIN_CODE_IN_L2      0x00000040      /* --code-in-l2 */
 #define EF_BFIN_DATA_IN_L2      0x00000080      /* --data-in-l2 */
 
+#if 1   /* core dumps not supported, but linux/elfcore.h needs these */
 typedef unsigned long elf_greg_t;
 
-#define ELF_NGREG 40 /* (sizeof(struct user_regs_struct) / sizeof(elf_greg_t)) */
+#define ELF_NGREG (sizeof(struct pt_regs) / sizeof(elf_greg_t))
 typedef elf_greg_t elf_gregset_t[ELF_NGREG];
 
 typedef struct { } elf_fpregset_t;
+#endif
+
 /*
  * This is used to ensure we don't load something for the wrong architecture.
  */
@@ -55,7 +58,9 @@ do {											\
         _regs->p2       = _dynamic_addr;                                \
 } while(0)
 
-#define USE_ELF_CORE_DUMP
+#if 0
+#define CORE_DUMP_USE_REGSET
+#endif
 #define ELF_FDPIC_CORE_EFLAGS   EF_BFIN_FDPIC
 #define ELF_EXEC_PAGESIZE       4096
 
diff --git a/arch/blackfin/include/asm/fcntl.h b/arch/blackfin/include/asm/fcntl.h
index 8727b2b382f1..251c911d59c1 100644
--- a/arch/blackfin/include/asm/fcntl.h
+++ b/arch/blackfin/include/asm/fcntl.h
@@ -7,8 +7,6 @@
 #ifndef _BFIN_FCNTL_H
 #define _BFIN_FCNTL_H
 
-/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
-   located on an ext2 file system */
 #define O_DIRECTORY      040000 /* must be a directory */
 #define O_NOFOLLOW      0100000 /* don't follow links */
 #define O_DIRECT        0200000 /* direct disk access hint - currently ignored */
diff --git a/arch/blackfin/include/asm/ftrace.h b/arch/blackfin/include/asm/ftrace.h
index 90c9b400ba6d..4cfe2d9ba7e8 100644
--- a/arch/blackfin/include/asm/ftrace.h
+++ b/arch/blackfin/include/asm/ftrace.h
@@ -10,4 +10,57 @@
 
 #define MCOUNT_INSN_SIZE        6 /* sizeof "[++sp] = rets; call __mcount;" */
 
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_FRAME_POINTER
+#include <linux/mm.h>
+
+extern inline void *return_address(unsigned int level)
+{
+        unsigned long *endstack, *fp, *ret_addr;
+        unsigned int current_level = 0;
+
+        if (level == 0)
+                return __builtin_return_address(0);
+
+        fp = (unsigned long *)__builtin_frame_address(0);
+        endstack = (unsigned long *)PAGE_ALIGN((unsigned long)&level);
+
+        while (((unsigned long)fp & 0x3) == 0 && fp &&
+               (fp + 1) < endstack && current_level < level) {
+                fp = (unsigned long *)*fp;
+                current_level++;
+        }
+
+        if (((unsigned long)fp & 0x3) == 0 && fp &&
+            (fp + 1) < endstack)
+                ret_addr = (unsigned long *)*(fp + 1);
+        else
+                ret_addr = NULL;
+
+        return ret_addr;
+}
+
+#else
+
+extern inline void *return_address(unsigned int level)
+{
+        return NULL;
+}
+
+#endif /* CONFIG_FRAME_POINTER */
+
+#define HAVE_ARCH_CALLER_ADDR
+
+/* inline function or macro may lead to unexpected result */
+#define CALLER_ADDR0 ((unsigned long)__builtin_return_address(0))
+#define CALLER_ADDR1 ((unsigned long)return_address(1))
+#define CALLER_ADDR2 ((unsigned long)return_address(2))
+#define CALLER_ADDR3 ((unsigned long)return_address(3))
+#define CALLER_ADDR4 ((unsigned long)return_address(4))
+#define CALLER_ADDR5 ((unsigned long)return_address(5))
+#define CALLER_ADDR6 ((unsigned long)return_address(6))
+
+#endif /* __ASSEMBLY__ */
+
 #endif
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
index 5b44d05ca53e..91bd2d7b9d55 100644
--- a/arch/blackfin/include/asm/gpio.h
+++ b/arch/blackfin/include/asm/gpio.h
@@ -70,6 +70,8 @@
 
 #ifndef __ASSEMBLY__
 
+#include <linux/compiler.h>
+
 /***********************************************************
 *
 * FUNCTIONS: Blackfin General Purpose Ports Access Functions
@@ -159,6 +161,11 @@ struct gpio_port_t {
 };
 #endif
 
+#ifdef BFIN_SPECIAL_GPIO_BANKS
+void bfin_special_gpio_free(unsigned gpio);
+int bfin_special_gpio_request(unsigned gpio, const char *label);
+#endif
+
 #ifdef CONFIG_PM
 
 unsigned int bfin_pm_standby_setup(void);
@@ -218,6 +225,9 @@ int bfin_gpio_direction_output(unsigned gpio, int value);
 int bfin_gpio_get_value(unsigned gpio);
 void bfin_gpio_set_value(unsigned gpio, int value);
 
+#include <asm/irq.h>
+#include <asm/errno.h>
+
 #ifdef CONFIG_GPIOLIB
 #include <asm-generic/gpio.h>           /* cansleep wrappers */
 
@@ -242,6 +252,11 @@ static inline int gpio_cansleep(unsigned int gpio)
         return __gpio_cansleep(gpio);
 }
 
+static inline int gpio_to_irq(unsigned gpio)
+{
+        return __gpio_to_irq(gpio);
+}
+
 #else /* !CONFIG_GPIOLIB */
 
 static inline int gpio_request(unsigned gpio, const char *label)
@@ -274,10 +289,6 @@ static inline void gpio_set_value(unsigned gpio, int value)
         return bfin_gpio_set_value(gpio, value);
 }
 
-#include <asm-generic/gpio.h>           /* cansleep wrappers */
-#endif  /* !CONFIG_GPIOLIB */
-#include <asm/irq.h>
-
 static inline int gpio_to_irq(unsigned gpio)
 {
         if (likely(gpio < MAX_BLACKFIN_GPIOS))
@@ -286,6 +297,9 @@ static inline int gpio_to_irq(unsigned gpio)
         return -EINVAL;
 }
 
+#include <asm-generic/gpio.h>           /* cansleep wrappers */
+#endif  /* !CONFIG_GPIOLIB */
+
 static inline int irq_to_gpio(unsigned irq)
 {
         return (irq - GPIO_IRQ_BASE);
diff --git a/arch/blackfin/include/asm/gptimers.h b/arch/blackfin/include/asm/gptimers.h
index 89f08decb8e0..c722acdda0d3 100644
--- a/arch/blackfin/include/asm/gptimers.h
+++ b/arch/blackfin/include/asm/gptimers.h
@@ -172,25 +172,25 @@
 
 /* The actual gptimer API */
 
-void     set_gptimer_pwidth(int timer_id, uint32_t width);
-uint32_t get_gptimer_pwidth(int timer_id);
-void     set_gptimer_period(int timer_id, uint32_t period);
-uint32_t get_gptimer_period(int timer_id);
-uint32_t get_gptimer_count(int timer_id);
-int      get_gptimer_intr(int timer_id);
-void     clear_gptimer_intr(int timer_id);
-int      get_gptimer_over(int timer_id);
-void     clear_gptimer_over(int timer_id);
-void     set_gptimer_config(int timer_id, uint16_t config);
-uint16_t get_gptimer_config(int timer_id);
-int      get_gptimer_run(int timer_id);
-void     set_gptimer_pulse_hi(int timer_id);
-void     clear_gptimer_pulse_hi(int timer_id);
+void     set_gptimer_pwidth(unsigned int timer_id, uint32_t width);
+uint32_t get_gptimer_pwidth(unsigned int timer_id);
+void     set_gptimer_period(unsigned int timer_id, uint32_t period);
+uint32_t get_gptimer_period(unsigned int timer_id);
+uint32_t get_gptimer_count(unsigned int timer_id);
+int      get_gptimer_intr(unsigned int timer_id);
+void     clear_gptimer_intr(unsigned int timer_id);
+int      get_gptimer_over(unsigned int timer_id);
+void     clear_gptimer_over(unsigned int timer_id);
+void     set_gptimer_config(unsigned int timer_id, uint16_t config);
+uint16_t get_gptimer_config(unsigned int timer_id);
+int      get_gptimer_run(unsigned int timer_id);
+void     set_gptimer_pulse_hi(unsigned int timer_id);
+void     clear_gptimer_pulse_hi(unsigned int timer_id);
 void     enable_gptimers(uint16_t mask);
 void     disable_gptimers(uint16_t mask);
 void     disable_gptimers_sync(uint16_t mask);
 uint16_t get_enabled_gptimers(void);
-uint32_t get_gptimer_status(int group);
-void     set_gptimer_status(int group, uint32_t value);
+uint32_t get_gptimer_status(unsigned int group);
+void     set_gptimer_status(unsigned int group, uint32_t value);
 
 #endif
diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h
index d1f5029189a7..29e55b9d88bc 100644
--- a/arch/blackfin/include/asm/io.h
+++ b/arch/blackfin/include/asm/io.h
@@ -31,12 +31,14 @@ static inline unsigned char readb(const volatile void __iomem *addr)
         unsigned int val;
         int tmp;
 
-        __asm__ __volatile__ ("cli %1;\n\t"
-                        "NOP; NOP; SSYNC;\n\t"
-                        "%0 = b [%2] (z);\n\t"
-                        "sti %1;\n\t"
-                        : "=d"(val), "=d"(tmp): "a"(addr)
-                        );
+        __asm__ __volatile__ (
+                "cli %1;"
+                "NOP; NOP; SSYNC;"
+                "%0 = b [%2] (z);"
+                "sti %1;"
+                : "=d"(val), "=d"(tmp)
+                : "a"(addr)
+        );
 
         return (unsigned char) val;
 }
@@ -46,12 +48,14 @@ static inline unsigned short readw(const volatile void __iomem *addr)
         unsigned int val;
         int tmp;
 
-        __asm__ __volatile__ ("cli %1;\n\t"
-                        "NOP; NOP; SSYNC;\n\t"
-                        "%0 = w [%2] (z);\n\t"
-                        "sti %1;\n\t"
-                        : "=d"(val), "=d"(tmp): "a"(addr)
-                        );
+        __asm__ __volatile__ (
+                "cli %1;"
+                "NOP; NOP; SSYNC;"
+                "%0 = w [%2] (z);"
+                "sti %1;"
+                : "=d"(val), "=d"(tmp)
+                : "a"(addr)
+        );
 
         return (unsigned short) val;
 }
@@ -61,20 +65,23 @@ static inline unsigned int readl(const volatile void __iomem *addr)
         unsigned int val;
         int tmp;
 
-        __asm__ __volatile__ ("cli %1;\n\t"
-                        "NOP; NOP; SSYNC;\n\t"
-                        "%0 = [%2];\n\t"
-                        "sti %1;\n\t"
-                        : "=d"(val), "=d"(tmp): "a"(addr)
-                        );
+        __asm__ __volatile__ (
+                "cli %1;"
+                "NOP; NOP; SSYNC;"
+                "%0 = [%2];"
+                "sti %1;"
+                : "=d"(val), "=d"(tmp)
+                : "a"(addr)
+        );
+
         return val;
 }
 
 #endif /*  __ASSEMBLY__ */
 
-#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
-#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
-#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
+#define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b))
+#define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b))
+#define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b))
 
 #define __raw_readb readb
 #define __raw_readw readw
@@ -82,9 +89,9 @@ static inline unsigned int readl(const volatile void __iomem *addr)
 #define __raw_writeb writeb
 #define __raw_writew writew
 #define __raw_writel writel
-#define memset_io(a,b,c)        memset((void *)(a),(b),(c))
-#define memcpy_fromio(a,b,c)    memcpy((a),(void *)(b),(c))
-#define memcpy_toio(a,b,c)      memcpy((void *)(a),(b),(c))
+#define memset_io(a, b, c)      memset((void *)(a), (b), (c))
+#define memcpy_fromio(a, b, c)  memcpy((a), (void *)(b), (c))
+#define memcpy_toio(a, b, c)    memcpy((void *)(a), (b), (c))
 
 /* Convert "I/O port addresses" to actual addresses.  i.e. ugly casts. */
 #define __io(port) ((void *)(unsigned long)(port))
@@ -92,30 +99,30 @@ static inline unsigned int readl(const volatile void __iomem *addr)
 #define inb(port)    readb(__io(port))
 #define inw(port)    readw(__io(port))
 #define inl(port)    readl(__io(port))
-#define outb(x,port) writeb(x,__io(port))
-#define outw(x,port) writew(x,__io(port))
-#define outl(x,port) writel(x,__io(port))
+#define outb(x, port) writeb(x, __io(port))
+#define outw(x, port) writew(x, __io(port))
+#define outl(x, port) writel(x, __io(port))
 
 #define inb_p(port)    inb(__io(port))
 #define inw_p(port)    inw(__io(port))
 #define inl_p(port)    inl(__io(port))
-#define outb_p(x,port) outb(x,__io(port))
-#define outw_p(x,port) outw(x,__io(port))
-#define outl_p(x,port) outl(x,__io(port))
-
-#define ioread8_rep(a,d,c)      readsb(a,d,c)
-#define ioread16_rep(a,d,c)     readsw(a,d,c)
-#define ioread32_rep(a,d,c)     readsl(a,d,c)
-#define iowrite8_rep(a,s,c)     writesb(a,s,c)
-#define iowrite16_rep(a,s,c)    writesw(a,s,c)
-#define iowrite32_rep(a,s,c)    writesl(a,s,c)
-
-#define ioread8(X)                      readb(X)
-#define ioread16(X)                     readw(X)
-#define ioread32(X)                     readl(X)
-#define iowrite8(val,X)                 writeb(val,X)
-#define iowrite16(val,X)                writew(val,X)
-#define iowrite32(val,X)                writel(val,X)
+#define outb_p(x, port) outb(x, __io(port))
+#define outw_p(x, port) outw(x, __io(port))
+#define outl_p(x, port) outl(x, __io(port))
+
+#define ioread8_rep(a, d, c)    readsb(a, d, c)
+#define ioread16_rep(a, d, c)   readsw(a, d, c)
+#define ioread32_rep(a, d, c)   readsl(a, d, c)
+#define iowrite8_rep(a, s, c)   writesb(a, s, c)
+#define iowrite16_rep(a, s, c)  writesw(a, s, c)
+#define iowrite32_rep(a, s, c)  writesl(a, s, c)
+
+#define ioread8(x)                      readb(x)
+#define ioread16(x)                     readw(x)
+#define ioread32(x)                     readl(x)
+#define iowrite8(val, x)                writeb(val, x)
+#define iowrite16(val, x)               writew(val, x)
+#define iowrite32(val, x)               writel(val, x)
 
 #define mmiowb() wmb()
 
diff --git a/arch/blackfin/include/asm/ipipe.h b/arch/blackfin/include/asm/ipipe.h
index 4617ba66278f..d3b40449ca0e 100644
--- a/arch/blackfin/include/asm/ipipe.h
+++ b/arch/blackfin/include/asm/ipipe.h
@@ -35,9 +35,9 @@
 #include <asm/atomic.h>
 #include <asm/traps.h>
 
-#define IPIPE_ARCH_STRING     "1.11-00"
+#define IPIPE_ARCH_STRING     "1.12-00"
 #define IPIPE_MAJOR_NUMBER    1
-#define IPIPE_MINOR_NUMBER    11
+#define IPIPE_MINOR_NUMBER    12
 #define IPIPE_PATCH_NUMBER    0
 
 #ifdef CONFIG_SMP
@@ -124,16 +124,6 @@ static inline int __ipipe_check_tickdev(const char *devname)
         return 1;
 }
 
-static inline void __ipipe_lock_root(void)
-{
-        set_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status));
-}
-
-static inline void __ipipe_unlock_root(void)
-{
-        clear_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status));
-}
-
 void __ipipe_enable_pipeline(void);
 
 #define __ipipe_hook_critical_ipi(ipd) do { } while (0)
diff --git a/arch/blackfin/include/asm/ipipe_base.h b/arch/blackfin/include/asm/ipipe_base.h
index 490098f532a7..00409201d9ed 100644
--- a/arch/blackfin/include/asm/ipipe_base.h
+++ b/arch/blackfin/include/asm/ipipe_base.h
@@ -51,23 +51,15 @@
 
 extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */
 
-#define __ipipe_stall_root()                                            \
-        do {                                                            \
-                volatile unsigned long *p = &__ipipe_root_status;       \
-                set_bit(0, p);                                          \
-        } while (0)
-
-#define __ipipe_test_and_stall_root()                                   \
-        ({                                                              \
-                volatile unsigned long *p = &__ipipe_root_status;       \
-                test_and_set_bit(0, p);                                 \
-        })
-
-#define __ipipe_test_root()                                     \
-        ({                                                      \
-                const unsigned long *p = &__ipipe_root_status;  \
-                test_bit(0, p);                                 \
-        })
+void __ipipe_stall_root(void);
+
+unsigned long __ipipe_test_and_stall_root(void);
+
+unsigned long __ipipe_test_root(void);
+
+void __ipipe_lock_root(void);
+
+void __ipipe_unlock_root(void);
 
 #endif /* !__ASSEMBLY__ */
 
diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h
index e7c0623f9091..12f4060a31b0 100644
--- a/arch/blackfin/include/asm/irq.h
+++ b/arch/blackfin/include/asm/irq.h
@@ -12,6 +12,9 @@
 
 #include <linux/irqflags.h>
 
+/* IRQs that may be used by external irq_chip controllers */
+#define NR_SPARE_IRQS   32
+
 #include <mach/anomaly.h>
 
 /* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h> */
@@ -35,4 +38,8 @@
 
 #include <asm-generic/irq.h>
 
+#ifdef CONFIG_NMI_WATCHDOG
+# define ARCH_HAS_NMI_WATCHDOG
+#endif
+
 #endif                          /* _BFIN_IRQ_H_ */
diff --git a/arch/blackfin/include/asm/irqflags.h b/arch/blackfin/include/asm/irqflags.h
index 9b19a19d9ae9..813a1af3e865 100644
--- a/arch/blackfin/include/asm/irqflags.h
+++ b/arch/blackfin/include/asm/irqflags.h
@@ -33,6 +33,7 @@ static inline unsigned long bfin_cli(void)
 
 #ifdef CONFIG_IPIPE
 
+#include <linux/compiler.h>
 #include <linux/ipipe_base.h>
 #include <linux/ipipe_trace.h>
 
@@ -49,12 +50,12 @@ static inline unsigned long bfin_cli(void)
                 barrier();                              \
         } while (0)
 
-static inline void raw_local_irq_enable(void)
-{
-        barrier();
-        ipipe_check_context(ipipe_root_domain);
-        __ipipe_unstall_root();
-}
+#define raw_local_irq_enable()                          \
+        do {                                            \
+                barrier();                              \
+                ipipe_check_context(ipipe_root_domain); \
+                __ipipe_unstall_root();                 \
+        } while (0)
 
 #define raw_local_save_flags_ptr(x)                                     \
         do {                                                            \
diff --git a/arch/blackfin/include/asm/kgdb.h b/arch/blackfin/include/asm/kgdb.h
index c8b256d2ea30..8651afe12990 100644
--- a/arch/blackfin/include/asm/kgdb.h
+++ b/arch/blackfin/include/asm/kgdb.h
@@ -10,9 +10,6 @@
 
 #include <linux/ptrace.h>
 
-/* gdb locks */
-#define KGDB_MAX_NO_CPUS 8
-
 /*
  * BUFMAX defines the maximum number of characters in inbound/outbound buffers.
  * At least NUMREGBYTES*2 are needed for register packets.
diff --git a/arch/blackfin/include/asm/mem_init.h b/arch/blackfin/include/asm/mem_init.h
index 4179e329b9c9..7c8fe834ff22 100644
--- a/arch/blackfin/include/asm/mem_init.h
+++ b/arch/blackfin/include/asm/mem_init.h
@@ -295,156 +295,3 @@
 #else
 #define PLL_BYPASS       0
 #endif
-
-/***************************************Currently Not Being Used *********************************/
-
-#if defined(CONFIG_FLASH_SPEED_BWAT) && \
-defined(CONFIG_FLASH_SPEED_BRAT) && \
-defined(CONFIG_FLASH_SPEED_BHT) && \
-defined(CONFIG_FLASH_SPEED_BST) && \
-defined(CONFIG_FLASH_SPEED_BTT)
-
-#define flash_EBIU_AMBCTL_WAT  ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_RAT  ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_HT   ((CONFIG_FLASH_SPEED_BHT  * 4) / (4000000000 / CONFIG_SCLK_HZ))
-#define flash_EBIU_AMBCTL_ST   ((CONFIG_FLASH_SPEED_BST  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_TT   ((CONFIG_FLASH_SPEED_BTT  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-
-#if (flash_EBIU_AMBCTL_TT > 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_4
-#endif
-#if (flash_EBIU_AMBCTL_TT == 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_3
-#endif
-#if (flash_EBIU_AMBCTL_TT == 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_2
-#endif
-#if (flash_EBIU_AMBCTL_TT < 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_ST > 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_4
-#endif
-#if (flash_EBIU_AMBCTL_ST == 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_3
-#endif
-#if (flash_EBIU_AMBCTL_ST == 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_2
-#endif
-#if (flash_EBIU_AMBCTL_ST < 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_1
-#endif
-
-#if (flash_EBIU_AMBCTL_HT > 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_3
-#endif
-#if (flash_EBIU_AMBCTL_HT == 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_2
-#endif
-#if (flash_EBIU_AMBCTL_HT == 1)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_0
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_WAT > 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_15
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_14
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 13)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_13
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 12)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_12
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 11)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_11
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 10)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_10
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 9)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_9
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 8)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_8
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 7)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_7
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 6)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_6
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 5)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_5
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 4)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_4
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 3)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_3
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 2)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_2
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 1)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_RAT > 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_15
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_14
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 13)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_13
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 12)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_12
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 11)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_11
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 10)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_10
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 9)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_9
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 8)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_8
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 7)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_7
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 6)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_6
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 5)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_5
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 4)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_4
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 3)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_3
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 2)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_2
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 1)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_1
-#endif
-
-#define flash_EBIU_AMBCTL0  \
-        (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
-         flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
-#endif
diff --git a/arch/blackfin/include/asm/mmu_context.h b/arch/blackfin/include/asm/mmu_context.h
index 4a3be376ad5b..e1a9b4624f91 100644
--- a/arch/blackfin/include/asm/mmu_context.h
+++ b/arch/blackfin/include/asm/mmu_context.h
@@ -7,12 +7,13 @@
 #ifndef __BLACKFIN_MMU_CONTEXT_H__
 #define __BLACKFIN_MMU_CONTEXT_H__
 
-#include <linux/gfp.h>
+#include <linux/slab.h>
 #include <linux/sched.h>
 #include <asm/setup.h>
 #include <asm/page.h>
 #include <asm/pgalloc.h>
 #include <asm/cplbinit.h>
+#include <asm/sections.h>
 
 /* Note: L1 stacks are CPU-private things, so we bluntly disable this
    feature in SMP mode, and use the per-CPU scratch SRAM bank only to
@@ -66,8 +67,8 @@ activate_l1stack(struct mm_struct *mm, unsigned long sp_base)
 
 #define activate_mm(prev, next) switch_mm(prev, next, NULL)
 
-static inline void switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm,
-                             struct task_struct *tsk)
+static inline void __switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm,
+                               struct task_struct *tsk)
 {
 #ifdef CONFIG_MPU
         unsigned int cpu = smp_processor_id();
@@ -95,14 +96,38 @@ static inline void switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_m
 #endif
 }
 
+#ifdef CONFIG_IPIPE
+#define lock_mm_switch(flags)   local_irq_save_hw_cond(flags)
+#define unlock_mm_switch(flags) local_irq_restore_hw_cond(flags)
+#else
+#define lock_mm_switch(flags)   do { (void)(flags); } while (0)
+#define unlock_mm_switch(flags) do { (void)(flags); } while (0)
+#endif /* CONFIG_IPIPE */
+
 #ifdef CONFIG_MPU
+static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
+                             struct task_struct *tsk)
+{
+        unsigned long flags;
+        lock_mm_switch(flags);
+        __switch_mm(prev, next, tsk);
+        unlock_mm_switch(flags);
+}
+
 static inline void protect_page(struct mm_struct *mm, unsigned long addr,
                                 unsigned long flags)
 {
         unsigned long *mask = mm->context.page_rwx_mask;
-        unsigned long page = addr >> 12;
-        unsigned long idx = page >> 5;
-        unsigned long bit = 1 << (page & 31);
+        unsigned long page;
+        unsigned long idx;
+        unsigned long bit;
+
+        if (unlikely(addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE))
+                page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> 12;
+        else
+                page = addr >> 12;
+        idx = page >> 5;
+        bit = 1 << (page & 31);
 
         if (flags & VM_READ)
                 mask[idx] |= bit;
@@ -128,6 +153,12 @@ static inline void update_protections(struct mm_struct *mm)
                 set_mask_dcplbs(mm->context.page_rwx_mask, cpu);
         }
 }
+#else /* !CONFIG_MPU */
+static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
+                             struct task_struct *tsk)
+{
+        __switch_mm(prev, next, tsk);
+}
 #endif
 
 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
@@ -173,4 +204,10 @@ static inline void destroy_context(struct mm_struct *mm)
 #endif
 }
 
+#define ipipe_mm_switch_protect(flags)          \
+        local_irq_save_hw_cond(flags)
+
+#define ipipe_mm_switch_unprotect(flags)        \
+        local_irq_restore_hw_cond(flags)
+
 #endif
diff --git a/arch/blackfin/include/asm/module.h b/arch/blackfin/include/asm/module.h
index 9c1cfffddd9b..4282b169ead9 100644
--- a/arch/blackfin/include/asm/module.h
+++ b/arch/blackfin/include/asm/module.h
@@ -7,8 +7,6 @@
 #ifndef _ASM_BFIN_MODULE_H
 #define _ASM_BFIN_MODULE_H
 
-#define MODULE_SYMBOL_PREFIX "_"
-
 #define Elf_Shdr        Elf32_Shdr
 #define Elf_Sym         Elf32_Sym
 #define Elf_Ehdr        Elf32_Ehdr
diff --git a/arch/blackfin/include/asm/nand.h b/arch/blackfin/include/asm/nand.h
index 3ae8b569edfc..3a1e79dfc8d9 100644
--- a/arch/blackfin/include/asm/nand.h
+++ b/arch/blackfin/include/asm/nand.h
@@ -1,5 +1,5 @@
 /*
- * BF5XX - NAND flash controller platfrom_device info
+ * BF5XX - NAND flash controller platform_device info
  *
  * Copyright 2007-2008 Analog Devices, Inc.
  *
@@ -8,7 +8,7 @@
 
 /* struct bf5xx_nand_platform
  *
- * define a interface between platfrom board specific code and
+ * define a interface between platform board specific code and
  * bf54x NFC driver.
  *
  * nr_partitions = number of partitions pointed to be partitoons (or zero)
diff --git a/arch/blackfin/include/asm/nmi.h b/arch/blackfin/include/asm/nmi.h
new file mode 100644
index 000000000000..b9caac4fcfd8
--- /dev/null
+++ b/arch/blackfin/include/asm/nmi.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2
+ */
+
+#ifndef _BFIN_NMI_H_
+#define _BFIN_NMI_H_
+
+#include <linux/nmi.h>
+
+#endif
diff --git a/arch/blackfin/include/asm/page.h b/arch/blackfin/include/asm/page.h
index 944a07c6cfd6..d0ce975bcd48 100644
--- a/arch/blackfin/include/asm/page.h
+++ b/arch/blackfin/include/asm/page.h
@@ -10,4 +10,12 @@
 #include <asm-generic/page.h>
 #define MAP_NR(addr) (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)
 
+#define VM_DATA_DEFAULT_FLAGS \
+        (VM_READ | VM_WRITE | \
+        ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0 ) | \
+                 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+
+#include <asm-generic/memory_model.h>
+#include <asm-generic/getorder.h>
+
 #endif
diff --git a/arch/blackfin/include/asm/pci.h b/arch/blackfin/include/asm/pci.h
index 61277358c865..99cae2e3bac7 100644
--- a/arch/blackfin/include/asm/pci.h
+++ b/arch/blackfin/include/asm/pci.h
@@ -4,145 +4,19 @@
 #define _ASM_BFIN_PCI_H
 
 #include <asm/scatterlist.h>
+#include <asm-generic/pci-dma-compat.h>
+#include <asm-generic/pci.h>
 
-/*
- *
- * Written by Wout Klaren.
- */
-
-/* Added by Chang Junxiao */
 #define PCIBIOS_MIN_IO 0x00001000
 #define PCIBIOS_MIN_MEM 0x10000000
 
-#define PCI_DMA_BUS_IS_PHYS       (1)
-struct pci_ops;
-
-/*
- * Structure with hardware dependent information and functions of the
- * PCI bus.
- */
-struct pci_bus_info {
-
-        /*
-         * Resources of the PCI bus.
-         */
-        struct resource mem_space;
-        struct resource io_space;
-
-        /*
-         * System dependent functions.
-         */
-        struct pci_ops *bfin_pci_ops;
-        void (*fixup) (int pci_modify);
-        void (*conf_device) (unsigned char bus, unsigned char device_fn);
-};
-
-#define pcibios_assign_all_busses()     0
 static inline void pcibios_set_master(struct pci_dev *dev)
 {
-
         /* No special bus mastering setup handling */
 }
 static inline void pcibios_penalize_isa_irq(int irq)
 {
-
         /* We don't do dynamic PCI IRQ allocation */
 }
-static inline dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr,
-                                        size_t size, int direction)
-{
-        if (direction == PCI_DMA_NONE)
-                BUG();
-
-         /* return virt_to_bus(ptr); */
-        return (dma_addr_t) ptr;
-}
-
-/* Unmap a single streaming mode DMA translation.  The dma_addr and size
- * must match what was provided for in a previous pci_map_single call.  All
- * other usages are undefined.
- *
- * After this call, reads by the cpu to the buffer are guarenteed to see
- * whatever the device wrote there.
- */
-static inline void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr,
-                                    size_t size, int direction)
-{
-        if (direction == PCI_DMA_NONE)
-                BUG();
-
-        /* Nothing to do */
-}
-
-/* Map a set of buffers described by scatterlist in streaming
- * mode for DMA.  This is the scather-gather version of the
- * above pci_map_single interface.  Here the scatter gather list
- * elements are each tagged with the appropriate dma address
- * and length.  They are obtained via sg_dma_{address,length}(SG).
- *
- * NOTE: An implementation may be able to use a smaller number of
- *       DMA address/length pairs than there are SG table elements.
- *       (for example via virtual mapping capabilities)
- *       The routine returns the number of addr/length pairs actually
- *       used, at most nents.
- *
- * Device ownership issues as mentioned above for pci_map_single are
- * the same here.
- */
-static inline int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg,
-                             int nents, int direction)
-{
-        if (direction == PCI_DMA_NONE)
-                BUG();
-        return nents;
-}
-
-/* Unmap a set of streaming mode DMA translations.
- * Again, cpu read rules concerning calls here are the same as for
- * pci_unmap_single() above.
- */
-static inline void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg,
-                                int nents, int direction)
-{
-        if (direction == PCI_DMA_NONE)
-                BUG();
-
-        /* Nothing to do */
-}
-
-/* Make physical memory consistent for a single
- * streaming mode DMA translation after a transfer.
- *
- * If you perform a pci_map_single() but wish to interrogate the
- * buffer using the cpu, yet do not wish to teardown the PCI dma
- * mapping, you must call this function before doing so.  At the
- * next point you give the PCI dma address back to the card, the
- * device again owns the buffer.
- */
-static inline void pci_dma_sync_single(struct pci_dev *hwdev,
-                                       dma_addr_t dma_handle, size_t size,
-                                       int direction)
-{
-        if (direction == PCI_DMA_NONE)
-                BUG();
-
-        /* Nothing to do */
-}
-
-/* Make physical memory consistent for a set of streaming
- * mode DMA translations after a transfer.
- *
- * The same as pci_dma_sync_single but for a scatter-gather list,
- * same rules and usage.
- */
-static inline void pci_dma_sync_sg(struct pci_dev *hwdev,
-                                   struct scatterlist *sg, int nelems,
-                                   int direction)
-{
-        if (direction == PCI_DMA_NONE)
-                BUG();
-
-        /* Nothing to do */
-}
 
 #endif                          /* _ASM_BFIN_PCI_H */
diff --git a/arch/blackfin/include/asm/ptrace.h b/arch/blackfin/include/asm/ptrace.h
index 27290c955a7a..aaa1c6c2bc19 100644
--- a/arch/blackfin/include/asm/ptrace.h
+++ b/arch/blackfin/include/asm/ptrace.h
@@ -24,6 +24,8 @@
 
 #ifndef __ASSEMBLY__
 
+struct task_struct;
+
 /* this struct defines the way the registers are stored on the
    stack during a system call. */
 
@@ -89,9 +91,9 @@ struct pt_regs {
 #define PTRACE_GETREGS            12
 #define PTRACE_SETREGS            13    /* ptrace signal  */
 
-#define PTRACE_GETFDPIC           31
-#define PTRACE_GETFDPIC_EXEC      0
-#define PTRACE_GETFDPIC_INTERP    1
+#define PTRACE_GETFDPIC           31    /* get the ELF fdpic loadmap address */
+#define PTRACE_GETFDPIC_EXEC       0    /* [addr] request the executable loadmap */
+#define PTRACE_GETFDPIC_INTERP     1    /* [addr] request the interpreter loadmap */
 
 #define PS_S  (0x0002)
 
@@ -101,9 +103,30 @@ struct pt_regs {
    master interrupt enable.  */
 #define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1)))
 #define instruction_pointer(regs) ((regs)->pc)
+#define user_stack_pointer(regs)  ((regs)->usp)
 #define profile_pc(regs) instruction_pointer(regs)
 extern void show_regs(struct pt_regs *);
 
+#define arch_has_single_step()  (1)
+extern void user_enable_single_step(struct task_struct *child);
+extern void user_disable_single_step(struct task_struct *child);
+/* common code demands this function */
+#define ptrace_disable(child) user_disable_single_step(child)
+
+/*
+ * Get the address of the live pt_regs for the specified task.
+ * These are saved onto the top kernel stack when the process
+ * is not running.
+ *
+ * Note: if a user thread is execve'd from kernel space, the
+ * kernel stack will not be empty on entry to the kernel, so
+ * ptracing these tasks will fail.
+ */
+#define task_pt_regs(task) \
+        (struct pt_regs *) \
+            ((unsigned long)task_stack_page(task) + \
+             (THREAD_SIZE - sizeof(struct pt_regs)))
+
 #endif  /*  __KERNEL__  */
 
 #endif                          /* __ASSEMBLY__ */
@@ -173,4 +196,6 @@ extern void show_regs(struct pt_regs *);
 #define PT_FDPIC_EXEC 232
 #define PT_FDPIC_INTERP 236
 
+#define PT_LAST_PSEUDO PT_FDPIC_INTERP
+
 #endif                          /* _BFIN_PTRACE_H */
diff --git a/arch/blackfin/include/asm/sections.h b/arch/blackfin/include/asm/sections.h
index 1f5381fbb4a7..14a3e66d9167 100644
--- a/arch/blackfin/include/asm/sections.h
+++ b/arch/blackfin/include/asm/sections.h
@@ -13,10 +13,21 @@ extern unsigned long memory_mtd_start, memory_mtd_end, mtd_size;
 extern unsigned long _ramstart, _ramend, _rambase;
 extern unsigned long memory_start, memory_end, physical_mem_end;
 
-extern char _stext_l1[], _etext_l1[], _sdata_l1[], _edata_l1[], _sbss_l1[],
-        _ebss_l1[], _l1_lma_start[], _sdata_b_l1[], _sbss_b_l1[], _ebss_b_l1[],
-        _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[], _sbss_l2[],
-        _ebss_l2[], _l2_lma_start[];
+/*
+ * The weak markings on the lengths might seem weird, but this is required
+ * in order to make gcc accept the fact that these may actually have a value
+ * of 0 (since they aren't actually addresses, but sizes of sections).
+ */
+extern char _stext_l1[], _etext_l1[], _text_l1_lma[], __weak _text_l1_len[];
+extern char _sdata_l1[], _edata_l1[], _sbss_l1[], _ebss_l1[],
+        _data_l1_lma[], __weak _data_l1_len[];
+#ifdef CONFIG_ROMKERNEL
+extern char _data_lma[], _data_len[], _sinitdata[], _einitdata[], _init_data_lma[], _init_data_len[];
+#endif
+extern char _sdata_b_l1[], _edata_b_l1[], _sbss_b_l1[], _ebss_b_l1[],
+        _data_b_l1_lma[], __weak _data_b_l1_len[];
+extern char _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[],
+        _sbss_l2[], _ebss_l2[], _l2_lma[], __weak _l2_len[];
 
 #include <asm/mem_map.h>
 
diff --git a/arch/blackfin/include/asm/smp.h b/arch/blackfin/include/asm/smp.h
index 6a0fe94b84a6..f5b537967116 100644
--- a/arch/blackfin/include/asm/smp.h
+++ b/arch/blackfin/include/asm/smp.h
@@ -22,8 +22,23 @@ extern char coreb_trampoline_start, coreb_trampoline_end;
 struct corelock_slot {
         int lock;
 };
+extern struct corelock_slot corelock;
+
+#ifdef __ARCH_SYNC_CORE_ICACHE
+extern unsigned long icache_invld_count[NR_CPUS];
+#endif
+#ifdef __ARCH_SYNC_CORE_DCACHE
+extern unsigned long dcache_invld_count[NR_CPUS];
+#endif
 
 void smp_icache_flush_range_others(unsigned long start,
                                    unsigned long end);
+#ifdef CONFIG_HOTPLUG_CPU
+void coreb_sleep(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
+void cpu_die(void);
+void platform_cpu_die(void);
+int __cpu_disable(void);
+int __cpu_die(unsigned int cpu);
+#endif
 
 #endif /* !__ASM_BLACKFIN_SMP_H */
diff --git a/arch/blackfin/include/asm/spinlock.h b/arch/blackfin/include/asm/spinlock.h
index b0c7f0ee4b03..1942ccfedbe0 100644
--- a/arch/blackfin/include/asm/spinlock.h
+++ b/arch/blackfin/include/asm/spinlock.h
@@ -17,84 +17,84 @@ asmlinkage int __raw_spin_is_locked_asm(volatile int *ptr);
 asmlinkage void __raw_spin_lock_asm(volatile int *ptr);
 asmlinkage int __raw_spin_trylock_asm(volatile int *ptr);
 asmlinkage void __raw_spin_unlock_asm(volatile int *ptr);
-asmlinkage void __raw_read_lock_asm(volatile int *ptr);
-asmlinkage int __raw_read_trylock_asm(volatile int *ptr);
-asmlinkage void __raw_read_unlock_asm(volatile int *ptr);
-asmlinkage void __raw_write_lock_asm(volatile int *ptr);
-asmlinkage int __raw_write_trylock_asm(volatile int *ptr);
-asmlinkage void __raw_write_unlock_asm(volatile int *ptr);
-
-static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
+asmlinkage void arch_read_lock_asm(volatile int *ptr);
+asmlinkage int arch_read_trylock_asm(volatile int *ptr);
+asmlinkage void arch_read_unlock_asm(volatile int *ptr);
+asmlinkage void arch_write_lock_asm(volatile int *ptr);
+asmlinkage int arch_write_trylock_asm(volatile int *ptr);
+asmlinkage void arch_write_unlock_asm(volatile int *ptr);
+
+static inline int arch_spin_is_locked(arch_spinlock_t *lock)
 {
         return __raw_spin_is_locked_asm(&lock->lock);
 }
 
-static inline void __raw_spin_lock(raw_spinlock_t *lock)
+static inline void arch_spin_lock(arch_spinlock_t *lock)
 {
         __raw_spin_lock_asm(&lock->lock);
 }
 
-#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
+#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
 
-static inline int __raw_spin_trylock(raw_spinlock_t *lock)
+static inline int arch_spin_trylock(arch_spinlock_t *lock)
 {
         return __raw_spin_trylock_asm(&lock->lock);
 }
 
-static inline void __raw_spin_unlock(raw_spinlock_t *lock)
+static inline void arch_spin_unlock(arch_spinlock_t *lock)
 {
         __raw_spin_unlock_asm(&lock->lock);
 }
 
-static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock)
+static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
 {
-        while (__raw_spin_is_locked(lock))
+        while (arch_spin_is_locked(lock))
                 cpu_relax();
 }
 
-static inline int __raw_read_can_lock(raw_rwlock_t *rw)
+static inline int arch_read_can_lock(arch_rwlock_t *rw)
 {
         return __raw_uncached_fetch_asm(&rw->lock) > 0;
 }
 
-static inline int __raw_write_can_lock(raw_rwlock_t *rw)
+static inline int arch_write_can_lock(arch_rwlock_t *rw)
 {
         return __raw_uncached_fetch_asm(&rw->lock) == RW_LOCK_BIAS;
 }
 
-static inline void __raw_read_lock(raw_rwlock_t *rw)
+static inline void arch_read_lock(arch_rwlock_t *rw)
 {
-        __raw_read_lock_asm(&rw->lock);
+        arch_read_lock_asm(&rw->lock);
 }
 
-static inline int __raw_read_trylock(raw_rwlock_t *rw)
+static inline int arch_read_trylock(arch_rwlock_t *rw)
 {
-        return __raw_read_trylock_asm(&rw->lock);
+        return arch_read_trylock_asm(&rw->lock);
 }
 
-static inline void __raw_read_unlock(raw_rwlock_t *rw)
+static inline void arch_read_unlock(arch_rwlock_t *rw)
 {
-        __raw_read_unlock_asm(&rw->lock);
+        arch_read_unlock_asm(&rw->lock);
 }
 
-static inline void __raw_write_lock(raw_rwlock_t *rw)
+static inline void arch_write_lock(arch_rwlock_t *rw)
 {
-        __raw_write_lock_asm(&rw->lock);
+        arch_write_lock_asm(&rw->lock);
 }
 
-static inline int __raw_write_trylock(raw_rwlock_t *rw)
+static inline int arch_write_trylock(arch_rwlock_t *rw)
 {
-        return __raw_write_trylock_asm(&rw->lock);
+        return arch_write_trylock_asm(&rw->lock);
 }
 
-static inline void __raw_write_unlock(raw_rwlock_t *rw)
+static inline void arch_write_unlock(arch_rwlock_t *rw)
 {
-        __raw_write_unlock_asm(&rw->lock);
+        arch_write_unlock_asm(&rw->lock);
 }
 
-#define _raw_spin_relax(lock)   cpu_relax()
-#define _raw_read_relax(lock)   cpu_relax()
-#define _raw_write_relax(lock)  cpu_relax()
+#define arch_spin_relax(lock)   cpu_relax()
+#define arch_read_relax(lock)   cpu_relax()
+#define arch_write_relax(lock)  cpu_relax()
 
 #endif
 
diff --git a/arch/blackfin/include/asm/spinlock_types.h b/arch/blackfin/include/asm/spinlock_types.h
index be75762c0610..1a33608c958b 100644
--- a/arch/blackfin/include/asm/spinlock_types.h
+++ b/arch/blackfin/include/asm/spinlock_types.h
@@ -15,14 +15,14 @@
 
 typedef struct {
         volatile unsigned int lock;
-} raw_spinlock_t;
+} arch_spinlock_t;
 
-#define __RAW_SPIN_LOCK_UNLOCKED        { 0 }
+#define __ARCH_SPIN_LOCK_UNLOCKED       { 0 }
 
 typedef struct {
         volatile unsigned int lock;
-} raw_rwlock_t;
+} arch_rwlock_t;
 
-#define __RAW_RW_LOCK_UNLOCKED          { RW_LOCK_BIAS }
+#define __ARCH_RW_LOCK_UNLOCKED         { RW_LOCK_BIAS }
 
 #endif
diff --git a/arch/blackfin/include/asm/syscall.h b/arch/blackfin/include/asm/syscall.h
new file mode 100644
index 000000000000..4921a4815cce
--- /dev/null
+++ b/arch/blackfin/include/asm/syscall.h
@@ -0,0 +1,96 @@
+/*
+ * Magic syscall break down functions
+ *
+ * Copyright 2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __ASM_BLACKFIN_SYSCALL_H__
+#define __ASM_BLACKFIN_SYSCALL_H__
+
+/*
+ * Blackfin syscalls are simple:
+ *      enter:
+ *              p0: syscall number
+ *              r{0,1,2,3,4,5}: syscall args 0,1,2,3,4,5
+ *      exit:
+ *              r0: return/error value
+ */
+
+#include <linux/err.h>
+#include <linux/sched.h>
+#include <asm/ptrace.h>
+
+static inline long
+syscall_get_nr(struct task_struct *task, struct pt_regs *regs)
+{
+        return regs->p0;
+}
+
+static inline void
+syscall_rollback(struct task_struct *task, struct pt_regs *regs)
+{
+        regs->p0 = regs->orig_p0;
+}
+
+static inline long
+syscall_get_error(struct task_struct *task, struct pt_regs *regs)
+{
+        return IS_ERR_VALUE(regs->r0) ? regs->r0 : 0;
+}
+
+static inline long
+syscall_get_return_value(struct task_struct *task, struct pt_regs *regs)
+{
+        return regs->r0;
+}
+
+static inline void
+syscall_set_return_value(struct task_struct *task, struct pt_regs *regs,
+                         int error, long val)
+{
+        regs->r0 = error ? -error : val;
+}
+
+/**
+ *      syscall_get_arguments()
+ *      @task:   unused
+ *      @regs:   the register layout to extract syscall arguments from
+ *      @i:      first syscall argument to extract
+ *      @n:      number of syscall arguments to extract
+ *      @args:   array to return the syscall arguments in
+ *
+ * args[0] gets i'th argument, args[n - 1] gets the i+n-1'th argument
+ */
+static inline void
+syscall_get_arguments(struct task_struct *task, struct pt_regs *regs,
+                      unsigned int i, unsigned int n, unsigned long *args)
+{
+        /*
+         * Assume the ptrace layout doesn't change -- r5 is first in memory,
+         * then r4, ..., then r0.  So we simply reverse the ptrace register
+         * array in memory to store into the args array.
+         */
+        long *aregs = &regs->r0 - i;
+
+        BUG_ON(i > 5 || i + n > 6);
+
+        while (n--)
+                *args++ = *aregs--;
+}
+
+/* See syscall_get_arguments() comments */
+static inline void
+syscall_set_arguments(struct task_struct *task, struct pt_regs *regs,
+                      unsigned int i, unsigned int n, const unsigned long *args)
+{
+        long *aregs = &regs->r0 - i;
+
+        BUG_ON(i > 5 || i + n > 6);
+
+        while (n--)
+                *aregs-- = *args++;
+}
+
+#endif
diff --git a/arch/blackfin/include/asm/thread_info.h b/arch/blackfin/include/asm/thread_info.h
index afb3a8626380..e9a5614cdbb1 100644
--- a/arch/blackfin/include/asm/thread_info.h
+++ b/arch/blackfin/include/asm/thread_info.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004-2009 Analog Devices Inc.
+ * Copyright 2004-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -17,7 +17,7 @@
 /* Thread Align Mask to reach to the top of the stack
  * for any process
  */
-#define ALIGN_PAGE_MASK         0xffffe000
+#define ALIGN_PAGE_MASK         0xffffe000
 
 /*
  * Size of kernel stack for each process. This must be a power of 2...
@@ -57,7 +57,7 @@ struct thread_info {
         .exec_domain    = &default_exec_domain, \
         .flags          = 0,                    \
         .cpu            = 0,                    \
-        .preempt_count  = INIT_PREEMPT_COUNT,   \
+        .preempt_count  = INIT_PREEMPT_COUNT,   \
         .restart_block  = {                     \
                 .fn = do_no_restart_syscall,    \
         },                                      \
@@ -73,8 +73,7 @@ __attribute_const__
 static inline struct thread_info *current_thread_info(void)
 {
         struct thread_info *ti;
-      __asm__("%0 = sp;" : "=da"(ti) :
-        );
+        __asm__("%0 = sp;" : "=da"(ti));
         return (struct thread_info *)((long)ti & ~((long)THREAD_SIZE-1));
 }
 
@@ -99,10 +98,12 @@ static inline struct thread_info *current_thread_info(void)
 #define TIF_NEED_RESCHED        2       /* rescheduling necessary */
 #define TIF_POLLING_NRFLAG      3       /* true if poll_idle() is polling
                                            TIF_NEED_RESCHED */
-#define TIF_MEMDIE              4
+#define TIF_MEMDIE              4
 #define TIF_RESTORE_SIGMASK     5       /* restore signal mask in do_signal() */
-#define TIF_FREEZE              6       /* is freezing for suspend */
-#define TIF_IRQ_SYNC            7       /* sync pipeline stage */
+#define TIF_FREEZE              6       /* is freezing for suspend */
+#define TIF_IRQ_SYNC            7       /* sync pipeline stage */
+#define TIF_NOTIFY_RESUME       8       /* callback before returning to user */
+#define TIF_SINGLESTEP          9
 
 /* as above, but as bit values */
 #define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
@@ -110,8 +111,10 @@ static inline struct thread_info *current_thread_info(void)
 #define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
 #define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
 #define _TIF_RESTORE_SIGMASK    (1<<TIF_RESTORE_SIGMASK)
-#define _TIF_FREEZE             (1<<TIF_FREEZE)
-#define _TIF_IRQ_SYNC           (1<<TIF_IRQ_SYNC)
+#define _TIF_FREEZE             (1<<TIF_FREEZE)
+#define _TIF_IRQ_SYNC           (1<<TIF_IRQ_SYNC)
+#define _TIF_NOTIFY_RESUME      (1<<TIF_NOTIFY_RESUME)
+#define _TIF_SINGLESTEP         (1<<TIF_SINGLESTEP)
 
 #define _TIF_WORK_MASK          0x0000FFFE      /* work to do on interrupt/exception return */
 
diff --git a/arch/blackfin/include/asm/time.h b/arch/blackfin/include/asm/time.h
index 589e937ed1eb..9ca7db844d10 100644
--- a/arch/blackfin/include/asm/time.h
+++ b/arch/blackfin/include/asm/time.h
@@ -23,9 +23,7 @@
  */
 
 #ifndef CONFIG_CPU_FREQ
-#define TIME_SCALE 1
-#define __bfin_cycles_off (0)
-#define __bfin_cycles_mod (0)
+# define TIME_SCALE 1
 #else
 /*
  * Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 .
@@ -33,9 +31,16 @@
  * adjust the Core Timer Presale Register. This way we don't lose time.
  */
 #define TIME_SCALE 4
+
+# ifdef CONFIG_CYCLES_CLOCKSOURCE
 extern unsigned long long __bfin_cycles_off;
 extern unsigned int __bfin_cycles_mod;
+# endif
+#endif
+
+#if defined(CONFIG_TICKSOURCE_CORETMR)
+extern void bfin_coretmr_init(void);
+extern void bfin_coretmr_clockevent_init(void);
 #endif
 
-extern void __init setup_core_timer(void);
 #endif
diff --git a/arch/blackfin/include/asm/trace.h b/arch/blackfin/include/asm/trace.h
index 609ad3c84189..dc0aa55ae773 100644
--- a/arch/blackfin/include/asm/trace.h
+++ b/arch/blackfin/include/asm/trace.h
@@ -28,6 +28,8 @@ extern unsigned long software_trace_buff[];
 
 #ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
 
+#define trace_buffer_init() bfin_write_TBUFCTL(BFIN_TRACE_INIT)
+
 #define trace_buffer_save(x) \
         do { \
                 (x) = bfin_read_TBUFCTL(); \
diff --git a/arch/blackfin/include/asm/uaccess.h b/arch/blackfin/include/asm/uaccess.h
index c03b8532aad3..1c0d190adaef 100644
--- a/arch/blackfin/include/asm/uaccess.h
+++ b/arch/blackfin/include/asm/uaccess.h
@@ -17,9 +17,7 @@
 #include <linux/string.h>
 
 #include <asm/segment.h>
-#ifdef CONFIG_ACCESS_CHECK
-# include <asm/bfin-global.h>
-#endif
+#include <asm/sections.h>
 
 #define get_ds()        (KERNEL_DS)
 #define get_fs()        (current_thread_info()->addr_limit)
diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h
index 779be02a910a..22886cbdae7a 100644
--- a/arch/blackfin/include/asm/unistd.h
+++ b/arch/blackfin/include/asm/unistd.h
@@ -388,8 +388,9 @@
 #define __NR_pwritev            367
 #define __NR_rt_tgsigqueueinfo  368
 #define __NR_perf_event_open    369
+#define __NR_recvmmsg           370
 
-#define __NR_syscall            370
+#define __NR_syscall            371
 #define NR_syscalls             __NR_syscall
 
 /* Old optional stuff no one actually uses */