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-rw-r--r--arch/arm/mm/proc-arm1020.S9
-rw-r--r--arch/arm/mm/proc-arm1020e.S9
-rw-r--r--arch/arm/mm/proc-arm1022.S9
-rw-r--r--arch/arm/mm/proc-arm1026.S9
-rw-r--r--arch/arm/mm/proc-arm6_7.S15
-rw-r--r--arch/arm/mm/proc-arm720.S12
-rw-r--r--arch/arm/mm/proc-arm920.S9
-rw-r--r--arch/arm/mm/proc-arm922.S9
-rw-r--r--arch/arm/mm/proc-arm925.S10
-rw-r--r--arch/arm/mm/proc-arm926.S9
-rw-r--r--arch/arm/mm/proc-sa110.S11
-rw-r--r--arch/arm/mm/proc-sa1100.S11
-rw-r--r--arch/arm/mm/proc-v6.S7
13 files changed, 129 insertions, 0 deletions
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 959588884fa5..b9abbafca812 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -3,6 +3,7 @@
3 * 3 *
4 * Copyright (C) 2000 ARM Limited 4 * Copyright (C) 2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
6 * 7 *
7 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
@@ -101,7 +102,9 @@ ENTRY(cpu_arm1020_reset)
101 mov ip, #0 102 mov ip, #0
102 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 103 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
103 mcr p15, 0, ip, c7, c10, 4 @ drain WB 104 mcr p15, 0, ip, c7, c10, 4 @ drain WB
105#ifdef CONFIG_MMU
104 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 106 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
107#endif
105 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 108 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
106 bic ip, ip, #0x000f @ ............wcam 109 bic ip, ip, #0x000f @ ............wcam
107 bic ip, ip, #0x1100 @ ...i...s........ 110 bic ip, ip, #0x1100 @ ...i...s........
@@ -359,6 +362,7 @@ ENTRY(cpu_arm1020_dcache_clean_area)
359 */ 362 */
360 .align 5 363 .align 5
361ENTRY(cpu_arm1020_switch_mm) 364ENTRY(cpu_arm1020_switch_mm)
365#ifdef CONFIG_MMU
362#ifndef CONFIG_CPU_DCACHE_DISABLE 366#ifndef CONFIG_CPU_DCACHE_DISABLE
363 mcr p15, 0, r3, c7, c10, 4 367 mcr p15, 0, r3, c7, c10, 4
364 mov r1, #0xF @ 16 segments 368 mov r1, #0xF @ 16 segments
@@ -383,6 +387,7 @@ ENTRY(cpu_arm1020_switch_mm)
383 mcr p15, 0, r1, c7, c10, 4 @ drain WB 387 mcr p15, 0, r1, c7, c10, 4 @ drain WB
384 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 388 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
385 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs 389 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
390#endif /* CONFIG_MMU */
386 mov pc, lr 391 mov pc, lr
387 392
388/* 393/*
@@ -392,6 +397,7 @@ ENTRY(cpu_arm1020_switch_mm)
392 */ 397 */
393 .align 5 398 .align 5
394ENTRY(cpu_arm1020_set_pte) 399ENTRY(cpu_arm1020_set_pte)
400#ifdef CONFIG_MMU
395 str r1, [r0], #-2048 @ linux version 401 str r1, [r0], #-2048 @ linux version
396 402
397 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 403 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -421,6 +427,7 @@ ENTRY(cpu_arm1020_set_pte)
421 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 427 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
422#endif 428#endif
423 mcr p15, 0, r0, c7, c10, 4 @ drain WB 429 mcr p15, 0, r0, c7, c10, 4 @ drain WB
430#endif /* CONFIG_MMU */
424 mov pc, lr 431 mov pc, lr
425 432
426 __INIT 433 __INIT
@@ -430,7 +437,9 @@ __arm1020_setup:
430 mov r0, #0 437 mov r0, #0
431 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 438 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
432 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 439 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
440#ifdef CONFIG_MMU
433 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 441 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
442#endif
434 mrc p15, 0, r0, c1, c0 @ get control register v4 443 mrc p15, 0, r0, c1, c0 @ get control register v4
435 ldr r5, arm1020_cr1_clear 444 ldr r5, arm1020_cr1_clear
436 bic r0, r0, r5 445 bic r0, r0, r5
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index be6d081ff2b7..bcd5ee022e00 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -3,6 +3,7 @@
3 * 3 *
4 * Copyright (C) 2000 ARM Limited 4 * Copyright (C) 2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
6 * 7 *
7 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
@@ -101,7 +102,9 @@ ENTRY(cpu_arm1020e_reset)
101 mov ip, #0 102 mov ip, #0
102 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 103 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
103 mcr p15, 0, ip, c7, c10, 4 @ drain WB 104 mcr p15, 0, ip, c7, c10, 4 @ drain WB
105#ifdef CONFIG_MMU
104 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 106 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
107#endif
105 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 108 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
106 bic ip, ip, #0x000f @ ............wcam 109 bic ip, ip, #0x000f @ ............wcam
107 bic ip, ip, #0x1100 @ ...i...s........ 110 bic ip, ip, #0x1100 @ ...i...s........
@@ -344,6 +347,7 @@ ENTRY(cpu_arm1020e_dcache_clean_area)
344 */ 347 */
345 .align 5 348 .align 5
346ENTRY(cpu_arm1020e_switch_mm) 349ENTRY(cpu_arm1020e_switch_mm)
350#ifdef CONFIG_MMU
347#ifndef CONFIG_CPU_DCACHE_DISABLE 351#ifndef CONFIG_CPU_DCACHE_DISABLE
348 mcr p15, 0, r3, c7, c10, 4 352 mcr p15, 0, r3, c7, c10, 4
349 mov r1, #0xF @ 16 segments 353 mov r1, #0xF @ 16 segments
@@ -367,6 +371,7 @@ ENTRY(cpu_arm1020e_switch_mm)
367 mcr p15, 0, r1, c7, c10, 4 @ drain WB 371 mcr p15, 0, r1, c7, c10, 4 @ drain WB
368 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 372 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
369 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs 373 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
374#endif
370 mov pc, lr 375 mov pc, lr
371 376
372/* 377/*
@@ -376,6 +381,7 @@ ENTRY(cpu_arm1020e_switch_mm)
376 */ 381 */
377 .align 5 382 .align 5
378ENTRY(cpu_arm1020e_set_pte) 383ENTRY(cpu_arm1020e_set_pte)
384#ifdef CONFIG_MMU
379 str r1, [r0], #-2048 @ linux version 385 str r1, [r0], #-2048 @ linux version
380 386
381 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 387 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -403,6 +409,7 @@ ENTRY(cpu_arm1020e_set_pte)
403#ifndef CONFIG_CPU_DCACHE_DISABLE 409#ifndef CONFIG_CPU_DCACHE_DISABLE
404 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 410 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
405#endif 411#endif
412#endif /* CONFIG_MMU */
406 mov pc, lr 413 mov pc, lr
407 414
408 __INIT 415 __INIT
@@ -412,7 +419,9 @@ __arm1020e_setup:
412 mov r0, #0 419 mov r0, #0
413 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 420 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
414 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 421 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
422#ifdef CONFIG_MMU
415 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 423 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
424#endif
416 mrc p15, 0, r0, c1, c0 @ get control register v4 425 mrc p15, 0, r0, c1, c0 @ get control register v4
417 ldr r5, arm1020e_cr1_clear 426 ldr r5, arm1020e_cr1_clear
418 bic r0, r0, r5 427 bic r0, r0, r5
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index f778545d57a2..b0ccff4fadd2 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -3,6 +3,7 @@
3 * 3 *
4 * Copyright (C) 2000 ARM Limited 4 * Copyright (C) 2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
6 * 7 *
7 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
@@ -90,7 +91,9 @@ ENTRY(cpu_arm1022_reset)
90 mov ip, #0 91 mov ip, #0
91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 92 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
92 mcr p15, 0, ip, c7, c10, 4 @ drain WB 93 mcr p15, 0, ip, c7, c10, 4 @ drain WB
94#ifdef CONFIG_MMU
93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 95 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
96#endif
94 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 97 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
95 bic ip, ip, #0x000f @ ............wcam 98 bic ip, ip, #0x000f @ ............wcam
96 bic ip, ip, #0x1100 @ ...i...s........ 99 bic ip, ip, #0x1100 @ ...i...s........
@@ -333,6 +336,7 @@ ENTRY(cpu_arm1022_dcache_clean_area)
333 */ 336 */
334 .align 5 337 .align 5
335ENTRY(cpu_arm1022_switch_mm) 338ENTRY(cpu_arm1022_switch_mm)
339#ifdef CONFIG_MMU
336#ifndef CONFIG_CPU_DCACHE_DISABLE 340#ifndef CONFIG_CPU_DCACHE_DISABLE
337 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments 341 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
3381: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries 3421: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
@@ -349,6 +353,7 @@ ENTRY(cpu_arm1022_switch_mm)
349 mcr p15, 0, r1, c7, c10, 4 @ drain WB 353 mcr p15, 0, r1, c7, c10, 4 @ drain WB
350 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 354 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
351 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs 355 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
356#endif
352 mov pc, lr 357 mov pc, lr
353 358
354/* 359/*
@@ -358,6 +363,7 @@ ENTRY(cpu_arm1022_switch_mm)
358 */ 363 */
359 .align 5 364 .align 5
360ENTRY(cpu_arm1022_set_pte) 365ENTRY(cpu_arm1022_set_pte)
366#ifdef CONFIG_MMU
361 str r1, [r0], #-2048 @ linux version 367 str r1, [r0], #-2048 @ linux version
362 368
363 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 369 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -385,6 +391,7 @@ ENTRY(cpu_arm1022_set_pte)
385#ifndef CONFIG_CPU_DCACHE_DISABLE 391#ifndef CONFIG_CPU_DCACHE_DISABLE
386 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 392 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
387#endif 393#endif
394#endif /* CONFIG_MMU */
388 mov pc, lr 395 mov pc, lr
389 396
390 __INIT 397 __INIT
@@ -394,7 +401,9 @@ __arm1022_setup:
394 mov r0, #0 401 mov r0, #0
395 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 402 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
396 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 403 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
404#ifdef CONFIG_MMU
397 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 405 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
406#endif
398 mrc p15, 0, r0, c1, c0 @ get control register v4 407 mrc p15, 0, r0, c1, c0 @ get control register v4
399 ldr r5, arm1022_cr1_clear 408 ldr r5, arm1022_cr1_clear
400 bic r0, r0, r5 409 bic r0, r0, r5
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 148c111fde73..abe850c9a641 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -3,6 +3,7 @@
3 * 3 *
4 * Copyright (C) 2000 ARM Limited 4 * Copyright (C) 2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
6 * 7 *
7 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
@@ -90,7 +91,9 @@ ENTRY(cpu_arm1026_reset)
90 mov ip, #0 91 mov ip, #0
91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 92 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
92 mcr p15, 0, ip, c7, c10, 4 @ drain WB 93 mcr p15, 0, ip, c7, c10, 4 @ drain WB
94#ifdef CONFIG_MMU
93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 95 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
96#endif
94 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 97 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
95 bic ip, ip, #0x000f @ ............wcam 98 bic ip, ip, #0x000f @ ............wcam
96 bic ip, ip, #0x1100 @ ...i...s........ 99 bic ip, ip, #0x1100 @ ...i...s........
@@ -327,6 +330,7 @@ ENTRY(cpu_arm1026_dcache_clean_area)
327 */ 330 */
328 .align 5 331 .align 5
329ENTRY(cpu_arm1026_switch_mm) 332ENTRY(cpu_arm1026_switch_mm)
333#ifdef CONFIG_MMU
330 mov r1, #0 334 mov r1, #0
331#ifndef CONFIG_CPU_DCACHE_DISABLE 335#ifndef CONFIG_CPU_DCACHE_DISABLE
3321: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate 3361: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate
@@ -338,6 +342,7 @@ ENTRY(cpu_arm1026_switch_mm)
338 mcr p15, 0, r1, c7, c10, 4 @ drain WB 342 mcr p15, 0, r1, c7, c10, 4 @ drain WB
339 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 343 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
340 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs 344 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
345#endif
341 mov pc, lr 346 mov pc, lr
342 347
343/* 348/*
@@ -347,6 +352,7 @@ ENTRY(cpu_arm1026_switch_mm)
347 */ 352 */
348 .align 5 353 .align 5
349ENTRY(cpu_arm1026_set_pte) 354ENTRY(cpu_arm1026_set_pte)
355#ifdef CONFIG_MMU
350 str r1, [r0], #-2048 @ linux version 356 str r1, [r0], #-2048 @ linux version
351 357
352 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 358 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -374,6 +380,7 @@ ENTRY(cpu_arm1026_set_pte)
374#ifndef CONFIG_CPU_DCACHE_DISABLE 380#ifndef CONFIG_CPU_DCACHE_DISABLE
375 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 381 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
376#endif 382#endif
383#endif /* CONFIG_MMU */
377 mov pc, lr 384 mov pc, lr
378 385
379 386
@@ -384,8 +391,10 @@ __arm1026_setup:
384 mov r0, #0 391 mov r0, #0
385 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 392 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
386 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 393 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
394#ifdef CONFIG_MMU
387 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 395 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
388 mcr p15, 0, r4, c2, c0 @ load page table pointer 396 mcr p15, 0, r4, c2, c0 @ load page table pointer
397#endif
389#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 398#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
390 mov r0, #4 @ explicitly disable writeback 399 mov r0, #4 @ explicitly disable writeback
391 mcr p15, 7, r0, c15, c0, 0 400 mcr p15, 7, r0, c15, c0, 0
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 540359b475d0..7a705edfa4b2 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -2,6 +2,7 @@
2 * linux/arch/arm/mm/proc-arm6,7.S 2 * linux/arch/arm/mm/proc-arm6,7.S
3 * 3 *
4 * Copyright (C) 1997-2000 Russell King 4 * Copyright (C) 1997-2000 Russell King
5 * hacked for non-paged-MM by Hyok S. Choi, 2003.
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
@@ -199,10 +200,12 @@ ENTRY(cpu_arm7_do_idle)
199 */ 200 */
200ENTRY(cpu_arm6_switch_mm) 201ENTRY(cpu_arm6_switch_mm)
201ENTRY(cpu_arm7_switch_mm) 202ENTRY(cpu_arm7_switch_mm)
203#ifdef CONFIG_MMU
202 mov r1, #0 204 mov r1, #0
203 mcr p15, 0, r1, c7, c0, 0 @ flush cache 205 mcr p15, 0, r1, c7, c0, 0 @ flush cache
204 mcr p15, 0, r0, c2, c0, 0 @ update page table ptr 206 mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
205 mcr p15, 0, r1, c5, c0, 0 @ flush TLBs 207 mcr p15, 0, r1, c5, c0, 0 @ flush TLBs
208#endif
206 mov pc, lr 209 mov pc, lr
207 210
208/* 211/*
@@ -214,6 +217,7 @@ ENTRY(cpu_arm7_switch_mm)
214 .align 5 217 .align 5
215ENTRY(cpu_arm6_set_pte) 218ENTRY(cpu_arm6_set_pte)
216ENTRY(cpu_arm7_set_pte) 219ENTRY(cpu_arm7_set_pte)
220#ifdef CONFIG_MMU
217 str r1, [r0], #-2048 @ linux version 221 str r1, [r0], #-2048 @ linux version
218 222
219 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 223 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -232,6 +236,7 @@ ENTRY(cpu_arm7_set_pte)
232 movne r2, #0 236 movne r2, #0
233 237
234 str r2, [r0] @ hardware version 238 str r2, [r0] @ hardware version
239#endif /* CONFIG_MMU */
235 mov pc, lr 240 mov pc, lr
236 241
237/* 242/*
@@ -243,7 +248,9 @@ ENTRY(cpu_arm6_reset)
243ENTRY(cpu_arm7_reset) 248ENTRY(cpu_arm7_reset)
244 mov r1, #0 249 mov r1, #0
245 mcr p15, 0, r1, c7, c0, 0 @ flush cache 250 mcr p15, 0, r1, c7, c0, 0 @ flush cache
251#ifdef CONFIG_MMU
246 mcr p15, 0, r1, c5, c0, 0 @ flush TLB 252 mcr p15, 0, r1, c5, c0, 0 @ flush TLB
253#endif
247 mov r1, #0x30 254 mov r1, #0x30
248 mcr p15, 0, r1, c1, c0, 0 @ turn off MMU etc 255 mcr p15, 0, r1, c1, c0, 0 @ turn off MMU etc
249 mov pc, r0 256 mov pc, r0
@@ -253,19 +260,27 @@ ENTRY(cpu_arm7_reset)
253 .type __arm6_setup, #function 260 .type __arm6_setup, #function
254__arm6_setup: mov r0, #0 261__arm6_setup: mov r0, #0
255 mcr p15, 0, r0, c7, c0 @ flush caches on v3 262 mcr p15, 0, r0, c7, c0 @ flush caches on v3
263#ifdef CONFIG_MMU
256 mcr p15, 0, r0, c5, c0 @ flush TLBs on v3 264 mcr p15, 0, r0, c5, c0 @ flush TLBs on v3
257 mov r0, #0x3d @ . ..RS BLDP WCAM 265 mov r0, #0x3d @ . ..RS BLDP WCAM
258 orr r0, r0, #0x100 @ . ..01 0011 1101 266 orr r0, r0, #0x100 @ . ..01 0011 1101
267#else
268 mov r0, #0x3c @ . ..RS BLDP WCA.
269#endif
259 mov pc, lr 270 mov pc, lr
260 .size __arm6_setup, . - __arm6_setup 271 .size __arm6_setup, . - __arm6_setup
261 272
262 .type __arm7_setup, #function 273 .type __arm7_setup, #function
263__arm7_setup: mov r0, #0 274__arm7_setup: mov r0, #0
264 mcr p15, 0, r0, c7, c0 @ flush caches on v3 275 mcr p15, 0, r0, c7, c0 @ flush caches on v3
276#ifdef CONFIG_MMU
265 mcr p15, 0, r0, c5, c0 @ flush TLBs on v3 277 mcr p15, 0, r0, c5, c0 @ flush TLBs on v3
266 mcr p15, 0, r0, c3, c0 @ load domain access register 278 mcr p15, 0, r0, c3, c0 @ load domain access register
267 mov r0, #0x7d @ . ..RS BLDP WCAM 279 mov r0, #0x7d @ . ..RS BLDP WCAM
268 orr r0, r0, #0x100 @ . ..01 0111 1101 280 orr r0, r0, #0x100 @ . ..01 0111 1101
281#else
282 mov r0, #0x7c @ . ..RS BLDP WCA.
283#endif
269 mov pc, lr 284 mov pc, lr
270 .size __arm7_setup, . - __arm7_setup 285 .size __arm7_setup, . - __arm7_setup
271 286
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index 26f00ee2ad9a..86102467d37f 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -4,6 +4,7 @@
4 * Copyright (C) 2000 Steve Hill (sjhill@cotw.com) 4 * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
5 * Rob Scott (rscott@mtrob.fdns.net) 5 * Rob Scott (rscott@mtrob.fdns.net)
6 * Copyright (C) 2000 ARM Limited, Deep Blue Solutions Ltd. 6 * Copyright (C) 2000 ARM Limited, Deep Blue Solutions Ltd.
7 * hacked for non-paged-MM by Hyok S. Choi, 2004.
7 * 8 *
8 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by 10 * it under the terms of the GNU General Public License as published by
@@ -29,6 +30,7 @@
29 * out of 'proc-arm6,7.S' per RMK discussion 30 * out of 'proc-arm6,7.S' per RMK discussion
30 * 07-25-2000 SJH Added idle function. 31 * 07-25-2000 SJH Added idle function.
31 * 08-25-2000 DBS Updated for integration of ARM Ltd version. 32 * 08-25-2000 DBS Updated for integration of ARM Ltd version.
33 * 04-20-2004 HSC modified for non-paged memory management mode.
32 */ 34 */
33#include <linux/linkage.h> 35#include <linux/linkage.h>
34#include <linux/init.h> 36#include <linux/init.h>
@@ -75,10 +77,12 @@ ENTRY(cpu_arm720_do_idle)
75 * the new. 77 * the new.
76 */ 78 */
77ENTRY(cpu_arm720_switch_mm) 79ENTRY(cpu_arm720_switch_mm)
80#ifdef CONFIG_MMU
78 mov r1, #0 81 mov r1, #0
79 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache 82 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache
80 mcr p15, 0, r0, c2, c0, 0 @ update page table ptr 83 mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
81 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4) 84 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4)
85#endif
82 mov pc, lr 86 mov pc, lr
83 87
84/* 88/*
@@ -89,6 +93,7 @@ ENTRY(cpu_arm720_switch_mm)
89 */ 93 */
90 .align 5 94 .align 5
91ENTRY(cpu_arm720_set_pte) 95ENTRY(cpu_arm720_set_pte)
96#ifdef CONFIG_MMU
92 str r1, [r0], #-2048 @ linux version 97 str r1, [r0], #-2048 @ linux version
93 98
94 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 99 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -107,6 +112,7 @@ ENTRY(cpu_arm720_set_pte)
107 movne r2, #0 112 movne r2, #0
108 113
109 str r2, [r0] @ hardware version 114 str r2, [r0] @ hardware version
115#endif
110 mov pc, lr 116 mov pc, lr
111 117
112/* 118/*
@@ -117,7 +123,9 @@ ENTRY(cpu_arm720_set_pte)
117ENTRY(cpu_arm720_reset) 123ENTRY(cpu_arm720_reset)
118 mov ip, #0 124 mov ip, #0
119 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache 125 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
126#ifdef CONFIG_MMU
120 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4) 127 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
128#endif
121 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register 129 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
122 bic ip, ip, #0x000f @ ............wcam 130 bic ip, ip, #0x000f @ ............wcam
123 bic ip, ip, #0x2100 @ ..v....s........ 131 bic ip, ip, #0x2100 @ ..v....s........
@@ -130,7 +138,9 @@ ENTRY(cpu_arm720_reset)
130__arm710_setup: 138__arm710_setup:
131 mov r0, #0 139 mov r0, #0
132 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches 140 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
141#ifdef CONFIG_MMU
133 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4) 142 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
143#endif
134 mrc p15, 0, r0, c1, c0 @ get control register 144 mrc p15, 0, r0, c1, c0 @ get control register
135 ldr r5, arm710_cr1_clear 145 ldr r5, arm710_cr1_clear
136 bic r0, r0, r5 146 bic r0, r0, r5
@@ -156,7 +166,9 @@ arm710_cr1_set:
156__arm720_setup: 166__arm720_setup:
157 mov r0, #0 167 mov r0, #0
158 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches 168 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
169#ifdef CONFIG_MMU
159 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4) 170 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
171#endif
160 mrc p15, 0, r0, c1, c0 @ get control register 172 mrc p15, 0, r0, c1, c0 @ get control register
161 ldr r5, arm720_cr1_clear 173 ldr r5, arm720_cr1_clear
162 bic r0, r0, r5 174 bic r0, r0, r5
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index a17f79e0199c..31dc839ba07c 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -3,6 +3,7 @@
3 * 3 *
4 * Copyright (C) 1999,2000 ARM Limited 4 * Copyright (C) 1999,2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
6 * 7 *
7 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
@@ -97,7 +98,9 @@ ENTRY(cpu_arm920_reset)
97 mov ip, #0 98 mov ip, #0
98 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 99 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
99 mcr p15, 0, ip, c7, c10, 4 @ drain WB 100 mcr p15, 0, ip, c7, c10, 4 @ drain WB
101#ifdef CONFIG_MMU
100 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 102 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
103#endif
101 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 104 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
102 bic ip, ip, #0x000f @ ............wcam 105 bic ip, ip, #0x000f @ ............wcam
103 bic ip, ip, #0x1100 @ ...i...s........ 106 bic ip, ip, #0x1100 @ ...i...s........
@@ -317,6 +320,7 @@ ENTRY(cpu_arm920_dcache_clean_area)
317 */ 320 */
318 .align 5 321 .align 5
319ENTRY(cpu_arm920_switch_mm) 322ENTRY(cpu_arm920_switch_mm)
323#ifdef CONFIG_MMU
320 mov ip, #0 324 mov ip, #0
321#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 325#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
322 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 326 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
@@ -337,6 +341,7 @@ ENTRY(cpu_arm920_switch_mm)
337 mcr p15, 0, ip, c7, c10, 4 @ drain WB 341 mcr p15, 0, ip, c7, c10, 4 @ drain WB
338 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 342 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
339 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 343 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
344#endif
340 mov pc, lr 345 mov pc, lr
341 346
342/* 347/*
@@ -346,6 +351,7 @@ ENTRY(cpu_arm920_switch_mm)
346 */ 351 */
347 .align 5 352 .align 5
348ENTRY(cpu_arm920_set_pte) 353ENTRY(cpu_arm920_set_pte)
354#ifdef CONFIG_MMU
349 str r1, [r0], #-2048 @ linux version 355 str r1, [r0], #-2048 @ linux version
350 356
351 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 357 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -372,6 +378,7 @@ ENTRY(cpu_arm920_set_pte)
372 mov r0, r0 378 mov r0, r0
373 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 379 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
374 mcr p15, 0, r0, c7, c10, 4 @ drain WB 380 mcr p15, 0, r0, c7, c10, 4 @ drain WB
381#endif /* CONFIG_MMU */
375 mov pc, lr 382 mov pc, lr
376 383
377 __INIT 384 __INIT
@@ -381,7 +388,9 @@ __arm920_setup:
381 mov r0, #0 388 mov r0, #0
382 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 389 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
383 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 390 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
391#ifdef CONFIG_MMU
384 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 392 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
393#endif
385 mrc p15, 0, r0, c1, c0 @ get control register v4 394 mrc p15, 0, r0, c1, c0 @ get control register v4
386 ldr r5, arm920_cr1_clear 395 ldr r5, arm920_cr1_clear
387 bic r0, r0, r5 396 bic r0, r0, r5
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index bbde4a024a48..9e57c34f5c09 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -4,6 +4,7 @@
4 * Copyright (C) 1999,2000 ARM Limited 4 * Copyright (C) 1999,2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * Copyright (C) 2001 Altera Corporation 6 * Copyright (C) 2001 Altera Corporation
7 * hacked for non-paged-MM by Hyok S. Choi, 2003.
7 * 8 *
8 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by 10 * it under the terms of the GNU General Public License as published by
@@ -99,7 +100,9 @@ ENTRY(cpu_arm922_reset)
99 mov ip, #0 100 mov ip, #0
100 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 101 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
101 mcr p15, 0, ip, c7, c10, 4 @ drain WB 102 mcr p15, 0, ip, c7, c10, 4 @ drain WB
103#ifdef CONFIG_MMU
102 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 104 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
105#endif
103 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 106 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
104 bic ip, ip, #0x000f @ ............wcam 107 bic ip, ip, #0x000f @ ............wcam
105 bic ip, ip, #0x1100 @ ...i...s........ 108 bic ip, ip, #0x1100 @ ...i...s........
@@ -321,6 +324,7 @@ ENTRY(cpu_arm922_dcache_clean_area)
321 */ 324 */
322 .align 5 325 .align 5
323ENTRY(cpu_arm922_switch_mm) 326ENTRY(cpu_arm922_switch_mm)
327#ifdef CONFIG_MMU
324 mov ip, #0 328 mov ip, #0
325#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 329#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
326 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 330 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
@@ -341,6 +345,7 @@ ENTRY(cpu_arm922_switch_mm)
341 mcr p15, 0, ip, c7, c10, 4 @ drain WB 345 mcr p15, 0, ip, c7, c10, 4 @ drain WB
342 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 346 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
343 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 347 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
348#endif
344 mov pc, lr 349 mov pc, lr
345 350
346/* 351/*
@@ -350,6 +355,7 @@ ENTRY(cpu_arm922_switch_mm)
350 */ 355 */
351 .align 5 356 .align 5
352ENTRY(cpu_arm922_set_pte) 357ENTRY(cpu_arm922_set_pte)
358#ifdef CONFIG_MMU
353 str r1, [r0], #-2048 @ linux version 359 str r1, [r0], #-2048 @ linux version
354 360
355 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 361 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -376,6 +382,7 @@ ENTRY(cpu_arm922_set_pte)
376 mov r0, r0 382 mov r0, r0
377 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 383 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
378 mcr p15, 0, r0, c7, c10, 4 @ drain WB 384 mcr p15, 0, r0, c7, c10, 4 @ drain WB
385#endif /* CONFIG_MMU */
379 mov pc, lr 386 mov pc, lr
380 387
381 __INIT 388 __INIT
@@ -385,7 +392,9 @@ __arm922_setup:
385 mov r0, #0 392 mov r0, #0
386 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 393 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
387 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 394 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
395#ifdef CONFIG_MMU
388 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 396 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
397#endif
389 mrc p15, 0, r0, c1, c0 @ get control register v4 398 mrc p15, 0, r0, c1, c0 @ get control register v4
390 ldr r5, arm922_cr1_clear 399 ldr r5, arm922_cr1_clear
391 bic r0, r0, r5 400 bic r0, r0, r5
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 224ce226a01b..8d47c9f3f931 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -9,6 +9,8 @@
9 * Update for Linux-2.6 and cache flush improvements 9 * Update for Linux-2.6 and cache flush improvements
10 * Copyright (C) 2004 Nokia Corporation by Tony Lindgren <tony@atomide.com> 10 * Copyright (C) 2004 Nokia Corporation by Tony Lindgren <tony@atomide.com>
11 * 11 *
12 * hacked for non-paged-MM by Hyok S. Choi, 2004.
13 *
12 * This program is free software; you can redistribute it and/or modify 14 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by 15 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or 16 * the Free Software Foundation; either version 2 of the License, or
@@ -122,7 +124,9 @@ ENTRY(cpu_arm925_reset)
122 mov ip, #0 124 mov ip, #0
123 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 125 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
124 mcr p15, 0, ip, c7, c10, 4 @ drain WB 126 mcr p15, 0, ip, c7, c10, 4 @ drain WB
127#ifdef CONFIG_MMU
125 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 128 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
129#endif
126 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 130 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
127 bic ip, ip, #0x000f @ ............wcam 131 bic ip, ip, #0x000f @ ............wcam
128 bic ip, ip, #0x1100 @ ...i...s........ 132 bic ip, ip, #0x1100 @ ...i...s........
@@ -369,6 +373,7 @@ ENTRY(cpu_arm925_dcache_clean_area)
369 */ 373 */
370 .align 5 374 .align 5
371ENTRY(cpu_arm925_switch_mm) 375ENTRY(cpu_arm925_switch_mm)
376#ifdef CONFIG_MMU
372 mov ip, #0 377 mov ip, #0
373#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 378#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
374 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 379 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
@@ -383,6 +388,7 @@ ENTRY(cpu_arm925_switch_mm)
383 mcr p15, 0, ip, c7, c10, 4 @ drain WB 388 mcr p15, 0, ip, c7, c10, 4 @ drain WB
384 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 389 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
385 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 390 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
391#endif
386 mov pc, lr 392 mov pc, lr
387 393
388/* 394/*
@@ -392,6 +398,7 @@ ENTRY(cpu_arm925_switch_mm)
392 */ 398 */
393 .align 5 399 .align 5
394ENTRY(cpu_arm925_set_pte) 400ENTRY(cpu_arm925_set_pte)
401#ifdef CONFIG_MMU
395 str r1, [r0], #-2048 @ linux version 402 str r1, [r0], #-2048 @ linux version
396 403
397 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 404 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -420,6 +427,7 @@ ENTRY(cpu_arm925_set_pte)
420 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 427 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
421#endif 428#endif
422 mcr p15, 0, r0, c7, c10, 4 @ drain WB 429 mcr p15, 0, r0, c7, c10, 4 @ drain WB
430#endif /* CONFIG_MMU */
423 mov pc, lr 431 mov pc, lr
424 432
425 __INIT 433 __INIT
@@ -438,7 +446,9 @@ __arm925_setup:
438 mov r0, #0 446 mov r0, #0
439 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 447 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
440 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 448 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
449#ifdef CONFIG_MMU
441 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 450 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
451#endif
442 452
443#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 453#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
444 mov r0, #4 @ disable write-back on caches explicitly 454 mov r0, #4 @ disable write-back on caches explicitly
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 4e2a087cf388..cb4d8f33d2a3 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -3,6 +3,7 @@
3 * 3 *
4 * Copyright (C) 1999-2001 ARM Limited 4 * Copyright (C) 1999-2001 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
6 * 7 *
7 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
@@ -85,7 +86,9 @@ ENTRY(cpu_arm926_reset)
85 mov ip, #0 86 mov ip, #0
86 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 87 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
87 mcr p15, 0, ip, c7, c10, 4 @ drain WB 88 mcr p15, 0, ip, c7, c10, 4 @ drain WB
89#ifdef CONFIG_MMU
88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 90 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
91#endif
89 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 92 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
90 bic ip, ip, #0x000f @ ............wcam 93 bic ip, ip, #0x000f @ ............wcam
91 bic ip, ip, #0x1100 @ ...i...s........ 94 bic ip, ip, #0x1100 @ ...i...s........
@@ -329,6 +332,7 @@ ENTRY(cpu_arm926_dcache_clean_area)
329 */ 332 */
330 .align 5 333 .align 5
331ENTRY(cpu_arm926_switch_mm) 334ENTRY(cpu_arm926_switch_mm)
335#ifdef CONFIG_MMU
332 mov ip, #0 336 mov ip, #0
333#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 337#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
334 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 338 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
@@ -341,6 +345,7 @@ ENTRY(cpu_arm926_switch_mm)
341 mcr p15, 0, ip, c7, c10, 4 @ drain WB 345 mcr p15, 0, ip, c7, c10, 4 @ drain WB
342 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 346 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
343 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 347 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
348#endif
344 mov pc, lr 349 mov pc, lr
345 350
346/* 351/*
@@ -350,6 +355,7 @@ ENTRY(cpu_arm926_switch_mm)
350 */ 355 */
351 .align 5 356 .align 5
352ENTRY(cpu_arm926_set_pte) 357ENTRY(cpu_arm926_set_pte)
358#ifdef CONFIG_MMU
353 str r1, [r0], #-2048 @ linux version 359 str r1, [r0], #-2048 @ linux version
354 360
355 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 361 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -378,6 +384,7 @@ ENTRY(cpu_arm926_set_pte)
378 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 384 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
379#endif 385#endif
380 mcr p15, 0, r0, c7, c10, 4 @ drain WB 386 mcr p15, 0, r0, c7, c10, 4 @ drain WB
387#endif
381 mov pc, lr 388 mov pc, lr
382 389
383 __INIT 390 __INIT
@@ -387,7 +394,9 @@ __arm926_setup:
387 mov r0, #0 394 mov r0, #0
388 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 395 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
389 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 396 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
397#ifdef CONFIG_MMU
390 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 398 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
399#endif
391 400
392 401
393#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH 402#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index a2dd5ae1077d..5a760a2c629c 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -2,6 +2,7 @@
2 * linux/arch/arm/mm/proc-sa110.S 2 * linux/arch/arm/mm/proc-sa110.S
3 * 3 *
4 * Copyright (C) 1997-2002 Russell King 4 * Copyright (C) 1997-2002 Russell King
5 * hacked for non-paged-MM by Hyok S. Choi, 2003.
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
@@ -67,7 +68,9 @@ ENTRY(cpu_sa110_reset)
67 mov ip, #0 68 mov ip, #0
68 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 69 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
69 mcr p15, 0, ip, c7, c10, 4 @ drain WB 70 mcr p15, 0, ip, c7, c10, 4 @ drain WB
71#ifdef CONFIG_MMU
70 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 72 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
73#endif
71 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 74 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
72 bic ip, ip, #0x000f @ ............wcam 75 bic ip, ip, #0x000f @ ............wcam
73 bic ip, ip, #0x1100 @ ...i...s........ 76 bic ip, ip, #0x1100 @ ...i...s........
@@ -130,11 +133,15 @@ ENTRY(cpu_sa110_dcache_clean_area)
130 */ 133 */
131 .align 5 134 .align 5
132ENTRY(cpu_sa110_switch_mm) 135ENTRY(cpu_sa110_switch_mm)
136#ifdef CONFIG_MMU
133 str lr, [sp, #-4]! 137 str lr, [sp, #-4]!
134 bl v4wb_flush_kern_cache_all @ clears IP 138 bl v4wb_flush_kern_cache_all @ clears IP
135 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 139 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
136 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 140 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
137 ldr pc, [sp], #4 141 ldr pc, [sp], #4
142#else
143 mov pc, lr
144#endif
138 145
139/* 146/*
140 * cpu_sa110_set_pte(ptep, pte) 147 * cpu_sa110_set_pte(ptep, pte)
@@ -143,6 +150,7 @@ ENTRY(cpu_sa110_switch_mm)
143 */ 150 */
144 .align 5 151 .align 5
145ENTRY(cpu_sa110_set_pte) 152ENTRY(cpu_sa110_set_pte)
153#ifdef CONFIG_MMU
146 str r1, [r0], #-2048 @ linux version 154 str r1, [r0], #-2048 @ linux version
147 155
148 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 156 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -164,6 +172,7 @@ ENTRY(cpu_sa110_set_pte)
164 mov r0, r0 172 mov r0, r0
165 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 173 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
166 mcr p15, 0, r0, c7, c10, 4 @ drain WB 174 mcr p15, 0, r0, c7, c10, 4 @ drain WB
175#endif
167 mov pc, lr 176 mov pc, lr
168 177
169 __INIT 178 __INIT
@@ -173,7 +182,9 @@ __sa110_setup:
173 mov r10, #0 182 mov r10, #0
174 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4 183 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
175 mcr p15, 0, r10, c7, c10, 4 @ drain write buffer on v4 184 mcr p15, 0, r10, c7, c10, 4 @ drain write buffer on v4
185#ifdef CONFIG_MMU
176 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4 186 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
187#endif
177 mrc p15, 0, r0, c1, c0 @ get control register v4 188 mrc p15, 0, r0, c1, c0 @ get control register v4
178 ldr r5, sa110_cr1_clear 189 ldr r5, sa110_cr1_clear
179 bic r0, r0, r5 190 bic r0, r0, r5
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 777ad99c1439..0a2107ad4c32 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -2,6 +2,7 @@
2 * linux/arch/arm/mm/proc-sa1100.S 2 * linux/arch/arm/mm/proc-sa1100.S
3 * 3 *
4 * Copyright (C) 1997-2002 Russell King 4 * Copyright (C) 1997-2002 Russell King
5 * hacked for non-paged-MM by Hyok S. Choi, 2003.
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
@@ -77,7 +78,9 @@ ENTRY(cpu_sa1100_reset)
77 mov ip, #0 78 mov ip, #0
78 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 79 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
79 mcr p15, 0, ip, c7, c10, 4 @ drain WB 80 mcr p15, 0, ip, c7, c10, 4 @ drain WB
81#ifdef CONFIG_MMU
80 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 82 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
83#endif
81 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 84 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
82 bic ip, ip, #0x000f @ ............wcam 85 bic ip, ip, #0x000f @ ............wcam
83 bic ip, ip, #0x1100 @ ...i...s........ 86 bic ip, ip, #0x1100 @ ...i...s........
@@ -142,12 +145,16 @@ ENTRY(cpu_sa1100_dcache_clean_area)
142 */ 145 */
143 .align 5 146 .align 5
144ENTRY(cpu_sa1100_switch_mm) 147ENTRY(cpu_sa1100_switch_mm)
148#ifdef CONFIG_MMU
145 str lr, [sp, #-4]! 149 str lr, [sp, #-4]!
146 bl v4wb_flush_kern_cache_all @ clears IP 150 bl v4wb_flush_kern_cache_all @ clears IP
147 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB 151 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
148 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 152 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
149 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 153 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
150 ldr pc, [sp], #4 154 ldr pc, [sp], #4
155#else
156 mov pc, lr
157#endif
151 158
152/* 159/*
153 * cpu_sa1100_set_pte(ptep, pte) 160 * cpu_sa1100_set_pte(ptep, pte)
@@ -156,6 +163,7 @@ ENTRY(cpu_sa1100_switch_mm)
156 */ 163 */
157 .align 5 164 .align 5
158ENTRY(cpu_sa1100_set_pte) 165ENTRY(cpu_sa1100_set_pte)
166#ifdef CONFIG_MMU
159 str r1, [r0], #-2048 @ linux version 167 str r1, [r0], #-2048 @ linux version
160 168
161 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 169 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
@@ -177,6 +185,7 @@ ENTRY(cpu_sa1100_set_pte)
177 mov r0, r0 185 mov r0, r0
178 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 186 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
179 mcr p15, 0, r0, c7, c10, 4 @ drain WB 187 mcr p15, 0, r0, c7, c10, 4 @ drain WB
188#endif
180 mov pc, lr 189 mov pc, lr
181 190
182 __INIT 191 __INIT
@@ -186,7 +195,9 @@ __sa1100_setup:
186 mov r0, #0 195 mov r0, #0
187 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 196 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
188 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 197 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
198#ifdef CONFIG_MMU
189 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 199 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
200#endif
190 mrc p15, 0, r0, c1, c0 @ get control register v4 201 mrc p15, 0, r0, c1, c0 @ get control register v4
191 ldr r5, sa1100_cr1_clear 202 ldr r5, sa1100_cr1_clear
192 bic r0, r0, r5 203 bic r0, r0, r5
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 09b1a41a6de8..ca13d4d05f65 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -2,6 +2,7 @@
2 * linux/arch/arm/mm/proc-v6.S 2 * linux/arch/arm/mm/proc-v6.S
3 * 3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 * Modified by Catalin Marinas for noMMU support
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
@@ -88,6 +89,7 @@ ENTRY(cpu_v6_dcache_clean_area)
88 * - we are not using split page tables 89 * - we are not using split page tables
89 */ 90 */
90ENTRY(cpu_v6_switch_mm) 91ENTRY(cpu_v6_switch_mm)
92#ifdef CONFIG_MMU
91 mov r2, #0 93 mov r2, #0
92 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id 94 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
93#ifdef CONFIG_SMP 95#ifdef CONFIG_SMP
@@ -97,6 +99,7 @@ ENTRY(cpu_v6_switch_mm)
97 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer 99 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
98 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 100 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
99 mcr p15, 0, r1, c13, c0, 1 @ set context ID 101 mcr p15, 0, r1, c13, c0, 1 @ set context ID
102#endif
100 mov pc, lr 103 mov pc, lr
101 104
102/* 105/*
@@ -119,6 +122,7 @@ ENTRY(cpu_v6_switch_mm)
119 * 1111 0 1 1 r/w r/w 122 * 1111 0 1 1 r/w r/w
120 */ 123 */
121ENTRY(cpu_v6_set_pte) 124ENTRY(cpu_v6_set_pte)
125#ifdef CONFIG_MMU
122 str r1, [r0], #-2048 @ linux version 126 str r1, [r0], #-2048 @ linux version
123 127
124 bic r2, r1, #0x000003f0 128 bic r2, r1, #0x000003f0
@@ -145,6 +149,7 @@ ENTRY(cpu_v6_set_pte)
145 149
146 str r2, [r0] 150 str r2, [r0]
147 mcr p15, 0, r0, c7, c10, 1 @ flush_pte 151 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
152#endif
148 mov pc, lr 153 mov pc, lr
149 154
150 155
@@ -194,12 +199,14 @@ __v6_setup:
194 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 199 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
195 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache 200 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
196 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 201 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
202#ifdef CONFIG_MMU
197 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs 203 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
198 mcr p15, 0, r0, c2, c0, 2 @ TTB control register 204 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
199#ifdef CONFIG_SMP 205#ifdef CONFIG_SMP
200 orr r4, r4, #TTB_RGN_WBWA|TTB_S @ mark PTWs shared, outer cacheable 206 orr r4, r4, #TTB_RGN_WBWA|TTB_S @ mark PTWs shared, outer cacheable
201#endif 207#endif
202 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 208 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
209#endif /* CONFIG_MMU */
203#ifdef CONFIG_VFP 210#ifdef CONFIG_VFP
204 mrc p15, 0, r0, c1, c0, 2 211 mrc p15, 0, r0, c1, c0, 2
205 orr r0, r0, #(0xf << 20) 212 orr r0, r0, #(0xf << 20)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 06:08:11 -0500