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-rw-r--r--arch/arm/mach-shmobile/clock-r7s72100.c8
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7778.c20
-rw-r--r--arch/arm/mach-shmobile/setup-r7s72100.c64
-rw-r--r--arch/arm/mach-shmobile/setup-r8a73a4.c66
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7740.c195
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7778.c46
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7779.c128
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7790.c116
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7791.c129
-rw-r--r--arch/arm/mach-shmobile/setup-sh7372.c160
-rw-r--r--arch/arm/mach-shmobile/setup-sh73a0.c191
11 files changed, 348 insertions, 775 deletions
diff --git a/arch/arm/mach-shmobile/clock-r7s72100.c b/arch/arm/mach-shmobile/clock-r7s72100.c
index 4aba20ca127e..850a8a371b43 100644
--- a/arch/arm/mach-shmobile/clock-r7s72100.c
+++ b/arch/arm/mach-shmobile/clock-r7s72100.c
@@ -27,6 +27,7 @@
27#define FRQCR2 0xfcfe0014 27#define FRQCR2 0xfcfe0014
28#define STBCR3 0xfcfe0420 28#define STBCR3 0xfcfe0420
29#define STBCR4 0xfcfe0424 29#define STBCR4 0xfcfe0424
30#define STBCR9 0xfcfe0438
30 31
31#define PLL_RATE 30 32#define PLL_RATE 30
32 33
@@ -144,10 +145,15 @@ struct clk div4_clks[DIV4_NR] = {
144 | CLK_ENABLE_ON_INIT), 145 | CLK_ENABLE_ON_INIT),
145}; 146};
146 147
147enum { MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40, 148enum { MSTP97, MSTP96, MSTP95, MSTP94,
149 MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
148 MSTP33, MSTP_NR }; 150 MSTP33, MSTP_NR };
149 151
150static struct clk mstp_clks[MSTP_NR] = { 152static struct clk mstp_clks[MSTP_NR] = {
153 [MSTP97] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 7, 0), /* RIIC0 */
154 [MSTP96] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 6, 0), /* RIIC1 */
155 [MSTP95] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 5, 0), /* RIIC2 */
156 [MSTP94] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 4, 0), /* RIIC3 */
151 [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */ 157 [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */
152 [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */ 158 [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */
153 [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */ 159 [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c
index 54064346dafb..dfb0fff4d24c 100644
--- a/arch/arm/mach-shmobile/clock-r8a7778.c
+++ b/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -115,6 +115,8 @@ static struct clk *main_clks[] = {
115}; 115};
116 116
117enum { 117enum {
118 MSTP531, MSTP530,
119 MSTP529, MSTP528, MSTP527, MSTP526, MSTP525, MSTP524, MSTP523,
118 MSTP331, 120 MSTP331,
119 MSTP323, MSTP322, MSTP321, 121 MSTP323, MSTP322, MSTP321,
120 MSTP311, MSTP310, 122 MSTP311, MSTP310,
@@ -129,6 +131,15 @@ enum {
129 MSTP_NR }; 131 MSTP_NR };
130 132
131static struct clk mstp_clks[MSTP_NR] = { 133static struct clk mstp_clks[MSTP_NR] = {
134 [MSTP531] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 31, 0), /* SCU0 */
135 [MSTP530] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 30, 0), /* SCU1 */
136 [MSTP529] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 29, 0), /* SCU2 */
137 [MSTP528] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 28, 0), /* SCU3 */
138 [MSTP527] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 27, 0), /* SCU4 */
139 [MSTP526] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 26, 0), /* SCU5 */
140 [MSTP525] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 25, 0), /* SCU6 */
141 [MSTP524] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 24, 0), /* SCU7 */
142 [MSTP523] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 23, 0), /* SCU8 */
132 [MSTP331] = SH_CLK_MSTP32(&s4_clk, MSTPCR3, 31, 0), /* MMC */ 143 [MSTP331] = SH_CLK_MSTP32(&s4_clk, MSTPCR3, 31, 0), /* MMC */
133 [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */ 144 [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */
134 [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */ 145 [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */
@@ -219,6 +230,15 @@ static struct clk_lookup lookups[] = {
219 CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP309]), 230 CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP309]),
220 CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP308]), 231 CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP308]),
221 CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP307]), 232 CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP307]),
233 CLKDEV_ICK_ID("scu.0", "rcar_sound", &mstp_clks[MSTP531]),
234 CLKDEV_ICK_ID("scu.1", "rcar_sound", &mstp_clks[MSTP530]),
235 CLKDEV_ICK_ID("scu.2", "rcar_sound", &mstp_clks[MSTP529]),
236 CLKDEV_ICK_ID("scu.3", "rcar_sound", &mstp_clks[MSTP528]),
237 CLKDEV_ICK_ID("scu.4", "rcar_sound", &mstp_clks[MSTP527]),
238 CLKDEV_ICK_ID("scu.5", "rcar_sound", &mstp_clks[MSTP526]),
239 CLKDEV_ICK_ID("scu.6", "rcar_sound", &mstp_clks[MSTP525]),
240 CLKDEV_ICK_ID("scu.7", "rcar_sound", &mstp_clks[MSTP524]),
241 CLKDEV_ICK_ID("scu.8", "rcar_sound", &mstp_clks[MSTP523]),
222}; 242};
223 243
224void __init r8a7778_clock_init(void) 244void __init r8a7778_clock_init(void)
diff --git a/arch/arm/mach-shmobile/setup-r7s72100.c b/arch/arm/mach-shmobile/setup-r7s72100.c
index 55f0b9c7c482..9c0b3a9d5f7a 100644
--- a/arch/arm/mach-shmobile/setup-r7s72100.c
+++ b/arch/arm/mach-shmobile/setup-r7s72100.c
@@ -28,36 +28,38 @@
28#include <mach/r7s72100.h> 28#include <mach/r7s72100.h>
29#include <asm/mach/arch.h> 29#include <asm/mach/arch.h>
30 30
31#define SCIF_DATA(index, baseaddr, irq) \ 31#define R7S72100_SCIF(index, baseaddr, irq) \
32[index] = { \ 32static const struct plat_sci_port scif##index##_platform_data = { \
33 .type = PORT_SCIF, \ 33 .type = PORT_SCIF, \
34 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, \ 34 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, \
35 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 35 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
36 .scbrr_algo_id = SCBRR_ALGO_2, \
37 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | \ 36 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | \
38 SCSCR_REIE, \ 37 SCSCR_REIE, \
39 .mapbase = baseaddr, \ 38}; \
40 .irqs = { irq + 1, irq + 2, irq + 3, irq }, \ 39 \
41} 40static struct resource scif##index##_resources[] = { \
42 41 DEFINE_RES_MEM(baseaddr, 0x100), \
43enum { SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7 }; 42 DEFINE_RES_IRQ(irq + 1), \
43 DEFINE_RES_IRQ(irq + 2), \
44 DEFINE_RES_IRQ(irq + 3), \
45 DEFINE_RES_IRQ(irq), \
46} \
44 47
45static const struct plat_sci_port scif[] __initconst = { 48R7S72100_SCIF(0, 0xe8007000, gic_iid(221));
46 SCIF_DATA(SCIF0, 0xe8007000, gic_iid(221)), /* SCIF0 */ 49R7S72100_SCIF(1, 0xe8007800, gic_iid(225));
47 SCIF_DATA(SCIF1, 0xe8007800, gic_iid(225)), /* SCIF1 */ 50R7S72100_SCIF(2, 0xe8008000, gic_iid(229));
48 SCIF_DATA(SCIF2, 0xe8008000, gic_iid(229)), /* SCIF2 */ 51R7S72100_SCIF(3, 0xe8008800, gic_iid(233));
49 SCIF_DATA(SCIF3, 0xe8008800, gic_iid(233)), /* SCIF3 */ 52R7S72100_SCIF(4, 0xe8009000, gic_iid(237));
50 SCIF_DATA(SCIF4, 0xe8009000, gic_iid(237)), /* SCIF4 */ 53R7S72100_SCIF(5, 0xe8009800, gic_iid(241));
51 SCIF_DATA(SCIF5, 0xe8009800, gic_iid(241)), /* SCIF5 */ 54R7S72100_SCIF(6, 0xe800a000, gic_iid(245));
52 SCIF_DATA(SCIF6, 0xe800a000, gic_iid(245)), /* SCIF6 */ 55R7S72100_SCIF(7, 0xe800a800, gic_iid(249));
53 SCIF_DATA(SCIF7, 0xe800a800, gic_iid(249)), /* SCIF7 */
54};
55 56
56static inline void r7s72100_register_scif(int idx) 57#define r7s72100_register_scif(index) \
57{ 58 platform_device_register_resndata(&platform_bus, "sh-sci", index, \
58 platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], 59 scif##index##_resources, \
59 sizeof(struct plat_sci_port)); 60 ARRAY_SIZE(scif##index##_resources), \
60} 61 &scif##index##_platform_data, \
62 sizeof(scif##index##_platform_data))
61 63
62 64
63static struct sh_timer_config mtu2_0_platform_data __initdata = { 65static struct sh_timer_config mtu2_0_platform_data __initdata = {
@@ -81,14 +83,14 @@ static struct resource mtu2_0_resources[] __initdata = {
81 83
82void __init r7s72100_add_dt_devices(void) 84void __init r7s72100_add_dt_devices(void)
83{ 85{
84 r7s72100_register_scif(SCIF0); 86 r7s72100_register_scif(0);
85 r7s72100_register_scif(SCIF1); 87 r7s72100_register_scif(1);
86 r7s72100_register_scif(SCIF2); 88 r7s72100_register_scif(2);
87 r7s72100_register_scif(SCIF3); 89 r7s72100_register_scif(3);
88 r7s72100_register_scif(SCIF4); 90 r7s72100_register_scif(4);
89 r7s72100_register_scif(SCIF5); 91 r7s72100_register_scif(5);
90 r7s72100_register_scif(SCIF6); 92 r7s72100_register_scif(6);
91 r7s72100_register_scif(SCIF7); 93 r7s72100_register_scif(7);
92 r7s72100_register_mtu2(0); 94 r7s72100_register_mtu2(0);
93} 95}
94 96
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
index cc94b64c2ef5..cd36f8078325 100644
--- a/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -40,41 +40,39 @@ void __init r8a73a4_pinmux_init(void)
40 ARRAY_SIZE(pfc_resources)); 40 ARRAY_SIZE(pfc_resources));
41} 41}
42 42
43#define SCIF_COMMON(scif_type, baseaddr, irq) \ 43#define R8A73A4_SCIF(scif_type, _scscr, index, baseaddr, irq) \
44static struct plat_sci_port scif##index##_platform_data = { \
44 .type = scif_type, \ 45 .type = scif_type, \
45 .mapbase = baseaddr, \
46 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 46 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
47 .scbrr_algo_id = SCBRR_ALGO_4, \ 47 .scscr = _scscr, \
48 .irqs = SCIx_IRQ_MUXED(irq) 48}; \
49 49 \
50#define SCIFA_DATA(index, baseaddr, irq) \ 50static struct resource scif##index##_resources[] = { \
51[index] = { \ 51 DEFINE_RES_MEM(baseaddr, 0x100), \
52 SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ 52 DEFINE_RES_IRQ(irq), \
53 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
54} 53}
55 54
56#define SCIFB_DATA(index, baseaddr, irq) \ 55#define R8A73A4_SCIFA(index, baseaddr, irq) \
57[index] = { \ 56 R8A73A4_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
58 SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \ 57 index, baseaddr, irq)
59 .scscr = SCSCR_RE | SCSCR_TE, \
60}
61 58
62enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 }; 59#define R8A73A4_SCIFB(index, baseaddr, irq) \
60 R8A73A4_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \
61 index, baseaddr, irq)
63 62
64static const struct plat_sci_port scif[] = { 63R8A73A4_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
65 SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ 64R8A73A4_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
66 SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ 65R8A73A4_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
67 SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ 66R8A73A4_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
68 SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ 67R8A73A4_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
69 SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ 68R8A73A4_SCIFB(5, 0xe6cf0000, gic_spi(151)); /* SCIFB3 */
70 SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */
71};
72 69
73static inline void r8a73a4_register_scif(int idx) 70#define r8a73a4_register_scif(index) \
74{ 71 platform_device_register_resndata(&platform_bus, "sh-sci", index, \
75 platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], 72 scif##index##_resources, \
76 sizeof(struct plat_sci_port)); 73 ARRAY_SIZE(scif##index##_resources), \
77} 74 &scif##index##_platform_data, \
75 sizeof(scif##index##_platform_data))
78 76
79static const struct renesas_irqc_config irqc0_data = { 77static const struct renesas_irqc_config irqc0_data = {
80 .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */ 78 .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */
@@ -192,12 +190,12 @@ static struct resource cmt10_resources[] = {
192 190
193void __init r8a73a4_add_dt_devices(void) 191void __init r8a73a4_add_dt_devices(void)
194{ 192{
195 r8a73a4_register_scif(SCIFA0); 193 r8a73a4_register_scif(0);
196 r8a73a4_register_scif(SCIFA1); 194 r8a73a4_register_scif(1);
197 r8a73a4_register_scif(SCIFB0); 195 r8a73a4_register_scif(2);
198 r8a73a4_register_scif(SCIFB1); 196 r8a73a4_register_scif(3);
199 r8a73a4_register_scif(SCIFB2); 197 r8a73a4_register_scif(4);
200 r8a73a4_register_scif(SCIFB3); 198 r8a73a4_register_scif(5);
201 r8a7790_register_cmt(10); 199 r8a7790_register_cmt(10);
202} 200}
203 201
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index b7d4b2c3bc29..8f3c68101d59 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -203,167 +203,38 @@ static struct platform_device irqpin3_device = {
203 }, 203 },
204}; 204};
205 205
206/* SCIFA0 */ 206/* SCIF */
207static struct plat_sci_port scif0_platform_data = { 207#define R8A7740_SCIF(scif_type, index, baseaddr, irq) \
208 .mapbase = 0xe6c40000, 208static struct plat_sci_port scif##index##_platform_data = { \
209 .flags = UPF_BOOT_AUTOCONF, 209 .type = scif_type, \
210 .scscr = SCSCR_RE | SCSCR_TE, 210 .flags = UPF_BOOT_AUTOCONF, \
211 .scbrr_algo_id = SCBRR_ALGO_4, 211 .scscr = SCSCR_RE | SCSCR_TE, \
212 .type = PORT_SCIFA, 212}; \
213 .irqs = SCIx_IRQ_MUXED(gic_spi(100)), 213 \
214}; 214static struct resource scif##index##_resources[] = { \
215 215 DEFINE_RES_MEM(baseaddr, 0x100), \
216static struct platform_device scif0_device = { 216 DEFINE_RES_IRQ(irq), \
217 .name = "sh-sci", 217}; \
218 .id = 0, 218 \
219 .dev = { 219static struct platform_device scif##index##_device = { \
220 .platform_data = &scif0_platform_data, 220 .name = "sh-sci", \
221 }, 221 .id = index, \
222}; 222 .resource = scif##index##_resources, \
223 223 .num_resources = ARRAY_SIZE(scif##index##_resources), \
224/* SCIFA1 */ 224 .dev = { \
225static struct plat_sci_port scif1_platform_data = { 225 .platform_data = &scif##index##_platform_data, \
226 .mapbase = 0xe6c50000, 226 }, \
227 .flags = UPF_BOOT_AUTOCONF, 227}
228 .scscr = SCSCR_RE | SCSCR_TE,
229 .scbrr_algo_id = SCBRR_ALGO_4,
230 .type = PORT_SCIFA,
231 .irqs = SCIx_IRQ_MUXED(gic_spi(101)),
232};
233
234static struct platform_device scif1_device = {
235 .name = "sh-sci",
236 .id = 1,
237 .dev = {
238 .platform_data = &scif1_platform_data,
239 },
240};
241
242/* SCIFA2 */
243static struct plat_sci_port scif2_platform_data = {
244 .mapbase = 0xe6c60000,
245 .flags = UPF_BOOT_AUTOCONF,
246 .scscr = SCSCR_RE | SCSCR_TE,
247 .scbrr_algo_id = SCBRR_ALGO_4,
248 .type = PORT_SCIFA,
249 .irqs = SCIx_IRQ_MUXED(gic_spi(102)),
250};
251
252static struct platform_device scif2_device = {
253 .name = "sh-sci",
254 .id = 2,
255 .dev = {
256 .platform_data = &scif2_platform_data,
257 },
258};
259
260/* SCIFA3 */
261static struct plat_sci_port scif3_platform_data = {
262 .mapbase = 0xe6c70000,
263 .flags = UPF_BOOT_AUTOCONF,
264 .scscr = SCSCR_RE | SCSCR_TE,
265 .scbrr_algo_id = SCBRR_ALGO_4,
266 .type = PORT_SCIFA,
267 .irqs = SCIx_IRQ_MUXED(gic_spi(103)),
268};
269
270static struct platform_device scif3_device = {
271 .name = "sh-sci",
272 .id = 3,
273 .dev = {
274 .platform_data = &scif3_platform_data,
275 },
276};
277
278/* SCIFA4 */
279static struct plat_sci_port scif4_platform_data = {
280 .mapbase = 0xe6c80000,
281 .flags = UPF_BOOT_AUTOCONF,
282 .scscr = SCSCR_RE | SCSCR_TE,
283 .scbrr_algo_id = SCBRR_ALGO_4,
284 .type = PORT_SCIFA,
285 .irqs = SCIx_IRQ_MUXED(gic_spi(104)),
286};
287
288static struct platform_device scif4_device = {
289 .name = "sh-sci",
290 .id = 4,
291 .dev = {
292 .platform_data = &scif4_platform_data,
293 },
294};
295
296/* SCIFA5 */
297static struct plat_sci_port scif5_platform_data = {
298 .mapbase = 0xe6cb0000,
299 .flags = UPF_BOOT_AUTOCONF,
300 .scscr = SCSCR_RE | SCSCR_TE,
301 .scbrr_algo_id = SCBRR_ALGO_4,
302 .type = PORT_SCIFA,
303 .irqs = SCIx_IRQ_MUXED(gic_spi(105)),
304};
305
306static struct platform_device scif5_device = {
307 .name = "sh-sci",
308 .id = 5,
309 .dev = {
310 .platform_data = &scif5_platform_data,
311 },
312};
313
314/* SCIFA6 */
315static struct plat_sci_port scif6_platform_data = {
316 .mapbase = 0xe6cc0000,
317 .flags = UPF_BOOT_AUTOCONF,
318 .scscr = SCSCR_RE | SCSCR_TE,
319 .scbrr_algo_id = SCBRR_ALGO_4,
320 .type = PORT_SCIFA,
321 .irqs = SCIx_IRQ_MUXED(gic_spi(106)),
322};
323
324static struct platform_device scif6_device = {
325 .name = "sh-sci",
326 .id = 6,
327 .dev = {
328 .platform_data = &scif6_platform_data,
329 },
330};
331
332/* SCIFA7 */
333static struct plat_sci_port scif7_platform_data = {
334 .mapbase = 0xe6cd0000,
335 .flags = UPF_BOOT_AUTOCONF,
336 .scscr = SCSCR_RE | SCSCR_TE,
337 .scbrr_algo_id = SCBRR_ALGO_4,
338 .type = PORT_SCIFA,
339 .irqs = SCIx_IRQ_MUXED(gic_spi(107)),
340};
341
342static struct platform_device scif7_device = {
343 .name = "sh-sci",
344 .id = 7,
345 .dev = {
346 .platform_data = &scif7_platform_data,
347 },
348};
349
350/* SCIFB */
351static struct plat_sci_port scifb_platform_data = {
352 .mapbase = 0xe6c30000,
353 .flags = UPF_BOOT_AUTOCONF,
354 .scscr = SCSCR_RE | SCSCR_TE,
355 .scbrr_algo_id = SCBRR_ALGO_4,
356 .type = PORT_SCIFB,
357 .irqs = SCIx_IRQ_MUXED(gic_spi(108)),
358};
359 228
360static struct platform_device scifb_device = { 229R8A7740_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(100));
361 .name = "sh-sci", 230R8A7740_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(101));
362 .id = 8, 231R8A7740_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(102));
363 .dev = { 232R8A7740_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(103));
364 .platform_data = &scifb_platform_data, 233R8A7740_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(104));
365 }, 234R8A7740_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(105));
366}; 235R8A7740_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(106));
236R8A7740_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(107));
237R8A7740_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(108));
367 238
368/* CMT */ 239/* CMT */
369static struct sh_timer_config cmt10_platform_data = { 240static struct sh_timer_config cmt10_platform_data = {
@@ -528,7 +399,7 @@ static struct platform_device *r8a7740_devices_dt[] __initdata = {
528 &scif5_device, 399 &scif5_device,
529 &scif6_device, 400 &scif6_device,
530 &scif7_device, 401 &scif7_device,
531 &scifb_device, 402 &scif8_device,
532 &cmt10_device, 403 &cmt10_device,
533}; 404};
534 405
@@ -981,7 +852,7 @@ void __init r8a7740_add_standard_devices(void)
981 rmobile_add_device_to_domain("A3SP", &scif5_device); 852 rmobile_add_device_to_domain("A3SP", &scif5_device);
982 rmobile_add_device_to_domain("A3SP", &scif6_device); 853 rmobile_add_device_to_domain("A3SP", &scif6_device);
983 rmobile_add_device_to_domain("A3SP", &scif7_device); 854 rmobile_add_device_to_domain("A3SP", &scif7_device);
984 rmobile_add_device_to_domain("A3SP", &scifb_device); 855 rmobile_add_device_to_domain("A3SP", &scif8_device);
985 rmobile_add_device_to_domain("A3SP", &i2c1_device); 856 rmobile_add_device_to_domain("A3SP", &i2c1_device);
986} 857}
987 858
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 7ea6308e5da8..6d694526e4ca 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -44,24 +44,31 @@
44#include <asm/hardware/cache-l2x0.h> 44#include <asm/hardware/cache-l2x0.h>
45 45
46/* SCIF */ 46/* SCIF */
47#define SCIF_INFO(baseaddr, irq) \ 47#define R8A7778_SCIF(index, baseaddr, irq) \
48{ \ 48static struct plat_sci_port scif##index##_platform_data = { \
49 .mapbase = baseaddr, \
50 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 49 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
51 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ 50 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
52 .scbrr_algo_id = SCBRR_ALGO_2, \
53 .type = PORT_SCIF, \ 51 .type = PORT_SCIF, \
54 .irqs = SCIx_IRQ_MUXED(irq), \ 52}; \
53 \
54static struct resource scif##index##_resources[] = { \
55 DEFINE_RES_MEM(baseaddr, 0x100), \
56 DEFINE_RES_IRQ(irq), \
55} 57}
56 58
57static struct plat_sci_port scif_platform_data[] __initdata = { 59R8A7778_SCIF(0, 0xffe40000, gic_iid(0x66));
58 SCIF_INFO(0xffe40000, gic_iid(0x66)), 60R8A7778_SCIF(1, 0xffe41000, gic_iid(0x67));
59 SCIF_INFO(0xffe41000, gic_iid(0x67)), 61R8A7778_SCIF(2, 0xffe42000, gic_iid(0x68));
60 SCIF_INFO(0xffe42000, gic_iid(0x68)), 62R8A7778_SCIF(3, 0xffe43000, gic_iid(0x69));
61 SCIF_INFO(0xffe43000, gic_iid(0x69)), 63R8A7778_SCIF(4, 0xffe44000, gic_iid(0x6a));
62 SCIF_INFO(0xffe44000, gic_iid(0x6a)), 64R8A7778_SCIF(5, 0xffe45000, gic_iid(0x6b));
63 SCIF_INFO(0xffe45000, gic_iid(0x6b)), 65
64}; 66#define r8a7778_register_scif(index) \
67 platform_device_register_resndata(&platform_bus, "sh-sci", index, \
68 scif##index##_resources, \
69 ARRAY_SIZE(scif##index##_resources), \
70 &scif##index##_platform_data, \
71 sizeof(scif##index##_platform_data))
65 72
66/* TMU */ 73/* TMU */
67static struct resource sh_tmu0_resources[] __initdata = { 74static struct resource sh_tmu0_resources[] __initdata = {
@@ -287,8 +294,6 @@ static void __init r8a7778_register_hspi(int id)
287 294
288void __init r8a7778_add_dt_devices(void) 295void __init r8a7778_add_dt_devices(void)
289{ 296{
290 int i;
291
292#ifdef CONFIG_CACHE_L2X0 297#ifdef CONFIG_CACHE_L2X0
293 void __iomem *base = ioremap_nocache(0xf0100000, 0x1000); 298 void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
294 if (base) { 299 if (base) {
@@ -300,11 +305,12 @@ void __init r8a7778_add_dt_devices(void)
300 } 305 }
301#endif 306#endif
302 307
303 for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++) 308 r8a7778_register_scif(0);
304 platform_device_register_data(&platform_bus, "sh-sci", i, 309 r8a7778_register_scif(1);
305 &scif_platform_data[i], 310 r8a7778_register_scif(2);
306 sizeof(struct plat_sci_port)); 311 r8a7778_register_scif(3);
307 312 r8a7778_register_scif(4);
313 r8a7778_register_scif(5);
308 r8a7778_register_tmu(0); 314 r8a7778_register_tmu(0);
309 r8a7778_register_tmu(1); 315 r8a7778_register_tmu(1);
310} 316}
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 13049e9d691c..339292e85838 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -188,107 +188,35 @@ void __init r8a7779_pinmux_init(void)
188 ARRAY_SIZE(r8a7779_pinctrl_devices)); 188 ARRAY_SIZE(r8a7779_pinctrl_devices));
189} 189}
190 190
191static struct plat_sci_port scif0_platform_data = { 191/* SCIF */
192 .mapbase = 0xffe40000, 192#define R8A7779_SCIF(index, baseaddr, irq) \
193 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, 193static struct plat_sci_port scif##index##_platform_data = { \
194 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 194 .type = PORT_SCIF, \
195 .scbrr_algo_id = SCBRR_ALGO_2, 195 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
196 .type = PORT_SCIF, 196 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
197 .irqs = SCIx_IRQ_MUXED(gic_iid(0x78)), 197}; \
198}; 198 \
199 199static struct resource scif##index##_resources[] = { \
200static struct platform_device scif0_device = { 200 DEFINE_RES_MEM(baseaddr, 0x100), \
201 .name = "sh-sci", 201 DEFINE_RES_IRQ(irq), \
202 .id = 0, 202}; \
203 .dev = { 203 \
204 .platform_data = &scif0_platform_data, 204static struct platform_device scif##index##_device = { \
205 }, 205 .name = "sh-sci", \
206}; 206 .id = index, \
207 207 .resource = scif##index##_resources, \
208static struct plat_sci_port scif1_platform_data = { 208 .num_resources = ARRAY_SIZE(scif##index##_resources), \
209 .mapbase = 0xffe41000, 209 .dev = { \
210 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, 210 .platform_data = &scif##index##_platform_data, \
211 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 211 }, \
212 .scbrr_algo_id = SCBRR_ALGO_2, 212}
213 .type = PORT_SCIF,
214 .irqs = SCIx_IRQ_MUXED(gic_iid(0x79)),
215};
216
217static struct platform_device scif1_device = {
218 .name = "sh-sci",
219 .id = 1,
220 .dev = {
221 .platform_data = &scif1_platform_data,
222 },
223};
224
225static struct plat_sci_port scif2_platform_data = {
226 .mapbase = 0xffe42000,
227 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
228 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
229 .scbrr_algo_id = SCBRR_ALGO_2,
230 .type = PORT_SCIF,
231 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7a)),
232};
233
234static struct platform_device scif2_device = {
235 .name = "sh-sci",
236 .id = 2,
237 .dev = {
238 .platform_data = &scif2_platform_data,
239 },
240};
241
242static struct plat_sci_port scif3_platform_data = {
243 .mapbase = 0xffe43000,
244 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
245 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
246 .scbrr_algo_id = SCBRR_ALGO_2,
247 .type = PORT_SCIF,
248 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7b)),
249};
250
251static struct platform_device scif3_device = {
252 .name = "sh-sci",
253 .id = 3,
254 .dev = {
255 .platform_data = &scif3_platform_data,
256 },
257};
258
259static struct plat_sci_port scif4_platform_data = {
260 .mapbase = 0xffe44000,
261 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
262 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
263 .scbrr_algo_id = SCBRR_ALGO_2,
264 .type = PORT_SCIF,
265 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7c)),
266};
267
268static struct platform_device scif4_device = {
269 .name = "sh-sci",
270 .id = 4,
271 .dev = {
272 .platform_data = &scif4_platform_data,
273 },
274};
275
276static struct plat_sci_port scif5_platform_data = {
277 .mapbase = 0xffe45000,
278 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
279 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
280 .scbrr_algo_id = SCBRR_ALGO_2,
281 .type = PORT_SCIF,
282 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7d)),
283};
284 213
285static struct platform_device scif5_device = { 214R8A7779_SCIF(0, 0xffe40000, gic_iid(0x78));
286 .name = "sh-sci", 215R8A7779_SCIF(1, 0xffe41000, gic_iid(0x79));
287 .id = 5, 216R8A7779_SCIF(2, 0xffe42000, gic_iid(0x7a));
288 .dev = { 217R8A7779_SCIF(3, 0xffe43000, gic_iid(0x7b));
289 .platform_data = &scif5_platform_data, 218R8A7779_SCIF(4, 0xffe44000, gic_iid(0x7c));
290 }, 219R8A7779_SCIF(5, 0xffe45000, gic_iid(0x7d));
291};
292 220
293/* TMU */ 221/* TMU */
294static struct sh_timer_config tmu00_platform_data = { 222static struct sh_timer_config tmu00_platform_data = {
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index 1a11e26a9431..66476d21544d 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -100,61 +100,51 @@ void __init r8a7790_pinmux_init(void)
100 r8a7790_register_i2c(3); 100 r8a7790_register_i2c(3);
101} 101}
102 102
103#define SCIF_COMMON(scif_type, baseaddr, irq) \ 103#define __R8A7790_SCIF(scif_type, _scscr, index, baseaddr, irq) \
104 .type = scif_type, \ 104static struct plat_sci_port scif##index##_platform_data = { \
105 .mapbase = baseaddr, \ 105 .type = scif_type, \
106 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 106 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
107 .irqs = SCIx_IRQ_MUXED(irq) 107 .scscr = _scscr, \
108 108}; \
109#define SCIFA_DATA(index, baseaddr, irq) \ 109 \
110[index] = { \ 110static struct resource scif##index##_resources[] = { \
111 SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ 111 DEFINE_RES_MEM(baseaddr, 0x100), \
112 .scbrr_algo_id = SCBRR_ALGO_4, \ 112 DEFINE_RES_IRQ(irq), \
113 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
114}
115
116#define SCIFB_DATA(index, baseaddr, irq) \
117[index] = { \
118 SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
119 .scbrr_algo_id = SCBRR_ALGO_4, \
120 .scscr = SCSCR_RE | SCSCR_TE, \
121}
122
123#define SCIF_DATA(index, baseaddr, irq) \
124[index] = { \
125 SCIF_COMMON(PORT_SCIF, baseaddr, irq), \
126 .scbrr_algo_id = SCBRR_ALGO_2, \
127 .scscr = SCSCR_RE | SCSCR_TE, \
128}
129
130#define HSCIF_DATA(index, baseaddr, irq) \
131[index] = { \
132 SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \
133 .scbrr_algo_id = SCBRR_ALGO_6, \
134 .scscr = SCSCR_RE | SCSCR_TE, \
135} 113}
136 114
137enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1, 115#define R8A7790_SCIF(index, baseaddr, irq) \
138 HSCIF0, HSCIF1 }; 116 __R8A7790_SCIF(PORT_SCIF, SCSCR_RE | SCSCR_TE, \
139 117 index, baseaddr, irq)
140static const struct plat_sci_port scif[] __initconst = { 118
141 SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ 119#define R8A7790_SCIFA(index, baseaddr, irq) \
142 SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ 120 __R8A7790_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
143 SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ 121 index, baseaddr, irq)
144 SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ 122
145 SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ 123#define R8A7790_SCIFB(index, baseaddr, irq) \
146 SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */ 124 __R8A7790_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \
147 SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */ 125 index, baseaddr, irq)
148 SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */ 126
149 HSCIF_DATA(HSCIF0, 0xe62c0000, gic_spi(154)), /* HSCIF0 */ 127#define R8A7790_HSCIF(index, baseaddr, irq) \
150 HSCIF_DATA(HSCIF1, 0xe62c8000, gic_spi(155)), /* HSCIF1 */ 128 __R8A7790_SCIF(PORT_HSCIF, SCSCR_RE | SCSCR_TE, \
151}; 129 index, baseaddr, irq)
152 130
153static inline void r8a7790_register_scif(int idx) 131R8A7790_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
154{ 132R8A7790_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
155 platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], 133R8A7790_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
156 sizeof(struct plat_sci_port)); 134R8A7790_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
157} 135R8A7790_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
136R8A7790_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */
137R8A7790_SCIF(6, 0xe6e60000, gic_spi(152)); /* SCIF0 */
138R8A7790_SCIF(7, 0xe6e68000, gic_spi(153)); /* SCIF1 */
139R8A7790_HSCIF(8, 0xe62c0000, gic_spi(154)); /* HSCIF0 */
140R8A7790_HSCIF(9, 0xe62c8000, gic_spi(155)); /* HSCIF1 */
141
142#define r8a7790_register_scif(index) \
143 platform_device_register_resndata(&platform_bus, "sh-sci", index, \
144 scif##index##_resources, \
145 ARRAY_SIZE(scif##index##_resources), \
146 &scif##index##_platform_data, \
147 sizeof(scif##index##_platform_data))
158 148
159static const struct renesas_irqc_config irqc0_data __initconst = { 149static const struct renesas_irqc_config irqc0_data __initconst = {
160 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ 150 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
@@ -207,16 +197,16 @@ static const struct resource cmt00_resources[] __initconst = {
207 197
208void __init r8a7790_add_dt_devices(void) 198void __init r8a7790_add_dt_devices(void)
209{ 199{
210 r8a7790_register_scif(SCIFA0); 200 r8a7790_register_scif(0);
211 r8a7790_register_scif(SCIFA1); 201 r8a7790_register_scif(1);
212 r8a7790_register_scif(SCIFB0); 202 r8a7790_register_scif(2);
213 r8a7790_register_scif(SCIFB1); 203 r8a7790_register_scif(3);
214 r8a7790_register_scif(SCIFB2); 204 r8a7790_register_scif(4);
215 r8a7790_register_scif(SCIFA2); 205 r8a7790_register_scif(5);
216 r8a7790_register_scif(SCIF0); 206 r8a7790_register_scif(6);
217 r8a7790_register_scif(SCIF1); 207 r8a7790_register_scif(7);
218 r8a7790_register_scif(HSCIF0); 208 r8a7790_register_scif(8);
219 r8a7790_register_scif(HSCIF1); 209 r8a7790_register_scif(9);
220 r8a7790_register_cmt(00); 210 r8a7790_register_cmt(00);
221} 211}
222 212
diff --git a/arch/arm/mach-shmobile/setup-r8a7791.c b/arch/arm/mach-shmobile/setup-r8a7791.c
index cddca99b434f..e28404e43860 100644
--- a/arch/arm/mach-shmobile/setup-r8a7791.c
+++ b/arch/arm/mach-shmobile/setup-r8a7791.c
@@ -84,66 +84,49 @@ void __init r8a7791_pinmux_init(void)
84 r8a7791_register_gpio(7); 84 r8a7791_register_gpio(7);
85} 85}
86 86
87#define SCIF_COMMON(scif_type, baseaddr, irq) \ 87#define __R8A7791_SCIF(scif_type, index, baseaddr, irq) \
88 .type = scif_type, \ 88static struct plat_sci_port scif##index##_platform_data = { \
89 .mapbase = baseaddr, \ 89 .type = scif_type, \
90 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 90 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
91 .irqs = SCIx_IRQ_MUXED(irq) 91 .scscr = SCSCR_RE | SCSCR_TE, \
92 92}; \
93#define SCIFA_DATA(index, baseaddr, irq) \ 93 \
94[index] = { \ 94static struct resource scif##index##_resources[] = { \
95 SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ 95 DEFINE_RES_MEM(baseaddr, 0x100), \
96 .scbrr_algo_id = SCBRR_ALGO_4, \ 96 DEFINE_RES_IRQ(irq), \
97 .scscr = SCSCR_RE | SCSCR_TE, \
98}
99
100#define SCIFB_DATA(index, baseaddr, irq) \
101[index] = { \
102 SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
103 .scbrr_algo_id = SCBRR_ALGO_4, \
104 .scscr = SCSCR_RE | SCSCR_TE, \
105}
106
107#define SCIF_DATA(index, baseaddr, irq) \
108[index] = { \
109 SCIF_COMMON(PORT_SCIF, baseaddr, irq), \
110 .scbrr_algo_id = SCBRR_ALGO_2, \
111 .scscr = SCSCR_RE | SCSCR_TE, \
112}
113
114#define HSCIF_DATA(index, baseaddr, irq) \
115[index] = { \
116 SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \
117 .scbrr_algo_id = SCBRR_ALGO_6, \
118 .scscr = SCSCR_RE | SCSCR_TE, \
119} 97}
120 98
121enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1, 99#define R8A7791_SCIF(index, baseaddr, irq) \
122 SCIF2, SCIF3, SCIF4, SCIF5, SCIFA3, SCIFA4, SCIFA5 }; 100 __R8A7791_SCIF(PORT_SCIF, index, baseaddr, irq)
123 101
124static const struct plat_sci_port scif[] __initconst = { 102#define R8A7791_SCIFA(index, baseaddr, irq) \
125 SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ 103 __R8A7791_SCIF(PORT_SCIFA, index, baseaddr, irq)
126 SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ 104
127 SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ 105#define R8A7791_SCIFB(index, baseaddr, irq) \
128 SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ 106 __R8A7791_SCIF(PORT_SCIFB, index, baseaddr, irq)
129 SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ 107
130 SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */ 108R8A7791_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
131 SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */ 109R8A7791_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
132 SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */ 110R8A7791_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
133 SCIF_DATA(SCIF2, 0xe6e58000, gic_spi(22)), /* SCIF2 */ 111R8A7791_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
134 SCIF_DATA(SCIF3, 0xe6ea8000, gic_spi(23)), /* SCIF3 */ 112R8A7791_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
135 SCIF_DATA(SCIF4, 0xe6ee0000, gic_spi(24)), /* SCIF4 */ 113R8A7791_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */
136 SCIF_DATA(SCIF5, 0xe6ee8000, gic_spi(25)), /* SCIF5 */ 114R8A7791_SCIF(6, 0xe6e60000, gic_spi(152)); /* SCIF0 */
137 SCIFA_DATA(SCIFA3, 0xe6c70000, gic_spi(29)), /* SCIFA3 */ 115R8A7791_SCIF(7, 0xe6e68000, gic_spi(153)); /* SCIF1 */
138 SCIFA_DATA(SCIFA4, 0xe6c78000, gic_spi(30)), /* SCIFA4 */ 116R8A7791_SCIF(8, 0xe6e58000, gic_spi(22)); /* SCIF2 */
139 SCIFA_DATA(SCIFA5, 0xe6c80000, gic_spi(31)), /* SCIFA5 */ 117R8A7791_SCIF(9, 0xe6ea8000, gic_spi(23)); /* SCIF3 */
140}; 118R8A7791_SCIF(10, 0xe6ee0000, gic_spi(24)); /* SCIF4 */
141 119R8A7791_SCIF(11, 0xe6ee8000, gic_spi(25)); /* SCIF5 */
142static inline void r8a7791_register_scif(int idx) 120R8A7791_SCIFA(12, 0xe6c70000, gic_spi(29)); /* SCIFA3 */
143{ 121R8A7791_SCIFA(13, 0xe6c78000, gic_spi(30)); /* SCIFA4 */
144 platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], 122R8A7791_SCIFA(14, 0xe6c80000, gic_spi(31)); /* SCIFA5 */
145 sizeof(struct plat_sci_port)); 123
146} 124#define r8a7791_register_scif(index) \
125 platform_device_register_resndata(&platform_bus, "sh-sci", index, \
126 scif##index##_resources, \
127 ARRAY_SIZE(scif##index##_resources), \
128 &scif##index##_platform_data, \
129 sizeof(scif##index##_platform_data))
147 130
148static const struct sh_timer_config cmt00_platform_data __initconst = { 131static const struct sh_timer_config cmt00_platform_data __initconst = {
149 .name = "CMT00", 132 .name = "CMT00",
@@ -202,21 +185,21 @@ static const struct resource thermal_resources[] __initconst = {
202 185
203void __init r8a7791_add_dt_devices(void) 186void __init r8a7791_add_dt_devices(void)
204{ 187{
205 r8a7791_register_scif(SCIFA0); 188 r8a7791_register_scif(0);
206 r8a7791_register_scif(SCIFA1); 189 r8a7791_register_scif(1);
207 r8a7791_register_scif(SCIFB0); 190 r8a7791_register_scif(2);
208 r8a7791_register_scif(SCIFB1); 191 r8a7791_register_scif(3);
209 r8a7791_register_scif(SCIFB2); 192 r8a7791_register_scif(4);
210 r8a7791_register_scif(SCIFA2); 193 r8a7791_register_scif(5);
211 r8a7791_register_scif(SCIF0); 194 r8a7791_register_scif(6);
212 r8a7791_register_scif(SCIF1); 195 r8a7791_register_scif(7);
213 r8a7791_register_scif(SCIF2); 196 r8a7791_register_scif(8);
214 r8a7791_register_scif(SCIF3); 197 r8a7791_register_scif(9);
215 r8a7791_register_scif(SCIF4); 198 r8a7791_register_scif(10);
216 r8a7791_register_scif(SCIF5); 199 r8a7791_register_scif(11);
217 r8a7791_register_scif(SCIFA3); 200 r8a7791_register_scif(12);
218 r8a7791_register_scif(SCIFA4); 201 r8a7791_register_scif(13);
219 r8a7791_register_scif(SCIFA5); 202 r8a7791_register_scif(14);
220 r8a7791_register_cmt(00); 203 r8a7791_register_cmt(00);
221} 204}
222 205
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 311878391e18..27301278c208 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -86,138 +86,36 @@ void __init sh7372_pinmux_init(void)
86 platform_device_register(&sh7372_pfc_device); 86 platform_device_register(&sh7372_pfc_device);
87} 87}
88 88
89/* SCIFA0 */ 89/* SCIF */
90static struct plat_sci_port scif0_platform_data = { 90#define SH7372_SCIF(scif_type, index, baseaddr, irq) \
91 .mapbase = 0xe6c40000, 91static struct plat_sci_port scif##index##_platform_data = { \
92 .flags = UPF_BOOT_AUTOCONF, 92 .type = scif_type, \
93 .scscr = SCSCR_RE | SCSCR_TE, 93 .flags = UPF_BOOT_AUTOCONF, \
94 .scbrr_algo_id = SCBRR_ALGO_4, 94 .scscr = SCSCR_RE | SCSCR_TE, \
95 .type = PORT_SCIFA, 95}; \
96 .irqs = { evt2irq(0x0c00), evt2irq(0x0c00), 96 \
97 evt2irq(0x0c00), evt2irq(0x0c00) }, 97static struct resource scif##index##_resources[] = { \
98}; 98 DEFINE_RES_MEM(baseaddr, 0x100), \
99 99 DEFINE_RES_IRQ(irq), \
100static struct platform_device scif0_device = { 100}; \
101 .name = "sh-sci", 101 \
102 .id = 0, 102static struct platform_device scif##index##_device = { \
103 .dev = { 103 .name = "sh-sci", \
104 .platform_data = &scif0_platform_data, 104 .id = index, \
105 }, 105 .resource = scif##index##_resources, \
106}; 106 .num_resources = ARRAY_SIZE(scif##index##_resources), \
107 107 .dev = { \
108/* SCIFA1 */ 108 .platform_data = &scif##index##_platform_data, \
109static struct plat_sci_port scif1_platform_data = { 109 }, \
110 .mapbase = 0xe6c50000, 110}
111 .flags = UPF_BOOT_AUTOCONF,
112 .scscr = SCSCR_RE | SCSCR_TE,
113 .scbrr_algo_id = SCBRR_ALGO_4,
114 .type = PORT_SCIFA,
115 .irqs = { evt2irq(0x0c20), evt2irq(0x0c20),
116 evt2irq(0x0c20), evt2irq(0x0c20) },
117};
118
119static struct platform_device scif1_device = {
120 .name = "sh-sci",
121 .id = 1,
122 .dev = {
123 .platform_data = &scif1_platform_data,
124 },
125};
126
127/* SCIFA2 */
128static struct plat_sci_port scif2_platform_data = {
129 .mapbase = 0xe6c60000,
130 .flags = UPF_BOOT_AUTOCONF,
131 .scscr = SCSCR_RE | SCSCR_TE,
132 .scbrr_algo_id = SCBRR_ALGO_4,
133 .type = PORT_SCIFA,
134 .irqs = { evt2irq(0x0c40), evt2irq(0x0c40),
135 evt2irq(0x0c40), evt2irq(0x0c40) },
136};
137
138static struct platform_device scif2_device = {
139 .name = "sh-sci",
140 .id = 2,
141 .dev = {
142 .platform_data = &scif2_platform_data,
143 },
144};
145
146/* SCIFA3 */
147static struct plat_sci_port scif3_platform_data = {
148 .mapbase = 0xe6c70000,
149 .flags = UPF_BOOT_AUTOCONF,
150 .scscr = SCSCR_RE | SCSCR_TE,
151 .scbrr_algo_id = SCBRR_ALGO_4,
152 .type = PORT_SCIFA,
153 .irqs = { evt2irq(0x0c60), evt2irq(0x0c60),
154 evt2irq(0x0c60), evt2irq(0x0c60) },
155};
156
157static struct platform_device scif3_device = {
158 .name = "sh-sci",
159 .id = 3,
160 .dev = {
161 .platform_data = &scif3_platform_data,
162 },
163};
164
165/* SCIFA4 */
166static struct plat_sci_port scif4_platform_data = {
167 .mapbase = 0xe6c80000,
168 .flags = UPF_BOOT_AUTOCONF,
169 .scscr = SCSCR_RE | SCSCR_TE,
170 .scbrr_algo_id = SCBRR_ALGO_4,
171 .type = PORT_SCIFA,
172 .irqs = { evt2irq(0x0d20), evt2irq(0x0d20),
173 evt2irq(0x0d20), evt2irq(0x0d20) },
174};
175
176static struct platform_device scif4_device = {
177 .name = "sh-sci",
178 .id = 4,
179 .dev = {
180 .platform_data = &scif4_platform_data,
181 },
182};
183
184/* SCIFA5 */
185static struct plat_sci_port scif5_platform_data = {
186 .mapbase = 0xe6cb0000,
187 .flags = UPF_BOOT_AUTOCONF,
188 .scscr = SCSCR_RE | SCSCR_TE,
189 .scbrr_algo_id = SCBRR_ALGO_4,
190 .type = PORT_SCIFA,
191 .irqs = { evt2irq(0x0d40), evt2irq(0x0d40),
192 evt2irq(0x0d40), evt2irq(0x0d40) },
193};
194
195static struct platform_device scif5_device = {
196 .name = "sh-sci",
197 .id = 5,
198 .dev = {
199 .platform_data = &scif5_platform_data,
200 },
201};
202
203/* SCIFB */
204static struct plat_sci_port scif6_platform_data = {
205 .mapbase = 0xe6c30000,
206 .flags = UPF_BOOT_AUTOCONF,
207 .scscr = SCSCR_RE | SCSCR_TE,
208 .scbrr_algo_id = SCBRR_ALGO_4,
209 .type = PORT_SCIFB,
210 .irqs = { evt2irq(0x0d60), evt2irq(0x0d60),
211 evt2irq(0x0d60), evt2irq(0x0d60) },
212};
213 111
214static struct platform_device scif6_device = { 112SH7372_SCIF(PORT_SCIFA, 0, 0xe6c40000, evt2irq(0x0c00));
215 .name = "sh-sci", 113SH7372_SCIF(PORT_SCIFA, 1, 0xe6c50000, evt2irq(0x0c20));
216 .id = 6, 114SH7372_SCIF(PORT_SCIFA, 2, 0xe6c60000, evt2irq(0x0c40));
217 .dev = { 115SH7372_SCIF(PORT_SCIFA, 3, 0xe6c70000, evt2irq(0x0c60));
218 .platform_data = &scif6_platform_data, 116SH7372_SCIF(PORT_SCIFA, 4, 0xe6c80000, evt2irq(0x0d20));
219 }, 117SH7372_SCIF(PORT_SCIFA, 5, 0xe6cb0000, evt2irq(0x0d40));
220}; 118SH7372_SCIF(PORT_SCIFB, 6, 0xe6c30000, evt2irq(0x0d60));
221 119
222/* CMT */ 120/* CMT */
223static struct sh_timer_config cmt2_platform_data = { 121static struct sh_timer_config cmt2_platform_data = {
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 22de17417fd7..00b348ec48b8 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -71,167 +71,38 @@ void __init sh73a0_pinmux_init(void)
71 ARRAY_SIZE(pfc_resources)); 71 ARRAY_SIZE(pfc_resources));
72} 72}
73 73
74static struct plat_sci_port scif0_platform_data = { 74/* SCIF */
75 .mapbase = 0xe6c40000, 75#define SH73A0_SCIF(scif_type, index, baseaddr, irq) \
76 .flags = UPF_BOOT_AUTOCONF, 76static struct plat_sci_port scif##index##_platform_data = { \
77 .scscr = SCSCR_RE | SCSCR_TE, 77 .type = scif_type, \
78 .scbrr_algo_id = SCBRR_ALGO_4, 78 .flags = UPF_BOOT_AUTOCONF, \
79 .type = PORT_SCIFA, 79 .scscr = SCSCR_RE | SCSCR_TE, \
80 .irqs = { gic_spi(72), gic_spi(72), 80}; \
81 gic_spi(72), gic_spi(72) }, 81 \
82}; 82static struct resource scif##index##_resources[] = { \
83 83 DEFINE_RES_MEM(baseaddr, 0x100), \
84static struct platform_device scif0_device = { 84 DEFINE_RES_IRQ(irq), \
85 .name = "sh-sci", 85}; \
86 .id = 0, 86 \
87 .dev = { 87static struct platform_device scif##index##_device = { \
88 .platform_data = &scif0_platform_data, 88 .name = "sh-sci", \
89 }, 89 .id = index, \
90}; 90 .resource = scif##index##_resources, \
91 91 .num_resources = ARRAY_SIZE(scif##index##_resources), \
92static struct plat_sci_port scif1_platform_data = { 92 .dev = { \
93 .mapbase = 0xe6c50000, 93 .platform_data = &scif##index##_platform_data, \
94 .flags = UPF_BOOT_AUTOCONF, 94 }, \
95 .scscr = SCSCR_RE | SCSCR_TE, 95}
96 .scbrr_algo_id = SCBRR_ALGO_4,
97 .type = PORT_SCIFA,
98 .irqs = { gic_spi(73), gic_spi(73),
99 gic_spi(73), gic_spi(73) },
100};
101
102static struct platform_device scif1_device = {
103 .name = "sh-sci",
104 .id = 1,
105 .dev = {
106 .platform_data = &scif1_platform_data,
107 },
108};
109
110static struct plat_sci_port scif2_platform_data = {
111 .mapbase = 0xe6c60000,
112 .flags = UPF_BOOT_AUTOCONF,
113 .scscr = SCSCR_RE | SCSCR_TE,
114 .scbrr_algo_id = SCBRR_ALGO_4,
115 .type = PORT_SCIFA,
116 .irqs = { gic_spi(74), gic_spi(74),
117 gic_spi(74), gic_spi(74) },
118};
119
120static struct platform_device scif2_device = {
121 .name = "sh-sci",
122 .id = 2,
123 .dev = {
124 .platform_data = &scif2_platform_data,
125 },
126};
127
128static struct plat_sci_port scif3_platform_data = {
129 .mapbase = 0xe6c70000,
130 .flags = UPF_BOOT_AUTOCONF,
131 .scscr = SCSCR_RE | SCSCR_TE,
132 .scbrr_algo_id = SCBRR_ALGO_4,
133 .type = PORT_SCIFA,
134 .irqs = { gic_spi(75), gic_spi(75),
135 gic_spi(75), gic_spi(75) },
136};
137
138static struct platform_device scif3_device = {
139 .name = "sh-sci",
140 .id = 3,
141 .dev = {
142 .platform_data = &scif3_platform_data,
143 },
144};
145
146static struct plat_sci_port scif4_platform_data = {
147 .mapbase = 0xe6c80000,
148 .flags = UPF_BOOT_AUTOCONF,
149 .scscr = SCSCR_RE | SCSCR_TE,
150 .scbrr_algo_id = SCBRR_ALGO_4,
151 .type = PORT_SCIFA,
152 .irqs = { gic_spi(78), gic_spi(78),
153 gic_spi(78), gic_spi(78) },
154};
155
156static struct platform_device scif4_device = {
157 .name = "sh-sci",
158 .id = 4,
159 .dev = {
160 .platform_data = &scif4_platform_data,
161 },
162};
163
164static struct plat_sci_port scif5_platform_data = {
165 .mapbase = 0xe6cb0000,
166 .flags = UPF_BOOT_AUTOCONF,
167 .scscr = SCSCR_RE | SCSCR_TE,
168 .scbrr_algo_id = SCBRR_ALGO_4,
169 .type = PORT_SCIFA,
170 .irqs = { gic_spi(79), gic_spi(79),
171 gic_spi(79), gic_spi(79) },
172};
173
174static struct platform_device scif5_device = {
175 .name = "sh-sci",
176 .id = 5,
177 .dev = {
178 .platform_data = &scif5_platform_data,
179 },
180};
181
182static struct plat_sci_port scif6_platform_data = {
183 .mapbase = 0xe6cc0000,
184 .flags = UPF_BOOT_AUTOCONF,
185 .scscr = SCSCR_RE | SCSCR_TE,
186 .scbrr_algo_id = SCBRR_ALGO_4,
187 .type = PORT_SCIFA,
188 .irqs = { gic_spi(156), gic_spi(156),
189 gic_spi(156), gic_spi(156) },
190};
191
192static struct platform_device scif6_device = {
193 .name = "sh-sci",
194 .id = 6,
195 .dev = {
196 .platform_data = &scif6_platform_data,
197 },
198};
199
200static struct plat_sci_port scif7_platform_data = {
201 .mapbase = 0xe6cd0000,
202 .flags = UPF_BOOT_AUTOCONF,
203 .scscr = SCSCR_RE | SCSCR_TE,
204 .scbrr_algo_id = SCBRR_ALGO_4,
205 .type = PORT_SCIFA,
206 .irqs = { gic_spi(143), gic_spi(143),
207 gic_spi(143), gic_spi(143) },
208};
209
210static struct platform_device scif7_device = {
211 .name = "sh-sci",
212 .id = 7,
213 .dev = {
214 .platform_data = &scif7_platform_data,
215 },
216};
217
218static struct plat_sci_port scif8_platform_data = {
219 .mapbase = 0xe6c30000,
220 .flags = UPF_BOOT_AUTOCONF,
221 .scscr = SCSCR_RE | SCSCR_TE,
222 .scbrr_algo_id = SCBRR_ALGO_4,
223 .type = PORT_SCIFB,
224 .irqs = { gic_spi(80), gic_spi(80),
225 gic_spi(80), gic_spi(80) },
226};
227 96
228static struct platform_device scif8_device = { 97SH73A0_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(72));
229 .name = "sh-sci", 98SH73A0_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(73));
230 .id = 8, 99SH73A0_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(74));
231 .dev = { 100SH73A0_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(75));
232 .platform_data = &scif8_platform_data, 101SH73A0_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(78));
233 }, 102SH73A0_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(79));
234}; 103SH73A0_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(156));
104SH73A0_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(143));
105SH73A0_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(80));
235 106
236static struct sh_timer_config cmt10_platform_data = { 107static struct sh_timer_config cmt10_platform_data = {
237 .name = "CMT10", 108 .name = "CMT10",
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-03 11:08:25 -0500