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-rw-r--r--arch/arm/mach-exynos4/cpu.c28
-rw-r--r--arch/arm/mach-exynos4/include/mach/map.h3
-rw-r--r--arch/arm/mach-exynos4/platsmp.c8
-rw-r--r--arch/arm/mach-s3c64xx/cpu.c22
-rw-r--r--arch/arm/mach-s5p64x0/dev-spi.c8
-rw-r--r--arch/arm/mach-s5p64x0/dma.c7
-rw-r--r--arch/arm/mach-s5p64x0/gpiolib.c7
-rw-r--r--arch/arm/mach-s5p64x0/irq-eint.c3
-rw-r--r--arch/arm/plat-s3c24xx/cpu.c9
-rw-r--r--arch/arm/plat-s5p/cpu.c28
-rw-r--r--arch/arm/plat-samsung/Makefile2
-rw-r--r--arch/arm/plat-samsung/cpu.c58
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu.h97
13 files changed, 220 insertions, 60 deletions
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 746d6fc6d397..0d281bbe345a 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -44,11 +44,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
44 .length = SZ_4K, 44 .length = SZ_4K,
45 .type = MT_DEVICE, 45 .type = MT_DEVICE,
46 }, { 46 }, {
47 .virtual = (unsigned long)S5P_VA_SYSRAM,
48 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM),
49 .length = SZ_4K,
50 .type = MT_DEVICE,
51 }, {
52 .virtual = (unsigned long)S5P_VA_CMU, 47 .virtual = (unsigned long)S5P_VA_CMU,
53 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU), 48 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
54 .length = SZ_128K, 49 .length = SZ_128K,
@@ -121,6 +116,24 @@ static struct map_desc exynos4_iodesc[] __initdata = {
121 }, 116 },
122}; 117};
123 118
119static struct map_desc exynos4_iodesc0[] __initdata = {
120 {
121 .virtual = (unsigned long)S5P_VA_SYSRAM,
122 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
123 .length = SZ_4K,
124 .type = MT_DEVICE,
125 },
126};
127
128static struct map_desc exynos4_iodesc1[] __initdata = {
129 {
130 .virtual = (unsigned long)S5P_VA_SYSRAM,
131 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
132 .length = SZ_4K,
133 .type = MT_DEVICE,
134 },
135};
136
124static void exynos4_idle(void) 137static void exynos4_idle(void)
125{ 138{
126 if (!need_resched()) 139 if (!need_resched())
@@ -143,6 +156,11 @@ void __init exynos4_map_io(void)
143{ 156{
144 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc)); 157 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
145 158
159 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
160 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
161 else
162 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
163
146 /* initialize device information early */ 164 /* initialize device information early */
147 exynos4_default_sdhci0(); 165 exynos4_default_sdhci0();
148 exynos4_default_sdhci1(); 166 exynos4_default_sdhci1();
diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h
index d32296dc65e2..7073ac730855 100644
--- a/arch/arm/mach-exynos4/include/mach/map.h
+++ b/arch/arm/mach-exynos4/include/mach/map.h
@@ -23,7 +23,8 @@
23 23
24#include <plat/map-s5p.h> 24#include <plat/map-s5p.h>
25 25
26#define EXYNOS4_PA_SYSRAM 0x02020000 26#define EXYNOS4_PA_SYSRAM0 0x02025000
27#define EXYNOS4_PA_SYSRAM1 0x02020000
27 28
28#define EXYNOS4_PA_FIMC0 0x11800000 29#define EXYNOS4_PA_FIMC0 0x11800000
29#define EXYNOS4_PA_FIMC1 0x11810000 30#define EXYNOS4_PA_FIMC1 0x11810000
diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c
index df6ef1b2f98b..a3346e36d0ae 100644
--- a/arch/arm/mach-exynos4/platsmp.c
+++ b/arch/arm/mach-exynos4/platsmp.c
@@ -30,9 +30,12 @@
30#include <mach/regs-clock.h> 30#include <mach/regs-clock.h>
31#include <mach/regs-pmu.h> 31#include <mach/regs-pmu.h>
32 32
33#include <plat/cpu.h>
34
33extern void exynos4_secondary_startup(void); 35extern void exynos4_secondary_startup(void);
34 36
35#define CPU1_BOOT_REG S5P_VA_SYSRAM 37#define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
38 S5P_INFORM5 : S5P_VA_SYSRAM)
36 39
37/* 40/*
38 * control for which core is the next to come out of the secondary 41 * control for which core is the next to come out of the secondary
@@ -218,5 +221,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
218 * until it receives a soft interrupt, and then the 221 * until it receives a soft interrupt, and then the
219 * secondary CPU branches to this address. 222 * secondary CPU branches to this address.
220 */ 223 */
221 __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), S5P_VA_SYSRAM); 224 __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
225 CPU1_BOOT_REG);
222} 226}
diff --git a/arch/arm/mach-s3c64xx/cpu.c b/arch/arm/mach-s3c64xx/cpu.c
index 374e45e566b8..6c498f9a18c5 100644
--- a/arch/arm/mach-s3c64xx/cpu.c
+++ b/arch/arm/mach-s3c64xx/cpu.c
@@ -43,16 +43,16 @@ static const char name_s3c6410[] = "S3C6410";
43 43
44static struct cpu_table cpu_ids[] __initdata = { 44static struct cpu_table cpu_ids[] __initdata = {
45 { 45 {
46 .idcode = 0x36400000, 46 .idcode = S3C6400_CPU_ID,
47 .idmask = 0xfffff000, 47 .idmask = S3C64XX_CPU_MASK,
48 .map_io = s3c6400_map_io, 48 .map_io = s3c6400_map_io,
49 .init_clocks = s3c6400_init_clocks, 49 .init_clocks = s3c6400_init_clocks,
50 .init_uarts = s3c6400_init_uarts, 50 .init_uarts = s3c6400_init_uarts,
51 .init = s3c6400_init, 51 .init = s3c6400_init,
52 .name = name_s3c6400, 52 .name = name_s3c6400,
53 }, { 53 }, {
54 .idcode = 0x36410100, 54 .idcode = S3C6410_CPU_ID,
55 .idmask = 0xffffff00, 55 .idmask = S3C64XX_CPU_MASK,
56 .map_io = s3c6410_map_io, 56 .map_io = s3c6410_map_io,
57 .init_clocks = s3c6410_init_clocks, 57 .init_clocks = s3c6410_init_clocks,
58 .init_uarts = s3c6410_init_uarts, 58 .init_uarts = s3c6410_init_uarts,
@@ -140,22 +140,14 @@ void __init s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
140 140
141void __init s3c64xx_init_io(struct map_desc *mach_desc, int size) 141void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
142{ 142{
143 unsigned long idcode;
144
145 /* initialise the io descriptors we need for initialisation */ 143 /* initialise the io descriptors we need for initialisation */
146 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); 144 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
147 iotable_init(mach_desc, size); 145 iotable_init(mach_desc, size);
148 146
149 idcode = __raw_readl(S3C_VA_SYS + 0x118); 147 /* detect cpu id */
150 if (!idcode) { 148 s3c64xx_init_cpu();
151 /* S3C6400 has the ID register in a different place,
152 * and needs a write before it can be read. */
153
154 __raw_writel(0x0, S3C_VA_SYS + 0xA1C);
155 idcode = __raw_readl(S3C_VA_SYS + 0xA1C);
156 }
157 149
158 s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); 150 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
159} 151}
160 152
161static __init int s3c64xx_sysdev_init(void) 153static __init int s3c64xx_sysdev_init(void)
diff --git a/arch/arm/mach-s5p64x0/dev-spi.c b/arch/arm/mach-s5p64x0/dev-spi.c
index ac825e826326..1fd9c79c7dbc 100644
--- a/arch/arm/mach-s5p64x0/dev-spi.c
+++ b/arch/arm/mach-s5p64x0/dev-spi.c
@@ -21,6 +21,7 @@
21#include <mach/regs-clock.h> 21#include <mach/regs-clock.h>
22#include <mach/spi-clocks.h> 22#include <mach/spi-clocks.h>
23 23
24#include <plat/cpu.h>
24#include <plat/s3c64xx-spi.h> 25#include <plat/s3c64xx-spi.h>
25#include <plat/gpio-cfg.h> 26#include <plat/gpio-cfg.h>
26 27
@@ -185,11 +186,8 @@ struct platform_device s5p64x0_device_spi1 = {
185 186
186void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) 187void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
187{ 188{
188 unsigned int id;
189 struct s3c64xx_spi_info *pd; 189 struct s3c64xx_spi_info *pd;
190 190
191 id = __raw_readl(S5P64X0_SYS_ID) & 0xFF000;
192
193 /* Reject invalid configuration */ 191 /* Reject invalid configuration */
194 if (!num_cs || src_clk_nr < 0 192 if (!num_cs || src_clk_nr < 0
195 || src_clk_nr > S5P64X0_SPI_SRCCLK_SCLK) { 193 || src_clk_nr > S5P64X0_SPI_SRCCLK_SCLK) {
@@ -199,7 +197,7 @@ void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
199 197
200 switch (cntrlr) { 198 switch (cntrlr) {
201 case 0: 199 case 0:
202 if (id == 0x50000) 200 if (soc_is_s5p6450())
203 pd = &s5p6450_spi0_pdata; 201 pd = &s5p6450_spi0_pdata;
204 else 202 else
205 pd = &s5p6440_spi0_pdata; 203 pd = &s5p6440_spi0_pdata;
@@ -207,7 +205,7 @@ void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
207 s5p64x0_device_spi0.dev.platform_data = pd; 205 s5p64x0_device_spi0.dev.platform_data = pd;
208 break; 206 break;
209 case 1: 207 case 1:
210 if (id == 0x50000) 208 if (soc_is_s5p6450())
211 pd = &s5p6450_spi1_pdata; 209 pd = &s5p6450_spi1_pdata;
212 else 210 else
213 pd = &s5p6440_spi1_pdata; 211 pd = &s5p6440_spi1_pdata;
diff --git a/arch/arm/mach-s5p64x0/dma.c b/arch/arm/mach-s5p64x0/dma.c
index d7ad944b3475..0e5b3e63e5b3 100644
--- a/arch/arm/mach-s5p64x0/dma.c
+++ b/arch/arm/mach-s5p64x0/dma.c
@@ -28,6 +28,7 @@
28#include <mach/irqs.h> 28#include <mach/irqs.h>
29#include <mach/regs-clock.h> 29#include <mach/regs-clock.h>
30 30
31#include <plat/cpu.h>
31#include <plat/devs.h> 32#include <plat/devs.h>
32#include <plat/s3c-pl330-pdata.h> 33#include <plat/s3c-pl330-pdata.h>
33 34
@@ -133,11 +134,7 @@ static struct platform_device s5p64x0_device_pdma = {
133 134
134static int __init s5p64x0_dma_init(void) 135static int __init s5p64x0_dma_init(void)
135{ 136{
136 unsigned int id; 137 if (soc_is_s5p6450())
137
138 id = __raw_readl(S5P64X0_SYS_ID) & 0xFF000;
139
140 if (id == 0x50000)
141 s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata; 138 s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata;
142 else 139 else
143 s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata; 140 s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata;
diff --git a/arch/arm/mach-s5p64x0/gpiolib.c b/arch/arm/mach-s5p64x0/gpiolib.c
index e7fb3b004e77..700dac6c43f3 100644
--- a/arch/arm/mach-s5p64x0/gpiolib.c
+++ b/arch/arm/mach-s5p64x0/gpiolib.c
@@ -19,6 +19,7 @@
19#include <mach/regs-gpio.h> 19#include <mach/regs-gpio.h>
20#include <mach/regs-clock.h> 20#include <mach/regs-clock.h>
21 21
22#include <plat/cpu.h>
22#include <plat/gpio-core.h> 23#include <plat/gpio-core.h>
23#include <plat/gpio-cfg.h> 24#include <plat/gpio-cfg.h>
24#include <plat/gpio-cfg-helpers.h> 25#include <plat/gpio-cfg-helpers.h>
@@ -473,14 +474,10 @@ static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
473 474
474static int __init s5p64x0_gpiolib_init(void) 475static int __init s5p64x0_gpiolib_init(void)
475{ 476{
476 unsigned int chipid;
477
478 chipid = __raw_readl(S5P64X0_SYS_ID);
479
480 s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs, 477 s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs,
481 ARRAY_SIZE(s5p64x0_gpio_cfgs)); 478 ARRAY_SIZE(s5p64x0_gpio_cfgs));
482 479
483 if ((chipid & 0xff000) == 0x50000) { 480 if (soc_is_s5p6450()) {
484 samsung_gpiolib_add_2bit_chips(s5p6450_gpio_2bit, 481 samsung_gpiolib_add_2bit_chips(s5p6450_gpio_2bit,
485 ARRAY_SIZE(s5p6450_gpio_2bit)); 482 ARRAY_SIZE(s5p6450_gpio_2bit));
486 483
diff --git a/arch/arm/mach-s5p64x0/irq-eint.c b/arch/arm/mach-s5p64x0/irq-eint.c
index fe7380f5c3cd..494e1a8f6f6d 100644
--- a/arch/arm/mach-s5p64x0/irq-eint.c
+++ b/arch/arm/mach-s5p64x0/irq-eint.c
@@ -17,6 +17,7 @@
17#include <linux/irq.h> 17#include <linux/irq.h>
18#include <linux/io.h> 18#include <linux/io.h>
19 19
20#include <plat/cpu.h>
20#include <plat/regs-irqtype.h> 21#include <plat/regs-irqtype.h>
21#include <plat/gpio-cfg.h> 22#include <plat/gpio-cfg.h>
22 23
@@ -67,7 +68,7 @@ static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
67 __raw_writel(ctrl, S5P64X0_EINT0CON0); 68 __raw_writel(ctrl, S5P64X0_EINT0CON0);
68 69
69 /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */ 70 /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
70 if (0x50000 == (__raw_readl(S5P64X0_SYS_ID) & 0xFF000)) 71 if (soc_is_s5p6450())
71 s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2)); 72 s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
72 else 73 else
73 s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2)); 74 s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index c1fc6c6fac72..3c6335307fb1 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -215,19 +215,18 @@ static void s3c24xx_pm_restart(char mode, const char *cmd)
215 215
216void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) 216void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
217{ 217{
218 unsigned long idcode = 0x0;
219
220 /* initialise the io descriptors we need for initialisation */ 218 /* initialise the io descriptors we need for initialisation */
221 iotable_init(mach_desc, size); 219 iotable_init(mach_desc, size);
222 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); 220 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
223 221
224 if (cpu_architecture() >= CPU_ARCH_ARMv5) { 222 if (cpu_architecture() >= CPU_ARCH_ARMv5) {
225 idcode = s3c24xx_read_idcode_v5(); 223 samsung_cpu_id = s3c24xx_read_idcode_v5();
226 } else { 224 } else {
227 idcode = s3c24xx_read_idcode_v4(); 225 samsung_cpu_id = s3c24xx_read_idcode_v4();
228 } 226 }
227 s3c24xx_init_cpu();
229 228
230 arm_pm_restart = s3c24xx_pm_restart; 229 arm_pm_restart = s3c24xx_pm_restart;
231 230
232 s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); 231 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
233} 232}
diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
index bbc2aa7449ca..04392c70d055 100644
--- a/arch/arm/plat-s5p/cpu.c
+++ b/arch/arm/plat-s5p/cpu.c
@@ -36,40 +36,40 @@ static const char name_exynos4210[] = "EXYNOS4210";
36 36
37static struct cpu_table cpu_ids[] __initdata = { 37static struct cpu_table cpu_ids[] __initdata = {
38 { 38 {
39 .idcode = 0x56440100, 39 .idcode = S5P6440_CPU_ID,
40 .idmask = 0xfffff000, 40 .idmask = S5P64XX_CPU_MASK,
41 .map_io = s5p6440_map_io, 41 .map_io = s5p6440_map_io,
42 .init_clocks = s5p6440_init_clocks, 42 .init_clocks = s5p6440_init_clocks,
43 .init_uarts = s5p6440_init_uarts, 43 .init_uarts = s5p6440_init_uarts,
44 .init = s5p64x0_init, 44 .init = s5p64x0_init,
45 .name = name_s5p6440, 45 .name = name_s5p6440,
46 }, { 46 }, {
47 .idcode = 0x36450000, 47 .idcode = S5P6450_CPU_ID,
48 .idmask = 0xfffff000, 48 .idmask = S5P64XX_CPU_MASK,
49 .map_io = s5p6450_map_io, 49 .map_io = s5p6450_map_io,
50 .init_clocks = s5p6450_init_clocks, 50 .init_clocks = s5p6450_init_clocks,
51 .init_uarts = s5p6450_init_uarts, 51 .init_uarts = s5p6450_init_uarts,
52 .init = s5p64x0_init, 52 .init = s5p64x0_init,
53 .name = name_s5p6450, 53 .name = name_s5p6450,
54 }, { 54 }, {
55 .idcode = 0x43100000, 55 .idcode = S5PC100_CPU_ID,
56 .idmask = 0xfffff000, 56 .idmask = S5PC100_CPU_MASK,
57 .map_io = s5pc100_map_io, 57 .map_io = s5pc100_map_io,
58 .init_clocks = s5pc100_init_clocks, 58 .init_clocks = s5pc100_init_clocks,
59 .init_uarts = s5pc100_init_uarts, 59 .init_uarts = s5pc100_init_uarts,
60 .init = s5pc100_init, 60 .init = s5pc100_init,
61 .name = name_s5pc100, 61 .name = name_s5pc100,
62 }, { 62 }, {
63 .idcode = 0x43110000, 63 .idcode = S5PV210_CPU_ID,
64 .idmask = 0xfffff000, 64 .idmask = S5PV210_CPU_MASK,
65 .map_io = s5pv210_map_io, 65 .map_io = s5pv210_map_io,
66 .init_clocks = s5pv210_init_clocks, 66 .init_clocks = s5pv210_init_clocks,
67 .init_uarts = s5pv210_init_uarts, 67 .init_uarts = s5pv210_init_uarts,
68 .init = s5pv210_init, 68 .init = s5pv210_init,
69 .name = name_s5pv210, 69 .name = name_s5pv210,
70 }, { 70 }, {
71 .idcode = 0x43210000, 71 .idcode = EXYNOS4210_CPU_ID,
72 .idmask = 0xfffe0000, 72 .idmask = EXYNOS4_CPU_MASK,
73 .map_io = exynos4_map_io, 73 .map_io = exynos4_map_io,
74 .init_clocks = exynos4_init_clocks, 74 .init_clocks = exynos4_init_clocks,
75 .init_uarts = exynos4_init_uarts, 75 .init_uarts = exynos4_init_uarts,
@@ -114,13 +114,13 @@ static struct map_desc s5p_iodesc[] __initdata = {
114void __init s5p_init_io(struct map_desc *mach_desc, 114void __init s5p_init_io(struct map_desc *mach_desc,
115 int size, void __iomem *cpuid_addr) 115 int size, void __iomem *cpuid_addr)
116{ 116{
117 unsigned long idcode;
118
119 /* initialize the io descriptors we need for initialization */ 117 /* initialize the io descriptors we need for initialization */
120 iotable_init(s5p_iodesc, ARRAY_SIZE(s5p_iodesc)); 118 iotable_init(s5p_iodesc, ARRAY_SIZE(s5p_iodesc));
121 if (mach_desc) 119 if (mach_desc)
122 iotable_init(mach_desc, size); 120 iotable_init(mach_desc, size);
123 121
124 idcode = __raw_readl(cpuid_addr); 122 /* detect cpu id and rev. */
125 s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); 123 s5p_init_cpu(cpuid_addr);
124
125 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
126} 126}
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 853764ba8cc5..3de756da5eaa 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -11,7 +11,7 @@ obj- :=
11 11
12# Objects we always build independent of SoC choice 12# Objects we always build independent of SoC choice
13 13
14obj-y += init.o 14obj-y += init.o cpu.o
15obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET) += time.o 15obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET) += time.o
16obj-y += clock.o 16obj-y += clock.o
17obj-y += pwm-clock.o 17obj-y += pwm-clock.o
diff --git a/arch/arm/plat-samsung/cpu.c b/arch/arm/plat-samsung/cpu.c
new file mode 100644
index 000000000000..81c06d44c11e
--- /dev/null
+++ b/arch/arm/plat-samsung/cpu.c
@@ -0,0 +1,58 @@
1/* linux/arch/arm/plat-samsung/cpu.c
2 *
3 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Samsung CPU Support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/io.h>
17
18#include <asm/system.h>
19
20#include <mach/map.h>
21#include <plat/cpu.h>
22
23unsigned long samsung_cpu_id;
24static unsigned int samsung_cpu_rev;
25
26unsigned int samsung_rev(void)
27{
28 return samsung_cpu_rev;
29}
30EXPORT_SYMBOL(samsung_rev);
31
32void __init s3c24xx_init_cpu(void)
33{
34 /* nothing here yet */
35
36 samsung_cpu_rev = 0;
37}
38
39void __init s3c64xx_init_cpu(void)
40{
41 samsung_cpu_id = __raw_readl(S3C_VA_SYS + 0x118);
42 if (!samsung_cpu_id) {
43 /*
44 * S3C6400 has the ID register in a different place,
45 * and needs a write before it can be read.
46 */
47 __raw_writel(0x0, S3C_VA_SYS + 0xA1C);
48 samsung_cpu_id = __raw_readl(S3C_VA_SYS + 0xA1C);
49 }
50
51 samsung_cpu_rev = 0;
52}
53
54void __init s5p_init_cpu(void __iomem *cpuid_addr)
55{
56 samsung_cpu_id = __raw_readl(cpuid_addr);
57 samsung_cpu_rev = samsung_cpu_id & 0xFF;
58}
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index c0a5741b23e6..efd920ec3b75 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -1,9 +1,12 @@
1/* linux/arch/arm/plat-samsung/include/plat/cpu.h 1/* linux/arch/arm/plat-samsung/include/plat/cpu.h
2 * 2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
3 * Copyright (c) 2004-2005 Simtec Electronics 6 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 7 * Ben Dooks <ben@simtec.co.uk>
5 * 8 *
6 * Header file for S3C24XX CPU support 9 * Header file for Samsung CPU support
7 * 10 *
8 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 12 * it under the terms of the GNU General Public License version 2 as
@@ -15,6 +18,92 @@
15#ifndef __SAMSUNG_PLAT_CPU_H 18#ifndef __SAMSUNG_PLAT_CPU_H
16#define __SAMSUNG_PLAT_CPU_H 19#define __SAMSUNG_PLAT_CPU_H
17 20
21extern unsigned long samsung_cpu_id;
22
23#define S3C24XX_CPU_ID 0x32400000
24#define S3C24XX_CPU_MASK 0xFFF00000
25
26#define S3C6400_CPU_ID 0x36400000
27#define S3C6410_CPU_ID 0x36410000
28#define S3C64XX_CPU_ID (S3C6400_CPU_ID & S3C6410_CPU_ID)
29#define S3C64XX_CPU_MASK 0xFFFFF000
30
31#define S5P6440_CPU_ID 0x56440000
32#define S5P6450_CPU_ID 0x36450000
33#define S5P64XX_CPU_MASK 0xFFFFF000
34
35#define S5PC100_CPU_ID 0x43100000
36#define S5PC100_CPU_MASK 0xFFFFF000
37
38#define S5PV210_CPU_ID 0x43110000
39#define S5PV210_CPU_MASK 0xFFFFF000
40
41#define EXYNOS4210_CPU_ID 0x43210000
42#define EXYNOS4_CPU_MASK 0xFFFE0000
43
44#define IS_SAMSUNG_CPU(name, id, mask) \
45static inline int is_samsung_##name(void) \
46{ \
47 return ((samsung_cpu_id & mask) == (id & mask)); \
48}
49
50IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK)
51IS_SAMSUNG_CPU(s3c64xx, S3C64XX_CPU_ID, S3C64XX_CPU_MASK)
52IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK)
53IS_SAMSUNG_CPU(s5p6450, S5P6450_CPU_ID, S5P64XX_CPU_MASK)
54IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK)
55IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
56IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
57
58#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
59 defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
60 defined(CONFIG_CPU_S3C2442) || defined(CONFIG_CPU_S3C244X) || \
61 defined(CONFIG_CPU_S3C2443)
62# define soc_is_s3c24xx() is_samsung_s3c24xx()
63#else
64# define soc_is_s3c24xx() 0
65#endif
66
67#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
68# define soc_is_s3c64xx() is_samsung_s3c64xx()
69#else
70# define soc_is_s3c64xx() 0
71#endif
72
73#if defined(CONFIG_CPU_S5P6440)
74# define soc_is_s5p6440() is_samsung_s5p6440()
75#else
76# define soc_is_s5p6440() 0
77#endif
78
79#if defined(CONFIG_CPU_S5P6450)
80# define soc_is_s5p6450() is_samsung_s5p6450()
81#else
82# define soc_is_s5p6450() 0
83#endif
84
85#if defined(CONFIG_CPU_S5PC100)
86# define soc_is_s5pc100() is_samsung_s5pc100()
87#else
88# define soc_is_s5pc100() 0
89#endif
90
91#if defined(CONFIG_CPU_S5PV210)
92# define soc_is_s5pv210() is_samsung_s5pv210()
93#else
94# define soc_is_s5pv210() 0
95#endif
96
97#if defined(CONFIG_CPU_EXYNOS4210)
98# define soc_is_exynos4210() is_samsung_exynos4210()
99#else
100# define soc_is_exynos4210() 0
101#endif
102
103#define EXYNOS4210_REV_0 (0x0)
104#define EXYNOS4210_REV_1_0 (0x10)
105#define EXYNOS4210_REV_1_1 (0x11)
106
18#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } 107#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
19 108
20#ifndef MHZ 109#ifndef MHZ
@@ -55,6 +144,12 @@ extern void s3c64xx_init_io(struct map_desc *mach_desc, int size);
55extern void s5p_init_io(struct map_desc *mach_desc, 144extern void s5p_init_io(struct map_desc *mach_desc,
56 int size, void __iomem *cpuid_addr); 145 int size, void __iomem *cpuid_addr);
57 146
147extern void s3c24xx_init_cpu(void);
148extern void s3c64xx_init_cpu(void);
149extern void s5p_init_cpu(void __iomem *cpuid_addr);
150
151extern unsigned int samsung_rev(void);
152
58extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no); 153extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no);
59 154
60extern void s3c24xx_init_clocks(int xtal); 155extern void s3c24xx_init_clocks(int xtal);