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-rw-r--r--arch/arm/boot/dts/sh7377.dtsi21
-rw-r--r--arch/arm/configs/armadillo800eva_defconfig1
-rw-r--r--arch/arm/mach-shmobile/Kconfig12
-rw-r--r--arch/arm/mach-shmobile/Makefile6
-rw-r--r--arch/arm/mach-shmobile/board-ap4evb.c2
-rw-r--r--arch/arm/mach-shmobile/board-mackerel.c2
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7740.c34
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7779.c23
-rw-r--r--arch/arm/mach-shmobile/clock-sh7367.c355
-rw-r--r--arch/arm/mach-shmobile/clock-sh7372.c94
-rw-r--r--arch/arm/mach-shmobile/clock-sh7377.c366
-rw-r--r--arch/arm/mach-shmobile/include/mach/common.h18
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7779.h2
-rw-r--r--arch/arm/mach-shmobile/include/mach/sh7367.h332
-rw-r--r--arch/arm/mach-shmobile/include/mach/sh7372.h6
-rw-r--r--arch/arm/mach-shmobile/include/mach/sh7377.h360
-rw-r--r--arch/arm/mach-shmobile/intc-sh7367.c413
-rw-r--r--arch/arm/mach-shmobile/intc-sh7377.c592
-rw-r--r--arch/arm/mach-shmobile/pfc-r8a7779.c16
-rw-r--r--arch/arm/mach-shmobile/pfc-sh7367.c1727
-rw-r--r--arch/arm/mach-shmobile/pfc-sh7377.c1688
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7740.c18
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7779.c77
-rw-r--r--arch/arm/mach-shmobile/setup-sh7367.c481
-rw-r--r--arch/arm/mach-shmobile/setup-sh7372.c20
-rw-r--r--arch/arm/mach-shmobile/setup-sh7377.c549
-rw-r--r--arch/arm/mach-shmobile/smp-emev2.c22
-rw-r--r--arch/arm/mach-shmobile/smp-r8a7779.c25
-rw-r--r--arch/arm/mach-shmobile/smp-sh73a0.c23
29 files changed, 205 insertions, 7080 deletions
diff --git a/arch/arm/boot/dts/sh7377.dtsi b/arch/arm/boot/dts/sh7377.dtsi
deleted file mode 100644
index 767ee0796daa..000000000000
--- a/arch/arm/boot/dts/sh7377.dtsi
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * Device Tree Source for the sh7377 SoC
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 compatible = "renesas,sh7377";
15
16 cpus {
17 cpu@0 {
18 compatible = "arm,cortex-a8";
19 };
20 };
21};
diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig
index f78d259f8d23..3d764072dd54 100644
--- a/arch/arm/configs/armadillo800eva_defconfig
+++ b/arch/arm/configs/armadillo800eva_defconfig
@@ -7,6 +7,7 @@ CONFIG_LOG_BUF_SHIFT=16
7# CONFIG_IPC_NS is not set 7# CONFIG_IPC_NS is not set
8# CONFIG_PID_NS is not set 8# CONFIG_PID_NS is not set
9CONFIG_CC_OPTIMIZE_FOR_SIZE=y 9CONFIG_CC_OPTIMIZE_FOR_SIZE=y
10CONFIG_PERF_EVENTS=y
10CONFIG_SLAB=y 11CONFIG_SLAB=y
11CONFIG_MODULES=y 12CONFIG_MODULES=y
12CONFIG_MODULE_UNLOAD=y 13CONFIG_MODULE_UNLOAD=y
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index f58c3ea97732..4eddca14ae07 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -2,18 +2,6 @@ if ARCH_SHMOBILE
2 2
3comment "SH-Mobile System Type" 3comment "SH-Mobile System Type"
4 4
5config ARCH_SH7367
6 bool "SH-Mobile G3 (SH7367)"
7 select ARCH_WANT_OPTIONAL_GPIOLIB
8 select CPU_V6
9 select SH_CLK_CPG
10
11config ARCH_SH7377
12 bool "SH-Mobile G4 (SH7377)"
13 select ARCH_WANT_OPTIONAL_GPIOLIB
14 select CPU_V7
15 select SH_CLK_CPG
16
17config ARCH_SH7372 5config ARCH_SH7372
18 bool "SH-Mobile AP4 (SH7372)" 6 bool "SH-Mobile AP4 (SH7372)"
19 select ARCH_WANT_OPTIONAL_GPIOLIB 7 select ARCH_WANT_OPTIONAL_GPIOLIB
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index bd2633bb175a..0b7147928aa3 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -6,8 +6,6 @@
6obj-y := timer.o console.o clock.o 6obj-y := timer.o console.o clock.o
7 7
8# CPU objects 8# CPU objects
9obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o
10obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7377.o intc-sh7377.o
11obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o 9obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o
12obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o 10obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o
13obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o 11obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o
@@ -23,16 +21,12 @@ smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o
23 21
24# Pinmux setup 22# Pinmux setup
25pfc-y := 23pfc-y :=
26pfc-$(CONFIG_ARCH_SH7367) += pfc-sh7367.o
27pfc-$(CONFIG_ARCH_SH7377) += pfc-sh7377.o
28pfc-$(CONFIG_ARCH_SH7372) += pfc-sh7372.o 24pfc-$(CONFIG_ARCH_SH7372) += pfc-sh7372.o
29pfc-$(CONFIG_ARCH_SH73A0) += pfc-sh73a0.o 25pfc-$(CONFIG_ARCH_SH73A0) += pfc-sh73a0.o
30pfc-$(CONFIG_ARCH_R8A7740) += pfc-r8a7740.o 26pfc-$(CONFIG_ARCH_R8A7740) += pfc-r8a7740.o
31pfc-$(CONFIG_ARCH_R8A7779) += pfc-r8a7779.o 27pfc-$(CONFIG_ARCH_R8A7779) += pfc-r8a7779.o
32 28
33# IRQ objects 29# IRQ objects
34obj-$(CONFIG_ARCH_SH7367) += entry-intc.o
35obj-$(CONFIG_ARCH_SH7377) += entry-intc.o
36obj-$(CONFIG_ARCH_SH7372) += entry-intc.o 30obj-$(CONFIG_ARCH_SH7372) += entry-intc.o
37obj-$(CONFIG_ARCH_R8A7740) += entry-intc.o 31obj-$(CONFIG_ARCH_R8A7740) += entry-intc.o
38 32
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 790dc68c4312..cefdd030361d 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -728,7 +728,7 @@ fsia_ick_out:
728static int fsi_hdmi_set_rate(struct device *dev, int rate, int enable) 728static int fsi_hdmi_set_rate(struct device *dev, int rate, int enable)
729{ 729{
730 struct clk *fsib_clk; 730 struct clk *fsib_clk;
731 struct clk *fdiv_clk = &sh7372_fsidivb_clk; 731 struct clk *fdiv_clk = clk_get(NULL, "fsidivb");
732 long fsib_rate = 0; 732 long fsib_rate = 0;
733 long fdiv_rate = 0; 733 long fdiv_rate = 0;
734 int ackmd_bpfmd; 734 int ackmd_bpfmd;
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 39b8f2e70638..f274252e4705 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -882,7 +882,7 @@ static int __fsi_set_round_rate(struct clk *clk, long rate, int enable)
882static int fsi_b_set_rate(struct device *dev, int rate, int enable) 882static int fsi_b_set_rate(struct device *dev, int rate, int enable)
883{ 883{
884 struct clk *fsib_clk; 884 struct clk *fsib_clk;
885 struct clk *fdiv_clk = &sh7372_fsidivb_clk; 885 struct clk *fdiv_clk = clk_get(NULL, "fsidivb");
886 long fsib_rate = 0; 886 long fsib_rate = 0;
887 long fdiv_rate = 0; 887 long fdiv_rate = 0;
888 int ackmd_bpfmd; 888 int ackmd_bpfmd;
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index 6729e0032180..eac49d59782f 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -65,6 +65,9 @@
65#define SMSTPCR3 IOMEM(0xe615013c) 65#define SMSTPCR3 IOMEM(0xe615013c)
66#define SMSTPCR4 IOMEM(0xe6150140) 66#define SMSTPCR4 IOMEM(0xe6150140)
67 67
68#define FSIDIVA IOMEM(0xFE1F8000)
69#define FSIDIVB IOMEM(0xFE1F8008)
70
68/* Fixed 32 KHz root clock from EXTALR pin */ 71/* Fixed 32 KHz root clock from EXTALR pin */
69static struct clk extalr_clk = { 72static struct clk extalr_clk = {
70 .rate = 32768, 73 .rate = 32768,
@@ -188,6 +191,22 @@ static struct clk pllc1_div2_clk = {
188}; 191};
189 192
190/* USB clock */ 193/* USB clock */
194/*
195 * USBCKCR is controlling usb24 clock
196 * bit[7] : parent clock
197 * bit[6] : clock divide rate
198 * And this bit[7] is used as a "usb24s" from other devices.
199 * (Video clock / Sub clock / SPU clock)
200 * You can controll this clock as a below.
201 *
202 * struct clk *usb24 = clk_get(dev, "usb24");
203 * struct clk *usb24s = clk_get(NULL, "usb24s");
204 * struct clk *system = clk_get(NULL, "system_clk");
205 * int rate = clk_get_rate(system);
206 *
207 * clk_set_parent(usb24s, system); // for bit[7]
208 * clk_set_rate(usb24, rate / 2); // for bit[6]
209 */
191static struct clk *usb24s_parents[] = { 210static struct clk *usb24s_parents[] = {
192 [0] = &system_clk, 211 [0] = &system_clk,
193 [1] = &extal2_clk 212 [1] = &extal2_clk
@@ -427,6 +446,14 @@ static struct clk *late_main_clks[] = {
427 &hdmi2_clk, 446 &hdmi2_clk,
428}; 447};
429 448
449/* FSI DIV */
450enum { FSIDIV_A, FSIDIV_B, FSIDIV_REPARENT_NR };
451
452static struct clk fsidivs[] = {
453 [FSIDIV_A] = SH_CLK_FSIDIV(FSIDIVA, &div6_reparent_clks[DIV6_FSIA]),
454 [FSIDIV_B] = SH_CLK_FSIDIV(FSIDIVB, &div6_reparent_clks[DIV6_FSIB]),
455};
456
430/* MSTP */ 457/* MSTP */
431enum { 458enum {
432 DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP, 459 DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
@@ -596,6 +623,10 @@ static struct clk_lookup lookups[] = {
596 623
597 CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]), 624 CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
598 CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]), 625 CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),
626 CLKDEV_ICK_ID("diva", "sh_fsi2", &fsidivs[FSIDIV_A]),
627 CLKDEV_ICK_ID("divb", "sh_fsi2", &fsidivs[FSIDIV_B]),
628 CLKDEV_ICK_ID("xcka", "sh_fsi2", &fsiack_clk),
629 CLKDEV_ICK_ID("xckb", "sh_fsi2", &fsibck_clk),
599}; 630};
600 631
601void __init r8a7740_clock_init(u8 md_ck) 632void __init r8a7740_clock_init(u8 md_ck)
@@ -641,6 +672,9 @@ void __init r8a7740_clock_init(u8 md_ck)
641 for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++) 672 for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
642 ret = clk_register(late_main_clks[k]); 673 ret = clk_register(late_main_clks[k]);
643 674
675 if (!ret)
676 ret = sh_clk_fsidiv_register(fsidivs, FSIDIV_REPARENT_NR);
677
644 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 678 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
645 679
646 if (!ret) 680 if (!ret)
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 3cafb6ab5e9a..be885cfc9eb4 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -87,8 +87,11 @@ static struct clk div4_clks[DIV4_NR] = {
87}; 87};
88 88
89enum { MSTP323, MSTP322, MSTP321, MSTP320, 89enum { MSTP323, MSTP322, MSTP321, MSTP320,
90 MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, 90 MSTP101, MSTP100,
91 MSTP030,
92 MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
91 MSTP016, MSTP015, MSTP014, 93 MSTP016, MSTP015, MSTP014,
94 MSTP007,
92 MSTP_NR }; 95 MSTP_NR };
93 96
94static struct clk mstp_clks[MSTP_NR] = { 97static struct clk mstp_clks[MSTP_NR] = {
@@ -96,6 +99,12 @@ static struct clk mstp_clks[MSTP_NR] = {
96 [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */ 99 [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */
97 [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */ 100 [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */
98 [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */ 101 [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */
102 [MSTP101] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 1, 0), /* USB2 */
103 [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0), /* USB0/1 */
104 [MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0), /* I2C0 */
105 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), /* I2C1 */
106 [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), /* I2C2 */
107 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), /* I2C3 */
99 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */ 108 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */
100 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */ 109 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */
101 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */ 110 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */
@@ -105,6 +114,7 @@ static struct clk mstp_clks[MSTP_NR] = {
105 [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), /* TMU0 */ 114 [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), /* TMU0 */
106 [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), /* TMU1 */ 115 [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), /* TMU1 */
107 [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), /* TMU2 */ 116 [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), /* TMU2 */
117 [MSTP007] = SH_CLK_MSTP32(&div4_clks[DIV4_S], MSTPCR0, 7, 0), /* HSPI */
108}; 118};
109 119
110static unsigned long mul4_recalc(struct clk *clk) 120static unsigned long mul4_recalc(struct clk *clk)
@@ -146,14 +156,25 @@ static struct clk_lookup lookups[] = {
146 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), 156 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
147 157
148 /* MSTP32 clocks */ 158 /* MSTP32 clocks */
159 CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */
160 CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */
161 CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
162 CLKDEV_DEV_ID("ohci-platform.0", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */
149 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */ 163 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
150 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */ 164 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */
165 CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
166 CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */
167 CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */
168 CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */
151 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ 169 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
152 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ 170 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
153 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */ 171 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
154 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */ 172 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
155 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */ 173 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
156 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */ 174 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
175 CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */
176 CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */
177 CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */
157 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */ 178 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
158 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ 179 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
159 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ 180 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
diff --git a/arch/arm/mach-shmobile/clock-sh7367.c b/arch/arm/mach-shmobile/clock-sh7367.c
deleted file mode 100644
index ef0a95e592c4..000000000000
--- a/arch/arm/mach-shmobile/clock-sh7367.c
+++ /dev/null
@@ -1,355 +0,0 @@
1/*
2 * SH7367 clock framework support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19#include <linux/init.h>
20#include <linux/kernel.h>
21#include <linux/io.h>
22#include <linux/sh_clk.h>
23#include <linux/clkdev.h>
24#include <mach/common.h>
25
26/* SH7367 registers */
27#define RTFRQCR IOMEM(0xe6150000)
28#define SYFRQCR IOMEM(0xe6150004)
29#define CMFRQCR IOMEM(0xe61500E0)
30#define VCLKCR1 IOMEM(0xe6150008)
31#define VCLKCR2 IOMEM(0xe615000C)
32#define VCLKCR3 IOMEM(0xe615001C)
33#define SCLKACR IOMEM(0xe6150010)
34#define SCLKBCR IOMEM(0xe6150014)
35#define SUBUSBCKCR IOMEM(0xe6158080)
36#define SPUCKCR IOMEM(0xe6150084)
37#define MSUCKCR IOMEM(0xe6150088)
38#define MVI3CKCR IOMEM(0xe6150090)
39#define VOUCKCR IOMEM(0xe6150094)
40#define MFCK1CR IOMEM(0xe6150098)
41#define MFCK2CR IOMEM(0xe615009C)
42#define PLLC1CR IOMEM(0xe6150028)
43#define PLLC2CR IOMEM(0xe615002C)
44#define RTMSTPCR0 IOMEM(0xe6158030)
45#define RTMSTPCR2 IOMEM(0xe6158038)
46#define SYMSTPCR0 IOMEM(0xe6158040)
47#define SYMSTPCR2 IOMEM(0xe6158048)
48#define CMMSTPCR0 IOMEM(0xe615804c)
49
50/* Fixed 32 KHz root clock from EXTALR pin */
51static struct clk r_clk = {
52 .rate = 32768,
53};
54
55/*
56 * 26MHz default rate for the EXTALB1 root input clock.
57 * If needed, reset this with clk_set_rate() from the platform code.
58 */
59struct clk sh7367_extalb1_clk = {
60 .rate = 26666666,
61};
62
63/*
64 * 48MHz default rate for the EXTAL2 root input clock.
65 * If needed, reset this with clk_set_rate() from the platform code.
66 */
67struct clk sh7367_extal2_clk = {
68 .rate = 48000000,
69};
70
71/* A fixed divide-by-2 block */
72static unsigned long div2_recalc(struct clk *clk)
73{
74 return clk->parent->rate / 2;
75}
76
77static struct sh_clk_ops div2_clk_ops = {
78 .recalc = div2_recalc,
79};
80
81/* Divide extalb1 by two */
82static struct clk extalb1_div2_clk = {
83 .ops = &div2_clk_ops,
84 .parent = &sh7367_extalb1_clk,
85};
86
87/* Divide extal2 by two */
88static struct clk extal2_div2_clk = {
89 .ops = &div2_clk_ops,
90 .parent = &sh7367_extal2_clk,
91};
92
93/* PLLC1 */
94static unsigned long pllc1_recalc(struct clk *clk)
95{
96 unsigned long mult = 1;
97
98 if (__raw_readl(PLLC1CR) & (1 << 14))
99 mult = (((__raw_readl(RTFRQCR) >> 24) & 0x3f) + 1) * 2;
100
101 return clk->parent->rate * mult;
102}
103
104static struct sh_clk_ops pllc1_clk_ops = {
105 .recalc = pllc1_recalc,
106};
107
108static struct clk pllc1_clk = {
109 .ops = &pllc1_clk_ops,
110 .flags = CLK_ENABLE_ON_INIT,
111 .parent = &extalb1_div2_clk,
112};
113
114/* Divide PLLC1 by two */
115static struct clk pllc1_div2_clk = {
116 .ops = &div2_clk_ops,
117 .parent = &pllc1_clk,
118};
119
120/* PLLC2 */
121static unsigned long pllc2_recalc(struct clk *clk)
122{
123 unsigned long mult = 1;
124
125 if (__raw_readl(PLLC2CR) & (1 << 31))
126 mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
127
128 return clk->parent->rate * mult;
129}
130
131static struct sh_clk_ops pllc2_clk_ops = {
132 .recalc = pllc2_recalc,
133};
134
135static struct clk pllc2_clk = {
136 .ops = &pllc2_clk_ops,
137 .flags = CLK_ENABLE_ON_INIT,
138 .parent = &extalb1_div2_clk,
139};
140
141static struct clk *main_clks[] = {
142 &r_clk,
143 &sh7367_extalb1_clk,
144 &sh7367_extal2_clk,
145 &extalb1_div2_clk,
146 &extal2_div2_clk,
147 &pllc1_clk,
148 &pllc1_div2_clk,
149 &pllc2_clk,
150};
151
152static void div4_kick(struct clk *clk)
153{
154 unsigned long value;
155
156 /* set KICK bit in SYFRQCR to update hardware setting */
157 value = __raw_readl(SYFRQCR);
158 value |= (1 << 31);
159 __raw_writel(value, SYFRQCR);
160}
161
162static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
163 24, 32, 36, 48, 0, 72, 0, 0 };
164
165static struct clk_div_mult_table div4_div_mult_table = {
166 .divisors = divisors,
167 .nr_divisors = ARRAY_SIZE(divisors),
168};
169
170static struct clk_div4_table div4_table = {
171 .div_mult_table = &div4_div_mult_table,
172 .kick = div4_kick,
173};
174
175enum { DIV4_I, DIV4_G, DIV4_S, DIV4_B,
176 DIV4_ZX, DIV4_ZT, DIV4_Z, DIV4_ZD, DIV4_HP,
177 DIV4_ZS, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_NR };
178
179#define DIV4(_reg, _bit, _mask, _flags) \
180 SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
181
182static struct clk div4_clks[DIV4_NR] = {
183 [DIV4_I] = DIV4(RTFRQCR, 20, 0x6fff, CLK_ENABLE_ON_INIT),
184 [DIV4_G] = DIV4(RTFRQCR, 16, 0x6fff, CLK_ENABLE_ON_INIT),
185 [DIV4_S] = DIV4(RTFRQCR, 12, 0x6fff, CLK_ENABLE_ON_INIT),
186 [DIV4_B] = DIV4(RTFRQCR, 8, 0x6fff, CLK_ENABLE_ON_INIT),
187 [DIV4_ZX] = DIV4(SYFRQCR, 20, 0x6fff, 0),
188 [DIV4_ZT] = DIV4(SYFRQCR, 16, 0x6fff, 0),
189 [DIV4_Z] = DIV4(SYFRQCR, 12, 0x6fff, 0),
190 [DIV4_ZD] = DIV4(SYFRQCR, 8, 0x6fff, 0),
191 [DIV4_HP] = DIV4(SYFRQCR, 4, 0x6fff, 0),
192 [DIV4_ZS] = DIV4(CMFRQCR, 12, 0x6fff, 0),
193 [DIV4_ZB] = DIV4(CMFRQCR, 8, 0x6fff, 0),
194 [DIV4_ZB3] = DIV4(CMFRQCR, 4, 0x6fff, 0),
195 [DIV4_CP] = DIV4(CMFRQCR, 0, 0x6fff, 0),
196};
197
198enum { DIV6_SUB, DIV6_SIUA, DIV6_SIUB, DIV6_MSU, DIV6_SPU,
199 DIV6_MVI3, DIV6_MF1, DIV6_MF2,
200 DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VOU,
201 DIV6_NR };
202
203static struct clk div6_clks[DIV6_NR] = {
204 [DIV6_SUB] = SH_CLK_DIV6(&sh7367_extal2_clk, SUBUSBCKCR, 0),
205 [DIV6_SIUA] = SH_CLK_DIV6(&pllc1_div2_clk, SCLKACR, 0),
206 [DIV6_SIUB] = SH_CLK_DIV6(&pllc1_div2_clk, SCLKBCR, 0),
207 [DIV6_MSU] = SH_CLK_DIV6(&pllc1_div2_clk, MSUCKCR, 0),
208 [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
209 [DIV6_MVI3] = SH_CLK_DIV6(&pllc1_div2_clk, MVI3CKCR, 0),
210 [DIV6_MF1] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK1CR, 0),
211 [DIV6_MF2] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK2CR, 0),
212 [DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
213 [DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
214 [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
215 [DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0),
216};
217
218enum { RTMSTP001,
219 RTMSTP231, RTMSTP230, RTMSTP229, RTMSTP228, RTMSTP226,
220 RTMSTP216, RTMSTP206, RTMSTP205, RTMSTP201,
221 SYMSTP023, SYMSTP007, SYMSTP006, SYMSTP004,
222 SYMSTP003, SYMSTP002, SYMSTP001, SYMSTP000,
223 SYMSTP231, SYMSTP229, SYMSTP225, SYMSTP223, SYMSTP222,
224 SYMSTP215, SYMSTP214, SYMSTP213, SYMSTP211,
225 CMMSTP003,
226 MSTP_NR };
227
228#define MSTP(_parent, _reg, _bit, _flags) \
229 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
230
231static struct clk mstp_clks[MSTP_NR] = {
232 [RTMSTP001] = MSTP(&div6_clks[DIV6_SUB], RTMSTPCR0, 1, 0), /* IIC2 */
233 [RTMSTP231] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 31, 0), /* VEU3 */
234 [RTMSTP230] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 30, 0), /* VEU2 */
235 [RTMSTP229] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 29, 0), /* VEU1 */
236 [RTMSTP228] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 28, 0), /* VEU0 */
237 [RTMSTP226] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 26, 0), /* VEU2H */
238 [RTMSTP216] = MSTP(&div6_clks[DIV6_SUB], RTMSTPCR2, 16, 0), /* IIC0 */
239 [RTMSTP206] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 6, 0), /* JPU */
240 [RTMSTP205] = MSTP(&div6_clks[DIV6_VOU], RTMSTPCR2, 5, 0), /* VOU */
241 [RTMSTP201] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 1, 0), /* VPU */
242 [SYMSTP023] = MSTP(&div6_clks[DIV6_SPU], SYMSTPCR0, 23, 0), /* SPU1 */
243 [SYMSTP007] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 7, 0), /* SCIFA5 */
244 [SYMSTP006] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 6, 0), /* SCIFB */
245 [SYMSTP004] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 4, 0), /* SCIFA0 */
246 [SYMSTP003] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 3, 0), /* SCIFA1 */
247 [SYMSTP002] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 2, 0), /* SCIFA2 */
248 [SYMSTP001] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 1, 0), /* SCIFA3 */
249 [SYMSTP000] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 0, 0), /* SCIFA4 */
250 [SYMSTP231] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 31, 0), /* SIU */
251 [SYMSTP229] = MSTP(&r_clk, SYMSTPCR2, 29, 0), /* CMT10 */
252 [SYMSTP225] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 25, 0), /* IRDA */
253 [SYMSTP223] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 23, 0), /* IIC1 */
254 [SYMSTP222] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 22, 0), /* USBHS */
255 [SYMSTP215] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 15, 0), /* FLCTL */
256 [SYMSTP214] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 14, 0), /* SDHI0 */
257 [SYMSTP213] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 13, 0), /* SDHI1 */
258 [SYMSTP211] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 11, 0), /* SDHI2 */
259 [CMMSTP003] = MSTP(&r_clk, CMMSTPCR0, 3, 0), /* KEYSC */
260};
261
262static struct clk_lookup lookups[] = {
263 /* main clocks */
264 CLKDEV_CON_ID("r_clk", &r_clk),
265 CLKDEV_CON_ID("extalb1", &sh7367_extalb1_clk),
266 CLKDEV_CON_ID("extal2", &sh7367_extal2_clk),
267 CLKDEV_CON_ID("extalb1_div2_clk", &extalb1_div2_clk),
268 CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
269 CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
270 CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
271 CLKDEV_CON_ID("pllc2_clk", &pllc2_clk),
272
273 /* DIV4 clocks */
274 CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
275 CLKDEV_CON_ID("g_clk", &div4_clks[DIV4_G]),
276 CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
277 CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]),
278 CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
279 CLKDEV_CON_ID("z_clk", &div4_clks[DIV4_Z]),
280 CLKDEV_CON_ID("zd_clk", &div4_clks[DIV4_ZD]),
281 CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
282 CLKDEV_CON_ID("zs_clk", &div4_clks[DIV4_ZS]),
283 CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
284 CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
285 CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
286
287 /* DIV6 clocks */
288 CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
289 CLKDEV_CON_ID("siua_clk", &div6_clks[DIV6_SIUA]),
290 CLKDEV_CON_ID("siub_clk", &div6_clks[DIV6_SIUB]),
291 CLKDEV_CON_ID("msu_clk", &div6_clks[DIV6_MSU]),
292 CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
293 CLKDEV_CON_ID("mvi3_clk", &div6_clks[DIV6_MVI3]),
294 CLKDEV_CON_ID("mf1_clk", &div6_clks[DIV6_MF1]),
295 CLKDEV_CON_ID("mf2_clk", &div6_clks[DIV6_MF2]),
296 CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
297 CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
298 CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
299 CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
300
301 /* MSTP32 clocks */
302 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[RTMSTP001]), /* IIC2 */
303 CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[RTMSTP231]), /* VEU3 */
304 CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[RTMSTP230]), /* VEU2 */
305 CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[RTMSTP229]), /* VEU1 */
306 CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[RTMSTP228]), /* VEU0 */
307 CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[RTMSTP226]), /* VEU2H */
308 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[RTMSTP216]), /* IIC0 */
309 CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[RTMSTP206]), /* JPU */
310 CLKDEV_DEV_ID("sh-vou", &mstp_clks[RTMSTP205]), /* VOU */
311 CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[RTMSTP201]), /* VPU */
312 CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[SYMSTP023]), /* SPU1 */
313 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[SYMSTP007]), /* SCIFA5 */
314 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[SYMSTP006]), /* SCIFB */
315 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[SYMSTP004]), /* SCIFA0 */
316 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[SYMSTP003]), /* SCIFA1 */
317 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[SYMSTP002]), /* SCIFA2 */
318 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[SYMSTP001]), /* SCIFA3 */
319 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[SYMSTP000]), /* SCIFA4 */
320 CLKDEV_DEV_ID("sh_siu", &mstp_clks[SYMSTP231]), /* SIU */
321 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[SYMSTP229]), /* CMT10 */
322 CLKDEV_DEV_ID("sh_irda", &mstp_clks[SYMSTP225]), /* IRDA */
323 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[SYMSTP223]), /* IIC1 */
324 CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[SYMSTP222]), /* USBHS */
325 CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[SYMSTP222]), /* USBHS */
326 CLKDEV_DEV_ID("sh_flctl", &mstp_clks[SYMSTP215]), /* FLCTL */
327 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[SYMSTP214]), /* SDHI0 */
328 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[SYMSTP213]), /* SDHI1 */
329 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[SYMSTP211]), /* SDHI2 */
330 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[CMMSTP003]), /* KEYSC */
331};
332
333void __init sh7367_clock_init(void)
334{
335 int k, ret = 0;
336
337 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
338 ret = clk_register(main_clks[k]);
339
340 if (!ret)
341 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
342
343 if (!ret)
344 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
345
346 if (!ret)
347 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
348
349 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
350
351 if (!ret)
352 shmobile_clk_init();
353 else
354 panic("failed to setup sh7367 clocks\n");
355}
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 430a90ffa120..4d57e342537b 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -420,87 +420,11 @@ static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
420}; 420};
421 421
422/* FSI DIV */ 422/* FSI DIV */
423static unsigned long fsidiv_recalc(struct clk *clk) 423enum { FSIDIV_A, FSIDIV_B, FSIDIV_REPARENT_NR };
424{
425 unsigned long value;
426
427 value = __raw_readl(clk->mapping->base);
428
429 value >>= 16;
430 if (value < 2)
431 return 0;
432
433 return clk->parent->rate / value;
434}
435
436static long fsidiv_round_rate(struct clk *clk, unsigned long rate)
437{
438 return clk_rate_div_range_round(clk, 2, 0xffff, rate);
439}
440
441static void fsidiv_disable(struct clk *clk)
442{
443 __raw_writel(0, clk->mapping->base);
444}
445
446static int fsidiv_enable(struct clk *clk)
447{
448 unsigned long value;
449
450 value = __raw_readl(clk->mapping->base) >> 16;
451 if (value < 2)
452 return -EIO;
453
454 __raw_writel((value << 16) | 0x3, clk->mapping->base);
455
456 return 0;
457}
458 424
459static int fsidiv_set_rate(struct clk *clk, unsigned long rate) 425static struct clk fsidivs[] = {
460{ 426 [FSIDIV_A] = SH_CLK_FSIDIV(FSIDIVA, &div6_reparent_clks[DIV6_FSIA]),
461 int idx; 427 [FSIDIV_B] = SH_CLK_FSIDIV(FSIDIVB, &div6_reparent_clks[DIV6_FSIB]),
462
463 idx = (clk->parent->rate / rate) & 0xffff;
464 if (idx < 2)
465 return -EINVAL;
466
467 __raw_writel(idx << 16, clk->mapping->base);
468 return 0;
469}
470
471static struct sh_clk_ops fsidiv_clk_ops = {
472 .recalc = fsidiv_recalc,
473 .round_rate = fsidiv_round_rate,
474 .set_rate = fsidiv_set_rate,
475 .enable = fsidiv_enable,
476 .disable = fsidiv_disable,
477};
478
479static struct clk_mapping fsidiva_clk_mapping = {
480 .phys = FSIDIVA,
481 .len = 8,
482};
483
484struct clk sh7372_fsidiva_clk = {
485 .ops = &fsidiv_clk_ops,
486 .parent = &div6_reparent_clks[DIV6_FSIA], /* late install */
487 .mapping = &fsidiva_clk_mapping,
488};
489
490static struct clk_mapping fsidivb_clk_mapping = {
491 .phys = FSIDIVB,
492 .len = 8,
493};
494
495struct clk sh7372_fsidivb_clk = {
496 .ops = &fsidiv_clk_ops,
497 .parent = &div6_reparent_clks[DIV6_FSIB], /* late install */
498 .mapping = &fsidivb_clk_mapping,
499};
500
501static struct clk *late_main_clks[] = {
502 &sh7372_fsidiva_clk,
503 &sh7372_fsidivb_clk,
504}; 428};
505 429
506enum { MSTP001, MSTP000, 430enum { MSTP001, MSTP000,
@@ -583,6 +507,8 @@ static struct clk_lookup lookups[] = {
583 CLKDEV_CON_ID("pllc1_clk", &pllc1_clk), 507 CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
584 CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk), 508 CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
585 CLKDEV_CON_ID("pllc2_clk", &sh7372_pllc2_clk), 509 CLKDEV_CON_ID("pllc2_clk", &sh7372_pllc2_clk),
510 CLKDEV_CON_ID("fsidiva", &fsidivs[FSIDIV_A]),
511 CLKDEV_CON_ID("fsidivb", &fsidivs[FSIDIV_B]),
586 512
587 /* DIV4 clocks */ 513 /* DIV4 clocks */
588 CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]), 514 CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
@@ -678,6 +604,10 @@ static struct clk_lookup lookups[] = {
678 CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]), 604 CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
679 CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]), 605 CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),
680 CLKDEV_ICK_ID("spu2", "sh_fsi2", &mstp_clks[MSTP223]), 606 CLKDEV_ICK_ID("spu2", "sh_fsi2", &mstp_clks[MSTP223]),
607 CLKDEV_ICK_ID("diva", "sh_fsi2", &fsidivs[FSIDIV_A]),
608 CLKDEV_ICK_ID("divb", "sh_fsi2", &fsidivs[FSIDIV_B]),
609 CLKDEV_ICK_ID("xcka", "sh_fsi2", &sh7372_fsiack_clk),
610 CLKDEV_ICK_ID("xckb", "sh_fsi2", &sh7372_fsibck_clk),
681}; 611};
682 612
683void __init sh7372_clock_init(void) 613void __init sh7372_clock_init(void)
@@ -706,8 +636,8 @@ void __init sh7372_clock_init(void)
706 if (!ret) 636 if (!ret)
707 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); 637 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
708 638
709 for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++) 639 if (!ret)
710 ret = clk_register(late_main_clks[k]); 640 ret = sh_clk_fsidiv_register(fsidivs, FSIDIV_REPARENT_NR);
711 641
712 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 642 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
713 643
diff --git a/arch/arm/mach-shmobile/clock-sh7377.c b/arch/arm/mach-shmobile/clock-sh7377.c
deleted file mode 100644
index b8480d19e1c8..000000000000
--- a/arch/arm/mach-shmobile/clock-sh7377.c
+++ /dev/null
@@ -1,366 +0,0 @@
1/*
2 * SH7377 clock framework support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#include <linux/init.h>
20#include <linux/kernel.h>
21#include <linux/io.h>
22#include <linux/sh_clk.h>
23#include <linux/clkdev.h>
24#include <mach/common.h>
25
26/* SH7377 registers */
27#define RTFRQCR IOMEM(0xe6150000)
28#define SYFRQCR IOMEM(0xe6150004)
29#define CMFRQCR IOMEM(0xe61500E0)
30#define VCLKCR1 IOMEM(0xe6150008)
31#define VCLKCR2 IOMEM(0xe615000C)
32#define VCLKCR3 IOMEM(0xe615001C)
33#define FMSICKCR IOMEM(0xe6150010)
34#define FMSOCKCR IOMEM(0xe6150014)
35#define FSICKCR IOMEM(0xe6150018)
36#define PLLC1CR IOMEM(0xe6150028)
37#define PLLC2CR IOMEM(0xe615002C)
38#define SUBUSBCKCR IOMEM(0xe6150080)
39#define SPUCKCR IOMEM(0xe6150084)
40#define MSUCKCR IOMEM(0xe6150088)
41#define MVI3CKCR IOMEM(0xe6150090)
42#define HDMICKCR IOMEM(0xe6150094)
43#define MFCK1CR IOMEM(0xe6150098)
44#define MFCK2CR IOMEM(0xe615009C)
45#define DSITCKCR IOMEM(0xe6150060)
46#define DSIPCKCR IOMEM(0xe6150064)
47#define SMSTPCR0 IOMEM(0xe6150130)
48#define SMSTPCR1 IOMEM(0xe6150134)
49#define SMSTPCR2 IOMEM(0xe6150138)
50#define SMSTPCR3 IOMEM(0xe615013C)
51#define SMSTPCR4 IOMEM(0xe6150140)
52
53/* Fixed 32 KHz root clock from EXTALR pin */
54static struct clk r_clk = {
55 .rate = 32768,
56};
57
58/*
59 * 26MHz default rate for the EXTALC1 root input clock.
60 * If needed, reset this with clk_set_rate() from the platform code.
61 */
62struct clk sh7377_extalc1_clk = {
63 .rate = 26666666,
64};
65
66/*
67 * 48MHz default rate for the EXTAL2 root input clock.
68 * If needed, reset this with clk_set_rate() from the platform code.
69 */
70struct clk sh7377_extal2_clk = {
71 .rate = 48000000,
72};
73
74/* A fixed divide-by-2 block */
75static unsigned long div2_recalc(struct clk *clk)
76{
77 return clk->parent->rate / 2;
78}
79
80static struct sh_clk_ops div2_clk_ops = {
81 .recalc = div2_recalc,
82};
83
84/* Divide extalc1 by two */
85static struct clk extalc1_div2_clk = {
86 .ops = &div2_clk_ops,
87 .parent = &sh7377_extalc1_clk,
88};
89
90/* Divide extal2 by two */
91static struct clk extal2_div2_clk = {
92 .ops = &div2_clk_ops,
93 .parent = &sh7377_extal2_clk,
94};
95
96/* Divide extal2 by four */
97static struct clk extal2_div4_clk = {
98 .ops = &div2_clk_ops,
99 .parent = &extal2_div2_clk,
100};
101
102/* PLLC1 */
103static unsigned long pllc1_recalc(struct clk *clk)
104{
105 unsigned long mult = 1;
106
107 if (__raw_readl(PLLC1CR) & (1 << 14))
108 mult = (((__raw_readl(RTFRQCR) >> 24) & 0x3f) + 1) * 2;
109
110 return clk->parent->rate * mult;
111}
112
113static struct sh_clk_ops pllc1_clk_ops = {
114 .recalc = pllc1_recalc,
115};
116
117static struct clk pllc1_clk = {
118 .ops = &pllc1_clk_ops,
119 .flags = CLK_ENABLE_ON_INIT,
120 .parent = &extalc1_div2_clk,
121};
122
123/* Divide PLLC1 by two */
124static struct clk pllc1_div2_clk = {
125 .ops = &div2_clk_ops,
126 .parent = &pllc1_clk,
127};
128
129/* PLLC2 */
130static unsigned long pllc2_recalc(struct clk *clk)
131{
132 unsigned long mult = 1;
133
134 if (__raw_readl(PLLC2CR) & (1 << 31))
135 mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
136
137 return clk->parent->rate * mult;
138}
139
140static struct sh_clk_ops pllc2_clk_ops = {
141 .recalc = pllc2_recalc,
142};
143
144static struct clk pllc2_clk = {
145 .ops = &pllc2_clk_ops,
146 .flags = CLK_ENABLE_ON_INIT,
147 .parent = &extalc1_div2_clk,
148};
149
150static struct clk *main_clks[] = {
151 &r_clk,
152 &sh7377_extalc1_clk,
153 &sh7377_extal2_clk,
154 &extalc1_div2_clk,
155 &extal2_div2_clk,
156 &extal2_div4_clk,
157 &pllc1_clk,
158 &pllc1_div2_clk,
159 &pllc2_clk,
160};
161
162static void div4_kick(struct clk *clk)
163{
164 unsigned long value;
165
166 /* set KICK bit in SYFRQCR to update hardware setting */
167 value = __raw_readl(SYFRQCR);
168 value |= (1 << 31);
169 __raw_writel(value, SYFRQCR);
170}
171
172static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
173 24, 32, 36, 48, 0, 72, 96, 0 };
174
175static struct clk_div_mult_table div4_div_mult_table = {
176 .divisors = divisors,
177 .nr_divisors = ARRAY_SIZE(divisors),
178};
179
180static struct clk_div4_table div4_table = {
181 .div_mult_table = &div4_div_mult_table,
182 .kick = div4_kick,
183};
184
185enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR,
186 DIV4_ZTR, DIV4_ZT, DIV4_Z, DIV4_HP,
187 DIV4_ZS, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_NR };
188
189#define DIV4(_reg, _bit, _mask, _flags) \
190 SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
191
192static struct clk div4_clks[DIV4_NR] = {
193 [DIV4_I] = DIV4(RTFRQCR, 20, 0x6fff, CLK_ENABLE_ON_INIT),
194 [DIV4_ZG] = DIV4(RTFRQCR, 16, 0x6fff, CLK_ENABLE_ON_INIT),
195 [DIV4_B] = DIV4(RTFRQCR, 8, 0x6fff, CLK_ENABLE_ON_INIT),
196 [DIV4_M1] = DIV4(RTFRQCR, 4, 0x6fff, CLK_ENABLE_ON_INIT),
197 [DIV4_CSIR] = DIV4(RTFRQCR, 0, 0x6fff, 0),
198 [DIV4_ZTR] = DIV4(SYFRQCR, 20, 0x6fff, 0),
199 [DIV4_ZT] = DIV4(SYFRQCR, 16, 0x6fff, 0),
200 [DIV4_Z] = DIV4(SYFRQCR, 12, 0x6fff, 0),
201 [DIV4_HP] = DIV4(SYFRQCR, 4, 0x6fff, 0),
202 [DIV4_ZS] = DIV4(CMFRQCR, 12, 0x6fff, 0),
203 [DIV4_ZB] = DIV4(CMFRQCR, 8, 0x6fff, 0),
204 [DIV4_ZB3] = DIV4(CMFRQCR, 4, 0x6fff, 0),
205 [DIV4_CP] = DIV4(CMFRQCR, 0, 0x6fff, 0),
206};
207
208enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO,
209 DIV6_FSI, DIV6_SUB, DIV6_SPU, DIV6_MSU, DIV6_MVI3, DIV6_HDMI,
210 DIV6_MF1, DIV6_MF2, DIV6_DSIT, DIV6_DSIP,
211 DIV6_NR };
212
213static struct clk div6_clks[] = {
214 [DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
215 [DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
216 [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
217 [DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0),
218 [DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0),
219 [DIV6_FSI] = SH_CLK_DIV6(&pllc1_div2_clk, FSICKCR, 0),
220 [DIV6_SUB] = SH_CLK_DIV6(&sh7377_extal2_clk, SUBUSBCKCR, 0),
221 [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
222 [DIV6_MSU] = SH_CLK_DIV6(&pllc1_div2_clk, MSUCKCR, 0),
223 [DIV6_MVI3] = SH_CLK_DIV6(&pllc1_div2_clk, MVI3CKCR, 0),
224 [DIV6_HDMI] = SH_CLK_DIV6(&pllc1_div2_clk, HDMICKCR, 0),
225 [DIV6_MF1] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK1CR, 0),
226 [DIV6_MF2] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK2CR, 0),
227 [DIV6_DSIT] = SH_CLK_DIV6(&pllc1_div2_clk, DSITCKCR, 0),
228 [DIV6_DSIP] = SH_CLK_DIV6(&pllc1_div2_clk, DSIPCKCR, 0),
229};
230
231enum { MSTP001,
232 MSTP131, MSTP130, MSTP129, MSTP128, MSTP116, MSTP106, MSTP101,
233 MSTP223, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
234 MSTP331, MSTP329, MSTP325, MSTP323, MSTP322,
235 MSTP315, MSTP314, MSTP313,
236 MSTP403,
237 MSTP_NR };
238
239#define MSTP(_parent, _reg, _bit, _flags) \
240 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
241
242static struct clk mstp_clks[] = {
243 [MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */
244 [MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */
245 [MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
246 [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
247 [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */
248 [MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
249 [MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */
250 [MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */
251 [MSTP223] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR2, 23, 0), /* SPU2 */
252 [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
253 [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
254 [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
255 [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
256 [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
257 [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
258 [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
259 [MSTP331] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 31, 0), /* SCIFA6 */
260 [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
261 [MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IRDA */
262 [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
263 [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
264 [MSTP315] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 15, 0), /* FLCTL */
265 [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
266 [MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
267 [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
268};
269
270static struct clk_lookup lookups[] = {
271 /* main clocks */
272 CLKDEV_CON_ID("r_clk", &r_clk),
273 CLKDEV_CON_ID("extalc1", &sh7377_extalc1_clk),
274 CLKDEV_CON_ID("extal2", &sh7377_extal2_clk),
275 CLKDEV_CON_ID("extalc1_div2_clk", &extalc1_div2_clk),
276 CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
277 CLKDEV_CON_ID("extal2_div4_clk", &extal2_div4_clk),
278 CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
279 CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
280 CLKDEV_CON_ID("pllc2_clk", &pllc2_clk),
281
282 /* DIV4 clocks */
283 CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
284 CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
285 CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
286 CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
287 CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]),
288 CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]),
289 CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
290 CLKDEV_CON_ID("z_clk", &div4_clks[DIV4_Z]),
291 CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
292 CLKDEV_CON_ID("zs_clk", &div4_clks[DIV4_ZS]),
293 CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
294 CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
295 CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
296
297 /* DIV6 clocks */
298 CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
299 CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
300 CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
301 CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]),
302 CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]),
303 CLKDEV_CON_ID("fsi_clk", &div6_clks[DIV6_FSI]),
304 CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
305 CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
306 CLKDEV_CON_ID("msu_clk", &div6_clks[DIV6_MSU]),
307 CLKDEV_CON_ID("mvi3_clk", &div6_clks[DIV6_MVI3]),
308 CLKDEV_CON_ID("hdmi_clk", &div6_clks[DIV6_HDMI]),
309 CLKDEV_CON_ID("mf1_clk", &div6_clks[DIV6_MF1]),
310 CLKDEV_CON_ID("mf2_clk", &div6_clks[DIV6_MF2]),
311 CLKDEV_CON_ID("dsit_clk", &div6_clks[DIV6_DSIT]),
312 CLKDEV_CON_ID("dsip_clk", &div6_clks[DIV6_DSIP]),
313
314 /* MSTP32 clocks */
315 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
316 CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
317 CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
318 CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
319 CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
320 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
321 CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
322 CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */
323 CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[MSTP223]), /* SPU2DSP0 */
324 CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[MSTP223]), /* SPU2DSP1 */
325 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
326 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP206]), /* SCIFB */
327 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
328 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
329 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
330 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
331 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
332 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
333 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
334 CLKDEV_DEV_ID("sh_irda", &mstp_clks[MSTP325]), /* IRDA */
335 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
336 CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USBHS */
337 CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP322]), /* USBHS */
338 CLKDEV_DEV_ID("sh_flctl", &mstp_clks[MSTP315]), /* FLCTL */
339 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
340 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
341 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
342};
343
344void __init sh7377_clock_init(void)
345{
346 int k, ret = 0;
347
348 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
349 ret = clk_register(main_clks[k]);
350
351 if (!ret)
352 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
353
354 if (!ret)
355 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
356
357 if (!ret)
358 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
359
360 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
361
362 if (!ret)
363 shmobile_clk_init();
364 else
365 panic("failed to setup sh7377 clocks\n");
366}
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index d47e215aca87..dfeca79e9e96 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -18,24 +18,6 @@ extern int shmobile_enter_wfi(struct cpuidle_device *dev,
18 struct cpuidle_driver *drv, int index); 18 struct cpuidle_driver *drv, int index);
19extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv); 19extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv);
20 20
21extern void sh7367_init_irq(void);
22extern void sh7367_map_io(void);
23extern void sh7367_add_early_devices(void);
24extern void sh7367_add_standard_devices(void);
25extern void sh7367_clock_init(void);
26extern void sh7367_pinmux_init(void);
27extern struct clk sh7367_extalb1_clk;
28extern struct clk sh7367_extal2_clk;
29
30extern void sh7377_init_irq(void);
31extern void sh7377_map_io(void);
32extern void sh7377_add_early_devices(void);
33extern void sh7377_add_standard_devices(void);
34extern void sh7377_clock_init(void);
35extern void sh7377_pinmux_init(void);
36extern struct clk sh7377_extalc1_clk;
37extern struct clk sh7377_extal2_clk;
38
39extern void sh7372_init_irq(void); 21extern void sh7372_init_irq(void);
40extern void sh7372_map_io(void); 22extern void sh7372_map_io(void);
41extern void sh7372_add_early_devices(void); 23extern void sh7372_add_early_devices(void);
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index 499f52d2a4a1..8ab0cd6ad6b0 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -71,7 +71,7 @@ enum {
71 GPIO_FN_A19, 71 GPIO_FN_A19,
72 72
73 /* IPSR0 */ 73 /* IPSR0 */
74 GPIO_FN_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0, 74 GPIO_FN_USB_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
75 GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS, GPIO_FN_SD1_DAT2, 75 GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS, GPIO_FN_SD1_DAT2,
76 GPIO_FN_MMC0_D2, GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF, 76 GPIO_FN_MMC0_D2, GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
77 GPIO_FN_HCTS1, GPIO_FN_TX4_C, GPIO_FN_A0, GPIO_FN_SD1_DAT3, 77 GPIO_FN_HCTS1, GPIO_FN_TX4_C, GPIO_FN_A0, GPIO_FN_SD1_DAT3,
diff --git a/arch/arm/mach-shmobile/include/mach/sh7367.h b/arch/arm/mach-shmobile/include/mach/sh7367.h
deleted file mode 100644
index 52d0de686f68..000000000000
--- a/arch/arm/mach-shmobile/include/mach/sh7367.h
+++ /dev/null
@@ -1,332 +0,0 @@
1#ifndef __ASM_SH7367_H__
2#define __ASM_SH7367_H__
3
4/* Pin Function Controller:
5 * GPIO_FN_xx - GPIO used to select pin function
6 * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
7 */
8enum {
9 /* 49-1 -> 49-6 (GPIO) */
10 GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
11 GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
12
13 GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
14 GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
15
16 GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
17 GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
18
19 GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
20 GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
21
22 GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
23 GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
24
25 GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
26 GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
27
28 GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
29 GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
30
31 GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
32 GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
33
34 GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
35 GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
36
37 GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
38 GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
39
40 GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
41 GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
42
43 GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
44 GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
45
46 GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
47 GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
48
49 GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
50 GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
51
52 GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
53 GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
54
55 GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
56 GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
57
58 GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
59 GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
60
61 GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
62 GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
63
64 GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
65 GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
66
67 GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
68 GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
69
70 GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
71 GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
72
73 GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214,
74 GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219,
75
76 GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224,
77 GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229,
78
79 GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234,
80 GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239,
81
82 GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244,
83 GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249,
84
85 GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254,
86 GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259,
87
88 GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264,
89 GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269,
90
91 GPIO_PORT270, GPIO_PORT271, GPIO_PORT272,
92
93 /* Special Pull-up / Pull-down Functions */
94 GPIO_FN_PORT48_KEYIN0_PU, GPIO_FN_PORT49_KEYIN1_PU,
95 GPIO_FN_PORT50_KEYIN2_PU, GPIO_FN_PORT55_KEYIN3_PU,
96 GPIO_FN_PORT56_KEYIN4_PU, GPIO_FN_PORT57_KEYIN5_PU,
97 GPIO_FN_PORT58_KEYIN6_PU,
98
99 /* 49-1 (FN) */
100 GPIO_FN_VBUS0, GPIO_FN_CPORT0, GPIO_FN_CPORT1, GPIO_FN_CPORT2,
101 GPIO_FN_CPORT3, GPIO_FN_CPORT4, GPIO_FN_CPORT5, GPIO_FN_CPORT6,
102 GPIO_FN_CPORT7, GPIO_FN_CPORT8, GPIO_FN_CPORT9, GPIO_FN_CPORT10,
103 GPIO_FN_CPORT11, GPIO_FN_SIN2, GPIO_FN_CPORT12, GPIO_FN_XCTS2,
104 GPIO_FN_CPORT13, GPIO_FN_RFSPO4, GPIO_FN_CPORT14, GPIO_FN_RFSPO5,
105 GPIO_FN_CPORT15, GPIO_FN_CPORT16, GPIO_FN_CPORT17, GPIO_FN_SOUT2,
106 GPIO_FN_CPORT18, GPIO_FN_XRTS2, GPIO_FN_CPORT19, GPIO_FN_CPORT20,
107 GPIO_FN_RFSPO6, GPIO_FN_CPORT21, GPIO_FN_STATUS0, GPIO_FN_CPORT22,
108 GPIO_FN_STATUS1, GPIO_FN_CPORT23, GPIO_FN_STATUS2, GPIO_FN_RFSPO7,
109 GPIO_FN_MPORT0, GPIO_FN_MPORT1, GPIO_FN_B_SYNLD1, GPIO_FN_B_SYNLD2,
110 GPIO_FN_XMAINPS, GPIO_FN_XDIVPS, GPIO_FN_XIDRST, GPIO_FN_IDCLK,
111 GPIO_FN_IDIO, GPIO_FN_SOUT1, GPIO_FN_SCIFA4_TXD,
112 GPIO_FN_M02_BERDAT, GPIO_FN_SIN1, GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
113 GPIO_FN_XRTS1, GPIO_FN_SCIFA4_RTS, GPIO_FN_M03_BERCLK,
114 GPIO_FN_XCTS1, GPIO_FN_SCIFA4_CTS,
115
116 /* 49-2 (FN) */
117 GPIO_FN_HSU_IQ_AGC6, GPIO_FN_MFG2_IN2, GPIO_FN_MSIOF2_MCK0,
118 GPIO_FN_HSU_IQ_AGC5, GPIO_FN_MFG2_IN1, GPIO_FN_MSIOF2_MCK1,
119 GPIO_FN_HSU_IQ_AGC4, GPIO_FN_MSIOF2_RSYNC,
120 GPIO_FN_HSU_IQ_AGC3, GPIO_FN_MFG2_OUT1, GPIO_FN_MSIOF2_RSCK,
121 GPIO_FN_HSU_IQ_AGC2, GPIO_FN_PORT42_KEYOUT0,
122 GPIO_FN_HSU_IQ_AGC1, GPIO_FN_PORT43_KEYOUT1,
123 GPIO_FN_HSU_IQ_AGC0, GPIO_FN_PORT44_KEYOUT2,
124 GPIO_FN_HSU_IQ_AGC_ST, GPIO_FN_PORT45_KEYOUT3,
125 GPIO_FN_HSU_IQ_PDO, GPIO_FN_PORT46_KEYOUT4,
126 GPIO_FN_HSU_IQ_PYO, GPIO_FN_PORT47_KEYOUT5,
127 GPIO_FN_HSU_EN_TXMUX_G3MO, GPIO_FN_PORT48_KEYIN0,
128 GPIO_FN_HSU_I_TXMUX_G3MO, GPIO_FN_PORT49_KEYIN1,
129 GPIO_FN_HSU_Q_TXMUX_G3MO, GPIO_FN_PORT50_KEYIN2,
130 GPIO_FN_HSU_SYO, GPIO_FN_PORT51_MSIOF2_TSYNC,
131 GPIO_FN_HSU_SDO, GPIO_FN_PORT52_MSIOF2_TSCK,
132 GPIO_FN_HSU_TGTTI_G3MO, GPIO_FN_PORT53_MSIOF2_TXD,
133 GPIO_FN_B_TIME_STAMP, GPIO_FN_PORT54_MSIOF2_RXD,
134 GPIO_FN_HSU_SDI, GPIO_FN_PORT55_KEYIN3,
135 GPIO_FN_HSU_SCO, GPIO_FN_PORT56_KEYIN4,
136 GPIO_FN_HSU_DREQ, GPIO_FN_PORT57_KEYIN5,
137 GPIO_FN_HSU_DACK, GPIO_FN_PORT58_KEYIN6,
138 GPIO_FN_HSU_CLK61M, GPIO_FN_PORT59_MSIOF2_SS1,
139 GPIO_FN_HSU_XRST, GPIO_FN_PORT60_MSIOF2_SS2,
140 GPIO_FN_PCMCLKO, GPIO_FN_SYNC8KO, GPIO_FN_DNPCM_A, GPIO_FN_UPPCM_A,
141 GPIO_FN_XTALB1L,
142 GPIO_FN_GPS_AGC1, GPIO_FN_SCIFA0_RTS,
143 GPIO_FN_GPS_AGC2, GPIO_FN_SCIFA0_SCK,
144 GPIO_FN_GPS_AGC3, GPIO_FN_SCIFA0_TXD,
145 GPIO_FN_GPS_AGC4, GPIO_FN_SCIFA0_RXD,
146 GPIO_FN_GPS_PWRD, GPIO_FN_SCIFA0_CTS,
147 GPIO_FN_GPS_IM, GPIO_FN_GPS_IS, GPIO_FN_GPS_QM, GPIO_FN_GPS_QS,
148 GPIO_FN_SIUBOMC, GPIO_FN_TPU2TO0,
149 GPIO_FN_SIUCKB, GPIO_FN_TPU2TO1,
150 GPIO_FN_SIUBOLR, GPIO_FN_BBIF2_TSYNC, GPIO_FN_TPU2TO2,
151 GPIO_FN_SIUBOBT, GPIO_FN_BBIF2_TSCK, GPIO_FN_TPU2TO3,
152 GPIO_FN_SIUBOSLD, GPIO_FN_BBIF2_TXD, GPIO_FN_TPU3TO0,
153 GPIO_FN_SIUBILR, GPIO_FN_TPU3TO1,
154 GPIO_FN_SIUBIBT, GPIO_FN_TPU3TO2,
155 GPIO_FN_SIUBISLD, GPIO_FN_TPU3TO3,
156 GPIO_FN_NMI, GPIO_FN_TPU4TO0,
157 GPIO_FN_DNPCM_M, GPIO_FN_TPU4TO1, GPIO_FN_TPU4TO2, GPIO_FN_TPU4TO3,
158 GPIO_FN_IRQ_TMPB,
159 GPIO_FN_PWEN, GPIO_FN_MFG1_OUT1,
160 GPIO_FN_OVCN, GPIO_FN_MFG1_IN1,
161 GPIO_FN_OVCN2, GPIO_FN_MFG1_IN2,
162
163 /* 49-3 (FN) */
164 GPIO_FN_RFSPO1, GPIO_FN_RFSPO2, GPIO_FN_RFSPO3, GPIO_FN_PORT93_VIO_CKO2,
165 GPIO_FN_USBTERM, GPIO_FN_EXTLP, GPIO_FN_IDIN,
166 GPIO_FN_SCIFA5_CTS, GPIO_FN_MFG0_IN1,
167 GPIO_FN_SCIFA5_RTS, GPIO_FN_MFG0_IN2,
168 GPIO_FN_SCIFA5_RXD,
169 GPIO_FN_SCIFA5_TXD,
170 GPIO_FN_SCIFA5_SCK, GPIO_FN_MFG0_OUT1,
171 GPIO_FN_A0_EA0, GPIO_FN_BS,
172 GPIO_FN_A14_EA14, GPIO_FN_PORT102_KEYOUT0,
173 GPIO_FN_A15_EA15, GPIO_FN_PORT103_KEYOUT1, GPIO_FN_DV_CLKOL,
174 GPIO_FN_A16_EA16, GPIO_FN_PORT104_KEYOUT2,
175 GPIO_FN_DV_VSYNCL, GPIO_FN_MSIOF0_SS1,
176 GPIO_FN_A17_EA17, GPIO_FN_PORT105_KEYOUT3,
177 GPIO_FN_DV_HSYNCL, GPIO_FN_MSIOF0_TSYNC,
178 GPIO_FN_A18_EA18, GPIO_FN_PORT106_KEYOUT4,
179 GPIO_FN_DV_DL0, GPIO_FN_MSIOF0_TSCK,
180 GPIO_FN_A19_EA19, GPIO_FN_PORT107_KEYOUT5,
181 GPIO_FN_DV_DL1, GPIO_FN_MSIOF0_TXD,
182 GPIO_FN_A20_EA20, GPIO_FN_PORT108_KEYIN0,
183 GPIO_FN_DV_DL2, GPIO_FN_MSIOF0_RSCK,
184 GPIO_FN_A21_EA21, GPIO_FN_PORT109_KEYIN1,
185 GPIO_FN_DV_DL3, GPIO_FN_MSIOF0_RSYNC,
186 GPIO_FN_A22_EA22, GPIO_FN_PORT110_KEYIN2,
187 GPIO_FN_DV_DL4, GPIO_FN_MSIOF0_MCK0,
188 GPIO_FN_A23_EA23, GPIO_FN_PORT111_KEYIN3,
189 GPIO_FN_DV_DL5, GPIO_FN_MSIOF0_MCK1,
190 GPIO_FN_A24_EA24, GPIO_FN_PORT112_KEYIN4,
191 GPIO_FN_DV_DL6, GPIO_FN_MSIOF0_RXD,
192 GPIO_FN_A25_EA25, GPIO_FN_PORT113_KEYIN5,
193 GPIO_FN_DV_DL7, GPIO_FN_MSIOF0_SS2,
194 GPIO_FN_A26, GPIO_FN_PORT113_KEYIN6, GPIO_FN_DV_CLKIL,
195 GPIO_FN_D0_ED0_NAF0, GPIO_FN_D1_ED1_NAF1, GPIO_FN_D2_ED2_NAF2,
196 GPIO_FN_D3_ED3_NAF3, GPIO_FN_D4_ED4_NAF4, GPIO_FN_D5_ED5_NAF5,
197 GPIO_FN_D6_ED6_NAF6, GPIO_FN_D7_ED7_NAF7, GPIO_FN_D8_ED8_NAF8,
198 GPIO_FN_D9_ED9_NAF9, GPIO_FN_D10_ED10_NAF10, GPIO_FN_D11_ED11_NAF11,
199 GPIO_FN_D12_ED12_NAF12, GPIO_FN_D13_ED13_NAF13,
200 GPIO_FN_D14_ED14_NAF14, GPIO_FN_D15_ED15_NAF15,
201 GPIO_FN_CS4, GPIO_FN_CS5A, GPIO_FN_CS5B, GPIO_FN_FCE1,
202 GPIO_FN_CS6B, GPIO_FN_XCS2, GPIO_FN_FCE0, GPIO_FN_CS6A,
203 GPIO_FN_DACK0, GPIO_FN_WAIT, GPIO_FN_DREQ0, GPIO_FN_RD_XRD,
204 GPIO_FN_A27, GPIO_FN_RDWR_XWE, GPIO_FN_WE0_XWR0_FWE,
205 GPIO_FN_WE1_XWR1, GPIO_FN_FRB, GPIO_FN_CKO,
206 GPIO_FN_NBRSTOUT, GPIO_FN_NBRST,
207
208 /* 49-4 (FN) */
209 GPIO_FN_RFSPO0, GPIO_FN_PORT146_VIO_CKO2, GPIO_FN_TSTMD,
210 GPIO_FN_VIO_VD, GPIO_FN_VIO_HD,
211 GPIO_FN_VIO_D0, GPIO_FN_VIO_D1, GPIO_FN_VIO_D2,
212 GPIO_FN_VIO_D3, GPIO_FN_VIO_D4, GPIO_FN_VIO_D5,
213 GPIO_FN_VIO_D6, GPIO_FN_VIO_D7, GPIO_FN_VIO_D8,
214 GPIO_FN_VIO_D9, GPIO_FN_VIO_D10, GPIO_FN_VIO_D11,
215 GPIO_FN_VIO_D12, GPIO_FN_VIO_D13, GPIO_FN_VIO_D14,
216 GPIO_FN_VIO_D15, GPIO_FN_VIO_CLK, GPIO_FN_VIO_FIELD,
217 GPIO_FN_VIO_CKO,
218 GPIO_FN_MFG3_IN1, GPIO_FN_MFG3_IN2,
219 GPIO_FN_M9_SLCD_A01, GPIO_FN_MFG3_OUT1, GPIO_FN_TPU0TO0,
220 GPIO_FN_M10_SLCD_CK1, GPIO_FN_MFG4_IN1, GPIO_FN_TPU0TO1,
221 GPIO_FN_M11_SLCD_SO1, GPIO_FN_MFG4_IN2, GPIO_FN_TPU0TO2,
222 GPIO_FN_M12_SLCD_CE1, GPIO_FN_MFG4_OUT1, GPIO_FN_TPU0TO3,
223 GPIO_FN_LCDD0, GPIO_FN_PORT175_KEYOUT0, GPIO_FN_DV_D0,
224 GPIO_FN_SIUCKA, GPIO_FN_MFG0_OUT2,
225 GPIO_FN_LCDD1, GPIO_FN_PORT176_KEYOUT1, GPIO_FN_DV_D1,
226 GPIO_FN_SIUAOLR, GPIO_FN_BBIF2_TSYNC1,
227 GPIO_FN_LCDD2, GPIO_FN_PORT177_KEYOUT2, GPIO_FN_DV_D2,
228 GPIO_FN_SIUAOBT, GPIO_FN_BBIF2_TSCK1,
229 GPIO_FN_LCDD3, GPIO_FN_PORT178_KEYOUT3, GPIO_FN_DV_D3,
230 GPIO_FN_SIUAOSLD, GPIO_FN_BBIF2_TXD1,
231 GPIO_FN_LCDD4, GPIO_FN_PORT179_KEYOUT4, GPIO_FN_DV_D4,
232 GPIO_FN_SIUAISPD, GPIO_FN_MFG1_OUT2,
233 GPIO_FN_LCDD5, GPIO_FN_PORT180_KEYOUT5, GPIO_FN_DV_D5,
234 GPIO_FN_SIUAILR, GPIO_FN_MFG2_OUT2,
235 GPIO_FN_LCDD6, GPIO_FN_DV_D6,
236 GPIO_FN_SIUAIBT, GPIO_FN_MFG3_OUT2, GPIO_FN_XWR2,
237 GPIO_FN_LCDD7, GPIO_FN_DV_D7,
238 GPIO_FN_SIUAISLD, GPIO_FN_MFG4_OUT2, GPIO_FN_XWR3,
239 GPIO_FN_LCDD8, GPIO_FN_DV_D8, GPIO_FN_D16, GPIO_FN_ED16,
240 GPIO_FN_LCDD9, GPIO_FN_DV_D9, GPIO_FN_D17, GPIO_FN_ED17,
241 GPIO_FN_LCDD10, GPIO_FN_DV_D10, GPIO_FN_D18, GPIO_FN_ED18,
242 GPIO_FN_LCDD11, GPIO_FN_DV_D11, GPIO_FN_D19, GPIO_FN_ED19,
243 GPIO_FN_LCDD12, GPIO_FN_DV_D12, GPIO_FN_D20, GPIO_FN_ED20,
244 GPIO_FN_LCDD13, GPIO_FN_DV_D13, GPIO_FN_D21, GPIO_FN_ED21,
245 GPIO_FN_LCDD14, GPIO_FN_DV_D14, GPIO_FN_D22, GPIO_FN_ED22,
246 GPIO_FN_LCDD15, GPIO_FN_DV_D15, GPIO_FN_D23, GPIO_FN_ED23,
247 GPIO_FN_LCDD16, GPIO_FN_DV_HSYNC, GPIO_FN_D24, GPIO_FN_ED24,
248 GPIO_FN_LCDD17, GPIO_FN_DV_VSYNC, GPIO_FN_D25, GPIO_FN_ED25,
249 GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_MSIOF0L_TSCK,
250 GPIO_FN_D26, GPIO_FN_ED26,
251 GPIO_FN_LCDD19, GPIO_FN_MSIOF0L_TSYNC,
252 GPIO_FN_D27, GPIO_FN_ED27,
253 GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0,
254 GPIO_FN_D28, GPIO_FN_ED28,
255 GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1,
256 GPIO_FN_D29, GPIO_FN_ED29,
257 GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_SS1,
258 GPIO_FN_D30, GPIO_FN_ED30,
259 GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_SS2,
260 GPIO_FN_D31, GPIO_FN_ED31,
261 GPIO_FN_LCDDCK, GPIO_FN_LCDWR, GPIO_FN_DV_CKO, GPIO_FN_SIUAOSPD,
262 GPIO_FN_LCDRD, GPIO_FN_DACK2, GPIO_FN_MSIOF0L_RSYNC,
263
264
265 /* 49-5 (FN) */
266 GPIO_FN_LCDHSYN, GPIO_FN_LCDCS, GPIO_FN_LCDCS2, GPIO_FN_DACK3,
267 GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_RSCK,
268 GPIO_FN_LCDCSYN, GPIO_FN_LCDCSYN2, GPIO_FN_DV_CKI,
269 GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_MSIOF0L_RXD,
270 GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_MSIOF0L_TXD,
271 GPIO_FN_VIO_DR0, GPIO_FN_VIO_DR1, GPIO_FN_VIO_DR2, GPIO_FN_VIO_DR3,
272 GPIO_FN_VIO_DR4, GPIO_FN_VIO_DR5, GPIO_FN_VIO_DR6, GPIO_FN_VIO_DR7,
273 GPIO_FN_VIO_VDR, GPIO_FN_VIO_HDR,
274 GPIO_FN_VIO_CLKR, GPIO_FN_VIO_CKOR,
275 GPIO_FN_SCIFA1_TXD, GPIO_FN_GPS_PGFA0,
276 GPIO_FN_SCIFA1_SCK, GPIO_FN_GPS_PGFA1,
277 GPIO_FN_SCIFA1_RTS, GPIO_FN_GPS_EPPSINMON,
278 GPIO_FN_SCIFA1_RXD, GPIO_FN_SCIFA1_CTS,
279 GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA1_TXD2, GPIO_FN_GPS_TXD,
280 GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA1_CTS2, GPIO_FN_I2C_SDA2,
281 GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA1_SCK2,
282 GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA1_RXD2, GPIO_FN_GPS_RXD,
283 GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA1_RTS2,
284 GPIO_FN_MSIOF1_RSYNC, GPIO_FN_I2C_SCL2,
285 GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1,
286 GPIO_FN_MSIOF1_SS1, GPIO_FN_EDBGREQ3,
287 GPIO_FN_MSIOF1_SS2,
288 GPIO_FN_PORT236_IROUT, GPIO_FN_IRDA_OUT,
289 GPIO_FN_IRDA_IN, GPIO_FN_IRDA_FIRSEL,
290 GPIO_FN_TPU1TO0, GPIO_FN_TS_SPSYNC3,
291 GPIO_FN_TPU1TO1, GPIO_FN_TS_SDAT3,
292 GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT241_MSIOF2_SS1,
293 GPIO_FN_TPU1TO3, GPIO_FN_PORT242_MSIOF2_TSCK,
294 GPIO_FN_M13_BSW, GPIO_FN_PORT243_MSIOF2_TSYNC,
295 GPIO_FN_M14_GSW, GPIO_FN_PORT244_MSIOF2_TXD,
296 GPIO_FN_PORT245_IROUT, GPIO_FN_M15_RSW,
297 GPIO_FN_SOUT3, GPIO_FN_SCIFA2_TXD1,
298 GPIO_FN_SIN3, GPIO_FN_SCIFA2_RXD1,
299 GPIO_FN_XRTS3, GPIO_FN_SCIFA2_RTS1, GPIO_FN_PORT248_MSIOF2_SS2,
300 GPIO_FN_XCTS3, GPIO_FN_SCIFA2_CTS1, GPIO_FN_PORT249_MSIOF2_RXD,
301 GPIO_FN_DINT, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3,
302 GPIO_FN_SDHICLK0, GPIO_FN_TCK2,
303 GPIO_FN_SDHICD0,
304 GPIO_FN_SDHID0_0, GPIO_FN_TMS2,
305 GPIO_FN_SDHID0_1, GPIO_FN_TDO2,
306 GPIO_FN_SDHID0_2, GPIO_FN_TDI2,
307 GPIO_FN_SDHID0_3, GPIO_FN_RTCK2,
308
309 /* 49-6 (FN) */
310 GPIO_FN_SDHICMD0, GPIO_FN_TRST2,
311 GPIO_FN_SDHIWP0, GPIO_FN_EDBGREQ2,
312 GPIO_FN_SDHICLK1, GPIO_FN_TCK3,
313 GPIO_FN_SDHID1_0, GPIO_FN_M11_SLCD_SO2,
314 GPIO_FN_TS_SPSYNC2, GPIO_FN_TMS3,
315 GPIO_FN_SDHID1_1, GPIO_FN_M9_SLCD_AO2,
316 GPIO_FN_TS_SDAT2, GPIO_FN_TDO3,
317 GPIO_FN_SDHID1_2, GPIO_FN_M10_SLCD_CK2,
318 GPIO_FN_TS_SDEN2, GPIO_FN_TDI3,
319 GPIO_FN_SDHID1_3, GPIO_FN_M12_SLCD_CE2,
320 GPIO_FN_TS_SCK2, GPIO_FN_RTCK3,
321 GPIO_FN_SDHICMD1, GPIO_FN_TRST3,
322 GPIO_FN_SDHICLK2, GPIO_FN_SCIFB_SCK,
323 GPIO_FN_SDHID2_0, GPIO_FN_SCIFB_TXD,
324 GPIO_FN_SDHID2_1, GPIO_FN_SCIFB_CTS,
325 GPIO_FN_SDHID2_2, GPIO_FN_SCIFB_RXD,
326 GPIO_FN_SDHID2_3, GPIO_FN_SCIFB_RTS,
327 GPIO_FN_SDHICMD2,
328 GPIO_FN_RESETOUTS,
329 GPIO_FN_DIVLOCK,
330};
331
332#endif /* __ASM_SH7367_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index eb98b45c5089..26cd1016fad8 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -452,6 +452,10 @@ enum {
452 SHDMA_SLAVE_SCIF5_RX, 452 SHDMA_SLAVE_SCIF5_RX,
453 SHDMA_SLAVE_SCIF6_TX, 453 SHDMA_SLAVE_SCIF6_TX,
454 SHDMA_SLAVE_SCIF6_RX, 454 SHDMA_SLAVE_SCIF6_RX,
455 SHDMA_SLAVE_FLCTL0_TX,
456 SHDMA_SLAVE_FLCTL0_RX,
457 SHDMA_SLAVE_FLCTL1_TX,
458 SHDMA_SLAVE_FLCTL1_RX,
455 SHDMA_SLAVE_SDHI0_RX, 459 SHDMA_SLAVE_SDHI0_RX,
456 SHDMA_SLAVE_SDHI0_TX, 460 SHDMA_SLAVE_SDHI0_TX,
457 SHDMA_SLAVE_SDHI1_RX, 461 SHDMA_SLAVE_SDHI1_RX,
@@ -475,8 +479,6 @@ extern struct clk sh7372_dv_clki_div2_clk;
475extern struct clk sh7372_pllc2_clk; 479extern struct clk sh7372_pllc2_clk;
476extern struct clk sh7372_fsiack_clk; 480extern struct clk sh7372_fsiack_clk;
477extern struct clk sh7372_fsibck_clk; 481extern struct clk sh7372_fsibck_clk;
478extern struct clk sh7372_fsidiva_clk;
479extern struct clk sh7372_fsidivb_clk;
480 482
481extern void sh7372_intcs_suspend(void); 483extern void sh7372_intcs_suspend(void);
482extern void sh7372_intcs_resume(void); 484extern void sh7372_intcs_resume(void);
diff --git a/arch/arm/mach-shmobile/include/mach/sh7377.h b/arch/arm/mach-shmobile/include/mach/sh7377.h
deleted file mode 100644
index f580e227dd1c..000000000000
--- a/arch/arm/mach-shmobile/include/mach/sh7377.h
+++ /dev/null
@@ -1,360 +0,0 @@
1#ifndef __ASM_SH7377_H__
2#define __ASM_SH7377_H__
3
4/* Pin Function Controller:
5 * GPIO_FN_xx - GPIO used to select pin function
6 * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
7 */
8enum {
9 /* 55-1 -> 55-5 (GPIO) */
10 GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
11 GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
12
13 GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
14 GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
15
16 GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
17 GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
18
19 GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
20 GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
21
22 GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
23 GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
24
25 GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
26 GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
27
28 GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
29 GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
30
31 GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
32 GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
33
34 GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
35 GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
36
37 GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
38 GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
39
40 GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
41 GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
42
43 GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
44 GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118,
45
46 GPIO_PORT128, GPIO_PORT129,
47
48 GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
49 GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
50
51 GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
52 GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
53
54 GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
55 GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
56
57 GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
58
59 GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
60 GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
61
62 GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
63 GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
64
65 GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214,
66 GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219,
67
68 GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224,
69 GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229,
70
71 GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234,
72 GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239,
73
74 GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244,
75 GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249,
76
77 GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254,
78 GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259,
79
80 GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264,
81
82 /* Special Pull-up / Pull-down Functions */
83 GPIO_FN_PORT66_KEYIN0_PU, GPIO_FN_PORT67_KEYIN1_PU,
84 GPIO_FN_PORT68_KEYIN2_PU, GPIO_FN_PORT69_KEYIN3_PU,
85 GPIO_FN_PORT70_KEYIN4_PU, GPIO_FN_PORT71_KEYIN5_PU,
86 GPIO_FN_PORT72_KEYIN6_PU,
87
88 /* 55-1 (FN) */
89 GPIO_FN_VBUS_0,
90 GPIO_FN_CPORT0,
91 GPIO_FN_CPORT1,
92 GPIO_FN_CPORT2,
93 GPIO_FN_CPORT3,
94 GPIO_FN_CPORT4,
95 GPIO_FN_CPORT5,
96 GPIO_FN_CPORT6,
97 GPIO_FN_CPORT7,
98 GPIO_FN_CPORT8,
99 GPIO_FN_CPORT9,
100 GPIO_FN_CPORT10,
101 GPIO_FN_CPORT11, GPIO_FN_SIN2,
102 GPIO_FN_CPORT12, GPIO_FN_XCTS2,
103 GPIO_FN_CPORT13, GPIO_FN_RFSPO4,
104 GPIO_FN_CPORT14, GPIO_FN_RFSPO5,
105 GPIO_FN_CPORT15, GPIO_FN_SCIFA0_SCK, GPIO_FN_GPS_AGC2,
106 GPIO_FN_CPORT16, GPIO_FN_SCIFA0_TXD, GPIO_FN_GPS_AGC3,
107 GPIO_FN_CPORT17_IC_OE, GPIO_FN_SOUT2,
108 GPIO_FN_CPORT18, GPIO_FN_XRTS2, GPIO_FN_PORT19_VIO_CKO2,
109 GPIO_FN_CPORT19_MPORT1,
110 GPIO_FN_CPORT20, GPIO_FN_RFSPO6,
111 GPIO_FN_CPORT21, GPIO_FN_STATUS0,
112 GPIO_FN_CPORT22, GPIO_FN_STATUS1,
113 GPIO_FN_CPORT23, GPIO_FN_STATUS2, GPIO_FN_RFSPO7,
114 GPIO_FN_B_SYNLD1,
115 GPIO_FN_B_SYNLD2, GPIO_FN_SYSENMSK,
116 GPIO_FN_XMAINPS,
117 GPIO_FN_XDIVPS,
118 GPIO_FN_XIDRST,
119 GPIO_FN_IDCLK, GPIO_FN_IC_DP,
120 GPIO_FN_IDIO, GPIO_FN_IC_DM,
121 GPIO_FN_SOUT1, GPIO_FN_SCIFA4_TXD, GPIO_FN_M02_BERDAT,
122 GPIO_FN_SIN1, GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
123 GPIO_FN_XRTS1, GPIO_FN_SCIFA4_RTS, GPIO_FN_M03_BERCLK,
124 GPIO_FN_XCTS1, GPIO_FN_SCIFA4_CTS,
125 GPIO_FN_PCMCLKO,
126 GPIO_FN_SYNC8KO,
127
128 /* 55-2 (FN) */
129 GPIO_FN_DNPCM_A,
130 GPIO_FN_UPPCM_A,
131 GPIO_FN_VACK,
132 GPIO_FN_XTALB1L,
133 GPIO_FN_GPS_AGC1, GPIO_FN_SCIFA0_RTS,
134 GPIO_FN_GPS_AGC4, GPIO_FN_SCIFA0_RXD,
135 GPIO_FN_GPS_PWRDOWN, GPIO_FN_SCIFA0_CTS,
136 GPIO_FN_GPS_IM,
137 GPIO_FN_GPS_IS,
138 GPIO_FN_GPS_QM,
139 GPIO_FN_GPS_QS,
140 GPIO_FN_FMSOCK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT,
141 GPIO_FN_FMSOOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_IPORT3,
142 GPIO_FN_FMSIOLR,
143 GPIO_FN_FMSOOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_OPORT1,
144 GPIO_FN_FMSIOBT,
145 GPIO_FN_FMSOSLD, GPIO_FN_BBIF2_TXD2, GPIO_FN_OPORT2,
146 GPIO_FN_FMSOILR, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3,
147 GPIO_FN_OPORT3, GPIO_FN_FMSIILR,
148 GPIO_FN_FMSOIBT, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2,
149 GPIO_FN_FMSIIBT,
150 GPIO_FN_FMSISLD, GPIO_FN_MFG0_OUT1, GPIO_FN_TPU0TO0,
151 GPIO_FN_A0_EA0, GPIO_FN_BS,
152 GPIO_FN_A12_EA12, GPIO_FN_PORT58_VIO_CKOR, GPIO_FN_TPU4TO2,
153 GPIO_FN_A13_EA13, GPIO_FN_PORT59_IROUT, GPIO_FN_MFG0_OUT2,
154 GPIO_FN_TPU0TO1,
155 GPIO_FN_A14_EA14, GPIO_FN_PORT60_KEYOUT5,
156 GPIO_FN_A15_EA15, GPIO_FN_PORT61_KEYOUT4,
157 GPIO_FN_A16_EA16, GPIO_FN_PORT62_KEYOUT3, GPIO_FN_MSIOF0_SS1,
158 GPIO_FN_A17_EA17, GPIO_FN_PORT63_KEYOUT2, GPIO_FN_MSIOF0_TSYNC,
159 GPIO_FN_A18_EA18, GPIO_FN_PORT64_KEYOUT1, GPIO_FN_MSIOF0_TSCK,
160 GPIO_FN_A19_EA19, GPIO_FN_PORT65_KEYOUT0, GPIO_FN_MSIOF0_TXD,
161 GPIO_FN_A20_EA20, GPIO_FN_PORT66_KEYIN0, GPIO_FN_MSIOF0_RSCK,
162 GPIO_FN_A21_EA21, GPIO_FN_PORT67_KEYIN1, GPIO_FN_MSIOF0_RSYNC,
163 GPIO_FN_A22_EA22, GPIO_FN_PORT68_KEYIN2, GPIO_FN_MSIOF0_MCK0,
164 GPIO_FN_A23_EA23, GPIO_FN_PORT69_KEYIN3, GPIO_FN_MSIOF0_MCK1,
165 GPIO_FN_A24_EA24, GPIO_FN_PORT70_KEYIN4, GPIO_FN_MSIOF0_RXD,
166 GPIO_FN_A25_EA25, GPIO_FN_PORT71_KEYIN5, GPIO_FN_MSIOF0_SS2,
167 GPIO_FN_A26, GPIO_FN_PORT72_KEYIN6,
168 GPIO_FN_D0_ED0_NAF0,
169 GPIO_FN_D1_ED1_NAF1,
170 GPIO_FN_D2_ED2_NAF2,
171 GPIO_FN_D3_ED3_NAF3,
172 GPIO_FN_D4_ED4_NAF4,
173 GPIO_FN_D5_ED5_NAF5,
174 GPIO_FN_D6_ED6_NAF6,
175 GPIO_FN_D7_ED7_NAF7,
176 GPIO_FN_D8_ED8_NAF8,
177 GPIO_FN_D9_ED9_NAF9,
178 GPIO_FN_D10_ED10_NAF10,
179 GPIO_FN_D11_ED11_NAF11,
180 GPIO_FN_D12_ED12_NAF12,
181 GPIO_FN_D13_ED13_NAF13,
182 GPIO_FN_D14_ED14_NAF14,
183 GPIO_FN_D15_ED15_NAF15,
184 GPIO_FN_CS4,
185 GPIO_FN_CS5A, GPIO_FN_FMSICK,
186 GPIO_FN_CS5B, GPIO_FN_FCE1,
187
188 /* 55-3 (FN) */
189 GPIO_FN_CS6B, GPIO_FN_XCS2, GPIO_FN_CS6A, GPIO_FN_DACK0,
190 GPIO_FN_FCE0,
191 GPIO_FN_WAIT, GPIO_FN_DREQ0,
192 GPIO_FN_RD_XRD,
193 GPIO_FN_WE0_XWR0_FWE,
194 GPIO_FN_WE1_XWR1,
195 GPIO_FN_FRB,
196 GPIO_FN_CKO,
197 GPIO_FN_NBRSTOUT,
198 GPIO_FN_NBRST,
199 GPIO_FN_GPS_EPPSIN,
200 GPIO_FN_LATCHPULSE,
201 GPIO_FN_LTESIGNAL,
202 GPIO_FN_LEGACYSTATE,
203 GPIO_FN_TCKON,
204 GPIO_FN_VIO_VD, GPIO_FN_PORT128_KEYOUT0, GPIO_FN_IPORT0,
205 GPIO_FN_VIO_HD, GPIO_FN_PORT129_KEYOUT1, GPIO_FN_IPORT1,
206 GPIO_FN_VIO_D0, GPIO_FN_PORT130_KEYOUT2, GPIO_FN_PORT130_MSIOF2_RXD,
207 GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT3, GPIO_FN_PORT131_MSIOF2_SS1,
208 GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT4, GPIO_FN_PORT132_MSIOF2_SS2,
209 GPIO_FN_VIO_D3, GPIO_FN_PORT133_KEYOUT5, GPIO_FN_PORT133_MSIOF2_TSYNC,
210 GPIO_FN_VIO_D4, GPIO_FN_PORT134_KEYIN0, GPIO_FN_PORT134_MSIOF2_TXD,
211 GPIO_FN_VIO_D5, GPIO_FN_PORT135_KEYIN1, GPIO_FN_PORT135_MSIOF2_TSCK,
212 GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYIN2,
213 GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYIN3,
214 GPIO_FN_VIO_D8, GPIO_FN_M9_SLCD_A01, GPIO_FN_PORT138_FSIAOMC,
215 GPIO_FN_VIO_D9, GPIO_FN_M10_SLCD_CK1, GPIO_FN_PORT139_FSIAOLR,
216 GPIO_FN_VIO_D10, GPIO_FN_M11_SLCD_SO1, GPIO_FN_TPU0TO2,
217 GPIO_FN_PORT140_FSIAOBT,
218 GPIO_FN_VIO_D11, GPIO_FN_M12_SLCD_CE1, GPIO_FN_TPU0TO3,
219 GPIO_FN_PORT141_FSIAOSLD,
220 GPIO_FN_VIO_D12, GPIO_FN_M13_BSW, GPIO_FN_PORT142_FSIACK,
221 GPIO_FN_VIO_D13, GPIO_FN_M14_GSW, GPIO_FN_PORT143_FSIAILR,
222 GPIO_FN_VIO_D14, GPIO_FN_M15_RSW, GPIO_FN_PORT144_FSIAIBT,
223 GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_FSIAISLD,
224 GPIO_FN_VIO_CLK, GPIO_FN_PORT146_KEYIN4, GPIO_FN_IPORT2,
225 GPIO_FN_VIO_FIELD, GPIO_FN_PORT147_KEYIN5,
226 GPIO_FN_VIO_CKO, GPIO_FN_PORT148_KEYIN6,
227 GPIO_FN_A27, GPIO_FN_RDWR_XWE, GPIO_FN_MFG0_IN1,
228 GPIO_FN_MFG0_IN2,
229 GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK,
230 GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC,
231 GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1,
232 GPIO_FN_SOUT3, GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0,
233 GPIO_FN_SIN3, GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1,
234 GPIO_FN_XRTS3, GPIO_FN_SCIFA2_RTS1, GPIO_FN_PORT156_MSIOF2_SS2,
235 GPIO_FN_XCTS3, GPIO_FN_SCIFA2_CTS1, GPIO_FN_PORT157_MSIOF2_RXD,
236
237 /* 55-4 (FN) */
238 GPIO_FN_DINT, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3,
239 GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI,
240 GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD, GPIO_FN_SOUT0,
241 GPIO_FN_PORT161_SCIFB_CTS, GPIO_FN_PORT161_SCIFA5_CTS, GPIO_FN_XCTS0,
242 GPIO_FN_MFG3_IN2,
243 GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD, GPIO_FN_SIN0,
244 GPIO_FN_MFG3_IN1,
245 GPIO_FN_PORT163_SCIFB_RTS, GPIO_FN_PORT163_SCIFA5_RTS, GPIO_FN_XRTS0,
246 GPIO_FN_MFG3_OUT1,
247 GPIO_FN_TPU3TO0,
248 GPIO_FN_LCDD0, GPIO_FN_PORT192_KEYOUT0, GPIO_FN_EXT_CKI,
249 GPIO_FN_LCDD1, GPIO_FN_PORT193_KEYOUT1, GPIO_FN_PORT193_SCIFA5_CTS,
250 GPIO_FN_BBIF2_TSYNC1,
251 GPIO_FN_LCDD2, GPIO_FN_PORT194_KEYOUT2, GPIO_FN_PORT194_SCIFA5_RTS,
252 GPIO_FN_BBIF2_TSCK1,
253 GPIO_FN_LCDD3, GPIO_FN_PORT195_KEYOUT3, GPIO_FN_PORT195_SCIFA5_RXD,
254 GPIO_FN_BBIF2_TXD1,
255 GPIO_FN_LCDD4, GPIO_FN_PORT196_KEYOUT4, GPIO_FN_PORT196_SCIFA5_TXD,
256 GPIO_FN_LCDD5, GPIO_FN_PORT197_KEYOUT5, GPIO_FN_PORT197_SCIFA5_SCK,
257 GPIO_FN_MFG2_OUT2, GPIO_FN_TPU2TO1,
258 GPIO_FN_LCDD6, GPIO_FN_XWR2,
259 GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2, GPIO_FN_XWR3,
260 GPIO_FN_LCDD8, GPIO_FN_PORT200_KEYIN0, GPIO_FN_VIO_DR0, GPIO_FN_D16,
261 GPIO_FN_ED16,
262 GPIO_FN_LCDD9, GPIO_FN_PORT201_KEYIN1, GPIO_FN_VIO_DR1, GPIO_FN_D17,
263 GPIO_FN_ED17,
264 GPIO_FN_LCDD10, GPIO_FN_PORT202_KEYIN2, GPIO_FN_VIO_DR2, GPIO_FN_D18,
265 GPIO_FN_ED18,
266 GPIO_FN_LCDD11, GPIO_FN_PORT203_KEYIN3, GPIO_FN_VIO_DR3, GPIO_FN_D19,
267 GPIO_FN_ED19,
268 GPIO_FN_LCDD12, GPIO_FN_PORT204_KEYIN4, GPIO_FN_VIO_DR4, GPIO_FN_D20,
269 GPIO_FN_ED20,
270 GPIO_FN_LCDD13, GPIO_FN_PORT205_KEYIN5, GPIO_FN_VIO_DR5, GPIO_FN_D21,
271 GPIO_FN_ED21,
272 GPIO_FN_LCDD14, GPIO_FN_PORT206_KEYIN6, GPIO_FN_VIO_DR6, GPIO_FN_D22,
273 GPIO_FN_ED22,
274 GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_PORT207_KEYOUT0,
275 GPIO_FN_VIO_DR7,
276 GPIO_FN_D23, GPIO_FN_ED23,
277 GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_PORT208_KEYOUT1,
278 GPIO_FN_VIO_VDR,
279 GPIO_FN_D24, GPIO_FN_ED24,
280 GPIO_FN_LCDD17, GPIO_FN_PORT209_KEYOUT2, GPIO_FN_VIO_HDR, GPIO_FN_D25,
281 GPIO_FN_ED25,
282 GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
283 GPIO_FN_ED26,
284 GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27, GPIO_FN_ED27,
285 GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
286 GPIO_FN_ED28,
287 GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
288 GPIO_FN_ED29,
289 GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
290 GPIO_FN_ED30,
291 GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
292 GPIO_FN_ED31,
293 GPIO_FN_LCDDCK, GPIO_FN_LCDWR, GPIO_FN_PORT216_KEYOUT3,
294 GPIO_FN_VIO_CLKR,
295 GPIO_FN_LCDRD, GPIO_FN_DACK2, GPIO_FN_MSIOF0L_TSYNC,
296 GPIO_FN_LCDHSYN, GPIO_FN_LCDCS, GPIO_FN_LCDCS2, GPIO_FN_DACK3,
297 GPIO_FN_PORT218_VIO_CKOR, GPIO_FN_PORT218_KEYOUT4,
298 GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK,
299 GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2, GPIO_FN_PORT220_KEYOUT5,
300 GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD,
301 GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN,
302 GPIO_FN_MSIOF0L_TXD,
303 GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2,
304 GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_USBTERM,
305 GPIO_FN_PORT226_VIO_CKO2,
306 GPIO_FN_SCIFA1_RTS, GPIO_FN_IDIN,
307 GPIO_FN_SCIFA1_RXD,
308 GPIO_FN_SCIFA1_CTS, GPIO_FN_MFG1_IN1,
309 GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2, GPIO_FN_PORT230_FSIAOMC,
310 GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2, GPIO_FN_PORT231_FSIAOLR,
311 GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2, GPIO_FN_PORT232_FSIAOBT,
312 GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2, GPIO_FN_GPS_VCOTRIG,
313 GPIO_FN_PORT233_FSIACK,
314 GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2, GPIO_FN_PORT234_FSIAOSLD,
315 GPIO_FN_MSIOF1_RSYNC, GPIO_FN_OPORT0, GPIO_FN_MFG1_IN2,
316 GPIO_FN_PORT235_FSIAILR,
317 GPIO_FN_MSIOF1_MCK0, GPIO_FN_I2C_SDA2, GPIO_FN_PORT236_FSIAIBT,
318 GPIO_FN_MSIOF1_MCK1, GPIO_FN_I2C_SCL2, GPIO_FN_PORT237_FSIAISLD,
319 GPIO_FN_MSIOF1_SS1, GPIO_FN_EDBGREQ3,
320
321 /* 55-5 (FN) */
322 GPIO_FN_MSIOF1_SS2,
323 GPIO_FN_SCIFA6_TXD,
324 GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1,
325 GPIO_FN_TPU4TO0,
326 GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2,
327 GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2,
328 GPIO_FN_PORT244_SCIFA5_CTS, GPIO_FN_MFG2_IN1, GPIO_FN_PORT244_SCIFB_CTS,
329 GPIO_FN_PORT244_MSIOF2_RXD,
330 GPIO_FN_PORT245_SCIFA5_RTS, GPIO_FN_MFG2_IN2, GPIO_FN_PORT245_SCIFB_RTS,
331 GPIO_FN_PORT245_MSIOF2_TXD,
332 GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1,
333 GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0,
334 GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2,
335 GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1,
336 GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1,
337 GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0,
338 GPIO_FN_PORT248_MSIOF2_TSCK,
339 GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, GPIO_FN_PORT249_MSIOF2_TSYNC,
340 GPIO_FN_SDHICLK0, GPIO_FN_TCK2_SWCLK_MC0,
341 GPIO_FN_SDHICD0,
342 GPIO_FN_SDHID0_0, GPIO_FN_TMS2_SWDIO_MC0,
343 GPIO_FN_SDHID0_1, GPIO_FN_TDO2_SWO0_MC0,
344 GPIO_FN_SDHID0_2, GPIO_FN_TDI2,
345 GPIO_FN_SDHID0_3, GPIO_FN_RTCK2_SWO1_MC0,
346 GPIO_FN_SDHICMD0, GPIO_FN_TRST2,
347 GPIO_FN_SDHIWP0, GPIO_FN_EDBGREQ2,
348 GPIO_FN_SDHICLK1, GPIO_FN_TCK3_SWCLK_MC1,
349 GPIO_FN_SDHID1_0, GPIO_FN_M11_SLCD_SO2, GPIO_FN_TS_SPSYNC2,
350 GPIO_FN_TMS3_SWDIO_MC1,
351 GPIO_FN_SDHID1_1, GPIO_FN_M9_SLCD_A02, GPIO_FN_TS_SDAT2,
352 GPIO_FN_TDO3_SWO0_MC1,
353 GPIO_FN_SDHID1_2, GPIO_FN_M10_SLCD_CK2, GPIO_FN_TS_SDEN2, GPIO_FN_TDI3,
354 GPIO_FN_SDHID1_3, GPIO_FN_M12_SLCD_CE2, GPIO_FN_TS_SCK2,
355 GPIO_FN_RTCK3_SWO1_MC1,
356 GPIO_FN_SDHICMD1, GPIO_FN_TRST3,
357 GPIO_FN_RESETOUTS,
358};
359
360#endif /* __ASM_SH7377_H__ */
diff --git a/arch/arm/mach-shmobile/intc-sh7367.c b/arch/arm/mach-shmobile/intc-sh7367.c
deleted file mode 100644
index 5bf776495b75..000000000000
--- a/arch/arm/mach-shmobile/intc-sh7367.c
+++ /dev/null
@@ -1,413 +0,0 @@
1/*
2 * sh7367 processor support - INTC hardware block
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/io.h>
24#include <linux/sh_intc.h>
25#include <mach/intc.h>
26#include <mach/irqs.h>
27#include <asm/mach-types.h>
28#include <asm/mach/arch.h>
29
30enum {
31 UNUSED_INTCA = 0,
32 ENABLED,
33 DISABLED,
34
35 /* interrupt sources INTCA */
36 DIRC,
37 CRYPT1_ERR, CRYPT2_STD,
38 IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1,
39 ARM11_IRQPMU, ARM11_COMMTX, ARM11_COMMRX,
40 ETM11_ACQCMP, ETM11_FULL,
41 MFI_MFIM, MFI_MFIS,
42 BBIF1, BBIF2,
43 USBDMAC_USHDMI,
44 USBHS_USHI0, USBHS_USHI1,
45 CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3,
46 KEYSC_KEY,
47 SCIFA0, SCIFA1, SCIFA2, SCIFA3,
48 MSIOF2, MSIOF1,
49 SCIFA4, SCIFA5, SCIFB,
50 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
51 SDHI0,
52 SDHI1,
53 MSU_MSU, MSU_MSU2,
54 IREM,
55 SIU,
56 SPU,
57 IRDA,
58 TPU0, TPU1, TPU2, TPU3, TPU4,
59 LCRC,
60 PINT1, PINT2,
61 TTI20,
62 MISTY,
63 DDM,
64 SDHI2,
65 RWDT0, RWDT1,
66 DMAC_1_DEI0, DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3,
67 DMAC_2_DEI4, DMAC_2_DEI5, DMAC_2_DADERR,
68 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
69 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
70 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
71 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
72
73 /* interrupt groups INTCA */
74 DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2,
75 ETM11, ARM11, USBHS, FLCTL, IIC1
76};
77
78static struct intc_vect intca_vectors[] __initdata = {
79 INTC_VECT(DIRC, 0x0560),
80 INTC_VECT(CRYPT1_ERR, 0x05e0),
81 INTC_VECT(CRYPT2_STD, 0x0700),
82 INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0),
83 INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0),
84 INTC_VECT(ARM11_IRQPMU, 0x0800), INTC_VECT(ARM11_COMMTX, 0x0840),
85 INTC_VECT(ARM11_COMMRX, 0x0860),
86 INTC_VECT(ETM11_ACQCMP, 0x0880), INTC_VECT(ETM11_FULL, 0x08a0),
87 INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920),
88 INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960),
89 INTC_VECT(USBDMAC_USHDMI, 0x0a00),
90 INTC_VECT(USBHS_USHI0, 0x0a20), INTC_VECT(USBHS_USHI1, 0x0a40),
91 INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20),
92 INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60),
93 INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0),
94 INTC_VECT(KEYSC_KEY, 0x0be0),
95 INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20),
96 INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60),
97 INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00),
98 INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40),
99 INTC_VECT(SCIFB, 0x0d60),
100 INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
101 INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
102 INTC_VECT(SDHI0, 0x0e00), INTC_VECT(SDHI0, 0x0e20),
103 INTC_VECT(SDHI0, 0x0e40), INTC_VECT(SDHI0, 0x0e60),
104 INTC_VECT(SDHI1, 0x0e80), INTC_VECT(SDHI1, 0x0ea0),
105 INTC_VECT(SDHI1, 0x0ec0), INTC_VECT(SDHI1, 0x0ee0),
106 INTC_VECT(MSU_MSU, 0x0f20), INTC_VECT(MSU_MSU2, 0x0f40),
107 INTC_VECT(IREM, 0x0f60),
108 INTC_VECT(SIU, 0x0fa0),
109 INTC_VECT(SPU, 0x0fc0),
110 INTC_VECT(IRDA, 0x0480),
111 INTC_VECT(TPU0, 0x04a0), INTC_VECT(TPU1, 0x04c0),
112 INTC_VECT(TPU2, 0x04e0), INTC_VECT(TPU3, 0x0500),
113 INTC_VECT(TPU4, 0x0520),
114 INTC_VECT(LCRC, 0x0540),
115 INTC_VECT(PINT1, 0x1000), INTC_VECT(PINT2, 0x1020),
116 INTC_VECT(TTI20, 0x1100),
117 INTC_VECT(MISTY, 0x1120),
118 INTC_VECT(DDM, 0x1140),
119 INTC_VECT(SDHI2, 0x1200), INTC_VECT(SDHI2, 0x1220),
120 INTC_VECT(SDHI2, 0x1240), INTC_VECT(SDHI2, 0x1260),
121 INTC_VECT(RWDT0, 0x1280), INTC_VECT(RWDT1, 0x12a0),
122 INTC_VECT(DMAC_1_DEI0, 0x2000), INTC_VECT(DMAC_1_DEI1, 0x2020),
123 INTC_VECT(DMAC_1_DEI2, 0x2040), INTC_VECT(DMAC_1_DEI3, 0x2060),
124 INTC_VECT(DMAC_2_DEI4, 0x2080), INTC_VECT(DMAC_2_DEI5, 0x20a0),
125 INTC_VECT(DMAC_2_DADERR, 0x20c0),
126 INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120),
127 INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160),
128 INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0),
129 INTC_VECT(DMAC2_2_DADERR, 0x21c0),
130 INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220),
131 INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260),
132 INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0),
133 INTC_VECT(DMAC3_2_DADERR, 0x22c0),
134};
135
136static struct intc_group intca_groups[] __initdata = {
137 INTC_GROUP(DMAC_1, DMAC_1_DEI0,
138 DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3),
139 INTC_GROUP(DMAC_2, DMAC_2_DEI4,
140 DMAC_2_DEI5, DMAC_2_DADERR),
141 INTC_GROUP(DMAC2_1, DMAC2_1_DEI0,
142 DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
143 INTC_GROUP(DMAC2_2, DMAC2_2_DEI4,
144 DMAC2_2_DEI5, DMAC2_2_DADERR),
145 INTC_GROUP(DMAC3_1, DMAC3_1_DEI0,
146 DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
147 INTC_GROUP(DMAC3_2, DMAC3_2_DEI4,
148 DMAC3_2_DEI5, DMAC3_2_DADERR),
149 INTC_GROUP(ETM11, ETM11_ACQCMP, ETM11_FULL),
150 INTC_GROUP(ARM11, ARM11_IRQPMU, ARM11_COMMTX, ARM11_COMMTX),
151 INTC_GROUP(USBHS, USBHS_USHI0, USBHS_USHI1),
152 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
153 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
154 INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
155};
156
157static struct intc_mask_reg intca_mask_registers[] __initdata = {
158 { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
159 { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
160 ARM11_IRQPMU, 0, ARM11_COMMTX, ARM11_COMMRX } },
161 { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */
162 { CRYPT1_ERR, CRYPT2_STD, DIRC, 0,
163 DMAC_1_DEI3, DMAC_1_DEI2, DMAC_1_DEI1, DMAC_1_DEI0 } },
164 { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */
165 { PINT1, PINT2, 0, 0,
166 BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } },
167 { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */
168 { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
169 DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
170 { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */
171 { DDM, 0, 0, 0,
172 0, 0, ETM11_FULL, ETM11_ACQCMP } },
173 { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */
174 { KEYSC_KEY, DMAC_2_DADERR, DMAC_2_DEI5, DMAC_2_DEI4,
175 SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
176 { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */
177 { SCIFB, SCIFA5, SCIFA4, MSIOF1,
178 0, 0, MSIOF2, 0 } },
179 { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
180 { DISABLED, ENABLED, ENABLED, ENABLED,
181 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
182 { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
183 { DISABLED, ENABLED, ENABLED, ENABLED,
184 TTI20, USBDMAC_USHDMI, SPU, SIU } },
185 { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
186 { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
187 CMT2, USBHS_USHI1, USBHS_USHI0, 0 } },
188 { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */
189 { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
190 0, 0, 0, 0 } },
191 { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */
192 { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1,
193 LCRC, MSU_MSU2, IREM, MSU_MSU } },
194 { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */
195 { 0, 0, TPU0, TPU1,
196 TPU2, TPU3, TPU4, 0 } },
197 { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
198 { DISABLED, ENABLED, ENABLED, ENABLED,
199 MISTY, CMT3, RWDT1, RWDT0 } },
200};
201
202static struct intc_prio_reg intca_prio_registers[] __initdata = {
203 { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } },
204 { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, ETM11, BBIF1, BBIF2 } },
205 { 0xe6940008, 0, 16, 4, /* IPRCA */ { CRYPT1_ERR, CRYPT2_STD,
206 CMT1_CMT11, ARM11 } },
207 { 0xe694000c, 0, 16, 4, /* IPRDA */ { PINT1, PINT2,
208 CMT1_CMT12, TPU4 } },
209 { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC_1, MFI_MFIS,
210 MFI_MFIM, USBHS } },
211 { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC_2,
212 0, CMT1_CMT10 } },
213 { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
214 SCIFA2, SCIFA3 } },
215 { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBDMAC_USHDMI,
216 FLCTL, SDHI0 } },
217 { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, MSU_MSU, IIC1 } },
218 { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, SIU, TTI20 } },
219 { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IREM, SDHI1 } },
220 { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, TPU1, TPU2, TPU3 } },
221 { 0xe6940030, 0, 16, 4, /* IPRMA */ { MISTY, CMT3, RWDT1, RWDT0 } },
222 { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, SPU, DDM } },
223 { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
224};
225
226static struct intc_desc intca_desc __initdata = {
227 .name = "sh7367-intca",
228 .force_enable = ENABLED,
229 .force_disable = DISABLED,
230 .hw = INTC_HW_DESC(intca_vectors, intca_groups,
231 intca_mask_registers, intca_prio_registers,
232 NULL, NULL),
233};
234
235INTC_IRQ_PINS_16(intca_irq_pins, 0xe6900000,
236 INTC_VECT, "sh7367-intca-irq-pins");
237
238enum {
239 UNUSED_INTCS = 0,
240
241 INTCS,
242
243 /* interrupt sources INTCS */
244 VIO2_VEU0, VIO2_VEU1, VIO2_VEU2, VIO2_VEU3,
245 VIO3_VOU,
246 RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3,
247 VIO1_CEU, VIO1_BEU0, VIO1_BEU1, VIO1_BEU2,
248 VPU,
249 SGX530,
250 _2DDMAC_2DDM0, _2DDMAC_2DDM1, _2DDMAC_2DDM2, _2DDMAC_2DDM3,
251 IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
252 IPMMU_IPMMUB, IPMMU_IPMMUS,
253 RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR,
254 MSIOF,
255 IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
256 TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
257 CMT,
258 TSIF,
259 IPMMUI,
260 MVI3,
261 ICB,
262 PEP,
263 ASA,
264 BEM,
265 VE2HO,
266 HQE,
267 JPEG,
268 LCDC,
269
270 /* interrupt groups INTCS */
271 _2DDMAC, RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2,
272};
273
274static struct intc_vect intcs_vectors[] = {
275 INTCS_VECT(VIO2_VEU0, 0x700), INTCS_VECT(VIO2_VEU1, 0x720),
276 INTCS_VECT(VIO2_VEU2, 0x740), INTCS_VECT(VIO2_VEU3, 0x760),
277 INTCS_VECT(VIO3_VOU, 0x780),
278 INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820),
279 INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860),
280 INTCS_VECT(VIO1_CEU, 0x880), INTCS_VECT(VIO1_BEU0, 0x8a0),
281 INTCS_VECT(VIO1_BEU1, 0x8c0), INTCS_VECT(VIO1_BEU2, 0x8e0),
282 INTCS_VECT(VPU, 0x980),
283 INTCS_VECT(SGX530, 0x9e0),
284 INTCS_VECT(_2DDMAC_2DDM0, 0xa00), INTCS_VECT(_2DDMAC_2DDM1, 0xa20),
285 INTCS_VECT(_2DDMAC_2DDM2, 0xa40), INTCS_VECT(_2DDMAC_2DDM3, 0xa60),
286 INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0),
287 INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0),
288 INTCS_VECT(IPMMU_IPMMUB, 0xb20), INTCS_VECT(IPMMU_IPMMUS, 0xb60),
289 INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0),
290 INTCS_VECT(RTDMAC_2_DADERR, 0xbc0),
291 INTCS_VECT(MSIOF, 0xd20),
292 INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20),
293 INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60),
294 INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0),
295 INTCS_VECT(TMU_TUNI2, 0xec0),
296 INTCS_VECT(CMT, 0xf00),
297 INTCS_VECT(TSIF, 0xf20),
298 INTCS_VECT(IPMMUI, 0xf60),
299 INTCS_VECT(MVI3, 0x420),
300 INTCS_VECT(ICB, 0x480),
301 INTCS_VECT(PEP, 0x4a0),
302 INTCS_VECT(ASA, 0x4c0),
303 INTCS_VECT(BEM, 0x4e0),
304 INTCS_VECT(VE2HO, 0x520),
305 INTCS_VECT(HQE, 0x540),
306 INTCS_VECT(JPEG, 0x560),
307 INTCS_VECT(LCDC, 0x580),
308
309 INTC_VECT(INTCS, 0xf80),
310};
311
312static struct intc_group intcs_groups[] __initdata = {
313 INTC_GROUP(_2DDMAC, _2DDMAC_2DDM0, _2DDMAC_2DDM1,
314 _2DDMAC_2DDM2, _2DDMAC_2DDM3),
315 INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI0, RTDMAC_1_DEI1,
316 RTDMAC_1_DEI2, RTDMAC_1_DEI3),
317 INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR),
318 INTC_GROUP(VEU, VIO2_VEU0, VIO2_VEU1, VIO2_VEU2, VIO2_VEU3),
319 INTC_GROUP(BEU, VIO1_BEU0, VIO1_BEU1, VIO1_BEU2),
320 INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
321 INTC_GROUP(IPMMU, IPMMU_IPMMUS, IPMMU_IPMMUB),
322 INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
323};
324
325static struct intc_mask_reg intcs_mask_registers[] = {
326 { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
327 { VIO1_BEU2, VIO1_BEU1, VIO1_BEU0, VIO1_CEU,
328 VIO2_VEU3, VIO2_VEU2, VIO2_VEU1, VIO2_VEU0 } },
329 { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
330 { VIO3_VOU, 0, VE2HO, VPU,
331 0, 0, 0, 0 } },
332 { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
333 { _2DDMAC_2DDM3, _2DDMAC_2DDM2, _2DDMAC_2DDM1, _2DDMAC_2DDM0,
334 BEM, ASA, PEP, ICB } },
335 { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
336 { 0, 0, MVI3, 0,
337 JPEG, HQE, 0, LCDC } },
338 { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
339 { 0, RTDMAC_2_DADERR, RTDMAC_2_DEI5, RTDMAC_2_DEI4,
340 RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } },
341 { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
342 { 0, 0, MSIOF, 0,
343 SGX530, 0, 0, 0 } },
344 { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
345 { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
346 0, 0, 0, 0 } },
347 { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
348 { 0, 0, 0, CMT,
349 IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
350 { 0xffd201a8, 0xffd201e8, 8, /* IMR10SA / IMCR10SA */
351 { IPMMU_IPMMUS, 0, IPMMU_IPMMUB, 0,
352 0, 0, 0, 0 } },
353 { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
354 { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
355 0, 0, IPMMUI, TSIF } },
356 { 0xffd20104, 0, 16, /* INTAMASK */
357 { 0, 0, 0, 0, 0, 0, 0, 0,
358 0, 0, 0, 0, 0, 0, 0, INTCS } },
359};
360
361/* Priority is needed for INTCA to receive the INTCS interrupt */
362static struct intc_prio_reg intcs_prio_registers[] = {
363 { 0xffd20000, 0, 16, 4, /* IPRAS */ { 0, MVI3, _2DDMAC, ICB } },
364 { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPEG, LCDC, 0, 0 } },
365 { 0xffd20008, 0, 16, 4, /* IPRCS */ { BBIF2, 0, 0, 0 } },
366 { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_1, VIO1_CEU, 0, VPU } },
367 { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0, RTDMAC_2, 0, CMT } },
368 { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU_TUNI0, TMU_TUNI1,
369 TMU_TUNI2, 0 } },
370 { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, VIO3_VOU, VEU, BEU } },
371 { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF, IIC0 } },
372 { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, SGX530, 0, 0 } },
373 { 0xffd20028, 0, 16, 4, /* IPRKS */ { BEM, ASA, IPMMUI, PEP } },
374 { 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, VE2HO, HQE } },
375 { 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } },
376};
377
378static struct resource intcs_resources[] __initdata = {
379 [0] = {
380 .start = 0xffd20000,
381 .end = 0xffd2ffff,
382 .flags = IORESOURCE_MEM,
383 }
384};
385
386static struct intc_desc intcs_desc __initdata = {
387 .name = "sh7367-intcs",
388 .resource = intcs_resources,
389 .num_resources = ARRAY_SIZE(intcs_resources),
390 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
391 intcs_prio_registers, NULL, NULL),
392};
393
394static void intcs_demux(unsigned int irq, struct irq_desc *desc)
395{
396 void __iomem *reg = (void *)irq_get_handler_data(irq);
397 unsigned int evtcodeas = ioread32(reg);
398
399 generic_handle_irq(intcs_evt2irq(evtcodeas));
400}
401
402void __init sh7367_init_irq(void)
403{
404 void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
405
406 register_intc_controller(&intca_desc);
407 register_intc_controller(&intca_irq_pins_desc);
408 register_intc_controller(&intcs_desc);
409
410 /* demux using INTEVTSA */
411 irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa);
412 irq_set_chained_handler(evt2irq(0xf80), intcs_demux);
413}
diff --git a/arch/arm/mach-shmobile/intc-sh7377.c b/arch/arm/mach-shmobile/intc-sh7377.c
deleted file mode 100644
index b84a460a3405..000000000000
--- a/arch/arm/mach-shmobile/intc-sh7377.c
+++ /dev/null
@@ -1,592 +0,0 @@
1/*
2 * sh7377 processor support - INTC hardware block
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/io.h>
24#include <linux/sh_intc.h>
25#include <mach/intc.h>
26#include <mach/irqs.h>
27#include <asm/mach-types.h>
28#include <asm/mach/arch.h>
29
30enum {
31 UNUSED_INTCA = 0,
32 ENABLED,
33 DISABLED,
34
35 /* interrupt sources INTCA */
36 DIRC,
37 _2DG,
38 CRYPT_STD,
39 IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1,
40 AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX,
41 MFI_MFIM, MFI_MFIS,
42 BBIF1, BBIF2,
43 USBDMAC_USHDMI,
44 USBHS_USHI0, USBHS_USHI1,
45 _3DG_SGX540,
46 CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3,
47 KEYSC_KEY,
48 SCIFA0, SCIFA1, SCIFA2, SCIFA3,
49 MSIOF2, MSIOF1,
50 SCIFA4, SCIFA5, SCIFB,
51 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
52 SDHI0,
53 SDHI1,
54 MSU_MSU, MSU_MSU2,
55 IRREM,
56 MSUG,
57 IRDA,
58 TPU0, TPU1, TPU2, TPU3, TPU4,
59 LCRC,
60 PINTCA_PINT1, PINTCA_PINT2,
61 TTI20,
62 MISTY,
63 DDM,
64 RWDT0, RWDT1,
65 DMAC_1_DEI0, DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3,
66 DMAC_2_DEI4, DMAC_2_DEI5, DMAC_2_DADERR,
67 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
68 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
69 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
70 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
71 SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
72 ICUSB_ICUSB0, ICUSB_ICUSB1,
73 ICUDMC_ICUDMC1, ICUDMC_ICUDMC2,
74 SPU2_SPU0, SPU2_SPU1,
75 FSI,
76 FMSI,
77 SCUV,
78 IPMMU_IPMMUB,
79 AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, AP_ARM_DMAIRQ, AP_ARM_DMASIRQ,
80 MFIS2,
81 CPORTR2S,
82 CMT14, CMT15,
83 SCIFA6,
84
85 /* interrupt groups INTCA */
86 DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT,
87 AP_ARM1, AP_ARM2, USBHS, SPU2, FLCTL, IIC1,
88 ICUSB, ICUDMC
89};
90
91static struct intc_vect intca_vectors[] __initdata = {
92 INTC_VECT(DIRC, 0x0560),
93 INTC_VECT(_2DG, 0x05e0),
94 INTC_VECT(CRYPT_STD, 0x0700),
95 INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0),
96 INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0),
97 INTC_VECT(AP_ARM_IRQPMU, 0x0800), INTC_VECT(AP_ARM_COMMTX, 0x0840),
98 INTC_VECT(AP_ARM_COMMRX, 0x0860),
99 INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920),
100 INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960),
101 INTC_VECT(USBDMAC_USHDMI, 0x0a00),
102 INTC_VECT(USBHS_USHI0, 0x0a20), INTC_VECT(USBHS_USHI1, 0x0a40),
103 INTC_VECT(_3DG_SGX540, 0x0a60),
104 INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20),
105 INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60),
106 INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0),
107 INTC_VECT(KEYSC_KEY, 0x0be0),
108 INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20),
109 INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60),
110 INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00),
111 INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40),
112 INTC_VECT(SCIFB, 0x0d60),
113 INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
114 INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
115 INTC_VECT(SDHI0, 0x0e00), INTC_VECT(SDHI0, 0x0e20),
116 INTC_VECT(SDHI0, 0x0e40), INTC_VECT(SDHI0, 0x0e60),
117 INTC_VECT(SDHI1, 0x0e80), INTC_VECT(SDHI1, 0x0ea0),
118 INTC_VECT(SDHI1, 0x0ec0), INTC_VECT(SDHI1, 0x0ee0),
119 INTC_VECT(MSU_MSU, 0x0f20), INTC_VECT(MSU_MSU2, 0x0f40),
120 INTC_VECT(IRREM, 0x0f60),
121 INTC_VECT(MSUG, 0x0fa0),
122 INTC_VECT(IRDA, 0x0480),
123 INTC_VECT(TPU0, 0x04a0), INTC_VECT(TPU1, 0x04c0),
124 INTC_VECT(TPU2, 0x04e0), INTC_VECT(TPU3, 0x0500),
125 INTC_VECT(TPU4, 0x0520),
126 INTC_VECT(LCRC, 0x0540),
127 INTC_VECT(PINTCA_PINT1, 0x1000), INTC_VECT(PINTCA_PINT2, 0x1020),
128 INTC_VECT(TTI20, 0x1100),
129 INTC_VECT(MISTY, 0x1120),
130 INTC_VECT(DDM, 0x1140),
131 INTC_VECT(RWDT0, 0x1280), INTC_VECT(RWDT1, 0x12a0),
132 INTC_VECT(DMAC_1_DEI0, 0x2000), INTC_VECT(DMAC_1_DEI1, 0x2020),
133 INTC_VECT(DMAC_1_DEI2, 0x2040), INTC_VECT(DMAC_1_DEI3, 0x2060),
134 INTC_VECT(DMAC_2_DEI4, 0x2080), INTC_VECT(DMAC_2_DEI5, 0x20a0),
135 INTC_VECT(DMAC_2_DADERR, 0x20c0),
136 INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120),
137 INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160),
138 INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0),
139 INTC_VECT(DMAC2_2_DADERR, 0x21c0),
140 INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220),
141 INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260),
142 INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0),
143 INTC_VECT(DMAC3_2_DADERR, 0x22c0),
144 INTC_VECT(SHWYSTAT_RT, 0x1300), INTC_VECT(SHWYSTAT_HS, 0x1d20),
145 INTC_VECT(SHWYSTAT_COM, 0x1340),
146 INTC_VECT(ICUSB_ICUSB0, 0x1700), INTC_VECT(ICUSB_ICUSB1, 0x1720),
147 INTC_VECT(ICUDMC_ICUDMC1, 0x1780), INTC_VECT(ICUDMC_ICUDMC2, 0x17a0),
148 INTC_VECT(SPU2_SPU0, 0x1800), INTC_VECT(SPU2_SPU1, 0x1820),
149 INTC_VECT(FSI, 0x1840),
150 INTC_VECT(FMSI, 0x1860),
151 INTC_VECT(SCUV, 0x1880),
152 INTC_VECT(IPMMU_IPMMUB, 0x1900),
153 INTC_VECT(AP_ARM_CTIIRQ, 0x1980),
154 INTC_VECT(AP_ARM_DMAEXTERRIRQ, 0x19a0),
155 INTC_VECT(AP_ARM_DMAIRQ, 0x19c0),
156 INTC_VECT(AP_ARM_DMASIRQ, 0x19e0),
157 INTC_VECT(MFIS2, 0x1a00),
158 INTC_VECT(CPORTR2S, 0x1a20),
159 INTC_VECT(CMT14, 0x1a40), INTC_VECT(CMT15, 0x1a60),
160 INTC_VECT(SCIFA6, 0x1a80),
161};
162
163static struct intc_group intca_groups[] __initdata = {
164 INTC_GROUP(DMAC_1, DMAC_1_DEI0,
165 DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3),
166 INTC_GROUP(DMAC_2, DMAC_2_DEI4,
167 DMAC_2_DEI5, DMAC_2_DADERR),
168 INTC_GROUP(DMAC2_1, DMAC2_1_DEI0,
169 DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
170 INTC_GROUP(DMAC2_2, DMAC2_2_DEI4,
171 DMAC2_2_DEI5, DMAC2_2_DADERR),
172 INTC_GROUP(DMAC3_1, DMAC3_1_DEI0,
173 DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
174 INTC_GROUP(DMAC3_2, DMAC3_2_DEI4,
175 DMAC3_2_DEI5, DMAC3_2_DADERR),
176 INTC_GROUP(AP_ARM1, AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMTX),
177 INTC_GROUP(USBHS, USBHS_USHI0, USBHS_USHI1),
178 INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1),
179 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
180 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
181 INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
182 INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
183 INTC_GROUP(ICUSB, ICUSB_ICUSB0, ICUSB_ICUSB1),
184 INTC_GROUP(ICUDMC, ICUDMC_ICUDMC1, ICUDMC_ICUDMC2),
185};
186
187static struct intc_mask_reg intca_mask_registers[] __initdata = {
188 { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
189 { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
190 AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
191 { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */
192 { _2DG, CRYPT_STD, DIRC, 0,
193 DMAC_1_DEI3, DMAC_1_DEI2, DMAC_1_DEI1, DMAC_1_DEI0 } },
194 { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */
195 { PINTCA_PINT1, PINTCA_PINT2, 0, 0,
196 BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } },
197 { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */
198 { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
199 DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
200 { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */
201 { DDM, 0, 0, 0,
202 0, 0, 0, 0 } },
203 { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */
204 { KEYSC_KEY, DMAC_2_DADERR, DMAC_2_DEI5, DMAC_2_DEI4,
205 SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
206 { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */
207 { SCIFB, SCIFA5, SCIFA4, MSIOF1,
208 0, 0, MSIOF2, 0 } },
209 { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
210 { DISABLED, ENABLED, ENABLED, ENABLED,
211 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
212 { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
213 { DISABLED, ENABLED, ENABLED, ENABLED,
214 TTI20, USBDMAC_USHDMI, 0, MSUG } },
215 { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
216 { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
217 CMT2, USBHS_USHI1, USBHS_USHI0, _3DG_SGX540 } },
218 { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */
219 { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
220 0, 0, 0, 0 } },
221 { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */
222 { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1,
223 LCRC, MSU_MSU2, IRREM, MSU_MSU } },
224 { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */
225 { 0, 0, TPU0, TPU1,
226 TPU2, TPU3, TPU4, 0 } },
227 { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
228 { 0, 0, 0, 0,
229 MISTY, CMT3, RWDT1, RWDT0 } },
230 { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */
231 { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
232 0, 0, 0, 0 } },
233 { 0xe6950090, 0xe69500d0, 8, /* IMR4A3 / IMCR4A3 */
234 { ICUSB_ICUSB0, ICUSB_ICUSB1, 0, 0,
235 ICUDMC_ICUDMC1, ICUDMC_ICUDMC2, 0, 0 } },
236 { 0xe6950094, 0xe69500d4, 8, /* IMR5A3 / IMCR5A3 */
237 { SPU2_SPU0, SPU2_SPU1, FSI, FMSI,
238 SCUV, 0, 0, 0 } },
239 { 0xe6950098, 0xe69500d8, 8, /* IMR6A3 / IMCR6A3 */
240 { IPMMU_IPMMUB, 0, 0, 0,
241 AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ,
242 AP_ARM_DMAIRQ, AP_ARM_DMASIRQ } },
243 { 0xe695009c, 0xe69500dc, 8, /* IMR7A3 / IMCR7A3 */
244 { MFIS2, CPORTR2S, CMT14, CMT15,
245 SCIFA6, 0, 0, 0 } },
246};
247
248static struct intc_prio_reg intca_prio_registers[] __initdata = {
249 { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } },
250 { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
251 { 0xe6940008, 0, 16, 4, /* IPRCA */ { _2DG, CRYPT_STD,
252 CMT1_CMT11, AP_ARM1 } },
253 { 0xe694000c, 0, 16, 4, /* IPRDA */ { PINTCA_PINT1, PINTCA_PINT2,
254 CMT1_CMT12, TPU4 } },
255 { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC_1, MFI_MFIS,
256 MFI_MFIM, USBHS } },
257 { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC_2,
258 _3DG_SGX540, CMT1_CMT10 } },
259 { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
260 SCIFA2, SCIFA3 } },
261 { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBDMAC_USHDMI,
262 FLCTL, SDHI0 } },
263 { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, MSU_MSU, IIC1 } },
264 { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, MSUG, TTI20 } },
265 { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IRREM, SDHI1 } },
266 { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, TPU1, TPU2, TPU3 } },
267 { 0xe6940030, 0, 16, 4, /* IPRMA */ { MISTY, CMT3, RWDT1, RWDT0 } },
268 { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } },
269 { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, 0 } },
270 { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } },
271 { 0xe6950020, 0, 16, 4, /* IPRIA3 */ { ICUSB, 0, 0, 0 } },
272 { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { ICUDMC, 0, 0, 0 } },
273 { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
274 { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { SCUV, 0, 0, 0 } },
275 { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU_IPMMUB, 0, 0, 0 } },
276 { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
277 { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
278 CMT14, CMT15 } },
279 { 0xe694003c, 0, 16, 4, /* IPRPA3 */ { SCIFA6, 0, 0, 0 } },
280};
281
282static struct intc_desc intca_desc __initdata = {
283 .name = "sh7377-intca",
284 .force_enable = ENABLED,
285 .force_disable = DISABLED,
286 .hw = INTC_HW_DESC(intca_vectors, intca_groups,
287 intca_mask_registers, intca_prio_registers,
288 NULL, NULL),
289};
290
291INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
292 INTC_VECT, "sh7377-intca-irq-pins");
293
294/* this macro ignore entry which is also in INTCA */
295#define __IGNORE(a...)
296#define __IGNORE0(a...) 0
297
298enum {
299 UNUSED_INTCS = 0,
300
301 INTCS,
302
303 /* interrupt sources INTCS */
304 VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3,
305 RTDMAC1_1_DEI0, RTDMAC1_1_DEI1, RTDMAC1_1_DEI2, RTDMAC1_1_DEI3,
306 CEU,
307 BEU_BEU0, BEU_BEU1, BEU_BEU2,
308 __IGNORE(MFI)
309 __IGNORE(BBIF2)
310 VPU,
311 TSIF1,
312 __IGNORE(SGX540)
313 _2DDMAC,
314 IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
315 IPMMU_IPMMUR, IPMMU_IPMMUR2,
316 RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR,
317 __IGNORE(KEYSC)
318 __IGNORE(TTI20)
319 __IGNORE(MSIOF)
320 IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
321 TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
322 CMT0,
323 TSIF0,
324 __IGNORE(CMT2)
325 LMB,
326 __IGNORE(MSUG)
327 __IGNORE(MSU_MSU, MSU_MSU2)
328 __IGNORE(CTI)
329 MVI3,
330 __IGNORE(RWDT0)
331 __IGNORE(RWDT1)
332 ICB,
333 PEP,
334 ASA,
335 __IGNORE(_2DG)
336 HQE,
337 JPU,
338 LCDC0,
339 __IGNORE(LCRC)
340 RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
341 RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR,
342 FRC,
343 LCDC1,
344 CSIRX,
345 DSITX_DSITX0, DSITX_DSITX1,
346 __IGNORE(SPU2_SPU0, SPU2_SPU1)
347 __IGNORE(FSI)
348 __IGNORE(FMSI)
349 __IGNORE(SCUV)
350 TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12,
351 TSIF2,
352 CMT4,
353 __IGNORE(MFIS2)
354 CPORTS2R,
355
356 /* interrupt groups INTCS */
357 RTDMAC1_1, RTDMAC1_2, VEU, BEU, IIC0, __IGNORE(MSU) IPMMU,
358 IIC2, RTDMAC2_1, RTDMAC2_2, DSITX, __IGNORE(SPU2) TMU1,
359};
360
361#define INTCS_INTVECT 0x0F80
362static struct intc_vect intcs_vectors[] __initdata = {
363 INTCS_VECT(VEU_VEU0, 0x0700), INTCS_VECT(VEU_VEU1, 0x0720),
364 INTCS_VECT(VEU_VEU2, 0x0740), INTCS_VECT(VEU_VEU3, 0x0760),
365 INTCS_VECT(RTDMAC1_1_DEI0, 0x0800), INTCS_VECT(RTDMAC1_1_DEI1, 0x0820),
366 INTCS_VECT(RTDMAC1_1_DEI2, 0x0840), INTCS_VECT(RTDMAC1_1_DEI3, 0x0860),
367 INTCS_VECT(CEU, 0x0880),
368 INTCS_VECT(BEU_BEU0, 0x08A0),
369 INTCS_VECT(BEU_BEU1, 0x08C0),
370 INTCS_VECT(BEU_BEU2, 0x08E0),
371 __IGNORE(INTCS_VECT(MFI, 0x0900))
372 __IGNORE(INTCS_VECT(BBIF2, 0x0960))
373 INTCS_VECT(VPU, 0x0980),
374 INTCS_VECT(TSIF1, 0x09A0),
375 __IGNORE(INTCS_VECT(SGX540, 0x09E0))
376 INTCS_VECT(_2DDMAC, 0x0A00),
377 INTCS_VECT(IIC2_ALI2, 0x0A80), INTCS_VECT(IIC2_TACKI2, 0x0AA0),
378 INTCS_VECT(IIC2_WAITI2, 0x0AC0), INTCS_VECT(IIC2_DTEI2, 0x0AE0),
379 INTCS_VECT(IPMMU_IPMMUR, 0x0B00), INTCS_VECT(IPMMU_IPMMUR2, 0x0B20),
380 INTCS_VECT(RTDMAC1_2_DEI4, 0x0B80),
381 INTCS_VECT(RTDMAC1_2_DEI5, 0x0BA0),
382 INTCS_VECT(RTDMAC1_2_DADERR, 0x0BC0),
383 __IGNORE(INTCS_VECT(KEYSC 0x0BE0))
384 __IGNORE(INTCS_VECT(TTI20, 0x0C80))
385 __IGNORE(INTCS_VECT(MSIOF, 0x0D20))
386 INTCS_VECT(IIC0_ALI0, 0x0E00), INTCS_VECT(IIC0_TACKI0, 0x0E20),
387 INTCS_VECT(IIC0_WAITI0, 0x0E40), INTCS_VECT(IIC0_DTEI0, 0x0E60),
388 INTCS_VECT(TMU_TUNI0, 0x0E80),
389 INTCS_VECT(TMU_TUNI1, 0x0EA0),
390 INTCS_VECT(TMU_TUNI2, 0x0EC0),
391 INTCS_VECT(CMT0, 0x0F00),
392 INTCS_VECT(TSIF0, 0x0F20),
393 __IGNORE(INTCS_VECT(CMT2, 0x0F40))
394 INTCS_VECT(LMB, 0x0F60),
395 __IGNORE(INTCS_VECT(MSUG, 0x0F80))
396 __IGNORE(INTCS_VECT(MSU_MSU, 0x0FA0))
397 __IGNORE(INTCS_VECT(MSU_MSU2, 0x0FC0))
398 __IGNORE(INTCS_VECT(CTI, 0x0400))
399 INTCS_VECT(MVI3, 0x0420),
400 __IGNORE(INTCS_VECT(RWDT0, 0x0440))
401 __IGNORE(INTCS_VECT(RWDT1, 0x0460))
402 INTCS_VECT(ICB, 0x0480),
403 INTCS_VECT(PEP, 0x04A0),
404 INTCS_VECT(ASA, 0x04C0),
405 __IGNORE(INTCS_VECT(_2DG, 0x04E0))
406 INTCS_VECT(HQE, 0x0540),
407 INTCS_VECT(JPU, 0x0560),
408 INTCS_VECT(LCDC0, 0x0580),
409 __IGNORE(INTCS_VECT(LCRC, 0x05A0))
410 INTCS_VECT(RTDMAC2_1_DEI0, 0x1300), INTCS_VECT(RTDMAC2_1_DEI1, 0x1320),
411 INTCS_VECT(RTDMAC2_1_DEI2, 0x1340), INTCS_VECT(RTDMAC2_1_DEI3, 0x1360),
412 INTCS_VECT(RTDMAC2_2_DEI4, 0x1380), INTCS_VECT(RTDMAC2_2_DEI5, 0x13A0),
413 INTCS_VECT(RTDMAC2_2_DADERR, 0x13C0),
414 INTCS_VECT(FRC, 0x1700),
415 INTCS_VECT(LCDC1, 0x1780),
416 INTCS_VECT(CSIRX, 0x17A0),
417 INTCS_VECT(DSITX_DSITX0, 0x17C0), INTCS_VECT(DSITX_DSITX1, 0x17E0),
418 __IGNORE(INTCS_VECT(SPU2_SPU0, 0x1800))
419 __IGNORE(INTCS_VECT(SPU2_SPU1, 0x1820))
420 __IGNORE(INTCS_VECT(FSI, 0x1840))
421 __IGNORE(INTCS_VECT(FMSI, 0x1860))
422 __IGNORE(INTCS_VECT(SCUV, 0x1880))
423 INTCS_VECT(TMU1_TUNI10, 0x1900), INTCS_VECT(TMU1_TUNI11, 0x1920),
424 INTCS_VECT(TMU1_TUNI12, 0x1940),
425 INTCS_VECT(TSIF2, 0x1960),
426 INTCS_VECT(CMT4, 0x1980),
427 __IGNORE(INTCS_VECT(MFIS2, 0x1A00))
428 INTCS_VECT(CPORTS2R, 0x1A20),
429
430 INTC_VECT(INTCS, INTCS_INTVECT),
431};
432
433static struct intc_group intcs_groups[] __initdata = {
434 INTC_GROUP(RTDMAC1_1,
435 RTDMAC1_1_DEI0, RTDMAC1_1_DEI1,
436 RTDMAC1_1_DEI2, RTDMAC1_1_DEI3),
437 INTC_GROUP(RTDMAC1_2,
438 RTDMAC1_2_DEI4, RTDMAC1_2_DEI5, RTDMAC1_2_DADERR),
439 INTC_GROUP(VEU, VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3),
440 INTC_GROUP(BEU, BEU_BEU0, BEU_BEU1, BEU_BEU2),
441 INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
442 __IGNORE(INTC_GROUP(MSU, MSU_MSU, MSU_MSU2))
443 INTC_GROUP(IPMMU, IPMMU_IPMMUR, IPMMU_IPMMUR2),
444 INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
445 INTC_GROUP(RTDMAC2_1,
446 RTDMAC2_1_DEI0, RTDMAC2_1_DEI1,
447 RTDMAC2_1_DEI2, RTDMAC2_1_DEI3),
448 INTC_GROUP(RTDMAC2_2, RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR),
449 INTC_GROUP(DSITX, DSITX_DSITX0, DSITX_DSITX1),
450 __IGNORE(INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1))
451 INTC_GROUP(TMU1, TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12),
452};
453
454static struct intc_mask_reg intcs_mask_registers[] __initdata = {
455 { 0xE6940184, 0xE69401C4, 8, /* IMR1AS / IMCR1AS */
456 { BEU_BEU2, BEU_BEU1, BEU_BEU0, CEU,
457 VEU_VEU3, VEU_VEU2, VEU_VEU1, VEU_VEU0 } },
458 { 0xE6940188, 0xE69401C8, 8, /* IMR2AS / IMCR2AS */
459 { 0, 0, 0, VPU,
460 __IGNORE0(BBIF2), 0, 0, __IGNORE0(MFI) } },
461 { 0xE694018C, 0xE69401CC, 8, /* IMR3AS / IMCR3AS */
462 { 0, 0, 0, _2DDMAC,
463 __IGNORE0(_2DG), ASA, PEP, ICB } },
464 { 0xE6940190, 0xE69401D0, 8, /* IMR4AS / IMCR4AS */
465 { 0, 0, MVI3, __IGNORE0(CTI),
466 JPU, HQE, __IGNORE0(LCRC), LCDC0 } },
467 { 0xE6940194, 0xE69401D4, 8, /* IMR5AS / IMCR5AS */
468 { __IGNORE0(KEYSC), RTDMAC1_2_DADERR, RTDMAC1_2_DEI5, RTDMAC1_2_DEI4,
469 RTDMAC1_1_DEI3, RTDMAC1_1_DEI2, RTDMAC1_1_DEI1, RTDMAC1_1_DEI0 } },
470 __IGNORE({ 0xE6940198, 0xE69401D8, 8, /* IMR6AS / IMCR6AS */
471 { 0, 0, MSIOF, 0,
472 SGX540, 0, TTI20, 0 } })
473 { 0xE694019C, 0xE69401DC, 8, /* IMR7AS / IMCR7AS */
474 { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
475 0, 0, 0, 0 } },
476 __IGNORE({ 0xE69401A0, 0xE69401E0, 8, /* IMR8AS / IMCR8AS */
477 { 0, 0, 0, 0,
478 0, MSU_MSU, MSU_MSU2, MSUG } })
479 { 0xE69401A4, 0xE69401E4, 8, /* IMR9AS / IMCR9AS */
480 { __IGNORE0(RWDT1), __IGNORE0(RWDT0), __IGNORE0(CMT2), CMT0,
481 IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
482 { 0xE69401A8, 0xE69401E8, 8, /* IMR10AS / IMCR10AS */
483 { 0, 0, IPMMU_IPMMUR, IPMMU_IPMMUR2,
484 0, 0, 0, 0 } },
485 { 0xE69401AC, 0xE69401EC, 8, /* IMR11AS / IMCR11AS */
486 { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
487 0, TSIF1, LMB, TSIF0 } },
488 { 0xE6950180, 0xE69501C0, 8, /* IMR0AS3 / IMCR0AS3 */
489 { RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
490 RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR, 0 } },
491 { 0xE6950190, 0xE69501D0, 8, /* IMR4AS3 / IMCR4AS3 */
492 { FRC, 0, 0, 0,
493 LCDC1, CSIRX, DSITX_DSITX0, DSITX_DSITX1 } },
494 __IGNORE({ 0xE6950194, 0xE69501D4, 8, /* IMR5AS3 / IMCR5AS3 */
495 {SPU2_SPU0, SPU2_SPU1, FSI, FMSI,
496 SCUV, 0, 0, 0 } })
497 { 0xE6950198, 0xE69501D8, 8, /* IMR6AS3 / IMCR6AS3 */
498 { TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, TSIF2,
499 CMT4, 0, 0, 0 } },
500 { 0xE695019C, 0xE69501DC, 8, /* IMR7AS3 / IMCR7AS3 */
501 { __IGNORE0(MFIS2), CPORTS2R, 0, 0,
502 0, 0, 0, 0 } },
503 { 0xFFD20104, 0, 16, /* INTAMASK */
504 { 0, 0, 0, 0, 0, 0, 0, 0,
505 0, 0, 0, 0, 0, 0, 0, INTCS } }
506};
507
508static struct intc_prio_reg intcs_prio_registers[] __initdata = {
509 /* IPRAS */
510 { 0xFFD20000, 0, 16, 4, { __IGNORE0(CTI), MVI3, _2DDMAC, ICB } },
511 /* IPRBS */
512 { 0xFFD20004, 0, 16, 4, { JPU, LCDC0, 0, __IGNORE0(LCRC) } },
513 /* IPRCS */
514 __IGNORE({ 0xFFD20008, 0, 16, 4, { BBIF2, 0, 0, 0 } })
515 /* IPRES */
516 { 0xFFD20010, 0, 16, 4, { RTDMAC1_1, CEU, __IGNORE0(MFI), VPU } },
517 /* IPRFS */
518 { 0xFFD20014, 0, 16, 4,
519 { __IGNORE0(KEYSC), RTDMAC1_2, __IGNORE0(CMT2), CMT0 } },
520 /* IPRGS */
521 { 0xFFD20018, 0, 16, 4, { TMU_TUNI0, TMU_TUNI1, TMU_TUNI2, TSIF1 } },
522 /* IPRHS */
523 { 0xFFD2001C, 0, 16, 4, { __IGNORE0(TTI20), 0, VEU, BEU } },
524 /* IPRIS */
525 { 0xFFD20020, 0, 16, 4, { 0, __IGNORE0(MSIOF), TSIF0, IIC0 } },
526 /* IPRJS */
527 __IGNORE({ 0xFFD20024, 0, 16, 4, { 0, SGX540, MSUG, MSU } })
528 /* IPRKS */
529 { 0xFFD20028, 0, 16, 4, { __IGNORE0(_2DG), ASA, LMB, PEP } },
530 /* IPRLS */
531 { 0xFFD2002C, 0, 16, 4, { IPMMU, 0, 0, HQE } },
532 /* IPRMS */
533 { 0xFFD20030, 0, 16, 4,
534 { IIC2, 0, __IGNORE0(RWDT1), __IGNORE0(RWDT0) } },
535 /* IPRAS3 */
536 { 0xFFD50000, 0, 16, 4, { RTDMAC2_1, 0, 0, 0 } },
537 /* IPRBS3 */
538 { 0xFFD50004, 0, 16, 4, { RTDMAC2_2, 0, 0, 0 } },
539 /* IPRIS3 */
540 { 0xFFD50020, 0, 16, 4, { FRC, 0, 0, 0 } },
541 /* IPRJS3 */
542 { 0xFFD50024, 0, 16, 4, { LCDC1, CSIRX, DSITX, 0 } },
543 /* IPRKS3 */
544 __IGNORE({ 0xFFD50028, 0, 16, 4, { SPU2, 0, FSI, FMSI } })
545 /* IPRLS3 */
546 __IGNORE({ 0xFFD5002C, 0, 16, 4, { SCUV, 0, 0, 0 } })
547 /* IPRMS3 */
548 { 0xFFD50030, 0, 16, 4, { TMU1, 0, 0, TSIF2 } },
549 /* IPRNS3 */
550 { 0xFFD50034, 0, 16, 4, { CMT4, 0, 0, 0 } },
551 /* IPROS3 */
552 { 0xFFD50038, 0, 16, 4, { __IGNORE0(MFIS2), CPORTS2R, 0, 0 } },
553};
554
555static struct resource intcs_resources[] __initdata = {
556 [0] = {
557 .start = 0xffd20000,
558 .end = 0xffd500ff,
559 .flags = IORESOURCE_MEM,
560 }
561};
562
563static struct intc_desc intcs_desc __initdata = {
564 .name = "sh7377-intcs",
565 .resource = intcs_resources,
566 .num_resources = ARRAY_SIZE(intcs_resources),
567 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups,
568 intcs_mask_registers, intcs_prio_registers,
569 NULL, NULL),
570};
571
572static void intcs_demux(unsigned int irq, struct irq_desc *desc)
573{
574 void __iomem *reg = (void *)irq_get_handler_data(irq);
575 unsigned int evtcodeas = ioread32(reg);
576
577 generic_handle_irq(intcs_evt2irq(evtcodeas));
578}
579
580#define INTEVTSA 0xFFD20100
581void __init sh7377_init_irq(void)
582{
583 void __iomem *intevtsa = ioremap_nocache(INTEVTSA, PAGE_SIZE);
584
585 register_intc_controller(&intca_desc);
586 register_intc_controller(&intca_irq_pins_desc);
587 register_intc_controller(&intcs_desc);
588
589 /* demux using INTEVTSA */
590 irq_set_handler_data(evt2irq(INTCS_INTVECT), (void *)intevtsa);
591 irq_set_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux);
592}
diff --git a/arch/arm/mach-shmobile/pfc-r8a7779.c b/arch/arm/mach-shmobile/pfc-r8a7779.c
index cbc26ba2a0a2..9513234d322b 100644
--- a/arch/arm/mach-shmobile/pfc-r8a7779.c
+++ b/arch/arm/mach-shmobile/pfc-r8a7779.c
@@ -140,7 +140,7 @@ enum {
140 FN_IP7_3_2, FN_IP7_6_4, FN_IP7_9_7, FN_IP7_12_10, 140 FN_IP7_3_2, FN_IP7_6_4, FN_IP7_9_7, FN_IP7_12_10,
141 FN_IP7_14_13, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12, 141 FN_IP7_14_13, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
142 FN_IP1_28_25, FN_IP2_3_0, FN_IP8_3_0, FN_IP8_7_4, 142 FN_IP1_28_25, FN_IP2_3_0, FN_IP8_3_0, FN_IP8_7_4,
143 FN_IP8_11_8, FN_IP8_15_12, FN_PENC0, FN_PENC1, 143 FN_IP8_11_8, FN_IP8_15_12, FN_USB_PENC0, FN_USB_PENC1,
144 FN_IP0_2_0, FN_IP8_17_16, FN_IP8_18, FN_IP8_19, 144 FN_IP0_2_0, FN_IP8_17_16, FN_IP8_18, FN_IP8_19,
145 145
146 /* GPSR5 */ 146 /* GPSR5 */
@@ -176,7 +176,7 @@ enum {
176 FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3, 176 FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
177 FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2, 177 FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
178 FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C, 178 FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
179 FN_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0, 179 FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
180 FN_SCIF_CLK, FN_TCLK0_C, 180 FN_SCIF_CLK, FN_TCLK0_C,
181 181
182 /* IPSR1 */ 182 /* IPSR1 */
@@ -447,7 +447,7 @@ enum {
447 A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK, 447 A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK,
448 BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK, 448 BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK,
449 ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK, 449 ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK,
450 PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK, 450 USB_PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
451 SCIF_CLK_MARK, TCLK0_C_MARK, 451 SCIF_CLK_MARK, TCLK0_C_MARK,
452 452
453 EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK, 453 EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK,
@@ -658,7 +658,7 @@ static pinmux_enum_t pinmux_data[] = {
658 PINMUX_DATA(A18_MARK, FN_A18), 658 PINMUX_DATA(A18_MARK, FN_A18),
659 PINMUX_DATA(A19_MARK, FN_A19), 659 PINMUX_DATA(A19_MARK, FN_A19),
660 660
661 PINMUX_IPSR_DATA(IP0_2_0, PENC2), 661 PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2),
662 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0), 662 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0),
663 PINMUX_IPSR_DATA(IP0_2_0, PWM1), 663 PINMUX_IPSR_DATA(IP0_2_0, PWM1),
664 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, PWMFSW0, SEL_PWMFSW_0), 664 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, PWMFSW0, SEL_PWMFSW_0),
@@ -1456,7 +1456,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
1456 GPIO_FN(A19), 1456 GPIO_FN(A19),
1457 1457
1458 /* IPSR0 */ 1458 /* IPSR0 */
1459 GPIO_FN(PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0), 1459 GPIO_FN(USB_PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
1460 GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS), GPIO_FN(SD1_DAT2), 1460 GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS), GPIO_FN(SD1_DAT2),
1461 GPIO_FN(MMC0_D2), GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF), 1461 GPIO_FN(MMC0_D2), GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF),
1462 GPIO_FN(HCTS1), GPIO_FN(TX4_C), GPIO_FN(A0), GPIO_FN(SD1_DAT3), 1462 GPIO_FN(HCTS1), GPIO_FN(TX4_C), GPIO_FN(A0), GPIO_FN(SD1_DAT3),
@@ -1865,8 +1865,8 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
1865 GP_4_30_FN, FN_IP8_18, 1865 GP_4_30_FN, FN_IP8_18,
1866 GP_4_29_FN, FN_IP8_17_16, 1866 GP_4_29_FN, FN_IP8_17_16,
1867 GP_4_28_FN, FN_IP0_2_0, 1867 GP_4_28_FN, FN_IP0_2_0,
1868 GP_4_27_FN, FN_PENC1, 1868 GP_4_27_FN, FN_USB_PENC1,
1869 GP_4_26_FN, FN_PENC0, 1869 GP_4_26_FN, FN_USB_PENC0,
1870 GP_4_25_FN, FN_IP8_15_12, 1870 GP_4_25_FN, FN_IP8_15_12,
1871 GP_4_24_FN, FN_IP8_11_8, 1871 GP_4_24_FN, FN_IP8_11_8,
1872 GP_4_23_FN, FN_IP8_7_4, 1872 GP_4_23_FN, FN_IP8_7_4,
@@ -1981,7 +1981,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
1981 FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2, 1981 FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
1982 FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C, 1982 FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
1983 /* IP0_2_0 [3] */ 1983 /* IP0_2_0 [3] */
1984 FN_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0, 1984 FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
1985 FN_SCIF_CLK, FN_TCLK0_C, 0, 0 } 1985 FN_SCIF_CLK, FN_TCLK0_C, 0, 0 }
1986 }, 1986 },
1987 { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32, 1987 { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
diff --git a/arch/arm/mach-shmobile/pfc-sh7367.c b/arch/arm/mach-shmobile/pfc-sh7367.c
deleted file mode 100644
index c0c137f39052..000000000000
--- a/arch/arm/mach-shmobile/pfc-sh7367.c
+++ /dev/null
@@ -1,1727 +0,0 @@
1/*
2 * sh7367 processor support - PFC hardware block
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19#include <linux/init.h>
20#include <linux/kernel.h>
21#include <linux/sh_pfc.h>
22#include <mach/sh7367.h>
23
24#define CPU_ALL_PORT(fn, pfx, sfx) \
25 PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
26 PORT_10(fn, pfx##10, sfx), PORT_90(fn, pfx##1, sfx), \
27 PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx), \
28 PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx), \
29 PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx), \
30 PORT_10(fn, pfx##26, sfx), PORT_1(fn, pfx##270, sfx), \
31 PORT_1(fn, pfx##271, sfx), PORT_1(fn, pfx##272, sfx)
32
33enum {
34 PINMUX_RESERVED = 0,
35
36 PINMUX_DATA_BEGIN,
37 PORT_ALL(DATA), /* PORT0_DATA -> PORT272_DATA */
38 PINMUX_DATA_END,
39
40 PINMUX_INPUT_BEGIN,
41 PORT_ALL(IN), /* PORT0_IN -> PORT272_IN */
42 PINMUX_INPUT_END,
43
44 PINMUX_INPUT_PULLUP_BEGIN,
45 PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT272_IN_PU */
46 PINMUX_INPUT_PULLUP_END,
47
48 PINMUX_INPUT_PULLDOWN_BEGIN,
49 PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT272_IN_PD */
50 PINMUX_INPUT_PULLDOWN_END,
51
52 PINMUX_OUTPUT_BEGIN,
53 PORT_ALL(OUT), /* PORT0_OUT -> PORT272_OUT */
54 PINMUX_OUTPUT_END,
55
56 PINMUX_FUNCTION_BEGIN,
57 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT272_FN_IN */
58 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT272_FN_OUT */
59 PORT_ALL(FN0), /* PORT0_FN0 -> PORT272_FN0 */
60 PORT_ALL(FN1), /* PORT0_FN1 -> PORT272_FN1 */
61 PORT_ALL(FN2), /* PORT0_FN2 -> PORT272_FN2 */
62 PORT_ALL(FN3), /* PORT0_FN3 -> PORT272_FN3 */
63 PORT_ALL(FN4), /* PORT0_FN4 -> PORT272_FN4 */
64 PORT_ALL(FN5), /* PORT0_FN5 -> PORT272_FN5 */
65 PORT_ALL(FN6), /* PORT0_FN6 -> PORT272_FN6 */
66 PORT_ALL(FN7), /* PORT0_FN7 -> PORT272_FN7 */
67
68 MSELBCR_MSEL2_1, MSELBCR_MSEL2_0,
69 PINMUX_FUNCTION_END,
70
71 PINMUX_MARK_BEGIN,
72 /* Special Pull-up / Pull-down Functions */
73 PORT48_KEYIN0_PU_MARK, PORT49_KEYIN1_PU_MARK,
74 PORT50_KEYIN2_PU_MARK, PORT55_KEYIN3_PU_MARK,
75 PORT56_KEYIN4_PU_MARK, PORT57_KEYIN5_PU_MARK,
76 PORT58_KEYIN6_PU_MARK,
77
78 /* 49-1 */
79 VBUS0_MARK, CPORT0_MARK, CPORT1_MARK, CPORT2_MARK,
80 CPORT3_MARK, CPORT4_MARK, CPORT5_MARK, CPORT6_MARK,
81 CPORT7_MARK, CPORT8_MARK, CPORT9_MARK, CPORT10_MARK,
82 CPORT11_MARK, SIN2_MARK, CPORT12_MARK, XCTS2_MARK,
83 CPORT13_MARK, RFSPO4_MARK, CPORT14_MARK, RFSPO5_MARK,
84 CPORT15_MARK, CPORT16_MARK, CPORT17_MARK, SOUT2_MARK,
85 CPORT18_MARK, XRTS2_MARK, CPORT19_MARK, CPORT20_MARK,
86 RFSPO6_MARK, CPORT21_MARK, STATUS0_MARK, CPORT22_MARK,
87 STATUS1_MARK, CPORT23_MARK, STATUS2_MARK, RFSPO7_MARK,
88 MPORT0_MARK, MPORT1_MARK, B_SYNLD1_MARK, B_SYNLD2_MARK,
89 XMAINPS_MARK, XDIVPS_MARK, XIDRST_MARK, IDCLK_MARK,
90 IDIO_MARK, SOUT1_MARK, SCIFA4_TXD_MARK,
91 M02_BERDAT_MARK, SIN1_MARK, SCIFA4_RXD_MARK, XWUP_MARK,
92 XRTS1_MARK, SCIFA4_RTS_MARK, M03_BERCLK_MARK,
93 XCTS1_MARK, SCIFA4_CTS_MARK,
94
95 /* 49-2 */
96 HSU_IQ_AGC6_MARK, MFG2_IN2_MARK, MSIOF2_MCK0_MARK,
97 HSU_IQ_AGC5_MARK, MFG2_IN1_MARK, MSIOF2_MCK1_MARK,
98 HSU_IQ_AGC4_MARK, MSIOF2_RSYNC_MARK,
99 HSU_IQ_AGC3_MARK, MFG2_OUT1_MARK, MSIOF2_RSCK_MARK,
100 HSU_IQ_AGC2_MARK, PORT42_KEYOUT0_MARK,
101 HSU_IQ_AGC1_MARK, PORT43_KEYOUT1_MARK,
102 HSU_IQ_AGC0_MARK, PORT44_KEYOUT2_MARK,
103 HSU_IQ_AGC_ST_MARK, PORT45_KEYOUT3_MARK,
104 HSU_IQ_PDO_MARK, PORT46_KEYOUT4_MARK,
105 HSU_IQ_PYO_MARK, PORT47_KEYOUT5_MARK,
106 HSU_EN_TXMUX_G3MO_MARK, PORT48_KEYIN0_MARK,
107 HSU_I_TXMUX_G3MO_MARK, PORT49_KEYIN1_MARK,
108 HSU_Q_TXMUX_G3MO_MARK, PORT50_KEYIN2_MARK,
109 HSU_SYO_MARK, PORT51_MSIOF2_TSYNC_MARK,
110 HSU_SDO_MARK, PORT52_MSIOF2_TSCK_MARK,
111 HSU_TGTTI_G3MO_MARK, PORT53_MSIOF2_TXD_MARK,
112 B_TIME_STAMP_MARK, PORT54_MSIOF2_RXD_MARK,
113 HSU_SDI_MARK, PORT55_KEYIN3_MARK,
114 HSU_SCO_MARK, PORT56_KEYIN4_MARK,
115 HSU_DREQ_MARK, PORT57_KEYIN5_MARK,
116 HSU_DACK_MARK, PORT58_KEYIN6_MARK,
117 HSU_CLK61M_MARK, PORT59_MSIOF2_SS1_MARK,
118 HSU_XRST_MARK, PORT60_MSIOF2_SS2_MARK,
119 PCMCLKO_MARK, SYNC8KO_MARK, DNPCM_A_MARK, UPPCM_A_MARK,
120 XTALB1L_MARK,
121 GPS_AGC1_MARK, SCIFA0_RTS_MARK,
122 GPS_AGC2_MARK, SCIFA0_SCK_MARK,
123 GPS_AGC3_MARK, SCIFA0_TXD_MARK,
124 GPS_AGC4_MARK, SCIFA0_RXD_MARK,
125 GPS_PWRD_MARK, SCIFA0_CTS_MARK,
126 GPS_IM_MARK, GPS_IS_MARK, GPS_QM_MARK, GPS_QS_MARK,
127 SIUBOMC_MARK, TPU2TO0_MARK,
128 SIUCKB_MARK, TPU2TO1_MARK,
129 SIUBOLR_MARK, BBIF2_TSYNC_MARK, TPU2TO2_MARK,
130 SIUBOBT_MARK, BBIF2_TSCK_MARK, TPU2TO3_MARK,
131 SIUBOSLD_MARK, BBIF2_TXD_MARK, TPU3TO0_MARK,
132 SIUBILR_MARK, TPU3TO1_MARK,
133 SIUBIBT_MARK, TPU3TO2_MARK,
134 SIUBISLD_MARK, TPU3TO3_MARK,
135 NMI_MARK, TPU4TO0_MARK,
136 DNPCM_M_MARK, TPU4TO1_MARK, TPU4TO2_MARK, TPU4TO3_MARK,
137 IRQ_TMPB_MARK,
138 PWEN_MARK, MFG1_OUT1_MARK,
139 OVCN_MARK, MFG1_IN1_MARK,
140 OVCN2_MARK, MFG1_IN2_MARK,
141
142 /* 49-3 */
143 RFSPO1_MARK, RFSPO2_MARK, RFSPO3_MARK, PORT93_VIO_CKO2_MARK,
144 USBTERM_MARK, EXTLP_MARK, IDIN_MARK,
145 SCIFA5_CTS_MARK, MFG0_IN1_MARK,
146 SCIFA5_RTS_MARK, MFG0_IN2_MARK,
147 SCIFA5_RXD_MARK,
148 SCIFA5_TXD_MARK,
149 SCIFA5_SCK_MARK, MFG0_OUT1_MARK,
150 A0_EA0_MARK, BS_MARK,
151 A14_EA14_MARK, PORT102_KEYOUT0_MARK,
152 A15_EA15_MARK, PORT103_KEYOUT1_MARK, DV_CLKOL_MARK,
153 A16_EA16_MARK, PORT104_KEYOUT2_MARK,
154 DV_VSYNCL_MARK, MSIOF0_SS1_MARK,
155 A17_EA17_MARK, PORT105_KEYOUT3_MARK,
156 DV_HSYNCL_MARK, MSIOF0_TSYNC_MARK,
157 A18_EA18_MARK, PORT106_KEYOUT4_MARK,
158 DV_DL0_MARK, MSIOF0_TSCK_MARK,
159 A19_EA19_MARK, PORT107_KEYOUT5_MARK,
160 DV_DL1_MARK, MSIOF0_TXD_MARK,
161 A20_EA20_MARK, PORT108_KEYIN0_MARK,
162 DV_DL2_MARK, MSIOF0_RSCK_MARK,
163 A21_EA21_MARK, PORT109_KEYIN1_MARK,
164 DV_DL3_MARK, MSIOF0_RSYNC_MARK,
165 A22_EA22_MARK, PORT110_KEYIN2_MARK,
166 DV_DL4_MARK, MSIOF0_MCK0_MARK,
167 A23_EA23_MARK, PORT111_KEYIN3_MARK,
168 DV_DL5_MARK, MSIOF0_MCK1_MARK,
169 A24_EA24_MARK, PORT112_KEYIN4_MARK,
170 DV_DL6_MARK, MSIOF0_RXD_MARK,
171 A25_EA25_MARK, PORT113_KEYIN5_MARK,
172 DV_DL7_MARK, MSIOF0_SS2_MARK,
173 A26_MARK, PORT113_KEYIN6_MARK, DV_CLKIL_MARK,
174 D0_ED0_NAF0_MARK, D1_ED1_NAF1_MARK, D2_ED2_NAF2_MARK,
175 D3_ED3_NAF3_MARK, D4_ED4_NAF4_MARK, D5_ED5_NAF5_MARK,
176 D6_ED6_NAF6_MARK, D7_ED7_NAF7_MARK, D8_ED8_NAF8_MARK,
177 D9_ED9_NAF9_MARK, D10_ED10_NAF10_MARK, D11_ED11_NAF11_MARK,
178 D12_ED12_NAF12_MARK, D13_ED13_NAF13_MARK,
179 D14_ED14_NAF14_MARK, D15_ED15_NAF15_MARK,
180 CS4_MARK, CS5A_MARK, CS5B_MARK, FCE1_MARK,
181 CS6B_MARK, XCS2_MARK, FCE0_MARK, CS6A_MARK,
182 DACK0_MARK, WAIT_MARK, DREQ0_MARK, RD_XRD_MARK,
183 A27_MARK, RDWR_XWE_MARK, WE0_XWR0_FWE_MARK,
184 WE1_XWR1_MARK, FRB_MARK, CKO_MARK,
185 NBRSTOUT_MARK, NBRST_MARK,
186
187 /* 49-4 */
188 RFSPO0_MARK, PORT146_VIO_CKO2_MARK, TSTMD_MARK,
189 VIO_VD_MARK, VIO_HD_MARK,
190 VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK,
191 VIO_D3_MARK, VIO_D4_MARK, VIO_D5_MARK,
192 VIO_D6_MARK, VIO_D7_MARK, VIO_D8_MARK,
193 VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK,
194 VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK,
195 VIO_D15_MARK, VIO_CLK_MARK, VIO_FIELD_MARK,
196 VIO_CKO_MARK,
197 MFG3_IN1_MARK, MFG3_IN2_MARK,
198 M9_SLCD_A01_MARK, MFG3_OUT1_MARK, TPU0TO0_MARK,
199 M10_SLCD_CK1_MARK, MFG4_IN1_MARK, TPU0TO1_MARK,
200 M11_SLCD_SO1_MARK, MFG4_IN2_MARK, TPU0TO2_MARK,
201 M12_SLCD_CE1_MARK, MFG4_OUT1_MARK, TPU0TO3_MARK,
202 LCDD0_MARK, PORT175_KEYOUT0_MARK, DV_D0_MARK,
203 SIUCKA_MARK, MFG0_OUT2_MARK,
204 LCDD1_MARK, PORT176_KEYOUT1_MARK, DV_D1_MARK,
205 SIUAOLR_MARK, BBIF2_TSYNC1_MARK,
206 LCDD2_MARK, PORT177_KEYOUT2_MARK, DV_D2_MARK,
207 SIUAOBT_MARK, BBIF2_TSCK1_MARK,
208 LCDD3_MARK, PORT178_KEYOUT3_MARK, DV_D3_MARK,
209 SIUAOSLD_MARK, BBIF2_TXD1_MARK,
210 LCDD4_MARK, PORT179_KEYOUT4_MARK, DV_D4_MARK,
211 SIUAISPD_MARK, MFG1_OUT2_MARK,
212 LCDD5_MARK, PORT180_KEYOUT5_MARK, DV_D5_MARK,
213 SIUAILR_MARK, MFG2_OUT2_MARK,
214 LCDD6_MARK, DV_D6_MARK,
215 SIUAIBT_MARK, MFG3_OUT2_MARK, XWR2_MARK,
216 LCDD7_MARK, DV_D7_MARK,
217 SIUAISLD_MARK, MFG4_OUT2_MARK, XWR3_MARK,
218 LCDD8_MARK, DV_D8_MARK, D16_MARK, ED16_MARK,
219 LCDD9_MARK, DV_D9_MARK, D17_MARK, ED17_MARK,
220 LCDD10_MARK, DV_D10_MARK, D18_MARK, ED18_MARK,
221 LCDD11_MARK, DV_D11_MARK, D19_MARK, ED19_MARK,
222 LCDD12_MARK, DV_D12_MARK, D20_MARK, ED20_MARK,
223 LCDD13_MARK, DV_D13_MARK, D21_MARK, ED21_MARK,
224 LCDD14_MARK, DV_D14_MARK, D22_MARK, ED22_MARK,
225 LCDD15_MARK, DV_D15_MARK, D23_MARK, ED23_MARK,
226 LCDD16_MARK, DV_HSYNC_MARK, D24_MARK, ED24_MARK,
227 LCDD17_MARK, DV_VSYNC_MARK, D25_MARK, ED25_MARK,
228 LCDD18_MARK, DREQ2_MARK, MSIOF0L_TSCK_MARK,
229 D26_MARK, ED26_MARK,
230 LCDD19_MARK, MSIOF0L_TSYNC_MARK,
231 D27_MARK, ED27_MARK,
232 LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK,
233 D28_MARK, ED28_MARK,
234 LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK,
235 D29_MARK, ED29_MARK,
236 LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_SS1_MARK,
237 D30_MARK, ED30_MARK,
238 LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_SS2_MARK,
239 D31_MARK, ED31_MARK,
240 LCDDCK_MARK, LCDWR_MARK, DV_CKO_MARK, SIUAOSPD_MARK,
241 LCDRD_MARK, DACK2_MARK, MSIOF0L_RSYNC_MARK,
242
243 /* 49-5 */
244 LCDHSYN_MARK, LCDCS_MARK, LCDCS2_MARK, DACK3_MARK,
245 LCDDISP_MARK, LCDRS_MARK, DREQ3_MARK, MSIOF0L_RSCK_MARK,
246 LCDCSYN_MARK, LCDCSYN2_MARK, DV_CKI_MARK,
247 LCDLCLK_MARK, DREQ1_MARK, MSIOF0L_RXD_MARK,
248 LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, MSIOF0L_TXD_MARK,
249 VIO_DR0_MARK, VIO_DR1_MARK, VIO_DR2_MARK, VIO_DR3_MARK,
250 VIO_DR4_MARK, VIO_DR5_MARK, VIO_DR6_MARK, VIO_DR7_MARK,
251 VIO_VDR_MARK, VIO_HDR_MARK,
252 VIO_CLKR_MARK, VIO_CKOR_MARK,
253 SCIFA1_TXD_MARK, GPS_PGFA0_MARK,
254 SCIFA1_SCK_MARK, GPS_PGFA1_MARK,
255 SCIFA1_RTS_MARK, GPS_EPPSINMON_MARK,
256 SCIFA1_RXD_MARK, SCIFA1_CTS_MARK,
257 MSIOF1_TXD_MARK, SCIFA1_TXD2_MARK, GPS_TXD_MARK,
258 MSIOF1_TSYNC_MARK, SCIFA1_CTS2_MARK, I2C_SDA2_MARK,
259 MSIOF1_TSCK_MARK, SCIFA1_SCK2_MARK,
260 MSIOF1_RXD_MARK, SCIFA1_RXD2_MARK, GPS_RXD_MARK,
261 MSIOF1_RSCK_MARK, SCIFA1_RTS2_MARK,
262 MSIOF1_RSYNC_MARK, I2C_SCL2_MARK,
263 MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK,
264 MSIOF1_SS1_MARK, EDBGREQ3_MARK,
265 MSIOF1_SS2_MARK,
266 PORT236_IROUT_MARK, IRDA_OUT_MARK,
267 IRDA_IN_MARK, IRDA_FIRSEL_MARK,
268 TPU1TO0_MARK, TS_SPSYNC3_MARK,
269 TPU1TO1_MARK, TS_SDAT3_MARK,
270 TPU1TO2_MARK, TS_SDEN3_MARK, PORT241_MSIOF2_SS1_MARK,
271 TPU1TO3_MARK, PORT242_MSIOF2_TSCK_MARK,
272 M13_BSW_MARK, PORT243_MSIOF2_TSYNC_MARK,
273 M14_GSW_MARK, PORT244_MSIOF2_TXD_MARK,
274 PORT245_IROUT_MARK, M15_RSW_MARK,
275 SOUT3_MARK, SCIFA2_TXD1_MARK,
276 SIN3_MARK, SCIFA2_RXD1_MARK,
277 XRTS3_MARK, SCIFA2_RTS1_MARK, PORT248_MSIOF2_SS2_MARK,
278 XCTS3_MARK, SCIFA2_CTS1_MARK, PORT249_MSIOF2_RXD_MARK,
279 DINT_MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
280 SDHICLK0_MARK, TCK2_MARK,
281 SDHICD0_MARK,
282 SDHID0_0_MARK, TMS2_MARK,
283 SDHID0_1_MARK, TDO2_MARK,
284 SDHID0_2_MARK, TDI2_MARK,
285 SDHID0_3_MARK, RTCK2_MARK,
286
287 /* 49-6 */
288 SDHICMD0_MARK, TRST2_MARK,
289 SDHIWP0_MARK, EDBGREQ2_MARK,
290 SDHICLK1_MARK, TCK3_MARK,
291 SDHID1_0_MARK, M11_SLCD_SO2_MARK,
292 TS_SPSYNC2_MARK, TMS3_MARK,
293 SDHID1_1_MARK, M9_SLCD_AO2_MARK,
294 TS_SDAT2_MARK, TDO3_MARK,
295 SDHID1_2_MARK, M10_SLCD_CK2_MARK,
296 TS_SDEN2_MARK, TDI3_MARK,
297 SDHID1_3_MARK, M12_SLCD_CE2_MARK,
298 TS_SCK2_MARK, RTCK3_MARK,
299 SDHICMD1_MARK, TRST3_MARK,
300 SDHICLK2_MARK, SCIFB_SCK_MARK,
301 SDHID2_0_MARK, SCIFB_TXD_MARK,
302 SDHID2_1_MARK, SCIFB_CTS_MARK,
303 SDHID2_2_MARK, SCIFB_RXD_MARK,
304 SDHID2_3_MARK, SCIFB_RTS_MARK,
305 SDHICMD2_MARK,
306 RESETOUTS_MARK,
307 DIVLOCK_MARK,
308 PINMUX_MARK_END,
309};
310
311static pinmux_enum_t pinmux_data[] = {
312
313 /* specify valid pin states for each pin in GPIO mode */
314
315 /* 49-1 (GPIO) */
316 PORT_DATA_I_PD(0),
317 PORT_DATA_I_PU(1), PORT_DATA_I_PU(2), PORT_DATA_I_PU(3),
318 PORT_DATA_I_PU(4), PORT_DATA_I_PU(5), PORT_DATA_I_PU(6),
319 PORT_DATA_I_PU(7), PORT_DATA_I_PU(8), PORT_DATA_I_PU(9),
320 PORT_DATA_I_PU(10), PORT_DATA_I_PU(11), PORT_DATA_I_PU(12),
321 PORT_DATA_I_PU(13),
322 PORT_DATA_IO_PU_PD(14), PORT_DATA_IO_PU_PD(15),
323 PORT_DATA_O(16), PORT_DATA_O(17), PORT_DATA_O(18), PORT_DATA_O(19),
324 PORT_DATA_O(20), PORT_DATA_O(21), PORT_DATA_O(22), PORT_DATA_O(23),
325 PORT_DATA_O(24), PORT_DATA_O(25), PORT_DATA_O(26),
326 PORT_DATA_I_PD(27), PORT_DATA_I_PD(28),
327 PORT_DATA_O(29), PORT_DATA_O(30), PORT_DATA_O(31), PORT_DATA_O(32),
328 PORT_DATA_IO_PU(33),
329 PORT_DATA_O(34),
330 PORT_DATA_I_PU(35),
331 PORT_DATA_O(36),
332 PORT_DATA_I_PU_PD(37),
333
334 /* 49-2 (GPIO) */
335 PORT_DATA_IO_PU_PD(38),
336 PORT_DATA_IO_PD(39), PORT_DATA_IO_PD(40), PORT_DATA_IO_PD(41),
337 PORT_DATA_O(42), PORT_DATA_O(43), PORT_DATA_O(44), PORT_DATA_O(45),
338 PORT_DATA_O(46), PORT_DATA_O(47),
339 PORT_DATA_I_PU_PD(48), PORT_DATA_I_PU_PD(49), PORT_DATA_I_PU_PD(50),
340 PORT_DATA_IO_PD(51), PORT_DATA_IO_PD(52),
341 PORT_DATA_O(53),
342 PORT_DATA_IO_PD(54),
343 PORT_DATA_I_PU_PD(55),
344 PORT_DATA_IO_PU_PD(56),
345 PORT_DATA_I_PU_PD(57),
346 PORT_DATA_IO_PU_PD(58),
347 PORT_DATA_O(59), PORT_DATA_O(60), PORT_DATA_O(61), PORT_DATA_O(62),
348 PORT_DATA_O(63),
349 PORT_DATA_I_PU(64),
350 PORT_DATA_O(65), PORT_DATA_O(66), PORT_DATA_O(67), PORT_DATA_O(68),
351 PORT_DATA_IO_PD(69), PORT_DATA_IO_PD(70),
352 PORT_DATA_I_PD(71), PORT_DATA_I_PD(72), PORT_DATA_I_PD(73),
353 PORT_DATA_I_PD(74),
354 PORT_DATA_IO_PU_PD(75), PORT_DATA_IO_PU_PD(76),
355 PORT_DATA_IO_PD(77), PORT_DATA_IO_PD(78),
356 PORT_DATA_O(79),
357 PORT_DATA_IO_PD(80), PORT_DATA_IO_PD(81), PORT_DATA_IO_PD(82),
358 PORT_DATA_IO_PU_PD(83), PORT_DATA_IO_PU_PD(84),
359 PORT_DATA_IO_PU_PD(85), PORT_DATA_IO_PU_PD(86),
360 PORT_DATA_I_PD(87),
361 PORT_DATA_IO_PU_PD(88),
362 PORT_DATA_I_PU_PD(89), PORT_DATA_I_PU_PD(90),
363
364 /* 49-3 (GPIO) */
365 PORT_DATA_O(91), PORT_DATA_O(92), PORT_DATA_O(93), PORT_DATA_O(94),
366 PORT_DATA_I_PU_PD(95),
367 PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97), PORT_DATA_IO_PU_PD(98),
368 PORT_DATA_IO_PU_PD(99), PORT_DATA_IO_PU_PD(100),
369 PORT_DATA_IO(101), PORT_DATA_IO(102), PORT_DATA_IO(103),
370 PORT_DATA_IO_PD(104), PORT_DATA_IO_PD(105), PORT_DATA_IO_PD(106),
371 PORT_DATA_IO_PD(107),
372 PORT_DATA_IO_PU_PD(108), PORT_DATA_IO_PU_PD(109),
373 PORT_DATA_IO_PU_PD(110), PORT_DATA_IO_PU_PD(111),
374 PORT_DATA_IO_PU_PD(112), PORT_DATA_IO_PU_PD(113),
375 PORT_DATA_IO_PU_PD(114),
376 PORT_DATA_IO_PU(115), PORT_DATA_IO_PU(116), PORT_DATA_IO_PU(117),
377 PORT_DATA_IO_PU(118), PORT_DATA_IO_PU(119), PORT_DATA_IO_PU(120),
378 PORT_DATA_IO_PU(121), PORT_DATA_IO_PU(122), PORT_DATA_IO_PU(123),
379 PORT_DATA_IO_PU(124), PORT_DATA_IO_PU(125), PORT_DATA_IO_PU(126),
380 PORT_DATA_IO_PU(127), PORT_DATA_IO_PU(128), PORT_DATA_IO_PU(129),
381 PORT_DATA_IO_PU(130),
382 PORT_DATA_O(131), PORT_DATA_O(132), PORT_DATA_O(133),
383 PORT_DATA_IO_PU(134),
384 PORT_DATA_O(135), PORT_DATA_O(136),
385 PORT_DATA_I_PU_PD(137),
386 PORT_DATA_IO(138),
387 PORT_DATA_IO_PU_PD(139),
388 PORT_DATA_IO(140), PORT_DATA_IO(141),
389 PORT_DATA_I_PU(142),
390 PORT_DATA_O(143), PORT_DATA_O(144),
391 PORT_DATA_I_PU(145),
392
393 /* 49-4 (GPIO) */
394 PORT_DATA_O(146),
395 PORT_DATA_I_PU_PD(147),
396 PORT_DATA_I_PD(148), PORT_DATA_I_PD(149),
397 PORT_DATA_IO_PD(150), PORT_DATA_IO_PD(151), PORT_DATA_IO_PD(152),
398 PORT_DATA_IO_PD(153), PORT_DATA_IO_PD(154), PORT_DATA_IO_PD(155),
399 PORT_DATA_IO_PD(156), PORT_DATA_IO_PD(157), PORT_DATA_IO_PD(158),
400 PORT_DATA_IO_PD(159), PORT_DATA_IO_PD(160), PORT_DATA_IO_PD(161),
401 PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163), PORT_DATA_IO_PD(164),
402 PORT_DATA_IO_PD(165), PORT_DATA_IO_PD(166),
403 PORT_DATA_IO_PU_PD(167),
404 PORT_DATA_O(168),
405 PORT_DATA_I_PD(169), PORT_DATA_I_PD(170),
406 PORT_DATA_O(171),
407 PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173),
408 PORT_DATA_O(174),
409 PORT_DATA_IO_PD(175), PORT_DATA_IO_PD(176), PORT_DATA_IO_PD(177),
410 PORT_DATA_IO_PD(178), PORT_DATA_IO_PD(179), PORT_DATA_IO_PD(180),
411 PORT_DATA_IO_PD(181), PORT_DATA_IO_PD(182), PORT_DATA_IO_PD(183),
412 PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185), PORT_DATA_IO_PD(186),
413 PORT_DATA_IO_PD(187), PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189),
414 PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191), PORT_DATA_IO_PD(192),
415 PORT_DATA_IO_PD(193), PORT_DATA_IO_PD(194), PORT_DATA_IO_PD(195),
416 PORT_DATA_IO_PD(196), PORT_DATA_IO_PD(197), PORT_DATA_IO_PD(198),
417 PORT_DATA_O(199),
418 PORT_DATA_IO_PD(200),
419
420 /* 49-5 (GPIO) */
421 PORT_DATA_O(201),
422 PORT_DATA_IO_PD(202), PORT_DATA_IO_PD(203),
423 PORT_DATA_I(204),
424 PORT_DATA_O(205),
425 PORT_DATA_IO_PD(206), PORT_DATA_IO_PD(207), PORT_DATA_IO_PD(208),
426 PORT_DATA_IO_PD(209), PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211),
427 PORT_DATA_IO_PD(212), PORT_DATA_IO_PD(213), PORT_DATA_IO_PD(214),
428 PORT_DATA_IO_PD(215), PORT_DATA_IO_PD(216),
429 PORT_DATA_O(217),
430 PORT_DATA_I_PU_PD(218), PORT_DATA_I_PU_PD(219),
431 PORT_DATA_O(220), PORT_DATA_O(221), PORT_DATA_O(222),
432 PORT_DATA_I_PD(223),
433 PORT_DATA_I_PU_PD(224),
434 PORT_DATA_O(225),
435 PORT_DATA_IO_PD(226),
436 PORT_DATA_IO_PU_PD(227),
437 PORT_DATA_I_PD(228),
438 PORT_DATA_IO_PD(229), PORT_DATA_IO_PD(230),
439 PORT_DATA_I_PU_PD(231), PORT_DATA_I_PU_PD(232),
440 PORT_DATA_IO_PU_PD(233), PORT_DATA_IO_PU_PD(234),
441 PORT_DATA_I_PU_PD(235),
442 PORT_DATA_O(236),
443 PORT_DATA_I_PD(237),
444 PORT_DATA_IO_PU_PD(238), PORT_DATA_IO_PU_PD(239),
445 PORT_DATA_IO_PD(240), PORT_DATA_IO_PD(241),
446 PORT_DATA_IO_PD(242), PORT_DATA_IO_PD(243),
447 PORT_DATA_O(244),
448 PORT_DATA_IO_PU_PD(245),
449 PORT_DATA_O(246),
450 PORT_DATA_I_PD(247),
451 PORT_DATA_IO_PU_PD(248),
452 PORT_DATA_I_PU_PD(249),
453 PORT_DATA_IO_PD(250), PORT_DATA_IO_PD(251),
454 PORT_DATA_IO_PU_PD(252), PORT_DATA_IO_PU_PD(253),
455 PORT_DATA_IO_PU_PD(254), PORT_DATA_IO_PU_PD(255),
456 PORT_DATA_IO_PU_PD(256),
457
458 /* 49-6 (GPIO) */
459 PORT_DATA_IO_PU_PD(257), PORT_DATA_IO_PU_PD(258),
460 PORT_DATA_IO_PD(259),
461 PORT_DATA_IO_PU(260), PORT_DATA_IO_PU(261), PORT_DATA_IO_PU(262),
462 PORT_DATA_IO_PU(263), PORT_DATA_IO_PU(264),
463 PORT_DATA_O(265),
464 PORT_DATA_IO_PU(266), PORT_DATA_IO_PU(267), PORT_DATA_IO_PU(268),
465 PORT_DATA_IO_PU(269), PORT_DATA_IO_PU(270),
466 PORT_DATA_O(271),
467 PORT_DATA_I_PD(272),
468
469 /* Special Pull-up / Pull-down Functions */
470 PINMUX_DATA(PORT48_KEYIN0_PU_MARK, MSELBCR_MSEL2_1,
471 PORT48_FN2, PORT48_IN_PU),
472 PINMUX_DATA(PORT49_KEYIN1_PU_MARK, MSELBCR_MSEL2_1,
473 PORT49_FN2, PORT49_IN_PU),
474 PINMUX_DATA(PORT50_KEYIN2_PU_MARK, MSELBCR_MSEL2_1,
475 PORT50_FN2, PORT50_IN_PU),
476 PINMUX_DATA(PORT55_KEYIN3_PU_MARK, MSELBCR_MSEL2_1,
477 PORT55_FN2, PORT55_IN_PU),
478 PINMUX_DATA(PORT56_KEYIN4_PU_MARK, MSELBCR_MSEL2_1,
479 PORT56_FN2, PORT56_IN_PU),
480 PINMUX_DATA(PORT57_KEYIN5_PU_MARK, MSELBCR_MSEL2_1,
481 PORT57_FN2, PORT57_IN_PU),
482 PINMUX_DATA(PORT58_KEYIN6_PU_MARK, MSELBCR_MSEL2_1,
483 PORT58_FN2, PORT58_IN_PU),
484
485 /* 49-1 (FN) */
486 PINMUX_DATA(VBUS0_MARK, PORT0_FN1),
487 PINMUX_DATA(CPORT0_MARK, PORT1_FN1),
488 PINMUX_DATA(CPORT1_MARK, PORT2_FN1),
489 PINMUX_DATA(CPORT2_MARK, PORT3_FN1),
490 PINMUX_DATA(CPORT3_MARK, PORT4_FN1),
491 PINMUX_DATA(CPORT4_MARK, PORT5_FN1),
492 PINMUX_DATA(CPORT5_MARK, PORT6_FN1),
493 PINMUX_DATA(CPORT6_MARK, PORT7_FN1),
494 PINMUX_DATA(CPORT7_MARK, PORT8_FN1),
495 PINMUX_DATA(CPORT8_MARK, PORT9_FN1),
496 PINMUX_DATA(CPORT9_MARK, PORT10_FN1),
497 PINMUX_DATA(CPORT10_MARK, PORT11_FN1),
498 PINMUX_DATA(CPORT11_MARK, PORT12_FN1),
499 PINMUX_DATA(SIN2_MARK, PORT12_FN2),
500 PINMUX_DATA(CPORT12_MARK, PORT13_FN1),
501 PINMUX_DATA(XCTS2_MARK, PORT13_FN2),
502 PINMUX_DATA(CPORT13_MARK, PORT14_FN1),
503 PINMUX_DATA(RFSPO4_MARK, PORT14_FN2),
504 PINMUX_DATA(CPORT14_MARK, PORT15_FN1),
505 PINMUX_DATA(RFSPO5_MARK, PORT15_FN2),
506 PINMUX_DATA(CPORT15_MARK, PORT16_FN1),
507 PINMUX_DATA(CPORT16_MARK, PORT17_FN1),
508 PINMUX_DATA(CPORT17_MARK, PORT18_FN1),
509 PINMUX_DATA(SOUT2_MARK, PORT18_FN2),
510 PINMUX_DATA(CPORT18_MARK, PORT19_FN1),
511 PINMUX_DATA(XRTS2_MARK, PORT19_FN1),
512 PINMUX_DATA(CPORT19_MARK, PORT20_FN1),
513 PINMUX_DATA(CPORT20_MARK, PORT21_FN1),
514 PINMUX_DATA(RFSPO6_MARK, PORT21_FN2),
515 PINMUX_DATA(CPORT21_MARK, PORT22_FN1),
516 PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
517 PINMUX_DATA(CPORT22_MARK, PORT23_FN1),
518 PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
519 PINMUX_DATA(CPORT23_MARK, PORT24_FN1),
520 PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
521 PINMUX_DATA(RFSPO7_MARK, PORT24_FN3),
522 PINMUX_DATA(MPORT0_MARK, PORT25_FN1),
523 PINMUX_DATA(MPORT1_MARK, PORT26_FN1),
524 PINMUX_DATA(B_SYNLD1_MARK, PORT27_FN1),
525 PINMUX_DATA(B_SYNLD2_MARK, PORT28_FN1),
526 PINMUX_DATA(XMAINPS_MARK, PORT29_FN1),
527 PINMUX_DATA(XDIVPS_MARK, PORT30_FN1),
528 PINMUX_DATA(XIDRST_MARK, PORT31_FN1),
529 PINMUX_DATA(IDCLK_MARK, PORT32_FN1),
530 PINMUX_DATA(IDIO_MARK, PORT33_FN1),
531 PINMUX_DATA(SOUT1_MARK, PORT34_FN1),
532 PINMUX_DATA(SCIFA4_TXD_MARK, PORT34_FN2),
533 PINMUX_DATA(M02_BERDAT_MARK, PORT34_FN3),
534 PINMUX_DATA(SIN1_MARK, PORT35_FN1),
535 PINMUX_DATA(SCIFA4_RXD_MARK, PORT35_FN2),
536 PINMUX_DATA(XWUP_MARK, PORT35_FN3),
537 PINMUX_DATA(XRTS1_MARK, PORT36_FN1),
538 PINMUX_DATA(SCIFA4_RTS_MARK, PORT36_FN2),
539 PINMUX_DATA(M03_BERCLK_MARK, PORT36_FN3),
540 PINMUX_DATA(XCTS1_MARK, PORT37_FN1),
541 PINMUX_DATA(SCIFA4_CTS_MARK, PORT37_FN2),
542
543 /* 49-2 (FN) */
544 PINMUX_DATA(HSU_IQ_AGC6_MARK, PORT38_FN1),
545 PINMUX_DATA(MFG2_IN2_MARK, PORT38_FN2),
546 PINMUX_DATA(MSIOF2_MCK0_MARK, PORT38_FN3),
547 PINMUX_DATA(HSU_IQ_AGC5_MARK, PORT39_FN1),
548 PINMUX_DATA(MFG2_IN1_MARK, PORT39_FN2),
549 PINMUX_DATA(MSIOF2_MCK1_MARK, PORT39_FN3),
550 PINMUX_DATA(HSU_IQ_AGC4_MARK, PORT40_FN1),
551 PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT40_FN3),
552 PINMUX_DATA(HSU_IQ_AGC3_MARK, PORT41_FN1),
553 PINMUX_DATA(MFG2_OUT1_MARK, PORT41_FN2),
554 PINMUX_DATA(MSIOF2_RSCK_MARK, PORT41_FN3),
555 PINMUX_DATA(HSU_IQ_AGC2_MARK, PORT42_FN1),
556 PINMUX_DATA(PORT42_KEYOUT0_MARK, MSELBCR_MSEL2_1, PORT42_FN2),
557 PINMUX_DATA(HSU_IQ_AGC1_MARK, PORT43_FN1),
558 PINMUX_DATA(PORT43_KEYOUT1_MARK, MSELBCR_MSEL2_1, PORT43_FN2),
559 PINMUX_DATA(HSU_IQ_AGC0_MARK, PORT44_FN1),
560 PINMUX_DATA(PORT44_KEYOUT2_MARK, MSELBCR_MSEL2_1, PORT44_FN2),
561 PINMUX_DATA(HSU_IQ_AGC_ST_MARK, PORT45_FN1),
562 PINMUX_DATA(PORT45_KEYOUT3_MARK, MSELBCR_MSEL2_1, PORT45_FN2),
563 PINMUX_DATA(HSU_IQ_PDO_MARK, PORT46_FN1),
564 PINMUX_DATA(PORT46_KEYOUT4_MARK, MSELBCR_MSEL2_1, PORT46_FN2),
565 PINMUX_DATA(HSU_IQ_PYO_MARK, PORT47_FN1),
566 PINMUX_DATA(PORT47_KEYOUT5_MARK, MSELBCR_MSEL2_1, PORT47_FN2),
567 PINMUX_DATA(HSU_EN_TXMUX_G3MO_MARK, PORT48_FN1),
568 PINMUX_DATA(PORT48_KEYIN0_MARK, MSELBCR_MSEL2_1, PORT48_FN2),
569 PINMUX_DATA(HSU_I_TXMUX_G3MO_MARK, PORT49_FN1),
570 PINMUX_DATA(PORT49_KEYIN1_MARK, MSELBCR_MSEL2_1, PORT49_FN2),
571 PINMUX_DATA(HSU_Q_TXMUX_G3MO_MARK, PORT50_FN1),
572 PINMUX_DATA(PORT50_KEYIN2_MARK, MSELBCR_MSEL2_1, PORT50_FN2),
573 PINMUX_DATA(HSU_SYO_MARK, PORT51_FN1),
574 PINMUX_DATA(PORT51_MSIOF2_TSYNC_MARK, PORT51_FN2),
575 PINMUX_DATA(HSU_SDO_MARK, PORT52_FN1),
576 PINMUX_DATA(PORT52_MSIOF2_TSCK_MARK, PORT52_FN2),
577 PINMUX_DATA(HSU_TGTTI_G3MO_MARK, PORT53_FN1),
578 PINMUX_DATA(PORT53_MSIOF2_TXD_MARK, PORT53_FN2),
579 PINMUX_DATA(B_TIME_STAMP_MARK, PORT54_FN1),
580 PINMUX_DATA(PORT54_MSIOF2_RXD_MARK, PORT54_FN2),
581 PINMUX_DATA(HSU_SDI_MARK, PORT55_FN1),
582 PINMUX_DATA(PORT55_KEYIN3_MARK, MSELBCR_MSEL2_1, PORT55_FN2),
583 PINMUX_DATA(HSU_SCO_MARK, PORT56_FN1),
584 PINMUX_DATA(PORT56_KEYIN4_MARK, MSELBCR_MSEL2_1, PORT56_FN2),
585 PINMUX_DATA(HSU_DREQ_MARK, PORT57_FN1),
586 PINMUX_DATA(PORT57_KEYIN5_MARK, MSELBCR_MSEL2_1, PORT57_FN2),
587 PINMUX_DATA(HSU_DACK_MARK, PORT58_FN1),
588 PINMUX_DATA(PORT58_KEYIN6_MARK, MSELBCR_MSEL2_1, PORT58_FN2),
589 PINMUX_DATA(HSU_CLK61M_MARK, PORT59_FN1),
590 PINMUX_DATA(PORT59_MSIOF2_SS1_MARK, PORT59_FN2),
591 PINMUX_DATA(HSU_XRST_MARK, PORT60_FN1),
592 PINMUX_DATA(PORT60_MSIOF2_SS2_MARK, PORT60_FN2),
593 PINMUX_DATA(PCMCLKO_MARK, PORT61_FN1),
594 PINMUX_DATA(SYNC8KO_MARK, PORT62_FN1),
595 PINMUX_DATA(DNPCM_A_MARK, PORT63_FN1),
596 PINMUX_DATA(UPPCM_A_MARK, PORT64_FN1),
597 PINMUX_DATA(XTALB1L_MARK, PORT65_FN1),
598 PINMUX_DATA(GPS_AGC1_MARK, PORT66_FN1),
599 PINMUX_DATA(SCIFA0_RTS_MARK, PORT66_FN2),
600 PINMUX_DATA(GPS_AGC2_MARK, PORT67_FN1),
601 PINMUX_DATA(SCIFA0_SCK_MARK, PORT67_FN2),
602 PINMUX_DATA(GPS_AGC3_MARK, PORT68_FN1),
603 PINMUX_DATA(SCIFA0_TXD_MARK, PORT68_FN2),
604 PINMUX_DATA(GPS_AGC4_MARK, PORT69_FN1),
605 PINMUX_DATA(SCIFA0_RXD_MARK, PORT69_FN2),
606 PINMUX_DATA(GPS_PWRD_MARK, PORT70_FN1),
607 PINMUX_DATA(SCIFA0_CTS_MARK, PORT70_FN2),
608 PINMUX_DATA(GPS_IM_MARK, PORT71_FN1),
609 PINMUX_DATA(GPS_IS_MARK, PORT72_FN1),
610 PINMUX_DATA(GPS_QM_MARK, PORT73_FN1),
611 PINMUX_DATA(GPS_QS_MARK, PORT74_FN1),
612 PINMUX_DATA(SIUBOMC_MARK, PORT75_FN1),
613 PINMUX_DATA(TPU2TO0_MARK, PORT75_FN3),
614 PINMUX_DATA(SIUCKB_MARK, PORT76_FN1),
615 PINMUX_DATA(TPU2TO1_MARK, PORT76_FN3),
616 PINMUX_DATA(SIUBOLR_MARK, PORT77_FN1),
617 PINMUX_DATA(BBIF2_TSYNC_MARK, PORT77_FN2),
618 PINMUX_DATA(TPU2TO2_MARK, PORT77_FN3),
619 PINMUX_DATA(SIUBOBT_MARK, PORT78_FN1),
620 PINMUX_DATA(BBIF2_TSCK_MARK, PORT78_FN2),
621 PINMUX_DATA(TPU2TO3_MARK, PORT78_FN3),
622 PINMUX_DATA(SIUBOSLD_MARK, PORT79_FN1),
623 PINMUX_DATA(BBIF2_TXD_MARK, PORT79_FN2),
624 PINMUX_DATA(TPU3TO0_MARK, PORT79_FN3),
625 PINMUX_DATA(SIUBILR_MARK, PORT80_FN1),
626 PINMUX_DATA(TPU3TO1_MARK, PORT80_FN3),
627 PINMUX_DATA(SIUBIBT_MARK, PORT81_FN1),
628 PINMUX_DATA(TPU3TO2_MARK, PORT81_FN3),
629 PINMUX_DATA(SIUBISLD_MARK, PORT82_FN1),
630 PINMUX_DATA(TPU3TO3_MARK, PORT82_FN3),
631 PINMUX_DATA(NMI_MARK, PORT83_FN1),
632 PINMUX_DATA(TPU4TO0_MARK, PORT83_FN3),
633 PINMUX_DATA(DNPCM_M_MARK, PORT84_FN1),
634 PINMUX_DATA(TPU4TO1_MARK, PORT84_FN3),
635 PINMUX_DATA(TPU4TO2_MARK, PORT85_FN3),
636 PINMUX_DATA(TPU4TO3_MARK, PORT86_FN3),
637 PINMUX_DATA(IRQ_TMPB_MARK, PORT87_FN1),
638 PINMUX_DATA(PWEN_MARK, PORT88_FN1),
639 PINMUX_DATA(MFG1_OUT1_MARK, PORT88_FN2),
640 PINMUX_DATA(OVCN_MARK, PORT89_FN1),
641 PINMUX_DATA(MFG1_IN1_MARK, PORT89_FN2),
642 PINMUX_DATA(OVCN2_MARK, PORT90_FN1),
643 PINMUX_DATA(MFG1_IN2_MARK, PORT90_FN2),
644
645 /* 49-3 (FN) */
646 PINMUX_DATA(RFSPO1_MARK, PORT91_FN1),
647 PINMUX_DATA(RFSPO2_MARK, PORT92_FN1),
648 PINMUX_DATA(RFSPO3_MARK, PORT93_FN1),
649 PINMUX_DATA(PORT93_VIO_CKO2_MARK, PORT93_FN2),
650 PINMUX_DATA(USBTERM_MARK, PORT94_FN1),
651 PINMUX_DATA(EXTLP_MARK, PORT94_FN2),
652 PINMUX_DATA(IDIN_MARK, PORT95_FN1),
653 PINMUX_DATA(SCIFA5_CTS_MARK, PORT96_FN1),
654 PINMUX_DATA(MFG0_IN1_MARK, PORT96_FN2),
655 PINMUX_DATA(SCIFA5_RTS_MARK, PORT97_FN1),
656 PINMUX_DATA(MFG0_IN2_MARK, PORT97_FN2),
657 PINMUX_DATA(SCIFA5_RXD_MARK, PORT98_FN1),
658 PINMUX_DATA(SCIFA5_TXD_MARK, PORT99_FN1),
659 PINMUX_DATA(SCIFA5_SCK_MARK, PORT100_FN1),
660 PINMUX_DATA(MFG0_OUT1_MARK, PORT100_FN2),
661 PINMUX_DATA(A0_EA0_MARK, PORT101_FN1),
662 PINMUX_DATA(BS_MARK, PORT101_FN2),
663 PINMUX_DATA(A14_EA14_MARK, PORT102_FN1),
664 PINMUX_DATA(PORT102_KEYOUT0_MARK, MSELBCR_MSEL2_0, PORT102_FN2),
665 PINMUX_DATA(A15_EA15_MARK, PORT103_FN1),
666 PINMUX_DATA(PORT103_KEYOUT1_MARK, MSELBCR_MSEL2_0, PORT103_FN2),
667 PINMUX_DATA(DV_CLKOL_MARK, PORT103_FN3),
668 PINMUX_DATA(A16_EA16_MARK, PORT104_FN1),
669 PINMUX_DATA(PORT104_KEYOUT2_MARK, MSELBCR_MSEL2_0, PORT104_FN2),
670 PINMUX_DATA(DV_VSYNCL_MARK, PORT104_FN3),
671 PINMUX_DATA(MSIOF0_SS1_MARK, PORT104_FN4),
672 PINMUX_DATA(A17_EA17_MARK, PORT105_FN1),
673 PINMUX_DATA(PORT105_KEYOUT3_MARK, MSELBCR_MSEL2_0, PORT105_FN2),
674 PINMUX_DATA(DV_HSYNCL_MARK, PORT105_FN3),
675 PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT105_FN4),
676 PINMUX_DATA(A18_EA18_MARK, PORT106_FN1),
677 PINMUX_DATA(PORT106_KEYOUT4_MARK, MSELBCR_MSEL2_0, PORT106_FN2),
678 PINMUX_DATA(DV_DL0_MARK, PORT106_FN3),
679 PINMUX_DATA(MSIOF0_TSCK_MARK, PORT106_FN4),
680 PINMUX_DATA(A19_EA19_MARK, PORT107_FN1),
681 PINMUX_DATA(PORT107_KEYOUT5_MARK, MSELBCR_MSEL2_0, PORT107_FN2),
682 PINMUX_DATA(DV_DL1_MARK, PORT107_FN3),
683 PINMUX_DATA(MSIOF0_TXD_MARK, PORT107_FN4),
684 PINMUX_DATA(A20_EA20_MARK, PORT108_FN1),
685 PINMUX_DATA(PORT108_KEYIN0_MARK, MSELBCR_MSEL2_0, PORT108_FN2),
686 PINMUX_DATA(DV_DL2_MARK, PORT108_FN3),
687 PINMUX_DATA(MSIOF0_RSCK_MARK, PORT108_FN4),
688 PINMUX_DATA(A21_EA21_MARK, PORT109_FN1),
689 PINMUX_DATA(PORT109_KEYIN1_MARK, MSELBCR_MSEL2_0, PORT109_FN2),
690 PINMUX_DATA(DV_DL3_MARK, PORT109_FN3),
691 PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT109_FN4),
692 PINMUX_DATA(A22_EA22_MARK, PORT110_FN1),
693 PINMUX_DATA(PORT110_KEYIN2_MARK, MSELBCR_MSEL2_0, PORT110_FN2),
694 PINMUX_DATA(DV_DL4_MARK, PORT110_FN3),
695 PINMUX_DATA(MSIOF0_MCK0_MARK, PORT110_FN4),
696 PINMUX_DATA(A23_EA23_MARK, PORT111_FN1),
697 PINMUX_DATA(PORT111_KEYIN3_MARK, MSELBCR_MSEL2_0, PORT111_FN2),
698 PINMUX_DATA(DV_DL5_MARK, PORT111_FN3),
699 PINMUX_DATA(MSIOF0_MCK1_MARK, PORT111_FN4),
700 PINMUX_DATA(A24_EA24_MARK, PORT112_FN1),
701 PINMUX_DATA(PORT112_KEYIN4_MARK, MSELBCR_MSEL2_0, PORT112_FN2),
702 PINMUX_DATA(DV_DL6_MARK, PORT112_FN3),
703 PINMUX_DATA(MSIOF0_RXD_MARK, PORT112_FN4),
704 PINMUX_DATA(A25_EA25_MARK, PORT113_FN1),
705 PINMUX_DATA(PORT113_KEYIN5_MARK, MSELBCR_MSEL2_0, PORT113_FN2),
706 PINMUX_DATA(DV_DL7_MARK, PORT113_FN3),
707 PINMUX_DATA(MSIOF0_SS2_MARK, PORT113_FN4),
708 PINMUX_DATA(A26_MARK, PORT114_FN1),
709 PINMUX_DATA(PORT113_KEYIN6_MARK, MSELBCR_MSEL2_0, PORT114_FN2),
710 PINMUX_DATA(DV_CLKIL_MARK, PORT114_FN3),
711 PINMUX_DATA(D0_ED0_NAF0_MARK, PORT115_FN1),
712 PINMUX_DATA(D1_ED1_NAF1_MARK, PORT116_FN1),
713 PINMUX_DATA(D2_ED2_NAF2_MARK, PORT117_FN1),
714 PINMUX_DATA(D3_ED3_NAF3_MARK, PORT118_FN1),
715 PINMUX_DATA(D4_ED4_NAF4_MARK, PORT119_FN1),
716 PINMUX_DATA(D5_ED5_NAF5_MARK, PORT120_FN1),
717 PINMUX_DATA(D6_ED6_NAF6_MARK, PORT121_FN1),
718 PINMUX_DATA(D7_ED7_NAF7_MARK, PORT122_FN1),
719 PINMUX_DATA(D8_ED8_NAF8_MARK, PORT123_FN1),
720 PINMUX_DATA(D9_ED9_NAF9_MARK, PORT124_FN1),
721 PINMUX_DATA(D10_ED10_NAF10_MARK, PORT125_FN1),
722 PINMUX_DATA(D11_ED11_NAF11_MARK, PORT126_FN1),
723 PINMUX_DATA(D12_ED12_NAF12_MARK, PORT127_FN1),
724 PINMUX_DATA(D13_ED13_NAF13_MARK, PORT128_FN1),
725 PINMUX_DATA(D14_ED14_NAF14_MARK, PORT129_FN1),
726 PINMUX_DATA(D15_ED15_NAF15_MARK, PORT130_FN1),
727 PINMUX_DATA(CS4_MARK, PORT131_FN1),
728 PINMUX_DATA(CS5A_MARK, PORT132_FN1),
729 PINMUX_DATA(CS5B_MARK, PORT133_FN1),
730 PINMUX_DATA(FCE1_MARK, PORT133_FN2),
731 PINMUX_DATA(CS6B_MARK, PORT134_FN1),
732 PINMUX_DATA(XCS2_MARK, PORT134_FN2),
733 PINMUX_DATA(FCE0_MARK, PORT135_FN1),
734 PINMUX_DATA(CS6A_MARK, PORT136_FN1),
735 PINMUX_DATA(DACK0_MARK, PORT136_FN2),
736 PINMUX_DATA(WAIT_MARK, PORT137_FN1),
737 PINMUX_DATA(DREQ0_MARK, PORT137_FN2),
738 PINMUX_DATA(RD_XRD_MARK, PORT138_FN1),
739 PINMUX_DATA(A27_MARK, PORT139_FN1),
740 PINMUX_DATA(RDWR_XWE_MARK, PORT139_FN2),
741 PINMUX_DATA(WE0_XWR0_FWE_MARK, PORT140_FN1),
742 PINMUX_DATA(WE1_XWR1_MARK, PORT141_FN1),
743 PINMUX_DATA(FRB_MARK, PORT142_FN1),
744 PINMUX_DATA(CKO_MARK, PORT143_FN1),
745 PINMUX_DATA(NBRSTOUT_MARK, PORT144_FN1),
746 PINMUX_DATA(NBRST_MARK, PORT145_FN1),
747
748 /* 49-4 (FN) */
749 PINMUX_DATA(RFSPO0_MARK, PORT146_FN1),
750 PINMUX_DATA(PORT146_VIO_CKO2_MARK, PORT146_FN2),
751 PINMUX_DATA(TSTMD_MARK, PORT147_FN1),
752 PINMUX_DATA(VIO_VD_MARK, PORT148_FN1),
753 PINMUX_DATA(VIO_HD_MARK, PORT149_FN1),
754 PINMUX_DATA(VIO_D0_MARK, PORT150_FN1),
755 PINMUX_DATA(VIO_D1_MARK, PORT151_FN1),
756 PINMUX_DATA(VIO_D2_MARK, PORT152_FN1),
757 PINMUX_DATA(VIO_D3_MARK, PORT153_FN1),
758 PINMUX_DATA(VIO_D4_MARK, PORT154_FN1),
759 PINMUX_DATA(VIO_D5_MARK, PORT155_FN1),
760 PINMUX_DATA(VIO_D6_MARK, PORT156_FN1),
761 PINMUX_DATA(VIO_D7_MARK, PORT157_FN1),
762 PINMUX_DATA(VIO_D8_MARK, PORT158_FN1),
763 PINMUX_DATA(VIO_D9_MARK, PORT159_FN1),
764 PINMUX_DATA(VIO_D10_MARK, PORT160_FN1),
765 PINMUX_DATA(VIO_D11_MARK, PORT161_FN1),
766 PINMUX_DATA(VIO_D12_MARK, PORT162_FN1),
767 PINMUX_DATA(VIO_D13_MARK, PORT163_FN1),
768 PINMUX_DATA(VIO_D14_MARK, PORT164_FN1),
769 PINMUX_DATA(VIO_D15_MARK, PORT165_FN1),
770 PINMUX_DATA(VIO_CLK_MARK, PORT166_FN1),
771 PINMUX_DATA(VIO_FIELD_MARK, PORT167_FN1),
772 PINMUX_DATA(VIO_CKO_MARK, PORT168_FN1),
773 PINMUX_DATA(MFG3_IN1_MARK, PORT169_FN2),
774 PINMUX_DATA(MFG3_IN2_MARK, PORT170_FN2),
775 PINMUX_DATA(M9_SLCD_A01_MARK, PORT171_FN1),
776 PINMUX_DATA(MFG3_OUT1_MARK, PORT171_FN2),
777 PINMUX_DATA(TPU0TO0_MARK, PORT171_FN3),
778 PINMUX_DATA(M10_SLCD_CK1_MARK, PORT172_FN1),
779 PINMUX_DATA(MFG4_IN1_MARK, PORT172_FN2),
780 PINMUX_DATA(TPU0TO1_MARK, PORT172_FN3),
781 PINMUX_DATA(M11_SLCD_SO1_MARK, PORT173_FN1),
782 PINMUX_DATA(MFG4_IN2_MARK, PORT173_FN2),
783 PINMUX_DATA(TPU0TO2_MARK, PORT173_FN3),
784 PINMUX_DATA(M12_SLCD_CE1_MARK, PORT174_FN1),
785 PINMUX_DATA(MFG4_OUT1_MARK, PORT174_FN2),
786 PINMUX_DATA(TPU0TO3_MARK, PORT174_FN3),
787 PINMUX_DATA(LCDD0_MARK, PORT175_FN1),
788 PINMUX_DATA(PORT175_KEYOUT0_MARK, PORT175_FN2),
789 PINMUX_DATA(DV_D0_MARK, PORT175_FN3),
790 PINMUX_DATA(SIUCKA_MARK, PORT175_FN4),
791 PINMUX_DATA(MFG0_OUT2_MARK, PORT175_FN5),
792 PINMUX_DATA(LCDD1_MARK, PORT176_FN1),
793 PINMUX_DATA(PORT176_KEYOUT1_MARK, PORT176_FN2),
794 PINMUX_DATA(DV_D1_MARK, PORT176_FN3),
795 PINMUX_DATA(SIUAOLR_MARK, PORT176_FN4),
796 PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT176_FN5),
797 PINMUX_DATA(LCDD2_MARK, PORT177_FN1),
798 PINMUX_DATA(PORT177_KEYOUT2_MARK, PORT177_FN2),
799 PINMUX_DATA(DV_D2_MARK, PORT177_FN3),
800 PINMUX_DATA(SIUAOBT_MARK, PORT177_FN4),
801 PINMUX_DATA(BBIF2_TSCK1_MARK, PORT177_FN5),
802 PINMUX_DATA(LCDD3_MARK, PORT178_FN1),
803 PINMUX_DATA(PORT178_KEYOUT3_MARK, PORT178_FN2),
804 PINMUX_DATA(DV_D3_MARK, PORT178_FN3),
805 PINMUX_DATA(SIUAOSLD_MARK, PORT178_FN4),
806 PINMUX_DATA(BBIF2_TXD1_MARK, PORT178_FN5),
807 PINMUX_DATA(LCDD4_MARK, PORT179_FN1),
808 PINMUX_DATA(PORT179_KEYOUT4_MARK, PORT179_FN2),
809 PINMUX_DATA(DV_D4_MARK, PORT179_FN3),
810 PINMUX_DATA(SIUAISPD_MARK, PORT179_FN4),
811 PINMUX_DATA(MFG1_OUT2_MARK, PORT179_FN5),
812 PINMUX_DATA(LCDD5_MARK, PORT180_FN1),
813 PINMUX_DATA(PORT180_KEYOUT5_MARK, PORT180_FN2),
814 PINMUX_DATA(DV_D5_MARK, PORT180_FN3),
815 PINMUX_DATA(SIUAILR_MARK, PORT180_FN4),
816 PINMUX_DATA(MFG2_OUT2_MARK, PORT180_FN5),
817 PINMUX_DATA(LCDD6_MARK, PORT181_FN1),
818 PINMUX_DATA(DV_D6_MARK, PORT181_FN3),
819 PINMUX_DATA(SIUAIBT_MARK, PORT181_FN4),
820 PINMUX_DATA(MFG3_OUT2_MARK, PORT181_FN5),
821 PINMUX_DATA(XWR2_MARK, PORT181_FN7),
822 PINMUX_DATA(LCDD7_MARK, PORT182_FN1),
823 PINMUX_DATA(DV_D7_MARK, PORT182_FN3),
824 PINMUX_DATA(SIUAISLD_MARK, PORT182_FN4),
825 PINMUX_DATA(MFG4_OUT2_MARK, PORT182_FN5),
826 PINMUX_DATA(XWR3_MARK, PORT182_FN7),
827 PINMUX_DATA(LCDD8_MARK, PORT183_FN1),
828 PINMUX_DATA(DV_D8_MARK, PORT183_FN3),
829 PINMUX_DATA(D16_MARK, PORT183_FN6),
830 PINMUX_DATA(ED16_MARK, PORT183_FN7),
831 PINMUX_DATA(LCDD9_MARK, PORT184_FN1),
832 PINMUX_DATA(DV_D9_MARK, PORT184_FN3),
833 PINMUX_DATA(D17_MARK, PORT184_FN6),
834 PINMUX_DATA(ED17_MARK, PORT184_FN7),
835 PINMUX_DATA(LCDD10_MARK, PORT185_FN1),
836 PINMUX_DATA(DV_D10_MARK, PORT185_FN3),
837 PINMUX_DATA(D18_MARK, PORT185_FN6),
838 PINMUX_DATA(ED18_MARK, PORT185_FN7),
839 PINMUX_DATA(LCDD11_MARK, PORT186_FN1),
840 PINMUX_DATA(DV_D11_MARK, PORT186_FN3),
841 PINMUX_DATA(D19_MARK, PORT186_FN6),
842 PINMUX_DATA(ED19_MARK, PORT186_FN7),
843 PINMUX_DATA(LCDD12_MARK, PORT187_FN1),
844 PINMUX_DATA(DV_D12_MARK, PORT187_FN3),
845 PINMUX_DATA(D20_MARK, PORT187_FN6),
846 PINMUX_DATA(ED20_MARK, PORT187_FN7),
847 PINMUX_DATA(LCDD13_MARK, PORT188_FN1),
848 PINMUX_DATA(DV_D13_MARK, PORT188_FN3),
849 PINMUX_DATA(D21_MARK, PORT188_FN6),
850 PINMUX_DATA(ED21_MARK, PORT188_FN7),
851 PINMUX_DATA(LCDD14_MARK, PORT189_FN1),
852 PINMUX_DATA(DV_D14_MARK, PORT189_FN3),
853 PINMUX_DATA(D22_MARK, PORT189_FN6),
854 PINMUX_DATA(ED22_MARK, PORT189_FN7),
855 PINMUX_DATA(LCDD15_MARK, PORT190_FN1),
856 PINMUX_DATA(DV_D15_MARK, PORT190_FN3),
857 PINMUX_DATA(D23_MARK, PORT190_FN6),
858 PINMUX_DATA(ED23_MARK, PORT190_FN7),
859 PINMUX_DATA(LCDD16_MARK, PORT191_FN1),
860 PINMUX_DATA(DV_HSYNC_MARK, PORT191_FN3),
861 PINMUX_DATA(D24_MARK, PORT191_FN6),
862 PINMUX_DATA(ED24_MARK, PORT191_FN7),
863 PINMUX_DATA(LCDD17_MARK, PORT192_FN1),
864 PINMUX_DATA(DV_VSYNC_MARK, PORT192_FN3),
865 PINMUX_DATA(D25_MARK, PORT192_FN6),
866 PINMUX_DATA(ED25_MARK, PORT192_FN7),
867 PINMUX_DATA(LCDD18_MARK, PORT193_FN1),
868 PINMUX_DATA(DREQ2_MARK, PORT193_FN2),
869 PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT193_FN5),
870 PINMUX_DATA(D26_MARK, PORT193_FN6),
871 PINMUX_DATA(ED26_MARK, PORT193_FN7),
872 PINMUX_DATA(LCDD19_MARK, PORT194_FN1),
873 PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT194_FN5),
874 PINMUX_DATA(D27_MARK, PORT194_FN6),
875 PINMUX_DATA(ED27_MARK, PORT194_FN7),
876 PINMUX_DATA(LCDD20_MARK, PORT195_FN1),
877 PINMUX_DATA(TS_SPSYNC1_MARK, PORT195_FN2),
878 PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT195_FN5),
879 PINMUX_DATA(D28_MARK, PORT195_FN6),
880 PINMUX_DATA(ED28_MARK, PORT195_FN7),
881 PINMUX_DATA(LCDD21_MARK, PORT196_FN1),
882 PINMUX_DATA(TS_SDAT1_MARK, PORT196_FN2),
883 PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT196_FN5),
884 PINMUX_DATA(D29_MARK, PORT196_FN6),
885 PINMUX_DATA(ED29_MARK, PORT196_FN7),
886 PINMUX_DATA(LCDD22_MARK, PORT197_FN1),
887 PINMUX_DATA(TS_SDEN1_MARK, PORT197_FN2),
888 PINMUX_DATA(MSIOF0L_SS1_MARK, PORT197_FN5),
889 PINMUX_DATA(D30_MARK, PORT197_FN6),
890 PINMUX_DATA(ED30_MARK, PORT197_FN7),
891 PINMUX_DATA(LCDD23_MARK, PORT198_FN1),
892 PINMUX_DATA(TS_SCK1_MARK, PORT198_FN2),
893 PINMUX_DATA(MSIOF0L_SS2_MARK, PORT198_FN5),
894 PINMUX_DATA(D31_MARK, PORT198_FN6),
895 PINMUX_DATA(ED31_MARK, PORT198_FN7),
896 PINMUX_DATA(LCDDCK_MARK, PORT199_FN1),
897 PINMUX_DATA(LCDWR_MARK, PORT199_FN2),
898 PINMUX_DATA(DV_CKO_MARK, PORT199_FN3),
899 PINMUX_DATA(SIUAOSPD_MARK, PORT199_FN4),
900 PINMUX_DATA(LCDRD_MARK, PORT200_FN1),
901 PINMUX_DATA(DACK2_MARK, PORT200_FN2),
902 PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT200_FN5),
903
904 /* 49-5 (FN) */
905 PINMUX_DATA(LCDHSYN_MARK, PORT201_FN1),
906 PINMUX_DATA(LCDCS_MARK, PORT201_FN2),
907 PINMUX_DATA(LCDCS2_MARK, PORT201_FN3),
908 PINMUX_DATA(DACK3_MARK, PORT201_FN4),
909 PINMUX_DATA(LCDDISP_MARK, PORT202_FN1),
910 PINMUX_DATA(LCDRS_MARK, PORT202_FN2),
911 PINMUX_DATA(DREQ3_MARK, PORT202_FN4),
912 PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT202_FN5),
913 PINMUX_DATA(LCDCSYN_MARK, PORT203_FN1),
914 PINMUX_DATA(LCDCSYN2_MARK, PORT203_FN2),
915 PINMUX_DATA(DV_CKI_MARK, PORT203_FN3),
916 PINMUX_DATA(LCDLCLK_MARK, PORT204_FN1),
917 PINMUX_DATA(DREQ1_MARK, PORT204_FN3),
918 PINMUX_DATA(MSIOF0L_RXD_MARK, PORT204_FN5),
919 PINMUX_DATA(LCDDON_MARK, PORT205_FN1),
920 PINMUX_DATA(LCDDON2_MARK, PORT205_FN2),
921 PINMUX_DATA(DACK1_MARK, PORT205_FN3),
922 PINMUX_DATA(MSIOF0L_TXD_MARK, PORT205_FN5),
923 PINMUX_DATA(VIO_DR0_MARK, PORT206_FN1),
924 PINMUX_DATA(VIO_DR1_MARK, PORT207_FN1),
925 PINMUX_DATA(VIO_DR2_MARK, PORT208_FN1),
926 PINMUX_DATA(VIO_DR3_MARK, PORT209_FN1),
927 PINMUX_DATA(VIO_DR4_MARK, PORT210_FN1),
928 PINMUX_DATA(VIO_DR5_MARK, PORT211_FN1),
929 PINMUX_DATA(VIO_DR6_MARK, PORT212_FN1),
930 PINMUX_DATA(VIO_DR7_MARK, PORT213_FN1),
931 PINMUX_DATA(VIO_VDR_MARK, PORT214_FN1),
932 PINMUX_DATA(VIO_HDR_MARK, PORT215_FN1),
933 PINMUX_DATA(VIO_CLKR_MARK, PORT216_FN1),
934 PINMUX_DATA(VIO_CKOR_MARK, PORT217_FN1),
935 PINMUX_DATA(SCIFA1_TXD_MARK, PORT220_FN2),
936 PINMUX_DATA(GPS_PGFA0_MARK, PORT220_FN3),
937 PINMUX_DATA(SCIFA1_SCK_MARK, PORT221_FN2),
938 PINMUX_DATA(GPS_PGFA1_MARK, PORT221_FN3),
939 PINMUX_DATA(SCIFA1_RTS_MARK, PORT222_FN2),
940 PINMUX_DATA(GPS_EPPSINMON_MARK, PORT222_FN3),
941 PINMUX_DATA(SCIFA1_RXD_MARK, PORT223_FN2),
942 PINMUX_DATA(SCIFA1_CTS_MARK, PORT224_FN2),
943 PINMUX_DATA(MSIOF1_TXD_MARK, PORT225_FN1),
944 PINMUX_DATA(SCIFA1_TXD2_MARK, PORT225_FN2),
945 PINMUX_DATA(GPS_TXD_MARK, PORT225_FN3),
946 PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT226_FN1),
947 PINMUX_DATA(SCIFA1_CTS2_MARK, PORT226_FN2),
948 PINMUX_DATA(I2C_SDA2_MARK, PORT226_FN3),
949 PINMUX_DATA(MSIOF1_TSCK_MARK, PORT227_FN1),
950 PINMUX_DATA(SCIFA1_SCK2_MARK, PORT227_FN2),
951 PINMUX_DATA(MSIOF1_RXD_MARK, PORT228_FN1),
952 PINMUX_DATA(SCIFA1_RXD2_MARK, PORT228_FN2),
953 PINMUX_DATA(GPS_RXD_MARK, PORT228_FN3),
954 PINMUX_DATA(MSIOF1_RSCK_MARK, PORT229_FN1),
955 PINMUX_DATA(SCIFA1_RTS2_MARK, PORT229_FN2),
956 PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT230_FN1),
957 PINMUX_DATA(I2C_SCL2_MARK, PORT230_FN3),
958 PINMUX_DATA(MSIOF1_MCK0_MARK, PORT231_FN1),
959 PINMUX_DATA(MSIOF1_MCK1_MARK, PORT232_FN1),
960 PINMUX_DATA(MSIOF1_SS1_MARK, PORT233_FN1),
961 PINMUX_DATA(EDBGREQ3_MARK, PORT233_FN2),
962 PINMUX_DATA(MSIOF1_SS2_MARK, PORT234_FN1),
963 PINMUX_DATA(PORT236_IROUT_MARK, PORT236_FN1),
964 PINMUX_DATA(IRDA_OUT_MARK, PORT236_FN2),
965 PINMUX_DATA(IRDA_IN_MARK, PORT237_FN2),
966 PINMUX_DATA(IRDA_FIRSEL_MARK, PORT238_FN1),
967 PINMUX_DATA(TPU1TO0_MARK, PORT239_FN3),
968 PINMUX_DATA(TS_SPSYNC3_MARK, PORT239_FN4),
969 PINMUX_DATA(TPU1TO1_MARK, PORT240_FN3),
970 PINMUX_DATA(TS_SDAT3_MARK, PORT240_FN4),
971 PINMUX_DATA(TPU1TO2_MARK, PORT241_FN3),
972 PINMUX_DATA(TS_SDEN3_MARK, PORT241_FN4),
973 PINMUX_DATA(PORT241_MSIOF2_SS1_MARK, PORT241_FN5),
974 PINMUX_DATA(TPU1TO3_MARK, PORT242_FN3),
975 PINMUX_DATA(PORT242_MSIOF2_TSCK_MARK, PORT242_FN5),
976 PINMUX_DATA(M13_BSW_MARK, PORT243_FN2),
977 PINMUX_DATA(PORT243_MSIOF2_TSYNC_MARK, PORT243_FN5),
978 PINMUX_DATA(M14_GSW_MARK, PORT244_FN2),
979 PINMUX_DATA(PORT244_MSIOF2_TXD_MARK, PORT244_FN5),
980 PINMUX_DATA(PORT245_IROUT_MARK, PORT245_FN1),
981 PINMUX_DATA(M15_RSW_MARK, PORT245_FN2),
982 PINMUX_DATA(SOUT3_MARK, PORT246_FN1),
983 PINMUX_DATA(SCIFA2_TXD1_MARK, PORT246_FN2),
984 PINMUX_DATA(SIN3_MARK, PORT247_FN1),
985 PINMUX_DATA(SCIFA2_RXD1_MARK, PORT247_FN2),
986 PINMUX_DATA(XRTS3_MARK, PORT248_FN1),
987 PINMUX_DATA(SCIFA2_RTS1_MARK, PORT248_FN2),
988 PINMUX_DATA(PORT248_MSIOF2_SS2_MARK, PORT248_FN5),
989 PINMUX_DATA(XCTS3_MARK, PORT249_FN1),
990 PINMUX_DATA(SCIFA2_CTS1_MARK, PORT249_FN2),
991 PINMUX_DATA(PORT249_MSIOF2_RXD_MARK, PORT249_FN5),
992 PINMUX_DATA(DINT_MARK, PORT250_FN1),
993 PINMUX_DATA(SCIFA2_SCK1_MARK, PORT250_FN2),
994 PINMUX_DATA(TS_SCK3_MARK, PORT250_FN4),
995 PINMUX_DATA(SDHICLK0_MARK, PORT251_FN1),
996 PINMUX_DATA(TCK2_MARK, PORT251_FN2),
997 PINMUX_DATA(SDHICD0_MARK, PORT252_FN1),
998 PINMUX_DATA(SDHID0_0_MARK, PORT253_FN1),
999 PINMUX_DATA(TMS2_MARK, PORT253_FN2),
1000 PINMUX_DATA(SDHID0_1_MARK, PORT254_FN1),
1001 PINMUX_DATA(TDO2_MARK, PORT254_FN2),
1002 PINMUX_DATA(SDHID0_2_MARK, PORT255_FN1),
1003 PINMUX_DATA(TDI2_MARK, PORT255_FN2),
1004 PINMUX_DATA(SDHID0_3_MARK, PORT256_FN1),
1005 PINMUX_DATA(RTCK2_MARK, PORT256_FN2),
1006
1007 /* 49-6 (FN) */
1008 PINMUX_DATA(SDHICMD0_MARK, PORT257_FN1),
1009 PINMUX_DATA(TRST2_MARK, PORT257_FN2),
1010 PINMUX_DATA(SDHIWP0_MARK, PORT258_FN1),
1011 PINMUX_DATA(EDBGREQ2_MARK, PORT258_FN2),
1012 PINMUX_DATA(SDHICLK1_MARK, PORT259_FN1),
1013 PINMUX_DATA(TCK3_MARK, PORT259_FN4),
1014 PINMUX_DATA(SDHID1_0_MARK, PORT260_FN1),
1015 PINMUX_DATA(M11_SLCD_SO2_MARK, PORT260_FN2),
1016 PINMUX_DATA(TS_SPSYNC2_MARK, PORT260_FN3),
1017 PINMUX_DATA(TMS3_MARK, PORT260_FN4),
1018 PINMUX_DATA(SDHID1_1_MARK, PORT261_FN1),
1019 PINMUX_DATA(M9_SLCD_AO2_MARK, PORT261_FN2),
1020 PINMUX_DATA(TS_SDAT2_MARK, PORT261_FN3),
1021 PINMUX_DATA(TDO3_MARK, PORT261_FN4),
1022 PINMUX_DATA(SDHID1_2_MARK, PORT262_FN1),
1023 PINMUX_DATA(M10_SLCD_CK2_MARK, PORT262_FN2),
1024 PINMUX_DATA(TS_SDEN2_MARK, PORT262_FN3),
1025 PINMUX_DATA(TDI3_MARK, PORT262_FN4),
1026 PINMUX_DATA(SDHID1_3_MARK, PORT263_FN1),
1027 PINMUX_DATA(M12_SLCD_CE2_MARK, PORT263_FN2),
1028 PINMUX_DATA(TS_SCK2_MARK, PORT263_FN3),
1029 PINMUX_DATA(RTCK3_MARK, PORT263_FN4),
1030 PINMUX_DATA(SDHICMD1_MARK, PORT264_FN1),
1031 PINMUX_DATA(TRST3_MARK, PORT264_FN4),
1032 PINMUX_DATA(SDHICLK2_MARK, PORT265_FN1),
1033 PINMUX_DATA(SCIFB_SCK_MARK, PORT265_FN2),
1034 PINMUX_DATA(SDHID2_0_MARK, PORT266_FN1),
1035 PINMUX_DATA(SCIFB_TXD_MARK, PORT266_FN2),
1036 PINMUX_DATA(SDHID2_1_MARK, PORT267_FN1),
1037 PINMUX_DATA(SCIFB_CTS_MARK, PORT267_FN2),
1038 PINMUX_DATA(SDHID2_2_MARK, PORT268_FN1),
1039 PINMUX_DATA(SCIFB_RXD_MARK, PORT268_FN2),
1040 PINMUX_DATA(SDHID2_3_MARK, PORT269_FN1),
1041 PINMUX_DATA(SCIFB_RTS_MARK, PORT269_FN2),
1042 PINMUX_DATA(SDHICMD2_MARK, PORT270_FN1),
1043 PINMUX_DATA(RESETOUTS_MARK, PORT271_FN1),
1044 PINMUX_DATA(DIVLOCK_MARK, PORT272_FN1),
1045};
1046
1047static struct pinmux_gpio pinmux_gpios[] = {
1048 /* 49-1 -> 49-6 (GPIO) */
1049 GPIO_PORT_ALL(),
1050
1051 /* Special Pull-up / Pull-down Functions */
1052 GPIO_FN(PORT48_KEYIN0_PU), GPIO_FN(PORT49_KEYIN1_PU),
1053 GPIO_FN(PORT50_KEYIN2_PU), GPIO_FN(PORT55_KEYIN3_PU),
1054 GPIO_FN(PORT56_KEYIN4_PU), GPIO_FN(PORT57_KEYIN5_PU),
1055 GPIO_FN(PORT58_KEYIN6_PU),
1056
1057 /* 49-1 (FN) */
1058 GPIO_FN(VBUS0), GPIO_FN(CPORT0), GPIO_FN(CPORT1), GPIO_FN(CPORT2),
1059 GPIO_FN(CPORT3), GPIO_FN(CPORT4), GPIO_FN(CPORT5), GPIO_FN(CPORT6),
1060 GPIO_FN(CPORT7), GPIO_FN(CPORT8), GPIO_FN(CPORT9), GPIO_FN(CPORT10),
1061 GPIO_FN(CPORT11), GPIO_FN(SIN2), GPIO_FN(CPORT12), GPIO_FN(XCTS2),
1062 GPIO_FN(CPORT13), GPIO_FN(RFSPO4), GPIO_FN(CPORT14), GPIO_FN(RFSPO5),
1063 GPIO_FN(CPORT15), GPIO_FN(CPORT16), GPIO_FN(CPORT17), GPIO_FN(SOUT2),
1064 GPIO_FN(CPORT18), GPIO_FN(XRTS2), GPIO_FN(CPORT19), GPIO_FN(CPORT20),
1065 GPIO_FN(RFSPO6), GPIO_FN(CPORT21), GPIO_FN(STATUS0), GPIO_FN(CPORT22),
1066 GPIO_FN(STATUS1), GPIO_FN(CPORT23), GPIO_FN(STATUS2), GPIO_FN(RFSPO7),
1067 GPIO_FN(MPORT0), GPIO_FN(MPORT1), GPIO_FN(B_SYNLD1), GPIO_FN(B_SYNLD2),
1068 GPIO_FN(XMAINPS), GPIO_FN(XDIVPS), GPIO_FN(XIDRST), GPIO_FN(IDCLK),
1069 GPIO_FN(IDIO), GPIO_FN(SOUT1), GPIO_FN(SCIFA4_TXD),
1070 GPIO_FN(M02_BERDAT), GPIO_FN(SIN1), GPIO_FN(SCIFA4_RXD), GPIO_FN(XWUP),
1071 GPIO_FN(XRTS1), GPIO_FN(SCIFA4_RTS), GPIO_FN(M03_BERCLK),
1072 GPIO_FN(XCTS1), GPIO_FN(SCIFA4_CTS),
1073
1074 /* 49-2 (FN) */
1075 GPIO_FN(HSU_IQ_AGC6), GPIO_FN(MFG2_IN2), GPIO_FN(MSIOF2_MCK0),
1076 GPIO_FN(HSU_IQ_AGC5), GPIO_FN(MFG2_IN1), GPIO_FN(MSIOF2_MCK1),
1077 GPIO_FN(HSU_IQ_AGC4), GPIO_FN(MSIOF2_RSYNC),
1078 GPIO_FN(HSU_IQ_AGC3), GPIO_FN(MFG2_OUT1), GPIO_FN(MSIOF2_RSCK),
1079 GPIO_FN(HSU_IQ_AGC2), GPIO_FN(PORT42_KEYOUT0),
1080 GPIO_FN(HSU_IQ_AGC1), GPIO_FN(PORT43_KEYOUT1),
1081 GPIO_FN(HSU_IQ_AGC0), GPIO_FN(PORT44_KEYOUT2),
1082 GPIO_FN(HSU_IQ_AGC_ST), GPIO_FN(PORT45_KEYOUT3),
1083 GPIO_FN(HSU_IQ_PDO), GPIO_FN(PORT46_KEYOUT4),
1084 GPIO_FN(HSU_IQ_PYO), GPIO_FN(PORT47_KEYOUT5),
1085 GPIO_FN(HSU_EN_TXMUX_G3MO), GPIO_FN(PORT48_KEYIN0),
1086 GPIO_FN(HSU_I_TXMUX_G3MO), GPIO_FN(PORT49_KEYIN1),
1087 GPIO_FN(HSU_Q_TXMUX_G3MO), GPIO_FN(PORT50_KEYIN2),
1088 GPIO_FN(HSU_SYO), GPIO_FN(PORT51_MSIOF2_TSYNC),
1089 GPIO_FN(HSU_SDO), GPIO_FN(PORT52_MSIOF2_TSCK),
1090 GPIO_FN(HSU_TGTTI_G3MO), GPIO_FN(PORT53_MSIOF2_TXD),
1091 GPIO_FN(B_TIME_STAMP), GPIO_FN(PORT54_MSIOF2_RXD),
1092 GPIO_FN(HSU_SDI), GPIO_FN(PORT55_KEYIN3),
1093 GPIO_FN(HSU_SCO), GPIO_FN(PORT56_KEYIN4),
1094 GPIO_FN(HSU_DREQ), GPIO_FN(PORT57_KEYIN5),
1095 GPIO_FN(HSU_DACK), GPIO_FN(PORT58_KEYIN6),
1096 GPIO_FN(HSU_CLK61M), GPIO_FN(PORT59_MSIOF2_SS1),
1097 GPIO_FN(HSU_XRST), GPIO_FN(PORT60_MSIOF2_SS2),
1098 GPIO_FN(PCMCLKO), GPIO_FN(SYNC8KO), GPIO_FN(DNPCM_A), GPIO_FN(UPPCM_A),
1099 GPIO_FN(XTALB1L),
1100 GPIO_FN(GPS_AGC1), GPIO_FN(SCIFA0_RTS),
1101 GPIO_FN(GPS_AGC2), GPIO_FN(SCIFA0_SCK),
1102 GPIO_FN(GPS_AGC3), GPIO_FN(SCIFA0_TXD),
1103 GPIO_FN(GPS_AGC4), GPIO_FN(SCIFA0_RXD),
1104 GPIO_FN(GPS_PWRD), GPIO_FN(SCIFA0_CTS),
1105 GPIO_FN(GPS_IM), GPIO_FN(GPS_IS), GPIO_FN(GPS_QM), GPIO_FN(GPS_QS),
1106 GPIO_FN(SIUBOMC), GPIO_FN(TPU2TO0),
1107 GPIO_FN(SIUCKB), GPIO_FN(TPU2TO1),
1108 GPIO_FN(SIUBOLR), GPIO_FN(BBIF2_TSYNC), GPIO_FN(TPU2TO2),
1109 GPIO_FN(SIUBOBT), GPIO_FN(BBIF2_TSCK), GPIO_FN(TPU2TO3),
1110 GPIO_FN(SIUBOSLD), GPIO_FN(BBIF2_TXD), GPIO_FN(TPU3TO0),
1111 GPIO_FN(SIUBILR), GPIO_FN(TPU3TO1),
1112 GPIO_FN(SIUBIBT), GPIO_FN(TPU3TO2),
1113 GPIO_FN(SIUBISLD), GPIO_FN(TPU3TO3),
1114 GPIO_FN(NMI), GPIO_FN(TPU4TO0),
1115 GPIO_FN(DNPCM_M), GPIO_FN(TPU4TO1), GPIO_FN(TPU4TO2), GPIO_FN(TPU4TO3),
1116 GPIO_FN(IRQ_TMPB),
1117 GPIO_FN(PWEN), GPIO_FN(MFG1_OUT1),
1118 GPIO_FN(OVCN), GPIO_FN(MFG1_IN1),
1119 GPIO_FN(OVCN2), GPIO_FN(MFG1_IN2),
1120
1121 /* 49-3 (FN) */
1122 GPIO_FN(RFSPO1), GPIO_FN(RFSPO2), GPIO_FN(RFSPO3),
1123 GPIO_FN(PORT93_VIO_CKO2),
1124 GPIO_FN(USBTERM), GPIO_FN(EXTLP), GPIO_FN(IDIN),
1125 GPIO_FN(SCIFA5_CTS), GPIO_FN(MFG0_IN1),
1126 GPIO_FN(SCIFA5_RTS), GPIO_FN(MFG0_IN2),
1127 GPIO_FN(SCIFA5_RXD),
1128 GPIO_FN(SCIFA5_TXD),
1129 GPIO_FN(SCIFA5_SCK), GPIO_FN(MFG0_OUT1),
1130 GPIO_FN(A0_EA0), GPIO_FN(BS),
1131 GPIO_FN(A14_EA14), GPIO_FN(PORT102_KEYOUT0),
1132 GPIO_FN(A15_EA15), GPIO_FN(PORT103_KEYOUT1), GPIO_FN(DV_CLKOL),
1133 GPIO_FN(A16_EA16), GPIO_FN(PORT104_KEYOUT2),
1134 GPIO_FN(DV_VSYNCL), GPIO_FN(MSIOF0_SS1),
1135 GPIO_FN(A17_EA17), GPIO_FN(PORT105_KEYOUT3),
1136 GPIO_FN(DV_HSYNCL), GPIO_FN(MSIOF0_TSYNC),
1137 GPIO_FN(A18_EA18), GPIO_FN(PORT106_KEYOUT4),
1138 GPIO_FN(DV_DL0), GPIO_FN(MSIOF0_TSCK),
1139 GPIO_FN(A19_EA19), GPIO_FN(PORT107_KEYOUT5),
1140 GPIO_FN(DV_DL1), GPIO_FN(MSIOF0_TXD),
1141 GPIO_FN(A20_EA20), GPIO_FN(PORT108_KEYIN0),
1142 GPIO_FN(DV_DL2), GPIO_FN(MSIOF0_RSCK),
1143 GPIO_FN(A21_EA21), GPIO_FN(PORT109_KEYIN1),
1144 GPIO_FN(DV_DL3), GPIO_FN(MSIOF0_RSYNC),
1145 GPIO_FN(A22_EA22), GPIO_FN(PORT110_KEYIN2),
1146 GPIO_FN(DV_DL4), GPIO_FN(MSIOF0_MCK0),
1147 GPIO_FN(A23_EA23), GPIO_FN(PORT111_KEYIN3),
1148 GPIO_FN(DV_DL5), GPIO_FN(MSIOF0_MCK1),
1149 GPIO_FN(A24_EA24), GPIO_FN(PORT112_KEYIN4),
1150 GPIO_FN(DV_DL6), GPIO_FN(MSIOF0_RXD),
1151 GPIO_FN(A25_EA25), GPIO_FN(PORT113_KEYIN5),
1152 GPIO_FN(DV_DL7), GPIO_FN(MSIOF0_SS2),
1153 GPIO_FN(A26), GPIO_FN(PORT113_KEYIN6), GPIO_FN(DV_CLKIL),
1154 GPIO_FN(D0_ED0_NAF0), GPIO_FN(D1_ED1_NAF1), GPIO_FN(D2_ED2_NAF2),
1155 GPIO_FN(D3_ED3_NAF3), GPIO_FN(D4_ED4_NAF4), GPIO_FN(D5_ED5_NAF5),
1156 GPIO_FN(D6_ED6_NAF6), GPIO_FN(D7_ED7_NAF7), GPIO_FN(D8_ED8_NAF8),
1157 GPIO_FN(D9_ED9_NAF9), GPIO_FN(D10_ED10_NAF10), GPIO_FN(D11_ED11_NAF11),
1158 GPIO_FN(D12_ED12_NAF12), GPIO_FN(D13_ED13_NAF13),
1159 GPIO_FN(D14_ED14_NAF14), GPIO_FN(D15_ED15_NAF15),
1160 GPIO_FN(CS4), GPIO_FN(CS5A), GPIO_FN(CS5B), GPIO_FN(FCE1),
1161 GPIO_FN(CS6B), GPIO_FN(XCS2), GPIO_FN(FCE0), GPIO_FN(CS6A),
1162 GPIO_FN(DACK0), GPIO_FN(WAIT), GPIO_FN(DREQ0), GPIO_FN(RD_XRD),
1163 GPIO_FN(A27), GPIO_FN(RDWR_XWE), GPIO_FN(WE0_XWR0_FWE),
1164 GPIO_FN(WE1_XWR1), GPIO_FN(FRB), GPIO_FN(CKO),
1165 GPIO_FN(NBRSTOUT), GPIO_FN(NBRST),
1166
1167 /* 49-4 (FN) */
1168 GPIO_FN(RFSPO0), GPIO_FN(PORT146_VIO_CKO2), GPIO_FN(TSTMD),
1169 GPIO_FN(VIO_VD), GPIO_FN(VIO_HD),
1170 GPIO_FN(VIO_D0), GPIO_FN(VIO_D1), GPIO_FN(VIO_D2),
1171 GPIO_FN(VIO_D3), GPIO_FN(VIO_D4), GPIO_FN(VIO_D5),
1172 GPIO_FN(VIO_D6), GPIO_FN(VIO_D7), GPIO_FN(VIO_D8),
1173 GPIO_FN(VIO_D9), GPIO_FN(VIO_D10), GPIO_FN(VIO_D11),
1174 GPIO_FN(VIO_D12), GPIO_FN(VIO_D13), GPIO_FN(VIO_D14),
1175 GPIO_FN(VIO_D15), GPIO_FN(VIO_CLK), GPIO_FN(VIO_FIELD),
1176 GPIO_FN(VIO_CKO),
1177 GPIO_FN(MFG3_IN1), GPIO_FN(MFG3_IN2),
1178 GPIO_FN(M9_SLCD_A01), GPIO_FN(MFG3_OUT1), GPIO_FN(TPU0TO0),
1179 GPIO_FN(M10_SLCD_CK1), GPIO_FN(MFG4_IN1), GPIO_FN(TPU0TO1),
1180 GPIO_FN(M11_SLCD_SO1), GPIO_FN(MFG4_IN2), GPIO_FN(TPU0TO2),
1181 GPIO_FN(M12_SLCD_CE1), GPIO_FN(MFG4_OUT1), GPIO_FN(TPU0TO3),
1182 GPIO_FN(LCDD0), GPIO_FN(PORT175_KEYOUT0), GPIO_FN(DV_D0),
1183 GPIO_FN(SIUCKA), GPIO_FN(MFG0_OUT2),
1184 GPIO_FN(LCDD1), GPIO_FN(PORT176_KEYOUT1), GPIO_FN(DV_D1),
1185 GPIO_FN(SIUAOLR), GPIO_FN(BBIF2_TSYNC1),
1186 GPIO_FN(LCDD2), GPIO_FN(PORT177_KEYOUT2), GPIO_FN(DV_D2),
1187 GPIO_FN(SIUAOBT), GPIO_FN(BBIF2_TSCK1),
1188 GPIO_FN(LCDD3), GPIO_FN(PORT178_KEYOUT3), GPIO_FN(DV_D3),
1189 GPIO_FN(SIUAOSLD), GPIO_FN(BBIF2_TXD1),
1190 GPIO_FN(LCDD4), GPIO_FN(PORT179_KEYOUT4), GPIO_FN(DV_D4),
1191 GPIO_FN(SIUAISPD), GPIO_FN(MFG1_OUT2),
1192 GPIO_FN(LCDD5), GPIO_FN(PORT180_KEYOUT5), GPIO_FN(DV_D5),
1193 GPIO_FN(SIUAILR), GPIO_FN(MFG2_OUT2),
1194 GPIO_FN(LCDD6), GPIO_FN(DV_D6),
1195 GPIO_FN(SIUAIBT), GPIO_FN(MFG3_OUT2), GPIO_FN(XWR2),
1196 GPIO_FN(LCDD7), GPIO_FN(DV_D7),
1197 GPIO_FN(SIUAISLD), GPIO_FN(MFG4_OUT2), GPIO_FN(XWR3),
1198 GPIO_FN(LCDD8), GPIO_FN(DV_D8), GPIO_FN(D16), GPIO_FN(ED16),
1199 GPIO_FN(LCDD9), GPIO_FN(DV_D9), GPIO_FN(D17), GPIO_FN(ED17),
1200 GPIO_FN(LCDD10), GPIO_FN(DV_D10), GPIO_FN(D18), GPIO_FN(ED18),
1201 GPIO_FN(LCDD11), GPIO_FN(DV_D11), GPIO_FN(D19), GPIO_FN(ED19),
1202 GPIO_FN(LCDD12), GPIO_FN(DV_D12), GPIO_FN(D20), GPIO_FN(ED20),
1203 GPIO_FN(LCDD13), GPIO_FN(DV_D13), GPIO_FN(D21), GPIO_FN(ED21),
1204 GPIO_FN(LCDD14), GPIO_FN(DV_D14), GPIO_FN(D22), GPIO_FN(ED22),
1205 GPIO_FN(LCDD15), GPIO_FN(DV_D15), GPIO_FN(D23), GPIO_FN(ED23),
1206 GPIO_FN(LCDD16), GPIO_FN(DV_HSYNC), GPIO_FN(D24), GPIO_FN(ED24),
1207 GPIO_FN(LCDD17), GPIO_FN(DV_VSYNC), GPIO_FN(D25), GPIO_FN(ED25),
1208 GPIO_FN(LCDD18), GPIO_FN(DREQ2), GPIO_FN(MSIOF0L_TSCK),
1209 GPIO_FN(D26), GPIO_FN(ED26),
1210 GPIO_FN(LCDD19), GPIO_FN(MSIOF0L_TSYNC),
1211 GPIO_FN(D27), GPIO_FN(ED27),
1212 GPIO_FN(LCDD20), GPIO_FN(TS_SPSYNC1), GPIO_FN(MSIOF0L_MCK0),
1213 GPIO_FN(D28), GPIO_FN(ED28),
1214 GPIO_FN(LCDD21), GPIO_FN(TS_SDAT1), GPIO_FN(MSIOF0L_MCK1),
1215 GPIO_FN(D29), GPIO_FN(ED29),
1216 GPIO_FN(LCDD22), GPIO_FN(TS_SDEN1), GPIO_FN(MSIOF0L_SS1),
1217 GPIO_FN(D30), GPIO_FN(ED30),
1218 GPIO_FN(LCDD23), GPIO_FN(TS_SCK1), GPIO_FN(MSIOF0L_SS2),
1219 GPIO_FN(D31), GPIO_FN(ED31),
1220 GPIO_FN(LCDDCK), GPIO_FN(LCDWR), GPIO_FN(DV_CKO), GPIO_FN(SIUAOSPD),
1221 GPIO_FN(LCDRD), GPIO_FN(DACK2), GPIO_FN(MSIOF0L_RSYNC),
1222
1223 /* 49-5 (FN) */
1224 GPIO_FN(LCDHSYN), GPIO_FN(LCDCS), GPIO_FN(LCDCS2), GPIO_FN(DACK3),
1225 GPIO_FN(LCDDISP), GPIO_FN(LCDRS), GPIO_FN(DREQ3), GPIO_FN(MSIOF0L_RSCK),
1226 GPIO_FN(LCDCSYN), GPIO_FN(LCDCSYN2), GPIO_FN(DV_CKI),
1227 GPIO_FN(LCDLCLK), GPIO_FN(DREQ1), GPIO_FN(MSIOF0L_RXD),
1228 GPIO_FN(LCDDON), GPIO_FN(LCDDON2), GPIO_FN(DACK1), GPIO_FN(MSIOF0L_TXD),
1229 GPIO_FN(VIO_DR0), GPIO_FN(VIO_DR1), GPIO_FN(VIO_DR2), GPIO_FN(VIO_DR3),
1230 GPIO_FN(VIO_DR4), GPIO_FN(VIO_DR5), GPIO_FN(VIO_DR6), GPIO_FN(VIO_DR7),
1231 GPIO_FN(VIO_VDR), GPIO_FN(VIO_HDR),
1232 GPIO_FN(VIO_CLKR), GPIO_FN(VIO_CKOR),
1233 GPIO_FN(SCIFA1_TXD), GPIO_FN(GPS_PGFA0),
1234 GPIO_FN(SCIFA1_SCK), GPIO_FN(GPS_PGFA1),
1235 GPIO_FN(SCIFA1_RTS), GPIO_FN(GPS_EPPSINMON),
1236 GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_CTS),
1237 GPIO_FN(MSIOF1_TXD), GPIO_FN(SCIFA1_TXD2), GPIO_FN(GPS_TXD),
1238 GPIO_FN(MSIOF1_TSYNC), GPIO_FN(SCIFA1_CTS2), GPIO_FN(I2C_SDA2),
1239 GPIO_FN(MSIOF1_TSCK), GPIO_FN(SCIFA1_SCK2),
1240 GPIO_FN(MSIOF1_RXD), GPIO_FN(SCIFA1_RXD2), GPIO_FN(GPS_RXD),
1241 GPIO_FN(MSIOF1_RSCK), GPIO_FN(SCIFA1_RTS2),
1242 GPIO_FN(MSIOF1_RSYNC), GPIO_FN(I2C_SCL2),
1243 GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1),
1244 GPIO_FN(MSIOF1_SS1), GPIO_FN(EDBGREQ3),
1245 GPIO_FN(MSIOF1_SS2),
1246 GPIO_FN(PORT236_IROUT), GPIO_FN(IRDA_OUT),
1247 GPIO_FN(IRDA_IN), GPIO_FN(IRDA_FIRSEL),
1248 GPIO_FN(TPU1TO0), GPIO_FN(TS_SPSYNC3),
1249 GPIO_FN(TPU1TO1), GPIO_FN(TS_SDAT3),
1250 GPIO_FN(TPU1TO2), GPIO_FN(TS_SDEN3), GPIO_FN(PORT241_MSIOF2_SS1),
1251 GPIO_FN(TPU1TO3), GPIO_FN(PORT242_MSIOF2_TSCK),
1252 GPIO_FN(M13_BSW), GPIO_FN(PORT243_MSIOF2_TSYNC),
1253 GPIO_FN(M14_GSW), GPIO_FN(PORT244_MSIOF2_TXD),
1254 GPIO_FN(PORT245_IROUT), GPIO_FN(M15_RSW),
1255 GPIO_FN(SOUT3), GPIO_FN(SCIFA2_TXD1),
1256 GPIO_FN(SIN3), GPIO_FN(SCIFA2_RXD1),
1257 GPIO_FN(XRTS3), GPIO_FN(SCIFA2_RTS1), GPIO_FN(PORT248_MSIOF2_SS2),
1258 GPIO_FN(XCTS3), GPIO_FN(SCIFA2_CTS1), GPIO_FN(PORT249_MSIOF2_RXD),
1259 GPIO_FN(DINT), GPIO_FN(SCIFA2_SCK1), GPIO_FN(TS_SCK3),
1260 GPIO_FN(SDHICLK0), GPIO_FN(TCK2),
1261 GPIO_FN(SDHICD0),
1262 GPIO_FN(SDHID0_0), GPIO_FN(TMS2),
1263 GPIO_FN(SDHID0_1), GPIO_FN(TDO2),
1264 GPIO_FN(SDHID0_2), GPIO_FN(TDI2),
1265 GPIO_FN(SDHID0_3), GPIO_FN(RTCK2),
1266
1267 /* 49-6 (FN) */
1268 GPIO_FN(SDHICMD0), GPIO_FN(TRST2),
1269 GPIO_FN(SDHIWP0), GPIO_FN(EDBGREQ2),
1270 GPIO_FN(SDHICLK1), GPIO_FN(TCK3),
1271 GPIO_FN(SDHID1_0), GPIO_FN(M11_SLCD_SO2),
1272 GPIO_FN(TS_SPSYNC2), GPIO_FN(TMS3),
1273 GPIO_FN(SDHID1_1), GPIO_FN(M9_SLCD_AO2),
1274 GPIO_FN(TS_SDAT2), GPIO_FN(TDO3),
1275 GPIO_FN(SDHID1_2), GPIO_FN(M10_SLCD_CK2),
1276 GPIO_FN(TS_SDEN2), GPIO_FN(TDI3),
1277 GPIO_FN(SDHID1_3), GPIO_FN(M12_SLCD_CE2),
1278 GPIO_FN(TS_SCK2), GPIO_FN(RTCK3),
1279 GPIO_FN(SDHICMD1), GPIO_FN(TRST3),
1280 GPIO_FN(SDHICLK2), GPIO_FN(SCIFB_SCK),
1281 GPIO_FN(SDHID2_0), GPIO_FN(SCIFB_TXD),
1282 GPIO_FN(SDHID2_1), GPIO_FN(SCIFB_CTS),
1283 GPIO_FN(SDHID2_2), GPIO_FN(SCIFB_RXD),
1284 GPIO_FN(SDHID2_3), GPIO_FN(SCIFB_RTS),
1285 GPIO_FN(SDHICMD2),
1286 GPIO_FN(RESETOUTS),
1287 GPIO_FN(DIVLOCK),
1288};
1289
1290static struct pinmux_cfg_reg pinmux_config_regs[] = {
1291 PORTCR(0, 0xe6050000), /* PORT0CR */
1292 PORTCR(1, 0xe6050001), /* PORT1CR */
1293 PORTCR(2, 0xe6050002), /* PORT2CR */
1294 PORTCR(3, 0xe6050003), /* PORT3CR */
1295 PORTCR(4, 0xe6050004), /* PORT4CR */
1296 PORTCR(5, 0xe6050005), /* PORT5CR */
1297 PORTCR(6, 0xe6050006), /* PORT6CR */
1298 PORTCR(7, 0xe6050007), /* PORT7CR */
1299 PORTCR(8, 0xe6050008), /* PORT8CR */
1300 PORTCR(9, 0xe6050009), /* PORT9CR */
1301
1302 PORTCR(10, 0xe605000a), /* PORT10CR */
1303 PORTCR(11, 0xe605000b), /* PORT11CR */
1304 PORTCR(12, 0xe605000c), /* PORT12CR */
1305 PORTCR(13, 0xe605000d), /* PORT13CR */
1306 PORTCR(14, 0xe605000e), /* PORT14CR */
1307 PORTCR(15, 0xe605000f), /* PORT15CR */
1308 PORTCR(16, 0xe6050010), /* PORT16CR */
1309 PORTCR(17, 0xe6050011), /* PORT17CR */
1310 PORTCR(18, 0xe6050012), /* PORT18CR */
1311 PORTCR(19, 0xe6050013), /* PORT19CR */
1312
1313 PORTCR(20, 0xe6050014), /* PORT20CR */
1314 PORTCR(21, 0xe6050015), /* PORT21CR */
1315 PORTCR(22, 0xe6050016), /* PORT22CR */
1316 PORTCR(23, 0xe6050017), /* PORT23CR */
1317 PORTCR(24, 0xe6050018), /* PORT24CR */
1318 PORTCR(25, 0xe6050019), /* PORT25CR */
1319 PORTCR(26, 0xe605001a), /* PORT26CR */
1320 PORTCR(27, 0xe605001b), /* PORT27CR */
1321 PORTCR(28, 0xe605001c), /* PORT28CR */
1322 PORTCR(29, 0xe605001d), /* PORT29CR */
1323
1324 PORTCR(30, 0xe605001e), /* PORT30CR */
1325 PORTCR(31, 0xe605001f), /* PORT31CR */
1326 PORTCR(32, 0xe6050020), /* PORT32CR */
1327 PORTCR(33, 0xe6050021), /* PORT33CR */
1328 PORTCR(34, 0xe6050022), /* PORT34CR */
1329 PORTCR(35, 0xe6050023), /* PORT35CR */
1330 PORTCR(36, 0xe6050024), /* PORT36CR */
1331 PORTCR(37, 0xe6050025), /* PORT37CR */
1332 PORTCR(38, 0xe6050026), /* PORT38CR */
1333 PORTCR(39, 0xe6050027), /* PORT39CR */
1334
1335 PORTCR(40, 0xe6050028), /* PORT40CR */
1336 PORTCR(41, 0xe6050029), /* PORT41CR */
1337 PORTCR(42, 0xe605002a), /* PORT42CR */
1338 PORTCR(43, 0xe605002b), /* PORT43CR */
1339 PORTCR(44, 0xe605002c), /* PORT44CR */
1340 PORTCR(45, 0xe605002d), /* PORT45CR */
1341 PORTCR(46, 0xe605002e), /* PORT46CR */
1342 PORTCR(47, 0xe605002f), /* PORT47CR */
1343 PORTCR(48, 0xe6050030), /* PORT48CR */
1344 PORTCR(49, 0xe6050031), /* PORT49CR */
1345
1346 PORTCR(50, 0xe6050032), /* PORT50CR */
1347 PORTCR(51, 0xe6050033), /* PORT51CR */
1348 PORTCR(52, 0xe6050034), /* PORT52CR */
1349 PORTCR(53, 0xe6050035), /* PORT53CR */
1350 PORTCR(54, 0xe6050036), /* PORT54CR */
1351 PORTCR(55, 0xe6050037), /* PORT55CR */
1352 PORTCR(56, 0xe6050038), /* PORT56CR */
1353 PORTCR(57, 0xe6050039), /* PORT57CR */
1354 PORTCR(58, 0xe605003a), /* PORT58CR */
1355 PORTCR(59, 0xe605003b), /* PORT59CR */
1356
1357 PORTCR(60, 0xe605003c), /* PORT60CR */
1358 PORTCR(61, 0xe605003d), /* PORT61CR */
1359 PORTCR(62, 0xe605003e), /* PORT62CR */
1360 PORTCR(63, 0xe605003f), /* PORT63CR */
1361 PORTCR(64, 0xe6050040), /* PORT64CR */
1362 PORTCR(65, 0xe6050041), /* PORT65CR */
1363 PORTCR(66, 0xe6050042), /* PORT66CR */
1364 PORTCR(67, 0xe6050043), /* PORT67CR */
1365 PORTCR(68, 0xe6050044), /* PORT68CR */
1366 PORTCR(69, 0xe6050045), /* PORT69CR */
1367
1368 PORTCR(70, 0xe6050046), /* PORT70CR */
1369 PORTCR(71, 0xe6050047), /* PORT71CR */
1370 PORTCR(72, 0xe6050048), /* PORT72CR */
1371 PORTCR(73, 0xe6050049), /* PORT73CR */
1372 PORTCR(74, 0xe605004a), /* PORT74CR */
1373 PORTCR(75, 0xe605004b), /* PORT75CR */
1374 PORTCR(76, 0xe605004c), /* PORT76CR */
1375 PORTCR(77, 0xe605004d), /* PORT77CR */
1376 PORTCR(78, 0xe605004e), /* PORT78CR */
1377 PORTCR(79, 0xe605004f), /* PORT79CR */
1378
1379 PORTCR(80, 0xe6050050), /* PORT80CR */
1380 PORTCR(81, 0xe6050051), /* PORT81CR */
1381 PORTCR(82, 0xe6050052), /* PORT82CR */
1382 PORTCR(83, 0xe6050053), /* PORT83CR */
1383 PORTCR(84, 0xe6050054), /* PORT84CR */
1384 PORTCR(85, 0xe6050055), /* PORT85CR */
1385 PORTCR(86, 0xe6050056), /* PORT86CR */
1386 PORTCR(87, 0xe6050057), /* PORT87CR */
1387 PORTCR(88, 0xe6051058), /* PORT88CR */
1388 PORTCR(89, 0xe6051059), /* PORT89CR */
1389
1390 PORTCR(90, 0xe605105a), /* PORT90CR */
1391 PORTCR(91, 0xe605105b), /* PORT91CR */
1392 PORTCR(92, 0xe605105c), /* PORT92CR */
1393 PORTCR(93, 0xe605105d), /* PORT93CR */
1394 PORTCR(94, 0xe605105e), /* PORT94CR */
1395 PORTCR(95, 0xe605105f), /* PORT95CR */
1396 PORTCR(96, 0xe6051060), /* PORT96CR */
1397 PORTCR(97, 0xe6051061), /* PORT97CR */
1398 PORTCR(98, 0xe6051062), /* PORT98CR */
1399 PORTCR(99, 0xe6051063), /* PORT99CR */
1400
1401 PORTCR(100, 0xe6051064), /* PORT100CR */
1402 PORTCR(101, 0xe6051065), /* PORT101CR */
1403 PORTCR(102, 0xe6051066), /* PORT102CR */
1404 PORTCR(103, 0xe6051067), /* PORT103CR */
1405 PORTCR(104, 0xe6051068), /* PORT104CR */
1406 PORTCR(105, 0xe6051069), /* PORT105CR */
1407 PORTCR(106, 0xe605106a), /* PORT106CR */
1408 PORTCR(107, 0xe605106b), /* PORT107CR */
1409 PORTCR(108, 0xe605106c), /* PORT108CR */
1410 PORTCR(109, 0xe605106d), /* PORT109CR */
1411
1412 PORTCR(110, 0xe605106e), /* PORT110CR */
1413 PORTCR(111, 0xe605106f), /* PORT111CR */
1414 PORTCR(112, 0xe6051070), /* PORT112CR */
1415 PORTCR(113, 0xe6051071), /* PORT113CR */
1416 PORTCR(114, 0xe6051072), /* PORT114CR */
1417 PORTCR(115, 0xe6051073), /* PORT115CR */
1418 PORTCR(116, 0xe6051074), /* PORT116CR */
1419 PORTCR(117, 0xe6051075), /* PORT117CR */
1420 PORTCR(118, 0xe6051076), /* PORT118CR */
1421 PORTCR(119, 0xe6051077), /* PORT119CR */
1422
1423 PORTCR(120, 0xe6051078), /* PORT120CR */
1424 PORTCR(121, 0xe6051079), /* PORT121CR */
1425 PORTCR(122, 0xe605107a), /* PORT122CR */
1426 PORTCR(123, 0xe605107b), /* PORT123CR */
1427 PORTCR(124, 0xe605107c), /* PORT124CR */
1428 PORTCR(125, 0xe605107d), /* PORT125CR */
1429 PORTCR(126, 0xe605107e), /* PORT126CR */
1430 PORTCR(127, 0xe605107f), /* PORT127CR */
1431 PORTCR(128, 0xe6051080), /* PORT128CR */
1432 PORTCR(129, 0xe6051081), /* PORT129CR */
1433
1434 PORTCR(130, 0xe6051082), /* PORT130CR */
1435 PORTCR(131, 0xe6051083), /* PORT131CR */
1436 PORTCR(132, 0xe6051084), /* PORT132CR */
1437 PORTCR(133, 0xe6051085), /* PORT133CR */
1438 PORTCR(134, 0xe6051086), /* PORT134CR */
1439 PORTCR(135, 0xe6051087), /* PORT135CR */
1440 PORTCR(136, 0xe6051088), /* PORT136CR */
1441 PORTCR(137, 0xe6051089), /* PORT137CR */
1442 PORTCR(138, 0xe605108a), /* PORT138CR */
1443 PORTCR(139, 0xe605108b), /* PORT139CR */
1444
1445 PORTCR(140, 0xe605108c), /* PORT140CR */
1446 PORTCR(141, 0xe605108d), /* PORT141CR */
1447 PORTCR(142, 0xe605108e), /* PORT142CR */
1448 PORTCR(143, 0xe605108f), /* PORT143CR */
1449 PORTCR(144, 0xe6051090), /* PORT144CR */
1450 PORTCR(145, 0xe6051091), /* PORT145CR */
1451 PORTCR(146, 0xe6051092), /* PORT146CR */
1452 PORTCR(147, 0xe6051093), /* PORT147CR */
1453 PORTCR(148, 0xe6051094), /* PORT148CR */
1454 PORTCR(149, 0xe6051095), /* PORT149CR */
1455
1456 PORTCR(150, 0xe6051096), /* PORT150CR */
1457 PORTCR(151, 0xe6051097), /* PORT151CR */
1458 PORTCR(152, 0xe6051098), /* PORT152CR */
1459 PORTCR(153, 0xe6051099), /* PORT153CR */
1460 PORTCR(154, 0xe605109a), /* PORT154CR */
1461 PORTCR(155, 0xe605109b), /* PORT155CR */
1462 PORTCR(156, 0xe605109c), /* PORT156CR */
1463 PORTCR(157, 0xe605109d), /* PORT157CR */
1464 PORTCR(158, 0xe605109e), /* PORT158CR */
1465 PORTCR(159, 0xe605109f), /* PORT159CR */
1466
1467 PORTCR(160, 0xe60510a0), /* PORT160CR */
1468 PORTCR(161, 0xe60510a1), /* PORT161CR */
1469 PORTCR(162, 0xe60510a2), /* PORT162CR */
1470 PORTCR(163, 0xe60510a3), /* PORT163CR */
1471 PORTCR(164, 0xe60510a4), /* PORT164CR */
1472 PORTCR(165, 0xe60510a5), /* PORT165CR */
1473 PORTCR(166, 0xe60510a6), /* PORT166CR */
1474 PORTCR(167, 0xe60510a7), /* PORT167CR */
1475 PORTCR(168, 0xe60510a8), /* PORT168CR */
1476 PORTCR(169, 0xe60510a9), /* PORT169CR */
1477
1478 PORTCR(170, 0xe60510aa), /* PORT170CR */
1479 PORTCR(171, 0xe60510ab), /* PORT171CR */
1480 PORTCR(172, 0xe60510ac), /* PORT172CR */
1481 PORTCR(173, 0xe60510ad), /* PORT173CR */
1482 PORTCR(174, 0xe60510ae), /* PORT174CR */
1483 PORTCR(175, 0xe60520af), /* PORT175CR */
1484 PORTCR(176, 0xe60520b0), /* PORT176CR */
1485 PORTCR(177, 0xe60520b1), /* PORT177CR */
1486 PORTCR(178, 0xe60520b2), /* PORT178CR */
1487 PORTCR(179, 0xe60520b3), /* PORT179CR */
1488
1489 PORTCR(180, 0xe60520b4), /* PORT180CR */
1490 PORTCR(181, 0xe60520b5), /* PORT181CR */
1491 PORTCR(182, 0xe60520b6), /* PORT182CR */
1492 PORTCR(183, 0xe60520b7), /* PORT183CR */
1493 PORTCR(184, 0xe60520b8), /* PORT184CR */
1494 PORTCR(185, 0xe60520b9), /* PORT185CR */
1495 PORTCR(186, 0xe60520ba), /* PORT186CR */
1496 PORTCR(187, 0xe60520bb), /* PORT187CR */
1497 PORTCR(188, 0xe60520bc), /* PORT188CR */
1498 PORTCR(189, 0xe60520bd), /* PORT189CR */
1499
1500 PORTCR(190, 0xe60520be), /* PORT190CR */
1501 PORTCR(191, 0xe60520bf), /* PORT191CR */
1502 PORTCR(192, 0xe60520c0), /* PORT192CR */
1503 PORTCR(193, 0xe60520c1), /* PORT193CR */
1504 PORTCR(194, 0xe60520c2), /* PORT194CR */
1505 PORTCR(195, 0xe60520c3), /* PORT195CR */
1506 PORTCR(196, 0xe60520c4), /* PORT196CR */
1507 PORTCR(197, 0xe60520c5), /* PORT197CR */
1508 PORTCR(198, 0xe60520c6), /* PORT198CR */
1509 PORTCR(199, 0xe60520c7), /* PORT199CR */
1510
1511 PORTCR(200, 0xe60520c8), /* PORT200CR */
1512 PORTCR(201, 0xe60520c9), /* PORT201CR */
1513 PORTCR(202, 0xe60520ca), /* PORT202CR */
1514 PORTCR(203, 0xe60520cb), /* PORT203CR */
1515 PORTCR(204, 0xe60520cc), /* PORT204CR */
1516 PORTCR(205, 0xe60520cd), /* PORT205CR */
1517 PORTCR(206, 0xe60520ce), /* PORT206CR */
1518 PORTCR(207, 0xe60520cf), /* PORT207CR */
1519 PORTCR(208, 0xe60520d0), /* PORT208CR */
1520 PORTCR(209, 0xe60520d1), /* PORT209CR */
1521
1522 PORTCR(210, 0xe60520d2), /* PORT210CR */
1523 PORTCR(211, 0xe60520d3), /* PORT211CR */
1524 PORTCR(212, 0xe60520d4), /* PORT212CR */
1525 PORTCR(213, 0xe60520d5), /* PORT213CR */
1526 PORTCR(214, 0xe60520d6), /* PORT214CR */
1527 PORTCR(215, 0xe60520d7), /* PORT215CR */
1528 PORTCR(216, 0xe60520d8), /* PORT216CR */
1529 PORTCR(217, 0xe60520d9), /* PORT217CR */
1530 PORTCR(218, 0xe60520da), /* PORT218CR */
1531 PORTCR(219, 0xe60520db), /* PORT219CR */
1532
1533 PORTCR(220, 0xe60520dc), /* PORT220CR */
1534 PORTCR(221, 0xe60520dd), /* PORT221CR */
1535 PORTCR(222, 0xe60520de), /* PORT222CR */
1536 PORTCR(223, 0xe60520df), /* PORT223CR */
1537 PORTCR(224, 0xe60520e0), /* PORT224CR */
1538 PORTCR(225, 0xe60520e1), /* PORT225CR */
1539 PORTCR(226, 0xe60520e2), /* PORT226CR */
1540 PORTCR(227, 0xe60520e3), /* PORT227CR */
1541 PORTCR(228, 0xe60520e4), /* PORT228CR */
1542 PORTCR(229, 0xe60520e5), /* PORT229CR */
1543
1544 PORTCR(230, 0xe60520e6), /* PORT230CR */
1545 PORTCR(231, 0xe60520e7), /* PORT231CR */
1546 PORTCR(232, 0xe60520e8), /* PORT232CR */
1547 PORTCR(233, 0xe60520e9), /* PORT233CR */
1548 PORTCR(234, 0xe60520ea), /* PORT234CR */
1549 PORTCR(235, 0xe60520eb), /* PORT235CR */
1550 PORTCR(236, 0xe60530ec), /* PORT236CR */
1551 PORTCR(237, 0xe60530ed), /* PORT237CR */
1552 PORTCR(238, 0xe60530ee), /* PORT238CR */
1553 PORTCR(239, 0xe60530ef), /* PORT239CR */
1554
1555 PORTCR(240, 0xe60530f0), /* PORT240CR */
1556 PORTCR(241, 0xe60530f1), /* PORT241CR */
1557 PORTCR(242, 0xe60530f2), /* PORT242CR */
1558 PORTCR(243, 0xe60530f3), /* PORT243CR */
1559 PORTCR(244, 0xe60530f4), /* PORT244CR */
1560 PORTCR(245, 0xe60530f5), /* PORT245CR */
1561 PORTCR(246, 0xe60530f6), /* PORT246CR */
1562 PORTCR(247, 0xe60530f7), /* PORT247CR */
1563 PORTCR(248, 0xe60530f8), /* PORT248CR */
1564 PORTCR(249, 0xe60530f9), /* PORT249CR */
1565
1566 PORTCR(250, 0xe60530fa), /* PORT250CR */
1567 PORTCR(251, 0xe60530fb), /* PORT251CR */
1568 PORTCR(252, 0xe60530fc), /* PORT252CR */
1569 PORTCR(253, 0xe60530fd), /* PORT253CR */
1570 PORTCR(254, 0xe60530fe), /* PORT254CR */
1571 PORTCR(255, 0xe60530ff), /* PORT255CR */
1572 PORTCR(256, 0xe6053100), /* PORT256CR */
1573 PORTCR(257, 0xe6053101), /* PORT257CR */
1574 PORTCR(258, 0xe6053102), /* PORT258CR */
1575 PORTCR(259, 0xe6053103), /* PORT259CR */
1576
1577 PORTCR(260, 0xe6053104), /* PORT260CR */
1578 PORTCR(261, 0xe6053105), /* PORT261CR */
1579 PORTCR(262, 0xe6053106), /* PORT262CR */
1580 PORTCR(263, 0xe6053107), /* PORT263CR */
1581 PORTCR(264, 0xe6053108), /* PORT264CR */
1582 PORTCR(265, 0xe6053109), /* PORT265CR */
1583 PORTCR(266, 0xe605310a), /* PORT266CR */
1584 PORTCR(267, 0xe605310b), /* PORT267CR */
1585 PORTCR(268, 0xe605310c), /* PORT268CR */
1586 PORTCR(269, 0xe605310d), /* PORT269CR */
1587
1588 PORTCR(270, 0xe605310e), /* PORT270CR */
1589 PORTCR(271, 0xe605310f), /* PORT271CR */
1590 PORTCR(272, 0xe6053110), /* PORT272CR */
1591
1592 { PINMUX_CFG_REG("MSELBCR", 0xe6058024, 32, 1) {
1593 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1594 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1595 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1596 0, 0,
1597 0, 0,
1598 0, 0,
1599 0, 0,
1600 0, 0,
1601 MSELBCR_MSEL2_0, MSELBCR_MSEL2_1,
1602 0, 0,
1603 0, 0 }
1604 },
1605 { },
1606};
1607
1608static struct pinmux_data_reg pinmux_data_regs[] = {
1609 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
1610 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
1611 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
1612 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
1613 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
1614 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
1615 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
1616 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
1617 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
1618 },
1619 { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054004, 32) {
1620 PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
1621 PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
1622 PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
1623 PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
1624 PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
1625 PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
1626 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
1627 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
1628 },
1629 { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054008, 32) {
1630 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
1631 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
1632 PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
1633 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
1634 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
1635 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
1636 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
1637 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
1638 },
1639 { PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32) {
1640 PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
1641 PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
1642 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
1643 PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
1644 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
1645 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
1646 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
1647 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
1648 },
1649 { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32) {
1650 PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
1651 PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
1652 PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
1653 PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
1654 PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
1655 PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
1656 PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
1657 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
1658 },
1659 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32) {
1660 PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
1661 PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
1662 PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
1663 PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
1664 PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
1665 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
1666 PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
1667 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
1668 },
1669 { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32) {
1670 PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
1671 PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
1672 PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
1673 PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
1674 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
1675 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
1676 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
1677 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
1678 },
1679 { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) {
1680 PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
1681 PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
1682 PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
1683 PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
1684 PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
1685 PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
1686 PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
1687 PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
1688 },
1689 { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) {
1690 0, 0, 0, 0,
1691 0, 0, 0, 0,
1692 0, 0, 0, 0,
1693 0, 0, 0, PORT272_DATA,
1694 PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
1695 PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
1696 PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
1697 PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
1698 },
1699 { },
1700};
1701
1702static struct pinmux_info sh7367_pinmux_info = {
1703 .name = "sh7367_pfc",
1704 .reserved_id = PINMUX_RESERVED,
1705 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
1706 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
1707 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
1708 .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
1709 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
1710 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
1711 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1712
1713 .first_gpio = GPIO_PORT0,
1714 .last_gpio = GPIO_FN_DIVLOCK,
1715
1716 .gpios = pinmux_gpios,
1717 .cfg_regs = pinmux_config_regs,
1718 .data_regs = pinmux_data_regs,
1719
1720 .gpio_data = pinmux_data,
1721 .gpio_data_size = ARRAY_SIZE(pinmux_data),
1722};
1723
1724void sh7367_pinmux_init(void)
1725{
1726 register_pinmux(&sh7367_pinmux_info);
1727}
diff --git a/arch/arm/mach-shmobile/pfc-sh7377.c b/arch/arm/mach-shmobile/pfc-sh7377.c
deleted file mode 100644
index f3117f67fa25..000000000000
--- a/arch/arm/mach-shmobile/pfc-sh7377.c
+++ /dev/null
@@ -1,1688 +0,0 @@
1/*
2 * sh7377 processor support - PFC hardware block
3 *
4 * Copyright (C) 2010 NISHIMOTO Hiroki
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of the
9 * License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/sh_pfc.h>
23#include <mach/sh7377.h>
24
25#define CPU_ALL_PORT(fn, pfx, sfx) \
26 PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
27 PORT_10(fn, pfx##10, sfx), \
28 PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \
29 PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \
30 PORT_1(fn, pfx##114, sfx), PORT_1(fn, pfx##115, sfx), \
31 PORT_1(fn, pfx##116, sfx), PORT_1(fn, pfx##117, sfx), \
32 PORT_1(fn, pfx##118, sfx), \
33 PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \
34 PORT_10(fn, pfx##13, sfx), PORT_10(fn, pfx##14, sfx), \
35 PORT_10(fn, pfx##15, sfx), \
36 PORT_1(fn, pfx##160, sfx), PORT_1(fn, pfx##161, sfx), \
37 PORT_1(fn, pfx##162, sfx), PORT_1(fn, pfx##163, sfx), \
38 PORT_1(fn, pfx##164, sfx), \
39 PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \
40 PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \
41 PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \
42 PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \
43 PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx), \
44 PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx), \
45 PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx), \
46 PORT_1(fn, pfx##260, sfx), PORT_1(fn, pfx##261, sfx), \
47 PORT_1(fn, pfx##262, sfx), PORT_1(fn, pfx##263, sfx), \
48 PORT_1(fn, pfx##264, sfx)
49
50enum {
51 PINMUX_RESERVED = 0,
52
53 PINMUX_DATA_BEGIN,
54 PORT_ALL(DATA), /* PORT0_DATA -> PORT264_DATA */
55 PINMUX_DATA_END,
56
57 PINMUX_INPUT_BEGIN,
58 PORT_ALL(IN), /* PORT0_IN -> PORT264_IN */
59 PINMUX_INPUT_END,
60
61 PINMUX_INPUT_PULLUP_BEGIN,
62 PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT264_IN_PU */
63 PINMUX_INPUT_PULLUP_END,
64
65 PINMUX_INPUT_PULLDOWN_BEGIN,
66 PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT264_IN_PD */
67 PINMUX_INPUT_PULLDOWN_END,
68
69 PINMUX_OUTPUT_BEGIN,
70 PORT_ALL(OUT), /* PORT0_OUT -> PORT264_OUT */
71 PINMUX_OUTPUT_END,
72
73 PINMUX_FUNCTION_BEGIN,
74 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT264_FN_IN */
75 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT264_FN_OUT */
76 PORT_ALL(FN0), /* PORT0_FN0 -> PORT264_FN0 */
77 PORT_ALL(FN1), /* PORT0_FN1 -> PORT264_FN1 */
78 PORT_ALL(FN2), /* PORT0_FN2 -> PORT264_FN2 */
79 PORT_ALL(FN3), /* PORT0_FN3 -> PORT264_FN3 */
80 PORT_ALL(FN4), /* PORT0_FN4 -> PORT264_FN4 */
81 PORT_ALL(FN5), /* PORT0_FN5 -> PORT264_FN5 */
82 PORT_ALL(FN6), /* PORT0_FN6 -> PORT264_FN6 */
83 PORT_ALL(FN7), /* PORT0_FN7 -> PORT264_FN7 */
84
85 MSELBCR_MSEL17_1, MSELBCR_MSEL17_0,
86 MSELBCR_MSEL16_1, MSELBCR_MSEL16_0,
87 PINMUX_FUNCTION_END,
88
89 PINMUX_MARK_BEGIN,
90 /* Special Pull-up / Pull-down Functions */
91 PORT66_KEYIN0_PU_MARK, PORT67_KEYIN1_PU_MARK,
92 PORT68_KEYIN2_PU_MARK, PORT69_KEYIN3_PU_MARK,
93 PORT70_KEYIN4_PU_MARK, PORT71_KEYIN5_PU_MARK,
94 PORT72_KEYIN6_PU_MARK,
95
96 /* 55-1 */
97 VBUS_0_MARK,
98 CPORT0_MARK,
99 CPORT1_MARK,
100 CPORT2_MARK,
101 CPORT3_MARK,
102 CPORT4_MARK,
103 CPORT5_MARK,
104 CPORT6_MARK,
105 CPORT7_MARK,
106 CPORT8_MARK,
107 CPORT9_MARK,
108 CPORT10_MARK,
109 CPORT11_MARK, SIN2_MARK,
110 CPORT12_MARK, XCTS2_MARK,
111 CPORT13_MARK, RFSPO4_MARK,
112 CPORT14_MARK, RFSPO5_MARK,
113 CPORT15_MARK, SCIFA0_SCK_MARK, GPS_AGC2_MARK,
114 CPORT16_MARK, SCIFA0_TXD_MARK, GPS_AGC3_MARK,
115 CPORT17_IC_OE_MARK, SOUT2_MARK,
116 CPORT18_MARK, XRTS2_MARK, PORT19_VIO_CKO2_MARK,
117 CPORT19_MPORT1_MARK,
118 CPORT20_MARK, RFSPO6_MARK,
119 CPORT21_MARK, STATUS0_MARK,
120 CPORT22_MARK, STATUS1_MARK,
121 CPORT23_MARK, STATUS2_MARK, RFSPO7_MARK,
122 B_SYNLD1_MARK,
123 B_SYNLD2_MARK, SYSENMSK_MARK,
124 XMAINPS_MARK,
125 XDIVPS_MARK,
126 XIDRST_MARK,
127 IDCLK_MARK, IC_DP_MARK,
128 IDIO_MARK, IC_DM_MARK,
129 SOUT1_MARK, SCIFA4_TXD_MARK, M02_BERDAT_MARK,
130 SIN1_MARK, SCIFA4_RXD_MARK, XWUP_MARK,
131 XRTS1_MARK, SCIFA4_RTS_MARK, M03_BERCLK_MARK,
132 XCTS1_MARK, SCIFA4_CTS_MARK,
133 PCMCLKO_MARK,
134 SYNC8KO_MARK,
135
136 /* 55-2 */
137 DNPCM_A_MARK,
138 UPPCM_A_MARK,
139 VACK_MARK,
140 XTALB1L_MARK,
141 GPS_AGC1_MARK, SCIFA0_RTS_MARK,
142 GPS_AGC4_MARK, SCIFA0_RXD_MARK,
143 GPS_PWRDOWN_MARK, SCIFA0_CTS_MARK,
144 GPS_IM_MARK,
145 GPS_IS_MARK,
146 GPS_QM_MARK,
147 GPS_QS_MARK,
148 FMSOCK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK,
149 FMSOOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, IPORT3_MARK,
150 FMSIOLR_MARK,
151 FMSOOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, OPORT1_MARK,
152 FMSIOBT_MARK,
153 FMSOSLD_MARK, BBIF2_TXD2_MARK, OPORT2_MARK,
154 FMSOILR_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, OPORT3_MARK,
155 FMSIILR_MARK,
156 FMSOIBT_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FMSIIBT_MARK,
157 FMSISLD_MARK, MFG0_OUT1_MARK, TPU0TO0_MARK,
158 A0_EA0_MARK, BS_MARK,
159 A12_EA12_MARK, PORT58_VIO_CKOR_MARK, TPU4TO2_MARK,
160 A13_EA13_MARK, PORT59_IROUT_MARK, MFG0_OUT2_MARK, TPU0TO1_MARK,
161 A14_EA14_MARK, PORT60_KEYOUT5_MARK,
162 A15_EA15_MARK, PORT61_KEYOUT4_MARK,
163 A16_EA16_MARK, PORT62_KEYOUT3_MARK, MSIOF0_SS1_MARK,
164 A17_EA17_MARK, PORT63_KEYOUT2_MARK, MSIOF0_TSYNC_MARK,
165 A18_EA18_MARK, PORT64_KEYOUT1_MARK, MSIOF0_TSCK_MARK,
166 A19_EA19_MARK, PORT65_KEYOUT0_MARK, MSIOF0_TXD_MARK,
167 A20_EA20_MARK, PORT66_KEYIN0_MARK, MSIOF0_RSCK_MARK,
168 A21_EA21_MARK, PORT67_KEYIN1_MARK, MSIOF0_RSYNC_MARK,
169 A22_EA22_MARK, PORT68_KEYIN2_MARK, MSIOF0_MCK0_MARK,
170 A23_EA23_MARK, PORT69_KEYIN3_MARK, MSIOF0_MCK1_MARK,
171 A24_EA24_MARK, PORT70_KEYIN4_MARK, MSIOF0_RXD_MARK,
172 A25_EA25_MARK, PORT71_KEYIN5_MARK, MSIOF0_SS2_MARK,
173 A26_MARK, PORT72_KEYIN6_MARK,
174 D0_ED0_NAF0_MARK,
175 D1_ED1_NAF1_MARK,
176 D2_ED2_NAF2_MARK,
177 D3_ED3_NAF3_MARK,
178 D4_ED4_NAF4_MARK,
179 D5_ED5_NAF5_MARK,
180 D6_ED6_NAF6_MARK,
181 D7_ED7_NAF7_MARK,
182 D8_ED8_NAF8_MARK,
183 D9_ED9_NAF9_MARK,
184 D10_ED10_NAF10_MARK,
185 D11_ED11_NAF11_MARK,
186 D12_ED12_NAF12_MARK,
187 D13_ED13_NAF13_MARK,
188 D14_ED14_NAF14_MARK,
189 D15_ED15_NAF15_MARK,
190 CS4_MARK,
191 CS5A_MARK, FMSICK_MARK,
192 CS5B_MARK, FCE1_MARK,
193
194 /* 55-3 */
195 CS6B_MARK, XCS2_MARK, CS6A_MARK, DACK0_MARK,
196 FCE0_MARK,
197 WAIT_MARK, DREQ0_MARK,
198 RD_XRD_MARK,
199 WE0_XWR0_FWE_MARK,
200 WE1_XWR1_MARK,
201 FRB_MARK,
202 CKO_MARK,
203 NBRSTOUT_MARK,
204 NBRST_MARK,
205 GPS_EPPSIN_MARK,
206 LATCHPULSE_MARK,
207 LTESIGNAL_MARK,
208 LEGACYSTATE_MARK,
209 TCKON_MARK,
210 VIO_VD_MARK, PORT128_KEYOUT0_MARK, IPORT0_MARK,
211 VIO_HD_MARK, PORT129_KEYOUT1_MARK, IPORT1_MARK,
212 VIO_D0_MARK, PORT130_KEYOUT2_MARK, PORT130_MSIOF2_RXD_MARK,
213 VIO_D1_MARK, PORT131_KEYOUT3_MARK, PORT131_MSIOF2_SS1_MARK,
214 VIO_D2_MARK, PORT132_KEYOUT4_MARK, PORT132_MSIOF2_SS2_MARK,
215 VIO_D3_MARK, PORT133_KEYOUT5_MARK, PORT133_MSIOF2_TSYNC_MARK,
216 VIO_D4_MARK, PORT134_KEYIN0_MARK, PORT134_MSIOF2_TXD_MARK,
217 VIO_D5_MARK, PORT135_KEYIN1_MARK, PORT135_MSIOF2_TSCK_MARK,
218 VIO_D6_MARK, PORT136_KEYIN2_MARK,
219 VIO_D7_MARK, PORT137_KEYIN3_MARK,
220 VIO_D8_MARK, M9_SLCD_A01_MARK, PORT138_FSIAOMC_MARK,
221 VIO_D9_MARK, M10_SLCD_CK1_MARK, PORT139_FSIAOLR_MARK,
222 VIO_D10_MARK, M11_SLCD_SO1_MARK, TPU0TO2_MARK, PORT140_FSIAOBT_MARK,
223 VIO_D11_MARK, M12_SLCD_CE1_MARK, TPU0TO3_MARK, PORT141_FSIAOSLD_MARK,
224 VIO_D12_MARK, M13_BSW_MARK, PORT142_FSIACK_MARK,
225 VIO_D13_MARK, M14_GSW_MARK, PORT143_FSIAILR_MARK,
226 VIO_D14_MARK, M15_RSW_MARK, PORT144_FSIAIBT_MARK,
227 VIO_D15_MARK, TPU1TO3_MARK, PORT145_FSIAISLD_MARK,
228 VIO_CLK_MARK, PORT146_KEYIN4_MARK, IPORT2_MARK,
229 VIO_FIELD_MARK, PORT147_KEYIN5_MARK,
230 VIO_CKO_MARK, PORT148_KEYIN6_MARK,
231 A27_MARK, RDWR_XWE_MARK, MFG0_IN1_MARK,
232 MFG0_IN2_MARK,
233 TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK,
234 TS_SDAT3_MARK, MSIOF2_RSYNC_MARK,
235 TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK,
236 SOUT3_MARK, SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK,
237 SIN3_MARK, SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK,
238 XRTS3_MARK, SCIFA2_RTS1_MARK, PORT156_MSIOF2_SS2_MARK,
239 XCTS3_MARK, SCIFA2_CTS1_MARK, PORT157_MSIOF2_RXD_MARK,
240
241 /* 55-4 */
242 DINT_MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
243 PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK,
244 PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK, SOUT0_MARK,
245 PORT161_SCIFB_CTS_MARK, PORT161_SCIFA5_CTS_MARK, XCTS0_MARK,
246 MFG3_IN2_MARK,
247 PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK, SIN0_MARK,
248 MFG3_IN1_MARK,
249 PORT163_SCIFB_RTS_MARK, PORT163_SCIFA5_RTS_MARK, XRTS0_MARK,
250 MFG3_OUT1_MARK, TPU3TO0_MARK,
251 LCDD0_MARK, PORT192_KEYOUT0_MARK, EXT_CKI_MARK,
252 LCDD1_MARK, PORT193_KEYOUT1_MARK, PORT193_SCIFA5_CTS_MARK,
253 BBIF2_TSYNC1_MARK,
254 LCDD2_MARK, PORT194_KEYOUT2_MARK, PORT194_SCIFA5_RTS_MARK,
255 BBIF2_TSCK1_MARK,
256 LCDD3_MARK, PORT195_KEYOUT3_MARK, PORT195_SCIFA5_RXD_MARK,
257 BBIF2_TXD1_MARK,
258 LCDD4_MARK, PORT196_KEYOUT4_MARK, PORT196_SCIFA5_TXD_MARK,
259 LCDD5_MARK, PORT197_KEYOUT5_MARK, PORT197_SCIFA5_SCK_MARK,
260 MFG2_OUT2_MARK,
261 TPU2TO1_MARK,
262 LCDD6_MARK, XWR2_MARK,
263 LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK, XWR3_MARK,
264 LCDD8_MARK, PORT200_KEYIN0_MARK, VIO_DR0_MARK, D16_MARK, ED16_MARK,
265 LCDD9_MARK, PORT201_KEYIN1_MARK, VIO_DR1_MARK, D17_MARK, ED17_MARK,
266 LCDD10_MARK, PORT202_KEYIN2_MARK, VIO_DR2_MARK, D18_MARK, ED18_MARK,
267 LCDD11_MARK, PORT203_KEYIN3_MARK, VIO_DR3_MARK, D19_MARK, ED19_MARK,
268 LCDD12_MARK, PORT204_KEYIN4_MARK, VIO_DR4_MARK, D20_MARK, ED20_MARK,
269 LCDD13_MARK, PORT205_KEYIN5_MARK, VIO_DR5_MARK, D21_MARK, ED21_MARK,
270 LCDD14_MARK, PORT206_KEYIN6_MARK, VIO_DR6_MARK, D22_MARK, ED22_MARK,
271 LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, PORT207_KEYOUT0_MARK,
272 VIO_DR7_MARK, D23_MARK, ED23_MARK,
273 LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, PORT208_KEYOUT1_MARK,
274 VIO_VDR_MARK, D24_MARK, ED24_MARK,
275 LCDD17_MARK, PORT209_KEYOUT2_MARK, VIO_HDR_MARK, D25_MARK, ED25_MARK,
276 LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK, ED26_MARK,
277 LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK, ED27_MARK,
278 LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK, ED28_MARK,
279 LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK, ED29_MARK,
280 LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK, ED30_MARK,
281 LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK, ED31_MARK,
282 LCDDCK_MARK, LCDWR_MARK, PORT216_KEYOUT3_MARK, VIO_CLKR_MARK,
283 LCDRD_MARK, DACK2_MARK, MSIOF0L_TSYNC_MARK,
284 LCDHSYN_MARK, LCDCS_MARK, LCDCS2_MARK, DACK3_MARK,
285 PORT218_VIO_CKOR_MARK, PORT218_KEYOUT4_MARK,
286 LCDDISP_MARK, LCDRS_MARK, DREQ3_MARK, MSIOF0L_TSCK_MARK,
287 LCDVSYN_MARK, LCDVSYN2_MARK, PORT220_KEYOUT5_MARK,
288 LCDLCLK_MARK, DREQ1_MARK, PWEN_MARK, MSIOF0L_RXD_MARK,
289 LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK,
290 SCIFA1_TXD_MARK, OVCN2_MARK,
291 EXTLP_MARK, SCIFA1_SCK_MARK, USBTERM_MARK, PORT226_VIO_CKO2_MARK,
292 SCIFA1_RTS_MARK, IDIN_MARK,
293 SCIFA1_RXD_MARK,
294 SCIFA1_CTS_MARK, MFG1_IN1_MARK,
295 MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK, PORT230_FSIAOMC_MARK,
296 MSIOF1_TSYNC_MARK, SCIFA2_CTS2_MARK, PORT231_FSIAOLR_MARK,
297 MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK, PORT232_FSIAOBT_MARK,
298 MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK, GPS_VCOTRIG_MARK,
299 PORT233_FSIACK_MARK,
300 MSIOF1_RSCK_MARK, SCIFA2_RTS2_MARK, PORT234_FSIAOSLD_MARK,
301 MSIOF1_RSYNC_MARK, OPORT0_MARK, MFG1_IN2_MARK, PORT235_FSIAILR_MARK,
302 MSIOF1_MCK0_MARK, I2C_SDA2_MARK, PORT236_FSIAIBT_MARK,
303 MSIOF1_MCK1_MARK, I2C_SCL2_MARK, PORT237_FSIAISLD_MARK,
304 MSIOF1_SS1_MARK, EDBGREQ3_MARK,
305
306 /* 55-5 */
307 MSIOF1_SS2_MARK,
308 SCIFA6_TXD_MARK,
309 PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK,
310 TPU4TO0_MARK,
311 PORT242_IRDA_IN_MARK, MFG4_IN2_MARK,
312 PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK,
313 PORT244_SCIFA5_CTS_MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS_MARK,
314 PORT244_MSIOF2_RXD_MARK,
315 PORT245_SCIFA5_RTS_MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS_MARK,
316 PORT245_MSIOF2_TXD_MARK,
317 PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK,
318 TPU1TO0_MARK,
319 PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK,
320 TPU3TO1_MARK,
321 PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK,
322 TPU2TO0_MARK,
323 PORT248_MSIOF2_TSCK_MARK,
324 PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_MSIOF2_TSYNC_MARK,
325 SDHICLK0_MARK, TCK2_SWCLK_MC0_MARK,
326 SDHICD0_MARK,
327 SDHID0_0_MARK, TMS2_SWDIO_MC0_MARK,
328 SDHID0_1_MARK, TDO2_SWO0_MC0_MARK,
329 SDHID0_2_MARK, TDI2_MARK,
330 SDHID0_3_MARK, RTCK2_SWO1_MC0_MARK,
331 SDHICMD0_MARK, TRST2_MARK,
332 SDHIWP0_MARK, EDBGREQ2_MARK,
333 SDHICLK1_MARK, TCK3_SWCLK_MC1_MARK,
334 SDHID1_0_MARK, M11_SLCD_SO2_MARK, TS_SPSYNC2_MARK,
335 TMS3_SWDIO_MC1_MARK,
336 SDHID1_1_MARK, M9_SLCD_A02_MARK, TS_SDAT2_MARK, TDO3_SWO0_MC1_MARK,
337 SDHID1_2_MARK, M10_SLCD_CK2_MARK, TS_SDEN2_MARK, TDI3_MARK,
338 SDHID1_3_MARK, M12_SLCD_CE2_MARK, TS_SCK2_MARK, RTCK3_SWO1_MC1_MARK,
339 SDHICMD1_MARK, TRST3_MARK,
340 RESETOUTS_MARK,
341 PINMUX_MARK_END,
342};
343
344static pinmux_enum_t pinmux_data[] = {
345 /* specify valid pin states for each pin in GPIO mode */
346 /* 55-1 (GPIO) */
347 PORT_DATA_I_PD(0), PORT_DATA_I_PU(1),
348 PORT_DATA_I_PU(2), PORT_DATA_I_PU(3),
349 PORT_DATA_I_PU(4), PORT_DATA_I_PU(5),
350 PORT_DATA_I_PU(6), PORT_DATA_I_PU(7),
351 PORT_DATA_I_PU(8), PORT_DATA_I_PU(9),
352 PORT_DATA_I_PU(10), PORT_DATA_I_PU(11),
353 PORT_DATA_IO_PU(12), PORT_DATA_IO_PU(13),
354 PORT_DATA_IO_PU_PD(14), PORT_DATA_IO_PU_PD(15),
355 PORT_DATA_O(16), PORT_DATA_IO(17),
356 PORT_DATA_O(18), PORT_DATA_O(19),
357 PORT_DATA_O(20), PORT_DATA_O(21),
358 PORT_DATA_O(22), PORT_DATA_O(23),
359 PORT_DATA_O(24), PORT_DATA_I_PD(25),
360 PORT_DATA_I_PD(26), PORT_DATA_O(27),
361 PORT_DATA_O(28), PORT_DATA_O(29),
362 PORT_DATA_IO(30), PORT_DATA_IO_PU(31),
363 PORT_DATA_IO_PD(32), PORT_DATA_I_PU(33),
364 PORT_DATA_IO_PD(34), PORT_DATA_I_PU_PD(35),
365 PORT_DATA_O(36), PORT_DATA_IO(37),
366
367 /* 55-2 (GPIO) */
368 PORT_DATA_O(38), PORT_DATA_I_PU(39),
369 PORT_DATA_I_PU_PD(40), PORT_DATA_O(41),
370 PORT_DATA_IO_PD(42), PORT_DATA_IO_PD(43),
371 PORT_DATA_IO_PD(44), PORT_DATA_I_PD(45),
372 PORT_DATA_I_PD(46), PORT_DATA_I_PD(47),
373 PORT_DATA_I_PD(48), PORT_DATA_IO_PU_PD(49),
374 PORT_DATA_IO_PD(50), PORT_DATA_IO_PD(51),
375 PORT_DATA_O(52), PORT_DATA_IO_PU_PD(53),
376 PORT_DATA_IO_PU_PD(54), PORT_DATA_IO_PD(55),
377 PORT_DATA_I_PU_PD(56), PORT_DATA_IO(57),
378 PORT_DATA_IO(58), PORT_DATA_IO(59),
379 PORT_DATA_IO(60), PORT_DATA_IO(61),
380 PORT_DATA_IO_PD(62), PORT_DATA_IO_PD(63),
381 PORT_DATA_IO_PD(64), PORT_DATA_IO_PD(65),
382 PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67),
383 PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69),
384 PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71),
385 PORT_DATA_IO_PU_PD(72), PORT_DATA_I_PU_PD(73),
386 PORT_DATA_IO_PU(74), PORT_DATA_IO_PU(75),
387 PORT_DATA_IO_PU(76), PORT_DATA_IO_PU(77),
388 PORT_DATA_IO_PU(78), PORT_DATA_IO_PU(79),
389 PORT_DATA_IO_PU(80), PORT_DATA_IO_PU(81),
390 PORT_DATA_IO_PU(82), PORT_DATA_IO_PU(83),
391 PORT_DATA_IO_PU(84), PORT_DATA_IO_PU(85),
392 PORT_DATA_IO_PU(86), PORT_DATA_IO_PU(87),
393 PORT_DATA_IO_PU(88), PORT_DATA_IO_PU(89),
394 PORT_DATA_O(90), PORT_DATA_IO_PU(91),
395 PORT_DATA_O(92),
396
397 /* 55-3 (GPIO) */
398 PORT_DATA_IO_PU(93),
399 PORT_DATA_O(94),
400 PORT_DATA_I_PU_PD(95),
401 PORT_DATA_IO(96), PORT_DATA_IO(97),
402 PORT_DATA_IO(98), PORT_DATA_I_PU(99),
403 PORT_DATA_O(100), PORT_DATA_O(101),
404 PORT_DATA_I_PU(102), PORT_DATA_IO_PD(103),
405 PORT_DATA_I_PD(104), PORT_DATA_I_PD(105),
406 PORT_DATA_I_PD(106), PORT_DATA_I_PD(107),
407 PORT_DATA_I_PD(108), PORT_DATA_IO_PD(109),
408 PORT_DATA_IO_PD(110), PORT_DATA_I_PD(111),
409 PORT_DATA_IO_PD(112), PORT_DATA_IO_PD(113),
410 PORT_DATA_IO_PD(114), PORT_DATA_I_PD(115),
411 PORT_DATA_I_PD(116), PORT_DATA_IO_PD(117),
412 PORT_DATA_I_PD(118), PORT_DATA_IO_PD(128),
413 PORT_DATA_IO_PD(129), PORT_DATA_IO_PD(130),
414 PORT_DATA_IO_PD(131), PORT_DATA_IO_PD(132),
415 PORT_DATA_IO_PD(133), PORT_DATA_IO_PU_PD(134),
416 PORT_DATA_IO_PU_PD(135), PORT_DATA_IO_PU_PD(136),
417 PORT_DATA_IO_PU_PD(137), PORT_DATA_IO_PD(138),
418 PORT_DATA_IO_PD(139), PORT_DATA_IO_PD(140),
419 PORT_DATA_IO_PD(141), PORT_DATA_IO_PD(142),
420 PORT_DATA_IO_PD(143), PORT_DATA_IO_PU_PD(144),
421 PORT_DATA_IO_PD(145), PORT_DATA_IO_PU_PD(146),
422 PORT_DATA_IO_PU_PD(147), PORT_DATA_IO_PU_PD(148),
423 PORT_DATA_IO_PU_PD(149), PORT_DATA_I_PD(150),
424 PORT_DATA_IO_PU_PD(151), PORT_DATA_IO_PD(152),
425 PORT_DATA_IO_PD(153), PORT_DATA_IO_PD(154),
426 PORT_DATA_I_PD(155), PORT_DATA_IO_PU_PD(156),
427 PORT_DATA_I_PD(157), PORT_DATA_IO_PD(158),
428
429 /* 55-4 (GPIO) */
430 PORT_DATA_IO_PU_PD(159), PORT_DATA_IO_PU_PD(160),
431 PORT_DATA_I_PU_PD(161), PORT_DATA_I_PU_PD(162),
432 PORT_DATA_IO_PU_PD(163), PORT_DATA_I_PU_PD(164),
433 PORT_DATA_IO_PD(192), PORT_DATA_IO_PD(193),
434 PORT_DATA_IO_PD(194), PORT_DATA_IO_PD(195),
435 PORT_DATA_IO_PD(196), PORT_DATA_IO_PD(197),
436 PORT_DATA_IO_PD(198), PORT_DATA_IO_PD(199),
437 PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU_PD(201),
438 PORT_DATA_IO_PU_PD(202), PORT_DATA_IO_PU_PD(203),
439 PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205),
440 PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PD(207),
441 PORT_DATA_IO_PD(208), PORT_DATA_IO_PD(209),
442 PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211),
443 PORT_DATA_IO_PD(212), PORT_DATA_IO_PD(213),
444 PORT_DATA_IO_PD(214), PORT_DATA_IO_PD(215),
445 PORT_DATA_IO_PD(216), PORT_DATA_IO_PD(217),
446 PORT_DATA_O(218), PORT_DATA_IO_PD(219),
447 PORT_DATA_IO_PD(220), PORT_DATA_IO_PD(221),
448 PORT_DATA_IO_PU_PD(222),
449 PORT_DATA_I_PU_PD(223), PORT_DATA_I_PU_PD(224),
450 PORT_DATA_IO_PU_PD(225), PORT_DATA_O(226),
451 PORT_DATA_IO_PU_PD(227), PORT_DATA_I_PD(228),
452 PORT_DATA_I_PD(229), PORT_DATA_IO(230),
453 PORT_DATA_IO_PD(231), PORT_DATA_IO_PU_PD(232),
454 PORT_DATA_I_PD(233), PORT_DATA_IO_PU_PD(234),
455 PORT_DATA_IO_PU_PD(235), PORT_DATA_IO_PU_PD(236),
456 PORT_DATA_IO_PD(237), PORT_DATA_IO_PU_PD(238),
457
458 /* 55-5 (GPIO) */
459 PORT_DATA_IO_PU_PD(239), PORT_DATA_IO_PU_PD(240),
460 PORT_DATA_O(241), PORT_DATA_I_PD(242),
461 PORT_DATA_IO_PU_PD(243), PORT_DATA_IO_PU_PD(244),
462 PORT_DATA_IO_PU_PD(245), PORT_DATA_IO_PU_PD(246),
463 PORT_DATA_IO_PU_PD(247), PORT_DATA_IO_PU_PD(248),
464 PORT_DATA_IO_PU_PD(249), PORT_DATA_IO_PD(250),
465 PORT_DATA_IO_PU_PD(251), PORT_DATA_IO_PU_PD(252),
466 PORT_DATA_IO_PU_PD(253), PORT_DATA_IO_PU_PD(254),
467 PORT_DATA_IO_PU_PD(255), PORT_DATA_IO_PU_PD(256),
468 PORT_DATA_IO_PU_PD(257), PORT_DATA_IO_PD(258),
469 PORT_DATA_IO_PU_PD(259), PORT_DATA_IO_PU_PD(260),
470 PORT_DATA_IO_PU_PD(261), PORT_DATA_IO_PU_PD(262),
471 PORT_DATA_IO_PU_PD(263),
472
473 /* Special Pull-up / Pull-down Functions */
474 PINMUX_DATA(PORT66_KEYIN0_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
475 PORT66_FN2, PORT66_IN_PU),
476 PINMUX_DATA(PORT67_KEYIN1_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
477 PORT67_FN2, PORT67_IN_PU),
478 PINMUX_DATA(PORT68_KEYIN2_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
479 PORT68_FN2, PORT68_IN_PU),
480 PINMUX_DATA(PORT69_KEYIN3_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
481 PORT69_FN2, PORT69_IN_PU),
482 PINMUX_DATA(PORT70_KEYIN4_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
483 PORT70_FN2, PORT70_IN_PU),
484 PINMUX_DATA(PORT71_KEYIN5_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
485 PORT71_FN2, PORT71_IN_PU),
486 PINMUX_DATA(PORT72_KEYIN6_PU_MARK, MSELBCR_MSEL17_0, MSELBCR_MSEL16_0,
487 PORT72_FN2, PORT72_IN_PU),
488
489
490 /* 55-1 (FN) */
491 PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
492 PINMUX_DATA(CPORT0_MARK, PORT1_FN1),
493 PINMUX_DATA(CPORT1_MARK, PORT2_FN1),
494 PINMUX_DATA(CPORT2_MARK, PORT3_FN1),
495 PINMUX_DATA(CPORT3_MARK, PORT4_FN1),
496 PINMUX_DATA(CPORT4_MARK, PORT5_FN1),
497 PINMUX_DATA(CPORT5_MARK, PORT6_FN1),
498 PINMUX_DATA(CPORT6_MARK, PORT7_FN1),
499 PINMUX_DATA(CPORT7_MARK, PORT8_FN1),
500 PINMUX_DATA(CPORT8_MARK, PORT9_FN1),
501 PINMUX_DATA(CPORT9_MARK, PORT10_FN1),
502 PINMUX_DATA(CPORT10_MARK, PORT11_FN1),
503 PINMUX_DATA(CPORT11_MARK, PORT12_FN1),
504 PINMUX_DATA(SIN2_MARK, PORT12_FN2),
505 PINMUX_DATA(CPORT12_MARK, PORT13_FN1),
506 PINMUX_DATA(XCTS2_MARK, PORT13_FN2),
507 PINMUX_DATA(CPORT13_MARK, PORT14_FN1),
508 PINMUX_DATA(RFSPO4_MARK, PORT14_FN2),
509 PINMUX_DATA(CPORT14_MARK, PORT15_FN1),
510 PINMUX_DATA(RFSPO5_MARK, PORT15_FN2),
511 PINMUX_DATA(CPORT15_MARK, PORT16_FN1),
512 PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2),
513 PINMUX_DATA(GPS_AGC2_MARK, PORT16_FN3),
514 PINMUX_DATA(CPORT16_MARK, PORT17_FN1),
515 PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2),
516 PINMUX_DATA(GPS_AGC3_MARK, PORT17_FN3),
517 PINMUX_DATA(CPORT17_IC_OE_MARK, PORT18_FN1),
518 PINMUX_DATA(SOUT2_MARK, PORT18_FN2),
519 PINMUX_DATA(CPORT18_MARK, PORT19_FN1),
520 PINMUX_DATA(XRTS2_MARK, PORT19_FN2),
521 PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3),
522 PINMUX_DATA(CPORT19_MPORT1_MARK, PORT20_FN1),
523 PINMUX_DATA(CPORT20_MARK, PORT21_FN1),
524 PINMUX_DATA(RFSPO6_MARK, PORT21_FN2),
525 PINMUX_DATA(CPORT21_MARK, PORT22_FN1),
526 PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
527 PINMUX_DATA(CPORT22_MARK, PORT23_FN1),
528 PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
529 PINMUX_DATA(CPORT23_MARK, PORT24_FN1),
530 PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
531 PINMUX_DATA(RFSPO7_MARK, PORT24_FN3),
532 PINMUX_DATA(B_SYNLD1_MARK, PORT25_FN1),
533 PINMUX_DATA(B_SYNLD2_MARK, PORT26_FN1),
534 PINMUX_DATA(SYSENMSK_MARK, PORT26_FN2),
535 PINMUX_DATA(XMAINPS_MARK, PORT27_FN1),
536 PINMUX_DATA(XDIVPS_MARK, PORT28_FN1),
537 PINMUX_DATA(XIDRST_MARK, PORT29_FN1),
538 PINMUX_DATA(IDCLK_MARK, PORT30_FN1),
539 PINMUX_DATA(IC_DP_MARK, PORT30_FN2),
540 PINMUX_DATA(IDIO_MARK, PORT31_FN1),
541 PINMUX_DATA(IC_DM_MARK, PORT31_FN2),
542 PINMUX_DATA(SOUT1_MARK, PORT32_FN1),
543 PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2),
544 PINMUX_DATA(M02_BERDAT_MARK, PORT32_FN3),
545 PINMUX_DATA(SIN1_MARK, PORT33_FN1),
546 PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2),
547 PINMUX_DATA(XWUP_MARK, PORT33_FN3),
548 PINMUX_DATA(XRTS1_MARK, PORT34_FN1),
549 PINMUX_DATA(SCIFA4_RTS_MARK, PORT34_FN2),
550 PINMUX_DATA(M03_BERCLK_MARK, PORT34_FN3),
551 PINMUX_DATA(XCTS1_MARK, PORT35_FN1),
552 PINMUX_DATA(SCIFA4_CTS_MARK, PORT35_FN2),
553 PINMUX_DATA(PCMCLKO_MARK, PORT36_FN1),
554 PINMUX_DATA(SYNC8KO_MARK, PORT37_FN1),
555
556 /* 55-2 (FN) */
557 PINMUX_DATA(DNPCM_A_MARK, PORT38_FN1),
558 PINMUX_DATA(UPPCM_A_MARK, PORT39_FN1),
559 PINMUX_DATA(VACK_MARK, PORT40_FN1),
560 PINMUX_DATA(XTALB1L_MARK, PORT41_FN1),
561 PINMUX_DATA(GPS_AGC1_MARK, PORT42_FN1),
562 PINMUX_DATA(SCIFA0_RTS_MARK, PORT42_FN2),
563 PINMUX_DATA(GPS_AGC4_MARK, PORT43_FN1),
564 PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2),
565 PINMUX_DATA(GPS_PWRDOWN_MARK, PORT44_FN1),
566 PINMUX_DATA(SCIFA0_CTS_MARK, PORT44_FN2),
567 PINMUX_DATA(GPS_IM_MARK, PORT45_FN1),
568 PINMUX_DATA(GPS_IS_MARK, PORT46_FN1),
569 PINMUX_DATA(GPS_QM_MARK, PORT47_FN1),
570 PINMUX_DATA(GPS_QS_MARK, PORT48_FN1),
571 PINMUX_DATA(FMSOCK_MARK, PORT49_FN1),
572 PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2),
573 PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN3),
574 PINMUX_DATA(FMSOOLR_MARK, PORT50_FN1),
575 PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2),
576 PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3),
577 PINMUX_DATA(IPORT3_MARK, PORT50_FN4),
578 PINMUX_DATA(FMSIOLR_MARK, PORT50_FN5),
579 PINMUX_DATA(FMSOOBT_MARK, PORT51_FN1),
580 PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2),
581 PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3),
582 PINMUX_DATA(OPORT1_MARK, PORT51_FN4),
583 PINMUX_DATA(FMSIOBT_MARK, PORT51_FN5),
584 PINMUX_DATA(FMSOSLD_MARK, PORT52_FN1),
585 PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2),
586 PINMUX_DATA(OPORT2_MARK, PORT52_FN3),
587 PINMUX_DATA(FMSOILR_MARK, PORT53_FN1),
588 PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2),
589 PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3),
590 PINMUX_DATA(OPORT3_MARK, PORT53_FN4),
591 PINMUX_DATA(FMSIILR_MARK, PORT53_FN5),
592 PINMUX_DATA(FMSOIBT_MARK, PORT54_FN1),
593 PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2),
594 PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3),
595 PINMUX_DATA(FMSIIBT_MARK, PORT54_FN4),
596 PINMUX_DATA(FMSISLD_MARK, PORT55_FN1),
597 PINMUX_DATA(MFG0_OUT1_MARK, PORT55_FN2),
598 PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3),
599 PINMUX_DATA(A0_EA0_MARK, PORT57_FN1),
600 PINMUX_DATA(BS_MARK, PORT57_FN2),
601 PINMUX_DATA(A12_EA12_MARK, PORT58_FN1),
602 PINMUX_DATA(PORT58_VIO_CKOR_MARK, PORT58_FN2),
603 PINMUX_DATA(TPU4TO2_MARK, PORT58_FN3),
604 PINMUX_DATA(A13_EA13_MARK, PORT59_FN1),
605 PINMUX_DATA(PORT59_IROUT_MARK, PORT59_FN2),
606 PINMUX_DATA(MFG0_OUT2_MARK, PORT59_FN3),
607 PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4),
608 PINMUX_DATA(A14_EA14_MARK, PORT60_FN1),
609 PINMUX_DATA(PORT60_KEYOUT5_MARK, PORT60_FN2),
610 PINMUX_DATA(A15_EA15_MARK, PORT61_FN1),
611 PINMUX_DATA(PORT61_KEYOUT4_MARK, PORT61_FN2),
612 PINMUX_DATA(A16_EA16_MARK, PORT62_FN1),
613 PINMUX_DATA(PORT62_KEYOUT3_MARK, PORT62_FN2),
614 PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN3),
615 PINMUX_DATA(A17_EA17_MARK, PORT63_FN1),
616 PINMUX_DATA(PORT63_KEYOUT2_MARK, PORT63_FN2),
617 PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN3),
618 PINMUX_DATA(A18_EA18_MARK, PORT64_FN1),
619 PINMUX_DATA(PORT64_KEYOUT1_MARK, PORT64_FN2),
620 PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN3),
621 PINMUX_DATA(A19_EA19_MARK, PORT65_FN1),
622 PINMUX_DATA(PORT65_KEYOUT0_MARK, PORT65_FN2),
623 PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN3),
624 PINMUX_DATA(A20_EA20_MARK, PORT66_FN1),
625 PINMUX_DATA(PORT66_KEYIN0_MARK, PORT66_FN2),
626 PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN3),
627 PINMUX_DATA(A21_EA21_MARK, PORT67_FN1),
628 PINMUX_DATA(PORT67_KEYIN1_MARK, PORT67_FN2),
629 PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN3),
630 PINMUX_DATA(A22_EA22_MARK, PORT68_FN1),
631 PINMUX_DATA(PORT68_KEYIN2_MARK, PORT68_FN2),
632 PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN3),
633 PINMUX_DATA(A23_EA23_MARK, PORT69_FN1),
634 PINMUX_DATA(PORT69_KEYIN3_MARK, PORT69_FN2),
635 PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN3),
636 PINMUX_DATA(A24_EA24_MARK, PORT70_FN1),
637 PINMUX_DATA(PORT70_KEYIN4_MARK, PORT70_FN2),
638 PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN3),
639 PINMUX_DATA(A25_EA25_MARK, PORT71_FN1),
640 PINMUX_DATA(PORT71_KEYIN5_MARK, PORT71_FN2),
641 PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN3),
642 PINMUX_DATA(A26_MARK, PORT72_FN1),
643 PINMUX_DATA(PORT72_KEYIN6_MARK, PORT72_FN2),
644 PINMUX_DATA(D0_ED0_NAF0_MARK, PORT74_FN1),
645 PINMUX_DATA(D1_ED1_NAF1_MARK, PORT75_FN1),
646 PINMUX_DATA(D2_ED2_NAF2_MARK, PORT76_FN1),
647 PINMUX_DATA(D3_ED3_NAF3_MARK, PORT77_FN1),
648 PINMUX_DATA(D4_ED4_NAF4_MARK, PORT78_FN1),
649 PINMUX_DATA(D5_ED5_NAF5_MARK, PORT79_FN1),
650 PINMUX_DATA(D6_ED6_NAF6_MARK, PORT80_FN1),
651 PINMUX_DATA(D7_ED7_NAF7_MARK, PORT81_FN1),
652 PINMUX_DATA(D8_ED8_NAF8_MARK, PORT82_FN1),
653 PINMUX_DATA(D9_ED9_NAF9_MARK, PORT83_FN1),
654 PINMUX_DATA(D10_ED10_NAF10_MARK, PORT84_FN1),
655 PINMUX_DATA(D11_ED11_NAF11_MARK, PORT85_FN1),
656 PINMUX_DATA(D12_ED12_NAF12_MARK, PORT86_FN1),
657 PINMUX_DATA(D13_ED13_NAF13_MARK, PORT87_FN1),
658 PINMUX_DATA(D14_ED14_NAF14_MARK, PORT88_FN1),
659 PINMUX_DATA(D15_ED15_NAF15_MARK, PORT89_FN1),
660 PINMUX_DATA(CS4_MARK, PORT90_FN1),
661 PINMUX_DATA(CS5A_MARK, PORT91_FN1),
662 PINMUX_DATA(FMSICK_MARK, PORT91_FN2),
663 PINMUX_DATA(CS5B_MARK, PORT92_FN1),
664 PINMUX_DATA(FCE1_MARK, PORT92_FN2),
665
666 /* 55-3 (FN) */
667 PINMUX_DATA(CS6B_MARK, PORT93_FN1),
668 PINMUX_DATA(XCS2_MARK, PORT93_FN2),
669 PINMUX_DATA(CS6A_MARK, PORT93_FN3),
670 PINMUX_DATA(DACK0_MARK, PORT93_FN4),
671 PINMUX_DATA(FCE0_MARK, PORT94_FN1),
672 PINMUX_DATA(WAIT_MARK, PORT95_FN1),
673 PINMUX_DATA(DREQ0_MARK, PORT95_FN2),
674 PINMUX_DATA(RD_XRD_MARK, PORT96_FN1),
675 PINMUX_DATA(WE0_XWR0_FWE_MARK, PORT97_FN1),
676 PINMUX_DATA(WE1_XWR1_MARK, PORT98_FN1),
677 PINMUX_DATA(FRB_MARK, PORT99_FN1),
678 PINMUX_DATA(CKO_MARK, PORT100_FN1),
679 PINMUX_DATA(NBRSTOUT_MARK, PORT101_FN1),
680 PINMUX_DATA(NBRST_MARK, PORT102_FN1),
681 PINMUX_DATA(GPS_EPPSIN_MARK, PORT106_FN1),
682 PINMUX_DATA(LATCHPULSE_MARK, PORT110_FN1),
683 PINMUX_DATA(LTESIGNAL_MARK, PORT111_FN1),
684 PINMUX_DATA(LEGACYSTATE_MARK, PORT112_FN1),
685 PINMUX_DATA(TCKON_MARK, PORT118_FN1),
686 PINMUX_DATA(VIO_VD_MARK, PORT128_FN1),
687 PINMUX_DATA(PORT128_KEYOUT0_MARK, PORT128_FN2),
688 PINMUX_DATA(IPORT0_MARK, PORT128_FN3),
689 PINMUX_DATA(VIO_HD_MARK, PORT129_FN1),
690 PINMUX_DATA(PORT129_KEYOUT1_MARK, PORT129_FN2),
691 PINMUX_DATA(IPORT1_MARK, PORT129_FN3),
692 PINMUX_DATA(VIO_D0_MARK, PORT130_FN1),
693 PINMUX_DATA(PORT130_KEYOUT2_MARK, PORT130_FN2),
694 PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3),
695 PINMUX_DATA(VIO_D1_MARK, PORT131_FN1),
696 PINMUX_DATA(PORT131_KEYOUT3_MARK, PORT131_FN2),
697 PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3),
698 PINMUX_DATA(VIO_D2_MARK, PORT132_FN1),
699 PINMUX_DATA(PORT132_KEYOUT4_MARK, PORT132_FN2),
700 PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3),
701 PINMUX_DATA(VIO_D3_MARK, PORT133_FN1),
702 PINMUX_DATA(PORT133_KEYOUT5_MARK, PORT133_FN2),
703 PINMUX_DATA(PORT133_MSIOF2_TSYNC_MARK, PORT133_FN3),
704 PINMUX_DATA(VIO_D4_MARK, PORT134_FN1),
705 PINMUX_DATA(PORT134_KEYIN0_MARK, PORT134_FN2),
706 PINMUX_DATA(PORT134_MSIOF2_TXD_MARK, PORT134_FN3),
707 PINMUX_DATA(VIO_D5_MARK, PORT135_FN1),
708 PINMUX_DATA(PORT135_KEYIN1_MARK, PORT135_FN2),
709 PINMUX_DATA(PORT135_MSIOF2_TSCK_MARK, PORT135_FN3),
710 PINMUX_DATA(VIO_D6_MARK, PORT136_FN1),
711 PINMUX_DATA(PORT136_KEYIN2_MARK, PORT136_FN2),
712 PINMUX_DATA(VIO_D7_MARK, PORT137_FN1),
713 PINMUX_DATA(PORT137_KEYIN3_MARK, PORT137_FN2),
714 PINMUX_DATA(VIO_D8_MARK, PORT138_FN1),
715 PINMUX_DATA(M9_SLCD_A01_MARK, PORT138_FN2),
716 PINMUX_DATA(PORT138_FSIAOMC_MARK, PORT138_FN3),
717 PINMUX_DATA(VIO_D9_MARK, PORT139_FN1),
718 PINMUX_DATA(M10_SLCD_CK1_MARK, PORT139_FN2),
719 PINMUX_DATA(PORT139_FSIAOLR_MARK, PORT139_FN3),
720 PINMUX_DATA(VIO_D10_MARK, PORT140_FN1),
721 PINMUX_DATA(M11_SLCD_SO1_MARK, PORT140_FN2),
722 PINMUX_DATA(TPU0TO2_MARK, PORT140_FN3),
723 PINMUX_DATA(PORT140_FSIAOBT_MARK, PORT140_FN4),
724 PINMUX_DATA(VIO_D11_MARK, PORT141_FN1),
725 PINMUX_DATA(M12_SLCD_CE1_MARK, PORT141_FN2),
726 PINMUX_DATA(TPU0TO3_MARK, PORT141_FN3),
727 PINMUX_DATA(PORT141_FSIAOSLD_MARK, PORT141_FN4),
728 PINMUX_DATA(VIO_D12_MARK, PORT142_FN1),
729 PINMUX_DATA(M13_BSW_MARK, PORT142_FN2),
730 PINMUX_DATA(PORT142_FSIACK_MARK, PORT142_FN3),
731 PINMUX_DATA(VIO_D13_MARK, PORT143_FN1),
732 PINMUX_DATA(M14_GSW_MARK, PORT143_FN2),
733 PINMUX_DATA(PORT143_FSIAILR_MARK, PORT143_FN3),
734 PINMUX_DATA(VIO_D14_MARK, PORT144_FN1),
735 PINMUX_DATA(M15_RSW_MARK, PORT144_FN2),
736 PINMUX_DATA(PORT144_FSIAIBT_MARK, PORT144_FN3),
737 PINMUX_DATA(VIO_D15_MARK, PORT145_FN1),
738 PINMUX_DATA(TPU1TO3_MARK, PORT145_FN2),
739 PINMUX_DATA(PORT145_FSIAISLD_MARK, PORT145_FN3),
740 PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1),
741 PINMUX_DATA(PORT146_KEYIN4_MARK, PORT146_FN2),
742 PINMUX_DATA(IPORT2_MARK, PORT146_FN3),
743 PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1),
744 PINMUX_DATA(PORT147_KEYIN5_MARK, PORT147_FN2),
745 PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1),
746 PINMUX_DATA(PORT148_KEYIN6_MARK, PORT148_FN2),
747 PINMUX_DATA(A27_MARK, PORT149_FN1),
748 PINMUX_DATA(RDWR_XWE_MARK, PORT149_FN2),
749 PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3),
750 PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN1),
751 PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN1),
752 PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN2),
753 PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN1),
754 PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN2),
755 PINMUX_DATA(TPU1TO2_MARK, PORT153_FN1),
756 PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN2),
757 PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN3),
758 PINMUX_DATA(SOUT3_MARK, PORT154_FN1),
759 PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2),
760 PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN3),
761 PINMUX_DATA(SIN3_MARK, PORT155_FN1),
762 PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2),
763 PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN3),
764 PINMUX_DATA(XRTS3_MARK, PORT156_FN1),
765 PINMUX_DATA(SCIFA2_RTS1_MARK, PORT156_FN2),
766 PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN3),
767 PINMUX_DATA(XCTS3_MARK, PORT157_FN1),
768 PINMUX_DATA(SCIFA2_CTS1_MARK, PORT157_FN2),
769 PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN3),
770
771 /* 55-4 (FN) */
772 PINMUX_DATA(DINT_MARK, PORT158_FN1),
773 PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2),
774 PINMUX_DATA(TS_SCK3_MARK, PORT158_FN3),
775 PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1),
776 PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2),
777 PINMUX_DATA(NMI_MARK, PORT159_FN3),
778 PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1),
779 PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2),
780 PINMUX_DATA(SOUT0_MARK, PORT160_FN3),
781 PINMUX_DATA(PORT161_SCIFB_CTS_MARK, PORT161_FN1),
782 PINMUX_DATA(PORT161_SCIFA5_CTS_MARK, PORT161_FN2),
783 PINMUX_DATA(XCTS0_MARK, PORT161_FN3),
784 PINMUX_DATA(MFG3_IN2_MARK, PORT161_FN4),
785 PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1),
786 PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2),
787 PINMUX_DATA(SIN0_MARK, PORT162_FN3),
788 PINMUX_DATA(MFG3_IN1_MARK, PORT162_FN4),
789 PINMUX_DATA(PORT163_SCIFB_RTS_MARK, PORT163_FN1),
790 PINMUX_DATA(PORT163_SCIFA5_RTS_MARK, PORT163_FN2),
791 PINMUX_DATA(XRTS0_MARK, PORT163_FN3),
792 PINMUX_DATA(MFG3_OUT1_MARK, PORT163_FN4),
793 PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5),
794 PINMUX_DATA(LCDD0_MARK, PORT192_FN1),
795 PINMUX_DATA(PORT192_KEYOUT0_MARK, PORT192_FN2),
796 PINMUX_DATA(EXT_CKI_MARK, PORT192_FN3),
797 PINMUX_DATA(LCDD1_MARK, PORT193_FN1),
798 PINMUX_DATA(PORT193_KEYOUT1_MARK, PORT193_FN2),
799 PINMUX_DATA(PORT193_SCIFA5_CTS_MARK, PORT193_FN3),
800 PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN4),
801 PINMUX_DATA(LCDD2_MARK, PORT194_FN1),
802 PINMUX_DATA(PORT194_KEYOUT2_MARK, PORT194_FN2),
803 PINMUX_DATA(PORT194_SCIFA5_RTS_MARK, PORT194_FN3),
804 PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN4),
805 PINMUX_DATA(LCDD3_MARK, PORT195_FN1),
806 PINMUX_DATA(PORT195_KEYOUT3_MARK, PORT195_FN2),
807 PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3),
808 PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN4),
809 PINMUX_DATA(LCDD4_MARK, PORT196_FN1),
810 PINMUX_DATA(PORT196_KEYOUT4_MARK, PORT196_FN2),
811 PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3),
812 PINMUX_DATA(LCDD5_MARK, PORT197_FN1),
813 PINMUX_DATA(PORT197_KEYOUT5_MARK, PORT197_FN2),
814 PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3),
815 PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN4),
816 PINMUX_DATA(LCDD6_MARK, PORT198_FN1),
817 PINMUX_DATA(LCDD7_MARK, PORT199_FN1),
818 PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2),
819 PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN3),
820 PINMUX_DATA(LCDD8_MARK, PORT200_FN1),
821 PINMUX_DATA(PORT200_KEYIN0_MARK, PORT200_FN2),
822 PINMUX_DATA(VIO_DR0_MARK, PORT200_FN3),
823 PINMUX_DATA(D16_MARK, PORT200_FN4),
824 PINMUX_DATA(LCDD9_MARK, PORT201_FN1),
825 PINMUX_DATA(PORT201_KEYIN1_MARK, PORT201_FN2),
826 PINMUX_DATA(VIO_DR1_MARK, PORT201_FN3),
827 PINMUX_DATA(D17_MARK, PORT201_FN4),
828 PINMUX_DATA(LCDD10_MARK, PORT202_FN1),
829 PINMUX_DATA(PORT202_KEYIN2_MARK, PORT202_FN2),
830 PINMUX_DATA(VIO_DR2_MARK, PORT202_FN3),
831 PINMUX_DATA(D18_MARK, PORT202_FN4),
832 PINMUX_DATA(LCDD11_MARK, PORT203_FN1),
833 PINMUX_DATA(PORT203_KEYIN3_MARK, PORT203_FN2),
834 PINMUX_DATA(VIO_DR3_MARK, PORT203_FN3),
835 PINMUX_DATA(D19_MARK, PORT203_FN4),
836 PINMUX_DATA(LCDD12_MARK, PORT204_FN1),
837 PINMUX_DATA(PORT204_KEYIN4_MARK, PORT204_FN2),
838 PINMUX_DATA(VIO_DR4_MARK, PORT204_FN3),
839 PINMUX_DATA(D20_MARK, PORT204_FN4),
840 PINMUX_DATA(LCDD13_MARK, PORT205_FN1),
841 PINMUX_DATA(PORT205_KEYIN5_MARK, PORT205_FN2),
842 PINMUX_DATA(VIO_DR5_MARK, PORT205_FN3),
843 PINMUX_DATA(D21_MARK, PORT205_FN4),
844 PINMUX_DATA(LCDD14_MARK, PORT206_FN1),
845 PINMUX_DATA(PORT206_KEYIN6_MARK, PORT206_FN2),
846 PINMUX_DATA(VIO_DR6_MARK, PORT206_FN3),
847 PINMUX_DATA(D22_MARK, PORT206_FN4),
848 PINMUX_DATA(LCDD15_MARK, PORT207_FN1),
849 PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2),
850 PINMUX_DATA(PORT207_KEYOUT0_MARK, PORT207_FN3),
851 PINMUX_DATA(VIO_DR7_MARK, PORT207_FN4),
852 PINMUX_DATA(D23_MARK, PORT207_FN5),
853 PINMUX_DATA(LCDD16_MARK, PORT208_FN1),
854 PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2),
855 PINMUX_DATA(PORT208_KEYOUT1_MARK, PORT208_FN3),
856 PINMUX_DATA(VIO_VDR_MARK, PORT208_FN4),
857 PINMUX_DATA(D24_MARK, PORT208_FN5),
858 PINMUX_DATA(LCDD17_MARK, PORT209_FN1),
859 PINMUX_DATA(PORT209_KEYOUT2_MARK, PORT209_FN2),
860 PINMUX_DATA(VIO_HDR_MARK, PORT209_FN3),
861 PINMUX_DATA(D25_MARK, PORT209_FN4),
862 PINMUX_DATA(LCDD18_MARK, PORT210_FN1),
863 PINMUX_DATA(DREQ2_MARK, PORT210_FN2),
864 PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN3),
865 PINMUX_DATA(D26_MARK, PORT210_FN4),
866 PINMUX_DATA(LCDD19_MARK, PORT211_FN1),
867 PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN2),
868 PINMUX_DATA(D27_MARK, PORT211_FN3),
869 PINMUX_DATA(LCDD20_MARK, PORT212_FN1),
870 PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2),
871 PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN3),
872 PINMUX_DATA(D28_MARK, PORT212_FN4),
873 PINMUX_DATA(LCDD21_MARK, PORT213_FN1),
874 PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2),
875 PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN3),
876 PINMUX_DATA(D29_MARK, PORT213_FN4),
877 PINMUX_DATA(LCDD22_MARK, PORT214_FN1),
878 PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2),
879 PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN3),
880 PINMUX_DATA(D30_MARK, PORT214_FN4),
881 PINMUX_DATA(LCDD23_MARK, PORT215_FN1),
882 PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2),
883 PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN3),
884 PINMUX_DATA(D31_MARK, PORT215_FN4),
885 PINMUX_DATA(LCDDCK_MARK, PORT216_FN1),
886 PINMUX_DATA(LCDWR_MARK, PORT216_FN2),
887 PINMUX_DATA(PORT216_KEYOUT3_MARK, PORT216_FN3),
888 PINMUX_DATA(VIO_CLKR_MARK, PORT216_FN4),
889 PINMUX_DATA(LCDRD_MARK, PORT217_FN1),
890 PINMUX_DATA(DACK2_MARK, PORT217_FN2),
891 PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN3),
892 PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1),
893 PINMUX_DATA(LCDCS_MARK, PORT218_FN2),
894 PINMUX_DATA(LCDCS2_MARK, PORT218_FN3),
895 PINMUX_DATA(DACK3_MARK, PORT218_FN4),
896 PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5),
897 PINMUX_DATA(PORT218_KEYOUT4_MARK, PORT218_FN6),
898 PINMUX_DATA(LCDDISP_MARK, PORT219_FN1),
899 PINMUX_DATA(LCDRS_MARK, PORT219_FN2),
900 PINMUX_DATA(DREQ3_MARK, PORT219_FN3),
901 PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN4),
902 PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1),
903 PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2),
904 PINMUX_DATA(PORT220_KEYOUT5_MARK, PORT220_FN3),
905 PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1),
906 PINMUX_DATA(DREQ1_MARK, PORT221_FN2),
907 PINMUX_DATA(PWEN_MARK, PORT221_FN3),
908 PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN4),
909 PINMUX_DATA(LCDDON_MARK, PORT222_FN1),
910 PINMUX_DATA(LCDDON2_MARK, PORT222_FN2),
911 PINMUX_DATA(DACK1_MARK, PORT222_FN3),
912 PINMUX_DATA(OVCN_MARK, PORT222_FN4),
913 PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5),
914 PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN1),
915 PINMUX_DATA(OVCN2_MARK, PORT225_FN2),
916 PINMUX_DATA(EXTLP_MARK, PORT226_FN1),
917 PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2),
918 PINMUX_DATA(USBTERM_MARK, PORT226_FN3),
919 PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN4),
920 PINMUX_DATA(SCIFA1_RTS_MARK, PORT227_FN1),
921 PINMUX_DATA(IDIN_MARK, PORT227_FN2),
922 PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN1),
923 PINMUX_DATA(SCIFA1_CTS_MARK, PORT229_FN1),
924 PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN2),
925 PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1),
926 PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2),
927 PINMUX_DATA(PORT230_FSIAOMC_MARK, PORT230_FN3),
928 PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1),
929 PINMUX_DATA(SCIFA2_CTS2_MARK, PORT231_FN2),
930 PINMUX_DATA(PORT231_FSIAOLR_MARK, PORT231_FN3),
931 PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1),
932 PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2),
933 PINMUX_DATA(PORT232_FSIAOBT_MARK, PORT232_FN3),
934 PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1),
935 PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2),
936 PINMUX_DATA(GPS_VCOTRIG_MARK, PORT233_FN3),
937 PINMUX_DATA(PORT233_FSIACK_MARK, PORT233_FN4),
938 PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1),
939 PINMUX_DATA(SCIFA2_RTS2_MARK, PORT234_FN2),
940 PINMUX_DATA(PORT234_FSIAOSLD_MARK, PORT234_FN3),
941 PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1),
942 PINMUX_DATA(OPORT0_MARK, PORT235_FN2),
943 PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3),
944 PINMUX_DATA(PORT235_FSIAILR_MARK, PORT235_FN4),
945 PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1),
946 PINMUX_DATA(I2C_SDA2_MARK, PORT236_FN2),
947 PINMUX_DATA(PORT236_FSIAIBT_MARK, PORT236_FN3),
948 PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1),
949 PINMUX_DATA(I2C_SCL2_MARK, PORT237_FN2),
950 PINMUX_DATA(PORT237_FSIAISLD_MARK, PORT237_FN3),
951 PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1),
952 PINMUX_DATA(EDBGREQ3_MARK, PORT238_FN2),
953
954 /* 55-5 (FN) */
955 PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1),
956 PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1),
957 PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1),
958 PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2),
959 PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3),
960 PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4),
961 PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1),
962 PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN2),
963 PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1),
964 PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2),
965 PINMUX_DATA(PORT244_SCIFA5_CTS_MARK, PORT244_FN1),
966 PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2),
967 PINMUX_DATA(PORT244_SCIFB_CTS_MARK, PORT244_FN3),
968 PINMUX_DATA(PORT245_SCIFA5_RTS_MARK, PORT245_FN1),
969 PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2),
970 PINMUX_DATA(PORT245_SCIFB_RTS_MARK, PORT245_FN3),
971 PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1),
972 PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2),
973 PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3),
974 PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4),
975 PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1),
976 PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2),
977 PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3),
978 PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4),
979 PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1),
980 PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2),
981 PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3),
982 PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4),
983 PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1),
984 PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2),
985 PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1),
986 PINMUX_DATA(TCK2_SWCLK_MC0_MARK, PORT250_FN2),
987 PINMUX_DATA(SDHICD0_MARK, PORT251_FN1),
988 PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1),
989 PINMUX_DATA(TMS2_SWDIO_MC0_MARK, PORT252_FN2),
990 PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1),
991 PINMUX_DATA(TDO2_SWO0_MC0_MARK, PORT253_FN2),
992 PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1),
993 PINMUX_DATA(TDI2_MARK, PORT254_FN2),
994 PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1),
995 PINMUX_DATA(RTCK2_SWO1_MC0_MARK, PORT255_FN2),
996 PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1),
997 PINMUX_DATA(TRST2_MARK, PORT256_FN2),
998 PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1),
999 PINMUX_DATA(EDBGREQ2_MARK, PORT257_FN2),
1000 PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1),
1001 PINMUX_DATA(TCK3_SWCLK_MC1_MARK, PORT258_FN2),
1002 PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1),
1003 PINMUX_DATA(M11_SLCD_SO2_MARK, PORT259_FN2),
1004 PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3),
1005 PINMUX_DATA(TMS3_SWDIO_MC1_MARK, PORT259_FN4),
1006 PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1),
1007 PINMUX_DATA(M9_SLCD_A02_MARK, PORT260_FN2),
1008 PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3),
1009 PINMUX_DATA(TDO3_SWO0_MC1_MARK, PORT260_FN4),
1010 PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1),
1011 PINMUX_DATA(M10_SLCD_CK2_MARK, PORT261_FN2),
1012 PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3),
1013 PINMUX_DATA(TDI3_MARK, PORT261_FN4),
1014 PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1),
1015 PINMUX_DATA(M12_SLCD_CE2_MARK, PORT262_FN2),
1016 PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3),
1017 PINMUX_DATA(RTCK3_SWO1_MC1_MARK, PORT262_FN4),
1018 PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1),
1019 PINMUX_DATA(TRST3_MARK, PORT263_FN2),
1020 PINMUX_DATA(RESETOUTS_MARK, PORT264_FN1),
1021};
1022
1023static struct pinmux_gpio pinmux_gpios[] = {
1024 /* 55-1 -> 55-5 (GPIO) */
1025 GPIO_PORT_ALL(),
1026
1027 /* Special Pull-up / Pull-down Functions */
1028 GPIO_FN(PORT66_KEYIN0_PU), GPIO_FN(PORT67_KEYIN1_PU),
1029 GPIO_FN(PORT68_KEYIN2_PU), GPIO_FN(PORT69_KEYIN3_PU),
1030 GPIO_FN(PORT70_KEYIN4_PU), GPIO_FN(PORT71_KEYIN5_PU),
1031 GPIO_FN(PORT72_KEYIN6_PU),
1032
1033 /* 55-1 (FN) */
1034 GPIO_FN(VBUS_0),
1035 GPIO_FN(CPORT0),
1036 GPIO_FN(CPORT1),
1037 GPIO_FN(CPORT2),
1038 GPIO_FN(CPORT3),
1039 GPIO_FN(CPORT4),
1040 GPIO_FN(CPORT5),
1041 GPIO_FN(CPORT6),
1042 GPIO_FN(CPORT7),
1043 GPIO_FN(CPORT8),
1044 GPIO_FN(CPORT9),
1045 GPIO_FN(CPORT10),
1046 GPIO_FN(CPORT11), GPIO_FN(SIN2),
1047 GPIO_FN(CPORT12), GPIO_FN(XCTS2),
1048 GPIO_FN(CPORT13), GPIO_FN(RFSPO4),
1049 GPIO_FN(CPORT14), GPIO_FN(RFSPO5),
1050 GPIO_FN(CPORT15), GPIO_FN(SCIFA0_SCK), GPIO_FN(GPS_AGC2),
1051 GPIO_FN(CPORT16), GPIO_FN(SCIFA0_TXD), GPIO_FN(GPS_AGC3),
1052 GPIO_FN(CPORT17_IC_OE), GPIO_FN(SOUT2),
1053 GPIO_FN(CPORT18), GPIO_FN(XRTS2), GPIO_FN(PORT19_VIO_CKO2),
1054 GPIO_FN(CPORT19_MPORT1),
1055 GPIO_FN(CPORT20), GPIO_FN(RFSPO6),
1056 GPIO_FN(CPORT21), GPIO_FN(STATUS0),
1057 GPIO_FN(CPORT22), GPIO_FN(STATUS1),
1058 GPIO_FN(CPORT23), GPIO_FN(STATUS2), GPIO_FN(RFSPO7),
1059 GPIO_FN(B_SYNLD1),
1060 GPIO_FN(B_SYNLD2), GPIO_FN(SYSENMSK),
1061 GPIO_FN(XMAINPS),
1062 GPIO_FN(XDIVPS),
1063 GPIO_FN(XIDRST),
1064 GPIO_FN(IDCLK), GPIO_FN(IC_DP),
1065 GPIO_FN(IDIO), GPIO_FN(IC_DM),
1066 GPIO_FN(SOUT1), GPIO_FN(SCIFA4_TXD), GPIO_FN(M02_BERDAT),
1067 GPIO_FN(SIN1), GPIO_FN(SCIFA4_RXD), GPIO_FN(XWUP),
1068 GPIO_FN(XRTS1), GPIO_FN(SCIFA4_RTS), GPIO_FN(M03_BERCLK),
1069 GPIO_FN(XCTS1), GPIO_FN(SCIFA4_CTS),
1070 GPIO_FN(PCMCLKO),
1071 GPIO_FN(SYNC8KO),
1072
1073 /* 55-2 (FN) */
1074 GPIO_FN(DNPCM_A),
1075 GPIO_FN(UPPCM_A),
1076 GPIO_FN(VACK),
1077 GPIO_FN(XTALB1L),
1078 GPIO_FN(GPS_AGC1), GPIO_FN(SCIFA0_RTS),
1079 GPIO_FN(GPS_AGC4), GPIO_FN(SCIFA0_RXD),
1080 GPIO_FN(GPS_PWRDOWN), GPIO_FN(SCIFA0_CTS),
1081 GPIO_FN(GPS_IM),
1082 GPIO_FN(GPS_IS),
1083 GPIO_FN(GPS_QM),
1084 GPIO_FN(GPS_QS),
1085 GPIO_FN(FMSOCK), GPIO_FN(PORT49_IRDA_OUT), GPIO_FN(PORT49_IROUT),
1086 GPIO_FN(FMSOOLR), GPIO_FN(BBIF2_TSYNC2), GPIO_FN(TPU2TO2),
1087 GPIO_FN(IPORT3), GPIO_FN(FMSIOLR),
1088 GPIO_FN(FMSOOBT), GPIO_FN(BBIF2_TSCK2), GPIO_FN(TPU2TO3),
1089 GPIO_FN(OPORT1), GPIO_FN(FMSIOBT),
1090 GPIO_FN(FMSOSLD), GPIO_FN(BBIF2_TXD2), GPIO_FN(OPORT2),
1091 GPIO_FN(FMSOILR), GPIO_FN(PORT53_IRDA_IN), GPIO_FN(TPU3TO3),
1092 GPIO_FN(OPORT3), GPIO_FN(FMSIILR),
1093 GPIO_FN(FMSOIBT), GPIO_FN(PORT54_IRDA_FIRSEL), GPIO_FN(TPU3TO2),
1094 GPIO_FN(FMSIIBT),
1095 GPIO_FN(FMSISLD), GPIO_FN(MFG0_OUT1), GPIO_FN(TPU0TO0),
1096 GPIO_FN(A0_EA0), GPIO_FN(BS),
1097 GPIO_FN(A12_EA12), GPIO_FN(PORT58_VIO_CKOR), GPIO_FN(TPU4TO2),
1098 GPIO_FN(A13_EA13), GPIO_FN(PORT59_IROUT), GPIO_FN(MFG0_OUT2),
1099 GPIO_FN(TPU0TO1),
1100 GPIO_FN(A14_EA14), GPIO_FN(PORT60_KEYOUT5),
1101 GPIO_FN(A15_EA15), GPIO_FN(PORT61_KEYOUT4),
1102 GPIO_FN(A16_EA16), GPIO_FN(PORT62_KEYOUT3), GPIO_FN(MSIOF0_SS1),
1103 GPIO_FN(A17_EA17), GPIO_FN(PORT63_KEYOUT2), GPIO_FN(MSIOF0_TSYNC),
1104 GPIO_FN(A18_EA18), GPIO_FN(PORT64_KEYOUT1), GPIO_FN(MSIOF0_TSCK),
1105 GPIO_FN(A19_EA19), GPIO_FN(PORT65_KEYOUT0), GPIO_FN(MSIOF0_TXD),
1106 GPIO_FN(A20_EA20), GPIO_FN(PORT66_KEYIN0), GPIO_FN(MSIOF0_RSCK),
1107 GPIO_FN(A21_EA21), GPIO_FN(PORT67_KEYIN1), GPIO_FN(MSIOF0_RSYNC),
1108 GPIO_FN(A22_EA22), GPIO_FN(PORT68_KEYIN2), GPIO_FN(MSIOF0_MCK0),
1109 GPIO_FN(A23_EA23), GPIO_FN(PORT69_KEYIN3), GPIO_FN(MSIOF0_MCK1),
1110 GPIO_FN(A24_EA24), GPIO_FN(PORT70_KEYIN4), GPIO_FN(MSIOF0_RXD),
1111 GPIO_FN(A25_EA25), GPIO_FN(PORT71_KEYIN5), GPIO_FN(MSIOF0_SS2),
1112 GPIO_FN(A26), GPIO_FN(PORT72_KEYIN6),
1113 GPIO_FN(D0_ED0_NAF0),
1114 GPIO_FN(D1_ED1_NAF1),
1115 GPIO_FN(D2_ED2_NAF2),
1116 GPIO_FN(D3_ED3_NAF3),
1117 GPIO_FN(D4_ED4_NAF4),
1118 GPIO_FN(D5_ED5_NAF5),
1119 GPIO_FN(D6_ED6_NAF6),
1120 GPIO_FN(D7_ED7_NAF7),
1121 GPIO_FN(D8_ED8_NAF8),
1122 GPIO_FN(D9_ED9_NAF9),
1123 GPIO_FN(D10_ED10_NAF10),
1124 GPIO_FN(D11_ED11_NAF11),
1125 GPIO_FN(D12_ED12_NAF12),
1126 GPIO_FN(D13_ED13_NAF13),
1127 GPIO_FN(D14_ED14_NAF14),
1128 GPIO_FN(D15_ED15_NAF15),
1129 GPIO_FN(CS4),
1130 GPIO_FN(CS5A), GPIO_FN(FMSICK),
1131
1132 /* 55-3 (FN) */
1133 GPIO_FN(CS5B), GPIO_FN(FCE1),
1134 GPIO_FN(CS6B), GPIO_FN(XCS2), GPIO_FN(CS6A), GPIO_FN(DACK0),
1135 GPIO_FN(FCE0),
1136 GPIO_FN(WAIT), GPIO_FN(DREQ0),
1137 GPIO_FN(RD_XRD),
1138 GPIO_FN(WE0_XWR0_FWE),
1139 GPIO_FN(WE1_XWR1),
1140 GPIO_FN(FRB),
1141 GPIO_FN(CKO),
1142 GPIO_FN(NBRSTOUT),
1143 GPIO_FN(NBRST),
1144 GPIO_FN(GPS_EPPSIN),
1145 GPIO_FN(LATCHPULSE),
1146 GPIO_FN(LTESIGNAL),
1147 GPIO_FN(LEGACYSTATE),
1148 GPIO_FN(TCKON),
1149 GPIO_FN(VIO_VD), GPIO_FN(PORT128_KEYOUT0), GPIO_FN(IPORT0),
1150 GPIO_FN(VIO_HD), GPIO_FN(PORT129_KEYOUT1), GPIO_FN(IPORT1),
1151 GPIO_FN(VIO_D0), GPIO_FN(PORT130_KEYOUT2), GPIO_FN(PORT130_MSIOF2_RXD),
1152 GPIO_FN(VIO_D1), GPIO_FN(PORT131_KEYOUT3), GPIO_FN(PORT131_MSIOF2_SS1),
1153 GPIO_FN(VIO_D2), GPIO_FN(PORT132_KEYOUT4), GPIO_FN(PORT132_MSIOF2_SS2),
1154 GPIO_FN(VIO_D3), GPIO_FN(PORT133_KEYOUT5),
1155 GPIO_FN(PORT133_MSIOF2_TSYNC),
1156 GPIO_FN(VIO_D4), GPIO_FN(PORT134_KEYIN0), GPIO_FN(PORT134_MSIOF2_TXD),
1157 GPIO_FN(VIO_D5), GPIO_FN(PORT135_KEYIN1), GPIO_FN(PORT135_MSIOF2_TSCK),
1158 GPIO_FN(VIO_D6), GPIO_FN(PORT136_KEYIN2),
1159 GPIO_FN(VIO_D7), GPIO_FN(PORT137_KEYIN3),
1160 GPIO_FN(VIO_D8), GPIO_FN(M9_SLCD_A01), GPIO_FN(PORT138_FSIAOMC),
1161 GPIO_FN(VIO_D9), GPIO_FN(M10_SLCD_CK1), GPIO_FN(PORT139_FSIAOLR),
1162 GPIO_FN(VIO_D10), GPIO_FN(M11_SLCD_SO1), GPIO_FN(TPU0TO2),
1163 GPIO_FN(PORT140_FSIAOBT),
1164 GPIO_FN(VIO_D11), GPIO_FN(M12_SLCD_CE1), GPIO_FN(TPU0TO3),
1165 GPIO_FN(PORT141_FSIAOSLD),
1166 GPIO_FN(VIO_D12), GPIO_FN(M13_BSW), GPIO_FN(PORT142_FSIACK),
1167 GPIO_FN(VIO_D13), GPIO_FN(M14_GSW), GPIO_FN(PORT143_FSIAILR),
1168 GPIO_FN(VIO_D14), GPIO_FN(M15_RSW), GPIO_FN(PORT144_FSIAIBT),
1169 GPIO_FN(VIO_D15), GPIO_FN(TPU1TO3), GPIO_FN(PORT145_FSIAISLD),
1170 GPIO_FN(VIO_CLK), GPIO_FN(PORT146_KEYIN4), GPIO_FN(IPORT2),
1171 GPIO_FN(VIO_FIELD), GPIO_FN(PORT147_KEYIN5),
1172 GPIO_FN(VIO_CKO), GPIO_FN(PORT148_KEYIN6),
1173 GPIO_FN(A27), GPIO_FN(RDWR_XWE), GPIO_FN(MFG0_IN1),
1174 GPIO_FN(MFG0_IN2),
1175 GPIO_FN(TS_SPSYNC3), GPIO_FN(MSIOF2_RSCK),
1176 GPIO_FN(TS_SDAT3), GPIO_FN(MSIOF2_RSYNC),
1177 GPIO_FN(TPU1TO2), GPIO_FN(TS_SDEN3), GPIO_FN(PORT153_MSIOF2_SS1),
1178 GPIO_FN(SOUT3), GPIO_FN(SCIFA2_TXD1), GPIO_FN(MSIOF2_MCK0),
1179 GPIO_FN(SIN3), GPIO_FN(SCIFA2_RXD1), GPIO_FN(MSIOF2_MCK1),
1180 GPIO_FN(XRTS3), GPIO_FN(SCIFA2_RTS1), GPIO_FN(PORT156_MSIOF2_SS2),
1181 GPIO_FN(XCTS3), GPIO_FN(SCIFA2_CTS1), GPIO_FN(PORT157_MSIOF2_RXD),
1182
1183 /* 55-4 (FN) */
1184 GPIO_FN(DINT), GPIO_FN(SCIFA2_SCK1), GPIO_FN(TS_SCK3),
1185 GPIO_FN(PORT159_SCIFB_SCK), GPIO_FN(PORT159_SCIFA5_SCK), GPIO_FN(NMI),
1186 GPIO_FN(PORT160_SCIFB_TXD), GPIO_FN(PORT160_SCIFA5_TXD), GPIO_FN(SOUT0),
1187 GPIO_FN(PORT161_SCIFB_CTS), GPIO_FN(PORT161_SCIFA5_CTS), GPIO_FN(XCTS0),
1188 GPIO_FN(MFG3_IN2),
1189 GPIO_FN(PORT162_SCIFB_RXD), GPIO_FN(PORT162_SCIFA5_RXD), GPIO_FN(SIN0),
1190 GPIO_FN(MFG3_IN1),
1191 GPIO_FN(PORT163_SCIFB_RTS), GPIO_FN(PORT163_SCIFA5_RTS), GPIO_FN(XRTS0),
1192 GPIO_FN(MFG3_OUT1), GPIO_FN(TPU3TO0),
1193 GPIO_FN(LCDD0), GPIO_FN(PORT192_KEYOUT0), GPIO_FN(EXT_CKI),
1194 GPIO_FN(LCDD1), GPIO_FN(PORT193_KEYOUT1), GPIO_FN(PORT193_SCIFA5_CTS),
1195 GPIO_FN(BBIF2_TSYNC1),
1196 GPIO_FN(LCDD2), GPIO_FN(PORT194_KEYOUT2), GPIO_FN(PORT194_SCIFA5_RTS),
1197 GPIO_FN(BBIF2_TSCK1),
1198 GPIO_FN(LCDD3), GPIO_FN(PORT195_KEYOUT3), GPIO_FN(PORT195_SCIFA5_RXD),
1199 GPIO_FN(BBIF2_TXD1),
1200 GPIO_FN(LCDD4), GPIO_FN(PORT196_KEYOUT4), GPIO_FN(PORT196_SCIFA5_TXD),
1201 GPIO_FN(LCDD5), GPIO_FN(PORT197_KEYOUT5), GPIO_FN(PORT197_SCIFA5_SCK),
1202 GPIO_FN(MFG2_OUT2),
1203 GPIO_FN(LCDD6),
1204 GPIO_FN(LCDD7), GPIO_FN(TPU4TO1), GPIO_FN(MFG4_OUT2),
1205 GPIO_FN(LCDD8), GPIO_FN(PORT200_KEYIN0), GPIO_FN(VIO_DR0),
1206 GPIO_FN(D16),
1207 GPIO_FN(LCDD9), GPIO_FN(PORT201_KEYIN1), GPIO_FN(VIO_DR1),
1208 GPIO_FN(D17),
1209 GPIO_FN(LCDD10), GPIO_FN(PORT202_KEYIN2), GPIO_FN(VIO_DR2),
1210 GPIO_FN(D18),
1211 GPIO_FN(LCDD11), GPIO_FN(PORT203_KEYIN3), GPIO_FN(VIO_DR3),
1212 GPIO_FN(D19),
1213 GPIO_FN(LCDD12), GPIO_FN(PORT204_KEYIN4), GPIO_FN(VIO_DR4),
1214 GPIO_FN(D20),
1215 GPIO_FN(LCDD13), GPIO_FN(PORT205_KEYIN5), GPIO_FN(VIO_DR5),
1216 GPIO_FN(D21),
1217 GPIO_FN(LCDD14), GPIO_FN(PORT206_KEYIN6), GPIO_FN(VIO_DR6),
1218 GPIO_FN(D22),
1219 GPIO_FN(LCDD15), GPIO_FN(PORT207_MSIOF0L_SS1), GPIO_FN(PORT207_KEYOUT0),
1220 GPIO_FN(VIO_DR7), GPIO_FN(D23),
1221 GPIO_FN(LCDD16), GPIO_FN(PORT208_MSIOF0L_SS2), GPIO_FN(PORT208_KEYOUT1),
1222 GPIO_FN(VIO_VDR), GPIO_FN(D24),
1223 GPIO_FN(LCDD17), GPIO_FN(PORT209_KEYOUT2), GPIO_FN(VIO_HDR),
1224 GPIO_FN(D25),
1225 GPIO_FN(LCDD18), GPIO_FN(DREQ2), GPIO_FN(PORT210_MSIOF0L_SS1),
1226 GPIO_FN(D26),
1227 GPIO_FN(LCDD19), GPIO_FN(PORT211_MSIOF0L_SS2), GPIO_FN(D27),
1228 GPIO_FN(LCDD20), GPIO_FN(TS_SPSYNC1), GPIO_FN(MSIOF0L_MCK0),
1229 GPIO_FN(D28),
1230 GPIO_FN(LCDD21), GPIO_FN(TS_SDAT1), GPIO_FN(MSIOF0L_MCK1),
1231 GPIO_FN(D29),
1232 GPIO_FN(LCDD22), GPIO_FN(TS_SDEN1), GPIO_FN(MSIOF0L_RSCK),
1233 GPIO_FN(D30),
1234 GPIO_FN(LCDD23), GPIO_FN(TS_SCK1), GPIO_FN(MSIOF0L_RSYNC),
1235 GPIO_FN(D31),
1236 GPIO_FN(LCDDCK), GPIO_FN(LCDWR), GPIO_FN(PORT216_KEYOUT3),
1237 GPIO_FN(VIO_CLKR),
1238 GPIO_FN(LCDRD), GPIO_FN(DACK2), GPIO_FN(MSIOF0L_TSYNC),
1239 GPIO_FN(LCDHSYN), GPIO_FN(LCDCS), GPIO_FN(LCDCS2), GPIO_FN(DACK3),
1240 GPIO_FN(PORT218_VIO_CKOR), GPIO_FN(PORT218_KEYOUT4),
1241 GPIO_FN(LCDDISP), GPIO_FN(LCDRS), GPIO_FN(DREQ3), GPIO_FN(MSIOF0L_TSCK),
1242 GPIO_FN(LCDVSYN), GPIO_FN(LCDVSYN2), GPIO_FN(PORT220_KEYOUT5),
1243 GPIO_FN(LCDLCLK), GPIO_FN(DREQ1), GPIO_FN(PWEN), GPIO_FN(MSIOF0L_RXD),
1244 GPIO_FN(LCDDON), GPIO_FN(LCDDON2), GPIO_FN(DACK1), GPIO_FN(OVCN),
1245 GPIO_FN(MSIOF0L_TXD),
1246 GPIO_FN(SCIFA1_TXD), GPIO_FN(OVCN2),
1247 GPIO_FN(EXTLP), GPIO_FN(SCIFA1_SCK), GPIO_FN(USBTERM),
1248 GPIO_FN(PORT226_VIO_CKO2),
1249 GPIO_FN(SCIFA1_RTS), GPIO_FN(IDIN),
1250 GPIO_FN(SCIFA1_RXD),
1251 GPIO_FN(SCIFA1_CTS), GPIO_FN(MFG1_IN1),
1252 GPIO_FN(MSIOF1_TXD), GPIO_FN(SCIFA2_TXD2), GPIO_FN(PORT230_FSIAOMC),
1253 GPIO_FN(MSIOF1_TSYNC), GPIO_FN(SCIFA2_CTS2), GPIO_FN(PORT231_FSIAOLR),
1254 GPIO_FN(MSIOF1_TSCK), GPIO_FN(SCIFA2_SCK2), GPIO_FN(PORT232_FSIAOBT),
1255 GPIO_FN(MSIOF1_RXD), GPIO_FN(SCIFA2_RXD2), GPIO_FN(GPS_VCOTRIG),
1256 GPIO_FN(PORT233_FSIACK),
1257 GPIO_FN(MSIOF1_RSCK), GPIO_FN(SCIFA2_RTS2), GPIO_FN(PORT234_FSIAOSLD),
1258 GPIO_FN(MSIOF1_RSYNC), GPIO_FN(OPORT0), GPIO_FN(MFG1_IN2),
1259 GPIO_FN(PORT235_FSIAILR),
1260 GPIO_FN(MSIOF1_MCK0), GPIO_FN(I2C_SDA2), GPIO_FN(PORT236_FSIAIBT),
1261 GPIO_FN(MSIOF1_MCK1), GPIO_FN(I2C_SCL2), GPIO_FN(PORT237_FSIAISLD),
1262 GPIO_FN(MSIOF1_SS1), GPIO_FN(EDBGREQ3),
1263
1264 /* 55-5 (FN) */
1265 GPIO_FN(MSIOF1_SS2),
1266 GPIO_FN(SCIFA6_TXD),
1267 GPIO_FN(PORT241_IRDA_OUT), GPIO_FN(PORT241_IROUT), GPIO_FN(MFG4_OUT1),
1268 GPIO_FN(TPU4TO0),
1269 GPIO_FN(PORT242_IRDA_IN), GPIO_FN(MFG4_IN2),
1270 GPIO_FN(PORT243_IRDA_FIRSEL), GPIO_FN(PORT243_VIO_CKO2),
1271 GPIO_FN(PORT244_SCIFA5_CTS), GPIO_FN(MFG2_IN1),
1272 GPIO_FN(PORT244_SCIFB_CTS),
1273 GPIO_FN(PORT245_SCIFA5_RTS), GPIO_FN(MFG2_IN2),
1274 GPIO_FN(PORT245_SCIFB_RTS),
1275 GPIO_FN(PORT246_SCIFA5_RXD), GPIO_FN(MFG1_OUT1),
1276 GPIO_FN(PORT246_SCIFB_RXD), GPIO_FN(TPU1TO0),
1277 GPIO_FN(PORT247_SCIFA5_TXD), GPIO_FN(MFG3_OUT2),
1278 GPIO_FN(PORT247_SCIFB_TXD), GPIO_FN(TPU3TO1),
1279 GPIO_FN(PORT248_SCIFA5_SCK), GPIO_FN(MFG2_OUT1),
1280 GPIO_FN(PORT248_SCIFB_SCK), GPIO_FN(TPU2TO0),
1281 GPIO_FN(PORT249_IROUT), GPIO_FN(MFG4_IN1),
1282 GPIO_FN(SDHICLK0), GPIO_FN(TCK2_SWCLK_MC0),
1283 GPIO_FN(SDHICD0),
1284 GPIO_FN(SDHID0_0), GPIO_FN(TMS2_SWDIO_MC0),
1285 GPIO_FN(SDHID0_1), GPIO_FN(TDO2_SWO0_MC0),
1286 GPIO_FN(SDHID0_2), GPIO_FN(TDI2),
1287 GPIO_FN(SDHID0_3), GPIO_FN(RTCK2_SWO1_MC0),
1288 GPIO_FN(SDHICMD0), GPIO_FN(TRST2),
1289 GPIO_FN(SDHIWP0), GPIO_FN(EDBGREQ2),
1290 GPIO_FN(SDHICLK1), GPIO_FN(TCK3_SWCLK_MC1),
1291 GPIO_FN(SDHID1_0), GPIO_FN(M11_SLCD_SO2), GPIO_FN(TS_SPSYNC2),
1292 GPIO_FN(TMS3_SWDIO_MC1),
1293 GPIO_FN(SDHID1_1), GPIO_FN(M9_SLCD_A02), GPIO_FN(TS_SDAT2),
1294 GPIO_FN(TDO3_SWO0_MC1),
1295 GPIO_FN(SDHID1_2), GPIO_FN(M10_SLCD_CK2), GPIO_FN(TS_SDEN2),
1296 GPIO_FN(TDI3),
1297 GPIO_FN(SDHID1_3), GPIO_FN(M12_SLCD_CE2), GPIO_FN(TS_SCK2),
1298 GPIO_FN(RTCK3_SWO1_MC1),
1299 GPIO_FN(SDHICMD1), GPIO_FN(TRST3),
1300 GPIO_FN(RESETOUTS),
1301};
1302
1303static struct pinmux_cfg_reg pinmux_config_regs[] = {
1304 PORTCR(0, 0xe6050000), /* PORT0CR */
1305 PORTCR(1, 0xe6050001), /* PORT1CR */
1306 PORTCR(2, 0xe6050002), /* PORT2CR */
1307 PORTCR(3, 0xe6050003), /* PORT3CR */
1308 PORTCR(4, 0xe6050004), /* PORT4CR */
1309 PORTCR(5, 0xe6050005), /* PORT5CR */
1310 PORTCR(6, 0xe6050006), /* PORT6CR */
1311 PORTCR(7, 0xe6050007), /* PORT7CR */
1312 PORTCR(8, 0xe6050008), /* PORT8CR */
1313 PORTCR(9, 0xe6050009), /* PORT9CR */
1314
1315 PORTCR(10, 0xe605000a), /* PORT10CR */
1316 PORTCR(11, 0xe605000b), /* PORT11CR */
1317 PORTCR(12, 0xe605000c), /* PORT12CR */
1318 PORTCR(13, 0xe605000d), /* PORT13CR */
1319 PORTCR(14, 0xe605000e), /* PORT14CR */
1320 PORTCR(15, 0xe605000f), /* PORT15CR */
1321 PORTCR(16, 0xe6050010), /* PORT16CR */
1322 PORTCR(17, 0xe6050011), /* PORT17CR */
1323 PORTCR(18, 0xe6050012), /* PORT18CR */
1324 PORTCR(19, 0xe6050013), /* PORT19CR */
1325
1326 PORTCR(20, 0xe6050014), /* PORT20CR */
1327 PORTCR(21, 0xe6050015), /* PORT21CR */
1328 PORTCR(22, 0xe6050016), /* PORT22CR */
1329 PORTCR(23, 0xe6050017), /* PORT23CR */
1330 PORTCR(24, 0xe6050018), /* PORT24CR */
1331 PORTCR(25, 0xe6050019), /* PORT25CR */
1332 PORTCR(26, 0xe605001a), /* PORT26CR */
1333 PORTCR(27, 0xe605001b), /* PORT27CR */
1334 PORTCR(28, 0xe605001c), /* PORT28CR */
1335 PORTCR(29, 0xe605001d), /* PORT29CR */
1336
1337 PORTCR(30, 0xe605001e), /* PORT30CR */
1338 PORTCR(31, 0xe605001f), /* PORT31CR */
1339 PORTCR(32, 0xe6050020), /* PORT32CR */
1340 PORTCR(33, 0xe6050021), /* PORT33CR */
1341 PORTCR(34, 0xe6050022), /* PORT34CR */
1342 PORTCR(35, 0xe6050023), /* PORT35CR */
1343 PORTCR(36, 0xe6050024), /* PORT36CR */
1344 PORTCR(37, 0xe6050025), /* PORT37CR */
1345 PORTCR(38, 0xe6050026), /* PORT38CR */
1346 PORTCR(39, 0xe6050027), /* PORT39CR */
1347
1348 PORTCR(40, 0xe6050028), /* PORT40CR */
1349 PORTCR(41, 0xe6050029), /* PORT41CR */
1350 PORTCR(42, 0xe605002a), /* PORT42CR */
1351 PORTCR(43, 0xe605002b), /* PORT43CR */
1352 PORTCR(44, 0xe605002c), /* PORT44CR */
1353 PORTCR(45, 0xe605002d), /* PORT45CR */
1354 PORTCR(46, 0xe605002e), /* PORT46CR */
1355 PORTCR(47, 0xe605002f), /* PORT47CR */
1356 PORTCR(48, 0xe6050030), /* PORT48CR */
1357 PORTCR(49, 0xe6050031), /* PORT49CR */
1358
1359 PORTCR(50, 0xe6050032), /* PORT50CR */
1360 PORTCR(51, 0xe6050033), /* PORT51CR */
1361 PORTCR(52, 0xe6050034), /* PORT52CR */
1362 PORTCR(53, 0xe6050035), /* PORT53CR */
1363 PORTCR(54, 0xe6050036), /* PORT54CR */
1364 PORTCR(55, 0xe6050037), /* PORT55CR */
1365 PORTCR(56, 0xe6050038), /* PORT56CR */
1366 PORTCR(57, 0xe6050039), /* PORT57CR */
1367 PORTCR(58, 0xe605003a), /* PORT58CR */
1368 PORTCR(59, 0xe605003b), /* PORT59CR */
1369
1370 PORTCR(60, 0xe605003c), /* PORT60CR */
1371 PORTCR(61, 0xe605003d), /* PORT61CR */
1372 PORTCR(62, 0xe605003e), /* PORT62CR */
1373 PORTCR(63, 0xe605003f), /* PORT63CR */
1374 PORTCR(64, 0xe6050040), /* PORT64CR */
1375 PORTCR(65, 0xe6050041), /* PORT65CR */
1376 PORTCR(66, 0xe6050042), /* PORT66CR */
1377 PORTCR(67, 0xe6050043), /* PORT67CR */
1378 PORTCR(68, 0xe6050044), /* PORT68CR */
1379 PORTCR(69, 0xe6050045), /* PORT69CR */
1380
1381 PORTCR(70, 0xe6050046), /* PORT70CR */
1382 PORTCR(71, 0xe6050047), /* PORT71CR */
1383 PORTCR(72, 0xe6050048), /* PORT72CR */
1384 PORTCR(73, 0xe6050049), /* PORT73CR */
1385 PORTCR(74, 0xe605004a), /* PORT74CR */
1386 PORTCR(75, 0xe605004b), /* PORT75CR */
1387 PORTCR(76, 0xe605004c), /* PORT76CR */
1388 PORTCR(77, 0xe605004d), /* PORT77CR */
1389 PORTCR(78, 0xe605004e), /* PORT78CR */
1390 PORTCR(79, 0xe605004f), /* PORT79CR */
1391
1392 PORTCR(80, 0xe6050050), /* PORT80CR */
1393 PORTCR(81, 0xe6050051), /* PORT81CR */
1394 PORTCR(82, 0xe6050052), /* PORT82CR */
1395 PORTCR(83, 0xe6050053), /* PORT83CR */
1396 PORTCR(84, 0xe6050054), /* PORT84CR */
1397 PORTCR(85, 0xe6050055), /* PORT85CR */
1398 PORTCR(86, 0xe6050056), /* PORT86CR */
1399 PORTCR(87, 0xe6050057), /* PORT87CR */
1400 PORTCR(88, 0xe6050058), /* PORT88CR */
1401 PORTCR(89, 0xe6050059), /* PORT89CR */
1402
1403 PORTCR(90, 0xe605005a), /* PORT90CR */
1404 PORTCR(91, 0xe605005b), /* PORT91CR */
1405 PORTCR(92, 0xe605005c), /* PORT92CR */
1406 PORTCR(93, 0xe605005d), /* PORT93CR */
1407 PORTCR(94, 0xe605005e), /* PORT94CR */
1408 PORTCR(95, 0xe605005f), /* PORT95CR */
1409 PORTCR(96, 0xe6050060), /* PORT96CR */
1410 PORTCR(97, 0xe6050061), /* PORT97CR */
1411 PORTCR(98, 0xe6050062), /* PORT98CR */
1412 PORTCR(99, 0xe6050063), /* PORT99CR */
1413
1414 PORTCR(100, 0xe6050064), /* PORT100CR */
1415 PORTCR(101, 0xe6050065), /* PORT101CR */
1416 PORTCR(102, 0xe6050066), /* PORT102CR */
1417 PORTCR(103, 0xe6050067), /* PORT103CR */
1418 PORTCR(104, 0xe6050068), /* PORT104CR */
1419 PORTCR(105, 0xe6050069), /* PORT105CR */
1420 PORTCR(106, 0xe605006a), /* PORT106CR */
1421 PORTCR(107, 0xe605006b), /* PORT107CR */
1422 PORTCR(108, 0xe605006c), /* PORT108CR */
1423 PORTCR(109, 0xe605006d), /* PORT109CR */
1424
1425 PORTCR(110, 0xe605006e), /* PORT110CR */
1426 PORTCR(111, 0xe605006f), /* PORT111CR */
1427 PORTCR(112, 0xe6050070), /* PORT112CR */
1428 PORTCR(113, 0xe6050071), /* PORT113CR */
1429 PORTCR(114, 0xe6050072), /* PORT114CR */
1430 PORTCR(115, 0xe6050073), /* PORT115CR */
1431 PORTCR(116, 0xe6050074), /* PORT116CR */
1432 PORTCR(117, 0xe6050075), /* PORT117CR */
1433 PORTCR(118, 0xe6050076), /* PORT118CR */
1434
1435 PORTCR(128, 0xe6051080), /* PORT128CR */
1436 PORTCR(129, 0xe6051081), /* PORT129CR */
1437
1438 PORTCR(130, 0xe6051082), /* PORT130CR */
1439 PORTCR(131, 0xe6051083), /* PORT131CR */
1440 PORTCR(132, 0xe6051084), /* PORT132CR */
1441 PORTCR(133, 0xe6051085), /* PORT133CR */
1442 PORTCR(134, 0xe6051086), /* PORT134CR */
1443 PORTCR(135, 0xe6051087), /* PORT135CR */
1444 PORTCR(136, 0xe6051088), /* PORT136CR */
1445 PORTCR(137, 0xe6051089), /* PORT137CR */
1446 PORTCR(138, 0xe605108a), /* PORT138CR */
1447 PORTCR(139, 0xe605108b), /* PORT139CR */
1448
1449 PORTCR(140, 0xe605108c), /* PORT140CR */
1450 PORTCR(141, 0xe605108d), /* PORT141CR */
1451 PORTCR(142, 0xe605108e), /* PORT142CR */
1452 PORTCR(143, 0xe605108f), /* PORT143CR */
1453 PORTCR(144, 0xe6051090), /* PORT144CR */
1454 PORTCR(145, 0xe6051091), /* PORT145CR */
1455 PORTCR(146, 0xe6051092), /* PORT146CR */
1456 PORTCR(147, 0xe6051093), /* PORT147CR */
1457 PORTCR(148, 0xe6051094), /* PORT148CR */
1458 PORTCR(149, 0xe6051095), /* PORT149CR */
1459
1460 PORTCR(150, 0xe6051096), /* PORT150CR */
1461 PORTCR(151, 0xe6051097), /* PORT151CR */
1462 PORTCR(152, 0xe6051098), /* PORT152CR */
1463 PORTCR(153, 0xe6051099), /* PORT153CR */
1464 PORTCR(154, 0xe605109a), /* PORT154CR */
1465 PORTCR(155, 0xe605109b), /* PORT155CR */
1466 PORTCR(156, 0xe605109c), /* PORT156CR */
1467 PORTCR(157, 0xe605109d), /* PORT157CR */
1468 PORTCR(158, 0xe605109e), /* PORT158CR */
1469 PORTCR(159, 0xe605109f), /* PORT159CR */
1470
1471 PORTCR(160, 0xe60510a0), /* PORT160CR */
1472 PORTCR(161, 0xe60510a1), /* PORT161CR */
1473 PORTCR(162, 0xe60510a2), /* PORT162CR */
1474 PORTCR(163, 0xe60510a3), /* PORT163CR */
1475 PORTCR(164, 0xe60510a4), /* PORT164CR */
1476
1477 PORTCR(192, 0xe60520c0), /* PORT192CR */
1478 PORTCR(193, 0xe60520c1), /* PORT193CR */
1479 PORTCR(194, 0xe60520c2), /* PORT194CR */
1480 PORTCR(195, 0xe60520c3), /* PORT195CR */
1481 PORTCR(196, 0xe60520c4), /* PORT196CR */
1482 PORTCR(197, 0xe60520c5), /* PORT197CR */
1483 PORTCR(198, 0xe60520c6), /* PORT198CR */
1484 PORTCR(199, 0xe60520c7), /* PORT199CR */
1485
1486 PORTCR(200, 0xe60520c8), /* PORT200CR */
1487 PORTCR(201, 0xe60520c9), /* PORT201CR */
1488 PORTCR(202, 0xe60520ca), /* PORT202CR */
1489 PORTCR(203, 0xe60520cb), /* PORT203CR */
1490 PORTCR(204, 0xe60520cc), /* PORT204CR */
1491 PORTCR(205, 0xe60520cd), /* PORT205CR */
1492 PORTCR(206, 0xe60520ce), /* PORT206CR */
1493 PORTCR(207, 0xe60520cf), /* PORT207CR */
1494 PORTCR(208, 0xe60520d0), /* PORT208CR */
1495 PORTCR(209, 0xe60520d1), /* PORT209CR */
1496
1497 PORTCR(210, 0xe60520d2), /* PORT210CR */
1498 PORTCR(211, 0xe60520d3), /* PORT211CR */
1499 PORTCR(212, 0xe60520d4), /* PORT212CR */
1500 PORTCR(213, 0xe60520d5), /* PORT213CR */
1501 PORTCR(214, 0xe60520d6), /* PORT214CR */
1502 PORTCR(215, 0xe60520d7), /* PORT215CR */
1503 PORTCR(216, 0xe60520d8), /* PORT216CR */
1504 PORTCR(217, 0xe60520d9), /* PORT217CR */
1505 PORTCR(218, 0xe60520da), /* PORT218CR */
1506 PORTCR(219, 0xe60520db), /* PORT219CR */
1507
1508 PORTCR(220, 0xe60520dc), /* PORT220CR */
1509 PORTCR(221, 0xe60520dd), /* PORT221CR */
1510 PORTCR(222, 0xe60520de), /* PORT222CR */
1511 PORTCR(223, 0xe60520df), /* PORT223CR */
1512 PORTCR(224, 0xe60520e0), /* PORT224CR */
1513 PORTCR(225, 0xe60520e1), /* PORT225CR */
1514 PORTCR(226, 0xe60520e2), /* PORT226CR */
1515 PORTCR(227, 0xe60520e3), /* PORT227CR */
1516 PORTCR(228, 0xe60520e4), /* PORT228CR */
1517 PORTCR(229, 0xe60520e5), /* PORT229CR */
1518
1519 PORTCR(230, 0xe60520e6), /* PORT230CR */
1520 PORTCR(231, 0xe60520e7), /* PORT231CR */
1521 PORTCR(232, 0xe60520e8), /* PORT232CR */
1522 PORTCR(233, 0xe60520e9), /* PORT233CR */
1523 PORTCR(234, 0xe60520ea), /* PORT234CR */
1524 PORTCR(235, 0xe60520eb), /* PORT235CR */
1525 PORTCR(236, 0xe60520ec), /* PORT236CR */
1526 PORTCR(237, 0xe60520ed), /* PORT237CR */
1527 PORTCR(238, 0xe60520ee), /* PORT238CR */
1528 PORTCR(239, 0xe60520ef), /* PORT239CR */
1529
1530 PORTCR(240, 0xe60520f0), /* PORT240CR */
1531 PORTCR(241, 0xe60520f1), /* PORT241CR */
1532 PORTCR(242, 0xe60520f2), /* PORT242CR */
1533 PORTCR(243, 0xe60520f3), /* PORT243CR */
1534 PORTCR(244, 0xe60520f4), /* PORT244CR */
1535 PORTCR(245, 0xe60520f5), /* PORT245CR */
1536 PORTCR(246, 0xe60520f6), /* PORT246CR */
1537 PORTCR(247, 0xe60520f7), /* PORT247CR */
1538 PORTCR(248, 0xe60520f8), /* PORT248CR */
1539 PORTCR(249, 0xe60520f9), /* PORT249CR */
1540
1541 PORTCR(250, 0xe60520fa), /* PORT250CR */
1542 PORTCR(251, 0xe60520fb), /* PORT251CR */
1543 PORTCR(252, 0xe60520fc), /* PORT252CR */
1544 PORTCR(253, 0xe60520fd), /* PORT253CR */
1545 PORTCR(254, 0xe60520fe), /* PORT254CR */
1546 PORTCR(255, 0xe60520ff), /* PORT255CR */
1547 PORTCR(256, 0xe6052100), /* PORT256CR */
1548 PORTCR(257, 0xe6052101), /* PORT257CR */
1549 PORTCR(258, 0xe6052102), /* PORT258CR */
1550 PORTCR(259, 0xe6052103), /* PORT259CR */
1551
1552 PORTCR(260, 0xe6052104), /* PORT260CR */
1553 PORTCR(261, 0xe6052105), /* PORT261CR */
1554 PORTCR(262, 0xe6052106), /* PORT262CR */
1555 PORTCR(263, 0xe6052107), /* PORT263CR */
1556 PORTCR(264, 0xe6052108), /* PORT264CR */
1557
1558 { PINMUX_CFG_REG("MSELBCR", 0xe6058024, 32, 1) {
1559 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1560 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1561 MSELBCR_MSEL17_0, MSELBCR_MSEL17_1,
1562 MSELBCR_MSEL16_0, MSELBCR_MSEL16_1,
1563 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1564 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
1565 },
1566 { },
1567};
1568
1569static struct pinmux_data_reg pinmux_data_regs[] = {
1570 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
1571 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
1572 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
1573 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
1574 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
1575 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
1576 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
1577 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
1578 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
1579 },
1580 { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054004, 32) {
1581 PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
1582 PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
1583 PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
1584 PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
1585 PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
1586 PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
1587 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
1588 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
1589 },
1590 { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054008, 32) {
1591 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
1592 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
1593 PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
1594 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
1595 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
1596 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
1597 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
1598 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
1599 },
1600 { PINMUX_DATA_REG("PORTD127_096DR", 0xe605400C, 32) {
1601 0, 0, 0, 0,
1602 0, 0, 0, 0,
1603 0, PORT118_DATA, PORT117_DATA, PORT116_DATA,
1604 PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
1605 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
1606 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
1607 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
1608 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
1609 },
1610 { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055000, 32) {
1611 PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
1612 PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
1613 PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
1614 PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
1615 PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
1616 PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
1617 PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
1618 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
1619 },
1620 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6055004, 32) {
1621 0, 0, 0, 0,
1622 0, 0, 0, 0,
1623 0, 0, 0, 0,
1624 0, 0, 0, 0,
1625 0, 0, 0, 0,
1626 0, 0, 0, 0,
1627 0, 0, 0, PORT164_DATA,
1628 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
1629 },
1630 { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056000, 32) {
1631 PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
1632 PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
1633 PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
1634 PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
1635 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
1636 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
1637 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
1638 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
1639 },
1640 { PINMUX_DATA_REG("PORTU255_224DR", 0xe6056004, 32) {
1641 PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
1642 PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
1643 PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
1644 PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
1645 PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
1646 PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
1647 PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
1648 PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
1649 },
1650 { PINMUX_DATA_REG("PORTU287_256DR", 0xe6056008, 32) {
1651 0, 0, 0, 0,
1652 0, 0, 0, 0,
1653 0, 0, 0, 0,
1654 0, 0, 0, 0,
1655 0, 0, 0, 0,
1656 0, 0, 0, PORT264_DATA,
1657 PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
1658 PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
1659 },
1660 { },
1661};
1662
1663static struct pinmux_info sh7377_pinmux_info = {
1664 .name = "sh7377_pfc",
1665 .reserved_id = PINMUX_RESERVED,
1666 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
1667 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
1668 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
1669 .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
1670 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
1671 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
1672 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1673
1674 .first_gpio = GPIO_PORT0,
1675 .last_gpio = GPIO_FN_RESETOUTS,
1676
1677 .gpios = pinmux_gpios,
1678 .cfg_regs = pinmux_config_regs,
1679 .data_regs = pinmux_data_regs,
1680
1681 .gpio_data = pinmux_data,
1682 .gpio_data_size = ARRAY_SIZE(pinmux_data),
1683};
1684
1685void sh7377_pinmux_init(void)
1686{
1687 register_pinmux(&sh7377_pinmux_info);
1688}
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 11bb1d984197..6ac242cdca7f 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -590,6 +590,21 @@ static struct platform_device i2c1_device = {
590 .num_resources = ARRAY_SIZE(i2c1_resources), 590 .num_resources = ARRAY_SIZE(i2c1_resources),
591}; 591};
592 592
593static struct resource pmu_resources[] = {
594 [0] = {
595 .start = evt2irq(0x19a0),
596 .end = evt2irq(0x19a0),
597 .flags = IORESOURCE_IRQ,
598 },
599};
600
601static struct platform_device pmu_device = {
602 .name = "arm-pmu",
603 .id = -1,
604 .num_resources = ARRAY_SIZE(pmu_resources),
605 .resource = pmu_resources,
606};
607
593static struct platform_device *r8a7740_late_devices[] __initdata = { 608static struct platform_device *r8a7740_late_devices[] __initdata = {
594 &i2c0_device, 609 &i2c0_device,
595 &i2c1_device, 610 &i2c1_device,
@@ -597,6 +612,7 @@ static struct platform_device *r8a7740_late_devices[] __initdata = {
597 &dma1_device, 612 &dma1_device,
598 &dma2_device, 613 &dma2_device,
599 &usb_dma_device, 614 &usb_dma_device,
615 &pmu_device,
600}; 616};
601 617
602/* 618/*
@@ -747,7 +763,7 @@ static const char *r8a7740_boards_compat_dt[] __initdata = {
747 NULL, 763 NULL,
748}; 764};
749 765
750DT_MACHINE_START(SH7372_DT, "Generic R8A7740 (Flattened Device Tree)") 766DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
751 .map_io = r8a7740_map_io, 767 .map_io = r8a7740_map_io,
752 .init_early = r8a7740_add_early_devices_dt, 768 .init_early = r8a7740_add_early_devices_dt,
753 .init_irq = r8a7740_init_irq, 769 .init_irq = r8a7740_init_irq,
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 2917668f0091..63de5cb28e4a 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -229,6 +229,79 @@ static struct platform_device tmu01_device = {
229 .num_resources = ARRAY_SIZE(tmu01_resources), 229 .num_resources = ARRAY_SIZE(tmu01_resources),
230}; 230};
231 231
232/* I2C */
233static struct resource rcar_i2c0_res[] = {
234 {
235 .start = 0xffc70000,
236 .end = 0xffc70fff,
237 .flags = IORESOURCE_MEM,
238 }, {
239 .start = gic_spi(79),
240 .flags = IORESOURCE_IRQ,
241 },
242};
243
244static struct platform_device i2c0_device = {
245 .name = "i2c-rcar",
246 .id = 0,
247 .resource = rcar_i2c0_res,
248 .num_resources = ARRAY_SIZE(rcar_i2c0_res),
249};
250
251static struct resource rcar_i2c1_res[] = {
252 {
253 .start = 0xffc71000,
254 .end = 0xffc71fff,
255 .flags = IORESOURCE_MEM,
256 }, {
257 .start = gic_spi(82),
258 .flags = IORESOURCE_IRQ,
259 },
260};
261
262static struct platform_device i2c1_device = {
263 .name = "i2c-rcar",
264 .id = 1,
265 .resource = rcar_i2c1_res,
266 .num_resources = ARRAY_SIZE(rcar_i2c1_res),
267};
268
269static struct resource rcar_i2c2_res[] = {
270 {
271 .start = 0xffc72000,
272 .end = 0xffc72fff,
273 .flags = IORESOURCE_MEM,
274 }, {
275 .start = gic_spi(80),
276 .flags = IORESOURCE_IRQ,
277 },
278};
279
280static struct platform_device i2c2_device = {
281 .name = "i2c-rcar",
282 .id = 2,
283 .resource = rcar_i2c2_res,
284 .num_resources = ARRAY_SIZE(rcar_i2c2_res),
285};
286
287static struct resource rcar_i2c3_res[] = {
288 {
289 .start = 0xffc73000,
290 .end = 0xffc73fff,
291 .flags = IORESOURCE_MEM,
292 }, {
293 .start = gic_spi(81),
294 .flags = IORESOURCE_IRQ,
295 },
296};
297
298static struct platform_device i2c3_device = {
299 .name = "i2c-rcar",
300 .id = 3,
301 .resource = rcar_i2c3_res,
302 .num_resources = ARRAY_SIZE(rcar_i2c3_res),
303};
304
232static struct platform_device *r8a7779_early_devices[] __initdata = { 305static struct platform_device *r8a7779_early_devices[] __initdata = {
233 &scif0_device, 306 &scif0_device,
234 &scif1_device, 307 &scif1_device,
@@ -238,6 +311,10 @@ static struct platform_device *r8a7779_early_devices[] __initdata = {
238 &scif5_device, 311 &scif5_device,
239 &tmu00_device, 312 &tmu00_device,
240 &tmu01_device, 313 &tmu01_device,
314 &i2c0_device,
315 &i2c1_device,
316 &i2c2_device,
317 &i2c3_device,
241}; 318};
242 319
243static struct platform_device *r8a7779_late_devices[] __initdata = { 320static struct platform_device *r8a7779_late_devices[] __initdata = {
diff --git a/arch/arm/mach-shmobile/setup-sh7367.c b/arch/arm/mach-shmobile/setup-sh7367.c
deleted file mode 100644
index e647f5410879..000000000000
--- a/arch/arm/mach-shmobile/setup-sh7367.c
+++ /dev/null
@@ -1,481 +0,0 @@
1/*
2 * sh7367 processor support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/platform_device.h>
25#include <linux/uio_driver.h>
26#include <linux/delay.h>
27#include <linux/input.h>
28#include <linux/io.h>
29#include <linux/serial_sci.h>
30#include <linux/sh_timer.h>
31#include <mach/hardware.h>
32#include <mach/common.h>
33#include <mach/irqs.h>
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36#include <asm/mach/map.h>
37#include <asm/mach/time.h>
38
39static struct map_desc sh7367_io_desc[] __initdata = {
40 /* create a 1:1 entity map for 0xe6xxxxxx
41 * used by CPGA, INTC and PFC.
42 */
43 {
44 .virtual = 0xe6000000,
45 .pfn = __phys_to_pfn(0xe6000000),
46 .length = 256 << 20,
47 .type = MT_DEVICE_NONSHARED
48 },
49};
50
51void __init sh7367_map_io(void)
52{
53 iotable_init(sh7367_io_desc, ARRAY_SIZE(sh7367_io_desc));
54}
55
56/* SCIFA0 */
57static struct plat_sci_port scif0_platform_data = {
58 .mapbase = 0xe6c40000,
59 .flags = UPF_BOOT_AUTOCONF,
60 .scscr = SCSCR_RE | SCSCR_TE,
61 .scbrr_algo_id = SCBRR_ALGO_4,
62 .type = PORT_SCIFA,
63 .irqs = { evt2irq(0xc00), evt2irq(0xc00),
64 evt2irq(0xc00), evt2irq(0xc00) },
65};
66
67static struct platform_device scif0_device = {
68 .name = "sh-sci",
69 .id = 0,
70 .dev = {
71 .platform_data = &scif0_platform_data,
72 },
73};
74
75/* SCIFA1 */
76static struct plat_sci_port scif1_platform_data = {
77 .mapbase = 0xe6c50000,
78 .flags = UPF_BOOT_AUTOCONF,
79 .scscr = SCSCR_RE | SCSCR_TE,
80 .scbrr_algo_id = SCBRR_ALGO_4,
81 .type = PORT_SCIFA,
82 .irqs = { evt2irq(0xc20), evt2irq(0xc20),
83 evt2irq(0xc20), evt2irq(0xc20) },
84};
85
86static struct platform_device scif1_device = {
87 .name = "sh-sci",
88 .id = 1,
89 .dev = {
90 .platform_data = &scif1_platform_data,
91 },
92};
93
94/* SCIFA2 */
95static struct plat_sci_port scif2_platform_data = {
96 .mapbase = 0xe6c60000,
97 .flags = UPF_BOOT_AUTOCONF,
98 .scscr = SCSCR_RE | SCSCR_TE,
99 .scbrr_algo_id = SCBRR_ALGO_4,
100 .type = PORT_SCIFA,
101 .irqs = { evt2irq(0xc40), evt2irq(0xc40),
102 evt2irq(0xc40), evt2irq(0xc40) },
103};
104
105static struct platform_device scif2_device = {
106 .name = "sh-sci",
107 .id = 2,
108 .dev = {
109 .platform_data = &scif2_platform_data,
110 },
111};
112
113/* SCIFA3 */
114static struct plat_sci_port scif3_platform_data = {
115 .mapbase = 0xe6c70000,
116 .flags = UPF_BOOT_AUTOCONF,
117 .scscr = SCSCR_RE | SCSCR_TE,
118 .scbrr_algo_id = SCBRR_ALGO_4,
119 .type = PORT_SCIFA,
120 .irqs = { evt2irq(0xc60), evt2irq(0xc60),
121 evt2irq(0xc60), evt2irq(0xc60) },
122};
123
124static struct platform_device scif3_device = {
125 .name = "sh-sci",
126 .id = 3,
127 .dev = {
128 .platform_data = &scif3_platform_data,
129 },
130};
131
132/* SCIFA4 */
133static struct plat_sci_port scif4_platform_data = {
134 .mapbase = 0xe6c80000,
135 .flags = UPF_BOOT_AUTOCONF,
136 .scscr = SCSCR_RE | SCSCR_TE,
137 .scbrr_algo_id = SCBRR_ALGO_4,
138 .type = PORT_SCIFA,
139 .irqs = { evt2irq(0xd20), evt2irq(0xd20),
140 evt2irq(0xd20), evt2irq(0xd20) },
141};
142
143static struct platform_device scif4_device = {
144 .name = "sh-sci",
145 .id = 4,
146 .dev = {
147 .platform_data = &scif4_platform_data,
148 },
149};
150
151/* SCIFA5 */
152static struct plat_sci_port scif5_platform_data = {
153 .mapbase = 0xe6cb0000,
154 .flags = UPF_BOOT_AUTOCONF,
155 .scscr = SCSCR_RE | SCSCR_TE,
156 .scbrr_algo_id = SCBRR_ALGO_4,
157 .type = PORT_SCIFA,
158 .irqs = { evt2irq(0xd40), evt2irq(0xd40),
159 evt2irq(0xd40), evt2irq(0xd40) },
160};
161
162static struct platform_device scif5_device = {
163 .name = "sh-sci",
164 .id = 5,
165 .dev = {
166 .platform_data = &scif5_platform_data,
167 },
168};
169
170/* SCIFB */
171static struct plat_sci_port scif6_platform_data = {
172 .mapbase = 0xe6c30000,
173 .flags = UPF_BOOT_AUTOCONF,
174 .scscr = SCSCR_RE | SCSCR_TE,
175 .scbrr_algo_id = SCBRR_ALGO_4,
176 .type = PORT_SCIFB,
177 .irqs = { evt2irq(0xd60), evt2irq(0xd60),
178 evt2irq(0xd60), evt2irq(0xd60) },
179};
180
181static struct platform_device scif6_device = {
182 .name = "sh-sci",
183 .id = 6,
184 .dev = {
185 .platform_data = &scif6_platform_data,
186 },
187};
188
189static struct sh_timer_config cmt10_platform_data = {
190 .name = "CMT10",
191 .channel_offset = 0x10,
192 .timer_bit = 0,
193 .clockevent_rating = 125,
194 .clocksource_rating = 125,
195};
196
197static struct resource cmt10_resources[] = {
198 [0] = {
199 .name = "CMT10",
200 .start = 0xe6138010,
201 .end = 0xe613801b,
202 .flags = IORESOURCE_MEM,
203 },
204 [1] = {
205 .start = evt2irq(0xb00), /* CMT1_CMT10 */
206 .flags = IORESOURCE_IRQ,
207 },
208};
209
210static struct platform_device cmt10_device = {
211 .name = "sh_cmt",
212 .id = 10,
213 .dev = {
214 .platform_data = &cmt10_platform_data,
215 },
216 .resource = cmt10_resources,
217 .num_resources = ARRAY_SIZE(cmt10_resources),
218};
219
220/* VPU */
221static struct uio_info vpu_platform_data = {
222 .name = "VPU5",
223 .version = "0",
224 .irq = intcs_evt2irq(0x980),
225};
226
227static struct resource vpu_resources[] = {
228 [0] = {
229 .name = "VPU",
230 .start = 0xfe900000,
231 .end = 0xfe902807,
232 .flags = IORESOURCE_MEM,
233 },
234};
235
236static struct platform_device vpu_device = {
237 .name = "uio_pdrv_genirq",
238 .id = 0,
239 .dev = {
240 .platform_data = &vpu_platform_data,
241 },
242 .resource = vpu_resources,
243 .num_resources = ARRAY_SIZE(vpu_resources),
244};
245
246/* VEU0 */
247static struct uio_info veu0_platform_data = {
248 .name = "VEU0",
249 .version = "0",
250 .irq = intcs_evt2irq(0x700),
251};
252
253static struct resource veu0_resources[] = {
254 [0] = {
255 .name = "VEU0",
256 .start = 0xfe920000,
257 .end = 0xfe9200b7,
258 .flags = IORESOURCE_MEM,
259 },
260};
261
262static struct platform_device veu0_device = {
263 .name = "uio_pdrv_genirq",
264 .id = 1,
265 .dev = {
266 .platform_data = &veu0_platform_data,
267 },
268 .resource = veu0_resources,
269 .num_resources = ARRAY_SIZE(veu0_resources),
270};
271
272/* VEU1 */
273static struct uio_info veu1_platform_data = {
274 .name = "VEU1",
275 .version = "0",
276 .irq = intcs_evt2irq(0x720),
277};
278
279static struct resource veu1_resources[] = {
280 [0] = {
281 .name = "VEU1",
282 .start = 0xfe924000,
283 .end = 0xfe9240b7,
284 .flags = IORESOURCE_MEM,
285 },
286};
287
288static struct platform_device veu1_device = {
289 .name = "uio_pdrv_genirq",
290 .id = 2,
291 .dev = {
292 .platform_data = &veu1_platform_data,
293 },
294 .resource = veu1_resources,
295 .num_resources = ARRAY_SIZE(veu1_resources),
296};
297
298/* VEU2 */
299static struct uio_info veu2_platform_data = {
300 .name = "VEU2",
301 .version = "0",
302 .irq = intcs_evt2irq(0x740),
303};
304
305static struct resource veu2_resources[] = {
306 [0] = {
307 .name = "VEU2",
308 .start = 0xfe928000,
309 .end = 0xfe9280b7,
310 .flags = IORESOURCE_MEM,
311 },
312};
313
314static struct platform_device veu2_device = {
315 .name = "uio_pdrv_genirq",
316 .id = 3,
317 .dev = {
318 .platform_data = &veu2_platform_data,
319 },
320 .resource = veu2_resources,
321 .num_resources = ARRAY_SIZE(veu2_resources),
322};
323
324/* VEU3 */
325static struct uio_info veu3_platform_data = {
326 .name = "VEU3",
327 .version = "0",
328 .irq = intcs_evt2irq(0x760),
329};
330
331static struct resource veu3_resources[] = {
332 [0] = {
333 .name = "VEU3",
334 .start = 0xfe92c000,
335 .end = 0xfe92c0b7,
336 .flags = IORESOURCE_MEM,
337 },
338};
339
340static struct platform_device veu3_device = {
341 .name = "uio_pdrv_genirq",
342 .id = 4,
343 .dev = {
344 .platform_data = &veu3_platform_data,
345 },
346 .resource = veu3_resources,
347 .num_resources = ARRAY_SIZE(veu3_resources),
348};
349
350/* VEU2H */
351static struct uio_info veu2h_platform_data = {
352 .name = "VEU2H",
353 .version = "0",
354 .irq = intcs_evt2irq(0x520),
355};
356
357static struct resource veu2h_resources[] = {
358 [0] = {
359 .name = "VEU2H",
360 .start = 0xfe93c000,
361 .end = 0xfe93c27b,
362 .flags = IORESOURCE_MEM,
363 },
364};
365
366static struct platform_device veu2h_device = {
367 .name = "uio_pdrv_genirq",
368 .id = 5,
369 .dev = {
370 .platform_data = &veu2h_platform_data,
371 },
372 .resource = veu2h_resources,
373 .num_resources = ARRAY_SIZE(veu2h_resources),
374};
375
376/* JPU */
377static struct uio_info jpu_platform_data = {
378 .name = "JPU",
379 .version = "0",
380 .irq = intcs_evt2irq(0x560),
381};
382
383static struct resource jpu_resources[] = {
384 [0] = {
385 .name = "JPU",
386 .start = 0xfe980000,
387 .end = 0xfe9902d3,
388 .flags = IORESOURCE_MEM,
389 },
390};
391
392static struct platform_device jpu_device = {
393 .name = "uio_pdrv_genirq",
394 .id = 6,
395 .dev = {
396 .platform_data = &jpu_platform_data,
397 },
398 .resource = jpu_resources,
399 .num_resources = ARRAY_SIZE(jpu_resources),
400};
401
402/* SPU1 */
403static struct uio_info spu1_platform_data = {
404 .name = "SPU1",
405 .version = "0",
406 .irq = evt2irq(0xfc0),
407};
408
409static struct resource spu1_resources[] = {
410 [0] = {
411 .name = "SPU1",
412 .start = 0xfe300000,
413 .end = 0xfe3fffff,
414 .flags = IORESOURCE_MEM,
415 },
416};
417
418static struct platform_device spu1_device = {
419 .name = "uio_pdrv_genirq",
420 .id = 7,
421 .dev = {
422 .platform_data = &spu1_platform_data,
423 },
424 .resource = spu1_resources,
425 .num_resources = ARRAY_SIZE(spu1_resources),
426};
427
428static struct platform_device *sh7367_early_devices[] __initdata = {
429 &scif0_device,
430 &scif1_device,
431 &scif2_device,
432 &scif3_device,
433 &scif4_device,
434 &scif5_device,
435 &scif6_device,
436 &cmt10_device,
437};
438
439static struct platform_device *sh7367_devices[] __initdata = {
440 &vpu_device,
441 &veu0_device,
442 &veu1_device,
443 &veu2_device,
444 &veu3_device,
445 &veu2h_device,
446 &jpu_device,
447 &spu1_device,
448};
449
450void __init sh7367_add_standard_devices(void)
451{
452 platform_add_devices(sh7367_early_devices,
453 ARRAY_SIZE(sh7367_early_devices));
454
455 platform_add_devices(sh7367_devices,
456 ARRAY_SIZE(sh7367_devices));
457}
458
459static void __init sh7367_earlytimer_init(void)
460{
461 sh7367_clock_init();
462 shmobile_earlytimer_init();
463}
464
465#define SYMSTPCR2 IOMEM(0xe6158048)
466#define SYMSTPCR2_CMT1 (1 << 29)
467
468void __init sh7367_add_early_devices(void)
469{
470 /* enable clock to CMT1 */
471 __raw_writel(__raw_readl(SYMSTPCR2) & ~SYMSTPCR2_CMT1, SYMSTPCR2);
472
473 early_platform_add_devices(sh7367_early_devices,
474 ARRAY_SIZE(sh7367_early_devices));
475
476 /* setup early console here as well */
477 shmobile_setup_console();
478
479 /* override timer setup with soc-specific code */
480 shmobile_timer.init = sh7367_earlytimer_init;
481}
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index a07954fbcd22..a36011184c16 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -408,6 +408,26 @@ static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
408 .chcr = CHCR_RX(XMIT_SZ_8BIT), 408 .chcr = CHCR_RX(XMIT_SZ_8BIT),
409 .mid_rid = 0x3e, 409 .mid_rid = 0x3e,
410 }, { 410 }, {
411 .slave_id = SHDMA_SLAVE_FLCTL0_TX,
412 .addr = 0xe6a30050,
413 .chcr = CHCR_TX(XMIT_SZ_32BIT),
414 .mid_rid = 0x83,
415 }, {
416 .slave_id = SHDMA_SLAVE_FLCTL0_RX,
417 .addr = 0xe6a30050,
418 .chcr = CHCR_RX(XMIT_SZ_32BIT),
419 .mid_rid = 0x83,
420 }, {
421 .slave_id = SHDMA_SLAVE_FLCTL1_TX,
422 .addr = 0xe6a30060,
423 .chcr = CHCR_TX(XMIT_SZ_32BIT),
424 .mid_rid = 0x87,
425 }, {
426 .slave_id = SHDMA_SLAVE_FLCTL1_RX,
427 .addr = 0xe6a30060,
428 .chcr = CHCR_RX(XMIT_SZ_32BIT),
429 .mid_rid = 0x87,
430 }, {
411 .slave_id = SHDMA_SLAVE_SDHI0_TX, 431 .slave_id = SHDMA_SLAVE_SDHI0_TX,
412 .addr = 0xe6850030, 432 .addr = 0xe6850030,
413 .chcr = CHCR_TX(XMIT_SZ_16BIT), 433 .chcr = CHCR_TX(XMIT_SZ_16BIT),
diff --git a/arch/arm/mach-shmobile/setup-sh7377.c b/arch/arm/mach-shmobile/setup-sh7377.c
deleted file mode 100644
index edcf98bb7012..000000000000
--- a/arch/arm/mach-shmobile/setup-sh7377.c
+++ /dev/null
@@ -1,549 +0,0 @@
1/*
2 * sh7377 processor support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/platform_device.h>
25#include <linux/of_platform.h>
26#include <linux/uio_driver.h>
27#include <linux/delay.h>
28#include <linux/input.h>
29#include <linux/io.h>
30#include <linux/serial_sci.h>
31#include <linux/sh_intc.h>
32#include <linux/sh_timer.h>
33#include <mach/hardware.h>
34#include <mach/common.h>
35#include <asm/mach/map.h>
36#include <mach/irqs.h>
37#include <asm/mach-types.h>
38#include <asm/mach/arch.h>
39#include <asm/mach/time.h>
40
41static struct map_desc sh7377_io_desc[] __initdata = {
42 /* create a 1:1 entity map for 0xe6xxxxxx
43 * used by CPGA, INTC and PFC.
44 */
45 {
46 .virtual = 0xe6000000,
47 .pfn = __phys_to_pfn(0xe6000000),
48 .length = 256 << 20,
49 .type = MT_DEVICE_NONSHARED
50 },
51};
52
53void __init sh7377_map_io(void)
54{
55 iotable_init(sh7377_io_desc, ARRAY_SIZE(sh7377_io_desc));
56}
57
58/* SCIFA0 */
59static struct plat_sci_port scif0_platform_data = {
60 .mapbase = 0xe6c40000,
61 .flags = UPF_BOOT_AUTOCONF,
62 .scscr = SCSCR_RE | SCSCR_TE,
63 .scbrr_algo_id = SCBRR_ALGO_4,
64 .type = PORT_SCIFA,
65 .irqs = { evt2irq(0xc00), evt2irq(0xc00),
66 evt2irq(0xc00), evt2irq(0xc00) },
67};
68
69static struct platform_device scif0_device = {
70 .name = "sh-sci",
71 .id = 0,
72 .dev = {
73 .platform_data = &scif0_platform_data,
74 },
75};
76
77/* SCIFA1 */
78static struct plat_sci_port scif1_platform_data = {
79 .mapbase = 0xe6c50000,
80 .flags = UPF_BOOT_AUTOCONF,
81 .scscr = SCSCR_RE | SCSCR_TE,
82 .scbrr_algo_id = SCBRR_ALGO_4,
83 .type = PORT_SCIFA,
84 .irqs = { evt2irq(0xc20), evt2irq(0xc20),
85 evt2irq(0xc20), evt2irq(0xc20) },
86};
87
88static struct platform_device scif1_device = {
89 .name = "sh-sci",
90 .id = 1,
91 .dev = {
92 .platform_data = &scif1_platform_data,
93 },
94};
95
96/* SCIFA2 */
97static struct plat_sci_port scif2_platform_data = {
98 .mapbase = 0xe6c60000,
99 .flags = UPF_BOOT_AUTOCONF,
100 .scscr = SCSCR_RE | SCSCR_TE,
101 .scbrr_algo_id = SCBRR_ALGO_4,
102 .type = PORT_SCIFA,
103 .irqs = { evt2irq(0xc40), evt2irq(0xc40),
104 evt2irq(0xc40), evt2irq(0xc40) },
105};
106
107static struct platform_device scif2_device = {
108 .name = "sh-sci",
109 .id = 2,
110 .dev = {
111 .platform_data = &scif2_platform_data,
112 },
113};
114
115/* SCIFA3 */
116static struct plat_sci_port scif3_platform_data = {
117 .mapbase = 0xe6c70000,
118 .flags = UPF_BOOT_AUTOCONF,
119 .scscr = SCSCR_RE | SCSCR_TE,
120 .scbrr_algo_id = SCBRR_ALGO_4,
121 .type = PORT_SCIFA,
122 .irqs = { evt2irq(0xc60), evt2irq(0xc60),
123 evt2irq(0xc60), evt2irq(0xc60) },
124};
125
126static struct platform_device scif3_device = {
127 .name = "sh-sci",
128 .id = 3,
129 .dev = {
130 .platform_data = &scif3_platform_data,
131 },
132};
133
134/* SCIFA4 */
135static struct plat_sci_port scif4_platform_data = {
136 .mapbase = 0xe6c80000,
137 .flags = UPF_BOOT_AUTOCONF,
138 .scscr = SCSCR_RE | SCSCR_TE,
139 .scbrr_algo_id = SCBRR_ALGO_4,
140 .type = PORT_SCIFA,
141 .irqs = { evt2irq(0xd20), evt2irq(0xd20),
142 evt2irq(0xd20), evt2irq(0xd20) },
143};
144
145static struct platform_device scif4_device = {
146 .name = "sh-sci",
147 .id = 4,
148 .dev = {
149 .platform_data = &scif4_platform_data,
150 },
151};
152
153/* SCIFA5 */
154static struct plat_sci_port scif5_platform_data = {
155 .mapbase = 0xe6cb0000,
156 .flags = UPF_BOOT_AUTOCONF,
157 .scscr = SCSCR_RE | SCSCR_TE,
158 .scbrr_algo_id = SCBRR_ALGO_4,
159 .type = PORT_SCIFA,
160 .irqs = { evt2irq(0xd40), evt2irq(0xd40),
161 evt2irq(0xd40), evt2irq(0xd40) },
162};
163
164static struct platform_device scif5_device = {
165 .name = "sh-sci",
166 .id = 5,
167 .dev = {
168 .platform_data = &scif5_platform_data,
169 },
170};
171
172/* SCIFA6 */
173static struct plat_sci_port scif6_platform_data = {
174 .mapbase = 0xe6cc0000,
175 .flags = UPF_BOOT_AUTOCONF,
176 .scscr = SCSCR_RE | SCSCR_TE,
177 .scbrr_algo_id = SCBRR_ALGO_4,
178 .type = PORT_SCIFA,
179 .irqs = { intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80),
180 intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80) },
181};
182
183static struct platform_device scif6_device = {
184 .name = "sh-sci",
185 .id = 6,
186 .dev = {
187 .platform_data = &scif6_platform_data,
188 },
189};
190
191/* SCIFB */
192static struct plat_sci_port scif7_platform_data = {
193 .mapbase = 0xe6c30000,
194 .flags = UPF_BOOT_AUTOCONF,
195 .scscr = SCSCR_RE | SCSCR_TE,
196 .scbrr_algo_id = SCBRR_ALGO_4,
197 .type = PORT_SCIFB,
198 .irqs = { evt2irq(0xd60), evt2irq(0xd60),
199 evt2irq(0xd60), evt2irq(0xd60) },
200};
201
202static struct platform_device scif7_device = {
203 .name = "sh-sci",
204 .id = 7,
205 .dev = {
206 .platform_data = &scif7_platform_data,
207 },
208};
209
210static struct sh_timer_config cmt10_platform_data = {
211 .name = "CMT10",
212 .channel_offset = 0x10,
213 .timer_bit = 0,
214 .clockevent_rating = 125,
215 .clocksource_rating = 125,
216};
217
218static struct resource cmt10_resources[] = {
219 [0] = {
220 .name = "CMT10",
221 .start = 0xe6138010,
222 .end = 0xe613801b,
223 .flags = IORESOURCE_MEM,
224 },
225 [1] = {
226 .start = evt2irq(0xb00), /* CMT1_CMT10 */
227 .flags = IORESOURCE_IRQ,
228 },
229};
230
231static struct platform_device cmt10_device = {
232 .name = "sh_cmt",
233 .id = 10,
234 .dev = {
235 .platform_data = &cmt10_platform_data,
236 },
237 .resource = cmt10_resources,
238 .num_resources = ARRAY_SIZE(cmt10_resources),
239};
240
241/* VPU */
242static struct uio_info vpu_platform_data = {
243 .name = "VPU5HG",
244 .version = "0",
245 .irq = intcs_evt2irq(0x980),
246};
247
248static struct resource vpu_resources[] = {
249 [0] = {
250 .name = "VPU",
251 .start = 0xfe900000,
252 .end = 0xfe900157,
253 .flags = IORESOURCE_MEM,
254 },
255};
256
257static struct platform_device vpu_device = {
258 .name = "uio_pdrv_genirq",
259 .id = 0,
260 .dev = {
261 .platform_data = &vpu_platform_data,
262 },
263 .resource = vpu_resources,
264 .num_resources = ARRAY_SIZE(vpu_resources),
265};
266
267/* VEU0 */
268static struct uio_info veu0_platform_data = {
269 .name = "VEU0",
270 .version = "0",
271 .irq = intcs_evt2irq(0x700),
272};
273
274static struct resource veu0_resources[] = {
275 [0] = {
276 .name = "VEU0",
277 .start = 0xfe920000,
278 .end = 0xfe9200cb,
279 .flags = IORESOURCE_MEM,
280 },
281};
282
283static struct platform_device veu0_device = {
284 .name = "uio_pdrv_genirq",
285 .id = 1,
286 .dev = {
287 .platform_data = &veu0_platform_data,
288 },
289 .resource = veu0_resources,
290 .num_resources = ARRAY_SIZE(veu0_resources),
291};
292
293/* VEU1 */
294static struct uio_info veu1_platform_data = {
295 .name = "VEU1",
296 .version = "0",
297 .irq = intcs_evt2irq(0x720),
298};
299
300static struct resource veu1_resources[] = {
301 [0] = {
302 .name = "VEU1",
303 .start = 0xfe924000,
304 .end = 0xfe9240cb,
305 .flags = IORESOURCE_MEM,
306 },
307};
308
309static struct platform_device veu1_device = {
310 .name = "uio_pdrv_genirq",
311 .id = 2,
312 .dev = {
313 .platform_data = &veu1_platform_data,
314 },
315 .resource = veu1_resources,
316 .num_resources = ARRAY_SIZE(veu1_resources),
317};
318
319/* VEU2 */
320static struct uio_info veu2_platform_data = {
321 .name = "VEU2",
322 .version = "0",
323 .irq = intcs_evt2irq(0x740),
324};
325
326static struct resource veu2_resources[] = {
327 [0] = {
328 .name = "VEU2",
329 .start = 0xfe928000,
330 .end = 0xfe928307,
331 .flags = IORESOURCE_MEM,
332 },
333};
334
335static struct platform_device veu2_device = {
336 .name = "uio_pdrv_genirq",
337 .id = 3,
338 .dev = {
339 .platform_data = &veu2_platform_data,
340 },
341 .resource = veu2_resources,
342 .num_resources = ARRAY_SIZE(veu2_resources),
343};
344
345/* VEU3 */
346static struct uio_info veu3_platform_data = {
347 .name = "VEU3",
348 .version = "0",
349 .irq = intcs_evt2irq(0x760),
350};
351
352static struct resource veu3_resources[] = {
353 [0] = {
354 .name = "VEU3",
355 .start = 0xfe92c000,
356 .end = 0xfe92c307,
357 .flags = IORESOURCE_MEM,
358 },
359};
360
361static struct platform_device veu3_device = {
362 .name = "uio_pdrv_genirq",
363 .id = 4,
364 .dev = {
365 .platform_data = &veu3_platform_data,
366 },
367 .resource = veu3_resources,
368 .num_resources = ARRAY_SIZE(veu3_resources),
369};
370
371/* JPU */
372static struct uio_info jpu_platform_data = {
373 .name = "JPU",
374 .version = "0",
375 .irq = intcs_evt2irq(0x560),
376};
377
378static struct resource jpu_resources[] = {
379 [0] = {
380 .name = "JPU",
381 .start = 0xfe980000,
382 .end = 0xfe9902d3,
383 .flags = IORESOURCE_MEM,
384 },
385};
386
387static struct platform_device jpu_device = {
388 .name = "uio_pdrv_genirq",
389 .id = 5,
390 .dev = {
391 .platform_data = &jpu_platform_data,
392 },
393 .resource = jpu_resources,
394 .num_resources = ARRAY_SIZE(jpu_resources),
395};
396
397/* SPU2DSP0 */
398static struct uio_info spu0_platform_data = {
399 .name = "SPU2DSP0",
400 .version = "0",
401 .irq = evt2irq(0x1800),
402};
403
404static struct resource spu0_resources[] = {
405 [0] = {
406 .name = "SPU2DSP0",
407 .start = 0xfe200000,
408 .end = 0xfe2fffff,
409 .flags = IORESOURCE_MEM,
410 },
411};
412
413static struct platform_device spu0_device = {
414 .name = "uio_pdrv_genirq",
415 .id = 6,
416 .dev = {
417 .platform_data = &spu0_platform_data,
418 },
419 .resource = spu0_resources,
420 .num_resources = ARRAY_SIZE(spu0_resources),
421};
422
423/* SPU2DSP1 */
424static struct uio_info spu1_platform_data = {
425 .name = "SPU2DSP1",
426 .version = "0",
427 .irq = evt2irq(0x1820),
428};
429
430static struct resource spu1_resources[] = {
431 [0] = {
432 .name = "SPU2DSP1",
433 .start = 0xfe300000,
434 .end = 0xfe3fffff,
435 .flags = IORESOURCE_MEM,
436 },
437};
438
439static struct platform_device spu1_device = {
440 .name = "uio_pdrv_genirq",
441 .id = 7,
442 .dev = {
443 .platform_data = &spu1_platform_data,
444 },
445 .resource = spu1_resources,
446 .num_resources = ARRAY_SIZE(spu1_resources),
447};
448
449static struct platform_device *sh7377_early_devices[] __initdata = {
450 &scif0_device,
451 &scif1_device,
452 &scif2_device,
453 &scif3_device,
454 &scif4_device,
455 &scif5_device,
456 &scif6_device,
457 &scif7_device,
458 &cmt10_device,
459};
460
461static struct platform_device *sh7377_devices[] __initdata = {
462 &vpu_device,
463 &veu0_device,
464 &veu1_device,
465 &veu2_device,
466 &veu3_device,
467 &jpu_device,
468 &spu0_device,
469 &spu1_device,
470};
471
472void __init sh7377_add_standard_devices(void)
473{
474 platform_add_devices(sh7377_early_devices,
475 ARRAY_SIZE(sh7377_early_devices));
476
477 platform_add_devices(sh7377_devices,
478 ARRAY_SIZE(sh7377_devices));
479}
480
481static void __init sh7377_earlytimer_init(void)
482{
483 sh7377_clock_init();
484 shmobile_earlytimer_init();
485}
486
487#define SMSTPCR3 IOMEM(0xe615013c)
488#define SMSTPCR3_CMT1 (1 << 29)
489
490void __init sh7377_add_early_devices(void)
491{
492 /* enable clock to CMT1 */
493 __raw_writel(__raw_readl(SMSTPCR3) & ~SMSTPCR3_CMT1, SMSTPCR3);
494
495 early_platform_add_devices(sh7377_early_devices,
496 ARRAY_SIZE(sh7377_early_devices));
497
498 /* setup early console here as well */
499 shmobile_setup_console();
500
501 /* override timer setup with soc-specific code */
502 shmobile_timer.init = sh7377_earlytimer_init;
503}
504
505#ifdef CONFIG_USE_OF
506
507void __init sh7377_add_early_devices_dt(void)
508{
509 shmobile_setup_delay(600, 1, 3); /* Cortex-A8 @ 600MHz */
510
511 early_platform_add_devices(sh7377_early_devices,
512 ARRAY_SIZE(sh7377_early_devices));
513
514 /* setup early console here as well */
515 shmobile_setup_console();
516}
517
518static const struct of_dev_auxdata sh7377_auxdata_lookup[] __initconst = {
519 { }
520};
521
522void __init sh7377_add_standard_devices_dt(void)
523{
524 /* clocks are setup late during boot in the case of DT */
525 sh7377_clock_init();
526
527 platform_add_devices(sh7377_early_devices,
528 ARRAY_SIZE(sh7377_early_devices));
529
530 of_platform_populate(NULL, of_default_bus_match_table,
531 sh7377_auxdata_lookup, NULL);
532}
533
534static const char *sh7377_boards_compat_dt[] __initdata = {
535 "renesas,sh7377",
536 NULL,
537};
538
539DT_MACHINE_START(SH7377_DT, "Generic SH7377 (Flattened Device Tree)")
540 .map_io = sh7377_map_io,
541 .init_early = sh7377_add_early_devices_dt,
542 .init_irq = sh7377_init_irq,
543 .handle_irq = shmobile_handle_irq_intc,
544 .init_machine = sh7377_add_standard_devices_dt,
545 .timer = &shmobile_timer,
546 .dt_compat = sh7377_boards_compat_dt,
547MACHINE_END
548
549#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index f67456286280..535426c306bd 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -32,24 +32,8 @@
32 32
33#define EMEV2_SCU_BASE 0x1e000000 33#define EMEV2_SCU_BASE 0x1e000000
34 34
35static DEFINE_SPINLOCK(scu_lock);
36static void __iomem *scu_base; 35static void __iomem *scu_base;
37 36
38static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
39{
40 unsigned long tmp;
41
42 /* we assume this code is running on a different cpu
43 * than the one that is changing coherency setting */
44 spin_lock(&scu_lock);
45 tmp = readl(scu_base + 8);
46 tmp &= ~clr;
47 tmp |= set;
48 writel(tmp, scu_base + 8);
49 spin_unlock(&scu_lock);
50
51}
52
53static unsigned int __init emev2_get_core_count(void) 37static unsigned int __init emev2_get_core_count(void)
54{ 38{
55 if (!scu_base) { 39 if (!scu_base) {
@@ -95,7 +79,7 @@ static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *
95 cpu = cpu_logical_map(cpu); 79 cpu = cpu_logical_map(cpu);
96 80
97 /* enable cache coherency */ 81 /* enable cache coherency */
98 modify_scu_cpu_psr(0, 3 << (cpu * 8)); 82 scu_power_mode(scu_base, 0);
99 83
100 /* Tell ROM loader about our vector (in headsmp.S) */ 84 /* Tell ROM loader about our vector (in headsmp.S) */
101 emev2_set_boot_vector(__pa(shmobile_secondary_vector)); 85 emev2_set_boot_vector(__pa(shmobile_secondary_vector));
@@ -106,12 +90,10 @@ static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *
106 90
107static void __init emev2_smp_prepare_cpus(unsigned int max_cpus) 91static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
108{ 92{
109 int cpu = cpu_logical_map(0);
110
111 scu_enable(scu_base); 93 scu_enable(scu_base);
112 94
113 /* enable cache coherency on CPU0 */ 95 /* enable cache coherency on CPU0 */
114 modify_scu_cpu_psr(0, 3 << (cpu * 8)); 96 scu_power_mode(scu_base, 0);
115} 97}
116 98
117static void __init emev2_smp_init_cpus(void) 99static void __init emev2_smp_init_cpus(void)
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index 2ce6af9a6a37..9def0f22bf22 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -61,9 +61,6 @@ static void __iomem *scu_base_addr(void)
61 return (void __iomem *)0xf0000000; 61 return (void __iomem *)0xf0000000;
62} 62}
63 63
64static DEFINE_SPINLOCK(scu_lock);
65static unsigned long tmp;
66
67#ifdef CONFIG_HAVE_ARM_TWD 64#ifdef CONFIG_HAVE_ARM_TWD
68static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29); 65static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
69 66
@@ -73,20 +70,6 @@ void __init r8a7779_register_twd(void)
73} 70}
74#endif 71#endif
75 72
76static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
77{
78 void __iomem *scu_base = scu_base_addr();
79
80 spin_lock(&scu_lock);
81 tmp = __raw_readl(scu_base + 8);
82 tmp &= ~clr;
83 tmp |= set;
84 spin_unlock(&scu_lock);
85
86 /* disable cache coherency after releasing the lock */
87 __raw_writel(tmp, scu_base + 8);
88}
89
90static unsigned int __init r8a7779_get_core_count(void) 73static unsigned int __init r8a7779_get_core_count(void)
91{ 74{
92 void __iomem *scu_base = scu_base_addr(); 75 void __iomem *scu_base = scu_base_addr();
@@ -102,7 +85,7 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu)
102 cpu = cpu_logical_map(cpu); 85 cpu = cpu_logical_map(cpu);
103 86
104 /* disable cache coherency */ 87 /* disable cache coherency */
105 modify_scu_cpu_psr(3 << (cpu * 8), 0); 88 scu_power_mode(scu_base_addr(), 3);
106 89
107 if (cpu < ARRAY_SIZE(r8a7779_ch_cpu)) 90 if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
108 ch = r8a7779_ch_cpu[cpu]; 91 ch = r8a7779_ch_cpu[cpu];
@@ -145,7 +128,7 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct
145 cpu = cpu_logical_map(cpu); 128 cpu = cpu_logical_map(cpu);
146 129
147 /* enable cache coherency */ 130 /* enable cache coherency */
148 modify_scu_cpu_psr(0, 3 << (cpu * 8)); 131 scu_power_mode(scu_base_addr(), 0);
149 132
150 if (cpu < ARRAY_SIZE(r8a7779_ch_cpu)) 133 if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
151 ch = r8a7779_ch_cpu[cpu]; 134 ch = r8a7779_ch_cpu[cpu];
@@ -158,15 +141,13 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct
158 141
159static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) 142static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
160{ 143{
161 int cpu = cpu_logical_map(0);
162
163 scu_enable(scu_base_addr()); 144 scu_enable(scu_base_addr());
164 145
165 /* Map the reset vector (in headsmp.S) */ 146 /* Map the reset vector (in headsmp.S) */
166 __raw_writel(__pa(shmobile_secondary_vector), AVECR); 147 __raw_writel(__pa(shmobile_secondary_vector), AVECR);
167 148
168 /* enable cache coherency on CPU0 */ 149 /* enable cache coherency on CPU0 */
169 modify_scu_cpu_psr(0, 3 << (cpu * 8)); 150 scu_power_mode(scu_base_addr(), 0);
170 151
171 r8a7779_pm_init(); 152 r8a7779_pm_init();
172 153
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index 624f00f70abf..96ddb97babbe 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -41,9 +41,6 @@ static void __iomem *scu_base_addr(void)
41 return (void __iomem *)0xf0000000; 41 return (void __iomem *)0xf0000000;
42} 42}
43 43
44static DEFINE_SPINLOCK(scu_lock);
45static unsigned long tmp;
46
47#ifdef CONFIG_HAVE_ARM_TWD 44#ifdef CONFIG_HAVE_ARM_TWD
48static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29); 45static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
49void __init sh73a0_register_twd(void) 46void __init sh73a0_register_twd(void)
@@ -52,20 +49,6 @@ void __init sh73a0_register_twd(void)
52} 49}
53#endif 50#endif
54 51
55static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
56{
57 void __iomem *scu_base = scu_base_addr();
58
59 spin_lock(&scu_lock);
60 tmp = __raw_readl(scu_base + 8);
61 tmp &= ~clr;
62 tmp |= set;
63 spin_unlock(&scu_lock);
64
65 /* disable cache coherency after releasing the lock */
66 __raw_writel(tmp, scu_base + 8);
67}
68
69static unsigned int __init sh73a0_get_core_count(void) 52static unsigned int __init sh73a0_get_core_count(void)
70{ 53{
71 void __iomem *scu_base = scu_base_addr(); 54 void __iomem *scu_base = scu_base_addr();
@@ -83,7 +66,7 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct
83 cpu = cpu_logical_map(cpu); 66 cpu = cpu_logical_map(cpu);
84 67
85 /* enable cache coherency */ 68 /* enable cache coherency */
86 modify_scu_cpu_psr(0, 3 << (cpu * 8)); 69 scu_power_mode(scu_base_addr(), 0);
87 70
88 if (((__raw_readl(PSTR) >> (4 * cpu)) & 3) == 3) 71 if (((__raw_readl(PSTR) >> (4 * cpu)) & 3) == 3)
89 __raw_writel(1 << cpu, WUPCR); /* wake up */ 72 __raw_writel(1 << cpu, WUPCR); /* wake up */
@@ -95,8 +78,6 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct
95 78
96static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) 79static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
97{ 80{
98 int cpu = cpu_logical_map(0);
99
100 scu_enable(scu_base_addr()); 81 scu_enable(scu_base_addr());
101 82
102 /* Map the reset vector (in headsmp.S) */ 83 /* Map the reset vector (in headsmp.S) */
@@ -104,7 +85,7 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
104 __raw_writel(__pa(shmobile_secondary_vector), SBAR); 85 __raw_writel(__pa(shmobile_secondary_vector), SBAR);
105 86
106 /* enable cache coherency on CPU0 */ 87 /* enable cache coherency on CPU0 */
107 modify_scu_cpu_psr(0, 3 << (cpu * 8)); 88 scu_power_mode(scu_base_addr(), 0);
108} 89}
109 90
110static void __init sh73a0_smp_init_cpus(void) 91static void __init sh73a0_smp_init_cpus(void)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 12:54:34 -0500