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-rw-r--r--arch/arm/mach-orion5x/addr-map.c23
1 files changed, 18 insertions, 5 deletions
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index e63fb05dc893..5ffbac9e1570 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -70,6 +70,7 @@
70 70
71 71
72struct mbus_dram_target_info orion5x_mbus_dram_info; 72struct mbus_dram_target_info orion5x_mbus_dram_info;
73static int __initdata win_alloc_count;
73 74
74static int __init orion5x_cpu_win_can_remap(int win) 75static int __init orion5x_cpu_win_can_remap(int win)
75{ 76{
@@ -87,6 +88,12 @@ static int __init orion5x_cpu_win_can_remap(int win)
87static void __init setup_cpu_win(int win, u32 base, u32 size, 88static void __init setup_cpu_win(int win, u32 base, u32 size,
88 u8 target, u8 attr, int remap) 89 u8 target, u8 attr, int remap)
89{ 90{
91 if (win >= 8) {
92 printk(KERN_ERR "setup_cpu_win: trying to allocate "
93 "window %d\n", win);
94 return;
95 }
96
90 orion5x_write(CPU_WIN_BASE(win), base & 0xffff0000); 97 orion5x_write(CPU_WIN_BASE(win), base & 0xffff0000);
91 orion5x_write(CPU_WIN_CTRL(win), 98 orion5x_write(CPU_WIN_CTRL(win),
92 ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1); 99 ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1);
@@ -128,6 +135,7 @@ void __init orion5x_setup_cpu_mbus_bridge(void)
128 TARGET_PCIE, ATTR_PCIE_MEM, -1); 135 TARGET_PCIE, ATTR_PCIE_MEM, -1);
129 setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE, 136 setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE,
130 TARGET_PCI, ATTR_PCI_MEM, -1); 137 TARGET_PCI, ATTR_PCI_MEM, -1);
138 win_alloc_count = 4;
131 139
132 /* 140 /*
133 * Setup MBUS dram target info. 141 * Setup MBUS dram target info.
@@ -156,25 +164,30 @@ void __init orion5x_setup_cpu_mbus_bridge(void)
156 164
157void __init orion5x_setup_dev_boot_win(u32 base, u32 size) 165void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
158{ 166{
159 setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); 167 setup_cpu_win(win_alloc_count++, base, size,
168 TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
160} 169}
161 170
162void __init orion5x_setup_dev0_win(u32 base, u32 size) 171void __init orion5x_setup_dev0_win(u32 base, u32 size)
163{ 172{
164 setup_cpu_win(5, base, size, TARGET_DEV_BUS, ATTR_DEV_CS0, -1); 173 setup_cpu_win(win_alloc_count++, base, size,
174 TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
165} 175}
166 176
167void __init orion5x_setup_dev1_win(u32 base, u32 size) 177void __init orion5x_setup_dev1_win(u32 base, u32 size)
168{ 178{
169 setup_cpu_win(6, base, size, TARGET_DEV_BUS, ATTR_DEV_CS1, -1); 179 setup_cpu_win(win_alloc_count++, base, size,
180 TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
170} 181}
171 182
172void __init orion5x_setup_dev2_win(u32 base, u32 size) 183void __init orion5x_setup_dev2_win(u32 base, u32 size)
173{ 184{
174 setup_cpu_win(7, base, size, TARGET_DEV_BUS, ATTR_DEV_CS2, -1); 185 setup_cpu_win(win_alloc_count++, base, size,
186 TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
175} 187}
176 188
177void __init orion5x_setup_pcie_wa_win(u32 base, u32 size) 189void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
178{ 190{
179 setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1); 191 setup_cpu_win(win_alloc_count++, base, size,
192 TARGET_PCIE, ATTR_PCIE_WA, -1);
180} 193}