diff options
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/tegra20.dtsi | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 5b104f1d5003..d665a67d4358 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi | |||
| @@ -9,6 +9,7 @@ | |||
| 9 | reg = <0x50000000 0x00024000>; | 9 | reg = <0x50000000 0x00024000>; |
| 10 | interrupts = <0 65 0x04 /* mpcore syncpt */ | 10 | interrupts = <0 65 0x04 /* mpcore syncpt */ |
| 11 | 0 67 0x04>; /* mpcore general */ | 11 | 0 67 0x04>; /* mpcore general */ |
| 12 | clocks = <&tegra_car 28>; | ||
| 12 | 13 | ||
| 13 | #address-cells = <1>; | 14 | #address-cells = <1>; |
| 14 | #size-cells = <1>; | 15 | #size-cells = <1>; |
| @@ -19,41 +20,49 @@ | |||
| 19 | compatible = "nvidia,tegra20-mpe"; | 20 | compatible = "nvidia,tegra20-mpe"; |
| 20 | reg = <0x54040000 0x00040000>; | 21 | reg = <0x54040000 0x00040000>; |
| 21 | interrupts = <0 68 0x04>; | 22 | interrupts = <0 68 0x04>; |
| 23 | clocks = <&tegra_car 60>; | ||
| 22 | }; | 24 | }; |
| 23 | 25 | ||
| 24 | vi { | 26 | vi { |
| 25 | compatible = "nvidia,tegra20-vi"; | 27 | compatible = "nvidia,tegra20-vi"; |
| 26 | reg = <0x54080000 0x00040000>; | 28 | reg = <0x54080000 0x00040000>; |
| 27 | interrupts = <0 69 0x04>; | 29 | interrupts = <0 69 0x04>; |
| 30 | clocks = <&tegra_car 100>; | ||
| 28 | }; | 31 | }; |
| 29 | 32 | ||
| 30 | epp { | 33 | epp { |
| 31 | compatible = "nvidia,tegra20-epp"; | 34 | compatible = "nvidia,tegra20-epp"; |
| 32 | reg = <0x540c0000 0x00040000>; | 35 | reg = <0x540c0000 0x00040000>; |
| 33 | interrupts = <0 70 0x04>; | 36 | interrupts = <0 70 0x04>; |
| 37 | clocks = <&tegra_car 19>; | ||
| 34 | }; | 38 | }; |
| 35 | 39 | ||
| 36 | isp { | 40 | isp { |
| 37 | compatible = "nvidia,tegra20-isp"; | 41 | compatible = "nvidia,tegra20-isp"; |
| 38 | reg = <0x54100000 0x00040000>; | 42 | reg = <0x54100000 0x00040000>; |
| 39 | interrupts = <0 71 0x04>; | 43 | interrupts = <0 71 0x04>; |
| 44 | clocks = <&tegra_car 23>; | ||
| 40 | }; | 45 | }; |
| 41 | 46 | ||
| 42 | gr2d { | 47 | gr2d { |
| 43 | compatible = "nvidia,tegra20-gr2d"; | 48 | compatible = "nvidia,tegra20-gr2d"; |
| 44 | reg = <0x54140000 0x00040000>; | 49 | reg = <0x54140000 0x00040000>; |
| 45 | interrupts = <0 72 0x04>; | 50 | interrupts = <0 72 0x04>; |
| 51 | clocks = <&tegra_car 21>; | ||
| 46 | }; | 52 | }; |
| 47 | 53 | ||
| 48 | gr3d { | 54 | gr3d { |
| 49 | compatible = "nvidia,tegra20-gr3d"; | 55 | compatible = "nvidia,tegra20-gr3d"; |
| 50 | reg = <0x54180000 0x00040000>; | 56 | reg = <0x54180000 0x00040000>; |
| 57 | clocks = <&tegra_car 24>; | ||
| 51 | }; | 58 | }; |
| 52 | 59 | ||
| 53 | dc@54200000 { | 60 | dc@54200000 { |
| 54 | compatible = "nvidia,tegra20-dc"; | 61 | compatible = "nvidia,tegra20-dc"; |
| 55 | reg = <0x54200000 0x00040000>; | 62 | reg = <0x54200000 0x00040000>; |
| 56 | interrupts = <0 73 0x04>; | 63 | interrupts = <0 73 0x04>; |
| 64 | clocks = <&tegra_car 27>, <&tegra_car 121>; | ||
| 65 | clock-names = "disp1", "parent"; | ||
| 57 | 66 | ||
| 58 | rgb { | 67 | rgb { |
| 59 | status = "disabled"; | 68 | status = "disabled"; |
| @@ -64,6 +73,8 @@ | |||
| 64 | compatible = "nvidia,tegra20-dc"; | 73 | compatible = "nvidia,tegra20-dc"; |
| 65 | reg = <0x54240000 0x00040000>; | 74 | reg = <0x54240000 0x00040000>; |
| 66 | interrupts = <0 74 0x04>; | 75 | interrupts = <0 74 0x04>; |
| 76 | clocks = <&tegra_car 26>, <&tegra_car 121>; | ||
| 77 | clock-names = "disp2", "parent"; | ||
| 67 | 78 | ||
| 68 | rgb { | 79 | rgb { |
| 69 | status = "disabled"; | 80 | status = "disabled"; |
| @@ -74,6 +85,8 @@ | |||
| 74 | compatible = "nvidia,tegra20-hdmi"; | 85 | compatible = "nvidia,tegra20-hdmi"; |
| 75 | reg = <0x54280000 0x00040000>; | 86 | reg = <0x54280000 0x00040000>; |
| 76 | interrupts = <0 75 0x04>; | 87 | interrupts = <0 75 0x04>; |
| 88 | clocks = <&tegra_car 51>, <&tegra_car 117>; | ||
| 89 | clock-names = "hdmi", "parent"; | ||
| 77 | status = "disabled"; | 90 | status = "disabled"; |
| 78 | }; | 91 | }; |
| 79 | 92 | ||
| @@ -81,12 +94,14 @@ | |||
| 81 | compatible = "nvidia,tegra20-tvo"; | 94 | compatible = "nvidia,tegra20-tvo"; |
| 82 | reg = <0x542c0000 0x00040000>; | 95 | reg = <0x542c0000 0x00040000>; |
| 83 | interrupts = <0 76 0x04>; | 96 | interrupts = <0 76 0x04>; |
| 97 | clocks = <&tegra_car 102>; | ||
| 84 | status = "disabled"; | 98 | status = "disabled"; |
| 85 | }; | 99 | }; |
| 86 | 100 | ||
| 87 | dsi { | 101 | dsi { |
| 88 | compatible = "nvidia,tegra20-dsi"; | 102 | compatible = "nvidia,tegra20-dsi"; |
| 89 | reg = <0x54300000 0x00040000>; | 103 | reg = <0x54300000 0x00040000>; |
| 104 | clocks = <&tegra_car 48>; | ||
| 90 | status = "disabled"; | 105 | status = "disabled"; |
| 91 | }; | 106 | }; |
| 92 | }; | 107 | }; |
| @@ -148,6 +163,7 @@ | |||
| 148 | 0 117 0x04 | 163 | 0 117 0x04 |
| 149 | 0 118 0x04 | 164 | 0 118 0x04 |
| 150 | 0 119 0x04>; | 165 | 0 119 0x04>; |
| 166 | clocks = <&tegra_car 34>; | ||
| 151 | }; | 167 | }; |
| 152 | 168 | ||
| 153 | ahb { | 169 | ahb { |
| @@ -189,6 +205,7 @@ | |||
| 189 | reg = <0x70002800 0x200>; | 205 | reg = <0x70002800 0x200>; |
| 190 | interrupts = <0 13 0x04>; | 206 | interrupts = <0 13 0x04>; |
| 191 | nvidia,dma-request-selector = <&apbdma 2>; | 207 | nvidia,dma-request-selector = <&apbdma 2>; |
| 208 | clocks = <&tegra_car 11>; | ||
| 192 | status = "disabled"; | 209 | status = "disabled"; |
| 193 | }; | 210 | }; |
| 194 | 211 | ||
| @@ -197,6 +214,7 @@ | |||
| 197 | reg = <0x70002a00 0x200>; | 214 | reg = <0x70002a00 0x200>; |
| 198 | interrupts = <0 3 0x04>; | 215 | interrupts = <0 3 0x04>; |
| 199 | nvidia,dma-request-selector = <&apbdma 1>; | 216 | nvidia,dma-request-selector = <&apbdma 1>; |
| 217 | clocks = <&tegra_car 18>; | ||
| 200 | status = "disabled"; | 218 | status = "disabled"; |
| 201 | }; | 219 | }; |
| 202 | 220 | ||
| @@ -205,6 +223,7 @@ | |||
| 205 | reg = <0x70006000 0x40>; | 223 | reg = <0x70006000 0x40>; |
| 206 | reg-shift = <2>; | 224 | reg-shift = <2>; |
| 207 | interrupts = <0 36 0x04>; | 225 | interrupts = <0 36 0x04>; |
| 226 | clocks = <&tegra_car 6>; | ||
| 208 | status = "disabled"; | 227 | status = "disabled"; |
| 209 | }; | 228 | }; |
| 210 | 229 | ||
| @@ -213,6 +232,7 @@ | |||
| 213 | reg = <0x70006040 0x40>; | 232 | reg = <0x70006040 0x40>; |
| 214 | reg-shift = <2>; | 233 | reg-shift = <2>; |
| 215 | interrupts = <0 37 0x04>; | 234 | interrupts = <0 37 0x04>; |
| 235 | clocks = <&tegra_car 96>; | ||
| 216 | status = "disabled"; | 236 | status = "disabled"; |
| 217 | }; | 237 | }; |
| 218 | 238 | ||
| @@ -221,6 +241,7 @@ | |||
| 221 | reg = <0x70006200 0x100>; | 241 | reg = <0x70006200 0x100>; |
| 222 | reg-shift = <2>; | 242 | reg-shift = <2>; |
| 223 | interrupts = <0 46 0x04>; | 243 | interrupts = <0 46 0x04>; |
| 244 | clocks = <&tegra_car 55>; | ||
| 224 | status = "disabled"; | 245 | status = "disabled"; |
| 225 | }; | 246 | }; |
| 226 | 247 | ||
| @@ -229,6 +250,7 @@ | |||
| 229 | reg = <0x70006300 0x100>; | 250 | reg = <0x70006300 0x100>; |
| 230 | reg-shift = <2>; | 251 | reg-shift = <2>; |
| 231 | interrupts = <0 90 0x04>; | 252 | interrupts = <0 90 0x04>; |
| 253 | clocks = <&tegra_car 65>; | ||
| 232 | status = "disabled"; | 254 | status = "disabled"; |
| 233 | }; | 255 | }; |
| 234 | 256 | ||
| @@ -237,6 +259,7 @@ | |||
| 237 | reg = <0x70006400 0x100>; | 259 | reg = <0x70006400 0x100>; |
| 238 | reg-shift = <2>; | 260 | reg-shift = <2>; |
| 239 | interrupts = <0 91 0x04>; | 261 | interrupts = <0 91 0x04>; |
| 262 | clocks = <&tegra_car 66>; | ||
| 240 | status = "disabled"; | 263 | status = "disabled"; |
| 241 | }; | 264 | }; |
| 242 | 265 | ||
| @@ -244,6 +267,7 @@ | |||
| 244 | compatible = "nvidia,tegra20-pwm"; | 267 | compatible = "nvidia,tegra20-pwm"; |
| 245 | reg = <0x7000a000 0x100>; | 268 | reg = <0x7000a000 0x100>; |
| 246 | #pwm-cells = <2>; | 269 | #pwm-cells = <2>; |
| 270 | clocks = <&tegra_car 17>; | ||
| 247 | }; | 271 | }; |
| 248 | 272 | ||
| 249 | rtc { | 273 | rtc { |
| @@ -258,6 +282,8 @@ | |||
| 258 | interrupts = <0 38 0x04>; | 282 | interrupts = <0 38 0x04>; |
| 259 | #address-cells = <1>; | 283 | #address-cells = <1>; |
| 260 | #size-cells = <0>; | 284 | #size-cells = <0>; |
| 285 | clocks = <&tegra_car 12>, <&tegra_car 124>; | ||
| 286 | clock-names = "div-clk", "fast-clk"; | ||
| 261 | status = "disabled"; | 287 | status = "disabled"; |
| 262 | }; | 288 | }; |
| 263 | 289 | ||
| @@ -268,6 +294,7 @@ | |||
| 268 | nvidia,dma-request-selector = <&apbdma 11>; | 294 | nvidia,dma-request-selector = <&apbdma 11>; |
| 269 | #address-cells = <1>; | 295 | #address-cells = <1>; |
| 270 | #size-cells = <0>; | 296 | #size-cells = <0>; |
| 297 | clocks = <&tegra_car 43>; | ||
| 271 | status = "disabled"; | 298 | status = "disabled"; |
| 272 | }; | 299 | }; |
| 273 | 300 | ||
| @@ -277,6 +304,8 @@ | |||
| 277 | interrupts = <0 84 0x04>; | 304 | interrupts = <0 84 0x04>; |
| 278 | #address-cells = <1>; | 305 | #address-cells = <1>; |
| 279 | #size-cells = <0>; | 306 | #size-cells = <0>; |
| 307 | clocks = <&tegra_car 54>, <&tegra_car 124>; | ||
| 308 | clock-names = "div-clk", "fast-clk"; | ||
| 280 | status = "disabled"; | 309 | status = "disabled"; |
| 281 | }; | 310 | }; |
| 282 | 311 | ||
| @@ -286,6 +315,8 @@ | |||
| 286 | interrupts = <0 92 0x04>; | 315 | interrupts = <0 92 0x04>; |
| 287 | #address-cells = <1>; | 316 | #address-cells = <1>; |
| 288 | #size-cells = <0>; | 317 | #size-cells = <0>; |
| 318 | clocks = <&tegra_car 67>, <&tegra_car 124>; | ||
| 319 | clock-names = "div-clk", "fast-clk"; | ||
| 289 | status = "disabled"; | 320 | status = "disabled"; |
| 290 | }; | 321 | }; |
| 291 | 322 | ||
| @@ -295,6 +326,8 @@ | |||
| 295 | interrupts = <0 53 0x04>; | 326 | interrupts = <0 53 0x04>; |
| 296 | #address-cells = <1>; | 327 | #address-cells = <1>; |
| 297 | #size-cells = <0>; | 328 | #size-cells = <0>; |
| 329 | clocks = <&tegra_car 47>, <&tegra_car 124>; | ||
| 330 | clock-names = "div-clk", "fast-clk"; | ||
| 298 | status = "disabled"; | 331 | status = "disabled"; |
| 299 | }; | 332 | }; |
| 300 | 333 | ||
| @@ -305,6 +338,7 @@ | |||
| 305 | nvidia,dma-request-selector = <&apbdma 15>; | 338 | nvidia,dma-request-selector = <&apbdma 15>; |
| 306 | #address-cells = <1>; | 339 | #address-cells = <1>; |
| 307 | #size-cells = <0>; | 340 | #size-cells = <0>; |
| 341 | clocks = <&tegra_car 41>; | ||
| 308 | status = "disabled"; | 342 | status = "disabled"; |
| 309 | }; | 343 | }; |
| 310 | 344 | ||
| @@ -315,6 +349,7 @@ | |||
| 315 | nvidia,dma-request-selector = <&apbdma 16>; | 349 | nvidia,dma-request-selector = <&apbdma 16>; |
| 316 | #address-cells = <1>; | 350 | #address-cells = <1>; |
| 317 | #size-cells = <0>; | 351 | #size-cells = <0>; |
| 352 | clocks = <&tegra_car 44>; | ||
| 318 | status = "disabled"; | 353 | status = "disabled"; |
| 319 | }; | 354 | }; |
| 320 | 355 | ||
| @@ -325,6 +360,7 @@ | |||
| 325 | nvidia,dma-request-selector = <&apbdma 17>; | 360 | nvidia,dma-request-selector = <&apbdma 17>; |
| 326 | #address-cells = <1>; | 361 | #address-cells = <1>; |
| 327 | #size-cells = <0>; | 362 | #size-cells = <0>; |
| 363 | clocks = <&tegra_car 46>; | ||
| 328 | status = "disabled"; | 364 | status = "disabled"; |
| 329 | }; | 365 | }; |
| 330 | 366 | ||
| @@ -335,6 +371,7 @@ | |||
| 335 | nvidia,dma-request-selector = <&apbdma 18>; | 371 | nvidia,dma-request-selector = <&apbdma 18>; |
| 336 | #address-cells = <1>; | 372 | #address-cells = <1>; |
| 337 | #size-cells = <0>; | 373 | #size-cells = <0>; |
| 374 | clocks = <&tegra_car 68>; | ||
| 338 | status = "disabled"; | 375 | status = "disabled"; |
| 339 | }; | 376 | }; |
| 340 | 377 | ||
| @@ -369,6 +406,7 @@ | |||
| 369 | interrupts = <0 20 0x04>; | 406 | interrupts = <0 20 0x04>; |
| 370 | phy_type = "utmi"; | 407 | phy_type = "utmi"; |
| 371 | nvidia,has-legacy-mode; | 408 | nvidia,has-legacy-mode; |
| 409 | clocks = <&tegra_car 22>; | ||
| 372 | status = "disabled"; | 410 | status = "disabled"; |
| 373 | }; | 411 | }; |
| 374 | 412 | ||
| @@ -377,6 +415,7 @@ | |||
| 377 | reg = <0xc5004000 0x4000>; | 415 | reg = <0xc5004000 0x4000>; |
| 378 | interrupts = <0 21 0x04>; | 416 | interrupts = <0 21 0x04>; |
| 379 | phy_type = "ulpi"; | 417 | phy_type = "ulpi"; |
| 418 | clocks = <&tegra_car 58>; | ||
| 380 | status = "disabled"; | 419 | status = "disabled"; |
| 381 | }; | 420 | }; |
| 382 | 421 | ||
| @@ -385,6 +424,7 @@ | |||
| 385 | reg = <0xc5008000 0x4000>; | 424 | reg = <0xc5008000 0x4000>; |
| 386 | interrupts = <0 97 0x04>; | 425 | interrupts = <0 97 0x04>; |
| 387 | phy_type = "utmi"; | 426 | phy_type = "utmi"; |
| 427 | clocks = <&tegra_car 59>; | ||
| 388 | status = "disabled"; | 428 | status = "disabled"; |
| 389 | }; | 429 | }; |
| 390 | 430 | ||
| @@ -392,6 +432,7 @@ | |||
| 392 | compatible = "nvidia,tegra20-sdhci"; | 432 | compatible = "nvidia,tegra20-sdhci"; |
| 393 | reg = <0xc8000000 0x200>; | 433 | reg = <0xc8000000 0x200>; |
| 394 | interrupts = <0 14 0x04>; | 434 | interrupts = <0 14 0x04>; |
| 435 | clocks = <&tegra_car 14>; | ||
| 395 | status = "disabled"; | 436 | status = "disabled"; |
| 396 | }; | 437 | }; |
| 397 | 438 | ||
| @@ -399,6 +440,7 @@ | |||
| 399 | compatible = "nvidia,tegra20-sdhci"; | 440 | compatible = "nvidia,tegra20-sdhci"; |
| 400 | reg = <0xc8000200 0x200>; | 441 | reg = <0xc8000200 0x200>; |
| 401 | interrupts = <0 15 0x04>; | 442 | interrupts = <0 15 0x04>; |
| 443 | clocks = <&tegra_car 9>; | ||
| 402 | status = "disabled"; | 444 | status = "disabled"; |
| 403 | }; | 445 | }; |
| 404 | 446 | ||
| @@ -406,6 +448,7 @@ | |||
| 406 | compatible = "nvidia,tegra20-sdhci"; | 448 | compatible = "nvidia,tegra20-sdhci"; |
| 407 | reg = <0xc8000400 0x200>; | 449 | reg = <0xc8000400 0x200>; |
| 408 | interrupts = <0 19 0x04>; | 450 | interrupts = <0 19 0x04>; |
| 451 | clocks = <&tegra_car 69>; | ||
| 409 | status = "disabled"; | 452 | status = "disabled"; |
| 410 | }; | 453 | }; |
| 411 | 454 | ||
| @@ -413,6 +456,7 @@ | |||
| 413 | compatible = "nvidia,tegra20-sdhci"; | 456 | compatible = "nvidia,tegra20-sdhci"; |
| 414 | reg = <0xc8000600 0x200>; | 457 | reg = <0xc8000600 0x200>; |
| 415 | interrupts = <0 31 0x04>; | 458 | interrupts = <0 31 0x04>; |
| 459 | clocks = <&tegra_car 15>; | ||
| 416 | status = "disabled"; | 460 | status = "disabled"; |
| 417 | }; | 461 | }; |
| 418 | 462 | ||
