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-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/Kconfig.debug8
-rw-r--r--arch/arm/boot/dts/imx23-evk.dts43
-rw-r--r--arch/arm/boot/dts/imx23.dtsi295
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycore.dts8
-rw-r--r--arch/arm/boot/dts/imx27.dtsi14
-rw-r--r--arch/arm/boot/dts/imx28-evk.dts114
-rw-r--r--arch/arm/boot/dts/imx28.dtsi497
-rw-r--r--arch/arm/boot/dts/imx51-babbage.dts40
-rw-r--r--arch/arm/boot/dts/imx51.dtsi41
-rw-r--r--arch/arm/boot/dts/imx53-ard.dts6
-rw-r--r--arch/arm/boot/dts/imx53-evk.dts8
-rw-r--r--arch/arm/boot/dts/imx53-qsb.dts121
-rw-r--r--arch/arm/boot/dts/imx53-smd.dts12
-rw-r--r--arch/arm/boot/dts/imx53.dtsi45
-rw-r--r--arch/arm/boot/dts/imx6q-arm2.dts13
-rw-r--r--arch/arm/boot/dts/imx6q-sabrelite.dts50
-rw-r--r--arch/arm/boot/dts/imx6q-sabresd.dts53
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi171
-rw-r--r--arch/arm/boot/dts/tegra-cardhu.dts85
-rw-r--r--arch/arm/boot/dts/tegra-harmony.dts104
-rw-r--r--arch/arm/boot/dts/tegra-paz00.dts112
-rw-r--r--arch/arm/boot/dts/tegra-seaboard.dts213
-rw-r--r--arch/arm/boot/dts/tegra-trimslice.dts83
-rw-r--r--arch/arm/boot/dts/tegra-ventana.dts102
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi275
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi292
-rw-r--r--arch/arm/configs/mxs_defconfig1
-rw-r--r--arch/arm/mach-imx/Makefile.boot3
-rw-r--r--arch/arm/mach-imx/clk-imx51-imx53.c40
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c35
-rw-r--r--arch/arm/mach-imx/imx53-dt.c19
-rw-r--r--arch/arm/mach-imx/lluart.c6
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c55
-rw-r--r--arch/arm/mach-imx/mach-mx51_babbage.c6
-rw-r--r--arch/arm/mach-mxs/Kconfig10
-rw-r--r--arch/arm/mach-mxs/Makefile1
-rw-r--r--arch/arm/mach-mxs/devices/Kconfig1
-rw-r--r--arch/arm/mach-mxs/devices/platform-dma.c21
-rw-r--r--arch/arm/mach-mxs/devices/platform-gpio-mxs.c24
-rw-r--r--arch/arm/mach-mxs/devices/platform-mxs-mmc.c21
-rw-r--r--arch/arm/mach-mxs/include/mach/common.h7
-rw-r--r--arch/arm/mach-mxs/include/mach/devices-common.h3
-rw-r--r--arch/arm/mach-mxs/include/mach/mmc.h18
-rw-r--r--arch/arm/mach-mxs/mach-mxs.c121
-rw-r--r--arch/arm/mach-mxs/mm.c16
-rw-r--r--arch/arm/plat-mxc/include/mach/debug-macro.S2
-rw-r--r--arch/arm/plat-mxc/include/mach/mx6q.h2
48 files changed, 2447 insertions, 771 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 515c8c85cbbb..5e7601301b41 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -459,6 +459,7 @@ config ARCH_MXS
459 select COMMON_CLK 459 select COMMON_CLK
460 select HAVE_CLK_PREPARE 460 select HAVE_CLK_PREPARE
461 select PINCTRL 461 select PINCTRL
462 select USE_OF
462 help 463 help
463 Support for Freescale MXS-based family of processors 464 Support for Freescale MXS-based family of processors
464 465
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index e561adc1db0c..01a134141216 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -209,6 +209,14 @@ choice
209 Say Y here if you want kernel low-level debugging support 209 Say Y here if you want kernel low-level debugging support
210 on i.MX50 or i.MX53. 210 on i.MX50 or i.MX53.
211 211
212 config DEBUG_IMX6Q_UART2
213 bool "i.MX6Q Debug UART2"
214 depends on SOC_IMX6Q
215 help
216 Say Y here if you want kernel low-level debugging support
217 on i.MX6Q UART2. This is correct for e.g. the SabreLite
218 board.
219
212 config DEBUG_IMX6Q_UART4 220 config DEBUG_IMX6Q_UART4
213 bool "i.MX6Q Debug UART4" 221 bool "i.MX6Q Debug UART4"
214 depends on SOC_IMX6Q 222 depends on SOC_IMX6Q
diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts
new file mode 100644
index 000000000000..70bffa929b65
--- /dev/null
+++ b/arch/arm/boot/dts/imx23-evk.dts
@@ -0,0 +1,43 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "imx23.dtsi"
14
15/ {
16 model = "Freescale i.MX23 Evaluation Kit";
17 compatible = "fsl,imx23-evk", "fsl,imx23";
18
19 memory {
20 reg = <0x40000000 0x08000000>;
21 };
22
23 apb@80000000 {
24 apbh@80000000 {
25 ssp0: ssp@80010000 {
26 compatible = "fsl,imx23-mmc";
27 pinctrl-names = "default";
28 pinctrl-0 = <&mmc0_8bit_pins_a &mmc0_pins_fixup>;
29 bus-width = <8>;
30 wp-gpios = <&gpio1 30 0>;
31 status = "okay";
32 };
33 };
34
35 apbx@80040000 {
36 duart: serial@80070000 {
37 pinctrl-names = "default";
38 pinctrl-0 = <&duart_pins_a>;
39 status = "okay";
40 };
41 };
42 };
43};
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
new file mode 100644
index 000000000000..8c5f9994f3fc
--- /dev/null
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -0,0 +1,295 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 interrupt-parent = <&icoll>;
16
17 aliases {
18 gpio0 = &gpio0;
19 gpio1 = &gpio1;
20 gpio2 = &gpio2;
21 };
22
23 cpus {
24 cpu@0 {
25 compatible = "arm,arm926ejs";
26 };
27 };
28
29 apb@80000000 {
30 compatible = "simple-bus";
31 #address-cells = <1>;
32 #size-cells = <1>;
33 reg = <0x80000000 0x80000>;
34 ranges;
35
36 apbh@80000000 {
37 compatible = "simple-bus";
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x80000000 0x40000>;
41 ranges;
42
43 icoll: interrupt-controller@80000000 {
44 compatible = "fsl,imx23-icoll", "fsl,mxs-icoll";
45 interrupt-controller;
46 #interrupt-cells = <1>;
47 reg = <0x80000000 0x2000>;
48 };
49
50 dma-apbh@80004000 {
51 compatible = "fsl,imx23-dma-apbh";
52 reg = <0x80004000 2000>;
53 };
54
55 ecc@80008000 {
56 reg = <0x80008000 2000>;
57 status = "disabled";
58 };
59
60 bch@8000a000 {
61 reg = <0x8000a000 2000>;
62 status = "disabled";
63 };
64
65 gpmi@8000c000 {
66 reg = <0x8000c000 2000>;
67 status = "disabled";
68 };
69
70 ssp0: ssp@80010000 {
71 reg = <0x80010000 2000>;
72 interrupts = <15 14>;
73 fsl,ssp-dma-channel = <1>;
74 status = "disabled";
75 };
76
77 etm@80014000 {
78 reg = <0x80014000 2000>;
79 status = "disabled";
80 };
81
82 pinctrl@80018000 {
83 #address-cells = <1>;
84 #size-cells = <0>;
85 compatible = "fsl,imx23-pinctrl", "simple-bus";
86 reg = <0x80018000 2000>;
87
88 gpio0: gpio@0 {
89 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
90 interrupts = <16>;
91 gpio-controller;
92 #gpio-cells = <2>;
93 interrupt-controller;
94 #interrupt-cells = <2>;
95 };
96
97 gpio1: gpio@1 {
98 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
99 interrupts = <17>;
100 gpio-controller;
101 #gpio-cells = <2>;
102 interrupt-controller;
103 #interrupt-cells = <2>;
104 };
105
106 gpio2: gpio@2 {
107 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
108 interrupts = <18>;
109 gpio-controller;
110 #gpio-cells = <2>;
111 interrupt-controller;
112 #interrupt-cells = <2>;
113 };
114
115 duart_pins_a: duart@0 {
116 reg = <0>;
117 fsl,pinmux-ids = <0x11a2 0x11b2>;
118 fsl,drive-strength = <0>;
119 fsl,voltage = <1>;
120 fsl,pull-up = <0>;
121 };
122
123 mmc0_8bit_pins_a: mmc0-8bit@0 {
124 reg = <0>;
125 fsl,pinmux-ids = <0x2020 0x2030 0x2040
126 0x2050 0x0082 0x0092 0x00a2
127 0x00b2 0x2000 0x2010 0x2060>;
128 fsl,drive-strength = <1>;
129 fsl,voltage = <1>;
130 fsl,pull-up = <1>;
131 };
132
133 mmc0_pins_fixup: mmc0-pins-fixup {
134 fsl,pinmux-ids = <0x2010 0x2060>;
135 fsl,pull-up = <0>;
136 };
137 };
138
139 digctl@8001c000 {
140 reg = <0x8001c000 2000>;
141 status = "disabled";
142 };
143
144 emi@80020000 {
145 reg = <0x80020000 2000>;
146 status = "disabled";
147 };
148
149 dma-apbx@80024000 {
150 compatible = "fsl,imx23-dma-apbx";
151 reg = <0x80024000 2000>;
152 };
153
154 dcp@80028000 {
155 reg = <0x80028000 2000>;
156 status = "disabled";
157 };
158
159 pxp@8002a000 {
160 reg = <0x8002a000 2000>;
161 status = "disabled";
162 };
163
164 ocotp@8002c000 {
165 reg = <0x8002c000 2000>;
166 status = "disabled";
167 };
168
169 axi-ahb@8002e000 {
170 reg = <0x8002e000 2000>;
171 status = "disabled";
172 };
173
174 lcdif@80030000 {
175 reg = <0x80030000 2000>;
176 status = "disabled";
177 };
178
179 ssp1: ssp@80034000 {
180 reg = <0x80034000 2000>;
181 interrupts = <2 20>;
182 fsl,ssp-dma-channel = <2>;
183 status = "disabled";
184 };
185
186 tvenc@80038000 {
187 reg = <0x80038000 2000>;
188 status = "disabled";
189 };
190 };
191
192 apbx@80040000 {
193 compatible = "simple-bus";
194 #address-cells = <1>;
195 #size-cells = <1>;
196 reg = <0x80040000 0x40000>;
197 ranges;
198
199 clkctl@80040000 {
200 reg = <0x80040000 2000>;
201 status = "disabled";
202 };
203
204 saif0: saif@80042000 {
205 reg = <0x80042000 2000>;
206 status = "disabled";
207 };
208
209 power@80044000 {
210 reg = <0x80044000 2000>;
211 status = "disabled";
212 };
213
214 saif1: saif@80046000 {
215 reg = <0x80046000 2000>;
216 status = "disabled";
217 };
218
219 audio-out@80048000 {
220 reg = <0x80048000 2000>;
221 status = "disabled";
222 };
223
224 audio-in@8004c000 {
225 reg = <0x8004c000 2000>;
226 status = "disabled";
227 };
228
229 lradc@80050000 {
230 reg = <0x80050000 2000>;
231 status = "disabled";
232 };
233
234 spdif@80054000 {
235 reg = <0x80054000 2000>;
236 status = "disabled";
237 };
238
239 i2c@80058000 {
240 reg = <0x80058000 2000>;
241 status = "disabled";
242 };
243
244 rtc@8005c000 {
245 reg = <0x8005c000 2000>;
246 status = "disabled";
247 };
248
249 pwm@80064000 {
250 reg = <0x80064000 2000>;
251 status = "disabled";
252 };
253
254 timrot@80068000 {
255 reg = <0x80068000 2000>;
256 status = "disabled";
257 };
258
259 auart0: serial@8006c000 {
260 reg = <0x8006c000 0x2000>;
261 status = "disabled";
262 };
263
264 auart1: serial@8006e000 {
265 reg = <0x8006e000 0x2000>;
266 status = "disabled";
267 };
268
269 duart: serial@80070000 {
270 compatible = "arm,pl011", "arm,primecell";
271 reg = <0x80070000 0x2000>;
272 interrupts = <0>;
273 status = "disabled";
274 };
275
276 usbphy@8007c000 {
277 reg = <0x8007c000 0x2000>;
278 status = "disabled";
279 };
280 };
281 };
282
283 ahb@80080000 {
284 compatible = "simple-bus";
285 #address-cells = <1>;
286 #size-cells = <1>;
287 reg = <0x80080000 0x80000>;
288 ranges;
289
290 usbctrl@80080000 {
291 reg = <0x80080000 0x10000>;
292 status = "disabled";
293 };
294 };
295};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts
index a51a08fc2af9..2b0ff60247a4 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore.dts
@@ -27,22 +27,22 @@
27 status = "okay"; 27 status = "okay";
28 }; 28 };
29 29
30 uart@1000a000 { 30 serial@1000a000 {
31 fsl,uart-has-rtscts; 31 fsl,uart-has-rtscts;
32 status = "okay"; 32 status = "okay";
33 }; 33 };
34 34
35 uart@1000b000 { 35 serial@1000b000 {
36 fsl,uart-has-rtscts; 36 fsl,uart-has-rtscts;
37 status = "okay"; 37 status = "okay";
38 }; 38 };
39 39
40 uart@1000c000 { 40 serial@1000c000 {
41 fsl,uart-has-rtscts; 41 fsl,uart-has-rtscts;
42 status = "okay"; 42 status = "okay";
43 }; 43 };
44 44
45 fec@1002b000 { 45 ethernet@1002b000 {
46 status = "okay"; 46 status = "okay";
47 }; 47 };
48 48
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index bc5e7d5ddd54..2b1a166d41f9 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -59,28 +59,28 @@
59 status = "disabled"; 59 status = "disabled";
60 }; 60 };
61 61
62 uart1: uart@1000a000 { 62 uart1: serial@1000a000 {
63 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 63 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
64 reg = <0x1000a000 0x1000>; 64 reg = <0x1000a000 0x1000>;
65 interrupts = <20>; 65 interrupts = <20>;
66 status = "disabled"; 66 status = "disabled";
67 }; 67 };
68 68
69 uart2: uart@1000b000 { 69 uart2: serial@1000b000 {
70 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 70 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
71 reg = <0x1000b000 0x1000>; 71 reg = <0x1000b000 0x1000>;
72 interrupts = <19>; 72 interrupts = <19>;
73 status = "disabled"; 73 status = "disabled";
74 }; 74 };
75 75
76 uart3: uart@1000c000 { 76 uart3: serial@1000c000 {
77 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 77 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
78 reg = <0x1000c000 0x1000>; 78 reg = <0x1000c000 0x1000>;
79 interrupts = <18>; 79 interrupts = <18>;
80 status = "disabled"; 80 status = "disabled";
81 }; 81 };
82 82
83 uart4: uart@1000d000 { 83 uart4: serial@1000d000 {
84 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 84 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
85 reg = <0x1000d000 0x1000>; 85 reg = <0x1000d000 0x1000>;
86 interrupts = <17>; 86 interrupts = <17>;
@@ -183,14 +183,14 @@
183 status = "disabled"; 183 status = "disabled";
184 }; 184 };
185 185
186 uart5: uart@1001b000 { 186 uart5: serial@1001b000 {
187 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 187 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
188 reg = <0x1001b000 0x1000>; 188 reg = <0x1001b000 0x1000>;
189 interrupts = <49>; 189 interrupts = <49>;
190 status = "disabled"; 190 status = "disabled";
191 }; 191 };
192 192
193 uart6: uart@1001c000 { 193 uart6: serial@1001c000 {
194 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 194 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
195 reg = <0x1001c000 0x1000>; 195 reg = <0x1001c000 0x1000>;
196 interrupts = <48>; 196 interrupts = <48>;
@@ -206,7 +206,7 @@
206 status = "disabled"; 206 status = "disabled";
207 }; 207 };
208 208
209 fec: fec@1002b000 { 209 fec: ethernet@1002b000 {
210 compatible = "fsl,imx27-fec"; 210 compatible = "fsl,imx27-fec";
211 reg = <0x1002b000 0x4000>; 211 reg = <0x1002b000 0x4000>;
212 interrupts = <50>; 212 interrupts = <50>;
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
new file mode 100644
index 000000000000..ee520a529cb4
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -0,0 +1,114 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "imx28.dtsi"
14
15/ {
16 model = "Freescale i.MX28 Evaluation Kit";
17 compatible = "fsl,imx28-evk", "fsl,imx28";
18
19 memory {
20 reg = <0x40000000 0x08000000>;
21 };
22
23 apb@80000000 {
24 apbh@80000000 {
25 ssp0: ssp@80010000 {
26 compatible = "fsl,imx28-mmc";
27 pinctrl-names = "default";
28 pinctrl-0 = <&mmc0_8bit_pins_a
29 &mmc0_cd_cfg &mmc0_sck_cfg>;
30 bus-width = <8>;
31 wp-gpios = <&gpio2 12 0>;
32 status = "okay";
33 };
34
35 ssp1: ssp@80012000 {
36 compatible = "fsl,imx28-mmc";
37 bus-width = <8>;
38 wp-gpios = <&gpio0 28 0>;
39 status = "okay";
40 };
41 };
42
43 apbx@80040000 {
44 saif0: saif@80042000 {
45 pinctrl-names = "default";
46 pinctrl-0 = <&saif0_pins_a>;
47 status = "okay";
48 };
49
50 saif1: saif@80046000 {
51 pinctrl-names = "default";
52 pinctrl-0 = <&saif1_pins_a>;
53 fsl,saif-master = <&saif0>;
54 status = "okay";
55 };
56
57 i2c0: i2c@80058000 {
58 pinctrl-names = "default";
59 pinctrl-0 = <&i2c0_pins_a>;
60 status = "okay";
61
62 sgtl5000: codec@0a {
63 compatible = "fsl,sgtl5000";
64 reg = <0x0a>;
65 VDDA-supply = <&reg_3p3v>;
66 VDDIO-supply = <&reg_3p3v>;
67
68 };
69 };
70
71 duart: serial@80074000 {
72 pinctrl-names = "default";
73 pinctrl-0 = <&duart_pins_a>;
74 status = "okay";
75 };
76 };
77 };
78
79 ahb@80080000 {
80 mac0: ethernet@800f0000 {
81 phy-mode = "rmii";
82 pinctrl-names = "default";
83 pinctrl-0 = <&mac0_pins_a>;
84 status = "okay";
85 };
86
87 mac1: ethernet@800f4000 {
88 phy-mode = "rmii";
89 pinctrl-names = "default";
90 pinctrl-0 = <&mac1_pins_a>;
91 status = "okay";
92 };
93 };
94
95 regulators {
96 compatible = "simple-bus";
97
98 reg_3p3v: 3p3v {
99 compatible = "regulator-fixed";
100 regulator-name = "3P3V";
101 regulator-min-microvolt = <3300000>;
102 regulator-max-microvolt = <3300000>;
103 regulator-always-on;
104 };
105 };
106
107 sound {
108 compatible = "fsl,imx28-evk-sgtl5000",
109 "fsl,mxs-audio-sgtl5000";
110 model = "imx28-evk-sgtl5000";
111 saif-controllers = <&saif0 &saif1>;
112 audio-codec = <&sgtl5000>;
113 };
114};
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
new file mode 100644
index 000000000000..4634cb861a59
--- /dev/null
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -0,0 +1,497 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 interrupt-parent = <&icoll>;
16
17 aliases {
18 gpio0 = &gpio0;
19 gpio1 = &gpio1;
20 gpio2 = &gpio2;
21 gpio3 = &gpio3;
22 gpio4 = &gpio4;
23 saif0 = &saif0;
24 saif1 = &saif1;
25 };
26
27 cpus {
28 cpu@0 {
29 compatible = "arm,arm926ejs";
30 };
31 };
32
33 apb@80000000 {
34 compatible = "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <1>;
37 reg = <0x80000000 0x80000>;
38 ranges;
39
40 apbh@80000000 {
41 compatible = "simple-bus";
42 #address-cells = <1>;
43 #size-cells = <1>;
44 reg = <0x80000000 0x3c900>;
45 ranges;
46
47 icoll: interrupt-controller@80000000 {
48 compatible = "fsl,imx28-icoll", "fsl,mxs-icoll";
49 interrupt-controller;
50 #interrupt-cells = <1>;
51 reg = <0x80000000 0x2000>;
52 };
53
54 hsadc@80002000 {
55 reg = <0x80002000 2000>;
56 interrupts = <13 87>;
57 status = "disabled";
58 };
59
60 dma-apbh@80004000 {
61 compatible = "fsl,imx28-dma-apbh";
62 reg = <0x80004000 2000>;
63 };
64
65 perfmon@80006000 {
66 reg = <0x80006000 800>;
67 interrupts = <27>;
68 status = "disabled";
69 };
70
71 bch@8000a000 {
72 reg = <0x8000a000 2000>;
73 interrupts = <41>;
74 status = "disabled";
75 };
76
77 gpmi@8000c000 {
78 reg = <0x8000c000 2000>;
79 interrupts = <42 88>;
80 status = "disabled";
81 };
82
83 ssp0: ssp@80010000 {
84 reg = <0x80010000 2000>;
85 interrupts = <96 82>;
86 fsl,ssp-dma-channel = <0>;
87 status = "disabled";
88 };
89
90 ssp1: ssp@80012000 {
91 reg = <0x80012000 2000>;
92 interrupts = <97 83>;
93 fsl,ssp-dma-channel = <1>;
94 status = "disabled";
95 };
96
97 ssp2: ssp@80014000 {
98 reg = <0x80014000 2000>;
99 interrupts = <98 84>;
100 fsl,ssp-dma-channel = <2>;
101 status = "disabled";
102 };
103
104 ssp3: ssp@80016000 {
105 reg = <0x80016000 2000>;
106 interrupts = <99 85>;
107 fsl,ssp-dma-channel = <3>;
108 status = "disabled";
109 };
110
111 pinctrl@80018000 {
112 #address-cells = <1>;
113 #size-cells = <0>;
114 compatible = "fsl,imx28-pinctrl", "simple-bus";
115 reg = <0x80018000 2000>;
116
117 gpio0: gpio@0 {
118 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
119 interrupts = <127>;
120 gpio-controller;
121 #gpio-cells = <2>;
122 interrupt-controller;
123 #interrupt-cells = <2>;
124 };
125
126 gpio1: gpio@1 {
127 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
128 interrupts = <126>;
129 gpio-controller;
130 #gpio-cells = <2>;
131 interrupt-controller;
132 #interrupt-cells = <2>;
133 };
134
135 gpio2: gpio@2 {
136 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
137 interrupts = <125>;
138 gpio-controller;
139 #gpio-cells = <2>;
140 interrupt-controller;
141 #interrupt-cells = <2>;
142 };
143
144 gpio3: gpio@3 {
145 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
146 interrupts = <124>;
147 gpio-controller;
148 #gpio-cells = <2>;
149 interrupt-controller;
150 #interrupt-cells = <2>;
151 };
152
153 gpio4: gpio@4 {
154 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
155 interrupts = <123>;
156 gpio-controller;
157 #gpio-cells = <2>;
158 interrupt-controller;
159 #interrupt-cells = <2>;
160 };
161
162 duart_pins_a: duart@0 {
163 reg = <0>;
164 fsl,pinmux-ids = <0x3102 0x3112>;
165 fsl,drive-strength = <0>;
166 fsl,voltage = <1>;
167 fsl,pull-up = <0>;
168 };
169
170 mac0_pins_a: mac0@0 {
171 reg = <0>;
172 fsl,pinmux-ids = <0x4000 0x4010 0x4020
173 0x4030 0x4040 0x4060 0x4070
174 0x4080 0x4100>;
175 fsl,drive-strength = <1>;
176 fsl,voltage = <1>;
177 fsl,pull-up = <1>;
178 };
179
180 mac1_pins_a: mac1@0 {
181 reg = <0>;
182 fsl,pinmux-ids = <0x40f1 0x4091 0x40a1
183 0x40e1 0x40b1 0x40c1>;
184 fsl,drive-strength = <1>;
185 fsl,voltage = <1>;
186 fsl,pull-up = <1>;
187 };
188
189 mmc0_8bit_pins_a: mmc0-8bit@0 {
190 reg = <0>;
191 fsl,pinmux-ids = <0x2000 0x2010 0x2020
192 0x2030 0x2040 0x2050 0x2060
193 0x2070 0x2080 0x2090 0x20a0>;
194 fsl,drive-strength = <1>;
195 fsl,voltage = <1>;
196 fsl,pull-up = <1>;
197 };
198
199 mmc0_cd_cfg: mmc0-cd-cfg {
200 fsl,pinmux-ids = <0x2090>;
201 fsl,pull-up = <0>;
202 };
203
204 mmc0_sck_cfg: mmc0-sck-cfg {
205 fsl,pinmux-ids = <0x20a0>;
206 fsl,drive-strength = <2>;
207 fsl,pull-up = <0>;
208 };
209
210 i2c0_pins_a: i2c0@0 {
211 reg = <0>;
212 fsl,pinmux-ids = <0x3180 0x3190>;
213 fsl,drive-strength = <1>;
214 fsl,voltage = <1>;
215 fsl,pull-up = <1>;
216 };
217
218 saif0_pins_a: saif0@0 {
219 reg = <0>;
220 fsl,pinmux-ids =
221 <0x3140 0x3150 0x3160 0x3170>;
222 fsl,drive-strength = <2>;
223 fsl,voltage = <1>;
224 fsl,pull-up = <1>;
225 };
226
227 saif1_pins_a: saif1@0 {
228 reg = <0>;
229 fsl,pinmux-ids = <0x31a0>;
230 fsl,drive-strength = <2>;
231 fsl,voltage = <1>;
232 fsl,pull-up = <1>;
233 };
234 };
235
236 digctl@8001c000 {
237 reg = <0x8001c000 2000>;
238 interrupts = <89>;
239 status = "disabled";
240 };
241
242 etm@80022000 {
243 reg = <0x80022000 2000>;
244 status = "disabled";
245 };
246
247 dma-apbx@80024000 {
248 compatible = "fsl,imx28-dma-apbx";
249 reg = <0x80024000 2000>;
250 };
251
252 dcp@80028000 {
253 reg = <0x80028000 2000>;
254 interrupts = <52 53 54>;
255 status = "disabled";
256 };
257
258 pxp@8002a000 {
259 reg = <0x8002a000 2000>;
260 interrupts = <39>;
261 status = "disabled";
262 };
263
264 ocotp@8002c000 {
265 reg = <0x8002c000 2000>;
266 status = "disabled";
267 };
268
269 axi-ahb@8002e000 {
270 reg = <0x8002e000 2000>;
271 status = "disabled";
272 };
273
274 lcdif@80030000 {
275 reg = <0x80030000 2000>;
276 interrupts = <38 86>;
277 status = "disabled";
278 };
279
280 can0: can@80032000 {
281 reg = <0x80032000 2000>;
282 interrupts = <8>;
283 status = "disabled";
284 };
285
286 can1: can@80034000 {
287 reg = <0x80034000 2000>;
288 interrupts = <9>;
289 status = "disabled";
290 };
291
292 simdbg@8003c000 {
293 reg = <0x8003c000 200>;
294 status = "disabled";
295 };
296
297 simgpmisel@8003c200 {
298 reg = <0x8003c200 100>;
299 status = "disabled";
300 };
301
302 simsspsel@8003c300 {
303 reg = <0x8003c300 100>;
304 status = "disabled";
305 };
306
307 simmemsel@8003c400 {
308 reg = <0x8003c400 100>;
309 status = "disabled";
310 };
311
312 gpiomon@8003c500 {
313 reg = <0x8003c500 100>;
314 status = "disabled";
315 };
316
317 simenet@8003c700 {
318 reg = <0x8003c700 100>;
319 status = "disabled";
320 };
321
322 armjtag@8003c800 {
323 reg = <0x8003c800 100>;
324 status = "disabled";
325 };
326 };
327
328 apbx@80040000 {
329 compatible = "simple-bus";
330 #address-cells = <1>;
331 #size-cells = <1>;
332 reg = <0x80040000 0x40000>;
333 ranges;
334
335 clkctl@80040000 {
336 reg = <0x80040000 2000>;
337 status = "disabled";
338 };
339
340 saif0: saif@80042000 {
341 compatible = "fsl,imx28-saif";
342 reg = <0x80042000 2000>;
343 interrupts = <59 80>;
344 fsl,saif-dma-channel = <4>;
345 status = "disabled";
346 };
347
348 power@80044000 {
349 reg = <0x80044000 2000>;
350 status = "disabled";
351 };
352
353 saif1: saif@80046000 {
354 compatible = "fsl,imx28-saif";
355 reg = <0x80046000 2000>;
356 interrupts = <58 81>;
357 fsl,saif-dma-channel = <5>;
358 status = "disabled";
359 };
360
361 lradc@80050000 {
362 reg = <0x80050000 2000>;
363 status = "disabled";
364 };
365
366 spdif@80054000 {
367 reg = <0x80054000 2000>;
368 interrupts = <45 66>;
369 status = "disabled";
370 };
371
372 rtc@80056000 {
373 reg = <0x80056000 2000>;
374 interrupts = <28 29>;
375 status = "disabled";
376 };
377
378 i2c0: i2c@80058000 {
379 #address-cells = <1>;
380 #size-cells = <0>;
381 compatible = "fsl,imx28-i2c";
382 reg = <0x80058000 2000>;
383 interrupts = <111 68>;
384 status = "disabled";
385 };
386
387 i2c1: i2c@8005a000 {
388 #address-cells = <1>;
389 #size-cells = <0>;
390 compatible = "fsl,imx28-i2c";
391 reg = <0x8005a000 2000>;
392 interrupts = <110 69>;
393 status = "disabled";
394 };
395
396 pwm@80064000 {
397 reg = <0x80064000 2000>;
398 status = "disabled";
399 };
400
401 timrot@80068000 {
402 reg = <0x80068000 2000>;
403 status = "disabled";
404 };
405
406 auart0: serial@8006a000 {
407 reg = <0x8006a000 0x2000>;
408 interrupts = <112 70 71>;
409 status = "disabled";
410 };
411
412 auart1: serial@8006c000 {
413 reg = <0x8006c000 0x2000>;
414 interrupts = <113 72 73>;
415 status = "disabled";
416 };
417
418 auart2: serial@8006e000 {
419 reg = <0x8006e000 0x2000>;
420 interrupts = <114 74 75>;
421 status = "disabled";
422 };
423
424 auart3: serial@80070000 {
425 reg = <0x80070000 0x2000>;
426 interrupts = <115 76 77>;
427 status = "disabled";
428 };
429
430 auart4: serial@80072000 {
431 reg = <0x80072000 0x2000>;
432 interrupts = <116 78 79>;
433 status = "disabled";
434 };
435
436 duart: serial@80074000 {
437 compatible = "arm,pl011", "arm,primecell";
438 reg = <0x80074000 0x1000>;
439 interrupts = <47>;
440 status = "disabled";
441 };
442
443 usbphy0: usbphy@8007c000 {
444 reg = <0x8007c000 0x2000>;
445 status = "disabled";
446 };
447
448 usbphy1: usbphy@8007e000 {
449 reg = <0x8007e000 0x2000>;
450 status = "disabled";
451 };
452 };
453 };
454
455 ahb@80080000 {
456 compatible = "simple-bus";
457 #address-cells = <1>;
458 #size-cells = <1>;
459 reg = <0x80080000 0x80000>;
460 ranges;
461
462 usbctrl0: usbctrl@80080000 {
463 reg = <0x80080000 0x10000>;
464 status = "disabled";
465 };
466
467 usbctrl1: usbctrl@80090000 {
468 reg = <0x80090000 0x10000>;
469 status = "disabled";
470 };
471
472 dflpt@800c0000 {
473 reg = <0x800c0000 0x10000>;
474 status = "disabled";
475 };
476
477 mac0: ethernet@800f0000 {
478 compatible = "fsl,imx28-fec";
479 reg = <0x800f0000 0x4000>;
480 interrupts = <101>;
481 status = "disabled";
482 };
483
484 mac1: ethernet@800f4000 {
485 compatible = "fsl,imx28-fec";
486 reg = <0x800f4000 0x4000>;
487 interrupts = <102>;
488 status = "disabled";
489 };
490
491 switch@800f8000 {
492 reg = <0x800f8000 0x8000>;
493 status = "disabled";
494 };
495
496 };
497};
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 9949e6060dee..de065b5976e6 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -17,10 +17,6 @@
17 model = "Freescale i.MX51 Babbage Board"; 17 model = "Freescale i.MX51 Babbage Board";
18 compatible = "fsl,imx51-babbage", "fsl,imx51"; 18 compatible = "fsl,imx51-babbage", "fsl,imx51";
19 19
20 chosen {
21 bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
22 };
23
24 memory { 20 memory {
25 reg = <0x90000000 0x20000000>; 21 reg = <0x90000000 0x20000000>;
26 }; 22 };
@@ -40,7 +36,7 @@
40 status = "okay"; 36 status = "okay";
41 }; 37 };
42 38
43 uart3: uart@7000c000 { 39 uart3: serial@7000c000 {
44 fsl,uart-has-rtscts; 40 fsl,uart-has-rtscts;
45 status = "okay"; 41 status = "okay";
46 }; 42 };
@@ -166,6 +162,11 @@
166 }; 162 };
167 }; 163 };
168 }; 164 };
165
166 ssi2: ssi@70014000 {
167 fsl,mode = "i2s-slave";
168 status = "okay";
169 };
169 }; 170 };
170 171
171 wdog@73f98000 { /* WDOG1 */ 172 wdog@73f98000 { /* WDOG1 */
@@ -177,12 +178,12 @@
177 reg = <0x73fa8000 0x4000>; 178 reg = <0x73fa8000 0x4000>;
178 }; 179 };
179 180
180 uart1: uart@73fbc000 { 181 uart1: serial@73fbc000 {
181 fsl,uart-has-rtscts; 182 fsl,uart-has-rtscts;
182 status = "okay"; 183 status = "okay";
183 }; 184 };
184 185
185 uart2: uart@73fc0000 { 186 uart2: serial@73fc0000 {
186 status = "okay"; 187 status = "okay";
187 }; 188 };
188 }; 189 };
@@ -195,13 +196,20 @@
195 i2c@83fc4000 { /* I2C2 */ 196 i2c@83fc4000 { /* I2C2 */
196 status = "okay"; 197 status = "okay";
197 198
198 codec: sgtl5000@0a { 199 sgtl5000: codec@0a {
199 compatible = "fsl,sgtl5000"; 200 compatible = "fsl,sgtl5000";
200 reg = <0x0a>; 201 reg = <0x0a>;
202 clock-frequency = <26000000>;
203 VDDA-supply = <&vdig_reg>;
204 VDDIO-supply = <&vvideo_reg>;
201 }; 205 };
202 }; 206 };
203 207
204 fec@83fec000 { 208 audmux@83fd0000 {
209 status = "okay";
210 };
211
212 ethernet@83fec000 {
205 phy-mode = "mii"; 213 phy-mode = "mii";
206 status = "okay"; 214 status = "okay";
207 }; 215 };
@@ -218,4 +226,18 @@
218 gpio-key,wakeup; 226 gpio-key,wakeup;
219 }; 227 };
220 }; 228 };
229
230 sound {
231 compatible = "fsl,imx51-babbage-sgtl5000",
232 "fsl,imx-audio-sgtl5000";
233 model = "imx51-babbage-sgtl5000";
234 ssi-controller = <&ssi2>;
235 audio-codec = <&sgtl5000>;
236 audio-routing =
237 "MIC_IN", "Mic Jack",
238 "Mic Jack", "Mic Bias",
239 "Headphone Jack", "HP_OUT";
240 mux-int-port = <2>;
241 mux-ext-port = <3>;
242 };
221}; 243};
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 6663986fe1c8..bfa65abe8ef2 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -86,7 +86,7 @@
86 status = "disabled"; 86 status = "disabled";
87 }; 87 };
88 88
89 uart3: uart@7000c000 { 89 uart3: serial@7000c000 {
90 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 90 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
91 reg = <0x7000c000 0x4000>; 91 reg = <0x7000c000 0x4000>;
92 interrupts = <33>; 92 interrupts = <33>;
@@ -102,6 +102,15 @@
102 status = "disabled"; 102 status = "disabled";
103 }; 103 };
104 104
105 ssi2: ssi@70014000 {
106 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
107 reg = <0x70014000 0x4000>;
108 interrupts = <30>;
109 fsl,fifo-depth = <15>;
110 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
111 status = "disabled";
112 };
113
105 esdhc@70020000 { /* ESDHC3 */ 114 esdhc@70020000 { /* ESDHC3 */
106 compatible = "fsl,imx51-esdhc"; 115 compatible = "fsl,imx51-esdhc";
107 reg = <0x70020000 0x4000>; 116 reg = <0x70020000 0x4000>;
@@ -171,14 +180,14 @@
171 status = "disabled"; 180 status = "disabled";
172 }; 181 };
173 182
174 uart1: uart@73fbc000 { 183 uart1: serial@73fbc000 {
175 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 184 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
176 reg = <0x73fbc000 0x4000>; 185 reg = <0x73fbc000 0x4000>;
177 interrupts = <31>; 186 interrupts = <31>;
178 status = "disabled"; 187 status = "disabled";
179 }; 188 };
180 189
181 uart2: uart@73fc0000 { 190 uart2: serial@73fc0000 {
182 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 191 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
183 reg = <0x73fc0000 0x4000>; 192 reg = <0x73fc0000 0x4000>;
184 interrupts = <32>; 193 interrupts = <32>;
@@ -235,7 +244,31 @@
235 status = "disabled"; 244 status = "disabled";
236 }; 245 };
237 246
238 fec@83fec000 { 247 ssi1: ssi@83fcc000 {
248 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
249 reg = <0x83fcc000 0x4000>;
250 interrupts = <29>;
251 fsl,fifo-depth = <15>;
252 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
253 status = "disabled";
254 };
255
256 audmux@83fd0000 {
257 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
258 reg = <0x83fd0000 0x4000>;
259 status = "disabled";
260 };
261
262 ssi3: ssi@83fe8000 {
263 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
264 reg = <0x83fe8000 0x4000>;
265 interrupts = <96>;
266 fsl,fifo-depth = <15>;
267 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
268 status = "disabled";
269 };
270
271 ethernet@83fec000 {
239 compatible = "fsl,imx51-fec", "fsl,imx27-fec"; 272 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
240 reg = <0x83fec000 0x4000>; 273 reg = <0x83fec000 0x4000>;
241 interrupts = <87>; 274 interrupts = <87>;
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index 2dccce46ed81..5b8eafcdbeec 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -17,10 +17,6 @@
17 model = "Freescale i.MX53 Automotive Reference Design Board"; 17 model = "Freescale i.MX53 Automotive Reference Design Board";
18 compatible = "fsl,imx53-ard", "fsl,imx53"; 18 compatible = "fsl,imx53-ard", "fsl,imx53";
19 19
20 chosen {
21 bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
22 };
23
24 memory { 20 memory {
25 reg = <0x70000000 0x40000000>; 21 reg = <0x70000000 0x40000000>;
26 }; 22 };
@@ -44,7 +40,7 @@
44 reg = <0x53fa8000 0x4000>; 40 reg = <0x53fa8000 0x4000>;
45 }; 41 };
46 42
47 uart1: uart@53fbc000 { 43 uart1: serial@53fbc000 {
48 status = "okay"; 44 status = "okay";
49 }; 45 };
50 }; 46 };
diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts
index 5bac4aa4800b..9c798034675e 100644
--- a/arch/arm/boot/dts/imx53-evk.dts
+++ b/arch/arm/boot/dts/imx53-evk.dts
@@ -17,10 +17,6 @@
17 model = "Freescale i.MX53 Evaluation Kit"; 17 model = "Freescale i.MX53 Evaluation Kit";
18 compatible = "fsl,imx53-evk", "fsl,imx53"; 18 compatible = "fsl,imx53-evk", "fsl,imx53";
19 19
20 chosen {
21 bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
22 };
23
24 memory { 20 memory {
25 reg = <0x70000000 0x80000000>; 21 reg = <0x70000000 0x80000000>;
26 }; 22 };
@@ -75,7 +71,7 @@
75 reg = <0x53fa8000 0x4000>; 71 reg = <0x53fa8000 0x4000>;
76 }; 72 };
77 73
78 uart1: uart@53fbc000 { 74 uart1: serial@53fbc000 {
79 status = "okay"; 75 status = "okay";
80 }; 76 };
81 }; 77 };
@@ -99,7 +95,7 @@
99 }; 95 };
100 }; 96 };
101 97
102 fec@63fec000 { 98 ethernet@63fec000 {
103 phy-mode = "rmii"; 99 phy-mode = "rmii";
104 phy-reset-gpios = <&gpio7 6 0>; 100 phy-reset-gpios = <&gpio7 6 0>;
105 status = "okay"; 101 status = "okay";
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index 5c57c8672c36..2d803a9a6949 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -17,10 +17,6 @@
17 model = "Freescale i.MX53 Quick Start Board"; 17 model = "Freescale i.MX53 Quick Start Board";
18 compatible = "fsl,imx53-qsb", "fsl,imx53"; 18 compatible = "fsl,imx53-qsb", "fsl,imx53";
19 19
20 chosen {
21 bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
22 };
23
24 memory { 20 memory {
25 reg = <0x70000000 0x40000000>; 21 reg = <0x70000000 0x40000000>;
26 }; 22 };
@@ -33,6 +29,11 @@
33 status = "okay"; 29 status = "okay";
34 }; 30 };
35 31
32 ssi2: ssi@50014000 {
33 fsl,mode = "i2s-slave";
34 status = "okay";
35 };
36
36 esdhc@50020000 { /* ESDHC3 */ 37 esdhc@50020000 { /* ESDHC3 */
37 cd-gpios = <&gpio3 11 0>; 38 cd-gpios = <&gpio3 11 0>;
38 wp-gpios = <&gpio3 12 0>; 39 wp-gpios = <&gpio3 12 0>;
@@ -49,7 +50,7 @@
49 reg = <0x53fa8000 0x4000>; 50 reg = <0x53fa8000 0x4000>;
50 }; 51 };
51 52
52 uart1: uart@53fbc000 { 53 uart1: serial@53fbc000 {
53 status = "okay"; 54 status = "okay";
54 }; 55 };
55 }; 56 };
@@ -62,9 +63,11 @@
62 i2c@63fc4000 { /* I2C2 */ 63 i2c@63fc4000 { /* I2C2 */
63 status = "okay"; 64 status = "okay";
64 65
65 codec: sgtl5000@0a { 66 sgtl5000: codec@0a {
66 compatible = "fsl,sgtl5000"; 67 compatible = "fsl,sgtl5000";
67 reg = <0x0a>; 68 reg = <0x0a>;
69 VDDA-supply = <&reg_3p2v>;
70 VDDIO-supply = <&reg_3p2v>;
68 }; 71 };
69 }; 72 };
70 73
@@ -77,12 +80,88 @@
77 }; 80 };
78 81
79 pmic: dialog@48 { 82 pmic: dialog@48 {
80 compatible = "dialog,da9053", "dialog,da9052"; 83 compatible = "dlg,da9053-aa", "dlg,da9052";
81 reg = <0x48>; 84 reg = <0x48>;
85
86 regulators {
87 buck0 {
88 regulator-min-microvolt = <500000>;
89 regulator-max-microvolt = <2075000>;
90 };
91
92 buck1 {
93 regulator-min-microvolt = <500000>;
94 regulator-max-microvolt = <2075000>;
95 };
96
97 buck2 {
98 regulator-min-microvolt = <925000>;
99 regulator-max-microvolt = <2500000>;
100 };
101
102 buck3 {
103 regulator-min-microvolt = <925000>;
104 regulator-max-microvolt = <2500000>;
105 };
106
107 ldo4 {
108 regulator-min-microvolt = <600000>;
109 regulator-max-microvolt = <1800000>;
110 };
111
112 ldo5 {
113 regulator-min-microvolt = <600000>;
114 regulator-max-microvolt = <1800000>;
115 };
116
117 ldo6 {
118 regulator-min-microvolt = <1725000>;
119 regulator-max-microvolt = <3300000>;
120 };
121
122 ldo7 {
123 regulator-min-microvolt = <1725000>;
124 regulator-max-microvolt = <3300000>;
125 };
126
127 ldo8 {
128 regulator-min-microvolt = <1200000>;
129 regulator-max-microvolt = <3600000>;
130 };
131
132 ldo9 {
133 regulator-min-microvolt = <1200000>;
134 regulator-max-microvolt = <3600000>;
135 };
136
137 ldo10 {
138 regulator-min-microvolt = <1200000>;
139 regulator-max-microvolt = <3600000>;
140 };
141
142 ldo11 {
143 regulator-min-microvolt = <1200000>;
144 regulator-max-microvolt = <3600000>;
145 };
146
147 ldo12 {
148 regulator-min-microvolt = <1250000>;
149 regulator-max-microvolt = <3650000>;
150 };
151
152 ldo13 {
153 regulator-min-microvolt = <1200000>;
154 regulator-max-microvolt = <3600000>;
155 };
156 };
82 }; 157 };
83 }; 158 };
84 159
85 fec@63fec000 { 160 audmux@63fd0000 {
161 status = "okay";
162 };
163
164 ethernet@63fec000 {
86 phy-mode = "rmii"; 165 phy-mode = "rmii";
87 phy-reset-gpios = <&gpio7 6 0>; 166 phy-reset-gpios = <&gpio7 6 0>;
88 status = "okay"; 167 status = "okay";
@@ -122,4 +201,30 @@
122 linux,default-trigger = "heartbeat"; 201 linux,default-trigger = "heartbeat";
123 }; 202 };
124 }; 203 };
204
205 regulators {
206 compatible = "simple-bus";
207
208 reg_3p2v: 3p2v {
209 compatible = "regulator-fixed";
210 regulator-name = "3P2V";
211 regulator-min-microvolt = <3200000>;
212 regulator-max-microvolt = <3200000>;
213 regulator-always-on;
214 };
215 };
216
217 sound {
218 compatible = "fsl,imx53-qsb-sgtl5000",
219 "fsl,imx-audio-sgtl5000";
220 model = "imx53-qsb-sgtl5000";
221 ssi-controller = <&ssi2>;
222 audio-codec = <&sgtl5000>;
223 audio-routing =
224 "MIC_IN", "Mic Jack",
225 "Mic Jack", "Mic Bias",
226 "Headphone Jack", "HP_OUT";
227 mux-int-port = <2>;
228 mux-ext-port = <5>;
229 };
125}; 230};
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index 139138a556b0..08091029168e 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -17,10 +17,6 @@
17 model = "Freescale i.MX53 Smart Mobile Reference Design Board"; 17 model = "Freescale i.MX53 Smart Mobile Reference Design Board";
18 compatible = "fsl,imx53-smd", "fsl,imx53"; 18 compatible = "fsl,imx53-smd", "fsl,imx53";
19 19
20 chosen {
21 bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
22 };
23
24 memory { 20 memory {
25 reg = <0x70000000 0x40000000>; 21 reg = <0x70000000 0x40000000>;
26 }; 22 };
@@ -39,7 +35,7 @@
39 status = "okay"; 35 status = "okay";
40 }; 36 };
41 37
42 uart3: uart@5000c000 { 38 uart3: serial@5000c000 {
43 fsl,uart-has-rtscts; 39 fsl,uart-has-rtscts;
44 status = "okay"; 40 status = "okay";
45 }; 41 };
@@ -90,11 +86,11 @@
90 reg = <0x53fa8000 0x4000>; 86 reg = <0x53fa8000 0x4000>;
91 }; 87 };
92 88
93 uart1: uart@53fbc000 { 89 uart1: serial@53fbc000 {
94 status = "okay"; 90 status = "okay";
95 }; 91 };
96 92
97 uart2: uart@53fc0000 { 93 uart2: serial@53fc0000 {
98 status = "okay"; 94 status = "okay";
99 }; 95 };
100 }; 96 };
@@ -142,7 +138,7 @@
142 }; 138 };
143 }; 139 };
144 140
145 fec@63fec000 { 141 ethernet@63fec000 {
146 phy-mode = "rmii"; 142 phy-mode = "rmii";
147 phy-reset-gpios = <&gpio7 6 0>; 143 phy-reset-gpios = <&gpio7 6 0>;
148 status = "okay"; 144 status = "okay";
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 5dd91b942c91..e3e869470cd3 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -88,7 +88,7 @@
88 status = "disabled"; 88 status = "disabled";
89 }; 89 };
90 90
91 uart3: uart@5000c000 { 91 uart3: serial@5000c000 {
92 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 92 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
93 reg = <0x5000c000 0x4000>; 93 reg = <0x5000c000 0x4000>;
94 interrupts = <33>; 94 interrupts = <33>;
@@ -104,6 +104,15 @@
104 status = "disabled"; 104 status = "disabled";
105 }; 105 };
106 106
107 ssi2: ssi@50014000 {
108 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
109 reg = <0x50014000 0x4000>;
110 interrupts = <30>;
111 fsl,fifo-depth = <15>;
112 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
113 status = "disabled";
114 };
115
107 esdhc@50020000 { /* ESDHC3 */ 116 esdhc@50020000 { /* ESDHC3 */
108 compatible = "fsl,imx53-esdhc"; 117 compatible = "fsl,imx53-esdhc";
109 reg = <0x50020000 0x4000>; 118 reg = <0x50020000 0x4000>;
@@ -173,14 +182,14 @@
173 status = "disabled"; 182 status = "disabled";
174 }; 183 };
175 184
176 uart1: uart@53fbc000 { 185 uart1: serial@53fbc000 {
177 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 186 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
178 reg = <0x53fbc000 0x4000>; 187 reg = <0x53fbc000 0x4000>;
179 interrupts = <31>; 188 interrupts = <31>;
180 status = "disabled"; 189 status = "disabled";
181 }; 190 };
182 191
183 uart2: uart@53fc0000 { 192 uart2: serial@53fc0000 {
184 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 193 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
185 reg = <0x53fc0000 0x4000>; 194 reg = <0x53fc0000 0x4000>;
186 interrupts = <32>; 195 interrupts = <32>;
@@ -226,7 +235,7 @@
226 status = "disabled"; 235 status = "disabled";
227 }; 236 };
228 237
229 uart4: uart@53ff0000 { 238 uart4: serial@53ff0000 {
230 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 239 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
231 reg = <0x53ff0000 0x4000>; 240 reg = <0x53ff0000 0x4000>;
232 interrupts = <13>; 241 interrupts = <13>;
@@ -241,7 +250,7 @@
241 reg = <0x60000000 0x10000000>; 250 reg = <0x60000000 0x10000000>;
242 ranges; 251 ranges;
243 252
244 uart5: uart@63f90000 { 253 uart5: serial@63f90000 {
245 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 254 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
246 reg = <0x63f90000 0x4000>; 255 reg = <0x63f90000 0x4000>;
247 interrupts = <86>; 256 interrupts = <86>;
@@ -290,7 +299,31 @@
290 status = "disabled"; 299 status = "disabled";
291 }; 300 };
292 301
293 fec@63fec000 { 302 ssi1: ssi@63fcc000 {
303 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
304 reg = <0x63fcc000 0x4000>;
305 interrupts = <29>;
306 fsl,fifo-depth = <15>;
307 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
308 status = "disabled";
309 };
310
311 audmux@63fd0000 {
312 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
313 reg = <0x63fd0000 0x4000>;
314 status = "disabled";
315 };
316
317 ssi3: ssi@63fe8000 {
318 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
319 reg = <0x63fe8000 0x4000>;
320 interrupts = <96>;
321 fsl,fifo-depth = <15>;
322 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
323 status = "disabled";
324 };
325
326 ethernet@63fec000 {
294 compatible = "fsl,imx53-fec", "fsl,imx25-fec"; 327 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
295 reg = <0x63fec000 0x4000>; 328 reg = <0x63fec000 0x4000>;
296 interrupts = <87>; 329 interrupts = <87>;
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index d2eaf521c9fd..db4c6096c562 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -17,19 +17,14 @@
17 model = "Freescale i.MX6 Quad Armadillo2 Board"; 17 model = "Freescale i.MX6 Quad Armadillo2 Board";
18 compatible = "fsl,imx6q-arm2", "fsl,imx6q"; 18 compatible = "fsl,imx6q-arm2", "fsl,imx6q";
19 19
20 chosen {
21 bootargs = "console=ttymxc0,115200 root=/dev/mmcblk3p3 rootwait";
22 };
23
24 memory { 20 memory {
25 reg = <0x10000000 0x80000000>; 21 reg = <0x10000000 0x80000000>;
26 }; 22 };
27 23
28 soc { 24 soc {
29 aips-bus@02100000 { /* AIPS2 */ 25 aips-bus@02100000 { /* AIPS2 */
30 enet@02188000 { 26 ethernet@02188000 {
31 phy-mode = "rgmii"; 27 phy-mode = "rgmii";
32 local-mac-address = [00 04 9F 01 1B 61];
33 status = "okay"; 28 status = "okay";
34 }; 29 };
35 30
@@ -37,16 +32,20 @@
37 cd-gpios = <&gpio6 11 0>; 32 cd-gpios = <&gpio6 11 0>;
38 wp-gpios = <&gpio6 14 0>; 33 wp-gpios = <&gpio6 14 0>;
39 vmmc-supply = <&reg_3p3v>; 34 vmmc-supply = <&reg_3p3v>;
35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_usdhc3_1>;
40 status = "okay"; 37 status = "okay";
41 }; 38 };
42 39
43 usdhc@0219c000 { /* uSDHC4 */ 40 usdhc@0219c000 { /* uSDHC4 */
44 non-removable; 41 non-removable;
45 vmmc-supply = <&reg_3p3v>; 42 vmmc-supply = <&reg_3p3v>;
43 pinctrl-names = "default";
44 pinctrl-0 = <&pinctrl_usdhc4_1>;
46 status = "okay"; 45 status = "okay";
47 }; 46 };
48 47
49 uart4: uart@021f0000 { 48 uart4: serial@021f0000 {
50 status = "okay"; 49 status = "okay";
51 }; 50 };
52 }; 51 };
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 4663a4e5a285..e0ec92973e7e 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -22,8 +22,30 @@
22 }; 22 };
23 23
24 soc { 24 soc {
25 aips-bus@02000000 { /* AIPS1 */
26 spba-bus@02000000 {
27 ecspi@02008000 { /* eCSPI1 */
28 fsl,spi-num-chipselects = <1>;
29 cs-gpios = <&gpio3 19 0>;
30 status = "okay";
31
32 flash: m25p80@0 {
33 compatible = "sst,sst25vf016b";
34 spi-max-frequency = <20000000>;
35 reg = <0>;
36 };
37 };
38
39 ssi1: ssi@02028000 {
40 fsl,mode = "i2s-slave";
41 status = "okay";
42 };
43 };
44
45 };
46
25 aips-bus@02100000 { /* AIPS2 */ 47 aips-bus@02100000 { /* AIPS2 */
26 enet@02188000 { 48 ethernet@02188000 {
27 phy-mode = "rgmii"; 49 phy-mode = "rgmii";
28 phy-reset-gpios = <&gpio3 23 0>; 50 phy-reset-gpios = <&gpio3 23 0>;
29 status = "okay"; 51 status = "okay";
@@ -43,13 +65,23 @@
43 status = "okay"; 65 status = "okay";
44 }; 66 };
45 67
46 uart2: uart@021e8000 { 68 audmux@021d8000 {
69 status = "okay";
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_audmux_1>;
72 };
73
74 uart2: serial@021e8000 {
47 status = "okay"; 75 status = "okay";
76 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_serial2_1>;
48 }; 78 };
49 79
50 i2c@021a0000 { /* I2C1 */ 80 i2c@021a0000 { /* I2C1 */
51 status = "okay"; 81 status = "okay";
52 clock-frequency = <100000>; 82 clock-frequency = <100000>;
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_i2c1_1>;
53 85
54 codec: sgtl5000@0a { 86 codec: sgtl5000@0a {
55 compatible = "fsl,sgtl5000"; 87 compatible = "fsl,sgtl5000";
@@ -80,4 +112,18 @@
80 regulator-always-on; 112 regulator-always-on;
81 }; 113 };
82 }; 114 };
115
116 sound {
117 compatible = "fsl,imx6q-sabrelite-sgtl5000",
118 "fsl,imx-audio-sgtl5000";
119 model = "imx6q-sabrelite-sgtl5000";
120 ssi-controller = <&ssi1>;
121 audio-codec = <&codec>;
122 audio-routing =
123 "MIC_IN", "Mic Jack",
124 "Mic Jack", "Mic Bias",
125 "Headphone Jack", "HP_OUT";
126 mux-int-port = <1>;
127 mux-ext-port = <4>;
128 };
83}; 129};
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
new file mode 100644
index 000000000000..07509a181178
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
@@ -0,0 +1,53 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "imx6q.dtsi"
15
16/ {
17 model = "Freescale i.MX6Q SABRE Smart Device Board";
18 compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
19
20 memory {
21 reg = <0x10000000 0x40000000>;
22 };
23
24 soc {
25
26 aips-bus@02000000 { /* AIPS1 */
27 spba-bus@02000000 {
28 uart1: serial@02020000 {
29 status = "okay";
30 };
31 };
32 };
33
34 aips-bus@02100000 { /* AIPS2 */
35 ethernet@02188000 {
36 phy-mode = "rgmii";
37 status = "okay";
38 };
39
40 usdhc@02194000 { /* uSDHC2 */
41 cd-gpios = <&gpio2 2 0>;
42 wp-gpios = <&gpio2 3 0>;
43 status = "okay";
44 };
45
46 usdhc@02198000 { /* uSDHC3 */
47 cd-gpios = <&gpio2 0 0>;
48 wp-gpios = <&gpio2 1 0>;
49 status = "okay";
50 };
51 };
52 };
53};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 4905f51a106f..8c90cbac945f 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -165,7 +165,7 @@
165 status = "disabled"; 165 status = "disabled";
166 }; 166 };
167 167
168 uart1: uart@02020000 { 168 uart1: serial@02020000 {
169 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 169 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
170 reg = <0x02020000 0x4000>; 170 reg = <0x02020000 0x4000>;
171 interrupts = <0 26 0x04>; 171 interrupts = <0 26 0x04>;
@@ -177,19 +177,31 @@
177 interrupts = <0 51 0x04>; 177 interrupts = <0 51 0x04>;
178 }; 178 };
179 179
180 ssi@02028000 { /* SSI1 */ 180 ssi1: ssi@02028000 {
181 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
181 reg = <0x02028000 0x4000>; 182 reg = <0x02028000 0x4000>;
182 interrupts = <0 46 0x04>; 183 interrupts = <0 46 0x04>;
184 fsl,fifo-depth = <15>;
185 fsl,ssi-dma-events = <38 37>;
186 status = "disabled";
183 }; 187 };
184 188
185 ssi@0202c000 { /* SSI2 */ 189 ssi2: ssi@0202c000 {
190 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
186 reg = <0x0202c000 0x4000>; 191 reg = <0x0202c000 0x4000>;
187 interrupts = <0 47 0x04>; 192 interrupts = <0 47 0x04>;
193 fsl,fifo-depth = <15>;
194 fsl,ssi-dma-events = <42 41>;
195 status = "disabled";
188 }; 196 };
189 197
190 ssi@02030000 { /* SSI3 */ 198 ssi3: ssi@02030000 {
199 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
191 reg = <0x02030000 0x4000>; 200 reg = <0x02030000 0x4000>;
192 interrupts = <0 48 0x04>; 201 interrupts = <0 48 0x04>;
202 fsl,fifo-depth = <15>;
203 fsl,ssi-dma-events = <46 45>;
204 status = "disabled";
193 }; 205 };
194 206
195 asrc@02034000 { 207 asrc@02034000 {
@@ -346,6 +358,90 @@
346 compatible = "fsl,imx6q-anatop"; 358 compatible = "fsl,imx6q-anatop";
347 reg = <0x020c8000 0x1000>; 359 reg = <0x020c8000 0x1000>;
348 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; 360 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
361
362 regulator-1p1@110 {
363 compatible = "fsl,anatop-regulator";
364 regulator-name = "vdd1p1";
365 regulator-min-microvolt = <800000>;
366 regulator-max-microvolt = <1375000>;
367 regulator-always-on;
368 anatop-reg-offset = <0x110>;
369 anatop-vol-bit-shift = <8>;
370 anatop-vol-bit-width = <5>;
371 anatop-min-bit-val = <4>;
372 anatop-min-voltage = <800000>;
373 anatop-max-voltage = <1375000>;
374 };
375
376 regulator-3p0@120 {
377 compatible = "fsl,anatop-regulator";
378 regulator-name = "vdd3p0";
379 regulator-min-microvolt = <2800000>;
380 regulator-max-microvolt = <3150000>;
381 regulator-always-on;
382 anatop-reg-offset = <0x120>;
383 anatop-vol-bit-shift = <8>;
384 anatop-vol-bit-width = <5>;
385 anatop-min-bit-val = <0>;
386 anatop-min-voltage = <2625000>;
387 anatop-max-voltage = <3400000>;
388 };
389
390 regulator-2p5@130 {
391 compatible = "fsl,anatop-regulator";
392 regulator-name = "vdd2p5";
393 regulator-min-microvolt = <2000000>;
394 regulator-max-microvolt = <2750000>;
395 regulator-always-on;
396 anatop-reg-offset = <0x130>;
397 anatop-vol-bit-shift = <8>;
398 anatop-vol-bit-width = <5>;
399 anatop-min-bit-val = <0>;
400 anatop-min-voltage = <2000000>;
401 anatop-max-voltage = <2750000>;
402 };
403
404 regulator-vddcore@140 {
405 compatible = "fsl,anatop-regulator";
406 regulator-name = "cpu";
407 regulator-min-microvolt = <725000>;
408 regulator-max-microvolt = <1450000>;
409 regulator-always-on;
410 anatop-reg-offset = <0x140>;
411 anatop-vol-bit-shift = <0>;
412 anatop-vol-bit-width = <5>;
413 anatop-min-bit-val = <1>;
414 anatop-min-voltage = <725000>;
415 anatop-max-voltage = <1450000>;
416 };
417
418 regulator-vddpu@140 {
419 compatible = "fsl,anatop-regulator";
420 regulator-name = "vddpu";
421 regulator-min-microvolt = <725000>;
422 regulator-max-microvolt = <1450000>;
423 regulator-always-on;
424 anatop-reg-offset = <0x140>;
425 anatop-vol-bit-shift = <9>;
426 anatop-vol-bit-width = <5>;
427 anatop-min-bit-val = <1>;
428 anatop-min-voltage = <725000>;
429 anatop-max-voltage = <1450000>;
430 };
431
432 regulator-vddsoc@140 {
433 compatible = "fsl,anatop-regulator";
434 regulator-name = "vddsoc";
435 regulator-min-microvolt = <725000>;
436 regulator-max-microvolt = <1450000>;
437 regulator-always-on;
438 anatop-reg-offset = <0x140>;
439 anatop-vol-bit-shift = <18>;
440 anatop-vol-bit-width = <5>;
441 anatop-min-bit-val = <1>;
442 anatop-min-voltage = <725000>;
443 anatop-max-voltage = <1450000>;
444 };
349 }; 445 };
350 446
351 usbphy@020c9000 { /* USBPHY1 */ 447 usbphy@020c9000 { /* USBPHY1 */
@@ -386,7 +482,62 @@
386 }; 482 };
387 483
388 iomuxc@020e0000 { 484 iomuxc@020e0000 {
485 compatible = "fsl,imx6q-iomuxc";
389 reg = <0x020e0000 0x4000>; 486 reg = <0x020e0000 0x4000>;
487
488 /* shared pinctrl settings */
489 audmux {
490 pinctrl_audmux_1: audmux-1 {
491 fsl,pins = <18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
492 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
493 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
494 3 0x80000000>; /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
495 };
496 };
497
498 i2c1 {
499 pinctrl_i2c1_1: i2c1grp-1 {
500 fsl,pins = <137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
501 196 0x4001b8b1>; /* MX6Q_PAD_EIM_D28__I2C1_SDA */
502 };
503 };
504
505 serial2 {
506 pinctrl_serial2_1: serial2grp-1 {
507 fsl,pins = <183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
508 191 0x1b0b1>; /* MX6Q_PAD_EIM_D27__UART2_RXD */
509 };
510 };
511
512 usdhc3 {
513 pinctrl_usdhc3_1: usdhc3grp-1 {
514 fsl,pins = <1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
515 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
516 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
517 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
518 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
519 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
520 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
521 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
522 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
523 1241 0x17059>; /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
524 };
525 };
526
527 usdhc4 {
528 pinctrl_usdhc4_1: usdhc4grp-1 {
529 fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
530 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
531 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
532 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
533 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
534 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
535 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
536 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
537 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
538 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
539 };
540 };
390 }; 541 };
391 542
392 dcic@020e4000 { /* DCIC1 */ 543 dcic@020e4000 { /* DCIC1 */
@@ -422,7 +573,7 @@
422 reg = <0x0217c000 0x4000>; 573 reg = <0x0217c000 0x4000>;
423 }; 574 };
424 575
425 enet@02188000 { 576 ethernet@02188000 {
426 compatible = "fsl,imx6q-fec"; 577 compatible = "fsl,imx6q-fec";
427 reg = <0x02188000 0x4000>; 578 reg = <0x02188000 0x4000>;
428 interrupts = <0 118 0x04 0 119 0x04>; 579 interrupts = <0 118 0x04 0 119 0x04>;
@@ -527,7 +678,9 @@
527 }; 678 };
528 679
529 audmux@021d8000 { 680 audmux@021d8000 {
681 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
530 reg = <0x021d8000 0x4000>; 682 reg = <0x021d8000 0x4000>;
683 status = "disabled";
531 }; 684 };
532 685
533 mipi@021dc000 { /* MIPI-CSI */ 686 mipi@021dc000 { /* MIPI-CSI */
@@ -543,28 +696,28 @@
543 interrupts = <0 18 0x04>; 696 interrupts = <0 18 0x04>;
544 }; 697 };
545 698
546 uart2: uart@021e8000 { 699 uart2: serial@021e8000 {
547 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 700 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
548 reg = <0x021e8000 0x4000>; 701 reg = <0x021e8000 0x4000>;
549 interrupts = <0 27 0x04>; 702 interrupts = <0 27 0x04>;
550 status = "disabled"; 703 status = "disabled";
551 }; 704 };
552 705
553 uart3: uart@021ec000 { 706 uart3: serial@021ec000 {
554 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 707 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
555 reg = <0x021ec000 0x4000>; 708 reg = <0x021ec000 0x4000>;
556 interrupts = <0 28 0x04>; 709 interrupts = <0 28 0x04>;
557 status = "disabled"; 710 status = "disabled";
558 }; 711 };
559 712
560 uart4: uart@021f0000 { 713 uart4: serial@021f0000 {
561 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 714 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
562 reg = <0x021f0000 0x4000>; 715 reg = <0x021f0000 0x4000>;
563 interrupts = <0 29 0x04>; 716 interrupts = <0 29 0x04>;
564 status = "disabled"; 717 status = "disabled";
565 }; 718 };
566 719
567 uart5: uart@021f4000 { 720 uart5: serial@021f4000 {
568 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 721 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
569 reg = <0x021f4000 0x4000>; 722 reg = <0x021f4000 0x4000>;
570 interrupts = <0 30 0x04>; 723 interrupts = <0 30 0x04>;
diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts
index 4a166357172b..36321bceec46 100644
--- a/arch/arm/boot/dts/tegra-cardhu.dts
+++ b/arch/arm/boot/dts/tegra-cardhu.dts
@@ -7,10 +7,10 @@
7 compatible = "nvidia,cardhu", "nvidia,tegra30"; 7 compatible = "nvidia,cardhu", "nvidia,tegra30";
8 8
9 memory { 9 memory {
10 reg = < 0x80000000 0x40000000 >; 10 reg = <0x80000000 0x40000000>;
11 }; 11 };
12 12
13 pinmux@70000000 { 13 pinmux {
14 pinctrl-names = "default"; 14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>; 15 pinctrl-0 = <&state_default>;
16 16
@@ -64,42 +64,40 @@
64 }; 64 };
65 65
66 serial@70006000 { 66 serial@70006000 {
67 clock-frequency = < 408000000 >; 67 status = "okay";
68 }; 68 clock-frequency = <408000000>;
69
70 serial@70006040 {
71 status = "disable";
72 };
73
74 serial@70006200 {
75 status = "disable";
76 };
77
78 serial@70006300 {
79 status = "disable";
80 };
81
82 serial@70006400 {
83 status = "disable";
84 }; 69 };
85 70
86 i2c@7000c000 { 71 i2c@7000c000 {
72 status = "okay";
87 clock-frequency = <100000>; 73 clock-frequency = <100000>;
88 }; 74 };
89 75
90 i2c@7000c400 { 76 i2c@7000c400 {
77 status = "okay";
91 clock-frequency = <100000>; 78 clock-frequency = <100000>;
92 }; 79 };
93 80
94 i2c@7000c500 { 81 i2c@7000c500 {
82 status = "okay";
95 clock-frequency = <100000>; 83 clock-frequency = <100000>;
84
85 /* ALS and Proximity sensor */
86 isl29028@44 {
87 compatible = "isil,isl29028";
88 reg = <0x44>;
89 interrupt-parent = <&gpio>;
90 interrupts = <88 0x04>; /*gpio PL0 */
91 };
96 }; 92 };
97 93
98 i2c@7000c700 { 94 i2c@7000c700 {
95 status = "okay";
99 clock-frequency = <100000>; 96 clock-frequency = <100000>;
100 }; 97 };
101 98
102 i2c@7000d000 { 99 i2c@7000d000 {
100 status = "okay";
103 clock-frequency = <100000>; 101 clock-frequency = <100000>;
104 102
105 wm8903: wm8903@1a { 103 wm8903: wm8903@1a {
@@ -115,46 +113,41 @@
115 micdet-delay = <100>; 113 micdet-delay = <100>;
116 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; 114 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
117 }; 115 };
116
117 tps62361 {
118 compatible = "ti,tps62361";
119 reg = <0x60>;
120
121 regulator-name = "tps62361-vout";
122 regulator-min-microvolt = <500000>;
123 regulator-max-microvolt = <1500000>;
124 regulator-boot-on;
125 regulator-always-on;
126 ti,vsel0-state-high;
127 ti,vsel1-state-high;
128 };
129 };
130
131 ahub {
132 i2s@70080400 {
133 status = "okay";
134 };
118 }; 135 };
119 136
120 sdhci@78000000 { 137 sdhci@78000000 {
138 status = "okay";
121 cd-gpios = <&gpio 69 0>; /* gpio PI5 */ 139 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
122 wp-gpios = <&gpio 155 0>; /* gpio PT3 */ 140 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
123 power-gpios = <&gpio 31 0>; /* gpio PD7 */ 141 power-gpios = <&gpio 31 0>; /* gpio PD7 */
124 bus-width = <4>; 142 bus-width = <4>;
125 }; 143 };
126 144
127 sdhci@78000200 { 145 sdhci@78000600 {
128 status = "disable"; 146 status = "okay";
129 };
130
131 sdhci@78000400 {
132 status = "disable";
133 };
134
135 sdhci@78000400 {
136 support-8bit; 147 support-8bit;
137 bus-width = <8>; 148 bus-width = <8>;
138 }; 149 };
139 150
140 ahub@70080000 {
141 i2s@70080300 {
142 status = "disable";
143 };
144
145 i2s@70080500 {
146 status = "disable";
147 };
148
149 i2s@70080600 {
150 status = "disable";
151 };
152
153 i2s@70080700 {
154 status = "disable";
155 };
156 };
157
158 sound { 151 sound {
159 compatible = "nvidia,tegra-audio-wm8903-cardhu", 152 compatible = "nvidia,tegra-audio-wm8903-cardhu",
160 "nvidia,tegra-audio-wm8903"; 153 "nvidia,tegra-audio-wm8903";
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts
index 7cd513ac5ea6..7de701365fce 100644
--- a/arch/arm/boot/dts/tegra-harmony.dts
+++ b/arch/arm/boot/dts/tegra-harmony.dts
@@ -6,11 +6,11 @@
6 model = "NVIDIA Tegra2 Harmony evaluation board"; 6 model = "NVIDIA Tegra2 Harmony evaluation board";
7 compatible = "nvidia,harmony", "nvidia,tegra20"; 7 compatible = "nvidia,harmony", "nvidia,tegra20";
8 8
9 memory@0 { 9 memory {
10 reg = < 0x00000000 0x40000000 >; 10 reg = <0x00000000 0x40000000>;
11 }; 11 };
12 12
13 pinmux@70000000 { 13 pinmux {
14 pinctrl-names = "default"; 14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>; 15 pinctrl-0 = <&state_default>;
16 16
@@ -234,42 +234,81 @@
234 }; 234 };
235 }; 235 };
236 236
237 pmc@7000f400 { 237 i2s@70002800 {
238 nvidia,invert-interrupt; 238 status = "okay";
239 };
240
241 serial@70006300 {
242 status = "okay";
243 clock-frequency = <216000000>;
239 }; 244 };
240 245
241 i2c@7000c000 { 246 i2c@7000c000 {
247 status = "okay";
242 clock-frequency = <400000>; 248 clock-frequency = <400000>;
243 249
244 wm8903: wm8903@1a { 250 wm8903: wm8903@1a {
245 compatible = "wlf,wm8903"; 251 compatible = "wlf,wm8903";
246 reg = <0x1a>; 252 reg = <0x1a>;
247 interrupt-parent = <&gpio>; 253 interrupt-parent = <&gpio>;
248 interrupts = < 187 0x04 >; 254 interrupts = <187 0x04>;
249 255
250 gpio-controller; 256 gpio-controller;
251 #gpio-cells = <2>; 257 #gpio-cells = <2>;
252 258
253 micdet-cfg = <0>; 259 micdet-cfg = <0>;
254 micdet-delay = <100>; 260 micdet-delay = <100>;
255 gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >; 261 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
256 }; 262 };
257 }; 263 };
258 264
259 i2c@7000c400 { 265 i2c@7000c400 {
266 status = "okay";
260 clock-frequency = <400000>; 267 clock-frequency = <400000>;
261 }; 268 };
262 269
263 i2c@7000c500 { 270 i2c@7000c500 {
271 status = "okay";
264 clock-frequency = <400000>; 272 clock-frequency = <400000>;
265 }; 273 };
266 274
267 i2c@7000d000 { 275 i2c@7000d000 {
276 status = "okay";
268 clock-frequency = <400000>; 277 clock-frequency = <400000>;
269 }; 278 };
270 279
271 i2s@70002a00 { 280 pmc {
272 status = "disable"; 281 nvidia,invert-interrupt;
282 };
283
284 usb@c5000000 {
285 status = "okay";
286 };
287
288 usb@c5004000 {
289 status = "okay";
290 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
291 };
292
293 usb@c5008000 {
294 status = "okay";
295 };
296
297 sdhci@c8000200 {
298 status = "okay";
299 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
300 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
301 power-gpios = <&gpio 155 0>; /* gpio PT3 */
302 bus-width = <4>;
303 };
304
305 sdhci@c8000600 {
306 status = "okay";
307 cd-gpios = <&gpio 58 0>; /* gpio PH2 */
308 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
309 power-gpios = <&gpio 70 0>; /* gpio PI6 */
310 support-8bit;
311 bus-width = <8>;
273 }; 312 };
274 313
275 sound { 314 sound {
@@ -295,51 +334,4 @@
295 nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */ 334 nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
296 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ 335 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
297 }; 336 };
298
299 serial@70006000 {
300 status = "disable";
301 };
302
303 serial@70006040 {
304 status = "disable";
305 };
306
307 serial@70006200 {
308 status = "disable";
309 };
310
311 serial@70006300 {
312 clock-frequency = < 216000000 >;
313 };
314
315 serial@70006400 {
316 status = "disable";
317 };
318
319 sdhci@c8000000 {
320 status = "disable";
321 };
322
323 sdhci@c8000200 {
324 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
325 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
326 power-gpios = <&gpio 155 0>; /* gpio PT3 */
327 bus-width = <4>;
328 };
329
330 sdhci@c8000400 {
331 status = "disable";
332 };
333
334 sdhci@c8000600 {
335 cd-gpios = <&gpio 58 0>; /* gpio PH2 */
336 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
337 power-gpios = <&gpio 70 0>; /* gpio PI6 */
338 support-8bit;
339 bus-width = <8>;
340 };
341
342 usb@c5004000 {
343 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
344 };
345}; 337};
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts
index 8d625e4c5de5..bfeb117d5aea 100644
--- a/arch/arm/boot/dts/tegra-paz00.dts
+++ b/arch/arm/boot/dts/tegra-paz00.dts
@@ -6,11 +6,11 @@
6 model = "Toshiba AC100 / Dynabook AZ"; 6 model = "Toshiba AC100 / Dynabook AZ";
7 compatible = "compal,paz00", "nvidia,tegra20"; 7 compatible = "compal,paz00", "nvidia,tegra20";
8 8
9 memory@0 { 9 memory {
10 reg = <0x00000000 0x20000000>; 10 reg = <0x00000000 0x20000000>;
11 }; 11 };
12 12
13 pinmux@70000000 { 13 pinmux {
14 pinctrl-names = "default"; 14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>; 15 pinctrl-0 = <&state_default>;
16 16
@@ -226,7 +226,22 @@
226 }; 226 };
227 }; 227 };
228 228
229 i2s@70002800 {
230 status = "okay";
231 };
232
233 serial@70006000 {
234 status = "okay";
235 clock-frequency = <216000000>;
236 };
237
238 serial@70006200 {
239 status = "okay";
240 clock-frequency = <216000000>;
241 };
242
229 i2c@7000c000 { 243 i2c@7000c000 {
244 status = "okay";
230 clock-frequency = <400000>; 245 clock-frequency = <400000>;
231 246
232 alc5632: alc5632@1e { 247 alc5632: alc5632@1e {
@@ -238,25 +253,23 @@
238 }; 253 };
239 254
240 i2c@7000c400 { 255 i2c@7000c400 {
256 status = "okay";
241 clock-frequency = <400000>; 257 clock-frequency = <400000>;
242 }; 258 };
243 259
244 i2c@7000c500 { 260 nvec {
245 status = "disable";
246 };
247
248 nvec@7000c500 {
249 #address-cells = <1>;
250 #size-cells = <0>;
251 compatible = "nvidia,nvec"; 261 compatible = "nvidia,nvec";
252 reg = <0x7000C500 0x100>; 262 reg = <0x7000c500 0x100>;
253 interrupts = <0 92 0x04>; 263 interrupts = <0 92 0x04>;
264 #address-cells = <1>;
265 #size-cells = <0>;
254 clock-frequency = <80000>; 266 clock-frequency = <80000>;
255 request-gpios = <&gpio 170 0>; 267 request-gpios = <&gpio 170 0>; /* gpio PV2 */
256 slave-addr = <138>; 268 slave-addr = <138>;
257 }; 269 };
258 270
259 i2c@7000d000 { 271 i2c@7000d000 {
272 status = "okay";
260 clock-frequency = <400000>; 273 clock-frequency = <400000>;
261 274
262 adt7461@4c { 275 adt7461@4c {
@@ -265,66 +278,29 @@
265 }; 278 };
266 }; 279 };
267 280
268 i2s@70002a00 { 281 usb@c5000000 {
269 status = "disable"; 282 status = "okay";
270 };
271
272 sound {
273 compatible = "nvidia,tegra-audio-alc5632-paz00",
274 "nvidia,tegra-audio-alc5632";
275
276 nvidia,model = "Compal PAZ00";
277
278 nvidia,audio-routing =
279 "Int Spk", "SPKOUT",
280 "Int Spk", "SPKOUTN",
281 "Headset Mic", "MICBIAS1",
282 "MIC1", "Headset Mic",
283 "Headset Stereophone", "HPR",
284 "Headset Stereophone", "HPL",
285 "DMICDAT", "Digital Mic";
286
287 nvidia,audio-codec = <&alc5632>;
288 nvidia,i2s-controller = <&tegra_i2s1>;
289 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
290 };
291
292 serial@70006000 {
293 clock-frequency = <216000000>;
294 };
295
296 serial@70006040 {
297 status = "disable";
298 };
299
300 serial@70006200 {
301 clock-frequency = <216000000>;
302 }; 283 };
303 284
304 serial@70006300 { 285 usb@c5004000 {
305 status = "disable"; 286 status = "okay";
287 nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
306 }; 288 };
307 289
308 serial@70006400 { 290 usb@c5008000 {
309 status = "disable"; 291 status = "okay";
310 }; 292 };
311 293
312 sdhci@c8000000 { 294 sdhci@c8000000 {
295 status = "okay";
313 cd-gpios = <&gpio 173 0>; /* gpio PV5 */ 296 cd-gpios = <&gpio 173 0>; /* gpio PV5 */
314 wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 297 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
315 power-gpios = <&gpio 169 0>; /* gpio PV1 */ 298 power-gpios = <&gpio 169 0>; /* gpio PV1 */
316 bus-width = <4>; 299 bus-width = <4>;
317 }; 300 };
318 301
319 sdhci@c8000200 {
320 status = "disable";
321 };
322
323 sdhci@c8000400 {
324 status = "disable";
325 };
326
327 sdhci@c8000600 { 302 sdhci@c8000600 {
303 status = "okay";
328 support-8bit; 304 support-8bit;
329 bus-width = <8>; 305 bus-width = <8>;
330 }; 306 };
@@ -345,12 +321,28 @@
345 321
346 wifi { 322 wifi {
347 label = "wifi-led"; 323 label = "wifi-led";
348 gpios = <&gpio 24 0>; 324 gpios = <&gpio 24 0>; /* gpio PD0 */
349 linux,default-trigger = "rfkill0"; 325 linux,default-trigger = "rfkill0";
350 }; 326 };
351 }; 327 };
352 328
353 usb@c5004000 { 329 sound {
354 nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ 330 compatible = "nvidia,tegra-audio-alc5632-paz00",
331 "nvidia,tegra-audio-alc5632";
332
333 nvidia,model = "Compal PAZ00";
334
335 nvidia,audio-routing =
336 "Int Spk", "SPKOUT",
337 "Int Spk", "SPKOUTN",
338 "Headset Mic", "MICBIAS1",
339 "MIC1", "Headset Mic",
340 "Headset Stereophone", "HPR",
341 "Headset Stereophone", "HPL",
342 "DMICDAT", "Digital Mic";
343
344 nvidia,audio-codec = <&alc5632>;
345 nvidia,i2s-controller = <&tegra_i2s1>;
346 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
355 }; 347 };
356}; 348};
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
index 315971993cfd..89cb7f2acd92 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -7,11 +7,10 @@
7 compatible = "nvidia,seaboard", "nvidia,tegra20"; 7 compatible = "nvidia,seaboard", "nvidia,tegra20";
8 8
9 memory { 9 memory {
10 device_type = "memory"; 10 reg = <0x00000000 0x40000000>;
11 reg = < 0x00000000 0x40000000 >;
12 }; 11 };
13 12
14 pinmux@70000000 { 13 pinmux {
15 pinctrl-names = "default"; 14 pinctrl-names = "default";
16 pinctrl-0 = <&state_default>; 15 pinctrl-0 = <&state_default>;
17 16
@@ -100,7 +99,7 @@
100 }; 99 };
101 hdint { 100 hdint {
102 nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1", 101 nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
103 "lsck", "lsda", "pta"; 102 "lsck", "lsda";
104 nvidia,function = "hdmi"; 103 nvidia,function = "hdmi";
105 }; 104 };
106 i2cp { 105 i2cp {
@@ -134,6 +133,10 @@
134 nvidia,pins = "pmc"; 133 nvidia,pins = "pmc";
135 nvidia,function = "pwr_on"; 134 nvidia,function = "pwr_on";
136 }; 135 };
136 pta {
137 nvidia,pins = "pta";
138 nvidia,function = "i2c2";
139 };
137 rm { 140 rm {
138 nvidia,pins = "rm"; 141 nvidia,pins = "rm";
139 nvidia,function = "i2c1"; 142 nvidia,function = "i2c1";
@@ -254,96 +257,138 @@
254 }; 257 };
255 }; 258 };
256 259
260 i2s@70002800 {
261 status = "okay";
262 };
263
264 serial@70006300 {
265 status = "okay";
266 clock-frequency = <216000000>;
267 };
268
257 i2c@7000c000 { 269 i2c@7000c000 {
270 status = "okay";
258 clock-frequency = <400000>; 271 clock-frequency = <400000>;
259 272
260 wm8903: wm8903@1a { 273 wm8903: wm8903@1a {
261 compatible = "wlf,wm8903"; 274 compatible = "wlf,wm8903";
262 reg = <0x1a>; 275 reg = <0x1a>;
263 interrupt-parent = <&gpio>; 276 interrupt-parent = <&gpio>;
264 interrupts = < 187 0x04 >; 277 interrupts = <187 0x04>;
265 278
266 gpio-controller; 279 gpio-controller;
267 #gpio-cells = <2>; 280 #gpio-cells = <2>;
268 281
269 micdet-cfg = <0>; 282 micdet-cfg = <0>;
270 micdet-delay = <100>; 283 micdet-delay = <100>;
271 gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >; 284 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
285 };
286
287 /* ALS and proximity sensor */
288 isl29018@44 {
289 compatible = "isil,isl29018";
290 reg = <0x44>;
291 interrupt-parent = <&gpio>;
292 interrupts = <202 0x04>; /* GPIO PZ2 */
293 };
294
295 gyrometer@68 {
296 compatible = "invn,mpu3050";
297 reg = <0x68>;
298 interrupt-parent = <&gpio>;
299 interrupts = <204 0x04>; /* gpio PZ4 */
272 }; 300 };
273 }; 301 };
274 302
275 i2c@7000c400 { 303 i2c@7000c400 {
276 clock-frequency = <400000>; 304 status = "okay";
305 clock-frequency = <100000>;
306
307 smart-battery@b {
308 compatible = "ti,bq20z75", "smart-battery-1.1";
309 reg = <0xb>;
310 ti,i2c-retry-count = <2>;
311 ti,poll-retry-count = <10>;
312 };
277 }; 313 };
278 314
279 i2c@7000c500 { 315 i2c@7000c500 {
316 status = "okay";
280 clock-frequency = <400000>; 317 clock-frequency = <400000>;
281 }; 318 };
282 319
283 i2c@7000d000 { 320 i2c@7000d000 {
321 status = "okay";
284 clock-frequency = <400000>; 322 clock-frequency = <400000>;
285 323
286 adt7461@4c { 324 temperature-sensor@4c {
287 compatible = "adt7461"; 325 compatible = "nct1008";
288 reg = <0x4c>; 326 reg = <0x4c>;
289 }; 327 };
290 };
291
292 i2s@70002a00 {
293 status = "disable";
294 };
295
296 sound {
297 compatible = "nvidia,tegra-audio-wm8903-seaboard",
298 "nvidia,tegra-audio-wm8903";
299 nvidia,model = "NVIDIA Tegra Seaboard";
300
301 nvidia,audio-routing =
302 "Headphone Jack", "HPOUTR",
303 "Headphone Jack", "HPOUTL",
304 "Int Spk", "ROP",
305 "Int Spk", "RON",
306 "Int Spk", "LOP",
307 "Int Spk", "LON",
308 "Mic Jack", "MICBIAS",
309 "IN1R", "Mic Jack";
310 328
311 nvidia,i2s-controller = <&tegra_i2s1>; 329 magnetometer@c {
312 nvidia,audio-codec = <&wm8903>; 330 compatible = "ak8975";
313 331 reg = <0xc>;
314 nvidia,spkr-en-gpios = <&wm8903 2 0>; 332 interrupt-parent = <&gpio>;
315 nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */ 333 interrupts = <109 0x04>; /* gpio PN5 */
316 }; 334 };
317
318 serial@70006000 {
319 status = "disable";
320 };
321
322 serial@70006040 {
323 status = "disable";
324 }; 335 };
325 336
326 serial@70006200 { 337 emc {
327 status = "disable"; 338 emc-table@190000 {
328 }; 339 reg = <190000>;
340 compatible = "nvidia,tegra20-emc-table";
341 clock-frequency = <190000>;
342 nvidia,emc-registers = <0x0000000c 0x00000026
343 0x00000009 0x00000003 0x00000004 0x00000004
344 0x00000002 0x0000000c 0x00000003 0x00000003
345 0x00000002 0x00000001 0x00000004 0x00000005
346 0x00000004 0x00000009 0x0000000d 0x0000059f
347 0x00000000 0x00000003 0x00000003 0x00000003
348 0x00000003 0x00000001 0x0000000b 0x000000c8
349 0x00000003 0x00000007 0x00000004 0x0000000f
350 0x00000002 0x00000000 0x00000000 0x00000002
351 0x00000000 0x00000000 0x00000083 0xa06204ae
352 0x007dc010 0x00000000 0x00000000 0x00000000
353 0x00000000 0x00000000 0x00000000 0x00000000>;
354 };
329 355
330 serial@70006300 { 356 emc-table@380000 {
331 clock-frequency = < 216000000 >; 357 reg = <380000>;
358 compatible = "nvidia,tegra20-emc-table";
359 clock-frequency = <380000>;
360 nvidia,emc-registers = <0x00000017 0x0000004b
361 0x00000012 0x00000006 0x00000004 0x00000005
362 0x00000003 0x0000000c 0x00000006 0x00000006
363 0x00000003 0x00000001 0x00000004 0x00000005
364 0x00000004 0x00000009 0x0000000d 0x00000b5f
365 0x00000000 0x00000003 0x00000003 0x00000006
366 0x00000006 0x00000001 0x00000011 0x000000c8
367 0x00000003 0x0000000e 0x00000007 0x0000000f
368 0x00000002 0x00000000 0x00000000 0x00000002
369 0x00000000 0x00000000 0x00000083 0xe044048b
370 0x007d8010 0x00000000 0x00000000 0x00000000
371 0x00000000 0x00000000 0x00000000 0x00000000>;
372 };
332 }; 373 };
333 374
334 serial@70006400 { 375 usb@c5000000 {
335 status = "disable"; 376 status = "okay";
377 nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
378 dr_mode = "otg";
336 }; 379 };
337 380
338 sdhci@c8000000 { 381 usb@c5004000 {
339 status = "disable"; 382 status = "okay";
383 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
340 }; 384 };
341 385
342 sdhci@c8000200 { 386 usb@c5008000 {
343 status = "disable"; 387 status = "okay";
344 }; 388 };
345 389
346 sdhci@c8000400 { 390 sdhci@c8000400 {
391 status = "okay";
347 cd-gpios = <&gpio 69 0>; /* gpio PI5 */ 392 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
348 wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 393 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
349 power-gpios = <&gpio 70 0>; /* gpio PI6 */ 394 power-gpios = <&gpio 70 0>; /* gpio PI6 */
@@ -351,15 +396,11 @@
351 }; 396 };
352 397
353 sdhci@c8000600 { 398 sdhci@c8000600 {
399 status = "okay";
354 support-8bit; 400 support-8bit;
355 bus-width = <8>; 401 bus-width = <8>;
356 }; 402 };
357 403
358 usb@c5000000 {
359 nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
360 dr_mode = "otg";
361 };
362
363 gpio-keys { 404 gpio-keys {
364 compatible = "gpio-keys"; 405 compatible = "gpio-keys";
365 406
@@ -380,45 +421,25 @@
380 }; 421 };
381 }; 422 };
382 423
383 emc@7000f400 { 424 sound {
384 emc-table@190000 { 425 compatible = "nvidia,tegra-audio-wm8903-seaboard",
385 reg = < 190000 >; 426 "nvidia,tegra-audio-wm8903";
386 compatible = "nvidia,tegra20-emc-table"; 427 nvidia,model = "NVIDIA Tegra Seaboard";
387 clock-frequency = < 190000 >;
388 nvidia,emc-registers = < 0x0000000c 0x00000026
389 0x00000009 0x00000003 0x00000004 0x00000004
390 0x00000002 0x0000000c 0x00000003 0x00000003
391 0x00000002 0x00000001 0x00000004 0x00000005
392 0x00000004 0x00000009 0x0000000d 0x0000059f
393 0x00000000 0x00000003 0x00000003 0x00000003
394 0x00000003 0x00000001 0x0000000b 0x000000c8
395 0x00000003 0x00000007 0x00000004 0x0000000f
396 0x00000002 0x00000000 0x00000000 0x00000002
397 0x00000000 0x00000000 0x00000083 0xa06204ae
398 0x007dc010 0x00000000 0x00000000 0x00000000
399 0x00000000 0x00000000 0x00000000 0x00000000 >;
400 };
401 428
402 emc-table@380000 { 429 nvidia,audio-routing =
403 reg = < 380000 >; 430 "Headphone Jack", "HPOUTR",
404 compatible = "nvidia,tegra20-emc-table"; 431 "Headphone Jack", "HPOUTL",
405 clock-frequency = < 380000 >; 432 "Int Spk", "ROP",
406 nvidia,emc-registers = < 0x00000017 0x0000004b 433 "Int Spk", "RON",
407 0x00000012 0x00000006 0x00000004 0x00000005 434 "Int Spk", "LOP",
408 0x00000003 0x0000000c 0x00000006 0x00000006 435 "Int Spk", "LON",
409 0x00000003 0x00000001 0x00000004 0x00000005 436 "Mic Jack", "MICBIAS",
410 0x00000004 0x00000009 0x0000000d 0x00000b5f 437 "IN1R", "Mic Jack";
411 0x00000000 0x00000003 0x00000003 0x00000006
412 0x00000006 0x00000001 0x00000011 0x000000c8
413 0x00000003 0x0000000e 0x00000007 0x0000000f
414 0x00000002 0x00000000 0x00000000 0x00000002
415 0x00000000 0x00000000 0x00000083 0xe044048b
416 0x007d8010 0x00000000 0x00000000 0x00000000
417 0x00000000 0x00000000 0x00000000 0x00000000 >;
418 };
419 };
420 438
421 usb@c5004000 { 439 nvidia,i2s-controller = <&tegra_i2s1>;
422 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ 440 nvidia,audio-codec = <&wm8903>;
441
442 nvidia,spkr-en-gpios = <&wm8903 2 0>;
443 nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */
423 }; 444 };
424}; 445};
diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts
index e4fcf9a8178a..9de5636023f6 100644
--- a/arch/arm/boot/dts/tegra-trimslice.dts
+++ b/arch/arm/boot/dts/tegra-trimslice.dts
@@ -6,11 +6,11 @@
6 model = "Compulab TrimSlice board"; 6 model = "Compulab TrimSlice board";
7 compatible = "compulab,trimslice", "nvidia,tegra20"; 7 compatible = "compulab,trimslice", "nvidia,tegra20";
8 8
9 memory@0 { 9 memory {
10 reg = < 0x00000000 0x40000000 >; 10 reg = <0x00000000 0x40000000>;
11 }; 11 };
12 12
13 pinmux@70000000 { 13 pinmux {
14 pinctrl-names = "default"; 14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>; 15 pinctrl-0 = <&state_default>;
16 16
@@ -240,72 +240,67 @@
240 }; 240 };
241 }; 241 };
242 242
243 i2s@70002800 {
244 status = "okay";
245 };
246
247 serial@70006000 {
248 status = "okay";
249 clock-frequency = <216000000>;
250 };
251
243 i2c@7000c000 { 252 i2c@7000c000 {
253 status = "okay";
244 clock-frequency = <400000>; 254 clock-frequency = <400000>;
245 }; 255 };
246 256
247 i2c@7000c400 { 257 i2c@7000c400 {
258 status = "okay";
248 clock-frequency = <400000>; 259 clock-frequency = <400000>;
249 }; 260 };
250 261
251 i2c@7000c500 { 262 i2c@7000c500 {
263 status = "okay";
252 clock-frequency = <400000>; 264 clock-frequency = <400000>;
253 };
254
255 i2c@7000d000 {
256 status = "disable";
257 };
258
259 i2s@70002800 {
260 status = "disable";
261 };
262
263 i2s@70002a00 {
264 status = "disable";
265 };
266 265
267 das@70000c00 { 266 codec: codec@1a {
268 status = "disable"; 267 compatible = "ti,tlv320aic23";
269 }; 268 reg = <0x1a>;
270 269 };
271 serial@70006000 {
272 clock-frequency = < 216000000 >;
273 };
274 270
275 serial@70006040 { 271 rtc@56 {
276 status = "disable"; 272 compatible = "emmicro,em3027";
273 reg = <0x56>;
274 };
277 }; 275 };
278 276
279 serial@70006200 { 277 usb@c5000000 {
280 status = "disable"; 278 status = "okay";
281 }; 279 };
282 280
283 serial@70006300 { 281 usb@c5004000 {
284 status = "disable"; 282 nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
285 }; 283 };
286 284
287 serial@70006400 { 285 usb@c5008000 {
288 status = "disable"; 286 status = "okay";
289 }; 287 };
290 288
291 sdhci@c8000000 { 289 sdhci@c8000000 {
292 status = "disable"; 290 status = "okay";
293 }; 291 bus-width = <4>;
294
295 sdhci@c8000200 {
296 status = "disable";
297 };
298
299 sdhci@c8000400 {
300 status = "disable";
301 }; 292 };
302 293
303 sdhci@c8000600 { 294 sdhci@c8000600 {
304 cd-gpios = <&gpio 121 0>; 295 status = "okay";
305 wp-gpios = <&gpio 122 0>; 296 cd-gpios = <&gpio 121 0>; /* gpio PP1 */
297 wp-gpios = <&gpio 122 0>; /* gpio PP2 */
298 bus-width = <4>;
306 }; 299 };
307 300
308 usb@c5004000 { 301 sound {
309 nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */ 302 compatible = "nvidia,tegra-audio-trimslice";
303 nvidia,i2s-controller = <&tegra_i2s1>;
304 nvidia,audio-codec = <&codec>;
310 }; 305 };
311}; 306};
diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts
index b922a26747e7..445343b0fbdd 100644
--- a/arch/arm/boot/dts/tegra-ventana.dts
+++ b/arch/arm/boot/dts/tegra-ventana.dts
@@ -7,10 +7,10 @@
7 compatible = "nvidia,ventana", "nvidia,tegra20"; 7 compatible = "nvidia,ventana", "nvidia,tegra20";
8 8
9 memory { 9 memory {
10 reg = < 0x00000000 0x40000000 >; 10 reg = <0x00000000 0x40000000>;
11 }; 11 };
12 12
13 pinmux@70000000 { 13 pinmux {
14 pinctrl-names = "default"; 14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>; 15 pinctrl-0 = <&state_default>;
16 16
@@ -240,38 +240,82 @@
240 }; 240 };
241 }; 241 };
242 242
243 i2s@70002800 {
244 status = "okay";
245 };
246
247 serial@70006300 {
248 status = "okay";
249 clock-frequency = <216000000>;
250 };
251
243 i2c@7000c000 { 252 i2c@7000c000 {
253 status = "okay";
244 clock-frequency = <400000>; 254 clock-frequency = <400000>;
245 255
246 wm8903: wm8903@1a { 256 wm8903: wm8903@1a {
247 compatible = "wlf,wm8903"; 257 compatible = "wlf,wm8903";
248 reg = <0x1a>; 258 reg = <0x1a>;
249 interrupt-parent = <&gpio>; 259 interrupt-parent = <&gpio>;
250 interrupts = < 187 0x04 >; 260 interrupts = <187 0x04>;
251 261
252 gpio-controller; 262 gpio-controller;
253 #gpio-cells = <2>; 263 #gpio-cells = <2>;
254 264
255 micdet-cfg = <0>; 265 micdet-cfg = <0>;
256 micdet-delay = <100>; 266 micdet-delay = <100>;
257 gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >; 267 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
268 };
269
270 /* ALS and proximity sensor */
271 isl29018@44 {
272 compatible = "isil,isl29018";
273 reg = <0x44>;
274 interrupt-parent = <&gpio>;
275 interrupts = <202 0x04>; /*gpio PZ2 */
258 }; 276 };
259 }; 277 };
260 278
261 i2c@7000c400 { 279 i2c@7000c400 {
280 status = "okay";
262 clock-frequency = <400000>; 281 clock-frequency = <400000>;
263 }; 282 };
264 283
265 i2c@7000c500 { 284 i2c@7000c500 {
285 status = "okay";
266 clock-frequency = <400000>; 286 clock-frequency = <400000>;
267 }; 287 };
268 288
269 i2c@7000d000 { 289 i2c@7000d000 {
290 status = "okay";
270 clock-frequency = <400000>; 291 clock-frequency = <400000>;
271 }; 292 };
272 293
273 i2s@70002a00 { 294 usb@c5000000 {
274 status = "disable"; 295 status = "okay";
296 };
297
298 usb@c5004000 {
299 status = "okay";
300 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
301 };
302
303 usb@c5008000 {
304 status = "okay";
305 };
306
307 sdhci@c8000400 {
308 status = "okay";
309 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
310 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
311 power-gpios = <&gpio 70 0>; /* gpio PI6 */
312 bus-width = <4>;
313 };
314
315 sdhci@c8000600 {
316 status = "okay";
317 support-8bit;
318 bus-width = <8>;
275 }; 319 };
276 320
277 sound { 321 sound {
@@ -294,51 +338,7 @@
294 338
295 nvidia,spkr-en-gpios = <&wm8903 2 0>; 339 nvidia,spkr-en-gpios = <&wm8903 2 0>;
296 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ 340 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
297 nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */ 341 nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */
298 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ 342 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
299 }; 343 };
300
301 serial@70006000 {
302 status = "disable";
303 };
304
305 serial@70006040 {
306 status = "disable";
307 };
308
309 serial@70006200 {
310 status = "disable";
311 };
312
313 serial@70006300 {
314 clock-frequency = < 216000000 >;
315 };
316
317 serial@70006400 {
318 status = "disable";
319 };
320
321 sdhci@c8000000 {
322 status = "disable";
323 };
324
325 sdhci@c8000200 {
326 status = "disable";
327 };
328
329 sdhci@c8000400 {
330 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
331 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
332 power-gpios = <&gpio 70 0>; /* gpio PI6 */
333 bus-width = <4>;
334 };
335
336 sdhci@c8000600 {
337 support-8bit;
338 bus-width = <8>;
339 };
340
341 usb@c5004000 {
342 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
343 };
344}; 344};
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 108e894a8926..c417d67e9027 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -4,207 +4,242 @@
4 compatible = "nvidia,tegra20"; 4 compatible = "nvidia,tegra20";
5 interrupt-parent = <&intc>; 5 interrupt-parent = <&intc>;
6 6
7 pmc@7000f400 { 7 intc: interrupt-controller {
8 compatible = "nvidia,tegra20-pmc";
9 reg = <0x7000e400 0x400>;
10 };
11
12 intc: interrupt-controller@50041000 {
13 compatible = "arm,cortex-a9-gic"; 8 compatible = "arm,cortex-a9-gic";
9 reg = <0x50041000 0x1000
10 0x50040100 0x0100>;
14 interrupt-controller; 11 interrupt-controller;
15 #interrupt-cells = <3>; 12 #interrupt-cells = <3>;
16 reg = < 0x50041000 0x1000 >,
17 < 0x50040100 0x0100 >;
18 }; 13 };
19 14
20 pmu { 15 apbdma: dma {
21 compatible = "arm,cortex-a9-pmu";
22 interrupts = <0 56 0x04
23 0 57 0x04>;
24 };
25
26 apbdma: dma@6000a000 {
27 compatible = "nvidia,tegra20-apbdma"; 16 compatible = "nvidia,tegra20-apbdma";
28 reg = <0x6000a000 0x1200>; 17 reg = <0x6000a000 0x1200>;
29 interrupts = < 0 104 0x04 18 interrupts = <0 104 0x04
30 0 105 0x04 19 0 105 0x04
31 0 106 0x04 20 0 106 0x04
32 0 107 0x04 21 0 107 0x04
33 0 108 0x04 22 0 108 0x04
34 0 109 0x04 23 0 109 0x04
35 0 110 0x04 24 0 110 0x04
36 0 111 0x04 25 0 111 0x04
37 0 112 0x04 26 0 112 0x04
38 0 113 0x04 27 0 113 0x04
39 0 114 0x04 28 0 114 0x04
40 0 115 0x04 29 0 115 0x04
41 0 116 0x04 30 0 116 0x04
42 0 117 0x04 31 0 117 0x04
43 0 118 0x04 32 0 118 0x04
44 0 119 0x04 >; 33 0 119 0x04>;
45 }; 34 };
46 35
47 i2c@7000c000 { 36 ahb {
48 #address-cells = <1>; 37 compatible = "nvidia,tegra20-ahb";
49 #size-cells = <0>; 38 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
50 compatible = "nvidia,tegra20-i2c"; 39 };
51 reg = <0x7000C000 0x100>; 40
52 interrupts = < 0 38 0x04 >; 41 gpio: gpio {
53 }; 42 compatible = "nvidia,tegra20-gpio";
54 43 reg = <0x6000d000 0x1000>;
55 i2c@7000c400 { 44 interrupts = <0 32 0x04
56 #address-cells = <1>; 45 0 33 0x04
57 #size-cells = <0>; 46 0 34 0x04
58 compatible = "nvidia,tegra20-i2c"; 47 0 35 0x04
59 reg = <0x7000C400 0x100>; 48 0 55 0x04
60 interrupts = < 0 84 0x04 >; 49 0 87 0x04
50 0 89 0x04>;
51 #gpio-cells = <2>;
52 gpio-controller;
53 #interrupt-cells = <2>;
54 interrupt-controller;
61 }; 55 };
62 56
63 i2c@7000c500 { 57 pinmux: pinmux {
64 #address-cells = <1>; 58 compatible = "nvidia,tegra20-pinmux";
65 #size-cells = <0>; 59 reg = <0x70000014 0x10 /* Tri-state registers */
66 compatible = "nvidia,tegra20-i2c"; 60 0x70000080 0x20 /* Mux registers */
67 reg = <0x7000C500 0x100>; 61 0x700000a0 0x14 /* Pull-up/down registers */
68 interrupts = < 0 92 0x04 >; 62 0x70000868 0xa8>; /* Pad control registers */
69 }; 63 };
70 64
71 i2c@7000d000 { 65 das {
72 #address-cells = <1>; 66 compatible = "nvidia,tegra20-das";
73 #size-cells = <0>; 67 reg = <0x70000c00 0x80>;
74 compatible = "nvidia,tegra20-i2c-dvc";
75 reg = <0x7000D000 0x200>;
76 interrupts = < 0 53 0x04 >;
77 }; 68 };
78 69
79 tegra_i2s1: i2s@70002800 { 70 tegra_i2s1: i2s@70002800 {
80 compatible = "nvidia,tegra20-i2s"; 71 compatible = "nvidia,tegra20-i2s";
81 reg = <0x70002800 0x200>; 72 reg = <0x70002800 0x200>;
82 interrupts = < 0 13 0x04 >; 73 interrupts = <0 13 0x04>;
83 nvidia,dma-request-selector = < &apbdma 2 >; 74 nvidia,dma-request-selector = <&apbdma 2>;
75 status = "disable";
84 }; 76 };
85 77
86 tegra_i2s2: i2s@70002a00 { 78 tegra_i2s2: i2s@70002a00 {
87 compatible = "nvidia,tegra20-i2s"; 79 compatible = "nvidia,tegra20-i2s";
88 reg = <0x70002a00 0x200>; 80 reg = <0x70002a00 0x200>;
89 interrupts = < 0 3 0x04 >; 81 interrupts = <0 3 0x04>;
90 nvidia,dma-request-selector = < &apbdma 1 >; 82 nvidia,dma-request-selector = <&apbdma 1>;
91 }; 83 status = "disable";
92
93 das@70000c00 {
94 compatible = "nvidia,tegra20-das";
95 reg = <0x70000c00 0x80>;
96 };
97
98 gpio: gpio@6000d000 {
99 compatible = "nvidia,tegra20-gpio";
100 reg = < 0x6000d000 0x1000 >;
101 interrupts = < 0 32 0x04
102 0 33 0x04
103 0 34 0x04
104 0 35 0x04
105 0 55 0x04
106 0 87 0x04
107 0 89 0x04 >;
108 #gpio-cells = <2>;
109 gpio-controller;
110 #interrupt-cells = <2>;
111 interrupt-controller;
112 };
113
114 pinmux: pinmux@70000000 {
115 compatible = "nvidia,tegra20-pinmux";
116 reg = < 0x70000014 0x10 /* Tri-state registers */
117 0x70000080 0x20 /* Mux registers */
118 0x700000a0 0x14 /* Pull-up/down registers */
119 0x70000868 0xa8 >; /* Pad control registers */
120 }; 84 };
121 85
122 serial@70006000 { 86 serial@70006000 {
123 compatible = "nvidia,tegra20-uart"; 87 compatible = "nvidia,tegra20-uart";
124 reg = <0x70006000 0x40>; 88 reg = <0x70006000 0x40>;
125 reg-shift = <2>; 89 reg-shift = <2>;
126 interrupts = < 0 36 0x04 >; 90 interrupts = <0 36 0x04>;
91 status = "disable";
127 }; 92 };
128 93
129 serial@70006040 { 94 serial@70006040 {
130 compatible = "nvidia,tegra20-uart"; 95 compatible = "nvidia,tegra20-uart";
131 reg = <0x70006040 0x40>; 96 reg = <0x70006040 0x40>;
132 reg-shift = <2>; 97 reg-shift = <2>;
133 interrupts = < 0 37 0x04 >; 98 interrupts = <0 37 0x04>;
99 status = "disable";
134 }; 100 };
135 101
136 serial@70006200 { 102 serial@70006200 {
137 compatible = "nvidia,tegra20-uart"; 103 compatible = "nvidia,tegra20-uart";
138 reg = <0x70006200 0x100>; 104 reg = <0x70006200 0x100>;
139 reg-shift = <2>; 105 reg-shift = <2>;
140 interrupts = < 0 46 0x04 >; 106 interrupts = <0 46 0x04>;
107 status = "disable";
141 }; 108 };
142 109
143 serial@70006300 { 110 serial@70006300 {
144 compatible = "nvidia,tegra20-uart"; 111 compatible = "nvidia,tegra20-uart";
145 reg = <0x70006300 0x100>; 112 reg = <0x70006300 0x100>;
146 reg-shift = <2>; 113 reg-shift = <2>;
147 interrupts = < 0 90 0x04 >; 114 interrupts = <0 90 0x04>;
115 status = "disable";
148 }; 116 };
149 117
150 serial@70006400 { 118 serial@70006400 {
151 compatible = "nvidia,tegra20-uart"; 119 compatible = "nvidia,tegra20-uart";
152 reg = <0x70006400 0x100>; 120 reg = <0x70006400 0x100>;
153 reg-shift = <2>; 121 reg-shift = <2>;
154 interrupts = < 0 91 0x04 >; 122 interrupts = <0 91 0x04>;
123 status = "disable";
155 }; 124 };
156 125
157 emc@7000f400 { 126 i2c@7000c000 {
127 compatible = "nvidia,tegra20-i2c";
128 reg = <0x7000c000 0x100>;
129 interrupts = <0 38 0x04>;
158 #address-cells = <1>; 130 #address-cells = <1>;
159 #size-cells = <0>; 131 #size-cells = <0>;
160 compatible = "nvidia,tegra20-emc"; 132 status = "disable";
161 reg = <0x7000f400 0x200>;
162 }; 133 };
163 134
164 sdhci@c8000000 { 135 i2c@7000c400 {
165 compatible = "nvidia,tegra20-sdhci"; 136 compatible = "nvidia,tegra20-i2c";
166 reg = <0xc8000000 0x200>; 137 reg = <0x7000c400 0x100>;
167 interrupts = < 0 14 0x04 >; 138 interrupts = <0 84 0x04>;
139 #address-cells = <1>;
140 #size-cells = <0>;
141 status = "disable";
168 }; 142 };
169 143
170 sdhci@c8000200 { 144 i2c@7000c500 {
171 compatible = "nvidia,tegra20-sdhci"; 145 compatible = "nvidia,tegra20-i2c";
172 reg = <0xc8000200 0x200>; 146 reg = <0x7000c500 0x100>;
173 interrupts = < 0 15 0x04 >; 147 interrupts = <0 92 0x04>;
148 #address-cells = <1>;
149 #size-cells = <0>;
150 status = "disable";
174 }; 151 };
175 152
176 sdhci@c8000400 { 153 i2c@7000d000 {
177 compatible = "nvidia,tegra20-sdhci"; 154 compatible = "nvidia,tegra20-i2c-dvc";
178 reg = <0xc8000400 0x200>; 155 reg = <0x7000d000 0x200>;
179 interrupts = < 0 19 0x04 >; 156 interrupts = <0 53 0x04>;
157 #address-cells = <1>;
158 #size-cells = <0>;
159 status = "disable";
180 }; 160 };
181 161
182 sdhci@c8000600 { 162 pmc {
183 compatible = "nvidia,tegra20-sdhci"; 163 compatible = "nvidia,tegra20-pmc";
184 reg = <0xc8000600 0x200>; 164 reg = <0x7000e400 0x400>;
185 interrupts = < 0 31 0x04 >; 165 };
166
167 mc {
168 compatible = "nvidia,tegra20-mc";
169 reg = <0x7000f000 0x024
170 0x7000f03c 0x3c4>;
171 interrupts = <0 77 0x04>;
172 };
173
174 gart {
175 compatible = "nvidia,tegra20-gart";
176 reg = <0x7000f024 0x00000018 /* controller registers */
177 0x58000000 0x02000000>; /* GART aperture */
178 };
179
180 emc {
181 compatible = "nvidia,tegra20-emc";
182 reg = <0x7000f400 0x200>;
183 #address-cells = <1>;
184 #size-cells = <0>;
186 }; 185 };
187 186
188 usb@c5000000 { 187 usb@c5000000 {
189 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 188 compatible = "nvidia,tegra20-ehci", "usb-ehci";
190 reg = <0xc5000000 0x4000>; 189 reg = <0xc5000000 0x4000>;
191 interrupts = < 0 20 0x04 >; 190 interrupts = <0 20 0x04>;
192 phy_type = "utmi"; 191 phy_type = "utmi";
193 nvidia,has-legacy-mode; 192 nvidia,has-legacy-mode;
193 status = "disable";
194 }; 194 };
195 195
196 usb@c5004000 { 196 usb@c5004000 {
197 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 197 compatible = "nvidia,tegra20-ehci", "usb-ehci";
198 reg = <0xc5004000 0x4000>; 198 reg = <0xc5004000 0x4000>;
199 interrupts = < 0 21 0x04 >; 199 interrupts = <0 21 0x04>;
200 phy_type = "ulpi"; 200 phy_type = "ulpi";
201 status = "disable";
201 }; 202 };
202 203
203 usb@c5008000 { 204 usb@c5008000 {
204 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 205 compatible = "nvidia,tegra20-ehci", "usb-ehci";
205 reg = <0xc5008000 0x4000>; 206 reg = <0xc5008000 0x4000>;
206 interrupts = < 0 97 0x04 >; 207 interrupts = <0 97 0x04>;
207 phy_type = "utmi"; 208 phy_type = "utmi";
209 status = "disable";
210 };
211
212 sdhci@c8000000 {
213 compatible = "nvidia,tegra20-sdhci";
214 reg = <0xc8000000 0x200>;
215 interrupts = <0 14 0x04>;
216 status = "disable";
208 }; 217 };
209};
210 218
219 sdhci@c8000200 {
220 compatible = "nvidia,tegra20-sdhci";
221 reg = <0xc8000200 0x200>;
222 interrupts = <0 15 0x04>;
223 status = "disable";
224 };
225
226 sdhci@c8000400 {
227 compatible = "nvidia,tegra20-sdhci";
228 reg = <0xc8000400 0x200>;
229 interrupts = <0 19 0x04>;
230 status = "disable";
231 };
232
233 sdhci@c8000600 {
234 compatible = "nvidia,tegra20-sdhci";
235 reg = <0xc8000600 0x200>;
236 interrupts = <0 31 0x04>;
237 status = "disable";
238 };
239
240 pmu {
241 compatible = "arm,cortex-a9-pmu";
242 interrupts = <0 56 0x04
243 0 57 0x04>;
244 };
245};
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 15200a949a81..2dcc09e784b5 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -4,190 +4,193 @@
4 compatible = "nvidia,tegra30"; 4 compatible = "nvidia,tegra30";
5 interrupt-parent = <&intc>; 5 interrupt-parent = <&intc>;
6 6
7 pmc@7000f400 { 7 intc: interrupt-controller {
8 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
9 reg = <0x7000e400 0x400>;
10 };
11
12 intc: interrupt-controller@50041000 {
13 compatible = "arm,cortex-a9-gic"; 8 compatible = "arm,cortex-a9-gic";
9 reg = <0x50041000 0x1000
10 0x50040100 0x0100>;
14 interrupt-controller; 11 interrupt-controller;
15 #interrupt-cells = <3>; 12 #interrupt-cells = <3>;
16 reg = < 0x50041000 0x1000 >,
17 < 0x50040100 0x0100 >;
18 }; 13 };
19 14
20 pmu { 15 apbdma: dma {
21 compatible = "arm,cortex-a9-pmu";
22 interrupts = <0 144 0x04
23 0 145 0x04
24 0 146 0x04
25 0 147 0x04>;
26 };
27
28 apbdma: dma@6000a000 {
29 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; 16 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
30 reg = <0x6000a000 0x1400>; 17 reg = <0x6000a000 0x1400>;
31 interrupts = < 0 104 0x04 18 interrupts = <0 104 0x04
32 0 105 0x04 19 0 105 0x04
33 0 106 0x04 20 0 106 0x04
34 0 107 0x04 21 0 107 0x04
35 0 108 0x04 22 0 108 0x04
36 0 109 0x04 23 0 109 0x04
37 0 110 0x04 24 0 110 0x04
38 0 111 0x04 25 0 111 0x04
39 0 112 0x04 26 0 112 0x04
40 0 113 0x04 27 0 113 0x04
41 0 114 0x04 28 0 114 0x04
42 0 115 0x04 29 0 115 0x04
43 0 116 0x04 30 0 116 0x04
44 0 117 0x04 31 0 117 0x04
45 0 118 0x04 32 0 118 0x04
46 0 119 0x04 33 0 119 0x04
47 0 128 0x04 34 0 128 0x04
48 0 129 0x04 35 0 129 0x04
49 0 130 0x04 36 0 130 0x04
50 0 131 0x04 37 0 131 0x04
51 0 132 0x04 38 0 132 0x04
52 0 133 0x04 39 0 133 0x04
53 0 134 0x04 40 0 134 0x04
54 0 135 0x04 41 0 135 0x04
55 0 136 0x04 42 0 136 0x04
56 0 137 0x04 43 0 137 0x04
57 0 138 0x04 44 0 138 0x04
58 0 139 0x04 45 0 139 0x04
59 0 140 0x04 46 0 140 0x04
60 0 141 0x04 47 0 141 0x04
61 0 142 0x04 48 0 142 0x04
62 0 143 0x04 >; 49 0 143 0x04>;
63 }; 50 };
64 51
65 i2c@7000c000 { 52 ahb: ahb {
66 #address-cells = <1>; 53 compatible = "nvidia,tegra30-ahb";
67 #size-cells = <0>; 54 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
68 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
69 reg = <0x7000C000 0x100>;
70 interrupts = < 0 38 0x04 >;
71 };
72
73 i2c@7000c400 {
74 #address-cells = <1>;
75 #size-cells = <0>;
76 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
77 reg = <0x7000C400 0x100>;
78 interrupts = < 0 84 0x04 >;
79 }; 55 };
80 56
81 i2c@7000c500 { 57 gpio: gpio {
82 #address-cells = <1>;
83 #size-cells = <0>;
84 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
85 reg = <0x7000C500 0x100>;
86 interrupts = < 0 92 0x04 >;
87 };
88
89 i2c@7000c700 {
90 #address-cells = <1>;
91 #size-cells = <0>;
92 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
93 reg = <0x7000c700 0x100>;
94 interrupts = < 0 120 0x04 >;
95 };
96
97 i2c@7000d000 {
98 #address-cells = <1>;
99 #size-cells = <0>;
100 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
101 reg = <0x7000D000 0x100>;
102 interrupts = < 0 53 0x04 >;
103 };
104
105 gpio: gpio@6000d000 {
106 compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio"; 58 compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
107 reg = < 0x6000d000 0x1000 >; 59 reg = <0x6000d000 0x1000>;
108 interrupts = < 0 32 0x04 60 interrupts = <0 32 0x04
109 0 33 0x04 61 0 33 0x04
110 0 34 0x04 62 0 34 0x04
111 0 35 0x04 63 0 35 0x04
112 0 55 0x04 64 0 55 0x04
113 0 87 0x04 65 0 87 0x04
114 0 89 0x04 66 0 89 0x04
115 0 125 0x04 >; 67 0 125 0x04>;
116 #gpio-cells = <2>; 68 #gpio-cells = <2>;
117 gpio-controller; 69 gpio-controller;
118 #interrupt-cells = <2>; 70 #interrupt-cells = <2>;
119 interrupt-controller; 71 interrupt-controller;
120 }; 72 };
121 73
74 pinmux: pinmux {
75 compatible = "nvidia,tegra30-pinmux";
76 reg = <0x70000868 0xd0 /* Pad control registers */
77 0x70003000 0x3e0>; /* Mux registers */
78 };
79
122 serial@70006000 { 80 serial@70006000 {
123 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 81 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
124 reg = <0x70006000 0x40>; 82 reg = <0x70006000 0x40>;
125 reg-shift = <2>; 83 reg-shift = <2>;
126 interrupts = < 0 36 0x04 >; 84 interrupts = <0 36 0x04>;
85 status = "disable";
127 }; 86 };
128 87
129 serial@70006040 { 88 serial@70006040 {
130 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 89 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
131 reg = <0x70006040 0x40>; 90 reg = <0x70006040 0x40>;
132 reg-shift = <2>; 91 reg-shift = <2>;
133 interrupts = < 0 37 0x04 >; 92 interrupts = <0 37 0x04>;
93 status = "disable";
134 }; 94 };
135 95
136 serial@70006200 { 96 serial@70006200 {
137 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 97 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
138 reg = <0x70006200 0x100>; 98 reg = <0x70006200 0x100>;
139 reg-shift = <2>; 99 reg-shift = <2>;
140 interrupts = < 0 46 0x04 >; 100 interrupts = <0 46 0x04>;
101 status = "disable";
141 }; 102 };
142 103
143 serial@70006300 { 104 serial@70006300 {
144 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 105 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
145 reg = <0x70006300 0x100>; 106 reg = <0x70006300 0x100>;
146 reg-shift = <2>; 107 reg-shift = <2>;
147 interrupts = < 0 90 0x04 >; 108 interrupts = <0 90 0x04>;
109 status = "disable";
148 }; 110 };
149 111
150 serial@70006400 { 112 serial@70006400 {
151 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 113 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
152 reg = <0x70006400 0x100>; 114 reg = <0x70006400 0x100>;
153 reg-shift = <2>; 115 reg-shift = <2>;
154 interrupts = < 0 91 0x04 >; 116 interrupts = <0 91 0x04>;
117 status = "disable";
155 }; 118 };
156 119
157 sdhci@78000000 { 120 i2c@7000c000 {
158 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 121 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
159 reg = <0x78000000 0x200>; 122 reg = <0x7000c000 0x100>;
160 interrupts = < 0 14 0x04 >; 123 interrupts = <0 38 0x04>;
124 #address-cells = <1>;
125 #size-cells = <0>;
126 status = "disable";
161 }; 127 };
162 128
163 sdhci@78000200 { 129 i2c@7000c400 {
164 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 130 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
165 reg = <0x78000200 0x200>; 131 reg = <0x7000c400 0x100>;
166 interrupts = < 0 15 0x04 >; 132 interrupts = <0 84 0x04>;
133 #address-cells = <1>;
134 #size-cells = <0>;
135 status = "disable";
167 }; 136 };
168 137
169 sdhci@78000400 { 138 i2c@7000c500 {
170 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 139 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
171 reg = <0x78000400 0x200>; 140 reg = <0x7000c500 0x100>;
172 interrupts = < 0 19 0x04 >; 141 interrupts = <0 92 0x04>;
142 #address-cells = <1>;
143 #size-cells = <0>;
144 status = "disable";
173 }; 145 };
174 146
175 sdhci@78000600 { 147 i2c@7000c700 {
176 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 148 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
177 reg = <0x78000600 0x200>; 149 reg = <0x7000c700 0x100>;
178 interrupts = < 0 31 0x04 >; 150 interrupts = <0 120 0x04>;
151 #address-cells = <1>;
152 #size-cells = <0>;
153 status = "disable";
179 }; 154 };
180 155
181 pinmux: pinmux@70000000 { 156 i2c@7000d000 {
182 compatible = "nvidia,tegra30-pinmux"; 157 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
183 reg = < 0x70000868 0xd0 /* Pad control registers */ 158 reg = <0x7000d000 0x100>;
184 0x70003000 0x3e0 >; /* Mux registers */ 159 interrupts = <0 53 0x04>;
160 #address-cells = <1>;
161 #size-cells = <0>;
162 status = "disable";
163 };
164
165 pmc {
166 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
167 reg = <0x7000e400 0x400>;
168 };
169
170 mc {
171 compatible = "nvidia,tegra30-mc";
172 reg = <0x7000f000 0x010
173 0x7000f03c 0x1b4
174 0x7000f200 0x028
175 0x7000f284 0x17c>;
176 interrupts = <0 77 0x04>;
177 };
178
179 smmu {
180 compatible = "nvidia,tegra30-smmu";
181 reg = <0x7000f010 0x02c
182 0x7000f1f0 0x010
183 0x7000f228 0x05c>;
184 nvidia,#asids = <4>; /* # of ASIDs */
185 dma-window = <0 0x40000000>; /* IOVA start & length */
186 nvidia,ahb = <&ahb>;
185 }; 187 };
186 188
187 ahub { 189 ahub {
188 compatible = "nvidia,tegra30-ahub"; 190 compatible = "nvidia,tegra30-ahub";
189 reg = <0x70080000 0x200 0x70080200 0x100>; 191 reg = <0x70080000 0x200
190 interrupts = < 0 103 0x04 >; 192 0x70080200 0x100>;
193 interrupts = <0 103 0x04>;
191 nvidia,dma-request-selector = <&apbdma 1>; 194 nvidia,dma-request-selector = <&apbdma 1>;
192 195
193 ranges; 196 ranges;
@@ -198,30 +201,71 @@
198 compatible = "nvidia,tegra30-i2s"; 201 compatible = "nvidia,tegra30-i2s";
199 reg = <0x70080300 0x100>; 202 reg = <0x70080300 0x100>;
200 nvidia,ahub-cif-ids = <4 4>; 203 nvidia,ahub-cif-ids = <4 4>;
204 status = "disable";
201 }; 205 };
202 206
203 tegra_i2s1: i2s@70080400 { 207 tegra_i2s1: i2s@70080400 {
204 compatible = "nvidia,tegra30-i2s"; 208 compatible = "nvidia,tegra30-i2s";
205 reg = <0x70080400 0x100>; 209 reg = <0x70080400 0x100>;
206 nvidia,ahub-cif-ids = <5 5>; 210 nvidia,ahub-cif-ids = <5 5>;
211 status = "disable";
207 }; 212 };
208 213
209 tegra_i2s2: i2s@70080500 { 214 tegra_i2s2: i2s@70080500 {
210 compatible = "nvidia,tegra30-i2s"; 215 compatible = "nvidia,tegra30-i2s";
211 reg = <0x70080500 0x100>; 216 reg = <0x70080500 0x100>;
212 nvidia,ahub-cif-ids = <6 6>; 217 nvidia,ahub-cif-ids = <6 6>;
218 status = "disable";
213 }; 219 };
214 220
215 tegra_i2s3: i2s@70080600 { 221 tegra_i2s3: i2s@70080600 {
216 compatible = "nvidia,tegra30-i2s"; 222 compatible = "nvidia,tegra30-i2s";
217 reg = <0x70080600 0x100>; 223 reg = <0x70080600 0x100>;
218 nvidia,ahub-cif-ids = <7 7>; 224 nvidia,ahub-cif-ids = <7 7>;
225 status = "disable";
219 }; 226 };
220 227
221 tegra_i2s4: i2s@70080700 { 228 tegra_i2s4: i2s@70080700 {
222 compatible = "nvidia,tegra30-i2s"; 229 compatible = "nvidia,tegra30-i2s";
223 reg = <0x70080700 0x100>; 230 reg = <0x70080700 0x100>;
224 nvidia,ahub-cif-ids = <8 8>; 231 nvidia,ahub-cif-ids = <8 8>;
232 status = "disable";
225 }; 233 };
226 }; 234 };
235
236 sdhci@78000000 {
237 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
238 reg = <0x78000000 0x200>;
239 interrupts = <0 14 0x04>;
240 status = "disable";
241 };
242
243 sdhci@78000200 {
244 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
245 reg = <0x78000200 0x200>;
246 interrupts = <0 15 0x04>;
247 status = "disable";
248 };
249
250 sdhci@78000400 {
251 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
252 reg = <0x78000400 0x200>;
253 interrupts = <0 19 0x04>;
254 status = "disable";
255 };
256
257 sdhci@78000600 {
258 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
259 reg = <0x78000600 0x200>;
260 interrupts = <0 31 0x04>;
261 status = "disable";
262 };
263
264 pmu {
265 compatible = "arm,cortex-a9-pmu";
266 interrupts = <0 144 0x04
267 0 145 0x04
268 0 146 0x04
269 0 147 0x04>;
270 };
227}; 271};
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index 1ebbf451c48d..5406c23a02e3 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -22,6 +22,7 @@ CONFIG_BLK_DEV_INTEGRITY=y
22# CONFIG_IOSCHED_DEADLINE is not set 22# CONFIG_IOSCHED_DEADLINE is not set
23# CONFIG_IOSCHED_CFQ is not set 23# CONFIG_IOSCHED_CFQ is not set
24CONFIG_ARCH_MXS=y 24CONFIG_ARCH_MXS=y
25CONFIG_MACH_MXS_DT=y
25CONFIG_MACH_MX23EVK=y 26CONFIG_MACH_MX23EVK=y
26CONFIG_MACH_MX28EVK=y 27CONFIG_MACH_MX28EVK=y
27CONFIG_MACH_STMP378X_DEVB=y 28CONFIG_MACH_STMP378X_DEVB=y
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
index 3851d8a27875..05541cf4a878 100644
--- a/arch/arm/mach-imx/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -42,4 +42,5 @@ dtb-$(CONFIG_MACH_IMX51_DT) += imx51-babbage.dtb
42dtb-$(CONFIG_MACH_IMX53_DT) += imx53-ard.dtb imx53-evk.dtb \ 42dtb-$(CONFIG_MACH_IMX53_DT) += imx53-ard.dtb imx53-evk.dtb \
43 imx53-qsb.dtb imx53-smd.dtb 43 imx53-qsb.dtb imx53-smd.dtb
44dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \ 44dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \
45 imx6q-sabrelite.dtb 45 imx6q-sabrelite.dtb \
46 imx6q-sabresd.dtb \
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index b8a382defb23..fcd94f3b0f0e 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -31,6 +31,11 @@ static const char *per_lp_apm_sel[] = { "main_bus", "lp_apm", };
31static const char *per_root_sel[] = { "per_podf", "ipg", }; 31static const char *per_root_sel[] = { "per_podf", "ipg", };
32static const char *esdhc_c_sel[] = { "esdhc_a_podf", "esdhc_b_podf", }; 32static const char *esdhc_c_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
33static const char *esdhc_d_sel[] = { "esdhc_a_podf", "esdhc_b_podf", }; 33static const char *esdhc_d_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
34static const char *ssi_apm_sels[] = { "ckih1", "lp_amp", "ckih2", };
35static const char *ssi_clk_sels[] = { "pll1_sw", "pll2_sw", "pll3_sw", "ssi_apm", };
36static const char *ssi3_clk_sels[] = { "ssi1_root_gate", "ssi2_root_gate", };
37static const char *ssi_ext1_com_sels[] = { "ssi_ext1_podf", "ssi1_root_gate", };
38static const char *ssi_ext2_com_sels[] = { "ssi_ext2_podf", "ssi2_root_gate", };
34static const char *emi_slow_sel[] = { "main_bus", "ahb", }; 39static const char *emi_slow_sel[] = { "main_bus", "ahb", };
35static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", }; 40static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", };
36static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", }; 41static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", };
@@ -71,6 +76,11 @@ enum imx5_clks {
71 pll3_sw, ipu_di0_sel, ipu_di1_sel, tve_ext_sel, mx51_mipi, pll4_sw, 76 pll3_sw, ipu_di0_sel, ipu_di1_sel, tve_ext_sel, mx51_mipi, pll4_sw,
72 ldb_di1_sel, di_pll4_podf, ldb_di0_sel, ldb_di0_gate, usb_phy1_gate, 77 ldb_di1_sel, di_pll4_podf, ldb_di0_sel, ldb_di0_gate, usb_phy1_gate,
73 usb_phy2_gate, per_lp_apm, per_pred1, per_pred2, per_podf, per_root, 78 usb_phy2_gate, per_lp_apm, per_pred1, per_pred2, per_podf, per_root,
79 ssi_apm, ssi1_root_sel, ssi2_root_sel, ssi3_root_sel, ssi_ext1_sel,
80 ssi_ext2_sel, ssi_ext1_com_sel, ssi_ext2_com_sel, ssi1_root_pred,
81 ssi1_root_podf, ssi2_root_pred, ssi2_root_podf, ssi_ext1_pred,
82 ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate,
83 ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
74 clk_max 84 clk_max
75}; 85};
76 86
@@ -195,6 +205,28 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
195 clk[uart5_per_gate] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14); 205 clk[uart5_per_gate] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
196 clk[gpc_dvfs] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24); 206 clk[gpc_dvfs] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24);
197 207
208 clk[ssi_apm] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels));
209 clk[ssi1_root_sel] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
210 clk[ssi2_root_sel] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
211 clk[ssi3_root_sel] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels));
212 clk[ssi_ext1_sel] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
213 clk[ssi_ext2_sel] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
214 clk[ssi_ext1_com_sel] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels));
215 clk[ssi_ext2_com_sel] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels));
216 clk[ssi1_root_pred] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3);
217 clk[ssi1_root_podf] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6);
218 clk[ssi2_root_pred] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3);
219 clk[ssi2_root_podf] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6);
220 clk[ssi_ext1_pred] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3);
221 clk[ssi_ext1_podf] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6);
222 clk[ssi_ext2_pred] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3);
223 clk[ssi_ext2_podf] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6);
224 clk[ssi1_root_gate] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18);
225 clk[ssi2_root_gate] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22);
226 clk[ssi3_root_gate] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26);
227 clk[ssi_ext1_gate] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28);
228 clk[ssi_ext2_gate] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30);
229
198 for (i = 0; i < ARRAY_SIZE(clk); i++) 230 for (i = 0; i < ARRAY_SIZE(clk); i++)
199 if (IS_ERR(clk[i])) 231 if (IS_ERR(clk[i]))
200 pr_err("i.MX5 clk %d: register failed with %ld\n", 232 pr_err("i.MX5 clk %d: register failed with %ld\n",
@@ -237,6 +269,8 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
237 clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0"); 269 clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
238 clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1"); 270 clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
239 clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2"); 271 clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2");
272 clk_register_clkdev(clk[ssi_ext1_gate], "ssi_ext1", NULL);
273 clk_register_clkdev(clk[ssi_ext2_gate], "ssi_ext2", NULL);
240 clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma"); 274 clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
241 clk_register_clkdev(clk[cpu_podf], "cpu", NULL); 275 clk_register_clkdev(clk[cpu_podf], "cpu", NULL);
242 clk_register_clkdev(clk[iim_gate], "iim", NULL); 276 clk_register_clkdev(clk[iim_gate], "iim", NULL);
@@ -320,6 +354,9 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
320 clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx51.3"); 354 clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx51.3");
321 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.3"); 355 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.3");
322 clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx51.3"); 356 clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx51.3");
357 clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "83fcc000.ssi");
358 clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "70014000.ssi");
359 clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "83fe8000.ssi");
323 360
324 /* set the usboh3 parent to pll2_sw */ 361 /* set the usboh3 parent to pll2_sw */
325 clk_set_parent(clk[usboh3_sel], clk[pll2_sw]); 362 clk_set_parent(clk[usboh3_sel], clk[pll2_sw]);
@@ -406,6 +443,9 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
406 clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx53.3"); 443 clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx53.3");
407 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.3"); 444 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.3");
408 clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx53.3"); 445 clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx53.3");
446 clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi");
447 clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi");
448 clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi");
409 449
410 /* set SDHC root clock to 200MHZ*/ 450 /* set SDHC root clock to 200MHZ*/
411 clk_set_rate(clk[esdhc_a_podf], 200000000); 451 clk_set_rate(clk[esdhc_a_podf], 200000000);
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index f40a35da2e5c..cab02d0a15d6 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -155,7 +155,8 @@ enum mx6q_clks {
155 gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1, 155 gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
156 ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3, 156 ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
157 usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg, 157 usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
158 pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, clk_max 158 pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg,
159 ssi2_ipg, ssi3_ipg, clk_max
159}; 160};
160 161
161static struct clk *clk[clk_max]; 162static struct clk *clk[clk_max];
@@ -367,9 +368,9 @@ int __init mx6q_clocks_init(void)
367 clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4); 368 clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4);
368 clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); 369 clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
369 clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); 370 clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
370 clk[ssi1] = imx_clk_gate2("ssi1", "ssi1_podf", base + 0x7c, 18); 371 clk[ssi1_ipg] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18);
371 clk[ssi2] = imx_clk_gate2("ssi2", "ssi2_podf", base + 0x7c, 20); 372 clk[ssi2_ipg] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20);
372 clk[ssi3] = imx_clk_gate2("ssi3", "ssi3_podf", base + 0x7c, 22); 373 clk[ssi3_ipg] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22);
373 clk[uart_ipg] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24); 374 clk[uart_ipg] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
374 clk[uart_serial] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26); 375 clk[uart_serial] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26);
375 clk[usboh3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); 376 clk[usboh3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
@@ -392,17 +393,17 @@ int __init mx6q_clocks_init(void)
392 clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); 393 clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
393 clk_register_clkdev(clk[twd], NULL, "smp_twd"); 394 clk_register_clkdev(clk[twd], NULL, "smp_twd");
394 clk_register_clkdev(clk[usboh3], NULL, "usboh3"); 395 clk_register_clkdev(clk[usboh3], NULL, "usboh3");
395 clk_register_clkdev(clk[uart_serial], "per", "2020000.uart"); 396 clk_register_clkdev(clk[uart_serial], "per", "2020000.serial");
396 clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.uart"); 397 clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial");
397 clk_register_clkdev(clk[uart_serial], "per", "21e8000.uart"); 398 clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial");
398 clk_register_clkdev(clk[uart_ipg], "ipg", "21e8000.uart"); 399 clk_register_clkdev(clk[uart_ipg], "ipg", "21e8000.serial");
399 clk_register_clkdev(clk[uart_serial], "per", "21ec000.uart"); 400 clk_register_clkdev(clk[uart_serial], "per", "21ec000.serial");
400 clk_register_clkdev(clk[uart_ipg], "ipg", "21ec000.uart"); 401 clk_register_clkdev(clk[uart_ipg], "ipg", "21ec000.serial");
401 clk_register_clkdev(clk[uart_serial], "per", "21f0000.uart"); 402 clk_register_clkdev(clk[uart_serial], "per", "21f0000.serial");
402 clk_register_clkdev(clk[uart_ipg], "ipg", "21f0000.uart"); 403 clk_register_clkdev(clk[uart_ipg], "ipg", "21f0000.serial");
403 clk_register_clkdev(clk[uart_serial], "per", "21f4000.uart"); 404 clk_register_clkdev(clk[uart_serial], "per", "21f4000.serial");
404 clk_register_clkdev(clk[uart_ipg], "ipg", "21f4000.uart"); 405 clk_register_clkdev(clk[uart_ipg], "ipg", "21f4000.serial");
405 clk_register_clkdev(clk[enet], NULL, "2188000.enet"); 406 clk_register_clkdev(clk[enet], NULL, "2188000.ethernet");
406 clk_register_clkdev(clk[usdhc1], NULL, "2190000.usdhc"); 407 clk_register_clkdev(clk[usdhc1], NULL, "2190000.usdhc");
407 clk_register_clkdev(clk[usdhc2], NULL, "2194000.usdhc"); 408 clk_register_clkdev(clk[usdhc2], NULL, "2194000.usdhc");
408 clk_register_clkdev(clk[usdhc3], NULL, "2198000.usdhc"); 409 clk_register_clkdev(clk[usdhc3], NULL, "2198000.usdhc");
@@ -418,6 +419,10 @@ int __init mx6q_clocks_init(void)
418 clk_register_clkdev(clk[sdma], NULL, "20ec000.sdma"); 419 clk_register_clkdev(clk[sdma], NULL, "20ec000.sdma");
419 clk_register_clkdev(clk[dummy], NULL, "20bc000.wdog"); 420 clk_register_clkdev(clk[dummy], NULL, "20bc000.wdog");
420 clk_register_clkdev(clk[dummy], NULL, "20c0000.wdog"); 421 clk_register_clkdev(clk[dummy], NULL, "20c0000.wdog");
422 clk_register_clkdev(clk[ssi1_ipg], NULL, "2028000.ssi");
423 clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
424 clk_register_clkdev(clk[ahb], "ahb", NULL);
425 clk_register_clkdev(clk[cko1], "cko1", NULL);
421 426
422 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) { 427 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) {
423 c = clk_get_sys(clks_init_on[i], NULL); 428 c = clk_get_sys(clks_init_on[i], NULL);
diff --git a/arch/arm/mach-imx/imx53-dt.c b/arch/arm/mach-imx/imx53-dt.c
index 574eca4b89a5..eb04b6248e48 100644
--- a/arch/arm/mach-imx/imx53-dt.c
+++ b/arch/arm/mach-imx/imx53-dt.c
@@ -10,6 +10,9 @@
10 * http://www.gnu.org/copyleft/gpl.html 10 * http://www.gnu.org/copyleft/gpl.html
11 */ 11 */
12 12
13#include <linux/clk.h>
14#include <linux/clkdev.h>
15#include <linux/err.h>
13#include <linux/io.h> 16#include <linux/io.h>
14#include <linux/irq.h> 17#include <linux/irq.h>
15#include <linux/irqdomain.h> 18#include <linux/irqdomain.h>
@@ -81,6 +84,19 @@ static const struct of_device_id imx53_iomuxc_of_match[] __initconst = {
81 { /* sentinel */ } 84 { /* sentinel */ }
82}; 85};
83 86
87static void __init imx53_qsb_init(void)
88{
89 struct clk *clk;
90
91 clk = clk_get_sys(NULL, "ssi_ext1");
92 if (IS_ERR(clk)) {
93 pr_err("failed to get clk ssi_ext1\n");
94 return;
95 }
96
97 clk_register_clkdev(clk, NULL, "0-000a");
98}
99
84static void __init imx53_dt_init(void) 100static void __init imx53_dt_init(void)
85{ 101{
86 struct device_node *node; 102 struct device_node *node;
@@ -99,6 +115,9 @@ static void __init imx53_dt_init(void)
99 of_node_put(node); 115 of_node_put(node);
100 } 116 }
101 117
118 if (of_machine_is_compatible("fsl,imx53-qsb"))
119 imx53_qsb_init();
120
102 of_platform_populate(NULL, of_default_bus_match_table, 121 of_platform_populate(NULL, of_default_bus_match_table,
103 imx53_auxdata_lookup, NULL); 122 imx53_auxdata_lookup, NULL);
104} 123}
diff --git a/arch/arm/mach-imx/lluart.c b/arch/arm/mach-imx/lluart.c
index 0213f8dcee81..c40a34c00489 100644
--- a/arch/arm/mach-imx/lluart.c
+++ b/arch/arm/mach-imx/lluart.c
@@ -17,6 +17,12 @@
17#include <mach/hardware.h> 17#include <mach/hardware.h>
18 18
19static struct map_desc imx_lluart_desc = { 19static struct map_desc imx_lluart_desc = {
20#ifdef CONFIG_DEBUG_IMX6Q_UART2
21 .virtual = MX6Q_IO_P2V(MX6Q_UART2_BASE_ADDR),
22 .pfn = __phys_to_pfn(MX6Q_UART2_BASE_ADDR),
23 .length = MX6Q_UART2_SIZE,
24 .type = MT_DEVICE,
25#endif
20#ifdef CONFIG_DEBUG_IMX6Q_UART4 26#ifdef CONFIG_DEBUG_IMX6Q_UART4
21 .virtual = MX6Q_IO_P2V(MX6Q_UART4_BASE_ADDR), 27 .virtual = MX6Q_IO_P2V(MX6Q_UART4_BASE_ADDR),
22 .pfn = __phys_to_pfn(MX6Q_UART4_BASE_ADDR), 28 .pfn = __phys_to_pfn(MX6Q_UART4_BASE_ADDR),
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 3df360a52c17..b47e98b7d539 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -10,6 +10,8 @@
10 * http://www.gnu.org/copyleft/gpl.html 10 * http://www.gnu.org/copyleft/gpl.html
11 */ 11 */
12 12
13#include <linux/clk.h>
14#include <linux/clkdev.h>
13#include <linux/delay.h> 15#include <linux/delay.h>
14#include <linux/init.h> 16#include <linux/init.h>
15#include <linux/io.h> 17#include <linux/io.h>
@@ -64,18 +66,53 @@ soft:
64/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */ 66/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
65static int ksz9021rn_phy_fixup(struct phy_device *phydev) 67static int ksz9021rn_phy_fixup(struct phy_device *phydev)
66{ 68{
67 /* min rx data delay */ 69 if (IS_ENABLED(CONFIG_PHYLIB)) {
68 phy_write(phydev, 0x0b, 0x8105); 70 /* min rx data delay */
69 phy_write(phydev, 0x0c, 0x0000); 71 phy_write(phydev, 0x0b, 0x8105);
72 phy_write(phydev, 0x0c, 0x0000);
70 73
71 /* max rx/tx clock delay, min rx/tx control delay */ 74 /* max rx/tx clock delay, min rx/tx control delay */
72 phy_write(phydev, 0x0b, 0x8104); 75 phy_write(phydev, 0x0b, 0x8104);
73 phy_write(phydev, 0x0c, 0xf0f0); 76 phy_write(phydev, 0x0c, 0xf0f0);
74 phy_write(phydev, 0x0b, 0x104); 77 phy_write(phydev, 0x0b, 0x104);
78 }
75 79
76 return 0; 80 return 0;
77} 81}
78 82
83static void __init imx6q_sabrelite_cko1_setup(void)
84{
85 struct clk *cko1_sel, *ahb, *cko1;
86 unsigned long rate;
87
88 cko1_sel = clk_get_sys(NULL, "cko1_sel");
89 ahb = clk_get_sys(NULL, "ahb");
90 cko1 = clk_get_sys(NULL, "cko1");
91 if (IS_ERR(cko1_sel) || IS_ERR(ahb) || IS_ERR(cko1)) {
92 pr_err("cko1 setup failed!\n");
93 goto put_clk;
94 }
95 clk_set_parent(cko1_sel, ahb);
96 rate = clk_round_rate(cko1, 16000000);
97 clk_set_rate(cko1, rate);
98 clk_register_clkdev(cko1, NULL, "0-000a");
99put_clk:
100 if (!IS_ERR(cko1_sel))
101 clk_put(cko1_sel);
102 if (!IS_ERR(ahb))
103 clk_put(ahb);
104 if (!IS_ERR(cko1))
105 clk_put(cko1);
106}
107
108static void __init imx6q_sabrelite_init(void)
109{
110 if (IS_ENABLED(CONFIG_PHYLIB))
111 phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
112 ksz9021rn_phy_fixup);
113 imx6q_sabrelite_cko1_setup();
114}
115
79static void __init imx6q_init_machine(void) 116static void __init imx6q_init_machine(void)
80{ 117{
81 /* 118 /*
@@ -85,8 +122,7 @@ static void __init imx6q_init_machine(void)
85 pinctrl_provide_dummies(); 122 pinctrl_provide_dummies();
86 123
87 if (of_machine_is_compatible("fsl,imx6q-sabrelite")) 124 if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
88 phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, 125 imx6q_sabrelite_init();
89 ksz9021rn_phy_fixup);
90 126
91 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 127 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
92 128
@@ -139,6 +175,7 @@ static struct sys_timer imx6q_timer = {
139static const char *imx6q_dt_compat[] __initdata = { 175static const char *imx6q_dt_compat[] __initdata = {
140 "fsl,imx6q-arm2", 176 "fsl,imx6q-arm2",
141 "fsl,imx6q-sabrelite", 177 "fsl,imx6q-sabrelite",
178 "fsl,imx6q-sabresd",
142 "fsl,imx6q", 179 "fsl,imx6q",
143 NULL, 180 NULL,
144}; 181};
diff --git a/arch/arm/mach-imx/mach-mx51_babbage.c b/arch/arm/mach-imx/mach-mx51_babbage.c
index e4b822e9f719..517672ebcbc5 100644
--- a/arch/arm/mach-imx/mach-mx51_babbage.c
+++ b/arch/arm/mach-imx/mach-mx51_babbage.c
@@ -163,6 +163,12 @@ static iomux_v3_cfg_t mx51babbage_pads[] = {
163 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, 163 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
164 MX51_PAD_CSPI1_SS0__GPIO4_24, 164 MX51_PAD_CSPI1_SS0__GPIO4_24,
165 MX51_PAD_CSPI1_SS1__GPIO4_25, 165 MX51_PAD_CSPI1_SS1__GPIO4_25,
166
167 /* Audio */
168 MX51_PAD_AUD3_BB_TXD__AUD3_TXD,
169 MX51_PAD_AUD3_BB_RXD__AUD3_RXD,
170 MX51_PAD_AUD3_BB_CK__AUD3_TXC,
171 MX51_PAD_AUD3_BB_FS__AUD3_TXFS,
166}; 172};
167 173
168/* Serial ports */ 174/* Serial ports */
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 07d5383d68ee..91cf0625819c 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -7,18 +7,28 @@ config MXS_OCOTP
7 7
8config SOC_IMX23 8config SOC_IMX23
9 bool 9 bool
10 select ARM_AMBA
10 select CPU_ARM926T 11 select CPU_ARM926T
11 select HAVE_PWM 12 select HAVE_PWM
12 select PINCTRL_IMX23 13 select PINCTRL_IMX23
13 14
14config SOC_IMX28 15config SOC_IMX28
15 bool 16 bool
17 select ARM_AMBA
16 select CPU_ARM926T 18 select CPU_ARM926T
17 select HAVE_PWM 19 select HAVE_PWM
18 select PINCTRL_IMX28 20 select PINCTRL_IMX28
19 21
20comment "MXS platforms:" 22comment "MXS platforms:"
21 23
24config MACH_MXS_DT
25 bool "Support MXS platforms from device tree"
26 select SOC_IMX23
27 select SOC_IMX28
28 help
29 Include support for Freescale MXS platforms(i.MX23 and i.MX28)
30 using the device tree for discovery
31
22config MACH_STMP378X_DEVB 32config MACH_STMP378X_DEVB
23 bool "Support STMP378x_devb Platform" 33 bool "Support STMP378x_devb Platform"
24 select SOC_IMX23 34 select SOC_IMX23
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index 6ce21a26412e..e41590ccb437 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -4,6 +4,7 @@ obj-y := devices.o icoll.o iomux.o system.o timer.o mm.o
4obj-$(CONFIG_MXS_OCOTP) += ocotp.o 4obj-$(CONFIG_MXS_OCOTP) += ocotp.o
5obj-$(CONFIG_PM) += pm.o 5obj-$(CONFIG_PM) += pm.o
6 6
7obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o
7obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o 8obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
8obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o 9obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
9obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o 10obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig
index b8913df4cfa2..19659de1c4e8 100644
--- a/arch/arm/mach-mxs/devices/Kconfig
+++ b/arch/arm/mach-mxs/devices/Kconfig
@@ -1,6 +1,5 @@
1config MXS_HAVE_AMBA_DUART 1config MXS_HAVE_AMBA_DUART
2 bool 2 bool
3 select ARM_AMBA
4 3
5config MXS_HAVE_PLATFORM_AUART 4config MXS_HAVE_PLATFORM_AUART
6 bool 5 bool
diff --git a/arch/arm/mach-mxs/devices/platform-dma.c b/arch/arm/mach-mxs/devices/platform-dma.c
index 6a0202b1016c..46824501de00 100644
--- a/arch/arm/mach-mxs/devices/platform-dma.c
+++ b/arch/arm/mach-mxs/devices/platform-dma.c
@@ -14,7 +14,7 @@
14#include <mach/mx28.h> 14#include <mach/mx28.h>
15#include <mach/devices-common.h> 15#include <mach/devices-common.h>
16 16
17static struct platform_device *__init mxs_add_dma(const char *devid, 17struct platform_device *__init mxs_add_dma(const char *devid,
18 resource_size_t base) 18 resource_size_t base)
19{ 19{
20 struct resource res[] = { 20 struct resource res[] = {
@@ -29,22 +29,3 @@ static struct platform_device *__init mxs_add_dma(const char *devid,
29 res, ARRAY_SIZE(res), NULL, 0, 29 res, ARRAY_SIZE(res), NULL, 0,
30 DMA_BIT_MASK(32)); 30 DMA_BIT_MASK(32));
31} 31}
32
33static int __init mxs_add_mxs_dma(void)
34{
35 char *apbh = "mxs-dma-apbh";
36 char *apbx = "mxs-dma-apbx";
37
38 if (cpu_is_mx23()) {
39 mxs_add_dma(apbh, MX23_APBH_DMA_BASE_ADDR);
40 mxs_add_dma(apbx, MX23_APBX_DMA_BASE_ADDR);
41 }
42
43 if (cpu_is_mx28()) {
44 mxs_add_dma(apbh, MX28_APBH_DMA_BASE_ADDR);
45 mxs_add_dma(apbx, MX28_APBX_DMA_BASE_ADDR);
46 }
47
48 return 0;
49}
50arch_initcall(mxs_add_mxs_dma);
diff --git a/arch/arm/mach-mxs/devices/platform-gpio-mxs.c b/arch/arm/mach-mxs/devices/platform-gpio-mxs.c
index ed0885e414e0..cd99f19ec637 100644
--- a/arch/arm/mach-mxs/devices/platform-gpio-mxs.c
+++ b/arch/arm/mach-mxs/devices/platform-gpio-mxs.c
@@ -14,7 +14,7 @@
14#include <mach/devices-common.h> 14#include <mach/devices-common.h>
15 15
16struct platform_device *__init mxs_add_gpio( 16struct platform_device *__init mxs_add_gpio(
17 int id, resource_size_t iobase, int irq) 17 char *name, int id, resource_size_t iobase, int irq)
18{ 18{
19 struct resource res[] = { 19 struct resource res[] = {
20 { 20 {
@@ -29,25 +29,5 @@ struct platform_device *__init mxs_add_gpio(
29 }; 29 };
30 30
31 return platform_device_register_resndata(&mxs_apbh_bus, 31 return platform_device_register_resndata(&mxs_apbh_bus,
32 "gpio-mxs", id, res, ARRAY_SIZE(res), NULL, 0); 32 name, id, res, ARRAY_SIZE(res), NULL, 0);
33} 33}
34
35static int __init mxs_add_mxs_gpio(void)
36{
37 if (cpu_is_mx23()) {
38 mxs_add_gpio(0, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO0);
39 mxs_add_gpio(1, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO1);
40 mxs_add_gpio(2, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO2);
41 }
42
43 if (cpu_is_mx28()) {
44 mxs_add_gpio(0, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO0);
45 mxs_add_gpio(1, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO1);
46 mxs_add_gpio(2, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO2);
47 mxs_add_gpio(3, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO3);
48 mxs_add_gpio(4, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO4);
49 }
50
51 return 0;
52}
53postcore_initcall(mxs_add_mxs_gpio);
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-mmc.c b/arch/arm/mach-mxs/devices/platform-mxs-mmc.c
index bef9d923f54e..b33c9d05c552 100644
--- a/arch/arm/mach-mxs/devices/platform-mxs-mmc.c
+++ b/arch/arm/mach-mxs/devices/platform-mxs-mmc.c
@@ -17,8 +17,9 @@
17#include <mach/mx28.h> 17#include <mach/mx28.h>
18#include <mach/devices-common.h> 18#include <mach/devices-common.h>
19 19
20#define mxs_mxs_mmc_data_entry_single(soc, _id, hwid) \ 20#define mxs_mxs_mmc_data_entry_single(soc, _devid, _id, hwid) \
21 { \ 21 { \
22 .devid = _devid, \
22 .id = _id, \ 23 .id = _id, \
23 .iobase = soc ## _SSP ## hwid ## _BASE_ADDR, \ 24 .iobase = soc ## _SSP ## hwid ## _BASE_ADDR, \
24 .dma = soc ## _DMA_SSP ## hwid, \ 25 .dma = soc ## _DMA_SSP ## hwid, \
@@ -26,23 +27,23 @@
26 .irq_dma = soc ## _INT_SSP ## hwid ## _DMA, \ 27 .irq_dma = soc ## _INT_SSP ## hwid ## _DMA, \
27 } 28 }
28 29
29#define mxs_mxs_mmc_data_entry(soc, _id, hwid) \ 30#define mxs_mxs_mmc_data_entry(soc, _devid, _id, hwid) \
30 [_id] = mxs_mxs_mmc_data_entry_single(soc, _id, hwid) 31 [_id] = mxs_mxs_mmc_data_entry_single(soc, _devid, _id, hwid)
31 32
32 33
33#ifdef CONFIG_SOC_IMX23 34#ifdef CONFIG_SOC_IMX23
34const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst = { 35const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst = {
35 mxs_mxs_mmc_data_entry(MX23, 0, 1), 36 mxs_mxs_mmc_data_entry(MX23, "imx23-mmc", 0, 1),
36 mxs_mxs_mmc_data_entry(MX23, 1, 2), 37 mxs_mxs_mmc_data_entry(MX23, "imx23-mmc", 1, 2),
37}; 38};
38#endif 39#endif
39 40
40#ifdef CONFIG_SOC_IMX28 41#ifdef CONFIG_SOC_IMX28
41const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst = { 42const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst = {
42 mxs_mxs_mmc_data_entry(MX28, 0, 0), 43 mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 0, 0),
43 mxs_mxs_mmc_data_entry(MX28, 1, 1), 44 mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 1, 1),
44 mxs_mxs_mmc_data_entry(MX28, 2, 2), 45 mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 2, 2),
45 mxs_mxs_mmc_data_entry(MX28, 3, 3), 46 mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 3, 3),
46}; 47};
47#endif 48#endif
48 49
@@ -70,6 +71,6 @@ struct platform_device *__init mxs_add_mxs_mmc(
70 }, 71 },
71 }; 72 };
72 73
73 return mxs_add_platform_device("mxs-mmc", data->id, 74 return mxs_add_platform_device(data->devid, data->id,
74 res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); 75 res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
75} 76}
diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h
index 84af61cf6a62..de6c7ba42544 100644
--- a/arch/arm/mach-mxs/include/mach/common.h
+++ b/arch/arm/mach-mxs/include/mach/common.h
@@ -18,17 +18,20 @@ extern void mxs_restart(char, const char *);
18extern int mxs_saif_clkmux_select(unsigned int clkmux); 18extern int mxs_saif_clkmux_select(unsigned int clkmux);
19 19
20extern void mx23_soc_init(void); 20extern void mx23_soc_init(void);
21extern int mx23_register_gpios(void);
22extern int mx23_clocks_init(void); 21extern int mx23_clocks_init(void);
23extern void mx23_map_io(void); 22extern void mx23_map_io(void);
24extern void mx23_init_irq(void); 23extern void mx23_init_irq(void);
25 24
26extern void mx28_soc_init(void); 25extern void mx28_soc_init(void);
27extern int mx28_register_gpios(void);
28extern int mx28_clocks_init(void); 26extern int mx28_clocks_init(void);
29extern void mx28_map_io(void); 27extern void mx28_map_io(void);
30extern void mx28_init_irq(void); 28extern void mx28_init_irq(void);
31 29
32extern void icoll_init_irq(void); 30extern void icoll_init_irq(void);
33 31
32extern struct platform_device *mxs_add_dma(const char *devid,
33 resource_size_t base);
34extern struct platform_device *mxs_add_gpio(char *name, int id,
35 resource_size_t iobase, int irq);
36
34#endif /* __MACH_MXS_COMMON_H__ */ 37#endif /* __MACH_MXS_COMMON_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h
index 21e45a70d344..e8b1d958240b 100644
--- a/arch/arm/mach-mxs/include/mach/devices-common.h
+++ b/arch/arm/mach-mxs/include/mach/devices-common.h
@@ -82,8 +82,9 @@ struct platform_device * __init mxs_add_mxs_i2c(
82 const struct mxs_mxs_i2c_data *data); 82 const struct mxs_mxs_i2c_data *data);
83 83
84/* mmc */ 84/* mmc */
85#include <mach/mmc.h> 85#include <linux/mmc/mxs-mmc.h>
86struct mxs_mxs_mmc_data { 86struct mxs_mxs_mmc_data {
87 const char *devid;
87 int id; 88 int id;
88 resource_size_t iobase; 89 resource_size_t iobase;
89 resource_size_t dma; 90 resource_size_t dma;
diff --git a/arch/arm/mach-mxs/include/mach/mmc.h b/arch/arm/mach-mxs/include/mach/mmc.h
deleted file mode 100644
index 211547a05564..000000000000
--- a/arch/arm/mach-mxs/include/mach/mmc.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __MACH_MXS_MMC_H__
10#define __MACH_MXS_MMC_H__
11
12struct mxs_mmc_platform_data {
13 int wp_gpio; /* write protect pin */
14 unsigned int flags;
15#define SLOTF_4_BIT_CAPABLE (1 << 0)
16#define SLOTF_8_BIT_CAPABLE (1 << 1)
17};
18#endif /* __MACH_MXS_MMC_H__ */
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
new file mode 100644
index 000000000000..8cac94b33020
--- /dev/null
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -0,0 +1,121 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2012 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/clk.h>
14#include <linux/clkdev.h>
15#include <linux/err.h>
16#include <linux/init.h>
17#include <linux/init.h>
18#include <linux/irqdomain.h>
19#include <linux/of_irq.h>
20#include <linux/of_platform.h>
21#include <asm/mach/arch.h>
22#include <asm/mach/time.h>
23#include <mach/common.h>
24
25static int __init mxs_icoll_add_irq_domain(struct device_node *np,
26 struct device_node *interrupt_parent)
27{
28 irq_domain_add_legacy(np, 128, 0, 0, &irq_domain_simple_ops, NULL);
29
30 return 0;
31}
32
33static int __init mxs_gpio_add_irq_domain(struct device_node *np,
34 struct device_node *interrupt_parent)
35{
36 static int gpio_irq_base = MXS_GPIO_IRQ_START;
37
38 irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops, NULL);
39 gpio_irq_base += 32;
40
41 return 0;
42}
43
44static const struct of_device_id mxs_irq_match[] __initconst = {
45 { .compatible = "fsl,mxs-icoll", .data = mxs_icoll_add_irq_domain, },
46 { .compatible = "fsl,mxs-gpio", .data = mxs_gpio_add_irq_domain, },
47 { /* sentinel */ }
48};
49
50static void __init mxs_dt_init_irq(void)
51{
52 icoll_init_irq();
53 of_irq_init(mxs_irq_match);
54}
55
56static void __init imx23_timer_init(void)
57{
58 mx23_clocks_init();
59}
60
61static struct sys_timer imx23_timer = {
62 .init = imx23_timer_init,
63};
64
65static void __init imx28_timer_init(void)
66{
67 mx28_clocks_init();
68}
69
70static struct sys_timer imx28_timer = {
71 .init = imx28_timer_init,
72};
73
74static void __init imx28_evk_init(void)
75{
76 struct clk *clk;
77
78 /* Enable fec phy clock */
79 clk = clk_get_sys("enet_out", NULL);
80 if (!IS_ERR(clk))
81 clk_prepare_enable(clk);
82}
83
84static void __init mxs_machine_init(void)
85{
86 if (of_machine_is_compatible("fsl,imx28-evk"))
87 imx28_evk_init();
88
89 of_platform_populate(NULL, of_default_bus_match_table,
90 NULL, NULL);
91}
92
93static const char *imx23_dt_compat[] __initdata = {
94 "fsl,imx23-evk",
95 "fsl,imx23",
96 NULL,
97};
98
99static const char *imx28_dt_compat[] __initdata = {
100 "fsl,imx28-evk",
101 "fsl,imx28",
102 NULL,
103};
104
105DT_MACHINE_START(IMX23, "Freescale i.MX23 (Device Tree)")
106 .map_io = mx23_map_io,
107 .init_irq = mxs_dt_init_irq,
108 .timer = &imx23_timer,
109 .init_machine = mxs_machine_init,
110 .dt_compat = imx23_dt_compat,
111 .restart = mxs_restart,
112MACHINE_END
113
114DT_MACHINE_START(IMX28, "Freescale i.MX28 (Device Tree)")
115 .map_io = mx28_map_io,
116 .init_irq = mxs_dt_init_irq,
117 .timer = &imx28_timer,
118 .init_machine = mxs_machine_init,
119 .dt_compat = imx28_dt_compat,
120 .restart = mxs_restart,
121MACHINE_END
diff --git a/arch/arm/mach-mxs/mm.c b/arch/arm/mach-mxs/mm.c
index 67a384edcf5b..dccb67a9e7c4 100644
--- a/arch/arm/mach-mxs/mm.c
+++ b/arch/arm/mach-mxs/mm.c
@@ -66,9 +66,25 @@ void __init mx28_init_irq(void)
66void __init mx23_soc_init(void) 66void __init mx23_soc_init(void)
67{ 67{
68 pinctrl_provide_dummies(); 68 pinctrl_provide_dummies();
69
70 mxs_add_dma("imx23-dma-apbh", MX23_APBH_DMA_BASE_ADDR);
71 mxs_add_dma("imx23-dma-apbx", MX23_APBX_DMA_BASE_ADDR);
72
73 mxs_add_gpio("imx23-gpio", 0, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO0);
74 mxs_add_gpio("imx23-gpio", 1, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO1);
75 mxs_add_gpio("imx23-gpio", 2, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO2);
69} 76}
70 77
71void __init mx28_soc_init(void) 78void __init mx28_soc_init(void)
72{ 79{
73 pinctrl_provide_dummies(); 80 pinctrl_provide_dummies();
81
82 mxs_add_dma("imx28-dma-apbh", MX23_APBH_DMA_BASE_ADDR);
83 mxs_add_dma("imx28-dma-apbx", MX23_APBX_DMA_BASE_ADDR);
84
85 mxs_add_gpio("imx28-gpio", 0, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO0);
86 mxs_add_gpio("imx28-gpio", 1, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO1);
87 mxs_add_gpio("imx28-gpio", 2, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO2);
88 mxs_add_gpio("imx28-gpio", 3, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO3);
89 mxs_add_gpio("imx28-gpio", 4, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO4);
74} 90}
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index 8ddda365f1a0..761e45f9456f 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -24,6 +24,8 @@
24#define UART_PADDR MX51_UART1_BASE_ADDR 24#define UART_PADDR MX51_UART1_BASE_ADDR
25#elif defined (CONFIG_DEBUG_IMX50_IMX53_UART) 25#elif defined (CONFIG_DEBUG_IMX50_IMX53_UART)
26#define UART_PADDR MX53_UART1_BASE_ADDR 26#define UART_PADDR MX53_UART1_BASE_ADDR
27#elif defined (CONFIG_DEBUG_IMX6Q_UART2)
28#define UART_PADDR MX6Q_UART2_BASE_ADDR
27#elif defined (CONFIG_DEBUG_IMX6Q_UART4) 29#elif defined (CONFIG_DEBUG_IMX6Q_UART4)
28#define UART_PADDR MX6Q_UART4_BASE_ADDR 30#define UART_PADDR MX6Q_UART4_BASE_ADDR
29#endif 31#endif
diff --git a/arch/arm/plat-mxc/include/mach/mx6q.h b/arch/arm/plat-mxc/include/mach/mx6q.h
index 254a561a2799..f7e7dbac8f4b 100644
--- a/arch/arm/plat-mxc/include/mach/mx6q.h
+++ b/arch/arm/plat-mxc/include/mach/mx6q.h
@@ -27,6 +27,8 @@
27#define MX6Q_CCM_SIZE 0x4000 27#define MX6Q_CCM_SIZE 0x4000
28#define MX6Q_ANATOP_BASE_ADDR 0x020c8000 28#define MX6Q_ANATOP_BASE_ADDR 0x020c8000
29#define MX6Q_ANATOP_SIZE 0x1000 29#define MX6Q_ANATOP_SIZE 0x1000
30#define MX6Q_UART2_BASE_ADDR 0x021e8000
31#define MX6Q_UART2_SIZE 0x4000
30#define MX6Q_UART4_BASE_ADDR 0x021f0000 32#define MX6Q_UART4_BASE_ADDR 0x021f0000
31#define MX6Q_UART4_SIZE 0x4000 33#define MX6Q_UART4_SIZE 0x4000
32 34
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-01 15:47:42 -0400