diff options
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-at91/include/mach/at91_adc.h | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91_adc.h b/arch/arm/mach-at91/include/mach/at91_adc.h index 8e7ed5c90817..048a57f76bd3 100644 --- a/arch/arm/mach-at91/include/mach/at91_adc.h +++ b/arch/arm/mach-at91/include/mach/at91_adc.h | |||
| @@ -28,9 +28,12 @@ | |||
| 28 | #define AT91_ADC_TRGSEL_EXTERNAL (6 << 1) | 28 | #define AT91_ADC_TRGSEL_EXTERNAL (6 << 1) |
| 29 | #define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */ | 29 | #define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */ |
| 30 | #define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */ | 30 | #define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */ |
| 31 | #define AT91_ADC_PRESCAL (0x3f << 8) /* Prescalar Rate Selection */ | 31 | #define AT91_ADC_PRESCAL_9260 (0x3f << 8) /* Prescalar Rate Selection */ |
| 32 | #define AT91_ADC_PRESCAL_9G45 (0xff << 8) | ||
| 32 | #define AT91_ADC_PRESCAL_(x) ((x) << 8) | 33 | #define AT91_ADC_PRESCAL_(x) ((x) << 8) |
| 33 | #define AT91_ADC_STARTUP (0x1f << 16) /* Startup Up Time */ | 34 | #define AT91_ADC_STARTUP_9260 (0x1f << 16) /* Startup Up Time */ |
| 35 | #define AT91_ADC_STARTUP_9G45 (0x7f << 16) | ||
| 36 | #define AT91_ADC_STARTUP_9X5 (0xf << 16) | ||
| 34 | #define AT91_ADC_STARTUP_(x) ((x) << 16) | 37 | #define AT91_ADC_STARTUP_(x) ((x) << 16) |
| 35 | #define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */ | 38 | #define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */ |
| 36 | #define AT91_ADC_SHTIM_(x) ((x) << 24) | 39 | #define AT91_ADC_SHTIM_(x) ((x) << 24) |
| @@ -48,6 +51,9 @@ | |||
| 48 | #define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */ | 51 | #define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */ |
| 49 | #define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */ | 52 | #define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */ |
| 50 | 53 | ||
| 54 | #define AT91_ADC_SR_9X5 0x30 /* Status Register for 9x5 */ | ||
| 55 | #define AT91_ADC_SR_DRDY_9X5 (1 << 24) /* Data Ready */ | ||
| 56 | |||
| 51 | #define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */ | 57 | #define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */ |
| 52 | #define AT91_ADC_LDATA (0x3ff) | 58 | #define AT91_ADC_LDATA (0x3ff) |
| 53 | 59 | ||
| @@ -58,4 +64,10 @@ | |||
| 58 | #define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */ | 64 | #define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */ |
| 59 | #define AT91_ADC_DATA (0x3ff) | 65 | #define AT91_ADC_DATA (0x3ff) |
| 60 | 66 | ||
| 67 | #define AT91_ADC_CDR0_9X5 (0x50) /* Channel Data Register 0 for 9X5 */ | ||
| 68 | |||
| 69 | #define AT91_ADC_TRGR_9260 AT91_ADC_MR | ||
| 70 | #define AT91_ADC_TRGR_9G45 0x08 | ||
| 71 | #define AT91_ADC_TRGR_9X5 0xC0 | ||
| 72 | |||
| 61 | #endif | 73 | #endif |