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-rw-r--r--arch/arm/mach-iop33x/irq.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c
index 675ed3989973..3c720551ac12 100644
--- a/arch/arm/mach-iop33x/irq.c
+++ b/arch/arm/mach-iop33x/irq.c
@@ -57,6 +57,20 @@ static inline void intstr_write1(u32 val)
57 iop3xx_cp6_disable(); 57 iop3xx_cp6_disable();
58} 58}
59 59
60static inline void intbase_write(u32 val)
61{
62 iop3xx_cp6_enable();
63 asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val));
64 iop3xx_cp6_disable();
65}
66
67static inline void intsize_write(u32 val)
68{
69 iop3xx_cp6_enable();
70 asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val));
71 iop3xx_cp6_disable();
72}
73
60static void 74static void
61iop331_irq_mask1 (unsigned int irq) 75iop331_irq_mask1 (unsigned int irq)
62{ 76{
@@ -107,6 +121,8 @@ void __init iop331_init_irq(void)
107 intctl_write1(0); 121 intctl_write1(0);
108 intstr_write0(0); // treat all as IRQ 122 intstr_write0(0); // treat all as IRQ
109 intstr_write1(0); 123 intstr_write1(0);
124 intbase_write(0);
125 intsize_write(1);
110 if(machine_is_iq80331()) // all interrupts are inputs to chip 126 if(machine_is_iq80331()) // all interrupts are inputs to chip
111 *IOP3XX_PCIIRSR = 0x0f; 127 *IOP3XX_PCIIRSR = 0x0f;
112 128