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-rw-r--r--arch/arm/boot/compressed/head.S2
-rw-r--r--arch/arm/include/asm/highmem.h15
-rw-r--r--arch/arm/include/asm/kmap_types.h1
-rw-r--r--arch/arm/include/asm/ucontext.h23
-rw-r--r--arch/arm/include/asm/user.h12
-rw-r--r--arch/arm/kernel/signal.c93
-rw-r--r--arch/arm/mach-at91/Makefile4
-rw-r--r--arch/arm/mach-at91/pm_slowclock.S16
-rw-r--r--arch/arm/mach-bcmring/dma.c13
-rw-r--r--arch/arm/mach-ep93xx/gpio.c6
-rw-r--r--arch/arm/mach-mx3/Kconfig10
-rw-r--r--arch/arm/mach-mx3/clock-imx31.c5
-rw-r--r--arch/arm/mach-mx3/devices.c19
-rw-r--r--arch/arm/mach-mx3/devices.h3
-rw-r--r--arch/arm/mach-mx3/mach-armadillo5x0.c166
-rw-r--r--arch/arm/mach-mx3/mach-mx31_3ds.c116
-rw-r--r--arch/arm/mach-mx3/mach-pcm037.c1
-rw-r--r--arch/arm/mach-mx3/mx31lite-db.c2
-rw-r--r--arch/arm/mach-mx5/clock-mx51.c2
-rw-r--r--arch/arm/mach-mx5/cpu.c53
-rw-r--r--arch/arm/mach-mx5/mm.c32
-rw-r--r--arch/arm/mm/copypage-v6.c9
-rw-r--r--arch/arm/mm/dma-mapping.c5
-rw-r--r--arch/arm/mm/flush.c25
-rw-r--r--arch/arm/mm/highmem.c87
-rw-r--r--arch/arm/mm/mmu.c14
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31_3ds.h (renamed from arch/arm/plat-mxc/include/mach/board-mx31pdk.h)6
-rw-r--r--arch/arm/plat-mxc/include/mach/mx51.h33
-rw-r--r--arch/arm/plat-mxc/include/mach/uncompress.h4
-rw-r--r--arch/arm/vfp/vfpmodule.c31
30 files changed, 663 insertions, 145 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 0f23009170a1..6ab6b337a913 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -172,7 +172,7 @@ not_angel:
172 adr r0, LC0 172 adr r0, LC0
173 ARM( ldmia r0, {r1, r2, r3, r4, r5, r6, r11, ip, sp}) 173 ARM( ldmia r0, {r1, r2, r3, r4, r5, r6, r11, ip, sp})
174 THUMB( ldmia r0, {r1, r2, r3, r4, r5, r6, r11, ip} ) 174 THUMB( ldmia r0, {r1, r2, r3, r4, r5, r6, r11, ip} )
175 THUMB( ldr sp, [r0, #28] ) 175 THUMB( ldr sp, [r0, #32] )
176 subs r0, r0, r1 @ calculate the delta offset 176 subs r0, r0, r1 @ calculate the delta offset
177 177
178 @ if delta is zero, we are 178 @ if delta is zero, we are
diff --git a/arch/arm/include/asm/highmem.h b/arch/arm/include/asm/highmem.h
index 7f36d00600b4..feb988a7ec37 100644
--- a/arch/arm/include/asm/highmem.h
+++ b/arch/arm/include/asm/highmem.h
@@ -11,7 +11,11 @@
11 11
12#define kmap_prot PAGE_KERNEL 12#define kmap_prot PAGE_KERNEL
13 13
14#define flush_cache_kmaps() flush_cache_all() 14#define flush_cache_kmaps() \
15 do { \
16 if (cache_is_vivt()) \
17 flush_cache_all(); \
18 } while (0)
15 19
16extern pte_t *pkmap_page_table; 20extern pte_t *pkmap_page_table;
17 21
@@ -21,11 +25,20 @@ extern void *kmap_high(struct page *page);
21extern void *kmap_high_get(struct page *page); 25extern void *kmap_high_get(struct page *page);
22extern void kunmap_high(struct page *page); 26extern void kunmap_high(struct page *page);
23 27
28extern void *kmap_high_l1_vipt(struct page *page, pte_t *saved_pte);
29extern void kunmap_high_l1_vipt(struct page *page, pte_t saved_pte);
30
31/*
32 * The following functions are already defined by <linux/highmem.h>
33 * when CONFIG_HIGHMEM is not set.
34 */
35#ifdef CONFIG_HIGHMEM
24extern void *kmap(struct page *page); 36extern void *kmap(struct page *page);
25extern void kunmap(struct page *page); 37extern void kunmap(struct page *page);
26extern void *kmap_atomic(struct page *page, enum km_type type); 38extern void *kmap_atomic(struct page *page, enum km_type type);
27extern void kunmap_atomic(void *kvaddr, enum km_type type); 39extern void kunmap_atomic(void *kvaddr, enum km_type type);
28extern void *kmap_atomic_pfn(unsigned long pfn, enum km_type type); 40extern void *kmap_atomic_pfn(unsigned long pfn, enum km_type type);
29extern struct page *kmap_atomic_to_page(const void *ptr); 41extern struct page *kmap_atomic_to_page(const void *ptr);
42#endif
30 43
31#endif 44#endif
diff --git a/arch/arm/include/asm/kmap_types.h b/arch/arm/include/asm/kmap_types.h
index c019949a5189..c4b2ea3fbe42 100644
--- a/arch/arm/include/asm/kmap_types.h
+++ b/arch/arm/include/asm/kmap_types.h
@@ -18,6 +18,7 @@ enum km_type {
18 KM_IRQ1, 18 KM_IRQ1,
19 KM_SOFTIRQ0, 19 KM_SOFTIRQ0,
20 KM_SOFTIRQ1, 20 KM_SOFTIRQ1,
21 KM_L1_CACHE,
21 KM_L2_CACHE, 22 KM_L2_CACHE,
22 KM_TYPE_NR 23 KM_TYPE_NR
23}; 24};
diff --git a/arch/arm/include/asm/ucontext.h b/arch/arm/include/asm/ucontext.h
index bf65e9f4525d..47f023aa8495 100644
--- a/arch/arm/include/asm/ucontext.h
+++ b/arch/arm/include/asm/ucontext.h
@@ -59,23 +59,22 @@ struct iwmmxt_sigframe {
59#endif /* CONFIG_IWMMXT */ 59#endif /* CONFIG_IWMMXT */
60 60
61#ifdef CONFIG_VFP 61#ifdef CONFIG_VFP
62#if __LINUX_ARM_ARCH__ < 6
63/* For ARM pre-v6, we use fstmiax and fldmiax. This adds one extra
64 * word after the registers, and a word of padding at the end for
65 * alignment. */
66#define VFP_MAGIC 0x56465001 62#define VFP_MAGIC 0x56465001
67#define VFP_STORAGE_SIZE 152
68#else
69#define VFP_MAGIC 0x56465002
70#define VFP_STORAGE_SIZE 144
71#endif
72 63
73struct vfp_sigframe 64struct vfp_sigframe
74{ 65{
75 unsigned long magic; 66 unsigned long magic;
76 unsigned long size; 67 unsigned long size;
77 union vfp_state storage; 68 struct user_vfp ufp;
78}; 69 struct user_vfp_exc ufp_exc;
70} __attribute__((__aligned__(8)));
71
72/*
73 * 8 byte for magic and size, 264 byte for ufp, 12 bytes for ufp_exc,
74 * 4 bytes padding.
75 */
76#define VFP_STORAGE_SIZE sizeof(struct vfp_sigframe)
77
79#endif /* CONFIG_VFP */ 78#endif /* CONFIG_VFP */
80 79
81/* 80/*
@@ -91,7 +90,7 @@ struct aux_sigframe {
91#ifdef CONFIG_IWMMXT 90#ifdef CONFIG_IWMMXT
92 struct iwmmxt_sigframe iwmmxt; 91 struct iwmmxt_sigframe iwmmxt;
93#endif 92#endif
94#if 0 && defined CONFIG_VFP /* Not yet saved. */ 93#ifdef CONFIG_VFP
95 struct vfp_sigframe vfp; 94 struct vfp_sigframe vfp;
96#endif 95#endif
97 /* Something that isn't a valid magic number for any coprocessor. */ 96 /* Something that isn't a valid magic number for any coprocessor. */
diff --git a/arch/arm/include/asm/user.h b/arch/arm/include/asm/user.h
index df95e050f9dd..05ac4b06876a 100644
--- a/arch/arm/include/asm/user.h
+++ b/arch/arm/include/asm/user.h
@@ -83,11 +83,21 @@ struct user{
83 83
84/* 84/*
85 * User specific VFP registers. If only VFPv2 is present, registers 16 to 31 85 * User specific VFP registers. If only VFPv2 is present, registers 16 to 31
86 * are ignored by the ptrace system call. 86 * are ignored by the ptrace system call and the signal handler.
87 */ 87 */
88struct user_vfp { 88struct user_vfp {
89 unsigned long long fpregs[32]; 89 unsigned long long fpregs[32];
90 unsigned long fpscr; 90 unsigned long fpscr;
91}; 91};
92 92
93/*
94 * VFP exception registers exposed to user space during signal delivery.
95 * Fields not relavant to the current VFP architecture are ignored.
96 */
97struct user_vfp_exc {
98 unsigned long fpexc;
99 unsigned long fpinst;
100 unsigned long fpinst2;
101};
102
93#endif /* _ARM_USER_H */ 103#endif /* _ARM_USER_H */
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index e7714f367eb8..907d5a620bca 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -18,6 +18,7 @@
18#include <asm/cacheflush.h> 18#include <asm/cacheflush.h>
19#include <asm/ucontext.h> 19#include <asm/ucontext.h>
20#include <asm/unistd.h> 20#include <asm/unistd.h>
21#include <asm/vfp.h>
21 22
22#include "ptrace.h" 23#include "ptrace.h"
23#include "signal.h" 24#include "signal.h"
@@ -175,6 +176,90 @@ static int restore_iwmmxt_context(struct iwmmxt_sigframe *frame)
175 176
176#endif 177#endif
177 178
179#ifdef CONFIG_VFP
180
181static int preserve_vfp_context(struct vfp_sigframe __user *frame)
182{
183 struct thread_info *thread = current_thread_info();
184 struct vfp_hard_struct *h = &thread->vfpstate.hard;
185 const unsigned long magic = VFP_MAGIC;
186 const unsigned long size = VFP_STORAGE_SIZE;
187 int err = 0;
188
189 vfp_sync_hwstate(thread);
190 __put_user_error(magic, &frame->magic, err);
191 __put_user_error(size, &frame->size, err);
192
193 /*
194 * Copy the floating point registers. There can be unused
195 * registers see asm/hwcap.h for details.
196 */
197 err |= __copy_to_user(&frame->ufp.fpregs, &h->fpregs,
198 sizeof(h->fpregs));
199 /*
200 * Copy the status and control register.
201 */
202 __put_user_error(h->fpscr, &frame->ufp.fpscr, err);
203
204 /*
205 * Copy the exception registers.
206 */
207 __put_user_error(h->fpexc, &frame->ufp_exc.fpexc, err);
208 __put_user_error(h->fpinst, &frame->ufp_exc.fpinst, err);
209 __put_user_error(h->fpinst2, &frame->ufp_exc.fpinst2, err);
210
211 return err ? -EFAULT : 0;
212}
213
214static int restore_vfp_context(struct vfp_sigframe __user *frame)
215{
216 struct thread_info *thread = current_thread_info();
217 struct vfp_hard_struct *h = &thread->vfpstate.hard;
218 unsigned long magic;
219 unsigned long size;
220 unsigned long fpexc;
221 int err = 0;
222
223 __get_user_error(magic, &frame->magic, err);
224 __get_user_error(size, &frame->size, err);
225
226 if (err)
227 return -EFAULT;
228 if (magic != VFP_MAGIC || size != VFP_STORAGE_SIZE)
229 return -EINVAL;
230
231 /*
232 * Copy the floating point registers. There can be unused
233 * registers see asm/hwcap.h for details.
234 */
235 err |= __copy_from_user(&h->fpregs, &frame->ufp.fpregs,
236 sizeof(h->fpregs));
237 /*
238 * Copy the status and control register.
239 */
240 __get_user_error(h->fpscr, &frame->ufp.fpscr, err);
241
242 /*
243 * Sanitise and restore the exception registers.
244 */
245 __get_user_error(fpexc, &frame->ufp_exc.fpexc, err);
246 /* Ensure the VFP is enabled. */
247 fpexc |= FPEXC_EN;
248 /* Ensure FPINST2 is invalid and the exception flag is cleared. */
249 fpexc &= ~(FPEXC_EX | FPEXC_FP2V);
250 h->fpexc = fpexc;
251
252 __get_user_error(h->fpinst, &frame->ufp_exc.fpinst, err);
253 __get_user_error(h->fpinst2, &frame->ufp_exc.fpinst2, err);
254
255 if (!err)
256 vfp_flush_hwstate(thread);
257
258 return err ? -EFAULT : 0;
259}
260
261#endif
262
178/* 263/*
179 * Do a signal return; undo the signal stack. These are aligned to 64-bit. 264 * Do a signal return; undo the signal stack. These are aligned to 64-bit.
180 */ 265 */
@@ -233,8 +318,8 @@ static int restore_sigframe(struct pt_regs *regs, struct sigframe __user *sf)
233 err |= restore_iwmmxt_context(&aux->iwmmxt); 318 err |= restore_iwmmxt_context(&aux->iwmmxt);
234#endif 319#endif
235#ifdef CONFIG_VFP 320#ifdef CONFIG_VFP
236// if (err == 0) 321 if (err == 0)
237// err |= vfp_restore_state(&sf->aux.vfp); 322 err |= restore_vfp_context(&aux->vfp);
238#endif 323#endif
239 324
240 return err; 325 return err;
@@ -348,8 +433,8 @@ setup_sigframe(struct sigframe __user *sf, struct pt_regs *regs, sigset_t *set)
348 err |= preserve_iwmmxt_context(&aux->iwmmxt); 433 err |= preserve_iwmmxt_context(&aux->iwmmxt);
349#endif 434#endif
350#ifdef CONFIG_VFP 435#ifdef CONFIG_VFP
351// if (err == 0) 436 if (err == 0)
352// err |= vfp_save_state(&sf->aux.vfp); 437 err |= preserve_vfp_context(&aux->vfp);
353#endif 438#endif
354 __put_user_error(0, &aux->end_magic, err); 439 __put_user_error(0, &aux->end_magic, err);
355 440
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 027dd570dcc3..d4004557532a 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -16,8 +16,8 @@ obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_d
16obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o 16obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
17obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o 17obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o
18obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o 18obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
19obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o 19obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
20 obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o 20obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
21obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o 21obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
22obj-$(CONFIG_ARCH_AT572D940HF) += at572d940hf.o at91sam926x_time.o at572d940hf_devices.o sam9_smc.o 22obj-$(CONFIG_ARCH_AT572D940HF) += at572d940hf.o at91sam926x_time.o at572d940hf_devices.o sam9_smc.o
23obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o 23obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 987fab3d846a..9c5b48e68a71 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -175,8 +175,6 @@ ENTRY(at91_slow_clock)
175 orr r3, r3, #(1 << 29) /* bit 29 always set */ 175 orr r3, r3, #(1 << 29) /* bit 29 always set */
176 str r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)] 176 str r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)]
177 177
178 wait_pllalock
179
180 /* Save PLLB setting and disable it */ 178 /* Save PLLB setting and disable it */
181 ldr r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)] 179 ldr r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)]
182 str r3, .saved_pllbr 180 str r3, .saved_pllbr
@@ -184,8 +182,6 @@ ENTRY(at91_slow_clock)
184 mov r3, #AT91_PMC_PLLCOUNT 182 mov r3, #AT91_PMC_PLLCOUNT
185 str r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)] 183 str r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)]
186 184
187 wait_pllblock
188
189 /* Turn off the main oscillator */ 185 /* Turn off the main oscillator */
190 ldr r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)] 186 ldr r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
191 bic r3, r3, #AT91_PMC_MOSCEN 187 bic r3, r3, #AT91_PMC_MOSCEN
@@ -205,13 +201,25 @@ ENTRY(at91_slow_clock)
205 ldr r3, .saved_pllbr 201 ldr r3, .saved_pllbr
206 str r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)] 202 str r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)]
207 203
204 tst r3, #(AT91_PMC_MUL & 0xff0000)
205 bne 1f
206 tst r3, #(AT91_PMC_MUL & ~0xff0000)
207 beq 2f
2081:
208 wait_pllblock 209 wait_pllblock
2102:
209 211
210 /* Restore PLLA setting */ 212 /* Restore PLLA setting */
211 ldr r3, .saved_pllar 213 ldr r3, .saved_pllar
212 str r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)] 214 str r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)]
213 215
216 tst r3, #(AT91_PMC_MUL & 0xff0000)
217 bne 3f
218 tst r3, #(AT91_PMC_MUL & ~0xff0000)
219 beq 4f
2203:
214 wait_pllalock 221 wait_pllalock
2224:
215 223
216#ifdef SLOWDOWN_MASTER_CLOCK 224#ifdef SLOWDOWN_MASTER_CLOCK
217 /* 225 /*
diff --git a/arch/arm/mach-bcmring/dma.c b/arch/arm/mach-bcmring/dma.c
index 2ccf670ce1ac..29c0a911df26 100644
--- a/arch/arm/mach-bcmring/dma.c
+++ b/arch/arm/mach-bcmring/dma.c
@@ -2221,11 +2221,15 @@ EXPORT_SYMBOL(dma_map_create_descriptor_ring);
2221int dma_unmap(DMA_MemMap_t *memMap, /* Stores state information about the map */ 2221int dma_unmap(DMA_MemMap_t *memMap, /* Stores state information about the map */
2222 int dirtied /* non-zero if any of the pages were modified */ 2222 int dirtied /* non-zero if any of the pages were modified */
2223 ) { 2223 ) {
2224
2225 int rc = 0;
2224 int regionIdx; 2226 int regionIdx;
2225 int segmentIdx; 2227 int segmentIdx;
2226 DMA_Region_t *region; 2228 DMA_Region_t *region;
2227 DMA_Segment_t *segment; 2229 DMA_Segment_t *segment;
2228 2230
2231 down(&memMap->lock);
2232
2229 for (regionIdx = 0; regionIdx < memMap->numRegionsUsed; regionIdx++) { 2233 for (regionIdx = 0; regionIdx < memMap->numRegionsUsed; regionIdx++) {
2230 region = &memMap->region[regionIdx]; 2234 region = &memMap->region[regionIdx];
2231 2235
@@ -2239,7 +2243,8 @@ int dma_unmap(DMA_MemMap_t *memMap, /* Stores state information about the map */
2239 printk(KERN_ERR 2243 printk(KERN_ERR
2240 "%s: vmalloc'd pages are not yet supported\n", 2244 "%s: vmalloc'd pages are not yet supported\n",
2241 __func__); 2245 __func__);
2242 return -EINVAL; 2246 rc = -EINVAL;
2247 goto out;
2243 } 2248 }
2244 2249
2245 case DMA_MEM_TYPE_KMALLOC: 2250 case DMA_MEM_TYPE_KMALLOC:
@@ -2276,7 +2281,8 @@ int dma_unmap(DMA_MemMap_t *memMap, /* Stores state information about the map */
2276 printk(KERN_ERR 2281 printk(KERN_ERR
2277 "%s: Unsupported memory type: %d\n", 2282 "%s: Unsupported memory type: %d\n",
2278 __func__, region->memType); 2283 __func__, region->memType);
2279 return -EINVAL; 2284 rc = -EINVAL;
2285 goto out;
2280 } 2286 }
2281 } 2287 }
2282 2288
@@ -2314,9 +2320,10 @@ int dma_unmap(DMA_MemMap_t *memMap, /* Stores state information about the map */
2314 memMap->numRegionsUsed = 0; 2320 memMap->numRegionsUsed = 0;
2315 memMap->inUse = 0; 2321 memMap->inUse = 0;
2316 2322
2323out:
2317 up(&memMap->lock); 2324 up(&memMap->lock);
2318 2325
2319 return 0; 2326 return rc;
2320} 2327}
2321 2328
2322EXPORT_SYMBOL(dma_unmap); 2329EXPORT_SYMBOL(dma_unmap);
diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c
index cc377ae8c428..cf547ad7ebd4 100644
--- a/arch/arm/mach-ep93xx/gpio.c
+++ b/arch/arm/mach-ep93xx/gpio.c
@@ -25,7 +25,7 @@
25#include <mach/hardware.h> 25#include <mach/hardware.h>
26 26
27/************************************************************************* 27/*************************************************************************
28 * GPIO handling for EP93xx 28 * Interrupt handling for EP93xx on-chip GPIOs
29 *************************************************************************/ 29 *************************************************************************/
30static unsigned char gpio_int_unmasked[3]; 30static unsigned char gpio_int_unmasked[3];
31static unsigned char gpio_int_enabled[3]; 31static unsigned char gpio_int_enabled[3];
@@ -40,7 +40,7 @@ static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
40static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 }; 40static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
41static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 }; 41static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
42 42
43void ep93xx_gpio_update_int_params(unsigned port) 43static void ep93xx_gpio_update_int_params(unsigned port)
44{ 44{
45 BUG_ON(port > 2); 45 BUG_ON(port > 2);
46 46
@@ -56,7 +56,7 @@ void ep93xx_gpio_update_int_params(unsigned port)
56 EP93XX_GPIO_REG(int_en_register_offset[port])); 56 EP93XX_GPIO_REG(int_en_register_offset[port]));
57} 57}
58 58
59void ep93xx_gpio_int_mask(unsigned line) 59static inline void ep93xx_gpio_int_mask(unsigned line)
60{ 60{
61 gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7)); 61 gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
62} 62}
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 3872af1cf2c3..170f68e46dd5 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -62,6 +62,15 @@ config MACH_MX31_3DS
62 Include support for MX31PDK (3DS) platform. This includes specific 62 Include support for MX31PDK (3DS) platform. This includes specific
63 configurations for the board and its peripherals. 63 configurations for the board and its peripherals.
64 64
65config MACH_MX31_3DS_MXC_NAND_USE_BBT
66 bool "Make the MXC NAND driver use the in flash Bad Block Table"
67 depends on MACH_MX31_3DS
68 depends on MTD_NAND_MXC
69 help
70 Enable this if you want that the MXC NAND driver uses the in flash
71 Bad Block Table to know what blocks are bad instead of scanning the
72 entire flash looking for bad block markers.
73
65config MACH_MX31MOBOARD 74config MACH_MX31MOBOARD
66 bool "Support mx31moboard platforms (EPFL Mobots group)" 75 bool "Support mx31moboard platforms (EPFL Mobots group)"
67 select ARCH_MX31 76 select ARCH_MX31
@@ -95,6 +104,7 @@ config MACH_PCM043
95config MACH_ARMADILLO5X0 104config MACH_ARMADILLO5X0
96 bool "Support Atmark Armadillo-500 Development Base Board" 105 bool "Support Atmark Armadillo-500 Development Base Board"
97 select ARCH_MX31 106 select ARCH_MX31
107 select MXC_ULPI if USB_ULPI
98 help 108 help
99 Include support for Atmark Armadillo-500 platform. This includes 109 Include support for Atmark Armadillo-500 platform. This includes
100 specific configurations for the board and its peripherals. 110 specific configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mx3/clock-imx31.c b/arch/arm/mach-mx3/clock-imx31.c
index 80dba9966b5e..9a9eb6de6127 100644
--- a/arch/arm/mach-mx3/clock-imx31.c
+++ b/arch/arm/mach-mx3/clock-imx31.c
@@ -468,6 +468,7 @@ static struct clk ahb_clk = {
468 } 468 }
469 469
470DEFINE_CLOCK(perclk_clk, 0, NULL, 0, NULL, NULL, &ipg_clk); 470DEFINE_CLOCK(perclk_clk, 0, NULL, 0, NULL, NULL, &ipg_clk);
471DEFINE_CLOCK(ckil_clk, 0, NULL, 0, clk_ckil_get_rate, NULL, NULL);
471 472
472DEFINE_CLOCK(sdhc1_clk, 0, MXC_CCM_CGR0, 0, NULL, NULL, &perclk_clk); 473DEFINE_CLOCK(sdhc1_clk, 0, MXC_CCM_CGR0, 0, NULL, NULL, &perclk_clk);
473DEFINE_CLOCK(sdhc2_clk, 1, MXC_CCM_CGR0, 2, NULL, NULL, &perclk_clk); 474DEFINE_CLOCK(sdhc2_clk, 1, MXC_CCM_CGR0, 2, NULL, NULL, &perclk_clk);
@@ -490,7 +491,7 @@ DEFINE_CLOCK(mpeg4_clk, 0, MXC_CCM_CGR1, 0, NULL, NULL, &ahb_clk);
490DEFINE_CLOCK(mstick1_clk, 0, MXC_CCM_CGR1, 2, mstick1_get_rate, NULL, &usb_pll_clk); 491DEFINE_CLOCK(mstick1_clk, 0, MXC_CCM_CGR1, 2, mstick1_get_rate, NULL, &usb_pll_clk);
491DEFINE_CLOCK(mstick2_clk, 1, MXC_CCM_CGR1, 4, mstick2_get_rate, NULL, &usb_pll_clk); 492DEFINE_CLOCK(mstick2_clk, 1, MXC_CCM_CGR1, 4, mstick2_get_rate, NULL, &usb_pll_clk);
492DEFINE_CLOCK1(csi_clk, 0, MXC_CCM_CGR1, 6, csi, NULL, &serial_pll_clk); 493DEFINE_CLOCK1(csi_clk, 0, MXC_CCM_CGR1, 6, csi, NULL, &serial_pll_clk);
493DEFINE_CLOCK(rtc_clk, 0, MXC_CCM_CGR1, 8, NULL, NULL, &ipg_clk); 494DEFINE_CLOCK(rtc_clk, 0, MXC_CCM_CGR1, 8, NULL, NULL, &ckil_clk);
494DEFINE_CLOCK(wdog_clk, 0, MXC_CCM_CGR1, 10, NULL, NULL, &ipg_clk); 495DEFINE_CLOCK(wdog_clk, 0, MXC_CCM_CGR1, 10, NULL, NULL, &ipg_clk);
495DEFINE_CLOCK(pwm_clk, 0, MXC_CCM_CGR1, 12, NULL, NULL, &perclk_clk); 496DEFINE_CLOCK(pwm_clk, 0, MXC_CCM_CGR1, 12, NULL, NULL, &perclk_clk);
496DEFINE_CLOCK(usb_clk2, 0, MXC_CCM_CGR1, 18, usb_get_rate, NULL, &ahb_clk); 497DEFINE_CLOCK(usb_clk2, 0, MXC_CCM_CGR1, 18, usb_get_rate, NULL, &ahb_clk);
@@ -514,7 +515,6 @@ DEFINE_CLOCK(usb_clk1, 0, NULL, 0, usb_get_rate, NULL, &usb_pll_clk)
514DEFINE_CLOCK(nfc_clk, 0, NULL, 0, nfc_get_rate, NULL, &ahb_clk); 515DEFINE_CLOCK(nfc_clk, 0, NULL, 0, nfc_get_rate, NULL, &ahb_clk);
515DEFINE_CLOCK(scc_clk, 0, NULL, 0, NULL, NULL, &ipg_clk); 516DEFINE_CLOCK(scc_clk, 0, NULL, 0, NULL, NULL, &ipg_clk);
516DEFINE_CLOCK(ipg_clk, 0, NULL, 0, ipg_get_rate, NULL, &ahb_clk); 517DEFINE_CLOCK(ipg_clk, 0, NULL, 0, ipg_get_rate, NULL, &ahb_clk);
517DEFINE_CLOCK(ckil_clk, 0, NULL, 0, clk_ckil_get_rate, NULL, NULL);
518 518
519#define _REGISTER_CLOCK(d, n, c) \ 519#define _REGISTER_CLOCK(d, n, c) \
520 { \ 520 { \
@@ -572,7 +572,6 @@ static struct clk_lookup lookups[] = {
572 _REGISTER_CLOCK(NULL, "iim", iim_clk) 572 _REGISTER_CLOCK(NULL, "iim", iim_clk)
573 _REGISTER_CLOCK(NULL, "mpeg4", mpeg4_clk) 573 _REGISTER_CLOCK(NULL, "mpeg4", mpeg4_clk)
574 _REGISTER_CLOCK(NULL, "mbx", mbx_clk) 574 _REGISTER_CLOCK(NULL, "mbx", mbx_clk)
575 _REGISTER_CLOCK("mxc_rtc", NULL, ckil_clk)
576}; 575};
577 576
578int __init mx31_clocks_init(unsigned long fref) 577int __init mx31_clocks_init(unsigned long fref)
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index 6adb586515ea..f8911154a9fa 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -575,11 +575,26 @@ struct platform_device imx_ssi_device1 = {
575 .resource = imx_ssi_resources1, 575 .resource = imx_ssi_resources1,
576}; 576};
577 577
578static int mx3_devices_init(void) 578static struct resource imx_wdt_resources[] = {
579 {
580 .flags = IORESOURCE_MEM,
581 },
582};
583
584struct platform_device imx_wdt_device0 = {
585 .name = "imx-wdt",
586 .id = 0,
587 .num_resources = ARRAY_SIZE(imx_wdt_resources),
588 .resource = imx_wdt_resources,
589};
590
591static int __init mx3_devices_init(void)
579{ 592{
580 if (cpu_is_mx31()) { 593 if (cpu_is_mx31()) {
581 mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR; 594 mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR;
582 mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff; 595 mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff;
596 imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR;
597 imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff;
583 mxc_register_device(&mxc_rnga_device, NULL); 598 mxc_register_device(&mxc_rnga_device, NULL);
584 } 599 }
585 if (cpu_is_mx35()) { 600 if (cpu_is_mx35()) {
@@ -597,6 +612,8 @@ static int mx3_devices_init(void)
597 imx_ssi_resources0[1].end = MX35_INT_SSI1; 612 imx_ssi_resources0[1].end = MX35_INT_SSI1;
598 imx_ssi_resources1[1].start = MX35_INT_SSI2; 613 imx_ssi_resources1[1].start = MX35_INT_SSI2;
599 imx_ssi_resources1[1].end = MX35_INT_SSI2; 614 imx_ssi_resources1[1].end = MX35_INT_SSI2;
615 imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR;
616 imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff;
600 } 617 }
601 618
602 return 0; 619 return 0;
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index 42cf175eac6b..4f77eb501274 100644
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -25,4 +25,5 @@ extern struct platform_device mxc_spi_device1;
25extern struct platform_device mxc_spi_device2; 25extern struct platform_device mxc_spi_device2;
26extern struct platform_device imx_ssi_device0; 26extern struct platform_device imx_ssi_device0;
27extern struct platform_device imx_ssi_device1; 27extern struct platform_device imx_ssi_device1;
28 28extern struct platform_device imx_ssi_device1;
29extern struct platform_device imx_wdt_device0;
diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c
index 3d72b0b89705..5f72ec91af2d 100644
--- a/arch/arm/mach-mx3/mach-armadillo5x0.c
+++ b/arch/arm/mach-mx3/mach-armadillo5x0.c
@@ -36,6 +36,9 @@
36#include <linux/input.h> 36#include <linux/input.h>
37#include <linux/gpio_keys.h> 37#include <linux/gpio_keys.h>
38#include <linux/i2c.h> 38#include <linux/i2c.h>
39#include <linux/usb/otg.h>
40#include <linux/usb/ulpi.h>
41#include <linux/delay.h>
39 42
40#include <mach/hardware.h> 43#include <mach/hardware.h>
41#include <asm/mach-types.h> 44#include <asm/mach-types.h>
@@ -52,6 +55,8 @@
52#include <mach/ipu.h> 55#include <mach/ipu.h>
53#include <mach/mx3fb.h> 56#include <mach/mx3fb.h>
54#include <mach/mxc_nand.h> 57#include <mach/mxc_nand.h>
58#include <mach/mxc_ehci.h>
59#include <mach/ulpi.h>
55 60
56#include "devices.h" 61#include "devices.h"
57#include "crm_regs.h" 62#include "crm_regs.h"
@@ -103,8 +108,158 @@ static int armadillo5x0_pins[] = {
103 /* I2C2 */ 108 /* I2C2 */
104 MX31_PIN_CSPI2_MOSI__SCL, 109 MX31_PIN_CSPI2_MOSI__SCL,
105 MX31_PIN_CSPI2_MISO__SDA, 110 MX31_PIN_CSPI2_MISO__SDA,
111 /* OTG */
112 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
113 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
114 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
115 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
116 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
117 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
118 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
119 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
120 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
121 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
122 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
123 MX31_PIN_USBOTG_STP__USBOTG_STP,
124 /* USB host 2 */
125 IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
126 IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
127 IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
128 IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
129 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
130 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
131 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC),
132 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC),
133 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC),
134 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC),
135 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC),
136 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC),
106}; 137};
107 138
139/* USB */
140#if defined(CONFIG_USB_ULPI)
141
142#define OTG_RESET IOMUX_TO_GPIO(MX31_PIN_STXD4)
143#define USBH2_RESET IOMUX_TO_GPIO(MX31_PIN_SCK6)
144#define USBH2_CS IOMUX_TO_GPIO(MX31_PIN_GPIO1_3)
145
146#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
147 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
148
149static int usbotg_init(struct platform_device *pdev)
150{
151 int err;
152
153 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
154 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
155 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
156 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
157 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
158 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
159 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
160 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
161 mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
162 mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
163 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
164 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
165
166 /* Chip already enabled by hardware */
167 /* OTG phy reset*/
168 err = gpio_request(OTG_RESET, "USB-OTG-RESET");
169 if (err) {
170 pr_err("Failed to request the usb otg reset gpio\n");
171 return err;
172 }
173
174 err = gpio_direction_output(OTG_RESET, 1/*HIGH*/);
175 if (err) {
176 pr_err("Failed to reset the usb otg phy\n");
177 goto otg_free_reset;
178 }
179
180 gpio_set_value(OTG_RESET, 0/*LOW*/);
181 mdelay(5);
182 gpio_set_value(OTG_RESET, 1/*HIGH*/);
183
184 return 0;
185
186otg_free_reset:
187 gpio_free(OTG_RESET);
188 return err;
189}
190
191static int usbh2_init(struct platform_device *pdev)
192{
193 int err;
194
195 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
196 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
197 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
198 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
199 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
200 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
201 mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
202 mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
203 mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
204 mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
205 mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
206 mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
207
208 mxc_iomux_set_gpr(MUX_PGP_UH2, true);
209
210
211 /* Enable the chip */
212 err = gpio_request(USBH2_CS, "USB-H2-CS");
213 if (err) {
214 pr_err("Failed to request the usb host 2 CS gpio\n");
215 return err;
216 }
217
218 err = gpio_direction_output(USBH2_CS, 0/*Enabled*/);
219 if (err) {
220 pr_err("Failed to drive the usb host 2 CS gpio\n");
221 goto h2_free_cs;
222 }
223
224 /* H2 phy reset*/
225 err = gpio_request(USBH2_RESET, "USB-H2-RESET");
226 if (err) {
227 pr_err("Failed to request the usb host 2 reset gpio\n");
228 goto h2_free_cs;
229 }
230
231 err = gpio_direction_output(USBH2_RESET, 1/*HIGH*/);
232 if (err) {
233 pr_err("Failed to reset the usb host 2 phy\n");
234 goto h2_free_reset;
235 }
236
237 gpio_set_value(USBH2_RESET, 0/*LOW*/);
238 mdelay(5);
239 gpio_set_value(USBH2_RESET, 1/*HIGH*/);
240
241 return 0;
242
243h2_free_reset:
244 gpio_free(USBH2_RESET);
245h2_free_cs:
246 gpio_free(USBH2_CS);
247 return err;
248}
249
250static struct mxc_usbh_platform_data usbotg_pdata = {
251 .init = usbotg_init,
252 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
253 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
254};
255
256static struct mxc_usbh_platform_data usbh2_pdata = {
257 .init = usbh2_init,
258 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
259 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
260};
261#endif /* CONFIG_USB_ULPI */
262
108/* RTC over I2C*/ 263/* RTC over I2C*/
109#define ARMADILLO5X0_RTC_GPIO IOMUX_TO_GPIO(MX31_PIN_SRXD4) 264#define ARMADILLO5X0_RTC_GPIO IOMUX_TO_GPIO(MX31_PIN_SRXD4)
110 265
@@ -393,6 +548,17 @@ static void __init armadillo5x0_init(void)
393 if (armadillo5x0_i2c_rtc.irq == 0) 548 if (armadillo5x0_i2c_rtc.irq == 0)
394 pr_warning("armadillo5x0_init: failed to get RTC IRQ\n"); 549 pr_warning("armadillo5x0_init: failed to get RTC IRQ\n");
395 i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1); 550 i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1);
551
552 /* USB */
553#if defined(CONFIG_USB_ULPI)
554 usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
555 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
556 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
557 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
558
559 mxc_register_device(&mxc_otg_host, &usbotg_pdata);
560 mxc_register_device(&mxc_usbh2, &usbh2_pdata);
561#endif
396} 562}
397 563
398static void __init armadillo5x0_timer_init(void) 564static void __init armadillo5x0_timer_init(void)
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index b88c18ad7698..f54af1e29ca4 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -23,6 +23,9 @@
23#include <linux/gpio.h> 23#include <linux/gpio.h>
24#include <linux/smsc911x.h> 24#include <linux/smsc911x.h>
25#include <linux/platform_device.h> 25#include <linux/platform_device.h>
26#include <linux/mfd/mc13783.h>
27#include <linux/spi/spi.h>
28#include <linux/regulator/machine.h>
26 29
27#include <mach/hardware.h> 30#include <mach/hardware.h>
28#include <asm/mach-types.h> 31#include <asm/mach-types.h>
@@ -31,26 +34,96 @@
31#include <asm/memory.h> 34#include <asm/memory.h>
32#include <asm/mach/map.h> 35#include <asm/mach/map.h>
33#include <mach/common.h> 36#include <mach/common.h>
34#include <mach/board-mx31pdk.h> 37#include <mach/board-mx31_3ds.h>
35#include <mach/imx-uart.h> 38#include <mach/imx-uart.h>
36#include <mach/iomux-mx3.h> 39#include <mach/iomux-mx3.h>
40#include <mach/mxc_nand.h>
41#include <mach/spi.h>
37#include "devices.h" 42#include "devices.h"
38 43
39/*! 44/*!
40 * @file mx31pdk.c 45 * @file mx31_3ds.c
41 * 46 *
42 * @brief This file contains the board-specific initialization routines. 47 * @brief This file contains the board-specific initialization routines.
43 * 48 *
44 * @ingroup System 49 * @ingroup System
45 */ 50 */
46 51
47static int mx31pdk_pins[] = { 52static int mx31_3ds_pins[] = {
48 /* UART1 */ 53 /* UART1 */
49 MX31_PIN_CTS1__CTS1, 54 MX31_PIN_CTS1__CTS1,
50 MX31_PIN_RTS1__RTS1, 55 MX31_PIN_RTS1__RTS1,
51 MX31_PIN_TXD1__TXD1, 56 MX31_PIN_TXD1__TXD1,
52 MX31_PIN_RXD1__RXD1, 57 MX31_PIN_RXD1__RXD1,
53 IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO), 58 IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
59 /* SPI 1 */
60 MX31_PIN_CSPI2_SCLK__SCLK,
61 MX31_PIN_CSPI2_MOSI__MOSI,
62 MX31_PIN_CSPI2_MISO__MISO,
63 MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
64 MX31_PIN_CSPI2_SS0__SS0,
65 MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
66 /* MC13783 IRQ */
67 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
68};
69
70/* Regulators */
71static struct regulator_init_data pwgtx_init = {
72 .constraints = {
73 .boot_on = 1,
74 .always_on = 1,
75 },
76};
77
78static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
79 {
80 .id = MC13783_REGU_PWGT1SPI, /* Power Gate for ARM core. */
81 .init_data = &pwgtx_init,
82 }, {
83 .id = MC13783_REGU_PWGT2SPI, /* Power Gate for L2 Cache. */
84 .init_data = &pwgtx_init,
85 },
86};
87
88/* MC13783 */
89static struct mc13783_platform_data mc13783_pdata __initdata = {
90 .regulators = mx31_3ds_regulators,
91 .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
92 .flags = MC13783_USE_REGULATOR,
93};
94
95/* SPI */
96static int spi1_internal_chipselect[] = {
97 MXC_SPI_CS(0),
98 MXC_SPI_CS(2),
99};
100
101static struct spi_imx_master spi1_pdata = {
102 .chipselect = spi1_internal_chipselect,
103 .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
104};
105
106static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
107 {
108 .modalias = "mc13783",
109 .max_speed_hz = 1000000,
110 .bus_num = 1,
111 .chip_select = 1, /* SS2 */
112 .platform_data = &mc13783_pdata,
113 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
114 .mode = SPI_CS_HIGH,
115 },
116};
117
118/*
119 * NAND Flash
120 */
121static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = {
122 .width = 1,
123 .hw_ecc = 1,
124#ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
125 .flash_bbt = 1,
126#endif
54}; 127};
55 128
56static struct imxuart_platform_data uart_pdata = { 129static struct imxuart_platform_data uart_pdata = {
@@ -95,7 +168,7 @@ static struct platform_device smsc911x_device = {
95 * LEDs, switches, interrupts for Ethernet. 168 * LEDs, switches, interrupts for Ethernet.
96 */ 169 */
97 170
98static void mx31pdk_expio_irq_handler(uint32_t irq, struct irq_desc *desc) 171static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
99{ 172{
100 uint32_t imr_val; 173 uint32_t imr_val;
101 uint32_t int_valid; 174 uint32_t int_valid;
@@ -163,7 +236,7 @@ static struct irq_chip expio_irq_chip = {
163 .unmask = expio_unmask_irq, 236 .unmask = expio_unmask_irq,
164}; 237};
165 238
166static int __init mx31pdk_init_expio(void) 239static int __init mx31_3ds_init_expio(void)
167{ 240{
168 int i; 241 int i;
169 int ret; 242 int ret;
@@ -176,7 +249,7 @@ static int __init mx31pdk_init_expio(void)
176 return -ENODEV; 249 return -ENODEV;
177 } 250 }
178 251
179 pr_info("i.MX31PDK Debug board detected, rev = 0x%04X\n", 252 pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n",
180 __raw_readw(CPLD_CODE_VER_REG)); 253 __raw_readw(CPLD_CODE_VER_REG));
181 254
182 /* 255 /*
@@ -201,7 +274,7 @@ static int __init mx31pdk_init_expio(void)
201 set_irq_flags(i, IRQF_VALID); 274 set_irq_flags(i, IRQF_VALID);
202 } 275 }
203 set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW); 276 set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW);
204 set_irq_chained_handler(EXPIO_PARENT_INT, mx31pdk_expio_irq_handler); 277 set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler);
205 278
206 return 0; 279 return 0;
207} 280}
@@ -209,7 +282,7 @@ static int __init mx31pdk_init_expio(void)
209/* 282/*
210 * This structure defines the MX31 memory map. 283 * This structure defines the MX31 memory map.
211 */ 284 */
212static struct map_desc mx31pdk_io_desc[] __initdata = { 285static struct map_desc mx31_3ds_io_desc[] __initdata = {
213 { 286 {
214 .virtual = MX31_CS5_BASE_ADDR_VIRT, 287 .virtual = MX31_CS5_BASE_ADDR_VIRT,
215 .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR), 288 .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
@@ -221,10 +294,10 @@ static struct map_desc mx31pdk_io_desc[] __initdata = {
221/* 294/*
222 * Set up static virtual mappings. 295 * Set up static virtual mappings.
223 */ 296 */
224static void __init mx31pdk_map_io(void) 297static void __init mx31_3ds_map_io(void)
225{ 298{
226 mx31_map_io(); 299 mx31_map_io();
227 iotable_init(mx31pdk_io_desc, ARRAY_SIZE(mx31pdk_io_desc)); 300 iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc));
228} 301}
229 302
230/*! 303/*!
@@ -232,35 +305,40 @@ static void __init mx31pdk_map_io(void)
232 */ 305 */
233static void __init mxc_board_init(void) 306static void __init mxc_board_init(void)
234{ 307{
235 mxc_iomux_setup_multiple_pins(mx31pdk_pins, ARRAY_SIZE(mx31pdk_pins), 308 mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
236 "mx31pdk"); 309 "mx31_3ds");
237 310
238 mxc_register_device(&mxc_uart_device0, &uart_pdata); 311 mxc_register_device(&mxc_uart_device0, &uart_pdata);
312 mxc_register_device(&mxc_nand_device, &imx31_3ds_nand_flash_pdata);
313
314 mxc_register_device(&mxc_spi_device1, &spi1_pdata);
315 spi_register_board_info(mx31_3ds_spi_devs,
316 ARRAY_SIZE(mx31_3ds_spi_devs));
239 317
240 if (!mx31pdk_init_expio()) 318 if (!mx31_3ds_init_expio())
241 platform_device_register(&smsc911x_device); 319 platform_device_register(&smsc911x_device);
242} 320}
243 321
244static void __init mx31pdk_timer_init(void) 322static void __init mx31_3ds_timer_init(void)
245{ 323{
246 mx31_clocks_init(26000000); 324 mx31_clocks_init(26000000);
247} 325}
248 326
249static struct sys_timer mx31pdk_timer = { 327static struct sys_timer mx31_3ds_timer = {
250 .init = mx31pdk_timer_init, 328 .init = mx31_3ds_timer_init,
251}; 329};
252 330
253/* 331/*
254 * The following uses standard kernel macros defined in arch.h in order to 332 * The following uses standard kernel macros defined in arch.h in order to
255 * initialize __mach_desc_MX31PDK data structure. 333 * initialize __mach_desc_MX31_3DS data structure.
256 */ 334 */
257MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") 335MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
258 /* Maintainer: Freescale Semiconductor, Inc. */ 336 /* Maintainer: Freescale Semiconductor, Inc. */
259 .phys_io = MX31_AIPS1_BASE_ADDR, 337 .phys_io = MX31_AIPS1_BASE_ADDR,
260 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, 338 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
261 .boot_params = MX3x_PHYS_OFFSET + 0x100, 339 .boot_params = MX3x_PHYS_OFFSET + 0x100,
262 .map_io = mx31pdk_map_io, 340 .map_io = mx31_3ds_map_io,
263 .init_irq = mx31_init_irq, 341 .init_irq = mx31_init_irq,
264 .init_machine = mxc_board_init, 342 .init_machine = mxc_board_init,
265 .timer = &mx31pdk_timer, 343 .timer = &mx31_3ds_timer,
266MACHINE_END 344MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c
index 034ec8190065..2df1ec55a97e 100644
--- a/arch/arm/mach-mx3/mach-pcm037.c
+++ b/arch/arm/mach-mx3/mach-pcm037.c
@@ -35,7 +35,6 @@
35#include <linux/can/platform/sja1000.h> 35#include <linux/can/platform/sja1000.h>
36#include <linux/usb/otg.h> 36#include <linux/usb/otg.h>
37#include <linux/usb/ulpi.h> 37#include <linux/usb/ulpi.h>
38#include <linux/fsl_devices.h>
39#include <linux/gfp.h> 38#include <linux/gfp.h>
40 39
41#include <media/soc_camera.h> 40#include <media/soc_camera.h>
diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c
index ccd874225c3b..093c595ca581 100644
--- a/arch/arm/mach-mx3/mx31lite-db.c
+++ b/arch/arm/mach-mx3/mx31lite-db.c
@@ -28,7 +28,6 @@
28#include <linux/types.h> 28#include <linux/types.h>
29#include <linux/init.h> 29#include <linux/init.h>
30#include <linux/gpio.h> 30#include <linux/gpio.h>
31#include <linux/platform_device.h>
32#include <linux/leds.h> 31#include <linux/leds.h>
33#include <linux/platform_device.h> 32#include <linux/platform_device.h>
34 33
@@ -206,5 +205,6 @@ void __init mx31lite_db_init(void)
206 mxc_register_device(&mxcsdhc_device0, &mmc_pdata); 205 mxc_register_device(&mxcsdhc_device0, &mmc_pdata);
207 mxc_register_device(&mxc_spi_device0, &spi0_pdata); 206 mxc_register_device(&mxc_spi_device0, &spi0_pdata);
208 platform_device_register(&litekit_led_device); 207 platform_device_register(&litekit_led_device);
208 mxc_register_device(&imx_wdt_device0, NULL);
209} 209}
210 210
diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
index be90c03101cd..8f85f73b83a8 100644
--- a/arch/arm/mach-mx5/clock-mx51.c
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -757,7 +757,7 @@ DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,
757 757
758/* GPT */ 758/* GPT */
759DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET, 759DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
760 NULL, NULL, &ipg_perclk, NULL); 760 NULL, NULL, &ipg_clk, NULL);
761DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET, 761DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
762 NULL, NULL, &ipg_clk, NULL); 762 NULL, NULL, &ipg_clk, NULL);
763 763
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index 41c769f08c4d..2d37785e3857 100644
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -14,9 +14,62 @@
14#include <linux/types.h> 14#include <linux/types.h>
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/module.h>
17#include <mach/hardware.h> 18#include <mach/hardware.h>
18#include <asm/io.h> 19#include <asm/io.h>
19 20
21static int cpu_silicon_rev = -1;
22
23#define SI_REV 0x48
24
25static void query_silicon_parameter(void)
26{
27 void __iomem *rom = ioremap(MX51_IROM_BASE_ADDR, MX51_IROM_SIZE);
28 u32 rev;
29
30 if (!rom) {
31 cpu_silicon_rev = -EINVAL;
32 return;
33 }
34
35 rev = readl(rom + SI_REV);
36 switch (rev) {
37 case 0x1:
38 cpu_silicon_rev = MX51_CHIP_REV_1_0;
39 break;
40 case 0x2:
41 cpu_silicon_rev = MX51_CHIP_REV_1_1;
42 break;
43 case 0x10:
44 cpu_silicon_rev = MX51_CHIP_REV_2_0;
45 break;
46 case 0x20:
47 cpu_silicon_rev = MX51_CHIP_REV_3_0;
48 break;
49 default:
50 cpu_silicon_rev = 0;
51 }
52
53 iounmap(rom);
54}
55
56/*
57 * Returns:
58 * the silicon revision of the cpu
59 * -EINVAL - not a mx51
60 */
61int mx51_revision(void)
62{
63 if (!cpu_is_mx51())
64 return -EINVAL;
65
66 if (cpu_silicon_rev == -1)
67 query_silicon_parameter();
68
69 return cpu_silicon_rev;
70}
71EXPORT_SYMBOL(mx51_revision);
72
20static int __init post_cpu_init(void) 73static int __init post_cpu_init(void)
21{ 74{
22 unsigned int reg; 75 unsigned int reg;
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
index c21e18be7af8..b7677ef80cc4 100644
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-mx5/mm.c
@@ -35,11 +35,6 @@ static struct map_desc mxc_io_desc[] __initdata = {
35 .length = MX51_DEBUG_SIZE, 35 .length = MX51_DEBUG_SIZE,
36 .type = MT_DEVICE 36 .type = MT_DEVICE
37 }, { 37 }, {
38 .virtual = MX51_TZIC_BASE_ADDR_VIRT,
39 .pfn = __phys_to_pfn(MX51_TZIC_BASE_ADDR),
40 .length = MX51_TZIC_SIZE,
41 .type = MT_DEVICE
42 }, {
43 .virtual = MX51_AIPS1_BASE_ADDR_VIRT, 38 .virtual = MX51_AIPS1_BASE_ADDR_VIRT,
44 .pfn = __phys_to_pfn(MX51_AIPS1_BASE_ADDR), 39 .pfn = __phys_to_pfn(MX51_AIPS1_BASE_ADDR),
45 .length = MX51_AIPS1_SIZE, 40 .length = MX51_AIPS1_SIZE,
@@ -54,11 +49,6 @@ static struct map_desc mxc_io_desc[] __initdata = {
54 .pfn = __phys_to_pfn(MX51_AIPS2_BASE_ADDR), 49 .pfn = __phys_to_pfn(MX51_AIPS2_BASE_ADDR),
55 .length = MX51_AIPS2_SIZE, 50 .length = MX51_AIPS2_SIZE,
56 .type = MT_DEVICE 51 .type = MT_DEVICE
57 }, {
58 .virtual = MX51_NFC_AXI_BASE_ADDR_VIRT,
59 .pfn = __phys_to_pfn(MX51_NFC_AXI_BASE_ADDR),
60 .length = MX51_NFC_AXI_SIZE,
61 .type = MT_DEVICE
62 }, 52 },
63}; 53};
64 54
@@ -69,14 +59,6 @@ static struct map_desc mxc_io_desc[] __initdata = {
69 */ 59 */
70void __init mx51_map_io(void) 60void __init mx51_map_io(void)
71{ 61{
72 u32 tzic_addr;
73
74 if (mx51_revision() < MX51_CHIP_REV_2_0)
75 tzic_addr = 0x8FFFC000;
76 else
77 tzic_addr = 0xE0003000;
78 mxc_io_desc[2].pfn = __phys_to_pfn(tzic_addr);
79
80 mxc_set_cpu_type(MXC_CPU_MX51); 62 mxc_set_cpu_type(MXC_CPU_MX51);
81 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); 63 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
82 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG_BASE_ADDR)); 64 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG_BASE_ADDR));
@@ -85,5 +67,17 @@ void __init mx51_map_io(void)
85 67
86void __init mx51_init_irq(void) 68void __init mx51_init_irq(void)
87{ 69{
88 tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR)); 70 unsigned long tzic_addr;
71 void __iomem *tzic_virt;
72
73 if (mx51_revision() < MX51_CHIP_REV_2_0)
74 tzic_addr = MX51_TZIC_BASE_ADDR_TO1;
75 else
76 tzic_addr = MX51_TZIC_BASE_ADDR;
77
78 tzic_virt = ioremap(tzic_addr, SZ_16K);
79 if (!tzic_virt)
80 panic("unable to map TZIC interrupt controller\n");
81
82 tzic_init_irq(tzic_virt);
89} 83}
diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c
index 8bca4dea6dfa..f55fa1044f72 100644
--- a/arch/arm/mm/copypage-v6.c
+++ b/arch/arm/mm/copypage-v6.c
@@ -41,14 +41,7 @@ static void v6_copy_user_highpage_nonaliasing(struct page *to,
41 kfrom = kmap_atomic(from, KM_USER0); 41 kfrom = kmap_atomic(from, KM_USER0);
42 kto = kmap_atomic(to, KM_USER1); 42 kto = kmap_atomic(to, KM_USER1);
43 copy_page(kto, kfrom); 43 copy_page(kto, kfrom);
44#ifdef CONFIG_HIGHMEM 44 __cpuc_flush_dcache_area(kto, PAGE_SIZE);
45 /*
46 * kmap_atomic() doesn't set the page virtual address, and
47 * kunmap_atomic() takes care of cache flushing already.
48 */
49 if (page_address(to) != NULL)
50#endif
51 __cpuc_flush_dcache_area(kto, PAGE_SIZE);
52 kunmap_atomic(kto, KM_USER1); 45 kunmap_atomic(kto, KM_USER1);
53 kunmap_atomic(kfrom, KM_USER0); 46 kunmap_atomic(kfrom, KM_USER0);
54} 47}
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 1351edc0b26f..13fa536d82e6 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -464,6 +464,11 @@ static void dma_cache_maint_page(struct page *page, unsigned long offset,
464 vaddr += offset; 464 vaddr += offset;
465 op(vaddr, len, dir); 465 op(vaddr, len, dir);
466 kunmap_high(page); 466 kunmap_high(page);
467 } else if (cache_is_vipt()) {
468 pte_t saved_pte;
469 vaddr = kmap_high_l1_vipt(page, &saved_pte);
470 op(vaddr + offset, len, dir);
471 kunmap_high_l1_vipt(page, saved_pte);
467 } 472 }
468 } else { 473 } else {
469 vaddr = page_address(page) + offset; 474 vaddr = page_address(page) + offset;
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index e34f095e2090..c6844cb9b508 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -13,6 +13,7 @@
13 13
14#include <asm/cacheflush.h> 14#include <asm/cacheflush.h>
15#include <asm/cachetype.h> 15#include <asm/cachetype.h>
16#include <asm/highmem.h>
16#include <asm/smp_plat.h> 17#include <asm/smp_plat.h>
17#include <asm/system.h> 18#include <asm/system.h>
18#include <asm/tlbflush.h> 19#include <asm/tlbflush.h>
@@ -152,21 +153,25 @@ void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
152 153
153void __flush_dcache_page(struct address_space *mapping, struct page *page) 154void __flush_dcache_page(struct address_space *mapping, struct page *page)
154{ 155{
155 void *addr = page_address(page);
156
157 /* 156 /*
158 * Writeback any data associated with the kernel mapping of this 157 * Writeback any data associated with the kernel mapping of this
159 * page. This ensures that data in the physical page is mutually 158 * page. This ensures that data in the physical page is mutually
160 * coherent with the kernels mapping. 159 * coherent with the kernels mapping.
161 */ 160 */
162#ifdef CONFIG_HIGHMEM 161 if (!PageHighMem(page)) {
163 /* 162 __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
164 * kmap_atomic() doesn't set the page virtual address, and 163 } else {
165 * kunmap_atomic() takes care of cache flushing already. 164 void *addr = kmap_high_get(page);
166 */ 165 if (addr) {
167 if (addr) 166 __cpuc_flush_dcache_area(addr, PAGE_SIZE);
168#endif 167 kunmap_high(page);
169 __cpuc_flush_dcache_area(addr, PAGE_SIZE); 168 } else if (cache_is_vipt()) {
169 pte_t saved_pte;
170 addr = kmap_high_l1_vipt(page, &saved_pte);
171 __cpuc_flush_dcache_area(addr, PAGE_SIZE);
172 kunmap_high_l1_vipt(page, saved_pte);
173 }
174 }
170 175
171 /* 176 /*
172 * If this is a page cache page, and we have an aliasing VIPT cache, 177 * If this is a page cache page, and we have an aliasing VIPT cache,
diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c
index 2be1ec7c1b41..77b030f5ec09 100644
--- a/arch/arm/mm/highmem.c
+++ b/arch/arm/mm/highmem.c
@@ -79,7 +79,8 @@ void kunmap_atomic(void *kvaddr, enum km_type type)
79 unsigned int idx = type + KM_TYPE_NR * smp_processor_id(); 79 unsigned int idx = type + KM_TYPE_NR * smp_processor_id();
80 80
81 if (kvaddr >= (void *)FIXADDR_START) { 81 if (kvaddr >= (void *)FIXADDR_START) {
82 __cpuc_flush_dcache_area((void *)vaddr, PAGE_SIZE); 82 if (cache_is_vivt())
83 __cpuc_flush_dcache_area((void *)vaddr, PAGE_SIZE);
83#ifdef CONFIG_DEBUG_HIGHMEM 84#ifdef CONFIG_DEBUG_HIGHMEM
84 BUG_ON(vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx)); 85 BUG_ON(vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx));
85 set_pte_ext(TOP_PTE(vaddr), __pte(0), 0); 86 set_pte_ext(TOP_PTE(vaddr), __pte(0), 0);
@@ -124,3 +125,87 @@ struct page *kmap_atomic_to_page(const void *ptr)
124 pte = TOP_PTE(vaddr); 125 pte = TOP_PTE(vaddr);
125 return pte_page(*pte); 126 return pte_page(*pte);
126} 127}
128
129#ifdef CONFIG_CPU_CACHE_VIPT
130
131#include <linux/percpu.h>
132
133/*
134 * The VIVT cache of a highmem page is always flushed before the page
135 * is unmapped. Hence unmapped highmem pages need no cache maintenance
136 * in that case.
137 *
138 * However unmapped pages may still be cached with a VIPT cache, and
139 * it is not possible to perform cache maintenance on them using physical
140 * addresses unfortunately. So we have no choice but to set up a temporary
141 * virtual mapping for that purpose.
142 *
143 * Yet this VIPT cache maintenance may be triggered from DMA support
144 * functions which are possibly called from interrupt context. As we don't
145 * want to keep interrupt disabled all the time when such maintenance is
146 * taking place, we therefore allow for some reentrancy by preserving and
147 * restoring the previous fixmap entry before the interrupted context is
148 * resumed. If the reentrancy depth is 0 then there is no need to restore
149 * the previous fixmap, and leaving the current one in place allow it to
150 * be reused the next time without a TLB flush (common with DMA).
151 */
152
153static DEFINE_PER_CPU(int, kmap_high_l1_vipt_depth);
154
155void *kmap_high_l1_vipt(struct page *page, pte_t *saved_pte)
156{
157 unsigned int idx, cpu = smp_processor_id();
158 int *depth = &per_cpu(kmap_high_l1_vipt_depth, cpu);
159 unsigned long vaddr, flags;
160 pte_t pte, *ptep;
161
162 idx = KM_L1_CACHE + KM_TYPE_NR * cpu;
163 vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
164 ptep = TOP_PTE(vaddr);
165 pte = mk_pte(page, kmap_prot);
166
167 if (!in_interrupt())
168 preempt_disable();
169
170 raw_local_irq_save(flags);
171 (*depth)++;
172 if (pte_val(*ptep) == pte_val(pte)) {
173 *saved_pte = pte;
174 } else {
175 *saved_pte = *ptep;
176 set_pte_ext(ptep, pte, 0);
177 local_flush_tlb_kernel_page(vaddr);
178 }
179 raw_local_irq_restore(flags);
180
181 return (void *)vaddr;
182}
183
184void kunmap_high_l1_vipt(struct page *page, pte_t saved_pte)
185{
186 unsigned int idx, cpu = smp_processor_id();
187 int *depth = &per_cpu(kmap_high_l1_vipt_depth, cpu);
188 unsigned long vaddr, flags;
189 pte_t pte, *ptep;
190
191 idx = KM_L1_CACHE + KM_TYPE_NR * cpu;
192 vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
193 ptep = TOP_PTE(vaddr);
194 pte = mk_pte(page, kmap_prot);
195
196 BUG_ON(pte_val(*ptep) != pte_val(pte));
197 BUG_ON(*depth <= 0);
198
199 raw_local_irq_save(flags);
200 (*depth)--;
201 if (*depth != 0 && pte_val(pte) != pte_val(saved_pte)) {
202 set_pte_ext(ptep, saved_pte, 0);
203 local_flush_tlb_kernel_page(vaddr);
204 }
205 raw_local_irq_restore(flags);
206
207 if (!in_interrupt())
208 preempt_enable();
209}
210
211#endif /* CONFIG_CPU_CACHE_VIPT */
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 9d4da6ac28eb..241c24a1c18f 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -420,6 +420,10 @@ static void __init build_mem_type_table(void)
420 user_pgprot |= L_PTE_SHARED; 420 user_pgprot |= L_PTE_SHARED;
421 kern_pgprot |= L_PTE_SHARED; 421 kern_pgprot |= L_PTE_SHARED;
422 vecs_pgprot |= L_PTE_SHARED; 422 vecs_pgprot |= L_PTE_SHARED;
423 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
424 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
425 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
426 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
423 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; 427 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
424 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; 428 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
425#endif 429#endif
@@ -1050,10 +1054,12 @@ void setup_mm_for_reboot(char mode)
1050 pgd_t *pgd; 1054 pgd_t *pgd;
1051 int i; 1055 int i;
1052 1056
1053 if (current->mm && current->mm->pgd) 1057 /*
1054 pgd = current->mm->pgd; 1058 * We need to access to user-mode page tables here. For kernel threads
1055 else 1059 * we don't have any user-mode mappings so we use the context that we
1056 pgd = init_mm.pgd; 1060 * "borrowed".
1061 */
1062 pgd = current->active_mm->pgd;
1057 1063
1058 base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT; 1064 base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT;
1059 if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale()) 1065 if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31pdk.h b/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
index 2bbd6ed17f50..da92933a233b 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31pdk.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
@@ -8,8 +8,8 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11#ifndef __ASM_ARCH_MXC_BOARD_MX31PDK_H__ 11#ifndef __ASM_ARCH_MXC_BOARD_MX31_3DS_H__
12#define __ASM_ARCH_MXC_BOARD_MX31PDK_H__ 12#define __ASM_ARCH_MXC_BOARD_MX31_3DS_H__
13 13
14/* Definitions for components on the Debug board */ 14/* Definitions for components on the Debug board */
15 15
@@ -56,4 +56,4 @@
56 56
57#define MXC_MAX_EXP_IO_LINES 16 57#define MXC_MAX_EXP_IO_LINES 16
58 58
59#endif /* __ASM_ARCH_MXC_BOARD_MX31PDK_H__ */ 59#endif /* __ASM_ARCH_MXC_BOARD_MX31_3DS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index 771532b6b4a6..5aad344d5651 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -14,7 +14,7 @@
14 * FB100000 70000000 1M SPBA 0 14 * FB100000 70000000 1M SPBA 0
15 * FB000000 73F00000 1M AIPS 1 15 * FB000000 73F00000 1M AIPS 1
16 * FB200000 83F00000 1M AIPS 2 16 * FB200000 83F00000 1M AIPS 2
17 * FA100000 8FFFC000 16K TZIC (interrupt controller) 17 * 8FFFC000 16K TZIC (interrupt controller)
18 * 90000000 256M CSD0 SDRAM/DDR 18 * 90000000 256M CSD0 SDRAM/DDR
19 * A0000000 256M CSD1 SDRAM/DDR 19 * A0000000 256M CSD1 SDRAM/DDR
20 * B0000000 128M CS0 Flash 20 * B0000000 128M CS0 Flash
@@ -23,11 +23,17 @@
23 * C8000000 64M CS3 Flash 23 * C8000000 64M CS3 Flash
24 * CC000000 32M CS4 SRAM 24 * CC000000 32M CS4 SRAM
25 * CE000000 32M CS5 SRAM 25 * CE000000 32M CS5 SRAM
26 * F9000000 CFFF0000 64K NFC (NAND Flash AXI) 26 * CFFF0000 64K NFC (NAND Flash AXI)
27 * 27 *
28 */ 28 */
29 29
30/* 30/*
31 * IROM
32 */
33#define MX51_IROM_BASE_ADDR 0x0
34#define MX51_IROM_SIZE SZ_64K
35
36/*
31 * IRAM 37 * IRAM
32 */ 38 */
33#define MX51_IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ 39#define MX51_IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
@@ -40,7 +46,6 @@
40 * NFC 46 * NFC
41 */ 47 */
42#define MX51_NFC_AXI_BASE_ADDR 0xCFFF0000 /* NAND flash AXI */ 48#define MX51_NFC_AXI_BASE_ADDR 0xCFFF0000 /* NAND flash AXI */
43#define MX51_NFC_AXI_BASE_ADDR_VIRT 0xF9000000
44#define MX51_NFC_AXI_SIZE SZ_64K 49#define MX51_NFC_AXI_SIZE SZ_64K
45 50
46/* 51/*
@@ -49,9 +54,8 @@
49#define MX51_GPU_BASE_ADDR 0x20000000 54#define MX51_GPU_BASE_ADDR 0x20000000
50#define MX51_GPU2D_BASE_ADDR 0xD0000000 55#define MX51_GPU2D_BASE_ADDR 0xD0000000
51 56
52#define MX51_TZIC_BASE_ADDR 0x8FFFC000 57#define MX51_TZIC_BASE_ADDR_TO1 0x8FFFC000
53#define MX51_TZIC_BASE_ADDR_VIRT 0xFA100000 58#define MX51_TZIC_BASE_ADDR 0xE0000000
54#define MX51_TZIC_SIZE SZ_16K
55 59
56#define MX51_DEBUG_BASE_ADDR 0x60000000 60#define MX51_DEBUG_BASE_ADDR 0x60000000
57#define MX51_DEBUG_BASE_ADDR_VIRT 0xFA200000 61#define MX51_DEBUG_BASE_ADDR_VIRT 0xFA200000
@@ -232,12 +236,10 @@
232#define MX51_IO_ADDRESS(x) \ 236#define MX51_IO_ADDRESS(x) \
233 (void __iomem *) \ 237 (void __iomem *) \
234 (MX51_IS_MODULE(x, IRAM) ? MX51_IRAM_IO_ADDRESS(x) : \ 238 (MX51_IS_MODULE(x, IRAM) ? MX51_IRAM_IO_ADDRESS(x) : \
235 MX51_IS_MODULE(x, TZIC) ? MX51_TZIC_IO_ADDRESS(x) : \
236 MX51_IS_MODULE(x, DEBUG) ? MX51_DEBUG_IO_ADDRESS(x) : \ 239 MX51_IS_MODULE(x, DEBUG) ? MX51_DEBUG_IO_ADDRESS(x) : \
237 MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) : \ 240 MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) : \
238 MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) : \ 241 MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) : \
239 MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \ 242 MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \
240 MX51_IS_MODULE(x, NFC_AXI) ? MX51_NFC_AXI_IO_ADDRESS(x) : \
241 0xDEADBEEF) 243 0xDEADBEEF)
242 244
243/* 245/*
@@ -246,9 +248,6 @@
246#define MX51_IRAM_IO_ADDRESS(x) \ 248#define MX51_IRAM_IO_ADDRESS(x) \
247 (((x) - MX51_IRAM_BASE_ADDR) + MX51_IRAM_BASE_ADDR_VIRT) 249 (((x) - MX51_IRAM_BASE_ADDR) + MX51_IRAM_BASE_ADDR_VIRT)
248 250
249#define MX51_TZIC_IO_ADDRESS(x) \
250 (((x) - MX51_TZIC_BASE_ADDR) + MX51_TZIC_BASE_ADDR_VIRT)
251
252#define MX51_DEBUG_IO_ADDRESS(x) \ 251#define MX51_DEBUG_IO_ADDRESS(x) \
253 (((x) - MX51_DEBUG_BASE_ADDR) + MX51_DEBUG_BASE_ADDR_VIRT) 252 (((x) - MX51_DEBUG_BASE_ADDR) + MX51_DEBUG_BASE_ADDR_VIRT)
254 253
@@ -261,9 +260,6 @@
261#define MX51_AIPS2_IO_ADDRESS(x) \ 260#define MX51_AIPS2_IO_ADDRESS(x) \
262 (((x) - MX51_AIPS2_BASE_ADDR) + MX51_AIPS2_BASE_ADDR_VIRT) 261 (((x) - MX51_AIPS2_BASE_ADDR) + MX51_AIPS2_BASE_ADDR_VIRT)
263 262
264#define MX51_NFC_AXI_IO_ADDRESS(x) \
265 (((x) - MX51_NFC_AXI_BASE_ADDR) + MX51_NFC_AXI_BASE_ADDR_VIRT)
266
267#define MX51_IS_MEM_DEVICE_NONSHARED(x) 0 263#define MX51_IS_MEM_DEVICE_NONSHARED(x) 0
268 264
269/* 265/*
@@ -443,12 +439,7 @@
443 439
444#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) 440#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
445 441
446extern unsigned int system_rev; 442extern int mx51_revision(void);
447
448static inline unsigned int mx51_revision(void)
449{
450 return system_rev;
451}
452#endif 443#endif
453 444
454#endif /* __ASM_ARCH_MXC_MX51_H__ */ 445#endif /* __ASM_ARCH_MXC_MX51_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index 52e476a150ca..b6d3d0fddc48 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -66,6 +66,7 @@ static inline void flush(void)
66#define MX2X_UART1_BASE_ADDR 0x1000a000 66#define MX2X_UART1_BASE_ADDR 0x1000a000
67#define MX3X_UART1_BASE_ADDR 0x43F90000 67#define MX3X_UART1_BASE_ADDR 0x43F90000
68#define MX3X_UART2_BASE_ADDR 0x43F94000 68#define MX3X_UART2_BASE_ADDR 0x43F94000
69#define MX51_UART1_BASE_ADDR 0x73fbc000
69 70
70static __inline__ void __arch_decomp_setup(unsigned long arch_id) 71static __inline__ void __arch_decomp_setup(unsigned long arch_id)
71{ 72{
@@ -101,6 +102,9 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
101 case MACH_TYPE_MAGX_ZN5: 102 case MACH_TYPE_MAGX_ZN5:
102 uart_base = MX3X_UART2_BASE_ADDR; 103 uart_base = MX3X_UART2_BASE_ADDR;
103 break; 104 break;
105 case MACH_TYPE_MX51_BABBAGE:
106 uart_base = MX51_UART1_BASE_ADDR;
107 break;
104 default: 108 default:
105 break; 109 break;
106 } 110 }
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index a420cb949328..315a540c7ce5 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -428,26 +428,6 @@ static void vfp_pm_init(void)
428static inline void vfp_pm_init(void) { } 428static inline void vfp_pm_init(void) { }
429#endif /* CONFIG_PM */ 429#endif /* CONFIG_PM */
430 430
431/*
432 * Synchronise the hardware VFP state of a thread other than current with the
433 * saved one. This function is used by the ptrace mechanism.
434 */
435#ifdef CONFIG_SMP
436void vfp_sync_hwstate(struct thread_info *thread)
437{
438}
439
440void vfp_flush_hwstate(struct thread_info *thread)
441{
442 /*
443 * On SMP systems, the VFP state is automatically saved at every
444 * context switch. We mark the thread VFP state as belonging to a
445 * non-existent CPU so that the saved one will be reloaded when
446 * needed.
447 */
448 thread->vfpstate.hard.cpu = NR_CPUS;
449}
450#else
451void vfp_sync_hwstate(struct thread_info *thread) 431void vfp_sync_hwstate(struct thread_info *thread)
452{ 432{
453 unsigned int cpu = get_cpu(); 433 unsigned int cpu = get_cpu();
@@ -490,9 +470,18 @@ void vfp_flush_hwstate(struct thread_info *thread)
490 last_VFP_context[cpu] = NULL; 470 last_VFP_context[cpu] = NULL;
491 } 471 }
492 472
473#ifdef CONFIG_SMP
474 /*
475 * For SMP we still have to take care of the case where the thread
476 * migrates to another CPU and then back to the original CPU on which
477 * the last VFP user is still the same thread. Mark the thread VFP
478 * state as belonging to a non-existent CPU so that the saved one will
479 * be reloaded in the above case.
480 */
481 thread->vfpstate.hard.cpu = NR_CPUS;
482#endif
493 put_cpu(); 483 put_cpu();
494} 484}
495#endif
496 485
497#include <linux/smp.h> 486#include <linux/smp.h>
498 487
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 04:33:24 -0500