4 files changed, 17 insertions, 3 deletions

diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 207fce2d6932..297352f214df 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -242,6 +242,10 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
                 save_state = 1;
                 break;
         case PWRDM_POWER_RET:
+                if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE)) {
+                        save_state = 0;
+                        break;
+                }
         default:
                 /*
                  * CPUx CSWR is invalid hardware state. Also CPUx OSWR
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index e844e1603d76..f961c46453b9 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -32,6 +32,7 @@
 #include "soc.h"
 #include "omap4-sar-layout.h"
 #include "common.h"
+#include "pm.h"
 
 #define AM43XX_NR_REG_BANKS     7
 #define AM43XX_IRQS             224
@@ -381,7 +382,7 @@ static struct notifier_block irq_notifier_block = {
 static void __init irq_pm_init(void)
 {
         /* FIXME: Remove this when MPU OSWR support is added */
-        if (!soc_is_omap54xx())
+        if (!IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
                 cpu_pm_register_notifier(&irq_notifier_block);
 }
 #else
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index e150102d6c06..425bfcd67db6 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -101,6 +101,7 @@ static inline void enable_omap3630_toggle_l2_on_restore(void) { }
 #endif          /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */
 
 #define PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD      (1 << 0)
+#define PM_OMAP4_CPU_OSWR_DISABLE               (1 << 1)
 
 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP4)
 extern u16 pm44xx_errata;
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index b6f243db200d..64df620075a5 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -36,6 +36,8 @@ struct power_state {
         struct list_head node;
 };
 
+static u32 cpu_suspend_state = PWRDM_POWER_OFF;
+
 static LIST_HEAD(pwrst_list);
 
 #ifdef CONFIG_SUSPEND
@@ -66,7 +68,7 @@ static int omap4_pm_suspend(void)
          * domain CSWR is not supported by hardware.
          * More details can be found in OMAP4430 TRM section 4.3.4.2.
          */
-        omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF);
+        omap4_enter_lowpower(cpu_id, cpu_suspend_state);
 
         /* Restore next powerdomain state */
         list_for_each_entry(pwrst, &pwrst_list, node) {
@@ -112,8 +114,11 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
          * through hotplug path and CPU0 explicitly programmed
          * further down in the code path
          */
-        if (!strncmp(pwrdm->name, "cpu", 3))
+        if (!strncmp(pwrdm->name, "cpu", 3)) {
+                if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
+                        cpu_suspend_state = PWRDM_POWER_RET;
                 return 0;
+        }
 
         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
         if (!pwrst)
@@ -238,6 +243,9 @@ int __init omap4_pm_init_early(void)
         if (cpu_is_omap446x())
                 pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
 
+        if (soc_is_omap54xx() || soc_is_dra7xx())
+                pm44xx_errata |= PM_OMAP4_CPU_OSWR_DISABLE;
+
         return 0;
 }