diff options
Diffstat (limited to 'arch/arm')
899 files changed, 56787 insertions, 20016 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d56d21c0573b..e2f801167593 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
| @@ -2,6 +2,7 @@ config ARM | |||
| 2 | bool | 2 | bool |
| 3 | default y | 3 | default y |
| 4 | select HAVE_AOUT | 4 | select HAVE_AOUT |
| 5 | select HAVE_DMA_API_DEBUG | ||
| 5 | select HAVE_IDE | 6 | select HAVE_IDE |
| 6 | select HAVE_MEMBLOCK | 7 | select HAVE_MEMBLOCK |
| 7 | select RTC_LIB | 8 | select RTC_LIB |
| @@ -14,6 +15,7 @@ config ARM | |||
| 14 | select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) | 15 | select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) |
| 15 | select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) | 16 | select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) |
| 16 | select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) | 17 | select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) |
| 18 | select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) | ||
| 17 | select HAVE_GENERIC_DMA_COHERENT | 19 | select HAVE_GENERIC_DMA_COHERENT |
| 18 | select HAVE_KERNEL_GZIP | 20 | select HAVE_KERNEL_GZIP |
| 19 | select HAVE_KERNEL_LZO | 21 | select HAVE_KERNEL_LZO |
| @@ -23,6 +25,7 @@ config ARM | |||
| 23 | select PERF_USE_VMALLOC | 25 | select PERF_USE_VMALLOC |
| 24 | select HAVE_REGS_AND_STACK_ACCESS_API | 26 | select HAVE_REGS_AND_STACK_ACCESS_API |
| 25 | select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7)) | 27 | select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7)) |
| 28 | select HAVE_C_RECORDMCOUNT | ||
| 26 | help | 29 | help |
| 27 | The ARM series is a line of low-power-consumption RISC chip designs | 30 | The ARM series is a line of low-power-consumption RISC chip designs |
| 28 | licensed by ARM Ltd and targeted at embedded applications and | 31 | licensed by ARM Ltd and targeted at embedded applications and |
| @@ -34,9 +37,15 @@ config ARM | |||
| 34 | config HAVE_PWM | 37 | config HAVE_PWM |
| 35 | bool | 38 | bool |
| 36 | 39 | ||
| 40 | config MIGHT_HAVE_PCI | ||
| 41 | bool | ||
| 42 | |||
| 37 | config SYS_SUPPORTS_APM_EMULATION | 43 | config SYS_SUPPORTS_APM_EMULATION |
| 38 | bool | 44 | bool |
| 39 | 45 | ||
| 46 | config HAVE_SCHED_CLOCK | ||
| 47 | bool | ||
| 48 | |||
| 40 | config GENERIC_GPIO | 49 | config GENERIC_GPIO |
| 41 | bool | 50 | bool |
| 42 | 51 | ||
| @@ -221,7 +230,7 @@ config ARCH_INTEGRATOR | |||
| 221 | bool "ARM Ltd. Integrator family" | 230 | bool "ARM Ltd. Integrator family" |
| 222 | select ARM_AMBA | 231 | select ARM_AMBA |
| 223 | select ARCH_HAS_CPUFREQ | 232 | select ARCH_HAS_CPUFREQ |
| 224 | select COMMON_CLKDEV | 233 | select CLKDEV_LOOKUP |
| 225 | select ICST | 234 | select ICST |
| 226 | select GENERIC_CLOCKEVENTS | 235 | select GENERIC_CLOCKEVENTS |
| 227 | select PLAT_VERSATILE | 236 | select PLAT_VERSATILE |
| @@ -231,7 +240,8 @@ config ARCH_INTEGRATOR | |||
| 231 | config ARCH_REALVIEW | 240 | config ARCH_REALVIEW |
| 232 | bool "ARM Ltd. RealView family" | 241 | bool "ARM Ltd. RealView family" |
| 233 | select ARM_AMBA | 242 | select ARM_AMBA |
| 234 | select COMMON_CLKDEV | 243 | select CLKDEV_LOOKUP |
| 244 | select HAVE_SCHED_CLOCK | ||
| 235 | select ICST | 245 | select ICST |
| 236 | select GENERIC_CLOCKEVENTS | 246 | select GENERIC_CLOCKEVENTS |
| 237 | select ARCH_WANT_OPTIONAL_GPIOLIB | 247 | select ARCH_WANT_OPTIONAL_GPIOLIB |
| @@ -245,7 +255,8 @@ config ARCH_VERSATILE | |||
| 245 | bool "ARM Ltd. Versatile family" | 255 | bool "ARM Ltd. Versatile family" |
| 246 | select ARM_AMBA | 256 | select ARM_AMBA |
| 247 | select ARM_VIC | 257 | select ARM_VIC |
| 248 | select COMMON_CLKDEV | 258 | select CLKDEV_LOOKUP |
| 259 | select HAVE_SCHED_CLOCK | ||
| 249 | select ICST | 260 | select ICST |
| 250 | select GENERIC_CLOCKEVENTS | 261 | select GENERIC_CLOCKEVENTS |
| 251 | select ARCH_WANT_OPTIONAL_GPIOLIB | 262 | select ARCH_WANT_OPTIONAL_GPIOLIB |
| @@ -259,9 +270,10 @@ config ARCH_VEXPRESS | |||
| 259 | select ARCH_WANT_OPTIONAL_GPIOLIB | 270 | select ARCH_WANT_OPTIONAL_GPIOLIB |
| 260 | select ARM_AMBA | 271 | select ARM_AMBA |
| 261 | select ARM_TIMER_SP804 | 272 | select ARM_TIMER_SP804 |
| 262 | select COMMON_CLKDEV | 273 | select CLKDEV_LOOKUP |
| 263 | select GENERIC_CLOCKEVENTS | 274 | select GENERIC_CLOCKEVENTS |
| 264 | select HAVE_CLK | 275 | select HAVE_CLK |
| 276 | select HAVE_SCHED_CLOCK | ||
| 265 | select ICST | 277 | select ICST |
| 266 | select PLAT_VERSATILE | 278 | select PLAT_VERSATILE |
| 267 | help | 279 | help |
| @@ -280,7 +292,7 @@ config ARCH_BCMRING | |||
| 280 | depends on MMU | 292 | depends on MMU |
| 281 | select CPU_V6 | 293 | select CPU_V6 |
| 282 | select ARM_AMBA | 294 | select ARM_AMBA |
| 283 | select COMMON_CLKDEV | 295 | select CLKDEV_LOOKUP |
| 284 | select GENERIC_CLOCKEVENTS | 296 | select GENERIC_CLOCKEVENTS |
| 285 | select ARCH_WANT_OPTIONAL_GPIOLIB | 297 | select ARCH_WANT_OPTIONAL_GPIOLIB |
| 286 | help | 298 | help |
| @@ -298,6 +310,7 @@ config ARCH_CNS3XXX | |||
| 298 | select CPU_V6 | 310 | select CPU_V6 |
| 299 | select GENERIC_CLOCKEVENTS | 311 | select GENERIC_CLOCKEVENTS |
| 300 | select ARM_GIC | 312 | select ARM_GIC |
| 313 | select MIGHT_HAVE_PCI | ||
| 301 | select PCI_DOMAINS if PCI | 314 | select PCI_DOMAINS if PCI |
| 302 | help | 315 | help |
| 303 | Support for Cavium Networks CNS3XXX platform. | 316 | Support for Cavium Networks CNS3XXX platform. |
| @@ -327,7 +340,7 @@ config ARCH_EP93XX | |||
| 327 | select CPU_ARM920T | 340 | select CPU_ARM920T |
| 328 | select ARM_AMBA | 341 | select ARM_AMBA |
| 329 | select ARM_VIC | 342 | select ARM_VIC |
| 330 | select COMMON_CLKDEV | 343 | select CLKDEV_LOOKUP |
| 331 | select ARCH_REQUIRE_GPIOLIB | 344 | select ARCH_REQUIRE_GPIOLIB |
| 332 | select ARCH_HAS_HOLES_MEMORYMODEL | 345 | select ARCH_HAS_HOLES_MEMORYMODEL |
| 333 | select ARCH_USES_GETTIMEOFFSET | 346 | select ARCH_USES_GETTIMEOFFSET |
| @@ -347,14 +360,22 @@ config ARCH_MXC | |||
| 347 | bool "Freescale MXC/iMX-based" | 360 | bool "Freescale MXC/iMX-based" |
| 348 | select GENERIC_CLOCKEVENTS | 361 | select GENERIC_CLOCKEVENTS |
| 349 | select ARCH_REQUIRE_GPIOLIB | 362 | select ARCH_REQUIRE_GPIOLIB |
| 350 | select COMMON_CLKDEV | 363 | select CLKDEV_LOOKUP |
| 351 | help | 364 | help |
| 352 | Support for Freescale MXC/iMX-based family of processors | 365 | Support for Freescale MXC/iMX-based family of processors |
| 353 | 366 | ||
| 367 | config ARCH_MXS | ||
| 368 | bool "Freescale MXS-based" | ||
| 369 | select GENERIC_CLOCKEVENTS | ||
| 370 | select ARCH_REQUIRE_GPIOLIB | ||
| 371 | select COMMON_CLKDEV | ||
| 372 | help | ||
| 373 | Support for Freescale MXS-based family of processors | ||
| 374 | |||
| 354 | config ARCH_STMP3XXX | 375 | config ARCH_STMP3XXX |
| 355 | bool "Freescale STMP3xxx" | 376 | bool "Freescale STMP3xxx" |
| 356 | select CPU_ARM926T | 377 | select CPU_ARM926T |
| 357 | select COMMON_CLKDEV | 378 | select CLKDEV_LOOKUP |
| 358 | select ARCH_REQUIRE_GPIOLIB | 379 | select ARCH_REQUIRE_GPIOLIB |
| 359 | select GENERIC_CLOCKEVENTS | 380 | select GENERIC_CLOCKEVENTS |
| 360 | select USB_ARCH_HAS_EHCI | 381 | select USB_ARCH_HAS_EHCI |
| @@ -433,6 +454,8 @@ config ARCH_IXP4XX | |||
| 433 | select CPU_XSCALE | 454 | select CPU_XSCALE |
| 434 | select GENERIC_GPIO | 455 | select GENERIC_GPIO |
| 435 | select GENERIC_CLOCKEVENTS | 456 | select GENERIC_CLOCKEVENTS |
| 457 | select HAVE_SCHED_CLOCK | ||
| 458 | select MIGHT_HAVE_PCI | ||
| 436 | select DMABOUNCE if PCI | 459 | select DMABOUNCE if PCI |
| 437 | help | 460 | help |
| 438 | Support for Intel's IXP4XX (XScale) family of processors. | 461 | Support for Intel's IXP4XX (XScale) family of processors. |
| @@ -472,7 +495,7 @@ config ARCH_LPC32XX | |||
| 472 | select HAVE_IDE | 495 | select HAVE_IDE |
| 473 | select ARM_AMBA | 496 | select ARM_AMBA |
| 474 | select USB_ARCH_HAS_OHCI | 497 | select USB_ARCH_HAS_OHCI |
| 475 | select COMMON_CLKDEV | 498 | select CLKDEV_LOOKUP |
| 476 | select GENERIC_TIME | 499 | select GENERIC_TIME |
| 477 | select GENERIC_CLOCKEVENTS | 500 | select GENERIC_CLOCKEVENTS |
| 478 | help | 501 | help |
| @@ -506,8 +529,9 @@ config ARCH_MMP | |||
| 506 | bool "Marvell PXA168/910/MMP2" | 529 | bool "Marvell PXA168/910/MMP2" |
| 507 | depends on MMU | 530 | depends on MMU |
| 508 | select ARCH_REQUIRE_GPIOLIB | 531 | select ARCH_REQUIRE_GPIOLIB |
| 509 | select COMMON_CLKDEV | 532 | select CLKDEV_LOOKUP |
| 510 | select GENERIC_CLOCKEVENTS | 533 | select GENERIC_CLOCKEVENTS |
| 534 | select HAVE_SCHED_CLOCK | ||
| 511 | select TICK_ONESHOT | 535 | select TICK_ONESHOT |
| 512 | select PLAT_PXA | 536 | select PLAT_PXA |
| 513 | select SPARSE_IRQ | 537 | select SPARSE_IRQ |
| @@ -539,7 +563,7 @@ config ARCH_W90X900 | |||
| 539 | bool "Nuvoton W90X900 CPU" | 563 | bool "Nuvoton W90X900 CPU" |
| 540 | select CPU_ARM926T | 564 | select CPU_ARM926T |
| 541 | select ARCH_REQUIRE_GPIOLIB | 565 | select ARCH_REQUIRE_GPIOLIB |
| 542 | select COMMON_CLKDEV | 566 | select CLKDEV_LOOKUP |
| 543 | select GENERIC_CLOCKEVENTS | 567 | select GENERIC_CLOCKEVENTS |
| 544 | help | 568 | help |
| 545 | Support for Nuvoton (Winbond logic dept.) ARM9 processor, | 569 | Support for Nuvoton (Winbond logic dept.) ARM9 processor, |
| @@ -553,18 +577,19 @@ config ARCH_W90X900 | |||
| 553 | config ARCH_NUC93X | 577 | config ARCH_NUC93X |
| 554 | bool "Nuvoton NUC93X CPU" | 578 | bool "Nuvoton NUC93X CPU" |
| 555 | select CPU_ARM926T | 579 | select CPU_ARM926T |
| 556 | select COMMON_CLKDEV | 580 | select CLKDEV_LOOKUP |
| 557 | help | 581 | help |
| 558 | Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a | 582 | Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a |
| 559 | low-power and high performance MPEG-4/JPEG multimedia controller chip. | 583 | low-power and high performance MPEG-4/JPEG multimedia controller chip. |
| 560 | 584 | ||
| 561 | config ARCH_TEGRA | 585 | config ARCH_TEGRA |
| 562 | bool "NVIDIA Tegra" | 586 | bool "NVIDIA Tegra" |
| 587 | select CLKDEV_LOOKUP | ||
| 563 | select GENERIC_TIME | 588 | select GENERIC_TIME |
| 564 | select GENERIC_CLOCKEVENTS | 589 | select GENERIC_CLOCKEVENTS |
| 565 | select GENERIC_GPIO | 590 | select GENERIC_GPIO |
| 566 | select HAVE_CLK | 591 | select HAVE_CLK |
| 567 | select COMMON_CLKDEV | 592 | select HAVE_SCHED_CLOCK |
| 568 | select ARCH_HAS_BARRIERS if CACHE_L2X0 | 593 | select ARCH_HAS_BARRIERS if CACHE_L2X0 |
| 569 | select ARCH_HAS_CPUFREQ | 594 | select ARCH_HAS_CPUFREQ |
| 570 | help | 595 | help |
| @@ -574,7 +599,7 @@ config ARCH_TEGRA | |||
| 574 | config ARCH_PNX4008 | 599 | config ARCH_PNX4008 |
| 575 | bool "Philips Nexperia PNX4008 Mobile" | 600 | bool "Philips Nexperia PNX4008 Mobile" |
| 576 | select CPU_ARM926T | 601 | select CPU_ARM926T |
| 577 | select COMMON_CLKDEV | 602 | select CLKDEV_LOOKUP |
| 578 | select ARCH_USES_GETTIMEOFFSET | 603 | select ARCH_USES_GETTIMEOFFSET |
| 579 | help | 604 | help |
| 580 | This enables support for Philips PNX4008 mobile platform. | 605 | This enables support for Philips PNX4008 mobile platform. |
| @@ -584,9 +609,10 @@ config ARCH_PXA | |||
| 584 | depends on MMU | 609 | depends on MMU |
| 585 | select ARCH_MTD_XIP | 610 | select ARCH_MTD_XIP |
| 586 | select ARCH_HAS_CPUFREQ | 611 | select ARCH_HAS_CPUFREQ |
| 587 | select COMMON_CLKDEV | 612 | select CLKDEV_LOOKUP |
| 588 | select ARCH_REQUIRE_GPIOLIB | 613 | select ARCH_REQUIRE_GPIOLIB |
| 589 | select GENERIC_CLOCKEVENTS | 614 | select GENERIC_CLOCKEVENTS |
| 615 | select HAVE_SCHED_CLOCK | ||
| 590 | select TICK_ONESHOT | 616 | select TICK_ONESHOT |
| 591 | select PLAT_PXA | 617 | select PLAT_PXA |
| 592 | select SPARSE_IRQ | 618 | select SPARSE_IRQ |
| @@ -606,9 +632,15 @@ config ARCH_MSM | |||
| 606 | (clock and power control, etc). | 632 | (clock and power control, etc). |
| 607 | 633 | ||
| 608 | config ARCH_SHMOBILE | 634 | config ARCH_SHMOBILE |
| 609 | bool "Renesas SH-Mobile" | 635 | bool "Renesas SH-Mobile / R-Mobile" |
| 636 | select HAVE_CLK | ||
| 637 | select CLKDEV_LOOKUP | ||
| 638 | select GENERIC_CLOCKEVENTS | ||
| 639 | select NO_IOPORT | ||
| 640 | select SPARSE_IRQ | ||
| 641 | select MULTI_IRQ_HANDLER | ||
| 610 | help | 642 | help |
| 611 | Support for Renesas's SH-Mobile ARM platforms | 643 | Support for Renesas's SH-Mobile and R-Mobile ARM platforms. |
| 612 | 644 | ||
| 613 | config ARCH_RPC | 645 | config ARCH_RPC |
| 614 | bool "RiscPC" | 646 | bool "RiscPC" |
| @@ -635,6 +667,7 @@ config ARCH_SA1100 | |||
| 635 | select CPU_FREQ | 667 | select CPU_FREQ |
| 636 | select GENERIC_CLOCKEVENTS | 668 | select GENERIC_CLOCKEVENTS |
| 637 | select HAVE_CLK | 669 | select HAVE_CLK |
| 670 | select HAVE_SCHED_CLOCK | ||
| 638 | select TICK_ONESHOT | 671 | select TICK_ONESHOT |
| 639 | select ARCH_REQUIRE_GPIOLIB | 672 | select ARCH_REQUIRE_GPIOLIB |
| 640 | help | 673 | help |
| @@ -761,7 +794,7 @@ config ARCH_TCC_926 | |||
| 761 | bool "Telechips TCC ARM926-based systems" | 794 | bool "Telechips TCC ARM926-based systems" |
| 762 | select CPU_ARM926T | 795 | select CPU_ARM926T |
| 763 | select HAVE_CLK | 796 | select HAVE_CLK |
| 764 | select COMMON_CLKDEV | 797 | select CLKDEV_LOOKUP |
| 765 | select GENERIC_CLOCKEVENTS | 798 | select GENERIC_CLOCKEVENTS |
| 766 | help | 799 | help |
| 767 | Support for Telechips TCC ARM926-based systems. | 800 | Support for Telechips TCC ARM926-based systems. |
| @@ -781,11 +814,12 @@ config ARCH_U300 | |||
| 781 | bool "ST-Ericsson U300 Series" | 814 | bool "ST-Ericsson U300 Series" |
| 782 | depends on MMU | 815 | depends on MMU |
| 783 | select CPU_ARM926T | 816 | select CPU_ARM926T |
| 817 | select HAVE_SCHED_CLOCK | ||
| 784 | select HAVE_TCM | 818 | select HAVE_TCM |
| 785 | select ARM_AMBA | 819 | select ARM_AMBA |
| 786 | select ARM_VIC | 820 | select ARM_VIC |
| 787 | select GENERIC_CLOCKEVENTS | 821 | select GENERIC_CLOCKEVENTS |
| 788 | select COMMON_CLKDEV | 822 | select CLKDEV_LOOKUP |
| 789 | select GENERIC_GPIO | 823 | select GENERIC_GPIO |
| 790 | help | 824 | help |
| 791 | Support for ST-Ericsson U300 series mobile platforms. | 825 | Support for ST-Ericsson U300 series mobile platforms. |
| @@ -795,8 +829,9 @@ config ARCH_U8500 | |||
| 795 | select CPU_V7 | 829 | select CPU_V7 |
| 796 | select ARM_AMBA | 830 | select ARM_AMBA |
| 797 | select GENERIC_CLOCKEVENTS | 831 | select GENERIC_CLOCKEVENTS |
| 798 | select COMMON_CLKDEV | 832 | select CLKDEV_LOOKUP |
| 799 | select ARCH_REQUIRE_GPIOLIB | 833 | select ARCH_REQUIRE_GPIOLIB |
| 834 | select ARCH_HAS_CPUFREQ | ||
| 800 | help | 835 | help |
| 801 | Support for ST-Ericsson's Ux500 architecture | 836 | Support for ST-Ericsson's Ux500 architecture |
| 802 | 837 | ||
| @@ -805,7 +840,7 @@ config ARCH_NOMADIK | |||
| 805 | select ARM_AMBA | 840 | select ARM_AMBA |
| 806 | select ARM_VIC | 841 | select ARM_VIC |
| 807 | select CPU_ARM926T | 842 | select CPU_ARM926T |
| 808 | select COMMON_CLKDEV | 843 | select CLKDEV_LOOKUP |
| 809 | select GENERIC_CLOCKEVENTS | 844 | select GENERIC_CLOCKEVENTS |
| 810 | select ARCH_REQUIRE_GPIOLIB | 845 | select ARCH_REQUIRE_GPIOLIB |
| 811 | help | 846 | help |
| @@ -817,7 +852,7 @@ config ARCH_DAVINCI | |||
| 817 | select ARCH_REQUIRE_GPIOLIB | 852 | select ARCH_REQUIRE_GPIOLIB |
| 818 | select ZONE_DMA | 853 | select ZONE_DMA |
| 819 | select HAVE_IDE | 854 | select HAVE_IDE |
| 820 | select COMMON_CLKDEV | 855 | select CLKDEV_LOOKUP |
| 821 | select GENERIC_ALLOCATOR | 856 | select GENERIC_ALLOCATOR |
| 822 | select ARCH_HAS_HOLES_MEMORYMODEL | 857 | select ARCH_HAS_HOLES_MEMORYMODEL |
| 823 | help | 858 | help |
| @@ -829,6 +864,7 @@ config ARCH_OMAP | |||
| 829 | select ARCH_REQUIRE_GPIOLIB | 864 | select ARCH_REQUIRE_GPIOLIB |
| 830 | select ARCH_HAS_CPUFREQ | 865 | select ARCH_HAS_CPUFREQ |
| 831 | select GENERIC_CLOCKEVENTS | 866 | select GENERIC_CLOCKEVENTS |
| 867 | select HAVE_SCHED_CLOCK | ||
| 832 | select ARCH_HAS_HOLES_MEMORYMODEL | 868 | select ARCH_HAS_HOLES_MEMORYMODEL |
| 833 | help | 869 | help |
| 834 | Support for TI's OMAP platform (OMAP1/2/3/4). | 870 | Support for TI's OMAP platform (OMAP1/2/3/4). |
| @@ -837,7 +873,7 @@ config PLAT_SPEAR | |||
| 837 | bool "ST SPEAr" | 873 | bool "ST SPEAr" |
| 838 | select ARM_AMBA | 874 | select ARM_AMBA |
| 839 | select ARCH_REQUIRE_GPIOLIB | 875 | select ARCH_REQUIRE_GPIOLIB |
| 840 | select COMMON_CLKDEV | 876 | select CLKDEV_LOOKUP |
| 841 | select GENERIC_CLOCKEVENTS | 877 | select GENERIC_CLOCKEVENTS |
| 842 | select HAVE_CLK | 878 | select HAVE_CLK |
| 843 | help | 879 | help |
| @@ -902,6 +938,8 @@ source "arch/arm/mach-mv78xx0/Kconfig" | |||
| 902 | 938 | ||
| 903 | source "arch/arm/plat-mxc/Kconfig" | 939 | source "arch/arm/plat-mxc/Kconfig" |
| 904 | 940 | ||
| 941 | source "arch/arm/mach-mxs/Kconfig" | ||
| 942 | |||
| 905 | source "arch/arm/mach-netx/Kconfig" | 943 | source "arch/arm/mach-netx/Kconfig" |
| 906 | 944 | ||
| 907 | source "arch/arm/mach-nomadik/Kconfig" | 945 | source "arch/arm/mach-nomadik/Kconfig" |
| @@ -982,9 +1020,11 @@ config ARCH_ACORN | |||
| 982 | config PLAT_IOP | 1020 | config PLAT_IOP |
| 983 | bool | 1021 | bool |
| 984 | select GENERIC_CLOCKEVENTS | 1022 | select GENERIC_CLOCKEVENTS |
| 1023 | select HAVE_SCHED_CLOCK | ||
| 985 | 1024 | ||
| 986 | config PLAT_ORION | 1025 | config PLAT_ORION |
| 987 | bool | 1026 | bool |
| 1027 | select HAVE_SCHED_CLOCK | ||
| 988 | 1028 | ||
| 989 | config PLAT_PXA | 1029 | config PLAT_PXA |
| 990 | bool | 1030 | bool |
| @@ -999,8 +1039,8 @@ source arch/arm/mm/Kconfig | |||
| 999 | 1039 | ||
| 1000 | config IWMMXT | 1040 | config IWMMXT |
| 1001 | bool "Enable iWMMXt support" | 1041 | bool "Enable iWMMXt support" |
| 1002 | depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK | 1042 | depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 |
| 1003 | default y if PXA27x || PXA3xx || ARCH_MMP | 1043 | default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP |
| 1004 | help | 1044 | help |
| 1005 | Enable support for iWMMXt context switching at run time if | 1045 | Enable support for iWMMXt context switching at run time if |
| 1006 | running on a CPU that supports it. | 1046 | running on a CPU that supports it. |
| @@ -1017,6 +1057,11 @@ config CPU_HAS_PMU | |||
| 1017 | default y | 1057 | default y |
| 1018 | bool | 1058 | bool |
| 1019 | 1059 | ||
| 1060 | config MULTI_IRQ_HANDLER | ||
| 1061 | bool | ||
| 1062 | help | ||
| 1063 | Allow each machine to specify it's own IRQ handler at run time. | ||
| 1064 | |||
| 1020 | if !MMU | 1065 | if !MMU |
| 1021 | source "arch/arm/Kconfig-nommu" | 1066 | source "arch/arm/Kconfig-nommu" |
| 1022 | endif | 1067 | endif |
| @@ -1164,7 +1209,7 @@ config ISA_DMA_API | |||
| 1164 | bool | 1209 | bool |
| 1165 | 1210 | ||
| 1166 | config PCI | 1211 | config PCI |
| 1167 | bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX | 1212 | bool "PCI support" if MIGHT_HAVE_PCI |
| 1168 | help | 1213 | help |
| 1169 | Find out whether you have a PCI motherboard. PCI is the name of a | 1214 | Find out whether you have a PCI motherboard. PCI is the name of a |
| 1170 | bus system, i.e. the way the CPU talks to the other stuff inside | 1215 | bus system, i.e. the way the CPU talks to the other stuff inside |
| @@ -1175,6 +1220,12 @@ config PCI_DOMAINS | |||
| 1175 | bool | 1220 | bool |
| 1176 | depends on PCI | 1221 | depends on PCI |
| 1177 | 1222 | ||
| 1223 | config PCI_NANOENGINE | ||
| 1224 | bool "BSE nanoEngine PCI support" | ||
| 1225 | depends on SA1100_NANOENGINE | ||
| 1226 | help | ||
| 1227 | Enable PCI on the BSE nanoEngine board. | ||
| 1228 | |||
| 1178 | config PCI_SYSCALL | 1229 | config PCI_SYSCALL |
| 1179 | def_bool PCI | 1230 | def_bool PCI |
| 1180 | 1231 | ||
| @@ -1205,10 +1256,11 @@ config SMP | |||
| 1205 | depends on EXPERIMENTAL | 1256 | depends on EXPERIMENTAL |
| 1206 | depends on GENERIC_CLOCKEVENTS | 1257 | depends on GENERIC_CLOCKEVENTS |
| 1207 | depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \ | 1258 | depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \ |
| 1208 | MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 ||\ | 1259 | MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \ |
| 1209 | ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 | 1260 | ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \ |
| 1261 | ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE | ||
| 1210 | select USE_GENERIC_SMP_HELPERS | 1262 | select USE_GENERIC_SMP_HELPERS |
| 1211 | select HAVE_ARM_SCU | 1263 | select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP |
| 1212 | help | 1264 | help |
| 1213 | This enables support for systems with more than one CPU. If you have | 1265 | This enables support for systems with more than one CPU. If you have |
| 1214 | a system with only one CPU, like most personal computers, say N. If | 1266 | a system with only one CPU, like most personal computers, say N. If |
| @@ -1229,7 +1281,7 @@ config SMP | |||
| 1229 | config SMP_ON_UP | 1281 | config SMP_ON_UP |
| 1230 | bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)" | 1282 | bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)" |
| 1231 | depends on EXPERIMENTAL | 1283 | depends on EXPERIMENTAL |
| 1232 | depends on SMP && !XIP && !THUMB2_KERNEL | 1284 | depends on SMP && !XIP |
| 1233 | default y | 1285 | default y |
| 1234 | help | 1286 | help |
| 1235 | SMP kernels contain instructions which fail on non-SMP processors. | 1287 | SMP kernels contain instructions which fail on non-SMP processors. |
| @@ -1248,6 +1300,7 @@ config HAVE_ARM_SCU | |||
| 1248 | config HAVE_ARM_TWD | 1300 | config HAVE_ARM_TWD |
| 1249 | bool | 1301 | bool |
| 1250 | depends on SMP | 1302 | depends on SMP |
| 1303 | select TICK_ONESHOT | ||
| 1251 | help | 1304 | help |
| 1252 | This options enables support for the ARM timer and watchdog unit | 1305 | This options enables support for the ARM timer and watchdog unit |
| 1253 | 1306 | ||
| @@ -1283,6 +1336,7 @@ config NR_CPUS | |||
| 1283 | config HOTPLUG_CPU | 1336 | config HOTPLUG_CPU |
| 1284 | bool "Support for hot-pluggable CPUs (EXPERIMENTAL)" | 1337 | bool "Support for hot-pluggable CPUs (EXPERIMENTAL)" |
| 1285 | depends on SMP && HOTPLUG && EXPERIMENTAL | 1338 | depends on SMP && HOTPLUG && EXPERIMENTAL |
| 1339 | depends on !ARCH_MSM | ||
| 1286 | help | 1340 | help |
| 1287 | Say Y here to experiment with turning CPUs off and on. CPUs | 1341 | Say Y here to experiment with turning CPUs off and on. CPUs |
| 1288 | can be controlled through /sys/devices/system/cpu. | 1342 | can be controlled through /sys/devices/system/cpu. |
| @@ -1291,7 +1345,7 @@ config LOCAL_TIMERS | |||
| 1291 | bool "Use local timer interrupts" | 1345 | bool "Use local timer interrupts" |
| 1292 | depends on SMP | 1346 | depends on SMP |
| 1293 | default y | 1347 | default y |
| 1294 | select HAVE_ARM_TWD | 1348 | select HAVE_ARM_TWD if !ARCH_MSM_SCORPIONMP |
| 1295 | help | 1349 | help |
| 1296 | Enable support for local timers on SMP platforms, rather then the | 1350 | Enable support for local timers on SMP platforms, rather then the |
| 1297 | legacy IPI broadcast method. Local timers allows the system | 1351 | legacy IPI broadcast method. Local timers allows the system |
| @@ -1310,7 +1364,7 @@ config HZ | |||
| 1310 | default 100 | 1364 | default 100 |
| 1311 | 1365 | ||
| 1312 | config THUMB2_KERNEL | 1366 | config THUMB2_KERNEL |
| 1313 | bool "Compile the kernel in Thumb-2 mode" | 1367 | bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)" |
| 1314 | depends on CPU_V7 && !CPU_V6 && EXPERIMENTAL | 1368 | depends on CPU_V7 && !CPU_V6 && EXPERIMENTAL |
| 1315 | select AEABI | 1369 | select AEABI |
| 1316 | select ARM_ASM_UNIFIED | 1370 | select ARM_ASM_UNIFIED |
| @@ -1524,6 +1578,7 @@ config SECCOMP | |||
| 1524 | 1578 | ||
| 1525 | config CC_STACKPROTECTOR | 1579 | config CC_STACKPROTECTOR |
| 1526 | bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" | 1580 | bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" |
| 1581 | depends on EXPERIMENTAL | ||
| 1527 | help | 1582 | help |
| 1528 | This option turns on the -fstack-protector GCC feature. This | 1583 | This option turns on the -fstack-protector GCC feature. This |
| 1529 | feature puts, at the beginning of functions, a canary value on | 1584 | feature puts, at the beginning of functions, a canary value on |
| @@ -1650,6 +1705,19 @@ config ATAGS_PROC | |||
| 1650 | Should the atags used to boot the kernel be exported in an "atags" | 1705 | Should the atags used to boot the kernel be exported in an "atags" |
| 1651 | file in procfs. Useful with kexec. | 1706 | file in procfs. Useful with kexec. |
| 1652 | 1707 | ||
| 1708 | config CRASH_DUMP | ||
| 1709 | bool "Build kdump crash kernel (EXPERIMENTAL)" | ||
| 1710 | depends on EXPERIMENTAL | ||
| 1711 | help | ||
| 1712 | Generate crash dump after being started by kexec. This should | ||
| 1713 | be normally only set in special crash dump kernels which are | ||
| 1714 | loaded in the main kernel with kexec-tools into a specially | ||
| 1715 | reserved region and then later executed after a crash by | ||
| 1716 | kdump/kexec. The crash dump kernel must be compiled to a | ||
| 1717 | memory address not used by the main kernel | ||
| 1718 | |||
| 1719 | For more details see Documentation/kdump/kdump.txt | ||
| 1720 | |||
| 1653 | config AUTO_ZRELADDR | 1721 | config AUTO_ZRELADDR |
| 1654 | bool "Auto calculation of the decompressed kernel image address" | 1722 | bool "Auto calculation of the decompressed kernel image address" |
| 1655 | depends on !ZBOOT_ROM && !ARCH_U300 | 1723 | depends on !ZBOOT_ROM && !ARCH_U300 |
| @@ -1707,7 +1775,7 @@ config CPU_FREQ_S3C | |||
| 1707 | Internal configuration node for common cpufreq on Samsung SoC | 1775 | Internal configuration node for common cpufreq on Samsung SoC |
| 1708 | 1776 | ||
| 1709 | config CPU_FREQ_S3C24XX | 1777 | config CPU_FREQ_S3C24XX |
| 1710 | bool "CPUfreq driver for Samsung S3C24XX series CPUs" | 1778 | bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)" |
| 1711 | depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL | 1779 | depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL |
| 1712 | select CPU_FREQ_S3C | 1780 | select CPU_FREQ_S3C |
| 1713 | help | 1781 | help |
| @@ -1719,7 +1787,7 @@ config CPU_FREQ_S3C24XX | |||
| 1719 | If in doubt, say N. | 1787 | If in doubt, say N. |
| 1720 | 1788 | ||
| 1721 | config CPU_FREQ_S3C24XX_PLL | 1789 | config CPU_FREQ_S3C24XX_PLL |
| 1722 | bool "Support CPUfreq changing of PLL frequency" | 1790 | bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)" |
| 1723 | depends on CPU_FREQ_S3C24XX && EXPERIMENTAL | 1791 | depends on CPU_FREQ_S3C24XX && EXPERIMENTAL |
| 1724 | help | 1792 | help |
| 1725 | Compile in support for changing the PLL frequency from the | 1793 | Compile in support for changing the PLL frequency from the |
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 2fd0b99afc4b..494224a9b459 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug | |||
| @@ -23,7 +23,7 @@ config STRICT_DEVMEM | |||
| 23 | config FRAME_POINTER | 23 | config FRAME_POINTER |
| 24 | bool | 24 | bool |
| 25 | depends on !THUMB2_KERNEL | 25 | depends on !THUMB2_KERNEL |
| 26 | default y if !ARM_UNWIND | 26 | default y if !ARM_UNWIND || FUNCTION_GRAPH_TRACER |
| 27 | help | 27 | help |
| 28 | If you say N here, the resulting kernel will be slightly smaller and | 28 | If you say N here, the resulting kernel will be slightly smaller and |
| 29 | faster. However, if neither FRAME_POINTER nor ARM_UNWIND are enabled, | 29 | faster. However, if neither FRAME_POINTER nor ARM_UNWIND are enabled, |
| @@ -31,7 +31,7 @@ config FRAME_POINTER | |||
| 31 | reported is severely limited. | 31 | reported is severely limited. |
| 32 | 32 | ||
| 33 | config ARM_UNWIND | 33 | config ARM_UNWIND |
| 34 | bool "Enable stack unwinding support" | 34 | bool "Enable stack unwinding support (EXPERIMENTAL)" |
| 35 | depends on AEABI && EXPERIMENTAL | 35 | depends on AEABI && EXPERIMENTAL |
| 36 | default y | 36 | default y |
| 37 | help | 37 | help |
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index b87aed028eef..c22c1adfedd6 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile | |||
| @@ -154,10 +154,11 @@ machine-$(CONFIG_ARCH_MSM) := msm | |||
| 154 | machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 | 154 | machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 |
| 155 | machine-$(CONFIG_ARCH_MX1) := imx | 155 | machine-$(CONFIG_ARCH_MX1) := imx |
| 156 | machine-$(CONFIG_ARCH_MX2) := imx | 156 | machine-$(CONFIG_ARCH_MX2) := imx |
| 157 | machine-$(CONFIG_ARCH_MX25) := mx25 | 157 | machine-$(CONFIG_ARCH_MX25) := imx |
| 158 | machine-$(CONFIG_ARCH_MX3) := mx3 | 158 | machine-$(CONFIG_ARCH_MX3) := mx3 |
| 159 | machine-$(CONFIG_ARCH_MX5) := mx5 | 159 | machine-$(CONFIG_ARCH_MX5) := mx5 |
| 160 | machine-$(CONFIG_ARCH_MXC91231) := mxc91231 | 160 | machine-$(CONFIG_ARCH_MXC91231) := mxc91231 |
| 161 | machine-$(CONFIG_ARCH_MXS) := mxs | ||
| 161 | machine-$(CONFIG_ARCH_NETX) := netx | 162 | machine-$(CONFIG_ARCH_NETX) := netx |
| 162 | machine-$(CONFIG_ARCH_NOMADIK) := nomadik | 163 | machine-$(CONFIG_ARCH_NOMADIK) := nomadik |
| 163 | machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx | 164 | machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx |
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 65a7c1c588a9..0a8f748e506a 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile | |||
| @@ -45,6 +45,10 @@ else | |||
| 45 | endif | 45 | endif |
| 46 | endif | 46 | endif |
| 47 | 47 | ||
| 48 | ifeq ($(CONFIG_ARCH_SHMOBILE),y) | ||
| 49 | OBJS += head-shmobile.o | ||
| 50 | endif | ||
| 51 | |||
| 48 | # | 52 | # |
| 49 | # We now have a PIC decompressor implementation. Decompressors running | 53 | # We now have a PIC decompressor implementation. Decompressors running |
| 50 | # from RAM should not define ZTEXTADDR. Decompressors running directly | 54 | # from RAM should not define ZTEXTADDR. Decompressors running directly |
diff --git a/arch/arm/boot/compressed/head-shmobile.S b/arch/arm/boot/compressed/head-shmobile.S new file mode 100644 index 000000000000..30973b76e6ae --- /dev/null +++ b/arch/arm/boot/compressed/head-shmobile.S | |||
| @@ -0,0 +1,53 @@ | |||
| 1 | /* | ||
| 2 | * The head-file for SH-Mobile ARM platforms | ||
| 3 | * | ||
| 4 | * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | ||
| 5 | * Simon Horman <horms@verge.net.au> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; version 2 of the License. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifdef CONFIG_ZBOOT_ROM | ||
| 22 | |||
| 23 | .section ".start", "ax" | ||
| 24 | |||
| 25 | /* load board-specific initialization code */ | ||
| 26 | #include <mach/zboot.h> | ||
| 27 | |||
| 28 | b 1f | ||
| 29 | __atags:@ tag #1 | ||
| 30 | .long 12 @ tag->hdr.size = tag_size(tag_core); | ||
| 31 | .long 0x54410001 @ tag->hdr.tag = ATAG_CORE; | ||
| 32 | .long 0 @ tag->u.core.flags = 0; | ||
| 33 | .long 0 @ tag->u.core.pagesize = 0; | ||
| 34 | .long 0 @ tag->u.core.rootdev = 0; | ||
| 35 | @ tag #2 | ||
| 36 | .long 8 @ tag->hdr.size = tag_size(tag_mem32); | ||
| 37 | .long 0x54410002 @ tag->hdr.tag = ATAG_MEM; | ||
| 38 | .long CONFIG_MEMORY_SIZE @ tag->u.mem.size = CONFIG_MEMORY_SIZE; | ||
| 39 | .long CONFIG_MEMORY_START @ @ tag->u.mem.start = CONFIG_MEMORY_START; | ||
| 40 | @ tag #3 | ||
| 41 | .long 0 @ tag->hdr.size = 0 | ||
| 42 | .long 0 @ tag->hdr.tag = ATAG_NONE; | ||
| 43 | 1: | ||
| 44 | |||
| 45 | /* Set board ID necessary for boot */ | ||
| 46 | ldr r7, 1f @ Set machine type register | ||
| 47 | adr r8, __atags @ Set atag register | ||
| 48 | b 2f | ||
| 49 | |||
| 50 | 1 : .long MACH_TYPE | ||
| 51 | 2 : | ||
| 52 | |||
| 53 | #endif /* CONFIG_ZBOOT_ROM */ | ||
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig index 0a34c8186924..778655f0257a 100644 --- a/arch/arm/common/Kconfig +++ b/arch/arm/common/Kconfig | |||
| @@ -37,7 +37,3 @@ config SHARP_PARAM | |||
| 37 | 37 | ||
| 38 | config SHARP_SCOOP | 38 | config SHARP_SCOOP |
| 39 | bool | 39 | bool |
| 40 | |||
| 41 | config COMMON_CLKDEV | ||
| 42 | bool | ||
| 43 | select HAVE_CLK | ||
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile index e6e8664a9413..e7521bca2c35 100644 --- a/arch/arm/common/Makefile +++ b/arch/arm/common/Makefile | |||
| @@ -17,3 +17,4 @@ obj-$(CONFIG_ARCH_IXP2000) += uengine.o | |||
| 17 | obj-$(CONFIG_ARCH_IXP23XX) += uengine.o | 17 | obj-$(CONFIG_ARCH_IXP23XX) += uengine.o |
| 18 | obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o | 18 | obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o |
| 19 | obj-$(CONFIG_COMMON_CLKDEV) += clkdev.o | 19 | obj-$(CONFIG_COMMON_CLKDEV) += clkdev.o |
| 20 | obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o | ||
diff --git a/arch/arm/common/clkdev.c b/arch/arm/common/clkdev.c deleted file mode 100644 index e2b2bb66e094..000000000000 --- a/arch/arm/common/clkdev.c +++ /dev/null | |||
| @@ -1,179 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/common/clkdev.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008 Russell King. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * Helper for the clk API to assist looking up a struct clk. | ||
| 11 | */ | ||
| 12 | #include <linux/module.h> | ||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/device.h> | ||
| 15 | #include <linux/list.h> | ||
| 16 | #include <linux/errno.h> | ||
| 17 | #include <linux/err.h> | ||
| 18 | #include <linux/string.h> | ||
| 19 | #include <linux/mutex.h> | ||
| 20 | #include <linux/clk.h> | ||
| 21 | #include <linux/slab.h> | ||
| 22 | |||
| 23 | #include <asm/clkdev.h> | ||
| 24 | #include <mach/clkdev.h> | ||
| 25 | |||
| 26 | static LIST_HEAD(clocks); | ||
| 27 | static DEFINE_MUTEX(clocks_mutex); | ||
| 28 | |||
| 29 | /* | ||
| 30 | * Find the correct struct clk for the device and connection ID. | ||
| 31 | * We do slightly fuzzy matching here: | ||
| 32 | * An entry with a NULL ID is assumed to be a wildcard. | ||
| 33 | * If an entry has a device ID, it must match | ||
| 34 | * If an entry has a connection ID, it must match | ||
| 35 | * Then we take the most specific entry - with the following | ||
| 36 | * order of precedence: dev+con > dev only > con only. | ||
| 37 | */ | ||
| 38 | static struct clk *clk_find(const char *dev_id, const char *con_id) | ||
| 39 | { | ||
| 40 | struct clk_lookup *p; | ||
| 41 | struct clk *clk = NULL; | ||
| 42 | int match, best = 0; | ||
| 43 | |||
| 44 | list_for_each_entry(p, &clocks, node) { | ||
| 45 | match = 0; | ||
| 46 | if (p->dev_id) { | ||
| 47 | if (!dev_id || strcmp(p->dev_id, dev_id)) | ||
| 48 | continue; | ||
| 49 | match += 2; | ||
| 50 | } | ||
| 51 | if (p->con_id) { | ||
| 52 | if (!con_id || strcmp(p->con_id, con_id)) | ||
| 53 | continue; | ||
| 54 | match += 1; | ||
| 55 | } | ||
| 56 | |||
| 57 | if (match > best) { | ||
| 58 | clk = p->clk; | ||
| 59 | if (match != 3) | ||
| 60 | best = match; | ||
| 61 | else | ||
| 62 | break; | ||
| 63 | } | ||
| 64 | } | ||
| 65 | return clk; | ||
| 66 | } | ||
| 67 | |||
| 68 | struct clk *clk_get_sys(const char *dev_id, const char *con_id) | ||
| 69 | { | ||
| 70 | struct clk *clk; | ||
| 71 | |||
| 72 | mutex_lock(&clocks_mutex); | ||
| 73 | clk = clk_find(dev_id, con_id); | ||
| 74 | if (clk && !__clk_get(clk)) | ||
| 75 | clk = NULL; | ||
| 76 | mutex_unlock(&clocks_mutex); | ||
| 77 | |||
| 78 | return clk ? clk : ERR_PTR(-ENOENT); | ||
| 79 | } | ||
| 80 | EXPORT_SYMBOL(clk_get_sys); | ||
| 81 | |||
| 82 | struct clk *clk_get(struct device *dev, const char *con_id) | ||
| 83 | { | ||
| 84 | const char *dev_id = dev ? dev_name(dev) : NULL; | ||
| 85 | |||
| 86 | return clk_get_sys(dev_id, con_id); | ||
| 87 | } | ||
| 88 | EXPORT_SYMBOL(clk_get); | ||
| 89 | |||
| 90 | void clk_put(struct clk *clk) | ||
| 91 | { | ||
| 92 | __clk_put(clk); | ||
| 93 | } | ||
| 94 | EXPORT_SYMBOL(clk_put); | ||
| 95 | |||
| 96 | void clkdev_add(struct clk_lookup *cl) | ||
| 97 | { | ||
| 98 | mutex_lock(&clocks_mutex); | ||
| 99 | list_add_tail(&cl->node, &clocks); | ||
| 100 | mutex_unlock(&clocks_mutex); | ||
| 101 | } | ||
| 102 | EXPORT_SYMBOL(clkdev_add); | ||
| 103 | |||
| 104 | void __init clkdev_add_table(struct clk_lookup *cl, size_t num) | ||
| 105 | { | ||
| 106 | mutex_lock(&clocks_mutex); | ||
| 107 | while (num--) { | ||
| 108 | list_add_tail(&cl->node, &clocks); | ||
| 109 | cl++; | ||
| 110 | } | ||
| 111 | mutex_unlock(&clocks_mutex); | ||
| 112 | } | ||
| 113 | |||
| 114 | #define MAX_DEV_ID 20 | ||
| 115 | #define MAX_CON_ID 16 | ||
| 116 | |||
| 117 | struct clk_lookup_alloc { | ||
| 118 | struct clk_lookup cl; | ||
| 119 | char dev_id[MAX_DEV_ID]; | ||
| 120 | char con_id[MAX_CON_ID]; | ||
| 121 | }; | ||
| 122 | |||
| 123 | struct clk_lookup *clkdev_alloc(struct clk *clk, const char *con_id, | ||
| 124 | const char *dev_fmt, ...) | ||
| 125 | { | ||
| 126 | struct clk_lookup_alloc *cla; | ||
| 127 | |||
| 128 | cla = kzalloc(sizeof(*cla), GFP_KERNEL); | ||
| 129 | if (!cla) | ||
| 130 | return NULL; | ||
| 131 | |||
| 132 | cla->cl.clk = clk; | ||
| 133 | if (con_id) { | ||
| 134 | strlcpy(cla->con_id, con_id, sizeof(cla->con_id)); | ||
| 135 | cla->cl.con_id = cla->con_id; | ||
| 136 | } | ||
| 137 | |||
| 138 | if (dev_fmt) { | ||
| 139 | va_list ap; | ||
| 140 | |||
| 141 | va_start(ap, dev_fmt); | ||
| 142 | vscnprintf(cla->dev_id, sizeof(cla->dev_id), dev_fmt, ap); | ||
| 143 | cla->cl.dev_id = cla->dev_id; | ||
| 144 | va_end(ap); | ||
| 145 | } | ||
| 146 | |||
| 147 | return &cla->cl; | ||
| 148 | } | ||
| 149 | EXPORT_SYMBOL(clkdev_alloc); | ||
| 150 | |||
| 151 | int clk_add_alias(const char *alias, const char *alias_dev_name, char *id, | ||
| 152 | struct device *dev) | ||
| 153 | { | ||
| 154 | struct clk *r = clk_get(dev, id); | ||
| 155 | struct clk_lookup *l; | ||
| 156 | |||
| 157 | if (IS_ERR(r)) | ||
| 158 | return PTR_ERR(r); | ||
| 159 | |||
| 160 | l = clkdev_alloc(r, alias, alias_dev_name); | ||
| 161 | clk_put(r); | ||
| 162 | if (!l) | ||
| 163 | return -ENODEV; | ||
| 164 | clkdev_add(l); | ||
| 165 | return 0; | ||
| 166 | } | ||
| 167 | EXPORT_SYMBOL(clk_add_alias); | ||
| 168 | |||
| 169 | /* | ||
| 170 | * clkdev_drop - remove a clock dynamically allocated | ||
| 171 | */ | ||
| 172 | void clkdev_drop(struct clk_lookup *cl) | ||
| 173 | { | ||
| 174 | mutex_lock(&clocks_mutex); | ||
| 175 | list_del(&cl->node); | ||
| 176 | mutex_unlock(&clocks_mutex); | ||
| 177 | kfree(cl); | ||
| 178 | } | ||
| 179 | EXPORT_SYMBOL(clkdev_drop); | ||
diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c index cc0a932bbea9..e5681636626f 100644 --- a/arch/arm/common/dmabounce.c +++ b/arch/arm/common/dmabounce.c | |||
| @@ -328,7 +328,7 @@ static inline void unmap_single(struct device *dev, dma_addr_t dma_addr, | |||
| 328 | * substitute the safe buffer for the unsafe one. | 328 | * substitute the safe buffer for the unsafe one. |
| 329 | * (basically move the buffer from an unsafe area to a safe one) | 329 | * (basically move the buffer from an unsafe area to a safe one) |
| 330 | */ | 330 | */ |
| 331 | dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size, | 331 | dma_addr_t __dma_map_single(struct device *dev, void *ptr, size_t size, |
| 332 | enum dma_data_direction dir) | 332 | enum dma_data_direction dir) |
| 333 | { | 333 | { |
| 334 | dev_dbg(dev, "%s(ptr=%p,size=%d,dir=%x)\n", | 334 | dev_dbg(dev, "%s(ptr=%p,size=%d,dir=%x)\n", |
| @@ -338,7 +338,7 @@ dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size, | |||
| 338 | 338 | ||
| 339 | return map_single(dev, ptr, size, dir); | 339 | return map_single(dev, ptr, size, dir); |
| 340 | } | 340 | } |
| 341 | EXPORT_SYMBOL(dma_map_single); | 341 | EXPORT_SYMBOL(__dma_map_single); |
| 342 | 342 | ||
| 343 | /* | 343 | /* |
| 344 | * see if a mapped address was really a "safe" buffer and if so, copy | 344 | * see if a mapped address was really a "safe" buffer and if so, copy |
| @@ -346,7 +346,7 @@ EXPORT_SYMBOL(dma_map_single); | |||
| 346 | * the safe buffer. (basically return things back to the way they | 346 | * the safe buffer. (basically return things back to the way they |
| 347 | * should be) | 347 | * should be) |
| 348 | */ | 348 | */ |
| 349 | void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, | 349 | void __dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, |
| 350 | enum dma_data_direction dir) | 350 | enum dma_data_direction dir) |
| 351 | { | 351 | { |
| 352 | dev_dbg(dev, "%s(ptr=%p,size=%d,dir=%x)\n", | 352 | dev_dbg(dev, "%s(ptr=%p,size=%d,dir=%x)\n", |
| @@ -354,9 +354,9 @@ void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, | |||
| 354 | 354 | ||
| 355 | unmap_single(dev, dma_addr, size, dir); | 355 | unmap_single(dev, dma_addr, size, dir); |
| 356 | } | 356 | } |
| 357 | EXPORT_SYMBOL(dma_unmap_single); | 357 | EXPORT_SYMBOL(__dma_unmap_single); |
| 358 | 358 | ||
| 359 | dma_addr_t dma_map_page(struct device *dev, struct page *page, | 359 | dma_addr_t __dma_map_page(struct device *dev, struct page *page, |
| 360 | unsigned long offset, size_t size, enum dma_data_direction dir) | 360 | unsigned long offset, size_t size, enum dma_data_direction dir) |
| 361 | { | 361 | { |
| 362 | dev_dbg(dev, "%s(page=%p,off=%#lx,size=%zx,dir=%x)\n", | 362 | dev_dbg(dev, "%s(page=%p,off=%#lx,size=%zx,dir=%x)\n", |
| @@ -372,7 +372,7 @@ dma_addr_t dma_map_page(struct device *dev, struct page *page, | |||
| 372 | 372 | ||
| 373 | return map_single(dev, page_address(page) + offset, size, dir); | 373 | return map_single(dev, page_address(page) + offset, size, dir); |
| 374 | } | 374 | } |
| 375 | EXPORT_SYMBOL(dma_map_page); | 375 | EXPORT_SYMBOL(__dma_map_page); |
| 376 | 376 | ||
| 377 | /* | 377 | /* |
| 378 | * see if a mapped address was really a "safe" buffer and if so, copy | 378 | * see if a mapped address was really a "safe" buffer and if so, copy |
| @@ -380,7 +380,7 @@ EXPORT_SYMBOL(dma_map_page); | |||
| 380 | * the safe buffer. (basically return things back to the way they | 380 | * the safe buffer. (basically return things back to the way they |
| 381 | * should be) | 381 | * should be) |
| 382 | */ | 382 | */ |
| 383 | void dma_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, | 383 | void __dma_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
| 384 | enum dma_data_direction dir) | 384 | enum dma_data_direction dir) |
| 385 | { | 385 | { |
| 386 | dev_dbg(dev, "%s(ptr=%p,size=%d,dir=%x)\n", | 386 | dev_dbg(dev, "%s(ptr=%p,size=%d,dir=%x)\n", |
| @@ -388,7 +388,7 @@ void dma_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, | |||
| 388 | 388 | ||
| 389 | unmap_single(dev, dma_addr, size, dir); | 389 | unmap_single(dev, dma_addr, size, dir); |
| 390 | } | 390 | } |
| 391 | EXPORT_SYMBOL(dma_unmap_page); | 391 | EXPORT_SYMBOL(__dma_unmap_page); |
| 392 | 392 | ||
| 393 | int dmabounce_sync_for_cpu(struct device *dev, dma_addr_t addr, | 393 | int dmabounce_sync_for_cpu(struct device *dev, dma_addr_t addr, |
| 394 | unsigned long off, size_t sz, enum dma_data_direction dir) | 394 | unsigned long off, size_t sz, enum dma_data_direction dir) |
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index e6388dcd8cfa..0b89ef001330 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c | |||
| @@ -35,6 +35,9 @@ | |||
| 35 | 35 | ||
| 36 | static DEFINE_SPINLOCK(irq_controller_lock); | 36 | static DEFINE_SPINLOCK(irq_controller_lock); |
| 37 | 37 | ||
| 38 | /* Address of GIC 0 CPU interface */ | ||
| 39 | void __iomem *gic_cpu_base_addr __read_mostly; | ||
| 40 | |||
| 38 | struct gic_chip_data { | 41 | struct gic_chip_data { |
| 39 | unsigned int irq_offset; | 42 | unsigned int irq_offset; |
| 40 | void __iomem *dist_base; | 43 | void __iomem *dist_base; |
| @@ -45,7 +48,7 @@ struct gic_chip_data { | |||
| 45 | #define MAX_GIC_NR 1 | 48 | #define MAX_GIC_NR 1 |
| 46 | #endif | 49 | #endif |
| 47 | 50 | ||
| 48 | static struct gic_chip_data gic_data[MAX_GIC_NR]; | 51 | static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly; |
| 49 | 52 | ||
| 50 | static inline void __iomem *gic_dist_base(unsigned int irq) | 53 | static inline void __iomem *gic_dist_base(unsigned int irq) |
| 51 | { | 54 | { |
| @@ -213,21 +216,16 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) | |||
| 213 | set_irq_chained_handler(irq, gic_handle_cascade_irq); | 216 | set_irq_chained_handler(irq, gic_handle_cascade_irq); |
| 214 | } | 217 | } |
| 215 | 218 | ||
| 216 | void __init gic_dist_init(unsigned int gic_nr, void __iomem *base, | 219 | static void __init gic_dist_init(struct gic_chip_data *gic, |
| 217 | unsigned int irq_start) | 220 | unsigned int irq_start) |
| 218 | { | 221 | { |
| 219 | unsigned int gic_irqs, irq_limit, i; | 222 | unsigned int gic_irqs, irq_limit, i; |
| 223 | void __iomem *base = gic->dist_base; | ||
| 220 | u32 cpumask = 1 << smp_processor_id(); | 224 | u32 cpumask = 1 << smp_processor_id(); |
| 221 | 225 | ||
| 222 | if (gic_nr >= MAX_GIC_NR) | ||
| 223 | BUG(); | ||
| 224 | |||
| 225 | cpumask |= cpumask << 8; | 226 | cpumask |= cpumask << 8; |
| 226 | cpumask |= cpumask << 16; | 227 | cpumask |= cpumask << 16; |
| 227 | 228 | ||
| 228 | gic_data[gic_nr].dist_base = base; | ||
| 229 | gic_data[gic_nr].irq_offset = (irq_start - 1) & ~31; | ||
| 230 | |||
| 231 | writel(0, base + GIC_DIST_CTRL); | 229 | writel(0, base + GIC_DIST_CTRL); |
| 232 | 230 | ||
| 233 | /* | 231 | /* |
| @@ -267,7 +265,7 @@ void __init gic_dist_init(unsigned int gic_nr, void __iomem *base, | |||
| 267 | /* | 265 | /* |
| 268 | * Limit number of interrupts registered to the platform maximum | 266 | * Limit number of interrupts registered to the platform maximum |
| 269 | */ | 267 | */ |
| 270 | irq_limit = gic_data[gic_nr].irq_offset + gic_irqs; | 268 | irq_limit = gic->irq_offset + gic_irqs; |
| 271 | if (WARN_ON(irq_limit > NR_IRQS)) | 269 | if (WARN_ON(irq_limit > NR_IRQS)) |
| 272 | irq_limit = NR_IRQS; | 270 | irq_limit = NR_IRQS; |
| 273 | 271 | ||
| @@ -276,7 +274,7 @@ void __init gic_dist_init(unsigned int gic_nr, void __iomem *base, | |||
| 276 | */ | 274 | */ |
| 277 | for (i = irq_start; i < irq_limit; i++) { | 275 | for (i = irq_start; i < irq_limit; i++) { |
| 278 | set_irq_chip(i, &gic_chip); | 276 | set_irq_chip(i, &gic_chip); |
| 279 | set_irq_chip_data(i, &gic_data[gic_nr]); | 277 | set_irq_chip_data(i, gic); |
| 280 | set_irq_handler(i, handle_level_irq); | 278 | set_irq_handler(i, handle_level_irq); |
| 281 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 279 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
| 282 | } | 280 | } |
| @@ -284,19 +282,12 @@ void __init gic_dist_init(unsigned int gic_nr, void __iomem *base, | |||
| 284 | writel(1, base + GIC_DIST_CTRL); | 282 | writel(1, base + GIC_DIST_CTRL); |
| 285 | } | 283 | } |
| 286 | 284 | ||
| 287 | void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base) | 285 | static void __cpuinit gic_cpu_init(struct gic_chip_data *gic) |
| 288 | { | 286 | { |
| 289 | void __iomem *dist_base; | 287 | void __iomem *dist_base = gic->dist_base; |
| 288 | void __iomem *base = gic->cpu_base; | ||
| 290 | int i; | 289 | int i; |
| 291 | 290 | ||
| 292 | if (gic_nr >= MAX_GIC_NR) | ||
| 293 | BUG(); | ||
| 294 | |||
| 295 | dist_base = gic_data[gic_nr].dist_base; | ||
| 296 | BUG_ON(!dist_base); | ||
| 297 | |||
| 298 | gic_data[gic_nr].cpu_base = base; | ||
| 299 | |||
| 300 | /* | 291 | /* |
| 301 | * Deal with the banked PPI and SGI interrupts - disable all | 292 | * Deal with the banked PPI and SGI interrupts - disable all |
| 302 | * PPI interrupts, ensure all SGI interrupts are enabled. | 293 | * PPI interrupts, ensure all SGI interrupts are enabled. |
| @@ -314,6 +305,42 @@ void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base) | |||
| 314 | writel(1, base + GIC_CPU_CTRL); | 305 | writel(1, base + GIC_CPU_CTRL); |
| 315 | } | 306 | } |
| 316 | 307 | ||
| 308 | void __init gic_init(unsigned int gic_nr, unsigned int irq_start, | ||
| 309 | void __iomem *dist_base, void __iomem *cpu_base) | ||
| 310 | { | ||
| 311 | struct gic_chip_data *gic; | ||
| 312 | |||
| 313 | BUG_ON(gic_nr >= MAX_GIC_NR); | ||
| 314 | |||
| 315 | gic = &gic_data[gic_nr]; | ||
| 316 | gic->dist_base = dist_base; | ||
| 317 | gic->cpu_base = cpu_base; | ||
| 318 | gic->irq_offset = (irq_start - 1) & ~31; | ||
| 319 | |||
| 320 | if (gic_nr == 0) | ||
| 321 | gic_cpu_base_addr = cpu_base; | ||
| 322 | |||
| 323 | gic_dist_init(gic, irq_start); | ||
| 324 | gic_cpu_init(gic); | ||
| 325 | } | ||
| 326 | |||
| 327 | void __cpuinit gic_secondary_init(unsigned int gic_nr) | ||
| 328 | { | ||
| 329 | BUG_ON(gic_nr >= MAX_GIC_NR); | ||
| 330 | |||
| 331 | gic_cpu_init(&gic_data[gic_nr]); | ||
| 332 | } | ||
| 333 | |||
| 334 | void __cpuinit gic_enable_ppi(unsigned int irq) | ||
| 335 | { | ||
| 336 | unsigned long flags; | ||
| 337 | |||
| 338 | local_irq_save(flags); | ||
| 339 | irq_to_desc(irq)->status |= IRQ_NOPROBE; | ||
| 340 | gic_unmask_irq(irq); | ||
| 341 | local_irq_restore(flags); | ||
| 342 | } | ||
| 343 | |||
| 317 | #ifdef CONFIG_SMP | 344 | #ifdef CONFIG_SMP |
| 318 | void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) | 345 | void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) |
| 319 | { | 346 | { |
diff --git a/arch/arm/plat-versatile/timer-sp.c b/arch/arm/common/timer-sp.c index fb0d1c299718..6ef3342153b9 100644 --- a/arch/arm/plat-versatile/timer-sp.c +++ b/arch/arm/common/timer-sp.c | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * linux/arch/arm/plat-versatile/timer-sp.c | 2 | * linux/arch/arm/common/timer-sp.c |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 1999 - 2003 ARM Limited | 4 | * Copyright (C) 1999 - 2003 ARM Limited |
| 5 | * Copyright (C) 2000 Deep Blue Solutions Ltd | 5 | * Copyright (C) 2000 Deep Blue Solutions Ltd |
| @@ -26,8 +26,6 @@ | |||
| 26 | 26 | ||
| 27 | #include <asm/hardware/arm_timer.h> | 27 | #include <asm/hardware/arm_timer.h> |
| 28 | 28 | ||
| 29 | #include <plat/timer-sp.h> | ||
| 30 | |||
| 31 | /* | 29 | /* |
| 32 | * These timers are currently always setup to be clocked at 1MHz. | 30 | * These timers are currently always setup to be clocked at 1MHz. |
| 33 | */ | 31 | */ |
| @@ -46,7 +44,6 @@ static struct clocksource clocksource_sp804 = { | |||
| 46 | .rating = 200, | 44 | .rating = 200, |
| 47 | .read = sp804_read, | 45 | .read = sp804_read, |
| 48 | .mask = CLOCKSOURCE_MASK(32), | 46 | .mask = CLOCKSOURCE_MASK(32), |
| 49 | .shift = 20, | ||
| 50 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 47 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 51 | }; | 48 | }; |
| 52 | 49 | ||
| @@ -63,8 +60,7 @@ void __init sp804_clocksource_init(void __iomem *base) | |||
| 63 | writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, | 60 | writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, |
| 64 | clksrc_base + TIMER_CTRL); | 61 | clksrc_base + TIMER_CTRL); |
| 65 | 62 | ||
| 66 | cs->mult = clocksource_khz2mult(TIMER_FREQ_KHZ, cs->shift); | 63 | clocksource_register_khz(cs, TIMER_FREQ_KHZ); |
| 67 | clocksource_register(cs); | ||
| 68 | } | 64 | } |
| 69 | 65 | ||
| 70 | 66 | ||
diff --git a/arch/arm/configs/ag5evm_defconfig b/arch/arm/configs/ag5evm_defconfig new file mode 100644 index 000000000000..2b9cf56db363 --- /dev/null +++ b/arch/arm/configs/ag5evm_defconfig | |||
| @@ -0,0 +1,83 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | ||
| 3 | CONFIG_IKCONFIG=y | ||
| 4 | CONFIG_IKCONFIG_PROC=y | ||
| 5 | CONFIG_LOG_BUF_SHIFT=16 | ||
| 6 | CONFIG_NAMESPACES=y | ||
| 7 | # CONFIG_UTS_NS is not set | ||
| 8 | # CONFIG_IPC_NS is not set | ||
| 9 | # CONFIG_USER_NS is not set | ||
| 10 | # CONFIG_PID_NS is not set | ||
| 11 | CONFIG_BLK_DEV_INITRD=y | ||
| 12 | CONFIG_INITRAMFS_SOURCE="" | ||
| 13 | CONFIG_EMBEDDED=y | ||
| 14 | CONFIG_SLAB=y | ||
| 15 | # CONFIG_BLK_DEV_BSG is not set | ||
| 16 | # CONFIG_IOSCHED_DEADLINE is not set | ||
| 17 | # CONFIG_IOSCHED_CFQ is not set | ||
| 18 | CONFIG_ARCH_SHMOBILE=y | ||
| 19 | CONFIG_ARCH_SH73A0=y | ||
| 20 | CONFIG_MACH_AG5EVM=y | ||
| 21 | CONFIG_MEMORY_SIZE=0x10000000 | ||
| 22 | CONFIG_CPU_BPREDICT_DISABLE=y | ||
| 23 | CONFIG_ARM_ERRATA_430973=y | ||
| 24 | CONFIG_ARM_ERRATA_458693=y | ||
| 25 | CONFIG_NO_HZ=y | ||
| 26 | CONFIG_AEABI=y | ||
| 27 | # CONFIG_OABI_COMPAT is not set | ||
| 28 | CONFIG_HIGHMEM=y | ||
| 29 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 30 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 31 | CONFIG_CMDLINE="console=tty0 console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel" | ||
| 32 | CONFIG_CMDLINE_FORCE=y | ||
| 33 | CONFIG_KEXEC=y | ||
| 34 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 35 | CONFIG_PM=y | ||
| 36 | # CONFIG_SUSPEND is not set | ||
| 37 | CONFIG_PM_RUNTIME=y | ||
| 38 | CONFIG_NET=y | ||
| 39 | CONFIG_PACKET=y | ||
| 40 | CONFIG_UNIX=y | ||
| 41 | CONFIG_INET=y | ||
| 42 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | ||
| 43 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | ||
| 44 | # CONFIG_INET_XFRM_MODE_BEET is not set | ||
| 45 | # CONFIG_INET_LRO is not set | ||
| 46 | # CONFIG_INET_DIAG is not set | ||
| 47 | # CONFIG_IPV6 is not set | ||
| 48 | # CONFIG_WIRELESS is not set | ||
| 49 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 50 | # CONFIG_BLK_DEV is not set | ||
| 51 | CONFIG_NETDEVICES=y | ||
| 52 | CONFIG_NET_ETHERNET=y | ||
| 53 | CONFIG_SMSC911X=y | ||
| 54 | # CONFIG_NETDEV_1000 is not set | ||
| 55 | # CONFIG_NETDEV_10000 is not set | ||
| 56 | # CONFIG_WLAN is not set | ||
| 57 | CONFIG_INPUT_SPARSEKMAP=y | ||
| 58 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | ||
| 59 | CONFIG_INPUT_EVDEV=y | ||
| 60 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 61 | # CONFIG_INPUT_MOUSE is not set | ||
| 62 | CONFIG_SERIAL_SH_SCI=y | ||
| 63 | CONFIG_SERIAL_SH_SCI_NR_UARTS=9 | ||
| 64 | CONFIG_SERIAL_SH_SCI_CONSOLE=y | ||
| 65 | # CONFIG_LEGACY_PTYS is not set | ||
| 66 | # CONFIG_HW_RANDOM is not set | ||
| 67 | CONFIG_I2C=y | ||
| 68 | CONFIG_I2C_SH_MOBILE=y | ||
| 69 | # CONFIG_HWMON is not set | ||
| 70 | # CONFIG_MFD_SUPPORT is not set | ||
| 71 | CONFIG_FB=y | ||
| 72 | CONFIG_FB_SH_MOBILE_LCDC=y | ||
| 73 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 74 | CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y | ||
| 75 | # CONFIG_HID_SUPPORT is not set | ||
| 76 | # CONFIG_USB_SUPPORT is not set | ||
| 77 | # CONFIG_DNOTIFY is not set | ||
| 78 | # CONFIG_INOTIFY_USER is not set | ||
| 79 | CONFIG_TMPFS=y | ||
| 80 | # CONFIG_MISC_FILESYSTEMS is not set | ||
| 81 | CONFIG_MAGIC_SYSRQ=y | ||
| 82 | CONFIG_DEBUG_KERNEL=y | ||
| 83 | # CONFIG_FTRACE is not set | ||
diff --git a/arch/arm/configs/ams_delta_defconfig b/arch/arm/configs/ams_delta_defconfig deleted file mode 100644 index 75de45e949b9..000000000000 --- a/arch/arm/configs/ams_delta_defconfig +++ /dev/null | |||
| @@ -1,121 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | # CONFIG_SWAP is not set | ||
| 3 | CONFIG_SYSVIPC=y | ||
| 4 | CONFIG_TREE_PREEMPT_RCU=y | ||
| 5 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 6 | CONFIG_BLK_DEV_INITRD=y | ||
| 7 | CONFIG_EMBEDDED=y | ||
| 8 | # CONFIG_KALLSYMS is not set | ||
| 9 | CONFIG_SLAB=y | ||
| 10 | CONFIG_MODULES=y | ||
| 11 | CONFIG_MODULE_UNLOAD=y | ||
| 12 | CONFIG_MODULE_FORCE_UNLOAD=y | ||
| 13 | # CONFIG_LBDAF is not set | ||
| 14 | CONFIG_ARCH_OMAP=y | ||
| 15 | CONFIG_ARCH_OMAP1=y | ||
| 16 | CONFIG_OMAP_MBOX_FWK=m | ||
| 17 | CONFIG_MACH_AMS_DELTA=y | ||
| 18 | CONFIG_OMAP_ARM_150MHZ=y | ||
| 19 | # CONFIG_OMAP_ARM_60MHZ is not set | ||
| 20 | CONFIG_PREEMPT=y | ||
| 21 | CONFIG_AEABI=y | ||
| 22 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 23 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 24 | CONFIG_CMDLINE="mem=32M console=ttyS0,115200n8 root=/dev/ram0 initrd=0x11c00000,4M" | ||
| 25 | CONFIG_FPE_NWFPE=y | ||
| 26 | CONFIG_PM=y | ||
| 27 | # CONFIG_SUSPEND is not set | ||
| 28 | CONFIG_PM_RUNTIME=y | ||
| 29 | CONFIG_NET=y | ||
| 30 | CONFIG_PACKET=y | ||
| 31 | CONFIG_UNIX=y | ||
| 32 | CONFIG_INET=y | ||
| 33 | CONFIG_IP_MULTICAST=y | ||
| 34 | CONFIG_IPV6=y | ||
| 35 | # CONFIG_FW_LOADER is not set | ||
| 36 | CONFIG_MTD=y | ||
| 37 | CONFIG_MTD_PARTITIONS=y | ||
| 38 | CONFIG_MTD_CHAR=y | ||
| 39 | CONFIG_MTD_BLOCK=y | ||
| 40 | CONFIG_MTD_NAND=y | ||
| 41 | CONFIG_MTD_NAND_AMS_DELTA=y | ||
| 42 | CONFIG_BLK_DEV_LOOP=y | ||
| 43 | CONFIG_BLK_DEV_RAM=y | ||
| 44 | CONFIG_BLK_DEV_RAM_SIZE=8192 | ||
| 45 | CONFIG_SCSI=y | ||
| 46 | CONFIG_BLK_DEV_SD=y | ||
| 47 | CONFIG_NETDEVICES=y | ||
| 48 | CONFIG_NET_ETHERNET=y | ||
| 49 | CONFIG_USB_CATC=y | ||
| 50 | CONFIG_USB_KAWETH=y | ||
| 51 | CONFIG_USB_PEGASUS=y | ||
| 52 | CONFIG_USB_RTL8150=y | ||
| 53 | CONFIG_USB_USBNET=y | ||
| 54 | CONFIG_PPP=y | ||
| 55 | CONFIG_PPP_MULTILINK=y | ||
| 56 | CONFIG_INPUT_EVDEV=y | ||
| 57 | CONFIG_KEYBOARD_OMAP=y | ||
| 58 | # CONFIG_INPUT_MOUSE is not set | ||
| 59 | CONFIG_SERIAL_8250=y | ||
| 60 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 61 | # CONFIG_LEGACY_PTYS is not set | ||
| 62 | CONFIG_HW_RANDOM=y | ||
| 63 | CONFIG_I2C=y | ||
| 64 | CONFIG_I2C_CHARDEV=y | ||
| 65 | CONFIG_I2C_OMAP=y | ||
| 66 | CONFIG_GPIO_SYSFS=y | ||
| 67 | # CONFIG_HWMON is not set | ||
| 68 | CONFIG_FB=y | ||
| 69 | CONFIG_FIRMWARE_EDID=y | ||
| 70 | CONFIG_FB_OMAP=y | ||
| 71 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | ||
| 72 | CONFIG_LCD_CLASS_DEVICE=y | ||
| 73 | # CONFIG_VGA_CONSOLE is not set | ||
| 74 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 75 | CONFIG_FONTS=y | ||
| 76 | CONFIG_FONT_6x11=y | ||
| 77 | CONFIG_LOGO=y | ||
| 78 | # CONFIG_LOGO_LINUX_MONO is not set | ||
| 79 | # CONFIG_LOGO_LINUX_VGA16 is not set | ||
| 80 | CONFIG_SOUND=y | ||
| 81 | CONFIG_SND=y | ||
| 82 | CONFIG_SND_MIXER_OSS=y | ||
| 83 | CONFIG_SND_PCM_OSS=y | ||
| 84 | CONFIG_SND_SOC=y | ||
| 85 | CONFIG_SND_OMAP_SOC=y | ||
| 86 | CONFIG_SND_OMAP_SOC_AMS_DELTA=y | ||
| 87 | CONFIG_USB=y | ||
| 88 | CONFIG_USB_DEVICEFS=y | ||
| 89 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 90 | CONFIG_USB_MON=y | ||
| 91 | CONFIG_USB_OHCI_HCD=y | ||
| 92 | CONFIG_USB_STORAGE=y | ||
| 93 | CONFIG_NEW_LEDS=y | ||
| 94 | CONFIG_LEDS_CLASS=y | ||
| 95 | CONFIG_LEDS_AMS_DELTA=y | ||
| 96 | CONFIG_LEDS_TRIGGERS=y | ||
| 97 | CONFIG_LEDS_TRIGGER_TIMER=y | ||
| 98 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
| 99 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=y | ||
| 100 | CONFIG_RTC_CLASS=y | ||
| 101 | CONFIG_RTC_DRV_OMAP=y | ||
| 102 | CONFIG_EXT2_FS=y | ||
| 103 | CONFIG_EXT3_FS=y | ||
| 104 | CONFIG_INOTIFY=y | ||
| 105 | CONFIG_AUTOFS_FS=y | ||
| 106 | CONFIG_AUTOFS4_FS=y | ||
| 107 | CONFIG_MSDOS_FS=y | ||
| 108 | CONFIG_VFAT_FS=y | ||
| 109 | CONFIG_TMPFS=y | ||
| 110 | CONFIG_JFFS2_FS=y | ||
| 111 | CONFIG_JFFS2_SUMMARY=y | ||
| 112 | CONFIG_NFS_FS=y | ||
| 113 | CONFIG_PARTITION_ADVANCED=y | ||
| 114 | CONFIG_NLS_CODEPAGE_437=y | ||
| 115 | CONFIG_NLS_CODEPAGE_850=y | ||
| 116 | CONFIG_NLS_CODEPAGE_852=y | ||
| 117 | CONFIG_NLS_ISO8859_1=y | ||
| 118 | CONFIG_NLS_ISO8859_2=y | ||
| 119 | CONFIG_MAGIC_SYSRQ=y | ||
| 120 | CONFIG_DEBUG_KERNEL=y | ||
| 121 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
diff --git a/arch/arm/configs/htcherald_defconfig b/arch/arm/configs/htcherald_defconfig deleted file mode 100644 index edfa1c0daab0..000000000000 --- a/arch/arm/configs/htcherald_defconfig +++ /dev/null | |||
| @@ -1,73 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | ||
| 3 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 4 | CONFIG_BLK_DEV_INITRD=y | ||
| 5 | CONFIG_SLAB=y | ||
| 6 | CONFIG_MODULES=y | ||
| 7 | CONFIG_MODULE_UNLOAD=y | ||
| 8 | # CONFIG_BLK_DEV_BSG is not set | ||
| 9 | CONFIG_ARCH_OMAP=y | ||
| 10 | CONFIG_ARCH_OMAP1=y | ||
| 11 | CONFIG_ARCH_OMAP850=y | ||
| 12 | # CONFIG_ARCH_OMAP15XX is not set | ||
| 13 | CONFIG_MACH_HERALD=y | ||
| 14 | CONFIG_OMAP_ARM_195MHZ=y | ||
| 15 | # CONFIG_OMAP_ARM_60MHZ is not set | ||
| 16 | CONFIG_CPU_ARM925T=y | ||
| 17 | CONFIG_PREEMPT=y | ||
| 18 | CONFIG_AEABI=y | ||
| 19 | CONFIG_LEDS=y | ||
| 20 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 21 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 22 | CONFIG_CMDLINE="mem=32M console=ttyS0,115200 ip=dhcp" | ||
| 23 | CONFIG_FPE_NWFPE=y | ||
| 24 | CONFIG_PM=y | ||
| 25 | CONFIG_NET=y | ||
| 26 | CONFIG_PACKET=y | ||
| 27 | CONFIG_UNIX=y | ||
| 28 | CONFIG_INET=y | ||
| 29 | CONFIG_IP_MULTICAST=y | ||
| 30 | CONFIG_IP_PNP=y | ||
| 31 | CONFIG_IP_PNP_DHCP=y | ||
| 32 | CONFIG_IP_PNP_BOOTP=y | ||
| 33 | # CONFIG_IPV6 is not set | ||
| 34 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 35 | CONFIG_BLK_DEV_LOOP=y | ||
| 36 | CONFIG_BLK_DEV_RAM=y | ||
| 37 | CONFIG_BLK_DEV_RAM_SIZE=8192 | ||
| 38 | CONFIG_NETDEVICES=y | ||
| 39 | CONFIG_NET_ETHERNET=y | ||
| 40 | CONFIG_SMC91X=y | ||
| 41 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 42 | CONFIG_KEYBOARD_OMAP=y | ||
| 43 | # CONFIG_INPUT_MOUSE is not set | ||
| 44 | CONFIG_SERIAL_8250=m | ||
| 45 | # CONFIG_LEGACY_PTYS is not set | ||
| 46 | CONFIG_VIDEO_OUTPUT_CONTROL=m | ||
| 47 | CONFIG_FB=y | ||
| 48 | CONFIG_FB_MODE_HELPERS=y | ||
| 49 | CONFIG_FB_OMAP=y | ||
| 50 | # CONFIG_VGA_CONSOLE is not set | ||
| 51 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 52 | CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y | ||
| 53 | CONFIG_FONTS=y | ||
| 54 | CONFIG_FONT_MINI_4x6=y | ||
| 55 | CONFIG_USB_GADGET=y | ||
| 56 | CONFIG_USB_ETH=m | ||
| 57 | # CONFIG_USB_ETH_RNDIS is not set | ||
| 58 | CONFIG_MMC=y | ||
| 59 | CONFIG_MMC_SDHCI=y | ||
| 60 | CONFIG_MMC_SDHCI_PLTFM=y | ||
| 61 | CONFIG_MMC_OMAP=y | ||
| 62 | CONFIG_RTC_CLASS=y | ||
| 63 | CONFIG_EXT2_FS=y | ||
| 64 | CONFIG_EXT3_FS=y | ||
| 65 | CONFIG_INOTIFY=y | ||
| 66 | CONFIG_TMPFS=y | ||
| 67 | CONFIG_NFS_FS=y | ||
| 68 | CONFIG_ROOT_NFS=y | ||
| 69 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 70 | CONFIG_CRYPTO_DEFLATE=y | ||
| 71 | CONFIG_CRYPTO_ZLIB=y | ||
| 72 | CONFIG_CRYPTO_LZO=y | ||
| 73 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
diff --git a/arch/arm/configs/mackerel_defconfig b/arch/arm/configs/mackerel_defconfig new file mode 100644 index 000000000000..306a2e2d3622 --- /dev/null +++ b/arch/arm/configs/mackerel_defconfig | |||
| @@ -0,0 +1,138 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | ||
| 3 | CONFIG_IKCONFIG=y | ||
| 4 | CONFIG_IKCONFIG_PROC=y | ||
| 5 | CONFIG_LOG_BUF_SHIFT=16 | ||
| 6 | # CONFIG_UTS_NS is not set | ||
| 7 | # CONFIG_IPC_NS is not set | ||
| 8 | # CONFIG_USER_NS is not set | ||
| 9 | # CONFIG_PID_NS is not set | ||
| 10 | # CONFIG_NET_NS is not set | ||
| 11 | CONFIG_SLAB=y | ||
| 12 | CONFIG_MODULES=y | ||
| 13 | CONFIG_MODULE_UNLOAD=y | ||
| 14 | # CONFIG_BLK_DEV_BSG is not set | ||
| 15 | # CONFIG_IOSCHED_DEADLINE is not set | ||
| 16 | # CONFIG_IOSCHED_CFQ is not set | ||
| 17 | CONFIG_ARCH_SHMOBILE=y | ||
| 18 | CONFIG_ARCH_SH7372=y | ||
| 19 | CONFIG_MACH_MACKEREL=y | ||
| 20 | CONFIG_MEMORY_SIZE=0x10000000 | ||
| 21 | CONFIG_AEABI=y | ||
| 22 | # CONFIG_OABI_COMPAT is not set | ||
| 23 | CONFIG_FORCE_MAX_ZONEORDER=15 | ||
| 24 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 25 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 26 | CONFIG_CMDLINE="console=tty0, console=ttySC0,115200 earlyprintk=sh-sci.0,115200 root=/dev/nfs nfsroot=,tcp,v3 ip=dhcp memchunk.vpu=64m memchunk.veu0=8m memchunk.spu0=2m mem=240m" | ||
| 27 | CONFIG_KEXEC=y | ||
| 28 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 29 | CONFIG_PM=y | ||
| 30 | CONFIG_PM_RUNTIME=y | ||
| 31 | CONFIG_NET=y | ||
| 32 | CONFIG_PACKET=y | ||
| 33 | CONFIG_UNIX=y | ||
| 34 | CONFIG_INET=y | ||
| 35 | CONFIG_IP_MULTICAST=y | ||
| 36 | CONFIG_IP_PNP=y | ||
| 37 | CONFIG_IP_PNP_DHCP=y | ||
| 38 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | ||
| 39 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | ||
| 40 | # CONFIG_INET_XFRM_MODE_BEET is not set | ||
| 41 | # CONFIG_IPV6 is not set | ||
| 42 | # CONFIG_WIRELESS is not set | ||
| 43 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 44 | # CONFIG_FIRMWARE_IN_KERNEL is not set | ||
| 45 | CONFIG_MTD=y | ||
| 46 | CONFIG_MTD_CONCAT=y | ||
| 47 | CONFIG_MTD_PARTITIONS=y | ||
| 48 | CONFIG_MTD_CHAR=y | ||
| 49 | CONFIG_MTD_BLOCK=y | ||
| 50 | CONFIG_MTD_CFI=y | ||
| 51 | CONFIG_MTD_CFI_ADV_OPTIONS=y | ||
| 52 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 53 | CONFIG_MTD_PHYSMAP=y | ||
| 54 | CONFIG_MTD_ARM_INTEGRATOR=y | ||
| 55 | CONFIG_MTD_BLOCK2MTD=y | ||
| 56 | CONFIG_SCSI=y | ||
| 57 | CONFIG_BLK_DEV_SD=y | ||
| 58 | # CONFIG_SCSI_LOWLEVEL is not set | ||
| 59 | CONFIG_NETDEVICES=y | ||
| 60 | CONFIG_NET_ETHERNET=y | ||
| 61 | CONFIG_SMSC911X=y | ||
| 62 | # CONFIG_NETDEV_1000 is not set | ||
| 63 | # CONFIG_NETDEV_10000 is not set | ||
| 64 | # CONFIG_WLAN is not set | ||
| 65 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | ||
| 66 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 67 | # CONFIG_INPUT_MOUSE is not set | ||
| 68 | CONFIG_SERIAL_SH_SCI=y | ||
| 69 | CONFIG_SERIAL_SH_SCI_NR_UARTS=8 | ||
| 70 | CONFIG_SERIAL_SH_SCI_CONSOLE=y | ||
| 71 | # CONFIG_LEGACY_PTYS is not set | ||
| 72 | # CONFIG_HW_RANDOM is not set | ||
| 73 | # CONFIG_HWMON is not set | ||
| 74 | # CONFIG_MFD_SUPPORT is not set | ||
| 75 | CONFIG_FB=y | ||
| 76 | CONFIG_FB_MODE_HELPERS=y | ||
| 77 | CONFIG_FB_SH_MOBILE_LCDC=y | ||
| 78 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 79 | CONFIG_LOGO=y | ||
| 80 | # CONFIG_LOGO_LINUX_MONO is not set | ||
| 81 | # CONFIG_LOGO_LINUX_CLUT224 is not set | ||
| 82 | # CONFIG_HID_SUPPORT is not set | ||
| 83 | # CONFIG_USB_SUPPORT is not set | ||
| 84 | CONFIG_EXT2_FS=y | ||
| 85 | CONFIG_EXT2_FS_XATTR=y | ||
| 86 | CONFIG_EXT2_FS_POSIX_ACL=y | ||
| 87 | CONFIG_EXT2_FS_SECURITY=y | ||
| 88 | CONFIG_EXT2_FS_XIP=y | ||
| 89 | CONFIG_EXT3_FS=y | ||
| 90 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set | ||
| 91 | CONFIG_EXT3_FS_POSIX_ACL=y | ||
| 92 | CONFIG_EXT3_FS_SECURITY=y | ||
| 93 | # CONFIG_DNOTIFY is not set | ||
| 94 | # CONFIG_INOTIFY_USER is not set | ||
| 95 | CONFIG_MSDOS_FS=y | ||
| 96 | CONFIG_VFAT_FS=y | ||
| 97 | CONFIG_TMPFS=y | ||
| 98 | # CONFIG_MISC_FILESYSTEMS is not set | ||
| 99 | CONFIG_NFS_FS=y | ||
| 100 | CONFIG_NFS_V3=y | ||
| 101 | CONFIG_NFS_V3_ACL=y | ||
| 102 | CONFIG_NFS_V4=y | ||
| 103 | CONFIG_NFS_V4_1=y | ||
| 104 | CONFIG_ROOT_NFS=y | ||
| 105 | CONFIG_NLS_CODEPAGE_437=y | ||
| 106 | CONFIG_NLS_CODEPAGE_737=y | ||
| 107 | CONFIG_NLS_CODEPAGE_775=y | ||
| 108 | CONFIG_NLS_CODEPAGE_850=y | ||
| 109 | CONFIG_NLS_CODEPAGE_852=y | ||
| 110 | CONFIG_NLS_CODEPAGE_855=y | ||
| 111 | CONFIG_NLS_CODEPAGE_857=y | ||
| 112 | CONFIG_NLS_CODEPAGE_860=y | ||
| 113 | CONFIG_NLS_CODEPAGE_861=y | ||
| 114 | CONFIG_NLS_CODEPAGE_862=y | ||
| 115 | CONFIG_NLS_CODEPAGE_863=y | ||
| 116 | CONFIG_NLS_CODEPAGE_864=y | ||
| 117 | CONFIG_NLS_CODEPAGE_865=y | ||
| 118 | CONFIG_NLS_CODEPAGE_866=y | ||
| 119 | CONFIG_NLS_CODEPAGE_869=y | ||
| 120 | CONFIG_NLS_ISO8859_1=y | ||
| 121 | CONFIG_NLS_ISO8859_2=y | ||
| 122 | CONFIG_NLS_ISO8859_3=y | ||
| 123 | CONFIG_NLS_ISO8859_4=y | ||
| 124 | CONFIG_NLS_ISO8859_5=y | ||
| 125 | CONFIG_NLS_ISO8859_6=y | ||
| 126 | CONFIG_NLS_ISO8859_7=y | ||
| 127 | CONFIG_NLS_ISO8859_9=y | ||
| 128 | CONFIG_NLS_ISO8859_13=y | ||
| 129 | CONFIG_NLS_ISO8859_14=y | ||
| 130 | CONFIG_NLS_ISO8859_15=y | ||
| 131 | CONFIG_NLS_KOI8_R=y | ||
| 132 | CONFIG_NLS_KOI8_U=y | ||
| 133 | CONFIG_NLS_UTF8=y | ||
| 134 | # CONFIG_ENABLE_WARN_DEPRECATED is not set | ||
| 135 | # CONFIG_ENABLE_MUST_CHECK is not set | ||
| 136 | # CONFIG_ARM_UNWIND is not set | ||
| 137 | CONFIG_CRYPTO=y | ||
| 138 | CONFIG_CRYPTO_ANSI_CPRNG=y | ||
diff --git a/arch/arm/configs/mx3_defconfig b/arch/arm/configs/mx3_defconfig index f0c339fd5d21..e648ea3429be 100644 --- a/arch/arm/configs/mx3_defconfig +++ b/arch/arm/configs/mx3_defconfig | |||
| @@ -84,6 +84,7 @@ CONFIG_SERIAL_IMX_CONSOLE=y | |||
| 84 | CONFIG_I2C=y | 84 | CONFIG_I2C=y |
| 85 | CONFIG_I2C_CHARDEV=y | 85 | CONFIG_I2C_CHARDEV=y |
| 86 | CONFIG_I2C_IMX=y | 86 | CONFIG_I2C_IMX=y |
| 87 | CONFIG_SPI=y | ||
| 87 | CONFIG_W1=y | 88 | CONFIG_W1=y |
| 88 | CONFIG_W1_MASTER_MXC=y | 89 | CONFIG_W1_MASTER_MXC=y |
| 89 | CONFIG_W1_SLAVE_THERM=y | 90 | CONFIG_W1_SLAVE_THERM=y |
diff --git a/arch/arm/configs/n770_defconfig b/arch/arm/configs/n770_defconfig deleted file mode 100644 index 993e94df5d0e..000000000000 --- a/arch/arm/configs/n770_defconfig +++ /dev/null | |||
| @@ -1,138 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | ||
| 3 | CONFIG_POSIX_MQUEUE=y | ||
| 4 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 5 | CONFIG_SLAB=y | ||
| 6 | CONFIG_MODULES=y | ||
| 7 | CONFIG_MODULE_UNLOAD=y | ||
| 8 | # CONFIG_BLK_DEV_BSG is not set | ||
| 9 | # CONFIG_IOSCHED_DEADLINE is not set | ||
| 10 | CONFIG_ARCH_OMAP=y | ||
| 11 | CONFIG_ARCH_OMAP1=y | ||
| 12 | CONFIG_OMAP_RESET_CLOCKS=y | ||
| 13 | # CONFIG_OMAP_MUX is not set | ||
| 14 | CONFIG_OMAP_MBOX_FWK=y | ||
| 15 | CONFIG_OMAP_32K_TIMER=y | ||
| 16 | CONFIG_OMAP_DM_TIMER=y | ||
| 17 | # CONFIG_ARCH_OMAP15XX is not set | ||
| 18 | CONFIG_ARCH_OMAP16XX=y | ||
| 19 | CONFIG_MACH_NOKIA770=y | ||
| 20 | CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER=y | ||
| 21 | CONFIG_OMAP_ARM_216MHZ=y | ||
| 22 | # CONFIG_OMAP_ARM_60MHZ is not set | ||
| 23 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 24 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 25 | CONFIG_CMDLINE="root=1f03 rootfstype=jffs2 time" | ||
| 26 | CONFIG_FPE_NWFPE=y | ||
| 27 | CONFIG_PM=y | ||
| 28 | CONFIG_PM_RUNTIME=y | ||
| 29 | CONFIG_NET=y | ||
| 30 | CONFIG_PACKET=y | ||
| 31 | CONFIG_UNIX=y | ||
| 32 | CONFIG_INET=y | ||
| 33 | CONFIG_IP_MULTICAST=y | ||
| 34 | CONFIG_IP_PNP=y | ||
| 35 | CONFIG_IP_PNP_DHCP=y | ||
| 36 | CONFIG_IP_PNP_BOOTP=y | ||
| 37 | # CONFIG_INET_LRO is not set | ||
| 38 | # CONFIG_INET_DIAG is not set | ||
| 39 | # CONFIG_IPV6 is not set | ||
| 40 | CONFIG_NETFILTER=y | ||
| 41 | CONFIG_BT=y | ||
| 42 | CONFIG_BT_L2CAP=y | ||
| 43 | CONFIG_BT_SCO=y | ||
| 44 | CONFIG_BT_RFCOMM=y | ||
| 45 | CONFIG_BT_RFCOMM_TTY=y | ||
| 46 | CONFIG_BT_BNEP=y | ||
| 47 | CONFIG_BT_HIDP=y | ||
| 48 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 49 | CONFIG_CONNECTOR=y | ||
| 50 | # CONFIG_PROC_EVENTS is not set | ||
| 51 | CONFIG_MTD=y | ||
| 52 | CONFIG_MTD_PARTITIONS=y | ||
| 53 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 54 | CONFIG_MTD_CHAR=y | ||
| 55 | CONFIG_MTD_BLOCK=y | ||
| 56 | CONFIG_MTD_NAND=y | ||
| 57 | CONFIG_BLK_DEV_LOOP=y | ||
| 58 | CONFIG_SCSI=y | ||
| 59 | # CONFIG_SCSI_PROC_FS is not set | ||
| 60 | CONFIG_BLK_DEV_SD=y | ||
| 61 | CONFIG_NETDEVICES=y | ||
| 62 | CONFIG_TUN=y | ||
| 63 | CONFIG_NET_ETHERNET=y | ||
| 64 | CONFIG_USB_USBNET=y | ||
| 65 | # CONFIG_USB_NET_AX8817X is not set | ||
| 66 | # CONFIG_USB_NET_CDC_SUBSET is not set | ||
| 67 | CONFIG_PPP=y | ||
| 68 | CONFIG_PPP_FILTER=y | ||
| 69 | CONFIG_PPP_ASYNC=y | ||
| 70 | CONFIG_PPP_DEFLATE=y | ||
| 71 | CONFIG_PPP_BSDCOMP=y | ||
| 72 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | ||
| 73 | CONFIG_INPUT_EVDEV=y | ||
| 74 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 75 | CONFIG_KEYBOARD_OMAP=y | ||
| 76 | # CONFIG_INPUT_MOUSE is not set | ||
| 77 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 78 | CONFIG_TOUCHSCREEN_ADS7846=y | ||
| 79 | CONFIG_SERIAL_8250=y | ||
| 80 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 81 | # CONFIG_LEGACY_PTYS is not set | ||
| 82 | CONFIG_I2C=y | ||
| 83 | CONFIG_I2C_OMAP=y | ||
| 84 | CONFIG_SPI=y | ||
| 85 | CONFIG_SPI_OMAP_UWIRE=y | ||
| 86 | # CONFIG_HWMON is not set | ||
| 87 | CONFIG_WATCHDOG=y | ||
| 88 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 89 | CONFIG_OMAP_WATCHDOG=y | ||
| 90 | CONFIG_FB=y | ||
| 91 | CONFIG_FB_OMAP=y | ||
| 92 | CONFIG_FB_OMAP_LCDC_EXTERNAL=y | ||
| 93 | CONFIG_FB_OMAP_LCDC_HWA742=y | ||
| 94 | CONFIG_FB_OMAP_MANUAL_UPDATE=y | ||
| 95 | CONFIG_FB_OMAP_LCD_MIPID=y | ||
| 96 | # CONFIG_VGA_CONSOLE is not set | ||
| 97 | CONFIG_SOUND=y | ||
| 98 | CONFIG_SND=y | ||
| 99 | # CONFIG_SND_SUPPORT_OLD_API is not set | ||
| 100 | CONFIG_SND_DUMMY=y | ||
| 101 | CONFIG_SND_USB_AUDIO=y | ||
| 102 | CONFIG_USB=y | ||
| 103 | CONFIG_USB_DEVICEFS=y | ||
| 104 | CONFIG_USB_SUSPEND=y | ||
| 105 | CONFIG_USB_OTG=y | ||
| 106 | # CONFIG_USB_OTG_WHITELIST is not set | ||
| 107 | CONFIG_USB_OHCI_HCD=y | ||
| 108 | CONFIG_USB_STORAGE=y | ||
| 109 | CONFIG_USB_SERIAL=y | ||
| 110 | CONFIG_USB_SERIAL_CONSOLE=y | ||
| 111 | CONFIG_USB_SERIAL_PL2303=y | ||
| 112 | CONFIG_USB_GADGET=y | ||
| 113 | CONFIG_USB_ETH=m | ||
| 114 | CONFIG_USB_FILE_STORAGE=m | ||
| 115 | CONFIG_USB_FILE_STORAGE_TEST=y | ||
| 116 | CONFIG_MMC=y | ||
| 117 | CONFIG_MMC_OMAP=y | ||
| 118 | CONFIG_EXT2_FS=y | ||
| 119 | CONFIG_EXT3_FS=y | ||
| 120 | CONFIG_MSDOS_FS=y | ||
| 121 | CONFIG_VFAT_FS=y | ||
| 122 | CONFIG_TMPFS=y | ||
| 123 | CONFIG_JFFS2_FS=y | ||
| 124 | CONFIG_JFFS2_SUMMARY=y | ||
| 125 | CONFIG_JFFS2_COMPRESSION_OPTIONS=y | ||
| 126 | CONFIG_NFS_FS=y | ||
| 127 | CONFIG_NFS_V3=y | ||
| 128 | CONFIG_PARTITION_ADVANCED=y | ||
| 129 | CONFIG_NLS_CODEPAGE_437=y | ||
| 130 | CONFIG_NLS_CODEPAGE_852=y | ||
| 131 | CONFIG_NLS_ISO8859_1=y | ||
| 132 | CONFIG_NLS_ISO8859_15=y | ||
| 133 | CONFIG_NLS_UTF8=y | ||
| 134 | CONFIG_MAGIC_SYSRQ=y | ||
| 135 | CONFIG_DEBUG_KERNEL=y | ||
| 136 | CONFIG_DEBUG_MUTEXES=y | ||
| 137 | CONFIG_DEBUG_ERRORS=y | ||
| 138 | CONFIG_SECURITY=y | ||
diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig new file mode 100644 index 000000000000..a350cc6bfe6a --- /dev/null +++ b/arch/arm/configs/omap1_defconfig | |||
| @@ -0,0 +1,286 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | # CONFIG_SWAP is not set | ||
| 3 | CONFIG_SYSVIPC=y | ||
| 4 | CONFIG_POSIX_MQUEUE=y | ||
| 5 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 6 | CONFIG_IKCONFIG=y | ||
| 7 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 8 | CONFIG_BLK_DEV_INITRD=y | ||
| 9 | CONFIG_EMBEDDED=y | ||
| 10 | # CONFIG_KALLSYMS is not set | ||
| 11 | # CONFIG_ELF_CORE is not set | ||
| 12 | # CONFIG_BASE_FULL is not set | ||
| 13 | # CONFIG_SHMEM is not set | ||
| 14 | # CONFIG_VM_EVENT_COUNTERS is not set | ||
| 15 | CONFIG_SLOB=y | ||
| 16 | CONFIG_PROFILING=y | ||
| 17 | CONFIG_OPROFILE=y | ||
| 18 | CONFIG_MODULES=y | ||
| 19 | CONFIG_MODULE_UNLOAD=y | ||
| 20 | CONFIG_MODULE_FORCE_UNLOAD=y | ||
| 21 | # CONFIG_LBDAF is not set | ||
| 22 | # CONFIG_BLK_DEV_BSG is not set | ||
| 23 | # CONFIG_IOSCHED_DEADLINE is not set | ||
| 24 | # CONFIG_IOSCHED_CFQ is not set | ||
| 25 | CONFIG_ARCH_OMAP=y | ||
| 26 | CONFIG_ARCH_OMAP1=y | ||
| 27 | CONFIG_OMAP_RESET_CLOCKS=y | ||
| 28 | # CONFIG_OMAP_MUX is not set | ||
| 29 | CONFIG_OMAP_MBOX_FWK=y | ||
| 30 | CONFIG_OMAP_32K_TIMER=y | ||
| 31 | CONFIG_OMAP_DM_TIMER=y | ||
| 32 | CONFIG_ARCH_OMAP730=y | ||
| 33 | CONFIG_ARCH_OMAP850=y | ||
| 34 | CONFIG_ARCH_OMAP16XX=y | ||
| 35 | CONFIG_MACH_OMAP_INNOVATOR=y | ||
| 36 | CONFIG_MACH_OMAP_H2=y | ||
| 37 | CONFIG_MACH_OMAP_H3=y | ||
| 38 | CONFIG_MACH_OMAP_HTCWIZARD=y | ||
| 39 | CONFIG_MACH_HERALD=y | ||
| 40 | CONFIG_MACH_OMAP_OSK=y | ||
| 41 | CONFIG_MACH_OMAP_PERSEUS2=y | ||
| 42 | CONFIG_MACH_OMAP_FSAMPLE=y | ||
| 43 | CONFIG_MACH_VOICEBLUE=y | ||
| 44 | CONFIG_MACH_OMAP_PALMTE=y | ||
| 45 | CONFIG_MACH_OMAP_PALMZ71=y | ||
| 46 | CONFIG_MACH_OMAP_PALMTT=y | ||
| 47 | CONFIG_MACH_SX1=y | ||
| 48 | CONFIG_MACH_NOKIA770=y | ||
| 49 | CONFIG_MACH_AMS_DELTA=y | ||
| 50 | CONFIG_MACH_OMAP_GENERIC=y | ||
| 51 | CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER=y | ||
| 52 | CONFIG_OMAP_ARM_216MHZ=y | ||
| 53 | CONFIG_OMAP_ARM_195MHZ=y | ||
| 54 | CONFIG_OMAP_ARM_192MHZ=y | ||
| 55 | CONFIG_OMAP_ARM_182MHZ=y | ||
| 56 | CONFIG_OMAP_ARM_168MHZ=y | ||
| 57 | # CONFIG_OMAP_ARM_60MHZ is not set | ||
| 58 | # CONFIG_ARM_THUMB is not set | ||
| 59 | CONFIG_PCCARD=y | ||
| 60 | CONFIG_OMAP_CF=y | ||
| 61 | CONFIG_NO_HZ=y | ||
| 62 | CONFIG_HIGH_RES_TIMERS=y | ||
| 63 | CONFIG_PREEMPT=y | ||
| 64 | CONFIG_AEABI=y | ||
| 65 | CONFIG_LEDS=y | ||
| 66 | CONFIG_LEDS_CPU=y | ||
| 67 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 68 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 69 | CONFIG_CMDLINE="root=1f03 rootfstype=jffs2" | ||
| 70 | CONFIG_FPE_NWFPE=y | ||
| 71 | CONFIG_BINFMT_MISC=y | ||
| 72 | CONFIG_PM=y | ||
| 73 | # CONFIG_SUSPEND is not set | ||
| 74 | CONFIG_PM_RUNTIME=y | ||
| 75 | CONFIG_NET=y | ||
| 76 | CONFIG_PACKET=y | ||
| 77 | CONFIG_UNIX=y | ||
| 78 | CONFIG_NET_KEY=y | ||
| 79 | CONFIG_INET=y | ||
| 80 | CONFIG_IP_MULTICAST=y | ||
| 81 | CONFIG_IP_PNP=y | ||
| 82 | CONFIG_IP_PNP_DHCP=y | ||
| 83 | CONFIG_IP_PNP_BOOTP=y | ||
| 84 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | ||
| 85 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | ||
| 86 | # CONFIG_INET_XFRM_MODE_BEET is not set | ||
| 87 | # CONFIG_INET_LRO is not set | ||
| 88 | # CONFIG_INET_DIAG is not set | ||
| 89 | CONFIG_IPV6=y | ||
| 90 | CONFIG_NETFILTER=y | ||
| 91 | CONFIG_BT=y | ||
| 92 | CONFIG_BT_L2CAP=y | ||
| 93 | CONFIG_BT_SCO=y | ||
| 94 | CONFIG_BT_RFCOMM=y | ||
| 95 | CONFIG_BT_RFCOMM_TTY=y | ||
| 96 | CONFIG_BT_BNEP=y | ||
| 97 | CONFIG_BT_HIDP=y | ||
| 98 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 99 | # CONFIG_STANDALONE is not set | ||
| 100 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set | ||
| 101 | CONFIG_CONNECTOR=y | ||
| 102 | # CONFIG_PROC_EVENTS is not set | ||
| 103 | CONFIG_MTD=y | ||
| 104 | CONFIG_MTD_DEBUG=y | ||
| 105 | CONFIG_MTD_DEBUG_VERBOSE=3 | ||
| 106 | CONFIG_MTD_PARTITIONS=y | ||
| 107 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 108 | CONFIG_MTD_CHAR=y | ||
| 109 | CONFIG_MTD_BLOCK=y | ||
| 110 | CONFIG_MTD_CFI=y | ||
| 111 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 112 | CONFIG_MTD_NAND=y | ||
| 113 | CONFIG_BLK_DEV_LOOP=y | ||
| 114 | CONFIG_BLK_DEV_RAM=y | ||
| 115 | CONFIG_BLK_DEV_RAM_COUNT=2 | ||
| 116 | CONFIG_BLK_DEV_RAM_SIZE=8192 | ||
| 117 | CONFIG_IDE=m | ||
| 118 | CONFIG_BLK_DEV_IDECS=m | ||
| 119 | CONFIG_SCSI=y | ||
| 120 | # CONFIG_SCSI_PROC_FS is not set | ||
| 121 | CONFIG_BLK_DEV_SD=y | ||
| 122 | CONFIG_CHR_DEV_ST=y | ||
| 123 | CONFIG_BLK_DEV_SR=y | ||
| 124 | CONFIG_CHR_DEV_SG=y | ||
| 125 | CONFIG_SCSI_MULTI_LUN=y | ||
| 126 | CONFIG_NETDEVICES=y | ||
| 127 | CONFIG_TUN=y | ||
| 128 | CONFIG_PHYLIB=y | ||
| 129 | CONFIG_NET_ETHERNET=y | ||
| 130 | CONFIG_SMC91X=y | ||
| 131 | CONFIG_USB_CATC=y | ||
| 132 | CONFIG_USB_KAWETH=y | ||
| 133 | CONFIG_USB_PEGASUS=y | ||
| 134 | CONFIG_USB_RTL8150=y | ||
| 135 | CONFIG_USB_USBNET=y | ||
| 136 | # CONFIG_USB_NET_AX8817X is not set | ||
| 137 | # CONFIG_USB_NET_CDC_SUBSET is not set | ||
| 138 | CONFIG_PPP=y | ||
| 139 | CONFIG_PPP_MULTILINK=y | ||
| 140 | CONFIG_PPP_FILTER=y | ||
| 141 | CONFIG_PPP_ASYNC=y | ||
| 142 | CONFIG_PPP_DEFLATE=y | ||
| 143 | CONFIG_PPP_BSDCOMP=y | ||
| 144 | CONFIG_SLIP=y | ||
| 145 | CONFIG_SLIP_COMPRESSED=y | ||
| 146 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 147 | CONFIG_INPUT_EVDEV=y | ||
| 148 | CONFIG_INPUT_EVBUG=y | ||
| 149 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 150 | # CONFIG_INPUT_MOUSE is not set | ||
| 151 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 152 | CONFIG_TOUCHSCREEN_ADS7846=y | ||
| 153 | CONFIG_INPUT_MISC=y | ||
| 154 | CONFIG_INPUT_UINPUT=y | ||
| 155 | # CONFIG_SERIO is not set | ||
| 156 | CONFIG_SERIAL_8250=y | ||
| 157 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 158 | CONFIG_SERIAL_8250_NR_UARTS=3 | ||
| 159 | CONFIG_SERIAL_8250_RUNTIME_UARTS=3 | ||
| 160 | # CONFIG_LEGACY_PTYS is not set | ||
| 161 | CONFIG_HW_RANDOM=y | ||
| 162 | CONFIG_I2C=y | ||
| 163 | CONFIG_I2C_CHARDEV=y | ||
| 164 | CONFIG_SPI=y | ||
| 165 | CONFIG_SPI_OMAP_UWIRE=y | ||
| 166 | # CONFIG_HWMON is not set | ||
| 167 | CONFIG_WATCHDOG=y | ||
| 168 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 169 | CONFIG_OMAP_WATCHDOG=y | ||
| 170 | CONFIG_VIDEO_OUTPUT_CONTROL=y | ||
| 171 | CONFIG_FB=y | ||
| 172 | CONFIG_FIRMWARE_EDID=y | ||
| 173 | CONFIG_FB_MODE_HELPERS=y | ||
| 174 | CONFIG_FB_VIRTUAL=y | ||
| 175 | CONFIG_FB_OMAP=y | ||
| 176 | CONFIG_FB_OMAP_LCDC_EXTERNAL=y | ||
| 177 | CONFIG_FB_OMAP_LCDC_HWA742=y | ||
| 178 | CONFIG_FB_OMAP_MANUAL_UPDATE=y | ||
| 179 | CONFIG_FB_OMAP_LCD_MIPID=y | ||
| 180 | CONFIG_FB_OMAP_BOOTLOADER_INIT=y | ||
| 181 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | ||
| 182 | CONFIG_LCD_CLASS_DEVICE=y | ||
| 183 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 184 | CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y | ||
| 185 | CONFIG_FONTS=y | ||
| 186 | CONFIG_FONT_8x8=y | ||
| 187 | CONFIG_FONT_8x16=y | ||
| 188 | CONFIG_FONT_6x11=y | ||
| 189 | CONFIG_FONT_MINI_4x6=y | ||
| 190 | CONFIG_LOGO=y | ||
| 191 | # CONFIG_LOGO_LINUX_MONO is not set | ||
| 192 | # CONFIG_LOGO_LINUX_VGA16 is not set | ||
| 193 | CONFIG_SOUND=y | ||
| 194 | CONFIG_SND=y | ||
| 195 | CONFIG_SND_MIXER_OSS=y | ||
| 196 | CONFIG_SND_PCM_OSS=y | ||
| 197 | # CONFIG_SND_SUPPORT_OLD_API is not set | ||
| 198 | # CONFIG_SND_VERBOSE_PROCFS is not set | ||
| 199 | CONFIG_SND_DUMMY=y | ||
| 200 | CONFIG_SND_USB_AUDIO=y | ||
| 201 | CONFIG_SND_SOC=y | ||
| 202 | CONFIG_SND_OMAP_SOC=y | ||
| 203 | # CONFIG_USB_HID is not set | ||
| 204 | CONFIG_USB=y | ||
| 205 | CONFIG_USB_DEBUG=y | ||
| 206 | CONFIG_USB_DEVICEFS=y | ||
| 207 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 208 | CONFIG_USB_SUSPEND=y | ||
| 209 | CONFIG_USB_MON=y | ||
| 210 | CONFIG_USB_OHCI_HCD=y | ||
| 211 | CONFIG_USB_STORAGE=y | ||
| 212 | CONFIG_USB_STORAGE_DATAFAB=y | ||
| 213 | CONFIG_USB_STORAGE_FREECOM=y | ||
| 214 | CONFIG_USB_STORAGE_SDDR09=y | ||
| 215 | CONFIG_USB_STORAGE_SDDR55=y | ||
| 216 | CONFIG_USB_STORAGE_JUMPSHOT=y | ||
| 217 | CONFIG_USB_SERIAL=y | ||
| 218 | CONFIG_USB_SERIAL_CONSOLE=y | ||
| 219 | CONFIG_USB_SERIAL_PL2303=y | ||
| 220 | CONFIG_USB_TEST=y | ||
| 221 | CONFIG_USB_GADGET=y | ||
| 222 | CONFIG_USB_ETH=m | ||
| 223 | # CONFIG_USB_ETH_RNDIS is not set | ||
| 224 | CONFIG_USB_FILE_STORAGE=m | ||
| 225 | CONFIG_USB_FILE_STORAGE_TEST=y | ||
| 226 | CONFIG_MMC=y | ||
| 227 | CONFIG_MMC_SDHCI=y | ||
| 228 | CONFIG_MMC_SDHCI_PLTFM=y | ||
| 229 | CONFIG_MMC_OMAP=y | ||
| 230 | CONFIG_NEW_LEDS=y | ||
| 231 | CONFIG_LEDS_CLASS=y | ||
| 232 | CONFIG_LEDS_TRIGGERS=y | ||
| 233 | CONFIG_LEDS_TRIGGER_TIMER=y | ||
| 234 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
| 235 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=y | ||
| 236 | CONFIG_RTC_CLASS=y | ||
| 237 | CONFIG_RTC_DRV_OMAP=y | ||
| 238 | CONFIG_EXT2_FS=y | ||
| 239 | CONFIG_EXT3_FS=y | ||
| 240 | # CONFIG_DNOTIFY is not set | ||
| 241 | CONFIG_AUTOFS4_FS=y | ||
| 242 | CONFIG_ISO9660_FS=y | ||
| 243 | CONFIG_JOLIET=y | ||
| 244 | CONFIG_MSDOS_FS=y | ||
| 245 | CONFIG_VFAT_FS=y | ||
| 246 | CONFIG_FAT_DEFAULT_CODEPAGE=866 | ||
| 247 | CONFIG_FAT_DEFAULT_IOCHARSET="koi8-r" | ||
| 248 | CONFIG_JFFS2_FS=y | ||
| 249 | CONFIG_JFFS2_SUMMARY=y | ||
| 250 | CONFIG_JFFS2_COMPRESSION_OPTIONS=y | ||
| 251 | CONFIG_CRAMFS=y | ||
| 252 | CONFIG_ROMFS_FS=y | ||
| 253 | CONFIG_NFS_FS=y | ||
| 254 | CONFIG_NFS_V3=y | ||
| 255 | CONFIG_NFS_V4=y | ||
| 256 | CONFIG_ROOT_NFS=y | ||
| 257 | CONFIG_PARTITION_ADVANCED=y | ||
| 258 | CONFIG_NLS_CODEPAGE_437=y | ||
| 259 | CONFIG_NLS_CODEPAGE_850=y | ||
| 260 | CONFIG_NLS_CODEPAGE_852=y | ||
| 261 | CONFIG_NLS_CODEPAGE_866=y | ||
| 262 | CONFIG_NLS_CODEPAGE_1251=y | ||
| 263 | CONFIG_NLS_ISO8859_1=y | ||
| 264 | CONFIG_NLS_ISO8859_2=y | ||
| 265 | CONFIG_NLS_ISO8859_5=y | ||
| 266 | CONFIG_NLS_ISO8859_15=y | ||
| 267 | CONFIG_NLS_KOI8_R=y | ||
| 268 | CONFIG_NLS_UTF8=y | ||
| 269 | # CONFIG_ENABLE_MUST_CHECK is not set | ||
| 270 | CONFIG_MAGIC_SYSRQ=y | ||
| 271 | CONFIG_DEBUG_KERNEL=y | ||
| 272 | CONFIG_DEBUG_SPINLOCK=y | ||
| 273 | CONFIG_DEBUG_MUTEXES=y | ||
| 274 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 275 | CONFIG_DEBUG_INFO=y | ||
| 276 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 277 | CONFIG_DEBUG_USER=y | ||
| 278 | CONFIG_DEBUG_ERRORS=y | ||
| 279 | CONFIG_SECURITY=y | ||
| 280 | CONFIG_CRYPTO_ECB=y | ||
| 281 | CONFIG_CRYPTO_PCBC=y | ||
| 282 | CONFIG_CRYPTO_DEFLATE=y | ||
| 283 | CONFIG_CRYPTO_ZLIB=y | ||
| 284 | CONFIG_CRYPTO_LZO=y | ||
| 285 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 286 | CONFIG_LIBCRC32C=y | ||
diff --git a/arch/arm/configs/omap_generic_1510_defconfig b/arch/arm/configs/omap_generic_1510_defconfig deleted file mode 100644 index 0e42ba4ede9d..000000000000 --- a/arch/arm/configs/omap_generic_1510_defconfig +++ /dev/null | |||
| @@ -1,84 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | ||
| 3 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 4 | CONFIG_BLK_DEV_INITRD=y | ||
| 5 | CONFIG_SLAB=y | ||
| 6 | CONFIG_MODULES=y | ||
| 7 | CONFIG_MODULE_UNLOAD=y | ||
| 8 | CONFIG_MODULE_FORCE_UNLOAD=y | ||
| 9 | # CONFIG_BLK_DEV_BSG is not set | ||
| 10 | CONFIG_ARCH_OMAP=y | ||
| 11 | CONFIG_ARCH_OMAP1=y | ||
| 12 | CONFIG_MACH_OMAP_GENERIC=y | ||
| 13 | CONFIG_OMAP_ARM_168MHZ=y | ||
| 14 | # CONFIG_OMAP_ARM_60MHZ is not set | ||
| 15 | # CONFIG_ARM_THUMB is not set | ||
| 16 | CONFIG_PREEMPT=y | ||
| 17 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 18 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 19 | CONFIG_CMDLINE="mem=64M console=ttyS2,115200 root=0803 ro init=/bin/sh" | ||
| 20 | CONFIG_FPE_NWFPE=y | ||
| 21 | CONFIG_PM=y | ||
| 22 | CONFIG_NET=y | ||
| 23 | CONFIG_PACKET=y | ||
| 24 | CONFIG_UNIX=y | ||
| 25 | CONFIG_INET=y | ||
| 26 | CONFIG_IP_MULTICAST=y | ||
| 27 | CONFIG_IP_PNP=y | ||
| 28 | CONFIG_IP_PNP_DHCP=y | ||
| 29 | CONFIG_IP_PNP_BOOTP=y | ||
| 30 | # CONFIG_IPV6 is not set | ||
| 31 | CONFIG_BLK_DEV_LOOP=y | ||
| 32 | CONFIG_BLK_DEV_RAM=y | ||
| 33 | CONFIG_BLK_DEV_RAM_SIZE=8192 | ||
| 34 | CONFIG_SCSI=y | ||
| 35 | CONFIG_BLK_DEV_SD=y | ||
| 36 | CONFIG_BLK_DEV_SR=y | ||
| 37 | CONFIG_CHR_DEV_SG=y | ||
| 38 | CONFIG_SCSI_MULTI_LUN=y | ||
| 39 | CONFIG_NETDEVICES=y | ||
| 40 | CONFIG_NET_ETHERNET=y | ||
| 41 | CONFIG_USB_RTL8150=y | ||
| 42 | CONFIG_USB_USBNET=y | ||
| 43 | CONFIG_USB_AN2720=y | ||
| 44 | CONFIG_USB_EPSON2888=y | ||
| 45 | CONFIG_PPP=y | ||
| 46 | CONFIG_PPP_MULTILINK=y | ||
| 47 | CONFIG_KEYBOARD_OMAP=y | ||
| 48 | # CONFIG_INPUT_MOUSE is not set | ||
| 49 | CONFIG_SERIAL_8250=y | ||
| 50 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 51 | # CONFIG_LEGACY_PTYS is not set | ||
| 52 | CONFIG_I2C=y | ||
| 53 | CONFIG_I2C_CHARDEV=y | ||
| 54 | CONFIG_VIDEO_OUTPUT_CONTROL=m | ||
| 55 | # CONFIG_VGA_CONSOLE is not set | ||
| 56 | CONFIG_USB=y | ||
| 57 | CONFIG_USB_DEBUG=y | ||
| 58 | CONFIG_USB_DEVICEFS=y | ||
| 59 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 60 | CONFIG_USB_MON=y | ||
| 61 | CONFIG_USB_OHCI_HCD=y | ||
| 62 | CONFIG_USB_STORAGE=y | ||
| 63 | CONFIG_USB_STORAGE_DATAFAB=y | ||
| 64 | CONFIG_USB_STORAGE_FREECOM=y | ||
| 65 | CONFIG_USB_STORAGE_SDDR09=y | ||
| 66 | CONFIG_USB_STORAGE_SDDR55=y | ||
| 67 | CONFIG_USB_STORAGE_JUMPSHOT=y | ||
| 68 | CONFIG_MMC=y | ||
| 69 | CONFIG_MMC_OMAP=y | ||
| 70 | CONFIG_RTC_CLASS=y | ||
| 71 | CONFIG_RTC_DRV_OMAP=y | ||
| 72 | CONFIG_EXT2_FS=y | ||
| 73 | CONFIG_EXT3_FS=y | ||
| 74 | CONFIG_INOTIFY=y | ||
| 75 | CONFIG_AUTOFS_FS=y | ||
| 76 | CONFIG_AUTOFS4_FS=y | ||
| 77 | CONFIG_ISO9660_FS=y | ||
| 78 | CONFIG_JOLIET=y | ||
| 79 | CONFIG_MSDOS_FS=m | ||
| 80 | CONFIG_VFAT_FS=m | ||
| 81 | CONFIG_NFS_FS=y | ||
| 82 | CONFIG_PARTITION_ADVANCED=y | ||
| 83 | CONFIG_MAGIC_SYSRQ=y | ||
| 84 | CONFIG_DEBUG_KERNEL=y | ||
diff --git a/arch/arm/configs/omap_generic_1610_defconfig b/arch/arm/configs/omap_generic_1610_defconfig deleted file mode 100644 index 5e536cf0f9f7..000000000000 --- a/arch/arm/configs/omap_generic_1610_defconfig +++ /dev/null | |||
| @@ -1,87 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | ||
| 3 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 4 | CONFIG_BLK_DEV_INITRD=y | ||
| 5 | CONFIG_SLAB=y | ||
| 6 | CONFIG_MODULES=y | ||
| 7 | CONFIG_MODULE_UNLOAD=y | ||
| 8 | CONFIG_MODULE_FORCE_UNLOAD=y | ||
| 9 | # CONFIG_BLK_DEV_BSG is not set | ||
| 10 | CONFIG_ARCH_OMAP=y | ||
| 11 | CONFIG_ARCH_OMAP1=y | ||
| 12 | # CONFIG_ARCH_OMAP15XX is not set | ||
| 13 | CONFIG_ARCH_OMAP16XX=y | ||
| 14 | CONFIG_MACH_OMAP_GENERIC=y | ||
| 15 | CONFIG_OMAP_ARM_192MHZ=y | ||
| 16 | # CONFIG_OMAP_ARM_60MHZ is not set | ||
| 17 | # CONFIG_ARM_THUMB is not set | ||
| 18 | CONFIG_PREEMPT=y | ||
| 19 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 20 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 21 | CONFIG_CMDLINE="mem=64M console=ttyS2,115200 root=0803 ro init=/bin/sh" | ||
| 22 | CONFIG_FPE_NWFPE=y | ||
| 23 | CONFIG_PM=y | ||
| 24 | CONFIG_NET=y | ||
| 25 | CONFIG_PACKET=y | ||
| 26 | CONFIG_UNIX=y | ||
| 27 | CONFIG_INET=y | ||
| 28 | CONFIG_IP_MULTICAST=y | ||
| 29 | CONFIG_IP_PNP=y | ||
| 30 | CONFIG_IP_PNP_DHCP=y | ||
| 31 | CONFIG_IP_PNP_BOOTP=y | ||
| 32 | # CONFIG_IPV6 is not set | ||
| 33 | CONFIG_BLK_DEV_LOOP=y | ||
| 34 | CONFIG_BLK_DEV_RAM=y | ||
| 35 | CONFIG_BLK_DEV_RAM_SIZE=8192 | ||
| 36 | CONFIG_SCSI=y | ||
| 37 | CONFIG_BLK_DEV_SD=y | ||
| 38 | CONFIG_BLK_DEV_SR=y | ||
| 39 | CONFIG_CHR_DEV_SG=y | ||
| 40 | CONFIG_SCSI_MULTI_LUN=y | ||
| 41 | CONFIG_NETDEVICES=y | ||
| 42 | CONFIG_NET_ETHERNET=y | ||
| 43 | CONFIG_USB_RTL8150=y | ||
| 44 | CONFIG_USB_USBNET=y | ||
| 45 | CONFIG_USB_ALI_M5632=y | ||
| 46 | CONFIG_USB_AN2720=y | ||
| 47 | CONFIG_USB_EPSON2888=y | ||
| 48 | CONFIG_PPP=y | ||
| 49 | CONFIG_PPP_MULTILINK=y | ||
| 50 | CONFIG_KEYBOARD_OMAP=y | ||
| 51 | # CONFIG_INPUT_MOUSE is not set | ||
| 52 | CONFIG_SERIAL_8250=y | ||
| 53 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 54 | # CONFIG_LEGACY_PTYS is not set | ||
| 55 | CONFIG_I2C=y | ||
| 56 | CONFIG_I2C_CHARDEV=y | ||
| 57 | CONFIG_VIDEO_OUTPUT_CONTROL=m | ||
| 58 | # CONFIG_VGA_CONSOLE is not set | ||
| 59 | CONFIG_USB=y | ||
| 60 | CONFIG_USB_DEBUG=y | ||
| 61 | CONFIG_USB_DEVICEFS=y | ||
| 62 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 63 | CONFIG_USB_MON=y | ||
| 64 | CONFIG_USB_OHCI_HCD=y | ||
| 65 | CONFIG_USB_STORAGE=y | ||
| 66 | CONFIG_USB_STORAGE_DATAFAB=y | ||
| 67 | CONFIG_USB_STORAGE_FREECOM=y | ||
| 68 | CONFIG_USB_STORAGE_SDDR09=y | ||
| 69 | CONFIG_USB_STORAGE_SDDR55=y | ||
| 70 | CONFIG_USB_STORAGE_JUMPSHOT=y | ||
| 71 | CONFIG_MMC=y | ||
| 72 | CONFIG_MMC_OMAP=y | ||
| 73 | CONFIG_RTC_CLASS=y | ||
| 74 | CONFIG_RTC_DRV_OMAP=y | ||
| 75 | CONFIG_EXT2_FS=y | ||
| 76 | CONFIG_EXT3_FS=y | ||
| 77 | CONFIG_INOTIFY=y | ||
| 78 | CONFIG_AUTOFS_FS=y | ||
| 79 | CONFIG_AUTOFS4_FS=y | ||
| 80 | CONFIG_ISO9660_FS=y | ||
| 81 | CONFIG_JOLIET=y | ||
| 82 | CONFIG_MSDOS_FS=m | ||
| 83 | CONFIG_VFAT_FS=m | ||
| 84 | CONFIG_NFS_FS=y | ||
| 85 | CONFIG_PARTITION_ADVANCED=y | ||
| 86 | CONFIG_MAGIC_SYSRQ=y | ||
| 87 | CONFIG_DEBUG_KERNEL=y | ||
diff --git a/arch/arm/configs/omap_generic_1710_defconfig b/arch/arm/configs/omap_generic_1710_defconfig deleted file mode 100644 index c0867b1d9815..000000000000 --- a/arch/arm/configs/omap_generic_1710_defconfig +++ /dev/null | |||
| @@ -1,75 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | ||
| 3 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 4 | CONFIG_BLK_DEV_INITRD=y | ||
| 5 | # CONFIG_BLK_DEV_BSG is not set | ||
| 6 | CONFIG_ARCH_OMAP=y | ||
| 7 | CONFIG_ARCH_OMAP1=y | ||
| 8 | # CONFIG_OMAP_MUX is not set | ||
| 9 | # CONFIG_ARCH_OMAP15XX is not set | ||
| 10 | CONFIG_ARCH_OMAP16XX=y | ||
| 11 | CONFIG_MACH_OMAP_GENERIC=y | ||
| 12 | CONFIG_OMAP_ARM_192MHZ=y | ||
| 13 | # CONFIG_OMAP_ARM_60MHZ is not set | ||
| 14 | # CONFIG_ARM_THUMB is not set | ||
| 15 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 16 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 17 | CONFIG_CMDLINE="mem=64M console=tty0 console=ttyS2,115200 root=0801" | ||
| 18 | CONFIG_FPE_NWFPE=y | ||
| 19 | CONFIG_ARTHUR=y | ||
| 20 | CONFIG_PM=y | ||
| 21 | CONFIG_NET=y | ||
| 22 | CONFIG_PACKET=y | ||
| 23 | CONFIG_UNIX=y | ||
| 24 | CONFIG_INET=y | ||
| 25 | CONFIG_IP_MULTICAST=y | ||
| 26 | CONFIG_IP_PNP=y | ||
| 27 | CONFIG_IP_PNP_DHCP=y | ||
| 28 | CONFIG_IP_PNP_BOOTP=y | ||
| 29 | # CONFIG_IPV6 is not set | ||
| 30 | CONFIG_BLK_DEV_LOOP=y | ||
| 31 | CONFIG_BLK_DEV_RAM=y | ||
| 32 | CONFIG_BLK_DEV_RAM_SIZE=8192 | ||
| 33 | CONFIG_SCSI=y | ||
| 34 | CONFIG_BLK_DEV_SD=y | ||
| 35 | CONFIG_NETDEVICES=y | ||
| 36 | CONFIG_NET_ETHERNET=y | ||
| 37 | CONFIG_USB_USBNET=y | ||
| 38 | CONFIG_USB_ALI_M5632=y | ||
| 39 | # CONFIG_USB_BELKIN is not set | ||
| 40 | # CONFIG_USB_ARMLINUX is not set | ||
| 41 | CONFIG_PPP=y | ||
| 42 | CONFIG_INPUT_EVDEV=y | ||
| 43 | CONFIG_KEYBOARD_OMAP=y | ||
| 44 | # CONFIG_INPUT_MOUSE is not set | ||
| 45 | CONFIG_SERIAL_8250=y | ||
| 46 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 47 | CONFIG_VIDEO_OUTPUT_CONTROL=y | ||
| 48 | # CONFIG_VGA_CONSOLE is not set | ||
| 49 | CONFIG_USB=y | ||
| 50 | CONFIG_USB_DEBUG=y | ||
| 51 | CONFIG_USB_DEVICEFS=y | ||
| 52 | CONFIG_USB_MON=y | ||
| 53 | CONFIG_USB_OHCI_HCD=y | ||
| 54 | CONFIG_USB_STORAGE=y | ||
| 55 | CONFIG_MMC=y | ||
| 56 | CONFIG_MMC_OMAP=y | ||
| 57 | CONFIG_EXT2_FS=y | ||
| 58 | CONFIG_EXT3_FS=y | ||
| 59 | CONFIG_INOTIFY=y | ||
| 60 | CONFIG_TMPFS=y | ||
| 61 | CONFIG_NFS_FS=y | ||
| 62 | CONFIG_NFS_V3=y | ||
| 63 | CONFIG_NFS_V4=y | ||
| 64 | CONFIG_PARTITION_ADVANCED=y | ||
| 65 | CONFIG_NLS_CODEPAGE_437=y | ||
| 66 | CONFIG_NLS_CODEPAGE_852=y | ||
| 67 | CONFIG_NLS_ISO8859_1=y | ||
| 68 | CONFIG_NLS_ISO8859_15=y | ||
| 69 | CONFIG_MAGIC_SYSRQ=y | ||
| 70 | CONFIG_DEBUG_KERNEL=y | ||
| 71 | CONFIG_DEBUG_SPINLOCK=y | ||
| 72 | CONFIG_DEBUG_ERRORS=y | ||
| 73 | CONFIG_SECURITY=y | ||
| 74 | CONFIG_CRYPTO_ECB=y | ||
| 75 | CONFIG_CRYPTO_PCBC=y | ||
diff --git a/arch/arm/configs/omap_h2_1610_defconfig b/arch/arm/configs/omap_h2_1610_defconfig deleted file mode 100644 index e2de2aa17e62..000000000000 --- a/arch/arm/configs/omap_h2_1610_defconfig +++ /dev/null | |||
| @@ -1,109 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | ||
| 3 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 4 | CONFIG_BLK_DEV_INITRD=y | ||
| 5 | CONFIG_SLAB=y | ||
| 6 | CONFIG_MODULES=y | ||
| 7 | CONFIG_MODULE_UNLOAD=y | ||
| 8 | # CONFIG_BLK_DEV_BSG is not set | ||
| 9 | CONFIG_ARCH_OMAP=y | ||
| 10 | CONFIG_ARCH_OMAP1=y | ||
| 11 | CONFIG_OMAP_MUX_DEBUG=y | ||
| 12 | CONFIG_OMAP_32K_TIMER=y | ||
| 13 | CONFIG_OMAP_DM_TIMER=y | ||
| 14 | # CONFIG_ARCH_OMAP15XX is not set | ||
| 15 | CONFIG_ARCH_OMAP16XX=y | ||
| 16 | CONFIG_MACH_OMAP_H2=y | ||
| 17 | CONFIG_NO_HZ=y | ||
| 18 | CONFIG_HIGH_RES_TIMERS=y | ||
| 19 | CONFIG_LEDS=y | ||
| 20 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 21 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 22 | CONFIG_CMDLINE="mem=32M console=ttyS0,115200n8 root=/dev/ram0 rw initrd=0x10600000,8M ramdisk_size=8192" | ||
| 23 | CONFIG_FPE_NWFPE=y | ||
| 24 | CONFIG_PM=y | ||
| 25 | CONFIG_PM_RUNTIME=y | ||
| 26 | CONFIG_NET=y | ||
| 27 | CONFIG_PACKET=y | ||
| 28 | CONFIG_UNIX=y | ||
| 29 | CONFIG_INET=y | ||
| 30 | CONFIG_IP_PNP=y | ||
| 31 | CONFIG_IP_PNP_DHCP=y | ||
| 32 | CONFIG_IP_PNP_BOOTP=y | ||
| 33 | # CONFIG_INET_LRO is not set | ||
| 34 | # CONFIG_IPV6 is not set | ||
| 35 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 36 | CONFIG_DEBUG_DRIVER=y | ||
| 37 | CONFIG_MTD=y | ||
| 38 | CONFIG_MTD_DEBUG=y | ||
| 39 | CONFIG_MTD_DEBUG_VERBOSE=3 | ||
| 40 | CONFIG_MTD_PARTITIONS=y | ||
| 41 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 42 | CONFIG_MTD_CHAR=y | ||
| 43 | CONFIG_MTD_BLOCK=y | ||
| 44 | CONFIG_MTD_CFI=y | ||
| 45 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 46 | CONFIG_BLK_DEV_LOOP=y | ||
| 47 | CONFIG_BLK_DEV_RAM=y | ||
| 48 | CONFIG_BLK_DEV_RAM_SIZE=8192 | ||
| 49 | CONFIG_NETDEVICES=y | ||
| 50 | CONFIG_NET_ETHERNET=y | ||
| 51 | CONFIG_SMC91X=y | ||
| 52 | CONFIG_PPP=y | ||
| 53 | CONFIG_SLIP=y | ||
| 54 | CONFIG_SLIP_COMPRESSED=y | ||
| 55 | CONFIG_INPUT_EVDEV=y | ||
| 56 | CONFIG_INPUT_EVBUG=y | ||
| 57 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 58 | # CONFIG_INPUT_MOUSE is not set | ||
| 59 | CONFIG_INPUT_MISC=y | ||
| 60 | CONFIG_INPUT_UINPUT=y | ||
| 61 | CONFIG_SERIAL_8250=y | ||
| 62 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 63 | # CONFIG_LEGACY_PTYS is not set | ||
| 64 | CONFIG_I2C=y | ||
| 65 | CONFIG_I2C_OMAP=y | ||
| 66 | CONFIG_SPI=y | ||
| 67 | CONFIG_SPI_OMAP_UWIRE=y | ||
| 68 | CONFIG_WATCHDOG=y | ||
| 69 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 70 | CONFIG_VIDEO_OUTPUT_CONTROL=m | ||
| 71 | CONFIG_FB=y | ||
| 72 | CONFIG_FIRMWARE_EDID=y | ||
| 73 | CONFIG_FB_MODE_HELPERS=y | ||
| 74 | CONFIG_FB_OMAP=y | ||
| 75 | # CONFIG_VGA_CONSOLE is not set | ||
| 76 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 77 | CONFIG_LOGO=y | ||
| 78 | # CONFIG_LOGO_LINUX_MONO is not set | ||
| 79 | # CONFIG_LOGO_LINUX_VGA16 is not set | ||
| 80 | # CONFIG_USB_HID is not set | ||
| 81 | CONFIG_USB=y | ||
| 82 | CONFIG_USB_DEVICEFS=y | ||
| 83 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 84 | CONFIG_USB_SUSPEND=y | ||
| 85 | CONFIG_USB_OTG=y | ||
| 86 | CONFIG_USB_MON=y | ||
| 87 | CONFIG_USB_OHCI_HCD=y | ||
| 88 | CONFIG_USB_TEST=y | ||
| 89 | CONFIG_USB_GADGET=y | ||
| 90 | CONFIG_USB_ETH=m | ||
| 91 | CONFIG_MMC=y | ||
| 92 | CONFIG_MMC_OMAP=y | ||
| 93 | CONFIG_RTC_CLASS=y | ||
| 94 | CONFIG_RTC_DRV_OMAP=y | ||
| 95 | CONFIG_EXT2_FS=y | ||
| 96 | CONFIG_INOTIFY=y | ||
| 97 | CONFIG_MSDOS_FS=y | ||
| 98 | CONFIG_VFAT_FS=y | ||
| 99 | CONFIG_JFFS2_FS=y | ||
| 100 | CONFIG_CRAMFS=y | ||
| 101 | CONFIG_ROMFS_FS=y | ||
| 102 | CONFIG_NFS_FS=y | ||
| 103 | CONFIG_ROOT_NFS=y | ||
| 104 | CONFIG_NLS_CODEPAGE_437=y | ||
| 105 | CONFIG_NLS_ISO8859_1=y | ||
| 106 | CONFIG_DEBUG_KERNEL=y | ||
| 107 | CONFIG_DEBUG_INFO=y | ||
| 108 | CONFIG_DEBUG_USER=y | ||
| 109 | CONFIG_DEBUG_ERRORS=y | ||
diff --git a/arch/arm/configs/omap_innovator_1510_defconfig b/arch/arm/configs/omap_innovator_1510_defconfig deleted file mode 100644 index 265af2669ede..000000000000 --- a/arch/arm/configs/omap_innovator_1510_defconfig +++ /dev/null | |||
| @@ -1,102 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | ||
| 3 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 4 | CONFIG_BLK_DEV_INITRD=y | ||
| 5 | CONFIG_SLAB=y | ||
| 6 | CONFIG_MODULES=y | ||
| 7 | CONFIG_MODULE_UNLOAD=y | ||
| 8 | # CONFIG_BLK_DEV_BSG is not set | ||
| 9 | CONFIG_ARCH_OMAP=y | ||
| 10 | CONFIG_ARCH_OMAP1=y | ||
| 11 | CONFIG_MACH_OMAP_INNOVATOR=y | ||
| 12 | CONFIG_OMAP_ARM_168MHZ=y | ||
| 13 | # CONFIG_OMAP_ARM_60MHZ is not set | ||
| 14 | CONFIG_PREEMPT=y | ||
| 15 | CONFIG_LEDS=y | ||
| 16 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 17 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 18 | CONFIG_CMDLINE="console=ttyS0,115200n8 root=/dev/nfs ip=bootp noinitrd" | ||
| 19 | CONFIG_FPE_NWFPE=y | ||
| 20 | CONFIG_PM=y | ||
| 21 | CONFIG_NET=y | ||
| 22 | CONFIG_PACKET=y | ||
| 23 | CONFIG_UNIX=y | ||
| 24 | CONFIG_INET=y | ||
| 25 | CONFIG_IP_MULTICAST=y | ||
| 26 | CONFIG_IP_PNP=y | ||
| 27 | CONFIG_IP_PNP_DHCP=y | ||
| 28 | CONFIG_IP_PNP_BOOTP=y | ||
| 29 | # CONFIG_IPV6 is not set | ||
| 30 | CONFIG_BLK_DEV_LOOP=y | ||
| 31 | CONFIG_BLK_DEV_RAM=y | ||
| 32 | CONFIG_BLK_DEV_RAM_SIZE=8192 | ||
| 33 | CONFIG_SCSI=y | ||
| 34 | CONFIG_BLK_DEV_SD=y | ||
| 35 | CONFIG_CHR_DEV_ST=y | ||
| 36 | CONFIG_BLK_DEV_SR=y | ||
| 37 | CONFIG_CHR_DEV_SG=y | ||
| 38 | CONFIG_SCSI_MULTI_LUN=y | ||
| 39 | CONFIG_NETDEVICES=y | ||
| 40 | CONFIG_NET_ETHERNET=y | ||
| 41 | CONFIG_SMC91X=y | ||
| 42 | CONFIG_USB_RTL8150=y | ||
| 43 | CONFIG_USB_USBNET=y | ||
| 44 | # CONFIG_USB_NET_CDC_SUBSET is not set | ||
| 45 | CONFIG_PPP=y | ||
| 46 | CONFIG_PPP_MULTILINK=y | ||
| 47 | CONFIG_PPP_ASYNC=y | ||
| 48 | CONFIG_PPP_DEFLATE=y | ||
| 49 | CONFIG_PPP_BSDCOMP=y | ||
| 50 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=240 | ||
| 51 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320 | ||
| 52 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 53 | CONFIG_KEYBOARD_OMAP=y | ||
| 54 | # CONFIG_INPUT_MOUSE is not set | ||
| 55 | CONFIG_SERIAL_8250=y | ||
| 56 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 57 | # CONFIG_LEGACY_PTYS is not set | ||
| 58 | CONFIG_I2C=y | ||
| 59 | CONFIG_VIDEO_OUTPUT_CONTROL=m | ||
| 60 | CONFIG_FB=y | ||
| 61 | CONFIG_FB_OMAP=y | ||
| 62 | # CONFIG_VGA_CONSOLE is not set | ||
| 63 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 64 | CONFIG_FONTS=y | ||
| 65 | CONFIG_FONT_8x8=y | ||
| 66 | CONFIG_FONT_8x16=y | ||
| 67 | CONFIG_LOGO=y | ||
| 68 | CONFIG_USB=y | ||
| 69 | CONFIG_USB_DEBUG=y | ||
| 70 | CONFIG_USB_DEVICEFS=y | ||
| 71 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 72 | CONFIG_USB_MON=y | ||
| 73 | CONFIG_USB_OHCI_HCD=y | ||
| 74 | CONFIG_USB_STORAGE=y | ||
| 75 | CONFIG_USB_STORAGE_DATAFAB=y | ||
| 76 | CONFIG_USB_STORAGE_FREECOM=y | ||
| 77 | CONFIG_USB_STORAGE_SDDR09=y | ||
| 78 | CONFIG_USB_STORAGE_SDDR55=y | ||
| 79 | CONFIG_USB_STORAGE_JUMPSHOT=y | ||
| 80 | CONFIG_MMC=y | ||
| 81 | CONFIG_MMC_OMAP=y | ||
| 82 | CONFIG_RTC_CLASS=y | ||
| 83 | CONFIG_RTC_DRV_OMAP=y | ||
| 84 | CONFIG_EXT2_FS=y | ||
| 85 | CONFIG_EXT3_FS=y | ||
| 86 | CONFIG_INOTIFY=y | ||
| 87 | CONFIG_AUTOFS_FS=y | ||
| 88 | CONFIG_AUTOFS4_FS=y | ||
| 89 | CONFIG_ISO9660_FS=y | ||
| 90 | CONFIG_JOLIET=y | ||
| 91 | CONFIG_MSDOS_FS=m | ||
| 92 | CONFIG_VFAT_FS=m | ||
| 93 | CONFIG_TMPFS=y | ||
| 94 | CONFIG_NFS_FS=y | ||
| 95 | CONFIG_NFS_V3=y | ||
| 96 | CONFIG_NFS_V4=y | ||
| 97 | CONFIG_ROOT_NFS=y | ||
| 98 | CONFIG_PARTITION_ADVANCED=y | ||
| 99 | CONFIG_MAGIC_SYSRQ=y | ||
| 100 | CONFIG_DEBUG_KERNEL=y | ||
| 101 | CONFIG_CRYPTO_ECB=m | ||
| 102 | CONFIG_CRYPTO_PCBC=m | ||
diff --git a/arch/arm/configs/omap_innovator_1610_defconfig b/arch/arm/configs/omap_innovator_1610_defconfig deleted file mode 100644 index cc7fbf84ddd9..000000000000 --- a/arch/arm/configs/omap_innovator_1610_defconfig +++ /dev/null | |||
| @@ -1,58 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | ||
| 3 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 4 | CONFIG_BLK_DEV_INITRD=y | ||
| 5 | CONFIG_MODULES=y | ||
| 6 | CONFIG_MODULE_UNLOAD=y | ||
| 7 | # CONFIG_BLK_DEV_BSG is not set | ||
| 8 | CONFIG_ARCH_OMAP=y | ||
| 9 | CONFIG_ARCH_OMAP1=y | ||
| 10 | # CONFIG_ARCH_OMAP15XX is not set | ||
| 11 | CONFIG_ARCH_OMAP16XX=y | ||
| 12 | CONFIG_MACH_OMAP_INNOVATOR=y | ||
| 13 | CONFIG_OMAP_ARM_192MHZ=y | ||
| 14 | # CONFIG_OMAP_ARM_60MHZ is not set | ||
| 15 | # CONFIG_ARM_THUMB is not set | ||
| 16 | CONFIG_CPU_DCACHE_WRITETHROUGH=y | ||
| 17 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 18 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 19 | CONFIG_CMDLINE="mem=32M console=tty0 console=ttyS0,115200 initrd=0x10200000,8M root=/dev/ram0 rw" | ||
| 20 | CONFIG_FPE_NWFPE=y | ||
| 21 | CONFIG_NET=y | ||
| 22 | CONFIG_PACKET=m | ||
| 23 | CONFIG_UNIX=y | ||
| 24 | CONFIG_INET=y | ||
| 25 | CONFIG_IP_MULTICAST=y | ||
| 26 | CONFIG_IP_PNP=y | ||
| 27 | CONFIG_IP_PNP_DHCP=y | ||
| 28 | CONFIG_IP_PNP_BOOTP=y | ||
| 29 | # CONFIG_IPV6 is not set | ||
| 30 | CONFIG_BLK_DEV_LOOP=y | ||
| 31 | CONFIG_BLK_DEV_RAM=y | ||
| 32 | CONFIG_BLK_DEV_RAM_SIZE=8192 | ||
| 33 | CONFIG_NETDEVICES=y | ||
| 34 | CONFIG_NET_ETHERNET=y | ||
| 35 | CONFIG_SMC91X=y | ||
| 36 | CONFIG_PPP=y | ||
| 37 | CONFIG_PPP_MULTILINK=y | ||
| 38 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 39 | CONFIG_KEYBOARD_OMAP=y | ||
| 40 | # CONFIG_INPUT_MOUSE is not set | ||
| 41 | CONFIG_SERIAL_8250=y | ||
| 42 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 43 | CONFIG_VIDEO_OUTPUT_CONTROL=m | ||
| 44 | CONFIG_FB=y | ||
| 45 | CONFIG_FB_MODE_HELPERS=y | ||
| 46 | CONFIG_FB_OMAP=y | ||
| 47 | # CONFIG_VGA_CONSOLE is not set | ||
| 48 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 49 | CONFIG_FONTS=y | ||
| 50 | CONFIG_FONT_8x8=y | ||
| 51 | CONFIG_FONT_8x16=y | ||
| 52 | CONFIG_LOGO=y | ||
| 53 | CONFIG_EXT2_FS=y | ||
| 54 | CONFIG_INOTIFY=y | ||
| 55 | CONFIG_AUTOFS_FS=y | ||
| 56 | CONFIG_AUTOFS4_FS=y | ||
| 57 | CONFIG_NFS_FS=y | ||
| 58 | CONFIG_NFS_V3=y | ||
diff --git a/arch/arm/configs/omap_osk_5912_defconfig b/arch/arm/configs/omap_osk_5912_defconfig deleted file mode 100644 index 9105de7661f9..000000000000 --- a/arch/arm/configs/omap_osk_5912_defconfig +++ /dev/null | |||
| @@ -1,87 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | ||
| 3 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 4 | CONFIG_BLK_DEV_INITRD=y | ||
| 5 | CONFIG_MODULES=y | ||
| 6 | CONFIG_MODULE_UNLOAD=y | ||
| 7 | # CONFIG_BLK_DEV_BSG is not set | ||
| 8 | CONFIG_ARCH_OMAP=y | ||
| 9 | CONFIG_ARCH_OMAP1=y | ||
| 10 | CONFIG_OMAP_RESET_CLOCKS=y | ||
| 11 | CONFIG_OMAP_32K_TIMER=y | ||
| 12 | # CONFIG_ARCH_OMAP15XX is not set | ||
| 13 | CONFIG_ARCH_OMAP16XX=y | ||
| 14 | CONFIG_MACH_OMAP_OSK=y | ||
| 15 | CONFIG_OMAP_ARM_192MHZ=y | ||
| 16 | # CONFIG_OMAP_ARM_60MHZ is not set | ||
| 17 | # CONFIG_ARM_THUMB is not set | ||
| 18 | CONFIG_PCCARD=y | ||
| 19 | CONFIG_OMAP_CF=y | ||
| 20 | CONFIG_NO_HZ=y | ||
| 21 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 22 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 23 | CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x10400000,8M root=/dev/ram0 rw" | ||
| 24 | CONFIG_FPE_NWFPE=y | ||
| 25 | CONFIG_PM=y | ||
| 26 | CONFIG_NET=y | ||
| 27 | CONFIG_PACKET=m | ||
| 28 | CONFIG_UNIX=y | ||
| 29 | CONFIG_INET=y | ||
| 30 | CONFIG_IP_MULTICAST=y | ||
| 31 | CONFIG_IP_PNP=y | ||
| 32 | CONFIG_IP_PNP_DHCP=y | ||
| 33 | CONFIG_IP_PNP_BOOTP=y | ||
| 34 | # CONFIG_INET_LRO is not set | ||
| 35 | # CONFIG_IPV6 is not set | ||
| 36 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 37 | CONFIG_MTD=y | ||
| 38 | CONFIG_MTD_PARTITIONS=y | ||
| 39 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 40 | CONFIG_MTD_CHAR=y | ||
| 41 | CONFIG_MTD_BLOCK=y | ||
| 42 | CONFIG_MTD_CFI=y | ||
| 43 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 44 | CONFIG_BLK_DEV_LOOP=y | ||
| 45 | CONFIG_BLK_DEV_RAM=y | ||
| 46 | CONFIG_BLK_DEV_RAM_SIZE=8192 | ||
| 47 | CONFIG_IDE=m | ||
| 48 | CONFIG_BLK_DEV_IDECS=m | ||
| 49 | CONFIG_NETDEVICES=y | ||
| 50 | CONFIG_NET_ETHERNET=y | ||
| 51 | CONFIG_SMC91X=y | ||
| 52 | CONFIG_PPP=y | ||
| 53 | CONFIG_PPP_MULTILINK=y | ||
| 54 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | ||
| 55 | CONFIG_INPUT_EVDEV=y | ||
| 56 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 57 | CONFIG_KEYBOARD_OMAP=y | ||
| 58 | # CONFIG_INPUT_MOUSE is not set | ||
| 59 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 60 | # CONFIG_SERIO is not set | ||
| 61 | CONFIG_SERIAL_8250=y | ||
| 62 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 63 | CONFIG_I2C=y | ||
| 64 | CONFIG_I2C_CHARDEV=y | ||
| 65 | CONFIG_VIDEO_OUTPUT_CONTROL=m | ||
| 66 | CONFIG_FB=y | ||
| 67 | CONFIG_FB_MODE_HELPERS=y | ||
| 68 | CONFIG_FB_OMAP=y | ||
| 69 | # CONFIG_VGA_CONSOLE is not set | ||
| 70 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 71 | CONFIG_FONTS=y | ||
| 72 | CONFIG_FONT_8x8=y | ||
| 73 | CONFIG_LOGO=y | ||
| 74 | # CONFIG_LOGO_LINUX_MONO is not set | ||
| 75 | # CONFIG_LOGO_LINUX_VGA16 is not set | ||
| 76 | CONFIG_EXT2_FS=y | ||
| 77 | CONFIG_INOTIFY=y | ||
| 78 | CONFIG_AUTOFS_FS=y | ||
| 79 | CONFIG_AUTOFS4_FS=y | ||
| 80 | CONFIG_MSDOS_FS=m | ||
| 81 | CONFIG_VFAT_FS=m | ||
| 82 | CONFIG_JFFS2_FS=y | ||
| 83 | CONFIG_NFS_FS=y | ||
| 84 | CONFIG_NFS_V3=y | ||
| 85 | CONFIG_ROOT_NFS=y | ||
| 86 | CONFIG_NLS_CODEPAGE_437=m | ||
| 87 | CONFIG_NLS_ISO8859_1=m | ||
diff --git a/arch/arm/configs/omap_perseus2_730_defconfig b/arch/arm/configs/omap_perseus2_730_defconfig deleted file mode 100644 index aa777e624e23..000000000000 --- a/arch/arm/configs/omap_perseus2_730_defconfig +++ /dev/null | |||
| @@ -1,65 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | ||
| 3 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 4 | CONFIG_BLK_DEV_INITRD=y | ||
| 5 | CONFIG_SLAB=y | ||
| 6 | CONFIG_MODULES=y | ||
| 7 | CONFIG_MODULE_UNLOAD=y | ||
| 8 | # CONFIG_BLK_DEV_BSG is not set | ||
| 9 | CONFIG_ARCH_OMAP=y | ||
| 10 | CONFIG_ARCH_OMAP1=y | ||
| 11 | CONFIG_ARCH_OMAP730=y | ||
| 12 | # CONFIG_ARCH_OMAP15XX is not set | ||
| 13 | CONFIG_MACH_OMAP_PERSEUS2=y | ||
| 14 | CONFIG_OMAP_ARM_182MHZ=y | ||
| 15 | # CONFIG_OMAP_ARM_60MHZ is not set | ||
| 16 | # CONFIG_ARM_THUMB is not set | ||
| 17 | CONFIG_PREEMPT=y | ||
| 18 | CONFIG_LEDS=y | ||
| 19 | CONFIG_LEDS_CPU=y | ||
| 20 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 21 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 22 | CONFIG_CMDLINE="mem=32M console=ttyS0,115200 ip=dhcp" | ||
| 23 | CONFIG_FPE_NWFPE=y | ||
| 24 | CONFIG_PM=y | ||
| 25 | CONFIG_NET=y | ||
| 26 | CONFIG_PACKET=y | ||
| 27 | CONFIG_UNIX=y | ||
| 28 | CONFIG_INET=y | ||
| 29 | CONFIG_IP_MULTICAST=y | ||
| 30 | CONFIG_IP_PNP=y | ||
| 31 | CONFIG_IP_PNP_DHCP=y | ||
| 32 | CONFIG_IP_PNP_BOOTP=y | ||
| 33 | # CONFIG_IPV6 is not set | ||
| 34 | CONFIG_MTD=y | ||
| 35 | CONFIG_MTD_PARTITIONS=y | ||
| 36 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 37 | CONFIG_MTD_CHAR=y | ||
| 38 | CONFIG_MTD_BLOCK=y | ||
| 39 | CONFIG_MTD_CFI=y | ||
| 40 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 41 | CONFIG_MTD_NAND=y | ||
| 42 | CONFIG_BLK_DEV_LOOP=y | ||
| 43 | CONFIG_BLK_DEV_RAM=y | ||
| 44 | CONFIG_BLK_DEV_RAM_SIZE=8192 | ||
| 45 | CONFIG_NETDEVICES=y | ||
| 46 | CONFIG_NET_ETHERNET=y | ||
| 47 | CONFIG_SMC91X=y | ||
| 48 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 49 | CONFIG_KEYBOARD_OMAP=y | ||
| 50 | # CONFIG_INPUT_MOUSE is not set | ||
| 51 | CONFIG_SERIAL_8250=y | ||
| 52 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 53 | # CONFIG_LEGACY_PTYS is not set | ||
| 54 | CONFIG_VIDEO_OUTPUT_CONTROL=m | ||
| 55 | CONFIG_FB=y | ||
| 56 | CONFIG_FB_MODE_HELPERS=y | ||
| 57 | CONFIG_FB_VIRTUAL=y | ||
| 58 | # CONFIG_VGA_CONSOLE is not set | ||
| 59 | CONFIG_RTC_CLASS=y | ||
| 60 | CONFIG_RTC_DRV_OMAP=y | ||
| 61 | CONFIG_EXT2_FS=y | ||
| 62 | CONFIG_INOTIFY=y | ||
| 63 | CONFIG_JFFS2_FS=y | ||
| 64 | CONFIG_NFS_FS=y | ||
| 65 | CONFIG_ROOT_NFS=y | ||
diff --git a/arch/arm/configs/palmte_defconfig b/arch/arm/configs/palmte_defconfig deleted file mode 100644 index 828d7cb9e667..000000000000 --- a/arch/arm/configs/palmte_defconfig +++ /dev/null | |||
| @@ -1,48 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | # CONFIG_SWAP is not set | ||
| 3 | CONFIG_SYSVIPC=y | ||
| 4 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 5 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 6 | CONFIG_SLAB=y | ||
| 7 | # CONFIG_IOSCHED_DEADLINE is not set | ||
| 8 | # CONFIG_IOSCHED_CFQ is not set | ||
| 9 | CONFIG_ARCH_OMAP=y | ||
| 10 | CONFIG_ARCH_OMAP1=y | ||
| 11 | CONFIG_MACH_OMAP_PALMTE=y | ||
| 12 | CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER=y | ||
| 13 | # CONFIG_OMAP_ARM_60MHZ is not set | ||
| 14 | # CONFIG_ARM_THUMB is not set | ||
| 15 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set | ||
| 16 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 17 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 18 | CONFIG_FPE_NWFPE=y | ||
| 19 | # CONFIG_STANDALONE is not set | ||
| 20 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set | ||
| 21 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | ||
| 22 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=320 | ||
| 23 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320 | ||
| 24 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 25 | # CONFIG_INPUT_MOUSE is not set | ||
| 26 | # CONFIG_SERIO is not set | ||
| 27 | # CONFIG_LEGACY_PTYS is not set | ||
| 28 | # CONFIG_HWMON is not set | ||
| 29 | CONFIG_FB=y | ||
| 30 | CONFIG_FB_OMAP=y | ||
| 31 | # CONFIG_VGA_CONSOLE is not set | ||
| 32 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 33 | CONFIG_LOGO=y | ||
| 34 | # CONFIG_LOGO_LINUX_MONO is not set | ||
| 35 | # CONFIG_LOGO_LINUX_VGA16 is not set | ||
| 36 | CONFIG_USB_GADGET=y | ||
| 37 | CONFIG_MMC=y | ||
| 38 | CONFIG_MMC_OMAP=y | ||
| 39 | CONFIG_EXT2_FS=y | ||
| 40 | CONFIG_MSDOS_FS=y | ||
| 41 | CONFIG_VFAT_FS=y | ||
| 42 | CONFIG_FAT_DEFAULT_CODEPAGE=850 | ||
| 43 | CONFIG_TMPFS=y | ||
| 44 | CONFIG_CRAMFS=y | ||
| 45 | CONFIG_PARTITION_ADVANCED=y | ||
| 46 | CONFIG_NLS_CODEPAGE_850=y | ||
| 47 | CONFIG_NLS_ISO8859_1=y | ||
| 48 | CONFIG_CRC_CCITT=y | ||
diff --git a/arch/arm/configs/palmtt_defconfig b/arch/arm/configs/palmtt_defconfig deleted file mode 100644 index 31d02c48a3d9..000000000000 --- a/arch/arm/configs/palmtt_defconfig +++ /dev/null | |||
| @@ -1,56 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | ||
| 3 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 4 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 5 | CONFIG_SLAB=y | ||
| 6 | # CONFIG_IOSCHED_DEADLINE is not set | ||
| 7 | # CONFIG_IOSCHED_CFQ is not set | ||
| 8 | CONFIG_ARCH_OMAP=y | ||
| 9 | CONFIG_ARCH_OMAP1=y | ||
| 10 | CONFIG_MACH_OMAP_PALMTT=y | ||
| 11 | CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER=y | ||
| 12 | # CONFIG_OMAP_ARM_60MHZ is not set | ||
| 13 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set | ||
| 14 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 15 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 16 | CONFIG_CMDLINE="root=/dev/mmcblk0p2 rw init=/init" | ||
| 17 | CONFIG_FPE_NWFPE=y | ||
| 18 | CONFIG_NET=y | ||
| 19 | CONFIG_PACKET=y | ||
| 20 | CONFIG_UNIX=y | ||
| 21 | CONFIG_NET_KEY=y | ||
| 22 | CONFIG_INET=y | ||
| 23 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | ||
| 24 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | ||
| 25 | # CONFIG_INET_XFRM_MODE_BEET is not set | ||
| 26 | # CONFIG_INET_DIAG is not set | ||
| 27 | # CONFIG_IPV6 is not set | ||
| 28 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=320 | ||
| 29 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320 | ||
| 30 | CONFIG_INPUT_EVDEV=y | ||
| 31 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 32 | # CONFIG_INPUT_MOUSE is not set | ||
| 33 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 34 | CONFIG_TOUCHSCREEN_ADS7846=y | ||
| 35 | # CONFIG_SERIO is not set | ||
| 36 | CONFIG_SPI=y | ||
| 37 | CONFIG_SPI_OMAP_UWIRE=y | ||
| 38 | CONFIG_FB=y | ||
| 39 | CONFIG_FIRMWARE_EDID=y | ||
| 40 | CONFIG_FB_OMAP=y | ||
| 41 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | ||
| 42 | # CONFIG_VGA_CONSOLE is not set | ||
| 43 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 44 | CONFIG_NEW_LEDS=y | ||
| 45 | CONFIG_LEDS_CLASS=y | ||
| 46 | CONFIG_LEDS_TRIGGERS=y | ||
| 47 | CONFIG_LEDS_TRIGGER_TIMER=y | ||
| 48 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
| 49 | CONFIG_RTC_CLASS=y | ||
| 50 | CONFIG_RTC_DRV_OMAP=y | ||
| 51 | CONFIG_EXT2_FS=y | ||
| 52 | CONFIG_PARTITION_ADVANCED=y | ||
| 53 | # CONFIG_ENABLE_MUST_CHECK is not set | ||
| 54 | CONFIG_CRC_CCITT=y | ||
| 55 | CONFIG_CRC16=y | ||
| 56 | CONFIG_LIBCRC32C=y | ||
diff --git a/arch/arm/configs/palmz71_defconfig b/arch/arm/configs/palmz71_defconfig deleted file mode 100644 index c478db6f5192..000000000000 --- a/arch/arm/configs/palmz71_defconfig +++ /dev/null | |||
| @@ -1,53 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_LOCALVERSION="-z71" | ||
| 3 | CONFIG_SYSVIPC=y | ||
| 4 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 5 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 6 | CONFIG_SLAB=y | ||
| 7 | # CONFIG_IOSCHED_DEADLINE is not set | ||
| 8 | # CONFIG_IOSCHED_CFQ is not set | ||
| 9 | CONFIG_ARCH_OMAP=y | ||
| 10 | CONFIG_ARCH_OMAP1=y | ||
| 11 | CONFIG_MACH_OMAP_PALMZ71=y | ||
| 12 | CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER=y | ||
| 13 | # CONFIG_OMAP_ARM_60MHZ is not set | ||
| 14 | # CONFIG_ARM_THUMB is not set | ||
| 15 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set | ||
| 16 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 17 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 18 | CONFIG_FPE_NWFPE=y | ||
| 19 | CONFIG_NET=y | ||
| 20 | CONFIG_PACKET=y | ||
| 21 | CONFIG_UNIX=y | ||
| 22 | CONFIG_NET_KEY=y | ||
| 23 | CONFIG_INET=y | ||
| 24 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | ||
| 25 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | ||
| 26 | # CONFIG_INET_DIAG is not set | ||
| 27 | # CONFIG_IPV6 is not set | ||
| 28 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=320 | ||
| 29 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320 | ||
| 30 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 31 | # CONFIG_INPUT_MOUSE is not set | ||
| 32 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 33 | CONFIG_TOUCHSCREEN_ADS7846=y | ||
| 34 | # CONFIG_SERIO is not set | ||
| 35 | CONFIG_SERIAL_8250=y | ||
| 36 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 37 | CONFIG_LEGACY_PTY_COUNT=16 | ||
| 38 | CONFIG_SPI=y | ||
| 39 | CONFIG_SPI_OMAP_UWIRE=y | ||
| 40 | CONFIG_FB=y | ||
| 41 | CONFIG_FIRMWARE_EDID=y | ||
| 42 | CONFIG_FB_OMAP=y | ||
| 43 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | ||
| 44 | # CONFIG_VGA_CONSOLE is not set | ||
| 45 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 46 | CONFIG_MMC=y | ||
| 47 | CONFIG_MMC_OMAP=y | ||
| 48 | CONFIG_RTC_CLASS=y | ||
| 49 | CONFIG_RTC_DRV_OMAP=y | ||
| 50 | CONFIG_EXT2_FS=y | ||
| 51 | CONFIG_CRC_CCITT=y | ||
| 52 | CONFIG_CRC16=y | ||
| 53 | CONFIG_LIBCRC32C=y | ||
diff --git a/arch/arm/configs/sx1_defconfig b/arch/arm/configs/sx1_defconfig deleted file mode 100644 index 20a861877a33..000000000000 --- a/arch/arm/configs/sx1_defconfig +++ /dev/null | |||
| @@ -1,110 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | ||
| 3 | CONFIG_POSIX_MQUEUE=y | ||
| 4 | CONFIG_IKCONFIG=y | ||
| 5 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 6 | CONFIG_EMBEDDED=y | ||
| 7 | # CONFIG_KALLSYMS is not set | ||
| 8 | # CONFIG_ELF_CORE is not set | ||
| 9 | # CONFIG_BASE_FULL is not set | ||
| 10 | # CONFIG_SHMEM is not set | ||
| 11 | # CONFIG_VM_EVENT_COUNTERS is not set | ||
| 12 | CONFIG_SLOB=y | ||
| 13 | CONFIG_PROFILING=y | ||
| 14 | CONFIG_OPROFILE=y | ||
| 15 | CONFIG_MODULES=y | ||
| 16 | CONFIG_MODULE_UNLOAD=y | ||
| 17 | # CONFIG_IOSCHED_CFQ is not set | ||
| 18 | CONFIG_ARCH_OMAP=y | ||
| 19 | CONFIG_ARCH_OMAP1=y | ||
| 20 | CONFIG_OMAP_MBOX_FWK=y | ||
| 21 | CONFIG_MACH_SX1=y | ||
| 22 | CONFIG_OMAP_ARM_168MHZ=y | ||
| 23 | # CONFIG_OMAP_ARM_60MHZ is not set | ||
| 24 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set | ||
| 25 | CONFIG_PREEMPT=y | ||
| 26 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 27 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 28 | CONFIG_FPE_NWFPE=y | ||
| 29 | CONFIG_BINFMT_MISC=y | ||
| 30 | CONFIG_NET=y | ||
| 31 | CONFIG_PACKET=y | ||
| 32 | CONFIG_UNIX=y | ||
| 33 | CONFIG_INET=y | ||
| 34 | CONFIG_IP_PNP=y | ||
| 35 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | ||
| 36 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | ||
| 37 | # CONFIG_INET_XFRM_MODE_BEET is not set | ||
| 38 | # CONFIG_INET_DIAG is not set | ||
| 39 | # CONFIG_IPV6 is not set | ||
| 40 | # CONFIG_FW_LOADER is not set | ||
| 41 | CONFIG_CONNECTOR=y | ||
| 42 | # CONFIG_PROC_EVENTS is not set | ||
| 43 | CONFIG_BLK_DEV_LOOP=m | ||
| 44 | CONFIG_BLK_DEV_RAM=m | ||
| 45 | CONFIG_BLK_DEV_RAM_COUNT=2 | ||
| 46 | CONFIG_NETDEVICES=y | ||
| 47 | CONFIG_PHYLIB=y | ||
| 48 | CONFIG_NET_ETHERNET=y | ||
| 49 | CONFIG_MII=y | ||
| 50 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 51 | CONFIG_INPUT_EVDEV=y | ||
| 52 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 53 | CONFIG_KEYBOARD_OMAP=y | ||
| 54 | # CONFIG_INPUT_MOUSE is not set | ||
| 55 | # CONFIG_SERIO is not set | ||
| 56 | CONFIG_SERIAL_8250=y | ||
| 57 | CONFIG_SERIAL_8250_NR_UARTS=3 | ||
| 58 | # CONFIG_LEGACY_PTYS is not set | ||
| 59 | # CONFIG_HW_RANDOM is not set | ||
| 60 | CONFIG_I2C=y | ||
| 61 | CONFIG_I2C_CHARDEV=y | ||
| 62 | CONFIG_I2C_OMAP=y | ||
| 63 | # CONFIG_HWMON is not set | ||
| 64 | CONFIG_FB=y | ||
| 65 | CONFIG_FB_OMAP=y | ||
| 66 | CONFIG_FB_OMAP_BOOTLOADER_INIT=y | ||
| 67 | # CONFIG_VGA_CONSOLE is not set | ||
| 68 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 69 | CONFIG_FONTS=y | ||
| 70 | CONFIG_FONT_MINI_4x6=y | ||
| 71 | CONFIG_LOGO=y | ||
| 72 | # CONFIG_LOGO_LINUX_MONO is not set | ||
| 73 | # CONFIG_LOGO_LINUX_VGA16 is not set | ||
| 74 | CONFIG_SOUND=y | ||
| 75 | CONFIG_SND=y | ||
| 76 | CONFIG_SND_MIXER_OSS=y | ||
| 77 | CONFIG_SND_PCM_OSS=y | ||
| 78 | # CONFIG_SND_SUPPORT_OLD_API is not set | ||
| 79 | # CONFIG_SND_VERBOSE_PROCFS is not set | ||
| 80 | CONFIG_USB_GADGET=y | ||
| 81 | CONFIG_USB_ETH=m | ||
| 82 | CONFIG_MMC=y | ||
| 83 | CONFIG_MMC_OMAP=y | ||
| 84 | CONFIG_RTC_CLASS=y | ||
| 85 | CONFIG_RTC_DRV_OMAP=y | ||
| 86 | CONFIG_EXT2_FS=y | ||
| 87 | # CONFIG_DNOTIFY is not set | ||
| 88 | CONFIG_INOTIFY=y | ||
| 89 | CONFIG_MSDOS_FS=y | ||
| 90 | CONFIG_VFAT_FS=y | ||
| 91 | CONFIG_FAT_DEFAULT_CODEPAGE=866 | ||
| 92 | CONFIG_FAT_DEFAULT_IOCHARSET="koi8-r" | ||
| 93 | CONFIG_CRAMFS=y | ||
| 94 | CONFIG_NFS_FS=y | ||
| 95 | CONFIG_ROOT_NFS=y | ||
| 96 | CONFIG_PARTITION_ADVANCED=y | ||
| 97 | CONFIG_NLS_CODEPAGE_437=y | ||
| 98 | CONFIG_NLS_CODEPAGE_866=y | ||
| 99 | CONFIG_NLS_CODEPAGE_1251=y | ||
| 100 | CONFIG_NLS_ISO8859_1=y | ||
| 101 | CONFIG_NLS_ISO8859_5=y | ||
| 102 | CONFIG_NLS_KOI8_R=y | ||
| 103 | CONFIG_NLS_UTF8=y | ||
| 104 | # CONFIG_ENABLE_MUST_CHECK is not set | ||
| 105 | CONFIG_DEBUG_KERNEL=y | ||
| 106 | # CONFIG_DETECT_SOFTLOCKUP is not set | ||
| 107 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 108 | CONFIG_CRC_CCITT=y | ||
| 109 | CONFIG_CRC16=y | ||
| 110 | CONFIG_LIBCRC32C=y | ||
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig index be80f037f85a..52d86c4485bf 100644 --- a/arch/arm/configs/u8500_defconfig +++ b/arch/arm/configs/u8500_defconfig | |||
| @@ -9,6 +9,10 @@ CONFIG_MODULE_UNLOAD=y | |||
| 9 | # CONFIG_LBDAF is not set | 9 | # CONFIG_LBDAF is not set |
| 10 | # CONFIG_BLK_DEV_BSG is not set | 10 | # CONFIG_BLK_DEV_BSG is not set |
| 11 | CONFIG_ARCH_U8500=y | 11 | CONFIG_ARCH_U8500=y |
| 12 | CONFIG_UX500_SOC_DB5500=y | ||
| 13 | CONFIG_UX500_SOC_DB8500=y | ||
| 14 | CONFIG_MACH_U8500=y | ||
| 15 | CONFIG_MACH_U5500=y | ||
| 12 | CONFIG_SMP=y | 16 | CONFIG_SMP=y |
| 13 | CONFIG_NR_CPUS=2 | 17 | CONFIG_NR_CPUS=2 |
| 14 | CONFIG_PREEMPT=y | 18 | CONFIG_PREEMPT=y |
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 749bb6622404..bc2d2d75f706 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h | |||
| @@ -18,6 +18,7 @@ | |||
| 18 | #endif | 18 | #endif |
| 19 | 19 | ||
| 20 | #include <asm/ptrace.h> | 20 | #include <asm/ptrace.h> |
| 21 | #include <asm/domain.h> | ||
| 21 | 22 | ||
| 22 | /* | 23 | /* |
| 23 | * Endian independent macros for shifting bytes within registers. | 24 | * Endian independent macros for shifting bytes within registers. |
| @@ -157,16 +158,24 @@ | |||
| 157 | #ifdef CONFIG_SMP | 158 | #ifdef CONFIG_SMP |
| 158 | #define ALT_SMP(instr...) \ | 159 | #define ALT_SMP(instr...) \ |
| 159 | 9998: instr | 160 | 9998: instr |
| 161 | /* | ||
| 162 | * Note: if you get assembler errors from ALT_UP() when building with | ||
| 163 | * CONFIG_THUMB2_KERNEL, you almost certainly need to use | ||
| 164 | * ALT_SMP( W(instr) ... ) | ||
| 165 | */ | ||
| 160 | #define ALT_UP(instr...) \ | 166 | #define ALT_UP(instr...) \ |
| 161 | .pushsection ".alt.smp.init", "a" ;\ | 167 | .pushsection ".alt.smp.init", "a" ;\ |
| 162 | .long 9998b ;\ | 168 | .long 9998b ;\ |
| 163 | instr ;\ | 169 | 9997: instr ;\ |
| 170 | .if . - 9997b != 4 ;\ | ||
| 171 | .error "ALT_UP() content must assemble to exactly 4 bytes";\ | ||
| 172 | .endif ;\ | ||
| 164 | .popsection | 173 | .popsection |
| 165 | #define ALT_UP_B(label) \ | 174 | #define ALT_UP_B(label) \ |
| 166 | .equ up_b_offset, label - 9998b ;\ | 175 | .equ up_b_offset, label - 9998b ;\ |
| 167 | .pushsection ".alt.smp.init", "a" ;\ | 176 | .pushsection ".alt.smp.init", "a" ;\ |
| 168 | .long 9998b ;\ | 177 | .long 9998b ;\ |
| 169 | b . + up_b_offset ;\ | 178 | W(b) . + up_b_offset ;\ |
| 170 | .popsection | 179 | .popsection |
| 171 | #else | 180 | #else |
| 172 | #define ALT_SMP(instr...) | 181 | #define ALT_SMP(instr...) |
| @@ -177,16 +186,24 @@ | |||
| 177 | /* | 186 | /* |
| 178 | * SMP data memory barrier | 187 | * SMP data memory barrier |
| 179 | */ | 188 | */ |
| 180 | .macro smp_dmb | 189 | .macro smp_dmb mode |
| 181 | #ifdef CONFIG_SMP | 190 | #ifdef CONFIG_SMP |
| 182 | #if __LINUX_ARM_ARCH__ >= 7 | 191 | #if __LINUX_ARM_ARCH__ >= 7 |
| 192 | .ifeqs "\mode","arm" | ||
| 183 | ALT_SMP(dmb) | 193 | ALT_SMP(dmb) |
| 194 | .else | ||
| 195 | ALT_SMP(W(dmb)) | ||
| 196 | .endif | ||
| 184 | #elif __LINUX_ARM_ARCH__ == 6 | 197 | #elif __LINUX_ARM_ARCH__ == 6 |
| 185 | ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb | 198 | ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb |
| 186 | #else | 199 | #else |
| 187 | #error Incompatible SMP platform | 200 | #error Incompatible SMP platform |
| 188 | #endif | 201 | #endif |
| 202 | .ifeqs "\mode","arm" | ||
| 189 | ALT_UP(nop) | 203 | ALT_UP(nop) |
| 204 | .else | ||
| 205 | ALT_UP(W(nop)) | ||
| 206 | .endif | ||
| 190 | #endif | 207 | #endif |
| 191 | .endm | 208 | .endm |
| 192 | 209 | ||
| @@ -206,12 +223,12 @@ | |||
| 206 | */ | 223 | */ |
| 207 | #ifdef CONFIG_THUMB2_KERNEL | 224 | #ifdef CONFIG_THUMB2_KERNEL |
| 208 | 225 | ||
| 209 | .macro usraccoff, instr, reg, ptr, inc, off, cond, abort | 226 | .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=T() |
| 210 | 9999: | 227 | 9999: |
| 211 | .if \inc == 1 | 228 | .if \inc == 1 |
| 212 | \instr\cond\()bt \reg, [\ptr, #\off] | 229 | \instr\cond\()b\()\t\().w \reg, [\ptr, #\off] |
| 213 | .elseif \inc == 4 | 230 | .elseif \inc == 4 |
| 214 | \instr\cond\()t \reg, [\ptr, #\off] | 231 | \instr\cond\()\t\().w \reg, [\ptr, #\off] |
| 215 | .else | 232 | .else |
| 216 | .error "Unsupported inc macro argument" | 233 | .error "Unsupported inc macro argument" |
| 217 | .endif | 234 | .endif |
| @@ -246,13 +263,13 @@ | |||
| 246 | 263 | ||
| 247 | #else /* !CONFIG_THUMB2_KERNEL */ | 264 | #else /* !CONFIG_THUMB2_KERNEL */ |
| 248 | 265 | ||
| 249 | .macro usracc, instr, reg, ptr, inc, cond, rept, abort | 266 | .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=T() |
| 250 | .rept \rept | 267 | .rept \rept |
| 251 | 9999: | 268 | 9999: |
| 252 | .if \inc == 1 | 269 | .if \inc == 1 |
| 253 | \instr\cond\()bt \reg, [\ptr], #\inc | 270 | \instr\cond\()b\()\t \reg, [\ptr], #\inc |
| 254 | .elseif \inc == 4 | 271 | .elseif \inc == 4 |
| 255 | \instr\cond\()t \reg, [\ptr], #\inc | 272 | \instr\cond\()\t \reg, [\ptr], #\inc |
| 256 | .else | 273 | .else |
| 257 | .error "Unsupported inc macro argument" | 274 | .error "Unsupported inc macro argument" |
| 258 | .endif | 275 | .endif |
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index 9d6122096fbe..75fe66bc02b4 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h | |||
| @@ -23,4 +23,6 @@ | |||
| 23 | #define ARCH_SLAB_MINALIGN 8 | 23 | #define ARCH_SLAB_MINALIGN 8 |
| 24 | #endif | 24 | #endif |
| 25 | 25 | ||
| 26 | #define __read_mostly __attribute__((__section__(".data..read_mostly"))) | ||
| 27 | |||
| 26 | #endif | 28 | #endif |
diff --git a/arch/arm/include/asm/clkdev.h b/arch/arm/include/asm/clkdev.h index b56c1389b6fa..765d33222369 100644 --- a/arch/arm/include/asm/clkdev.h +++ b/arch/arm/include/asm/clkdev.h | |||
| @@ -12,23 +12,13 @@ | |||
| 12 | #ifndef __ASM_CLKDEV_H | 12 | #ifndef __ASM_CLKDEV_H |
| 13 | #define __ASM_CLKDEV_H | 13 | #define __ASM_CLKDEV_H |
| 14 | 14 | ||
| 15 | struct clk; | 15 | #include <linux/slab.h> |
| 16 | struct device; | ||
| 17 | 16 | ||
| 18 | struct clk_lookup { | 17 | #include <mach/clkdev.h> |
| 19 | struct list_head node; | ||
| 20 | const char *dev_id; | ||
| 21 | const char *con_id; | ||
| 22 | struct clk *clk; | ||
| 23 | }; | ||
| 24 | 18 | ||
| 25 | struct clk_lookup *clkdev_alloc(struct clk *clk, const char *con_id, | 19 | static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size) |
| 26 | const char *dev_fmt, ...); | 20 | { |
| 27 | 21 | return kzalloc(size, GFP_KERNEL); | |
| 28 | void clkdev_add(struct clk_lookup *cl); | 22 | } |
| 29 | void clkdev_drop(struct clk_lookup *cl); | ||
| 30 | |||
| 31 | void clkdev_add_table(struct clk_lookup *, size_t); | ||
| 32 | int clk_add_alias(const char *, const char *, char *, struct device *); | ||
| 33 | 23 | ||
| 34 | #endif | 24 | #endif |
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index c568da7dcae4..4fff837363ed 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h | |||
| @@ -5,24 +5,29 @@ | |||
| 5 | 5 | ||
| 6 | #include <linux/mm_types.h> | 6 | #include <linux/mm_types.h> |
| 7 | #include <linux/scatterlist.h> | 7 | #include <linux/scatterlist.h> |
| 8 | #include <linux/dma-debug.h> | ||
| 8 | 9 | ||
| 9 | #include <asm-generic/dma-coherent.h> | 10 | #include <asm-generic/dma-coherent.h> |
| 10 | #include <asm/memory.h> | 11 | #include <asm/memory.h> |
| 11 | 12 | ||
| 13 | #ifdef __arch_page_to_dma | ||
| 14 | #error Please update to __arch_pfn_to_dma | ||
| 15 | #endif | ||
| 16 | |||
| 12 | /* | 17 | /* |
| 13 | * page_to_dma/dma_to_virt/virt_to_dma are architecture private functions | 18 | * dma_to_pfn/pfn_to_dma/dma_to_virt/virt_to_dma are architecture private |
| 14 | * used internally by the DMA-mapping API to provide DMA addresses. They | 19 | * functions used internally by the DMA-mapping API to provide DMA |
| 15 | * must not be used by drivers. | 20 | * addresses. They must not be used by drivers. |
| 16 | */ | 21 | */ |
| 17 | #ifndef __arch_page_to_dma | 22 | #ifndef __arch_pfn_to_dma |
| 18 | static inline dma_addr_t page_to_dma(struct device *dev, struct page *page) | 23 | static inline dma_addr_t pfn_to_dma(struct device *dev, unsigned long pfn) |
| 19 | { | 24 | { |
| 20 | return (dma_addr_t)__pfn_to_bus(page_to_pfn(page)); | 25 | return (dma_addr_t)__pfn_to_bus(pfn); |
| 21 | } | 26 | } |
| 22 | 27 | ||
| 23 | static inline struct page *dma_to_page(struct device *dev, dma_addr_t addr) | 28 | static inline unsigned long dma_to_pfn(struct device *dev, dma_addr_t addr) |
| 24 | { | 29 | { |
| 25 | return pfn_to_page(__bus_to_pfn(addr)); | 30 | return __bus_to_pfn(addr); |
| 26 | } | 31 | } |
| 27 | 32 | ||
| 28 | static inline void *dma_to_virt(struct device *dev, dma_addr_t addr) | 33 | static inline void *dma_to_virt(struct device *dev, dma_addr_t addr) |
| @@ -35,14 +40,14 @@ static inline dma_addr_t virt_to_dma(struct device *dev, void *addr) | |||
| 35 | return (dma_addr_t)__virt_to_bus((unsigned long)(addr)); | 40 | return (dma_addr_t)__virt_to_bus((unsigned long)(addr)); |
| 36 | } | 41 | } |
| 37 | #else | 42 | #else |
| 38 | static inline dma_addr_t page_to_dma(struct device *dev, struct page *page) | 43 | static inline dma_addr_t pfn_to_dma(struct device *dev, unsigned long pfn) |
| 39 | { | 44 | { |
| 40 | return __arch_page_to_dma(dev, page); | 45 | return __arch_pfn_to_dma(dev, pfn); |
| 41 | } | 46 | } |
| 42 | 47 | ||
| 43 | static inline struct page *dma_to_page(struct device *dev, dma_addr_t addr) | 48 | static inline unsigned long dma_to_pfn(struct device *dev, dma_addr_t addr) |
| 44 | { | 49 | { |
| 45 | return __arch_dma_to_page(dev, addr); | 50 | return __arch_dma_to_pfn(dev, addr); |
| 46 | } | 51 | } |
| 47 | 52 | ||
| 48 | static inline void *dma_to_virt(struct device *dev, dma_addr_t addr) | 53 | static inline void *dma_to_virt(struct device *dev, dma_addr_t addr) |
| @@ -293,13 +298,13 @@ extern int dma_needs_bounce(struct device*, dma_addr_t, size_t); | |||
| 293 | /* | 298 | /* |
| 294 | * The DMA API, implemented by dmabounce.c. See below for descriptions. | 299 | * The DMA API, implemented by dmabounce.c. See below for descriptions. |
| 295 | */ | 300 | */ |
| 296 | extern dma_addr_t dma_map_single(struct device *, void *, size_t, | 301 | extern dma_addr_t __dma_map_single(struct device *, void *, size_t, |
| 297 | enum dma_data_direction); | 302 | enum dma_data_direction); |
| 298 | extern void dma_unmap_single(struct device *, dma_addr_t, size_t, | 303 | extern void __dma_unmap_single(struct device *, dma_addr_t, size_t, |
| 299 | enum dma_data_direction); | 304 | enum dma_data_direction); |
| 300 | extern dma_addr_t dma_map_page(struct device *, struct page *, | 305 | extern dma_addr_t __dma_map_page(struct device *, struct page *, |
| 301 | unsigned long, size_t, enum dma_data_direction); | 306 | unsigned long, size_t, enum dma_data_direction); |
| 302 | extern void dma_unmap_page(struct device *, dma_addr_t, size_t, | 307 | extern void __dma_unmap_page(struct device *, dma_addr_t, size_t, |
| 303 | enum dma_data_direction); | 308 | enum dma_data_direction); |
| 304 | 309 | ||
| 305 | /* | 310 | /* |
| @@ -323,6 +328,34 @@ static inline int dmabounce_sync_for_device(struct device *d, dma_addr_t addr, | |||
| 323 | } | 328 | } |
| 324 | 329 | ||
| 325 | 330 | ||
| 331 | static inline dma_addr_t __dma_map_single(struct device *dev, void *cpu_addr, | ||
| 332 | size_t size, enum dma_data_direction dir) | ||
| 333 | { | ||
| 334 | __dma_single_cpu_to_dev(cpu_addr, size, dir); | ||
| 335 | return virt_to_dma(dev, cpu_addr); | ||
| 336 | } | ||
| 337 | |||
| 338 | static inline dma_addr_t __dma_map_page(struct device *dev, struct page *page, | ||
| 339 | unsigned long offset, size_t size, enum dma_data_direction dir) | ||
| 340 | { | ||
| 341 | __dma_page_cpu_to_dev(page, offset, size, dir); | ||
| 342 | return pfn_to_dma(dev, page_to_pfn(page)) + offset; | ||
| 343 | } | ||
| 344 | |||
| 345 | static inline void __dma_unmap_single(struct device *dev, dma_addr_t handle, | ||
| 346 | size_t size, enum dma_data_direction dir) | ||
| 347 | { | ||
| 348 | __dma_single_dev_to_cpu(dma_to_virt(dev, handle), size, dir); | ||
| 349 | } | ||
| 350 | |||
| 351 | static inline void __dma_unmap_page(struct device *dev, dma_addr_t handle, | ||
| 352 | size_t size, enum dma_data_direction dir) | ||
| 353 | { | ||
| 354 | __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)), | ||
| 355 | handle & ~PAGE_MASK, size, dir); | ||
| 356 | } | ||
| 357 | #endif /* CONFIG_DMABOUNCE */ | ||
| 358 | |||
| 326 | /** | 359 | /** |
| 327 | * dma_map_single - map a single buffer for streaming DMA | 360 | * dma_map_single - map a single buffer for streaming DMA |
| 328 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | 361 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
| @@ -340,11 +373,16 @@ static inline int dmabounce_sync_for_device(struct device *d, dma_addr_t addr, | |||
| 340 | static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr, | 373 | static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr, |
| 341 | size_t size, enum dma_data_direction dir) | 374 | size_t size, enum dma_data_direction dir) |
| 342 | { | 375 | { |
| 376 | dma_addr_t addr; | ||
| 377 | |||
| 343 | BUG_ON(!valid_dma_direction(dir)); | 378 | BUG_ON(!valid_dma_direction(dir)); |
| 344 | 379 | ||
| 345 | __dma_single_cpu_to_dev(cpu_addr, size, dir); | 380 | addr = __dma_map_single(dev, cpu_addr, size, dir); |
| 381 | debug_dma_map_page(dev, virt_to_page(cpu_addr), | ||
| 382 | (unsigned long)cpu_addr & ~PAGE_MASK, size, | ||
| 383 | dir, addr, true); | ||
| 346 | 384 | ||
| 347 | return virt_to_dma(dev, cpu_addr); | 385 | return addr; |
| 348 | } | 386 | } |
| 349 | 387 | ||
| 350 | /** | 388 | /** |
| @@ -364,11 +402,14 @@ static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr, | |||
| 364 | static inline dma_addr_t dma_map_page(struct device *dev, struct page *page, | 402 | static inline dma_addr_t dma_map_page(struct device *dev, struct page *page, |
| 365 | unsigned long offset, size_t size, enum dma_data_direction dir) | 403 | unsigned long offset, size_t size, enum dma_data_direction dir) |
| 366 | { | 404 | { |
| 405 | dma_addr_t addr; | ||
| 406 | |||
| 367 | BUG_ON(!valid_dma_direction(dir)); | 407 | BUG_ON(!valid_dma_direction(dir)); |
| 368 | 408 | ||
| 369 | __dma_page_cpu_to_dev(page, offset, size, dir); | 409 | addr = __dma_map_page(dev, page, offset, size, dir); |
| 410 | debug_dma_map_page(dev, page, offset, size, dir, addr, false); | ||
| 370 | 411 | ||
| 371 | return page_to_dma(dev, page) + offset; | 412 | return addr; |
| 372 | } | 413 | } |
| 373 | 414 | ||
| 374 | /** | 415 | /** |
| @@ -388,7 +429,8 @@ static inline dma_addr_t dma_map_page(struct device *dev, struct page *page, | |||
| 388 | static inline void dma_unmap_single(struct device *dev, dma_addr_t handle, | 429 | static inline void dma_unmap_single(struct device *dev, dma_addr_t handle, |
| 389 | size_t size, enum dma_data_direction dir) | 430 | size_t size, enum dma_data_direction dir) |
| 390 | { | 431 | { |
| 391 | __dma_single_dev_to_cpu(dma_to_virt(dev, handle), size, dir); | 432 | debug_dma_unmap_page(dev, handle, size, dir, true); |
| 433 | __dma_unmap_single(dev, handle, size, dir); | ||
| 392 | } | 434 | } |
| 393 | 435 | ||
| 394 | /** | 436 | /** |
| @@ -408,10 +450,9 @@ static inline void dma_unmap_single(struct device *dev, dma_addr_t handle, | |||
| 408 | static inline void dma_unmap_page(struct device *dev, dma_addr_t handle, | 450 | static inline void dma_unmap_page(struct device *dev, dma_addr_t handle, |
| 409 | size_t size, enum dma_data_direction dir) | 451 | size_t size, enum dma_data_direction dir) |
| 410 | { | 452 | { |
| 411 | __dma_page_dev_to_cpu(dma_to_page(dev, handle), handle & ~PAGE_MASK, | 453 | debug_dma_unmap_page(dev, handle, size, dir, false); |
| 412 | size, dir); | 454 | __dma_unmap_page(dev, handle, size, dir); |
| 413 | } | 455 | } |
| 414 | #endif /* CONFIG_DMABOUNCE */ | ||
| 415 | 456 | ||
| 416 | /** | 457 | /** |
| 417 | * dma_sync_single_range_for_cpu | 458 | * dma_sync_single_range_for_cpu |
| @@ -437,6 +478,8 @@ static inline void dma_sync_single_range_for_cpu(struct device *dev, | |||
| 437 | { | 478 | { |
| 438 | BUG_ON(!valid_dma_direction(dir)); | 479 | BUG_ON(!valid_dma_direction(dir)); |
| 439 | 480 | ||
| 481 | debug_dma_sync_single_for_cpu(dev, handle + offset, size, dir); | ||
| 482 | |||
| 440 | if (!dmabounce_sync_for_cpu(dev, handle, offset, size, dir)) | 483 | if (!dmabounce_sync_for_cpu(dev, handle, offset, size, dir)) |
| 441 | return; | 484 | return; |
| 442 | 485 | ||
| @@ -449,6 +492,8 @@ static inline void dma_sync_single_range_for_device(struct device *dev, | |||
| 449 | { | 492 | { |
| 450 | BUG_ON(!valid_dma_direction(dir)); | 493 | BUG_ON(!valid_dma_direction(dir)); |
| 451 | 494 | ||
| 495 | debug_dma_sync_single_for_device(dev, handle + offset, size, dir); | ||
| 496 | |||
| 452 | if (!dmabounce_sync_for_device(dev, handle, offset, size, dir)) | 497 | if (!dmabounce_sync_for_device(dev, handle, offset, size, dir)) |
| 453 | return; | 498 | return; |
| 454 | 499 | ||
diff --git a/arch/arm/include/asm/domain.h b/arch/arm/include/asm/domain.h index cc7ef4080711..af18ceaacf5d 100644 --- a/arch/arm/include/asm/domain.h +++ b/arch/arm/include/asm/domain.h | |||
| @@ -45,13 +45,17 @@ | |||
| 45 | */ | 45 | */ |
| 46 | #define DOMAIN_NOACCESS 0 | 46 | #define DOMAIN_NOACCESS 0 |
| 47 | #define DOMAIN_CLIENT 1 | 47 | #define DOMAIN_CLIENT 1 |
| 48 | #ifdef CONFIG_CPU_USE_DOMAINS | ||
| 48 | #define DOMAIN_MANAGER 3 | 49 | #define DOMAIN_MANAGER 3 |
| 50 | #else | ||
| 51 | #define DOMAIN_MANAGER 1 | ||
| 52 | #endif | ||
| 49 | 53 | ||
| 50 | #define domain_val(dom,type) ((type) << (2*(dom))) | 54 | #define domain_val(dom,type) ((type) << (2*(dom))) |
| 51 | 55 | ||
| 52 | #ifndef __ASSEMBLY__ | 56 | #ifndef __ASSEMBLY__ |
| 53 | 57 | ||
| 54 | #ifdef CONFIG_MMU | 58 | #ifdef CONFIG_CPU_USE_DOMAINS |
| 55 | #define set_domain(x) \ | 59 | #define set_domain(x) \ |
| 56 | do { \ | 60 | do { \ |
| 57 | __asm__ __volatile__( \ | 61 | __asm__ __volatile__( \ |
| @@ -74,5 +78,28 @@ | |||
| 74 | #define modify_domain(dom,type) do { } while (0) | 78 | #define modify_domain(dom,type) do { } while (0) |
| 75 | #endif | 79 | #endif |
| 76 | 80 | ||
| 81 | /* | ||
| 82 | * Generate the T (user) versions of the LDR/STR and related | ||
| 83 | * instructions (inline assembly) | ||
| 84 | */ | ||
| 85 | #ifdef CONFIG_CPU_USE_DOMAINS | ||
| 86 | #define T(instr) #instr "t" | ||
| 87 | #else | ||
| 88 | #define T(instr) #instr | ||
| 77 | #endif | 89 | #endif |
| 78 | #endif /* !__ASSEMBLY__ */ | 90 | |
| 91 | #else /* __ASSEMBLY__ */ | ||
| 92 | |||
| 93 | /* | ||
| 94 | * Generate the T (user) versions of the LDR/STR and related | ||
| 95 | * instructions | ||
| 96 | */ | ||
| 97 | #ifdef CONFIG_CPU_USE_DOMAINS | ||
| 98 | #define T(instr) instr ## t | ||
| 99 | #else | ||
| 100 | #define T(instr) instr | ||
| 101 | #endif | ||
| 102 | |||
| 103 | #endif /* __ASSEMBLY__ */ | ||
| 104 | |||
| 105 | #endif /* !__ASM_PROC_DOMAIN_H */ | ||
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h index 8bb66bca2e3e..c3cd8755e648 100644 --- a/arch/arm/include/asm/elf.h +++ b/arch/arm/include/asm/elf.h | |||
| @@ -99,6 +99,8 @@ struct elf32_hdr; | |||
| 99 | extern int elf_check_arch(const struct elf32_hdr *); | 99 | extern int elf_check_arch(const struct elf32_hdr *); |
| 100 | #define elf_check_arch elf_check_arch | 100 | #define elf_check_arch elf_check_arch |
| 101 | 101 | ||
| 102 | #define vmcore_elf64_check_arch(x) (0) | ||
| 103 | |||
| 102 | extern int arm_elf_read_implies_exec(const struct elf32_hdr *, int); | 104 | extern int arm_elf_read_implies_exec(const struct elf32_hdr *, int); |
| 103 | #define elf_read_implies_exec(ex,stk) arm_elf_read_implies_exec(&(ex), stk) | 105 | #define elf_read_implies_exec(ex,stk) arm_elf_read_implies_exec(&(ex), stk) |
| 104 | 106 | ||
diff --git a/arch/arm/include/asm/entry-macro-multi.S b/arch/arm/include/asm/entry-macro-multi.S new file mode 100644 index 000000000000..ec0bbf79c71f --- /dev/null +++ b/arch/arm/include/asm/entry-macro-multi.S | |||
| @@ -0,0 +1,44 @@ | |||
| 1 | /* | ||
| 2 | * Interrupt handling. Preserves r7, r8, r9 | ||
| 3 | */ | ||
| 4 | .macro arch_irq_handler_default | ||
| 5 | get_irqnr_preamble r5, lr | ||
| 6 | 1: get_irqnr_and_base r0, r6, r5, lr | ||
| 7 | movne r1, sp | ||
| 8 | @ | ||
| 9 | @ routine called with r0 = irq number, r1 = struct pt_regs * | ||
| 10 | @ | ||
| 11 | adrne lr, BSYM(1b) | ||
| 12 | bne asm_do_IRQ | ||
| 13 | |||
| 14 | #ifdef CONFIG_SMP | ||
| 15 | /* | ||
| 16 | * XXX | ||
| 17 | * | ||
| 18 | * this macro assumes that irqstat (r6) and base (r5) are | ||
| 19 | * preserved from get_irqnr_and_base above | ||
| 20 | */ | ||
| 21 | ALT_SMP(test_for_ipi r0, r6, r5, lr) | ||
| 22 | ALT_UP_B(9997f) | ||
| 23 | movne r1, sp | ||
| 24 | adrne lr, BSYM(1b) | ||
| 25 | bne do_IPI | ||
| 26 | |||
| 27 | #ifdef CONFIG_LOCAL_TIMERS | ||
| 28 | test_for_ltirq r0, r6, r5, lr | ||
| 29 | movne r0, sp | ||
| 30 | adrne lr, BSYM(1b) | ||
| 31 | bne do_local_timer | ||
| 32 | #endif | ||
| 33 | #endif | ||
| 34 | 9997: | ||
| 35 | .endm | ||
| 36 | |||
| 37 | .macro arch_irq_handler, symbol_name | ||
| 38 | .align 5 | ||
| 39 | .global \symbol_name | ||
| 40 | \symbol_name: | ||
| 41 | mov r4, lr | ||
| 42 | arch_irq_handler_default | ||
| 43 | mov pc, r4 | ||
| 44 | .endm | ||
diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h index 540a044153a5..b33fe7065b38 100644 --- a/arch/arm/include/asm/futex.h +++ b/arch/arm/include/asm/futex.h | |||
| @@ -13,12 +13,13 @@ | |||
| 13 | #include <linux/preempt.h> | 13 | #include <linux/preempt.h> |
| 14 | #include <linux/uaccess.h> | 14 | #include <linux/uaccess.h> |
| 15 | #include <asm/errno.h> | 15 | #include <asm/errno.h> |
| 16 | #include <asm/domain.h> | ||
| 16 | 17 | ||
| 17 | #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ | 18 | #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ |
| 18 | __asm__ __volatile__( \ | 19 | __asm__ __volatile__( \ |
| 19 | "1: ldrt %1, [%2]\n" \ | 20 | "1: " T(ldr) " %1, [%2]\n" \ |
| 20 | " " insn "\n" \ | 21 | " " insn "\n" \ |
| 21 | "2: strt %0, [%2]\n" \ | 22 | "2: " T(str) " %0, [%2]\n" \ |
| 22 | " mov %0, #0\n" \ | 23 | " mov %0, #0\n" \ |
| 23 | "3:\n" \ | 24 | "3:\n" \ |
| 24 | " .pushsection __ex_table,\"a\"\n" \ | 25 | " .pushsection __ex_table,\"a\"\n" \ |
| @@ -97,10 +98,10 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) | |||
| 97 | pagefault_disable(); /* implies preempt_disable() */ | 98 | pagefault_disable(); /* implies preempt_disable() */ |
| 98 | 99 | ||
| 99 | __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n" | 100 | __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n" |
| 100 | "1: ldrt %0, [%3]\n" | 101 | "1: " T(ldr) " %0, [%3]\n" |
| 101 | " teq %0, %1\n" | 102 | " teq %0, %1\n" |
| 102 | " it eq @ explicit IT needed for the 2b label\n" | 103 | " it eq @ explicit IT needed for the 2b label\n" |
| 103 | "2: streqt %2, [%3]\n" | 104 | "2: " T(streq) " %2, [%3]\n" |
| 104 | "3:\n" | 105 | "3:\n" |
| 105 | " .pushsection __ex_table,\"a\"\n" | 106 | " .pushsection __ex_table,\"a\"\n" |
| 106 | " .align 3\n" | 107 | " .align 3\n" |
diff --git a/arch/arm/include/asm/hardirq.h b/arch/arm/include/asm/hardirq.h index 6d7485aff955..89ad1805e579 100644 --- a/arch/arm/include/asm/hardirq.h +++ b/arch/arm/include/asm/hardirq.h | |||
| @@ -5,13 +5,31 @@ | |||
| 5 | #include <linux/threads.h> | 5 | #include <linux/threads.h> |
| 6 | #include <asm/irq.h> | 6 | #include <asm/irq.h> |
| 7 | 7 | ||
| 8 | #define NR_IPI 5 | ||
| 9 | |||
| 8 | typedef struct { | 10 | typedef struct { |
| 9 | unsigned int __softirq_pending; | 11 | unsigned int __softirq_pending; |
| 12 | #ifdef CONFIG_LOCAL_TIMERS | ||
| 10 | unsigned int local_timer_irqs; | 13 | unsigned int local_timer_irqs; |
| 14 | #endif | ||
| 15 | #ifdef CONFIG_SMP | ||
| 16 | unsigned int ipi_irqs[NR_IPI]; | ||
| 17 | #endif | ||
| 11 | } ____cacheline_aligned irq_cpustat_t; | 18 | } ____cacheline_aligned irq_cpustat_t; |
| 12 | 19 | ||
| 13 | #include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */ | 20 | #include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */ |
| 14 | 21 | ||
| 22 | #define __inc_irq_stat(cpu, member) __IRQ_STAT(cpu, member)++ | ||
| 23 | #define __get_irq_stat(cpu, member) __IRQ_STAT(cpu, member) | ||
| 24 | |||
| 25 | #ifdef CONFIG_SMP | ||
| 26 | u64 smp_irq_stat_cpu(unsigned int cpu); | ||
| 27 | #else | ||
| 28 | #define smp_irq_stat_cpu(cpu) 0 | ||
| 29 | #endif | ||
| 30 | |||
| 31 | #define arch_irq_stat_cpu smp_irq_stat_cpu | ||
| 32 | |||
| 15 | #if NR_IRQS > 512 | 33 | #if NR_IRQS > 512 |
| 16 | #define HARDIRQ_BITS 10 | 34 | #define HARDIRQ_BITS 10 |
| 17 | #elif NR_IRQS > 256 | 35 | #elif NR_IRQS > 256 |
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index cc42d5fdee17..5aeec1e1735c 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h | |||
| @@ -59,7 +59,17 @@ | |||
| 59 | #define L2X0_CACHE_ID_PART_MASK (0xf << 6) | 59 | #define L2X0_CACHE_ID_PART_MASK (0xf << 6) |
| 60 | #define L2X0_CACHE_ID_PART_L210 (1 << 6) | 60 | #define L2X0_CACHE_ID_PART_L210 (1 << 6) |
| 61 | #define L2X0_CACHE_ID_PART_L310 (3 << 6) | 61 | #define L2X0_CACHE_ID_PART_L310 (3 << 6) |
| 62 | #define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x3 << 17) | 62 | |
| 63 | #define L2X0_AUX_CTRL_MASK 0xc0000fff | ||
| 64 | #define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16 | ||
| 65 | #define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17 | ||
| 66 | #define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x3 << 17) | ||
| 67 | #define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT 22 | ||
| 68 | #define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT 26 | ||
| 69 | #define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT 27 | ||
| 70 | #define L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT 28 | ||
| 71 | #define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT 29 | ||
| 72 | #define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT 30 | ||
| 63 | 73 | ||
| 64 | #ifndef __ASSEMBLY__ | 74 | #ifndef __ASSEMBLY__ |
| 65 | extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask); | 75 | extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask); |
diff --git a/arch/arm/include/asm/hardware/entry-macro-gic.S b/arch/arm/include/asm/hardware/entry-macro-gic.S new file mode 100644 index 000000000000..c115b82fe80a --- /dev/null +++ b/arch/arm/include/asm/hardware/entry-macro-gic.S | |||
| @@ -0,0 +1,75 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/include/asm/hardware/entry-macro-gic.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper macros for GIC | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <asm/hardware/gic.h> | ||
| 12 | |||
| 13 | #ifndef HAVE_GET_IRQNR_PREAMBLE | ||
| 14 | .macro get_irqnr_preamble, base, tmp | ||
| 15 | ldr \base, =gic_cpu_base_addr | ||
| 16 | ldr \base, [\base] | ||
| 17 | .endm | ||
| 18 | #endif | ||
| 19 | |||
| 20 | /* | ||
| 21 | * The interrupt numbering scheme is defined in the | ||
| 22 | * interrupt controller spec. To wit: | ||
| 23 | * | ||
| 24 | * Interrupts 0-15 are IPI | ||
| 25 | * 16-28 are reserved | ||
| 26 | * 29-31 are local. We allow 30 to be used for the watchdog. | ||
| 27 | * 32-1020 are global | ||
| 28 | * 1021-1022 are reserved | ||
| 29 | * 1023 is "spurious" (no interrupt) | ||
| 30 | * | ||
| 31 | * For now, we ignore all local interrupts so only return an interrupt if it's | ||
| 32 | * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs. | ||
| 33 | * | ||
| 34 | * A simple read from the controller will tell us the number of the highest | ||
| 35 | * priority enabled interrupt. We then just need to check whether it is in the | ||
| 36 | * valid range for an IRQ (30-1020 inclusive). | ||
| 37 | */ | ||
| 38 | |||
| 39 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 40 | |||
| 41 | ldr \irqstat, [\base, #GIC_CPU_INTACK] | ||
| 42 | /* bits 12-10 = src CPU, 9-0 = int # */ | ||
| 43 | |||
| 44 | ldr \tmp, =1021 | ||
| 45 | bic \irqnr, \irqstat, #0x1c00 | ||
| 46 | cmp \irqnr, #29 | ||
| 47 | cmpcc \irqnr, \irqnr | ||
| 48 | cmpne \irqnr, \tmp | ||
| 49 | cmpcs \irqnr, \irqnr | ||
| 50 | .endm | ||
| 51 | |||
| 52 | /* We assume that irqstat (the raw value of the IRQ acknowledge | ||
| 53 | * register) is preserved from the macro above. | ||
| 54 | * If there is an IPI, we immediately signal end of interrupt on the | ||
| 55 | * controller, since this requires the original irqstat value which | ||
| 56 | * we won't easily be able to recreate later. | ||
| 57 | */ | ||
| 58 | |||
| 59 | .macro test_for_ipi, irqnr, irqstat, base, tmp | ||
| 60 | bic \irqnr, \irqstat, #0x1c00 | ||
| 61 | cmp \irqnr, #16 | ||
| 62 | strcc \irqstat, [\base, #GIC_CPU_EOI] | ||
| 63 | cmpcs \irqnr, \irqnr | ||
| 64 | .endm | ||
| 65 | |||
| 66 | /* As above, this assumes that irqstat and base are preserved.. */ | ||
| 67 | |||
| 68 | .macro test_for_ltirq, irqnr, irqstat, base, tmp | ||
| 69 | bic \irqnr, \irqstat, #0x1c00 | ||
| 70 | mov \tmp, #0 | ||
| 71 | cmp \irqnr, #29 | ||
| 72 | moveq \tmp, #1 | ||
| 73 | streq \irqstat, [\base, #GIC_CPU_EOI] | ||
| 74 | cmp \tmp, #0 | ||
| 75 | .endm | ||
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h index 7f34333bb545..84557d321001 100644 --- a/arch/arm/include/asm/hardware/gic.h +++ b/arch/arm/include/asm/hardware/gic.h | |||
| @@ -33,10 +33,13 @@ | |||
| 33 | #define GIC_DIST_SOFTINT 0xf00 | 33 | #define GIC_DIST_SOFTINT 0xf00 |
| 34 | 34 | ||
| 35 | #ifndef __ASSEMBLY__ | 35 | #ifndef __ASSEMBLY__ |
| 36 | void gic_dist_init(unsigned int gic_nr, void __iomem *base, unsigned int irq_start); | 36 | extern void __iomem *gic_cpu_base_addr; |
| 37 | void gic_cpu_init(unsigned int gic_nr, void __iomem *base); | 37 | |
| 38 | void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *); | ||
| 39 | void gic_secondary_init(unsigned int); | ||
| 38 | void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); | 40 | void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); |
| 39 | void gic_raise_softirq(const struct cpumask *mask, unsigned int irq); | 41 | void gic_raise_softirq(const struct cpumask *mask, unsigned int irq); |
| 42 | void gic_enable_ppi(unsigned int); | ||
| 40 | #endif | 43 | #endif |
| 41 | 44 | ||
| 42 | #endif | 45 | #endif |
diff --git a/arch/arm/plat-versatile/include/plat/timer-sp.h b/arch/arm/include/asm/hardware/timer-sp.h index 21e75e30d497..21e75e30d497 100644 --- a/arch/arm/plat-versatile/include/plat/timer-sp.h +++ b/arch/arm/include/asm/hardware/timer-sp.h | |||
diff --git a/arch/arm/include/asm/hw_breakpoint.h b/arch/arm/include/asm/hw_breakpoint.h index 4d8ae9d67abe..f389b2704d82 100644 --- a/arch/arm/include/asm/hw_breakpoint.h +++ b/arch/arm/include/asm/hw_breakpoint.h | |||
| @@ -20,8 +20,8 @@ struct arch_hw_breakpoint_ctrl { | |||
| 20 | struct arch_hw_breakpoint { | 20 | struct arch_hw_breakpoint { |
| 21 | u32 address; | 21 | u32 address; |
| 22 | u32 trigger; | 22 | u32 trigger; |
| 23 | struct perf_event *suspended_wp; | 23 | struct arch_hw_breakpoint_ctrl step_ctrl; |
| 24 | struct arch_hw_breakpoint_ctrl ctrl; | 24 | struct arch_hw_breakpoint_ctrl ctrl; |
| 25 | }; | 25 | }; |
| 26 | 26 | ||
| 27 | static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl) | 27 | static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl) |
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 815efa2d4e07..20e0f7c9e03e 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h | |||
| @@ -241,18 +241,15 @@ extern void _memset_io(volatile void __iomem *, int, size_t); | |||
| 241 | * | 241 | * |
| 242 | */ | 242 | */ |
| 243 | #ifndef __arch_ioremap | 243 | #ifndef __arch_ioremap |
| 244 | #define ioremap(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE) | 244 | #define __arch_ioremap __arm_ioremap |
| 245 | #define ioremap_nocache(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE) | 245 | #define __arch_iounmap __iounmap |
| 246 | #define ioremap_cached(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE_CACHED) | 246 | #endif |
| 247 | #define ioremap_wc(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE_WC) | 247 | |
| 248 | #define iounmap(cookie) __iounmap(cookie) | ||
| 249 | #else | ||
| 250 | #define ioremap(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE) | 248 | #define ioremap(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE) |
| 251 | #define ioremap_nocache(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE) | 249 | #define ioremap_nocache(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE) |
| 252 | #define ioremap_cached(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE_CACHED) | 250 | #define ioremap_cached(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE_CACHED) |
| 253 | #define ioremap_wc(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE_WC) | 251 | #define ioremap_wc(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE_WC) |
| 254 | #define iounmap(cookie) __arch_iounmap(cookie) | 252 | #define iounmap __arch_iounmap |
| 255 | #endif | ||
| 256 | 253 | ||
| 257 | /* | 254 | /* |
| 258 | * io{read,write}{8,16,32} macros | 255 | * io{read,write}{8,16,32} macros |
diff --git a/arch/arm/include/asm/kexec.h b/arch/arm/include/asm/kexec.h index 8ec9ef5c3c7b..c0094d8edae4 100644 --- a/arch/arm/include/asm/kexec.h +++ b/arch/arm/include/asm/kexec.h | |||
| @@ -33,10 +33,20 @@ static inline void crash_setup_regs(struct pt_regs *newregs, | |||
| 33 | if (oldregs) { | 33 | if (oldregs) { |
| 34 | memcpy(newregs, oldregs, sizeof(*newregs)); | 34 | memcpy(newregs, oldregs, sizeof(*newregs)); |
| 35 | } else { | 35 | } else { |
| 36 | __asm__ __volatile__ ("stmia %0, {r0 - r15}" | 36 | __asm__ __volatile__ ( |
| 37 | : : "r" (&newregs->ARM_r0)); | 37 | "stmia %[regs_base], {r0-r12}\n\t" |
| 38 | __asm__ __volatile__ ("mrs %0, cpsr" | 38 | "mov %[_ARM_sp], sp\n\t" |
| 39 | : "=r" (newregs->ARM_cpsr)); | 39 | "str lr, %[_ARM_lr]\n\t" |
| 40 | "adr %[_ARM_pc], 1f\n\t" | ||
| 41 | "mrs %[_ARM_cpsr], cpsr\n\t" | ||
| 42 | "1:" | ||
| 43 | : [_ARM_pc] "=r" (newregs->ARM_pc), | ||
| 44 | [_ARM_cpsr] "=r" (newregs->ARM_cpsr), | ||
| 45 | [_ARM_sp] "=r" (newregs->ARM_sp), | ||
| 46 | [_ARM_lr] "=o" (newregs->ARM_lr) | ||
| 47 | : [regs_base] "r" (&newregs->ARM_r0) | ||
| 48 | : "memory" | ||
| 49 | ); | ||
| 40 | } | 50 | } |
| 41 | } | 51 | } |
| 42 | 52 | ||
diff --git a/arch/arm/include/asm/localtimer.h b/arch/arm/include/asm/localtimer.h index 50c7e7cfd670..6bc63ab498ce 100644 --- a/arch/arm/include/asm/localtimer.h +++ b/arch/arm/include/asm/localtimer.h | |||
| @@ -30,7 +30,6 @@ asmlinkage void do_local_timer(struct pt_regs *); | |||
| 30 | #include "smp_twd.h" | 30 | #include "smp_twd.h" |
| 31 | 31 | ||
| 32 | #define local_timer_ack() twd_timer_ack() | 32 | #define local_timer_ack() twd_timer_ack() |
| 33 | #define local_timer_stop() twd_timer_stop() | ||
| 34 | 33 | ||
| 35 | #else | 34 | #else |
| 36 | 35 | ||
| @@ -40,11 +39,6 @@ asmlinkage void do_local_timer(struct pt_regs *); | |||
| 40 | */ | 39 | */ |
| 41 | int local_timer_ack(void); | 40 | int local_timer_ack(void); |
| 42 | 41 | ||
| 43 | /* | ||
| 44 | * Stop a local timer interrupt. | ||
| 45 | */ | ||
| 46 | void local_timer_stop(void); | ||
| 47 | |||
| 48 | #endif | 42 | #endif |
| 49 | 43 | ||
| 50 | /* | 44 | /* |
| @@ -52,12 +46,6 @@ void local_timer_stop(void); | |||
| 52 | */ | 46 | */ |
| 53 | void local_timer_setup(struct clock_event_device *); | 47 | void local_timer_setup(struct clock_event_device *); |
| 54 | 48 | ||
| 55 | #else | ||
| 56 | |||
| 57 | static inline void local_timer_stop(void) | ||
| 58 | { | ||
| 59 | } | ||
| 60 | |||
| 61 | #endif | 49 | #endif |
| 62 | 50 | ||
| 63 | #endif | 51 | #endif |
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h index d97a964207fa..3a0893a76a3b 100644 --- a/arch/arm/include/asm/mach/arch.h +++ b/arch/arm/include/asm/mach/arch.h | |||
| @@ -37,12 +37,21 @@ struct machine_desc { | |||
| 37 | struct meminfo *); | 37 | struct meminfo *); |
| 38 | void (*reserve)(void);/* reserve mem blocks */ | 38 | void (*reserve)(void);/* reserve mem blocks */ |
| 39 | void (*map_io)(void);/* IO mapping function */ | 39 | void (*map_io)(void);/* IO mapping function */ |
| 40 | void (*init_early)(void); | ||
| 40 | void (*init_irq)(void); | 41 | void (*init_irq)(void); |
| 41 | struct sys_timer *timer; /* system tick timer */ | 42 | struct sys_timer *timer; /* system tick timer */ |
| 42 | void (*init_machine)(void); | 43 | void (*init_machine)(void); |
| 44 | #ifdef CONFIG_MULTI_IRQ_HANDLER | ||
| 45 | void (*handle_irq)(struct pt_regs *); | ||
| 46 | #endif | ||
| 43 | }; | 47 | }; |
| 44 | 48 | ||
| 45 | /* | 49 | /* |
| 50 | * Current machine - only accessible during boot. | ||
| 51 | */ | ||
| 52 | extern struct machine_desc *machine_desc; | ||
| 53 | |||
| 54 | /* | ||
| 46 | * Set of macros to define architecture features. This is built into | 55 | * Set of macros to define architecture features. This is built into |
| 47 | * a table by the linker. | 56 | * a table by the linker. |
| 48 | */ | 57 | */ |
diff --git a/arch/arm/include/asm/mach/irq.h b/arch/arm/include/asm/mach/irq.h index ce3eee9fe26c..22ac140edd9e 100644 --- a/arch/arm/include/asm/mach/irq.h +++ b/arch/arm/include/asm/mach/irq.h | |||
| @@ -17,10 +17,12 @@ struct seq_file; | |||
| 17 | /* | 17 | /* |
| 18 | * This is internal. Do not use it. | 18 | * This is internal. Do not use it. |
| 19 | */ | 19 | */ |
| 20 | extern unsigned int arch_nr_irqs; | ||
| 21 | extern void (*init_arch_irq)(void); | ||
| 22 | extern void init_FIQ(void); | 20 | extern void init_FIQ(void); |
| 23 | extern int show_fiq_list(struct seq_file *, void *); | 21 | extern int show_fiq_list(struct seq_file *, int); |
| 22 | |||
| 23 | #ifdef CONFIG_MULTI_IRQ_HANDLER | ||
| 24 | extern void (*handle_arch_irq)(struct pt_regs *); | ||
| 25 | #endif | ||
| 24 | 26 | ||
| 25 | /* | 27 | /* |
| 26 | * This is for easy migration, but should be changed in the source | 28 | * This is for easy migration, but should be changed in the source |
diff --git a/arch/arm/include/asm/mach/time.h b/arch/arm/include/asm/mach/time.h index 35d408f6dccf..883f6be5117a 100644 --- a/arch/arm/include/asm/mach/time.h +++ b/arch/arm/include/asm/mach/time.h | |||
| @@ -43,7 +43,6 @@ struct sys_timer { | |||
| 43 | #endif | 43 | #endif |
| 44 | }; | 44 | }; |
| 45 | 45 | ||
| 46 | extern struct sys_timer *system_timer; | ||
| 47 | extern void timer_tick(void); | 46 | extern void timer_tick(void); |
| 48 | 47 | ||
| 49 | #endif | 48 | #endif |
diff --git a/arch/arm/include/asm/module.h b/arch/arm/include/asm/module.h index cbb0bc295d2b..12c8e680cbff 100644 --- a/arch/arm/include/asm/module.h +++ b/arch/arm/include/asm/module.h | |||
| @@ -8,11 +8,6 @@ | |||
| 8 | struct unwind_table; | 8 | struct unwind_table; |
| 9 | 9 | ||
| 10 | #ifdef CONFIG_ARM_UNWIND | 10 | #ifdef CONFIG_ARM_UNWIND |
| 11 | struct arm_unwind_mapping { | ||
| 12 | Elf_Shdr *unw_sec; | ||
| 13 | Elf_Shdr *sec_text; | ||
| 14 | struct unwind_table *unwind; | ||
| 15 | }; | ||
| 16 | enum { | 11 | enum { |
| 17 | ARM_SEC_INIT, | 12 | ARM_SEC_INIT, |
| 18 | ARM_SEC_DEVINIT, | 13 | ARM_SEC_DEVINIT, |
| @@ -21,13 +16,13 @@ enum { | |||
| 21 | ARM_SEC_DEVEXIT, | 16 | ARM_SEC_DEVEXIT, |
| 22 | ARM_SEC_MAX, | 17 | ARM_SEC_MAX, |
| 23 | }; | 18 | }; |
| 19 | #endif | ||
| 20 | |||
| 24 | struct mod_arch_specific { | 21 | struct mod_arch_specific { |
| 25 | struct arm_unwind_mapping map[ARM_SEC_MAX]; | 22 | #ifdef CONFIG_ARM_UNWIND |
| 26 | }; | 23 | struct unwind_table *unwind[ARM_SEC_MAX]; |
| 27 | #else | ||
| 28 | struct mod_arch_specific { | ||
| 29 | }; | ||
| 30 | #endif | 24 | #endif |
| 25 | }; | ||
| 31 | 26 | ||
| 32 | /* | 27 | /* |
| 33 | * Include the ARM architecture version. | 28 | * Include the ARM architecture version. |
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h index a485ac3c8696..f51a69595f6e 100644 --- a/arch/arm/include/asm/page.h +++ b/arch/arm/include/asm/page.h | |||
| @@ -151,13 +151,15 @@ extern void __cpu_copy_user_highpage(struct page *to, struct page *from, | |||
| 151 | #define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) | 151 | #define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) |
| 152 | extern void copy_page(void *to, const void *from); | 152 | extern void copy_page(void *to, const void *from); |
| 153 | 153 | ||
| 154 | typedef unsigned long pteval_t; | ||
| 155 | |||
| 154 | #undef STRICT_MM_TYPECHECKS | 156 | #undef STRICT_MM_TYPECHECKS |
| 155 | 157 | ||
| 156 | #ifdef STRICT_MM_TYPECHECKS | 158 | #ifdef STRICT_MM_TYPECHECKS |
| 157 | /* | 159 | /* |
| 158 | * These are used to make use of C type-checking.. | 160 | * These are used to make use of C type-checking.. |
| 159 | */ | 161 | */ |
| 160 | typedef struct { unsigned long pte; } pte_t; | 162 | typedef struct { pteval_t pte; } pte_t; |
| 161 | typedef struct { unsigned long pmd; } pmd_t; | 163 | typedef struct { unsigned long pmd; } pmd_t; |
| 162 | typedef struct { unsigned long pgd[2]; } pgd_t; | 164 | typedef struct { unsigned long pgd[2]; } pgd_t; |
| 163 | typedef struct { unsigned long pgprot; } pgprot_t; | 165 | typedef struct { unsigned long pgprot; } pgprot_t; |
| @@ -175,7 +177,7 @@ typedef struct { unsigned long pgprot; } pgprot_t; | |||
| 175 | /* | 177 | /* |
| 176 | * .. while these make it easier on the compiler | 178 | * .. while these make it easier on the compiler |
| 177 | */ | 179 | */ |
| 178 | typedef unsigned long pte_t; | 180 | typedef pteval_t pte_t; |
| 179 | typedef unsigned long pmd_t; | 181 | typedef unsigned long pmd_t; |
| 180 | typedef unsigned long pgd_t[2]; | 182 | typedef unsigned long pgd_t[2]; |
| 181 | typedef unsigned long pgprot_t; | 183 | typedef unsigned long pgprot_t; |
diff --git a/arch/arm/include/asm/pgalloc.h b/arch/arm/include/asm/pgalloc.h index b12cc98bbe04..9763be04f77e 100644 --- a/arch/arm/include/asm/pgalloc.h +++ b/arch/arm/include/asm/pgalloc.h | |||
| @@ -30,14 +30,16 @@ | |||
| 30 | #define pmd_free(mm, pmd) do { } while (0) | 30 | #define pmd_free(mm, pmd) do { } while (0) |
| 31 | #define pgd_populate(mm,pmd,pte) BUG() | 31 | #define pgd_populate(mm,pmd,pte) BUG() |
| 32 | 32 | ||
| 33 | extern pgd_t *get_pgd_slow(struct mm_struct *mm); | 33 | extern pgd_t *pgd_alloc(struct mm_struct *mm); |
| 34 | extern void free_pgd_slow(struct mm_struct *mm, pgd_t *pgd); | 34 | extern void pgd_free(struct mm_struct *mm, pgd_t *pgd); |
| 35 | |||
| 36 | #define pgd_alloc(mm) get_pgd_slow(mm) | ||
| 37 | #define pgd_free(mm, pgd) free_pgd_slow(mm, pgd) | ||
| 38 | 35 | ||
| 39 | #define PGALLOC_GFP (GFP_KERNEL | __GFP_NOTRACK | __GFP_REPEAT | __GFP_ZERO) | 36 | #define PGALLOC_GFP (GFP_KERNEL | __GFP_NOTRACK | __GFP_REPEAT | __GFP_ZERO) |
| 40 | 37 | ||
| 38 | static inline void clean_pte_table(pte_t *pte) | ||
| 39 | { | ||
| 40 | clean_dcache_area(pte + PTE_HWTABLE_PTRS, PTE_HWTABLE_SIZE); | ||
| 41 | } | ||
| 42 | |||
| 41 | /* | 43 | /* |
| 42 | * Allocate one PTE table. | 44 | * Allocate one PTE table. |
| 43 | * | 45 | * |
| @@ -45,14 +47,14 @@ extern void free_pgd_slow(struct mm_struct *mm, pgd_t *pgd); | |||
| 45 | * into one table thus: | 47 | * into one table thus: |
| 46 | * | 48 | * |
| 47 | * +------------+ | 49 | * +------------+ |
| 48 | * | h/w pt 0 | | ||
| 49 | * +------------+ | ||
| 50 | * | h/w pt 1 | | ||
| 51 | * +------------+ | ||
| 52 | * | Linux pt 0 | | 50 | * | Linux pt 0 | |
| 53 | * +------------+ | 51 | * +------------+ |
| 54 | * | Linux pt 1 | | 52 | * | Linux pt 1 | |
| 55 | * +------------+ | 53 | * +------------+ |
| 54 | * | h/w pt 0 | | ||
| 55 | * +------------+ | ||
| 56 | * | h/w pt 1 | | ||
| 57 | * +------------+ | ||
| 56 | */ | 58 | */ |
| 57 | static inline pte_t * | 59 | static inline pte_t * |
| 58 | pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr) | 60 | pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr) |
| @@ -60,10 +62,8 @@ pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr) | |||
| 60 | pte_t *pte; | 62 | pte_t *pte; |
| 61 | 63 | ||
| 62 | pte = (pte_t *)__get_free_page(PGALLOC_GFP); | 64 | pte = (pte_t *)__get_free_page(PGALLOC_GFP); |
| 63 | if (pte) { | 65 | if (pte) |
| 64 | clean_dcache_area(pte, sizeof(pte_t) * PTRS_PER_PTE); | 66 | clean_pte_table(pte); |
| 65 | pte += PTRS_PER_PTE; | ||
| 66 | } | ||
| 67 | 67 | ||
| 68 | return pte; | 68 | return pte; |
| 69 | } | 69 | } |
| @@ -79,10 +79,8 @@ pte_alloc_one(struct mm_struct *mm, unsigned long addr) | |||
| 79 | pte = alloc_pages(PGALLOC_GFP, 0); | 79 | pte = alloc_pages(PGALLOC_GFP, 0); |
| 80 | #endif | 80 | #endif |
| 81 | if (pte) { | 81 | if (pte) { |
| 82 | if (!PageHighMem(pte)) { | 82 | if (!PageHighMem(pte)) |
| 83 | void *page = page_address(pte); | 83 | clean_pte_table(page_address(pte)); |
| 84 | clean_dcache_area(page, sizeof(pte_t) * PTRS_PER_PTE); | ||
| 85 | } | ||
| 86 | pgtable_page_ctor(pte); | 84 | pgtable_page_ctor(pte); |
| 87 | } | 85 | } |
| 88 | 86 | ||
| @@ -94,10 +92,8 @@ pte_alloc_one(struct mm_struct *mm, unsigned long addr) | |||
| 94 | */ | 92 | */ |
| 95 | static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) | 93 | static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) |
| 96 | { | 94 | { |
| 97 | if (pte) { | 95 | if (pte) |
| 98 | pte -= PTRS_PER_PTE; | ||
| 99 | free_page((unsigned long)pte); | 96 | free_page((unsigned long)pte); |
| 100 | } | ||
| 101 | } | 97 | } |
| 102 | 98 | ||
| 103 | static inline void pte_free(struct mm_struct *mm, pgtable_t pte) | 99 | static inline void pte_free(struct mm_struct *mm, pgtable_t pte) |
| @@ -106,8 +102,10 @@ static inline void pte_free(struct mm_struct *mm, pgtable_t pte) | |||
| 106 | __free_page(pte); | 102 | __free_page(pte); |
| 107 | } | 103 | } |
| 108 | 104 | ||
| 109 | static inline void __pmd_populate(pmd_t *pmdp, unsigned long pmdval) | 105 | static inline void __pmd_populate(pmd_t *pmdp, phys_addr_t pte, |
| 106 | unsigned long prot) | ||
| 110 | { | 107 | { |
| 108 | unsigned long pmdval = (pte + PTE_HWTABLE_OFF) | prot; | ||
| 111 | pmdp[0] = __pmd(pmdval); | 109 | pmdp[0] = __pmd(pmdval); |
| 112 | pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t)); | 110 | pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t)); |
| 113 | flush_pmd_entry(pmdp); | 111 | flush_pmd_entry(pmdp); |
| @@ -122,20 +120,16 @@ static inline void __pmd_populate(pmd_t *pmdp, unsigned long pmdval) | |||
| 122 | static inline void | 120 | static inline void |
| 123 | pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep) | 121 | pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep) |
| 124 | { | 122 | { |
| 125 | unsigned long pte_ptr = (unsigned long)ptep; | ||
| 126 | |||
| 127 | /* | 123 | /* |
| 128 | * The pmd must be loaded with the physical | 124 | * The pmd must be loaded with the physical address of the PTE table |
| 129 | * address of the PTE table | ||
| 130 | */ | 125 | */ |
| 131 | pte_ptr -= PTRS_PER_PTE * sizeof(void *); | 126 | __pmd_populate(pmdp, __pa(ptep), _PAGE_KERNEL_TABLE); |
| 132 | __pmd_populate(pmdp, __pa(pte_ptr) | _PAGE_KERNEL_TABLE); | ||
| 133 | } | 127 | } |
| 134 | 128 | ||
| 135 | static inline void | 129 | static inline void |
| 136 | pmd_populate(struct mm_struct *mm, pmd_t *pmdp, pgtable_t ptep) | 130 | pmd_populate(struct mm_struct *mm, pmd_t *pmdp, pgtable_t ptep) |
| 137 | { | 131 | { |
| 138 | __pmd_populate(pmdp, page_to_pfn(ptep) << PAGE_SHIFT | _PAGE_USER_TABLE); | 132 | __pmd_populate(pmdp, page_to_phys(ptep), _PAGE_USER_TABLE); |
| 139 | } | 133 | } |
| 140 | #define pmd_pgtable(pmd) pmd_page(pmd) | 134 | #define pmd_pgtable(pmd) pmd_page(pmd) |
| 141 | 135 | ||
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h index 53d1d5deb111..ebcb6432f45f 100644 --- a/arch/arm/include/asm/pgtable.h +++ b/arch/arm/include/asm/pgtable.h | |||
| @@ -10,6 +10,7 @@ | |||
| 10 | #ifndef _ASMARM_PGTABLE_H | 10 | #ifndef _ASMARM_PGTABLE_H |
| 11 | #define _ASMARM_PGTABLE_H | 11 | #define _ASMARM_PGTABLE_H |
| 12 | 12 | ||
| 13 | #include <linux/const.h> | ||
| 13 | #include <asm-generic/4level-fixup.h> | 14 | #include <asm-generic/4level-fixup.h> |
| 14 | #include <asm/proc-fns.h> | 15 | #include <asm/proc-fns.h> |
| 15 | 16 | ||
| @@ -54,7 +55,7 @@ | |||
| 54 | * Therefore, we tweak the implementation slightly - we tell Linux that we | 55 | * Therefore, we tweak the implementation slightly - we tell Linux that we |
| 55 | * have 2048 entries in the first level, each of which is 8 bytes (iow, two | 56 | * have 2048 entries in the first level, each of which is 8 bytes (iow, two |
| 56 | * hardware pointers to the second level.) The second level contains two | 57 | * hardware pointers to the second level.) The second level contains two |
| 57 | * hardware PTE tables arranged contiguously, followed by Linux versions | 58 | * hardware PTE tables arranged contiguously, preceded by Linux versions |
| 58 | * which contain the state information Linux needs. We, therefore, end up | 59 | * which contain the state information Linux needs. We, therefore, end up |
| 59 | * with 512 entries in the "PTE" level. | 60 | * with 512 entries in the "PTE" level. |
| 60 | * | 61 | * |
| @@ -62,15 +63,15 @@ | |||
| 62 | * | 63 | * |
| 63 | * pgd pte | 64 | * pgd pte |
| 64 | * | | | 65 | * | | |
| 65 | * +--------+ +0 | 66 | * +--------+ |
| 66 | * | |-----> +------------+ +0 | 67 | * | | +------------+ +0 |
| 68 | * +- - - - + | Linux pt 0 | | ||
| 69 | * | | +------------+ +1024 | ||
| 70 | * +--------+ +0 | Linux pt 1 | | ||
| 71 | * | |-----> +------------+ +2048 | ||
| 67 | * +- - - - + +4 | h/w pt 0 | | 72 | * +- - - - + +4 | h/w pt 0 | |
| 68 | * | |-----> +------------+ +1024 | 73 | * | |-----> +------------+ +3072 |
| 69 | * +--------+ +8 | h/w pt 1 | | 74 | * +--------+ +8 | h/w pt 1 | |
| 70 | * | | +------------+ +2048 | ||
| 71 | * +- - - - + | Linux pt 0 | | ||
| 72 | * | | +------------+ +3072 | ||
| 73 | * +--------+ | Linux pt 1 | | ||
| 74 | * | | +------------+ +4096 | 75 | * | | +------------+ +4096 |
| 75 | * | 76 | * |
| 76 | * See L_PTE_xxx below for definitions of bits in the "Linux pt", and | 77 | * See L_PTE_xxx below for definitions of bits in the "Linux pt", and |
| @@ -102,6 +103,10 @@ | |||
| 102 | #define PTRS_PER_PMD 1 | 103 | #define PTRS_PER_PMD 1 |
| 103 | #define PTRS_PER_PGD 2048 | 104 | #define PTRS_PER_PGD 2048 |
| 104 | 105 | ||
| 106 | #define PTE_HWTABLE_PTRS (PTRS_PER_PTE) | ||
| 107 | #define PTE_HWTABLE_OFF (PTE_HWTABLE_PTRS * sizeof(pte_t)) | ||
| 108 | #define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u32)) | ||
| 109 | |||
| 105 | /* | 110 | /* |
| 106 | * PMD_SHIFT determines the size of the area a second-level page table can map | 111 | * PMD_SHIFT determines the size of the area a second-level page table can map |
| 107 | * PGDIR_SHIFT determines what a third-level page table entry can map | 112 | * PGDIR_SHIFT determines what a third-level page table entry can map |
| @@ -112,13 +117,13 @@ | |||
| 112 | #define LIBRARY_TEXT_START 0x0c000000 | 117 | #define LIBRARY_TEXT_START 0x0c000000 |
| 113 | 118 | ||
| 114 | #ifndef __ASSEMBLY__ | 119 | #ifndef __ASSEMBLY__ |
| 115 | extern void __pte_error(const char *file, int line, unsigned long val); | 120 | extern void __pte_error(const char *file, int line, pte_t); |
| 116 | extern void __pmd_error(const char *file, int line, unsigned long val); | 121 | extern void __pmd_error(const char *file, int line, pmd_t); |
| 117 | extern void __pgd_error(const char *file, int line, unsigned long val); | 122 | extern void __pgd_error(const char *file, int line, pgd_t); |
| 118 | 123 | ||
| 119 | #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte)) | 124 | #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte) |
| 120 | #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd)) | 125 | #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd) |
| 121 | #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd)) | 126 | #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd) |
| 122 | #endif /* !__ASSEMBLY__ */ | 127 | #endif /* !__ASSEMBLY__ */ |
| 123 | 128 | ||
| 124 | #define PMD_SIZE (1UL << PMD_SHIFT) | 129 | #define PMD_SIZE (1UL << PMD_SHIFT) |
| @@ -133,8 +138,7 @@ extern void __pgd_error(const char *file, int line, unsigned long val); | |||
| 133 | */ | 138 | */ |
| 134 | #define FIRST_USER_ADDRESS PAGE_SIZE | 139 | #define FIRST_USER_ADDRESS PAGE_SIZE |
| 135 | 140 | ||
| 136 | #define FIRST_USER_PGD_NR 1 | 141 | #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) |
| 137 | #define USER_PTRS_PER_PGD ((TASK_SIZE/PGDIR_SIZE) - FIRST_USER_PGD_NR) | ||
| 138 | 142 | ||
| 139 | /* | 143 | /* |
| 140 | * section address mask and size definitions. | 144 | * section address mask and size definitions. |
| @@ -161,30 +165,30 @@ extern void __pgd_error(const char *file, int line, unsigned long val); | |||
| 161 | * The PTE table pointer refers to the hardware entries; the "Linux" | 165 | * The PTE table pointer refers to the hardware entries; the "Linux" |
| 162 | * entries are stored 1024 bytes below. | 166 | * entries are stored 1024 bytes below. |
| 163 | */ | 167 | */ |
| 164 | #define L_PTE_PRESENT (1 << 0) | 168 | #define L_PTE_PRESENT (_AT(pteval_t, 1) << 0) |
| 165 | #define L_PTE_YOUNG (1 << 1) | 169 | #define L_PTE_YOUNG (_AT(pteval_t, 1) << 1) |
| 166 | #define L_PTE_FILE (1 << 2) /* only when !PRESENT */ | 170 | #define L_PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !PRESENT */ |
| 167 | #define L_PTE_DIRTY (1 << 6) | 171 | #define L_PTE_DIRTY (_AT(pteval_t, 1) << 6) |
| 168 | #define L_PTE_WRITE (1 << 7) | 172 | #define L_PTE_RDONLY (_AT(pteval_t, 1) << 7) |
| 169 | #define L_PTE_USER (1 << 8) | 173 | #define L_PTE_USER (_AT(pteval_t, 1) << 8) |
| 170 | #define L_PTE_EXEC (1 << 9) | 174 | #define L_PTE_XN (_AT(pteval_t, 1) << 9) |
| 171 | #define L_PTE_SHARED (1 << 10) /* shared(v6), coherent(xsc3) */ | 175 | #define L_PTE_SHARED (_AT(pteval_t, 1) << 10) /* shared(v6), coherent(xsc3) */ |
| 172 | 176 | ||
| 173 | /* | 177 | /* |
| 174 | * These are the memory types, defined to be compatible with | 178 | * These are the memory types, defined to be compatible with |
| 175 | * pre-ARMv6 CPUs cacheable and bufferable bits: XXCB | 179 | * pre-ARMv6 CPUs cacheable and bufferable bits: XXCB |
| 176 | */ | 180 | */ |
| 177 | #define L_PTE_MT_UNCACHED (0x00 << 2) /* 0000 */ | 181 | #define L_PTE_MT_UNCACHED (_AT(pteval_t, 0x00) << 2) /* 0000 */ |
| 178 | #define L_PTE_MT_BUFFERABLE (0x01 << 2) /* 0001 */ | 182 | #define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 0x01) << 2) /* 0001 */ |
| 179 | #define L_PTE_MT_WRITETHROUGH (0x02 << 2) /* 0010 */ | 183 | #define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 0x02) << 2) /* 0010 */ |
| 180 | #define L_PTE_MT_WRITEBACK (0x03 << 2) /* 0011 */ | 184 | #define L_PTE_MT_WRITEBACK (_AT(pteval_t, 0x03) << 2) /* 0011 */ |
| 181 | #define L_PTE_MT_MINICACHE (0x06 << 2) /* 0110 (sa1100, xscale) */ | 185 | #define L_PTE_MT_MINICACHE (_AT(pteval_t, 0x06) << 2) /* 0110 (sa1100, xscale) */ |
| 182 | #define L_PTE_MT_WRITEALLOC (0x07 << 2) /* 0111 */ | 186 | #define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 0x07) << 2) /* 0111 */ |
| 183 | #define L_PTE_MT_DEV_SHARED (0x04 << 2) /* 0100 */ | 187 | #define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */ |
| 184 | #define L_PTE_MT_DEV_NONSHARED (0x0c << 2) /* 1100 */ | 188 | #define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */ |
| 185 | #define L_PTE_MT_DEV_WC (0x09 << 2) /* 1001 */ | 189 | #define L_PTE_MT_DEV_WC (_AT(pteval_t, 0x09) << 2) /* 1001 */ |
| 186 | #define L_PTE_MT_DEV_CACHED (0x0b << 2) /* 1011 */ | 190 | #define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 0x0b) << 2) /* 1011 */ |
| 187 | #define L_PTE_MT_MASK (0x0f << 2) | 191 | #define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2) |
| 188 | 192 | ||
| 189 | #ifndef __ASSEMBLY__ | 193 | #ifndef __ASSEMBLY__ |
| 190 | 194 | ||
| @@ -201,23 +205,44 @@ extern pgprot_t pgprot_kernel; | |||
| 201 | 205 | ||
| 202 | #define _MOD_PROT(p, b) __pgprot(pgprot_val(p) | (b)) | 206 | #define _MOD_PROT(p, b) __pgprot(pgprot_val(p) | (b)) |
| 203 | 207 | ||
| 204 | #define PAGE_NONE pgprot_user | 208 | #define PAGE_NONE _MOD_PROT(pgprot_user, L_PTE_XN | L_PTE_RDONLY) |
| 205 | #define PAGE_SHARED _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_WRITE) | 209 | #define PAGE_SHARED _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_XN) |
| 206 | #define PAGE_SHARED_EXEC _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_WRITE | L_PTE_EXEC) | 210 | #define PAGE_SHARED_EXEC _MOD_PROT(pgprot_user, L_PTE_USER) |
| 207 | #define PAGE_COPY _MOD_PROT(pgprot_user, L_PTE_USER) | 211 | #define PAGE_COPY _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY | L_PTE_XN) |
| 208 | #define PAGE_COPY_EXEC _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_EXEC) | 212 | #define PAGE_COPY_EXEC _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY) |
| 209 | #define PAGE_READONLY _MOD_PROT(pgprot_user, L_PTE_USER) | 213 | #define PAGE_READONLY _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY | L_PTE_XN) |
| 210 | #define PAGE_READONLY_EXEC _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_EXEC) | 214 | #define PAGE_READONLY_EXEC _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY) |
| 211 | #define PAGE_KERNEL pgprot_kernel | 215 | #define PAGE_KERNEL _MOD_PROT(pgprot_kernel, L_PTE_XN) |
| 212 | #define PAGE_KERNEL_EXEC _MOD_PROT(pgprot_kernel, L_PTE_EXEC) | 216 | #define PAGE_KERNEL_EXEC pgprot_kernel |
| 213 | 217 | ||
| 214 | #define __PAGE_NONE __pgprot(_L_PTE_DEFAULT) | 218 | #define __PAGE_NONE __pgprot(_L_PTE_DEFAULT | L_PTE_RDONLY | L_PTE_XN) |
| 215 | #define __PAGE_SHARED __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_WRITE) | 219 | #define __PAGE_SHARED __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_XN) |
| 216 | #define __PAGE_SHARED_EXEC __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_WRITE | L_PTE_EXEC) | 220 | #define __PAGE_SHARED_EXEC __pgprot(_L_PTE_DEFAULT | L_PTE_USER) |
| 217 | #define __PAGE_COPY __pgprot(_L_PTE_DEFAULT | L_PTE_USER) | 221 | #define __PAGE_COPY __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY | L_PTE_XN) |
| 218 | #define __PAGE_COPY_EXEC __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_EXEC) | 222 | #define __PAGE_COPY_EXEC __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY) |
| 219 | #define __PAGE_READONLY __pgprot(_L_PTE_DEFAULT | L_PTE_USER) | 223 | #define __PAGE_READONLY __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY | L_PTE_XN) |
| 220 | #define __PAGE_READONLY_EXEC __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_EXEC) | 224 | #define __PAGE_READONLY_EXEC __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY) |
| 225 | |||
| 226 | #define __pgprot_modify(prot,mask,bits) \ | ||
| 227 | __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) | ||
| 228 | |||
| 229 | #define pgprot_noncached(prot) \ | ||
| 230 | __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED) | ||
| 231 | |||
| 232 | #define pgprot_writecombine(prot) \ | ||
| 233 | __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE) | ||
| 234 | |||
| 235 | #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE | ||
| 236 | #define pgprot_dmacoherent(prot) \ | ||
| 237 | __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE | L_PTE_XN) | ||
| 238 | #define __HAVE_PHYS_MEM_ACCESS_PROT | ||
| 239 | struct file; | ||
| 240 | extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, | ||
| 241 | unsigned long size, pgprot_t vma_prot); | ||
| 242 | #else | ||
| 243 | #define pgprot_dmacoherent(prot) \ | ||
| 244 | __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED | L_PTE_XN) | ||
| 245 | #endif | ||
| 221 | 246 | ||
| 222 | #endif /* __ASSEMBLY__ */ | 247 | #endif /* __ASSEMBLY__ */ |
| 223 | 248 | ||
| @@ -255,26 +280,84 @@ extern pgprot_t pgprot_kernel; | |||
| 255 | extern struct page *empty_zero_page; | 280 | extern struct page *empty_zero_page; |
| 256 | #define ZERO_PAGE(vaddr) (empty_zero_page) | 281 | #define ZERO_PAGE(vaddr) (empty_zero_page) |
| 257 | 282 | ||
| 258 | #define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) | ||
| 259 | #define pfn_pte(pfn,prot) (__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))) | ||
| 260 | 283 | ||
| 261 | #define pte_none(pte) (!pte_val(pte)) | 284 | extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; |
| 262 | #define pte_clear(mm,addr,ptep) set_pte_ext(ptep, __pte(0), 0) | 285 | |
| 263 | #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) | 286 | /* to find an entry in a page-table-directory */ |
| 264 | #define pte_offset_kernel(dir,addr) (pmd_page_vaddr(*(dir)) + __pte_index(addr)) | 287 | #define pgd_index(addr) ((addr) >> PGDIR_SHIFT) |
| 288 | |||
| 289 | #define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr)) | ||
| 290 | |||
| 291 | /* to find an entry in a kernel page-table-directory */ | ||
| 292 | #define pgd_offset_k(addr) pgd_offset(&init_mm, addr) | ||
| 293 | |||
| 294 | /* | ||
| 295 | * The "pgd_xxx()" functions here are trivial for a folded two-level | ||
| 296 | * setup: the pgd is never bad, and a pmd always exists (as it's folded | ||
| 297 | * into the pgd entry) | ||
| 298 | */ | ||
| 299 | #define pgd_none(pgd) (0) | ||
| 300 | #define pgd_bad(pgd) (0) | ||
| 301 | #define pgd_present(pgd) (1) | ||
| 302 | #define pgd_clear(pgdp) do { } while (0) | ||
| 303 | #define set_pgd(pgd,pgdp) do { } while (0) | ||
| 304 | |||
| 305 | |||
| 306 | /* Find an entry in the second-level page table.. */ | ||
| 307 | #define pmd_offset(dir, addr) ((pmd_t *)(dir)) | ||
| 308 | |||
| 309 | #define pmd_none(pmd) (!pmd_val(pmd)) | ||
| 310 | #define pmd_present(pmd) (pmd_val(pmd)) | ||
| 311 | #define pmd_bad(pmd) (pmd_val(pmd) & 2) | ||
| 312 | |||
| 313 | #define copy_pmd(pmdpd,pmdps) \ | ||
| 314 | do { \ | ||
| 315 | pmdpd[0] = pmdps[0]; \ | ||
| 316 | pmdpd[1] = pmdps[1]; \ | ||
| 317 | flush_pmd_entry(pmdpd); \ | ||
| 318 | } while (0) | ||
| 319 | |||
| 320 | #define pmd_clear(pmdp) \ | ||
| 321 | do { \ | ||
| 322 | pmdp[0] = __pmd(0); \ | ||
| 323 | pmdp[1] = __pmd(0); \ | ||
| 324 | clean_pmd_entry(pmdp); \ | ||
| 325 | } while (0) | ||
| 326 | |||
| 327 | static inline pte_t *pmd_page_vaddr(pmd_t pmd) | ||
| 328 | { | ||
| 329 | return __va(pmd_val(pmd) & PAGE_MASK); | ||
| 330 | } | ||
| 331 | |||
| 332 | #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd))) | ||
| 333 | |||
| 334 | /* we don't need complex calculations here as the pmd is folded into the pgd */ | ||
| 335 | #define pmd_addr_end(addr,end) (end) | ||
| 265 | 336 | ||
| 266 | #define pte_offset_map(dir,addr) (__pte_map(dir) + __pte_index(addr)) | ||
| 267 | #define pte_unmap(pte) __pte_unmap(pte) | ||
| 268 | 337 | ||
| 269 | #ifndef CONFIG_HIGHPTE | 338 | #ifndef CONFIG_HIGHPTE |
| 270 | #define __pte_map(dir) pmd_page_vaddr(*(dir)) | 339 | #define __pte_map(pmd) pmd_page_vaddr(*(pmd)) |
| 271 | #define __pte_unmap(pte) do { } while (0) | 340 | #define __pte_unmap(pte) do { } while (0) |
| 272 | #else | 341 | #else |
| 273 | #define __pte_map(dir) ((pte_t *)kmap_atomic(pmd_page(*(dir))) + PTRS_PER_PTE) | 342 | #define __pte_map(pmd) (pte_t *)kmap_atomic(pmd_page(*(pmd))) |
| 274 | #define __pte_unmap(pte) kunmap_atomic((pte - PTRS_PER_PTE)) | 343 | #define __pte_unmap(pte) kunmap_atomic(pte) |
| 275 | #endif | 344 | #endif |
| 276 | 345 | ||
| 346 | #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) | ||
| 347 | |||
| 348 | #define pte_offset_kernel(pmd,addr) (pmd_page_vaddr(*(pmd)) + pte_index(addr)) | ||
| 349 | |||
| 350 | #define pte_offset_map(pmd,addr) (__pte_map(pmd) + pte_index(addr)) | ||
| 351 | #define pte_unmap(pte) __pte_unmap(pte) | ||
| 352 | |||
| 353 | #define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) | ||
| 354 | #define pfn_pte(pfn,prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) | ||
| 355 | |||
| 356 | #define pte_page(pte) pfn_to_page(pte_pfn(pte)) | ||
| 357 | #define mk_pte(page,prot) pfn_pte(page_to_pfn(page), prot) | ||
| 358 | |||
| 277 | #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext) | 359 | #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext) |
| 360 | #define pte_clear(mm,addr,ptep) set_pte_ext(ptep, __pte(0), 0) | ||
| 278 | 361 | ||
| 279 | #if __LINUX_ARM_ARCH__ < 6 | 362 | #if __LINUX_ARM_ARCH__ < 6 |
| 280 | static inline void __sync_icache_dcache(pte_t pteval) | 363 | static inline void __sync_icache_dcache(pte_t pteval) |
| @@ -295,15 +378,12 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, | |||
| 295 | } | 378 | } |
| 296 | } | 379 | } |
| 297 | 380 | ||
| 298 | /* | 381 | #define pte_none(pte) (!pte_val(pte)) |
| 299 | * The following only work if pte_present() is true. | ||
| 300 | * Undefined behaviour if not.. | ||
| 301 | */ | ||
| 302 | #define pte_present(pte) (pte_val(pte) & L_PTE_PRESENT) | 382 | #define pte_present(pte) (pte_val(pte) & L_PTE_PRESENT) |
| 303 | #define pte_write(pte) (pte_val(pte) & L_PTE_WRITE) | 383 | #define pte_write(pte) (!(pte_val(pte) & L_PTE_RDONLY)) |
| 304 | #define pte_dirty(pte) (pte_val(pte) & L_PTE_DIRTY) | 384 | #define pte_dirty(pte) (pte_val(pte) & L_PTE_DIRTY) |
| 305 | #define pte_young(pte) (pte_val(pte) & L_PTE_YOUNG) | 385 | #define pte_young(pte) (pte_val(pte) & L_PTE_YOUNG) |
| 306 | #define pte_exec(pte) (pte_val(pte) & L_PTE_EXEC) | 386 | #define pte_exec(pte) (!(pte_val(pte) & L_PTE_XN)) |
| 307 | #define pte_special(pte) (0) | 387 | #define pte_special(pte) (0) |
| 308 | 388 | ||
| 309 | #define pte_present_user(pte) \ | 389 | #define pte_present_user(pte) \ |
| @@ -313,8 +393,8 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, | |||
| 313 | #define PTE_BIT_FUNC(fn,op) \ | 393 | #define PTE_BIT_FUNC(fn,op) \ |
| 314 | static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; } | 394 | static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; } |
| 315 | 395 | ||
| 316 | PTE_BIT_FUNC(wrprotect, &= ~L_PTE_WRITE); | 396 | PTE_BIT_FUNC(wrprotect, |= L_PTE_RDONLY); |
| 317 | PTE_BIT_FUNC(mkwrite, |= L_PTE_WRITE); | 397 | PTE_BIT_FUNC(mkwrite, &= ~L_PTE_RDONLY); |
| 318 | PTE_BIT_FUNC(mkclean, &= ~L_PTE_DIRTY); | 398 | PTE_BIT_FUNC(mkclean, &= ~L_PTE_DIRTY); |
| 319 | PTE_BIT_FUNC(mkdirty, |= L_PTE_DIRTY); | 399 | PTE_BIT_FUNC(mkdirty, |= L_PTE_DIRTY); |
| 320 | PTE_BIT_FUNC(mkold, &= ~L_PTE_YOUNG); | 400 | PTE_BIT_FUNC(mkold, &= ~L_PTE_YOUNG); |
| @@ -322,101 +402,13 @@ PTE_BIT_FUNC(mkyoung, |= L_PTE_YOUNG); | |||
| 322 | 402 | ||
| 323 | static inline pte_t pte_mkspecial(pte_t pte) { return pte; } | 403 | static inline pte_t pte_mkspecial(pte_t pte) { return pte; } |
| 324 | 404 | ||
| 325 | #define __pgprot_modify(prot,mask,bits) \ | ||
| 326 | __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) | ||
| 327 | |||
| 328 | /* | ||
| 329 | * Mark the prot value as uncacheable and unbufferable. | ||
| 330 | */ | ||
| 331 | #define pgprot_noncached(prot) \ | ||
| 332 | __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED) | ||
| 333 | #define pgprot_writecombine(prot) \ | ||
| 334 | __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE) | ||
| 335 | #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE | ||
| 336 | #define pgprot_dmacoherent(prot) \ | ||
| 337 | __pgprot_modify(prot, L_PTE_MT_MASK|L_PTE_EXEC, L_PTE_MT_BUFFERABLE) | ||
| 338 | #define __HAVE_PHYS_MEM_ACCESS_PROT | ||
| 339 | struct file; | ||
| 340 | extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, | ||
| 341 | unsigned long size, pgprot_t vma_prot); | ||
| 342 | #else | ||
| 343 | #define pgprot_dmacoherent(prot) \ | ||
| 344 | __pgprot_modify(prot, L_PTE_MT_MASK|L_PTE_EXEC, L_PTE_MT_UNCACHED) | ||
| 345 | #endif | ||
| 346 | |||
| 347 | #define pmd_none(pmd) (!pmd_val(pmd)) | ||
| 348 | #define pmd_present(pmd) (pmd_val(pmd)) | ||
| 349 | #define pmd_bad(pmd) (pmd_val(pmd) & 2) | ||
| 350 | |||
| 351 | #define copy_pmd(pmdpd,pmdps) \ | ||
| 352 | do { \ | ||
| 353 | pmdpd[0] = pmdps[0]; \ | ||
| 354 | pmdpd[1] = pmdps[1]; \ | ||
| 355 | flush_pmd_entry(pmdpd); \ | ||
| 356 | } while (0) | ||
| 357 | |||
| 358 | #define pmd_clear(pmdp) \ | ||
| 359 | do { \ | ||
| 360 | pmdp[0] = __pmd(0); \ | ||
| 361 | pmdp[1] = __pmd(0); \ | ||
| 362 | clean_pmd_entry(pmdp); \ | ||
| 363 | } while (0) | ||
| 364 | |||
| 365 | static inline pte_t *pmd_page_vaddr(pmd_t pmd) | ||
| 366 | { | ||
| 367 | unsigned long ptr; | ||
| 368 | |||
| 369 | ptr = pmd_val(pmd) & ~(PTRS_PER_PTE * sizeof(void *) - 1); | ||
| 370 | ptr += PTRS_PER_PTE * sizeof(void *); | ||
| 371 | |||
| 372 | return __va(ptr); | ||
| 373 | } | ||
| 374 | |||
| 375 | #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd))) | ||
| 376 | |||
| 377 | /* we don't need complex calculations here as the pmd is folded into the pgd */ | ||
| 378 | #define pmd_addr_end(addr,end) (end) | ||
| 379 | |||
| 380 | /* | ||
| 381 | * Conversion functions: convert a page and protection to a page entry, | ||
| 382 | * and a page entry and page directory to the page they refer to. | ||
| 383 | */ | ||
| 384 | #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) | ||
| 385 | |||
| 386 | /* | ||
| 387 | * The "pgd_xxx()" functions here are trivial for a folded two-level | ||
| 388 | * setup: the pgd is never bad, and a pmd always exists (as it's folded | ||
| 389 | * into the pgd entry) | ||
| 390 | */ | ||
| 391 | #define pgd_none(pgd) (0) | ||
| 392 | #define pgd_bad(pgd) (0) | ||
| 393 | #define pgd_present(pgd) (1) | ||
| 394 | #define pgd_clear(pgdp) do { } while (0) | ||
| 395 | #define set_pgd(pgd,pgdp) do { } while (0) | ||
| 396 | |||
| 397 | /* to find an entry in a page-table-directory */ | ||
| 398 | #define pgd_index(addr) ((addr) >> PGDIR_SHIFT) | ||
| 399 | |||
| 400 | #define pgd_offset(mm, addr) ((mm)->pgd+pgd_index(addr)) | ||
| 401 | |||
| 402 | /* to find an entry in a kernel page-table-directory */ | ||
| 403 | #define pgd_offset_k(addr) pgd_offset(&init_mm, addr) | ||
| 404 | |||
| 405 | /* Find an entry in the second-level page table.. */ | ||
| 406 | #define pmd_offset(dir, addr) ((pmd_t *)(dir)) | ||
| 407 | |||
| 408 | /* Find an entry in the third-level page table.. */ | ||
| 409 | #define __pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) | ||
| 410 | |||
| 411 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) | 405 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) |
| 412 | { | 406 | { |
| 413 | const unsigned long mask = L_PTE_EXEC | L_PTE_WRITE | L_PTE_USER; | 407 | const pteval_t mask = L_PTE_XN | L_PTE_RDONLY | L_PTE_USER; |
| 414 | pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); | 408 | pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); |
| 415 | return pte; | 409 | return pte; |
| 416 | } | 410 | } |
| 417 | 411 | ||
| 418 | extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; | ||
| 419 | |||
| 420 | /* | 412 | /* |
| 421 | * Encode and decode a swap entry. Swap entries are stored in the Linux | 413 | * Encode and decode a swap entry. Swap entries are stored in the Linux |
| 422 | * page tables as follows: | 414 | * page tables as follows: |
| @@ -481,6 +473,9 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; | |||
| 481 | 473 | ||
| 482 | #define pgtable_cache_init() do { } while (0) | 474 | #define pgtable_cache_init() do { } while (0) |
| 483 | 475 | ||
| 476 | void identity_mapping_add(pgd_t *, unsigned long, unsigned long); | ||
| 477 | void identity_mapping_del(pgd_t *, unsigned long, unsigned long); | ||
| 478 | |||
| 484 | #endif /* !__ASSEMBLY__ */ | 479 | #endif /* !__ASSEMBLY__ */ |
| 485 | 480 | ||
| 486 | #endif /* CONFIG_MMU */ | 481 | #endif /* CONFIG_MMU */ |
diff --git a/arch/arm/include/asm/sched_clock.h b/arch/arm/include/asm/sched_clock.h new file mode 100644 index 000000000000..a84628be1a7b --- /dev/null +++ b/arch/arm/include/asm/sched_clock.h | |||
| @@ -0,0 +1,118 @@ | |||
| 1 | /* | ||
| 2 | * sched_clock.h: support for extending counters to full 64-bit ns counter | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | #ifndef ASM_SCHED_CLOCK | ||
| 9 | #define ASM_SCHED_CLOCK | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/types.h> | ||
| 13 | |||
| 14 | struct clock_data { | ||
| 15 | u64 epoch_ns; | ||
| 16 | u32 epoch_cyc; | ||
| 17 | u32 epoch_cyc_copy; | ||
| 18 | u32 mult; | ||
| 19 | u32 shift; | ||
| 20 | }; | ||
| 21 | |||
| 22 | #define DEFINE_CLOCK_DATA(name) struct clock_data name | ||
| 23 | |||
| 24 | static inline u64 cyc_to_ns(u64 cyc, u32 mult, u32 shift) | ||
| 25 | { | ||
| 26 | return (cyc * mult) >> shift; | ||
| 27 | } | ||
| 28 | |||
| 29 | /* | ||
| 30 | * Atomically update the sched_clock epoch. Your update callback will | ||
| 31 | * be called from a timer before the counter wraps - read the current | ||
| 32 | * counter value, and call this function to safely move the epochs | ||
| 33 | * forward. Only use this from the update callback. | ||
| 34 | */ | ||
| 35 | static inline void update_sched_clock(struct clock_data *cd, u32 cyc, u32 mask) | ||
| 36 | { | ||
| 37 | unsigned long flags; | ||
| 38 | u64 ns = cd->epoch_ns + | ||
| 39 | cyc_to_ns((cyc - cd->epoch_cyc) & mask, cd->mult, cd->shift); | ||
| 40 | |||
| 41 | /* | ||
| 42 | * Write epoch_cyc and epoch_ns in a way that the update is | ||
| 43 | * detectable in cyc_to_fixed_sched_clock(). | ||
| 44 | */ | ||
| 45 | raw_local_irq_save(flags); | ||
| 46 | cd->epoch_cyc = cyc; | ||
| 47 | smp_wmb(); | ||
| 48 | cd->epoch_ns = ns; | ||
| 49 | smp_wmb(); | ||
| 50 | cd->epoch_cyc_copy = cyc; | ||
| 51 | raw_local_irq_restore(flags); | ||
| 52 | } | ||
| 53 | |||
| 54 | /* | ||
| 55 | * If your clock rate is known at compile time, using this will allow | ||
| 56 | * you to optimize the mult/shift loads away. This is paired with | ||
| 57 | * init_fixed_sched_clock() to ensure that your mult/shift are correct. | ||
| 58 | */ | ||
| 59 | static inline unsigned long long cyc_to_fixed_sched_clock(struct clock_data *cd, | ||
| 60 | u32 cyc, u32 mask, u32 mult, u32 shift) | ||
| 61 | { | ||
| 62 | u64 epoch_ns; | ||
| 63 | u32 epoch_cyc; | ||
| 64 | |||
| 65 | /* | ||
| 66 | * Load the epoch_cyc and epoch_ns atomically. We do this by | ||
| 67 | * ensuring that we always write epoch_cyc, epoch_ns and | ||
| 68 | * epoch_cyc_copy in strict order, and read them in strict order. | ||
| 69 | * If epoch_cyc and epoch_cyc_copy are not equal, then we're in | ||
| 70 | * the middle of an update, and we should repeat the load. | ||
| 71 | */ | ||
| 72 | do { | ||
| 73 | epoch_cyc = cd->epoch_cyc; | ||
| 74 | smp_rmb(); | ||
| 75 | epoch_ns = cd->epoch_ns; | ||
| 76 | smp_rmb(); | ||
| 77 | } while (epoch_cyc != cd->epoch_cyc_copy); | ||
| 78 | |||
| 79 | return epoch_ns + cyc_to_ns((cyc - epoch_cyc) & mask, mult, shift); | ||
| 80 | } | ||
| 81 | |||
| 82 | /* | ||
| 83 | * Otherwise, you need to use this, which will obtain the mult/shift | ||
| 84 | * from the clock_data structure. Use init_sched_clock() with this. | ||
| 85 | */ | ||
| 86 | static inline unsigned long long cyc_to_sched_clock(struct clock_data *cd, | ||
| 87 | u32 cyc, u32 mask) | ||
| 88 | { | ||
| 89 | return cyc_to_fixed_sched_clock(cd, cyc, mask, cd->mult, cd->shift); | ||
| 90 | } | ||
| 91 | |||
| 92 | /* | ||
| 93 | * Initialize the clock data - calculate the appropriate multiplier | ||
| 94 | * and shift. Also setup a timer to ensure that the epoch is refreshed | ||
| 95 | * at the appropriate time interval, which will call your update | ||
| 96 | * handler. | ||
| 97 | */ | ||
| 98 | void init_sched_clock(struct clock_data *, void (*)(void), | ||
| 99 | unsigned int, unsigned long); | ||
| 100 | |||
| 101 | /* | ||
| 102 | * Use this initialization function rather than init_sched_clock() if | ||
| 103 | * you're using cyc_to_fixed_sched_clock, which will warn if your | ||
| 104 | * constants are incorrect. | ||
| 105 | */ | ||
| 106 | static inline void init_fixed_sched_clock(struct clock_data *cd, | ||
| 107 | void (*update)(void), unsigned int bits, unsigned long rate, | ||
| 108 | u32 mult, u32 shift) | ||
| 109 | { | ||
| 110 | init_sched_clock(cd, update, bits, rate); | ||
| 111 | if (cd->mult != mult || cd->shift != shift) { | ||
| 112 | pr_crit("sched_clock: wrong multiply/shift: %u>>%u vs calculated %u>>%u\n" | ||
| 113 | "sched_clock: fix multiply/shift to avoid scheduler hiccups\n", | ||
| 114 | mult, shift, cd->mult, cd->shift); | ||
| 115 | } | ||
| 116 | } | ||
| 117 | |||
| 118 | #endif | ||
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h index 3d05190797cb..96ed521f2408 100644 --- a/arch/arm/include/asm/smp.h +++ b/arch/arm/include/asm/smp.h | |||
| @@ -33,27 +33,23 @@ struct seq_file; | |||
| 33 | /* | 33 | /* |
| 34 | * generate IPI list text | 34 | * generate IPI list text |
| 35 | */ | 35 | */ |
| 36 | extern void show_ipi_list(struct seq_file *p); | 36 | extern void show_ipi_list(struct seq_file *, int); |
| 37 | 37 | ||
| 38 | /* | 38 | /* |
| 39 | * Called from assembly code, this handles an IPI. | 39 | * Called from assembly code, this handles an IPI. |
| 40 | */ | 40 | */ |
| 41 | asmlinkage void do_IPI(struct pt_regs *regs); | 41 | asmlinkage void do_IPI(int ipinr, struct pt_regs *regs); |
| 42 | 42 | ||
| 43 | /* | 43 | /* |
| 44 | * Setup the set of possible CPUs (via set_cpu_possible) | 44 | * Setup the set of possible CPUs (via set_cpu_possible) |
| 45 | */ | 45 | */ |
| 46 | extern void smp_init_cpus(void); | 46 | extern void smp_init_cpus(void); |
| 47 | 47 | ||
| 48 | /* | ||
| 49 | * Move global data into per-processor storage. | ||
| 50 | */ | ||
| 51 | extern void smp_store_cpu_info(unsigned int cpuid); | ||
| 52 | 48 | ||
| 53 | /* | 49 | /* |
| 54 | * Raise an IPI cross call on CPUs in callmap. | 50 | * Raise an IPI cross call on CPUs in callmap. |
| 55 | */ | 51 | */ |
| 56 | extern void smp_cross_call(const struct cpumask *mask); | 52 | extern void smp_cross_call(const struct cpumask *mask, int ipi); |
| 57 | 53 | ||
| 58 | /* | 54 | /* |
| 59 | * Boot a secondary CPU, and assign it the specified idle task. | 55 | * Boot a secondary CPU, and assign it the specified idle task. |
| @@ -73,6 +69,11 @@ asmlinkage void secondary_start_kernel(void); | |||
| 73 | extern void platform_secondary_init(unsigned int cpu); | 69 | extern void platform_secondary_init(unsigned int cpu); |
| 74 | 70 | ||
| 75 | /* | 71 | /* |
| 72 | * Initialize cpu_possible map, and enable coherency | ||
| 73 | */ | ||
| 74 | extern void platform_smp_prepare_cpus(unsigned int); | ||
| 75 | |||
| 76 | /* | ||
| 76 | * Initial data for bringing up a secondary CPU. | 77 | * Initial data for bringing up a secondary CPU. |
| 77 | */ | 78 | */ |
| 78 | struct secondary_data { | 79 | struct secondary_data { |
| @@ -97,6 +98,6 @@ extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); | |||
| 97 | /* | 98 | /* |
| 98 | * show local interrupt info | 99 | * show local interrupt info |
| 99 | */ | 100 | */ |
| 100 | extern void show_local_irqs(struct seq_file *); | 101 | extern void show_local_irqs(struct seq_file *, int); |
| 101 | 102 | ||
| 102 | #endif /* ifndef __ASM_ARM_SMP_H */ | 103 | #endif /* ifndef __ASM_ARM_SMP_H */ |
diff --git a/arch/arm/include/asm/smp_mpidr.h b/arch/arm/include/asm/smp_mpidr.h deleted file mode 100644 index 6a9307d64900..000000000000 --- a/arch/arm/include/asm/smp_mpidr.h +++ /dev/null | |||
| @@ -1,17 +0,0 @@ | |||
| 1 | #ifndef ASMARM_SMP_MIDR_H | ||
| 2 | #define ASMARM_SMP_MIDR_H | ||
| 3 | |||
| 4 | #define hard_smp_processor_id() \ | ||
| 5 | ({ \ | ||
| 6 | unsigned int cpunum; \ | ||
| 7 | __asm__("\n" \ | ||
| 8 | "1: mrc p15, 0, %0, c0, c0, 5\n" \ | ||
| 9 | " .pushsection \".alt.smp.init\", \"a\"\n"\ | ||
| 10 | " .long 1b\n" \ | ||
| 11 | " mov %0, #0\n" \ | ||
| 12 | " .popsection" \ | ||
| 13 | : "=r" (cpunum)); \ | ||
| 14 | cpunum &= 0x0F; \ | ||
| 15 | }) | ||
| 16 | |||
| 17 | #endif | ||
diff --git a/arch/arm/include/asm/smp_twd.h b/arch/arm/include/asm/smp_twd.h index 634f357be6bb..fed9981fba08 100644 --- a/arch/arm/include/asm/smp_twd.h +++ b/arch/arm/include/asm/smp_twd.h | |||
| @@ -22,7 +22,6 @@ struct clock_event_device; | |||
| 22 | 22 | ||
| 23 | extern void __iomem *twd_base; | 23 | extern void __iomem *twd_base; |
| 24 | 24 | ||
| 25 | void twd_timer_stop(void); | ||
| 26 | int twd_timer_ack(void); | 25 | int twd_timer_ack(void); |
| 27 | void twd_timer_setup(struct clock_event_device *); | 26 | void twd_timer_setup(struct clock_event_device *); |
| 28 | 27 | ||
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 80025948b8ad..97f6d60297d5 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h | |||
| @@ -63,6 +63,11 @@ | |||
| 63 | #include <asm/outercache.h> | 63 | #include <asm/outercache.h> |
| 64 | 64 | ||
| 65 | #define __exception __attribute__((section(".exception.text"))) | 65 | #define __exception __attribute__((section(".exception.text"))) |
| 66 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER | ||
| 67 | #define __exception_irq_entry __irq_entry | ||
| 68 | #else | ||
| 69 | #define __exception_irq_entry __exception | ||
| 70 | #endif | ||
| 66 | 71 | ||
| 67 | struct thread_info; | 72 | struct thread_info; |
| 68 | struct task_struct; | 73 | struct task_struct; |
| @@ -119,6 +124,13 @@ extern unsigned int user_debug; | |||
| 119 | #define vectors_high() (0) | 124 | #define vectors_high() (0) |
| 120 | #endif | 125 | #endif |
| 121 | 126 | ||
| 127 | #if __LINUX_ARM_ARCH__ >= 7 || \ | ||
| 128 | (__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K)) | ||
| 129 | #define sev() __asm__ __volatile__ ("sev" : : : "memory") | ||
| 130 | #define wfe() __asm__ __volatile__ ("wfe" : : : "memory") | ||
| 131 | #define wfi() __asm__ __volatile__ ("wfi" : : : "memory") | ||
| 132 | #endif | ||
| 133 | |||
| 122 | #if __LINUX_ARM_ARCH__ >= 7 | 134 | #if __LINUX_ARM_ARCH__ >= 7 |
| 123 | #define isb() __asm__ __volatile__ ("isb" : : : "memory") | 135 | #define isb() __asm__ __volatile__ ("isb" : : : "memory") |
| 124 | #define dsb() __asm__ __volatile__ ("dsb" : : : "memory") | 136 | #define dsb() __asm__ __volatile__ ("dsb" : : : "memory") |
diff --git a/arch/arm/include/asm/traps.h b/arch/arm/include/asm/traps.h index 491960bf4260..1b960d5ef6a5 100644 --- a/arch/arm/include/asm/traps.h +++ b/arch/arm/include/asm/traps.h | |||
| @@ -15,16 +15,37 @@ struct undef_hook { | |||
| 15 | void register_undef_hook(struct undef_hook *hook); | 15 | void register_undef_hook(struct undef_hook *hook); |
| 16 | void unregister_undef_hook(struct undef_hook *hook); | 16 | void unregister_undef_hook(struct undef_hook *hook); |
| 17 | 17 | ||
| 18 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER | ||
| 19 | static inline int __in_irqentry_text(unsigned long ptr) | ||
| 20 | { | ||
| 21 | extern char __irqentry_text_start[]; | ||
| 22 | extern char __irqentry_text_end[]; | ||
| 23 | |||
| 24 | return ptr >= (unsigned long)&__irqentry_text_start && | ||
| 25 | ptr < (unsigned long)&__irqentry_text_end; | ||
| 26 | } | ||
| 27 | #else | ||
| 28 | static inline int __in_irqentry_text(unsigned long ptr) | ||
| 29 | { | ||
| 30 | return 0; | ||
| 31 | } | ||
| 32 | #endif | ||
| 33 | |||
| 18 | static inline int in_exception_text(unsigned long ptr) | 34 | static inline int in_exception_text(unsigned long ptr) |
| 19 | { | 35 | { |
| 20 | extern char __exception_text_start[]; | 36 | extern char __exception_text_start[]; |
| 21 | extern char __exception_text_end[]; | 37 | extern char __exception_text_end[]; |
| 38 | int in; | ||
| 22 | 39 | ||
| 23 | return ptr >= (unsigned long)&__exception_text_start && | 40 | in = ptr >= (unsigned long)&__exception_text_start && |
| 24 | ptr < (unsigned long)&__exception_text_end; | 41 | ptr < (unsigned long)&__exception_text_end; |
| 42 | |||
| 43 | return in ? : __in_irqentry_text(ptr); | ||
| 25 | } | 44 | } |
| 26 | 45 | ||
| 27 | extern void __init early_trap_init(void); | 46 | extern void __init early_trap_init(void); |
| 28 | extern void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long frame); | 47 | extern void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long frame); |
| 29 | 48 | ||
| 49 | extern void *vectors_page; | ||
| 50 | |||
| 30 | #endif | 51 | #endif |
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h index 33e4a48fe103..b293616a1a1a 100644 --- a/arch/arm/include/asm/uaccess.h +++ b/arch/arm/include/asm/uaccess.h | |||
| @@ -227,7 +227,7 @@ do { \ | |||
| 227 | 227 | ||
| 228 | #define __get_user_asm_byte(x,addr,err) \ | 228 | #define __get_user_asm_byte(x,addr,err) \ |
| 229 | __asm__ __volatile__( \ | 229 | __asm__ __volatile__( \ |
| 230 | "1: ldrbt %1,[%2]\n" \ | 230 | "1: " T(ldrb) " %1,[%2],#0\n" \ |
| 231 | "2:\n" \ | 231 | "2:\n" \ |
| 232 | " .pushsection .fixup,\"ax\"\n" \ | 232 | " .pushsection .fixup,\"ax\"\n" \ |
| 233 | " .align 2\n" \ | 233 | " .align 2\n" \ |
| @@ -263,7 +263,7 @@ do { \ | |||
| 263 | 263 | ||
| 264 | #define __get_user_asm_word(x,addr,err) \ | 264 | #define __get_user_asm_word(x,addr,err) \ |
| 265 | __asm__ __volatile__( \ | 265 | __asm__ __volatile__( \ |
| 266 | "1: ldrt %1,[%2]\n" \ | 266 | "1: " T(ldr) " %1,[%2],#0\n" \ |
| 267 | "2:\n" \ | 267 | "2:\n" \ |
| 268 | " .pushsection .fixup,\"ax\"\n" \ | 268 | " .pushsection .fixup,\"ax\"\n" \ |
| 269 | " .align 2\n" \ | 269 | " .align 2\n" \ |
| @@ -308,7 +308,7 @@ do { \ | |||
| 308 | 308 | ||
| 309 | #define __put_user_asm_byte(x,__pu_addr,err) \ | 309 | #define __put_user_asm_byte(x,__pu_addr,err) \ |
| 310 | __asm__ __volatile__( \ | 310 | __asm__ __volatile__( \ |
| 311 | "1: strbt %1,[%2]\n" \ | 311 | "1: " T(strb) " %1,[%2],#0\n" \ |
| 312 | "2:\n" \ | 312 | "2:\n" \ |
| 313 | " .pushsection .fixup,\"ax\"\n" \ | 313 | " .pushsection .fixup,\"ax\"\n" \ |
| 314 | " .align 2\n" \ | 314 | " .align 2\n" \ |
| @@ -341,7 +341,7 @@ do { \ | |||
| 341 | 341 | ||
| 342 | #define __put_user_asm_word(x,__pu_addr,err) \ | 342 | #define __put_user_asm_word(x,__pu_addr,err) \ |
| 343 | __asm__ __volatile__( \ | 343 | __asm__ __volatile__( \ |
| 344 | "1: strt %1,[%2]\n" \ | 344 | "1: " T(str) " %1,[%2],#0\n" \ |
| 345 | "2:\n" \ | 345 | "2:\n" \ |
| 346 | " .pushsection .fixup,\"ax\"\n" \ | 346 | " .pushsection .fixup,\"ax\"\n" \ |
| 347 | " .align 2\n" \ | 347 | " .align 2\n" \ |
| @@ -366,10 +366,10 @@ do { \ | |||
| 366 | 366 | ||
| 367 | #define __put_user_asm_dword(x,__pu_addr,err) \ | 367 | #define __put_user_asm_dword(x,__pu_addr,err) \ |
| 368 | __asm__ __volatile__( \ | 368 | __asm__ __volatile__( \ |
| 369 | ARM( "1: strt " __reg_oper1 ", [%1], #4\n" ) \ | 369 | ARM( "1: " T(str) " " __reg_oper1 ", [%1], #4\n" ) \ |
| 370 | ARM( "2: strt " __reg_oper0 ", [%1]\n" ) \ | 370 | ARM( "2: " T(str) " " __reg_oper0 ", [%1]\n" ) \ |
| 371 | THUMB( "1: strt " __reg_oper1 ", [%1]\n" ) \ | 371 | THUMB( "1: " T(str) " " __reg_oper1 ", [%1]\n" ) \ |
| 372 | THUMB( "2: strt " __reg_oper0 ", [%1, #4]\n" ) \ | 372 | THUMB( "2: " T(str) " " __reg_oper0 ", [%1, #4]\n" ) \ |
| 373 | "3:\n" \ | 373 | "3:\n" \ |
| 374 | " .pushsection .fixup,\"ax\"\n" \ | 374 | " .pushsection .fixup,\"ax\"\n" \ |
| 375 | " .align 2\n" \ | 375 | " .align 2\n" \ |
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 5b9b268f4fbb..185ee822c935 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile | |||
| @@ -5,7 +5,7 @@ | |||
| 5 | CPPFLAGS_vmlinux.lds := -DTEXT_OFFSET=$(TEXT_OFFSET) | 5 | CPPFLAGS_vmlinux.lds := -DTEXT_OFFSET=$(TEXT_OFFSET) |
| 6 | AFLAGS_head.o := -DTEXT_OFFSET=$(TEXT_OFFSET) | 6 | AFLAGS_head.o := -DTEXT_OFFSET=$(TEXT_OFFSET) |
| 7 | 7 | ||
| 8 | ifdef CONFIG_DYNAMIC_FTRACE | 8 | ifdef CONFIG_FUNCTION_TRACER |
| 9 | CFLAGS_REMOVE_ftrace.o = -pg | 9 | CFLAGS_REMOVE_ftrace.o = -pg |
| 10 | endif | 10 | endif |
| 11 | 11 | ||
| @@ -29,10 +29,12 @@ obj-$(CONFIG_MODULES) += armksyms.o module.o | |||
| 29 | obj-$(CONFIG_ARTHUR) += arthur.o | 29 | obj-$(CONFIG_ARTHUR) += arthur.o |
| 30 | obj-$(CONFIG_ISA_DMA) += dma-isa.o | 30 | obj-$(CONFIG_ISA_DMA) += dma-isa.o |
| 31 | obj-$(CONFIG_PCI) += bios32.o isa.o | 31 | obj-$(CONFIG_PCI) += bios32.o isa.o |
| 32 | obj-$(CONFIG_SMP) += smp.o | 32 | obj-$(CONFIG_HAVE_SCHED_CLOCK) += sched_clock.o |
| 33 | obj-$(CONFIG_SMP) += smp.o smp_tlb.o | ||
| 33 | obj-$(CONFIG_HAVE_ARM_SCU) += smp_scu.o | 34 | obj-$(CONFIG_HAVE_ARM_SCU) += smp_scu.o |
| 34 | obj-$(CONFIG_HAVE_ARM_TWD) += smp_twd.o | 35 | obj-$(CONFIG_HAVE_ARM_TWD) += smp_twd.o |
| 35 | obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o | 36 | obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o |
| 37 | obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o | ||
| 36 | obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o | 38 | obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o |
| 37 | obj-$(CONFIG_KPROBES) += kprobes.o kprobes-decode.o | 39 | obj-$(CONFIG_KPROBES) += kprobes.o kprobes-decode.o |
| 38 | obj-$(CONFIG_ATAGS_PROC) += atags.o | 40 | obj-$(CONFIG_ATAGS_PROC) += atags.o |
| @@ -42,6 +44,8 @@ obj-$(CONFIG_KGDB) += kgdb.o | |||
| 42 | obj-$(CONFIG_ARM_UNWIND) += unwind.o | 44 | obj-$(CONFIG_ARM_UNWIND) += unwind.o |
| 43 | obj-$(CONFIG_HAVE_TCM) += tcm.o | 45 | obj-$(CONFIG_HAVE_TCM) += tcm.o |
| 44 | obj-$(CONFIG_CRASH_DUMP) += crash_dump.o | 46 | obj-$(CONFIG_CRASH_DUMP) += crash_dump.o |
| 47 | obj-$(CONFIG_SWP_EMULATE) += swp_emulate.o | ||
| 48 | CFLAGS_swp_emulate.o := -Wa,-march=armv7-a | ||
| 45 | obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o | 49 | obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o |
| 46 | 50 | ||
| 47 | obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o | 51 | obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o |
| @@ -50,6 +54,7 @@ AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312 | |||
| 50 | obj-$(CONFIG_CPU_XSCALE) += xscale-cp0.o | 54 | obj-$(CONFIG_CPU_XSCALE) += xscale-cp0.o |
| 51 | obj-$(CONFIG_CPU_XSC3) += xscale-cp0.o | 55 | obj-$(CONFIG_CPU_XSC3) += xscale-cp0.o |
| 52 | obj-$(CONFIG_CPU_MOHAWK) += xscale-cp0.o | 56 | obj-$(CONFIG_CPU_MOHAWK) += xscale-cp0.o |
| 57 | obj-$(CONFIG_CPU_PJ4) += pj4-cp0.o | ||
| 53 | obj-$(CONFIG_IWMMXT) += iwmmxt.o | 58 | obj-$(CONFIG_IWMMXT) += iwmmxt.o |
| 54 | obj-$(CONFIG_CPU_HAS_PMU) += pmu.o | 59 | obj-$(CONFIG_CPU_HAS_PMU) += pmu.o |
| 55 | obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o | 60 | obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o |
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index bb96a7d4bbf5..2b46fea36c9f 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S | |||
| @@ -25,42 +25,22 @@ | |||
| 25 | #include <asm/tls.h> | 25 | #include <asm/tls.h> |
| 26 | 26 | ||
| 27 | #include "entry-header.S" | 27 | #include "entry-header.S" |
| 28 | #include <asm/entry-macro-multi.S> | ||
| 28 | 29 | ||
| 29 | /* | 30 | /* |
| 30 | * Interrupt handling. Preserves r7, r8, r9 | 31 | * Interrupt handling. Preserves r7, r8, r9 |
| 31 | */ | 32 | */ |
| 32 | .macro irq_handler | 33 | .macro irq_handler |
| 33 | get_irqnr_preamble r5, lr | 34 | #ifdef CONFIG_MULTI_IRQ_HANDLER |
| 34 | 1: get_irqnr_and_base r0, r6, r5, lr | 35 | ldr r5, =handle_arch_irq |
| 35 | movne r1, sp | 36 | mov r0, sp |
| 36 | @ | 37 | ldr r5, [r5] |
| 37 | @ routine called with r0 = irq number, r1 = struct pt_regs * | 38 | adr lr, BSYM(9997f) |
| 38 | @ | 39 | teq r5, #0 |
| 39 | adrne lr, BSYM(1b) | 40 | movne pc, r5 |
| 40 | bne asm_do_IRQ | ||
| 41 | |||
| 42 | #ifdef CONFIG_SMP | ||
| 43 | /* | ||
| 44 | * XXX | ||
| 45 | * | ||
| 46 | * this macro assumes that irqstat (r6) and base (r5) are | ||
| 47 | * preserved from get_irqnr_and_base above | ||
| 48 | */ | ||
| 49 | ALT_SMP(test_for_ipi r0, r6, r5, lr) | ||
| 50 | ALT_UP_B(9997f) | ||
| 51 | movne r0, sp | ||
| 52 | adrne lr, BSYM(1b) | ||
| 53 | bne do_IPI | ||
| 54 | |||
| 55 | #ifdef CONFIG_LOCAL_TIMERS | ||
| 56 | test_for_ltirq r0, r6, r5, lr | ||
| 57 | movne r0, sp | ||
| 58 | adrne lr, BSYM(1b) | ||
| 59 | bne do_local_timer | ||
| 60 | #endif | 41 | #endif |
| 42 | arch_irq_handler_default | ||
| 61 | 9997: | 43 | 9997: |
| 62 | #endif | ||
| 63 | |||
| 64 | .endm | 44 | .endm |
| 65 | 45 | ||
| 66 | #ifdef CONFIG_KPROBES | 46 | #ifdef CONFIG_KPROBES |
| @@ -198,6 +178,7 @@ __dabt_svc: | |||
| 198 | @ | 178 | @ |
| 199 | @ set desired IRQ state, then call main handler | 179 | @ set desired IRQ state, then call main handler |
| 200 | @ | 180 | @ |
| 181 | debug_entry r1 | ||
| 201 | msr cpsr_c, r9 | 182 | msr cpsr_c, r9 |
| 202 | mov r2, sp | 183 | mov r2, sp |
| 203 | bl do_DataAbort | 184 | bl do_DataAbort |
| @@ -324,6 +305,7 @@ __pabt_svc: | |||
| 324 | #else | 305 | #else |
| 325 | bl CPU_PABORT_HANDLER | 306 | bl CPU_PABORT_HANDLER |
| 326 | #endif | 307 | #endif |
| 308 | debug_entry r1 | ||
| 327 | msr cpsr_c, r9 @ Maybe enable interrupts | 309 | msr cpsr_c, r9 @ Maybe enable interrupts |
| 328 | mov r2, sp @ regs | 310 | mov r2, sp @ regs |
| 329 | bl do_PrefetchAbort @ call abort handler | 311 | bl do_PrefetchAbort @ call abort handler |
| @@ -439,6 +421,7 @@ __dabt_usr: | |||
| 439 | @ | 421 | @ |
| 440 | @ IRQs on, then call the main handler | 422 | @ IRQs on, then call the main handler |
| 441 | @ | 423 | @ |
| 424 | debug_entry r1 | ||
| 442 | enable_irq | 425 | enable_irq |
| 443 | mov r2, sp | 426 | mov r2, sp |
| 444 | adr lr, BSYM(ret_from_exception) | 427 | adr lr, BSYM(ret_from_exception) |
| @@ -703,6 +686,7 @@ __pabt_usr: | |||
| 703 | #else | 686 | #else |
| 704 | bl CPU_PABORT_HANDLER | 687 | bl CPU_PABORT_HANDLER |
| 705 | #endif | 688 | #endif |
| 689 | debug_entry r1 | ||
| 706 | enable_irq @ Enable interrupts | 690 | enable_irq @ Enable interrupts |
| 707 | mov r2, sp @ regs | 691 | mov r2, sp @ regs |
| 708 | bl do_PrefetchAbort @ call abort handler | 692 | bl do_PrefetchAbort @ call abort handler |
| @@ -735,7 +719,7 @@ ENTRY(__switch_to) | |||
| 735 | THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack | 719 | THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack |
| 736 | THUMB( str sp, [ip], #4 ) | 720 | THUMB( str sp, [ip], #4 ) |
| 737 | THUMB( str lr, [ip], #4 ) | 721 | THUMB( str lr, [ip], #4 ) |
| 738 | #ifdef CONFIG_MMU | 722 | #ifdef CONFIG_CPU_USE_DOMAINS |
| 739 | ldr r6, [r2, #TI_CPU_DOMAIN] | 723 | ldr r6, [r2, #TI_CPU_DOMAIN] |
| 740 | #endif | 724 | #endif |
| 741 | set_tls r3, r4, r5 | 725 | set_tls r3, r4, r5 |
| @@ -744,7 +728,7 @@ ENTRY(__switch_to) | |||
| 744 | ldr r8, =__stack_chk_guard | 728 | ldr r8, =__stack_chk_guard |
| 745 | ldr r7, [r7, #TSK_STACK_CANARY] | 729 | ldr r7, [r7, #TSK_STACK_CANARY] |
| 746 | #endif | 730 | #endif |
| 747 | #ifdef CONFIG_MMU | 731 | #ifdef CONFIG_CPU_USE_DOMAINS |
| 748 | mcr p15, 0, r6, c3, c0, 0 @ Set domain register | 732 | mcr p15, 0, r6, c3, c0, 0 @ Set domain register |
| 749 | #endif | 733 | #endif |
| 750 | mov r5, r0 | 734 | mov r5, r0 |
| @@ -842,7 +826,7 @@ __kuser_helper_start: | |||
| 842 | */ | 826 | */ |
| 843 | 827 | ||
| 844 | __kuser_memory_barrier: @ 0xffff0fa0 | 828 | __kuser_memory_barrier: @ 0xffff0fa0 |
| 845 | smp_dmb | 829 | smp_dmb arm |
| 846 | usr_ret lr | 830 | usr_ret lr |
| 847 | 831 | ||
| 848 | .align 5 | 832 | .align 5 |
| @@ -959,7 +943,7 @@ kuser_cmpxchg_fixup: | |||
| 959 | 943 | ||
| 960 | #else | 944 | #else |
| 961 | 945 | ||
| 962 | smp_dmb | 946 | smp_dmb arm |
| 963 | 1: ldrex r3, [r2] | 947 | 1: ldrex r3, [r2] |
| 964 | subs r3, r3, r0 | 948 | subs r3, r3, r0 |
| 965 | strexeq r3, r1, [r2] | 949 | strexeq r3, r1, [r2] |
| @@ -1245,3 +1229,9 @@ cr_alignment: | |||
| 1245 | .space 4 | 1229 | .space 4 |
| 1246 | cr_no_alignment: | 1230 | cr_no_alignment: |
| 1247 | .space 4 | 1231 | .space 4 |
| 1232 | |||
| 1233 | #ifdef CONFIG_MULTI_IRQ_HANDLER | ||
| 1234 | .globl handle_arch_irq | ||
| 1235 | handle_arch_irq: | ||
| 1236 | .space 4 | ||
| 1237 | #endif | ||
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 80bf8cd88d7c..1e7b04a40a31 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S | |||
| @@ -147,98 +147,170 @@ ENDPROC(ret_from_fork) | |||
| 147 | #endif | 147 | #endif |
| 148 | #endif | 148 | #endif |
| 149 | 149 | ||
| 150 | #ifdef CONFIG_DYNAMIC_FTRACE | 150 | .macro __mcount suffix |
| 151 | ENTRY(__gnu_mcount_nc) | 151 | mcount_enter |
| 152 | mov ip, lr | 152 | ldr r0, =ftrace_trace_function |
| 153 | ldmia sp!, {lr} | 153 | ldr r2, [r0] |
| 154 | mov pc, ip | 154 | adr r0, .Lftrace_stub |
| 155 | ENDPROC(__gnu_mcount_nc) | 155 | cmp r0, r2 |
| 156 | bne 1f | ||
| 157 | |||
| 158 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER | ||
| 159 | ldr r1, =ftrace_graph_return | ||
| 160 | ldr r2, [r1] | ||
| 161 | cmp r0, r2 | ||
| 162 | bne ftrace_graph_caller\suffix | ||
| 163 | |||
| 164 | ldr r1, =ftrace_graph_entry | ||
| 165 | ldr r2, [r1] | ||
| 166 | ldr r0, =ftrace_graph_entry_stub | ||
| 167 | cmp r0, r2 | ||
| 168 | bne ftrace_graph_caller\suffix | ||
| 169 | #endif | ||
| 156 | 170 | ||
| 157 | ENTRY(ftrace_caller) | 171 | mcount_exit |
| 158 | stmdb sp!, {r0-r3, lr} | 172 | |
| 159 | mov r0, lr | 173 | 1: mcount_get_lr r1 @ lr of instrumented func |
| 174 | mov r0, lr @ instrumented function | ||
| 175 | sub r0, r0, #MCOUNT_INSN_SIZE | ||
| 176 | adr lr, BSYM(2f) | ||
| 177 | mov pc, r2 | ||
| 178 | 2: mcount_exit | ||
| 179 | .endm | ||
| 180 | |||
| 181 | .macro __ftrace_caller suffix | ||
| 182 | mcount_enter | ||
| 183 | |||
| 184 | mcount_get_lr r1 @ lr of instrumented func | ||
| 185 | mov r0, lr @ instrumented function | ||
| 160 | sub r0, r0, #MCOUNT_INSN_SIZE | 186 | sub r0, r0, #MCOUNT_INSN_SIZE |
| 161 | ldr r1, [sp, #20] | ||
| 162 | 187 | ||
| 163 | .global ftrace_call | 188 | .globl ftrace_call\suffix |
| 164 | ftrace_call: | 189 | ftrace_call\suffix: |
| 165 | bl ftrace_stub | 190 | bl ftrace_stub |
| 166 | ldmia sp!, {r0-r3, ip, lr} | 191 | |
| 167 | mov pc, ip | 192 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
| 168 | ENDPROC(ftrace_caller) | 193 | .globl ftrace_graph_call\suffix |
| 194 | ftrace_graph_call\suffix: | ||
| 195 | mov r0, r0 | ||
| 196 | #endif | ||
| 197 | |||
| 198 | mcount_exit | ||
| 199 | .endm | ||
| 200 | |||
| 201 | .macro __ftrace_graph_caller | ||
| 202 | sub r0, fp, #4 @ &lr of instrumented routine (&parent) | ||
| 203 | #ifdef CONFIG_DYNAMIC_FTRACE | ||
| 204 | @ called from __ftrace_caller, saved in mcount_enter | ||
| 205 | ldr r1, [sp, #16] @ instrumented routine (func) | ||
| 206 | #else | ||
| 207 | @ called from __mcount, untouched in lr | ||
| 208 | mov r1, lr @ instrumented routine (func) | ||
| 209 | #endif | ||
| 210 | sub r1, r1, #MCOUNT_INSN_SIZE | ||
| 211 | mov r2, fp @ frame pointer | ||
| 212 | bl prepare_ftrace_return | ||
| 213 | mcount_exit | ||
| 214 | .endm | ||
| 169 | 215 | ||
| 170 | #ifdef CONFIG_OLD_MCOUNT | 216 | #ifdef CONFIG_OLD_MCOUNT |
| 217 | /* | ||
| 218 | * mcount | ||
| 219 | */ | ||
| 220 | |||
| 221 | .macro mcount_enter | ||
| 222 | stmdb sp!, {r0-r3, lr} | ||
| 223 | .endm | ||
| 224 | |||
| 225 | .macro mcount_get_lr reg | ||
| 226 | ldr \reg, [fp, #-4] | ||
| 227 | .endm | ||
| 228 | |||
| 229 | .macro mcount_exit | ||
| 230 | ldr lr, [fp, #-4] | ||
| 231 | ldmia sp!, {r0-r3, pc} | ||
| 232 | .endm | ||
| 233 | |||
| 171 | ENTRY(mcount) | 234 | ENTRY(mcount) |
| 235 | #ifdef CONFIG_DYNAMIC_FTRACE | ||
| 172 | stmdb sp!, {lr} | 236 | stmdb sp!, {lr} |
| 173 | ldr lr, [fp, #-4] | 237 | ldr lr, [fp, #-4] |
| 174 | ldmia sp!, {pc} | 238 | ldmia sp!, {pc} |
| 239 | #else | ||
| 240 | __mcount _old | ||
| 241 | #endif | ||
| 175 | ENDPROC(mcount) | 242 | ENDPROC(mcount) |
| 176 | 243 | ||
| 244 | #ifdef CONFIG_DYNAMIC_FTRACE | ||
| 177 | ENTRY(ftrace_caller_old) | 245 | ENTRY(ftrace_caller_old) |
| 178 | stmdb sp!, {r0-r3, lr} | 246 | __ftrace_caller _old |
| 179 | ldr r1, [fp, #-4] | ||
| 180 | mov r0, lr | ||
| 181 | sub r0, r0, #MCOUNT_INSN_SIZE | ||
| 182 | |||
| 183 | .globl ftrace_call_old | ||
| 184 | ftrace_call_old: | ||
| 185 | bl ftrace_stub | ||
| 186 | ldr lr, [fp, #-4] @ restore lr | ||
| 187 | ldmia sp!, {r0-r3, pc} | ||
| 188 | ENDPROC(ftrace_caller_old) | 247 | ENDPROC(ftrace_caller_old) |
| 189 | #endif | 248 | #endif |
| 190 | 249 | ||
| 191 | #else | 250 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
| 251 | ENTRY(ftrace_graph_caller_old) | ||
| 252 | __ftrace_graph_caller | ||
| 253 | ENDPROC(ftrace_graph_caller_old) | ||
| 254 | #endif | ||
| 192 | 255 | ||
| 193 | ENTRY(__gnu_mcount_nc) | 256 | .purgem mcount_enter |
| 257 | .purgem mcount_get_lr | ||
| 258 | .purgem mcount_exit | ||
| 259 | #endif | ||
| 260 | |||
| 261 | /* | ||
| 262 | * __gnu_mcount_nc | ||
| 263 | */ | ||
| 264 | |||
| 265 | .macro mcount_enter | ||
| 194 | stmdb sp!, {r0-r3, lr} | 266 | stmdb sp!, {r0-r3, lr} |
| 195 | ldr r0, =ftrace_trace_function | 267 | .endm |
| 196 | ldr r2, [r0] | 268 | |
| 197 | adr r0, .Lftrace_stub | 269 | .macro mcount_get_lr reg |
| 198 | cmp r0, r2 | 270 | ldr \reg, [sp, #20] |
| 199 | bne gnu_trace | 271 | .endm |
| 272 | |||
| 273 | .macro mcount_exit | ||
| 200 | ldmia sp!, {r0-r3, ip, lr} | 274 | ldmia sp!, {r0-r3, ip, lr} |
| 201 | mov pc, ip | 275 | mov pc, ip |
| 276 | .endm | ||
| 202 | 277 | ||
| 203 | gnu_trace: | 278 | ENTRY(__gnu_mcount_nc) |
| 204 | ldr r1, [sp, #20] @ lr of instrumented routine | 279 | #ifdef CONFIG_DYNAMIC_FTRACE |
| 205 | mov r0, lr | 280 | mov ip, lr |
| 206 | sub r0, r0, #MCOUNT_INSN_SIZE | 281 | ldmia sp!, {lr} |
| 207 | adr lr, BSYM(1f) | ||
| 208 | mov pc, r2 | ||
| 209 | 1: | ||
| 210 | ldmia sp!, {r0-r3, ip, lr} | ||
| 211 | mov pc, ip | 282 | mov pc, ip |
| 283 | #else | ||
| 284 | __mcount | ||
| 285 | #endif | ||
| 212 | ENDPROC(__gnu_mcount_nc) | 286 | ENDPROC(__gnu_mcount_nc) |
| 213 | 287 | ||
| 214 | #ifdef CONFIG_OLD_MCOUNT | 288 | #ifdef CONFIG_DYNAMIC_FTRACE |
| 215 | /* | 289 | ENTRY(ftrace_caller) |
| 216 | * This is under an ifdef in order to force link-time errors for people trying | 290 | __ftrace_caller |
| 217 | * to build with !FRAME_POINTER with a GCC which doesn't use the new-style | 291 | ENDPROC(ftrace_caller) |
| 218 | * mcount. | 292 | #endif |
| 219 | */ | ||
| 220 | ENTRY(mcount) | ||
| 221 | stmdb sp!, {r0-r3, lr} | ||
| 222 | ldr r0, =ftrace_trace_function | ||
| 223 | ldr r2, [r0] | ||
| 224 | adr r0, ftrace_stub | ||
| 225 | cmp r0, r2 | ||
| 226 | bne trace | ||
| 227 | ldr lr, [fp, #-4] @ restore lr | ||
| 228 | ldmia sp!, {r0-r3, pc} | ||
| 229 | 293 | ||
| 230 | trace: | 294 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
| 231 | ldr r1, [fp, #-4] @ lr of instrumented routine | 295 | ENTRY(ftrace_graph_caller) |
| 232 | mov r0, lr | 296 | __ftrace_graph_caller |
| 233 | sub r0, r0, #MCOUNT_INSN_SIZE | 297 | ENDPROC(ftrace_graph_caller) |
| 234 | mov lr, pc | ||
| 235 | mov pc, r2 | ||
| 236 | ldr lr, [fp, #-4] @ restore lr | ||
| 237 | ldmia sp!, {r0-r3, pc} | ||
| 238 | ENDPROC(mcount) | ||
| 239 | #endif | 298 | #endif |
| 240 | 299 | ||
| 241 | #endif /* CONFIG_DYNAMIC_FTRACE */ | 300 | .purgem mcount_enter |
| 301 | .purgem mcount_get_lr | ||
| 302 | .purgem mcount_exit | ||
| 303 | |||
| 304 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER | ||
| 305 | .globl return_to_handler | ||
| 306 | return_to_handler: | ||
| 307 | stmdb sp!, {r0-r3} | ||
| 308 | mov r0, fp @ frame pointer | ||
| 309 | bl ftrace_return_to_handler | ||
| 310 | mov lr, r0 @ r0 has real ret addr | ||
| 311 | ldmia sp!, {r0-r3} | ||
| 312 | mov pc, lr | ||
| 313 | #endif | ||
| 242 | 314 | ||
| 243 | ENTRY(ftrace_stub) | 315 | ENTRY(ftrace_stub) |
| 244 | .Lftrace_stub: | 316 | .Lftrace_stub: |
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S index d93f976fb389..ae9464900168 100644 --- a/arch/arm/kernel/entry-header.S +++ b/arch/arm/kernel/entry-header.S | |||
| @@ -165,6 +165,25 @@ | |||
| 165 | .endm | 165 | .endm |
| 166 | #endif /* !CONFIG_THUMB2_KERNEL */ | 166 | #endif /* !CONFIG_THUMB2_KERNEL */ |
| 167 | 167 | ||
| 168 | @ | ||
| 169 | @ Debug exceptions are taken as prefetch or data aborts. | ||
| 170 | @ We must disable preemption during the handler so that | ||
| 171 | @ we can access the debug registers safely. | ||
| 172 | @ | ||
| 173 | .macro debug_entry, fsr | ||
| 174 | #if defined(CONFIG_HAVE_HW_BREAKPOINT) && defined(CONFIG_PREEMPT) | ||
| 175 | ldr r4, =0x40f @ mask out fsr.fs | ||
| 176 | and r5, r4, \fsr | ||
| 177 | cmp r5, #2 @ debug exception | ||
| 178 | bne 1f | ||
| 179 | get_thread_info r10 | ||
| 180 | ldr r6, [r10, #TI_PREEMPT] @ get preempt count | ||
| 181 | add r11, r6, #1 @ increment it | ||
| 182 | str r11, [r10, #TI_PREEMPT] | ||
| 183 | 1: | ||
| 184 | #endif | ||
| 185 | .endm | ||
| 186 | |||
| 168 | /* | 187 | /* |
| 169 | * These are the registers used in the syscall handler, and allow us to | 188 | * These are the registers used in the syscall handler, and allow us to |
| 170 | * have in theory up to 7 arguments to a function - r0 to r6. | 189 | * have in theory up to 7 arguments to a function - r0 to r6. |
diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c index 6ff7919613d7..e72dc34eea1c 100644 --- a/arch/arm/kernel/fiq.c +++ b/arch/arm/kernel/fiq.c | |||
| @@ -45,6 +45,7 @@ | |||
| 45 | #include <asm/fiq.h> | 45 | #include <asm/fiq.h> |
| 46 | #include <asm/irq.h> | 46 | #include <asm/irq.h> |
| 47 | #include <asm/system.h> | 47 | #include <asm/system.h> |
| 48 | #include <asm/traps.h> | ||
| 48 | 49 | ||
| 49 | static unsigned long no_fiq_insn; | 50 | static unsigned long no_fiq_insn; |
| 50 | 51 | ||
| @@ -67,17 +68,22 @@ static struct fiq_handler default_owner = { | |||
| 67 | 68 | ||
| 68 | static struct fiq_handler *current_fiq = &default_owner; | 69 | static struct fiq_handler *current_fiq = &default_owner; |
| 69 | 70 | ||
| 70 | int show_fiq_list(struct seq_file *p, void *v) | 71 | int show_fiq_list(struct seq_file *p, int prec) |
| 71 | { | 72 | { |
| 72 | if (current_fiq != &default_owner) | 73 | if (current_fiq != &default_owner) |
| 73 | seq_printf(p, "FIQ: %s\n", current_fiq->name); | 74 | seq_printf(p, "%*s: %s\n", prec, "FIQ", |
| 75 | current_fiq->name); | ||
| 74 | 76 | ||
| 75 | return 0; | 77 | return 0; |
| 76 | } | 78 | } |
| 77 | 79 | ||
| 78 | void set_fiq_handler(void *start, unsigned int length) | 80 | void set_fiq_handler(void *start, unsigned int length) |
| 79 | { | 81 | { |
| 82 | #if defined(CONFIG_CPU_USE_DOMAINS) | ||
| 80 | memcpy((void *)0xffff001c, start, length); | 83 | memcpy((void *)0xffff001c, start, length); |
| 84 | #else | ||
| 85 | memcpy(vectors_page + 0x1c, start, length); | ||
| 86 | #endif | ||
| 81 | flush_icache_range(0xffff001c, 0xffff001c + length); | 87 | flush_icache_range(0xffff001c, 0xffff001c + length); |
| 82 | if (!vectors_high()) | 88 | if (!vectors_high()) |
| 83 | flush_icache_range(0x1c, 0x1c + length); | 89 | flush_icache_range(0x1c, 0x1c + length); |
diff --git a/arch/arm/kernel/ftrace.c b/arch/arm/kernel/ftrace.c index 971ac8c36ea7..c0062ad1e847 100644 --- a/arch/arm/kernel/ftrace.c +++ b/arch/arm/kernel/ftrace.c | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | #define NOP 0xe8bd4000 /* pop {lr} */ | 24 | #define NOP 0xe8bd4000 /* pop {lr} */ |
| 25 | #endif | 25 | #endif |
| 26 | 26 | ||
| 27 | #ifdef CONFIG_DYNAMIC_FTRACE | ||
| 27 | #ifdef CONFIG_OLD_MCOUNT | 28 | #ifdef CONFIG_OLD_MCOUNT |
| 28 | #define OLD_MCOUNT_ADDR ((unsigned long) mcount) | 29 | #define OLD_MCOUNT_ADDR ((unsigned long) mcount) |
| 29 | #define OLD_FTRACE_ADDR ((unsigned long) ftrace_caller_old) | 30 | #define OLD_FTRACE_ADDR ((unsigned long) ftrace_caller_old) |
| @@ -59,9 +60,9 @@ static unsigned long adjust_address(struct dyn_ftrace *rec, unsigned long addr) | |||
| 59 | } | 60 | } |
| 60 | #endif | 61 | #endif |
| 61 | 62 | ||
| 62 | /* construct a branch (BL) instruction to addr */ | ||
| 63 | #ifdef CONFIG_THUMB2_KERNEL | 63 | #ifdef CONFIG_THUMB2_KERNEL |
| 64 | static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr) | 64 | static unsigned long ftrace_gen_branch(unsigned long pc, unsigned long addr, |
| 65 | bool link) | ||
| 65 | { | 66 | { |
| 66 | unsigned long s, j1, j2, i1, i2, imm10, imm11; | 67 | unsigned long s, j1, j2, i1, i2, imm10, imm11; |
| 67 | unsigned long first, second; | 68 | unsigned long first, second; |
| @@ -83,15 +84,22 @@ static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr) | |||
| 83 | j2 = (!i2) ^ s; | 84 | j2 = (!i2) ^ s; |
| 84 | 85 | ||
| 85 | first = 0xf000 | (s << 10) | imm10; | 86 | first = 0xf000 | (s << 10) | imm10; |
| 86 | second = 0xd000 | (j1 << 13) | (j2 << 11) | imm11; | 87 | second = 0x9000 | (j1 << 13) | (j2 << 11) | imm11; |
| 88 | if (link) | ||
| 89 | second |= 1 << 14; | ||
| 87 | 90 | ||
| 88 | return (second << 16) | first; | 91 | return (second << 16) | first; |
| 89 | } | 92 | } |
| 90 | #else | 93 | #else |
| 91 | static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr) | 94 | static unsigned long ftrace_gen_branch(unsigned long pc, unsigned long addr, |
| 95 | bool link) | ||
| 92 | { | 96 | { |
| 97 | unsigned long opcode = 0xea000000; | ||
| 93 | long offset; | 98 | long offset; |
| 94 | 99 | ||
| 100 | if (link) | ||
| 101 | opcode |= 1 << 24; | ||
| 102 | |||
| 95 | offset = (long)addr - (long)(pc + 8); | 103 | offset = (long)addr - (long)(pc + 8); |
| 96 | if (unlikely(offset < -33554432 || offset > 33554428)) { | 104 | if (unlikely(offset < -33554432 || offset > 33554428)) { |
| 97 | /* Can't generate branches that far (from ARM ARM). Ftrace | 105 | /* Can't generate branches that far (from ARM ARM). Ftrace |
| @@ -103,10 +111,15 @@ static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr) | |||
| 103 | 111 | ||
| 104 | offset = (offset >> 2) & 0x00ffffff; | 112 | offset = (offset >> 2) & 0x00ffffff; |
| 105 | 113 | ||
| 106 | return 0xeb000000 | offset; | 114 | return opcode | offset; |
| 107 | } | 115 | } |
| 108 | #endif | 116 | #endif |
| 109 | 117 | ||
| 118 | static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr) | ||
| 119 | { | ||
| 120 | return ftrace_gen_branch(pc, addr, true); | ||
| 121 | } | ||
| 122 | |||
| 110 | static int ftrace_modify_code(unsigned long pc, unsigned long old, | 123 | static int ftrace_modify_code(unsigned long pc, unsigned long old, |
| 111 | unsigned long new) | 124 | unsigned long new) |
| 112 | { | 125 | { |
| @@ -193,3 +206,83 @@ int __init ftrace_dyn_arch_init(void *data) | |||
| 193 | 206 | ||
| 194 | return 0; | 207 | return 0; |
| 195 | } | 208 | } |
| 209 | #endif /* CONFIG_DYNAMIC_FTRACE */ | ||
| 210 | |||
| 211 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER | ||
| 212 | void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr, | ||
| 213 | unsigned long frame_pointer) | ||
| 214 | { | ||
| 215 | unsigned long return_hooker = (unsigned long) &return_to_handler; | ||
| 216 | struct ftrace_graph_ent trace; | ||
| 217 | unsigned long old; | ||
| 218 | int err; | ||
| 219 | |||
| 220 | if (unlikely(atomic_read(¤t->tracing_graph_pause))) | ||
| 221 | return; | ||
| 222 | |||
| 223 | old = *parent; | ||
| 224 | *parent = return_hooker; | ||
| 225 | |||
| 226 | err = ftrace_push_return_trace(old, self_addr, &trace.depth, | ||
| 227 | frame_pointer); | ||
| 228 | if (err == -EBUSY) { | ||
| 229 | *parent = old; | ||
| 230 | return; | ||
| 231 | } | ||
| 232 | |||
| 233 | trace.func = self_addr; | ||
| 234 | |||
| 235 | /* Only trace if the calling function expects to */ | ||
| 236 | if (!ftrace_graph_entry(&trace)) { | ||
| 237 | current->curr_ret_stack--; | ||
| 238 | *parent = old; | ||
| 239 | } | ||
| 240 | } | ||
| 241 | |||
| 242 | #ifdef CONFIG_DYNAMIC_FTRACE | ||
| 243 | extern unsigned long ftrace_graph_call; | ||
| 244 | extern unsigned long ftrace_graph_call_old; | ||
| 245 | extern void ftrace_graph_caller_old(void); | ||
| 246 | |||
| 247 | static int __ftrace_modify_caller(unsigned long *callsite, | ||
| 248 | void (*func) (void), bool enable) | ||
| 249 | { | ||
| 250 | unsigned long caller_fn = (unsigned long) func; | ||
| 251 | unsigned long pc = (unsigned long) callsite; | ||
| 252 | unsigned long branch = ftrace_gen_branch(pc, caller_fn, false); | ||
| 253 | unsigned long nop = 0xe1a00000; /* mov r0, r0 */ | ||
| 254 | unsigned long old = enable ? nop : branch; | ||
| 255 | unsigned long new = enable ? branch : nop; | ||
| 256 | |||
| 257 | return ftrace_modify_code(pc, old, new); | ||
| 258 | } | ||
| 259 | |||
| 260 | static int ftrace_modify_graph_caller(bool enable) | ||
| 261 | { | ||
| 262 | int ret; | ||
| 263 | |||
| 264 | ret = __ftrace_modify_caller(&ftrace_graph_call, | ||
| 265 | ftrace_graph_caller, | ||
| 266 | enable); | ||
| 267 | |||
| 268 | #ifdef CONFIG_OLD_MCOUNT | ||
| 269 | if (!ret) | ||
| 270 | ret = __ftrace_modify_caller(&ftrace_graph_call_old, | ||
| 271 | ftrace_graph_caller_old, | ||
| 272 | enable); | ||
| 273 | #endif | ||
| 274 | |||
| 275 | return ret; | ||
| 276 | } | ||
| 277 | |||
| 278 | int ftrace_enable_ftrace_graph_caller(void) | ||
| 279 | { | ||
| 280 | return ftrace_modify_graph_caller(true); | ||
| 281 | } | ||
| 282 | |||
| 283 | int ftrace_disable_ftrace_graph_caller(void) | ||
| 284 | { | ||
| 285 | return ftrace_modify_graph_caller(false); | ||
| 286 | } | ||
| 287 | #endif /* CONFIG_DYNAMIC_FTRACE */ | ||
| 288 | #endif /* CONFIG_FUNCTION_GRAPH_TRACER */ | ||
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 6bd82d25683c..f17d9a09e8fb 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S | |||
| @@ -91,6 +91,11 @@ ENTRY(stext) | |||
| 91 | movs r8, r5 @ invalid machine (r5=0)? | 91 | movs r8, r5 @ invalid machine (r5=0)? |
| 92 | THUMB( it eq ) @ force fixup-able long branch encoding | 92 | THUMB( it eq ) @ force fixup-able long branch encoding |
| 93 | beq __error_a @ yes, error 'a' | 93 | beq __error_a @ yes, error 'a' |
| 94 | |||
| 95 | /* | ||
| 96 | * r1 = machine no, r2 = atags, | ||
| 97 | * r8 = machinfo, r9 = cpuid, r10 = procinfo | ||
| 98 | */ | ||
| 94 | bl __vet_atags | 99 | bl __vet_atags |
| 95 | #ifdef CONFIG_SMP_ON_UP | 100 | #ifdef CONFIG_SMP_ON_UP |
| 96 | bl __fixup_smp | 101 | bl __fixup_smp |
| @@ -387,19 +392,19 @@ ENDPROC(__turn_mmu_on) | |||
| 387 | 392 | ||
| 388 | #ifdef CONFIG_SMP_ON_UP | 393 | #ifdef CONFIG_SMP_ON_UP |
| 389 | __fixup_smp: | 394 | __fixup_smp: |
| 390 | mov r7, #0x00070000 | 395 | mov r4, #0x00070000 |
| 391 | orr r6, r7, #0xff000000 @ mask 0xff070000 | 396 | orr r3, r4, #0xff000000 @ mask 0xff070000 |
| 392 | orr r7, r7, #0x41000000 @ val 0x41070000 | 397 | orr r4, r4, #0x41000000 @ val 0x41070000 |
| 393 | and r0, r9, r6 | 398 | and r0, r9, r3 |
| 394 | teq r0, r7 @ ARM CPU and ARMv6/v7? | 399 | teq r0, r4 @ ARM CPU and ARMv6/v7? |
| 395 | bne __fixup_smp_on_up @ no, assume UP | 400 | bne __fixup_smp_on_up @ no, assume UP |
| 396 | 401 | ||
| 397 | orr r6, r6, #0x0000ff00 | 402 | orr r3, r3, #0x0000ff00 |
| 398 | orr r6, r6, #0x000000f0 @ mask 0xff07fff0 | 403 | orr r3, r3, #0x000000f0 @ mask 0xff07fff0 |
| 399 | orr r7, r7, #0x0000b000 | 404 | orr r4, r4, #0x0000b000 |
| 400 | orr r7, r7, #0x00000020 @ val 0x4107b020 | 405 | orr r4, r4, #0x00000020 @ val 0x4107b020 |
| 401 | and r0, r9, r6 | 406 | and r0, r9, r3 |
| 402 | teq r0, r7 @ ARM 11MPCore? | 407 | teq r0, r4 @ ARM 11MPCore? |
| 403 | moveq pc, lr @ yes, assume SMP | 408 | moveq pc, lr @ yes, assume SMP |
| 404 | 409 | ||
| 405 | mrc p15, 0, r0, c0, c0, 5 @ read MPIDR | 410 | mrc p15, 0, r0, c0, c0, 5 @ read MPIDR |
| @@ -408,15 +413,22 @@ __fixup_smp: | |||
| 408 | 413 | ||
| 409 | __fixup_smp_on_up: | 414 | __fixup_smp_on_up: |
| 410 | adr r0, 1f | 415 | adr r0, 1f |
| 411 | ldmia r0, {r3, r6, r7} | 416 | ldmia r0, {r3 - r5} |
| 412 | sub r3, r0, r3 | 417 | sub r3, r0, r3 |
| 413 | add r6, r6, r3 | 418 | add r4, r4, r3 |
| 414 | add r7, r7, r3 | 419 | add r5, r5, r3 |
| 415 | 2: cmp r6, r7 | 420 | 2: cmp r4, r5 |
| 416 | ldmia r6!, {r0, r4} | 421 | movhs pc, lr |
| 417 | strlo r4, [r0, r3] | 422 | ldmia r4!, {r0, r6} |
| 418 | blo 2b | 423 | ARM( str r6, [r0, r3] ) |
| 419 | mov pc, lr | 424 | THUMB( add r0, r0, r3 ) |
| 425 | #ifdef __ARMEB__ | ||
| 426 | THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian. | ||
| 427 | #endif | ||
| 428 | THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords | ||
| 429 | THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3. | ||
| 430 | THUMB( strh r6, [r0] ) | ||
| 431 | b 2b | ||
| 420 | ENDPROC(__fixup_smp) | 432 | ENDPROC(__fixup_smp) |
| 421 | 433 | ||
| 422 | .align | 434 | .align |
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c index 21e3a4ab3b8c..c9f3f0467570 100644 --- a/arch/arm/kernel/hw_breakpoint.c +++ b/arch/arm/kernel/hw_breakpoint.c | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | #define pr_fmt(fmt) "hw-breakpoint: " fmt | 24 | #define pr_fmt(fmt) "hw-breakpoint: " fmt |
| 25 | 25 | ||
| 26 | #include <linux/errno.h> | 26 | #include <linux/errno.h> |
| 27 | #include <linux/hardirq.h> | ||
| 27 | #include <linux/perf_event.h> | 28 | #include <linux/perf_event.h> |
| 28 | #include <linux/hw_breakpoint.h> | 29 | #include <linux/hw_breakpoint.h> |
| 29 | #include <linux/smp.h> | 30 | #include <linux/smp.h> |
| @@ -44,6 +45,7 @@ static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]); | |||
| 44 | 45 | ||
| 45 | /* Number of BRP/WRP registers on this CPU. */ | 46 | /* Number of BRP/WRP registers on this CPU. */ |
| 46 | static int core_num_brps; | 47 | static int core_num_brps; |
| 48 | static int core_num_reserved_brps; | ||
| 47 | static int core_num_wrps; | 49 | static int core_num_wrps; |
| 48 | 50 | ||
| 49 | /* Debug architecture version. */ | 51 | /* Debug architecture version. */ |
| @@ -52,87 +54,6 @@ static u8 debug_arch; | |||
| 52 | /* Maximum supported watchpoint length. */ | 54 | /* Maximum supported watchpoint length. */ |
| 53 | static u8 max_watchpoint_len; | 55 | static u8 max_watchpoint_len; |
| 54 | 56 | ||
| 55 | /* Determine number of BRP registers available. */ | ||
| 56 | static int get_num_brps(void) | ||
| 57 | { | ||
| 58 | u32 didr; | ||
| 59 | ARM_DBG_READ(c0, 0, didr); | ||
| 60 | return ((didr >> 24) & 0xf) + 1; | ||
| 61 | } | ||
| 62 | |||
| 63 | /* Determine number of WRP registers available. */ | ||
| 64 | static int get_num_wrps(void) | ||
| 65 | { | ||
| 66 | /* | ||
| 67 | * FIXME: When a watchpoint fires, the only way to work out which | ||
| 68 | * watchpoint it was is by disassembling the faulting instruction | ||
| 69 | * and working out the address of the memory access. | ||
| 70 | * | ||
| 71 | * Furthermore, we can only do this if the watchpoint was precise | ||
| 72 | * since imprecise watchpoints prevent us from calculating register | ||
| 73 | * based addresses. | ||
| 74 | * | ||
| 75 | * For the time being, we only report 1 watchpoint register so we | ||
| 76 | * always know which watchpoint fired. In the future we can either | ||
| 77 | * add a disassembler and address generation emulator, or we can | ||
| 78 | * insert a check to see if the DFAR is set on watchpoint exception | ||
| 79 | * entry [the ARM ARM states that the DFAR is UNKNOWN, but | ||
| 80 | * experience shows that it is set on some implementations]. | ||
| 81 | */ | ||
| 82 | |||
| 83 | #if 0 | ||
| 84 | u32 didr, wrps; | ||
| 85 | ARM_DBG_READ(c0, 0, didr); | ||
| 86 | return ((didr >> 28) & 0xf) + 1; | ||
| 87 | #endif | ||
| 88 | |||
| 89 | return 1; | ||
| 90 | } | ||
| 91 | |||
| 92 | int hw_breakpoint_slots(int type) | ||
| 93 | { | ||
| 94 | /* | ||
| 95 | * We can be called early, so don't rely on | ||
| 96 | * our static variables being initialised. | ||
| 97 | */ | ||
| 98 | switch (type) { | ||
| 99 | case TYPE_INST: | ||
| 100 | return get_num_brps(); | ||
| 101 | case TYPE_DATA: | ||
| 102 | return get_num_wrps(); | ||
| 103 | default: | ||
| 104 | pr_warning("unknown slot type: %d\n", type); | ||
| 105 | return 0; | ||
| 106 | } | ||
| 107 | } | ||
| 108 | |||
| 109 | /* Determine debug architecture. */ | ||
| 110 | static u8 get_debug_arch(void) | ||
| 111 | { | ||
| 112 | u32 didr; | ||
| 113 | |||
| 114 | /* Do we implement the extended CPUID interface? */ | ||
| 115 | if (((read_cpuid_id() >> 16) & 0xf) != 0xf) { | ||
| 116 | pr_warning("CPUID feature registers not supported. " | ||
| 117 | "Assuming v6 debug is present.\n"); | ||
| 118 | return ARM_DEBUG_ARCH_V6; | ||
| 119 | } | ||
| 120 | |||
| 121 | ARM_DBG_READ(c0, 0, didr); | ||
| 122 | return (didr >> 16) & 0xf; | ||
| 123 | } | ||
| 124 | |||
| 125 | /* Does this core support mismatch breakpoints? */ | ||
| 126 | static int core_has_mismatch_bps(void) | ||
| 127 | { | ||
| 128 | return debug_arch >= ARM_DEBUG_ARCH_V7_ECP14 && core_num_brps > 1; | ||
| 129 | } | ||
| 130 | |||
| 131 | u8 arch_get_debug_arch(void) | ||
| 132 | { | ||
| 133 | return debug_arch; | ||
| 134 | } | ||
| 135 | |||
| 136 | #define READ_WB_REG_CASE(OP2, M, VAL) \ | 57 | #define READ_WB_REG_CASE(OP2, M, VAL) \ |
| 137 | case ((OP2 << 4) + M): \ | 58 | case ((OP2 << 4) + M): \ |
| 138 | ARM_DBG_READ(c ## M, OP2, VAL); \ | 59 | ARM_DBG_READ(c ## M, OP2, VAL); \ |
| @@ -210,6 +131,94 @@ static void write_wb_reg(int n, u32 val) | |||
| 210 | isb(); | 131 | isb(); |
| 211 | } | 132 | } |
| 212 | 133 | ||
| 134 | /* Determine debug architecture. */ | ||
| 135 | static u8 get_debug_arch(void) | ||
| 136 | { | ||
| 137 | u32 didr; | ||
| 138 | |||
| 139 | /* Do we implement the extended CPUID interface? */ | ||
| 140 | if (((read_cpuid_id() >> 16) & 0xf) != 0xf) { | ||
| 141 | pr_warning("CPUID feature registers not supported. " | ||
| 142 | "Assuming v6 debug is present.\n"); | ||
| 143 | return ARM_DEBUG_ARCH_V6; | ||
| 144 | } | ||
| 145 | |||
| 146 | ARM_DBG_READ(c0, 0, didr); | ||
| 147 | return (didr >> 16) & 0xf; | ||
| 148 | } | ||
| 149 | |||
| 150 | u8 arch_get_debug_arch(void) | ||
| 151 | { | ||
| 152 | return debug_arch; | ||
| 153 | } | ||
| 154 | |||
| 155 | /* Determine number of BRP register available. */ | ||
| 156 | static int get_num_brp_resources(void) | ||
| 157 | { | ||
| 158 | u32 didr; | ||
| 159 | ARM_DBG_READ(c0, 0, didr); | ||
| 160 | return ((didr >> 24) & 0xf) + 1; | ||
| 161 | } | ||
| 162 | |||
| 163 | /* Does this core support mismatch breakpoints? */ | ||
| 164 | static int core_has_mismatch_brps(void) | ||
| 165 | { | ||
| 166 | return (get_debug_arch() >= ARM_DEBUG_ARCH_V7_ECP14 && | ||
| 167 | get_num_brp_resources() > 1); | ||
| 168 | } | ||
| 169 | |||
| 170 | /* Determine number of usable WRPs available. */ | ||
| 171 | static int get_num_wrps(void) | ||
| 172 | { | ||
| 173 | /* | ||
| 174 | * FIXME: When a watchpoint fires, the only way to work out which | ||
| 175 | * watchpoint it was is by disassembling the faulting instruction | ||
| 176 | * and working out the address of the memory access. | ||
| 177 | * | ||
| 178 | * Furthermore, we can only do this if the watchpoint was precise | ||
| 179 | * since imprecise watchpoints prevent us from calculating register | ||
| 180 | * based addresses. | ||
| 181 | * | ||
| 182 | * Providing we have more than 1 breakpoint register, we only report | ||
| 183 | * a single watchpoint register for the time being. This way, we always | ||
| 184 | * know which watchpoint fired. In the future we can either add a | ||
| 185 | * disassembler and address generation emulator, or we can insert a | ||
| 186 | * check to see if the DFAR is set on watchpoint exception entry | ||
| 187 | * [the ARM ARM states that the DFAR is UNKNOWN, but experience shows | ||
| 188 | * that it is set on some implementations]. | ||
| 189 | */ | ||
| 190 | |||
| 191 | #if 0 | ||
| 192 | int wrps; | ||
| 193 | u32 didr; | ||
| 194 | ARM_DBG_READ(c0, 0, didr); | ||
| 195 | wrps = ((didr >> 28) & 0xf) + 1; | ||
| 196 | #endif | ||
| 197 | int wrps = 1; | ||
| 198 | |||
| 199 | if (core_has_mismatch_brps() && wrps >= get_num_brp_resources()) | ||
| 200 | wrps = get_num_brp_resources() - 1; | ||
| 201 | |||
| 202 | return wrps; | ||
| 203 | } | ||
| 204 | |||
| 205 | /* We reserve one breakpoint for each watchpoint. */ | ||
| 206 | static int get_num_reserved_brps(void) | ||
| 207 | { | ||
| 208 | if (core_has_mismatch_brps()) | ||
| 209 | return get_num_wrps(); | ||
| 210 | return 0; | ||
| 211 | } | ||
| 212 | |||
| 213 | /* Determine number of usable BRPs available. */ | ||
| 214 | static int get_num_brps(void) | ||
| 215 | { | ||
| 216 | int brps = get_num_brp_resources(); | ||
| 217 | if (core_has_mismatch_brps()) | ||
| 218 | brps -= get_num_reserved_brps(); | ||
| 219 | return brps; | ||
| 220 | } | ||
| 221 | |||
| 213 | /* | 222 | /* |
| 214 | * In order to access the breakpoint/watchpoint control registers, | 223 | * In order to access the breakpoint/watchpoint control registers, |
| 215 | * we must be running in debug monitor mode. Unfortunately, we can | 224 | * we must be running in debug monitor mode. Unfortunately, we can |
| @@ -230,8 +239,12 @@ static int enable_monitor_mode(void) | |||
| 230 | goto out; | 239 | goto out; |
| 231 | } | 240 | } |
| 232 | 241 | ||
| 242 | /* If monitor mode is already enabled, just return. */ | ||
| 243 | if (dscr & ARM_DSCR_MDBGEN) | ||
| 244 | goto out; | ||
| 245 | |||
| 233 | /* Write to the corresponding DSCR. */ | 246 | /* Write to the corresponding DSCR. */ |
| 234 | switch (debug_arch) { | 247 | switch (get_debug_arch()) { |
| 235 | case ARM_DEBUG_ARCH_V6: | 248 | case ARM_DEBUG_ARCH_V6: |
| 236 | case ARM_DEBUG_ARCH_V6_1: | 249 | case ARM_DEBUG_ARCH_V6_1: |
| 237 | ARM_DBG_WRITE(c1, 0, (dscr | ARM_DSCR_MDBGEN)); | 250 | ARM_DBG_WRITE(c1, 0, (dscr | ARM_DSCR_MDBGEN)); |
| @@ -246,15 +259,30 @@ static int enable_monitor_mode(void) | |||
| 246 | 259 | ||
| 247 | /* Check that the write made it through. */ | 260 | /* Check that the write made it through. */ |
| 248 | ARM_DBG_READ(c1, 0, dscr); | 261 | ARM_DBG_READ(c1, 0, dscr); |
| 249 | if (WARN_ONCE(!(dscr & ARM_DSCR_MDBGEN), | 262 | if (!(dscr & ARM_DSCR_MDBGEN)) |
| 250 | "failed to enable monitor mode.")) { | ||
| 251 | ret = -EPERM; | 263 | ret = -EPERM; |
| 252 | } | ||
| 253 | 264 | ||
| 254 | out: | 265 | out: |
| 255 | return ret; | 266 | return ret; |
| 256 | } | 267 | } |
| 257 | 268 | ||
| 269 | int hw_breakpoint_slots(int type) | ||
| 270 | { | ||
| 271 | /* | ||
| 272 | * We can be called early, so don't rely on | ||
| 273 | * our static variables being initialised. | ||
| 274 | */ | ||
| 275 | switch (type) { | ||
| 276 | case TYPE_INST: | ||
| 277 | return get_num_brps(); | ||
| 278 | case TYPE_DATA: | ||
| 279 | return get_num_wrps(); | ||
| 280 | default: | ||
| 281 | pr_warning("unknown slot type: %d\n", type); | ||
| 282 | return 0; | ||
| 283 | } | ||
| 284 | } | ||
| 285 | |||
| 258 | /* | 286 | /* |
| 259 | * Check if 8-bit byte-address select is available. | 287 | * Check if 8-bit byte-address select is available. |
| 260 | * This clobbers WRP 0. | 288 | * This clobbers WRP 0. |
| @@ -268,9 +296,6 @@ static u8 get_max_wp_len(void) | |||
| 268 | if (debug_arch < ARM_DEBUG_ARCH_V7_ECP14) | 296 | if (debug_arch < ARM_DEBUG_ARCH_V7_ECP14) |
| 269 | goto out; | 297 | goto out; |
| 270 | 298 | ||
| 271 | if (enable_monitor_mode()) | ||
| 272 | goto out; | ||
| 273 | |||
| 274 | memset(&ctrl, 0, sizeof(ctrl)); | 299 | memset(&ctrl, 0, sizeof(ctrl)); |
| 275 | ctrl.len = ARM_BREAKPOINT_LEN_8; | 300 | ctrl.len = ARM_BREAKPOINT_LEN_8; |
| 276 | ctrl_reg = encode_ctrl_reg(ctrl); | 301 | ctrl_reg = encode_ctrl_reg(ctrl); |
| @@ -290,23 +315,6 @@ u8 arch_get_max_wp_len(void) | |||
| 290 | } | 315 | } |
| 291 | 316 | ||
| 292 | /* | 317 | /* |
| 293 | * Handler for reactivating a suspended watchpoint when the single | ||
| 294 | * step `mismatch' breakpoint is triggered. | ||
| 295 | */ | ||
| 296 | static void wp_single_step_handler(struct perf_event *bp, int unused, | ||
| 297 | struct perf_sample_data *data, | ||
| 298 | struct pt_regs *regs) | ||
| 299 | { | ||
| 300 | perf_event_enable(counter_arch_bp(bp)->suspended_wp); | ||
| 301 | unregister_hw_breakpoint(bp); | ||
| 302 | } | ||
| 303 | |||
| 304 | static int bp_is_single_step(struct perf_event *bp) | ||
| 305 | { | ||
| 306 | return bp->overflow_handler == wp_single_step_handler; | ||
| 307 | } | ||
| 308 | |||
| 309 | /* | ||
| 310 | * Install a perf counter breakpoint. | 318 | * Install a perf counter breakpoint. |
| 311 | */ | 319 | */ |
| 312 | int arch_install_hw_breakpoint(struct perf_event *bp) | 320 | int arch_install_hw_breakpoint(struct perf_event *bp) |
| @@ -314,30 +322,41 @@ int arch_install_hw_breakpoint(struct perf_event *bp) | |||
| 314 | struct arch_hw_breakpoint *info = counter_arch_bp(bp); | 322 | struct arch_hw_breakpoint *info = counter_arch_bp(bp); |
| 315 | struct perf_event **slot, **slots; | 323 | struct perf_event **slot, **slots; |
| 316 | int i, max_slots, ctrl_base, val_base, ret = 0; | 324 | int i, max_slots, ctrl_base, val_base, ret = 0; |
| 325 | u32 addr, ctrl; | ||
| 317 | 326 | ||
| 318 | /* Ensure that we are in monitor mode and halting mode is disabled. */ | 327 | /* Ensure that we are in monitor mode and halting mode is disabled. */ |
| 319 | ret = enable_monitor_mode(); | 328 | ret = enable_monitor_mode(); |
| 320 | if (ret) | 329 | if (ret) |
| 321 | goto out; | 330 | goto out; |
| 322 | 331 | ||
| 332 | addr = info->address; | ||
| 333 | ctrl = encode_ctrl_reg(info->ctrl) | 0x1; | ||
| 334 | |||
| 323 | if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { | 335 | if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { |
| 324 | /* Breakpoint */ | 336 | /* Breakpoint */ |
| 325 | ctrl_base = ARM_BASE_BCR; | 337 | ctrl_base = ARM_BASE_BCR; |
| 326 | val_base = ARM_BASE_BVR; | 338 | val_base = ARM_BASE_BVR; |
| 327 | slots = __get_cpu_var(bp_on_reg); | 339 | slots = (struct perf_event **)__get_cpu_var(bp_on_reg); |
| 328 | max_slots = core_num_brps - 1; | 340 | max_slots = core_num_brps; |
| 329 | 341 | if (info->step_ctrl.enabled) { | |
| 330 | if (bp_is_single_step(bp)) { | 342 | /* Override the breakpoint data with the step data. */ |
| 331 | info->ctrl.mismatch = 1; | 343 | addr = info->trigger & ~0x3; |
| 332 | i = max_slots; | 344 | ctrl = encode_ctrl_reg(info->step_ctrl); |
| 333 | slots[i] = bp; | ||
| 334 | goto setup; | ||
| 335 | } | 345 | } |
| 336 | } else { | 346 | } else { |
| 337 | /* Watchpoint */ | 347 | /* Watchpoint */ |
| 338 | ctrl_base = ARM_BASE_WCR; | 348 | if (info->step_ctrl.enabled) { |
| 339 | val_base = ARM_BASE_WVR; | 349 | /* Install into the reserved breakpoint region. */ |
| 340 | slots = __get_cpu_var(wp_on_reg); | 350 | ctrl_base = ARM_BASE_BCR + core_num_brps; |
| 351 | val_base = ARM_BASE_BVR + core_num_brps; | ||
| 352 | /* Override the watchpoint data with the step data. */ | ||
| 353 | addr = info->trigger & ~0x3; | ||
| 354 | ctrl = encode_ctrl_reg(info->step_ctrl); | ||
| 355 | } else { | ||
| 356 | ctrl_base = ARM_BASE_WCR; | ||
| 357 | val_base = ARM_BASE_WVR; | ||
| 358 | } | ||
| 359 | slots = (struct perf_event **)__get_cpu_var(wp_on_reg); | ||
| 341 | max_slots = core_num_wrps; | 360 | max_slots = core_num_wrps; |
| 342 | } | 361 | } |
| 343 | 362 | ||
| @@ -355,12 +374,11 @@ int arch_install_hw_breakpoint(struct perf_event *bp) | |||
| 355 | goto out; | 374 | goto out; |
| 356 | } | 375 | } |
| 357 | 376 | ||
| 358 | setup: | ||
| 359 | /* Setup the address register. */ | 377 | /* Setup the address register. */ |
| 360 | write_wb_reg(val_base + i, info->address); | 378 | write_wb_reg(val_base + i, addr); |
| 361 | 379 | ||
| 362 | /* Setup the control register. */ | 380 | /* Setup the control register. */ |
| 363 | write_wb_reg(ctrl_base + i, encode_ctrl_reg(info->ctrl) | 0x1); | 381 | write_wb_reg(ctrl_base + i, ctrl); |
| 364 | 382 | ||
| 365 | out: | 383 | out: |
| 366 | return ret; | 384 | return ret; |
| @@ -375,18 +393,15 @@ void arch_uninstall_hw_breakpoint(struct perf_event *bp) | |||
| 375 | if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { | 393 | if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { |
| 376 | /* Breakpoint */ | 394 | /* Breakpoint */ |
| 377 | base = ARM_BASE_BCR; | 395 | base = ARM_BASE_BCR; |
| 378 | slots = __get_cpu_var(bp_on_reg); | 396 | slots = (struct perf_event **)__get_cpu_var(bp_on_reg); |
| 379 | max_slots = core_num_brps - 1; | 397 | max_slots = core_num_brps; |
| 380 | |||
| 381 | if (bp_is_single_step(bp)) { | ||
| 382 | i = max_slots; | ||
| 383 | slots[i] = NULL; | ||
| 384 | goto reset; | ||
| 385 | } | ||
| 386 | } else { | 398 | } else { |
| 387 | /* Watchpoint */ | 399 | /* Watchpoint */ |
| 388 | base = ARM_BASE_WCR; | 400 | if (info->step_ctrl.enabled) |
| 389 | slots = __get_cpu_var(wp_on_reg); | 401 | base = ARM_BASE_BCR + core_num_brps; |
| 402 | else | ||
| 403 | base = ARM_BASE_WCR; | ||
| 404 | slots = (struct perf_event **)__get_cpu_var(wp_on_reg); | ||
| 390 | max_slots = core_num_wrps; | 405 | max_slots = core_num_wrps; |
| 391 | } | 406 | } |
| 392 | 407 | ||
| @@ -403,7 +418,6 @@ void arch_uninstall_hw_breakpoint(struct perf_event *bp) | |||
| 403 | if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot")) | 418 | if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot")) |
| 404 | return; | 419 | return; |
| 405 | 420 | ||
| 406 | reset: | ||
| 407 | /* Reset the control register. */ | 421 | /* Reset the control register. */ |
| 408 | write_wb_reg(base + i, 0); | 422 | write_wb_reg(base + i, 0); |
| 409 | } | 423 | } |
| @@ -537,12 +551,23 @@ static int arch_build_bp_info(struct perf_event *bp) | |||
| 537 | return -EINVAL; | 551 | return -EINVAL; |
| 538 | } | 552 | } |
| 539 | 553 | ||
| 554 | /* | ||
| 555 | * Breakpoints must be of length 2 (thumb) or 4 (ARM) bytes. | ||
| 556 | * Watchpoints can be of length 1, 2, 4 or 8 bytes if supported | ||
| 557 | * by the hardware and must be aligned to the appropriate number of | ||
| 558 | * bytes. | ||
| 559 | */ | ||
| 560 | if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE && | ||
| 561 | info->ctrl.len != ARM_BREAKPOINT_LEN_2 && | ||
| 562 | info->ctrl.len != ARM_BREAKPOINT_LEN_4) | ||
| 563 | return -EINVAL; | ||
| 564 | |||
| 540 | /* Address */ | 565 | /* Address */ |
| 541 | info->address = bp->attr.bp_addr; | 566 | info->address = bp->attr.bp_addr; |
| 542 | 567 | ||
| 543 | /* Privilege */ | 568 | /* Privilege */ |
| 544 | info->ctrl.privilege = ARM_BREAKPOINT_USER; | 569 | info->ctrl.privilege = ARM_BREAKPOINT_USER; |
| 545 | if (arch_check_bp_in_kernelspace(bp) && !bp_is_single_step(bp)) | 570 | if (arch_check_bp_in_kernelspace(bp)) |
| 546 | info->ctrl.privilege |= ARM_BREAKPOINT_PRIV; | 571 | info->ctrl.privilege |= ARM_BREAKPOINT_PRIV; |
| 547 | 572 | ||
| 548 | /* Enabled? */ | 573 | /* Enabled? */ |
| @@ -561,7 +586,7 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp) | |||
| 561 | { | 586 | { |
| 562 | struct arch_hw_breakpoint *info = counter_arch_bp(bp); | 587 | struct arch_hw_breakpoint *info = counter_arch_bp(bp); |
| 563 | int ret = 0; | 588 | int ret = 0; |
| 564 | u32 bytelen, max_len, offset, alignment_mask = 0x3; | 589 | u32 offset, alignment_mask = 0x3; |
| 565 | 590 | ||
| 566 | /* Build the arch_hw_breakpoint. */ | 591 | /* Build the arch_hw_breakpoint. */ |
| 567 | ret = arch_build_bp_info(bp); | 592 | ret = arch_build_bp_info(bp); |
| @@ -571,84 +596,85 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp) | |||
| 571 | /* Check address alignment. */ | 596 | /* Check address alignment. */ |
| 572 | if (info->ctrl.len == ARM_BREAKPOINT_LEN_8) | 597 | if (info->ctrl.len == ARM_BREAKPOINT_LEN_8) |
| 573 | alignment_mask = 0x7; | 598 | alignment_mask = 0x7; |
| 574 | if (info->address & alignment_mask) { | 599 | offset = info->address & alignment_mask; |
| 575 | /* | 600 | switch (offset) { |
| 576 | * Try to fix the alignment. This may result in a length | 601 | case 0: |
| 577 | * that is too large, so we must check for that. | 602 | /* Aligned */ |
| 578 | */ | 603 | break; |
| 579 | bytelen = get_hbp_len(info->ctrl.len); | 604 | case 1: |
| 580 | max_len = info->ctrl.type == ARM_BREAKPOINT_EXECUTE ? 4 : | 605 | /* Allow single byte watchpoint. */ |
| 581 | max_watchpoint_len; | 606 | if (info->ctrl.len == ARM_BREAKPOINT_LEN_1) |
| 582 | 607 | break; | |
| 583 | if (max_len >= 8) | 608 | case 2: |
| 584 | offset = info->address & 0x7; | 609 | /* Allow halfword watchpoints and breakpoints. */ |
| 585 | else | 610 | if (info->ctrl.len == ARM_BREAKPOINT_LEN_2) |
| 586 | offset = info->address & 0x3; | 611 | break; |
| 587 | 612 | default: | |
| 588 | if (bytelen > (1 << ((max_len - (offset + 1)) >> 1))) { | 613 | ret = -EINVAL; |
| 589 | ret = -EFBIG; | 614 | goto out; |
| 590 | goto out; | ||
| 591 | } | ||
| 592 | |||
| 593 | info->ctrl.len <<= offset; | ||
| 594 | info->address &= ~offset; | ||
| 595 | |||
| 596 | pr_debug("breakpoint alignment fixup: length = 0x%x, " | ||
| 597 | "address = 0x%x\n", info->ctrl.len, info->address); | ||
| 598 | } | 615 | } |
| 599 | 616 | ||
| 617 | info->address &= ~alignment_mask; | ||
| 618 | info->ctrl.len <<= offset; | ||
| 619 | |||
| 600 | /* | 620 | /* |
| 601 | * Currently we rely on an overflow handler to take | 621 | * Currently we rely on an overflow handler to take |
| 602 | * care of single-stepping the breakpoint when it fires. | 622 | * care of single-stepping the breakpoint when it fires. |
| 603 | * In the case of userspace breakpoints on a core with V7 debug, | 623 | * In the case of userspace breakpoints on a core with V7 debug, |
| 604 | * we can use the mismatch feature as a poor-man's hardware single-step. | 624 | * we can use the mismatch feature as a poor-man's hardware |
| 625 | * single-step, but this only works for per-task breakpoints. | ||
| 605 | */ | 626 | */ |
| 606 | if (WARN_ONCE(!bp->overflow_handler && | 627 | if (WARN_ONCE(!bp->overflow_handler && |
| 607 | (arch_check_bp_in_kernelspace(bp) || !core_has_mismatch_bps()), | 628 | (arch_check_bp_in_kernelspace(bp) || !core_has_mismatch_brps() |
| 629 | || !bp->hw.bp_target), | ||
| 608 | "overflow handler required but none found")) { | 630 | "overflow handler required but none found")) { |
| 609 | ret = -EINVAL; | 631 | ret = -EINVAL; |
| 610 | goto out; | ||
| 611 | } | 632 | } |
| 612 | out: | 633 | out: |
| 613 | return ret; | 634 | return ret; |
| 614 | } | 635 | } |
| 615 | 636 | ||
| 616 | static void update_mismatch_flag(int idx, int flag) | 637 | /* |
| 638 | * Enable/disable single-stepping over the breakpoint bp at address addr. | ||
| 639 | */ | ||
| 640 | static void enable_single_step(struct perf_event *bp, u32 addr) | ||
| 617 | { | 641 | { |
| 618 | struct perf_event *bp = __get_cpu_var(bp_on_reg[idx]); | 642 | struct arch_hw_breakpoint *info = counter_arch_bp(bp); |
| 619 | struct arch_hw_breakpoint *info; | ||
| 620 | |||
| 621 | if (bp == NULL) | ||
| 622 | return; | ||
| 623 | 643 | ||
| 624 | info = counter_arch_bp(bp); | 644 | arch_uninstall_hw_breakpoint(bp); |
| 645 | info->step_ctrl.mismatch = 1; | ||
| 646 | info->step_ctrl.len = ARM_BREAKPOINT_LEN_4; | ||
| 647 | info->step_ctrl.type = ARM_BREAKPOINT_EXECUTE; | ||
| 648 | info->step_ctrl.privilege = info->ctrl.privilege; | ||
| 649 | info->step_ctrl.enabled = 1; | ||
| 650 | info->trigger = addr; | ||
| 651 | arch_install_hw_breakpoint(bp); | ||
| 652 | } | ||
| 625 | 653 | ||
| 626 | /* Update the mismatch field to enter/exit `single-step' mode */ | 654 | static void disable_single_step(struct perf_event *bp) |
| 627 | if (!bp->overflow_handler && info->ctrl.mismatch != flag) { | 655 | { |
| 628 | info->ctrl.mismatch = flag; | 656 | arch_uninstall_hw_breakpoint(bp); |
| 629 | write_wb_reg(ARM_BASE_BCR + idx, encode_ctrl_reg(info->ctrl) | 0x1); | 657 | counter_arch_bp(bp)->step_ctrl.enabled = 0; |
| 630 | } | 658 | arch_install_hw_breakpoint(bp); |
| 631 | } | 659 | } |
| 632 | 660 | ||
| 633 | static void watchpoint_handler(unsigned long unknown, struct pt_regs *regs) | 661 | static void watchpoint_handler(unsigned long unknown, struct pt_regs *regs) |
| 634 | { | 662 | { |
| 635 | int i; | 663 | int i; |
| 636 | struct perf_event *bp, **slots = __get_cpu_var(wp_on_reg); | 664 | struct perf_event *wp, **slots; |
| 637 | struct arch_hw_breakpoint *info; | 665 | struct arch_hw_breakpoint *info; |
| 638 | struct perf_event_attr attr; | 666 | |
| 667 | slots = (struct perf_event **)__get_cpu_var(wp_on_reg); | ||
| 639 | 668 | ||
| 640 | /* Without a disassembler, we can only handle 1 watchpoint. */ | 669 | /* Without a disassembler, we can only handle 1 watchpoint. */ |
| 641 | BUG_ON(core_num_wrps > 1); | 670 | BUG_ON(core_num_wrps > 1); |
| 642 | 671 | ||
| 643 | hw_breakpoint_init(&attr); | ||
| 644 | attr.bp_addr = regs->ARM_pc & ~0x3; | ||
| 645 | attr.bp_len = HW_BREAKPOINT_LEN_4; | ||
| 646 | attr.bp_type = HW_BREAKPOINT_X; | ||
| 647 | |||
| 648 | for (i = 0; i < core_num_wrps; ++i) { | 672 | for (i = 0; i < core_num_wrps; ++i) { |
| 649 | rcu_read_lock(); | 673 | rcu_read_lock(); |
| 650 | 674 | ||
| 651 | if (slots[i] == NULL) { | 675 | wp = slots[i]; |
| 676 | |||
| 677 | if (wp == NULL) { | ||
| 652 | rcu_read_unlock(); | 678 | rcu_read_unlock(); |
| 653 | continue; | 679 | continue; |
| 654 | } | 680 | } |
| @@ -658,24 +684,51 @@ static void watchpoint_handler(unsigned long unknown, struct pt_regs *regs) | |||
| 658 | * single watchpoint, we can set the trigger to the lowest | 684 | * single watchpoint, we can set the trigger to the lowest |
| 659 | * possible faulting address. | 685 | * possible faulting address. |
| 660 | */ | 686 | */ |
| 661 | info = counter_arch_bp(slots[i]); | 687 | info = counter_arch_bp(wp); |
| 662 | info->trigger = slots[i]->attr.bp_addr; | 688 | info->trigger = wp->attr.bp_addr; |
| 663 | pr_debug("watchpoint fired: address = 0x%x\n", info->trigger); | 689 | pr_debug("watchpoint fired: address = 0x%x\n", info->trigger); |
| 664 | perf_bp_event(slots[i], regs); | 690 | perf_bp_event(wp, regs); |
| 665 | 691 | ||
| 666 | /* | 692 | /* |
| 667 | * If no overflow handler is present, insert a temporary | 693 | * If no overflow handler is present, insert a temporary |
| 668 | * mismatch breakpoint so we can single-step over the | 694 | * mismatch breakpoint so we can single-step over the |
| 669 | * watchpoint trigger. | 695 | * watchpoint trigger. |
| 670 | */ | 696 | */ |
| 671 | if (!slots[i]->overflow_handler) { | 697 | if (!wp->overflow_handler) |
| 672 | bp = register_user_hw_breakpoint(&attr, | 698 | enable_single_step(wp, instruction_pointer(regs)); |
| 673 | wp_single_step_handler, | 699 | |
| 674 | current); | 700 | rcu_read_unlock(); |
| 675 | counter_arch_bp(bp)->suspended_wp = slots[i]; | 701 | } |
| 676 | perf_event_disable(slots[i]); | 702 | } |
| 677 | } | ||
| 678 | 703 | ||
| 704 | static void watchpoint_single_step_handler(unsigned long pc) | ||
| 705 | { | ||
| 706 | int i; | ||
| 707 | struct perf_event *wp, **slots; | ||
| 708 | struct arch_hw_breakpoint *info; | ||
| 709 | |||
| 710 | slots = (struct perf_event **)__get_cpu_var(wp_on_reg); | ||
| 711 | |||
| 712 | for (i = 0; i < core_num_reserved_brps; ++i) { | ||
| 713 | rcu_read_lock(); | ||
| 714 | |||
| 715 | wp = slots[i]; | ||
| 716 | |||
| 717 | if (wp == NULL) | ||
| 718 | goto unlock; | ||
| 719 | |||
| 720 | info = counter_arch_bp(wp); | ||
| 721 | if (!info->step_ctrl.enabled) | ||
| 722 | goto unlock; | ||
| 723 | |||
| 724 | /* | ||
| 725 | * Restore the original watchpoint if we've completed the | ||
| 726 | * single-step. | ||
| 727 | */ | ||
| 728 | if (info->trigger != pc) | ||
| 729 | disable_single_step(wp); | ||
| 730 | |||
| 731 | unlock: | ||
| 679 | rcu_read_unlock(); | 732 | rcu_read_unlock(); |
| 680 | } | 733 | } |
| 681 | } | 734 | } |
| @@ -683,62 +736,69 @@ static void watchpoint_handler(unsigned long unknown, struct pt_regs *regs) | |||
| 683 | static void breakpoint_handler(unsigned long unknown, struct pt_regs *regs) | 736 | static void breakpoint_handler(unsigned long unknown, struct pt_regs *regs) |
| 684 | { | 737 | { |
| 685 | int i; | 738 | int i; |
| 686 | int mismatch; | ||
| 687 | u32 ctrl_reg, val, addr; | 739 | u32 ctrl_reg, val, addr; |
| 688 | struct perf_event *bp, **slots = __get_cpu_var(bp_on_reg); | 740 | struct perf_event *bp, **slots; |
| 689 | struct arch_hw_breakpoint *info; | 741 | struct arch_hw_breakpoint *info; |
| 690 | struct arch_hw_breakpoint_ctrl ctrl; | 742 | struct arch_hw_breakpoint_ctrl ctrl; |
| 691 | 743 | ||
| 744 | slots = (struct perf_event **)__get_cpu_var(bp_on_reg); | ||
| 745 | |||
| 692 | /* The exception entry code places the amended lr in the PC. */ | 746 | /* The exception entry code places the amended lr in the PC. */ |
| 693 | addr = regs->ARM_pc; | 747 | addr = regs->ARM_pc; |
| 694 | 748 | ||
| 749 | /* Check the currently installed breakpoints first. */ | ||
| 695 | for (i = 0; i < core_num_brps; ++i) { | 750 | for (i = 0; i < core_num_brps; ++i) { |
| 696 | rcu_read_lock(); | 751 | rcu_read_lock(); |
| 697 | 752 | ||
| 698 | bp = slots[i]; | 753 | bp = slots[i]; |
| 699 | 754 | ||
| 700 | if (bp == NULL) { | 755 | if (bp == NULL) |
| 701 | rcu_read_unlock(); | 756 | goto unlock; |
| 702 | continue; | ||
| 703 | } | ||
| 704 | 757 | ||
| 705 | mismatch = 0; | 758 | info = counter_arch_bp(bp); |
| 706 | 759 | ||
| 707 | /* Check if the breakpoint value matches. */ | 760 | /* Check if the breakpoint value matches. */ |
| 708 | val = read_wb_reg(ARM_BASE_BVR + i); | 761 | val = read_wb_reg(ARM_BASE_BVR + i); |
| 709 | if (val != (addr & ~0x3)) | 762 | if (val != (addr & ~0x3)) |
| 710 | goto unlock; | 763 | goto mismatch; |
| 711 | 764 | ||
| 712 | /* Possible match, check the byte address select to confirm. */ | 765 | /* Possible match, check the byte address select to confirm. */ |
| 713 | ctrl_reg = read_wb_reg(ARM_BASE_BCR + i); | 766 | ctrl_reg = read_wb_reg(ARM_BASE_BCR + i); |
| 714 | decode_ctrl_reg(ctrl_reg, &ctrl); | 767 | decode_ctrl_reg(ctrl_reg, &ctrl); |
| 715 | if ((1 << (addr & 0x3)) & ctrl.len) { | 768 | if ((1 << (addr & 0x3)) & ctrl.len) { |
| 716 | mismatch = 1; | ||
| 717 | info = counter_arch_bp(bp); | ||
| 718 | info->trigger = addr; | 769 | info->trigger = addr; |
| 719 | } | ||
| 720 | |||
| 721 | unlock: | ||
| 722 | if ((mismatch && !info->ctrl.mismatch) || bp_is_single_step(bp)) { | ||
| 723 | pr_debug("breakpoint fired: address = 0x%x\n", addr); | 770 | pr_debug("breakpoint fired: address = 0x%x\n", addr); |
| 724 | perf_bp_event(bp, regs); | 771 | perf_bp_event(bp, regs); |
| 772 | if (!bp->overflow_handler) | ||
| 773 | enable_single_step(bp, addr); | ||
| 774 | goto unlock; | ||
| 725 | } | 775 | } |
| 726 | 776 | ||
| 727 | update_mismatch_flag(i, mismatch); | 777 | mismatch: |
| 778 | /* If we're stepping a breakpoint, it can now be restored. */ | ||
| 779 | if (info->step_ctrl.enabled) | ||
| 780 | disable_single_step(bp); | ||
| 781 | unlock: | ||
| 728 | rcu_read_unlock(); | 782 | rcu_read_unlock(); |
| 729 | } | 783 | } |
| 784 | |||
| 785 | /* Handle any pending watchpoint single-step breakpoints. */ | ||
| 786 | watchpoint_single_step_handler(addr); | ||
| 730 | } | 787 | } |
| 731 | 788 | ||
| 732 | /* | 789 | /* |
| 733 | * Called from either the Data Abort Handler [watchpoint] or the | 790 | * Called from either the Data Abort Handler [watchpoint] or the |
| 734 | * Prefetch Abort Handler [breakpoint]. | 791 | * Prefetch Abort Handler [breakpoint] with preemption disabled. |
| 735 | */ | 792 | */ |
| 736 | static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr, | 793 | static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr, |
| 737 | struct pt_regs *regs) | 794 | struct pt_regs *regs) |
| 738 | { | 795 | { |
| 739 | int ret = 1; /* Unhandled fault. */ | 796 | int ret = 0; |
| 740 | u32 dscr; | 797 | u32 dscr; |
| 741 | 798 | ||
| 799 | /* We must be called with preemption disabled. */ | ||
| 800 | WARN_ON(preemptible()); | ||
| 801 | |||
| 742 | /* We only handle watchpoints and hardware breakpoints. */ | 802 | /* We only handle watchpoints and hardware breakpoints. */ |
| 743 | ARM_DBG_READ(c1, 0, dscr); | 803 | ARM_DBG_READ(c1, 0, dscr); |
| 744 | 804 | ||
| @@ -753,25 +813,47 @@ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr, | |||
| 753 | watchpoint_handler(addr, regs); | 813 | watchpoint_handler(addr, regs); |
| 754 | break; | 814 | break; |
| 755 | default: | 815 | default: |
| 756 | goto out; | 816 | ret = 1; /* Unhandled fault. */ |
| 757 | } | 817 | } |
| 758 | 818 | ||
| 759 | ret = 0; | 819 | /* |
| 760 | out: | 820 | * Re-enable preemption after it was disabled in the |
| 821 | * low-level exception handling code. | ||
| 822 | */ | ||
| 823 | preempt_enable(); | ||
| 824 | |||
| 761 | return ret; | 825 | return ret; |
| 762 | } | 826 | } |
| 763 | 827 | ||
| 764 | /* | 828 | /* |
| 765 | * One-time initialisation. | 829 | * One-time initialisation. |
| 766 | */ | 830 | */ |
| 767 | static void __init reset_ctrl_regs(void *unused) | 831 | static void reset_ctrl_regs(void *unused) |
| 768 | { | 832 | { |
| 769 | int i; | 833 | int i; |
| 770 | 834 | ||
| 835 | /* | ||
| 836 | * v7 debug contains save and restore registers so that debug state | ||
| 837 | * can be maintained across low-power modes without leaving | ||
| 838 | * the debug logic powered up. It is IMPLEMENTATION DEFINED whether | ||
| 839 | * we can write to the debug registers out of reset, so we must | ||
| 840 | * unlock the OS Lock Access Register to avoid taking undefined | ||
| 841 | * instruction exceptions later on. | ||
| 842 | */ | ||
| 843 | if (debug_arch >= ARM_DEBUG_ARCH_V7_ECP14) { | ||
| 844 | /* | ||
| 845 | * Unconditionally clear the lock by writing a value | ||
| 846 | * other than 0xC5ACCE55 to the access register. | ||
| 847 | */ | ||
| 848 | asm volatile("mcr p14, 0, %0, c1, c0, 4" : : "r" (0)); | ||
| 849 | isb(); | ||
| 850 | } | ||
| 851 | |||
| 771 | if (enable_monitor_mode()) | 852 | if (enable_monitor_mode()) |
| 772 | return; | 853 | return; |
| 773 | 854 | ||
| 774 | for (i = 0; i < core_num_brps; ++i) { | 855 | /* We must also reset any reserved registers. */ |
| 856 | for (i = 0; i < core_num_brps + core_num_reserved_brps; ++i) { | ||
| 775 | write_wb_reg(ARM_BASE_BCR + i, 0UL); | 857 | write_wb_reg(ARM_BASE_BCR + i, 0UL); |
| 776 | write_wb_reg(ARM_BASE_BVR + i, 0UL); | 858 | write_wb_reg(ARM_BASE_BVR + i, 0UL); |
| 777 | } | 859 | } |
| @@ -782,45 +864,57 @@ static void __init reset_ctrl_regs(void *unused) | |||
| 782 | } | 864 | } |
| 783 | } | 865 | } |
| 784 | 866 | ||
| 867 | static int __cpuinit dbg_reset_notify(struct notifier_block *self, | ||
| 868 | unsigned long action, void *cpu) | ||
| 869 | { | ||
| 870 | if (action == CPU_ONLINE) | ||
| 871 | smp_call_function_single((int)cpu, reset_ctrl_regs, NULL, 1); | ||
| 872 | return NOTIFY_OK; | ||
| 873 | } | ||
| 874 | |||
| 875 | static struct notifier_block __cpuinitdata dbg_reset_nb = { | ||
| 876 | .notifier_call = dbg_reset_notify, | ||
| 877 | }; | ||
| 878 | |||
| 785 | static int __init arch_hw_breakpoint_init(void) | 879 | static int __init arch_hw_breakpoint_init(void) |
| 786 | { | 880 | { |
| 787 | int ret = 0; | ||
| 788 | u32 dscr; | 881 | u32 dscr; |
| 789 | 882 | ||
| 790 | debug_arch = get_debug_arch(); | 883 | debug_arch = get_debug_arch(); |
| 791 | 884 | ||
| 792 | if (debug_arch > ARM_DEBUG_ARCH_V7_ECP14) { | 885 | if (debug_arch > ARM_DEBUG_ARCH_V7_ECP14) { |
| 793 | pr_info("debug architecture 0x%x unsupported.\n", debug_arch); | 886 | pr_info("debug architecture 0x%x unsupported.\n", debug_arch); |
| 794 | ret = -ENODEV; | 887 | return 0; |
| 795 | goto out; | ||
| 796 | } | 888 | } |
| 797 | 889 | ||
| 798 | /* Determine how many BRPs/WRPs are available. */ | 890 | /* Determine how many BRPs/WRPs are available. */ |
| 799 | core_num_brps = get_num_brps(); | 891 | core_num_brps = get_num_brps(); |
| 892 | core_num_reserved_brps = get_num_reserved_brps(); | ||
| 800 | core_num_wrps = get_num_wrps(); | 893 | core_num_wrps = get_num_wrps(); |
| 801 | 894 | ||
| 802 | pr_info("found %d breakpoint and %d watchpoint registers.\n", | 895 | pr_info("found %d breakpoint and %d watchpoint registers.\n", |
| 803 | core_num_brps, core_num_wrps); | 896 | core_num_brps + core_num_reserved_brps, core_num_wrps); |
| 804 | 897 | ||
| 805 | if (core_has_mismatch_bps()) | 898 | if (core_num_reserved_brps) |
| 806 | pr_info("1 breakpoint reserved for watchpoint single-step.\n"); | 899 | pr_info("%d breakpoint(s) reserved for watchpoint " |
| 900 | "single-step.\n", core_num_reserved_brps); | ||
| 807 | 901 | ||
| 808 | ARM_DBG_READ(c1, 0, dscr); | 902 | ARM_DBG_READ(c1, 0, dscr); |
| 809 | if (dscr & ARM_DSCR_HDBGEN) { | 903 | if (dscr & ARM_DSCR_HDBGEN) { |
| 810 | pr_warning("halting debug mode enabled. Assuming maximum " | 904 | pr_warning("halting debug mode enabled. Assuming maximum " |
| 811 | "watchpoint size of 4 bytes."); | 905 | "watchpoint size of 4 bytes."); |
| 812 | } else { | 906 | } else { |
| 813 | /* Work out the maximum supported watchpoint length. */ | ||
| 814 | max_watchpoint_len = get_max_wp_len(); | ||
| 815 | pr_info("maximum watchpoint size is %u bytes.\n", | ||
| 816 | max_watchpoint_len); | ||
| 817 | |||
| 818 | /* | 907 | /* |
| 819 | * Reset the breakpoint resources. We assume that a halting | 908 | * Reset the breakpoint resources. We assume that a halting |
| 820 | * debugger will leave the world in a nice state for us. | 909 | * debugger will leave the world in a nice state for us. |
| 821 | */ | 910 | */ |
| 822 | smp_call_function(reset_ctrl_regs, NULL, 1); | 911 | smp_call_function(reset_ctrl_regs, NULL, 1); |
| 823 | reset_ctrl_regs(NULL); | 912 | reset_ctrl_regs(NULL); |
| 913 | |||
| 914 | /* Work out the maximum supported watchpoint length. */ | ||
| 915 | max_watchpoint_len = get_max_wp_len(); | ||
| 916 | pr_info("maximum watchpoint size is %u bytes.\n", | ||
| 917 | max_watchpoint_len); | ||
| 824 | } | 918 | } |
| 825 | 919 | ||
| 826 | /* Register debug fault handler. */ | 920 | /* Register debug fault handler. */ |
| @@ -829,8 +923,9 @@ static int __init arch_hw_breakpoint_init(void) | |||
| 829 | hook_ifault_code(2, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT, | 923 | hook_ifault_code(2, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT, |
| 830 | "breakpoint debug exception"); | 924 | "breakpoint debug exception"); |
| 831 | 925 | ||
| 832 | out: | 926 | /* Register hotplug notifier. */ |
| 833 | return ret; | 927 | register_cpu_notifier(&dbg_reset_nb); |
| 928 | return 0; | ||
| 834 | } | 929 | } |
| 835 | arch_initcall(arch_hw_breakpoint_init); | 930 | arch_initcall(arch_hw_breakpoint_init); |
| 836 | 931 | ||
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 36ad3be4692a..8135438b8818 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c | |||
| @@ -35,8 +35,10 @@ | |||
| 35 | #include <linux/list.h> | 35 | #include <linux/list.h> |
| 36 | #include <linux/kallsyms.h> | 36 | #include <linux/kallsyms.h> |
| 37 | #include <linux/proc_fs.h> | 37 | #include <linux/proc_fs.h> |
| 38 | #include <linux/ftrace.h> | ||
| 38 | 39 | ||
| 39 | #include <asm/system.h> | 40 | #include <asm/system.h> |
| 41 | #include <asm/mach/arch.h> | ||
| 40 | #include <asm/mach/irq.h> | 42 | #include <asm/mach/irq.h> |
| 41 | #include <asm/mach/time.h> | 43 | #include <asm/mach/time.h> |
| 42 | 44 | ||
| @@ -47,8 +49,6 @@ | |||
| 47 | #define irq_finish(irq) do { } while (0) | 49 | #define irq_finish(irq) do { } while (0) |
| 48 | #endif | 50 | #endif |
| 49 | 51 | ||
| 50 | unsigned int arch_nr_irqs; | ||
| 51 | void (*init_arch_irq)(void) __initdata = NULL; | ||
| 52 | unsigned long irq_err_count; | 52 | unsigned long irq_err_count; |
| 53 | 53 | ||
| 54 | int show_interrupts(struct seq_file *p, void *v) | 54 | int show_interrupts(struct seq_file *p, void *v) |
| @@ -57,11 +57,20 @@ int show_interrupts(struct seq_file *p, void *v) | |||
| 57 | struct irq_desc *desc; | 57 | struct irq_desc *desc; |
| 58 | struct irqaction * action; | 58 | struct irqaction * action; |
| 59 | unsigned long flags; | 59 | unsigned long flags; |
| 60 | int prec, n; | ||
| 61 | |||
| 62 | for (prec = 3, n = 1000; prec < 10 && n <= nr_irqs; prec++) | ||
| 63 | n *= 10; | ||
| 64 | |||
| 65 | #ifdef CONFIG_SMP | ||
| 66 | if (prec < 4) | ||
| 67 | prec = 4; | ||
| 68 | #endif | ||
| 60 | 69 | ||
| 61 | if (i == 0) { | 70 | if (i == 0) { |
| 62 | char cpuname[12]; | 71 | char cpuname[12]; |
| 63 | 72 | ||
| 64 | seq_printf(p, " "); | 73 | seq_printf(p, "%*s ", prec, ""); |
| 65 | for_each_present_cpu(cpu) { | 74 | for_each_present_cpu(cpu) { |
| 66 | sprintf(cpuname, "CPU%d", cpu); | 75 | sprintf(cpuname, "CPU%d", cpu); |
| 67 | seq_printf(p, " %10s", cpuname); | 76 | seq_printf(p, " %10s", cpuname); |
| @@ -76,7 +85,7 @@ int show_interrupts(struct seq_file *p, void *v) | |||
| 76 | if (!action) | 85 | if (!action) |
| 77 | goto unlock; | 86 | goto unlock; |
| 78 | 87 | ||
| 79 | seq_printf(p, "%3d: ", i); | 88 | seq_printf(p, "%*d: ", prec, i); |
| 80 | for_each_present_cpu(cpu) | 89 | for_each_present_cpu(cpu) |
| 81 | seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu)); | 90 | seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu)); |
| 82 | seq_printf(p, " %10s", desc->chip->name ? : "-"); | 91 | seq_printf(p, " %10s", desc->chip->name ? : "-"); |
| @@ -89,13 +98,15 @@ unlock: | |||
| 89 | raw_spin_unlock_irqrestore(&desc->lock, flags); | 98 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
| 90 | } else if (i == nr_irqs) { | 99 | } else if (i == nr_irqs) { |
| 91 | #ifdef CONFIG_FIQ | 100 | #ifdef CONFIG_FIQ |
| 92 | show_fiq_list(p, v); | 101 | show_fiq_list(p, prec); |
| 93 | #endif | 102 | #endif |
| 94 | #ifdef CONFIG_SMP | 103 | #ifdef CONFIG_SMP |
| 95 | show_ipi_list(p); | 104 | show_ipi_list(p, prec); |
| 96 | show_local_irqs(p); | 105 | #endif |
| 106 | #ifdef CONFIG_LOCAL_TIMERS | ||
| 107 | show_local_irqs(p, prec); | ||
| 97 | #endif | 108 | #endif |
| 98 | seq_printf(p, "Err: %10lu\n", irq_err_count); | 109 | seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count); |
| 99 | } | 110 | } |
| 100 | return 0; | 111 | return 0; |
| 101 | } | 112 | } |
| @@ -105,7 +116,8 @@ unlock: | |||
| 105 | * come via this function. Instead, they should provide their | 116 | * come via this function. Instead, they should provide their |
| 106 | * own 'handler' | 117 | * own 'handler' |
| 107 | */ | 118 | */ |
| 108 | asmlinkage void __exception asm_do_IRQ(unsigned int irq, struct pt_regs *regs) | 119 | asmlinkage void __exception_irq_entry |
| 120 | asm_do_IRQ(unsigned int irq, struct pt_regs *regs) | ||
| 109 | { | 121 | { |
| 110 | struct pt_regs *old_regs = set_irq_regs(regs); | 122 | struct pt_regs *old_regs = set_irq_regs(regs); |
| 111 | 123 | ||
| @@ -154,13 +166,13 @@ void set_irq_flags(unsigned int irq, unsigned int iflags) | |||
| 154 | 166 | ||
| 155 | void __init init_IRQ(void) | 167 | void __init init_IRQ(void) |
| 156 | { | 168 | { |
| 157 | init_arch_irq(); | 169 | machine_desc->init_irq(); |
| 158 | } | 170 | } |
| 159 | 171 | ||
| 160 | #ifdef CONFIG_SPARSE_IRQ | 172 | #ifdef CONFIG_SPARSE_IRQ |
| 161 | int __init arch_probe_nr_irqs(void) | 173 | int __init arch_probe_nr_irqs(void) |
| 162 | { | 174 | { |
| 163 | nr_irqs = arch_nr_irqs ? arch_nr_irqs : NR_IRQS; | 175 | nr_irqs = machine_desc->nr_irqs ? machine_desc->nr_irqs : NR_IRQS; |
| 164 | return nr_irqs; | 176 | return nr_irqs; |
| 165 | } | 177 | } |
| 166 | #endif | 178 | #endif |
diff --git a/arch/arm/kernel/iwmmxt.S b/arch/arm/kernel/iwmmxt.S index b63b528f22a6..7fa3bb0d2397 100644 --- a/arch/arm/kernel/iwmmxt.S +++ b/arch/arm/kernel/iwmmxt.S | |||
| @@ -19,6 +19,14 @@ | |||
| 19 | #include <asm/thread_info.h> | 19 | #include <asm/thread_info.h> |
| 20 | #include <asm/asm-offsets.h> | 20 | #include <asm/asm-offsets.h> |
| 21 | 21 | ||
| 22 | #if defined(CONFIG_CPU_PJ4) | ||
| 23 | #define PJ4(code...) code | ||
| 24 | #define XSC(code...) | ||
| 25 | #else | ||
| 26 | #define PJ4(code...) | ||
| 27 | #define XSC(code...) code | ||
| 28 | #endif | ||
| 29 | |||
| 22 | #define MMX_WR0 (0x00) | 30 | #define MMX_WR0 (0x00) |
| 23 | #define MMX_WR1 (0x08) | 31 | #define MMX_WR1 (0x08) |
| 24 | #define MMX_WR2 (0x10) | 32 | #define MMX_WR2 (0x10) |
| @@ -58,11 +66,17 @@ | |||
| 58 | 66 | ||
| 59 | ENTRY(iwmmxt_task_enable) | 67 | ENTRY(iwmmxt_task_enable) |
| 60 | 68 | ||
| 61 | mrc p15, 0, r2, c15, c1, 0 | 69 | XSC(mrc p15, 0, r2, c15, c1, 0) |
| 62 | tst r2, #0x3 @ CP0 and CP1 accessible? | 70 | PJ4(mrc p15, 0, r2, c1, c0, 2) |
| 71 | @ CP0 and CP1 accessible? | ||
| 72 | XSC(tst r2, #0x3) | ||
| 73 | PJ4(tst r2, #0xf) | ||
| 63 | movne pc, lr @ if so no business here | 74 | movne pc, lr @ if so no business here |
| 64 | orr r2, r2, #0x3 @ enable access to CP0 and CP1 | 75 | @ enable access to CP0 and CP1 |
| 65 | mcr p15, 0, r2, c15, c1, 0 | 76 | XSC(orr r2, r2, #0x3) |
| 77 | XSC(mcr p15, 0, r2, c15, c1, 0) | ||
| 78 | PJ4(orr r2, r2, #0xf) | ||
| 79 | PJ4(mcr p15, 0, r2, c1, c0, 2) | ||
| 66 | 80 | ||
| 67 | ldr r3, =concan_owner | 81 | ldr r3, =concan_owner |
| 68 | add r0, r10, #TI_IWMMXT_STATE @ get task Concan save area | 82 | add r0, r10, #TI_IWMMXT_STATE @ get task Concan save area |
| @@ -179,17 +193,26 @@ ENTRY(iwmmxt_task_disable) | |||
| 179 | teqne r1, r2 @ or specified one? | 193 | teqne r1, r2 @ or specified one? |
| 180 | bne 1f @ no: quit | 194 | bne 1f @ no: quit |
| 181 | 195 | ||
| 182 | mrc p15, 0, r4, c15, c1, 0 | 196 | @ enable access to CP0 and CP1 |
| 183 | orr r4, r4, #0x3 @ enable access to CP0 and CP1 | 197 | XSC(mrc p15, 0, r4, c15, c1, 0) |
| 184 | mcr p15, 0, r4, c15, c1, 0 | 198 | XSC(orr r4, r4, #0xf) |
| 199 | XSC(mcr p15, 0, r4, c15, c1, 0) | ||
| 200 | PJ4(mrc p15, 0, r4, c1, c0, 2) | ||
| 201 | PJ4(orr r4, r4, #0x3) | ||
| 202 | PJ4(mcr p15, 0, r4, c1, c0, 2) | ||
| 203 | |||
| 185 | mov r0, #0 @ nothing to load | 204 | mov r0, #0 @ nothing to load |
| 186 | str r0, [r3] @ no more current owner | 205 | str r0, [r3] @ no more current owner |
| 187 | mrc p15, 0, r2, c2, c0, 0 | 206 | mrc p15, 0, r2, c2, c0, 0 |
| 188 | mov r2, r2 @ cpwait | 207 | mov r2, r2 @ cpwait |
| 189 | bl concan_save | 208 | bl concan_save |
| 190 | 209 | ||
| 191 | bic r4, r4, #0x3 @ disable access to CP0 and CP1 | 210 | @ disable access to CP0 and CP1 |
| 192 | mcr p15, 0, r4, c15, c1, 0 | 211 | XSC(bic r4, r4, #0x3) |
| 212 | XSC(mcr p15, 0, r4, c15, c1, 0) | ||
| 213 | PJ4(bic r4, r4, #0xf) | ||
| 214 | PJ4(mcr p15, 0, r4, c1, c0, 2) | ||
| 215 | |||
| 193 | mrc p15, 0, r2, c2, c0, 0 | 216 | mrc p15, 0, r2, c2, c0, 0 |
| 194 | mov r2, r2 @ cpwait | 217 | mov r2, r2 @ cpwait |
| 195 | 218 | ||
| @@ -277,8 +300,11 @@ ENTRY(iwmmxt_task_restore) | |||
| 277 | */ | 300 | */ |
| 278 | ENTRY(iwmmxt_task_switch) | 301 | ENTRY(iwmmxt_task_switch) |
| 279 | 302 | ||
| 280 | mrc p15, 0, r1, c15, c1, 0 | 303 | XSC(mrc p15, 0, r1, c15, c1, 0) |
| 281 | tst r1, #0x3 @ CP0 and CP1 accessible? | 304 | PJ4(mrc p15, 0, r1, c1, c0, 2) |
| 305 | @ CP0 and CP1 accessible? | ||
| 306 | XSC(tst r1, #0x3) | ||
| 307 | PJ4(tst r1, #0xf) | ||
| 282 | bne 1f @ yes: block them for next task | 308 | bne 1f @ yes: block them for next task |
| 283 | 309 | ||
| 284 | ldr r2, =concan_owner | 310 | ldr r2, =concan_owner |
| @@ -287,8 +313,11 @@ ENTRY(iwmmxt_task_switch) | |||
| 287 | teq r2, r3 @ next task owns it? | 313 | teq r2, r3 @ next task owns it? |
| 288 | movne pc, lr @ no: leave Concan disabled | 314 | movne pc, lr @ no: leave Concan disabled |
| 289 | 315 | ||
| 290 | 1: eor r1, r1, #3 @ flip Concan access | 316 | 1: @ flip Conan access |
| 291 | mcr p15, 0, r1, c15, c1, 0 | 317 | XSC(eor r1, r1, #0x3) |
| 318 | XSC(mcr p15, 0, r1, c15, c1, 0) | ||
| 319 | PJ4(eor r1, r1, #0xf) | ||
| 320 | PJ4(mcr p15, 0, r1, c1, c0, 2) | ||
| 292 | 321 | ||
| 293 | mrc p15, 0, r1, c2, c0, 0 | 322 | mrc p15, 0, r1, c2, c0, 0 |
| 294 | sub pc, lr, r1, lsr #32 @ cpwait and return | 323 | sub pc, lr, r1, lsr #32 @ cpwait and return |
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c index 3a8fd5140d7a..30ead135ff5f 100644 --- a/arch/arm/kernel/machine_kexec.c +++ b/arch/arm/kernel/machine_kexec.c | |||
| @@ -23,6 +23,8 @@ extern unsigned long kexec_indirection_page; | |||
| 23 | extern unsigned long kexec_mach_type; | 23 | extern unsigned long kexec_mach_type; |
| 24 | extern unsigned long kexec_boot_atags; | 24 | extern unsigned long kexec_boot_atags; |
| 25 | 25 | ||
| 26 | static atomic_t waiting_for_crash_ipi; | ||
| 27 | |||
| 26 | /* | 28 | /* |
| 27 | * Provide a dummy crash_notes definition while crash dump arrives to arm. | 29 | * Provide a dummy crash_notes definition while crash dump arrives to arm. |
| 28 | * This prevents breakage of crash_notes attribute in kernel/ksysfs.c. | 30 | * This prevents breakage of crash_notes attribute in kernel/ksysfs.c. |
| @@ -37,9 +39,37 @@ void machine_kexec_cleanup(struct kimage *image) | |||
| 37 | { | 39 | { |
| 38 | } | 40 | } |
| 39 | 41 | ||
| 42 | void machine_crash_nonpanic_core(void *unused) | ||
| 43 | { | ||
| 44 | struct pt_regs regs; | ||
| 45 | |||
| 46 | crash_setup_regs(®s, NULL); | ||
| 47 | printk(KERN_DEBUG "CPU %u will stop doing anything useful since another CPU has crashed\n", | ||
| 48 | smp_processor_id()); | ||
| 49 | crash_save_cpu(®s, smp_processor_id()); | ||
| 50 | flush_cache_all(); | ||
| 51 | |||
| 52 | atomic_dec(&waiting_for_crash_ipi); | ||
| 53 | while (1) | ||
| 54 | cpu_relax(); | ||
| 55 | } | ||
| 56 | |||
| 40 | void machine_crash_shutdown(struct pt_regs *regs) | 57 | void machine_crash_shutdown(struct pt_regs *regs) |
| 41 | { | 58 | { |
| 59 | unsigned long msecs; | ||
| 60 | |||
| 42 | local_irq_disable(); | 61 | local_irq_disable(); |
| 62 | |||
| 63 | atomic_set(&waiting_for_crash_ipi, num_online_cpus() - 1); | ||
| 64 | smp_call_function(machine_crash_nonpanic_core, NULL, false); | ||
| 65 | msecs = 1000; /* Wait at most a second for the other cpus to stop */ | ||
| 66 | while ((atomic_read(&waiting_for_crash_ipi) > 0) && msecs) { | ||
| 67 | mdelay(1); | ||
| 68 | msecs--; | ||
| 69 | } | ||
| 70 | if (atomic_read(&waiting_for_crash_ipi) > 0) | ||
| 71 | printk(KERN_WARNING "Non-crashing CPUs did not react to IPI\n"); | ||
| 72 | |||
| 43 | crash_save_cpu(regs, smp_processor_id()); | 73 | crash_save_cpu(regs, smp_processor_id()); |
| 44 | 74 | ||
| 45 | printk(KERN_INFO "Loading crashdump kernel...\n"); | 75 | printk(KERN_INFO "Loading crashdump kernel...\n"); |
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c index d9bd786ce23d..0c1bb68ff4a8 100644 --- a/arch/arm/kernel/module.c +++ b/arch/arm/kernel/module.c | |||
| @@ -67,35 +67,6 @@ int module_frob_arch_sections(Elf_Ehdr *hdr, | |||
| 67 | char *secstrings, | 67 | char *secstrings, |
| 68 | struct module *mod) | 68 | struct module *mod) |
| 69 | { | 69 | { |
| 70 | #ifdef CONFIG_ARM_UNWIND | ||
| 71 | Elf_Shdr *s, *sechdrs_end = sechdrs + hdr->e_shnum; | ||
| 72 | struct arm_unwind_mapping *maps = mod->arch.map; | ||
| 73 | |||
| 74 | for (s = sechdrs; s < sechdrs_end; s++) { | ||
| 75 | char const *secname = secstrings + s->sh_name; | ||
| 76 | |||
| 77 | if (strcmp(".ARM.exidx.init.text", secname) == 0) | ||
| 78 | maps[ARM_SEC_INIT].unw_sec = s; | ||
| 79 | else if (strcmp(".ARM.exidx.devinit.text", secname) == 0) | ||
| 80 | maps[ARM_SEC_DEVINIT].unw_sec = s; | ||
| 81 | else if (strcmp(".ARM.exidx", secname) == 0) | ||
| 82 | maps[ARM_SEC_CORE].unw_sec = s; | ||
| 83 | else if (strcmp(".ARM.exidx.exit.text", secname) == 0) | ||
| 84 | maps[ARM_SEC_EXIT].unw_sec = s; | ||
| 85 | else if (strcmp(".ARM.exidx.devexit.text", secname) == 0) | ||
| 86 | maps[ARM_SEC_DEVEXIT].unw_sec = s; | ||
| 87 | else if (strcmp(".init.text", secname) == 0) | ||
| 88 | maps[ARM_SEC_INIT].sec_text = s; | ||
| 89 | else if (strcmp(".devinit.text", secname) == 0) | ||
| 90 | maps[ARM_SEC_DEVINIT].sec_text = s; | ||
| 91 | else if (strcmp(".text", secname) == 0) | ||
| 92 | maps[ARM_SEC_CORE].sec_text = s; | ||
| 93 | else if (strcmp(".exit.text", secname) == 0) | ||
| 94 | maps[ARM_SEC_EXIT].sec_text = s; | ||
| 95 | else if (strcmp(".devexit.text", secname) == 0) | ||
| 96 | maps[ARM_SEC_DEVEXIT].sec_text = s; | ||
| 97 | } | ||
| 98 | #endif | ||
| 99 | return 0; | 70 | return 0; |
| 100 | } | 71 | } |
| 101 | 72 | ||
| @@ -300,41 +271,69 @@ apply_relocate_add(Elf32_Shdr *sechdrs, const char *strtab, | |||
| 300 | return -ENOEXEC; | 271 | return -ENOEXEC; |
| 301 | } | 272 | } |
| 302 | 273 | ||
| 303 | #ifdef CONFIG_ARM_UNWIND | 274 | struct mod_unwind_map { |
| 304 | static void register_unwind_tables(struct module *mod) | 275 | const Elf_Shdr *unw_sec; |
| 276 | const Elf_Shdr *txt_sec; | ||
| 277 | }; | ||
| 278 | |||
| 279 | int module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs, | ||
| 280 | struct module *mod) | ||
| 305 | { | 281 | { |
| 282 | #ifdef CONFIG_ARM_UNWIND | ||
| 283 | const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset; | ||
| 284 | const Elf_Shdr *s, *sechdrs_end = sechdrs + hdr->e_shnum; | ||
| 285 | struct mod_unwind_map maps[ARM_SEC_MAX]; | ||
| 306 | int i; | 286 | int i; |
| 307 | for (i = 0; i < ARM_SEC_MAX; ++i) { | 287 | |
| 308 | struct arm_unwind_mapping *map = &mod->arch.map[i]; | 288 | memset(maps, 0, sizeof(maps)); |
| 309 | if (map->unw_sec && map->sec_text) | 289 | |
| 310 | map->unwind = unwind_table_add(map->unw_sec->sh_addr, | 290 | for (s = sechdrs; s < sechdrs_end; s++) { |
| 311 | map->unw_sec->sh_size, | 291 | const char *secname = secstrs + s->sh_name; |
| 312 | map->sec_text->sh_addr, | 292 | |
| 313 | map->sec_text->sh_size); | 293 | if (!(s->sh_flags & SHF_ALLOC)) |
| 294 | continue; | ||
| 295 | |||
| 296 | if (strcmp(".ARM.exidx.init.text", secname) == 0) | ||
| 297 | maps[ARM_SEC_INIT].unw_sec = s; | ||
| 298 | else if (strcmp(".ARM.exidx.devinit.text", secname) == 0) | ||
| 299 | maps[ARM_SEC_DEVINIT].unw_sec = s; | ||
| 300 | else if (strcmp(".ARM.exidx", secname) == 0) | ||
| 301 | maps[ARM_SEC_CORE].unw_sec = s; | ||
| 302 | else if (strcmp(".ARM.exidx.exit.text", secname) == 0) | ||
| 303 | maps[ARM_SEC_EXIT].unw_sec = s; | ||
| 304 | else if (strcmp(".ARM.exidx.devexit.text", secname) == 0) | ||
| 305 | maps[ARM_SEC_DEVEXIT].unw_sec = s; | ||
| 306 | else if (strcmp(".init.text", secname) == 0) | ||
| 307 | maps[ARM_SEC_INIT].txt_sec = s; | ||
| 308 | else if (strcmp(".devinit.text", secname) == 0) | ||
| 309 | maps[ARM_SEC_DEVINIT].txt_sec = s; | ||
| 310 | else if (strcmp(".text", secname) == 0) | ||
| 311 | maps[ARM_SEC_CORE].txt_sec = s; | ||
| 312 | else if (strcmp(".exit.text", secname) == 0) | ||
| 313 | maps[ARM_SEC_EXIT].txt_sec = s; | ||
| 314 | else if (strcmp(".devexit.text", secname) == 0) | ||
| 315 | maps[ARM_SEC_DEVEXIT].txt_sec = s; | ||
| 314 | } | 316 | } |
| 315 | } | ||
| 316 | 317 | ||
| 317 | static void unregister_unwind_tables(struct module *mod) | 318 | for (i = 0; i < ARM_SEC_MAX; i++) |
| 318 | { | 319 | if (maps[i].unw_sec && maps[i].txt_sec) |
| 319 | int i = ARM_SEC_MAX; | 320 | mod->arch.unwind[i] = |
| 320 | while (--i >= 0) | 321 | unwind_table_add(maps[i].unw_sec->sh_addr, |
| 321 | unwind_table_del(mod->arch.map[i].unwind); | 322 | maps[i].unw_sec->sh_size, |
| 322 | } | 323 | maps[i].txt_sec->sh_addr, |
| 323 | #else | 324 | maps[i].txt_sec->sh_size); |
| 324 | static inline void register_unwind_tables(struct module *mod) { } | ||
| 325 | static inline void unregister_unwind_tables(struct module *mod) { } | ||
| 326 | #endif | 325 | #endif |
| 327 | |||
| 328 | int | ||
| 329 | module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs, | ||
| 330 | struct module *module) | ||
| 331 | { | ||
| 332 | register_unwind_tables(module); | ||
| 333 | return 0; | 326 | return 0; |
| 334 | } | 327 | } |
| 335 | 328 | ||
| 336 | void | 329 | void |
| 337 | module_arch_cleanup(struct module *mod) | 330 | module_arch_cleanup(struct module *mod) |
| 338 | { | 331 | { |
| 339 | unregister_unwind_tables(mod); | 332 | #ifdef CONFIG_ARM_UNWIND |
| 333 | int i; | ||
| 334 | |||
| 335 | for (i = 0; i < ARM_SEC_MAX; i++) | ||
| 336 | if (mod->arch.unwind[i]) | ||
| 337 | unwind_table_del(mod->arch.unwind[i]); | ||
| 338 | #endif | ||
| 340 | } | 339 | } |
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index 07a50357492a..5efa2647a2fb 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c | |||
| @@ -4,9 +4,7 @@ | |||
| 4 | * ARM performance counter support. | 4 | * ARM performance counter support. |
| 5 | * | 5 | * |
| 6 | * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles | 6 | * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles |
| 7 | * | 7 | * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com> |
| 8 | * ARMv7 support: Jean Pihet <jpihet@mvista.com> | ||
| 9 | * 2010 (c) MontaVista Software, LLC. | ||
| 10 | * | 8 | * |
| 11 | * This code is based on the sparc64 perf event code, which is in turn based | 9 | * This code is based on the sparc64 perf event code, which is in turn based |
| 12 | * on the x86 code. Callchain code is based on the ARM OProfile backtrace | 10 | * on the x86 code. Callchain code is based on the ARM OProfile backtrace |
| @@ -34,7 +32,7 @@ static struct platform_device *pmu_device; | |||
| 34 | * Hardware lock to serialize accesses to PMU registers. Needed for the | 32 | * Hardware lock to serialize accesses to PMU registers. Needed for the |
| 35 | * read/modify/write sequences. | 33 | * read/modify/write sequences. |
| 36 | */ | 34 | */ |
| 37 | DEFINE_SPINLOCK(pmu_lock); | 35 | static DEFINE_RAW_SPINLOCK(pmu_lock); |
| 38 | 36 | ||
| 39 | /* | 37 | /* |
| 40 | * ARMv6 supports a maximum of 3 events, starting from index 1. If we add | 38 | * ARMv6 supports a maximum of 3 events, starting from index 1. If we add |
| @@ -67,31 +65,25 @@ struct cpu_hw_events { | |||
| 67 | */ | 65 | */ |
| 68 | unsigned long active_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)]; | 66 | unsigned long active_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)]; |
| 69 | }; | 67 | }; |
| 70 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); | 68 | static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); |
| 71 | |||
| 72 | /* PMU names. */ | ||
| 73 | static const char *arm_pmu_names[] = { | ||
| 74 | [ARM_PERF_PMU_ID_XSCALE1] = "xscale1", | ||
| 75 | [ARM_PERF_PMU_ID_XSCALE2] = "xscale2", | ||
| 76 | [ARM_PERF_PMU_ID_V6] = "v6", | ||
| 77 | [ARM_PERF_PMU_ID_V6MP] = "v6mpcore", | ||
| 78 | [ARM_PERF_PMU_ID_CA8] = "ARMv7 Cortex-A8", | ||
| 79 | [ARM_PERF_PMU_ID_CA9] = "ARMv7 Cortex-A9", | ||
| 80 | }; | ||
| 81 | 69 | ||
| 82 | struct arm_pmu { | 70 | struct arm_pmu { |
| 83 | enum arm_perf_pmu_ids id; | 71 | enum arm_perf_pmu_ids id; |
| 72 | const char *name; | ||
| 84 | irqreturn_t (*handle_irq)(int irq_num, void *dev); | 73 | irqreturn_t (*handle_irq)(int irq_num, void *dev); |
| 85 | void (*enable)(struct hw_perf_event *evt, int idx); | 74 | void (*enable)(struct hw_perf_event *evt, int idx); |
| 86 | void (*disable)(struct hw_perf_event *evt, int idx); | 75 | void (*disable)(struct hw_perf_event *evt, int idx); |
| 87 | int (*event_map)(int evt); | ||
| 88 | u64 (*raw_event)(u64); | ||
| 89 | int (*get_event_idx)(struct cpu_hw_events *cpuc, | 76 | int (*get_event_idx)(struct cpu_hw_events *cpuc, |
| 90 | struct hw_perf_event *hwc); | 77 | struct hw_perf_event *hwc); |
| 91 | u32 (*read_counter)(int idx); | 78 | u32 (*read_counter)(int idx); |
| 92 | void (*write_counter)(int idx, u32 val); | 79 | void (*write_counter)(int idx, u32 val); |
| 93 | void (*start)(void); | 80 | void (*start)(void); |
| 94 | void (*stop)(void); | 81 | void (*stop)(void); |
| 82 | const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX] | ||
| 83 | [PERF_COUNT_HW_CACHE_OP_MAX] | ||
| 84 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | ||
| 85 | const unsigned (*event_map)[PERF_COUNT_HW_MAX]; | ||
| 86 | u32 raw_event_mask; | ||
| 95 | int num_events; | 87 | int num_events; |
| 96 | u64 max_period; | 88 | u64 max_period; |
| 97 | }; | 89 | }; |
| @@ -136,10 +128,6 @@ EXPORT_SYMBOL_GPL(perf_num_counters); | |||
| 136 | 128 | ||
| 137 | #define CACHE_OP_UNSUPPORTED 0xFFFF | 129 | #define CACHE_OP_UNSUPPORTED 0xFFFF |
| 138 | 130 | ||
| 139 | static unsigned armpmu_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | ||
| 140 | [PERF_COUNT_HW_CACHE_OP_MAX] | ||
| 141 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | ||
| 142 | |||
| 143 | static int | 131 | static int |
| 144 | armpmu_map_cache_event(u64 config) | 132 | armpmu_map_cache_event(u64 config) |
| 145 | { | 133 | { |
| @@ -157,7 +145,7 @@ armpmu_map_cache_event(u64 config) | |||
| 157 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | 145 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) |
| 158 | return -EINVAL; | 146 | return -EINVAL; |
| 159 | 147 | ||
| 160 | ret = (int)armpmu_perf_cache_map[cache_type][cache_op][cache_result]; | 148 | ret = (int)(*armpmu->cache_map)[cache_type][cache_op][cache_result]; |
| 161 | 149 | ||
| 162 | if (ret == CACHE_OP_UNSUPPORTED) | 150 | if (ret == CACHE_OP_UNSUPPORTED) |
| 163 | return -ENOENT; | 151 | return -ENOENT; |
| @@ -166,6 +154,19 @@ armpmu_map_cache_event(u64 config) | |||
| 166 | } | 154 | } |
| 167 | 155 | ||
| 168 | static int | 156 | static int |
| 157 | armpmu_map_event(u64 config) | ||
| 158 | { | ||
| 159 | int mapping = (*armpmu->event_map)[config]; | ||
| 160 | return mapping == HW_OP_UNSUPPORTED ? -EOPNOTSUPP : mapping; | ||
| 161 | } | ||
| 162 | |||
| 163 | static int | ||
| 164 | armpmu_map_raw_event(u64 config) | ||
| 165 | { | ||
| 166 | return (int)(config & armpmu->raw_event_mask); | ||
| 167 | } | ||
| 168 | |||
| 169 | static int | ||
| 169 | armpmu_event_set_period(struct perf_event *event, | 170 | armpmu_event_set_period(struct perf_event *event, |
| 170 | struct hw_perf_event *hwc, | 171 | struct hw_perf_event *hwc, |
| 171 | int idx) | 172 | int idx) |
| @@ -458,11 +459,11 @@ __hw_perf_event_init(struct perf_event *event) | |||
| 458 | 459 | ||
| 459 | /* Decode the generic type into an ARM event identifier. */ | 460 | /* Decode the generic type into an ARM event identifier. */ |
| 460 | if (PERF_TYPE_HARDWARE == event->attr.type) { | 461 | if (PERF_TYPE_HARDWARE == event->attr.type) { |
| 461 | mapping = armpmu->event_map(event->attr.config); | 462 | mapping = armpmu_map_event(event->attr.config); |
| 462 | } else if (PERF_TYPE_HW_CACHE == event->attr.type) { | 463 | } else if (PERF_TYPE_HW_CACHE == event->attr.type) { |
| 463 | mapping = armpmu_map_cache_event(event->attr.config); | 464 | mapping = armpmu_map_cache_event(event->attr.config); |
| 464 | } else if (PERF_TYPE_RAW == event->attr.type) { | 465 | } else if (PERF_TYPE_RAW == event->attr.type) { |
| 465 | mapping = armpmu->raw_event(event->attr.config); | 466 | mapping = armpmu_map_raw_event(event->attr.config); |
| 466 | } else { | 467 | } else { |
| 467 | pr_debug("event type %x not supported\n", event->attr.type); | 468 | pr_debug("event type %x not supported\n", event->attr.type); |
| 468 | return -EOPNOTSUPP; | 469 | return -EOPNOTSUPP; |
| @@ -603,2366 +604,10 @@ static struct pmu pmu = { | |||
| 603 | .read = armpmu_read, | 604 | .read = armpmu_read, |
| 604 | }; | 605 | }; |
| 605 | 606 | ||
| 606 | /* | 607 | /* Include the PMU-specific implementations. */ |
| 607 | * ARMv6 Performance counter handling code. | 608 | #include "perf_event_xscale.c" |
| 608 | * | 609 | #include "perf_event_v6.c" |
| 609 | * ARMv6 has 2 configurable performance counters and a single cycle counter. | 610 | #include "perf_event_v7.c" |
| 610 | * They all share a single reset bit but can be written to zero so we can use | ||
| 611 | * that for a reset. | ||
| 612 | * | ||
| 613 | * The counters can't be individually enabled or disabled so when we remove | ||
| 614 | * one event and replace it with another we could get spurious counts from the | ||
| 615 | * wrong event. However, we can take advantage of the fact that the | ||
| 616 | * performance counters can export events to the event bus, and the event bus | ||
| 617 | * itself can be monitored. This requires that we *don't* export the events to | ||
| 618 | * the event bus. The procedure for disabling a configurable counter is: | ||
| 619 | * - change the counter to count the ETMEXTOUT[0] signal (0x20). This | ||
| 620 | * effectively stops the counter from counting. | ||
| 621 | * - disable the counter's interrupt generation (each counter has it's | ||
| 622 | * own interrupt enable bit). | ||
| 623 | * Once stopped, the counter value can be written as 0 to reset. | ||
| 624 | * | ||
| 625 | * To enable a counter: | ||
| 626 | * - enable the counter's interrupt generation. | ||
| 627 | * - set the new event type. | ||
| 628 | * | ||
| 629 | * Note: the dedicated cycle counter only counts cycles and can't be | ||
| 630 | * enabled/disabled independently of the others. When we want to disable the | ||
| 631 | * cycle counter, we have to just disable the interrupt reporting and start | ||
| 632 | * ignoring that counter. When re-enabling, we have to reset the value and | ||
| 633 | * enable the interrupt. | ||
| 634 | */ | ||
| 635 | |||
| 636 | enum armv6_perf_types { | ||
| 637 | ARMV6_PERFCTR_ICACHE_MISS = 0x0, | ||
| 638 | ARMV6_PERFCTR_IBUF_STALL = 0x1, | ||
| 639 | ARMV6_PERFCTR_DDEP_STALL = 0x2, | ||
| 640 | ARMV6_PERFCTR_ITLB_MISS = 0x3, | ||
| 641 | ARMV6_PERFCTR_DTLB_MISS = 0x4, | ||
| 642 | ARMV6_PERFCTR_BR_EXEC = 0x5, | ||
| 643 | ARMV6_PERFCTR_BR_MISPREDICT = 0x6, | ||
| 644 | ARMV6_PERFCTR_INSTR_EXEC = 0x7, | ||
| 645 | ARMV6_PERFCTR_DCACHE_HIT = 0x9, | ||
| 646 | ARMV6_PERFCTR_DCACHE_ACCESS = 0xA, | ||
| 647 | ARMV6_PERFCTR_DCACHE_MISS = 0xB, | ||
| 648 | ARMV6_PERFCTR_DCACHE_WBACK = 0xC, | ||
| 649 | ARMV6_PERFCTR_SW_PC_CHANGE = 0xD, | ||
| 650 | ARMV6_PERFCTR_MAIN_TLB_MISS = 0xF, | ||
| 651 | ARMV6_PERFCTR_EXPL_D_ACCESS = 0x10, | ||
| 652 | ARMV6_PERFCTR_LSU_FULL_STALL = 0x11, | ||
| 653 | ARMV6_PERFCTR_WBUF_DRAINED = 0x12, | ||
| 654 | ARMV6_PERFCTR_CPU_CYCLES = 0xFF, | ||
| 655 | ARMV6_PERFCTR_NOP = 0x20, | ||
| 656 | }; | ||
| 657 | |||
| 658 | enum armv6_counters { | ||
| 659 | ARMV6_CYCLE_COUNTER = 1, | ||
| 660 | ARMV6_COUNTER0, | ||
| 661 | ARMV6_COUNTER1, | ||
| 662 | }; | ||
| 663 | |||
| 664 | /* | ||
| 665 | * The hardware events that we support. We do support cache operations but | ||
| 666 | * we have harvard caches and no way to combine instruction and data | ||
| 667 | * accesses/misses in hardware. | ||
| 668 | */ | ||
| 669 | static const unsigned armv6_perf_map[PERF_COUNT_HW_MAX] = { | ||
| 670 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV6_PERFCTR_CPU_CYCLES, | ||
| 671 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6_PERFCTR_INSTR_EXEC, | ||
| 672 | [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, | ||
| 673 | [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, | ||
| 674 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6_PERFCTR_BR_EXEC, | ||
| 675 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6_PERFCTR_BR_MISPREDICT, | ||
| 676 | [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED, | ||
| 677 | }; | ||
| 678 | |||
| 679 | static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | ||
| 680 | [PERF_COUNT_HW_CACHE_OP_MAX] | ||
| 681 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { | ||
| 682 | [C(L1D)] = { | ||
| 683 | /* | ||
| 684 | * The performance counters don't differentiate between read | ||
| 685 | * and write accesses/misses so this isn't strictly correct, | ||
| 686 | * but it's the best we can do. Writes and reads get | ||
| 687 | * combined. | ||
| 688 | */ | ||
| 689 | [C(OP_READ)] = { | ||
| 690 | [C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS, | ||
| 691 | [C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS, | ||
| 692 | }, | ||
| 693 | [C(OP_WRITE)] = { | ||
| 694 | [C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS, | ||
| 695 | [C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS, | ||
| 696 | }, | ||
| 697 | [C(OP_PREFETCH)] = { | ||
| 698 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 699 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 700 | }, | ||
| 701 | }, | ||
| 702 | [C(L1I)] = { | ||
| 703 | [C(OP_READ)] = { | ||
| 704 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 705 | [C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS, | ||
| 706 | }, | ||
| 707 | [C(OP_WRITE)] = { | ||
| 708 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 709 | [C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS, | ||
| 710 | }, | ||
| 711 | [C(OP_PREFETCH)] = { | ||
| 712 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 713 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 714 | }, | ||
| 715 | }, | ||
| 716 | [C(LL)] = { | ||
| 717 | [C(OP_READ)] = { | ||
| 718 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 719 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 720 | }, | ||
| 721 | [C(OP_WRITE)] = { | ||
| 722 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 723 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 724 | }, | ||
| 725 | [C(OP_PREFETCH)] = { | ||
| 726 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 727 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 728 | }, | ||
| 729 | }, | ||
| 730 | [C(DTLB)] = { | ||
| 731 | /* | ||
| 732 | * The ARM performance counters can count micro DTLB misses, | ||
| 733 | * micro ITLB misses and main TLB misses. There isn't an event | ||
| 734 | * for TLB misses, so use the micro misses here and if users | ||
| 735 | * want the main TLB misses they can use a raw counter. | ||
| 736 | */ | ||
| 737 | [C(OP_READ)] = { | ||
| 738 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 739 | [C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS, | ||
| 740 | }, | ||
| 741 | [C(OP_WRITE)] = { | ||
| 742 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 743 | [C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS, | ||
| 744 | }, | ||
| 745 | [C(OP_PREFETCH)] = { | ||
| 746 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 747 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 748 | }, | ||
| 749 | }, | ||
| 750 | [C(ITLB)] = { | ||
| 751 | [C(OP_READ)] = { | ||
| 752 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 753 | [C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS, | ||
| 754 | }, | ||
| 755 | [C(OP_WRITE)] = { | ||
| 756 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 757 | [C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS, | ||
| 758 | }, | ||
| 759 | [C(OP_PREFETCH)] = { | ||
| 760 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 761 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 762 | }, | ||
| 763 | }, | ||
| 764 | [C(BPU)] = { | ||
| 765 | [C(OP_READ)] = { | ||
| 766 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 767 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 768 | }, | ||
| 769 | [C(OP_WRITE)] = { | ||
| 770 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 771 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 772 | }, | ||
| 773 | [C(OP_PREFETCH)] = { | ||
| 774 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 775 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 776 | }, | ||
| 777 | }, | ||
| 778 | }; | ||
| 779 | |||
| 780 | enum armv6mpcore_perf_types { | ||
| 781 | ARMV6MPCORE_PERFCTR_ICACHE_MISS = 0x0, | ||
| 782 | ARMV6MPCORE_PERFCTR_IBUF_STALL = 0x1, | ||
| 783 | ARMV6MPCORE_PERFCTR_DDEP_STALL = 0x2, | ||
| 784 | ARMV6MPCORE_PERFCTR_ITLB_MISS = 0x3, | ||
| 785 | ARMV6MPCORE_PERFCTR_DTLB_MISS = 0x4, | ||
| 786 | ARMV6MPCORE_PERFCTR_BR_EXEC = 0x5, | ||
| 787 | ARMV6MPCORE_PERFCTR_BR_NOTPREDICT = 0x6, | ||
| 788 | ARMV6MPCORE_PERFCTR_BR_MISPREDICT = 0x7, | ||
| 789 | ARMV6MPCORE_PERFCTR_INSTR_EXEC = 0x8, | ||
| 790 | ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS = 0xA, | ||
| 791 | ARMV6MPCORE_PERFCTR_DCACHE_RDMISS = 0xB, | ||
| 792 | ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS = 0xC, | ||
| 793 | ARMV6MPCORE_PERFCTR_DCACHE_WRMISS = 0xD, | ||
| 794 | ARMV6MPCORE_PERFCTR_DCACHE_EVICTION = 0xE, | ||
| 795 | ARMV6MPCORE_PERFCTR_SW_PC_CHANGE = 0xF, | ||
| 796 | ARMV6MPCORE_PERFCTR_MAIN_TLB_MISS = 0x10, | ||
| 797 | ARMV6MPCORE_PERFCTR_EXPL_MEM_ACCESS = 0x11, | ||
| 798 | ARMV6MPCORE_PERFCTR_LSU_FULL_STALL = 0x12, | ||
| 799 | ARMV6MPCORE_PERFCTR_WBUF_DRAINED = 0x13, | ||
| 800 | ARMV6MPCORE_PERFCTR_CPU_CYCLES = 0xFF, | ||
| 801 | }; | ||
| 802 | |||
| 803 | /* | ||
| 804 | * The hardware events that we support. We do support cache operations but | ||
| 805 | * we have harvard caches and no way to combine instruction and data | ||
| 806 | * accesses/misses in hardware. | ||
| 807 | */ | ||
| 808 | static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = { | ||
| 809 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV6MPCORE_PERFCTR_CPU_CYCLES, | ||
| 810 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_INSTR_EXEC, | ||
| 811 | [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, | ||
| 812 | [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, | ||
| 813 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC, | ||
| 814 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6MPCORE_PERFCTR_BR_MISPREDICT, | ||
| 815 | [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED, | ||
| 816 | }; | ||
| 817 | |||
| 818 | static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | ||
| 819 | [PERF_COUNT_HW_CACHE_OP_MAX] | ||
| 820 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { | ||
| 821 | [C(L1D)] = { | ||
| 822 | [C(OP_READ)] = { | ||
| 823 | [C(RESULT_ACCESS)] = | ||
| 824 | ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS, | ||
| 825 | [C(RESULT_MISS)] = | ||
| 826 | ARMV6MPCORE_PERFCTR_DCACHE_RDMISS, | ||
| 827 | }, | ||
| 828 | [C(OP_WRITE)] = { | ||
| 829 | [C(RESULT_ACCESS)] = | ||
| 830 | ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS, | ||
| 831 | [C(RESULT_MISS)] = | ||
| 832 | ARMV6MPCORE_PERFCTR_DCACHE_WRMISS, | ||
| 833 | }, | ||
| 834 | [C(OP_PREFETCH)] = { | ||
| 835 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 836 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 837 | }, | ||
| 838 | }, | ||
| 839 | [C(L1I)] = { | ||
| 840 | [C(OP_READ)] = { | ||
| 841 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 842 | [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS, | ||
| 843 | }, | ||
| 844 | [C(OP_WRITE)] = { | ||
| 845 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 846 | [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS, | ||
| 847 | }, | ||
| 848 | [C(OP_PREFETCH)] = { | ||
| 849 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 850 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 851 | }, | ||
| 852 | }, | ||
| 853 | [C(LL)] = { | ||
| 854 | [C(OP_READ)] = { | ||
| 855 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 856 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 857 | }, | ||
| 858 | [C(OP_WRITE)] = { | ||
| 859 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 860 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 861 | }, | ||
| 862 | [C(OP_PREFETCH)] = { | ||
| 863 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 864 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 865 | }, | ||
| 866 | }, | ||
| 867 | [C(DTLB)] = { | ||
| 868 | /* | ||
| 869 | * The ARM performance counters can count micro DTLB misses, | ||
| 870 | * micro ITLB misses and main TLB misses. There isn't an event | ||
| 871 | * for TLB misses, so use the micro misses here and if users | ||
| 872 | * want the main TLB misses they can use a raw counter. | ||
| 873 | */ | ||
| 874 | [C(OP_READ)] = { | ||
| 875 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 876 | [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS, | ||
| 877 | }, | ||
| 878 | [C(OP_WRITE)] = { | ||
| 879 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 880 | [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS, | ||
| 881 | }, | ||
| 882 | [C(OP_PREFETCH)] = { | ||
| 883 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 884 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 885 | }, | ||
| 886 | }, | ||
| 887 | [C(ITLB)] = { | ||
| 888 | [C(OP_READ)] = { | ||
| 889 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 890 | [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS, | ||
| 891 | }, | ||
| 892 | [C(OP_WRITE)] = { | ||
| 893 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 894 | [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS, | ||
| 895 | }, | ||
| 896 | [C(OP_PREFETCH)] = { | ||
| 897 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 898 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 899 | }, | ||
| 900 | }, | ||
| 901 | [C(BPU)] = { | ||
| 902 | [C(OP_READ)] = { | ||
| 903 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 904 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 905 | }, | ||
| 906 | [C(OP_WRITE)] = { | ||
| 907 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 908 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 909 | }, | ||
| 910 | [C(OP_PREFETCH)] = { | ||
| 911 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 912 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 913 | }, | ||
| 914 | }, | ||
| 915 | }; | ||
| 916 | |||
| 917 | static inline unsigned long | ||
| 918 | armv6_pmcr_read(void) | ||
| 919 | { | ||
| 920 | u32 val; | ||
| 921 | asm volatile("mrc p15, 0, %0, c15, c12, 0" : "=r"(val)); | ||
| 922 | return val; | ||
| 923 | } | ||
| 924 | |||
| 925 | static inline void | ||
| 926 | armv6_pmcr_write(unsigned long val) | ||
| 927 | { | ||
| 928 | asm volatile("mcr p15, 0, %0, c15, c12, 0" : : "r"(val)); | ||
| 929 | } | ||
| 930 | |||
| 931 | #define ARMV6_PMCR_ENABLE (1 << 0) | ||
| 932 | #define ARMV6_PMCR_CTR01_RESET (1 << 1) | ||
| 933 | #define ARMV6_PMCR_CCOUNT_RESET (1 << 2) | ||
| 934 | #define ARMV6_PMCR_CCOUNT_DIV (1 << 3) | ||
| 935 | #define ARMV6_PMCR_COUNT0_IEN (1 << 4) | ||
| 936 | #define ARMV6_PMCR_COUNT1_IEN (1 << 5) | ||
| 937 | #define ARMV6_PMCR_CCOUNT_IEN (1 << 6) | ||
| 938 | #define ARMV6_PMCR_COUNT0_OVERFLOW (1 << 8) | ||
| 939 | #define ARMV6_PMCR_COUNT1_OVERFLOW (1 << 9) | ||
| 940 | #define ARMV6_PMCR_CCOUNT_OVERFLOW (1 << 10) | ||
| 941 | #define ARMV6_PMCR_EVT_COUNT0_SHIFT 20 | ||
| 942 | #define ARMV6_PMCR_EVT_COUNT0_MASK (0xFF << ARMV6_PMCR_EVT_COUNT0_SHIFT) | ||
| 943 | #define ARMV6_PMCR_EVT_COUNT1_SHIFT 12 | ||
| 944 | #define ARMV6_PMCR_EVT_COUNT1_MASK (0xFF << ARMV6_PMCR_EVT_COUNT1_SHIFT) | ||
| 945 | |||
| 946 | #define ARMV6_PMCR_OVERFLOWED_MASK \ | ||
| 947 | (ARMV6_PMCR_COUNT0_OVERFLOW | ARMV6_PMCR_COUNT1_OVERFLOW | \ | ||
| 948 | ARMV6_PMCR_CCOUNT_OVERFLOW) | ||
| 949 | |||
| 950 | static inline int | ||
| 951 | armv6_pmcr_has_overflowed(unsigned long pmcr) | ||
| 952 | { | ||
| 953 | return (pmcr & ARMV6_PMCR_OVERFLOWED_MASK); | ||
| 954 | } | ||
| 955 | |||
| 956 | static inline int | ||
| 957 | armv6_pmcr_counter_has_overflowed(unsigned long pmcr, | ||
| 958 | enum armv6_counters counter) | ||
| 959 | { | ||
| 960 | int ret = 0; | ||
| 961 | |||
| 962 | if (ARMV6_CYCLE_COUNTER == counter) | ||
| 963 | ret = pmcr & ARMV6_PMCR_CCOUNT_OVERFLOW; | ||
| 964 | else if (ARMV6_COUNTER0 == counter) | ||
| 965 | ret = pmcr & ARMV6_PMCR_COUNT0_OVERFLOW; | ||
| 966 | else if (ARMV6_COUNTER1 == counter) | ||
| 967 | ret = pmcr & ARMV6_PMCR_COUNT1_OVERFLOW; | ||
| 968 | else | ||
| 969 | WARN_ONCE(1, "invalid counter number (%d)\n", counter); | ||
| 970 | |||
| 971 | return ret; | ||
| 972 | } | ||
| 973 | |||
| 974 | static inline u32 | ||
| 975 | armv6pmu_read_counter(int counter) | ||
| 976 | { | ||
| 977 | unsigned long value = 0; | ||
| 978 | |||
| 979 | if (ARMV6_CYCLE_COUNTER == counter) | ||
| 980 | asm volatile("mrc p15, 0, %0, c15, c12, 1" : "=r"(value)); | ||
| 981 | else if (ARMV6_COUNTER0 == counter) | ||
| 982 | asm volatile("mrc p15, 0, %0, c15, c12, 2" : "=r"(value)); | ||
| 983 | else if (ARMV6_COUNTER1 == counter) | ||
| 984 | asm volatile("mrc p15, 0, %0, c15, c12, 3" : "=r"(value)); | ||
| 985 | else | ||
| 986 | WARN_ONCE(1, "invalid counter number (%d)\n", counter); | ||
| 987 | |||
| 988 | return value; | ||
| 989 | } | ||
| 990 | |||
| 991 | static inline void | ||
| 992 | armv6pmu_write_counter(int counter, | ||
| 993 | u32 value) | ||
| 994 | { | ||
| 995 | if (ARMV6_CYCLE_COUNTER == counter) | ||
| 996 | asm volatile("mcr p15, 0, %0, c15, c12, 1" : : "r"(value)); | ||
| 997 | else if (ARMV6_COUNTER0 == counter) | ||
| 998 | asm volatile("mcr p15, 0, %0, c15, c12, 2" : : "r"(value)); | ||
| 999 | else if (ARMV6_COUNTER1 == counter) | ||
| 1000 | asm volatile("mcr p15, 0, %0, c15, c12, 3" : : "r"(value)); | ||
| 1001 | else | ||
| 1002 | WARN_ONCE(1, "invalid counter number (%d)\n", counter); | ||
| 1003 | } | ||
| 1004 | |||
| 1005 | void | ||
| 1006 | armv6pmu_enable_event(struct hw_perf_event *hwc, | ||
| 1007 | int idx) | ||
| 1008 | { | ||
| 1009 | unsigned long val, mask, evt, flags; | ||
| 1010 | |||
| 1011 | if (ARMV6_CYCLE_COUNTER == idx) { | ||
| 1012 | mask = 0; | ||
| 1013 | evt = ARMV6_PMCR_CCOUNT_IEN; | ||
| 1014 | } else if (ARMV6_COUNTER0 == idx) { | ||
| 1015 | mask = ARMV6_PMCR_EVT_COUNT0_MASK; | ||
| 1016 | evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT0_SHIFT) | | ||
| 1017 | ARMV6_PMCR_COUNT0_IEN; | ||
| 1018 | } else if (ARMV6_COUNTER1 == idx) { | ||
| 1019 | mask = ARMV6_PMCR_EVT_COUNT1_MASK; | ||
| 1020 | evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT1_SHIFT) | | ||
| 1021 | ARMV6_PMCR_COUNT1_IEN; | ||
| 1022 | } else { | ||
| 1023 | WARN_ONCE(1, "invalid counter number (%d)\n", idx); | ||
| 1024 | return; | ||
| 1025 | } | ||
| 1026 | |||
| 1027 | /* | ||
| 1028 | * Mask out the current event and set the counter to count the event | ||
| 1029 | * that we're interested in. | ||
| 1030 | */ | ||
| 1031 | spin_lock_irqsave(&pmu_lock, flags); | ||
| 1032 | val = armv6_pmcr_read(); | ||
| 1033 | val &= ~mask; | ||
| 1034 | val |= evt; | ||
| 1035 | armv6_pmcr_write(val); | ||
| 1036 | spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 1037 | } | ||
| 1038 | |||
| 1039 | static irqreturn_t | ||
| 1040 | armv6pmu_handle_irq(int irq_num, | ||
| 1041 | void *dev) | ||
| 1042 | { | ||
| 1043 | unsigned long pmcr = armv6_pmcr_read(); | ||
| 1044 | struct perf_sample_data data; | ||
| 1045 | struct cpu_hw_events *cpuc; | ||
| 1046 | struct pt_regs *regs; | ||
| 1047 | int idx; | ||
| 1048 | |||
| 1049 | if (!armv6_pmcr_has_overflowed(pmcr)) | ||
| 1050 | return IRQ_NONE; | ||
| 1051 | |||
| 1052 | regs = get_irq_regs(); | ||
| 1053 | |||
| 1054 | /* | ||
| 1055 | * The interrupts are cleared by writing the overflow flags back to | ||
| 1056 | * the control register. All of the other bits don't have any effect | ||
| 1057 | * if they are rewritten, so write the whole value back. | ||
| 1058 | */ | ||
| 1059 | armv6_pmcr_write(pmcr); | ||
| 1060 | |||
| 1061 | perf_sample_data_init(&data, 0); | ||
| 1062 | |||
| 1063 | cpuc = &__get_cpu_var(cpu_hw_events); | ||
| 1064 | for (idx = 0; idx <= armpmu->num_events; ++idx) { | ||
| 1065 | struct perf_event *event = cpuc->events[idx]; | ||
| 1066 | struct hw_perf_event *hwc; | ||
| 1067 | |||
| 1068 | if (!test_bit(idx, cpuc->active_mask)) | ||
| 1069 | continue; | ||
| 1070 | |||
| 1071 | /* | ||
| 1072 | * We have a single interrupt for all counters. Check that | ||
| 1073 | * each counter has overflowed before we process it. | ||
| 1074 | */ | ||
| 1075 | if (!armv6_pmcr_counter_has_overflowed(pmcr, idx)) | ||
| 1076 | continue; | ||
| 1077 | |||
| 1078 | hwc = &event->hw; | ||
| 1079 | armpmu_event_update(event, hwc, idx); | ||
| 1080 | data.period = event->hw.last_period; | ||
| 1081 | if (!armpmu_event_set_period(event, hwc, idx)) | ||
| 1082 | continue; | ||
| 1083 | |||
| 1084 | if (perf_event_overflow(event, 0, &data, regs)) | ||
| 1085 | armpmu->disable(hwc, idx); | ||
| 1086 | } | ||
| 1087 | |||
| 1088 | /* | ||
| 1089 | * Handle the pending perf events. | ||
| 1090 | * | ||
| 1091 | * Note: this call *must* be run with interrupts disabled. For | ||
| 1092 | * platforms that can have the PMU interrupts raised as an NMI, this | ||
| 1093 | * will not work. | ||
| 1094 | */ | ||
| 1095 | irq_work_run(); | ||
| 1096 | |||
| 1097 | return IRQ_HANDLED; | ||
| 1098 | } | ||
| 1099 | |||
| 1100 | static void | ||
| 1101 | armv6pmu_start(void) | ||
| 1102 | { | ||
| 1103 | unsigned long flags, val; | ||
| 1104 | |||
| 1105 | spin_lock_irqsave(&pmu_lock, flags); | ||
| 1106 | val = armv6_pmcr_read(); | ||
| 1107 | val |= ARMV6_PMCR_ENABLE; | ||
| 1108 | armv6_pmcr_write(val); | ||
| 1109 | spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 1110 | } | ||
| 1111 | |||
| 1112 | void | ||
| 1113 | armv6pmu_stop(void) | ||
| 1114 | { | ||
| 1115 | unsigned long flags, val; | ||
| 1116 | |||
| 1117 | spin_lock_irqsave(&pmu_lock, flags); | ||
| 1118 | val = armv6_pmcr_read(); | ||
| 1119 | val &= ~ARMV6_PMCR_ENABLE; | ||
| 1120 | armv6_pmcr_write(val); | ||
| 1121 | spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 1122 | } | ||
| 1123 | |||
| 1124 | static inline int | ||
| 1125 | armv6pmu_event_map(int config) | ||
| 1126 | { | ||
| 1127 | int mapping = armv6_perf_map[config]; | ||
| 1128 | if (HW_OP_UNSUPPORTED == mapping) | ||
| 1129 | mapping = -EOPNOTSUPP; | ||
| 1130 | return mapping; | ||
| 1131 | } | ||
| 1132 | |||
| 1133 | static inline int | ||
| 1134 | armv6mpcore_pmu_event_map(int config) | ||
| 1135 | { | ||
| 1136 | int mapping = armv6mpcore_perf_map[config]; | ||
| 1137 | if (HW_OP_UNSUPPORTED == mapping) | ||
| 1138 | mapping = -EOPNOTSUPP; | ||
| 1139 | return mapping; | ||
| 1140 | } | ||
| 1141 | |||
| 1142 | static u64 | ||
| 1143 | armv6pmu_raw_event(u64 config) | ||
| 1144 | { | ||
| 1145 | return config & 0xff; | ||
| 1146 | } | ||
| 1147 | |||
| 1148 | static int | ||
| 1149 | armv6pmu_get_event_idx(struct cpu_hw_events *cpuc, | ||
| 1150 | struct hw_perf_event *event) | ||
| 1151 | { | ||
| 1152 | /* Always place a cycle counter into the cycle counter. */ | ||
| 1153 | if (ARMV6_PERFCTR_CPU_CYCLES == event->config_base) { | ||
| 1154 | if (test_and_set_bit(ARMV6_CYCLE_COUNTER, cpuc->used_mask)) | ||
| 1155 | return -EAGAIN; | ||
| 1156 | |||
| 1157 | return ARMV6_CYCLE_COUNTER; | ||
| 1158 | } else { | ||
| 1159 | /* | ||
| 1160 | * For anything other than a cycle counter, try and use | ||
| 1161 | * counter0 and counter1. | ||
| 1162 | */ | ||
| 1163 | if (!test_and_set_bit(ARMV6_COUNTER1, cpuc->used_mask)) { | ||
| 1164 | return ARMV6_COUNTER1; | ||
| 1165 | } | ||
| 1166 | |||
| 1167 | if (!test_and_set_bit(ARMV6_COUNTER0, cpuc->used_mask)) { | ||
| 1168 | return ARMV6_COUNTER0; | ||
| 1169 | } | ||
| 1170 | |||
| 1171 | /* The counters are all in use. */ | ||
| 1172 | return -EAGAIN; | ||
| 1173 | } | ||
| 1174 | } | ||
| 1175 | |||
| 1176 | static void | ||
| 1177 | armv6pmu_disable_event(struct hw_perf_event *hwc, | ||
| 1178 | int idx) | ||
| 1179 | { | ||
| 1180 | unsigned long val, mask, evt, flags; | ||
| 1181 | |||
| 1182 | if (ARMV6_CYCLE_COUNTER == idx) { | ||
| 1183 | mask = ARMV6_PMCR_CCOUNT_IEN; | ||
| 1184 | evt = 0; | ||
| 1185 | } else if (ARMV6_COUNTER0 == idx) { | ||
| 1186 | mask = ARMV6_PMCR_COUNT0_IEN | ARMV6_PMCR_EVT_COUNT0_MASK; | ||
| 1187 | evt = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT0_SHIFT; | ||
| 1188 | } else if (ARMV6_COUNTER1 == idx) { | ||
| 1189 | mask = ARMV6_PMCR_COUNT1_IEN | ARMV6_PMCR_EVT_COUNT1_MASK; | ||
| 1190 | evt = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT1_SHIFT; | ||
| 1191 | } else { | ||
| 1192 | WARN_ONCE(1, "invalid counter number (%d)\n", idx); | ||
| 1193 | return; | ||
| 1194 | } | ||
| 1195 | |||
| 1196 | /* | ||
| 1197 | * Mask out the current event and set the counter to count the number | ||
| 1198 | * of ETM bus signal assertion cycles. The external reporting should | ||
| 1199 | * be disabled and so this should never increment. | ||
| 1200 | */ | ||
| 1201 | spin_lock_irqsave(&pmu_lock, flags); | ||
| 1202 | val = armv6_pmcr_read(); | ||
| 1203 | val &= ~mask; | ||
| 1204 | val |= evt; | ||
| 1205 | armv6_pmcr_write(val); | ||
| 1206 | spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 1207 | } | ||
| 1208 | |||
| 1209 | static void | ||
| 1210 | armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc, | ||
| 1211 | int idx) | ||
| 1212 | { | ||
| 1213 | unsigned long val, mask, flags, evt = 0; | ||
| 1214 | |||
| 1215 | if (ARMV6_CYCLE_COUNTER == idx) { | ||
| 1216 | mask = ARMV6_PMCR_CCOUNT_IEN; | ||
| 1217 | } else if (ARMV6_COUNTER0 == idx) { | ||
| 1218 | mask = ARMV6_PMCR_COUNT0_IEN; | ||
| 1219 | } else if (ARMV6_COUNTER1 == idx) { | ||
| 1220 | mask = ARMV6_PMCR_COUNT1_IEN; | ||
| 1221 | } else { | ||
| 1222 | WARN_ONCE(1, "invalid counter number (%d)\n", idx); | ||
| 1223 | return; | ||
| 1224 | } | ||
| 1225 | |||
| 1226 | /* | ||
| 1227 | * Unlike UP ARMv6, we don't have a way of stopping the counters. We | ||
| 1228 | * simply disable the interrupt reporting. | ||
| 1229 | */ | ||
| 1230 | spin_lock_irqsave(&pmu_lock, flags); | ||
| 1231 | val = armv6_pmcr_read(); | ||
| 1232 | val &= ~mask; | ||
| 1233 | val |= evt; | ||
| 1234 | armv6_pmcr_write(val); | ||
| 1235 | spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 1236 | } | ||
| 1237 | |||
| 1238 | static const struct arm_pmu armv6pmu = { | ||
| 1239 | .id = ARM_PERF_PMU_ID_V6, | ||
| 1240 | .handle_irq = armv6pmu_handle_irq, | ||
| 1241 | .enable = armv6pmu_enable_event, | ||
| 1242 | .disable = armv6pmu_disable_event, | ||
| 1243 | .event_map = armv6pmu_event_map, | ||
| 1244 | .raw_event = armv6pmu_raw_event, | ||
| 1245 | .read_counter = armv6pmu_read_counter, | ||
| 1246 | .write_counter = armv6pmu_write_counter, | ||
| 1247 | .get_event_idx = armv6pmu_get_event_idx, | ||
| 1248 | .start = armv6pmu_start, | ||
| 1249 | .stop = armv6pmu_stop, | ||
| 1250 | .num_events = 3, | ||
| 1251 | .max_period = (1LLU << 32) - 1, | ||
| 1252 | }; | ||
| 1253 | |||
| 1254 | /* | ||
| 1255 | * ARMv6mpcore is almost identical to single core ARMv6 with the exception | ||
| 1256 | * that some of the events have different enumerations and that there is no | ||
| 1257 | * *hack* to stop the programmable counters. To stop the counters we simply | ||
| 1258 | * disable the interrupt reporting and update the event. When unthrottling we | ||
| 1259 | * reset the period and enable the interrupt reporting. | ||
| 1260 | */ | ||
| 1261 | static const struct arm_pmu armv6mpcore_pmu = { | ||
| 1262 | .id = ARM_PERF_PMU_ID_V6MP, | ||
| 1263 | .handle_irq = armv6pmu_handle_irq, | ||
| 1264 | .enable = armv6pmu_enable_event, | ||
| 1265 | .disable = armv6mpcore_pmu_disable_event, | ||
| 1266 | .event_map = armv6mpcore_pmu_event_map, | ||
| 1267 | .raw_event = armv6pmu_raw_event, | ||
| 1268 | .read_counter = armv6pmu_read_counter, | ||
| 1269 | .write_counter = armv6pmu_write_counter, | ||
| 1270 | .get_event_idx = armv6pmu_get_event_idx, | ||
| 1271 | .start = armv6pmu_start, | ||
| 1272 | .stop = armv6pmu_stop, | ||
| 1273 | .num_events = 3, | ||
| 1274 | .max_period = (1LLU << 32) - 1, | ||
| 1275 | }; | ||
| 1276 | |||
| 1277 | /* | ||
| 1278 | * ARMv7 Cortex-A8 and Cortex-A9 Performance Events handling code. | ||
| 1279 | * | ||
| 1280 | * Copied from ARMv6 code, with the low level code inspired | ||
| 1281 | * by the ARMv7 Oprofile code. | ||
| 1282 | * | ||
| 1283 | * Cortex-A8 has up to 4 configurable performance counters and | ||
| 1284 | * a single cycle counter. | ||
| 1285 | * Cortex-A9 has up to 31 configurable performance counters and | ||
| 1286 | * a single cycle counter. | ||
| 1287 | * | ||
| 1288 | * All counters can be enabled/disabled and IRQ masked separately. The cycle | ||
| 1289 | * counter and all 4 performance counters together can be reset separately. | ||
| 1290 | */ | ||
| 1291 | |||
| 1292 | /* Common ARMv7 event types */ | ||
| 1293 | enum armv7_perf_types { | ||
| 1294 | ARMV7_PERFCTR_PMNC_SW_INCR = 0x00, | ||
| 1295 | ARMV7_PERFCTR_IFETCH_MISS = 0x01, | ||
| 1296 | ARMV7_PERFCTR_ITLB_MISS = 0x02, | ||
| 1297 | ARMV7_PERFCTR_DCACHE_REFILL = 0x03, | ||
| 1298 | ARMV7_PERFCTR_DCACHE_ACCESS = 0x04, | ||
| 1299 | ARMV7_PERFCTR_DTLB_REFILL = 0x05, | ||
| 1300 | ARMV7_PERFCTR_DREAD = 0x06, | ||
| 1301 | ARMV7_PERFCTR_DWRITE = 0x07, | ||
| 1302 | |||
| 1303 | ARMV7_PERFCTR_EXC_TAKEN = 0x09, | ||
| 1304 | ARMV7_PERFCTR_EXC_EXECUTED = 0x0A, | ||
| 1305 | ARMV7_PERFCTR_CID_WRITE = 0x0B, | ||
| 1306 | /* ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS. | ||
| 1307 | * It counts: | ||
| 1308 | * - all branch instructions, | ||
| 1309 | * - instructions that explicitly write the PC, | ||
| 1310 | * - exception generating instructions. | ||
| 1311 | */ | ||
| 1312 | ARMV7_PERFCTR_PC_WRITE = 0x0C, | ||
| 1313 | ARMV7_PERFCTR_PC_IMM_BRANCH = 0x0D, | ||
| 1314 | ARMV7_PERFCTR_UNALIGNED_ACCESS = 0x0F, | ||
| 1315 | ARMV7_PERFCTR_PC_BRANCH_MIS_PRED = 0x10, | ||
| 1316 | ARMV7_PERFCTR_CLOCK_CYCLES = 0x11, | ||
| 1317 | |||
| 1318 | ARMV7_PERFCTR_PC_BRANCH_MIS_USED = 0x12, | ||
| 1319 | |||
| 1320 | ARMV7_PERFCTR_CPU_CYCLES = 0xFF | ||
| 1321 | }; | ||
| 1322 | |||
| 1323 | /* ARMv7 Cortex-A8 specific event types */ | ||
| 1324 | enum armv7_a8_perf_types { | ||
| 1325 | ARMV7_PERFCTR_INSTR_EXECUTED = 0x08, | ||
| 1326 | |||
| 1327 | ARMV7_PERFCTR_PC_PROC_RETURN = 0x0E, | ||
| 1328 | |||
| 1329 | ARMV7_PERFCTR_WRITE_BUFFER_FULL = 0x40, | ||
| 1330 | ARMV7_PERFCTR_L2_STORE_MERGED = 0x41, | ||
| 1331 | ARMV7_PERFCTR_L2_STORE_BUFF = 0x42, | ||
| 1332 | ARMV7_PERFCTR_L2_ACCESS = 0x43, | ||
| 1333 | ARMV7_PERFCTR_L2_CACH_MISS = 0x44, | ||
| 1334 | ARMV7_PERFCTR_AXI_READ_CYCLES = 0x45, | ||
| 1335 | ARMV7_PERFCTR_AXI_WRITE_CYCLES = 0x46, | ||
| 1336 | ARMV7_PERFCTR_MEMORY_REPLAY = 0x47, | ||
| 1337 | ARMV7_PERFCTR_UNALIGNED_ACCESS_REPLAY = 0x48, | ||
| 1338 | ARMV7_PERFCTR_L1_DATA_MISS = 0x49, | ||
| 1339 | ARMV7_PERFCTR_L1_INST_MISS = 0x4A, | ||
| 1340 | ARMV7_PERFCTR_L1_DATA_COLORING = 0x4B, | ||
| 1341 | ARMV7_PERFCTR_L1_NEON_DATA = 0x4C, | ||
| 1342 | ARMV7_PERFCTR_L1_NEON_CACH_DATA = 0x4D, | ||
| 1343 | ARMV7_PERFCTR_L2_NEON = 0x4E, | ||
| 1344 | ARMV7_PERFCTR_L2_NEON_HIT = 0x4F, | ||
| 1345 | ARMV7_PERFCTR_L1_INST = 0x50, | ||
| 1346 | ARMV7_PERFCTR_PC_RETURN_MIS_PRED = 0x51, | ||
| 1347 | ARMV7_PERFCTR_PC_BRANCH_FAILED = 0x52, | ||
| 1348 | ARMV7_PERFCTR_PC_BRANCH_TAKEN = 0x53, | ||
| 1349 | ARMV7_PERFCTR_PC_BRANCH_EXECUTED = 0x54, | ||
| 1350 | ARMV7_PERFCTR_OP_EXECUTED = 0x55, | ||
| 1351 | ARMV7_PERFCTR_CYCLES_INST_STALL = 0x56, | ||
| 1352 | ARMV7_PERFCTR_CYCLES_INST = 0x57, | ||
| 1353 | ARMV7_PERFCTR_CYCLES_NEON_DATA_STALL = 0x58, | ||
| 1354 | ARMV7_PERFCTR_CYCLES_NEON_INST_STALL = 0x59, | ||
| 1355 | ARMV7_PERFCTR_NEON_CYCLES = 0x5A, | ||
| 1356 | |||
| 1357 | ARMV7_PERFCTR_PMU0_EVENTS = 0x70, | ||
| 1358 | ARMV7_PERFCTR_PMU1_EVENTS = 0x71, | ||
| 1359 | ARMV7_PERFCTR_PMU_EVENTS = 0x72, | ||
| 1360 | }; | ||
| 1361 | |||
| 1362 | /* ARMv7 Cortex-A9 specific event types */ | ||
| 1363 | enum armv7_a9_perf_types { | ||
| 1364 | ARMV7_PERFCTR_JAVA_HW_BYTECODE_EXEC = 0x40, | ||
| 1365 | ARMV7_PERFCTR_JAVA_SW_BYTECODE_EXEC = 0x41, | ||
| 1366 | ARMV7_PERFCTR_JAZELLE_BRANCH_EXEC = 0x42, | ||
| 1367 | |||
| 1368 | ARMV7_PERFCTR_COHERENT_LINE_MISS = 0x50, | ||
| 1369 | ARMV7_PERFCTR_COHERENT_LINE_HIT = 0x51, | ||
| 1370 | |||
| 1371 | ARMV7_PERFCTR_ICACHE_DEP_STALL_CYCLES = 0x60, | ||
| 1372 | ARMV7_PERFCTR_DCACHE_DEP_STALL_CYCLES = 0x61, | ||
| 1373 | ARMV7_PERFCTR_TLB_MISS_DEP_STALL_CYCLES = 0x62, | ||
| 1374 | ARMV7_PERFCTR_STREX_EXECUTED_PASSED = 0x63, | ||
| 1375 | ARMV7_PERFCTR_STREX_EXECUTED_FAILED = 0x64, | ||
| 1376 | ARMV7_PERFCTR_DATA_EVICTION = 0x65, | ||
| 1377 | ARMV7_PERFCTR_ISSUE_STAGE_NO_INST = 0x66, | ||
| 1378 | ARMV7_PERFCTR_ISSUE_STAGE_EMPTY = 0x67, | ||
| 1379 | ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE = 0x68, | ||
| 1380 | |||
| 1381 | ARMV7_PERFCTR_PREDICTABLE_FUNCT_RETURNS = 0x6E, | ||
| 1382 | |||
| 1383 | ARMV7_PERFCTR_MAIN_UNIT_EXECUTED_INST = 0x70, | ||
| 1384 | ARMV7_PERFCTR_SECOND_UNIT_EXECUTED_INST = 0x71, | ||
| 1385 | ARMV7_PERFCTR_LD_ST_UNIT_EXECUTED_INST = 0x72, | ||
| 1386 | ARMV7_PERFCTR_FP_EXECUTED_INST = 0x73, | ||
| 1387 | ARMV7_PERFCTR_NEON_EXECUTED_INST = 0x74, | ||
| 1388 | |||
| 1389 | ARMV7_PERFCTR_PLD_FULL_DEP_STALL_CYCLES = 0x80, | ||
| 1390 | ARMV7_PERFCTR_DATA_WR_DEP_STALL_CYCLES = 0x81, | ||
| 1391 | ARMV7_PERFCTR_ITLB_MISS_DEP_STALL_CYCLES = 0x82, | ||
| 1392 | ARMV7_PERFCTR_DTLB_MISS_DEP_STALL_CYCLES = 0x83, | ||
| 1393 | ARMV7_PERFCTR_MICRO_ITLB_MISS_DEP_STALL_CYCLES = 0x84, | ||
| 1394 | ARMV7_PERFCTR_MICRO_DTLB_MISS_DEP_STALL_CYCLES = 0x85, | ||
| 1395 | ARMV7_PERFCTR_DMB_DEP_STALL_CYCLES = 0x86, | ||
| 1396 | |||
| 1397 | ARMV7_PERFCTR_INTGR_CLK_ENABLED_CYCLES = 0x8A, | ||
| 1398 | ARMV7_PERFCTR_DATA_ENGINE_CLK_EN_CYCLES = 0x8B, | ||
| 1399 | |||
| 1400 | ARMV7_PERFCTR_ISB_INST = 0x90, | ||
| 1401 | ARMV7_PERFCTR_DSB_INST = 0x91, | ||
| 1402 | ARMV7_PERFCTR_DMB_INST = 0x92, | ||
| 1403 | ARMV7_PERFCTR_EXT_INTERRUPTS = 0x93, | ||
| 1404 | |||
| 1405 | ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_COMPLETED = 0xA0, | ||
| 1406 | ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_SKIPPED = 0xA1, | ||
| 1407 | ARMV7_PERFCTR_PLE_FIFO_FLUSH = 0xA2, | ||
| 1408 | ARMV7_PERFCTR_PLE_RQST_COMPLETED = 0xA3, | ||
| 1409 | ARMV7_PERFCTR_PLE_FIFO_OVERFLOW = 0xA4, | ||
| 1410 | ARMV7_PERFCTR_PLE_RQST_PROG = 0xA5 | ||
| 1411 | }; | ||
| 1412 | |||
| 1413 | /* | ||
| 1414 | * Cortex-A8 HW events mapping | ||
| 1415 | * | ||
| 1416 | * The hardware events that we support. We do support cache operations but | ||
| 1417 | * we have harvard caches and no way to combine instruction and data | ||
| 1418 | * accesses/misses in hardware. | ||
| 1419 | */ | ||
| 1420 | static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = { | ||
| 1421 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, | ||
| 1422 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, | ||
| 1423 | [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, | ||
| 1424 | [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, | ||
| 1425 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, | ||
| 1426 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, | ||
| 1427 | [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, | ||
| 1428 | }; | ||
| 1429 | |||
| 1430 | static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | ||
| 1431 | [PERF_COUNT_HW_CACHE_OP_MAX] | ||
| 1432 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { | ||
| 1433 | [C(L1D)] = { | ||
| 1434 | /* | ||
| 1435 | * The performance counters don't differentiate between read | ||
| 1436 | * and write accesses/misses so this isn't strictly correct, | ||
| 1437 | * but it's the best we can do. Writes and reads get | ||
| 1438 | * combined. | ||
| 1439 | */ | ||
| 1440 | [C(OP_READ)] = { | ||
| 1441 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS, | ||
| 1442 | [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL, | ||
| 1443 | }, | ||
| 1444 | [C(OP_WRITE)] = { | ||
| 1445 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS, | ||
| 1446 | [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL, | ||
| 1447 | }, | ||
| 1448 | [C(OP_PREFETCH)] = { | ||
| 1449 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 1450 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 1451 | }, | ||
| 1452 | }, | ||
| 1453 | [C(L1I)] = { | ||
| 1454 | [C(OP_READ)] = { | ||
| 1455 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_INST, | ||
| 1456 | [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_INST_MISS, | ||
| 1457 | }, | ||
| 1458 | [C(OP_WRITE)] = { | ||
| 1459 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_INST, | ||
| 1460 | [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_INST_MISS, | ||
| 1461 | }, | ||
| 1462 | [C(OP_PREFETCH)] = { | ||
| 1463 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 1464 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 1465 | }, | ||
| 1466 | }, | ||
| 1467 | [C(LL)] = { | ||
| 1468 | [C(OP_READ)] = { | ||
| 1469 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_ACCESS, | ||
| 1470 | [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACH_MISS, | ||
| 1471 | }, | ||
| 1472 | [C(OP_WRITE)] = { | ||
| 1473 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_ACCESS, | ||
| 1474 | [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACH_MISS, | ||
| 1475 | }, | ||
| 1476 | [C(OP_PREFETCH)] = { | ||
| 1477 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 1478 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 1479 | }, | ||
| 1480 | }, | ||
| 1481 | [C(DTLB)] = { | ||
| 1482 | /* | ||
| 1483 | * Only ITLB misses and DTLB refills are supported. | ||
| 1484 | * If users want the DTLB refills misses a raw counter | ||
| 1485 | * must be used. | ||
| 1486 | */ | ||
| 1487 | [C(OP_READ)] = { | ||
| 1488 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 1489 | [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, | ||
| 1490 | }, | ||
| 1491 | [C(OP_WRITE)] = { | ||
| 1492 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 1493 | [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, | ||
| 1494 | }, | ||
| 1495 | [C(OP_PREFETCH)] = { | ||
| 1496 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 1497 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 1498 | }, | ||
| 1499 | }, | ||
| 1500 | [C(ITLB)] = { | ||
| 1501 | [C(OP_READ)] = { | ||
| 1502 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 1503 | [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS, | ||
| 1504 | }, | ||
| 1505 | [C(OP_WRITE)] = { | ||
| 1506 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 1507 | [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS, | ||
| 1508 | }, | ||
| 1509 | [C(OP_PREFETCH)] = { | ||
| 1510 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 1511 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 1512 | }, | ||
| 1513 | }, | ||
| 1514 | [C(BPU)] = { | ||
| 1515 | [C(OP_READ)] = { | ||
| 1516 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE, | ||
| 1517 | [C(RESULT_MISS)] | ||
| 1518 | = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, | ||
| 1519 | }, | ||
| 1520 | [C(OP_WRITE)] = { | ||
| 1521 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE, | ||
| 1522 | [C(RESULT_MISS)] | ||
| 1523 | = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, | ||
| 1524 | }, | ||
| 1525 | [C(OP_PREFETCH)] = { | ||
| 1526 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 1527 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 1528 | }, | ||
| 1529 | }, | ||
| 1530 | }; | ||
| 1531 | |||
| 1532 | /* | ||
| 1533 | * Cortex-A9 HW events mapping | ||
| 1534 | */ | ||
| 1535 | static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = { | ||
| 1536 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, | ||
| 1537 | [PERF_COUNT_HW_INSTRUCTIONS] = | ||
| 1538 | ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE, | ||
| 1539 | [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_COHERENT_LINE_HIT, | ||
| 1540 | [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_COHERENT_LINE_MISS, | ||
| 1541 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, | ||
| 1542 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, | ||
| 1543 | [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, | ||
| 1544 | }; | ||
| 1545 | |||
| 1546 | static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | ||
| 1547 | [PERF_COUNT_HW_CACHE_OP_MAX] | ||
| 1548 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { | ||
| 1549 | [C(L1D)] = { | ||
| 1550 | /* | ||
| 1551 | * The performance counters don't differentiate between read | ||
| 1552 | * and write accesses/misses so this isn't strictly correct, | ||
| 1553 | * but it's the best we can do. Writes and reads get | ||
| 1554 | * combined. | ||
| 1555 | */ | ||
| 1556 | [C(OP_READ)] = { | ||
| 1557 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS, | ||
| 1558 | [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL, | ||
| 1559 | }, | ||
| 1560 | [C(OP_WRITE)] = { | ||
| 1561 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS, | ||
| 1562 | [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL, | ||
| 1563 | }, | ||
| 1564 | [C(OP_PREFETCH)] = { | ||
| 1565 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 1566 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 1567 | }, | ||
| 1568 | }, | ||
| 1569 | [C(L1I)] = { | ||
| 1570 | [C(OP_READ)] = { | ||
| 1571 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 1572 | [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS, | ||
| 1573 | }, | ||
| 1574 | [C(OP_WRITE)] = { | ||
| 1575 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 1576 | [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS, | ||
| 1577 | }, | ||
| 1578 | [C(OP_PREFETCH)] = { | ||
| 1579 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 1580 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 1581 | }, | ||
| 1582 | }, | ||
| 1583 | [C(LL)] = { | ||
| 1584 | [C(OP_READ)] = { | ||
| 1585 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 1586 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 1587 | }, | ||
| 1588 | [C(OP_WRITE)] = { | ||
| 1589 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 1590 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 1591 | }, | ||
| 1592 | [C(OP_PREFETCH)] = { | ||
| 1593 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 1594 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 1595 | }, | ||
| 1596 | }, | ||
| 1597 | [C(DTLB)] = { | ||
| 1598 | /* | ||
| 1599 | * Only ITLB misses and DTLB refills are supported. | ||
| 1600 | * If users want the DTLB refills misses a raw counter | ||
| 1601 | * must be used. | ||
| 1602 | */ | ||
| 1603 | [C(OP_READ)] = { | ||
| 1604 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 1605 | [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, | ||
| 1606 | }, | ||
| 1607 | [C(OP_WRITE)] = { | ||
| 1608 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 1609 | [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, | ||
| 1610 | }, | ||
| 1611 | [C(OP_PREFETCH)] = { | ||
| 1612 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 1613 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 1614 | }, | ||
| 1615 | }, | ||
| 1616 | [C(ITLB)] = { | ||
| 1617 | [C(OP_READ)] = { | ||
| 1618 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 1619 | [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS, | ||
| 1620 | }, | ||
| 1621 | [C(OP_WRITE)] = { | ||
| 1622 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 1623 | [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS, | ||
| 1624 | }, | ||
| 1625 | [C(OP_PREFETCH)] = { | ||
| 1626 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 1627 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 1628 | }, | ||
| 1629 | }, | ||
| 1630 | [C(BPU)] = { | ||
| 1631 | [C(OP_READ)] = { | ||
| 1632 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE, | ||
| 1633 | [C(RESULT_MISS)] | ||
| 1634 | = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, | ||
| 1635 | }, | ||
| 1636 | [C(OP_WRITE)] = { | ||
| 1637 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE, | ||
| 1638 | [C(RESULT_MISS)] | ||
| 1639 | = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, | ||
| 1640 | }, | ||
| 1641 | [C(OP_PREFETCH)] = { | ||
| 1642 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 1643 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 1644 | }, | ||
| 1645 | }, | ||
| 1646 | }; | ||
| 1647 | |||
| 1648 | /* | ||
| 1649 | * Perf Events counters | ||
| 1650 | */ | ||
| 1651 | enum armv7_counters { | ||
| 1652 | ARMV7_CYCLE_COUNTER = 1, /* Cycle counter */ | ||
| 1653 | ARMV7_COUNTER0 = 2, /* First event counter */ | ||
| 1654 | }; | ||
| 1655 | |||
| 1656 | /* | ||
| 1657 | * The cycle counter is ARMV7_CYCLE_COUNTER. | ||
| 1658 | * The first event counter is ARMV7_COUNTER0. | ||
| 1659 | * The last event counter is (ARMV7_COUNTER0 + armpmu->num_events - 1). | ||
| 1660 | */ | ||
| 1661 | #define ARMV7_COUNTER_LAST (ARMV7_COUNTER0 + armpmu->num_events - 1) | ||
| 1662 | |||
| 1663 | /* | ||
| 1664 | * ARMv7 low level PMNC access | ||
| 1665 | */ | ||
| 1666 | |||
| 1667 | /* | ||
| 1668 | * Per-CPU PMNC: config reg | ||
| 1669 | */ | ||
| 1670 | #define ARMV7_PMNC_E (1 << 0) /* Enable all counters */ | ||
| 1671 | #define ARMV7_PMNC_P (1 << 1) /* Reset all counters */ | ||
| 1672 | #define ARMV7_PMNC_C (1 << 2) /* Cycle counter reset */ | ||
| 1673 | #define ARMV7_PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */ | ||
| 1674 | #define ARMV7_PMNC_X (1 << 4) /* Export to ETM */ | ||
| 1675 | #define ARMV7_PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ | ||
| 1676 | #define ARMV7_PMNC_N_SHIFT 11 /* Number of counters supported */ | ||
| 1677 | #define ARMV7_PMNC_N_MASK 0x1f | ||
| 1678 | #define ARMV7_PMNC_MASK 0x3f /* Mask for writable bits */ | ||
| 1679 | |||
| 1680 | /* | ||
| 1681 | * Available counters | ||
| 1682 | */ | ||
| 1683 | #define ARMV7_CNT0 0 /* First event counter */ | ||
| 1684 | #define ARMV7_CCNT 31 /* Cycle counter */ | ||
| 1685 | |||
| 1686 | /* Perf Event to low level counters mapping */ | ||
| 1687 | #define ARMV7_EVENT_CNT_TO_CNTx (ARMV7_COUNTER0 - ARMV7_CNT0) | ||
| 1688 | |||
| 1689 | /* | ||
| 1690 | * CNTENS: counters enable reg | ||
| 1691 | */ | ||
| 1692 | #define ARMV7_CNTENS_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx)) | ||
| 1693 | #define ARMV7_CNTENS_C (1 << ARMV7_CCNT) | ||
| 1694 | |||
| 1695 | /* | ||
| 1696 | * CNTENC: counters disable reg | ||
| 1697 | */ | ||
| 1698 | #define ARMV7_CNTENC_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx)) | ||
| 1699 | #define ARMV7_CNTENC_C (1 << ARMV7_CCNT) | ||
| 1700 | |||
| 1701 | /* | ||
| 1702 | * INTENS: counters overflow interrupt enable reg | ||
| 1703 | */ | ||
| 1704 | #define ARMV7_INTENS_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx)) | ||
| 1705 | #define ARMV7_INTENS_C (1 << ARMV7_CCNT) | ||
| 1706 | |||
| 1707 | /* | ||
| 1708 | * INTENC: counters overflow interrupt disable reg | ||
| 1709 | */ | ||
| 1710 | #define ARMV7_INTENC_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx)) | ||
| 1711 | #define ARMV7_INTENC_C (1 << ARMV7_CCNT) | ||
| 1712 | |||
| 1713 | /* | ||
| 1714 | * EVTSEL: Event selection reg | ||
| 1715 | */ | ||
| 1716 | #define ARMV7_EVTSEL_MASK 0xff /* Mask for writable bits */ | ||
| 1717 | |||
| 1718 | /* | ||
| 1719 | * SELECT: Counter selection reg | ||
| 1720 | */ | ||
| 1721 | #define ARMV7_SELECT_MASK 0x1f /* Mask for writable bits */ | ||
| 1722 | |||
| 1723 | /* | ||
| 1724 | * FLAG: counters overflow flag status reg | ||
| 1725 | */ | ||
| 1726 | #define ARMV7_FLAG_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx)) | ||
| 1727 | #define ARMV7_FLAG_C (1 << ARMV7_CCNT) | ||
| 1728 | #define ARMV7_FLAG_MASK 0xffffffff /* Mask for writable bits */ | ||
| 1729 | #define ARMV7_OVERFLOWED_MASK ARMV7_FLAG_MASK | ||
| 1730 | |||
| 1731 | static inline unsigned long armv7_pmnc_read(void) | ||
| 1732 | { | ||
| 1733 | u32 val; | ||
| 1734 | asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val)); | ||
| 1735 | return val; | ||
| 1736 | } | ||
| 1737 | |||
| 1738 | static inline void armv7_pmnc_write(unsigned long val) | ||
| 1739 | { | ||
| 1740 | val &= ARMV7_PMNC_MASK; | ||
| 1741 | asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val)); | ||
| 1742 | } | ||
| 1743 | |||
| 1744 | static inline int armv7_pmnc_has_overflowed(unsigned long pmnc) | ||
| 1745 | { | ||
| 1746 | return pmnc & ARMV7_OVERFLOWED_MASK; | ||
| 1747 | } | ||
| 1748 | |||
| 1749 | static inline int armv7_pmnc_counter_has_overflowed(unsigned long pmnc, | ||
| 1750 | enum armv7_counters counter) | ||
| 1751 | { | ||
| 1752 | int ret = 0; | ||
| 1753 | |||
| 1754 | if (counter == ARMV7_CYCLE_COUNTER) | ||
| 1755 | ret = pmnc & ARMV7_FLAG_C; | ||
| 1756 | else if ((counter >= ARMV7_COUNTER0) && (counter <= ARMV7_COUNTER_LAST)) | ||
| 1757 | ret = pmnc & ARMV7_FLAG_P(counter); | ||
| 1758 | else | ||
| 1759 | pr_err("CPU%u checking wrong counter %d overflow status\n", | ||
| 1760 | smp_processor_id(), counter); | ||
| 1761 | |||
| 1762 | return ret; | ||
| 1763 | } | ||
| 1764 | |||
| 1765 | static inline int armv7_pmnc_select_counter(unsigned int idx) | ||
| 1766 | { | ||
| 1767 | u32 val; | ||
| 1768 | |||
| 1769 | if ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST)) { | ||
| 1770 | pr_err("CPU%u selecting wrong PMNC counter" | ||
| 1771 | " %d\n", smp_processor_id(), idx); | ||
| 1772 | return -1; | ||
| 1773 | } | ||
| 1774 | |||
| 1775 | val = (idx - ARMV7_EVENT_CNT_TO_CNTx) & ARMV7_SELECT_MASK; | ||
| 1776 | asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val)); | ||
| 1777 | |||
| 1778 | return idx; | ||
| 1779 | } | ||
| 1780 | |||
| 1781 | static inline u32 armv7pmu_read_counter(int idx) | ||
| 1782 | { | ||
| 1783 | unsigned long value = 0; | ||
| 1784 | |||
| 1785 | if (idx == ARMV7_CYCLE_COUNTER) | ||
| 1786 | asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value)); | ||
| 1787 | else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) { | ||
| 1788 | if (armv7_pmnc_select_counter(idx) == idx) | ||
| 1789 | asm volatile("mrc p15, 0, %0, c9, c13, 2" | ||
| 1790 | : "=r" (value)); | ||
| 1791 | } else | ||
| 1792 | pr_err("CPU%u reading wrong counter %d\n", | ||
| 1793 | smp_processor_id(), idx); | ||
| 1794 | |||
| 1795 | return value; | ||
| 1796 | } | ||
| 1797 | |||
| 1798 | static inline void armv7pmu_write_counter(int idx, u32 value) | ||
| 1799 | { | ||
| 1800 | if (idx == ARMV7_CYCLE_COUNTER) | ||
| 1801 | asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (value)); | ||
| 1802 | else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) { | ||
| 1803 | if (armv7_pmnc_select_counter(idx) == idx) | ||
| 1804 | asm volatile("mcr p15, 0, %0, c9, c13, 2" | ||
| 1805 | : : "r" (value)); | ||
| 1806 | } else | ||
| 1807 | pr_err("CPU%u writing wrong counter %d\n", | ||
| 1808 | smp_processor_id(), idx); | ||
| 1809 | } | ||
| 1810 | |||
| 1811 | static inline void armv7_pmnc_write_evtsel(unsigned int idx, u32 val) | ||
| 1812 | { | ||
| 1813 | if (armv7_pmnc_select_counter(idx) == idx) { | ||
| 1814 | val &= ARMV7_EVTSEL_MASK; | ||
| 1815 | asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val)); | ||
| 1816 | } | ||
| 1817 | } | ||
| 1818 | |||
| 1819 | static inline u32 armv7_pmnc_enable_counter(unsigned int idx) | ||
| 1820 | { | ||
| 1821 | u32 val; | ||
| 1822 | |||
| 1823 | if ((idx != ARMV7_CYCLE_COUNTER) && | ||
| 1824 | ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) { | ||
| 1825 | pr_err("CPU%u enabling wrong PMNC counter" | ||
| 1826 | " %d\n", smp_processor_id(), idx); | ||
| 1827 | return -1; | ||
| 1828 | } | ||
| 1829 | |||
| 1830 | if (idx == ARMV7_CYCLE_COUNTER) | ||
| 1831 | val = ARMV7_CNTENS_C; | ||
| 1832 | else | ||
| 1833 | val = ARMV7_CNTENS_P(idx); | ||
| 1834 | |||
| 1835 | asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (val)); | ||
| 1836 | |||
| 1837 | return idx; | ||
| 1838 | } | ||
| 1839 | |||
| 1840 | static inline u32 armv7_pmnc_disable_counter(unsigned int idx) | ||
| 1841 | { | ||
| 1842 | u32 val; | ||
| 1843 | |||
| 1844 | |||
| 1845 | if ((idx != ARMV7_CYCLE_COUNTER) && | ||
| 1846 | ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) { | ||
| 1847 | pr_err("CPU%u disabling wrong PMNC counter" | ||
| 1848 | " %d\n", smp_processor_id(), idx); | ||
| 1849 | return -1; | ||
| 1850 | } | ||
| 1851 | |||
| 1852 | if (idx == ARMV7_CYCLE_COUNTER) | ||
| 1853 | val = ARMV7_CNTENC_C; | ||
| 1854 | else | ||
| 1855 | val = ARMV7_CNTENC_P(idx); | ||
| 1856 | |||
| 1857 | asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (val)); | ||
| 1858 | |||
| 1859 | return idx; | ||
| 1860 | } | ||
| 1861 | |||
| 1862 | static inline u32 armv7_pmnc_enable_intens(unsigned int idx) | ||
| 1863 | { | ||
| 1864 | u32 val; | ||
| 1865 | |||
| 1866 | if ((idx != ARMV7_CYCLE_COUNTER) && | ||
| 1867 | ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) { | ||
| 1868 | pr_err("CPU%u enabling wrong PMNC counter" | ||
| 1869 | " interrupt enable %d\n", smp_processor_id(), idx); | ||
| 1870 | return -1; | ||
| 1871 | } | ||
| 1872 | |||
| 1873 | if (idx == ARMV7_CYCLE_COUNTER) | ||
| 1874 | val = ARMV7_INTENS_C; | ||
| 1875 | else | ||
| 1876 | val = ARMV7_INTENS_P(idx); | ||
| 1877 | |||
| 1878 | asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (val)); | ||
| 1879 | |||
| 1880 | return idx; | ||
| 1881 | } | ||
| 1882 | |||
| 1883 | static inline u32 armv7_pmnc_disable_intens(unsigned int idx) | ||
| 1884 | { | ||
| 1885 | u32 val; | ||
| 1886 | |||
| 1887 | if ((idx != ARMV7_CYCLE_COUNTER) && | ||
| 1888 | ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) { | ||
| 1889 | pr_err("CPU%u disabling wrong PMNC counter" | ||
| 1890 | " interrupt enable %d\n", smp_processor_id(), idx); | ||
| 1891 | return -1; | ||
| 1892 | } | ||
| 1893 | |||
| 1894 | if (idx == ARMV7_CYCLE_COUNTER) | ||
| 1895 | val = ARMV7_INTENC_C; | ||
| 1896 | else | ||
| 1897 | val = ARMV7_INTENC_P(idx); | ||
| 1898 | |||
| 1899 | asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (val)); | ||
| 1900 | |||
| 1901 | return idx; | ||
| 1902 | } | ||
| 1903 | |||
| 1904 | static inline u32 armv7_pmnc_getreset_flags(void) | ||
| 1905 | { | ||
| 1906 | u32 val; | ||
| 1907 | |||
| 1908 | /* Read */ | ||
| 1909 | asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); | ||
| 1910 | |||
| 1911 | /* Write to clear flags */ | ||
| 1912 | val &= ARMV7_FLAG_MASK; | ||
| 1913 | asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val)); | ||
| 1914 | |||
| 1915 | return val; | ||
| 1916 | } | ||
| 1917 | |||
| 1918 | #ifdef DEBUG | ||
| 1919 | static void armv7_pmnc_dump_regs(void) | ||
| 1920 | { | ||
| 1921 | u32 val; | ||
| 1922 | unsigned int cnt; | ||
| 1923 | |||
| 1924 | printk(KERN_INFO "PMNC registers dump:\n"); | ||
| 1925 | |||
| 1926 | asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val)); | ||
| 1927 | printk(KERN_INFO "PMNC =0x%08x\n", val); | ||
| 1928 | |||
| 1929 | asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val)); | ||
| 1930 | printk(KERN_INFO "CNTENS=0x%08x\n", val); | ||
| 1931 | |||
| 1932 | asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val)); | ||
| 1933 | printk(KERN_INFO "INTENS=0x%08x\n", val); | ||
| 1934 | |||
| 1935 | asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); | ||
| 1936 | printk(KERN_INFO "FLAGS =0x%08x\n", val); | ||
| 1937 | |||
| 1938 | asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val)); | ||
| 1939 | printk(KERN_INFO "SELECT=0x%08x\n", val); | ||
| 1940 | |||
| 1941 | asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val)); | ||
| 1942 | printk(KERN_INFO "CCNT =0x%08x\n", val); | ||
| 1943 | |||
| 1944 | for (cnt = ARMV7_COUNTER0; cnt < ARMV7_COUNTER_LAST; cnt++) { | ||
| 1945 | armv7_pmnc_select_counter(cnt); | ||
| 1946 | asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val)); | ||
| 1947 | printk(KERN_INFO "CNT[%d] count =0x%08x\n", | ||
| 1948 | cnt-ARMV7_EVENT_CNT_TO_CNTx, val); | ||
| 1949 | asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val)); | ||
| 1950 | printk(KERN_INFO "CNT[%d] evtsel=0x%08x\n", | ||
| 1951 | cnt-ARMV7_EVENT_CNT_TO_CNTx, val); | ||
| 1952 | } | ||
| 1953 | } | ||
| 1954 | #endif | ||
| 1955 | |||
| 1956 | void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx) | ||
| 1957 | { | ||
| 1958 | unsigned long flags; | ||
| 1959 | |||
| 1960 | /* | ||
| 1961 | * Enable counter and interrupt, and set the counter to count | ||
| 1962 | * the event that we're interested in. | ||
| 1963 | */ | ||
| 1964 | spin_lock_irqsave(&pmu_lock, flags); | ||
| 1965 | |||
| 1966 | /* | ||
| 1967 | * Disable counter | ||
| 1968 | */ | ||
| 1969 | armv7_pmnc_disable_counter(idx); | ||
| 1970 | |||
| 1971 | /* | ||
| 1972 | * Set event (if destined for PMNx counters) | ||
| 1973 | * We don't need to set the event if it's a cycle count | ||
| 1974 | */ | ||
| 1975 | if (idx != ARMV7_CYCLE_COUNTER) | ||
| 1976 | armv7_pmnc_write_evtsel(idx, hwc->config_base); | ||
| 1977 | |||
| 1978 | /* | ||
| 1979 | * Enable interrupt for this counter | ||
| 1980 | */ | ||
| 1981 | armv7_pmnc_enable_intens(idx); | ||
| 1982 | |||
| 1983 | /* | ||
| 1984 | * Enable counter | ||
| 1985 | */ | ||
| 1986 | armv7_pmnc_enable_counter(idx); | ||
| 1987 | |||
| 1988 | spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 1989 | } | ||
| 1990 | |||
| 1991 | static void armv7pmu_disable_event(struct hw_perf_event *hwc, int idx) | ||
| 1992 | { | ||
| 1993 | unsigned long flags; | ||
| 1994 | |||
| 1995 | /* | ||
| 1996 | * Disable counter and interrupt | ||
| 1997 | */ | ||
| 1998 | spin_lock_irqsave(&pmu_lock, flags); | ||
| 1999 | |||
| 2000 | /* | ||
| 2001 | * Disable counter | ||
| 2002 | */ | ||
| 2003 | armv7_pmnc_disable_counter(idx); | ||
| 2004 | |||
| 2005 | /* | ||
| 2006 | * Disable interrupt for this counter | ||
| 2007 | */ | ||
| 2008 | armv7_pmnc_disable_intens(idx); | ||
| 2009 | |||
| 2010 | spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 2011 | } | ||
| 2012 | |||
| 2013 | static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev) | ||
| 2014 | { | ||
| 2015 | unsigned long pmnc; | ||
| 2016 | struct perf_sample_data data; | ||
| 2017 | struct cpu_hw_events *cpuc; | ||
| 2018 | struct pt_regs *regs; | ||
| 2019 | int idx; | ||
| 2020 | |||
| 2021 | /* | ||
| 2022 | * Get and reset the IRQ flags | ||
| 2023 | */ | ||
| 2024 | pmnc = armv7_pmnc_getreset_flags(); | ||
| 2025 | |||
| 2026 | /* | ||
| 2027 | * Did an overflow occur? | ||
| 2028 | */ | ||
| 2029 | if (!armv7_pmnc_has_overflowed(pmnc)) | ||
| 2030 | return IRQ_NONE; | ||
| 2031 | |||
| 2032 | /* | ||
| 2033 | * Handle the counter(s) overflow(s) | ||
| 2034 | */ | ||
| 2035 | regs = get_irq_regs(); | ||
| 2036 | |||
| 2037 | perf_sample_data_init(&data, 0); | ||
| 2038 | |||
| 2039 | cpuc = &__get_cpu_var(cpu_hw_events); | ||
| 2040 | for (idx = 0; idx <= armpmu->num_events; ++idx) { | ||
| 2041 | struct perf_event *event = cpuc->events[idx]; | ||
| 2042 | struct hw_perf_event *hwc; | ||
| 2043 | |||
| 2044 | if (!test_bit(idx, cpuc->active_mask)) | ||
| 2045 | continue; | ||
| 2046 | |||
| 2047 | /* | ||
| 2048 | * We have a single interrupt for all counters. Check that | ||
| 2049 | * each counter has overflowed before we process it. | ||
| 2050 | */ | ||
| 2051 | if (!armv7_pmnc_counter_has_overflowed(pmnc, idx)) | ||
| 2052 | continue; | ||
| 2053 | |||
| 2054 | hwc = &event->hw; | ||
| 2055 | armpmu_event_update(event, hwc, idx); | ||
| 2056 | data.period = event->hw.last_period; | ||
| 2057 | if (!armpmu_event_set_period(event, hwc, idx)) | ||
| 2058 | continue; | ||
| 2059 | |||
| 2060 | if (perf_event_overflow(event, 0, &data, regs)) | ||
| 2061 | armpmu->disable(hwc, idx); | ||
| 2062 | } | ||
| 2063 | |||
| 2064 | /* | ||
| 2065 | * Handle the pending perf events. | ||
| 2066 | * | ||
| 2067 | * Note: this call *must* be run with interrupts disabled. For | ||
| 2068 | * platforms that can have the PMU interrupts raised as an NMI, this | ||
| 2069 | * will not work. | ||
| 2070 | */ | ||
| 2071 | irq_work_run(); | ||
| 2072 | |||
| 2073 | return IRQ_HANDLED; | ||
| 2074 | } | ||
| 2075 | |||
| 2076 | static void armv7pmu_start(void) | ||
| 2077 | { | ||
| 2078 | unsigned long flags; | ||
| 2079 | |||
| 2080 | spin_lock_irqsave(&pmu_lock, flags); | ||
| 2081 | /* Enable all counters */ | ||
| 2082 | armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_E); | ||
| 2083 | spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 2084 | } | ||
| 2085 | |||
| 2086 | static void armv7pmu_stop(void) | ||
| 2087 | { | ||
| 2088 | unsigned long flags; | ||
| 2089 | |||
| 2090 | spin_lock_irqsave(&pmu_lock, flags); | ||
| 2091 | /* Disable all counters */ | ||
| 2092 | armv7_pmnc_write(armv7_pmnc_read() & ~ARMV7_PMNC_E); | ||
| 2093 | spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 2094 | } | ||
| 2095 | |||
| 2096 | static inline int armv7_a8_pmu_event_map(int config) | ||
| 2097 | { | ||
| 2098 | int mapping = armv7_a8_perf_map[config]; | ||
| 2099 | if (HW_OP_UNSUPPORTED == mapping) | ||
| 2100 | mapping = -EOPNOTSUPP; | ||
| 2101 | return mapping; | ||
| 2102 | } | ||
| 2103 | |||
| 2104 | static inline int armv7_a9_pmu_event_map(int config) | ||
| 2105 | { | ||
| 2106 | int mapping = armv7_a9_perf_map[config]; | ||
| 2107 | if (HW_OP_UNSUPPORTED == mapping) | ||
| 2108 | mapping = -EOPNOTSUPP; | ||
| 2109 | return mapping; | ||
| 2110 | } | ||
| 2111 | |||
| 2112 | static u64 armv7pmu_raw_event(u64 config) | ||
| 2113 | { | ||
| 2114 | return config & 0xff; | ||
| 2115 | } | ||
| 2116 | |||
| 2117 | static int armv7pmu_get_event_idx(struct cpu_hw_events *cpuc, | ||
| 2118 | struct hw_perf_event *event) | ||
| 2119 | { | ||
| 2120 | int idx; | ||
| 2121 | |||
| 2122 | /* Always place a cycle counter into the cycle counter. */ | ||
| 2123 | if (event->config_base == ARMV7_PERFCTR_CPU_CYCLES) { | ||
| 2124 | if (test_and_set_bit(ARMV7_CYCLE_COUNTER, cpuc->used_mask)) | ||
| 2125 | return -EAGAIN; | ||
| 2126 | |||
| 2127 | return ARMV7_CYCLE_COUNTER; | ||
| 2128 | } else { | ||
| 2129 | /* | ||
| 2130 | * For anything other than a cycle counter, try and use | ||
| 2131 | * the events counters | ||
| 2132 | */ | ||
| 2133 | for (idx = ARMV7_COUNTER0; idx <= armpmu->num_events; ++idx) { | ||
| 2134 | if (!test_and_set_bit(idx, cpuc->used_mask)) | ||
| 2135 | return idx; | ||
| 2136 | } | ||
| 2137 | |||
| 2138 | /* The counters are all in use. */ | ||
| 2139 | return -EAGAIN; | ||
| 2140 | } | ||
| 2141 | } | ||
| 2142 | |||
| 2143 | static struct arm_pmu armv7pmu = { | ||
| 2144 | .handle_irq = armv7pmu_handle_irq, | ||
| 2145 | .enable = armv7pmu_enable_event, | ||
| 2146 | .disable = armv7pmu_disable_event, | ||
| 2147 | .raw_event = armv7pmu_raw_event, | ||
| 2148 | .read_counter = armv7pmu_read_counter, | ||
| 2149 | .write_counter = armv7pmu_write_counter, | ||
| 2150 | .get_event_idx = armv7pmu_get_event_idx, | ||
| 2151 | .start = armv7pmu_start, | ||
| 2152 | .stop = armv7pmu_stop, | ||
| 2153 | .max_period = (1LLU << 32) - 1, | ||
| 2154 | }; | ||
| 2155 | |||
| 2156 | static u32 __init armv7_reset_read_pmnc(void) | ||
| 2157 | { | ||
| 2158 | u32 nb_cnt; | ||
| 2159 | |||
| 2160 | /* Initialize & Reset PMNC: C and P bits */ | ||
| 2161 | armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C); | ||
| 2162 | |||
| 2163 | /* Read the nb of CNTx counters supported from PMNC */ | ||
| 2164 | nb_cnt = (armv7_pmnc_read() >> ARMV7_PMNC_N_SHIFT) & ARMV7_PMNC_N_MASK; | ||
| 2165 | |||
| 2166 | /* Add the CPU cycles counter and return */ | ||
| 2167 | return nb_cnt + 1; | ||
| 2168 | } | ||
| 2169 | |||
| 2170 | /* | ||
| 2171 | * ARMv5 [xscale] Performance counter handling code. | ||
| 2172 | * | ||
| 2173 | * Based on xscale OProfile code. | ||
| 2174 | * | ||
| 2175 | * There are two variants of the xscale PMU that we support: | ||
| 2176 | * - xscale1pmu: 2 event counters and a cycle counter | ||
| 2177 | * - xscale2pmu: 4 event counters and a cycle counter | ||
| 2178 | * The two variants share event definitions, but have different | ||
| 2179 | * PMU structures. | ||
| 2180 | */ | ||
| 2181 | |||
| 2182 | enum xscale_perf_types { | ||
| 2183 | XSCALE_PERFCTR_ICACHE_MISS = 0x00, | ||
| 2184 | XSCALE_PERFCTR_ICACHE_NO_DELIVER = 0x01, | ||
| 2185 | XSCALE_PERFCTR_DATA_STALL = 0x02, | ||
| 2186 | XSCALE_PERFCTR_ITLB_MISS = 0x03, | ||
| 2187 | XSCALE_PERFCTR_DTLB_MISS = 0x04, | ||
| 2188 | XSCALE_PERFCTR_BRANCH = 0x05, | ||
| 2189 | XSCALE_PERFCTR_BRANCH_MISS = 0x06, | ||
| 2190 | XSCALE_PERFCTR_INSTRUCTION = 0x07, | ||
| 2191 | XSCALE_PERFCTR_DCACHE_FULL_STALL = 0x08, | ||
| 2192 | XSCALE_PERFCTR_DCACHE_FULL_STALL_CONTIG = 0x09, | ||
| 2193 | XSCALE_PERFCTR_DCACHE_ACCESS = 0x0A, | ||
| 2194 | XSCALE_PERFCTR_DCACHE_MISS = 0x0B, | ||
| 2195 | XSCALE_PERFCTR_DCACHE_WRITE_BACK = 0x0C, | ||
| 2196 | XSCALE_PERFCTR_PC_CHANGED = 0x0D, | ||
| 2197 | XSCALE_PERFCTR_BCU_REQUEST = 0x10, | ||
| 2198 | XSCALE_PERFCTR_BCU_FULL = 0x11, | ||
| 2199 | XSCALE_PERFCTR_BCU_DRAIN = 0x12, | ||
| 2200 | XSCALE_PERFCTR_BCU_ECC_NO_ELOG = 0x14, | ||
| 2201 | XSCALE_PERFCTR_BCU_1_BIT_ERR = 0x15, | ||
| 2202 | XSCALE_PERFCTR_RMW = 0x16, | ||
| 2203 | /* XSCALE_PERFCTR_CCNT is not hardware defined */ | ||
| 2204 | XSCALE_PERFCTR_CCNT = 0xFE, | ||
| 2205 | XSCALE_PERFCTR_UNUSED = 0xFF, | ||
| 2206 | }; | ||
| 2207 | |||
| 2208 | enum xscale_counters { | ||
| 2209 | XSCALE_CYCLE_COUNTER = 1, | ||
| 2210 | XSCALE_COUNTER0, | ||
| 2211 | XSCALE_COUNTER1, | ||
| 2212 | XSCALE_COUNTER2, | ||
| 2213 | XSCALE_COUNTER3, | ||
| 2214 | }; | ||
| 2215 | |||
| 2216 | static const unsigned xscale_perf_map[PERF_COUNT_HW_MAX] = { | ||
| 2217 | [PERF_COUNT_HW_CPU_CYCLES] = XSCALE_PERFCTR_CCNT, | ||
| 2218 | [PERF_COUNT_HW_INSTRUCTIONS] = XSCALE_PERFCTR_INSTRUCTION, | ||
| 2219 | [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, | ||
| 2220 | [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, | ||
| 2221 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XSCALE_PERFCTR_BRANCH, | ||
| 2222 | [PERF_COUNT_HW_BRANCH_MISSES] = XSCALE_PERFCTR_BRANCH_MISS, | ||
| 2223 | [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED, | ||
| 2224 | }; | ||
| 2225 | |||
| 2226 | static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | ||
| 2227 | [PERF_COUNT_HW_CACHE_OP_MAX] | ||
| 2228 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { | ||
| 2229 | [C(L1D)] = { | ||
| 2230 | [C(OP_READ)] = { | ||
| 2231 | [C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS, | ||
| 2232 | [C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS, | ||
| 2233 | }, | ||
| 2234 | [C(OP_WRITE)] = { | ||
| 2235 | [C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS, | ||
| 2236 | [C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS, | ||
| 2237 | }, | ||
| 2238 | [C(OP_PREFETCH)] = { | ||
| 2239 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 2240 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 2241 | }, | ||
| 2242 | }, | ||
| 2243 | [C(L1I)] = { | ||
| 2244 | [C(OP_READ)] = { | ||
| 2245 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 2246 | [C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS, | ||
| 2247 | }, | ||
| 2248 | [C(OP_WRITE)] = { | ||
| 2249 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 2250 | [C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS, | ||
| 2251 | }, | ||
| 2252 | [C(OP_PREFETCH)] = { | ||
| 2253 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 2254 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 2255 | }, | ||
| 2256 | }, | ||
| 2257 | [C(LL)] = { | ||
| 2258 | [C(OP_READ)] = { | ||
| 2259 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 2260 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 2261 | }, | ||
| 2262 | [C(OP_WRITE)] = { | ||
| 2263 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 2264 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 2265 | }, | ||
| 2266 | [C(OP_PREFETCH)] = { | ||
| 2267 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 2268 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 2269 | }, | ||
| 2270 | }, | ||
| 2271 | [C(DTLB)] = { | ||
| 2272 | [C(OP_READ)] = { | ||
| 2273 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 2274 | [C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS, | ||
| 2275 | }, | ||
| 2276 | [C(OP_WRITE)] = { | ||
| 2277 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 2278 | [C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS, | ||
| 2279 | }, | ||
| 2280 | [C(OP_PREFETCH)] = { | ||
| 2281 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 2282 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 2283 | }, | ||
| 2284 | }, | ||
| 2285 | [C(ITLB)] = { | ||
| 2286 | [C(OP_READ)] = { | ||
| 2287 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 2288 | [C(RESULT_MISS)] = XSCALE_PERFCTR_ITLB_MISS, | ||
| 2289 | }, | ||
| 2290 | [C(OP_WRITE)] = { | ||
| 2291 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 2292 | [C(RESULT_MISS)] = XSCALE_PERFCTR_ITLB_MISS, | ||
| 2293 | }, | ||
| 2294 | [C(OP_PREFETCH)] = { | ||
| 2295 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 2296 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 2297 | }, | ||
| 2298 | }, | ||
| 2299 | [C(BPU)] = { | ||
| 2300 | [C(OP_READ)] = { | ||
| 2301 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 2302 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 2303 | }, | ||
| 2304 | [C(OP_WRITE)] = { | ||
| 2305 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 2306 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 2307 | }, | ||
| 2308 | [C(OP_PREFETCH)] = { | ||
| 2309 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 2310 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 2311 | }, | ||
| 2312 | }, | ||
| 2313 | }; | ||
| 2314 | |||
| 2315 | #define XSCALE_PMU_ENABLE 0x001 | ||
| 2316 | #define XSCALE_PMN_RESET 0x002 | ||
| 2317 | #define XSCALE_CCNT_RESET 0x004 | ||
| 2318 | #define XSCALE_PMU_RESET (CCNT_RESET | PMN_RESET) | ||
| 2319 | #define XSCALE_PMU_CNT64 0x008 | ||
| 2320 | |||
| 2321 | static inline int | ||
| 2322 | xscalepmu_event_map(int config) | ||
| 2323 | { | ||
| 2324 | int mapping = xscale_perf_map[config]; | ||
| 2325 | if (HW_OP_UNSUPPORTED == mapping) | ||
| 2326 | mapping = -EOPNOTSUPP; | ||
| 2327 | return mapping; | ||
| 2328 | } | ||
| 2329 | |||
| 2330 | static u64 | ||
| 2331 | xscalepmu_raw_event(u64 config) | ||
| 2332 | { | ||
| 2333 | return config & 0xff; | ||
| 2334 | } | ||
| 2335 | |||
| 2336 | #define XSCALE1_OVERFLOWED_MASK 0x700 | ||
| 2337 | #define XSCALE1_CCOUNT_OVERFLOW 0x400 | ||
| 2338 | #define XSCALE1_COUNT0_OVERFLOW 0x100 | ||
| 2339 | #define XSCALE1_COUNT1_OVERFLOW 0x200 | ||
| 2340 | #define XSCALE1_CCOUNT_INT_EN 0x040 | ||
| 2341 | #define XSCALE1_COUNT0_INT_EN 0x010 | ||
| 2342 | #define XSCALE1_COUNT1_INT_EN 0x020 | ||
| 2343 | #define XSCALE1_COUNT0_EVT_SHFT 12 | ||
| 2344 | #define XSCALE1_COUNT0_EVT_MASK (0xff << XSCALE1_COUNT0_EVT_SHFT) | ||
| 2345 | #define XSCALE1_COUNT1_EVT_SHFT 20 | ||
| 2346 | #define XSCALE1_COUNT1_EVT_MASK (0xff << XSCALE1_COUNT1_EVT_SHFT) | ||
| 2347 | |||
| 2348 | static inline u32 | ||
| 2349 | xscale1pmu_read_pmnc(void) | ||
| 2350 | { | ||
| 2351 | u32 val; | ||
| 2352 | asm volatile("mrc p14, 0, %0, c0, c0, 0" : "=r" (val)); | ||
| 2353 | return val; | ||
| 2354 | } | ||
| 2355 | |||
| 2356 | static inline void | ||
| 2357 | xscale1pmu_write_pmnc(u32 val) | ||
| 2358 | { | ||
| 2359 | /* upper 4bits and 7, 11 are write-as-0 */ | ||
| 2360 | val &= 0xffff77f; | ||
| 2361 | asm volatile("mcr p14, 0, %0, c0, c0, 0" : : "r" (val)); | ||
| 2362 | } | ||
| 2363 | |||
| 2364 | static inline int | ||
| 2365 | xscale1_pmnc_counter_has_overflowed(unsigned long pmnc, | ||
| 2366 | enum xscale_counters counter) | ||
| 2367 | { | ||
| 2368 | int ret = 0; | ||
| 2369 | |||
| 2370 | switch (counter) { | ||
| 2371 | case XSCALE_CYCLE_COUNTER: | ||
| 2372 | ret = pmnc & XSCALE1_CCOUNT_OVERFLOW; | ||
| 2373 | break; | ||
| 2374 | case XSCALE_COUNTER0: | ||
| 2375 | ret = pmnc & XSCALE1_COUNT0_OVERFLOW; | ||
| 2376 | break; | ||
| 2377 | case XSCALE_COUNTER1: | ||
| 2378 | ret = pmnc & XSCALE1_COUNT1_OVERFLOW; | ||
| 2379 | break; | ||
| 2380 | default: | ||
| 2381 | WARN_ONCE(1, "invalid counter number (%d)\n", counter); | ||
| 2382 | } | ||
| 2383 | |||
| 2384 | return ret; | ||
| 2385 | } | ||
| 2386 | |||
| 2387 | static irqreturn_t | ||
| 2388 | xscale1pmu_handle_irq(int irq_num, void *dev) | ||
| 2389 | { | ||
| 2390 | unsigned long pmnc; | ||
| 2391 | struct perf_sample_data data; | ||
| 2392 | struct cpu_hw_events *cpuc; | ||
| 2393 | struct pt_regs *regs; | ||
| 2394 | int idx; | ||
| 2395 | |||
| 2396 | /* | ||
| 2397 | * NOTE: there's an A stepping erratum that states if an overflow | ||
| 2398 | * bit already exists and another occurs, the previous | ||
| 2399 | * Overflow bit gets cleared. There's no workaround. | ||
| 2400 | * Fixed in B stepping or later. | ||
| 2401 | */ | ||
| 2402 | pmnc = xscale1pmu_read_pmnc(); | ||
| 2403 | |||
| 2404 | /* | ||
| 2405 | * Write the value back to clear the overflow flags. Overflow | ||
| 2406 | * flags remain in pmnc for use below. We also disable the PMU | ||
| 2407 | * while we process the interrupt. | ||
| 2408 | */ | ||
| 2409 | xscale1pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE); | ||
| 2410 | |||
| 2411 | if (!(pmnc & XSCALE1_OVERFLOWED_MASK)) | ||
| 2412 | return IRQ_NONE; | ||
| 2413 | |||
| 2414 | regs = get_irq_regs(); | ||
| 2415 | |||
| 2416 | perf_sample_data_init(&data, 0); | ||
| 2417 | |||
| 2418 | cpuc = &__get_cpu_var(cpu_hw_events); | ||
| 2419 | for (idx = 0; idx <= armpmu->num_events; ++idx) { | ||
| 2420 | struct perf_event *event = cpuc->events[idx]; | ||
| 2421 | struct hw_perf_event *hwc; | ||
| 2422 | |||
| 2423 | if (!test_bit(idx, cpuc->active_mask)) | ||
| 2424 | continue; | ||
| 2425 | |||
| 2426 | if (!xscale1_pmnc_counter_has_overflowed(pmnc, idx)) | ||
| 2427 | continue; | ||
| 2428 | |||
| 2429 | hwc = &event->hw; | ||
| 2430 | armpmu_event_update(event, hwc, idx); | ||
| 2431 | data.period = event->hw.last_period; | ||
| 2432 | if (!armpmu_event_set_period(event, hwc, idx)) | ||
| 2433 | continue; | ||
| 2434 | |||
| 2435 | if (perf_event_overflow(event, 0, &data, regs)) | ||
| 2436 | armpmu->disable(hwc, idx); | ||
| 2437 | } | ||
| 2438 | |||
| 2439 | irq_work_run(); | ||
| 2440 | |||
| 2441 | /* | ||
| 2442 | * Re-enable the PMU. | ||
| 2443 | */ | ||
| 2444 | pmnc = xscale1pmu_read_pmnc() | XSCALE_PMU_ENABLE; | ||
| 2445 | xscale1pmu_write_pmnc(pmnc); | ||
| 2446 | |||
| 2447 | return IRQ_HANDLED; | ||
| 2448 | } | ||
| 2449 | |||
| 2450 | static void | ||
| 2451 | xscale1pmu_enable_event(struct hw_perf_event *hwc, int idx) | ||
| 2452 | { | ||
| 2453 | unsigned long val, mask, evt, flags; | ||
| 2454 | |||
| 2455 | switch (idx) { | ||
| 2456 | case XSCALE_CYCLE_COUNTER: | ||
| 2457 | mask = 0; | ||
| 2458 | evt = XSCALE1_CCOUNT_INT_EN; | ||
| 2459 | break; | ||
| 2460 | case XSCALE_COUNTER0: | ||
| 2461 | mask = XSCALE1_COUNT0_EVT_MASK; | ||
| 2462 | evt = (hwc->config_base << XSCALE1_COUNT0_EVT_SHFT) | | ||
| 2463 | XSCALE1_COUNT0_INT_EN; | ||
| 2464 | break; | ||
| 2465 | case XSCALE_COUNTER1: | ||
| 2466 | mask = XSCALE1_COUNT1_EVT_MASK; | ||
| 2467 | evt = (hwc->config_base << XSCALE1_COUNT1_EVT_SHFT) | | ||
| 2468 | XSCALE1_COUNT1_INT_EN; | ||
| 2469 | break; | ||
| 2470 | default: | ||
| 2471 | WARN_ONCE(1, "invalid counter number (%d)\n", idx); | ||
| 2472 | return; | ||
| 2473 | } | ||
| 2474 | |||
| 2475 | spin_lock_irqsave(&pmu_lock, flags); | ||
| 2476 | val = xscale1pmu_read_pmnc(); | ||
| 2477 | val &= ~mask; | ||
| 2478 | val |= evt; | ||
| 2479 | xscale1pmu_write_pmnc(val); | ||
| 2480 | spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 2481 | } | ||
| 2482 | |||
| 2483 | static void | ||
| 2484 | xscale1pmu_disable_event(struct hw_perf_event *hwc, int idx) | ||
| 2485 | { | ||
| 2486 | unsigned long val, mask, evt, flags; | ||
| 2487 | |||
| 2488 | switch (idx) { | ||
| 2489 | case XSCALE_CYCLE_COUNTER: | ||
| 2490 | mask = XSCALE1_CCOUNT_INT_EN; | ||
| 2491 | evt = 0; | ||
| 2492 | break; | ||
| 2493 | case XSCALE_COUNTER0: | ||
| 2494 | mask = XSCALE1_COUNT0_INT_EN | XSCALE1_COUNT0_EVT_MASK; | ||
| 2495 | evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT0_EVT_SHFT; | ||
| 2496 | break; | ||
| 2497 | case XSCALE_COUNTER1: | ||
| 2498 | mask = XSCALE1_COUNT1_INT_EN | XSCALE1_COUNT1_EVT_MASK; | ||
| 2499 | evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT1_EVT_SHFT; | ||
| 2500 | break; | ||
| 2501 | default: | ||
| 2502 | WARN_ONCE(1, "invalid counter number (%d)\n", idx); | ||
| 2503 | return; | ||
| 2504 | } | ||
| 2505 | |||
| 2506 | spin_lock_irqsave(&pmu_lock, flags); | ||
| 2507 | val = xscale1pmu_read_pmnc(); | ||
| 2508 | val &= ~mask; | ||
| 2509 | val |= evt; | ||
| 2510 | xscale1pmu_write_pmnc(val); | ||
| 2511 | spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 2512 | } | ||
| 2513 | |||
| 2514 | static int | ||
| 2515 | xscale1pmu_get_event_idx(struct cpu_hw_events *cpuc, | ||
| 2516 | struct hw_perf_event *event) | ||
| 2517 | { | ||
| 2518 | if (XSCALE_PERFCTR_CCNT == event->config_base) { | ||
| 2519 | if (test_and_set_bit(XSCALE_CYCLE_COUNTER, cpuc->used_mask)) | ||
| 2520 | return -EAGAIN; | ||
| 2521 | |||
| 2522 | return XSCALE_CYCLE_COUNTER; | ||
| 2523 | } else { | ||
| 2524 | if (!test_and_set_bit(XSCALE_COUNTER1, cpuc->used_mask)) { | ||
| 2525 | return XSCALE_COUNTER1; | ||
| 2526 | } | ||
| 2527 | |||
| 2528 | if (!test_and_set_bit(XSCALE_COUNTER0, cpuc->used_mask)) { | ||
| 2529 | return XSCALE_COUNTER0; | ||
| 2530 | } | ||
| 2531 | |||
| 2532 | return -EAGAIN; | ||
| 2533 | } | ||
| 2534 | } | ||
| 2535 | |||
| 2536 | static void | ||
| 2537 | xscale1pmu_start(void) | ||
| 2538 | { | ||
| 2539 | unsigned long flags, val; | ||
| 2540 | |||
| 2541 | spin_lock_irqsave(&pmu_lock, flags); | ||
| 2542 | val = xscale1pmu_read_pmnc(); | ||
| 2543 | val |= XSCALE_PMU_ENABLE; | ||
| 2544 | xscale1pmu_write_pmnc(val); | ||
| 2545 | spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 2546 | } | ||
| 2547 | |||
| 2548 | static void | ||
| 2549 | xscale1pmu_stop(void) | ||
| 2550 | { | ||
| 2551 | unsigned long flags, val; | ||
| 2552 | |||
| 2553 | spin_lock_irqsave(&pmu_lock, flags); | ||
| 2554 | val = xscale1pmu_read_pmnc(); | ||
| 2555 | val &= ~XSCALE_PMU_ENABLE; | ||
| 2556 | xscale1pmu_write_pmnc(val); | ||
| 2557 | spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 2558 | } | ||
| 2559 | |||
| 2560 | static inline u32 | ||
| 2561 | xscale1pmu_read_counter(int counter) | ||
| 2562 | { | ||
| 2563 | u32 val = 0; | ||
| 2564 | |||
| 2565 | switch (counter) { | ||
| 2566 | case XSCALE_CYCLE_COUNTER: | ||
| 2567 | asm volatile("mrc p14, 0, %0, c1, c0, 0" : "=r" (val)); | ||
| 2568 | break; | ||
| 2569 | case XSCALE_COUNTER0: | ||
| 2570 | asm volatile("mrc p14, 0, %0, c2, c0, 0" : "=r" (val)); | ||
| 2571 | break; | ||
| 2572 | case XSCALE_COUNTER1: | ||
| 2573 | asm volatile("mrc p14, 0, %0, c3, c0, 0" : "=r" (val)); | ||
| 2574 | break; | ||
| 2575 | } | ||
| 2576 | |||
| 2577 | return val; | ||
| 2578 | } | ||
| 2579 | |||
| 2580 | static inline void | ||
| 2581 | xscale1pmu_write_counter(int counter, u32 val) | ||
| 2582 | { | ||
| 2583 | switch (counter) { | ||
| 2584 | case XSCALE_CYCLE_COUNTER: | ||
| 2585 | asm volatile("mcr p14, 0, %0, c1, c0, 0" : : "r" (val)); | ||
| 2586 | break; | ||
| 2587 | case XSCALE_COUNTER0: | ||
| 2588 | asm volatile("mcr p14, 0, %0, c2, c0, 0" : : "r" (val)); | ||
| 2589 | break; | ||
| 2590 | case XSCALE_COUNTER1: | ||
| 2591 | asm volatile("mcr p14, 0, %0, c3, c0, 0" : : "r" (val)); | ||
| 2592 | break; | ||
| 2593 | } | ||
| 2594 | } | ||
| 2595 | |||
| 2596 | static const struct arm_pmu xscale1pmu = { | ||
| 2597 | .id = ARM_PERF_PMU_ID_XSCALE1, | ||
| 2598 | .handle_irq = xscale1pmu_handle_irq, | ||
| 2599 | .enable = xscale1pmu_enable_event, | ||
| 2600 | .disable = xscale1pmu_disable_event, | ||
| 2601 | .event_map = xscalepmu_event_map, | ||
| 2602 | .raw_event = xscalepmu_raw_event, | ||
| 2603 | .read_counter = xscale1pmu_read_counter, | ||
| 2604 | .write_counter = xscale1pmu_write_counter, | ||
| 2605 | .get_event_idx = xscale1pmu_get_event_idx, | ||
| 2606 | .start = xscale1pmu_start, | ||
| 2607 | .stop = xscale1pmu_stop, | ||
| 2608 | .num_events = 3, | ||
| 2609 | .max_period = (1LLU << 32) - 1, | ||
| 2610 | }; | ||
| 2611 | |||
| 2612 | #define XSCALE2_OVERFLOWED_MASK 0x01f | ||
| 2613 | #define XSCALE2_CCOUNT_OVERFLOW 0x001 | ||
| 2614 | #define XSCALE2_COUNT0_OVERFLOW 0x002 | ||
| 2615 | #define XSCALE2_COUNT1_OVERFLOW 0x004 | ||
| 2616 | #define XSCALE2_COUNT2_OVERFLOW 0x008 | ||
| 2617 | #define XSCALE2_COUNT3_OVERFLOW 0x010 | ||
| 2618 | #define XSCALE2_CCOUNT_INT_EN 0x001 | ||
| 2619 | #define XSCALE2_COUNT0_INT_EN 0x002 | ||
| 2620 | #define XSCALE2_COUNT1_INT_EN 0x004 | ||
| 2621 | #define XSCALE2_COUNT2_INT_EN 0x008 | ||
| 2622 | #define XSCALE2_COUNT3_INT_EN 0x010 | ||
| 2623 | #define XSCALE2_COUNT0_EVT_SHFT 0 | ||
| 2624 | #define XSCALE2_COUNT0_EVT_MASK (0xff << XSCALE2_COUNT0_EVT_SHFT) | ||
| 2625 | #define XSCALE2_COUNT1_EVT_SHFT 8 | ||
| 2626 | #define XSCALE2_COUNT1_EVT_MASK (0xff << XSCALE2_COUNT1_EVT_SHFT) | ||
| 2627 | #define XSCALE2_COUNT2_EVT_SHFT 16 | ||
| 2628 | #define XSCALE2_COUNT2_EVT_MASK (0xff << XSCALE2_COUNT2_EVT_SHFT) | ||
| 2629 | #define XSCALE2_COUNT3_EVT_SHFT 24 | ||
| 2630 | #define XSCALE2_COUNT3_EVT_MASK (0xff << XSCALE2_COUNT3_EVT_SHFT) | ||
| 2631 | |||
| 2632 | static inline u32 | ||
| 2633 | xscale2pmu_read_pmnc(void) | ||
| 2634 | { | ||
| 2635 | u32 val; | ||
| 2636 | asm volatile("mrc p14, 0, %0, c0, c1, 0" : "=r" (val)); | ||
| 2637 | /* bits 1-2 and 4-23 are read-unpredictable */ | ||
| 2638 | return val & 0xff000009; | ||
| 2639 | } | ||
| 2640 | |||
| 2641 | static inline void | ||
| 2642 | xscale2pmu_write_pmnc(u32 val) | ||
| 2643 | { | ||
| 2644 | /* bits 4-23 are write-as-0, 24-31 are write ignored */ | ||
| 2645 | val &= 0xf; | ||
| 2646 | asm volatile("mcr p14, 0, %0, c0, c1, 0" : : "r" (val)); | ||
| 2647 | } | ||
| 2648 | |||
| 2649 | static inline u32 | ||
| 2650 | xscale2pmu_read_overflow_flags(void) | ||
| 2651 | { | ||
| 2652 | u32 val; | ||
| 2653 | asm volatile("mrc p14, 0, %0, c5, c1, 0" : "=r" (val)); | ||
| 2654 | return val; | ||
| 2655 | } | ||
| 2656 | |||
| 2657 | static inline void | ||
| 2658 | xscale2pmu_write_overflow_flags(u32 val) | ||
| 2659 | { | ||
| 2660 | asm volatile("mcr p14, 0, %0, c5, c1, 0" : : "r" (val)); | ||
| 2661 | } | ||
| 2662 | |||
| 2663 | static inline u32 | ||
| 2664 | xscale2pmu_read_event_select(void) | ||
| 2665 | { | ||
| 2666 | u32 val; | ||
| 2667 | asm volatile("mrc p14, 0, %0, c8, c1, 0" : "=r" (val)); | ||
| 2668 | return val; | ||
| 2669 | } | ||
| 2670 | |||
| 2671 | static inline void | ||
| 2672 | xscale2pmu_write_event_select(u32 val) | ||
| 2673 | { | ||
| 2674 | asm volatile("mcr p14, 0, %0, c8, c1, 0" : : "r"(val)); | ||
| 2675 | } | ||
| 2676 | |||
| 2677 | static inline u32 | ||
| 2678 | xscale2pmu_read_int_enable(void) | ||
| 2679 | { | ||
| 2680 | u32 val; | ||
| 2681 | asm volatile("mrc p14, 0, %0, c4, c1, 0" : "=r" (val)); | ||
| 2682 | return val; | ||
| 2683 | } | ||
| 2684 | |||
| 2685 | static void | ||
| 2686 | xscale2pmu_write_int_enable(u32 val) | ||
| 2687 | { | ||
| 2688 | asm volatile("mcr p14, 0, %0, c4, c1, 0" : : "r" (val)); | ||
| 2689 | } | ||
| 2690 | |||
| 2691 | static inline int | ||
| 2692 | xscale2_pmnc_counter_has_overflowed(unsigned long of_flags, | ||
| 2693 | enum xscale_counters counter) | ||
| 2694 | { | ||
| 2695 | int ret = 0; | ||
| 2696 | |||
| 2697 | switch (counter) { | ||
| 2698 | case XSCALE_CYCLE_COUNTER: | ||
| 2699 | ret = of_flags & XSCALE2_CCOUNT_OVERFLOW; | ||
| 2700 | break; | ||
| 2701 | case XSCALE_COUNTER0: | ||
| 2702 | ret = of_flags & XSCALE2_COUNT0_OVERFLOW; | ||
| 2703 | break; | ||
| 2704 | case XSCALE_COUNTER1: | ||
| 2705 | ret = of_flags & XSCALE2_COUNT1_OVERFLOW; | ||
| 2706 | break; | ||
| 2707 | case XSCALE_COUNTER2: | ||
| 2708 | ret = of_flags & XSCALE2_COUNT2_OVERFLOW; | ||
| 2709 | break; | ||
| 2710 | case XSCALE_COUNTER3: | ||
| 2711 | ret = of_flags & XSCALE2_COUNT3_OVERFLOW; | ||
| 2712 | break; | ||
| 2713 | default: | ||
| 2714 | WARN_ONCE(1, "invalid counter number (%d)\n", counter); | ||
| 2715 | } | ||
| 2716 | |||
| 2717 | return ret; | ||
| 2718 | } | ||
| 2719 | |||
| 2720 | static irqreturn_t | ||
| 2721 | xscale2pmu_handle_irq(int irq_num, void *dev) | ||
| 2722 | { | ||
| 2723 | unsigned long pmnc, of_flags; | ||
| 2724 | struct perf_sample_data data; | ||
| 2725 | struct cpu_hw_events *cpuc; | ||
| 2726 | struct pt_regs *regs; | ||
| 2727 | int idx; | ||
| 2728 | |||
| 2729 | /* Disable the PMU. */ | ||
| 2730 | pmnc = xscale2pmu_read_pmnc(); | ||
| 2731 | xscale2pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE); | ||
| 2732 | |||
| 2733 | /* Check the overflow flag register. */ | ||
| 2734 | of_flags = xscale2pmu_read_overflow_flags(); | ||
| 2735 | if (!(of_flags & XSCALE2_OVERFLOWED_MASK)) | ||
| 2736 | return IRQ_NONE; | ||
| 2737 | |||
| 2738 | /* Clear the overflow bits. */ | ||
| 2739 | xscale2pmu_write_overflow_flags(of_flags); | ||
| 2740 | |||
| 2741 | regs = get_irq_regs(); | ||
| 2742 | |||
| 2743 | perf_sample_data_init(&data, 0); | ||
| 2744 | |||
| 2745 | cpuc = &__get_cpu_var(cpu_hw_events); | ||
| 2746 | for (idx = 0; idx <= armpmu->num_events; ++idx) { | ||
| 2747 | struct perf_event *event = cpuc->events[idx]; | ||
| 2748 | struct hw_perf_event *hwc; | ||
| 2749 | |||
| 2750 | if (!test_bit(idx, cpuc->active_mask)) | ||
| 2751 | continue; | ||
| 2752 | |||
| 2753 | if (!xscale2_pmnc_counter_has_overflowed(pmnc, idx)) | ||
| 2754 | continue; | ||
| 2755 | |||
| 2756 | hwc = &event->hw; | ||
| 2757 | armpmu_event_update(event, hwc, idx); | ||
| 2758 | data.period = event->hw.last_period; | ||
| 2759 | if (!armpmu_event_set_period(event, hwc, idx)) | ||
| 2760 | continue; | ||
| 2761 | |||
| 2762 | if (perf_event_overflow(event, 0, &data, regs)) | ||
| 2763 | armpmu->disable(hwc, idx); | ||
| 2764 | } | ||
| 2765 | |||
| 2766 | irq_work_run(); | ||
| 2767 | |||
| 2768 | /* | ||
| 2769 | * Re-enable the PMU. | ||
| 2770 | */ | ||
| 2771 | pmnc = xscale2pmu_read_pmnc() | XSCALE_PMU_ENABLE; | ||
| 2772 | xscale2pmu_write_pmnc(pmnc); | ||
| 2773 | |||
| 2774 | return IRQ_HANDLED; | ||
| 2775 | } | ||
| 2776 | |||
| 2777 | static void | ||
| 2778 | xscale2pmu_enable_event(struct hw_perf_event *hwc, int idx) | ||
| 2779 | { | ||
| 2780 | unsigned long flags, ien, evtsel; | ||
| 2781 | |||
| 2782 | ien = xscale2pmu_read_int_enable(); | ||
| 2783 | evtsel = xscale2pmu_read_event_select(); | ||
| 2784 | |||
| 2785 | switch (idx) { | ||
| 2786 | case XSCALE_CYCLE_COUNTER: | ||
| 2787 | ien |= XSCALE2_CCOUNT_INT_EN; | ||
| 2788 | break; | ||
| 2789 | case XSCALE_COUNTER0: | ||
| 2790 | ien |= XSCALE2_COUNT0_INT_EN; | ||
| 2791 | evtsel &= ~XSCALE2_COUNT0_EVT_MASK; | ||
| 2792 | evtsel |= hwc->config_base << XSCALE2_COUNT0_EVT_SHFT; | ||
| 2793 | break; | ||
| 2794 | case XSCALE_COUNTER1: | ||
| 2795 | ien |= XSCALE2_COUNT1_INT_EN; | ||
| 2796 | evtsel &= ~XSCALE2_COUNT1_EVT_MASK; | ||
| 2797 | evtsel |= hwc->config_base << XSCALE2_COUNT1_EVT_SHFT; | ||
| 2798 | break; | ||
| 2799 | case XSCALE_COUNTER2: | ||
| 2800 | ien |= XSCALE2_COUNT2_INT_EN; | ||
| 2801 | evtsel &= ~XSCALE2_COUNT2_EVT_MASK; | ||
| 2802 | evtsel |= hwc->config_base << XSCALE2_COUNT2_EVT_SHFT; | ||
| 2803 | break; | ||
| 2804 | case XSCALE_COUNTER3: | ||
| 2805 | ien |= XSCALE2_COUNT3_INT_EN; | ||
| 2806 | evtsel &= ~XSCALE2_COUNT3_EVT_MASK; | ||
| 2807 | evtsel |= hwc->config_base << XSCALE2_COUNT3_EVT_SHFT; | ||
| 2808 | break; | ||
| 2809 | default: | ||
| 2810 | WARN_ONCE(1, "invalid counter number (%d)\n", idx); | ||
| 2811 | return; | ||
| 2812 | } | ||
| 2813 | |||
| 2814 | spin_lock_irqsave(&pmu_lock, flags); | ||
| 2815 | xscale2pmu_write_event_select(evtsel); | ||
| 2816 | xscale2pmu_write_int_enable(ien); | ||
| 2817 | spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 2818 | } | ||
| 2819 | |||
| 2820 | static void | ||
| 2821 | xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx) | ||
| 2822 | { | ||
| 2823 | unsigned long flags, ien, evtsel; | ||
| 2824 | |||
| 2825 | ien = xscale2pmu_read_int_enable(); | ||
| 2826 | evtsel = xscale2pmu_read_event_select(); | ||
| 2827 | |||
| 2828 | switch (idx) { | ||
| 2829 | case XSCALE_CYCLE_COUNTER: | ||
| 2830 | ien &= ~XSCALE2_CCOUNT_INT_EN; | ||
| 2831 | break; | ||
| 2832 | case XSCALE_COUNTER0: | ||
| 2833 | ien &= ~XSCALE2_COUNT0_INT_EN; | ||
| 2834 | evtsel &= ~XSCALE2_COUNT0_EVT_MASK; | ||
| 2835 | evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT0_EVT_SHFT; | ||
| 2836 | break; | ||
| 2837 | case XSCALE_COUNTER1: | ||
| 2838 | ien &= ~XSCALE2_COUNT1_INT_EN; | ||
| 2839 | evtsel &= ~XSCALE2_COUNT1_EVT_MASK; | ||
| 2840 | evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT1_EVT_SHFT; | ||
| 2841 | break; | ||
| 2842 | case XSCALE_COUNTER2: | ||
| 2843 | ien &= ~XSCALE2_COUNT2_INT_EN; | ||
| 2844 | evtsel &= ~XSCALE2_COUNT2_EVT_MASK; | ||
| 2845 | evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT2_EVT_SHFT; | ||
| 2846 | break; | ||
| 2847 | case XSCALE_COUNTER3: | ||
| 2848 | ien &= ~XSCALE2_COUNT3_INT_EN; | ||
| 2849 | evtsel &= ~XSCALE2_COUNT3_EVT_MASK; | ||
| 2850 | evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT3_EVT_SHFT; | ||
| 2851 | break; | ||
| 2852 | default: | ||
| 2853 | WARN_ONCE(1, "invalid counter number (%d)\n", idx); | ||
| 2854 | return; | ||
| 2855 | } | ||
| 2856 | |||
| 2857 | spin_lock_irqsave(&pmu_lock, flags); | ||
| 2858 | xscale2pmu_write_event_select(evtsel); | ||
| 2859 | xscale2pmu_write_int_enable(ien); | ||
| 2860 | spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 2861 | } | ||
| 2862 | |||
| 2863 | static int | ||
| 2864 | xscale2pmu_get_event_idx(struct cpu_hw_events *cpuc, | ||
| 2865 | struct hw_perf_event *event) | ||
| 2866 | { | ||
| 2867 | int idx = xscale1pmu_get_event_idx(cpuc, event); | ||
| 2868 | if (idx >= 0) | ||
| 2869 | goto out; | ||
| 2870 | |||
| 2871 | if (!test_and_set_bit(XSCALE_COUNTER3, cpuc->used_mask)) | ||
| 2872 | idx = XSCALE_COUNTER3; | ||
| 2873 | else if (!test_and_set_bit(XSCALE_COUNTER2, cpuc->used_mask)) | ||
| 2874 | idx = XSCALE_COUNTER2; | ||
| 2875 | out: | ||
| 2876 | return idx; | ||
| 2877 | } | ||
| 2878 | |||
| 2879 | static void | ||
| 2880 | xscale2pmu_start(void) | ||
| 2881 | { | ||
| 2882 | unsigned long flags, val; | ||
| 2883 | |||
| 2884 | spin_lock_irqsave(&pmu_lock, flags); | ||
| 2885 | val = xscale2pmu_read_pmnc() & ~XSCALE_PMU_CNT64; | ||
| 2886 | val |= XSCALE_PMU_ENABLE; | ||
| 2887 | xscale2pmu_write_pmnc(val); | ||
| 2888 | spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 2889 | } | ||
| 2890 | |||
| 2891 | static void | ||
| 2892 | xscale2pmu_stop(void) | ||
| 2893 | { | ||
| 2894 | unsigned long flags, val; | ||
| 2895 | |||
| 2896 | spin_lock_irqsave(&pmu_lock, flags); | ||
| 2897 | val = xscale2pmu_read_pmnc(); | ||
| 2898 | val &= ~XSCALE_PMU_ENABLE; | ||
| 2899 | xscale2pmu_write_pmnc(val); | ||
| 2900 | spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 2901 | } | ||
| 2902 | |||
| 2903 | static inline u32 | ||
| 2904 | xscale2pmu_read_counter(int counter) | ||
| 2905 | { | ||
| 2906 | u32 val = 0; | ||
| 2907 | |||
| 2908 | switch (counter) { | ||
| 2909 | case XSCALE_CYCLE_COUNTER: | ||
| 2910 | asm volatile("mrc p14, 0, %0, c1, c1, 0" : "=r" (val)); | ||
| 2911 | break; | ||
| 2912 | case XSCALE_COUNTER0: | ||
| 2913 | asm volatile("mrc p14, 0, %0, c0, c2, 0" : "=r" (val)); | ||
| 2914 | break; | ||
| 2915 | case XSCALE_COUNTER1: | ||
| 2916 | asm volatile("mrc p14, 0, %0, c1, c2, 0" : "=r" (val)); | ||
| 2917 | break; | ||
| 2918 | case XSCALE_COUNTER2: | ||
| 2919 | asm volatile("mrc p14, 0, %0, c2, c2, 0" : "=r" (val)); | ||
| 2920 | break; | ||
| 2921 | case XSCALE_COUNTER3: | ||
| 2922 | asm volatile("mrc p14, 0, %0, c3, c2, 0" : "=r" (val)); | ||
| 2923 | break; | ||
| 2924 | } | ||
| 2925 | |||
| 2926 | return val; | ||
| 2927 | } | ||
| 2928 | |||
| 2929 | static inline void | ||
| 2930 | xscale2pmu_write_counter(int counter, u32 val) | ||
| 2931 | { | ||
| 2932 | switch (counter) { | ||
| 2933 | case XSCALE_CYCLE_COUNTER: | ||
| 2934 | asm volatile("mcr p14, 0, %0, c1, c1, 0" : : "r" (val)); | ||
| 2935 | break; | ||
| 2936 | case XSCALE_COUNTER0: | ||
| 2937 | asm volatile("mcr p14, 0, %0, c0, c2, 0" : : "r" (val)); | ||
| 2938 | break; | ||
| 2939 | case XSCALE_COUNTER1: | ||
| 2940 | asm volatile("mcr p14, 0, %0, c1, c2, 0" : : "r" (val)); | ||
| 2941 | break; | ||
| 2942 | case XSCALE_COUNTER2: | ||
| 2943 | asm volatile("mcr p14, 0, %0, c2, c2, 0" : : "r" (val)); | ||
| 2944 | break; | ||
| 2945 | case XSCALE_COUNTER3: | ||
| 2946 | asm volatile("mcr p14, 0, %0, c3, c2, 0" : : "r" (val)); | ||
| 2947 | break; | ||
| 2948 | } | ||
| 2949 | } | ||
| 2950 | |||
| 2951 | static const struct arm_pmu xscale2pmu = { | ||
| 2952 | .id = ARM_PERF_PMU_ID_XSCALE2, | ||
| 2953 | .handle_irq = xscale2pmu_handle_irq, | ||
| 2954 | .enable = xscale2pmu_enable_event, | ||
| 2955 | .disable = xscale2pmu_disable_event, | ||
| 2956 | .event_map = xscalepmu_event_map, | ||
| 2957 | .raw_event = xscalepmu_raw_event, | ||
| 2958 | .read_counter = xscale2pmu_read_counter, | ||
| 2959 | .write_counter = xscale2pmu_write_counter, | ||
| 2960 | .get_event_idx = xscale2pmu_get_event_idx, | ||
| 2961 | .start = xscale2pmu_start, | ||
| 2962 | .stop = xscale2pmu_stop, | ||
| 2963 | .num_events = 5, | ||
| 2964 | .max_period = (1LLU << 32) - 1, | ||
| 2965 | }; | ||
| 2966 | 611 | ||
| 2967 | static int __init | 612 | static int __init |
| 2968 | init_hw_perf_events(void) | 613 | init_hw_perf_events(void) |
| @@ -2977,37 +622,16 @@ init_hw_perf_events(void) | |||
| 2977 | case 0xB360: /* ARM1136 */ | 622 | case 0xB360: /* ARM1136 */ |
| 2978 | case 0xB560: /* ARM1156 */ | 623 | case 0xB560: /* ARM1156 */ |
| 2979 | case 0xB760: /* ARM1176 */ | 624 | case 0xB760: /* ARM1176 */ |
| 2980 | armpmu = &armv6pmu; | 625 | armpmu = armv6pmu_init(); |
| 2981 | memcpy(armpmu_perf_cache_map, armv6_perf_cache_map, | ||
| 2982 | sizeof(armv6_perf_cache_map)); | ||
| 2983 | break; | 626 | break; |
| 2984 | case 0xB020: /* ARM11mpcore */ | 627 | case 0xB020: /* ARM11mpcore */ |
| 2985 | armpmu = &armv6mpcore_pmu; | 628 | armpmu = armv6mpcore_pmu_init(); |
| 2986 | memcpy(armpmu_perf_cache_map, | ||
| 2987 | armv6mpcore_perf_cache_map, | ||
| 2988 | sizeof(armv6mpcore_perf_cache_map)); | ||
| 2989 | break; | 629 | break; |
| 2990 | case 0xC080: /* Cortex-A8 */ | 630 | case 0xC080: /* Cortex-A8 */ |
| 2991 | armv7pmu.id = ARM_PERF_PMU_ID_CA8; | 631 | armpmu = armv7_a8_pmu_init(); |
| 2992 | memcpy(armpmu_perf_cache_map, armv7_a8_perf_cache_map, | ||
| 2993 | sizeof(armv7_a8_perf_cache_map)); | ||
| 2994 | armv7pmu.event_map = armv7_a8_pmu_event_map; | ||
| 2995 | armpmu = &armv7pmu; | ||
| 2996 | |||
| 2997 | /* Reset PMNC and read the nb of CNTx counters | ||
| 2998 | supported */ | ||
| 2999 | armv7pmu.num_events = armv7_reset_read_pmnc(); | ||
| 3000 | break; | 632 | break; |
| 3001 | case 0xC090: /* Cortex-A9 */ | 633 | case 0xC090: /* Cortex-A9 */ |
| 3002 | armv7pmu.id = ARM_PERF_PMU_ID_CA9; | 634 | armpmu = armv7_a9_pmu_init(); |
| 3003 | memcpy(armpmu_perf_cache_map, armv7_a9_perf_cache_map, | ||
| 3004 | sizeof(armv7_a9_perf_cache_map)); | ||
| 3005 | armv7pmu.event_map = armv7_a9_pmu_event_map; | ||
| 3006 | armpmu = &armv7pmu; | ||
| 3007 | |||
| 3008 | /* Reset PMNC and read the nb of CNTx counters | ||
| 3009 | supported */ | ||
| 3010 | armv7pmu.num_events = armv7_reset_read_pmnc(); | ||
| 3011 | break; | 635 | break; |
| 3012 | } | 636 | } |
| 3013 | /* Intel CPUs [xscale]. */ | 637 | /* Intel CPUs [xscale]. */ |
| @@ -3015,30 +639,26 @@ init_hw_perf_events(void) | |||
| 3015 | part_number = (cpuid >> 13) & 0x7; | 639 | part_number = (cpuid >> 13) & 0x7; |
| 3016 | switch (part_number) { | 640 | switch (part_number) { |
| 3017 | case 1: | 641 | case 1: |
| 3018 | armpmu = &xscale1pmu; | 642 | armpmu = xscale1pmu_init(); |
| 3019 | memcpy(armpmu_perf_cache_map, xscale_perf_cache_map, | ||
| 3020 | sizeof(xscale_perf_cache_map)); | ||
| 3021 | break; | 643 | break; |
| 3022 | case 2: | 644 | case 2: |
| 3023 | armpmu = &xscale2pmu; | 645 | armpmu = xscale2pmu_init(); |
| 3024 | memcpy(armpmu_perf_cache_map, xscale_perf_cache_map, | ||
| 3025 | sizeof(xscale_perf_cache_map)); | ||
| 3026 | break; | 646 | break; |
| 3027 | } | 647 | } |
| 3028 | } | 648 | } |
| 3029 | 649 | ||
| 3030 | if (armpmu) { | 650 | if (armpmu) { |
| 3031 | pr_info("enabled with %s PMU driver, %d counters available\n", | 651 | pr_info("enabled with %s PMU driver, %d counters available\n", |
| 3032 | arm_pmu_names[armpmu->id], armpmu->num_events); | 652 | armpmu->name, armpmu->num_events); |
| 3033 | } else { | 653 | } else { |
| 3034 | pr_info("no hardware support available\n"); | 654 | pr_info("no hardware support available\n"); |
| 3035 | } | 655 | } |
| 3036 | 656 | ||
| 3037 | perf_pmu_register(&pmu); | 657 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
| 3038 | 658 | ||
| 3039 | return 0; | 659 | return 0; |
| 3040 | } | 660 | } |
| 3041 | arch_initcall(init_hw_perf_events); | 661 | early_initcall(init_hw_perf_events); |
| 3042 | 662 | ||
| 3043 | /* | 663 | /* |
| 3044 | * Callchain handling code. | 664 | * Callchain handling code. |
| @@ -3053,17 +673,17 @@ arch_initcall(init_hw_perf_events); | |||
| 3053 | * This code has been adapted from the ARM OProfile support. | 673 | * This code has been adapted from the ARM OProfile support. |
| 3054 | */ | 674 | */ |
| 3055 | struct frame_tail { | 675 | struct frame_tail { |
| 3056 | struct frame_tail *fp; | 676 | struct frame_tail __user *fp; |
| 3057 | unsigned long sp; | 677 | unsigned long sp; |
| 3058 | unsigned long lr; | 678 | unsigned long lr; |
| 3059 | } __attribute__((packed)); | 679 | } __attribute__((packed)); |
| 3060 | 680 | ||
| 3061 | /* | 681 | /* |
| 3062 | * Get the return address for a single stackframe and return a pointer to the | 682 | * Get the return address for a single stackframe and return a pointer to the |
| 3063 | * next frame tail. | 683 | * next frame tail. |
| 3064 | */ | 684 | */ |
| 3065 | static struct frame_tail * | 685 | static struct frame_tail __user * |
| 3066 | user_backtrace(struct frame_tail *tail, | 686 | user_backtrace(struct frame_tail __user *tail, |
| 3067 | struct perf_callchain_entry *entry) | 687 | struct perf_callchain_entry *entry) |
| 3068 | { | 688 | { |
| 3069 | struct frame_tail buftail; | 689 | struct frame_tail buftail; |
| @@ -3089,10 +709,10 @@ user_backtrace(struct frame_tail *tail, | |||
| 3089 | void | 709 | void |
| 3090 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | 710 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) |
| 3091 | { | 711 | { |
| 3092 | struct frame_tail *tail; | 712 | struct frame_tail __user *tail; |
| 3093 | 713 | ||
| 3094 | 714 | ||
| 3095 | tail = (struct frame_tail *)regs->ARM_fp - 1; | 715 | tail = (struct frame_tail __user *)regs->ARM_fp - 1; |
| 3096 | 716 | ||
| 3097 | while (tail && !((unsigned long)tail & 0x3)) | 717 | while (tail && !((unsigned long)tail & 0x3)) |
| 3098 | tail = user_backtrace(tail, entry); | 718 | tail = user_backtrace(tail, entry); |
diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c new file mode 100644 index 000000000000..c058bfc8532b --- /dev/null +++ b/arch/arm/kernel/perf_event_v6.c | |||
| @@ -0,0 +1,672 @@ | |||
| 1 | /* | ||
| 2 | * ARMv6 Performance counter handling code. | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles | ||
| 5 | * | ||
| 6 | * ARMv6 has 2 configurable performance counters and a single cycle counter. | ||
| 7 | * They all share a single reset bit but can be written to zero so we can use | ||
| 8 | * that for a reset. | ||
| 9 | * | ||
| 10 | * The counters can't be individually enabled or disabled so when we remove | ||
| 11 | * one event and replace it with another we could get spurious counts from the | ||
| 12 | * wrong event. However, we can take advantage of the fact that the | ||
| 13 | * performance counters can export events to the event bus, and the event bus | ||
| 14 | * itself can be monitored. This requires that we *don't* export the events to | ||
| 15 | * the event bus. The procedure for disabling a configurable counter is: | ||
| 16 | * - change the counter to count the ETMEXTOUT[0] signal (0x20). This | ||
| 17 | * effectively stops the counter from counting. | ||
| 18 | * - disable the counter's interrupt generation (each counter has it's | ||
| 19 | * own interrupt enable bit). | ||
| 20 | * Once stopped, the counter value can be written as 0 to reset. | ||
| 21 | * | ||
| 22 | * To enable a counter: | ||
| 23 | * - enable the counter's interrupt generation. | ||
| 24 | * - set the new event type. | ||
| 25 | * | ||
| 26 | * Note: the dedicated cycle counter only counts cycles and can't be | ||
| 27 | * enabled/disabled independently of the others. When we want to disable the | ||
| 28 | * cycle counter, we have to just disable the interrupt reporting and start | ||
| 29 | * ignoring that counter. When re-enabling, we have to reset the value and | ||
| 30 | * enable the interrupt. | ||
| 31 | */ | ||
| 32 | |||
| 33 | #ifdef CONFIG_CPU_V6 | ||
| 34 | enum armv6_perf_types { | ||
| 35 | ARMV6_PERFCTR_ICACHE_MISS = 0x0, | ||
| 36 | ARMV6_PERFCTR_IBUF_STALL = 0x1, | ||
| 37 | ARMV6_PERFCTR_DDEP_STALL = 0x2, | ||
| 38 | ARMV6_PERFCTR_ITLB_MISS = 0x3, | ||
| 39 | ARMV6_PERFCTR_DTLB_MISS = 0x4, | ||
| 40 | ARMV6_PERFCTR_BR_EXEC = 0x5, | ||
| 41 | ARMV6_PERFCTR_BR_MISPREDICT = 0x6, | ||
| 42 | ARMV6_PERFCTR_INSTR_EXEC = 0x7, | ||
| 43 | ARMV6_PERFCTR_DCACHE_HIT = 0x9, | ||
| 44 | ARMV6_PERFCTR_DCACHE_ACCESS = 0xA, | ||
| 45 | ARMV6_PERFCTR_DCACHE_MISS = 0xB, | ||
| 46 | ARMV6_PERFCTR_DCACHE_WBACK = 0xC, | ||
| 47 | ARMV6_PERFCTR_SW_PC_CHANGE = 0xD, | ||
| 48 | ARMV6_PERFCTR_MAIN_TLB_MISS = 0xF, | ||
| 49 | ARMV6_PERFCTR_EXPL_D_ACCESS = 0x10, | ||
| 50 | ARMV6_PERFCTR_LSU_FULL_STALL = 0x11, | ||
| 51 | ARMV6_PERFCTR_WBUF_DRAINED = 0x12, | ||
| 52 | ARMV6_PERFCTR_CPU_CYCLES = 0xFF, | ||
| 53 | ARMV6_PERFCTR_NOP = 0x20, | ||
| 54 | }; | ||
| 55 | |||
| 56 | enum armv6_counters { | ||
| 57 | ARMV6_CYCLE_COUNTER = 1, | ||
| 58 | ARMV6_COUNTER0, | ||
| 59 | ARMV6_COUNTER1, | ||
| 60 | }; | ||
| 61 | |||
| 62 | /* | ||
| 63 | * The hardware events that we support. We do support cache operations but | ||
| 64 | * we have harvard caches and no way to combine instruction and data | ||
| 65 | * accesses/misses in hardware. | ||
| 66 | */ | ||
| 67 | static const unsigned armv6_perf_map[PERF_COUNT_HW_MAX] = { | ||
| 68 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV6_PERFCTR_CPU_CYCLES, | ||
| 69 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6_PERFCTR_INSTR_EXEC, | ||
| 70 | [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, | ||
| 71 | [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, | ||
| 72 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6_PERFCTR_BR_EXEC, | ||
| 73 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6_PERFCTR_BR_MISPREDICT, | ||
| 74 | [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED, | ||
| 75 | }; | ||
| 76 | |||
| 77 | static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | ||
| 78 | [PERF_COUNT_HW_CACHE_OP_MAX] | ||
| 79 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { | ||
| 80 | [C(L1D)] = { | ||
| 81 | /* | ||
| 82 | * The performance counters don't differentiate between read | ||
| 83 | * and write accesses/misses so this isn't strictly correct, | ||
| 84 | * but it's the best we can do. Writes and reads get | ||
| 85 | * combined. | ||
| 86 | */ | ||
| 87 | [C(OP_READ)] = { | ||
| 88 | [C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS, | ||
| 89 | [C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS, | ||
| 90 | }, | ||
| 91 | [C(OP_WRITE)] = { | ||
| 92 | [C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS, | ||
| 93 | [C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS, | ||
| 94 | }, | ||
| 95 | [C(OP_PREFETCH)] = { | ||
| 96 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 97 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 98 | }, | ||
| 99 | }, | ||
| 100 | [C(L1I)] = { | ||
| 101 | [C(OP_READ)] = { | ||
| 102 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 103 | [C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS, | ||
| 104 | }, | ||
| 105 | [C(OP_WRITE)] = { | ||
| 106 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 107 | [C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS, | ||
| 108 | }, | ||
| 109 | [C(OP_PREFETCH)] = { | ||
| 110 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 111 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 112 | }, | ||
| 113 | }, | ||
| 114 | [C(LL)] = { | ||
| 115 | [C(OP_READ)] = { | ||
| 116 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 117 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 118 | }, | ||
| 119 | [C(OP_WRITE)] = { | ||
| 120 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 121 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 122 | }, | ||
| 123 | [C(OP_PREFETCH)] = { | ||
| 124 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 125 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 126 | }, | ||
| 127 | }, | ||
| 128 | [C(DTLB)] = { | ||
| 129 | /* | ||
| 130 | * The ARM performance counters can count micro DTLB misses, | ||
| 131 | * micro ITLB misses and main TLB misses. There isn't an event | ||
| 132 | * for TLB misses, so use the micro misses here and if users | ||
| 133 | * want the main TLB misses they can use a raw counter. | ||
| 134 | */ | ||
| 135 | [C(OP_READ)] = { | ||
| 136 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 137 | [C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS, | ||
| 138 | }, | ||
| 139 | [C(OP_WRITE)] = { | ||
| 140 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 141 | [C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS, | ||
| 142 | }, | ||
| 143 | [C(OP_PREFETCH)] = { | ||
| 144 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 145 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 146 | }, | ||
| 147 | }, | ||
| 148 | [C(ITLB)] = { | ||
| 149 | [C(OP_READ)] = { | ||
| 150 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 151 | [C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS, | ||
| 152 | }, | ||
| 153 | [C(OP_WRITE)] = { | ||
| 154 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 155 | [C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS, | ||
| 156 | }, | ||
| 157 | [C(OP_PREFETCH)] = { | ||
| 158 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 159 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 160 | }, | ||
| 161 | }, | ||
| 162 | [C(BPU)] = { | ||
| 163 | [C(OP_READ)] = { | ||
| 164 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 165 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 166 | }, | ||
| 167 | [C(OP_WRITE)] = { | ||
| 168 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 169 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 170 | }, | ||
| 171 | [C(OP_PREFETCH)] = { | ||
| 172 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 173 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 174 | }, | ||
| 175 | }, | ||
| 176 | }; | ||
| 177 | |||
| 178 | enum armv6mpcore_perf_types { | ||
| 179 | ARMV6MPCORE_PERFCTR_ICACHE_MISS = 0x0, | ||
| 180 | ARMV6MPCORE_PERFCTR_IBUF_STALL = 0x1, | ||
| 181 | ARMV6MPCORE_PERFCTR_DDEP_STALL = 0x2, | ||
| 182 | ARMV6MPCORE_PERFCTR_ITLB_MISS = 0x3, | ||
| 183 | ARMV6MPCORE_PERFCTR_DTLB_MISS = 0x4, | ||
| 184 | ARMV6MPCORE_PERFCTR_BR_EXEC = 0x5, | ||
| 185 | ARMV6MPCORE_PERFCTR_BR_NOTPREDICT = 0x6, | ||
| 186 | ARMV6MPCORE_PERFCTR_BR_MISPREDICT = 0x7, | ||
| 187 | ARMV6MPCORE_PERFCTR_INSTR_EXEC = 0x8, | ||
| 188 | ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS = 0xA, | ||
| 189 | ARMV6MPCORE_PERFCTR_DCACHE_RDMISS = 0xB, | ||
| 190 | ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS = 0xC, | ||
| 191 | ARMV6MPCORE_PERFCTR_DCACHE_WRMISS = 0xD, | ||
| 192 | ARMV6MPCORE_PERFCTR_DCACHE_EVICTION = 0xE, | ||
| 193 | ARMV6MPCORE_PERFCTR_SW_PC_CHANGE = 0xF, | ||
| 194 | ARMV6MPCORE_PERFCTR_MAIN_TLB_MISS = 0x10, | ||
| 195 | ARMV6MPCORE_PERFCTR_EXPL_MEM_ACCESS = 0x11, | ||
| 196 | ARMV6MPCORE_PERFCTR_LSU_FULL_STALL = 0x12, | ||
| 197 | ARMV6MPCORE_PERFCTR_WBUF_DRAINED = 0x13, | ||
| 198 | ARMV6MPCORE_PERFCTR_CPU_CYCLES = 0xFF, | ||
| 199 | }; | ||
| 200 | |||
| 201 | /* | ||
| 202 | * The hardware events that we support. We do support cache operations but | ||
| 203 | * we have harvard caches and no way to combine instruction and data | ||
| 204 | * accesses/misses in hardware. | ||
| 205 | */ | ||
| 206 | static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = { | ||
| 207 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV6MPCORE_PERFCTR_CPU_CYCLES, | ||
| 208 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_INSTR_EXEC, | ||
| 209 | [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, | ||
| 210 | [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, | ||
| 211 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC, | ||
| 212 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6MPCORE_PERFCTR_BR_MISPREDICT, | ||
| 213 | [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED, | ||
| 214 | }; | ||
| 215 | |||
| 216 | static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | ||
| 217 | [PERF_COUNT_HW_CACHE_OP_MAX] | ||
| 218 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { | ||
| 219 | [C(L1D)] = { | ||
| 220 | [C(OP_READ)] = { | ||
| 221 | [C(RESULT_ACCESS)] = | ||
| 222 | ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS, | ||
| 223 | [C(RESULT_MISS)] = | ||
| 224 | ARMV6MPCORE_PERFCTR_DCACHE_RDMISS, | ||
| 225 | }, | ||
| 226 | [C(OP_WRITE)] = { | ||
| 227 | [C(RESULT_ACCESS)] = | ||
| 228 | ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS, | ||
| 229 | [C(RESULT_MISS)] = | ||
| 230 | ARMV6MPCORE_PERFCTR_DCACHE_WRMISS, | ||
| 231 | }, | ||
| 232 | [C(OP_PREFETCH)] = { | ||
| 233 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 234 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 235 | }, | ||
| 236 | }, | ||
| 237 | [C(L1I)] = { | ||
| 238 | [C(OP_READ)] = { | ||
| 239 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 240 | [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS, | ||
| 241 | }, | ||
| 242 | [C(OP_WRITE)] = { | ||
| 243 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 244 | [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS, | ||
| 245 | }, | ||
| 246 | [C(OP_PREFETCH)] = { | ||
| 247 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 248 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 249 | }, | ||
| 250 | }, | ||
| 251 | [C(LL)] = { | ||
| 252 | [C(OP_READ)] = { | ||
| 253 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 254 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 255 | }, | ||
| 256 | [C(OP_WRITE)] = { | ||
| 257 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 258 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 259 | }, | ||
| 260 | [C(OP_PREFETCH)] = { | ||
| 261 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 262 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 263 | }, | ||
| 264 | }, | ||
| 265 | [C(DTLB)] = { | ||
| 266 | /* | ||
| 267 | * The ARM performance counters can count micro DTLB misses, | ||
| 268 | * micro ITLB misses and main TLB misses. There isn't an event | ||
| 269 | * for TLB misses, so use the micro misses here and if users | ||
| 270 | * want the main TLB misses they can use a raw counter. | ||
| 271 | */ | ||
| 272 | [C(OP_READ)] = { | ||
| 273 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 274 | [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS, | ||
| 275 | }, | ||
| 276 | [C(OP_WRITE)] = { | ||
| 277 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 278 | [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS, | ||
| 279 | }, | ||
| 280 | [C(OP_PREFETCH)] = { | ||
| 281 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 282 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 283 | }, | ||
| 284 | }, | ||
| 285 | [C(ITLB)] = { | ||
| 286 | [C(OP_READ)] = { | ||
| 287 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 288 | [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS, | ||
| 289 | }, | ||
| 290 | [C(OP_WRITE)] = { | ||
| 291 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 292 | [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS, | ||
| 293 | }, | ||
| 294 | [C(OP_PREFETCH)] = { | ||
| 295 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 296 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 297 | }, | ||
| 298 | }, | ||
| 299 | [C(BPU)] = { | ||
| 300 | [C(OP_READ)] = { | ||
| 301 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 302 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 303 | }, | ||
| 304 | [C(OP_WRITE)] = { | ||
| 305 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 306 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 307 | }, | ||
| 308 | [C(OP_PREFETCH)] = { | ||
| 309 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 310 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 311 | }, | ||
| 312 | }, | ||
| 313 | }; | ||
| 314 | |||
| 315 | static inline unsigned long | ||
| 316 | armv6_pmcr_read(void) | ||
| 317 | { | ||
| 318 | u32 val; | ||
| 319 | asm volatile("mrc p15, 0, %0, c15, c12, 0" : "=r"(val)); | ||
| 320 | return val; | ||
| 321 | } | ||
| 322 | |||
| 323 | static inline void | ||
| 324 | armv6_pmcr_write(unsigned long val) | ||
| 325 | { | ||
| 326 | asm volatile("mcr p15, 0, %0, c15, c12, 0" : : "r"(val)); | ||
| 327 | } | ||
| 328 | |||
| 329 | #define ARMV6_PMCR_ENABLE (1 << 0) | ||
| 330 | #define ARMV6_PMCR_CTR01_RESET (1 << 1) | ||
| 331 | #define ARMV6_PMCR_CCOUNT_RESET (1 << 2) | ||
| 332 | #define ARMV6_PMCR_CCOUNT_DIV (1 << 3) | ||
| 333 | #define ARMV6_PMCR_COUNT0_IEN (1 << 4) | ||
| 334 | #define ARMV6_PMCR_COUNT1_IEN (1 << 5) | ||
| 335 | #define ARMV6_PMCR_CCOUNT_IEN (1 << 6) | ||
| 336 | #define ARMV6_PMCR_COUNT0_OVERFLOW (1 << 8) | ||
| 337 | #define ARMV6_PMCR_COUNT1_OVERFLOW (1 << 9) | ||
| 338 | #define ARMV6_PMCR_CCOUNT_OVERFLOW (1 << 10) | ||
| 339 | #define ARMV6_PMCR_EVT_COUNT0_SHIFT 20 | ||
| 340 | #define ARMV6_PMCR_EVT_COUNT0_MASK (0xFF << ARMV6_PMCR_EVT_COUNT0_SHIFT) | ||
| 341 | #define ARMV6_PMCR_EVT_COUNT1_SHIFT 12 | ||
| 342 | #define ARMV6_PMCR_EVT_COUNT1_MASK (0xFF << ARMV6_PMCR_EVT_COUNT1_SHIFT) | ||
| 343 | |||
| 344 | #define ARMV6_PMCR_OVERFLOWED_MASK \ | ||
| 345 | (ARMV6_PMCR_COUNT0_OVERFLOW | ARMV6_PMCR_COUNT1_OVERFLOW | \ | ||
| 346 | ARMV6_PMCR_CCOUNT_OVERFLOW) | ||
| 347 | |||
| 348 | static inline int | ||
| 349 | armv6_pmcr_has_overflowed(unsigned long pmcr) | ||
| 350 | { | ||
| 351 | return pmcr & ARMV6_PMCR_OVERFLOWED_MASK; | ||
| 352 | } | ||
| 353 | |||
| 354 | static inline int | ||
| 355 | armv6_pmcr_counter_has_overflowed(unsigned long pmcr, | ||
| 356 | enum armv6_counters counter) | ||
| 357 | { | ||
| 358 | int ret = 0; | ||
| 359 | |||
| 360 | if (ARMV6_CYCLE_COUNTER == counter) | ||
| 361 | ret = pmcr & ARMV6_PMCR_CCOUNT_OVERFLOW; | ||
| 362 | else if (ARMV6_COUNTER0 == counter) | ||
| 363 | ret = pmcr & ARMV6_PMCR_COUNT0_OVERFLOW; | ||
| 364 | else if (ARMV6_COUNTER1 == counter) | ||
| 365 | ret = pmcr & ARMV6_PMCR_COUNT1_OVERFLOW; | ||
| 366 | else | ||
| 367 | WARN_ONCE(1, "invalid counter number (%d)\n", counter); | ||
| 368 | |||
| 369 | return ret; | ||
| 370 | } | ||
| 371 | |||
| 372 | static inline u32 | ||
| 373 | armv6pmu_read_counter(int counter) | ||
| 374 | { | ||
| 375 | unsigned long value = 0; | ||
| 376 | |||
| 377 | if (ARMV6_CYCLE_COUNTER == counter) | ||
| 378 | asm volatile("mrc p15, 0, %0, c15, c12, 1" : "=r"(value)); | ||
| 379 | else if (ARMV6_COUNTER0 == counter) | ||
| 380 | asm volatile("mrc p15, 0, %0, c15, c12, 2" : "=r"(value)); | ||
| 381 | else if (ARMV6_COUNTER1 == counter) | ||
| 382 | asm volatile("mrc p15, 0, %0, c15, c12, 3" : "=r"(value)); | ||
| 383 | else | ||
| 384 | WARN_ONCE(1, "invalid counter number (%d)\n", counter); | ||
| 385 | |||
| 386 | return value; | ||
| 387 | } | ||
| 388 | |||
| 389 | static inline void | ||
| 390 | armv6pmu_write_counter(int counter, | ||
| 391 | u32 value) | ||
| 392 | { | ||
| 393 | if (ARMV6_CYCLE_COUNTER == counter) | ||
| 394 | asm volatile("mcr p15, 0, %0, c15, c12, 1" : : "r"(value)); | ||
| 395 | else if (ARMV6_COUNTER0 == counter) | ||
| 396 | asm volatile("mcr p15, 0, %0, c15, c12, 2" : : "r"(value)); | ||
| 397 | else if (ARMV6_COUNTER1 == counter) | ||
| 398 | asm volatile("mcr p15, 0, %0, c15, c12, 3" : : "r"(value)); | ||
| 399 | else | ||
| 400 | WARN_ONCE(1, "invalid counter number (%d)\n", counter); | ||
| 401 | } | ||
| 402 | |||
| 403 | static void | ||
| 404 | armv6pmu_enable_event(struct hw_perf_event *hwc, | ||
| 405 | int idx) | ||
| 406 | { | ||
| 407 | unsigned long val, mask, evt, flags; | ||
| 408 | |||
| 409 | if (ARMV6_CYCLE_COUNTER == idx) { | ||
| 410 | mask = 0; | ||
| 411 | evt = ARMV6_PMCR_CCOUNT_IEN; | ||
| 412 | } else if (ARMV6_COUNTER0 == idx) { | ||
| 413 | mask = ARMV6_PMCR_EVT_COUNT0_MASK; | ||
| 414 | evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT0_SHIFT) | | ||
| 415 | ARMV6_PMCR_COUNT0_IEN; | ||
| 416 | } else if (ARMV6_COUNTER1 == idx) { | ||
| 417 | mask = ARMV6_PMCR_EVT_COUNT1_MASK; | ||
| 418 | evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT1_SHIFT) | | ||
| 419 | ARMV6_PMCR_COUNT1_IEN; | ||
| 420 | } else { | ||
| 421 | WARN_ONCE(1, "invalid counter number (%d)\n", idx); | ||
| 422 | return; | ||
| 423 | } | ||
| 424 | |||
| 425 | /* | ||
| 426 | * Mask out the current event and set the counter to count the event | ||
| 427 | * that we're interested in. | ||
| 428 | */ | ||
| 429 | raw_spin_lock_irqsave(&pmu_lock, flags); | ||
| 430 | val = armv6_pmcr_read(); | ||
| 431 | val &= ~mask; | ||
| 432 | val |= evt; | ||
| 433 | armv6_pmcr_write(val); | ||
| 434 | raw_spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 435 | } | ||
| 436 | |||
| 437 | static irqreturn_t | ||
| 438 | armv6pmu_handle_irq(int irq_num, | ||
| 439 | void *dev) | ||
| 440 | { | ||
| 441 | unsigned long pmcr = armv6_pmcr_read(); | ||
| 442 | struct perf_sample_data data; | ||
| 443 | struct cpu_hw_events *cpuc; | ||
| 444 | struct pt_regs *regs; | ||
| 445 | int idx; | ||
| 446 | |||
| 447 | if (!armv6_pmcr_has_overflowed(pmcr)) | ||
| 448 | return IRQ_NONE; | ||
| 449 | |||
| 450 | regs = get_irq_regs(); | ||
| 451 | |||
| 452 | /* | ||
| 453 | * The interrupts are cleared by writing the overflow flags back to | ||
| 454 | * the control register. All of the other bits don't have any effect | ||
| 455 | * if they are rewritten, so write the whole value back. | ||
| 456 | */ | ||
| 457 | armv6_pmcr_write(pmcr); | ||
| 458 | |||
| 459 | perf_sample_data_init(&data, 0); | ||
| 460 | |||
| 461 | cpuc = &__get_cpu_var(cpu_hw_events); | ||
| 462 | for (idx = 0; idx <= armpmu->num_events; ++idx) { | ||
| 463 | struct perf_event *event = cpuc->events[idx]; | ||
| 464 | struct hw_perf_event *hwc; | ||
| 465 | |||
| 466 | if (!test_bit(idx, cpuc->active_mask)) | ||
| 467 | continue; | ||
| 468 | |||
| 469 | /* | ||
| 470 | * We have a single interrupt for all counters. Check that | ||
| 471 | * each counter has overflowed before we process it. | ||
| 472 | */ | ||
| 473 | if (!armv6_pmcr_counter_has_overflowed(pmcr, idx)) | ||
| 474 | continue; | ||
| 475 | |||
| 476 | hwc = &event->hw; | ||
| 477 | armpmu_event_update(event, hwc, idx); | ||
| 478 | data.period = event->hw.last_period; | ||
| 479 | if (!armpmu_event_set_period(event, hwc, idx)) | ||
| 480 | continue; | ||
| 481 | |||
| 482 | if (perf_event_overflow(event, 0, &data, regs)) | ||
| 483 | armpmu->disable(hwc, idx); | ||
| 484 | } | ||
| 485 | |||
| 486 | /* | ||
| 487 | * Handle the pending perf events. | ||
| 488 | * | ||
| 489 | * Note: this call *must* be run with interrupts disabled. For | ||
| 490 | * platforms that can have the PMU interrupts raised as an NMI, this | ||
| 491 | * will not work. | ||
| 492 | */ | ||
| 493 | irq_work_run(); | ||
| 494 | |||
| 495 | return IRQ_HANDLED; | ||
| 496 | } | ||
| 497 | |||
| 498 | static void | ||
| 499 | armv6pmu_start(void) | ||
| 500 | { | ||
| 501 | unsigned long flags, val; | ||
| 502 | |||
| 503 | raw_spin_lock_irqsave(&pmu_lock, flags); | ||
| 504 | val = armv6_pmcr_read(); | ||
| 505 | val |= ARMV6_PMCR_ENABLE; | ||
| 506 | armv6_pmcr_write(val); | ||
| 507 | raw_spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 508 | } | ||
| 509 | |||
| 510 | static void | ||
| 511 | armv6pmu_stop(void) | ||
| 512 | { | ||
| 513 | unsigned long flags, val; | ||
| 514 | |||
| 515 | raw_spin_lock_irqsave(&pmu_lock, flags); | ||
| 516 | val = armv6_pmcr_read(); | ||
| 517 | val &= ~ARMV6_PMCR_ENABLE; | ||
| 518 | armv6_pmcr_write(val); | ||
| 519 | raw_spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 520 | } | ||
| 521 | |||
| 522 | static int | ||
| 523 | armv6pmu_get_event_idx(struct cpu_hw_events *cpuc, | ||
| 524 | struct hw_perf_event *event) | ||
| 525 | { | ||
| 526 | /* Always place a cycle counter into the cycle counter. */ | ||
| 527 | if (ARMV6_PERFCTR_CPU_CYCLES == event->config_base) { | ||
| 528 | if (test_and_set_bit(ARMV6_CYCLE_COUNTER, cpuc->used_mask)) | ||
| 529 | return -EAGAIN; | ||
| 530 | |||
| 531 | return ARMV6_CYCLE_COUNTER; | ||
| 532 | } else { | ||
| 533 | /* | ||
| 534 | * For anything other than a cycle counter, try and use | ||
| 535 | * counter0 and counter1. | ||
| 536 | */ | ||
| 537 | if (!test_and_set_bit(ARMV6_COUNTER1, cpuc->used_mask)) | ||
| 538 | return ARMV6_COUNTER1; | ||
| 539 | |||
| 540 | if (!test_and_set_bit(ARMV6_COUNTER0, cpuc->used_mask)) | ||
| 541 | return ARMV6_COUNTER0; | ||
| 542 | |||
| 543 | /* The counters are all in use. */ | ||
| 544 | return -EAGAIN; | ||
| 545 | } | ||
| 546 | } | ||
| 547 | |||
| 548 | static void | ||
| 549 | armv6pmu_disable_event(struct hw_perf_event *hwc, | ||
| 550 | int idx) | ||
| 551 | { | ||
| 552 | unsigned long val, mask, evt, flags; | ||
| 553 | |||
| 554 | if (ARMV6_CYCLE_COUNTER == idx) { | ||
| 555 | mask = ARMV6_PMCR_CCOUNT_IEN; | ||
| 556 | evt = 0; | ||
| 557 | } else if (ARMV6_COUNTER0 == idx) { | ||
| 558 | mask = ARMV6_PMCR_COUNT0_IEN | ARMV6_PMCR_EVT_COUNT0_MASK; | ||
| 559 | evt = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT0_SHIFT; | ||
| 560 | } else if (ARMV6_COUNTER1 == idx) { | ||
| 561 | mask = ARMV6_PMCR_COUNT1_IEN | ARMV6_PMCR_EVT_COUNT1_MASK; | ||
| 562 | evt = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT1_SHIFT; | ||
| 563 | } else { | ||
| 564 | WARN_ONCE(1, "invalid counter number (%d)\n", idx); | ||
| 565 | return; | ||
| 566 | } | ||
| 567 | |||
| 568 | /* | ||
| 569 | * Mask out the current event and set the counter to count the number | ||
| 570 | * of ETM bus signal assertion cycles. The external reporting should | ||
| 571 | * be disabled and so this should never increment. | ||
| 572 | */ | ||
| 573 | raw_spin_lock_irqsave(&pmu_lock, flags); | ||
| 574 | val = armv6_pmcr_read(); | ||
| 575 | val &= ~mask; | ||
| 576 | val |= evt; | ||
| 577 | armv6_pmcr_write(val); | ||
| 578 | raw_spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 579 | } | ||
| 580 | |||
| 581 | static void | ||
| 582 | armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc, | ||
| 583 | int idx) | ||
| 584 | { | ||
| 585 | unsigned long val, mask, flags, evt = 0; | ||
| 586 | |||
| 587 | if (ARMV6_CYCLE_COUNTER == idx) { | ||
| 588 | mask = ARMV6_PMCR_CCOUNT_IEN; | ||
| 589 | } else if (ARMV6_COUNTER0 == idx) { | ||
| 590 | mask = ARMV6_PMCR_COUNT0_IEN; | ||
| 591 | } else if (ARMV6_COUNTER1 == idx) { | ||
| 592 | mask = ARMV6_PMCR_COUNT1_IEN; | ||
| 593 | } else { | ||
| 594 | WARN_ONCE(1, "invalid counter number (%d)\n", idx); | ||
| 595 | return; | ||
| 596 | } | ||
| 597 | |||
| 598 | /* | ||
| 599 | * Unlike UP ARMv6, we don't have a way of stopping the counters. We | ||
| 600 | * simply disable the interrupt reporting. | ||
| 601 | */ | ||
| 602 | raw_spin_lock_irqsave(&pmu_lock, flags); | ||
| 603 | val = armv6_pmcr_read(); | ||
| 604 | val &= ~mask; | ||
| 605 | val |= evt; | ||
| 606 | armv6_pmcr_write(val); | ||
| 607 | raw_spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 608 | } | ||
| 609 | |||
| 610 | static const struct arm_pmu armv6pmu = { | ||
| 611 | .id = ARM_PERF_PMU_ID_V6, | ||
| 612 | .name = "v6", | ||
| 613 | .handle_irq = armv6pmu_handle_irq, | ||
| 614 | .enable = armv6pmu_enable_event, | ||
| 615 | .disable = armv6pmu_disable_event, | ||
| 616 | .read_counter = armv6pmu_read_counter, | ||
| 617 | .write_counter = armv6pmu_write_counter, | ||
| 618 | .get_event_idx = armv6pmu_get_event_idx, | ||
| 619 | .start = armv6pmu_start, | ||
| 620 | .stop = armv6pmu_stop, | ||
| 621 | .cache_map = &armv6_perf_cache_map, | ||
| 622 | .event_map = &armv6_perf_map, | ||
| 623 | .raw_event_mask = 0xFF, | ||
| 624 | .num_events = 3, | ||
| 625 | .max_period = (1LLU << 32) - 1, | ||
| 626 | }; | ||
| 627 | |||
| 628 | static const struct arm_pmu *__init armv6pmu_init(void) | ||
| 629 | { | ||
| 630 | return &armv6pmu; | ||
| 631 | } | ||
| 632 | |||
| 633 | /* | ||
| 634 | * ARMv6mpcore is almost identical to single core ARMv6 with the exception | ||
| 635 | * that some of the events have different enumerations and that there is no | ||
| 636 | * *hack* to stop the programmable counters. To stop the counters we simply | ||
| 637 | * disable the interrupt reporting and update the event. When unthrottling we | ||
| 638 | * reset the period and enable the interrupt reporting. | ||
| 639 | */ | ||
| 640 | static const struct arm_pmu armv6mpcore_pmu = { | ||
| 641 | .id = ARM_PERF_PMU_ID_V6MP, | ||
| 642 | .name = "v6mpcore", | ||
| 643 | .handle_irq = armv6pmu_handle_irq, | ||
| 644 | .enable = armv6pmu_enable_event, | ||
| 645 | .disable = armv6mpcore_pmu_disable_event, | ||
| 646 | .read_counter = armv6pmu_read_counter, | ||
| 647 | .write_counter = armv6pmu_write_counter, | ||
| 648 | .get_event_idx = armv6pmu_get_event_idx, | ||
| 649 | .start = armv6pmu_start, | ||
| 650 | .stop = armv6pmu_stop, | ||
| 651 | .cache_map = &armv6mpcore_perf_cache_map, | ||
| 652 | .event_map = &armv6mpcore_perf_map, | ||
| 653 | .raw_event_mask = 0xFF, | ||
| 654 | .num_events = 3, | ||
| 655 | .max_period = (1LLU << 32) - 1, | ||
| 656 | }; | ||
| 657 | |||
| 658 | static const struct arm_pmu *__init armv6mpcore_pmu_init(void) | ||
| 659 | { | ||
| 660 | return &armv6mpcore_pmu; | ||
| 661 | } | ||
| 662 | #else | ||
| 663 | static const struct arm_pmu *__init armv6pmu_init(void) | ||
| 664 | { | ||
| 665 | return NULL; | ||
| 666 | } | ||
| 667 | |||
| 668 | static const struct arm_pmu *__init armv6mpcore_pmu_init(void) | ||
| 669 | { | ||
| 670 | return NULL; | ||
| 671 | } | ||
| 672 | #endif /* CONFIG_CPU_V6 */ | ||
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c new file mode 100644 index 000000000000..2e1402556fa0 --- /dev/null +++ b/arch/arm/kernel/perf_event_v7.c | |||
| @@ -0,0 +1,906 @@ | |||
| 1 | /* | ||
| 2 | * ARMv7 Cortex-A8 and Cortex-A9 Performance Events handling code. | ||
| 3 | * | ||
| 4 | * ARMv7 support: Jean Pihet <jpihet@mvista.com> | ||
| 5 | * 2010 (c) MontaVista Software, LLC. | ||
| 6 | * | ||
| 7 | * Copied from ARMv6 code, with the low level code inspired | ||
| 8 | * by the ARMv7 Oprofile code. | ||
| 9 | * | ||
| 10 | * Cortex-A8 has up to 4 configurable performance counters and | ||
| 11 | * a single cycle counter. | ||
| 12 | * Cortex-A9 has up to 31 configurable performance counters and | ||
| 13 | * a single cycle counter. | ||
| 14 | * | ||
| 15 | * All counters can be enabled/disabled and IRQ masked separately. The cycle | ||
| 16 | * counter and all 4 performance counters together can be reset separately. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifdef CONFIG_CPU_V7 | ||
| 20 | /* Common ARMv7 event types */ | ||
| 21 | enum armv7_perf_types { | ||
| 22 | ARMV7_PERFCTR_PMNC_SW_INCR = 0x00, | ||
| 23 | ARMV7_PERFCTR_IFETCH_MISS = 0x01, | ||
| 24 | ARMV7_PERFCTR_ITLB_MISS = 0x02, | ||
| 25 | ARMV7_PERFCTR_DCACHE_REFILL = 0x03, | ||
| 26 | ARMV7_PERFCTR_DCACHE_ACCESS = 0x04, | ||
| 27 | ARMV7_PERFCTR_DTLB_REFILL = 0x05, | ||
| 28 | ARMV7_PERFCTR_DREAD = 0x06, | ||
| 29 | ARMV7_PERFCTR_DWRITE = 0x07, | ||
| 30 | |||
| 31 | ARMV7_PERFCTR_EXC_TAKEN = 0x09, | ||
| 32 | ARMV7_PERFCTR_EXC_EXECUTED = 0x0A, | ||
| 33 | ARMV7_PERFCTR_CID_WRITE = 0x0B, | ||
| 34 | /* ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS. | ||
| 35 | * It counts: | ||
| 36 | * - all branch instructions, | ||
| 37 | * - instructions that explicitly write the PC, | ||
| 38 | * - exception generating instructions. | ||
| 39 | */ | ||
| 40 | ARMV7_PERFCTR_PC_WRITE = 0x0C, | ||
| 41 | ARMV7_PERFCTR_PC_IMM_BRANCH = 0x0D, | ||
| 42 | ARMV7_PERFCTR_UNALIGNED_ACCESS = 0x0F, | ||
| 43 | ARMV7_PERFCTR_PC_BRANCH_MIS_PRED = 0x10, | ||
| 44 | ARMV7_PERFCTR_CLOCK_CYCLES = 0x11, | ||
| 45 | |||
| 46 | ARMV7_PERFCTR_PC_BRANCH_MIS_USED = 0x12, | ||
| 47 | |||
| 48 | ARMV7_PERFCTR_CPU_CYCLES = 0xFF | ||
| 49 | }; | ||
| 50 | |||
| 51 | /* ARMv7 Cortex-A8 specific event types */ | ||
| 52 | enum armv7_a8_perf_types { | ||
| 53 | ARMV7_PERFCTR_INSTR_EXECUTED = 0x08, | ||
| 54 | |||
| 55 | ARMV7_PERFCTR_PC_PROC_RETURN = 0x0E, | ||
| 56 | |||
| 57 | ARMV7_PERFCTR_WRITE_BUFFER_FULL = 0x40, | ||
| 58 | ARMV7_PERFCTR_L2_STORE_MERGED = 0x41, | ||
| 59 | ARMV7_PERFCTR_L2_STORE_BUFF = 0x42, | ||
| 60 | ARMV7_PERFCTR_L2_ACCESS = 0x43, | ||
| 61 | ARMV7_PERFCTR_L2_CACH_MISS = 0x44, | ||
| 62 | ARMV7_PERFCTR_AXI_READ_CYCLES = 0x45, | ||
| 63 | ARMV7_PERFCTR_AXI_WRITE_CYCLES = 0x46, | ||
| 64 | ARMV7_PERFCTR_MEMORY_REPLAY = 0x47, | ||
| 65 | ARMV7_PERFCTR_UNALIGNED_ACCESS_REPLAY = 0x48, | ||
| 66 | ARMV7_PERFCTR_L1_DATA_MISS = 0x49, | ||
| 67 | ARMV7_PERFCTR_L1_INST_MISS = 0x4A, | ||
| 68 | ARMV7_PERFCTR_L1_DATA_COLORING = 0x4B, | ||
| 69 | ARMV7_PERFCTR_L1_NEON_DATA = 0x4C, | ||
| 70 | ARMV7_PERFCTR_L1_NEON_CACH_DATA = 0x4D, | ||
| 71 | ARMV7_PERFCTR_L2_NEON = 0x4E, | ||
| 72 | ARMV7_PERFCTR_L2_NEON_HIT = 0x4F, | ||
| 73 | ARMV7_PERFCTR_L1_INST = 0x50, | ||
| 74 | ARMV7_PERFCTR_PC_RETURN_MIS_PRED = 0x51, | ||
| 75 | ARMV7_PERFCTR_PC_BRANCH_FAILED = 0x52, | ||
| 76 | ARMV7_PERFCTR_PC_BRANCH_TAKEN = 0x53, | ||
| 77 | ARMV7_PERFCTR_PC_BRANCH_EXECUTED = 0x54, | ||
| 78 | ARMV7_PERFCTR_OP_EXECUTED = 0x55, | ||
| 79 | ARMV7_PERFCTR_CYCLES_INST_STALL = 0x56, | ||
| 80 | ARMV7_PERFCTR_CYCLES_INST = 0x57, | ||
| 81 | ARMV7_PERFCTR_CYCLES_NEON_DATA_STALL = 0x58, | ||
| 82 | ARMV7_PERFCTR_CYCLES_NEON_INST_STALL = 0x59, | ||
| 83 | ARMV7_PERFCTR_NEON_CYCLES = 0x5A, | ||
| 84 | |||
| 85 | ARMV7_PERFCTR_PMU0_EVENTS = 0x70, | ||
| 86 | ARMV7_PERFCTR_PMU1_EVENTS = 0x71, | ||
| 87 | ARMV7_PERFCTR_PMU_EVENTS = 0x72, | ||
| 88 | }; | ||
| 89 | |||
| 90 | /* ARMv7 Cortex-A9 specific event types */ | ||
| 91 | enum armv7_a9_perf_types { | ||
| 92 | ARMV7_PERFCTR_JAVA_HW_BYTECODE_EXEC = 0x40, | ||
| 93 | ARMV7_PERFCTR_JAVA_SW_BYTECODE_EXEC = 0x41, | ||
| 94 | ARMV7_PERFCTR_JAZELLE_BRANCH_EXEC = 0x42, | ||
| 95 | |||
| 96 | ARMV7_PERFCTR_COHERENT_LINE_MISS = 0x50, | ||
| 97 | ARMV7_PERFCTR_COHERENT_LINE_HIT = 0x51, | ||
| 98 | |||
| 99 | ARMV7_PERFCTR_ICACHE_DEP_STALL_CYCLES = 0x60, | ||
| 100 | ARMV7_PERFCTR_DCACHE_DEP_STALL_CYCLES = 0x61, | ||
| 101 | ARMV7_PERFCTR_TLB_MISS_DEP_STALL_CYCLES = 0x62, | ||
| 102 | ARMV7_PERFCTR_STREX_EXECUTED_PASSED = 0x63, | ||
| 103 | ARMV7_PERFCTR_STREX_EXECUTED_FAILED = 0x64, | ||
| 104 | ARMV7_PERFCTR_DATA_EVICTION = 0x65, | ||
| 105 | ARMV7_PERFCTR_ISSUE_STAGE_NO_INST = 0x66, | ||
| 106 | ARMV7_PERFCTR_ISSUE_STAGE_EMPTY = 0x67, | ||
| 107 | ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE = 0x68, | ||
| 108 | |||
| 109 | ARMV7_PERFCTR_PREDICTABLE_FUNCT_RETURNS = 0x6E, | ||
| 110 | |||
| 111 | ARMV7_PERFCTR_MAIN_UNIT_EXECUTED_INST = 0x70, | ||
| 112 | ARMV7_PERFCTR_SECOND_UNIT_EXECUTED_INST = 0x71, | ||
| 113 | ARMV7_PERFCTR_LD_ST_UNIT_EXECUTED_INST = 0x72, | ||
| 114 | ARMV7_PERFCTR_FP_EXECUTED_INST = 0x73, | ||
| 115 | ARMV7_PERFCTR_NEON_EXECUTED_INST = 0x74, | ||
| 116 | |||
| 117 | ARMV7_PERFCTR_PLD_FULL_DEP_STALL_CYCLES = 0x80, | ||
| 118 | ARMV7_PERFCTR_DATA_WR_DEP_STALL_CYCLES = 0x81, | ||
| 119 | ARMV7_PERFCTR_ITLB_MISS_DEP_STALL_CYCLES = 0x82, | ||
| 120 | ARMV7_PERFCTR_DTLB_MISS_DEP_STALL_CYCLES = 0x83, | ||
| 121 | ARMV7_PERFCTR_MICRO_ITLB_MISS_DEP_STALL_CYCLES = 0x84, | ||
| 122 | ARMV7_PERFCTR_MICRO_DTLB_MISS_DEP_STALL_CYCLES = 0x85, | ||
| 123 | ARMV7_PERFCTR_DMB_DEP_STALL_CYCLES = 0x86, | ||
| 124 | |||
| 125 | ARMV7_PERFCTR_INTGR_CLK_ENABLED_CYCLES = 0x8A, | ||
| 126 | ARMV7_PERFCTR_DATA_ENGINE_CLK_EN_CYCLES = 0x8B, | ||
| 127 | |||
| 128 | ARMV7_PERFCTR_ISB_INST = 0x90, | ||
| 129 | ARMV7_PERFCTR_DSB_INST = 0x91, | ||
| 130 | ARMV7_PERFCTR_DMB_INST = 0x92, | ||
| 131 | ARMV7_PERFCTR_EXT_INTERRUPTS = 0x93, | ||
| 132 | |||
| 133 | ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_COMPLETED = 0xA0, | ||
| 134 | ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_SKIPPED = 0xA1, | ||
| 135 | ARMV7_PERFCTR_PLE_FIFO_FLUSH = 0xA2, | ||
| 136 | ARMV7_PERFCTR_PLE_RQST_COMPLETED = 0xA3, | ||
| 137 | ARMV7_PERFCTR_PLE_FIFO_OVERFLOW = 0xA4, | ||
| 138 | ARMV7_PERFCTR_PLE_RQST_PROG = 0xA5 | ||
| 139 | }; | ||
| 140 | |||
| 141 | /* | ||
| 142 | * Cortex-A8 HW events mapping | ||
| 143 | * | ||
| 144 | * The hardware events that we support. We do support cache operations but | ||
| 145 | * we have harvard caches and no way to combine instruction and data | ||
| 146 | * accesses/misses in hardware. | ||
| 147 | */ | ||
| 148 | static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = { | ||
| 149 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, | ||
| 150 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, | ||
| 151 | [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, | ||
| 152 | [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, | ||
| 153 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, | ||
| 154 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, | ||
| 155 | [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, | ||
| 156 | }; | ||
| 157 | |||
| 158 | static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | ||
| 159 | [PERF_COUNT_HW_CACHE_OP_MAX] | ||
| 160 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { | ||
| 161 | [C(L1D)] = { | ||
| 162 | /* | ||
| 163 | * The performance counters don't differentiate between read | ||
| 164 | * and write accesses/misses so this isn't strictly correct, | ||
| 165 | * but it's the best we can do. Writes and reads get | ||
| 166 | * combined. | ||
| 167 | */ | ||
| 168 | [C(OP_READ)] = { | ||
| 169 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS, | ||
| 170 | [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL, | ||
| 171 | }, | ||
| 172 | [C(OP_WRITE)] = { | ||
| 173 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS, | ||
| 174 | [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL, | ||
| 175 | }, | ||
| 176 | [C(OP_PREFETCH)] = { | ||
| 177 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 178 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 179 | }, | ||
| 180 | }, | ||
| 181 | [C(L1I)] = { | ||
| 182 | [C(OP_READ)] = { | ||
| 183 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_INST, | ||
| 184 | [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_INST_MISS, | ||
| 185 | }, | ||
| 186 | [C(OP_WRITE)] = { | ||
| 187 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_INST, | ||
| 188 | [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_INST_MISS, | ||
| 189 | }, | ||
| 190 | [C(OP_PREFETCH)] = { | ||
| 191 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 192 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 193 | }, | ||
| 194 | }, | ||
| 195 | [C(LL)] = { | ||
| 196 | [C(OP_READ)] = { | ||
| 197 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_ACCESS, | ||
| 198 | [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACH_MISS, | ||
| 199 | }, | ||
| 200 | [C(OP_WRITE)] = { | ||
| 201 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_ACCESS, | ||
| 202 | [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACH_MISS, | ||
| 203 | }, | ||
| 204 | [C(OP_PREFETCH)] = { | ||
| 205 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 206 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 207 | }, | ||
| 208 | }, | ||
| 209 | [C(DTLB)] = { | ||
| 210 | /* | ||
| 211 | * Only ITLB misses and DTLB refills are supported. | ||
| 212 | * If users want the DTLB refills misses a raw counter | ||
| 213 | * must be used. | ||
| 214 | */ | ||
| 215 | [C(OP_READ)] = { | ||
| 216 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 217 | [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, | ||
| 218 | }, | ||
| 219 | [C(OP_WRITE)] = { | ||
| 220 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 221 | [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, | ||
| 222 | }, | ||
| 223 | [C(OP_PREFETCH)] = { | ||
| 224 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 225 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 226 | }, | ||
| 227 | }, | ||
| 228 | [C(ITLB)] = { | ||
| 229 | [C(OP_READ)] = { | ||
| 230 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 231 | [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS, | ||
| 232 | }, | ||
| 233 | [C(OP_WRITE)] = { | ||
| 234 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 235 | [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS, | ||
| 236 | }, | ||
| 237 | [C(OP_PREFETCH)] = { | ||
| 238 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 239 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 240 | }, | ||
| 241 | }, | ||
| 242 | [C(BPU)] = { | ||
| 243 | [C(OP_READ)] = { | ||
| 244 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE, | ||
| 245 | [C(RESULT_MISS)] | ||
| 246 | = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, | ||
| 247 | }, | ||
| 248 | [C(OP_WRITE)] = { | ||
| 249 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE, | ||
| 250 | [C(RESULT_MISS)] | ||
| 251 | = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, | ||
| 252 | }, | ||
| 253 | [C(OP_PREFETCH)] = { | ||
| 254 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 255 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 256 | }, | ||
| 257 | }, | ||
| 258 | }; | ||
| 259 | |||
| 260 | /* | ||
| 261 | * Cortex-A9 HW events mapping | ||
| 262 | */ | ||
| 263 | static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = { | ||
| 264 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, | ||
| 265 | [PERF_COUNT_HW_INSTRUCTIONS] = | ||
| 266 | ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE, | ||
| 267 | [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_COHERENT_LINE_HIT, | ||
| 268 | [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_COHERENT_LINE_MISS, | ||
| 269 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, | ||
| 270 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, | ||
| 271 | [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, | ||
| 272 | }; | ||
| 273 | |||
| 274 | static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | ||
| 275 | [PERF_COUNT_HW_CACHE_OP_MAX] | ||
| 276 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { | ||
| 277 | [C(L1D)] = { | ||
| 278 | /* | ||
| 279 | * The performance counters don't differentiate between read | ||
| 280 | * and write accesses/misses so this isn't strictly correct, | ||
| 281 | * but it's the best we can do. Writes and reads get | ||
| 282 | * combined. | ||
| 283 | */ | ||
| 284 | [C(OP_READ)] = { | ||
| 285 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS, | ||
| 286 | [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL, | ||
| 287 | }, | ||
| 288 | [C(OP_WRITE)] = { | ||
| 289 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS, | ||
| 290 | [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL, | ||
| 291 | }, | ||
| 292 | [C(OP_PREFETCH)] = { | ||
| 293 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 294 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 295 | }, | ||
| 296 | }, | ||
| 297 | [C(L1I)] = { | ||
| 298 | [C(OP_READ)] = { | ||
| 299 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 300 | [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS, | ||
| 301 | }, | ||
| 302 | [C(OP_WRITE)] = { | ||
| 303 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 304 | [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS, | ||
| 305 | }, | ||
| 306 | [C(OP_PREFETCH)] = { | ||
| 307 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 308 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 309 | }, | ||
| 310 | }, | ||
| 311 | [C(LL)] = { | ||
| 312 | [C(OP_READ)] = { | ||
| 313 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 314 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 315 | }, | ||
| 316 | [C(OP_WRITE)] = { | ||
| 317 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 318 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 319 | }, | ||
| 320 | [C(OP_PREFETCH)] = { | ||
| 321 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 322 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 323 | }, | ||
| 324 | }, | ||
| 325 | [C(DTLB)] = { | ||
| 326 | /* | ||
| 327 | * Only ITLB misses and DTLB refills are supported. | ||
| 328 | * If users want the DTLB refills misses a raw counter | ||
| 329 | * must be used. | ||
| 330 | */ | ||
| 331 | [C(OP_READ)] = { | ||
| 332 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 333 | [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, | ||
| 334 | }, | ||
| 335 | [C(OP_WRITE)] = { | ||
| 336 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 337 | [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, | ||
| 338 | }, | ||
| 339 | [C(OP_PREFETCH)] = { | ||
| 340 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 341 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 342 | }, | ||
| 343 | }, | ||
| 344 | [C(ITLB)] = { | ||
| 345 | [C(OP_READ)] = { | ||
| 346 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 347 | [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS, | ||
| 348 | }, | ||
| 349 | [C(OP_WRITE)] = { | ||
| 350 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 351 | [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS, | ||
| 352 | }, | ||
| 353 | [C(OP_PREFETCH)] = { | ||
| 354 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 355 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 356 | }, | ||
| 357 | }, | ||
| 358 | [C(BPU)] = { | ||
| 359 | [C(OP_READ)] = { | ||
| 360 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE, | ||
| 361 | [C(RESULT_MISS)] | ||
| 362 | = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, | ||
| 363 | }, | ||
| 364 | [C(OP_WRITE)] = { | ||
| 365 | [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE, | ||
| 366 | [C(RESULT_MISS)] | ||
| 367 | = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, | ||
| 368 | }, | ||
| 369 | [C(OP_PREFETCH)] = { | ||
| 370 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 371 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 372 | }, | ||
| 373 | }, | ||
| 374 | }; | ||
| 375 | |||
| 376 | /* | ||
| 377 | * Perf Events counters | ||
| 378 | */ | ||
| 379 | enum armv7_counters { | ||
| 380 | ARMV7_CYCLE_COUNTER = 1, /* Cycle counter */ | ||
| 381 | ARMV7_COUNTER0 = 2, /* First event counter */ | ||
| 382 | }; | ||
| 383 | |||
| 384 | /* | ||
| 385 | * The cycle counter is ARMV7_CYCLE_COUNTER. | ||
| 386 | * The first event counter is ARMV7_COUNTER0. | ||
| 387 | * The last event counter is (ARMV7_COUNTER0 + armpmu->num_events - 1). | ||
| 388 | */ | ||
| 389 | #define ARMV7_COUNTER_LAST (ARMV7_COUNTER0 + armpmu->num_events - 1) | ||
| 390 | |||
| 391 | /* | ||
| 392 | * ARMv7 low level PMNC access | ||
| 393 | */ | ||
| 394 | |||
| 395 | /* | ||
| 396 | * Per-CPU PMNC: config reg | ||
| 397 | */ | ||
| 398 | #define ARMV7_PMNC_E (1 << 0) /* Enable all counters */ | ||
| 399 | #define ARMV7_PMNC_P (1 << 1) /* Reset all counters */ | ||
| 400 | #define ARMV7_PMNC_C (1 << 2) /* Cycle counter reset */ | ||
| 401 | #define ARMV7_PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */ | ||
| 402 | #define ARMV7_PMNC_X (1 << 4) /* Export to ETM */ | ||
| 403 | #define ARMV7_PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ | ||
| 404 | #define ARMV7_PMNC_N_SHIFT 11 /* Number of counters supported */ | ||
| 405 | #define ARMV7_PMNC_N_MASK 0x1f | ||
| 406 | #define ARMV7_PMNC_MASK 0x3f /* Mask for writable bits */ | ||
| 407 | |||
| 408 | /* | ||
| 409 | * Available counters | ||
| 410 | */ | ||
| 411 | #define ARMV7_CNT0 0 /* First event counter */ | ||
| 412 | #define ARMV7_CCNT 31 /* Cycle counter */ | ||
| 413 | |||
| 414 | /* Perf Event to low level counters mapping */ | ||
| 415 | #define ARMV7_EVENT_CNT_TO_CNTx (ARMV7_COUNTER0 - ARMV7_CNT0) | ||
| 416 | |||
| 417 | /* | ||
| 418 | * CNTENS: counters enable reg | ||
| 419 | */ | ||
| 420 | #define ARMV7_CNTENS_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx)) | ||
| 421 | #define ARMV7_CNTENS_C (1 << ARMV7_CCNT) | ||
| 422 | |||
| 423 | /* | ||
| 424 | * CNTENC: counters disable reg | ||
| 425 | */ | ||
| 426 | #define ARMV7_CNTENC_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx)) | ||
| 427 | #define ARMV7_CNTENC_C (1 << ARMV7_CCNT) | ||
| 428 | |||
| 429 | /* | ||
| 430 | * INTENS: counters overflow interrupt enable reg | ||
| 431 | */ | ||
| 432 | #define ARMV7_INTENS_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx)) | ||
| 433 | #define ARMV7_INTENS_C (1 << ARMV7_CCNT) | ||
| 434 | |||
| 435 | /* | ||
| 436 | * INTENC: counters overflow interrupt disable reg | ||
| 437 | */ | ||
| 438 | #define ARMV7_INTENC_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx)) | ||
| 439 | #define ARMV7_INTENC_C (1 << ARMV7_CCNT) | ||
| 440 | |||
| 441 | /* | ||
| 442 | * EVTSEL: Event selection reg | ||
| 443 | */ | ||
| 444 | #define ARMV7_EVTSEL_MASK 0xff /* Mask for writable bits */ | ||
| 445 | |||
| 446 | /* | ||
| 447 | * SELECT: Counter selection reg | ||
| 448 | */ | ||
| 449 | #define ARMV7_SELECT_MASK 0x1f /* Mask for writable bits */ | ||
| 450 | |||
| 451 | /* | ||
| 452 | * FLAG: counters overflow flag status reg | ||
| 453 | */ | ||
| 454 | #define ARMV7_FLAG_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx)) | ||
| 455 | #define ARMV7_FLAG_C (1 << ARMV7_CCNT) | ||
| 456 | #define ARMV7_FLAG_MASK 0xffffffff /* Mask for writable bits */ | ||
| 457 | #define ARMV7_OVERFLOWED_MASK ARMV7_FLAG_MASK | ||
| 458 | |||
| 459 | static inline unsigned long armv7_pmnc_read(void) | ||
| 460 | { | ||
| 461 | u32 val; | ||
| 462 | asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val)); | ||
| 463 | return val; | ||
| 464 | } | ||
| 465 | |||
| 466 | static inline void armv7_pmnc_write(unsigned long val) | ||
| 467 | { | ||
| 468 | val &= ARMV7_PMNC_MASK; | ||
| 469 | asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val)); | ||
| 470 | } | ||
| 471 | |||
| 472 | static inline int armv7_pmnc_has_overflowed(unsigned long pmnc) | ||
| 473 | { | ||
| 474 | return pmnc & ARMV7_OVERFLOWED_MASK; | ||
| 475 | } | ||
| 476 | |||
| 477 | static inline int armv7_pmnc_counter_has_overflowed(unsigned long pmnc, | ||
| 478 | enum armv7_counters counter) | ||
| 479 | { | ||
| 480 | int ret = 0; | ||
| 481 | |||
| 482 | if (counter == ARMV7_CYCLE_COUNTER) | ||
| 483 | ret = pmnc & ARMV7_FLAG_C; | ||
| 484 | else if ((counter >= ARMV7_COUNTER0) && (counter <= ARMV7_COUNTER_LAST)) | ||
| 485 | ret = pmnc & ARMV7_FLAG_P(counter); | ||
| 486 | else | ||
| 487 | pr_err("CPU%u checking wrong counter %d overflow status\n", | ||
| 488 | smp_processor_id(), counter); | ||
| 489 | |||
| 490 | return ret; | ||
| 491 | } | ||
| 492 | |||
| 493 | static inline int armv7_pmnc_select_counter(unsigned int idx) | ||
| 494 | { | ||
| 495 | u32 val; | ||
| 496 | |||
| 497 | if ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST)) { | ||
| 498 | pr_err("CPU%u selecting wrong PMNC counter" | ||
| 499 | " %d\n", smp_processor_id(), idx); | ||
| 500 | return -1; | ||
| 501 | } | ||
| 502 | |||
| 503 | val = (idx - ARMV7_EVENT_CNT_TO_CNTx) & ARMV7_SELECT_MASK; | ||
| 504 | asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val)); | ||
| 505 | |||
| 506 | return idx; | ||
| 507 | } | ||
| 508 | |||
| 509 | static inline u32 armv7pmu_read_counter(int idx) | ||
| 510 | { | ||
| 511 | unsigned long value = 0; | ||
| 512 | |||
| 513 | if (idx == ARMV7_CYCLE_COUNTER) | ||
| 514 | asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value)); | ||
| 515 | else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) { | ||
| 516 | if (armv7_pmnc_select_counter(idx) == idx) | ||
| 517 | asm volatile("mrc p15, 0, %0, c9, c13, 2" | ||
| 518 | : "=r" (value)); | ||
| 519 | } else | ||
| 520 | pr_err("CPU%u reading wrong counter %d\n", | ||
| 521 | smp_processor_id(), idx); | ||
| 522 | |||
| 523 | return value; | ||
| 524 | } | ||
| 525 | |||
| 526 | static inline void armv7pmu_write_counter(int idx, u32 value) | ||
| 527 | { | ||
| 528 | if (idx == ARMV7_CYCLE_COUNTER) | ||
| 529 | asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (value)); | ||
| 530 | else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) { | ||
| 531 | if (armv7_pmnc_select_counter(idx) == idx) | ||
| 532 | asm volatile("mcr p15, 0, %0, c9, c13, 2" | ||
| 533 | : : "r" (value)); | ||
| 534 | } else | ||
| 535 | pr_err("CPU%u writing wrong counter %d\n", | ||
| 536 | smp_processor_id(), idx); | ||
| 537 | } | ||
| 538 | |||
| 539 | static inline void armv7_pmnc_write_evtsel(unsigned int idx, u32 val) | ||
| 540 | { | ||
| 541 | if (armv7_pmnc_select_counter(idx) == idx) { | ||
| 542 | val &= ARMV7_EVTSEL_MASK; | ||
| 543 | asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val)); | ||
| 544 | } | ||
| 545 | } | ||
| 546 | |||
| 547 | static inline u32 armv7_pmnc_enable_counter(unsigned int idx) | ||
| 548 | { | ||
| 549 | u32 val; | ||
| 550 | |||
| 551 | if ((idx != ARMV7_CYCLE_COUNTER) && | ||
| 552 | ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) { | ||
| 553 | pr_err("CPU%u enabling wrong PMNC counter" | ||
| 554 | " %d\n", smp_processor_id(), idx); | ||
| 555 | return -1; | ||
| 556 | } | ||
| 557 | |||
| 558 | if (idx == ARMV7_CYCLE_COUNTER) | ||
| 559 | val = ARMV7_CNTENS_C; | ||
| 560 | else | ||
| 561 | val = ARMV7_CNTENS_P(idx); | ||
| 562 | |||
| 563 | asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (val)); | ||
| 564 | |||
| 565 | return idx; | ||
| 566 | } | ||
| 567 | |||
| 568 | static inline u32 armv7_pmnc_disable_counter(unsigned int idx) | ||
| 569 | { | ||
| 570 | u32 val; | ||
| 571 | |||
| 572 | |||
| 573 | if ((idx != ARMV7_CYCLE_COUNTER) && | ||
| 574 | ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) { | ||
| 575 | pr_err("CPU%u disabling wrong PMNC counter" | ||
| 576 | " %d\n", smp_processor_id(), idx); | ||
| 577 | return -1; | ||
| 578 | } | ||
| 579 | |||
| 580 | if (idx == ARMV7_CYCLE_COUNTER) | ||
| 581 | val = ARMV7_CNTENC_C; | ||
| 582 | else | ||
| 583 | val = ARMV7_CNTENC_P(idx); | ||
| 584 | |||
| 585 | asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (val)); | ||
| 586 | |||
| 587 | return idx; | ||
| 588 | } | ||
| 589 | |||
| 590 | static inline u32 armv7_pmnc_enable_intens(unsigned int idx) | ||
| 591 | { | ||
| 592 | u32 val; | ||
| 593 | |||
| 594 | if ((idx != ARMV7_CYCLE_COUNTER) && | ||
| 595 | ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) { | ||
| 596 | pr_err("CPU%u enabling wrong PMNC counter" | ||
| 597 | " interrupt enable %d\n", smp_processor_id(), idx); | ||
| 598 | return -1; | ||
| 599 | } | ||
| 600 | |||
| 601 | if (idx == ARMV7_CYCLE_COUNTER) | ||
| 602 | val = ARMV7_INTENS_C; | ||
| 603 | else | ||
| 604 | val = ARMV7_INTENS_P(idx); | ||
| 605 | |||
| 606 | asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (val)); | ||
| 607 | |||
| 608 | return idx; | ||
| 609 | } | ||
| 610 | |||
| 611 | static inline u32 armv7_pmnc_disable_intens(unsigned int idx) | ||
| 612 | { | ||
| 613 | u32 val; | ||
| 614 | |||
| 615 | if ((idx != ARMV7_CYCLE_COUNTER) && | ||
| 616 | ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) { | ||
| 617 | pr_err("CPU%u disabling wrong PMNC counter" | ||
| 618 | " interrupt enable %d\n", smp_processor_id(), idx); | ||
| 619 | return -1; | ||
| 620 | } | ||
| 621 | |||
| 622 | if (idx == ARMV7_CYCLE_COUNTER) | ||
| 623 | val = ARMV7_INTENC_C; | ||
| 624 | else | ||
| 625 | val = ARMV7_INTENC_P(idx); | ||
| 626 | |||
| 627 | asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (val)); | ||
| 628 | |||
| 629 | return idx; | ||
| 630 | } | ||
| 631 | |||
| 632 | static inline u32 armv7_pmnc_getreset_flags(void) | ||
| 633 | { | ||
| 634 | u32 val; | ||
| 635 | |||
| 636 | /* Read */ | ||
| 637 | asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); | ||
| 638 | |||
| 639 | /* Write to clear flags */ | ||
| 640 | val &= ARMV7_FLAG_MASK; | ||
| 641 | asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val)); | ||
| 642 | |||
| 643 | return val; | ||
| 644 | } | ||
| 645 | |||
| 646 | #ifdef DEBUG | ||
| 647 | static void armv7_pmnc_dump_regs(void) | ||
| 648 | { | ||
| 649 | u32 val; | ||
| 650 | unsigned int cnt; | ||
| 651 | |||
| 652 | printk(KERN_INFO "PMNC registers dump:\n"); | ||
| 653 | |||
| 654 | asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val)); | ||
| 655 | printk(KERN_INFO "PMNC =0x%08x\n", val); | ||
| 656 | |||
| 657 | asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val)); | ||
| 658 | printk(KERN_INFO "CNTENS=0x%08x\n", val); | ||
| 659 | |||
| 660 | asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val)); | ||
| 661 | printk(KERN_INFO "INTENS=0x%08x\n", val); | ||
| 662 | |||
| 663 | asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); | ||
| 664 | printk(KERN_INFO "FLAGS =0x%08x\n", val); | ||
| 665 | |||
| 666 | asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val)); | ||
| 667 | printk(KERN_INFO "SELECT=0x%08x\n", val); | ||
| 668 | |||
| 669 | asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val)); | ||
| 670 | printk(KERN_INFO "CCNT =0x%08x\n", val); | ||
| 671 | |||
| 672 | for (cnt = ARMV7_COUNTER0; cnt < ARMV7_COUNTER_LAST; cnt++) { | ||
| 673 | armv7_pmnc_select_counter(cnt); | ||
| 674 | asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val)); | ||
| 675 | printk(KERN_INFO "CNT[%d] count =0x%08x\n", | ||
| 676 | cnt-ARMV7_EVENT_CNT_TO_CNTx, val); | ||
| 677 | asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val)); | ||
| 678 | printk(KERN_INFO "CNT[%d] evtsel=0x%08x\n", | ||
| 679 | cnt-ARMV7_EVENT_CNT_TO_CNTx, val); | ||
| 680 | } | ||
| 681 | } | ||
| 682 | #endif | ||
| 683 | |||
| 684 | static void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx) | ||
| 685 | { | ||
| 686 | unsigned long flags; | ||
| 687 | |||
| 688 | /* | ||
| 689 | * Enable counter and interrupt, and set the counter to count | ||
| 690 | * the event that we're interested in. | ||
| 691 | */ | ||
| 692 | raw_spin_lock_irqsave(&pmu_lock, flags); | ||
| 693 | |||
| 694 | /* | ||
| 695 | * Disable counter | ||
| 696 | */ | ||
| 697 | armv7_pmnc_disable_counter(idx); | ||
| 698 | |||
| 699 | /* | ||
| 700 | * Set event (if destined for PMNx counters) | ||
| 701 | * We don't need to set the event if it's a cycle count | ||
| 702 | */ | ||
| 703 | if (idx != ARMV7_CYCLE_COUNTER) | ||
| 704 | armv7_pmnc_write_evtsel(idx, hwc->config_base); | ||
| 705 | |||
| 706 | /* | ||
| 707 | * Enable interrupt for this counter | ||
| 708 | */ | ||
| 709 | armv7_pmnc_enable_intens(idx); | ||
| 710 | |||
| 711 | /* | ||
| 712 | * Enable counter | ||
| 713 | */ | ||
| 714 | armv7_pmnc_enable_counter(idx); | ||
| 715 | |||
| 716 | raw_spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 717 | } | ||
| 718 | |||
| 719 | static void armv7pmu_disable_event(struct hw_perf_event *hwc, int idx) | ||
| 720 | { | ||
| 721 | unsigned long flags; | ||
| 722 | |||
| 723 | /* | ||
| 724 | * Disable counter and interrupt | ||
| 725 | */ | ||
| 726 | raw_spin_lock_irqsave(&pmu_lock, flags); | ||
| 727 | |||
| 728 | /* | ||
| 729 | * Disable counter | ||
| 730 | */ | ||
| 731 | armv7_pmnc_disable_counter(idx); | ||
| 732 | |||
| 733 | /* | ||
| 734 | * Disable interrupt for this counter | ||
| 735 | */ | ||
| 736 | armv7_pmnc_disable_intens(idx); | ||
| 737 | |||
| 738 | raw_spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 739 | } | ||
| 740 | |||
| 741 | static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev) | ||
| 742 | { | ||
| 743 | unsigned long pmnc; | ||
| 744 | struct perf_sample_data data; | ||
| 745 | struct cpu_hw_events *cpuc; | ||
| 746 | struct pt_regs *regs; | ||
| 747 | int idx; | ||
| 748 | |||
| 749 | /* | ||
| 750 | * Get and reset the IRQ flags | ||
| 751 | */ | ||
| 752 | pmnc = armv7_pmnc_getreset_flags(); | ||
| 753 | |||
| 754 | /* | ||
| 755 | * Did an overflow occur? | ||
| 756 | */ | ||
| 757 | if (!armv7_pmnc_has_overflowed(pmnc)) | ||
| 758 | return IRQ_NONE; | ||
| 759 | |||
| 760 | /* | ||
| 761 | * Handle the counter(s) overflow(s) | ||
| 762 | */ | ||
| 763 | regs = get_irq_regs(); | ||
| 764 | |||
| 765 | perf_sample_data_init(&data, 0); | ||
| 766 | |||
| 767 | cpuc = &__get_cpu_var(cpu_hw_events); | ||
| 768 | for (idx = 0; idx <= armpmu->num_events; ++idx) { | ||
| 769 | struct perf_event *event = cpuc->events[idx]; | ||
| 770 | struct hw_perf_event *hwc; | ||
| 771 | |||
| 772 | if (!test_bit(idx, cpuc->active_mask)) | ||
| 773 | continue; | ||
| 774 | |||
| 775 | /* | ||
| 776 | * We have a single interrupt for all counters. Check that | ||
| 777 | * each counter has overflowed before we process it. | ||
| 778 | */ | ||
| 779 | if (!armv7_pmnc_counter_has_overflowed(pmnc, idx)) | ||
| 780 | continue; | ||
| 781 | |||
| 782 | hwc = &event->hw; | ||
| 783 | armpmu_event_update(event, hwc, idx); | ||
| 784 | data.period = event->hw.last_period; | ||
| 785 | if (!armpmu_event_set_period(event, hwc, idx)) | ||
| 786 | continue; | ||
| 787 | |||
| 788 | if (perf_event_overflow(event, 0, &data, regs)) | ||
| 789 | armpmu->disable(hwc, idx); | ||
| 790 | } | ||
| 791 | |||
| 792 | /* | ||
| 793 | * Handle the pending perf events. | ||
| 794 | * | ||
| 795 | * Note: this call *must* be run with interrupts disabled. For | ||
| 796 | * platforms that can have the PMU interrupts raised as an NMI, this | ||
| 797 | * will not work. | ||
| 798 | */ | ||
| 799 | irq_work_run(); | ||
| 800 | |||
| 801 | return IRQ_HANDLED; | ||
| 802 | } | ||
| 803 | |||
| 804 | static void armv7pmu_start(void) | ||
| 805 | { | ||
| 806 | unsigned long flags; | ||
| 807 | |||
| 808 | raw_spin_lock_irqsave(&pmu_lock, flags); | ||
| 809 | /* Enable all counters */ | ||
| 810 | armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_E); | ||
| 811 | raw_spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 812 | } | ||
| 813 | |||
| 814 | static void armv7pmu_stop(void) | ||
| 815 | { | ||
| 816 | unsigned long flags; | ||
| 817 | |||
| 818 | raw_spin_lock_irqsave(&pmu_lock, flags); | ||
| 819 | /* Disable all counters */ | ||
| 820 | armv7_pmnc_write(armv7_pmnc_read() & ~ARMV7_PMNC_E); | ||
| 821 | raw_spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 822 | } | ||
| 823 | |||
| 824 | static int armv7pmu_get_event_idx(struct cpu_hw_events *cpuc, | ||
| 825 | struct hw_perf_event *event) | ||
| 826 | { | ||
| 827 | int idx; | ||
| 828 | |||
| 829 | /* Always place a cycle counter into the cycle counter. */ | ||
| 830 | if (event->config_base == ARMV7_PERFCTR_CPU_CYCLES) { | ||
| 831 | if (test_and_set_bit(ARMV7_CYCLE_COUNTER, cpuc->used_mask)) | ||
| 832 | return -EAGAIN; | ||
| 833 | |||
| 834 | return ARMV7_CYCLE_COUNTER; | ||
| 835 | } else { | ||
| 836 | /* | ||
| 837 | * For anything other than a cycle counter, try and use | ||
| 838 | * the events counters | ||
| 839 | */ | ||
| 840 | for (idx = ARMV7_COUNTER0; idx <= armpmu->num_events; ++idx) { | ||
| 841 | if (!test_and_set_bit(idx, cpuc->used_mask)) | ||
| 842 | return idx; | ||
| 843 | } | ||
| 844 | |||
| 845 | /* The counters are all in use. */ | ||
| 846 | return -EAGAIN; | ||
| 847 | } | ||
| 848 | } | ||
| 849 | |||
| 850 | static struct arm_pmu armv7pmu = { | ||
| 851 | .handle_irq = armv7pmu_handle_irq, | ||
| 852 | .enable = armv7pmu_enable_event, | ||
| 853 | .disable = armv7pmu_disable_event, | ||
| 854 | .read_counter = armv7pmu_read_counter, | ||
| 855 | .write_counter = armv7pmu_write_counter, | ||
| 856 | .get_event_idx = armv7pmu_get_event_idx, | ||
| 857 | .start = armv7pmu_start, | ||
| 858 | .stop = armv7pmu_stop, | ||
| 859 | .raw_event_mask = 0xFF, | ||
| 860 | .max_period = (1LLU << 32) - 1, | ||
| 861 | }; | ||
| 862 | |||
| 863 | static u32 __init armv7_reset_read_pmnc(void) | ||
| 864 | { | ||
| 865 | u32 nb_cnt; | ||
| 866 | |||
| 867 | /* Initialize & Reset PMNC: C and P bits */ | ||
| 868 | armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C); | ||
| 869 | |||
| 870 | /* Read the nb of CNTx counters supported from PMNC */ | ||
| 871 | nb_cnt = (armv7_pmnc_read() >> ARMV7_PMNC_N_SHIFT) & ARMV7_PMNC_N_MASK; | ||
| 872 | |||
| 873 | /* Add the CPU cycles counter and return */ | ||
| 874 | return nb_cnt + 1; | ||
| 875 | } | ||
| 876 | |||
| 877 | static const struct arm_pmu *__init armv7_a8_pmu_init(void) | ||
| 878 | { | ||
| 879 | armv7pmu.id = ARM_PERF_PMU_ID_CA8; | ||
| 880 | armv7pmu.name = "ARMv7 Cortex-A8"; | ||
| 881 | armv7pmu.cache_map = &armv7_a8_perf_cache_map; | ||
| 882 | armv7pmu.event_map = &armv7_a8_perf_map; | ||
| 883 | armv7pmu.num_events = armv7_reset_read_pmnc(); | ||
| 884 | return &armv7pmu; | ||
| 885 | } | ||
| 886 | |||
| 887 | static const struct arm_pmu *__init armv7_a9_pmu_init(void) | ||
| 888 | { | ||
| 889 | armv7pmu.id = ARM_PERF_PMU_ID_CA9; | ||
| 890 | armv7pmu.name = "ARMv7 Cortex-A9"; | ||
| 891 | armv7pmu.cache_map = &armv7_a9_perf_cache_map; | ||
| 892 | armv7pmu.event_map = &armv7_a9_perf_map; | ||
| 893 | armv7pmu.num_events = armv7_reset_read_pmnc(); | ||
| 894 | return &armv7pmu; | ||
| 895 | } | ||
| 896 | #else | ||
| 897 | static const struct arm_pmu *__init armv7_a8_pmu_init(void) | ||
| 898 | { | ||
| 899 | return NULL; | ||
| 900 | } | ||
| 901 | |||
| 902 | static const struct arm_pmu *__init armv7_a9_pmu_init(void) | ||
| 903 | { | ||
| 904 | return NULL; | ||
| 905 | } | ||
| 906 | #endif /* CONFIG_CPU_V7 */ | ||
diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c new file mode 100644 index 000000000000..28cd3b025bc3 --- /dev/null +++ b/arch/arm/kernel/perf_event_xscale.c | |||
| @@ -0,0 +1,807 @@ | |||
| 1 | /* | ||
| 2 | * ARMv5 [xscale] Performance counter handling code. | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010, ARM Ltd., Will Deacon <will.deacon@arm.com> | ||
| 5 | * | ||
| 6 | * Based on the previous xscale OProfile code. | ||
| 7 | * | ||
| 8 | * There are two variants of the xscale PMU that we support: | ||
| 9 | * - xscale1pmu: 2 event counters and a cycle counter | ||
| 10 | * - xscale2pmu: 4 event counters and a cycle counter | ||
| 11 | * The two variants share event definitions, but have different | ||
| 12 | * PMU structures. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifdef CONFIG_CPU_XSCALE | ||
| 16 | enum xscale_perf_types { | ||
| 17 | XSCALE_PERFCTR_ICACHE_MISS = 0x00, | ||
| 18 | XSCALE_PERFCTR_ICACHE_NO_DELIVER = 0x01, | ||
| 19 | XSCALE_PERFCTR_DATA_STALL = 0x02, | ||
| 20 | XSCALE_PERFCTR_ITLB_MISS = 0x03, | ||
| 21 | XSCALE_PERFCTR_DTLB_MISS = 0x04, | ||
| 22 | XSCALE_PERFCTR_BRANCH = 0x05, | ||
| 23 | XSCALE_PERFCTR_BRANCH_MISS = 0x06, | ||
| 24 | XSCALE_PERFCTR_INSTRUCTION = 0x07, | ||
| 25 | XSCALE_PERFCTR_DCACHE_FULL_STALL = 0x08, | ||
| 26 | XSCALE_PERFCTR_DCACHE_FULL_STALL_CONTIG = 0x09, | ||
| 27 | XSCALE_PERFCTR_DCACHE_ACCESS = 0x0A, | ||
| 28 | XSCALE_PERFCTR_DCACHE_MISS = 0x0B, | ||
| 29 | XSCALE_PERFCTR_DCACHE_WRITE_BACK = 0x0C, | ||
| 30 | XSCALE_PERFCTR_PC_CHANGED = 0x0D, | ||
| 31 | XSCALE_PERFCTR_BCU_REQUEST = 0x10, | ||
| 32 | XSCALE_PERFCTR_BCU_FULL = 0x11, | ||
| 33 | XSCALE_PERFCTR_BCU_DRAIN = 0x12, | ||
| 34 | XSCALE_PERFCTR_BCU_ECC_NO_ELOG = 0x14, | ||
| 35 | XSCALE_PERFCTR_BCU_1_BIT_ERR = 0x15, | ||
| 36 | XSCALE_PERFCTR_RMW = 0x16, | ||
| 37 | /* XSCALE_PERFCTR_CCNT is not hardware defined */ | ||
| 38 | XSCALE_PERFCTR_CCNT = 0xFE, | ||
| 39 | XSCALE_PERFCTR_UNUSED = 0xFF, | ||
| 40 | }; | ||
| 41 | |||
| 42 | enum xscale_counters { | ||
| 43 | XSCALE_CYCLE_COUNTER = 1, | ||
| 44 | XSCALE_COUNTER0, | ||
| 45 | XSCALE_COUNTER1, | ||
| 46 | XSCALE_COUNTER2, | ||
| 47 | XSCALE_COUNTER3, | ||
| 48 | }; | ||
| 49 | |||
| 50 | static const unsigned xscale_perf_map[PERF_COUNT_HW_MAX] = { | ||
| 51 | [PERF_COUNT_HW_CPU_CYCLES] = XSCALE_PERFCTR_CCNT, | ||
| 52 | [PERF_COUNT_HW_INSTRUCTIONS] = XSCALE_PERFCTR_INSTRUCTION, | ||
| 53 | [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, | ||
| 54 | [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, | ||
| 55 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XSCALE_PERFCTR_BRANCH, | ||
| 56 | [PERF_COUNT_HW_BRANCH_MISSES] = XSCALE_PERFCTR_BRANCH_MISS, | ||
| 57 | [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED, | ||
| 58 | }; | ||
| 59 | |||
| 60 | static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | ||
| 61 | [PERF_COUNT_HW_CACHE_OP_MAX] | ||
| 62 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { | ||
| 63 | [C(L1D)] = { | ||
| 64 | [C(OP_READ)] = { | ||
| 65 | [C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS, | ||
| 66 | [C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS, | ||
| 67 | }, | ||
| 68 | [C(OP_WRITE)] = { | ||
| 69 | [C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS, | ||
| 70 | [C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS, | ||
| 71 | }, | ||
| 72 | [C(OP_PREFETCH)] = { | ||
| 73 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 74 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 75 | }, | ||
| 76 | }, | ||
| 77 | [C(L1I)] = { | ||
| 78 | [C(OP_READ)] = { | ||
| 79 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 80 | [C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS, | ||
| 81 | }, | ||
| 82 | [C(OP_WRITE)] = { | ||
| 83 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 84 | [C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS, | ||
| 85 | }, | ||
| 86 | [C(OP_PREFETCH)] = { | ||
| 87 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 88 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 89 | }, | ||
| 90 | }, | ||
| 91 | [C(LL)] = { | ||
| 92 | [C(OP_READ)] = { | ||
| 93 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 94 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 95 | }, | ||
| 96 | [C(OP_WRITE)] = { | ||
| 97 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 98 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 99 | }, | ||
| 100 | [C(OP_PREFETCH)] = { | ||
| 101 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 102 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 103 | }, | ||
| 104 | }, | ||
| 105 | [C(DTLB)] = { | ||
| 106 | [C(OP_READ)] = { | ||
| 107 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 108 | [C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS, | ||
| 109 | }, | ||
| 110 | [C(OP_WRITE)] = { | ||
| 111 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 112 | [C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS, | ||
| 113 | }, | ||
| 114 | [C(OP_PREFETCH)] = { | ||
| 115 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 116 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 117 | }, | ||
| 118 | }, | ||
| 119 | [C(ITLB)] = { | ||
| 120 | [C(OP_READ)] = { | ||
| 121 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 122 | [C(RESULT_MISS)] = XSCALE_PERFCTR_ITLB_MISS, | ||
| 123 | }, | ||
| 124 | [C(OP_WRITE)] = { | ||
| 125 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 126 | [C(RESULT_MISS)] = XSCALE_PERFCTR_ITLB_MISS, | ||
| 127 | }, | ||
| 128 | [C(OP_PREFETCH)] = { | ||
| 129 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 130 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 131 | }, | ||
| 132 | }, | ||
| 133 | [C(BPU)] = { | ||
| 134 | [C(OP_READ)] = { | ||
| 135 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 136 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 137 | }, | ||
| 138 | [C(OP_WRITE)] = { | ||
| 139 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 140 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 141 | }, | ||
| 142 | [C(OP_PREFETCH)] = { | ||
| 143 | [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, | ||
| 144 | [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, | ||
| 145 | }, | ||
| 146 | }, | ||
| 147 | }; | ||
| 148 | |||
| 149 | #define XSCALE_PMU_ENABLE 0x001 | ||
| 150 | #define XSCALE_PMN_RESET 0x002 | ||
| 151 | #define XSCALE_CCNT_RESET 0x004 | ||
| 152 | #define XSCALE_PMU_RESET (CCNT_RESET | PMN_RESET) | ||
| 153 | #define XSCALE_PMU_CNT64 0x008 | ||
| 154 | |||
| 155 | #define XSCALE1_OVERFLOWED_MASK 0x700 | ||
| 156 | #define XSCALE1_CCOUNT_OVERFLOW 0x400 | ||
| 157 | #define XSCALE1_COUNT0_OVERFLOW 0x100 | ||
| 158 | #define XSCALE1_COUNT1_OVERFLOW 0x200 | ||
| 159 | #define XSCALE1_CCOUNT_INT_EN 0x040 | ||
| 160 | #define XSCALE1_COUNT0_INT_EN 0x010 | ||
| 161 | #define XSCALE1_COUNT1_INT_EN 0x020 | ||
| 162 | #define XSCALE1_COUNT0_EVT_SHFT 12 | ||
| 163 | #define XSCALE1_COUNT0_EVT_MASK (0xff << XSCALE1_COUNT0_EVT_SHFT) | ||
| 164 | #define XSCALE1_COUNT1_EVT_SHFT 20 | ||
| 165 | #define XSCALE1_COUNT1_EVT_MASK (0xff << XSCALE1_COUNT1_EVT_SHFT) | ||
| 166 | |||
| 167 | static inline u32 | ||
| 168 | xscale1pmu_read_pmnc(void) | ||
| 169 | { | ||
| 170 | u32 val; | ||
| 171 | asm volatile("mrc p14, 0, %0, c0, c0, 0" : "=r" (val)); | ||
| 172 | return val; | ||
| 173 | } | ||
| 174 | |||
| 175 | static inline void | ||
| 176 | xscale1pmu_write_pmnc(u32 val) | ||
| 177 | { | ||
| 178 | /* upper 4bits and 7, 11 are write-as-0 */ | ||
| 179 | val &= 0xffff77f; | ||
| 180 | asm volatile("mcr p14, 0, %0, c0, c0, 0" : : "r" (val)); | ||
| 181 | } | ||
| 182 | |||
| 183 | static inline int | ||
| 184 | xscale1_pmnc_counter_has_overflowed(unsigned long pmnc, | ||
| 185 | enum xscale_counters counter) | ||
| 186 | { | ||
| 187 | int ret = 0; | ||
| 188 | |||
| 189 | switch (counter) { | ||
| 190 | case XSCALE_CYCLE_COUNTER: | ||
| 191 | ret = pmnc & XSCALE1_CCOUNT_OVERFLOW; | ||
| 192 | break; | ||
| 193 | case XSCALE_COUNTER0: | ||
| 194 | ret = pmnc & XSCALE1_COUNT0_OVERFLOW; | ||
| 195 | break; | ||
| 196 | case XSCALE_COUNTER1: | ||
| 197 | ret = pmnc & XSCALE1_COUNT1_OVERFLOW; | ||
| 198 | break; | ||
| 199 | default: | ||
| 200 | WARN_ONCE(1, "invalid counter number (%d)\n", counter); | ||
| 201 | } | ||
| 202 | |||
| 203 | return ret; | ||
| 204 | } | ||
| 205 | |||
| 206 | static irqreturn_t | ||
| 207 | xscale1pmu_handle_irq(int irq_num, void *dev) | ||
| 208 | { | ||
| 209 | unsigned long pmnc; | ||
| 210 | struct perf_sample_data data; | ||
| 211 | struct cpu_hw_events *cpuc; | ||
| 212 | struct pt_regs *regs; | ||
| 213 | int idx; | ||
| 214 | |||
| 215 | /* | ||
| 216 | * NOTE: there's an A stepping erratum that states if an overflow | ||
| 217 | * bit already exists and another occurs, the previous | ||
| 218 | * Overflow bit gets cleared. There's no workaround. | ||
| 219 | * Fixed in B stepping or later. | ||
| 220 | */ | ||
| 221 | pmnc = xscale1pmu_read_pmnc(); | ||
| 222 | |||
| 223 | /* | ||
| 224 | * Write the value back to clear the overflow flags. Overflow | ||
| 225 | * flags remain in pmnc for use below. We also disable the PMU | ||
| 226 | * while we process the interrupt. | ||
| 227 | */ | ||
| 228 | xscale1pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE); | ||
| 229 | |||
| 230 | if (!(pmnc & XSCALE1_OVERFLOWED_MASK)) | ||
| 231 | return IRQ_NONE; | ||
| 232 | |||
| 233 | regs = get_irq_regs(); | ||
| 234 | |||
| 235 | perf_sample_data_init(&data, 0); | ||
| 236 | |||
| 237 | cpuc = &__get_cpu_var(cpu_hw_events); | ||
| 238 | for (idx = 0; idx <= armpmu->num_events; ++idx) { | ||
| 239 | struct perf_event *event = cpuc->events[idx]; | ||
| 240 | struct hw_perf_event *hwc; | ||
| 241 | |||
| 242 | if (!test_bit(idx, cpuc->active_mask)) | ||
| 243 | continue; | ||
| 244 | |||
| 245 | if (!xscale1_pmnc_counter_has_overflowed(pmnc, idx)) | ||
| 246 | continue; | ||
| 247 | |||
| 248 | hwc = &event->hw; | ||
| 249 | armpmu_event_update(event, hwc, idx); | ||
| 250 | data.period = event->hw.last_period; | ||
| 251 | if (!armpmu_event_set_period(event, hwc, idx)) | ||
| 252 | continue; | ||
| 253 | |||
| 254 | if (perf_event_overflow(event, 0, &data, regs)) | ||
| 255 | armpmu->disable(hwc, idx); | ||
| 256 | } | ||
| 257 | |||
| 258 | irq_work_run(); | ||
| 259 | |||
| 260 | /* | ||
| 261 | * Re-enable the PMU. | ||
| 262 | */ | ||
| 263 | pmnc = xscale1pmu_read_pmnc() | XSCALE_PMU_ENABLE; | ||
| 264 | xscale1pmu_write_pmnc(pmnc); | ||
| 265 | |||
| 266 | return IRQ_HANDLED; | ||
| 267 | } | ||
| 268 | |||
| 269 | static void | ||
| 270 | xscale1pmu_enable_event(struct hw_perf_event *hwc, int idx) | ||
| 271 | { | ||
| 272 | unsigned long val, mask, evt, flags; | ||
| 273 | |||
| 274 | switch (idx) { | ||
| 275 | case XSCALE_CYCLE_COUNTER: | ||
| 276 | mask = 0; | ||
| 277 | evt = XSCALE1_CCOUNT_INT_EN; | ||
| 278 | break; | ||
| 279 | case XSCALE_COUNTER0: | ||
| 280 | mask = XSCALE1_COUNT0_EVT_MASK; | ||
| 281 | evt = (hwc->config_base << XSCALE1_COUNT0_EVT_SHFT) | | ||
| 282 | XSCALE1_COUNT0_INT_EN; | ||
| 283 | break; | ||
| 284 | case XSCALE_COUNTER1: | ||
| 285 | mask = XSCALE1_COUNT1_EVT_MASK; | ||
| 286 | evt = (hwc->config_base << XSCALE1_COUNT1_EVT_SHFT) | | ||
| 287 | XSCALE1_COUNT1_INT_EN; | ||
| 288 | break; | ||
| 289 | default: | ||
| 290 | WARN_ONCE(1, "invalid counter number (%d)\n", idx); | ||
| 291 | return; | ||
| 292 | } | ||
| 293 | |||
| 294 | raw_spin_lock_irqsave(&pmu_lock, flags); | ||
| 295 | val = xscale1pmu_read_pmnc(); | ||
| 296 | val &= ~mask; | ||
| 297 | val |= evt; | ||
| 298 | xscale1pmu_write_pmnc(val); | ||
| 299 | raw_spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 300 | } | ||
| 301 | |||
| 302 | static void | ||
| 303 | xscale1pmu_disable_event(struct hw_perf_event *hwc, int idx) | ||
| 304 | { | ||
| 305 | unsigned long val, mask, evt, flags; | ||
| 306 | |||
| 307 | switch (idx) { | ||
| 308 | case XSCALE_CYCLE_COUNTER: | ||
| 309 | mask = XSCALE1_CCOUNT_INT_EN; | ||
| 310 | evt = 0; | ||
| 311 | break; | ||
| 312 | case XSCALE_COUNTER0: | ||
| 313 | mask = XSCALE1_COUNT0_INT_EN | XSCALE1_COUNT0_EVT_MASK; | ||
| 314 | evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT0_EVT_SHFT; | ||
| 315 | break; | ||
| 316 | case XSCALE_COUNTER1: | ||
| 317 | mask = XSCALE1_COUNT1_INT_EN | XSCALE1_COUNT1_EVT_MASK; | ||
| 318 | evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT1_EVT_SHFT; | ||
| 319 | break; | ||
| 320 | default: | ||
| 321 | WARN_ONCE(1, "invalid counter number (%d)\n", idx); | ||
| 322 | return; | ||
| 323 | } | ||
| 324 | |||
| 325 | raw_spin_lock_irqsave(&pmu_lock, flags); | ||
| 326 | val = xscale1pmu_read_pmnc(); | ||
| 327 | val &= ~mask; | ||
| 328 | val |= evt; | ||
| 329 | xscale1pmu_write_pmnc(val); | ||
| 330 | raw_spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 331 | } | ||
| 332 | |||
| 333 | static int | ||
| 334 | xscale1pmu_get_event_idx(struct cpu_hw_events *cpuc, | ||
| 335 | struct hw_perf_event *event) | ||
| 336 | { | ||
| 337 | if (XSCALE_PERFCTR_CCNT == event->config_base) { | ||
| 338 | if (test_and_set_bit(XSCALE_CYCLE_COUNTER, cpuc->used_mask)) | ||
| 339 | return -EAGAIN; | ||
| 340 | |||
| 341 | return XSCALE_CYCLE_COUNTER; | ||
| 342 | } else { | ||
| 343 | if (!test_and_set_bit(XSCALE_COUNTER1, cpuc->used_mask)) | ||
| 344 | return XSCALE_COUNTER1; | ||
| 345 | |||
| 346 | if (!test_and_set_bit(XSCALE_COUNTER0, cpuc->used_mask)) | ||
| 347 | return XSCALE_COUNTER0; | ||
| 348 | |||
| 349 | return -EAGAIN; | ||
| 350 | } | ||
| 351 | } | ||
| 352 | |||
| 353 | static void | ||
| 354 | xscale1pmu_start(void) | ||
| 355 | { | ||
| 356 | unsigned long flags, val; | ||
| 357 | |||
| 358 | raw_spin_lock_irqsave(&pmu_lock, flags); | ||
| 359 | val = xscale1pmu_read_pmnc(); | ||
| 360 | val |= XSCALE_PMU_ENABLE; | ||
| 361 | xscale1pmu_write_pmnc(val); | ||
| 362 | raw_spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 363 | } | ||
| 364 | |||
| 365 | static void | ||
| 366 | xscale1pmu_stop(void) | ||
| 367 | { | ||
| 368 | unsigned long flags, val; | ||
| 369 | |||
| 370 | raw_spin_lock_irqsave(&pmu_lock, flags); | ||
| 371 | val = xscale1pmu_read_pmnc(); | ||
| 372 | val &= ~XSCALE_PMU_ENABLE; | ||
| 373 | xscale1pmu_write_pmnc(val); | ||
| 374 | raw_spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 375 | } | ||
| 376 | |||
| 377 | static inline u32 | ||
| 378 | xscale1pmu_read_counter(int counter) | ||
| 379 | { | ||
| 380 | u32 val = 0; | ||
| 381 | |||
| 382 | switch (counter) { | ||
| 383 | case XSCALE_CYCLE_COUNTER: | ||
| 384 | asm volatile("mrc p14, 0, %0, c1, c0, 0" : "=r" (val)); | ||
| 385 | break; | ||
| 386 | case XSCALE_COUNTER0: | ||
| 387 | asm volatile("mrc p14, 0, %0, c2, c0, 0" : "=r" (val)); | ||
| 388 | break; | ||
| 389 | case XSCALE_COUNTER1: | ||
| 390 | asm volatile("mrc p14, 0, %0, c3, c0, 0" : "=r" (val)); | ||
| 391 | break; | ||
| 392 | } | ||
| 393 | |||
| 394 | return val; | ||
| 395 | } | ||
| 396 | |||
| 397 | static inline void | ||
| 398 | xscale1pmu_write_counter(int counter, u32 val) | ||
| 399 | { | ||
| 400 | switch (counter) { | ||
| 401 | case XSCALE_CYCLE_COUNTER: | ||
| 402 | asm volatile("mcr p14, 0, %0, c1, c0, 0" : : "r" (val)); | ||
| 403 | break; | ||
| 404 | case XSCALE_COUNTER0: | ||
| 405 | asm volatile("mcr p14, 0, %0, c2, c0, 0" : : "r" (val)); | ||
| 406 | break; | ||
| 407 | case XSCALE_COUNTER1: | ||
| 408 | asm volatile("mcr p14, 0, %0, c3, c0, 0" : : "r" (val)); | ||
| 409 | break; | ||
| 410 | } | ||
| 411 | } | ||
| 412 | |||
| 413 | static const struct arm_pmu xscale1pmu = { | ||
| 414 | .id = ARM_PERF_PMU_ID_XSCALE1, | ||
| 415 | .name = "xscale1", | ||
| 416 | .handle_irq = xscale1pmu_handle_irq, | ||
| 417 | .enable = xscale1pmu_enable_event, | ||
| 418 | .disable = xscale1pmu_disable_event, | ||
| 419 | .read_counter = xscale1pmu_read_counter, | ||
| 420 | .write_counter = xscale1pmu_write_counter, | ||
| 421 | .get_event_idx = xscale1pmu_get_event_idx, | ||
| 422 | .start = xscale1pmu_start, | ||
| 423 | .stop = xscale1pmu_stop, | ||
| 424 | .cache_map = &xscale_perf_cache_map, | ||
| 425 | .event_map = &xscale_perf_map, | ||
| 426 | .raw_event_mask = 0xFF, | ||
| 427 | .num_events = 3, | ||
| 428 | .max_period = (1LLU << 32) - 1, | ||
| 429 | }; | ||
| 430 | |||
| 431 | static const struct arm_pmu *__init xscale1pmu_init(void) | ||
| 432 | { | ||
| 433 | return &xscale1pmu; | ||
| 434 | } | ||
| 435 | |||
| 436 | #define XSCALE2_OVERFLOWED_MASK 0x01f | ||
| 437 | #define XSCALE2_CCOUNT_OVERFLOW 0x001 | ||
| 438 | #define XSCALE2_COUNT0_OVERFLOW 0x002 | ||
| 439 | #define XSCALE2_COUNT1_OVERFLOW 0x004 | ||
| 440 | #define XSCALE2_COUNT2_OVERFLOW 0x008 | ||
| 441 | #define XSCALE2_COUNT3_OVERFLOW 0x010 | ||
| 442 | #define XSCALE2_CCOUNT_INT_EN 0x001 | ||
| 443 | #define XSCALE2_COUNT0_INT_EN 0x002 | ||
| 444 | #define XSCALE2_COUNT1_INT_EN 0x004 | ||
| 445 | #define XSCALE2_COUNT2_INT_EN 0x008 | ||
| 446 | #define XSCALE2_COUNT3_INT_EN 0x010 | ||
| 447 | #define XSCALE2_COUNT0_EVT_SHFT 0 | ||
| 448 | #define XSCALE2_COUNT0_EVT_MASK (0xff << XSCALE2_COUNT0_EVT_SHFT) | ||
| 449 | #define XSCALE2_COUNT1_EVT_SHFT 8 | ||
| 450 | #define XSCALE2_COUNT1_EVT_MASK (0xff << XSCALE2_COUNT1_EVT_SHFT) | ||
| 451 | #define XSCALE2_COUNT2_EVT_SHFT 16 | ||
| 452 | #define XSCALE2_COUNT2_EVT_MASK (0xff << XSCALE2_COUNT2_EVT_SHFT) | ||
| 453 | #define XSCALE2_COUNT3_EVT_SHFT 24 | ||
| 454 | #define XSCALE2_COUNT3_EVT_MASK (0xff << XSCALE2_COUNT3_EVT_SHFT) | ||
| 455 | |||
| 456 | static inline u32 | ||
| 457 | xscale2pmu_read_pmnc(void) | ||
| 458 | { | ||
| 459 | u32 val; | ||
| 460 | asm volatile("mrc p14, 0, %0, c0, c1, 0" : "=r" (val)); | ||
| 461 | /* bits 1-2 and 4-23 are read-unpredictable */ | ||
| 462 | return val & 0xff000009; | ||
| 463 | } | ||
| 464 | |||
| 465 | static inline void | ||
| 466 | xscale2pmu_write_pmnc(u32 val) | ||
| 467 | { | ||
| 468 | /* bits 4-23 are write-as-0, 24-31 are write ignored */ | ||
| 469 | val &= 0xf; | ||
| 470 | asm volatile("mcr p14, 0, %0, c0, c1, 0" : : "r" (val)); | ||
| 471 | } | ||
| 472 | |||
| 473 | static inline u32 | ||
| 474 | xscale2pmu_read_overflow_flags(void) | ||
| 475 | { | ||
| 476 | u32 val; | ||
| 477 | asm volatile("mrc p14, 0, %0, c5, c1, 0" : "=r" (val)); | ||
| 478 | return val; | ||
| 479 | } | ||
| 480 | |||
| 481 | static inline void | ||
| 482 | xscale2pmu_write_overflow_flags(u32 val) | ||
| 483 | { | ||
| 484 | asm volatile("mcr p14, 0, %0, c5, c1, 0" : : "r" (val)); | ||
| 485 | } | ||
| 486 | |||
| 487 | static inline u32 | ||
| 488 | xscale2pmu_read_event_select(void) | ||
| 489 | { | ||
| 490 | u32 val; | ||
| 491 | asm volatile("mrc p14, 0, %0, c8, c1, 0" : "=r" (val)); | ||
| 492 | return val; | ||
| 493 | } | ||
| 494 | |||
| 495 | static inline void | ||
| 496 | xscale2pmu_write_event_select(u32 val) | ||
| 497 | { | ||
| 498 | asm volatile("mcr p14, 0, %0, c8, c1, 0" : : "r"(val)); | ||
| 499 | } | ||
| 500 | |||
| 501 | static inline u32 | ||
| 502 | xscale2pmu_read_int_enable(void) | ||
| 503 | { | ||
| 504 | u32 val; | ||
| 505 | asm volatile("mrc p14, 0, %0, c4, c1, 0" : "=r" (val)); | ||
| 506 | return val; | ||
| 507 | } | ||
| 508 | |||
| 509 | static void | ||
| 510 | xscale2pmu_write_int_enable(u32 val) | ||
| 511 | { | ||
| 512 | asm volatile("mcr p14, 0, %0, c4, c1, 0" : : "r" (val)); | ||
| 513 | } | ||
| 514 | |||
| 515 | static inline int | ||
| 516 | xscale2_pmnc_counter_has_overflowed(unsigned long of_flags, | ||
| 517 | enum xscale_counters counter) | ||
| 518 | { | ||
| 519 | int ret = 0; | ||
| 520 | |||
| 521 | switch (counter) { | ||
| 522 | case XSCALE_CYCLE_COUNTER: | ||
| 523 | ret = of_flags & XSCALE2_CCOUNT_OVERFLOW; | ||
| 524 | break; | ||
| 525 | case XSCALE_COUNTER0: | ||
| 526 | ret = of_flags & XSCALE2_COUNT0_OVERFLOW; | ||
| 527 | break; | ||
| 528 | case XSCALE_COUNTER1: | ||
| 529 | ret = of_flags & XSCALE2_COUNT1_OVERFLOW; | ||
| 530 | break; | ||
| 531 | case XSCALE_COUNTER2: | ||
| 532 | ret = of_flags & XSCALE2_COUNT2_OVERFLOW; | ||
| 533 | break; | ||
| 534 | case XSCALE_COUNTER3: | ||
| 535 | ret = of_flags & XSCALE2_COUNT3_OVERFLOW; | ||
| 536 | break; | ||
| 537 | default: | ||
| 538 | WARN_ONCE(1, "invalid counter number (%d)\n", counter); | ||
| 539 | } | ||
| 540 | |||
| 541 | return ret; | ||
| 542 | } | ||
| 543 | |||
| 544 | static irqreturn_t | ||
| 545 | xscale2pmu_handle_irq(int irq_num, void *dev) | ||
| 546 | { | ||
| 547 | unsigned long pmnc, of_flags; | ||
| 548 | struct perf_sample_data data; | ||
| 549 | struct cpu_hw_events *cpuc; | ||
| 550 | struct pt_regs *regs; | ||
| 551 | int idx; | ||
| 552 | |||
| 553 | /* Disable the PMU. */ | ||
| 554 | pmnc = xscale2pmu_read_pmnc(); | ||
| 555 | xscale2pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE); | ||
| 556 | |||
| 557 | /* Check the overflow flag register. */ | ||
| 558 | of_flags = xscale2pmu_read_overflow_flags(); | ||
| 559 | if (!(of_flags & XSCALE2_OVERFLOWED_MASK)) | ||
| 560 | return IRQ_NONE; | ||
| 561 | |||
| 562 | /* Clear the overflow bits. */ | ||
| 563 | xscale2pmu_write_overflow_flags(of_flags); | ||
| 564 | |||
| 565 | regs = get_irq_regs(); | ||
| 566 | |||
| 567 | perf_sample_data_init(&data, 0); | ||
| 568 | |||
| 569 | cpuc = &__get_cpu_var(cpu_hw_events); | ||
| 570 | for (idx = 0; idx <= armpmu->num_events; ++idx) { | ||
| 571 | struct perf_event *event = cpuc->events[idx]; | ||
| 572 | struct hw_perf_event *hwc; | ||
| 573 | |||
| 574 | if (!test_bit(idx, cpuc->active_mask)) | ||
| 575 | continue; | ||
| 576 | |||
| 577 | if (!xscale2_pmnc_counter_has_overflowed(pmnc, idx)) | ||
| 578 | continue; | ||
| 579 | |||
| 580 | hwc = &event->hw; | ||
| 581 | armpmu_event_update(event, hwc, idx); | ||
| 582 | data.period = event->hw.last_period; | ||
| 583 | if (!armpmu_event_set_period(event, hwc, idx)) | ||
| 584 | continue; | ||
| 585 | |||
| 586 | if (perf_event_overflow(event, 0, &data, regs)) | ||
| 587 | armpmu->disable(hwc, idx); | ||
| 588 | } | ||
| 589 | |||
| 590 | irq_work_run(); | ||
| 591 | |||
| 592 | /* | ||
| 593 | * Re-enable the PMU. | ||
| 594 | */ | ||
| 595 | pmnc = xscale2pmu_read_pmnc() | XSCALE_PMU_ENABLE; | ||
| 596 | xscale2pmu_write_pmnc(pmnc); | ||
| 597 | |||
| 598 | return IRQ_HANDLED; | ||
| 599 | } | ||
| 600 | |||
| 601 | static void | ||
| 602 | xscale2pmu_enable_event(struct hw_perf_event *hwc, int idx) | ||
| 603 | { | ||
| 604 | unsigned long flags, ien, evtsel; | ||
| 605 | |||
| 606 | ien = xscale2pmu_read_int_enable(); | ||
| 607 | evtsel = xscale2pmu_read_event_select(); | ||
| 608 | |||
| 609 | switch (idx) { | ||
| 610 | case XSCALE_CYCLE_COUNTER: | ||
| 611 | ien |= XSCALE2_CCOUNT_INT_EN; | ||
| 612 | break; | ||
| 613 | case XSCALE_COUNTER0: | ||
| 614 | ien |= XSCALE2_COUNT0_INT_EN; | ||
| 615 | evtsel &= ~XSCALE2_COUNT0_EVT_MASK; | ||
| 616 | evtsel |= hwc->config_base << XSCALE2_COUNT0_EVT_SHFT; | ||
| 617 | break; | ||
| 618 | case XSCALE_COUNTER1: | ||
| 619 | ien |= XSCALE2_COUNT1_INT_EN; | ||
| 620 | evtsel &= ~XSCALE2_COUNT1_EVT_MASK; | ||
| 621 | evtsel |= hwc->config_base << XSCALE2_COUNT1_EVT_SHFT; | ||
| 622 | break; | ||
| 623 | case XSCALE_COUNTER2: | ||
| 624 | ien |= XSCALE2_COUNT2_INT_EN; | ||
| 625 | evtsel &= ~XSCALE2_COUNT2_EVT_MASK; | ||
| 626 | evtsel |= hwc->config_base << XSCALE2_COUNT2_EVT_SHFT; | ||
| 627 | break; | ||
| 628 | case XSCALE_COUNTER3: | ||
| 629 | ien |= XSCALE2_COUNT3_INT_EN; | ||
| 630 | evtsel &= ~XSCALE2_COUNT3_EVT_MASK; | ||
| 631 | evtsel |= hwc->config_base << XSCALE2_COUNT3_EVT_SHFT; | ||
| 632 | break; | ||
| 633 | default: | ||
| 634 | WARN_ONCE(1, "invalid counter number (%d)\n", idx); | ||
| 635 | return; | ||
| 636 | } | ||
| 637 | |||
| 638 | raw_spin_lock_irqsave(&pmu_lock, flags); | ||
| 639 | xscale2pmu_write_event_select(evtsel); | ||
| 640 | xscale2pmu_write_int_enable(ien); | ||
| 641 | raw_spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 642 | } | ||
| 643 | |||
| 644 | static void | ||
| 645 | xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx) | ||
| 646 | { | ||
| 647 | unsigned long flags, ien, evtsel; | ||
| 648 | |||
| 649 | ien = xscale2pmu_read_int_enable(); | ||
| 650 | evtsel = xscale2pmu_read_event_select(); | ||
| 651 | |||
| 652 | switch (idx) { | ||
| 653 | case XSCALE_CYCLE_COUNTER: | ||
| 654 | ien &= ~XSCALE2_CCOUNT_INT_EN; | ||
| 655 | break; | ||
| 656 | case XSCALE_COUNTER0: | ||
| 657 | ien &= ~XSCALE2_COUNT0_INT_EN; | ||
| 658 | evtsel &= ~XSCALE2_COUNT0_EVT_MASK; | ||
| 659 | evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT0_EVT_SHFT; | ||
| 660 | break; | ||
| 661 | case XSCALE_COUNTER1: | ||
| 662 | ien &= ~XSCALE2_COUNT1_INT_EN; | ||
| 663 | evtsel &= ~XSCALE2_COUNT1_EVT_MASK; | ||
| 664 | evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT1_EVT_SHFT; | ||
| 665 | break; | ||
| 666 | case XSCALE_COUNTER2: | ||
| 667 | ien &= ~XSCALE2_COUNT2_INT_EN; | ||
| 668 | evtsel &= ~XSCALE2_COUNT2_EVT_MASK; | ||
| 669 | evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT2_EVT_SHFT; | ||
| 670 | break; | ||
| 671 | case XSCALE_COUNTER3: | ||
| 672 | ien &= ~XSCALE2_COUNT3_INT_EN; | ||
| 673 | evtsel &= ~XSCALE2_COUNT3_EVT_MASK; | ||
| 674 | evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT3_EVT_SHFT; | ||
| 675 | break; | ||
| 676 | default: | ||
| 677 | WARN_ONCE(1, "invalid counter number (%d)\n", idx); | ||
| 678 | return; | ||
| 679 | } | ||
| 680 | |||
| 681 | raw_spin_lock_irqsave(&pmu_lock, flags); | ||
| 682 | xscale2pmu_write_event_select(evtsel); | ||
| 683 | xscale2pmu_write_int_enable(ien); | ||
| 684 | raw_spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 685 | } | ||
| 686 | |||
| 687 | static int | ||
| 688 | xscale2pmu_get_event_idx(struct cpu_hw_events *cpuc, | ||
| 689 | struct hw_perf_event *event) | ||
| 690 | { | ||
| 691 | int idx = xscale1pmu_get_event_idx(cpuc, event); | ||
| 692 | if (idx >= 0) | ||
| 693 | goto out; | ||
| 694 | |||
| 695 | if (!test_and_set_bit(XSCALE_COUNTER3, cpuc->used_mask)) | ||
| 696 | idx = XSCALE_COUNTER3; | ||
| 697 | else if (!test_and_set_bit(XSCALE_COUNTER2, cpuc->used_mask)) | ||
| 698 | idx = XSCALE_COUNTER2; | ||
| 699 | out: | ||
| 700 | return idx; | ||
| 701 | } | ||
| 702 | |||
| 703 | static void | ||
| 704 | xscale2pmu_start(void) | ||
| 705 | { | ||
| 706 | unsigned long flags, val; | ||
| 707 | |||
| 708 | raw_spin_lock_irqsave(&pmu_lock, flags); | ||
| 709 | val = xscale2pmu_read_pmnc() & ~XSCALE_PMU_CNT64; | ||
| 710 | val |= XSCALE_PMU_ENABLE; | ||
| 711 | xscale2pmu_write_pmnc(val); | ||
| 712 | raw_spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 713 | } | ||
| 714 | |||
| 715 | static void | ||
| 716 | xscale2pmu_stop(void) | ||
| 717 | { | ||
| 718 | unsigned long flags, val; | ||
| 719 | |||
| 720 | raw_spin_lock_irqsave(&pmu_lock, flags); | ||
| 721 | val = xscale2pmu_read_pmnc(); | ||
| 722 | val &= ~XSCALE_PMU_ENABLE; | ||
| 723 | xscale2pmu_write_pmnc(val); | ||
| 724 | raw_spin_unlock_irqrestore(&pmu_lock, flags); | ||
| 725 | } | ||
| 726 | |||
| 727 | static inline u32 | ||
| 728 | xscale2pmu_read_counter(int counter) | ||
| 729 | { | ||
| 730 | u32 val = 0; | ||
| 731 | |||
| 732 | switch (counter) { | ||
| 733 | case XSCALE_CYCLE_COUNTER: | ||
| 734 | asm volatile("mrc p14, 0, %0, c1, c1, 0" : "=r" (val)); | ||
| 735 | break; | ||
| 736 | case XSCALE_COUNTER0: | ||
| 737 | asm volatile("mrc p14, 0, %0, c0, c2, 0" : "=r" (val)); | ||
| 738 | break; | ||
| 739 | case XSCALE_COUNTER1: | ||
| 740 | asm volatile("mrc p14, 0, %0, c1, c2, 0" : "=r" (val)); | ||
| 741 | break; | ||
| 742 | case XSCALE_COUNTER2: | ||
| 743 | asm volatile("mrc p14, 0, %0, c2, c2, 0" : "=r" (val)); | ||
| 744 | break; | ||
| 745 | case XSCALE_COUNTER3: | ||
| 746 | asm volatile("mrc p14, 0, %0, c3, c2, 0" : "=r" (val)); | ||
| 747 | break; | ||
| 748 | } | ||
| 749 | |||
| 750 | return val; | ||
| 751 | } | ||
| 752 | |||
| 753 | static inline void | ||
| 754 | xscale2pmu_write_counter(int counter, u32 val) | ||
| 755 | { | ||
| 756 | switch (counter) { | ||
| 757 | case XSCALE_CYCLE_COUNTER: | ||
| 758 | asm volatile("mcr p14, 0, %0, c1, c1, 0" : : "r" (val)); | ||
| 759 | break; | ||
| 760 | case XSCALE_COUNTER0: | ||
| 761 | asm volatile("mcr p14, 0, %0, c0, c2, 0" : : "r" (val)); | ||
| 762 | break; | ||
| 763 | case XSCALE_COUNTER1: | ||
| 764 | asm volatile("mcr p14, 0, %0, c1, c2, 0" : : "r" (val)); | ||
| 765 | break; | ||
| 766 | case XSCALE_COUNTER2: | ||
| 767 | asm volatile("mcr p14, 0, %0, c2, c2, 0" : : "r" (val)); | ||
| 768 | break; | ||
| 769 | case XSCALE_COUNTER3: | ||
| 770 | asm volatile("mcr p14, 0, %0, c3, c2, 0" : : "r" (val)); | ||
| 771 | break; | ||
| 772 | } | ||
| 773 | } | ||
| 774 | |||
| 775 | static const struct arm_pmu xscale2pmu = { | ||
| 776 | .id = ARM_PERF_PMU_ID_XSCALE2, | ||
| 777 | .name = "xscale2", | ||
| 778 | .handle_irq = xscale2pmu_handle_irq, | ||
| 779 | .enable = xscale2pmu_enable_event, | ||
| 780 | .disable = xscale2pmu_disable_event, | ||
| 781 | .read_counter = xscale2pmu_read_counter, | ||
| 782 | .write_counter = xscale2pmu_write_counter, | ||
| 783 | .get_event_idx = xscale2pmu_get_event_idx, | ||
| 784 | .start = xscale2pmu_start, | ||
| 785 | .stop = xscale2pmu_stop, | ||
| 786 | .cache_map = &xscale_perf_cache_map, | ||
| 787 | .event_map = &xscale_perf_map, | ||
| 788 | .raw_event_mask = 0xFF, | ||
| 789 | .num_events = 5, | ||
| 790 | .max_period = (1LLU << 32) - 1, | ||
| 791 | }; | ||
| 792 | |||
| 793 | static const struct arm_pmu *__init xscale2pmu_init(void) | ||
| 794 | { | ||
| 795 | return &xscale2pmu; | ||
| 796 | } | ||
| 797 | #else | ||
| 798 | static const struct arm_pmu *__init xscale1pmu_init(void) | ||
| 799 | { | ||
| 800 | return NULL; | ||
| 801 | } | ||
| 802 | |||
| 803 | static const struct arm_pmu *__init xscale2pmu_init(void) | ||
| 804 | { | ||
| 805 | return NULL; | ||
| 806 | } | ||
| 807 | #endif /* CONFIG_CPU_XSCALE */ | ||
diff --git a/arch/arm/kernel/pj4-cp0.c b/arch/arm/kernel/pj4-cp0.c new file mode 100644 index 000000000000..a4b1b0748fd3 --- /dev/null +++ b/arch/arm/kernel/pj4-cp0.c | |||
| @@ -0,0 +1,94 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/kernel/pj4-cp0.c | ||
| 3 | * | ||
| 4 | * PJ4 iWMMXt coprocessor context switching and handling | ||
| 5 | * | ||
| 6 | * Copyright (c) 2010 Marvell International Inc. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/module.h> | ||
| 14 | #include <linux/types.h> | ||
| 15 | #include <linux/kernel.h> | ||
| 16 | #include <linux/signal.h> | ||
| 17 | #include <linux/sched.h> | ||
| 18 | #include <linux/init.h> | ||
| 19 | #include <linux/io.h> | ||
| 20 | #include <asm/thread_notify.h> | ||
| 21 | |||
| 22 | static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t) | ||
| 23 | { | ||
| 24 | struct thread_info *thread = t; | ||
| 25 | |||
| 26 | switch (cmd) { | ||
| 27 | case THREAD_NOTIFY_FLUSH: | ||
| 28 | /* | ||
| 29 | * flush_thread() zeroes thread->fpstate, so no need | ||
| 30 | * to do anything here. | ||
| 31 | * | ||
| 32 | * FALLTHROUGH: Ensure we don't try to overwrite our newly | ||
| 33 | * initialised state information on the first fault. | ||
| 34 | */ | ||
| 35 | |||
| 36 | case THREAD_NOTIFY_EXIT: | ||
| 37 | iwmmxt_task_release(thread); | ||
| 38 | break; | ||
| 39 | |||
| 40 | case THREAD_NOTIFY_SWITCH: | ||
| 41 | iwmmxt_task_switch(thread); | ||
| 42 | break; | ||
| 43 | } | ||
| 44 | |||
| 45 | return NOTIFY_DONE; | ||
| 46 | } | ||
| 47 | |||
| 48 | static struct notifier_block iwmmxt_notifier_block = { | ||
| 49 | .notifier_call = iwmmxt_do, | ||
| 50 | }; | ||
| 51 | |||
| 52 | |||
| 53 | static u32 __init pj4_cp_access_read(void) | ||
| 54 | { | ||
| 55 | u32 value; | ||
| 56 | |||
| 57 | __asm__ __volatile__ ( | ||
| 58 | "mrc p15, 0, %0, c1, c0, 2\n\t" | ||
| 59 | : "=r" (value)); | ||
| 60 | return value; | ||
| 61 | } | ||
| 62 | |||
| 63 | static void __init pj4_cp_access_write(u32 value) | ||
| 64 | { | ||
| 65 | u32 temp; | ||
| 66 | |||
| 67 | __asm__ __volatile__ ( | ||
| 68 | "mcr p15, 0, %1, c1, c0, 2\n\t" | ||
| 69 | "mrc p15, 0, %0, c1, c0, 2\n\t" | ||
| 70 | "mov %0, %0\n\t" | ||
| 71 | "sub pc, pc, #4\n\t" | ||
| 72 | : "=r" (temp) : "r" (value)); | ||
| 73 | } | ||
| 74 | |||
| 75 | |||
| 76 | /* | ||
| 77 | * Disable CP0/CP1 on boot, and let call_fpe() and the iWMMXt lazy | ||
| 78 | * switch code handle iWMMXt context switching. | ||
| 79 | */ | ||
| 80 | static int __init pj4_cp0_init(void) | ||
| 81 | { | ||
| 82 | u32 cp_access; | ||
| 83 | |||
| 84 | cp_access = pj4_cp_access_read() & ~0xf; | ||
| 85 | pj4_cp_access_write(cp_access); | ||
| 86 | |||
| 87 | printk(KERN_INFO "PJ4 iWMMXt coprocessor enabled.\n"); | ||
| 88 | elf_hwcap |= HWCAP_IWMMXT; | ||
| 89 | thread_register_notifier(&iwmmxt_notifier_block); | ||
| 90 | |||
| 91 | return 0; | ||
| 92 | } | ||
| 93 | |||
| 94 | late_initcall(pj4_cp0_init); | ||
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c index 3e97483abcf0..19c6816db61e 100644 --- a/arch/arm/kernel/ptrace.c +++ b/arch/arm/kernel/ptrace.c | |||
| @@ -1060,8 +1060,8 @@ static int ptrace_sethbpregs(struct task_struct *tsk, long num, | |||
| 1060 | goto out; | 1060 | goto out; |
| 1061 | 1061 | ||
| 1062 | if ((gen_type & implied_type) != gen_type) { | 1062 | if ((gen_type & implied_type) != gen_type) { |
| 1063 | ret = -EINVAL; | 1063 | ret = -EINVAL; |
| 1064 | goto out; | 1064 | goto out; |
| 1065 | } | 1065 | } |
| 1066 | 1066 | ||
| 1067 | attr.bp_len = gen_len; | 1067 | attr.bp_len = gen_len; |
diff --git a/arch/arm/kernel/sched_clock.c b/arch/arm/kernel/sched_clock.c new file mode 100644 index 000000000000..2cdcc9287c74 --- /dev/null +++ b/arch/arm/kernel/sched_clock.c | |||
| @@ -0,0 +1,69 @@ | |||
| 1 | /* | ||
| 2 | * sched_clock.c: support for extending counters to full 64-bit ns counter | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | #include <linux/clocksource.h> | ||
| 9 | #include <linux/init.h> | ||
| 10 | #include <linux/jiffies.h> | ||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/sched.h> | ||
| 13 | #include <linux/timer.h> | ||
| 14 | |||
| 15 | #include <asm/sched_clock.h> | ||
| 16 | |||
| 17 | static void sched_clock_poll(unsigned long wrap_ticks); | ||
| 18 | static DEFINE_TIMER(sched_clock_timer, sched_clock_poll, 0, 0); | ||
| 19 | static void (*sched_clock_update_fn)(void); | ||
| 20 | |||
| 21 | static void sched_clock_poll(unsigned long wrap_ticks) | ||
| 22 | { | ||
| 23 | mod_timer(&sched_clock_timer, round_jiffies(jiffies + wrap_ticks)); | ||
| 24 | sched_clock_update_fn(); | ||
| 25 | } | ||
| 26 | |||
| 27 | void __init init_sched_clock(struct clock_data *cd, void (*update)(void), | ||
| 28 | unsigned int clock_bits, unsigned long rate) | ||
| 29 | { | ||
| 30 | unsigned long r, w; | ||
| 31 | u64 res, wrap; | ||
| 32 | char r_unit; | ||
| 33 | |||
| 34 | sched_clock_update_fn = update; | ||
| 35 | |||
| 36 | /* calculate the mult/shift to convert counter ticks to ns. */ | ||
| 37 | clocks_calc_mult_shift(&cd->mult, &cd->shift, rate, NSEC_PER_SEC, 60); | ||
| 38 | |||
| 39 | r = rate; | ||
| 40 | if (r >= 4000000) { | ||
| 41 | r /= 1000000; | ||
| 42 | r_unit = 'M'; | ||
| 43 | } else { | ||
| 44 | r /= 1000; | ||
| 45 | r_unit = 'k'; | ||
| 46 | } | ||
| 47 | |||
| 48 | /* calculate how many ns until we wrap */ | ||
| 49 | wrap = cyc_to_ns((1ULL << clock_bits) - 1, cd->mult, cd->shift); | ||
| 50 | do_div(wrap, NSEC_PER_MSEC); | ||
| 51 | w = wrap; | ||
| 52 | |||
| 53 | /* calculate the ns resolution of this counter */ | ||
| 54 | res = cyc_to_ns(1ULL, cd->mult, cd->shift); | ||
| 55 | pr_info("sched_clock: %u bits at %lu%cHz, resolution %lluns, wraps every %lums\n", | ||
| 56 | clock_bits, r, r_unit, res, w); | ||
| 57 | |||
| 58 | /* | ||
| 59 | * Start the timer to keep sched_clock() properly updated and | ||
| 60 | * sets the initial epoch. | ||
| 61 | */ | ||
| 62 | sched_clock_timer.data = msecs_to_jiffies(w - (w / 10)); | ||
| 63 | sched_clock_poll(sched_clock_timer.data); | ||
| 64 | |||
| 65 | /* | ||
| 66 | * Ensure that sched_clock() starts off at 0ns | ||
| 67 | */ | ||
| 68 | cd->epoch_ns = 0; | ||
| 69 | } | ||
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 336f14e0e5c2..3455ad33de4c 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c | |||
| @@ -75,9 +75,9 @@ extern void reboot_setup(char *str); | |||
| 75 | 75 | ||
| 76 | unsigned int processor_id; | 76 | unsigned int processor_id; |
| 77 | EXPORT_SYMBOL(processor_id); | 77 | EXPORT_SYMBOL(processor_id); |
| 78 | unsigned int __machine_arch_type; | 78 | unsigned int __machine_arch_type __read_mostly; |
| 79 | EXPORT_SYMBOL(__machine_arch_type); | 79 | EXPORT_SYMBOL(__machine_arch_type); |
| 80 | unsigned int cacheid; | 80 | unsigned int cacheid __read_mostly; |
| 81 | EXPORT_SYMBOL(cacheid); | 81 | EXPORT_SYMBOL(cacheid); |
| 82 | 82 | ||
| 83 | unsigned int __atags_pointer __initdata; | 83 | unsigned int __atags_pointer __initdata; |
| @@ -91,24 +91,24 @@ EXPORT_SYMBOL(system_serial_low); | |||
| 91 | unsigned int system_serial_high; | 91 | unsigned int system_serial_high; |
| 92 | EXPORT_SYMBOL(system_serial_high); | 92 | EXPORT_SYMBOL(system_serial_high); |
| 93 | 93 | ||
| 94 | unsigned int elf_hwcap; | 94 | unsigned int elf_hwcap __read_mostly; |
| 95 | EXPORT_SYMBOL(elf_hwcap); | 95 | EXPORT_SYMBOL(elf_hwcap); |
| 96 | 96 | ||
| 97 | 97 | ||
| 98 | #ifdef MULTI_CPU | 98 | #ifdef MULTI_CPU |
| 99 | struct processor processor; | 99 | struct processor processor __read_mostly; |
| 100 | #endif | 100 | #endif |
| 101 | #ifdef MULTI_TLB | 101 | #ifdef MULTI_TLB |
| 102 | struct cpu_tlb_fns cpu_tlb; | 102 | struct cpu_tlb_fns cpu_tlb __read_mostly; |
| 103 | #endif | 103 | #endif |
| 104 | #ifdef MULTI_USER | 104 | #ifdef MULTI_USER |
| 105 | struct cpu_user_fns cpu_user; | 105 | struct cpu_user_fns cpu_user __read_mostly; |
| 106 | #endif | 106 | #endif |
| 107 | #ifdef MULTI_CACHE | 107 | #ifdef MULTI_CACHE |
| 108 | struct cpu_cache_fns cpu_cache; | 108 | struct cpu_cache_fns cpu_cache __read_mostly; |
| 109 | #endif | 109 | #endif |
| 110 | #ifdef CONFIG_OUTER_CACHE | 110 | #ifdef CONFIG_OUTER_CACHE |
| 111 | struct outer_cache_fns outer_cache; | 111 | struct outer_cache_fns outer_cache __read_mostly; |
| 112 | EXPORT_SYMBOL(outer_cache); | 112 | EXPORT_SYMBOL(outer_cache); |
| 113 | #endif | 113 | #endif |
| 114 | 114 | ||
| @@ -126,6 +126,7 @@ EXPORT_SYMBOL(elf_platform); | |||
| 126 | static const char *cpu_name; | 126 | static const char *cpu_name; |
| 127 | static const char *machine_name; | 127 | static const char *machine_name; |
| 128 | static char __initdata cmd_line[COMMAND_LINE_SIZE]; | 128 | static char __initdata cmd_line[COMMAND_LINE_SIZE]; |
| 129 | struct machine_desc *machine_desc __initdata; | ||
| 129 | 130 | ||
| 130 | static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE; | 131 | static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE; |
| 131 | static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } }; | 132 | static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } }; |
| @@ -708,13 +709,11 @@ static struct init_tags { | |||
| 708 | { 0, ATAG_NONE } | 709 | { 0, ATAG_NONE } |
| 709 | }; | 710 | }; |
| 710 | 711 | ||
| 711 | static void (*init_machine)(void) __initdata; | ||
| 712 | |||
| 713 | static int __init customize_machine(void) | 712 | static int __init customize_machine(void) |
| 714 | { | 713 | { |
| 715 | /* customizes platform devices, or adds new ones */ | 714 | /* customizes platform devices, or adds new ones */ |
| 716 | if (init_machine) | 715 | if (machine_desc->init_machine) |
| 717 | init_machine(); | 716 | machine_desc->init_machine(); |
| 718 | return 0; | 717 | return 0; |
| 719 | } | 718 | } |
| 720 | arch_initcall(customize_machine); | 719 | arch_initcall(customize_machine); |
| @@ -809,6 +808,7 @@ void __init setup_arch(char **cmdline_p) | |||
| 809 | 808 | ||
| 810 | setup_processor(); | 809 | setup_processor(); |
| 811 | mdesc = setup_machine(machine_arch_type); | 810 | mdesc = setup_machine(machine_arch_type); |
| 811 | machine_desc = mdesc; | ||
| 812 | machine_name = mdesc->name; | 812 | machine_name = mdesc->name; |
| 813 | 813 | ||
| 814 | if (mdesc->soft_reboot) | 814 | if (mdesc->soft_reboot) |
| @@ -868,13 +868,9 @@ void __init setup_arch(char **cmdline_p) | |||
| 868 | cpu_init(); | 868 | cpu_init(); |
| 869 | tcm_init(); | 869 | tcm_init(); |
| 870 | 870 | ||
| 871 | /* | 871 | #ifdef CONFIG_MULTI_IRQ_HANDLER |
| 872 | * Set up various architecture-specific pointers | 872 | handle_arch_irq = mdesc->handle_irq; |
| 873 | */ | 873 | #endif |
| 874 | arch_nr_irqs = mdesc->nr_irqs; | ||
| 875 | init_arch_irq = mdesc->init_irq; | ||
| 876 | system_timer = mdesc->timer; | ||
| 877 | init_machine = mdesc->init_machine; | ||
| 878 | 874 | ||
| 879 | #ifdef CONFIG_VT | 875 | #ifdef CONFIG_VT |
| 880 | #if defined(CONFIG_VGA_CONSOLE) | 876 | #if defined(CONFIG_VGA_CONSOLE) |
| @@ -884,6 +880,9 @@ void __init setup_arch(char **cmdline_p) | |||
| 884 | #endif | 880 | #endif |
| 885 | #endif | 881 | #endif |
| 886 | early_trap_init(); | 882 | early_trap_init(); |
| 883 | |||
| 884 | if (mdesc->init_early) | ||
| 885 | mdesc->init_early(); | ||
| 887 | } | 886 | } |
| 888 | 887 | ||
| 889 | 888 | ||
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 9066473c0ebc..4539ebcb089f 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c | |||
| @@ -16,6 +16,7 @@ | |||
| 16 | #include <linux/cache.h> | 16 | #include <linux/cache.h> |
| 17 | #include <linux/profile.h> | 17 | #include <linux/profile.h> |
| 18 | #include <linux/errno.h> | 18 | #include <linux/errno.h> |
| 19 | #include <linux/ftrace.h> | ||
| 19 | #include <linux/mm.h> | 20 | #include <linux/mm.h> |
| 20 | #include <linux/err.h> | 21 | #include <linux/err.h> |
| 21 | #include <linux/cpu.h> | 22 | #include <linux/cpu.h> |
| @@ -24,6 +25,7 @@ | |||
| 24 | #include <linux/irq.h> | 25 | #include <linux/irq.h> |
| 25 | #include <linux/percpu.h> | 26 | #include <linux/percpu.h> |
| 26 | #include <linux/clockchips.h> | 27 | #include <linux/clockchips.h> |
| 28 | #include <linux/completion.h> | ||
| 27 | 29 | ||
| 28 | #include <asm/atomic.h> | 30 | #include <asm/atomic.h> |
| 29 | #include <asm/cacheflush.h> | 31 | #include <asm/cacheflush.h> |
| @@ -37,7 +39,6 @@ | |||
| 37 | #include <asm/tlbflush.h> | 39 | #include <asm/tlbflush.h> |
| 38 | #include <asm/ptrace.h> | 40 | #include <asm/ptrace.h> |
| 39 | #include <asm/localtimer.h> | 41 | #include <asm/localtimer.h> |
| 40 | #include <asm/smp_plat.h> | ||
| 41 | 42 | ||
| 42 | /* | 43 | /* |
| 43 | * as from 2.5, kernels no longer have an init_tasks structure | 44 | * as from 2.5, kernels no longer have an init_tasks structure |
| @@ -46,64 +47,14 @@ | |||
| 46 | */ | 47 | */ |
| 47 | struct secondary_data secondary_data; | 48 | struct secondary_data secondary_data; |
| 48 | 49 | ||
| 49 | /* | ||
| 50 | * structures for inter-processor calls | ||
| 51 | * - A collection of single bit ipi messages. | ||
| 52 | */ | ||
| 53 | struct ipi_data { | ||
| 54 | spinlock_t lock; | ||
| 55 | unsigned long ipi_count; | ||
| 56 | unsigned long bits; | ||
| 57 | }; | ||
| 58 | |||
| 59 | static DEFINE_PER_CPU(struct ipi_data, ipi_data) = { | ||
| 60 | .lock = SPIN_LOCK_UNLOCKED, | ||
| 61 | }; | ||
| 62 | |||
| 63 | enum ipi_msg_type { | 50 | enum ipi_msg_type { |
| 64 | IPI_TIMER, | 51 | IPI_TIMER = 2, |
| 65 | IPI_RESCHEDULE, | 52 | IPI_RESCHEDULE, |
| 66 | IPI_CALL_FUNC, | 53 | IPI_CALL_FUNC, |
| 67 | IPI_CALL_FUNC_SINGLE, | 54 | IPI_CALL_FUNC_SINGLE, |
| 68 | IPI_CPU_STOP, | 55 | IPI_CPU_STOP, |
| 69 | }; | 56 | }; |
| 70 | 57 | ||
| 71 | static inline void identity_mapping_add(pgd_t *pgd, unsigned long start, | ||
| 72 | unsigned long end) | ||
| 73 | { | ||
| 74 | unsigned long addr, prot; | ||
| 75 | pmd_t *pmd; | ||
| 76 | |||
| 77 | prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE; | ||
| 78 | if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale()) | ||
| 79 | prot |= PMD_BIT4; | ||
| 80 | |||
| 81 | for (addr = start & PGDIR_MASK; addr < end;) { | ||
| 82 | pmd = pmd_offset(pgd + pgd_index(addr), addr); | ||
| 83 | pmd[0] = __pmd(addr | prot); | ||
| 84 | addr += SECTION_SIZE; | ||
| 85 | pmd[1] = __pmd(addr | prot); | ||
| 86 | addr += SECTION_SIZE; | ||
| 87 | flush_pmd_entry(pmd); | ||
| 88 | outer_clean_range(__pa(pmd), __pa(pmd + 1)); | ||
| 89 | } | ||
| 90 | } | ||
| 91 | |||
| 92 | static inline void identity_mapping_del(pgd_t *pgd, unsigned long start, | ||
| 93 | unsigned long end) | ||
| 94 | { | ||
| 95 | unsigned long addr; | ||
| 96 | pmd_t *pmd; | ||
| 97 | |||
| 98 | for (addr = start & PGDIR_MASK; addr < end; addr += PGDIR_SIZE) { | ||
| 99 | pmd = pmd_offset(pgd + pgd_index(addr), addr); | ||
| 100 | pmd[0] = __pmd(0); | ||
| 101 | pmd[1] = __pmd(0); | ||
| 102 | clean_pmd_entry(pmd); | ||
| 103 | outer_clean_range(__pa(pmd), __pa(pmd + 1)); | ||
| 104 | } | ||
| 105 | } | ||
| 106 | |||
| 107 | int __cpuinit __cpu_up(unsigned int cpu) | 58 | int __cpuinit __cpu_up(unsigned int cpu) |
| 108 | { | 59 | { |
| 109 | struct cpuinfo_arm *ci = &per_cpu(cpu_data, cpu); | 60 | struct cpuinfo_arm *ci = &per_cpu(cpu_data, cpu); |
| @@ -177,8 +128,12 @@ int __cpuinit __cpu_up(unsigned int cpu) | |||
| 177 | barrier(); | 128 | barrier(); |
| 178 | } | 129 | } |
| 179 | 130 | ||
| 180 | if (!cpu_online(cpu)) | 131 | if (!cpu_online(cpu)) { |
| 132 | pr_crit("CPU%u: failed to come online\n", cpu); | ||
| 181 | ret = -EIO; | 133 | ret = -EIO; |
| 134 | } | ||
| 135 | } else { | ||
| 136 | pr_err("CPU%u: failed to boot: %d\n", cpu, ret); | ||
| 182 | } | 137 | } |
| 183 | 138 | ||
| 184 | secondary_data.stack = NULL; | 139 | secondary_data.stack = NULL; |
| @@ -194,18 +149,12 @@ int __cpuinit __cpu_up(unsigned int cpu) | |||
| 194 | 149 | ||
| 195 | pgd_free(&init_mm, pgd); | 150 | pgd_free(&init_mm, pgd); |
| 196 | 151 | ||
| 197 | if (ret) { | ||
| 198 | printk(KERN_CRIT "CPU%u: processor failed to boot\n", cpu); | ||
| 199 | |||
| 200 | /* | ||
| 201 | * FIXME: We need to clean up the new idle thread. --rmk | ||
| 202 | */ | ||
| 203 | } | ||
| 204 | |||
| 205 | return ret; | 152 | return ret; |
| 206 | } | 153 | } |
| 207 | 154 | ||
| 208 | #ifdef CONFIG_HOTPLUG_CPU | 155 | #ifdef CONFIG_HOTPLUG_CPU |
| 156 | static void percpu_timer_stop(void); | ||
| 157 | |||
| 209 | /* | 158 | /* |
| 210 | * __cpu_disable runs on the processor to be shutdown. | 159 | * __cpu_disable runs on the processor to be shutdown. |
| 211 | */ | 160 | */ |
| @@ -233,7 +182,7 @@ int __cpu_disable(void) | |||
| 233 | /* | 182 | /* |
| 234 | * Stop the local timer for this CPU. | 183 | * Stop the local timer for this CPU. |
| 235 | */ | 184 | */ |
| 236 | local_timer_stop(); | 185 | percpu_timer_stop(); |
| 237 | 186 | ||
| 238 | /* | 187 | /* |
| 239 | * Flush user cache and TLB mappings, and then remove this CPU | 188 | * Flush user cache and TLB mappings, and then remove this CPU |
| @@ -252,12 +201,20 @@ int __cpu_disable(void) | |||
| 252 | return 0; | 201 | return 0; |
| 253 | } | 202 | } |
| 254 | 203 | ||
| 204 | static DECLARE_COMPLETION(cpu_died); | ||
| 205 | |||
| 255 | /* | 206 | /* |
| 256 | * called on the thread which is asking for a CPU to be shutdown - | 207 | * called on the thread which is asking for a CPU to be shutdown - |
| 257 | * waits until shutdown has completed, or it is timed out. | 208 | * waits until shutdown has completed, or it is timed out. |
| 258 | */ | 209 | */ |
| 259 | void __cpu_die(unsigned int cpu) | 210 | void __cpu_die(unsigned int cpu) |
| 260 | { | 211 | { |
| 212 | if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(5000))) { | ||
| 213 | pr_err("CPU%u: cpu didn't die\n", cpu); | ||
| 214 | return; | ||
| 215 | } | ||
| 216 | printk(KERN_NOTICE "CPU%u: shutdown\n", cpu); | ||
| 217 | |||
| 261 | if (!platform_cpu_kill(cpu)) | 218 | if (!platform_cpu_kill(cpu)) |
| 262 | printk("CPU%u: unable to kill\n", cpu); | 219 | printk("CPU%u: unable to kill\n", cpu); |
| 263 | } | 220 | } |
| @@ -274,12 +231,17 @@ void __ref cpu_die(void) | |||
| 274 | { | 231 | { |
| 275 | unsigned int cpu = smp_processor_id(); | 232 | unsigned int cpu = smp_processor_id(); |
| 276 | 233 | ||
| 277 | local_irq_disable(); | ||
| 278 | idle_task_exit(); | 234 | idle_task_exit(); |
| 279 | 235 | ||
| 236 | local_irq_disable(); | ||
| 237 | mb(); | ||
| 238 | |||
| 239 | /* Tell __cpu_die() that this CPU is now safe to dispose of */ | ||
| 240 | complete(&cpu_died); | ||
| 241 | |||
| 280 | /* | 242 | /* |
| 281 | * actual CPU shutdown procedure is at least platform (if not | 243 | * actual CPU shutdown procedure is at least platform (if not |
| 282 | * CPU) specific | 244 | * CPU) specific. |
| 283 | */ | 245 | */ |
| 284 | platform_cpu_die(cpu); | 246 | platform_cpu_die(cpu); |
| 285 | 247 | ||
| @@ -289,6 +251,7 @@ void __ref cpu_die(void) | |||
| 289 | * to be repeated to undo the effects of taking the CPU offline. | 251 | * to be repeated to undo the effects of taking the CPU offline. |
| 290 | */ | 252 | */ |
| 291 | __asm__("mov sp, %0\n" | 253 | __asm__("mov sp, %0\n" |
| 254 | " mov fp, #0\n" | ||
| 292 | " b secondary_start_kernel" | 255 | " b secondary_start_kernel" |
| 293 | : | 256 | : |
| 294 | : "r" (task_stack_page(current) + THREAD_SIZE - 8)); | 257 | : "r" (task_stack_page(current) + THREAD_SIZE - 8)); |
| @@ -296,6 +259,17 @@ void __ref cpu_die(void) | |||
| 296 | #endif /* CONFIG_HOTPLUG_CPU */ | 259 | #endif /* CONFIG_HOTPLUG_CPU */ |
| 297 | 260 | ||
| 298 | /* | 261 | /* |
| 262 | * Called by both boot and secondaries to move global data into | ||
| 263 | * per-processor storage. | ||
| 264 | */ | ||
| 265 | static void __cpuinit smp_store_cpu_info(unsigned int cpuid) | ||
| 266 | { | ||
| 267 | struct cpuinfo_arm *cpu_info = &per_cpu(cpu_data, cpuid); | ||
| 268 | |||
| 269 | cpu_info->loops_per_jiffy = loops_per_jiffy; | ||
| 270 | } | ||
| 271 | |||
| 272 | /* | ||
| 299 | * This is the secondary CPU boot entry. We're using this CPUs | 273 | * This is the secondary CPU boot entry. We're using this CPUs |
| 300 | * idle thread stack, but a set of temporary page tables. | 274 | * idle thread stack, but a set of temporary page tables. |
| 301 | */ | 275 | */ |
| @@ -319,6 +293,7 @@ asmlinkage void __cpuinit secondary_start_kernel(void) | |||
| 319 | 293 | ||
| 320 | cpu_init(); | 294 | cpu_init(); |
| 321 | preempt_disable(); | 295 | preempt_disable(); |
| 296 | trace_hardirqs_off(); | ||
| 322 | 297 | ||
| 323 | /* | 298 | /* |
| 324 | * Give the platform a chance to do its own initialisation. | 299 | * Give the platform a chance to do its own initialisation. |
| @@ -352,17 +327,6 @@ asmlinkage void __cpuinit secondary_start_kernel(void) | |||
| 352 | cpu_idle(); | 327 | cpu_idle(); |
| 353 | } | 328 | } |
| 354 | 329 | ||
| 355 | /* | ||
| 356 | * Called by both boot and secondaries to move global data into | ||
| 357 | * per-processor storage. | ||
| 358 | */ | ||
| 359 | void __cpuinit smp_store_cpu_info(unsigned int cpuid) | ||
| 360 | { | ||
| 361 | struct cpuinfo_arm *cpu_info = &per_cpu(cpu_data, cpuid); | ||
| 362 | |||
| 363 | cpu_info->loops_per_jiffy = loops_per_jiffy; | ||
| 364 | } | ||
| 365 | |||
| 366 | void __init smp_cpus_done(unsigned int max_cpus) | 330 | void __init smp_cpus_done(unsigned int max_cpus) |
| 367 | { | 331 | { |
| 368 | int cpu; | 332 | int cpu; |
| @@ -385,61 +349,80 @@ void __init smp_prepare_boot_cpu(void) | |||
| 385 | per_cpu(cpu_data, cpu).idle = current; | 349 | per_cpu(cpu_data, cpu).idle = current; |
| 386 | } | 350 | } |
| 387 | 351 | ||
| 388 | static void send_ipi_message(const struct cpumask *mask, enum ipi_msg_type msg) | 352 | void __init smp_prepare_cpus(unsigned int max_cpus) |
| 389 | { | 353 | { |
| 390 | unsigned long flags; | 354 | unsigned int ncores = num_possible_cpus(); |
| 391 | unsigned int cpu; | ||
| 392 | 355 | ||
| 393 | local_irq_save(flags); | 356 | smp_store_cpu_info(smp_processor_id()); |
| 394 | |||
| 395 | for_each_cpu(cpu, mask) { | ||
| 396 | struct ipi_data *ipi = &per_cpu(ipi_data, cpu); | ||
| 397 | |||
| 398 | spin_lock(&ipi->lock); | ||
| 399 | ipi->bits |= 1 << msg; | ||
| 400 | spin_unlock(&ipi->lock); | ||
| 401 | } | ||
| 402 | 357 | ||
| 403 | /* | 358 | /* |
| 404 | * Call the platform specific cross-CPU call function. | 359 | * are we trying to boot more cores than exist? |
| 405 | */ | 360 | */ |
| 406 | smp_cross_call(mask); | 361 | if (max_cpus > ncores) |
| 362 | max_cpus = ncores; | ||
| 363 | |||
| 364 | if (max_cpus > 1) { | ||
| 365 | /* | ||
| 366 | * Enable the local timer or broadcast device for the | ||
| 367 | * boot CPU, but only if we have more than one CPU. | ||
| 368 | */ | ||
| 369 | percpu_timer_setup(); | ||
| 407 | 370 | ||
| 408 | local_irq_restore(flags); | 371 | /* |
| 372 | * Initialise the SCU if there are more than one CPU | ||
| 373 | * and let them know where to start. | ||
| 374 | */ | ||
| 375 | platform_smp_prepare_cpus(max_cpus); | ||
| 376 | } | ||
| 409 | } | 377 | } |
| 410 | 378 | ||
| 411 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) | 379 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
| 412 | { | 380 | { |
| 413 | send_ipi_message(mask, IPI_CALL_FUNC); | 381 | smp_cross_call(mask, IPI_CALL_FUNC); |
| 414 | } | 382 | } |
| 415 | 383 | ||
| 416 | void arch_send_call_function_single_ipi(int cpu) | 384 | void arch_send_call_function_single_ipi(int cpu) |
| 417 | { | 385 | { |
| 418 | send_ipi_message(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE); | 386 | smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE); |
| 419 | } | 387 | } |
| 420 | 388 | ||
| 421 | void show_ipi_list(struct seq_file *p) | 389 | static const char *ipi_types[NR_IPI] = { |
| 390 | #define S(x,s) [x - IPI_TIMER] = s | ||
| 391 | S(IPI_TIMER, "Timer broadcast interrupts"), | ||
| 392 | S(IPI_RESCHEDULE, "Rescheduling interrupts"), | ||
| 393 | S(IPI_CALL_FUNC, "Function call interrupts"), | ||
| 394 | S(IPI_CALL_FUNC_SINGLE, "Single function call interrupts"), | ||
| 395 | S(IPI_CPU_STOP, "CPU stop interrupts"), | ||
| 396 | }; | ||
| 397 | |||
| 398 | void show_ipi_list(struct seq_file *p, int prec) | ||
| 422 | { | 399 | { |
| 423 | unsigned int cpu; | 400 | unsigned int cpu, i; |
| 424 | 401 | ||
| 425 | seq_puts(p, "IPI:"); | 402 | for (i = 0; i < NR_IPI; i++) { |
| 403 | seq_printf(p, "%*s%u: ", prec - 1, "IPI", i); | ||
| 426 | 404 | ||
| 427 | for_each_present_cpu(cpu) | 405 | for_each_present_cpu(cpu) |
| 428 | seq_printf(p, " %10lu", per_cpu(ipi_data, cpu).ipi_count); | 406 | seq_printf(p, "%10u ", |
| 407 | __get_irq_stat(cpu, ipi_irqs[i])); | ||
| 429 | 408 | ||
| 430 | seq_putc(p, '\n'); | 409 | seq_printf(p, " %s\n", ipi_types[i]); |
| 410 | } | ||
| 431 | } | 411 | } |
| 432 | 412 | ||
| 433 | void show_local_irqs(struct seq_file *p) | 413 | u64 smp_irq_stat_cpu(unsigned int cpu) |
| 434 | { | 414 | { |
| 435 | unsigned int cpu; | 415 | u64 sum = 0; |
| 416 | int i; | ||
| 436 | 417 | ||
| 437 | seq_printf(p, "LOC: "); | 418 | for (i = 0; i < NR_IPI; i++) |
| 419 | sum += __get_irq_stat(cpu, ipi_irqs[i]); | ||
| 438 | 420 | ||
| 439 | for_each_present_cpu(cpu) | 421 | #ifdef CONFIG_LOCAL_TIMERS |
| 440 | seq_printf(p, "%10u ", irq_stat[cpu].local_timer_irqs); | 422 | sum += __get_irq_stat(cpu, local_timer_irqs); |
| 423 | #endif | ||
| 441 | 424 | ||
| 442 | seq_putc(p, '\n'); | 425 | return sum; |
| 443 | } | 426 | } |
| 444 | 427 | ||
| 445 | /* | 428 | /* |
| @@ -456,24 +439,36 @@ static void ipi_timer(void) | |||
| 456 | } | 439 | } |
| 457 | 440 | ||
| 458 | #ifdef CONFIG_LOCAL_TIMERS | 441 | #ifdef CONFIG_LOCAL_TIMERS |
| 459 | asmlinkage void __exception do_local_timer(struct pt_regs *regs) | 442 | asmlinkage void __exception_irq_entry do_local_timer(struct pt_regs *regs) |
| 460 | { | 443 | { |
| 461 | struct pt_regs *old_regs = set_irq_regs(regs); | 444 | struct pt_regs *old_regs = set_irq_regs(regs); |
| 462 | int cpu = smp_processor_id(); | 445 | int cpu = smp_processor_id(); |
| 463 | 446 | ||
| 464 | if (local_timer_ack()) { | 447 | if (local_timer_ack()) { |
| 465 | irq_stat[cpu].local_timer_irqs++; | 448 | __inc_irq_stat(cpu, local_timer_irqs); |
| 466 | ipi_timer(); | 449 | ipi_timer(); |
| 467 | } | 450 | } |
| 468 | 451 | ||
| 469 | set_irq_regs(old_regs); | 452 | set_irq_regs(old_regs); |
| 470 | } | 453 | } |
| 454 | |||
| 455 | void show_local_irqs(struct seq_file *p, int prec) | ||
| 456 | { | ||
| 457 | unsigned int cpu; | ||
| 458 | |||
| 459 | seq_printf(p, "%*s: ", prec, "LOC"); | ||
| 460 | |||
| 461 | for_each_present_cpu(cpu) | ||
| 462 | seq_printf(p, "%10u ", __get_irq_stat(cpu, local_timer_irqs)); | ||
| 463 | |||
| 464 | seq_printf(p, " Local timer interrupts\n"); | ||
| 465 | } | ||
| 471 | #endif | 466 | #endif |
| 472 | 467 | ||
| 473 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST | 468 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
| 474 | static void smp_timer_broadcast(const struct cpumask *mask) | 469 | static void smp_timer_broadcast(const struct cpumask *mask) |
| 475 | { | 470 | { |
| 476 | send_ipi_message(mask, IPI_TIMER); | 471 | smp_cross_call(mask, IPI_TIMER); |
| 477 | } | 472 | } |
| 478 | #else | 473 | #else |
| 479 | #define smp_timer_broadcast NULL | 474 | #define smp_timer_broadcast NULL |
| @@ -510,6 +505,21 @@ void __cpuinit percpu_timer_setup(void) | |||
| 510 | local_timer_setup(evt); | 505 | local_timer_setup(evt); |
| 511 | } | 506 | } |
| 512 | 507 | ||
| 508 | #ifdef CONFIG_HOTPLUG_CPU | ||
| 509 | /* | ||
| 510 | * The generic clock events code purposely does not stop the local timer | ||
| 511 | * on CPU_DEAD/CPU_DEAD_FROZEN hotplug events, so we have to do it | ||
| 512 | * manually here. | ||
| 513 | */ | ||
| 514 | static void percpu_timer_stop(void) | ||
| 515 | { | ||
| 516 | unsigned int cpu = smp_processor_id(); | ||
| 517 | struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu); | ||
| 518 | |||
| 519 | evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt); | ||
| 520 | } | ||
| 521 | #endif | ||
| 522 | |||
| 513 | static DEFINE_SPINLOCK(stop_lock); | 523 | static DEFINE_SPINLOCK(stop_lock); |
| 514 | 524 | ||
| 515 | /* | 525 | /* |
| @@ -536,216 +546,76 @@ static void ipi_cpu_stop(unsigned int cpu) | |||
| 536 | 546 | ||
| 537 | /* | 547 | /* |
| 538 | * Main handler for inter-processor interrupts | 548 | * Main handler for inter-processor interrupts |
| 539 | * | ||
| 540 | * For ARM, the ipimask now only identifies a single | ||
| 541 | * category of IPI (Bit 1 IPIs have been replaced by a | ||
| 542 | * different mechanism): | ||
| 543 | * | ||
| 544 | * Bit 0 - Inter-processor function call | ||
| 545 | */ | 549 | */ |
| 546 | asmlinkage void __exception do_IPI(struct pt_regs *regs) | 550 | asmlinkage void __exception_irq_entry do_IPI(int ipinr, struct pt_regs *regs) |
| 547 | { | 551 | { |
| 548 | unsigned int cpu = smp_processor_id(); | 552 | unsigned int cpu = smp_processor_id(); |
| 549 | struct ipi_data *ipi = &per_cpu(ipi_data, cpu); | ||
| 550 | struct pt_regs *old_regs = set_irq_regs(regs); | 553 | struct pt_regs *old_regs = set_irq_regs(regs); |
| 551 | 554 | ||
| 552 | ipi->ipi_count++; | 555 | if (ipinr >= IPI_TIMER && ipinr < IPI_TIMER + NR_IPI) |
| 553 | 556 | __inc_irq_stat(cpu, ipi_irqs[ipinr - IPI_TIMER]); | |
| 554 | for (;;) { | ||
| 555 | unsigned long msgs; | ||
| 556 | |||
| 557 | spin_lock(&ipi->lock); | ||
| 558 | msgs = ipi->bits; | ||
| 559 | ipi->bits = 0; | ||
| 560 | spin_unlock(&ipi->lock); | ||
| 561 | 557 | ||
| 562 | if (!msgs) | 558 | switch (ipinr) { |
| 563 | break; | 559 | case IPI_TIMER: |
| 564 | 560 | ipi_timer(); | |
| 565 | do { | 561 | break; |
| 566 | unsigned nextmsg; | ||
| 567 | |||
| 568 | nextmsg = msgs & -msgs; | ||
| 569 | msgs &= ~nextmsg; | ||
| 570 | nextmsg = ffz(~nextmsg); | ||
| 571 | |||
| 572 | switch (nextmsg) { | ||
| 573 | case IPI_TIMER: | ||
| 574 | ipi_timer(); | ||
| 575 | break; | ||
| 576 | 562 | ||
| 577 | case IPI_RESCHEDULE: | 563 | case IPI_RESCHEDULE: |
| 578 | /* | 564 | /* |
| 579 | * nothing more to do - eveything is | 565 | * nothing more to do - eveything is |
| 580 | * done on the interrupt return path | 566 | * done on the interrupt return path |
| 581 | */ | 567 | */ |
| 582 | break; | 568 | break; |
| 583 | 569 | ||
| 584 | case IPI_CALL_FUNC: | 570 | case IPI_CALL_FUNC: |
| 585 | generic_smp_call_function_interrupt(); | 571 | generic_smp_call_function_interrupt(); |
| 586 | break; | 572 | break; |
| 587 | 573 | ||
| 588 | case IPI_CALL_FUNC_SINGLE: | 574 | case IPI_CALL_FUNC_SINGLE: |
| 589 | generic_smp_call_function_single_interrupt(); | 575 | generic_smp_call_function_single_interrupt(); |
| 590 | break; | 576 | break; |
| 591 | 577 | ||
| 592 | case IPI_CPU_STOP: | 578 | case IPI_CPU_STOP: |
| 593 | ipi_cpu_stop(cpu); | 579 | ipi_cpu_stop(cpu); |
| 594 | break; | 580 | break; |
| 595 | 581 | ||
| 596 | default: | 582 | default: |
| 597 | printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%x\n", | 583 | printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%x\n", |
| 598 | cpu, nextmsg); | 584 | cpu, ipinr); |
| 599 | break; | 585 | break; |
| 600 | } | ||
| 601 | } while (msgs); | ||
| 602 | } | 586 | } |
| 603 | |||
| 604 | set_irq_regs(old_regs); | 587 | set_irq_regs(old_regs); |
| 605 | } | 588 | } |
| 606 | 589 | ||
| 607 | void smp_send_reschedule(int cpu) | 590 | void smp_send_reschedule(int cpu) |
| 608 | { | 591 | { |
| 609 | send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE); | 592 | smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE); |
| 610 | } | 593 | } |
| 611 | 594 | ||
| 612 | void smp_send_stop(void) | 595 | void smp_send_stop(void) |
| 613 | { | 596 | { |
| 614 | cpumask_t mask = cpu_online_map; | 597 | unsigned long timeout; |
| 615 | cpu_clear(smp_processor_id(), mask); | ||
| 616 | if (!cpus_empty(mask)) | ||
| 617 | send_ipi_message(&mask, IPI_CPU_STOP); | ||
| 618 | } | ||
| 619 | 598 | ||
| 620 | /* | 599 | if (num_online_cpus() > 1) { |
| 621 | * not supported here | 600 | cpumask_t mask = cpu_online_map; |
| 622 | */ | 601 | cpu_clear(smp_processor_id(), mask); |
| 623 | int setup_profiling_timer(unsigned int multiplier) | ||
| 624 | { | ||
| 625 | return -EINVAL; | ||
| 626 | } | ||
| 627 | 602 | ||
| 628 | static void | 603 | smp_cross_call(&mask, IPI_CPU_STOP); |
| 629 | on_each_cpu_mask(void (*func)(void *), void *info, int wait, | 604 | } |
| 630 | const struct cpumask *mask) | ||
| 631 | { | ||
| 632 | preempt_disable(); | ||
| 633 | 605 | ||
| 634 | smp_call_function_many(mask, func, info, wait); | 606 | /* Wait up to one second for other CPUs to stop */ |
| 635 | if (cpumask_test_cpu(smp_processor_id(), mask)) | 607 | timeout = USEC_PER_SEC; |
| 636 | func(info); | 608 | while (num_online_cpus() > 1 && timeout--) |
| 609 | udelay(1); | ||
| 637 | 610 | ||
| 638 | preempt_enable(); | 611 | if (num_online_cpus() > 1) |
| 612 | pr_warning("SMP: failed to stop secondary CPUs\n"); | ||
| 639 | } | 613 | } |
| 640 | 614 | ||
| 641 | /**********************************************************************/ | ||
| 642 | |||
| 643 | /* | 615 | /* |
| 644 | * TLB operations | 616 | * not supported here |
| 645 | */ | 617 | */ |
| 646 | struct tlb_args { | 618 | int setup_profiling_timer(unsigned int multiplier) |
| 647 | struct vm_area_struct *ta_vma; | ||
| 648 | unsigned long ta_start; | ||
| 649 | unsigned long ta_end; | ||
| 650 | }; | ||
| 651 | |||
| 652 | static inline void ipi_flush_tlb_all(void *ignored) | ||
| 653 | { | ||
| 654 | local_flush_tlb_all(); | ||
| 655 | } | ||
| 656 | |||
| 657 | static inline void ipi_flush_tlb_mm(void *arg) | ||
| 658 | { | ||
| 659 | struct mm_struct *mm = (struct mm_struct *)arg; | ||
| 660 | |||
| 661 | local_flush_tlb_mm(mm); | ||
| 662 | } | ||
| 663 | |||
| 664 | static inline void ipi_flush_tlb_page(void *arg) | ||
| 665 | { | ||
| 666 | struct tlb_args *ta = (struct tlb_args *)arg; | ||
| 667 | |||
| 668 | local_flush_tlb_page(ta->ta_vma, ta->ta_start); | ||
| 669 | } | ||
| 670 | |||
| 671 | static inline void ipi_flush_tlb_kernel_page(void *arg) | ||
| 672 | { | ||
| 673 | struct tlb_args *ta = (struct tlb_args *)arg; | ||
| 674 | |||
| 675 | local_flush_tlb_kernel_page(ta->ta_start); | ||
| 676 | } | ||
| 677 | |||
| 678 | static inline void ipi_flush_tlb_range(void *arg) | ||
| 679 | { | ||
| 680 | struct tlb_args *ta = (struct tlb_args *)arg; | ||
| 681 | |||
| 682 | local_flush_tlb_range(ta->ta_vma, ta->ta_start, ta->ta_end); | ||
| 683 | } | ||
| 684 | |||
| 685 | static inline void ipi_flush_tlb_kernel_range(void *arg) | ||
| 686 | { | ||
| 687 | struct tlb_args *ta = (struct tlb_args *)arg; | ||
| 688 | |||
| 689 | local_flush_tlb_kernel_range(ta->ta_start, ta->ta_end); | ||
| 690 | } | ||
| 691 | |||
| 692 | void flush_tlb_all(void) | ||
| 693 | { | ||
| 694 | if (tlb_ops_need_broadcast()) | ||
| 695 | on_each_cpu(ipi_flush_tlb_all, NULL, 1); | ||
| 696 | else | ||
| 697 | local_flush_tlb_all(); | ||
| 698 | } | ||
| 699 | |||
| 700 | void flush_tlb_mm(struct mm_struct *mm) | ||
| 701 | { | ||
| 702 | if (tlb_ops_need_broadcast()) | ||
| 703 | on_each_cpu_mask(ipi_flush_tlb_mm, mm, 1, mm_cpumask(mm)); | ||
| 704 | else | ||
| 705 | local_flush_tlb_mm(mm); | ||
| 706 | } | ||
| 707 | |||
| 708 | void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) | ||
| 709 | { | ||
| 710 | if (tlb_ops_need_broadcast()) { | ||
| 711 | struct tlb_args ta; | ||
| 712 | ta.ta_vma = vma; | ||
| 713 | ta.ta_start = uaddr; | ||
| 714 | on_each_cpu_mask(ipi_flush_tlb_page, &ta, 1, mm_cpumask(vma->vm_mm)); | ||
| 715 | } else | ||
| 716 | local_flush_tlb_page(vma, uaddr); | ||
| 717 | } | ||
| 718 | |||
| 719 | void flush_tlb_kernel_page(unsigned long kaddr) | ||
| 720 | { | ||
| 721 | if (tlb_ops_need_broadcast()) { | ||
| 722 | struct tlb_args ta; | ||
| 723 | ta.ta_start = kaddr; | ||
| 724 | on_each_cpu(ipi_flush_tlb_kernel_page, &ta, 1); | ||
| 725 | } else | ||
| 726 | local_flush_tlb_kernel_page(kaddr); | ||
| 727 | } | ||
| 728 | |||
| 729 | void flush_tlb_range(struct vm_area_struct *vma, | ||
| 730 | unsigned long start, unsigned long end) | ||
| 731 | { | ||
| 732 | if (tlb_ops_need_broadcast()) { | ||
| 733 | struct tlb_args ta; | ||
| 734 | ta.ta_vma = vma; | ||
| 735 | ta.ta_start = start; | ||
| 736 | ta.ta_end = end; | ||
| 737 | on_each_cpu_mask(ipi_flush_tlb_range, &ta, 1, mm_cpumask(vma->vm_mm)); | ||
| 738 | } else | ||
| 739 | local_flush_tlb_range(vma, start, end); | ||
| 740 | } | ||
| 741 | |||
| 742 | void flush_tlb_kernel_range(unsigned long start, unsigned long end) | ||
| 743 | { | 619 | { |
| 744 | if (tlb_ops_need_broadcast()) { | 620 | return -EINVAL; |
| 745 | struct tlb_args ta; | ||
| 746 | ta.ta_start = start; | ||
| 747 | ta.ta_end = end; | ||
| 748 | on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1); | ||
| 749 | } else | ||
| 750 | local_flush_tlb_kernel_range(start, end); | ||
| 751 | } | 621 | } |
diff --git a/arch/arm/kernel/smp_tlb.c b/arch/arm/kernel/smp_tlb.c new file mode 100644 index 000000000000..7dcb35285be7 --- /dev/null +++ b/arch/arm/kernel/smp_tlb.c | |||
| @@ -0,0 +1,139 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/kernel/smp_tlb.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | #include <linux/preempt.h> | ||
| 11 | #include <linux/smp.h> | ||
| 12 | |||
| 13 | #include <asm/smp_plat.h> | ||
| 14 | #include <asm/tlbflush.h> | ||
| 15 | |||
| 16 | static void on_each_cpu_mask(void (*func)(void *), void *info, int wait, | ||
| 17 | const struct cpumask *mask) | ||
| 18 | { | ||
| 19 | preempt_disable(); | ||
| 20 | |||
| 21 | smp_call_function_many(mask, func, info, wait); | ||
| 22 | if (cpumask_test_cpu(smp_processor_id(), mask)) | ||
| 23 | func(info); | ||
| 24 | |||
| 25 | preempt_enable(); | ||
| 26 | } | ||
| 27 | |||
| 28 | /**********************************************************************/ | ||
| 29 | |||
| 30 | /* | ||
| 31 | * TLB operations | ||
| 32 | */ | ||
| 33 | struct tlb_args { | ||
| 34 | struct vm_area_struct *ta_vma; | ||
| 35 | unsigned long ta_start; | ||
| 36 | unsigned long ta_end; | ||
| 37 | }; | ||
| 38 | |||
| 39 | static inline void ipi_flush_tlb_all(void *ignored) | ||
| 40 | { | ||
| 41 | local_flush_tlb_all(); | ||
| 42 | } | ||
| 43 | |||
| 44 | static inline void ipi_flush_tlb_mm(void *arg) | ||
| 45 | { | ||
| 46 | struct mm_struct *mm = (struct mm_struct *)arg; | ||
| 47 | |||
| 48 | local_flush_tlb_mm(mm); | ||
| 49 | } | ||
| 50 | |||
| 51 | static inline void ipi_flush_tlb_page(void *arg) | ||
| 52 | { | ||
| 53 | struct tlb_args *ta = (struct tlb_args *)arg; | ||
| 54 | |||
| 55 | local_flush_tlb_page(ta->ta_vma, ta->ta_start); | ||
| 56 | } | ||
| 57 | |||
| 58 | static inline void ipi_flush_tlb_kernel_page(void *arg) | ||
| 59 | { | ||
| 60 | struct tlb_args *ta = (struct tlb_args *)arg; | ||
| 61 | |||
| 62 | local_flush_tlb_kernel_page(ta->ta_start); | ||
| 63 | } | ||
| 64 | |||
| 65 | static inline void ipi_flush_tlb_range(void *arg) | ||
| 66 | { | ||
| 67 | struct tlb_args *ta = (struct tlb_args *)arg; | ||
| 68 | |||
| 69 | local_flush_tlb_range(ta->ta_vma, ta->ta_start, ta->ta_end); | ||
| 70 | } | ||
| 71 | |||
| 72 | static inline void ipi_flush_tlb_kernel_range(void *arg) | ||
| 73 | { | ||
| 74 | struct tlb_args *ta = (struct tlb_args *)arg; | ||
| 75 | |||
| 76 | local_flush_tlb_kernel_range(ta->ta_start, ta->ta_end); | ||
| 77 | } | ||
| 78 | |||
| 79 | void flush_tlb_all(void) | ||
| 80 | { | ||
| 81 | if (tlb_ops_need_broadcast()) | ||
| 82 | on_each_cpu(ipi_flush_tlb_all, NULL, 1); | ||
| 83 | else | ||
| 84 | local_flush_tlb_all(); | ||
| 85 | } | ||
| 86 | |||
| 87 | void flush_tlb_mm(struct mm_struct *mm) | ||
| 88 | { | ||
| 89 | if (tlb_ops_need_broadcast()) | ||
| 90 | on_each_cpu_mask(ipi_flush_tlb_mm, mm, 1, mm_cpumask(mm)); | ||
| 91 | else | ||
| 92 | local_flush_tlb_mm(mm); | ||
| 93 | } | ||
| 94 | |||
| 95 | void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) | ||
| 96 | { | ||
| 97 | if (tlb_ops_need_broadcast()) { | ||
| 98 | struct tlb_args ta; | ||
| 99 | ta.ta_vma = vma; | ||
| 100 | ta.ta_start = uaddr; | ||
| 101 | on_each_cpu_mask(ipi_flush_tlb_page, &ta, 1, mm_cpumask(vma->vm_mm)); | ||
| 102 | } else | ||
| 103 | local_flush_tlb_page(vma, uaddr); | ||
| 104 | } | ||
| 105 | |||
| 106 | void flush_tlb_kernel_page(unsigned long kaddr) | ||
| 107 | { | ||
| 108 | if (tlb_ops_need_broadcast()) { | ||
| 109 | struct tlb_args ta; | ||
| 110 | ta.ta_start = kaddr; | ||
| 111 | on_each_cpu(ipi_flush_tlb_kernel_page, &ta, 1); | ||
| 112 | } else | ||
| 113 | local_flush_tlb_kernel_page(kaddr); | ||
| 114 | } | ||
| 115 | |||
| 116 | void flush_tlb_range(struct vm_area_struct *vma, | ||
| 117 | unsigned long start, unsigned long end) | ||
| 118 | { | ||
| 119 | if (tlb_ops_need_broadcast()) { | ||
| 120 | struct tlb_args ta; | ||
| 121 | ta.ta_vma = vma; | ||
| 122 | ta.ta_start = start; | ||
| 123 | ta.ta_end = end; | ||
| 124 | on_each_cpu_mask(ipi_flush_tlb_range, &ta, 1, mm_cpumask(vma->vm_mm)); | ||
| 125 | } else | ||
| 126 | local_flush_tlb_range(vma, start, end); | ||
| 127 | } | ||
| 128 | |||
| 129 | void flush_tlb_kernel_range(unsigned long start, unsigned long end) | ||
| 130 | { | ||
| 131 | if (tlb_ops_need_broadcast()) { | ||
| 132 | struct tlb_args ta; | ||
| 133 | ta.ta_start = start; | ||
| 134 | ta.ta_end = end; | ||
| 135 | on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1); | ||
| 136 | } else | ||
| 137 | local_flush_tlb_kernel_range(start, end); | ||
| 138 | } | ||
| 139 | |||
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c index 35882fbf37f9..dd790745b3ef 100644 --- a/arch/arm/kernel/smp_twd.c +++ b/arch/arm/kernel/smp_twd.c | |||
| @@ -127,8 +127,6 @@ static void __cpuinit twd_calibrate_rate(void) | |||
| 127 | */ | 127 | */ |
| 128 | void __cpuinit twd_timer_setup(struct clock_event_device *clk) | 128 | void __cpuinit twd_timer_setup(struct clock_event_device *clk) |
| 129 | { | 129 | { |
| 130 | unsigned long flags; | ||
| 131 | |||
| 132 | twd_calibrate_rate(); | 130 | twd_calibrate_rate(); |
| 133 | 131 | ||
| 134 | clk->name = "local_timer"; | 132 | clk->name = "local_timer"; |
| @@ -143,20 +141,7 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk) | |||
| 143 | clk->min_delta_ns = clockevent_delta2ns(0xf, clk); | 141 | clk->min_delta_ns = clockevent_delta2ns(0xf, clk); |
| 144 | 142 | ||
| 145 | /* Make sure our local interrupt controller has this enabled */ | 143 | /* Make sure our local interrupt controller has this enabled */ |
| 146 | local_irq_save(flags); | 144 | gic_enable_ppi(clk->irq); |
| 147 | irq_to_desc(clk->irq)->status |= IRQ_NOPROBE; | ||
| 148 | get_irq_chip(clk->irq)->unmask(clk->irq); | ||
| 149 | local_irq_restore(flags); | ||
| 150 | 145 | ||
| 151 | clockevents_register_device(clk); | 146 | clockevents_register_device(clk); |
| 152 | } | 147 | } |
| 153 | |||
| 154 | #ifdef CONFIG_HOTPLUG_CPU | ||
| 155 | /* | ||
| 156 | * take a local timer down | ||
| 157 | */ | ||
| 158 | void twd_timer_stop(void) | ||
| 159 | { | ||
| 160 | __raw_writel(0, twd_base + TWD_TIMER_CONTROL); | ||
| 161 | } | ||
| 162 | #endif | ||
diff --git a/arch/arm/kernel/swp_emulate.c b/arch/arm/kernel/swp_emulate.c new file mode 100644 index 000000000000..7a5760922914 --- /dev/null +++ b/arch/arm/kernel/swp_emulate.c | |||
| @@ -0,0 +1,267 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/kernel/swp_emulate.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 ARM Limited | ||
| 5 | * __user_* functions adapted from include/asm/uaccess.h | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | * | ||
| 11 | * Implements emulation of the SWP/SWPB instructions using load-exclusive and | ||
| 12 | * store-exclusive for processors that have them disabled (or future ones that | ||
| 13 | * might not implement them). | ||
| 14 | * | ||
| 15 | * Syntax of SWP{B} instruction: SWP{B}<c> <Rt>, <Rt2>, [<Rn>] | ||
| 16 | * Where: Rt = destination | ||
| 17 | * Rt2 = source | ||
| 18 | * Rn = address | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include <linux/init.h> | ||
| 22 | #include <linux/kernel.h> | ||
| 23 | #include <linux/proc_fs.h> | ||
| 24 | #include <linux/sched.h> | ||
| 25 | #include <linux/syscalls.h> | ||
| 26 | #include <linux/perf_event.h> | ||
| 27 | |||
| 28 | #include <asm/traps.h> | ||
| 29 | #include <asm/uaccess.h> | ||
| 30 | |||
| 31 | /* | ||
| 32 | * Error-checking SWP macros implemented using ldrex{b}/strex{b} | ||
| 33 | */ | ||
| 34 | #define __user_swpX_asm(data, addr, res, temp, B) \ | ||
| 35 | __asm__ __volatile__( \ | ||
| 36 | " mov %2, %1\n" \ | ||
| 37 | "0: ldrex"B" %1, [%3]\n" \ | ||
| 38 | "1: strex"B" %0, %2, [%3]\n" \ | ||
| 39 | " cmp %0, #0\n" \ | ||
| 40 | " movne %0, %4\n" \ | ||
| 41 | "2:\n" \ | ||
| 42 | " .section .fixup,\"ax\"\n" \ | ||
| 43 | " .align 2\n" \ | ||
| 44 | "3: mov %0, %5\n" \ | ||
| 45 | " b 2b\n" \ | ||
| 46 | " .previous\n" \ | ||
| 47 | " .section __ex_table,\"a\"\n" \ | ||
| 48 | " .align 3\n" \ | ||
| 49 | " .long 0b, 3b\n" \ | ||
| 50 | " .long 1b, 3b\n" \ | ||
| 51 | " .previous" \ | ||
| 52 | : "=&r" (res), "+r" (data), "=&r" (temp) \ | ||
| 53 | : "r" (addr), "i" (-EAGAIN), "i" (-EFAULT) \ | ||
| 54 | : "cc", "memory") | ||
| 55 | |||
| 56 | #define __user_swp_asm(data, addr, res, temp) \ | ||
| 57 | __user_swpX_asm(data, addr, res, temp, "") | ||
| 58 | #define __user_swpb_asm(data, addr, res, temp) \ | ||
| 59 | __user_swpX_asm(data, addr, res, temp, "b") | ||
| 60 | |||
| 61 | /* | ||
| 62 | * Macros/defines for extracting register numbers from instruction. | ||
| 63 | */ | ||
| 64 | #define EXTRACT_REG_NUM(instruction, offset) \ | ||
| 65 | (((instruction) & (0xf << (offset))) >> (offset)) | ||
| 66 | #define RN_OFFSET 16 | ||
| 67 | #define RT_OFFSET 12 | ||
| 68 | #define RT2_OFFSET 0 | ||
| 69 | /* | ||
| 70 | * Bit 22 of the instruction encoding distinguishes between | ||
| 71 | * the SWP and SWPB variants (bit set means SWPB). | ||
| 72 | */ | ||
| 73 | #define TYPE_SWPB (1 << 22) | ||
| 74 | |||
| 75 | static unsigned long swpcounter; | ||
| 76 | static unsigned long swpbcounter; | ||
| 77 | static unsigned long abtcounter; | ||
| 78 | static pid_t previous_pid; | ||
| 79 | |||
| 80 | #ifdef CONFIG_PROC_FS | ||
| 81 | static int proc_read_status(char *page, char **start, off_t off, int count, | ||
| 82 | int *eof, void *data) | ||
| 83 | { | ||
| 84 | char *p = page; | ||
| 85 | int len; | ||
| 86 | |||
| 87 | p += sprintf(p, "Emulated SWP:\t\t%lu\n", swpcounter); | ||
| 88 | p += sprintf(p, "Emulated SWPB:\t\t%lu\n", swpbcounter); | ||
| 89 | p += sprintf(p, "Aborted SWP{B}:\t\t%lu\n", abtcounter); | ||
| 90 | if (previous_pid != 0) | ||
| 91 | p += sprintf(p, "Last process:\t\t%d\n", previous_pid); | ||
| 92 | |||
| 93 | len = (p - page) - off; | ||
| 94 | if (len < 0) | ||
| 95 | len = 0; | ||
| 96 | |||
| 97 | *eof = (len <= count) ? 1 : 0; | ||
| 98 | *start = page + off; | ||
| 99 | |||
| 100 | return len; | ||
| 101 | } | ||
| 102 | #endif | ||
| 103 | |||
| 104 | /* | ||
| 105 | * Set up process info to signal segmentation fault - called on access error. | ||
| 106 | */ | ||
| 107 | static void set_segfault(struct pt_regs *regs, unsigned long addr) | ||
| 108 | { | ||
| 109 | siginfo_t info; | ||
| 110 | |||
| 111 | if (find_vma(current->mm, addr) == NULL) | ||
| 112 | info.si_code = SEGV_MAPERR; | ||
| 113 | else | ||
| 114 | info.si_code = SEGV_ACCERR; | ||
| 115 | |||
| 116 | info.si_signo = SIGSEGV; | ||
| 117 | info.si_errno = 0; | ||
| 118 | info.si_addr = (void *) instruction_pointer(regs); | ||
| 119 | |||
| 120 | pr_debug("SWP{B} emulation: access caused memory abort!\n"); | ||
| 121 | arm_notify_die("Illegal memory access", regs, &info, 0, 0); | ||
| 122 | |||
| 123 | abtcounter++; | ||
| 124 | } | ||
| 125 | |||
| 126 | static int emulate_swpX(unsigned int address, unsigned int *data, | ||
| 127 | unsigned int type) | ||
| 128 | { | ||
| 129 | unsigned int res = 0; | ||
| 130 | |||
| 131 | if ((type != TYPE_SWPB) && (address & 0x3)) { | ||
| 132 | /* SWP to unaligned address not permitted */ | ||
| 133 | pr_debug("SWP instruction on unaligned pointer!\n"); | ||
| 134 | return -EFAULT; | ||
| 135 | } | ||
| 136 | |||
| 137 | while (1) { | ||
| 138 | unsigned long temp; | ||
| 139 | |||
| 140 | /* | ||
| 141 | * Barrier required between accessing protected resource and | ||
| 142 | * releasing a lock for it. Legacy code might not have done | ||
| 143 | * this, and we cannot determine that this is not the case | ||
| 144 | * being emulated, so insert always. | ||
| 145 | */ | ||
| 146 | smp_mb(); | ||
| 147 | |||
| 148 | if (type == TYPE_SWPB) | ||
| 149 | __user_swpb_asm(*data, address, res, temp); | ||
| 150 | else | ||
| 151 | __user_swp_asm(*data, address, res, temp); | ||
| 152 | |||
| 153 | if (likely(res != -EAGAIN) || signal_pending(current)) | ||
| 154 | break; | ||
| 155 | |||
| 156 | cond_resched(); | ||
| 157 | } | ||
| 158 | |||
| 159 | if (res == 0) { | ||
| 160 | /* | ||
| 161 | * Barrier also required between aquiring a lock for a | ||
| 162 | * protected resource and accessing the resource. Inserted for | ||
| 163 | * same reason as above. | ||
| 164 | */ | ||
| 165 | smp_mb(); | ||
| 166 | |||
| 167 | if (type == TYPE_SWPB) | ||
| 168 | swpbcounter++; | ||
| 169 | else | ||
| 170 | swpcounter++; | ||
| 171 | } | ||
| 172 | |||
| 173 | return res; | ||
| 174 | } | ||
| 175 | |||
| 176 | /* | ||
| 177 | * swp_handler logs the id of calling process, dissects the instruction, sanity | ||
| 178 | * checks the memory location, calls emulate_swpX for the actual operation and | ||
| 179 | * deals with fixup/error handling before returning | ||
| 180 | */ | ||
| 181 | static int swp_handler(struct pt_regs *regs, unsigned int instr) | ||
| 182 | { | ||
| 183 | unsigned int address, destreg, data, type; | ||
| 184 | unsigned int res = 0; | ||
| 185 | |||
| 186 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, regs, regs->ARM_pc); | ||
| 187 | |||
| 188 | if (current->pid != previous_pid) { | ||
| 189 | pr_debug("\"%s\" (%ld) uses deprecated SWP{B} instruction\n", | ||
| 190 | current->comm, (unsigned long)current->pid); | ||
| 191 | previous_pid = current->pid; | ||
| 192 | } | ||
| 193 | |||
| 194 | address = regs->uregs[EXTRACT_REG_NUM(instr, RN_OFFSET)]; | ||
| 195 | data = regs->uregs[EXTRACT_REG_NUM(instr, RT2_OFFSET)]; | ||
| 196 | destreg = EXTRACT_REG_NUM(instr, RT_OFFSET); | ||
| 197 | |||
| 198 | type = instr & TYPE_SWPB; | ||
| 199 | |||
| 200 | pr_debug("addr in r%d->0x%08x, dest is r%d, source in r%d->0x%08x)\n", | ||
| 201 | EXTRACT_REG_NUM(instr, RN_OFFSET), address, | ||
| 202 | destreg, EXTRACT_REG_NUM(instr, RT2_OFFSET), data); | ||
| 203 | |||
| 204 | /* Check access in reasonable access range for both SWP and SWPB */ | ||
| 205 | if (!access_ok(VERIFY_WRITE, (address & ~3), 4)) { | ||
| 206 | pr_debug("SWP{B} emulation: access to %p not allowed!\n", | ||
| 207 | (void *)address); | ||
| 208 | res = -EFAULT; | ||
| 209 | } else { | ||
| 210 | res = emulate_swpX(address, &data, type); | ||
| 211 | } | ||
| 212 | |||
| 213 | if (res == 0) { | ||
| 214 | /* | ||
| 215 | * On successful emulation, revert the adjustment to the PC | ||
| 216 | * made in kernel/traps.c in order to resume execution at the | ||
| 217 | * instruction following the SWP{B}. | ||
| 218 | */ | ||
| 219 | regs->ARM_pc += 4; | ||
| 220 | regs->uregs[destreg] = data; | ||
| 221 | } else if (res == -EFAULT) { | ||
| 222 | /* | ||
| 223 | * Memory errors do not mean emulation failed. | ||
| 224 | * Set up signal info to return SEGV, then return OK | ||
| 225 | */ | ||
| 226 | set_segfault(regs, address); | ||
| 227 | } | ||
| 228 | |||
| 229 | return 0; | ||
| 230 | } | ||
| 231 | |||
| 232 | /* | ||
| 233 | * Only emulate SWP/SWPB executed in ARM state/User mode. | ||
| 234 | * The kernel must be SWP free and SWP{B} does not exist in Thumb/ThumbEE. | ||
| 235 | */ | ||
| 236 | static struct undef_hook swp_hook = { | ||
| 237 | .instr_mask = 0x0fb00ff0, | ||
| 238 | .instr_val = 0x01000090, | ||
| 239 | .cpsr_mask = MODE_MASK | PSR_T_BIT | PSR_J_BIT, | ||
| 240 | .cpsr_val = USR_MODE, | ||
| 241 | .fn = swp_handler | ||
| 242 | }; | ||
| 243 | |||
| 244 | /* | ||
| 245 | * Register handler and create status file in /proc/cpu | ||
| 246 | * Invoked as late_initcall, since not needed before init spawned. | ||
| 247 | */ | ||
| 248 | static int __init swp_emulation_init(void) | ||
| 249 | { | ||
| 250 | #ifdef CONFIG_PROC_FS | ||
| 251 | struct proc_dir_entry *res; | ||
| 252 | |||
| 253 | res = create_proc_entry("cpu/swp_emulation", S_IRUGO, NULL); | ||
| 254 | |||
| 255 | if (!res) | ||
| 256 | return -ENOMEM; | ||
| 257 | |||
| 258 | res->read_proc = proc_read_status; | ||
| 259 | #endif /* CONFIG_PROC_FS */ | ||
| 260 | |||
| 261 | printk(KERN_NOTICE "Registering SWP/SWPB emulation handler\n"); | ||
| 262 | register_undef_hook(&swp_hook); | ||
| 263 | |||
| 264 | return 0; | ||
| 265 | } | ||
| 266 | |||
| 267 | late_initcall(swp_emulation_init); | ||
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c index 38c261f9951c..f1e2eb19a67d 100644 --- a/arch/arm/kernel/time.c +++ b/arch/arm/kernel/time.c | |||
| @@ -30,12 +30,13 @@ | |||
| 30 | #include <asm/leds.h> | 30 | #include <asm/leds.h> |
| 31 | #include <asm/thread_info.h> | 31 | #include <asm/thread_info.h> |
| 32 | #include <asm/stacktrace.h> | 32 | #include <asm/stacktrace.h> |
| 33 | #include <asm/mach/arch.h> | ||
| 33 | #include <asm/mach/time.h> | 34 | #include <asm/mach/time.h> |
| 34 | 35 | ||
| 35 | /* | 36 | /* |
| 36 | * Our system timer. | 37 | * Our system timer. |
| 37 | */ | 38 | */ |
| 38 | struct sys_timer *system_timer; | 39 | static struct sys_timer *system_timer; |
| 39 | 40 | ||
| 40 | #if defined(CONFIG_RTC_DRV_CMOS) || defined(CONFIG_RTC_DRV_CMOS_MODULE) | 41 | #if defined(CONFIG_RTC_DRV_CMOS) || defined(CONFIG_RTC_DRV_CMOS_MODULE) |
| 41 | /* this needs a better home */ | 42 | /* this needs a better home */ |
| @@ -160,6 +161,7 @@ device_initcall(timer_init_sysfs); | |||
| 160 | 161 | ||
| 161 | void __init time_init(void) | 162 | void __init time_init(void) |
| 162 | { | 163 | { |
| 164 | system_timer = machine_desc->timer; | ||
| 163 | system_timer->init(); | 165 | system_timer->init(); |
| 164 | } | 166 | } |
| 165 | 167 | ||
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 446aee97436f..ee57640ba2bb 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c | |||
| @@ -37,6 +37,8 @@ | |||
| 37 | 37 | ||
| 38 | static const char *handler[]= { "prefetch abort", "data abort", "address exception", "interrupt" }; | 38 | static const char *handler[]= { "prefetch abort", "data abort", "address exception", "interrupt" }; |
| 39 | 39 | ||
| 40 | void *vectors_page; | ||
| 41 | |||
| 40 | #ifdef CONFIG_DEBUG_USER | 42 | #ifdef CONFIG_DEBUG_USER |
| 41 | unsigned int user_debug; | 43 | unsigned int user_debug; |
| 42 | 44 | ||
| @@ -708,19 +710,19 @@ void __readwrite_bug(const char *fn) | |||
| 708 | } | 710 | } |
| 709 | EXPORT_SYMBOL(__readwrite_bug); | 711 | EXPORT_SYMBOL(__readwrite_bug); |
| 710 | 712 | ||
| 711 | void __pte_error(const char *file, int line, unsigned long val) | 713 | void __pte_error(const char *file, int line, pte_t pte) |
| 712 | { | 714 | { |
| 713 | printk("%s:%d: bad pte %08lx.\n", file, line, val); | 715 | printk("%s:%d: bad pte %08lx.\n", file, line, pte_val(pte)); |
| 714 | } | 716 | } |
| 715 | 717 | ||
| 716 | void __pmd_error(const char *file, int line, unsigned long val) | 718 | void __pmd_error(const char *file, int line, pmd_t pmd) |
| 717 | { | 719 | { |
| 718 | printk("%s:%d: bad pmd %08lx.\n", file, line, val); | 720 | printk("%s:%d: bad pmd %08lx.\n", file, line, pmd_val(pmd)); |
| 719 | } | 721 | } |
| 720 | 722 | ||
| 721 | void __pgd_error(const char *file, int line, unsigned long val) | 723 | void __pgd_error(const char *file, int line, pgd_t pgd) |
| 722 | { | 724 | { |
| 723 | printk("%s:%d: bad pgd %08lx.\n", file, line, val); | 725 | printk("%s:%d: bad pgd %08lx.\n", file, line, pgd_val(pgd)); |
| 724 | } | 726 | } |
| 725 | 727 | ||
| 726 | asmlinkage void __div0(void) | 728 | asmlinkage void __div0(void) |
| @@ -756,7 +758,11 @@ static void __init kuser_get_tls_init(unsigned long vectors) | |||
| 756 | 758 | ||
| 757 | void __init early_trap_init(void) | 759 | void __init early_trap_init(void) |
| 758 | { | 760 | { |
| 761 | #if defined(CONFIG_CPU_USE_DOMAINS) | ||
| 759 | unsigned long vectors = CONFIG_VECTORS_BASE; | 762 | unsigned long vectors = CONFIG_VECTORS_BASE; |
| 763 | #else | ||
| 764 | unsigned long vectors = (unsigned long)vectors_page; | ||
| 765 | #endif | ||
| 760 | extern char __stubs_start[], __stubs_end[]; | 766 | extern char __stubs_start[], __stubs_end[]; |
| 761 | extern char __vectors_start[], __vectors_end[]; | 767 | extern char __vectors_start[], __vectors_end[]; |
| 762 | extern char __kuser_helper_start[], __kuser_helper_end[]; | 768 | extern char __kuser_helper_start[], __kuser_helper_end[]; |
| @@ -780,10 +786,10 @@ void __init early_trap_init(void) | |||
| 780 | * Copy signal return handlers into the vector page, and | 786 | * Copy signal return handlers into the vector page, and |
| 781 | * set sigreturn to be a pointer to these. | 787 | * set sigreturn to be a pointer to these. |
| 782 | */ | 788 | */ |
| 783 | memcpy((void *)KERN_SIGRETURN_CODE, sigreturn_codes, | 789 | memcpy((void *)(vectors + KERN_SIGRETURN_CODE - CONFIG_VECTORS_BASE), |
| 784 | sizeof(sigreturn_codes)); | 790 | sigreturn_codes, sizeof(sigreturn_codes)); |
| 785 | memcpy((void *)KERN_RESTART_CODE, syscall_restart_code, | 791 | memcpy((void *)(vectors + KERN_RESTART_CODE - CONFIG_VECTORS_BASE), |
| 786 | sizeof(syscall_restart_code)); | 792 | syscall_restart_code, sizeof(syscall_restart_code)); |
| 787 | 793 | ||
| 788 | flush_icache_range(vectors, vectors + PAGE_SIZE); | 794 | flush_icache_range(vectors, vectors + PAGE_SIZE); |
| 789 | modify_domain(DOMAIN_USER, DOMAIN_CLIENT); | 795 | modify_domain(DOMAIN_USER, DOMAIN_CLIENT); |
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S index cead8893b46b..86b66f3f2031 100644 --- a/arch/arm/kernel/vmlinux.lds.S +++ b/arch/arm/kernel/vmlinux.lds.S | |||
| @@ -101,6 +101,7 @@ SECTIONS | |||
| 101 | __exception_text_start = .; | 101 | __exception_text_start = .; |
| 102 | *(.exception.text) | 102 | *(.exception.text) |
| 103 | __exception_text_end = .; | 103 | __exception_text_end = .; |
| 104 | IRQENTRY_TEXT | ||
| 104 | TEXT_TEXT | 105 | TEXT_TEXT |
| 105 | SCHED_TEXT | 106 | SCHED_TEXT |
| 106 | LOCK_TEXT | 107 | LOCK_TEXT |
| @@ -167,6 +168,7 @@ SECTIONS | |||
| 167 | 168 | ||
| 168 | NOSAVE_DATA | 169 | NOSAVE_DATA |
| 169 | CACHELINE_ALIGNED_DATA(32) | 170 | CACHELINE_ALIGNED_DATA(32) |
| 171 | READ_MOSTLY_DATA(32) | ||
| 170 | 172 | ||
| 171 | /* | 173 | /* |
| 172 | * The exception fixup table (might need resorting at runtime) | 174 | * The exception fixup table (might need resorting at runtime) |
diff --git a/arch/arm/lib/getuser.S b/arch/arm/lib/getuser.S index b1631a7dbe75..1b049cd7a49a 100644 --- a/arch/arm/lib/getuser.S +++ b/arch/arm/lib/getuser.S | |||
| @@ -28,20 +28,21 @@ | |||
| 28 | */ | 28 | */ |
| 29 | #include <linux/linkage.h> | 29 | #include <linux/linkage.h> |
| 30 | #include <asm/errno.h> | 30 | #include <asm/errno.h> |
| 31 | #include <asm/domain.h> | ||
| 31 | 32 | ||
| 32 | ENTRY(__get_user_1) | 33 | ENTRY(__get_user_1) |
| 33 | 1: ldrbt r2, [r0] | 34 | 1: T(ldrb) r2, [r0] |
| 34 | mov r0, #0 | 35 | mov r0, #0 |
| 35 | mov pc, lr | 36 | mov pc, lr |
| 36 | ENDPROC(__get_user_1) | 37 | ENDPROC(__get_user_1) |
| 37 | 38 | ||
| 38 | ENTRY(__get_user_2) | 39 | ENTRY(__get_user_2) |
| 39 | #ifdef CONFIG_THUMB2_KERNEL | 40 | #ifdef CONFIG_THUMB2_KERNEL |
| 40 | 2: ldrbt r2, [r0] | 41 | 2: T(ldrb) r2, [r0] |
| 41 | 3: ldrbt r3, [r0, #1] | 42 | 3: T(ldrb) r3, [r0, #1] |
| 42 | #else | 43 | #else |
| 43 | 2: ldrbt r2, [r0], #1 | 44 | 2: T(ldrb) r2, [r0], #1 |
| 44 | 3: ldrbt r3, [r0] | 45 | 3: T(ldrb) r3, [r0] |
| 45 | #endif | 46 | #endif |
| 46 | #ifndef __ARMEB__ | 47 | #ifndef __ARMEB__ |
| 47 | orr r2, r2, r3, lsl #8 | 48 | orr r2, r2, r3, lsl #8 |
| @@ -53,7 +54,7 @@ ENTRY(__get_user_2) | |||
| 53 | ENDPROC(__get_user_2) | 54 | ENDPROC(__get_user_2) |
| 54 | 55 | ||
| 55 | ENTRY(__get_user_4) | 56 | ENTRY(__get_user_4) |
| 56 | 4: ldrt r2, [r0] | 57 | 4: T(ldr) r2, [r0] |
| 57 | mov r0, #0 | 58 | mov r0, #0 |
| 58 | mov pc, lr | 59 | mov pc, lr |
| 59 | ENDPROC(__get_user_4) | 60 | ENDPROC(__get_user_4) |
diff --git a/arch/arm/lib/putuser.S b/arch/arm/lib/putuser.S index 5a01a23c6c06..c023fc11e86c 100644 --- a/arch/arm/lib/putuser.S +++ b/arch/arm/lib/putuser.S | |||
| @@ -28,9 +28,10 @@ | |||
| 28 | */ | 28 | */ |
| 29 | #include <linux/linkage.h> | 29 | #include <linux/linkage.h> |
| 30 | #include <asm/errno.h> | 30 | #include <asm/errno.h> |
| 31 | #include <asm/domain.h> | ||
| 31 | 32 | ||
| 32 | ENTRY(__put_user_1) | 33 | ENTRY(__put_user_1) |
| 33 | 1: strbt r2, [r0] | 34 | 1: T(strb) r2, [r0] |
| 34 | mov r0, #0 | 35 | mov r0, #0 |
| 35 | mov pc, lr | 36 | mov pc, lr |
| 36 | ENDPROC(__put_user_1) | 37 | ENDPROC(__put_user_1) |
| @@ -39,19 +40,19 @@ ENTRY(__put_user_2) | |||
| 39 | mov ip, r2, lsr #8 | 40 | mov ip, r2, lsr #8 |
| 40 | #ifdef CONFIG_THUMB2_KERNEL | 41 | #ifdef CONFIG_THUMB2_KERNEL |
| 41 | #ifndef __ARMEB__ | 42 | #ifndef __ARMEB__ |
| 42 | 2: strbt r2, [r0] | 43 | 2: T(strb) r2, [r0] |
| 43 | 3: strbt ip, [r0, #1] | 44 | 3: T(strb) ip, [r0, #1] |
| 44 | #else | 45 | #else |
| 45 | 2: strbt ip, [r0] | 46 | 2: T(strb) ip, [r0] |
| 46 | 3: strbt r2, [r0, #1] | 47 | 3: T(strb) r2, [r0, #1] |
| 47 | #endif | 48 | #endif |
| 48 | #else /* !CONFIG_THUMB2_KERNEL */ | 49 | #else /* !CONFIG_THUMB2_KERNEL */ |
| 49 | #ifndef __ARMEB__ | 50 | #ifndef __ARMEB__ |
| 50 | 2: strbt r2, [r0], #1 | 51 | 2: T(strb) r2, [r0], #1 |
| 51 | 3: strbt ip, [r0] | 52 | 3: T(strb) ip, [r0] |
| 52 | #else | 53 | #else |
| 53 | 2: strbt ip, [r0], #1 | 54 | 2: T(strb) ip, [r0], #1 |
| 54 | 3: strbt r2, [r0] | 55 | 3: T(strb) r2, [r0] |
| 55 | #endif | 56 | #endif |
| 56 | #endif /* CONFIG_THUMB2_KERNEL */ | 57 | #endif /* CONFIG_THUMB2_KERNEL */ |
| 57 | mov r0, #0 | 58 | mov r0, #0 |
| @@ -59,18 +60,18 @@ ENTRY(__put_user_2) | |||
| 59 | ENDPROC(__put_user_2) | 60 | ENDPROC(__put_user_2) |
| 60 | 61 | ||
| 61 | ENTRY(__put_user_4) | 62 | ENTRY(__put_user_4) |
| 62 | 4: strt r2, [r0] | 63 | 4: T(str) r2, [r0] |
| 63 | mov r0, #0 | 64 | mov r0, #0 |
| 64 | mov pc, lr | 65 | mov pc, lr |
| 65 | ENDPROC(__put_user_4) | 66 | ENDPROC(__put_user_4) |
| 66 | 67 | ||
| 67 | ENTRY(__put_user_8) | 68 | ENTRY(__put_user_8) |
| 68 | #ifdef CONFIG_THUMB2_KERNEL | 69 | #ifdef CONFIG_THUMB2_KERNEL |
| 69 | 5: strt r2, [r0] | 70 | 5: T(str) r2, [r0] |
| 70 | 6: strt r3, [r0, #4] | 71 | 6: T(str) r3, [r0, #4] |
| 71 | #else | 72 | #else |
| 72 | 5: strt r2, [r0], #4 | 73 | 5: T(str) r2, [r0], #4 |
| 73 | 6: strt r3, [r0] | 74 | 6: T(str) r3, [r0] |
| 74 | #endif | 75 | #endif |
| 75 | mov r0, #0 | 76 | mov r0, #0 |
| 76 | mov pc, lr | 77 | mov pc, lr |
diff --git a/arch/arm/lib/uaccess.S b/arch/arm/lib/uaccess.S index fee9f6f88adb..d0ece2aeb70d 100644 --- a/arch/arm/lib/uaccess.S +++ b/arch/arm/lib/uaccess.S | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | #include <linux/linkage.h> | 14 | #include <linux/linkage.h> |
| 15 | #include <asm/assembler.h> | 15 | #include <asm/assembler.h> |
| 16 | #include <asm/errno.h> | 16 | #include <asm/errno.h> |
| 17 | #include <asm/domain.h> | ||
| 17 | 18 | ||
| 18 | .text | 19 | .text |
| 19 | 20 | ||
| @@ -31,11 +32,11 @@ | |||
| 31 | rsb ip, ip, #4 | 32 | rsb ip, ip, #4 |
| 32 | cmp ip, #2 | 33 | cmp ip, #2 |
| 33 | ldrb r3, [r1], #1 | 34 | ldrb r3, [r1], #1 |
| 34 | USER( strbt r3, [r0], #1) @ May fault | 35 | USER( T(strb) r3, [r0], #1) @ May fault |
| 35 | ldrgeb r3, [r1], #1 | 36 | ldrgeb r3, [r1], #1 |
| 36 | USER( strgebt r3, [r0], #1) @ May fault | 37 | USER( T(strgeb) r3, [r0], #1) @ May fault |
| 37 | ldrgtb r3, [r1], #1 | 38 | ldrgtb r3, [r1], #1 |
| 38 | USER( strgtbt r3, [r0], #1) @ May fault | 39 | USER( T(strgtb) r3, [r0], #1) @ May fault |
| 39 | sub r2, r2, ip | 40 | sub r2, r2, ip |
| 40 | b .Lc2u_dest_aligned | 41 | b .Lc2u_dest_aligned |
| 41 | 42 | ||
| @@ -58,7 +59,7 @@ ENTRY(__copy_to_user) | |||
| 58 | addmi ip, r2, #4 | 59 | addmi ip, r2, #4 |
| 59 | bmi .Lc2u_0nowords | 60 | bmi .Lc2u_0nowords |
| 60 | ldr r3, [r1], #4 | 61 | ldr r3, [r1], #4 |
| 61 | USER( strt r3, [r0], #4) @ May fault | 62 | USER( T(str) r3, [r0], #4) @ May fault |
| 62 | mov ip, r0, lsl #32 - PAGE_SHIFT @ On each page, use a ld/st??t instruction | 63 | mov ip, r0, lsl #32 - PAGE_SHIFT @ On each page, use a ld/st??t instruction |
| 63 | rsb ip, ip, #0 | 64 | rsb ip, ip, #0 |
| 64 | movs ip, ip, lsr #32 - PAGE_SHIFT | 65 | movs ip, ip, lsr #32 - PAGE_SHIFT |
| @@ -87,18 +88,18 @@ USER( strt r3, [r0], #4) @ May fault | |||
| 87 | stmneia r0!, {r3 - r4} @ Shouldnt fault | 88 | stmneia r0!, {r3 - r4} @ Shouldnt fault |
| 88 | tst ip, #4 | 89 | tst ip, #4 |
| 89 | ldrne r3, [r1], #4 | 90 | ldrne r3, [r1], #4 |
| 90 | strnet r3, [r0], #4 @ Shouldnt fault | 91 | T(strne) r3, [r0], #4 @ Shouldnt fault |
| 91 | ands ip, ip, #3 | 92 | ands ip, ip, #3 |
| 92 | beq .Lc2u_0fupi | 93 | beq .Lc2u_0fupi |
| 93 | .Lc2u_0nowords: teq ip, #0 | 94 | .Lc2u_0nowords: teq ip, #0 |
| 94 | beq .Lc2u_finished | 95 | beq .Lc2u_finished |
| 95 | .Lc2u_nowords: cmp ip, #2 | 96 | .Lc2u_nowords: cmp ip, #2 |
| 96 | ldrb r3, [r1], #1 | 97 | ldrb r3, [r1], #1 |
| 97 | USER( strbt r3, [r0], #1) @ May fault | 98 | USER( T(strb) r3, [r0], #1) @ May fault |
| 98 | ldrgeb r3, [r1], #1 | 99 | ldrgeb r3, [r1], #1 |
| 99 | USER( strgebt r3, [r0], #1) @ May fault | 100 | USER( T(strgeb) r3, [r0], #1) @ May fault |
| 100 | ldrgtb r3, [r1], #1 | 101 | ldrgtb r3, [r1], #1 |
| 101 | USER( strgtbt r3, [r0], #1) @ May fault | 102 | USER( T(strgtb) r3, [r0], #1) @ May fault |
| 102 | b .Lc2u_finished | 103 | b .Lc2u_finished |
| 103 | 104 | ||
| 104 | .Lc2u_not_enough: | 105 | .Lc2u_not_enough: |
| @@ -119,7 +120,7 @@ USER( strgtbt r3, [r0], #1) @ May fault | |||
| 119 | mov r3, r7, pull #8 | 120 | mov r3, r7, pull #8 |
| 120 | ldr r7, [r1], #4 | 121 | ldr r7, [r1], #4 |
| 121 | orr r3, r3, r7, push #24 | 122 | orr r3, r3, r7, push #24 |
| 122 | USER( strt r3, [r0], #4) @ May fault | 123 | USER( T(str) r3, [r0], #4) @ May fault |
| 123 | mov ip, r0, lsl #32 - PAGE_SHIFT | 124 | mov ip, r0, lsl #32 - PAGE_SHIFT |
| 124 | rsb ip, ip, #0 | 125 | rsb ip, ip, #0 |
| 125 | movs ip, ip, lsr #32 - PAGE_SHIFT | 126 | movs ip, ip, lsr #32 - PAGE_SHIFT |
| @@ -154,18 +155,18 @@ USER( strt r3, [r0], #4) @ May fault | |||
| 154 | movne r3, r7, pull #8 | 155 | movne r3, r7, pull #8 |
| 155 | ldrne r7, [r1], #4 | 156 | ldrne r7, [r1], #4 |
| 156 | orrne r3, r3, r7, push #24 | 157 | orrne r3, r3, r7, push #24 |
| 157 | strnet r3, [r0], #4 @ Shouldnt fault | 158 | T(strne) r3, [r0], #4 @ Shouldnt fault |
| 158 | ands ip, ip, #3 | 159 | ands ip, ip, #3 |
| 159 | beq .Lc2u_1fupi | 160 | beq .Lc2u_1fupi |
| 160 | .Lc2u_1nowords: mov r3, r7, get_byte_1 | 161 | .Lc2u_1nowords: mov r3, r7, get_byte_1 |
| 161 | teq ip, #0 | 162 | teq ip, #0 |
| 162 | beq .Lc2u_finished | 163 | beq .Lc2u_finished |
| 163 | cmp ip, #2 | 164 | cmp ip, #2 |
| 164 | USER( strbt r3, [r0], #1) @ May fault | 165 | USER( T(strb) r3, [r0], #1) @ May fault |
| 165 | movge r3, r7, get_byte_2 | 166 | movge r3, r7, get_byte_2 |
| 166 | USER( strgebt r3, [r0], #1) @ May fault | 167 | USER( T(strgeb) r3, [r0], #1) @ May fault |
| 167 | movgt r3, r7, get_byte_3 | 168 | movgt r3, r7, get_byte_3 |
| 168 | USER( strgtbt r3, [r0], #1) @ May fault | 169 | USER( T(strgtb) r3, [r0], #1) @ May fault |
| 169 | b .Lc2u_finished | 170 | b .Lc2u_finished |
| 170 | 171 | ||
| 171 | .Lc2u_2fupi: subs r2, r2, #4 | 172 | .Lc2u_2fupi: subs r2, r2, #4 |
| @@ -174,7 +175,7 @@ USER( strgtbt r3, [r0], #1) @ May fault | |||
| 174 | mov r3, r7, pull #16 | 175 | mov r3, r7, pull #16 |
| 175 | ldr r7, [r1], #4 | 176 | ldr r7, [r1], #4 |
| 176 | orr r3, r3, r7, push #16 | 177 | orr r3, r3, r7, push #16 |
| 177 | USER( strt r3, [r0], #4) @ May fault | 178 | USER( T(str) r3, [r0], #4) @ May fault |
| 178 | mov ip, r0, lsl #32 - PAGE_SHIFT | 179 | mov ip, r0, lsl #32 - PAGE_SHIFT |
| 179 | rsb ip, ip, #0 | 180 | rsb ip, ip, #0 |
| 180 | movs ip, ip, lsr #32 - PAGE_SHIFT | 181 | movs ip, ip, lsr #32 - PAGE_SHIFT |
| @@ -209,18 +210,18 @@ USER( strt r3, [r0], #4) @ May fault | |||
| 209 | movne r3, r7, pull #16 | 210 | movne r3, r7, pull #16 |
| 210 | ldrne r7, [r1], #4 | 211 | ldrne r7, [r1], #4 |
| 211 | orrne r3, r3, r7, push #16 | 212 | orrne r3, r3, r7, push #16 |
| 212 | strnet r3, [r0], #4 @ Shouldnt fault | 213 | T(strne) r3, [r0], #4 @ Shouldnt fault |
| 213 | ands ip, ip, #3 | 214 | ands ip, ip, #3 |
| 214 | beq .Lc2u_2fupi | 215 | beq .Lc2u_2fupi |
| 215 | .Lc2u_2nowords: mov r3, r7, get_byte_2 | 216 | .Lc2u_2nowords: mov r3, r7, get_byte_2 |
| 216 | teq ip, #0 | 217 | teq ip, #0 |
| 217 | beq .Lc2u_finished | 218 | beq .Lc2u_finished |
| 218 | cmp ip, #2 | 219 | cmp ip, #2 |
| 219 | USER( strbt r3, [r0], #1) @ May fault | 220 | USER( T(strb) r3, [r0], #1) @ May fault |
| 220 | movge r3, r7, get_byte_3 | 221 | movge r3, r7, get_byte_3 |
| 221 | USER( strgebt r3, [r0], #1) @ May fault | 222 | USER( T(strgeb) r3, [r0], #1) @ May fault |
| 222 | ldrgtb r3, [r1], #0 | 223 | ldrgtb r3, [r1], #0 |
| 223 | USER( strgtbt r3, [r0], #1) @ May fault | 224 | USER( T(strgtb) r3, [r0], #1) @ May fault |
| 224 | b .Lc2u_finished | 225 | b .Lc2u_finished |
| 225 | 226 | ||
| 226 | .Lc2u_3fupi: subs r2, r2, #4 | 227 | .Lc2u_3fupi: subs r2, r2, #4 |
| @@ -229,7 +230,7 @@ USER( strgtbt r3, [r0], #1) @ May fault | |||
| 229 | mov r3, r7, pull #24 | 230 | mov r3, r7, pull #24 |
| 230 | ldr r7, [r1], #4 | 231 | ldr r7, [r1], #4 |
| 231 | orr r3, r3, r7, push #8 | 232 | orr r3, r3, r7, push #8 |
| 232 | USER( strt r3, [r0], #4) @ May fault | 233 | USER( T(str) r3, [r0], #4) @ May fault |
| 233 | mov ip, r0, lsl #32 - PAGE_SHIFT | 234 | mov ip, r0, lsl #32 - PAGE_SHIFT |
| 234 | rsb ip, ip, #0 | 235 | rsb ip, ip, #0 |
| 235 | movs ip, ip, lsr #32 - PAGE_SHIFT | 236 | movs ip, ip, lsr #32 - PAGE_SHIFT |
| @@ -264,18 +265,18 @@ USER( strt r3, [r0], #4) @ May fault | |||
| 264 | movne r3, r7, pull #24 | 265 | movne r3, r7, pull #24 |
| 265 | ldrne r7, [r1], #4 | 266 | ldrne r7, [r1], #4 |
| 266 | orrne r3, r3, r7, push #8 | 267 | orrne r3, r3, r7, push #8 |
| 267 | strnet r3, [r0], #4 @ Shouldnt fault | 268 | T(strne) r3, [r0], #4 @ Shouldnt fault |
| 268 | ands ip, ip, #3 | 269 | ands ip, ip, #3 |
| 269 | beq .Lc2u_3fupi | 270 | beq .Lc2u_3fupi |
| 270 | .Lc2u_3nowords: mov r3, r7, get_byte_3 | 271 | .Lc2u_3nowords: mov r3, r7, get_byte_3 |
| 271 | teq ip, #0 | 272 | teq ip, #0 |
| 272 | beq .Lc2u_finished | 273 | beq .Lc2u_finished |
| 273 | cmp ip, #2 | 274 | cmp ip, #2 |
| 274 | USER( strbt r3, [r0], #1) @ May fault | 275 | USER( T(strb) r3, [r0], #1) @ May fault |
| 275 | ldrgeb r3, [r1], #1 | 276 | ldrgeb r3, [r1], #1 |
| 276 | USER( strgebt r3, [r0], #1) @ May fault | 277 | USER( T(strgeb) r3, [r0], #1) @ May fault |
| 277 | ldrgtb r3, [r1], #0 | 278 | ldrgtb r3, [r1], #0 |
| 278 | USER( strgtbt r3, [r0], #1) @ May fault | 279 | USER( T(strgtb) r3, [r0], #1) @ May fault |
| 279 | b .Lc2u_finished | 280 | b .Lc2u_finished |
| 280 | ENDPROC(__copy_to_user) | 281 | ENDPROC(__copy_to_user) |
| 281 | 282 | ||
| @@ -294,11 +295,11 @@ ENDPROC(__copy_to_user) | |||
| 294 | .Lcfu_dest_not_aligned: | 295 | .Lcfu_dest_not_aligned: |
| 295 | rsb ip, ip, #4 | 296 | rsb ip, ip, #4 |
| 296 | cmp ip, #2 | 297 | cmp ip, #2 |
| 297 | USER( ldrbt r3, [r1], #1) @ May fault | 298 | USER( T(ldrb) r3, [r1], #1) @ May fault |
| 298 | strb r3, [r0], #1 | 299 | strb r3, [r0], #1 |
| 299 | USER( ldrgebt r3, [r1], #1) @ May fault | 300 | USER( T(ldrgeb) r3, [r1], #1) @ May fault |
| 300 | strgeb r3, [r0], #1 | 301 | strgeb r3, [r0], #1 |
| 301 | USER( ldrgtbt r3, [r1], #1) @ May fault | 302 | USER( T(ldrgtb) r3, [r1], #1) @ May fault |
| 302 | strgtb r3, [r0], #1 | 303 | strgtb r3, [r0], #1 |
| 303 | sub r2, r2, ip | 304 | sub r2, r2, ip |
| 304 | b .Lcfu_dest_aligned | 305 | b .Lcfu_dest_aligned |
| @@ -321,7 +322,7 @@ ENTRY(__copy_from_user) | |||
| 321 | .Lcfu_0fupi: subs r2, r2, #4 | 322 | .Lcfu_0fupi: subs r2, r2, #4 |
| 322 | addmi ip, r2, #4 | 323 | addmi ip, r2, #4 |
| 323 | bmi .Lcfu_0nowords | 324 | bmi .Lcfu_0nowords |
| 324 | USER( ldrt r3, [r1], #4) | 325 | USER( T(ldr) r3, [r1], #4) |
| 325 | str r3, [r0], #4 | 326 | str r3, [r0], #4 |
| 326 | mov ip, r1, lsl #32 - PAGE_SHIFT @ On each page, use a ld/st??t instruction | 327 | mov ip, r1, lsl #32 - PAGE_SHIFT @ On each page, use a ld/st??t instruction |
| 327 | rsb ip, ip, #0 | 328 | rsb ip, ip, #0 |
| @@ -350,18 +351,18 @@ USER( ldrt r3, [r1], #4) | |||
| 350 | ldmneia r1!, {r3 - r4} @ Shouldnt fault | 351 | ldmneia r1!, {r3 - r4} @ Shouldnt fault |
| 351 | stmneia r0!, {r3 - r4} | 352 | stmneia r0!, {r3 - r4} |
| 352 | tst ip, #4 | 353 | tst ip, #4 |
| 353 | ldrnet r3, [r1], #4 @ Shouldnt fault | 354 | T(ldrne) r3, [r1], #4 @ Shouldnt fault |
| 354 | strne r3, [r0], #4 | 355 | strne r3, [r0], #4 |
| 355 | ands ip, ip, #3 | 356 | ands ip, ip, #3 |
| 356 | beq .Lcfu_0fupi | 357 | beq .Lcfu_0fupi |
| 357 | .Lcfu_0nowords: teq ip, #0 | 358 | .Lcfu_0nowords: teq ip, #0 |
| 358 | beq .Lcfu_finished | 359 | beq .Lcfu_finished |
| 359 | .Lcfu_nowords: cmp ip, #2 | 360 | .Lcfu_nowords: cmp ip, #2 |
| 360 | USER( ldrbt r3, [r1], #1) @ May fault | 361 | USER( T(ldrb) r3, [r1], #1) @ May fault |
| 361 | strb r3, [r0], #1 | 362 | strb r3, [r0], #1 |
| 362 | USER( ldrgebt r3, [r1], #1) @ May fault | 363 | USER( T(ldrgeb) r3, [r1], #1) @ May fault |
| 363 | strgeb r3, [r0], #1 | 364 | strgeb r3, [r0], #1 |
| 364 | USER( ldrgtbt r3, [r1], #1) @ May fault | 365 | USER( T(ldrgtb) r3, [r1], #1) @ May fault |
| 365 | strgtb r3, [r0], #1 | 366 | strgtb r3, [r0], #1 |
| 366 | b .Lcfu_finished | 367 | b .Lcfu_finished |
| 367 | 368 | ||
| @@ -374,7 +375,7 @@ USER( ldrgtbt r3, [r1], #1) @ May fault | |||
| 374 | 375 | ||
| 375 | .Lcfu_src_not_aligned: | 376 | .Lcfu_src_not_aligned: |
| 376 | bic r1, r1, #3 | 377 | bic r1, r1, #3 |
| 377 | USER( ldrt r7, [r1], #4) @ May fault | 378 | USER( T(ldr) r7, [r1], #4) @ May fault |
| 378 | cmp ip, #2 | 379 | cmp ip, #2 |
| 379 | bgt .Lcfu_3fupi | 380 | bgt .Lcfu_3fupi |
| 380 | beq .Lcfu_2fupi | 381 | beq .Lcfu_2fupi |
| @@ -382,7 +383,7 @@ USER( ldrt r7, [r1], #4) @ May fault | |||
| 382 | addmi ip, r2, #4 | 383 | addmi ip, r2, #4 |
| 383 | bmi .Lcfu_1nowords | 384 | bmi .Lcfu_1nowords |
| 384 | mov r3, r7, pull #8 | 385 | mov r3, r7, pull #8 |
| 385 | USER( ldrt r7, [r1], #4) @ May fault | 386 | USER( T(ldr) r7, [r1], #4) @ May fault |
| 386 | orr r3, r3, r7, push #24 | 387 | orr r3, r3, r7, push #24 |
| 387 | str r3, [r0], #4 | 388 | str r3, [r0], #4 |
| 388 | mov ip, r1, lsl #32 - PAGE_SHIFT | 389 | mov ip, r1, lsl #32 - PAGE_SHIFT |
| @@ -417,7 +418,7 @@ USER( ldrt r7, [r1], #4) @ May fault | |||
| 417 | stmneia r0!, {r3 - r4} | 418 | stmneia r0!, {r3 - r4} |
| 418 | tst ip, #4 | 419 | tst ip, #4 |
| 419 | movne r3, r7, pull #8 | 420 | movne r3, r7, pull #8 |
| 420 | USER( ldrnet r7, [r1], #4) @ May fault | 421 | USER( T(ldrne) r7, [r1], #4) @ May fault |
| 421 | orrne r3, r3, r7, push #24 | 422 | orrne r3, r3, r7, push #24 |
| 422 | strne r3, [r0], #4 | 423 | strne r3, [r0], #4 |
| 423 | ands ip, ip, #3 | 424 | ands ip, ip, #3 |
| @@ -437,7 +438,7 @@ USER( ldrnet r7, [r1], #4) @ May fault | |||
| 437 | addmi ip, r2, #4 | 438 | addmi ip, r2, #4 |
| 438 | bmi .Lcfu_2nowords | 439 | bmi .Lcfu_2nowords |
| 439 | mov r3, r7, pull #16 | 440 | mov r3, r7, pull #16 |
| 440 | USER( ldrt r7, [r1], #4) @ May fault | 441 | USER( T(ldr) r7, [r1], #4) @ May fault |
| 441 | orr r3, r3, r7, push #16 | 442 | orr r3, r3, r7, push #16 |
| 442 | str r3, [r0], #4 | 443 | str r3, [r0], #4 |
| 443 | mov ip, r1, lsl #32 - PAGE_SHIFT | 444 | mov ip, r1, lsl #32 - PAGE_SHIFT |
| @@ -473,7 +474,7 @@ USER( ldrt r7, [r1], #4) @ May fault | |||
| 473 | stmneia r0!, {r3 - r4} | 474 | stmneia r0!, {r3 - r4} |
| 474 | tst ip, #4 | 475 | tst ip, #4 |
| 475 | movne r3, r7, pull #16 | 476 | movne r3, r7, pull #16 |
| 476 | USER( ldrnet r7, [r1], #4) @ May fault | 477 | USER( T(ldrne) r7, [r1], #4) @ May fault |
| 477 | orrne r3, r3, r7, push #16 | 478 | orrne r3, r3, r7, push #16 |
| 478 | strne r3, [r0], #4 | 479 | strne r3, [r0], #4 |
| 479 | ands ip, ip, #3 | 480 | ands ip, ip, #3 |
| @@ -485,7 +486,7 @@ USER( ldrnet r7, [r1], #4) @ May fault | |||
| 485 | strb r3, [r0], #1 | 486 | strb r3, [r0], #1 |
| 486 | movge r3, r7, get_byte_3 | 487 | movge r3, r7, get_byte_3 |
| 487 | strgeb r3, [r0], #1 | 488 | strgeb r3, [r0], #1 |
| 488 | USER( ldrgtbt r3, [r1], #0) @ May fault | 489 | USER( T(ldrgtb) r3, [r1], #0) @ May fault |
| 489 | strgtb r3, [r0], #1 | 490 | strgtb r3, [r0], #1 |
| 490 | b .Lcfu_finished | 491 | b .Lcfu_finished |
| 491 | 492 | ||
| @@ -493,7 +494,7 @@ USER( ldrgtbt r3, [r1], #0) @ May fault | |||
| 493 | addmi ip, r2, #4 | 494 | addmi ip, r2, #4 |
| 494 | bmi .Lcfu_3nowords | 495 | bmi .Lcfu_3nowords |
| 495 | mov r3, r7, pull #24 | 496 | mov r3, r7, pull #24 |
| 496 | USER( ldrt r7, [r1], #4) @ May fault | 497 | USER( T(ldr) r7, [r1], #4) @ May fault |
| 497 | orr r3, r3, r7, push #8 | 498 | orr r3, r3, r7, push #8 |
| 498 | str r3, [r0], #4 | 499 | str r3, [r0], #4 |
| 499 | mov ip, r1, lsl #32 - PAGE_SHIFT | 500 | mov ip, r1, lsl #32 - PAGE_SHIFT |
| @@ -528,7 +529,7 @@ USER( ldrt r7, [r1], #4) @ May fault | |||
| 528 | stmneia r0!, {r3 - r4} | 529 | stmneia r0!, {r3 - r4} |
| 529 | tst ip, #4 | 530 | tst ip, #4 |
| 530 | movne r3, r7, pull #24 | 531 | movne r3, r7, pull #24 |
| 531 | USER( ldrnet r7, [r1], #4) @ May fault | 532 | USER( T(ldrne) r7, [r1], #4) @ May fault |
| 532 | orrne r3, r3, r7, push #8 | 533 | orrne r3, r3, r7, push #8 |
| 533 | strne r3, [r0], #4 | 534 | strne r3, [r0], #4 |
| 534 | ands ip, ip, #3 | 535 | ands ip, ip, #3 |
| @@ -538,9 +539,9 @@ USER( ldrnet r7, [r1], #4) @ May fault | |||
| 538 | beq .Lcfu_finished | 539 | beq .Lcfu_finished |
| 539 | cmp ip, #2 | 540 | cmp ip, #2 |
| 540 | strb r3, [r0], #1 | 541 | strb r3, [r0], #1 |
| 541 | USER( ldrgebt r3, [r1], #1) @ May fault | 542 | USER( T(ldrgeb) r3, [r1], #1) @ May fault |
| 542 | strgeb r3, [r0], #1 | 543 | strgeb r3, [r0], #1 |
| 543 | USER( ldrgtbt r3, [r1], #1) @ May fault | 544 | USER( T(ldrgtb) r3, [r1], #1) @ May fault |
| 544 | strgtb r3, [r0], #1 | 545 | strgtb r3, [r0], #1 |
| 545 | b .Lcfu_finished | 546 | b .Lcfu_finished |
| 546 | ENDPROC(__copy_from_user) | 547 | ENDPROC(__copy_from_user) |
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c index 2500f41d8d2d..1dd69c85dfec 100644 --- a/arch/arm/mach-at91/at91rm9200_time.c +++ b/arch/arm/mach-at91/at91rm9200_time.c | |||
| @@ -101,7 +101,6 @@ static struct clocksource clk32k = { | |||
| 101 | .rating = 150, | 101 | .rating = 150, |
| 102 | .read = read_clk32k, | 102 | .read = read_clk32k, |
| 103 | .mask = CLOCKSOURCE_MASK(20), | 103 | .mask = CLOCKSOURCE_MASK(20), |
| 104 | .shift = 10, | ||
| 105 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 104 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 106 | }; | 105 | }; |
| 107 | 106 | ||
| @@ -201,8 +200,7 @@ void __init at91rm9200_timer_init(void) | |||
| 201 | clockevents_register_device(&clkevt); | 200 | clockevents_register_device(&clkevt); |
| 202 | 201 | ||
| 203 | /* register clocksource */ | 202 | /* register clocksource */ |
| 204 | clk32k.mult = clocksource_hz2mult(AT91_SLOW_CLOCK, clk32k.shift); | 203 | clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK); |
| 205 | clocksource_register(&clk32k); | ||
| 206 | } | 204 | } |
| 207 | 205 | ||
| 208 | struct sys_timer at91rm9200_timer = { | 206 | struct sys_timer at91rm9200_timer = { |
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c index 608a63240b64..4ba85499fa97 100644 --- a/arch/arm/mach-at91/at91sam926x_time.c +++ b/arch/arm/mach-at91/at91sam926x_time.c | |||
| @@ -51,7 +51,6 @@ static struct clocksource pit_clk = { | |||
| 51 | .name = "pit", | 51 | .name = "pit", |
| 52 | .rating = 175, | 52 | .rating = 175, |
| 53 | .read = read_pit_clk, | 53 | .read = read_pit_clk, |
| 54 | .shift = 20, | ||
| 55 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 54 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 56 | }; | 55 | }; |
| 57 | 56 | ||
| @@ -163,10 +162,9 @@ static void __init at91sam926x_pit_init(void) | |||
| 163 | * Register clocksource. The high order bits of PIV are unused, | 162 | * Register clocksource. The high order bits of PIV are unused, |
| 164 | * so this isn't a 32-bit counter unless we get clockevent irqs. | 163 | * so this isn't a 32-bit counter unless we get clockevent irqs. |
| 165 | */ | 164 | */ |
| 166 | pit_clk.mult = clocksource_hz2mult(pit_rate, pit_clk.shift); | ||
| 167 | bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */; | 165 | bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */; |
| 168 | pit_clk.mask = CLOCKSOURCE_MASK(bits); | 166 | pit_clk.mask = CLOCKSOURCE_MASK(bits); |
| 169 | clocksource_register(&pit_clk); | 167 | clocksource_register_hz(&pit_clk, pit_rate); |
| 170 | 168 | ||
| 171 | /* Set up irq handler */ | 169 | /* Set up irq handler */ |
| 172 | setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq); | 170 | setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq); |
diff --git a/arch/arm/mach-bcmring/clock.c b/arch/arm/mach-bcmring/clock.c index 14bafc38f2dc..ad237a42d265 100644 --- a/arch/arm/mach-bcmring/clock.c +++ b/arch/arm/mach-bcmring/clock.c | |||
| @@ -21,13 +21,12 @@ | |||
| 21 | #include <linux/string.h> | 21 | #include <linux/string.h> |
| 22 | #include <linux/clk.h> | 22 | #include <linux/clk.h> |
| 23 | #include <linux/spinlock.h> | 23 | #include <linux/spinlock.h> |
| 24 | #include <linux/clkdev.h> | ||
| 24 | #include <mach/csp/hw_cfg.h> | 25 | #include <mach/csp/hw_cfg.h> |
| 25 | #include <mach/csp/chipcHw_def.h> | 26 | #include <mach/csp/chipcHw_def.h> |
| 26 | #include <mach/csp/chipcHw_reg.h> | 27 | #include <mach/csp/chipcHw_reg.h> |
| 27 | #include <mach/csp/chipcHw_inline.h> | 28 | #include <mach/csp/chipcHw_inline.h> |
| 28 | 29 | ||
| 29 | #include <asm/clkdev.h> | ||
| 30 | |||
| 31 | #include "clock.h" | 30 | #include "clock.h" |
| 32 | 31 | ||
| 33 | #define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY) | 32 | #define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY) |
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c index d3f959e92b2d..8fc2035759fb 100644 --- a/arch/arm/mach-bcmring/core.c +++ b/arch/arm/mach-bcmring/core.c | |||
| @@ -30,10 +30,10 @@ | |||
| 30 | #include <linux/amba/bus.h> | 30 | #include <linux/amba/bus.h> |
| 31 | #include <linux/clocksource.h> | 31 | #include <linux/clocksource.h> |
| 32 | #include <linux/clockchips.h> | 32 | #include <linux/clockchips.h> |
| 33 | #include <linux/clkdev.h> | ||
| 33 | 34 | ||
| 34 | #include <mach/csp/mm_addr.h> | 35 | #include <mach/csp/mm_addr.h> |
| 35 | #include <mach/hardware.h> | 36 | #include <mach/hardware.h> |
| 36 | #include <asm/clkdev.h> | ||
| 37 | #include <linux/io.h> | 37 | #include <linux/io.h> |
| 38 | #include <asm/irq.h> | 38 | #include <asm/irq.h> |
| 39 | #include <asm/hardware/arm_timer.h> | 39 | #include <asm/hardware/arm_timer.h> |
| @@ -294,7 +294,6 @@ static struct clocksource clocksource_bcmring_timer1 = { | |||
| 294 | .rating = 200, | 294 | .rating = 200, |
| 295 | .read = bcmring_get_cycles_timer1, | 295 | .read = bcmring_get_cycles_timer1, |
| 296 | .mask = CLOCKSOURCE_MASK(32), | 296 | .mask = CLOCKSOURCE_MASK(32), |
| 297 | .shift = 20, | ||
| 298 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 297 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 299 | }; | 298 | }; |
| 300 | 299 | ||
| @@ -303,7 +302,6 @@ static struct clocksource clocksource_bcmring_timer3 = { | |||
| 303 | .rating = 100, | 302 | .rating = 100, |
| 304 | .read = bcmring_get_cycles_timer3, | 303 | .read = bcmring_get_cycles_timer3, |
| 305 | .mask = CLOCKSOURCE_MASK(32), | 304 | .mask = CLOCKSOURCE_MASK(32), |
| 306 | .shift = 20, | ||
| 307 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 305 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 308 | }; | 306 | }; |
| 309 | 307 | ||
| @@ -316,10 +314,8 @@ static int __init bcmring_clocksource_init(void) | |||
| 316 | writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, | 314 | writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, |
| 317 | TIMER1_VA_BASE + TIMER_CTRL); | 315 | TIMER1_VA_BASE + TIMER_CTRL); |
| 318 | 316 | ||
| 319 | clocksource_bcmring_timer1.mult = | 317 | clocksource_register_khz(&clocksource_bcmring_timer1, |
| 320 | clocksource_khz2mult(TIMER1_FREQUENCY_MHZ * 1000, | 318 | TIMER1_FREQUENCY_MHZ * 1000); |
| 321 | clocksource_bcmring_timer1.shift); | ||
| 322 | clocksource_register(&clocksource_bcmring_timer1); | ||
| 323 | 319 | ||
| 324 | /* setup timer3 as free-running clocksource */ | 320 | /* setup timer3 as free-running clocksource */ |
| 325 | writel(0, TIMER3_VA_BASE + TIMER_CTRL); | 321 | writel(0, TIMER3_VA_BASE + TIMER_CTRL); |
| @@ -328,10 +324,8 @@ static int __init bcmring_clocksource_init(void) | |||
| 328 | writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, | 324 | writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, |
| 329 | TIMER3_VA_BASE + TIMER_CTRL); | 325 | TIMER3_VA_BASE + TIMER_CTRL); |
| 330 | 326 | ||
| 331 | clocksource_bcmring_timer3.mult = | 327 | clocksource_register_khz(&clocksource_bcmring_timer3, |
| 332 | clocksource_khz2mult(TIMER3_FREQUENCY_KHZ, | 328 | TIMER3_FREQUENCY_KHZ); |
| 333 | clocksource_bcmring_timer3.shift); | ||
| 334 | clocksource_register(&clocksource_bcmring_timer3); | ||
| 335 | 329 | ||
| 336 | return 0; | 330 | return 0; |
| 337 | } | 331 | } |
diff --git a/arch/arm/mach-cns3xxx/Kconfig b/arch/arm/mach-cns3xxx/Kconfig index 9ebfcc46feb1..29b13f249aa9 100644 --- a/arch/arm/mach-cns3xxx/Kconfig +++ b/arch/arm/mach-cns3xxx/Kconfig | |||
| @@ -3,6 +3,7 @@ menu "CNS3XXX platform type" | |||
| 3 | 3 | ||
| 4 | config MACH_CNS3420VB | 4 | config MACH_CNS3420VB |
| 5 | bool "Support for CNS3420 Validation Board" | 5 | bool "Support for CNS3420 Validation Board" |
| 6 | select MIGHT_HAVE_PCI | ||
| 6 | help | 7 | help |
| 7 | Include support for the Cavium Networks CNS3420 MPCore Platform | 8 | Include support for the Cavium Networks CNS3420 MPCore Platform |
| 8 | Baseboard. | 9 | Baseboard. |
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c index 90fe9ab8591d..08e5c8759502 100644 --- a/arch/arm/mach-cns3xxx/cns3420vb.c +++ b/arch/arm/mach-cns3xxx/cns3420vb.c | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | #include <linux/kernel.h> | 17 | #include <linux/kernel.h> |
| 18 | #include <linux/compiler.h> | 18 | #include <linux/compiler.h> |
| 19 | #include <linux/io.h> | 19 | #include <linux/io.h> |
| 20 | #include <linux/dma-mapping.h> | ||
| 20 | #include <linux/serial_core.h> | 21 | #include <linux/serial_core.h> |
| 21 | #include <linux/serial_8250.h> | 22 | #include <linux/serial_8250.h> |
| 22 | #include <linux/platform_device.h> | 23 | #include <linux/platform_device.h> |
| @@ -108,10 +109,63 @@ static void __init cns3420_early_serial_setup(void) | |||
| 108 | } | 109 | } |
| 109 | 110 | ||
| 110 | /* | 111 | /* |
| 112 | * USB | ||
| 113 | */ | ||
| 114 | static struct resource cns3xxx_usb_ehci_resources[] = { | ||
| 115 | [0] = { | ||
| 116 | .start = CNS3XXX_USB_BASE, | ||
| 117 | .end = CNS3XXX_USB_BASE + SZ_16M - 1, | ||
| 118 | .flags = IORESOURCE_MEM, | ||
| 119 | }, | ||
| 120 | [1] = { | ||
| 121 | .start = IRQ_CNS3XXX_USB_EHCI, | ||
| 122 | .flags = IORESOURCE_IRQ, | ||
| 123 | }, | ||
| 124 | }; | ||
| 125 | |||
| 126 | static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32); | ||
| 127 | |||
| 128 | static struct platform_device cns3xxx_usb_ehci_device = { | ||
| 129 | .name = "cns3xxx-ehci", | ||
| 130 | .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources), | ||
| 131 | .resource = cns3xxx_usb_ehci_resources, | ||
| 132 | .dev = { | ||
| 133 | .dma_mask = &cns3xxx_usb_ehci_dma_mask, | ||
| 134 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 135 | }, | ||
| 136 | }; | ||
| 137 | |||
| 138 | static struct resource cns3xxx_usb_ohci_resources[] = { | ||
| 139 | [0] = { | ||
| 140 | .start = CNS3XXX_USB_OHCI_BASE, | ||
| 141 | .end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1, | ||
| 142 | .flags = IORESOURCE_MEM, | ||
| 143 | }, | ||
| 144 | [1] = { | ||
| 145 | .start = IRQ_CNS3XXX_USB_OHCI, | ||
| 146 | .flags = IORESOURCE_IRQ, | ||
| 147 | }, | ||
| 148 | }; | ||
| 149 | |||
| 150 | static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32); | ||
| 151 | |||
| 152 | static struct platform_device cns3xxx_usb_ohci_device = { | ||
| 153 | .name = "cns3xxx-ohci", | ||
| 154 | .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources), | ||
| 155 | .resource = cns3xxx_usb_ohci_resources, | ||
| 156 | .dev = { | ||
| 157 | .dma_mask = &cns3xxx_usb_ohci_dma_mask, | ||
| 158 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 159 | }, | ||
| 160 | }; | ||
| 161 | |||
| 162 | /* | ||
| 111 | * Initialization | 163 | * Initialization |
| 112 | */ | 164 | */ |
| 113 | static struct platform_device *cns3420_pdevs[] __initdata = { | 165 | static struct platform_device *cns3420_pdevs[] __initdata = { |
| 114 | &cns3420_nor_pdev, | 166 | &cns3420_nor_pdev, |
| 167 | &cns3xxx_usb_ehci_device, | ||
| 168 | &cns3xxx_usb_ohci_device, | ||
| 115 | }; | 169 | }; |
| 116 | 170 | ||
| 117 | static void __init cns3420_init(void) | 171 | static void __init cns3420_init(void) |
diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c index 9ca4d581016f..da30078a80c1 100644 --- a/arch/arm/mach-cns3xxx/core.c +++ b/arch/arm/mach-cns3xxx/core.c | |||
| @@ -69,13 +69,10 @@ void __init cns3xxx_map_io(void) | |||
| 69 | } | 69 | } |
| 70 | 70 | ||
| 71 | /* used by entry-macro.S */ | 71 | /* used by entry-macro.S */ |
| 72 | void __iomem *gic_cpu_base_addr; | ||
| 73 | |||
| 74 | void __init cns3xxx_init_irq(void) | 72 | void __init cns3xxx_init_irq(void) |
| 75 | { | 73 | { |
| 76 | gic_cpu_base_addr = __io(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT); | 74 | gic_init(0, 29, __io(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT), |
| 77 | gic_dist_init(0, __io(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT), 29); | 75 | __io(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT)); |
| 78 | gic_cpu_init(0, gic_cpu_base_addr); | ||
| 79 | } | 76 | } |
| 80 | 77 | ||
| 81 | void cns3xxx_power_off(void) | 78 | void cns3xxx_power_off(void) |
diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h index 6b33ec11346e..ffeb3a8b73ba 100644 --- a/arch/arm/mach-cns3xxx/core.h +++ b/arch/arm/mach-cns3xxx/core.h | |||
| @@ -11,13 +11,10 @@ | |||
| 11 | #ifndef __CNS3XXX_CORE_H | 11 | #ifndef __CNS3XXX_CORE_H |
| 12 | #define __CNS3XXX_CORE_H | 12 | #define __CNS3XXX_CORE_H |
| 13 | 13 | ||
| 14 | extern void __iomem *gic_cpu_base_addr; | ||
| 15 | extern struct sys_timer cns3xxx_timer; | 14 | extern struct sys_timer cns3xxx_timer; |
| 16 | 15 | ||
| 17 | void __init cns3xxx_map_io(void); | 16 | void __init cns3xxx_map_io(void); |
| 18 | void __init cns3xxx_init_irq(void); | 17 | void __init cns3xxx_init_irq(void); |
| 19 | void cns3xxx_power_off(void); | 18 | void cns3xxx_power_off(void); |
| 20 | void cns3xxx_pwr_power_up(unsigned int block); | ||
| 21 | void cns3xxx_pwr_power_down(unsigned int block); | ||
| 22 | 19 | ||
| 23 | #endif /* __CNS3XXX_CORE_H */ | 20 | #endif /* __CNS3XXX_CORE_H */ |
diff --git a/arch/arm/mach-cns3xxx/devices.c b/arch/arm/mach-cns3xxx/devices.c index 50b4d31c27c0..79d1fb02c23f 100644 --- a/arch/arm/mach-cns3xxx/devices.c +++ b/arch/arm/mach-cns3xxx/devices.c | |||
| @@ -18,6 +18,7 @@ | |||
| 18 | #include <linux/platform_device.h> | 18 | #include <linux/platform_device.h> |
| 19 | #include <mach/cns3xxx.h> | 19 | #include <mach/cns3xxx.h> |
| 20 | #include <mach/irqs.h> | 20 | #include <mach/irqs.h> |
| 21 | #include <mach/pm.h> | ||
| 21 | #include "core.h" | 22 | #include "core.h" |
| 22 | #include "devices.h" | 23 | #include "devices.h" |
| 23 | 24 | ||
diff --git a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h index 6dbce13771ca..191c8e57f289 100644 --- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h +++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h | |||
| @@ -165,7 +165,6 @@ | |||
| 165 | #define CNS3XXX_USBOTG_BASE_VIRT 0xFFF15000 | 165 | #define CNS3XXX_USBOTG_BASE_VIRT 0xFFF15000 |
| 166 | 166 | ||
| 167 | #define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */ | 167 | #define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */ |
| 168 | #define CNS3XXX_USB_BASE_VIRT 0xFFF16000 | ||
| 169 | 168 | ||
| 170 | #define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */ | 169 | #define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */ |
| 171 | #define CNS3XXX_SATA2_SIZE SZ_16M | 170 | #define CNS3XXX_SATA2_SIZE SZ_16M |
| @@ -184,7 +183,6 @@ | |||
| 184 | #define CNS3XXX_2DG_BASE_VIRT 0xFFF1B000 | 183 | #define CNS3XXX_2DG_BASE_VIRT 0xFFF1B000 |
| 185 | 184 | ||
| 186 | #define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */ | 185 | #define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */ |
| 187 | #define CNS3XXX_USB_OHCI_BASE_VIRT 0xFFF1C000 | ||
| 188 | 186 | ||
| 189 | #define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */ | 187 | #define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */ |
| 190 | #define CNS3XXX_L2C_BASE_VIRT 0xFFF27000 | 188 | #define CNS3XXX_L2C_BASE_VIRT 0xFFF27000 |
diff --git a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S index 5e1c5545680f..6bd83ed90afe 100644 --- a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S +++ b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S | |||
| @@ -9,74 +9,10 @@ | |||
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | #include <mach/hardware.h> | 11 | #include <mach/hardware.h> |
| 12 | #include <asm/hardware/gic.h> | 12 | #include <asm/hardware/entry-macro-gic.S> |
| 13 | 13 | ||
| 14 | .macro disable_fiq | 14 | .macro disable_fiq |
| 15 | .endm | 15 | .endm |
| 16 | 16 | ||
| 17 | .macro get_irqnr_preamble, base, tmp | ||
| 18 | ldr \base, =gic_cpu_base_addr | ||
| 19 | ldr \base, [\base] | ||
| 20 | .endm | ||
| 21 | |||
| 22 | .macro arch_ret_to_user, tmp1, tmp2 | 17 | .macro arch_ret_to_user, tmp1, tmp2 |
| 23 | .endm | 18 | .endm |
| 24 | |||
| 25 | /* | ||
| 26 | * The interrupt numbering scheme is defined in the | ||
| 27 | * interrupt controller spec. To wit: | ||
| 28 | * | ||
| 29 | * Interrupts 0-15 are IPI | ||
| 30 | * 16-28 are reserved | ||
| 31 | * 29-31 are local. We allow 30 to be used for the watchdog. | ||
| 32 | * 32-1020 are global | ||
| 33 | * 1021-1022 are reserved | ||
| 34 | * 1023 is "spurious" (no interrupt) | ||
| 35 | * | ||
| 36 | * For now, we ignore all local interrupts so only return an interrupt if it's | ||
| 37 | * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs. | ||
| 38 | * | ||
| 39 | * A simple read from the controller will tell us the number of the highest | ||
| 40 | * priority enabled interrupt. We then just need to check whether it is in the | ||
| 41 | * valid range for an IRQ (30-1020 inclusive). | ||
| 42 | */ | ||
| 43 | |||
| 44 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 45 | |||
| 46 | ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */ | ||
| 47 | |||
| 48 | ldr \tmp, =1021 | ||
| 49 | |||
| 50 | bic \irqnr, \irqstat, #0x1c00 | ||
| 51 | |||
| 52 | cmp \irqnr, #29 | ||
| 53 | cmpcc \irqnr, \irqnr | ||
| 54 | cmpne \irqnr, \tmp | ||
| 55 | cmpcs \irqnr, \irqnr | ||
| 56 | |||
| 57 | .endm | ||
| 58 | |||
| 59 | /* We assume that irqstat (the raw value of the IRQ acknowledge | ||
| 60 | * register) is preserved from the macro above. | ||
| 61 | * If there is an IPI, we immediately signal end of interrupt on the | ||
| 62 | * controller, since this requires the original irqstat value which | ||
| 63 | * we won't easily be able to recreate later. | ||
| 64 | */ | ||
| 65 | |||
| 66 | .macro test_for_ipi, irqnr, irqstat, base, tmp | ||
| 67 | bic \irqnr, \irqstat, #0x1c00 | ||
| 68 | cmp \irqnr, #16 | ||
| 69 | strcc \irqstat, [\base, #GIC_CPU_EOI] | ||
| 70 | cmpcs \irqnr, \irqnr | ||
| 71 | .endm | ||
| 72 | |||
| 73 | /* As above, this assumes that irqstat and base are preserved.. */ | ||
| 74 | |||
| 75 | .macro test_for_ltirq, irqnr, irqstat, base, tmp | ||
| 76 | bic \irqnr, \irqstat, #0x1c00 | ||
| 77 | mov \tmp, #0 | ||
| 78 | cmp \irqnr, #29 | ||
| 79 | moveq \tmp, #1 | ||
| 80 | streq \irqstat, [\base, #GIC_CPU_EOI] | ||
| 81 | cmp \tmp, #0 | ||
| 82 | .endm | ||
diff --git a/arch/arm/mach-cns3xxx/include/mach/pm.h b/arch/arm/mach-cns3xxx/include/mach/pm.h new file mode 100644 index 000000000000..6eae7f764d1d --- /dev/null +++ b/arch/arm/mach-cns3xxx/include/mach/pm.h | |||
| @@ -0,0 +1,23 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2000 Deep Blue Solutions Ltd | ||
| 3 | * Copyright 2004 ARM Limited | ||
| 4 | * Copyright 2008 Cavium Networks | ||
| 5 | * | ||
| 6 | * This file is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License, Version 2, as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __CNS3XXX_PM_H | ||
| 12 | #define __CNS3XXX_PM_H | ||
| 13 | |||
| 14 | #include <asm/atomic.h> | ||
| 15 | |||
| 16 | void cns3xxx_pwr_clk_en(unsigned int block); | ||
| 17 | void cns3xxx_pwr_clk_dis(unsigned int block); | ||
| 18 | void cns3xxx_pwr_power_up(unsigned int block); | ||
| 19 | void cns3xxx_pwr_power_down(unsigned int block); | ||
| 20 | |||
| 21 | extern atomic_t usb_pwr_ref; | ||
| 22 | |||
| 23 | #endif /* __CNS3XXX_PM_H */ | ||
diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c index 38e44706feab..5e579552aa54 100644 --- a/arch/arm/mach-cns3xxx/pm.c +++ b/arch/arm/mach-cns3xxx/pm.c | |||
| @@ -6,10 +6,14 @@ | |||
| 6 | * published by the Free Software Foundation. | 6 | * published by the Free Software Foundation. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | #include <linux/init.h> | ||
| 10 | #include <linux/module.h> | ||
| 9 | #include <linux/io.h> | 11 | #include <linux/io.h> |
| 10 | #include <linux/delay.h> | 12 | #include <linux/delay.h> |
| 13 | #include <asm/atomic.h> | ||
| 11 | #include <mach/system.h> | 14 | #include <mach/system.h> |
| 12 | #include <mach/cns3xxx.h> | 15 | #include <mach/cns3xxx.h> |
| 16 | #include <mach/pm.h> | ||
| 13 | 17 | ||
| 14 | void cns3xxx_pwr_clk_en(unsigned int block) | 18 | void cns3xxx_pwr_clk_en(unsigned int block) |
| 15 | { | 19 | { |
| @@ -18,6 +22,16 @@ void cns3xxx_pwr_clk_en(unsigned int block) | |||
| 18 | reg |= (block & PM_CLK_GATE_REG_MASK); | 22 | reg |= (block & PM_CLK_GATE_REG_MASK); |
| 19 | __raw_writel(reg, PM_CLK_GATE_REG); | 23 | __raw_writel(reg, PM_CLK_GATE_REG); |
| 20 | } | 24 | } |
| 25 | EXPORT_SYMBOL(cns3xxx_pwr_clk_en); | ||
| 26 | |||
| 27 | void cns3xxx_pwr_clk_dis(unsigned int block) | ||
| 28 | { | ||
| 29 | u32 reg = __raw_readl(PM_CLK_GATE_REG); | ||
| 30 | |||
| 31 | reg &= ~(block & PM_CLK_GATE_REG_MASK); | ||
| 32 | __raw_writel(reg, PM_CLK_GATE_REG); | ||
| 33 | } | ||
| 34 | EXPORT_SYMBOL(cns3xxx_pwr_clk_dis); | ||
| 21 | 35 | ||
| 22 | void cns3xxx_pwr_power_up(unsigned int block) | 36 | void cns3xxx_pwr_power_up(unsigned int block) |
| 23 | { | 37 | { |
| @@ -29,6 +43,7 @@ void cns3xxx_pwr_power_up(unsigned int block) | |||
| 29 | /* Wait for 300us for the PLL output clock locked. */ | 43 | /* Wait for 300us for the PLL output clock locked. */ |
| 30 | udelay(300); | 44 | udelay(300); |
| 31 | }; | 45 | }; |
| 46 | EXPORT_SYMBOL(cns3xxx_pwr_power_up); | ||
| 32 | 47 | ||
| 33 | void cns3xxx_pwr_power_down(unsigned int block) | 48 | void cns3xxx_pwr_power_down(unsigned int block) |
| 34 | { | 49 | { |
| @@ -38,6 +53,7 @@ void cns3xxx_pwr_power_down(unsigned int block) | |||
| 38 | reg |= (block & CNS3XXX_PWR_PLL_ALL); | 53 | reg |= (block & CNS3XXX_PWR_PLL_ALL); |
| 39 | __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG); | 54 | __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG); |
| 40 | }; | 55 | }; |
| 56 | EXPORT_SYMBOL(cns3xxx_pwr_power_down); | ||
| 41 | 57 | ||
| 42 | static void cns3xxx_pwr_soft_rst_force(unsigned int block) | 58 | static void cns3xxx_pwr_soft_rst_force(unsigned int block) |
| 43 | { | 59 | { |
| @@ -51,11 +67,13 @@ static void cns3xxx_pwr_soft_rst_force(unsigned int block) | |||
| 51 | reg &= ~(block & PM_SOFT_RST_REG_MASK); | 67 | reg &= ~(block & PM_SOFT_RST_REG_MASK); |
| 52 | } else { | 68 | } else { |
| 53 | reg &= ~(block & PM_SOFT_RST_REG_MASK); | 69 | reg &= ~(block & PM_SOFT_RST_REG_MASK); |
| 70 | __raw_writel(reg, PM_SOFT_RST_REG); | ||
| 54 | reg |= (block & PM_SOFT_RST_REG_MASK); | 71 | reg |= (block & PM_SOFT_RST_REG_MASK); |
| 55 | } | 72 | } |
| 56 | 73 | ||
| 57 | __raw_writel(reg, PM_SOFT_RST_REG); | 74 | __raw_writel(reg, PM_SOFT_RST_REG); |
| 58 | } | 75 | } |
| 76 | EXPORT_SYMBOL(cns3xxx_pwr_soft_rst_force); | ||
| 59 | 77 | ||
| 60 | void cns3xxx_pwr_soft_rst(unsigned int block) | 78 | void cns3xxx_pwr_soft_rst(unsigned int block) |
| 61 | { | 79 | { |
| @@ -69,6 +87,7 @@ void cns3xxx_pwr_soft_rst(unsigned int block) | |||
| 69 | } | 87 | } |
| 70 | cns3xxx_pwr_soft_rst_force(block); | 88 | cns3xxx_pwr_soft_rst_force(block); |
| 71 | } | 89 | } |
| 90 | EXPORT_SYMBOL(cns3xxx_pwr_soft_rst); | ||
| 72 | 91 | ||
| 73 | void arch_reset(char mode, const char *cmd) | 92 | void arch_reset(char mode, const char *cmd) |
| 74 | { | 93 | { |
| @@ -99,3 +118,7 @@ int cns3xxx_cpu_clock(void) | |||
| 99 | 118 | ||
| 100 | return cpu; | 119 | return cpu; |
| 101 | } | 120 | } |
| 121 | EXPORT_SYMBOL(cns3xxx_cpu_clock); | ||
| 122 | |||
| 123 | atomic_t usb_pwr_ref = ATOMIC_INIT(0); | ||
| 124 | EXPORT_SYMBOL(usb_pwr_ref); | ||
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index b77b860b36d7..32f147998cd9 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig | |||
| @@ -61,6 +61,8 @@ config MACH_DAVINCI_EVM | |||
| 61 | bool "TI DM644x EVM" | 61 | bool "TI DM644x EVM" |
| 62 | default ARCH_DAVINCI_DM644x | 62 | default ARCH_DAVINCI_DM644x |
| 63 | depends on ARCH_DAVINCI_DM644x | 63 | depends on ARCH_DAVINCI_DM644x |
| 64 | select MISC_DEVICES | ||
| 65 | select EEPROM_AT24 | ||
| 64 | help | 66 | help |
| 65 | Configure this option to specify the whether the board used | 67 | Configure this option to specify the whether the board used |
| 66 | for development is a DM644x EVM | 68 | for development is a DM644x EVM |
| @@ -68,6 +70,8 @@ config MACH_DAVINCI_EVM | |||
| 68 | config MACH_SFFSDR | 70 | config MACH_SFFSDR |
| 69 | bool "Lyrtech SFFSDR" | 71 | bool "Lyrtech SFFSDR" |
| 70 | depends on ARCH_DAVINCI_DM644x | 72 | depends on ARCH_DAVINCI_DM644x |
| 73 | select MISC_DEVICES | ||
| 74 | select EEPROM_AT24 | ||
| 71 | help | 75 | help |
| 72 | Say Y here to select the Lyrtech Small Form Factor | 76 | Say Y here to select the Lyrtech Small Form Factor |
| 73 | Software Defined Radio (SFFSDR) board. | 77 | Software Defined Radio (SFFSDR) board. |
| @@ -99,6 +103,8 @@ config MACH_DAVINCI_DM6467_EVM | |||
| 99 | default ARCH_DAVINCI_DM646x | 103 | default ARCH_DAVINCI_DM646x |
| 100 | depends on ARCH_DAVINCI_DM646x | 104 | depends on ARCH_DAVINCI_DM646x |
| 101 | select MACH_DAVINCI_DM6467TEVM | 105 | select MACH_DAVINCI_DM6467TEVM |
| 106 | select MISC_DEVICES | ||
| 107 | select EEPROM_AT24 | ||
| 102 | help | 108 | help |
| 103 | Configure this option to specify the whether the board used | 109 | Configure this option to specify the whether the board used |
| 104 | for development is a DM6467 EVM | 110 | for development is a DM6467 EVM |
| @@ -110,6 +116,8 @@ config MACH_DAVINCI_DM365_EVM | |||
| 110 | bool "TI DM365 EVM" | 116 | bool "TI DM365 EVM" |
| 111 | default ARCH_DAVINCI_DM365 | 117 | default ARCH_DAVINCI_DM365 |
| 112 | depends on ARCH_DAVINCI_DM365 | 118 | depends on ARCH_DAVINCI_DM365 |
| 119 | select MISC_DEVICES | ||
| 120 | select EEPROM_AT24 | ||
| 113 | help | 121 | help |
| 114 | Configure this option to specify whether the board used | 122 | Configure this option to specify whether the board used |
| 115 | for development is a DM365 EVM | 123 | for development is a DM365 EVM |
| @@ -119,6 +127,8 @@ config MACH_DAVINCI_DA830_EVM | |||
| 119 | default ARCH_DAVINCI_DA830 | 127 | default ARCH_DAVINCI_DA830 |
| 120 | depends on ARCH_DAVINCI_DA830 | 128 | depends on ARCH_DAVINCI_DA830 |
| 121 | select GPIO_PCF857X | 129 | select GPIO_PCF857X |
| 130 | select MISC_DEVICES | ||
| 131 | select EEPROM_AT24 | ||
| 122 | help | 132 | help |
| 123 | Say Y here to select the TI DA830/OMAP-L137/AM17x Evaluation Module. | 133 | Say Y here to select the TI DA830/OMAP-L137/AM17x Evaluation Module. |
| 124 | 134 | ||
| @@ -148,7 +158,6 @@ config MACH_DAVINCI_DA850_EVM | |||
| 148 | bool "TI DA850/OMAP-L138/AM18x Reference Platform" | 158 | bool "TI DA850/OMAP-L138/AM18x Reference Platform" |
| 149 | default ARCH_DAVINCI_DA850 | 159 | default ARCH_DAVINCI_DA850 |
| 150 | depends on ARCH_DAVINCI_DA850 | 160 | depends on ARCH_DAVINCI_DA850 |
| 151 | select GPIO_PCA953X | ||
| 152 | help | 161 | help |
| 153 | Say Y here to select the TI DA850/OMAP-L138/AM18x Evaluation Module. | 162 | Say Y here to select the TI DA850/OMAP-L138/AM18x Evaluation Module. |
| 154 | 163 | ||
| @@ -178,6 +187,12 @@ config DA850_UI_RMII | |||
| 178 | 187 | ||
| 179 | endchoice | 188 | endchoice |
| 180 | 189 | ||
| 190 | config GPIO_PCA953X | ||
| 191 | default MACH_DAVINCI_DA850_EVM | ||
| 192 | |||
| 193 | config KEYBOARD_GPIO_POLLED | ||
| 194 | default MACH_DAVINCI_DA850_EVM | ||
| 195 | |||
| 181 | config MACH_TNETV107X | 196 | config MACH_TNETV107X |
| 182 | bool "TI TNETV107X Reference Platform" | 197 | bool "TI TNETV107X Reference Platform" |
| 183 | default ARCH_DAVINCI_TNETV107X | 198 | default ARCH_DAVINCI_TNETV107X |
| @@ -188,6 +203,8 @@ config MACH_TNETV107X | |||
| 188 | config MACH_MITYOMAPL138 | 203 | config MACH_MITYOMAPL138 |
| 189 | bool "Critical Link MityDSP-L138/MityARM-1808 SoM" | 204 | bool "Critical Link MityDSP-L138/MityARM-1808 SoM" |
| 190 | depends on ARCH_DAVINCI_DA850 | 205 | depends on ARCH_DAVINCI_DA850 |
| 206 | select MISC_DEVICES | ||
| 207 | select EEPROM_AT24 | ||
| 191 | help | 208 | help |
| 192 | Say Y here to select the Critical Link MityDSP-L138/MityARM-1808 | 209 | Say Y here to select the Critical Link MityDSP-L138/MityARM-1808 |
| 193 | System on Module. Information on this SoM may be found at | 210 | System on Module. Information on this SoM may be found at |
diff --git a/arch/arm/mach-davinci/aemif.c b/arch/arm/mach-davinci/aemif.c index 9c3f500fc12f..1ce70a91f2e9 100644 --- a/arch/arm/mach-davinci/aemif.c +++ b/arch/arm/mach-davinci/aemif.c | |||
| @@ -90,7 +90,7 @@ int davinci_aemif_setup_timing(struct davinci_aemif_timing *t, | |||
| 90 | void __iomem *base, unsigned cs) | 90 | void __iomem *base, unsigned cs) |
| 91 | { | 91 | { |
| 92 | unsigned set, val; | 92 | unsigned set, val; |
| 93 | unsigned ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup; | 93 | int ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup; |
| 94 | unsigned offset = A1CR_OFFSET + cs * 4; | 94 | unsigned offset = A1CR_OFFSET + cs * 4; |
| 95 | struct clk *aemif_clk; | 95 | struct clk *aemif_clk; |
| 96 | unsigned long clkrate; | 96 | unsigned long clkrate; |
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index c6e11c682e4c..b01fb2ab944a 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c | |||
| @@ -17,8 +17,10 @@ | |||
| 17 | #include <linux/i2c.h> | 17 | #include <linux/i2c.h> |
| 18 | #include <linux/i2c/at24.h> | 18 | #include <linux/i2c/at24.h> |
| 19 | #include <linux/i2c/pca953x.h> | 19 | #include <linux/i2c/pca953x.h> |
| 20 | #include <linux/input.h> | ||
| 20 | #include <linux/mfd/tps6507x.h> | 21 | #include <linux/mfd/tps6507x.h> |
| 21 | #include <linux/gpio.h> | 22 | #include <linux/gpio.h> |
| 23 | #include <linux/gpio_keys.h> | ||
| 22 | #include <linux/platform_device.h> | 24 | #include <linux/platform_device.h> |
| 23 | #include <linux/mtd/mtd.h> | 25 | #include <linux/mtd/mtd.h> |
| 24 | #include <linux/mtd/nand.h> | 26 | #include <linux/mtd/nand.h> |
| @@ -266,34 +268,115 @@ static inline void da850_evm_setup_emac_rmii(int rmii_sel) | |||
| 266 | struct davinci_soc_info *soc_info = &davinci_soc_info; | 268 | struct davinci_soc_info *soc_info = &davinci_soc_info; |
| 267 | 269 | ||
| 268 | soc_info->emac_pdata->rmii_en = 1; | 270 | soc_info->emac_pdata->rmii_en = 1; |
| 269 | gpio_set_value(rmii_sel, 0); | 271 | gpio_set_value_cansleep(rmii_sel, 0); |
| 270 | } | 272 | } |
| 271 | #else | 273 | #else |
| 272 | static inline void da850_evm_setup_emac_rmii(int rmii_sel) { } | 274 | static inline void da850_evm_setup_emac_rmii(int rmii_sel) { } |
| 273 | #endif | 275 | #endif |
| 274 | 276 | ||
| 277 | |||
| 278 | #define DA850_KEYS_DEBOUNCE_MS 10 | ||
| 279 | /* | ||
| 280 | * At 200ms polling interval it is possible to miss an | ||
| 281 | * event by tapping very lightly on the push button but most | ||
| 282 | * pushes do result in an event; longer intervals require the | ||
| 283 | * user to hold the button whereas shorter intervals require | ||
| 284 | * more CPU time for polling. | ||
| 285 | */ | ||
| 286 | #define DA850_GPIO_KEYS_POLL_MS 200 | ||
| 287 | |||
| 288 | enum da850_evm_ui_exp_pins { | ||
| 289 | DA850_EVM_UI_EXP_SEL_C = 5, | ||
| 290 | DA850_EVM_UI_EXP_SEL_B, | ||
| 291 | DA850_EVM_UI_EXP_SEL_A, | ||
| 292 | DA850_EVM_UI_EXP_PB8, | ||
| 293 | DA850_EVM_UI_EXP_PB7, | ||
| 294 | DA850_EVM_UI_EXP_PB6, | ||
| 295 | DA850_EVM_UI_EXP_PB5, | ||
| 296 | DA850_EVM_UI_EXP_PB4, | ||
| 297 | DA850_EVM_UI_EXP_PB3, | ||
| 298 | DA850_EVM_UI_EXP_PB2, | ||
| 299 | DA850_EVM_UI_EXP_PB1, | ||
| 300 | }; | ||
| 301 | |||
| 302 | static const char const *da850_evm_ui_exp[] = { | ||
| 303 | [DA850_EVM_UI_EXP_SEL_C] = "sel_c", | ||
| 304 | [DA850_EVM_UI_EXP_SEL_B] = "sel_b", | ||
| 305 | [DA850_EVM_UI_EXP_SEL_A] = "sel_a", | ||
| 306 | [DA850_EVM_UI_EXP_PB8] = "pb8", | ||
| 307 | [DA850_EVM_UI_EXP_PB7] = "pb7", | ||
| 308 | [DA850_EVM_UI_EXP_PB6] = "pb6", | ||
| 309 | [DA850_EVM_UI_EXP_PB5] = "pb5", | ||
| 310 | [DA850_EVM_UI_EXP_PB4] = "pb4", | ||
| 311 | [DA850_EVM_UI_EXP_PB3] = "pb3", | ||
| 312 | [DA850_EVM_UI_EXP_PB2] = "pb2", | ||
| 313 | [DA850_EVM_UI_EXP_PB1] = "pb1", | ||
| 314 | }; | ||
| 315 | |||
| 316 | #define DA850_N_UI_PB 8 | ||
| 317 | |||
| 318 | static struct gpio_keys_button da850_evm_ui_keys[] = { | ||
| 319 | [0 ... DA850_N_UI_PB - 1] = { | ||
| 320 | .type = EV_KEY, | ||
| 321 | .active_low = 1, | ||
| 322 | .wakeup = 0, | ||
| 323 | .debounce_interval = DA850_KEYS_DEBOUNCE_MS, | ||
| 324 | .code = -1, /* assigned at runtime */ | ||
| 325 | .gpio = -1, /* assigned at runtime */ | ||
| 326 | .desc = NULL, /* assigned at runtime */ | ||
| 327 | }, | ||
| 328 | }; | ||
| 329 | |||
| 330 | static struct gpio_keys_platform_data da850_evm_ui_keys_pdata = { | ||
| 331 | .buttons = da850_evm_ui_keys, | ||
| 332 | .nbuttons = ARRAY_SIZE(da850_evm_ui_keys), | ||
| 333 | .poll_interval = DA850_GPIO_KEYS_POLL_MS, | ||
| 334 | }; | ||
| 335 | |||
| 336 | static struct platform_device da850_evm_ui_keys_device = { | ||
| 337 | .name = "gpio-keys-polled", | ||
| 338 | .id = 0, | ||
| 339 | .dev = { | ||
| 340 | .platform_data = &da850_evm_ui_keys_pdata | ||
| 341 | }, | ||
| 342 | }; | ||
| 343 | |||
| 344 | static void da850_evm_ui_keys_init(unsigned gpio) | ||
| 345 | { | ||
| 346 | int i; | ||
| 347 | struct gpio_keys_button *button; | ||
| 348 | |||
| 349 | for (i = 0; i < DA850_N_UI_PB; i++) { | ||
| 350 | button = &da850_evm_ui_keys[i]; | ||
| 351 | button->code = KEY_F8 - i; | ||
| 352 | button->desc = (char *) | ||
| 353 | da850_evm_ui_exp[DA850_EVM_UI_EXP_PB8 + i]; | ||
| 354 | button->gpio = gpio + DA850_EVM_UI_EXP_PB8 + i; | ||
| 355 | } | ||
| 356 | } | ||
| 357 | |||
| 275 | static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio, | 358 | static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio, |
| 276 | unsigned ngpio, void *c) | 359 | unsigned ngpio, void *c) |
| 277 | { | 360 | { |
| 278 | int sel_a, sel_b, sel_c, ret; | 361 | int sel_a, sel_b, sel_c, ret; |
| 279 | 362 | ||
| 280 | sel_a = gpio + 7; | 363 | sel_a = gpio + DA850_EVM_UI_EXP_SEL_A; |
| 281 | sel_b = gpio + 6; | 364 | sel_b = gpio + DA850_EVM_UI_EXP_SEL_B; |
| 282 | sel_c = gpio + 5; | 365 | sel_c = gpio + DA850_EVM_UI_EXP_SEL_C; |
| 283 | 366 | ||
| 284 | ret = gpio_request(sel_a, "sel_a"); | 367 | ret = gpio_request(sel_a, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_A]); |
| 285 | if (ret) { | 368 | if (ret) { |
| 286 | pr_warning("Cannot open UI expander pin %d\n", sel_a); | 369 | pr_warning("Cannot open UI expander pin %d\n", sel_a); |
| 287 | goto exp_setup_sela_fail; | 370 | goto exp_setup_sela_fail; |
| 288 | } | 371 | } |
| 289 | 372 | ||
| 290 | ret = gpio_request(sel_b, "sel_b"); | 373 | ret = gpio_request(sel_b, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_B]); |
| 291 | if (ret) { | 374 | if (ret) { |
| 292 | pr_warning("Cannot open UI expander pin %d\n", sel_b); | 375 | pr_warning("Cannot open UI expander pin %d\n", sel_b); |
| 293 | goto exp_setup_selb_fail; | 376 | goto exp_setup_selb_fail; |
| 294 | } | 377 | } |
| 295 | 378 | ||
| 296 | ret = gpio_request(sel_c, "sel_c"); | 379 | ret = gpio_request(sel_c, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_C]); |
| 297 | if (ret) { | 380 | if (ret) { |
| 298 | pr_warning("Cannot open UI expander pin %d\n", sel_c); | 381 | pr_warning("Cannot open UI expander pin %d\n", sel_c); |
| 299 | goto exp_setup_selc_fail; | 382 | goto exp_setup_selc_fail; |
| @@ -304,6 +387,13 @@ static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio, | |||
| 304 | gpio_direction_output(sel_b, 1); | 387 | gpio_direction_output(sel_b, 1); |
| 305 | gpio_direction_output(sel_c, 1); | 388 | gpio_direction_output(sel_c, 1); |
| 306 | 389 | ||
| 390 | da850_evm_ui_keys_init(gpio); | ||
| 391 | ret = platform_device_register(&da850_evm_ui_keys_device); | ||
| 392 | if (ret) { | ||
| 393 | pr_warning("Could not register UI GPIO expander push-buttons"); | ||
| 394 | goto exp_setup_keys_fail; | ||
| 395 | } | ||
| 396 | |||
| 307 | ui_card_detected = 1; | 397 | ui_card_detected = 1; |
| 308 | pr_info("DA850/OMAP-L138 EVM UI card detected\n"); | 398 | pr_info("DA850/OMAP-L138 EVM UI card detected\n"); |
| 309 | 399 | ||
| @@ -313,6 +403,8 @@ static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio, | |||
| 313 | 403 | ||
| 314 | return 0; | 404 | return 0; |
| 315 | 405 | ||
| 406 | exp_setup_keys_fail: | ||
| 407 | gpio_free(sel_c); | ||
| 316 | exp_setup_selc_fail: | 408 | exp_setup_selc_fail: |
| 317 | gpio_free(sel_b); | 409 | gpio_free(sel_b); |
| 318 | exp_setup_selb_fail: | 410 | exp_setup_selb_fail: |
| @@ -324,14 +416,192 @@ exp_setup_sela_fail: | |||
| 324 | static int da850_evm_ui_expander_teardown(struct i2c_client *client, | 416 | static int da850_evm_ui_expander_teardown(struct i2c_client *client, |
| 325 | unsigned gpio, unsigned ngpio, void *c) | 417 | unsigned gpio, unsigned ngpio, void *c) |
| 326 | { | 418 | { |
| 419 | platform_device_unregister(&da850_evm_ui_keys_device); | ||
| 420 | |||
| 327 | /* deselect all functionalities */ | 421 | /* deselect all functionalities */ |
| 328 | gpio_set_value(gpio + 5, 1); | 422 | gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_C, 1); |
| 329 | gpio_set_value(gpio + 6, 1); | 423 | gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_B, 1); |
| 330 | gpio_set_value(gpio + 7, 1); | 424 | gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_A, 1); |
| 425 | |||
| 426 | gpio_free(gpio + DA850_EVM_UI_EXP_SEL_C); | ||
| 427 | gpio_free(gpio + DA850_EVM_UI_EXP_SEL_B); | ||
| 428 | gpio_free(gpio + DA850_EVM_UI_EXP_SEL_A); | ||
| 429 | |||
| 430 | return 0; | ||
| 431 | } | ||
| 432 | |||
| 433 | /* assign the baseboard expander's GPIOs after the UI board's */ | ||
| 434 | #define DA850_UI_EXPANDER_N_GPIOS ARRAY_SIZE(da850_evm_ui_exp) | ||
| 435 | #define DA850_BB_EXPANDER_GPIO_BASE (DAVINCI_N_GPIO + DA850_UI_EXPANDER_N_GPIOS) | ||
| 436 | |||
| 437 | enum da850_evm_bb_exp_pins { | ||
| 438 | DA850_EVM_BB_EXP_DEEP_SLEEP_EN = 0, | ||
| 439 | DA850_EVM_BB_EXP_SW_RST, | ||
| 440 | DA850_EVM_BB_EXP_TP_23, | ||
| 441 | DA850_EVM_BB_EXP_TP_22, | ||
| 442 | DA850_EVM_BB_EXP_TP_21, | ||
| 443 | DA850_EVM_BB_EXP_USER_PB1, | ||
| 444 | DA850_EVM_BB_EXP_USER_LED2, | ||
| 445 | DA850_EVM_BB_EXP_USER_LED1, | ||
| 446 | DA850_EVM_BB_EXP_USER_SW1, | ||
| 447 | DA850_EVM_BB_EXP_USER_SW2, | ||
| 448 | DA850_EVM_BB_EXP_USER_SW3, | ||
| 449 | DA850_EVM_BB_EXP_USER_SW4, | ||
| 450 | DA850_EVM_BB_EXP_USER_SW5, | ||
| 451 | DA850_EVM_BB_EXP_USER_SW6, | ||
| 452 | DA850_EVM_BB_EXP_USER_SW7, | ||
| 453 | DA850_EVM_BB_EXP_USER_SW8 | ||
| 454 | }; | ||
| 455 | |||
| 456 | static const char const *da850_evm_bb_exp[] = { | ||
| 457 | [DA850_EVM_BB_EXP_DEEP_SLEEP_EN] = "deep_sleep_en", | ||
| 458 | [DA850_EVM_BB_EXP_SW_RST] = "sw_rst", | ||
| 459 | [DA850_EVM_BB_EXP_TP_23] = "tp_23", | ||
| 460 | [DA850_EVM_BB_EXP_TP_22] = "tp_22", | ||
| 461 | [DA850_EVM_BB_EXP_TP_21] = "tp_21", | ||
| 462 | [DA850_EVM_BB_EXP_USER_PB1] = "user_pb1", | ||
| 463 | [DA850_EVM_BB_EXP_USER_LED2] = "user_led2", | ||
| 464 | [DA850_EVM_BB_EXP_USER_LED1] = "user_led1", | ||
| 465 | [DA850_EVM_BB_EXP_USER_SW1] = "user_sw1", | ||
| 466 | [DA850_EVM_BB_EXP_USER_SW2] = "user_sw2", | ||
| 467 | [DA850_EVM_BB_EXP_USER_SW3] = "user_sw3", | ||
| 468 | [DA850_EVM_BB_EXP_USER_SW4] = "user_sw4", | ||
| 469 | [DA850_EVM_BB_EXP_USER_SW5] = "user_sw5", | ||
| 470 | [DA850_EVM_BB_EXP_USER_SW6] = "user_sw6", | ||
| 471 | [DA850_EVM_BB_EXP_USER_SW7] = "user_sw7", | ||
| 472 | [DA850_EVM_BB_EXP_USER_SW8] = "user_sw8", | ||
| 473 | }; | ||
| 474 | |||
| 475 | #define DA850_N_BB_USER_SW 8 | ||
| 476 | |||
| 477 | static struct gpio_keys_button da850_evm_bb_keys[] = { | ||
| 478 | [0] = { | ||
| 479 | .type = EV_KEY, | ||
| 480 | .active_low = 1, | ||
| 481 | .wakeup = 0, | ||
| 482 | .debounce_interval = DA850_KEYS_DEBOUNCE_MS, | ||
| 483 | .code = KEY_PROG1, | ||
| 484 | .desc = NULL, /* assigned at runtime */ | ||
| 485 | .gpio = -1, /* assigned at runtime */ | ||
| 486 | }, | ||
| 487 | [1 ... DA850_N_BB_USER_SW] = { | ||
| 488 | .type = EV_SW, | ||
| 489 | .active_low = 1, | ||
| 490 | .wakeup = 0, | ||
| 491 | .debounce_interval = DA850_KEYS_DEBOUNCE_MS, | ||
| 492 | .code = -1, /* assigned at runtime */ | ||
| 493 | .desc = NULL, /* assigned at runtime */ | ||
| 494 | .gpio = -1, /* assigned at runtime */ | ||
| 495 | }, | ||
| 496 | }; | ||
| 497 | |||
| 498 | static struct gpio_keys_platform_data da850_evm_bb_keys_pdata = { | ||
| 499 | .buttons = da850_evm_bb_keys, | ||
| 500 | .nbuttons = ARRAY_SIZE(da850_evm_bb_keys), | ||
| 501 | .poll_interval = DA850_GPIO_KEYS_POLL_MS, | ||
| 502 | }; | ||
| 503 | |||
| 504 | static struct platform_device da850_evm_bb_keys_device = { | ||
| 505 | .name = "gpio-keys-polled", | ||
| 506 | .id = 1, | ||
| 507 | .dev = { | ||
| 508 | .platform_data = &da850_evm_bb_keys_pdata | ||
| 509 | }, | ||
| 510 | }; | ||
| 511 | |||
| 512 | static void da850_evm_bb_keys_init(unsigned gpio) | ||
| 513 | { | ||
| 514 | int i; | ||
| 515 | struct gpio_keys_button *button; | ||
| 516 | |||
| 517 | button = &da850_evm_bb_keys[0]; | ||
| 518 | button->desc = (char *) | ||
| 519 | da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_PB1]; | ||
| 520 | button->gpio = gpio + DA850_EVM_BB_EXP_USER_PB1; | ||
| 521 | |||
| 522 | for (i = 0; i < DA850_N_BB_USER_SW; i++) { | ||
| 523 | button = &da850_evm_bb_keys[i + 1]; | ||
| 524 | button->code = SW_LID + i; | ||
| 525 | button->desc = (char *) | ||
| 526 | da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_SW1 + i]; | ||
| 527 | button->gpio = gpio + DA850_EVM_BB_EXP_USER_SW1 + i; | ||
| 528 | } | ||
| 529 | } | ||
| 331 | 530 | ||
| 332 | gpio_free(gpio + 5); | 531 | #define DA850_N_BB_USER_LED 2 |
| 333 | gpio_free(gpio + 6); | 532 | |
| 334 | gpio_free(gpio + 7); | 533 | static struct gpio_led da850_evm_bb_leds[] = { |
| 534 | [0 ... DA850_N_BB_USER_LED - 1] = { | ||
| 535 | .active_low = 1, | ||
| 536 | .gpio = -1, /* assigned at runtime */ | ||
| 537 | .name = NULL, /* assigned at runtime */ | ||
| 538 | }, | ||
| 539 | }; | ||
| 540 | |||
| 541 | static struct gpio_led_platform_data da850_evm_bb_leds_pdata = { | ||
| 542 | .leds = da850_evm_bb_leds, | ||
| 543 | .num_leds = ARRAY_SIZE(da850_evm_bb_leds), | ||
| 544 | }; | ||
| 545 | |||
| 546 | static struct platform_device da850_evm_bb_leds_device = { | ||
| 547 | .name = "leds-gpio", | ||
| 548 | .id = -1, | ||
| 549 | .dev = { | ||
| 550 | .platform_data = &da850_evm_bb_leds_pdata | ||
| 551 | } | ||
| 552 | }; | ||
| 553 | |||
| 554 | static void da850_evm_bb_leds_init(unsigned gpio) | ||
| 555 | { | ||
| 556 | int i; | ||
| 557 | struct gpio_led *led; | ||
| 558 | |||
| 559 | for (i = 0; i < DA850_N_BB_USER_LED; i++) { | ||
| 560 | led = &da850_evm_bb_leds[i]; | ||
| 561 | |||
| 562 | led->gpio = gpio + DA850_EVM_BB_EXP_USER_LED2 + i; | ||
| 563 | led->name = | ||
| 564 | da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_LED2 + i]; | ||
| 565 | } | ||
| 566 | } | ||
| 567 | |||
| 568 | static int da850_evm_bb_expander_setup(struct i2c_client *client, | ||
| 569 | unsigned gpio, unsigned ngpio, | ||
| 570 | void *c) | ||
| 571 | { | ||
| 572 | int ret; | ||
| 573 | |||
| 574 | /* | ||
| 575 | * Register the switches and pushbutton on the baseboard as a gpio-keys | ||
| 576 | * device. | ||
| 577 | */ | ||
| 578 | da850_evm_bb_keys_init(gpio); | ||
| 579 | ret = platform_device_register(&da850_evm_bb_keys_device); | ||
| 580 | if (ret) { | ||
| 581 | pr_warning("Could not register baseboard GPIO expander keys"); | ||
| 582 | goto io_exp_setup_sw_fail; | ||
| 583 | } | ||
| 584 | |||
| 585 | da850_evm_bb_leds_init(gpio); | ||
| 586 | ret = platform_device_register(&da850_evm_bb_leds_device); | ||
| 587 | if (ret) { | ||
| 588 | pr_warning("Could not register baseboard GPIO expander LEDS"); | ||
| 589 | goto io_exp_setup_leds_fail; | ||
| 590 | } | ||
| 591 | |||
| 592 | return 0; | ||
| 593 | |||
| 594 | io_exp_setup_leds_fail: | ||
| 595 | platform_device_unregister(&da850_evm_bb_keys_device); | ||
| 596 | io_exp_setup_sw_fail: | ||
| 597 | return ret; | ||
| 598 | } | ||
| 599 | |||
| 600 | static int da850_evm_bb_expander_teardown(struct i2c_client *client, | ||
| 601 | unsigned gpio, unsigned ngpio, void *c) | ||
| 602 | { | ||
| 603 | platform_device_unregister(&da850_evm_bb_leds_device); | ||
| 604 | platform_device_unregister(&da850_evm_bb_keys_device); | ||
| 335 | 605 | ||
| 336 | return 0; | 606 | return 0; |
| 337 | } | 607 | } |
| @@ -340,6 +610,14 @@ static struct pca953x_platform_data da850_evm_ui_expander_info = { | |||
| 340 | .gpio_base = DAVINCI_N_GPIO, | 610 | .gpio_base = DAVINCI_N_GPIO, |
| 341 | .setup = da850_evm_ui_expander_setup, | 611 | .setup = da850_evm_ui_expander_setup, |
| 342 | .teardown = da850_evm_ui_expander_teardown, | 612 | .teardown = da850_evm_ui_expander_teardown, |
| 613 | .names = da850_evm_ui_exp, | ||
| 614 | }; | ||
| 615 | |||
| 616 | static struct pca953x_platform_data da850_evm_bb_expander_info = { | ||
| 617 | .gpio_base = DA850_BB_EXPANDER_GPIO_BASE, | ||
| 618 | .setup = da850_evm_bb_expander_setup, | ||
| 619 | .teardown = da850_evm_bb_expander_teardown, | ||
| 620 | .names = da850_evm_bb_exp, | ||
| 343 | }; | 621 | }; |
| 344 | 622 | ||
| 345 | static struct i2c_board_info __initdata da850_evm_i2c_devices[] = { | 623 | static struct i2c_board_info __initdata da850_evm_i2c_devices[] = { |
| @@ -350,6 +628,10 @@ static struct i2c_board_info __initdata da850_evm_i2c_devices[] = { | |||
| 350 | I2C_BOARD_INFO("tca6416", 0x20), | 628 | I2C_BOARD_INFO("tca6416", 0x20), |
| 351 | .platform_data = &da850_evm_ui_expander_info, | 629 | .platform_data = &da850_evm_ui_expander_info, |
| 352 | }, | 630 | }, |
| 631 | { | ||
| 632 | I2C_BOARD_INFO("tca6416", 0x21), | ||
| 633 | .platform_data = &da850_evm_bb_expander_info, | ||
| 634 | }, | ||
| 353 | }; | 635 | }; |
| 354 | 636 | ||
| 355 | static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = { | 637 | static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = { |
| @@ -540,7 +822,7 @@ static struct regulator_init_data tps65070_regulator_data[] = { | |||
| 540 | { | 822 | { |
| 541 | .constraints = { | 823 | .constraints = { |
| 542 | .min_uV = 950000, | 824 | .min_uV = 950000, |
| 543 | .max_uV = 1320000, | 825 | .max_uV = 1350000, |
| 544 | .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | | 826 | .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | |
| 545 | REGULATOR_CHANGE_STATUS), | 827 | REGULATOR_CHANGE_STATUS), |
| 546 | .boot_on = 1, | 828 | .boot_on = 1, |
| @@ -591,7 +873,7 @@ static struct tps6507x_board tps_board = { | |||
| 591 | .tps6507x_ts_init_data = &tps6507x_touchscreen_data, | 873 | .tps6507x_ts_init_data = &tps6507x_touchscreen_data, |
| 592 | }; | 874 | }; |
| 593 | 875 | ||
| 594 | static struct i2c_board_info __initdata da850evm_tps65070_info[] = { | 876 | static struct i2c_board_info __initdata da850_evm_tps65070_info[] = { |
| 595 | { | 877 | { |
| 596 | I2C_BOARD_INFO("tps6507x", 0x48), | 878 | I2C_BOARD_INFO("tps6507x", 0x48), |
| 597 | .platform_data = &tps_board, | 879 | .platform_data = &tps_board, |
| @@ -600,8 +882,8 @@ static struct i2c_board_info __initdata da850evm_tps65070_info[] = { | |||
| 600 | 882 | ||
| 601 | static int __init pmic_tps65070_init(void) | 883 | static int __init pmic_tps65070_init(void) |
| 602 | { | 884 | { |
| 603 | return i2c_register_board_info(1, da850evm_tps65070_info, | 885 | return i2c_register_board_info(1, da850_evm_tps65070_info, |
| 604 | ARRAY_SIZE(da850evm_tps65070_info)); | 886 | ARRAY_SIZE(da850_evm_tps65070_info)); |
| 605 | } | 887 | } |
| 606 | 888 | ||
| 607 | static const short da850_evm_lcdc_pins[] = { | 889 | static const short da850_evm_lcdc_pins[] = { |
| @@ -736,6 +1018,27 @@ static struct edma_rsv_info *da850_edma_rsv[2] = { | |||
| 736 | &da850_edma_cc1_rsv, | 1018 | &da850_edma_cc1_rsv, |
| 737 | }; | 1019 | }; |
| 738 | 1020 | ||
| 1021 | #ifdef CONFIG_CPU_FREQ | ||
| 1022 | static __init int da850_evm_init_cpufreq(void) | ||
| 1023 | { | ||
| 1024 | switch (system_rev & 0xF) { | ||
| 1025 | case 3: | ||
| 1026 | da850_max_speed = 456000; | ||
| 1027 | break; | ||
| 1028 | case 2: | ||
| 1029 | da850_max_speed = 408000; | ||
| 1030 | break; | ||
| 1031 | case 1: | ||
| 1032 | da850_max_speed = 372000; | ||
| 1033 | break; | ||
| 1034 | } | ||
| 1035 | |||
| 1036 | return da850_register_cpufreq("pll0_sysclk3"); | ||
| 1037 | } | ||
| 1038 | #else | ||
| 1039 | static __init int da850_evm_init_cpufreq(void) { return 0; } | ||
| 1040 | #endif | ||
| 1041 | |||
| 739 | static __init void da850_evm_init(void) | 1042 | static __init void da850_evm_init(void) |
| 740 | { | 1043 | { |
| 741 | int ret; | 1044 | int ret; |
| @@ -836,7 +1139,7 @@ static __init void da850_evm_init(void) | |||
| 836 | if (ret) | 1139 | if (ret) |
| 837 | pr_warning("da850_evm_init: rtc setup failed: %d\n", ret); | 1140 | pr_warning("da850_evm_init: rtc setup failed: %d\n", ret); |
| 838 | 1141 | ||
| 839 | ret = da850_register_cpufreq("pll0_sysclk3"); | 1142 | ret = da850_evm_init_cpufreq(); |
| 840 | if (ret) | 1143 | if (ret) |
| 841 | pr_warning("da850_evm_init: cpufreq registration failed: %d\n", | 1144 | pr_warning("da850_evm_init: cpufreq registration failed: %d\n", |
| 842 | ret); | 1145 | ret); |
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index 01ba080433db..e4e3af179f02 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c | |||
| @@ -336,7 +336,7 @@ int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate) | |||
| 336 | ratio--; | 336 | ratio--; |
| 337 | } | 337 | } |
| 338 | 338 | ||
| 339 | if (ratio > PLLDIV_RATIO_MASK) | 339 | if (ratio > pll->div_ratio_mask) |
| 340 | return -EINVAL; | 340 | return -EINVAL; |
| 341 | 341 | ||
| 342 | do { | 342 | do { |
| @@ -344,7 +344,7 @@ int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate) | |||
| 344 | } while (v & PLLSTAT_GOSTAT); | 344 | } while (v & PLLSTAT_GOSTAT); |
| 345 | 345 | ||
| 346 | v = __raw_readl(pll->base + clk->div_reg); | 346 | v = __raw_readl(pll->base + clk->div_reg); |
| 347 | v &= ~PLLDIV_RATIO_MASK; | 347 | v &= ~pll->div_ratio_mask; |
| 348 | v |= ratio | PLLDIV_EN; | 348 | v |= ratio | PLLDIV_EN; |
| 349 | __raw_writel(v, pll->base + clk->div_reg); | 349 | __raw_writel(v, pll->base + clk->div_reg); |
| 350 | 350 | ||
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index 11099980b58b..0dd22031ec62 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h | |||
| @@ -68,7 +68,7 @@ | |||
| 68 | #ifndef __ASSEMBLER__ | 68 | #ifndef __ASSEMBLER__ |
| 69 | 69 | ||
| 70 | #include <linux/list.h> | 70 | #include <linux/list.h> |
| 71 | #include <asm/clkdev.h> | 71 | #include <linux/clkdev.h> |
| 72 | 72 | ||
| 73 | #define PLLSTAT_GOSTAT BIT(0) | 73 | #define PLLSTAT_GOSTAT BIT(0) |
| 74 | #define PLLCMD_GOSET BIT(0) | 74 | #define PLLCMD_GOSET BIT(0) |
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 63916b902760..78b5ae29ae40 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c | |||
| @@ -830,8 +830,7 @@ static void da850_set_async3_src(int pllnum) | |||
| 830 | * According to the TRM, minimum PLLM results in maximum power savings. | 830 | * According to the TRM, minimum PLLM results in maximum power savings. |
| 831 | * The OPP definitions below should keep the PLLM as low as possible. | 831 | * The OPP definitions below should keep the PLLM as low as possible. |
| 832 | * | 832 | * |
| 833 | * The output of the PLLM must be between 400 to 600 MHz. | 833 | * The output of the PLLM must be between 300 to 600 MHz. |
| 834 | * This rules out prediv of anything but divide-by-one for 24Mhz OSC input. | ||
| 835 | */ | 834 | */ |
| 836 | struct da850_opp { | 835 | struct da850_opp { |
| 837 | unsigned int freq; /* in KHz */ | 836 | unsigned int freq; /* in KHz */ |
| @@ -842,6 +841,33 @@ struct da850_opp { | |||
| 842 | unsigned int cvdd_max; /* in uV */ | 841 | unsigned int cvdd_max; /* in uV */ |
| 843 | }; | 842 | }; |
| 844 | 843 | ||
| 844 | static const struct da850_opp da850_opp_456 = { | ||
| 845 | .freq = 456000, | ||
| 846 | .prediv = 1, | ||
| 847 | .mult = 19, | ||
| 848 | .postdiv = 1, | ||
| 849 | .cvdd_min = 1300000, | ||
| 850 | .cvdd_max = 1350000, | ||
| 851 | }; | ||
| 852 | |||
| 853 | static const struct da850_opp da850_opp_408 = { | ||
| 854 | .freq = 408000, | ||
| 855 | .prediv = 1, | ||
| 856 | .mult = 17, | ||
| 857 | .postdiv = 1, | ||
| 858 | .cvdd_min = 1300000, | ||
| 859 | .cvdd_max = 1350000, | ||
| 860 | }; | ||
| 861 | |||
| 862 | static const struct da850_opp da850_opp_372 = { | ||
| 863 | .freq = 372000, | ||
| 864 | .prediv = 2, | ||
| 865 | .mult = 31, | ||
| 866 | .postdiv = 1, | ||
| 867 | .cvdd_min = 1200000, | ||
| 868 | .cvdd_max = 1320000, | ||
| 869 | }; | ||
| 870 | |||
| 845 | static const struct da850_opp da850_opp_300 = { | 871 | static const struct da850_opp da850_opp_300 = { |
| 846 | .freq = 300000, | 872 | .freq = 300000, |
| 847 | .prediv = 1, | 873 | .prediv = 1, |
| @@ -876,6 +902,9 @@ static const struct da850_opp da850_opp_96 = { | |||
| 876 | } | 902 | } |
| 877 | 903 | ||
| 878 | static struct cpufreq_frequency_table da850_freq_table[] = { | 904 | static struct cpufreq_frequency_table da850_freq_table[] = { |
| 905 | OPP(456), | ||
| 906 | OPP(408), | ||
| 907 | OPP(372), | ||
| 879 | OPP(300), | 908 | OPP(300), |
| 880 | OPP(200), | 909 | OPP(200), |
| 881 | OPP(96), | 910 | OPP(96), |
| @@ -886,6 +915,19 @@ static struct cpufreq_frequency_table da850_freq_table[] = { | |||
| 886 | }; | 915 | }; |
| 887 | 916 | ||
| 888 | #ifdef CONFIG_REGULATOR | 917 | #ifdef CONFIG_REGULATOR |
| 918 | static int da850_set_voltage(unsigned int index); | ||
| 919 | static int da850_regulator_init(void); | ||
| 920 | #endif | ||
| 921 | |||
| 922 | static struct davinci_cpufreq_config cpufreq_info = { | ||
| 923 | .freq_table = da850_freq_table, | ||
| 924 | #ifdef CONFIG_REGULATOR | ||
| 925 | .init = da850_regulator_init, | ||
| 926 | .set_voltage = da850_set_voltage, | ||
| 927 | #endif | ||
| 928 | }; | ||
| 929 | |||
| 930 | #ifdef CONFIG_REGULATOR | ||
| 889 | static struct regulator *cvdd; | 931 | static struct regulator *cvdd; |
| 890 | 932 | ||
| 891 | static int da850_set_voltage(unsigned int index) | 933 | static int da850_set_voltage(unsigned int index) |
| @@ -895,7 +937,7 @@ static int da850_set_voltage(unsigned int index) | |||
| 895 | if (!cvdd) | 937 | if (!cvdd) |
| 896 | return -ENODEV; | 938 | return -ENODEV; |
| 897 | 939 | ||
| 898 | opp = (struct da850_opp *) da850_freq_table[index].index; | 940 | opp = (struct da850_opp *) cpufreq_info.freq_table[index].index; |
| 899 | 941 | ||
| 900 | return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max); | 942 | return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max); |
| 901 | } | 943 | } |
| @@ -912,14 +954,6 @@ static int da850_regulator_init(void) | |||
| 912 | } | 954 | } |
| 913 | #endif | 955 | #endif |
| 914 | 956 | ||
| 915 | static struct davinci_cpufreq_config cpufreq_info = { | ||
| 916 | .freq_table = &da850_freq_table[0], | ||
| 917 | #ifdef CONFIG_REGULATOR | ||
| 918 | .init = da850_regulator_init, | ||
| 919 | .set_voltage = da850_set_voltage, | ||
| 920 | #endif | ||
| 921 | }; | ||
| 922 | |||
| 923 | static struct platform_device da850_cpufreq_device = { | 957 | static struct platform_device da850_cpufreq_device = { |
| 924 | .name = "cpufreq-davinci", | 958 | .name = "cpufreq-davinci", |
| 925 | .dev = { | 959 | .dev = { |
| @@ -928,12 +962,22 @@ static struct platform_device da850_cpufreq_device = { | |||
| 928 | .id = -1, | 962 | .id = -1, |
| 929 | }; | 963 | }; |
| 930 | 964 | ||
| 965 | unsigned int da850_max_speed = 300000; | ||
| 966 | |||
| 931 | int __init da850_register_cpufreq(char *async_clk) | 967 | int __init da850_register_cpufreq(char *async_clk) |
| 932 | { | 968 | { |
| 969 | int i; | ||
| 970 | |||
| 933 | /* cpufreq driver can help keep an "async" clock constant */ | 971 | /* cpufreq driver can help keep an "async" clock constant */ |
| 934 | if (async_clk) | 972 | if (async_clk) |
| 935 | clk_add_alias("async", da850_cpufreq_device.name, | 973 | clk_add_alias("async", da850_cpufreq_device.name, |
| 936 | async_clk, NULL); | 974 | async_clk, NULL); |
| 975 | for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) { | ||
| 976 | if (da850_freq_table[i].frequency <= da850_max_speed) { | ||
| 977 | cpufreq_info.freq_table = &da850_freq_table[i]; | ||
| 978 | break; | ||
| 979 | } | ||
| 980 | } | ||
| 937 | 981 | ||
| 938 | return platform_device_register(&da850_cpufreq_device); | 982 | return platform_device_register(&da850_cpufreq_device); |
| 939 | } | 983 | } |
| @@ -942,17 +986,18 @@ static int da850_round_armrate(struct clk *clk, unsigned long rate) | |||
| 942 | { | 986 | { |
| 943 | int i, ret = 0, diff; | 987 | int i, ret = 0, diff; |
| 944 | unsigned int best = (unsigned int) -1; | 988 | unsigned int best = (unsigned int) -1; |
| 989 | struct cpufreq_frequency_table *table = cpufreq_info.freq_table; | ||
| 945 | 990 | ||
| 946 | rate /= 1000; /* convert to kHz */ | 991 | rate /= 1000; /* convert to kHz */ |
| 947 | 992 | ||
| 948 | for (i = 0; da850_freq_table[i].frequency != CPUFREQ_TABLE_END; i++) { | 993 | for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) { |
| 949 | diff = da850_freq_table[i].frequency - rate; | 994 | diff = table[i].frequency - rate; |
| 950 | if (diff < 0) | 995 | if (diff < 0) |
| 951 | diff = -diff; | 996 | diff = -diff; |
| 952 | 997 | ||
| 953 | if (diff < best) { | 998 | if (diff < best) { |
| 954 | best = diff; | 999 | best = diff; |
| 955 | ret = da850_freq_table[i].frequency; | 1000 | ret = table[i].frequency; |
| 956 | } | 1001 | } |
| 957 | } | 1002 | } |
| 958 | 1003 | ||
| @@ -973,7 +1018,7 @@ static int da850_set_pll0rate(struct clk *clk, unsigned long index) | |||
| 973 | struct pll_data *pll = clk->pll_data; | 1018 | struct pll_data *pll = clk->pll_data; |
| 974 | int ret; | 1019 | int ret; |
| 975 | 1020 | ||
| 976 | opp = (struct da850_opp *) da850_freq_table[index].index; | 1021 | opp = (struct da850_opp *) cpufreq_info.freq_table[index].index; |
| 977 | prediv = opp->prediv; | 1022 | prediv = opp->prediv; |
| 978 | mult = opp->mult; | 1023 | mult = opp->mult; |
| 979 | postdiv = opp->postdiv; | 1024 | postdiv = opp->postdiv; |
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c index c9a86d8130d1..85503debda51 100644 --- a/arch/arm/mach-davinci/devices-tnetv107x.c +++ b/arch/arm/mach-davinci/devices-tnetv107x.c | |||
| @@ -344,7 +344,20 @@ static struct platform_device tsc_device = { | |||
| 344 | 344 | ||
| 345 | void __init tnetv107x_devices_init(struct tnetv107x_device_info *info) | 345 | void __init tnetv107x_devices_init(struct tnetv107x_device_info *info) |
| 346 | { | 346 | { |
| 347 | int i; | 347 | int i, error; |
| 348 | struct clk *tsc_clk; | ||
| 349 | |||
| 350 | /* | ||
| 351 | * The reset defaults for tnetv107x tsc clock divider is set too high. | ||
| 352 | * This forces the clock down to a range that allows the ADC to | ||
| 353 | * complete sample conversion in time. | ||
| 354 | */ | ||
| 355 | tsc_clk = clk_get(NULL, "sys_tsc_clk"); | ||
| 356 | if (tsc_clk) { | ||
| 357 | error = clk_set_rate(tsc_clk, 5000000); | ||
| 358 | WARN_ON(error < 0); | ||
| 359 | clk_put(tsc_clk); | ||
| 360 | } | ||
| 348 | 361 | ||
| 349 | platform_device_register(&edma_device); | 362 | platform_device_register(&edma_device); |
| 350 | platform_device_register(&tnetv107x_wdt_device); | 363 | platform_device_register(&tnetv107x_wdt_device); |
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c index 2652af124acd..a5f8a80c1f28 100644 --- a/arch/arm/mach-davinci/dm355.c +++ b/arch/arm/mach-davinci/dm355.c | |||
| @@ -412,12 +412,7 @@ static struct resource dm355_spi0_resources[] = { | |||
| 412 | static struct davinci_spi_platform_data dm355_spi0_pdata = { | 412 | static struct davinci_spi_platform_data dm355_spi0_pdata = { |
| 413 | .version = SPI_VERSION_1, | 413 | .version = SPI_VERSION_1, |
| 414 | .num_chipselect = 2, | 414 | .num_chipselect = 2, |
| 415 | .clk_internal = 1, | 415 | .cshold_bug = true, |
| 416 | .cs_hold = 1, | ||
| 417 | .intr_level = 0, | ||
| 418 | .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */ | ||
| 419 | .c2tdelay = 0, | ||
| 420 | .t2cdelay = 0, | ||
| 421 | }; | 416 | }; |
| 422 | static struct platform_device dm355_spi0_device = { | 417 | static struct platform_device dm355_spi0_device = { |
| 423 | .name = "spi_davinci", | 418 | .name = "spi_davinci", |
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index c466d710d3c1..02d2cc380df7 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c | |||
| @@ -625,12 +625,6 @@ static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32); | |||
| 625 | static struct davinci_spi_platform_data dm365_spi0_pdata = { | 625 | static struct davinci_spi_platform_data dm365_spi0_pdata = { |
| 626 | .version = SPI_VERSION_1, | 626 | .version = SPI_VERSION_1, |
| 627 | .num_chipselect = 2, | 627 | .num_chipselect = 2, |
| 628 | .clk_internal = 1, | ||
| 629 | .cs_hold = 1, | ||
| 630 | .intr_level = 0, | ||
| 631 | .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */ | ||
| 632 | .c2tdelay = 0, | ||
| 633 | .t2cdelay = 0, | ||
| 634 | }; | 628 | }; |
| 635 | 629 | ||
| 636 | static struct resource dm365_spi0_resources[] = { | 630 | static struct resource dm365_spi0_resources[] = { |
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 4247b3f53b33..e7f952066527 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h | |||
| @@ -28,6 +28,13 @@ extern void __iomem *da8xx_syscfg0_base; | |||
| 28 | extern void __iomem *da8xx_syscfg1_base; | 28 | extern void __iomem *da8xx_syscfg1_base; |
| 29 | 29 | ||
| 30 | /* | 30 | /* |
| 31 | * If the DA850/OMAP-L138/AM18x SoC on board is of a higher speed grade | ||
| 32 | * (than the regular 300Mhz variant), the board code should set this up | ||
| 33 | * with the supported speed before calling da850_register_cpufreq(). | ||
| 34 | */ | ||
| 35 | extern unsigned int da850_max_speed; | ||
| 36 | |||
| 37 | /* | ||
| 31 | * The cp_intc interrupt controller for the da8xx isn't in the same | 38 | * The cp_intc interrupt controller for the da8xx isn't in the same |
| 32 | * chunk of physical memory space as the other registers (like it is | 39 | * chunk of physical memory space as the other registers (like it is |
| 33 | * on the davincis) so it needs to be mapped separately. It will be | 40 | * on the davincis) so it needs to be mapped separately. It will be |
diff --git a/arch/arm/mach-davinci/include/mach/io.h b/arch/arm/mach-davinci/include/mach/io.h index 62b0a90309ad..d1b954955c12 100644 --- a/arch/arm/mach-davinci/include/mach/io.h +++ b/arch/arm/mach-davinci/include/mach/io.h | |||
| @@ -22,8 +22,8 @@ | |||
| 22 | #define __mem_isa(a) (a) | 22 | #define __mem_isa(a) (a) |
| 23 | 23 | ||
| 24 | #ifndef __ASSEMBLER__ | 24 | #ifndef __ASSEMBLER__ |
| 25 | #define __arch_ioremap(p, s, t) davinci_ioremap(p, s, t) | 25 | #define __arch_ioremap davinci_ioremap |
| 26 | #define __arch_iounmap(v) davinci_iounmap(v) | 26 | #define __arch_iounmap davinci_iounmap |
| 27 | 27 | ||
| 28 | void __iomem *davinci_ioremap(unsigned long phys, size_t size, | 28 | void __iomem *davinci_ioremap(unsigned long phys, size_t size, |
| 29 | unsigned int type); | 29 | unsigned int type); |
diff --git a/arch/arm/mach-davinci/include/mach/spi.h b/arch/arm/mach-davinci/include/mach/spi.h index 910efbf099c0..38f4da5ca135 100644 --- a/arch/arm/mach-davinci/include/mach/spi.h +++ b/arch/arm/mach-davinci/include/mach/spi.h | |||
| @@ -19,26 +19,66 @@ | |||
| 19 | #ifndef __ARCH_ARM_DAVINCI_SPI_H | 19 | #ifndef __ARCH_ARM_DAVINCI_SPI_H |
| 20 | #define __ARCH_ARM_DAVINCI_SPI_H | 20 | #define __ARCH_ARM_DAVINCI_SPI_H |
| 21 | 21 | ||
| 22 | #define SPI_INTERN_CS 0xFF | ||
| 23 | |||
| 22 | enum { | 24 | enum { |
| 23 | SPI_VERSION_1, /* For DM355/DM365/DM6467 */ | 25 | SPI_VERSION_1, /* For DM355/DM365/DM6467 */ |
| 24 | SPI_VERSION_2, /* For DA8xx */ | 26 | SPI_VERSION_2, /* For DA8xx */ |
| 25 | }; | 27 | }; |
| 26 | 28 | ||
| 29 | /** | ||
| 30 | * davinci_spi_platform_data - Platform data for SPI master device on DaVinci | ||
| 31 | * | ||
| 32 | * @version: version of the SPI IP. Different DaVinci devices have slightly | ||
| 33 | * varying versions of the same IP. | ||
| 34 | * @num_chipselect: number of chipselects supported by this SPI master | ||
| 35 | * @intr_line: interrupt line used to connect the SPI IP to the ARM interrupt | ||
| 36 | * controller withn the SoC. Possible values are 0 and 1. | ||
| 37 | * @chip_sel: list of GPIOs which can act as chip-selects for the SPI. | ||
| 38 | * SPI_INTERN_CS denotes internal SPI chip-select. Not necessary | ||
| 39 | * to populate if all chip-selects are internal. | ||
| 40 | * @cshold_bug: set this to true if the SPI controller on your chip requires | ||
| 41 | * a write to CSHOLD bit in between transfers (like in DM355). | ||
| 42 | */ | ||
| 27 | struct davinci_spi_platform_data { | 43 | struct davinci_spi_platform_data { |
| 28 | u8 version; | 44 | u8 version; |
| 29 | u8 num_chipselect; | 45 | u8 num_chipselect; |
| 46 | u8 intr_line; | ||
| 47 | u8 *chip_sel; | ||
| 48 | bool cshold_bug; | ||
| 49 | }; | ||
| 50 | |||
| 51 | /** | ||
| 52 | * davinci_spi_config - Per-chip-select configuration for SPI slave devices | ||
| 53 | * | ||
| 54 | * @wdelay: amount of delay between transmissions. Measured in number of | ||
| 55 | * SPI module clocks. | ||
| 56 | * @odd_parity: polarity of parity flag at the end of transmit data stream. | ||
| 57 | * 0 - odd parity, 1 - even parity. | ||
| 58 | * @parity_enable: enable transmission of parity at end of each transmit | ||
| 59 | * data stream. | ||
| 60 | * @io_type: type of IO transfer. Choose between polled, interrupt and DMA. | ||
| 61 | * @timer_disable: disable chip-select timers (setup and hold) | ||
| 62 | * @c2tdelay: chip-select setup time. Measured in number of SPI module clocks. | ||
| 63 | * @t2cdelay: chip-select hold time. Measured in number of SPI module clocks. | ||
| 64 | * @t2edelay: transmit data finished to SPI ENAn pin inactive time. Measured | ||
| 65 | * in number of SPI clocks. | ||
| 66 | * @c2edelay: chip-select active to SPI ENAn signal active time. Measured in | ||
| 67 | * number of SPI clocks. | ||
| 68 | */ | ||
| 69 | struct davinci_spi_config { | ||
| 30 | u8 wdelay; | 70 | u8 wdelay; |
| 31 | u8 odd_parity; | 71 | u8 odd_parity; |
| 32 | u8 parity_enable; | 72 | u8 parity_enable; |
| 33 | u8 wait_enable; | 73 | #define SPI_IO_TYPE_INTR 0 |
| 74 | #define SPI_IO_TYPE_POLL 1 | ||
| 75 | #define SPI_IO_TYPE_DMA 2 | ||
| 76 | u8 io_type; | ||
| 34 | u8 timer_disable; | 77 | u8 timer_disable; |
| 35 | u8 clk_internal; | ||
| 36 | u8 cs_hold; | ||
| 37 | u8 intr_level; | ||
| 38 | u8 poll_mode; | ||
| 39 | u8 use_dma; | ||
| 40 | u8 c2tdelay; | 78 | u8 c2tdelay; |
| 41 | u8 t2cdelay; | 79 | u8 t2cdelay; |
| 80 | u8 t2edelay; | ||
| 81 | u8 c2edelay; | ||
| 42 | }; | 82 | }; |
| 43 | 83 | ||
| 44 | #endif /* __ARCH_ARM_DAVINCI_SPI_H */ | 84 | #endif /* __ARCH_ARM_DAVINCI_SPI_H */ |
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c index 1b15dbd0a77b..a41580400701 100644 --- a/arch/arm/mach-davinci/psc.c +++ b/arch/arm/mach-davinci/psc.c | |||
| @@ -83,21 +83,16 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr, | |||
| 83 | pdctl1 = __raw_readl(psc_base + PDCTL1); | 83 | pdctl1 = __raw_readl(psc_base + PDCTL1); |
| 84 | pdctl1 |= 0x100; | 84 | pdctl1 |= 0x100; |
| 85 | __raw_writel(pdctl1, psc_base + PDCTL1); | 85 | __raw_writel(pdctl1, psc_base + PDCTL1); |
| 86 | |||
| 87 | do { | ||
| 88 | ptstat = __raw_readl(psc_base + | ||
| 89 | PTSTAT); | ||
| 90 | } while (!(((ptstat >> domain) & 1) == 0)); | ||
| 91 | } else { | 86 | } else { |
| 92 | ptcmd = 1 << domain; | 87 | ptcmd = 1 << domain; |
| 93 | __raw_writel(ptcmd, psc_base + PTCMD); | 88 | __raw_writel(ptcmd, psc_base + PTCMD); |
| 94 | |||
| 95 | do { | ||
| 96 | ptstat = __raw_readl(psc_base + PTSTAT); | ||
| 97 | } while (!(((ptstat >> domain) & 1) == 0)); | ||
| 98 | } | 89 | } |
| 99 | 90 | ||
| 100 | do { | 91 | do { |
| 92 | ptstat = __raw_readl(psc_base + PTSTAT); | ||
| 93 | } while (!(((ptstat >> domain) & 1) == 0)); | ||
| 94 | |||
| 95 | do { | ||
| 101 | mdstat = __raw_readl(psc_base + MDSTAT + 4 * id); | 96 | mdstat = __raw_readl(psc_base + MDSTAT + 4 * id); |
| 102 | } while (!((mdstat & MDSTAT_STATE_MASK) == next_state)); | 97 | } while (!((mdstat & MDSTAT_STATE_MASK) == next_state)); |
| 103 | 98 | ||
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c index 0f21c36e65dd..e1969ce904dc 100644 --- a/arch/arm/mach-davinci/time.c +++ b/arch/arm/mach-davinci/time.c | |||
| @@ -272,15 +272,35 @@ static cycle_t read_cycles(struct clocksource *cs) | |||
| 272 | return (cycles_t)timer32_read(t); | 272 | return (cycles_t)timer32_read(t); |
| 273 | } | 273 | } |
| 274 | 274 | ||
| 275 | /* | ||
| 276 | * Kernel assumes that sched_clock can be called early but may not have | ||
| 277 | * things ready yet. | ||
| 278 | */ | ||
| 279 | static cycle_t read_dummy(struct clocksource *cs) | ||
| 280 | { | ||
| 281 | return 0; | ||
| 282 | } | ||
| 283 | |||
| 284 | |||
| 275 | static struct clocksource clocksource_davinci = { | 285 | static struct clocksource clocksource_davinci = { |
| 276 | .rating = 300, | 286 | .rating = 300, |
| 277 | .read = read_cycles, | 287 | .read = read_dummy, |
| 278 | .mask = CLOCKSOURCE_MASK(32), | 288 | .mask = CLOCKSOURCE_MASK(32), |
| 279 | .shift = 24, | ||
| 280 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 289 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 281 | }; | 290 | }; |
| 282 | 291 | ||
| 283 | /* | 292 | /* |
| 293 | * Overwrite weak default sched_clock with something more precise | ||
| 294 | */ | ||
| 295 | unsigned long long notrace sched_clock(void) | ||
| 296 | { | ||
| 297 | const cycle_t cyc = clocksource_davinci.read(&clocksource_davinci); | ||
| 298 | |||
| 299 | return clocksource_cyc2ns(cyc, clocksource_davinci.mult, | ||
| 300 | clocksource_davinci.shift); | ||
| 301 | } | ||
| 302 | |||
| 303 | /* | ||
| 284 | * clockevent | 304 | * clockevent |
| 285 | */ | 305 | */ |
| 286 | static int davinci_set_next_event(unsigned long cycles, | 306 | static int davinci_set_next_event(unsigned long cycles, |
| @@ -377,11 +397,10 @@ static void __init davinci_timer_init(void) | |||
| 377 | davinci_clock_tick_rate = clk_get_rate(timer_clk); | 397 | davinci_clock_tick_rate = clk_get_rate(timer_clk); |
| 378 | 398 | ||
| 379 | /* setup clocksource */ | 399 | /* setup clocksource */ |
| 400 | clocksource_davinci.read = read_cycles; | ||
| 380 | clocksource_davinci.name = id_to_name[clocksource_id]; | 401 | clocksource_davinci.name = id_to_name[clocksource_id]; |
| 381 | clocksource_davinci.mult = | 402 | if (clocksource_register_hz(&clocksource_davinci, |
| 382 | clocksource_khz2mult(davinci_clock_tick_rate/1000, | 403 | davinci_clock_tick_rate)) |
| 383 | clocksource_davinci.shift); | ||
| 384 | if (clocksource_register(&clocksource_davinci)) | ||
| 385 | printk(err, clocksource_davinci.name); | 404 | printk(err, clocksource_davinci.name); |
| 386 | 405 | ||
| 387 | /* setup clockevent */ | 406 | /* setup clockevent */ |
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c index daeae06430b9..6fcdecec8d8c 100644 --- a/arch/arm/mach-davinci/tnetv107x.c +++ b/arch/arm/mach-davinci/tnetv107x.c | |||
| @@ -131,12 +131,13 @@ define_pll_clk(tdm, 1, 0x0ff, 0x200); | |||
| 131 | define_pll_clk(eth, 2, 0x0ff, 0x400); | 131 | define_pll_clk(eth, 2, 0x0ff, 0x400); |
| 132 | 132 | ||
| 133 | /* Level 2 - divided outputs from the PLLs */ | 133 | /* Level 2 - divided outputs from the PLLs */ |
| 134 | #define define_pll_div_clk(pll, cname, div) \ | 134 | #define define_pll_div_clk(pll, cname, div) \ |
| 135 | static struct clk pll##_##cname##_clk = { \ | 135 | static struct clk pll##_##cname##_clk = { \ |
| 136 | .name = #pll "_" #cname "_clk",\ | 136 | .name = #pll "_" #cname "_clk", \ |
| 137 | .parent = &pll_##pll##_clk, \ | 137 | .parent = &pll_##pll##_clk, \ |
| 138 | .flags = CLK_PLL, \ | 138 | .flags = CLK_PLL, \ |
| 139 | .div_reg = PLLDIV##div, \ | 139 | .div_reg = PLLDIV##div, \ |
| 140 | .set_rate = davinci_set_sysclk_rate, \ | ||
| 140 | } | 141 | } |
| 141 | 142 | ||
| 142 | define_pll_div_clk(sys, arm1176, 1); | 143 | define_pll_div_clk(sys, arm1176, 1); |
| @@ -192,6 +193,7 @@ lpsc_clk_enabled(system, sys_half_clk, SYSTEM); | |||
| 192 | lpsc_clk_enabled(ddr2_vrst, sys_ddr_clk, DDR2_EMIF1_VRST); | 193 | lpsc_clk_enabled(ddr2_vrst, sys_ddr_clk, DDR2_EMIF1_VRST); |
| 193 | lpsc_clk_enabled(ddr2_vctl_rst, sys_ddr_clk, DDR2_EMIF2_VCTL_RST); | 194 | lpsc_clk_enabled(ddr2_vctl_rst, sys_ddr_clk, DDR2_EMIF2_VCTL_RST); |
| 194 | lpsc_clk_enabled(wdt_arm, sys_half_clk, WDT_ARM); | 195 | lpsc_clk_enabled(wdt_arm, sys_half_clk, WDT_ARM); |
| 196 | lpsc_clk_enabled(timer1, sys_half_clk, TIMER1); | ||
| 195 | 197 | ||
| 196 | lpsc_clk(mbx_lite, sys_arm1176_clk, MBX_LITE); | 198 | lpsc_clk(mbx_lite, sys_arm1176_clk, MBX_LITE); |
| 197 | lpsc_clk(ethss, eth_125mhz_clk, ETHSS); | 199 | lpsc_clk(ethss, eth_125mhz_clk, ETHSS); |
| @@ -205,16 +207,15 @@ lpsc_clk(mdio, sys_half_clk, MDIO); | |||
| 205 | lpsc_clk(sdio0, sys_half_clk, SDIO0); | 207 | lpsc_clk(sdio0, sys_half_clk, SDIO0); |
| 206 | lpsc_clk(sdio1, sys_half_clk, SDIO1); | 208 | lpsc_clk(sdio1, sys_half_clk, SDIO1); |
| 207 | lpsc_clk(timer0, sys_half_clk, TIMER0); | 209 | lpsc_clk(timer0, sys_half_clk, TIMER0); |
| 208 | lpsc_clk(timer1, sys_half_clk, TIMER1); | ||
| 209 | lpsc_clk(wdt_dsp, sys_half_clk, WDT_DSP); | 210 | lpsc_clk(wdt_dsp, sys_half_clk, WDT_DSP); |
| 210 | lpsc_clk(ssp, sys_half_clk, SSP); | 211 | lpsc_clk(ssp, sys_half_clk, SSP); |
| 211 | lpsc_clk(tdm0, tdm_0_clk, TDM0); | 212 | lpsc_clk(tdm0, tdm_0_clk, TDM0); |
| 212 | lpsc_clk(tdm1, tdm_1_clk, TDM1); | 213 | lpsc_clk(tdm1, tdm_1_clk, TDM1); |
| 213 | lpsc_clk(vlynq, sys_vlynq_ref_clk, VLYNQ); | 214 | lpsc_clk(vlynq, sys_vlynq_ref_clk, VLYNQ); |
| 214 | lpsc_clk(mcdma, sys_half_clk, MCDMA); | 215 | lpsc_clk(mcdma, sys_half_clk, MCDMA); |
| 215 | lpsc_clk(usb0, sys_half_clk, USB0); | ||
| 216 | lpsc_clk(usb1, sys_half_clk, USB1); | ||
| 217 | lpsc_clk(usbss, sys_half_clk, USBSS); | 216 | lpsc_clk(usbss, sys_half_clk, USBSS); |
| 217 | lpsc_clk(usb0, clk_usbss, USB0); | ||
| 218 | lpsc_clk(usb1, clk_usbss, USB1); | ||
| 218 | lpsc_clk(ethss_rgmii, eth_250mhz_clk, ETHSS_RGMII); | 219 | lpsc_clk(ethss_rgmii, eth_250mhz_clk, ETHSS_RGMII); |
| 219 | lpsc_clk(imcop, sys_dsp_clk, IMCOP); | 220 | lpsc_clk(imcop, sys_dsp_clk, IMCOP); |
| 220 | lpsc_clk(spare, sys_half_clk, SPARE); | 221 | lpsc_clk(spare, sys_half_clk, SPARE); |
| @@ -281,7 +282,9 @@ static struct clk_lookup clks[] = { | |||
| 281 | CLK(NULL, "clk_tdm0", &clk_tdm0), | 282 | CLK(NULL, "clk_tdm0", &clk_tdm0), |
| 282 | CLK(NULL, "clk_vlynq", &clk_vlynq), | 283 | CLK(NULL, "clk_vlynq", &clk_vlynq), |
| 283 | CLK(NULL, "clk_mcdma", &clk_mcdma), | 284 | CLK(NULL, "clk_mcdma", &clk_mcdma), |
| 285 | CLK(NULL, "clk_usbss", &clk_usbss), | ||
| 284 | CLK(NULL, "clk_usb0", &clk_usb0), | 286 | CLK(NULL, "clk_usb0", &clk_usb0), |
| 287 | CLK(NULL, "clk_usb1", &clk_usb1), | ||
| 285 | CLK(NULL, "clk_tdm1", &clk_tdm1), | 288 | CLK(NULL, "clk_tdm1", &clk_tdm1), |
| 286 | CLK(NULL, "clk_debugss", &clk_debugss), | 289 | CLK(NULL, "clk_debugss", &clk_debugss), |
| 287 | CLK(NULL, "clk_ethss_rgmii", &clk_ethss_rgmii), | 290 | CLK(NULL, "clk_ethss_rgmii", &clk_ethss_rgmii), |
| @@ -289,8 +292,6 @@ static struct clk_lookup clks[] = { | |||
| 289 | CLK(NULL, "clk_imcop", &clk_imcop), | 292 | CLK(NULL, "clk_imcop", &clk_imcop), |
| 290 | CLK(NULL, "clk_spare", &clk_spare), | 293 | CLK(NULL, "clk_spare", &clk_spare), |
| 291 | CLK("davinci_mmc.1", NULL, &clk_sdio1), | 294 | CLK("davinci_mmc.1", NULL, &clk_sdio1), |
| 292 | CLK(NULL, "clk_usb1", &clk_usb1), | ||
| 293 | CLK(NULL, "clk_usbss", &clk_usbss), | ||
| 294 | CLK(NULL, "clk_ddr2_vrst", &clk_ddr2_vrst), | 295 | CLK(NULL, "clk_ddr2_vrst", &clk_ddr2_vrst), |
| 295 | CLK(NULL, "clk_ddr2_vctl_rst", &clk_ddr2_vctl_rst), | 296 | CLK(NULL, "clk_ddr2_vctl_rst", &clk_ddr2_vctl_rst), |
| 296 | CLK(NULL, NULL, NULL), | 297 | CLK(NULL, NULL, NULL), |
diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c index 31f0cbea0caa..23d2b6d9fa63 100644 --- a/arch/arm/mach-davinci/usb.c +++ b/arch/arm/mach-davinci/usb.c | |||
| @@ -64,17 +64,19 @@ static struct resource usb_resources[] = { | |||
| 64 | { | 64 | { |
| 65 | .start = IRQ_USBINT, | 65 | .start = IRQ_USBINT, |
| 66 | .flags = IORESOURCE_IRQ, | 66 | .flags = IORESOURCE_IRQ, |
| 67 | .name = "mc" | ||
| 67 | }, | 68 | }, |
| 68 | { | 69 | { |
| 69 | /* placeholder for the dedicated CPPI IRQ */ | 70 | /* placeholder for the dedicated CPPI IRQ */ |
| 70 | .flags = IORESOURCE_IRQ, | 71 | .flags = IORESOURCE_IRQ, |
| 72 | .name = "dma" | ||
| 71 | }, | 73 | }, |
| 72 | }; | 74 | }; |
| 73 | 75 | ||
| 74 | static u64 usb_dmamask = DMA_BIT_MASK(32); | 76 | static u64 usb_dmamask = DMA_BIT_MASK(32); |
| 75 | 77 | ||
| 76 | static struct platform_device usb_dev = { | 78 | static struct platform_device usb_dev = { |
| 77 | .name = "musb_hdrc", | 79 | .name = "musb-davinci", |
| 78 | .id = -1, | 80 | .id = -1, |
| 79 | .dev = { | 81 | .dev = { |
| 80 | .platform_data = &usb_data, | 82 | .platform_data = &usb_data, |
| @@ -110,6 +112,7 @@ static struct resource da8xx_usb20_resources[] = { | |||
| 110 | { | 112 | { |
| 111 | .start = IRQ_DA8XX_USB_INT, | 113 | .start = IRQ_DA8XX_USB_INT, |
| 112 | .flags = IORESOURCE_IRQ, | 114 | .flags = IORESOURCE_IRQ, |
| 115 | .name = "mc", | ||
| 113 | }, | 116 | }, |
| 114 | }; | 117 | }; |
| 115 | 118 | ||
| @@ -121,6 +124,7 @@ int __init da8xx_register_usb20(unsigned mA, unsigned potpgt) | |||
| 121 | 124 | ||
| 122 | usb_dev.resource = da8xx_usb20_resources; | 125 | usb_dev.resource = da8xx_usb20_resources; |
| 123 | usb_dev.num_resources = ARRAY_SIZE(da8xx_usb20_resources); | 126 | usb_dev.num_resources = ARRAY_SIZE(da8xx_usb20_resources); |
| 127 | usb_dev.name = "musb-da8xx"; | ||
| 124 | 128 | ||
| 125 | return platform_device_register(&usb_dev); | 129 | return platform_device_register(&usb_dev); |
| 126 | } | 130 | } |
diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig index 3b9a32ace909..a4ed3900912a 100644 --- a/arch/arm/mach-dove/Kconfig +++ b/arch/arm/mach-dove/Kconfig | |||
| @@ -9,6 +9,12 @@ config MACH_DOVE_DB | |||
| 9 | Say 'Y' here if you want your kernel to support the | 9 | Say 'Y' here if you want your kernel to support the |
| 10 | Marvell DB-MV88AP510 Development Board. | 10 | Marvell DB-MV88AP510 Development Board. |
| 11 | 11 | ||
| 12 | config MACH_CM_A510 | ||
| 13 | bool "CompuLab CM-A510 Board" | ||
| 14 | help | ||
| 15 | Say 'Y' here if you want your kernel to support the | ||
| 16 | CompuLab CM-A510 Board. | ||
| 17 | |||
| 12 | endmenu | 18 | endmenu |
| 13 | 19 | ||
| 14 | endif | 20 | endif |
diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile index 7ab3be53f642..fa0f01856060 100644 --- a/arch/arm/mach-dove/Makefile +++ b/arch/arm/mach-dove/Makefile | |||
| @@ -1,3 +1,4 @@ | |||
| 1 | obj-y += common.o addr-map.o irq.o pcie.o | 1 | obj-y += common.o addr-map.o irq.o pcie.o mpp.o |
| 2 | 2 | ||
| 3 | obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o | 3 | obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o |
| 4 | obj-$(CONFIG_MACH_CM_A510) += cm-a510.o | ||
diff --git a/arch/arm/mach-dove/cm-a510.c b/arch/arm/mach-dove/cm-a510.c new file mode 100644 index 000000000000..96e0e94e5fa9 --- /dev/null +++ b/arch/arm/mach-dove/cm-a510.c | |||
| @@ -0,0 +1,95 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-dove/cm-a510.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 CompuLab, Ltd. | ||
| 5 | * Konstantin Sinyuk <kostyas@compulab.co.il> | ||
| 6 | * | ||
| 7 | * Based on Marvell DB-MV88AP510-BP Development Board Setup | ||
| 8 | * | ||
| 9 | * This file is licensed under the terms of the GNU General Public | ||
| 10 | * License version 2. This program is licensed "as is" without any | ||
| 11 | * warranty of any kind, whether express or implied. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/init.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <linux/ata_platform.h> | ||
| 18 | #include <linux/mv643xx_eth.h> | ||
| 19 | #include <linux/spi/spi.h> | ||
| 20 | #include <linux/spi/flash.h> | ||
| 21 | |||
| 22 | #include <asm/mach-types.h> | ||
| 23 | #include <asm/mach/arch.h> | ||
| 24 | |||
| 25 | #include <mach/dove.h> | ||
| 26 | |||
| 27 | #include "common.h" | ||
| 28 | |||
| 29 | static struct mv643xx_eth_platform_data cm_a510_ge00_data = { | ||
| 30 | .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT, | ||
| 31 | }; | ||
| 32 | |||
| 33 | static struct mv_sata_platform_data cm_a510_sata_data = { | ||
| 34 | .n_ports = 1, | ||
| 35 | }; | ||
| 36 | |||
| 37 | /* | ||
| 38 | * SPI Devices: | ||
| 39 | * SPI0: 1M Flash Winbond w25q32bv | ||
| 40 | */ | ||
| 41 | static const struct flash_platform_data cm_a510_spi_flash_data = { | ||
| 42 | .type = "w25q32bv", | ||
| 43 | }; | ||
| 44 | |||
| 45 | static struct spi_board_info __initdata cm_a510_spi_flash_info[] = { | ||
| 46 | { | ||
| 47 | .modalias = "m25p80", | ||
| 48 | .platform_data = &cm_a510_spi_flash_data, | ||
| 49 | .irq = -1, | ||
| 50 | .max_speed_hz = 20000000, | ||
| 51 | .bus_num = 0, | ||
| 52 | .chip_select = 0, | ||
| 53 | }, | ||
| 54 | }; | ||
| 55 | |||
| 56 | static int __init cm_a510_pci_init(void) | ||
| 57 | { | ||
| 58 | if (machine_is_cm_a510()) | ||
| 59 | dove_pcie_init(1, 1); | ||
| 60 | |||
| 61 | return 0; | ||
| 62 | } | ||
| 63 | |||
| 64 | subsys_initcall(cm_a510_pci_init); | ||
| 65 | |||
| 66 | /* Board Init */ | ||
| 67 | static void __init cm_a510_init(void) | ||
| 68 | { | ||
| 69 | /* | ||
| 70 | * Basic Dove setup. Needs to be called early. | ||
| 71 | */ | ||
| 72 | dove_init(); | ||
| 73 | |||
| 74 | dove_ge00_init(&cm_a510_ge00_data); | ||
| 75 | dove_ehci0_init(); | ||
| 76 | dove_ehci1_init(); | ||
| 77 | dove_sata_init(&cm_a510_sata_data); | ||
| 78 | dove_sdio0_init(); | ||
| 79 | dove_sdio1_init(); | ||
| 80 | dove_spi0_init(); | ||
| 81 | dove_spi1_init(); | ||
| 82 | dove_uart0_init(); | ||
| 83 | dove_uart1_init(); | ||
| 84 | dove_i2c_init(); | ||
| 85 | spi_register_board_info(cm_a510_spi_flash_info, | ||
| 86 | ARRAY_SIZE(cm_a510_spi_flash_info)); | ||
| 87 | } | ||
| 88 | |||
| 89 | MACHINE_START(CM_A510, "Compulab CM-A510 Board") | ||
| 90 | .boot_params = 0x00000100, | ||
| 91 | .init_machine = cm_a510_init, | ||
| 92 | .map_io = dove_map_io, | ||
| 93 | .init_irq = dove_init_irq, | ||
| 94 | .timer = &dove_timer, | ||
| 95 | MACHINE_END | ||
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index f7a12586a1f5..fe627aba6da7 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c | |||
| @@ -770,7 +770,7 @@ static struct resource dove_sdio0_resources[] = { | |||
| 770 | }; | 770 | }; |
| 771 | 771 | ||
| 772 | static struct platform_device dove_sdio0 = { | 772 | static struct platform_device dove_sdio0 = { |
| 773 | .name = "sdhci-mv", | 773 | .name = "sdhci-dove", |
| 774 | .id = 0, | 774 | .id = 0, |
| 775 | .dev = { | 775 | .dev = { |
| 776 | .dma_mask = &sdio_dmamask, | 776 | .dma_mask = &sdio_dmamask, |
| @@ -798,7 +798,7 @@ static struct resource dove_sdio1_resources[] = { | |||
| 798 | }; | 798 | }; |
| 799 | 799 | ||
| 800 | static struct platform_device dove_sdio1 = { | 800 | static struct platform_device dove_sdio1 = { |
| 801 | .name = "sdhci-mv", | 801 | .name = "sdhci-dove", |
| 802 | .id = 1, | 802 | .id = 1, |
| 803 | .dev = { | 803 | .dev = { |
| 804 | .dma_mask = &sdio_dmamask, | 804 | .dma_mask = &sdio_dmamask, |
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h index f6a08397f046..27b414578f2e 100644 --- a/arch/arm/mach-dove/include/mach/dove.h +++ b/arch/arm/mach-dove/include/mach/dove.h | |||
| @@ -131,14 +131,21 @@ | |||
| 131 | #define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE | 0x014) | 131 | #define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE | 0x014) |
| 132 | #define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE | 0x018) | 132 | #define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE | 0x018) |
| 133 | #define DOVE_GPIO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400) | 133 | #define DOVE_GPIO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400) |
| 134 | #define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe8400) | ||
| 134 | #define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c) | 135 | #define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c) |
| 135 | #define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1) | 136 | #define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1) |
| 136 | #define DOVE_NAND_GPIO_EN (1 << 0) | 137 | #define DOVE_NAND_GPIO_EN (1 << 0) |
| 137 | #define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_VIRT_BASE + 0x40) | 138 | #define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_VIRT_BASE + 0x40) |
| 138 | 139 | #define DOVE_SPI_GPIO_SEL (1 << 5) | |
| 140 | #define DOVE_UART1_GPIO_SEL (1 << 4) | ||
| 141 | #define DOVE_AU1_GPIO_SEL (1 << 3) | ||
| 142 | #define DOVE_CAM_GPIO_SEL (1 << 2) | ||
| 143 | #define DOVE_SD1_GPIO_SEL (1 << 1) | ||
| 144 | #define DOVE_SD0_GPIO_SEL (1 << 0) | ||
| 139 | 145 | ||
| 140 | /* Power Management */ | 146 | /* Power Management */ |
| 141 | #define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0000) | 147 | #define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0000) |
| 148 | #define DOVE_PMU_SIG_CTRL (DOVE_PMU_VIRT_BASE + 0x802c) | ||
| 142 | 149 | ||
| 143 | /* Real Time Clock */ | 150 | /* Real Time Clock */ |
| 144 | #define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xd8500) | 151 | #define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xd8500) |
diff --git a/arch/arm/mach-dove/include/mach/gpio.h b/arch/arm/mach-dove/include/mach/gpio.h index 0ee70ff39e11..340bb7af529d 100644 --- a/arch/arm/mach-dove/include/mach/gpio.h +++ b/arch/arm/mach-dove/include/mach/gpio.h | |||
| @@ -14,12 +14,14 @@ | |||
| 14 | #include <plat/gpio.h> | 14 | #include <plat/gpio.h> |
| 15 | #include <asm-generic/gpio.h> /* cansleep wrappers */ | 15 | #include <asm-generic/gpio.h> /* cansleep wrappers */ |
| 16 | 16 | ||
| 17 | #define GPIO_MAX 64 | 17 | #define GPIO_MAX 72 |
| 18 | 18 | ||
| 19 | #define GPIO_BASE_LO (DOVE_GPIO_VIRT_BASE + 0x00) | 19 | #define GPIO_BASE_LO (DOVE_GPIO_VIRT_BASE + 0x00) |
| 20 | #define GPIO_BASE_HI (DOVE_GPIO_VIRT_BASE + 0x20) | 20 | #define GPIO_BASE_HI (DOVE_GPIO_VIRT_BASE + 0x20) |
| 21 | 21 | ||
| 22 | #define GPIO_BASE(pin) ((pin < 32) ? GPIO_BASE_LO : GPIO_BASE_HI) | 22 | #define GPIO_BASE(pin) ((pin < 32) ? GPIO_BASE_LO : \ |
| 23 | ((pin < 64) ? GPIO_BASE_HI : \ | ||
| 24 | DOVE_GPIO2_VIRT_BASE)) | ||
| 23 | 25 | ||
| 24 | #define GPIO_OUT(pin) (GPIO_BASE(pin) + 0x00) | 26 | #define GPIO_OUT(pin) (GPIO_BASE(pin) + 0x00) |
| 25 | #define GPIO_IO_CONF(pin) (GPIO_BASE(pin) + 0x04) | 27 | #define GPIO_IO_CONF(pin) (GPIO_BASE(pin) + 0x04) |
diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c new file mode 100644 index 000000000000..71db2bdf2f28 --- /dev/null +++ b/arch/arm/mach-dove/mpp.c | |||
| @@ -0,0 +1,212 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-dove/mpp.c | ||
| 3 | * | ||
| 4 | * MPP functions for Marvell Dove SoCs | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/gpio.h> | ||
| 13 | #include <linux/io.h> | ||
| 14 | |||
| 15 | #include <mach/dove.h> | ||
| 16 | |||
| 17 | #include "mpp.h" | ||
| 18 | |||
| 19 | #define MPP_NR_REGS 4 | ||
| 20 | #define MPP_CTRL(i) ((i) == 3 ? \ | ||
| 21 | DOVE_MPP_CTRL4_VIRT_BASE : \ | ||
| 22 | DOVE_MPP_VIRT_BASE + (i) * 4) | ||
| 23 | #define PMU_SIG_REGS 2 | ||
| 24 | #define PMU_SIG_CTRL(i) (DOVE_PMU_SIG_CTRL + (i) * 4) | ||
| 25 | |||
| 26 | struct dove_mpp_grp { | ||
| 27 | int start; | ||
| 28 | int end; | ||
| 29 | }; | ||
| 30 | |||
| 31 | static struct dove_mpp_grp dove_mpp_grp[] = { | ||
| 32 | [MPP_24_39] = { | ||
| 33 | .start = 24, | ||
| 34 | .end = 39, | ||
| 35 | }, | ||
| 36 | [MPP_40_45] = { | ||
| 37 | .start = 40, | ||
| 38 | .end = 45, | ||
| 39 | }, | ||
| 40 | [MPP_46_51] = { | ||
| 41 | .start = 40, | ||
| 42 | .end = 45, | ||
| 43 | }, | ||
| 44 | [MPP_58_61] = { | ||
| 45 | .start = 58, | ||
| 46 | .end = 61, | ||
| 47 | }, | ||
| 48 | [MPP_62_63] = { | ||
| 49 | .start = 62, | ||
| 50 | .end = 63, | ||
| 51 | }, | ||
| 52 | }; | ||
| 53 | |||
| 54 | static void dove_mpp_gpio_mode(int start, int end, int gpio_mode) | ||
| 55 | { | ||
| 56 | int i; | ||
| 57 | |||
| 58 | for (i = start; i <= end; i++) | ||
| 59 | orion_gpio_set_valid(i, gpio_mode); | ||
| 60 | } | ||
| 61 | |||
| 62 | static void dove_mpp_dump_regs(void) | ||
| 63 | { | ||
| 64 | #ifdef DEBUG | ||
| 65 | int i; | ||
| 66 | |||
| 67 | pr_debug("MPP_CTRL regs:"); | ||
| 68 | for (i = 0; i < MPP_NR_REGS; i++) | ||
| 69 | printk(" %08x", readl(MPP_CTRL(i))); | ||
| 70 | printk("\n"); | ||
| 71 | |||
| 72 | pr_debug("PMU_SIG_CTRL regs:"); | ||
| 73 | for (i = 0; i < PMU_SIG_REGS; i++) | ||
| 74 | printk(" %08x", readl(PMU_SIG_CTRL(i))); | ||
| 75 | printk("\n"); | ||
| 76 | |||
| 77 | pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n", readl(DOVE_PMU_MPP_GENERAL_CTRL)); | ||
| 78 | pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE)); | ||
| 79 | #endif | ||
| 80 | } | ||
| 81 | |||
| 82 | static void dove_mpp_cfg_nfc(int sel) | ||
| 83 | { | ||
| 84 | u32 mpp_gen_cfg = readl(DOVE_MPP_GENERAL_VIRT_BASE); | ||
| 85 | |||
| 86 | mpp_gen_cfg &= ~0x1; | ||
| 87 | mpp_gen_cfg |= sel; | ||
| 88 | writel(mpp_gen_cfg, DOVE_MPP_GENERAL_VIRT_BASE); | ||
| 89 | |||
| 90 | dove_mpp_gpio_mode(64, 71, GPIO_OUTPUT_OK); | ||
| 91 | } | ||
| 92 | |||
| 93 | static void dove_mpp_cfg_au1(int sel) | ||
| 94 | { | ||
| 95 | u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); | ||
| 96 | u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1); | ||
| 97 | u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE); | ||
| 98 | u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2); | ||
| 99 | |||
| 100 | mpp_ctrl4 &= ~(DOVE_AU1_GPIO_SEL); | ||
| 101 | ssp_ctrl1 &= ~(DOVE_SSP_ON_AU1); | ||
| 102 | mpp_gen_ctrl &= ~(DOVE_AU1_SPDIFO_GPIO_EN); | ||
| 103 | global_cfg_2 &= ~(DOVE_TWSI_OPTION3_GPIO); | ||
| 104 | |||
| 105 | if (!sel || sel == 0x2) | ||
| 106 | dove_mpp_gpio_mode(52, 57, 0); | ||
| 107 | else | ||
| 108 | dove_mpp_gpio_mode(52, 57, GPIO_OUTPUT_OK | GPIO_INPUT_OK); | ||
| 109 | |||
| 110 | if (sel & 0x1) { | ||
| 111 | global_cfg_2 |= DOVE_TWSI_OPTION3_GPIO; | ||
| 112 | dove_mpp_gpio_mode(56, 57, 0); | ||
| 113 | } | ||
| 114 | if (sel & 0x2) { | ||
| 115 | mpp_gen_ctrl |= DOVE_AU1_SPDIFO_GPIO_EN; | ||
| 116 | dove_mpp_gpio_mode(57, 57, GPIO_OUTPUT_OK | GPIO_INPUT_OK); | ||
| 117 | } | ||
| 118 | if (sel & 0x4) { | ||
| 119 | ssp_ctrl1 |= DOVE_SSP_ON_AU1; | ||
| 120 | dove_mpp_gpio_mode(52, 55, 0); | ||
| 121 | } | ||
| 122 | if (sel & 0x8) | ||
| 123 | mpp_ctrl4 |= DOVE_AU1_GPIO_SEL; | ||
| 124 | |||
| 125 | writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE); | ||
| 126 | writel(ssp_ctrl1, DOVE_SSP_CTRL_STATUS_1); | ||
| 127 | writel(mpp_gen_ctrl, DOVE_MPP_GENERAL_VIRT_BASE); | ||
| 128 | writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2); | ||
| 129 | } | ||
| 130 | |||
| 131 | static void dove_mpp_conf_grp(int num, int sel, u32 *mpp_ctrl) | ||
| 132 | { | ||
| 133 | int start = dove_mpp_grp[num].start; | ||
| 134 | int end = dove_mpp_grp[num].end; | ||
| 135 | int gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0; | ||
| 136 | |||
| 137 | *mpp_ctrl &= ~(0x1 << num); | ||
| 138 | *mpp_ctrl |= sel << num; | ||
| 139 | |||
| 140 | dove_mpp_gpio_mode(start, end, gpio_mode); | ||
| 141 | } | ||
| 142 | |||
| 143 | void __init dove_mpp_conf(unsigned int *mpp_list) | ||
| 144 | { | ||
| 145 | u32 mpp_ctrl[MPP_NR_REGS]; | ||
| 146 | u32 pmu_mpp_ctrl = 0; | ||
| 147 | u32 pmu_sig_ctrl[PMU_SIG_REGS]; | ||
| 148 | int i; | ||
| 149 | |||
| 150 | /* Initialize gpiolib. */ | ||
| 151 | orion_gpio_init(); | ||
| 152 | |||
| 153 | for (i = 0; i < MPP_NR_REGS; i++) | ||
| 154 | mpp_ctrl[i] = readl(MPP_CTRL(i)); | ||
| 155 | |||
| 156 | for (i = 0; i < PMU_SIG_REGS; i++) | ||
| 157 | pmu_sig_ctrl[i] = readl(PMU_SIG_CTRL(i)); | ||
| 158 | |||
| 159 | pmu_mpp_ctrl = readl(DOVE_PMU_MPP_GENERAL_CTRL); | ||
| 160 | |||
| 161 | dove_mpp_dump_regs(); | ||
| 162 | |||
| 163 | for ( ; *mpp_list != MPP_END; mpp_list++) { | ||
| 164 | unsigned int num = MPP_NUM(*mpp_list); | ||
| 165 | unsigned int sel = MPP_SEL(*mpp_list); | ||
| 166 | int shift, gpio_mode; | ||
| 167 | |||
| 168 | if (num > MPP_MAX) { | ||
| 169 | pr_err("dove: invalid MPP number (%u)\n", num); | ||
| 170 | continue; | ||
| 171 | } | ||
| 172 | |||
| 173 | if (*mpp_list & MPP_NFC_MASK) { | ||
| 174 | dove_mpp_cfg_nfc(sel); | ||
| 175 | continue; | ||
| 176 | } | ||
| 177 | |||
| 178 | if (*mpp_list & MPP_AU1_MASK) { | ||
| 179 | dove_mpp_cfg_au1(sel); | ||
| 180 | continue; | ||
| 181 | } | ||
| 182 | |||
| 183 | if (*mpp_list & MPP_GRP_MASK) { | ||
| 184 | dove_mpp_conf_grp(num, sel, &mpp_ctrl[3]); | ||
| 185 | continue; | ||
| 186 | } | ||
| 187 | |||
| 188 | shift = (num & 7) << 2; | ||
| 189 | if (*mpp_list & MPP_PMU_MASK) { | ||
| 190 | pmu_mpp_ctrl |= (0x1 << num); | ||
| 191 | pmu_sig_ctrl[num / 8] &= ~(0xf << shift); | ||
| 192 | pmu_sig_ctrl[num / 8] |= 0xf << shift; | ||
| 193 | gpio_mode = 0; | ||
| 194 | } else { | ||
| 195 | mpp_ctrl[num / 8] &= ~(0xf << shift); | ||
| 196 | mpp_ctrl[num / 8] |= sel << shift; | ||
| 197 | gpio_mode = GPIO_OUTPUT_OK | GPIO_INPUT_OK; | ||
| 198 | } | ||
| 199 | |||
| 200 | orion_gpio_set_valid(num, gpio_mode); | ||
| 201 | } | ||
| 202 | |||
| 203 | for (i = 0; i < MPP_NR_REGS; i++) | ||
| 204 | writel(mpp_ctrl[i], MPP_CTRL(i)); | ||
| 205 | |||
| 206 | for (i = 0; i < PMU_SIG_REGS; i++) | ||
| 207 | writel(pmu_sig_ctrl[i], PMU_SIG_CTRL(i)); | ||
| 208 | |||
| 209 | writel(pmu_mpp_ctrl, DOVE_PMU_MPP_GENERAL_CTRL); | ||
| 210 | |||
| 211 | dove_mpp_dump_regs(); | ||
| 212 | } | ||
diff --git a/arch/arm/mach-dove/mpp.h b/arch/arm/mach-dove/mpp.h new file mode 100644 index 000000000000..2a43ce413b15 --- /dev/null +++ b/arch/arm/mach-dove/mpp.h | |||
| @@ -0,0 +1,220 @@ | |||
| 1 | #ifndef __ARCH_DOVE_MPP_CODED_H | ||
| 2 | #define __ARCH_DOVE_MPP_CODED_H | ||
| 3 | |||
| 4 | #define MPP(_num, _mode, _pmu, _grp, _au1, _nfc) ( \ | ||
| 5 | /* MPP/group number */ ((_num) & 0xff) | \ | ||
| 6 | /* MPP select value */ (((_mode) & 0xf) << 8) | \ | ||
| 7 | /* MPP PMU */ ((!!(_pmu)) << 12) | \ | ||
| 8 | /* group flag */ ((!!(_grp)) << 13) | \ | ||
| 9 | /* AU1 flag */ ((!!(_au1)) << 14) | \ | ||
| 10 | /* NFCE flag */ ((!!(_nfc)) << 15)) | ||
| 11 | |||
| 12 | #define MPP_MAX 71 | ||
| 13 | |||
| 14 | #define MPP_NUM(x) ((x) & 0xff) | ||
| 15 | #define MPP_SEL(x) (((x) >> 8) & 0xf) | ||
| 16 | |||
| 17 | #define MPP_PMU_MASK MPP(0, 0x0, 1, 0, 0, 0) | ||
| 18 | #define MPP_GRP_MASK MPP(0, 0x0, 0, 1, 0, 0) | ||
| 19 | #define MPP_AU1_MASK MPP(0, 0x0, 0, 0, 1, 0) | ||
| 20 | #define MPP_NFC_MASK MPP(0, 0x0, 0, 0, 0, 1) | ||
| 21 | |||
| 22 | #define MPP_END MPP(0xff, 0xf, 1, 1, 1, 1) | ||
| 23 | |||
| 24 | #define MPP_PMU_DRIVE_0 0x1 | ||
| 25 | #define MPP_PMU_DRIVE_1 0x2 | ||
| 26 | #define MPP_PMU_SDI 0x3 | ||
| 27 | #define MPP_PMU_CPU_PWRDWN 0x4 | ||
| 28 | #define MPP_PMU_STBY_PWRDWN 0x5 | ||
| 29 | #define MPP_PMU_CORE_PWR_GOOD 0x8 | ||
| 30 | #define MPP_PMU_BAT_FAULT 0xa | ||
| 31 | #define MPP_PMU_EXT0_WU 0xb | ||
| 32 | #define MPP_PMU_EXT1_WU 0xc | ||
| 33 | #define MPP_PMU_EXT2_WU 0xd | ||
| 34 | #define MPP_PMU_BLINK 0xe | ||
| 35 | #define MPP_PMU(_num, _mode) MPP((_num), MPP_PMU_##_mode, 1, 0, 0, 0) | ||
| 36 | |||
| 37 | #define MPP_PIN(_num, _mode) MPP((_num), (_mode), 0, 0, 0, 0) | ||
| 38 | #define MPP_GRP(_grp, _mode) MPP((_grp), (_mode), 0, 1, 0, 0) | ||
| 39 | #define MPP_GRP_AU1(_mode) MPP(0, (_mode), 0, 0, 1, 0) | ||
| 40 | #define MPP_GRP_NFC(_mode) MPP(0, (_mode), 0, 0, 0, 1) | ||
| 41 | |||
| 42 | #define MPP0_GPIO0 MPP_PIN(0, 0x0) | ||
| 43 | #define MPP0_UA2_RTSn MPP_PIN(0, 0x2) | ||
| 44 | #define MPP0_SDIO0_CD MPP_PIN(0, 0x3) | ||
| 45 | #define MPP0_LCD0_PWM MPP_PIN(0, 0xf) | ||
| 46 | |||
| 47 | #define MPP1_GPIO1 MPP_PIN(1, 0x0) | ||
| 48 | #define MPP1_UA2_CTSn MPP_PIN(1, 0x2) | ||
| 49 | #define MPP1_SDIO0_WP MPP_PIN(1, 0x3) | ||
| 50 | #define MPP1_LCD1_PWM MPP_PIN(1, 0xf) | ||
| 51 | |||
| 52 | #define MPP2_GPIO2 MPP_PIN(2, 0x0) | ||
| 53 | #define MPP2_SATA_PRESENT MPP_PIN(2, 0x1) | ||
| 54 | #define MPP2_UA2_TXD MPP_PIN(2, 0x2) | ||
| 55 | #define MPP2_SDIO0_BUS_POWER MPP_PIN(2, 0x3) | ||
| 56 | #define MPP2_UA_RTSn1 MPP_PIN(2, 0x4) | ||
| 57 | |||
| 58 | #define MPP3_GPIO3 MPP_PIN(3, 0x0) | ||
| 59 | #define MPP3_SATA_ACT MPP_PIN(3, 0x1) | ||
| 60 | #define MPP3_UA2_RXD MPP_PIN(3, 0x2) | ||
| 61 | #define MPP3_SDIO0_LED_CTRL MPP_PIN(3, 0x3) | ||
| 62 | #define MPP3_UA_CTSn1 MPP_PIN(3, 0x4) | ||
| 63 | #define MPP3_SPI_LCD_CS1 MPP_PIN(3, 0xf) | ||
| 64 | |||
| 65 | #define MPP4_GPIO4 MPP_PIN(4, 0x0) | ||
| 66 | #define MPP4_UA3_RTSn MPP_PIN(4, 0x2) | ||
| 67 | #define MPP4_SDIO1_CD MPP_PIN(4, 0x3) | ||
| 68 | #define MPP4_SPI_1_MISO MPP_PIN(4, 0x4) | ||
| 69 | |||
| 70 | #define MPP5_GPIO5 MPP_PIN(5, 0x0) | ||
| 71 | #define MPP5_UA3_CTSn MPP_PIN(5, 0x2) | ||
| 72 | #define MPP5_SDIO1_WP MPP_PIN(5, 0x3) | ||
| 73 | #define MPP5_SPI_1_CS MPP_PIN(5, 0x4) | ||
| 74 | |||
| 75 | #define MPP6_GPIO6 MPP_PIN(6, 0x0) | ||
| 76 | #define MPP6_UA3_TXD MPP_PIN(6, 0x2) | ||
| 77 | #define MPP6_SDIO1_BUS_POWER MPP_PIN(6, 0x3) | ||
| 78 | #define MPP6_SPI_1_MOSI MPP_PIN(6, 0x4) | ||
| 79 | |||
| 80 | #define MPP7_GPIO7 MPP_PIN(7, 0x0) | ||
| 81 | #define MPP7_UA3_RXD MPP_PIN(7, 0x2) | ||
| 82 | #define MPP7_SDIO1_LED_CTRL MPP_PIN(7, 0x3) | ||
| 83 | #define MPP7_SPI_1_SCK MPP_PIN(7, 0x4) | ||
| 84 | |||
| 85 | #define MPP8_GPIO8 MPP_PIN(8, 0x0) | ||
| 86 | #define MPP8_WD_RST_OUT MPP_PIN(8, 0x1) | ||
| 87 | |||
| 88 | #define MPP9_GPIO9 MPP_PIN(9, 0x0) | ||
| 89 | #define MPP9_PEX1_CLKREQn MPP_PIN(9, 0x5) | ||
| 90 | |||
| 91 | #define MPP10_GPIO10 MPP_PIN(10, 0x0) | ||
| 92 | #define MPP10_SSP_SCLK MPP_PIN(10, 0x5) | ||
| 93 | |||
| 94 | #define MPP11_GPIO11 MPP_PIN(11, 0x0) | ||
| 95 | #define MPP11_SATA_PRESENT MPP_PIN(11, 0x1) | ||
| 96 | #define MPP11_SATA_ACT MPP_PIN(11, 0x2) | ||
| 97 | #define MPP11_SDIO0_LED_CTRL MPP_PIN(11, 0x3) | ||
| 98 | #define MPP11_SDIO1_LED_CTRL MPP_PIN(11, 0x4) | ||
| 99 | #define MPP11_PEX0_CLKREQn MPP_PIN(11, 0x5) | ||
| 100 | |||
| 101 | #define MPP12_GPIO12 MPP_PIN(12, 0x0) | ||
| 102 | #define MPP12_SATA_ACT MPP_PIN(12, 0x1) | ||
| 103 | #define MPP12_UA2_RTSn MPP_PIN(12, 0x2) | ||
| 104 | #define MPP12_AD0_I2S_EXT_MCLK MPP_PIN(12, 0x3) | ||
| 105 | #define MPP12_SDIO1_CD MPP_PIN(12, 0x4) | ||
| 106 | |||
| 107 | #define MPP13_GPIO13 MPP_PIN(13, 0x0) | ||
| 108 | #define MPP13_UA2_CTSn MPP_PIN(13, 0x2) | ||
| 109 | #define MPP13_AD1_I2S_EXT_MCLK MPP_PIN(13, 0x3) | ||
| 110 | #define MPP13_SDIO1WP MPP_PIN(13, 0x4) | ||
| 111 | #define MPP13_SSP_EXTCLK MPP_PIN(13, 0x5) | ||
| 112 | |||
| 113 | #define MPP14_GPIO14 MPP_PIN(14, 0x0) | ||
| 114 | #define MPP14_UA2_TXD MPP_PIN(14, 0x2) | ||
| 115 | #define MPP14_SDIO1_BUS_POWER MPP_PIN(14, 0x4) | ||
| 116 | #define MPP14_SSP_RXD MPP_PIN(14, 0x5) | ||
| 117 | |||
| 118 | #define MPP15_GPIO15 MPP_PIN(15, 0x0) | ||
| 119 | #define MPP15_UA2_RXD MPP_PIN(15, 0x2) | ||
| 120 | #define MPP15_SDIO1_LED_CTRL MPP_PIN(15, 0x4) | ||
| 121 | #define MPP15_SSP_SFRM MPP_PIN(15, 0x5) | ||
| 122 | |||
| 123 | #define MPP16_GPIO16 MPP_PIN(16, 0x0) | ||
| 124 | #define MPP16_UA3_RTSn MPP_PIN(16, 0x2) | ||
| 125 | #define MPP16_SDIO0_CD MPP_PIN(16, 0x3) | ||
| 126 | #define MPP16_SPI_LCD_CS1 MPP_PIN(16, 0x4) | ||
| 127 | #define MPP16_AC97_SDATA_IN1 MPP_PIN(16, 0x5) | ||
| 128 | |||
| 129 | #define MPP17_GPIO17 MPP_PIN(17, 0x0) | ||
| 130 | #define MPP17_AC97_SYSCLK_OUT MPP_PIN(17, 0x1) | ||
| 131 | #define MPP17_UA3_CTSn MPP_PIN(17, 0x2) | ||
| 132 | #define MPP17_SDIO0_WP MPP_PIN(17, 0x3) | ||
| 133 | #define MPP17_TW_SDA2 MPP_PIN(17, 0x4) | ||
| 134 | #define MPP17_AC97_SDATA_IN2 MPP_PIN(17, 0x5) | ||
| 135 | |||
| 136 | #define MPP18_GPIO18 MPP_PIN(18, 0x0) | ||
| 137 | #define MPP18_UA3_TXD MPP_PIN(18, 0x2) | ||
| 138 | #define MPP18_SDIO0_BUS_POWER MPP_PIN(18, 0x3) | ||
| 139 | #define MPP18_LCD0_PWM MPP_PIN(18, 0x4) | ||
| 140 | #define MPP18_AC_SDATA_IN3 MPP_PIN(18, 0x5) | ||
| 141 | |||
| 142 | #define MPP19_GPIO19 MPP_PIN(19, 0x0) | ||
| 143 | #define MPP19_UA3_RXD MPP_PIN(19, 0x2) | ||
| 144 | #define MPP19_SDIO0_LED_CTRL MPP_PIN(19, 0x3) | ||
| 145 | #define MPP19_TW_SCK2 MPP_PIN(19, 0x4) | ||
| 146 | |||
| 147 | #define MPP20_GPIO20 MPP_PIN(20, 0x0) | ||
| 148 | #define MPP20_AC97_SYSCLK_OUT MPP_PIN(20, 0x1) | ||
| 149 | #define MPP20_SPI_LCD_MISO MPP_PIN(20, 0x2) | ||
| 150 | #define MPP20_SDIO1_CD MPP_PIN(20, 0x3) | ||
| 151 | #define MPP20_SDIO0_CD MPP_PIN(20, 0x5) | ||
| 152 | #define MPP20_SPI_1_MISO MPP_PIN(20, 0x6) | ||
| 153 | |||
| 154 | #define MPP21_GPIO21 MPP_PIN(21, 0x0) | ||
| 155 | #define MPP21_UA1_RTSn MPP_PIN(21, 0x1) | ||
| 156 | #define MPP21_SPI_LCD_CS0 MPP_PIN(21, 0x2) | ||
| 157 | #define MPP21_SDIO1_WP MPP_PIN(21, 0x3) | ||
| 158 | #define MPP21_SSP_SFRM MPP_PIN(21, 0x4) | ||
| 159 | #define MPP21_SDIO0_WP MPP_PIN(21, 0x5) | ||
| 160 | #define MPP21_SPI_1_CS MPP_PIN(21, 0x6) | ||
| 161 | |||
| 162 | #define MPP22_GPIO22 MPP_PIN(22, 0x0) | ||
| 163 | #define MPP22_UA1_CTSn MPP_PIN(22, 0x1) | ||
| 164 | #define MPP22_SPI_LCD_MOSI MPP_PIN(22, 0x2) | ||
| 165 | #define MPP22_SDIO1_BUS_POWER MPP_PIN(22, 0x3) | ||
| 166 | #define MPP22_SSP_TXD MPP_PIN(22, 0x4) | ||
| 167 | #define MPP22_SDIO0_BUS_POWER MPP_PIN(22, 0x5) | ||
| 168 | #define MPP22_SPI_1_MOSI MPP_PIN(22, 0x6) | ||
| 169 | |||
| 170 | #define MPP23_GPIO23 MPP_PIN(23, 0x0) | ||
| 171 | #define MPP23_SPI_LCD_SCK MPP_PIN(23, 0x2) | ||
| 172 | #define MPP23_SDIO1_LED_CTRL MPP_PIN(23, 0x3) | ||
| 173 | #define MPP23_SSP_SCLK MPP_PIN(23, 0x4) | ||
| 174 | #define MPP23_SDIO0_LED_CTRL MPP_PIN(23, 0x5) | ||
| 175 | #define MPP23_SPI_1_SCK MPP_PIN(23, 0x6) | ||
| 176 | |||
| 177 | /* for MPP groups _num is a group index */ | ||
| 178 | enum dove_mpp_grp_idx { | ||
| 179 | MPP_24_39 = 2, | ||
| 180 | MPP_40_45 = 0, | ||
| 181 | MPP_46_51 = 1, | ||
| 182 | MPP_58_61 = 5, | ||
| 183 | MPP_62_63 = 4, | ||
| 184 | }; | ||
| 185 | |||
| 186 | #define MPP24_39_GPIO MPP_GRP(MPP_24_39, 0x1) | ||
| 187 | #define MPP24_39_CAM MPP_GRP(MPP_24_39, 0x0) | ||
| 188 | |||
| 189 | #define MPP40_45_GPIO MPP_GRP(MPP_40_45, 0x1) | ||
| 190 | #define MPP40_45_SD0 MPP_GRP(MPP_40_45, 0x0) | ||
| 191 | |||
| 192 | #define MPP46_51_GPIO MPP_GRP(MPP_46_51, 0x1) | ||
| 193 | #define MPP46_51_SD1 MPP_GRP(MPP_46_51, 0x0) | ||
| 194 | |||
| 195 | #define MPP58_61_GPIO MPP_GRP(MPP_58_61, 0x1) | ||
| 196 | #define MPP58_61_SPI MPP_GRP(MPP_58_61, 0x0) | ||
| 197 | |||
| 198 | #define MPP62_63_GPIO MPP_GRP(MPP_62_63, 0x1) | ||
| 199 | #define MPP62_63_UA1 MPP_GRP(MPP_62_63, 0x0) | ||
| 200 | |||
| 201 | /* The MPP[64:71] control differs from other groups */ | ||
| 202 | #define MPP64_71_GPO MPP_GRP_NFC(0x1) | ||
| 203 | #define MPP64_71_NFC MPP_GRP_NFC(0x0) | ||
| 204 | |||
| 205 | /* | ||
| 206 | * The MPP[52:57] functionality is encoded by 4 bits in different | ||
| 207 | * registers. The _num field in this case encodes those bits in | ||
| 208 | * correspodence with Table 135 of 88AP510 Functional specification | ||
| 209 | */ | ||
| 210 | #define MPP52_57_AU1 MPP_GRP_AU1(0x0) | ||
| 211 | #define MPP52_57_AU1_GPIO57 MPP_GRP_AU1(0x2) | ||
| 212 | #define MPP52_57_GPIO MPP_GRP_AU1(0xa) | ||
| 213 | #define MPP52_57_TW_GPIO MPP_GRP_AU1(0xb) | ||
| 214 | #define MPP52_57_AU1_SSP MPP_GRP_AU1(0xc) | ||
| 215 | #define MPP52_57_SSP_GPIO MPP_GRP_AU1(0xe) | ||
| 216 | #define MPP52_57_SSP_TW MPP_GRP_AU1(0xf) | ||
| 217 | |||
| 218 | void dove_mpp_conf(unsigned int *mpp_list); | ||
| 219 | |||
| 220 | #endif /* __ARCH_DOVE_MPP_CODED_H */ | ||
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c index ef06c66a6f16..ca4de7105097 100644 --- a/arch/arm/mach-ep93xx/clock.c +++ b/arch/arm/mach-ep93xx/clock.c | |||
| @@ -19,10 +19,10 @@ | |||
| 19 | #include <linux/string.h> | 19 | #include <linux/string.h> |
| 20 | #include <linux/io.h> | 20 | #include <linux/io.h> |
| 21 | #include <linux/spinlock.h> | 21 | #include <linux/spinlock.h> |
| 22 | #include <linux/clkdev.h> | ||
| 22 | 23 | ||
| 23 | #include <mach/hardware.h> | 24 | #include <mach/hardware.h> |
| 24 | 25 | ||
| 25 | #include <asm/clkdev.h> | ||
| 26 | #include <asm/div64.h> | 26 | #include <asm/div64.h> |
| 27 | 27 | ||
| 28 | 28 | ||
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 197f9e241cff..17d2e608a214 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig | |||
| @@ -1,13 +1,37 @@ | |||
| 1 | config IMX_HAVE_DMA_V1 | 1 | config IMX_HAVE_DMA_V1 |
| 2 | bool | 2 | bool |
| 3 | 3 | ||
| 4 | if ARCH_MX1 | ||
| 5 | |||
| 6 | config SOC_IMX1 | 4 | config SOC_IMX1 |
| 5 | bool | ||
| 7 | select CPU_ARM920T | 6 | select CPU_ARM920T |
| 8 | select IMX_HAVE_DMA_V1 | 7 | select IMX_HAVE_DMA_V1 |
| 9 | select IMX_HAVE_IOMUX_V1 | 8 | select IMX_HAVE_IOMUX_V1 |
| 9 | select MXC_AVIC | ||
| 10 | |||
| 11 | config SOC_IMX21 | ||
| 12 | bool | ||
| 13 | select CPU_ARM926T | ||
| 14 | select ARCH_MXC_AUDMUX_V1 | ||
| 15 | select IMX_HAVE_DMA_V1 | ||
| 16 | select IMX_HAVE_IOMUX_V1 | ||
| 17 | select MXC_AVIC | ||
| 18 | |||
| 19 | config SOC_IMX25 | ||
| 10 | bool | 20 | bool |
| 21 | select CPU_ARM926T | ||
| 22 | select ARCH_MXC_AUDMUX_V2 | ||
| 23 | select ARCH_MXC_IOMUX_V3 | ||
| 24 | select MXC_AVIC | ||
| 25 | |||
| 26 | config SOC_IMX27 | ||
| 27 | bool | ||
| 28 | select CPU_ARM926T | ||
| 29 | select ARCH_MXC_AUDMUX_V1 | ||
| 30 | select IMX_HAVE_DMA_V1 | ||
| 31 | select IMX_HAVE_IOMUX_V1 | ||
| 32 | select MXC_AVIC | ||
| 33 | |||
| 34 | if ARCH_MX1 | ||
| 11 | 35 | ||
| 12 | comment "MX1 platforms:" | 36 | comment "MX1 platforms:" |
| 13 | config MACH_MXLADS | 37 | config MACH_MXLADS |
| @@ -31,33 +55,17 @@ endif | |||
| 31 | 55 | ||
| 32 | if ARCH_MX2 | 56 | if ARCH_MX2 |
| 33 | 57 | ||
| 34 | config SOC_IMX21 | ||
| 35 | select CPU_ARM926T | ||
| 36 | select ARCH_MXC_AUDMUX_V1 | ||
| 37 | select IMX_HAVE_DMA_V1 | ||
| 38 | select IMX_HAVE_IOMUX_V1 | ||
| 39 | bool | ||
| 40 | |||
| 41 | config SOC_IMX27 | ||
| 42 | select CPU_ARM926T | ||
| 43 | select ARCH_MXC_AUDMUX_V1 | ||
| 44 | select IMX_HAVE_DMA_V1 | ||
| 45 | select IMX_HAVE_IOMUX_V1 | ||
| 46 | bool | ||
| 47 | |||
| 48 | choice | 58 | choice |
| 49 | prompt "CPUs:" | 59 | prompt "CPUs:" |
| 50 | default MACH_MX21 | 60 | default MACH_MX21 |
| 51 | 61 | ||
| 52 | config MACH_MX21 | 62 | config MACH_MX21 |
| 53 | bool "i.MX21 support" | 63 | bool "i.MX21 support" |
| 54 | select SOC_IMX21 | ||
| 55 | help | 64 | help |
| 56 | This enables support for Freescale's MX2 based i.MX21 processor. | 65 | This enables support for Freescale's MX2 based i.MX21 processor. |
| 57 | 66 | ||
| 58 | config MACH_MX27 | 67 | config MACH_MX27 |
| 59 | bool "i.MX27 support" | 68 | bool "i.MX27 support" |
| 60 | select SOC_IMX27 | ||
| 61 | help | 69 | help |
| 62 | This enables support for Freescale's MX2 based i.MX27 processor. | 70 | This enables support for Freescale's MX2 based i.MX27 processor. |
| 63 | 71 | ||
| @@ -71,7 +79,10 @@ comment "MX21 platforms:" | |||
| 71 | 79 | ||
| 72 | config MACH_MX21ADS | 80 | config MACH_MX21ADS |
| 73 | bool "MX21ADS platform" | 81 | bool "MX21ADS platform" |
| 82 | select SOC_IMX21 | ||
| 83 | select IMX_HAVE_PLATFORM_IMX_FB | ||
| 74 | select IMX_HAVE_PLATFORM_IMX_UART | 84 | select IMX_HAVE_PLATFORM_IMX_UART |
| 85 | select IMX_HAVE_PLATFORM_MXC_MMC | ||
| 75 | select IMX_HAVE_PLATFORM_MXC_NAND | 86 | select IMX_HAVE_PLATFORM_MXC_NAND |
| 76 | help | 87 | help |
| 77 | Include support for MX21ADS platform. This includes specific | 88 | Include support for MX21ADS platform. This includes specific |
| @@ -79,24 +90,79 @@ config MACH_MX21ADS | |||
| 79 | 90 | ||
| 80 | endif | 91 | endif |
| 81 | 92 | ||
| 93 | if ARCH_MX25 | ||
| 94 | |||
| 95 | comment "MX25 platforms:" | ||
| 96 | |||
| 97 | config MACH_MX25_3DS | ||
| 98 | bool "Support MX25PDK (3DS) Platform" | ||
| 99 | select SOC_IMX25 | ||
| 100 | select IMX_HAVE_PLATFORM_FSL_USB2_UDC | ||
| 101 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
| 102 | select IMX_HAVE_PLATFORM_IMXDI_RTC | ||
| 103 | select IMX_HAVE_PLATFORM_IMX_FB | ||
| 104 | select IMX_HAVE_PLATFORM_IMX_KEYPAD | ||
| 105 | select IMX_HAVE_PLATFORM_IMX_UART | ||
| 106 | select IMX_HAVE_PLATFORM_MXC_EHCI | ||
| 107 | select IMX_HAVE_PLATFORM_MXC_NAND | ||
| 108 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
| 109 | |||
| 110 | config MACH_EUKREA_CPUIMX25 | ||
| 111 | bool "Support Eukrea CPUIMX25 Platform" | ||
| 112 | select SOC_IMX25 | ||
| 113 | select IMX_HAVE_PLATFORM_FLEXCAN | ||
| 114 | select IMX_HAVE_PLATFORM_FSL_USB2_UDC | ||
| 115 | select IMX_HAVE_PLATFORM_IMXDI_RTC | ||
| 116 | select IMX_HAVE_PLATFORM_IMX_FB | ||
| 117 | select IMX_HAVE_PLATFORM_IMX_I2C | ||
| 118 | select IMX_HAVE_PLATFORM_IMX_UART | ||
| 119 | select IMX_HAVE_PLATFORM_MXC_EHCI | ||
| 120 | select IMX_HAVE_PLATFORM_MXC_NAND | ||
| 121 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
| 122 | select MXC_ULPI if USB_ULPI | ||
| 123 | |||
| 124 | choice | ||
| 125 | prompt "Baseboard" | ||
| 126 | depends on MACH_EUKREA_CPUIMX25 | ||
| 127 | default MACH_EUKREA_MBIMXSD25_BASEBOARD | ||
| 128 | |||
| 129 | config MACH_EUKREA_MBIMXSD25_BASEBOARD | ||
| 130 | bool "Eukrea MBIMXSD development board" | ||
| 131 | select IMX_HAVE_PLATFORM_IMX_SSI | ||
| 132 | help | ||
| 133 | This adds board specific devices that can be found on Eukrea's | ||
| 134 | MBIMXSD evaluation board. | ||
| 135 | |||
| 136 | endchoice | ||
| 137 | |||
| 138 | endif | ||
| 139 | |||
| 82 | if MACH_MX27 | 140 | if MACH_MX27 |
| 83 | 141 | ||
| 84 | comment "MX27 platforms:" | 142 | comment "MX27 platforms:" |
| 85 | 143 | ||
| 86 | config MACH_MX27ADS | 144 | config MACH_MX27ADS |
| 87 | bool "MX27ADS platform" | 145 | bool "MX27ADS platform" |
| 146 | select SOC_IMX27 | ||
| 147 | select IMX_HAVE_PLATFORM_IMX_FB | ||
| 88 | select IMX_HAVE_PLATFORM_IMX_I2C | 148 | select IMX_HAVE_PLATFORM_IMX_I2C |
| 89 | select IMX_HAVE_PLATFORM_IMX_UART | 149 | select IMX_HAVE_PLATFORM_IMX_UART |
| 150 | select IMX_HAVE_PLATFORM_MXC_MMC | ||
| 90 | select IMX_HAVE_PLATFORM_MXC_NAND | 151 | select IMX_HAVE_PLATFORM_MXC_NAND |
| 152 | select IMX_HAVE_PLATFORM_MXC_W1 | ||
| 91 | help | 153 | help |
| 92 | Include support for MX27ADS platform. This includes specific | 154 | Include support for MX27ADS platform. This includes specific |
| 93 | configurations for the board and its peripherals. | 155 | configurations for the board and its peripherals. |
| 94 | 156 | ||
| 95 | config MACH_PCM038 | 157 | config MACH_PCM038 |
| 96 | bool "Phytec phyCORE-i.MX27 CPU module (pcm038)" | 158 | bool "Phytec phyCORE-i.MX27 CPU module (pcm038)" |
| 159 | select SOC_IMX27 | ||
| 160 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
| 97 | select IMX_HAVE_PLATFORM_IMX_I2C | 161 | select IMX_HAVE_PLATFORM_IMX_I2C |
| 98 | select IMX_HAVE_PLATFORM_IMX_UART | 162 | select IMX_HAVE_PLATFORM_IMX_UART |
| 163 | select IMX_HAVE_PLATFORM_MXC_EHCI | ||
| 99 | select IMX_HAVE_PLATFORM_MXC_NAND | 164 | select IMX_HAVE_PLATFORM_MXC_NAND |
| 165 | select IMX_HAVE_PLATFORM_MXC_W1 | ||
| 100 | select IMX_HAVE_PLATFORM_SPI_IMX | 166 | select IMX_HAVE_PLATFORM_SPI_IMX |
| 101 | select MXC_ULPI if USB_ULPI | 167 | select MXC_ULPI if USB_ULPI |
| 102 | help | 168 | help |
| @@ -109,8 +175,9 @@ choice | |||
| 109 | default MACH_PCM970_BASEBOARD | 175 | default MACH_PCM970_BASEBOARD |
| 110 | 176 | ||
| 111 | config MACH_PCM970_BASEBOARD | 177 | config MACH_PCM970_BASEBOARD |
| 112 | prompt "PHYTEC PCM970 development board" | 178 | bool "PHYTEC PCM970 development board" |
| 113 | bool | 179 | select IMX_HAVE_PLATFORM_IMX_FB |
| 180 | select IMX_HAVE_PLATFORM_MXC_MMC | ||
| 114 | help | 181 | help |
| 115 | This adds board specific devices that can be found on Phytec's | 182 | This adds board specific devices that can be found on Phytec's |
| 116 | PCM970 evaluation board. | 183 | PCM970 evaluation board. |
| @@ -119,9 +186,14 @@ endchoice | |||
| 119 | 186 | ||
| 120 | config MACH_CPUIMX27 | 187 | config MACH_CPUIMX27 |
| 121 | bool "Eukrea CPUIMX27 module" | 188 | bool "Eukrea CPUIMX27 module" |
| 189 | select SOC_IMX27 | ||
| 190 | select IMX_HAVE_PLATFORM_FSL_USB2_UDC | ||
| 191 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
| 122 | select IMX_HAVE_PLATFORM_IMX_I2C | 192 | select IMX_HAVE_PLATFORM_IMX_I2C |
| 123 | select IMX_HAVE_PLATFORM_IMX_UART | 193 | select IMX_HAVE_PLATFORM_IMX_UART |
| 194 | select IMX_HAVE_PLATFORM_MXC_EHCI | ||
| 124 | select IMX_HAVE_PLATFORM_MXC_NAND | 195 | select IMX_HAVE_PLATFORM_MXC_NAND |
| 196 | select IMX_HAVE_PLATFORM_MXC_W1 | ||
| 125 | select MXC_ULPI if USB_ULPI | 197 | select MXC_ULPI if USB_ULPI |
| 126 | help | 198 | help |
| 127 | Include support for Eukrea CPUIMX27 platform. This includes | 199 | Include support for Eukrea CPUIMX27 platform. This includes |
| @@ -130,6 +202,7 @@ config MACH_CPUIMX27 | |||
| 130 | config MACH_EUKREA_CPUIMX27_USESDHC2 | 202 | config MACH_EUKREA_CPUIMX27_USESDHC2 |
| 131 | bool "CPUIMX27 integrates SDHC2 module" | 203 | bool "CPUIMX27 integrates SDHC2 module" |
| 132 | depends on MACH_CPUIMX27 | 204 | depends on MACH_CPUIMX27 |
| 205 | select IMX_HAVE_PLATFORM_MXC_MMC | ||
| 133 | help | 206 | help |
| 134 | This adds support for the internal SDHC2 used on CPUIMX27 | 207 | This adds support for the internal SDHC2 used on CPUIMX27 |
| 135 | for wifi or eMMC. | 208 | for wifi or eMMC. |
| @@ -148,8 +221,11 @@ choice | |||
| 148 | 221 | ||
| 149 | config MACH_EUKREA_MBIMX27_BASEBOARD | 222 | config MACH_EUKREA_MBIMX27_BASEBOARD |
| 150 | bool "Eukrea MBIMX27 development board" | 223 | bool "Eukrea MBIMX27 development board" |
| 224 | select IMX_HAVE_PLATFORM_IMX_FB | ||
| 225 | select IMX_HAVE_PLATFORM_IMX_KEYPAD | ||
| 151 | select IMX_HAVE_PLATFORM_IMX_SSI | 226 | select IMX_HAVE_PLATFORM_IMX_SSI |
| 152 | select IMX_HAVE_PLATFORM_IMX_UART | 227 | select IMX_HAVE_PLATFORM_IMX_UART |
| 228 | select IMX_HAVE_PLATFORM_MXC_MMC | ||
| 153 | select IMX_HAVE_PLATFORM_SPI_IMX | 229 | select IMX_HAVE_PLATFORM_SPI_IMX |
| 154 | help | 230 | help |
| 155 | This adds board specific devices that can be found on Eukrea's | 231 | This adds board specific devices that can be found on Eukrea's |
| @@ -159,15 +235,26 @@ endchoice | |||
| 159 | 235 | ||
| 160 | config MACH_MX27_3DS | 236 | config MACH_MX27_3DS |
| 161 | bool "MX27PDK platform" | 237 | bool "MX27PDK platform" |
| 238 | select SOC_IMX27 | ||
| 239 | select IMX_HAVE_PLATFORM_FSL_USB2_UDC | ||
| 240 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
| 241 | select IMX_HAVE_PLATFORM_IMX_KEYPAD | ||
| 162 | select IMX_HAVE_PLATFORM_IMX_UART | 242 | select IMX_HAVE_PLATFORM_IMX_UART |
| 243 | select IMX_HAVE_PLATFORM_MXC_EHCI | ||
| 244 | select IMX_HAVE_PLATFORM_MXC_MMC | ||
| 245 | select IMX_HAVE_PLATFORM_SPI_IMX | ||
| 246 | select MXC_ULPI if USB_ULPI | ||
| 163 | help | 247 | help |
| 164 | Include support for MX27PDK platform. This includes specific | 248 | Include support for MX27PDK platform. This includes specific |
| 165 | configurations for the board and its peripherals. | 249 | configurations for the board and its peripherals. |
| 166 | 250 | ||
| 167 | config MACH_IMX27_VISSTRIM_M10 | 251 | config MACH_IMX27_VISSTRIM_M10 |
| 168 | bool "Vista Silicon i.MX27 Visstrim_m10" | 252 | bool "Vista Silicon i.MX27 Visstrim_m10" |
| 253 | select SOC_IMX27 | ||
| 169 | select IMX_HAVE_PLATFORM_IMX_I2C | 254 | select IMX_HAVE_PLATFORM_IMX_I2C |
| 170 | select IMX_HAVE_PLATFORM_IMX_UART | 255 | select IMX_HAVE_PLATFORM_IMX_UART |
| 256 | select IMX_HAVE_PLATFORM_MXC_MMC | ||
| 257 | select IMX_HAVE_PLATFORM_MXC_EHCI | ||
| 171 | help | 258 | help |
| 172 | Include support for Visstrim_m10 platform and its different variants. | 259 | Include support for Visstrim_m10 platform and its different variants. |
| 173 | This includes specific configurations for the board and its | 260 | This includes specific configurations for the board and its |
| @@ -175,6 +262,7 @@ config MACH_IMX27_VISSTRIM_M10 | |||
| 175 | 262 | ||
| 176 | config MACH_IMX27LITE | 263 | config MACH_IMX27LITE |
| 177 | bool "LogicPD MX27 LITEKIT platform" | 264 | bool "LogicPD MX27 LITEKIT platform" |
| 265 | select SOC_IMX27 | ||
| 178 | select IMX_HAVE_PLATFORM_IMX_UART | 266 | select IMX_HAVE_PLATFORM_IMX_UART |
| 179 | help | 267 | help |
| 180 | Include support for MX27 LITEKIT platform. This includes specific | 268 | Include support for MX27 LITEKIT platform. This includes specific |
| @@ -182,10 +270,17 @@ config MACH_IMX27LITE | |||
| 182 | 270 | ||
| 183 | config MACH_PCA100 | 271 | config MACH_PCA100 |
| 184 | bool "Phytec phyCARD-s (pca100)" | 272 | bool "Phytec phyCARD-s (pca100)" |
| 273 | select SOC_IMX27 | ||
| 274 | select IMX_HAVE_PLATFORM_FSL_USB2_UDC | ||
| 275 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
| 276 | select IMX_HAVE_PLATFORM_IMX_FB | ||
| 185 | select IMX_HAVE_PLATFORM_IMX_I2C | 277 | select IMX_HAVE_PLATFORM_IMX_I2C |
| 186 | select IMX_HAVE_PLATFORM_IMX_SSI | 278 | select IMX_HAVE_PLATFORM_IMX_SSI |
| 187 | select IMX_HAVE_PLATFORM_IMX_UART | 279 | select IMX_HAVE_PLATFORM_IMX_UART |
| 280 | select IMX_HAVE_PLATFORM_MXC_EHCI | ||
| 281 | select IMX_HAVE_PLATFORM_MXC_MMC | ||
| 188 | select IMX_HAVE_PLATFORM_MXC_NAND | 282 | select IMX_HAVE_PLATFORM_MXC_NAND |
| 283 | select IMX_HAVE_PLATFORM_MXC_W1 | ||
| 189 | select IMX_HAVE_PLATFORM_SPI_IMX | 284 | select IMX_HAVE_PLATFORM_SPI_IMX |
| 190 | select MXC_ULPI if USB_ULPI | 285 | select MXC_ULPI if USB_ULPI |
| 191 | help | 286 | help |
| @@ -194,8 +289,11 @@ config MACH_PCA100 | |||
| 194 | 289 | ||
| 195 | config MACH_MXT_TD60 | 290 | config MACH_MXT_TD60 |
| 196 | bool "Maxtrack i-MXT TD60" | 291 | bool "Maxtrack i-MXT TD60" |
| 292 | select SOC_IMX27 | ||
| 293 | select IMX_HAVE_PLATFORM_IMX_FB | ||
| 197 | select IMX_HAVE_PLATFORM_IMX_I2C | 294 | select IMX_HAVE_PLATFORM_IMX_I2C |
| 198 | select IMX_HAVE_PLATFORM_IMX_UART | 295 | select IMX_HAVE_PLATFORM_IMX_UART |
| 296 | select IMX_HAVE_PLATFORM_MXC_MMC | ||
| 199 | select IMX_HAVE_PLATFORM_MXC_NAND | 297 | select IMX_HAVE_PLATFORM_MXC_NAND |
| 200 | help | 298 | help |
| 201 | Include support for i-MXT (aka td60) platform. This | 299 | Include support for i-MXT (aka td60) platform. This |
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 5582692bb176..77100bf26153 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile | |||
| @@ -4,13 +4,13 @@ | |||
| 4 | 4 | ||
| 5 | # Object file lists. | 5 | # Object file lists. |
| 6 | 6 | ||
| 7 | obj-y := devices.o | ||
| 8 | |||
| 9 | obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o | 7 | obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o |
| 10 | 8 | ||
| 11 | obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o | 9 | obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o |
| 12 | obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o | 10 | obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o |
| 13 | 11 | ||
| 12 | obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o | ||
| 13 | |||
| 14 | obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o | 14 | obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o |
| 15 | obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o | 15 | obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o |
| 16 | 16 | ||
| @@ -22,6 +22,10 @@ obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o | |||
| 22 | 22 | ||
| 23 | obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o | 23 | obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o |
| 24 | 24 | ||
| 25 | obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o | ||
| 26 | obj-$(CONFIG_MACH_EUKREA_CPUIMX25) += mach-eukrea_cpuimx25.o | ||
| 27 | obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd25-baseboard.o | ||
| 28 | |||
| 25 | obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o | 29 | obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o |
| 26 | obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o | 30 | obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o |
| 27 | obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o | 31 | obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o |
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot index 7988a85cf07d..3953d60bff0b 100644 --- a/arch/arm/mach-imx/Makefile.boot +++ b/arch/arm/mach-imx/Makefile.boot | |||
| @@ -6,6 +6,10 @@ zreladdr-$(CONFIG_MACH_MX21) := 0xC0008000 | |||
| 6 | params_phys-$(CONFIG_MACH_MX21) := 0xC0000100 | 6 | params_phys-$(CONFIG_MACH_MX21) := 0xC0000100 |
| 7 | initrd_phys-$(CONFIG_MACH_MX21) := 0xC0800000 | 7 | initrd_phys-$(CONFIG_MACH_MX21) := 0xC0800000 |
| 8 | 8 | ||
| 9 | zreladdr-$(CONFIG_ARCH_MX25) := 0x80008000 | ||
| 10 | params_phys-$(CONFIG_ARCH_MX25) := 0x80000100 | ||
| 11 | initrd_phys-$(CONFIG_ARCH_MX25) := 0x80800000 | ||
| 12 | |||
| 9 | zreladdr-$(CONFIG_MACH_MX27) := 0xA0008000 | 13 | zreladdr-$(CONFIG_MACH_MX27) := 0xA0008000 |
| 10 | params_phys-$(CONFIG_MACH_MX27) := 0xA0000100 | 14 | params_phys-$(CONFIG_MACH_MX27) := 0xA0000100 |
| 11 | initrd_phys-$(CONFIG_MACH_MX27) := 0xA0800000 | 15 | initrd_phys-$(CONFIG_MACH_MX27) := 0xA0800000 |
diff --git a/arch/arm/mach-imx/clock-imx1.c b/arch/arm/mach-imx/clock-imx1.c index daca30b2d5b1..3938a563b280 100644 --- a/arch/arm/mach-imx/clock-imx1.c +++ b/arch/arm/mach-imx/clock-imx1.c | |||
| @@ -22,8 +22,7 @@ | |||
| 22 | #include <linux/err.h> | 22 | #include <linux/err.h> |
| 23 | #include <linux/clk.h> | 23 | #include <linux/clk.h> |
| 24 | #include <linux/io.h> | 24 | #include <linux/io.h> |
| 25 | 25 | #include <linux/clkdev.h> | |
| 26 | #include <asm/clkdev.h> | ||
| 27 | 26 | ||
| 28 | #include <mach/clock.h> | 27 | #include <mach/clock.h> |
| 29 | #include <mach/hardware.h> | 28 | #include <mach/hardware.h> |
diff --git a/arch/arm/mach-imx/clock-imx21.c b/arch/arm/mach-imx/clock-imx21.c index cf15ea516a72..bf30a8c7ce6f 100644 --- a/arch/arm/mach-imx/clock-imx21.c +++ b/arch/arm/mach-imx/clock-imx21.c | |||
| @@ -21,11 +21,11 @@ | |||
| 21 | #include <linux/clk.h> | 21 | #include <linux/clk.h> |
| 22 | #include <linux/io.h> | 22 | #include <linux/io.h> |
| 23 | #include <linux/module.h> | 23 | #include <linux/module.h> |
| 24 | #include <linux/clkdev.h> | ||
| 24 | 25 | ||
| 25 | #include <mach/clock.h> | 26 | #include <mach/clock.h> |
| 26 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
| 27 | #include <mach/common.h> | 28 | #include <mach/common.h> |
| 28 | #include <asm/clkdev.h> | ||
| 29 | #include <asm/div64.h> | 29 | #include <asm/div64.h> |
| 30 | 30 | ||
| 31 | #define IO_ADDR_CCM(off) (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off))) | 31 | #define IO_ADDR_CCM(off) (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off))) |
| @@ -1185,7 +1185,7 @@ static struct clk_lookup lookups[] = { | |||
| 1185 | _REGISTER_CLOCK(NULL, "brom", brom_clk) | 1185 | _REGISTER_CLOCK(NULL, "brom", brom_clk) |
| 1186 | _REGISTER_CLOCK(NULL, "emma", emma_clk[0]) | 1186 | _REGISTER_CLOCK(NULL, "emma", emma_clk[0]) |
| 1187 | _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk[0]) | 1187 | _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk[0]) |
| 1188 | _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk) | 1188 | _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk) |
| 1189 | _REGISTER_CLOCK(NULL, "gpio", gpio_clk) | 1189 | _REGISTER_CLOCK(NULL, "gpio", gpio_clk) |
| 1190 | _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk) | 1190 | _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk) |
| 1191 | _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk) | 1191 | _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk) |
diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-imx/clock-imx25.c index 9e4a5578c2fb..daa0165b6772 100644 --- a/arch/arm/mach-mx25/clock.c +++ b/arch/arm/mach-imx/clock-imx25.c | |||
| @@ -21,8 +21,7 @@ | |||
| 21 | #include <linux/list.h> | 21 | #include <linux/list.h> |
| 22 | #include <linux/clk.h> | 22 | #include <linux/clk.h> |
| 23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
| 24 | 24 | #include <linux/clkdev.h> | |
| 25 | #include <asm/clkdev.h> | ||
| 26 | 25 | ||
| 27 | #include <mach/clock.h> | 26 | #include <mach/clock.h> |
| 28 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
| @@ -296,7 +295,7 @@ static struct clk_lookup lookups[] = { | |||
| 296 | _REGISTER_CLOCK("fec.0", NULL, fec_clk) | 295 | _REGISTER_CLOCK("fec.0", NULL, fec_clk) |
| 297 | _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk) | 296 | _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk) |
| 298 | _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) | 297 | _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) |
| 299 | _REGISTER_CLOCK("imx-wdt.0", NULL, wdt_clk) | 298 | _REGISTER_CLOCK("imx2-wdt.0", NULL, wdt_clk) |
| 300 | _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) | 299 | _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) |
| 301 | _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) | 300 | _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) |
| 302 | _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk) | 301 | _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk) |
diff --git a/arch/arm/mach-imx/clock-imx27.c b/arch/arm/mach-imx/clock-imx27.c index 98a25bada783..583f2515c1d5 100644 --- a/arch/arm/mach-imx/clock-imx27.c +++ b/arch/arm/mach-imx/clock-imx27.c | |||
| @@ -21,8 +21,8 @@ | |||
| 21 | #include <linux/clk.h> | 21 | #include <linux/clk.h> |
| 22 | #include <linux/io.h> | 22 | #include <linux/io.h> |
| 23 | #include <linux/module.h> | 23 | #include <linux/module.h> |
| 24 | #include <linux/clkdev.h> | ||
| 24 | 25 | ||
| 25 | #include <asm/clkdev.h> | ||
| 26 | #include <asm/div64.h> | 26 | #include <asm/div64.h> |
| 27 | 27 | ||
| 28 | #include <mach/clock.h> | 28 | #include <mach/clock.h> |
| @@ -125,7 +125,7 @@ static int clk_cpu_set_parent(struct clk *clk, struct clk *parent) | |||
| 125 | if (clk->parent == parent) | 125 | if (clk->parent == parent) |
| 126 | return 0; | 126 | return 0; |
| 127 | 127 | ||
| 128 | if (mx27_revision() >= CHIP_REV_2_0) { | 128 | if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { |
| 129 | if (parent == &mpll_main1_clk) { | 129 | if (parent == &mpll_main1_clk) { |
| 130 | cscr |= CCM_CSCR_ARM_SRC; | 130 | cscr |= CCM_CSCR_ARM_SRC; |
| 131 | } else { | 131 | } else { |
| @@ -174,7 +174,7 @@ static int set_rate_cpu(struct clk *clk, unsigned long rate) | |||
| 174 | div--; | 174 | div--; |
| 175 | 175 | ||
| 176 | reg = __raw_readl(CCM_CSCR); | 176 | reg = __raw_readl(CCM_CSCR); |
| 177 | if (mx27_revision() >= CHIP_REV_2_0) { | 177 | if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { |
| 178 | reg &= ~(3 << 12); | 178 | reg &= ~(3 << 12); |
| 179 | reg |= div << 12; | 179 | reg |= div << 12; |
| 180 | reg &= ~(CCM_CSCR_FPM | CCM_CSCR_SPEN); | 180 | reg &= ~(CCM_CSCR_FPM | CCM_CSCR_SPEN); |
| @@ -244,7 +244,7 @@ static unsigned long get_rate_ssix(struct clk *clk, unsigned long pdf) | |||
| 244 | 244 | ||
| 245 | parent_rate = clk_get_rate(clk->parent); | 245 | parent_rate = clk_get_rate(clk->parent); |
| 246 | 246 | ||
| 247 | if (mx27_revision() >= CHIP_REV_2_0) | 247 | if (mx27_revision() >= IMX_CHIP_REVISION_2_0) |
| 248 | pdf += 4; /* MX27 TO2+ */ | 248 | pdf += 4; /* MX27 TO2+ */ |
| 249 | else | 249 | else |
| 250 | pdf = (pdf < 2) ? 124UL : pdf; /* MX21 & MX27 TO1 */ | 250 | pdf = (pdf < 2) ? 124UL : pdf; /* MX21 & MX27 TO1 */ |
| @@ -269,7 +269,7 @@ static unsigned long get_rate_nfc(struct clk *clk) | |||
| 269 | 269 | ||
| 270 | parent_rate = clk_get_rate(clk->parent); | 270 | parent_rate = clk_get_rate(clk->parent); |
| 271 | 271 | ||
| 272 | if (mx27_revision() >= CHIP_REV_2_0) | 272 | if (mx27_revision() >= IMX_CHIP_REVISION_2_0) |
| 273 | nfc_pdf = (__raw_readl(CCM_PCDR0) >> 6) & 0xf; | 273 | nfc_pdf = (__raw_readl(CCM_PCDR0) >> 6) & 0xf; |
| 274 | else | 274 | else |
| 275 | nfc_pdf = (__raw_readl(CCM_PCDR0) >> 12) & 0xf; | 275 | nfc_pdf = (__raw_readl(CCM_PCDR0) >> 12) & 0xf; |
| @@ -284,7 +284,7 @@ static unsigned long get_rate_vpu(struct clk *clk) | |||
| 284 | 284 | ||
| 285 | parent_rate = clk_get_rate(clk->parent); | 285 | parent_rate = clk_get_rate(clk->parent); |
| 286 | 286 | ||
| 287 | if (mx27_revision() >= CHIP_REV_2_0) { | 287 | if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { |
| 288 | vpu_pdf = (__raw_readl(CCM_PCDR0) >> 10) & 0x3f; | 288 | vpu_pdf = (__raw_readl(CCM_PCDR0) >> 10) & 0x3f; |
| 289 | vpu_pdf += 4; | 289 | vpu_pdf += 4; |
| 290 | } else { | 290 | } else { |
| @@ -347,7 +347,7 @@ static unsigned long get_rate_mpll_main(struct clk *clk) | |||
| 347 | * clk->id == 0: arm clock source path 1 which is from 2 * MPLL / 2 | 347 | * clk->id == 0: arm clock source path 1 which is from 2 * MPLL / 2 |
| 348 | * clk->id == 1: arm clock source path 2 which is from 2 * MPLL / 3 | 348 | * clk->id == 1: arm clock source path 2 which is from 2 * MPLL / 3 |
| 349 | */ | 349 | */ |
| 350 | if (mx27_revision() >= CHIP_REV_2_0 && clk->id == 1) | 350 | if (mx27_revision() >= IMX_CHIP_REVISION_2_0 && clk->id == 1) |
| 351 | return 2UL * parent_rate / 3UL; | 351 | return 2UL * parent_rate / 3UL; |
| 352 | 352 | ||
| 353 | return parent_rate; | 353 | return parent_rate; |
| @@ -365,7 +365,7 @@ static unsigned long get_rate_spll(struct clk *clk) | |||
| 365 | /* On TO2 we have to write the value back. Otherwise we | 365 | /* On TO2 we have to write the value back. Otherwise we |
| 366 | * read 0 from this register the next time. | 366 | * read 0 from this register the next time. |
| 367 | */ | 367 | */ |
| 368 | if (mx27_revision() >= CHIP_REV_2_0) | 368 | if (mx27_revision() >= IMX_CHIP_REVISION_2_0) |
| 369 | __raw_writel(reg, CCM_SPCTL0); | 369 | __raw_writel(reg, CCM_SPCTL0); |
| 370 | 370 | ||
| 371 | return mxc_decode_pll(reg, rate); | 371 | return mxc_decode_pll(reg, rate); |
| @@ -376,7 +376,7 @@ static unsigned long get_rate_cpu(struct clk *clk) | |||
| 376 | u32 div; | 376 | u32 div; |
| 377 | unsigned long rate; | 377 | unsigned long rate; |
| 378 | 378 | ||
| 379 | if (mx27_revision() >= CHIP_REV_2_0) | 379 | if (mx27_revision() >= IMX_CHIP_REVISION_2_0) |
| 380 | div = (__raw_readl(CCM_CSCR) >> 12) & 0x3; | 380 | div = (__raw_readl(CCM_CSCR) >> 12) & 0x3; |
| 381 | else | 381 | else |
| 382 | div = (__raw_readl(CCM_CSCR) >> 13) & 0x7; | 382 | div = (__raw_readl(CCM_CSCR) >> 13) & 0x7; |
| @@ -389,7 +389,7 @@ static unsigned long get_rate_ahb(struct clk *clk) | |||
| 389 | { | 389 | { |
| 390 | unsigned long rate, bclk_pdf; | 390 | unsigned long rate, bclk_pdf; |
| 391 | 391 | ||
| 392 | if (mx27_revision() >= CHIP_REV_2_0) | 392 | if (mx27_revision() >= IMX_CHIP_REVISION_2_0) |
| 393 | bclk_pdf = (__raw_readl(CCM_CSCR) >> 8) & 0x3; | 393 | bclk_pdf = (__raw_readl(CCM_CSCR) >> 8) & 0x3; |
| 394 | else | 394 | else |
| 395 | bclk_pdf = (__raw_readl(CCM_CSCR) >> 9) & 0xf; | 395 | bclk_pdf = (__raw_readl(CCM_CSCR) >> 9) & 0xf; |
| @@ -402,7 +402,7 @@ static unsigned long get_rate_ipg(struct clk *clk) | |||
| 402 | { | 402 | { |
| 403 | unsigned long rate, ipg_pdf; | 403 | unsigned long rate, ipg_pdf; |
| 404 | 404 | ||
| 405 | if (mx27_revision() >= CHIP_REV_2_0) | 405 | if (mx27_revision() >= IMX_CHIP_REVISION_2_0) |
| 406 | return clk_get_rate(clk->parent); | 406 | return clk_get_rate(clk->parent); |
| 407 | else | 407 | else |
| 408 | ipg_pdf = (__raw_readl(CCM_CSCR) >> 8) & 1; | 408 | ipg_pdf = (__raw_readl(CCM_CSCR) >> 8) & 1; |
| @@ -667,7 +667,7 @@ static struct clk_lookup lookups[] = { | |||
| 667 | _REGISTER_CLOCK(NULL, "sahara2", sahara2_clk) | 667 | _REGISTER_CLOCK(NULL, "sahara2", sahara2_clk) |
| 668 | _REGISTER_CLOCK(NULL, "ata", ata_clk) | 668 | _REGISTER_CLOCK(NULL, "ata", ata_clk) |
| 669 | _REGISTER_CLOCK(NULL, "mstick", mstick_clk) | 669 | _REGISTER_CLOCK(NULL, "mstick", mstick_clk) |
| 670 | _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk) | 670 | _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk) |
| 671 | _REGISTER_CLOCK(NULL, "gpio", gpio_clk) | 671 | _REGISTER_CLOCK(NULL, "gpio", gpio_clk) |
| 672 | _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk) | 672 | _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk) |
| 673 | _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) | 673 | _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) |
| @@ -683,7 +683,7 @@ static void __init to2_adjust_clocks(void) | |||
| 683 | { | 683 | { |
| 684 | unsigned long cscr = __raw_readl(CCM_CSCR); | 684 | unsigned long cscr = __raw_readl(CCM_CSCR); |
| 685 | 685 | ||
| 686 | if (mx27_revision() >= CHIP_REV_2_0) { | 686 | if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { |
| 687 | if (cscr & CCM_CSCR_ARM_SRC) | 687 | if (cscr & CCM_CSCR_ARM_SRC) |
| 688 | cpu_clk.parent = &mpll_main1_clk; | 688 | cpu_clk.parent = &mpll_main1_clk; |
| 689 | 689 | ||
diff --git a/arch/arm/mach-imx/cpu-imx27.c b/arch/arm/mach-imx/cpu-imx27.c index d8d3b2d84dc5..3b117be37bd2 100644 --- a/arch/arm/mach-imx/cpu-imx27.c +++ b/arch/arm/mach-imx/cpu-imx27.c | |||
| @@ -42,7 +42,19 @@ static void query_silicon_parameter(void) | |||
| 42 | val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR | 42 | val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR |
| 43 | + SYS_CHIP_ID)); | 43 | + SYS_CHIP_ID)); |
| 44 | 44 | ||
| 45 | cpu_silicon_rev = (int)(val >> 28); | 45 | switch (val >> 28) { |
| 46 | case 0: | ||
| 47 | cpu_silicon_rev = IMX_CHIP_REVISION_1_0; | ||
| 48 | break; | ||
| 49 | case 1: | ||
| 50 | cpu_silicon_rev = IMX_CHIP_REVISION_2_0; | ||
| 51 | break; | ||
| 52 | case 2: | ||
| 53 | cpu_silicon_rev = IMX_CHIP_REVISION_2_1; | ||
| 54 | break; | ||
| 55 | default: | ||
| 56 | cpu_silicon_rev = IMX_CHIP_REVISION_UNKNOWN; | ||
| 57 | } | ||
| 46 | cpu_partnumber = (int)((val >> 12) & 0xFFFF); | 58 | cpu_partnumber = (int)((val >> 12) & 0xFFFF); |
| 47 | } | 59 | } |
| 48 | 60 | ||
diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h index d189039749b0..16744d2d9b81 100644 --- a/arch/arm/mach-imx/devices-imx21.h +++ b/arch/arm/mach-imx/devices-imx21.h | |||
| @@ -9,10 +9,26 @@ | |||
| 9 | #include <mach/mx21.h> | 9 | #include <mach/mx21.h> |
| 10 | #include <mach/devices-common.h> | 10 | #include <mach/devices-common.h> |
| 11 | 11 | ||
| 12 | extern const struct imx_imx21_hcd_data imx21_imx21_hcd_data __initconst; | ||
| 13 | #define imx21_add_imx21_hcd(pdata) \ | ||
| 14 | imx_add_imx21_hcd(&imx21_imx21_hcd_data, pdata) | ||
| 15 | |||
| 16 | extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst; | ||
| 17 | #define imx21_add_imx2_wdt(pdata) \ | ||
| 18 | imx_add_imx2_wdt(&imx21_imx2_wdt_data) | ||
| 19 | |||
| 20 | extern const struct imx_imx_fb_data imx21_imx_fb_data __initconst; | ||
| 21 | #define imx21_add_imx_fb(pdata) \ | ||
| 22 | imx_add_imx_fb(&imx21_imx_fb_data, pdata) | ||
| 23 | |||
| 12 | extern const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst; | 24 | extern const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst; |
| 13 | #define imx21_add_imx_i2c(pdata) \ | 25 | #define imx21_add_imx_i2c(pdata) \ |
| 14 | imx_add_imx_i2c(&imx21_imx_i2c_data, pdata) | 26 | imx_add_imx_i2c(&imx21_imx_i2c_data, pdata) |
| 15 | 27 | ||
| 28 | extern const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst; | ||
| 29 | #define imx21_add_imx_keypad(pdata) \ | ||
| 30 | imx_add_imx_keypad(&imx21_imx_keypad_data, pdata) | ||
| 31 | |||
| 16 | extern const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst; | 32 | extern const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst; |
| 17 | #define imx21_add_imx_ssi(id, pdata) \ | 33 | #define imx21_add_imx_ssi(id, pdata) \ |
| 18 | imx_add_imx_ssi(&imx21_imx_ssi_data[id], pdata) | 34 | imx_add_imx_ssi(&imx21_imx_ssi_data[id], pdata) |
| @@ -25,10 +41,18 @@ extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst; | |||
| 25 | #define imx21_add_imx_uart2(pdata) imx21_add_imx_uart(2, pdata) | 41 | #define imx21_add_imx_uart2(pdata) imx21_add_imx_uart(2, pdata) |
| 26 | #define imx21_add_imx_uart3(pdata) imx21_add_imx_uart(3, pdata) | 42 | #define imx21_add_imx_uart3(pdata) imx21_add_imx_uart(3, pdata) |
| 27 | 43 | ||
| 44 | extern const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst; | ||
| 45 | #define imx21_add_mxc_mmc(id, pdata) \ | ||
| 46 | imx_add_mxc_mmc(&imx21_mxc_mmc_data[id], pdata) | ||
| 47 | |||
| 28 | extern const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst; | 48 | extern const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst; |
| 29 | #define imx21_add_mxc_nand(pdata) \ | 49 | #define imx21_add_mxc_nand(pdata) \ |
| 30 | imx_add_mxc_nand(&imx21_mxc_nand_data, pdata) | 50 | imx_add_mxc_nand(&imx21_mxc_nand_data, pdata) |
| 31 | 51 | ||
| 52 | extern const struct imx_mxc_w1_data imx21_mxc_w1_data __initconst; | ||
| 53 | #define imx21_add_mxc_w1(pdata) \ | ||
| 54 | imx_add_mxc_w1(&imx21_mxc_w1_data) | ||
| 55 | |||
| 32 | extern const struct imx_spi_imx_data imx21_cspi_data[] __initconst; | 56 | extern const struct imx_spi_imx_data imx21_cspi_data[] __initconst; |
| 33 | #define imx21_add_cspi(id, pdata) \ | 57 | #define imx21_add_cspi(id, pdata) \ |
| 34 | imx_add_spi_imx(&imx21_cspi_data[id], pdata) | 58 | imx_add_spi_imx(&imx21_cspi_data[id], pdata) |
diff --git a/arch/arm/mach-mx25/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h index d94d282fa676..bde33caf1b90 100644 --- a/arch/arm/mach-mx25/devices-imx25.h +++ b/arch/arm/mach-imx/devices-imx25.h | |||
| @@ -13,10 +13,27 @@ extern const struct imx_fec_data imx25_fec_data __initconst; | |||
| 13 | #define imx25_add_fec(pdata) \ | 13 | #define imx25_add_fec(pdata) \ |
| 14 | imx_add_fec(&imx25_fec_data, pdata) | 14 | imx_add_fec(&imx25_fec_data, pdata) |
| 15 | 15 | ||
| 16 | #define imx25_add_flexcan0(pdata) \ | 16 | extern const struct imx_flexcan_data imx25_flexcan_data[] __initconst; |
| 17 | imx_add_flexcan(0, MX25_CAN1_BASE_ADDR, SZ_16K, MX25_INT_CAN1, pdata) | 17 | #define imx25_add_flexcan(id, pdata) \ |
| 18 | #define imx25_add_flexcan1(pdata) \ | 18 | imx_add_flexcan(&imx25_flexcan_data[id], pdata) |
| 19 | imx_add_flexcan(1, MX25_CAN2_BASE_ADDR, SZ_16K, MX25_INT_CAN2, pdata) | 19 | #define imx25_add_flexcan0(pdata) imx25_add_flexcan(0, pdata) |
| 20 | #define imx25_add_flexcan1(pdata) imx25_add_flexcan(1, pdata) | ||
| 21 | |||
| 22 | extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst; | ||
| 23 | #define imx25_add_fsl_usb2_udc(pdata) \ | ||
| 24 | imx_add_fsl_usb2_udc(&imx25_fsl_usb2_udc_data, pdata) | ||
| 25 | |||
| 26 | extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst; | ||
| 27 | #define imx25_add_imxdi_rtc(pdata) \ | ||
| 28 | imx_add_imxdi_rtc(&imx25_imxdi_rtc_data) | ||
| 29 | |||
| 30 | extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst; | ||
| 31 | #define imx25_add_imx2_wdt(pdata) \ | ||
| 32 | imx_add_imx2_wdt(&imx25_imx2_wdt_data) | ||
| 33 | |||
| 34 | extern const struct imx_imx_fb_data imx25_imx_fb_data __initconst; | ||
| 35 | #define imx25_add_imx_fb(pdata) \ | ||
| 36 | imx_add_imx_fb(&imx25_imx_fb_data, pdata) | ||
| 20 | 37 | ||
| 21 | extern const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst; | 38 | extern const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst; |
| 22 | #define imx25_add_imx_i2c(id, pdata) \ | 39 | #define imx25_add_imx_i2c(id, pdata) \ |
| @@ -25,6 +42,10 @@ extern const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst; | |||
| 25 | #define imx25_add_imx_i2c1(pdata) imx25_add_imx_i2c(1, pdata) | 42 | #define imx25_add_imx_i2c1(pdata) imx25_add_imx_i2c(1, pdata) |
| 26 | #define imx25_add_imx_i2c2(pdata) imx25_add_imx_i2c(2, pdata) | 43 | #define imx25_add_imx_i2c2(pdata) imx25_add_imx_i2c(2, pdata) |
| 27 | 44 | ||
| 45 | extern const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst; | ||
| 46 | #define imx25_add_imx_keypad(pdata) \ | ||
| 47 | imx_add_imx_keypad(&imx25_imx_keypad_data, pdata) | ||
| 48 | |||
| 28 | extern const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst; | 49 | extern const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst; |
| 29 | #define imx25_add_imx_ssi(id, pdata) \ | 50 | #define imx25_add_imx_ssi(id, pdata) \ |
| 30 | imx_add_imx_ssi(&imx25_imx_ssi_data[id], pdata) | 51 | imx_add_imx_ssi(&imx25_imx_ssi_data[id], pdata) |
| @@ -38,17 +59,29 @@ extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst; | |||
| 38 | #define imx25_add_imx_uart3(pdata) imx25_add_imx_uart(3, pdata) | 59 | #define imx25_add_imx_uart3(pdata) imx25_add_imx_uart(3, pdata) |
| 39 | #define imx25_add_imx_uart4(pdata) imx25_add_imx_uart(4, pdata) | 60 | #define imx25_add_imx_uart4(pdata) imx25_add_imx_uart(4, pdata) |
| 40 | 61 | ||
| 62 | extern const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst; | ||
| 63 | #define imx25_add_mx2_camera(pdata) \ | ||
| 64 | imx_add_mx2_camera(&imx25_mx2_camera_data, pdata) | ||
| 65 | |||
| 66 | extern const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst; | ||
| 67 | #define imx25_add_mxc_ehci_otg(pdata) \ | ||
| 68 | imx_add_mxc_ehci(&imx25_mxc_ehci_otg_data, pdata) | ||
| 69 | extern const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst; | ||
| 70 | #define imx25_add_mxc_ehci_hs(pdata) \ | ||
| 71 | imx_add_mxc_ehci(&imx25_mxc_ehci_hs_data, pdata) | ||
| 72 | |||
| 41 | extern const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst; | 73 | extern const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst; |
| 42 | #define imx25_add_mxc_nand(pdata) \ | 74 | #define imx25_add_mxc_nand(pdata) \ |
| 43 | imx_add_mxc_nand(&imx25_mxc_nand_data, pdata) | 75 | imx_add_mxc_nand(&imx25_mxc_nand_data, pdata) |
| 44 | 76 | ||
| 77 | extern const struct imx_sdhci_esdhc_imx_data | ||
| 78 | imx25_sdhci_esdhc_imx_data[] __initconst; | ||
| 79 | #define imx25_add_sdhci_esdhc_imx(id, pdata) \ | ||
| 80 | imx_add_sdhci_esdhc_imx(&imx25_sdhci_esdhc_imx_data[id], pdata) | ||
| 81 | |||
| 45 | extern const struct imx_spi_imx_data imx25_cspi_data[] __initconst; | 82 | extern const struct imx_spi_imx_data imx25_cspi_data[] __initconst; |
| 46 | #define imx25_add_spi_imx(id, pdata) \ | 83 | #define imx25_add_spi_imx(id, pdata) \ |
| 47 | imx_add_spi_imx(&imx25_cspi_data[id], pdata) | 84 | imx_add_spi_imx(&imx25_spi_imx_data[id], pdata) |
| 48 | #define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata) | 85 | #define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata) |
| 49 | #define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata) | 86 | #define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata) |
| 50 | #define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata) | 87 | #define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata) |
| 51 | |||
| 52 | extern const struct imx_esdhc_imx_data imx25_esdhc_data[] __initconst; | ||
| 53 | #define imx25_add_esdhc(id, pdata) \ | ||
| 54 | imx_add_esdhc(&imx25_esdhc_data[id], pdata) | ||
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h index 7011690364f2..f1272d4b5a33 100644 --- a/arch/arm/mach-imx/devices-imx27.h +++ b/arch/arm/mach-imx/devices-imx27.h | |||
| @@ -13,10 +13,26 @@ extern const struct imx_fec_data imx27_fec_data __initconst; | |||
| 13 | #define imx27_add_fec(pdata) \ | 13 | #define imx27_add_fec(pdata) \ |
| 14 | imx_add_fec(&imx27_fec_data, pdata) | 14 | imx_add_fec(&imx27_fec_data, pdata) |
| 15 | 15 | ||
| 16 | extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst; | ||
| 17 | #define imx27_add_fsl_usb2_udc(pdata) \ | ||
| 18 | imx_add_fsl_usb2_udc(&imx27_fsl_usb2_udc_data, pdata) | ||
| 19 | |||
| 20 | extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst; | ||
| 21 | #define imx27_add_imx2_wdt(pdata) \ | ||
| 22 | imx_add_imx2_wdt(&imx27_imx2_wdt_data) | ||
| 23 | |||
| 24 | extern const struct imx_imx_fb_data imx27_imx_fb_data __initconst; | ||
| 25 | #define imx27_add_imx_fb(pdata) \ | ||
| 26 | imx_add_imx_fb(&imx27_imx_fb_data, pdata) | ||
| 27 | |||
| 16 | extern const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst; | 28 | extern const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst; |
| 17 | #define imx27_add_imx_i2c(id, pdata) \ | 29 | #define imx27_add_imx_i2c(id, pdata) \ |
| 18 | imx_add_imx_i2c(&imx27_imx_i2c_data[id], pdata) | 30 | imx_add_imx_i2c(&imx27_imx_i2c_data[id], pdata) |
| 19 | 31 | ||
| 32 | extern const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst; | ||
| 33 | #define imx27_add_imx_keypad(pdata) \ | ||
| 34 | imx_add_imx_keypad(&imx27_imx_keypad_data, pdata) | ||
| 35 | |||
| 20 | extern const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst; | 36 | extern const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst; |
| 21 | #define imx27_add_imx_ssi(id, pdata) \ | 37 | #define imx27_add_imx_ssi(id, pdata) \ |
| 22 | imx_add_imx_ssi(&imx27_imx_ssi_data[id], pdata) | 38 | imx_add_imx_ssi(&imx27_imx_ssi_data[id], pdata) |
| @@ -31,10 +47,29 @@ extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst; | |||
| 31 | #define imx27_add_imx_uart4(pdata) imx27_add_imx_uart(4, pdata) | 47 | #define imx27_add_imx_uart4(pdata) imx27_add_imx_uart(4, pdata) |
| 32 | #define imx27_add_imx_uart5(pdata) imx27_add_imx_uart(5, pdata) | 48 | #define imx27_add_imx_uart5(pdata) imx27_add_imx_uart(5, pdata) |
| 33 | 49 | ||
| 50 | extern const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst; | ||
| 51 | #define imx27_add_mx2_camera(pdata) \ | ||
| 52 | imx_add_mx2_camera(&imx27_mx2_camera_data, pdata) | ||
| 53 | |||
| 54 | extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst; | ||
| 55 | #define imx27_add_mxc_ehci_otg(pdata) \ | ||
| 56 | imx_add_mxc_ehci(&imx27_mxc_ehci_otg_data, pdata) | ||
| 57 | extern const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[] __initconst; | ||
| 58 | #define imx27_add_mxc_ehci_hs(id, pdata) \ | ||
| 59 | imx_add_mxc_ehci(&imx27_mxc_ehci_hs_data[id - 1], pdata) | ||
| 60 | |||
| 61 | extern const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst; | ||
| 62 | #define imx27_add_mxc_mmc(id, pdata) \ | ||
| 63 | imx_add_mxc_mmc(&imx27_mxc_mmc_data[id], pdata) | ||
| 64 | |||
| 34 | extern const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst; | 65 | extern const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst; |
| 35 | #define imx27_add_mxc_nand(pdata) \ | 66 | #define imx27_add_mxc_nand(pdata) \ |
| 36 | imx_add_mxc_nand(&imx27_mxc_nand_data, pdata) | 67 | imx_add_mxc_nand(&imx27_mxc_nand_data, pdata) |
| 37 | 68 | ||
| 69 | extern const struct imx_mxc_w1_data imx27_mxc_w1_data __initconst; | ||
| 70 | #define imx27_add_mxc_w1(pdata) \ | ||
| 71 | imx_add_mxc_w1(&imx27_mxc_w1_data) | ||
| 72 | |||
| 38 | extern const struct imx_spi_imx_data imx27_cspi_data[] __initconst; | 73 | extern const struct imx_spi_imx_data imx27_cspi_data[] __initconst; |
| 39 | #define imx27_add_cspi(id, pdata) \ | 74 | #define imx27_add_cspi(id, pdata) \ |
| 40 | imx_add_spi_imx(&imx27_cspi_data[id], pdata) | 75 | imx_add_spi_imx(&imx27_cspi_data[id], pdata) |
diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c deleted file mode 100644 index fba5047de8b1..000000000000 --- a/arch/arm/mach-imx/devices.c +++ /dev/null | |||
| @@ -1,553 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Author: MontaVista Software, Inc. | ||
| 3 | * <source@mvista.com> | ||
| 4 | * | ||
| 5 | * Based on the OMAP devices.c | ||
| 6 | * | ||
| 7 | * 2005 (c) MontaVista Software, Inc. This file is licensed under the | ||
| 8 | * terms of the GNU General Public License version 2. This program is | ||
| 9 | * licensed "as is" without any warranty of any kind, whether express | ||
| 10 | * or implied. | ||
| 11 | * | ||
| 12 | * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 13 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | ||
| 14 | * Copyright 2008 Sascha Hauer, kernel@pengutronix.de | ||
| 15 | * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | ||
| 16 | * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt> | ||
| 17 | * | ||
| 18 | * This program is free software; you can redistribute it and/or | ||
| 19 | * modify it under the terms of the GNU General Public License | ||
| 20 | * as published by the Free Software Foundation; either version 2 | ||
| 21 | * of the License, or (at your option) any later version. | ||
| 22 | * This program is distributed in the hope that it will be useful, | ||
| 23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 25 | * GNU General Public License for more details. | ||
| 26 | * | ||
| 27 | * You should have received a copy of the GNU General Public License | ||
| 28 | * along with this program; if not, write to the Free Software | ||
| 29 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 30 | * MA 02110-1301, USA. | ||
| 31 | */ | ||
| 32 | #include <linux/module.h> | ||
| 33 | #include <linux/kernel.h> | ||
| 34 | #include <linux/init.h> | ||
| 35 | #include <linux/platform_device.h> | ||
| 36 | #include <linux/gpio.h> | ||
| 37 | #include <linux/dma-mapping.h> | ||
| 38 | #include <linux/serial.h> | ||
| 39 | |||
| 40 | #include <mach/irqs.h> | ||
| 41 | #include <mach/hardware.h> | ||
| 42 | #include <mach/common.h> | ||
| 43 | #include <mach/mmc.h> | ||
| 44 | |||
| 45 | #include "devices.h" | ||
| 46 | |||
| 47 | #if defined(CONFIG_ARCH_MX1) | ||
| 48 | static struct resource imx1_camera_resources[] = { | ||
| 49 | { | ||
| 50 | .start = 0x00224000, | ||
| 51 | .end = 0x00224010, | ||
| 52 | .flags = IORESOURCE_MEM, | ||
| 53 | }, { | ||
| 54 | .start = MX1_CSI_INT, | ||
| 55 | .end = MX1_CSI_INT, | ||
| 56 | .flags = IORESOURCE_IRQ, | ||
| 57 | }, | ||
| 58 | }; | ||
| 59 | |||
| 60 | static u64 imx1_camera_dmamask = DMA_BIT_MASK(32); | ||
| 61 | |||
| 62 | struct platform_device imx1_camera_device = { | ||
| 63 | .name = "mx1-camera", | ||
| 64 | .id = 0, /* This is used to put cameras on this interface */ | ||
| 65 | .dev = { | ||
| 66 | .dma_mask = &imx1_camera_dmamask, | ||
| 67 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 68 | }, | ||
| 69 | .resource = imx1_camera_resources, | ||
| 70 | .num_resources = ARRAY_SIZE(imx1_camera_resources), | ||
| 71 | }; | ||
| 72 | |||
| 73 | static struct resource imx_rtc_resources[] = { | ||
| 74 | { | ||
| 75 | .start = 0x00204000, | ||
| 76 | .end = 0x00204024, | ||
| 77 | .flags = IORESOURCE_MEM, | ||
| 78 | }, { | ||
| 79 | .start = MX1_RTC_INT, | ||
| 80 | .end = MX1_RTC_INT, | ||
| 81 | .flags = IORESOURCE_IRQ, | ||
| 82 | }, { | ||
| 83 | .start = MX1_RTC_SAMINT, | ||
| 84 | .end = MX1_RTC_SAMINT, | ||
| 85 | .flags = IORESOURCE_IRQ, | ||
| 86 | }, | ||
| 87 | }; | ||
| 88 | |||
| 89 | struct platform_device imx_rtc_device = { | ||
| 90 | .name = "rtc-imx", | ||
| 91 | .id = 0, | ||
| 92 | .resource = imx_rtc_resources, | ||
| 93 | .num_resources = ARRAY_SIZE(imx_rtc_resources), | ||
| 94 | }; | ||
| 95 | |||
| 96 | static struct resource imx_wdt_resources[] = { | ||
| 97 | { | ||
| 98 | .start = 0x00201000, | ||
| 99 | .end = 0x00201008, | ||
| 100 | .flags = IORESOURCE_MEM, | ||
| 101 | }, { | ||
| 102 | .start = MX1_WDT_INT, | ||
| 103 | .end = MX1_WDT_INT, | ||
| 104 | .flags = IORESOURCE_IRQ, | ||
| 105 | }, | ||
| 106 | }; | ||
| 107 | |||
| 108 | struct platform_device imx_wdt_device = { | ||
| 109 | .name = "imx-wdt", | ||
| 110 | .id = 0, | ||
| 111 | .resource = imx_wdt_resources, | ||
| 112 | .num_resources = ARRAY_SIZE(imx_wdt_resources), | ||
| 113 | }; | ||
| 114 | |||
| 115 | static struct resource imx_usb_resources[] = { | ||
| 116 | { | ||
| 117 | .start = 0x00212000, | ||
| 118 | .end = 0x00212148, | ||
| 119 | .flags = IORESOURCE_MEM, | ||
| 120 | }, { | ||
| 121 | .start = MX1_USBD_INT0, | ||
| 122 | .end = MX1_USBD_INT0, | ||
| 123 | .flags = IORESOURCE_IRQ, | ||
| 124 | }, { | ||
| 125 | .start = MX1_USBD_INT1, | ||
| 126 | .end = MX1_USBD_INT1, | ||
| 127 | .flags = IORESOURCE_IRQ, | ||
| 128 | }, { | ||
| 129 | .start = MX1_USBD_INT2, | ||
| 130 | .end = MX1_USBD_INT2, | ||
| 131 | .flags = IORESOURCE_IRQ, | ||
| 132 | }, { | ||
| 133 | .start = MX1_USBD_INT3, | ||
| 134 | .end = MX1_USBD_INT3, | ||
| 135 | .flags = IORESOURCE_IRQ, | ||
| 136 | }, { | ||
| 137 | .start = MX1_USBD_INT4, | ||
| 138 | .end = MX1_USBD_INT4, | ||
| 139 | .flags = IORESOURCE_IRQ, | ||
| 140 | }, { | ||
| 141 | .start = MX1_USBD_INT5, | ||
| 142 | .end = MX1_USBD_INT5, | ||
| 143 | .flags = IORESOURCE_IRQ, | ||
| 144 | }, { | ||
| 145 | .start = MX1_USBD_INT6, | ||
| 146 | .end = MX1_USBD_INT6, | ||
| 147 | .flags = IORESOURCE_IRQ, | ||
| 148 | }, | ||
| 149 | }; | ||
| 150 | |||
| 151 | struct platform_device imx_usb_device = { | ||
| 152 | .name = "imx_udc", | ||
| 153 | .id = 0, | ||
| 154 | .num_resources = ARRAY_SIZE(imx_usb_resources), | ||
| 155 | .resource = imx_usb_resources, | ||
| 156 | }; | ||
| 157 | |||
| 158 | /* GPIO port description */ | ||
| 159 | static struct mxc_gpio_port imx_gpio_ports[] = { | ||
| 160 | { | ||
| 161 | .chip.label = "gpio-0", | ||
| 162 | .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR), | ||
| 163 | .irq = MX1_GPIO_INT_PORTA, | ||
| 164 | .virtual_irq_start = MXC_GPIO_IRQ_START, | ||
| 165 | }, { | ||
| 166 | .chip.label = "gpio-1", | ||
| 167 | .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100), | ||
| 168 | .irq = MX1_GPIO_INT_PORTB, | ||
| 169 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32, | ||
| 170 | }, { | ||
| 171 | .chip.label = "gpio-2", | ||
| 172 | .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200), | ||
| 173 | .irq = MX1_GPIO_INT_PORTC, | ||
| 174 | .virtual_irq_start = MXC_GPIO_IRQ_START + 64, | ||
| 175 | }, { | ||
| 176 | .chip.label = "gpio-3", | ||
| 177 | .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300), | ||
| 178 | .irq = MX1_GPIO_INT_PORTD, | ||
| 179 | .virtual_irq_start = MXC_GPIO_IRQ_START + 96, | ||
| 180 | } | ||
| 181 | }; | ||
| 182 | |||
| 183 | int __init imx1_register_gpios(void) | ||
| 184 | { | ||
| 185 | return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); | ||
| 186 | } | ||
| 187 | #endif | ||
| 188 | |||
| 189 | #if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27) | ||
| 190 | |||
| 191 | #ifdef CONFIG_MACH_MX27 | ||
| 192 | static struct resource mx27_camera_resources[] = { | ||
| 193 | { | ||
| 194 | .start = MX27_CSI_BASE_ADDR, | ||
| 195 | .end = MX27_CSI_BASE_ADDR + 0x1f, | ||
| 196 | .flags = IORESOURCE_MEM, | ||
| 197 | }, { | ||
| 198 | .start = MX27_EMMA_PRP_BASE_ADDR, | ||
| 199 | .end = MX27_EMMA_PRP_BASE_ADDR + 0x1f, | ||
| 200 | .flags = IORESOURCE_MEM, | ||
| 201 | }, { | ||
| 202 | .start = MX27_INT_CSI, | ||
| 203 | .end = MX27_INT_CSI, | ||
| 204 | .flags = IORESOURCE_IRQ, | ||
| 205 | },{ | ||
| 206 | .start = MX27_INT_EMMAPRP, | ||
| 207 | .end = MX27_INT_EMMAPRP, | ||
| 208 | .flags = IORESOURCE_IRQ, | ||
| 209 | }, | ||
| 210 | }; | ||
| 211 | struct platform_device mx27_camera_device = { | ||
| 212 | .name = "mx2-camera", | ||
| 213 | .id = 0, | ||
| 214 | .num_resources = ARRAY_SIZE(mx27_camera_resources), | ||
| 215 | .resource = mx27_camera_resources, | ||
| 216 | .dev = { | ||
| 217 | .coherent_dma_mask = 0xffffffff, | ||
| 218 | }, | ||
| 219 | }; | ||
| 220 | #endif | ||
| 221 | |||
| 222 | /* | ||
| 223 | * General Purpose Timer | ||
| 224 | * - i.MX21: 3 timers | ||
| 225 | * - i.MX27: 6 timers | ||
| 226 | */ | ||
| 227 | #define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \ | ||
| 228 | static struct resource timer ## n ##_resources[] = { \ | ||
| 229 | { \ | ||
| 230 | .start = baseaddr, \ | ||
| 231 | .end = baseaddr + SZ_4K - 1, \ | ||
| 232 | .flags = IORESOURCE_MEM, \ | ||
| 233 | }, { \ | ||
| 234 | .start = irq, \ | ||
| 235 | .end = irq, \ | ||
| 236 | .flags = IORESOURCE_IRQ, \ | ||
| 237 | } \ | ||
| 238 | }; \ | ||
| 239 | \ | ||
| 240 | struct platform_device mxc_gpt ## n = { \ | ||
| 241 | .name = "imx_gpt", \ | ||
| 242 | .id = n, \ | ||
| 243 | .num_resources = ARRAY_SIZE(timer ## n ## _resources), \ | ||
| 244 | .resource = timer ## n ## _resources, \ | ||
| 245 | } | ||
| 246 | |||
| 247 | /* We use gpt1 as system timer, so do not add a device for this one */ | ||
| 248 | DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2); | ||
| 249 | DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3); | ||
| 250 | |||
| 251 | #ifdef CONFIG_MACH_MX27 | ||
| 252 | DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4); | ||
| 253 | DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5); | ||
| 254 | DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6); | ||
| 255 | #endif | ||
| 256 | |||
| 257 | /* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */ | ||
| 258 | static struct resource mxc_wdt_resources[] = { | ||
| 259 | { | ||
| 260 | .start = MX2x_WDOG_BASE_ADDR, | ||
| 261 | .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1, | ||
| 262 | .flags = IORESOURCE_MEM, | ||
| 263 | }, | ||
| 264 | }; | ||
| 265 | |||
| 266 | struct platform_device mxc_wdt = { | ||
| 267 | .name = "imx2-wdt", | ||
| 268 | .id = 0, | ||
| 269 | .num_resources = ARRAY_SIZE(mxc_wdt_resources), | ||
| 270 | .resource = mxc_wdt_resources, | ||
| 271 | }; | ||
| 272 | |||
| 273 | static struct resource mxc_w1_master_resources[] = { | ||
| 274 | { | ||
| 275 | .start = MX2x_OWIRE_BASE_ADDR, | ||
| 276 | .end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1, | ||
| 277 | .flags = IORESOURCE_MEM, | ||
| 278 | }, | ||
| 279 | }; | ||
| 280 | |||
| 281 | struct platform_device mxc_w1_master_device = { | ||
| 282 | .name = "mxc_w1", | ||
| 283 | .id = 0, | ||
| 284 | .num_resources = ARRAY_SIZE(mxc_w1_master_resources), | ||
| 285 | .resource = mxc_w1_master_resources, | ||
| 286 | }; | ||
| 287 | |||
| 288 | /* | ||
| 289 | * lcdc: | ||
| 290 | * - i.MX1: the basic controller | ||
| 291 | * - i.MX21: to be checked | ||
| 292 | * - i.MX27: like i.MX1, with slightly variations | ||
| 293 | */ | ||
| 294 | static struct resource mxc_fb[] = { | ||
| 295 | { | ||
| 296 | .start = MX2x_LCDC_BASE_ADDR, | ||
| 297 | .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1, | ||
| 298 | .flags = IORESOURCE_MEM, | ||
| 299 | }, { | ||
| 300 | .start = MX2x_INT_LCDC, | ||
| 301 | .end = MX2x_INT_LCDC, | ||
| 302 | .flags = IORESOURCE_IRQ, | ||
| 303 | } | ||
| 304 | }; | ||
| 305 | |||
| 306 | /* mxc lcd driver */ | ||
| 307 | struct platform_device mxc_fb_device = { | ||
| 308 | .name = "imx-fb", | ||
| 309 | .id = 0, | ||
| 310 | .num_resources = ARRAY_SIZE(mxc_fb), | ||
| 311 | .resource = mxc_fb, | ||
| 312 | .dev = { | ||
| 313 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 314 | }, | ||
| 315 | }; | ||
| 316 | |||
| 317 | static struct resource mxc_pwm_resources[] = { | ||
| 318 | { | ||
| 319 | .start = MX2x_PWM_BASE_ADDR, | ||
| 320 | .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1, | ||
| 321 | .flags = IORESOURCE_MEM, | ||
| 322 | }, { | ||
| 323 | .start = MX2x_INT_PWM, | ||
| 324 | .end = MX2x_INT_PWM, | ||
| 325 | .flags = IORESOURCE_IRQ, | ||
| 326 | } | ||
| 327 | }; | ||
| 328 | |||
| 329 | struct platform_device mxc_pwm_device = { | ||
| 330 | .name = "mxc_pwm", | ||
| 331 | .id = 0, | ||
| 332 | .num_resources = ARRAY_SIZE(mxc_pwm_resources), | ||
| 333 | .resource = mxc_pwm_resources, | ||
| 334 | }; | ||
| 335 | |||
| 336 | #define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \ | ||
| 337 | static struct resource mxc_sdhc_resources ## n[] = { \ | ||
| 338 | { \ | ||
| 339 | .start = baseaddr, \ | ||
| 340 | .end = baseaddr + SZ_4K - 1, \ | ||
| 341 | .flags = IORESOURCE_MEM, \ | ||
| 342 | }, { \ | ||
| 343 | .start = irq, \ | ||
| 344 | .end = irq, \ | ||
| 345 | .flags = IORESOURCE_IRQ, \ | ||
| 346 | }, { \ | ||
| 347 | .start = dmareq, \ | ||
| 348 | .end = dmareq, \ | ||
| 349 | .flags = IORESOURCE_DMA, \ | ||
| 350 | }, \ | ||
| 351 | }; \ | ||
| 352 | \ | ||
| 353 | static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \ | ||
| 354 | \ | ||
| 355 | struct platform_device mxc_sdhc_device ## n = { \ | ||
| 356 | .name = "mxc-mmc", \ | ||
| 357 | .id = n, \ | ||
| 358 | .dev = { \ | ||
| 359 | .dma_mask = &mxc_sdhc ## n ## _dmamask, \ | ||
| 360 | .coherent_dma_mask = DMA_BIT_MASK(32), \ | ||
| 361 | }, \ | ||
| 362 | .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \ | ||
| 363 | .resource = mxc_sdhc_resources ## n, \ | ||
| 364 | } | ||
| 365 | |||
| 366 | DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1); | ||
| 367 | DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2); | ||
| 368 | |||
| 369 | #ifdef CONFIG_MACH_MX27 | ||
| 370 | static struct resource otg_resources[] = { | ||
| 371 | { | ||
| 372 | .start = MX27_USBOTG_BASE_ADDR, | ||
| 373 | .end = MX27_USBOTG_BASE_ADDR + 0x1ff, | ||
| 374 | .flags = IORESOURCE_MEM, | ||
| 375 | }, { | ||
| 376 | .start = MX27_INT_USB3, | ||
| 377 | .end = MX27_INT_USB3, | ||
| 378 | .flags = IORESOURCE_IRQ, | ||
| 379 | }, | ||
| 380 | }; | ||
| 381 | |||
| 382 | static u64 otg_dmamask = DMA_BIT_MASK(32); | ||
| 383 | |||
| 384 | /* OTG gadget device */ | ||
| 385 | struct platform_device mxc_otg_udc_device = { | ||
| 386 | .name = "fsl-usb2-udc", | ||
| 387 | .id = -1, | ||
| 388 | .dev = { | ||
| 389 | .dma_mask = &otg_dmamask, | ||
| 390 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 391 | }, | ||
| 392 | .resource = otg_resources, | ||
| 393 | .num_resources = ARRAY_SIZE(otg_resources), | ||
| 394 | }; | ||
| 395 | |||
| 396 | /* OTG host */ | ||
| 397 | struct platform_device mxc_otg_host = { | ||
| 398 | .name = "mxc-ehci", | ||
| 399 | .id = 0, | ||
| 400 | .dev = { | ||
| 401 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 402 | .dma_mask = &otg_dmamask, | ||
| 403 | }, | ||
| 404 | .resource = otg_resources, | ||
| 405 | .num_resources = ARRAY_SIZE(otg_resources), | ||
| 406 | }; | ||
| 407 | |||
| 408 | /* USB host 1 */ | ||
| 409 | |||
| 410 | static u64 usbh1_dmamask = DMA_BIT_MASK(32); | ||
| 411 | |||
| 412 | static struct resource mxc_usbh1_resources[] = { | ||
| 413 | { | ||
| 414 | .start = MX27_USBOTG_BASE_ADDR + 0x200, | ||
| 415 | .end = MX27_USBOTG_BASE_ADDR + 0x3ff, | ||
| 416 | .flags = IORESOURCE_MEM, | ||
| 417 | }, { | ||
| 418 | .start = MX27_INT_USB1, | ||
| 419 | .end = MX27_INT_USB1, | ||
| 420 | .flags = IORESOURCE_IRQ, | ||
| 421 | }, | ||
| 422 | }; | ||
| 423 | |||
| 424 | struct platform_device mxc_usbh1 = { | ||
| 425 | .name = "mxc-ehci", | ||
| 426 | .id = 1, | ||
| 427 | .dev = { | ||
| 428 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 429 | .dma_mask = &usbh1_dmamask, | ||
| 430 | }, | ||
| 431 | .resource = mxc_usbh1_resources, | ||
| 432 | .num_resources = ARRAY_SIZE(mxc_usbh1_resources), | ||
| 433 | }; | ||
| 434 | |||
| 435 | /* USB host 2 */ | ||
| 436 | static u64 usbh2_dmamask = DMA_BIT_MASK(32); | ||
| 437 | |||
| 438 | static struct resource mxc_usbh2_resources[] = { | ||
| 439 | { | ||
| 440 | .start = MX27_USBOTG_BASE_ADDR + 0x400, | ||
| 441 | .end = MX27_USBOTG_BASE_ADDR + 0x5ff, | ||
| 442 | .flags = IORESOURCE_MEM, | ||
| 443 | }, { | ||
| 444 | .start = MX27_INT_USB2, | ||
| 445 | .end = MX27_INT_USB2, | ||
| 446 | .flags = IORESOURCE_IRQ, | ||
| 447 | }, | ||
| 448 | }; | ||
| 449 | |||
| 450 | struct platform_device mxc_usbh2 = { | ||
| 451 | .name = "mxc-ehci", | ||
| 452 | .id = 2, | ||
| 453 | .dev = { | ||
| 454 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 455 | .dma_mask = &usbh2_dmamask, | ||
| 456 | }, | ||
| 457 | .resource = mxc_usbh2_resources, | ||
| 458 | .num_resources = ARRAY_SIZE(mxc_usbh2_resources), | ||
| 459 | }; | ||
| 460 | #endif | ||
| 461 | |||
| 462 | /* GPIO port description */ | ||
| 463 | #define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \ | ||
| 464 | { \ | ||
| 465 | .chip.label = "gpio-" #n, \ | ||
| 466 | .irq = _irq, \ | ||
| 467 | .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \ | ||
| 468 | n * 0x100), \ | ||
| 469 | .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \ | ||
| 470 | } | ||
| 471 | |||
| 472 | #define DEFINE_MXC_GPIO_PORT(SOC, n) \ | ||
| 473 | { \ | ||
| 474 | .chip.label = "gpio-" #n, \ | ||
| 475 | .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \ | ||
| 476 | n * 0x100), \ | ||
| 477 | .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \ | ||
| 478 | } | ||
| 479 | |||
| 480 | #define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \ | ||
| 481 | static struct mxc_gpio_port pfx ## _gpio_ports[] = { \ | ||
| 482 | DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \ | ||
| 483 | DEFINE_MXC_GPIO_PORT(SOC, 1), \ | ||
| 484 | DEFINE_MXC_GPIO_PORT(SOC, 2), \ | ||
| 485 | DEFINE_MXC_GPIO_PORT(SOC, 3), \ | ||
| 486 | DEFINE_MXC_GPIO_PORT(SOC, 4), \ | ||
| 487 | DEFINE_MXC_GPIO_PORT(SOC, 5), \ | ||
| 488 | } | ||
| 489 | |||
| 490 | #ifdef CONFIG_MACH_MX21 | ||
| 491 | DEFINE_MXC_GPIO_PORTS(MX21, imx21); | ||
| 492 | |||
| 493 | int __init imx21_register_gpios(void) | ||
| 494 | { | ||
| 495 | return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports)); | ||
| 496 | } | ||
| 497 | #endif | ||
| 498 | |||
| 499 | #ifdef CONFIG_MACH_MX27 | ||
| 500 | DEFINE_MXC_GPIO_PORTS(MX27, imx27); | ||
| 501 | |||
| 502 | int __init imx27_register_gpios(void) | ||
| 503 | { | ||
| 504 | return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports)); | ||
| 505 | } | ||
| 506 | #endif | ||
| 507 | |||
| 508 | #ifdef CONFIG_MACH_MX21 | ||
| 509 | static struct resource mx21_usbhc_resources[] = { | ||
| 510 | { | ||
| 511 | .start = MX21_USBOTG_BASE_ADDR, | ||
| 512 | .end = MX21_USBOTG_BASE_ADDR + SZ_8K - 1, | ||
| 513 | .flags = IORESOURCE_MEM, | ||
| 514 | }, | ||
| 515 | { | ||
| 516 | .start = MX21_INT_USBHOST, | ||
| 517 | .end = MX21_INT_USBHOST, | ||
| 518 | .flags = IORESOURCE_IRQ, | ||
| 519 | }, | ||
| 520 | }; | ||
| 521 | |||
| 522 | struct platform_device mx21_usbhc_device = { | ||
| 523 | .name = "imx21-hcd", | ||
| 524 | .id = 0, | ||
| 525 | .dev = { | ||
| 526 | .dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask, | ||
| 527 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 528 | }, | ||
| 529 | .num_resources = ARRAY_SIZE(mx21_usbhc_resources), | ||
| 530 | .resource = mx21_usbhc_resources, | ||
| 531 | }; | ||
| 532 | #endif | ||
| 533 | |||
| 534 | static struct resource imx_kpp_resources[] = { | ||
| 535 | { | ||
| 536 | .start = MX2x_KPP_BASE_ADDR, | ||
| 537 | .end = MX2x_KPP_BASE_ADDR + 0xf, | ||
| 538 | .flags = IORESOURCE_MEM | ||
| 539 | }, { | ||
| 540 | .start = MX2x_INT_KPP, | ||
| 541 | .end = MX2x_INT_KPP, | ||
| 542 | .flags = IORESOURCE_IRQ, | ||
| 543 | }, | ||
| 544 | }; | ||
| 545 | |||
| 546 | struct platform_device imx_kpp_device = { | ||
| 547 | .name = "imx-keypad", | ||
| 548 | .id = -1, | ||
| 549 | .num_resources = ARRAY_SIZE(imx_kpp_resources), | ||
| 550 | .resource = imx_kpp_resources, | ||
| 551 | }; | ||
| 552 | |||
| 553 | #endif | ||
diff --git a/arch/arm/mach-imx/devices.h b/arch/arm/mach-imx/devices.h deleted file mode 100644 index 807f02a031c9..000000000000 --- a/arch/arm/mach-imx/devices.h +++ /dev/null | |||
| @@ -1,29 +0,0 @@ | |||
| 1 | #ifdef CONFIG_ARCH_MX1 | ||
| 2 | extern struct platform_device imx1_camera_device; | ||
| 3 | extern struct platform_device imx_rtc_device; | ||
| 4 | extern struct platform_device imx_wdt_device; | ||
| 5 | extern struct platform_device imx_usb_device; | ||
| 6 | #endif | ||
| 7 | |||
| 8 | #if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27) | ||
| 9 | extern struct platform_device mxc_gpt1; | ||
| 10 | extern struct platform_device mxc_gpt2; | ||
| 11 | #ifdef CONFIG_MACH_MX27 | ||
| 12 | extern struct platform_device mxc_gpt3; | ||
| 13 | extern struct platform_device mxc_gpt4; | ||
| 14 | extern struct platform_device mxc_gpt5; | ||
| 15 | #endif | ||
| 16 | extern struct platform_device mxc_wdt; | ||
| 17 | extern struct platform_device mxc_w1_master_device; | ||
| 18 | extern struct platform_device mxc_fb_device; | ||
| 19 | extern struct platform_device mxc_pwm_device; | ||
| 20 | extern struct platform_device mxc_sdhc_device0; | ||
| 21 | extern struct platform_device mxc_sdhc_device1; | ||
| 22 | extern struct platform_device mxc_otg_udc_device; | ||
| 23 | extern struct platform_device mx27_camera_device; | ||
| 24 | extern struct platform_device mxc_otg_host; | ||
| 25 | extern struct platform_device mxc_usbh1; | ||
| 26 | extern struct platform_device mxc_usbh2; | ||
| 27 | extern struct platform_device mx21_usbhc_device; | ||
| 28 | extern struct platform_device imx_kpp_device; | ||
| 29 | #endif | ||
diff --git a/arch/arm/mach-imx/dma-v1.c b/arch/arm/mach-imx/dma-v1.c index 3e8c47c63bac..e9f1769b49f5 100644 --- a/arch/arm/mach-imx/dma-v1.c +++ b/arch/arm/mach-imx/dma-v1.c | |||
| @@ -818,9 +818,11 @@ static int __init imx_dma_init(void) | |||
| 818 | imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR); | 818 | imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR); |
| 819 | else | 819 | else |
| 820 | #endif | 820 | #endif |
| 821 | BUG(); | 821 | return 0; |
| 822 | 822 | ||
| 823 | dma_clk = clk_get(NULL, "dma"); | 823 | dma_clk = clk_get(NULL, "dma"); |
| 824 | if (IS_ERR(dma_clk)) | ||
| 825 | return PTR_ERR(dma_clk); | ||
| 824 | clk_enable(dma_clk); | 826 | clk_enable(dma_clk); |
| 825 | 827 | ||
| 826 | /* reset DMA module */ | 828 | /* reset DMA module */ |
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c index 7e1e9dc2c8fc..275c8589d797 100644 --- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c +++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c | |||
| @@ -26,20 +26,16 @@ | |||
| 26 | #include <linux/spi/ads7846.h> | 26 | #include <linux/spi/ads7846.h> |
| 27 | #include <linux/backlight.h> | 27 | #include <linux/backlight.h> |
| 28 | #include <video/platform_lcd.h> | 28 | #include <video/platform_lcd.h> |
| 29 | #include <linux/input/matrix_keypad.h> | ||
| 30 | 29 | ||
| 31 | #include <asm/mach/arch.h> | 30 | #include <asm/mach/arch.h> |
| 32 | 31 | ||
| 33 | #include <mach/common.h> | 32 | #include <mach/common.h> |
| 34 | #include <mach/iomux-mx27.h> | 33 | #include <mach/iomux-mx27.h> |
| 35 | #include <mach/imxfb.h> | ||
| 36 | #include <mach/hardware.h> | 34 | #include <mach/hardware.h> |
| 37 | #include <mach/mmc.h> | ||
| 38 | #include <mach/spi.h> | 35 | #include <mach/spi.h> |
| 39 | #include <mach/audmux.h> | 36 | #include <mach/audmux.h> |
| 40 | 37 | ||
| 41 | #include "devices-imx27.h" | 38 | #include "devices-imx27.h" |
| 42 | #include "devices.h" | ||
| 43 | 39 | ||
| 44 | static const int eukrea_mbimx27_pins[] __initconst = { | 40 | static const int eukrea_mbimx27_pins[] __initconst = { |
| 45 | /* UART2 */ | 41 | /* UART2 */ |
| @@ -111,7 +107,8 @@ static const uint32_t eukrea_mbimx27_keymap[] = { | |||
| 111 | KEY(1, 1, KEY_LEFT), | 107 | KEY(1, 1, KEY_LEFT), |
| 112 | }; | 108 | }; |
| 113 | 109 | ||
| 114 | static struct matrix_keymap_data eukrea_mbimx27_keymap_data = { | 110 | static const struct matrix_keymap_data |
| 111 | eukrea_mbimx27_keymap_data __initconst = { | ||
| 115 | .keymap = eukrea_mbimx27_keymap, | 112 | .keymap = eukrea_mbimx27_keymap, |
| 116 | .keymap_size = ARRAY_SIZE(eukrea_mbimx27_keymap), | 113 | .keymap_size = ARRAY_SIZE(eukrea_mbimx27_keymap), |
| 117 | }; | 114 | }; |
| @@ -196,7 +193,7 @@ static struct imx_fb_videomode eukrea_mbimx27_modes[] = { | |||
| 196 | }, | 193 | }, |
| 197 | }; | 194 | }; |
| 198 | 195 | ||
| 199 | static struct imx_fb_platform_data eukrea_mbimx27_fb_data = { | 196 | static const struct imx_fb_platform_data eukrea_mbimx27_fb_data __initconst = { |
| 200 | .mode = eukrea_mbimx27_modes, | 197 | .mode = eukrea_mbimx27_modes, |
| 201 | .num_modes = ARRAY_SIZE(eukrea_mbimx27_modes), | 198 | .num_modes = ARRAY_SIZE(eukrea_mbimx27_modes), |
| 202 | 199 | ||
| @@ -300,7 +297,7 @@ static struct platform_device *platform_devices[] __initdata = { | |||
| 300 | &leds_gpio, | 297 | &leds_gpio, |
| 301 | }; | 298 | }; |
| 302 | 299 | ||
| 303 | static struct imxmmc_platform_data sdhc_pdata = { | 300 | static const struct imxmmc_platform_data sdhc_pdata __initconst = { |
| 304 | .dat3_card_detect = 1, | 301 | .dat3_card_detect = 1, |
| 305 | }; | 302 | }; |
| 306 | 303 | ||
| @@ -345,8 +342,8 @@ void __init eukrea_mbimx27_baseboard_init(void) | |||
| 345 | imx27_add_imx_uart3(&uart_pdata); | 342 | imx27_add_imx_uart3(&uart_pdata); |
| 346 | #endif | 343 | #endif |
| 347 | 344 | ||
| 348 | mxc_register_device(&mxc_fb_device, &eukrea_mbimx27_fb_data); | 345 | imx27_add_imx_fb(&eukrea_mbimx27_fb_data); |
| 349 | mxc_register_device(&mxc_sdhc_device0, &sdhc_pdata); | 346 | imx27_add_mxc_mmc(0, &sdhc_pdata); |
| 350 | 347 | ||
| 351 | i2c_register_board_info(0, eukrea_mbimx27_i2c_devices, | 348 | i2c_register_board_info(0, eukrea_mbimx27_i2c_devices, |
| 352 | ARRAY_SIZE(eukrea_mbimx27_i2c_devices)); | 349 | ARRAY_SIZE(eukrea_mbimx27_i2c_devices)); |
| @@ -380,7 +377,7 @@ void __init eukrea_mbimx27_baseboard_init(void) | |||
| 380 | gpio_request(GPIO_PORTA | 25, "lcd_enable"); | 377 | gpio_request(GPIO_PORTA | 25, "lcd_enable"); |
| 381 | platform_device_register(&eukrea_mbimx27_lcd_powerdev); | 378 | platform_device_register(&eukrea_mbimx27_lcd_powerdev); |
| 382 | 379 | ||
| 383 | mxc_register_device(&imx_kpp_device, &eukrea_mbimx27_keymap_data); | 380 | imx27_add_imx_keypad(&eukrea_mbimx27_keymap_data); |
| 384 | 381 | ||
| 385 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); | 382 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); |
| 386 | } | 383 | } |
diff --git a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c index e765ac5d9a08..cb705c28de02 100644 --- a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c +++ b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c | |||
| @@ -33,13 +33,11 @@ | |||
| 33 | #include <asm/mach/arch.h> | 33 | #include <asm/mach/arch.h> |
| 34 | #include <mach/mx25.h> | 34 | #include <mach/mx25.h> |
| 35 | #include <mach/imx-uart.h> | 35 | #include <mach/imx-uart.h> |
| 36 | #include <mach/imxfb.h> | ||
| 37 | #include <mach/audmux.h> | 36 | #include <mach/audmux.h> |
| 38 | 37 | ||
| 39 | #include "devices-imx25.h" | 38 | #include "devices-imx25.h" |
| 40 | #include "devices.h" | ||
| 41 | 39 | ||
| 42 | static struct pad_desc eukrea_mbimxsd_pads[] = { | 40 | static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = { |
| 43 | /* LCD */ | 41 | /* LCD */ |
| 44 | MX25_PAD_LD0__LD0, | 42 | MX25_PAD_LD0__LD0, |
| 45 | MX25_PAD_LD1__LD1, | 43 | MX25_PAD_LD1__LD1, |
| @@ -151,7 +149,7 @@ static struct imx_fb_videomode eukrea_mximxsd_modes[] = { | |||
| 151 | }, | 149 | }, |
| 152 | }; | 150 | }; |
| 153 | 151 | ||
| 154 | static struct imx_fb_platform_data eukrea_mximxsd_fb_pdata = { | 152 | static const struct imx_fb_platform_data eukrea_mximxsd_fb_pdata __initconst = { |
| 155 | .mode = eukrea_mximxsd_modes, | 153 | .mode = eukrea_mximxsd_modes, |
| 156 | .num_modes = ARRAY_SIZE(eukrea_mximxsd_modes), | 154 | .num_modes = ARRAY_SIZE(eukrea_mximxsd_modes), |
| 157 | .pwmr = 0x00A903FF, | 155 | .pwmr = 0x00A903FF, |
| @@ -273,11 +271,11 @@ void __init eukrea_mbimxsd25_baseboard_init(void) | |||
| 273 | #endif | 271 | #endif |
| 274 | 272 | ||
| 275 | imx25_add_imx_uart1(&uart_pdata); | 273 | imx25_add_imx_uart1(&uart_pdata); |
| 276 | mxc_register_device(&mx25_fb_device, &eukrea_mximxsd_fb_pdata); | 274 | imx25_add_imx_fb(&eukrea_mximxsd_fb_pdata); |
| 277 | imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); | 275 | imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); |
| 278 | 276 | ||
| 279 | imx25_add_flexcan1(NULL); | 277 | imx25_add_flexcan1(NULL); |
| 280 | imx25_add_esdhc(0, NULL); | 278 | imx25_add_sdhci_esdhc_imx(0, NULL); |
| 281 | 279 | ||
| 282 | gpio_request(GPIO_LED1, "LED1"); | 280 | gpio_request(GPIO_LED1, "LED1"); |
| 283 | gpio_direction_output(GPIO_LED1, 1); | 281 | gpio_direction_output(GPIO_LED1, 1); |
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c index 745ee60fb068..6cf04da2456a 100644 --- a/arch/arm/mach-imx/mach-cpuimx27.c +++ b/arch/arm/mach-imx/mach-cpuimx27.c | |||
| @@ -28,7 +28,6 @@ | |||
| 28 | #include <linux/serial_8250.h> | 28 | #include <linux/serial_8250.h> |
| 29 | #include <linux/usb/otg.h> | 29 | #include <linux/usb/otg.h> |
| 30 | #include <linux/usb/ulpi.h> | 30 | #include <linux/usb/ulpi.h> |
| 31 | #include <linux/fsl_devices.h> | ||
| 32 | 31 | ||
| 33 | #include <asm/mach-types.h> | 32 | #include <asm/mach-types.h> |
| 34 | #include <asm/mach/arch.h> | 33 | #include <asm/mach/arch.h> |
| @@ -40,11 +39,9 @@ | |||
| 40 | #include <mach/hardware.h> | 39 | #include <mach/hardware.h> |
| 41 | #include <mach/iomux-mx27.h> | 40 | #include <mach/iomux-mx27.h> |
| 42 | #include <mach/mxc_nand.h> | 41 | #include <mach/mxc_nand.h> |
| 43 | #include <mach/mxc_ehci.h> | ||
| 44 | #include <mach/ulpi.h> | 42 | #include <mach/ulpi.h> |
| 45 | 43 | ||
| 46 | #include "devices-imx27.h" | 44 | #include "devices-imx27.h" |
| 47 | #include "devices.h" | ||
| 48 | 45 | ||
| 49 | static const int eukrea_cpuimx27_pins[] __initconst = { | 46 | static const int eukrea_cpuimx27_pins[] __initconst = { |
| 50 | /* UART1 */ | 47 | /* UART1 */ |
| @@ -157,8 +154,6 @@ cpuimx27_nand_board_info __initconst = { | |||
| 157 | 154 | ||
| 158 | static struct platform_device *platform_devices[] __initdata = { | 155 | static struct platform_device *platform_devices[] __initdata = { |
| 159 | &eukrea_cpuimx27_nor_mtd_device, | 156 | &eukrea_cpuimx27_nor_mtd_device, |
| 160 | &mxc_wdt, | ||
| 161 | &mxc_w1_master_device, | ||
| 162 | }; | 157 | }; |
| 163 | 158 | ||
| 164 | static const struct imxi2c_platform_data cpuimx27_i2c1_data __initconst = { | 159 | static const struct imxi2c_platform_data cpuimx27_i2c1_data __initconst = { |
| @@ -215,18 +210,18 @@ static struct platform_device serial_device = { | |||
| 215 | #endif | 210 | #endif |
| 216 | 211 | ||
| 217 | #if defined(CONFIG_USB_ULPI) | 212 | #if defined(CONFIG_USB_ULPI) |
| 218 | static struct mxc_usbh_platform_data otg_pdata = { | 213 | static struct mxc_usbh_platform_data otg_pdata __initdata = { |
| 219 | .portsc = MXC_EHCI_MODE_ULPI, | 214 | .portsc = MXC_EHCI_MODE_ULPI, |
| 220 | .flags = MXC_EHCI_INTERFACE_DIFF_UNI, | 215 | .flags = MXC_EHCI_INTERFACE_DIFF_UNI, |
| 221 | }; | 216 | }; |
| 222 | 217 | ||
| 223 | static struct mxc_usbh_platform_data usbh2_pdata = { | 218 | static struct mxc_usbh_platform_data usbh2_pdata __initdata = { |
| 224 | .portsc = MXC_EHCI_MODE_ULPI, | 219 | .portsc = MXC_EHCI_MODE_ULPI, |
| 225 | .flags = MXC_EHCI_INTERFACE_DIFF_UNI, | 220 | .flags = MXC_EHCI_INTERFACE_DIFF_UNI, |
| 226 | }; | 221 | }; |
| 227 | #endif | 222 | #endif |
| 228 | 223 | ||
| 229 | static struct fsl_usb2_platform_data otg_device_pdata = { | 224 | static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { |
| 230 | .operating_mode = FSL_USB2_DR_DEVICE, | 225 | .operating_mode = FSL_USB2_DR_DEVICE, |
| 231 | .phy_mode = FSL_USB2_PHY_ULPI, | 226 | .phy_mode = FSL_USB2_PHY_ULPI, |
| 232 | }; | 227 | }; |
| @@ -262,10 +257,12 @@ static void __init eukrea_cpuimx27_init(void) | |||
| 262 | 257 | ||
| 263 | imx27_add_fec(NULL); | 258 | imx27_add_fec(NULL); |
| 264 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); | 259 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); |
| 260 | imx27_add_imx2_wdt(NULL); | ||
| 261 | imx27_add_mxc_w1(NULL); | ||
| 265 | 262 | ||
| 266 | #if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2) | 263 | #if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2) |
| 267 | /* SDHC2 can be used for Wifi */ | 264 | /* SDHC2 can be used for Wifi */ |
| 268 | mxc_register_device(&mxc_sdhc_device1, NULL); | 265 | imx27_add_mxc_mmc(1, NULL); |
| 269 | #endif | 266 | #endif |
| 270 | #if defined(MACH_EUKREA_CPUIMX27_USEUART4) | 267 | #if defined(MACH_EUKREA_CPUIMX27_USEUART4) |
| 271 | /* in which case UART4 is also used for Bluetooth */ | 268 | /* in which case UART4 is also used for Bluetooth */ |
| @@ -281,16 +278,16 @@ static void __init eukrea_cpuimx27_init(void) | |||
| 281 | otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, | 278 | otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, |
| 282 | ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); | 279 | ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); |
| 283 | 280 | ||
| 284 | mxc_register_device(&mxc_otg_host, &otg_pdata); | 281 | imx27_add_mxc_ehci_otg(&otg_pdata); |
| 285 | } | 282 | } |
| 286 | 283 | ||
| 287 | usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, | 284 | usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, |
| 288 | ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); | 285 | ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); |
| 289 | 286 | ||
| 290 | mxc_register_device(&mxc_usbh2, &usbh2_pdata); | 287 | imx27_add_mxc_ehci_hs(2, &usbh2_pdata); |
| 291 | #endif | 288 | #endif |
| 292 | if (!otg_mode_host) | 289 | if (!otg_mode_host) |
| 293 | mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); | 290 | imx27_add_fsl_usb2_udc(&otg_device_pdata); |
| 294 | 291 | ||
| 295 | #ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD | 292 | #ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD |
| 296 | eukrea_mbimx27_baseboard_init(); | 293 | eukrea_mbimx27_baseboard_init(); |
diff --git a/arch/arm/mach-mx25/mach-cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c index f6f9ad60c25e..eb395aba9237 100644 --- a/arch/arm/mach-mx25/mach-cpuimx25.c +++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c | |||
| @@ -26,7 +26,6 @@ | |||
| 26 | #include <linux/platform_device.h> | 26 | #include <linux/platform_device.h> |
| 27 | #include <linux/usb/otg.h> | 27 | #include <linux/usb/otg.h> |
| 28 | #include <linux/usb/ulpi.h> | 28 | #include <linux/usb/ulpi.h> |
| 29 | #include <linux/fsl_devices.h> | ||
| 30 | 29 | ||
| 31 | #include <mach/eukrea-baseboards.h> | 30 | #include <mach/eukrea-baseboards.h> |
| 32 | #include <mach/hardware.h> | 31 | #include <mach/hardware.h> |
| @@ -39,17 +38,15 @@ | |||
| 39 | #include <mach/mx25.h> | 38 | #include <mach/mx25.h> |
| 40 | #include <mach/mxc_nand.h> | 39 | #include <mach/mxc_nand.h> |
| 41 | #include <mach/imxfb.h> | 40 | #include <mach/imxfb.h> |
| 42 | #include <mach/mxc_ehci.h> | ||
| 43 | #include <mach/iomux-mx25.h> | 41 | #include <mach/iomux-mx25.h> |
| 44 | 42 | ||
| 45 | #include "devices-imx25.h" | 43 | #include "devices-imx25.h" |
| 46 | #include "devices.h" | ||
| 47 | 44 | ||
| 48 | static const struct imxuart_platform_data uart_pdata __initconst = { | 45 | static const struct imxuart_platform_data uart_pdata __initconst = { |
| 49 | .flags = IMXUART_HAVE_RTSCTS, | 46 | .flags = IMXUART_HAVE_RTSCTS, |
| 50 | }; | 47 | }; |
| 51 | 48 | ||
| 52 | static struct pad_desc eukrea_cpuimx25_pads[] = { | 49 | static iomux_v3_cfg_t eukrea_cpuimx25_pads[] = { |
| 53 | /* FEC - RMII */ | 50 | /* FEC - RMII */ |
| 54 | MX25_PAD_FEC_MDC__FEC_MDC, | 51 | MX25_PAD_FEC_MDC__FEC_MDC, |
| 55 | MX25_PAD_FEC_MDIO__FEC_MDIO, | 52 | MX25_PAD_FEC_MDIO__FEC_MDIO, |
| @@ -87,18 +84,18 @@ static struct i2c_board_info eukrea_cpuimx25_i2c_devices[] = { | |||
| 87 | }, | 84 | }, |
| 88 | }; | 85 | }; |
| 89 | 86 | ||
| 90 | static struct mxc_usbh_platform_data otg_pdata = { | 87 | static const struct mxc_usbh_platform_data otg_pdata __initconst = { |
| 91 | .portsc = MXC_EHCI_MODE_UTMI, | 88 | .portsc = MXC_EHCI_MODE_UTMI, |
| 92 | .flags = MXC_EHCI_INTERFACE_DIFF_UNI, | 89 | .flags = MXC_EHCI_INTERFACE_DIFF_UNI, |
| 93 | }; | 90 | }; |
| 94 | 91 | ||
| 95 | static struct mxc_usbh_platform_data usbh2_pdata = { | 92 | static const struct mxc_usbh_platform_data usbh2_pdata __initconst = { |
| 96 | .portsc = MXC_EHCI_MODE_SERIAL, | 93 | .portsc = MXC_EHCI_MODE_SERIAL, |
| 97 | .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | | 94 | .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | |
| 98 | MXC_EHCI_IPPUE_DOWN, | 95 | MXC_EHCI_IPPUE_DOWN, |
| 99 | }; | 96 | }; |
| 100 | 97 | ||
| 101 | static struct fsl_usb2_platform_data otg_device_pdata = { | 98 | static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { |
| 102 | .operating_mode = FSL_USB2_DR_DEVICE, | 99 | .operating_mode = FSL_USB2_DR_DEVICE, |
| 103 | .phy_mode = FSL_USB2_PHY_UTMI, | 100 | .phy_mode = FSL_USB2_PHY_UTMI, |
| 104 | }; | 101 | }; |
| @@ -126,7 +123,7 @@ static void __init eukrea_cpuimx25_init(void) | |||
| 126 | 123 | ||
| 127 | imx25_add_imx_uart0(&uart_pdata); | 124 | imx25_add_imx_uart0(&uart_pdata); |
| 128 | imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info); | 125 | imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info); |
| 129 | mxc_register_device(&mx25_rtc_device, NULL); | 126 | imx25_add_imxdi_rtc(NULL); |
| 130 | imx25_add_fec(&mx25_fec_pdata); | 127 | imx25_add_fec(&mx25_fec_pdata); |
| 131 | 128 | ||
| 132 | i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices, | 129 | i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices, |
| @@ -134,11 +131,11 @@ static void __init eukrea_cpuimx25_init(void) | |||
| 134 | imx25_add_imx_i2c0(&eukrea_cpuimx25_i2c0_data); | 131 | imx25_add_imx_i2c0(&eukrea_cpuimx25_i2c0_data); |
| 135 | 132 | ||
| 136 | if (otg_mode_host) | 133 | if (otg_mode_host) |
| 137 | mxc_register_device(&mxc_otg, &otg_pdata); | 134 | imx25_add_mxc_ehci_otg(&otg_pdata); |
| 138 | else | 135 | else |
| 139 | mxc_register_device(&otg_udc_device, &otg_device_pdata); | 136 | imx25_add_fsl_usb2_udc(&otg_device_pdata); |
| 140 | 137 | ||
| 141 | mxc_register_device(&mxc_usbh2, &usbh2_pdata); | 138 | imx25_add_mxc_ehci_hs(&usbh2_pdata); |
| 142 | 139 | ||
| 143 | #ifdef CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD | 140 | #ifdef CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD |
| 144 | eukrea_mbimxsd25_baseboard_init(); | 141 | eukrea_mbimxsd25_baseboard_init(); |
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c index 59716fab586d..40a3666ea632 100644 --- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c +++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c | |||
| @@ -34,12 +34,9 @@ | |||
| 34 | #include <asm/mach/arch.h> | 34 | #include <asm/mach/arch.h> |
| 35 | #include <asm/mach/time.h> | 35 | #include <asm/mach/time.h> |
| 36 | #include <mach/common.h> | 36 | #include <mach/common.h> |
| 37 | #include <mach/mmc.h> | ||
| 38 | #include <mach/iomux.h> | 37 | #include <mach/iomux.h> |
| 39 | #include <mach/mxc_ehci.h> | ||
| 40 | 38 | ||
| 41 | #include "devices-imx27.h" | 39 | #include "devices-imx27.h" |
| 42 | #include "devices.h" | ||
| 43 | 40 | ||
| 44 | #define OTG_PHY_CS_GPIO (GPIO_PORTF + 17) | 41 | #define OTG_PHY_CS_GPIO (GPIO_PORTF + 17) |
| 45 | #define SDHC1_IRQ IRQ_GPIOB(25) | 42 | #define SDHC1_IRQ IRQ_GPIOB(25) |
| @@ -156,7 +153,7 @@ static void visstrim_m10_sdhc1_exit(struct device *dev, void *data) | |||
| 156 | free_irq(SDHC1_IRQ, data); | 153 | free_irq(SDHC1_IRQ, data); |
| 157 | } | 154 | } |
| 158 | 155 | ||
| 159 | static struct imxmmc_platform_data visstrim_m10_sdhc_pdata = { | 156 | static const struct imxmmc_platform_data visstrim_m10_sdhc_pdata __initconst = { |
| 160 | .init = visstrim_m10_sdhc1_init, | 157 | .init = visstrim_m10_sdhc1_init, |
| 161 | .exit = visstrim_m10_sdhc1_exit, | 158 | .exit = visstrim_m10_sdhc1_exit, |
| 162 | }; | 159 | }; |
| @@ -216,7 +213,8 @@ static int otg_phy_init(struct platform_device *pdev) | |||
| 216 | return 0; | 213 | return 0; |
| 217 | } | 214 | } |
| 218 | 215 | ||
| 219 | static struct mxc_usbh_platform_data visstrim_m10_usbotg_pdata = { | 216 | static const struct mxc_usbh_platform_data |
| 217 | visstrim_m10_usbotg_pdata __initconst = { | ||
| 220 | .init = otg_phy_init, | 218 | .init = otg_phy_init, |
| 221 | .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, | 219 | .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, |
| 222 | .flags = MXC_EHCI_POWER_PINS_ENABLED, | 220 | .flags = MXC_EHCI_POWER_PINS_ENABLED, |
| @@ -237,8 +235,8 @@ static void __init visstrim_m10_board_init(void) | |||
| 237 | ARRAY_SIZE(visstrim_m10_i2c_devices)); | 235 | ARRAY_SIZE(visstrim_m10_i2c_devices)); |
| 238 | imx27_add_imx_i2c(0, &visstrim_m10_i2c_data); | 236 | imx27_add_imx_i2c(0, &visstrim_m10_i2c_data); |
| 239 | imx27_add_imx_i2c(1, &visstrim_m10_i2c_data); | 237 | imx27_add_imx_i2c(1, &visstrim_m10_i2c_data); |
| 240 | mxc_register_device(&mxc_sdhc_device0, &visstrim_m10_sdhc_pdata); | 238 | imx27_add_mxc_mmc(0, &visstrim_m10_sdhc_pdata); |
| 241 | mxc_register_device(&mxc_otg_host, &visstrim_m10_usbotg_pdata); | 239 | imx27_add_mxc_ehci_otg(&visstrim_m10_usbotg_pdata); |
| 242 | imx27_add_fec(NULL); | 240 | imx27_add_fec(NULL); |
| 243 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); | 241 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); |
| 244 | } | 242 | } |
diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c index bbdbc75127d3..3a1202e47212 100644 --- a/arch/arm/mach-imx/mach-imx27lite.c +++ b/arch/arm/mach-imx/mach-imx27lite.c | |||
| @@ -25,7 +25,6 @@ | |||
| 25 | #include <mach/iomux-mx27.h> | 25 | #include <mach/iomux-mx27.h> |
| 26 | 26 | ||
| 27 | #include "devices-imx27.h" | 27 | #include "devices-imx27.h" |
| 28 | #include "devices.h" | ||
| 29 | 28 | ||
| 30 | static const int mx27lite_pins[] __initconst = { | 29 | static const int mx27lite_pins[] __initconst = { |
| 31 | /* UART1 */ | 30 | /* UART1 */ |
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c index 6187ce9ba7d5..1f446e5eb636 100644 --- a/arch/arm/mach-imx/mach-mx1ads.c +++ b/arch/arm/mach-imx/mach-mx1ads.c | |||
| @@ -30,7 +30,6 @@ | |||
| 30 | #include <mach/irqs.h> | 30 | #include <mach/irqs.h> |
| 31 | 31 | ||
| 32 | #include "devices-imx1.h" | 32 | #include "devices-imx1.h" |
| 33 | #include "devices.h" | ||
| 34 | 33 | ||
| 35 | static const int mx1ads_pins[] __initconst = { | 34 | static const int mx1ads_pins[] __initconst = { |
| 36 | /* UART1 */ | 35 | /* UART1 */ |
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c index e1282e9f50ff..0a372577c2ac 100644 --- a/arch/arm/mach-imx/mach-mx21ads.c +++ b/arch/arm/mach-imx/mach-mx21ads.c | |||
| @@ -24,13 +24,10 @@ | |||
| 24 | #include <asm/mach/arch.h> | 24 | #include <asm/mach/arch.h> |
| 25 | #include <asm/mach/time.h> | 25 | #include <asm/mach/time.h> |
| 26 | #include <asm/mach/map.h> | 26 | #include <asm/mach/map.h> |
| 27 | #include <mach/imxfb.h> | ||
| 28 | #include <mach/iomux-mx21.h> | 27 | #include <mach/iomux-mx21.h> |
| 29 | #include <mach/mxc_nand.h> | 28 | #include <mach/mxc_nand.h> |
| 30 | #include <mach/mmc.h> | ||
| 31 | 29 | ||
| 32 | #include "devices-imx21.h" | 30 | #include "devices-imx21.h" |
| 33 | #include "devices.h" | ||
| 34 | 31 | ||
| 35 | /* | 32 | /* |
| 36 | * Memory-mapped I/O on MX21ADS base board | 33 | * Memory-mapped I/O on MX21ADS base board |
| @@ -213,7 +210,7 @@ static struct imx_fb_videomode mx21ads_modes[] = { | |||
| 213 | }, | 210 | }, |
| 214 | }; | 211 | }; |
| 215 | 212 | ||
| 216 | static struct imx_fb_platform_data mx21ads_fb_data = { | 213 | static const struct imx_fb_platform_data mx21ads_fb_data __initconst = { |
| 217 | .mode = mx21ads_modes, | 214 | .mode = mx21ads_modes, |
| 218 | .num_modes = ARRAY_SIZE(mx21ads_modes), | 215 | .num_modes = ARRAY_SIZE(mx21ads_modes), |
| 219 | 216 | ||
| @@ -233,15 +230,8 @@ static int mx21ads_sdhc_get_ro(struct device *dev) | |||
| 233 | static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq, | 230 | static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq, |
| 234 | void *data) | 231 | void *data) |
| 235 | { | 232 | { |
| 236 | int ret; | 233 | return request_irq(IRQ_GPIOD(25), detect_irq, |
| 237 | |||
| 238 | ret = request_irq(IRQ_GPIOD(25), detect_irq, | ||
| 239 | IRQF_TRIGGER_FALLING, "mmc-detect", data); | 234 | IRQF_TRIGGER_FALLING, "mmc-detect", data); |
| 240 | if (ret) | ||
| 241 | goto out; | ||
| 242 | return 0; | ||
| 243 | out: | ||
| 244 | return ret; | ||
| 245 | } | 235 | } |
| 246 | 236 | ||
| 247 | static void mx21ads_sdhc_exit(struct device *dev, void *data) | 237 | static void mx21ads_sdhc_exit(struct device *dev, void *data) |
| @@ -249,7 +239,7 @@ static void mx21ads_sdhc_exit(struct device *dev, void *data) | |||
| 249 | free_irq(IRQ_GPIOD(25), data); | 239 | free_irq(IRQ_GPIOD(25), data); |
| 250 | } | 240 | } |
| 251 | 241 | ||
| 252 | static struct imxmmc_platform_data mx21ads_sdhc_pdata = { | 242 | static const struct imxmmc_platform_data mx21ads_sdhc_pdata __initconst = { |
| 253 | .ocr_avail = MMC_VDD_29_30 | MMC_VDD_30_31, /* 3.0V */ | 243 | .ocr_avail = MMC_VDD_29_30 | MMC_VDD_30_31, /* 3.0V */ |
| 254 | .get_ro = mx21ads_sdhc_get_ro, | 244 | .get_ro = mx21ads_sdhc_get_ro, |
| 255 | .init = mx21ads_sdhc_init, | 245 | .init = mx21ads_sdhc_init, |
| @@ -296,8 +286,8 @@ static void __init mx21ads_board_init(void) | |||
| 296 | imx21_add_imx_uart0(&uart_pdata_rts); | 286 | imx21_add_imx_uart0(&uart_pdata_rts); |
| 297 | imx21_add_imx_uart2(&uart_pdata_norts); | 287 | imx21_add_imx_uart2(&uart_pdata_norts); |
| 298 | imx21_add_imx_uart3(&uart_pdata_rts); | 288 | imx21_add_imx_uart3(&uart_pdata_rts); |
| 299 | mxc_register_device(&mxc_fb_device, &mx21ads_fb_data); | 289 | imx21_add_imx_fb(&mx21ads_fb_data); |
| 300 | mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata); | 290 | imx21_add_mxc_mmc(0, &mx21ads_sdhc_pdata); |
| 301 | imx21_add_mxc_nand(&mx21ads_nand_board_info); | 291 | imx21_add_mxc_nand(&mx21ads_nand_board_info); |
| 302 | 292 | ||
| 303 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); | 293 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); |
diff --git a/arch/arm/mach-mx25/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c index f8be1eb0c062..aa76cfd9f348 100644 --- a/arch/arm/mach-mx25/mach-mx25_3ds.c +++ b/arch/arm/mach-imx/mach-mx25_3ds.c | |||
| @@ -30,6 +30,7 @@ | |||
| 30 | #include <linux/gpio.h> | 30 | #include <linux/gpio.h> |
| 31 | #include <linux/platform_device.h> | 31 | #include <linux/platform_device.h> |
| 32 | #include <linux/input/matrix_keypad.h> | 32 | #include <linux/input/matrix_keypad.h> |
| 33 | #include <linux/usb/otg.h> | ||
| 33 | 34 | ||
| 34 | #include <mach/hardware.h> | 35 | #include <mach/hardware.h> |
| 35 | #include <asm/mach-types.h> | 36 | #include <asm/mach-types.h> |
| @@ -39,17 +40,15 @@ | |||
| 39 | #include <asm/mach/map.h> | 40 | #include <asm/mach/map.h> |
| 40 | #include <mach/common.h> | 41 | #include <mach/common.h> |
| 41 | #include <mach/mx25.h> | 42 | #include <mach/mx25.h> |
| 42 | #include <mach/imxfb.h> | ||
| 43 | #include <mach/iomux-mx25.h> | 43 | #include <mach/iomux-mx25.h> |
| 44 | 44 | ||
| 45 | #include "devices-imx25.h" | 45 | #include "devices-imx25.h" |
| 46 | #include "devices.h" | ||
| 47 | 46 | ||
| 48 | static const struct imxuart_platform_data uart_pdata __initconst = { | 47 | static const struct imxuart_platform_data uart_pdata __initconst = { |
| 49 | .flags = IMXUART_HAVE_RTSCTS, | 48 | .flags = IMXUART_HAVE_RTSCTS, |
| 50 | }; | 49 | }; |
| 51 | 50 | ||
| 52 | static struct pad_desc mx25pdk_pads[] = { | 51 | static iomux_v3_cfg_t mx25pdk_pads[] = { |
| 53 | MX25_PAD_FEC_MDC__FEC_MDC, | 52 | MX25_PAD_FEC_MDC__FEC_MDC, |
| 54 | MX25_PAD_FEC_MDIO__FEC_MDIO, | 53 | MX25_PAD_FEC_MDIO__FEC_MDIO, |
| 55 | MX25_PAD_FEC_TDATA0__FEC_TDATA0, | 54 | MX25_PAD_FEC_TDATA0__FEC_TDATA0, |
| @@ -107,7 +106,7 @@ static struct pad_desc mx25pdk_pads[] = { | |||
| 107 | }; | 106 | }; |
| 108 | 107 | ||
| 109 | static const struct fec_platform_data mx25_fec_pdata __initconst = { | 108 | static const struct fec_platform_data mx25_fec_pdata __initconst = { |
| 110 | .phy = PHY_INTERFACE_MODE_RMII, | 109 | .phy = PHY_INTERFACE_MODE_RMII, |
| 111 | }; | 110 | }; |
| 112 | 111 | ||
| 113 | #define FEC_ENABLE_GPIO 35 | 112 | #define FEC_ENABLE_GPIO 35 |
| @@ -154,7 +153,7 @@ static struct imx_fb_videomode mx25pdk_modes[] = { | |||
| 154 | }, | 153 | }, |
| 155 | }; | 154 | }; |
| 156 | 155 | ||
| 157 | static struct imx_fb_platform_data mx25pdk_fb_pdata = { | 156 | static const struct imx_fb_platform_data mx25pdk_fb_pdata __initconst = { |
| 158 | .mode = mx25pdk_modes, | 157 | .mode = mx25pdk_modes, |
| 159 | .num_modes = ARRAY_SIZE(mx25pdk_modes), | 158 | .num_modes = ARRAY_SIZE(mx25pdk_modes), |
| 160 | .pwmr = 0x00A903FF, | 159 | .pwmr = 0x00A903FF, |
| @@ -181,28 +180,39 @@ static const uint32_t mx25pdk_keymap[] = { | |||
| 181 | KEY(3, 3, KEY_POWER), | 180 | KEY(3, 3, KEY_POWER), |
| 182 | }; | 181 | }; |
| 183 | 182 | ||
| 184 | static struct matrix_keymap_data mx25pdk_keymap_data = { | 183 | static const struct matrix_keymap_data mx25pdk_keymap_data __initdata = { |
| 185 | .keymap = mx25pdk_keymap, | 184 | .keymap = mx25pdk_keymap, |
| 186 | .keymap_size = ARRAY_SIZE(mx25pdk_keymap), | 185 | .keymap_size = ARRAY_SIZE(mx25pdk_keymap), |
| 187 | }; | 186 | }; |
| 188 | 187 | ||
| 188 | static const struct mxc_usbh_platform_data usbh2_pdata __initconst = { | ||
| 189 | .portsc = MXC_EHCI_MODE_SERIAL, | ||
| 190 | .flags = MXC_EHCI_INTERNAL_PHY, | ||
| 191 | }; | ||
| 192 | |||
| 193 | static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { | ||
| 194 | .operating_mode = FSL_USB2_DR_DEVICE, | ||
| 195 | .phy_mode = FSL_USB2_PHY_UTMI, | ||
| 196 | }; | ||
| 197 | |||
| 189 | static void __init mx25pdk_init(void) | 198 | static void __init mx25pdk_init(void) |
| 190 | { | 199 | { |
| 191 | mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads, | 200 | mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads, |
| 192 | ARRAY_SIZE(mx25pdk_pads)); | 201 | ARRAY_SIZE(mx25pdk_pads)); |
| 193 | 202 | ||
| 194 | imx25_add_imx_uart0(&uart_pdata); | 203 | imx25_add_imx_uart0(&uart_pdata); |
| 195 | mxc_register_device(&mxc_usbh2, NULL); | 204 | imx25_add_fsl_usb2_udc(&otg_device_pdata); |
| 205 | imx25_add_mxc_ehci_hs(&usbh2_pdata); | ||
| 196 | imx25_add_mxc_nand(&mx25pdk_nand_board_info); | 206 | imx25_add_mxc_nand(&mx25pdk_nand_board_info); |
| 197 | mxc_register_device(&mx25_rtc_device, NULL); | 207 | imx25_add_imxdi_rtc(NULL); |
| 198 | mxc_register_device(&mx25_fb_device, &mx25pdk_fb_pdata); | 208 | imx25_add_imx_fb(&mx25pdk_fb_pdata); |
| 199 | mxc_register_device(&mxc_wdt, NULL); | 209 | imx25_add_imx2_wdt(NULL); |
| 200 | 210 | ||
| 201 | mx25pdk_fec_reset(); | 211 | mx25pdk_fec_reset(); |
| 202 | imx25_add_fec(&mx25_fec_pdata); | 212 | imx25_add_fec(&mx25_fec_pdata); |
| 203 | mxc_register_device(&mx25_kpp_device, &mx25pdk_keymap_data); | 213 | imx25_add_imx_keypad(&mx25pdk_keymap_data); |
| 204 | 214 | ||
| 205 | imx25_add_esdhc(0, NULL); | 215 | imx25_add_sdhci_esdhc_imx(0, NULL); |
| 206 | } | 216 | } |
| 207 | 217 | ||
| 208 | static void __init mx25pdk_timer_init(void) | 218 | static void __init mx25pdk_timer_init(void) |
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c index 84a5ba03f1ba..6fd0f8f6deb6 100644 --- a/arch/arm/mach-imx/mach-mx27_3ds.c +++ b/arch/arm/mach-imx/mach-mx27_3ds.c | |||
| @@ -22,20 +22,27 @@ | |||
| 22 | 22 | ||
| 23 | #include <linux/platform_device.h> | 23 | #include <linux/platform_device.h> |
| 24 | #include <linux/gpio.h> | 24 | #include <linux/gpio.h> |
| 25 | #include <linux/input/matrix_keypad.h> | ||
| 26 | #include <linux/irq.h> | 25 | #include <linux/irq.h> |
| 26 | #include <linux/usb/otg.h> | ||
| 27 | #include <linux/usb/ulpi.h> | ||
| 28 | #include <linux/delay.h> | ||
| 29 | #include <linux/mfd/mc13783.h> | ||
| 30 | #include <linux/spi/spi.h> | ||
| 31 | #include <linux/regulator/machine.h> | ||
| 32 | |||
| 27 | #include <asm/mach-types.h> | 33 | #include <asm/mach-types.h> |
| 28 | #include <asm/mach/arch.h> | 34 | #include <asm/mach/arch.h> |
| 29 | #include <asm/mach/time.h> | 35 | #include <asm/mach/time.h> |
| 30 | #include <mach/hardware.h> | 36 | #include <mach/hardware.h> |
| 31 | #include <mach/common.h> | 37 | #include <mach/common.h> |
| 32 | #include <mach/iomux-mx27.h> | 38 | #include <mach/iomux-mx27.h> |
| 33 | #include <mach/mmc.h> | 39 | #include <mach/ulpi.h> |
| 34 | 40 | ||
| 35 | #include "devices-imx27.h" | 41 | #include "devices-imx27.h" |
| 36 | #include "devices.h" | ||
| 37 | 42 | ||
| 38 | #define SD1_EN_GPIO (GPIO_PORTB + 25) | 43 | #define SD1_EN_GPIO (GPIO_PORTB + 25) |
| 44 | #define OTG_PHY_RESET_GPIO (GPIO_PORTB + 23) | ||
| 45 | #define SPI2_SS0 (GPIO_PORTD + 21) | ||
| 39 | 46 | ||
| 40 | static const int mx27pdk_pins[] __initconst = { | 47 | static const int mx27pdk_pins[] __initconst = { |
| 41 | /* UART1 */ | 48 | /* UART1 */ |
| @@ -70,6 +77,24 @@ static const int mx27pdk_pins[] __initconst = { | |||
| 70 | PE22_PF_SD1_CMD, | 77 | PE22_PF_SD1_CMD, |
| 71 | PE23_PF_SD1_CLK, | 78 | PE23_PF_SD1_CLK, |
| 72 | SD1_EN_GPIO | GPIO_GPIO | GPIO_OUT, | 79 | SD1_EN_GPIO | GPIO_GPIO | GPIO_OUT, |
| 80 | /* OTG */ | ||
| 81 | OTG_PHY_RESET_GPIO | GPIO_GPIO | GPIO_OUT, | ||
| 82 | PC7_PF_USBOTG_DATA5, | ||
| 83 | PC8_PF_USBOTG_DATA6, | ||
| 84 | PC9_PF_USBOTG_DATA0, | ||
| 85 | PC10_PF_USBOTG_DATA2, | ||
| 86 | PC11_PF_USBOTG_DATA1, | ||
| 87 | PC12_PF_USBOTG_DATA4, | ||
| 88 | PC13_PF_USBOTG_DATA3, | ||
| 89 | PE0_PF_USBOTG_NXT, | ||
| 90 | PE1_PF_USBOTG_STP, | ||
| 91 | PE2_PF_USBOTG_DIR, | ||
| 92 | PE24_PF_USBOTG_CLK, | ||
| 93 | PE25_PF_USBOTG_DATA7, | ||
| 94 | /* CSPI2 */ | ||
| 95 | PD22_PF_CSPI2_SCLK, | ||
| 96 | PD23_PF_CSPI2_MISO, | ||
| 97 | PD24_PF_CSPI2_MOSI, | ||
| 73 | }; | 98 | }; |
| 74 | 99 | ||
| 75 | static const struct imxuart_platform_data uart_pdata __initconst = { | 100 | static const struct imxuart_platform_data uart_pdata __initconst = { |
| @@ -92,7 +117,7 @@ static const uint32_t mx27_3ds_keymap[] = { | |||
| 92 | KEY(2, 3, KEY_F10), | 117 | KEY(2, 3, KEY_F10), |
| 93 | }; | 118 | }; |
| 94 | 119 | ||
| 95 | static struct matrix_keymap_data mx27_3ds_keymap_data = { | 120 | static const struct matrix_keymap_data mx27_3ds_keymap_data __initconst = { |
| 96 | .keymap = mx27_3ds_keymap, | 121 | .keymap = mx27_3ds_keymap, |
| 97 | .keymap_size = ARRAY_SIZE(mx27_3ds_keymap), | 122 | .keymap_size = ARRAY_SIZE(mx27_3ds_keymap), |
| 98 | }; | 123 | }; |
| @@ -109,7 +134,7 @@ static void mx27_3ds_sdhc1_exit(struct device *dev, void *data) | |||
| 109 | free_irq(IRQ_GPIOB(26), data); | 134 | free_irq(IRQ_GPIOB(26), data); |
| 110 | } | 135 | } |
| 111 | 136 | ||
| 112 | static struct imxmmc_platform_data sdhc1_pdata = { | 137 | static const struct imxmmc_platform_data sdhc1_pdata __initconst = { |
| 113 | .init = mx27_3ds_sdhc1_init, | 138 | .init = mx27_3ds_sdhc1_init, |
| 114 | .exit = mx27_3ds_sdhc1_exit, | 139 | .exit = mx27_3ds_sdhc1_exit, |
| 115 | }; | 140 | }; |
| @@ -121,6 +146,111 @@ static void mx27_3ds_sdhc1_enable_level_translator(void) | |||
| 121 | gpio_direction_output(SD1_EN_GPIO, 1); | 146 | gpio_direction_output(SD1_EN_GPIO, 1); |
| 122 | } | 147 | } |
| 123 | 148 | ||
| 149 | |||
| 150 | static int otg_phy_init(void) | ||
| 151 | { | ||
| 152 | gpio_request(OTG_PHY_RESET_GPIO, "usb-otg-reset"); | ||
| 153 | gpio_direction_output(OTG_PHY_RESET_GPIO, 0); | ||
| 154 | mdelay(1); | ||
| 155 | gpio_set_value(OTG_PHY_RESET_GPIO, 1); | ||
| 156 | return 0; | ||
| 157 | } | ||
| 158 | |||
| 159 | #if defined(CONFIG_USB_ULPI) | ||
| 160 | |||
| 161 | static struct mxc_usbh_platform_data otg_pdata __initdata = { | ||
| 162 | .portsc = MXC_EHCI_MODE_ULPI, | ||
| 163 | .flags = MXC_EHCI_INTERFACE_DIFF_UNI, | ||
| 164 | }; | ||
| 165 | #endif | ||
| 166 | |||
| 167 | static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { | ||
| 168 | .operating_mode = FSL_USB2_DR_DEVICE, | ||
| 169 | .phy_mode = FSL_USB2_PHY_ULPI, | ||
| 170 | }; | ||
| 171 | |||
| 172 | static int otg_mode_host; | ||
| 173 | |||
| 174 | static int __init mx27_3ds_otg_mode(char *options) | ||
| 175 | { | ||
| 176 | if (!strcmp(options, "host")) | ||
| 177 | otg_mode_host = 1; | ||
| 178 | else if (!strcmp(options, "device")) | ||
| 179 | otg_mode_host = 0; | ||
| 180 | else | ||
| 181 | pr_info("otg_mode neither \"host\" nor \"device\". " | ||
| 182 | "Defaulting to device\n"); | ||
| 183 | return 0; | ||
| 184 | } | ||
| 185 | __setup("otg_mode=", mx27_3ds_otg_mode); | ||
| 186 | |||
| 187 | /* Regulators */ | ||
| 188 | static struct regulator_consumer_supply vmmc1_consumers[] = { | ||
| 189 | REGULATOR_SUPPLY("lcd_2v8", NULL), | ||
| 190 | }; | ||
| 191 | |||
| 192 | static struct regulator_init_data vmmc1_init = { | ||
| 193 | .constraints = { | ||
| 194 | .min_uV = 2800000, | ||
| 195 | .max_uV = 2800000, | ||
| 196 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, | ||
| 197 | }, | ||
| 198 | .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers), | ||
| 199 | .consumer_supplies = vmmc1_consumers, | ||
| 200 | }; | ||
| 201 | |||
| 202 | static struct regulator_consumer_supply vgen_consumers[] = { | ||
| 203 | REGULATOR_SUPPLY("vdd_lcdio", NULL), | ||
| 204 | }; | ||
| 205 | |||
| 206 | static struct regulator_init_data vgen_init = { | ||
| 207 | .constraints = { | ||
| 208 | .min_uV = 1800000, | ||
| 209 | .max_uV = 1800000, | ||
| 210 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, | ||
| 211 | }, | ||
| 212 | .num_consumer_supplies = ARRAY_SIZE(vgen_consumers), | ||
| 213 | .consumer_supplies = vgen_consumers, | ||
| 214 | }; | ||
| 215 | |||
| 216 | static struct mc13783_regulator_init_data mx27_3ds_regulators[] = { | ||
| 217 | { | ||
| 218 | .id = MC13783_REGU_VMMC1, | ||
| 219 | .init_data = &vmmc1_init, | ||
| 220 | }, { | ||
| 221 | .id = MC13783_REGU_VGEN, | ||
| 222 | .init_data = &vgen_init, | ||
| 223 | }, | ||
| 224 | }; | ||
| 225 | |||
| 226 | /* MC13783 */ | ||
| 227 | static struct mc13783_platform_data mc13783_pdata __initdata = { | ||
| 228 | .regulators = mx27_3ds_regulators, | ||
| 229 | .num_regulators = ARRAY_SIZE(mx27_3ds_regulators), | ||
| 230 | .flags = MC13783_USE_REGULATOR, | ||
| 231 | }; | ||
| 232 | |||
| 233 | /* SPI */ | ||
| 234 | static int spi2_internal_chipselect[] = {SPI2_SS0}; | ||
| 235 | |||
| 236 | static const struct spi_imx_master spi2_pdata __initconst = { | ||
| 237 | .chipselect = spi2_internal_chipselect, | ||
| 238 | .num_chipselect = ARRAY_SIZE(spi2_internal_chipselect), | ||
| 239 | }; | ||
| 240 | |||
| 241 | static struct spi_board_info mx27_3ds_spi_devs[] __initdata = { | ||
| 242 | { | ||
| 243 | .modalias = "mc13783", | ||
| 244 | .max_speed_hz = 1000000, | ||
| 245 | .bus_num = 1, | ||
| 246 | .chip_select = 0, /* SS0 */ | ||
| 247 | .platform_data = &mc13783_pdata, | ||
| 248 | .irq = IRQ_GPIOC(14), | ||
| 249 | .mode = SPI_CS_HIGH, | ||
| 250 | }, | ||
| 251 | }; | ||
| 252 | |||
| 253 | |||
| 124 | static void __init mx27pdk_init(void) | 254 | static void __init mx27pdk_init(void) |
| 125 | { | 255 | { |
| 126 | mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins), | 256 | mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins), |
| @@ -128,8 +258,24 @@ static void __init mx27pdk_init(void) | |||
| 128 | mx27_3ds_sdhc1_enable_level_translator(); | 258 | mx27_3ds_sdhc1_enable_level_translator(); |
| 129 | imx27_add_imx_uart0(&uart_pdata); | 259 | imx27_add_imx_uart0(&uart_pdata); |
| 130 | imx27_add_fec(NULL); | 260 | imx27_add_fec(NULL); |
| 131 | mxc_register_device(&imx_kpp_device, &mx27_3ds_keymap_data); | 261 | imx27_add_imx_keypad(&mx27_3ds_keymap_data); |
| 132 | mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata); | 262 | imx27_add_mxc_mmc(0, &sdhc1_pdata); |
| 263 | imx27_add_imx2_wdt(NULL); | ||
| 264 | otg_phy_init(); | ||
| 265 | #if defined(CONFIG_USB_ULPI) | ||
| 266 | if (otg_mode_host) { | ||
| 267 | otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, | ||
| 268 | ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); | ||
| 269 | |||
| 270 | imx27_add_mxc_ehci_otg(&otg_pdata); | ||
| 271 | } | ||
| 272 | #endif | ||
| 273 | if (!otg_mode_host) | ||
| 274 | imx27_add_fsl_usb2_udc(&otg_device_pdata); | ||
| 275 | |||
| 276 | imx27_add_spi_imx1(&spi2_pdata); | ||
| 277 | spi_register_board_info(mx27_3ds_spi_devs, | ||
| 278 | ARRAY_SIZE(mx27_3ds_spi_devs)); | ||
| 133 | } | 279 | } |
| 134 | 280 | ||
| 135 | static void __init mx27pdk_timer_init(void) | 281 | static void __init mx27pdk_timer_init(void) |
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c index a1e4bc573afc..b832f960fec4 100644 --- a/arch/arm/mach-imx/mach-mx27ads.c +++ b/arch/arm/mach-imx/mach-mx27ads.c | |||
| @@ -30,11 +30,8 @@ | |||
| 30 | #include <mach/gpio.h> | 30 | #include <mach/gpio.h> |
| 31 | #include <mach/iomux-mx27.h> | 31 | #include <mach/iomux-mx27.h> |
| 32 | #include <mach/mxc_nand.h> | 32 | #include <mach/mxc_nand.h> |
| 33 | #include <mach/imxfb.h> | ||
| 34 | #include <mach/mmc.h> | ||
| 35 | 33 | ||
| 36 | #include "devices-imx27.h" | 34 | #include "devices-imx27.h" |
| 37 | #include "devices.h" | ||
| 38 | 35 | ||
| 39 | /* | 36 | /* |
| 40 | * Base address of PBC controller, CS4 | 37 | * Base address of PBC controller, CS4 |
| @@ -228,7 +225,7 @@ static struct imx_fb_videomode mx27ads_modes[] = { | |||
| 228 | }, | 225 | }, |
| 229 | }; | 226 | }; |
| 230 | 227 | ||
| 231 | static struct imx_fb_platform_data mx27ads_fb_data = { | 228 | static const struct imx_fb_platform_data mx27ads_fb_data __initconst = { |
| 232 | .mode = mx27ads_modes, | 229 | .mode = mx27ads_modes, |
| 233 | .num_modes = ARRAY_SIZE(mx27ads_modes), | 230 | .num_modes = ARRAY_SIZE(mx27ads_modes), |
| 234 | 231 | ||
| @@ -272,19 +269,18 @@ static void mx27ads_sdhc2_exit(struct device *dev, void *data) | |||
| 272 | free_irq(IRQ_GPIOB(7), data); | 269 | free_irq(IRQ_GPIOB(7), data); |
| 273 | } | 270 | } |
| 274 | 271 | ||
| 275 | static struct imxmmc_platform_data sdhc1_pdata = { | 272 | static const struct imxmmc_platform_data sdhc1_pdata __initconst = { |
| 276 | .init = mx27ads_sdhc1_init, | 273 | .init = mx27ads_sdhc1_init, |
| 277 | .exit = mx27ads_sdhc1_exit, | 274 | .exit = mx27ads_sdhc1_exit, |
| 278 | }; | 275 | }; |
| 279 | 276 | ||
| 280 | static struct imxmmc_platform_data sdhc2_pdata = { | 277 | static const struct imxmmc_platform_data sdhc2_pdata __initconst = { |
| 281 | .init = mx27ads_sdhc2_init, | 278 | .init = mx27ads_sdhc2_init, |
| 282 | .exit = mx27ads_sdhc2_exit, | 279 | .exit = mx27ads_sdhc2_exit, |
| 283 | }; | 280 | }; |
| 284 | 281 | ||
| 285 | static struct platform_device *platform_devices[] __initdata = { | 282 | static struct platform_device *platform_devices[] __initdata = { |
| 286 | &mx27ads_nor_mtd_device, | 283 | &mx27ads_nor_mtd_device, |
| 287 | &mxc_w1_master_device, | ||
| 288 | }; | 284 | }; |
| 289 | 285 | ||
| 290 | static const struct imxuart_platform_data uart_pdata __initconst = { | 286 | static const struct imxuart_platform_data uart_pdata __initconst = { |
| @@ -308,12 +304,13 @@ static void __init mx27ads_board_init(void) | |||
| 308 | i2c_register_board_info(1, mx27ads_i2c_devices, | 304 | i2c_register_board_info(1, mx27ads_i2c_devices, |
| 309 | ARRAY_SIZE(mx27ads_i2c_devices)); | 305 | ARRAY_SIZE(mx27ads_i2c_devices)); |
| 310 | imx27_add_imx_i2c(1, &mx27ads_i2c1_data); | 306 | imx27_add_imx_i2c(1, &mx27ads_i2c1_data); |
| 311 | mxc_register_device(&mxc_fb_device, &mx27ads_fb_data); | 307 | imx27_add_imx_fb(&mx27ads_fb_data); |
| 312 | mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata); | 308 | imx27_add_mxc_mmc(0, &sdhc1_pdata); |
| 313 | mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata); | 309 | imx27_add_mxc_mmc(1, &sdhc2_pdata); |
| 314 | 310 | ||
| 315 | imx27_add_fec(NULL); | 311 | imx27_add_fec(NULL); |
| 316 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); | 312 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); |
| 313 | imx27_add_mxc_w1(NULL); | ||
| 317 | } | 314 | } |
| 318 | 315 | ||
| 319 | static void __init mx27ads_timer_init(void) | 316 | static void __init mx27ads_timer_init(void) |
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c index 38d3a4ae17c7..4ce71b0401db 100644 --- a/arch/arm/mach-imx/mach-mxt_td60.c +++ b/arch/arm/mach-imx/mach-mxt_td60.c | |||
| @@ -31,11 +31,8 @@ | |||
| 31 | #include <mach/iomux-mx27.h> | 31 | #include <mach/iomux-mx27.h> |
| 32 | #include <mach/mxc_nand.h> | 32 | #include <mach/mxc_nand.h> |
| 33 | #include <linux/i2c/pca953x.h> | 33 | #include <linux/i2c/pca953x.h> |
| 34 | #include <mach/imxfb.h> | ||
| 35 | #include <mach/mmc.h> | ||
| 36 | 34 | ||
| 37 | #include "devices-imx27.h" | 35 | #include "devices-imx27.h" |
| 38 | #include "devices.h" | ||
| 39 | 36 | ||
| 40 | static const int mxt_td60_pins[] __initconst = { | 37 | static const int mxt_td60_pins[] __initconst = { |
| 41 | /* UART0 */ | 38 | /* UART0 */ |
| @@ -196,7 +193,7 @@ static struct imx_fb_videomode mxt_td60_modes[] = { | |||
| 196 | }, | 193 | }, |
| 197 | }; | 194 | }; |
| 198 | 195 | ||
| 199 | static struct imx_fb_platform_data mxt_td60_fb_data = { | 196 | static const struct imx_fb_platform_data mxt_td60_fb_data __initconst = { |
| 200 | .mode = mxt_td60_modes, | 197 | .mode = mxt_td60_modes, |
| 201 | .num_modes = ARRAY_SIZE(mxt_td60_modes), | 198 | .num_modes = ARRAY_SIZE(mxt_td60_modes), |
| 202 | 199 | ||
| @@ -226,7 +223,7 @@ static void mxt_td60_sdhc1_exit(struct device *dev, void *data) | |||
| 226 | free_irq(IRQ_GPIOF(8), data); | 223 | free_irq(IRQ_GPIOF(8), data); |
| 227 | } | 224 | } |
| 228 | 225 | ||
| 229 | static struct imxmmc_platform_data sdhc1_pdata = { | 226 | static const struct imxmmc_platform_data sdhc1_pdata __initconst = { |
| 230 | .init = mxt_td60_sdhc1_init, | 227 | .init = mxt_td60_sdhc1_init, |
| 231 | .exit = mxt_td60_sdhc1_exit, | 228 | .exit = mxt_td60_sdhc1_exit, |
| 232 | }; | 229 | }; |
| @@ -253,8 +250,8 @@ static void __init mxt_td60_board_init(void) | |||
| 253 | 250 | ||
| 254 | imx27_add_imx_i2c(0, &mxt_td60_i2c0_data); | 251 | imx27_add_imx_i2c(0, &mxt_td60_i2c0_data); |
| 255 | imx27_add_imx_i2c(1, &mxt_td60_i2c1_data); | 252 | imx27_add_imx_i2c(1, &mxt_td60_i2c1_data); |
| 256 | mxc_register_device(&mxc_fb_device, &mxt_td60_fb_data); | 253 | imx27_add_imx_fb(&mxt_td60_fb_data); |
| 257 | mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata); | 254 | imx27_add_mxc_mmc(0, &sdhc1_pdata); |
| 258 | imx27_add_fec(NULL); | 255 | imx27_add_fec(NULL); |
| 259 | } | 256 | } |
| 260 | 257 | ||
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c index 8c720d44602a..cccc0a0a9c72 100644 --- a/arch/arm/mach-imx/mach-pca100.c +++ b/arch/arm/mach-imx/mach-pca100.c | |||
| @@ -29,7 +29,6 @@ | |||
| 29 | #include <linux/gpio.h> | 29 | #include <linux/gpio.h> |
| 30 | #include <linux/usb/otg.h> | 30 | #include <linux/usb/otg.h> |
| 31 | #include <linux/usb/ulpi.h> | 31 | #include <linux/usb/ulpi.h> |
| 32 | #include <linux/fsl_devices.h> | ||
| 33 | 32 | ||
| 34 | #include <asm/mach/arch.h> | 33 | #include <asm/mach/arch.h> |
| 35 | #include <asm/mach-types.h> | 34 | #include <asm/mach-types.h> |
| @@ -40,13 +39,9 @@ | |||
| 40 | #include <mach/audmux.h> | 39 | #include <mach/audmux.h> |
| 41 | #include <mach/mxc_nand.h> | 40 | #include <mach/mxc_nand.h> |
| 42 | #include <mach/irqs.h> | 41 | #include <mach/irqs.h> |
| 43 | #include <mach/mmc.h> | ||
| 44 | #include <mach/mxc_ehci.h> | ||
| 45 | #include <mach/ulpi.h> | 42 | #include <mach/ulpi.h> |
| 46 | #include <mach/imxfb.h> | ||
| 47 | 43 | ||
| 48 | #include "devices-imx27.h" | 44 | #include "devices-imx27.h" |
| 49 | #include "devices.h" | ||
| 50 | 45 | ||
| 51 | #define OTG_PHY_CS_GPIO (GPIO_PORTB + 23) | 46 | #define OTG_PHY_CS_GPIO (GPIO_PORTB + 23) |
| 52 | #define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24) | 47 | #define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24) |
| @@ -171,11 +166,6 @@ pca100_nand_board_info __initconst = { | |||
| 171 | .hw_ecc = 1, | 166 | .hw_ecc = 1, |
| 172 | }; | 167 | }; |
| 173 | 168 | ||
| 174 | static struct platform_device *platform_devices[] __initdata = { | ||
| 175 | &mxc_w1_master_device, | ||
| 176 | &mxc_wdt, | ||
| 177 | }; | ||
| 178 | |||
| 179 | static const struct imxi2c_platform_data pca100_i2c1_data __initconst = { | 169 | static const struct imxi2c_platform_data pca100_i2c1_data __initconst = { |
| 180 | .bitrate = 100000, | 170 | .bitrate = 100000, |
| 181 | }; | 171 | }; |
| @@ -274,7 +264,7 @@ static void pca100_sdhc2_exit(struct device *dev, void *data) | |||
| 274 | free_irq(IRQ_GPIOC(29), data); | 264 | free_irq(IRQ_GPIOC(29), data); |
| 275 | } | 265 | } |
| 276 | 266 | ||
| 277 | static struct imxmmc_platform_data sdhc_pdata = { | 267 | static const struct imxmmc_platform_data sdhc_pdata __initconst = { |
| 278 | .init = pca100_sdhc2_init, | 268 | .init = pca100_sdhc2_init, |
| 279 | .exit = pca100_sdhc2_exit, | 269 | .exit = pca100_sdhc2_exit, |
| 280 | }; | 270 | }; |
| @@ -286,7 +276,7 @@ static int otg_phy_init(struct platform_device *pdev) | |||
| 286 | return 0; | 276 | return 0; |
| 287 | } | 277 | } |
| 288 | 278 | ||
| 289 | static struct mxc_usbh_platform_data otg_pdata = { | 279 | static struct mxc_usbh_platform_data otg_pdata __initdata = { |
| 290 | .init = otg_phy_init, | 280 | .init = otg_phy_init, |
| 291 | .portsc = MXC_EHCI_MODE_ULPI, | 281 | .portsc = MXC_EHCI_MODE_ULPI, |
| 292 | .flags = MXC_EHCI_INTERFACE_DIFF_UNI, | 282 | .flags = MXC_EHCI_INTERFACE_DIFF_UNI, |
| @@ -298,14 +288,14 @@ static int usbh2_phy_init(struct platform_device *pdev) | |||
| 298 | return 0; | 288 | return 0; |
| 299 | } | 289 | } |
| 300 | 290 | ||
| 301 | static struct mxc_usbh_platform_data usbh2_pdata = { | 291 | static struct mxc_usbh_platform_data usbh2_pdata __initdata = { |
| 302 | .init = usbh2_phy_init, | 292 | .init = usbh2_phy_init, |
| 303 | .portsc = MXC_EHCI_MODE_ULPI, | 293 | .portsc = MXC_EHCI_MODE_ULPI, |
| 304 | .flags = MXC_EHCI_INTERFACE_DIFF_UNI, | 294 | .flags = MXC_EHCI_INTERFACE_DIFF_UNI, |
| 305 | }; | 295 | }; |
| 306 | #endif | 296 | #endif |
| 307 | 297 | ||
| 308 | static struct fsl_usb2_platform_data otg_device_pdata = { | 298 | static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { |
| 309 | .operating_mode = FSL_USB2_DR_DEVICE, | 299 | .operating_mode = FSL_USB2_DR_DEVICE, |
| 310 | .phy_mode = FSL_USB2_PHY_ULPI, | 300 | .phy_mode = FSL_USB2_PHY_ULPI, |
| 311 | }; | 301 | }; |
| @@ -355,7 +345,7 @@ static struct imx_fb_videomode pca100_fb_modes[] = { | |||
| 355 | }, | 345 | }, |
| 356 | }; | 346 | }; |
| 357 | 347 | ||
| 358 | static struct imx_fb_platform_data pca100_fb_data = { | 348 | static const struct imx_fb_platform_data pca100_fb_data __initconst = { |
| 359 | .mode = pca100_fb_modes, | 349 | .mode = pca100_fb_modes, |
| 360 | .num_modes = ARRAY_SIZE(pca100_fb_modes), | 350 | .num_modes = ARRAY_SIZE(pca100_fb_modes), |
| 361 | 351 | ||
| @@ -389,7 +379,7 @@ static void __init pca100_init(void) | |||
| 389 | 379 | ||
| 390 | imx27_add_imx_uart0(&uart_pdata); | 380 | imx27_add_imx_uart0(&uart_pdata); |
| 391 | 381 | ||
| 392 | mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata); | 382 | imx27_add_mxc_mmc(1, &sdhc_pdata); |
| 393 | 383 | ||
| 394 | imx27_add_mxc_nand(&pca100_nand_board_info); | 384 | imx27_add_mxc_nand(&pca100_nand_board_info); |
| 395 | 385 | ||
| @@ -417,23 +407,24 @@ static void __init pca100_init(void) | |||
| 417 | otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, | 407 | otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, |
| 418 | ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); | 408 | ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); |
| 419 | 409 | ||
| 420 | mxc_register_device(&mxc_otg_host, &otg_pdata); | 410 | imx27_add_mxc_ehci_otg(&otg_pdata); |
| 421 | } | 411 | } |
| 422 | 412 | ||
| 423 | usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, | 413 | usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, |
| 424 | ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); | 414 | ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); |
| 425 | 415 | ||
| 426 | mxc_register_device(&mxc_usbh2, &usbh2_pdata); | 416 | imx27_add_mxc_ehci_hs(2, &usbh2_pdata); |
| 427 | #endif | 417 | #endif |
| 428 | if (!otg_mode_host) { | 418 | if (!otg_mode_host) { |
| 429 | gpio_set_value(OTG_PHY_CS_GPIO, 0); | 419 | gpio_set_value(OTG_PHY_CS_GPIO, 0); |
| 430 | mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); | 420 | imx27_add_fsl_usb2_udc(&otg_device_pdata); |
| 431 | } | 421 | } |
| 432 | 422 | ||
| 433 | mxc_register_device(&mxc_fb_device, &pca100_fb_data); | 423 | imx27_add_imx_fb(&pca100_fb_data); |
| 434 | 424 | ||
| 435 | imx27_add_fec(NULL); | 425 | imx27_add_fec(NULL); |
| 436 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); | 426 | imx27_add_imx2_wdt(NULL); |
| 427 | imx27_add_mxc_w1(NULL); | ||
| 437 | } | 428 | } |
| 438 | 429 | ||
| 439 | static void __init pca100_timer_init(void) | 430 | static void __init pca100_timer_init(void) |
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c index 49a97ce07426..f667a262dfc1 100644 --- a/arch/arm/mach-imx/mach-pcm038.c +++ b/arch/arm/mach-imx/mach-pcm038.c | |||
| @@ -37,11 +37,9 @@ | |||
| 37 | #include <mach/hardware.h> | 37 | #include <mach/hardware.h> |
| 38 | #include <mach/iomux-mx27.h> | 38 | #include <mach/iomux-mx27.h> |
| 39 | #include <mach/mxc_nand.h> | 39 | #include <mach/mxc_nand.h> |
| 40 | #include <mach/mxc_ehci.h> | ||
| 41 | #include <mach/ulpi.h> | 40 | #include <mach/ulpi.h> |
| 42 | 41 | ||
| 43 | #include "devices-imx27.h" | 42 | #include "devices-imx27.h" |
| 44 | #include "devices.h" | ||
| 45 | 43 | ||
| 46 | static const int pcm038_pins[] __initconst = { | 44 | static const int pcm038_pins[] __initconst = { |
| 47 | /* UART1 */ | 45 | /* UART1 */ |
| @@ -172,9 +170,7 @@ pcm038_nand_board_info __initconst = { | |||
| 172 | 170 | ||
| 173 | static struct platform_device *platform_devices[] __initdata = { | 171 | static struct platform_device *platform_devices[] __initdata = { |
| 174 | &pcm038_nor_mtd_device, | 172 | &pcm038_nor_mtd_device, |
| 175 | &mxc_w1_master_device, | ||
| 176 | &pcm038_sram_mtd_device, | 173 | &pcm038_sram_mtd_device, |
| 177 | &mxc_wdt, | ||
| 178 | }; | 174 | }; |
| 179 | 175 | ||
| 180 | /* On pcm038 there's a sram attached to CS1, we enable the chipselect here and | 176 | /* On pcm038 there's a sram attached to CS1, we enable the chipselect here and |
| @@ -214,7 +210,7 @@ static const struct spi_imx_master pcm038_spi0_data __initconst = { | |||
| 214 | 210 | ||
| 215 | static struct regulator_consumer_supply sdhc1_consumers[] = { | 211 | static struct regulator_consumer_supply sdhc1_consumers[] = { |
| 216 | { | 212 | { |
| 217 | .dev = &mxc_sdhc_device1.dev, | 213 | .dev_name = "mxc-mmc.1", |
| 218 | .supply = "sdhc_vcc", | 214 | .supply = "sdhc_vcc", |
| 219 | }, | 215 | }, |
| 220 | }; | 216 | }; |
| @@ -285,7 +281,7 @@ static struct spi_board_info pcm038_spi_board_info[] __initdata = { | |||
| 285 | } | 281 | } |
| 286 | }; | 282 | }; |
| 287 | 283 | ||
| 288 | static struct mxc_usbh_platform_data usbh2_pdata = { | 284 | static const struct mxc_usbh_platform_data usbh2_pdata __initconst = { |
| 289 | .portsc = MXC_EHCI_MODE_ULPI, | 285 | .portsc = MXC_EHCI_MODE_ULPI, |
| 290 | .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI, | 286 | .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI, |
| 291 | }; | 287 | }; |
| @@ -322,10 +318,12 @@ static void __init pcm038_init(void) | |||
| 322 | spi_register_board_info(pcm038_spi_board_info, | 318 | spi_register_board_info(pcm038_spi_board_info, |
| 323 | ARRAY_SIZE(pcm038_spi_board_info)); | 319 | ARRAY_SIZE(pcm038_spi_board_info)); |
| 324 | 320 | ||
| 325 | mxc_register_device(&mxc_usbh2, &usbh2_pdata); | 321 | imx27_add_mxc_ehci_hs(2, &usbh2_pdata); |
| 326 | 322 | ||
| 327 | imx27_add_fec(NULL); | 323 | imx27_add_fec(NULL); |
| 328 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); | 324 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); |
| 325 | imx27_add_imx2_wdt(NULL); | ||
| 326 | imx27_add_mxc_w1(NULL); | ||
| 329 | 327 | ||
| 330 | #ifdef CONFIG_MACH_PCM970_BASEBOARD | 328 | #ifdef CONFIG_MACH_PCM970_BASEBOARD |
| 331 | pcm970_baseboard_init(); | 329 | pcm970_baseboard_init(); |
diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c index 1fbdd3faa7ab..eae878f306c6 100644 --- a/arch/arm/mach-imx/mach-scb9328.c +++ b/arch/arm/mach-imx/mach-scb9328.c | |||
| @@ -25,7 +25,6 @@ | |||
| 25 | #include <mach/iomux-mx1.h> | 25 | #include <mach/iomux-mx1.h> |
| 26 | 26 | ||
| 27 | #include "devices-imx1.h" | 27 | #include "devices-imx1.h" |
| 28 | #include "devices.h" | ||
| 29 | 28 | ||
| 30 | /* | 29 | /* |
| 31 | * This scb9328 has a 32MiB flash | 30 | * This scb9328 has a 32MiB flash |
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c index 9be92b96dc89..729ae0915af8 100644 --- a/arch/arm/mach-imx/mm-imx1.c +++ b/arch/arm/mach-imx/mm-imx1.c | |||
| @@ -25,12 +25,7 @@ | |||
| 25 | #include <mach/hardware.h> | 25 | #include <mach/hardware.h> |
| 26 | 26 | ||
| 27 | static struct map_desc imx_io_desc[] __initdata = { | 27 | static struct map_desc imx_io_desc[] __initdata = { |
| 28 | { | 28 | imx_map_entry(MX1, IO, MT_DEVICE), |
| 29 | .virtual = MX1_IO_BASE_ADDR_VIRT, | ||
| 30 | .pfn = __phys_to_pfn(MX1_IO_BASE_ADDR), | ||
| 31 | .length = MX1_IO_SIZE, | ||
| 32 | .type = MT_DEVICE | ||
| 33 | } | ||
| 34 | }; | 29 | }; |
| 35 | 30 | ||
| 36 | void __init mx1_map_io(void) | 31 | void __init mx1_map_io(void) |
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c index 12faeeaa0a97..e728af81d1b1 100644 --- a/arch/arm/mach-imx/mm-imx21.c +++ b/arch/arm/mach-imx/mm-imx21.c | |||
| @@ -35,33 +35,18 @@ static struct map_desc imx21_io_desc[] __initdata = { | |||
| 35 | * - ROM Patch | 35 | * - ROM Patch |
| 36 | * - and some reserved space | 36 | * - and some reserved space |
| 37 | */ | 37 | */ |
| 38 | { | 38 | imx_map_entry(MX21, AIPI, MT_DEVICE), |
| 39 | .virtual = MX21_AIPI_BASE_ADDR_VIRT, | ||
| 40 | .pfn = __phys_to_pfn(MX21_AIPI_BASE_ADDR), | ||
| 41 | .length = MX21_AIPI_SIZE, | ||
| 42 | .type = MT_DEVICE | ||
| 43 | }, | ||
| 44 | /* | 39 | /* |
| 45 | * this fixed mapping covers: | 40 | * this fixed mapping covers: |
| 46 | * - CSI | 41 | * - CSI |
| 47 | * - ATA | 42 | * - ATA |
| 48 | */ | 43 | */ |
| 49 | { | 44 | imx_map_entry(MX21, SAHB1, MT_DEVICE), |
| 50 | .virtual = MX21_SAHB1_BASE_ADDR_VIRT, | ||
| 51 | .pfn = __phys_to_pfn(MX21_SAHB1_BASE_ADDR), | ||
| 52 | .length = MX21_SAHB1_SIZE, | ||
| 53 | .type = MT_DEVICE | ||
| 54 | }, | ||
| 55 | /* | 45 | /* |
| 56 | * this fixed mapping covers: | 46 | * this fixed mapping covers: |
| 57 | * - EMI | 47 | * - EMI |
| 58 | */ | 48 | */ |
| 59 | { | 49 | imx_map_entry(MX21, X_MEMC, MT_DEVICE), |
| 60 | .virtual = MX21_X_MEMC_BASE_ADDR_VIRT, | ||
| 61 | .pfn = __phys_to_pfn(MX21_X_MEMC_BASE_ADDR), | ||
| 62 | .length = MX21_X_MEMC_SIZE, | ||
| 63 | .type = MT_DEVICE | ||
| 64 | }, | ||
| 65 | }; | 50 | }; |
| 66 | 51 | ||
| 67 | /* | 52 | /* |
diff --git a/arch/arm/mach-mx25/mm.c b/arch/arm/mach-imx/mm-imx25.c index bb677111fb0f..2edec6ce8fe7 100644 --- a/arch/arm/mach-mx25/mm.c +++ b/arch/arm/mach-imx/mm-imx25.c | |||
| @@ -30,25 +30,12 @@ | |||
| 30 | 30 | ||
| 31 | /* | 31 | /* |
| 32 | * This table defines static virtual address mappings for I/O regions. | 32 | * This table defines static virtual address mappings for I/O regions. |
| 33 | * These are the mappings common across all MX3 boards. | 33 | * These are the mappings common across all MX25 boards. |
| 34 | */ | 34 | */ |
| 35 | static struct map_desc mxc_io_desc[] __initdata = { | 35 | static struct map_desc mx25_io_desc[] __initdata = { |
| 36 | { | 36 | imx_map_entry(MX25, AVIC, MT_DEVICE_NONSHARED), |
| 37 | .virtual = MX25_AVIC_BASE_ADDR_VIRT, | 37 | imx_map_entry(MX25, AIPS1, MT_DEVICE_NONSHARED), |
| 38 | .pfn = __phys_to_pfn(MX25_AVIC_BASE_ADDR), | 38 | imx_map_entry(MX25, AIPS2, MT_DEVICE_NONSHARED), |
| 39 | .length = MX25_AVIC_SIZE, | ||
| 40 | .type = MT_DEVICE_NONSHARED | ||
| 41 | }, { | ||
| 42 | .virtual = MX25_AIPS1_BASE_ADDR_VIRT, | ||
| 43 | .pfn = __phys_to_pfn(MX25_AIPS1_BASE_ADDR), | ||
| 44 | .length = MX25_AIPS1_SIZE, | ||
| 45 | .type = MT_DEVICE_NONSHARED | ||
| 46 | }, { | ||
| 47 | .virtual = MX25_AIPS2_BASE_ADDR_VIRT, | ||
| 48 | .pfn = __phys_to_pfn(MX25_AIPS2_BASE_ADDR), | ||
| 49 | .length = MX25_AIPS2_SIZE, | ||
| 50 | .type = MT_DEVICE_NONSHARED | ||
| 51 | }, | ||
| 52 | }; | 39 | }; |
| 53 | 40 | ||
| 54 | /* | 41 | /* |
| @@ -62,14 +49,14 @@ void __init mx25_map_io(void) | |||
| 62 | mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR)); | 49 | mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR)); |
| 63 | mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR)); | 50 | mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR)); |
| 64 | 51 | ||
| 65 | iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); | 52 | iotable_init(mx25_io_desc, ARRAY_SIZE(mx25_io_desc)); |
| 66 | } | 53 | } |
| 67 | 54 | ||
| 68 | int imx25_register_gpios(void); | 55 | int imx25_register_gpios(void); |
| 69 | 56 | ||
| 70 | void __init mx25_init_irq(void) | 57 | void __init mx25_init_irq(void) |
| 71 | { | 58 | { |
| 72 | mxc_init_irq((void __iomem *)MX25_AVIC_BASE_ADDR_VIRT); | 59 | mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR)); |
| 73 | imx25_register_gpios(); | 60 | imx25_register_gpios(); |
| 74 | } | 61 | } |
| 75 | 62 | ||
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c index a24622957ff2..374e48b7a412 100644 --- a/arch/arm/mach-imx/mm-imx27.c +++ b/arch/arm/mach-imx/mm-imx27.c | |||
| @@ -35,33 +35,18 @@ static struct map_desc imx27_io_desc[] __initdata = { | |||
| 35 | * - ROM Patch | 35 | * - ROM Patch |
| 36 | * - and some reserved space | 36 | * - and some reserved space |
| 37 | */ | 37 | */ |
| 38 | { | 38 | imx_map_entry(MX27, AIPI, MT_DEVICE), |
| 39 | .virtual = MX27_AIPI_BASE_ADDR_VIRT, | ||
| 40 | .pfn = __phys_to_pfn(MX27_AIPI_BASE_ADDR), | ||
| 41 | .length = MX27_AIPI_SIZE, | ||
| 42 | .type = MT_DEVICE | ||
| 43 | }, | ||
| 44 | /* | 39 | /* |
| 45 | * this fixed mapping covers: | 40 | * this fixed mapping covers: |
| 46 | * - CSI | 41 | * - CSI |
| 47 | * - ATA | 42 | * - ATA |
| 48 | */ | 43 | */ |
| 49 | { | 44 | imx_map_entry(MX27, SAHB1, MT_DEVICE), |
| 50 | .virtual = MX27_SAHB1_BASE_ADDR_VIRT, | ||
| 51 | .pfn = __phys_to_pfn(MX27_SAHB1_BASE_ADDR), | ||
| 52 | .length = MX27_SAHB1_SIZE, | ||
| 53 | .type = MT_DEVICE | ||
| 54 | }, | ||
| 55 | /* | 45 | /* |
| 56 | * this fixed mapping covers: | 46 | * this fixed mapping covers: |
| 57 | * - EMI | 47 | * - EMI |
| 58 | */ | 48 | */ |
| 59 | { | 49 | imx_map_entry(MX27, X_MEMC, MT_DEVICE), |
| 60 | .virtual = MX27_X_MEMC_BASE_ADDR_VIRT, | ||
| 61 | .pfn = __phys_to_pfn(MX27_X_MEMC_BASE_ADDR), | ||
| 62 | .length = MX27_X_MEMC_SIZE, | ||
| 63 | .type = MT_DEVICE | ||
| 64 | }, | ||
| 65 | }; | 50 | }; |
| 66 | 51 | ||
| 67 | /* | 52 | /* |
diff --git a/arch/arm/mach-imx/pcm970-baseboard.c b/arch/arm/mach-imx/pcm970-baseboard.c index 9110d9cca7a2..99afbc3f43a3 100644 --- a/arch/arm/mach-imx/pcm970-baseboard.c +++ b/arch/arm/mach-imx/pcm970-baseboard.c | |||
| @@ -25,11 +25,9 @@ | |||
| 25 | 25 | ||
| 26 | #include <mach/common.h> | 26 | #include <mach/common.h> |
| 27 | #include <mach/iomux-mx27.h> | 27 | #include <mach/iomux-mx27.h> |
| 28 | #include <mach/imxfb.h> | ||
| 29 | #include <mach/hardware.h> | 28 | #include <mach/hardware.h> |
| 30 | #include <mach/mmc.h> | ||
| 31 | 29 | ||
| 32 | #include "devices.h" | 30 | #include "devices-imx27.h" |
| 33 | 31 | ||
| 34 | static const int pcm970_pins[] __initconst = { | 32 | static const int pcm970_pins[] __initconst = { |
| 35 | /* SDHC */ | 33 | /* SDHC */ |
| @@ -119,7 +117,7 @@ static void pcm970_sdhc2_exit(struct device *dev, void *data) | |||
| 119 | gpio_free(GPIO_PORTC + 28); | 117 | gpio_free(GPIO_PORTC + 28); |
| 120 | } | 118 | } |
| 121 | 119 | ||
| 122 | static struct imxmmc_platform_data sdhc_pdata = { | 120 | static const struct imxmmc_platform_data sdhc_pdata __initconst = { |
| 123 | .get_ro = pcm970_sdhc2_get_ro, | 121 | .get_ro = pcm970_sdhc2_get_ro, |
| 124 | .init = pcm970_sdhc2_init, | 122 | .init = pcm970_sdhc2_init, |
| 125 | .exit = pcm970_sdhc2_exit, | 123 | .exit = pcm970_sdhc2_exit, |
| @@ -179,7 +177,7 @@ static struct imx_fb_videomode pcm970_modes[] = { | |||
| 179 | }, | 177 | }, |
| 180 | }; | 178 | }; |
| 181 | 179 | ||
| 182 | static struct imx_fb_platform_data pcm038_fb_data = { | 180 | static const struct imx_fb_platform_data pcm038_fb_data __initconst = { |
| 183 | .mode = pcm970_modes, | 181 | .mode = pcm970_modes, |
| 184 | .num_modes = ARRAY_SIZE(pcm970_modes), | 182 | .num_modes = ARRAY_SIZE(pcm970_modes), |
| 185 | 183 | ||
| @@ -226,8 +224,8 @@ void __init pcm970_baseboard_init(void) | |||
| 226 | mxc_gpio_setup_multiple_pins(pcm970_pins, ARRAY_SIZE(pcm970_pins), | 224 | mxc_gpio_setup_multiple_pins(pcm970_pins, ARRAY_SIZE(pcm970_pins), |
| 227 | "PCM970"); | 225 | "PCM970"); |
| 228 | 226 | ||
| 229 | mxc_register_device(&mxc_fb_device, &pcm038_fb_data); | 227 | imx27_add_imx_fb(&pcm038_fb_data); |
| 230 | mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_IN); | 228 | mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_IN); |
| 231 | mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata); | 229 | imx27_add_mxc_mmc(1, &sdhc_pdata); |
| 232 | platform_device_register(&pcm970_sja1000); | 230 | platform_device_register(&pcm970_sja1000); |
| 233 | } | 231 | } |
diff --git a/arch/arm/mach-imx/pm-imx27.c b/arch/arm/mach-imx/pm-imx27.c index afc17ce0bb54..6bf81ceea137 100644 --- a/arch/arm/mach-imx/pm-imx27.c +++ b/arch/arm/mach-imx/pm-imx27.c | |||
| @@ -39,6 +39,9 @@ static struct platform_suspend_ops mx27_suspend_ops = { | |||
| 39 | 39 | ||
| 40 | static int __init mx27_pm_init(void) | 40 | static int __init mx27_pm_init(void) |
| 41 | { | 41 | { |
| 42 | if (!cpu_is_mx27()) | ||
| 43 | return 0; | ||
| 44 | |||
| 42 | suspend_set_ops(&mx27_suspend_ops); | 45 | suspend_set_ops(&mx27_suspend_ops); |
| 43 | return 0; | 46 | return 0; |
| 44 | } | 47 | } |
diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig index 27db275b367c..769b0f10c834 100644 --- a/arch/arm/mach-integrator/Kconfig +++ b/arch/arm/mach-integrator/Kconfig | |||
| @@ -4,6 +4,7 @@ menu "Integrator Options" | |||
| 4 | 4 | ||
| 5 | config ARCH_INTEGRATOR_AP | 5 | config ARCH_INTEGRATOR_AP |
| 6 | bool "Support Integrator/AP and Integrator/PP2 platforms" | 6 | bool "Support Integrator/AP and Integrator/PP2 platforms" |
| 7 | select MIGHT_HAVE_PCI | ||
| 7 | help | 8 | help |
| 8 | Include support for the ARM(R) Integrator/AP and | 9 | Include support for the ARM(R) Integrator/AP and |
| 9 | Integrator/PP2 platforms. | 10 | Integrator/PP2 platforms. |
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c index 8f4fb6d638f7..b8e884b450da 100644 --- a/arch/arm/mach-integrator/core.c +++ b/arch/arm/mach-integrator/core.c | |||
| @@ -21,9 +21,8 @@ | |||
| 21 | #include <linux/amba/bus.h> | 21 | #include <linux/amba/bus.h> |
| 22 | #include <linux/amba/serial.h> | 22 | #include <linux/amba/serial.h> |
| 23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
| 24 | #include <linux/clkdev.h> | ||
| 24 | 25 | ||
| 25 | #include <asm/clkdev.h> | ||
| 26 | #include <mach/clkdev.h> | ||
| 27 | #include <mach/hardware.h> | 26 | #include <mach/hardware.h> |
| 28 | #include <mach/platform.h> | 27 | #include <mach/platform.h> |
| 29 | #include <asm/irq.h> | 28 | #include <asm/irq.h> |
diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c index fd684bf205e5..5db574f8ae3f 100644 --- a/arch/arm/mach-integrator/impd1.c +++ b/arch/arm/mach-integrator/impd1.c | |||
| @@ -22,9 +22,8 @@ | |||
| 22 | #include <linux/amba/clcd.h> | 22 | #include <linux/amba/clcd.h> |
| 23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
| 24 | #include <linux/slab.h> | 24 | #include <linux/slab.h> |
| 25 | #include <linux/clkdev.h> | ||
| 25 | 26 | ||
| 26 | #include <asm/clkdev.h> | ||
| 27 | #include <mach/clkdev.h> | ||
| 28 | #include <asm/hardware/icst.h> | 27 | #include <asm/hardware/icst.h> |
| 29 | #include <mach/lm.h> | 28 | #include <mach/lm.h> |
| 30 | #include <mach/impd1.h> | 29 | #include <mach/impd1.h> |
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index 548208f11179..2774df8021dc 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c | |||
| @@ -372,7 +372,6 @@ static struct clocksource clocksource_timersp = { | |||
| 372 | .rating = 200, | 372 | .rating = 200, |
| 373 | .read = timersp_read, | 373 | .read = timersp_read, |
| 374 | .mask = CLOCKSOURCE_MASK(16), | 374 | .mask = CLOCKSOURCE_MASK(16), |
| 375 | .shift = 16, | ||
| 376 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 375 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 377 | }; | 376 | }; |
| 378 | 377 | ||
| @@ -390,8 +389,7 @@ static void integrator_clocksource_init(u32 khz) | |||
| 390 | writel(ctrl, base + TIMER_CTRL); | 389 | writel(ctrl, base + TIMER_CTRL); |
| 391 | writel(0xffff, base + TIMER_LOAD); | 390 | writel(0xffff, base + TIMER_LOAD); |
| 392 | 391 | ||
| 393 | cs->mult = clocksource_khz2mult(khz, cs->shift); | 392 | clocksource_register_khz(cs, khz); |
| 394 | clocksource_register(cs); | ||
| 395 | } | 393 | } |
| 396 | 394 | ||
| 397 | static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE; | 395 | static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE; |
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c index 6258c90d020c..85e48a5f77b9 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-integrator/integrator_cp.c | |||
| @@ -21,9 +21,8 @@ | |||
| 21 | #include <linux/amba/mmci.h> | 21 | #include <linux/amba/mmci.h> |
| 22 | #include <linux/io.h> | 22 | #include <linux/io.h> |
| 23 | #include <linux/gfp.h> | 23 | #include <linux/gfp.h> |
| 24 | #include <linux/clkdev.h> | ||
| 24 | 25 | ||
| 25 | #include <asm/clkdev.h> | ||
| 26 | #include <mach/clkdev.h> | ||
| 27 | #include <mach/hardware.h> | 26 | #include <mach/hardware.h> |
| 28 | #include <mach/platform.h> | 27 | #include <mach/platform.h> |
| 29 | #include <asm/irq.h> | 28 | #include <asm/irq.h> |
| @@ -41,7 +40,7 @@ | |||
| 41 | #include <asm/mach/map.h> | 40 | #include <asm/mach/map.h> |
| 42 | #include <asm/mach/time.h> | 41 | #include <asm/mach/time.h> |
| 43 | 42 | ||
| 44 | #include <plat/timer-sp.h> | 43 | #include <asm/hardware/timer-sp.h> |
| 45 | 44 | ||
| 46 | #include "common.h" | 45 | #include "common.h" |
| 47 | 46 | ||
diff --git a/arch/arm/mach-iop13xx/include/mach/io.h b/arch/arm/mach-iop13xx/include/mach/io.h index a6e0f9e6ddcf..dffb234bb967 100644 --- a/arch/arm/mach-iop13xx/include/mach/io.h +++ b/arch/arm/mach-iop13xx/include/mach/io.h | |||
| @@ -35,7 +35,7 @@ extern u32 iop13xx_atux_mem_base; | |||
| 35 | extern size_t iop13xx_atue_mem_size; | 35 | extern size_t iop13xx_atue_mem_size; |
| 36 | extern size_t iop13xx_atux_mem_size; | 36 | extern size_t iop13xx_atux_mem_size; |
| 37 | 37 | ||
| 38 | #define __arch_ioremap(a, s, f) __iop13xx_ioremap(a, s, f) | 38 | #define __arch_ioremap __iop13xx_ioremap |
| 39 | #define __arch_iounmap(a) __iop13xx_iounmap(a) | 39 | #define __arch_iounmap __iop13xx_iounmap |
| 40 | 40 | ||
| 41 | #endif | 41 | #endif |
diff --git a/arch/arm/mach-iop13xx/include/mach/memory.h b/arch/arm/mach-iop13xx/include/mach/memory.h index 7415e4338651..3ad455318868 100644 --- a/arch/arm/mach-iop13xx/include/mach/memory.h +++ b/arch/arm/mach-iop13xx/include/mach/memory.h | |||
| @@ -58,13 +58,13 @@ static inline unsigned long __lbus_to_virt(dma_addr_t x) | |||
| 58 | __dma; \ | 58 | __dma; \ |
| 59 | }) | 59 | }) |
| 60 | 60 | ||
| 61 | #define __arch_page_to_dma(dev, page) \ | 61 | #define __arch_pfn_to_dma(dev, pfn) \ |
| 62 | ({ \ | 62 | ({ \ |
| 63 | /* __is_lbus_virt() can never be true for RAM pages */ \ | 63 | /* __is_lbus_virt() can never be true for RAM pages */ \ |
| 64 | (dma_addr_t)page_to_phys(page); \ | 64 | (dma_addr_t)__pfn_to_phys(pfn); \ |
| 65 | }) | 65 | }) |
| 66 | 66 | ||
| 67 | #define __arch_dma_to_page(dev, addr) phys_to_page(addr) | 67 | #define __arch_dma_to_pfn(dev, addr) __phys_to_pfn(addr) |
| 68 | 68 | ||
| 69 | #endif /* CONFIG_ARCH_IOP13XX */ | 69 | #endif /* CONFIG_ARCH_IOP13XX */ |
| 70 | #endif /* !ASSEMBLY */ | 70 | #endif /* !ASSEMBLY */ |
diff --git a/arch/arm/mach-iop32x/include/mach/io.h b/arch/arm/mach-iop32x/include/mach/io.h index 339e5854728b..059c783ce0b2 100644 --- a/arch/arm/mach-iop32x/include/mach/io.h +++ b/arch/arm/mach-iop32x/include/mach/io.h | |||
| @@ -21,7 +21,7 @@ extern void __iop3xx_iounmap(void __iomem *addr); | |||
| 21 | #define __io(p) ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p)) | 21 | #define __io(p) ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p)) |
| 22 | #define __mem_pci(a) (a) | 22 | #define __mem_pci(a) (a) |
| 23 | 23 | ||
| 24 | #define __arch_ioremap(a, s, f) __iop3xx_ioremap(a, s, f) | 24 | #define __arch_ioremap __iop3xx_ioremap |
| 25 | #define __arch_iounmap(a) __iop3xx_iounmap(a) | 25 | #define __arch_iounmap __iop3xx_iounmap |
| 26 | 26 | ||
| 27 | #endif | 27 | #endif |
diff --git a/arch/arm/mach-iop33x/include/mach/io.h b/arch/arm/mach-iop33x/include/mach/io.h index e99a7ed6d050..39e893e97c21 100644 --- a/arch/arm/mach-iop33x/include/mach/io.h +++ b/arch/arm/mach-iop33x/include/mach/io.h | |||
| @@ -21,7 +21,7 @@ extern void __iop3xx_iounmap(void __iomem *addr); | |||
| 21 | #define __io(p) ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p)) | 21 | #define __io(p) ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p)) |
| 22 | #define __mem_pci(a) (a) | 22 | #define __mem_pci(a) (a) |
| 23 | 23 | ||
| 24 | #define __arch_ioremap(a, s, f) __iop3xx_ioremap(a, s, f) | 24 | #define __arch_ioremap __iop3xx_ioremap |
| 25 | #define __arch_iounmap(a) __iop3xx_iounmap(a) | 25 | #define __arch_iounmap __iop3xx_iounmap |
| 26 | 26 | ||
| 27 | #endif | 27 | #endif |
diff --git a/arch/arm/mach-ixp23xx/include/mach/io.h b/arch/arm/mach-ixp23xx/include/mach/io.h index fd9ef8e519f7..a1749d0fd896 100644 --- a/arch/arm/mach-ixp23xx/include/mach/io.h +++ b/arch/arm/mach-ixp23xx/include/mach/io.h | |||
| @@ -45,8 +45,8 @@ ixp23xx_iounmap(void __iomem *addr) | |||
| 45 | __iounmap(addr); | 45 | __iounmap(addr); |
| 46 | } | 46 | } |
| 47 | 47 | ||
| 48 | #define __arch_ioremap(a,s,f) ixp23xx_ioremap(a,s,f) | 48 | #define __arch_ioremap ixp23xx_ioremap |
| 49 | #define __arch_iounmap(a) ixp23xx_iounmap(a) | 49 | #define __arch_iounmap ixp23xx_iounmap |
| 50 | 50 | ||
| 51 | 51 | ||
| 52 | #endif | 52 | #endif |
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index 0bce09799d18..4dbfcbb9163c 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c | |||
| @@ -35,6 +35,7 @@ | |||
| 35 | #include <asm/pgtable.h> | 35 | #include <asm/pgtable.h> |
| 36 | #include <asm/page.h> | 36 | #include <asm/page.h> |
| 37 | #include <asm/irq.h> | 37 | #include <asm/irq.h> |
| 38 | #include <asm/sched_clock.h> | ||
| 38 | 39 | ||
| 39 | #include <asm/mach/map.h> | 40 | #include <asm/mach/map.h> |
| 40 | #include <asm/mach/irq.h> | 41 | #include <asm/mach/irq.h> |
| @@ -399,6 +400,23 @@ void __init ixp4xx_sys_init(void) | |||
| 399 | } | 400 | } |
| 400 | 401 | ||
| 401 | /* | 402 | /* |
| 403 | * sched_clock() | ||
| 404 | */ | ||
| 405 | static DEFINE_CLOCK_DATA(cd); | ||
| 406 | |||
| 407 | unsigned long long notrace sched_clock(void) | ||
| 408 | { | ||
| 409 | u32 cyc = *IXP4XX_OSTS; | ||
| 410 | return cyc_to_sched_clock(&cd, cyc, (u32)~0); | ||
| 411 | } | ||
| 412 | |||
| 413 | static void notrace ixp4xx_update_sched_clock(void) | ||
| 414 | { | ||
| 415 | u32 cyc = *IXP4XX_OSTS; | ||
| 416 | update_sched_clock(&cd, cyc, (u32)~0); | ||
| 417 | } | ||
| 418 | |||
| 419 | /* | ||
| 402 | * clocksource | 420 | * clocksource |
| 403 | */ | 421 | */ |
| 404 | static cycle_t ixp4xx_get_cycles(struct clocksource *cs) | 422 | static cycle_t ixp4xx_get_cycles(struct clocksource *cs) |
| @@ -411,7 +429,6 @@ static struct clocksource clocksource_ixp4xx = { | |||
| 411 | .rating = 200, | 429 | .rating = 200, |
| 412 | .read = ixp4xx_get_cycles, | 430 | .read = ixp4xx_get_cycles, |
| 413 | .mask = CLOCKSOURCE_MASK(32), | 431 | .mask = CLOCKSOURCE_MASK(32), |
| 414 | .shift = 20, | ||
| 415 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 432 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 416 | }; | 433 | }; |
| 417 | 434 | ||
| @@ -419,21 +436,9 @@ unsigned long ixp4xx_timer_freq = FREQ; | |||
| 419 | EXPORT_SYMBOL(ixp4xx_timer_freq); | 436 | EXPORT_SYMBOL(ixp4xx_timer_freq); |
| 420 | static void __init ixp4xx_clocksource_init(void) | 437 | static void __init ixp4xx_clocksource_init(void) |
| 421 | { | 438 | { |
| 422 | clocksource_ixp4xx.mult = | 439 | init_sched_clock(&cd, ixp4xx_update_sched_clock, 32, ixp4xx_timer_freq); |
| 423 | clocksource_hz2mult(ixp4xx_timer_freq, | ||
| 424 | clocksource_ixp4xx.shift); | ||
| 425 | clocksource_register(&clocksource_ixp4xx); | ||
| 426 | } | ||
| 427 | |||
| 428 | /* | ||
| 429 | * sched_clock() | ||
| 430 | */ | ||
| 431 | unsigned long long sched_clock(void) | ||
| 432 | { | ||
| 433 | cycle_t cyc = ixp4xx_get_cycles(NULL); | ||
| 434 | struct clocksource *cs = &clocksource_ixp4xx; | ||
| 435 | 440 | ||
| 436 | return clocksource_cyc2ns(cyc, cs->mult, cs->shift); | 441 | clocksource_register_hz(&clocksource_ixp4xx, ixp4xx_timer_freq); |
| 437 | } | 442 | } |
| 438 | 443 | ||
| 439 | /* | 444 | /* |
diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h index de274a1f19d7..57b5410c31f4 100644 --- a/arch/arm/mach-ixp4xx/include/mach/io.h +++ b/arch/arm/mach-ixp4xx/include/mach/io.h | |||
| @@ -74,8 +74,8 @@ static inline void __indirect_iounmap(void __iomem *addr) | |||
| 74 | __iounmap(addr); | 74 | __iounmap(addr); |
| 75 | } | 75 | } |
| 76 | 76 | ||
| 77 | #define __arch_ioremap(a, s, f) __indirect_ioremap(a, s, f) | 77 | #define __arch_ioremap __indirect_ioremap |
| 78 | #define __arch_iounmap(a) __indirect_iounmap(a) | 78 | #define __arch_iounmap __indirect_iounmap |
| 79 | 79 | ||
| 80 | #define writeb(v, p) __indirect_writeb(v, p) | 80 | #define writeb(v, p) __indirect_writeb(v, p) |
| 81 | #define writew(v, p) __indirect_writew(v, p) | 81 | #define writew(v, p) __indirect_writew(v, p) |
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 34106335c728..7fc603b46891 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig | |||
| @@ -45,18 +45,18 @@ config MACH_GURUPLUG | |||
| 45 | Marvell GuruPlug Reference Board. | 45 | Marvell GuruPlug Reference Board. |
| 46 | 46 | ||
| 47 | config MACH_TS219 | 47 | config MACH_TS219 |
| 48 | bool "QNAP TS-110, TS-119, TS-210, TS-219 and TS-219P Turbo NAS" | 48 | bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS" |
| 49 | help | 49 | help |
| 50 | Say 'Y' here if you want your kernel to support the | 50 | Say 'Y' here if you want your kernel to support the |
| 51 | QNAP TS-110, TS-119, TS-210, TS-219 and TS-219P Turbo NAS | 51 | QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and |
| 52 | devices. | 52 | TS-219P+ Turbo NAS devices. |
| 53 | 53 | ||
| 54 | config MACH_TS41X | 54 | config MACH_TS41X |
| 55 | bool "QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS" | 55 | bool "QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo NAS" |
| 56 | help | 56 | help |
| 57 | Say 'Y' here if you want your kernel to support the | 57 | Say 'Y' here if you want your kernel to support the |
| 58 | QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS | 58 | QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo |
| 59 | devices. | 59 | NAS devices. |
| 60 | 60 | ||
| 61 | config MACH_DOCKSTAR | 61 | config MACH_DOCKSTAR |
| 62 | bool "Seagate FreeAgent DockStar" | 62 | bool "Seagate FreeAgent DockStar" |
diff --git a/arch/arm/mach-kirkwood/include/mach/io.h b/arch/arm/mach-kirkwood/include/mach/io.h index 44e8be04f259..1aaddc364f2e 100644 --- a/arch/arm/mach-kirkwood/include/mach/io.h +++ b/arch/arm/mach-kirkwood/include/mach/io.h | |||
| @@ -42,8 +42,8 @@ __arch_iounmap(void __iomem *addr) | |||
| 42 | __iounmap(addr); | 42 | __iounmap(addr); |
| 43 | } | 43 | } |
| 44 | 44 | ||
| 45 | #define __arch_ioremap(p, s, m) __arch_ioremap(p, s, m) | 45 | #define __arch_ioremap __arch_ioremap |
| 46 | #define __arch_iounmap(a) __arch_iounmap(a) | 46 | #define __arch_iounmap __arch_iounmap |
| 47 | #define __io(a) __io(a) | 47 | #define __io(a) __io(a) |
| 48 | #define __mem_pci(a) (a) | 48 | #define __mem_pci(a) (a) |
| 49 | 49 | ||
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c index 6710bd7773b8..dc999c4c5806 100644 --- a/arch/arm/mach-kirkwood/ts219-setup.c +++ b/arch/arm/mach-kirkwood/ts219-setup.c | |||
| @@ -80,15 +80,19 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = { | |||
| 80 | MPP11_UART0_RXD, | 80 | MPP11_UART0_RXD, |
| 81 | MPP13_UART1_TXD, /* PIC controller */ | 81 | MPP13_UART1_TXD, /* PIC controller */ |
| 82 | MPP14_UART1_RXD, /* PIC controller */ | 82 | MPP14_UART1_RXD, /* PIC controller */ |
| 83 | MPP15_GPIO, /* USB Copy button */ | 83 | MPP15_GPIO, /* USB Copy button (on devices with 88F6281) */ |
| 84 | MPP16_GPIO, /* Reset button */ | 84 | MPP16_GPIO, /* Reset button (on devices with 88F6281) */ |
| 85 | MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */ | 85 | MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */ |
| 86 | MPP37_GPIO, /* Reset button (on devices with 88F6282) */ | ||
| 87 | MPP43_GPIO, /* USB Copy button (on devices with 88F6282) */ | ||
| 86 | MPP44_GPIO, /* Board ID: 0: TS-11x, 1: TS-21x */ | 88 | MPP44_GPIO, /* Board ID: 0: TS-11x, 1: TS-21x */ |
| 87 | 0 | 89 | 0 |
| 88 | }; | 90 | }; |
| 89 | 91 | ||
| 90 | static void __init qnap_ts219_init(void) | 92 | static void __init qnap_ts219_init(void) |
| 91 | { | 93 | { |
| 94 | u32 dev, rev; | ||
| 95 | |||
| 92 | /* | 96 | /* |
| 93 | * Basic setup. Needs to be called early. | 97 | * Basic setup. Needs to be called early. |
| 94 | */ | 98 | */ |
| @@ -100,6 +104,14 @@ static void __init qnap_ts219_init(void) | |||
| 100 | qnap_tsx1x_register_flash(); | 104 | qnap_tsx1x_register_flash(); |
| 101 | kirkwood_i2c_init(); | 105 | kirkwood_i2c_init(); |
| 102 | i2c_register_board_info(0, &qnap_ts219_i2c_rtc, 1); | 106 | i2c_register_board_info(0, &qnap_ts219_i2c_rtc, 1); |
| 107 | |||
| 108 | kirkwood_pcie_id(&dev, &rev); | ||
| 109 | if (dev == MV88F6282_DEV_ID) { | ||
| 110 | qnap_ts219_buttons[0].gpio = 43; /* USB Copy button */ | ||
| 111 | qnap_ts219_buttons[1].gpio = 37; /* Reset button */ | ||
| 112 | qnap_ts219_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0); | ||
| 113 | } | ||
| 114 | |||
| 103 | kirkwood_ge00_init(&qnap_ts219_ge00_data); | 115 | kirkwood_ge00_init(&qnap_ts219_ge00_data); |
| 104 | kirkwood_sata_init(&qnap_ts219_sata_data); | 116 | kirkwood_sata_init(&qnap_ts219_sata_data); |
| 105 | kirkwood_ehci_init(); | 117 | kirkwood_ehci_init(); |
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c index 3587a281d993..9a44029915e2 100644 --- a/arch/arm/mach-kirkwood/ts41x-setup.c +++ b/arch/arm/mach-kirkwood/ts41x-setup.c | |||
| @@ -119,6 +119,8 @@ static unsigned int qnap_ts41x_mpp_config[] __initdata = { | |||
| 119 | 119 | ||
| 120 | static void __init qnap_ts41x_init(void) | 120 | static void __init qnap_ts41x_init(void) |
| 121 | { | 121 | { |
| 122 | u32 dev, rev; | ||
| 123 | |||
| 122 | /* | 124 | /* |
| 123 | * Basic setup. Needs to be called early. | 125 | * Basic setup. Needs to be called early. |
| 124 | */ | 126 | */ |
| @@ -130,8 +132,15 @@ static void __init qnap_ts41x_init(void) | |||
| 130 | qnap_tsx1x_register_flash(); | 132 | qnap_tsx1x_register_flash(); |
| 131 | kirkwood_i2c_init(); | 133 | kirkwood_i2c_init(); |
| 132 | i2c_register_board_info(0, &qnap_ts41x_i2c_rtc, 1); | 134 | i2c_register_board_info(0, &qnap_ts41x_i2c_rtc, 1); |
| 135 | |||
| 136 | kirkwood_pcie_id(&dev, &rev); | ||
| 137 | if (dev == MV88F6282_DEV_ID) { | ||
| 138 | qnap_ts41x_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0); | ||
| 139 | qnap_ts41x_ge01_data.phy_addr = MV643XX_ETH_PHY_ADDR(1); | ||
| 140 | } | ||
| 133 | kirkwood_ge00_init(&qnap_ts41x_ge00_data); | 141 | kirkwood_ge00_init(&qnap_ts41x_ge00_data); |
| 134 | kirkwood_ge01_init(&qnap_ts41x_ge01_data); | 142 | kirkwood_ge01_init(&qnap_ts41x_ge01_data); |
| 143 | |||
| 135 | kirkwood_sata_init(&qnap_ts41x_sata_data); | 144 | kirkwood_sata_init(&qnap_ts41x_sata_data); |
| 136 | kirkwood_ehci_init(); | 145 | kirkwood_ehci_init(); |
| 137 | platform_device_register(&qnap_ts41x_button_device); | 146 | platform_device_register(&qnap_ts41x_button_device); |
diff --git a/arch/arm/mach-ks8695/Kconfig b/arch/arm/mach-ks8695/Kconfig index fe0c82e30b2d..f5c39a8c2b00 100644 --- a/arch/arm/mach-ks8695/Kconfig +++ b/arch/arm/mach-ks8695/Kconfig | |||
| @@ -4,6 +4,7 @@ menu "Kendin/Micrel KS8695 Implementations" | |||
| 4 | 4 | ||
| 5 | config MACH_KS8695 | 5 | config MACH_KS8695 |
| 6 | bool "KS8695 development board" | 6 | bool "KS8695 development board" |
| 7 | select MIGHT_HAVE_PCI | ||
| 7 | help | 8 | help |
| 8 | Say 'Y' here if you want your kernel to run on the original | 9 | Say 'Y' here if you want your kernel to run on the original |
| 9 | Kendin-Micrel KS8695 development board. | 10 | Kendin-Micrel KS8695 development board. |
diff --git a/arch/arm/mach-ks8695/include/mach/memory.h b/arch/arm/mach-ks8695/include/mach/memory.h index ffa19aae6e05..bace9a681adc 100644 --- a/arch/arm/mach-ks8695/include/mach/memory.h +++ b/arch/arm/mach-ks8695/include/mach/memory.h | |||
| @@ -35,17 +35,17 @@ extern struct bus_type platform_bus_type; | |||
| 35 | __phys_to_virt(x) : __bus_to_virt(x)); }) | 35 | __phys_to_virt(x) : __bus_to_virt(x)); }) |
| 36 | #define __arch_virt_to_dma(dev, x) ({ is_lbus_device(dev) ? \ | 36 | #define __arch_virt_to_dma(dev, x) ({ is_lbus_device(dev) ? \ |
| 37 | (dma_addr_t)__virt_to_phys(x) : (dma_addr_t)__virt_to_bus(x); }) | 37 | (dma_addr_t)__virt_to_phys(x) : (dma_addr_t)__virt_to_bus(x); }) |
| 38 | #define __arch_page_to_dma(dev, x) \ | 38 | #define __arch_pfn_to_dma(dev, pfn) \ |
| 39 | ({ dma_addr_t __dma = page_to_phys(page); \ | 39 | ({ dma_addr_t __dma = __pfn_to_phys(pfn); \ |
| 40 | if (!is_lbus_device(dev)) \ | 40 | if (!is_lbus_device(dev)) \ |
| 41 | __dma = __dma - PHYS_OFFSET + KS8695_PCIMEM_PA; \ | 41 | __dma = __dma - PHYS_OFFSET + KS8695_PCIMEM_PA; \ |
| 42 | __dma; }) | 42 | __dma; }) |
| 43 | 43 | ||
| 44 | #define __arch_dma_to_page(dev, x) \ | 44 | #define __arch_dma_to_pfn(dev, x) \ |
| 45 | ({ dma_addr_t __dma = x; \ | 45 | ({ dma_addr_t __dma = x; \ |
| 46 | if (!is_lbus_device(dev)) \ | 46 | if (!is_lbus_device(dev)) \ |
| 47 | __dma += PHYS_OFFSET - KS8695_PCIMEM_PA; \ | 47 | __dma += PHYS_OFFSET - KS8695_PCIMEM_PA; \ |
| 48 | phys_to_page(__dma); \ | 48 | __phys_to_pfn(__dma); \ |
| 49 | }) | 49 | }) |
| 50 | 50 | ||
| 51 | #endif | 51 | #endif |
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c index 32d63796430a..da0e6498110a 100644 --- a/arch/arm/mach-lpc32xx/clock.c +++ b/arch/arm/mach-lpc32xx/clock.c | |||
| @@ -90,10 +90,9 @@ | |||
| 90 | #include <linux/clk.h> | 90 | #include <linux/clk.h> |
| 91 | #include <linux/amba/bus.h> | 91 | #include <linux/amba/bus.h> |
| 92 | #include <linux/amba/clcd.h> | 92 | #include <linux/amba/clcd.h> |
| 93 | #include <linux/clkdev.h> | ||
| 93 | 94 | ||
| 94 | #include <mach/hardware.h> | 95 | #include <mach/hardware.h> |
| 95 | #include <asm/clkdev.h> | ||
| 96 | #include <mach/clkdev.h> | ||
| 97 | #include <mach/platform.h> | 96 | #include <mach/platform.h> |
| 98 | #include "clock.h" | 97 | #include "clock.h" |
| 99 | #include "common.h" | 98 | #include "common.h" |
diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c index 630dd4a74b26..6162ac308c20 100644 --- a/arch/arm/mach-lpc32xx/timer.c +++ b/arch/arm/mach-lpc32xx/timer.c | |||
| @@ -38,7 +38,6 @@ static cycle_t lpc32xx_clksrc_read(struct clocksource *cs) | |||
| 38 | 38 | ||
| 39 | static struct clocksource lpc32xx_clksrc = { | 39 | static struct clocksource lpc32xx_clksrc = { |
| 40 | .name = "lpc32xx_clksrc", | 40 | .name = "lpc32xx_clksrc", |
| 41 | .shift = 24, | ||
| 42 | .rating = 300, | 41 | .rating = 300, |
| 43 | .read = lpc32xx_clksrc_read, | 42 | .read = lpc32xx_clksrc_read, |
| 44 | .mask = CLOCKSOURCE_MASK(32), | 43 | .mask = CLOCKSOURCE_MASK(32), |
| @@ -171,9 +170,7 @@ static void __init lpc32xx_timer_init(void) | |||
| 171 | __raw_writel(0, LCP32XX_TIMER_MCR(LPC32XX_TIMER1_BASE)); | 170 | __raw_writel(0, LCP32XX_TIMER_MCR(LPC32XX_TIMER1_BASE)); |
| 172 | __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN, | 171 | __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN, |
| 173 | LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE)); | 172 | LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE)); |
| 174 | lpc32xx_clksrc.mult = clocksource_hz2mult(clkrate, | 173 | clocksource_register_hz(&lpc32xx_clksrc, clkrate); |
| 175 | lpc32xx_clksrc.shift); | ||
| 176 | clocksource_register(&lpc32xx_clksrc); | ||
| 177 | } | 174 | } |
| 178 | 175 | ||
| 179 | struct sys_timer lpc32xx_timer = { | 176 | struct sys_timer lpc32xx_timer = { |
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig index 0711d3b620ad..67793a690272 100644 --- a/arch/arm/mach-mmp/Kconfig +++ b/arch/arm/mach-mmp/Kconfig | |||
| @@ -37,25 +37,38 @@ config MACH_TTC_DKB | |||
| 37 | Say 'Y' here if you want to support the Marvell PXA910-based | 37 | Say 'Y' here if you want to support the Marvell PXA910-based |
| 38 | TTC_DKB Development Board. | 38 | TTC_DKB Development Board. |
| 39 | 39 | ||
| 40 | config MACH_BROWNSTONE | ||
| 41 | bool "Marvell's Brownstone Development Platform" | ||
| 42 | depends on !CPU_MOHAWK | ||
| 43 | select CPU_MMP2 | ||
| 44 | help | ||
| 45 | Say 'Y' here if you want to support the Marvell MMP2-based | ||
| 46 | Brown Development Platform. | ||
| 47 | MMP2-based board can't be co-existed with PXA168-based & | ||
| 48 | PXA910-based development board. Since MMP2 is compatible to | ||
| 49 | ARMv7 architecture. | ||
| 50 | |||
| 40 | config MACH_FLINT | 51 | config MACH_FLINT |
| 41 | bool "Marvell's Flint Development Platform" | 52 | bool "Marvell's Flint Development Platform" |
| 53 | depends on !CPU_MOHAWK | ||
| 42 | select CPU_MMP2 | 54 | select CPU_MMP2 |
| 43 | help | 55 | help |
| 44 | Say 'Y' here if you want to support the Marvell MMP2-based | 56 | Say 'Y' here if you want to support the Marvell MMP2-based |
| 45 | Flint Development Platform. | 57 | Flint Development Platform. |
| 46 | MMP2-based board can't be co-existed with PXA168-based & | 58 | MMP2-based board can't be co-existed with PXA168-based & |
| 47 | PXA910-based development board. Since MMP2 is compatible to | 59 | PXA910-based development board. Since MMP2 is compatible to |
| 48 | ARMv6 architecture. | 60 | ARMv7 architecture. |
| 49 | 61 | ||
| 50 | config MACH_MARVELL_JASPER | 62 | config MACH_MARVELL_JASPER |
| 51 | bool "Marvell's Jasper Development Platform" | 63 | bool "Marvell's Jasper Development Platform" |
| 64 | depends on !CPU_MOHAWK | ||
| 52 | select CPU_MMP2 | 65 | select CPU_MMP2 |
| 53 | help | 66 | help |
| 54 | Say 'Y' here if you want to support the Marvell MMP2-base | 67 | Say 'Y' here if you want to support the Marvell MMP2-base |
| 55 | Jasper Development Platform. | 68 | Jasper Development Platform. |
| 56 | MMP2-based board can't be co-existed with PXA168-based & | 69 | MMP2-based board can't be co-existed with PXA168-based & |
| 57 | PXA910-based development board. Since MMP2 is compatible to | 70 | PXA910-based development board. Since MMP2 is compatible to |
| 58 | ARMv6 architecture. | 71 | ARMv7 architecture. |
| 59 | 72 | ||
| 60 | config MACH_TETON_BGA | 73 | config MACH_TETON_BGA |
| 61 | bool "Marvell's PXA168 Teton BGA Development Board" | 74 | bool "Marvell's PXA168 Teton BGA Development Board" |
| @@ -80,8 +93,7 @@ config CPU_PXA910 | |||
| 80 | 93 | ||
| 81 | config CPU_MMP2 | 94 | config CPU_MMP2 |
| 82 | bool | 95 | bool |
| 83 | select CPU_V6 | 96 | select CPU_PJ4 |
| 84 | select CPU_32v6K | ||
| 85 | help | 97 | help |
| 86 | Select code specific to MMP2. MMP2 is ARMv6 compatible. | 98 | Select code specific to MMP2. MMP2 is ARMv7 compatible. |
| 87 | endif | 99 | endif |
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile index 751cdbf733c8..5c68382141af 100644 --- a/arch/arm/mach-mmp/Makefile +++ b/arch/arm/mach-mmp/Makefile | |||
| @@ -15,6 +15,7 @@ obj-$(CONFIG_MACH_ZYLONITE2) += aspenite.o | |||
| 15 | obj-$(CONFIG_MACH_AVENGERS_LITE)+= avengers_lite.o | 15 | obj-$(CONFIG_MACH_AVENGERS_LITE)+= avengers_lite.o |
| 16 | obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o | 16 | obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o |
| 17 | obj-$(CONFIG_MACH_TTC_DKB) += ttc_dkb.o | 17 | obj-$(CONFIG_MACH_TTC_DKB) += ttc_dkb.o |
| 18 | obj-$(CONFIG_MACH_BROWNSTONE) += brownstone.o | ||
| 18 | obj-$(CONFIG_MACH_FLINT) += flint.o | 19 | obj-$(CONFIG_MACH_FLINT) += flint.o |
| 19 | obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o | 20 | obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o |
| 20 | obj-$(CONFIG_MACH_TETON_BGA) += teton_bga.o | 21 | obj-$(CONFIG_MACH_TETON_BGA) += teton_bga.o |
diff --git a/arch/arm/mach-mmp/brownstone.c b/arch/arm/mach-mmp/brownstone.c new file mode 100644 index 000000000000..7bb78fd5a2a6 --- /dev/null +++ b/arch/arm/mach-mmp/brownstone.c | |||
| @@ -0,0 +1,204 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/brownstone.c | ||
| 3 | * | ||
| 4 | * Support for the Marvell Brownstone Development Platform. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2009-2010 Marvell International Ltd. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * publishhed by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/init.h> | ||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/platform_device.h> | ||
| 16 | #include <linux/io.h> | ||
| 17 | #include <linux/gpio.h> | ||
| 18 | #include <linux/regulator/machine.h> | ||
| 19 | #include <linux/regulator/max8649.h> | ||
| 20 | #include <linux/regulator/fixed.h> | ||
| 21 | #include <linux/mfd/max8925.h> | ||
| 22 | |||
| 23 | #include <asm/mach-types.h> | ||
| 24 | #include <asm/mach/arch.h> | ||
| 25 | #include <mach/addr-map.h> | ||
| 26 | #include <mach/mfp-mmp2.h> | ||
| 27 | #include <mach/mmp2.h> | ||
| 28 | #include <mach/irqs.h> | ||
| 29 | |||
| 30 | #include "common.h" | ||
| 31 | |||
| 32 | #define BROWNSTONE_NR_IRQS (IRQ_BOARD_START + 40) | ||
| 33 | |||
| 34 | #define GPIO_5V_ENABLE (89) | ||
| 35 | |||
| 36 | static unsigned long brownstone_pin_config[] __initdata = { | ||
| 37 | /* UART1 */ | ||
| 38 | GPIO29_UART1_RXD, | ||
| 39 | GPIO30_UART1_TXD, | ||
| 40 | |||
| 41 | /* UART3 */ | ||
| 42 | GPIO51_UART3_RXD, | ||
| 43 | GPIO52_UART3_TXD, | ||
| 44 | |||
| 45 | /* DFI */ | ||
| 46 | GPIO168_DFI_D0, | ||
| 47 | GPIO167_DFI_D1, | ||
| 48 | GPIO166_DFI_D2, | ||
| 49 | GPIO165_DFI_D3, | ||
| 50 | GPIO107_DFI_D4, | ||
| 51 | GPIO106_DFI_D5, | ||
| 52 | GPIO105_DFI_D6, | ||
| 53 | GPIO104_DFI_D7, | ||
| 54 | GPIO111_DFI_D8, | ||
| 55 | GPIO164_DFI_D9, | ||
| 56 | GPIO163_DFI_D10, | ||
| 57 | GPIO162_DFI_D11, | ||
| 58 | GPIO161_DFI_D12, | ||
| 59 | GPIO110_DFI_D13, | ||
| 60 | GPIO109_DFI_D14, | ||
| 61 | GPIO108_DFI_D15, | ||
| 62 | GPIO143_ND_nCS0, | ||
| 63 | GPIO144_ND_nCS1, | ||
| 64 | GPIO147_ND_nWE, | ||
| 65 | GPIO148_ND_nRE, | ||
| 66 | GPIO150_ND_ALE, | ||
| 67 | GPIO149_ND_CLE, | ||
| 68 | GPIO112_ND_RDY0, | ||
| 69 | GPIO160_ND_RDY1, | ||
| 70 | |||
| 71 | /* PMIC */ | ||
| 72 | PMIC_PMIC_INT | MFP_LPM_EDGE_FALL, | ||
| 73 | |||
| 74 | /* MMC0 */ | ||
| 75 | GPIO131_MMC1_DAT3 | MFP_PULL_HIGH, | ||
| 76 | GPIO132_MMC1_DAT2 | MFP_PULL_HIGH, | ||
| 77 | GPIO133_MMC1_DAT1 | MFP_PULL_HIGH, | ||
| 78 | GPIO134_MMC1_DAT0 | MFP_PULL_HIGH, | ||
| 79 | GPIO136_MMC1_CMD | MFP_PULL_HIGH, | ||
| 80 | GPIO139_MMC1_CLK, | ||
| 81 | GPIO140_MMC1_CD | MFP_PULL_LOW, | ||
| 82 | GPIO141_MMC1_WP | MFP_PULL_LOW, | ||
| 83 | |||
| 84 | /* MMC1 */ | ||
| 85 | GPIO37_MMC2_DAT3 | MFP_PULL_HIGH, | ||
| 86 | GPIO38_MMC2_DAT2 | MFP_PULL_HIGH, | ||
| 87 | GPIO39_MMC2_DAT1 | MFP_PULL_HIGH, | ||
| 88 | GPIO40_MMC2_DAT0 | MFP_PULL_HIGH, | ||
| 89 | GPIO41_MMC2_CMD | MFP_PULL_HIGH, | ||
| 90 | GPIO42_MMC2_CLK, | ||
| 91 | |||
| 92 | /* MMC2 */ | ||
| 93 | GPIO165_MMC3_DAT7 | MFP_PULL_HIGH, | ||
| 94 | GPIO162_MMC3_DAT6 | MFP_PULL_HIGH, | ||
| 95 | GPIO166_MMC3_DAT5 | MFP_PULL_HIGH, | ||
| 96 | GPIO163_MMC3_DAT4 | MFP_PULL_HIGH, | ||
| 97 | GPIO167_MMC3_DAT3 | MFP_PULL_HIGH, | ||
| 98 | GPIO164_MMC3_DAT2 | MFP_PULL_HIGH, | ||
| 99 | GPIO168_MMC3_DAT1 | MFP_PULL_HIGH, | ||
| 100 | GPIO111_MMC3_DAT0 | MFP_PULL_HIGH, | ||
| 101 | GPIO112_MMC3_CMD | MFP_PULL_HIGH, | ||
| 102 | GPIO151_MMC3_CLK, | ||
| 103 | |||
| 104 | /* 5V regulator */ | ||
| 105 | GPIO89_GPIO, | ||
| 106 | }; | ||
| 107 | |||
| 108 | static struct regulator_consumer_supply max8649_supply[] = { | ||
| 109 | REGULATOR_SUPPLY("vcc_core", NULL), | ||
| 110 | }; | ||
| 111 | |||
| 112 | static struct regulator_init_data max8649_init_data = { | ||
| 113 | .constraints = { | ||
| 114 | .name = "vcc_core range", | ||
| 115 | .min_uV = 1150000, | ||
| 116 | .max_uV = 1280000, | ||
| 117 | .always_on = 1, | ||
| 118 | .boot_on = 1, | ||
| 119 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, | ||
| 120 | }, | ||
| 121 | .num_consumer_supplies = 1, | ||
| 122 | .consumer_supplies = &max8649_supply[0], | ||
| 123 | }; | ||
| 124 | |||
| 125 | static struct max8649_platform_data brownstone_max8649_info = { | ||
| 126 | .mode = 2, /* VID1 = 1, VID0 = 0 */ | ||
| 127 | .extclk = 0, | ||
| 128 | .ramp_timing = MAX8649_RAMP_32MV, | ||
| 129 | .regulator = &max8649_init_data, | ||
| 130 | }; | ||
| 131 | |||
| 132 | static struct regulator_consumer_supply brownstone_v_5vp_supplies[] = { | ||
| 133 | REGULATOR_SUPPLY("v_5vp", NULL), | ||
| 134 | }; | ||
| 135 | |||
| 136 | static struct regulator_init_data brownstone_v_5vp_data = { | ||
| 137 | .constraints = { | ||
| 138 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | ||
| 139 | }, | ||
| 140 | .num_consumer_supplies = ARRAY_SIZE(brownstone_v_5vp_supplies), | ||
| 141 | .consumer_supplies = brownstone_v_5vp_supplies, | ||
| 142 | }; | ||
| 143 | |||
| 144 | static struct fixed_voltage_config brownstone_v_5vp = { | ||
| 145 | .supply_name = "v_5vp", | ||
| 146 | .microvolts = 5000000, | ||
| 147 | .gpio = GPIO_5V_ENABLE, | ||
| 148 | .enable_high = 1, | ||
| 149 | .enabled_at_boot = 1, | ||
| 150 | .init_data = &brownstone_v_5vp_data, | ||
| 151 | }; | ||
| 152 | |||
| 153 | static struct platform_device brownstone_v_5vp_device = { | ||
| 154 | .name = "reg-fixed-voltage", | ||
| 155 | .id = 1, | ||
| 156 | .dev = { | ||
| 157 | .platform_data = &brownstone_v_5vp, | ||
| 158 | }, | ||
| 159 | }; | ||
| 160 | |||
| 161 | static struct max8925_platform_data brownstone_max8925_info = { | ||
| 162 | .irq_base = IRQ_BOARD_START, | ||
| 163 | }; | ||
| 164 | |||
| 165 | static struct i2c_board_info brownstone_twsi1_info[] = { | ||
| 166 | [0] = { | ||
| 167 | .type = "max8649", | ||
| 168 | .addr = 0x60, | ||
| 169 | .platform_data = &brownstone_max8649_info, | ||
| 170 | }, | ||
| 171 | [1] = { | ||
| 172 | .type = "max8925", | ||
| 173 | .addr = 0x3c, | ||
| 174 | .irq = IRQ_MMP2_PMIC, | ||
| 175 | .platform_data = &brownstone_max8925_info, | ||
| 176 | }, | ||
| 177 | }; | ||
| 178 | |||
| 179 | static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc0 = { | ||
| 180 | .max_speed = 25000000, | ||
| 181 | }; | ||
| 182 | |||
| 183 | static void __init brownstone_init(void) | ||
| 184 | { | ||
| 185 | mfp_config(ARRAY_AND_SIZE(brownstone_pin_config)); | ||
| 186 | |||
| 187 | /* on-chip devices */ | ||
| 188 | mmp2_add_uart(1); | ||
| 189 | mmp2_add_uart(3); | ||
| 190 | mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(brownstone_twsi1_info)); | ||
| 191 | mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */ | ||
| 192 | |||
| 193 | /* enable 5v regulator */ | ||
| 194 | platform_device_register(&brownstone_v_5vp_device); | ||
| 195 | } | ||
| 196 | |||
| 197 | MACHINE_START(BROWNSTONE, "Brownstone Development Platform") | ||
| 198 | /* Maintainer: Haojian Zhuang <haojian.zhuang@marvell.com> */ | ||
| 199 | .map_io = mmp_map_io, | ||
| 200 | .nr_irqs = BROWNSTONE_NR_IRQS, | ||
| 201 | .init_irq = mmp2_init_irq, | ||
| 202 | .timer = &mmp2_timer, | ||
| 203 | .init_machine = brownstone_init, | ||
| 204 | MACHINE_END | ||
diff --git a/arch/arm/mach-mmp/clock.h b/arch/arm/mach-mmp/clock.h index 016ae94691c0..9b027d7491f5 100644 --- a/arch/arm/mach-mmp/clock.h +++ b/arch/arm/mach-mmp/clock.h | |||
| @@ -6,7 +6,7 @@ | |||
| 6 | * published by the Free Software Foundation. | 6 | * published by the Free Software Foundation. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | #include <asm/clkdev.h> | 9 | #include <linux/clkdev.h> |
| 10 | 10 | ||
| 11 | struct clkops { | 11 | struct clkops { |
| 12 | void (*enable)(struct clk *); | 12 | void (*enable)(struct clk *); |
diff --git a/arch/arm/mach-mmp/flint.c b/arch/arm/mach-mmp/flint.c index bdeb6db4d49a..c4fd806b15b4 100644 --- a/arch/arm/mach-mmp/flint.c +++ b/arch/arm/mach-mmp/flint.c | |||
| @@ -47,7 +47,7 @@ static unsigned long flint_pin_config[] __initdata = { | |||
| 47 | GPIO113_SMC_RDY, | 47 | GPIO113_SMC_RDY, |
| 48 | 48 | ||
| 49 | /*Ethernet*/ | 49 | /*Ethernet*/ |
| 50 | GPIO155_GPIO155, | 50 | GPIO155_GPIO, |
| 51 | 51 | ||
| 52 | /* DFI */ | 52 | /* DFI */ |
| 53 | GPIO168_DFI_D0, | 53 | GPIO168_DFI_D0, |
diff --git a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h index 761c2dacc079..117e30366087 100644 --- a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h +++ b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h | |||
| @@ -9,175 +9,175 @@ | |||
| 9 | #define MFP_DRIVE_FAST (0x8 << 13) | 9 | #define MFP_DRIVE_FAST (0x8 << 13) |
| 10 | 10 | ||
| 11 | /* GPIO */ | 11 | /* GPIO */ |
| 12 | #define GPIO0_GPIO0 MFP_CFG(GPIO0, AF0) | 12 | #define GPIO0_GPIO MFP_CFG(GPIO0, AF0) |
| 13 | #define GPIO1_GPIO1 MFP_CFG(GPIO1, AF0) | 13 | #define GPIO1_GPIO MFP_CFG(GPIO1, AF0) |
| 14 | #define GPIO2_GPIO2 MFP_CFG(GPIO2, AF0) | 14 | #define GPIO2_GPIO MFP_CFG(GPIO2, AF0) |
| 15 | #define GPIO3_GPIO3 MFP_CFG(GPIO3, AF0) | 15 | #define GPIO3_GPIO MFP_CFG(GPIO3, AF0) |
| 16 | #define GPIO4_GPIO4 MFP_CFG(GPIO4, AF0) | 16 | #define GPIO4_GPIO MFP_CFG(GPIO4, AF0) |
| 17 | #define GPIO5_GPIO5 MFP_CFG(GPIO5, AF0) | 17 | #define GPIO5_GPIO MFP_CFG(GPIO5, AF0) |
| 18 | #define GPIO6_GPIO6 MFP_CFG(GPIO6, AF0) | 18 | #define GPIO6_GPIO MFP_CFG(GPIO6, AF0) |
| 19 | #define GPIO7_GPIO7 MFP_CFG(GPIO7, AF0) | 19 | #define GPIO7_GPIO MFP_CFG(GPIO7, AF0) |
| 20 | #define GPIO8_GPIO8 MFP_CFG(GPIO8, AF0) | 20 | #define GPIO8_GPIO MFP_CFG(GPIO8, AF0) |
| 21 | #define GPIO9_GPIO9 MFP_CFG(GPIO9, AF0) | 21 | #define GPIO9_GPIO MFP_CFG(GPIO9, AF0) |
| 22 | #define GPIO10_GPIO10 MFP_CFG(GPIO10, AF0) | 22 | #define GPIO10_GPIO MFP_CFG(GPIO10, AF0) |
| 23 | #define GPIO11_GPIO11 MFP_CFG(GPIO11, AF0) | 23 | #define GPIO11_GPIO MFP_CFG(GPIO11, AF0) |
| 24 | #define GPIO12_GPIO12 MFP_CFG(GPIO12, AF0) | 24 | #define GPIO12_GPIO MFP_CFG(GPIO12, AF0) |
| 25 | #define GPIO13_GPIO13 MFP_CFG(GPIO13, AF0) | 25 | #define GPIO13_GPIO MFP_CFG(GPIO13, AF0) |
| 26 | #define GPIO14_GPIO14 MFP_CFG(GPIO14, AF0) | 26 | #define GPIO14_GPIO MFP_CFG(GPIO14, AF0) |
| 27 | #define GPIO15_GPIO15 MFP_CFG(GPIO15, AF0) | 27 | #define GPIO15_GPIO MFP_CFG(GPIO15, AF0) |
| 28 | #define GPIO16_GPIO16 MFP_CFG(GPIO16, AF0) | 28 | #define GPIO16_GPIO MFP_CFG(GPIO16, AF0) |
| 29 | #define GPIO17_GPIO17 MFP_CFG(GPIO17, AF0) | 29 | #define GPIO17_GPIO MFP_CFG(GPIO17, AF0) |
| 30 | #define GPIO18_GPIO18 MFP_CFG(GPIO18, AF0) | 30 | #define GPIO18_GPIO MFP_CFG(GPIO18, AF0) |
| 31 | #define GPIO19_GPIO19 MFP_CFG(GPIO19, AF0) | 31 | #define GPIO19_GPIO MFP_CFG(GPIO19, AF0) |
| 32 | #define GPIO20_GPIO20 MFP_CFG(GPIO20, AF0) | 32 | #define GPIO20_GPIO MFP_CFG(GPIO20, AF0) |
| 33 | #define GPIO21_GPIO21 MFP_CFG(GPIO21, AF0) | 33 | #define GPIO21_GPIO MFP_CFG(GPIO21, AF0) |
| 34 | #define GPIO22_GPIO22 MFP_CFG(GPIO22, AF0) | 34 | #define GPIO22_GPIO MFP_CFG(GPIO22, AF0) |
| 35 | #define GPIO23_GPIO23 MFP_CFG(GPIO23, AF0) | 35 | #define GPIO23_GPIO MFP_CFG(GPIO23, AF0) |
| 36 | #define GPIO24_GPIO24 MFP_CFG(GPIO24, AF0) | 36 | #define GPIO24_GPIO MFP_CFG(GPIO24, AF0) |
| 37 | #define GPIO25_GPIO25 MFP_CFG(GPIO25, AF0) | 37 | #define GPIO25_GPIO MFP_CFG(GPIO25, AF0) |
| 38 | #define GPIO26_GPIO26 MFP_CFG(GPIO26, AF0) | 38 | #define GPIO26_GPIO MFP_CFG(GPIO26, AF0) |
| 39 | #define GPIO27_GPIO27 MFP_CFG(GPIO27, AF0) | 39 | #define GPIO27_GPIO MFP_CFG(GPIO27, AF0) |
| 40 | #define GPIO28_GPIO28 MFP_CFG(GPIO28, AF0) | 40 | #define GPIO28_GPIO MFP_CFG(GPIO28, AF0) |
| 41 | #define GPIO29_GPIO29 MFP_CFG(GPIO29, AF0) | 41 | #define GPIO29_GPIO MFP_CFG(GPIO29, AF0) |
| 42 | #define GPIO30_GPIO30 MFP_CFG(GPIO30, AF0) | 42 | #define GPIO30_GPIO MFP_CFG(GPIO30, AF0) |
| 43 | #define GPIO31_GPIO31 MFP_CFG(GPIO31, AF0) | 43 | #define GPIO31_GPIO MFP_CFG(GPIO31, AF0) |
| 44 | #define GPIO32_GPIO32 MFP_CFG(GPIO32, AF0) | 44 | #define GPIO32_GPIO MFP_CFG(GPIO32, AF0) |
| 45 | #define GPIO33_GPIO33 MFP_CFG(GPIO33, AF0) | 45 | #define GPIO33_GPIO MFP_CFG(GPIO33, AF0) |
| 46 | #define GPIO34_GPIO34 MFP_CFG(GPIO34, AF0) | 46 | #define GPIO34_GPIO MFP_CFG(GPIO34, AF0) |
| 47 | #define GPIO35_GPIO35 MFP_CFG(GPIO35, AF0) | 47 | #define GPIO35_GPIO MFP_CFG(GPIO35, AF0) |
| 48 | #define GPIO36_GPIO36 MFP_CFG(GPIO36, AF0) | 48 | #define GPIO36_GPIO MFP_CFG(GPIO36, AF0) |
| 49 | #define GPIO37_GPIO37 MFP_CFG(GPIO37, AF0) | 49 | #define GPIO37_GPIO MFP_CFG(GPIO37, AF0) |
| 50 | #define GPIO38_GPIO38 MFP_CFG(GPIO38, AF0) | 50 | #define GPIO38_GPIO MFP_CFG(GPIO38, AF0) |
| 51 | #define GPIO39_GPIO39 MFP_CFG(GPIO39, AF0) | 51 | #define GPIO39_GPIO MFP_CFG(GPIO39, AF0) |
| 52 | #define GPIO40_GPIO40 MFP_CFG(GPIO40, AF0) | 52 | #define GPIO40_GPIO MFP_CFG(GPIO40, AF0) |
| 53 | #define GPIO41_GPIO41 MFP_CFG(GPIO41, AF0) | 53 | #define GPIO41_GPIO MFP_CFG(GPIO41, AF0) |
| 54 | #define GPIO42_GPIO42 MFP_CFG(GPIO42, AF0) | 54 | #define GPIO42_GPIO MFP_CFG(GPIO42, AF0) |
| 55 | #define GPIO43_GPIO43 MFP_CFG(GPIO43, AF0) | 55 | #define GPIO43_GPIO MFP_CFG(GPIO43, AF0) |
| 56 | #define GPIO44_GPIO44 MFP_CFG(GPIO44, AF0) | 56 | #define GPIO44_GPIO MFP_CFG(GPIO44, AF0) |
| 57 | #define GPIO45_GPIO45 MFP_CFG(GPIO45, AF0) | 57 | #define GPIO45_GPIO MFP_CFG(GPIO45, AF0) |
| 58 | #define GPIO46_GPIO46 MFP_CFG(GPIO46, AF0) | 58 | #define GPIO46_GPIO MFP_CFG(GPIO46, AF0) |
| 59 | #define GPIO47_GPIO47 MFP_CFG(GPIO47, AF0) | 59 | #define GPIO47_GPIO MFP_CFG(GPIO47, AF0) |
| 60 | #define GPIO48_GPIO48 MFP_CFG(GPIO48, AF0) | 60 | #define GPIO48_GPIO MFP_CFG(GPIO48, AF0) |
| 61 | #define GPIO49_GPIO49 MFP_CFG(GPIO49, AF0) | 61 | #define GPIO49_GPIO MFP_CFG(GPIO49, AF0) |
| 62 | #define GPIO50_GPIO50 MFP_CFG(GPIO50, AF0) | 62 | #define GPIO50_GPIO MFP_CFG(GPIO50, AF0) |
| 63 | #define GPIO51_GPIO51 MFP_CFG(GPIO51, AF0) | 63 | #define GPIO51_GPIO MFP_CFG(GPIO51, AF0) |
| 64 | #define GPIO52_GPIO52 MFP_CFG(GPIO52, AF0) | 64 | #define GPIO52_GPIO MFP_CFG(GPIO52, AF0) |
| 65 | #define GPIO53_GPIO53 MFP_CFG(GPIO53, AF0) | 65 | #define GPIO53_GPIO MFP_CFG(GPIO53, AF0) |
| 66 | #define GPIO54_GPIO54 MFP_CFG(GPIO54, AF0) | 66 | #define GPIO54_GPIO MFP_CFG(GPIO54, AF0) |
| 67 | #define GPIO55_GPIO55 MFP_CFG(GPIO55, AF0) | 67 | #define GPIO55_GPIO MFP_CFG(GPIO55, AF0) |
| 68 | #define GPIO56_GPIO56 MFP_CFG(GPIO56, AF0) | 68 | #define GPIO56_GPIO MFP_CFG(GPIO56, AF0) |
| 69 | #define GPIO57_GPIO57 MFP_CFG(GPIO57, AF0) | 69 | #define GPIO57_GPIO MFP_CFG(GPIO57, AF0) |
| 70 | #define GPIO58_GPIO58 MFP_CFG(GPIO58, AF0) | 70 | #define GPIO58_GPIO MFP_CFG(GPIO58, AF0) |
| 71 | #define GPIO59_GPIO59 MFP_CFG(GPIO59, AF0) | 71 | #define GPIO59_GPIO MFP_CFG(GPIO59, AF0) |
| 72 | #define GPIO60_GPIO60 MFP_CFG(GPIO60, AF0) | 72 | #define GPIO60_GPIO MFP_CFG(GPIO60, AF0) |
| 73 | #define GPIO61_GPIO61 MFP_CFG(GPIO61, AF0) | 73 | #define GPIO61_GPIO MFP_CFG(GPIO61, AF0) |
| 74 | #define GPIO62_GPIO62 MFP_CFG(GPIO62, AF0) | 74 | #define GPIO62_GPIO MFP_CFG(GPIO62, AF0) |
| 75 | #define GPIO63_GPIO63 MFP_CFG(GPIO63, AF0) | 75 | #define GPIO63_GPIO MFP_CFG(GPIO63, AF0) |
| 76 | #define GPIO64_GPIO64 MFP_CFG(GPIO64, AF0) | 76 | #define GPIO64_GPIO MFP_CFG(GPIO64, AF0) |
| 77 | #define GPIO65_GPIO65 MFP_CFG(GPIO65, AF0) | 77 | #define GPIO65_GPIO MFP_CFG(GPIO65, AF0) |
| 78 | #define GPIO66_GPIO66 MFP_CFG(GPIO66, AF0) | 78 | #define GPIO66_GPIO MFP_CFG(GPIO66, AF0) |
| 79 | #define GPIO67_GPIO67 MFP_CFG(GPIO67, AF0) | 79 | #define GPIO67_GPIO MFP_CFG(GPIO67, AF0) |
| 80 | #define GPIO68_GPIO68 MFP_CFG(GPIO68, AF0) | 80 | #define GPIO68_GPIO MFP_CFG(GPIO68, AF0) |
| 81 | #define GPIO69_GPIO69 MFP_CFG(GPIO69, AF0) | 81 | #define GPIO69_GPIO MFP_CFG(GPIO69, AF0) |
| 82 | #define GPIO70_GPIO70 MFP_CFG(GPIO70, AF0) | 82 | #define GPIO70_GPIO MFP_CFG(GPIO70, AF0) |
| 83 | #define GPIO71_GPIO71 MFP_CFG(GPIO71, AF0) | 83 | #define GPIO71_GPIO MFP_CFG(GPIO71, AF0) |
| 84 | #define GPIO72_GPIO72 MFP_CFG(GPIO72, AF0) | 84 | #define GPIO72_GPIO MFP_CFG(GPIO72, AF0) |
| 85 | #define GPIO73_GPIO73 MFP_CFG(GPIO73, AF0) | 85 | #define GPIO73_GPIO MFP_CFG(GPIO73, AF0) |
| 86 | #define GPIO74_GPIO74 MFP_CFG(GPIO74, AF0) | 86 | #define GPIO74_GPIO MFP_CFG(GPIO74, AF0) |
| 87 | #define GPIO75_GPIO75 MFP_CFG(GPIO75, AF0) | 87 | #define GPIO75_GPIO MFP_CFG(GPIO75, AF0) |
| 88 | #define GPIO76_GPIO76 MFP_CFG(GPIO76, AF0) | 88 | #define GPIO76_GPIO MFP_CFG(GPIO76, AF0) |
| 89 | #define GPIO77_GPIO77 MFP_CFG(GPIO77, AF0) | 89 | #define GPIO77_GPIO MFP_CFG(GPIO77, AF0) |
| 90 | #define GPIO78_GPIO78 MFP_CFG(GPIO78, AF0) | 90 | #define GPIO78_GPIO MFP_CFG(GPIO78, AF0) |
| 91 | #define GPIO79_GPIO79 MFP_CFG(GPIO79, AF0) | 91 | #define GPIO79_GPIO MFP_CFG(GPIO79, AF0) |
| 92 | #define GPIO80_GPIO80 MFP_CFG(GPIO80, AF0) | 92 | #define GPIO80_GPIO MFP_CFG(GPIO80, AF0) |
| 93 | #define GPIO81_GPIO81 MFP_CFG(GPIO81, AF0) | 93 | #define GPIO81_GPIO MFP_CFG(GPIO81, AF0) |
| 94 | #define GPIO82_GPIO82 MFP_CFG(GPIO82, AF0) | 94 | #define GPIO82_GPIO MFP_CFG(GPIO82, AF0) |
| 95 | #define GPIO83_GPIO83 MFP_CFG(GPIO83, AF0) | 95 | #define GPIO83_GPIO MFP_CFG(GPIO83, AF0) |
| 96 | #define GPIO84_GPIO84 MFP_CFG(GPIO84, AF0) | 96 | #define GPIO84_GPIO MFP_CFG(GPIO84, AF0) |
| 97 | #define GPIO85_GPIO85 MFP_CFG(GPIO85, AF0) | 97 | #define GPIO85_GPIO MFP_CFG(GPIO85, AF0) |
| 98 | #define GPIO86_GPIO86 MFP_CFG(GPIO86, AF0) | 98 | #define GPIO86_GPIO MFP_CFG(GPIO86, AF0) |
| 99 | #define GPIO87_GPIO87 MFP_CFG(GPIO87, AF0) | 99 | #define GPIO87_GPIO MFP_CFG(GPIO87, AF0) |
| 100 | #define GPIO88_GPIO88 MFP_CFG(GPIO88, AF0) | 100 | #define GPIO88_GPIO MFP_CFG(GPIO88, AF0) |
| 101 | #define GPIO89_GPIO89 MFP_CFG(GPIO89, AF0) | 101 | #define GPIO89_GPIO MFP_CFG(GPIO89, AF0) |
| 102 | #define GPIO90_GPIO90 MFP_CFG(GPIO90, AF0) | 102 | #define GPIO90_GPIO MFP_CFG(GPIO90, AF0) |
| 103 | #define GPIO91_GPIO91 MFP_CFG(GPIO91, AF0) | 103 | #define GPIO91_GPIO MFP_CFG(GPIO91, AF0) |
| 104 | #define GPIO92_GPIO92 MFP_CFG(GPIO92, AF0) | 104 | #define GPIO92_GPIO MFP_CFG(GPIO92, AF0) |
| 105 | #define GPIO93_GPIO93 MFP_CFG(GPIO93, AF0) | 105 | #define GPIO93_GPIO MFP_CFG(GPIO93, AF0) |
| 106 | #define GPIO94_GPIO94 MFP_CFG(GPIO94, AF0) | 106 | #define GPIO94_GPIO MFP_CFG(GPIO94, AF0) |
| 107 | #define GPIO95_GPIO95 MFP_CFG(GPIO95, AF0) | 107 | #define GPIO95_GPIO MFP_CFG(GPIO95, AF0) |
| 108 | #define GPIO96_GPIO96 MFP_CFG(GPIO96, AF0) | 108 | #define GPIO96_GPIO MFP_CFG(GPIO96, AF0) |
| 109 | #define GPIO97_GPIO97 MFP_CFG(GPIO97, AF0) | 109 | #define GPIO97_GPIO MFP_CFG(GPIO97, AF0) |
| 110 | #define GPIO98_GPIO98 MFP_CFG(GPIO98, AF0) | 110 | #define GPIO98_GPIO MFP_CFG(GPIO98, AF0) |
| 111 | #define GPIO99_GPIO99 MFP_CFG(GPIO99, AF0) | 111 | #define GPIO99_GPIO MFP_CFG(GPIO99, AF0) |
| 112 | #define GPIO100_GPIO100 MFP_CFG(GPIO100, AF0) | 112 | #define GPIO100_GPIO MFP_CFG(GPIO100, AF0) |
| 113 | #define GPIO101_GPIO101 MFP_CFG(GPIO101, AF0) | 113 | #define GPIO101_GPIO MFP_CFG(GPIO101, AF0) |
| 114 | #define GPIO102_GPIO102 MFP_CFG(GPIO102, AF1) | 114 | #define GPIO102_GPIO MFP_CFG(GPIO102, AF1) |
| 115 | #define GPIO103_GPIO103 MFP_CFG(GPIO103, AF1) | 115 | #define GPIO103_GPIO MFP_CFG(GPIO103, AF1) |
| 116 | #define GPIO104_GPIO104 MFP_CFG(GPIO104, AF1) | 116 | #define GPIO104_GPIO MFP_CFG(GPIO104, AF1) |
| 117 | #define GPIO105_GPIO105 MFP_CFG(GPIO105, AF1) | 117 | #define GPIO105_GPIO MFP_CFG(GPIO105, AF1) |
| 118 | #define GPIO106_GPIO106 MFP_CFG(GPIO106, AF1) | 118 | #define GPIO106_GPIO MFP_CFG(GPIO106, AF1) |
| 119 | #define GPIO107_GPIO107 MFP_CFG(GPIO107, AF1) | 119 | #define GPIO107_GPIO MFP_CFG(GPIO107, AF1) |
| 120 | #define GPIO108_GPIO108 MFP_CFG(GPIO108, AF1) | 120 | #define GPIO108_GPIO MFP_CFG(GPIO108, AF1) |
| 121 | #define GPIO109_GPIO109 MFP_CFG(GPIO109, AF1) | 121 | #define GPIO109_GPIO MFP_CFG(GPIO109, AF1) |
| 122 | #define GPIO110_GPIO110 MFP_CFG(GPIO110, AF1) | 122 | #define GPIO110_GPIO MFP_CFG(GPIO110, AF1) |
| 123 | #define GPIO111_GPIO111 MFP_CFG(GPIO111, AF1) | 123 | #define GPIO111_GPIO MFP_CFG(GPIO111, AF1) |
| 124 | #define GPIO112_GPIO112 MFP_CFG(GPIO112, AF1) | 124 | #define GPIO112_GPIO MFP_CFG(GPIO112, AF1) |
| 125 | #define GPIO113_GPIO113 MFP_CFG(GPIO113, AF1) | 125 | #define GPIO113_GPIO MFP_CFG(GPIO113, AF1) |
| 126 | #define GPIO114_GPIO114 MFP_CFG(GPIO114, AF0) | 126 | #define GPIO114_GPIO MFP_CFG(GPIO114, AF0) |
| 127 | #define GPIO115_GPIO115 MFP_CFG(GPIO115, AF0) | 127 | #define GPIO115_GPIO MFP_CFG(GPIO115, AF0) |
| 128 | #define GPIO116_GPIO116 MFP_CFG(GPIO116, AF0) | 128 | #define GPIO116_GPIO MFP_CFG(GPIO116, AF0) |
| 129 | #define GPIO117_GPIO117 MFP_CFG(GPIO117, AF0) | 129 | #define GPIO117_GPIO MFP_CFG(GPIO117, AF0) |
| 130 | #define GPIO118_GPIO118 MFP_CFG(GPIO118, AF0) | 130 | #define GPIO118_GPIO MFP_CFG(GPIO118, AF0) |
| 131 | #define GPIO119_GPIO119 MFP_CFG(GPIO119, AF0) | 131 | #define GPIO119_GPIO MFP_CFG(GPIO119, AF0) |
| 132 | #define GPIO120_GPIO120 MFP_CFG(GPIO120, AF0) | 132 | #define GPIO120_GPIO MFP_CFG(GPIO120, AF0) |
| 133 | #define GPIO121_GPIO121 MFP_CFG(GPIO121, AF0) | 133 | #define GPIO121_GPIO MFP_CFG(GPIO121, AF0) |
| 134 | #define GPIO122_GPIO122 MFP_CFG(GPIO122, AF0) | 134 | #define GPIO122_GPIO MFP_CFG(GPIO122, AF0) |
| 135 | #define GPIO123_GPIO123 MFP_CFG(GPIO123, AF0) | 135 | #define GPIO123_GPIO MFP_CFG(GPIO123, AF0) |
| 136 | #define GPIO124_GPIO124 MFP_CFG(GPIO124, AF0) | 136 | #define GPIO124_GPIO MFP_CFG(GPIO124, AF0) |
| 137 | #define GPIO125_GPIO125 MFP_CFG(GPIO125, AF0) | 137 | #define GPIO125_GPIO MFP_CFG(GPIO125, AF0) |
| 138 | #define GPIO126_GPIO126 MFP_CFG(GPIO126, AF0) | 138 | #define GPIO126_GPIO MFP_CFG(GPIO126, AF0) |
| 139 | #define GPIO127_GPIO127 MFP_CFG(GPIO127, AF0) | 139 | #define GPIO127_GPIO MFP_CFG(GPIO127, AF0) |
| 140 | #define GPIO128_GPIO128 MFP_CFG(GPIO128, AF0) | 140 | #define GPIO128_GPIO MFP_CFG(GPIO128, AF0) |
| 141 | #define GPIO129_GPIO129 MFP_CFG(GPIO129, AF0) | 141 | #define GPIO129_GPIO MFP_CFG(GPIO129, AF0) |
| 142 | #define GPIO130_GPIO130 MFP_CFG(GPIO130, AF0) | 142 | #define GPIO130_GPIO MFP_CFG(GPIO130, AF0) |
| 143 | #define GPIO131_GPIO131 MFP_CFG(GPIO131, AF0) | 143 | #define GPIO131_GPIO MFP_CFG(GPIO131, AF0) |
| 144 | #define GPIO132_GPIO132 MFP_CFG(GPIO132, AF0) | 144 | #define GPIO132_GPIO MFP_CFG(GPIO132, AF0) |
| 145 | #define GPIO133_GPIO133 MFP_CFG(GPIO133, AF0) | 145 | #define GPIO133_GPIO MFP_CFG(GPIO133, AF0) |
| 146 | #define GPIO134_GPIO134 MFP_CFG(GPIO134, AF0) | 146 | #define GPIO134_GPIO MFP_CFG(GPIO134, AF0) |
| 147 | #define GPIO135_GPIO135 MFP_CFG(GPIO135, AF0) | 147 | #define GPIO135_GPIO MFP_CFG(GPIO135, AF0) |
| 148 | #define GPIO136_GPIO136 MFP_CFG(GPIO136, AF0) | 148 | #define GPIO136_GPIO MFP_CFG(GPIO136, AF0) |
| 149 | #define GPIO137_GPIO137 MFP_CFG(GPIO137, AF0) | 149 | #define GPIO137_GPIO MFP_CFG(GPIO137, AF0) |
| 150 | #define GPIO138_GPIO138 MFP_CFG(GPIO138, AF0) | 150 | #define GPIO138_GPIO MFP_CFG(GPIO138, AF0) |
| 151 | #define GPIO139_GPIO139 MFP_CFG(GPIO139, AF0) | 151 | #define GPIO139_GPIO MFP_CFG(GPIO139, AF0) |
| 152 | #define GPIO140_GPIO140 MFP_CFG(GPIO140, AF0) | 152 | #define GPIO140_GPIO MFP_CFG(GPIO140, AF0) |
| 153 | #define GPIO141_GPIO141 MFP_CFG(GPIO141, AF0) | 153 | #define GPIO141_GPIO MFP_CFG(GPIO141, AF0) |
| 154 | #define GPIO142_GPIO142 MFP_CFG(GPIO142, AF1) | 154 | #define GPIO142_GPIO MFP_CFG(GPIO142, AF1) |
| 155 | #define GPIO143_GPIO143 MFP_CFG(GPIO143, AF1) | 155 | #define GPIO143_GPIO MFP_CFG(GPIO143, AF1) |
| 156 | #define GPIO144_GPIO144 MFP_CFG(GPIO144, AF1) | 156 | #define GPIO144_GPIO MFP_CFG(GPIO144, AF1) |
| 157 | #define GPIO145_GPIO145 MFP_CFG(GPIO145, AF1) | 157 | #define GPIO145_GPIO MFP_CFG(GPIO145, AF1) |
| 158 | #define GPIO146_GPIO146 MFP_CFG(GPIO146, AF1) | 158 | #define GPIO146_GPIO MFP_CFG(GPIO146, AF1) |
| 159 | #define GPIO147_GPIO147 MFP_CFG(GPIO147, AF1) | 159 | #define GPIO147_GPIO MFP_CFG(GPIO147, AF1) |
| 160 | #define GPIO148_GPIO148 MFP_CFG(GPIO148, AF1) | 160 | #define GPIO148_GPIO MFP_CFG(GPIO148, AF1) |
| 161 | #define GPIO149_GPIO149 MFP_CFG(GPIO149, AF1) | 161 | #define GPIO149_GPIO MFP_CFG(GPIO149, AF1) |
| 162 | #define GPIO150_GPIO150 MFP_CFG(GPIO150, AF1) | 162 | #define GPIO150_GPIO MFP_CFG(GPIO150, AF1) |
| 163 | #define GPIO151_GPIO151 MFP_CFG(GPIO151, AF1) | 163 | #define GPIO151_GPIO MFP_CFG(GPIO151, AF1) |
| 164 | #define GPIO152_GPIO152 MFP_CFG(GPIO152, AF1) | 164 | #define GPIO152_GPIO MFP_CFG(GPIO152, AF1) |
| 165 | #define GPIO153_GPIO153 MFP_CFG(GPIO153, AF1) | 165 | #define GPIO153_GPIO MFP_CFG(GPIO153, AF1) |
| 166 | #define GPIO154_GPIO154 MFP_CFG(GPIO154, AF1) | 166 | #define GPIO154_GPIO MFP_CFG(GPIO154, AF1) |
| 167 | #define GPIO155_GPIO155 MFP_CFG(GPIO155, AF1) | 167 | #define GPIO155_GPIO MFP_CFG(GPIO155, AF1) |
| 168 | #define GPIO156_GPIO156 MFP_CFG(GPIO156, AF1) | 168 | #define GPIO156_GPIO MFP_CFG(GPIO156, AF1) |
| 169 | #define GPIO157_GPIO157 MFP_CFG(GPIO157, AF1) | 169 | #define GPIO157_GPIO MFP_CFG(GPIO157, AF1) |
| 170 | #define GPIO158_GPIO158 MFP_CFG(GPIO158, AF1) | 170 | #define GPIO158_GPIO MFP_CFG(GPIO158, AF1) |
| 171 | #define GPIO159_GPIO159 MFP_CFG(GPIO159, AF1) | 171 | #define GPIO159_GPIO MFP_CFG(GPIO159, AF1) |
| 172 | #define GPIO160_GPIO160 MFP_CFG(GPIO160, AF1) | 172 | #define GPIO160_GPIO MFP_CFG(GPIO160, AF1) |
| 173 | #define GPIO161_GPIO161 MFP_CFG(GPIO161, AF1) | 173 | #define GPIO161_GPIO MFP_CFG(GPIO161, AF1) |
| 174 | #define GPIO162_GPIO162 MFP_CFG(GPIO162, AF1) | 174 | #define GPIO162_GPIO MFP_CFG(GPIO162, AF1) |
| 175 | #define GPIO163_GPIO163 MFP_CFG(GPIO163, AF1) | 175 | #define GPIO163_GPIO MFP_CFG(GPIO163, AF1) |
| 176 | #define GPIO164_GPIO164 MFP_CFG(GPIO164, AF1) | 176 | #define GPIO164_GPIO MFP_CFG(GPIO164, AF1) |
| 177 | #define GPIO165_GPIO165 MFP_CFG(GPIO165, AF1) | 177 | #define GPIO165_GPIO MFP_CFG(GPIO165, AF1) |
| 178 | #define GPIO166_GPIO166 MFP_CFG(GPIO166, AF1) | 178 | #define GPIO166_GPIO MFP_CFG(GPIO166, AF1) |
| 179 | #define GPIO167_GPIO167 MFP_CFG(GPIO167, AF1) | 179 | #define GPIO167_GPIO MFP_CFG(GPIO167, AF1) |
| 180 | #define GPIO168_GPIO168 MFP_CFG(GPIO168, AF1) | 180 | #define GPIO168_GPIO MFP_CFG(GPIO168, AF1) |
| 181 | 181 | ||
| 182 | /* DFI */ | 182 | /* DFI */ |
| 183 | #define GPIO108_DFI_D15 MFP_CFG(GPIO108, AF0) | 183 | #define GPIO108_DFI_D15 MFP_CFG(GPIO108, AF0) |
diff --git a/arch/arm/mach-mmp/include/mach/mmp2.h b/arch/arm/mach-mmp/include/mach/mmp2.h index dbba6e8a60c4..4aec493640b4 100644 --- a/arch/arm/mach-mmp/include/mach/mmp2.h +++ b/arch/arm/mach-mmp/include/mach/mmp2.h | |||
| @@ -1,6 +1,8 @@ | |||
| 1 | #ifndef __ASM_MACH_MMP2_H | 1 | #ifndef __ASM_MACH_MMP2_H |
| 2 | #define __ASM_MACH_MMP2_H | 2 | #define __ASM_MACH_MMP2_H |
| 3 | 3 | ||
| 4 | #include <plat/sdhci.h> | ||
| 5 | |||
| 4 | struct sys_timer; | 6 | struct sys_timer; |
| 5 | 7 | ||
| 6 | extern struct sys_timer mmp2_timer; | 8 | extern struct sys_timer mmp2_timer; |
| @@ -22,6 +24,10 @@ extern struct pxa_device_desc mmp2_device_twsi3; | |||
| 22 | extern struct pxa_device_desc mmp2_device_twsi4; | 24 | extern struct pxa_device_desc mmp2_device_twsi4; |
| 23 | extern struct pxa_device_desc mmp2_device_twsi5; | 25 | extern struct pxa_device_desc mmp2_device_twsi5; |
| 24 | extern struct pxa_device_desc mmp2_device_twsi6; | 26 | extern struct pxa_device_desc mmp2_device_twsi6; |
| 27 | extern struct pxa_device_desc mmp2_device_sdh0; | ||
| 28 | extern struct pxa_device_desc mmp2_device_sdh1; | ||
| 29 | extern struct pxa_device_desc mmp2_device_sdh2; | ||
| 30 | extern struct pxa_device_desc mmp2_device_sdh3; | ||
| 25 | 31 | ||
| 26 | static inline int mmp2_add_uart(int id) | 32 | static inline int mmp2_add_uart(int id) |
| 27 | { | 33 | { |
| @@ -63,5 +69,21 @@ static inline int mmp2_add_twsi(int id, struct i2c_pxa_platform_data *data, | |||
| 63 | return pxa_register_device(d, data, sizeof(*data)); | 69 | return pxa_register_device(d, data, sizeof(*data)); |
| 64 | } | 70 | } |
| 65 | 71 | ||
| 72 | static inline int mmp2_add_sdhost(int id, struct sdhci_pxa_platdata *data) | ||
| 73 | { | ||
| 74 | struct pxa_device_desc *d = NULL; | ||
| 75 | |||
| 76 | switch (id) { | ||
| 77 | case 0: d = &mmp2_device_sdh0; break; | ||
| 78 | case 1: d = &mmp2_device_sdh1; break; | ||
| 79 | case 2: d = &mmp2_device_sdh2; break; | ||
| 80 | case 3: d = &mmp2_device_sdh3; break; | ||
| 81 | default: | ||
| 82 | return -EINVAL; | ||
| 83 | } | ||
| 84 | |||
| 85 | return pxa_register_device(d, data, sizeof(*data)); | ||
| 86 | } | ||
| 87 | |||
| 66 | #endif /* __ASM_MACH_MMP2_H */ | 88 | #endif /* __ASM_MACH_MMP2_H */ |
| 67 | 89 | ||
diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h b/arch/arm/mach-mmp/include/mach/regs-apmu.h index ac4702357a6e..f7011ef70bf5 100644 --- a/arch/arm/mach-mmp/include/mach/regs-apmu.h +++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h | |||
| @@ -27,6 +27,8 @@ | |||
| 27 | #define APMU_DMA APMU_REG(0x064) | 27 | #define APMU_DMA APMU_REG(0x064) |
| 28 | #define APMU_GEU APMU_REG(0x068) | 28 | #define APMU_GEU APMU_REG(0x068) |
| 29 | #define APMU_BUS APMU_REG(0x06c) | 29 | #define APMU_BUS APMU_REG(0x06c) |
| 30 | #define APMU_SDH2 APMU_REG(0x0e8) | ||
| 31 | #define APMU_SDH3 APMU_REG(0x0ec) | ||
| 30 | 32 | ||
| 31 | #define APMU_FNCLK_EN (1 << 4) | 33 | #define APMU_FNCLK_EN (1 << 4) |
| 32 | #define APMU_AXICLK_EN (1 << 3) | 34 | #define APMU_AXICLK_EN (1 << 3) |
diff --git a/arch/arm/mach-mmp/jasper.c b/arch/arm/mach-mmp/jasper.c index 2a684fa50773..24172a0aad59 100644 --- a/arch/arm/mach-mmp/jasper.c +++ b/arch/arm/mach-mmp/jasper.c | |||
| @@ -67,6 +67,36 @@ static unsigned long jasper_pin_config[] __initdata = { | |||
| 67 | 67 | ||
| 68 | /* PMIC */ | 68 | /* PMIC */ |
| 69 | PMIC_PMIC_INT | MFP_LPM_EDGE_FALL, | 69 | PMIC_PMIC_INT | MFP_LPM_EDGE_FALL, |
| 70 | |||
| 71 | /* MMC1 */ | ||
| 72 | GPIO131_MMC1_DAT3, | ||
| 73 | GPIO132_MMC1_DAT2, | ||
| 74 | GPIO133_MMC1_DAT1, | ||
| 75 | GPIO134_MMC1_DAT0, | ||
| 76 | GPIO136_MMC1_CMD, | ||
| 77 | GPIO139_MMC1_CLK, | ||
| 78 | GPIO140_MMC1_CD, | ||
| 79 | GPIO141_MMC1_WP, | ||
| 80 | |||
| 81 | /* MMC2 */ | ||
| 82 | GPIO37_MMC2_DAT3, | ||
| 83 | GPIO38_MMC2_DAT2, | ||
| 84 | GPIO39_MMC2_DAT1, | ||
| 85 | GPIO40_MMC2_DAT0, | ||
| 86 | GPIO41_MMC2_CMD, | ||
| 87 | GPIO42_MMC2_CLK, | ||
| 88 | |||
| 89 | /* MMC3 */ | ||
| 90 | GPIO165_MMC3_DAT7, | ||
| 91 | GPIO162_MMC3_DAT6, | ||
| 92 | GPIO166_MMC3_DAT5, | ||
| 93 | GPIO163_MMC3_DAT4, | ||
| 94 | GPIO167_MMC3_DAT3, | ||
| 95 | GPIO164_MMC3_DAT2, | ||
| 96 | GPIO168_MMC3_DAT1, | ||
| 97 | GPIO111_MMC3_DAT0, | ||
| 98 | GPIO112_MMC3_CMD, | ||
| 99 | GPIO151_MMC3_CLK, | ||
| 70 | }; | 100 | }; |
| 71 | 101 | ||
| 72 | static struct regulator_consumer_supply max8649_supply[] = { | 102 | static struct regulator_consumer_supply max8649_supply[] = { |
| @@ -123,6 +153,10 @@ static struct i2c_board_info jasper_twsi1_info[] = { | |||
| 123 | }, | 153 | }, |
| 124 | }; | 154 | }; |
| 125 | 155 | ||
| 156 | static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc0 = { | ||
| 157 | .max_speed = 25000000, | ||
| 158 | }; | ||
| 159 | |||
| 126 | static void __init jasper_init(void) | 160 | static void __init jasper_init(void) |
| 127 | { | 161 | { |
| 128 | mfp_config(ARRAY_AND_SIZE(jasper_pin_config)); | 162 | mfp_config(ARRAY_AND_SIZE(jasper_pin_config)); |
| @@ -131,6 +165,7 @@ static void __init jasper_init(void) | |||
| 131 | mmp2_add_uart(1); | 165 | mmp2_add_uart(1); |
| 132 | mmp2_add_uart(3); | 166 | mmp2_add_uart(3); |
| 133 | mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(jasper_twsi1_info)); | 167 | mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(jasper_twsi1_info)); |
| 168 | mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */ | ||
| 134 | 169 | ||
| 135 | regulator_has_full_constraints(); | 170 | regulator_has_full_constraints(); |
| 136 | } | 171 | } |
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c index 2e3dd08ccc3f..8e6c3ac7f7c1 100644 --- a/arch/arm/mach-mmp/mmp2.c +++ b/arch/arm/mach-mmp/mmp2.c | |||
| @@ -115,6 +115,29 @@ void __init mmp2_init_irq(void) | |||
| 115 | mmp2_init_gpio(); | 115 | mmp2_init_gpio(); |
| 116 | } | 116 | } |
| 117 | 117 | ||
| 118 | static void sdhc_clk_enable(struct clk *clk) | ||
| 119 | { | ||
| 120 | uint32_t clk_rst; | ||
| 121 | |||
| 122 | clk_rst = __raw_readl(clk->clk_rst); | ||
| 123 | clk_rst |= clk->enable_val; | ||
| 124 | __raw_writel(clk_rst, clk->clk_rst); | ||
| 125 | } | ||
| 126 | |||
| 127 | static void sdhc_clk_disable(struct clk *clk) | ||
| 128 | { | ||
| 129 | uint32_t clk_rst; | ||
| 130 | |||
| 131 | clk_rst = __raw_readl(clk->clk_rst); | ||
| 132 | clk_rst &= ~clk->enable_val; | ||
| 133 | __raw_writel(clk_rst, clk->clk_rst); | ||
| 134 | } | ||
| 135 | |||
| 136 | struct clkops sdhc_clk_ops = { | ||
| 137 | .enable = sdhc_clk_enable, | ||
| 138 | .disable = sdhc_clk_disable, | ||
| 139 | }; | ||
| 140 | |||
| 118 | /* APB peripheral clocks */ | 141 | /* APB peripheral clocks */ |
| 119 | static APBC_CLK(uart1, MMP2_UART1, 1, 26000000); | 142 | static APBC_CLK(uart1, MMP2_UART1, 1, 26000000); |
| 120 | static APBC_CLK(uart2, MMP2_UART2, 1, 26000000); | 143 | static APBC_CLK(uart2, MMP2_UART2, 1, 26000000); |
| @@ -128,6 +151,10 @@ static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000); | |||
| 128 | static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000); | 151 | static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000); |
| 129 | 152 | ||
| 130 | static APMU_CLK(nand, NAND, 0xbf, 100000000); | 153 | static APMU_CLK(nand, NAND, 0xbf, 100000000); |
| 154 | static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops); | ||
| 155 | static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops); | ||
| 156 | static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops); | ||
| 157 | static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops); | ||
| 131 | 158 | ||
| 132 | static struct clk_lookup mmp2_clkregs[] = { | 159 | static struct clk_lookup mmp2_clkregs[] = { |
| 133 | INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), | 160 | INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), |
| @@ -141,6 +168,10 @@ static struct clk_lookup mmp2_clkregs[] = { | |||
| 141 | INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL), | 168 | INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL), |
| 142 | INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL), | 169 | INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL), |
| 143 | INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), | 170 | INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), |
| 171 | INIT_CLKREG(&clk_sdh0, "sdhci-pxa.0", "PXA-SDHCLK"), | ||
| 172 | INIT_CLKREG(&clk_sdh1, "sdhci-pxa.1", "PXA-SDHCLK"), | ||
| 173 | INIT_CLKREG(&clk_sdh2, "sdhci-pxa.2", "PXA-SDHCLK"), | ||
| 174 | INIT_CLKREG(&clk_sdh3, "sdhci-pxa.3", "PXA-SDHCLK"), | ||
| 144 | }; | 175 | }; |
| 145 | 176 | ||
| 146 | static int __init mmp2_init(void) | 177 | static int __init mmp2_init(void) |
| @@ -191,4 +222,8 @@ MMP2_DEVICE(twsi4, "pxa2xx-i2c", 3, TWSI4, 0xd4033000, 0x70); | |||
| 191 | MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70); | 222 | MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70); |
| 192 | MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70); | 223 | MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70); |
| 193 | MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29); | 224 | MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29); |
| 225 | MMP2_DEVICE(sdh0, "sdhci-pxa", 0, MMC, 0xd4280000, 0x120); | ||
| 226 | MMP2_DEVICE(sdh1, "sdhci-pxa", 1, MMC2, 0xd4280800, 0x120); | ||
| 227 | MMP2_DEVICE(sdh2, "sdhci-pxa", 2, MMC3, 0xd4281000, 0x120); | ||
| 228 | MMP2_DEVICE(sdh3, "sdhci-pxa", 3, MMC4, 0xd4281800, 0x120); | ||
| 194 | 229 | ||
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c index 46f2d69bef3c..8f92ccd26edf 100644 --- a/arch/arm/mach-mmp/pxa910.c +++ b/arch/arm/mach-mmp/pxa910.c | |||
| @@ -111,6 +111,7 @@ static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000); | |||
| 111 | static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000); | 111 | static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000); |
| 112 | 112 | ||
| 113 | static APMU_CLK(nand, NAND, 0x01db, 208000000); | 113 | static APMU_CLK(nand, NAND, 0x01db, 208000000); |
| 114 | static APMU_CLK(u2o, USB, 0x1b, 480000000); | ||
| 114 | 115 | ||
| 115 | /* device and clock bindings */ | 116 | /* device and clock bindings */ |
| 116 | static struct clk_lookup pxa910_clkregs[] = { | 117 | static struct clk_lookup pxa910_clkregs[] = { |
| @@ -123,6 +124,7 @@ static struct clk_lookup pxa910_clkregs[] = { | |||
| 123 | INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL), | 124 | INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL), |
| 124 | INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL), | 125 | INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL), |
| 125 | INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), | 126 | INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), |
| 127 | INIT_CLKREG(&clk_u2o, "pxa-u2o", "U2OCLK"), | ||
| 126 | }; | 128 | }; |
| 127 | 129 | ||
| 128 | static int __init pxa910_init(void) | 130 | static int __init pxa910_init(void) |
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c index 66528193f939..aeb9ae23e6ce 100644 --- a/arch/arm/mach-mmp/time.c +++ b/arch/arm/mach-mmp/time.c | |||
| @@ -26,8 +26,8 @@ | |||
| 26 | #include <linux/io.h> | 26 | #include <linux/io.h> |
| 27 | #include <linux/irq.h> | 27 | #include <linux/irq.h> |
| 28 | #include <linux/sched.h> | 28 | #include <linux/sched.h> |
| 29 | #include <linux/cnt32_to_63.h> | ||
| 30 | 29 | ||
| 30 | #include <asm/sched_clock.h> | ||
| 31 | #include <mach/addr-map.h> | 31 | #include <mach/addr-map.h> |
| 32 | #include <mach/regs-timers.h> | 32 | #include <mach/regs-timers.h> |
| 33 | #include <mach/regs-apbc.h> | 33 | #include <mach/regs-apbc.h> |
| @@ -42,23 +42,7 @@ | |||
| 42 | #define MAX_DELTA (0xfffffffe) | 42 | #define MAX_DELTA (0xfffffffe) |
| 43 | #define MIN_DELTA (16) | 43 | #define MIN_DELTA (16) |
| 44 | 44 | ||
| 45 | #define TCR2NS_SCALE_FACTOR 10 | 45 | static DEFINE_CLOCK_DATA(cd); |
| 46 | |||
| 47 | static unsigned long tcr2ns_scale; | ||
| 48 | |||
| 49 | static void __init set_tcr2ns_scale(unsigned long tcr_rate) | ||
| 50 | { | ||
| 51 | unsigned long long v = 1000000000ULL << TCR2NS_SCALE_FACTOR; | ||
| 52 | do_div(v, tcr_rate); | ||
| 53 | tcr2ns_scale = v; | ||
| 54 | /* | ||
| 55 | * We want an even value to automatically clear the top bit | ||
| 56 | * returned by cnt32_to_63() without an additional run time | ||
| 57 | * instruction. So if the LSB is 1 then round it up. | ||
| 58 | */ | ||
| 59 | if (tcr2ns_scale & 1) | ||
| 60 | tcr2ns_scale++; | ||
| 61 | } | ||
| 62 | 46 | ||
| 63 | /* | 47 | /* |
| 64 | * FIXME: the timer needs some delay to stablize the counter capture | 48 | * FIXME: the timer needs some delay to stablize the counter capture |
| @@ -75,10 +59,16 @@ static inline uint32_t timer_read(void) | |||
| 75 | return __raw_readl(TIMERS_VIRT_BASE + TMR_CVWR(0)); | 59 | return __raw_readl(TIMERS_VIRT_BASE + TMR_CVWR(0)); |
| 76 | } | 60 | } |
| 77 | 61 | ||
| 78 | unsigned long long sched_clock(void) | 62 | unsigned long long notrace sched_clock(void) |
| 79 | { | 63 | { |
| 80 | unsigned long long v = cnt32_to_63(timer_read()); | 64 | u32 cyc = timer_read(); |
| 81 | return (v * tcr2ns_scale) >> TCR2NS_SCALE_FACTOR; | 65 | return cyc_to_sched_clock(&cd, cyc, (u32)~0); |
| 66 | } | ||
| 67 | |||
| 68 | static void notrace mmp_update_sched_clock(void) | ||
| 69 | { | ||
| 70 | u32 cyc = timer_read(); | ||
| 71 | update_sched_clock(&cd, cyc, (u32)~0); | ||
| 82 | } | 72 | } |
| 83 | 73 | ||
| 84 | static irqreturn_t timer_interrupt(int irq, void *dev_id) | 74 | static irqreturn_t timer_interrupt(int irq, void *dev_id) |
| @@ -146,7 +136,6 @@ static cycle_t clksrc_read(struct clocksource *cs) | |||
| 146 | 136 | ||
| 147 | static struct clocksource cksrc = { | 137 | static struct clocksource cksrc = { |
| 148 | .name = "clocksource", | 138 | .name = "clocksource", |
| 149 | .shift = 20, | ||
| 150 | .rating = 200, | 139 | .rating = 200, |
| 151 | .read = clksrc_read, | 140 | .read = clksrc_read, |
| 152 | .mask = CLOCKSOURCE_MASK(32), | 141 | .mask = CLOCKSOURCE_MASK(32), |
| @@ -186,17 +175,15 @@ void __init timer_init(int irq) | |||
| 186 | { | 175 | { |
| 187 | timer_config(); | 176 | timer_config(); |
| 188 | 177 | ||
| 189 | set_tcr2ns_scale(CLOCK_TICK_RATE); | 178 | init_sched_clock(&cd, mmp_update_sched_clock, 32, CLOCK_TICK_RATE); |
| 190 | 179 | ||
| 191 | ckevt.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt.shift); | 180 | ckevt.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt.shift); |
| 192 | ckevt.max_delta_ns = clockevent_delta2ns(MAX_DELTA, &ckevt); | 181 | ckevt.max_delta_ns = clockevent_delta2ns(MAX_DELTA, &ckevt); |
| 193 | ckevt.min_delta_ns = clockevent_delta2ns(MIN_DELTA, &ckevt); | 182 | ckevt.min_delta_ns = clockevent_delta2ns(MIN_DELTA, &ckevt); |
| 194 | ckevt.cpumask = cpumask_of(0); | 183 | ckevt.cpumask = cpumask_of(0); |
| 195 | 184 | ||
| 196 | cksrc.mult = clocksource_hz2mult(CLOCK_TICK_RATE, cksrc.shift); | ||
| 197 | |||
| 198 | setup_irq(irq, &timer_irq); | 185 | setup_irq(irq, &timer_irq); |
| 199 | 186 | ||
| 200 | clocksource_register(&cksrc); | 187 | clocksource_register_hz(&cksrc, CLOCK_TICK_RATE); |
| 201 | clockevents_register_device(&ckevt); | 188 | clockevents_register_device(&ckevt); |
| 202 | } | 189 | } |
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index dbbcfeb919db..5d3d9ade12fb 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig | |||
| @@ -40,15 +40,20 @@ config ARCH_MSM8X60 | |||
| 40 | bool "MSM8X60" | 40 | bool "MSM8X60" |
| 41 | select MACH_MSM8X60_SURF if (!MACH_MSM8X60_RUMI3 && !MACH_MSM8X60_SIM \ | 41 | select MACH_MSM8X60_SURF if (!MACH_MSM8X60_RUMI3 && !MACH_MSM8X60_SIM \ |
| 42 | && !MACH_MSM8X60_FFA) | 42 | && !MACH_MSM8X60_FFA) |
| 43 | select ARCH_MSM_SCORPIONMP | ||
| 43 | select ARM_GIC | 44 | select ARM_GIC |
| 44 | select CPU_V7 | 45 | select CPU_V7 |
| 45 | select MSM_V2_TLMM | 46 | select MSM_V2_TLMM |
| 46 | select MSM_GPIOMUX | 47 | select MSM_GPIOMUX |
| 48 | select IOMMU_API | ||
| 49 | select MSM_SCM if SMP | ||
| 47 | 50 | ||
| 48 | endchoice | 51 | endchoice |
| 49 | 52 | ||
| 50 | config MSM_SOC_REV_A | 53 | config MSM_SOC_REV_A |
| 51 | bool | 54 | bool |
| 55 | config ARCH_MSM_SCORPIONMP | ||
| 56 | bool | ||
| 52 | 57 | ||
| 53 | config ARCH_MSM_ARM11 | 58 | config ARCH_MSM_ARM11 |
| 54 | bool | 59 | bool |
| @@ -122,6 +127,10 @@ config MACH_MSM8X60_FFA | |||
| 122 | 127 | ||
| 123 | endmenu | 128 | endmenu |
| 124 | 129 | ||
| 130 | config IOMMU_PGTABLES_L2 | ||
| 131 | def_bool y | ||
| 132 | depends on ARCH_MSM8X60 && MMU && SMP && CPU_DCACHE_DISABLE=n | ||
| 133 | |||
| 125 | config MSM_DEBUG_UART | 134 | config MSM_DEBUG_UART |
| 126 | int | 135 | int |
| 127 | default 1 if MSM_DEBUG_UART1 | 136 | default 1 if MSM_DEBUG_UART1 |
| @@ -162,4 +171,10 @@ config MSM_GPIOMUX | |||
| 162 | 171 | ||
| 163 | config MSM_V2_TLMM | 172 | config MSM_V2_TLMM |
| 164 | bool | 173 | bool |
| 174 | |||
| 175 | config IOMMU_API | ||
| 176 | bool | ||
| 177 | |||
| 178 | config MSM_SCM | ||
| 179 | bool | ||
| 165 | endif | 180 | endif |
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index b5a7b07a44f5..94195c190e13 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile | |||
| @@ -18,8 +18,13 @@ obj-$(CONFIG_MSM_PROC_COMM) += clock.o | |||
| 18 | obj-$(CONFIG_ARCH_QSD8X50) += sirc.o | 18 | obj-$(CONFIG_ARCH_QSD8X50) += sirc.o |
| 19 | obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o | 19 | obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o |
| 20 | obj-$(CONFIG_MSM_SMD) += last_radio_log.o | 20 | obj-$(CONFIG_MSM_SMD) += last_radio_log.o |
| 21 | obj-$(CONFIG_MSM_SCM) += scm.o scm-boot.o | ||
| 22 | |||
| 23 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o | ||
| 24 | obj-$(CONFIG_SMP) += headsmp.o platsmp.o | ||
| 21 | 25 | ||
| 22 | obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o devices-msm7x00.o | 26 | obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o devices-msm7x00.o |
| 27 | obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o board-trout-panel.o devices-msm7x00.o | ||
| 23 | obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o | 28 | obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o |
| 24 | obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o | 29 | obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o |
| 25 | obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o | 30 | obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o |
| @@ -28,6 +33,8 @@ obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o | |||
| 28 | obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-7x30.o gpiomux-v1.o gpiomux.o | 33 | obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-7x30.o gpiomux-v1.o gpiomux.o |
| 29 | obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o | 34 | obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o |
| 30 | obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o | 35 | obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o |
| 31 | ifndef CONFIG_MSM_V2_TLMM | 36 | ifdef CONFIG_MSM_V2_TLMM |
| 37 | obj-y += gpio-v2.o | ||
| 38 | else | ||
| 32 | obj-y += gpio.o | 39 | obj-y += gpio.o |
| 33 | endif | 40 | endif |
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c index 05241df3f9b6..6f3b9735e970 100644 --- a/arch/arm/mach-msm/board-msm7x30.c +++ b/arch/arm/mach-msm/board-msm7x30.c | |||
| @@ -22,6 +22,7 @@ | |||
| 22 | #include <linux/delay.h> | 22 | #include <linux/delay.h> |
| 23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
| 24 | #include <linux/smsc911x.h> | 24 | #include <linux/smsc911x.h> |
| 25 | #include <linux/usb/msm_hsusb.h> | ||
| 25 | 26 | ||
| 26 | #include <asm/mach-types.h> | 27 | #include <asm/mach-types.h> |
| 27 | #include <asm/mach/arch.h> | 28 | #include <asm/mach/arch.h> |
| @@ -39,11 +40,26 @@ | |||
| 39 | 40 | ||
| 40 | extern struct sys_timer msm_timer; | 41 | extern struct sys_timer msm_timer; |
| 41 | 42 | ||
| 43 | static int hsusb_phy_init_seq[] = { | ||
| 44 | 0x30, 0x32, /* Enable and set Pre-Emphasis Depth to 20% */ | ||
| 45 | 0x02, 0x36, /* Disable CDR Auto Reset feature */ | ||
| 46 | -1 | ||
| 47 | }; | ||
| 48 | |||
| 49 | static struct msm_otg_platform_data msm_otg_pdata = { | ||
| 50 | .phy_init_seq = hsusb_phy_init_seq, | ||
| 51 | .mode = USB_PERIPHERAL, | ||
| 52 | .otg_control = OTG_PHY_CONTROL, | ||
| 53 | }; | ||
| 54 | |||
| 42 | static struct platform_device *devices[] __initdata = { | 55 | static struct platform_device *devices[] __initdata = { |
| 43 | #if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER) | 56 | #if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER) |
| 44 | &msm_device_uart2, | 57 | &msm_device_uart2, |
| 45 | #endif | 58 | #endif |
| 46 | &msm_device_smd, | 59 | &msm_device_smd, |
| 60 | &msm_device_otg, | ||
| 61 | &msm_device_hsusb, | ||
| 62 | &msm_device_hsusb_host, | ||
| 47 | }; | 63 | }; |
| 48 | 64 | ||
| 49 | static void __init msm7x30_init_irq(void) | 65 | static void __init msm7x30_init_irq(void) |
| @@ -53,6 +69,10 @@ static void __init msm7x30_init_irq(void) | |||
| 53 | 69 | ||
| 54 | static void __init msm7x30_init(void) | 70 | static void __init msm7x30_init(void) |
| 55 | { | 71 | { |
| 72 | msm_device_otg.dev.platform_data = &msm_otg_pdata; | ||
| 73 | msm_device_hsusb.dev.parent = &msm_device_otg.dev; | ||
| 74 | msm_device_hsusb_host.dev.parent = &msm_device_otg.dev; | ||
| 75 | |||
| 56 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 76 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 57 | } | 77 | } |
| 58 | 78 | ||
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c index 7486a681cc71..9b5eb2b4ae1b 100644 --- a/arch/arm/mach-msm/board-msm8x60.c +++ b/arch/arm/mach-msm/board-msm8x60.c | |||
| @@ -28,8 +28,6 @@ | |||
| 28 | #include <mach/board.h> | 28 | #include <mach/board.h> |
| 29 | #include <mach/msm_iomap.h> | 29 | #include <mach/msm_iomap.h> |
| 30 | 30 | ||
| 31 | void __iomem *gic_cpu_base_addr; | ||
| 32 | |||
| 33 | unsigned long clk_get_max_axi_khz(void) | 31 | unsigned long clk_get_max_axi_khz(void) |
| 34 | { | 32 | { |
| 35 | return 0; | 33 | return 0; |
| @@ -44,9 +42,8 @@ static void __init msm8x60_init_irq(void) | |||
| 44 | { | 42 | { |
| 45 | unsigned int i; | 43 | unsigned int i; |
| 46 | 44 | ||
| 47 | gic_dist_init(0, MSM_QGIC_DIST_BASE, GIC_PPI_START); | 45 | gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, |
| 48 | gic_cpu_base_addr = (void *)MSM_QGIC_CPU_BASE; | 46 | (void *)MSM_QGIC_CPU_BASE); |
| 49 | gic_cpu_init(0, MSM_QGIC_CPU_BASE); | ||
| 50 | 47 | ||
| 51 | /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ | 48 | /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ |
| 52 | writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); | 49 | writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); |
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c index ed2af4ad97ed..2e8391307f55 100644 --- a/arch/arm/mach-msm/board-qsd8x50.c +++ b/arch/arm/mach-msm/board-qsd8x50.c | |||
| @@ -20,6 +20,7 @@ | |||
| 20 | #include <linux/gpio.h> | 20 | #include <linux/gpio.h> |
| 21 | #include <linux/platform_device.h> | 21 | #include <linux/platform_device.h> |
| 22 | #include <linux/delay.h> | 22 | #include <linux/delay.h> |
| 23 | #include <linux/usb/msm_hsusb.h> | ||
| 23 | 24 | ||
| 24 | #include <asm/mach-types.h> | 25 | #include <asm/mach-types.h> |
| 25 | #include <asm/mach/arch.h> | 26 | #include <asm/mach/arch.h> |
| @@ -74,9 +75,24 @@ static int __init msm_init_smc91x(void) | |||
| 74 | } | 75 | } |
| 75 | module_init(msm_init_smc91x); | 76 | module_init(msm_init_smc91x); |
| 76 | 77 | ||
| 78 | static int hsusb_phy_init_seq[] = { | ||
| 79 | 0x08, 0x31, /* Increase HS Driver Amplitude */ | ||
| 80 | 0x20, 0x32, /* Enable and set Pre-Emphasis Depth to 10% */ | ||
| 81 | -1 | ||
| 82 | }; | ||
| 83 | |||
| 84 | static struct msm_otg_platform_data msm_otg_pdata = { | ||
| 85 | .phy_init_seq = hsusb_phy_init_seq, | ||
| 86 | .mode = USB_PERIPHERAL, | ||
| 87 | .otg_control = OTG_PHY_CONTROL, | ||
| 88 | }; | ||
| 89 | |||
| 77 | static struct platform_device *devices[] __initdata = { | 90 | static struct platform_device *devices[] __initdata = { |
| 78 | &msm_device_uart3, | 91 | &msm_device_uart3, |
| 79 | &msm_device_smd, | 92 | &msm_device_smd, |
| 93 | &msm_device_otg, | ||
| 94 | &msm_device_hsusb, | ||
| 95 | &msm_device_hsusb_host, | ||
| 80 | }; | 96 | }; |
| 81 | 97 | ||
| 82 | static void __init qsd8x50_map_io(void) | 98 | static void __init qsd8x50_map_io(void) |
| @@ -93,6 +109,9 @@ static void __init qsd8x50_init_irq(void) | |||
| 93 | 109 | ||
| 94 | static void __init qsd8x50_init(void) | 110 | static void __init qsd8x50_init(void) |
| 95 | { | 111 | { |
| 112 | msm_device_otg.dev.platform_data = &msm_otg_pdata; | ||
| 113 | msm_device_hsusb.dev.parent = &msm_device_otg.dev; | ||
| 114 | msm_device_hsusb_host.dev.parent = &msm_device_otg.dev; | ||
| 96 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 115 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 97 | } | 116 | } |
| 98 | 117 | ||
diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c index c50f3afc3134..f8c09ef6666f 100644 --- a/arch/arm/mach-msm/board-trout-gpio.c +++ b/arch/arm/mach-msm/board-trout-gpio.c | |||
| @@ -72,6 +72,13 @@ static int msm_gpiolib_direction_output(struct gpio_chip *chip, | |||
| 72 | return 0; | 72 | return 0; |
| 73 | } | 73 | } |
| 74 | 74 | ||
| 75 | static int trout_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | ||
| 76 | { | ||
| 77 | struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip); | ||
| 78 | |||
| 79 | return TROUT_GPIO_TO_INT(offset + chip->base); | ||
| 80 | } | ||
| 81 | |||
| 75 | #define TROUT_GPIO_BANK(name, reg_num, base_gpio, shadow_val) \ | 82 | #define TROUT_GPIO_BANK(name, reg_num, base_gpio, shadow_val) \ |
| 76 | { \ | 83 | { \ |
| 77 | .chip = { \ | 84 | .chip = { \ |
| @@ -80,6 +87,7 @@ static int msm_gpiolib_direction_output(struct gpio_chip *chip, | |||
| 80 | .direction_output = msm_gpiolib_direction_output, \ | 87 | .direction_output = msm_gpiolib_direction_output, \ |
| 81 | .get = msm_gpiolib_get, \ | 88 | .get = msm_gpiolib_get, \ |
| 82 | .set = msm_gpiolib_set, \ | 89 | .set = msm_gpiolib_set, \ |
| 90 | .to_irq = trout_gpio_to_irq, \ | ||
| 83 | .base = base_gpio, \ | 91 | .base = base_gpio, \ |
| 84 | .ngpio = 8, \ | 92 | .ngpio = 8, \ |
| 85 | }, \ | 93 | }, \ |
diff --git a/arch/arm/mach-msm/board-trout-panel.c b/arch/arm/mach-msm/board-trout-panel.c new file mode 100644 index 000000000000..729bb49a44ca --- /dev/null +++ b/arch/arm/mach-msm/board-trout-panel.c | |||
| @@ -0,0 +1,297 @@ | |||
| 1 | /* linux/arch/arm/mach-msm/board-trout-mddi.c | ||
| 2 | ** Author: Brian Swetland <swetland@google.com> | ||
| 3 | */ | ||
| 4 | |||
| 5 | #include <linux/kernel.h> | ||
| 6 | #include <linux/init.h> | ||
| 7 | #include <linux/platform_device.h> | ||
| 8 | #include <linux/delay.h> | ||
| 9 | #include <linux/leds.h> | ||
| 10 | #include <linux/clk.h> | ||
| 11 | #include <linux/err.h> | ||
| 12 | |||
| 13 | #include <asm/io.h> | ||
| 14 | #include <asm/gpio.h> | ||
| 15 | #include <asm/mach-types.h> | ||
| 16 | |||
| 17 | #include <mach/msm_fb.h> | ||
| 18 | #include <mach/vreg.h> | ||
| 19 | |||
| 20 | #include "board-trout.h" | ||
| 21 | #include "proc_comm.h" | ||
| 22 | #include "devices.h" | ||
| 23 | |||
| 24 | #define TROUT_DEFAULT_BACKLIGHT_BRIGHTNESS 255 | ||
| 25 | |||
| 26 | #define MDDI_CLIENT_CORE_BASE 0x108000 | ||
| 27 | #define LCD_CONTROL_BLOCK_BASE 0x110000 | ||
| 28 | #define SPI_BLOCK_BASE 0x120000 | ||
| 29 | #define I2C_BLOCK_BASE 0x130000 | ||
| 30 | #define PWM_BLOCK_BASE 0x140000 | ||
| 31 | #define GPIO_BLOCK_BASE 0x150000 | ||
| 32 | #define SYSTEM_BLOCK1_BASE 0x160000 | ||
| 33 | #define SYSTEM_BLOCK2_BASE 0x170000 | ||
| 34 | |||
| 35 | |||
| 36 | #define DPSUS (MDDI_CLIENT_CORE_BASE|0x24) | ||
| 37 | #define SYSCLKENA (MDDI_CLIENT_CORE_BASE|0x2C) | ||
| 38 | #define PWM0OFF (PWM_BLOCK_BASE|0x1C) | ||
| 39 | |||
| 40 | #define V_VDDE2E_VDD2_GPIO 0 | ||
| 41 | #define MDDI_RST_N 82 | ||
| 42 | |||
| 43 | #define MDDICAP0 (MDDI_CLIENT_CORE_BASE|0x00) | ||
| 44 | #define MDDICAP1 (MDDI_CLIENT_CORE_BASE|0x04) | ||
| 45 | #define MDDICAP2 (MDDI_CLIENT_CORE_BASE|0x08) | ||
| 46 | #define MDDICAP3 (MDDI_CLIENT_CORE_BASE|0x0C) | ||
| 47 | #define MDCAPCHG (MDDI_CLIENT_CORE_BASE|0x10) | ||
| 48 | #define MDCRCERC (MDDI_CLIENT_CORE_BASE|0x14) | ||
| 49 | #define TTBUSSEL (MDDI_CLIENT_CORE_BASE|0x18) | ||
| 50 | #define DPSET0 (MDDI_CLIENT_CORE_BASE|0x1C) | ||
| 51 | #define DPSET1 (MDDI_CLIENT_CORE_BASE|0x20) | ||
| 52 | #define DPSUS (MDDI_CLIENT_CORE_BASE|0x24) | ||
| 53 | #define DPRUN (MDDI_CLIENT_CORE_BASE|0x28) | ||
| 54 | #define SYSCKENA (MDDI_CLIENT_CORE_BASE|0x2C) | ||
| 55 | #define TESTMODE (MDDI_CLIENT_CORE_BASE|0x30) | ||
| 56 | #define FIFOMONI (MDDI_CLIENT_CORE_BASE|0x34) | ||
| 57 | #define INTMONI (MDDI_CLIENT_CORE_BASE|0x38) | ||
| 58 | #define MDIOBIST (MDDI_CLIENT_CORE_BASE|0x3C) | ||
| 59 | #define MDIOPSET (MDDI_CLIENT_CORE_BASE|0x40) | ||
| 60 | #define BITMAP0 (MDDI_CLIENT_CORE_BASE|0x44) | ||
| 61 | #define BITMAP1 (MDDI_CLIENT_CORE_BASE|0x48) | ||
| 62 | #define BITMAP2 (MDDI_CLIENT_CORE_BASE|0x4C) | ||
| 63 | #define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50) | ||
| 64 | #define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54) | ||
| 65 | |||
| 66 | #define SRST (LCD_CONTROL_BLOCK_BASE|0x00) | ||
| 67 | #define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04) | ||
| 68 | #define START (LCD_CONTROL_BLOCK_BASE|0x08) | ||
| 69 | #define PORT (LCD_CONTROL_BLOCK_BASE|0x0C) | ||
| 70 | #define CMN (LCD_CONTROL_BLOCK_BASE|0x10) | ||
| 71 | #define GAMMA (LCD_CONTROL_BLOCK_BASE|0x14) | ||
| 72 | #define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18) | ||
| 73 | #define INTMSK (LCD_CONTROL_BLOCK_BASE|0x1C) | ||
| 74 | #define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20) | ||
| 75 | #define HDE_LEFT (LCD_CONTROL_BLOCK_BASE|0x24) | ||
| 76 | #define VDE_TOP (LCD_CONTROL_BLOCK_BASE|0x28) | ||
| 77 | #define PXL (LCD_CONTROL_BLOCK_BASE|0x30) | ||
| 78 | #define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34) | ||
| 79 | #define HSW (LCD_CONTROL_BLOCK_BASE|0x38) | ||
| 80 | #define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C) | ||
| 81 | #define HDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x40) | ||
| 82 | #define VCYCLE (LCD_CONTROL_BLOCK_BASE|0x44) | ||
| 83 | #define VSW (LCD_CONTROL_BLOCK_BASE|0x48) | ||
| 84 | #define VDE_START (LCD_CONTROL_BLOCK_BASE|0x4C) | ||
| 85 | #define VDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x50) | ||
| 86 | #define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54) | ||
| 87 | #define WSYN_DLY (LCD_CONTROL_BLOCK_BASE|0x58) | ||
| 88 | #define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C) | ||
| 89 | #define VSYNIF (LCD_CONTROL_BLOCK_BASE|0x60) | ||
| 90 | #define WRSTB (LCD_CONTROL_BLOCK_BASE|0x64) | ||
| 91 | #define RDSTB (LCD_CONTROL_BLOCK_BASE|0x68) | ||
| 92 | #define ASY_DATA (LCD_CONTROL_BLOCK_BASE|0x6C) | ||
| 93 | #define ASY_DATB (LCD_CONTROL_BLOCK_BASE|0x70) | ||
| 94 | #define ASY_DATC (LCD_CONTROL_BLOCK_BASE|0x74) | ||
| 95 | #define ASY_DATD (LCD_CONTROL_BLOCK_BASE|0x78) | ||
| 96 | #define ASY_DATE (LCD_CONTROL_BLOCK_BASE|0x7C) | ||
| 97 | #define ASY_DATF (LCD_CONTROL_BLOCK_BASE|0x80) | ||
| 98 | #define ASY_DATG (LCD_CONTROL_BLOCK_BASE|0x84) | ||
| 99 | #define ASY_DATH (LCD_CONTROL_BLOCK_BASE|0x88) | ||
| 100 | #define ASY_CMDSET (LCD_CONTROL_BLOCK_BASE|0x8C) | ||
| 101 | |||
| 102 | #define SSICTL (SPI_BLOCK_BASE|0x00) | ||
| 103 | #define SSITIME (SPI_BLOCK_BASE|0x04) | ||
| 104 | #define SSITX (SPI_BLOCK_BASE|0x08) | ||
| 105 | #define SSIRX (SPI_BLOCK_BASE|0x0C) | ||
| 106 | #define SSIINTC (SPI_BLOCK_BASE|0x10) | ||
| 107 | #define SSIINTS (SPI_BLOCK_BASE|0x14) | ||
| 108 | #define SSIDBG1 (SPI_BLOCK_BASE|0x18) | ||
| 109 | #define SSIDBG2 (SPI_BLOCK_BASE|0x1C) | ||
| 110 | #define SSIID (SPI_BLOCK_BASE|0x20) | ||
| 111 | |||
| 112 | #define WKREQ (SYSTEM_BLOCK1_BASE|0x00) | ||
| 113 | #define CLKENB (SYSTEM_BLOCK1_BASE|0x04) | ||
| 114 | #define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08) | ||
| 115 | #define INTMASK (SYSTEM_BLOCK1_BASE|0x0C) | ||
| 116 | #define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00) | ||
| 117 | |||
| 118 | #define GPIODATA (GPIO_BLOCK_BASE|0x00) | ||
| 119 | #define GPIODIR (GPIO_BLOCK_BASE|0x04) | ||
| 120 | #define GPIOIS (GPIO_BLOCK_BASE|0x08) | ||
| 121 | #define GPIOIBE (GPIO_BLOCK_BASE|0x0C) | ||
| 122 | #define GPIOIEV (GPIO_BLOCK_BASE|0x10) | ||
| 123 | #define GPIOIE (GPIO_BLOCK_BASE|0x14) | ||
| 124 | #define GPIORIS (GPIO_BLOCK_BASE|0x18) | ||
| 125 | #define GPIOMIS (GPIO_BLOCK_BASE|0x1C) | ||
| 126 | #define GPIOIC (GPIO_BLOCK_BASE|0x20) | ||
| 127 | #define GPIOOMS (GPIO_BLOCK_BASE|0x24) | ||
| 128 | #define GPIOPC (GPIO_BLOCK_BASE|0x28) | ||
| 129 | #define GPIOID (GPIO_BLOCK_BASE|0x30) | ||
| 130 | |||
| 131 | #define SPI_WRITE(reg, val) \ | ||
| 132 | { SSITX, 0x00010000 | (((reg) & 0xff) << 8) | ((val) & 0xff) }, \ | ||
| 133 | { 0, 5 }, | ||
| 134 | |||
| 135 | #define SPI_WRITE1(reg) \ | ||
| 136 | { SSITX, (reg) & 0xff }, \ | ||
| 137 | { 0, 5 }, | ||
| 138 | |||
| 139 | struct mddi_table { | ||
| 140 | uint32_t reg; | ||
| 141 | uint32_t value; | ||
| 142 | }; | ||
| 143 | static struct mddi_table mddi_toshiba_init_table[] = { | ||
| 144 | { DPSET0, 0x09e90046 }, | ||
| 145 | { DPSET1, 0x00000118 }, | ||
| 146 | { DPSUS, 0x00000000 }, | ||
| 147 | { DPRUN, 0x00000001 }, | ||
| 148 | { 1, 14 }, /* msleep 14 */ | ||
| 149 | { SYSCKENA, 0x00000001 }, | ||
| 150 | { CLKENB, 0x0000A1EF }, /* # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK) */ | ||
| 151 | |||
| 152 | { GPIODATA, 0x02000200 }, /* # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0 */ | ||
| 153 | { GPIODIR, 0x000030D }, /* 24D # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output) */ | ||
| 154 | { GPIOSEL, 0/*0x00000173*/}, /* # SYS.GPIOSEL # GPIO port multiplexing control */ | ||
| 155 | { GPIOPC, 0x03C300C0 }, /* # GPI .GPIOPC # GPIO2,3 PD cut */ | ||
| 156 | { WKREQ, 0x00000000 }, /* # SYS.WKREQ # Wake-up request event is VSYNC alignment */ | ||
| 157 | |||
| 158 | { GPIOIBE, 0x000003FF }, | ||
| 159 | { GPIOIS, 0x00000000 }, | ||
| 160 | { GPIOIC, 0x000003FF }, | ||
| 161 | { GPIOIE, 0x00000000 }, | ||
| 162 | |||
| 163 | { GPIODATA, 0x00040004 }, /* # GPI .GPIODATA # eDRAM VD supply */ | ||
| 164 | { 1, 1 }, /* msleep 1 */ | ||
| 165 | { GPIODATA, 0x02040004 }, /* # GPI .GPIODATA # eDRAM VD supply */ | ||
| 166 | { DRAMPWR, 0x00000001 }, /* eDRAM power */ | ||
| 167 | }; | ||
| 168 | |||
| 169 | #define GPIOSEL_VWAKEINT (1U << 0) | ||
| 170 | #define INTMASK_VWAKEOUT (1U << 0) | ||
| 171 | |||
| 172 | |||
| 173 | static struct clk *gp_clk; | ||
| 174 | static int trout_new_backlight = 1; | ||
| 175 | static struct vreg *vreg_mddi_1v5; | ||
| 176 | static struct vreg *vreg_lcm_2v85; | ||
| 177 | |||
| 178 | static void trout_process_mddi_table(struct msm_mddi_client_data *client_data, | ||
| 179 | struct mddi_table *table, size_t count) | ||
| 180 | { | ||
| 181 | int i; | ||
| 182 | for (i = 0; i < count; i++) { | ||
| 183 | uint32_t reg = table[i].reg; | ||
| 184 | uint32_t value = table[i].value; | ||
| 185 | |||
| 186 | if (reg == 0) | ||
| 187 | udelay(value); | ||
| 188 | else if (reg == 1) | ||
| 189 | msleep(value); | ||
| 190 | else | ||
| 191 | client_data->remote_write(client_data, value, reg); | ||
| 192 | } | ||
| 193 | } | ||
| 194 | |||
| 195 | static int trout_mddi_toshiba_client_init( | ||
| 196 | struct msm_mddi_bridge_platform_data *bridge_data, | ||
| 197 | struct msm_mddi_client_data *client_data) | ||
| 198 | { | ||
| 199 | int panel_id; | ||
| 200 | |||
| 201 | client_data->auto_hibernate(client_data, 0); | ||
| 202 | trout_process_mddi_table(client_data, mddi_toshiba_init_table, | ||
| 203 | ARRAY_SIZE(mddi_toshiba_init_table)); | ||
| 204 | client_data->auto_hibernate(client_data, 1); | ||
| 205 | panel_id = (client_data->remote_read(client_data, GPIODATA) >> 4) & 3; | ||
| 206 | if (panel_id > 1) { | ||
| 207 | printk(KERN_WARNING "unknown panel id at mddi_enable\n"); | ||
| 208 | return -1; | ||
| 209 | } | ||
| 210 | return 0; | ||
| 211 | } | ||
| 212 | |||
| 213 | static int trout_mddi_toshiba_client_uninit( | ||
| 214 | struct msm_mddi_bridge_platform_data *bridge_data, | ||
| 215 | struct msm_mddi_client_data *client_data) | ||
| 216 | { | ||
| 217 | return 0; | ||
| 218 | } | ||
| 219 | |||
| 220 | static struct resource resources_msm_fb[] = { | ||
| 221 | { | ||
| 222 | .start = MSM_FB_BASE, | ||
| 223 | .end = MSM_FB_BASE + MSM_FB_SIZE, | ||
| 224 | .flags = IORESOURCE_MEM, | ||
| 225 | }, | ||
| 226 | }; | ||
| 227 | |||
| 228 | struct msm_mddi_bridge_platform_data toshiba_client_data = { | ||
| 229 | .init = trout_mddi_toshiba_client_init, | ||
| 230 | .uninit = trout_mddi_toshiba_client_uninit, | ||
| 231 | .fb_data = { | ||
| 232 | .xres = 320, | ||
| 233 | .yres = 480, | ||
| 234 | .width = 45, | ||
| 235 | .height = 67, | ||
| 236 | .output_format = 0, | ||
| 237 | }, | ||
| 238 | }; | ||
| 239 | |||
| 240 | static struct msm_mddi_platform_data mddi_pdata = { | ||
| 241 | .clk_rate = 122880000, | ||
| 242 | .fb_resource = resources_msm_fb, | ||
| 243 | .num_clients = 1, | ||
| 244 | .client_platform_data = { | ||
| 245 | { | ||
| 246 | .product_id = (0xd263 << 16 | 0), | ||
| 247 | .name = "mddi_c_d263_0000", | ||
| 248 | .id = 0, | ||
| 249 | .client_data = &toshiba_client_data, | ||
| 250 | .clk_rate = 0, | ||
| 251 | }, | ||
| 252 | }, | ||
| 253 | }; | ||
| 254 | |||
| 255 | int __init trout_init_panel(void) | ||
| 256 | { | ||
| 257 | int rc; | ||
| 258 | |||
| 259 | if (!machine_is_trout()) | ||
| 260 | return 0; | ||
| 261 | vreg_mddi_1v5 = vreg_get(0, "gp2"); | ||
| 262 | if (IS_ERR(vreg_mddi_1v5)) | ||
| 263 | return PTR_ERR(vreg_mddi_1v5); | ||
| 264 | vreg_lcm_2v85 = vreg_get(0, "gp4"); | ||
| 265 | if (IS_ERR(vreg_lcm_2v85)) | ||
| 266 | return PTR_ERR(vreg_lcm_2v85); | ||
| 267 | |||
| 268 | trout_new_backlight = system_rev >= 5; | ||
| 269 | if (trout_new_backlight) { | ||
| 270 | uint32_t config = PCOM_GPIO_CFG(27, 0, GPIO_OUTPUT, | ||
| 271 | GPIO_NO_PULL, GPIO_8MA); | ||
| 272 | msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0); | ||
| 273 | } else { | ||
| 274 | uint32_t config = PCOM_GPIO_CFG(27, 1, GPIO_OUTPUT, | ||
| 275 | GPIO_NO_PULL, GPIO_8MA); | ||
| 276 | msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0); | ||
| 277 | |||
| 278 | gp_clk = clk_get(NULL, "gp_clk"); | ||
| 279 | if (IS_ERR(gp_clk)) { | ||
| 280 | printk(KERN_ERR "trout_init_panel: could not get gp" | ||
| 281 | "clock\n"); | ||
| 282 | gp_clk = NULL; | ||
| 283 | } | ||
| 284 | rc = clk_set_rate(gp_clk, 19200000); | ||
| 285 | if (rc) | ||
| 286 | printk(KERN_ERR "trout_init_panel: set clock rate " | ||
| 287 | "failed\n"); | ||
| 288 | } | ||
| 289 | |||
| 290 | rc = platform_device_register(&msm_device_mdp); | ||
| 291 | if (rc) | ||
| 292 | return rc; | ||
| 293 | msm_device_mddi0.dev.platform_data = &mddi_pdata; | ||
| 294 | return platform_device_register(&msm_device_mddi0); | ||
| 295 | } | ||
| 296 | |||
| 297 | device_initcall(trout_init_panel); | ||
diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c index c57210f4f06a..2069bfaa3a26 100644 --- a/arch/arm/mach-msm/clock.c +++ b/arch/arm/mach-msm/clock.c | |||
| @@ -120,6 +120,21 @@ EXPORT_SYMBOL(clk_get_rate); | |||
| 120 | 120 | ||
| 121 | int clk_set_rate(struct clk *clk, unsigned long rate) | 121 | int clk_set_rate(struct clk *clk, unsigned long rate) |
| 122 | { | 122 | { |
| 123 | int ret; | ||
| 124 | if (clk->flags & CLKFLAG_MAX) { | ||
| 125 | ret = clk->ops->set_max_rate(clk->id, rate); | ||
| 126 | if (ret) | ||
| 127 | return ret; | ||
| 128 | } | ||
| 129 | if (clk->flags & CLKFLAG_MIN) { | ||
| 130 | ret = clk->ops->set_min_rate(clk->id, rate); | ||
| 131 | if (ret) | ||
| 132 | return ret; | ||
| 133 | } | ||
| 134 | |||
| 135 | if (clk->flags & CLKFLAG_MAX || clk->flags & CLKFLAG_MIN) | ||
| 136 | return ret; | ||
| 137 | |||
| 123 | return clk->ops->set_rate(clk->id, rate); | 138 | return clk->ops->set_rate(clk->id, rate); |
| 124 | } | 139 | } |
| 125 | EXPORT_SYMBOL(clk_set_rate); | 140 | EXPORT_SYMBOL(clk_set_rate); |
diff --git a/arch/arm/mach-msm/devices-msm7x00.c b/arch/arm/mach-msm/devices-msm7x00.c index 4e8c0bcdc92d..fb548a8a21db 100644 --- a/arch/arm/mach-msm/devices-msm7x00.c +++ b/arch/arm/mach-msm/devices-msm7x00.c | |||
| @@ -347,6 +347,73 @@ int __init msm_add_sdcc(unsigned int controller, | |||
| 347 | return platform_device_register(pdev); | 347 | return platform_device_register(pdev); |
| 348 | } | 348 | } |
| 349 | 349 | ||
| 350 | static struct resource resources_mddi0[] = { | ||
| 351 | { | ||
| 352 | .start = MSM_PMDH_PHYS, | ||
| 353 | .end = MSM_PMDH_PHYS + MSM_PMDH_SIZE - 1, | ||
| 354 | .flags = IORESOURCE_MEM, | ||
| 355 | }, | ||
| 356 | { | ||
| 357 | .start = INT_MDDI_PRI, | ||
| 358 | .end = INT_MDDI_PRI, | ||
| 359 | .flags = IORESOURCE_IRQ, | ||
| 360 | }, | ||
| 361 | }; | ||
| 362 | |||
| 363 | static struct resource resources_mddi1[] = { | ||
| 364 | { | ||
| 365 | .start = MSM_EMDH_PHYS, | ||
| 366 | .end = MSM_EMDH_PHYS + MSM_EMDH_SIZE - 1, | ||
| 367 | .flags = IORESOURCE_MEM, | ||
| 368 | }, | ||
| 369 | { | ||
| 370 | .start = INT_MDDI_EXT, | ||
| 371 | .end = INT_MDDI_EXT, | ||
| 372 | .flags = IORESOURCE_IRQ, | ||
| 373 | }, | ||
| 374 | }; | ||
| 375 | |||
| 376 | struct platform_device msm_device_mddi0 = { | ||
| 377 | .name = "msm_mddi", | ||
| 378 | .id = 0, | ||
| 379 | .num_resources = ARRAY_SIZE(resources_mddi0), | ||
| 380 | .resource = resources_mddi0, | ||
| 381 | .dev = { | ||
| 382 | .coherent_dma_mask = 0xffffffff, | ||
| 383 | }, | ||
| 384 | }; | ||
| 385 | |||
| 386 | struct platform_device msm_device_mddi1 = { | ||
| 387 | .name = "msm_mddi", | ||
| 388 | .id = 1, | ||
| 389 | .num_resources = ARRAY_SIZE(resources_mddi1), | ||
| 390 | .resource = resources_mddi1, | ||
| 391 | .dev = { | ||
| 392 | .coherent_dma_mask = 0xffffffff, | ||
| 393 | }, | ||
| 394 | }; | ||
| 395 | |||
| 396 | static struct resource resources_mdp[] = { | ||
| 397 | { | ||
| 398 | .start = MSM_MDP_PHYS, | ||
| 399 | .end = MSM_MDP_PHYS + MSM_MDP_SIZE - 1, | ||
| 400 | .name = "mdp", | ||
| 401 | .flags = IORESOURCE_MEM | ||
| 402 | }, | ||
| 403 | { | ||
| 404 | .start = INT_MDP, | ||
| 405 | .end = INT_MDP, | ||
| 406 | .flags = IORESOURCE_IRQ, | ||
| 407 | }, | ||
| 408 | }; | ||
| 409 | |||
| 410 | struct platform_device msm_device_mdp = { | ||
| 411 | .name = "msm_mdp", | ||
| 412 | .id = 0, | ||
| 413 | .num_resources = ARRAY_SIZE(resources_mdp), | ||
| 414 | .resource = resources_mdp, | ||
| 415 | }; | ||
| 416 | |||
| 350 | struct clk msm_clocks_7x01a[] = { | 417 | struct clk msm_clocks_7x01a[] = { |
| 351 | CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), | 418 | CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), |
| 352 | CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0), | 419 | CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0), |
| @@ -364,7 +431,7 @@ struct clk msm_clocks_7x01a[] = { | |||
| 364 | CLK_PCOM("mdp_clk", MDP_CLK, NULL, OFF), | 431 | CLK_PCOM("mdp_clk", MDP_CLK, NULL, OFF), |
| 365 | CLK_PCOM("pbus_clk", PBUS_CLK, NULL, 0), | 432 | CLK_PCOM("pbus_clk", PBUS_CLK, NULL, 0), |
| 366 | CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0), | 433 | CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0), |
| 367 | CLK_PCOM("pmdh_clk", PMDH_CLK, NULL, OFF ), | 434 | CLK_PCOM("mddi_clk", PMDH_CLK, NULL, OFF | CLK_MINMAX), |
| 368 | CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF), | 435 | CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF), |
| 369 | CLK_PCOM("sdc_clk", SDC1_CLK, &msm_device_sdc1.dev, OFF), | 436 | CLK_PCOM("sdc_clk", SDC1_CLK, &msm_device_sdc1.dev, OFF), |
| 370 | CLK_PCOM("sdc_pclk", SDC1_P_CLK, &msm_device_sdc1.dev, OFF), | 437 | CLK_PCOM("sdc_pclk", SDC1_P_CLK, &msm_device_sdc1.dev, OFF), |
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c index 7fcf2e3b7698..4e9a0ab3e937 100644 --- a/arch/arm/mach-msm/devices-msm7x30.c +++ b/arch/arm/mach-msm/devices-msm7x30.c | |||
| @@ -56,6 +56,77 @@ struct platform_device msm_device_smd = { | |||
| 56 | .id = -1, | 56 | .id = -1, |
| 57 | }; | 57 | }; |
| 58 | 58 | ||
| 59 | static struct resource resources_otg[] = { | ||
| 60 | { | ||
| 61 | .start = MSM_HSUSB_PHYS, | ||
| 62 | .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE, | ||
| 63 | .flags = IORESOURCE_MEM, | ||
| 64 | }, | ||
| 65 | { | ||
| 66 | .start = INT_USB_HS, | ||
| 67 | .end = INT_USB_HS, | ||
| 68 | .flags = IORESOURCE_IRQ, | ||
| 69 | }, | ||
| 70 | }; | ||
| 71 | |||
| 72 | struct platform_device msm_device_otg = { | ||
| 73 | .name = "msm_otg", | ||
| 74 | .id = -1, | ||
| 75 | .num_resources = ARRAY_SIZE(resources_otg), | ||
| 76 | .resource = resources_otg, | ||
| 77 | .dev = { | ||
| 78 | .coherent_dma_mask = 0xffffffff, | ||
| 79 | }, | ||
| 80 | }; | ||
| 81 | |||
| 82 | static struct resource resources_hsusb[] = { | ||
| 83 | { | ||
| 84 | .start = MSM_HSUSB_PHYS, | ||
| 85 | .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE, | ||
| 86 | .flags = IORESOURCE_MEM, | ||
| 87 | }, | ||
| 88 | { | ||
| 89 | .start = INT_USB_HS, | ||
| 90 | .end = INT_USB_HS, | ||
| 91 | .flags = IORESOURCE_IRQ, | ||
| 92 | }, | ||
| 93 | }; | ||
| 94 | |||
| 95 | struct platform_device msm_device_hsusb = { | ||
| 96 | .name = "msm_hsusb", | ||
| 97 | .id = -1, | ||
| 98 | .num_resources = ARRAY_SIZE(resources_hsusb), | ||
| 99 | .resource = resources_hsusb, | ||
| 100 | .dev = { | ||
| 101 | .coherent_dma_mask = 0xffffffff, | ||
| 102 | }, | ||
| 103 | }; | ||
| 104 | |||
| 105 | static u64 dma_mask = 0xffffffffULL; | ||
| 106 | static struct resource resources_hsusb_host[] = { | ||
| 107 | { | ||
| 108 | .start = MSM_HSUSB_PHYS, | ||
| 109 | .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE, | ||
| 110 | .flags = IORESOURCE_MEM, | ||
| 111 | }, | ||
| 112 | { | ||
| 113 | .start = INT_USB_HS, | ||
| 114 | .end = INT_USB_HS, | ||
| 115 | .flags = IORESOURCE_IRQ, | ||
| 116 | }, | ||
| 117 | }; | ||
| 118 | |||
| 119 | struct platform_device msm_device_hsusb_host = { | ||
| 120 | .name = "msm_hsusb_host", | ||
| 121 | .id = -1, | ||
| 122 | .num_resources = ARRAY_SIZE(resources_hsusb_host), | ||
| 123 | .resource = resources_hsusb_host, | ||
| 124 | .dev = { | ||
| 125 | .dma_mask = &dma_mask, | ||
| 126 | .coherent_dma_mask = 0xffffffffULL, | ||
| 127 | }, | ||
| 128 | }; | ||
| 129 | |||
| 59 | struct clk msm_clocks_7x30[] = { | 130 | struct clk msm_clocks_7x30[] = { |
| 60 | CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), | 131 | CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), |
| 61 | CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0), | 132 | CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0), |
| @@ -107,6 +178,7 @@ struct clk msm_clocks_7x30[] = { | |||
| 107 | CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0), | 178 | CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0), |
| 108 | CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0), | 179 | CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0), |
| 109 | CLK_PCOM("uart_clk", UART2_CLK, &msm_device_uart2.dev, 0), | 180 | CLK_PCOM("uart_clk", UART2_CLK, &msm_device_uart2.dev, 0), |
| 181 | CLK_PCOM("usb_phy_clk", USB_PHY_CLK, NULL, 0), | ||
| 110 | CLK_PCOM("usb_hs_clk", USB_HS_CLK, NULL, OFF), | 182 | CLK_PCOM("usb_hs_clk", USB_HS_CLK, NULL, OFF), |
| 111 | CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, NULL, OFF), | 183 | CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, NULL, OFF), |
| 112 | CLK_PCOM("usb_hs_core_clk", USB_HS_CORE_CLK, NULL, OFF), | 184 | CLK_PCOM("usb_hs_core_clk", USB_HS_CORE_CLK, NULL, OFF), |
diff --git a/arch/arm/mach-msm/devices-msm8x60-iommu.c b/arch/arm/mach-msm/devices-msm8x60-iommu.c index 89b9d4437e92..f9e7bd34ec59 100644 --- a/arch/arm/mach-msm/devices-msm8x60-iommu.c +++ b/arch/arm/mach-msm/devices-msm8x60-iommu.c | |||
| @@ -254,60 +254,86 @@ static struct resource msm_iommu_gfx2d0_resources[] = { | |||
| 254 | }, | 254 | }, |
| 255 | }; | 255 | }; |
| 256 | 256 | ||
| 257 | static struct resource msm_iommu_gfx2d1_resources[] = { | ||
| 258 | { | ||
| 259 | .start = MSM_IOMMU_GFX2D1_PHYS, | ||
| 260 | .end = MSM_IOMMU_GFX2D1_PHYS + MSM_IOMMU_GFX2D1_SIZE - 1, | ||
| 261 | .name = "physbase", | ||
| 262 | .flags = IORESOURCE_MEM, | ||
| 263 | }, | ||
| 264 | { | ||
| 265 | .name = "nonsecure_irq", | ||
| 266 | .start = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ, | ||
| 267 | .end = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ, | ||
| 268 | .flags = IORESOURCE_IRQ, | ||
| 269 | }, | ||
| 270 | { | ||
| 271 | .name = "secure_irq", | ||
| 272 | .start = SMMU_GFX2D1_CB_SC_SECURE_IRQ, | ||
| 273 | .end = SMMU_GFX2D1_CB_SC_SECURE_IRQ, | ||
| 274 | .flags = IORESOURCE_IRQ, | ||
| 275 | }, | ||
| 276 | }; | ||
| 277 | |||
| 257 | static struct platform_device msm_root_iommu_dev = { | 278 | static struct platform_device msm_root_iommu_dev = { |
| 258 | .name = "msm_iommu", | 279 | .name = "msm_iommu", |
| 259 | .id = -1, | 280 | .id = -1, |
| 260 | }; | 281 | }; |
| 261 | 282 | ||
| 262 | static struct msm_iommu_dev jpegd_smmu = { | 283 | static struct msm_iommu_dev jpegd_iommu = { |
| 263 | .name = "jpegd", | 284 | .name = "jpegd", |
| 264 | .clk_rate = -1 | 285 | .clk_rate = -1 |
| 265 | }; | 286 | }; |
| 266 | 287 | ||
| 267 | static struct msm_iommu_dev vpe_smmu = { | 288 | static struct msm_iommu_dev vpe_iommu = { |
| 268 | .name = "vpe" | 289 | .name = "vpe" |
| 269 | }; | 290 | }; |
| 270 | 291 | ||
| 271 | static struct msm_iommu_dev mdp0_smmu = { | 292 | static struct msm_iommu_dev mdp0_iommu = { |
| 272 | .name = "mdp0" | 293 | .name = "mdp0" |
| 273 | }; | 294 | }; |
| 274 | 295 | ||
| 275 | static struct msm_iommu_dev mdp1_smmu = { | 296 | static struct msm_iommu_dev mdp1_iommu = { |
| 276 | .name = "mdp1" | 297 | .name = "mdp1" |
| 277 | }; | 298 | }; |
| 278 | 299 | ||
| 279 | static struct msm_iommu_dev rot_smmu = { | 300 | static struct msm_iommu_dev rot_iommu = { |
| 280 | .name = "rot" | 301 | .name = "rot" |
| 281 | }; | 302 | }; |
| 282 | 303 | ||
| 283 | static struct msm_iommu_dev ijpeg_smmu = { | 304 | static struct msm_iommu_dev ijpeg_iommu = { |
| 284 | .name = "ijpeg" | 305 | .name = "ijpeg" |
| 285 | }; | 306 | }; |
| 286 | 307 | ||
| 287 | static struct msm_iommu_dev vfe_smmu = { | 308 | static struct msm_iommu_dev vfe_iommu = { |
| 288 | .name = "vfe", | 309 | .name = "vfe", |
| 289 | .clk_rate = -1 | 310 | .clk_rate = -1 |
| 290 | }; | 311 | }; |
| 291 | 312 | ||
| 292 | static struct msm_iommu_dev vcodec_a_smmu = { | 313 | static struct msm_iommu_dev vcodec_a_iommu = { |
| 293 | .name = "vcodec_a" | 314 | .name = "vcodec_a" |
| 294 | }; | 315 | }; |
| 295 | 316 | ||
| 296 | static struct msm_iommu_dev vcodec_b_smmu = { | 317 | static struct msm_iommu_dev vcodec_b_iommu = { |
| 297 | .name = "vcodec_b" | 318 | .name = "vcodec_b" |
| 298 | }; | 319 | }; |
| 299 | 320 | ||
| 300 | static struct msm_iommu_dev gfx3d_smmu = { | 321 | static struct msm_iommu_dev gfx3d_iommu = { |
| 301 | .name = "gfx3d", | 322 | .name = "gfx3d", |
| 302 | .clk_rate = 27000000 | 323 | .clk_rate = 27000000 |
| 303 | }; | 324 | }; |
| 304 | 325 | ||
| 305 | static struct msm_iommu_dev gfx2d0_smmu = { | 326 | static struct msm_iommu_dev gfx2d0_iommu = { |
| 306 | .name = "gfx2d0", | 327 | .name = "gfx2d0", |
| 307 | .clk_rate = 27000000 | 328 | .clk_rate = 27000000 |
| 308 | }; | 329 | }; |
| 309 | 330 | ||
| 310 | static struct platform_device msm_device_smmu_jpegd = { | 331 | static struct msm_iommu_dev gfx2d1_iommu = { |
| 332 | .name = "gfx2d1", | ||
| 333 | .clk_rate = 27000000 | ||
| 334 | }; | ||
| 335 | |||
| 336 | static struct platform_device msm_device_iommu_jpegd = { | ||
| 311 | .name = "msm_iommu", | 337 | .name = "msm_iommu", |
| 312 | .id = 0, | 338 | .id = 0, |
| 313 | .dev = { | 339 | .dev = { |
| @@ -317,7 +343,7 @@ static struct platform_device msm_device_smmu_jpegd = { | |||
| 317 | .resource = msm_iommu_jpegd_resources, | 343 | .resource = msm_iommu_jpegd_resources, |
| 318 | }; | 344 | }; |
| 319 | 345 | ||
| 320 | static struct platform_device msm_device_smmu_vpe = { | 346 | static struct platform_device msm_device_iommu_vpe = { |
| 321 | .name = "msm_iommu", | 347 | .name = "msm_iommu", |
| 322 | .id = 1, | 348 | .id = 1, |
| 323 | .dev = { | 349 | .dev = { |
| @@ -327,7 +353,7 @@ static struct platform_device msm_device_smmu_vpe = { | |||
| 327 | .resource = msm_iommu_vpe_resources, | 353 | .resource = msm_iommu_vpe_resources, |
| 328 | }; | 354 | }; |
| 329 | 355 | ||
| 330 | static struct platform_device msm_device_smmu_mdp0 = { | 356 | static struct platform_device msm_device_iommu_mdp0 = { |
| 331 | .name = "msm_iommu", | 357 | .name = "msm_iommu", |
| 332 | .id = 2, | 358 | .id = 2, |
| 333 | .dev = { | 359 | .dev = { |
| @@ -337,7 +363,7 @@ static struct platform_device msm_device_smmu_mdp0 = { | |||
| 337 | .resource = msm_iommu_mdp0_resources, | 363 | .resource = msm_iommu_mdp0_resources, |
| 338 | }; | 364 | }; |
| 339 | 365 | ||
| 340 | static struct platform_device msm_device_smmu_mdp1 = { | 366 | static struct platform_device msm_device_iommu_mdp1 = { |
| 341 | .name = "msm_iommu", | 367 | .name = "msm_iommu", |
| 342 | .id = 3, | 368 | .id = 3, |
| 343 | .dev = { | 369 | .dev = { |
| @@ -347,7 +373,7 @@ static struct platform_device msm_device_smmu_mdp1 = { | |||
| 347 | .resource = msm_iommu_mdp1_resources, | 373 | .resource = msm_iommu_mdp1_resources, |
| 348 | }; | 374 | }; |
| 349 | 375 | ||
| 350 | static struct platform_device msm_device_smmu_rot = { | 376 | static struct platform_device msm_device_iommu_rot = { |
| 351 | .name = "msm_iommu", | 377 | .name = "msm_iommu", |
| 352 | .id = 4, | 378 | .id = 4, |
| 353 | .dev = { | 379 | .dev = { |
| @@ -357,7 +383,7 @@ static struct platform_device msm_device_smmu_rot = { | |||
| 357 | .resource = msm_iommu_rot_resources, | 383 | .resource = msm_iommu_rot_resources, |
| 358 | }; | 384 | }; |
| 359 | 385 | ||
| 360 | static struct platform_device msm_device_smmu_ijpeg = { | 386 | static struct platform_device msm_device_iommu_ijpeg = { |
| 361 | .name = "msm_iommu", | 387 | .name = "msm_iommu", |
| 362 | .id = 5, | 388 | .id = 5, |
| 363 | .dev = { | 389 | .dev = { |
| @@ -367,7 +393,7 @@ static struct platform_device msm_device_smmu_ijpeg = { | |||
| 367 | .resource = msm_iommu_ijpeg_resources, | 393 | .resource = msm_iommu_ijpeg_resources, |
| 368 | }; | 394 | }; |
| 369 | 395 | ||
| 370 | static struct platform_device msm_device_smmu_vfe = { | 396 | static struct platform_device msm_device_iommu_vfe = { |
| 371 | .name = "msm_iommu", | 397 | .name = "msm_iommu", |
| 372 | .id = 6, | 398 | .id = 6, |
| 373 | .dev = { | 399 | .dev = { |
| @@ -377,7 +403,7 @@ static struct platform_device msm_device_smmu_vfe = { | |||
| 377 | .resource = msm_iommu_vfe_resources, | 403 | .resource = msm_iommu_vfe_resources, |
| 378 | }; | 404 | }; |
| 379 | 405 | ||
| 380 | static struct platform_device msm_device_smmu_vcodec_a = { | 406 | static struct platform_device msm_device_iommu_vcodec_a = { |
| 381 | .name = "msm_iommu", | 407 | .name = "msm_iommu", |
| 382 | .id = 7, | 408 | .id = 7, |
| 383 | .dev = { | 409 | .dev = { |
| @@ -387,7 +413,7 @@ static struct platform_device msm_device_smmu_vcodec_a = { | |||
| 387 | .resource = msm_iommu_vcodec_a_resources, | 413 | .resource = msm_iommu_vcodec_a_resources, |
| 388 | }; | 414 | }; |
| 389 | 415 | ||
| 390 | static struct platform_device msm_device_smmu_vcodec_b = { | 416 | static struct platform_device msm_device_iommu_vcodec_b = { |
| 391 | .name = "msm_iommu", | 417 | .name = "msm_iommu", |
| 392 | .id = 8, | 418 | .id = 8, |
| 393 | .dev = { | 419 | .dev = { |
| @@ -397,7 +423,7 @@ static struct platform_device msm_device_smmu_vcodec_b = { | |||
| 397 | .resource = msm_iommu_vcodec_b_resources, | 423 | .resource = msm_iommu_vcodec_b_resources, |
| 398 | }; | 424 | }; |
| 399 | 425 | ||
| 400 | static struct platform_device msm_device_smmu_gfx3d = { | 426 | static struct platform_device msm_device_iommu_gfx3d = { |
| 401 | .name = "msm_iommu", | 427 | .name = "msm_iommu", |
| 402 | .id = 9, | 428 | .id = 9, |
| 403 | .dev = { | 429 | .dev = { |
| @@ -407,7 +433,7 @@ static struct platform_device msm_device_smmu_gfx3d = { | |||
| 407 | .resource = msm_iommu_gfx3d_resources, | 433 | .resource = msm_iommu_gfx3d_resources, |
| 408 | }; | 434 | }; |
| 409 | 435 | ||
| 410 | static struct platform_device msm_device_smmu_gfx2d0 = { | 436 | static struct platform_device msm_device_iommu_gfx2d0 = { |
| 411 | .name = "msm_iommu", | 437 | .name = "msm_iommu", |
| 412 | .id = 10, | 438 | .id = 10, |
| 413 | .dev = { | 439 | .dev = { |
| @@ -417,6 +443,16 @@ static struct platform_device msm_device_smmu_gfx2d0 = { | |||
| 417 | .resource = msm_iommu_gfx2d0_resources, | 443 | .resource = msm_iommu_gfx2d0_resources, |
| 418 | }; | 444 | }; |
| 419 | 445 | ||
| 446 | struct platform_device msm_device_iommu_gfx2d1 = { | ||
| 447 | .name = "msm_iommu", | ||
| 448 | .id = 11, | ||
| 449 | .dev = { | ||
| 450 | .parent = &msm_root_iommu_dev.dev, | ||
| 451 | }, | ||
| 452 | .num_resources = ARRAY_SIZE(msm_iommu_gfx2d1_resources), | ||
| 453 | .resource = msm_iommu_gfx2d1_resources, | ||
| 454 | }; | ||
| 455 | |||
| 420 | static struct msm_iommu_ctx_dev jpegd_src_ctx = { | 456 | static struct msm_iommu_ctx_dev jpegd_src_ctx = { |
| 421 | .name = "jpegd_src", | 457 | .name = "jpegd_src", |
| 422 | .num = 0, | 458 | .num = 0, |
| @@ -519,41 +555,36 @@ static struct msm_iommu_ctx_dev vcodec_b_mm2_ctx = { | |||
| 519 | .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1} | 555 | .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1} |
| 520 | }; | 556 | }; |
| 521 | 557 | ||
| 522 | static struct msm_iommu_ctx_dev gfx3d_rbpa_ctx = { | 558 | static struct msm_iommu_ctx_dev gfx3d_user_ctx = { |
| 523 | .name = "gfx3d_rbpa", | 559 | .name = "gfx3d_user", |
| 524 | .num = 0, | 560 | .num = 0, |
| 525 | .mids = {-1} | 561 | .mids = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1} |
| 526 | }; | 562 | }; |
| 527 | 563 | ||
| 528 | static struct msm_iommu_ctx_dev gfx3d_cpvgttc_ctx = { | 564 | static struct msm_iommu_ctx_dev gfx3d_priv_ctx = { |
| 529 | .name = "gfx3d_cpvgttc", | 565 | .name = "gfx3d_priv", |
| 530 | .num = 1, | 566 | .num = 1, |
| 531 | .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1} | 567 | .mids = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, |
| 532 | }; | 568 | 31, -1} |
| 533 | |||
| 534 | static struct msm_iommu_ctx_dev gfx3d_smmu_ctx = { | ||
| 535 | .name = "gfx3d_smmu", | ||
| 536 | .num = 2, | ||
| 537 | .mids = {8, 9, 10, 11, 12, -1} | ||
| 538 | }; | 569 | }; |
| 539 | 570 | ||
| 540 | static struct msm_iommu_ctx_dev gfx2d0_pixv1_ctx = { | 571 | static struct msm_iommu_ctx_dev gfx2d0_2d0_ctx = { |
| 541 | .name = "gfx2d0_pixv1_smmu", | 572 | .name = "gfx2d0_2d0", |
| 542 | .num = 0, | 573 | .num = 0, |
| 543 | .mids = {0, 3, 4, -1} | 574 | .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1} |
| 544 | }; | 575 | }; |
| 545 | 576 | ||
| 546 | static struct msm_iommu_ctx_dev gfx2d0_texv3_ctx = { | 577 | static struct msm_iommu_ctx_dev gfx2d1_2d1_ctx = { |
| 547 | .name = "gfx2d0_texv3_smmu", | 578 | .name = "gfx2d1_2d1", |
| 548 | .num = 1, | 579 | .num = 0, |
| 549 | .mids = {1, 6, 7, -1} | 580 | .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1} |
| 550 | }; | 581 | }; |
| 551 | 582 | ||
| 552 | static struct platform_device msm_device_jpegd_src_ctx = { | 583 | static struct platform_device msm_device_jpegd_src_ctx = { |
| 553 | .name = "msm_iommu_ctx", | 584 | .name = "msm_iommu_ctx", |
| 554 | .id = 0, | 585 | .id = 0, |
| 555 | .dev = { | 586 | .dev = { |
| 556 | .parent = &msm_device_smmu_jpegd.dev, | 587 | .parent = &msm_device_iommu_jpegd.dev, |
| 557 | }, | 588 | }, |
| 558 | }; | 589 | }; |
| 559 | 590 | ||
| @@ -561,7 +592,7 @@ static struct platform_device msm_device_jpegd_dst_ctx = { | |||
| 561 | .name = "msm_iommu_ctx", | 592 | .name = "msm_iommu_ctx", |
| 562 | .id = 1, | 593 | .id = 1, |
| 563 | .dev = { | 594 | .dev = { |
| 564 | .parent = &msm_device_smmu_jpegd.dev, | 595 | .parent = &msm_device_iommu_jpegd.dev, |
| 565 | }, | 596 | }, |
| 566 | }; | 597 | }; |
| 567 | 598 | ||
| @@ -569,7 +600,7 @@ static struct platform_device msm_device_vpe_src_ctx = { | |||
| 569 | .name = "msm_iommu_ctx", | 600 | .name = "msm_iommu_ctx", |
| 570 | .id = 2, | 601 | .id = 2, |
| 571 | .dev = { | 602 | .dev = { |
| 572 | .parent = &msm_device_smmu_vpe.dev, | 603 | .parent = &msm_device_iommu_vpe.dev, |
| 573 | }, | 604 | }, |
| 574 | }; | 605 | }; |
| 575 | 606 | ||
| @@ -577,7 +608,7 @@ static struct platform_device msm_device_vpe_dst_ctx = { | |||
| 577 | .name = "msm_iommu_ctx", | 608 | .name = "msm_iommu_ctx", |
| 578 | .id = 3, | 609 | .id = 3, |
| 579 | .dev = { | 610 | .dev = { |
| 580 | .parent = &msm_device_smmu_vpe.dev, | 611 | .parent = &msm_device_iommu_vpe.dev, |
| 581 | }, | 612 | }, |
| 582 | }; | 613 | }; |
| 583 | 614 | ||
| @@ -585,7 +616,7 @@ static struct platform_device msm_device_mdp_vg1_ctx = { | |||
| 585 | .name = "msm_iommu_ctx", | 616 | .name = "msm_iommu_ctx", |
| 586 | .id = 4, | 617 | .id = 4, |
| 587 | .dev = { | 618 | .dev = { |
| 588 | .parent = &msm_device_smmu_mdp0.dev, | 619 | .parent = &msm_device_iommu_mdp0.dev, |
| 589 | }, | 620 | }, |
| 590 | }; | 621 | }; |
| 591 | 622 | ||
| @@ -593,7 +624,7 @@ static struct platform_device msm_device_mdp_rgb1_ctx = { | |||
| 593 | .name = "msm_iommu_ctx", | 624 | .name = "msm_iommu_ctx", |
| 594 | .id = 5, | 625 | .id = 5, |
| 595 | .dev = { | 626 | .dev = { |
| 596 | .parent = &msm_device_smmu_mdp0.dev, | 627 | .parent = &msm_device_iommu_mdp0.dev, |
| 597 | }, | 628 | }, |
| 598 | }; | 629 | }; |
| 599 | 630 | ||
| @@ -601,7 +632,7 @@ static struct platform_device msm_device_mdp_vg2_ctx = { | |||
| 601 | .name = "msm_iommu_ctx", | 632 | .name = "msm_iommu_ctx", |
| 602 | .id = 6, | 633 | .id = 6, |
| 603 | .dev = { | 634 | .dev = { |
| 604 | .parent = &msm_device_smmu_mdp1.dev, | 635 | .parent = &msm_device_iommu_mdp1.dev, |
| 605 | }, | 636 | }, |
| 606 | }; | 637 | }; |
| 607 | 638 | ||
| @@ -609,7 +640,7 @@ static struct platform_device msm_device_mdp_rgb2_ctx = { | |||
| 609 | .name = "msm_iommu_ctx", | 640 | .name = "msm_iommu_ctx", |
| 610 | .id = 7, | 641 | .id = 7, |
| 611 | .dev = { | 642 | .dev = { |
| 612 | .parent = &msm_device_smmu_mdp1.dev, | 643 | .parent = &msm_device_iommu_mdp1.dev, |
| 613 | }, | 644 | }, |
| 614 | }; | 645 | }; |
| 615 | 646 | ||
| @@ -617,7 +648,7 @@ static struct platform_device msm_device_rot_src_ctx = { | |||
| 617 | .name = "msm_iommu_ctx", | 648 | .name = "msm_iommu_ctx", |
| 618 | .id = 8, | 649 | .id = 8, |
| 619 | .dev = { | 650 | .dev = { |
| 620 | .parent = &msm_device_smmu_rot.dev, | 651 | .parent = &msm_device_iommu_rot.dev, |
| 621 | }, | 652 | }, |
| 622 | }; | 653 | }; |
| 623 | 654 | ||
| @@ -625,7 +656,7 @@ static struct platform_device msm_device_rot_dst_ctx = { | |||
| 625 | .name = "msm_iommu_ctx", | 656 | .name = "msm_iommu_ctx", |
| 626 | .id = 9, | 657 | .id = 9, |
| 627 | .dev = { | 658 | .dev = { |
| 628 | .parent = &msm_device_smmu_rot.dev, | 659 | .parent = &msm_device_iommu_rot.dev, |
| 629 | }, | 660 | }, |
| 630 | }; | 661 | }; |
| 631 | 662 | ||
| @@ -633,7 +664,7 @@ static struct platform_device msm_device_ijpeg_src_ctx = { | |||
| 633 | .name = "msm_iommu_ctx", | 664 | .name = "msm_iommu_ctx", |
| 634 | .id = 10, | 665 | .id = 10, |
| 635 | .dev = { | 666 | .dev = { |
| 636 | .parent = &msm_device_smmu_ijpeg.dev, | 667 | .parent = &msm_device_iommu_ijpeg.dev, |
| 637 | }, | 668 | }, |
| 638 | }; | 669 | }; |
| 639 | 670 | ||
| @@ -641,7 +672,7 @@ static struct platform_device msm_device_ijpeg_dst_ctx = { | |||
| 641 | .name = "msm_iommu_ctx", | 672 | .name = "msm_iommu_ctx", |
| 642 | .id = 11, | 673 | .id = 11, |
| 643 | .dev = { | 674 | .dev = { |
| 644 | .parent = &msm_device_smmu_ijpeg.dev, | 675 | .parent = &msm_device_iommu_ijpeg.dev, |
| 645 | }, | 676 | }, |
| 646 | }; | 677 | }; |
| 647 | 678 | ||
| @@ -649,7 +680,7 @@ static struct platform_device msm_device_vfe_imgwr_ctx = { | |||
| 649 | .name = "msm_iommu_ctx", | 680 | .name = "msm_iommu_ctx", |
| 650 | .id = 12, | 681 | .id = 12, |
| 651 | .dev = { | 682 | .dev = { |
| 652 | .parent = &msm_device_smmu_vfe.dev, | 683 | .parent = &msm_device_iommu_vfe.dev, |
| 653 | }, | 684 | }, |
| 654 | }; | 685 | }; |
| 655 | 686 | ||
| @@ -657,7 +688,7 @@ static struct platform_device msm_device_vfe_misc_ctx = { | |||
| 657 | .name = "msm_iommu_ctx", | 688 | .name = "msm_iommu_ctx", |
| 658 | .id = 13, | 689 | .id = 13, |
| 659 | .dev = { | 690 | .dev = { |
| 660 | .parent = &msm_device_smmu_vfe.dev, | 691 | .parent = &msm_device_iommu_vfe.dev, |
| 661 | }, | 692 | }, |
| 662 | }; | 693 | }; |
| 663 | 694 | ||
| @@ -665,7 +696,7 @@ static struct platform_device msm_device_vcodec_a_stream_ctx = { | |||
| 665 | .name = "msm_iommu_ctx", | 696 | .name = "msm_iommu_ctx", |
| 666 | .id = 14, | 697 | .id = 14, |
| 667 | .dev = { | 698 | .dev = { |
| 668 | .parent = &msm_device_smmu_vcodec_a.dev, | 699 | .parent = &msm_device_iommu_vcodec_a.dev, |
| 669 | }, | 700 | }, |
| 670 | }; | 701 | }; |
| 671 | 702 | ||
| @@ -673,7 +704,7 @@ static struct platform_device msm_device_vcodec_a_mm1_ctx = { | |||
| 673 | .name = "msm_iommu_ctx", | 704 | .name = "msm_iommu_ctx", |
| 674 | .id = 15, | 705 | .id = 15, |
| 675 | .dev = { | 706 | .dev = { |
| 676 | .parent = &msm_device_smmu_vcodec_a.dev, | 707 | .parent = &msm_device_iommu_vcodec_a.dev, |
| 677 | }, | 708 | }, |
| 678 | }; | 709 | }; |
| 679 | 710 | ||
| @@ -681,76 +712,70 @@ static struct platform_device msm_device_vcodec_b_mm2_ctx = { | |||
| 681 | .name = "msm_iommu_ctx", | 712 | .name = "msm_iommu_ctx", |
| 682 | .id = 16, | 713 | .id = 16, |
| 683 | .dev = { | 714 | .dev = { |
| 684 | .parent = &msm_device_smmu_vcodec_b.dev, | 715 | .parent = &msm_device_iommu_vcodec_b.dev, |
| 685 | }, | 716 | }, |
| 686 | }; | 717 | }; |
| 687 | 718 | ||
| 688 | static struct platform_device msm_device_gfx3d_rbpa_ctx = { | 719 | static struct platform_device msm_device_gfx3d_user_ctx = { |
| 689 | .name = "msm_iommu_ctx", | 720 | .name = "msm_iommu_ctx", |
| 690 | .id = 17, | 721 | .id = 17, |
| 691 | .dev = { | 722 | .dev = { |
| 692 | .parent = &msm_device_smmu_gfx3d.dev, | 723 | .parent = &msm_device_iommu_gfx3d.dev, |
| 693 | }, | 724 | }, |
| 694 | }; | 725 | }; |
| 695 | 726 | ||
| 696 | static struct platform_device msm_device_gfx3d_cpvgttc_ctx = { | 727 | static struct platform_device msm_device_gfx3d_priv_ctx = { |
| 697 | .name = "msm_iommu_ctx", | 728 | .name = "msm_iommu_ctx", |
| 698 | .id = 18, | 729 | .id = 18, |
| 699 | .dev = { | 730 | .dev = { |
| 700 | .parent = &msm_device_smmu_gfx3d.dev, | 731 | .parent = &msm_device_iommu_gfx3d.dev, |
| 701 | }, | 732 | }, |
| 702 | }; | 733 | }; |
| 703 | 734 | ||
| 704 | static struct platform_device msm_device_gfx3d_smmu_ctx = { | 735 | static struct platform_device msm_device_gfx2d0_2d0_ctx = { |
| 705 | .name = "msm_iommu_ctx", | 736 | .name = "msm_iommu_ctx", |
| 706 | .id = 19, | 737 | .id = 19, |
| 707 | .dev = { | 738 | .dev = { |
| 708 | .parent = &msm_device_smmu_gfx3d.dev, | 739 | .parent = &msm_device_iommu_gfx2d0.dev, |
| 709 | }, | 740 | }, |
| 710 | }; | 741 | }; |
| 711 | 742 | ||
| 712 | static struct platform_device msm_device_gfx2d0_pixv1_ctx = { | 743 | static struct platform_device msm_device_gfx2d1_2d1_ctx = { |
| 713 | .name = "msm_iommu_ctx", | 744 | .name = "msm_iommu_ctx", |
| 714 | .id = 20, | 745 | .id = 20, |
| 715 | .dev = { | 746 | .dev = { |
| 716 | .parent = &msm_device_smmu_gfx2d0.dev, | 747 | .parent = &msm_device_iommu_gfx2d1.dev, |
| 717 | }, | ||
| 718 | }; | ||
| 719 | |||
| 720 | static struct platform_device msm_device_gfx2d0_texv3_ctx = { | ||
| 721 | .name = "msm_iommu_ctx", | ||
| 722 | .id = 21, | ||
| 723 | .dev = { | ||
| 724 | .parent = &msm_device_smmu_gfx2d0.dev, | ||
| 725 | }, | 748 | }, |
| 726 | }; | 749 | }; |
| 727 | 750 | ||
| 728 | static struct platform_device *msm_iommu_devs[] = { | 751 | static struct platform_device *msm_iommu_devs[] = { |
| 729 | &msm_device_smmu_jpegd, | 752 | &msm_device_iommu_jpegd, |
| 730 | &msm_device_smmu_vpe, | 753 | &msm_device_iommu_vpe, |
| 731 | &msm_device_smmu_mdp0, | 754 | &msm_device_iommu_mdp0, |
| 732 | &msm_device_smmu_mdp1, | 755 | &msm_device_iommu_mdp1, |
| 733 | &msm_device_smmu_rot, | 756 | &msm_device_iommu_rot, |
| 734 | &msm_device_smmu_ijpeg, | 757 | &msm_device_iommu_ijpeg, |
| 735 | &msm_device_smmu_vfe, | 758 | &msm_device_iommu_vfe, |
| 736 | &msm_device_smmu_vcodec_a, | 759 | &msm_device_iommu_vcodec_a, |
| 737 | &msm_device_smmu_vcodec_b, | 760 | &msm_device_iommu_vcodec_b, |
| 738 | &msm_device_smmu_gfx3d, | 761 | &msm_device_iommu_gfx3d, |
| 739 | &msm_device_smmu_gfx2d0, | 762 | &msm_device_iommu_gfx2d0, |
| 763 | &msm_device_iommu_gfx2d1, | ||
| 740 | }; | 764 | }; |
| 741 | 765 | ||
| 742 | static struct msm_iommu_dev *msm_iommu_data[] = { | 766 | static struct msm_iommu_dev *msm_iommu_data[] = { |
| 743 | &jpegd_smmu, | 767 | &jpegd_iommu, |
| 744 | &vpe_smmu, | 768 | &vpe_iommu, |
| 745 | &mdp0_smmu, | 769 | &mdp0_iommu, |
| 746 | &mdp1_smmu, | 770 | &mdp1_iommu, |
| 747 | &rot_smmu, | 771 | &rot_iommu, |
| 748 | &ijpeg_smmu, | 772 | &ijpeg_iommu, |
| 749 | &vfe_smmu, | 773 | &vfe_iommu, |
| 750 | &vcodec_a_smmu, | 774 | &vcodec_a_iommu, |
| 751 | &vcodec_b_smmu, | 775 | &vcodec_b_iommu, |
| 752 | &gfx3d_smmu, | 776 | &gfx3d_iommu, |
| 753 | &gfx2d0_smmu, | 777 | &gfx2d0_iommu, |
| 778 | &gfx2d1_iommu, | ||
| 754 | }; | 779 | }; |
| 755 | 780 | ||
| 756 | static struct platform_device *msm_iommu_ctx_devs[] = { | 781 | static struct platform_device *msm_iommu_ctx_devs[] = { |
| @@ -771,11 +796,10 @@ static struct platform_device *msm_iommu_ctx_devs[] = { | |||
| 771 | &msm_device_vcodec_a_stream_ctx, | 796 | &msm_device_vcodec_a_stream_ctx, |
| 772 | &msm_device_vcodec_a_mm1_ctx, | 797 | &msm_device_vcodec_a_mm1_ctx, |
| 773 | &msm_device_vcodec_b_mm2_ctx, | 798 | &msm_device_vcodec_b_mm2_ctx, |
| 774 | &msm_device_gfx3d_rbpa_ctx, | 799 | &msm_device_gfx3d_user_ctx, |
| 775 | &msm_device_gfx3d_cpvgttc_ctx, | 800 | &msm_device_gfx3d_priv_ctx, |
| 776 | &msm_device_gfx3d_smmu_ctx, | 801 | &msm_device_gfx2d0_2d0_ctx, |
| 777 | &msm_device_gfx2d0_pixv1_ctx, | 802 | &msm_device_gfx2d1_2d1_ctx, |
| 778 | &msm_device_gfx2d0_texv3_ctx, | ||
| 779 | }; | 803 | }; |
| 780 | 804 | ||
| 781 | static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = { | 805 | static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = { |
| @@ -796,14 +820,13 @@ static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = { | |||
| 796 | &vcodec_a_stream_ctx, | 820 | &vcodec_a_stream_ctx, |
| 797 | &vcodec_a_mm1_ctx, | 821 | &vcodec_a_mm1_ctx, |
| 798 | &vcodec_b_mm2_ctx, | 822 | &vcodec_b_mm2_ctx, |
| 799 | &gfx3d_rbpa_ctx, | 823 | &gfx3d_user_ctx, |
| 800 | &gfx3d_cpvgttc_ctx, | 824 | &gfx3d_priv_ctx, |
| 801 | &gfx3d_smmu_ctx, | 825 | &gfx2d0_2d0_ctx, |
| 802 | &gfx2d0_pixv1_ctx, | 826 | &gfx2d1_2d1_ctx, |
| 803 | &gfx2d0_texv3_ctx, | ||
| 804 | }; | 827 | }; |
| 805 | 828 | ||
| 806 | static int msm8x60_iommu_init(void) | 829 | static int __init msm8x60_iommu_init(void) |
| 807 | { | 830 | { |
| 808 | int ret, i; | 831 | int ret, i; |
| 809 | 832 | ||
| @@ -826,7 +849,7 @@ static int msm8x60_iommu_init(void) | |||
| 826 | ret = platform_device_register(msm_iommu_devs[i]); | 849 | ret = platform_device_register(msm_iommu_devs[i]); |
| 827 | 850 | ||
| 828 | if (ret != 0) { | 851 | if (ret != 0) { |
| 829 | pr_err("platform_device_register smmu failed, " | 852 | pr_err("platform_device_register iommu failed, " |
| 830 | "i = %d\n", i); | 853 | "i = %d\n", i); |
| 831 | goto failure_unwind; | 854 | goto failure_unwind; |
| 832 | } | 855 | } |
| @@ -837,7 +860,7 @@ static int msm8x60_iommu_init(void) | |||
| 837 | msm_iommu_ctx_data[i], | 860 | msm_iommu_ctx_data[i], |
| 838 | sizeof(*msm_iommu_ctx_devs[i])); | 861 | sizeof(*msm_iommu_ctx_devs[i])); |
| 839 | if (ret != 0) { | 862 | if (ret != 0) { |
| 840 | pr_err("platform_device_add_data smmu failed, " | 863 | pr_err("platform_device_add_data iommu failed, " |
| 841 | "i = %d\n", i); | 864 | "i = %d\n", i); |
| 842 | goto failure_unwind2; | 865 | goto failure_unwind2; |
| 843 | } | 866 | } |
| @@ -863,7 +886,7 @@ failure: | |||
| 863 | return ret; | 886 | return ret; |
| 864 | } | 887 | } |
| 865 | 888 | ||
| 866 | static void msm8x60_iommu_exit(void) | 889 | static void __exit msm8x60_iommu_exit(void) |
| 867 | { | 890 | { |
| 868 | int i; | 891 | int i; |
| 869 | 892 | ||
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c index 6fe67c5d1ae0..a4b798f20ccb 100644 --- a/arch/arm/mach-msm/devices-qsd8x50.c +++ b/arch/arm/mach-msm/devices-qsd8x50.c | |||
| @@ -53,6 +53,77 @@ struct platform_device msm_device_smd = { | |||
| 53 | .id = -1, | 53 | .id = -1, |
| 54 | }; | 54 | }; |
| 55 | 55 | ||
| 56 | static struct resource resources_otg[] = { | ||
| 57 | { | ||
| 58 | .start = MSM_HSUSB_PHYS, | ||
| 59 | .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE, | ||
| 60 | .flags = IORESOURCE_MEM, | ||
| 61 | }, | ||
| 62 | { | ||
| 63 | .start = INT_USB_HS, | ||
| 64 | .end = INT_USB_HS, | ||
| 65 | .flags = IORESOURCE_IRQ, | ||
| 66 | }, | ||
| 67 | }; | ||
| 68 | |||
| 69 | struct platform_device msm_device_otg = { | ||
| 70 | .name = "msm_otg", | ||
| 71 | .id = -1, | ||
| 72 | .num_resources = ARRAY_SIZE(resources_otg), | ||
| 73 | .resource = resources_otg, | ||
| 74 | .dev = { | ||
| 75 | .coherent_dma_mask = 0xffffffff, | ||
| 76 | }, | ||
| 77 | }; | ||
| 78 | |||
| 79 | static struct resource resources_hsusb[] = { | ||
| 80 | { | ||
| 81 | .start = MSM_HSUSB_PHYS, | ||
| 82 | .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE, | ||
| 83 | .flags = IORESOURCE_MEM, | ||
| 84 | }, | ||
| 85 | { | ||
| 86 | .start = INT_USB_HS, | ||
| 87 | .end = INT_USB_HS, | ||
| 88 | .flags = IORESOURCE_IRQ, | ||
| 89 | }, | ||
| 90 | }; | ||
| 91 | |||
| 92 | struct platform_device msm_device_hsusb = { | ||
| 93 | .name = "msm_hsusb", | ||
| 94 | .id = -1, | ||
| 95 | .num_resources = ARRAY_SIZE(resources_hsusb), | ||
| 96 | .resource = resources_hsusb, | ||
| 97 | .dev = { | ||
| 98 | .coherent_dma_mask = 0xffffffff, | ||
| 99 | }, | ||
| 100 | }; | ||
| 101 | |||
| 102 | static u64 dma_mask = 0xffffffffULL; | ||
| 103 | static struct resource resources_hsusb_host[] = { | ||
| 104 | { | ||
| 105 | .start = MSM_HSUSB_PHYS, | ||
| 106 | .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE, | ||
| 107 | .flags = IORESOURCE_MEM, | ||
| 108 | }, | ||
| 109 | { | ||
| 110 | .start = INT_USB_HS, | ||
| 111 | .end = INT_USB_HS, | ||
| 112 | .flags = IORESOURCE_IRQ, | ||
| 113 | }, | ||
| 114 | }; | ||
| 115 | |||
| 116 | struct platform_device msm_device_hsusb_host = { | ||
| 117 | .name = "msm_hsusb_host", | ||
| 118 | .id = -1, | ||
| 119 | .num_resources = ARRAY_SIZE(resources_hsusb_host), | ||
| 120 | .resource = resources_hsusb_host, | ||
| 121 | .dev = { | ||
| 122 | .dma_mask = &dma_mask, | ||
| 123 | .coherent_dma_mask = 0xffffffffULL, | ||
| 124 | }, | ||
| 125 | }; | ||
| 126 | |||
| 56 | struct clk msm_clocks_8x50[] = { | 127 | struct clk msm_clocks_8x50[] = { |
| 57 | CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), | 128 | CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), |
| 58 | CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN), | 129 | CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN), |
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h index 568443e76423..87c70bfce2bd 100644 --- a/arch/arm/mach-msm/devices.h +++ b/arch/arm/mach-msm/devices.h | |||
| @@ -28,6 +28,8 @@ extern struct platform_device msm_device_sdc3; | |||
| 28 | extern struct platform_device msm_device_sdc4; | 28 | extern struct platform_device msm_device_sdc4; |
| 29 | 29 | ||
| 30 | extern struct platform_device msm_device_hsusb; | 30 | extern struct platform_device msm_device_hsusb; |
| 31 | extern struct platform_device msm_device_otg; | ||
| 32 | extern struct platform_device msm_device_hsusb_host; | ||
| 31 | 33 | ||
| 32 | extern struct platform_device msm_device_i2c; | 34 | extern struct platform_device msm_device_i2c; |
| 33 | 35 | ||
| @@ -35,6 +37,10 @@ extern struct platform_device msm_device_smd; | |||
| 35 | 37 | ||
| 36 | extern struct platform_device msm_device_nand; | 38 | extern struct platform_device msm_device_nand; |
| 37 | 39 | ||
| 40 | extern struct platform_device msm_device_mddi0; | ||
| 41 | extern struct platform_device msm_device_mddi1; | ||
| 42 | extern struct platform_device msm_device_mdp; | ||
| 43 | |||
| 38 | extern struct clk msm_clocks_7x01a[]; | 44 | extern struct clk msm_clocks_7x01a[]; |
| 39 | extern unsigned msm_num_clocks_7x01a; | 45 | extern unsigned msm_num_clocks_7x01a; |
| 40 | 46 | ||
diff --git a/arch/arm/mach-msm/gpio-v2.c b/arch/arm/mach-msm/gpio-v2.c new file mode 100644 index 000000000000..0de19ec74e34 --- /dev/null +++ b/arch/arm/mach-msm/gpio-v2.c | |||
| @@ -0,0 +1,426 @@ | |||
| 1 | /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. | ||
| 2 | * | ||
| 3 | * This program is free software; you can redistribute it and/or modify | ||
| 4 | * it under the terms of the GNU General Public License version 2 and | ||
| 5 | * only version 2 as published by the Free Software Foundation. | ||
| 6 | * | ||
| 7 | * This program is distributed in the hope that it will be useful, | ||
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 10 | * GNU General Public License for more details. | ||
| 11 | * | ||
| 12 | * You should have received a copy of the GNU General Public License | ||
| 13 | * along with this program; if not, write to the Free Software | ||
| 14 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | ||
| 15 | * 02110-1301, USA. | ||
| 16 | * | ||
| 17 | */ | ||
| 18 | #define pr_fmt(fmt) "%s: " fmt, __func__ | ||
| 19 | |||
| 20 | #include <linux/bitmap.h> | ||
| 21 | #include <linux/bitops.h> | ||
| 22 | #include <linux/gpio.h> | ||
| 23 | #include <linux/init.h> | ||
| 24 | #include <linux/interrupt.h> | ||
| 25 | #include <linux/io.h> | ||
| 26 | #include <linux/irq.h> | ||
| 27 | #include <linux/module.h> | ||
| 28 | #include <linux/platform_device.h> | ||
| 29 | #include <linux/spinlock.h> | ||
| 30 | #include <mach/msm_iomap.h> | ||
| 31 | #include "gpiomux.h" | ||
| 32 | |||
| 33 | /* Bits of interest in the GPIO_IN_OUT register. | ||
| 34 | */ | ||
| 35 | enum { | ||
| 36 | GPIO_IN = 0, | ||
| 37 | GPIO_OUT = 1 | ||
| 38 | }; | ||
| 39 | |||
| 40 | /* Bits of interest in the GPIO_INTR_STATUS register. | ||
| 41 | */ | ||
| 42 | enum { | ||
| 43 | INTR_STATUS = 0, | ||
| 44 | }; | ||
| 45 | |||
| 46 | /* Bits of interest in the GPIO_CFG register. | ||
| 47 | */ | ||
| 48 | enum { | ||
| 49 | GPIO_OE = 9, | ||
| 50 | }; | ||
| 51 | |||
| 52 | /* Bits of interest in the GPIO_INTR_CFG register. | ||
| 53 | * When a GPIO triggers, two separate decisions are made, controlled | ||
| 54 | * by two separate flags. | ||
| 55 | * | ||
| 56 | * - First, INTR_RAW_STATUS_EN controls whether or not the GPIO_INTR_STATUS | ||
| 57 | * register for that GPIO will be updated to reflect the triggering of that | ||
| 58 | * gpio. If this bit is 0, this register will not be updated. | ||
| 59 | * - Second, INTR_ENABLE controls whether an interrupt is triggered. | ||
| 60 | * | ||
| 61 | * If INTR_ENABLE is set and INTR_RAW_STATUS_EN is NOT set, an interrupt | ||
| 62 | * can be triggered but the status register will not reflect it. | ||
| 63 | */ | ||
| 64 | enum { | ||
| 65 | INTR_ENABLE = 0, | ||
| 66 | INTR_POL_CTL = 1, | ||
| 67 | INTR_DECT_CTL = 2, | ||
| 68 | INTR_RAW_STATUS_EN = 3, | ||
| 69 | }; | ||
| 70 | |||
| 71 | /* Codes of interest in GPIO_INTR_CFG_SU. | ||
| 72 | */ | ||
| 73 | enum { | ||
| 74 | TARGET_PROC_SCORPION = 4, | ||
| 75 | TARGET_PROC_NONE = 7, | ||
| 76 | }; | ||
| 77 | |||
| 78 | |||
| 79 | #define GPIO_INTR_CFG_SU(gpio) (MSM_TLMM_BASE + 0x0400 + (0x04 * (gpio))) | ||
| 80 | #define GPIO_CONFIG(gpio) (MSM_TLMM_BASE + 0x1000 + (0x10 * (gpio))) | ||
| 81 | #define GPIO_IN_OUT(gpio) (MSM_TLMM_BASE + 0x1004 + (0x10 * (gpio))) | ||
| 82 | #define GPIO_INTR_CFG(gpio) (MSM_TLMM_BASE + 0x1008 + (0x10 * (gpio))) | ||
| 83 | #define GPIO_INTR_STATUS(gpio) (MSM_TLMM_BASE + 0x100c + (0x10 * (gpio))) | ||
| 84 | |||
| 85 | /** | ||
| 86 | * struct msm_gpio_dev: the MSM8660 SoC GPIO device structure | ||
| 87 | * | ||
| 88 | * @enabled_irqs: a bitmap used to optimize the summary-irq handler. By | ||
| 89 | * keeping track of which gpios are unmasked as irq sources, we avoid | ||
| 90 | * having to do readl calls on hundreds of iomapped registers each time | ||
| 91 | * the summary interrupt fires in order to locate the active interrupts. | ||
| 92 | * | ||
| 93 | * @wake_irqs: a bitmap for tracking which interrupt lines are enabled | ||
| 94 | * as wakeup sources. When the device is suspended, interrupts which are | ||
| 95 | * not wakeup sources are disabled. | ||
| 96 | * | ||
| 97 | * @dual_edge_irqs: a bitmap used to track which irqs are configured | ||
| 98 | * as dual-edge, as this is not supported by the hardware and requires | ||
| 99 | * some special handling in the driver. | ||
| 100 | */ | ||
| 101 | struct msm_gpio_dev { | ||
| 102 | struct gpio_chip gpio_chip; | ||
| 103 | DECLARE_BITMAP(enabled_irqs, NR_GPIO_IRQS); | ||
| 104 | DECLARE_BITMAP(wake_irqs, NR_GPIO_IRQS); | ||
| 105 | DECLARE_BITMAP(dual_edge_irqs, NR_GPIO_IRQS); | ||
| 106 | }; | ||
| 107 | |||
| 108 | static DEFINE_SPINLOCK(tlmm_lock); | ||
| 109 | |||
| 110 | static inline struct msm_gpio_dev *to_msm_gpio_dev(struct gpio_chip *chip) | ||
| 111 | { | ||
| 112 | return container_of(chip, struct msm_gpio_dev, gpio_chip); | ||
| 113 | } | ||
| 114 | |||
| 115 | static inline void set_gpio_bits(unsigned n, void __iomem *reg) | ||
| 116 | { | ||
| 117 | writel(readl(reg) | n, reg); | ||
| 118 | } | ||
| 119 | |||
| 120 | static inline void clear_gpio_bits(unsigned n, void __iomem *reg) | ||
| 121 | { | ||
| 122 | writel(readl(reg) & ~n, reg); | ||
| 123 | } | ||
| 124 | |||
| 125 | static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) | ||
| 126 | { | ||
| 127 | return readl(GPIO_IN_OUT(offset)) & BIT(GPIO_IN); | ||
| 128 | } | ||
| 129 | |||
| 130 | static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int val) | ||
| 131 | { | ||
| 132 | writel(val ? BIT(GPIO_OUT) : 0, GPIO_IN_OUT(offset)); | ||
| 133 | } | ||
| 134 | |||
| 135 | static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | ||
| 136 | { | ||
| 137 | unsigned long irq_flags; | ||
| 138 | |||
| 139 | spin_lock_irqsave(&tlmm_lock, irq_flags); | ||
| 140 | clear_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset)); | ||
| 141 | spin_unlock_irqrestore(&tlmm_lock, irq_flags); | ||
| 142 | return 0; | ||
| 143 | } | ||
| 144 | |||
| 145 | static int msm_gpio_direction_output(struct gpio_chip *chip, | ||
| 146 | unsigned offset, | ||
| 147 | int val) | ||
| 148 | { | ||
| 149 | unsigned long irq_flags; | ||
| 150 | |||
| 151 | spin_lock_irqsave(&tlmm_lock, irq_flags); | ||
| 152 | msm_gpio_set(chip, offset, val); | ||
| 153 | set_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset)); | ||
| 154 | spin_unlock_irqrestore(&tlmm_lock, irq_flags); | ||
| 155 | return 0; | ||
| 156 | } | ||
| 157 | |||
| 158 | static int msm_gpio_request(struct gpio_chip *chip, unsigned offset) | ||
| 159 | { | ||
| 160 | return msm_gpiomux_get(chip->base + offset); | ||
| 161 | } | ||
| 162 | |||
| 163 | static void msm_gpio_free(struct gpio_chip *chip, unsigned offset) | ||
| 164 | { | ||
| 165 | msm_gpiomux_put(chip->base + offset); | ||
| 166 | } | ||
| 167 | |||
| 168 | static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | ||
| 169 | { | ||
| 170 | return MSM_GPIO_TO_INT(chip->base + offset); | ||
| 171 | } | ||
| 172 | |||
| 173 | static inline int msm_irq_to_gpio(struct gpio_chip *chip, unsigned irq) | ||
| 174 | { | ||
| 175 | return irq - MSM_GPIO_TO_INT(chip->base); | ||
| 176 | } | ||
| 177 | |||
| 178 | static struct msm_gpio_dev msm_gpio = { | ||
| 179 | .gpio_chip = { | ||
| 180 | .base = 0, | ||
| 181 | .ngpio = NR_GPIO_IRQS, | ||
| 182 | .direction_input = msm_gpio_direction_input, | ||
| 183 | .direction_output = msm_gpio_direction_output, | ||
| 184 | .get = msm_gpio_get, | ||
| 185 | .set = msm_gpio_set, | ||
| 186 | .to_irq = msm_gpio_to_irq, | ||
| 187 | .request = msm_gpio_request, | ||
| 188 | .free = msm_gpio_free, | ||
| 189 | }, | ||
| 190 | }; | ||
| 191 | |||
| 192 | /* For dual-edge interrupts in software, since the hardware has no | ||
| 193 | * such support: | ||
| 194 | * | ||
| 195 | * At appropriate moments, this function may be called to flip the polarity | ||
| 196 | * settings of both-edge irq lines to try and catch the next edge. | ||
| 197 | * | ||
| 198 | * The attempt is considered successful if: | ||
| 199 | * - the status bit goes high, indicating that an edge was caught, or | ||
| 200 | * - the input value of the gpio doesn't change during the attempt. | ||
| 201 | * If the value changes twice during the process, that would cause the first | ||
| 202 | * test to fail but would force the second, as two opposite | ||
| 203 | * transitions would cause a detection no matter the polarity setting. | ||
| 204 | * | ||
| 205 | * The do-loop tries to sledge-hammer closed the timing hole between | ||
| 206 | * the initial value-read and the polarity-write - if the line value changes | ||
| 207 | * during that window, an interrupt is lost, the new polarity setting is | ||
| 208 | * incorrect, and the first success test will fail, causing a retry. | ||
| 209 | * | ||
| 210 | * Algorithm comes from Google's msmgpio driver, see mach-msm/gpio.c. | ||
| 211 | */ | ||
| 212 | static void msm_gpio_update_dual_edge_pos(unsigned gpio) | ||
| 213 | { | ||
| 214 | int loop_limit = 100; | ||
| 215 | unsigned val, val2, intstat; | ||
| 216 | |||
| 217 | do { | ||
| 218 | val = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN); | ||
| 219 | if (val) | ||
| 220 | clear_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio)); | ||
| 221 | else | ||
| 222 | set_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio)); | ||
| 223 | val2 = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN); | ||
| 224 | intstat = readl(GPIO_INTR_STATUS(gpio)) & BIT(INTR_STATUS); | ||
| 225 | if (intstat || val == val2) | ||
| 226 | return; | ||
| 227 | } while (loop_limit-- > 0); | ||
| 228 | pr_err("dual-edge irq failed to stabilize, " | ||
| 229 | "interrupts dropped. %#08x != %#08x\n", | ||
| 230 | val, val2); | ||
| 231 | } | ||
| 232 | |||
| 233 | static void msm_gpio_irq_ack(unsigned int irq) | ||
| 234 | { | ||
| 235 | int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); | ||
| 236 | |||
| 237 | writel(BIT(INTR_STATUS), GPIO_INTR_STATUS(gpio)); | ||
| 238 | if (test_bit(gpio, msm_gpio.dual_edge_irqs)) | ||
| 239 | msm_gpio_update_dual_edge_pos(gpio); | ||
| 240 | } | ||
| 241 | |||
| 242 | static void msm_gpio_irq_mask(unsigned int irq) | ||
| 243 | { | ||
| 244 | int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); | ||
| 245 | unsigned long irq_flags; | ||
| 246 | |||
| 247 | spin_lock_irqsave(&tlmm_lock, irq_flags); | ||
| 248 | writel(TARGET_PROC_NONE, GPIO_INTR_CFG_SU(gpio)); | ||
| 249 | clear_gpio_bits(INTR_RAW_STATUS_EN | INTR_ENABLE, GPIO_INTR_CFG(gpio)); | ||
| 250 | __clear_bit(gpio, msm_gpio.enabled_irqs); | ||
| 251 | spin_unlock_irqrestore(&tlmm_lock, irq_flags); | ||
| 252 | } | ||
| 253 | |||
| 254 | static void msm_gpio_irq_unmask(unsigned int irq) | ||
| 255 | { | ||
| 256 | int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); | ||
| 257 | unsigned long irq_flags; | ||
| 258 | |||
| 259 | spin_lock_irqsave(&tlmm_lock, irq_flags); | ||
| 260 | __set_bit(gpio, msm_gpio.enabled_irqs); | ||
| 261 | set_gpio_bits(INTR_RAW_STATUS_EN | INTR_ENABLE, GPIO_INTR_CFG(gpio)); | ||
| 262 | writel(TARGET_PROC_SCORPION, GPIO_INTR_CFG_SU(gpio)); | ||
| 263 | spin_unlock_irqrestore(&tlmm_lock, irq_flags); | ||
| 264 | } | ||
| 265 | |||
| 266 | static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) | ||
| 267 | { | ||
| 268 | int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); | ||
| 269 | unsigned long irq_flags; | ||
| 270 | uint32_t bits; | ||
| 271 | |||
| 272 | spin_lock_irqsave(&tlmm_lock, irq_flags); | ||
| 273 | |||
| 274 | bits = readl(GPIO_INTR_CFG(gpio)); | ||
| 275 | |||
| 276 | if (flow_type & IRQ_TYPE_EDGE_BOTH) { | ||
| 277 | bits |= BIT(INTR_DECT_CTL); | ||
| 278 | irq_desc[irq].handle_irq = handle_edge_irq; | ||
| 279 | if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) | ||
| 280 | __set_bit(gpio, msm_gpio.dual_edge_irqs); | ||
| 281 | else | ||
| 282 | __clear_bit(gpio, msm_gpio.dual_edge_irqs); | ||
| 283 | } else { | ||
| 284 | bits &= ~BIT(INTR_DECT_CTL); | ||
| 285 | irq_desc[irq].handle_irq = handle_level_irq; | ||
| 286 | __clear_bit(gpio, msm_gpio.dual_edge_irqs); | ||
| 287 | } | ||
| 288 | |||
| 289 | if (flow_type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)) | ||
| 290 | bits |= BIT(INTR_POL_CTL); | ||
| 291 | else | ||
| 292 | bits &= ~BIT(INTR_POL_CTL); | ||
| 293 | |||
| 294 | writel(bits, GPIO_INTR_CFG(gpio)); | ||
| 295 | |||
| 296 | if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) | ||
| 297 | msm_gpio_update_dual_edge_pos(gpio); | ||
| 298 | |||
| 299 | spin_unlock_irqrestore(&tlmm_lock, irq_flags); | ||
| 300 | |||
| 301 | return 0; | ||
| 302 | } | ||
| 303 | |||
| 304 | /* | ||
| 305 | * When the summary IRQ is raised, any number of GPIO lines may be high. | ||
| 306 | * It is the job of the summary handler to find all those GPIO lines | ||
| 307 | * which have been set as summary IRQ lines and which are triggered, | ||
| 308 | * and to call their interrupt handlers. | ||
| 309 | */ | ||
| 310 | static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc) | ||
| 311 | { | ||
| 312 | unsigned long i; | ||
| 313 | |||
| 314 | for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS); | ||
| 315 | i < NR_GPIO_IRQS; | ||
| 316 | i = find_next_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS, i + 1)) { | ||
| 317 | if (readl(GPIO_INTR_STATUS(i)) & BIT(INTR_STATUS)) | ||
| 318 | generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip, | ||
| 319 | i)); | ||
| 320 | } | ||
| 321 | desc->chip->ack(irq); | ||
| 322 | } | ||
| 323 | |||
| 324 | static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on) | ||
| 325 | { | ||
| 326 | int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); | ||
| 327 | |||
| 328 | if (on) { | ||
| 329 | if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) | ||
| 330 | set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1); | ||
| 331 | set_bit(gpio, msm_gpio.wake_irqs); | ||
| 332 | } else { | ||
| 333 | clear_bit(gpio, msm_gpio.wake_irqs); | ||
| 334 | if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) | ||
| 335 | set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0); | ||
| 336 | } | ||
| 337 | |||
| 338 | return 0; | ||
| 339 | } | ||
| 340 | |||
| 341 | static struct irq_chip msm_gpio_irq_chip = { | ||
| 342 | .name = "msmgpio", | ||
| 343 | .mask = msm_gpio_irq_mask, | ||
| 344 | .unmask = msm_gpio_irq_unmask, | ||
| 345 | .ack = msm_gpio_irq_ack, | ||
| 346 | .set_type = msm_gpio_irq_set_type, | ||
| 347 | .set_wake = msm_gpio_irq_set_wake, | ||
| 348 | }; | ||
| 349 | |||
| 350 | static int __devinit msm_gpio_probe(struct platform_device *dev) | ||
| 351 | { | ||
| 352 | int i, irq, ret; | ||
| 353 | |||
| 354 | bitmap_zero(msm_gpio.enabled_irqs, NR_GPIO_IRQS); | ||
| 355 | bitmap_zero(msm_gpio.wake_irqs, NR_GPIO_IRQS); | ||
| 356 | bitmap_zero(msm_gpio.dual_edge_irqs, NR_GPIO_IRQS); | ||
| 357 | msm_gpio.gpio_chip.label = dev->name; | ||
| 358 | ret = gpiochip_add(&msm_gpio.gpio_chip); | ||
| 359 | if (ret < 0) | ||
| 360 | return ret; | ||
| 361 | |||
| 362 | for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) { | ||
| 363 | irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i); | ||
| 364 | set_irq_chip(irq, &msm_gpio_irq_chip); | ||
| 365 | set_irq_handler(irq, handle_level_irq); | ||
| 366 | set_irq_flags(irq, IRQF_VALID); | ||
| 367 | } | ||
| 368 | |||
| 369 | set_irq_chained_handler(TLMM_SCSS_SUMMARY_IRQ, | ||
| 370 | msm_summary_irq_handler); | ||
| 371 | return 0; | ||
| 372 | } | ||
| 373 | |||
| 374 | static int __devexit msm_gpio_remove(struct platform_device *dev) | ||
| 375 | { | ||
| 376 | int ret = gpiochip_remove(&msm_gpio.gpio_chip); | ||
| 377 | |||
| 378 | if (ret < 0) | ||
| 379 | return ret; | ||
| 380 | |||
| 381 | set_irq_handler(TLMM_SCSS_SUMMARY_IRQ, NULL); | ||
| 382 | |||
| 383 | return 0; | ||
| 384 | } | ||
| 385 | |||
| 386 | static struct platform_driver msm_gpio_driver = { | ||
| 387 | .probe = msm_gpio_probe, | ||
| 388 | .remove = __devexit_p(msm_gpio_remove), | ||
| 389 | .driver = { | ||
| 390 | .name = "msmgpio", | ||
| 391 | .owner = THIS_MODULE, | ||
| 392 | }, | ||
| 393 | }; | ||
| 394 | |||
| 395 | static struct platform_device msm_device_gpio = { | ||
| 396 | .name = "msmgpio", | ||
| 397 | .id = -1, | ||
| 398 | }; | ||
| 399 | |||
| 400 | static int __init msm_gpio_init(void) | ||
| 401 | { | ||
| 402 | int rc; | ||
| 403 | |||
| 404 | rc = platform_driver_register(&msm_gpio_driver); | ||
| 405 | if (!rc) { | ||
| 406 | rc = platform_device_register(&msm_device_gpio); | ||
| 407 | if (rc) | ||
| 408 | platform_driver_unregister(&msm_gpio_driver); | ||
| 409 | } | ||
| 410 | |||
| 411 | return rc; | ||
| 412 | } | ||
| 413 | |||
| 414 | static void __exit msm_gpio_exit(void) | ||
| 415 | { | ||
| 416 | platform_device_unregister(&msm_device_gpio); | ||
| 417 | platform_driver_unregister(&msm_gpio_driver); | ||
| 418 | } | ||
| 419 | |||
| 420 | postcore_initcall(msm_gpio_init); | ||
| 421 | module_exit(msm_gpio_exit); | ||
| 422 | |||
| 423 | MODULE_AUTHOR("Gregory Bean <gbean@codeaurora.org>"); | ||
| 424 | MODULE_DESCRIPTION("Driver for Qualcomm MSM TLMMv2 SoC GPIOs"); | ||
| 425 | MODULE_LICENSE("GPL v2"); | ||
| 426 | MODULE_ALIAS("platform:msmgpio"); | ||
diff --git a/arch/arm/mach-msm/headsmp.S b/arch/arm/mach-msm/headsmp.S new file mode 100644 index 000000000000..d0c214338df9 --- /dev/null +++ b/arch/arm/mach-msm/headsmp.S | |||
| @@ -0,0 +1,40 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-realview/headsmp.S | ||
| 3 | * | ||
| 4 | * Copyright (c) 2003 ARM Limited | ||
| 5 | * All Rights Reserved | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #include <linux/linkage.h> | ||
| 12 | #include <linux/init.h> | ||
| 13 | |||
| 14 | __INIT | ||
| 15 | |||
| 16 | /* | ||
| 17 | * MSM specific entry point for secondary CPUs. This provides | ||
| 18 | * a "holding pen" into which all secondary cores are held until we're | ||
| 19 | * ready for them to initialise. | ||
| 20 | */ | ||
| 21 | ENTRY(msm_secondary_startup) | ||
| 22 | mrc p15, 0, r0, c0, c0, 5 | ||
| 23 | and r0, r0, #15 | ||
| 24 | adr r4, 1f | ||
| 25 | ldmia r4, {r5, r6} | ||
| 26 | sub r4, r4, r5 | ||
| 27 | add r6, r6, r4 | ||
| 28 | pen: ldr r7, [r6] | ||
| 29 | cmp r7, r0 | ||
| 30 | bne pen | ||
| 31 | |||
| 32 | /* | ||
| 33 | * we've been released from the holding pen: secondary_stack | ||
| 34 | * should now contain the SVC stack for this core | ||
| 35 | */ | ||
| 36 | b secondary_startup | ||
| 37 | |||
| 38 | .align | ||
| 39 | 1: .long . | ||
| 40 | .long pen_release | ||
diff --git a/arch/arm/mach-msm/hotplug.c b/arch/arm/mach-msm/hotplug.c new file mode 100644 index 000000000000..5a31f70dfb8e --- /dev/null +++ b/arch/arm/mach-msm/hotplug.c | |||
| @@ -0,0 +1,91 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2002 ARM Ltd. | ||
| 3 | * All Rights Reserved | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License version 2 as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <linux/kernel.h> | ||
| 10 | #include <linux/errno.h> | ||
| 11 | #include <linux/smp.h> | ||
| 12 | |||
| 13 | #include <asm/cacheflush.h> | ||
| 14 | |||
| 15 | extern volatile int pen_release; | ||
| 16 | |||
| 17 | static inline void cpu_enter_lowpower(void) | ||
| 18 | { | ||
| 19 | /* Just flush the cache. Changing the coherency is not yet | ||
| 20 | * available on msm. */ | ||
| 21 | flush_cache_all(); | ||
| 22 | } | ||
| 23 | |||
| 24 | static inline void cpu_leave_lowpower(void) | ||
| 25 | { | ||
| 26 | } | ||
| 27 | |||
| 28 | static inline void platform_do_lowpower(unsigned int cpu) | ||
| 29 | { | ||
| 30 | /* Just enter wfi for now. TODO: Properly shut off the cpu. */ | ||
| 31 | for (;;) { | ||
| 32 | /* | ||
| 33 | * here's the WFI | ||
| 34 | */ | ||
| 35 | asm("wfi" | ||
| 36 | : | ||
| 37 | : | ||
| 38 | : "memory", "cc"); | ||
| 39 | |||
| 40 | if (pen_release == cpu) { | ||
| 41 | /* | ||
| 42 | * OK, proper wakeup, we're done | ||
| 43 | */ | ||
| 44 | break; | ||
| 45 | } | ||
| 46 | |||
| 47 | /* | ||
| 48 | * getting here, means that we have come out of WFI without | ||
| 49 | * having been woken up - this shouldn't happen | ||
| 50 | * | ||
| 51 | * The trouble is, letting people know about this is not really | ||
| 52 | * possible, since we are currently running incoherently, and | ||
| 53 | * therefore cannot safely call printk() or anything else | ||
| 54 | */ | ||
| 55 | pr_debug("CPU%u: spurious wakeup call\n", cpu); | ||
| 56 | } | ||
| 57 | } | ||
| 58 | |||
| 59 | int platform_cpu_kill(unsigned int cpu) | ||
| 60 | { | ||
| 61 | return 1; | ||
| 62 | } | ||
| 63 | |||
| 64 | /* | ||
| 65 | * platform-specific code to shutdown a CPU | ||
| 66 | * | ||
| 67 | * Called with IRQs disabled | ||
| 68 | */ | ||
| 69 | void platform_cpu_die(unsigned int cpu) | ||
| 70 | { | ||
| 71 | /* | ||
| 72 | * we're ready for shutdown now, so do it | ||
| 73 | */ | ||
| 74 | cpu_enter_lowpower(); | ||
| 75 | platform_do_lowpower(cpu); | ||
| 76 | |||
| 77 | /* | ||
| 78 | * bring this CPU back into the world of cache | ||
| 79 | * coherency, and then restore interrupts | ||
| 80 | */ | ||
| 81 | cpu_leave_lowpower(); | ||
| 82 | } | ||
| 83 | |||
| 84 | int platform_cpu_disable(unsigned int cpu) | ||
| 85 | { | ||
| 86 | /* | ||
| 87 | * we don't allow CPU 0 to be shutdown (it is still too special | ||
| 88 | * e.g. clock tick interrupts) | ||
| 89 | */ | ||
| 90 | return cpu == 0 ? -EPERM : 0; | ||
| 91 | } | ||
diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h index 218ef5732a24..296c0f10f230 100644 --- a/arch/arm/mach-msm/include/mach/iommu.h +++ b/arch/arm/mach-msm/include/mach/iommu.h | |||
| @@ -20,13 +20,26 @@ | |||
| 20 | 20 | ||
| 21 | #include <linux/interrupt.h> | 21 | #include <linux/interrupt.h> |
| 22 | 22 | ||
| 23 | /* Sharability attributes of MSM IOMMU mappings */ | ||
| 24 | #define MSM_IOMMU_ATTR_NON_SH 0x0 | ||
| 25 | #define MSM_IOMMU_ATTR_SH 0x4 | ||
| 26 | |||
| 27 | /* Cacheability attributes of MSM IOMMU mappings */ | ||
| 28 | #define MSM_IOMMU_ATTR_NONCACHED 0x0 | ||
| 29 | #define MSM_IOMMU_ATTR_CACHED_WB_WA 0x1 | ||
| 30 | #define MSM_IOMMU_ATTR_CACHED_WB_NWA 0x2 | ||
| 31 | #define MSM_IOMMU_ATTR_CACHED_WT 0x3 | ||
| 32 | |||
| 33 | /* Mask for the cache policy attribute */ | ||
| 34 | #define MSM_IOMMU_CP_MASK 0x03 | ||
| 35 | |||
| 23 | /* Maximum number of Machine IDs that we are allowing to be mapped to the same | 36 | /* Maximum number of Machine IDs that we are allowing to be mapped to the same |
| 24 | * context bank. The number of MIDs mapped to the same CB does not affect | 37 | * context bank. The number of MIDs mapped to the same CB does not affect |
| 25 | * performance, but there is a practical limit on how many distinct MIDs may | 38 | * performance, but there is a practical limit on how many distinct MIDs may |
| 26 | * be present. These mappings are typically determined at design time and are | 39 | * be present. These mappings are typically determined at design time and are |
| 27 | * not expected to change at run time. | 40 | * not expected to change at run time. |
| 28 | */ | 41 | */ |
| 29 | #define MAX_NUM_MIDS 16 | 42 | #define MAX_NUM_MIDS 32 |
| 30 | 43 | ||
| 31 | /** | 44 | /** |
| 32 | * struct msm_iommu_dev - a single IOMMU hardware instance | 45 | * struct msm_iommu_dev - a single IOMMU hardware instance |
diff --git a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h index f9386d3a2f77..c2c3da9444f4 100644 --- a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h +++ b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h | |||
| @@ -54,6 +54,7 @@ do { \ | |||
| 54 | 54 | ||
| 55 | #define NUM_FL_PTE 4096 | 55 | #define NUM_FL_PTE 4096 |
| 56 | #define NUM_SL_PTE 256 | 56 | #define NUM_SL_PTE 256 |
| 57 | #define NUM_TEX_CLASS 8 | ||
| 57 | 58 | ||
| 58 | /* First-level page table bits */ | 59 | /* First-level page table bits */ |
| 59 | #define FL_BASE_MASK 0xFFFFFC00 | 60 | #define FL_BASE_MASK 0xFFFFFC00 |
| @@ -63,6 +64,9 @@ do { \ | |||
| 63 | #define FL_AP_WRITE (1 << 10) | 64 | #define FL_AP_WRITE (1 << 10) |
| 64 | #define FL_AP_READ (1 << 11) | 65 | #define FL_AP_READ (1 << 11) |
| 65 | #define FL_SHARED (1 << 16) | 66 | #define FL_SHARED (1 << 16) |
| 67 | #define FL_BUFFERABLE (1 << 2) | ||
| 68 | #define FL_CACHEABLE (1 << 3) | ||
| 69 | #define FL_TEX0 (1 << 12) | ||
| 66 | #define FL_OFFSET(va) (((va) & 0xFFF00000) >> 20) | 70 | #define FL_OFFSET(va) (((va) & 0xFFF00000) >> 20) |
| 67 | 71 | ||
| 68 | /* Second-level page table bits */ | 72 | /* Second-level page table bits */ |
| @@ -73,8 +77,20 @@ do { \ | |||
| 73 | #define SL_AP0 (1 << 4) | 77 | #define SL_AP0 (1 << 4) |
| 74 | #define SL_AP1 (2 << 4) | 78 | #define SL_AP1 (2 << 4) |
| 75 | #define SL_SHARED (1 << 10) | 79 | #define SL_SHARED (1 << 10) |
| 80 | #define SL_BUFFERABLE (1 << 2) | ||
| 81 | #define SL_CACHEABLE (1 << 3) | ||
| 82 | #define SL_TEX0 (1 << 6) | ||
| 76 | #define SL_OFFSET(va) (((va) & 0xFF000) >> 12) | 83 | #define SL_OFFSET(va) (((va) & 0xFF000) >> 12) |
| 77 | 84 | ||
| 85 | /* Memory type and cache policy attributes */ | ||
| 86 | #define MT_SO 0 | ||
| 87 | #define MT_DEV 1 | ||
| 88 | #define MT_NORMAL 2 | ||
| 89 | #define CP_NONCACHED 0 | ||
| 90 | #define CP_WB_WA 1 | ||
| 91 | #define CP_WT 2 | ||
| 92 | #define CP_WB_NWA 3 | ||
| 93 | |||
| 78 | /* Global register setters / getters */ | 94 | /* Global register setters / getters */ |
| 79 | #define SET_M2VCBR_N(b, N, v) SET_GLOBAL_REG_N(M2VCBR_N, N, (b), (v)) | 95 | #define SET_M2VCBR_N(b, N, v) SET_GLOBAL_REG_N(M2VCBR_N, N, (b), (v)) |
| 80 | #define SET_CBACR_N(b, N, v) SET_GLOBAL_REG_N(CBACR_N, N, (b), (v)) | 96 | #define SET_CBACR_N(b, N, v) SET_GLOBAL_REG_N(CBACR_N, N, (b), (v)) |
| @@ -706,7 +722,9 @@ do { \ | |||
| 706 | #define GET_OCPC5(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC5) | 722 | #define GET_OCPC5(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC5) |
| 707 | #define GET_OCPC6(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC6) | 723 | #define GET_OCPC6(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC6) |
| 708 | #define GET_OCPC7(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC7) | 724 | #define GET_OCPC7(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC7) |
| 709 | 725 | #define NMRR_ICP(nmrr, n) (((nmrr) & (3 << ((n) * 2))) >> ((n) * 2)) | |
| 726 | #define NMRR_OCP(nmrr, n) (((nmrr) & (3 << ((n) * 2 + 16))) >> \ | ||
| 727 | ((n) * 2 + 16)) | ||
| 710 | 728 | ||
| 711 | /* PAR */ | 729 | /* PAR */ |
| 712 | #define GET_FAULT(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT) | 730 | #define GET_FAULT(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT) |
| @@ -750,6 +768,8 @@ do { \ | |||
| 750 | #define GET_NOS5(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS5) | 768 | #define GET_NOS5(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS5) |
| 751 | #define GET_NOS6(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS6) | 769 | #define GET_NOS6(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS6) |
| 752 | #define GET_NOS7(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS7) | 770 | #define GET_NOS7(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS7) |
| 771 | #define PRRR_NOS(prrr, n) ((prrr) & (1 << ((n) + 24)) ? 1 : 0) | ||
| 772 | #define PRRR_MT(prrr, n) ((((prrr) & (3 << ((n) * 2))) >> ((n) * 2))) | ||
| 753 | 773 | ||
| 754 | 774 | ||
| 755 | /* RESUME */ | 775 | /* RESUME */ |
diff --git a/arch/arm/mach-msm/include/mach/irqs-8x60.h b/arch/arm/mach-msm/include/mach/irqs-8x60.h index 36074cfc9ad2..f65841c74c0b 100644 --- a/arch/arm/mach-msm/include/mach/irqs-8x60.h +++ b/arch/arm/mach-msm/include/mach/irqs-8x60.h | |||
| @@ -237,7 +237,12 @@ | |||
| 237 | #define GSBI11_QUP_IRQ (GIC_SPI_START + 194) | 237 | #define GSBI11_QUP_IRQ (GIC_SPI_START + 194) |
| 238 | #define INT_UART12DM_IRQ (GIC_SPI_START + 195) | 238 | #define INT_UART12DM_IRQ (GIC_SPI_START + 195) |
| 239 | #define GSBI12_QUP_IRQ (GIC_SPI_START + 196) | 239 | #define GSBI12_QUP_IRQ (GIC_SPI_START + 196) |
| 240 | /*SPI 197 to 216 arent used in 8x60*/ | 240 | |
| 241 | /*SPI 197 to 209 arent used in 8x60*/ | ||
| 242 | #define SMMU_GFX2D1_CB_SC_SECURE_IRQ (GIC_SPI_START + 210) | ||
| 243 | #define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 211) | ||
| 244 | |||
| 245 | /*SPI 212 to 216 arent used in 8x60*/ | ||
| 241 | #define SMPSS_SPARE_1 (GIC_SPI_START + 217) | 246 | #define SMPSS_SPARE_1 (GIC_SPI_START + 217) |
| 242 | #define SMPSS_SPARE_2 (GIC_SPI_START + 218) | 247 | #define SMPSS_SPARE_2 (GIC_SPI_START + 218) |
| 243 | #define SMPSS_SPARE_3 (GIC_SPI_START + 219) | 248 | #define SMPSS_SPARE_3 (GIC_SPI_START + 219) |
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h index 8a00c2defbc1..0fd7b68ca114 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h | |||
| @@ -119,4 +119,7 @@ | |||
| 119 | #define MSM_AD5_PHYS 0xA7000000 | 119 | #define MSM_AD5_PHYS 0xA7000000 |
| 120 | #define MSM_AD5_SIZE (SZ_1M*13) | 120 | #define MSM_AD5_SIZE (SZ_1M*13) |
| 121 | 121 | ||
| 122 | #define MSM_HSUSB_PHYS 0xA3600000 | ||
| 123 | #define MSM_HSUSB_SIZE SZ_1K | ||
| 124 | |||
| 122 | #endif | 125 | #endif |
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h index 45bab50e3ee6..a54e33b0882e 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h | |||
| @@ -60,7 +60,11 @@ | |||
| 60 | 60 | ||
| 61 | #define MSM_TMR_BASE IOMEM(0xF0200000) | 61 | #define MSM_TMR_BASE IOMEM(0xF0200000) |
| 62 | #define MSM_TMR_PHYS 0x02000000 | 62 | #define MSM_TMR_PHYS 0x02000000 |
| 63 | #define MSM_TMR_SIZE (SZ_1M) | 63 | #define MSM_TMR_SIZE SZ_4K |
| 64 | |||
| 65 | #define MSM_TMR0_BASE IOMEM(0xF0201000) | ||
| 66 | #define MSM_TMR0_PHYS 0x02040000 | ||
| 67 | #define MSM_TMR0_SIZE SZ_4K | ||
| 64 | 68 | ||
| 65 | #define MSM_GPT_BASE (MSM_TMR_BASE + 0x4) | 69 | #define MSM_GPT_BASE (MSM_TMR_BASE + 0x4) |
| 66 | #define MSM_DGT_BASE (MSM_TMR_BASE + 0x24) | 70 | #define MSM_DGT_BASE (MSM_TMR_BASE + 0x24) |
| @@ -98,4 +102,7 @@ | |||
| 98 | #define MSM_IOMMU_GFX2D0_PHYS 0x07D00000 | 102 | #define MSM_IOMMU_GFX2D0_PHYS 0x07D00000 |
| 99 | #define MSM_IOMMU_GFX2D0_SIZE SZ_1M | 103 | #define MSM_IOMMU_GFX2D0_SIZE SZ_1M |
| 100 | 104 | ||
| 105 | #define MSM_IOMMU_GFX2D1_PHYS 0x07E00000 | ||
| 106 | #define MSM_IOMMU_GFX2D1_SIZE SZ_1M | ||
| 107 | |||
| 101 | #endif | 108 | #endif |
diff --git a/arch/arm/mach-msm/include/mach/smp.h b/arch/arm/mach-msm/include/mach/smp.h index 3ff7bf5e679e..a95f7b9efe31 100644 --- a/arch/arm/mach-msm/include/mach/smp.h +++ b/arch/arm/mach-msm/include/mach/smp.h | |||
| @@ -31,9 +31,9 @@ | |||
| 31 | 31 | ||
| 32 | #include <asm/hardware/gic.h> | 32 | #include <asm/hardware/gic.h> |
| 33 | 33 | ||
| 34 | static inline void smp_cross_call(const struct cpumask *mask) | 34 | static inline void smp_cross_call(const struct cpumask *mask, int ipi) |
| 35 | { | 35 | { |
| 36 | gic_raise_softirq(mask, 1); | 36 | gic_raise_softirq(mask, ipi); |
| 37 | } | 37 | } |
| 38 | 38 | ||
| 39 | #endif | 39 | #endif |
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c index d36b61074146..800f327a7ecc 100644 --- a/arch/arm/mach-msm/io.c +++ b/arch/arm/mach-msm/io.c | |||
| @@ -105,6 +105,7 @@ static struct map_desc msm8x60_io_desc[] __initdata = { | |||
| 105 | MSM_DEVICE(QGIC_DIST), | 105 | MSM_DEVICE(QGIC_DIST), |
| 106 | MSM_DEVICE(QGIC_CPU), | 106 | MSM_DEVICE(QGIC_CPU), |
| 107 | MSM_DEVICE(TMR), | 107 | MSM_DEVICE(TMR), |
| 108 | MSM_DEVICE(TMR0), | ||
| 108 | MSM_DEVICE(ACC), | 109 | MSM_DEVICE(ACC), |
| 109 | MSM_DEVICE(GCC), | 110 | MSM_DEVICE(GCC), |
| 110 | }; | 111 | }; |
| @@ -163,3 +164,4 @@ __msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) | |||
| 163 | return __arm_ioremap_caller(phys_addr, size, mtype, | 164 | return __arm_ioremap_caller(phys_addr, size, mtype, |
| 164 | __builtin_return_address(0)); | 165 | __builtin_return_address(0)); |
| 165 | } | 166 | } |
| 167 | EXPORT_SYMBOL(__msm_ioremap); | ||
diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c index f71747db3bee..e2d58e4cb0d7 100644 --- a/arch/arm/mach-msm/iommu.c +++ b/arch/arm/mach-msm/iommu.c | |||
| @@ -33,6 +33,16 @@ | |||
| 33 | #include <mach/iommu_hw-8xxx.h> | 33 | #include <mach/iommu_hw-8xxx.h> |
| 34 | #include <mach/iommu.h> | 34 | #include <mach/iommu.h> |
| 35 | 35 | ||
| 36 | #define MRC(reg, processor, op1, crn, crm, op2) \ | ||
| 37 | __asm__ __volatile__ ( \ | ||
| 38 | " mrc " #processor "," #op1 ", %0," #crn "," #crm "," #op2 "\n" \ | ||
| 39 | : "=r" (reg)) | ||
| 40 | |||
| 41 | #define RCP15_PRRR(reg) MRC(reg, p15, 0, c10, c2, 0) | ||
| 42 | #define RCP15_NMRR(reg) MRC(reg, p15, 0, c10, c2, 1) | ||
| 43 | |||
| 44 | static int msm_iommu_tex_class[4]; | ||
| 45 | |||
| 36 | DEFINE_SPINLOCK(msm_iommu_lock); | 46 | DEFINE_SPINLOCK(msm_iommu_lock); |
| 37 | 47 | ||
| 38 | struct msm_priv { | 48 | struct msm_priv { |
| @@ -40,23 +50,26 @@ struct msm_priv { | |||
| 40 | struct list_head list_attached; | 50 | struct list_head list_attached; |
| 41 | }; | 51 | }; |
| 42 | 52 | ||
| 43 | static void __flush_iotlb(struct iommu_domain *domain) | 53 | static int __flush_iotlb(struct iommu_domain *domain) |
| 44 | { | 54 | { |
| 45 | struct msm_priv *priv = domain->priv; | 55 | struct msm_priv *priv = domain->priv; |
| 46 | struct msm_iommu_drvdata *iommu_drvdata; | 56 | struct msm_iommu_drvdata *iommu_drvdata; |
| 47 | struct msm_iommu_ctx_drvdata *ctx_drvdata; | 57 | struct msm_iommu_ctx_drvdata *ctx_drvdata; |
| 48 | 58 | int ret = 0; | |
| 49 | #ifndef CONFIG_IOMMU_PGTABLES_L2 | 59 | #ifndef CONFIG_IOMMU_PGTABLES_L2 |
| 50 | unsigned long *fl_table = priv->pgtable; | 60 | unsigned long *fl_table = priv->pgtable; |
| 51 | int i; | 61 | int i; |
| 52 | 62 | ||
| 53 | dmac_flush_range(fl_table, fl_table + SZ_16K); | 63 | if (!list_empty(&priv->list_attached)) { |
| 64 | dmac_flush_range(fl_table, fl_table + SZ_16K); | ||
| 54 | 65 | ||
| 55 | for (i = 0; i < NUM_FL_PTE; i++) | 66 | for (i = 0; i < NUM_FL_PTE; i++) |
| 56 | if ((fl_table[i] & 0x03) == FL_TYPE_TABLE) { | 67 | if ((fl_table[i] & 0x03) == FL_TYPE_TABLE) { |
| 57 | void *sl_table = __va(fl_table[i] & FL_BASE_MASK); | 68 | void *sl_table = __va(fl_table[i] & |
| 58 | dmac_flush_range(sl_table, sl_table + SZ_4K); | 69 | FL_BASE_MASK); |
| 59 | } | 70 | dmac_flush_range(sl_table, sl_table + SZ_4K); |
| 71 | } | ||
| 72 | } | ||
| 60 | #endif | 73 | #endif |
| 61 | 74 | ||
| 62 | list_for_each_entry(ctx_drvdata, &priv->list_attached, attached_elm) { | 75 | list_for_each_entry(ctx_drvdata, &priv->list_attached, attached_elm) { |
| @@ -66,6 +79,8 @@ static void __flush_iotlb(struct iommu_domain *domain) | |||
| 66 | iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent); | 79 | iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent); |
| 67 | SET_CTX_TLBIALL(iommu_drvdata->base, ctx_drvdata->num, 0); | 80 | SET_CTX_TLBIALL(iommu_drvdata->base, ctx_drvdata->num, 0); |
| 68 | } | 81 | } |
| 82 | |||
| 83 | return ret; | ||
| 69 | } | 84 | } |
| 70 | 85 | ||
| 71 | static void __reset_context(void __iomem *base, int ctx) | 86 | static void __reset_context(void __iomem *base, int ctx) |
| @@ -95,6 +110,7 @@ static void __reset_context(void __iomem *base, int ctx) | |||
| 95 | 110 | ||
| 96 | static void __program_context(void __iomem *base, int ctx, phys_addr_t pgtable) | 111 | static void __program_context(void __iomem *base, int ctx, phys_addr_t pgtable) |
| 97 | { | 112 | { |
| 113 | unsigned int prrr, nmrr; | ||
| 98 | __reset_context(base, ctx); | 114 | __reset_context(base, ctx); |
| 99 | 115 | ||
| 100 | /* Set up HTW mode */ | 116 | /* Set up HTW mode */ |
| @@ -127,11 +143,11 @@ static void __program_context(void __iomem *base, int ctx, phys_addr_t pgtable) | |||
| 127 | /* Turn on TEX Remap */ | 143 | /* Turn on TEX Remap */ |
| 128 | SET_TRE(base, ctx, 1); | 144 | SET_TRE(base, ctx, 1); |
| 129 | 145 | ||
| 130 | /* Do not configure PRRR / NMRR on the IOMMU for now. We will assume | 146 | /* Set TEX remap attributes */ |
| 131 | * TEX class 0 for everything until attributes are properly worked out | 147 | RCP15_PRRR(prrr); |
| 132 | */ | 148 | RCP15_NMRR(nmrr); |
| 133 | SET_PRRR(base, ctx, 0); | 149 | SET_PRRR(base, ctx, prrr); |
| 134 | SET_NMRR(base, ctx, 0); | 150 | SET_NMRR(base, ctx, nmrr); |
| 135 | 151 | ||
| 136 | /* Turn on BFB prefetch */ | 152 | /* Turn on BFB prefetch */ |
| 137 | SET_BFBDFE(base, ctx, 1); | 153 | SET_BFBDFE(base, ctx, 1); |
| @@ -238,6 +254,11 @@ static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) | |||
| 238 | goto fail; | 254 | goto fail; |
| 239 | } | 255 | } |
| 240 | 256 | ||
| 257 | if (!list_empty(&ctx_drvdata->attached_elm)) { | ||
| 258 | ret = -EBUSY; | ||
| 259 | goto fail; | ||
| 260 | } | ||
| 261 | |||
| 241 | list_for_each_entry(tmp_drvdata, &priv->list_attached, attached_elm) | 262 | list_for_each_entry(tmp_drvdata, &priv->list_attached, attached_elm) |
| 242 | if (tmp_drvdata == ctx_drvdata) { | 263 | if (tmp_drvdata == ctx_drvdata) { |
| 243 | ret = -EBUSY; | 264 | ret = -EBUSY; |
| @@ -248,7 +269,7 @@ static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) | |||
| 248 | __pa(priv->pgtable)); | 269 | __pa(priv->pgtable)); |
| 249 | 270 | ||
| 250 | list_add(&(ctx_drvdata->attached_elm), &priv->list_attached); | 271 | list_add(&(ctx_drvdata->attached_elm), &priv->list_attached); |
| 251 | __flush_iotlb(domain); | 272 | ret = __flush_iotlb(domain); |
| 252 | 273 | ||
| 253 | fail: | 274 | fail: |
| 254 | spin_unlock_irqrestore(&msm_iommu_lock, flags); | 275 | spin_unlock_irqrestore(&msm_iommu_lock, flags); |
| @@ -263,6 +284,7 @@ static void msm_iommu_detach_dev(struct iommu_domain *domain, | |||
| 263 | struct msm_iommu_drvdata *iommu_drvdata; | 284 | struct msm_iommu_drvdata *iommu_drvdata; |
| 264 | struct msm_iommu_ctx_drvdata *ctx_drvdata; | 285 | struct msm_iommu_ctx_drvdata *ctx_drvdata; |
| 265 | unsigned long flags; | 286 | unsigned long flags; |
| 287 | int ret; | ||
| 266 | 288 | ||
| 267 | spin_lock_irqsave(&msm_iommu_lock, flags); | 289 | spin_lock_irqsave(&msm_iommu_lock, flags); |
| 268 | priv = domain->priv; | 290 | priv = domain->priv; |
| @@ -277,7 +299,10 @@ static void msm_iommu_detach_dev(struct iommu_domain *domain, | |||
| 277 | if (!iommu_drvdata || !ctx_drvdata || !ctx_dev) | 299 | if (!iommu_drvdata || !ctx_drvdata || !ctx_dev) |
| 278 | goto fail; | 300 | goto fail; |
| 279 | 301 | ||
| 280 | __flush_iotlb(domain); | 302 | ret = __flush_iotlb(domain); |
| 303 | if (ret) | ||
| 304 | goto fail; | ||
| 305 | |||
| 281 | __reset_context(iommu_drvdata->base, ctx_dev->num); | 306 | __reset_context(iommu_drvdata->base, ctx_dev->num); |
| 282 | list_del_init(&ctx_drvdata->attached_elm); | 307 | list_del_init(&ctx_drvdata->attached_elm); |
| 283 | 308 | ||
| @@ -296,12 +321,21 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va, | |||
| 296 | unsigned long *sl_table; | 321 | unsigned long *sl_table; |
| 297 | unsigned long *sl_pte; | 322 | unsigned long *sl_pte; |
| 298 | unsigned long sl_offset; | 323 | unsigned long sl_offset; |
| 324 | unsigned int pgprot; | ||
| 299 | size_t len = 0x1000UL << order; | 325 | size_t len = 0x1000UL << order; |
| 300 | int ret = 0; | 326 | int ret = 0, tex, sh; |
| 301 | 327 | ||
| 302 | spin_lock_irqsave(&msm_iommu_lock, flags); | 328 | spin_lock_irqsave(&msm_iommu_lock, flags); |
| 303 | priv = domain->priv; | ||
| 304 | 329 | ||
| 330 | sh = (prot & MSM_IOMMU_ATTR_SH) ? 1 : 0; | ||
| 331 | tex = msm_iommu_tex_class[prot & MSM_IOMMU_CP_MASK]; | ||
| 332 | |||
| 333 | if (tex < 0 || tex > NUM_TEX_CLASS - 1) { | ||
| 334 | ret = -EINVAL; | ||
| 335 | goto fail; | ||
| 336 | } | ||
| 337 | |||
| 338 | priv = domain->priv; | ||
| 305 | if (!priv) { | 339 | if (!priv) { |
| 306 | ret = -EINVAL; | 340 | ret = -EINVAL; |
| 307 | goto fail; | 341 | goto fail; |
| @@ -322,6 +356,18 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va, | |||
| 322 | goto fail; | 356 | goto fail; |
| 323 | } | 357 | } |
| 324 | 358 | ||
| 359 | if (len == SZ_16M || len == SZ_1M) { | ||
| 360 | pgprot = sh ? FL_SHARED : 0; | ||
| 361 | pgprot |= tex & 0x01 ? FL_BUFFERABLE : 0; | ||
| 362 | pgprot |= tex & 0x02 ? FL_CACHEABLE : 0; | ||
| 363 | pgprot |= tex & 0x04 ? FL_TEX0 : 0; | ||
| 364 | } else { | ||
| 365 | pgprot = sh ? SL_SHARED : 0; | ||
| 366 | pgprot |= tex & 0x01 ? SL_BUFFERABLE : 0; | ||
| 367 | pgprot |= tex & 0x02 ? SL_CACHEABLE : 0; | ||
| 368 | pgprot |= tex & 0x04 ? SL_TEX0 : 0; | ||
| 369 | } | ||
| 370 | |||
| 325 | fl_offset = FL_OFFSET(va); /* Upper 12 bits */ | 371 | fl_offset = FL_OFFSET(va); /* Upper 12 bits */ |
| 326 | fl_pte = fl_table + fl_offset; /* int pointers, 4 bytes */ | 372 | fl_pte = fl_table + fl_offset; /* int pointers, 4 bytes */ |
| 327 | 373 | ||
| @@ -330,17 +376,17 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va, | |||
| 330 | for (i = 0; i < 16; i++) | 376 | for (i = 0; i < 16; i++) |
| 331 | *(fl_pte+i) = (pa & 0xFF000000) | FL_SUPERSECTION | | 377 | *(fl_pte+i) = (pa & 0xFF000000) | FL_SUPERSECTION | |
| 332 | FL_AP_READ | FL_AP_WRITE | FL_TYPE_SECT | | 378 | FL_AP_READ | FL_AP_WRITE | FL_TYPE_SECT | |
| 333 | FL_SHARED; | 379 | FL_SHARED | pgprot; |
| 334 | } | 380 | } |
| 335 | 381 | ||
| 336 | if (len == SZ_1M) | 382 | if (len == SZ_1M) |
| 337 | *fl_pte = (pa & 0xFFF00000) | FL_AP_READ | FL_AP_WRITE | | 383 | *fl_pte = (pa & 0xFFF00000) | FL_AP_READ | FL_AP_WRITE | |
| 338 | FL_TYPE_SECT | FL_SHARED; | 384 | FL_TYPE_SECT | FL_SHARED | pgprot; |
| 339 | 385 | ||
| 340 | /* Need a 2nd level table */ | 386 | /* Need a 2nd level table */ |
| 341 | if ((len == SZ_4K || len == SZ_64K) && (*fl_pte) == 0) { | 387 | if ((len == SZ_4K || len == SZ_64K) && (*fl_pte) == 0) { |
| 342 | unsigned long *sl; | 388 | unsigned long *sl; |
| 343 | sl = (unsigned long *) __get_free_pages(GFP_KERNEL, | 389 | sl = (unsigned long *) __get_free_pages(GFP_ATOMIC, |
| 344 | get_order(SZ_4K)); | 390 | get_order(SZ_4K)); |
| 345 | 391 | ||
| 346 | if (!sl) { | 392 | if (!sl) { |
| @@ -360,17 +406,17 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va, | |||
| 360 | 406 | ||
| 361 | if (len == SZ_4K) | 407 | if (len == SZ_4K) |
| 362 | *sl_pte = (pa & SL_BASE_MASK_SMALL) | SL_AP0 | SL_AP1 | | 408 | *sl_pte = (pa & SL_BASE_MASK_SMALL) | SL_AP0 | SL_AP1 | |
| 363 | SL_SHARED | SL_TYPE_SMALL; | 409 | SL_SHARED | SL_TYPE_SMALL | pgprot; |
| 364 | 410 | ||
| 365 | if (len == SZ_64K) { | 411 | if (len == SZ_64K) { |
| 366 | int i; | 412 | int i; |
| 367 | 413 | ||
| 368 | for (i = 0; i < 16; i++) | 414 | for (i = 0; i < 16; i++) |
| 369 | *(sl_pte+i) = (pa & SL_BASE_MASK_LARGE) | SL_AP0 | | 415 | *(sl_pte+i) = (pa & SL_BASE_MASK_LARGE) | SL_AP0 | |
| 370 | SL_AP1 | SL_SHARED | SL_TYPE_LARGE; | 416 | SL_AP1 | SL_SHARED | SL_TYPE_LARGE | pgprot; |
| 371 | } | 417 | } |
| 372 | 418 | ||
| 373 | __flush_iotlb(domain); | 419 | ret = __flush_iotlb(domain); |
| 374 | fail: | 420 | fail: |
| 375 | spin_unlock_irqrestore(&msm_iommu_lock, flags); | 421 | spin_unlock_irqrestore(&msm_iommu_lock, flags); |
| 376 | return ret; | 422 | return ret; |
| @@ -455,7 +501,7 @@ static int msm_iommu_unmap(struct iommu_domain *domain, unsigned long va, | |||
| 455 | } | 501 | } |
| 456 | } | 502 | } |
| 457 | 503 | ||
| 458 | __flush_iotlb(domain); | 504 | ret = __flush_iotlb(domain); |
| 459 | fail: | 505 | fail: |
| 460 | spin_unlock_irqrestore(&msm_iommu_lock, flags); | 506 | spin_unlock_irqrestore(&msm_iommu_lock, flags); |
| 461 | return ret; | 507 | return ret; |
| @@ -490,9 +536,6 @@ static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain, | |||
| 490 | SET_CTX_TLBIALL(base, ctx, 0); | 536 | SET_CTX_TLBIALL(base, ctx, 0); |
| 491 | SET_V2PPR_VA(base, ctx, va >> V2Pxx_VA_SHIFT); | 537 | SET_V2PPR_VA(base, ctx, va >> V2Pxx_VA_SHIFT); |
| 492 | 538 | ||
| 493 | if (GET_FAULT(base, ctx)) | ||
| 494 | goto fail; | ||
| 495 | |||
| 496 | par = GET_PAR(base, ctx); | 539 | par = GET_PAR(base, ctx); |
| 497 | 540 | ||
| 498 | /* We are dealing with a supersection */ | 541 | /* We are dealing with a supersection */ |
| @@ -501,6 +544,9 @@ static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain, | |||
| 501 | else /* Upper 20 bits from PAR, lower 12 from VA */ | 544 | else /* Upper 20 bits from PAR, lower 12 from VA */ |
| 502 | ret = (par & 0xFFFFF000) | (va & 0x00000FFF); | 545 | ret = (par & 0xFFFFF000) | (va & 0x00000FFF); |
| 503 | 546 | ||
| 547 | if (GET_FAULT(base, ctx)) | ||
| 548 | ret = 0; | ||
| 549 | |||
| 504 | fail: | 550 | fail: |
| 505 | spin_unlock_irqrestore(&msm_iommu_lock, flags); | 551 | spin_unlock_irqrestore(&msm_iommu_lock, flags); |
| 506 | return ret; | 552 | return ret; |
| @@ -543,8 +589,8 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id) | |||
| 543 | { | 589 | { |
| 544 | struct msm_iommu_drvdata *drvdata = dev_id; | 590 | struct msm_iommu_drvdata *drvdata = dev_id; |
| 545 | void __iomem *base; | 591 | void __iomem *base; |
| 546 | unsigned int fsr = 0; | 592 | unsigned int fsr; |
| 547 | int ncb = 0, i = 0; | 593 | int ncb, i; |
| 548 | 594 | ||
| 549 | spin_lock(&msm_iommu_lock); | 595 | spin_lock(&msm_iommu_lock); |
| 550 | 596 | ||
| @@ -555,7 +601,6 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id) | |||
| 555 | 601 | ||
| 556 | base = drvdata->base; | 602 | base = drvdata->base; |
| 557 | 603 | ||
| 558 | pr_err("===== WOAH! =====\n"); | ||
| 559 | pr_err("Unexpected IOMMU page fault!\n"); | 604 | pr_err("Unexpected IOMMU page fault!\n"); |
| 560 | pr_err("base = %08x\n", (unsigned int) base); | 605 | pr_err("base = %08x\n", (unsigned int) base); |
| 561 | 606 | ||
| @@ -585,8 +630,47 @@ static struct iommu_ops msm_iommu_ops = { | |||
| 585 | .domain_has_cap = msm_iommu_domain_has_cap | 630 | .domain_has_cap = msm_iommu_domain_has_cap |
| 586 | }; | 631 | }; |
| 587 | 632 | ||
| 588 | static int msm_iommu_init(void) | 633 | static int __init get_tex_class(int icp, int ocp, int mt, int nos) |
| 634 | { | ||
| 635 | int i = 0; | ||
| 636 | unsigned int prrr = 0; | ||
| 637 | unsigned int nmrr = 0; | ||
| 638 | int c_icp, c_ocp, c_mt, c_nos; | ||
| 639 | |||
| 640 | RCP15_PRRR(prrr); | ||
| 641 | RCP15_NMRR(nmrr); | ||
| 642 | |||
| 643 | for (i = 0; i < NUM_TEX_CLASS; i++) { | ||
| 644 | c_nos = PRRR_NOS(prrr, i); | ||
| 645 | c_mt = PRRR_MT(prrr, i); | ||
| 646 | c_icp = NMRR_ICP(nmrr, i); | ||
| 647 | c_ocp = NMRR_OCP(nmrr, i); | ||
| 648 | |||
| 649 | if (icp == c_icp && ocp == c_ocp && c_mt == mt && c_nos == nos) | ||
| 650 | return i; | ||
| 651 | } | ||
| 652 | |||
| 653 | return -ENODEV; | ||
| 654 | } | ||
| 655 | |||
| 656 | static void __init setup_iommu_tex_classes(void) | ||
| 657 | { | ||
| 658 | msm_iommu_tex_class[MSM_IOMMU_ATTR_NONCACHED] = | ||
| 659 | get_tex_class(CP_NONCACHED, CP_NONCACHED, MT_NORMAL, 1); | ||
| 660 | |||
| 661 | msm_iommu_tex_class[MSM_IOMMU_ATTR_CACHED_WB_WA] = | ||
| 662 | get_tex_class(CP_WB_WA, CP_WB_WA, MT_NORMAL, 1); | ||
| 663 | |||
| 664 | msm_iommu_tex_class[MSM_IOMMU_ATTR_CACHED_WB_NWA] = | ||
| 665 | get_tex_class(CP_WB_NWA, CP_WB_NWA, MT_NORMAL, 1); | ||
| 666 | |||
| 667 | msm_iommu_tex_class[MSM_IOMMU_ATTR_CACHED_WT] = | ||
| 668 | get_tex_class(CP_WT, CP_WT, MT_NORMAL, 1); | ||
| 669 | } | ||
| 670 | |||
| 671 | static int __init msm_iommu_init(void) | ||
| 589 | { | 672 | { |
| 673 | setup_iommu_tex_classes(); | ||
| 590 | register_iommu(&msm_iommu_ops); | 674 | register_iommu(&msm_iommu_ops); |
| 591 | return 0; | 675 | return 0; |
| 592 | } | 676 | } |
diff --git a/arch/arm/mach-msm/iommu_dev.c b/arch/arm/mach-msm/iommu_dev.c index 9019cee2907b..b83c73b41fd1 100644 --- a/arch/arm/mach-msm/iommu_dev.c +++ b/arch/arm/mach-msm/iommu_dev.c | |||
| @@ -346,7 +346,7 @@ static struct platform_driver msm_iommu_ctx_driver = { | |||
| 346 | .remove = msm_iommu_ctx_remove, | 346 | .remove = msm_iommu_ctx_remove, |
| 347 | }; | 347 | }; |
| 348 | 348 | ||
| 349 | static int msm_iommu_driver_init(void) | 349 | static int __init msm_iommu_driver_init(void) |
| 350 | { | 350 | { |
| 351 | int ret; | 351 | int ret; |
| 352 | ret = platform_driver_register(&msm_iommu_driver); | 352 | ret = platform_driver_register(&msm_iommu_driver); |
| @@ -365,7 +365,7 @@ error: | |||
| 365 | return ret; | 365 | return ret; |
| 366 | } | 366 | } |
| 367 | 367 | ||
| 368 | static void msm_iommu_driver_exit(void) | 368 | static void __exit msm_iommu_driver_exit(void) |
| 369 | { | 369 | { |
| 370 | platform_driver_unregister(&msm_iommu_ctx_driver); | 370 | platform_driver_unregister(&msm_iommu_ctx_driver); |
| 371 | platform_driver_unregister(&msm_iommu_driver); | 371 | platform_driver_unregister(&msm_iommu_driver); |
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c new file mode 100644 index 000000000000..0f427bc94447 --- /dev/null +++ b/arch/arm/mach-msm/platsmp.c | |||
| @@ -0,0 +1,166 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2002 ARM Ltd. | ||
| 3 | * All Rights Reserved | ||
| 4 | * Copyright (c) 2010, Code Aurora Forum. All rights reserved. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/init.h> | ||
| 12 | #include <linux/errno.h> | ||
| 13 | #include <linux/delay.h> | ||
| 14 | #include <linux/device.h> | ||
| 15 | #include <linux/jiffies.h> | ||
| 16 | #include <linux/smp.h> | ||
| 17 | #include <linux/io.h> | ||
| 18 | |||
| 19 | #include <asm/hardware/gic.h> | ||
| 20 | #include <asm/cacheflush.h> | ||
| 21 | #include <asm/mach-types.h> | ||
| 22 | |||
| 23 | #include <mach/msm_iomap.h> | ||
| 24 | |||
| 25 | #include "scm-boot.h" | ||
| 26 | |||
| 27 | #define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0 | ||
| 28 | #define SCSS_CPU1CORE_RESET 0xD80 | ||
| 29 | #define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64 | ||
| 30 | |||
| 31 | /* Mask for edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ | ||
| 32 | #define GIC_PPI_EDGE_MASK 0xFFFFD7FF | ||
| 33 | |||
| 34 | extern void msm_secondary_startup(void); | ||
| 35 | /* | ||
| 36 | * control for which core is the next to come out of the secondary | ||
| 37 | * boot "holding pen". | ||
| 38 | */ | ||
| 39 | volatile int pen_release = -1; | ||
| 40 | |||
| 41 | static DEFINE_SPINLOCK(boot_lock); | ||
| 42 | |||
| 43 | void __cpuinit platform_secondary_init(unsigned int cpu) | ||
| 44 | { | ||
| 45 | /* Configure edge-triggered PPIs */ | ||
| 46 | writel(GIC_PPI_EDGE_MASK, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); | ||
| 47 | |||
| 48 | /* | ||
| 49 | * if any interrupts are already enabled for the primary | ||
| 50 | * core (e.g. timer irq), then they will not have been enabled | ||
| 51 | * for us: do so | ||
| 52 | */ | ||
| 53 | gic_secondary_init(0); | ||
| 54 | |||
| 55 | /* | ||
| 56 | * let the primary processor know we're out of the | ||
| 57 | * pen, then head off into the C entry point | ||
| 58 | */ | ||
| 59 | pen_release = -1; | ||
| 60 | smp_wmb(); | ||
| 61 | |||
| 62 | /* | ||
| 63 | * Synchronise with the boot thread. | ||
| 64 | */ | ||
| 65 | spin_lock(&boot_lock); | ||
| 66 | spin_unlock(&boot_lock); | ||
| 67 | } | ||
| 68 | |||
| 69 | static __cpuinit void prepare_cold_cpu(unsigned int cpu) | ||
| 70 | { | ||
| 71 | int ret; | ||
| 72 | ret = scm_set_boot_addr(virt_to_phys(msm_secondary_startup), | ||
| 73 | SCM_FLAG_COLDBOOT_CPU1); | ||
| 74 | if (ret == 0) { | ||
| 75 | void *sc1_base_ptr; | ||
| 76 | sc1_base_ptr = ioremap_nocache(0x00902000, SZ_4K*2); | ||
| 77 | if (sc1_base_ptr) { | ||
| 78 | writel(0, sc1_base_ptr + VDD_SC1_ARRAY_CLAMP_GFS_CTL); | ||
| 79 | writel(0, sc1_base_ptr + SCSS_CPU1CORE_RESET); | ||
| 80 | writel(3, sc1_base_ptr + SCSS_DBG_STATUS_CORE_PWRDUP); | ||
| 81 | iounmap(sc1_base_ptr); | ||
| 82 | } | ||
| 83 | } else | ||
| 84 | printk(KERN_DEBUG "Failed to set secondary core boot " | ||
| 85 | "address\n"); | ||
| 86 | } | ||
| 87 | |||
| 88 | int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) | ||
| 89 | { | ||
| 90 | unsigned long timeout; | ||
| 91 | static int cold_boot_done; | ||
| 92 | |||
| 93 | /* Only need to bring cpu out of reset this way once */ | ||
| 94 | if (cold_boot_done == false) { | ||
| 95 | prepare_cold_cpu(cpu); | ||
| 96 | cold_boot_done = true; | ||
| 97 | } | ||
| 98 | |||
| 99 | /* | ||
| 100 | * set synchronisation state between this boot processor | ||
| 101 | * and the secondary one | ||
| 102 | */ | ||
| 103 | spin_lock(&boot_lock); | ||
| 104 | |||
| 105 | /* | ||
| 106 | * The secondary processor is waiting to be released from | ||
| 107 | * the holding pen - release it, then wait for it to flag | ||
| 108 | * that it has been released by resetting pen_release. | ||
| 109 | * | ||
| 110 | * Note that "pen_release" is the hardware CPU ID, whereas | ||
| 111 | * "cpu" is Linux's internal ID. | ||
| 112 | */ | ||
| 113 | pen_release = cpu; | ||
| 114 | __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); | ||
| 115 | outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); | ||
| 116 | |||
| 117 | /* | ||
| 118 | * Send the secondary CPU a soft interrupt, thereby causing | ||
| 119 | * the boot monitor to read the system wide flags register, | ||
| 120 | * and branch to the address found there. | ||
| 121 | */ | ||
| 122 | smp_cross_call(cpumask_of(cpu), 1); | ||
| 123 | |||
| 124 | timeout = jiffies + (1 * HZ); | ||
| 125 | while (time_before(jiffies, timeout)) { | ||
| 126 | smp_rmb(); | ||
| 127 | if (pen_release == -1) | ||
| 128 | break; | ||
| 129 | |||
| 130 | udelay(10); | ||
| 131 | } | ||
| 132 | |||
| 133 | /* | ||
| 134 | * now the secondary core is starting up let it run its | ||
| 135 | * calibrations, then wait for it to finish | ||
| 136 | */ | ||
| 137 | spin_unlock(&boot_lock); | ||
| 138 | |||
| 139 | return pen_release != -1 ? -ENOSYS : 0; | ||
| 140 | } | ||
| 141 | |||
| 142 | /* | ||
| 143 | * Initialise the CPU possible map early - this describes the CPUs | ||
| 144 | * which may be present or become present in the system. The msm8x60 | ||
| 145 | * does not support the ARM SCU, so just set the possible cpu mask to | ||
| 146 | * NR_CPUS. | ||
| 147 | */ | ||
| 148 | void __init smp_init_cpus(void) | ||
| 149 | { | ||
| 150 | unsigned int i; | ||
| 151 | |||
| 152 | for (i = 0; i < NR_CPUS; i++) | ||
| 153 | set_cpu_possible(i, true); | ||
| 154 | } | ||
| 155 | |||
| 156 | void __init platform_smp_prepare_cpus(unsigned int max_cpus) | ||
| 157 | { | ||
| 158 | int i; | ||
| 159 | |||
| 160 | /* | ||
| 161 | * Initialise the present map, which describes the set of CPUs | ||
| 162 | * actually populated at the present time. | ||
| 163 | */ | ||
| 164 | for (i = 0; i < max_cpus; i++) | ||
| 165 | set_cpu_present(i, true); | ||
| 166 | } | ||
diff --git a/arch/arm/mach-msm/scm-boot.c b/arch/arm/mach-msm/scm-boot.c new file mode 100644 index 000000000000..45cee3e469a5 --- /dev/null +++ b/arch/arm/mach-msm/scm-boot.c | |||
| @@ -0,0 +1,39 @@ | |||
| 1 | /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. | ||
| 2 | * | ||
| 3 | * This program is free software; you can redistribute it and/or modify | ||
| 4 | * it under the terms of the GNU General Public License version 2 and | ||
| 5 | * only version 2 as published by the Free Software Foundation. | ||
| 6 | * | ||
| 7 | * This program is distributed in the hope that it will be useful, | ||
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 10 | * GNU General Public License for more details. | ||
| 11 | * | ||
| 12 | * You should have received a copy of the GNU General Public License | ||
| 13 | * along with this program; if not, write to the Free Software | ||
| 14 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | ||
| 15 | * 02110-1301, USA. | ||
| 16 | */ | ||
| 17 | |||
| 18 | #include <linux/module.h> | ||
| 19 | #include <linux/slab.h> | ||
| 20 | |||
| 21 | #include "scm.h" | ||
| 22 | #include "scm-boot.h" | ||
| 23 | |||
| 24 | /* | ||
| 25 | * Set the cold/warm boot address for one of the CPU cores. | ||
| 26 | */ | ||
| 27 | int scm_set_boot_addr(phys_addr_t addr, int flags) | ||
| 28 | { | ||
| 29 | struct { | ||
| 30 | unsigned int flags; | ||
| 31 | phys_addr_t addr; | ||
| 32 | } cmd; | ||
| 33 | |||
| 34 | cmd.addr = addr; | ||
| 35 | cmd.flags = flags; | ||
| 36 | return scm_call(SCM_SVC_BOOT, SCM_BOOT_ADDR, | ||
| 37 | &cmd, sizeof(cmd), NULL, 0); | ||
| 38 | } | ||
| 39 | EXPORT_SYMBOL(scm_set_boot_addr); | ||
diff --git a/arch/arm/mach-msm/scm-boot.h b/arch/arm/mach-msm/scm-boot.h new file mode 100644 index 000000000000..68f9b6153d74 --- /dev/null +++ b/arch/arm/mach-msm/scm-boot.h | |||
| @@ -0,0 +1,38 @@ | |||
| 1 | /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. | ||
| 2 | * | ||
| 3 | * Redistribution and use in source and binary forms, with or without | ||
| 4 | * modification, are permitted provided that the following conditions are | ||
| 5 | * met: | ||
| 6 | * * Redistributions of source code must retain the above copyright | ||
| 7 | * notice, this list of conditions and the following disclaimer. | ||
| 8 | * * Redistributions in binary form must reproduce the above | ||
| 9 | * copyright notice, this list of conditions and the following | ||
| 10 | * disclaimer in the documentation and/or other materials provided | ||
| 11 | * with the distribution. | ||
| 12 | * * Neither the name of Code Aurora Forum, Inc. nor the names of its | ||
| 13 | * contributors may be used to endorse or promote products derived | ||
| 14 | * from this software without specific prior written permission. | ||
| 15 | * | ||
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | ||
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT | ||
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS | ||
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | ||
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | ||
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | ||
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | ||
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 27 | */ | ||
| 28 | #ifndef __MACH_SCM_BOOT_H | ||
| 29 | #define __MACH_SCM_BOOT_H | ||
| 30 | |||
| 31 | #define SCM_BOOT_ADDR 0x1 | ||
| 32 | #define SCM_FLAG_COLDBOOT_CPU1 0x1 | ||
| 33 | #define SCM_FLAG_WARMBOOT_CPU1 0x2 | ||
| 34 | #define SCM_FLAG_WARMBOOT_CPU0 0x4 | ||
| 35 | |||
| 36 | int scm_set_boot_addr(phys_addr_t addr, int flags); | ||
| 37 | |||
| 38 | #endif | ||
diff --git a/arch/arm/mach-msm/scm.c b/arch/arm/mach-msm/scm.c new file mode 100644 index 000000000000..f4b9bc90d6a7 --- /dev/null +++ b/arch/arm/mach-msm/scm.c | |||
| @@ -0,0 +1,287 @@ | |||
| 1 | /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. | ||
| 2 | * | ||
| 3 | * This program is free software; you can redistribute it and/or modify | ||
| 4 | * it under the terms of the GNU General Public License version 2 and | ||
| 5 | * only version 2 as published by the Free Software Foundation. | ||
| 6 | * | ||
| 7 | * This program is distributed in the hope that it will be useful, | ||
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 10 | * GNU General Public License for more details. | ||
| 11 | * | ||
| 12 | * You should have received a copy of the GNU General Public License | ||
| 13 | * along with this program; if not, write to the Free Software | ||
| 14 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | ||
| 15 | * 02110-1301, USA. | ||
| 16 | */ | ||
| 17 | |||
| 18 | #include <linux/slab.h> | ||
| 19 | #include <linux/io.h> | ||
| 20 | #include <linux/module.h> | ||
| 21 | #include <linux/mutex.h> | ||
| 22 | #include <linux/errno.h> | ||
| 23 | #include <linux/err.h> | ||
| 24 | |||
| 25 | #include <asm/cacheflush.h> | ||
| 26 | |||
| 27 | #include "scm.h" | ||
| 28 | |||
| 29 | /* Cache line size for msm8x60 */ | ||
| 30 | #define CACHELINESIZE 32 | ||
| 31 | |||
| 32 | #define SCM_ENOMEM -5 | ||
| 33 | #define SCM_EOPNOTSUPP -4 | ||
| 34 | #define SCM_EINVAL_ADDR -3 | ||
| 35 | #define SCM_EINVAL_ARG -2 | ||
| 36 | #define SCM_ERROR -1 | ||
| 37 | #define SCM_INTERRUPTED 1 | ||
| 38 | |||
| 39 | static DEFINE_MUTEX(scm_lock); | ||
| 40 | |||
| 41 | /** | ||
| 42 | * struct scm_command - one SCM command buffer | ||
| 43 | * @len: total available memory for command and response | ||
| 44 | * @buf_offset: start of command buffer | ||
| 45 | * @resp_hdr_offset: start of response buffer | ||
| 46 | * @id: command to be executed | ||
| 47 | * @buf: buffer returned from scm_get_command_buffer() | ||
| 48 | * | ||
| 49 | * An SCM command is layed out in memory as follows: | ||
| 50 | * | ||
| 51 | * ------------------- <--- struct scm_command | ||
| 52 | * | command header | | ||
| 53 | * ------------------- <--- scm_get_command_buffer() | ||
| 54 | * | command buffer | | ||
| 55 | * ------------------- <--- struct scm_response and | ||
| 56 | * | response header | scm_command_to_response() | ||
| 57 | * ------------------- <--- scm_get_response_buffer() | ||
| 58 | * | response buffer | | ||
| 59 | * ------------------- | ||
| 60 | * | ||
| 61 | * There can be arbitrary padding between the headers and buffers so | ||
| 62 | * you should always use the appropriate scm_get_*_buffer() routines | ||
| 63 | * to access the buffers in a safe manner. | ||
| 64 | */ | ||
| 65 | struct scm_command { | ||
| 66 | u32 len; | ||
| 67 | u32 buf_offset; | ||
| 68 | u32 resp_hdr_offset; | ||
| 69 | u32 id; | ||
| 70 | u32 buf[0]; | ||
| 71 | }; | ||
| 72 | |||
| 73 | /** | ||
| 74 | * struct scm_response - one SCM response buffer | ||
| 75 | * @len: total available memory for response | ||
| 76 | * @buf_offset: start of response data relative to start of scm_response | ||
| 77 | * @is_complete: indicates if the command has finished processing | ||
| 78 | */ | ||
| 79 | struct scm_response { | ||
| 80 | u32 len; | ||
| 81 | u32 buf_offset; | ||
| 82 | u32 is_complete; | ||
| 83 | }; | ||
| 84 | |||
| 85 | /** | ||
| 86 | * alloc_scm_command() - Allocate an SCM command | ||
| 87 | * @cmd_size: size of the command buffer | ||
| 88 | * @resp_size: size of the response buffer | ||
| 89 | * | ||
| 90 | * Allocate an SCM command, including enough room for the command | ||
| 91 | * and response headers as well as the command and response buffers. | ||
| 92 | * | ||
| 93 | * Returns a valid &scm_command on success or %NULL if the allocation fails. | ||
| 94 | */ | ||
| 95 | static struct scm_command *alloc_scm_command(size_t cmd_size, size_t resp_size) | ||
| 96 | { | ||
| 97 | struct scm_command *cmd; | ||
| 98 | size_t len = sizeof(*cmd) + sizeof(struct scm_response) + cmd_size + | ||
| 99 | resp_size; | ||
| 100 | |||
| 101 | cmd = kzalloc(PAGE_ALIGN(len), GFP_KERNEL); | ||
| 102 | if (cmd) { | ||
| 103 | cmd->len = len; | ||
| 104 | cmd->buf_offset = offsetof(struct scm_command, buf); | ||
| 105 | cmd->resp_hdr_offset = cmd->buf_offset + cmd_size; | ||
| 106 | } | ||
| 107 | return cmd; | ||
| 108 | } | ||
| 109 | |||
| 110 | /** | ||
| 111 | * free_scm_command() - Free an SCM command | ||
| 112 | * @cmd: command to free | ||
| 113 | * | ||
| 114 | * Free an SCM command. | ||
| 115 | */ | ||
| 116 | static inline void free_scm_command(struct scm_command *cmd) | ||
| 117 | { | ||
| 118 | kfree(cmd); | ||
| 119 | } | ||
| 120 | |||
| 121 | /** | ||
| 122 | * scm_command_to_response() - Get a pointer to a scm_response | ||
| 123 | * @cmd: command | ||
| 124 | * | ||
| 125 | * Returns a pointer to a response for a command. | ||
| 126 | */ | ||
| 127 | static inline struct scm_response *scm_command_to_response( | ||
| 128 | const struct scm_command *cmd) | ||
| 129 | { | ||
| 130 | return (void *)cmd + cmd->resp_hdr_offset; | ||
| 131 | } | ||
| 132 | |||
| 133 | /** | ||
| 134 | * scm_get_command_buffer() - Get a pointer to a command buffer | ||
| 135 | * @cmd: command | ||
| 136 | * | ||
| 137 | * Returns a pointer to the command buffer of a command. | ||
| 138 | */ | ||
| 139 | static inline void *scm_get_command_buffer(const struct scm_command *cmd) | ||
| 140 | { | ||
| 141 | return (void *)cmd->buf; | ||
| 142 | } | ||
| 143 | |||
| 144 | /** | ||
| 145 | * scm_get_response_buffer() - Get a pointer to a response buffer | ||
| 146 | * @rsp: response | ||
| 147 | * | ||
| 148 | * Returns a pointer to a response buffer of a response. | ||
| 149 | */ | ||
| 150 | static inline void *scm_get_response_buffer(const struct scm_response *rsp) | ||
| 151 | { | ||
| 152 | return (void *)rsp + rsp->buf_offset; | ||
| 153 | } | ||
| 154 | |||
| 155 | static int scm_remap_error(int err) | ||
| 156 | { | ||
| 157 | switch (err) { | ||
| 158 | case SCM_ERROR: | ||
| 159 | return -EIO; | ||
| 160 | case SCM_EINVAL_ADDR: | ||
| 161 | case SCM_EINVAL_ARG: | ||
| 162 | return -EINVAL; | ||
| 163 | case SCM_EOPNOTSUPP: | ||
| 164 | return -EOPNOTSUPP; | ||
| 165 | case SCM_ENOMEM: | ||
| 166 | return -ENOMEM; | ||
| 167 | } | ||
| 168 | return -EINVAL; | ||
| 169 | } | ||
| 170 | |||
| 171 | static u32 smc(u32 cmd_addr) | ||
| 172 | { | ||
| 173 | int context_id; | ||
| 174 | register u32 r0 asm("r0") = 1; | ||
| 175 | register u32 r1 asm("r1") = (u32)&context_id; | ||
| 176 | register u32 r2 asm("r2") = cmd_addr; | ||
| 177 | asm( | ||
| 178 | __asmeq("%0", "r0") | ||
| 179 | __asmeq("%1", "r0") | ||
| 180 | __asmeq("%2", "r1") | ||
| 181 | __asmeq("%3", "r2") | ||
| 182 | "smc #0 @ switch to secure world\n" | ||
| 183 | : "=r" (r0) | ||
| 184 | : "r" (r0), "r" (r1), "r" (r2) | ||
| 185 | : "r3"); | ||
| 186 | return r0; | ||
| 187 | } | ||
| 188 | |||
| 189 | static int __scm_call(const struct scm_command *cmd) | ||
| 190 | { | ||
| 191 | int ret; | ||
| 192 | u32 cmd_addr = virt_to_phys(cmd); | ||
| 193 | |||
| 194 | /* | ||
| 195 | * Flush the entire cache here so callers don't have to remember | ||
| 196 | * to flush the cache when passing physical addresses to the secure | ||
| 197 | * side in the buffer. | ||
| 198 | */ | ||
| 199 | flush_cache_all(); | ||
| 200 | do { | ||
| 201 | ret = smc(cmd_addr); | ||
| 202 | if (ret < 0) { | ||
| 203 | ret = scm_remap_error(ret); | ||
| 204 | break; | ||
| 205 | } | ||
| 206 | } while (ret == SCM_INTERRUPTED); | ||
| 207 | |||
| 208 | return ret; | ||
| 209 | } | ||
| 210 | |||
| 211 | /** | ||
| 212 | * scm_call() - Send an SCM command | ||
| 213 | * @svc_id: service identifier | ||
| 214 | * @cmd_id: command identifier | ||
| 215 | * @cmd_buf: command buffer | ||
| 216 | * @cmd_len: length of the command buffer | ||
| 217 | * @resp_buf: response buffer | ||
| 218 | * @resp_len: length of the response buffer | ||
| 219 | * | ||
| 220 | * Sends a command to the SCM and waits for the command to finish processing. | ||
| 221 | */ | ||
| 222 | int scm_call(u32 svc_id, u32 cmd_id, const void *cmd_buf, size_t cmd_len, | ||
| 223 | void *resp_buf, size_t resp_len) | ||
| 224 | { | ||
| 225 | int ret; | ||
| 226 | struct scm_command *cmd; | ||
| 227 | struct scm_response *rsp; | ||
| 228 | |||
| 229 | cmd = alloc_scm_command(cmd_len, resp_len); | ||
| 230 | if (!cmd) | ||
| 231 | return -ENOMEM; | ||
| 232 | |||
| 233 | cmd->id = (svc_id << 10) | cmd_id; | ||
| 234 | if (cmd_buf) | ||
| 235 | memcpy(scm_get_command_buffer(cmd), cmd_buf, cmd_len); | ||
| 236 | |||
| 237 | mutex_lock(&scm_lock); | ||
| 238 | ret = __scm_call(cmd); | ||
| 239 | mutex_unlock(&scm_lock); | ||
| 240 | if (ret) | ||
| 241 | goto out; | ||
| 242 | |||
| 243 | rsp = scm_command_to_response(cmd); | ||
| 244 | do { | ||
| 245 | u32 start = (u32)rsp; | ||
| 246 | u32 end = (u32)scm_get_response_buffer(rsp) + resp_len; | ||
| 247 | start &= ~(CACHELINESIZE - 1); | ||
| 248 | while (start < end) { | ||
| 249 | asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start) | ||
| 250 | : "memory"); | ||
| 251 | start += CACHELINESIZE; | ||
| 252 | } | ||
| 253 | } while (!rsp->is_complete); | ||
| 254 | |||
| 255 | if (resp_buf) | ||
| 256 | memcpy(resp_buf, scm_get_response_buffer(rsp), resp_len); | ||
| 257 | out: | ||
| 258 | free_scm_command(cmd); | ||
| 259 | return ret; | ||
| 260 | } | ||
| 261 | EXPORT_SYMBOL(scm_call); | ||
| 262 | |||
| 263 | u32 scm_get_version(void) | ||
| 264 | { | ||
| 265 | int context_id; | ||
| 266 | static u32 version = -1; | ||
| 267 | register u32 r0 asm("r0") = 0x1 << 8; | ||
| 268 | register u32 r1 asm("r1") = (u32)&context_id; | ||
| 269 | |||
| 270 | if (version != -1) | ||
| 271 | return version; | ||
| 272 | |||
| 273 | mutex_lock(&scm_lock); | ||
| 274 | asm( | ||
| 275 | __asmeq("%0", "r1") | ||
| 276 | __asmeq("%1", "r0") | ||
| 277 | __asmeq("%2", "r1") | ||
| 278 | "smc #0 @ switch to secure world\n" | ||
| 279 | : "=r" (r1) | ||
| 280 | : "r" (r0), "r" (r1) | ||
| 281 | : "r2", "r3"); | ||
| 282 | version = r1; | ||
| 283 | mutex_unlock(&scm_lock); | ||
| 284 | |||
| 285 | return version; | ||
| 286 | } | ||
| 287 | EXPORT_SYMBOL(scm_get_version); | ||
diff --git a/arch/arm/mach-msm/scm.h b/arch/arm/mach-msm/scm.h new file mode 100644 index 000000000000..261786be11c5 --- /dev/null +++ b/arch/arm/mach-msm/scm.h | |||
| @@ -0,0 +1,41 @@ | |||
| 1 | /* Copyright (c) 2010, Code Aurora Forum. All rights reserved. | ||
| 2 | * | ||
| 3 | * Redistribution and use in source and binary forms, with or without | ||
| 4 | * modification, are permitted provided that the following conditions are | ||
| 5 | * met: | ||
| 6 | * * Redistributions of source code must retain the above copyright | ||
| 7 | * notice, this list of conditions and the following disclaimer. | ||
| 8 | * * Redistributions in binary form must reproduce the above | ||
| 9 | * copyright notice, this list of conditions and the following | ||
| 10 | * disclaimer in the documentation and/or other materials provided | ||
| 11 | * with the distribution. | ||
| 12 | * * Neither the name of Code Aurora Forum, Inc. nor the names of its | ||
| 13 | * contributors may be used to endorse or promote products derived | ||
| 14 | * from this software without specific prior written permission. | ||
| 15 | * | ||
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | ||
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT | ||
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS | ||
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | ||
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | ||
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | ||
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | ||
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 27 | */ | ||
| 28 | #ifndef __MACH_SCM_H | ||
| 29 | #define __MACH_SCM_H | ||
| 30 | |||
| 31 | #define SCM_SVC_BOOT 0x1 | ||
| 32 | #define SCM_SVC_PIL 0x2 | ||
| 33 | |||
| 34 | extern int scm_call(u32 svc_id, u32 cmd_id, const void *cmd_buf, size_t cmd_len, | ||
| 35 | void *resp_buf, size_t resp_len); | ||
| 36 | |||
| 37 | #define SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF)) | ||
| 38 | |||
| 39 | extern u32 scm_get_version(void); | ||
| 40 | |||
| 41 | #endif | ||
diff --git a/arch/arm/mach-msm/sirc.c b/arch/arm/mach-msm/sirc.c index b0794524ba6e..152eefda3ce6 100644 --- a/arch/arm/mach-msm/sirc.c +++ b/arch/arm/mach-msm/sirc.c | |||
| @@ -40,9 +40,6 @@ static struct sirc_cascade_regs sirc_reg_table[] = { | |||
| 40 | } | 40 | } |
| 41 | }; | 41 | }; |
| 42 | 42 | ||
| 43 | static unsigned int save_type; | ||
| 44 | static unsigned int save_polarity; | ||
| 45 | |||
| 46 | /* Mask off the given interrupt. Keep the int_enable mask in sync with | 43 | /* Mask off the given interrupt. Keep the int_enable mask in sync with |
| 47 | the enable reg, so it can be restored after power collapse. */ | 44 | the enable reg, so it can be restored after power collapse. */ |
| 48 | static void sirc_irq_mask(unsigned int irq) | 45 | static void sirc_irq_mask(unsigned int irq) |
diff --git a/arch/arm/mach-msm/smd.c b/arch/arm/mach-msm/smd.c index f07dc7c738f0..657be73297db 100644 --- a/arch/arm/mach-msm/smd.c +++ b/arch/arm/mach-msm/smd.c | |||
| @@ -14,6 +14,8 @@ | |||
| 14 | * | 14 | * |
| 15 | */ | 15 | */ |
| 16 | 16 | ||
| 17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | ||
| 18 | |||
| 17 | #include <linux/platform_device.h> | 19 | #include <linux/platform_device.h> |
| 18 | #include <linux/module.h> | 20 | #include <linux/module.h> |
| 19 | #include <linux/fs.h> | 21 | #include <linux/fs.h> |
| @@ -89,7 +91,7 @@ static void smd_diag(void) | |||
| 89 | x = smem_find(ID_DIAG_ERR_MSG, SZ_DIAG_ERR_MSG); | 91 | x = smem_find(ID_DIAG_ERR_MSG, SZ_DIAG_ERR_MSG); |
| 90 | if (x != 0) { | 92 | if (x != 0) { |
| 91 | x[SZ_DIAG_ERR_MSG - 1] = 0; | 93 | x[SZ_DIAG_ERR_MSG - 1] = 0; |
| 92 | pr_info("smem: DIAG '%s'\n", x); | 94 | pr_debug("DIAG '%s'\n", x); |
| 93 | } | 95 | } |
| 94 | } | 96 | } |
| 95 | 97 | ||
| @@ -312,7 +314,7 @@ static void smd_state_change(struct smd_channel *ch, | |||
| 312 | { | 314 | { |
| 313 | ch->last_state = next; | 315 | ch->last_state = next; |
| 314 | 316 | ||
| 315 | pr_info("SMD: ch %d %d -> %d\n", ch->n, last, next); | 317 | pr_debug("ch %d %d -> %d\n", ch->n, last, next); |
| 316 | 318 | ||
| 317 | switch (next) { | 319 | switch (next) { |
| 318 | case SMD_SS_OPENING: | 320 | case SMD_SS_OPENING: |
| @@ -601,7 +603,7 @@ static int smd_alloc_channel(const char *name, uint32_t cid, uint32_t type) | |||
| 601 | ch->pdev.name = ch->name; | 603 | ch->pdev.name = ch->name; |
| 602 | ch->pdev.id = -1; | 604 | ch->pdev.id = -1; |
| 603 | 605 | ||
| 604 | pr_info("smd_alloc_channel() cid=%02d size=%05d '%s'\n", | 606 | pr_debug("smd_alloc_channel() cid=%02d size=%05d '%s'\n", |
| 605 | ch->n, ch->fifo_size, ch->name); | 607 | ch->n, ch->fifo_size, ch->name); |
| 606 | 608 | ||
| 607 | mutex_lock(&smd_creation_mutex); | 609 | mutex_lock(&smd_creation_mutex); |
| @@ -621,7 +623,7 @@ static void smd_channel_probe_worker(struct work_struct *work) | |||
| 621 | 623 | ||
| 622 | shared = smem_find(ID_CH_ALLOC_TBL, sizeof(*shared) * 64); | 624 | shared = smem_find(ID_CH_ALLOC_TBL, sizeof(*shared) * 64); |
| 623 | if (!shared) { | 625 | if (!shared) { |
| 624 | pr_err("smd: cannot find allocation table\n"); | 626 | pr_err("cannot find allocation table\n"); |
| 625 | return; | 627 | return; |
| 626 | } | 628 | } |
| 627 | for (n = 0; n < 64; n++) { | 629 | for (n = 0; n < 64; n++) { |
| @@ -725,8 +727,6 @@ int smd_close(smd_channel_t *ch) | |||
| 725 | { | 727 | { |
| 726 | unsigned long flags; | 728 | unsigned long flags; |
| 727 | 729 | ||
| 728 | pr_info("smd_close(%p)\n", ch); | ||
| 729 | |||
| 730 | if (ch == 0) | 730 | if (ch == 0) |
| 731 | return -1; | 731 | return -1; |
| 732 | 732 | ||
| @@ -939,7 +939,6 @@ int smsm_set_sleep_duration(uint32_t delay) | |||
| 939 | int smd_core_init(void) | 939 | int smd_core_init(void) |
| 940 | { | 940 | { |
| 941 | int r; | 941 | int r; |
| 942 | pr_info("smd_core_init()\n"); | ||
| 943 | 942 | ||
| 944 | /* wait for essential items to be initialized */ | 943 | /* wait for essential items to be initialized */ |
| 945 | for (;;) { | 944 | for (;;) { |
| @@ -992,15 +991,11 @@ int smd_core_init(void) | |||
| 992 | smsm_change_state(SMSM_STATE_APPS_DEM, ~0, 0); | 991 | smsm_change_state(SMSM_STATE_APPS_DEM, ~0, 0); |
| 993 | #endif | 992 | #endif |
| 994 | 993 | ||
| 995 | pr_info("smd_core_init() done\n"); | ||
| 996 | |||
| 997 | return 0; | 994 | return 0; |
| 998 | } | 995 | } |
| 999 | 996 | ||
| 1000 | static int __devinit msm_smd_probe(struct platform_device *pdev) | 997 | static int __devinit msm_smd_probe(struct platform_device *pdev) |
| 1001 | { | 998 | { |
| 1002 | pr_info("smd_init()\n"); | ||
| 1003 | |||
| 1004 | /* | 999 | /* |
| 1005 | * If we haven't waited for the ARM9 to boot up till now, | 1000 | * If we haven't waited for the ARM9 to boot up till now, |
| 1006 | * then we need to wait here. Otherwise this should just | 1001 | * then we need to wait here. Otherwise this should just |
diff --git a/arch/arm/mach-msm/smd_debug.c b/arch/arm/mach-msm/smd_debug.c index f91c3b7bc655..8736afff82f3 100644 --- a/arch/arm/mach-msm/smd_debug.c +++ b/arch/arm/mach-msm/smd_debug.c | |||
| @@ -270,8 +270,10 @@ void smsm_print_sleep_info(void) | |||
| 270 | { | 270 | { |
| 271 | unsigned long flags; | 271 | unsigned long flags; |
| 272 | uint32_t *ptr; | 272 | uint32_t *ptr; |
| 273 | #ifndef CONFIG_ARCH_MSM_SCORPION | ||
| 273 | struct tramp_gpio_smem *gpio; | 274 | struct tramp_gpio_smem *gpio; |
| 274 | struct smsm_interrupt_info *int_info; | 275 | struct smsm_interrupt_info *int_info; |
| 276 | #endif | ||
| 275 | 277 | ||
| 276 | 278 | ||
| 277 | spin_lock_irqsave(&smem_lock, flags); | 279 | spin_lock_irqsave(&smem_lock, flags); |
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index 950100f19d07..c105d28b53e3 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c | |||
| @@ -47,6 +47,19 @@ enum { | |||
| 47 | 47 | ||
| 48 | #define GPT_HZ 32768 | 48 | #define GPT_HZ 32768 |
| 49 | 49 | ||
| 50 | enum timer_location { | ||
| 51 | LOCAL_TIMER = 0, | ||
| 52 | GLOBAL_TIMER = 1, | ||
| 53 | }; | ||
| 54 | |||
| 55 | #ifdef MSM_TMR0_BASE | ||
| 56 | #define MSM_TMR_GLOBAL (MSM_TMR0_BASE - MSM_TMR_BASE) | ||
| 57 | #else | ||
| 58 | #define MSM_TMR_GLOBAL 0 | ||
| 59 | #endif | ||
| 60 | |||
| 61 | #define MSM_GLOBAL_TIMER MSM_CLOCK_DGT | ||
| 62 | |||
| 50 | #if defined(CONFIG_ARCH_QSD8X50) | 63 | #if defined(CONFIG_ARCH_QSD8X50) |
| 51 | #define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */ | 64 | #define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */ |
| 52 | #define MSM_DGT_SHIFT (0) | 65 | #define MSM_DGT_SHIFT (0) |
| @@ -65,49 +78,67 @@ struct msm_clock { | |||
| 65 | void __iomem *regbase; | 78 | void __iomem *regbase; |
| 66 | uint32_t freq; | 79 | uint32_t freq; |
| 67 | uint32_t shift; | 80 | uint32_t shift; |
| 81 | void __iomem *global_counter; | ||
| 82 | void __iomem *local_counter; | ||
| 83 | }; | ||
| 84 | |||
| 85 | enum { | ||
| 86 | MSM_CLOCK_GPT, | ||
| 87 | MSM_CLOCK_DGT, | ||
| 88 | NR_TIMERS, | ||
| 68 | }; | 89 | }; |
| 69 | 90 | ||
| 91 | |||
| 92 | static struct msm_clock msm_clocks[]; | ||
| 93 | static struct clock_event_device *local_clock_event; | ||
| 94 | |||
| 70 | static irqreturn_t msm_timer_interrupt(int irq, void *dev_id) | 95 | static irqreturn_t msm_timer_interrupt(int irq, void *dev_id) |
| 71 | { | 96 | { |
| 72 | struct clock_event_device *evt = dev_id; | 97 | struct clock_event_device *evt = dev_id; |
| 98 | if (smp_processor_id() != 0) | ||
| 99 | evt = local_clock_event; | ||
| 100 | if (evt->event_handler == NULL) | ||
| 101 | return IRQ_HANDLED; | ||
| 73 | evt->event_handler(evt); | 102 | evt->event_handler(evt); |
| 74 | return IRQ_HANDLED; | 103 | return IRQ_HANDLED; |
| 75 | } | 104 | } |
| 76 | 105 | ||
| 77 | static cycle_t msm_gpt_read(struct clocksource *cs) | 106 | static cycle_t msm_read_timer_count(struct clocksource *cs) |
| 78 | { | 107 | { |
| 79 | return readl(MSM_GPT_BASE + TIMER_COUNT_VAL); | 108 | struct msm_clock *clk = container_of(cs, struct msm_clock, clocksource); |
| 109 | |||
| 110 | return readl(clk->global_counter); | ||
| 80 | } | 111 | } |
| 81 | 112 | ||
| 82 | static cycle_t msm_dgt_read(struct clocksource *cs) | 113 | static struct msm_clock *clockevent_to_clock(struct clock_event_device *evt) |
| 83 | { | 114 | { |
| 84 | return readl(MSM_DGT_BASE + TIMER_COUNT_VAL) >> MSM_DGT_SHIFT; | 115 | #ifdef CONFIG_SMP |
| 116 | int i; | ||
| 117 | for (i = 0; i < NR_TIMERS; i++) | ||
| 118 | if (evt == &(msm_clocks[i].clockevent)) | ||
| 119 | return &msm_clocks[i]; | ||
| 120 | return &msm_clocks[MSM_GLOBAL_TIMER]; | ||
| 121 | #else | ||
| 122 | return container_of(evt, struct msm_clock, clockevent); | ||
| 123 | #endif | ||
| 85 | } | 124 | } |
| 86 | 125 | ||
| 87 | static int msm_timer_set_next_event(unsigned long cycles, | 126 | static int msm_timer_set_next_event(unsigned long cycles, |
| 88 | struct clock_event_device *evt) | 127 | struct clock_event_device *evt) |
| 89 | { | 128 | { |
| 90 | struct msm_clock *clock = container_of(evt, struct msm_clock, clockevent); | 129 | struct msm_clock *clock = clockevent_to_clock(evt); |
| 91 | uint32_t now = readl(clock->regbase + TIMER_COUNT_VAL); | 130 | uint32_t now = readl(clock->local_counter); |
| 92 | uint32_t alarm = now + (cycles << clock->shift); | 131 | uint32_t alarm = now + (cycles << clock->shift); |
| 93 | int late; | ||
| 94 | 132 | ||
| 95 | writel(alarm, clock->regbase + TIMER_MATCH_VAL); | 133 | writel(alarm, clock->regbase + TIMER_MATCH_VAL); |
| 96 | now = readl(clock->regbase + TIMER_COUNT_VAL); | ||
| 97 | late = now - alarm; | ||
| 98 | if (late >= (-2 << clock->shift) && late < DGT_HZ*5) { | ||
| 99 | printk(KERN_NOTICE "msm_timer_set_next_event(%lu) clock %s, " | ||
| 100 | "alarm already expired, now %x, alarm %x, late %d\n", | ||
| 101 | cycles, clock->clockevent.name, now, alarm, late); | ||
| 102 | return -ETIME; | ||
| 103 | } | ||
| 104 | return 0; | 134 | return 0; |
| 105 | } | 135 | } |
| 106 | 136 | ||
| 107 | static void msm_timer_set_mode(enum clock_event_mode mode, | 137 | static void msm_timer_set_mode(enum clock_event_mode mode, |
| 108 | struct clock_event_device *evt) | 138 | struct clock_event_device *evt) |
| 109 | { | 139 | { |
| 110 | struct msm_clock *clock = container_of(evt, struct msm_clock, clockevent); | 140 | struct msm_clock *clock = clockevent_to_clock(evt); |
| 141 | |||
| 111 | switch (mode) { | 142 | switch (mode) { |
| 112 | case CLOCK_EVT_MODE_RESUME: | 143 | case CLOCK_EVT_MODE_RESUME: |
| 113 | case CLOCK_EVT_MODE_PERIODIC: | 144 | case CLOCK_EVT_MODE_PERIODIC: |
| @@ -123,7 +154,7 @@ static void msm_timer_set_mode(enum clock_event_mode mode, | |||
| 123 | } | 154 | } |
| 124 | 155 | ||
| 125 | static struct msm_clock msm_clocks[] = { | 156 | static struct msm_clock msm_clocks[] = { |
| 126 | { | 157 | [MSM_CLOCK_GPT] = { |
| 127 | .clockevent = { | 158 | .clockevent = { |
| 128 | .name = "gp_timer", | 159 | .name = "gp_timer", |
| 129 | .features = CLOCK_EVT_FEAT_ONESHOT, | 160 | .features = CLOCK_EVT_FEAT_ONESHOT, |
| @@ -135,9 +166,8 @@ static struct msm_clock msm_clocks[] = { | |||
| 135 | .clocksource = { | 166 | .clocksource = { |
| 136 | .name = "gp_timer", | 167 | .name = "gp_timer", |
| 137 | .rating = 200, | 168 | .rating = 200, |
| 138 | .read = msm_gpt_read, | 169 | .read = msm_read_timer_count, |
| 139 | .mask = CLOCKSOURCE_MASK(32), | 170 | .mask = CLOCKSOURCE_MASK(32), |
| 140 | .shift = 17, | ||
| 141 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 171 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 142 | }, | 172 | }, |
| 143 | .irq = { | 173 | .irq = { |
| @@ -148,9 +178,12 @@ static struct msm_clock msm_clocks[] = { | |||
| 148 | .irq = INT_GP_TIMER_EXP | 178 | .irq = INT_GP_TIMER_EXP |
| 149 | }, | 179 | }, |
| 150 | .regbase = MSM_GPT_BASE, | 180 | .regbase = MSM_GPT_BASE, |
| 151 | .freq = GPT_HZ | 181 | .freq = GPT_HZ, |
| 182 | .local_counter = MSM_GPT_BASE + TIMER_COUNT_VAL, | ||
| 183 | .global_counter = MSM_GPT_BASE + TIMER_COUNT_VAL + | ||
| 184 | MSM_TMR_GLOBAL, | ||
| 152 | }, | 185 | }, |
| 153 | { | 186 | [MSM_CLOCK_DGT] = { |
| 154 | .clockevent = { | 187 | .clockevent = { |
| 155 | .name = "dg_timer", | 188 | .name = "dg_timer", |
| 156 | .features = CLOCK_EVT_FEAT_ONESHOT, | 189 | .features = CLOCK_EVT_FEAT_ONESHOT, |
| @@ -162,9 +195,8 @@ static struct msm_clock msm_clocks[] = { | |||
| 162 | .clocksource = { | 195 | .clocksource = { |
| 163 | .name = "dg_timer", | 196 | .name = "dg_timer", |
| 164 | .rating = 300, | 197 | .rating = 300, |
| 165 | .read = msm_dgt_read, | 198 | .read = msm_read_timer_count, |
| 166 | .mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)), | 199 | .mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)), |
| 167 | .shift = 24 - MSM_DGT_SHIFT, | ||
| 168 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 200 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 169 | }, | 201 | }, |
| 170 | .irq = { | 202 | .irq = { |
| @@ -176,7 +208,10 @@ static struct msm_clock msm_clocks[] = { | |||
| 176 | }, | 208 | }, |
| 177 | .regbase = MSM_DGT_BASE, | 209 | .regbase = MSM_DGT_BASE, |
| 178 | .freq = DGT_HZ >> MSM_DGT_SHIFT, | 210 | .freq = DGT_HZ >> MSM_DGT_SHIFT, |
| 179 | .shift = MSM_DGT_SHIFT | 211 | .shift = MSM_DGT_SHIFT, |
| 212 | .local_counter = MSM_DGT_BASE + TIMER_COUNT_VAL, | ||
| 213 | .global_counter = MSM_DGT_BASE + TIMER_COUNT_VAL + | ||
| 214 | MSM_TMR_GLOBAL, | ||
| 180 | } | 215 | } |
| 181 | }; | 216 | }; |
| 182 | 217 | ||
| @@ -185,7 +220,7 @@ static void __init msm_timer_init(void) | |||
| 185 | int i; | 220 | int i; |
| 186 | int res; | 221 | int res; |
| 187 | 222 | ||
| 188 | #ifdef CONFIG_ARCH_MSM8X60 | 223 | #ifdef CONFIG_ARCH_MSM_SCORPIONMP |
| 189 | writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL); | 224 | writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL); |
| 190 | #endif | 225 | #endif |
| 191 | 226 | ||
| @@ -205,8 +240,7 @@ static void __init msm_timer_init(void) | |||
| 205 | ce->min_delta_ns = clockevent_delta2ns(4, ce); | 240 | ce->min_delta_ns = clockevent_delta2ns(4, ce); |
| 206 | ce->cpumask = cpumask_of(0); | 241 | ce->cpumask = cpumask_of(0); |
| 207 | 242 | ||
| 208 | cs->mult = clocksource_hz2mult(clock->freq, cs->shift); | 243 | res = clocksource_register_hz(cs, clock->freq); |
| 209 | res = clocksource_register(cs); | ||
| 210 | if (res) | 244 | if (res) |
| 211 | printk(KERN_ERR "msm_timer_init: clocksource_register " | 245 | printk(KERN_ERR "msm_timer_init: clocksource_register " |
| 212 | "failed for %s\n", cs->name); | 246 | "failed for %s\n", cs->name); |
| @@ -220,6 +254,48 @@ static void __init msm_timer_init(void) | |||
| 220 | } | 254 | } |
| 221 | } | 255 | } |
| 222 | 256 | ||
| 257 | #ifdef CONFIG_SMP | ||
| 258 | void __cpuinit local_timer_setup(struct clock_event_device *evt) | ||
| 259 | { | ||
| 260 | struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER]; | ||
| 261 | |||
| 262 | /* Use existing clock_event for cpu 0 */ | ||
| 263 | if (!smp_processor_id()) | ||
| 264 | return; | ||
| 265 | |||
| 266 | writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL); | ||
| 267 | |||
| 268 | if (!local_clock_event) { | ||
| 269 | writel(0, clock->regbase + TIMER_ENABLE); | ||
| 270 | writel(0, clock->regbase + TIMER_CLEAR); | ||
| 271 | writel(~0, clock->regbase + TIMER_MATCH_VAL); | ||
| 272 | } | ||
| 273 | evt->irq = clock->irq.irq; | ||
| 274 | evt->name = "local_timer"; | ||
| 275 | evt->features = CLOCK_EVT_FEAT_ONESHOT; | ||
| 276 | evt->rating = clock->clockevent.rating; | ||
| 277 | evt->set_mode = msm_timer_set_mode; | ||
| 278 | evt->set_next_event = msm_timer_set_next_event; | ||
| 279 | evt->shift = clock->clockevent.shift; | ||
| 280 | evt->mult = div_sc(clock->freq, NSEC_PER_SEC, evt->shift); | ||
| 281 | evt->max_delta_ns = | ||
| 282 | clockevent_delta2ns(0xf0000000 >> clock->shift, evt); | ||
| 283 | evt->min_delta_ns = clockevent_delta2ns(4, evt); | ||
| 284 | |||
| 285 | local_clock_event = evt; | ||
| 286 | |||
| 287 | gic_enable_ppi(clock->irq.irq); | ||
| 288 | |||
| 289 | clockevents_register_device(evt); | ||
| 290 | } | ||
| 291 | |||
| 292 | inline int local_timer_ack(void) | ||
| 293 | { | ||
| 294 | return 1; | ||
| 295 | } | ||
| 296 | |||
| 297 | #endif | ||
| 298 | |||
| 223 | struct sys_timer msm_timer = { | 299 | struct sys_timer msm_timer = { |
| 224 | .init = msm_timer_init | 300 | .init = msm_timer_init |
| 225 | }; | 301 | }; |
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index 788bdace1304..3eff39921d4d 100644 --- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h | |||
| @@ -65,7 +65,7 @@ | |||
| 65 | */ | 65 | */ |
| 66 | #define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000) | 66 | #define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000) |
| 67 | #define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE | 0x1500) | 67 | #define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE | 0x1500) |
| 68 | #define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE | 0x1700) | 68 | #define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE | 0x1570) |
| 69 | 69 | ||
| 70 | #define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x10000) | 70 | #define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x10000) |
| 71 | #define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000) | 71 | #define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000) |
diff --git a/arch/arm/mach-mx25/Kconfig b/arch/arm/mach-mx25/Kconfig deleted file mode 100644 index 38ca09a5df9d..000000000000 --- a/arch/arm/mach-mx25/Kconfig +++ /dev/null | |||
| @@ -1,34 +0,0 @@ | |||
| 1 | if ARCH_MX25 | ||
| 2 | |||
| 3 | comment "MX25 platforms:" | ||
| 4 | |||
| 5 | config MACH_MX25_3DS | ||
| 6 | bool "Support MX25PDK (3DS) Platform" | ||
| 7 | select IMX_HAVE_PLATFORM_IMX_UART | ||
| 8 | select IMX_HAVE_PLATFORM_MXC_NAND | ||
| 9 | select IMX_HAVE_PLATFORM_ESDHC | ||
| 10 | |||
| 11 | config MACH_EUKREA_CPUIMX25 | ||
| 12 | bool "Support Eukrea CPUIMX25 Platform" | ||
| 13 | select IMX_HAVE_PLATFORM_IMX_I2C | ||
| 14 | select IMX_HAVE_PLATFORM_IMX_UART | ||
| 15 | select IMX_HAVE_PLATFORM_MXC_NAND | ||
| 16 | select IMX_HAVE_PLATFORM_FLEXCAN | ||
| 17 | select IMX_HAVE_PLATFORM_ESDHC | ||
| 18 | select MXC_ULPI if USB_ULPI | ||
| 19 | |||
| 20 | choice | ||
| 21 | prompt "Baseboard" | ||
| 22 | depends on MACH_EUKREA_CPUIMX25 | ||
| 23 | default MACH_EUKREA_MBIMXSD25_BASEBOARD | ||
| 24 | |||
| 25 | config MACH_EUKREA_MBIMXSD25_BASEBOARD | ||
| 26 | bool "Eukrea MBIMXSD development board" | ||
| 27 | select IMX_HAVE_PLATFORM_IMX_SSI | ||
| 28 | help | ||
| 29 | This adds board specific devices that can be found on Eukrea's | ||
| 30 | MBIMXSD evaluation board. | ||
| 31 | |||
| 32 | endchoice | ||
| 33 | |||
| 34 | endif | ||
diff --git a/arch/arm/mach-mx25/Makefile b/arch/arm/mach-mx25/Makefile deleted file mode 100644 index d9e46ce00a4e..000000000000 --- a/arch/arm/mach-mx25/Makefile +++ /dev/null | |||
| @@ -1,5 +0,0 @@ | |||
| 1 | obj-y := mm.o devices.o | ||
| 2 | obj-$(CONFIG_ARCH_MX25) += clock.o | ||
| 3 | obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o | ||
| 4 | obj-$(CONFIG_MACH_EUKREA_CPUIMX25) += mach-cpuimx25.o | ||
| 5 | obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd-baseboard.o | ||
diff --git a/arch/arm/mach-mx25/Makefile.boot b/arch/arm/mach-mx25/Makefile.boot deleted file mode 100644 index e1dd366f836b..000000000000 --- a/arch/arm/mach-mx25/Makefile.boot +++ /dev/null | |||
| @@ -1,3 +0,0 @@ | |||
| 1 | zreladdr-y := 0x80008000 | ||
| 2 | params_phys-y := 0x80000100 | ||
| 3 | initrd_phys-y := 0x80800000 | ||
diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c deleted file mode 100644 index 1d0eb3e85941..000000000000 --- a/arch/arm/mach-mx25/devices.c +++ /dev/null | |||
| @@ -1,308 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2009 Sascha Hauer, <kernel@pengutronix.de> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation; either version 2 | ||
| 7 | * of the License, or (at your option) any later version. | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License | ||
| 14 | * along with this program; if not, write to the Free Software | ||
| 15 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, | ||
| 16 | * Boston, MA 02110-1301, USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/platform_device.h> | ||
| 20 | #include <linux/dma-mapping.h> | ||
| 21 | #include <linux/gpio.h> | ||
| 22 | #include <mach/mx25.h> | ||
| 23 | #include <mach/irqs.h> | ||
| 24 | |||
| 25 | static u64 otg_dmamask = DMA_BIT_MASK(32); | ||
| 26 | |||
| 27 | static struct resource mxc_otg_resources[] = { | ||
| 28 | { | ||
| 29 | .start = MX25_OTG_BASE_ADDR, | ||
| 30 | .end = MX25_OTG_BASE_ADDR + 0x1ff, | ||
| 31 | .flags = IORESOURCE_MEM, | ||
| 32 | }, { | ||
| 33 | .start = 37, | ||
| 34 | .end = 37, | ||
| 35 | .flags = IORESOURCE_IRQ, | ||
| 36 | }, | ||
| 37 | }; | ||
| 38 | |||
| 39 | struct platform_device mxc_otg = { | ||
| 40 | .name = "mxc-ehci", | ||
| 41 | .id = 0, | ||
| 42 | .dev = { | ||
| 43 | .coherent_dma_mask = 0xffffffff, | ||
| 44 | .dma_mask = &otg_dmamask, | ||
| 45 | }, | ||
| 46 | .resource = mxc_otg_resources, | ||
| 47 | .num_resources = ARRAY_SIZE(mxc_otg_resources), | ||
| 48 | }; | ||
| 49 | |||
| 50 | /* OTG gadget device */ | ||
| 51 | struct platform_device otg_udc_device = { | ||
| 52 | .name = "fsl-usb2-udc", | ||
| 53 | .id = -1, | ||
| 54 | .dev = { | ||
| 55 | .dma_mask = &otg_dmamask, | ||
| 56 | .coherent_dma_mask = 0xffffffff, | ||
| 57 | }, | ||
| 58 | .resource = mxc_otg_resources, | ||
| 59 | .num_resources = ARRAY_SIZE(mxc_otg_resources), | ||
| 60 | }; | ||
| 61 | |||
| 62 | static u64 usbh2_dmamask = DMA_BIT_MASK(32); | ||
| 63 | |||
| 64 | static struct resource mxc_usbh2_resources[] = { | ||
| 65 | { | ||
| 66 | .start = MX25_OTG_BASE_ADDR + 0x400, | ||
| 67 | .end = MX25_OTG_BASE_ADDR + 0x5ff, | ||
| 68 | .flags = IORESOURCE_MEM, | ||
| 69 | }, { | ||
| 70 | .start = 35, | ||
| 71 | .end = 35, | ||
| 72 | .flags = IORESOURCE_IRQ, | ||
| 73 | }, | ||
| 74 | }; | ||
| 75 | |||
| 76 | struct platform_device mxc_usbh2 = { | ||
| 77 | .name = "mxc-ehci", | ||
| 78 | .id = 1, | ||
| 79 | .dev = { | ||
| 80 | .coherent_dma_mask = 0xffffffff, | ||
| 81 | .dma_mask = &usbh2_dmamask, | ||
| 82 | }, | ||
| 83 | .resource = mxc_usbh2_resources, | ||
| 84 | .num_resources = ARRAY_SIZE(mxc_usbh2_resources), | ||
| 85 | }; | ||
| 86 | |||
| 87 | static struct resource mxc_pwm_resources0[] = { | ||
| 88 | { | ||
| 89 | .start = 0x53fe0000, | ||
| 90 | .end = 0x53fe3fff, | ||
| 91 | .flags = IORESOURCE_MEM, | ||
| 92 | }, { | ||
| 93 | .start = 26, | ||
| 94 | .end = 26, | ||
| 95 | .flags = IORESOURCE_IRQ, | ||
| 96 | } | ||
| 97 | }; | ||
| 98 | |||
| 99 | struct platform_device mxc_pwm_device0 = { | ||
| 100 | .name = "mxc_pwm", | ||
| 101 | .id = 0, | ||
| 102 | .num_resources = ARRAY_SIZE(mxc_pwm_resources0), | ||
| 103 | .resource = mxc_pwm_resources0, | ||
| 104 | }; | ||
| 105 | |||
| 106 | static struct resource mxc_pwm_resources1[] = { | ||
| 107 | { | ||
| 108 | .start = 0x53fa0000, | ||
| 109 | .end = 0x53fa3fff, | ||
| 110 | .flags = IORESOURCE_MEM, | ||
| 111 | }, { | ||
| 112 | .start = 36, | ||
| 113 | .end = 36, | ||
| 114 | .flags = IORESOURCE_IRQ, | ||
| 115 | } | ||
| 116 | }; | ||
| 117 | |||
| 118 | struct platform_device mxc_pwm_device1 = { | ||
| 119 | .name = "mxc_pwm", | ||
| 120 | .id = 1, | ||
| 121 | .num_resources = ARRAY_SIZE(mxc_pwm_resources1), | ||
| 122 | .resource = mxc_pwm_resources1, | ||
| 123 | }; | ||
| 124 | |||
| 125 | static struct resource mxc_pwm_resources2[] = { | ||
| 126 | { | ||
| 127 | .start = 0x53fa8000, | ||
| 128 | .end = 0x53fabfff, | ||
| 129 | .flags = IORESOURCE_MEM, | ||
| 130 | }, { | ||
| 131 | .start = 41, | ||
| 132 | .end = 41, | ||
| 133 | .flags = IORESOURCE_IRQ, | ||
| 134 | } | ||
| 135 | }; | ||
| 136 | |||
| 137 | struct platform_device mxc_pwm_device2 = { | ||
| 138 | .name = "mxc_pwm", | ||
| 139 | .id = 2, | ||
| 140 | .num_resources = ARRAY_SIZE(mxc_pwm_resources2), | ||
| 141 | .resource = mxc_pwm_resources2, | ||
| 142 | }; | ||
| 143 | |||
| 144 | static struct resource mxc_keypad_resources[] = { | ||
| 145 | { | ||
| 146 | .start = 0x43fa8000, | ||
| 147 | .end = 0x43fabfff, | ||
| 148 | .flags = IORESOURCE_MEM, | ||
| 149 | }, { | ||
| 150 | .start = 24, | ||
| 151 | .end = 24, | ||
| 152 | .flags = IORESOURCE_IRQ, | ||
| 153 | } | ||
| 154 | }; | ||
| 155 | |||
| 156 | struct platform_device mxc_keypad_device = { | ||
| 157 | .name = "mxc-keypad", | ||
| 158 | .id = -1, | ||
| 159 | .num_resources = ARRAY_SIZE(mxc_keypad_resources), | ||
| 160 | .resource = mxc_keypad_resources, | ||
| 161 | }; | ||
| 162 | |||
| 163 | static struct resource mxc_pwm_resources3[] = { | ||
| 164 | { | ||
| 165 | .start = 0x53fc8000, | ||
| 166 | .end = 0x53fcbfff, | ||
| 167 | .flags = IORESOURCE_MEM, | ||
| 168 | }, { | ||
| 169 | .start = 42, | ||
| 170 | .end = 42, | ||
| 171 | .flags = IORESOURCE_IRQ, | ||
| 172 | } | ||
| 173 | }; | ||
| 174 | |||
| 175 | struct platform_device mxc_pwm_device3 = { | ||
| 176 | .name = "mxc_pwm", | ||
| 177 | .id = 3, | ||
| 178 | .num_resources = ARRAY_SIZE(mxc_pwm_resources3), | ||
| 179 | .resource = mxc_pwm_resources3, | ||
| 180 | }; | ||
| 181 | |||
| 182 | static struct mxc_gpio_port imx_gpio_ports[] = { | ||
| 183 | { | ||
| 184 | .chip.label = "gpio-0", | ||
| 185 | .base = (void __iomem *)MX25_GPIO1_BASE_ADDR_VIRT, | ||
| 186 | .irq = 52, | ||
| 187 | .virtual_irq_start = MXC_GPIO_IRQ_START, | ||
| 188 | }, { | ||
| 189 | .chip.label = "gpio-1", | ||
| 190 | .base = (void __iomem *)MX25_GPIO2_BASE_ADDR_VIRT, | ||
| 191 | .irq = 51, | ||
| 192 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32, | ||
| 193 | }, { | ||
| 194 | .chip.label = "gpio-2", | ||
| 195 | .base = (void __iomem *)MX25_GPIO3_BASE_ADDR_VIRT, | ||
| 196 | .irq = 16, | ||
| 197 | .virtual_irq_start = MXC_GPIO_IRQ_START + 64, | ||
| 198 | }, { | ||
| 199 | .chip.label = "gpio-3", | ||
| 200 | .base = (void __iomem *)MX25_GPIO4_BASE_ADDR_VIRT, | ||
| 201 | .irq = 23, | ||
| 202 | .virtual_irq_start = MXC_GPIO_IRQ_START + 96, | ||
| 203 | } | ||
| 204 | }; | ||
| 205 | |||
| 206 | int __init imx25_register_gpios(void) | ||
| 207 | { | ||
| 208 | return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); | ||
| 209 | } | ||
| 210 | |||
| 211 | static struct resource mx25_rtc_resources[] = { | ||
| 212 | { | ||
| 213 | .start = MX25_DRYICE_BASE_ADDR, | ||
| 214 | .end = MX25_DRYICE_BASE_ADDR + 0x40, | ||
| 215 | .flags = IORESOURCE_MEM, | ||
| 216 | }, | ||
| 217 | { | ||
| 218 | .start = MX25_INT_DRYICE, | ||
| 219 | .flags = IORESOURCE_IRQ | ||
| 220 | }, | ||
| 221 | }; | ||
| 222 | |||
| 223 | struct platform_device mx25_rtc_device = { | ||
| 224 | .name = "imxdi_rtc", | ||
| 225 | .id = 0, | ||
| 226 | .num_resources = ARRAY_SIZE(mx25_rtc_resources), | ||
| 227 | .resource = mx25_rtc_resources, | ||
| 228 | }; | ||
| 229 | |||
| 230 | static struct resource mx25_fb_resources[] = { | ||
| 231 | { | ||
| 232 | .start = MX25_LCDC_BASE_ADDR, | ||
| 233 | .end = MX25_LCDC_BASE_ADDR + 0xfff, | ||
| 234 | .flags = IORESOURCE_MEM, | ||
| 235 | }, | ||
| 236 | { | ||
| 237 | .start = MX25_INT_LCDC, | ||
| 238 | .end = MX25_INT_LCDC, | ||
| 239 | .flags = IORESOURCE_IRQ, | ||
| 240 | }, | ||
| 241 | }; | ||
| 242 | |||
| 243 | struct platform_device mx25_fb_device = { | ||
| 244 | .name = "imx-fb", | ||
| 245 | .id = 0, | ||
| 246 | .resource = mx25_fb_resources, | ||
| 247 | .num_resources = ARRAY_SIZE(mx25_fb_resources), | ||
| 248 | .dev = { | ||
| 249 | .coherent_dma_mask = 0xFFFFFFFF, | ||
| 250 | }, | ||
| 251 | }; | ||
| 252 | |||
| 253 | static struct resource mxc_wdt_resources[] = { | ||
| 254 | { | ||
| 255 | .start = MX25_WDOG_BASE_ADDR, | ||
| 256 | .end = MX25_WDOG_BASE_ADDR + SZ_16K - 1, | ||
| 257 | .flags = IORESOURCE_MEM, | ||
| 258 | }, | ||
| 259 | }; | ||
| 260 | |||
| 261 | struct platform_device mxc_wdt = { | ||
| 262 | .name = "imx2-wdt", | ||
| 263 | .id = 0, | ||
| 264 | .num_resources = ARRAY_SIZE(mxc_wdt_resources), | ||
| 265 | .resource = mxc_wdt_resources, | ||
| 266 | }; | ||
| 267 | |||
| 268 | static struct resource mx25_kpp_resources[] = { | ||
| 269 | { | ||
| 270 | .start = MX25_KPP_BASE_ADDR, | ||
| 271 | .end = MX25_KPP_BASE_ADDR + 0xf, | ||
| 272 | .flags = IORESOURCE_MEM, | ||
| 273 | }, | ||
| 274 | { | ||
| 275 | .start = MX25_INT_KPP, | ||
| 276 | .end = MX25_INT_KPP, | ||
| 277 | .flags = IORESOURCE_IRQ, | ||
| 278 | }, | ||
| 279 | }; | ||
| 280 | |||
| 281 | struct platform_device mx25_kpp_device = { | ||
| 282 | .name = "imx-keypad", | ||
| 283 | .id = -1, | ||
| 284 | .num_resources = ARRAY_SIZE(mx25_kpp_resources), | ||
| 285 | .resource = mx25_kpp_resources, | ||
| 286 | }; | ||
| 287 | |||
| 288 | static struct resource mx25_csi_resources[] = { | ||
| 289 | { | ||
| 290 | .start = MX25_CSI_BASE_ADDR, | ||
| 291 | .end = MX25_CSI_BASE_ADDR + 0xfff, | ||
| 292 | .flags = IORESOURCE_MEM, | ||
| 293 | }, | ||
| 294 | { | ||
| 295 | .start = MX25_INT_CSI, | ||
| 296 | .flags = IORESOURCE_IRQ | ||
| 297 | }, | ||
| 298 | }; | ||
| 299 | |||
| 300 | struct platform_device mx25_csi_device = { | ||
| 301 | .name = "mx2-camera", | ||
| 302 | .id = 0, | ||
| 303 | .num_resources = ARRAY_SIZE(mx25_csi_resources), | ||
| 304 | .resource = mx25_csi_resources, | ||
| 305 | .dev = { | ||
| 306 | .coherent_dma_mask = 0xffffffff, | ||
| 307 | }, | ||
| 308 | }; | ||
diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h deleted file mode 100644 index 7b70a43c3a4b..000000000000 --- a/arch/arm/mach-mx25/devices.h +++ /dev/null | |||
| @@ -1,13 +0,0 @@ | |||
| 1 | extern struct platform_device mxc_otg; | ||
| 2 | extern struct platform_device otg_udc_device; | ||
| 3 | extern struct platform_device mxc_usbh2; | ||
| 4 | extern struct platform_device mxc_pwm_device0; | ||
| 5 | extern struct platform_device mxc_pwm_device1; | ||
| 6 | extern struct platform_device mxc_pwm_device2; | ||
| 7 | extern struct platform_device mxc_pwm_device3; | ||
| 8 | extern struct platform_device mxc_keypad_device; | ||
| 9 | extern struct platform_device mx25_rtc_device; | ||
| 10 | extern struct platform_device mx25_fb_device; | ||
| 11 | extern struct platform_device mxc_wdt; | ||
| 12 | extern struct platform_device mx25_kpp_device; | ||
| 13 | extern struct platform_device mx25_csi_device; | ||
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig index 5000ac1f93e3..0717f887cba0 100644 --- a/arch/arm/mach-mx3/Kconfig +++ b/arch/arm/mach-mx3/Kconfig | |||
| @@ -1,21 +1,35 @@ | |||
| 1 | if ARCH_MX3 | 1 | if ARCH_MX3 |
| 2 | 2 | ||
| 3 | # ARCH_MX31 and ARCH_MX35 are left for compatibility | ||
| 4 | # Some usages assume that having one of them implies not having (e.g.) ARCH_MX2. | ||
| 5 | # To easily distinguish good and reviewed from unreviewed usages new (and IMHO | ||
| 6 | # more sensible) names are used: SOC_IMX31 and SOC_IMX35 | ||
| 3 | config ARCH_MX31 | 7 | config ARCH_MX31 |
| 4 | select ARCH_HAS_RNGA | ||
| 5 | select ARCH_MXC_AUDMUX_V2 | ||
| 6 | bool | 8 | bool |
| 7 | 9 | ||
| 8 | config ARCH_MX35 | 10 | config ARCH_MX35 |
| 9 | bool | 11 | bool |
| 12 | |||
| 13 | config SOC_IMX31 | ||
| 14 | bool | ||
| 15 | select IMX_HAVE_PLATFORM_MXC_RNGA | ||
| 16 | select ARCH_MXC_AUDMUX_V2 | ||
| 17 | select ARCH_MX31 | ||
| 18 | select MXC_AVIC | ||
| 19 | |||
| 20 | config SOC_IMX35 | ||
| 21 | bool | ||
| 10 | select ARCH_MXC_IOMUX_V3 | 22 | select ARCH_MXC_IOMUX_V3 |
| 11 | select ARCH_MXC_AUDMUX_V2 | 23 | select ARCH_MXC_AUDMUX_V2 |
| 12 | select HAVE_EPIT | 24 | select HAVE_EPIT |
| 25 | select ARCH_MX35 | ||
| 26 | select MXC_AVIC | ||
| 13 | 27 | ||
| 14 | comment "MX3 platforms:" | 28 | comment "MX3 platforms:" |
| 15 | 29 | ||
| 16 | config MACH_MX31ADS | 30 | config MACH_MX31ADS |
| 17 | bool "Support MX31ADS platforms" | 31 | bool "Support MX31ADS platforms" |
| 18 | select ARCH_MX31 | 32 | select SOC_IMX31 |
| 19 | select IMX_HAVE_PLATFORM_IMX_I2C | 33 | select IMX_HAVE_PLATFORM_IMX_I2C |
| 20 | select IMX_HAVE_PLATFORM_IMX_SSI | 34 | select IMX_HAVE_PLATFORM_IMX_SSI |
| 21 | select IMX_HAVE_PLATFORM_IMX_UART | 35 | select IMX_HAVE_PLATFORM_IMX_UART |
| @@ -37,10 +51,15 @@ config MACH_MX31ADS_WM1133_EV1 | |||
| 37 | 51 | ||
| 38 | config MACH_PCM037 | 52 | config MACH_PCM037 |
| 39 | bool "Support Phytec pcm037 (i.MX31) platforms" | 53 | bool "Support Phytec pcm037 (i.MX31) platforms" |
| 40 | select ARCH_MX31 | 54 | select SOC_IMX31 |
| 55 | select IMX_HAVE_PLATFORM_FSL_USB2_UDC | ||
| 56 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
| 41 | select IMX_HAVE_PLATFORM_IMX_I2C | 57 | select IMX_HAVE_PLATFORM_IMX_I2C |
| 42 | select IMX_HAVE_PLATFORM_IMX_UART | 58 | select IMX_HAVE_PLATFORM_IMX_UART |
| 59 | select IMX_HAVE_PLATFORM_MXC_EHCI | ||
| 60 | select IMX_HAVE_PLATFORM_MXC_MMC | ||
| 43 | select IMX_HAVE_PLATFORM_MXC_NAND | 61 | select IMX_HAVE_PLATFORM_MXC_NAND |
| 62 | select IMX_HAVE_PLATFORM_MXC_W1 | ||
| 44 | select MXC_ULPI if USB_ULPI | 63 | select MXC_ULPI if USB_ULPI |
| 45 | help | 64 | help |
| 46 | Include support for Phytec pcm037 platform. This includes | 65 | Include support for Phytec pcm037 platform. This includes |
| @@ -57,9 +76,12 @@ config MACH_PCM037_EET | |||
| 57 | 76 | ||
| 58 | config MACH_MX31LITE | 77 | config MACH_MX31LITE |
| 59 | bool "Support MX31 LITEKIT (LogicPD)" | 78 | bool "Support MX31 LITEKIT (LogicPD)" |
| 60 | select ARCH_MX31 | 79 | select SOC_IMX31 |
| 61 | select MXC_ULPI if USB_ULPI | 80 | select MXC_ULPI if USB_ULPI |
| 81 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
| 62 | select IMX_HAVE_PLATFORM_IMX_UART | 82 | select IMX_HAVE_PLATFORM_IMX_UART |
| 83 | select IMX_HAVE_PLATFORM_MXC_EHCI | ||
| 84 | select IMX_HAVE_PLATFORM_MXC_MMC | ||
| 63 | select IMX_HAVE_PLATFORM_MXC_NAND | 85 | select IMX_HAVE_PLATFORM_MXC_NAND |
| 64 | select IMX_HAVE_PLATFORM_SPI_IMX | 86 | select IMX_HAVE_PLATFORM_SPI_IMX |
| 65 | help | 87 | help |
| @@ -68,11 +90,16 @@ config MACH_MX31LITE | |||
| 68 | 90 | ||
| 69 | config MACH_MX31_3DS | 91 | config MACH_MX31_3DS |
| 70 | bool "Support MX31PDK (3DS)" | 92 | bool "Support MX31PDK (3DS)" |
| 71 | select ARCH_MX31 | 93 | select SOC_IMX31 |
| 72 | select MXC_DEBUG_BOARD | 94 | select MXC_DEBUG_BOARD |
| 95 | select IMX_HAVE_PLATFORM_FSL_USB2_UDC | ||
| 96 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
| 97 | select IMX_HAVE_PLATFORM_IMX_KEYPAD | ||
| 73 | select IMX_HAVE_PLATFORM_IMX_UART | 98 | select IMX_HAVE_PLATFORM_IMX_UART |
| 99 | select IMX_HAVE_PLATFORM_MXC_EHCI | ||
| 74 | select IMX_HAVE_PLATFORM_MXC_NAND | 100 | select IMX_HAVE_PLATFORM_MXC_NAND |
| 75 | select IMX_HAVE_PLATFORM_SPI_IMX | 101 | select IMX_HAVE_PLATFORM_SPI_IMX |
| 102 | select MXC_ULPI if USB_ULPI | ||
| 76 | help | 103 | help |
| 77 | Include support for MX31PDK (3DS) platform. This includes specific | 104 | Include support for MX31PDK (3DS) platform. This includes specific |
| 78 | configurations for the board and its peripherals. | 105 | configurations for the board and its peripherals. |
| @@ -88,9 +115,12 @@ config MACH_MX31_3DS_MXC_NAND_USE_BBT | |||
| 88 | 115 | ||
| 89 | config MACH_MX31MOBOARD | 116 | config MACH_MX31MOBOARD |
| 90 | bool "Support mx31moboard platforms (EPFL Mobots group)" | 117 | bool "Support mx31moboard platforms (EPFL Mobots group)" |
| 91 | select ARCH_MX31 | 118 | select SOC_IMX31 |
| 119 | select IMX_HAVE_PLATFORM_FSL_USB2_UDC | ||
| 92 | select IMX_HAVE_PLATFORM_IMX_I2C | 120 | select IMX_HAVE_PLATFORM_IMX_I2C |
| 93 | select IMX_HAVE_PLATFORM_IMX_UART | 121 | select IMX_HAVE_PLATFORM_IMX_UART |
| 122 | select IMX_HAVE_PLATFORM_MXC_EHCI | ||
| 123 | select IMX_HAVE_PLATFORM_MXC_MMC | ||
| 94 | select IMX_HAVE_PLATFORM_SPI_IMX | 124 | select IMX_HAVE_PLATFORM_SPI_IMX |
| 95 | select MXC_ULPI if USB_ULPI | 125 | select MXC_ULPI if USB_ULPI |
| 96 | help | 126 | help |
| @@ -99,8 +129,10 @@ config MACH_MX31MOBOARD | |||
| 99 | 129 | ||
| 100 | config MACH_MX31LILLY | 130 | config MACH_MX31LILLY |
| 101 | bool "Support MX31 LILLY-1131 platforms (INCO startec)" | 131 | bool "Support MX31 LILLY-1131 platforms (INCO startec)" |
| 102 | select ARCH_MX31 | 132 | select SOC_IMX31 |
| 103 | select IMX_HAVE_PLATFORM_IMX_UART | 133 | select IMX_HAVE_PLATFORM_IMX_UART |
| 134 | select IMX_HAVE_PLATFORM_MXC_EHCI | ||
| 135 | select IMX_HAVE_PLATFORM_MXC_MMC | ||
| 104 | select IMX_HAVE_PLATFORM_SPI_IMX | 136 | select IMX_HAVE_PLATFORM_SPI_IMX |
| 105 | select MXC_ULPI if USB_ULPI | 137 | select MXC_ULPI if USB_ULPI |
| 106 | help | 138 | help |
| @@ -109,7 +141,7 @@ config MACH_MX31LILLY | |||
| 109 | 141 | ||
| 110 | config MACH_QONG | 142 | config MACH_QONG |
| 111 | bool "Support Dave/DENX QongEVB-LITE platform" | 143 | bool "Support Dave/DENX QongEVB-LITE platform" |
| 112 | select ARCH_MX31 | 144 | select SOC_IMX31 |
| 113 | select IMX_HAVE_PLATFORM_IMX_UART | 145 | select IMX_HAVE_PLATFORM_IMX_UART |
| 114 | help | 146 | help |
| 115 | Include support for Dave/DENX QongEVB-LITE platform. This includes | 147 | Include support for Dave/DENX QongEVB-LITE platform. This includes |
| @@ -117,13 +149,16 @@ config MACH_QONG | |||
| 117 | 149 | ||
| 118 | config MACH_PCM043 | 150 | config MACH_PCM043 |
| 119 | bool "Support Phytec pcm043 (i.MX35) platforms" | 151 | bool "Support Phytec pcm043 (i.MX35) platforms" |
| 120 | select ARCH_MX35 | 152 | select SOC_IMX35 |
| 153 | select IMX_HAVE_PLATFORM_FLEXCAN | ||
| 154 | select IMX_HAVE_PLATFORM_FSL_USB2_UDC | ||
| 155 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
| 121 | select IMX_HAVE_PLATFORM_IMX_I2C | 156 | select IMX_HAVE_PLATFORM_IMX_I2C |
| 122 | select IMX_HAVE_PLATFORM_IMX_SSI | 157 | select IMX_HAVE_PLATFORM_IMX_SSI |
| 123 | select IMX_HAVE_PLATFORM_IMX_UART | 158 | select IMX_HAVE_PLATFORM_IMX_UART |
| 159 | select IMX_HAVE_PLATFORM_MXC_EHCI | ||
| 124 | select IMX_HAVE_PLATFORM_MXC_NAND | 160 | select IMX_HAVE_PLATFORM_MXC_NAND |
| 125 | select IMX_HAVE_PLATFORM_FLEXCAN | 161 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX |
| 126 | select IMX_HAVE_PLATFORM_ESDHC | ||
| 127 | select MXC_ULPI if USB_ULPI | 162 | select MXC_ULPI if USB_ULPI |
| 128 | help | 163 | help |
| 129 | Include support for Phytec pcm043 platform. This includes | 164 | Include support for Phytec pcm043 platform. This includes |
| @@ -131,9 +166,11 @@ config MACH_PCM043 | |||
| 131 | 166 | ||
| 132 | config MACH_ARMADILLO5X0 | 167 | config MACH_ARMADILLO5X0 |
| 133 | bool "Support Atmark Armadillo-500 Development Base Board" | 168 | bool "Support Atmark Armadillo-500 Development Base Board" |
| 134 | select ARCH_MX31 | 169 | select SOC_IMX31 |
| 135 | select IMX_HAVE_PLATFORM_IMX_I2C | 170 | select IMX_HAVE_PLATFORM_IMX_I2C |
| 136 | select IMX_HAVE_PLATFORM_IMX_UART | 171 | select IMX_HAVE_PLATFORM_IMX_UART |
| 172 | select IMX_HAVE_PLATFORM_MXC_EHCI | ||
| 173 | select IMX_HAVE_PLATFORM_MXC_MMC | ||
| 137 | select IMX_HAVE_PLATFORM_MXC_NAND | 174 | select IMX_HAVE_PLATFORM_MXC_NAND |
| 138 | select MXC_ULPI if USB_ULPI | 175 | select MXC_ULPI if USB_ULPI |
| 139 | help | 176 | help |
| @@ -142,19 +179,21 @@ config MACH_ARMADILLO5X0 | |||
| 142 | 179 | ||
| 143 | config MACH_MX35_3DS | 180 | config MACH_MX35_3DS |
| 144 | bool "Support MX35PDK platform" | 181 | bool "Support MX35PDK platform" |
| 145 | select ARCH_MX35 | 182 | select SOC_IMX35 |
| 146 | select MXC_DEBUG_BOARD | 183 | select MXC_DEBUG_BOARD |
| 184 | select IMX_HAVE_PLATFORM_FSL_USB2_UDC | ||
| 185 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
| 147 | select IMX_HAVE_PLATFORM_IMX_UART | 186 | select IMX_HAVE_PLATFORM_IMX_UART |
| 187 | select IMX_HAVE_PLATFORM_MXC_EHCI | ||
| 148 | select IMX_HAVE_PLATFORM_MXC_NAND | 188 | select IMX_HAVE_PLATFORM_MXC_NAND |
| 149 | select IMX_HAVE_PLATFORM_ESDHC | 189 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX |
| 150 | default n | ||
| 151 | help | 190 | help |
| 152 | Include support for MX35PDK platform. This includes specific | 191 | Include support for MX35PDK platform. This includes specific |
| 153 | configurations for the board and its peripherals. | 192 | configurations for the board and its peripherals. |
| 154 | 193 | ||
| 155 | config MACH_KZM_ARM11_01 | 194 | config MACH_KZM_ARM11_01 |
| 156 | bool "Support KZM-ARM11-01(Kyoto Microcomputer)" | 195 | bool "Support KZM-ARM11-01(Kyoto Microcomputer)" |
| 157 | select ARCH_MX31 | 196 | select SOC_IMX31 |
| 158 | select IMX_HAVE_PLATFORM_IMX_UART | 197 | select IMX_HAVE_PLATFORM_IMX_UART |
| 159 | help | 198 | help |
| 160 | Include support for KZM-ARM11-01. This includes specific | 199 | Include support for KZM-ARM11-01. This includes specific |
| @@ -162,12 +201,15 @@ config MACH_KZM_ARM11_01 | |||
| 162 | 201 | ||
| 163 | config MACH_EUKREA_CPUIMX35 | 202 | config MACH_EUKREA_CPUIMX35 |
| 164 | bool "Support Eukrea CPUIMX35 Platform" | 203 | bool "Support Eukrea CPUIMX35 Platform" |
| 165 | select ARCH_MX35 | 204 | select SOC_IMX35 |
| 166 | select IMX_HAVE_PLATFORM_IMX_UART | 205 | select IMX_HAVE_PLATFORM_FLEXCAN |
| 206 | select IMX_HAVE_PLATFORM_FSL_USB2_UDC | ||
| 207 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
| 167 | select IMX_HAVE_PLATFORM_IMX_I2C | 208 | select IMX_HAVE_PLATFORM_IMX_I2C |
| 209 | select IMX_HAVE_PLATFORM_IMX_UART | ||
| 210 | select IMX_HAVE_PLATFORM_MXC_EHCI | ||
| 168 | select IMX_HAVE_PLATFORM_MXC_NAND | 211 | select IMX_HAVE_PLATFORM_MXC_NAND |
| 169 | select IMX_HAVE_PLATFORM_FLEXCAN | 212 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX |
| 170 | select IMX_HAVE_PLATFORM_ESDHC | ||
| 171 | select MXC_ULPI if USB_ULPI | 213 | select MXC_ULPI if USB_ULPI |
| 172 | help | 214 | help |
| 173 | Include support for Eukrea CPUIMX35 platform. This includes | 215 | Include support for Eukrea CPUIMX35 platform. This includes |
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile index 8a182d0a3fcf..8db13294ad27 100644 --- a/arch/arm/mach-mx3/Makefile +++ b/arch/arm/mach-mx3/Makefile | |||
| @@ -5,17 +5,14 @@ | |||
| 5 | # Object file lists. | 5 | # Object file lists. |
| 6 | 6 | ||
| 7 | obj-y := mm.o devices.o cpu.o | 7 | obj-y := mm.o devices.o cpu.o |
| 8 | CFLAGS_mm.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS | 8 | obj-$(CONFIG_SOC_IMX31) += clock-imx31.o iomux-imx31.o |
| 9 | CFLAGS_devices.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS | 9 | obj-$(CONFIG_SOC_IMX35) += clock-imx35.o |
| 10 | obj-$(CONFIG_ARCH_MX31) += clock-imx31.o iomux-imx31.o | ||
| 11 | obj-$(CONFIG_ARCH_MX35) += clock-imx35.o | ||
| 12 | obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o | 10 | obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o |
| 13 | obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o | 11 | obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o |
| 14 | obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o | 12 | obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o |
| 15 | obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o | 13 | obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o |
| 16 | obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o | 14 | obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o |
| 17 | obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o | 15 | obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o |
| 18 | CFLAGS_mach-mx31_3ds.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS | ||
| 19 | obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \ | 16 | obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \ |
| 20 | mx31moboard-marxbot.o mx31moboard-smartbot.o | 17 | mx31moboard-marxbot.o mx31moboard-smartbot.o |
| 21 | obj-$(CONFIG_MACH_QONG) += mach-qong.o | 18 | obj-$(CONFIG_MACH_QONG) += mach-qong.o |
diff --git a/arch/arm/mach-mx3/clock-imx31.c b/arch/arm/mach-mx3/clock-imx31.c index 109e98f323e0..d423cac8cab7 100644 --- a/arch/arm/mach-mx3/clock-imx31.c +++ b/arch/arm/mach-mx3/clock-imx31.c | |||
| @@ -23,8 +23,8 @@ | |||
| 23 | #include <linux/clk.h> | 23 | #include <linux/clk.h> |
| 24 | #include <linux/err.h> | 24 | #include <linux/err.h> |
| 25 | #include <linux/io.h> | 25 | #include <linux/io.h> |
| 26 | #include <linux/clkdev.h> | ||
| 26 | 27 | ||
| 27 | #include <asm/clkdev.h> | ||
| 28 | #include <asm/div64.h> | 28 | #include <asm/div64.h> |
| 29 | 29 | ||
| 30 | #include <mach/clock.h> | 30 | #include <mach/clock.h> |
| @@ -530,7 +530,7 @@ static struct clk_lookup lookups[] = { | |||
| 530 | _REGISTER_CLOCK("imx31-cspi.2", NULL, cspi3_clk) | 530 | _REGISTER_CLOCK("imx31-cspi.2", NULL, cspi3_clk) |
| 531 | _REGISTER_CLOCK(NULL, "gpt", gpt_clk) | 531 | _REGISTER_CLOCK(NULL, "gpt", gpt_clk) |
| 532 | _REGISTER_CLOCK(NULL, "pwm", pwm_clk) | 532 | _REGISTER_CLOCK(NULL, "pwm", pwm_clk) |
| 533 | _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk) | 533 | _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk) |
| 534 | _REGISTER_CLOCK(NULL, "rtc", rtc_clk) | 534 | _REGISTER_CLOCK(NULL, "rtc", rtc_clk) |
| 535 | _REGISTER_CLOCK(NULL, "epit", epit1_clk) | 535 | _REGISTER_CLOCK(NULL, "epit", epit1_clk) |
| 536 | _REGISTER_CLOCK(NULL, "epit", epit2_clk) | 536 | _REGISTER_CLOCK(NULL, "epit", epit2_clk) |
| @@ -615,7 +615,7 @@ int __init mx31_clocks_init(unsigned long fref) | |||
| 615 | 615 | ||
| 616 | mx31_read_cpu_rev(); | 616 | mx31_read_cpu_rev(); |
| 617 | 617 | ||
| 618 | if (mx31_revision() >= MX31_CHIP_REV_2_0) { | 618 | if (mx31_revision() >= IMX_CHIP_REVISION_2_0) { |
| 619 | reg = __raw_readl(MXC_CCM_PMCR1); | 619 | reg = __raw_readl(MXC_CCM_PMCR1); |
| 620 | /* No PLL restart on DVFS switch; enable auto EMI handshake */ | 620 | /* No PLL restart on DVFS switch; enable auto EMI handshake */ |
| 621 | reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN; | 621 | reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN; |
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c index 61e4a318980a..448a038cd1ec 100644 --- a/arch/arm/mach-mx3/clock-imx35.c +++ b/arch/arm/mach-mx3/clock-imx35.c | |||
| @@ -21,8 +21,7 @@ | |||
| 21 | #include <linux/list.h> | 21 | #include <linux/list.h> |
| 22 | #include <linux/clk.h> | 22 | #include <linux/clk.h> |
| 23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
| 24 | 24 | #include <linux/clkdev.h> | |
| 25 | #include <asm/clkdev.h> | ||
| 26 | 25 | ||
| 27 | #include <mach/clock.h> | 26 | #include <mach/clock.h> |
| 28 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
| @@ -495,7 +494,7 @@ static struct clk_lookup lookups[] = { | |||
| 495 | _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk) | 494 | _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk) |
| 496 | _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk) | 495 | _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk) |
| 497 | _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usbahb_clk) | 496 | _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usbahb_clk) |
| 498 | _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk) | 497 | _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk) |
| 499 | _REGISTER_CLOCK(NULL, "max", max_clk) | 498 | _REGISTER_CLOCK(NULL, "max", max_clk) |
| 500 | _REGISTER_CLOCK(NULL, "audmux", audmux_clk) | 499 | _REGISTER_CLOCK(NULL, "audmux", audmux_clk) |
| 501 | _REGISTER_CLOCK(NULL, "csi", csi_clk) | 500 | _REGISTER_CLOCK(NULL, "csi", csi_clk) |
diff --git a/arch/arm/mach-mx3/cpu.c b/arch/arm/mach-mx3/cpu.c index d00a75457812..d1d339576fdf 100644 --- a/arch/arm/mach-mx3/cpu.c +++ b/arch/arm/mach-mx3/cpu.c | |||
| @@ -25,15 +25,15 @@ struct mx3_cpu_type { | |||
| 25 | }; | 25 | }; |
| 26 | 26 | ||
| 27 | static struct mx3_cpu_type mx31_cpu_type[] __initdata = { | 27 | static struct mx3_cpu_type mx31_cpu_type[] __initdata = { |
| 28 | { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = MX3x_CHIP_REV_1_0 }, | 28 | { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = IMX_CHIP_REVISION_1_0 }, |
| 29 | { .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = MX3x_CHIP_REV_1_1 }, | 29 | { .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 }, |
| 30 | { .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = MX3x_CHIP_REV_1_1 }, | 30 | { .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 }, |
| 31 | { .srev = 0x12, .name = "i.MX31", .v = "1.15", .rev = MX3x_CHIP_REV_1_1 }, | 31 | { .srev = 0x12, .name = "i.MX31", .v = "1.15", .rev = IMX_CHIP_REVISION_1_1 }, |
| 32 | { .srev = 0x13, .name = "i.MX31L", .v = "1.15", .rev = MX3x_CHIP_REV_1_1 }, | 32 | { .srev = 0x13, .name = "i.MX31L", .v = "1.15", .rev = IMX_CHIP_REVISION_1_1 }, |
| 33 | { .srev = 0x14, .name = "i.MX31", .v = "1.2", .rev = MX3x_CHIP_REV_1_2 }, | 33 | { .srev = 0x14, .name = "i.MX31", .v = "1.2", .rev = IMX_CHIP_REVISION_1_2 }, |
| 34 | { .srev = 0x15, .name = "i.MX31L", .v = "1.2", .rev = MX3x_CHIP_REV_1_2 }, | 34 | { .srev = 0x15, .name = "i.MX31L", .v = "1.2", .rev = IMX_CHIP_REVISION_1_2 }, |
| 35 | { .srev = 0x28, .name = "i.MX31", .v = "2.0", .rev = MX3x_CHIP_REV_2_0 }, | 35 | { .srev = 0x28, .name = "i.MX31", .v = "2.0", .rev = IMX_CHIP_REVISION_2_0 }, |
| 36 | { .srev = 0x29, .name = "i.MX31L", .v = "2.0", .rev = MX3x_CHIP_REV_2_0 }, | 36 | { .srev = 0x29, .name = "i.MX31L", .v = "2.0", .rev = IMX_CHIP_REVISION_2_0 }, |
| 37 | }; | 37 | }; |
| 38 | 38 | ||
| 39 | void __init mx31_read_cpu_rev(void) | 39 | void __init mx31_read_cpu_rev(void) |
| @@ -53,6 +53,8 @@ void __init mx31_read_cpu_rev(void) | |||
| 53 | return; | 53 | return; |
| 54 | } | 54 | } |
| 55 | 55 | ||
| 56 | mx31_cpu_rev = IMX_CHIP_REVISION_UNKNOWN; | ||
| 57 | |||
| 56 | printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev); | 58 | printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev); |
| 57 | } | 59 | } |
| 58 | 60 | ||
| @@ -62,22 +64,25 @@ EXPORT_SYMBOL(mx35_cpu_rev); | |||
| 62 | void __init mx35_read_cpu_rev(void) | 64 | void __init mx35_read_cpu_rev(void) |
| 63 | { | 65 | { |
| 64 | u32 rev; | 66 | u32 rev; |
| 65 | char *srev = "unknown"; | 67 | char *srev; |
| 66 | 68 | ||
| 67 | rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV)); | 69 | rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV)); |
| 68 | switch (rev) { | 70 | switch (rev) { |
| 69 | case 0x00: | 71 | case 0x00: |
| 70 | mx35_cpu_rev = MX3x_CHIP_REV_1_0; | 72 | mx35_cpu_rev = IMX_CHIP_REVISION_1_0; |
| 71 | srev = "1.0"; | 73 | srev = "1.0"; |
| 72 | break; | 74 | break; |
| 73 | case 0x10: | 75 | case 0x10: |
| 74 | mx35_cpu_rev = MX3x_CHIP_REV_2_0; | 76 | mx35_cpu_rev = IMX_CHIP_REVISION_2_0; |
| 75 | srev = "2.0"; | 77 | srev = "2.0"; |
| 76 | break; | 78 | break; |
| 77 | case 0x11: | 79 | case 0x11: |
| 78 | mx35_cpu_rev = MX3x_CHIP_REV_2_1; | 80 | mx35_cpu_rev = IMX_CHIP_REVISION_2_1; |
| 79 | srev = "2.1"; | 81 | srev = "2.1"; |
| 80 | break; | 82 | break; |
| 83 | default: | ||
| 84 | mx35_cpu_rev = IMX_CHIP_REVISION_UNKNOWN; | ||
| 85 | srev = "unknown"; | ||
| 81 | } | 86 | } |
| 82 | 87 | ||
| 83 | printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev); | 88 | printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev); |
diff --git a/arch/arm/mach-mx3/devices-imx31.h b/arch/arm/mach-mx3/devices-imx31.h index de9598590eba..40f4e848a671 100644 --- a/arch/arm/mach-mx3/devices-imx31.h +++ b/arch/arm/mach-mx3/devices-imx31.h | |||
| @@ -9,6 +9,14 @@ | |||
| 9 | #include <mach/mx31.h> | 9 | #include <mach/mx31.h> |
| 10 | #include <mach/devices-common.h> | 10 | #include <mach/devices-common.h> |
| 11 | 11 | ||
| 12 | extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst; | ||
| 13 | #define imx31_add_fsl_usb2_udc(pdata) \ | ||
| 14 | imx_add_fsl_usb2_udc(&imx31_fsl_usb2_udc_data, pdata) | ||
| 15 | |||
| 16 | extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data __initconst; | ||
| 17 | #define imx31_add_imx2_wdt(pdata) \ | ||
| 18 | imx_add_imx2_wdt(&imx31_imx2_wdt_data) | ||
| 19 | |||
| 12 | extern const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst; | 20 | extern const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst; |
| 13 | #define imx31_add_imx_i2c(id, pdata) \ | 21 | #define imx31_add_imx_i2c(id, pdata) \ |
| 14 | imx_add_imx_i2c(&imx31_imx_i2c_data[id], pdata) | 22 | imx_add_imx_i2c(&imx31_imx_i2c_data[id], pdata) |
| @@ -16,6 +24,10 @@ extern const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst; | |||
| 16 | #define imx31_add_imx_i2c1(pdata) imx31_add_imx_i2c(1, pdata) | 24 | #define imx31_add_imx_i2c1(pdata) imx31_add_imx_i2c(1, pdata) |
| 17 | #define imx31_add_imx_i2c2(pdata) imx31_add_imx_i2c(2, pdata) | 25 | #define imx31_add_imx_i2c2(pdata) imx31_add_imx_i2c(2, pdata) |
| 18 | 26 | ||
| 27 | extern const struct imx_imx_keypad_data imx31_imx_keypad_data __initconst; | ||
| 28 | #define imx31_add_imx_keypad(pdata) \ | ||
| 29 | imx_add_imx_keypad(&imx31_imx_keypad_data, pdata) | ||
| 30 | |||
| 19 | extern const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst; | 31 | extern const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst; |
| 20 | #define imx31_add_imx_ssi(id, pdata) \ | 32 | #define imx31_add_imx_ssi(id, pdata) \ |
| 21 | imx_add_imx_ssi(&imx31_imx_ssi_data[id], pdata) | 33 | imx_add_imx_ssi(&imx31_imx_ssi_data[id], pdata) |
| @@ -29,10 +41,25 @@ extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst; | |||
| 29 | #define imx31_add_imx_uart3(pdata) imx31_add_imx_uart(3, pdata) | 41 | #define imx31_add_imx_uart3(pdata) imx31_add_imx_uart(3, pdata) |
| 30 | #define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata) | 42 | #define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata) |
| 31 | 43 | ||
| 44 | extern const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data __initconst; | ||
| 45 | #define imx31_add_mxc_ehci_otg(pdata) \ | ||
| 46 | imx_add_mxc_ehci(&imx31_mxc_ehci_otg_data, pdata) | ||
| 47 | extern const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[] __initconst; | ||
| 48 | #define imx31_add_mxc_ehci_hs(id, pdata) \ | ||
| 49 | imx_add_mxc_ehci(&imx31_mxc_ehci_hs_data[id - 1], pdata) | ||
| 50 | |||
| 51 | extern const struct imx_mxc_mmc_data imx31_mxc_mmc_data[] __initconst; | ||
| 52 | #define imx31_add_mxc_mmc(id, pdata) \ | ||
| 53 | imx_add_mxc_mmc(&imx31_mxc_mmc_data[id], pdata) | ||
| 54 | |||
| 32 | extern const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst; | 55 | extern const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst; |
| 33 | #define imx31_add_mxc_nand(pdata) \ | 56 | #define imx31_add_mxc_nand(pdata) \ |
| 34 | imx_add_mxc_nand(&imx31_mxc_nand_data, pdata) | 57 | imx_add_mxc_nand(&imx31_mxc_nand_data, pdata) |
| 35 | 58 | ||
| 59 | extern const struct imx_mxc_w1_data imx31_mxc_w1_data __initconst; | ||
| 60 | #define imx31_add_mxc_w1(pdata) \ | ||
| 61 | imx_add_mxc_w1(&imx31_mxc_w1_data) | ||
| 62 | |||
| 36 | extern const struct imx_spi_imx_data imx31_cspi_data[] __initconst; | 63 | extern const struct imx_spi_imx_data imx31_cspi_data[] __initconst; |
| 37 | #define imx31_add_cspi(id, pdata) \ | 64 | #define imx31_add_cspi(id, pdata) \ |
| 38 | imx_add_spi_imx(&imx31_cspi_data[id], pdata) | 65 | imx_add_spi_imx(&imx31_cspi_data[id], pdata) |
diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h index 5eb917b638d0..677b18aa7ae6 100644 --- a/arch/arm/mach-mx3/devices-imx35.h +++ b/arch/arm/mach-mx3/devices-imx35.h | |||
| @@ -13,10 +13,19 @@ extern const struct imx_fec_data imx35_fec_data __initconst; | |||
| 13 | #define imx35_add_fec(pdata) \ | 13 | #define imx35_add_fec(pdata) \ |
| 14 | imx_add_fec(&imx35_fec_data, pdata) | 14 | imx_add_fec(&imx35_fec_data, pdata) |
| 15 | 15 | ||
| 16 | #define imx35_add_flexcan0(pdata) \ | 16 | extern const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst; |
| 17 | imx_add_flexcan(0, MX35_CAN1_BASE_ADDR, SZ_16K, MX35_INT_CAN1, pdata) | 17 | #define imx35_add_fsl_usb2_udc(pdata) \ |
| 18 | #define imx35_add_flexcan1(pdata) \ | 18 | imx_add_fsl_usb2_udc(&imx35_fsl_usb2_udc_data, pdata) |
| 19 | imx_add_flexcan(1, MX35_CAN2_BASE_ADDR, SZ_16K, MX35_INT_CAN2, pdata) | 19 | |
| 20 | extern const struct imx_flexcan_data imx35_flexcan_data[] __initconst; | ||
| 21 | #define imx35_add_flexcan(id, pdata) \ | ||
| 22 | imx_add_flexcan(&imx35_flexcan_data[id], pdata) | ||
| 23 | #define imx35_add_flexcan0(pdata) imx35_add_flexcan(0, pdata) | ||
| 24 | #define imx35_add_flexcan1(pdata) imx35_add_flexcan(1, pdata) | ||
| 25 | |||
| 26 | extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst; | ||
| 27 | #define imx35_add_imx2_wdt(pdata) \ | ||
| 28 | imx_add_imx2_wdt(&imx35_imx2_wdt_data) | ||
| 20 | 29 | ||
| 21 | extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst; | 30 | extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst; |
| 22 | #define imx35_add_imx_i2c(id, pdata) \ | 31 | #define imx35_add_imx_i2c(id, pdata) \ |
| @@ -25,6 +34,10 @@ extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst; | |||
| 25 | #define imx35_add_imx_i2c1(pdata) imx35_add_imx_i2c(1, pdata) | 34 | #define imx35_add_imx_i2c1(pdata) imx35_add_imx_i2c(1, pdata) |
| 26 | #define imx35_add_imx_i2c2(pdata) imx35_add_imx_i2c(2, pdata) | 35 | #define imx35_add_imx_i2c2(pdata) imx35_add_imx_i2c(2, pdata) |
| 27 | 36 | ||
| 37 | extern const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst; | ||
| 38 | #define imx31_add_imx_keypad(pdata) \ | ||
| 39 | imx_add_imx_keypad(&imx35_imx_keypad_data, pdata) | ||
| 40 | |||
| 28 | extern const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst; | 41 | extern const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst; |
| 29 | #define imx35_add_imx_ssi(id, pdata) \ | 42 | #define imx35_add_imx_ssi(id, pdata) \ |
| 30 | imx_add_imx_ssi(&imx35_imx_ssi_data[id], pdata) | 43 | imx_add_imx_ssi(&imx35_imx_ssi_data[id], pdata) |
| @@ -36,16 +49,28 @@ extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst; | |||
| 36 | #define imx35_add_imx_uart1(pdata) imx35_add_imx_uart(1, pdata) | 49 | #define imx35_add_imx_uart1(pdata) imx35_add_imx_uart(1, pdata) |
| 37 | #define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2, pdata) | 50 | #define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2, pdata) |
| 38 | 51 | ||
| 52 | extern const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data __initconst; | ||
| 53 | #define imx35_add_mxc_ehci_otg(pdata) \ | ||
| 54 | imx_add_mxc_ehci(&imx35_mxc_ehci_otg_data, pdata) | ||
| 55 | extern const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst; | ||
| 56 | #define imx35_add_mxc_ehci_hs(pdata) \ | ||
| 57 | imx_add_mxc_ehci(&imx35_mxc_ehci_hs_data, pdata) | ||
| 58 | |||
| 39 | extern const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst; | 59 | extern const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst; |
| 40 | #define imx35_add_mxc_nand(pdata) \ | 60 | #define imx35_add_mxc_nand(pdata) \ |
| 41 | imx_add_mxc_nand(&imx35_mxc_nand_data, pdata) | 61 | imx_add_mxc_nand(&imx35_mxc_nand_data, pdata) |
| 42 | 62 | ||
| 63 | extern const struct imx_mxc_w1_data imx35_mxc_w1_data __initconst; | ||
| 64 | #define imx35_add_mxc_w1(pdata) \ | ||
| 65 | imx_add_mxc_w1(&imx35_mxc_w1_data) | ||
| 66 | |||
| 67 | extern const struct imx_sdhci_esdhc_imx_data | ||
| 68 | imx35_sdhci_esdhc_imx_data[] __initconst; | ||
| 69 | #define imx35_add_sdhci_esdhc_imx(id, pdata) \ | ||
| 70 | imx_add_sdhci_esdhc_imx(&imx35_sdhci_esdhc_imx_data[id], pdata) | ||
| 71 | |||
| 43 | extern const struct imx_spi_imx_data imx35_cspi_data[] __initconst; | 72 | extern const struct imx_spi_imx_data imx35_cspi_data[] __initconst; |
| 44 | #define imx35_add_cspi(id, pdata) \ | 73 | #define imx35_add_cspi(id, pdata) \ |
| 45 | imx_add_spi_imx(&imx35_cspi_data[id], pdata) | 74 | imx_add_spi_imx(&imx35_cspi_data[id], pdata) |
| 46 | #define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata) | 75 | #define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata) |
| 47 | #define imx35_add_spi_imx1(pdata) imx35_add_cspi(1, pdata) | 76 | #define imx35_add_spi_imx1(pdata) imx35_add_cspi(1, pdata) |
| 48 | |||
| 49 | extern const struct imx_esdhc_imx_data imx35_esdhc_data[] __initconst; | ||
| 50 | #define imx35_add_esdhc(id, pdata) \ | ||
| 51 | imx_add_esdhc(&imx35_esdhc_data[id], pdata) | ||
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c index d4da9496089a..b6672db788fb 100644 --- a/arch/arm/mach-mx3/devices.c +++ b/arch/arm/mach-mx3/devices.c | |||
| @@ -29,120 +29,25 @@ | |||
| 29 | 29 | ||
| 30 | #include "devices.h" | 30 | #include "devices.h" |
| 31 | 31 | ||
| 32 | /* GPIO port description */ | ||
| 33 | static struct mxc_gpio_port imx_gpio_ports[] = { | ||
| 34 | { | ||
| 35 | .chip.label = "gpio-0", | ||
| 36 | .base = IO_ADDRESS(GPIO1_BASE_ADDR), | ||
| 37 | .irq = MXC_INT_GPIO1, | ||
| 38 | .virtual_irq_start = MXC_GPIO_IRQ_START, | ||
| 39 | }, { | ||
| 40 | .chip.label = "gpio-1", | ||
| 41 | .base = IO_ADDRESS(GPIO2_BASE_ADDR), | ||
| 42 | .irq = MXC_INT_GPIO2, | ||
| 43 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32, | ||
| 44 | }, { | ||
| 45 | .chip.label = "gpio-2", | ||
| 46 | .base = IO_ADDRESS(GPIO3_BASE_ADDR), | ||
| 47 | .irq = MXC_INT_GPIO3, | ||
| 48 | .virtual_irq_start = MXC_GPIO_IRQ_START + 64, | ||
| 49 | } | ||
| 50 | }; | ||
| 51 | |||
| 52 | int __init imx3x_register_gpios(void) | ||
| 53 | { | ||
| 54 | return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); | ||
| 55 | } | ||
| 56 | |||
| 57 | static struct resource mxc_w1_master_resources[] = { | ||
| 58 | { | ||
| 59 | .start = OWIRE_BASE_ADDR, | ||
| 60 | .end = OWIRE_BASE_ADDR + SZ_4K - 1, | ||
| 61 | .flags = IORESOURCE_MEM, | ||
| 62 | }, | ||
| 63 | }; | ||
| 64 | |||
| 65 | struct platform_device mxc_w1_master_device = { | ||
| 66 | .name = "mxc_w1", | ||
| 67 | .id = 0, | ||
| 68 | .num_resources = ARRAY_SIZE(mxc_w1_master_resources), | ||
| 69 | .resource = mxc_w1_master_resources, | ||
| 70 | }; | ||
| 71 | |||
| 72 | #ifdef CONFIG_ARCH_MX31 | ||
| 73 | static struct resource mxcsdhc0_resources[] = { | ||
| 74 | { | ||
| 75 | .start = MX31_MMC_SDHC1_BASE_ADDR, | ||
| 76 | .end = MX31_MMC_SDHC1_BASE_ADDR + SZ_16K - 1, | ||
| 77 | .flags = IORESOURCE_MEM, | ||
| 78 | }, { | ||
| 79 | .start = MX31_INT_MMC_SDHC1, | ||
| 80 | .end = MX31_INT_MMC_SDHC1, | ||
| 81 | .flags = IORESOURCE_IRQ, | ||
| 82 | }, | ||
| 83 | }; | ||
| 84 | |||
| 85 | static struct resource mxcsdhc1_resources[] = { | ||
| 86 | { | ||
| 87 | .start = MX31_MMC_SDHC2_BASE_ADDR, | ||
| 88 | .end = MX31_MMC_SDHC2_BASE_ADDR + SZ_16K - 1, | ||
| 89 | .flags = IORESOURCE_MEM, | ||
| 90 | }, { | ||
| 91 | .start = MX31_INT_MMC_SDHC2, | ||
| 92 | .end = MX31_INT_MMC_SDHC2, | ||
| 93 | .flags = IORESOURCE_IRQ, | ||
| 94 | }, | ||
| 95 | }; | ||
| 96 | |||
| 97 | struct platform_device mxcsdhc_device0 = { | ||
| 98 | .name = "mxc-mmc", | ||
| 99 | .id = 0, | ||
| 100 | .num_resources = ARRAY_SIZE(mxcsdhc0_resources), | ||
| 101 | .resource = mxcsdhc0_resources, | ||
| 102 | }; | ||
| 103 | |||
| 104 | struct platform_device mxcsdhc_device1 = { | ||
| 105 | .name = "mxc-mmc", | ||
| 106 | .id = 1, | ||
| 107 | .num_resources = ARRAY_SIZE(mxcsdhc1_resources), | ||
| 108 | .resource = mxcsdhc1_resources, | ||
| 109 | }; | ||
| 110 | |||
| 111 | static struct resource rnga_resources[] = { | ||
| 112 | { | ||
| 113 | .start = RNGA_BASE_ADDR, | ||
| 114 | .end = RNGA_BASE_ADDR + 0x28, | ||
| 115 | .flags = IORESOURCE_MEM, | ||
| 116 | }, | ||
| 117 | }; | ||
| 118 | |||
| 119 | struct platform_device mxc_rnga_device = { | ||
| 120 | .name = "mxc_rnga", | ||
| 121 | .id = -1, | ||
| 122 | .num_resources = 1, | ||
| 123 | .resource = rnga_resources, | ||
| 124 | }; | ||
| 125 | #endif /* CONFIG_ARCH_MX31 */ | ||
| 126 | |||
| 127 | /* i.MX31 Image Processing Unit */ | 32 | /* i.MX31 Image Processing Unit */ |
| 128 | 33 | ||
| 129 | /* The resource order is important! */ | 34 | /* The resource order is important! */ |
| 130 | static struct resource mx3_ipu_rsrc[] = { | 35 | static struct resource mx3_ipu_rsrc[] = { |
| 131 | { | 36 | { |
| 132 | .start = IPU_CTRL_BASE_ADDR, | 37 | .start = MX3x_IPU_CTRL_BASE_ADDR, |
| 133 | .end = IPU_CTRL_BASE_ADDR + 0x5F, | 38 | .end = MX3x_IPU_CTRL_BASE_ADDR + 0x5F, |
| 134 | .flags = IORESOURCE_MEM, | 39 | .flags = IORESOURCE_MEM, |
| 135 | }, { | 40 | }, { |
| 136 | .start = IPU_CTRL_BASE_ADDR + 0x88, | 41 | .start = MX3x_IPU_CTRL_BASE_ADDR + 0x88, |
| 137 | .end = IPU_CTRL_BASE_ADDR + 0xB3, | 42 | .end = MX3x_IPU_CTRL_BASE_ADDR + 0xB3, |
| 138 | .flags = IORESOURCE_MEM, | 43 | .flags = IORESOURCE_MEM, |
| 139 | }, { | 44 | }, { |
| 140 | .start = MXC_INT_IPU_SYN, | 45 | .start = MX3x_INT_IPU_SYN, |
| 141 | .end = MXC_INT_IPU_SYN, | 46 | .end = MX3x_INT_IPU_SYN, |
| 142 | .flags = IORESOURCE_IRQ, | 47 | .flags = IORESOURCE_IRQ, |
| 143 | }, { | 48 | }, { |
| 144 | .start = MXC_INT_IPU_ERR, | 49 | .start = MX3x_INT_IPU_ERR, |
| 145 | .end = MXC_INT_IPU_ERR, | 50 | .end = MX3x_INT_IPU_ERR, |
| 146 | .flags = IORESOURCE_IRQ, | 51 | .flags = IORESOURCE_IRQ, |
| 147 | }, | 52 | }, |
| 148 | }; | 53 | }; |
| @@ -156,8 +61,8 @@ struct platform_device mx3_ipu = { | |||
| 156 | 61 | ||
| 157 | static struct resource fb_resources[] = { | 62 | static struct resource fb_resources[] = { |
| 158 | { | 63 | { |
| 159 | .start = IPU_CTRL_BASE_ADDR + 0xB4, | 64 | .start = MX3x_IPU_CTRL_BASE_ADDR + 0xB4, |
| 160 | .end = IPU_CTRL_BASE_ADDR + 0x1BF, | 65 | .end = MX3x_IPU_CTRL_BASE_ADDR + 0x1BF, |
| 161 | .flags = IORESOURCE_MEM, | 66 | .flags = IORESOURCE_MEM, |
| 162 | }, | 67 | }, |
| 163 | }; | 68 | }; |
| @@ -174,8 +79,8 @@ struct platform_device mx3_fb = { | |||
| 174 | 79 | ||
| 175 | static struct resource camera_resources[] = { | 80 | static struct resource camera_resources[] = { |
| 176 | { | 81 | { |
| 177 | .start = IPU_CTRL_BASE_ADDR + 0x60, | 82 | .start = MX3x_IPU_CTRL_BASE_ADDR + 0x60, |
| 178 | .end = IPU_CTRL_BASE_ADDR + 0x87, | 83 | .end = MX3x_IPU_CTRL_BASE_ADDR + 0x87, |
| 179 | .flags = IORESOURCE_MEM, | 84 | .flags = IORESOURCE_MEM, |
| 180 | }, | 85 | }, |
| 181 | }; | 86 | }; |
| @@ -190,110 +95,6 @@ struct platform_device mx3_camera = { | |||
| 190 | }, | 95 | }, |
| 191 | }; | 96 | }; |
| 192 | 97 | ||
| 193 | static struct resource otg_resources[] = { | ||
| 194 | { | ||
| 195 | .start = MX31_OTG_BASE_ADDR, | ||
| 196 | .end = MX31_OTG_BASE_ADDR + 0x1ff, | ||
| 197 | .flags = IORESOURCE_MEM, | ||
| 198 | }, { | ||
| 199 | .start = MXC_INT_USB3, | ||
| 200 | .end = MXC_INT_USB3, | ||
| 201 | .flags = IORESOURCE_IRQ, | ||
| 202 | }, | ||
| 203 | }; | ||
| 204 | |||
| 205 | static u64 otg_dmamask = DMA_BIT_MASK(32); | ||
| 206 | |||
| 207 | /* OTG gadget device */ | ||
| 208 | struct platform_device mxc_otg_udc_device = { | ||
| 209 | .name = "fsl-usb2-udc", | ||
| 210 | .id = -1, | ||
| 211 | .dev = { | ||
| 212 | .dma_mask = &otg_dmamask, | ||
| 213 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 214 | }, | ||
| 215 | .resource = otg_resources, | ||
| 216 | .num_resources = ARRAY_SIZE(otg_resources), | ||
| 217 | }; | ||
| 218 | |||
| 219 | /* OTG host */ | ||
| 220 | struct platform_device mxc_otg_host = { | ||
| 221 | .name = "mxc-ehci", | ||
| 222 | .id = 0, | ||
| 223 | .dev = { | ||
| 224 | .coherent_dma_mask = 0xffffffff, | ||
| 225 | .dma_mask = &otg_dmamask, | ||
| 226 | }, | ||
| 227 | .resource = otg_resources, | ||
| 228 | .num_resources = ARRAY_SIZE(otg_resources), | ||
| 229 | }; | ||
| 230 | |||
| 231 | /* USB host 1 */ | ||
| 232 | |||
| 233 | static u64 usbh1_dmamask = ~(u32)0; | ||
| 234 | |||
| 235 | static struct resource mxc_usbh1_resources[] = { | ||
| 236 | { | ||
| 237 | .start = MX31_OTG_BASE_ADDR + 0x200, | ||
| 238 | .end = MX31_OTG_BASE_ADDR + 0x3ff, | ||
| 239 | .flags = IORESOURCE_MEM, | ||
| 240 | }, { | ||
| 241 | .start = MXC_INT_USB1, | ||
| 242 | .end = MXC_INT_USB1, | ||
| 243 | .flags = IORESOURCE_IRQ, | ||
| 244 | }, | ||
| 245 | }; | ||
| 246 | |||
| 247 | struct platform_device mxc_usbh1 = { | ||
| 248 | .name = "mxc-ehci", | ||
| 249 | .id = 1, | ||
| 250 | .dev = { | ||
| 251 | .coherent_dma_mask = 0xffffffff, | ||
| 252 | .dma_mask = &usbh1_dmamask, | ||
| 253 | }, | ||
| 254 | .resource = mxc_usbh1_resources, | ||
| 255 | .num_resources = ARRAY_SIZE(mxc_usbh1_resources), | ||
| 256 | }; | ||
| 257 | |||
| 258 | /* USB host 2 */ | ||
| 259 | static u64 usbh2_dmamask = ~(u32)0; | ||
| 260 | |||
| 261 | static struct resource mxc_usbh2_resources[] = { | ||
| 262 | { | ||
| 263 | .start = MX31_OTG_BASE_ADDR + 0x400, | ||
| 264 | .end = MX31_OTG_BASE_ADDR + 0x5ff, | ||
| 265 | .flags = IORESOURCE_MEM, | ||
| 266 | }, { | ||
| 267 | .start = MXC_INT_USB2, | ||
| 268 | .end = MXC_INT_USB2, | ||
| 269 | .flags = IORESOURCE_IRQ, | ||
| 270 | }, | ||
| 271 | }; | ||
| 272 | |||
| 273 | struct platform_device mxc_usbh2 = { | ||
| 274 | .name = "mxc-ehci", | ||
| 275 | .id = 2, | ||
| 276 | .dev = { | ||
| 277 | .coherent_dma_mask = 0xffffffff, | ||
| 278 | .dma_mask = &usbh2_dmamask, | ||
| 279 | }, | ||
| 280 | .resource = mxc_usbh2_resources, | ||
| 281 | .num_resources = ARRAY_SIZE(mxc_usbh2_resources), | ||
| 282 | }; | ||
| 283 | |||
| 284 | static struct resource imx_wdt_resources[] = { | ||
| 285 | { | ||
| 286 | .flags = IORESOURCE_MEM, | ||
| 287 | }, | ||
| 288 | }; | ||
| 289 | |||
| 290 | struct platform_device imx_wdt_device0 = { | ||
| 291 | .name = "imx2-wdt", | ||
| 292 | .id = 0, | ||
| 293 | .num_resources = ARRAY_SIZE(imx_wdt_resources), | ||
| 294 | .resource = imx_wdt_resources, | ||
| 295 | }; | ||
| 296 | |||
| 297 | static struct resource imx_rtc_resources[] = { | 98 | static struct resource imx_rtc_resources[] = { |
| 298 | { | 99 | { |
| 299 | .start = MX31_RTC_BASE_ADDR, | 100 | .start = MX31_RTC_BASE_ADDR, |
| @@ -312,51 +113,3 @@ struct platform_device imx_rtc_device0 = { | |||
| 312 | .num_resources = ARRAY_SIZE(imx_rtc_resources), | 113 | .num_resources = ARRAY_SIZE(imx_rtc_resources), |
| 313 | .resource = imx_rtc_resources, | 114 | .resource = imx_rtc_resources, |
| 314 | }; | 115 | }; |
| 315 | |||
| 316 | static struct resource imx_kpp_resources[] = { | ||
| 317 | { | ||
| 318 | .start = MX3x_KPP_BASE_ADDR, | ||
| 319 | .end = MX3x_KPP_BASE_ADDR + 0xf, | ||
| 320 | .flags = IORESOURCE_MEM | ||
| 321 | }, { | ||
| 322 | .start = MX3x_INT_KPP, | ||
| 323 | .end = MX3x_INT_KPP, | ||
| 324 | .flags = IORESOURCE_IRQ, | ||
| 325 | }, | ||
| 326 | }; | ||
| 327 | |||
| 328 | struct platform_device imx_kpp_device = { | ||
| 329 | .name = "imx-keypad", | ||
| 330 | .id = -1, | ||
| 331 | .num_resources = ARRAY_SIZE(imx_kpp_resources), | ||
| 332 | .resource = imx_kpp_resources, | ||
| 333 | }; | ||
| 334 | |||
| 335 | static int __init mx3_devices_init(void) | ||
| 336 | { | ||
| 337 | #if defined(CONFIG_ARCH_MX31) | ||
| 338 | if (cpu_is_mx31()) { | ||
| 339 | imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR; | ||
| 340 | imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff; | ||
| 341 | mxc_register_device(&mxc_rnga_device, NULL); | ||
| 342 | } | ||
| 343 | #endif | ||
| 344 | #if defined(CONFIG_ARCH_MX35) | ||
| 345 | if (cpu_is_mx35()) { | ||
| 346 | otg_resources[0].start = MX35_OTG_BASE_ADDR; | ||
| 347 | otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff; | ||
| 348 | otg_resources[1].start = MXC_INT_USBOTG; | ||
| 349 | otg_resources[1].end = MXC_INT_USBOTG; | ||
| 350 | mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400; | ||
| 351 | mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff; | ||
| 352 | mxc_usbh1_resources[1].start = MXC_INT_USBHS; | ||
| 353 | mxc_usbh1_resources[1].end = MXC_INT_USBHS; | ||
| 354 | imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR; | ||
| 355 | imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff; | ||
| 356 | } | ||
| 357 | #endif | ||
| 358 | |||
| 359 | return 0; | ||
| 360 | } | ||
| 361 | |||
| 362 | subsys_initcall(mx3_devices_init); | ||
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h index 585f814473d5..121962c568d1 100644 --- a/arch/arm/mach-mx3/devices.h +++ b/arch/arm/mach-mx3/devices.h | |||
| @@ -1,14 +1,4 @@ | |||
| 1 | extern struct platform_device mxc_w1_master_device; | ||
| 2 | extern struct platform_device mx3_ipu; | 1 | extern struct platform_device mx3_ipu; |
| 3 | extern struct platform_device mx3_fb; | 2 | extern struct platform_device mx3_fb; |
| 4 | extern struct platform_device mx3_camera; | 3 | extern struct platform_device mx3_camera; |
| 5 | extern struct platform_device mxcsdhc_device0; | ||
| 6 | extern struct platform_device mxcsdhc_device1; | ||
| 7 | extern struct platform_device mxc_otg_udc_device; | ||
| 8 | extern struct platform_device mxc_otg_host; | ||
| 9 | extern struct platform_device mxc_usbh1; | ||
| 10 | extern struct platform_device mxc_usbh2; | ||
| 11 | extern struct platform_device mxc_rnga_device; | ||
| 12 | extern struct platform_device imx_wdt_device0; | ||
| 13 | extern struct platform_device imx_rtc_device0; | 4 | extern struct platform_device imx_rtc_device0; |
| 14 | extern struct platform_device imx_kpp_device; | ||
diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c index 1abc10d52922..14a5ffc939ad 100644 --- a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c +++ b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c | |||
| @@ -111,7 +111,7 @@ static struct mx3fb_platform_data mx3fb_pdata = { | |||
| 111 | .num_modes = ARRAY_SIZE(fb_modedb), | 111 | .num_modes = ARRAY_SIZE(fb_modedb), |
| 112 | }; | 112 | }; |
| 113 | 113 | ||
| 114 | static struct pad_desc eukrea_mbimxsd_pads[] = { | 114 | static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = { |
| 115 | /* LCD */ | 115 | /* LCD */ |
| 116 | MX35_PAD_LD0__IPU_DISPB_DAT_0, | 116 | MX35_PAD_LD0__IPU_DISPB_DAT_0, |
| 117 | MX35_PAD_LD1__IPU_DISPB_DAT_1, | 117 | MX35_PAD_LD1__IPU_DISPB_DAT_1, |
| @@ -289,7 +289,7 @@ void __init eukrea_mbimxsd35_baseboard_init(void) | |||
| 289 | imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); | 289 | imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); |
| 290 | 290 | ||
| 291 | imx35_add_flexcan1(NULL); | 291 | imx35_add_flexcan1(NULL); |
| 292 | imx35_add_esdhc(0, NULL); | 292 | imx35_add_sdhci_esdhc_imx(0, NULL); |
| 293 | 293 | ||
| 294 | gpio_request(GPIO_LED1, "LED1"); | 294 | gpio_request(GPIO_LED1, "LED1"); |
| 295 | gpio_direction_output(GPIO_LED1, 1); | 295 | gpio_direction_output(GPIO_LED1, 1); |
diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c index aaa30fe18f85..28b6f414b5d5 100644 --- a/arch/arm/mach-mx3/mach-armadillo5x0.c +++ b/arch/arm/mach-mx3/mach-armadillo5x0.c | |||
| @@ -49,10 +49,8 @@ | |||
| 49 | 49 | ||
| 50 | #include <mach/common.h> | 50 | #include <mach/common.h> |
| 51 | #include <mach/iomux-mx3.h> | 51 | #include <mach/iomux-mx3.h> |
| 52 | #include <mach/mmc.h> | ||
| 53 | #include <mach/ipu.h> | 52 | #include <mach/ipu.h> |
| 54 | #include <mach/mx3fb.h> | 53 | #include <mach/mx3fb.h> |
| 55 | #include <mach/mxc_ehci.h> | ||
| 56 | #include <mach/ulpi.h> | 54 | #include <mach/ulpi.h> |
| 57 | 55 | ||
| 58 | #include "devices-imx31.h" | 56 | #include "devices-imx31.h" |
| @@ -245,13 +243,13 @@ h2_free_cs: | |||
| 245 | return err; | 243 | return err; |
| 246 | } | 244 | } |
| 247 | 245 | ||
| 248 | static struct mxc_usbh_platform_data usbotg_pdata = { | 246 | static struct mxc_usbh_platform_data usbotg_pdata __initdata = { |
| 249 | .init = usbotg_init, | 247 | .init = usbotg_init, |
| 250 | .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, | 248 | .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, |
| 251 | .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI, | 249 | .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI, |
| 252 | }; | 250 | }; |
| 253 | 251 | ||
| 254 | static struct mxc_usbh_platform_data usbh2_pdata = { | 252 | static struct mxc_usbh_platform_data usbh2_pdata __initdata = { |
| 255 | .init = usbh2_init, | 253 | .init = usbh2_init, |
| 256 | .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, | 254 | .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, |
| 257 | .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI, | 255 | .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI, |
| @@ -453,7 +451,7 @@ static void armadillo5x0_sdhc1_exit(struct device *dev, void *data) | |||
| 453 | gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B)); | 451 | gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B)); |
| 454 | } | 452 | } |
| 455 | 453 | ||
| 456 | static struct imxmmc_platform_data sdhc_pdata = { | 454 | static const struct imxmmc_platform_data sdhc_pdata __initconst = { |
| 457 | .get_ro = armadillo5x0_sdhc1_get_ro, | 455 | .get_ro = armadillo5x0_sdhc1_get_ro, |
| 458 | .init = armadillo5x0_sdhc1_init, | 456 | .init = armadillo5x0_sdhc1_init, |
| 459 | .exit = armadillo5x0_sdhc1_exit, | 457 | .exit = armadillo5x0_sdhc1_exit, |
| @@ -520,7 +518,7 @@ static void __init armadillo5x0_init(void) | |||
| 520 | gpio_direction_input(MX31_PIN_GPIO1_0); | 518 | gpio_direction_input(MX31_PIN_GPIO1_0); |
| 521 | 519 | ||
| 522 | /* Register SDHC */ | 520 | /* Register SDHC */ |
| 523 | mxc_register_device(&mxcsdhc_device0, &sdhc_pdata); | 521 | imx31_add_mxc_mmc(0, &sdhc_pdata); |
| 524 | 522 | ||
| 525 | /* Register FB */ | 523 | /* Register FB */ |
| 526 | mxc_register_device(&mx3_ipu, &mx3_ipu_data); | 524 | mxc_register_device(&mx3_ipu, &mx3_ipu_data); |
| @@ -555,8 +553,8 @@ static void __init armadillo5x0_init(void) | |||
| 555 | usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, | 553 | usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, |
| 556 | ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); | 554 | ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); |
| 557 | 555 | ||
| 558 | mxc_register_device(&mxc_otg_host, &usbotg_pdata); | 556 | imx31_add_mxc_ehci_otg(&usbotg_pdata); |
| 559 | mxc_register_device(&mxc_usbh2, &usbh2_pdata); | 557 | imx31_add_mxc_ehci_hs(2, &usbh2_pdata); |
| 560 | #endif | 558 | #endif |
| 561 | } | 559 | } |
| 562 | 560 | ||
diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c index 9fde873f5889..26ae90f02582 100644 --- a/arch/arm/mach-mx3/mach-cpuimx35.c +++ b/arch/arm/mach-mx3/mach-cpuimx35.c | |||
| @@ -30,7 +30,6 @@ | |||
| 30 | #include <linux/i2c/tsc2007.h> | 30 | #include <linux/i2c/tsc2007.h> |
| 31 | #include <linux/usb/otg.h> | 31 | #include <linux/usb/otg.h> |
| 32 | #include <linux/usb/ulpi.h> | 32 | #include <linux/usb/ulpi.h> |
| 33 | #include <linux/fsl_devices.h> | ||
| 34 | #include <linux/i2c-gpio.h> | 33 | #include <linux/i2c-gpio.h> |
| 35 | 34 | ||
| 36 | #include <asm/mach-types.h> | 35 | #include <asm/mach-types.h> |
| @@ -43,7 +42,6 @@ | |||
| 43 | #include <mach/common.h> | 42 | #include <mach/common.h> |
| 44 | #include <mach/iomux-mx35.h> | 43 | #include <mach/iomux-mx35.h> |
| 45 | #include <mach/mxc_nand.h> | 44 | #include <mach/mxc_nand.h> |
| 46 | #include <mach/mxc_ehci.h> | ||
| 47 | 45 | ||
| 48 | #include "devices-imx35.h" | 46 | #include "devices-imx35.h" |
| 49 | #include "devices.h" | 47 | #include "devices.h" |
| @@ -74,11 +72,7 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = { | |||
| 74 | }, | 72 | }, |
| 75 | }; | 73 | }; |
| 76 | 74 | ||
| 77 | static struct platform_device *devices[] __initdata = { | 75 | static iomux_v3_cfg_t eukrea_cpuimx35_pads[] = { |
| 78 | &imx_wdt_device0, | ||
| 79 | }; | ||
| 80 | |||
| 81 | static struct pad_desc eukrea_cpuimx35_pads[] = { | ||
| 82 | /* UART1 */ | 76 | /* UART1 */ |
| 83 | MX35_PAD_CTS1__UART1_CTS, | 77 | MX35_PAD_CTS1__UART1_CTS, |
| 84 | MX35_PAD_RTS1__UART1_RTS, | 78 | MX35_PAD_RTS1__UART1_RTS, |
| @@ -117,18 +111,18 @@ static const struct mxc_nand_platform_data | |||
| 117 | .flash_bbt = 1, | 111 | .flash_bbt = 1, |
| 118 | }; | 112 | }; |
| 119 | 113 | ||
| 120 | static struct mxc_usbh_platform_data __maybe_unused otg_pdata = { | 114 | static const struct mxc_usbh_platform_data otg_pdata __initconst = { |
| 121 | .portsc = MXC_EHCI_MODE_UTMI, | 115 | .portsc = MXC_EHCI_MODE_UTMI, |
| 122 | .flags = MXC_EHCI_INTERFACE_DIFF_UNI, | 116 | .flags = MXC_EHCI_INTERFACE_DIFF_UNI, |
| 123 | }; | 117 | }; |
| 124 | 118 | ||
| 125 | static struct mxc_usbh_platform_data __maybe_unused usbh1_pdata = { | 119 | static const struct mxc_usbh_platform_data usbh1_pdata __initconst = { |
| 126 | .portsc = MXC_EHCI_MODE_SERIAL, | 120 | .portsc = MXC_EHCI_MODE_SERIAL, |
| 127 | .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | | 121 | .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | |
| 128 | MXC_EHCI_IPPUE_DOWN, | 122 | MXC_EHCI_IPPUE_DOWN, |
| 129 | }; | 123 | }; |
| 130 | 124 | ||
| 131 | static struct fsl_usb2_platform_data otg_device_pdata = { | 125 | static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { |
| 132 | .operating_mode = FSL_USB2_DR_DEVICE, | 126 | .operating_mode = FSL_USB2_DR_DEVICE, |
| 133 | .phy_mode = FSL_USB2_PHY_UTMI, | 127 | .phy_mode = FSL_USB2_PHY_UTMI, |
| 134 | .workaround = FLS_USB2_WORKAROUND_ENGCM09152, | 128 | .workaround = FLS_USB2_WORKAROUND_ENGCM09152, |
| @@ -158,7 +152,7 @@ static void __init mxc_board_init(void) | |||
| 158 | ARRAY_SIZE(eukrea_cpuimx35_pads)); | 152 | ARRAY_SIZE(eukrea_cpuimx35_pads)); |
| 159 | 153 | ||
| 160 | imx35_add_fec(NULL); | 154 | imx35_add_fec(NULL); |
| 161 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 155 | imx35_add_imx2_wdt(NULL); |
| 162 | 156 | ||
| 163 | imx35_add_imx_uart0(&uart_pdata); | 157 | imx35_add_imx_uart0(&uart_pdata); |
| 164 | imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info); | 158 | imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info); |
| @@ -168,11 +162,11 @@ static void __init mxc_board_init(void) | |||
| 168 | imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data); | 162 | imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data); |
| 169 | 163 | ||
| 170 | if (otg_mode_host) | 164 | if (otg_mode_host) |
| 171 | mxc_register_device(&mxc_otg_host, &otg_pdata); | 165 | imx35_add_mxc_ehci_otg(&otg_pdata); |
| 172 | else | 166 | else |
| 173 | mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); | 167 | imx35_add_fsl_usb2_udc(&otg_device_pdata); |
| 174 | 168 | ||
| 175 | mxc_register_device(&mxc_usbh1, &usbh1_pdata); | 169 | imx35_add_mxc_ehci_hs(&usbh1_pdata); |
| 176 | 170 | ||
| 177 | #ifdef CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD | 171 | #ifdef CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD |
| 178 | eukrea_mbimxsd35_baseboard_init(); | 172 | eukrea_mbimxsd35_baseboard_init(); |
diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c index 042cd5655e17..a5f3eb24e4d5 100644 --- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c +++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c | |||
| @@ -41,9 +41,9 @@ | |||
| 41 | #include "devices-imx31.h" | 41 | #include "devices-imx31.h" |
| 42 | #include "devices.h" | 42 | #include "devices.h" |
| 43 | 43 | ||
| 44 | #define KZM_ARM11_IO_ADDRESS(x) ( \ | 44 | #define KZM_ARM11_IO_ADDRESS(x) (IOMEM( \ |
| 45 | IMX_IO_ADDRESS(x, MX31_CS4) ?: \ | 45 | IMX_IO_P2V_MODULE(x, MX31_CS4) ?: \ |
| 46 | IMX_IO_ADDRESS(x, MX31_CS5) ?: \ | 46 | IMX_IO_P2V_MODULE(x, MX31_CS5)) ?: \ |
| 47 | MX31_IO_ADDRESS(x)) | 47 | MX31_IO_ADDRESS(x)) |
| 48 | 48 | ||
| 49 | /* | 49 | /* |
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c index 0ad9e7821082..4e516b49a901 100644 --- a/arch/arm/mach-mx3/mach-mx31_3ds.c +++ b/arch/arm/mach-mx3/mach-mx31_3ds.c | |||
| @@ -22,8 +22,8 @@ | |||
| 22 | #include <linux/mfd/mc13783.h> | 22 | #include <linux/mfd/mc13783.h> |
| 23 | #include <linux/spi/spi.h> | 23 | #include <linux/spi/spi.h> |
| 24 | #include <linux/regulator/machine.h> | 24 | #include <linux/regulator/machine.h> |
| 25 | #include <linux/fsl_devices.h> | 25 | #include <linux/usb/otg.h> |
| 26 | #include <linux/input/matrix_keypad.h> | 26 | #include <linux/usb/ulpi.h> |
| 27 | 27 | ||
| 28 | #include <mach/hardware.h> | 28 | #include <mach/hardware.h> |
| 29 | #include <asm/mach-types.h> | 29 | #include <asm/mach-types.h> |
| @@ -34,6 +34,7 @@ | |||
| 34 | #include <mach/common.h> | 34 | #include <mach/common.h> |
| 35 | #include <mach/iomux-mx3.h> | 35 | #include <mach/iomux-mx3.h> |
| 36 | #include <mach/3ds_debugboard.h> | 36 | #include <mach/3ds_debugboard.h> |
| 37 | #include <mach/ulpi.h> | ||
| 37 | 38 | ||
| 38 | #include "devices-imx31.h" | 39 | #include "devices-imx31.h" |
| 39 | #include "devices.h" | 40 | #include "devices.h" |
| @@ -84,6 +85,21 @@ static int mx31_3ds_pins[] = { | |||
| 84 | MX31_PIN_KEY_COL1_KEY_COL1, | 85 | MX31_PIN_KEY_COL1_KEY_COL1, |
| 85 | MX31_PIN_KEY_COL2_KEY_COL2, | 86 | MX31_PIN_KEY_COL2_KEY_COL2, |
| 86 | MX31_PIN_KEY_COL3_KEY_COL3, | 87 | MX31_PIN_KEY_COL3_KEY_COL3, |
| 88 | /* USB Host 2 */ | ||
| 89 | IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC), | ||
| 90 | IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC), | ||
| 91 | IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC), | ||
| 92 | IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC), | ||
| 93 | IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC), | ||
| 94 | IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC), | ||
| 95 | IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT1), | ||
| 96 | IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT1), | ||
| 97 | IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT1), | ||
| 98 | IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT1), | ||
| 99 | IOMUX_MODE(MX31_PIN_IOIS16, IOMUX_CONFIG_ALT1), | ||
| 100 | IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1), | ||
| 101 | /* USB Host2 reset */ | ||
| 102 | IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO), | ||
| 87 | }; | 103 | }; |
| 88 | 104 | ||
| 89 | /* | 105 | /* |
| @@ -102,7 +118,7 @@ static const uint32_t mx31_3ds_keymap[] = { | |||
| 102 | KEY(2, 3, KEY_F10), | 118 | KEY(2, 3, KEY_F10), |
| 103 | }; | 119 | }; |
| 104 | 120 | ||
| 105 | static struct matrix_keymap_data mx31_3ds_keymap_data = { | 121 | static const struct matrix_keymap_data mx31_3ds_keymap_data __initconst = { |
| 106 | .keymap = mx31_3ds_keymap, | 122 | .keymap = mx31_3ds_keymap, |
| 107 | .keymap_size = ARRAY_SIZE(mx31_3ds_keymap), | 123 | .keymap_size = ARRAY_SIZE(mx31_3ds_keymap), |
| 108 | }; | 124 | }; |
| @@ -115,6 +131,13 @@ static struct regulator_init_data pwgtx_init = { | |||
| 115 | }, | 131 | }, |
| 116 | }; | 132 | }; |
| 117 | 133 | ||
| 134 | static struct regulator_init_data gpo_init = { | ||
| 135 | .constraints = { | ||
| 136 | .boot_on = 1, | ||
| 137 | .always_on = 1, | ||
| 138 | } | ||
| 139 | }; | ||
| 140 | |||
| 118 | static struct mc13783_regulator_init_data mx31_3ds_regulators[] = { | 141 | static struct mc13783_regulator_init_data mx31_3ds_regulators[] = { |
| 119 | { | 142 | { |
| 120 | .id = MC13783_REGU_PWGT1SPI, /* Power Gate for ARM core. */ | 143 | .id = MC13783_REGU_PWGT1SPI, /* Power Gate for ARM core. */ |
| @@ -122,6 +145,13 @@ static struct mc13783_regulator_init_data mx31_3ds_regulators[] = { | |||
| 122 | }, { | 145 | }, { |
| 123 | .id = MC13783_REGU_PWGT2SPI, /* Power Gate for L2 Cache. */ | 146 | .id = MC13783_REGU_PWGT2SPI, /* Power Gate for L2 Cache. */ |
| 124 | .init_data = &pwgtx_init, | 147 | .init_data = &pwgtx_init, |
| 148 | }, { | ||
| 149 | |||
| 150 | .id = MC13783_REGU_GPO1, /* Turn on 1.8V */ | ||
| 151 | .init_data = &gpo_init, | ||
| 152 | }, { | ||
| 153 | .id = MC13783_REGU_GPO3, /* Turn on 3.3V */ | ||
| 154 | .init_data = &gpo_init, | ||
| 125 | }, | 155 | }, |
| 126 | }; | 156 | }; |
| 127 | 157 | ||
| @@ -129,7 +159,7 @@ static struct mc13783_regulator_init_data mx31_3ds_regulators[] = { | |||
| 129 | static struct mc13783_platform_data mc13783_pdata __initdata = { | 159 | static struct mc13783_platform_data mc13783_pdata __initdata = { |
| 130 | .regulators = mx31_3ds_regulators, | 160 | .regulators = mx31_3ds_regulators, |
| 131 | .num_regulators = ARRAY_SIZE(mx31_3ds_regulators), | 161 | .num_regulators = ARRAY_SIZE(mx31_3ds_regulators), |
| 132 | .flags = MC13783_USE_REGULATOR, | 162 | .flags = MC13783_USE_REGULATOR | MC13783_USE_TOUCHSCREEN, |
| 133 | }; | 163 | }; |
| 134 | 164 | ||
| 135 | /* SPI */ | 165 | /* SPI */ |
| @@ -175,6 +205,7 @@ mx31_3ds_nand_board_info __initconst = { | |||
| 175 | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) | 205 | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) |
| 176 | 206 | ||
| 177 | #define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR) | 207 | #define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR) |
| 208 | #define USBH2_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_BYP) | ||
| 178 | 209 | ||
| 179 | static int mx31_3ds_usbotg_init(void) | 210 | static int mx31_3ds_usbotg_init(void) |
| 180 | { | 211 | { |
| @@ -214,11 +245,77 @@ usbotg_free_reset: | |||
| 214 | return err; | 245 | return err; |
| 215 | } | 246 | } |
| 216 | 247 | ||
| 217 | static struct fsl_usb2_platform_data usbotg_pdata = { | 248 | static int mx31_3ds_host2_init(struct platform_device *pdev) |
| 249 | { | ||
| 250 | int err; | ||
| 251 | |||
| 252 | mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG); | ||
| 253 | mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG); | ||
| 254 | mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG); | ||
| 255 | mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG); | ||
| 256 | mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG); | ||
| 257 | mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG); | ||
| 258 | mxc_iomux_set_pad(MX31_PIN_PC_VS2, USB_PAD_CFG); | ||
| 259 | mxc_iomux_set_pad(MX31_PIN_PC_BVD1, USB_PAD_CFG); | ||
| 260 | mxc_iomux_set_pad(MX31_PIN_PC_BVD2, USB_PAD_CFG); | ||
| 261 | mxc_iomux_set_pad(MX31_PIN_PC_RST, USB_PAD_CFG); | ||
| 262 | mxc_iomux_set_pad(MX31_PIN_IOIS16, USB_PAD_CFG); | ||
| 263 | mxc_iomux_set_pad(MX31_PIN_PC_RW_B, USB_PAD_CFG); | ||
| 264 | |||
| 265 | err = gpio_request(USBH2_RST_B, "usbh2-reset"); | ||
| 266 | if (err) { | ||
| 267 | pr_err("Failed to request the USB Host 2 reset gpio\n"); | ||
| 268 | return err; | ||
| 269 | } | ||
| 270 | |||
| 271 | err = gpio_direction_output(USBH2_RST_B, 0); | ||
| 272 | if (err) { | ||
| 273 | pr_err("Failed to drive the USB Host 2 reset gpio\n"); | ||
| 274 | goto usbotg_free_reset; | ||
| 275 | } | ||
| 276 | |||
| 277 | mdelay(1); | ||
| 278 | gpio_set_value(USBH2_RST_B, 1); | ||
| 279 | return 0; | ||
| 280 | |||
| 281 | usbotg_free_reset: | ||
| 282 | gpio_free(USBH2_RST_B); | ||
| 283 | return err; | ||
| 284 | } | ||
| 285 | |||
| 286 | #if defined(CONFIG_USB_ULPI) | ||
| 287 | static struct mxc_usbh_platform_data otg_pdata __initdata = { | ||
| 288 | .portsc = MXC_EHCI_MODE_ULPI, | ||
| 289 | .flags = MXC_EHCI_POWER_PINS_ENABLED, | ||
| 290 | }; | ||
| 291 | |||
| 292 | static struct mxc_usbh_platform_data usbh2_pdata __initdata = { | ||
| 293 | .init = mx31_3ds_host2_init, | ||
| 294 | .portsc = MXC_EHCI_MODE_ULPI, | ||
| 295 | .flags = MXC_EHCI_POWER_PINS_ENABLED, | ||
| 296 | }; | ||
| 297 | #endif | ||
| 298 | |||
| 299 | static const struct fsl_usb2_platform_data usbotg_pdata __initconst = { | ||
| 218 | .operating_mode = FSL_USB2_DR_DEVICE, | 300 | .operating_mode = FSL_USB2_DR_DEVICE, |
| 219 | .phy_mode = FSL_USB2_PHY_ULPI, | 301 | .phy_mode = FSL_USB2_PHY_ULPI, |
| 220 | }; | 302 | }; |
| 221 | 303 | ||
| 304 | static int otg_mode_host; | ||
| 305 | |||
| 306 | static int __init mx31_3ds_otg_mode(char *options) | ||
| 307 | { | ||
| 308 | if (!strcmp(options, "host")) | ||
| 309 | otg_mode_host = 1; | ||
| 310 | else if (!strcmp(options, "device")) | ||
| 311 | otg_mode_host = 0; | ||
| 312 | else | ||
| 313 | pr_info("otg_mode neither \"host\" nor \"device\". " | ||
| 314 | "Defaulting to device\n"); | ||
| 315 | return 0; | ||
| 316 | } | ||
| 317 | __setup("otg_mode=", mx31_3ds_otg_mode); | ||
| 318 | |||
| 222 | static const struct imxuart_platform_data uart_pdata __initconst = { | 319 | static const struct imxuart_platform_data uart_pdata __initconst = { |
| 223 | .flags = IMXUART_HAVE_RTSCTS, | 320 | .flags = IMXUART_HAVE_RTSCTS, |
| 224 | }; | 321 | }; |
| @@ -246,14 +343,27 @@ static void __init mxc_board_init(void) | |||
| 246 | spi_register_board_info(mx31_3ds_spi_devs, | 343 | spi_register_board_info(mx31_3ds_spi_devs, |
| 247 | ARRAY_SIZE(mx31_3ds_spi_devs)); | 344 | ARRAY_SIZE(mx31_3ds_spi_devs)); |
| 248 | 345 | ||
| 249 | mxc_register_device(&imx_kpp_device, &mx31_3ds_keymap_data); | 346 | imx31_add_imx_keypad(&mx31_3ds_keymap_data); |
| 250 | 347 | ||
| 251 | mx31_3ds_usbotg_init(); | 348 | mx31_3ds_usbotg_init(); |
| 252 | mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata); | 349 | #if defined(CONFIG_USB_ULPI) |
| 350 | if (otg_mode_host) { | ||
| 351 | otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, | ||
| 352 | ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); | ||
| 353 | |||
| 354 | imx31_add_mxc_ehci_otg(&otg_pdata); | ||
| 355 | } | ||
| 356 | usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, | ||
| 357 | ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); | ||
| 358 | imx31_add_mxc_ehci_hs(2, &usbh2_pdata); | ||
| 359 | #endif | ||
| 360 | if (!otg_mode_host) | ||
| 361 | imx31_add_fsl_usb2_udc(&usbotg_pdata); | ||
| 253 | 362 | ||
| 254 | if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT)) | 363 | if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT)) |
| 255 | printk(KERN_WARNING "Init of the debug board failed, all " | 364 | printk(KERN_WARNING "Init of the debug board failed, all " |
| 256 | "devices on the debug board are unusable.\n"); | 365 | "devices on the debug board are unusable.\n"); |
| 366 | imx31_add_imx2_wdt(NULL); | ||
| 257 | } | 367 | } |
| 258 | 368 | ||
| 259 | static void __init mx31_3ds_timer_init(void) | 369 | static void __init mx31_3ds_timer_init(void) |
diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c index 42f47faa6fd6..2c595483f356 100644 --- a/arch/arm/mach-mx3/mach-mx31lilly.c +++ b/arch/arm/mach-mx3/mach-mx31lilly.c | |||
| @@ -42,7 +42,6 @@ | |||
| 42 | #include <mach/common.h> | 42 | #include <mach/common.h> |
| 43 | #include <mach/iomux-mx3.h> | 43 | #include <mach/iomux-mx3.h> |
| 44 | #include <mach/board-mx31lilly.h> | 44 | #include <mach/board-mx31lilly.h> |
| 45 | #include <mach/mxc_ehci.h> | ||
| 46 | #include <mach/ulpi.h> | 45 | #include <mach/ulpi.h> |
| 47 | 46 | ||
| 48 | #include "devices-imx31.h" | 47 | #include "devices-imx31.h" |
| @@ -230,13 +229,13 @@ static struct mxc_usbh_platform_data usbotg_pdata = { | |||
| 230 | .flags = MXC_EHCI_POWER_PINS_ENABLED, | 229 | .flags = MXC_EHCI_POWER_PINS_ENABLED, |
| 231 | }; | 230 | }; |
| 232 | 231 | ||
| 233 | static struct mxc_usbh_platform_data usbh1_pdata = { | 232 | static const struct mxc_usbh_platform_data usbh1_pdata __initconst = { |
| 234 | .init = usbh1_init, | 233 | .init = usbh1_init, |
| 235 | .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, | 234 | .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, |
| 236 | .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI, | 235 | .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI, |
| 237 | }; | 236 | }; |
| 238 | 237 | ||
| 239 | static struct mxc_usbh_platform_data usbh2_pdata = { | 238 | static struct mxc_usbh_platform_data usbh2_pdata __initdata = { |
| 240 | .init = usbh2_init, | 239 | .init = usbh2_init, |
| 241 | .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, | 240 | .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, |
| 242 | .flags = MXC_EHCI_POWER_PINS_ENABLED, | 241 | .flags = MXC_EHCI_POWER_PINS_ENABLED, |
| @@ -249,8 +248,8 @@ static void lilly1131_usb_init(void) | |||
| 249 | usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, | 248 | usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, |
| 250 | ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); | 249 | ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); |
| 251 | 250 | ||
| 252 | mxc_register_device(&mxc_usbh1, &usbh1_pdata); | 251 | imx31_add_mxc_ehci_hs(1, &usbh1_pdata); |
| 253 | mxc_register_device(&mxc_usbh2, &usbh2_pdata); | 252 | imx31_add_mxc_ehci_hs(2, &usbh2_pdata); |
| 254 | } | 253 | } |
| 255 | 254 | ||
| 256 | #else | 255 | #else |
diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c index b93895814cdf..9e64c66396e0 100644 --- a/arch/arm/mach-mx3/mach-mx31lite.c +++ b/arch/arm/mach-mx3/mach-mx31lite.c | |||
| @@ -40,7 +40,6 @@ | |||
| 40 | #include <mach/board-mx31lite.h> | 40 | #include <mach/board-mx31lite.h> |
| 41 | #include <mach/iomux-mx3.h> | 41 | #include <mach/iomux-mx3.h> |
| 42 | #include <mach/irqs.h> | 42 | #include <mach/irqs.h> |
| 43 | #include <mach/mxc_ehci.h> | ||
| 44 | #include <mach/ulpi.h> | 43 | #include <mach/ulpi.h> |
| 45 | 44 | ||
| 46 | #include "devices-imx31.h" | 45 | #include "devices-imx31.h" |
| @@ -171,7 +170,7 @@ static int usbh2_init(struct platform_device *pdev) | |||
| 171 | return 0; | 170 | return 0; |
| 172 | } | 171 | } |
| 173 | 172 | ||
| 174 | static struct mxc_usbh_platform_data usbh2_pdata = { | 173 | static struct mxc_usbh_platform_data usbh2_pdata __initdata = { |
| 175 | .init = usbh2_init, | 174 | .init = usbh2_init, |
| 176 | .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, | 175 | .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, |
| 177 | .flags = MXC_EHCI_POWER_PINS_ENABLED, | 176 | .flags = MXC_EHCI_POWER_PINS_ENABLED, |
| @@ -258,7 +257,7 @@ static void __init mxc_board_init(void) | |||
| 258 | usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, | 257 | usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, |
| 259 | ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); | 258 | ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); |
| 260 | 259 | ||
| 261 | mxc_register_device(&mxc_usbh2, &usbh2_pdata); | 260 | imx31_add_mxc_ehci_hs(2, &usbh2_pdata); |
| 262 | #endif | 261 | #endif |
| 263 | 262 | ||
| 264 | /* SMSC9117 IRQ pin */ | 263 | /* SMSC9117 IRQ pin */ |
diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c index eb5f426df224..203d21a510aa 100644 --- a/arch/arm/mach-mx3/mach-mx31moboard.c +++ b/arch/arm/mach-mx3/mach-mx31moboard.c | |||
| @@ -40,8 +40,6 @@ | |||
| 40 | #include <mach/hardware.h> | 40 | #include <mach/hardware.h> |
| 41 | #include <mach/iomux-mx3.h> | 41 | #include <mach/iomux-mx3.h> |
| 42 | #include <mach/ipu.h> | 42 | #include <mach/ipu.h> |
| 43 | #include <mach/mmc.h> | ||
| 44 | #include <mach/mxc_ehci.h> | ||
| 45 | #include <mach/mx3_camera.h> | 43 | #include <mach/mx3_camera.h> |
| 46 | #include <mach/spi.h> | 44 | #include <mach/spi.h> |
| 47 | #include <mach/ulpi.h> | 45 | #include <mach/ulpi.h> |
| @@ -170,11 +168,11 @@ static const struct spi_imx_master moboard_spi1_pdata __initconst = { | |||
| 170 | 168 | ||
| 171 | static struct regulator_consumer_supply sdhc_consumers[] = { | 169 | static struct regulator_consumer_supply sdhc_consumers[] = { |
| 172 | { | 170 | { |
| 173 | .dev = &mxcsdhc_device0.dev, | 171 | .dev_name = "mxc-mmc.0", |
| 174 | .supply = "sdhc0_vcc", | 172 | .supply = "sdhc0_vcc", |
| 175 | }, | 173 | }, |
| 176 | { | 174 | { |
| 177 | .dev = &mxcsdhc_device1.dev, | 175 | .dev_name = "mxc-mmc.1", |
| 178 | .supply = "sdhc1_vcc", | 176 | .supply = "sdhc1_vcc", |
| 179 | }, | 177 | }, |
| 180 | }; | 178 | }; |
| @@ -345,7 +343,7 @@ static void moboard_sdhc1_exit(struct device *dev, void *data) | |||
| 345 | gpio_free(SDHC1_CD); | 343 | gpio_free(SDHC1_CD); |
| 346 | } | 344 | } |
| 347 | 345 | ||
| 348 | static struct imxmmc_platform_data sdhc1_pdata = { | 346 | static const struct imxmmc_platform_data sdhc1_pdata __initconst = { |
| 349 | .get_ro = moboard_sdhc1_get_ro, | 347 | .get_ro = moboard_sdhc1_get_ro, |
| 350 | .init = moboard_sdhc1_init, | 348 | .init = moboard_sdhc1_init, |
| 351 | .exit = moboard_sdhc1_exit, | 349 | .exit = moboard_sdhc1_exit, |
| @@ -404,17 +402,23 @@ static void usb_xcvr_reset(void) | |||
| 404 | 402 | ||
| 405 | #if defined(CONFIG_USB_ULPI) | 403 | #if defined(CONFIG_USB_ULPI) |
| 406 | 404 | ||
| 407 | static struct mxc_usbh_platform_data usbh2_pdata = { | 405 | static struct mxc_usbh_platform_data usbh2_pdata __initdata = { |
| 408 | .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, | 406 | .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, |
| 409 | .flags = MXC_EHCI_POWER_PINS_ENABLED, | 407 | .flags = MXC_EHCI_POWER_PINS_ENABLED, |
| 410 | }; | 408 | }; |
| 411 | 409 | ||
| 412 | static int __init moboard_usbh2_init(void) | 410 | static int __init moboard_usbh2_init(void) |
| 413 | { | 411 | { |
| 412 | struct platform_device *pdev; | ||
| 413 | |||
| 414 | usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, | 414 | usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, |
| 415 | ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); | 415 | ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); |
| 416 | 416 | ||
| 417 | return mxc_register_device(&mxc_usbh2, &usbh2_pdata); | 417 | pdev = imx31_add_mxc_ehci_hs(2, &usbh2_pdata); |
| 418 | if (IS_ERR(pdev)) | ||
| 419 | return PTR_ERR(pdev); | ||
| 420 | |||
| 421 | return 0; | ||
| 418 | } | 422 | } |
| 419 | #else | 423 | #else |
| 420 | static inline int moboard_usbh2_init(void) { return 0; } | 424 | static inline int moboard_usbh2_init(void) { return 0; } |
| @@ -520,7 +524,7 @@ static void __init mxc_board_init(void) | |||
| 520 | spi_register_board_info(moboard_spi_board_info, | 524 | spi_register_board_info(moboard_spi_board_info, |
| 521 | ARRAY_SIZE(moboard_spi_board_info)); | 525 | ARRAY_SIZE(moboard_spi_board_info)); |
| 522 | 526 | ||
| 523 | mxc_register_device(&mxcsdhc_device0, &sdhc1_pdata); | 527 | imx31_add_mxc_mmc(0, &sdhc1_pdata); |
| 524 | 528 | ||
| 525 | mxc_register_device(&mx3_ipu, &mx3_ipu_data); | 529 | mxc_register_device(&mx3_ipu, &mx3_ipu_data); |
| 526 | if (!mx31moboard_cam_alloc_dma(CAMERA_BUF_SIZE)) | 530 | if (!mx31moboard_cam_alloc_dma(CAMERA_BUF_SIZE)) |
diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-mx3/mach-mx35_3ds.c index b66a75aa2e88..b1963f257c20 100644 --- a/arch/arm/mach-mx3/mach-mx35_3ds.c +++ b/arch/arm/mach-mx3/mach-mx35_3ds.c | |||
| @@ -26,7 +26,7 @@ | |||
| 26 | #include <linux/platform_device.h> | 26 | #include <linux/platform_device.h> |
| 27 | #include <linux/memory.h> | 27 | #include <linux/memory.h> |
| 28 | #include <linux/gpio.h> | 28 | #include <linux/gpio.h> |
| 29 | #include <linux/fsl_devices.h> | 29 | #include <linux/usb/otg.h> |
| 30 | 30 | ||
| 31 | #include <linux/mtd/physmap.h> | 31 | #include <linux/mtd/physmap.h> |
| 32 | 32 | ||
| @@ -40,7 +40,6 @@ | |||
| 40 | #include <mach/iomux-mx35.h> | 40 | #include <mach/iomux-mx35.h> |
| 41 | #include <mach/irqs.h> | 41 | #include <mach/irqs.h> |
| 42 | #include <mach/3ds_debugboard.h> | 42 | #include <mach/3ds_debugboard.h> |
| 43 | #include <mach/mxc_ehci.h> | ||
| 44 | 43 | ||
| 45 | #include "devices-imx35.h" | 44 | #include "devices-imx35.h" |
| 46 | #include "devices.h" | 45 | #include "devices.h" |
| @@ -81,7 +80,7 @@ static struct platform_device *devices[] __initdata = { | |||
| 81 | &mx35pdk_flash, | 80 | &mx35pdk_flash, |
| 82 | }; | 81 | }; |
| 83 | 82 | ||
| 84 | static struct pad_desc mx35pdk_pads[] = { | 83 | static iomux_v3_cfg_t mx35pdk_pads[] = { |
| 85 | /* UART1 */ | 84 | /* UART1 */ |
| 86 | MX35_PAD_CTS1__UART1_CTS, | 85 | MX35_PAD_CTS1__UART1_CTS, |
| 87 | MX35_PAD_RTS1__UART1_RTS, | 86 | MX35_PAD_RTS1__UART1_RTS, |
| @@ -122,18 +121,38 @@ static struct pad_desc mx35pdk_pads[] = { | |||
| 122 | }; | 121 | }; |
| 123 | 122 | ||
| 124 | /* OTG config */ | 123 | /* OTG config */ |
| 125 | static struct fsl_usb2_platform_data usb_otg_pdata = { | 124 | static const struct fsl_usb2_platform_data usb_otg_pdata __initconst = { |
| 126 | .operating_mode = FSL_USB2_DR_DEVICE, | 125 | .operating_mode = FSL_USB2_DR_DEVICE, |
| 127 | .phy_mode = FSL_USB2_PHY_UTMI_WIDE, | 126 | .phy_mode = FSL_USB2_PHY_UTMI_WIDE, |
| 128 | }; | 127 | }; |
| 129 | 128 | ||
| 129 | static struct mxc_usbh_platform_data otg_pdata __initdata = { | ||
| 130 | .portsc = MXC_EHCI_MODE_UTMI, | ||
| 131 | .flags = MXC_EHCI_INTERNAL_PHY, | ||
| 132 | }; | ||
| 133 | |||
| 130 | /* USB HOST config */ | 134 | /* USB HOST config */ |
| 131 | static struct mxc_usbh_platform_data usb_host_pdata = { | 135 | static const struct mxc_usbh_platform_data usb_host_pdata __initconst = { |
| 132 | .portsc = MXC_EHCI_MODE_SERIAL, | 136 | .portsc = MXC_EHCI_MODE_SERIAL, |
| 133 | .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | | 137 | .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | |
| 134 | MXC_EHCI_INTERNAL_PHY, | 138 | MXC_EHCI_INTERNAL_PHY, |
| 135 | }; | 139 | }; |
| 136 | 140 | ||
| 141 | static int otg_mode_host; | ||
| 142 | |||
| 143 | static int __init mx35_3ds_otg_mode(char *options) | ||
| 144 | { | ||
| 145 | if (!strcmp(options, "host")) | ||
| 146 | otg_mode_host = 1; | ||
| 147 | else if (!strcmp(options, "device")) | ||
| 148 | otg_mode_host = 0; | ||
| 149 | else | ||
| 150 | pr_info("otg_mode neither \"host\" nor \"device\". " | ||
| 151 | "Defaulting to device\n"); | ||
| 152 | return 0; | ||
| 153 | } | ||
| 154 | __setup("otg_mode=", mx35_3ds_otg_mode); | ||
| 155 | |||
| 137 | /* | 156 | /* |
| 138 | * Board specific initialization. | 157 | * Board specific initialization. |
| 139 | */ | 158 | */ |
| @@ -142,16 +161,21 @@ static void __init mxc_board_init(void) | |||
| 142 | mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads)); | 161 | mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads)); |
| 143 | 162 | ||
| 144 | imx35_add_fec(NULL); | 163 | imx35_add_fec(NULL); |
| 164 | imx35_add_imx2_wdt(NULL); | ||
| 145 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 165 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 146 | 166 | ||
| 147 | imx35_add_imx_uart0(&uart_pdata); | 167 | imx35_add_imx_uart0(&uart_pdata); |
| 148 | 168 | ||
| 149 | mxc_register_device(&mxc_otg_udc_device, &usb_otg_pdata); | 169 | if (otg_mode_host) |
| 170 | imx35_add_mxc_ehci_otg(&otg_pdata); | ||
| 171 | |||
| 172 | imx35_add_mxc_ehci_hs(&usb_host_pdata); | ||
| 150 | 173 | ||
| 151 | mxc_register_device(&mxc_usbh1, &usb_host_pdata); | 174 | if (!otg_mode_host) |
| 175 | imx35_add_fsl_usb2_udc(&usb_otg_pdata); | ||
| 152 | 176 | ||
| 153 | imx35_add_mxc_nand(&mx35pdk_nand_board_info); | 177 | imx35_add_mxc_nand(&mx35pdk_nand_board_info); |
| 154 | imx35_add_esdhc(0, NULL); | 178 | imx35_add_sdhci_esdhc_imx(0, NULL); |
| 155 | 179 | ||
| 156 | if (mxc_expio_init(MX35_CS5_BASE_ADDR, EXPIO_PARENT_INT)) | 180 | if (mxc_expio_init(MX35_CS5_BASE_ADDR, EXPIO_PARENT_INT)) |
| 157 | pr_warn("Init of the debugboard failed, all " | 181 | pr_warn("Init of the debugboard failed, all " |
diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c index 2ff3f661a48e..b752f6bc20a2 100644 --- a/arch/arm/mach-mx3/mach-pcm037.c +++ b/arch/arm/mach-mx3/mach-pcm037.c | |||
| @@ -27,7 +27,6 @@ | |||
| 27 | #include <linux/delay.h> | 27 | #include <linux/delay.h> |
| 28 | #include <linux/spi/spi.h> | 28 | #include <linux/spi/spi.h> |
| 29 | #include <linux/irq.h> | 29 | #include <linux/irq.h> |
| 30 | #include <linux/fsl_devices.h> | ||
| 31 | #include <linux/can/platform/sja1000.h> | 30 | #include <linux/can/platform/sja1000.h> |
| 32 | #include <linux/usb/otg.h> | 31 | #include <linux/usb/otg.h> |
| 33 | #include <linux/usb/ulpi.h> | 32 | #include <linux/usb/ulpi.h> |
| @@ -43,10 +42,8 @@ | |||
| 43 | #include <mach/hardware.h> | 42 | #include <mach/hardware.h> |
| 44 | #include <mach/iomux-mx3.h> | 43 | #include <mach/iomux-mx3.h> |
| 45 | #include <mach/ipu.h> | 44 | #include <mach/ipu.h> |
| 46 | #include <mach/mmc.h> | ||
| 47 | #include <mach/mx3_camera.h> | 45 | #include <mach/mx3_camera.h> |
| 48 | #include <mach/mx3fb.h> | 46 | #include <mach/mx3fb.h> |
| 49 | #include <mach/mxc_ehci.h> | ||
| 50 | #include <mach/ulpi.h> | 47 | #include <mach/ulpi.h> |
| 51 | 48 | ||
| 52 | #include "devices-imx31.h" | 49 | #include "devices-imx31.h" |
| @@ -399,7 +396,7 @@ static void pcm970_sdhc1_exit(struct device *dev, void *data) | |||
| 399 | gpio_free(SDHC1_GPIO_WP); | 396 | gpio_free(SDHC1_GPIO_WP); |
| 400 | } | 397 | } |
| 401 | 398 | ||
| 402 | static struct imxmmc_platform_data sdhc_pdata = { | 399 | static const struct imxmmc_platform_data sdhc_pdata __initconst = { |
| 403 | #ifdef PCM970_SDHC_RW_SWITCH | 400 | #ifdef PCM970_SDHC_RW_SWITCH |
| 404 | .get_ro = pcm970_sdhc1_get_ro, | 401 | .get_ro = pcm970_sdhc1_get_ro, |
| 405 | #endif | 402 | #endif |
| @@ -441,7 +438,6 @@ static int __init pcm037_camera_alloc_dma(const size_t buf_size) | |||
| 441 | static struct platform_device *devices[] __initdata = { | 438 | static struct platform_device *devices[] __initdata = { |
| 442 | &pcm037_flash, | 439 | &pcm037_flash, |
| 443 | &pcm037_sram_device, | 440 | &pcm037_sram_device, |
| 444 | &imx_wdt_device0, | ||
| 445 | &pcm037_mt9t031, | 441 | &pcm037_mt9t031, |
| 446 | &pcm037_mt9v022, | 442 | &pcm037_mt9v022, |
| 447 | }; | 443 | }; |
| @@ -538,18 +534,18 @@ static struct platform_device pcm970_sja1000 = { | |||
| 538 | }; | 534 | }; |
| 539 | 535 | ||
| 540 | #if defined(CONFIG_USB_ULPI) | 536 | #if defined(CONFIG_USB_ULPI) |
| 541 | static struct mxc_usbh_platform_data otg_pdata = { | 537 | static struct mxc_usbh_platform_data otg_pdata __initdata = { |
| 542 | .portsc = MXC_EHCI_MODE_ULPI, | 538 | .portsc = MXC_EHCI_MODE_ULPI, |
| 543 | .flags = MXC_EHCI_INTERFACE_DIFF_UNI, | 539 | .flags = MXC_EHCI_INTERFACE_DIFF_UNI, |
| 544 | }; | 540 | }; |
| 545 | 541 | ||
| 546 | static struct mxc_usbh_platform_data usbh2_pdata = { | 542 | static struct mxc_usbh_platform_data usbh2_pdata __initdata = { |
| 547 | .portsc = MXC_EHCI_MODE_ULPI, | 543 | .portsc = MXC_EHCI_MODE_ULPI, |
| 548 | .flags = MXC_EHCI_INTERFACE_DIFF_UNI, | 544 | .flags = MXC_EHCI_INTERFACE_DIFF_UNI, |
| 549 | }; | 545 | }; |
| 550 | #endif | 546 | #endif |
| 551 | 547 | ||
| 552 | static struct fsl_usb2_platform_data otg_device_pdata = { | 548 | static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { |
| 553 | .operating_mode = FSL_USB2_DR_DEVICE, | 549 | .operating_mode = FSL_USB2_DR_DEVICE, |
| 554 | .phy_mode = FSL_USB2_PHY_ULPI, | 550 | .phy_mode = FSL_USB2_PHY_ULPI, |
| 555 | }; | 551 | }; |
| @@ -607,12 +603,13 @@ static void __init mxc_board_init(void) | |||
| 607 | 603 | ||
| 608 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 604 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 609 | 605 | ||
| 606 | imx31_add_imx2_wdt(NULL); | ||
| 610 | imx31_add_imx_uart0(&uart_pdata); | 607 | imx31_add_imx_uart0(&uart_pdata); |
| 611 | /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */ | 608 | /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */ |
| 612 | imx31_add_imx_uart1(&uart_pdata); | 609 | imx31_add_imx_uart1(&uart_pdata); |
| 613 | imx31_add_imx_uart2(&uart_pdata); | 610 | imx31_add_imx_uart2(&uart_pdata); |
| 614 | 611 | ||
| 615 | mxc_register_device(&mxc_w1_master_device, NULL); | 612 | imx31_add_mxc_w1(NULL); |
| 616 | 613 | ||
| 617 | /* LAN9217 IRQ pin */ | 614 | /* LAN9217 IRQ pin */ |
| 618 | ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq"); | 615 | ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq"); |
| @@ -632,7 +629,7 @@ static void __init mxc_board_init(void) | |||
| 632 | imx31_add_imx_i2c2(&pcm037_i2c2_data); | 629 | imx31_add_imx_i2c2(&pcm037_i2c2_data); |
| 633 | 630 | ||
| 634 | imx31_add_mxc_nand(&pcm037_nand_board_info); | 631 | imx31_add_mxc_nand(&pcm037_nand_board_info); |
| 635 | mxc_register_device(&mxcsdhc_device0, &sdhc_pdata); | 632 | imx31_add_mxc_mmc(0, &sdhc_pdata); |
| 636 | mxc_register_device(&mx3_ipu, &mx3_ipu_data); | 633 | mxc_register_device(&mx3_ipu, &mx3_ipu_data); |
| 637 | mxc_register_device(&mx3_fb, &mx3fb_pdata); | 634 | mxc_register_device(&mx3_fb, &mx3fb_pdata); |
| 638 | 635 | ||
| @@ -654,16 +651,16 @@ static void __init mxc_board_init(void) | |||
| 654 | otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, | 651 | otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, |
| 655 | ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); | 652 | ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); |
| 656 | 653 | ||
| 657 | mxc_register_device(&mxc_otg_host, &otg_pdata); | 654 | imx31_add_mxc_ehci_otg(&otg_pdata); |
| 658 | } | 655 | } |
| 659 | 656 | ||
| 660 | usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, | 657 | usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, |
| 661 | ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); | 658 | ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); |
| 662 | 659 | ||
| 663 | mxc_register_device(&mxc_usbh2, &usbh2_pdata); | 660 | imx31_add_mxc_ehci_hs(2, &usbh2_pdata); |
| 664 | #endif | 661 | #endif |
| 665 | if (!otg_mode_host) | 662 | if (!otg_mode_host) |
| 666 | mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); | 663 | imx31_add_fsl_usb2_udc(&otg_device_pdata); |
| 667 | 664 | ||
| 668 | } | 665 | } |
| 669 | 666 | ||
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c index 4e1de87995d4..bcf83fc7e701 100644 --- a/arch/arm/mach-mx3/mach-pcm043.c +++ b/arch/arm/mach-mx3/mach-pcm043.c | |||
| @@ -27,7 +27,6 @@ | |||
| 27 | #include <linux/i2c/at24.h> | 27 | #include <linux/i2c/at24.h> |
| 28 | #include <linux/usb/otg.h> | 28 | #include <linux/usb/otg.h> |
| 29 | #include <linux/usb/ulpi.h> | 29 | #include <linux/usb/ulpi.h> |
| 30 | #include <linux/fsl_devices.h> | ||
| 31 | 30 | ||
| 32 | #include <asm/mach-types.h> | 31 | #include <asm/mach-types.h> |
| 33 | #include <asm/mach/arch.h> | 32 | #include <asm/mach/arch.h> |
| @@ -39,7 +38,6 @@ | |||
| 39 | #include <mach/iomux-mx35.h> | 38 | #include <mach/iomux-mx35.h> |
| 40 | #include <mach/ipu.h> | 39 | #include <mach/ipu.h> |
| 41 | #include <mach/mx3fb.h> | 40 | #include <mach/mx3fb.h> |
| 42 | #include <mach/mxc_ehci.h> | ||
| 43 | #include <mach/ulpi.h> | 41 | #include <mach/ulpi.h> |
| 44 | #include <mach/audmux.h> | 42 | #include <mach/audmux.h> |
| 45 | 43 | ||
| @@ -140,10 +138,9 @@ static struct i2c_board_info pcm043_i2c_devices[] = { | |||
| 140 | 138 | ||
| 141 | static struct platform_device *devices[] __initdata = { | 139 | static struct platform_device *devices[] __initdata = { |
| 142 | &pcm043_flash, | 140 | &pcm043_flash, |
| 143 | &imx_wdt_device0, | ||
| 144 | }; | 141 | }; |
| 145 | 142 | ||
| 146 | static struct pad_desc pcm043_pads[] = { | 143 | static iomux_v3_cfg_t pcm043_pads[] = { |
| 147 | /* UART1 */ | 144 | /* UART1 */ |
| 148 | MX35_PAD_CTS1__UART1_CTS, | 145 | MX35_PAD_CTS1__UART1_CTS, |
| 149 | MX35_PAD_RTS1__UART1_RTS, | 146 | MX35_PAD_RTS1__UART1_RTS, |
| @@ -230,8 +227,8 @@ static struct pad_desc pcm043_pads[] = { | |||
| 230 | 227 | ||
| 231 | static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) | 228 | static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) |
| 232 | { | 229 | { |
| 233 | struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; | 230 | iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; |
| 234 | struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; | 231 | iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; |
| 235 | int ret; | 232 | int ret; |
| 236 | 233 | ||
| 237 | ret = gpio_request(AC97_GPIO_TXFS, "SSI"); | 234 | ret = gpio_request(AC97_GPIO_TXFS, "SSI"); |
| @@ -240,7 +237,7 @@ static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) | |||
| 240 | return; | 237 | return; |
| 241 | } | 238 | } |
| 242 | 239 | ||
| 243 | mxc_iomux_v3_setup_pad(&txfs_gpio); | 240 | mxc_iomux_v3_setup_pad(txfs_gpio); |
| 244 | 241 | ||
| 245 | /* warm reset */ | 242 | /* warm reset */ |
| 246 | gpio_direction_output(AC97_GPIO_TXFS, 1); | 243 | gpio_direction_output(AC97_GPIO_TXFS, 1); |
| @@ -248,16 +245,16 @@ static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) | |||
| 248 | gpio_set_value(AC97_GPIO_TXFS, 0); | 245 | gpio_set_value(AC97_GPIO_TXFS, 0); |
| 249 | 246 | ||
| 250 | gpio_free(AC97_GPIO_TXFS); | 247 | gpio_free(AC97_GPIO_TXFS); |
| 251 | mxc_iomux_v3_setup_pad(&txfs); | 248 | mxc_iomux_v3_setup_pad(txfs); |
| 252 | } | 249 | } |
| 253 | 250 | ||
| 254 | static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97) | 251 | static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97) |
| 255 | { | 252 | { |
| 256 | struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; | 253 | iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; |
| 257 | struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; | 254 | iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; |
| 258 | struct pad_desc txd_gpio = MX35_PAD_STXD4__GPIO2_28; | 255 | iomux_v3_cfg_t txd_gpio = MX35_PAD_STXD4__GPIO2_28; |
| 259 | struct pad_desc txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD; | 256 | iomux_v3_cfg_t txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD; |
| 260 | struct pad_desc reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0; | 257 | iomux_v3_cfg_t reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0; |
| 261 | int ret; | 258 | int ret; |
| 262 | 259 | ||
| 263 | ret = gpio_request(AC97_GPIO_TXFS, "SSI"); | 260 | ret = gpio_request(AC97_GPIO_TXFS, "SSI"); |
| @@ -272,9 +269,9 @@ static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97) | |||
| 272 | if (ret) | 269 | if (ret) |
| 273 | goto err3; | 270 | goto err3; |
| 274 | 271 | ||
| 275 | mxc_iomux_v3_setup_pad(&txfs_gpio); | 272 | mxc_iomux_v3_setup_pad(txfs_gpio); |
| 276 | mxc_iomux_v3_setup_pad(&txd_gpio); | 273 | mxc_iomux_v3_setup_pad(txd_gpio); |
| 277 | mxc_iomux_v3_setup_pad(&reset_gpio); | 274 | mxc_iomux_v3_setup_pad(reset_gpio); |
| 278 | 275 | ||
| 279 | gpio_direction_output(AC97_GPIO_TXFS, 0); | 276 | gpio_direction_output(AC97_GPIO_TXFS, 0); |
| 280 | gpio_direction_output(AC97_GPIO_TXD, 0); | 277 | gpio_direction_output(AC97_GPIO_TXD, 0); |
| @@ -284,8 +281,8 @@ static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97) | |||
| 284 | udelay(10); | 281 | udelay(10); |
| 285 | gpio_direction_output(AC97_GPIO_RESET, 1); | 282 | gpio_direction_output(AC97_GPIO_RESET, 1); |
| 286 | 283 | ||
| 287 | mxc_iomux_v3_setup_pad(&txd); | 284 | mxc_iomux_v3_setup_pad(txd); |
| 288 | mxc_iomux_v3_setup_pad(&txfs); | 285 | mxc_iomux_v3_setup_pad(txfs); |
| 289 | 286 | ||
| 290 | gpio_free(AC97_GPIO_RESET); | 287 | gpio_free(AC97_GPIO_RESET); |
| 291 | err3: | 288 | err3: |
| @@ -311,19 +308,19 @@ pcm037_nand_board_info __initconst = { | |||
| 311 | }; | 308 | }; |
| 312 | 309 | ||
| 313 | #if defined(CONFIG_USB_ULPI) | 310 | #if defined(CONFIG_USB_ULPI) |
| 314 | static struct mxc_usbh_platform_data otg_pdata = { | 311 | static struct mxc_usbh_platform_data otg_pdata __initdata = { |
| 315 | .portsc = MXC_EHCI_MODE_UTMI, | 312 | .portsc = MXC_EHCI_MODE_UTMI, |
| 316 | .flags = MXC_EHCI_INTERFACE_DIFF_UNI, | 313 | .flags = MXC_EHCI_INTERFACE_DIFF_UNI, |
| 317 | }; | 314 | }; |
| 318 | 315 | ||
| 319 | static struct mxc_usbh_platform_data usbh1_pdata = { | 316 | static const struct mxc_usbh_platform_data usbh1_pdata __initconst = { |
| 320 | .portsc = MXC_EHCI_MODE_SERIAL, | 317 | .portsc = MXC_EHCI_MODE_SERIAL, |
| 321 | .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | | 318 | .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | |
| 322 | MXC_EHCI_IPPUE_DOWN, | 319 | MXC_EHCI_IPPUE_DOWN, |
| 323 | }; | 320 | }; |
| 324 | #endif | 321 | #endif |
| 325 | 322 | ||
| 326 | static struct fsl_usb2_platform_data otg_device_pdata = { | 323 | static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { |
| 327 | .operating_mode = FSL_USB2_DR_DEVICE, | 324 | .operating_mode = FSL_USB2_DR_DEVICE, |
| 328 | .phy_mode = FSL_USB2_PHY_UTMI, | 325 | .phy_mode = FSL_USB2_PHY_UTMI, |
| 329 | }; | 326 | }; |
| @@ -364,6 +361,7 @@ static void __init mxc_board_init(void) | |||
| 364 | 361 | ||
| 365 | imx35_add_fec(NULL); | 362 | imx35_add_fec(NULL); |
| 366 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 363 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 364 | imx35_add_imx2_wdt(NULL); | ||
| 367 | 365 | ||
| 368 | imx35_add_imx_uart0(&uart_pdata); | 366 | imx35_add_imx_uart0(&uart_pdata); |
| 369 | imx35_add_mxc_nand(&pcm037_nand_board_info); | 367 | imx35_add_mxc_nand(&pcm037_nand_board_info); |
| @@ -386,16 +384,16 @@ static void __init mxc_board_init(void) | |||
| 386 | otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, | 384 | otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, |
| 387 | ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); | 385 | ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); |
| 388 | 386 | ||
| 389 | mxc_register_device(&mxc_otg_host, &otg_pdata); | 387 | imx35_add_mxc_ehci_otg(&otg_pdata); |
| 390 | } | 388 | } |
| 391 | 389 | ||
| 392 | mxc_register_device(&mxc_usbh1, &usbh1_pdata); | 390 | imx35_add_mxc_ehci_hs(&usbh1_pdata); |
| 393 | #endif | 391 | #endif |
| 394 | if (!otg_mode_host) | 392 | if (!otg_mode_host) |
| 395 | mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); | 393 | imx35_add_fsl_usb2_udc(&otg_device_pdata); |
| 396 | 394 | ||
| 397 | imx35_add_flexcan1(NULL); | 395 | imx35_add_flexcan1(NULL); |
| 398 | imx35_add_esdhc(0, NULL); | 396 | imx35_add_sdhci_esdhc_imx(0, NULL); |
| 399 | } | 397 | } |
| 400 | 398 | ||
| 401 | static void __init pcm043_timer_init(void) | 399 | static void __init pcm043_timer_init(void) |
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c index b4ffc531a82c..47118f760244 100644 --- a/arch/arm/mach-mx3/mm.c +++ b/arch/arm/mach-mx3/mm.c | |||
| @@ -36,40 +36,16 @@ | |||
| 36 | * @ingroup Memory | 36 | * @ingroup Memory |
| 37 | */ | 37 | */ |
| 38 | 38 | ||
| 39 | /*! | 39 | #ifdef CONFIG_SOC_IMX31 |
| 40 | * This table defines static virtual address mappings for I/O regions. | 40 | static struct map_desc mx31_io_desc[] __initdata = { |
| 41 | * These are the mappings common across all MX3 boards. | 41 | imx_map_entry(MX31, X_MEMC, MT_DEVICE), |
| 42 | */ | 42 | imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED), |
| 43 | static struct map_desc mxc_io_desc[] __initdata = { | 43 | imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED), |
| 44 | { | 44 | imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED), |
| 45 | .virtual = X_MEMC_BASE_ADDR_VIRT, | 45 | imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED), |
| 46 | .pfn = __phys_to_pfn(X_MEMC_BASE_ADDR), | ||
| 47 | .length = X_MEMC_SIZE, | ||
| 48 | .type = MT_DEVICE | ||
| 49 | }, { | ||
| 50 | .virtual = AVIC_BASE_ADDR_VIRT, | ||
| 51 | .pfn = __phys_to_pfn(AVIC_BASE_ADDR), | ||
| 52 | .length = AVIC_SIZE, | ||
| 53 | .type = MT_DEVICE_NONSHARED | ||
| 54 | }, { | ||
| 55 | .virtual = AIPS1_BASE_ADDR_VIRT, | ||
| 56 | .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), | ||
| 57 | .length = AIPS1_SIZE, | ||
| 58 | .type = MT_DEVICE_NONSHARED | ||
| 59 | }, { | ||
| 60 | .virtual = AIPS2_BASE_ADDR_VIRT, | ||
| 61 | .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), | ||
| 62 | .length = AIPS2_SIZE, | ||
| 63 | .type = MT_DEVICE_NONSHARED | ||
| 64 | }, { | ||
| 65 | .virtual = SPBA0_BASE_ADDR_VIRT, | ||
| 66 | .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), | ||
| 67 | .length = SPBA0_SIZE, | ||
| 68 | .type = MT_DEVICE_NONSHARED | ||
| 69 | }, | ||
| 70 | }; | 46 | }; |
| 71 | 47 | ||
| 72 | /*! | 48 | /* |
| 73 | * This function initializes the memory map. It is called during the | 49 | * This function initializes the memory map. It is called during the |
| 74 | * system startup to create static physical to virtual memory mappings | 50 | * system startup to create static physical to virtual memory mappings |
| 75 | * for the IO modules. | 51 | * for the IO modules. |
| @@ -77,34 +53,44 @@ static struct map_desc mxc_io_desc[] __initdata = { | |||
| 77 | void __init mx31_map_io(void) | 53 | void __init mx31_map_io(void) |
| 78 | { | 54 | { |
| 79 | mxc_set_cpu_type(MXC_CPU_MX31); | 55 | mxc_set_cpu_type(MXC_CPU_MX31); |
| 80 | mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR)); | 56 | mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); |
| 81 | 57 | ||
| 82 | iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); | 58 | iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc)); |
| 83 | } | 59 | } |
| 84 | 60 | ||
| 85 | #ifdef CONFIG_ARCH_MX35 | 61 | int imx31_register_gpios(void); |
| 86 | void __init mx35_map_io(void) | 62 | void __init mx31_init_irq(void) |
| 87 | { | 63 | { |
| 88 | mxc_set_cpu_type(MXC_CPU_MX35); | 64 | mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR)); |
| 89 | mxc_iomux_v3_init(IO_ADDRESS(IOMUXC_BASE_ADDR)); | 65 | imx31_register_gpios(); |
| 90 | mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR)); | ||
| 91 | |||
| 92 | iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); | ||
| 93 | } | 66 | } |
| 94 | #endif | 67 | #endif /* ifdef CONFIG_SOC_IMX31 */ |
| 95 | 68 | ||
| 96 | int imx3x_register_gpios(void); | 69 | #ifdef CONFIG_SOC_IMX35 |
| 70 | static struct map_desc mx35_io_desc[] __initdata = { | ||
| 71 | imx_map_entry(MX35, X_MEMC, MT_DEVICE), | ||
| 72 | imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED), | ||
| 73 | imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED), | ||
| 74 | imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED), | ||
| 75 | imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED), | ||
| 76 | }; | ||
| 97 | 77 | ||
| 98 | void __init mx31_init_irq(void) | 78 | void __init mx35_map_io(void) |
| 99 | { | 79 | { |
| 100 | mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR)); | 80 | mxc_set_cpu_type(MXC_CPU_MX35); |
| 101 | imx3x_register_gpios(); | 81 | mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR)); |
| 82 | mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR)); | ||
| 83 | |||
| 84 | iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc)); | ||
| 102 | } | 85 | } |
| 103 | 86 | ||
| 87 | int imx35_register_gpios(void); | ||
| 104 | void __init mx35_init_irq(void) | 88 | void __init mx35_init_irq(void) |
| 105 | { | 89 | { |
| 106 | mx31_init_irq(); | 90 | mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR)); |
| 91 | imx35_register_gpios(); | ||
| 107 | } | 92 | } |
| 93 | #endif /* ifdef CONFIG_SOC_IMX35 */ | ||
| 108 | 94 | ||
| 109 | #ifdef CONFIG_CACHE_L2X0 | 95 | #ifdef CONFIG_CACHE_L2X0 |
| 110 | static int mxc_init_l2x0(void) | 96 | static int mxc_init_l2x0(void) |
| @@ -129,7 +115,7 @@ static int mxc_init_l2x0(void) | |||
| 129 | pr_err("L2 cache: Cannot fix timing. Trying to continue without\n"); | 115 | pr_err("L2 cache: Cannot fix timing. Trying to continue without\n"); |
| 130 | } | 116 | } |
| 131 | 117 | ||
| 132 | l2x0_base = ioremap(L2CC_BASE_ADDR, 4096); | 118 | l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096); |
| 133 | if (IS_ERR(l2x0_base)) { | 119 | if (IS_ERR(l2x0_base)) { |
| 134 | printk(KERN_ERR "remapping L2 cache area failed with %ld\n", | 120 | printk(KERN_ERR "remapping L2 cache area failed with %ld\n", |
| 135 | PTR_ERR(l2x0_base)); | 121 | PTR_ERR(l2x0_base)); |
diff --git a/arch/arm/mach-mx3/mx31lilly-db.c b/arch/arm/mach-mx3/mx31lilly-db.c index 827fd3c80201..8f1a38ebf5c8 100644 --- a/arch/arm/mach-mx3/mx31lilly-db.c +++ b/arch/arm/mach-mx3/mx31lilly-db.c | |||
| @@ -34,7 +34,6 @@ | |||
| 34 | #include <mach/common.h> | 34 | #include <mach/common.h> |
| 35 | #include <mach/iomux-mx3.h> | 35 | #include <mach/iomux-mx3.h> |
| 36 | #include <mach/board-mx31lilly.h> | 36 | #include <mach/board-mx31lilly.h> |
| 37 | #include <mach/mmc.h> | ||
| 38 | #include <mach/mx3fb.h> | 37 | #include <mach/mx3fb.h> |
| 39 | #include <mach/ipu.h> | 38 | #include <mach/ipu.h> |
| 40 | 39 | ||
| @@ -158,7 +157,7 @@ static void mxc_mmc1_exit(struct device *dev, void *data) | |||
| 158 | free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), data); | 157 | free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), data); |
| 159 | } | 158 | } |
| 160 | 159 | ||
| 161 | static struct imxmmc_platform_data mmc_pdata = { | 160 | static const struct imxmmc_platform_data mmc_pdata __initconst = { |
| 162 | .get_ro = mxc_mmc1_get_ro, | 161 | .get_ro = mxc_mmc1_get_ro, |
| 163 | .init = mxc_mmc1_init, | 162 | .init = mxc_mmc1_init, |
| 164 | .exit = mxc_mmc1_exit, | 163 | .exit = mxc_mmc1_exit, |
| @@ -216,7 +215,7 @@ void __init mx31lilly_db_init(void) | |||
| 216 | imx31_add_imx_uart0(&uart_pdata); | 215 | imx31_add_imx_uart0(&uart_pdata); |
| 217 | imx31_add_imx_uart1(&uart_pdata); | 216 | imx31_add_imx_uart1(&uart_pdata); |
| 218 | imx31_add_imx_uart2(&uart_pdata); | 217 | imx31_add_imx_uart2(&uart_pdata); |
| 219 | mxc_register_device(&mxcsdhc_device0, &mmc_pdata); | 218 | imx31_add_mxc_mmc(0, &mmc_pdata); |
| 220 | mx31lilly_init_fb(); | 219 | mx31lilly_init_fb(); |
| 221 | } | 220 | } |
| 222 | 221 | ||
diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c index 7b0e74e275ba..3124ea837ac7 100644 --- a/arch/arm/mach-mx3/mx31lite-db.c +++ b/arch/arm/mach-mx3/mx31lite-db.c | |||
| @@ -35,7 +35,6 @@ | |||
| 35 | #include <mach/common.h> | 35 | #include <mach/common.h> |
| 36 | #include <mach/iomux-mx3.h> | 36 | #include <mach/iomux-mx3.h> |
| 37 | #include <mach/board-mx31lite.h> | 37 | #include <mach/board-mx31lite.h> |
| 38 | #include <mach/mmc.h> | ||
| 39 | 38 | ||
| 40 | #include "devices-imx31.h" | 39 | #include "devices-imx31.h" |
| 41 | #include "devices.h" | 40 | #include "devices.h" |
| @@ -142,7 +141,7 @@ static void mxc_mmc1_exit(struct device *dev, void *data) | |||
| 142 | free_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), data); | 141 | free_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), data); |
| 143 | } | 142 | } |
| 144 | 143 | ||
| 145 | static struct imxmmc_platform_data mmc_pdata = { | 144 | static const struct imxmmc_platform_data mmc_pdata __initconst = { |
| 146 | .get_ro = mxc_mmc1_get_ro, | 145 | .get_ro = mxc_mmc1_get_ro, |
| 147 | .init = mxc_mmc1_init, | 146 | .init = mxc_mmc1_init, |
| 148 | .exit = mxc_mmc1_exit, | 147 | .exit = mxc_mmc1_exit, |
| @@ -197,10 +196,9 @@ void __init mx31lite_db_init(void) | |||
| 197 | ARRAY_SIZE(litekit_db_board_pins), | 196 | ARRAY_SIZE(litekit_db_board_pins), |
| 198 | "development board pins"); | 197 | "development board pins"); |
| 199 | imx31_add_imx_uart0(&uart_pdata); | 198 | imx31_add_imx_uart0(&uart_pdata); |
| 200 | mxc_register_device(&mxcsdhc_device0, &mmc_pdata); | 199 | imx31_add_mxc_mmc(0, &mmc_pdata); |
| 201 | imx31_add_spi_imx0(&spi0_pdata); | 200 | imx31_add_spi_imx0(&spi0_pdata); |
| 202 | platform_device_register(&litekit_led_device); | 201 | platform_device_register(&litekit_led_device); |
| 203 | mxc_register_device(&imx_wdt_device0, NULL); | 202 | imx31_add_imx2_wdt(NULL); |
| 204 | mxc_register_device(&imx_rtc_device0, NULL); | 203 | mxc_register_device(&imx_rtc_device0, NULL); |
| 205 | } | 204 | } |
| 206 | |||
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c index fc395a7a8599..94a0b9e4b7f3 100644 --- a/arch/arm/mach-mx3/mx31moboard-devboard.c +++ b/arch/arm/mach-mx3/mx31moboard-devboard.c | |||
| @@ -18,15 +18,12 @@ | |||
| 18 | #include <linux/platform_device.h> | 18 | #include <linux/platform_device.h> |
| 19 | #include <linux/slab.h> | 19 | #include <linux/slab.h> |
| 20 | #include <linux/types.h> | 20 | #include <linux/types.h> |
| 21 | #include <linux/fsl_devices.h> | ||
| 22 | 21 | ||
| 23 | #include <linux/usb/otg.h> | 22 | #include <linux/usb/otg.h> |
| 24 | 23 | ||
| 25 | #include <mach/common.h> | 24 | #include <mach/common.h> |
| 26 | #include <mach/iomux-mx3.h> | 25 | #include <mach/iomux-mx3.h> |
| 27 | #include <mach/hardware.h> | 26 | #include <mach/hardware.h> |
| 28 | #include <mach/mmc.h> | ||
| 29 | #include <mach/mxc_ehci.h> | ||
| 30 | #include <mach/ulpi.h> | 27 | #include <mach/ulpi.h> |
| 31 | 28 | ||
| 32 | #include "devices-imx31.h" | 29 | #include "devices-imx31.h" |
| @@ -103,7 +100,7 @@ static void devboard_sdhc2_exit(struct device *dev, void *data) | |||
| 103 | gpio_free(SDHC2_CD); | 100 | gpio_free(SDHC2_CD); |
| 104 | } | 101 | } |
| 105 | 102 | ||
| 106 | static struct imxmmc_platform_data sdhc2_pdata = { | 103 | static const struct imxmmc_platform_data sdhc2_pdata __initconst = { |
| 107 | .get_ro = devboard_sdhc2_get_ro, | 104 | .get_ro = devboard_sdhc2_get_ro, |
| 108 | .init = devboard_sdhc2_init, | 105 | .init = devboard_sdhc2_init, |
| 109 | .exit = devboard_sdhc2_exit, | 106 | .exit = devboard_sdhc2_exit, |
| @@ -187,7 +184,7 @@ static int devboard_isp1105_set_vbus(struct otg_transceiver *otg, bool on) | |||
| 187 | return 0; | 184 | return 0; |
| 188 | } | 185 | } |
| 189 | 186 | ||
| 190 | static struct mxc_usbh_platform_data usbh1_pdata = { | 187 | static struct mxc_usbh_platform_data usbh1_pdata __initdata = { |
| 191 | .init = devboard_usbh1_hw_init, | 188 | .init = devboard_usbh1_hw_init, |
| 192 | .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, | 189 | .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, |
| 193 | .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI, | 190 | .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI, |
| @@ -196,6 +193,7 @@ static struct mxc_usbh_platform_data usbh1_pdata = { | |||
| 196 | static int __init devboard_usbh1_init(void) | 193 | static int __init devboard_usbh1_init(void) |
| 197 | { | 194 | { |
| 198 | struct otg_transceiver *otg; | 195 | struct otg_transceiver *otg; |
| 196 | struct platform_device *pdev; | ||
| 199 | 197 | ||
| 200 | otg = kzalloc(sizeof(*otg), GFP_KERNEL); | 198 | otg = kzalloc(sizeof(*otg), GFP_KERNEL); |
| 201 | if (!otg) | 199 | if (!otg) |
| @@ -207,11 +205,15 @@ static int __init devboard_usbh1_init(void) | |||
| 207 | 205 | ||
| 208 | usbh1_pdata.otg = otg; | 206 | usbh1_pdata.otg = otg; |
| 209 | 207 | ||
| 210 | return mxc_register_device(&mxc_usbh1, &usbh1_pdata); | 208 | pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata); |
| 209 | if (IS_ERR(pdev)) | ||
| 210 | return PTR_ERR(pdev); | ||
| 211 | |||
| 212 | return 0; | ||
| 211 | } | 213 | } |
| 212 | 214 | ||
| 213 | 215 | ||
| 214 | static struct fsl_usb2_platform_data usb_pdata = { | 216 | static const struct fsl_usb2_platform_data usb_pdata __initconst = { |
| 215 | .operating_mode = FSL_USB2_DR_DEVICE, | 217 | .operating_mode = FSL_USB2_DR_DEVICE, |
| 216 | .phy_mode = FSL_USB2_PHY_ULPI, | 218 | .phy_mode = FSL_USB2_PHY_ULPI, |
| 217 | }; | 219 | }; |
| @@ -228,11 +230,11 @@ void __init mx31moboard_devboard_init(void) | |||
| 228 | 230 | ||
| 229 | imx31_add_imx_uart1(&uart_pdata); | 231 | imx31_add_imx_uart1(&uart_pdata); |
| 230 | 232 | ||
| 231 | mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); | 233 | imx31_add_mxc_mmc(1, &sdhc2_pdata); |
| 232 | 234 | ||
| 233 | devboard_init_sel_gpios(); | 235 | devboard_init_sel_gpios(); |
| 234 | 236 | ||
| 235 | mxc_register_device(&mxc_otg_udc_device, &usb_pdata); | 237 | imx31_add_fsl_usb2_udc(&usb_pdata); |
| 236 | 238 | ||
| 237 | devboard_usbh1_init(); | 239 | devboard_usbh1_init(); |
| 238 | } | 240 | } |
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c index 18069cb7d068..f449a97ae1a2 100644 --- a/arch/arm/mach-mx3/mx31moboard-marxbot.c +++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c | |||
| @@ -21,7 +21,6 @@ | |||
| 21 | #include <linux/slab.h> | 21 | #include <linux/slab.h> |
| 22 | #include <linux/platform_device.h> | 22 | #include <linux/platform_device.h> |
| 23 | #include <linux/types.h> | 23 | #include <linux/types.h> |
| 24 | #include <linux/fsl_devices.h> | ||
| 25 | 24 | ||
| 26 | #include <linux/usb/otg.h> | 25 | #include <linux/usb/otg.h> |
| 27 | 26 | ||
| @@ -29,12 +28,11 @@ | |||
| 29 | #include <mach/hardware.h> | 28 | #include <mach/hardware.h> |
| 30 | #include <mach/imx-uart.h> | 29 | #include <mach/imx-uart.h> |
| 31 | #include <mach/iomux-mx3.h> | 30 | #include <mach/iomux-mx3.h> |
| 32 | #include <mach/mmc.h> | ||
| 33 | #include <mach/mxc_ehci.h> | ||
| 34 | #include <mach/ulpi.h> | 31 | #include <mach/ulpi.h> |
| 35 | 32 | ||
| 36 | #include <media/soc_camera.h> | 33 | #include <media/soc_camera.h> |
| 37 | 34 | ||
| 35 | #include "devices-imx31.h" | ||
| 38 | #include "devices.h" | 36 | #include "devices.h" |
| 39 | 37 | ||
| 40 | static unsigned int marxbot_pins[] = { | 38 | static unsigned int marxbot_pins[] = { |
| @@ -116,7 +114,7 @@ static void marxbot_sdhc2_exit(struct device *dev, void *data) | |||
| 116 | gpio_free(SDHC2_CD); | 114 | gpio_free(SDHC2_CD); |
| 117 | } | 115 | } |
| 118 | 116 | ||
| 119 | static struct imxmmc_platform_data sdhc2_pdata = { | 117 | static const struct imxmmc_platform_data sdhc2_pdata __initconst = { |
| 120 | .get_ro = marxbot_sdhc2_get_ro, | 118 | .get_ro = marxbot_sdhc2_get_ro, |
| 121 | .init = marxbot_sdhc2_init, | 119 | .init = marxbot_sdhc2_init, |
| 122 | .exit = marxbot_sdhc2_exit, | 120 | .exit = marxbot_sdhc2_exit, |
| @@ -302,7 +300,7 @@ static int marxbot_isp1105_set_vbus(struct otg_transceiver *otg, bool on) | |||
| 302 | return 0; | 300 | return 0; |
| 303 | } | 301 | } |
| 304 | 302 | ||
| 305 | static struct mxc_usbh_platform_data usbh1_pdata = { | 303 | static struct mxc_usbh_platform_data usbh1_pdata __initdata = { |
| 306 | .init = marxbot_usbh1_hw_init, | 304 | .init = marxbot_usbh1_hw_init, |
| 307 | .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, | 305 | .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, |
| 308 | .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI, | 306 | .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI, |
| @@ -311,6 +309,7 @@ static struct mxc_usbh_platform_data usbh1_pdata = { | |||
| 311 | static int __init marxbot_usbh1_init(void) | 309 | static int __init marxbot_usbh1_init(void) |
| 312 | { | 310 | { |
| 313 | struct otg_transceiver *otg; | 311 | struct otg_transceiver *otg; |
| 312 | struct platform_device *pdev; | ||
| 314 | 313 | ||
| 315 | otg = kzalloc(sizeof(*otg), GFP_KERNEL); | 314 | otg = kzalloc(sizeof(*otg), GFP_KERNEL); |
| 316 | if (!otg) | 315 | if (!otg) |
| @@ -322,10 +321,14 @@ static int __init marxbot_usbh1_init(void) | |||
| 322 | 321 | ||
| 323 | usbh1_pdata.otg = otg; | 322 | usbh1_pdata.otg = otg; |
| 324 | 323 | ||
| 325 | return mxc_register_device(&mxc_usbh1, &usbh1_pdata); | 324 | pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata); |
| 325 | if (IS_ERR(pdev)) | ||
| 326 | return PTR_ERR(pdev); | ||
| 327 | |||
| 328 | return 0; | ||
| 326 | } | 329 | } |
| 327 | 330 | ||
| 328 | static struct fsl_usb2_platform_data usb_pdata = { | 331 | static const struct fsl_usb2_platform_data usb_pdata __initconst = { |
| 329 | .operating_mode = FSL_USB2_DR_DEVICE, | 332 | .operating_mode = FSL_USB2_DR_DEVICE, |
| 330 | .phy_mode = FSL_USB2_PHY_ULPI, | 333 | .phy_mode = FSL_USB2_PHY_ULPI, |
| 331 | }; | 334 | }; |
| @@ -344,7 +347,7 @@ void __init mx31moboard_marxbot_init(void) | |||
| 344 | 347 | ||
| 345 | dspics_resets_init(); | 348 | dspics_resets_init(); |
| 346 | 349 | ||
| 347 | mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); | 350 | imx31_add_mxc_mmc(1, &sdhc2_pdata); |
| 348 | 351 | ||
| 349 | spi_register_board_info(marxbot_spi_board_info, | 352 | spi_register_board_info(marxbot_spi_board_info, |
| 350 | ARRAY_SIZE(marxbot_spi_board_info)); | 353 | ARRAY_SIZE(marxbot_spi_board_info)); |
| @@ -357,7 +360,7 @@ void __init mx31moboard_marxbot_init(void) | |||
| 357 | gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_LCS0)); | 360 | gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_LCS0)); |
| 358 | gpio_export(IOMUX_TO_GPIO(MX31_PIN_LCS0), false); | 361 | gpio_export(IOMUX_TO_GPIO(MX31_PIN_LCS0), false); |
| 359 | 362 | ||
| 360 | mxc_register_device(&mxc_otg_udc_device, &usb_pdata); | 363 | imx31_add_fsl_usb2_udc(&usb_pdata); |
| 361 | 364 | ||
| 362 | marxbot_usbh1_init(); | 365 | marxbot_usbh1_init(); |
| 363 | } | 366 | } |
diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-mx3/mx31moboard-smartbot.c index 04760a53005a..bbec3c82264a 100644 --- a/arch/arm/mach-mx3/mx31moboard-smartbot.c +++ b/arch/arm/mach-mx3/mx31moboard-smartbot.c | |||
| @@ -19,7 +19,6 @@ | |||
| 19 | #include <linux/i2c.h> | 19 | #include <linux/i2c.h> |
| 20 | #include <linux/platform_device.h> | 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/types.h> | 21 | #include <linux/types.h> |
| 22 | #include <linux/fsl_devices.h> | ||
| 23 | 22 | ||
| 24 | #include <linux/usb/otg.h> | 23 | #include <linux/usb/otg.h> |
| 25 | #include <linux/usb/ulpi.h> | 24 | #include <linux/usb/ulpi.h> |
| @@ -28,7 +27,6 @@ | |||
| 28 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
| 29 | #include <mach/iomux-mx3.h> | 28 | #include <mach/iomux-mx3.h> |
| 30 | #include <mach/board-mx31moboard.h> | 29 | #include <mach/board-mx31moboard.h> |
| 31 | #include <mach/mxc_ehci.h> | ||
| 32 | #include <mach/ulpi.h> | 30 | #include <mach/ulpi.h> |
| 33 | 31 | ||
| 34 | #include <media/soc_camera.h> | 32 | #include <media/soc_camera.h> |
| @@ -118,24 +116,30 @@ static int __init smartbot_cam_init(void) | |||
| 118 | return 0; | 116 | return 0; |
| 119 | } | 117 | } |
| 120 | 118 | ||
| 121 | static struct fsl_usb2_platform_data usb_pdata = { | 119 | static const struct fsl_usb2_platform_data usb_pdata __initconst = { |
| 122 | .operating_mode = FSL_USB2_DR_DEVICE, | 120 | .operating_mode = FSL_USB2_DR_DEVICE, |
| 123 | .phy_mode = FSL_USB2_PHY_ULPI, | 121 | .phy_mode = FSL_USB2_PHY_ULPI, |
| 124 | }; | 122 | }; |
| 125 | 123 | ||
| 126 | #if defined(CONFIG_USB_ULPI) | 124 | #if defined(CONFIG_USB_ULPI) |
| 127 | 125 | ||
| 128 | static struct mxc_usbh_platform_data otg_host_pdata = { | 126 | static struct mxc_usbh_platform_data otg_host_pdata __initdata = { |
| 129 | .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, | 127 | .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, |
| 130 | .flags = MXC_EHCI_POWER_PINS_ENABLED, | 128 | .flags = MXC_EHCI_POWER_PINS_ENABLED, |
| 131 | }; | 129 | }; |
| 132 | 130 | ||
| 133 | static int __init smartbot_otg_host_init(void) | 131 | static int __init smartbot_otg_host_init(void) |
| 134 | { | 132 | { |
| 133 | struct platform_device *pdev; | ||
| 134 | |||
| 135 | otg_host_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, | 135 | otg_host_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, |
| 136 | ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); | 136 | ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); |
| 137 | 137 | ||
| 138 | return mxc_register_device(&mxc_otg_host, &otg_host_pdata); | 138 | pdev = imx31_add_mxc_ehci_otg(&otg_host_pdata); |
| 139 | if (IS_ERR(pdev)) | ||
| 140 | return PTR_ERR(pdev); | ||
| 141 | |||
| 142 | return 0; | ||
| 139 | } | 143 | } |
| 140 | #else | 144 | #else |
| 141 | static inline int smartbot_otg_host_init(void) { return 0; } | 145 | static inline int smartbot_otg_host_init(void) { return 0; } |
| @@ -182,7 +186,7 @@ void __init mx31moboard_smartbot_init(int board) | |||
| 182 | 186 | ||
| 183 | switch (board) { | 187 | switch (board) { |
| 184 | case MX31SMARTBOT: | 188 | case MX31SMARTBOT: |
| 185 | mxc_register_device(&mxc_otg_udc_device, &usb_pdata); | 189 | imx31_add_fsl_usb2_udc(&usb_pdata); |
| 186 | break; | 190 | break; |
| 187 | case MX31EYEBOT: | 191 | case MX31EYEBOT: |
| 188 | smartbot_otg_host_init(); | 192 | smartbot_otg_host_init(); |
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index 3ec910a7a182..55254b6e9460 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig | |||
| @@ -1,20 +1,47 @@ | |||
| 1 | if ARCH_MX5 | 1 | if ARCH_MX5 |
| 2 | # ARCH_MX51 and ARCH_MX50 are left for compatibility | ||
| 3 | |||
| 4 | config ARCH_MX50 | ||
| 5 | bool | ||
| 2 | 6 | ||
| 3 | config ARCH_MX51 | 7 | config ARCH_MX51 |
| 4 | bool | 8 | bool |
| 5 | default y | 9 | |
| 10 | config ARCH_MX53 | ||
| 11 | bool | ||
| 12 | |||
| 13 | config SOC_IMX50 | ||
| 14 | bool | ||
| 15 | select MXC_TZIC | ||
| 16 | select ARCH_MXC_IOMUX_V3 | ||
| 17 | select ARCH_MXC_AUDMUX_V2 | ||
| 18 | select ARCH_HAS_CPUFREQ | ||
| 19 | select ARCH_MX50 | ||
| 20 | |||
| 21 | config SOC_IMX51 | ||
| 22 | bool | ||
| 6 | select MXC_TZIC | 23 | select MXC_TZIC |
| 7 | select ARCH_MXC_IOMUX_V3 | 24 | select ARCH_MXC_IOMUX_V3 |
| 8 | select ARCH_MXC_AUDMUX_V2 | 25 | select ARCH_MXC_AUDMUX_V2 |
| 9 | select ARCH_HAS_CPUFREQ | 26 | select ARCH_HAS_CPUFREQ |
| 27 | select ARCH_MX51 | ||
| 28 | |||
| 29 | config SOC_IMX53 | ||
| 30 | bool | ||
| 31 | select MXC_TZIC | ||
| 32 | select ARCH_MXC_IOMUX_V3 | ||
| 33 | select ARCH_MX53 | ||
| 10 | 34 | ||
| 11 | comment "MX5 platforms:" | 35 | comment "MX5 platforms:" |
| 12 | 36 | ||
| 13 | config MACH_MX51_BABBAGE | 37 | config MACH_MX51_BABBAGE |
| 14 | bool "Support MX51 BABBAGE platforms" | 38 | bool "Support MX51 BABBAGE platforms" |
| 39 | select SOC_IMX51 | ||
| 40 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
| 15 | select IMX_HAVE_PLATFORM_IMX_I2C | 41 | select IMX_HAVE_PLATFORM_IMX_I2C |
| 16 | select IMX_HAVE_PLATFORM_IMX_UART | 42 | select IMX_HAVE_PLATFORM_IMX_UART |
| 17 | select IMX_HAVE_PLATFORM_ESDHC | 43 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX |
| 44 | select IMX_HAVE_PLATFORM_SPI_IMX | ||
| 18 | help | 45 | help |
| 19 | Include support for MX51 Babbage platform, also known as MX51EVK in | 46 | Include support for MX51 Babbage platform, also known as MX51EVK in |
| 20 | u-boot. This includes specific configurations for the board and its | 47 | u-boot. This includes specific configurations for the board and its |
| @@ -22,7 +49,9 @@ config MACH_MX51_BABBAGE | |||
| 22 | 49 | ||
| 23 | config MACH_MX51_3DS | 50 | config MACH_MX51_3DS |
| 24 | bool "Support MX51PDK (3DS)" | 51 | bool "Support MX51PDK (3DS)" |
| 52 | select SOC_IMX51 | ||
| 25 | select IMX_HAVE_PLATFORM_IMX_UART | 53 | select IMX_HAVE_PLATFORM_IMX_UART |
| 54 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
| 26 | select IMX_HAVE_PLATFORM_SPI_IMX | 55 | select IMX_HAVE_PLATFORM_SPI_IMX |
| 27 | select MXC_DEBUG_BOARD | 56 | select MXC_DEBUG_BOARD |
| 28 | help | 57 | help |
| @@ -31,6 +60,7 @@ config MACH_MX51_3DS | |||
| 31 | 60 | ||
| 32 | config MACH_EUKREA_CPUIMX51 | 61 | config MACH_EUKREA_CPUIMX51 |
| 33 | bool "Support Eukrea CPUIMX51 module" | 62 | bool "Support Eukrea CPUIMX51 module" |
| 63 | select SOC_IMX51 | ||
| 34 | select IMX_HAVE_PLATFORM_IMX_I2C | 64 | select IMX_HAVE_PLATFORM_IMX_I2C |
| 35 | select IMX_HAVE_PLATFORM_IMX_UART | 65 | select IMX_HAVE_PLATFORM_IMX_UART |
| 36 | select IMX_HAVE_PLATFORM_MXC_NAND | 66 | select IMX_HAVE_PLATFORM_MXC_NAND |
| @@ -47,7 +77,7 @@ choice | |||
| 47 | config MACH_EUKREA_MBIMX51_BASEBOARD | 77 | config MACH_EUKREA_MBIMX51_BASEBOARD |
| 48 | prompt "Eukrea MBIMX51 development board" | 78 | prompt "Eukrea MBIMX51 development board" |
| 49 | bool | 79 | bool |
| 50 | select IMX_HAVE_PLATFORM_ESDHC | 80 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX |
| 51 | help | 81 | help |
| 52 | This adds board specific devices that can be found on Eukrea's | 82 | This adds board specific devices that can be found on Eukrea's |
| 53 | MBIMX51 evaluation board. | 83 | MBIMX51 evaluation board. |
| @@ -56,6 +86,7 @@ endchoice | |||
| 56 | 86 | ||
| 57 | config MACH_EUKREA_CPUIMX51SD | 87 | config MACH_EUKREA_CPUIMX51SD |
| 58 | bool "Support Eukrea CPUIMX51SD module" | 88 | bool "Support Eukrea CPUIMX51SD module" |
| 89 | select SOC_IMX51 | ||
| 59 | select IMX_HAVE_PLATFORM_IMX_I2C | 90 | select IMX_HAVE_PLATFORM_IMX_I2C |
| 60 | select IMX_HAVE_PLATFORM_SPI_IMX | 91 | select IMX_HAVE_PLATFORM_SPI_IMX |
| 61 | select IMX_HAVE_PLATFORM_IMX_UART | 92 | select IMX_HAVE_PLATFORM_IMX_UART |
| @@ -72,7 +103,7 @@ choice | |||
| 72 | config MACH_EUKREA_MBIMXSD51_BASEBOARD | 103 | config MACH_EUKREA_MBIMXSD51_BASEBOARD |
| 73 | prompt "Eukrea MBIMXSD development board" | 104 | prompt "Eukrea MBIMXSD development board" |
| 74 | bool | 105 | bool |
| 75 | select IMX_HAVE_PLATFORM_ESDHC | 106 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX |
| 76 | help | 107 | help |
| 77 | This adds board specific devices that can be found on Eukrea's | 108 | This adds board specific devices that can be found on Eukrea's |
| 78 | MBIMXSD evaluation board. | 109 | MBIMXSD evaluation board. |
| @@ -81,9 +112,33 @@ endchoice | |||
| 81 | 112 | ||
| 82 | config MACH_MX51_EFIKAMX | 113 | config MACH_MX51_EFIKAMX |
| 83 | bool "Support MX51 Genesi Efika MX nettop" | 114 | bool "Support MX51 Genesi Efika MX nettop" |
| 115 | select SOC_IMX51 | ||
| 84 | select IMX_HAVE_PLATFORM_IMX_UART | 116 | select IMX_HAVE_PLATFORM_IMX_UART |
| 117 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
| 118 | select IMX_HAVE_PLATFORM_SPI_IMX | ||
| 85 | help | 119 | help |
| 86 | Include support for Genesi Efika MX nettop. This includes specific | 120 | Include support for Genesi Efika MX nettop. This includes specific |
| 87 | configurations for the board and its peripherals. | 121 | configurations for the board and its peripherals. |
| 88 | 122 | ||
| 123 | config MACH_MX53_EVK | ||
| 124 | bool "Support MX53 EVK platforms" | ||
| 125 | select SOC_IMX53 | ||
| 126 | select IMX_HAVE_PLATFORM_IMX_UART | ||
| 127 | help | ||
| 128 | Include support for MX53 EVK platform. This includes specific | ||
| 129 | configurations for the board and its peripherals. | ||
| 130 | |||
| 131 | |||
| 132 | config MACH_MX50_RDP | ||
| 133 | bool "Support MX50 reference design platform" | ||
| 134 | depends on BROKEN | ||
| 135 | select SOC_IMX50 | ||
| 136 | select IMX_HAVE_PLATFORM_IMX_I2C | ||
| 137 | select IMX_HAVE_PLATFORM_IMX_UART | ||
| 138 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
| 139 | select IMX_HAVE_PLATFORM_SPI_IMX | ||
| 140 | help | ||
| 141 | Include support for MX50 reference design platform (RDP) board. This | ||
| 142 | includes specific configurations for the board and its peripherals. | ||
| 143 | |||
| 89 | endif | 144 | endif |
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile index 462f177eddfe..0c398baf11fe 100644 --- a/arch/arm/mach-mx5/Makefile +++ b/arch/arm/mach-mx5/Makefile | |||
| @@ -3,13 +3,16 @@ | |||
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | # Object file lists. | 5 | # Object file lists. |
| 6 | obj-y := cpu.o mm.o clock-mx51.o devices.o | 6 | obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o |
| 7 | obj-$(CONFIG_SOC_IMX50) += mm-mx50.o | ||
| 7 | 8 | ||
| 8 | obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o | 9 | obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o |
| 9 | obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o | 10 | obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o |
| 10 | obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o | 11 | obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o |
| 12 | obj-$(CONFIG_MACH_MX53_EVK) += board-mx53_evk.o | ||
| 11 | obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o | 13 | obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o |
| 12 | obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o | 14 | obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o |
| 13 | obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o | 15 | obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o |
| 14 | obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o | 16 | obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o |
| 15 | obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o | 17 | obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o |
| 18 | obj-$(CONFIG_MACH_MX50_RDP) += board-mx50_rdp.o | ||
diff --git a/arch/arm/mach-mx5/Makefile.boot b/arch/arm/mach-mx5/Makefile.boot index 9939a19d99a1..e928be1b6757 100644 --- a/arch/arm/mach-mx5/Makefile.boot +++ b/arch/arm/mach-mx5/Makefile.boot | |||
| @@ -1,3 +1,9 @@ | |||
| 1 | zreladdr-y := 0x90008000 | 1 | zreladdr-$(CONFIG_ARCH_MX50) := 0x70008000 |
| 2 | params_phys-y := 0x90000100 | 2 | params_phys-$(CONFIG_ARCH_MX50) := 0x70000100 |
| 3 | initrd_phys-y := 0x90800000 | 3 | initrd_phys-$(CONFIG_ARCH_MX50) := 0x70800000 |
| 4 | zreladdr-$(CONFIG_ARCH_MX51) := 0x90008000 | ||
| 5 | params_phys-$(CONFIG_ARCH_MX51) := 0x90000100 | ||
| 6 | initrd_phys-$(CONFIG_ARCH_MX51) := 0x90800000 | ||
| 7 | zreladdr-$(CONFIG_ARCH_MX53) := 0x70008000 | ||
| 8 | params_phys-$(CONFIG_ARCH_MX53) := 0x70000100 | ||
| 9 | initrd_phys-$(CONFIG_ARCH_MX53) := 0x70800000 | ||
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c index 6a9792fd0a76..f8652ef25f85 100644 --- a/arch/arm/mach-mx5/board-cpuimx51.c +++ b/arch/arm/mach-mx5/board-cpuimx51.c | |||
| @@ -40,11 +40,11 @@ | |||
| 40 | #include "devices-imx51.h" | 40 | #include "devices-imx51.h" |
| 41 | #include "devices.h" | 41 | #include "devices.h" |
| 42 | 42 | ||
| 43 | #define CPUIMX51_USBH1_STP (0*32 + 27) | 43 | #define CPUIMX51_USBH1_STP IMX_GPIO_NR(1, 27) |
| 44 | #define CPUIMX51_QUARTA_GPIO (2*32 + 28) | 44 | #define CPUIMX51_QUARTA_GPIO IMX_GPIO_NR(3, 28) |
| 45 | #define CPUIMX51_QUARTB_GPIO (2*32 + 25) | 45 | #define CPUIMX51_QUARTB_GPIO IMX_GPIO_NR(3, 25) |
| 46 | #define CPUIMX51_QUARTC_GPIO (2*32 + 26) | 46 | #define CPUIMX51_QUARTC_GPIO IMX_GPIO_NR(3, 26) |
| 47 | #define CPUIMX51_QUARTD_GPIO (2*32 + 27) | 47 | #define CPUIMX51_QUARTD_GPIO IMX_GPIO_NR(3, 27) |
| 48 | #define CPUIMX51_QUARTA_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTA_GPIO) | 48 | #define CPUIMX51_QUARTA_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTA_GPIO) |
| 49 | #define CPUIMX51_QUARTB_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTB_GPIO) | 49 | #define CPUIMX51_QUARTB_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTB_GPIO) |
| 50 | #define CPUIMX51_QUARTC_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTC_GPIO) | 50 | #define CPUIMX51_QUARTC_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTC_GPIO) |
| @@ -113,7 +113,7 @@ static struct platform_device *devices[] __initdata = { | |||
| 113 | #endif | 113 | #endif |
| 114 | }; | 114 | }; |
| 115 | 115 | ||
| 116 | static struct pad_desc eukrea_cpuimx51_pads[] = { | 116 | static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = { |
| 117 | /* UART1 */ | 117 | /* UART1 */ |
| 118 | MX51_PAD_UART1_RXD__UART1_RXD, | 118 | MX51_PAD_UART1_RXD__UART1_RXD, |
| 119 | MX51_PAD_UART1_TXD__UART1_TXD, | 119 | MX51_PAD_UART1_TXD__UART1_TXD, |
| @@ -121,15 +121,15 @@ static struct pad_desc eukrea_cpuimx51_pads[] = { | |||
| 121 | MX51_PAD_UART1_CTS__UART1_CTS, | 121 | MX51_PAD_UART1_CTS__UART1_CTS, |
| 122 | 122 | ||
| 123 | /* I2C2 */ | 123 | /* I2C2 */ |
| 124 | MX51_PAD_GPIO_1_2__I2C2_SCL, | 124 | MX51_PAD_GPIO1_2__I2C2_SCL, |
| 125 | MX51_PAD_GPIO_1_3__I2C2_SDA, | 125 | MX51_PAD_GPIO1_3__I2C2_SDA, |
| 126 | MX51_PAD_NANDF_D10__GPIO_3_30, | 126 | MX51_PAD_NANDF_D10__GPIO3_30, |
| 127 | 127 | ||
| 128 | /* QUART IRQ */ | 128 | /* QUART IRQ */ |
| 129 | MX51_PAD_NANDF_D15__GPIO_3_25, | 129 | MX51_PAD_NANDF_D15__GPIO3_25, |
| 130 | MX51_PAD_NANDF_D14__GPIO_3_26, | 130 | MX51_PAD_NANDF_D14__GPIO3_26, |
| 131 | MX51_PAD_NANDF_D13__GPIO_3_27, | 131 | MX51_PAD_NANDF_D13__GPIO3_27, |
| 132 | MX51_PAD_NANDF_D12__GPIO_3_28, | 132 | MX51_PAD_NANDF_D12__GPIO3_28, |
| 133 | 133 | ||
| 134 | /* USB HOST1 */ | 134 | /* USB HOST1 */ |
| 135 | MX51_PAD_USBH1_CLK__USBH1_CLK, | 135 | MX51_PAD_USBH1_CLK__USBH1_CLK, |
| @@ -178,6 +178,8 @@ static int initialize_otg_port(struct platform_device *pdev) | |||
| 178 | void __iomem *usbother_base; | 178 | void __iomem *usbother_base; |
| 179 | 179 | ||
| 180 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); | 180 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); |
| 181 | if (!usb_base) | ||
| 182 | return -ENOMEM; | ||
| 181 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; | 183 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; |
| 182 | 184 | ||
| 183 | /* Set the PHY clock to 19.2MHz */ | 185 | /* Set the PHY clock to 19.2MHz */ |
| @@ -196,6 +198,8 @@ static int initialize_usbh1_port(struct platform_device *pdev) | |||
| 196 | void __iomem *usbother_base; | 198 | void __iomem *usbother_base; |
| 197 | 199 | ||
| 198 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); | 200 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); |
| 201 | if (!usb_base) | ||
| 202 | return -ENOMEM; | ||
| 199 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; | 203 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; |
| 200 | 204 | ||
| 201 | /* The clock for the USBH1 ULPI port will come externally from the PHY. */ | 205 | /* The clock for the USBH1 ULPI port will come externally from the PHY. */ |
| @@ -292,7 +296,7 @@ static struct sys_timer mxc_timer = { | |||
| 292 | 296 | ||
| 293 | MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module") | 297 | MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module") |
| 294 | /* Maintainer: Eric Bénard <eric@eukrea.com> */ | 298 | /* Maintainer: Eric Bénard <eric@eukrea.com> */ |
| 295 | .boot_params = PHYS_OFFSET + 0x100, | 299 | .boot_params = MX51_PHYS_OFFSET + 0x100, |
| 296 | .map_io = mx51_map_io, | 300 | .map_io = mx51_map_io, |
| 297 | .init_irq = mx51_init_irq, | 301 | .init_irq = mx51_init_irq, |
| 298 | .init_machine = eukrea_cpuimx51_init, | 302 | .init_machine = eukrea_cpuimx51_init, |
diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c index 4b3a6119c5fb..ad931895d8b6 100644 --- a/arch/arm/mach-mx5/board-cpuimx51sd.c +++ b/arch/arm/mach-mx5/board-cpuimx51sd.c | |||
| @@ -43,19 +43,19 @@ | |||
| 43 | #include "devices-imx51.h" | 43 | #include "devices-imx51.h" |
| 44 | #include "devices.h" | 44 | #include "devices.h" |
| 45 | 45 | ||
| 46 | #define USBH1_RST (1*32 + 28) | 46 | #define USBH1_RST IMX_GPIO_NR(2, 28) |
| 47 | #define ETH_RST (1*32 + 31) | 47 | #define ETH_RST IMX_GPIO_NR(2, 31) |
| 48 | #define TSC2007_IRQGPIO (2*32 + 12) | 48 | #define TSC2007_IRQGPIO IMX_GPIO_NR(3, 12) |
| 49 | #define CAN_IRQGPIO (0*32 + 1) | 49 | #define CAN_IRQGPIO IMX_GPIO_NR(1, 1) |
| 50 | #define CAN_RST (3*32 + 15) | 50 | #define CAN_RST IMX_GPIO_NR(4, 15) |
| 51 | #define CAN_NCS (3*32 + 24) | 51 | #define CAN_NCS IMX_GPIO_NR(4, 24) |
| 52 | #define CAN_RXOBF (0*32 + 4) | 52 | #define CAN_RXOBF IMX_GPIO_NR(1, 4) |
| 53 | #define CAN_RX1BF (0*32 + 6) | 53 | #define CAN_RX1BF IMX_GPIO_NR(1, 6) |
| 54 | #define CAN_TXORTS (0*32 + 7) | 54 | #define CAN_TXORTS IMX_GPIO_NR(1, 7) |
| 55 | #define CAN_TX1RTS (0*32 + 8) | 55 | #define CAN_TX1RTS IMX_GPIO_NR(1, 8) |
| 56 | #define CAN_TX2RTS (0*32 + 9) | 56 | #define CAN_TX2RTS IMX_GPIO_NR(1, 9) |
| 57 | #define I2C_SCL (3*32 + 16) | 57 | #define I2C_SCL IMX_GPIO_NR(4, 16) |
| 58 | #define I2C_SDA (3*32 + 17) | 58 | #define I2C_SDA IMX_GPIO_NR(4, 17) |
| 59 | 59 | ||
| 60 | /* USB_CTRL_1 */ | 60 | /* USB_CTRL_1 */ |
| 61 | #define MX51_USB_CTRL_1_OFFSET 0x10 | 61 | #define MX51_USB_CTRL_1_OFFSET 0x10 |
| @@ -65,10 +65,7 @@ | |||
| 65 | #define MX51_USB_PLL_DIV_19_2_MHZ 0x01 | 65 | #define MX51_USB_PLL_DIV_19_2_MHZ 0x01 |
| 66 | #define MX51_USB_PLL_DIV_24_MHZ 0x02 | 66 | #define MX51_USB_PLL_DIV_24_MHZ 0x02 |
| 67 | 67 | ||
| 68 | #define CPUIMX51SD_GPIO_3_12 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, \ | 68 | static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = { |
| 69 | MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP) | ||
| 70 | |||
| 71 | static struct pad_desc eukrea_cpuimx51sd_pads[] = { | ||
| 72 | /* UART1 */ | 69 | /* UART1 */ |
| 73 | MX51_PAD_UART1_RXD__UART1_RXD, | 70 | MX51_PAD_UART1_RXD__UART1_RXD, |
| 74 | MX51_PAD_UART1_TXD__UART1_TXD, | 71 | MX51_PAD_UART1_TXD__UART1_TXD, |
| @@ -88,30 +85,33 @@ static struct pad_desc eukrea_cpuimx51sd_pads[] = { | |||
| 88 | MX51_PAD_USBH1_DATA6__USBH1_DATA6, | 85 | MX51_PAD_USBH1_DATA6__USBH1_DATA6, |
| 89 | MX51_PAD_USBH1_DATA7__USBH1_DATA7, | 86 | MX51_PAD_USBH1_DATA7__USBH1_DATA7, |
| 90 | MX51_PAD_USBH1_STP__USBH1_STP, | 87 | MX51_PAD_USBH1_STP__USBH1_STP, |
| 91 | MX51_PAD_EIM_CS3__GPIO_2_28, /* PHY nRESET */ | 88 | MX51_PAD_EIM_CS3__GPIO2_28, /* PHY nRESET */ |
| 92 | 89 | ||
| 93 | /* FEC */ | 90 | /* FEC */ |
| 94 | MX51_PAD_EIM_DTACK__GPIO_2_31, /* PHY nRESET */ | 91 | MX51_PAD_EIM_DTACK__GPIO2_31, /* PHY nRESET */ |
| 95 | 92 | ||
| 96 | /* HSI2C */ | 93 | /* HSI2C */ |
| 97 | MX51_PAD_I2C1_CLK__GPIO_4_16, | 94 | MX51_PAD_I2C1_CLK__GPIO4_16, |
| 98 | MX51_PAD_I2C1_DAT__GPIO_4_17, | 95 | MX51_PAD_I2C1_DAT__GPIO4_17, |
| 99 | 96 | ||
| 100 | /* CAN */ | 97 | /* CAN */ |
| 101 | MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, | 98 | MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, |
| 102 | MX51_PAD_CSPI1_MISO__ECSPI1_MISO, | 99 | MX51_PAD_CSPI1_MISO__ECSPI1_MISO, |
| 103 | MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, | 100 | MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, |
| 104 | MX51_PAD_CSPI1_SS0__GPIO_4_24, /* nCS */ | 101 | MX51_PAD_CSPI1_SS0__GPIO4_24, /* nCS */ |
| 105 | MX51_PAD_CSI2_PIXCLK__GPIO_4_15, /* nReset */ | 102 | MX51_PAD_CSI2_PIXCLK__GPIO4_15, /* nReset */ |
| 106 | MX51_PAD_GPIO_1_1__GPIO_1_1, /* IRQ */ | 103 | MX51_PAD_GPIO1_1__GPIO1_1, /* IRQ */ |
| 107 | MX51_PAD_GPIO_1_4__GPIO_1_4, /* Control signals */ | 104 | MX51_PAD_GPIO1_4__GPIO1_4, /* Control signals */ |
| 108 | MX51_PAD_GPIO_1_6__GPIO_1_6, | 105 | MX51_PAD_GPIO1_6__GPIO1_6, |
| 109 | MX51_PAD_GPIO_1_7__GPIO_1_7, | 106 | MX51_PAD_GPIO1_7__GPIO1_7, |
| 110 | MX51_PAD_GPIO_1_8__GPIO_1_8, | 107 | MX51_PAD_GPIO1_8__GPIO1_8, |
| 111 | MX51_PAD_GPIO_1_9__GPIO_1_9, | 108 | MX51_PAD_GPIO1_9__GPIO1_9, |
| 112 | 109 | ||
| 113 | /* Touchscreen */ | 110 | /* Touchscreen */ |
| 114 | CPUIMX51SD_GPIO_3_12, /* IRQ */ | 111 | /* IRQ */ |
| 112 | _MX51_PAD_CSI1_D8__GPIO3_12 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | | ||
| 113 | PAD_CTL_PKE | PAD_CTL_SRE_FAST | | ||
| 114 | PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS), | ||
| 115 | }; | 115 | }; |
| 116 | 116 | ||
| 117 | static const struct imxuart_platform_data uart_pdata __initconst = { | 117 | static const struct imxuart_platform_data uart_pdata __initconst = { |
| @@ -157,6 +157,8 @@ static int initialize_otg_port(struct platform_device *pdev) | |||
| 157 | void __iomem *usbother_base; | 157 | void __iomem *usbother_base; |
| 158 | 158 | ||
| 159 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); | 159 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); |
| 160 | if (!usb_base) | ||
| 161 | return -ENOMEM; | ||
| 160 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; | 162 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; |
| 161 | 163 | ||
| 162 | /* Set the PHY clock to 19.2MHz */ | 164 | /* Set the PHY clock to 19.2MHz */ |
| @@ -175,6 +177,8 @@ static int initialize_usbh1_port(struct platform_device *pdev) | |||
| 175 | void __iomem *usbother_base; | 177 | void __iomem *usbother_base; |
| 176 | 178 | ||
| 177 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); | 179 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); |
| 180 | if (!usb_base) | ||
| 181 | return -ENOMEM; | ||
| 178 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; | 182 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; |
| 179 | 183 | ||
| 180 | /* The clock for the USBH1 ULPI port will come from the PHY. */ | 184 | /* The clock for the USBH1 ULPI port will come from the PHY. */ |
| @@ -243,7 +247,7 @@ static struct spi_board_info cpuimx51sd_spi_device[] = { | |||
| 243 | .mode = SPI_MODE_0, | 247 | .mode = SPI_MODE_0, |
| 244 | .chip_select = 0, | 248 | .chip_select = 0, |
| 245 | .platform_data = &mcp251x_info, | 249 | .platform_data = &mcp251x_info, |
| 246 | .irq = gpio_to_irq(0 * 32 + 1) | 250 | .irq = gpio_to_irq(CAN_IRQGPIO) |
| 247 | }, | 251 | }, |
| 248 | }; | 252 | }; |
| 249 | 253 | ||
| @@ -323,7 +327,7 @@ static struct sys_timer mxc_timer = { | |||
| 323 | 327 | ||
| 324 | MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD") | 328 | MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD") |
| 325 | /* Maintainer: Eric Bénard <eric@eukrea.com> */ | 329 | /* Maintainer: Eric Bénard <eric@eukrea.com> */ |
| 326 | .boot_params = PHYS_OFFSET + 0x100, | 330 | .boot_params = MX51_PHYS_OFFSET + 0x100, |
| 327 | .map_io = mx51_map_io, | 331 | .map_io = mx51_map_io, |
| 328 | .init_irq = mx51_init_irq, | 332 | .init_irq = mx51_init_irq, |
| 329 | .init_machine = eukrea_cpuimx51sd_init, | 333 | .init_machine = eukrea_cpuimx51sd_init, |
diff --git a/arch/arm/mach-mx5/board-mx50_rdp.c b/arch/arm/mach-mx5/board-mx50_rdp.c new file mode 100644 index 000000000000..fd32e4c450e8 --- /dev/null +++ b/arch/arm/mach-mx5/board-mx50_rdp.c | |||
| @@ -0,0 +1,197 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | */ | ||
| 4 | |||
| 5 | /* | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | |||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | |||
| 16 | * You should have received a copy of the GNU General Public License along | ||
| 17 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include <linux/init.h> | ||
| 22 | #include <linux/platform_device.h> | ||
| 23 | #include <linux/gpio.h> | ||
| 24 | #include <linux/delay.h> | ||
| 25 | #include <linux/io.h> | ||
| 26 | #include <linux/fsl_devices.h> | ||
| 27 | |||
| 28 | #include <mach/common.h> | ||
| 29 | #include <mach/hardware.h> | ||
| 30 | #include <mach/iomux-mx50.h> | ||
| 31 | |||
| 32 | #include <asm/irq.h> | ||
| 33 | #include <asm/setup.h> | ||
| 34 | #include <asm/mach-types.h> | ||
| 35 | #include <asm/mach/arch.h> | ||
| 36 | #include <asm/mach/time.h> | ||
| 37 | |||
| 38 | #include "devices-mx50.h" | ||
| 39 | |||
| 40 | static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = { | ||
| 41 | /* SD1 */ | ||
| 42 | MX50_PAD_ECSPI2_SS0__GPIO_4_19, | ||
| 43 | MX50_PAD_EIM_CRE__GPIO_1_27, | ||
| 44 | MX50_PAD_SD1_CMD__SD1_CMD, | ||
| 45 | |||
| 46 | MX50_PAD_SD1_CLK__SD1_CLK, | ||
| 47 | MX50_PAD_SD1_D0__SD1_D0, | ||
| 48 | MX50_PAD_SD1_D1__SD1_D1, | ||
| 49 | MX50_PAD_SD1_D2__SD1_D2, | ||
| 50 | MX50_PAD_SD1_D3__SD1_D3, | ||
| 51 | |||
| 52 | /* SD2 */ | ||
| 53 | MX50_PAD_SD2_CD__GPIO_5_17, | ||
| 54 | MX50_PAD_SD2_WP__GPIO_5_16, | ||
| 55 | MX50_PAD_SD2_CMD__SD2_CMD, | ||
| 56 | MX50_PAD_SD2_CLK__SD2_CLK, | ||
| 57 | MX50_PAD_SD2_D0__SD2_D0, | ||
| 58 | MX50_PAD_SD2_D1__SD2_D1, | ||
| 59 | MX50_PAD_SD2_D2__SD2_D2, | ||
| 60 | MX50_PAD_SD2_D3__SD2_D3, | ||
| 61 | MX50_PAD_SD2_D4__SD2_D4, | ||
| 62 | MX50_PAD_SD2_D5__SD2_D5, | ||
| 63 | MX50_PAD_SD2_D6__SD2_D6, | ||
| 64 | MX50_PAD_SD2_D7__SD2_D7, | ||
| 65 | |||
| 66 | /* SD3 */ | ||
| 67 | MX50_PAD_SD3_CMD__SD3_CMD, | ||
| 68 | MX50_PAD_SD3_CLK__SD3_CLK, | ||
| 69 | MX50_PAD_SD3_D0__SD3_D0, | ||
| 70 | MX50_PAD_SD3_D1__SD3_D1, | ||
| 71 | MX50_PAD_SD3_D2__SD3_D2, | ||
| 72 | MX50_PAD_SD3_D3__SD3_D3, | ||
| 73 | MX50_PAD_SD3_D4__SD3_D4, | ||
| 74 | MX50_PAD_SD3_D5__SD3_D5, | ||
| 75 | MX50_PAD_SD3_D6__SD3_D6, | ||
| 76 | MX50_PAD_SD3_D7__SD3_D7, | ||
| 77 | |||
| 78 | /* PWR_INT */ | ||
| 79 | MX50_PAD_ECSPI2_MISO__GPIO_4_18, | ||
| 80 | |||
| 81 | /* UART pad setting */ | ||
| 82 | MX50_PAD_UART1_TXD__UART1_TXD, | ||
| 83 | MX50_PAD_UART1_RXD__UART1_RXD, | ||
| 84 | MX50_PAD_UART1_RTS__UART1_RTS, | ||
| 85 | MX50_PAD_UART2_TXD__UART2_TXD, | ||
| 86 | MX50_PAD_UART2_RXD__UART2_RXD, | ||
| 87 | MX50_PAD_UART2_CTS__UART2_CTS, | ||
| 88 | MX50_PAD_UART2_RTS__UART2_RTS, | ||
| 89 | |||
| 90 | MX50_PAD_I2C1_SCL__I2C1_SCL, | ||
| 91 | MX50_PAD_I2C1_SDA__I2C1_SDA, | ||
| 92 | MX50_PAD_I2C2_SCL__I2C2_SCL, | ||
| 93 | MX50_PAD_I2C2_SDA__I2C2_SDA, | ||
| 94 | |||
| 95 | MX50_PAD_EPITO__USBH1_PWR, | ||
| 96 | /* Need to comment below line if | ||
| 97 | * one needs to debug owire. | ||
| 98 | */ | ||
| 99 | MX50_PAD_OWIRE__USBH1_OC, | ||
| 100 | /* using gpio to control otg pwr */ | ||
| 101 | MX50_PAD_PWM2__GPIO_6_25, | ||
| 102 | MX50_PAD_I2C3_SCL__USBOTG_OC, | ||
| 103 | |||
| 104 | MX50_PAD_SSI_RXC__FEC_MDIO, | ||
| 105 | MX50_PAD_SSI_RXC__FEC_MDIO, | ||
| 106 | MX50_PAD_DISP_D0__FEC_TXCLK, | ||
| 107 | MX50_PAD_DISP_D1__FEC_RX_ER, | ||
| 108 | MX50_PAD_DISP_D2__FEC_RX_DV, | ||
| 109 | MX50_PAD_DISP_D3__FEC_RXD1, | ||
| 110 | MX50_PAD_DISP_D4__FEC_RXD0, | ||
| 111 | MX50_PAD_DISP_D5__FEC_TX_EN, | ||
| 112 | MX50_PAD_DISP_D6__FEC_TXD1, | ||
| 113 | MX50_PAD_DISP_D7__FEC_TXD0, | ||
| 114 | MX50_PAD_SSI_RXFS__FEC_MDC, | ||
| 115 | MX50_PAD_I2C3_SDA__GPIO_6_23, | ||
| 116 | MX50_PAD_ECSPI1_SCLK__GPIO_4_12, | ||
| 117 | |||
| 118 | MX50_PAD_CSPI_SS0__CSPI_SS0, | ||
| 119 | MX50_PAD_ECSPI1_MOSI__CSPI_SS1, | ||
| 120 | MX50_PAD_CSPI_MOSI__CSPI_MOSI, | ||
| 121 | MX50_PAD_CSPI_MISO__CSPI_MISO, | ||
| 122 | |||
| 123 | /* SGTL500_OSC_EN */ | ||
| 124 | MX50_PAD_UART1_CTS__GPIO_6_8, | ||
| 125 | |||
| 126 | /* SGTL_AMP_SHDN */ | ||
| 127 | MX50_PAD_UART3_RXD__GPIO_6_15, | ||
| 128 | |||
| 129 | /* Keypad */ | ||
| 130 | MX50_PAD_KEY_COL0__KEY_COL0, | ||
| 131 | MX50_PAD_KEY_ROW0__KEY_ROW0, | ||
| 132 | MX50_PAD_KEY_COL1__KEY_COL1, | ||
| 133 | MX50_PAD_KEY_ROW1__KEY_ROW1, | ||
| 134 | MX50_PAD_KEY_COL2__KEY_COL2, | ||
| 135 | MX50_PAD_KEY_ROW2__KEY_ROW2, | ||
| 136 | MX50_PAD_KEY_COL3__KEY_COL3, | ||
| 137 | MX50_PAD_KEY_ROW3__KEY_ROW3, | ||
| 138 | MX50_PAD_EIM_DA0__KEY_COL4, | ||
| 139 | MX50_PAD_EIM_DA1__KEY_ROW4, | ||
| 140 | MX50_PAD_EIM_DA2__KEY_COL5, | ||
| 141 | MX50_PAD_EIM_DA3__KEY_ROW5, | ||
| 142 | MX50_PAD_EIM_DA4__KEY_COL6, | ||
| 143 | MX50_PAD_EIM_DA5__KEY_ROW6, | ||
| 144 | MX50_PAD_EIM_DA6__KEY_COL7, | ||
| 145 | MX50_PAD_EIM_DA7__KEY_ROW7, | ||
| 146 | /*EIM pads */ | ||
| 147 | MX50_PAD_EIM_DA8__GPIO_1_8, | ||
| 148 | MX50_PAD_EIM_DA9__GPIO_1_9, | ||
| 149 | MX50_PAD_EIM_DA10__GPIO_1_10, | ||
| 150 | MX50_PAD_EIM_DA11__GPIO_1_11, | ||
| 151 | MX50_PAD_EIM_DA12__GPIO_1_12, | ||
| 152 | MX50_PAD_EIM_DA13__GPIO_1_13, | ||
| 153 | MX50_PAD_EIM_DA14__GPIO_1_14, | ||
| 154 | MX50_PAD_EIM_DA15__GPIO_1_15, | ||
| 155 | MX50_PAD_EIM_CS2__GPIO_1_16, | ||
| 156 | MX50_PAD_EIM_CS1__GPIO_1_17, | ||
| 157 | MX50_PAD_EIM_CS0__GPIO_1_18, | ||
| 158 | MX50_PAD_EIM_EB0__GPIO_1_19, | ||
| 159 | MX50_PAD_EIM_EB1__GPIO_1_20, | ||
| 160 | MX50_PAD_EIM_WAIT__GPIO_1_21, | ||
| 161 | MX50_PAD_EIM_BCLK__GPIO_1_22, | ||
| 162 | MX50_PAD_EIM_RDY__GPIO_1_23, | ||
| 163 | MX50_PAD_EIM_OE__GPIO_1_24, | ||
| 164 | }; | ||
| 165 | |||
| 166 | /* Serial ports */ | ||
| 167 | static const struct imxuart_platform_data uart_pdata __initconst = { | ||
| 168 | .flags = IMXUART_HAVE_RTSCTS, | ||
| 169 | }; | ||
| 170 | |||
| 171 | /* | ||
| 172 | * Board specific initialization. | ||
| 173 | */ | ||
| 174 | static void __init mx50_rdp_board_init(void) | ||
| 175 | { | ||
| 176 | mxc_iomux_v3_setup_multiple_pads(mx50_rdp_pads, | ||
| 177 | ARRAY_SIZE(mx50_rdp_pads)); | ||
| 178 | |||
| 179 | imx50_add_imx_uart(0, &uart_pdata); | ||
| 180 | imx50_add_imx_uart(1, &uart_pdata); | ||
| 181 | } | ||
| 182 | |||
| 183 | static void __init mx50_rdp_timer_init(void) | ||
| 184 | { | ||
| 185 | mx50_clocks_init(32768, 24000000, 22579200); | ||
| 186 | } | ||
| 187 | |||
| 188 | static struct sys_timer mx50_rdp_timer = { | ||
| 189 | .init = mx50_rdp_timer_init, | ||
| 190 | }; | ||
| 191 | |||
| 192 | MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform") | ||
| 193 | .map_io = mx50_map_io, | ||
| 194 | .init_irq = mx50_init_irq, | ||
| 195 | .init_machine = mx50_rdp_board_init, | ||
| 196 | .timer = &mx50_rdp_timer, | ||
| 197 | MACHINE_END | ||
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c index 79ce8dcf3cda..e42bd2eb034e 100644 --- a/arch/arm/mach-mx5/board-mx51_3ds.c +++ b/arch/arm/mach-mx5/board-mx51_3ds.c | |||
| @@ -30,7 +30,7 @@ | |||
| 30 | #define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 6) | 30 | #define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 6) |
| 31 | #define MX51_3DS_ECSPI2_CS (GPIO_PORTC + 28) | 31 | #define MX51_3DS_ECSPI2_CS (GPIO_PORTC + 28) |
| 32 | 32 | ||
| 33 | static struct pad_desc mx51_3ds_pads[] = { | 33 | static iomux_v3_cfg_t mx51_3ds_pads[] = { |
| 34 | /* UART1 */ | 34 | /* UART1 */ |
| 35 | MX51_PAD_UART1_RXD__UART1_RXD, | 35 | MX51_PAD_UART1_RXD__UART1_RXD, |
| 36 | MX51_PAD_UART1_TXD__UART1_TXD, | 36 | MX51_PAD_UART1_TXD__UART1_TXD, |
| @@ -50,7 +50,7 @@ static struct pad_desc mx51_3ds_pads[] = { | |||
| 50 | MX51_PAD_EIM_D27__UART3_RTS, | 50 | MX51_PAD_EIM_D27__UART3_RTS, |
| 51 | 51 | ||
| 52 | /* CPLD PARENT IRQ PIN */ | 52 | /* CPLD PARENT IRQ PIN */ |
| 53 | MX51_PAD_GPIO_1_6__GPIO_1_6, | 53 | MX51_PAD_GPIO1_6__GPIO1_6, |
| 54 | 54 | ||
| 55 | /* KPP */ | 55 | /* KPP */ |
| 56 | MX51_PAD_KEY_ROW0__KEY_ROW0, | 56 | MX51_PAD_KEY_ROW0__KEY_ROW0, |
| @@ -68,7 +68,7 @@ static struct pad_desc mx51_3ds_pads[] = { | |||
| 68 | MX51_PAD_NANDF_RB2__ECSPI2_SCLK, | 68 | MX51_PAD_NANDF_RB2__ECSPI2_SCLK, |
| 69 | MX51_PAD_NANDF_RB3__ECSPI2_MISO, | 69 | MX51_PAD_NANDF_RB3__ECSPI2_MISO, |
| 70 | MX51_PAD_NANDF_D15__ECSPI2_MOSI, | 70 | MX51_PAD_NANDF_D15__ECSPI2_MOSI, |
| 71 | MX51_PAD_NANDF_D12__GPIO_3_28, | 71 | MX51_PAD_NANDF_D12__GPIO3_28, |
| 72 | }; | 72 | }; |
| 73 | 73 | ||
| 74 | /* Serial ports */ | 74 | /* Serial ports */ |
| @@ -172,6 +172,7 @@ static void __init mxc_board_init(void) | |||
| 172 | printk(KERN_WARNING "Init of the debugboard failed, all " | 172 | printk(KERN_WARNING "Init of the debugboard failed, all " |
| 173 | "devices on the board are unusable.\n"); | 173 | "devices on the board are unusable.\n"); |
| 174 | 174 | ||
| 175 | imx51_add_sdhci_esdhc_imx(0, NULL); | ||
| 175 | mxc_init_keypad(); | 176 | mxc_init_keypad(); |
| 176 | } | 177 | } |
| 177 | 178 | ||
| @@ -186,7 +187,7 @@ static struct sys_timer mxc_timer = { | |||
| 186 | 187 | ||
| 187 | MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board") | 188 | MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board") |
| 188 | /* Maintainer: Freescale Semiconductor, Inc. */ | 189 | /* Maintainer: Freescale Semiconductor, Inc. */ |
| 189 | .boot_params = PHYS_OFFSET + 0x100, | 190 | .boot_params = MX51_PHYS_OFFSET + 0x100, |
| 190 | .map_io = mx51_map_io, | 191 | .map_io = mx51_map_io, |
| 191 | .init_irq = mx51_init_irq, | 192 | .init_irq = mx51_init_irq, |
| 192 | .init_machine = mxc_board_init, | 193 | .init_machine = mxc_board_init, |
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c index acbe30df2e69..1d231e84107c 100644 --- a/arch/arm/mach-mx5/board-mx51_babbage.c +++ b/arch/arm/mach-mx5/board-mx51_babbage.c | |||
| @@ -20,6 +20,8 @@ | |||
| 20 | #include <linux/fec.h> | 20 | #include <linux/fec.h> |
| 21 | #include <linux/gpio_keys.h> | 21 | #include <linux/gpio_keys.h> |
| 22 | #include <linux/input.h> | 22 | #include <linux/input.h> |
| 23 | #include <linux/spi/flash.h> | ||
| 24 | #include <linux/spi/spi.h> | ||
| 23 | 25 | ||
| 24 | #include <mach/common.h> | 26 | #include <mach/common.h> |
| 25 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
| @@ -36,11 +38,13 @@ | |||
| 36 | #include "devices.h" | 38 | #include "devices.h" |
| 37 | #include "cpu_op-mx51.h" | 39 | #include "cpu_op-mx51.h" |
| 38 | 40 | ||
| 39 | #define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */ | 41 | #define BABBAGE_USB_HUB_RESET IMX_GPIO_NR(1, 7) |
| 40 | #define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */ | 42 | #define BABBAGE_USBH1_STP IMX_GPIO_NR(1, 27) |
| 41 | #define BABBAGE_PHY_RESET (1*32 + 5) /* GPIO_2_5 */ | 43 | #define BABBAGE_PHY_RESET IMX_GPIO_NR(2, 5) |
| 42 | #define BABBAGE_FEC_PHY_RESET (1*32 + 14) /* GPIO_2_14 */ | 44 | #define BABBAGE_FEC_PHY_RESET IMX_GPIO_NR(2, 14) |
| 43 | #define BABBAGE_POWER_KEY (1*32 + 21) /* GPIO_2_21 */ | 45 | #define BABBAGE_POWER_KEY IMX_GPIO_NR(2, 21) |
| 46 | #define BABBAGE_ECSPI1_CS0 IMX_GPIO_NR(4, 24) | ||
| 47 | #define BABBAGE_ECSPI1_CS1 IMX_GPIO_NR(4, 25) | ||
| 44 | 48 | ||
| 45 | /* USB_CTRL_1 */ | 49 | /* USB_CTRL_1 */ |
| 46 | #define MX51_USB_CTRL_1_OFFSET 0x10 | 50 | #define MX51_USB_CTRL_1_OFFSET 0x10 |
| @@ -65,7 +69,7 @@ static const struct gpio_keys_platform_data imx_button_data __initconst = { | |||
| 65 | .nbuttons = ARRAY_SIZE(babbage_buttons), | 69 | .nbuttons = ARRAY_SIZE(babbage_buttons), |
| 66 | }; | 70 | }; |
| 67 | 71 | ||
| 68 | static struct pad_desc mx51babbage_pads[] = { | 72 | static iomux_v3_cfg_t mx51babbage_pads[] = { |
| 69 | /* UART1 */ | 73 | /* UART1 */ |
| 70 | MX51_PAD_UART1_RXD__UART1_RXD, | 74 | MX51_PAD_UART1_RXD__UART1_RXD, |
| 71 | MX51_PAD_UART1_TXD__UART1_TXD, | 75 | MX51_PAD_UART1_TXD__UART1_TXD, |
| @@ -91,8 +95,8 @@ static struct pad_desc mx51babbage_pads[] = { | |||
| 91 | MX51_PAD_KEY_COL5__I2C2_SDA, | 95 | MX51_PAD_KEY_COL5__I2C2_SDA, |
| 92 | 96 | ||
| 93 | /* HSI2C */ | 97 | /* HSI2C */ |
| 94 | MX51_PAD_I2C1_CLK__HSI2C_CLK, | 98 | MX51_PAD_I2C1_CLK__I2C1_CLK, |
| 95 | MX51_PAD_I2C1_DAT__HSI2C_DAT, | 99 | MX51_PAD_I2C1_DAT__I2C1_DAT, |
| 96 | 100 | ||
| 97 | /* USB HOST1 */ | 101 | /* USB HOST1 */ |
| 98 | MX51_PAD_USBH1_CLK__USBH1_CLK, | 102 | MX51_PAD_USBH1_CLK__USBH1_CLK, |
| @@ -108,29 +112,29 @@ static struct pad_desc mx51babbage_pads[] = { | |||
| 108 | MX51_PAD_USBH1_DATA7__USBH1_DATA7, | 112 | MX51_PAD_USBH1_DATA7__USBH1_DATA7, |
| 109 | 113 | ||
| 110 | /* USB HUB reset line*/ | 114 | /* USB HUB reset line*/ |
| 111 | MX51_PAD_GPIO_1_7__GPIO_1_7, | 115 | MX51_PAD_GPIO1_7__GPIO1_7, |
| 112 | 116 | ||
| 113 | /* FEC */ | 117 | /* FEC */ |
| 114 | MX51_PAD_EIM_EB2__FEC_MDIO, | 118 | MX51_PAD_EIM_EB2__FEC_MDIO, |
| 115 | MX51_PAD_EIM_EB3__FEC_RDAT1, | 119 | MX51_PAD_EIM_EB3__FEC_RDATA1, |
| 116 | MX51_PAD_EIM_CS2__FEC_RDAT2, | 120 | MX51_PAD_EIM_CS2__FEC_RDATA2, |
| 117 | MX51_PAD_EIM_CS3__FEC_RDAT3, | 121 | MX51_PAD_EIM_CS3__FEC_RDATA3, |
| 118 | MX51_PAD_EIM_CS4__FEC_RX_ER, | 122 | MX51_PAD_EIM_CS4__FEC_RX_ER, |
| 119 | MX51_PAD_EIM_CS5__FEC_CRS, | 123 | MX51_PAD_EIM_CS5__FEC_CRS, |
| 120 | MX51_PAD_NANDF_RB2__FEC_COL, | 124 | MX51_PAD_NANDF_RB2__FEC_COL, |
| 121 | MX51_PAD_NANDF_RB3__FEC_RXCLK, | 125 | MX51_PAD_NANDF_RB3__FEC_RX_CLK, |
| 122 | MX51_PAD_NANDF_RB6__FEC_RDAT0, | 126 | MX51_PAD_NANDF_D9__FEC_RDATA0, |
| 123 | MX51_PAD_NANDF_RB7__FEC_TDAT0, | 127 | MX51_PAD_NANDF_D8__FEC_TDATA0, |
| 124 | MX51_PAD_NANDF_CS2__FEC_TX_ER, | 128 | MX51_PAD_NANDF_CS2__FEC_TX_ER, |
| 125 | MX51_PAD_NANDF_CS3__FEC_MDC, | 129 | MX51_PAD_NANDF_CS3__FEC_MDC, |
| 126 | MX51_PAD_NANDF_CS4__FEC_TDAT1, | 130 | MX51_PAD_NANDF_CS4__FEC_TDATA1, |
| 127 | MX51_PAD_NANDF_CS5__FEC_TDAT2, | 131 | MX51_PAD_NANDF_CS5__FEC_TDATA2, |
| 128 | MX51_PAD_NANDF_CS6__FEC_TDAT3, | 132 | MX51_PAD_NANDF_CS6__FEC_TDATA3, |
| 129 | MX51_PAD_NANDF_CS7__FEC_TX_EN, | 133 | MX51_PAD_NANDF_CS7__FEC_TX_EN, |
| 130 | MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK, | 134 | MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK, |
| 131 | 135 | ||
| 132 | /* FEC PHY reset line */ | 136 | /* FEC PHY reset line */ |
| 133 | MX51_PAD_EIM_A20__GPIO_2_14, | 137 | MX51_PAD_EIM_A20__GPIO2_14, |
| 134 | 138 | ||
| 135 | /* SD 1 */ | 139 | /* SD 1 */ |
| 136 | MX51_PAD_SD1_CMD__SD1_CMD, | 140 | MX51_PAD_SD1_CMD__SD1_CMD, |
| @@ -147,6 +151,13 @@ static struct pad_desc mx51babbage_pads[] = { | |||
| 147 | MX51_PAD_SD2_DATA1__SD2_DATA1, | 151 | MX51_PAD_SD2_DATA1__SD2_DATA1, |
| 148 | MX51_PAD_SD2_DATA2__SD2_DATA2, | 152 | MX51_PAD_SD2_DATA2__SD2_DATA2, |
| 149 | MX51_PAD_SD2_DATA3__SD2_DATA3, | 153 | MX51_PAD_SD2_DATA3__SD2_DATA3, |
| 154 | |||
| 155 | /* eCSPI1 */ | ||
| 156 | MX51_PAD_CSPI1_MISO__ECSPI1_MISO, | ||
| 157 | MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, | ||
| 158 | MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, | ||
| 159 | MX51_PAD_CSPI1_SS0__GPIO4_24, | ||
| 160 | MX51_PAD_CSPI1_SS1__GPIO4_25, | ||
| 150 | }; | 161 | }; |
| 151 | 162 | ||
| 152 | /* Serial ports */ | 163 | /* Serial ports */ |
| @@ -177,12 +188,12 @@ static struct imxi2c_platform_data babbage_hsi2c_data = { | |||
| 177 | 188 | ||
| 178 | static int gpio_usbh1_active(void) | 189 | static int gpio_usbh1_active(void) |
| 179 | { | 190 | { |
| 180 | struct pad_desc usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27; | 191 | iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27; |
| 181 | struct pad_desc phyreset_gpio = MX51_PAD_EIM_D21__GPIO_2_5; | 192 | iomux_v3_cfg_t phyreset_gpio = MX51_PAD_EIM_D21__GPIO2_5; |
| 182 | int ret; | 193 | int ret; |
| 183 | 194 | ||
| 184 | /* Set USBH1_STP to GPIO and toggle it */ | 195 | /* Set USBH1_STP to GPIO and toggle it */ |
| 185 | mxc_iomux_v3_setup_pad(&usbh1stp_gpio); | 196 | mxc_iomux_v3_setup_pad(usbh1stp_gpio); |
| 186 | ret = gpio_request(BABBAGE_USBH1_STP, "usbh1_stp"); | 197 | ret = gpio_request(BABBAGE_USBH1_STP, "usbh1_stp"); |
| 187 | 198 | ||
| 188 | if (ret) { | 199 | if (ret) { |
| @@ -195,7 +206,7 @@ static int gpio_usbh1_active(void) | |||
| 195 | gpio_free(BABBAGE_USBH1_STP); | 206 | gpio_free(BABBAGE_USBH1_STP); |
| 196 | 207 | ||
| 197 | /* De-assert USB PHY RESETB */ | 208 | /* De-assert USB PHY RESETB */ |
| 198 | mxc_iomux_v3_setup_pad(&phyreset_gpio); | 209 | mxc_iomux_v3_setup_pad(phyreset_gpio); |
| 199 | ret = gpio_request(BABBAGE_PHY_RESET, "phy_reset"); | 210 | ret = gpio_request(BABBAGE_PHY_RESET, "phy_reset"); |
| 200 | 211 | ||
| 201 | if (ret) { | 212 | if (ret) { |
| @@ -251,6 +262,8 @@ static int initialize_otg_port(struct platform_device *pdev) | |||
| 251 | void __iomem *usbother_base; | 262 | void __iomem *usbother_base; |
| 252 | 263 | ||
| 253 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); | 264 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); |
| 265 | if (!usb_base) | ||
| 266 | return -ENOMEM; | ||
| 254 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; | 267 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; |
| 255 | 268 | ||
| 256 | /* Set the PHY clock to 19.2MHz */ | 269 | /* Set the PHY clock to 19.2MHz */ |
| @@ -269,6 +282,8 @@ static int initialize_usbh1_port(struct platform_device *pdev) | |||
| 269 | void __iomem *usbother_base; | 282 | void __iomem *usbother_base; |
| 270 | 283 | ||
| 271 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); | 284 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); |
| 285 | if (!usb_base) | ||
| 286 | return -ENOMEM; | ||
| 272 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; | 287 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; |
| 273 | 288 | ||
| 274 | /* The clock for the USBH1 ULPI port will come externally from the PHY. */ | 289 | /* The clock for the USBH1 ULPI port will come externally from the PHY. */ |
| @@ -310,13 +325,35 @@ static int __init babbage_otg_mode(char *options) | |||
| 310 | } | 325 | } |
| 311 | __setup("otg_mode=", babbage_otg_mode); | 326 | __setup("otg_mode=", babbage_otg_mode); |
| 312 | 327 | ||
| 328 | static struct spi_board_info mx51_babbage_spi_board_info[] __initdata = { | ||
| 329 | { | ||
| 330 | .modalias = "mtd_dataflash", | ||
| 331 | .max_speed_hz = 25000000, | ||
| 332 | .bus_num = 0, | ||
| 333 | .chip_select = 1, | ||
| 334 | .mode = SPI_MODE_0, | ||
| 335 | .platform_data = NULL, | ||
| 336 | }, | ||
| 337 | }; | ||
| 338 | |||
| 339 | static int mx51_babbage_spi_cs[] = { | ||
| 340 | BABBAGE_ECSPI1_CS0, | ||
| 341 | BABBAGE_ECSPI1_CS1, | ||
| 342 | }; | ||
| 343 | |||
| 344 | static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = { | ||
| 345 | .chipselect = mx51_babbage_spi_cs, | ||
| 346 | .num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs), | ||
| 347 | }; | ||
| 348 | |||
| 313 | /* | 349 | /* |
| 314 | * Board specific initialization. | 350 | * Board specific initialization. |
| 315 | */ | 351 | */ |
| 316 | static void __init mxc_board_init(void) | 352 | static void __init mxc_board_init(void) |
| 317 | { | 353 | { |
| 318 | struct pad_desc usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP; | 354 | iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP; |
| 319 | struct pad_desc power_key = MX51_PAD_EIM_A27__GPIO_2_21; | 355 | iomux_v3_cfg_t power_key = _MX51_PAD_EIM_A27__GPIO2_21 | |
| 356 | MUX_PAD_CTRL(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP); | ||
| 320 | 357 | ||
| 321 | #if defined(CONFIG_CPU_FREQ_IMX) | 358 | #if defined(CONFIG_CPU_FREQ_IMX) |
| 322 | get_cpu_op = mx51_get_cpu_op; | 359 | get_cpu_op = mx51_get_cpu_op; |
| @@ -328,8 +365,7 @@ static void __init mxc_board_init(void) | |||
| 328 | imx51_add_fec(NULL); | 365 | imx51_add_fec(NULL); |
| 329 | 366 | ||
| 330 | /* Set the PAD settings for the pwr key. */ | 367 | /* Set the PAD settings for the pwr key. */ |
| 331 | power_key.pad_ctrl = MX51_GPIO_PAD_CTRL_2; | 368 | mxc_iomux_v3_setup_pad(power_key); |
| 332 | mxc_iomux_v3_setup_pad(&power_key); | ||
| 333 | imx51_add_gpio_keys(&imx_button_data); | 369 | imx51_add_gpio_keys(&imx_button_data); |
| 334 | 370 | ||
| 335 | imx51_add_imx_i2c(0, &babbage_i2c_data); | 371 | imx51_add_imx_i2c(0, &babbage_i2c_data); |
| @@ -346,11 +382,16 @@ static void __init mxc_board_init(void) | |||
| 346 | gpio_usbh1_active(); | 382 | gpio_usbh1_active(); |
| 347 | mxc_register_device(&mxc_usbh1_device, &usbh1_config); | 383 | mxc_register_device(&mxc_usbh1_device, &usbh1_config); |
| 348 | /* setback USBH1_STP to be function */ | 384 | /* setback USBH1_STP to be function */ |
| 349 | mxc_iomux_v3_setup_pad(&usbh1stp); | 385 | mxc_iomux_v3_setup_pad(usbh1stp); |
| 350 | babbage_usbhub_reset(); | 386 | babbage_usbhub_reset(); |
| 351 | 387 | ||
| 352 | imx51_add_esdhc(0, NULL); | 388 | imx51_add_sdhci_esdhc_imx(0, NULL); |
| 353 | imx51_add_esdhc(1, NULL); | 389 | imx51_add_sdhci_esdhc_imx(1, NULL); |
| 390 | |||
| 391 | spi_register_board_info(mx51_babbage_spi_board_info, | ||
| 392 | ARRAY_SIZE(mx51_babbage_spi_board_info)); | ||
| 393 | imx51_add_ecspi(0, &mx51_babbage_spi_pdata); | ||
| 394 | imx51_add_imx2_wdt(0, NULL); | ||
| 354 | } | 395 | } |
| 355 | 396 | ||
| 356 | static void __init mx51_babbage_timer_init(void) | 397 | static void __init mx51_babbage_timer_init(void) |
diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c index 6e623bda3ee7..b7946f8e8d40 100644 --- a/arch/arm/mach-mx5/board-mx51_efikamx.c +++ b/arch/arm/mach-mx5/board-mx51_efikamx.c | |||
| @@ -18,9 +18,13 @@ | |||
| 18 | #include <linux/platform_device.h> | 18 | #include <linux/platform_device.h> |
| 19 | #include <linux/i2c.h> | 19 | #include <linux/i2c.h> |
| 20 | #include <linux/gpio.h> | 20 | #include <linux/gpio.h> |
| 21 | #include <linux/leds.h> | ||
| 22 | #include <linux/input.h> | ||
| 21 | #include <linux/delay.h> | 23 | #include <linux/delay.h> |
| 22 | #include <linux/io.h> | 24 | #include <linux/io.h> |
| 23 | #include <linux/fsl_devices.h> | 25 | #include <linux/fsl_devices.h> |
| 26 | #include <linux/spi/flash.h> | ||
| 27 | #include <linux/spi/spi.h> | ||
| 24 | 28 | ||
| 25 | #include <mach/common.h> | 29 | #include <mach/common.h> |
| 26 | #include <mach/hardware.h> | 30 | #include <mach/hardware.h> |
| @@ -39,12 +43,81 @@ | |||
| 39 | 43 | ||
| 40 | #define MX51_USB_PLL_DIV_24_MHZ 0x01 | 44 | #define MX51_USB_PLL_DIV_24_MHZ 0x01 |
| 41 | 45 | ||
| 42 | static struct pad_desc mx51efikamx_pads[] = { | 46 | #define EFIKAMX_PCBID0 IMX_GPIO_NR(3, 16) |
| 47 | #define EFIKAMX_PCBID1 IMX_GPIO_NR(3, 17) | ||
| 48 | #define EFIKAMX_PCBID2 IMX_GPIO_NR(3, 11) | ||
| 49 | |||
| 50 | #define EFIKAMX_BLUE_LED IMX_GPIO_NR(3, 13) | ||
| 51 | #define EFIKAMX_GREEN_LED IMX_GPIO_NR(3, 14) | ||
| 52 | #define EFIKAMX_RED_LED IMX_GPIO_NR(3, 15) | ||
| 53 | |||
| 54 | #define EFIKAMX_POWER_KEY IMX_GPIO_NR(2, 31) | ||
| 55 | |||
| 56 | #define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24) | ||
| 57 | #define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25) | ||
| 58 | |||
| 59 | /* board 1.1 doesn't have same reset gpio */ | ||
| 60 | #define EFIKAMX_RESET1_1 IMX_GPIO_NR(3, 2) | ||
| 61 | #define EFIKAMX_RESET IMX_GPIO_NR(1, 4) | ||
| 62 | |||
| 63 | /* the pci ids pin have pull up. they're driven low according to board id */ | ||
| 64 | #define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) | ||
| 65 | #define MX51_PAD_PCBID1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) | ||
| 66 | #define MX51_PAD_PCBID2 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) | ||
| 67 | #define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE) | ||
| 68 | |||
| 69 | static iomux_v3_cfg_t mx51efikamx_pads[] = { | ||
| 43 | /* UART1 */ | 70 | /* UART1 */ |
| 44 | MX51_PAD_UART1_RXD__UART1_RXD, | 71 | MX51_PAD_UART1_RXD__UART1_RXD, |
| 45 | MX51_PAD_UART1_TXD__UART1_TXD, | 72 | MX51_PAD_UART1_TXD__UART1_TXD, |
| 46 | MX51_PAD_UART1_RTS__UART1_RTS, | 73 | MX51_PAD_UART1_RTS__UART1_RTS, |
| 47 | MX51_PAD_UART1_CTS__UART1_CTS, | 74 | MX51_PAD_UART1_CTS__UART1_CTS, |
| 75 | /* board id */ | ||
| 76 | MX51_PAD_PCBID0, | ||
| 77 | MX51_PAD_PCBID1, | ||
| 78 | MX51_PAD_PCBID2, | ||
| 79 | |||
| 80 | /* SD 1 */ | ||
| 81 | MX51_PAD_SD1_CMD__SD1_CMD, | ||
| 82 | MX51_PAD_SD1_CLK__SD1_CLK, | ||
| 83 | MX51_PAD_SD1_DATA0__SD1_DATA0, | ||
| 84 | MX51_PAD_SD1_DATA1__SD1_DATA1, | ||
| 85 | MX51_PAD_SD1_DATA2__SD1_DATA2, | ||
| 86 | MX51_PAD_SD1_DATA3__SD1_DATA3, | ||
| 87 | |||
| 88 | /* SD 2 */ | ||
| 89 | MX51_PAD_SD2_CMD__SD2_CMD, | ||
| 90 | MX51_PAD_SD2_CLK__SD2_CLK, | ||
| 91 | MX51_PAD_SD2_DATA0__SD2_DATA0, | ||
| 92 | MX51_PAD_SD2_DATA1__SD2_DATA1, | ||
| 93 | MX51_PAD_SD2_DATA2__SD2_DATA2, | ||
| 94 | MX51_PAD_SD2_DATA3__SD2_DATA3, | ||
| 95 | |||
| 96 | /* SD/MMC WP/CD */ | ||
| 97 | MX51_PAD_GPIO1_0__SD1_CD, | ||
| 98 | MX51_PAD_GPIO1_1__SD1_WP, | ||
| 99 | MX51_PAD_GPIO1_7__SD2_WP, | ||
| 100 | MX51_PAD_GPIO1_8__SD2_CD, | ||
| 101 | |||
| 102 | /* leds */ | ||
| 103 | MX51_PAD_CSI1_D9__GPIO3_13, | ||
| 104 | MX51_PAD_CSI1_VSYNC__GPIO3_14, | ||
| 105 | MX51_PAD_CSI1_HSYNC__GPIO3_15, | ||
| 106 | |||
| 107 | /* power key */ | ||
| 108 | MX51_PAD_PWRKEY, | ||
| 109 | |||
| 110 | /* spi */ | ||
| 111 | MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, | ||
| 112 | MX51_PAD_CSPI1_MISO__ECSPI1_MISO, | ||
| 113 | MX51_PAD_CSPI1_SS0__GPIO4_24, | ||
| 114 | MX51_PAD_CSPI1_SS1__GPIO4_25, | ||
| 115 | MX51_PAD_CSPI1_RDY__ECSPI1_RDY, | ||
| 116 | MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, | ||
| 117 | |||
| 118 | /* reset */ | ||
| 119 | MX51_PAD_DI1_PIN13__GPIO3_2, | ||
| 120 | MX51_PAD_GPIO1_4__GPIO1_4, | ||
| 48 | }; | 121 | }; |
| 49 | 122 | ||
| 50 | /* Serial ports */ | 123 | /* Serial ports */ |
| @@ -75,6 +148,8 @@ static int initialize_otg_port(struct platform_device *pdev) | |||
| 75 | void __iomem *usb_base; | 148 | void __iomem *usb_base; |
| 76 | void __iomem *usbother_base; | 149 | void __iomem *usbother_base; |
| 77 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); | 150 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); |
| 151 | if (!usb_base) | ||
| 152 | return -ENOMEM; | ||
| 78 | usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET); | 153 | usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET); |
| 79 | 154 | ||
| 80 | /* Set the PHY clock to 19.2MHz */ | 155 | /* Set the PHY clock to 19.2MHz */ |
| @@ -92,12 +167,182 @@ static struct mxc_usbh_platform_data dr_utmi_config = { | |||
| 92 | .flags = MXC_EHCI_INTERNAL_PHY, | 167 | .flags = MXC_EHCI_INTERNAL_PHY, |
| 93 | }; | 168 | }; |
| 94 | 169 | ||
| 170 | /* PCBID2 PCBID1 PCBID0 STATE | ||
| 171 | 1 1 1 ER1:rev1.1 | ||
| 172 | 1 1 0 ER2:rev1.2 | ||
| 173 | 1 0 1 ER3:rev1.3 | ||
| 174 | 1 0 0 ER4:rev1.4 | ||
| 175 | */ | ||
| 176 | static void __init mx51_efikamx_board_id(void) | ||
| 177 | { | ||
| 178 | int id; | ||
| 179 | |||
| 180 | /* things are taking time to settle */ | ||
| 181 | msleep(150); | ||
| 182 | |||
| 183 | gpio_request(EFIKAMX_PCBID0, "pcbid0"); | ||
| 184 | gpio_direction_input(EFIKAMX_PCBID0); | ||
| 185 | gpio_request(EFIKAMX_PCBID1, "pcbid1"); | ||
| 186 | gpio_direction_input(EFIKAMX_PCBID1); | ||
| 187 | gpio_request(EFIKAMX_PCBID2, "pcbid2"); | ||
| 188 | gpio_direction_input(EFIKAMX_PCBID2); | ||
| 189 | |||
| 190 | id = gpio_get_value(EFIKAMX_PCBID0); | ||
| 191 | id |= gpio_get_value(EFIKAMX_PCBID1) << 1; | ||
| 192 | id |= gpio_get_value(EFIKAMX_PCBID2) << 2; | ||
| 193 | |||
| 194 | switch (id) { | ||
| 195 | case 7: | ||
| 196 | system_rev = 0x11; | ||
| 197 | break; | ||
| 198 | case 6: | ||
| 199 | system_rev = 0x12; | ||
| 200 | break; | ||
| 201 | case 5: | ||
| 202 | system_rev = 0x13; | ||
| 203 | break; | ||
| 204 | case 4: | ||
| 205 | system_rev = 0x14; | ||
| 206 | break; | ||
| 207 | default: | ||
| 208 | system_rev = 0x10; | ||
| 209 | break; | ||
| 210 | } | ||
| 211 | |||
| 212 | if ((system_rev == 0x10) | ||
| 213 | || (system_rev == 0x12) | ||
| 214 | || (system_rev == 0x14)) { | ||
| 215 | printk(KERN_WARNING | ||
| 216 | "EfikaMX: Unsupported board revision 1.%u!\n", | ||
| 217 | system_rev & 0xf); | ||
| 218 | } | ||
| 219 | } | ||
| 220 | |||
| 221 | static struct gpio_led mx51_efikamx_leds[] = { | ||
| 222 | { | ||
| 223 | .name = "efikamx:green", | ||
| 224 | .default_trigger = "default-on", | ||
| 225 | .gpio = EFIKAMX_GREEN_LED, | ||
| 226 | }, | ||
| 227 | { | ||
| 228 | .name = "efikamx:red", | ||
| 229 | .default_trigger = "ide-disk", | ||
| 230 | .gpio = EFIKAMX_RED_LED, | ||
| 231 | }, | ||
| 232 | { | ||
| 233 | .name = "efikamx:blue", | ||
| 234 | .default_trigger = "mmc0", | ||
| 235 | .gpio = EFIKAMX_BLUE_LED, | ||
| 236 | }, | ||
| 237 | }; | ||
| 238 | |||
| 239 | static struct gpio_led_platform_data mx51_efikamx_leds_data = { | ||
| 240 | .leds = mx51_efikamx_leds, | ||
| 241 | .num_leds = ARRAY_SIZE(mx51_efikamx_leds), | ||
| 242 | }; | ||
| 243 | |||
| 244 | static struct platform_device mx51_efikamx_leds_device = { | ||
| 245 | .name = "leds-gpio", | ||
| 246 | .id = -1, | ||
| 247 | .dev = { | ||
| 248 | .platform_data = &mx51_efikamx_leds_data, | ||
| 249 | }, | ||
| 250 | }; | ||
| 251 | |||
| 252 | static struct gpio_keys_button mx51_efikamx_powerkey[] = { | ||
| 253 | { | ||
| 254 | .code = KEY_POWER, | ||
| 255 | .gpio = EFIKAMX_POWER_KEY, | ||
| 256 | .type = EV_PWR, | ||
| 257 | .desc = "Power Button (CM)", | ||
| 258 | .wakeup = 1, | ||
| 259 | .debounce_interval = 10, /* ms */ | ||
| 260 | }, | ||
| 261 | }; | ||
| 262 | |||
| 263 | static const struct gpio_keys_platform_data mx51_efikamx_powerkey_data __initconst = { | ||
| 264 | .buttons = mx51_efikamx_powerkey, | ||
| 265 | .nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey), | ||
| 266 | }; | ||
| 267 | |||
| 268 | static struct mtd_partition mx51_efikamx_spi_nor_partitions[] = { | ||
| 269 | { | ||
| 270 | .name = "u-boot", | ||
| 271 | .offset = 0, | ||
| 272 | .size = SZ_256K, | ||
| 273 | }, | ||
| 274 | { | ||
| 275 | .name = "config", | ||
| 276 | .offset = MTDPART_OFS_APPEND, | ||
| 277 | .size = SZ_64K, | ||
| 278 | }, | ||
| 279 | }; | ||
| 280 | |||
| 281 | static struct flash_platform_data mx51_efikamx_spi_flash_data = { | ||
| 282 | .name = "spi_flash", | ||
| 283 | .parts = mx51_efikamx_spi_nor_partitions, | ||
| 284 | .nr_parts = ARRAY_SIZE(mx51_efikamx_spi_nor_partitions), | ||
| 285 | .type = "sst25vf032b", | ||
| 286 | }; | ||
| 287 | |||
| 288 | static struct spi_board_info mx51_efikamx_spi_board_info[] __initdata = { | ||
| 289 | { | ||
| 290 | .modalias = "m25p80", | ||
| 291 | .max_speed_hz = 25000000, | ||
| 292 | .bus_num = 0, | ||
| 293 | .chip_select = 1, | ||
| 294 | .platform_data = &mx51_efikamx_spi_flash_data, | ||
| 295 | .irq = -1, | ||
| 296 | }, | ||
| 297 | }; | ||
| 298 | |||
| 299 | static int mx51_efikamx_spi_cs[] = { | ||
| 300 | EFIKAMX_SPI_CS0, | ||
| 301 | EFIKAMX_SPI_CS1, | ||
| 302 | }; | ||
| 303 | |||
| 304 | static const struct spi_imx_master mx51_efikamx_spi_pdata __initconst = { | ||
| 305 | .chipselect = mx51_efikamx_spi_cs, | ||
| 306 | .num_chipselect = ARRAY_SIZE(mx51_efikamx_spi_cs), | ||
| 307 | }; | ||
| 308 | |||
| 309 | void mx51_efikamx_reset(void) | ||
| 310 | { | ||
| 311 | if (system_rev == 0x11) | ||
| 312 | gpio_direction_output(EFIKAMX_RESET1_1, 0); | ||
| 313 | else | ||
| 314 | gpio_direction_output(EFIKAMX_RESET, 0); | ||
| 315 | } | ||
| 316 | |||
| 95 | static void __init mxc_board_init(void) | 317 | static void __init mxc_board_init(void) |
| 96 | { | 318 | { |
| 97 | mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads, | 319 | mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads, |
| 98 | ARRAY_SIZE(mx51efikamx_pads)); | 320 | ARRAY_SIZE(mx51efikamx_pads)); |
| 321 | mx51_efikamx_board_id(); | ||
| 99 | mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); | 322 | mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); |
| 100 | mxc_init_imx_uart(); | 323 | mxc_init_imx_uart(); |
| 324 | imx51_add_sdhci_esdhc_imx(0, NULL); | ||
| 325 | |||
| 326 | /* on < 1.2 boards both SD controllers are used */ | ||
| 327 | if (system_rev < 0x12) { | ||
| 328 | imx51_add_sdhci_esdhc_imx(1, NULL); | ||
| 329 | mx51_efikamx_leds[2].default_trigger = "mmc1"; | ||
| 330 | } | ||
| 331 | |||
| 332 | platform_device_register(&mx51_efikamx_leds_device); | ||
| 333 | imx51_add_gpio_keys(&mx51_efikamx_powerkey_data); | ||
| 334 | |||
| 335 | spi_register_board_info(mx51_efikamx_spi_board_info, | ||
| 336 | ARRAY_SIZE(mx51_efikamx_spi_board_info)); | ||
| 337 | imx51_add_ecspi(0, &mx51_efikamx_spi_pdata); | ||
| 338 | |||
| 339 | if (system_rev == 0x11) { | ||
| 340 | gpio_request(EFIKAMX_RESET1_1, "reset"); | ||
| 341 | gpio_direction_output(EFIKAMX_RESET1_1, 1); | ||
| 342 | } else { | ||
| 343 | gpio_request(EFIKAMX_RESET, "reset"); | ||
| 344 | gpio_direction_output(EFIKAMX_RESET, 1); | ||
| 345 | } | ||
| 101 | } | 346 | } |
| 102 | 347 | ||
| 103 | static void __init mx51_efikamx_timer_init(void) | 348 | static void __init mx51_efikamx_timer_init(void) |
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c new file mode 100644 index 000000000000..fa97d0d5dd05 --- /dev/null +++ b/arch/arm/mach-mx5/board-mx53_evk.c | |||
| @@ -0,0 +1,84 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org> | ||
| 4 | */ | ||
| 5 | |||
| 6 | /* | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | |||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | |||
| 17 | * You should have received a copy of the GNU General Public License along | ||
| 18 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
| 20 | */ | ||
| 21 | |||
| 22 | #include <linux/init.h> | ||
| 23 | #include <linux/clk.h> | ||
| 24 | #include <mach/common.h> | ||
| 25 | #include <mach/hardware.h> | ||
| 26 | #include <asm/mach-types.h> | ||
| 27 | #include <asm/mach/arch.h> | ||
| 28 | #include <asm/mach/time.h> | ||
| 29 | #include <mach/imx-uart.h> | ||
| 30 | #include <mach/iomux-mx53.h> | ||
| 31 | |||
| 32 | #include "crm_regs.h" | ||
| 33 | #include "devices-imx53.h" | ||
| 34 | |||
| 35 | static iomux_v3_cfg_t mx53_evk_pads[] = { | ||
| 36 | MX53_PAD_CSI0_D10__UART1_TXD, | ||
| 37 | MX53_PAD_CSI0_D11__UART1_RXD, | ||
| 38 | MX53_PAD_ATA_DIOW__UART1_TXD, | ||
| 39 | MX53_PAD_ATA_DMACK__UART1_RXD, | ||
| 40 | |||
| 41 | MX53_PAD_ATA_BUFFER_EN__UART2_RXD, | ||
| 42 | MX53_PAD_ATA_DMARQ__UART2_TXD, | ||
| 43 | MX53_PAD_ATA_DIOR__UART2_RTS, | ||
| 44 | MX53_PAD_ATA_INTRQ__UART2_CTS, | ||
| 45 | |||
| 46 | MX53_PAD_ATA_CS_0__UART3_TXD, | ||
| 47 | MX53_PAD_ATA_CS_1__UART3_RXD, | ||
| 48 | MX53_PAD_ATA_DA_1__UART3_CTS, | ||
| 49 | MX53_PAD_ATA_DA_2__UART3_RTS, | ||
| 50 | }; | ||
| 51 | |||
| 52 | static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = { | ||
| 53 | .flags = IMXUART_HAVE_RTSCTS, | ||
| 54 | }; | ||
| 55 | |||
| 56 | static inline void mx53_evk_init_uart(void) | ||
| 57 | { | ||
| 58 | imx53_add_imx_uart(0, &mx53_evk_uart_pdata); | ||
| 59 | imx53_add_imx_uart(1, &mx53_evk_uart_pdata); | ||
| 60 | imx53_add_imx_uart(2, &mx53_evk_uart_pdata); | ||
| 61 | } | ||
| 62 | |||
| 63 | static void __init mx53_evk_board_init(void) | ||
| 64 | { | ||
| 65 | mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads, | ||
| 66 | ARRAY_SIZE(mx53_evk_pads)); | ||
| 67 | mx53_evk_init_uart(); | ||
| 68 | } | ||
| 69 | |||
| 70 | static void __init mx53_evk_timer_init(void) | ||
| 71 | { | ||
| 72 | mx53_clocks_init(32768, 24000000, 22579200, 0); | ||
| 73 | } | ||
| 74 | |||
| 75 | static struct sys_timer mx53_evk_timer = { | ||
| 76 | .init = mx53_evk_timer_init, | ||
| 77 | }; | ||
| 78 | |||
| 79 | MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board") | ||
| 80 | .map_io = mx53_map_io, | ||
| 81 | .init_irq = mx53_init_irq, | ||
| 82 | .init_machine = mx53_evk_board_init, | ||
| 83 | .timer = &mx53_evk_timer, | ||
| 84 | MACHINE_END | ||
diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51-mx53.c index 8ac36d882927..785e1a336183 100644 --- a/arch/arm/mach-mx5/clock-mx51.c +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c | |||
| @@ -14,8 +14,8 @@ | |||
| 14 | #include <linux/delay.h> | 14 | #include <linux/delay.h> |
| 15 | #include <linux/clk.h> | 15 | #include <linux/clk.h> |
| 16 | #include <linux/io.h> | 16 | #include <linux/io.h> |
| 17 | #include <linux/clkdev.h> | ||
| 17 | 18 | ||
| 18 | #include <asm/clkdev.h> | ||
| 19 | #include <asm/div64.h> | 19 | #include <asm/div64.h> |
| 20 | 20 | ||
| 21 | #include <mach/hardware.h> | 21 | #include <mach/hardware.h> |
| @@ -33,11 +33,15 @@ static struct clk pll1_main_clk; | |||
| 33 | static struct clk pll1_sw_clk; | 33 | static struct clk pll1_sw_clk; |
| 34 | static struct clk pll2_sw_clk; | 34 | static struct clk pll2_sw_clk; |
| 35 | static struct clk pll3_sw_clk; | 35 | static struct clk pll3_sw_clk; |
| 36 | static struct clk mx53_pll4_sw_clk; | ||
| 36 | static struct clk lp_apm_clk; | 37 | static struct clk lp_apm_clk; |
| 37 | static struct clk periph_apm_clk; | 38 | static struct clk periph_apm_clk; |
| 38 | static struct clk ahb_clk; | 39 | static struct clk ahb_clk; |
| 39 | static struct clk ipg_clk; | 40 | static struct clk ipg_clk; |
| 40 | static struct clk usboh3_clk; | 41 | static struct clk usboh3_clk; |
| 42 | static struct clk emi_fast_clk; | ||
| 43 | static struct clk ipu_clk; | ||
| 44 | static struct clk mipi_hsc1_clk; | ||
| 41 | 45 | ||
| 42 | #define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ | 46 | #define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ |
| 43 | 47 | ||
| @@ -123,7 +127,7 @@ static inline u32 _get_mux(struct clk *parent, struct clk *m0, | |||
| 123 | return -EINVAL; | 127 | return -EINVAL; |
| 124 | } | 128 | } |
| 125 | 129 | ||
| 126 | static inline void __iomem *_get_pll_base(struct clk *pll) | 130 | static inline void __iomem *_mx51_get_pll_base(struct clk *pll) |
| 127 | { | 131 | { |
| 128 | if (pll == &pll1_main_clk) | 132 | if (pll == &pll1_main_clk) |
| 129 | return MX51_DPLL1_BASE; | 133 | return MX51_DPLL1_BASE; |
| @@ -137,6 +141,30 @@ static inline void __iomem *_get_pll_base(struct clk *pll) | |||
| 137 | return NULL; | 141 | return NULL; |
| 138 | } | 142 | } |
| 139 | 143 | ||
| 144 | static inline void __iomem *_mx53_get_pll_base(struct clk *pll) | ||
| 145 | { | ||
| 146 | if (pll == &pll1_main_clk) | ||
| 147 | return MX53_DPLL1_BASE; | ||
| 148 | else if (pll == &pll2_sw_clk) | ||
| 149 | return MX53_DPLL2_BASE; | ||
| 150 | else if (pll == &pll3_sw_clk) | ||
| 151 | return MX53_DPLL3_BASE; | ||
| 152 | else if (pll == &mx53_pll4_sw_clk) | ||
| 153 | return MX53_DPLL4_BASE; | ||
| 154 | else | ||
| 155 | BUG(); | ||
| 156 | |||
| 157 | return NULL; | ||
| 158 | } | ||
| 159 | |||
| 160 | static inline void __iomem *_get_pll_base(struct clk *pll) | ||
| 161 | { | ||
| 162 | if (cpu_is_mx51()) | ||
| 163 | return _mx51_get_pll_base(pll); | ||
| 164 | else | ||
| 165 | return _mx53_get_pll_base(pll); | ||
| 166 | } | ||
| 167 | |||
| 140 | static unsigned long clk_pll_get_rate(struct clk *clk) | 168 | static unsigned long clk_pll_get_rate(struct clk *clk) |
| 141 | { | 169 | { |
| 142 | long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; | 170 | long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; |
| @@ -514,7 +542,10 @@ static int _clk_max_enable(struct clk *clk) | |||
| 514 | 542 | ||
| 515 | /* Handshake with MAX when LPM is entered. */ | 543 | /* Handshake with MAX when LPM is entered. */ |
| 516 | reg = __raw_readl(MXC_CCM_CLPCR); | 544 | reg = __raw_readl(MXC_CCM_CLPCR); |
| 517 | reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; | 545 | if (cpu_is_mx51()) |
| 546 | reg &= ~MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS; | ||
| 547 | else if (cpu_is_mx53()) | ||
| 548 | reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS; | ||
| 518 | __raw_writel(reg, MXC_CCM_CLPCR); | 549 | __raw_writel(reg, MXC_CCM_CLPCR); |
| 519 | 550 | ||
| 520 | return 0; | 551 | return 0; |
| @@ -528,7 +559,10 @@ static void _clk_max_disable(struct clk *clk) | |||
| 528 | 559 | ||
| 529 | /* No Handshake with MAX when LPM is entered as its disabled. */ | 560 | /* No Handshake with MAX when LPM is entered as its disabled. */ |
| 530 | reg = __raw_readl(MXC_CCM_CLPCR); | 561 | reg = __raw_readl(MXC_CCM_CLPCR); |
| 531 | reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; | 562 | if (cpu_is_mx51()) |
| 563 | reg |= MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS; | ||
| 564 | else if (cpu_is_mx53()) | ||
| 565 | reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS; | ||
| 532 | __raw_writel(reg, MXC_CCM_CLPCR); | 566 | __raw_writel(reg, MXC_CCM_CLPCR); |
| 533 | } | 567 | } |
| 534 | 568 | ||
| @@ -679,6 +713,19 @@ static unsigned long clk_emi_slow_get_rate(struct clk *clk) | |||
| 679 | return clk_get_rate(clk->parent) / div; | 713 | return clk_get_rate(clk->parent) / div; |
| 680 | } | 714 | } |
| 681 | 715 | ||
| 716 | static unsigned long _clk_ddr_hf_get_rate(struct clk *clk) | ||
| 717 | { | ||
| 718 | unsigned long rate; | ||
| 719 | u32 reg, div; | ||
| 720 | |||
| 721 | reg = __raw_readl(MXC_CCM_CBCDR); | ||
| 722 | div = ((reg & MXC_CCM_CBCDR_DDR_PODF_MASK) >> | ||
| 723 | MXC_CCM_CBCDR_DDR_PODF_OFFSET) + 1; | ||
| 724 | rate = clk_get_rate(clk->parent) / div; | ||
| 725 | |||
| 726 | return rate; | ||
| 727 | } | ||
| 728 | |||
| 682 | /* External high frequency clock */ | 729 | /* External high frequency clock */ |
| 683 | static struct clk ckih_clk = { | 730 | static struct clk ckih_clk = { |
| 684 | .get_rate = get_high_reference_clock_rate, | 731 | .get_rate = get_high_reference_clock_rate, |
| @@ -739,6 +786,14 @@ static struct clk pll3_sw_clk = { | |||
| 739 | .disable = _clk_pll_disable, | 786 | .disable = _clk_pll_disable, |
| 740 | }; | 787 | }; |
| 741 | 788 | ||
| 789 | /* PLL4 SW supplies to LVDS Display Bridge(LDB) */ | ||
| 790 | static struct clk mx53_pll4_sw_clk = { | ||
| 791 | .parent = &osc_clk, | ||
| 792 | .set_rate = _clk_pll_set_rate, | ||
| 793 | .enable = _clk_pll_enable, | ||
| 794 | .disable = _clk_pll_disable, | ||
| 795 | }; | ||
| 796 | |||
| 742 | /* Low-power Audio Playback Mode clock */ | 797 | /* Low-power Audio Playback Mode clock */ |
| 743 | static struct clk lp_apm_clk = { | 798 | static struct clk lp_apm_clk = { |
| 744 | .parent = &osc_clk, | 799 | .parent = &osc_clk, |
| @@ -763,6 +818,12 @@ static struct clk ahb_clk = { | |||
| 763 | .round_rate = _clk_ahb_round_rate, | 818 | .round_rate = _clk_ahb_round_rate, |
| 764 | }; | 819 | }; |
| 765 | 820 | ||
| 821 | static struct clk iim_clk = { | ||
| 822 | .parent = &ipg_clk, | ||
| 823 | .enable_reg = MXC_CCM_CCGR0, | ||
| 824 | .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET, | ||
| 825 | }; | ||
| 826 | |||
| 766 | /* Main IP interface clock for access to registers */ | 827 | /* Main IP interface clock for access to registers */ |
| 767 | static struct clk ipg_clk = { | 828 | static struct clk ipg_clk = { |
| 768 | .parent = &ahb_clk, | 829 | .parent = &ahb_clk, |
| @@ -810,6 +871,10 @@ static struct clk kpp_clk = { | |||
| 810 | .id = 0, | 871 | .id = 0, |
| 811 | }; | 872 | }; |
| 812 | 873 | ||
| 874 | static struct clk dummy_clk = { | ||
| 875 | .id = 0, | ||
| 876 | }; | ||
| 877 | |||
| 813 | static struct clk emi_slow_clk = { | 878 | static struct clk emi_slow_clk = { |
| 814 | .parent = &pll2_sw_clk, | 879 | .parent = &pll2_sw_clk, |
| 815 | .enable_reg = MXC_CCM_CCGR5, | 880 | .enable_reg = MXC_CCM_CCGR5, |
| @@ -819,6 +884,109 @@ static struct clk emi_slow_clk = { | |||
| 819 | .get_rate = clk_emi_slow_get_rate, | 884 | .get_rate = clk_emi_slow_get_rate, |
| 820 | }; | 885 | }; |
| 821 | 886 | ||
| 887 | static int clk_ipu_enable(struct clk *clk) | ||
| 888 | { | ||
| 889 | u32 reg; | ||
| 890 | |||
| 891 | _clk_ccgr_enable(clk); | ||
| 892 | |||
| 893 | /* Enable handshake with IPU when certain clock rates are changed */ | ||
| 894 | reg = __raw_readl(MXC_CCM_CCDR); | ||
| 895 | reg &= ~MXC_CCM_CCDR_IPU_HS_MASK; | ||
| 896 | __raw_writel(reg, MXC_CCM_CCDR); | ||
| 897 | |||
| 898 | /* Enable handshake with IPU when LPM is entered */ | ||
| 899 | reg = __raw_readl(MXC_CCM_CLPCR); | ||
| 900 | reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; | ||
| 901 | __raw_writel(reg, MXC_CCM_CLPCR); | ||
| 902 | |||
| 903 | return 0; | ||
| 904 | } | ||
| 905 | |||
| 906 | static void clk_ipu_disable(struct clk *clk) | ||
| 907 | { | ||
| 908 | u32 reg; | ||
| 909 | |||
| 910 | _clk_ccgr_disable(clk); | ||
| 911 | |||
| 912 | /* Disable handshake with IPU whe dividers are changed */ | ||
| 913 | reg = __raw_readl(MXC_CCM_CCDR); | ||
| 914 | reg |= MXC_CCM_CCDR_IPU_HS_MASK; | ||
| 915 | __raw_writel(reg, MXC_CCM_CCDR); | ||
| 916 | |||
| 917 | /* Disable handshake with IPU when LPM is entered */ | ||
| 918 | reg = __raw_readl(MXC_CCM_CLPCR); | ||
| 919 | reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; | ||
| 920 | __raw_writel(reg, MXC_CCM_CLPCR); | ||
| 921 | } | ||
| 922 | |||
| 923 | static struct clk ahbmux1_clk = { | ||
| 924 | .parent = &ahb_clk, | ||
| 925 | .secondary = &ahb_max_clk, | ||
| 926 | .enable_reg = MXC_CCM_CCGR0, | ||
| 927 | .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, | ||
| 928 | .enable = _clk_ccgr_enable, | ||
| 929 | .disable = _clk_ccgr_disable_inwait, | ||
| 930 | }; | ||
| 931 | |||
| 932 | static struct clk ipu_sec_clk = { | ||
| 933 | .parent = &emi_fast_clk, | ||
| 934 | .secondary = &ahbmux1_clk, | ||
| 935 | }; | ||
| 936 | |||
| 937 | static struct clk ddr_hf_clk = { | ||
| 938 | .parent = &pll1_sw_clk, | ||
| 939 | .get_rate = _clk_ddr_hf_get_rate, | ||
| 940 | }; | ||
| 941 | |||
| 942 | static struct clk ddr_clk = { | ||
| 943 | .parent = &ddr_hf_clk, | ||
| 944 | }; | ||
| 945 | |||
| 946 | /* clock definitions for MIPI HSC unit which has been removed | ||
| 947 | * from documentation, but not from hardware | ||
| 948 | */ | ||
| 949 | static int _clk_hsc_enable(struct clk *clk) | ||
| 950 | { | ||
| 951 | u32 reg; | ||
| 952 | |||
| 953 | _clk_ccgr_enable(clk); | ||
| 954 | /* Handshake with IPU when certain clock rates are changed. */ | ||
| 955 | reg = __raw_readl(MXC_CCM_CCDR); | ||
| 956 | reg &= ~MXC_CCM_CCDR_HSC_HS_MASK; | ||
| 957 | __raw_writel(reg, MXC_CCM_CCDR); | ||
| 958 | |||
| 959 | reg = __raw_readl(MXC_CCM_CLPCR); | ||
| 960 | reg &= ~MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS; | ||
| 961 | __raw_writel(reg, MXC_CCM_CLPCR); | ||
| 962 | |||
| 963 | return 0; | ||
| 964 | } | ||
| 965 | |||
| 966 | static void _clk_hsc_disable(struct clk *clk) | ||
| 967 | { | ||
| 968 | u32 reg; | ||
| 969 | |||
| 970 | _clk_ccgr_disable(clk); | ||
| 971 | /* No handshake with HSC as its not enabled. */ | ||
| 972 | reg = __raw_readl(MXC_CCM_CCDR); | ||
| 973 | reg |= MXC_CCM_CCDR_HSC_HS_MASK; | ||
| 974 | __raw_writel(reg, MXC_CCM_CCDR); | ||
| 975 | |||
| 976 | reg = __raw_readl(MXC_CCM_CLPCR); | ||
| 977 | reg |= MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS; | ||
| 978 | __raw_writel(reg, MXC_CCM_CLPCR); | ||
| 979 | } | ||
| 980 | |||
| 981 | static struct clk mipi_hsp_clk = { | ||
| 982 | .parent = &ipu_clk, | ||
| 983 | .enable_reg = MXC_CCM_CCGR4, | ||
| 984 | .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET, | ||
| 985 | .enable = _clk_hsc_enable, | ||
| 986 | .disable = _clk_hsc_disable, | ||
| 987 | .secondary = &mipi_hsc1_clk, | ||
| 988 | }; | ||
| 989 | |||
| 822 | #define DEFINE_CLOCK_CCGR(name, i, er, es, pfx, p, s) \ | 990 | #define DEFINE_CLOCK_CCGR(name, i, er, es, pfx, p, s) \ |
| 823 | static struct clk name = { \ | 991 | static struct clk name = { \ |
| 824 | .id = i, \ | 992 | .id = i, \ |
| @@ -927,6 +1095,41 @@ static struct clk usboh3_clk = { | |||
| 927 | .parent = &pll2_sw_clk, | 1095 | .parent = &pll2_sw_clk, |
| 928 | .get_rate = clk_usboh3_get_rate, | 1096 | .get_rate = clk_usboh3_get_rate, |
| 929 | .set_parent = clk_usboh3_set_parent, | 1097 | .set_parent = clk_usboh3_set_parent, |
| 1098 | .enable = _clk_ccgr_enable, | ||
| 1099 | .disable = _clk_ccgr_disable, | ||
| 1100 | .enable_reg = MXC_CCM_CCGR2, | ||
| 1101 | .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET, | ||
| 1102 | }; | ||
| 1103 | |||
| 1104 | static struct clk usb_ahb_clk = { | ||
| 1105 | .parent = &ipg_clk, | ||
| 1106 | .enable = _clk_ccgr_enable, | ||
| 1107 | .disable = _clk_ccgr_disable, | ||
| 1108 | .enable_reg = MXC_CCM_CCGR2, | ||
| 1109 | .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, | ||
| 1110 | }; | ||
| 1111 | |||
| 1112 | static int clk_usb_phy1_set_parent(struct clk *clk, struct clk *parent) | ||
| 1113 | { | ||
| 1114 | u32 reg; | ||
| 1115 | |||
| 1116 | reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL; | ||
| 1117 | |||
| 1118 | if (parent == &pll3_sw_clk) | ||
| 1119 | reg |= 1 << MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET; | ||
| 1120 | |||
| 1121 | __raw_writel(reg, MXC_CCM_CSCMR1); | ||
| 1122 | |||
| 1123 | return 0; | ||
| 1124 | } | ||
| 1125 | |||
| 1126 | static struct clk usb_phy1_clk = { | ||
| 1127 | .parent = &pll3_sw_clk, | ||
| 1128 | .set_parent = clk_usb_phy1_set_parent, | ||
| 1129 | .enable = _clk_ccgr_enable, | ||
| 1130 | .enable_reg = MXC_CCM_CCGR2, | ||
| 1131 | .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET, | ||
| 1132 | .disable = _clk_ccgr_disable, | ||
| 930 | }; | 1133 | }; |
| 931 | 1134 | ||
| 932 | /* eCSPI */ | 1135 | /* eCSPI */ |
| @@ -1013,6 +1216,10 @@ DEFINE_CLOCK(ssi2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG10_OFFSET, | |||
| 1013 | NULL, NULL, &ipg_clk, NULL); | 1216 | NULL, NULL, &ipg_clk, NULL); |
| 1014 | DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET, | 1217 | DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET, |
| 1015 | NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk); | 1218 | NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk); |
| 1219 | DEFINE_CLOCK(ssi3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG12_OFFSET, | ||
| 1220 | NULL, NULL, &ipg_clk, NULL); | ||
| 1221 | DEFINE_CLOCK(ssi3_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG13_OFFSET, | ||
| 1222 | NULL, NULL, &pll3_sw_clk, &ssi3_ipg_clk); | ||
| 1016 | 1223 | ||
| 1017 | /* eCSPI */ | 1224 | /* eCSPI */ |
| 1018 | DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET, | 1225 | DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET, |
| @@ -1046,6 +1253,23 @@ DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET, | |||
| 1046 | DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET, | 1253 | DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET, |
| 1047 | clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk); | 1254 | clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk); |
| 1048 | 1255 | ||
| 1256 | DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk); | ||
| 1257 | DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk); | ||
| 1258 | DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk); | ||
| 1259 | |||
| 1260 | /* IPU */ | ||
| 1261 | DEFINE_CLOCK_FULL(ipu_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG5_OFFSET, | ||
| 1262 | NULL, NULL, clk_ipu_enable, clk_ipu_disable, &ahb_clk, &ipu_sec_clk); | ||
| 1263 | |||
| 1264 | DEFINE_CLOCK_FULL(emi_fast_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG7_OFFSET, | ||
| 1265 | NULL, NULL, _clk_ccgr_enable, _clk_ccgr_disable_inwait, | ||
| 1266 | &ddr_clk, NULL); | ||
| 1267 | |||
| 1268 | DEFINE_CLOCK(ipu_di0_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG5_OFFSET, | ||
| 1269 | NULL, NULL, &pll3_sw_clk, NULL); | ||
| 1270 | DEFINE_CLOCK(ipu_di1_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG6_OFFSET, | ||
| 1271 | NULL, NULL, &pll3_sw_clk, NULL); | ||
| 1272 | |||
| 1049 | #define _REGISTER_CLOCK(d, n, c) \ | 1273 | #define _REGISTER_CLOCK(d, n, c) \ |
| 1050 | { \ | 1274 | { \ |
| 1051 | .dev_id = d, \ | 1275 | .dev_id = d, \ |
| @@ -1053,7 +1277,7 @@ DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET, | |||
| 1053 | .clk = &c, \ | 1277 | .clk = &c, \ |
| 1054 | }, | 1278 | }, |
| 1055 | 1279 | ||
| 1056 | static struct clk_lookup lookups[] = { | 1280 | static struct clk_lookup mx51_lookups[] = { |
| 1057 | _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) | 1281 | _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) |
| 1058 | _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) | 1282 | _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) |
| 1059 | _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) | 1283 | _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) |
| @@ -1063,15 +1287,19 @@ static struct clk_lookup lookups[] = { | |||
| 1063 | _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) | 1287 | _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) |
| 1064 | _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk) | 1288 | _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk) |
| 1065 | _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk) | 1289 | _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk) |
| 1066 | _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", ahb_clk) | 1290 | _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_ahb_clk) |
| 1291 | _REGISTER_CLOCK("mxc-ehci.0", "usb_phy1", usb_phy1_clk) | ||
| 1067 | _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk) | 1292 | _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk) |
| 1068 | _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk) | 1293 | _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_ahb_clk) |
| 1294 | _REGISTER_CLOCK("mxc-ehci.2", "usb", usboh3_clk) | ||
| 1295 | _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_ahb_clk) | ||
| 1069 | _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk) | 1296 | _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk) |
| 1070 | _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk) | 1297 | _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk) |
| 1071 | _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk) | 1298 | _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk) |
| 1072 | _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk) | 1299 | _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk) |
| 1073 | _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) | 1300 | _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) |
| 1074 | _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) | 1301 | _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) |
| 1302 | _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk) | ||
| 1075 | _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk) | 1303 | _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk) |
| 1076 | _REGISTER_CLOCK(NULL, "ckih", ckih_clk) | 1304 | _REGISTER_CLOCK(NULL, "ckih", ckih_clk) |
| 1077 | _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk) | 1305 | _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk) |
| @@ -1082,6 +1310,22 @@ static struct clk_lookup lookups[] = { | |||
| 1082 | _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk) | 1310 | _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk) |
| 1083 | _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk) | 1311 | _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk) |
| 1084 | _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk) | 1312 | _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk) |
| 1313 | _REGISTER_CLOCK(NULL, "iim_clk", iim_clk) | ||
| 1314 | _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk) | ||
| 1315 | _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk) | ||
| 1316 | _REGISTER_CLOCK(NULL, "mipi_hsp", mipi_hsp_clk) | ||
| 1317 | _REGISTER_CLOCK("imx-ipuv3", NULL, ipu_clk) | ||
| 1318 | _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk) | ||
| 1319 | _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk) | ||
| 1320 | }; | ||
| 1321 | |||
| 1322 | static struct clk_lookup mx53_lookups[] = { | ||
| 1323 | _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) | ||
| 1324 | _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) | ||
| 1325 | _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) | ||
| 1326 | _REGISTER_CLOCK(NULL, "gpt", gpt_clk) | ||
| 1327 | _REGISTER_CLOCK("fec.0", NULL, fec_clk) | ||
| 1328 | _REGISTER_CLOCK(NULL, "iim_clk", iim_clk) | ||
| 1085 | }; | 1329 | }; |
| 1086 | 1330 | ||
| 1087 | static void clk_tree_init(void) | 1331 | static void clk_tree_init(void) |
| @@ -1114,14 +1358,22 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, | |||
| 1114 | ckih2_reference = ckih2; | 1358 | ckih2_reference = ckih2; |
| 1115 | oscillator_reference = osc; | 1359 | oscillator_reference = osc; |
| 1116 | 1360 | ||
| 1117 | for (i = 0; i < ARRAY_SIZE(lookups); i++) | 1361 | for (i = 0; i < ARRAY_SIZE(mx51_lookups); i++) |
| 1118 | clkdev_add(&lookups[i]); | 1362 | clkdev_add(&mx51_lookups[i]); |
| 1119 | 1363 | ||
| 1120 | clk_tree_init(); | 1364 | clk_tree_init(); |
| 1121 | 1365 | ||
| 1366 | clk_set_parent(&uart_root_clk, &pll3_sw_clk); | ||
| 1122 | clk_enable(&cpu_clk); | 1367 | clk_enable(&cpu_clk); |
| 1123 | clk_enable(&main_bus_clk); | 1368 | clk_enable(&main_bus_clk); |
| 1124 | 1369 | ||
| 1370 | clk_enable(&iim_clk); | ||
| 1371 | mx51_revision(); | ||
| 1372 | clk_disable(&iim_clk); | ||
| 1373 | |||
| 1374 | /* move usb_phy_clk to 24MHz */ | ||
| 1375 | clk_set_parent(&usb_phy1_clk, &osc_clk); | ||
| 1376 | |||
| 1125 | /* set the usboh3_clk parent to pll2_sw_clk */ | 1377 | /* set the usboh3_clk parent to pll2_sw_clk */ |
| 1126 | clk_set_parent(&usboh3_clk, &pll2_sw_clk); | 1378 | clk_set_parent(&usboh3_clk, &pll2_sw_clk); |
| 1127 | 1379 | ||
| @@ -1138,3 +1390,31 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, | |||
| 1138 | MX51_MXC_INT_GPT); | 1390 | MX51_MXC_INT_GPT); |
| 1139 | return 0; | 1391 | return 0; |
| 1140 | } | 1392 | } |
| 1393 | |||
| 1394 | int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, | ||
| 1395 | unsigned long ckih1, unsigned long ckih2) | ||
| 1396 | { | ||
| 1397 | int i; | ||
| 1398 | |||
| 1399 | external_low_reference = ckil; | ||
| 1400 | external_high_reference = ckih1; | ||
| 1401 | ckih2_reference = ckih2; | ||
| 1402 | oscillator_reference = osc; | ||
| 1403 | |||
| 1404 | for (i = 0; i < ARRAY_SIZE(mx53_lookups); i++) | ||
| 1405 | clkdev_add(&mx53_lookups[i]); | ||
| 1406 | |||
| 1407 | clk_tree_init(); | ||
| 1408 | |||
| 1409 | clk_enable(&cpu_clk); | ||
| 1410 | clk_enable(&main_bus_clk); | ||
| 1411 | |||
| 1412 | clk_enable(&iim_clk); | ||
| 1413 | mx53_revision(); | ||
| 1414 | clk_disable(&iim_clk); | ||
| 1415 | |||
| 1416 | /* System timer */ | ||
| 1417 | mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), | ||
| 1418 | MX53_INT_GPT); | ||
| 1419 | return 0; | ||
| 1420 | } | ||
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c index eaacb6e9b5d0..d40671da4372 100644 --- a/arch/arm/mach-mx5/cpu.c +++ b/arch/arm/mach-mx5/cpu.c | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. | 2 | * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. |
| 3 | * | 3 | * |
| 4 | * The code contained herein is licensed under the GNU General Public | 4 | * The code contained herein is licensed under the GNU General Public |
| 5 | * License. You may obtain a copy of the GNU General Public License | 5 | * License. You may obtain a copy of the GNU General Public License |
| @@ -20,37 +20,18 @@ | |||
| 20 | 20 | ||
| 21 | static int cpu_silicon_rev = -1; | 21 | static int cpu_silicon_rev = -1; |
| 22 | 22 | ||
| 23 | #define SI_REV 0x48 | 23 | #define IIM_SREV 0x24 |
| 24 | 24 | ||
| 25 | static void query_silicon_parameter(void) | 25 | static int get_mx51_srev(void) |
| 26 | { | 26 | { |
| 27 | void __iomem *rom = ioremap(MX51_IROM_BASE_ADDR, MX51_IROM_SIZE); | 27 | void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR); |
| 28 | u32 rev; | 28 | u32 rev = readl(iim_base + IIM_SREV) & 0xff; |
| 29 | 29 | ||
| 30 | if (!rom) { | 30 | if (rev == 0x0) |
| 31 | cpu_silicon_rev = -EINVAL; | 31 | return IMX_CHIP_REVISION_2_0; |
| 32 | return; | 32 | else if (rev == 0x10) |
| 33 | } | 33 | return IMX_CHIP_REVISION_3_0; |
| 34 | 34 | return 0; | |
| 35 | rev = readl(rom + SI_REV); | ||
| 36 | switch (rev) { | ||
| 37 | case 0x1: | ||
| 38 | cpu_silicon_rev = MX51_CHIP_REV_1_0; | ||
| 39 | break; | ||
| 40 | case 0x2: | ||
| 41 | cpu_silicon_rev = MX51_CHIP_REV_1_1; | ||
| 42 | break; | ||
| 43 | case 0x10: | ||
| 44 | cpu_silicon_rev = MX51_CHIP_REV_2_0; | ||
| 45 | break; | ||
| 46 | case 0x20: | ||
| 47 | cpu_silicon_rev = MX51_CHIP_REV_3_0; | ||
| 48 | break; | ||
| 49 | default: | ||
| 50 | cpu_silicon_rev = 0; | ||
| 51 | } | ||
| 52 | |||
| 53 | iounmap(rom); | ||
| 54 | } | 35 | } |
| 55 | 36 | ||
| 56 | /* | 37 | /* |
| @@ -64,7 +45,7 @@ int mx51_revision(void) | |||
| 64 | return -EINVAL; | 45 | return -EINVAL; |
| 65 | 46 | ||
| 66 | if (cpu_silicon_rev == -1) | 47 | if (cpu_silicon_rev == -1) |
| 67 | query_silicon_parameter(); | 48 | cpu_silicon_rev = get_mx51_srev(); |
| 68 | 49 | ||
| 69 | return cpu_silicon_rev; | 50 | return cpu_silicon_rev; |
| 70 | } | 51 | } |
| @@ -79,7 +60,10 @@ EXPORT_SYMBOL(mx51_revision); | |||
| 79 | */ | 60 | */ |
| 80 | static int __init mx51_neon_fixup(void) | 61 | static int __init mx51_neon_fixup(void) |
| 81 | { | 62 | { |
| 82 | if (mx51_revision() < MX51_CHIP_REV_3_0 && (elf_hwcap & HWCAP_NEON)) { | 63 | if (!cpu_is_mx51()) |
| 64 | return 0; | ||
| 65 | |||
| 66 | if (mx51_revision() < IMX_CHIP_REVISION_3_0 && (elf_hwcap & HWCAP_NEON)) { | ||
| 83 | elf_hwcap &= ~HWCAP_NEON; | 67 | elf_hwcap &= ~HWCAP_NEON; |
| 84 | pr_info("Turning off NEON support, detected broken NEON implementation\n"); | 68 | pr_info("Turning off NEON support, detected broken NEON implementation\n"); |
| 85 | } | 69 | } |
| @@ -89,29 +73,65 @@ static int __init mx51_neon_fixup(void) | |||
| 89 | late_initcall(mx51_neon_fixup); | 73 | late_initcall(mx51_neon_fixup); |
| 90 | #endif | 74 | #endif |
| 91 | 75 | ||
| 76 | static int get_mx53_srev(void) | ||
| 77 | { | ||
| 78 | void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR); | ||
| 79 | u32 rev = readl(iim_base + IIM_SREV) & 0xff; | ||
| 80 | |||
| 81 | if (rev == 0x0) | ||
| 82 | return IMX_CHIP_REVISION_1_0; | ||
| 83 | else if (rev == 0x10) | ||
| 84 | return IMX_CHIP_REVISION_2_0; | ||
| 85 | return 0; | ||
| 86 | } | ||
| 87 | |||
| 88 | /* | ||
| 89 | * Returns: | ||
| 90 | * the silicon revision of the cpu | ||
| 91 | * -EINVAL - not a mx53 | ||
| 92 | */ | ||
| 93 | int mx53_revision(void) | ||
| 94 | { | ||
| 95 | if (!cpu_is_mx53()) | ||
| 96 | return -EINVAL; | ||
| 97 | |||
| 98 | if (cpu_silicon_rev == -1) | ||
| 99 | cpu_silicon_rev = get_mx53_srev(); | ||
| 100 | |||
| 101 | return cpu_silicon_rev; | ||
| 102 | } | ||
| 103 | EXPORT_SYMBOL(mx53_revision); | ||
| 104 | |||
| 92 | static int __init post_cpu_init(void) | 105 | static int __init post_cpu_init(void) |
| 93 | { | 106 | { |
| 94 | unsigned int reg; | 107 | unsigned int reg; |
| 95 | void __iomem *base; | 108 | void __iomem *base; |
| 96 | 109 | ||
| 97 | if (!cpu_is_mx51()) | 110 | if (cpu_is_mx51() || cpu_is_mx53()) { |
| 98 | return 0; | 111 | if (cpu_is_mx51()) |
| 99 | 112 | base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR); | |
| 100 | base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR); | 113 | else |
| 101 | __raw_writel(0x0, base + 0x40); | 114 | base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR); |
| 102 | __raw_writel(0x0, base + 0x44); | 115 | |
| 103 | __raw_writel(0x0, base + 0x48); | 116 | __raw_writel(0x0, base + 0x40); |
| 104 | __raw_writel(0x0, base + 0x4C); | 117 | __raw_writel(0x0, base + 0x44); |
| 105 | reg = __raw_readl(base + 0x50) & 0x00FFFFFF; | 118 | __raw_writel(0x0, base + 0x48); |
| 106 | __raw_writel(reg, base + 0x50); | 119 | __raw_writel(0x0, base + 0x4C); |
| 107 | 120 | reg = __raw_readl(base + 0x50) & 0x00FFFFFF; | |
| 108 | base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR); | 121 | __raw_writel(reg, base + 0x50); |
| 109 | __raw_writel(0x0, base + 0x40); | 122 | |
| 110 | __raw_writel(0x0, base + 0x44); | 123 | if (cpu_is_mx51()) |
| 111 | __raw_writel(0x0, base + 0x48); | 124 | base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR); |
| 112 | __raw_writel(0x0, base + 0x4C); | 125 | else |
| 113 | reg = __raw_readl(base + 0x50) & 0x00FFFFFF; | 126 | base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR); |
| 114 | __raw_writel(reg, base + 0x50); | 127 | |
| 128 | __raw_writel(0x0, base + 0x40); | ||
| 129 | __raw_writel(0x0, base + 0x44); | ||
| 130 | __raw_writel(0x0, base + 0x48); | ||
| 131 | __raw_writel(0x0, base + 0x4C); | ||
| 132 | reg = __raw_readl(base + 0x50) & 0x00FFFFFF; | ||
| 133 | __raw_writel(reg, base + 0x50); | ||
| 134 | } | ||
| 115 | 135 | ||
| 116 | return 0; | 136 | return 0; |
| 117 | } | 137 | } |
diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h index c776b9af0624..b462c22f53d8 100644 --- a/arch/arm/mach-mx5/crm_regs.h +++ b/arch/arm/mach-mx5/crm_regs.h | |||
| @@ -18,6 +18,13 @@ | |||
| 18 | #define MX51_CORTEXA8_BASE MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR) | 18 | #define MX51_CORTEXA8_BASE MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR) |
| 19 | #define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR) | 19 | #define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR) |
| 20 | 20 | ||
| 21 | /*MX53*/ | ||
| 22 | #define MX53_CCM_BASE MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR) | ||
| 23 | #define MX53_DPLL1_BASE MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR) | ||
| 24 | #define MX53_DPLL2_BASE MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR) | ||
| 25 | #define MX53_DPLL3_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR) | ||
| 26 | #define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR) | ||
| 27 | |||
| 21 | /* PLL Register Offsets */ | 28 | /* PLL Register Offsets */ |
| 22 | #define MXC_PLL_DP_CTL 0x00 | 29 | #define MXC_PLL_DP_CTL 0x00 |
| 23 | #define MXC_PLL_DP_CONFIG 0x04 | 30 | #define MXC_PLL_DP_CONFIG 0x04 |
| @@ -380,7 +387,8 @@ | |||
| 380 | /* Define the bits in register CLPCR */ | 387 | /* Define the bits in register CLPCR */ |
| 381 | #define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23) | 388 | #define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23) |
| 382 | #define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22) | 389 | #define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22) |
| 383 | #define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21) | 390 | #define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21) |
| 391 | #define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 25) | ||
| 384 | #define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20) | 392 | #define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20) |
| 385 | #define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19) | 393 | #define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19) |
| 386 | #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) | 394 | #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) |
diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h index 8c50cb5d05f5..6302e4670000 100644 --- a/arch/arm/mach-mx5/devices-imx51.h +++ b/arch/arm/mach-mx5/devices-imx51.h | |||
| @@ -31,6 +31,11 @@ extern const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst; | |||
| 31 | #define imx51_add_mxc_nand(pdata) \ | 31 | #define imx51_add_mxc_nand(pdata) \ |
| 32 | imx_add_mxc_nand(&imx51_mxc_nand_data, pdata) | 32 | imx_add_mxc_nand(&imx51_mxc_nand_data, pdata) |
| 33 | 33 | ||
| 34 | extern const struct imx_sdhci_esdhc_imx_data | ||
| 35 | imx51_sdhci_esdhc_imx_data[] __initconst; | ||
| 36 | #define imx51_add_sdhci_esdhc_imx(id, pdata) \ | ||
| 37 | imx_add_sdhci_esdhc_imx(&imx51_sdhci_esdhc_imx_data[id], pdata) | ||
| 38 | |||
| 34 | extern const struct imx_spi_imx_data imx51_cspi_data __initconst; | 39 | extern const struct imx_spi_imx_data imx51_cspi_data __initconst; |
| 35 | #define imx51_add_cspi(pdata) \ | 40 | #define imx51_add_cspi(pdata) \ |
| 36 | imx_add_spi_imx(&imx51_cspi_data, pdata) | 41 | imx_add_spi_imx(&imx51_cspi_data, pdata) |
| @@ -39,6 +44,6 @@ extern const struct imx_spi_imx_data imx51_ecspi_data[] __initconst; | |||
| 39 | #define imx51_add_ecspi(id, pdata) \ | 44 | #define imx51_add_ecspi(id, pdata) \ |
| 40 | imx_add_spi_imx(&imx51_ecspi_data[id], pdata) | 45 | imx_add_spi_imx(&imx51_ecspi_data[id], pdata) |
| 41 | 46 | ||
| 42 | extern const struct imx_esdhc_imx_data imx51_esdhc_data[] __initconst; | 47 | extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst; |
| 43 | #define imx51_add_esdhc(id, pdata) \ | 48 | #define imx51_add_imx2_wdt(id, pdata) \ |
| 44 | imx_add_esdhc(&imx51_esdhc_data[id], pdata) | 49 | imx_add_imx2_wdt(&imx51_imx2_wdt_data[id]) |
diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h new file mode 100644 index 000000000000..9d0ec2507fa6 --- /dev/null +++ b/arch/arm/mach-mx5/devices-imx53.h | |||
| @@ -0,0 +1,13 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it under | ||
| 5 | * the terms of the GNU General Public License version 2 as published by the | ||
| 6 | * Free Software Foundation. | ||
| 7 | */ | ||
| 8 | #include <mach/mx53.h> | ||
| 9 | #include <mach/devices-common.h> | ||
| 10 | |||
| 11 | extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[] __initconst; | ||
| 12 | #define imx53_add_imx_uart(id, pdata) \ | ||
| 13 | imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata) | ||
diff --git a/arch/arm/mach-mx5/devices-mx50.h b/arch/arm/mach-mx5/devices-mx50.h new file mode 100644 index 000000000000..98ab07468a0e --- /dev/null +++ b/arch/arm/mach-mx5/devices-mx50.h | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | */ | ||
| 4 | |||
| 5 | /* | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | |||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | |||
| 16 | * You should have received a copy of the GNU General Public License along | ||
| 17 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include <mach/mx50.h> | ||
| 22 | #include <mach/devices-common.h> | ||
| 23 | |||
| 24 | extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst; | ||
| 25 | #define imx50_add_imx_uart(id, pdata) \ | ||
| 26 | imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata) | ||
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c index 4c7be87a7c9d..1bda5cb339dc 100644 --- a/arch/arm/mach-mx5/devices.c +++ b/arch/arm/mach-mx5/devices.c | |||
| @@ -97,19 +97,27 @@ struct platform_device mxc_usbh1_device = { | |||
| 97 | }, | 97 | }, |
| 98 | }; | 98 | }; |
| 99 | 99 | ||
| 100 | static struct resource mxc_wdt_resources[] = { | 100 | static struct resource usbh2_resources[] = { |
| 101 | { | 101 | { |
| 102 | .start = MX51_WDOG_BASE_ADDR, | 102 | .start = MX51_OTG_BASE_ADDR + 0x400, |
| 103 | .end = MX51_WDOG_BASE_ADDR + SZ_16K - 1, | 103 | .end = MX51_OTG_BASE_ADDR + 0x400 + 0x1ff, |
| 104 | .flags = IORESOURCE_MEM, | 104 | .flags = IORESOURCE_MEM, |
| 105 | }, | 105 | }, |
| 106 | { | ||
| 107 | .start = MX51_MXC_INT_USB_H2, | ||
| 108 | .flags = IORESOURCE_IRQ, | ||
| 109 | }, | ||
| 106 | }; | 110 | }; |
| 107 | 111 | ||
| 108 | struct platform_device mxc_wdt = { | 112 | struct platform_device mxc_usbh2_device = { |
| 109 | .name = "imx2-wdt", | 113 | .name = "mxc-ehci", |
| 110 | .id = 0, | 114 | .id = 2, |
| 111 | .num_resources = ARRAY_SIZE(mxc_wdt_resources), | 115 | .num_resources = ARRAY_SIZE(usbh2_resources), |
| 112 | .resource = mxc_wdt_resources, | 116 | .resource = usbh2_resources, |
| 117 | .dev = { | ||
| 118 | .dma_mask = &usb_dma_mask, | ||
| 119 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 120 | }, | ||
| 113 | }; | 121 | }; |
| 114 | 122 | ||
| 115 | static struct resource mxc_kpp_resources[] = { | 123 | static struct resource mxc_kpp_resources[] = { |
| @@ -160,9 +168,36 @@ static struct mxc_gpio_port mxc_gpio_ports[] = { | |||
| 160 | .irq_high = MX51_MXC_INT_GPIO4_HIGH, | 168 | .irq_high = MX51_MXC_INT_GPIO4_HIGH, |
| 161 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3 | 169 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3 |
| 162 | }, | 170 | }, |
| 171 | { | ||
| 172 | .chip.label = "gpio-4", | ||
| 173 | .base = MX53_IO_ADDRESS(MX53_GPIO5_BASE_ADDR), | ||
| 174 | .irq = MX53_INT_GPIO5_LOW, | ||
| 175 | .irq_high = MX53_INT_GPIO5_HIGH, | ||
| 176 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 4 | ||
| 177 | }, | ||
| 178 | { | ||
| 179 | .chip.label = "gpio-5", | ||
| 180 | .base = MX53_IO_ADDRESS(MX53_GPIO6_BASE_ADDR), | ||
| 181 | .irq = MX53_INT_GPIO6_LOW, | ||
| 182 | .irq_high = MX53_INT_GPIO6_HIGH, | ||
| 183 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 5 | ||
| 184 | }, | ||
| 185 | { | ||
| 186 | .chip.label = "gpio-6", | ||
| 187 | .base = MX53_IO_ADDRESS(MX53_GPIO7_BASE_ADDR), | ||
| 188 | .irq = MX53_INT_GPIO7_LOW, | ||
| 189 | .irq_high = MX53_INT_GPIO7_HIGH, | ||
| 190 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 6 | ||
| 191 | }, | ||
| 163 | }; | 192 | }; |
| 164 | 193 | ||
| 165 | int __init imx51_register_gpios(void) | 194 | int __init imx51_register_gpios(void) |
| 166 | { | 195 | { |
| 196 | return mxc_gpio_init(mxc_gpio_ports, 4); | ||
| 197 | } | ||
| 198 | |||
| 199 | int __init imx53_register_gpios(void) | ||
| 200 | { | ||
| 167 | return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports)); | 201 | return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports)); |
| 168 | } | 202 | } |
| 203 | |||
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h index af1d07c0bbc1..16891aa3573c 100644 --- a/arch/arm/mach-mx5/devices.h +++ b/arch/arm/mach-mx5/devices.h | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | extern struct platform_device mxc_usbdr_host_device; | 1 | extern struct platform_device mxc_usbdr_host_device; |
| 2 | extern struct platform_device mxc_usbh1_device; | 2 | extern struct platform_device mxc_usbh1_device; |
| 3 | extern struct platform_device mxc_usbh2_device; | ||
| 3 | extern struct platform_device mxc_usbdr_udc_device; | 4 | extern struct platform_device mxc_usbdr_udc_device; |
| 4 | extern struct platform_device mxc_wdt; | ||
| 5 | extern struct platform_device mxc_hsi2c_device; | 5 | extern struct platform_device mxc_hsi2c_device; |
| 6 | extern struct platform_device mxc_keypad_device; | 6 | extern struct platform_device mxc_keypad_device; |
diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c index a2e6e8c39d25..c96d018ff8a2 100644 --- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c +++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c | |||
| @@ -33,12 +33,12 @@ | |||
| 33 | #include "devices-imx51.h" | 33 | #include "devices-imx51.h" |
| 34 | #include "devices.h" | 34 | #include "devices.h" |
| 35 | 35 | ||
| 36 | #define MBIMX51_TSC2007_GPIO (2*32 + 30) | 36 | #define MBIMX51_TSC2007_GPIO IMX_GPIO_NR(3, 30) |
| 37 | #define MBIMX51_TSC2007_IRQ (MXC_INTERNAL_IRQS + MBIMX51_TSC2007_GPIO) | 37 | #define MBIMX51_TSC2007_IRQ (MXC_INTERNAL_IRQS + MBIMX51_TSC2007_GPIO) |
| 38 | #define MBIMX51_LED0 (2*32 + 5) | 38 | #define MBIMX51_LED0 IMX_GPIO_NR(3, 5) |
| 39 | #define MBIMX51_LED1 (2*32 + 6) | 39 | #define MBIMX51_LED1 IMX_GPIO_NR(3, 6) |
| 40 | #define MBIMX51_LED2 (2*32 + 7) | 40 | #define MBIMX51_LED2 IMX_GPIO_NR(3, 7) |
| 41 | #define MBIMX51_LED3 (2*32 + 8) | 41 | #define MBIMX51_LED3 IMX_GPIO_NR(3, 8) |
| 42 | 42 | ||
| 43 | static struct gpio_led mbimx51_leds[] = { | 43 | static struct gpio_led mbimx51_leds[] = { |
| 44 | { | 44 | { |
| @@ -84,7 +84,7 @@ static struct platform_device *devices[] __initdata = { | |||
| 84 | &mbimx51_leds_gpio, | 84 | &mbimx51_leds_gpio, |
| 85 | }; | 85 | }; |
| 86 | 86 | ||
| 87 | static struct pad_desc mbimx51_pads[] = { | 87 | static iomux_v3_cfg_t mbimx51_pads[] = { |
| 88 | /* UART2 */ | 88 | /* UART2 */ |
| 89 | MX51_PAD_UART2_RXD__UART2_RXD, | 89 | MX51_PAD_UART2_RXD__UART2_RXD, |
| 90 | MX51_PAD_UART2_TXD__UART2_TXD, | 90 | MX51_PAD_UART2_TXD__UART2_TXD, |
| @@ -96,13 +96,13 @@ static struct pad_desc mbimx51_pads[] = { | |||
| 96 | MX51_PAD_KEY_COL5__UART3_CTS, | 96 | MX51_PAD_KEY_COL5__UART3_CTS, |
| 97 | 97 | ||
| 98 | /* TSC2007 IRQ */ | 98 | /* TSC2007 IRQ */ |
| 99 | MX51_PAD_NANDF_D10__GPIO_3_30, | 99 | MX51_PAD_NANDF_D10__GPIO3_30, |
| 100 | 100 | ||
| 101 | /* LEDS */ | 101 | /* LEDS */ |
| 102 | MX51_PAD_DISPB2_SER_DIN__GPIO_3_5, | 102 | MX51_PAD_DISPB2_SER_DIN__GPIO3_5, |
| 103 | MX51_PAD_DISPB2_SER_DIO__GPIO_3_6, | 103 | MX51_PAD_DISPB2_SER_DIO__GPIO3_6, |
| 104 | MX51_PAD_DISPB2_SER_CLK__GPIO_3_7, | 104 | MX51_PAD_DISPB2_SER_CLK__GPIO3_7, |
| 105 | MX51_PAD_DISPB2_SER_RS__GPIO_3_8, | 105 | MX51_PAD_DISPB2_SER_RS__GPIO3_8, |
| 106 | 106 | ||
| 107 | /* KPP */ | 107 | /* KPP */ |
| 108 | MX51_PAD_KEY_ROW0__KEY_ROW0, | 108 | MX51_PAD_KEY_ROW0__KEY_ROW0, |
| @@ -217,6 +217,6 @@ void __init eukrea_mbimx51_baseboard_init(void) | |||
| 217 | i2c_register_board_info(1, mbimx51_i2c_devices, | 217 | i2c_register_board_info(1, mbimx51_i2c_devices, |
| 218 | ARRAY_SIZE(mbimx51_i2c_devices)); | 218 | ARRAY_SIZE(mbimx51_i2c_devices)); |
| 219 | 219 | ||
| 220 | imx51_add_esdhc(0, NULL); | 220 | imx51_add_sdhci_esdhc_imx(0, NULL); |
| 221 | imx51_add_esdhc(1, NULL); | 221 | imx51_add_sdhci_esdhc_imx(1, NULL); |
| 222 | } | 222 | } |
diff --git a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c index 2b48f5190830..c372a4373691 100644 --- a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c +++ b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c | |||
| @@ -45,14 +45,13 @@ | |||
| 45 | #include "devices-imx51.h" | 45 | #include "devices-imx51.h" |
| 46 | #include "devices.h" | 46 | #include "devices.h" |
| 47 | 47 | ||
| 48 | #define MBIMXSD_GPIO_3_31 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, \ | 48 | static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = { |
| 49 | MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP) | ||
| 50 | |||
| 51 | static struct pad_desc eukrea_mbimxsd_pads[] = { | ||
| 52 | /* LED */ | 49 | /* LED */ |
| 53 | MX51_PAD_NANDF_D10__GPIO_3_30, | 50 | MX51_PAD_NANDF_D10__GPIO3_30, |
| 54 | /* SWITCH */ | 51 | /* SWITCH */ |
| 55 | MBIMXSD_GPIO_3_31, | 52 | _MX51_PAD_NANDF_D9__GPIO3_31 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | |
| 53 | PAD_CTL_PKE | PAD_CTL_SRE_FAST | | ||
| 54 | PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS), | ||
| 56 | /* UART2 */ | 55 | /* UART2 */ |
| 57 | MX51_PAD_UART2_RXD__UART2_RXD, | 56 | MX51_PAD_UART2_RXD__UART2_RXD, |
| 58 | MX51_PAD_UART2_TXD__UART2_TXD, | 57 | MX51_PAD_UART2_TXD__UART2_TXD, |
| @@ -70,8 +69,8 @@ static struct pad_desc eukrea_mbimxsd_pads[] = { | |||
| 70 | MX51_PAD_SD1_DATA3__SD1_DATA3, | 69 | MX51_PAD_SD1_DATA3__SD1_DATA3, |
| 71 | }; | 70 | }; |
| 72 | 71 | ||
| 73 | #define GPIO_LED1 (2 * 32 + 30) | 72 | #define GPIO_LED1 IMX_GPIO_NR(3, 30) |
| 74 | #define GPIO_SWITCH1 (2 * 32 + 31) | 73 | #define GPIO_SWITCH1 IMX_GPIO_NR(3, 31) |
| 75 | 74 | ||
| 76 | static struct gpio_led eukrea_mbimxsd_leds[] = { | 75 | static struct gpio_led eukrea_mbimxsd_leds[] = { |
| 77 | { | 76 | { |
| @@ -149,7 +148,7 @@ void __init eukrea_mbimxsd51_baseboard_init(void) | |||
| 149 | imx51_add_imx_uart(1, NULL); | 148 | imx51_add_imx_uart(1, NULL); |
| 150 | imx51_add_imx_uart(2, &uart_pdata); | 149 | imx51_add_imx_uart(2, &uart_pdata); |
| 151 | 150 | ||
| 152 | imx51_add_esdhc(0, NULL); | 151 | imx51_add_sdhci_esdhc_imx(0, NULL); |
| 153 | 152 | ||
| 154 | gpio_request(GPIO_LED1, "LED1"); | 153 | gpio_request(GPIO_LED1, "LED1"); |
| 155 | gpio_direction_output(GPIO_LED1, 1); | 154 | gpio_direction_output(GPIO_LED1, 1); |
diff --git a/arch/arm/mach-mx5/mm-mx50.c b/arch/arm/mach-mx5/mm-mx50.c new file mode 100644 index 000000000000..8c6540e58390 --- /dev/null +++ b/arch/arm/mach-mx5/mm-mx50.c | |||
| @@ -0,0 +1,59 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | |||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | |||
| 14 | * You should have received a copy of the GNU General Public License along | ||
| 15 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
| 17 | * | ||
| 18 | * Create static mapping between physical to virtual memory. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include <linux/mm.h> | ||
| 22 | #include <linux/init.h> | ||
| 23 | |||
| 24 | #include <asm/mach/map.h> | ||
| 25 | |||
| 26 | #include <mach/hardware.h> | ||
| 27 | #include <mach/common.h> | ||
| 28 | #include <mach/iomux-v3.h> | ||
| 29 | |||
| 30 | /* | ||
| 31 | * Define the MX50 memory map. | ||
| 32 | */ | ||
| 33 | static struct map_desc mx50_io_desc[] __initdata = { | ||
| 34 | imx_map_entry(MX50, TZIC, MT_DEVICE), | ||
| 35 | imx_map_entry(MX50, SPBA0, MT_DEVICE), | ||
| 36 | imx_map_entry(MX50, AIPS1, MT_DEVICE), | ||
| 37 | imx_map_entry(MX50, AIPS2, MT_DEVICE), | ||
| 38 | }; | ||
| 39 | |||
| 40 | /* | ||
| 41 | * This function initializes the memory map. It is called during the | ||
| 42 | * system startup to create static physical to virtual memory mappings | ||
| 43 | * for the IO modules. | ||
| 44 | */ | ||
| 45 | void __init mx50_map_io(void) | ||
| 46 | { | ||
| 47 | mxc_set_cpu_type(MXC_CPU_MX50); | ||
| 48 | mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR)); | ||
| 49 | mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR)); | ||
| 50 | iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc)); | ||
| 51 | } | ||
| 52 | |||
| 53 | int imx50_register_gpios(void); | ||
| 54 | |||
| 55 | void __init mx50_init_irq(void) | ||
| 56 | { | ||
| 57 | tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR)); | ||
| 58 | imx50_register_gpios(); | ||
| 59 | } | ||
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c index bc3f30db8d9a..457f9f95204b 100644 --- a/arch/arm/mach-mx5/mm.c +++ b/arch/arm/mach-mx5/mm.c | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. | 2 | * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. |
| 3 | * | 3 | * |
| 4 | * The code contained herein is licensed under the GNU General Public | 4 | * The code contained herein is licensed under the GNU General Public |
| 5 | * License. You may obtain a copy of the GNU General Public License | 5 | * License. You may obtain a copy of the GNU General Public License |
| @@ -23,33 +23,21 @@ | |||
| 23 | /* | 23 | /* |
| 24 | * Define the MX51 memory map. | 24 | * Define the MX51 memory map. |
| 25 | */ | 25 | */ |
| 26 | static struct map_desc mxc_io_desc[] __initdata = { | 26 | static struct map_desc mx51_io_desc[] __initdata = { |
| 27 | { | 27 | imx_map_entry(MX51, IRAM, MT_DEVICE), |
| 28 | .virtual = MX51_IRAM_BASE_ADDR_VIRT, | 28 | imx_map_entry(MX51, DEBUG, MT_DEVICE), |
| 29 | .pfn = __phys_to_pfn(MX51_IRAM_BASE_ADDR), | 29 | imx_map_entry(MX51, AIPS1, MT_DEVICE), |
| 30 | .length = MX51_IRAM_SIZE, | 30 | imx_map_entry(MX51, SPBA0, MT_DEVICE), |
| 31 | .type = MT_DEVICE | 31 | imx_map_entry(MX51, AIPS2, MT_DEVICE), |
| 32 | }, { | 32 | }; |
| 33 | .virtual = MX51_DEBUG_BASE_ADDR_VIRT, | 33 | |
| 34 | .pfn = __phys_to_pfn(MX51_DEBUG_BASE_ADDR), | 34 | /* |
| 35 | .length = MX51_DEBUG_SIZE, | 35 | * Define the MX53 memory map. |
| 36 | .type = MT_DEVICE | 36 | */ |
| 37 | }, { | 37 | static struct map_desc mx53_io_desc[] __initdata = { |
| 38 | .virtual = MX51_AIPS1_BASE_ADDR_VIRT, | 38 | imx_map_entry(MX53, AIPS1, MT_DEVICE), |
| 39 | .pfn = __phys_to_pfn(MX51_AIPS1_BASE_ADDR), | 39 | imx_map_entry(MX53, SPBA0, MT_DEVICE), |
| 40 | .length = MX51_AIPS1_SIZE, | 40 | imx_map_entry(MX53, AIPS2, MT_DEVICE), |
| 41 | .type = MT_DEVICE | ||
| 42 | }, { | ||
| 43 | .virtual = MX51_SPBA0_BASE_ADDR_VIRT, | ||
| 44 | .pfn = __phys_to_pfn(MX51_SPBA0_BASE_ADDR), | ||
| 45 | .length = MX51_SPBA0_SIZE, | ||
| 46 | .type = MT_DEVICE | ||
| 47 | }, { | ||
| 48 | .virtual = MX51_AIPS2_BASE_ADDR_VIRT, | ||
| 49 | .pfn = __phys_to_pfn(MX51_AIPS2_BASE_ADDR), | ||
| 50 | .length = MX51_AIPS2_SIZE, | ||
| 51 | .type = MT_DEVICE | ||
| 52 | }, | ||
| 53 | }; | 41 | }; |
| 54 | 42 | ||
| 55 | /* | 43 | /* |
| @@ -61,8 +49,16 @@ void __init mx51_map_io(void) | |||
| 61 | { | 49 | { |
| 62 | mxc_set_cpu_type(MXC_CPU_MX51); | 50 | mxc_set_cpu_type(MXC_CPU_MX51); |
| 63 | mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); | 51 | mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); |
| 64 | mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG_BASE_ADDR)); | 52 | mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR)); |
| 65 | iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); | 53 | iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc)); |
| 54 | } | ||
| 55 | |||
| 56 | void __init mx53_map_io(void) | ||
| 57 | { | ||
| 58 | mxc_set_cpu_type(MXC_CPU_MX53); | ||
| 59 | mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR)); | ||
| 60 | mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG_BASE_ADDR)); | ||
| 61 | iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc)); | ||
| 66 | } | 62 | } |
| 67 | 63 | ||
| 68 | int imx51_register_gpios(void); | 64 | int imx51_register_gpios(void); |
| @@ -72,7 +68,7 @@ void __init mx51_init_irq(void) | |||
| 72 | unsigned long tzic_addr; | 68 | unsigned long tzic_addr; |
| 73 | void __iomem *tzic_virt; | 69 | void __iomem *tzic_virt; |
| 74 | 70 | ||
| 75 | if (mx51_revision() < MX51_CHIP_REV_2_0) | 71 | if (mx51_revision() < IMX_CHIP_REVISION_2_0) |
| 76 | tzic_addr = MX51_TZIC_BASE_ADDR_TO1; | 72 | tzic_addr = MX51_TZIC_BASE_ADDR_TO1; |
| 77 | else | 73 | else |
| 78 | tzic_addr = MX51_TZIC_BASE_ADDR; | 74 | tzic_addr = MX51_TZIC_BASE_ADDR; |
| @@ -84,3 +80,20 @@ void __init mx51_init_irq(void) | |||
| 84 | tzic_init_irq(tzic_virt); | 80 | tzic_init_irq(tzic_virt); |
| 85 | imx51_register_gpios(); | 81 | imx51_register_gpios(); |
| 86 | } | 82 | } |
| 83 | |||
| 84 | int imx53_register_gpios(void); | ||
| 85 | |||
| 86 | void __init mx53_init_irq(void) | ||
| 87 | { | ||
| 88 | unsigned long tzic_addr; | ||
| 89 | void __iomem *tzic_virt; | ||
| 90 | |||
| 91 | tzic_addr = MX53_TZIC_BASE_ADDR; | ||
| 92 | |||
| 93 | tzic_virt = ioremap(tzic_addr, SZ_16K); | ||
| 94 | if (!tzic_virt) | ||
| 95 | panic("unable to map TZIC interrupt controller\n"); | ||
| 96 | |||
| 97 | tzic_init_irq(tzic_virt); | ||
| 98 | imx53_register_gpios(); | ||
| 99 | } | ||
diff --git a/arch/arm/mach-mxc91231/clock.c b/arch/arm/mach-mxc91231/clock.c index 5c85075d8a56..9fab505f1eb1 100644 --- a/arch/arm/mach-mxc91231/clock.c +++ b/arch/arm/mach-mxc91231/clock.c | |||
| @@ -2,12 +2,12 @@ | |||
| 2 | #include <linux/kernel.h> | 2 | #include <linux/kernel.h> |
| 3 | #include <linux/init.h> | 3 | #include <linux/init.h> |
| 4 | #include <linux/io.h> | 4 | #include <linux/io.h> |
| 5 | #include <linux/clkdev.h> | ||
| 5 | 6 | ||
| 6 | #include <mach/clock.h> | 7 | #include <mach/clock.h> |
| 7 | #include <mach/hardware.h> | 8 | #include <mach/hardware.h> |
| 8 | #include <mach/common.h> | 9 | #include <mach/common.h> |
| 9 | 10 | ||
| 10 | #include <asm/clkdev.h> | ||
| 11 | #include <asm/bug.h> | 11 | #include <asm/bug.h> |
| 12 | #include <asm/div64.h> | 12 | #include <asm/div64.h> |
| 13 | 13 | ||
diff --git a/arch/arm/mach-mxc91231/mm.c b/arch/arm/mach-mxc91231/mm.c index aeccfd755fee..7652c301da88 100644 --- a/arch/arm/mach-mxc91231/mm.c +++ b/arch/arm/mach-mxc91231/mm.c | |||
| @@ -27,48 +27,15 @@ | |||
| 27 | /* | 27 | /* |
| 28 | * This structure defines the MXC memory map. | 28 | * This structure defines the MXC memory map. |
| 29 | */ | 29 | */ |
| 30 | static struct map_desc mxc_io_desc[] __initdata = { | 30 | static struct map_desc mxc91231_io_desc[] __initdata = { |
| 31 | { | 31 | imx_map_entry(MXC91231, L2CC, MT_DEVICE), |
| 32 | .virtual = MXC91231_L2CC_BASE_ADDR_VIRT, | 32 | imx_map_entry(MXC91231, X_MEMC, MT_DEVICE), |
| 33 | .pfn = __phys_to_pfn(MXC91231_L2CC_BASE_ADDR), | 33 | imx_map_entry(MXC91231, ROMP, MT_DEVICE), |
| 34 | .length = MXC91231_L2CC_SIZE, | 34 | imx_map_entry(MXC91231, AVIC, MT_DEVICE), |
| 35 | .type = MT_DEVICE, | 35 | imx_map_entry(MXC91231, AIPS1, MT_DEVICE), |
| 36 | }, { | 36 | imx_map_entry(MXC91231, SPBA0, MT_DEVICE), |
| 37 | .virtual = MXC91231_X_MEMC_BASE_ADDR_VIRT, | 37 | imx_map_entry(MXC91231, SPBA1, MT_DEVICE), |
| 38 | .pfn = __phys_to_pfn(MXC91231_X_MEMC_BASE_ADDR), | 38 | imx_map_entry(MXC91231, AIPS2, MT_DEVICE), |
| 39 | .length = MXC91231_X_MEMC_SIZE, | ||
| 40 | .type = MT_DEVICE, | ||
| 41 | }, { | ||
| 42 | .virtual = MXC91231_ROMP_BASE_ADDR_VIRT, | ||
| 43 | .pfn = __phys_to_pfn(MXC91231_ROMP_BASE_ADDR), | ||
| 44 | .length = MXC91231_ROMP_SIZE, | ||
| 45 | .type = MT_DEVICE, | ||
| 46 | }, { | ||
| 47 | .virtual = MXC91231_AVIC_BASE_ADDR_VIRT, | ||
| 48 | .pfn = __phys_to_pfn(MXC91231_AVIC_BASE_ADDR), | ||
| 49 | .length = MXC91231_AVIC_SIZE, | ||
| 50 | .type = MT_DEVICE, | ||
| 51 | }, { | ||
| 52 | .virtual = MXC91231_AIPS1_BASE_ADDR_VIRT, | ||
| 53 | .pfn = __phys_to_pfn(MXC91231_AIPS1_BASE_ADDR), | ||
| 54 | .length = MXC91231_AIPS1_SIZE, | ||
| 55 | .type = MT_DEVICE, | ||
| 56 | }, { | ||
| 57 | .virtual = MXC91231_SPBA0_BASE_ADDR_VIRT, | ||
| 58 | .pfn = __phys_to_pfn(MXC91231_SPBA0_BASE_ADDR), | ||
| 59 | .length = MXC91231_SPBA0_SIZE, | ||
| 60 | .type = MT_DEVICE, | ||
| 61 | }, { | ||
| 62 | .virtual = MXC91231_SPBA1_BASE_ADDR_VIRT, | ||
| 63 | .pfn = __phys_to_pfn(MXC91231_SPBA1_BASE_ADDR), | ||
| 64 | .length = MXC91231_SPBA1_SIZE, | ||
| 65 | .type = MT_DEVICE, | ||
| 66 | }, { | ||
| 67 | .virtual = MXC91231_AIPS2_BASE_ADDR_VIRT, | ||
| 68 | .pfn = __phys_to_pfn(MXC91231_AIPS2_BASE_ADDR), | ||
| 69 | .length = MXC91231_AIPS2_SIZE, | ||
| 70 | .type = MT_DEVICE, | ||
| 71 | }, | ||
| 72 | }; | 39 | }; |
| 73 | 40 | ||
| 74 | /* | 41 | /* |
| @@ -80,7 +47,7 @@ void __init mxc91231_map_io(void) | |||
| 80 | { | 47 | { |
| 81 | mxc_set_cpu_type(MXC_CPU_MXC91231); | 48 | mxc_set_cpu_type(MXC_CPU_MXC91231); |
| 82 | 49 | ||
| 83 | iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); | 50 | iotable_init(mxc91231_io_desc, ARRAY_SIZE(mxc91231_io_desc)); |
| 84 | } | 51 | } |
| 85 | 52 | ||
| 86 | int mxc91231_register_gpios(void); | 53 | int mxc91231_register_gpios(void); |
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig new file mode 100644 index 000000000000..c4ac7b415195 --- /dev/null +++ b/arch/arm/mach-mxs/Kconfig | |||
| @@ -0,0 +1,34 @@ | |||
| 1 | if ARCH_MXS | ||
| 2 | |||
| 3 | source "arch/arm/mach-mxs/devices/Kconfig" | ||
| 4 | |||
| 5 | config SOC_IMX23 | ||
| 6 | bool | ||
| 7 | select CPU_ARM926T | ||
| 8 | |||
| 9 | config SOC_IMX28 | ||
| 10 | bool | ||
| 11 | select CPU_ARM926T | ||
| 12 | |||
| 13 | comment "MXS platforms:" | ||
| 14 | |||
| 15 | config MACH_MX23EVK | ||
| 16 | bool "Support MX23EVK Platform" | ||
| 17 | select SOC_IMX23 | ||
| 18 | select MXS_HAVE_PLATFORM_DUART | ||
| 19 | default y | ||
| 20 | help | ||
| 21 | Include support for MX23EVK platform. This includes specific | ||
| 22 | configurations for the board and its peripherals. | ||
| 23 | |||
| 24 | config MACH_MX28EVK | ||
| 25 | bool "Support MX28EVK Platform" | ||
| 26 | select SOC_IMX28 | ||
| 27 | select MXS_HAVE_PLATFORM_DUART | ||
| 28 | select MXS_HAVE_PLATFORM_FEC | ||
| 29 | default y | ||
| 30 | help | ||
| 31 | Include support for MX28EVK platform. This includes specific | ||
| 32 | configurations for the board and its peripherals. | ||
| 33 | |||
| 34 | endif | ||
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile new file mode 100644 index 000000000000..39d3f9c2a841 --- /dev/null +++ b/arch/arm/mach-mxs/Makefile | |||
| @@ -0,0 +1,10 @@ | |||
| 1 | # Common support | ||
| 2 | obj-y := clock.o devices.o gpio.o icoll.o iomux.o system.o timer.o | ||
| 3 | |||
| 4 | obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o | ||
| 5 | obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o | ||
| 6 | |||
| 7 | obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o | ||
| 8 | obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o | ||
| 9 | |||
| 10 | obj-y += devices/ | ||
diff --git a/arch/arm/mach-mxs/Makefile.boot b/arch/arm/mach-mxs/Makefile.boot new file mode 100644 index 000000000000..eb541e0291da --- /dev/null +++ b/arch/arm/mach-mxs/Makefile.boot | |||
| @@ -0,0 +1 @@ | |||
| zreladdr-y := 0x40008000 | |||
diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c new file mode 100644 index 000000000000..8f5a19ab558c --- /dev/null +++ b/arch/arm/mach-mxs/clock-mx23.c | |||
| @@ -0,0 +1,526 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License along | ||
| 15 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/mm.h> | ||
| 20 | #include <linux/delay.h> | ||
| 21 | #include <linux/clk.h> | ||
| 22 | #include <linux/io.h> | ||
| 23 | #include <linux/jiffies.h> | ||
| 24 | |||
| 25 | #include <asm/clkdev.h> | ||
| 26 | #include <asm/div64.h> | ||
| 27 | |||
| 28 | #include <mach/mx23.h> | ||
| 29 | #include <mach/common.h> | ||
| 30 | #include <mach/clock.h> | ||
| 31 | |||
| 32 | #include "regs-clkctrl-mx23.h" | ||
| 33 | |||
| 34 | #define CLKCTRL_BASE_ADDR MX23_IO_ADDRESS(MX23_CLKCTRL_BASE_ADDR) | ||
| 35 | #define DIGCTRL_BASE_ADDR MX23_IO_ADDRESS(MX23_DIGCTL_BASE_ADDR) | ||
| 36 | |||
| 37 | #define PARENT_RATE_SHIFT 8 | ||
| 38 | |||
| 39 | static int _raw_clk_enable(struct clk *clk) | ||
| 40 | { | ||
| 41 | u32 reg; | ||
| 42 | |||
| 43 | if (clk->enable_reg) { | ||
| 44 | reg = __raw_readl(clk->enable_reg); | ||
| 45 | reg &= ~(1 << clk->enable_shift); | ||
| 46 | __raw_writel(reg, clk->enable_reg); | ||
| 47 | } | ||
| 48 | |||
| 49 | return 0; | ||
| 50 | } | ||
| 51 | |||
| 52 | static void _raw_clk_disable(struct clk *clk) | ||
| 53 | { | ||
| 54 | u32 reg; | ||
| 55 | |||
| 56 | if (clk->enable_reg) { | ||
| 57 | reg = __raw_readl(clk->enable_reg); | ||
| 58 | reg |= 1 << clk->enable_shift; | ||
| 59 | __raw_writel(reg, clk->enable_reg); | ||
| 60 | } | ||
| 61 | } | ||
| 62 | |||
| 63 | /* | ||
| 64 | * ref_xtal_clk | ||
| 65 | */ | ||
| 66 | static unsigned long ref_xtal_clk_get_rate(struct clk *clk) | ||
| 67 | { | ||
| 68 | return 24000000; | ||
| 69 | } | ||
| 70 | |||
| 71 | static struct clk ref_xtal_clk = { | ||
| 72 | .get_rate = ref_xtal_clk_get_rate, | ||
| 73 | }; | ||
| 74 | |||
| 75 | /* | ||
| 76 | * pll_clk | ||
| 77 | */ | ||
| 78 | static unsigned long pll_clk_get_rate(struct clk *clk) | ||
| 79 | { | ||
| 80 | return 480000000; | ||
| 81 | } | ||
| 82 | |||
| 83 | static int pll_clk_enable(struct clk *clk) | ||
| 84 | { | ||
| 85 | __raw_writel(BM_CLKCTRL_PLLCTRL0_POWER | | ||
| 86 | BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS, | ||
| 87 | CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_SET); | ||
| 88 | |||
| 89 | /* Only a 10us delay is need. PLLCTRL1 LOCK bitfied is only a timer | ||
| 90 | * and is incorrect (excessive). Per definition of the PLLCTRL0 | ||
| 91 | * POWER field, waiting at least 10us. | ||
| 92 | */ | ||
| 93 | udelay(10); | ||
| 94 | |||
| 95 | return 0; | ||
| 96 | } | ||
| 97 | |||
| 98 | static void pll_clk_disable(struct clk *clk) | ||
| 99 | { | ||
| 100 | __raw_writel(BM_CLKCTRL_PLLCTRL0_POWER | | ||
| 101 | BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS, | ||
| 102 | CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_CLR); | ||
| 103 | } | ||
| 104 | |||
| 105 | static struct clk pll_clk = { | ||
| 106 | .get_rate = pll_clk_get_rate, | ||
| 107 | .enable = pll_clk_enable, | ||
| 108 | .disable = pll_clk_disable, | ||
| 109 | .parent = &ref_xtal_clk, | ||
| 110 | }; | ||
| 111 | |||
| 112 | /* | ||
| 113 | * ref_clk | ||
| 114 | */ | ||
| 115 | #define _CLK_GET_RATE_REF(name, sr, ss) \ | ||
| 116 | static unsigned long name##_get_rate(struct clk *clk) \ | ||
| 117 | { \ | ||
| 118 | unsigned long parent_rate; \ | ||
| 119 | u32 reg, div; \ | ||
| 120 | \ | ||
| 121 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##sr); \ | ||
| 122 | div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f; \ | ||
| 123 | parent_rate = clk_get_rate(clk->parent); \ | ||
| 124 | \ | ||
| 125 | return SH_DIV((parent_rate >> PARENT_RATE_SHIFT) * 18, \ | ||
| 126 | div, PARENT_RATE_SHIFT); \ | ||
| 127 | } | ||
| 128 | |||
| 129 | _CLK_GET_RATE_REF(ref_cpu_clk, FRAC, CPU) | ||
| 130 | _CLK_GET_RATE_REF(ref_emi_clk, FRAC, EMI) | ||
| 131 | _CLK_GET_RATE_REF(ref_pix_clk, FRAC, PIX) | ||
| 132 | _CLK_GET_RATE_REF(ref_io_clk, FRAC, IO) | ||
| 133 | |||
| 134 | #define _DEFINE_CLOCK_REF(name, er, es) \ | ||
| 135 | static struct clk name = { \ | ||
| 136 | .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \ | ||
| 137 | .enable_shift = BP_CLKCTRL_##er##_CLKGATE##es, \ | ||
| 138 | .get_rate = name##_get_rate, \ | ||
| 139 | .enable = _raw_clk_enable, \ | ||
| 140 | .disable = _raw_clk_disable, \ | ||
| 141 | .parent = &pll_clk, \ | ||
| 142 | } | ||
| 143 | |||
| 144 | _DEFINE_CLOCK_REF(ref_cpu_clk, FRAC, CPU); | ||
| 145 | _DEFINE_CLOCK_REF(ref_emi_clk, FRAC, EMI); | ||
| 146 | _DEFINE_CLOCK_REF(ref_pix_clk, FRAC, PIX); | ||
| 147 | _DEFINE_CLOCK_REF(ref_io_clk, FRAC, IO); | ||
| 148 | |||
| 149 | /* | ||
| 150 | * General clocks | ||
| 151 | * | ||
| 152 | * clk_get_rate | ||
| 153 | */ | ||
| 154 | static unsigned long rtc_clk_get_rate(struct clk *clk) | ||
| 155 | { | ||
| 156 | /* ref_xtal_clk is implemented as the only parent */ | ||
| 157 | return clk_get_rate(clk->parent) / 768; | ||
| 158 | } | ||
| 159 | |||
| 160 | static unsigned long clk32k_clk_get_rate(struct clk *clk) | ||
| 161 | { | ||
| 162 | return clk->parent->get_rate(clk->parent) / 750; | ||
| 163 | } | ||
| 164 | |||
| 165 | #define _CLK_GET_RATE(name, rs) \ | ||
| 166 | static unsigned long name##_get_rate(struct clk *clk) \ | ||
| 167 | { \ | ||
| 168 | u32 reg, div; \ | ||
| 169 | \ | ||
| 170 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \ | ||
| 171 | \ | ||
| 172 | if (clk->parent == &ref_xtal_clk) \ | ||
| 173 | div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >> \ | ||
| 174 | BP_CLKCTRL_##rs##_DIV_XTAL; \ | ||
| 175 | else \ | ||
| 176 | div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >> \ | ||
| 177 | BP_CLKCTRL_##rs##_DIV_##rs; \ | ||
| 178 | \ | ||
| 179 | if (!div) \ | ||
| 180 | return -EINVAL; \ | ||
| 181 | \ | ||
| 182 | return clk_get_rate(clk->parent) / div; \ | ||
| 183 | } | ||
| 184 | |||
| 185 | _CLK_GET_RATE(cpu_clk, CPU) | ||
| 186 | _CLK_GET_RATE(emi_clk, EMI) | ||
| 187 | |||
| 188 | #define _CLK_GET_RATE1(name, rs) \ | ||
| 189 | static unsigned long name##_get_rate(struct clk *clk) \ | ||
| 190 | { \ | ||
| 191 | u32 reg, div; \ | ||
| 192 | \ | ||
| 193 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \ | ||
| 194 | div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV; \ | ||
| 195 | \ | ||
| 196 | if (!div) \ | ||
| 197 | return -EINVAL; \ | ||
| 198 | \ | ||
| 199 | return clk_get_rate(clk->parent) / div; \ | ||
| 200 | } | ||
| 201 | |||
| 202 | _CLK_GET_RATE1(hbus_clk, HBUS) | ||
| 203 | _CLK_GET_RATE1(xbus_clk, XBUS) | ||
| 204 | _CLK_GET_RATE1(ssp_clk, SSP) | ||
| 205 | _CLK_GET_RATE1(gpmi_clk, GPMI) | ||
| 206 | _CLK_GET_RATE1(lcdif_clk, PIX) | ||
| 207 | |||
| 208 | #define _CLK_GET_RATE_STUB(name) \ | ||
| 209 | static unsigned long name##_get_rate(struct clk *clk) \ | ||
| 210 | { \ | ||
| 211 | return clk_get_rate(clk->parent); \ | ||
| 212 | } | ||
| 213 | |||
| 214 | _CLK_GET_RATE_STUB(uart_clk) | ||
| 215 | _CLK_GET_RATE_STUB(audio_clk) | ||
| 216 | _CLK_GET_RATE_STUB(pwm_clk) | ||
| 217 | |||
| 218 | /* | ||
| 219 | * clk_set_rate | ||
| 220 | */ | ||
| 221 | static int cpu_clk_set_rate(struct clk *clk, unsigned long rate) | ||
| 222 | { | ||
| 223 | u32 reg, bm_busy, div_max, d, f, div, frac; | ||
| 224 | unsigned long diff, parent_rate, calc_rate; | ||
| 225 | int i; | ||
| 226 | |||
| 227 | parent_rate = clk_get_rate(clk->parent); | ||
| 228 | |||
| 229 | if (clk->parent == &ref_xtal_clk) { | ||
| 230 | div_max = BM_CLKCTRL_CPU_DIV_XTAL >> BP_CLKCTRL_CPU_DIV_XTAL; | ||
| 231 | bm_busy = BM_CLKCTRL_CPU_BUSY_REF_XTAL; | ||
| 232 | div = DIV_ROUND_UP(parent_rate, rate); | ||
| 233 | if (div == 0 || div > div_max) | ||
| 234 | return -EINVAL; | ||
| 235 | } else { | ||
| 236 | div_max = BM_CLKCTRL_CPU_DIV_CPU >> BP_CLKCTRL_CPU_DIV_CPU; | ||
| 237 | bm_busy = BM_CLKCTRL_CPU_BUSY_REF_CPU; | ||
| 238 | rate >>= PARENT_RATE_SHIFT; | ||
| 239 | parent_rate >>= PARENT_RATE_SHIFT; | ||
| 240 | diff = parent_rate; | ||
| 241 | div = frac = 1; | ||
| 242 | for (d = 1; d <= div_max; d++) { | ||
| 243 | f = parent_rate * 18 / d / rate; | ||
| 244 | if ((parent_rate * 18 / d) % rate) | ||
| 245 | f++; | ||
| 246 | if (f < 18 || f > 35) | ||
| 247 | continue; | ||
| 248 | |||
| 249 | calc_rate = parent_rate * 18 / f / d; | ||
| 250 | if (calc_rate > rate) | ||
| 251 | continue; | ||
| 252 | |||
| 253 | if (rate - calc_rate < diff) { | ||
| 254 | frac = f; | ||
| 255 | div = d; | ||
| 256 | diff = rate - calc_rate; | ||
| 257 | } | ||
| 258 | |||
| 259 | if (diff == 0) | ||
| 260 | break; | ||
| 261 | } | ||
| 262 | |||
| 263 | if (diff == parent_rate) | ||
| 264 | return -EINVAL; | ||
| 265 | |||
| 266 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC); | ||
| 267 | reg &= ~BM_CLKCTRL_FRAC_CPUFRAC; | ||
| 268 | reg |= frac; | ||
| 269 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC); | ||
| 270 | } | ||
| 271 | |||
| 272 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU); | ||
| 273 | reg &= ~BM_CLKCTRL_CPU_DIV_CPU; | ||
| 274 | reg |= div << BP_CLKCTRL_CPU_DIV_CPU; | ||
| 275 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU); | ||
| 276 | |||
| 277 | for (i = 10000; i; i--) | ||
| 278 | if (!(__raw_readl(CLKCTRL_BASE_ADDR + | ||
| 279 | HW_CLKCTRL_CPU) & bm_busy)) | ||
| 280 | break; | ||
| 281 | if (!i) { | ||
| 282 | pr_err("%s: divider writing timeout\n", __func__); | ||
| 283 | return -ETIMEDOUT; | ||
| 284 | } | ||
| 285 | |||
| 286 | return 0; | ||
| 287 | } | ||
| 288 | |||
| 289 | #define _CLK_SET_RATE(name, dr) \ | ||
| 290 | static int name##_set_rate(struct clk *clk, unsigned long rate) \ | ||
| 291 | { \ | ||
| 292 | u32 reg, div_max, div; \ | ||
| 293 | unsigned long parent_rate; \ | ||
| 294 | int i; \ | ||
| 295 | \ | ||
| 296 | parent_rate = clk_get_rate(clk->parent); \ | ||
| 297 | div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \ | ||
| 298 | \ | ||
| 299 | div = DIV_ROUND_UP(parent_rate, rate); \ | ||
| 300 | if (div == 0 || div > div_max) \ | ||
| 301 | return -EINVAL; \ | ||
| 302 | \ | ||
| 303 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \ | ||
| 304 | reg &= ~BM_CLKCTRL_##dr##_DIV; \ | ||
| 305 | reg |= div << BP_CLKCTRL_##dr##_DIV; \ | ||
| 306 | if (reg | (1 << clk->enable_shift)) { \ | ||
| 307 | pr_err("%s: clock is gated\n", __func__); \ | ||
| 308 | return -EINVAL; \ | ||
| 309 | } \ | ||
| 310 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \ | ||
| 311 | \ | ||
| 312 | for (i = 10000; i; i--) \ | ||
| 313 | if (!(__raw_readl(CLKCTRL_BASE_ADDR + \ | ||
| 314 | HW_CLKCTRL_##dr) & BM_CLKCTRL_##dr##_BUSY)) \ | ||
| 315 | break; \ | ||
| 316 | if (!i) { \ | ||
| 317 | pr_err("%s: divider writing timeout\n", __func__); \ | ||
| 318 | return -ETIMEDOUT; \ | ||
| 319 | } \ | ||
| 320 | \ | ||
| 321 | return 0; \ | ||
| 322 | } | ||
| 323 | |||
| 324 | _CLK_SET_RATE(xbus_clk, XBUS) | ||
| 325 | _CLK_SET_RATE(ssp_clk, SSP) | ||
| 326 | _CLK_SET_RATE(gpmi_clk, GPMI) | ||
| 327 | _CLK_SET_RATE(lcdif_clk, PIX) | ||
| 328 | |||
| 329 | #define _CLK_SET_RATE_STUB(name) \ | ||
| 330 | static int name##_set_rate(struct clk *clk, unsigned long rate) \ | ||
| 331 | { \ | ||
| 332 | return -EINVAL; \ | ||
| 333 | } | ||
| 334 | |||
| 335 | _CLK_SET_RATE_STUB(emi_clk) | ||
| 336 | _CLK_SET_RATE_STUB(uart_clk) | ||
| 337 | _CLK_SET_RATE_STUB(audio_clk) | ||
| 338 | _CLK_SET_RATE_STUB(pwm_clk) | ||
| 339 | _CLK_SET_RATE_STUB(clk32k_clk) | ||
| 340 | |||
| 341 | /* | ||
| 342 | * clk_set_parent | ||
| 343 | */ | ||
| 344 | #define _CLK_SET_PARENT(name, bit) \ | ||
| 345 | static int name##_set_parent(struct clk *clk, struct clk *parent) \ | ||
| 346 | { \ | ||
| 347 | if (parent != clk->parent) { \ | ||
| 348 | __raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit, \ | ||
| 349 | HW_CLKCTRL_CLKSEQ_TOG); \ | ||
| 350 | clk->parent = parent; \ | ||
| 351 | } \ | ||
| 352 | \ | ||
| 353 | return 0; \ | ||
| 354 | } | ||
| 355 | |||
| 356 | _CLK_SET_PARENT(cpu_clk, CPU) | ||
| 357 | _CLK_SET_PARENT(emi_clk, EMI) | ||
| 358 | _CLK_SET_PARENT(ssp_clk, SSP) | ||
| 359 | _CLK_SET_PARENT(gpmi_clk, GPMI) | ||
| 360 | _CLK_SET_PARENT(lcdif_clk, PIX) | ||
| 361 | |||
| 362 | #define _CLK_SET_PARENT_STUB(name) \ | ||
| 363 | static int name##_set_parent(struct clk *clk, struct clk *parent) \ | ||
| 364 | { \ | ||
| 365 | if (parent != clk->parent) \ | ||
| 366 | return -EINVAL; \ | ||
| 367 | else \ | ||
| 368 | return 0; \ | ||
| 369 | } | ||
| 370 | |||
| 371 | _CLK_SET_PARENT_STUB(uart_clk) | ||
| 372 | _CLK_SET_PARENT_STUB(audio_clk) | ||
| 373 | _CLK_SET_PARENT_STUB(pwm_clk) | ||
| 374 | _CLK_SET_PARENT_STUB(clk32k_clk) | ||
| 375 | |||
| 376 | /* | ||
| 377 | * clk definition | ||
| 378 | */ | ||
| 379 | static struct clk cpu_clk = { | ||
| 380 | .get_rate = cpu_clk_get_rate, | ||
| 381 | .set_rate = cpu_clk_set_rate, | ||
| 382 | .set_parent = cpu_clk_set_parent, | ||
| 383 | .parent = &ref_cpu_clk, | ||
| 384 | }; | ||
| 385 | |||
| 386 | static struct clk hbus_clk = { | ||
| 387 | .get_rate = hbus_clk_get_rate, | ||
| 388 | .parent = &cpu_clk, | ||
| 389 | }; | ||
| 390 | |||
| 391 | static struct clk xbus_clk = { | ||
| 392 | .get_rate = xbus_clk_get_rate, | ||
| 393 | .set_rate = xbus_clk_set_rate, | ||
| 394 | .parent = &ref_xtal_clk, | ||
| 395 | }; | ||
| 396 | |||
| 397 | static struct clk rtc_clk = { | ||
| 398 | .get_rate = rtc_clk_get_rate, | ||
| 399 | .parent = &ref_xtal_clk, | ||
| 400 | }; | ||
| 401 | |||
| 402 | /* usb_clk gate is controlled in DIGCTRL other than CLKCTRL */ | ||
| 403 | static struct clk usb_clk = { | ||
| 404 | .enable_reg = DIGCTRL_BASE_ADDR, | ||
| 405 | .enable_shift = 2, | ||
| 406 | .enable = _raw_clk_enable, | ||
| 407 | .disable = _raw_clk_disable, | ||
| 408 | .parent = &pll_clk, | ||
| 409 | }; | ||
| 410 | |||
| 411 | #define _DEFINE_CLOCK(name, er, es, p) \ | ||
| 412 | static struct clk name = { \ | ||
| 413 | .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \ | ||
| 414 | .enable_shift = BP_CLKCTRL_##er##_##es, \ | ||
| 415 | .get_rate = name##_get_rate, \ | ||
| 416 | .set_rate = name##_set_rate, \ | ||
| 417 | .set_parent = name##_set_parent, \ | ||
| 418 | .enable = _raw_clk_enable, \ | ||
| 419 | .disable = _raw_clk_disable, \ | ||
| 420 | .parent = p, \ | ||
| 421 | } | ||
| 422 | |||
| 423 | _DEFINE_CLOCK(emi_clk, EMI, CLKGATE, &ref_xtal_clk); | ||
| 424 | _DEFINE_CLOCK(ssp_clk, SSP, CLKGATE, &ref_xtal_clk); | ||
| 425 | _DEFINE_CLOCK(gpmi_clk, GPMI, CLKGATE, &ref_xtal_clk); | ||
| 426 | _DEFINE_CLOCK(lcdif_clk, PIX, CLKGATE, &ref_xtal_clk); | ||
| 427 | _DEFINE_CLOCK(uart_clk, XTAL, UART_CLK_GATE, &ref_xtal_clk); | ||
| 428 | _DEFINE_CLOCK(audio_clk, XTAL, FILT_CLK24M_GATE, &ref_xtal_clk); | ||
| 429 | _DEFINE_CLOCK(pwm_clk, XTAL, PWM_CLK24M_GATE, &ref_xtal_clk); | ||
| 430 | _DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk); | ||
| 431 | |||
| 432 | #define _REGISTER_CLOCK(d, n, c) \ | ||
| 433 | { \ | ||
| 434 | .dev_id = d, \ | ||
| 435 | .con_id = n, \ | ||
| 436 | .clk = &c, \ | ||
| 437 | }, | ||
| 438 | |||
| 439 | static struct clk_lookup lookups[] = { | ||
| 440 | _REGISTER_CLOCK("mxs-duart.0", NULL, uart_clk) | ||
| 441 | _REGISTER_CLOCK("rtc", NULL, rtc_clk) | ||
| 442 | _REGISTER_CLOCK(NULL, "hclk", hbus_clk) | ||
| 443 | _REGISTER_CLOCK(NULL, "xclk", xbus_clk) | ||
| 444 | _REGISTER_CLOCK(NULL, "usb", usb_clk) | ||
| 445 | _REGISTER_CLOCK(NULL, "audio", audio_clk) | ||
| 446 | _REGISTER_CLOCK(NULL, "pwm", pwm_clk) | ||
| 447 | }; | ||
| 448 | |||
| 449 | static int clk_misc_init(void) | ||
| 450 | { | ||
| 451 | u32 reg; | ||
| 452 | int i; | ||
| 453 | |||
| 454 | /* Fix up parent per register setting */ | ||
| 455 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ); | ||
| 456 | cpu_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) ? | ||
| 457 | &ref_xtal_clk : &ref_cpu_clk; | ||
| 458 | emi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) ? | ||
| 459 | &ref_xtal_clk : &ref_emi_clk; | ||
| 460 | ssp_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP) ? | ||
| 461 | &ref_xtal_clk : &ref_io_clk; | ||
| 462 | gpmi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) ? | ||
| 463 | &ref_xtal_clk : &ref_io_clk; | ||
| 464 | lcdif_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_PIX) ? | ||
| 465 | &ref_xtal_clk : &ref_pix_clk; | ||
| 466 | |||
| 467 | /* Use int div over frac when both are available */ | ||
| 468 | __raw_writel(BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN, | ||
| 469 | CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR); | ||
| 470 | __raw_writel(BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN, | ||
| 471 | CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR); | ||
| 472 | __raw_writel(BM_CLKCTRL_HBUS_DIV_FRAC_EN, | ||
| 473 | CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR); | ||
| 474 | |||
| 475 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS); | ||
| 476 | reg &= ~BM_CLKCTRL_XBUS_DIV_FRAC_EN; | ||
| 477 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS); | ||
| 478 | |||
| 479 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP); | ||
| 480 | reg &= ~BM_CLKCTRL_SSP_DIV_FRAC_EN; | ||
| 481 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP); | ||
| 482 | |||
| 483 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI); | ||
| 484 | reg &= ~BM_CLKCTRL_GPMI_DIV_FRAC_EN; | ||
| 485 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI); | ||
| 486 | |||
| 487 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX); | ||
| 488 | reg &= ~BM_CLKCTRL_PIX_DIV_FRAC_EN; | ||
| 489 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX); | ||
| 490 | |||
| 491 | /* | ||
| 492 | * Set safe hbus clock divider. A divider of 3 ensure that | ||
| 493 | * the Vddd voltage required for the cpu clock is sufficiently | ||
| 494 | * high for the hbus clock. | ||
| 495 | */ | ||
| 496 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); | ||
| 497 | reg &= BM_CLKCTRL_HBUS_DIV; | ||
| 498 | reg |= 3 << BP_CLKCTRL_HBUS_DIV; | ||
| 499 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); | ||
| 500 | |||
| 501 | for (i = 10000; i; i--) | ||
| 502 | if (!(__raw_readl(CLKCTRL_BASE_ADDR + | ||
| 503 | HW_CLKCTRL_HBUS) & BM_CLKCTRL_HBUS_BUSY)) | ||
| 504 | break; | ||
| 505 | if (!i) { | ||
| 506 | pr_err("%s: divider writing timeout\n", __func__); | ||
| 507 | return -ETIMEDOUT; | ||
| 508 | } | ||
| 509 | |||
| 510 | /* Gate off cpu clock in WFI for power saving */ | ||
| 511 | __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT, | ||
| 512 | CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET); | ||
| 513 | |||
| 514 | return 0; | ||
| 515 | } | ||
| 516 | |||
| 517 | int __init mx23_clocks_init(void) | ||
| 518 | { | ||
| 519 | clk_misc_init(); | ||
| 520 | |||
| 521 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); | ||
| 522 | |||
| 523 | mxs_timer_init(&clk32k_clk, MX23_INT_TIMER0); | ||
| 524 | |||
| 525 | return 0; | ||
| 526 | } | ||
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c new file mode 100644 index 000000000000..74e2103c6011 --- /dev/null +++ b/arch/arm/mach-mxs/clock-mx28.c | |||
| @@ -0,0 +1,734 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License along | ||
| 15 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/mm.h> | ||
| 20 | #include <linux/delay.h> | ||
| 21 | #include <linux/clk.h> | ||
| 22 | #include <linux/io.h> | ||
| 23 | #include <linux/jiffies.h> | ||
| 24 | |||
| 25 | #include <asm/clkdev.h> | ||
| 26 | #include <asm/div64.h> | ||
| 27 | |||
| 28 | #include <mach/mx28.h> | ||
| 29 | #include <mach/common.h> | ||
| 30 | #include <mach/clock.h> | ||
| 31 | |||
| 32 | #include "regs-clkctrl-mx28.h" | ||
| 33 | |||
| 34 | #define CLKCTRL_BASE_ADDR MX28_IO_ADDRESS(MX28_CLKCTRL_BASE_ADDR) | ||
| 35 | #define DIGCTRL_BASE_ADDR MX28_IO_ADDRESS(MX28_DIGCTL_BASE_ADDR) | ||
| 36 | |||
| 37 | #define PARENT_RATE_SHIFT 8 | ||
| 38 | |||
| 39 | static struct clk pll2_clk; | ||
| 40 | static struct clk cpu_clk; | ||
| 41 | static struct clk emi_clk; | ||
| 42 | static struct clk saif0_clk; | ||
| 43 | static struct clk saif1_clk; | ||
| 44 | static struct clk clk32k_clk; | ||
| 45 | |||
| 46 | static int _raw_clk_enable(struct clk *clk) | ||
| 47 | { | ||
| 48 | u32 reg; | ||
| 49 | |||
| 50 | if (clk->enable_reg) { | ||
| 51 | reg = __raw_readl(clk->enable_reg); | ||
| 52 | reg &= ~(1 << clk->enable_shift); | ||
| 53 | __raw_writel(reg, clk->enable_reg); | ||
| 54 | } | ||
| 55 | |||
| 56 | return 0; | ||
| 57 | } | ||
| 58 | |||
| 59 | static void _raw_clk_disable(struct clk *clk) | ||
| 60 | { | ||
| 61 | u32 reg; | ||
| 62 | |||
| 63 | if (clk->enable_reg) { | ||
| 64 | reg = __raw_readl(clk->enable_reg); | ||
| 65 | reg |= 1 << clk->enable_shift; | ||
| 66 | __raw_writel(reg, clk->enable_reg); | ||
| 67 | } | ||
| 68 | } | ||
| 69 | |||
| 70 | /* | ||
| 71 | * ref_xtal_clk | ||
| 72 | */ | ||
| 73 | static unsigned long ref_xtal_clk_get_rate(struct clk *clk) | ||
| 74 | { | ||
| 75 | return 24000000; | ||
| 76 | } | ||
| 77 | |||
| 78 | static struct clk ref_xtal_clk = { | ||
| 79 | .get_rate = ref_xtal_clk_get_rate, | ||
| 80 | }; | ||
| 81 | |||
| 82 | /* | ||
| 83 | * pll_clk | ||
| 84 | */ | ||
| 85 | static unsigned long pll0_clk_get_rate(struct clk *clk) | ||
| 86 | { | ||
| 87 | return 480000000; | ||
| 88 | } | ||
| 89 | |||
| 90 | static unsigned long pll1_clk_get_rate(struct clk *clk) | ||
| 91 | { | ||
| 92 | return 480000000; | ||
| 93 | } | ||
| 94 | |||
| 95 | static unsigned long pll2_clk_get_rate(struct clk *clk) | ||
| 96 | { | ||
| 97 | return 50000000; | ||
| 98 | } | ||
| 99 | |||
| 100 | #define _CLK_ENABLE_PLL(name, r, g) \ | ||
| 101 | static int name##_enable(struct clk *clk) \ | ||
| 102 | { \ | ||
| 103 | __raw_writel(BM_CLKCTRL_##r##CTRL0_POWER, \ | ||
| 104 | CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \ | ||
| 105 | udelay(10); \ | ||
| 106 | \ | ||
| 107 | if (clk == &pll2_clk) \ | ||
| 108 | __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \ | ||
| 109 | CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \ | ||
| 110 | else \ | ||
| 111 | __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \ | ||
| 112 | CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \ | ||
| 113 | \ | ||
| 114 | return 0; \ | ||
| 115 | } | ||
| 116 | |||
| 117 | _CLK_ENABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS) | ||
| 118 | _CLK_ENABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS) | ||
| 119 | _CLK_ENABLE_PLL(pll2_clk, PLL2, CLKGATE) | ||
| 120 | |||
| 121 | #define _CLK_DISABLE_PLL(name, r, g) \ | ||
| 122 | static void name##_disable(struct clk *clk) \ | ||
| 123 | { \ | ||
| 124 | __raw_writel(BM_CLKCTRL_##r##CTRL0_POWER, \ | ||
| 125 | CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \ | ||
| 126 | \ | ||
| 127 | if (clk == &pll2_clk) \ | ||
| 128 | __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \ | ||
| 129 | CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \ | ||
| 130 | else \ | ||
| 131 | __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \ | ||
| 132 | CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \ | ||
| 133 | \ | ||
| 134 | } | ||
| 135 | |||
| 136 | _CLK_DISABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS) | ||
| 137 | _CLK_DISABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS) | ||
| 138 | _CLK_DISABLE_PLL(pll2_clk, PLL2, CLKGATE) | ||
| 139 | |||
| 140 | #define _DEFINE_CLOCK_PLL(name) \ | ||
| 141 | static struct clk name = { \ | ||
| 142 | .get_rate = name##_get_rate, \ | ||
| 143 | .enable = name##_enable, \ | ||
| 144 | .disable = name##_disable, \ | ||
| 145 | .parent = &ref_xtal_clk, \ | ||
| 146 | } | ||
| 147 | |||
| 148 | _DEFINE_CLOCK_PLL(pll0_clk); | ||
| 149 | _DEFINE_CLOCK_PLL(pll1_clk); | ||
| 150 | _DEFINE_CLOCK_PLL(pll2_clk); | ||
| 151 | |||
| 152 | /* | ||
| 153 | * ref_clk | ||
| 154 | */ | ||
| 155 | #define _CLK_GET_RATE_REF(name, sr, ss) \ | ||
| 156 | static unsigned long name##_get_rate(struct clk *clk) \ | ||
| 157 | { \ | ||
| 158 | unsigned long parent_rate; \ | ||
| 159 | u32 reg, div; \ | ||
| 160 | \ | ||
| 161 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##sr); \ | ||
| 162 | div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f; \ | ||
| 163 | parent_rate = clk_get_rate(clk->parent); \ | ||
| 164 | \ | ||
| 165 | return SH_DIV((parent_rate >> PARENT_RATE_SHIFT) * 18, \ | ||
| 166 | div, PARENT_RATE_SHIFT); \ | ||
| 167 | } | ||
| 168 | |||
| 169 | _CLK_GET_RATE_REF(ref_cpu_clk, FRAC0, CPU) | ||
| 170 | _CLK_GET_RATE_REF(ref_emi_clk, FRAC0, EMI) | ||
| 171 | _CLK_GET_RATE_REF(ref_io0_clk, FRAC0, IO0) | ||
| 172 | _CLK_GET_RATE_REF(ref_io1_clk, FRAC0, IO1) | ||
| 173 | _CLK_GET_RATE_REF(ref_pix_clk, FRAC1, PIX) | ||
| 174 | _CLK_GET_RATE_REF(ref_gpmi_clk, FRAC1, GPMI) | ||
| 175 | |||
| 176 | #define _DEFINE_CLOCK_REF(name, er, es) \ | ||
| 177 | static struct clk name = { \ | ||
| 178 | .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \ | ||
| 179 | .enable_shift = BP_CLKCTRL_##er##_CLKGATE##es, \ | ||
| 180 | .get_rate = name##_get_rate, \ | ||
| 181 | .enable = _raw_clk_enable, \ | ||
| 182 | .disable = _raw_clk_disable, \ | ||
| 183 | .parent = &pll0_clk, \ | ||
| 184 | } | ||
| 185 | |||
| 186 | _DEFINE_CLOCK_REF(ref_cpu_clk, FRAC0, CPU); | ||
| 187 | _DEFINE_CLOCK_REF(ref_emi_clk, FRAC0, EMI); | ||
| 188 | _DEFINE_CLOCK_REF(ref_io0_clk, FRAC0, IO0); | ||
| 189 | _DEFINE_CLOCK_REF(ref_io1_clk, FRAC0, IO1); | ||
| 190 | _DEFINE_CLOCK_REF(ref_pix_clk, FRAC1, PIX); | ||
| 191 | _DEFINE_CLOCK_REF(ref_gpmi_clk, FRAC1, GPMI); | ||
| 192 | |||
| 193 | /* | ||
| 194 | * General clocks | ||
| 195 | * | ||
| 196 | * clk_get_rate | ||
| 197 | */ | ||
| 198 | static unsigned long lradc_clk_get_rate(struct clk *clk) | ||
| 199 | { | ||
| 200 | return clk_get_rate(clk->parent) / 16; | ||
| 201 | } | ||
| 202 | |||
| 203 | static unsigned long rtc_clk_get_rate(struct clk *clk) | ||
| 204 | { | ||
| 205 | /* ref_xtal_clk is implemented as the only parent */ | ||
| 206 | return clk_get_rate(clk->parent) / 768; | ||
| 207 | } | ||
| 208 | |||
| 209 | static unsigned long clk32k_clk_get_rate(struct clk *clk) | ||
| 210 | { | ||
| 211 | return clk->parent->get_rate(clk->parent) / 750; | ||
| 212 | } | ||
| 213 | |||
| 214 | static unsigned long spdif_clk_get_rate(struct clk *clk) | ||
| 215 | { | ||
| 216 | return clk_get_rate(clk->parent) / 4; | ||
| 217 | } | ||
| 218 | |||
| 219 | #define _CLK_GET_RATE(name, rs) \ | ||
| 220 | static unsigned long name##_get_rate(struct clk *clk) \ | ||
| 221 | { \ | ||
| 222 | u32 reg, div; \ | ||
| 223 | \ | ||
| 224 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \ | ||
| 225 | \ | ||
| 226 | if (clk->parent == &ref_xtal_clk) \ | ||
| 227 | div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >> \ | ||
| 228 | BP_CLKCTRL_##rs##_DIV_XTAL; \ | ||
| 229 | else \ | ||
| 230 | div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >> \ | ||
| 231 | BP_CLKCTRL_##rs##_DIV_##rs; \ | ||
| 232 | \ | ||
| 233 | if (!div) \ | ||
| 234 | return -EINVAL; \ | ||
| 235 | \ | ||
| 236 | return clk_get_rate(clk->parent) / div; \ | ||
| 237 | } | ||
| 238 | |||
| 239 | _CLK_GET_RATE(cpu_clk, CPU) | ||
| 240 | _CLK_GET_RATE(emi_clk, EMI) | ||
| 241 | |||
| 242 | #define _CLK_GET_RATE1(name, rs) \ | ||
| 243 | static unsigned long name##_get_rate(struct clk *clk) \ | ||
| 244 | { \ | ||
| 245 | u32 reg, div; \ | ||
| 246 | \ | ||
| 247 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \ | ||
| 248 | div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV; \ | ||
| 249 | \ | ||
| 250 | if (!div) \ | ||
| 251 | return -EINVAL; \ | ||
| 252 | \ | ||
| 253 | if (clk == &saif0_clk || clk == &saif1_clk) \ | ||
| 254 | return clk_get_rate(clk->parent) >> 16 * div; \ | ||
| 255 | else \ | ||
| 256 | return clk_get_rate(clk->parent) / div; \ | ||
| 257 | } | ||
| 258 | |||
| 259 | _CLK_GET_RATE1(hbus_clk, HBUS) | ||
| 260 | _CLK_GET_RATE1(xbus_clk, XBUS) | ||
| 261 | _CLK_GET_RATE1(ssp0_clk, SSP0) | ||
| 262 | _CLK_GET_RATE1(ssp1_clk, SSP1) | ||
| 263 | _CLK_GET_RATE1(ssp2_clk, SSP2) | ||
| 264 | _CLK_GET_RATE1(ssp3_clk, SSP3) | ||
| 265 | _CLK_GET_RATE1(gpmi_clk, GPMI) | ||
| 266 | _CLK_GET_RATE1(lcdif_clk, DIS_LCDIF) | ||
| 267 | _CLK_GET_RATE1(saif0_clk, SAIF0) | ||
| 268 | _CLK_GET_RATE1(saif1_clk, SAIF1) | ||
| 269 | |||
| 270 | #define _CLK_GET_RATE_STUB(name) \ | ||
| 271 | static unsigned long name##_get_rate(struct clk *clk) \ | ||
| 272 | { \ | ||
| 273 | return clk_get_rate(clk->parent); \ | ||
| 274 | } | ||
| 275 | |||
| 276 | _CLK_GET_RATE_STUB(uart_clk) | ||
| 277 | _CLK_GET_RATE_STUB(pwm_clk) | ||
| 278 | _CLK_GET_RATE_STUB(can0_clk) | ||
| 279 | _CLK_GET_RATE_STUB(can1_clk) | ||
| 280 | _CLK_GET_RATE_STUB(fec_clk) | ||
| 281 | |||
| 282 | /* | ||
| 283 | * clk_set_rate | ||
| 284 | */ | ||
| 285 | /* fool compiler */ | ||
| 286 | #define BM_CLKCTRL_CPU_DIV 0 | ||
| 287 | #define BP_CLKCTRL_CPU_DIV 0 | ||
| 288 | #define BM_CLKCTRL_CPU_BUSY 0 | ||
| 289 | |||
| 290 | #define _CLK_SET_RATE(name, dr, fr, fs) \ | ||
| 291 | static int name##_set_rate(struct clk *clk, unsigned long rate) \ | ||
| 292 | { \ | ||
| 293 | u32 reg, bm_busy, div_max, d, f, div, frac; \ | ||
| 294 | unsigned long diff, parent_rate, calc_rate; \ | ||
| 295 | int i; \ | ||
| 296 | \ | ||
| 297 | parent_rate = clk_get_rate(clk->parent); \ | ||
| 298 | div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \ | ||
| 299 | bm_busy = BM_CLKCTRL_##dr##_BUSY; \ | ||
| 300 | \ | ||
| 301 | if (clk->parent == &ref_xtal_clk) { \ | ||
| 302 | div = DIV_ROUND_UP(parent_rate, rate); \ | ||
| 303 | if (clk == &cpu_clk) { \ | ||
| 304 | div_max = BM_CLKCTRL_CPU_DIV_XTAL >> \ | ||
| 305 | BP_CLKCTRL_CPU_DIV_XTAL; \ | ||
| 306 | bm_busy = BM_CLKCTRL_CPU_BUSY_REF_XTAL; \ | ||
| 307 | } \ | ||
| 308 | if (div == 0 || div > div_max) \ | ||
| 309 | return -EINVAL; \ | ||
| 310 | } else { \ | ||
| 311 | rate >>= PARENT_RATE_SHIFT; \ | ||
| 312 | parent_rate >>= PARENT_RATE_SHIFT; \ | ||
| 313 | diff = parent_rate; \ | ||
| 314 | div = frac = 1; \ | ||
| 315 | if (clk == &cpu_clk) { \ | ||
| 316 | div_max = BM_CLKCTRL_CPU_DIV_CPU >> \ | ||
| 317 | BP_CLKCTRL_CPU_DIV_CPU; \ | ||
| 318 | bm_busy = BM_CLKCTRL_CPU_BUSY_REF_CPU; \ | ||
| 319 | } \ | ||
| 320 | for (d = 1; d <= div_max; d++) { \ | ||
| 321 | f = parent_rate * 18 / d / rate; \ | ||
| 322 | if ((parent_rate * 18 / d) % rate) \ | ||
| 323 | f++; \ | ||
| 324 | if (f < 18 || f > 35) \ | ||
| 325 | continue; \ | ||
| 326 | \ | ||
| 327 | calc_rate = parent_rate * 18 / f / d; \ | ||
| 328 | if (calc_rate > rate) \ | ||
| 329 | continue; \ | ||
| 330 | \ | ||
| 331 | if (rate - calc_rate < diff) { \ | ||
| 332 | frac = f; \ | ||
| 333 | div = d; \ | ||
| 334 | diff = rate - calc_rate; \ | ||
| 335 | } \ | ||
| 336 | \ | ||
| 337 | if (diff == 0) \ | ||
| 338 | break; \ | ||
| 339 | } \ | ||
| 340 | \ | ||
| 341 | if (diff == parent_rate) \ | ||
| 342 | return -EINVAL; \ | ||
| 343 | \ | ||
| 344 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \ | ||
| 345 | reg &= ~BM_CLKCTRL_##fr##_##fs##FRAC; \ | ||
| 346 | reg |= frac; \ | ||
| 347 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \ | ||
| 348 | } \ | ||
| 349 | \ | ||
| 350 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \ | ||
| 351 | if (clk == &cpu_clk) { \ | ||
| 352 | reg &= ~BM_CLKCTRL_CPU_DIV_CPU; \ | ||
| 353 | reg |= div << BP_CLKCTRL_CPU_DIV_CPU; \ | ||
| 354 | } else { \ | ||
| 355 | reg &= ~BM_CLKCTRL_##dr##_DIV; \ | ||
| 356 | reg |= div << BP_CLKCTRL_##dr##_DIV; \ | ||
| 357 | if (reg | (1 << clk->enable_shift)) { \ | ||
| 358 | pr_err("%s: clock is gated\n", __func__); \ | ||
| 359 | return -EINVAL; \ | ||
| 360 | } \ | ||
| 361 | } \ | ||
| 362 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU); \ | ||
| 363 | \ | ||
| 364 | for (i = 10000; i; i--) \ | ||
| 365 | if (!(__raw_readl(CLKCTRL_BASE_ADDR + \ | ||
| 366 | HW_CLKCTRL_##dr) & bm_busy)) \ | ||
| 367 | break; \ | ||
| 368 | if (!i) { \ | ||
| 369 | pr_err("%s: divider writing timeout\n", __func__); \ | ||
| 370 | return -ETIMEDOUT; \ | ||
| 371 | } \ | ||
| 372 | \ | ||
| 373 | return 0; \ | ||
| 374 | } | ||
| 375 | |||
| 376 | _CLK_SET_RATE(cpu_clk, CPU, FRAC0, CPU) | ||
| 377 | _CLK_SET_RATE(ssp0_clk, SSP0, FRAC0, IO0) | ||
| 378 | _CLK_SET_RATE(ssp1_clk, SSP1, FRAC0, IO0) | ||
| 379 | _CLK_SET_RATE(ssp2_clk, SSP2, FRAC0, IO1) | ||
| 380 | _CLK_SET_RATE(ssp3_clk, SSP3, FRAC0, IO1) | ||
| 381 | _CLK_SET_RATE(lcdif_clk, DIS_LCDIF, FRAC1, PIX) | ||
| 382 | _CLK_SET_RATE(gpmi_clk, GPMI, FRAC1, GPMI) | ||
| 383 | |||
| 384 | #define _CLK_SET_RATE1(name, dr) \ | ||
| 385 | static int name##_set_rate(struct clk *clk, unsigned long rate) \ | ||
| 386 | { \ | ||
| 387 | u32 reg, div_max, div; \ | ||
| 388 | unsigned long parent_rate; \ | ||
| 389 | int i; \ | ||
| 390 | \ | ||
| 391 | parent_rate = clk_get_rate(clk->parent); \ | ||
| 392 | div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \ | ||
| 393 | \ | ||
| 394 | div = DIV_ROUND_UP(parent_rate, rate); \ | ||
| 395 | if (div == 0 || div > div_max) \ | ||
| 396 | return -EINVAL; \ | ||
| 397 | \ | ||
| 398 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \ | ||
| 399 | reg &= ~BM_CLKCTRL_##dr##_DIV; \ | ||
| 400 | reg |= div << BP_CLKCTRL_##dr##_DIV; \ | ||
| 401 | if (reg | (1 << clk->enable_shift)) { \ | ||
| 402 | pr_err("%s: clock is gated\n", __func__); \ | ||
| 403 | return -EINVAL; \ | ||
| 404 | } \ | ||
| 405 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \ | ||
| 406 | \ | ||
| 407 | for (i = 10000; i; i--) \ | ||
| 408 | if (!(__raw_readl(CLKCTRL_BASE_ADDR + \ | ||
| 409 | HW_CLKCTRL_##dr) & BM_CLKCTRL_##dr##_BUSY)) \ | ||
| 410 | break; \ | ||
| 411 | if (!i) { \ | ||
| 412 | pr_err("%s: divider writing timeout\n", __func__); \ | ||
| 413 | return -ETIMEDOUT; \ | ||
| 414 | } \ | ||
| 415 | \ | ||
| 416 | return 0; \ | ||
| 417 | } | ||
| 418 | |||
| 419 | _CLK_SET_RATE1(xbus_clk, XBUS) | ||
| 420 | |||
| 421 | /* saif clock uses 16 bits frac div */ | ||
| 422 | #define _CLK_SET_RATE_SAIF(name, rs) \ | ||
| 423 | static int name##_set_rate(struct clk *clk, unsigned long rate) \ | ||
| 424 | { \ | ||
| 425 | u16 div; \ | ||
| 426 | u32 reg; \ | ||
| 427 | u64 lrate; \ | ||
| 428 | unsigned long parent_rate; \ | ||
| 429 | int i; \ | ||
| 430 | \ | ||
| 431 | parent_rate = clk_get_rate(clk->parent); \ | ||
| 432 | if (rate > parent_rate) \ | ||
| 433 | return -EINVAL; \ | ||
| 434 | \ | ||
| 435 | lrate = (u64)rate << 16; \ | ||
| 436 | do_div(lrate, parent_rate); \ | ||
| 437 | div = (u16)lrate; \ | ||
| 438 | \ | ||
| 439 | if (!div) \ | ||
| 440 | return -EINVAL; \ | ||
| 441 | \ | ||
| 442 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \ | ||
| 443 | reg &= ~BM_CLKCTRL_##rs##_DIV; \ | ||
| 444 | reg |= div << BP_CLKCTRL_##rs##_DIV; \ | ||
| 445 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \ | ||
| 446 | \ | ||
| 447 | for (i = 10000; i; i--) \ | ||
| 448 | if (!(__raw_readl(CLKCTRL_BASE_ADDR + \ | ||
| 449 | HW_CLKCTRL_##rs) & BM_CLKCTRL_##rs##_BUSY)) \ | ||
| 450 | break; \ | ||
| 451 | if (!i) { \ | ||
| 452 | pr_err("%s: divider writing timeout\n", __func__); \ | ||
| 453 | return -ETIMEDOUT; \ | ||
| 454 | } \ | ||
| 455 | \ | ||
| 456 | return 0; \ | ||
| 457 | } | ||
| 458 | |||
| 459 | _CLK_SET_RATE_SAIF(saif0_clk, SAIF0) | ||
| 460 | _CLK_SET_RATE_SAIF(saif1_clk, SAIF1) | ||
| 461 | |||
| 462 | #define _CLK_SET_RATE_STUB(name) \ | ||
| 463 | static int name##_set_rate(struct clk *clk, unsigned long rate) \ | ||
| 464 | { \ | ||
| 465 | return -EINVAL; \ | ||
| 466 | } | ||
| 467 | |||
| 468 | _CLK_SET_RATE_STUB(emi_clk) | ||
| 469 | _CLK_SET_RATE_STUB(uart_clk) | ||
| 470 | _CLK_SET_RATE_STUB(pwm_clk) | ||
| 471 | _CLK_SET_RATE_STUB(spdif_clk) | ||
| 472 | _CLK_SET_RATE_STUB(clk32k_clk) | ||
| 473 | _CLK_SET_RATE_STUB(can0_clk) | ||
| 474 | _CLK_SET_RATE_STUB(can1_clk) | ||
| 475 | _CLK_SET_RATE_STUB(fec_clk) | ||
| 476 | |||
| 477 | /* | ||
| 478 | * clk_set_parent | ||
| 479 | */ | ||
| 480 | #define _CLK_SET_PARENT(name, bit) \ | ||
| 481 | static int name##_set_parent(struct clk *clk, struct clk *parent) \ | ||
| 482 | { \ | ||
| 483 | if (parent != clk->parent) { \ | ||
| 484 | __raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit, \ | ||
| 485 | HW_CLKCTRL_CLKSEQ_TOG); \ | ||
| 486 | clk->parent = parent; \ | ||
| 487 | } \ | ||
| 488 | \ | ||
| 489 | return 0; \ | ||
| 490 | } | ||
| 491 | |||
| 492 | _CLK_SET_PARENT(cpu_clk, CPU) | ||
| 493 | _CLK_SET_PARENT(emi_clk, EMI) | ||
| 494 | _CLK_SET_PARENT(ssp0_clk, SSP0) | ||
| 495 | _CLK_SET_PARENT(ssp1_clk, SSP1) | ||
| 496 | _CLK_SET_PARENT(ssp2_clk, SSP2) | ||
| 497 | _CLK_SET_PARENT(ssp3_clk, SSP3) | ||
| 498 | _CLK_SET_PARENT(lcdif_clk, DIS_LCDIF) | ||
| 499 | _CLK_SET_PARENT(gpmi_clk, GPMI) | ||
| 500 | _CLK_SET_PARENT(saif0_clk, SAIF0) | ||
| 501 | _CLK_SET_PARENT(saif1_clk, SAIF1) | ||
| 502 | |||
| 503 | #define _CLK_SET_PARENT_STUB(name) \ | ||
| 504 | static int name##_set_parent(struct clk *clk, struct clk *parent) \ | ||
| 505 | { \ | ||
| 506 | if (parent != clk->parent) \ | ||
| 507 | return -EINVAL; \ | ||
| 508 | else \ | ||
| 509 | return 0; \ | ||
| 510 | } | ||
| 511 | |||
| 512 | _CLK_SET_PARENT_STUB(pwm_clk) | ||
| 513 | _CLK_SET_PARENT_STUB(uart_clk) | ||
| 514 | _CLK_SET_PARENT_STUB(clk32k_clk) | ||
| 515 | _CLK_SET_PARENT_STUB(spdif_clk) | ||
| 516 | _CLK_SET_PARENT_STUB(fec_clk) | ||
| 517 | _CLK_SET_PARENT_STUB(can0_clk) | ||
| 518 | _CLK_SET_PARENT_STUB(can1_clk) | ||
| 519 | |||
| 520 | /* | ||
| 521 | * clk definition | ||
| 522 | */ | ||
| 523 | static struct clk cpu_clk = { | ||
| 524 | .get_rate = cpu_clk_get_rate, | ||
| 525 | .set_rate = cpu_clk_set_rate, | ||
| 526 | .set_parent = cpu_clk_set_parent, | ||
| 527 | .parent = &ref_cpu_clk, | ||
| 528 | }; | ||
| 529 | |||
| 530 | static struct clk hbus_clk = { | ||
| 531 | .get_rate = hbus_clk_get_rate, | ||
| 532 | .parent = &cpu_clk, | ||
| 533 | }; | ||
| 534 | |||
| 535 | static struct clk xbus_clk = { | ||
| 536 | .get_rate = xbus_clk_get_rate, | ||
| 537 | .set_rate = xbus_clk_set_rate, | ||
| 538 | .parent = &ref_xtal_clk, | ||
| 539 | }; | ||
| 540 | |||
| 541 | static struct clk lradc_clk = { | ||
| 542 | .get_rate = lradc_clk_get_rate, | ||
| 543 | .parent = &clk32k_clk, | ||
| 544 | }; | ||
| 545 | |||
| 546 | static struct clk rtc_clk = { | ||
| 547 | .get_rate = rtc_clk_get_rate, | ||
| 548 | .parent = &ref_xtal_clk, | ||
| 549 | }; | ||
| 550 | |||
| 551 | /* usb_clk gate is controlled in DIGCTRL other than CLKCTRL */ | ||
| 552 | static struct clk usb0_clk = { | ||
| 553 | .enable_reg = DIGCTRL_BASE_ADDR, | ||
| 554 | .enable_shift = 2, | ||
| 555 | .enable = _raw_clk_enable, | ||
| 556 | .disable = _raw_clk_disable, | ||
| 557 | .parent = &pll0_clk, | ||
| 558 | }; | ||
| 559 | |||
| 560 | static struct clk usb1_clk = { | ||
| 561 | .enable_reg = DIGCTRL_BASE_ADDR, | ||
| 562 | .enable_shift = 16, | ||
| 563 | .enable = _raw_clk_enable, | ||
| 564 | .disable = _raw_clk_disable, | ||
| 565 | .parent = &pll1_clk, | ||
| 566 | }; | ||
| 567 | |||
| 568 | #define _DEFINE_CLOCK(name, er, es, p) \ | ||
| 569 | static struct clk name = { \ | ||
| 570 | .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \ | ||
| 571 | .enable_shift = BP_CLKCTRL_##er##_##es, \ | ||
| 572 | .get_rate = name##_get_rate, \ | ||
| 573 | .set_rate = name##_set_rate, \ | ||
| 574 | .set_parent = name##_set_parent, \ | ||
| 575 | .enable = _raw_clk_enable, \ | ||
| 576 | .disable = _raw_clk_disable, \ | ||
| 577 | .parent = p, \ | ||
| 578 | } | ||
| 579 | |||
| 580 | _DEFINE_CLOCK(emi_clk, EMI, CLKGATE, &ref_xtal_clk); | ||
| 581 | _DEFINE_CLOCK(ssp0_clk, SSP0, CLKGATE, &ref_xtal_clk); | ||
| 582 | _DEFINE_CLOCK(ssp1_clk, SSP1, CLKGATE, &ref_xtal_clk); | ||
| 583 | _DEFINE_CLOCK(ssp2_clk, SSP2, CLKGATE, &ref_xtal_clk); | ||
| 584 | _DEFINE_CLOCK(ssp3_clk, SSP3, CLKGATE, &ref_xtal_clk); | ||
| 585 | _DEFINE_CLOCK(lcdif_clk, DIS_LCDIF, CLKGATE, &ref_xtal_clk); | ||
| 586 | _DEFINE_CLOCK(gpmi_clk, GPMI, CLKGATE, &ref_xtal_clk); | ||
| 587 | _DEFINE_CLOCK(saif0_clk, SAIF0, CLKGATE, &ref_xtal_clk); | ||
| 588 | _DEFINE_CLOCK(saif1_clk, SAIF1, CLKGATE, &ref_xtal_clk); | ||
| 589 | _DEFINE_CLOCK(can0_clk, FLEXCAN, STOP_CAN0, &ref_xtal_clk); | ||
| 590 | _DEFINE_CLOCK(can1_clk, FLEXCAN, STOP_CAN1, &ref_xtal_clk); | ||
| 591 | _DEFINE_CLOCK(pwm_clk, XTAL, PWM_CLK24M_GATE, &ref_xtal_clk); | ||
| 592 | _DEFINE_CLOCK(uart_clk, XTAL, UART_CLK_GATE, &ref_xtal_clk); | ||
| 593 | _DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk); | ||
| 594 | _DEFINE_CLOCK(spdif_clk, SPDIF, CLKGATE, &pll0_clk); | ||
| 595 | _DEFINE_CLOCK(fec_clk, ENET, DISABLE, &hbus_clk); | ||
| 596 | |||
| 597 | #define _REGISTER_CLOCK(d, n, c) \ | ||
| 598 | { \ | ||
| 599 | .dev_id = d, \ | ||
| 600 | .con_id = n, \ | ||
| 601 | .clk = &c, \ | ||
| 602 | }, | ||
| 603 | |||
| 604 | static struct clk_lookup lookups[] = { | ||
| 605 | _REGISTER_CLOCK("mxs-duart.0", NULL, uart_clk) | ||
| 606 | _REGISTER_CLOCK("fec.0", NULL, fec_clk) | ||
| 607 | _REGISTER_CLOCK("rtc", NULL, rtc_clk) | ||
| 608 | _REGISTER_CLOCK("pll2", NULL, pll2_clk) | ||
| 609 | _REGISTER_CLOCK(NULL, "hclk", hbus_clk) | ||
| 610 | _REGISTER_CLOCK(NULL, "xclk", xbus_clk) | ||
| 611 | _REGISTER_CLOCK(NULL, "can0", can0_clk) | ||
| 612 | _REGISTER_CLOCK(NULL, "can1", can1_clk) | ||
| 613 | _REGISTER_CLOCK(NULL, "usb0", usb0_clk) | ||
| 614 | _REGISTER_CLOCK(NULL, "usb1", usb1_clk) | ||
| 615 | _REGISTER_CLOCK(NULL, "pwm", pwm_clk) | ||
| 616 | _REGISTER_CLOCK(NULL, "lradc", lradc_clk) | ||
| 617 | _REGISTER_CLOCK(NULL, "spdif", spdif_clk) | ||
| 618 | }; | ||
| 619 | |||
| 620 | static int clk_misc_init(void) | ||
| 621 | { | ||
| 622 | u32 reg; | ||
| 623 | int i; | ||
| 624 | |||
| 625 | /* Fix up parent per register setting */ | ||
| 626 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ); | ||
| 627 | cpu_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) ? | ||
| 628 | &ref_xtal_clk : &ref_cpu_clk; | ||
| 629 | emi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) ? | ||
| 630 | &ref_xtal_clk : &ref_emi_clk; | ||
| 631 | ssp0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP0) ? | ||
| 632 | &ref_xtal_clk : &ref_io0_clk; | ||
| 633 | ssp1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP1) ? | ||
| 634 | &ref_xtal_clk : &ref_io0_clk; | ||
| 635 | ssp2_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP2) ? | ||
| 636 | &ref_xtal_clk : &ref_io1_clk; | ||
| 637 | ssp3_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP3) ? | ||
| 638 | &ref_xtal_clk : &ref_io1_clk; | ||
| 639 | lcdif_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF) ? | ||
| 640 | &ref_xtal_clk : &ref_pix_clk; | ||
| 641 | gpmi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) ? | ||
| 642 | &ref_xtal_clk : &ref_gpmi_clk; | ||
| 643 | saif0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0) ? | ||
| 644 | &ref_xtal_clk : &pll0_clk; | ||
| 645 | saif1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1) ? | ||
| 646 | &ref_xtal_clk : &pll0_clk; | ||
| 647 | |||
| 648 | /* Use int div over frac when both are available */ | ||
| 649 | __raw_writel(BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN, | ||
| 650 | CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR); | ||
| 651 | __raw_writel(BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN, | ||
| 652 | CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR); | ||
| 653 | __raw_writel(BM_CLKCTRL_HBUS_DIV_FRAC_EN, | ||
| 654 | CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR); | ||
| 655 | |||
| 656 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS); | ||
| 657 | reg &= ~BM_CLKCTRL_XBUS_DIV_FRAC_EN; | ||
| 658 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS); | ||
| 659 | |||
| 660 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0); | ||
| 661 | reg &= ~BM_CLKCTRL_SSP0_DIV_FRAC_EN; | ||
| 662 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0); | ||
| 663 | |||
| 664 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1); | ||
| 665 | reg &= ~BM_CLKCTRL_SSP1_DIV_FRAC_EN; | ||
| 666 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1); | ||
| 667 | |||
| 668 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2); | ||
| 669 | reg &= ~BM_CLKCTRL_SSP2_DIV_FRAC_EN; | ||
| 670 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2); | ||
| 671 | |||
| 672 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3); | ||
| 673 | reg &= ~BM_CLKCTRL_SSP3_DIV_FRAC_EN; | ||
| 674 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3); | ||
| 675 | |||
| 676 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI); | ||
| 677 | reg &= ~BM_CLKCTRL_GPMI_DIV_FRAC_EN; | ||
| 678 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI); | ||
| 679 | |||
| 680 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF); | ||
| 681 | reg &= ~BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN; | ||
| 682 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF); | ||
| 683 | |||
| 684 | /* SAIF has to use frac div for functional operation */ | ||
| 685 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0); | ||
| 686 | reg &= ~BM_CLKCTRL_SAIF0_DIV_FRAC_EN; | ||
| 687 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0); | ||
| 688 | |||
| 689 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1); | ||
| 690 | reg &= ~BM_CLKCTRL_SAIF1_DIV_FRAC_EN; | ||
| 691 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1); | ||
| 692 | |||
| 693 | /* | ||
| 694 | * Set safe hbus clock divider. A divider of 3 ensure that | ||
| 695 | * the Vddd voltage required for the cpu clock is sufficiently | ||
| 696 | * high for the hbus clock. | ||
| 697 | */ | ||
| 698 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); | ||
| 699 | reg &= BM_CLKCTRL_HBUS_DIV; | ||
| 700 | reg |= 3 << BP_CLKCTRL_HBUS_DIV; | ||
| 701 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); | ||
| 702 | |||
| 703 | for (i = 10000; i; i--) | ||
| 704 | if (!(__raw_readl(CLKCTRL_BASE_ADDR + | ||
| 705 | HW_CLKCTRL_HBUS) & BM_CLKCTRL_HBUS_ASM_BUSY)) | ||
| 706 | break; | ||
| 707 | if (!i) { | ||
| 708 | pr_err("%s: divider writing timeout\n", __func__); | ||
| 709 | return -ETIMEDOUT; | ||
| 710 | } | ||
| 711 | |||
| 712 | /* Gate off cpu clock in WFI for power saving */ | ||
| 713 | __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT, | ||
| 714 | CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET); | ||
| 715 | |||
| 716 | /* Extra fec clock setting */ | ||
| 717 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET); | ||
| 718 | reg &= ~BM_CLKCTRL_ENET_SLEEP; | ||
| 719 | reg |= BM_CLKCTRL_ENET_CLK_OUT_EN; | ||
| 720 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET); | ||
| 721 | |||
| 722 | return 0; | ||
| 723 | } | ||
| 724 | |||
| 725 | int __init mx28_clocks_init(void) | ||
| 726 | { | ||
| 727 | clk_misc_init(); | ||
| 728 | |||
| 729 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); | ||
| 730 | |||
| 731 | mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0); | ||
| 732 | |||
| 733 | return 0; | ||
| 734 | } | ||
diff --git a/arch/arm/mach-mxs/clock.c b/arch/arm/mach-mxs/clock.c new file mode 100644 index 000000000000..e7d2269cf70e --- /dev/null +++ b/arch/arm/mach-mxs/clock.c | |||
| @@ -0,0 +1,200 @@ | |||
| 1 | /* | ||
| 2 | * Based on arch/arm/plat-omap/clock.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2004 - 2005 Nokia corporation | ||
| 5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | ||
| 6 | * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com> | ||
| 7 | * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 8 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or | ||
| 11 | * modify it under the terms of the GNU General Public License | ||
| 12 | * as published by the Free Software Foundation; either version 2 | ||
| 13 | * of the License, or (at your option) any later version. | ||
| 14 | * This program is distributed in the hope that it will be useful, | ||
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 17 | * GNU General Public License for more details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this program; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 22 | * MA 02110-1301, USA. | ||
| 23 | */ | ||
| 24 | |||
| 25 | /* #define DEBUG */ | ||
| 26 | |||
| 27 | #include <linux/clk.h> | ||
| 28 | #include <linux/err.h> | ||
| 29 | #include <linux/errno.h> | ||
| 30 | #include <linux/init.h> | ||
| 31 | #include <linux/io.h> | ||
| 32 | #include <linux/kernel.h> | ||
| 33 | #include <linux/list.h> | ||
| 34 | #include <linux/module.h> | ||
| 35 | #include <linux/mutex.h> | ||
| 36 | #include <linux/platform_device.h> | ||
| 37 | #include <linux/proc_fs.h> | ||
| 38 | #include <linux/semaphore.h> | ||
| 39 | #include <linux/string.h> | ||
| 40 | |||
| 41 | #include <mach/clock.h> | ||
| 42 | |||
| 43 | static LIST_HEAD(clocks); | ||
| 44 | static DEFINE_MUTEX(clocks_mutex); | ||
| 45 | |||
| 46 | /*------------------------------------------------------------------------- | ||
| 47 | * Standard clock functions defined in include/linux/clk.h | ||
| 48 | *-------------------------------------------------------------------------*/ | ||
| 49 | |||
| 50 | static void __clk_disable(struct clk *clk) | ||
| 51 | { | ||
| 52 | if (clk == NULL || IS_ERR(clk)) | ||
| 53 | return; | ||
| 54 | WARN_ON(!clk->usecount); | ||
| 55 | |||
| 56 | if (!(--clk->usecount)) { | ||
| 57 | if (clk->disable) | ||
| 58 | clk->disable(clk); | ||
| 59 | __clk_disable(clk->parent); | ||
| 60 | __clk_disable(clk->secondary); | ||
| 61 | } | ||
| 62 | } | ||
| 63 | |||
| 64 | static int __clk_enable(struct clk *clk) | ||
| 65 | { | ||
| 66 | if (clk == NULL || IS_ERR(clk)) | ||
| 67 | return -EINVAL; | ||
| 68 | |||
| 69 | if (clk->usecount++ == 0) { | ||
| 70 | __clk_enable(clk->parent); | ||
| 71 | __clk_enable(clk->secondary); | ||
| 72 | |||
| 73 | if (clk->enable) | ||
| 74 | clk->enable(clk); | ||
| 75 | } | ||
| 76 | return 0; | ||
| 77 | } | ||
| 78 | |||
| 79 | /* This function increments the reference count on the clock and enables the | ||
| 80 | * clock if not already enabled. The parent clock tree is recursively enabled | ||
| 81 | */ | ||
| 82 | int clk_enable(struct clk *clk) | ||
| 83 | { | ||
| 84 | int ret = 0; | ||
| 85 | |||
| 86 | if (clk == NULL || IS_ERR(clk)) | ||
| 87 | return -EINVAL; | ||
| 88 | |||
| 89 | mutex_lock(&clocks_mutex); | ||
| 90 | ret = __clk_enable(clk); | ||
| 91 | mutex_unlock(&clocks_mutex); | ||
| 92 | |||
| 93 | return ret; | ||
| 94 | } | ||
| 95 | EXPORT_SYMBOL(clk_enable); | ||
| 96 | |||
| 97 | /* This function decrements the reference count on the clock and disables | ||
| 98 | * the clock when reference count is 0. The parent clock tree is | ||
| 99 | * recursively disabled | ||
| 100 | */ | ||
| 101 | void clk_disable(struct clk *clk) | ||
| 102 | { | ||
| 103 | if (clk == NULL || IS_ERR(clk)) | ||
| 104 | return; | ||
| 105 | |||
| 106 | mutex_lock(&clocks_mutex); | ||
| 107 | __clk_disable(clk); | ||
| 108 | mutex_unlock(&clocks_mutex); | ||
| 109 | } | ||
| 110 | EXPORT_SYMBOL(clk_disable); | ||
| 111 | |||
| 112 | /* Retrieve the *current* clock rate. If the clock itself | ||
| 113 | * does not provide a special calculation routine, ask | ||
| 114 | * its parent and so on, until one is able to return | ||
| 115 | * a valid clock rate | ||
| 116 | */ | ||
| 117 | unsigned long clk_get_rate(struct clk *clk) | ||
| 118 | { | ||
| 119 | if (clk == NULL || IS_ERR(clk)) | ||
| 120 | return 0UL; | ||
| 121 | |||
| 122 | if (clk->get_rate) | ||
| 123 | return clk->get_rate(clk); | ||
| 124 | |||
| 125 | return clk_get_rate(clk->parent); | ||
| 126 | } | ||
| 127 | EXPORT_SYMBOL(clk_get_rate); | ||
| 128 | |||
| 129 | /* Round the requested clock rate to the nearest supported | ||
| 130 | * rate that is less than or equal to the requested rate. | ||
| 131 | * This is dependent on the clock's current parent. | ||
| 132 | */ | ||
| 133 | long clk_round_rate(struct clk *clk, unsigned long rate) | ||
| 134 | { | ||
| 135 | if (clk == NULL || IS_ERR(clk) || !clk->round_rate) | ||
| 136 | return 0; | ||
| 137 | |||
| 138 | return clk->round_rate(clk, rate); | ||
| 139 | } | ||
| 140 | EXPORT_SYMBOL(clk_round_rate); | ||
| 141 | |||
| 142 | /* Set the clock to the requested clock rate. The rate must | ||
| 143 | * match a supported rate exactly based on what clk_round_rate returns | ||
| 144 | */ | ||
| 145 | int clk_set_rate(struct clk *clk, unsigned long rate) | ||
| 146 | { | ||
| 147 | int ret = -EINVAL; | ||
| 148 | |||
| 149 | if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0) | ||
| 150 | return ret; | ||
| 151 | |||
| 152 | mutex_lock(&clocks_mutex); | ||
| 153 | ret = clk->set_rate(clk, rate); | ||
| 154 | mutex_unlock(&clocks_mutex); | ||
| 155 | |||
| 156 | return ret; | ||
| 157 | } | ||
| 158 | EXPORT_SYMBOL(clk_set_rate); | ||
| 159 | |||
| 160 | /* Set the clock's parent to another clock source */ | ||
| 161 | int clk_set_parent(struct clk *clk, struct clk *parent) | ||
| 162 | { | ||
| 163 | int ret = -EINVAL; | ||
| 164 | struct clk *old; | ||
| 165 | |||
| 166 | if (clk == NULL || IS_ERR(clk) || parent == NULL || | ||
| 167 | IS_ERR(parent) || clk->set_parent == NULL) | ||
| 168 | return ret; | ||
| 169 | |||
| 170 | if (clk->usecount) | ||
| 171 | clk_enable(parent); | ||
| 172 | |||
| 173 | mutex_lock(&clocks_mutex); | ||
| 174 | ret = clk->set_parent(clk, parent); | ||
| 175 | if (ret == 0) { | ||
| 176 | old = clk->parent; | ||
| 177 | clk->parent = parent; | ||
| 178 | } else { | ||
| 179 | old = parent; | ||
| 180 | } | ||
| 181 | mutex_unlock(&clocks_mutex); | ||
| 182 | |||
| 183 | if (clk->usecount) | ||
| 184 | clk_disable(old); | ||
| 185 | |||
| 186 | return ret; | ||
| 187 | } | ||
| 188 | EXPORT_SYMBOL(clk_set_parent); | ||
| 189 | |||
| 190 | /* Retrieve the clock's parent clock source */ | ||
| 191 | struct clk *clk_get_parent(struct clk *clk) | ||
| 192 | { | ||
| 193 | struct clk *ret = NULL; | ||
| 194 | |||
| 195 | if (clk == NULL || IS_ERR(clk)) | ||
| 196 | return ret; | ||
| 197 | |||
| 198 | return clk->parent; | ||
| 199 | } | ||
| 200 | EXPORT_SYMBOL(clk_get_parent); | ||
diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h new file mode 100644 index 000000000000..d0f49fc0abb5 --- /dev/null +++ b/arch/arm/mach-mxs/devices-mx23.h | |||
| @@ -0,0 +1,16 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it under | ||
| 8 | * the terms of the GNU General Public License version 2 as published by the | ||
| 9 | * Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #include <mach/mx23.h> | ||
| 12 | #include <mach/devices-common.h> | ||
| 13 | |||
| 14 | extern const struct mxs_duart_data mx23_duart_data __initconst; | ||
| 15 | #define mx23_add_duart() \ | ||
| 16 | mxs_add_duart(&mx23_duart_data) | ||
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h new file mode 100644 index 000000000000..00b736c434ba --- /dev/null +++ b/arch/arm/mach-mxs/devices-mx28.h | |||
| @@ -0,0 +1,20 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it under | ||
| 8 | * the terms of the GNU General Public License version 2 as published by the | ||
| 9 | * Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #include <mach/mx28.h> | ||
| 12 | #include <mach/devices-common.h> | ||
| 13 | |||
| 14 | extern const struct mxs_duart_data mx28_duart_data __initconst; | ||
| 15 | #define mx28_add_duart() \ | ||
| 16 | mxs_add_duart(&mx28_duart_data) | ||
| 17 | |||
| 18 | extern const struct mxs_fec_data mx28_fec_data[] __initconst; | ||
| 19 | #define mx28_add_fec(id, pdata) \ | ||
| 20 | mxs_add_fec(&mx28_fec_data[id], pdata) | ||
diff --git a/arch/arm/mach-mxs/devices.c b/arch/arm/mach-mxs/devices.c new file mode 100644 index 000000000000..6b60f02ca2e3 --- /dev/null +++ b/arch/arm/mach-mxs/devices.c | |||
| @@ -0,0 +1,75 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2008 Sascha Hauer, kernel@pengutronix.de | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation; either version 2 | ||
| 7 | * of the License, or (at your option) any later version. | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License | ||
| 14 | * along with this program; if not, write to the Free Software | ||
| 15 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, | ||
| 16 | * Boston, MA 02110-1301, USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/kernel.h> | ||
| 20 | #include <linux/slab.h> | ||
| 21 | #include <linux/init.h> | ||
| 22 | #include <linux/err.h> | ||
| 23 | #include <linux/platform_device.h> | ||
| 24 | #include <mach/common.h> | ||
| 25 | |||
| 26 | struct platform_device *__init mxs_add_platform_device_dmamask( | ||
| 27 | const char *name, int id, | ||
| 28 | const struct resource *res, unsigned int num_resources, | ||
| 29 | const void *data, size_t size_data, u64 dmamask) | ||
| 30 | { | ||
| 31 | int ret = -ENOMEM; | ||
| 32 | struct platform_device *pdev; | ||
| 33 | |||
| 34 | pdev = platform_device_alloc(name, id); | ||
| 35 | if (!pdev) | ||
| 36 | goto err; | ||
| 37 | |||
| 38 | if (dmamask) { | ||
| 39 | /* | ||
| 40 | * This memory isn't freed when the device is put, | ||
| 41 | * I don't have a nice idea for that though. Conceptually | ||
| 42 | * dma_mask in struct device should not be a pointer. | ||
| 43 | * See http://thread.gmane.org/gmane.linux.kernel.pci/9081 | ||
| 44 | */ | ||
| 45 | pdev->dev.dma_mask = | ||
| 46 | kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL); | ||
| 47 | if (!pdev->dev.dma_mask) | ||
| 48 | /* ret is still -ENOMEM; */ | ||
| 49 | goto err; | ||
| 50 | |||
| 51 | *pdev->dev.dma_mask = dmamask; | ||
| 52 | pdev->dev.coherent_dma_mask = dmamask; | ||
| 53 | } | ||
| 54 | |||
| 55 | if (res) { | ||
| 56 | ret = platform_device_add_resources(pdev, res, num_resources); | ||
| 57 | if (ret) | ||
| 58 | goto err; | ||
| 59 | } | ||
| 60 | |||
| 61 | if (data) { | ||
| 62 | ret = platform_device_add_data(pdev, data, size_data); | ||
| 63 | if (ret) | ||
| 64 | goto err; | ||
| 65 | } | ||
| 66 | |||
| 67 | ret = platform_device_add(pdev); | ||
| 68 | if (ret) { | ||
| 69 | err: | ||
| 70 | platform_device_put(pdev); | ||
| 71 | return ERR_PTR(ret); | ||
| 72 | } | ||
| 73 | |||
| 74 | return pdev; | ||
| 75 | } | ||
diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig new file mode 100644 index 000000000000..a35a2dc55395 --- /dev/null +++ b/arch/arm/mach-mxs/devices/Kconfig | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | config MXS_HAVE_PLATFORM_DUART | ||
| 2 | bool | ||
| 3 | |||
| 4 | config MXS_HAVE_PLATFORM_FEC | ||
| 5 | bool | ||
diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile new file mode 100644 index 000000000000..4b5266a3e6d9 --- /dev/null +++ b/arch/arm/mach-mxs/devices/Makefile | |||
| @@ -0,0 +1,2 @@ | |||
| 1 | obj-$(CONFIG_MXS_HAVE_PLATFORM_DUART) += platform-duart.o | ||
| 2 | obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o | ||
diff --git a/arch/arm/mach-mxs/devices/platform-duart.c b/arch/arm/mach-mxs/devices/platform-duart.c new file mode 100644 index 000000000000..2fe0df5b0aad --- /dev/null +++ b/arch/arm/mach-mxs/devices/platform-duart.c | |||
| @@ -0,0 +1,48 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009-2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it under | ||
| 8 | * the terms of the GNU General Public License version 2 as published by the | ||
| 9 | * Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #include <mach/mx23.h> | ||
| 12 | #include <mach/mx28.h> | ||
| 13 | #include <mach/devices-common.h> | ||
| 14 | |||
| 15 | #define mxs_duart_data_entry(soc) \ | ||
| 16 | { \ | ||
| 17 | .iobase = soc ## _DUART_BASE_ADDR, \ | ||
| 18 | .irq = soc ## _INT_DUART, \ | ||
| 19 | } | ||
| 20 | |||
| 21 | #ifdef CONFIG_SOC_IMX23 | ||
| 22 | const struct mxs_duart_data mx23_duart_data __initconst = | ||
| 23 | mxs_duart_data_entry(MX23); | ||
| 24 | #endif | ||
| 25 | |||
| 26 | #ifdef CONFIG_SOC_IMX28 | ||
| 27 | const struct mxs_duart_data mx28_duart_data __initconst = | ||
| 28 | mxs_duart_data_entry(MX28); | ||
| 29 | #endif | ||
| 30 | |||
| 31 | struct platform_device *__init mxs_add_duart( | ||
| 32 | const struct mxs_duart_data *data) | ||
| 33 | { | ||
| 34 | struct resource res[] = { | ||
| 35 | { | ||
| 36 | .start = data->iobase, | ||
| 37 | .end = data->iobase + SZ_8K - 1, | ||
| 38 | .flags = IORESOURCE_MEM, | ||
| 39 | }, { | ||
| 40 | .start = data->irq, | ||
| 41 | .end = data->irq, | ||
| 42 | .flags = IORESOURCE_IRQ, | ||
| 43 | }, | ||
| 44 | }; | ||
| 45 | |||
| 46 | return mxs_add_platform_device("mxs-duart", 0, res, ARRAY_SIZE(res), | ||
| 47 | NULL, 0); | ||
| 48 | } | ||
diff --git a/arch/arm/mach-mxs/devices/platform-fec.c b/arch/arm/mach-mxs/devices/platform-fec.c new file mode 100644 index 000000000000..c08168cf3dec --- /dev/null +++ b/arch/arm/mach-mxs/devices/platform-fec.c | |||
| @@ -0,0 +1,50 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <asm/sizes.h> | ||
| 10 | #include <mach/mx28.h> | ||
| 11 | #include <mach/devices-common.h> | ||
| 12 | |||
| 13 | #define mxs_fec_data_entry_single(soc, _id) \ | ||
| 14 | { \ | ||
| 15 | .id = _id, \ | ||
| 16 | .iobase = soc ## _ENET_MAC ## _id ## _BASE_ADDR, \ | ||
| 17 | .irq = soc ## _INT_ENET_MAC ## _id, \ | ||
| 18 | } | ||
| 19 | |||
| 20 | #define mxs_fec_data_entry(soc, _id) \ | ||
| 21 | [_id] = mxs_fec_data_entry_single(soc, _id) | ||
| 22 | |||
| 23 | #ifdef CONFIG_SOC_IMX28 | ||
| 24 | const struct mxs_fec_data mx28_fec_data[] __initconst = { | ||
| 25 | #define mx28_fec_data_entry(_id) \ | ||
| 26 | mxs_fec_data_entry(MX28, _id) | ||
| 27 | mx28_fec_data_entry(0), | ||
| 28 | mx28_fec_data_entry(1), | ||
| 29 | }; | ||
| 30 | #endif | ||
| 31 | |||
| 32 | struct platform_device *__init mxs_add_fec( | ||
| 33 | const struct mxs_fec_data *data, | ||
| 34 | const struct fec_platform_data *pdata) | ||
| 35 | { | ||
| 36 | struct resource res[] = { | ||
| 37 | { | ||
| 38 | .start = data->iobase, | ||
| 39 | .end = data->iobase + SZ_16K - 1, | ||
| 40 | .flags = IORESOURCE_MEM, | ||
| 41 | }, { | ||
| 42 | .start = data->irq, | ||
| 43 | .end = data->irq, | ||
| 44 | .flags = IORESOURCE_IRQ, | ||
| 45 | }, | ||
| 46 | }; | ||
| 47 | |||
| 48 | return mxs_add_platform_device("fec", data->id, | ||
| 49 | res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); | ||
| 50 | } | ||
diff --git a/arch/arm/mach-mxs/gpio.c b/arch/arm/mach-mxs/gpio.c new file mode 100644 index 000000000000..d7ad7a61366d --- /dev/null +++ b/arch/arm/mach-mxs/gpio.c | |||
| @@ -0,0 +1,325 @@ | |||
| 1 | /* | ||
| 2 | * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> | ||
| 3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | ||
| 4 | * | ||
| 5 | * Based on code from Freescale, | ||
| 6 | * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or | ||
| 9 | * modify it under the terms of the GNU General Public License | ||
| 10 | * as published by the Free Software Foundation; either version 2 | ||
| 11 | * of the License, or (at your option) any later version. | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 20 | * MA 02110-1301, USA. | ||
| 21 | */ | ||
| 22 | |||
| 23 | #include <linux/init.h> | ||
| 24 | #include <linux/interrupt.h> | ||
| 25 | #include <linux/io.h> | ||
| 26 | #include <linux/irq.h> | ||
| 27 | #include <linux/gpio.h> | ||
| 28 | #include <mach/mx23.h> | ||
| 29 | #include <mach/mx28.h> | ||
| 30 | #include <asm-generic/bug.h> | ||
| 31 | |||
| 32 | #include "gpio.h" | ||
| 33 | |||
| 34 | static struct mxs_gpio_port *mxs_gpio_ports; | ||
| 35 | static int gpio_table_size; | ||
| 36 | |||
| 37 | #define PINCTRL_DOUT(n) ((cpu_is_mx23() ? 0x0500 : 0x0700) + (n) * 0x10) | ||
| 38 | #define PINCTRL_DIN(n) ((cpu_is_mx23() ? 0x0600 : 0x0900) + (n) * 0x10) | ||
| 39 | #define PINCTRL_DOE(n) ((cpu_is_mx23() ? 0x0700 : 0x0b00) + (n) * 0x10) | ||
| 40 | #define PINCTRL_PIN2IRQ(n) ((cpu_is_mx23() ? 0x0800 : 0x1000) + (n) * 0x10) | ||
| 41 | #define PINCTRL_IRQEN(n) ((cpu_is_mx23() ? 0x0900 : 0x1100) + (n) * 0x10) | ||
| 42 | #define PINCTRL_IRQLEV(n) ((cpu_is_mx23() ? 0x0a00 : 0x1200) + (n) * 0x10) | ||
| 43 | #define PINCTRL_IRQPOL(n) ((cpu_is_mx23() ? 0x0b00 : 0x1300) + (n) * 0x10) | ||
| 44 | #define PINCTRL_IRQSTAT(n) ((cpu_is_mx23() ? 0x0c00 : 0x1400) + (n) * 0x10) | ||
| 45 | |||
| 46 | #define GPIO_INT_FALL_EDGE 0x0 | ||
| 47 | #define GPIO_INT_LOW_LEV 0x1 | ||
| 48 | #define GPIO_INT_RISE_EDGE 0x2 | ||
| 49 | #define GPIO_INT_HIGH_LEV 0x3 | ||
| 50 | #define GPIO_INT_LEV_MASK (1 << 0) | ||
| 51 | #define GPIO_INT_POL_MASK (1 << 1) | ||
| 52 | |||
| 53 | /* Note: This driver assumes 32 GPIOs are handled in one register */ | ||
| 54 | |||
| 55 | static void clear_gpio_irqstatus(struct mxs_gpio_port *port, u32 index) | ||
| 56 | { | ||
| 57 | __mxs_clrl(1 << index, port->base + PINCTRL_IRQSTAT(port->id)); | ||
| 58 | } | ||
| 59 | |||
| 60 | static void set_gpio_irqenable(struct mxs_gpio_port *port, u32 index, | ||
| 61 | int enable) | ||
| 62 | { | ||
| 63 | if (enable) { | ||
| 64 | __mxs_setl(1 << index, port->base + PINCTRL_IRQEN(port->id)); | ||
| 65 | __mxs_setl(1 << index, port->base + PINCTRL_PIN2IRQ(port->id)); | ||
| 66 | } else { | ||
| 67 | __mxs_clrl(1 << index, port->base + PINCTRL_IRQEN(port->id)); | ||
| 68 | } | ||
| 69 | } | ||
| 70 | |||
| 71 | static void mxs_gpio_ack_irq(u32 irq) | ||
| 72 | { | ||
| 73 | u32 gpio = irq_to_gpio(irq); | ||
| 74 | clear_gpio_irqstatus(&mxs_gpio_ports[gpio / 32], gpio & 0x1f); | ||
| 75 | } | ||
| 76 | |||
| 77 | static void mxs_gpio_mask_irq(u32 irq) | ||
| 78 | { | ||
| 79 | u32 gpio = irq_to_gpio(irq); | ||
| 80 | set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 0); | ||
| 81 | } | ||
| 82 | |||
| 83 | static void mxs_gpio_unmask_irq(u32 irq) | ||
| 84 | { | ||
| 85 | u32 gpio = irq_to_gpio(irq); | ||
| 86 | set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 1); | ||
| 87 | } | ||
| 88 | |||
| 89 | static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset); | ||
| 90 | |||
| 91 | static int mxs_gpio_set_irq_type(u32 irq, u32 type) | ||
| 92 | { | ||
| 93 | u32 gpio = irq_to_gpio(irq); | ||
| 94 | u32 pin_mask = 1 << (gpio & 31); | ||
| 95 | struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32]; | ||
| 96 | void __iomem *pin_addr; | ||
| 97 | int edge; | ||
| 98 | |||
| 99 | switch (type) { | ||
| 100 | case IRQ_TYPE_EDGE_RISING: | ||
| 101 | edge = GPIO_INT_RISE_EDGE; | ||
| 102 | break; | ||
| 103 | case IRQ_TYPE_EDGE_FALLING: | ||
| 104 | edge = GPIO_INT_FALL_EDGE; | ||
| 105 | break; | ||
| 106 | case IRQ_TYPE_LEVEL_LOW: | ||
| 107 | edge = GPIO_INT_LOW_LEV; | ||
| 108 | break; | ||
| 109 | case IRQ_TYPE_LEVEL_HIGH: | ||
| 110 | edge = GPIO_INT_HIGH_LEV; | ||
| 111 | break; | ||
| 112 | default: | ||
| 113 | return -EINVAL; | ||
| 114 | } | ||
| 115 | |||
| 116 | /* set level or edge */ | ||
| 117 | pin_addr = port->base + PINCTRL_IRQLEV(port->id); | ||
| 118 | if (edge & GPIO_INT_LEV_MASK) | ||
| 119 | __mxs_setl(pin_mask, pin_addr); | ||
| 120 | else | ||
| 121 | __mxs_clrl(pin_mask, pin_addr); | ||
| 122 | |||
| 123 | /* set polarity */ | ||
| 124 | pin_addr = port->base + PINCTRL_IRQPOL(port->id); | ||
| 125 | if (edge & GPIO_INT_POL_MASK) | ||
| 126 | __mxs_setl(pin_mask, pin_addr); | ||
| 127 | else | ||
| 128 | __mxs_clrl(pin_mask, pin_addr); | ||
| 129 | |||
| 130 | clear_gpio_irqstatus(port, gpio & 0x1f); | ||
| 131 | |||
| 132 | return 0; | ||
| 133 | } | ||
| 134 | |||
| 135 | /* MXS has one interrupt *per* gpio port */ | ||
| 136 | static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc) | ||
| 137 | { | ||
| 138 | u32 irq_stat; | ||
| 139 | struct mxs_gpio_port *port = (struct mxs_gpio_port *)get_irq_data(irq); | ||
| 140 | u32 gpio_irq_no_base = port->virtual_irq_start; | ||
| 141 | |||
| 142 | irq_stat = __raw_readl(port->base + PINCTRL_IRQSTAT(port->id)) & | ||
| 143 | __raw_readl(port->base + PINCTRL_IRQEN(port->id)); | ||
| 144 | |||
| 145 | while (irq_stat != 0) { | ||
| 146 | int irqoffset = fls(irq_stat) - 1; | ||
| 147 | generic_handle_irq(gpio_irq_no_base + irqoffset); | ||
| 148 | irq_stat &= ~(1 << irqoffset); | ||
| 149 | } | ||
| 150 | } | ||
| 151 | |||
| 152 | /* | ||
| 153 | * Set interrupt number "irq" in the GPIO as a wake-up source. | ||
| 154 | * While system is running, all registered GPIO interrupts need to have | ||
| 155 | * wake-up enabled. When system is suspended, only selected GPIO interrupts | ||
| 156 | * need to have wake-up enabled. | ||
| 157 | * @param irq interrupt source number | ||
| 158 | * @param enable enable as wake-up if equal to non-zero | ||
| 159 | * @return This function returns 0 on success. | ||
| 160 | */ | ||
| 161 | static int mxs_gpio_set_wake_irq(u32 irq, u32 enable) | ||
| 162 | { | ||
| 163 | u32 gpio = irq_to_gpio(irq); | ||
| 164 | u32 gpio_idx = gpio & 0x1f; | ||
| 165 | struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32]; | ||
| 166 | |||
| 167 | if (enable) { | ||
| 168 | if (port->irq_high && (gpio_idx >= 16)) | ||
| 169 | enable_irq_wake(port->irq_high); | ||
| 170 | else | ||
| 171 | enable_irq_wake(port->irq); | ||
| 172 | } else { | ||
| 173 | if (port->irq_high && (gpio_idx >= 16)) | ||
| 174 | disable_irq_wake(port->irq_high); | ||
| 175 | else | ||
| 176 | disable_irq_wake(port->irq); | ||
| 177 | } | ||
| 178 | |||
| 179 | return 0; | ||
| 180 | } | ||
| 181 | |||
| 182 | static struct irq_chip gpio_irq_chip = { | ||
| 183 | .ack = mxs_gpio_ack_irq, | ||
| 184 | .mask = mxs_gpio_mask_irq, | ||
| 185 | .unmask = mxs_gpio_unmask_irq, | ||
| 186 | .set_type = mxs_gpio_set_irq_type, | ||
| 187 | .set_wake = mxs_gpio_set_wake_irq, | ||
| 188 | }; | ||
| 189 | |||
| 190 | static void mxs_set_gpio_direction(struct gpio_chip *chip, unsigned offset, | ||
| 191 | int dir) | ||
| 192 | { | ||
| 193 | struct mxs_gpio_port *port = | ||
| 194 | container_of(chip, struct mxs_gpio_port, chip); | ||
| 195 | void __iomem *pin_addr = port->base + PINCTRL_DOE(port->id); | ||
| 196 | |||
| 197 | if (dir) | ||
| 198 | __mxs_setl(1 << offset, pin_addr); | ||
| 199 | else | ||
| 200 | __mxs_clrl(1 << offset, pin_addr); | ||
| 201 | } | ||
| 202 | |||
| 203 | static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset) | ||
| 204 | { | ||
| 205 | struct mxs_gpio_port *port = | ||
| 206 | container_of(chip, struct mxs_gpio_port, chip); | ||
| 207 | |||
| 208 | return (__raw_readl(port->base + PINCTRL_DIN(port->id)) >> offset) & 1; | ||
| 209 | } | ||
| 210 | |||
| 211 | static void mxs_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | ||
| 212 | { | ||
| 213 | struct mxs_gpio_port *port = | ||
| 214 | container_of(chip, struct mxs_gpio_port, chip); | ||
| 215 | void __iomem *pin_addr = port->base + PINCTRL_DOUT(port->id); | ||
| 216 | |||
| 217 | if (value) | ||
| 218 | __mxs_setl(1 << offset, pin_addr); | ||
| 219 | else | ||
| 220 | __mxs_clrl(1 << offset, pin_addr); | ||
| 221 | } | ||
| 222 | |||
| 223 | static int mxs_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | ||
| 224 | { | ||
| 225 | struct mxs_gpio_port *port = | ||
| 226 | container_of(chip, struct mxs_gpio_port, chip); | ||
| 227 | |||
| 228 | return port->virtual_irq_start + offset; | ||
| 229 | } | ||
| 230 | |||
| 231 | static int mxs_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | ||
| 232 | { | ||
| 233 | mxs_set_gpio_direction(chip, offset, 0); | ||
| 234 | return 0; | ||
| 235 | } | ||
| 236 | |||
| 237 | static int mxs_gpio_direction_output(struct gpio_chip *chip, | ||
| 238 | unsigned offset, int value) | ||
| 239 | { | ||
| 240 | mxs_gpio_set(chip, offset, value); | ||
| 241 | mxs_set_gpio_direction(chip, offset, 1); | ||
| 242 | return 0; | ||
| 243 | } | ||
| 244 | |||
| 245 | int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt) | ||
| 246 | { | ||
| 247 | int i, j; | ||
| 248 | |||
| 249 | /* save for local usage */ | ||
| 250 | mxs_gpio_ports = port; | ||
| 251 | gpio_table_size = cnt; | ||
| 252 | |||
| 253 | pr_info("MXS GPIO hardware\n"); | ||
| 254 | |||
| 255 | for (i = 0; i < cnt; i++) { | ||
| 256 | /* disable the interrupt and clear the status */ | ||
| 257 | __raw_writel(0, port[i].base + PINCTRL_PIN2IRQ(i)); | ||
| 258 | __raw_writel(0, port[i].base + PINCTRL_IRQEN(i)); | ||
| 259 | |||
| 260 | /* clear address has to be used to clear IRQSTAT bits */ | ||
| 261 | __mxs_clrl(~0U, port[i].base + PINCTRL_IRQSTAT(i)); | ||
| 262 | |||
| 263 | for (j = port[i].virtual_irq_start; | ||
| 264 | j < port[i].virtual_irq_start + 32; j++) { | ||
| 265 | set_irq_chip(j, &gpio_irq_chip); | ||
| 266 | set_irq_handler(j, handle_level_irq); | ||
| 267 | set_irq_flags(j, IRQF_VALID); | ||
| 268 | } | ||
| 269 | |||
| 270 | /* setup one handler for each entry */ | ||
| 271 | set_irq_chained_handler(port[i].irq, mxs_gpio_irq_handler); | ||
| 272 | set_irq_data(port[i].irq, &port[i]); | ||
| 273 | |||
| 274 | /* register gpio chip */ | ||
| 275 | port[i].chip.direction_input = mxs_gpio_direction_input; | ||
| 276 | port[i].chip.direction_output = mxs_gpio_direction_output; | ||
| 277 | port[i].chip.get = mxs_gpio_get; | ||
| 278 | port[i].chip.set = mxs_gpio_set; | ||
| 279 | port[i].chip.to_irq = mxs_gpio_to_irq; | ||
| 280 | port[i].chip.base = i * 32; | ||
| 281 | port[i].chip.ngpio = 32; | ||
| 282 | |||
| 283 | /* its a serious configuration bug when it fails */ | ||
| 284 | BUG_ON(gpiochip_add(&port[i].chip) < 0); | ||
| 285 | } | ||
| 286 | |||
| 287 | return 0; | ||
| 288 | } | ||
| 289 | |||
| 290 | #define DEFINE_MXS_GPIO_PORT(soc, _id) \ | ||
| 291 | { \ | ||
| 292 | .chip.label = "gpio-" #_id, \ | ||
| 293 | .id = _id, \ | ||
| 294 | .irq = soc ## _INT_GPIO ## _id, \ | ||
| 295 | .base = soc ## _IO_ADDRESS( \ | ||
| 296 | soc ## _PINCTRL ## _BASE_ADDR), \ | ||
| 297 | .virtual_irq_start = MXS_GPIO_IRQ_START + (_id) * 32, \ | ||
| 298 | } | ||
| 299 | |||
| 300 | #define DEFINE_REGISTER_FUNCTION(prefix) \ | ||
| 301 | int __init prefix ## _register_gpios(void) \ | ||
| 302 | { \ | ||
| 303 | return mxs_gpio_init(prefix ## _gpio_ports, \ | ||
| 304 | ARRAY_SIZE(prefix ## _gpio_ports)); \ | ||
| 305 | } | ||
| 306 | |||
| 307 | #ifdef CONFIG_SOC_IMX23 | ||
| 308 | static struct mxs_gpio_port mx23_gpio_ports[] = { | ||
| 309 | DEFINE_MXS_GPIO_PORT(MX23, 0), | ||
| 310 | DEFINE_MXS_GPIO_PORT(MX23, 1), | ||
| 311 | DEFINE_MXS_GPIO_PORT(MX23, 2), | ||
| 312 | }; | ||
| 313 | DEFINE_REGISTER_FUNCTION(mx23) | ||
| 314 | #endif | ||
| 315 | |||
| 316 | #ifdef CONFIG_SOC_IMX28 | ||
| 317 | static struct mxs_gpio_port mx28_gpio_ports[] = { | ||
| 318 | DEFINE_MXS_GPIO_PORT(MX28, 0), | ||
| 319 | DEFINE_MXS_GPIO_PORT(MX28, 1), | ||
| 320 | DEFINE_MXS_GPIO_PORT(MX28, 2), | ||
| 321 | DEFINE_MXS_GPIO_PORT(MX28, 3), | ||
| 322 | DEFINE_MXS_GPIO_PORT(MX28, 4), | ||
| 323 | }; | ||
| 324 | DEFINE_REGISTER_FUNCTION(mx28) | ||
| 325 | #endif | ||
diff --git a/arch/arm/mach-mxs/gpio.h b/arch/arm/mach-mxs/gpio.h new file mode 100644 index 000000000000..005bb06630b1 --- /dev/null +++ b/arch/arm/mach-mxs/gpio.h | |||
| @@ -0,0 +1,34 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License | ||
| 7 | * as published by the Free Software Foundation; either version 2 | ||
| 8 | * of the License, or (at your option) any later version. | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 17 | * MA 02110-1301, USA. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef __MXS_GPIO_H__ | ||
| 21 | #define __MXS_GPIO_H__ | ||
| 22 | |||
| 23 | struct mxs_gpio_port { | ||
| 24 | void __iomem *base; | ||
| 25 | int id; | ||
| 26 | int irq; | ||
| 27 | int irq_high; | ||
| 28 | int virtual_irq_start; | ||
| 29 | struct gpio_chip chip; | ||
| 30 | }; | ||
| 31 | |||
| 32 | int mxs_gpio_init(struct mxs_gpio_port*, int); | ||
| 33 | |||
| 34 | #endif /* __MXS_GPIO_H__ */ | ||
diff --git a/arch/arm/mach-mxs/icoll.c b/arch/arm/mach-mxs/icoll.c new file mode 100644 index 000000000000..5dd43ba70058 --- /dev/null +++ b/arch/arm/mach-mxs/icoll.c | |||
| @@ -0,0 +1,81 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License along | ||
| 15 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/kernel.h> | ||
| 20 | #include <linux/init.h> | ||
| 21 | #include <linux/irq.h> | ||
| 22 | #include <linux/io.h> | ||
| 23 | |||
| 24 | #include <mach/mxs.h> | ||
| 25 | #include <mach/common.h> | ||
| 26 | |||
| 27 | #define HW_ICOLL_VECTOR 0x0000 | ||
| 28 | #define HW_ICOLL_LEVELACK 0x0010 | ||
| 29 | #define HW_ICOLL_CTRL 0x0020 | ||
| 30 | #define HW_ICOLL_INTERRUPTn_SET(n) (0x0124 + (n) * 0x10) | ||
| 31 | #define HW_ICOLL_INTERRUPTn_CLR(n) (0x0128 + (n) * 0x10) | ||
| 32 | #define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004 | ||
| 33 | #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1 | ||
| 34 | |||
| 35 | static void __iomem *icoll_base = MXS_IO_ADDRESS(MXS_ICOLL_BASE_ADDR); | ||
| 36 | |||
| 37 | static void icoll_ack_irq(unsigned int irq) | ||
| 38 | { | ||
| 39 | /* | ||
| 40 | * The Interrupt Collector is able to prioritize irqs. | ||
| 41 | * Currently only level 0 is used. So acking can use | ||
| 42 | * BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 unconditionally. | ||
| 43 | */ | ||
| 44 | __raw_writel(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0, | ||
| 45 | icoll_base + HW_ICOLL_LEVELACK); | ||
| 46 | } | ||
| 47 | |||
| 48 | static void icoll_mask_irq(unsigned int irq) | ||
| 49 | { | ||
| 50 | __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE, | ||
| 51 | icoll_base + HW_ICOLL_INTERRUPTn_CLR(irq)); | ||
| 52 | } | ||
| 53 | |||
| 54 | static void icoll_unmask_irq(unsigned int irq) | ||
| 55 | { | ||
| 56 | __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE, | ||
| 57 | icoll_base + HW_ICOLL_INTERRUPTn_SET(irq)); | ||
| 58 | } | ||
| 59 | |||
| 60 | static struct irq_chip mxs_icoll_chip = { | ||
| 61 | .ack = icoll_ack_irq, | ||
| 62 | .mask = icoll_mask_irq, | ||
| 63 | .unmask = icoll_unmask_irq, | ||
| 64 | }; | ||
| 65 | |||
| 66 | void __init icoll_init_irq(void) | ||
| 67 | { | ||
| 68 | int i; | ||
| 69 | |||
| 70 | /* | ||
| 71 | * Interrupt Collector reset, which initializes the priority | ||
| 72 | * for each irq to level 0. | ||
| 73 | */ | ||
| 74 | mxs_reset_block(icoll_base + HW_ICOLL_CTRL); | ||
| 75 | |||
| 76 | for (i = 0; i < MXS_INTERNAL_IRQS; i++) { | ||
| 77 | set_irq_chip(i, &mxs_icoll_chip); | ||
| 78 | set_irq_handler(i, handle_level_irq); | ||
| 79 | set_irq_flags(i, IRQF_VALID); | ||
| 80 | } | ||
| 81 | } | ||
diff --git a/arch/arm/mach-mxs/include/mach/clkdev.h b/arch/arm/mach-mxs/include/mach/clkdev.h new file mode 100644 index 000000000000..3a8f2e3a6309 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/clkdev.h | |||
| @@ -0,0 +1,7 @@ | |||
| 1 | #ifndef __MACH_MXS_CLKDEV_H__ | ||
| 2 | #define __MACH_MXS_CLKDEV_H__ | ||
| 3 | |||
| 4 | #define __clk_get(clk) ({ 1; }) | ||
| 5 | #define __clk_put(clk) do { } while (0) | ||
| 6 | |||
| 7 | #endif | ||
diff --git a/arch/arm/mach-mxs/include/mach/clock.h b/arch/arm/mach-mxs/include/mach/clock.h new file mode 100644 index 000000000000..041e276d8a32 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/clock.h | |||
| @@ -0,0 +1,64 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License | ||
| 7 | * as published by the Free Software Foundation; either version 2 | ||
| 8 | * of the License, or (at your option) any later version. | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 17 | * MA 02110-1301, USA. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef __MACH_MXS_CLOCK_H__ | ||
| 21 | #define __MACH_MXS_CLOCK_H__ | ||
| 22 | |||
| 23 | #ifndef __ASSEMBLY__ | ||
| 24 | #include <linux/list.h> | ||
| 25 | |||
| 26 | struct module; | ||
| 27 | |||
| 28 | struct clk { | ||
| 29 | int id; | ||
| 30 | /* Source clock this clk depends on */ | ||
| 31 | struct clk *parent; | ||
| 32 | /* Secondary clock to enable/disable with this clock */ | ||
| 33 | struct clk *secondary; | ||
| 34 | /* Reference count of clock enable/disable */ | ||
| 35 | __s8 usecount; | ||
| 36 | /* Register bit position for clock's enable/disable control. */ | ||
| 37 | u8 enable_shift; | ||
| 38 | /* Register address for clock's enable/disable control. */ | ||
| 39 | void __iomem *enable_reg; | ||
| 40 | u32 flags; | ||
| 41 | /* get the current clock rate (always a fresh value) */ | ||
| 42 | unsigned long (*get_rate) (struct clk *); | ||
| 43 | /* Function ptr to set the clock to a new rate. The rate must match a | ||
| 44 | supported rate returned from round_rate. Leave blank if clock is not | ||
| 45 | programmable */ | ||
| 46 | int (*set_rate) (struct clk *, unsigned long); | ||
| 47 | /* Function ptr to round the requested clock rate to the nearest | ||
| 48 | supported rate that is less than or equal to the requested rate. */ | ||
| 49 | unsigned long (*round_rate) (struct clk *, unsigned long); | ||
| 50 | /* Function ptr to enable the clock. Leave blank if clock can not | ||
| 51 | be gated. */ | ||
| 52 | int (*enable) (struct clk *); | ||
| 53 | /* Function ptr to disable the clock. Leave blank if clock can not | ||
| 54 | be gated. */ | ||
| 55 | void (*disable) (struct clk *); | ||
| 56 | /* Function ptr to set the parent clock of the clock. */ | ||
| 57 | int (*set_parent) (struct clk *, struct clk *); | ||
| 58 | }; | ||
| 59 | |||
| 60 | int clk_register(struct clk *clk); | ||
| 61 | void clk_unregister(struct clk *clk); | ||
| 62 | |||
| 63 | #endif /* __ASSEMBLY__ */ | ||
| 64 | #endif /* __MACH_MXS_CLOCK_H__ */ | ||
diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h new file mode 100644 index 000000000000..59133eb3cc96 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/common.h | |||
| @@ -0,0 +1,31 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | */ | ||
| 4 | |||
| 5 | /* | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __MACH_MXS_COMMON_H__ | ||
| 12 | #define __MACH_MXS_COMMON_H__ | ||
| 13 | |||
| 14 | struct clk; | ||
| 15 | |||
| 16 | extern int mxs_reset_block(void __iomem *); | ||
| 17 | extern void mxs_timer_init(struct clk *, int); | ||
| 18 | |||
| 19 | extern int mx23_register_gpios(void); | ||
| 20 | extern int mx23_clocks_init(void); | ||
| 21 | extern void mx23_map_io(void); | ||
| 22 | extern void mx23_init_irq(void); | ||
| 23 | |||
| 24 | extern int mx28_register_gpios(void); | ||
| 25 | extern int mx28_clocks_init(void); | ||
| 26 | extern void mx28_map_io(void); | ||
| 27 | extern void mx28_init_irq(void); | ||
| 28 | |||
| 29 | extern void icoll_init_irq(void); | ||
| 30 | |||
| 31 | #endif /* __MACH_MXS_COMMON_H__ */ | ||
diff --git a/arch/arm/mach-mxs/include/mach/debug-macro.S b/arch/arm/mach-mxs/include/mach/debug-macro.S new file mode 100644 index 000000000000..79650a1ad78d --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/debug-macro.S | |||
| @@ -0,0 +1,38 @@ | |||
| 1 | /* arch/arm/mach-mxs/include/mach/debug-macro.S | ||
| 2 | * | ||
| 3 | * Debugging macro include header | ||
| 4 | * | ||
| 5 | * Copyright (C) 1994-1999 Russell King | ||
| 6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <mach/mx23.h> | ||
| 15 | #include <mach/mx28.h> | ||
| 16 | |||
| 17 | #ifdef CONFIG_SOC_IMX23 | ||
| 18 | #ifdef UART_PADDR | ||
| 19 | #error "CONFIG_DEBUG_LL is incompatible with multiple archs" | ||
| 20 | #endif | ||
| 21 | #define UART_PADDR MX23_DUART_BASE_ADDR | ||
| 22 | #endif | ||
| 23 | |||
| 24 | #ifdef CONFIG_SOC_IMX28 | ||
| 25 | #ifdef UART_PADDR | ||
| 26 | #error "CONFIG_DEBUG_LL is incompatible with multiple archs" | ||
| 27 | #endif | ||
| 28 | #define UART_PADDR MX28_DUART_BASE_ADDR | ||
| 29 | #endif | ||
| 30 | |||
| 31 | #define UART_VADDR MXS_IO_ADDRESS(UART_PADDR) | ||
| 32 | |||
| 33 | .macro addruart, rp, rv | ||
| 34 | ldr \rp, =UART_PADDR @ physical | ||
| 35 | ldr \rv, =UART_VADDR @ virtual | ||
| 36 | .endm | ||
| 37 | |||
| 38 | #include <asm/hardware/debug-pl01x.S> | ||
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h new file mode 100644 index 000000000000..3da48d4d3273 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/devices-common.h | |||
| @@ -0,0 +1,46 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009-2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <linux/kernel.h> | ||
| 10 | #include <linux/platform_device.h> | ||
| 11 | #include <linux/init.h> | ||
| 12 | |||
| 13 | struct platform_device *mxs_add_platform_device_dmamask( | ||
| 14 | const char *name, int id, | ||
| 15 | const struct resource *res, unsigned int num_resources, | ||
| 16 | const void *data, size_t size_data, u64 dmamask); | ||
| 17 | |||
| 18 | static inline struct platform_device *mxs_add_platform_device( | ||
| 19 | const char *name, int id, | ||
| 20 | const struct resource *res, unsigned int num_resources, | ||
| 21 | const void *data, size_t size_data) | ||
| 22 | { | ||
| 23 | return mxs_add_platform_device_dmamask( | ||
| 24 | name, id, res, num_resources, data, size_data, 0); | ||
| 25 | } | ||
| 26 | |||
| 27 | /* duart */ | ||
| 28 | struct mxs_duart_data { | ||
| 29 | resource_size_t iobase; | ||
| 30 | resource_size_t iosize; | ||
| 31 | resource_size_t irq; | ||
| 32 | }; | ||
| 33 | struct platform_device *__init mxs_add_duart( | ||
| 34 | const struct mxs_duart_data *data); | ||
| 35 | |||
| 36 | /* fec */ | ||
| 37 | #include <linux/fec.h> | ||
| 38 | struct mxs_fec_data { | ||
| 39 | int id; | ||
| 40 | resource_size_t iobase; | ||
| 41 | resource_size_t iosize; | ||
| 42 | resource_size_t irq; | ||
| 43 | }; | ||
| 44 | struct platform_device *__init mxs_add_fec( | ||
| 45 | const struct mxs_fec_data *data, | ||
| 46 | const struct fec_platform_data *pdata); | ||
diff --git a/arch/arm/mach-mxs/include/mach/entry-macro.S b/arch/arm/mach-mxs/include/mach/entry-macro.S new file mode 100644 index 000000000000..9f0da12e657a --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/entry-macro.S | |||
| @@ -0,0 +1,41 @@ | |||
| 1 | /* | ||
| 2 | * Low-level IRQ helper macros for Freescale MXS-based | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License along | ||
| 17 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include <mach/mxs.h> | ||
| 22 | |||
| 23 | #define MXS_ICOLL_VBASE MXS_IO_ADDRESS(MXS_ICOLL_BASE_ADDR) | ||
| 24 | #define HW_ICOLL_STAT_OFFSET 0x70 | ||
| 25 | |||
| 26 | .macro disable_fiq | ||
| 27 | .endm | ||
| 28 | |||
| 29 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 30 | ldr \irqnr, [\base, #HW_ICOLL_STAT_OFFSET] | ||
| 31 | cmp \irqnr, #0x7F | ||
| 32 | strne \irqnr, [\base] | ||
| 33 | moveqs \irqnr, #0 | ||
| 34 | .endm | ||
| 35 | |||
| 36 | .macro get_irqnr_preamble, base, tmp | ||
| 37 | ldr \base, =MXS_ICOLL_VBASE | ||
| 38 | .endm | ||
| 39 | |||
| 40 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 41 | .endm | ||
diff --git a/arch/arm/mach-mxs/include/mach/gpio.h b/arch/arm/mach-mxs/include/mach/gpio.h new file mode 100644 index 000000000000..828ccccb6aad --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/gpio.h | |||
| @@ -0,0 +1,35 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License | ||
| 7 | * as published by the Free Software Foundation; either version 2 | ||
| 8 | * of the License, or (at your option) any later version. | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 17 | * MA 02110-1301, USA. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef __MACH_MXS_GPIO_H__ | ||
| 21 | #define __MACH_MXS_GPIO_H__ | ||
| 22 | |||
| 23 | #include <asm-generic/gpio.h> | ||
| 24 | |||
| 25 | #define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr)) | ||
| 26 | |||
| 27 | /* use gpiolib dispatchers */ | ||
| 28 | #define gpio_get_value __gpio_get_value | ||
| 29 | #define gpio_set_value __gpio_set_value | ||
| 30 | #define gpio_cansleep __gpio_cansleep | ||
| 31 | #define gpio_to_irq __gpio_to_irq | ||
| 32 | |||
| 33 | #define irq_to_gpio(irq) ((irq) - MXS_GPIO_IRQ_START) | ||
| 34 | |||
| 35 | #endif /* __MACH_MXS_GPIO_H__ */ | ||
diff --git a/arch/arm/mach-mxs/include/mach/hardware.h b/arch/arm/mach-mxs/include/mach/hardware.h new file mode 100644 index 000000000000..53e89a09bf0d --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/hardware.h | |||
| @@ -0,0 +1,29 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License | ||
| 7 | * as published by the Free Software Foundation; either version 2 | ||
| 8 | * of the License, or (at your option) any later version. | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 17 | * MA 02110-1301, USA. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef __MACH_MXS_HARDWARE_H__ | ||
| 21 | #define __MACH_MXS_HARDWARE_H__ | ||
| 22 | |||
| 23 | #ifdef __ASSEMBLER__ | ||
| 24 | #define IOMEM(addr) (addr) | ||
| 25 | #else | ||
| 26 | #define IOMEM(addr) ((void __force __iomem *)(addr)) | ||
| 27 | #endif | ||
| 28 | |||
| 29 | #endif /* __MACH_MXS_HARDWARE_H__ */ | ||
diff --git a/arch/arm/mach-mxs/include/mach/io.h b/arch/arm/mach-mxs/include/mach/io.h new file mode 100644 index 000000000000..289b7227e072 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/io.h | |||
| @@ -0,0 +1,22 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | */ | ||
| 4 | |||
| 5 | /* | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __MACH_MXS_IO_H__ | ||
| 12 | #define __MACH_MXS_IO_H__ | ||
| 13 | |||
| 14 | /* Allow IO space to be anywhere in the memory */ | ||
| 15 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 16 | |||
| 17 | /* io address mapping macro */ | ||
| 18 | #define __io(a) __typesafe_io(a) | ||
| 19 | |||
| 20 | #define __mem_pci(a) (a) | ||
| 21 | |||
| 22 | #endif /* __MACH_MXS_IO_H__ */ | ||
diff --git a/arch/arm/mach-mxs/include/mach/iomux-mx23.h b/arch/arm/mach-mxs/include/mach/iomux-mx23.h new file mode 100644 index 000000000000..94e5dd83cdb8 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/iomux-mx23.h | |||
| @@ -0,0 +1,355 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> | ||
| 3 | * Copyright (C) 2010 Freescale Semiconductor, Inc. | ||
| 4 | * | ||
| 5 | * The code contained herein is licensed under the GNU General Public | ||
| 6 | * License. You may obtain a copy of the GNU General Public License | ||
| 7 | * Version 2 or later at the following locations: | ||
| 8 | * | ||
| 9 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 10 | * http://www.gnu.org/copyleft/gpl.html | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __MACH_IOMUX_MX23_H__ | ||
| 14 | #define __MACH_IOMUX_MX23_H__ | ||
| 15 | |||
| 16 | #include <mach/iomux.h> | ||
| 17 | |||
| 18 | /* | ||
| 19 | * The naming convention for the pad modes is MX23_PAD_<padname>__<padmode> | ||
| 20 | * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> | ||
| 21 | * See also iomux.h | ||
| 22 | * | ||
| 23 | * BANK PIN MUX | ||
| 24 | */ | ||
| 25 | /* MUXSEL_0 */ | ||
| 26 | #define MX23_PAD_GPMI_D00__GPMI_D00 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_0) | ||
| 27 | #define MX23_PAD_GPMI_D01__GPMI_D01 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_0) | ||
| 28 | #define MX23_PAD_GPMI_D02__GPMI_D02 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_0) | ||
| 29 | #define MX23_PAD_GPMI_D03__GPMI_D03 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0) | ||
| 30 | #define MX23_PAD_GPMI_D04__GPMI_D04 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_0) | ||
| 31 | #define MX23_PAD_GPMI_D05__GPMI_D05 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_0) | ||
| 32 | #define MX23_PAD_GPMI_D06__GPMI_D06 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0) | ||
| 33 | #define MX23_PAD_GPMI_D07__GPMI_D07 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0) | ||
| 34 | #define MX23_PAD_GPMI_D08__GPMI_D08 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_0) | ||
| 35 | #define MX23_PAD_GPMI_D09__GPMI_D09 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_0) | ||
| 36 | #define MX23_PAD_GPMI_D10__GPMI_D10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_0) | ||
| 37 | #define MX23_PAD_GPMI_D11__GPMI_D11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_0) | ||
| 38 | #define MX23_PAD_GPMI_D12__GPMI_D12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_0) | ||
| 39 | #define MX23_PAD_GPMI_D13__GPMI_D13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_0) | ||
| 40 | #define MX23_PAD_GPMI_D14__GPMI_D14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_0) | ||
| 41 | #define MX23_PAD_GPMI_D15__GPMI_D15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_0) | ||
| 42 | #define MX23_PAD_GPMI_CLE__GPMI_CLE MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0) | ||
| 43 | #define MX23_PAD_GPMI_ALE__GPMI_ALE MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0) | ||
| 44 | #define MX23_PAD_GPMI_CE2N__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0) | ||
| 45 | #define MX23_PAD_GPMI_RDY0__GPMI_RDY0 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0) | ||
| 46 | #define MX23_PAD_GPMI_RDY1__GPMI_RDY1 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0) | ||
| 47 | #define MX23_PAD_GPMI_RDY2__GPMI_RDY2 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0) | ||
| 48 | #define MX23_PAD_GPMI_RDY3__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0) | ||
| 49 | #define MX23_PAD_GPMI_WPN__GPMI_WPN MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0) | ||
| 50 | #define MX23_PAD_GPMI_WRN__GPMI_WRN MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0) | ||
| 51 | #define MX23_PAD_GPMI_RDN__GPMI_RDN MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0) | ||
| 52 | #define MX23_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0) | ||
| 53 | #define MX23_PAD_AUART1_RTS__AUART1_RTS MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0) | ||
| 54 | #define MX23_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0) | ||
| 55 | #define MX23_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_0) | ||
| 56 | #define MX23_PAD_I2C_SCL__I2C_SCL MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_0) | ||
| 57 | #define MX23_PAD_I2C_SDA__I2C_SDA MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_0) | ||
| 58 | |||
| 59 | #define MX23_PAD_LCD_D00__LCD_D00 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_0) | ||
| 60 | #define MX23_PAD_LCD_D01__LCD_D01 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_0) | ||
| 61 | #define MX23_PAD_LCD_D02__LCD_D02 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_0) | ||
| 62 | #define MX23_PAD_LCD_D03__LCD_D03 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0) | ||
| 63 | #define MX23_PAD_LCD_D04__LCD_D04 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_0) | ||
| 64 | #define MX23_PAD_LCD_D05__LCD_D05 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_0) | ||
| 65 | #define MX23_PAD_LCD_D06__LCD_D06 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0) | ||
| 66 | #define MX23_PAD_LCD_D07__LCD_D07 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0) | ||
| 67 | #define MX23_PAD_LCD_D08__LCD_D08 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_0) | ||
| 68 | #define MX23_PAD_LCD_D09__LCD_D09 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_0) | ||
| 69 | #define MX23_PAD_LCD_D10__LCD_D10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0) | ||
| 70 | #define MX23_PAD_LCD_D11__LCD_D11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0) | ||
| 71 | #define MX23_PAD_LCD_D12__LCD_D12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0) | ||
| 72 | #define MX23_PAD_LCD_D13__LCD_D13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0) | ||
| 73 | #define MX23_PAD_LCD_D14__LCD_D14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0) | ||
| 74 | #define MX23_PAD_LCD_D15__LCD_D15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0) | ||
| 75 | #define MX23_PAD_LCD_D16__LCD_D16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0) | ||
| 76 | #define MX23_PAD_LCD_D17__LCD_D17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0) | ||
| 77 | #define MX23_PAD_LCD_RESET__LCD_RESET MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0) | ||
| 78 | #define MX23_PAD_LCD_RS__LCD_RS MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0) | ||
| 79 | #define MX23_PAD_LCD_WR__LCD_WR MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0) | ||
| 80 | #define MX23_PAD_LCD_CS__LCD_CS MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0) | ||
| 81 | #define MX23_PAD_LCD_DOTCK__LCD_DOTCK MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0) | ||
| 82 | #define MX23_PAD_LCD_ENABLE__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0) | ||
| 83 | #define MX23_PAD_LCD_HSYNC__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0) | ||
| 84 | #define MX23_PAD_LCD_VSYNC__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0) | ||
| 85 | #define MX23_PAD_PWM0__PWM0 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0) | ||
| 86 | #define MX23_PAD_PWM1__PWM1 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0) | ||
| 87 | #define MX23_PAD_PWM2__PWM2 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0) | ||
| 88 | #define MX23_PAD_PWM3__PWM3 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0) | ||
| 89 | #define MX23_PAD_PWM4__PWM4 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0) | ||
| 90 | |||
| 91 | #define MX23_PAD_SSP1_CMD__SSP1_CMD MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_0) | ||
| 92 | #define MX23_PAD_SSP1_DETECT__SSP1_DETECT MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_0) | ||
| 93 | #define MX23_PAD_SSP1_DATA0__SSP1_DATA0 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_0) | ||
| 94 | #define MX23_PAD_SSP1_DATA1__SSP1_DATA1 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0) | ||
| 95 | #define MX23_PAD_SSP1_DATA2__SSP1_DATA2 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_0) | ||
| 96 | #define MX23_PAD_SSP1_DATA3__SSP1_DATA3 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_0) | ||
| 97 | #define MX23_PAD_SSP1_SCK__SSP1_SCK MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0) | ||
| 98 | #define MX23_PAD_ROTARYA__ROTARYA MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0) | ||
| 99 | #define MX23_PAD_ROTARYB__ROTARYB MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_0) | ||
| 100 | #define MX23_PAD_EMI_A00__EMI_A00 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_0) | ||
| 101 | #define MX23_PAD_EMI_A01__EMI_A01 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0) | ||
| 102 | #define MX23_PAD_EMI_A02__EMI_A02 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_0) | ||
| 103 | #define MX23_PAD_EMI_A03__EMI_A03 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0) | ||
| 104 | #define MX23_PAD_EMI_A04__EMI_A04 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0) | ||
| 105 | #define MX23_PAD_EMI_A05__EMI_A05 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0) | ||
| 106 | #define MX23_PAD_EMI_A06__EMI_A06 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0) | ||
| 107 | #define MX23_PAD_EMI_A07__EMI_A07 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0) | ||
| 108 | #define MX23_PAD_EMI_A08__EMI_A08 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0) | ||
| 109 | #define MX23_PAD_EMI_A09__EMI_A09 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0) | ||
| 110 | #define MX23_PAD_EMI_A10__EMI_A10 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0) | ||
| 111 | #define MX23_PAD_EMI_A11__EMI_A11 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0) | ||
| 112 | #define MX23_PAD_EMI_A12__EMI_A12 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0) | ||
| 113 | #define MX23_PAD_EMI_BA0__EMI_BA0 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_0) | ||
| 114 | #define MX23_PAD_EMI_BA1__EMI_BA1 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_0) | ||
| 115 | #define MX23_PAD_EMI_CASN__EMI_CASN MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0) | ||
| 116 | #define MX23_PAD_EMI_CE0N__EMI_CE0N MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0) | ||
| 117 | #define MX23_PAD_EMI_CE1N__EMI_CE1N MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0) | ||
| 118 | #define MX23_PAD_GPMI_CE1N__GPMI_CE1N MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0) | ||
| 119 | #define MX23_PAD_GPMI_CE0N__GPMI_CE0N MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_0) | ||
| 120 | #define MX23_PAD_EMI_CKE__EMI_CKE MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_0) | ||
| 121 | #define MX23_PAD_EMI_RASN__EMI_RASN MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_0) | ||
| 122 | #define MX23_PAD_EMI_WEN__EMI_WEN MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_0) | ||
| 123 | |||
| 124 | #define MX23_PAD_EMI_D00__EMI_D00 MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0) | ||
| 125 | #define MX23_PAD_EMI_D01__EMI_D01 MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0) | ||
| 126 | #define MX23_PAD_EMI_D02__EMI_D02 MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0) | ||
| 127 | #define MX23_PAD_EMI_D03__EMI_D03 MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0) | ||
| 128 | #define MX23_PAD_EMI_D04__EMI_D04 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0) | ||
| 129 | #define MX23_PAD_EMI_D05__EMI_D05 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0) | ||
| 130 | #define MX23_PAD_EMI_D06__EMI_D06 MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0) | ||
| 131 | #define MX23_PAD_EMI_D07__EMI_D07 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0) | ||
| 132 | #define MX23_PAD_EMI_D08__EMI_D08 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_0) | ||
| 133 | #define MX23_PAD_EMI_D09__EMI_D09 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_0) | ||
| 134 | #define MX23_PAD_EMI_D10__EMI_D10 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0) | ||
| 135 | #define MX23_PAD_EMI_D11__EMI_D11 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0) | ||
| 136 | #define MX23_PAD_EMI_D12__EMI_D12 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0) | ||
| 137 | #define MX23_PAD_EMI_D13__EMI_D13 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0) | ||
| 138 | #define MX23_PAD_EMI_D14__EMI_D14 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0) | ||
| 139 | #define MX23_PAD_EMI_D15__EMI_D15 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0) | ||
| 140 | #define MX23_PAD_EMI_DQM0__EMI_DQM0 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0) | ||
| 141 | #define MX23_PAD_EMI_DQM1__EMI_DQM1 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0) | ||
| 142 | #define MX23_PAD_EMI_DQS0__EMI_DQS0 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0) | ||
| 143 | #define MX23_PAD_EMI_DQS1__EMI_DQS1 MXS_IOMUX_PAD_NAKED(3, 19, PAD_MUXSEL_0) | ||
| 144 | #define MX23_PAD_EMI_CLK__EMI_CLK MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0) | ||
| 145 | #define MX23_PAD_EMI_CLKN__EMI_CLKN MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0) | ||
| 146 | |||
| 147 | /* MUXSEL_1 */ | ||
| 148 | #define MX23_PAD_GPMI_D00__LCD_D8 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_1) | ||
| 149 | #define MX23_PAD_GPMI_D01__LCD_D9 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_1) | ||
| 150 | #define MX23_PAD_GPMI_D02__LCD_D10 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_1) | ||
| 151 | #define MX23_PAD_GPMI_D03__LCD_D11 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_1) | ||
| 152 | #define MX23_PAD_GPMI_D04__LCD_D12 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_1) | ||
| 153 | #define MX23_PAD_GPMI_D05__LCD_D13 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_1) | ||
| 154 | #define MX23_PAD_GPMI_D06__LCD_D14 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_1) | ||
| 155 | #define MX23_PAD_GPMI_D07__LCD_D15 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1) | ||
| 156 | #define MX23_PAD_GPMI_D08__LCD_D18 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_1) | ||
| 157 | #define MX23_PAD_GPMI_D09__LCD_D19 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_1) | ||
| 158 | #define MX23_PAD_GPMI_D10__LCD_D20 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_1) | ||
| 159 | #define MX23_PAD_GPMI_D11__LCD_D21 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_1) | ||
| 160 | #define MX23_PAD_GPMI_D12__LCD_D22 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_1) | ||
| 161 | #define MX23_PAD_GPMI_D13__LCD_D23 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_1) | ||
| 162 | #define MX23_PAD_GPMI_D14__AUART2_RX MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_1) | ||
| 163 | #define MX23_PAD_GPMI_D15__AUART2_TX MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_1) | ||
| 164 | #define MX23_PAD_GPMI_CLE__LCD_D16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1) | ||
| 165 | #define MX23_PAD_GPMI_ALE__LCD_D17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1) | ||
| 166 | #define MX23_PAD_GPMI_CE2N__ATA_A2 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1) | ||
| 167 | #define MX23_PAD_AUART1_RTS__IR_CLK MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1) | ||
| 168 | #define MX23_PAD_AUART1_RX__IR_RX MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1) | ||
| 169 | #define MX23_PAD_AUART1_TX__IR_TX MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_1) | ||
| 170 | #define MX23_PAD_I2C_SCL__GPMI_RDY2 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_1) | ||
| 171 | #define MX23_PAD_I2C_SDA__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_1) | ||
| 172 | |||
| 173 | #define MX23_PAD_LCD_D00__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_1) | ||
| 174 | #define MX23_PAD_LCD_D01__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_1) | ||
| 175 | #define MX23_PAD_LCD_D02__ETM_DA10 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_1) | ||
| 176 | #define MX23_PAD_LCD_D03__ETM_DA11 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_1) | ||
| 177 | #define MX23_PAD_LCD_D04__ETM_DA12 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_1) | ||
| 178 | #define MX23_PAD_LCD_D05__ETM_DA13 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_1) | ||
| 179 | #define MX23_PAD_LCD_D06__ETM_DA14 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_1) | ||
| 180 | #define MX23_PAD_LCD_D07__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_1) | ||
| 181 | #define MX23_PAD_LCD_D08__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_1) | ||
| 182 | #define MX23_PAD_LCD_D09__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_1) | ||
| 183 | #define MX23_PAD_LCD_D10__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_1) | ||
| 184 | #define MX23_PAD_LCD_D11__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_1) | ||
| 185 | #define MX23_PAD_LCD_D12__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_1) | ||
| 186 | #define MX23_PAD_LCD_D13__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_1) | ||
| 187 | #define MX23_PAD_LCD_D14__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_1) | ||
| 188 | #define MX23_PAD_LCD_D15__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_1) | ||
| 189 | #define MX23_PAD_LCD_RESET__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_1) | ||
| 190 | #define MX23_PAD_LCD_RS__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_1) | ||
| 191 | #define MX23_PAD_LCD_DOTCK__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1) | ||
| 192 | #define MX23_PAD_LCD_ENABLE__I2C_SCL MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1) | ||
| 193 | #define MX23_PAD_LCD_HSYNC__I2C_SDA MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1) | ||
| 194 | #define MX23_PAD_LCD_VSYNC__LCD_BUSY MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1) | ||
| 195 | #define MX23_PAD_PWM0__ROTARYA MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1) | ||
| 196 | #define MX23_PAD_PWM1__ROTARYB MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1) | ||
| 197 | #define MX23_PAD_PWM2__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1) | ||
| 198 | #define MX23_PAD_PWM3__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1) | ||
| 199 | #define MX23_PAD_PWM4__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1) | ||
| 200 | |||
| 201 | #define MX23_PAD_SSP1_DETECT__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_1) | ||
| 202 | #define MX23_PAD_SSP1_DATA1__I2C_SCL MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_1) | ||
| 203 | #define MX23_PAD_SSP1_DATA2__I2C_SDA MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_1) | ||
| 204 | #define MX23_PAD_ROTARYA__AUART2_RTS MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1) | ||
| 205 | #define MX23_PAD_ROTARYB__AUART2_CTS MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_1) | ||
| 206 | |||
| 207 | /* MUXSEL_2 */ | ||
| 208 | #define MX23_PAD_GPMI_D00__SSP2_DATA0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_2) | ||
| 209 | #define MX23_PAD_GPMI_D01__SSP2_DATA1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_2) | ||
| 210 | #define MX23_PAD_GPMI_D02__SSP2_DATA2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_2) | ||
| 211 | #define MX23_PAD_GPMI_D03__SSP2_DATA3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_2) | ||
| 212 | #define MX23_PAD_GPMI_D04__SSP2_DATA4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_2) | ||
| 213 | #define MX23_PAD_GPMI_D05__SSP2_DATA5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_2) | ||
| 214 | #define MX23_PAD_GPMI_D06__SSP2_DATA6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_2) | ||
| 215 | #define MX23_PAD_GPMI_D07__SSP2_DATA7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_2) | ||
| 216 | #define MX23_PAD_GPMI_D08__SSP1_DATA4 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_2) | ||
| 217 | #define MX23_PAD_GPMI_D09__SSP1_DATA5 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_2) | ||
| 218 | #define MX23_PAD_GPMI_D10__SSP1_DATA6 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_2) | ||
| 219 | #define MX23_PAD_GPMI_D11__SSP1_DATA7 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_2) | ||
| 220 | #define MX23_PAD_GPMI_D15__GPMI_CE3N MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_2) | ||
| 221 | #define MX23_PAD_GPMI_RDY0__SSP2_DETECT MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2) | ||
| 222 | #define MX23_PAD_GPMI_RDY1__SSP2_CMD MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2) | ||
| 223 | #define MX23_PAD_GPMI_WRN__SSP2_SCK MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_2) | ||
| 224 | #define MX23_PAD_AUART1_CTS__SSP1_DATA4 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2) | ||
| 225 | #define MX23_PAD_AUART1_RTS__SSP1_DATA5 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2) | ||
| 226 | #define MX23_PAD_AUART1_RX__SSP1_DATA6 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_2) | ||
| 227 | #define MX23_PAD_AUART1_TX__SSP1_DATA7 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_2) | ||
| 228 | #define MX23_PAD_I2C_SCL__AUART1_TX MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_2) | ||
| 229 | #define MX23_PAD_I2C_SDA__AUART1_RX MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_2) | ||
| 230 | |||
| 231 | #define MX23_PAD_LCD_D08__SAIF2_SDATA0 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_2) | ||
| 232 | #define MX23_PAD_LCD_D09__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_2) | ||
| 233 | #define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2) | ||
| 234 | #define MX23_PAD_LCD_D11__SAIF_LRCLK MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2) | ||
| 235 | #define MX23_PAD_LCD_D12__SAIF2_SDATA1 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2) | ||
| 236 | #define MX23_PAD_LCD_D13__SAIF2_SDATA2 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2) | ||
| 237 | #define MX23_PAD_LCD_D14__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2) | ||
| 238 | #define MX23_PAD_LCD_D15__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2) | ||
| 239 | #define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2) | ||
| 240 | #define MX23_PAD_LCD_RESET__GPMI_CE3N MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2) | ||
| 241 | #define MX23_PAD_PWM0__DUART_RX MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_2) | ||
| 242 | #define MX23_PAD_PWM1__DUART_TX MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_2) | ||
| 243 | #define MX23_PAD_PWM3__AUART1_CTS MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2) | ||
| 244 | #define MX23_PAD_PWM4__AUART1_RTS MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2) | ||
| 245 | |||
| 246 | #define MX23_PAD_SSP1_CMD__JTAG_TDO MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_2) | ||
| 247 | #define MX23_PAD_SSP1_DETECT__USB_OTG_ID MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_2) | ||
| 248 | #define MX23_PAD_SSP1_DATA0__JTAG_TDI MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_2) | ||
| 249 | #define MX23_PAD_SSP1_DATA1__JTAG_TCLK MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_2) | ||
| 250 | #define MX23_PAD_SSP1_DATA2__JTAG_RTCK MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_2) | ||
| 251 | #define MX23_PAD_SSP1_DATA3__JTAG_TMS MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_2) | ||
| 252 | #define MX23_PAD_SSP1_SCK__JTAG_TRST MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_2) | ||
| 253 | #define MX23_PAD_ROTARYA__SPDIF MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_2) | ||
| 254 | #define MX23_PAD_ROTARYB__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_2) | ||
| 255 | |||
| 256 | /* MUXSEL_GPIO */ | ||
| 257 | #define MX23_PAD_GPMI_D00__GPO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO) | ||
| 258 | #define MX23_PAD_GPMI_D01__GPO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO) | ||
| 259 | #define MX23_PAD_GPMI_D02__GPO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO) | ||
| 260 | #define MX23_PAD_GPMI_D03__GPO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO) | ||
| 261 | #define MX23_PAD_GPMI_D04__GPO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO) | ||
| 262 | #define MX23_PAD_GPMI_D05__GPO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO) | ||
| 263 | #define MX23_PAD_GPMI_D06__GPO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO) | ||
| 264 | #define MX23_PAD_GPMI_D07__GPO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO) | ||
| 265 | #define MX23_PAD_GPMI_D08__GPO_0_8 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_GPIO) | ||
| 266 | #define MX23_PAD_GPMI_D09__GPO_0_9 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_GPIO) | ||
| 267 | #define MX23_PAD_GPMI_D10__GPO_0_10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO) | ||
| 268 | #define MX23_PAD_GPMI_D11__GPO_0_11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO) | ||
| 269 | #define MX23_PAD_GPMI_D12__GPO_0_12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO) | ||
| 270 | #define MX23_PAD_GPMI_D13__GPO_0_13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO) | ||
| 271 | #define MX23_PAD_GPMI_D14__GPO_0_14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO) | ||
| 272 | #define MX23_PAD_GPMI_D15__GPO_0_15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO) | ||
| 273 | #define MX23_PAD_GPMI_CLE__GPO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO) | ||
| 274 | #define MX23_PAD_GPMI_ALE__GPO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO) | ||
| 275 | #define MX23_PAD_GPMI_CE2N__GPO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO) | ||
| 276 | #define MX23_PAD_GPMI_RDY0__GPO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO) | ||
| 277 | #define MX23_PAD_GPMI_RDY1__GPO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO) | ||
| 278 | #define MX23_PAD_GPMI_RDY2__GPO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO) | ||
| 279 | #define MX23_PAD_GPMI_RDY3__GPO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO) | ||
| 280 | #define MX23_PAD_GPMI_WPN__GPO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO) | ||
| 281 | #define MX23_PAD_GPMI_WRN__GPO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO) | ||
| 282 | #define MX23_PAD_GPMI_RDN__GPO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO) | ||
| 283 | #define MX23_PAD_AUART1_CTS__GPO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO) | ||
| 284 | #define MX23_PAD_AUART1_RTS__GPO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO) | ||
| 285 | #define MX23_PAD_AUART1_RX__GPO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO) | ||
| 286 | #define MX23_PAD_AUART1_TX__GPO_0_29 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO) | ||
| 287 | #define MX23_PAD_I2C_SCL__GPO_0_30 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO) | ||
| 288 | #define MX23_PAD_I2C_SDA__GPO_0_31 MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO) | ||
| 289 | |||
| 290 | #define MX23_PAD_LCD_D00__GPO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO) | ||
| 291 | #define MX23_PAD_LCD_D01__GPO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO) | ||
| 292 | #define MX23_PAD_LCD_D02__GPO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO) | ||
| 293 | #define MX23_PAD_LCD_D03__GPO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO) | ||
| 294 | #define MX23_PAD_LCD_D04__GPO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO) | ||
| 295 | #define MX23_PAD_LCD_D05__GPO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO) | ||
| 296 | #define MX23_PAD_LCD_D06__GPO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO) | ||
| 297 | #define MX23_PAD_LCD_D07__GPO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO) | ||
| 298 | #define MX23_PAD_LCD_D08__GPO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO) | ||
| 299 | #define MX23_PAD_LCD_D09__GPO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO) | ||
| 300 | #define MX23_PAD_LCD_D10__GPO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO) | ||
| 301 | #define MX23_PAD_LCD_D11__GPO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO) | ||
| 302 | #define MX23_PAD_LCD_D12__GPO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO) | ||
| 303 | #define MX23_PAD_LCD_D13__GPO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO) | ||
| 304 | #define MX23_PAD_LCD_D14__GPO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO) | ||
| 305 | #define MX23_PAD_LCD_D15__GPO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO) | ||
| 306 | #define MX23_PAD_LCD_D16__GPO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO) | ||
| 307 | #define MX23_PAD_LCD_D17__GPO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO) | ||
| 308 | #define MX23_PAD_LCD_RESET__GPO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO) | ||
| 309 | #define MX23_PAD_LCD_RS__GPO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO) | ||
| 310 | #define MX23_PAD_LCD_WR__GPO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO) | ||
| 311 | #define MX23_PAD_LCD_CS__GPO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO) | ||
| 312 | #define MX23_PAD_LCD_DOTCK__GPO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO) | ||
| 313 | #define MX23_PAD_LCD_ENABLE__GPO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO) | ||
| 314 | #define MX23_PAD_LCD_HSYNC__GPO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO) | ||
| 315 | #define MX23_PAD_LCD_VSYNC__GPO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO) | ||
| 316 | #define MX23_PAD_PWM0__GPO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO) | ||
| 317 | #define MX23_PAD_PWM1__GPO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO) | ||
| 318 | #define MX23_PAD_PWM2__GPO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO) | ||
| 319 | #define MX23_PAD_PWM3__GPO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO) | ||
| 320 | #define MX23_PAD_PWM4__GPO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO) | ||
| 321 | |||
| 322 | #define MX23_PAD_SSP1_CMD__GPO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO) | ||
| 323 | #define MX23_PAD_SSP1_DETECT__GPO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO) | ||
| 324 | #define MX23_PAD_SSP1_DATA0__GPO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO) | ||
| 325 | #define MX23_PAD_SSP1_DATA1__GPO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO) | ||
| 326 | #define MX23_PAD_SSP1_DATA2__GPO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO) | ||
| 327 | #define MX23_PAD_SSP1_DATA3__GPO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO) | ||
| 328 | #define MX23_PAD_SSP1_SCK__GPO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO) | ||
| 329 | #define MX23_PAD_ROTARYA__GPO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO) | ||
| 330 | #define MX23_PAD_ROTARYB__GPO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO) | ||
| 331 | #define MX23_PAD_EMI_A00__GPO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO) | ||
| 332 | #define MX23_PAD_EMI_A01__GPO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO) | ||
| 333 | #define MX23_PAD_EMI_A02__GPO_2_11 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO) | ||
| 334 | #define MX23_PAD_EMI_A03__GPO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO) | ||
| 335 | #define MX23_PAD_EMI_A04__GPO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO) | ||
| 336 | #define MX23_PAD_EMI_A05__GPO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO) | ||
| 337 | #define MX23_PAD_EMI_A06__GPO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO) | ||
| 338 | #define MX23_PAD_EMI_A07__GPO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO) | ||
| 339 | #define MX23_PAD_EMI_A08__GPO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO) | ||
| 340 | #define MX23_PAD_EMI_A09__GPO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO) | ||
| 341 | #define MX23_PAD_EMI_A10__GPO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO) | ||
| 342 | #define MX23_PAD_EMI_A11__GPO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO) | ||
| 343 | #define MX23_PAD_EMI_A12__GPO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO) | ||
| 344 | #define MX23_PAD_EMI_BA0__GPO_2_22 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO) | ||
| 345 | #define MX23_PAD_EMI_BA1__GPO_2_23 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO) | ||
| 346 | #define MX23_PAD_EMI_CASN__GPO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO) | ||
| 347 | #define MX23_PAD_EMI_CE0N__GPO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO) | ||
| 348 | #define MX23_PAD_EMI_CE1N__GPO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO) | ||
| 349 | #define MX23_PAD_GPMI_CE1N__GPO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO) | ||
| 350 | #define MX23_PAD_GPMI_CE0N__GPO_2_28 MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO) | ||
| 351 | #define MX23_PAD_EMI_CKE__GPO_2_29 MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO) | ||
| 352 | #define MX23_PAD_EMI_RASN__GPO_2_30 MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO) | ||
| 353 | #define MX23_PAD_EMI_WEN__GPO_2_31 MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO) | ||
| 354 | |||
| 355 | #endif /* __MACH_IOMUX_MX23_H__ */ | ||
diff --git a/arch/arm/mach-mxs/include/mach/iomux-mx28.h b/arch/arm/mach-mxs/include/mach/iomux-mx28.h new file mode 100644 index 000000000000..f50fefd10520 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/iomux-mx28.h | |||
| @@ -0,0 +1,537 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> | ||
| 3 | * Copyright (C) 2010 Freescale Semiconductor, Inc. | ||
| 4 | * | ||
| 5 | * The code contained herein is licensed under the GNU General Public | ||
| 6 | * License. You may obtain a copy of the GNU General Public License | ||
| 7 | * Version 2 or later at the following locations: | ||
| 8 | * | ||
| 9 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 10 | * http://www.gnu.org/copyleft/gpl.html | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __MACH_IOMUX_MX28_H__ | ||
| 14 | #define __MACH_IOMUX_MX28_H__ | ||
| 15 | |||
| 16 | #include <mach/iomux.h> | ||
| 17 | |||
| 18 | /* | ||
| 19 | * The naming convention for the pad modes is MX28_PAD_<padname>__<padmode> | ||
| 20 | * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> | ||
| 21 | * See also iomux.h | ||
| 22 | * | ||
| 23 | * BANK PIN MUX | ||
| 24 | */ | ||
| 25 | /* MUXSEL_0 */ | ||
| 26 | #define MX28_PAD_GPMI_D00__GPMI_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_0) | ||
| 27 | #define MX28_PAD_GPMI_D01__GPMI_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_0) | ||
| 28 | #define MX28_PAD_GPMI_D02__GPMI_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_0) | ||
| 29 | #define MX28_PAD_GPMI_D03__GPMI_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0) | ||
| 30 | #define MX28_PAD_GPMI_D04__GPMI_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_0) | ||
| 31 | #define MX28_PAD_GPMI_D05__GPMI_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_0) | ||
| 32 | #define MX28_PAD_GPMI_D06__GPMI_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0) | ||
| 33 | #define MX28_PAD_GPMI_D07__GPMI_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0) | ||
| 34 | #define MX28_PAD_GPMI_CE0N__GPMI_CE0N MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0) | ||
| 35 | #define MX28_PAD_GPMI_CE1N__GPMI_CE1N MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0) | ||
| 36 | #define MX28_PAD_GPMI_CE2N__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0) | ||
| 37 | #define MX28_PAD_GPMI_CE3N__GPMI_CE3N MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0) | ||
| 38 | #define MX28_PAD_GPMI_RDY0__GPMI_READY0 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0) | ||
| 39 | #define MX28_PAD_GPMI_RDY1__GPMI_READY1 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0) | ||
| 40 | #define MX28_PAD_GPMI_RDY2__GPMI_READY2 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0) | ||
| 41 | #define MX28_PAD_GPMI_RDY3__GPMI_READY3 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0) | ||
| 42 | #define MX28_PAD_GPMI_RDN__GPMI_RDN MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0) | ||
| 43 | #define MX28_PAD_GPMI_WRN__GPMI_WRN MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0) | ||
| 44 | #define MX28_PAD_GPMI_ALE__GPMI_ALE MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0) | ||
| 45 | #define MX28_PAD_GPMI_CLE__GPMI_CLE MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0) | ||
| 46 | #define MX28_PAD_GPMI_RESETN__GPMI_RESETN MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0) | ||
| 47 | |||
| 48 | #define MX28_PAD_LCD_D00__LCD_D0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_0) | ||
| 49 | #define MX28_PAD_LCD_D01__LCD_D1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_0) | ||
| 50 | #define MX28_PAD_LCD_D02__LCD_D2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_0) | ||
| 51 | #define MX28_PAD_LCD_D03__LCD_D3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0) | ||
| 52 | #define MX28_PAD_LCD_D04__LCD_D4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_0) | ||
| 53 | #define MX28_PAD_LCD_D05__LCD_D5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_0) | ||
| 54 | #define MX28_PAD_LCD_D06__LCD_D6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0) | ||
| 55 | #define MX28_PAD_LCD_D07__LCD_D7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0) | ||
| 56 | #define MX28_PAD_LCD_D08__LCD_D8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_0) | ||
| 57 | #define MX28_PAD_LCD_D09__LCD_D9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_0) | ||
| 58 | #define MX28_PAD_LCD_D10__LCD_D10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0) | ||
| 59 | #define MX28_PAD_LCD_D11__LCD_D11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0) | ||
| 60 | #define MX28_PAD_LCD_D12__LCD_D12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0) | ||
| 61 | #define MX28_PAD_LCD_D13__LCD_D13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0) | ||
| 62 | #define MX28_PAD_LCD_D14__LCD_D14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0) | ||
| 63 | #define MX28_PAD_LCD_D15__LCD_D15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0) | ||
| 64 | #define MX28_PAD_LCD_D16__LCD_D16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0) | ||
| 65 | #define MX28_PAD_LCD_D17__LCD_D17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0) | ||
| 66 | #define MX28_PAD_LCD_D18__LCD_D18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0) | ||
| 67 | #define MX28_PAD_LCD_D19__LCD_D19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0) | ||
| 68 | #define MX28_PAD_LCD_D20__LCD_D20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0) | ||
| 69 | #define MX28_PAD_LCD_D21__LCD_D21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0) | ||
| 70 | #define MX28_PAD_LCD_D22__LCD_D22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0) | ||
| 71 | #define MX28_PAD_LCD_D23__LCD_D23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0) | ||
| 72 | #define MX28_PAD_LCD_RD_E__LCD_RD_E MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0) | ||
| 73 | #define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0) | ||
| 74 | #define MX28_PAD_LCD_RS__LCD_RS MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0) | ||
| 75 | #define MX28_PAD_LCD_CS__LCD_CS MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0) | ||
| 76 | #define MX28_PAD_LCD_VSYNC__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0) | ||
| 77 | #define MX28_PAD_LCD_HSYNC__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0) | ||
| 78 | #define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0) | ||
| 79 | #define MX28_PAD_LCD_ENABLE__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_0) | ||
| 80 | |||
| 81 | #define MX28_PAD_SSP0_DATA0__SSP0_D0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_0) | ||
| 82 | #define MX28_PAD_SSP0_DATA1__SSP0_D1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_0) | ||
| 83 | #define MX28_PAD_SSP0_DATA2__SSP0_D2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_0) | ||
| 84 | #define MX28_PAD_SSP0_DATA3__SSP0_D3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0) | ||
| 85 | #define MX28_PAD_SSP0_DATA4__SSP0_D4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_0) | ||
| 86 | #define MX28_PAD_SSP0_DATA5__SSP0_D5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_0) | ||
| 87 | #define MX28_PAD_SSP0_DATA6__SSP0_D6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0) | ||
| 88 | #define MX28_PAD_SSP0_DATA7__SSP0_D7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0) | ||
| 89 | #define MX28_PAD_SSP0_CMD__SSP0_CMD MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_0) | ||
| 90 | #define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_0) | ||
| 91 | #define MX28_PAD_SSP0_SCK__SSP0_SCK MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0) | ||
| 92 | #define MX28_PAD_SSP1_SCK__SSP1_SCK MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0) | ||
| 93 | #define MX28_PAD_SSP1_CMD__SSP1_CMD MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0) | ||
| 94 | #define MX28_PAD_SSP1_DATA0__SSP1_D0 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0) | ||
| 95 | #define MX28_PAD_SSP1_DATA3__SSP1_D3 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0) | ||
| 96 | #define MX28_PAD_SSP2_SCK__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0) | ||
| 97 | #define MX28_PAD_SSP2_MOSI__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0) | ||
| 98 | #define MX28_PAD_SSP2_MISO__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0) | ||
| 99 | #define MX28_PAD_SSP2_SS0__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0) | ||
| 100 | #define MX28_PAD_SSP2_SS1__SSP2_D4 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0) | ||
| 101 | #define MX28_PAD_SSP2_SS2__SSP2_D5 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0) | ||
| 102 | #define MX28_PAD_SSP3_SCK__SSP3_SCK MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0) | ||
| 103 | #define MX28_PAD_SSP3_MOSI__SSP3_CMD MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0) | ||
| 104 | #define MX28_PAD_SSP3_MISO__SSP3_D0 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0) | ||
| 105 | #define MX28_PAD_SSP3_SS0__SSP3_D3 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0) | ||
| 106 | |||
| 107 | #define MX28_PAD_AUART0_RX__AUART0_RX MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0) | ||
| 108 | #define MX28_PAD_AUART0_TX__AUART0_TX MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0) | ||
| 109 | #define MX28_PAD_AUART0_CTS__AUART0_CTS MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0) | ||
| 110 | #define MX28_PAD_AUART0_RTS__AUART0_RTS MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0) | ||
| 111 | #define MX28_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0) | ||
| 112 | #define MX28_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0) | ||
| 113 | #define MX28_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0) | ||
| 114 | #define MX28_PAD_AUART1_RTS__AUART1_RTS MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0) | ||
| 115 | #define MX28_PAD_AUART2_RX__AUART2_RX MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_0) | ||
| 116 | #define MX28_PAD_AUART2_TX__AUART2_TX MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_0) | ||
| 117 | #define MX28_PAD_AUART2_CTS__AUART2_CTS MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0) | ||
| 118 | #define MX28_PAD_AUART2_RTS__AUART2_RTS MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0) | ||
| 119 | #define MX28_PAD_AUART3_RX__AUART3_RX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0) | ||
| 120 | #define MX28_PAD_AUART3_TX__AUART3_TX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0) | ||
| 121 | #define MX28_PAD_AUART3_CTS__AUART3_CTS MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0) | ||
| 122 | #define MX28_PAD_AUART3_RTS__AUART3_RTS MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0) | ||
| 123 | #define MX28_PAD_PWM0__PWM_0 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0) | ||
| 124 | #define MX28_PAD_PWM1__PWM_1 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0) | ||
| 125 | #define MX28_PAD_PWM2__PWM_2 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0) | ||
| 126 | #define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0) | ||
| 127 | #define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0) | ||
| 128 | #define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_0) | ||
| 129 | #define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_0) | ||
| 130 | #define MX28_PAD_I2C0_SCL__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_0) | ||
| 131 | #define MX28_PAD_I2C0_SDA__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_0) | ||
| 132 | #define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_0) | ||
| 133 | #define MX28_PAD_SPDIF__SPDIF_TX MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_0) | ||
| 134 | #define MX28_PAD_PWM3__PWM_3 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_0) | ||
| 135 | #define MX28_PAD_PWM4__PWM_4 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_0) | ||
| 136 | #define MX28_PAD_LCD_RESET__LCD_RESET MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_0) | ||
| 137 | |||
| 138 | #define MX28_PAD_ENET0_MDC__ENET0_MDC MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_0) | ||
| 139 | #define MX28_PAD_ENET0_MDIO__ENET0_MDIO MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_0) | ||
| 140 | #define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_0) | ||
| 141 | #define MX28_PAD_ENET0_RXD0__ENET0_RXD0 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_0) | ||
| 142 | #define MX28_PAD_ENET0_RXD1__ENET0_RXD1 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_0) | ||
| 143 | #define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_0) | ||
| 144 | #define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_0) | ||
| 145 | #define MX28_PAD_ENET0_TXD0__ENET0_TXD0 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_0) | ||
| 146 | #define MX28_PAD_ENET0_TXD1__ENET0_TXD1 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_0) | ||
| 147 | #define MX28_PAD_ENET0_RXD2__ENET0_RXD2 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_0) | ||
| 148 | #define MX28_PAD_ENET0_RXD3__ENET0_RXD3 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_0) | ||
| 149 | #define MX28_PAD_ENET0_TXD2__ENET0_TXD2 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_0) | ||
| 150 | #define MX28_PAD_ENET0_TXD3__ENET0_TXD3 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_0) | ||
| 151 | #define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_0) | ||
| 152 | #define MX28_PAD_ENET0_COL__ENET0_COL MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_0) | ||
| 153 | #define MX28_PAD_ENET0_CRS__ENET0_CRS MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_0) | ||
| 154 | #define MX28_PAD_ENET_CLK__CLKCTRL_ENET MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_0) | ||
| 155 | #define MX28_PAD_JTAG_RTCK__JTAG_RTCK MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_0) | ||
| 156 | |||
| 157 | #define MX28_PAD_EMI_D00__EMI_DATA0 MXS_IOMUX_PAD_NAKED(5, 0, PAD_MUXSEL_0) | ||
| 158 | #define MX28_PAD_EMI_D01__EMI_DATA1 MXS_IOMUX_PAD_NAKED(5, 1, PAD_MUXSEL_0) | ||
| 159 | #define MX28_PAD_EMI_D02__EMI_DATA2 MXS_IOMUX_PAD_NAKED(5, 2, PAD_MUXSEL_0) | ||
| 160 | #define MX28_PAD_EMI_D03__EMI_DATA3 MXS_IOMUX_PAD_NAKED(5, 3, PAD_MUXSEL_0) | ||
| 161 | #define MX28_PAD_EMI_D04__EMI_DATA4 MXS_IOMUX_PAD_NAKED(5, 4, PAD_MUXSEL_0) | ||
| 162 | #define MX28_PAD_EMI_D05__EMI_DATA5 MXS_IOMUX_PAD_NAKED(5, 5, PAD_MUXSEL_0) | ||
| 163 | #define MX28_PAD_EMI_D06__EMI_DATA6 MXS_IOMUX_PAD_NAKED(5, 6, PAD_MUXSEL_0) | ||
| 164 | #define MX28_PAD_EMI_D07__EMI_DATA7 MXS_IOMUX_PAD_NAKED(5, 7, PAD_MUXSEL_0) | ||
| 165 | #define MX28_PAD_EMI_D08__EMI_DATA8 MXS_IOMUX_PAD_NAKED(5, 8, PAD_MUXSEL_0) | ||
| 166 | #define MX28_PAD_EMI_D09__EMI_DATA9 MXS_IOMUX_PAD_NAKED(5, 9, PAD_MUXSEL_0) | ||
| 167 | #define MX28_PAD_EMI_D10__EMI_DATA10 MXS_IOMUX_PAD_NAKED(5, 10, PAD_MUXSEL_0) | ||
| 168 | #define MX28_PAD_EMI_D11__EMI_DATA11 MXS_IOMUX_PAD_NAKED(5, 11, PAD_MUXSEL_0) | ||
| 169 | #define MX28_PAD_EMI_D12__EMI_DATA12 MXS_IOMUX_PAD_NAKED(5, 12, PAD_MUXSEL_0) | ||
| 170 | #define MX28_PAD_EMI_D13__EMI_DATA13 MXS_IOMUX_PAD_NAKED(5, 13, PAD_MUXSEL_0) | ||
| 171 | #define MX28_PAD_EMI_D14__EMI_DATA14 MXS_IOMUX_PAD_NAKED(5, 14, PAD_MUXSEL_0) | ||
| 172 | #define MX28_PAD_EMI_D15__EMI_DATA15 MXS_IOMUX_PAD_NAKED(5, 15, PAD_MUXSEL_0) | ||
| 173 | #define MX28_PAD_EMI_ODT0__EMI_ODT0 MXS_IOMUX_PAD_NAKED(5, 16, PAD_MUXSEL_0) | ||
| 174 | #define MX28_PAD_EMI_DQM0__EMI_DQM0 MXS_IOMUX_PAD_NAKED(5, 17, PAD_MUXSEL_0) | ||
| 175 | #define MX28_PAD_EMI_ODT1__EMI_ODT1 MXS_IOMUX_PAD_NAKED(5, 18, PAD_MUXSEL_0) | ||
| 176 | #define MX28_PAD_EMI_DQM1__EMI_DQM1 MXS_IOMUX_PAD_NAKED(5, 19, PAD_MUXSEL_0) | ||
| 177 | #define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK MXS_IOMUX_PAD_NAKED(5, 20, PAD_MUXSEL_0) | ||
| 178 | #define MX28_PAD_EMI_CLK__EMI_CLK MXS_IOMUX_PAD_NAKED(5, 21, PAD_MUXSEL_0) | ||
| 179 | #define MX28_PAD_EMI_DQS0__EMI_DQS0 MXS_IOMUX_PAD_NAKED(5, 22, PAD_MUXSEL_0) | ||
| 180 | #define MX28_PAD_EMI_DQS1__EMI_DQS1 MXS_IOMUX_PAD_NAKED(5, 23, PAD_MUXSEL_0) | ||
| 181 | #define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN MXS_IOMUX_PAD_NAKED(5, 26, PAD_MUXSEL_0) | ||
| 182 | |||
| 183 | #define MX28_PAD_EMI_A00__EMI_ADDR0 MXS_IOMUX_PAD_NAKED(6, 0, PAD_MUXSEL_0) | ||
| 184 | #define MX28_PAD_EMI_A01__EMI_ADDR1 MXS_IOMUX_PAD_NAKED(6, 1, PAD_MUXSEL_0) | ||
| 185 | #define MX28_PAD_EMI_A02__EMI_ADDR2 MXS_IOMUX_PAD_NAKED(6, 2, PAD_MUXSEL_0) | ||
| 186 | #define MX28_PAD_EMI_A03__EMI_ADDR3 MXS_IOMUX_PAD_NAKED(6, 3, PAD_MUXSEL_0) | ||
| 187 | #define MX28_PAD_EMI_A04__EMI_ADDR4 MXS_IOMUX_PAD_NAKED(6, 4, PAD_MUXSEL_0) | ||
| 188 | #define MX28_PAD_EMI_A05__EMI_ADDR5 MXS_IOMUX_PAD_NAKED(6, 5, PAD_MUXSEL_0) | ||
| 189 | #define MX28_PAD_EMI_A06__EMI_ADDR6 MXS_IOMUX_PAD_NAKED(6, 6, PAD_MUXSEL_0) | ||
| 190 | #define MX28_PAD_EMI_A07__EMI_ADDR7 MXS_IOMUX_PAD_NAKED(6, 7, PAD_MUXSEL_0) | ||
| 191 | #define MX28_PAD_EMI_A08__EMI_ADDR8 MXS_IOMUX_PAD_NAKED(6, 8, PAD_MUXSEL_0) | ||
| 192 | #define MX28_PAD_EMI_A09__EMI_ADDR9 MXS_IOMUX_PAD_NAKED(6, 9, PAD_MUXSEL_0) | ||
| 193 | #define MX28_PAD_EMI_A10__EMI_ADDR10 MXS_IOMUX_PAD_NAKED(6, 10, PAD_MUXSEL_0) | ||
| 194 | #define MX28_PAD_EMI_A11__EMI_ADDR11 MXS_IOMUX_PAD_NAKED(6, 11, PAD_MUXSEL_0) | ||
| 195 | #define MX28_PAD_EMI_A12__EMI_ADDR12 MXS_IOMUX_PAD_NAKED(6, 12, PAD_MUXSEL_0) | ||
| 196 | #define MX28_PAD_EMI_A13__EMI_ADDR13 MXS_IOMUX_PAD_NAKED(6, 13, PAD_MUXSEL_0) | ||
| 197 | #define MX28_PAD_EMI_A14__EMI_ADDR14 MXS_IOMUX_PAD_NAKED(6, 14, PAD_MUXSEL_0) | ||
| 198 | #define MX28_PAD_EMI_BA0__EMI_BA0 MXS_IOMUX_PAD_NAKED(6, 16, PAD_MUXSEL_0) | ||
| 199 | #define MX28_PAD_EMI_BA1__EMI_BA1 MXS_IOMUX_PAD_NAKED(6, 17, PAD_MUXSEL_0) | ||
| 200 | #define MX28_PAD_EMI_BA2__EMI_BA2 MXS_IOMUX_PAD_NAKED(6, 18, PAD_MUXSEL_0) | ||
| 201 | #define MX28_PAD_EMI_CASN__EMI_CASN MXS_IOMUX_PAD_NAKED(6, 19, PAD_MUXSEL_0) | ||
| 202 | #define MX28_PAD_EMI_RASN__EMI_RASN MXS_IOMUX_PAD_NAKED(6, 20, PAD_MUXSEL_0) | ||
| 203 | #define MX28_PAD_EMI_WEN__EMI_WEN MXS_IOMUX_PAD_NAKED(6, 21, PAD_MUXSEL_0) | ||
| 204 | #define MX28_PAD_EMI_CE0N__EMI_CE0N MXS_IOMUX_PAD_NAKED(6, 22, PAD_MUXSEL_0) | ||
| 205 | #define MX28_PAD_EMI_CE1N__EMI_CE1N MXS_IOMUX_PAD_NAKED(6, 23, PAD_MUXSEL_0) | ||
| 206 | #define MX28_PAD_EMI_CKE__EMI_CKE MXS_IOMUX_PAD_NAKED(6, 24, PAD_MUXSEL_0) | ||
| 207 | |||
| 208 | /* MUXSEL_1 */ | ||
| 209 | #define MX28_PAD_GPMI_D00__SSP1_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_1) | ||
| 210 | #define MX28_PAD_GPMI_D01__SSP1_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_1) | ||
| 211 | #define MX28_PAD_GPMI_D02__SSP1_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_1) | ||
| 212 | #define MX28_PAD_GPMI_D03__SSP1_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_1) | ||
| 213 | #define MX28_PAD_GPMI_D04__SSP1_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_1) | ||
| 214 | #define MX28_PAD_GPMI_D05__SSP1_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_1) | ||
| 215 | #define MX28_PAD_GPMI_D06__SSP1_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_1) | ||
| 216 | #define MX28_PAD_GPMI_D07__SSP1_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1) | ||
| 217 | #define MX28_PAD_GPMI_CE0N__SSP3_D0 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1) | ||
| 218 | #define MX28_PAD_GPMI_CE1N__SSP3_D3 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1) | ||
| 219 | #define MX28_PAD_GPMI_CE2N__CAN1_TX MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1) | ||
| 220 | #define MX28_PAD_GPMI_CE3N__CAN1_RX MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_1) | ||
| 221 | #define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_1) | ||
| 222 | #define MX28_PAD_GPMI_RDY1__SSP1_CMD MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_1) | ||
| 223 | #define MX28_PAD_GPMI_RDY2__CAN0_TX MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_1) | ||
| 224 | #define MX28_PAD_GPMI_RDY3__CAN0_RX MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_1) | ||
| 225 | #define MX28_PAD_GPMI_RDN__SSP3_SCK MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_1) | ||
| 226 | #define MX28_PAD_GPMI_WRN__SSP1_SCK MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_1) | ||
| 227 | #define MX28_PAD_GPMI_ALE__SSP3_D1 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_1) | ||
| 228 | #define MX28_PAD_GPMI_CLE__SSP3_D2 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1) | ||
| 229 | #define MX28_PAD_GPMI_RESETN__SSP3_CMD MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1) | ||
| 230 | |||
| 231 | #define MX28_PAD_LCD_D03__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_1) | ||
| 232 | #define MX28_PAD_LCD_D04__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_1) | ||
| 233 | #define MX28_PAD_LCD_D08__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_1) | ||
| 234 | #define MX28_PAD_LCD_D09__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_1) | ||
| 235 | #define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_1) | ||
| 236 | #define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_1) | ||
| 237 | #define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1) | ||
| 238 | #define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1) | ||
| 239 | #define MX28_PAD_LCD_RD_E__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1) | ||
| 240 | #define MX28_PAD_LCD_WR_RWN__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1) | ||
| 241 | #define MX28_PAD_LCD_RS__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1) | ||
| 242 | #define MX28_PAD_LCD_CS__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1) | ||
| 243 | #define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1) | ||
| 244 | #define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1) | ||
| 245 | #define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1) | ||
| 246 | |||
| 247 | #define MX28_PAD_SSP0_DATA4__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_1) | ||
| 248 | #define MX28_PAD_SSP0_DATA5__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_1) | ||
| 249 | #define MX28_PAD_SSP0_DATA6__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_1) | ||
| 250 | #define MX28_PAD_SSP0_DATA7__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1) | ||
| 251 | #define MX28_PAD_SSP1_SCK__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_1) | ||
| 252 | #define MX28_PAD_SSP1_CMD__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_1) | ||
| 253 | #define MX28_PAD_SSP1_DATA0__SSP2_D6 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_1) | ||
| 254 | #define MX28_PAD_SSP1_DATA3__SSP2_D7 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_1) | ||
| 255 | #define MX28_PAD_SSP2_SCK__AUART2_RX MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_1) | ||
| 256 | #define MX28_PAD_SSP2_MOSI__AUART2_TX MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_1) | ||
| 257 | #define MX28_PAD_SSP2_MISO__AUART3_RX MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_1) | ||
| 258 | #define MX28_PAD_SSP2_SS0__AUART3_TX MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_1) | ||
| 259 | #define MX28_PAD_SSP2_SS1__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_1) | ||
| 260 | #define MX28_PAD_SSP2_SS2__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_1) | ||
| 261 | #define MX28_PAD_SSP3_SCK__AUART4_TX MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_1) | ||
| 262 | #define MX28_PAD_SSP3_MOSI__AUART4_RX MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_1) | ||
| 263 | #define MX28_PAD_SSP3_MISO__AUART4_RTS MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_1) | ||
| 264 | #define MX28_PAD_SSP3_SS0__AUART4_CTS MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_1) | ||
| 265 | |||
| 266 | #define MX28_PAD_AUART0_RX__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_1) | ||
| 267 | #define MX28_PAD_AUART0_TX__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_1) | ||
| 268 | #define MX28_PAD_AUART0_CTS__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_1) | ||
| 269 | #define MX28_PAD_AUART0_RTS__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_1) | ||
| 270 | #define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_1) | ||
| 271 | #define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_1) | ||
| 272 | #define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_1) | ||
| 273 | #define MX28_PAD_AUART1_RTS__USB0_ID MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_1) | ||
| 274 | #define MX28_PAD_AUART2_RX__SSP3_D1 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_1) | ||
| 275 | #define MX28_PAD_AUART2_TX__SSP3_D2 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_1) | ||
| 276 | #define MX28_PAD_AUART2_CTS__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_1) | ||
| 277 | #define MX28_PAD_AUART2_RTS__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_1) | ||
| 278 | #define MX28_PAD_AUART3_RX__CAN0_TX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_1) | ||
| 279 | #define MX28_PAD_AUART3_TX__CAN0_RX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_1) | ||
| 280 | #define MX28_PAD_AUART3_CTS__CAN1_TX MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_1) | ||
| 281 | #define MX28_PAD_AUART3_RTS__CAN1_RX MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_1) | ||
| 282 | #define MX28_PAD_PWM0__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_1) | ||
| 283 | #define MX28_PAD_PWM1__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_1) | ||
| 284 | #define MX28_PAD_PWM2__USB0_ID MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_1) | ||
| 285 | #define MX28_PAD_SAIF0_MCLK__PWM_3 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_1) | ||
| 286 | #define MX28_PAD_SAIF0_LRCLK__PWM_4 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_1) | ||
| 287 | #define MX28_PAD_SAIF0_BITCLK__PWM_5 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_1) | ||
| 288 | #define MX28_PAD_SAIF0_SDATA0__PWM_6 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_1) | ||
| 289 | #define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_1) | ||
| 290 | #define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_1) | ||
| 291 | #define MX28_PAD_SAIF1_SDATA0__PWM_7 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_1) | ||
| 292 | #define MX28_PAD_LCD_RESET__LCD_VSYNC MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_1) | ||
| 293 | |||
| 294 | #define MX28_PAD_ENET0_MDC__GPMI_CE4N MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_1) | ||
| 295 | #define MX28_PAD_ENET0_MDIO__GPMI_CE5N MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_1) | ||
| 296 | #define MX28_PAD_ENET0_RX_EN__GPMI_CE6N MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_1) | ||
| 297 | #define MX28_PAD_ENET0_RXD0__GPMI_CE7N MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_1) | ||
| 298 | #define MX28_PAD_ENET0_RXD1__GPMI_READY4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_1) | ||
| 299 | #define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_1) | ||
| 300 | #define MX28_PAD_ENET0_TX_EN__GPMI_READY5 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_1) | ||
| 301 | #define MX28_PAD_ENET0_TXD0__GPMI_READY6 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_1) | ||
| 302 | #define MX28_PAD_ENET0_TXD1__GPMI_READY7 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_1) | ||
| 303 | #define MX28_PAD_ENET0_RXD2__ENET1_RXD0 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_1) | ||
| 304 | #define MX28_PAD_ENET0_RXD3__ENET1_RXD1 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_1) | ||
| 305 | #define MX28_PAD_ENET0_TXD2__ENET1_TXD0 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_1) | ||
| 306 | #define MX28_PAD_ENET0_TXD3__ENET1_TXD1 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_1) | ||
| 307 | #define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_1) | ||
| 308 | #define MX28_PAD_ENET0_COL__ENET1_TX_EN MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_1) | ||
| 309 | #define MX28_PAD_ENET0_CRS__ENET1_RX_EN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_1) | ||
| 310 | |||
| 311 | /* MUXSEL_2 */ | ||
| 312 | #define MX28_PAD_GPMI_CE2N__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_2) | ||
| 313 | #define MX28_PAD_GPMI_CE3N__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2) | ||
| 314 | #define MX28_PAD_GPMI_RDY0__USB0_ID MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2) | ||
| 315 | #define MX28_PAD_GPMI_RDY2__ENET0_TX_ER MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_2) | ||
| 316 | #define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_2) | ||
| 317 | #define MX28_PAD_GPMI_ALE__SSP3_D4 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2) | ||
| 318 | #define MX28_PAD_GPMI_CLE__SSP3_D5 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2) | ||
| 319 | |||
| 320 | #define MX28_PAD_LCD_D00__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_2) | ||
| 321 | #define MX28_PAD_LCD_D01__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_2) | ||
| 322 | #define MX28_PAD_LCD_D02__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_2) | ||
| 323 | #define MX28_PAD_LCD_D03__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_2) | ||
| 324 | #define MX28_PAD_LCD_D04__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_2) | ||
| 325 | #define MX28_PAD_LCD_D05__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_2) | ||
| 326 | #define MX28_PAD_LCD_D06__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_2) | ||
| 327 | #define MX28_PAD_LCD_D07__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_2) | ||
| 328 | #define MX28_PAD_LCD_D08__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_2) | ||
| 329 | #define MX28_PAD_LCD_D09__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_2) | ||
| 330 | #define MX28_PAD_LCD_D10__ETM_DA10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2) | ||
| 331 | #define MX28_PAD_LCD_D11__ETM_DA11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2) | ||
| 332 | #define MX28_PAD_LCD_D12__ETM_DA12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2) | ||
| 333 | #define MX28_PAD_LCD_D13__ETM_DA13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2) | ||
| 334 | #define MX28_PAD_LCD_D14__ETM_DA14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2) | ||
| 335 | #define MX28_PAD_LCD_D15__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2) | ||
| 336 | #define MX28_PAD_LCD_D16__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2) | ||
| 337 | #define MX28_PAD_LCD_D17__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_2) | ||
| 338 | #define MX28_PAD_LCD_D18__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2) | ||
| 339 | #define MX28_PAD_LCD_D19__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_2) | ||
| 340 | #define MX28_PAD_LCD_D20__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_2) | ||
| 341 | #define MX28_PAD_LCD_D21__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_2) | ||
| 342 | #define MX28_PAD_LCD_D22__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_2) | ||
| 343 | #define MX28_PAD_LCD_D23__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_2) | ||
| 344 | #define MX28_PAD_LCD_RD_E__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_2) | ||
| 345 | #define MX28_PAD_LCD_WR_RWN__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_2) | ||
| 346 | #define MX28_PAD_LCD_HSYNC__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2) | ||
| 347 | #define MX28_PAD_LCD_DOTCLK__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2) | ||
| 348 | |||
| 349 | #define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_2) | ||
| 350 | #define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_2) | ||
| 351 | #define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_2) | ||
| 352 | #define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_2) | ||
| 353 | #define MX28_PAD_SSP2_SCK__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_2) | ||
| 354 | #define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_2) | ||
| 355 | #define MX28_PAD_SSP2_MISO__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_2) | ||
| 356 | #define MX28_PAD_SSP2_SS0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_2) | ||
| 357 | #define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_2) | ||
| 358 | #define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_2) | ||
| 359 | #define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_2) | ||
| 360 | #define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_2) | ||
| 361 | #define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_2) | ||
| 362 | #define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_2) | ||
| 363 | |||
| 364 | #define MX28_PAD_AUART0_RX__DUART_CTS MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_2) | ||
| 365 | #define MX28_PAD_AUART0_TX__DUART_RTS MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_2) | ||
| 366 | #define MX28_PAD_AUART0_CTS__DUART_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_2) | ||
| 367 | #define MX28_PAD_AUART0_RTS__DUART_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_2) | ||
| 368 | #define MX28_PAD_AUART1_RX__PWM_0 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_2) | ||
| 369 | #define MX28_PAD_AUART1_TX__PWM_1 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_2) | ||
| 370 | #define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_2) | ||
| 371 | #define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_2) | ||
| 372 | #define MX28_PAD_AUART2_RX__SSP3_D4 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_2) | ||
| 373 | #define MX28_PAD_AUART2_TX__SSP3_D5 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_2) | ||
| 374 | #define MX28_PAD_AUART2_CTS__SAIF1_BITCLK MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_2) | ||
| 375 | #define MX28_PAD_AUART2_RTS__SAIF1_LRCLK MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_2) | ||
| 376 | #define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_2) | ||
| 377 | #define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_2) | ||
| 378 | #define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_2) | ||
| 379 | #define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_2) | ||
| 380 | #define MX28_PAD_PWM0__DUART_RX MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_2) | ||
| 381 | #define MX28_PAD_PWM1__DUART_TX MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_2) | ||
| 382 | #define MX28_PAD_PWM2__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_2) | ||
| 383 | #define MX28_PAD_SAIF0_MCLK__AUART4_CTS MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_2) | ||
| 384 | #define MX28_PAD_SAIF0_LRCLK__AUART4_RTS MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_2) | ||
| 385 | #define MX28_PAD_SAIF0_BITCLK__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_2) | ||
| 386 | #define MX28_PAD_SAIF0_SDATA0__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_2) | ||
| 387 | #define MX28_PAD_I2C0_SCL__DUART_RX MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_2) | ||
| 388 | #define MX28_PAD_I2C0_SDA__DUART_TX MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_2) | ||
| 389 | #define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_2) | ||
| 390 | #define MX28_PAD_SPDIF__ENET1_RX_ER MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_2) | ||
| 391 | |||
| 392 | #define MX28_PAD_ENET0_MDC__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_2) | ||
| 393 | #define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_2) | ||
| 394 | #define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_2) | ||
| 395 | #define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_2) | ||
| 396 | #define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_2) | ||
| 397 | #define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_2) | ||
| 398 | #define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_2) | ||
| 399 | #define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_2) | ||
| 400 | #define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_2) | ||
| 401 | #define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_2) | ||
| 402 | #define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_2) | ||
| 403 | #define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_2) | ||
| 404 | |||
| 405 | /* MUXSEL_GPIO */ | ||
| 406 | #define MX28_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO) | ||
| 407 | #define MX28_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO) | ||
| 408 | #define MX28_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO) | ||
| 409 | #define MX28_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO) | ||
| 410 | #define MX28_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO) | ||
| 411 | #define MX28_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO) | ||
| 412 | #define MX28_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO) | ||
| 413 | #define MX28_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO) | ||
| 414 | #define MX28_PAD_GPMI_CE0N__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO) | ||
| 415 | #define MX28_PAD_GPMI_CE1N__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO) | ||
| 416 | #define MX28_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO) | ||
| 417 | #define MX28_PAD_GPMI_CE3N__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO) | ||
| 418 | #define MX28_PAD_GPMI_RDY0__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO) | ||
| 419 | #define MX28_PAD_GPMI_RDY1__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO) | ||
| 420 | #define MX28_PAD_GPMI_RDY2__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO) | ||
| 421 | #define MX28_PAD_GPMI_RDY3__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO) | ||
| 422 | #define MX28_PAD_GPMI_RDN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO) | ||
| 423 | #define MX28_PAD_GPMI_WRN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO) | ||
| 424 | #define MX28_PAD_GPMI_ALE__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO) | ||
| 425 | #define MX28_PAD_GPMI_CLE__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO) | ||
| 426 | #define MX28_PAD_GPMI_RESETN__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO) | ||
| 427 | |||
| 428 | #define MX28_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO) | ||
| 429 | #define MX28_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO) | ||
| 430 | #define MX28_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO) | ||
| 431 | #define MX28_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO) | ||
| 432 | #define MX28_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO) | ||
| 433 | #define MX28_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO) | ||
| 434 | #define MX28_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO) | ||
| 435 | #define MX28_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO) | ||
| 436 | #define MX28_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO) | ||
| 437 | #define MX28_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO) | ||
| 438 | #define MX28_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO) | ||
| 439 | #define MX28_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO) | ||
| 440 | #define MX28_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO) | ||
| 441 | #define MX28_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO) | ||
| 442 | #define MX28_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO) | ||
| 443 | #define MX28_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO) | ||
| 444 | #define MX28_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO) | ||
| 445 | #define MX28_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO) | ||
| 446 | #define MX28_PAD_LCD_D18__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO) | ||
| 447 | #define MX28_PAD_LCD_D19__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO) | ||
| 448 | #define MX28_PAD_LCD_D20__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO) | ||
| 449 | #define MX28_PAD_LCD_D21__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO) | ||
| 450 | #define MX28_PAD_LCD_D22__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO) | ||
| 451 | #define MX28_PAD_LCD_D23__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO) | ||
| 452 | #define MX28_PAD_LCD_RD_E__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO) | ||
| 453 | #define MX28_PAD_LCD_WR_RWN__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO) | ||
| 454 | #define MX28_PAD_LCD_RS__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO) | ||
| 455 | #define MX28_PAD_LCD_CS__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO) | ||
| 456 | #define MX28_PAD_LCD_VSYNC__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO) | ||
| 457 | #define MX28_PAD_LCD_HSYNC__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO) | ||
| 458 | #define MX28_PAD_LCD_DOTCLK__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO) | ||
| 459 | #define MX28_PAD_LCD_ENABLE__GPIO_1_31 MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_GPIO) | ||
| 460 | |||
| 461 | #define MX28_PAD_SSP0_DATA0__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO) | ||
| 462 | #define MX28_PAD_SSP0_DATA1__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO) | ||
| 463 | #define MX28_PAD_SSP0_DATA2__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO) | ||
| 464 | #define MX28_PAD_SSP0_DATA3__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO) | ||
| 465 | #define MX28_PAD_SSP0_DATA4__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO) | ||
| 466 | #define MX28_PAD_SSP0_DATA5__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO) | ||
| 467 | #define MX28_PAD_SSP0_DATA6__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO) | ||
| 468 | #define MX28_PAD_SSP0_DATA7__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO) | ||
| 469 | #define MX28_PAD_SSP0_CMD__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO) | ||
| 470 | #define MX28_PAD_SSP0_DETECT__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO) | ||
| 471 | #define MX28_PAD_SSP0_SCK__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO) | ||
| 472 | #define MX28_PAD_SSP1_SCK__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO) | ||
| 473 | #define MX28_PAD_SSP1_CMD__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO) | ||
| 474 | #define MX28_PAD_SSP1_DATA0__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO) | ||
| 475 | #define MX28_PAD_SSP1_DATA3__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO) | ||
| 476 | #define MX28_PAD_SSP2_SCK__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO) | ||
| 477 | #define MX28_PAD_SSP2_MOSI__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO) | ||
| 478 | #define MX28_PAD_SSP2_MISO__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO) | ||
| 479 | #define MX28_PAD_SSP2_SS0__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO) | ||
| 480 | #define MX28_PAD_SSP2_SS1__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO) | ||
| 481 | #define MX28_PAD_SSP2_SS2__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO) | ||
| 482 | #define MX28_PAD_SSP3_SCK__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO) | ||
| 483 | #define MX28_PAD_SSP3_MOSI__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO) | ||
| 484 | #define MX28_PAD_SSP3_MISO__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO) | ||
| 485 | #define MX28_PAD_SSP3_SS0__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO) | ||
| 486 | |||
| 487 | #define MX28_PAD_AUART0_RX__GPIO_3_0 MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_GPIO) | ||
| 488 | #define MX28_PAD_AUART0_TX__GPIO_3_1 MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_GPIO) | ||
| 489 | #define MX28_PAD_AUART0_CTS__GPIO_3_2 MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_GPIO) | ||
| 490 | #define MX28_PAD_AUART0_RTS__GPIO_3_3 MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_GPIO) | ||
| 491 | #define MX28_PAD_AUART1_RX__GPIO_3_4 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_GPIO) | ||
| 492 | #define MX28_PAD_AUART1_TX__GPIO_3_5 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_GPIO) | ||
| 493 | #define MX28_PAD_AUART1_CTS__GPIO_3_6 MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_GPIO) | ||
| 494 | #define MX28_PAD_AUART1_RTS__GPIO_3_7 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_GPIO) | ||
| 495 | #define MX28_PAD_AUART2_RX__GPIO_3_8 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_GPIO) | ||
| 496 | #define MX28_PAD_AUART2_TX__GPIO_3_9 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_GPIO) | ||
| 497 | #define MX28_PAD_AUART2_CTS__GPIO_3_10 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_GPIO) | ||
| 498 | #define MX28_PAD_AUART2_RTS__GPIO_3_11 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_GPIO) | ||
| 499 | #define MX28_PAD_AUART3_RX__GPIO_3_12 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_GPIO) | ||
| 500 | #define MX28_PAD_AUART3_TX__GPIO_3_13 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_GPIO) | ||
| 501 | #define MX28_PAD_AUART3_CTS__GPIO_3_14 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_GPIO) | ||
| 502 | #define MX28_PAD_AUART3_RTS__GPIO_3_15 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_GPIO) | ||
| 503 | #define MX28_PAD_PWM0__GPIO_3_16 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_GPIO) | ||
| 504 | #define MX28_PAD_PWM1__GPIO_3_17 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_GPIO) | ||
| 505 | #define MX28_PAD_PWM2__GPIO_3_18 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_GPIO) | ||
| 506 | #define MX28_PAD_SAIF0_MCLK__GPIO_3_20 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_GPIO) | ||
| 507 | #define MX28_PAD_SAIF0_LRCLK__GPIO_3_21 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_GPIO) | ||
| 508 | #define MX28_PAD_SAIF0_BITCLK__GPIO_3_22 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_GPIO) | ||
| 509 | #define MX28_PAD_SAIF0_SDATA0__GPIO_3_23 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_GPIO) | ||
| 510 | #define MX28_PAD_I2C0_SCL__GPIO_3_24 MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_GPIO) | ||
| 511 | #define MX28_PAD_I2C0_SDA__GPIO_3_25 MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_GPIO) | ||
| 512 | #define MX28_PAD_SAIF1_SDATA0__GPIO_3_26 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_GPIO) | ||
| 513 | #define MX28_PAD_SPDIF__GPIO_3_27 MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_GPIO) | ||
| 514 | #define MX28_PAD_PWM3__GPIO_3_28 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_GPIO) | ||
| 515 | #define MX28_PAD_PWM4__GPIO_3_29 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_GPIO) | ||
| 516 | #define MX28_PAD_LCD_RESET__GPIO_3_30 MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_GPIO) | ||
| 517 | |||
| 518 | #define MX28_PAD_ENET0_MDC__GPIO_4_0 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_GPIO) | ||
| 519 | #define MX28_PAD_ENET0_MDIO__GPIO_4_1 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_GPIO) | ||
| 520 | #define MX28_PAD_ENET0_RX_EN__GPIO_4_2 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_GPIO) | ||
| 521 | #define MX28_PAD_ENET0_RXD0__GPIO_4_3 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_GPIO) | ||
| 522 | #define MX28_PAD_ENET0_RXD1__GPIO_4_4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_GPIO) | ||
| 523 | #define MX28_PAD_ENET0_TX_CLK__GPIO_4_5 MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_GPIO) | ||
| 524 | #define MX28_PAD_ENET0_TX_EN__GPIO_4_6 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_GPIO) | ||
| 525 | #define MX28_PAD_ENET0_TXD0__GPIO_4_7 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_GPIO) | ||
| 526 | #define MX28_PAD_ENET0_TXD1__GPIO_4_8 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_GPIO) | ||
| 527 | #define MX28_PAD_ENET0_RXD2__GPIO_4_9 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_GPIO) | ||
| 528 | #define MX28_PAD_ENET0_RXD3__GPIO_4_10 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_GPIO) | ||
| 529 | #define MX28_PAD_ENET0_TXD2__GPIO_4_11 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_GPIO) | ||
| 530 | #define MX28_PAD_ENET0_TXD3__GPIO_4_12 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_GPIO) | ||
| 531 | #define MX28_PAD_ENET0_RX_CLK__GPIO_4_13 MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_GPIO) | ||
| 532 | #define MX28_PAD_ENET0_COL__GPIO_4_14 MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_GPIO) | ||
| 533 | #define MX28_PAD_ENET0_CRS__GPIO_4_15 MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_GPIO) | ||
| 534 | #define MX28_PAD_ENET_CLK__GPIO_4_16 MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_GPIO) | ||
| 535 | #define MX28_PAD_JTAG_RTCK__GPIO_4_20 MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_GPIO) | ||
| 536 | |||
| 537 | #endif /* __MACH_IOMUX_MX28_H__ */ | ||
diff --git a/arch/arm/mach-mxs/include/mach/iomux.h b/arch/arm/mach-mxs/include/mach/iomux.h new file mode 100644 index 000000000000..fe558e3c5a9a --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/iomux.h | |||
| @@ -0,0 +1,165 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, | ||
| 3 | * <armlinux@phytec.de> | ||
| 4 | * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License | ||
| 8 | * as published by the Free Software Foundation; either version 2 | ||
| 9 | * of the License, or (at your option) any later version. | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 18 | * MA 02110-1301, USA. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __MACH_MXS_IOMUX_H__ | ||
| 22 | #define __MACH_MXS_IOMUX_H__ | ||
| 23 | |||
| 24 | /* | ||
| 25 | * IOMUX/PAD Bit field definitions | ||
| 26 | * | ||
| 27 | * PAD_BANK: 0..2 (3) | ||
| 28 | * PAD_PIN: 3..7 (5) | ||
| 29 | * PAD_MUXSEL: 8..9 (2) | ||
| 30 | * PAD_MA: 10..11 (2) | ||
| 31 | * PAD_MA_VALID: 12 (1) | ||
| 32 | * PAD_VOL: 13 (1) | ||
| 33 | * PAD_VOL_VALID: 14 (1) | ||
| 34 | * PAD_PULL: 15 (1) | ||
| 35 | * PAD_PULL_VALID: 16 (1) | ||
| 36 | * RESERVED: 17..31 (15) | ||
| 37 | */ | ||
| 38 | typedef u32 iomux_cfg_t; | ||
| 39 | |||
| 40 | #define MXS_PAD_BANK_SHIFT 0 | ||
| 41 | #define MXS_PAD_BANK_MASK ((iomux_cfg_t)0x7 << MXS_PAD_BANK_SHIFT) | ||
| 42 | #define MXS_PAD_PIN_SHIFT 3 | ||
| 43 | #define MXS_PAD_PIN_MASK ((iomux_cfg_t)0x1f << MXS_PAD_PIN_SHIFT) | ||
| 44 | #define MXS_PAD_MUXSEL_SHIFT 8 | ||
| 45 | #define MXS_PAD_MUXSEL_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MUXSEL_SHIFT) | ||
| 46 | #define MXS_PAD_MA_SHIFT 10 | ||
| 47 | #define MXS_PAD_MA_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MA_SHIFT) | ||
| 48 | #define MXS_PAD_MA_VALID_SHIFT 12 | ||
| 49 | #define MXS_PAD_MA_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_MA_VALID_SHIFT) | ||
| 50 | #define MXS_PAD_VOL_SHIFT 13 | ||
| 51 | #define MXS_PAD_VOL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_SHIFT) | ||
| 52 | #define MXS_PAD_VOL_VALID_SHIFT 14 | ||
| 53 | #define MXS_PAD_VOL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_VALID_SHIFT) | ||
| 54 | #define MXS_PAD_PULL_SHIFT 15 | ||
| 55 | #define MXS_PAD_PULL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_SHIFT) | ||
| 56 | #define MXS_PAD_PULL_VALID_SHIFT 16 | ||
| 57 | #define MXS_PAD_PULL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_VALID_SHIFT) | ||
| 58 | |||
| 59 | #define PAD_MUXSEL_0 0 | ||
| 60 | #define PAD_MUXSEL_1 1 | ||
| 61 | #define PAD_MUXSEL_2 2 | ||
| 62 | #define PAD_MUXSEL_GPIO 3 | ||
| 63 | |||
| 64 | #define PAD_4MA 0 | ||
| 65 | #define PAD_8MA 1 | ||
| 66 | #define PAD_12MA 2 | ||
| 67 | #define PAD_16MA 3 | ||
| 68 | |||
| 69 | #define PAD_1V8 0 | ||
| 70 | #define PAD_3V3 1 | ||
| 71 | |||
| 72 | #define PAD_NOPULL 0 | ||
| 73 | #define PAD_PULLUP 1 | ||
| 74 | |||
| 75 | #define MXS_PAD_4MA ((PAD_4MA << MXS_PAD_MA_SHIFT) | \ | ||
| 76 | MXS_PAD_MA_VALID_MASK) | ||
| 77 | #define MXS_PAD_8MA ((PAD_8MA << MXS_PAD_MA_SHIFT) | \ | ||
| 78 | MXS_PAD_MA_VALID_MASK) | ||
| 79 | #define MXS_PAD_12MA ((PAD_12MA << MXS_PAD_MA_SHIFT) | \ | ||
| 80 | MXS_PAD_MA_VALID_MASK) | ||
| 81 | #define MXS_PAD_16MA ((PAD_16MA << MXS_PAD_MA_SHIFT) | \ | ||
| 82 | MXS_PAD_MA_VALID_MASK) | ||
| 83 | |||
| 84 | #define MXS_PAD_1V8 ((PAD_1V8 << MXS_PAD_VOL_SHIFT) | \ | ||
| 85 | MXS_PAD_VOL_VALID_MASK) | ||
| 86 | #define MXS_PAD_3V3 ((PAD_3V3 << MXS_PAD_VOL_SHIFT) | \ | ||
| 87 | MXS_PAD_VOL_VALID_MASK) | ||
| 88 | |||
| 89 | #define MXS_PAD_NOPULL ((PAD_NOPULL << MXS_PAD_PULL_SHIFT) | \ | ||
| 90 | MXS_PAD_PULL_VALID_MASK) | ||
| 91 | #define MXS_PAD_PULLUP ((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \ | ||
| 92 | MXS_PAD_PULL_VALID_MASK) | ||
| 93 | |||
| 94 | #define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull) \ | ||
| 95 | (((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) | \ | ||
| 96 | ((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) | \ | ||
| 97 | ((iomux_cfg_t)(_muxsel) << MXS_PAD_MUXSEL_SHIFT) | \ | ||
| 98 | ((iomux_cfg_t)(_ma) << MXS_PAD_MA_SHIFT) | \ | ||
| 99 | ((iomux_cfg_t)(_vol) << MXS_PAD_VOL_SHIFT) | \ | ||
| 100 | ((iomux_cfg_t)(_pull) << MXS_PAD_PULL_SHIFT)) | ||
| 101 | |||
| 102 | /* | ||
| 103 | * A pad becomes naked, when none of mA, vol or pull | ||
| 104 | * validity bits is set. | ||
| 105 | */ | ||
| 106 | #define MXS_IOMUX_PAD_NAKED(_bank, _pin, _muxsel) \ | ||
| 107 | MXS_IOMUX_PAD(_bank, _pin, _muxsel, 0, 0, 0) | ||
| 108 | |||
| 109 | static inline unsigned int PAD_BANK(iomux_cfg_t pad) | ||
| 110 | { | ||
| 111 | return (pad & MXS_PAD_BANK_MASK) >> MXS_PAD_BANK_SHIFT; | ||
| 112 | } | ||
| 113 | |||
| 114 | static inline unsigned int PAD_PIN(iomux_cfg_t pad) | ||
| 115 | { | ||
| 116 | return (pad & MXS_PAD_PIN_MASK) >> MXS_PAD_PIN_SHIFT; | ||
| 117 | } | ||
| 118 | |||
| 119 | static inline unsigned int PAD_MUXSEL(iomux_cfg_t pad) | ||
| 120 | { | ||
| 121 | return (pad & MXS_PAD_MUXSEL_MASK) >> MXS_PAD_MUXSEL_SHIFT; | ||
| 122 | } | ||
| 123 | |||
| 124 | static inline unsigned int PAD_MA(iomux_cfg_t pad) | ||
| 125 | { | ||
| 126 | return (pad & MXS_PAD_MA_MASK) >> MXS_PAD_MA_SHIFT; | ||
| 127 | } | ||
| 128 | |||
| 129 | static inline unsigned int PAD_MA_VALID(iomux_cfg_t pad) | ||
| 130 | { | ||
| 131 | return (pad & MXS_PAD_MA_VALID_MASK) >> MXS_PAD_MA_VALID_SHIFT; | ||
| 132 | } | ||
| 133 | |||
| 134 | static inline unsigned int PAD_VOL(iomux_cfg_t pad) | ||
| 135 | { | ||
| 136 | return (pad & MXS_PAD_VOL_MASK) >> MXS_PAD_VOL_SHIFT; | ||
| 137 | } | ||
| 138 | |||
| 139 | static inline unsigned int PAD_VOL_VALID(iomux_cfg_t pad) | ||
| 140 | { | ||
| 141 | return (pad & MXS_PAD_VOL_VALID_MASK) >> MXS_PAD_VOL_VALID_SHIFT; | ||
| 142 | } | ||
| 143 | |||
| 144 | static inline unsigned int PAD_PULL(iomux_cfg_t pad) | ||
| 145 | { | ||
| 146 | return (pad & MXS_PAD_PULL_MASK) >> MXS_PAD_PULL_SHIFT; | ||
| 147 | } | ||
| 148 | |||
| 149 | static inline unsigned int PAD_PULL_VALID(iomux_cfg_t pad) | ||
| 150 | { | ||
| 151 | return (pad & MXS_PAD_PULL_VALID_MASK) >> MXS_PAD_PULL_VALID_SHIFT; | ||
| 152 | } | ||
| 153 | |||
| 154 | /* | ||
| 155 | * configures a single pad in the iomuxer | ||
| 156 | */ | ||
| 157 | int mxs_iomux_setup_pad(iomux_cfg_t pad); | ||
| 158 | |||
| 159 | /* | ||
| 160 | * configures multiple pads | ||
| 161 | * convenient way to call the above function with tables | ||
| 162 | */ | ||
| 163 | int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count); | ||
| 164 | |||
| 165 | #endif /* __MACH_MXS_IOMUX_H__*/ | ||
diff --git a/arch/arm/mach-mxs/include/mach/irqs.h b/arch/arm/mach-mxs/include/mach/irqs.h new file mode 100644 index 000000000000..f771039b814a --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/irqs.h | |||
| @@ -0,0 +1,32 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | */ | ||
| 4 | |||
| 5 | /* | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __MACH_MXS_IRQS_H__ | ||
| 12 | #define __MACH_MXS_IRQS_H__ | ||
| 13 | |||
| 14 | #define MXS_INTERNAL_IRQS 128 | ||
| 15 | |||
| 16 | #define MXS_GPIO_IRQ_START MXS_INTERNAL_IRQS | ||
| 17 | |||
| 18 | /* the maximum for MXS-based */ | ||
| 19 | #define MXS_GPIO_IRQS (32 * 5) | ||
| 20 | |||
| 21 | /* | ||
| 22 | * The next 16 interrupts are for board specific purposes. Since | ||
| 23 | * the kernel can only run on one machine at a time, we can re-use | ||
| 24 | * these. If you need more, increase MXS_BOARD_IRQS, but keep it | ||
| 25 | * within sensible limits. | ||
| 26 | */ | ||
| 27 | #define MXS_BOARD_IRQ_START (MXS_GPIO_IRQ_START + MXS_GPIO_IRQS) | ||
| 28 | #define MXS_BOARD_IRQS 16 | ||
| 29 | |||
| 30 | #define NR_IRQS (MXS_BOARD_IRQ_START + MXS_BOARD_IRQS) | ||
| 31 | |||
| 32 | #endif /* __MACH_MXS_IRQS_H__ */ | ||
diff --git a/arch/arm/mach-mxs/include/mach/memory.h b/arch/arm/mach-mxs/include/mach/memory.h new file mode 100644 index 000000000000..b5420a5c2d4b --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/memory.h | |||
| @@ -0,0 +1,24 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License along | ||
| 15 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef __MACH_MXS_MEMORY_H__ | ||
| 20 | #define __MACH_MXS_MEMORY_H__ | ||
| 21 | |||
| 22 | #define PHYS_OFFSET UL(0x40000000) | ||
| 23 | |||
| 24 | #endif /* __MACH_MXS_MEMORY_H__ */ | ||
diff --git a/arch/arm/mach-mxs/include/mach/mx23.h b/arch/arm/mach-mxs/include/mach/mx23.h new file mode 100644 index 000000000000..9edd02ec8e30 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/mx23.h | |||
| @@ -0,0 +1,145 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License along | ||
| 15 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef __MACH_MX23_H__ | ||
| 20 | #define __MACH_MX23_H__ | ||
| 21 | |||
| 22 | #include <mach/mxs.h> | ||
| 23 | |||
| 24 | /* | ||
| 25 | * OCRAM | ||
| 26 | */ | ||
| 27 | #define MX23_OCRAM_BASE_ADDR 0x00000000 | ||
| 28 | #define MX23_OCRAM_SIZE SZ_32K | ||
| 29 | |||
| 30 | /* | ||
| 31 | * IO | ||
| 32 | */ | ||
| 33 | #define MX23_IO_BASE_ADDR 0x80000000 | ||
| 34 | #define MX23_IO_SIZE SZ_1M | ||
| 35 | |||
| 36 | #define MX23_ICOLL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x000000) | ||
| 37 | #define MX23_APBH_DMA_BASE_ADDR (MX23_IO_BASE_ADDR + 0x004000) | ||
| 38 | #define MX23_BCH_BASE_ADDR (MX23_IO_BASE_ADDR + 0x00a000) | ||
| 39 | #define MX23_GPMI_BASE_ADDR (MX23_IO_BASE_ADDR + 0x00c000) | ||
| 40 | #define MX23_SSP1_BASE_ADDR (MX23_IO_BASE_ADDR + 0x010000) | ||
| 41 | #define MX23_PINCTRL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x018000) | ||
| 42 | #define MX23_DIGCTL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x01c000) | ||
| 43 | #define MX23_ETM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x020000) | ||
| 44 | #define MX23_APBX_DMA_BASE_ADDR (MX23_IO_BASE_ADDR + 0x024000) | ||
| 45 | #define MX23_DCP_BASE_ADDR (MX23_IO_BASE_ADDR + 0x028000) | ||
| 46 | #define MX23_PXP_BASE_ADDR (MX23_IO_BASE_ADDR + 0x02a000) | ||
| 47 | #define MX23_OCOTP_BASE_ADDR (MX23_IO_BASE_ADDR + 0x02c000) | ||
| 48 | #define MX23_AXI_AHB0_BASE_ADDR (MX23_IO_BASE_ADDR + 0x02e000) | ||
| 49 | #define MX23_LCDIF_BASE_ADDR (MX23_IO_BASE_ADDR + 0x030000) | ||
| 50 | #define MX23_SSP2_BASE_ADDR (MX23_IO_BASE_ADDR + 0x034000) | ||
| 51 | #define MX23_TVENC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x038000) | ||
| 52 | #define MX23_CLKCTRL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x040000) | ||
| 53 | #define MX23_SAIF0_BASE_ADDR (MX23_IO_BASE_ADDR + 0x042000) | ||
| 54 | #define MX23_POWER_BASE_ADDR (MX23_IO_BASE_ADDR + 0x044000) | ||
| 55 | #define MX23_SAIF1_BASE_ADDR (MX23_IO_BASE_ADDR + 0x046000) | ||
| 56 | #define MX23_AUDIOOUT_BASE_ADDR (MX23_IO_BASE_ADDR + 0x048000) | ||
| 57 | #define MX23_AUDIOIN_BASE_ADDR (MX23_IO_BASE_ADDR + 0x04c000) | ||
| 58 | #define MX23_LRADC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x050000) | ||
| 59 | #define MX23_SPDIF_BASE_ADDR (MX23_IO_BASE_ADDR + 0x054000) | ||
| 60 | #define MX23_I2C0_BASE_ADDR (MX23_IO_BASE_ADDR + 0x058000) | ||
| 61 | #define MX23_RTC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x05c000) | ||
| 62 | #define MX23_PWM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x064000) | ||
| 63 | #define MX23_TIMROT_BASE_ADDR (MX23_IO_BASE_ADDR + 0x068000) | ||
| 64 | #define MX23_AUART1_BASE_ADDR (MX23_IO_BASE_ADDR + 0x06c000) | ||
| 65 | #define MX23_AUART2_BASE_ADDR (MX23_IO_BASE_ADDR + 0x06e000) | ||
| 66 | #define MX23_DUART_BASE_ADDR (MX23_IO_BASE_ADDR + 0x070000) | ||
| 67 | #define MX23_USBPHY_BASE_ADDR (MX23_IO_BASE_ADDR + 0x07c000) | ||
| 68 | #define MX23_USBCTRL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x080000) | ||
| 69 | #define MX23_DRAM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x0e0000) | ||
| 70 | |||
| 71 | #define MX23_IO_P2V(x) MXS_IO_P2V(x) | ||
| 72 | #define MX23_IO_ADDRESS(x) IOMEM(MX23_IO_P2V(x)) | ||
| 73 | |||
| 74 | /* | ||
| 75 | * IRQ | ||
| 76 | */ | ||
| 77 | #define MX23_INT_DUART 0 | ||
| 78 | #define MX23_INT_COMMS_RX 1 | ||
| 79 | #define MX23_INT_COMMS_TX 1 | ||
| 80 | #define MX23_INT_SSP2_ERROR 2 | ||
| 81 | #define MX23_INT_VDD5V 3 | ||
| 82 | #define MX23_INT_HEADPHONE_SHORT 4 | ||
| 83 | #define MX23_INT_DAC_DMA 5 | ||
| 84 | #define MX23_INT_DAC_ERROR 6 | ||
| 85 | #define MX23_INT_ADC_DMA 7 | ||
| 86 | #define MX23_INT_ADC_ERROR 8 | ||
| 87 | #define MX23_INT_SPDIF_DMA 9 | ||
| 88 | #define MX23_INT_SAIF2_DMA 9 | ||
| 89 | #define MX23_INT_SPDIF_ERROR 10 | ||
| 90 | #define MX23_INT_SAIF1_IRQ 10 | ||
| 91 | #define MX23_INT_SAIF2_IRQ 10 | ||
| 92 | #define MX23_INT_USB_CTRL 11 | ||
| 93 | #define MX23_INT_USB_WAKEUP 12 | ||
| 94 | #define MX23_INT_GPMI_DMA 13 | ||
| 95 | #define MX23_INT_SSP1_DMA 14 | ||
| 96 | #define MX23_INT_SSP_ERROR 15 | ||
| 97 | #define MX23_INT_GPIO0 16 | ||
| 98 | #define MX23_INT_GPIO1 17 | ||
| 99 | #define MX23_INT_GPIO2 18 | ||
| 100 | #define MX23_INT_SAIF1_DMA 19 | ||
| 101 | #define MX23_INT_SSP2_DMA 20 | ||
| 102 | #define MX23_INT_ECC8_IRQ 21 | ||
| 103 | #define MX23_INT_RTC_ALARM 22 | ||
| 104 | #define MX23_INT_UARTAPP_TX_DMA 23 | ||
| 105 | #define MX23_INT_UARTAPP_INTERNAL 24 | ||
| 106 | #define MX23_INT_UARTAPP_RX_DMA 25 | ||
| 107 | #define MX23_INT_I2C_DMA 26 | ||
| 108 | #define MX23_INT_I2C_ERROR 27 | ||
| 109 | #define MX23_INT_TIMER0 28 | ||
| 110 | #define MX23_INT_TIMER1 29 | ||
| 111 | #define MX23_INT_TIMER2 30 | ||
| 112 | #define MX23_INT_TIMER3 31 | ||
| 113 | #define MX23_INT_BATT_BRNOUT 32 | ||
| 114 | #define MX23_INT_VDDD_BRNOUT 33 | ||
| 115 | #define MX23_INT_VDDIO_BRNOUT 34 | ||
| 116 | #define MX23_INT_VDD18_BRNOUT 35 | ||
| 117 | #define MX23_INT_TOUCH_DETECT 36 | ||
| 118 | #define MX23_INT_LRADC_CH0 37 | ||
| 119 | #define MX23_INT_LRADC_CH1 38 | ||
| 120 | #define MX23_INT_LRADC_CH2 39 | ||
| 121 | #define MX23_INT_LRADC_CH3 40 | ||
| 122 | #define MX23_INT_LRADC_CH4 41 | ||
| 123 | #define MX23_INT_LRADC_CH5 42 | ||
| 124 | #define MX23_INT_LRADC_CH6 43 | ||
| 125 | #define MX23_INT_LRADC_CH7 44 | ||
| 126 | #define MX23_INT_LCDIF_DMA 45 | ||
| 127 | #define MX23_INT_LCDIF_ERROR 46 | ||
| 128 | #define MX23_INT_DIGCTL_DEBUG_TRAP 47 | ||
| 129 | #define MX23_INT_RTC_1MSEC 48 | ||
| 130 | #define MX23_INT_DRI_DMA 49 | ||
| 131 | #define MX23_INT_DRI_ATTENTION 50 | ||
| 132 | #define MX23_INT_GPMI_ATTENTION 51 | ||
| 133 | #define MX23_INT_IR 52 | ||
| 134 | #define MX23_INT_DCP_VMI 53 | ||
| 135 | #define MX23_INT_DCP 54 | ||
| 136 | #define MX23_INT_BCH 56 | ||
| 137 | #define MX23_INT_PXP 57 | ||
| 138 | #define MX23_INT_UARTAPP2_TX_DMA 58 | ||
| 139 | #define MX23_INT_UARTAPP2_INTERNAL 59 | ||
| 140 | #define MX23_INT_UARTAPP2_RX_DMA 60 | ||
| 141 | #define MX23_INT_VDAC_DETECT 61 | ||
| 142 | #define MX23_INT_VDD5V_DROOP 64 | ||
| 143 | #define MX23_INT_DCDC4P2_BO 65 | ||
| 144 | |||
| 145 | #endif /* __MACH_MX23_H__ */ | ||
diff --git a/arch/arm/mach-mxs/include/mach/mx28.h b/arch/arm/mach-mxs/include/mach/mx28.h new file mode 100644 index 000000000000..0716745267ad --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/mx28.h | |||
| @@ -0,0 +1,188 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License along | ||
| 15 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef __MACH_MX28_H__ | ||
| 20 | #define __MACH_MX28_H__ | ||
| 21 | |||
| 22 | #include <mach/mxs.h> | ||
| 23 | |||
| 24 | /* | ||
| 25 | * OCRAM | ||
| 26 | */ | ||
| 27 | #define MX28_OCRAM_BASE_ADDR 0x00000000 | ||
| 28 | #define MX28_OCRAM_SIZE SZ_128K | ||
| 29 | |||
| 30 | /* | ||
| 31 | * IO | ||
| 32 | */ | ||
| 33 | #define MX28_IO_BASE_ADDR 0x80000000 | ||
| 34 | #define MX28_IO_SIZE SZ_1M | ||
| 35 | |||
| 36 | #define MX28_ICOLL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x000000) | ||
| 37 | #define MX28_HSADC_BASE_ADDR (MX28_IO_BASE_ADDR + 0x002000) | ||
| 38 | #define MX28_APBH_DMA_BASE_ADDR (MX28_IO_BASE_ADDR + 0x004000) | ||
| 39 | #define MX28_PERFMON_BASE_ADDR (MX28_IO_BASE_ADDR + 0x006000) | ||
| 40 | #define MX28_BCH_BASE_ADDR (MX28_IO_BASE_ADDR + 0x00a000) | ||
| 41 | #define MX28_GPMI_BASE_ADDR (MX28_IO_BASE_ADDR + 0x00c000) | ||
| 42 | #define MX28_SSP0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x010000) | ||
| 43 | #define MX28_SSP1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x012000) | ||
| 44 | #define MX28_SSP2_BASE_ADDR (MX28_IO_BASE_ADDR + 0x014000) | ||
| 45 | #define MX28_SSP3_BASE_ADDR (MX28_IO_BASE_ADDR + 0x016000) | ||
| 46 | #define MX28_PINCTRL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x018000) | ||
| 47 | #define MX28_DIGCTL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x01c000) | ||
| 48 | #define MX28_ETM_BASE_ADDR (MX28_IO_BASE_ADDR + 0x022000) | ||
| 49 | #define MX28_APBX_DMA_BASE_ADDR (MX28_IO_BASE_ADDR + 0x024000) | ||
| 50 | #define MX28_DCP_BASE_ADDR (MX28_IO_BASE_ADDR + 0x028000) | ||
| 51 | #define MX28_PXP_BASE_ADDR (MX28_IO_BASE_ADDR + 0x02a000) | ||
| 52 | #define MX28_OCOTP_BASE_ADDR (MX28_IO_BASE_ADDR + 0x02c000) | ||
| 53 | #define MX28_AXI_AHB0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x02e000) | ||
| 54 | #define MX28_LCDIF_BASE_ADDR (MX28_IO_BASE_ADDR + 0x030000) | ||
| 55 | #define MX28_CAN0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x032000) | ||
| 56 | #define MX28_CAN1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x034000) | ||
| 57 | #define MX28_SIMDBG_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c000) | ||
| 58 | #define MX28_SIMGPMISEL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c200) | ||
| 59 | #define MX28_SIMSSPSEL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c300) | ||
| 60 | #define MX28_SIMMEMSEL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c400) | ||
| 61 | #define MX28_GPIOMON_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c500) | ||
| 62 | #define MX28_SIMENET_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c700) | ||
| 63 | #define MX28_ARMJTAG_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c800) | ||
| 64 | #define MX28_CLKCTRL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x040000) | ||
| 65 | #define MX28_SAIF0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x042000) | ||
| 66 | #define MX28_POWER_BASE_ADDR (MX28_IO_BASE_ADDR + 0x044000) | ||
| 67 | #define MX28_SAIF1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x046000) | ||
| 68 | #define MX28_LRADC_BASE_ADDR (MX28_IO_BASE_ADDR + 0x050000) | ||
| 69 | #define MX28_SPDIF_BASE_ADDR (MX28_IO_BASE_ADDR + 0x054000) | ||
| 70 | #define MX28_RTC_BASE_ADDR (MX28_IO_BASE_ADDR + 0x056000) | ||
| 71 | #define MX28_I2C0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x058000) | ||
| 72 | #define MX28_I2C1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x05a000) | ||
| 73 | #define MX28_PWM_BASE_ADDR (MX28_IO_BASE_ADDR + 0x064000) | ||
| 74 | #define MX28_TIMROT_BASE_ADDR (MX28_IO_BASE_ADDR + 0x068000) | ||
| 75 | #define MX28_AUART0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x06a000) | ||
| 76 | #define MX28_AUART1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x06c000) | ||
| 77 | #define MX28_AUART2_BASE_ADDR (MX28_IO_BASE_ADDR + 0x06e000) | ||
| 78 | #define MX28_AUART3_BASE_ADDR (MX28_IO_BASE_ADDR + 0x070000) | ||
| 79 | #define MX28_AUART4_BASE_ADDR (MX28_IO_BASE_ADDR + 0x072000) | ||
| 80 | #define MX28_DUART_BASE_ADDR (MX28_IO_BASE_ADDR + 0x074000) | ||
| 81 | #define MX28_USBPHY0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x07C000) | ||
| 82 | #define MX28_USBPHY1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x07e000) | ||
| 83 | #define MX28_USBCTRL0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x080000) | ||
| 84 | #define MX28_USBCTRL1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x090000) | ||
| 85 | #define MX28_DFLPT_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0c0000) | ||
| 86 | #define MX28_DRAM_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0e0000) | ||
| 87 | #define MX28_ENET_MAC0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0f0000) | ||
| 88 | #define MX28_ENET_MAC1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0f4000) | ||
| 89 | |||
| 90 | #define MX28_IO_P2V(x) MXS_IO_P2V(x) | ||
| 91 | #define MX28_IO_ADDRESS(x) IOMEM(MX28_IO_P2V(x)) | ||
| 92 | |||
| 93 | /* | ||
| 94 | * IRQ | ||
| 95 | */ | ||
| 96 | #define MX28_INT_BATT_BRNOUT 0 | ||
| 97 | #define MX28_INT_VDDD_BRNOUT 1 | ||
| 98 | #define MX28_INT_VDDIO_BRNOUT 2 | ||
| 99 | #define MX28_INT_VDDA_BRNOUT 3 | ||
| 100 | #define MX28_INT_VDD5V_DROOP 4 | ||
| 101 | #define MX28_INT_DCDC4P2_BRNOUT 5 | ||
| 102 | #define MX28_INT_VDD5V 6 | ||
| 103 | #define MX28_INT_CAN0 8 | ||
| 104 | #define MX28_INT_CAN1 9 | ||
| 105 | #define MX28_INT_LRADC_TOUCH 10 | ||
| 106 | #define MX28_INT_HSADC 13 | ||
| 107 | #define MX28_INT_IRADC_THRESH0 14 | ||
| 108 | #define MX28_INT_IRADC_THRESH1 15 | ||
| 109 | #define MX28_INT_LRADC_CH0 16 | ||
| 110 | #define MX28_INT_LRADC_CH1 17 | ||
| 111 | #define MX28_INT_LRADC_CH2 18 | ||
| 112 | #define MX28_INT_LRADC_CH3 19 | ||
| 113 | #define MX28_INT_LRADC_CH4 20 | ||
| 114 | #define MX28_INT_LRADC_CH5 21 | ||
| 115 | #define MX28_INT_LRADC_CH6 22 | ||
| 116 | #define MX28_INT_LRADC_CH7 23 | ||
| 117 | #define MX28_INT_LRADC_BUTTON0 24 | ||
| 118 | #define MX28_INT_LRADC_BUTTON1 25 | ||
| 119 | #define MX28_INT_PERFMON 27 | ||
| 120 | #define MX28_INT_RTC_1MSEC 28 | ||
| 121 | #define MX28_INT_RTC_ALARM 29 | ||
| 122 | #define MX28_INT_COMMS 31 | ||
| 123 | #define MX28_INT_EMI_ERR 32 | ||
| 124 | #define MX28_INT_LCDIF 38 | ||
| 125 | #define MX28_INT_PXP 39 | ||
| 126 | #define MX28_INT_BCH 41 | ||
| 127 | #define MX28_INT_GPMI 42 | ||
| 128 | #define MX28_INT_SPDIF_ERROR 45 | ||
| 129 | #define MX28_INT_DUART 47 | ||
| 130 | #define MX28_INT_TIMER0 48 | ||
| 131 | #define MX28_INT_TIMER1 49 | ||
| 132 | #define MX28_INT_TIMER2 50 | ||
| 133 | #define MX28_INT_TIMER3 51 | ||
| 134 | #define MX28_INT_DCP_VMI 52 | ||
| 135 | #define MX28_INT_DCP 53 | ||
| 136 | #define MX28_INT_DCP_SECURE 54 | ||
| 137 | #define MX28_INT_SAIF1 58 | ||
| 138 | #define MX28_INT_SAIF0 59 | ||
| 139 | #define MX28_INT_SPDIF_DMA 66 | ||
| 140 | #define MX28_INT_I2C0_DMA 68 | ||
| 141 | #define MX28_INT_I2C1_DMA 69 | ||
| 142 | #define MX28_INT_AUART0_RX_DMA 70 | ||
| 143 | #define MX28_INT_AUART0_TX_DMA 71 | ||
| 144 | #define MX28_INT_AUART1_RX_DMA 72 | ||
| 145 | #define MX28_INT_AUART1_TX_DMA 73 | ||
| 146 | #define MX28_INT_AUART2_RX_DMA 74 | ||
| 147 | #define MX28_INT_AUART2_TX_DMA 75 | ||
| 148 | #define MX28_INT_AUART3_RX_DMA 76 | ||
| 149 | #define MX28_INT_AUART3_TX_DMA 77 | ||
| 150 | #define MX28_INT_AUART4_RX_DMA 78 | ||
| 151 | #define MX28_INT_AUART4_TX_DMA 79 | ||
| 152 | #define MX28_INT_SAIF0_DMA 80 | ||
| 153 | #define MX28_INT_SAIF1_DMA 81 | ||
| 154 | #define MX28_INT_SSP0_DMA 82 | ||
| 155 | #define MX28_INT_SSP1_DMA 83 | ||
| 156 | #define MX28_INT_SSP2_DMA 84 | ||
| 157 | #define MX28_INT_SSP3_DMA 85 | ||
| 158 | #define MX28_INT_LCDIF_DMA 86 | ||
| 159 | #define MX28_INT_HSADC_DMA 87 | ||
| 160 | #define MX28_INT_GPMI_DMA 88 | ||
| 161 | #define MX28_INT_DIGCTL_DEBUG_TRAP 89 | ||
| 162 | #define MX28_INT_USB1 92 | ||
| 163 | #define MX28_INT_USB0 93 | ||
| 164 | #define MX28_INT_USB1_WAKEUP 94 | ||
| 165 | #define MX28_INT_USB0_WAKEUP 95 | ||
| 166 | #define MX28_INT_SSP0 96 | ||
| 167 | #define MX28_INT_SSP1 97 | ||
| 168 | #define MX28_INT_SSP2 98 | ||
| 169 | #define MX28_INT_SSP3 99 | ||
| 170 | #define MX28_INT_ENET_SWI 100 | ||
| 171 | #define MX28_INT_ENET_MAC0 101 | ||
| 172 | #define MX28_INT_ENET_MAC1 102 | ||
| 173 | #define MX28_INT_ENET_MAC0_1588 103 | ||
| 174 | #define MX28_INT_ENET_MAC1_1588 104 | ||
| 175 | #define MX28_INT_I2C1_ERROR 110 | ||
| 176 | #define MX28_INT_I2C0_ERROR 111 | ||
| 177 | #define MX28_INT_AUART0 112 | ||
| 178 | #define MX28_INT_AUART1 113 | ||
| 179 | #define MX28_INT_AUART2 114 | ||
| 180 | #define MX28_INT_AUART3 115 | ||
| 181 | #define MX28_INT_AUART4 116 | ||
| 182 | #define MX28_INT_GPIO4 123 | ||
| 183 | #define MX28_INT_GPIO3 124 | ||
| 184 | #define MX28_INT_GPIO2 125 | ||
| 185 | #define MX28_INT_GPIO1 126 | ||
| 186 | #define MX28_INT_GPIO0 127 | ||
| 187 | |||
| 188 | #endif /* __MACH_MX28_H__ */ | ||
diff --git a/arch/arm/mach-mxs/include/mach/mxs.h b/arch/arm/mach-mxs/include/mach/mxs.h new file mode 100644 index 000000000000..f186c08c2911 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/mxs.h | |||
| @@ -0,0 +1,105 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License along | ||
| 15 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef __MACH_MXS_H__ | ||
| 20 | #define __MACH_MXS_H__ | ||
| 21 | |||
| 22 | #ifndef __ASSEMBLER__ | ||
| 23 | #include <linux/io.h> | ||
| 24 | #endif | ||
| 25 | #include <asm/mach-types.h> | ||
| 26 | #include <mach/hardware.h> | ||
| 27 | |||
| 28 | /* | ||
| 29 | * MXS CPU types | ||
| 30 | */ | ||
| 31 | #define cpu_is_mx23() (machine_is_mx23evk()) | ||
| 32 | #define cpu_is_mx28() (machine_is_mx28evk()) | ||
| 33 | |||
| 34 | /* | ||
| 35 | * IO addresses common to MXS-based | ||
| 36 | */ | ||
| 37 | #define MXS_IO_BASE_ADDR 0x80000000 | ||
| 38 | #define MXS_IO_SIZE SZ_1M | ||
| 39 | |||
| 40 | #define MXS_ICOLL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x000000) | ||
| 41 | #define MXS_APBH_DMA_BASE_ADDR (MXS_IO_BASE_ADDR + 0x004000) | ||
| 42 | #define MXS_BCH_BASE_ADDR (MXS_IO_BASE_ADDR + 0x00a000) | ||
| 43 | #define MXS_GPMI_BASE_ADDR (MXS_IO_BASE_ADDR + 0x00c000) | ||
| 44 | #define MXS_PINCTRL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x018000) | ||
| 45 | #define MXS_DIGCTL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x01c000) | ||
| 46 | #define MXS_APBX_DMA_BASE_ADDR (MXS_IO_BASE_ADDR + 0x024000) | ||
| 47 | #define MXS_DCP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x028000) | ||
| 48 | #define MXS_PXP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02a000) | ||
| 49 | #define MXS_OCOTP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02c000) | ||
| 50 | #define MXS_AXI_AHB0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02e000) | ||
| 51 | #define MXS_LCDIF_BASE_ADDR (MXS_IO_BASE_ADDR + 0x030000) | ||
| 52 | #define MXS_CLKCTRL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x040000) | ||
| 53 | #define MXS_SAIF0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x042000) | ||
| 54 | #define MXS_POWER_BASE_ADDR (MXS_IO_BASE_ADDR + 0x044000) | ||
| 55 | #define MXS_SAIF1_BASE_ADDR (MXS_IO_BASE_ADDR + 0x046000) | ||
| 56 | #define MXS_LRADC_BASE_ADDR (MXS_IO_BASE_ADDR + 0x050000) | ||
| 57 | #define MXS_SPDIF_BASE_ADDR (MXS_IO_BASE_ADDR + 0x054000) | ||
| 58 | #define MXS_I2C0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x058000) | ||
| 59 | #define MXS_PWM_BASE_ADDR (MXS_IO_BASE_ADDR + 0x064000) | ||
| 60 | #define MXS_TIMROT_BASE_ADDR (MXS_IO_BASE_ADDR + 0x068000) | ||
| 61 | #define MXS_AUART1_BASE_ADDR (MXS_IO_BASE_ADDR + 0x06c000) | ||
| 62 | #define MXS_AUART2_BASE_ADDR (MXS_IO_BASE_ADDR + 0x06e000) | ||
| 63 | #define MXS_DRAM_BASE_ADDR (MXS_IO_BASE_ADDR + 0x0e0000) | ||
| 64 | |||
| 65 | /* | ||
| 66 | * It maps the whole address space to [0xf4000000, 0xf50fffff]. | ||
| 67 | * | ||
| 68 | * OCRAM 0x00000000+0x020000 -> 0xf4000000+0x020000 | ||
| 69 | * IO 0x80000000+0x100000 -> 0xf5000000+0x100000 | ||
| 70 | */ | ||
| 71 | #define MXS_IO_P2V(x) (0xf4000000 + \ | ||
| 72 | (((x) & 0x80000000) >> 7) + \ | ||
| 73 | (((x) & 0x000fffff))) | ||
| 74 | |||
| 75 | #define MXS_IO_ADDRESS(x) IOMEM(MXS_IO_P2V(x)) | ||
| 76 | |||
| 77 | #define mxs_map_entry(soc, name, _type) { \ | ||
| 78 | .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \ | ||
| 79 | .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \ | ||
| 80 | .length = soc ## _ ## name ## _SIZE, \ | ||
| 81 | .type = _type, \ | ||
| 82 | } | ||
| 83 | |||
| 84 | #define MXS_SET_ADDR 0x4 | ||
| 85 | #define MXS_CLR_ADDR 0x8 | ||
| 86 | #define MXS_TOG_ADDR 0xc | ||
| 87 | |||
| 88 | #ifndef __ASSEMBLER__ | ||
| 89 | static inline void __mxs_setl(u32 mask, void __iomem *reg) | ||
| 90 | { | ||
| 91 | __raw_writel(mask, reg + MXS_SET_ADDR); | ||
| 92 | } | ||
| 93 | |||
| 94 | static inline void __mxs_clrl(u32 mask, void __iomem *reg) | ||
| 95 | { | ||
| 96 | __raw_writel(mask, reg + MXS_CLR_ADDR); | ||
| 97 | } | ||
| 98 | |||
| 99 | static inline void __mxs_togl(u32 mask, void __iomem *reg) | ||
| 100 | { | ||
| 101 | __raw_writel(mask, reg + MXS_TOG_ADDR); | ||
| 102 | } | ||
| 103 | #endif | ||
| 104 | |||
| 105 | #endif /* __MACH_MXS_H__ */ | ||
diff --git a/arch/arm/mach-mxs/include/mach/system.h b/arch/arm/mach-mxs/include/mach/system.h new file mode 100644 index 000000000000..0e428239b433 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/system.h | |||
| @@ -0,0 +1,27 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 1999 ARM Limited | ||
| 3 | * Copyright (C) 2000 Deep Blue Solutions Ltd | ||
| 4 | * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef __MACH_MXS_SYSTEM_H__ | ||
| 18 | #define __MACH_MXS_SYSTEM_H__ | ||
| 19 | |||
| 20 | static inline void arch_idle(void) | ||
| 21 | { | ||
| 22 | cpu_do_idle(); | ||
| 23 | } | ||
| 24 | |||
| 25 | void arch_reset(char mode, const char *cmd); | ||
| 26 | |||
| 27 | #endif /* __MACH_MXS_SYSTEM_H__ */ | ||
diff --git a/arch/arm/mach-mxs/include/mach/timex.h b/arch/arm/mach-mxs/include/mach/timex.h new file mode 100644 index 000000000000..734ce8984a64 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/timex.h | |||
| @@ -0,0 +1,21 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 1999 ARM Limited | ||
| 3 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License as published by | ||
| 7 | * the Free Software Foundation; either version 2 of the License, or | ||
| 8 | * (at your option) any later version. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef __MACH_MXS_TIMEX_H__ | ||
| 17 | #define __MACH_MXS_TIMEX_H__ | ||
| 18 | |||
| 19 | #define CLOCK_TICK_RATE 32000 /* 32K */ | ||
| 20 | |||
| 21 | #endif /* __MACH_MXS_TIMEX_H__ */ | ||
diff --git a/arch/arm/mach-mxs/include/mach/uncompress.h b/arch/arm/mach-mxs/include/mach/uncompress.h new file mode 100644 index 000000000000..a005e76f34f9 --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/uncompress.h | |||
| @@ -0,0 +1,76 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-mxs/include/mach/uncompress.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1999 ARM Limited | ||
| 5 | * Copyright (C) Shane Nay (shane@minirl.com) | ||
| 6 | * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | */ | ||
| 18 | #ifndef __MACH_MXS_UNCOMPRESS_H__ | ||
| 19 | #define __MACH_MXS_UNCOMPRESS_H__ | ||
| 20 | |||
| 21 | #include <asm/mach-types.h> | ||
| 22 | |||
| 23 | static unsigned long mxs_duart_base; | ||
| 24 | |||
| 25 | #define MXS_DUART(x) (*(volatile unsigned long *)(mxs_duart_base + (x))) | ||
| 26 | |||
| 27 | #define MXS_DUART_DR 0x00 | ||
| 28 | #define MXS_DUART_FR 0x18 | ||
| 29 | #define MXS_DUART_FR_TXFE (1 << 7) | ||
| 30 | #define MXS_DUART_CR 0x30 | ||
| 31 | #define MXS_DUART_CR_UARTEN (1 << 0) | ||
| 32 | |||
| 33 | /* | ||
| 34 | * The following code assumes the serial port has already been | ||
| 35 | * initialized by the bootloader. If it's not, the output is | ||
| 36 | * simply discarded. | ||
| 37 | */ | ||
| 38 | |||
| 39 | static void putc(int ch) | ||
| 40 | { | ||
| 41 | if (!mxs_duart_base) | ||
| 42 | return; | ||
| 43 | if (!(MXS_DUART(MXS_DUART_CR) & MXS_DUART_CR_UARTEN)) | ||
| 44 | return; | ||
| 45 | |||
| 46 | while (!(MXS_DUART(MXS_DUART_FR) & MXS_DUART_FR_TXFE)) | ||
| 47 | barrier(); | ||
| 48 | |||
| 49 | MXS_DUART(MXS_DUART_DR) = ch; | ||
| 50 | } | ||
| 51 | |||
| 52 | static inline void flush(void) | ||
| 53 | { | ||
| 54 | } | ||
| 55 | |||
| 56 | #define MX23_DUART_BASE_ADDR 0x80070000 | ||
| 57 | #define MX28_DUART_BASE_ADDR 0x80074000 | ||
| 58 | |||
| 59 | static inline void __arch_decomp_setup(unsigned long arch_id) | ||
| 60 | { | ||
| 61 | switch (arch_id) { | ||
| 62 | case MACH_TYPE_MX23EVK: | ||
| 63 | mxs_duart_base = MX23_DUART_BASE_ADDR; | ||
| 64 | break; | ||
| 65 | case MACH_TYPE_MX28EVK: | ||
| 66 | mxs_duart_base = MX28_DUART_BASE_ADDR; | ||
| 67 | break; | ||
| 68 | default: | ||
| 69 | break; | ||
| 70 | } | ||
| 71 | } | ||
| 72 | |||
| 73 | #define arch_decomp_setup() __arch_decomp_setup(arch_id) | ||
| 74 | #define arch_decomp_wdog() | ||
| 75 | |||
| 76 | #endif /* __MACH_MXS_UNCOMPRESS_H__ */ | ||
diff --git a/arch/arm/mach-mxs/include/mach/vmalloc.h b/arch/arm/mach-mxs/include/mach/vmalloc.h new file mode 100644 index 000000000000..103b0165ed0b --- /dev/null +++ b/arch/arm/mach-mxs/include/mach/vmalloc.h | |||
| @@ -0,0 +1,22 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2000 Russell King. | ||
| 3 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License as published by | ||
| 7 | * the Free Software Foundation; either version 2 of the License, or | ||
| 8 | * (at your option) any later version. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef __MACH_MXS_VMALLOC_H__ | ||
| 17 | #define __MACH_MXS_VMALLOC_H__ | ||
| 18 | |||
| 19 | /* vmalloc ending address */ | ||
| 20 | #define VMALLOC_END 0xf4000000UL | ||
| 21 | |||
| 22 | #endif /* __MACH_MXS_VMALLOC_H__ */ | ||
diff --git a/arch/arm/mach-mxs/iomux.c b/arch/arm/mach-mxs/iomux.c new file mode 100644 index 000000000000..0e804e2f11f4 --- /dev/null +++ b/arch/arm/mach-mxs/iomux.c | |||
| @@ -0,0 +1,101 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2004-2006,2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> | ||
| 4 | * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, | ||
| 5 | * <armlinux@phytec.de> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or | ||
| 8 | * modify it under the terms of the GNU General Public License | ||
| 9 | * as published by the Free Software Foundation; either version 2 | ||
| 10 | * of the License, or (at your option) any later version. | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 19 | * MA 02110-1301, USA. | ||
| 20 | */ | ||
| 21 | |||
| 22 | #include <linux/errno.h> | ||
| 23 | #include <linux/init.h> | ||
| 24 | #include <linux/kernel.h> | ||
| 25 | #include <linux/module.h> | ||
| 26 | #include <linux/string.h> | ||
| 27 | #include <linux/gpio.h> | ||
| 28 | |||
| 29 | #include <asm/mach/map.h> | ||
| 30 | |||
| 31 | #include <mach/mxs.h> | ||
| 32 | #include <mach/iomux.h> | ||
| 33 | |||
| 34 | /* | ||
| 35 | * configures a single pad in the iomuxer | ||
| 36 | */ | ||
| 37 | int mxs_iomux_setup_pad(iomux_cfg_t pad) | ||
| 38 | { | ||
| 39 | u32 reg, ofs, bp, bm; | ||
| 40 | void __iomem *iomux_base = MXS_IO_ADDRESS(MXS_PINCTRL_BASE_ADDR); | ||
| 41 | |||
| 42 | /* muxsel */ | ||
| 43 | ofs = 0x100; | ||
| 44 | ofs += PAD_BANK(pad) * 0x20 + PAD_PIN(pad) / 16 * 0x10; | ||
| 45 | bp = PAD_PIN(pad) % 16 * 2; | ||
| 46 | bm = 0x3 << bp; | ||
| 47 | reg = __raw_readl(iomux_base + ofs); | ||
| 48 | reg &= ~bm; | ||
| 49 | reg |= PAD_MUXSEL(pad) << bp; | ||
| 50 | __raw_writel(reg, iomux_base + ofs); | ||
| 51 | |||
| 52 | /* drive */ | ||
| 53 | ofs = cpu_is_mx23() ? 0x200 : 0x300; | ||
| 54 | ofs += PAD_BANK(pad) * 0x40 + PAD_PIN(pad) / 8 * 0x10; | ||
| 55 | /* mA */ | ||
| 56 | if (PAD_MA_VALID(pad)) { | ||
| 57 | bp = PAD_PIN(pad) % 8 * 4; | ||
| 58 | bm = 0x3 << bp; | ||
| 59 | reg = __raw_readl(iomux_base + ofs); | ||
| 60 | reg &= ~bm; | ||
| 61 | reg |= PAD_MA(pad) << bp; | ||
| 62 | __raw_writel(reg, iomux_base + ofs); | ||
| 63 | } | ||
| 64 | /* vol */ | ||
| 65 | if (PAD_VOL_VALID(pad)) { | ||
| 66 | bp = PAD_PIN(pad) % 8 * 4 + 2; | ||
| 67 | if (PAD_VOL(pad)) | ||
| 68 | __mxs_setl(1 << bp, iomux_base + ofs); | ||
| 69 | else | ||
| 70 | __mxs_clrl(1 << bp, iomux_base + ofs); | ||
| 71 | } | ||
| 72 | |||
| 73 | /* pull */ | ||
| 74 | if (PAD_PULL_VALID(pad)) { | ||
| 75 | ofs = cpu_is_mx23() ? 0x400 : 0x600; | ||
| 76 | ofs += PAD_BANK(pad) * 0x10; | ||
| 77 | bp = PAD_PIN(pad); | ||
| 78 | if (PAD_PULL(pad)) | ||
| 79 | __mxs_setl(1 << bp, iomux_base + ofs); | ||
| 80 | else | ||
| 81 | __mxs_clrl(1 << bp, iomux_base + ofs); | ||
| 82 | } | ||
| 83 | |||
| 84 | return 0; | ||
| 85 | } | ||
| 86 | |||
| 87 | int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count) | ||
| 88 | { | ||
| 89 | const iomux_cfg_t *p = pad_list; | ||
| 90 | int i; | ||
| 91 | int ret; | ||
| 92 | |||
| 93 | for (i = 0; i < count; i++) { | ||
| 94 | ret = mxs_iomux_setup_pad(*p); | ||
| 95 | if (ret) | ||
| 96 | return ret; | ||
| 97 | p++; | ||
| 98 | } | ||
| 99 | |||
| 100 | return 0; | ||
| 101 | } | ||
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c new file mode 100644 index 000000000000..aa0640052f58 --- /dev/null +++ b/arch/arm/mach-mxs/mach-mx23evk.c | |||
| @@ -0,0 +1,57 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/delay.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <linux/gpio.h> | ||
| 18 | #include <linux/irq.h> | ||
| 19 | |||
| 20 | #include <asm/mach-types.h> | ||
| 21 | #include <asm/mach/arch.h> | ||
| 22 | #include <asm/mach/time.h> | ||
| 23 | |||
| 24 | #include <mach/common.h> | ||
| 25 | #include <mach/iomux-mx23.h> | ||
| 26 | |||
| 27 | #include "devices-mx23.h" | ||
| 28 | |||
| 29 | static const iomux_cfg_t mx23evk_pads[] __initconst = { | ||
| 30 | /* duart */ | ||
| 31 | MX23_PAD_PWM0__DUART_RX | MXS_PAD_4MA, | ||
| 32 | MX23_PAD_PWM1__DUART_TX | MXS_PAD_4MA, | ||
| 33 | }; | ||
| 34 | |||
| 35 | static void __init mx23evk_init(void) | ||
| 36 | { | ||
| 37 | mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads)); | ||
| 38 | |||
| 39 | mx23_add_duart(); | ||
| 40 | } | ||
| 41 | |||
| 42 | static void __init mx23evk_timer_init(void) | ||
| 43 | { | ||
| 44 | mx23_clocks_init(); | ||
| 45 | } | ||
| 46 | |||
| 47 | static struct sys_timer mx23evk_timer = { | ||
| 48 | .init = mx23evk_timer_init, | ||
| 49 | }; | ||
| 50 | |||
| 51 | MACHINE_START(MX23EVK, "Freescale MX23 EVK") | ||
| 52 | /* Maintainer: Freescale Semiconductor, Inc. */ | ||
| 53 | .map_io = mx23_map_io, | ||
| 54 | .init_irq = mx23_init_irq, | ||
| 55 | .init_machine = mx23evk_init, | ||
| 56 | .timer = &mx23evk_timer, | ||
| 57 | MACHINE_END | ||
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c new file mode 100644 index 000000000000..d162e95910f3 --- /dev/null +++ b/arch/arm/mach-mxs/mach-mx28evk.c | |||
| @@ -0,0 +1,138 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/delay.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <linux/gpio.h> | ||
| 18 | #include <linux/irq.h> | ||
| 19 | #include <linux/clk.h> | ||
| 20 | |||
| 21 | #include <asm/mach-types.h> | ||
| 22 | #include <asm/mach/arch.h> | ||
| 23 | #include <asm/mach/time.h> | ||
| 24 | |||
| 25 | #include <mach/common.h> | ||
| 26 | #include <mach/iomux-mx28.h> | ||
| 27 | |||
| 28 | #include "devices-mx28.h" | ||
| 29 | #include "gpio.h" | ||
| 30 | |||
| 31 | #define MX28EVK_FEC_PHY_POWER MXS_GPIO_NR(2, 15) | ||
| 32 | #define MX28EVK_FEC_PHY_RESET MXS_GPIO_NR(4, 13) | ||
| 33 | |||
| 34 | static const iomux_cfg_t mx28evk_pads[] __initconst = { | ||
| 35 | /* duart */ | ||
| 36 | MX28_PAD_PWM0__DUART_RX | | ||
| 37 | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 38 | MX28_PAD_PWM1__DUART_TX | | ||
| 39 | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 40 | |||
| 41 | /* fec0 */ | ||
| 42 | MX28_PAD_ENET0_MDC__ENET0_MDC | | ||
| 43 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 44 | MX28_PAD_ENET0_MDIO__ENET0_MDIO | | ||
| 45 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 46 | MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | | ||
| 47 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 48 | MX28_PAD_ENET0_RXD0__ENET0_RXD0 | | ||
| 49 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 50 | MX28_PAD_ENET0_RXD1__ENET0_RXD1 | | ||
| 51 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 52 | MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | | ||
| 53 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 54 | MX28_PAD_ENET0_TXD0__ENET0_TXD0 | | ||
| 55 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 56 | MX28_PAD_ENET0_TXD1__ENET0_TXD1 | | ||
| 57 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 58 | MX28_PAD_ENET_CLK__CLKCTRL_ENET | | ||
| 59 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 60 | /* phy power line */ | ||
| 61 | MX28_PAD_SSP1_DATA3__GPIO_2_15 | | ||
| 62 | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 63 | /* phy reset line */ | ||
| 64 | MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | | ||
| 65 | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
| 66 | }; | ||
| 67 | |||
| 68 | /* fec */ | ||
| 69 | static void __init mx28evk_fec_reset(void) | ||
| 70 | { | ||
| 71 | int ret; | ||
| 72 | struct clk *clk; | ||
| 73 | |||
| 74 | /* Enable fec phy clock */ | ||
| 75 | clk = clk_get_sys("pll2", NULL); | ||
| 76 | if (!IS_ERR(clk)) | ||
| 77 | clk_enable(clk); | ||
| 78 | |||
| 79 | /* Power up fec phy */ | ||
| 80 | ret = gpio_request(MX28EVK_FEC_PHY_POWER, "fec-phy-power"); | ||
| 81 | if (ret) { | ||
| 82 | pr_err("Failed to request gpio fec-phy-%s: %d\n", "power", ret); | ||
| 83 | return; | ||
| 84 | } | ||
| 85 | |||
| 86 | ret = gpio_direction_output(MX28EVK_FEC_PHY_POWER, 0); | ||
| 87 | if (ret) { | ||
| 88 | pr_err("Failed to drive gpio fec-phy-%s: %d\n", "power", ret); | ||
| 89 | return; | ||
| 90 | } | ||
| 91 | |||
| 92 | /* Reset fec phy */ | ||
| 93 | ret = gpio_request(MX28EVK_FEC_PHY_RESET, "fec-phy-reset"); | ||
| 94 | if (ret) { | ||
| 95 | pr_err("Failed to request gpio fec-phy-%s: %d\n", "reset", ret); | ||
| 96 | return; | ||
| 97 | } | ||
| 98 | |||
| 99 | gpio_direction_output(MX28EVK_FEC_PHY_RESET, 0); | ||
| 100 | if (ret) { | ||
| 101 | pr_err("Failed to drive gpio fec-phy-%s: %d\n", "reset", ret); | ||
| 102 | return; | ||
| 103 | } | ||
| 104 | |||
| 105 | mdelay(1); | ||
| 106 | gpio_set_value(MX28EVK_FEC_PHY_RESET, 1); | ||
| 107 | } | ||
| 108 | |||
| 109 | static const struct fec_platform_data mx28_fec_pdata __initconst = { | ||
| 110 | .phy = PHY_INTERFACE_MODE_RMII, | ||
| 111 | }; | ||
| 112 | |||
| 113 | static void __init mx28evk_init(void) | ||
| 114 | { | ||
| 115 | mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads)); | ||
| 116 | |||
| 117 | mx28_add_duart(); | ||
| 118 | |||
| 119 | mx28evk_fec_reset(); | ||
| 120 | mx28_add_fec(0, &mx28_fec_pdata); | ||
| 121 | } | ||
| 122 | |||
| 123 | static void __init mx28evk_timer_init(void) | ||
| 124 | { | ||
| 125 | mx28_clocks_init(); | ||
| 126 | } | ||
| 127 | |||
| 128 | static struct sys_timer mx28evk_timer = { | ||
| 129 | .init = mx28evk_timer_init, | ||
| 130 | }; | ||
| 131 | |||
| 132 | MACHINE_START(MX28EVK, "Freescale MX28 EVK") | ||
| 133 | /* Maintainer: Freescale Semiconductor, Inc. */ | ||
| 134 | .map_io = mx28_map_io, | ||
| 135 | .init_irq = mx28_init_irq, | ||
| 136 | .init_machine = mx28evk_init, | ||
| 137 | .timer = &mx28evk_timer, | ||
| 138 | MACHINE_END | ||
diff --git a/arch/arm/mach-mxs/mm-mx23.c b/arch/arm/mach-mxs/mm-mx23.c new file mode 100644 index 000000000000..5148cd64a6b7 --- /dev/null +++ b/arch/arm/mach-mxs/mm-mx23.c | |||
| @@ -0,0 +1,45 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | * | ||
| 11 | * Create static mapping between physical to virtual memory. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/mm.h> | ||
| 15 | #include <linux/init.h> | ||
| 16 | |||
| 17 | #include <asm/mach/map.h> | ||
| 18 | |||
| 19 | #include <mach/mx23.h> | ||
| 20 | #include <mach/common.h> | ||
| 21 | #include <mach/iomux.h> | ||
| 22 | |||
| 23 | /* | ||
| 24 | * Define the MX23 memory map. | ||
| 25 | */ | ||
| 26 | static struct map_desc mx23_io_desc[] __initdata = { | ||
| 27 | mxs_map_entry(MX23, OCRAM, MT_DEVICE), | ||
| 28 | mxs_map_entry(MX23, IO, MT_DEVICE), | ||
| 29 | }; | ||
| 30 | |||
| 31 | /* | ||
| 32 | * This function initializes the memory map. It is called during the | ||
| 33 | * system startup to create static physical to virtual memory mappings | ||
| 34 | * for the IO modules. | ||
| 35 | */ | ||
| 36 | void __init mx23_map_io(void) | ||
| 37 | { | ||
| 38 | iotable_init(mx23_io_desc, ARRAY_SIZE(mx23_io_desc)); | ||
| 39 | } | ||
| 40 | |||
| 41 | void __init mx23_init_irq(void) | ||
| 42 | { | ||
| 43 | icoll_init_irq(); | ||
| 44 | mx23_register_gpios(); | ||
| 45 | } | ||
diff --git a/arch/arm/mach-mxs/mm-mx28.c b/arch/arm/mach-mxs/mm-mx28.c new file mode 100644 index 000000000000..7e4cea32ebc6 --- /dev/null +++ b/arch/arm/mach-mxs/mm-mx28.c | |||
| @@ -0,0 +1,45 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | * | ||
| 11 | * Create static mapping between physical to virtual memory. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/mm.h> | ||
| 15 | #include <linux/init.h> | ||
| 16 | |||
| 17 | #include <asm/mach/map.h> | ||
| 18 | |||
| 19 | #include <mach/mx28.h> | ||
| 20 | #include <mach/common.h> | ||
| 21 | #include <mach/iomux.h> | ||
| 22 | |||
| 23 | /* | ||
| 24 | * Define the MX28 memory map. | ||
| 25 | */ | ||
| 26 | static struct map_desc mx28_io_desc[] __initdata = { | ||
| 27 | mxs_map_entry(MX28, OCRAM, MT_DEVICE), | ||
| 28 | mxs_map_entry(MX28, IO, MT_DEVICE), | ||
| 29 | }; | ||
| 30 | |||
| 31 | /* | ||
| 32 | * This function initializes the memory map. It is called during the | ||
| 33 | * system startup to create static physical to virtual memory mappings | ||
| 34 | * for the IO modules. | ||
| 35 | */ | ||
| 36 | void __init mx28_map_io(void) | ||
| 37 | { | ||
| 38 | iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc)); | ||
| 39 | } | ||
| 40 | |||
| 41 | void __init mx28_init_irq(void) | ||
| 42 | { | ||
| 43 | icoll_init_irq(); | ||
| 44 | mx28_register_gpios(); | ||
| 45 | } | ||
diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx23.h b/arch/arm/mach-mxs/regs-clkctrl-mx23.h new file mode 100644 index 000000000000..dbc04747b691 --- /dev/null +++ b/arch/arm/mach-mxs/regs-clkctrl-mx23.h | |||
| @@ -0,0 +1,455 @@ | |||
| 1 | /* | ||
| 2 | * Freescale CLKCTRL Register Definitions | ||
| 3 | * | ||
| 4 | * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. | ||
| 5 | * Copyright 2008-2010 Freescale Semiconductor, Inc. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | * | ||
| 21 | * This file is created by xml file. Don't Edit it. | ||
| 22 | * | ||
| 23 | * Xml Revision: 1.48 | ||
| 24 | * Template revision: 26195 | ||
| 25 | */ | ||
| 26 | |||
| 27 | #ifndef __REGS_CLKCTRL_MX23_H__ | ||
| 28 | #define __REGS_CLKCTRL_MX23_H__ | ||
| 29 | |||
| 30 | |||
| 31 | #define HW_CLKCTRL_PLLCTRL0 (0x00000000) | ||
| 32 | #define HW_CLKCTRL_PLLCTRL0_SET (0x00000004) | ||
| 33 | #define HW_CLKCTRL_PLLCTRL0_CLR (0x00000008) | ||
| 34 | #define HW_CLKCTRL_PLLCTRL0_TOG (0x0000000c) | ||
| 35 | |||
| 36 | #define BP_CLKCTRL_PLLCTRL0_RSRVD6 30 | ||
| 37 | #define BM_CLKCTRL_PLLCTRL0_RSRVD6 0xC0000000 | ||
| 38 | #define BF_CLKCTRL_PLLCTRL0_RSRVD6(v) \ | ||
| 39 | (((v) << 30) & BM_CLKCTRL_PLLCTRL0_RSRVD6) | ||
| 40 | #define BP_CLKCTRL_PLLCTRL0_LFR_SEL 28 | ||
| 41 | #define BM_CLKCTRL_PLLCTRL0_LFR_SEL 0x30000000 | ||
| 42 | #define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v) \ | ||
| 43 | (((v) << 28) & BM_CLKCTRL_PLLCTRL0_LFR_SEL) | ||
| 44 | #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT 0x0 | ||
| 45 | #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2 0x1 | ||
| 46 | #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05 0x2 | ||
| 47 | #define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3 | ||
| 48 | #define BP_CLKCTRL_PLLCTRL0_RSRVD5 26 | ||
| 49 | #define BM_CLKCTRL_PLLCTRL0_RSRVD5 0x0C000000 | ||
| 50 | #define BF_CLKCTRL_PLLCTRL0_RSRVD5(v) \ | ||
| 51 | (((v) << 26) & BM_CLKCTRL_PLLCTRL0_RSRVD5) | ||
| 52 | #define BP_CLKCTRL_PLLCTRL0_CP_SEL 24 | ||
| 53 | #define BM_CLKCTRL_PLLCTRL0_CP_SEL 0x03000000 | ||
| 54 | #define BF_CLKCTRL_PLLCTRL0_CP_SEL(v) \ | ||
| 55 | (((v) << 24) & BM_CLKCTRL_PLLCTRL0_CP_SEL) | ||
| 56 | #define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT 0x0 | ||
| 57 | #define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2 0x1 | ||
| 58 | #define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05 0x2 | ||
| 59 | #define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3 | ||
| 60 | #define BP_CLKCTRL_PLLCTRL0_RSRVD4 22 | ||
| 61 | #define BM_CLKCTRL_PLLCTRL0_RSRVD4 0x00C00000 | ||
| 62 | #define BF_CLKCTRL_PLLCTRL0_RSRVD4(v) \ | ||
| 63 | (((v) << 22) & BM_CLKCTRL_PLLCTRL0_RSRVD4) | ||
| 64 | #define BP_CLKCTRL_PLLCTRL0_DIV_SEL 20 | ||
| 65 | #define BM_CLKCTRL_PLLCTRL0_DIV_SEL 0x00300000 | ||
| 66 | #define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v) \ | ||
| 67 | (((v) << 20) & BM_CLKCTRL_PLLCTRL0_DIV_SEL) | ||
| 68 | #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT 0x0 | ||
| 69 | #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER 0x1 | ||
| 70 | #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST 0x2 | ||
| 71 | #define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3 | ||
| 72 | #define BM_CLKCTRL_PLLCTRL0_RSRVD3 0x00080000 | ||
| 73 | #define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000 | ||
| 74 | #define BM_CLKCTRL_PLLCTRL0_RSRVD2 0x00020000 | ||
| 75 | #define BM_CLKCTRL_PLLCTRL0_POWER 0x00010000 | ||
| 76 | #define BP_CLKCTRL_PLLCTRL0_RSRVD1 0 | ||
| 77 | #define BM_CLKCTRL_PLLCTRL0_RSRVD1 0x0000FFFF | ||
| 78 | #define BF_CLKCTRL_PLLCTRL0_RSRVD1(v) \ | ||
| 79 | (((v) << 0) & BM_CLKCTRL_PLLCTRL0_RSRVD1) | ||
| 80 | |||
| 81 | #define HW_CLKCTRL_PLLCTRL1 (0x00000010) | ||
| 82 | |||
| 83 | #define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000 | ||
| 84 | #define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000 | ||
| 85 | #define BP_CLKCTRL_PLLCTRL1_RSRVD1 16 | ||
| 86 | #define BM_CLKCTRL_PLLCTRL1_RSRVD1 0x3FFF0000 | ||
| 87 | #define BF_CLKCTRL_PLLCTRL1_RSRVD1(v) \ | ||
| 88 | (((v) << 16) & BM_CLKCTRL_PLLCTRL1_RSRVD1) | ||
| 89 | #define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0 | ||
| 90 | #define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0x0000FFFF | ||
| 91 | #define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) \ | ||
| 92 | (((v) << 0) & BM_CLKCTRL_PLLCTRL1_LOCK_COUNT) | ||
| 93 | |||
| 94 | #define HW_CLKCTRL_CPU (0x00000020) | ||
| 95 | #define HW_CLKCTRL_CPU_SET (0x00000024) | ||
| 96 | #define HW_CLKCTRL_CPU_CLR (0x00000028) | ||
| 97 | #define HW_CLKCTRL_CPU_TOG (0x0000002c) | ||
| 98 | |||
| 99 | #define BP_CLKCTRL_CPU_RSRVD5 30 | ||
| 100 | #define BM_CLKCTRL_CPU_RSRVD5 0xC0000000 | ||
| 101 | #define BF_CLKCTRL_CPU_RSRVD5(v) \ | ||
| 102 | (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5) | ||
| 103 | #define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000 | ||
| 104 | #define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000 | ||
| 105 | #define BM_CLKCTRL_CPU_RSRVD4 0x08000000 | ||
| 106 | #define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000 | ||
| 107 | #define BP_CLKCTRL_CPU_DIV_XTAL 16 | ||
| 108 | #define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000 | ||
| 109 | #define BF_CLKCTRL_CPU_DIV_XTAL(v) \ | ||
| 110 | (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL) | ||
| 111 | #define BP_CLKCTRL_CPU_RSRVD3 13 | ||
| 112 | #define BM_CLKCTRL_CPU_RSRVD3 0x0000E000 | ||
| 113 | #define BF_CLKCTRL_CPU_RSRVD3(v) \ | ||
| 114 | (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3) | ||
| 115 | #define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000 | ||
| 116 | #define BM_CLKCTRL_CPU_RSRVD2 0x00000800 | ||
| 117 | #define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400 | ||
| 118 | #define BP_CLKCTRL_CPU_RSRVD1 6 | ||
| 119 | #define BM_CLKCTRL_CPU_RSRVD1 0x000003C0 | ||
| 120 | #define BF_CLKCTRL_CPU_RSRVD1(v) \ | ||
| 121 | (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1) | ||
| 122 | #define BP_CLKCTRL_CPU_DIV_CPU 0 | ||
| 123 | #define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F | ||
| 124 | #define BF_CLKCTRL_CPU_DIV_CPU(v) \ | ||
| 125 | (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU) | ||
| 126 | |||
| 127 | #define HW_CLKCTRL_HBUS (0x00000030) | ||
| 128 | #define HW_CLKCTRL_HBUS_SET (0x00000034) | ||
| 129 | #define HW_CLKCTRL_HBUS_CLR (0x00000038) | ||
| 130 | #define HW_CLKCTRL_HBUS_TOG (0x0000003c) | ||
| 131 | |||
| 132 | #define BP_CLKCTRL_HBUS_RSRVD4 30 | ||
| 133 | #define BM_CLKCTRL_HBUS_RSRVD4 0xC0000000 | ||
| 134 | #define BF_CLKCTRL_HBUS_RSRVD4(v) \ | ||
| 135 | (((v) << 30) & BM_CLKCTRL_HBUS_RSRVD4) | ||
| 136 | #define BM_CLKCTRL_HBUS_BUSY 0x20000000 | ||
| 137 | #define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x10000000 | ||
| 138 | #define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x08000000 | ||
| 139 | #define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000 | ||
| 140 | #define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000 | ||
| 141 | #define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x01000000 | ||
| 142 | #define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x00800000 | ||
| 143 | #define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000 | ||
| 144 | #define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000 | ||
| 145 | #define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x00100000 | ||
| 146 | #define BM_CLKCTRL_HBUS_RSRVD2 0x00080000 | ||
| 147 | #define BP_CLKCTRL_HBUS_SLOW_DIV 16 | ||
| 148 | #define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000 | ||
| 149 | #define BF_CLKCTRL_HBUS_SLOW_DIV(v) \ | ||
| 150 | (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV) | ||
| 151 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0 | ||
| 152 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1 | ||
| 153 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2 | ||
| 154 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 | ||
| 155 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4 | ||
| 156 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5 | ||
| 157 | #define BP_CLKCTRL_HBUS_RSRVD1 6 | ||
| 158 | #define BM_CLKCTRL_HBUS_RSRVD1 0x0000FFC0 | ||
| 159 | #define BF_CLKCTRL_HBUS_RSRVD1(v) \ | ||
| 160 | (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1) | ||
| 161 | #define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020 | ||
| 162 | #define BP_CLKCTRL_HBUS_DIV 0 | ||
| 163 | #define BM_CLKCTRL_HBUS_DIV 0x0000001F | ||
| 164 | #define BF_CLKCTRL_HBUS_DIV(v) \ | ||
| 165 | (((v) << 0) & BM_CLKCTRL_HBUS_DIV) | ||
| 166 | |||
| 167 | #define HW_CLKCTRL_XBUS (0x00000040) | ||
| 168 | |||
| 169 | #define BM_CLKCTRL_XBUS_BUSY 0x80000000 | ||
| 170 | #define BP_CLKCTRL_XBUS_RSRVD1 11 | ||
| 171 | #define BM_CLKCTRL_XBUS_RSRVD1 0x7FFFF800 | ||
| 172 | #define BF_CLKCTRL_XBUS_RSRVD1(v) \ | ||
| 173 | (((v) << 11) & BM_CLKCTRL_XBUS_RSRVD1) | ||
| 174 | #define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400 | ||
| 175 | #define BP_CLKCTRL_XBUS_DIV 0 | ||
| 176 | #define BM_CLKCTRL_XBUS_DIV 0x000003FF | ||
| 177 | #define BF_CLKCTRL_XBUS_DIV(v) \ | ||
| 178 | (((v) << 0) & BM_CLKCTRL_XBUS_DIV) | ||
| 179 | |||
| 180 | #define HW_CLKCTRL_XTAL (0x00000050) | ||
| 181 | #define HW_CLKCTRL_XTAL_SET (0x00000054) | ||
| 182 | #define HW_CLKCTRL_XTAL_CLR (0x00000058) | ||
| 183 | #define HW_CLKCTRL_XTAL_TOG (0x0000005c) | ||
| 184 | |||
| 185 | #define BP_CLKCTRL_XTAL_UART_CLK_GATE 31 | ||
| 186 | #define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000 | ||
| 187 | #define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE 30 | ||
| 188 | #define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE 0x40000000 | ||
| 189 | #define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29 | ||
| 190 | #define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000 | ||
| 191 | #define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000 | ||
| 192 | #define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x08000000 | ||
| 193 | #define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26 | ||
| 194 | #define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000 | ||
| 195 | #define BP_CLKCTRL_XTAL_RSRVD1 2 | ||
| 196 | #define BM_CLKCTRL_XTAL_RSRVD1 0x03FFFFFC | ||
| 197 | #define BF_CLKCTRL_XTAL_RSRVD1(v) \ | ||
| 198 | (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1) | ||
| 199 | #define BP_CLKCTRL_XTAL_DIV_UART 0 | ||
| 200 | #define BM_CLKCTRL_XTAL_DIV_UART 0x00000003 | ||
| 201 | #define BF_CLKCTRL_XTAL_DIV_UART(v) \ | ||
| 202 | (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART) | ||
| 203 | |||
| 204 | #define HW_CLKCTRL_PIX (0x00000060) | ||
| 205 | |||
| 206 | #define BP_CLKCTRL_PIX_CLKGATE 31 | ||
| 207 | #define BM_CLKCTRL_PIX_CLKGATE 0x80000000 | ||
| 208 | #define BM_CLKCTRL_PIX_RSRVD2 0x40000000 | ||
| 209 | #define BM_CLKCTRL_PIX_BUSY 0x20000000 | ||
| 210 | #define BP_CLKCTRL_PIX_RSRVD1 13 | ||
| 211 | #define BM_CLKCTRL_PIX_RSRVD1 0x1FFFE000 | ||
| 212 | #define BF_CLKCTRL_PIX_RSRVD1(v) \ | ||
| 213 | (((v) << 13) & BM_CLKCTRL_PIX_RSRVD1) | ||
| 214 | #define BM_CLKCTRL_PIX_DIV_FRAC_EN 0x00001000 | ||
| 215 | #define BP_CLKCTRL_PIX_DIV 0 | ||
| 216 | #define BM_CLKCTRL_PIX_DIV 0x00000FFF | ||
| 217 | #define BF_CLKCTRL_PIX_DIV(v) \ | ||
| 218 | (((v) << 0) & BM_CLKCTRL_PIX_DIV) | ||
| 219 | |||
| 220 | #define HW_CLKCTRL_SSP (0x00000070) | ||
| 221 | |||
| 222 | #define BP_CLKCTRL_SSP_CLKGATE 31 | ||
| 223 | #define BM_CLKCTRL_SSP_CLKGATE 0x80000000 | ||
| 224 | #define BM_CLKCTRL_SSP_RSRVD2 0x40000000 | ||
| 225 | #define BM_CLKCTRL_SSP_BUSY 0x20000000 | ||
| 226 | #define BP_CLKCTRL_SSP_RSRVD1 10 | ||
| 227 | #define BM_CLKCTRL_SSP_RSRVD1 0x1FFFFC00 | ||
| 228 | #define BF_CLKCTRL_SSP_RSRVD1(v) \ | ||
| 229 | (((v) << 10) & BM_CLKCTRL_SSP_RSRVD1) | ||
| 230 | #define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x00000200 | ||
| 231 | #define BP_CLKCTRL_SSP_DIV 0 | ||
| 232 | #define BM_CLKCTRL_SSP_DIV 0x000001FF | ||
| 233 | #define BF_CLKCTRL_SSP_DIV(v) \ | ||
| 234 | (((v) << 0) & BM_CLKCTRL_SSP_DIV) | ||
| 235 | |||
| 236 | #define HW_CLKCTRL_GPMI (0x00000080) | ||
| 237 | |||
| 238 | #define BP_CLKCTRL_GPMI_CLKGATE 31 | ||
| 239 | #define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 | ||
| 240 | #define BM_CLKCTRL_GPMI_RSRVD2 0x40000000 | ||
| 241 | #define BM_CLKCTRL_GPMI_BUSY 0x20000000 | ||
| 242 | #define BP_CLKCTRL_GPMI_RSRVD1 11 | ||
| 243 | #define BM_CLKCTRL_GPMI_RSRVD1 0x1FFFF800 | ||
| 244 | #define BF_CLKCTRL_GPMI_RSRVD1(v) \ | ||
| 245 | (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1) | ||
| 246 | #define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400 | ||
| 247 | #define BP_CLKCTRL_GPMI_DIV 0 | ||
| 248 | #define BM_CLKCTRL_GPMI_DIV 0x000003FF | ||
| 249 | #define BF_CLKCTRL_GPMI_DIV(v) \ | ||
| 250 | (((v) << 0) & BM_CLKCTRL_GPMI_DIV) | ||
| 251 | |||
| 252 | #define HW_CLKCTRL_SPDIF (0x00000090) | ||
| 253 | |||
| 254 | #define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 | ||
| 255 | #define BP_CLKCTRL_SPDIF_RSRVD 0 | ||
| 256 | #define BM_CLKCTRL_SPDIF_RSRVD 0x7FFFFFFF | ||
| 257 | #define BF_CLKCTRL_SPDIF_RSRVD(v) \ | ||
| 258 | (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD) | ||
| 259 | |||
| 260 | #define HW_CLKCTRL_EMI (0x000000a0) | ||
| 261 | |||
| 262 | #define BP_CLKCTRL_EMI_CLKGATE 31 | ||
| 263 | #define BM_CLKCTRL_EMI_CLKGATE 0x80000000 | ||
| 264 | #define BM_CLKCTRL_EMI_SYNC_MODE_EN 0x40000000 | ||
| 265 | #define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000 | ||
| 266 | #define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 | ||
| 267 | #define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000 | ||
| 268 | #define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000 | ||
| 269 | #define BP_CLKCTRL_EMI_RSRVD3 18 | ||
| 270 | #define BM_CLKCTRL_EMI_RSRVD3 0x03FC0000 | ||
| 271 | #define BF_CLKCTRL_EMI_RSRVD3(v) \ | ||
| 272 | (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3) | ||
| 273 | #define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000 | ||
| 274 | #define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000 | ||
| 275 | #define BP_CLKCTRL_EMI_RSRVD2 12 | ||
| 276 | #define BM_CLKCTRL_EMI_RSRVD2 0x0000F000 | ||
| 277 | #define BF_CLKCTRL_EMI_RSRVD2(v) \ | ||
| 278 | (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2) | ||
| 279 | #define BP_CLKCTRL_EMI_DIV_XTAL 8 | ||
| 280 | #define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00 | ||
| 281 | #define BF_CLKCTRL_EMI_DIV_XTAL(v) \ | ||
| 282 | (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL) | ||
| 283 | #define BP_CLKCTRL_EMI_RSRVD1 6 | ||
| 284 | #define BM_CLKCTRL_EMI_RSRVD1 0x000000C0 | ||
| 285 | #define BF_CLKCTRL_EMI_RSRVD1(v) \ | ||
| 286 | (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1) | ||
| 287 | #define BP_CLKCTRL_EMI_DIV_EMI 0 | ||
| 288 | #define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F | ||
| 289 | #define BF_CLKCTRL_EMI_DIV_EMI(v) \ | ||
| 290 | (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI) | ||
| 291 | |||
| 292 | #define HW_CLKCTRL_IR (0x000000b0) | ||
| 293 | |||
| 294 | #define BM_CLKCTRL_IR_CLKGATE 0x80000000 | ||
| 295 | #define BM_CLKCTRL_IR_RSRVD3 0x40000000 | ||
| 296 | #define BM_CLKCTRL_IR_AUTO_DIV 0x20000000 | ||
| 297 | #define BM_CLKCTRL_IR_IR_BUSY 0x10000000 | ||
| 298 | #define BM_CLKCTRL_IR_IROV_BUSY 0x08000000 | ||
| 299 | #define BP_CLKCTRL_IR_RSRVD2 25 | ||
| 300 | #define BM_CLKCTRL_IR_RSRVD2 0x06000000 | ||
| 301 | #define BF_CLKCTRL_IR_RSRVD2(v) \ | ||
| 302 | (((v) << 25) & BM_CLKCTRL_IR_RSRVD2) | ||
| 303 | #define BP_CLKCTRL_IR_IROV_DIV 16 | ||
| 304 | #define BM_CLKCTRL_IR_IROV_DIV 0x01FF0000 | ||
| 305 | #define BF_CLKCTRL_IR_IROV_DIV(v) \ | ||
| 306 | (((v) << 16) & BM_CLKCTRL_IR_IROV_DIV) | ||
| 307 | #define BP_CLKCTRL_IR_RSRVD1 10 | ||
| 308 | #define BM_CLKCTRL_IR_RSRVD1 0x0000FC00 | ||
| 309 | #define BF_CLKCTRL_IR_RSRVD1(v) \ | ||
| 310 | (((v) << 10) & BM_CLKCTRL_IR_RSRVD1) | ||
| 311 | #define BP_CLKCTRL_IR_IR_DIV 0 | ||
| 312 | #define BM_CLKCTRL_IR_IR_DIV 0x000003FF | ||
| 313 | #define BF_CLKCTRL_IR_IR_DIV(v) \ | ||
| 314 | (((v) << 0) & BM_CLKCTRL_IR_IR_DIV) | ||
| 315 | |||
| 316 | #define HW_CLKCTRL_SAIF (0x000000c0) | ||
| 317 | |||
| 318 | #define BM_CLKCTRL_SAIF_CLKGATE 0x80000000 | ||
| 319 | #define BM_CLKCTRL_SAIF_RSRVD2 0x40000000 | ||
| 320 | #define BM_CLKCTRL_SAIF_BUSY 0x20000000 | ||
| 321 | #define BP_CLKCTRL_SAIF_RSRVD1 17 | ||
| 322 | #define BM_CLKCTRL_SAIF_RSRVD1 0x1FFE0000 | ||
| 323 | #define BF_CLKCTRL_SAIF_RSRVD1(v) \ | ||
| 324 | (((v) << 17) & BM_CLKCTRL_SAIF_RSRVD1) | ||
| 325 | #define BM_CLKCTRL_SAIF_DIV_FRAC_EN 0x00010000 | ||
| 326 | #define BP_CLKCTRL_SAIF_DIV 0 | ||
| 327 | #define BM_CLKCTRL_SAIF_DIV 0x0000FFFF | ||
| 328 | #define BF_CLKCTRL_SAIF_DIV(v) \ | ||
| 329 | (((v) << 0) & BM_CLKCTRL_SAIF_DIV) | ||
| 330 | |||
| 331 | #define HW_CLKCTRL_TV (0x000000d0) | ||
| 332 | |||
| 333 | #define BM_CLKCTRL_TV_CLK_TV108M_GATE 0x80000000 | ||
| 334 | #define BM_CLKCTRL_TV_CLK_TV_GATE 0x40000000 | ||
| 335 | #define BP_CLKCTRL_TV_RSRVD 0 | ||
| 336 | #define BM_CLKCTRL_TV_RSRVD 0x3FFFFFFF | ||
| 337 | #define BF_CLKCTRL_TV_RSRVD(v) \ | ||
| 338 | (((v) << 0) & BM_CLKCTRL_TV_RSRVD) | ||
| 339 | |||
| 340 | #define HW_CLKCTRL_ETM (0x000000e0) | ||
| 341 | |||
| 342 | #define BM_CLKCTRL_ETM_CLKGATE 0x80000000 | ||
| 343 | #define BM_CLKCTRL_ETM_RSRVD2 0x40000000 | ||
| 344 | #define BM_CLKCTRL_ETM_BUSY 0x20000000 | ||
| 345 | #define BP_CLKCTRL_ETM_RSRVD1 7 | ||
| 346 | #define BM_CLKCTRL_ETM_RSRVD1 0x1FFFFF80 | ||
| 347 | #define BF_CLKCTRL_ETM_RSRVD1(v) \ | ||
| 348 | (((v) << 7) & BM_CLKCTRL_ETM_RSRVD1) | ||
| 349 | #define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000040 | ||
| 350 | #define BP_CLKCTRL_ETM_DIV 0 | ||
| 351 | #define BM_CLKCTRL_ETM_DIV 0x0000003F | ||
| 352 | #define BF_CLKCTRL_ETM_DIV(v) \ | ||
| 353 | (((v) << 0) & BM_CLKCTRL_ETM_DIV) | ||
| 354 | |||
| 355 | #define HW_CLKCTRL_FRAC (0x000000f0) | ||
| 356 | #define HW_CLKCTRL_FRAC_SET (0x000000f4) | ||
| 357 | #define HW_CLKCTRL_FRAC_CLR (0x000000f8) | ||
| 358 | #define HW_CLKCTRL_FRAC_TOG (0x000000fc) | ||
| 359 | |||
| 360 | #define BP_CLKCTRL_FRAC_CLKGATEIO 31 | ||
| 361 | #define BM_CLKCTRL_FRAC_CLKGATEIO 0x80000000 | ||
| 362 | #define BM_CLKCTRL_FRAC_IO_STABLE 0x40000000 | ||
| 363 | #define BP_CLKCTRL_FRAC_IOFRAC 24 | ||
| 364 | #define BM_CLKCTRL_FRAC_IOFRAC 0x3F000000 | ||
| 365 | #define BF_CLKCTRL_FRAC_IOFRAC(v) \ | ||
| 366 | (((v) << 24) & BM_CLKCTRL_FRAC_IOFRAC) | ||
| 367 | #define BP_CLKCTRL_FRAC_CLKGATEPIX 23 | ||
| 368 | #define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000 | ||
| 369 | #define BM_CLKCTRL_FRAC_PIX_STABLE 0x00400000 | ||
| 370 | #define BP_CLKCTRL_FRAC_PIXFRAC 16 | ||
| 371 | #define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000 | ||
| 372 | #define BF_CLKCTRL_FRAC_PIXFRAC(v) \ | ||
| 373 | (((v) << 16) & BM_CLKCTRL_FRAC_PIXFRAC) | ||
| 374 | #define BP_CLKCTRL_FRAC_CLKGATEEMI 15 | ||
| 375 | #define BM_CLKCTRL_FRAC_CLKGATEEMI 0x00008000 | ||
| 376 | #define BM_CLKCTRL_FRAC_EMI_STABLE 0x00004000 | ||
| 377 | #define BP_CLKCTRL_FRAC_EMIFRAC 8 | ||
| 378 | #define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00 | ||
| 379 | #define BF_CLKCTRL_FRAC_EMIFRAC(v) \ | ||
| 380 | (((v) << 8) & BM_CLKCTRL_FRAC_EMIFRAC) | ||
| 381 | #define BP_CLKCTRL_FRAC_CLKGATECPU 7 | ||
| 382 | #define BM_CLKCTRL_FRAC_CLKGATECPU 0x00000080 | ||
| 383 | #define BM_CLKCTRL_FRAC_CPU_STABLE 0x00000040 | ||
| 384 | #define BP_CLKCTRL_FRAC_CPUFRAC 0 | ||
| 385 | #define BM_CLKCTRL_FRAC_CPUFRAC 0x0000003F | ||
| 386 | #define BF_CLKCTRL_FRAC_CPUFRAC(v) \ | ||
| 387 | (((v) << 0) & BM_CLKCTRL_FRAC_CPUFRAC) | ||
| 388 | |||
| 389 | #define HW_CLKCTRL_FRAC1 (0x00000100) | ||
| 390 | #define HW_CLKCTRL_FRAC1_SET (0x00000104) | ||
| 391 | #define HW_CLKCTRL_FRAC1_CLR (0x00000108) | ||
| 392 | #define HW_CLKCTRL_FRAC1_TOG (0x0000010c) | ||
| 393 | |||
| 394 | #define BM_CLKCTRL_FRAC1_CLKGATEVID 0x80000000 | ||
| 395 | #define BM_CLKCTRL_FRAC1_VID_STABLE 0x40000000 | ||
| 396 | #define BP_CLKCTRL_FRAC1_RSRVD1 0 | ||
| 397 | #define BM_CLKCTRL_FRAC1_RSRVD1 0x3FFFFFFF | ||
| 398 | #define BF_CLKCTRL_FRAC1_RSRVD1(v) \ | ||
| 399 | (((v) << 0) & BM_CLKCTRL_FRAC1_RSRVD1) | ||
| 400 | |||
| 401 | #define HW_CLKCTRL_CLKSEQ (0x00000110) | ||
| 402 | #define HW_CLKCTRL_CLKSEQ_SET (0x00000114) | ||
| 403 | #define HW_CLKCTRL_CLKSEQ_CLR (0x00000118) | ||
| 404 | #define HW_CLKCTRL_CLKSEQ_TOG (0x0000011c) | ||
| 405 | |||
| 406 | #define BP_CLKCTRL_CLKSEQ_RSRVD1 9 | ||
| 407 | #define BM_CLKCTRL_CLKSEQ_RSRVD1 0xFFFFFE00 | ||
| 408 | #define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \ | ||
| 409 | (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD1) | ||
| 410 | #define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100 | ||
| 411 | #define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00000080 | ||
| 412 | #define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000040 | ||
| 413 | #define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x00000020 | ||
| 414 | #define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000010 | ||
| 415 | #define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x00000008 | ||
| 416 | #define BM_CLKCTRL_CLKSEQ_RSRVD0 0x00000004 | ||
| 417 | #define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002 | ||
| 418 | #define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x00000001 | ||
| 419 | |||
| 420 | #define HW_CLKCTRL_RESET (0x00000120) | ||
| 421 | |||
| 422 | #define BP_CLKCTRL_RESET_RSRVD 2 | ||
| 423 | #define BM_CLKCTRL_RESET_RSRVD 0xFFFFFFFC | ||
| 424 | #define BF_CLKCTRL_RESET_RSRVD(v) \ | ||
| 425 | (((v) << 2) & BM_CLKCTRL_RESET_RSRVD) | ||
| 426 | #define BM_CLKCTRL_RESET_CHIP 0x00000002 | ||
| 427 | #define BM_CLKCTRL_RESET_DIG 0x00000001 | ||
| 428 | |||
| 429 | #define HW_CLKCTRL_STATUS (0x00000130) | ||
| 430 | |||
| 431 | #define BP_CLKCTRL_STATUS_CPU_LIMIT 30 | ||
| 432 | #define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000 | ||
| 433 | #define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \ | ||
| 434 | (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT) | ||
| 435 | #define BP_CLKCTRL_STATUS_RSRVD 0 | ||
| 436 | #define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF | ||
| 437 | #define BF_CLKCTRL_STATUS_RSRVD(v) \ | ||
| 438 | (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD) | ||
| 439 | |||
| 440 | #define HW_CLKCTRL_VERSION (0x00000140) | ||
| 441 | |||
| 442 | #define BP_CLKCTRL_VERSION_MAJOR 24 | ||
| 443 | #define BM_CLKCTRL_VERSION_MAJOR 0xFF000000 | ||
| 444 | #define BF_CLKCTRL_VERSION_MAJOR(v) \ | ||
| 445 | (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR) | ||
| 446 | #define BP_CLKCTRL_VERSION_MINOR 16 | ||
| 447 | #define BM_CLKCTRL_VERSION_MINOR 0x00FF0000 | ||
| 448 | #define BF_CLKCTRL_VERSION_MINOR(v) \ | ||
| 449 | (((v) << 16) & BM_CLKCTRL_VERSION_MINOR) | ||
| 450 | #define BP_CLKCTRL_VERSION_STEP 0 | ||
| 451 | #define BM_CLKCTRL_VERSION_STEP 0x0000FFFF | ||
| 452 | #define BF_CLKCTRL_VERSION_STEP(v) \ | ||
| 453 | (((v) << 0) & BM_CLKCTRL_VERSION_STEP) | ||
| 454 | |||
| 455 | #endif /* __REGS_CLKCTRL_MX23_H__ */ | ||
diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx28.h b/arch/arm/mach-mxs/regs-clkctrl-mx28.h new file mode 100644 index 000000000000..661df18755f7 --- /dev/null +++ b/arch/arm/mach-mxs/regs-clkctrl-mx28.h | |||
| @@ -0,0 +1,663 @@ | |||
| 1 | /* | ||
| 2 | * Freescale CLKCTRL Register Definitions | ||
| 3 | * | ||
| 4 | * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | * | ||
| 20 | * This file is created by xml file. Don't Edit it. | ||
| 21 | * | ||
| 22 | * Xml Revision: 1.48 | ||
| 23 | * Template revision: 26195 | ||
| 24 | */ | ||
| 25 | |||
| 26 | #ifndef __REGS_CLKCTRL_MX28_H__ | ||
| 27 | #define __REGS_CLKCTRL_MX28_H__ | ||
| 28 | |||
| 29 | #define HW_CLKCTRL_PLL0CTRL0 (0x00000000) | ||
| 30 | #define HW_CLKCTRL_PLL0CTRL0_SET (0x00000004) | ||
| 31 | #define HW_CLKCTRL_PLL0CTRL0_CLR (0x00000008) | ||
| 32 | #define HW_CLKCTRL_PLL0CTRL0_TOG (0x0000000c) | ||
| 33 | |||
| 34 | #define BP_CLKCTRL_PLL0CTRL0_RSRVD6 30 | ||
| 35 | #define BM_CLKCTRL_PLL0CTRL0_RSRVD6 0xC0000000 | ||
| 36 | #define BF_CLKCTRL_PLL0CTRL0_RSRVD6(v) \ | ||
| 37 | (((v) << 30) & BM_CLKCTRL_PLL0CTRL0_RSRVD6) | ||
| 38 | #define BP_CLKCTRL_PLL0CTRL0_LFR_SEL 28 | ||
| 39 | #define BM_CLKCTRL_PLL0CTRL0_LFR_SEL 0x30000000 | ||
| 40 | #define BF_CLKCTRL_PLL0CTRL0_LFR_SEL(v) \ | ||
| 41 | (((v) << 28) & BM_CLKCTRL_PLL0CTRL0_LFR_SEL) | ||
| 42 | #define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__DEFAULT 0x0 | ||
| 43 | #define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_2 0x1 | ||
| 44 | #define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_05 0x2 | ||
| 45 | #define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__UNDEFINED 0x3 | ||
| 46 | #define BP_CLKCTRL_PLL0CTRL0_RSRVD5 26 | ||
| 47 | #define BM_CLKCTRL_PLL0CTRL0_RSRVD5 0x0C000000 | ||
| 48 | #define BF_CLKCTRL_PLL0CTRL0_RSRVD5(v) \ | ||
| 49 | (((v) << 26) & BM_CLKCTRL_PLL0CTRL0_RSRVD5) | ||
| 50 | #define BP_CLKCTRL_PLL0CTRL0_CP_SEL 24 | ||
| 51 | #define BM_CLKCTRL_PLL0CTRL0_CP_SEL 0x03000000 | ||
| 52 | #define BF_CLKCTRL_PLL0CTRL0_CP_SEL(v) \ | ||
| 53 | (((v) << 24) & BM_CLKCTRL_PLL0CTRL0_CP_SEL) | ||
| 54 | #define BV_CLKCTRL_PLL0CTRL0_CP_SEL__DEFAULT 0x0 | ||
| 55 | #define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_2 0x1 | ||
| 56 | #define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_05 0x2 | ||
| 57 | #define BV_CLKCTRL_PLL0CTRL0_CP_SEL__UNDEFINED 0x3 | ||
| 58 | #define BP_CLKCTRL_PLL0CTRL0_RSRVD4 22 | ||
| 59 | #define BM_CLKCTRL_PLL0CTRL0_RSRVD4 0x00C00000 | ||
| 60 | #define BF_CLKCTRL_PLL0CTRL0_RSRVD4(v) \ | ||
| 61 | (((v) << 22) & BM_CLKCTRL_PLL0CTRL0_RSRVD4) | ||
| 62 | #define BP_CLKCTRL_PLL0CTRL0_DIV_SEL 20 | ||
| 63 | #define BM_CLKCTRL_PLL0CTRL0_DIV_SEL 0x00300000 | ||
| 64 | #define BF_CLKCTRL_PLL0CTRL0_DIV_SEL(v) \ | ||
| 65 | (((v) << 20) & BM_CLKCTRL_PLL0CTRL0_DIV_SEL) | ||
| 66 | #define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__DEFAULT 0x0 | ||
| 67 | #define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWER 0x1 | ||
| 68 | #define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWEST 0x2 | ||
| 69 | #define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__UNDEFINED 0x3 | ||
| 70 | #define BM_CLKCTRL_PLL0CTRL0_RSRVD3 0x00080000 | ||
| 71 | #define BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS 0x00040000 | ||
| 72 | #define BM_CLKCTRL_PLL0CTRL0_POWER 0x00020000 | ||
| 73 | #define BP_CLKCTRL_PLL0CTRL0_RSRVD1 0 | ||
| 74 | #define BM_CLKCTRL_PLL0CTRL0_RSRVD1 0x0001FFFF | ||
| 75 | #define BF_CLKCTRL_PLL0CTRL0_RSRVD1(v) \ | ||
| 76 | (((v) << 0) & BM_CLKCTRL_PLL0CTRL0_RSRVD1) | ||
| 77 | |||
| 78 | #define HW_CLKCTRL_PLL0CTRL1 (0x00000010) | ||
| 79 | |||
| 80 | #define BM_CLKCTRL_PLL0CTRL1_LOCK 0x80000000 | ||
| 81 | #define BM_CLKCTRL_PLL0CTRL1_FORCE_LOCK 0x40000000 | ||
| 82 | #define BP_CLKCTRL_PLL0CTRL1_RSRVD1 16 | ||
| 83 | #define BM_CLKCTRL_PLL0CTRL1_RSRVD1 0x3FFF0000 | ||
| 84 | #define BF_CLKCTRL_PLL0CTRL1_RSRVD1(v) \ | ||
| 85 | (((v) << 16) & BM_CLKCTRL_PLL0CTRL1_RSRVD1) | ||
| 86 | #define BP_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0 | ||
| 87 | #define BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0x0000FFFF | ||
| 88 | #define BF_CLKCTRL_PLL0CTRL1_LOCK_COUNT(v) \ | ||
| 89 | (((v) << 0) & BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT) | ||
| 90 | |||
| 91 | #define HW_CLKCTRL_PLL1CTRL0 (0x00000020) | ||
| 92 | #define HW_CLKCTRL_PLL1CTRL0_SET (0x00000024) | ||
| 93 | #define HW_CLKCTRL_PLL1CTRL0_CLR (0x00000028) | ||
| 94 | #define HW_CLKCTRL_PLL1CTRL0_TOG (0x0000002c) | ||
| 95 | |||
| 96 | #define BM_CLKCTRL_PLL1CTRL0_CLKGATEEMI 0x80000000 | ||
| 97 | #define BM_CLKCTRL_PLL1CTRL0_RSRVD6 0x40000000 | ||
| 98 | #define BP_CLKCTRL_PLL1CTRL0_LFR_SEL 28 | ||
| 99 | #define BM_CLKCTRL_PLL1CTRL0_LFR_SEL 0x30000000 | ||
| 100 | #define BF_CLKCTRL_PLL1CTRL0_LFR_SEL(v) \ | ||
| 101 | (((v) << 28) & BM_CLKCTRL_PLL1CTRL0_LFR_SEL) | ||
| 102 | #define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__DEFAULT 0x0 | ||
| 103 | #define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_2 0x1 | ||
| 104 | #define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_05 0x2 | ||
| 105 | #define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__UNDEFINED 0x3 | ||
| 106 | #define BP_CLKCTRL_PLL1CTRL0_RSRVD5 26 | ||
| 107 | #define BM_CLKCTRL_PLL1CTRL0_RSRVD5 0x0C000000 | ||
| 108 | #define BF_CLKCTRL_PLL1CTRL0_RSRVD5(v) \ | ||
| 109 | (((v) << 26) & BM_CLKCTRL_PLL1CTRL0_RSRVD5) | ||
| 110 | #define BP_CLKCTRL_PLL1CTRL0_CP_SEL 24 | ||
| 111 | #define BM_CLKCTRL_PLL1CTRL0_CP_SEL 0x03000000 | ||
| 112 | #define BF_CLKCTRL_PLL1CTRL0_CP_SEL(v) \ | ||
| 113 | (((v) << 24) & BM_CLKCTRL_PLL1CTRL0_CP_SEL) | ||
| 114 | #define BV_CLKCTRL_PLL1CTRL0_CP_SEL__DEFAULT 0x0 | ||
| 115 | #define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_2 0x1 | ||
| 116 | #define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_05 0x2 | ||
| 117 | #define BV_CLKCTRL_PLL1CTRL0_CP_SEL__UNDEFINED 0x3 | ||
| 118 | #define BP_CLKCTRL_PLL1CTRL0_RSRVD4 22 | ||
| 119 | #define BM_CLKCTRL_PLL1CTRL0_RSRVD4 0x00C00000 | ||
| 120 | #define BF_CLKCTRL_PLL1CTRL0_RSRVD4(v) \ | ||
| 121 | (((v) << 22) & BM_CLKCTRL_PLL1CTRL0_RSRVD4) | ||
| 122 | #define BP_CLKCTRL_PLL1CTRL0_DIV_SEL 20 | ||
| 123 | #define BM_CLKCTRL_PLL1CTRL0_DIV_SEL 0x00300000 | ||
| 124 | #define BF_CLKCTRL_PLL1CTRL0_DIV_SEL(v) \ | ||
| 125 | (((v) << 20) & BM_CLKCTRL_PLL1CTRL0_DIV_SEL) | ||
| 126 | #define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__DEFAULT 0x0 | ||
| 127 | #define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWER 0x1 | ||
| 128 | #define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWEST 0x2 | ||
| 129 | #define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__UNDEFINED 0x3 | ||
| 130 | #define BM_CLKCTRL_PLL1CTRL0_RSRVD3 0x00080000 | ||
| 131 | #define BM_CLKCTRL_PLL1CTRL0_EN_USB_CLKS 0x00040000 | ||
| 132 | #define BM_CLKCTRL_PLL1CTRL0_POWER 0x00020000 | ||
| 133 | #define BP_CLKCTRL_PLL1CTRL0_RSRVD1 0 | ||
| 134 | #define BM_CLKCTRL_PLL1CTRL0_RSRVD1 0x0001FFFF | ||
| 135 | #define BF_CLKCTRL_PLL1CTRL0_RSRVD1(v) \ | ||
| 136 | (((v) << 0) & BM_CLKCTRL_PLL1CTRL0_RSRVD1) | ||
| 137 | |||
| 138 | #define HW_CLKCTRL_PLL1CTRL1 (0x00000030) | ||
| 139 | |||
| 140 | #define BM_CLKCTRL_PLL1CTRL1_LOCK 0x80000000 | ||
| 141 | #define BM_CLKCTRL_PLL1CTRL1_FORCE_LOCK 0x40000000 | ||
| 142 | #define BP_CLKCTRL_PLL1CTRL1_RSRVD1 16 | ||
| 143 | #define BM_CLKCTRL_PLL1CTRL1_RSRVD1 0x3FFF0000 | ||
| 144 | #define BF_CLKCTRL_PLL1CTRL1_RSRVD1(v) \ | ||
| 145 | (((v) << 16) & BM_CLKCTRL_PLL1CTRL1_RSRVD1) | ||
| 146 | #define BP_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0 | ||
| 147 | #define BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0x0000FFFF | ||
| 148 | #define BF_CLKCTRL_PLL1CTRL1_LOCK_COUNT(v) \ | ||
| 149 | (((v) << 0) & BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT) | ||
| 150 | |||
| 151 | #define HW_CLKCTRL_PLL2CTRL0 (0x00000040) | ||
| 152 | #define HW_CLKCTRL_PLL2CTRL0_SET (0x00000044) | ||
| 153 | #define HW_CLKCTRL_PLL2CTRL0_CLR (0x00000048) | ||
| 154 | #define HW_CLKCTRL_PLL2CTRL0_TOG (0x0000004c) | ||
| 155 | |||
| 156 | #define BM_CLKCTRL_PLL2CTRL0_CLKGATE 0x80000000 | ||
| 157 | #define BM_CLKCTRL_PLL2CTRL0_RSRVD3 0x40000000 | ||
| 158 | #define BP_CLKCTRL_PLL2CTRL0_LFR_SEL 28 | ||
| 159 | #define BM_CLKCTRL_PLL2CTRL0_LFR_SEL 0x30000000 | ||
| 160 | #define BF_CLKCTRL_PLL2CTRL0_LFR_SEL(v) \ | ||
| 161 | (((v) << 28) & BM_CLKCTRL_PLL2CTRL0_LFR_SEL) | ||
| 162 | #define BM_CLKCTRL_PLL2CTRL0_RSRVD2 0x08000000 | ||
| 163 | #define BM_CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B 0x04000000 | ||
| 164 | #define BP_CLKCTRL_PLL2CTRL0_CP_SEL 24 | ||
| 165 | #define BM_CLKCTRL_PLL2CTRL0_CP_SEL 0x03000000 | ||
| 166 | #define BF_CLKCTRL_PLL2CTRL0_CP_SEL(v) \ | ||
| 167 | (((v) << 24) & BM_CLKCTRL_PLL2CTRL0_CP_SEL) | ||
| 168 | #define BM_CLKCTRL_PLL2CTRL0_POWER 0x00800000 | ||
| 169 | #define BP_CLKCTRL_PLL2CTRL0_RSRVD1 0 | ||
| 170 | #define BM_CLKCTRL_PLL2CTRL0_RSRVD1 0x007FFFFF | ||
| 171 | #define BF_CLKCTRL_PLL2CTRL0_RSRVD1(v) \ | ||
| 172 | (((v) << 0) & BM_CLKCTRL_PLL2CTRL0_RSRVD1) | ||
| 173 | |||
| 174 | #define HW_CLKCTRL_CPU (0x00000050) | ||
| 175 | #define HW_CLKCTRL_CPU_SET (0x00000054) | ||
| 176 | #define HW_CLKCTRL_CPU_CLR (0x00000058) | ||
| 177 | #define HW_CLKCTRL_CPU_TOG (0x0000005c) | ||
| 178 | |||
| 179 | #define BP_CLKCTRL_CPU_RSRVD5 30 | ||
| 180 | #define BM_CLKCTRL_CPU_RSRVD5 0xC0000000 | ||
| 181 | #define BF_CLKCTRL_CPU_RSRVD5(v) \ | ||
| 182 | (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5) | ||
| 183 | #define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000 | ||
| 184 | #define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000 | ||
| 185 | #define BM_CLKCTRL_CPU_RSRVD4 0x08000000 | ||
| 186 | #define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000 | ||
| 187 | #define BP_CLKCTRL_CPU_DIV_XTAL 16 | ||
| 188 | #define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000 | ||
| 189 | #define BF_CLKCTRL_CPU_DIV_XTAL(v) \ | ||
| 190 | (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL) | ||
| 191 | #define BP_CLKCTRL_CPU_RSRVD3 13 | ||
| 192 | #define BM_CLKCTRL_CPU_RSRVD3 0x0000E000 | ||
| 193 | #define BF_CLKCTRL_CPU_RSRVD3(v) \ | ||
| 194 | (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3) | ||
| 195 | #define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000 | ||
| 196 | #define BM_CLKCTRL_CPU_RSRVD2 0x00000800 | ||
| 197 | #define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400 | ||
| 198 | #define BP_CLKCTRL_CPU_RSRVD1 6 | ||
| 199 | #define BM_CLKCTRL_CPU_RSRVD1 0x000003C0 | ||
| 200 | #define BF_CLKCTRL_CPU_RSRVD1(v) \ | ||
| 201 | (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1) | ||
| 202 | #define BP_CLKCTRL_CPU_DIV_CPU 0 | ||
| 203 | #define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F | ||
| 204 | #define BF_CLKCTRL_CPU_DIV_CPU(v) \ | ||
| 205 | (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU) | ||
| 206 | |||
| 207 | #define HW_CLKCTRL_HBUS (0x00000060) | ||
| 208 | #define HW_CLKCTRL_HBUS_SET (0x00000064) | ||
| 209 | #define HW_CLKCTRL_HBUS_CLR (0x00000068) | ||
| 210 | #define HW_CLKCTRL_HBUS_TOG (0x0000006c) | ||
| 211 | |||
| 212 | #define BM_CLKCTRL_HBUS_ASM_BUSY 0x80000000 | ||
| 213 | #define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x40000000 | ||
| 214 | #define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x20000000 | ||
| 215 | #define BM_CLKCTRL_HBUS_RSRVD2 0x10000000 | ||
| 216 | #define BM_CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE 0x08000000 | ||
| 217 | #define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000 | ||
| 218 | #define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000 | ||
| 219 | #define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x01000000 | ||
| 220 | #define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x00800000 | ||
| 221 | #define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000 | ||
| 222 | #define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000 | ||
| 223 | #define BM_CLKCTRL_HBUS_ASM_ENABLE 0x00100000 | ||
| 224 | #define BM_CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE 0x00080000 | ||
| 225 | #define BP_CLKCTRL_HBUS_SLOW_DIV 16 | ||
| 226 | #define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000 | ||
| 227 | #define BF_CLKCTRL_HBUS_SLOW_DIV(v) \ | ||
| 228 | (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV) | ||
| 229 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0 | ||
| 230 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1 | ||
| 231 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2 | ||
| 232 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 | ||
| 233 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4 | ||
| 234 | #define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5 | ||
| 235 | #define BP_CLKCTRL_HBUS_RSRVD1 6 | ||
| 236 | #define BM_CLKCTRL_HBUS_RSRVD1 0x0000FFC0 | ||
| 237 | #define BF_CLKCTRL_HBUS_RSRVD1(v) \ | ||
| 238 | (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1) | ||
| 239 | #define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020 | ||
| 240 | #define BP_CLKCTRL_HBUS_DIV 0 | ||
| 241 | #define BM_CLKCTRL_HBUS_DIV 0x0000001F | ||
| 242 | #define BF_CLKCTRL_HBUS_DIV(v) \ | ||
| 243 | (((v) << 0) & BM_CLKCTRL_HBUS_DIV) | ||
| 244 | |||
| 245 | #define HW_CLKCTRL_XBUS (0x00000070) | ||
| 246 | |||
| 247 | #define BM_CLKCTRL_XBUS_BUSY 0x80000000 | ||
| 248 | #define BP_CLKCTRL_XBUS_RSRVD1 12 | ||
| 249 | #define BM_CLKCTRL_XBUS_RSRVD1 0x7FFFF000 | ||
| 250 | #define BF_CLKCTRL_XBUS_RSRVD1(v) \ | ||
| 251 | (((v) << 12) & BM_CLKCTRL_XBUS_RSRVD1) | ||
| 252 | #define BM_CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE 0x00000800 | ||
| 253 | #define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400 | ||
| 254 | #define BP_CLKCTRL_XBUS_DIV 0 | ||
| 255 | #define BM_CLKCTRL_XBUS_DIV 0x000003FF | ||
| 256 | #define BF_CLKCTRL_XBUS_DIV(v) \ | ||
| 257 | (((v) << 0) & BM_CLKCTRL_XBUS_DIV) | ||
| 258 | |||
| 259 | #define HW_CLKCTRL_XTAL (0x00000080) | ||
| 260 | #define HW_CLKCTRL_XTAL_SET (0x00000084) | ||
| 261 | #define HW_CLKCTRL_XTAL_CLR (0x00000088) | ||
| 262 | #define HW_CLKCTRL_XTAL_TOG (0x0000008c) | ||
| 263 | |||
| 264 | #define BP_CLKCTRL_XTAL_UART_CLK_GATE 31 | ||
| 265 | #define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000 | ||
| 266 | #define BM_CLKCTRL_XTAL_RSRVD3 0x40000000 | ||
| 267 | #define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29 | ||
| 268 | #define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000 | ||
| 269 | #define BP_CLKCTRL_XTAL_RSRVD2 27 | ||
| 270 | #define BM_CLKCTRL_XTAL_RSRVD2 0x18000000 | ||
| 271 | #define BF_CLKCTRL_XTAL_RSRVD2(v) \ | ||
| 272 | (((v) << 27) & BM_CLKCTRL_XTAL_RSRVD2) | ||
| 273 | #define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26 | ||
| 274 | #define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000 | ||
| 275 | #define BP_CLKCTRL_XTAL_RSRVD1 2 | ||
| 276 | #define BM_CLKCTRL_XTAL_RSRVD1 0x03FFFFFC | ||
| 277 | #define BF_CLKCTRL_XTAL_RSRVD1(v) \ | ||
| 278 | (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1) | ||
| 279 | #define BP_CLKCTRL_XTAL_DIV_UART 0 | ||
| 280 | #define BM_CLKCTRL_XTAL_DIV_UART 0x00000003 | ||
| 281 | #define BF_CLKCTRL_XTAL_DIV_UART(v) \ | ||
| 282 | (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART) | ||
| 283 | |||
| 284 | #define HW_CLKCTRL_SSP0 (0x00000090) | ||
| 285 | |||
| 286 | #define BP_CLKCTRL_SSP0_CLKGATE 31 | ||
| 287 | #define BM_CLKCTRL_SSP0_CLKGATE 0x80000000 | ||
| 288 | #define BM_CLKCTRL_SSP0_RSRVD2 0x40000000 | ||
| 289 | #define BM_CLKCTRL_SSP0_BUSY 0x20000000 | ||
| 290 | #define BP_CLKCTRL_SSP0_RSRVD1 10 | ||
| 291 | #define BM_CLKCTRL_SSP0_RSRVD1 0x1FFFFC00 | ||
| 292 | #define BF_CLKCTRL_SSP0_RSRVD1(v) \ | ||
| 293 | (((v) << 10) & BM_CLKCTRL_SSP0_RSRVD1) | ||
| 294 | #define BM_CLKCTRL_SSP0_DIV_FRAC_EN 0x00000200 | ||
| 295 | #define BP_CLKCTRL_SSP0_DIV 0 | ||
| 296 | #define BM_CLKCTRL_SSP0_DIV 0x000001FF | ||
| 297 | #define BF_CLKCTRL_SSP0_DIV(v) \ | ||
| 298 | (((v) << 0) & BM_CLKCTRL_SSP0_DIV) | ||
| 299 | |||
| 300 | #define HW_CLKCTRL_SSP1 (0x000000a0) | ||
| 301 | |||
| 302 | #define BP_CLKCTRL_SSP1_CLKGATE 31 | ||
| 303 | #define BM_CLKCTRL_SSP1_CLKGATE 0x80000000 | ||
| 304 | #define BM_CLKCTRL_SSP1_RSRVD2 0x40000000 | ||
| 305 | #define BM_CLKCTRL_SSP1_BUSY 0x20000000 | ||
| 306 | #define BP_CLKCTRL_SSP1_RSRVD1 10 | ||
| 307 | #define BM_CLKCTRL_SSP1_RSRVD1 0x1FFFFC00 | ||
| 308 | #define BF_CLKCTRL_SSP1_RSRVD1(v) \ | ||
| 309 | (((v) << 10) & BM_CLKCTRL_SSP1_RSRVD1) | ||
| 310 | #define BM_CLKCTRL_SSP1_DIV_FRAC_EN 0x00000200 | ||
| 311 | #define BP_CLKCTRL_SSP1_DIV 0 | ||
| 312 | #define BM_CLKCTRL_SSP1_DIV 0x000001FF | ||
| 313 | #define BF_CLKCTRL_SSP1_DIV(v) \ | ||
| 314 | (((v) << 0) & BM_CLKCTRL_SSP1_DIV) | ||
| 315 | |||
| 316 | #define HW_CLKCTRL_SSP2 (0x000000b0) | ||
| 317 | |||
| 318 | #define BP_CLKCTRL_SSP2_CLKGATE 31 | ||
| 319 | #define BM_CLKCTRL_SSP2_CLKGATE 0x80000000 | ||
| 320 | #define BM_CLKCTRL_SSP2_RSRVD2 0x40000000 | ||
| 321 | #define BM_CLKCTRL_SSP2_BUSY 0x20000000 | ||
| 322 | #define BP_CLKCTRL_SSP2_RSRVD1 10 | ||
| 323 | #define BM_CLKCTRL_SSP2_RSRVD1 0x1FFFFC00 | ||
| 324 | #define BF_CLKCTRL_SSP2_RSRVD1(v) \ | ||
| 325 | (((v) << 10) & BM_CLKCTRL_SSP2_RSRVD1) | ||
| 326 | #define BM_CLKCTRL_SSP2_DIV_FRAC_EN 0x00000200 | ||
| 327 | #define BP_CLKCTRL_SSP2_DIV 0 | ||
| 328 | #define BM_CLKCTRL_SSP2_DIV 0x000001FF | ||
| 329 | #define BF_CLKCTRL_SSP2_DIV(v) \ | ||
| 330 | (((v) << 0) & BM_CLKCTRL_SSP2_DIV) | ||
| 331 | |||
| 332 | #define HW_CLKCTRL_SSP3 (0x000000c0) | ||
| 333 | |||
| 334 | #define BP_CLKCTRL_SSP3_CLKGATE 31 | ||
| 335 | #define BM_CLKCTRL_SSP3_CLKGATE 0x80000000 | ||
| 336 | #define BM_CLKCTRL_SSP3_RSRVD2 0x40000000 | ||
| 337 | #define BM_CLKCTRL_SSP3_BUSY 0x20000000 | ||
| 338 | #define BP_CLKCTRL_SSP3_RSRVD1 10 | ||
| 339 | #define BM_CLKCTRL_SSP3_RSRVD1 0x1FFFFC00 | ||
| 340 | #define BF_CLKCTRL_SSP3_RSRVD1(v) \ | ||
| 341 | (((v) << 10) & BM_CLKCTRL_SSP3_RSRVD1) | ||
| 342 | #define BM_CLKCTRL_SSP3_DIV_FRAC_EN 0x00000200 | ||
| 343 | #define BP_CLKCTRL_SSP3_DIV 0 | ||
| 344 | #define BM_CLKCTRL_SSP3_DIV 0x000001FF | ||
| 345 | #define BF_CLKCTRL_SSP3_DIV(v) \ | ||
| 346 | (((v) << 0) & BM_CLKCTRL_SSP3_DIV) | ||
| 347 | |||
| 348 | #define HW_CLKCTRL_GPMI (0x000000d0) | ||
| 349 | |||
| 350 | #define BP_CLKCTRL_GPMI_CLKGATE 31 | ||
| 351 | #define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 | ||
| 352 | #define BM_CLKCTRL_GPMI_RSRVD2 0x40000000 | ||
| 353 | #define BM_CLKCTRL_GPMI_BUSY 0x20000000 | ||
| 354 | #define BP_CLKCTRL_GPMI_RSRVD1 11 | ||
| 355 | #define BM_CLKCTRL_GPMI_RSRVD1 0x1FFFF800 | ||
| 356 | #define BF_CLKCTRL_GPMI_RSRVD1(v) \ | ||
| 357 | (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1) | ||
| 358 | #define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400 | ||
| 359 | #define BP_CLKCTRL_GPMI_DIV 0 | ||
| 360 | #define BM_CLKCTRL_GPMI_DIV 0x000003FF | ||
| 361 | #define BF_CLKCTRL_GPMI_DIV(v) \ | ||
| 362 | (((v) << 0) & BM_CLKCTRL_GPMI_DIV) | ||
| 363 | |||
| 364 | #define HW_CLKCTRL_SPDIF (0x000000e0) | ||
| 365 | |||
| 366 | #define BP_CLKCTRL_SPDIF_CLKGATE 31 | ||
| 367 | #define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 | ||
| 368 | #define BP_CLKCTRL_SPDIF_RSRVD 0 | ||
| 369 | #define BM_CLKCTRL_SPDIF_RSRVD 0x7FFFFFFF | ||
| 370 | #define BF_CLKCTRL_SPDIF_RSRVD(v) \ | ||
| 371 | (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD) | ||
| 372 | |||
| 373 | #define HW_CLKCTRL_EMI (0x000000f0) | ||
| 374 | |||
| 375 | #define BP_CLKCTRL_EMI_CLKGATE 31 | ||
| 376 | #define BM_CLKCTRL_EMI_CLKGATE 0x80000000 | ||
| 377 | #define BM_CLKCTRL_EMI_SYNC_MODE_EN 0x40000000 | ||
| 378 | #define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000 | ||
| 379 | #define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 | ||
| 380 | #define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000 | ||
| 381 | #define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000 | ||
| 382 | #define BP_CLKCTRL_EMI_RSRVD3 18 | ||
| 383 | #define BM_CLKCTRL_EMI_RSRVD3 0x03FC0000 | ||
| 384 | #define BF_CLKCTRL_EMI_RSRVD3(v) \ | ||
| 385 | (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3) | ||
| 386 | #define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000 | ||
| 387 | #define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000 | ||
| 388 | #define BP_CLKCTRL_EMI_RSRVD2 12 | ||
| 389 | #define BM_CLKCTRL_EMI_RSRVD2 0x0000F000 | ||
| 390 | #define BF_CLKCTRL_EMI_RSRVD2(v) \ | ||
| 391 | (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2) | ||
| 392 | #define BP_CLKCTRL_EMI_DIV_XTAL 8 | ||
| 393 | #define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00 | ||
| 394 | #define BF_CLKCTRL_EMI_DIV_XTAL(v) \ | ||
| 395 | (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL) | ||
| 396 | #define BP_CLKCTRL_EMI_RSRVD1 6 | ||
| 397 | #define BM_CLKCTRL_EMI_RSRVD1 0x000000C0 | ||
| 398 | #define BF_CLKCTRL_EMI_RSRVD1(v) \ | ||
| 399 | (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1) | ||
| 400 | #define BP_CLKCTRL_EMI_DIV_EMI 0 | ||
| 401 | #define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F | ||
| 402 | #define BF_CLKCTRL_EMI_DIV_EMI(v) \ | ||
| 403 | (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI) | ||
| 404 | |||
| 405 | #define HW_CLKCTRL_SAIF0 (0x00000100) | ||
| 406 | |||
| 407 | #define BP_CLKCTRL_SAIF0_CLKGATE 31 | ||
| 408 | #define BM_CLKCTRL_SAIF0_CLKGATE 0x80000000 | ||
| 409 | #define BM_CLKCTRL_SAIF0_RSRVD2 0x40000000 | ||
| 410 | #define BM_CLKCTRL_SAIF0_BUSY 0x20000000 | ||
| 411 | #define BP_CLKCTRL_SAIF0_RSRVD1 17 | ||
| 412 | #define BM_CLKCTRL_SAIF0_RSRVD1 0x1FFE0000 | ||
| 413 | #define BF_CLKCTRL_SAIF0_RSRVD1(v) \ | ||
| 414 | (((v) << 17) & BM_CLKCTRL_SAIF0_RSRVD1) | ||
| 415 | #define BM_CLKCTRL_SAIF0_DIV_FRAC_EN 0x00010000 | ||
| 416 | #define BP_CLKCTRL_SAIF0_DIV 0 | ||
| 417 | #define BM_CLKCTRL_SAIF0_DIV 0x0000FFFF | ||
| 418 | #define BF_CLKCTRL_SAIF0_DIV(v) \ | ||
| 419 | (((v) << 0) & BM_CLKCTRL_SAIF0_DIV) | ||
| 420 | |||
| 421 | #define HW_CLKCTRL_SAIF1 (0x00000110) | ||
| 422 | |||
| 423 | #define BP_CLKCTRL_SAIF1_CLKGATE 31 | ||
| 424 | #define BM_CLKCTRL_SAIF1_CLKGATE 0x80000000 | ||
| 425 | #define BM_CLKCTRL_SAIF1_RSRVD2 0x40000000 | ||
| 426 | #define BM_CLKCTRL_SAIF1_BUSY 0x20000000 | ||
| 427 | #define BP_CLKCTRL_SAIF1_RSRVD1 17 | ||
| 428 | #define BM_CLKCTRL_SAIF1_RSRVD1 0x1FFE0000 | ||
| 429 | #define BF_CLKCTRL_SAIF1_RSRVD1(v) \ | ||
| 430 | (((v) << 17) & BM_CLKCTRL_SAIF1_RSRVD1) | ||
| 431 | #define BM_CLKCTRL_SAIF1_DIV_FRAC_EN 0x00010000 | ||
| 432 | #define BP_CLKCTRL_SAIF1_DIV 0 | ||
| 433 | #define BM_CLKCTRL_SAIF1_DIV 0x0000FFFF | ||
| 434 | #define BF_CLKCTRL_SAIF1_DIV(v) \ | ||
| 435 | (((v) << 0) & BM_CLKCTRL_SAIF1_DIV) | ||
| 436 | |||
| 437 | #define HW_CLKCTRL_DIS_LCDIF (0x00000120) | ||
| 438 | |||
| 439 | #define BP_CLKCTRL_DIS_LCDIF_CLKGATE 31 | ||
| 440 | #define BM_CLKCTRL_DIS_LCDIF_CLKGATE 0x80000000 | ||
| 441 | #define BM_CLKCTRL_DIS_LCDIF_RSRVD2 0x40000000 | ||
| 442 | #define BM_CLKCTRL_DIS_LCDIF_BUSY 0x20000000 | ||
| 443 | #define BP_CLKCTRL_DIS_LCDIF_RSRVD1 14 | ||
| 444 | #define BM_CLKCTRL_DIS_LCDIF_RSRVD1 0x1FFFC000 | ||
| 445 | #define BF_CLKCTRL_DIS_LCDIF_RSRVD1(v) \ | ||
| 446 | (((v) << 14) & BM_CLKCTRL_DIS_LCDIF_RSRVD1) | ||
| 447 | #define BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN 0x00002000 | ||
| 448 | #define BP_CLKCTRL_DIS_LCDIF_DIV 0 | ||
| 449 | #define BM_CLKCTRL_DIS_LCDIF_DIV 0x00001FFF | ||
| 450 | #define BF_CLKCTRL_DIS_LCDIF_DIV(v) \ | ||
| 451 | (((v) << 0) & BM_CLKCTRL_DIS_LCDIF_DIV) | ||
| 452 | |||
| 453 | #define HW_CLKCTRL_ETM (0x00000130) | ||
| 454 | |||
| 455 | #define BM_CLKCTRL_ETM_CLKGATE 0x80000000 | ||
| 456 | #define BM_CLKCTRL_ETM_RSRVD2 0x40000000 | ||
| 457 | #define BM_CLKCTRL_ETM_BUSY 0x20000000 | ||
| 458 | #define BP_CLKCTRL_ETM_RSRVD1 8 | ||
| 459 | #define BM_CLKCTRL_ETM_RSRVD1 0x1FFFFF00 | ||
| 460 | #define BF_CLKCTRL_ETM_RSRVD1(v) \ | ||
| 461 | (((v) << 8) & BM_CLKCTRL_ETM_RSRVD1) | ||
| 462 | #define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000080 | ||
| 463 | #define BP_CLKCTRL_ETM_DIV 0 | ||
| 464 | #define BM_CLKCTRL_ETM_DIV 0x0000007F | ||
| 465 | #define BF_CLKCTRL_ETM_DIV(v) \ | ||
| 466 | (((v) << 0) & BM_CLKCTRL_ETM_DIV) | ||
| 467 | |||
| 468 | #define HW_CLKCTRL_ENET (0x00000140) | ||
| 469 | |||
| 470 | #define BM_CLKCTRL_ENET_SLEEP 0x80000000 | ||
| 471 | #define BP_CLKCTRL_ENET_DISABLE 30 | ||
| 472 | #define BM_CLKCTRL_ENET_DISABLE 0x40000000 | ||
| 473 | #define BM_CLKCTRL_ENET_STATUS 0x20000000 | ||
| 474 | #define BM_CLKCTRL_ENET_RSRVD1 0x10000000 | ||
| 475 | #define BM_CLKCTRL_ENET_BUSY_TIME 0x08000000 | ||
| 476 | #define BP_CLKCTRL_ENET_DIV_TIME 21 | ||
| 477 | #define BM_CLKCTRL_ENET_DIV_TIME 0x07E00000 | ||
| 478 | #define BF_CLKCTRL_ENET_DIV_TIME(v) \ | ||
| 479 | (((v) << 21) & BM_CLKCTRL_ENET_DIV_TIME) | ||
| 480 | #define BM_CLKCTRL_ENET_BUSY 0x08000000 | ||
| 481 | #define BP_CLKCTRL_ENET_DIV 21 | ||
| 482 | #define BM_CLKCTRL_ENET_DIV 0x07E00000 | ||
| 483 | #define BF_CLKCTRL_ENET_DIV(v) \ | ||
| 484 | (((v) << 21) & BM_CLKCTRL_ENET_DIV) | ||
| 485 | #define BP_CLKCTRL_ENET_TIME_SEL 19 | ||
| 486 | #define BM_CLKCTRL_ENET_TIME_SEL 0x00180000 | ||
| 487 | #define BF_CLKCTRL_ENET_TIME_SEL(v) \ | ||
| 488 | (((v) << 19) & BM_CLKCTRL_ENET_TIME_SEL) | ||
| 489 | #define BV_CLKCTRL_ENET_TIME_SEL__XTAL 0x0 | ||
| 490 | #define BV_CLKCTRL_ENET_TIME_SEL__PLL 0x1 | ||
| 491 | #define BV_CLKCTRL_ENET_TIME_SEL__RMII_CLK 0x2 | ||
| 492 | #define BV_CLKCTRL_ENET_TIME_SEL__UNDEFINED 0x3 | ||
| 493 | #define BM_CLKCTRL_ENET_CLK_OUT_EN 0x00040000 | ||
| 494 | #define BM_CLKCTRL_ENET_RESET_BY_SW_CHIP 0x00020000 | ||
| 495 | #define BM_CLKCTRL_ENET_RESET_BY_SW 0x00010000 | ||
| 496 | #define BP_CLKCTRL_ENET_RSRVD0 0 | ||
| 497 | #define BM_CLKCTRL_ENET_RSRVD0 0x0000FFFF | ||
| 498 | #define BF_CLKCTRL_ENET_RSRVD0(v) \ | ||
| 499 | (((v) << 0) & BM_CLKCTRL_ENET_RSRVD0) | ||
| 500 | |||
| 501 | #define HW_CLKCTRL_HSADC (0x00000150) | ||
| 502 | |||
| 503 | #define BM_CLKCTRL_HSADC_RSRVD2 0x80000000 | ||
| 504 | #define BM_CLKCTRL_HSADC_RESETB 0x40000000 | ||
| 505 | #define BP_CLKCTRL_HSADC_FREQDIV 28 | ||
| 506 | #define BM_CLKCTRL_HSADC_FREQDIV 0x30000000 | ||
| 507 | #define BF_CLKCTRL_HSADC_FREQDIV(v) \ | ||
| 508 | (((v) << 28) & BM_CLKCTRL_HSADC_FREQDIV) | ||
| 509 | #define BP_CLKCTRL_HSADC_RSRVD1 0 | ||
| 510 | #define BM_CLKCTRL_HSADC_RSRVD1 0x0FFFFFFF | ||
| 511 | #define BF_CLKCTRL_HSADC_RSRVD1(v) \ | ||
| 512 | (((v) << 0) & BM_CLKCTRL_HSADC_RSRVD1) | ||
| 513 | |||
| 514 | #define HW_CLKCTRL_FLEXCAN (0x00000160) | ||
| 515 | |||
| 516 | #define BM_CLKCTRL_FLEXCAN_RSRVD2 0x80000000 | ||
| 517 | #define BP_CLKCTRL_FLEXCAN_STOP_CAN0 30 | ||
| 518 | #define BM_CLKCTRL_FLEXCAN_STOP_CAN0 0x40000000 | ||
| 519 | #define BM_CLKCTRL_FLEXCAN_CAN0_STATUS 0x20000000 | ||
| 520 | #define BP_CLKCTRL_FLEXCAN_STOP_CAN1 28 | ||
| 521 | #define BM_CLKCTRL_FLEXCAN_STOP_CAN1 0x10000000 | ||
| 522 | #define BM_CLKCTRL_FLEXCAN_CAN1_STATUS 0x08000000 | ||
| 523 | #define BP_CLKCTRL_FLEXCAN_RSRVD1 0 | ||
| 524 | #define BM_CLKCTRL_FLEXCAN_RSRVD1 0x07FFFFFF | ||
| 525 | #define BF_CLKCTRL_FLEXCAN_RSRVD1(v) \ | ||
| 526 | (((v) << 0) & BM_CLKCTRL_FLEXCAN_RSRVD1) | ||
| 527 | |||
| 528 | #define HW_CLKCTRL_FRAC0 (0x000001b0) | ||
| 529 | #define HW_CLKCTRL_FRAC0_SET (0x000001b4) | ||
| 530 | #define HW_CLKCTRL_FRAC0_CLR (0x000001b8) | ||
| 531 | #define HW_CLKCTRL_FRAC0_TOG (0x000001bc) | ||
| 532 | |||
| 533 | #define BP_CLKCTRL_FRAC0_CLKGATEIO0 31 | ||
| 534 | #define BM_CLKCTRL_FRAC0_CLKGATEIO0 0x80000000 | ||
| 535 | #define BM_CLKCTRL_FRAC0_IO0_STABLE 0x40000000 | ||
| 536 | #define BP_CLKCTRL_FRAC0_IO0FRAC 24 | ||
| 537 | #define BM_CLKCTRL_FRAC0_IO0FRAC 0x3F000000 | ||
| 538 | #define BF_CLKCTRL_FRAC0_IO0FRAC(v) \ | ||
| 539 | (((v) << 24) & BM_CLKCTRL_FRAC0_IO0FRAC) | ||
| 540 | #define BP_CLKCTRL_FRAC0_CLKGATEIO1 23 | ||
| 541 | #define BM_CLKCTRL_FRAC0_CLKGATEIO1 0x00800000 | ||
| 542 | #define BM_CLKCTRL_FRAC0_IO1_STABLE 0x00400000 | ||
| 543 | #define BP_CLKCTRL_FRAC0_IO1FRAC 16 | ||
| 544 | #define BM_CLKCTRL_FRAC0_IO1FRAC 0x003F0000 | ||
| 545 | #define BF_CLKCTRL_FRAC0_IO1FRAC(v) \ | ||
| 546 | (((v) << 16) & BM_CLKCTRL_FRAC0_IO1FRAC) | ||
| 547 | #define BP_CLKCTRL_FRAC0_CLKGATEEMI 15 | ||
| 548 | #define BM_CLKCTRL_FRAC0_CLKGATEEMI 0x00008000 | ||
| 549 | #define BM_CLKCTRL_FRAC0_EMI_STABLE 0x00004000 | ||
| 550 | #define BP_CLKCTRL_FRAC0_EMIFRAC 8 | ||
| 551 | #define BM_CLKCTRL_FRAC0_EMIFRAC 0x00003F00 | ||
| 552 | #define BF_CLKCTRL_FRAC0_EMIFRAC(v) \ | ||
| 553 | (((v) << 8) & BM_CLKCTRL_FRAC0_EMIFRAC) | ||
| 554 | #define BP_CLKCTRL_FRAC0_CLKGATECPU 7 | ||
| 555 | #define BM_CLKCTRL_FRAC0_CLKGATECPU 0x00000080 | ||
| 556 | #define BM_CLKCTRL_FRAC0_CPU_STABLE 0x00000040 | ||
| 557 | #define BP_CLKCTRL_FRAC0_CPUFRAC 0 | ||
| 558 | #define BM_CLKCTRL_FRAC0_CPUFRAC 0x0000003F | ||
| 559 | #define BF_CLKCTRL_FRAC0_CPUFRAC(v) \ | ||
| 560 | (((v) << 0) & BM_CLKCTRL_FRAC0_CPUFRAC) | ||
| 561 | |||
| 562 | #define HW_CLKCTRL_FRAC1 (0x000001c0) | ||
| 563 | #define HW_CLKCTRL_FRAC1_SET (0x000001c4) | ||
| 564 | #define HW_CLKCTRL_FRAC1_CLR (0x000001c8) | ||
| 565 | #define HW_CLKCTRL_FRAC1_TOG (0x000001cc) | ||
| 566 | |||
| 567 | #define BP_CLKCTRL_FRAC1_RSRVD2 24 | ||
| 568 | #define BM_CLKCTRL_FRAC1_RSRVD2 0xFF000000 | ||
| 569 | #define BF_CLKCTRL_FRAC1_RSRVD2(v) \ | ||
| 570 | (((v) << 24) & BM_CLKCTRL_FRAC1_RSRVD2) | ||
| 571 | #define BP_CLKCTRL_FRAC1_CLKGATEGPMI 23 | ||
| 572 | #define BM_CLKCTRL_FRAC1_CLKGATEGPMI 0x00800000 | ||
| 573 | #define BM_CLKCTRL_FRAC1_GPMI_STABLE 0x00400000 | ||
| 574 | #define BP_CLKCTRL_FRAC1_GPMIFRAC 16 | ||
| 575 | #define BM_CLKCTRL_FRAC1_GPMIFRAC 0x003F0000 | ||
| 576 | #define BF_CLKCTRL_FRAC1_GPMIFRAC(v) \ | ||
| 577 | (((v) << 16) & BM_CLKCTRL_FRAC1_GPMIFRAC) | ||
| 578 | #define BP_CLKCTRL_FRAC1_CLKGATEHSADC 15 | ||
| 579 | #define BM_CLKCTRL_FRAC1_CLKGATEHSADC 0x00008000 | ||
| 580 | #define BM_CLKCTRL_FRAC1_HSADC_STABLE 0x00004000 | ||
| 581 | #define BP_CLKCTRL_FRAC1_HSADCFRAC 8 | ||
| 582 | #define BM_CLKCTRL_FRAC1_HSADCFRAC 0x00003F00 | ||
| 583 | #define BF_CLKCTRL_FRAC1_HSADCFRAC(v) \ | ||
| 584 | (((v) << 8) & BM_CLKCTRL_FRAC1_HSADCFRAC) | ||
| 585 | #define BP_CLKCTRL_FRAC1_CLKGATEPIX 7 | ||
| 586 | #define BM_CLKCTRL_FRAC1_CLKGATEPIX 0x00000080 | ||
| 587 | #define BM_CLKCTRL_FRAC1_PIX_STABLE 0x00000040 | ||
| 588 | #define BP_CLKCTRL_FRAC1_PIXFRAC 0 | ||
| 589 | #define BM_CLKCTRL_FRAC1_PIXFRAC 0x0000003F | ||
| 590 | #define BF_CLKCTRL_FRAC1_PIXFRAC(v) \ | ||
| 591 | (((v) << 0) & BM_CLKCTRL_FRAC1_PIXFRAC) | ||
| 592 | |||
| 593 | #define HW_CLKCTRL_CLKSEQ (0x000001d0) | ||
| 594 | #define HW_CLKCTRL_CLKSEQ_SET (0x000001d4) | ||
| 595 | #define HW_CLKCTRL_CLKSEQ_CLR (0x000001d8) | ||
| 596 | #define HW_CLKCTRL_CLKSEQ_TOG (0x000001dc) | ||
| 597 | |||
| 598 | #define BP_CLKCTRL_CLKSEQ_RSRVD0 19 | ||
| 599 | #define BM_CLKCTRL_CLKSEQ_RSRVD0 0xFFF80000 | ||
| 600 | #define BF_CLKCTRL_CLKSEQ_RSRVD0(v) \ | ||
| 601 | (((v) << 19) & BM_CLKCTRL_CLKSEQ_RSRVD0) | ||
| 602 | #define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00040000 | ||
| 603 | #define BP_CLKCTRL_CLKSEQ_RSRVD1 15 | ||
| 604 | #define BM_CLKCTRL_CLKSEQ_RSRVD1 0x00038000 | ||
| 605 | #define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \ | ||
| 606 | (((v) << 15) & BM_CLKCTRL_CLKSEQ_RSRVD1) | ||
| 607 | #define BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF 0x00004000 | ||
| 608 | #define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__BYPASS 0x1 | ||
| 609 | #define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__PFD 0x0 | ||
| 610 | #define BP_CLKCTRL_CLKSEQ_RSRVD2 9 | ||
| 611 | #define BM_CLKCTRL_CLKSEQ_RSRVD2 0x00003E00 | ||
| 612 | #define BF_CLKCTRL_CLKSEQ_RSRVD2(v) \ | ||
| 613 | (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD2) | ||
| 614 | #define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100 | ||
| 615 | #define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000080 | ||
| 616 | #define BM_CLKCTRL_CLKSEQ_BYPASS_SSP3 0x00000040 | ||
| 617 | #define BM_CLKCTRL_CLKSEQ_BYPASS_SSP2 0x00000020 | ||
| 618 | #define BM_CLKCTRL_CLKSEQ_BYPASS_SSP1 0x00000010 | ||
| 619 | #define BM_CLKCTRL_CLKSEQ_BYPASS_SSP0 0x00000008 | ||
| 620 | #define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000004 | ||
| 621 | #define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1 0x00000002 | ||
| 622 | #define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0 0x00000001 | ||
| 623 | |||
| 624 | #define HW_CLKCTRL_RESET (0x000001e0) | ||
| 625 | |||
| 626 | #define BP_CLKCTRL_RESET_RSRVD 6 | ||
| 627 | #define BM_CLKCTRL_RESET_RSRVD 0xFFFFFFC0 | ||
| 628 | #define BF_CLKCTRL_RESET_RSRVD(v) \ | ||
| 629 | (((v) << 6) & BM_CLKCTRL_RESET_RSRVD) | ||
| 630 | #define BM_CLKCTRL_RESET_WDOG_POR_DISABLE 0x00000020 | ||
| 631 | #define BM_CLKCTRL_RESET_EXTERNAL_RESET_ENABLE 0x00000010 | ||
| 632 | #define BM_CLKCTRL_RESET_THERMAL_RESET_ENABLE 0x00000008 | ||
| 633 | #define BM_CLKCTRL_RESET_THERMAL_RESET_DEFAULT 0x00000004 | ||
| 634 | #define BM_CLKCTRL_RESET_CHIP 0x00000002 | ||
| 635 | #define BM_CLKCTRL_RESET_DIG 0x00000001 | ||
| 636 | |||
| 637 | #define HW_CLKCTRL_STATUS (0x000001f0) | ||
| 638 | |||
| 639 | #define BP_CLKCTRL_STATUS_CPU_LIMIT 30 | ||
| 640 | #define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000 | ||
| 641 | #define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \ | ||
| 642 | (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT) | ||
| 643 | #define BP_CLKCTRL_STATUS_RSRVD 0 | ||
| 644 | #define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF | ||
| 645 | #define BF_CLKCTRL_STATUS_RSRVD(v) \ | ||
| 646 | (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD) | ||
| 647 | |||
| 648 | #define HW_CLKCTRL_VERSION (0x00000200) | ||
| 649 | |||
| 650 | #define BP_CLKCTRL_VERSION_MAJOR 24 | ||
| 651 | #define BM_CLKCTRL_VERSION_MAJOR 0xFF000000 | ||
| 652 | #define BF_CLKCTRL_VERSION_MAJOR(v) \ | ||
| 653 | (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR) | ||
| 654 | #define BP_CLKCTRL_VERSION_MINOR 16 | ||
| 655 | #define BM_CLKCTRL_VERSION_MINOR 0x00FF0000 | ||
| 656 | #define BF_CLKCTRL_VERSION_MINOR(v) \ | ||
| 657 | (((v) << 16) & BM_CLKCTRL_VERSION_MINOR) | ||
| 658 | #define BP_CLKCTRL_VERSION_STEP 0 | ||
| 659 | #define BM_CLKCTRL_VERSION_STEP 0x0000FFFF | ||
| 660 | #define BF_CLKCTRL_VERSION_STEP(v) \ | ||
| 661 | (((v) << 0) & BM_CLKCTRL_VERSION_STEP) | ||
| 662 | |||
| 663 | #endif /* __REGS_CLKCTRL_MX28_H__ */ | ||
diff --git a/arch/arm/mach-mxs/system.c b/arch/arm/mach-mxs/system.c new file mode 100644 index 000000000000..9343d7edd4f6 --- /dev/null +++ b/arch/arm/mach-mxs/system.c | |||
| @@ -0,0 +1,137 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 1999 ARM Limited | ||
| 3 | * Copyright (C) 2000 Deep Blue Solutions Ltd | ||
| 4 | * Copyright 2006-2007,2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 5 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | ||
| 6 | * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/kernel.h> | ||
| 20 | #include <linux/clk.h> | ||
| 21 | #include <linux/io.h> | ||
| 22 | #include <linux/err.h> | ||
| 23 | #include <linux/delay.h> | ||
| 24 | #include <linux/init.h> | ||
| 25 | |||
| 26 | #include <asm/proc-fns.h> | ||
| 27 | #include <asm/system.h> | ||
| 28 | |||
| 29 | #include <mach/mxs.h> | ||
| 30 | #include <mach/common.h> | ||
| 31 | |||
| 32 | #define MX23_CLKCTRL_RESET_OFFSET 0x120 | ||
| 33 | #define MX28_CLKCTRL_RESET_OFFSET 0x1e0 | ||
| 34 | #define MXS_CLKCTRL_RESET_CHIP (1 << 1) | ||
| 35 | |||
| 36 | #define MXS_MODULE_CLKGATE (1 << 30) | ||
| 37 | #define MXS_MODULE_SFTRST (1 << 31) | ||
| 38 | |||
| 39 | static void __iomem *mxs_clkctrl_reset_addr; | ||
| 40 | |||
| 41 | /* | ||
| 42 | * Reset the system. It is called by machine_restart(). | ||
| 43 | */ | ||
| 44 | void arch_reset(char mode, const char *cmd) | ||
| 45 | { | ||
| 46 | /* reset the chip */ | ||
| 47 | __mxs_setl(MXS_CLKCTRL_RESET_CHIP, mxs_clkctrl_reset_addr); | ||
| 48 | |||
| 49 | pr_err("Failed to assert the chip reset\n"); | ||
| 50 | |||
| 51 | /* Delay to allow the serial port to show the message */ | ||
| 52 | mdelay(50); | ||
| 53 | |||
| 54 | /* We'll take a jump through zero as a poor second */ | ||
| 55 | cpu_reset(0); | ||
| 56 | } | ||
| 57 | |||
| 58 | static int __init mxs_arch_reset_init(void) | ||
| 59 | { | ||
| 60 | struct clk *clk; | ||
| 61 | |||
| 62 | mxs_clkctrl_reset_addr = MXS_IO_ADDRESS(MXS_CLKCTRL_BASE_ADDR) + | ||
| 63 | (cpu_is_mx23() ? MX23_CLKCTRL_RESET_OFFSET : | ||
| 64 | MX28_CLKCTRL_RESET_OFFSET); | ||
| 65 | |||
| 66 | clk = clk_get_sys("rtc", NULL); | ||
| 67 | if (!IS_ERR(clk)) | ||
| 68 | clk_enable(clk); | ||
| 69 | |||
| 70 | return 0; | ||
| 71 | } | ||
| 72 | core_initcall(mxs_arch_reset_init); | ||
| 73 | |||
| 74 | /* | ||
| 75 | * Clear the bit and poll it cleared. This is usually called with | ||
| 76 | * a reset address and mask being either SFTRST(bit 31) or CLKGATE | ||
| 77 | * (bit 30). | ||
| 78 | */ | ||
| 79 | static int clear_poll_bit(void __iomem *addr, u32 mask) | ||
| 80 | { | ||
| 81 | int timeout = 0x400; | ||
| 82 | |||
| 83 | /* clear the bit */ | ||
| 84 | __mxs_clrl(mask, addr); | ||
| 85 | |||
| 86 | /* | ||
| 87 | * SFTRST needs 3 GPMI clocks to settle, the reference manual | ||
| 88 | * recommends to wait 1us. | ||
| 89 | */ | ||
| 90 | udelay(1); | ||
| 91 | |||
| 92 | /* poll the bit becoming clear */ | ||
| 93 | while ((__raw_readl(addr) & mask) && --timeout) | ||
| 94 | /* nothing */; | ||
| 95 | |||
| 96 | return !timeout; | ||
| 97 | } | ||
| 98 | |||
| 99 | int mxs_reset_block(void __iomem *reset_addr) | ||
| 100 | { | ||
| 101 | int ret; | ||
| 102 | int timeout = 0x400; | ||
| 103 | |||
| 104 | /* clear and poll SFTRST */ | ||
| 105 | ret = clear_poll_bit(reset_addr, MXS_MODULE_SFTRST); | ||
| 106 | if (unlikely(ret)) | ||
| 107 | goto error; | ||
| 108 | |||
| 109 | /* clear CLKGATE */ | ||
| 110 | __mxs_clrl(MXS_MODULE_CLKGATE, reset_addr); | ||
| 111 | |||
| 112 | /* set SFTRST to reset the block */ | ||
| 113 | __mxs_setl(MXS_MODULE_SFTRST, reset_addr); | ||
| 114 | udelay(1); | ||
| 115 | |||
| 116 | /* poll CLKGATE becoming set */ | ||
| 117 | while ((!(__raw_readl(reset_addr) & MXS_MODULE_CLKGATE)) && --timeout) | ||
| 118 | /* nothing */; | ||
| 119 | if (unlikely(!timeout)) | ||
| 120 | goto error; | ||
| 121 | |||
| 122 | /* clear and poll SFTRST */ | ||
| 123 | ret = clear_poll_bit(reset_addr, MXS_MODULE_SFTRST); | ||
| 124 | if (unlikely(ret)) | ||
| 125 | goto error; | ||
| 126 | |||
| 127 | /* clear and poll CLKGATE */ | ||
| 128 | ret = clear_poll_bit(reset_addr, MXS_MODULE_CLKGATE); | ||
| 129 | if (unlikely(ret)) | ||
| 130 | goto error; | ||
| 131 | |||
| 132 | return 0; | ||
| 133 | |||
| 134 | error: | ||
| 135 | pr_err("%s(%p): module reset timeout\n", __func__, reset_addr); | ||
| 136 | return -ETIMEDOUT; | ||
| 137 | } | ||
diff --git a/arch/arm/mach-mxs/timer.c b/arch/arm/mach-mxs/timer.c new file mode 100644 index 000000000000..13647f301860 --- /dev/null +++ b/arch/arm/mach-mxs/timer.c | |||
| @@ -0,0 +1,296 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2000-2001 Deep Blue Solutions | ||
| 3 | * Copyright (C) 2002 Shane Nay (shane@minirl.com) | ||
| 4 | * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com) | ||
| 5 | * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) | ||
| 6 | * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or | ||
| 9 | * modify it under the terms of the GNU General Public License | ||
| 10 | * as published by the Free Software Foundation; either version 2 | ||
| 11 | * of the License, or (at your option) any later version. | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 20 | * MA 02110-1301, USA. | ||
| 21 | */ | ||
| 22 | |||
| 23 | #include <linux/interrupt.h> | ||
| 24 | #include <linux/irq.h> | ||
| 25 | #include <linux/clockchips.h> | ||
| 26 | #include <linux/clk.h> | ||
| 27 | |||
| 28 | #include <asm/mach/time.h> | ||
| 29 | #include <mach/mxs.h> | ||
| 30 | #include <mach/common.h> | ||
| 31 | |||
| 32 | /* | ||
| 33 | * There are 2 versions of the timrot on Freescale MXS-based SoCs. | ||
| 34 | * The v1 on MX23 only gets 16 bits counter, while v2 on MX28 | ||
| 35 | * extends the counter to 32 bits. | ||
| 36 | * | ||
| 37 | * The implementation uses two timers, one for clock_event and | ||
| 38 | * another for clocksource. MX28 uses timrot 0 and 1, while MX23 | ||
| 39 | * uses 0 and 2. | ||
| 40 | */ | ||
| 41 | |||
| 42 | #define MX23_TIMROT_VERSION_OFFSET 0x0a0 | ||
| 43 | #define MX28_TIMROT_VERSION_OFFSET 0x120 | ||
| 44 | #define BP_TIMROT_MAJOR_VERSION 24 | ||
| 45 | #define BV_TIMROT_VERSION_1 0x01 | ||
| 46 | #define BV_TIMROT_VERSION_2 0x02 | ||
| 47 | #define timrot_is_v1() (timrot_major_version == BV_TIMROT_VERSION_1) | ||
| 48 | |||
| 49 | /* | ||
| 50 | * There are 4 registers for each timrotv2 instance, and 2 registers | ||
| 51 | * for each timrotv1. So address step 0x40 in macros below strides | ||
| 52 | * one instance of timrotv2 while two instances of timrotv1. | ||
| 53 | * | ||
| 54 | * As the result, HW_TIMROT_XXXn(1) defines the address of timrot1 | ||
| 55 | * on MX28 while timrot2 on MX23. | ||
| 56 | */ | ||
| 57 | /* common between v1 and v2 */ | ||
| 58 | #define HW_TIMROT_ROTCTRL 0x00 | ||
| 59 | #define HW_TIMROT_TIMCTRLn(n) (0x20 + (n) * 0x40) | ||
| 60 | /* v1 only */ | ||
| 61 | #define HW_TIMROT_TIMCOUNTn(n) (0x30 + (n) * 0x40) | ||
| 62 | /* v2 only */ | ||
| 63 | #define HW_TIMROT_RUNNING_COUNTn(n) (0x30 + (n) * 0x40) | ||
| 64 | #define HW_TIMROT_FIXED_COUNTn(n) (0x40 + (n) * 0x40) | ||
| 65 | |||
| 66 | #define BM_TIMROT_TIMCTRLn_RELOAD (1 << 6) | ||
| 67 | #define BM_TIMROT_TIMCTRLn_UPDATE (1 << 7) | ||
| 68 | #define BM_TIMROT_TIMCTRLn_IRQ_EN (1 << 14) | ||
| 69 | #define BM_TIMROT_TIMCTRLn_IRQ (1 << 15) | ||
| 70 | #define BP_TIMROT_TIMCTRLn_SELECT 0 | ||
| 71 | #define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL 0x8 | ||
| 72 | #define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL 0xb | ||
| 73 | |||
| 74 | static struct clock_event_device mxs_clockevent_device; | ||
| 75 | static enum clock_event_mode mxs_clockevent_mode = CLOCK_EVT_MODE_UNUSED; | ||
| 76 | |||
| 77 | static void __iomem *mxs_timrot_base = MXS_IO_ADDRESS(MXS_TIMROT_BASE_ADDR); | ||
| 78 | static u32 timrot_major_version; | ||
| 79 | |||
| 80 | static inline void timrot_irq_disable(void) | ||
| 81 | { | ||
| 82 | __mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ_EN, | ||
| 83 | mxs_timrot_base + HW_TIMROT_TIMCTRLn(0)); | ||
| 84 | } | ||
| 85 | |||
| 86 | static inline void timrot_irq_enable(void) | ||
| 87 | { | ||
| 88 | __mxs_setl(BM_TIMROT_TIMCTRLn_IRQ_EN, | ||
| 89 | mxs_timrot_base + HW_TIMROT_TIMCTRLn(0)); | ||
| 90 | } | ||
| 91 | |||
| 92 | static void timrot_irq_acknowledge(void) | ||
| 93 | { | ||
| 94 | __mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ, | ||
| 95 | mxs_timrot_base + HW_TIMROT_TIMCTRLn(0)); | ||
| 96 | } | ||
| 97 | |||
| 98 | static cycle_t timrotv1_get_cycles(struct clocksource *cs) | ||
| 99 | { | ||
| 100 | return ~((__raw_readl(mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1)) | ||
| 101 | & 0xffff0000) >> 16); | ||
| 102 | } | ||
| 103 | |||
| 104 | static cycle_t timrotv2_get_cycles(struct clocksource *cs) | ||
| 105 | { | ||
| 106 | return ~__raw_readl(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1)); | ||
| 107 | } | ||
| 108 | |||
| 109 | static int timrotv1_set_next_event(unsigned long evt, | ||
| 110 | struct clock_event_device *dev) | ||
| 111 | { | ||
| 112 | /* timrot decrements the count */ | ||
| 113 | __raw_writel(evt, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(0)); | ||
| 114 | |||
| 115 | return 0; | ||
| 116 | } | ||
| 117 | |||
| 118 | static int timrotv2_set_next_event(unsigned long evt, | ||
| 119 | struct clock_event_device *dev) | ||
| 120 | { | ||
| 121 | /* timrot decrements the count */ | ||
| 122 | __raw_writel(evt, mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(0)); | ||
| 123 | |||
| 124 | return 0; | ||
| 125 | } | ||
| 126 | |||
| 127 | static irqreturn_t mxs_timer_interrupt(int irq, void *dev_id) | ||
| 128 | { | ||
| 129 | struct clock_event_device *evt = dev_id; | ||
| 130 | |||
| 131 | timrot_irq_acknowledge(); | ||
| 132 | evt->event_handler(evt); | ||
| 133 | |||
| 134 | return IRQ_HANDLED; | ||
| 135 | } | ||
| 136 | |||
| 137 | static struct irqaction mxs_timer_irq = { | ||
| 138 | .name = "MXS Timer Tick", | ||
| 139 | .dev_id = &mxs_clockevent_device, | ||
| 140 | .flags = IRQF_TIMER | IRQF_IRQPOLL, | ||
| 141 | .handler = mxs_timer_interrupt, | ||
| 142 | }; | ||
| 143 | |||
| 144 | #ifdef DEBUG | ||
| 145 | static const char *clock_event_mode_label[] const = { | ||
| 146 | [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC", | ||
| 147 | [CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT", | ||
| 148 | [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN", | ||
| 149 | [CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED" | ||
| 150 | }; | ||
| 151 | #endif /* DEBUG */ | ||
| 152 | |||
| 153 | static void mxs_set_mode(enum clock_event_mode mode, | ||
| 154 | struct clock_event_device *evt) | ||
| 155 | { | ||
| 156 | /* Disable interrupt in timer module */ | ||
| 157 | timrot_irq_disable(); | ||
| 158 | |||
| 159 | if (mode != mxs_clockevent_mode) { | ||
| 160 | /* Set event time into the furthest future */ | ||
| 161 | if (timrot_is_v1()) | ||
| 162 | __raw_writel(0xffff, | ||
| 163 | mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1)); | ||
| 164 | else | ||
| 165 | __raw_writel(0xffffffff, | ||
| 166 | mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1)); | ||
| 167 | |||
| 168 | /* Clear pending interrupt */ | ||
| 169 | timrot_irq_acknowledge(); | ||
| 170 | } | ||
| 171 | |||
| 172 | #ifdef DEBUG | ||
| 173 | pr_info("%s: changing mode from %s to %s\n", __func__, | ||
| 174 | clock_event_mode_label[mxs_clockevent_mode], | ||
| 175 | clock_event_mode_label[mode]); | ||
| 176 | #endif /* DEBUG */ | ||
| 177 | |||
| 178 | /* Remember timer mode */ | ||
| 179 | mxs_clockevent_mode = mode; | ||
| 180 | |||
| 181 | switch (mode) { | ||
| 182 | case CLOCK_EVT_MODE_PERIODIC: | ||
| 183 | pr_err("%s: Periodic mode is not implemented\n", __func__); | ||
| 184 | break; | ||
| 185 | case CLOCK_EVT_MODE_ONESHOT: | ||
| 186 | timrot_irq_enable(); | ||
| 187 | break; | ||
| 188 | case CLOCK_EVT_MODE_SHUTDOWN: | ||
| 189 | case CLOCK_EVT_MODE_UNUSED: | ||
| 190 | case CLOCK_EVT_MODE_RESUME: | ||
| 191 | /* Left event sources disabled, no more interrupts appear */ | ||
| 192 | break; | ||
| 193 | } | ||
| 194 | } | ||
| 195 | |||
| 196 | static struct clock_event_device mxs_clockevent_device = { | ||
| 197 | .name = "mxs_timrot", | ||
| 198 | .features = CLOCK_EVT_FEAT_ONESHOT, | ||
| 199 | .shift = 32, | ||
| 200 | .set_mode = mxs_set_mode, | ||
| 201 | .set_next_event = timrotv2_set_next_event, | ||
| 202 | .rating = 200, | ||
| 203 | }; | ||
| 204 | |||
| 205 | static int __init mxs_clockevent_init(struct clk *timer_clk) | ||
| 206 | { | ||
| 207 | unsigned int c = clk_get_rate(timer_clk); | ||
| 208 | |||
| 209 | mxs_clockevent_device.mult = | ||
| 210 | div_sc(c, NSEC_PER_SEC, mxs_clockevent_device.shift); | ||
| 211 | mxs_clockevent_device.cpumask = cpumask_of(0); | ||
| 212 | if (timrot_is_v1()) { | ||
| 213 | mxs_clockevent_device.set_next_event = timrotv1_set_next_event; | ||
| 214 | mxs_clockevent_device.max_delta_ns = | ||
| 215 | clockevent_delta2ns(0xfffe, &mxs_clockevent_device); | ||
| 216 | mxs_clockevent_device.min_delta_ns = | ||
| 217 | clockevent_delta2ns(0xf, &mxs_clockevent_device); | ||
| 218 | } else { | ||
| 219 | mxs_clockevent_device.max_delta_ns = | ||
| 220 | clockevent_delta2ns(0xfffffffe, &mxs_clockevent_device); | ||
| 221 | mxs_clockevent_device.min_delta_ns = | ||
| 222 | clockevent_delta2ns(0xf, &mxs_clockevent_device); | ||
| 223 | } | ||
| 224 | |||
| 225 | clockevents_register_device(&mxs_clockevent_device); | ||
| 226 | |||
| 227 | return 0; | ||
| 228 | } | ||
| 229 | |||
| 230 | static struct clocksource clocksource_mxs = { | ||
| 231 | .name = "mxs_timer", | ||
| 232 | .rating = 200, | ||
| 233 | .read = timrotv2_get_cycles, | ||
| 234 | .mask = CLOCKSOURCE_MASK(32), | ||
| 235 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | ||
| 236 | }; | ||
| 237 | |||
| 238 | static int __init mxs_clocksource_init(struct clk *timer_clk) | ||
| 239 | { | ||
| 240 | unsigned int c = clk_get_rate(timer_clk); | ||
| 241 | |||
| 242 | if (timrot_is_v1()) { | ||
| 243 | clocksource_mxs.read = timrotv1_get_cycles; | ||
| 244 | clocksource_mxs.mask = CLOCKSOURCE_MASK(16); | ||
| 245 | } | ||
| 246 | |||
| 247 | clocksource_register_hz(&clocksource_mxs, c); | ||
| 248 | |||
| 249 | return 0; | ||
| 250 | } | ||
| 251 | |||
| 252 | void __init mxs_timer_init(struct clk *timer_clk, int irq) | ||
| 253 | { | ||
| 254 | clk_enable(timer_clk); | ||
| 255 | |||
| 256 | /* | ||
| 257 | * Initialize timers to a known state | ||
| 258 | */ | ||
| 259 | mxs_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL); | ||
| 260 | |||
| 261 | /* get timrot version */ | ||
| 262 | timrot_major_version = __raw_readl(mxs_timrot_base + | ||
| 263 | (cpu_is_mx23() ? MX23_TIMROT_VERSION_OFFSET : | ||
| 264 | MX28_TIMROT_VERSION_OFFSET)); | ||
| 265 | timrot_major_version >>= BP_TIMROT_MAJOR_VERSION; | ||
| 266 | |||
| 267 | /* one for clock_event */ | ||
| 268 | __raw_writel((timrot_is_v1() ? | ||
| 269 | BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL : | ||
| 270 | BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL) | | ||
| 271 | BM_TIMROT_TIMCTRLn_UPDATE | | ||
| 272 | BM_TIMROT_TIMCTRLn_IRQ_EN, | ||
| 273 | mxs_timrot_base + HW_TIMROT_TIMCTRLn(0)); | ||
| 274 | |||
| 275 | /* another for clocksource */ | ||
| 276 | __raw_writel((timrot_is_v1() ? | ||
| 277 | BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL : | ||
| 278 | BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL) | | ||
| 279 | BM_TIMROT_TIMCTRLn_RELOAD, | ||
| 280 | mxs_timrot_base + HW_TIMROT_TIMCTRLn(1)); | ||
| 281 | |||
| 282 | /* set clocksource timer fixed count to the maximum */ | ||
| 283 | if (timrot_is_v1()) | ||
| 284 | __raw_writel(0xffff, | ||
| 285 | mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1)); | ||
| 286 | else | ||
| 287 | __raw_writel(0xffffffff, | ||
| 288 | mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1)); | ||
| 289 | |||
| 290 | /* init and register the timer to the framework */ | ||
| 291 | mxs_clocksource_init(timer_clk); | ||
| 292 | mxs_clockevent_init(timer_clk); | ||
| 293 | |||
| 294 | /* Make irqs happen */ | ||
| 295 | setup_irq(irq, &mxs_timer_irq); | ||
| 296 | } | ||
diff --git a/arch/arm/mach-netx/time.c b/arch/arm/mach-netx/time.c index 82801dbf0579..f12f22d09b6c 100644 --- a/arch/arm/mach-netx/time.c +++ b/arch/arm/mach-netx/time.c | |||
| @@ -114,7 +114,6 @@ static struct clocksource clocksource_netx = { | |||
| 114 | .rating = 200, | 114 | .rating = 200, |
| 115 | .read = netx_get_cycles, | 115 | .read = netx_get_cycles, |
| 116 | .mask = CLOCKSOURCE_MASK(32), | 116 | .mask = CLOCKSOURCE_MASK(32), |
| 117 | .shift = 20, | ||
| 118 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 117 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 119 | }; | 118 | }; |
| 120 | 119 | ||
| @@ -151,9 +150,7 @@ static void __init netx_timer_init(void) | |||
| 151 | writel(NETX_GPIO_COUNTER_CTRL_RUN, | 150 | writel(NETX_GPIO_COUNTER_CTRL_RUN, |
| 152 | NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE)); | 151 | NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE)); |
| 153 | 152 | ||
| 154 | clocksource_netx.mult = | 153 | clocksource_register_hz(&clocksource_netx, CLOCK_TICK_RATE); |
| 155 | clocksource_hz2mult(CLOCK_TICK_RATE, clocksource_netx.shift); | ||
| 156 | clocksource_register(&clocksource_netx); | ||
| 157 | 154 | ||
| 158 | netx_clockevent.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, | 155 | netx_clockevent.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, |
| 159 | netx_clockevent.shift); | 156 | netx_clockevent.shift); |
diff --git a/arch/arm/mach-nomadik/clock.c b/arch/arm/mach-nomadik/clock.c index 89f793adf776..48a59f24e10c 100644 --- a/arch/arm/mach-nomadik/clock.c +++ b/arch/arm/mach-nomadik/clock.c | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | #include <linux/module.h> | 7 | #include <linux/module.h> |
| 8 | #include <linux/errno.h> | 8 | #include <linux/errno.h> |
| 9 | #include <linux/clk.h> | 9 | #include <linux/clk.h> |
| 10 | #include <asm/clkdev.h> | 10 | #include <linux/clkdev.h> |
| 11 | #include "clock.h" | 11 | #include "clock.h" |
| 12 | 12 | ||
| 13 | /* | 13 | /* |
diff --git a/arch/arm/mach-ns9xxx/time-ns9360.c b/arch/arm/mach-ns9xxx/time-ns9360.c index 77281260358a..9ca32f55728b 100644 --- a/arch/arm/mach-ns9xxx/time-ns9360.c +++ b/arch/arm/mach-ns9xxx/time-ns9360.c | |||
| @@ -35,7 +35,6 @@ static struct clocksource ns9360_clocksource = { | |||
| 35 | .rating = 300, | 35 | .rating = 300, |
| 36 | .read = ns9360_clocksource_read, | 36 | .read = ns9360_clocksource_read, |
| 37 | .mask = CLOCKSOURCE_MASK(32), | 37 | .mask = CLOCKSOURCE_MASK(32), |
| 38 | .shift = 20, | ||
| 39 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 38 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 40 | }; | 39 | }; |
| 41 | 40 | ||
| @@ -148,10 +147,7 @@ static void __init ns9360_timer_init(void) | |||
| 148 | 147 | ||
| 149 | __raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE)); | 148 | __raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE)); |
| 150 | 149 | ||
| 151 | ns9360_clocksource.mult = clocksource_hz2mult(ns9360_cpuclock(), | 150 | clocksource_register_hz(&ns9360_clocksource, ns9360_cpuclock()); |
| 152 | ns9360_clocksource.shift); | ||
| 153 | |||
| 154 | clocksource_register(&ns9360_clocksource); | ||
| 155 | 151 | ||
| 156 | latch = SH_DIV(ns9360_cpuclock(), HZ, 0); | 152 | latch = SH_DIV(ns9360_cpuclock(), HZ, 0); |
| 157 | 153 | ||
diff --git a/arch/arm/mach-nuc93x/clock.h b/arch/arm/mach-nuc93x/clock.h index 18e51be4816f..4de1f1da9dc5 100644 --- a/arch/arm/mach-nuc93x/clock.h +++ b/arch/arm/mach-nuc93x/clock.h | |||
| @@ -10,7 +10,7 @@ | |||
| 10 | * the Free Software Foundation; either version 2 of the License. | 10 | * the Free Software Foundation; either version 2 of the License. |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | #include <asm/clkdev.h> | 13 | #include <linux/clkdev.h> |
| 14 | 14 | ||
| 15 | void nuc93x_clk_enable(struct clk *clk, int enable); | 15 | void nuc93x_clk_enable(struct clk *clk, int enable); |
| 16 | void clks_register(struct clk_lookup *clks, size_t num); | 16 | void clks_register(struct clk_lookup *clks, size_t num); |
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index 5f6496375404..8d2f2daba0c0 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig | |||
| @@ -152,20 +152,11 @@ config MACH_NOKIA770 | |||
| 152 | config MACH_AMS_DELTA | 152 | config MACH_AMS_DELTA |
| 153 | bool "Amstrad E3 (Delta)" | 153 | bool "Amstrad E3 (Delta)" |
| 154 | depends on ARCH_OMAP1 && ARCH_OMAP15XX | 154 | depends on ARCH_OMAP1 && ARCH_OMAP15XX |
| 155 | select FIQ | ||
| 155 | help | 156 | help |
| 156 | Support for the Amstrad E3 (codename Delta) videophone. Say Y here | 157 | Support for the Amstrad E3 (codename Delta) videophone. Say Y here |
| 157 | if you have such a device. | 158 | if you have such a device. |
| 158 | 159 | ||
| 159 | config AMS_DELTA_FIQ | ||
| 160 | bool "Fast Interrupt Request (FIQ) support for the E3" | ||
| 161 | depends on MACH_AMS_DELTA | ||
| 162 | select FIQ | ||
| 163 | help | ||
| 164 | Provide a FIQ handler for the E3. | ||
| 165 | This allows for fast handling of interrupts generated | ||
| 166 | by the clock line of the E3 mailboard (or a PS/2 keyboard) | ||
| 167 | connected to the GPIO based external keyboard port. | ||
| 168 | |||
| 169 | config MACH_OMAP_GENERIC | 160 | config MACH_OMAP_GENERIC |
| 170 | bool "Generic OMAP board" | 161 | bool "Generic OMAP board" |
| 171 | depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX) | 162 | depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX) |
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index 9a304d854e33..6ee19504845f 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile | |||
| @@ -3,7 +3,7 @@ | |||
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | # Common support | 5 | # Common support |
| 6 | obj-y := io.o id.o sram.o irq.o mux.o flash.o serial.o devices.o | 6 | obj-y := io.o id.o sram.o irq.o mux.o flash.o serial.o devices.o dma.o |
| 7 | obj-y += clock.o clock_data.o opp_data.o | 7 | obj-y += clock.o clock_data.o opp_data.o |
| 8 | 8 | ||
| 9 | obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o | 9 | obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o |
| @@ -39,8 +39,8 @@ obj-$(CONFIG_MACH_OMAP_PALMTE) += board-palmte.o | |||
| 39 | obj-$(CONFIG_MACH_OMAP_PALMZ71) += board-palmz71.o | 39 | obj-$(CONFIG_MACH_OMAP_PALMZ71) += board-palmz71.o |
| 40 | obj-$(CONFIG_MACH_OMAP_PALMTT) += board-palmtt.o | 40 | obj-$(CONFIG_MACH_OMAP_PALMTT) += board-palmtt.o |
| 41 | obj-$(CONFIG_MACH_NOKIA770) += board-nokia770.o | 41 | obj-$(CONFIG_MACH_NOKIA770) += board-nokia770.o |
| 42 | obj-$(CONFIG_MACH_AMS_DELTA) += board-ams-delta.o | 42 | obj-$(CONFIG_MACH_AMS_DELTA) += board-ams-delta.o ams-delta-fiq.o \ |
| 43 | obj-$(CONFIG_AMS_DELTA_FIQ) += ams-delta-fiq.o ams-delta-fiq-handler.o | 43 | ams-delta-fiq-handler.o |
| 44 | obj-$(CONFIG_MACH_SX1) += board-sx1.o board-sx1-mmc.o | 44 | obj-$(CONFIG_MACH_SX1) += board-sx1.o board-sx1-mmc.o |
| 45 | obj-$(CONFIG_MACH_HERALD) += board-htcherald.o | 45 | obj-$(CONFIG_MACH_HERALD) += board-htcherald.o |
| 46 | 46 | ||
| @@ -49,6 +49,12 @@ ifeq ($(CONFIG_ARCH_OMAP15XX),y) | |||
| 49 | obj-$(CONFIG_MACH_OMAP_INNOVATOR) += fpga.o | 49 | obj-$(CONFIG_MACH_OMAP_INNOVATOR) += fpga.o |
| 50 | endif | 50 | endif |
| 51 | 51 | ||
| 52 | # GPIO | ||
| 53 | obj-$(CONFIG_ARCH_OMAP730) += gpio7xx.o | ||
| 54 | obj-$(CONFIG_ARCH_OMAP850) += gpio7xx.o | ||
| 55 | obj-$(CONFIG_ARCH_OMAP15XX) += gpio15xx.o | ||
| 56 | obj-$(CONFIG_ARCH_OMAP16XX) += gpio16xx.o | ||
| 57 | |||
| 52 | # LEDs support | 58 | # LEDs support |
| 53 | led-$(CONFIG_MACH_OMAP_H2) += leds-h2p2-debug.o | 59 | led-$(CONFIG_MACH_OMAP_H2) += leds-h2p2-debug.o |
| 54 | led-$(CONFIG_MACH_OMAP_H3) += leds-h2p2-debug.o | 60 | led-$(CONFIG_MACH_OMAP_H3) += leds-h2p2-debug.o |
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index 1d4163b9f0b7..bd0495a9ac3b 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c | |||
| @@ -28,6 +28,7 @@ | |||
| 28 | #include <asm/mach/arch.h> | 28 | #include <asm/mach/arch.h> |
| 29 | #include <asm/mach/map.h> | 29 | #include <asm/mach/map.h> |
| 30 | 30 | ||
| 31 | #include <plat/io.h> | ||
| 31 | #include <plat/board-ams-delta.h> | 32 | #include <plat/board-ams-delta.h> |
| 32 | #include <mach/gpio.h> | 33 | #include <mach/gpio.h> |
| 33 | #include <plat/keypad.h> | 34 | #include <plat/keypad.h> |
| @@ -42,84 +43,82 @@ | |||
| 42 | static u8 ams_delta_latch1_reg; | 43 | static u8 ams_delta_latch1_reg; |
| 43 | static u16 ams_delta_latch2_reg; | 44 | static u16 ams_delta_latch2_reg; |
| 44 | 45 | ||
| 45 | static int ams_delta_keymap[] = { | 46 | static const unsigned int ams_delta_keymap[] = { |
| 46 | KEY(0, 0, KEY_F1), /* Advert */ | 47 | KEY(0, 0, KEY_F1), /* Advert */ |
| 47 | 48 | ||
| 48 | KEY(3, 0, KEY_COFFEE), /* Games */ | 49 | KEY(0, 3, KEY_COFFEE), /* Games */ |
| 49 | KEY(2, 0, KEY_QUESTION), /* Directory */ | 50 | KEY(0, 2, KEY_QUESTION), /* Directory */ |
| 50 | KEY(3, 2, KEY_CONNECT), /* Internet */ | 51 | KEY(2, 3, KEY_CONNECT), /* Internet */ |
| 51 | KEY(2, 1, KEY_SHOP), /* Services */ | 52 | KEY(1, 2, KEY_SHOP), /* Services */ |
| 52 | KEY(1, 1, KEY_PHONE), /* VoiceMail */ | 53 | KEY(1, 1, KEY_PHONE), /* VoiceMail */ |
| 53 | 54 | ||
| 54 | KEY(1, 0, KEY_DELETE), /* Delete */ | 55 | KEY(0, 1, KEY_DELETE), /* Delete */ |
| 55 | KEY(2, 2, KEY_PLAY), /* Play */ | 56 | KEY(2, 2, KEY_PLAY), /* Play */ |
| 56 | KEY(0, 1, KEY_PAGEUP), /* Up */ | 57 | KEY(1, 0, KEY_PAGEUP), /* Up */ |
| 57 | KEY(3, 1, KEY_PAGEDOWN), /* Down */ | 58 | KEY(1, 3, KEY_PAGEDOWN), /* Down */ |
| 58 | KEY(0, 2, KEY_EMAIL), /* ReadEmail */ | 59 | KEY(2, 0, KEY_EMAIL), /* ReadEmail */ |
| 59 | KEY(1, 2, KEY_STOP), /* Stop */ | 60 | KEY(2, 1, KEY_STOP), /* Stop */ |
| 60 | 61 | ||
| 61 | /* Numeric keypad portion */ | 62 | /* Numeric keypad portion */ |
| 62 | KEY(7, 0, KEY_KP1), | 63 | KEY(0, 7, KEY_KP1), |
| 63 | KEY(6, 0, KEY_KP2), | 64 | KEY(0, 6, KEY_KP2), |
| 64 | KEY(5, 0, KEY_KP3), | 65 | KEY(0, 5, KEY_KP3), |
| 65 | KEY(7, 1, KEY_KP4), | 66 | KEY(1, 7, KEY_KP4), |
| 66 | KEY(6, 1, KEY_KP5), | 67 | KEY(1, 6, KEY_KP5), |
| 67 | KEY(5, 1, KEY_KP6), | 68 | KEY(1, 5, KEY_KP6), |
| 68 | KEY(7, 2, KEY_KP7), | 69 | KEY(2, 7, KEY_KP7), |
| 69 | KEY(6, 2, KEY_KP8), | 70 | KEY(2, 6, KEY_KP8), |
| 70 | KEY(5, 2, KEY_KP9), | 71 | KEY(2, 5, KEY_KP9), |
| 71 | KEY(6, 3, KEY_KP0), | 72 | KEY(3, 6, KEY_KP0), |
| 72 | KEY(7, 3, KEY_KPASTERISK), | 73 | KEY(3, 7, KEY_KPASTERISK), |
| 73 | KEY(5, 3, KEY_KPDOT), /* # key */ | 74 | KEY(3, 5, KEY_KPDOT), /* # key */ |
| 74 | KEY(2, 7, KEY_NUMLOCK), /* Mute */ | 75 | KEY(7, 2, KEY_NUMLOCK), /* Mute */ |
| 75 | KEY(1, 7, KEY_KPMINUS), /* Recall */ | 76 | KEY(7, 1, KEY_KPMINUS), /* Recall */ |
| 76 | KEY(1, 6, KEY_KPPLUS), /* Redial */ | 77 | KEY(6, 1, KEY_KPPLUS), /* Redial */ |
| 77 | KEY(6, 7, KEY_KPSLASH), /* Handsfree */ | 78 | KEY(7, 6, KEY_KPSLASH), /* Handsfree */ |
| 78 | KEY(0, 6, KEY_ENTER), /* Video */ | 79 | KEY(6, 0, KEY_ENTER), /* Video */ |
| 79 | 80 | ||
| 80 | KEY(4, 7, KEY_CAMERA), /* Photo */ | 81 | KEY(7, 4, KEY_CAMERA), /* Photo */ |
| 81 | 82 | ||
| 82 | KEY(4, 0, KEY_F2), /* Home */ | 83 | KEY(0, 4, KEY_F2), /* Home */ |
| 83 | KEY(4, 1, KEY_F3), /* Office */ | 84 | KEY(1, 4, KEY_F3), /* Office */ |
| 84 | KEY(4, 2, KEY_F4), /* Mobile */ | 85 | KEY(2, 4, KEY_F4), /* Mobile */ |
| 85 | KEY(7, 7, KEY_F5), /* SMS */ | 86 | KEY(7, 7, KEY_F5), /* SMS */ |
| 86 | KEY(5, 7, KEY_F6), /* Email */ | 87 | KEY(7, 5, KEY_F6), /* Email */ |
| 87 | 88 | ||
| 88 | /* QWERTY portion of keypad */ | 89 | /* QWERTY portion of keypad */ |
| 89 | KEY(4, 3, KEY_Q), | 90 | KEY(3, 4, KEY_Q), |
| 90 | KEY(3, 3, KEY_W), | 91 | KEY(3, 3, KEY_W), |
| 91 | KEY(2, 3, KEY_E), | 92 | KEY(3, 2, KEY_E), |
| 92 | KEY(1, 3, KEY_R), | 93 | KEY(3, 1, KEY_R), |
| 93 | KEY(0, 3, KEY_T), | 94 | KEY(3, 0, KEY_T), |
| 94 | KEY(7, 4, KEY_Y), | 95 | KEY(4, 7, KEY_Y), |
| 95 | KEY(6, 4, KEY_U), | 96 | KEY(4, 6, KEY_U), |
| 96 | KEY(5, 4, KEY_I), | 97 | KEY(4, 5, KEY_I), |
| 97 | KEY(4, 4, KEY_O), | 98 | KEY(4, 4, KEY_O), |
| 98 | KEY(3, 4, KEY_P), | 99 | KEY(4, 3, KEY_P), |
| 99 | 100 | ||
| 100 | KEY(2, 4, KEY_A), | 101 | KEY(4, 2, KEY_A), |
| 101 | KEY(1, 4, KEY_S), | 102 | KEY(4, 1, KEY_S), |
| 102 | KEY(0, 4, KEY_D), | 103 | KEY(4, 0, KEY_D), |
| 103 | KEY(7, 5, KEY_F), | 104 | KEY(5, 7, KEY_F), |
| 104 | KEY(6, 5, KEY_G), | 105 | KEY(5, 6, KEY_G), |
| 105 | KEY(5, 5, KEY_H), | 106 | KEY(5, 5, KEY_H), |
| 106 | KEY(4, 5, KEY_J), | 107 | KEY(5, 4, KEY_J), |
| 107 | KEY(3, 5, KEY_K), | 108 | KEY(5, 3, KEY_K), |
| 108 | KEY(2, 5, KEY_L), | 109 | KEY(5, 2, KEY_L), |
| 109 | 110 | ||
| 110 | KEY(1, 5, KEY_Z), | 111 | KEY(5, 1, KEY_Z), |
| 111 | KEY(0, 5, KEY_X), | 112 | KEY(5, 0, KEY_X), |
| 112 | KEY(7, 6, KEY_C), | 113 | KEY(6, 7, KEY_C), |
| 113 | KEY(6, 6, KEY_V), | 114 | KEY(6, 6, KEY_V), |
| 114 | KEY(5, 6, KEY_B), | 115 | KEY(6, 5, KEY_B), |
| 115 | KEY(4, 6, KEY_N), | 116 | KEY(6, 4, KEY_N), |
| 116 | KEY(3, 6, KEY_M), | 117 | KEY(6, 3, KEY_M), |
| 117 | KEY(2, 6, KEY_SPACE), | 118 | KEY(6, 2, KEY_SPACE), |
| 118 | 119 | ||
| 119 | KEY(0, 7, KEY_LEFTSHIFT), /* Vol up */ | 120 | KEY(7, 0, KEY_LEFTSHIFT), /* Vol up */ |
| 120 | KEY(3, 7, KEY_LEFTCTRL), /* Vol down */ | 121 | KEY(7, 3, KEY_LEFTCTRL), /* Vol down */ |
| 121 | |||
| 122 | 0 | ||
| 123 | }; | 122 | }; |
| 124 | 123 | ||
| 125 | void ams_delta_latch1_write(u8 mask, u8 value) | 124 | void ams_delta_latch1_write(u8 mask, u8 value) |
| @@ -140,7 +139,6 @@ static void __init ams_delta_init_irq(void) | |||
| 140 | { | 139 | { |
| 141 | omap1_init_common_hw(); | 140 | omap1_init_common_hw(); |
| 142 | omap_init_irq(); | 141 | omap_init_irq(); |
| 143 | omap_gpio_init(); | ||
| 144 | } | 142 | } |
| 145 | 143 | ||
| 146 | static struct map_desc ams_delta_io_desc[] __initdata = { | 144 | static struct map_desc ams_delta_io_desc[] __initdata = { |
| @@ -189,11 +187,15 @@ static struct resource ams_delta_kp_resources[] = { | |||
| 189 | }, | 187 | }, |
| 190 | }; | 188 | }; |
| 191 | 189 | ||
| 190 | static const struct matrix_keymap_data ams_delta_keymap_data = { | ||
| 191 | .keymap = ams_delta_keymap, | ||
| 192 | .keymap_size = ARRAY_SIZE(ams_delta_keymap), | ||
| 193 | }; | ||
| 194 | |||
| 192 | static struct omap_kp_platform_data ams_delta_kp_data = { | 195 | static struct omap_kp_platform_data ams_delta_kp_data = { |
| 193 | .rows = 8, | 196 | .rows = 8, |
| 194 | .cols = 8, | 197 | .cols = 8, |
| 195 | .keymap = ams_delta_keymap, | 198 | .keymap_data = &ams_delta_keymap_data, |
| 196 | .keymapsize = ARRAY_SIZE(ams_delta_keymap), | ||
| 197 | .delay = 9, | 199 | .delay = 9, |
| 198 | }; | 200 | }; |
| 199 | 201 | ||
| @@ -307,16 +309,14 @@ static void __init ams_delta_init(void) | |||
| 307 | #endif | 309 | #endif |
| 308 | platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices)); | 310 | platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices)); |
| 309 | 311 | ||
| 310 | #ifdef CONFIG_AMS_DELTA_FIQ | ||
| 311 | ams_delta_init_fiq(); | 312 | ams_delta_init_fiq(); |
| 312 | #endif | ||
| 313 | 313 | ||
| 314 | omap_writew(omap_readw(ARM_RSTCT1) | 0x0004, ARM_RSTCT1); | 314 | omap_writew(omap_readw(ARM_RSTCT1) | 0x0004, ARM_RSTCT1); |
| 315 | } | 315 | } |
| 316 | 316 | ||
| 317 | static struct plat_serial8250_port ams_delta_modem_ports[] = { | 317 | static struct plat_serial8250_port ams_delta_modem_ports[] = { |
| 318 | { | 318 | { |
| 319 | .membase = (void *) AMS_DELTA_MODEM_VIRT, | 319 | .membase = IOMEM(AMS_DELTA_MODEM_VIRT), |
| 320 | .mapbase = AMS_DELTA_MODEM_PHYS, | 320 | .mapbase = AMS_DELTA_MODEM_PHYS, |
| 321 | .irq = -EINVAL, /* changed later */ | 321 | .irq = -EINVAL, /* changed later */ |
| 322 | .flags = UPF_BOOT_AUTOCONF, | 322 | .flags = UPF_BOOT_AUTOCONF, |
| @@ -340,6 +340,9 @@ static int __init ams_delta_modem_init(void) | |||
| 340 | { | 340 | { |
| 341 | int err; | 341 | int err; |
| 342 | 342 | ||
| 343 | if (!machine_is_ams_delta()) | ||
| 344 | return -ENODEV; | ||
| 345 | |||
| 343 | omap_cfg_reg(M14_1510_GPIO2); | 346 | omap_cfg_reg(M14_1510_GPIO2); |
| 344 | ams_delta_modem_ports[0].irq = | 347 | ams_delta_modem_ports[0].irq = |
| 345 | gpio_to_irq(AMS_DELTA_GPIO_PIN_MODEM_IRQ); | 348 | gpio_to_irq(AMS_DELTA_GPIO_PIN_MODEM_IRQ); |
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c index 149fdd32e127..0efb9dbae44c 100644 --- a/arch/arm/mach-omap1/board-fsample.c +++ b/arch/arm/mach-omap1/board-fsample.c | |||
| @@ -69,36 +69,35 @@ | |||
| 69 | #define fsample_cpld_clear(bit) \ | 69 | #define fsample_cpld_clear(bit) \ |
| 70 | fsample_cpld_write(0xf0 | ((bit) & 15), FSAMPLE_CPLD_SET_CLR) | 70 | fsample_cpld_write(0xf0 | ((bit) & 15), FSAMPLE_CPLD_SET_CLR) |
| 71 | 71 | ||
| 72 | static int fsample_keymap[] = { | 72 | static const unsigned int fsample_keymap[] = { |
| 73 | KEY(0,0,KEY_UP), | 73 | KEY(0, 0, KEY_UP), |
| 74 | KEY(0,1,KEY_RIGHT), | 74 | KEY(1, 0, KEY_RIGHT), |
| 75 | KEY(0,2,KEY_LEFT), | 75 | KEY(2, 0, KEY_LEFT), |
| 76 | KEY(0,3,KEY_DOWN), | 76 | KEY(3, 0, KEY_DOWN), |
| 77 | KEY(0,4,KEY_ENTER), | 77 | KEY(4, 0, KEY_ENTER), |
| 78 | KEY(1,0,KEY_F10), | 78 | KEY(0, 1, KEY_F10), |
| 79 | KEY(1,1,KEY_SEND), | 79 | KEY(1, 1, KEY_SEND), |
| 80 | KEY(1,2,KEY_END), | 80 | KEY(2, 1, KEY_END), |
| 81 | KEY(1,3,KEY_VOLUMEDOWN), | 81 | KEY(3, 1, KEY_VOLUMEDOWN), |
| 82 | KEY(1,4,KEY_VOLUMEUP), | 82 | KEY(4, 1, KEY_VOLUMEUP), |
| 83 | KEY(1,5,KEY_RECORD), | 83 | KEY(5, 1, KEY_RECORD), |
| 84 | KEY(2,0,KEY_F9), | 84 | KEY(0, 2, KEY_F9), |
| 85 | KEY(2,1,KEY_3), | 85 | KEY(1, 2, KEY_3), |
| 86 | KEY(2,2,KEY_6), | 86 | KEY(2, 2, KEY_6), |
| 87 | KEY(2,3,KEY_9), | 87 | KEY(3, 2, KEY_9), |
| 88 | KEY(2,4,KEY_KPDOT), | 88 | KEY(4, 2, KEY_KPDOT), |
| 89 | KEY(3,0,KEY_BACK), | 89 | KEY(0, 3, KEY_BACK), |
| 90 | KEY(3,1,KEY_2), | 90 | KEY(1, 3, KEY_2), |
| 91 | KEY(3,2,KEY_5), | 91 | KEY(2, 3, KEY_5), |
| 92 | KEY(3,3,KEY_8), | 92 | KEY(3, 3, KEY_8), |
| 93 | KEY(3,4,KEY_0), | 93 | KEY(4, 3, KEY_0), |
| 94 | KEY(3,5,KEY_KPSLASH), | 94 | KEY(5, 3, KEY_KPSLASH), |
| 95 | KEY(4,0,KEY_HOME), | 95 | KEY(0, 4, KEY_HOME), |
| 96 | KEY(4,1,KEY_1), | 96 | KEY(1, 4, KEY_1), |
| 97 | KEY(4,2,KEY_4), | 97 | KEY(2, 4, KEY_4), |
| 98 | KEY(4,3,KEY_7), | 98 | KEY(3, 4, KEY_7), |
| 99 | KEY(4,4,KEY_KPASTERISK), | 99 | KEY(4, 4, KEY_KPASTERISK), |
| 100 | KEY(4,5,KEY_POWER), | 100 | KEY(5, 4, KEY_POWER), |
| 101 | 0 | ||
| 102 | }; | 101 | }; |
| 103 | 102 | ||
| 104 | static struct smc91x_platdata smc91x_info = { | 103 | static struct smc91x_platdata smc91x_info = { |
| @@ -120,6 +119,15 @@ static struct resource smc91x_resources[] = { | |||
| 120 | }, | 119 | }, |
| 121 | }; | 120 | }; |
| 122 | 121 | ||
| 122 | static void __init fsample_init_smc91x(void) | ||
| 123 | { | ||
| 124 | fpga_write(1, H2P2_DBG_FPGA_LAN_RESET); | ||
| 125 | mdelay(50); | ||
| 126 | fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1, | ||
| 127 | H2P2_DBG_FPGA_LAN_RESET); | ||
| 128 | mdelay(50); | ||
| 129 | } | ||
| 130 | |||
| 123 | static struct mtd_partition nor_partitions[] = { | 131 | static struct mtd_partition nor_partitions[] = { |
| 124 | /* bootloader (U-Boot, etc) in first sector */ | 132 | /* bootloader (U-Boot, etc) in first sector */ |
| 125 | { | 133 | { |
| @@ -244,11 +252,15 @@ static struct resource kp_resources[] = { | |||
| 244 | }, | 252 | }, |
| 245 | }; | 253 | }; |
| 246 | 254 | ||
| 255 | static const struct matrix_keymap_data fsample_keymap_data = { | ||
| 256 | .keymap = fsample_keymap, | ||
| 257 | .keymap_size = ARRAY_SIZE(fsample_keymap), | ||
| 258 | }; | ||
| 259 | |||
| 247 | static struct omap_kp_platform_data kp_data = { | 260 | static struct omap_kp_platform_data kp_data = { |
| 248 | .rows = 8, | 261 | .rows = 8, |
| 249 | .cols = 8, | 262 | .cols = 8, |
| 250 | .keymap = fsample_keymap, | 263 | .keymap_data = &fsample_keymap_data, |
| 251 | .keymapsize = ARRAY_SIZE(fsample_keymap), | ||
| 252 | .delay = 4, | 264 | .delay = 4, |
| 253 | }; | 265 | }; |
| 254 | 266 | ||
| @@ -285,6 +297,8 @@ static struct omap_board_config_kernel fsample_config[] = { | |||
| 285 | 297 | ||
| 286 | static void __init omap_fsample_init(void) | 298 | static void __init omap_fsample_init(void) |
| 287 | { | 299 | { |
| 300 | fsample_init_smc91x(); | ||
| 301 | |||
| 288 | if (gpio_request(FSAMPLE_NAND_RB_GPIO_PIN, "NAND ready") < 0) | 302 | if (gpio_request(FSAMPLE_NAND_RB_GPIO_PIN, "NAND ready") < 0) |
| 289 | BUG(); | 303 | BUG(); |
| 290 | gpio_direction_input(FSAMPLE_NAND_RB_GPIO_PIN); | 304 | gpio_direction_input(FSAMPLE_NAND_RB_GPIO_PIN); |
| @@ -312,21 +326,10 @@ static void __init omap_fsample_init(void) | |||
| 312 | omap_register_i2c_bus(1, 100, NULL, 0); | 326 | omap_register_i2c_bus(1, 100, NULL, 0); |
| 313 | } | 327 | } |
| 314 | 328 | ||
| 315 | static void __init fsample_init_smc91x(void) | ||
| 316 | { | ||
| 317 | fpga_write(1, H2P2_DBG_FPGA_LAN_RESET); | ||
| 318 | mdelay(50); | ||
| 319 | fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1, | ||
| 320 | H2P2_DBG_FPGA_LAN_RESET); | ||
| 321 | mdelay(50); | ||
| 322 | } | ||
| 323 | |||
| 324 | static void __init omap_fsample_init_irq(void) | 329 | static void __init omap_fsample_init_irq(void) |
| 325 | { | 330 | { |
| 326 | omap1_init_common_hw(); | 331 | omap1_init_common_hw(); |
| 327 | omap_init_irq(); | 332 | omap_init_irq(); |
| 328 | omap_gpio_init(); | ||
| 329 | fsample_init_smc91x(); | ||
| 330 | } | 333 | } |
| 331 | 334 | ||
| 332 | /* Only FPGA needs to be mapped here. All others are done with ioremap */ | 335 | /* Only FPGA needs to be mapped here. All others are done with ioremap */ |
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index 197adb49dc5a..28b84aa9bdba 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c | |||
| @@ -52,43 +52,42 @@ | |||
| 52 | /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ | 52 | /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ |
| 53 | #define OMAP1610_ETHR_START 0x04000300 | 53 | #define OMAP1610_ETHR_START 0x04000300 |
| 54 | 54 | ||
| 55 | static int h2_keymap[] = { | 55 | static const unsigned int h2_keymap[] = { |
| 56 | KEY(0, 0, KEY_LEFT), | 56 | KEY(0, 0, KEY_LEFT), |
| 57 | KEY(0, 1, KEY_RIGHT), | 57 | KEY(1, 0, KEY_RIGHT), |
| 58 | KEY(0, 2, KEY_3), | 58 | KEY(2, 0, KEY_3), |
| 59 | KEY(0, 3, KEY_F10), | 59 | KEY(3, 0, KEY_F10), |
| 60 | KEY(0, 4, KEY_F5), | 60 | KEY(4, 0, KEY_F5), |
| 61 | KEY(0, 5, KEY_9), | 61 | KEY(5, 0, KEY_9), |
| 62 | KEY(1, 0, KEY_DOWN), | 62 | KEY(0, 1, KEY_DOWN), |
| 63 | KEY(1, 1, KEY_UP), | 63 | KEY(1, 1, KEY_UP), |
| 64 | KEY(1, 2, KEY_2), | 64 | KEY(2, 1, KEY_2), |
| 65 | KEY(1, 3, KEY_F9), | 65 | KEY(3, 1, KEY_F9), |
| 66 | KEY(1, 4, KEY_F7), | 66 | KEY(4, 1, KEY_F7), |
| 67 | KEY(1, 5, KEY_0), | 67 | KEY(5, 1, KEY_0), |
| 68 | KEY(2, 0, KEY_ENTER), | 68 | KEY(0, 2, KEY_ENTER), |
| 69 | KEY(2, 1, KEY_6), | 69 | KEY(1, 2, KEY_6), |
| 70 | KEY(2, 2, KEY_1), | 70 | KEY(2, 2, KEY_1), |
| 71 | KEY(2, 3, KEY_F2), | 71 | KEY(3, 2, KEY_F2), |
| 72 | KEY(2, 4, KEY_F6), | 72 | KEY(4, 2, KEY_F6), |
| 73 | KEY(2, 5, KEY_HOME), | 73 | KEY(5, 2, KEY_HOME), |
| 74 | KEY(3, 0, KEY_8), | 74 | KEY(0, 3, KEY_8), |
| 75 | KEY(3, 1, KEY_5), | 75 | KEY(1, 3, KEY_5), |
| 76 | KEY(3, 2, KEY_F12), | 76 | KEY(2, 3, KEY_F12), |
| 77 | KEY(3, 3, KEY_F3), | 77 | KEY(3, 3, KEY_F3), |
| 78 | KEY(3, 4, KEY_F8), | 78 | KEY(4, 3, KEY_F8), |
| 79 | KEY(3, 5, KEY_END), | 79 | KEY(5, 3, KEY_END), |
| 80 | KEY(4, 0, KEY_7), | 80 | KEY(0, 4, KEY_7), |
| 81 | KEY(4, 1, KEY_4), | 81 | KEY(1, 4, KEY_4), |
| 82 | KEY(4, 2, KEY_F11), | 82 | KEY(2, 4, KEY_F11), |
| 83 | KEY(4, 3, KEY_F1), | 83 | KEY(3, 4, KEY_F1), |
| 84 | KEY(4, 4, KEY_F4), | 84 | KEY(4, 4, KEY_F4), |
| 85 | KEY(4, 5, KEY_ESC), | 85 | KEY(5, 4, KEY_ESC), |
| 86 | KEY(5, 0, KEY_F13), | 86 | KEY(0, 5, KEY_F13), |
| 87 | KEY(5, 1, KEY_F14), | 87 | KEY(1, 5, KEY_F14), |
| 88 | KEY(5, 2, KEY_F15), | 88 | KEY(2, 5, KEY_F15), |
| 89 | KEY(5, 3, KEY_F16), | 89 | KEY(3, 5, KEY_F16), |
| 90 | KEY(5, 4, KEY_SLEEP), | 90 | KEY(4, 5, KEY_SLEEP), |
| 91 | 0 | ||
| 92 | }; | 91 | }; |
| 93 | 92 | ||
| 94 | static struct mtd_partition h2_nor_partitions[] = { | 93 | static struct mtd_partition h2_nor_partitions[] = { |
| @@ -270,14 +269,18 @@ static struct resource h2_kp_resources[] = { | |||
| 270 | }, | 269 | }, |
| 271 | }; | 270 | }; |
| 272 | 271 | ||
| 272 | static const struct matrix_keymap_data h2_keymap_data = { | ||
| 273 | .keymap = h2_keymap, | ||
| 274 | .keymap_size = ARRAY_SIZE(h2_keymap), | ||
| 275 | }; | ||
| 276 | |||
| 273 | static struct omap_kp_platform_data h2_kp_data = { | 277 | static struct omap_kp_platform_data h2_kp_data = { |
| 274 | .rows = 8, | 278 | .rows = 8, |
| 275 | .cols = 8, | 279 | .cols = 8, |
| 276 | .keymap = h2_keymap, | 280 | .keymap_data = &h2_keymap_data, |
| 277 | .keymapsize = ARRAY_SIZE(h2_keymap), | 281 | .rep = true, |
| 278 | .rep = 1, | ||
| 279 | .delay = 9, | 282 | .delay = 9, |
| 280 | .dbounce = 1, | 283 | .dbounce = true, |
| 281 | }; | 284 | }; |
| 282 | 285 | ||
| 283 | static struct platform_device h2_kp_device = { | 286 | static struct platform_device h2_kp_device = { |
| @@ -374,8 +377,6 @@ static void __init h2_init_irq(void) | |||
| 374 | { | 377 | { |
| 375 | omap1_init_common_hw(); | 378 | omap1_init_common_hw(); |
| 376 | omap_init_irq(); | 379 | omap_init_irq(); |
| 377 | omap_gpio_init(); | ||
| 378 | h2_init_smc91x(); | ||
| 379 | } | 380 | } |
| 380 | 381 | ||
| 381 | static struct omap_usb_config h2_usb_config __initdata = { | 382 | static struct omap_usb_config h2_usb_config __initdata = { |
| @@ -403,6 +404,8 @@ static struct omap_board_config_kernel h2_config[] __initdata = { | |||
| 403 | 404 | ||
| 404 | static void __init h2_init(void) | 405 | static void __init h2_init(void) |
| 405 | { | 406 | { |
| 407 | h2_init_smc91x(); | ||
| 408 | |||
| 406 | /* Here we assume the NOR boot config: NOR on CS3 (possibly swapped | 409 | /* Here we assume the NOR boot config: NOR on CS3 (possibly swapped |
| 407 | * to address 0 by a dip switch), NAND on CS2B. The NAND driver will | 410 | * to address 0 by a dip switch), NAND on CS2B. The NAND driver will |
| 408 | * notice whether a NAND chip is enabled at probe time. | 411 | * notice whether a NAND chip is enabled at probe time. |
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index 9126e3e37b4a..dbc8b8d882ba 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c | |||
| @@ -56,43 +56,42 @@ | |||
| 56 | 56 | ||
| 57 | #define H3_TS_GPIO 48 | 57 | #define H3_TS_GPIO 48 |
| 58 | 58 | ||
| 59 | static int h3_keymap[] = { | 59 | static const unsigned int h3_keymap[] = { |
| 60 | KEY(0, 0, KEY_LEFT), | 60 | KEY(0, 0, KEY_LEFT), |
| 61 | KEY(0, 1, KEY_RIGHT), | 61 | KEY(1, 0, KEY_RIGHT), |
| 62 | KEY(0, 2, KEY_3), | 62 | KEY(2, 0, KEY_3), |
| 63 | KEY(0, 3, KEY_F10), | 63 | KEY(3, 0, KEY_F10), |
| 64 | KEY(0, 4, KEY_F5), | 64 | KEY(4, 0, KEY_F5), |
| 65 | KEY(0, 5, KEY_9), | 65 | KEY(5, 0, KEY_9), |
| 66 | KEY(1, 0, KEY_DOWN), | 66 | KEY(0, 1, KEY_DOWN), |
| 67 | KEY(1, 1, KEY_UP), | 67 | KEY(1, 1, KEY_UP), |
| 68 | KEY(1, 2, KEY_2), | 68 | KEY(2, 1, KEY_2), |
| 69 | KEY(1, 3, KEY_F9), | 69 | KEY(3, 1, KEY_F9), |
| 70 | KEY(1, 4, KEY_F7), | 70 | KEY(4, 1, KEY_F7), |
| 71 | KEY(1, 5, KEY_0), | 71 | KEY(5, 1, KEY_0), |
| 72 | KEY(2, 0, KEY_ENTER), | 72 | KEY(0, 2, KEY_ENTER), |
| 73 | KEY(2, 1, KEY_6), | 73 | KEY(1, 2, KEY_6), |
| 74 | KEY(2, 2, KEY_1), | 74 | KEY(2, 2, KEY_1), |
| 75 | KEY(2, 3, KEY_F2), | 75 | KEY(3, 2, KEY_F2), |
| 76 | KEY(2, 4, KEY_F6), | 76 | KEY(4, 2, KEY_F6), |
| 77 | KEY(2, 5, KEY_HOME), | 77 | KEY(5, 2, KEY_HOME), |
| 78 | KEY(3, 0, KEY_8), | 78 | KEY(0, 3, KEY_8), |
| 79 | KEY(3, 1, KEY_5), | 79 | KEY(1, 3, KEY_5), |
| 80 | KEY(3, 2, KEY_F12), | 80 | KEY(2, 3, KEY_F12), |
| 81 | KEY(3, 3, KEY_F3), | 81 | KEY(3, 3, KEY_F3), |
| 82 | KEY(3, 4, KEY_F8), | 82 | KEY(4, 3, KEY_F8), |
| 83 | KEY(3, 5, KEY_END), | 83 | KEY(5, 3, KEY_END), |
| 84 | KEY(4, 0, KEY_7), | 84 | KEY(0, 4, KEY_7), |
| 85 | KEY(4, 1, KEY_4), | 85 | KEY(1, 4, KEY_4), |
| 86 | KEY(4, 2, KEY_F11), | 86 | KEY(2, 4, KEY_F11), |
| 87 | KEY(4, 3, KEY_F1), | 87 | KEY(3, 4, KEY_F1), |
| 88 | KEY(4, 4, KEY_F4), | 88 | KEY(4, 4, KEY_F4), |
| 89 | KEY(4, 5, KEY_ESC), | 89 | KEY(5, 4, KEY_ESC), |
| 90 | KEY(5, 0, KEY_F13), | 90 | KEY(0, 5, KEY_F13), |
| 91 | KEY(5, 1, KEY_F14), | 91 | KEY(1, 5, KEY_F14), |
| 92 | KEY(5, 2, KEY_F15), | 92 | KEY(2, 5, KEY_F15), |
| 93 | KEY(5, 3, KEY_F16), | 93 | KEY(3, 5, KEY_F16), |
| 94 | KEY(5, 4, KEY_SLEEP), | 94 | KEY(4, 5, KEY_SLEEP), |
| 95 | 0 | ||
| 96 | }; | 95 | }; |
| 97 | 96 | ||
| 98 | 97 | ||
| @@ -264,6 +263,15 @@ static struct platform_device smc91x_device = { | |||
| 264 | .resource = smc91x_resources, | 263 | .resource = smc91x_resources, |
| 265 | }; | 264 | }; |
| 266 | 265 | ||
| 266 | static void __init h3_init_smc91x(void) | ||
| 267 | { | ||
| 268 | omap_cfg_reg(W15_1710_GPIO40); | ||
| 269 | if (gpio_request(40, "SMC91x irq") < 0) { | ||
| 270 | printk("Error requesting gpio 40 for smc91x irq\n"); | ||
| 271 | return; | ||
| 272 | } | ||
| 273 | } | ||
| 274 | |||
| 267 | #define GPTIMER_BASE 0xFFFB1400 | 275 | #define GPTIMER_BASE 0xFFFB1400 |
| 268 | #define GPTIMER_REGS(x) (0xFFFB1400 + (x * 0x800)) | 276 | #define GPTIMER_REGS(x) (0xFFFB1400 + (x * 0x800)) |
| 269 | #define GPTIMER_REGS_SIZE 0x46 | 277 | #define GPTIMER_REGS_SIZE 0x46 |
| @@ -296,14 +304,18 @@ static struct resource h3_kp_resources[] = { | |||
| 296 | }, | 304 | }, |
| 297 | }; | 305 | }; |
| 298 | 306 | ||
| 307 | static const struct matrix_keymap_data h3_keymap_data = { | ||
| 308 | .keymap = h3_keymap, | ||
| 309 | .keymap_size = ARRAY_SIZE(h3_keymap), | ||
| 310 | }; | ||
| 311 | |||
| 299 | static struct omap_kp_platform_data h3_kp_data = { | 312 | static struct omap_kp_platform_data h3_kp_data = { |
| 300 | .rows = 8, | 313 | .rows = 8, |
| 301 | .cols = 8, | 314 | .cols = 8, |
| 302 | .keymap = h3_keymap, | 315 | .keymap_data = &h3_keymap_data, |
| 303 | .keymapsize = ARRAY_SIZE(h3_keymap), | 316 | .rep = true, |
| 304 | .rep = 1, | ||
| 305 | .delay = 9, | 317 | .delay = 9, |
| 306 | .dbounce = 1, | 318 | .dbounce = true, |
| 307 | }; | 319 | }; |
| 308 | 320 | ||
| 309 | static struct platform_device h3_kp_device = { | 321 | static struct platform_device h3_kp_device = { |
| @@ -376,6 +388,8 @@ static struct i2c_board_info __initdata h3_i2c_board_info[] = { | |||
| 376 | 388 | ||
| 377 | static void __init h3_init(void) | 389 | static void __init h3_init(void) |
| 378 | { | 390 | { |
| 391 | h3_init_smc91x(); | ||
| 392 | |||
| 379 | /* Here we assume the NOR boot config: NOR on CS3 (possibly swapped | 393 | /* Here we assume the NOR boot config: NOR on CS3 (possibly swapped |
| 380 | * to address 0 by a dip switch), NAND on CS2B. The NAND driver will | 394 | * to address 0 by a dip switch), NAND on CS2B. The NAND driver will |
| 381 | * notice whether a NAND chip is enabled at probe time. | 395 | * notice whether a NAND chip is enabled at probe time. |
| @@ -422,21 +436,10 @@ static void __init h3_init(void) | |||
| 422 | h3_mmc_init(); | 436 | h3_mmc_init(); |
| 423 | } | 437 | } |
| 424 | 438 | ||
| 425 | static void __init h3_init_smc91x(void) | ||
| 426 | { | ||
| 427 | omap_cfg_reg(W15_1710_GPIO40); | ||
| 428 | if (gpio_request(40, "SMC91x irq") < 0) { | ||
| 429 | printk("Error requesting gpio 40 for smc91x irq\n"); | ||
| 430 | return; | ||
| 431 | } | ||
| 432 | } | ||
| 433 | |||
| 434 | static void __init h3_init_irq(void) | 439 | static void __init h3_init_irq(void) |
| 435 | { | 440 | { |
| 436 | omap1_init_common_hw(); | 441 | omap1_init_common_hw(); |
| 437 | omap_init_irq(); | 442 | omap_init_irq(); |
| 438 | omap_gpio_init(); | ||
| 439 | h3_init_smc91x(); | ||
| 440 | } | 443 | } |
| 441 | 444 | ||
| 442 | static void __init h3_map_io(void) | 445 | static void __init h3_map_io(void) |
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c index 071af3e47789..f2c5c585bc83 100644 --- a/arch/arm/mach-omap1/board-htcherald.c +++ b/arch/arm/mach-omap1/board-htcherald.c | |||
| @@ -180,64 +180,68 @@ | |||
| 180 | 180 | ||
| 181 | /* Keyboard definition */ | 181 | /* Keyboard definition */ |
| 182 | 182 | ||
| 183 | static int htc_herald_keymap[] = { | 183 | static const unsigned int htc_herald_keymap[] = { |
| 184 | KEY(0, 0, KEY_RECORD), /* Mail button */ | 184 | KEY(0, 0, KEY_RECORD), /* Mail button */ |
| 185 | KEY(0, 1, KEY_CAMERA), /* Camera */ | 185 | KEY(1, 0, KEY_CAMERA), /* Camera */ |
| 186 | KEY(0, 2, KEY_PHONE), /* Send key */ | 186 | KEY(2, 0, KEY_PHONE), /* Send key */ |
| 187 | KEY(0, 3, KEY_VOLUMEUP), /* Volume up */ | 187 | KEY(3, 0, KEY_VOLUMEUP), /* Volume up */ |
| 188 | KEY(0, 4, KEY_F2), /* Right bar (landscape) */ | 188 | KEY(4, 0, KEY_F2), /* Right bar (landscape) */ |
| 189 | KEY(0, 5, KEY_MAIL), /* Win key (portrait) */ | 189 | KEY(5, 0, KEY_MAIL), /* Win key (portrait) */ |
| 190 | KEY(0, 6, KEY_DIRECTORY), /* Right bar (protrait) */ | 190 | KEY(6, 0, KEY_DIRECTORY), /* Right bar (protrait) */ |
| 191 | KEY(1, 0, KEY_LEFTCTRL), /* Windows key */ | 191 | KEY(0, 1, KEY_LEFTCTRL), /* Windows key */ |
| 192 | KEY(1, 1, KEY_COMMA), | 192 | KEY(1, 1, KEY_COMMA), |
| 193 | KEY(1, 2, KEY_M), | 193 | KEY(2, 1, KEY_M), |
| 194 | KEY(1, 3, KEY_K), | 194 | KEY(3, 1, KEY_K), |
| 195 | KEY(1, 4, KEY_SLASH), /* OK key */ | 195 | KEY(4, 1, KEY_SLASH), /* OK key */ |
| 196 | KEY(1, 5, KEY_I), | 196 | KEY(5, 1, KEY_I), |
| 197 | KEY(1, 6, KEY_U), | 197 | KEY(6, 1, KEY_U), |
| 198 | KEY(2, 0, KEY_LEFTALT), | 198 | KEY(0, 2, KEY_LEFTALT), |
| 199 | KEY(2, 1, KEY_TAB), | 199 | KEY(1, 2, KEY_TAB), |
| 200 | KEY(2, 2, KEY_N), | 200 | KEY(2, 2, KEY_N), |
| 201 | KEY(2, 3, KEY_J), | 201 | KEY(3, 2, KEY_J), |
| 202 | KEY(2, 4, KEY_ENTER), | 202 | KEY(4, 2, KEY_ENTER), |
| 203 | KEY(2, 5, KEY_H), | 203 | KEY(5, 2, KEY_H), |
| 204 | KEY(2, 6, KEY_Y), | 204 | KEY(6, 2, KEY_Y), |
| 205 | KEY(3, 0, KEY_SPACE), | 205 | KEY(0, 3, KEY_SPACE), |
| 206 | KEY(3, 1, KEY_L), | 206 | KEY(1, 3, KEY_L), |
| 207 | KEY(3, 2, KEY_B), | 207 | KEY(2, 3, KEY_B), |
| 208 | KEY(3, 3, KEY_V), | 208 | KEY(3, 3, KEY_V), |
| 209 | KEY(3, 4, KEY_BACKSPACE), | 209 | KEY(4, 3, KEY_BACKSPACE), |
| 210 | KEY(3, 5, KEY_G), | 210 | KEY(5, 3, KEY_G), |
| 211 | KEY(3, 6, KEY_T), | 211 | KEY(6, 3, KEY_T), |
| 212 | KEY(4, 0, KEY_CAPSLOCK), /* Shift */ | 212 | KEY(0, 4, KEY_CAPSLOCK), /* Shift */ |
| 213 | KEY(4, 1, KEY_C), | 213 | KEY(1, 4, KEY_C), |
| 214 | KEY(4, 2, KEY_F), | 214 | KEY(2, 4, KEY_F), |
| 215 | KEY(4, 3, KEY_R), | 215 | KEY(3, 4, KEY_R), |
| 216 | KEY(4, 4, KEY_O), | 216 | KEY(4, 4, KEY_O), |
| 217 | KEY(4, 5, KEY_E), | 217 | KEY(5, 4, KEY_E), |
| 218 | KEY(4, 6, KEY_D), | 218 | KEY(6, 4, KEY_D), |
| 219 | KEY(5, 0, KEY_X), | 219 | KEY(0, 5, KEY_X), |
| 220 | KEY(5, 1, KEY_Z), | 220 | KEY(1, 5, KEY_Z), |
| 221 | KEY(5, 2, KEY_S), | 221 | KEY(2, 5, KEY_S), |
| 222 | KEY(5, 3, KEY_W), | 222 | KEY(3, 5, KEY_W), |
| 223 | KEY(5, 4, KEY_P), | 223 | KEY(4, 5, KEY_P), |
| 224 | KEY(5, 5, KEY_Q), | 224 | KEY(5, 5, KEY_Q), |
| 225 | KEY(5, 6, KEY_A), | 225 | KEY(6, 5, KEY_A), |
| 226 | KEY(6, 0, KEY_CONNECT), /* Voice button */ | 226 | KEY(0, 6, KEY_CONNECT), /* Voice button */ |
| 227 | KEY(6, 2, KEY_CANCEL), /* End key */ | 227 | KEY(2, 6, KEY_CANCEL), /* End key */ |
| 228 | KEY(6, 3, KEY_VOLUMEDOWN), /* Volume down */ | 228 | KEY(3, 6, KEY_VOLUMEDOWN), /* Volume down */ |
| 229 | KEY(6, 4, KEY_F1), /* Left bar (landscape) */ | 229 | KEY(4, 6, KEY_F1), /* Left bar (landscape) */ |
| 230 | KEY(6, 5, KEY_WWW), /* OK button (portrait) */ | 230 | KEY(5, 6, KEY_WWW), /* OK button (portrait) */ |
| 231 | KEY(6, 6, KEY_CALENDAR), /* Left bar (portrait) */ | 231 | KEY(6, 6, KEY_CALENDAR), /* Left bar (portrait) */ |
| 232 | 0 | ||
| 233 | }; | 232 | }; |
| 234 | 233 | ||
| 235 | struct omap_kp_platform_data htcherald_kp_data = { | 234 | static const struct matrix_keymap_data htc_herald_keymap_data = { |
| 235 | .keymap = htc_herald_keymap, | ||
| 236 | .keymap_size = ARRAY_SIZE(htc_herald_keymap), | ||
| 237 | }; | ||
| 238 | |||
| 239 | static struct omap_kp_platform_data htcherald_kp_data = { | ||
| 236 | .rows = 7, | 240 | .rows = 7, |
| 237 | .cols = 7, | 241 | .cols = 7, |
| 238 | .delay = 20, | 242 | .delay = 20, |
| 239 | .rep = 1, | 243 | .rep = true, |
| 240 | .keymap = htc_herald_keymap, | 244 | .keymap_data = &htc_herald_keymap_data, |
| 241 | }; | 245 | }; |
| 242 | 246 | ||
| 243 | static struct resource kp_resources[] = { | 247 | static struct resource kp_resources[] = { |
| @@ -278,7 +282,7 @@ static struct gpio_keys_button herald_gpio_keys_table[] = { | |||
| 278 | static struct gpio_keys_platform_data herald_gpio_keys_data = { | 282 | static struct gpio_keys_platform_data herald_gpio_keys_data = { |
| 279 | .buttons = herald_gpio_keys_table, | 283 | .buttons = herald_gpio_keys_table, |
| 280 | .nbuttons = ARRAY_SIZE(herald_gpio_keys_table), | 284 | .nbuttons = ARRAY_SIZE(herald_gpio_keys_table), |
| 281 | .rep = 1, | 285 | .rep = true, |
| 282 | }; | 286 | }; |
| 283 | 287 | ||
| 284 | static struct platform_device herald_gpiokeys_device = { | 288 | static struct platform_device herald_gpiokeys_device = { |
| @@ -439,7 +443,7 @@ static const struct ads7846_platform_data htcherald_ts_platform_data = { | |||
| 439 | .keep_vref_on = 1, | 443 | .keep_vref_on = 1, |
| 440 | .x_plate_ohms = 496, | 444 | .x_plate_ohms = 496, |
| 441 | .gpio_pendown = HTCHERALD_GPIO_TS, | 445 | .gpio_pendown = HTCHERALD_GPIO_TS, |
| 442 | .pressure_max = 100000, | 446 | .pressure_max = 10000, |
| 443 | .pressure_min = 5000, | 447 | .pressure_min = 5000, |
| 444 | .x_min = 528, | 448 | .x_min = 528, |
| 445 | .x_max = 3760, | 449 | .x_max = 3760, |
| @@ -577,8 +581,6 @@ static void __init htcherald_init(void) | |||
| 577 | printk(KERN_INFO "HTC Herald init.\n"); | 581 | printk(KERN_INFO "HTC Herald init.\n"); |
| 578 | 582 | ||
| 579 | /* Do board initialization before we register all the devices */ | 583 | /* Do board initialization before we register all the devices */ |
| 580 | omap_gpio_init(); | ||
| 581 | |||
| 582 | omap_board_config = htcherald_config; | 584 | omap_board_config = htcherald_config; |
| 583 | omap_board_config_size = ARRAY_SIZE(htcherald_config); | 585 | omap_board_config_size = ARRAY_SIZE(htcherald_config); |
| 584 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 586 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c index dc2b86fd66c1..a36e6742bf9b 100644 --- a/arch/arm/mach-omap1/board-innovator.c +++ b/arch/arm/mach-omap1/board-innovator.c | |||
| @@ -44,17 +44,16 @@ | |||
| 44 | /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ | 44 | /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ |
| 45 | #define INNOVATOR1610_ETHR_START 0x04000300 | 45 | #define INNOVATOR1610_ETHR_START 0x04000300 |
| 46 | 46 | ||
| 47 | static int innovator_keymap[] = { | 47 | static const unsigned int innovator_keymap[] = { |
| 48 | KEY(0, 0, KEY_F1), | 48 | KEY(0, 0, KEY_F1), |
| 49 | KEY(0, 3, KEY_DOWN), | 49 | KEY(3, 0, KEY_DOWN), |
| 50 | KEY(1, 1, KEY_F2), | 50 | KEY(1, 1, KEY_F2), |
| 51 | KEY(1, 2, KEY_RIGHT), | 51 | KEY(2, 1, KEY_RIGHT), |
| 52 | KEY(2, 0, KEY_F3), | 52 | KEY(0, 2, KEY_F3), |
| 53 | KEY(2, 1, KEY_F4), | 53 | KEY(1, 2, KEY_F4), |
| 54 | KEY(2, 2, KEY_UP), | 54 | KEY(2, 2, KEY_UP), |
| 55 | KEY(3, 2, KEY_ENTER), | 55 | KEY(2, 3, KEY_ENTER), |
| 56 | KEY(3, 3, KEY_LEFT), | 56 | KEY(3, 3, KEY_LEFT), |
| 57 | 0 | ||
| 58 | }; | 57 | }; |
| 59 | 58 | ||
| 60 | static struct mtd_partition innovator_partitions[] = { | 59 | static struct mtd_partition innovator_partitions[] = { |
| @@ -126,11 +125,15 @@ static struct resource innovator_kp_resources[] = { | |||
| 126 | }, | 125 | }, |
| 127 | }; | 126 | }; |
| 128 | 127 | ||
| 128 | static const struct matrix_keymap_data innovator_keymap_data = { | ||
| 129 | .keymap = innovator_keymap, | ||
| 130 | .keymap_size = ARRAY_SIZE(innovator_keymap), | ||
| 131 | }; | ||
| 132 | |||
| 129 | static struct omap_kp_platform_data innovator_kp_data = { | 133 | static struct omap_kp_platform_data innovator_kp_data = { |
| 130 | .rows = 8, | 134 | .rows = 8, |
| 131 | .cols = 8, | 135 | .cols = 8, |
| 132 | .keymap = innovator_keymap, | 136 | .keymap_data = &innovator_keymap_data, |
| 133 | .keymapsize = ARRAY_SIZE(innovator_keymap), | ||
| 134 | .delay = 4, | 137 | .delay = 4, |
| 135 | }; | 138 | }; |
| 136 | 139 | ||
| @@ -290,13 +293,6 @@ static void __init innovator_init_irq(void) | |||
| 290 | { | 293 | { |
| 291 | omap1_init_common_hw(); | 294 | omap1_init_common_hw(); |
| 292 | omap_init_irq(); | 295 | omap_init_irq(); |
| 293 | omap_gpio_init(); | ||
| 294 | #ifdef CONFIG_ARCH_OMAP15XX | ||
| 295 | if (cpu_is_omap1510()) { | ||
| 296 | omap1510_fpga_init_irq(); | ||
| 297 | } | ||
| 298 | #endif | ||
| 299 | innovator_init_smc91x(); | ||
| 300 | } | 296 | } |
| 301 | 297 | ||
| 302 | #ifdef CONFIG_ARCH_OMAP15XX | 298 | #ifdef CONFIG_ARCH_OMAP15XX |
| @@ -387,6 +383,10 @@ static struct omap_board_config_kernel innovator_config[] = { | |||
| 387 | 383 | ||
| 388 | static void __init innovator_init(void) | 384 | static void __init innovator_init(void) |
| 389 | { | 385 | { |
| 386 | if (cpu_is_omap1510()) | ||
| 387 | omap1510_fpga_init_irq(); | ||
| 388 | innovator_init_smc91x(); | ||
| 389 | |||
| 390 | #ifdef CONFIG_ARCH_OMAP15XX | 390 | #ifdef CONFIG_ARCH_OMAP15XX |
| 391 | if (cpu_is_omap1510()) { | 391 | if (cpu_is_omap1510()) { |
| 392 | unsigned char reg; | 392 | unsigned char reg; |
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index aa8375b2a0a3..d21f09dc78f4 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c | |||
| @@ -54,19 +54,18 @@ static void __init omap_nokia770_init_irq(void) | |||
| 54 | omap_init_irq(); | 54 | omap_init_irq(); |
| 55 | } | 55 | } |
| 56 | 56 | ||
| 57 | static int nokia770_keymap[] = { | 57 | static const unsigned int nokia770_keymap[] = { |
| 58 | KEY(0, 1, GROUP_0 | KEY_UP), | 58 | KEY(1, 0, GROUP_0 | KEY_UP), |
| 59 | KEY(0, 2, GROUP_1 | KEY_F5), | 59 | KEY(2, 0, GROUP_1 | KEY_F5), |
| 60 | KEY(1, 0, GROUP_0 | KEY_LEFT), | 60 | KEY(0, 1, GROUP_0 | KEY_LEFT), |
| 61 | KEY(1, 1, GROUP_0 | KEY_ENTER), | 61 | KEY(1, 1, GROUP_0 | KEY_ENTER), |
| 62 | KEY(1, 2, GROUP_0 | KEY_RIGHT), | 62 | KEY(2, 1, GROUP_0 | KEY_RIGHT), |
| 63 | KEY(2, 0, GROUP_1 | KEY_ESC), | 63 | KEY(0, 2, GROUP_1 | KEY_ESC), |
| 64 | KEY(2, 1, GROUP_0 | KEY_DOWN), | 64 | KEY(1, 2, GROUP_0 | KEY_DOWN), |
| 65 | KEY(2, 2, GROUP_1 | KEY_F4), | 65 | KEY(2, 2, GROUP_1 | KEY_F4), |
| 66 | KEY(3, 0, GROUP_2 | KEY_F7), | 66 | KEY(0, 3, GROUP_2 | KEY_F7), |
| 67 | KEY(3, 1, GROUP_2 | KEY_F8), | 67 | KEY(1, 3, GROUP_2 | KEY_F8), |
| 68 | KEY(3, 2, GROUP_2 | KEY_F6), | 68 | KEY(2, 3, GROUP_2 | KEY_F6), |
| 69 | 0 | ||
| 70 | }; | 69 | }; |
| 71 | 70 | ||
| 72 | static struct resource nokia770_kp_resources[] = { | 71 | static struct resource nokia770_kp_resources[] = { |
| @@ -77,11 +76,15 @@ static struct resource nokia770_kp_resources[] = { | |||
| 77 | }, | 76 | }, |
| 78 | }; | 77 | }; |
| 79 | 78 | ||
| 79 | static const struct matrix_keymap_data nokia770_keymap_data = { | ||
| 80 | .keymap = nokia770_keymap, | ||
| 81 | .keymap_size = ARRAY_SIZE(nokia770_keymap), | ||
| 82 | }; | ||
| 83 | |||
| 80 | static struct omap_kp_platform_data nokia770_kp_data = { | 84 | static struct omap_kp_platform_data nokia770_kp_data = { |
| 81 | .rows = 8, | 85 | .rows = 8, |
| 82 | .cols = 8, | 86 | .cols = 8, |
| 83 | .keymap = nokia770_keymap, | 87 | .keymap_data = &nokia770_keymap_data, |
| 84 | .keymapsize = ARRAY_SIZE(nokia770_keymap), | ||
| 85 | .delay = 4, | 88 | .delay = 4, |
| 86 | }; | 89 | }; |
| 87 | 90 | ||
| @@ -246,7 +249,6 @@ static void __init omap_nokia770_init(void) | |||
| 246 | platform_add_devices(nokia770_devices, ARRAY_SIZE(nokia770_devices)); | 249 | platform_add_devices(nokia770_devices, ARRAY_SIZE(nokia770_devices)); |
| 247 | spi_register_board_info(nokia770_spi_board_info, | 250 | spi_register_board_info(nokia770_spi_board_info, |
| 248 | ARRAY_SIZE(nokia770_spi_board_info)); | 251 | ARRAY_SIZE(nokia770_spi_board_info)); |
| 249 | omap_gpio_init(); | ||
| 250 | omap_serial_init(); | 252 | omap_serial_init(); |
| 251 | omap_register_i2c_bus(1, 100, NULL, 0); | 253 | omap_register_i2c_bus(1, 100, NULL, 0); |
| 252 | hwa742_dev_init(); | 254 | hwa742_dev_init(); |
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index e9dd79149a8e..7c5e2112c776 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c | |||
| @@ -283,9 +283,6 @@ static void __init osk_init_irq(void) | |||
| 283 | { | 283 | { |
| 284 | omap1_init_common_hw(); | 284 | omap1_init_common_hw(); |
| 285 | omap_init_irq(); | 285 | omap_init_irq(); |
| 286 | omap_gpio_init(); | ||
| 287 | osk_init_smc91x(); | ||
| 288 | osk_init_cf(); | ||
| 289 | } | 286 | } |
| 290 | 287 | ||
| 291 | static struct omap_usb_config osk_usb_config __initdata = { | 288 | static struct omap_usb_config osk_usb_config __initdata = { |
| @@ -341,25 +338,28 @@ static struct i2c_board_info __initdata mistral_i2c_board_info[] = { | |||
| 341 | */ | 338 | */ |
| 342 | }; | 339 | }; |
| 343 | 340 | ||
| 344 | static const int osk_keymap[] = { | 341 | static const unsigned int osk_keymap[] = { |
| 345 | /* KEY(col, row, code) */ | 342 | /* KEY(col, row, code) */ |
| 346 | KEY(0, 0, KEY_F1), /* SW4 */ | 343 | KEY(0, 0, KEY_F1), /* SW4 */ |
| 347 | KEY(0, 3, KEY_UP), /* (sw2/up) */ | 344 | KEY(3, 0, KEY_UP), /* (sw2/up) */ |
| 348 | KEY(1, 1, KEY_LEFTCTRL), /* SW5 */ | 345 | KEY(1, 1, KEY_LEFTCTRL), /* SW5 */ |
| 349 | KEY(1, 2, KEY_LEFT), /* (sw2/left) */ | 346 | KEY(2, 1, KEY_LEFT), /* (sw2/left) */ |
| 350 | KEY(2, 0, KEY_SPACE), /* SW3 */ | 347 | KEY(0, 2, KEY_SPACE), /* SW3 */ |
| 351 | KEY(2, 1, KEY_ESC), /* SW6 */ | 348 | KEY(1, 2, KEY_ESC), /* SW6 */ |
| 352 | KEY(2, 2, KEY_DOWN), /* (sw2/down) */ | 349 | KEY(2, 2, KEY_DOWN), /* (sw2/down) */ |
| 353 | KEY(3, 2, KEY_ENTER), /* (sw2/select) */ | 350 | KEY(2, 3, KEY_ENTER), /* (sw2/select) */ |
| 354 | KEY(3, 3, KEY_RIGHT), /* (sw2/right) */ | 351 | KEY(3, 3, KEY_RIGHT), /* (sw2/right) */ |
| 355 | 0 | 352 | }; |
| 353 | |||
| 354 | static const struct matrix_keymap_data osk_keymap_data = { | ||
| 355 | .keymap = osk_keymap, | ||
| 356 | .keymap_size = ARRAY_SIZE(osk_keymap), | ||
| 356 | }; | 357 | }; |
| 357 | 358 | ||
| 358 | static struct omap_kp_platform_data osk_kp_data = { | 359 | static struct omap_kp_platform_data osk_kp_data = { |
| 359 | .rows = 8, | 360 | .rows = 8, |
| 360 | .cols = 8, | 361 | .cols = 8, |
| 361 | .keymap = (int *) osk_keymap, | 362 | .keymap_data = &osk_keymap_data, |
| 362 | .keymapsize = ARRAY_SIZE(osk_keymap), | ||
| 363 | .delay = 9, | 363 | .delay = 9, |
| 364 | }; | 364 | }; |
| 365 | 365 | ||
| @@ -541,6 +541,9 @@ static void __init osk_init(void) | |||
| 541 | { | 541 | { |
| 542 | u32 l; | 542 | u32 l; |
| 543 | 543 | ||
| 544 | osk_init_smc91x(); | ||
| 545 | osk_init_cf(); | ||
| 546 | |||
| 544 | /* Workaround for wrong CS3 (NOR flash) timing | 547 | /* Workaround for wrong CS3 (NOR flash) timing |
| 545 | * There are some U-Boot versions out there which configure | 548 | * There are some U-Boot versions out there which configure |
| 546 | * wrong CS3 memory timings. This mainly leads to CRC | 549 | * wrong CS3 memory timings. This mainly leads to CRC |
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c index f32738b1eb6b..fb51ce6123d8 100644 --- a/arch/arm/mach-omap1/board-palmte.c +++ b/arch/arm/mach-omap1/board-palmte.c | |||
| @@ -63,28 +63,31 @@ static void __init omap_palmte_init_irq(void) | |||
| 63 | { | 63 | { |
| 64 | omap1_init_common_hw(); | 64 | omap1_init_common_hw(); |
| 65 | omap_init_irq(); | 65 | omap_init_irq(); |
| 66 | omap_gpio_init(); | ||
| 67 | } | 66 | } |
| 68 | 67 | ||
| 69 | static const int palmte_keymap[] = { | 68 | static const unsigned int palmte_keymap[] = { |
| 70 | KEY(0, 0, KEY_F1), /* Calendar */ | 69 | KEY(0, 0, KEY_F1), /* Calendar */ |
| 71 | KEY(0, 1, KEY_F2), /* Contacts */ | 70 | KEY(1, 0, KEY_F2), /* Contacts */ |
| 72 | KEY(0, 2, KEY_F3), /* Tasks List */ | 71 | KEY(2, 0, KEY_F3), /* Tasks List */ |
| 73 | KEY(0, 3, KEY_F4), /* Note Pad */ | 72 | KEY(3, 0, KEY_F4), /* Note Pad */ |
| 74 | KEY(0, 4, KEY_POWER), | 73 | KEY(4, 0, KEY_POWER), |
| 75 | KEY(1, 0, KEY_LEFT), | 74 | KEY(0, 1, KEY_LEFT), |
| 76 | KEY(1, 1, KEY_DOWN), | 75 | KEY(1, 1, KEY_DOWN), |
| 77 | KEY(1, 2, KEY_UP), | 76 | KEY(2, 1, KEY_UP), |
| 78 | KEY(1, 3, KEY_RIGHT), | 77 | KEY(3, 1, KEY_RIGHT), |
| 79 | KEY(1, 4, KEY_ENTER), | 78 | KEY(4, 1, KEY_ENTER), |
| 80 | 0, | 79 | }; |
| 80 | |||
| 81 | static const struct matrix_keymap_data palmte_keymap_data = { | ||
| 82 | .keymap = palmte_keymap, | ||
| 83 | .keymap_size = ARRAY_SIZE(palmte_keymap), | ||
| 81 | }; | 84 | }; |
| 82 | 85 | ||
| 83 | static struct omap_kp_platform_data palmte_kp_data = { | 86 | static struct omap_kp_platform_data palmte_kp_data = { |
| 84 | .rows = 8, | 87 | .rows = 8, |
| 85 | .cols = 8, | 88 | .cols = 8, |
| 86 | .keymap = (int *) palmte_keymap, | 89 | .keymap_data = &palmte_keymap_data, |
| 87 | .rep = 1, | 90 | .rep = true, |
| 88 | .delay = 12, | 91 | .delay = 12, |
| 89 | }; | 92 | }; |
| 90 | 93 | ||
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c index ed1400a67f75..f04f2d36e7d3 100644 --- a/arch/arm/mach-omap1/board-palmtt.c +++ b/arch/arm/mach-omap1/board-palmtt.c | |||
| @@ -51,19 +51,18 @@ | |||
| 51 | #define PALMTT_MMC_WP_GPIO 8 | 51 | #define PALMTT_MMC_WP_GPIO 8 |
| 52 | #define PALMTT_HDQ_GPIO 11 | 52 | #define PALMTT_HDQ_GPIO 11 |
| 53 | 53 | ||
| 54 | static int palmtt_keymap[] = { | 54 | static const unsigned int palmtt_keymap[] = { |
| 55 | KEY(0, 0, KEY_ESC), | 55 | KEY(0, 0, KEY_ESC), |
| 56 | KEY(0, 1, KEY_SPACE), | 56 | KEY(1, 0, KEY_SPACE), |
| 57 | KEY(0, 2, KEY_LEFTCTRL), | 57 | KEY(2, 0, KEY_LEFTCTRL), |
| 58 | KEY(0, 3, KEY_TAB), | 58 | KEY(3, 0, KEY_TAB), |
| 59 | KEY(0, 4, KEY_ENTER), | 59 | KEY(4, 0, KEY_ENTER), |
| 60 | KEY(1, 0, KEY_LEFT), | 60 | KEY(0, 1, KEY_LEFT), |
| 61 | KEY(1, 1, KEY_DOWN), | 61 | KEY(1, 1, KEY_DOWN), |
| 62 | KEY(1, 2, KEY_UP), | 62 | KEY(2, 1, KEY_UP), |
| 63 | KEY(1, 3, KEY_RIGHT), | 63 | KEY(3, 1, KEY_RIGHT), |
| 64 | KEY(2, 0, KEY_SLEEP), | 64 | KEY(0, 2, KEY_SLEEP), |
| 65 | KEY(2, 4, KEY_Y), | 65 | KEY(4, 2, KEY_Y), |
| 66 | 0 | ||
| 67 | }; | 66 | }; |
| 68 | 67 | ||
| 69 | static struct mtd_partition palmtt_partitions[] = { | 68 | static struct mtd_partition palmtt_partitions[] = { |
| @@ -136,10 +135,15 @@ static struct resource palmtt_kp_resources[] = { | |||
| 136 | }, | 135 | }, |
| 137 | }; | 136 | }; |
| 138 | 137 | ||
| 138 | static const struct matrix_keymap_data palmtt_keymap_data = { | ||
| 139 | .keymap = palmtt_keymap, | ||
| 140 | .keymap_size = ARRAY_SIZE(palmtt_keymap), | ||
| 141 | }; | ||
| 142 | |||
| 139 | static struct omap_kp_platform_data palmtt_kp_data = { | 143 | static struct omap_kp_platform_data palmtt_kp_data = { |
| 140 | .rows = 6, | 144 | .rows = 6, |
| 141 | .cols = 3, | 145 | .cols = 3, |
| 142 | .keymap = palmtt_keymap, | 146 | .keymap_data = &palmtt_keymap_data, |
| 143 | }; | 147 | }; |
| 144 | 148 | ||
| 145 | static struct platform_device palmtt_kp_device = { | 149 | static struct platform_device palmtt_kp_device = { |
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index d7a245cef9a4..d7bbbe721a75 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c | |||
| @@ -62,29 +62,32 @@ omap_palmz71_init_irq(void) | |||
| 62 | { | 62 | { |
| 63 | omap1_init_common_hw(); | 63 | omap1_init_common_hw(); |
| 64 | omap_init_irq(); | 64 | omap_init_irq(); |
| 65 | omap_gpio_init(); | ||
| 66 | } | 65 | } |
| 67 | 66 | ||
| 68 | static int palmz71_keymap[] = { | 67 | static const unsigned int palmz71_keymap[] = { |
| 69 | KEY(0, 0, KEY_F1), | 68 | KEY(0, 0, KEY_F1), |
| 70 | KEY(0, 1, KEY_F2), | 69 | KEY(1, 0, KEY_F2), |
| 71 | KEY(0, 2, KEY_F3), | 70 | KEY(2, 0, KEY_F3), |
| 72 | KEY(0, 3, KEY_F4), | 71 | KEY(3, 0, KEY_F4), |
| 73 | KEY(0, 4, KEY_POWER), | 72 | KEY(4, 0, KEY_POWER), |
| 74 | KEY(1, 0, KEY_LEFT), | 73 | KEY(0, 1, KEY_LEFT), |
| 75 | KEY(1, 1, KEY_DOWN), | 74 | KEY(1, 1, KEY_DOWN), |
| 76 | KEY(1, 2, KEY_UP), | 75 | KEY(2, 1, KEY_UP), |
| 77 | KEY(1, 3, KEY_RIGHT), | 76 | KEY(3, 1, KEY_RIGHT), |
| 78 | KEY(1, 4, KEY_ENTER), | 77 | KEY(4, 1, KEY_ENTER), |
| 79 | KEY(2, 0, KEY_CAMERA), | 78 | KEY(0, 2, KEY_CAMERA), |
| 80 | 0, | 79 | }; |
| 80 | |||
| 81 | static const struct matrix_keymap_data palmz71_keymap_data = { | ||
| 82 | .keymap = palmz71_keymap, | ||
| 83 | .keymap_size = ARRAY_SIZE(palmz71_keymap), | ||
| 81 | }; | 84 | }; |
| 82 | 85 | ||
| 83 | static struct omap_kp_platform_data palmz71_kp_data = { | 86 | static struct omap_kp_platform_data palmz71_kp_data = { |
| 84 | .rows = 8, | 87 | .rows = 8, |
| 85 | .cols = 8, | 88 | .cols = 8, |
| 86 | .keymap = palmz71_keymap, | 89 | .keymap_data = &palmz71_keymap_data, |
| 87 | .rep = 1, | 90 | .rep = true, |
| 88 | .delay = 80, | 91 | .delay = 80, |
| 89 | }; | 92 | }; |
| 90 | 93 | ||
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c index a8d16a255c18..3c8ee8489458 100644 --- a/arch/arm/mach-omap1/board-perseus2.c +++ b/arch/arm/mach-omap1/board-perseus2.c | |||
| @@ -36,36 +36,35 @@ | |||
| 36 | #include <plat/common.h> | 36 | #include <plat/common.h> |
| 37 | #include <plat/board.h> | 37 | #include <plat/board.h> |
| 38 | 38 | ||
| 39 | static int p2_keymap[] = { | 39 | static const unsigned int p2_keymap[] = { |
| 40 | KEY(0,0,KEY_UP), | 40 | KEY(0, 0, KEY_UP), |
| 41 | KEY(0,1,KEY_RIGHT), | 41 | KEY(1, 0, KEY_RIGHT), |
| 42 | KEY(0,2,KEY_LEFT), | 42 | KEY(2, 0, KEY_LEFT), |
| 43 | KEY(0,3,KEY_DOWN), | 43 | KEY(3, 0, KEY_DOWN), |
| 44 | KEY(0,4,KEY_ENTER), | 44 | KEY(4, 0, KEY_ENTER), |
| 45 | KEY(1,0,KEY_F10), | 45 | KEY(0, 1, KEY_F10), |
| 46 | KEY(1,1,KEY_SEND), | 46 | KEY(1, 1, KEY_SEND), |
| 47 | KEY(1,2,KEY_END), | 47 | KEY(2, 1, KEY_END), |
| 48 | KEY(1,3,KEY_VOLUMEDOWN), | 48 | KEY(3, 1, KEY_VOLUMEDOWN), |
| 49 | KEY(1,4,KEY_VOLUMEUP), | 49 | KEY(4, 1, KEY_VOLUMEUP), |
| 50 | KEY(1,5,KEY_RECORD), | 50 | KEY(5, 1, KEY_RECORD), |
| 51 | KEY(2,0,KEY_F9), | 51 | KEY(0, 2, KEY_F9), |
| 52 | KEY(2,1,KEY_3), | 52 | KEY(1, 2, KEY_3), |
| 53 | KEY(2,2,KEY_6), | 53 | KEY(2, 2, KEY_6), |
| 54 | KEY(2,3,KEY_9), | 54 | KEY(3, 2, KEY_9), |
| 55 | KEY(2,4,KEY_KPDOT), | 55 | KEY(4, 2, KEY_KPDOT), |
| 56 | KEY(3,0,KEY_BACK), | 56 | KEY(0, 3, KEY_BACK), |
| 57 | KEY(3,1,KEY_2), | 57 | KEY(1, 3, KEY_2), |
| 58 | KEY(3,2,KEY_5), | 58 | KEY(2, 3, KEY_5), |
| 59 | KEY(3,3,KEY_8), | 59 | KEY(3, 3, KEY_8), |
| 60 | KEY(3,4,KEY_0), | 60 | KEY(4, 3, KEY_0), |
| 61 | KEY(3,5,KEY_KPSLASH), | 61 | KEY(5, 3, KEY_KPSLASH), |
| 62 | KEY(4,0,KEY_HOME), | 62 | KEY(0, 4, KEY_HOME), |
| 63 | KEY(4,1,KEY_1), | 63 | KEY(1, 4, KEY_1), |
| 64 | KEY(4,2,KEY_4), | 64 | KEY(2, 4, KEY_4), |
| 65 | KEY(4,3,KEY_7), | 65 | KEY(3, 4, KEY_7), |
| 66 | KEY(4,4,KEY_KPASTERISK), | 66 | KEY(4, 4, KEY_KPASTERISK), |
| 67 | KEY(4,5,KEY_POWER), | 67 | KEY(5, 4, KEY_POWER), |
| 68 | 0 | ||
| 69 | }; | 68 | }; |
| 70 | 69 | ||
| 71 | static struct smc91x_platdata smc91x_info = { | 70 | static struct smc91x_platdata smc91x_info = { |
| @@ -211,13 +210,17 @@ static struct resource kp_resources[] = { | |||
| 211 | }, | 210 | }, |
| 212 | }; | 211 | }; |
| 213 | 212 | ||
| 213 | static const struct matrix_keymap_data p2_keymap_data = { | ||
| 214 | .keymap = p2_keymap, | ||
| 215 | .keymap_size = ARRAY_SIZE(p2_keymap), | ||
| 216 | }; | ||
| 217 | |||
| 214 | static struct omap_kp_platform_data kp_data = { | 218 | static struct omap_kp_platform_data kp_data = { |
| 215 | .rows = 8, | 219 | .rows = 8, |
| 216 | .cols = 8, | 220 | .cols = 8, |
| 217 | .keymap = p2_keymap, | 221 | .keymap_data = &p2_keymap_data, |
| 218 | .keymapsize = ARRAY_SIZE(p2_keymap), | ||
| 219 | .delay = 4, | 222 | .delay = 4, |
| 220 | .dbounce = 1, | 223 | .dbounce = true, |
| 221 | }; | 224 | }; |
| 222 | 225 | ||
| 223 | static struct platform_device kp_device = { | 226 | static struct platform_device kp_device = { |
| @@ -251,8 +254,19 @@ static struct omap_board_config_kernel perseus2_config[] __initdata = { | |||
| 251 | { OMAP_TAG_LCD, &perseus2_lcd_config }, | 254 | { OMAP_TAG_LCD, &perseus2_lcd_config }, |
| 252 | }; | 255 | }; |
| 253 | 256 | ||
| 257 | static void __init perseus2_init_smc91x(void) | ||
| 258 | { | ||
| 259 | fpga_write(1, H2P2_DBG_FPGA_LAN_RESET); | ||
| 260 | mdelay(50); | ||
| 261 | fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1, | ||
| 262 | H2P2_DBG_FPGA_LAN_RESET); | ||
| 263 | mdelay(50); | ||
| 264 | } | ||
| 265 | |||
| 254 | static void __init omap_perseus2_init(void) | 266 | static void __init omap_perseus2_init(void) |
| 255 | { | 267 | { |
| 268 | perseus2_init_smc91x(); | ||
| 269 | |||
| 256 | if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0) | 270 | if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0) |
| 257 | BUG(); | 271 | BUG(); |
| 258 | gpio_direction_input(P2_NAND_RB_GPIO_PIN); | 272 | gpio_direction_input(P2_NAND_RB_GPIO_PIN); |
| @@ -280,21 +294,10 @@ static void __init omap_perseus2_init(void) | |||
| 280 | omap_register_i2c_bus(1, 100, NULL, 0); | 294 | omap_register_i2c_bus(1, 100, NULL, 0); |
| 281 | } | 295 | } |
| 282 | 296 | ||
| 283 | static void __init perseus2_init_smc91x(void) | ||
| 284 | { | ||
| 285 | fpga_write(1, H2P2_DBG_FPGA_LAN_RESET); | ||
| 286 | mdelay(50); | ||
| 287 | fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1, | ||
| 288 | H2P2_DBG_FPGA_LAN_RESET); | ||
| 289 | mdelay(50); | ||
| 290 | } | ||
| 291 | |||
| 292 | static void __init omap_perseus2_init_irq(void) | 297 | static void __init omap_perseus2_init_irq(void) |
| 293 | { | 298 | { |
| 294 | omap1_init_common_hw(); | 299 | omap1_init_common_hw(); |
| 295 | omap_init_irq(); | 300 | omap_init_irq(); |
| 296 | omap_gpio_init(); | ||
| 297 | perseus2_init_smc91x(); | ||
| 298 | } | 301 | } |
| 299 | /* Only FPGA needs to be mapped here. All others are done with ioremap */ | 302 | /* Only FPGA needs to be mapped here. All others are done with ioremap */ |
| 300 | static struct map_desc omap_perseus2_io_desc[] __initdata = { | 303 | static struct map_desc omap_perseus2_io_desc[] __initdata = { |
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c index d25f59e5a773..d41fe2d0616a 100644 --- a/arch/arm/mach-omap1/board-sx1.c +++ b/arch/arm/mach-omap1/board-sx1.c | |||
| @@ -164,36 +164,35 @@ EXPORT_SYMBOL(sx1_setusbpower); | |||
| 164 | 164 | ||
| 165 | /*----------- Keypad -------------------------*/ | 165 | /*----------- Keypad -------------------------*/ |
| 166 | 166 | ||
| 167 | static int sx1_keymap[] = { | 167 | static const unsigned int sx1_keymap[] = { |
| 168 | KEY(5, 3, GROUP_0 | 117), /* camera Qt::Key_F17 */ | 168 | KEY(3, 5, GROUP_0 | 117), /* camera Qt::Key_F17 */ |
| 169 | KEY(0, 4, GROUP_0 | 114), /* voice memo Qt::Key_F14 */ | 169 | KEY(4, 0, GROUP_0 | 114), /* voice memo Qt::Key_F14 */ |
| 170 | KEY(1, 4, GROUP_2 | 114), /* voice memo */ | 170 | KEY(4, 1, GROUP_2 | 114), /* voice memo */ |
| 171 | KEY(2, 4, GROUP_3 | 114), /* voice memo */ | 171 | KEY(4, 2, GROUP_3 | 114), /* voice memo */ |
| 172 | KEY(0, 0, GROUP_1 | KEY_F12), /* red button Qt::Key_Hangup */ | 172 | KEY(0, 0, GROUP_1 | KEY_F12), /* red button Qt::Key_Hangup */ |
| 173 | KEY(4, 3, GROUP_1 | KEY_LEFT), | 173 | KEY(3, 4, GROUP_1 | KEY_LEFT), |
| 174 | KEY(2, 3, GROUP_1 | KEY_DOWN), | 174 | KEY(3, 2, GROUP_1 | KEY_DOWN), |
| 175 | KEY(1, 3, GROUP_1 | KEY_RIGHT), | 175 | KEY(3, 1, GROUP_1 | KEY_RIGHT), |
| 176 | KEY(0, 3, GROUP_1 | KEY_UP), | 176 | KEY(3, 0, GROUP_1 | KEY_UP), |
| 177 | KEY(3, 3, GROUP_1 | KEY_POWER), /* joystick press or Qt::Key_Select */ | 177 | KEY(3, 3, GROUP_1 | KEY_POWER), /* joystick press or Qt::Key_Select */ |
| 178 | KEY(5, 0, GROUP_1 | KEY_1), | 178 | KEY(0, 5, GROUP_1 | KEY_1), |
| 179 | KEY(4, 0, GROUP_1 | KEY_2), | 179 | KEY(0, 4, GROUP_1 | KEY_2), |
| 180 | KEY(3, 0, GROUP_1 | KEY_3), | 180 | KEY(0, 3, GROUP_1 | KEY_3), |
| 181 | KEY(3, 4, GROUP_1 | KEY_4), | 181 | KEY(4, 3, GROUP_1 | KEY_4), |
| 182 | KEY(4, 4, GROUP_1 | KEY_5), | 182 | KEY(4, 4, GROUP_1 | KEY_5), |
| 183 | KEY(5, 4, GROUP_1 | KEY_KPASTERISK),/* "*" */ | 183 | KEY(4, 5, GROUP_1 | KEY_KPASTERISK),/* "*" */ |
| 184 | KEY(4, 1, GROUP_1 | KEY_6), | 184 | KEY(1, 4, GROUP_1 | KEY_6), |
| 185 | KEY(5, 1, GROUP_1 | KEY_7), | 185 | KEY(1, 5, GROUP_1 | KEY_7), |
| 186 | KEY(3, 1, GROUP_1 | KEY_8), | 186 | KEY(1, 3, GROUP_1 | KEY_8), |
| 187 | KEY(3, 2, GROUP_1 | KEY_9), | 187 | KEY(2, 3, GROUP_1 | KEY_9), |
| 188 | KEY(5, 2, GROUP_1 | KEY_0), | 188 | KEY(2, 5, GROUP_1 | KEY_0), |
| 189 | KEY(4, 2, GROUP_1 | 113), /* # F13 Toggle input method Qt::Key_F13 */ | 189 | KEY(2, 4, GROUP_1 | 113), /* # F13 Toggle input method Qt::Key_F13 */ |
| 190 | KEY(0, 1, GROUP_1 | KEY_F11), /* green button Qt::Key_Call */ | 190 | KEY(1, 0, GROUP_1 | KEY_F11), /* green button Qt::Key_Call */ |
| 191 | KEY(1, 2, GROUP_1 | KEY_YEN), /* left soft Qt::Key_Context1 */ | 191 | KEY(2, 1, GROUP_1 | KEY_YEN), /* left soft Qt::Key_Context1 */ |
| 192 | KEY(2, 2, GROUP_1 | KEY_F8), /* right soft Qt::Key_Back */ | 192 | KEY(2, 2, GROUP_1 | KEY_F8), /* right soft Qt::Key_Back */ |
| 193 | KEY(2, 1, GROUP_1 | KEY_LEFTSHIFT), /* shift */ | 193 | KEY(1, 2, GROUP_1 | KEY_LEFTSHIFT), /* shift */ |
| 194 | KEY(1, 1, GROUP_1 | KEY_BACKSPACE), /* C (clear) */ | 194 | KEY(1, 1, GROUP_1 | KEY_BACKSPACE), /* C (clear) */ |
| 195 | KEY(0, 2, GROUP_1 | KEY_F7), /* menu Qt::Key_Menu */ | 195 | KEY(2, 0, GROUP_1 | KEY_F7), /* menu Qt::Key_Menu */ |
| 196 | 0 | ||
| 197 | }; | 196 | }; |
| 198 | 197 | ||
| 199 | static struct resource sx1_kp_resources[] = { | 198 | static struct resource sx1_kp_resources[] = { |
| @@ -204,11 +203,15 @@ static struct resource sx1_kp_resources[] = { | |||
| 204 | }, | 203 | }, |
| 205 | }; | 204 | }; |
| 206 | 205 | ||
| 206 | static const struct matrix_keymap_data sx1_keymap_data = { | ||
| 207 | .keymap = sx1_keymap, | ||
| 208 | .keymap_size = ARRAY_SIZE(sx1_keymap), | ||
| 209 | }; | ||
| 210 | |||
| 207 | static struct omap_kp_platform_data sx1_kp_data = { | 211 | static struct omap_kp_platform_data sx1_kp_data = { |
| 208 | .rows = 6, | 212 | .rows = 6, |
| 209 | .cols = 6, | 213 | .cols = 6, |
| 210 | .keymap = sx1_keymap, | 214 | .keymap_data = &sx1_keymap_data, |
| 211 | .keymapsize = ARRAY_SIZE(sx1_keymap), | ||
| 212 | .delay = 80, | 215 | .delay = 80, |
| 213 | }; | 216 | }; |
| 214 | 217 | ||
| @@ -409,7 +412,6 @@ static void __init omap_sx1_init_irq(void) | |||
| 409 | { | 412 | { |
| 410 | omap1_init_common_hw(); | 413 | omap1_init_common_hw(); |
| 411 | omap_init_irq(); | 414 | omap_init_irq(); |
| 412 | omap_gpio_init(); | ||
| 413 | } | 415 | } |
| 414 | /*----------------------------------------*/ | 416 | /*----------------------------------------*/ |
| 415 | 417 | ||
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index f5992c239bcd..815a69ce821d 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c | |||
| @@ -83,6 +83,9 @@ static struct platform_device serial_device = { | |||
| 83 | 83 | ||
| 84 | static int __init ext_uart_init(void) | 84 | static int __init ext_uart_init(void) |
| 85 | { | 85 | { |
| 86 | if (!machine_is_voiceblue()) | ||
| 87 | return -ENODEV; | ||
| 88 | |||
| 86 | return platform_device_register(&serial_device); | 89 | return platform_device_register(&serial_device); |
| 87 | } | 90 | } |
| 88 | arch_initcall(ext_uart_init); | 91 | arch_initcall(ext_uart_init); |
| @@ -158,7 +161,6 @@ static void __init voiceblue_init_irq(void) | |||
| 158 | { | 161 | { |
| 159 | omap1_init_common_hw(); | 162 | omap1_init_common_hw(); |
| 160 | omap_init_irq(); | 163 | omap_init_irq(); |
| 161 | omap_gpio_init(); | ||
| 162 | } | 164 | } |
| 163 | 165 | ||
| 164 | static void __init voiceblue_init(void) | 166 | static void __init voiceblue_init(void) |
| @@ -236,6 +238,9 @@ static struct notifier_block panic_block = { | |||
| 236 | 238 | ||
| 237 | static int __init voiceblue_setup(void) | 239 | static int __init voiceblue_setup(void) |
| 238 | { | 240 | { |
| 241 | if (!machine_is_voiceblue()) | ||
| 242 | return -ENODEV; | ||
| 243 | |||
| 239 | /* Setup panic notifier */ | 244 | /* Setup panic notifier */ |
| 240 | atomic_notifier_chain_register(&panic_notifier_list, &panic_block); | 245 | atomic_notifier_chain_register(&panic_notifier_list, &panic_block); |
| 241 | 246 | ||
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index b8c7fb9d7921..84ef70476b51 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c | |||
| @@ -17,9 +17,9 @@ | |||
| 17 | #include <linux/err.h> | 17 | #include <linux/err.h> |
| 18 | #include <linux/clk.h> | 18 | #include <linux/clk.h> |
| 19 | #include <linux/io.h> | 19 | #include <linux/io.h> |
| 20 | #include <linux/clkdev.h> | ||
| 20 | 21 | ||
| 21 | #include <asm/mach-types.h> | 22 | #include <asm/mach-types.h> |
| 22 | #include <asm/clkdev.h> | ||
| 23 | 23 | ||
| 24 | #include <plat/cpu.h> | 24 | #include <plat/cpu.h> |
| 25 | #include <plat/usb.h> | 25 | #include <plat/usb.h> |
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index af54114b8f08..92400b9eb69f 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c | |||
| @@ -143,7 +143,7 @@ static struct arm_idlect1_clk armper_ck = { | |||
| 143 | * activation. [ GPIO code for 1510 ] | 143 | * activation. [ GPIO code for 1510 ] |
| 144 | */ | 144 | */ |
| 145 | static struct clk arm_gpio_ck = { | 145 | static struct clk arm_gpio_ck = { |
| 146 | .name = "arm_gpio_ck", | 146 | .name = "ick", |
| 147 | .ops = &clkops_generic, | 147 | .ops = &clkops_generic, |
| 148 | .parent = &ck_dpll1, | 148 | .parent = &ck_dpll1, |
| 149 | .flags = ENABLE_ON_INIT, | 149 | .flags = ENABLE_ON_INIT, |
| @@ -684,7 +684,7 @@ static struct omap_clk omap_clks[] = { | |||
| 684 | CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX), | 684 | CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX), |
| 685 | CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310), | 685 | CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310), |
| 686 | CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), | 686 | CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), |
| 687 | CLK(NULL, "arm_gpio_ck", &arm_gpio_ck, CK_1510 | CK_310), | 687 | CLK("omap_gpio.0", "ick", &arm_gpio_ck, CK_1510 | CK_310), |
| 688 | CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), | 688 | CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), |
| 689 | CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310), | 689 | CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310), |
| 690 | CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310), | 690 | CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310), |
| @@ -736,9 +736,9 @@ static struct omap_clk omap_clks[] = { | |||
| 736 | CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX), | 736 | CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX), |
| 737 | /* Virtual clocks */ | 737 | /* Virtual clocks */ |
| 738 | CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310), | 738 | CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310), |
| 739 | CLK("i2c_omap.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310 | CK_7XX), | 739 | CLK("omap_i2c.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310 | CK_7XX), |
| 740 | CLK("i2c_omap.1", "ick", &i2c_ick, CK_16XX), | 740 | CLK("omap_i2c.1", "ick", &i2c_ick, CK_16XX), |
| 741 | CLK("i2c_omap.1", "ick", &dummy_ck, CK_1510 | CK_310 | CK_7XX), | 741 | CLK("omap_i2c.1", "ick", &dummy_ck, CK_1510 | CK_310 | CK_7XX), |
| 742 | CLK("omap1_spi100k.1", "fck", &dummy_ck, CK_7XX), | 742 | CLK("omap1_spi100k.1", "fck", &dummy_ck, CK_7XX), |
| 743 | CLK("omap1_spi100k.1", "ick", &dummy_ck, CK_7XX), | 743 | CLK("omap1_spi100k.1", "ick", &dummy_ck, CK_7XX), |
| 744 | CLK("omap1_spi100k.2", "fck", &dummy_ck, CK_7XX), | 744 | CLK("omap1_spi100k.2", "fck", &dummy_ck, CK_7XX), |
| @@ -823,12 +823,10 @@ int __init omap1_clk_init(void) | |||
| 823 | crystal_type = info->system_clock_type; | 823 | crystal_type = info->system_clock_type; |
| 824 | } | 824 | } |
| 825 | 825 | ||
| 826 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) | 826 | if (cpu_is_omap7xx()) |
| 827 | ck_ref.rate = 13000000; | 827 | ck_ref.rate = 13000000; |
| 828 | #elif defined(CONFIG_ARCH_OMAP16XX) | 828 | if (cpu_is_omap16xx() && crystal_type == 2) |
| 829 | if (crystal_type == 2) | ||
| 830 | ck_ref.rate = 19200000; | 829 | ck_ref.rate = 19200000; |
| 831 | #endif | ||
| 832 | 830 | ||
| 833 | pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: " | 831 | pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: " |
| 834 | "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), | 832 | "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), |
| @@ -883,10 +881,11 @@ int __init omap1_clk_init(void) | |||
| 883 | ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, | 881 | ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, |
| 884 | arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); | 882 | arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); |
| 885 | 883 | ||
| 886 | #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE) | 884 | if (machine_is_omap_perseus2() || machine_is_omap_fsample()) { |
| 887 | /* Select slicer output as OMAP input clock */ | 885 | /* Select slicer output as OMAP input clock */ |
| 888 | omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL); | 886 | omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, |
| 889 | #endif | 887 | OMAP7XX_PCC_UPLD_CTRL); |
| 888 | } | ||
| 890 | 889 | ||
| 891 | /* Amstrad Delta wants BCLK high when inactive */ | 890 | /* Amstrad Delta wants BCLK high when inactive */ |
| 892 | if (machine_is_ams_delta()) | 891 | if (machine_is_ams_delta()) |
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c index e7f9ee63dce5..b0f4c231595f 100644 --- a/arch/arm/mach-omap1/devices.c +++ b/arch/arm/mach-omap1/devices.c | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | #include <linux/io.h> | 17 | #include <linux/io.h> |
| 18 | #include <linux/spi/spi.h> | 18 | #include <linux/spi/spi.h> |
| 19 | 19 | ||
| 20 | #include <mach/camera.h> | ||
| 20 | #include <mach/hardware.h> | 21 | #include <mach/hardware.h> |
| 21 | #include <asm/mach/map.h> | 22 | #include <asm/mach/map.h> |
| 22 | 23 | ||
| @@ -287,6 +288,9 @@ static inline void omap_init_audio(void) {} | |||
| 287 | */ | 288 | */ |
| 288 | static int __init omap1_init_devices(void) | 289 | static int __init omap1_init_devices(void) |
| 289 | { | 290 | { |
| 291 | if (!cpu_class_is_omap1()) | ||
| 292 | return -ENODEV; | ||
| 293 | |||
| 290 | /* please keep these calls, and their implementations above, | 294 | /* please keep these calls, and their implementations above, |
| 291 | * in alphabetical order so they're easier to sort through. | 295 | * in alphabetical order so they're easier to sort through. |
| 292 | */ | 296 | */ |
diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c new file mode 100644 index 000000000000..d8559344c6e2 --- /dev/null +++ b/arch/arm/mach-omap1/dma.c | |||
| @@ -0,0 +1,390 @@ | |||
| 1 | /* | ||
| 2 | * OMAP1/OMAP7xx - specific DMA driver | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 - 2008 Nokia Corporation | ||
| 5 | * Author: Juha Yrjölä <juha.yrjola@nokia.com> | ||
| 6 | * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com> | ||
| 7 | * Graphics DMA and LCD DMA graphics tranformations | ||
| 8 | * by Imre Deak <imre.deak@nokia.com> | ||
| 9 | * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc. | ||
| 10 | * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc. | ||
| 11 | * | ||
| 12 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 13 | * Converted DMA library into platform driver | ||
| 14 | * - G, Manjunath Kondaiah <manjugk@ti.com> | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or modify | ||
| 17 | * it under the terms of the GNU General Public License version 2 as | ||
| 18 | * published by the Free Software Foundation. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include <linux/err.h> | ||
| 22 | #include <linux/io.h> | ||
| 23 | #include <linux/slab.h> | ||
| 24 | #include <linux/module.h> | ||
| 25 | #include <linux/init.h> | ||
| 26 | #include <linux/device.h> | ||
| 27 | |||
| 28 | #include <plat/dma.h> | ||
| 29 | #include <plat/tc.h> | ||
| 30 | #include <plat/irqs.h> | ||
| 31 | |||
| 32 | #define OMAP1_DMA_BASE (0xfffed800) | ||
| 33 | #define OMAP1_LOGICAL_DMA_CH_COUNT 17 | ||
| 34 | #define OMAP1_DMA_STRIDE 0x40 | ||
| 35 | |||
| 36 | static u32 errata; | ||
| 37 | static u32 enable_1510_mode; | ||
| 38 | static u8 dma_stride; | ||
| 39 | static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end; | ||
| 40 | |||
| 41 | static u16 reg_map[] = { | ||
| 42 | [GCR] = 0x400, | ||
| 43 | [GSCR] = 0x404, | ||
| 44 | [GRST1] = 0x408, | ||
| 45 | [HW_ID] = 0x442, | ||
| 46 | [PCH2_ID] = 0x444, | ||
| 47 | [PCH0_ID] = 0x446, | ||
| 48 | [PCH1_ID] = 0x448, | ||
| 49 | [PCHG_ID] = 0x44a, | ||
| 50 | [PCHD_ID] = 0x44c, | ||
| 51 | [CAPS_0] = 0x44e, | ||
| 52 | [CAPS_1] = 0x452, | ||
| 53 | [CAPS_2] = 0x456, | ||
| 54 | [CAPS_3] = 0x458, | ||
| 55 | [CAPS_4] = 0x45a, | ||
| 56 | [PCH2_SR] = 0x460, | ||
| 57 | [PCH0_SR] = 0x480, | ||
| 58 | [PCH1_SR] = 0x482, | ||
| 59 | [PCHD_SR] = 0x4c0, | ||
| 60 | |||
| 61 | /* Common Registers */ | ||
| 62 | [CSDP] = 0x00, | ||
| 63 | [CCR] = 0x02, | ||
| 64 | [CICR] = 0x04, | ||
| 65 | [CSR] = 0x06, | ||
| 66 | [CEN] = 0x10, | ||
| 67 | [CFN] = 0x12, | ||
| 68 | [CSFI] = 0x14, | ||
| 69 | [CSEI] = 0x16, | ||
| 70 | [CPC] = 0x18, /* 15xx only */ | ||
| 71 | [CSAC] = 0x18, | ||
| 72 | [CDAC] = 0x1a, | ||
| 73 | [CDEI] = 0x1c, | ||
| 74 | [CDFI] = 0x1e, | ||
| 75 | [CLNK_CTRL] = 0x28, | ||
| 76 | |||
| 77 | /* Channel specific register offsets */ | ||
| 78 | [CSSA] = 0x08, | ||
| 79 | [CDSA] = 0x0c, | ||
| 80 | [COLOR] = 0x20, | ||
| 81 | [CCR2] = 0x24, | ||
| 82 | [LCH_CTRL] = 0x2a, | ||
| 83 | }; | ||
| 84 | |||
| 85 | static struct resource res[] __initdata = { | ||
| 86 | [0] = { | ||
| 87 | .start = OMAP1_DMA_BASE, | ||
| 88 | .end = OMAP1_DMA_BASE + SZ_2K - 1, | ||
| 89 | .flags = IORESOURCE_MEM, | ||
| 90 | }, | ||
| 91 | [1] = { | ||
| 92 | .name = "0", | ||
| 93 | .start = INT_DMA_CH0_6, | ||
| 94 | .flags = IORESOURCE_IRQ, | ||
| 95 | }, | ||
| 96 | [2] = { | ||
| 97 | .name = "1", | ||
| 98 | .start = INT_DMA_CH1_7, | ||
| 99 | .flags = IORESOURCE_IRQ, | ||
| 100 | }, | ||
| 101 | [3] = { | ||
| 102 | .name = "2", | ||
| 103 | .start = INT_DMA_CH2_8, | ||
| 104 | .flags = IORESOURCE_IRQ, | ||
| 105 | }, | ||
| 106 | [4] = { | ||
| 107 | .name = "3", | ||
| 108 | .start = INT_DMA_CH3, | ||
| 109 | .flags = IORESOURCE_IRQ, | ||
| 110 | }, | ||
| 111 | [5] = { | ||
| 112 | .name = "4", | ||
| 113 | .start = INT_DMA_CH4, | ||
| 114 | .flags = IORESOURCE_IRQ, | ||
| 115 | }, | ||
| 116 | [6] = { | ||
| 117 | .name = "5", | ||
| 118 | .start = INT_DMA_CH5, | ||
| 119 | .flags = IORESOURCE_IRQ, | ||
| 120 | }, | ||
| 121 | /* Handled in lcd_dma.c */ | ||
| 122 | [7] = { | ||
| 123 | .name = "6", | ||
| 124 | .start = INT_1610_DMA_CH6, | ||
| 125 | .flags = IORESOURCE_IRQ, | ||
| 126 | }, | ||
| 127 | /* irq's for omap16xx and omap7xx */ | ||
| 128 | [8] = { | ||
| 129 | .name = "7", | ||
| 130 | .start = INT_1610_DMA_CH7, | ||
| 131 | .flags = IORESOURCE_IRQ, | ||
| 132 | }, | ||
| 133 | [9] = { | ||
| 134 | .name = "8", | ||
| 135 | .start = INT_1610_DMA_CH8, | ||
| 136 | .flags = IORESOURCE_IRQ, | ||
| 137 | }, | ||
| 138 | [10] = { | ||
| 139 | .name = "9", | ||
| 140 | .start = INT_1610_DMA_CH9, | ||
| 141 | .flags = IORESOURCE_IRQ, | ||
| 142 | }, | ||
| 143 | [11] = { | ||
| 144 | .name = "10", | ||
| 145 | .start = INT_1610_DMA_CH10, | ||
| 146 | .flags = IORESOURCE_IRQ, | ||
| 147 | }, | ||
| 148 | [12] = { | ||
| 149 | .name = "11", | ||
| 150 | .start = INT_1610_DMA_CH11, | ||
| 151 | .flags = IORESOURCE_IRQ, | ||
| 152 | }, | ||
| 153 | [13] = { | ||
| 154 | .name = "12", | ||
| 155 | .start = INT_1610_DMA_CH12, | ||
| 156 | .flags = IORESOURCE_IRQ, | ||
| 157 | }, | ||
| 158 | [14] = { | ||
| 159 | .name = "13", | ||
| 160 | .start = INT_1610_DMA_CH13, | ||
| 161 | .flags = IORESOURCE_IRQ, | ||
| 162 | }, | ||
| 163 | [15] = { | ||
| 164 | .name = "14", | ||
| 165 | .start = INT_1610_DMA_CH14, | ||
| 166 | .flags = IORESOURCE_IRQ, | ||
| 167 | }, | ||
| 168 | [16] = { | ||
| 169 | .name = "15", | ||
| 170 | .start = INT_1610_DMA_CH15, | ||
| 171 | .flags = IORESOURCE_IRQ, | ||
| 172 | }, | ||
| 173 | [17] = { | ||
| 174 | .name = "16", | ||
| 175 | .start = INT_DMA_LCD, | ||
| 176 | .flags = IORESOURCE_IRQ, | ||
| 177 | }, | ||
| 178 | }; | ||
| 179 | |||
| 180 | static void __iomem *dma_base; | ||
| 181 | static inline void dma_write(u32 val, int reg, int lch) | ||
| 182 | { | ||
| 183 | u8 stride; | ||
| 184 | u32 offset; | ||
| 185 | |||
| 186 | stride = (reg >= dma_common_ch_start) ? dma_stride : 0; | ||
| 187 | offset = reg_map[reg] + (stride * lch); | ||
| 188 | |||
| 189 | __raw_writew(val, dma_base + offset); | ||
| 190 | if ((reg > CLNK_CTRL && reg < CCEN) || | ||
| 191 | (reg > PCHD_ID && reg < CAPS_2)) { | ||
| 192 | u32 offset2 = reg_map[reg] + 2 + (stride * lch); | ||
| 193 | __raw_writew(val >> 16, dma_base + offset2); | ||
| 194 | } | ||
| 195 | } | ||
| 196 | |||
| 197 | static inline u32 dma_read(int reg, int lch) | ||
| 198 | { | ||
| 199 | u8 stride; | ||
| 200 | u32 offset, val; | ||
| 201 | |||
| 202 | stride = (reg >= dma_common_ch_start) ? dma_stride : 0; | ||
| 203 | offset = reg_map[reg] + (stride * lch); | ||
| 204 | |||
| 205 | val = __raw_readw(dma_base + offset); | ||
| 206 | if ((reg > CLNK_CTRL && reg < CCEN) || | ||
| 207 | (reg > PCHD_ID && reg < CAPS_2)) { | ||
| 208 | u16 upper; | ||
| 209 | u32 offset2 = reg_map[reg] + 2 + (stride * lch); | ||
| 210 | upper = __raw_readw(dma_base + offset2); | ||
| 211 | val |= (upper << 16); | ||
| 212 | } | ||
| 213 | return val; | ||
| 214 | } | ||
| 215 | |||
| 216 | static void omap1_clear_lch_regs(int lch) | ||
| 217 | { | ||
| 218 | int i = dma_common_ch_start; | ||
| 219 | |||
| 220 | for (; i <= dma_common_ch_end; i += 1) | ||
| 221 | dma_write(0, i, lch); | ||
| 222 | } | ||
| 223 | |||
| 224 | static void omap1_clear_dma(int lch) | ||
| 225 | { | ||
| 226 | u32 l; | ||
| 227 | |||
| 228 | l = dma_read(CCR, lch); | ||
| 229 | l &= ~OMAP_DMA_CCR_EN; | ||
| 230 | dma_write(l, CCR, lch); | ||
| 231 | |||
| 232 | /* Clear pending interrupts */ | ||
| 233 | l = dma_read(CSR, lch); | ||
| 234 | } | ||
| 235 | |||
| 236 | static void omap1_show_dma_caps(void) | ||
| 237 | { | ||
| 238 | if (enable_1510_mode) { | ||
| 239 | printk(KERN_INFO "DMA support for OMAP15xx initialized\n"); | ||
| 240 | } else { | ||
| 241 | u16 w; | ||
| 242 | printk(KERN_INFO "OMAP DMA hardware version %d\n", | ||
| 243 | dma_read(HW_ID, 0)); | ||
| 244 | printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n", | ||
| 245 | dma_read(CAPS_0, 0), dma_read(CAPS_1, 0), | ||
| 246 | dma_read(CAPS_2, 0), dma_read(CAPS_3, 0), | ||
| 247 | dma_read(CAPS_4, 0)); | ||
| 248 | |||
| 249 | /* Disable OMAP 3.0/3.1 compatibility mode. */ | ||
| 250 | w = dma_read(GSCR, 0); | ||
| 251 | w |= 1 << 3; | ||
| 252 | dma_write(w, GSCR, 0); | ||
| 253 | } | ||
| 254 | return; | ||
| 255 | } | ||
| 256 | |||
| 257 | static u32 configure_dma_errata(void) | ||
| 258 | { | ||
| 259 | |||
| 260 | /* | ||
| 261 | * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is | ||
| 262 | * read before the DMA controller finished disabling the channel. | ||
| 263 | */ | ||
| 264 | if (!cpu_is_omap15xx()) | ||
| 265 | SET_DMA_ERRATA(DMA_ERRATA_3_3); | ||
| 266 | |||
| 267 | return errata; | ||
| 268 | } | ||
| 269 | |||
| 270 | static int __init omap1_system_dma_init(void) | ||
| 271 | { | ||
| 272 | struct omap_system_dma_plat_info *p; | ||
| 273 | struct omap_dma_dev_attr *d; | ||
| 274 | struct platform_device *pdev; | ||
| 275 | int ret; | ||
| 276 | |||
| 277 | pdev = platform_device_alloc("omap_dma_system", 0); | ||
| 278 | if (!pdev) { | ||
| 279 | pr_err("%s: Unable to device alloc for dma\n", | ||
| 280 | __func__); | ||
| 281 | return -ENOMEM; | ||
| 282 | } | ||
| 283 | |||
| 284 | dma_base = ioremap(res[0].start, resource_size(&res[0])); | ||
| 285 | if (!dma_base) { | ||
| 286 | pr_err("%s: Unable to ioremap\n", __func__); | ||
| 287 | return -ENODEV; | ||
| 288 | } | ||
| 289 | |||
| 290 | ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res)); | ||
| 291 | if (ret) { | ||
| 292 | dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n", | ||
| 293 | __func__, pdev->name, pdev->id); | ||
| 294 | goto exit_device_del; | ||
| 295 | } | ||
| 296 | |||
| 297 | p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL); | ||
| 298 | if (!p) { | ||
| 299 | dev_err(&pdev->dev, "%s: Unable to allocate 'p' for %s\n", | ||
| 300 | __func__, pdev->name); | ||
| 301 | ret = -ENOMEM; | ||
| 302 | goto exit_device_put; | ||
| 303 | } | ||
| 304 | |||
| 305 | d = kzalloc(sizeof(struct omap_dma_dev_attr), GFP_KERNEL); | ||
| 306 | if (!d) { | ||
| 307 | dev_err(&pdev->dev, "%s: Unable to allocate 'd' for %s\n", | ||
| 308 | __func__, pdev->name); | ||
| 309 | ret = -ENOMEM; | ||
| 310 | goto exit_release_p; | ||
| 311 | } | ||
| 312 | |||
| 313 | d->lch_count = OMAP1_LOGICAL_DMA_CH_COUNT; | ||
| 314 | |||
| 315 | /* Valid attributes for omap1 plus processors */ | ||
| 316 | if (cpu_is_omap15xx()) | ||
| 317 | d->dev_caps = ENABLE_1510_MODE; | ||
| 318 | enable_1510_mode = d->dev_caps & ENABLE_1510_MODE; | ||
| 319 | |||
| 320 | d->dev_caps |= SRC_PORT; | ||
| 321 | d->dev_caps |= DST_PORT; | ||
| 322 | d->dev_caps |= SRC_INDEX; | ||
| 323 | d->dev_caps |= DST_INDEX; | ||
| 324 | d->dev_caps |= IS_BURST_ONLY4; | ||
| 325 | d->dev_caps |= CLEAR_CSR_ON_READ; | ||
| 326 | d->dev_caps |= IS_WORD_16; | ||
| 327 | |||
| 328 | |||
| 329 | d->chan = kzalloc(sizeof(struct omap_dma_lch) * | ||
| 330 | (d->lch_count), GFP_KERNEL); | ||
| 331 | if (!d->chan) { | ||
| 332 | dev_err(&pdev->dev, "%s: Memory allocation failed" | ||
| 333 | "for d->chan!!!\n", __func__); | ||
| 334 | goto exit_release_d; | ||
| 335 | } | ||
| 336 | |||
| 337 | if (cpu_is_omap15xx()) | ||
| 338 | d->chan_count = 9; | ||
| 339 | else if (cpu_is_omap16xx() || cpu_is_omap7xx()) { | ||
| 340 | if (!(d->dev_caps & ENABLE_1510_MODE)) | ||
| 341 | d->chan_count = 16; | ||
| 342 | else | ||
| 343 | d->chan_count = 9; | ||
| 344 | } | ||
| 345 | |||
| 346 | p->dma_attr = d; | ||
| 347 | |||
| 348 | p->show_dma_caps = omap1_show_dma_caps; | ||
| 349 | p->clear_lch_regs = omap1_clear_lch_regs; | ||
| 350 | p->clear_dma = omap1_clear_dma; | ||
| 351 | p->dma_write = dma_write; | ||
| 352 | p->dma_read = dma_read; | ||
| 353 | p->disable_irq_lch = NULL; | ||
| 354 | |||
| 355 | p->errata = configure_dma_errata(); | ||
| 356 | |||
| 357 | ret = platform_device_add_data(pdev, p, sizeof(*p)); | ||
| 358 | if (ret) { | ||
| 359 | dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n", | ||
| 360 | __func__, pdev->name, pdev->id); | ||
| 361 | goto exit_release_chan; | ||
| 362 | } | ||
| 363 | |||
| 364 | ret = platform_device_add(pdev); | ||
| 365 | if (ret) { | ||
| 366 | dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n", | ||
| 367 | __func__, pdev->name, pdev->id); | ||
| 368 | goto exit_release_chan; | ||
| 369 | } | ||
| 370 | |||
| 371 | dma_stride = OMAP1_DMA_STRIDE; | ||
| 372 | dma_common_ch_start = CPC; | ||
| 373 | dma_common_ch_end = COLOR; | ||
| 374 | |||
| 375 | return ret; | ||
| 376 | |||
| 377 | exit_release_chan: | ||
| 378 | kfree(d->chan); | ||
| 379 | exit_release_d: | ||
| 380 | kfree(d); | ||
| 381 | exit_release_p: | ||
| 382 | kfree(p); | ||
| 383 | exit_device_put: | ||
| 384 | platform_device_put(pdev); | ||
| 385 | exit_device_del: | ||
| 386 | platform_device_del(pdev); | ||
| 387 | |||
| 388 | return ret; | ||
| 389 | } | ||
| 390 | arch_initcall(omap1_system_dma_init); | ||
diff --git a/arch/arm/mach-omap1/flash.c b/arch/arm/mach-omap1/flash.c index 0b07a78eeaa7..acd161666408 100644 --- a/arch/arm/mach-omap1/flash.c +++ b/arch/arm/mach-omap1/flash.c | |||
| @@ -11,6 +11,7 @@ | |||
| 11 | 11 | ||
| 12 | #include <plat/io.h> | 12 | #include <plat/io.h> |
| 13 | #include <plat/tc.h> | 13 | #include <plat/tc.h> |
| 14 | #include <plat/flash.h> | ||
| 14 | 15 | ||
| 15 | void omap1_set_vpp(struct map_info *map, int enable) | 16 | void omap1_set_vpp(struct map_info *map, int enable) |
| 16 | { | 17 | { |
diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c index 5cfce1636da0..8780e75cdc3d 100644 --- a/arch/arm/mach-omap1/fpga.c +++ b/arch/arm/mach-omap1/fpga.c | |||
| @@ -143,7 +143,7 @@ static struct irq_chip omap_fpga_irq = { | |||
| 143 | */ | 143 | */ |
| 144 | void omap1510_fpga_init_irq(void) | 144 | void omap1510_fpga_init_irq(void) |
| 145 | { | 145 | { |
| 146 | int i; | 146 | int i, res; |
| 147 | 147 | ||
| 148 | __raw_writeb(0, OMAP1510_FPGA_IMR_LO); | 148 | __raw_writeb(0, OMAP1510_FPGA_IMR_LO); |
| 149 | __raw_writeb(0, OMAP1510_FPGA_IMR_HI); | 149 | __raw_writeb(0, OMAP1510_FPGA_IMR_HI); |
| @@ -177,10 +177,12 @@ void omap1510_fpga_init_irq(void) | |||
| 177 | * NOTE: For general GPIO/MPUIO access and interrupts, please see | 177 | * NOTE: For general GPIO/MPUIO access and interrupts, please see |
| 178 | * gpio.[ch] | 178 | * gpio.[ch] |
| 179 | */ | 179 | */ |
| 180 | gpio_request(13, "FPGA irq"); | 180 | res = gpio_request(13, "FPGA irq"); |
| 181 | if (res) { | ||
| 182 | pr_err("%s failed to get gpio\n", __func__); | ||
| 183 | return; | ||
| 184 | } | ||
| 181 | gpio_direction_input(13); | 185 | gpio_direction_input(13); |
| 182 | set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); | 186 | set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); |
| 183 | set_irq_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux); | 187 | set_irq_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux); |
| 184 | } | 188 | } |
| 185 | |||
| 186 | EXPORT_SYMBOL(omap1510_fpga_init_irq); | ||
diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c new file mode 100644 index 000000000000..04c4b04cf54e --- /dev/null +++ b/arch/arm/mach-omap1/gpio15xx.c | |||
| @@ -0,0 +1,99 @@ | |||
| 1 | /* | ||
| 2 | * OMAP15xx specific gpio init | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 5 | * | ||
| 6 | * Author: | ||
| 7 | * Charulatha V <charu@ti.com> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or | ||
| 10 | * modify it under the terms of the GNU General Public License as | ||
| 11 | * published by the Free Software Foundation version 2. | ||
| 12 | * | ||
| 13 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
| 14 | * kind, whether express or implied; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/gpio.h> | ||
| 20 | |||
| 21 | #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE | ||
| 22 | #define OMAP1510_GPIO_BASE 0xFFFCE000 | ||
| 23 | |||
| 24 | /* gpio1 */ | ||
| 25 | static struct __initdata resource omap15xx_mpu_gpio_resources[] = { | ||
| 26 | { | ||
| 27 | .start = OMAP1_MPUIO_VBASE, | ||
| 28 | .end = OMAP1_MPUIO_VBASE + SZ_2K - 1, | ||
| 29 | .flags = IORESOURCE_MEM, | ||
| 30 | }, | ||
| 31 | { | ||
| 32 | .start = INT_MPUIO, | ||
| 33 | .flags = IORESOURCE_IRQ, | ||
| 34 | }, | ||
| 35 | }; | ||
| 36 | |||
| 37 | static struct __initdata omap_gpio_platform_data omap15xx_mpu_gpio_config = { | ||
| 38 | .virtual_irq_start = IH_MPUIO_BASE, | ||
| 39 | .bank_type = METHOD_MPUIO, | ||
| 40 | .bank_width = 16, | ||
| 41 | .bank_stride = 1, | ||
| 42 | }; | ||
| 43 | |||
| 44 | static struct __initdata platform_device omap15xx_mpu_gpio = { | ||
| 45 | .name = "omap_gpio", | ||
| 46 | .id = 0, | ||
| 47 | .dev = { | ||
| 48 | .platform_data = &omap15xx_mpu_gpio_config, | ||
| 49 | }, | ||
| 50 | .num_resources = ARRAY_SIZE(omap15xx_mpu_gpio_resources), | ||
| 51 | .resource = omap15xx_mpu_gpio_resources, | ||
| 52 | }; | ||
| 53 | |||
| 54 | /* gpio2 */ | ||
| 55 | static struct __initdata resource omap15xx_gpio_resources[] = { | ||
| 56 | { | ||
| 57 | .start = OMAP1510_GPIO_BASE, | ||
| 58 | .end = OMAP1510_GPIO_BASE + SZ_2K - 1, | ||
| 59 | .flags = IORESOURCE_MEM, | ||
| 60 | }, | ||
| 61 | { | ||
| 62 | .start = INT_GPIO_BANK1, | ||
| 63 | .flags = IORESOURCE_IRQ, | ||
| 64 | }, | ||
| 65 | }; | ||
| 66 | |||
| 67 | static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = { | ||
| 68 | .virtual_irq_start = IH_GPIO_BASE, | ||
| 69 | .bank_type = METHOD_GPIO_1510, | ||
| 70 | .bank_width = 16, | ||
| 71 | }; | ||
| 72 | |||
| 73 | static struct __initdata platform_device omap15xx_gpio = { | ||
| 74 | .name = "omap_gpio", | ||
| 75 | .id = 1, | ||
| 76 | .dev = { | ||
| 77 | .platform_data = &omap15xx_gpio_config, | ||
| 78 | }, | ||
| 79 | .num_resources = ARRAY_SIZE(omap15xx_gpio_resources), | ||
| 80 | .resource = omap15xx_gpio_resources, | ||
| 81 | }; | ||
| 82 | |||
| 83 | /* | ||
| 84 | * omap15xx_gpio_init needs to be done before | ||
| 85 | * machine_init functions access gpio APIs. | ||
| 86 | * Hence omap15xx_gpio_init is a postcore_initcall. | ||
| 87 | */ | ||
| 88 | static int __init omap15xx_gpio_init(void) | ||
| 89 | { | ||
| 90 | if (!cpu_is_omap15xx()) | ||
| 91 | return -EINVAL; | ||
| 92 | |||
| 93 | platform_device_register(&omap15xx_mpu_gpio); | ||
| 94 | platform_device_register(&omap15xx_gpio); | ||
| 95 | |||
| 96 | gpio_bank_count = 2; | ||
| 97 | return 0; | ||
| 98 | } | ||
| 99 | postcore_initcall(omap15xx_gpio_init); | ||
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c new file mode 100644 index 000000000000..5dd0d4c82b24 --- /dev/null +++ b/arch/arm/mach-omap1/gpio16xx.c | |||
| @@ -0,0 +1,200 @@ | |||
| 1 | /* | ||
| 2 | * OMAP16xx specific gpio init | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 5 | * | ||
| 6 | * Author: | ||
| 7 | * Charulatha V <charu@ti.com> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or | ||
| 10 | * modify it under the terms of the GNU General Public License as | ||
| 11 | * published by the Free Software Foundation version 2. | ||
| 12 | * | ||
| 13 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
| 14 | * kind, whether express or implied; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/gpio.h> | ||
| 20 | |||
| 21 | #define OMAP1610_GPIO1_BASE 0xfffbe400 | ||
| 22 | #define OMAP1610_GPIO2_BASE 0xfffbec00 | ||
| 23 | #define OMAP1610_GPIO3_BASE 0xfffbb400 | ||
| 24 | #define OMAP1610_GPIO4_BASE 0xfffbbc00 | ||
| 25 | #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE | ||
| 26 | |||
| 27 | /* mpu gpio */ | ||
| 28 | static struct __initdata resource omap16xx_mpu_gpio_resources[] = { | ||
| 29 | { | ||
| 30 | .start = OMAP1_MPUIO_VBASE, | ||
| 31 | .end = OMAP1_MPUIO_VBASE + SZ_2K - 1, | ||
| 32 | .flags = IORESOURCE_MEM, | ||
| 33 | }, | ||
| 34 | { | ||
| 35 | .start = INT_MPUIO, | ||
| 36 | .flags = IORESOURCE_IRQ, | ||
| 37 | }, | ||
| 38 | }; | ||
| 39 | |||
| 40 | static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = { | ||
| 41 | .virtual_irq_start = IH_MPUIO_BASE, | ||
| 42 | .bank_type = METHOD_MPUIO, | ||
| 43 | .bank_width = 16, | ||
| 44 | .bank_stride = 1, | ||
| 45 | }; | ||
| 46 | |||
| 47 | static struct __initdata platform_device omap16xx_mpu_gpio = { | ||
| 48 | .name = "omap_gpio", | ||
| 49 | .id = 0, | ||
| 50 | .dev = { | ||
| 51 | .platform_data = &omap16xx_mpu_gpio_config, | ||
| 52 | }, | ||
| 53 | .num_resources = ARRAY_SIZE(omap16xx_mpu_gpio_resources), | ||
| 54 | .resource = omap16xx_mpu_gpio_resources, | ||
| 55 | }; | ||
| 56 | |||
| 57 | /* gpio1 */ | ||
| 58 | static struct __initdata resource omap16xx_gpio1_resources[] = { | ||
| 59 | { | ||
| 60 | .start = OMAP1610_GPIO1_BASE, | ||
| 61 | .end = OMAP1610_GPIO1_BASE + SZ_2K - 1, | ||
| 62 | .flags = IORESOURCE_MEM, | ||
| 63 | }, | ||
| 64 | { | ||
| 65 | .start = INT_GPIO_BANK1, | ||
| 66 | .flags = IORESOURCE_IRQ, | ||
| 67 | }, | ||
| 68 | }; | ||
| 69 | |||
| 70 | static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = { | ||
| 71 | .virtual_irq_start = IH_GPIO_BASE, | ||
| 72 | .bank_type = METHOD_GPIO_1610, | ||
| 73 | .bank_width = 16, | ||
| 74 | }; | ||
| 75 | |||
| 76 | static struct __initdata platform_device omap16xx_gpio1 = { | ||
| 77 | .name = "omap_gpio", | ||
| 78 | .id = 1, | ||
| 79 | .dev = { | ||
| 80 | .platform_data = &omap16xx_gpio1_config, | ||
| 81 | }, | ||
| 82 | .num_resources = ARRAY_SIZE(omap16xx_gpio1_resources), | ||
| 83 | .resource = omap16xx_gpio1_resources, | ||
| 84 | }; | ||
| 85 | |||
| 86 | /* gpio2 */ | ||
| 87 | static struct __initdata resource omap16xx_gpio2_resources[] = { | ||
| 88 | { | ||
| 89 | .start = OMAP1610_GPIO2_BASE, | ||
| 90 | .end = OMAP1610_GPIO2_BASE + SZ_2K - 1, | ||
| 91 | .flags = IORESOURCE_MEM, | ||
| 92 | }, | ||
| 93 | { | ||
| 94 | .start = INT_1610_GPIO_BANK2, | ||
| 95 | .flags = IORESOURCE_IRQ, | ||
| 96 | }, | ||
| 97 | }; | ||
| 98 | |||
| 99 | static struct __initdata omap_gpio_platform_data omap16xx_gpio2_config = { | ||
| 100 | .virtual_irq_start = IH_GPIO_BASE + 16, | ||
| 101 | .bank_type = METHOD_GPIO_1610, | ||
| 102 | .bank_width = 16, | ||
| 103 | }; | ||
| 104 | |||
| 105 | static struct __initdata platform_device omap16xx_gpio2 = { | ||
| 106 | .name = "omap_gpio", | ||
| 107 | .id = 2, | ||
| 108 | .dev = { | ||
| 109 | .platform_data = &omap16xx_gpio2_config, | ||
| 110 | }, | ||
| 111 | .num_resources = ARRAY_SIZE(omap16xx_gpio2_resources), | ||
| 112 | .resource = omap16xx_gpio2_resources, | ||
| 113 | }; | ||
| 114 | |||
| 115 | /* gpio3 */ | ||
| 116 | static struct __initdata resource omap16xx_gpio3_resources[] = { | ||
| 117 | { | ||
| 118 | .start = OMAP1610_GPIO3_BASE, | ||
| 119 | .end = OMAP1610_GPIO3_BASE + SZ_2K - 1, | ||
| 120 | .flags = IORESOURCE_MEM, | ||
| 121 | }, | ||
| 122 | { | ||
| 123 | .start = INT_1610_GPIO_BANK3, | ||
| 124 | .flags = IORESOURCE_IRQ, | ||
| 125 | }, | ||
| 126 | }; | ||
| 127 | |||
| 128 | static struct __initdata omap_gpio_platform_data omap16xx_gpio3_config = { | ||
| 129 | .virtual_irq_start = IH_GPIO_BASE + 32, | ||
| 130 | .bank_type = METHOD_GPIO_1610, | ||
| 131 | .bank_width = 16, | ||
| 132 | }; | ||
| 133 | |||
| 134 | static struct __initdata platform_device omap16xx_gpio3 = { | ||
| 135 | .name = "omap_gpio", | ||
| 136 | .id = 3, | ||
| 137 | .dev = { | ||
| 138 | .platform_data = &omap16xx_gpio3_config, | ||
| 139 | }, | ||
| 140 | .num_resources = ARRAY_SIZE(omap16xx_gpio3_resources), | ||
| 141 | .resource = omap16xx_gpio3_resources, | ||
| 142 | }; | ||
| 143 | |||
| 144 | /* gpio4 */ | ||
| 145 | static struct __initdata resource omap16xx_gpio4_resources[] = { | ||
| 146 | { | ||
| 147 | .start = OMAP1610_GPIO4_BASE, | ||
| 148 | .end = OMAP1610_GPIO4_BASE + SZ_2K - 1, | ||
| 149 | .flags = IORESOURCE_MEM, | ||
| 150 | }, | ||
| 151 | { | ||
| 152 | .start = INT_1610_GPIO_BANK4, | ||
| 153 | .flags = IORESOURCE_IRQ, | ||
| 154 | }, | ||
| 155 | }; | ||
| 156 | |||
| 157 | static struct __initdata omap_gpio_platform_data omap16xx_gpio4_config = { | ||
| 158 | .virtual_irq_start = IH_GPIO_BASE + 48, | ||
| 159 | .bank_type = METHOD_GPIO_1610, | ||
| 160 | .bank_width = 16, | ||
| 161 | }; | ||
| 162 | |||
| 163 | static struct __initdata platform_device omap16xx_gpio4 = { | ||
| 164 | .name = "omap_gpio", | ||
| 165 | .id = 4, | ||
| 166 | .dev = { | ||
| 167 | .platform_data = &omap16xx_gpio4_config, | ||
| 168 | }, | ||
| 169 | .num_resources = ARRAY_SIZE(omap16xx_gpio4_resources), | ||
| 170 | .resource = omap16xx_gpio4_resources, | ||
| 171 | }; | ||
| 172 | |||
| 173 | static struct __initdata platform_device * omap16xx_gpio_dev[] = { | ||
| 174 | &omap16xx_mpu_gpio, | ||
| 175 | &omap16xx_gpio1, | ||
| 176 | &omap16xx_gpio2, | ||
| 177 | &omap16xx_gpio3, | ||
| 178 | &omap16xx_gpio4, | ||
| 179 | }; | ||
| 180 | |||
| 181 | /* | ||
| 182 | * omap16xx_gpio_init needs to be done before | ||
| 183 | * machine_init functions access gpio APIs. | ||
| 184 | * Hence omap16xx_gpio_init is a postcore_initcall. | ||
| 185 | */ | ||
| 186 | static int __init omap16xx_gpio_init(void) | ||
| 187 | { | ||
| 188 | int i; | ||
| 189 | |||
| 190 | if (!cpu_is_omap16xx()) | ||
| 191 | return -EINVAL; | ||
| 192 | |||
| 193 | for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++) | ||
| 194 | platform_device_register(omap16xx_gpio_dev[i]); | ||
| 195 | |||
| 196 | gpio_bank_count = ARRAY_SIZE(omap16xx_gpio_dev); | ||
| 197 | |||
| 198 | return 0; | ||
| 199 | } | ||
| 200 | postcore_initcall(omap16xx_gpio_init); | ||
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c new file mode 100644 index 000000000000..1204c8b871af --- /dev/null +++ b/arch/arm/mach-omap1/gpio7xx.c | |||
| @@ -0,0 +1,262 @@ | |||
| 1 | /* | ||
| 2 | * OMAP7xx specific gpio init | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 5 | * | ||
| 6 | * Author: | ||
| 7 | * Charulatha V <charu@ti.com> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or | ||
| 10 | * modify it under the terms of the GNU General Public License as | ||
| 11 | * published by the Free Software Foundation version 2. | ||
| 12 | * | ||
| 13 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
| 14 | * kind, whether express or implied; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/gpio.h> | ||
| 20 | |||
| 21 | #define OMAP7XX_GPIO1_BASE 0xfffbc000 | ||
| 22 | #define OMAP7XX_GPIO2_BASE 0xfffbc800 | ||
| 23 | #define OMAP7XX_GPIO3_BASE 0xfffbd000 | ||
| 24 | #define OMAP7XX_GPIO4_BASE 0xfffbd800 | ||
| 25 | #define OMAP7XX_GPIO5_BASE 0xfffbe000 | ||
| 26 | #define OMAP7XX_GPIO6_BASE 0xfffbe800 | ||
| 27 | #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE | ||
| 28 | |||
| 29 | /* mpu gpio */ | ||
| 30 | static struct __initdata resource omap7xx_mpu_gpio_resources[] = { | ||
| 31 | { | ||
| 32 | .start = OMAP1_MPUIO_VBASE, | ||
| 33 | .end = OMAP1_MPUIO_VBASE + SZ_2K - 1, | ||
| 34 | .flags = IORESOURCE_MEM, | ||
| 35 | }, | ||
| 36 | { | ||
| 37 | .start = INT_7XX_MPUIO, | ||
| 38 | .flags = IORESOURCE_IRQ, | ||
| 39 | }, | ||
| 40 | }; | ||
| 41 | |||
| 42 | static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = { | ||
| 43 | .virtual_irq_start = IH_MPUIO_BASE, | ||
| 44 | .bank_type = METHOD_MPUIO, | ||
| 45 | .bank_width = 32, | ||
| 46 | .bank_stride = 2, | ||
| 47 | }; | ||
| 48 | |||
| 49 | static struct __initdata platform_device omap7xx_mpu_gpio = { | ||
| 50 | .name = "omap_gpio", | ||
| 51 | .id = 0, | ||
| 52 | .dev = { | ||
| 53 | .platform_data = &omap7xx_mpu_gpio_config, | ||
| 54 | }, | ||
| 55 | .num_resources = ARRAY_SIZE(omap7xx_mpu_gpio_resources), | ||
| 56 | .resource = omap7xx_mpu_gpio_resources, | ||
| 57 | }; | ||
| 58 | |||
| 59 | /* gpio1 */ | ||
| 60 | static struct __initdata resource omap7xx_gpio1_resources[] = { | ||
| 61 | { | ||
| 62 | .start = OMAP7XX_GPIO1_BASE, | ||
| 63 | .end = OMAP7XX_GPIO1_BASE + SZ_2K - 1, | ||
| 64 | .flags = IORESOURCE_MEM, | ||
| 65 | }, | ||
| 66 | { | ||
| 67 | .start = INT_7XX_GPIO_BANK1, | ||
| 68 | .flags = IORESOURCE_IRQ, | ||
| 69 | }, | ||
| 70 | }; | ||
| 71 | |||
| 72 | static struct __initdata omap_gpio_platform_data omap7xx_gpio1_config = { | ||
| 73 | .virtual_irq_start = IH_GPIO_BASE, | ||
| 74 | .bank_type = METHOD_GPIO_7XX, | ||
| 75 | .bank_width = 32, | ||
| 76 | }; | ||
| 77 | |||
| 78 | static struct __initdata platform_device omap7xx_gpio1 = { | ||
| 79 | .name = "omap_gpio", | ||
| 80 | .id = 1, | ||
| 81 | .dev = { | ||
| 82 | .platform_data = &omap7xx_gpio1_config, | ||
| 83 | }, | ||
| 84 | .num_resources = ARRAY_SIZE(omap7xx_gpio1_resources), | ||
| 85 | .resource = omap7xx_gpio1_resources, | ||
| 86 | }; | ||
| 87 | |||
| 88 | /* gpio2 */ | ||
| 89 | static struct __initdata resource omap7xx_gpio2_resources[] = { | ||
| 90 | { | ||
| 91 | .start = OMAP7XX_GPIO2_BASE, | ||
| 92 | .end = OMAP7XX_GPIO2_BASE + SZ_2K - 1, | ||
| 93 | .flags = IORESOURCE_MEM, | ||
| 94 | }, | ||
| 95 | { | ||
| 96 | .start = INT_7XX_GPIO_BANK2, | ||
| 97 | .flags = IORESOURCE_IRQ, | ||
| 98 | }, | ||
| 99 | }; | ||
| 100 | |||
| 101 | static struct __initdata omap_gpio_platform_data omap7xx_gpio2_config = { | ||
| 102 | .virtual_irq_start = IH_GPIO_BASE + 32, | ||
| 103 | .bank_type = METHOD_GPIO_7XX, | ||
| 104 | .bank_width = 32, | ||
| 105 | }; | ||
| 106 | |||
| 107 | static struct __initdata platform_device omap7xx_gpio2 = { | ||
| 108 | .name = "omap_gpio", | ||
| 109 | .id = 2, | ||
| 110 | .dev = { | ||
| 111 | .platform_data = &omap7xx_gpio2_config, | ||
| 112 | }, | ||
| 113 | .num_resources = ARRAY_SIZE(omap7xx_gpio2_resources), | ||
| 114 | .resource = omap7xx_gpio2_resources, | ||
| 115 | }; | ||
| 116 | |||
| 117 | /* gpio3 */ | ||
| 118 | static struct __initdata resource omap7xx_gpio3_resources[] = { | ||
| 119 | { | ||
| 120 | .start = OMAP7XX_GPIO3_BASE, | ||
| 121 | .end = OMAP7XX_GPIO3_BASE + SZ_2K - 1, | ||
| 122 | .flags = IORESOURCE_MEM, | ||
| 123 | }, | ||
| 124 | { | ||
| 125 | .start = INT_7XX_GPIO_BANK3, | ||
| 126 | .flags = IORESOURCE_IRQ, | ||
| 127 | }, | ||
| 128 | }; | ||
| 129 | |||
| 130 | static struct __initdata omap_gpio_platform_data omap7xx_gpio3_config = { | ||
| 131 | .virtual_irq_start = IH_GPIO_BASE + 64, | ||
| 132 | .bank_type = METHOD_GPIO_7XX, | ||
| 133 | .bank_width = 32, | ||
| 134 | }; | ||
| 135 | |||
| 136 | static struct __initdata platform_device omap7xx_gpio3 = { | ||
| 137 | .name = "omap_gpio", | ||
| 138 | .id = 3, | ||
| 139 | .dev = { | ||
| 140 | .platform_data = &omap7xx_gpio3_config, | ||
| 141 | }, | ||
| 142 | .num_resources = ARRAY_SIZE(omap7xx_gpio3_resources), | ||
| 143 | .resource = omap7xx_gpio3_resources, | ||
| 144 | }; | ||
| 145 | |||
| 146 | /* gpio4 */ | ||
| 147 | static struct __initdata resource omap7xx_gpio4_resources[] = { | ||
| 148 | { | ||
| 149 | .start = OMAP7XX_GPIO4_BASE, | ||
| 150 | .end = OMAP7XX_GPIO4_BASE + SZ_2K - 1, | ||
| 151 | .flags = IORESOURCE_MEM, | ||
| 152 | }, | ||
| 153 | { | ||
| 154 | .start = INT_7XX_GPIO_BANK4, | ||
| 155 | .flags = IORESOURCE_IRQ, | ||
| 156 | }, | ||
| 157 | }; | ||
| 158 | |||
| 159 | static struct __initdata omap_gpio_platform_data omap7xx_gpio4_config = { | ||
| 160 | .virtual_irq_start = IH_GPIO_BASE + 96, | ||
| 161 | .bank_type = METHOD_GPIO_7XX, | ||
| 162 | .bank_width = 32, | ||
| 163 | }; | ||
| 164 | |||
| 165 | static struct __initdata platform_device omap7xx_gpio4 = { | ||
| 166 | .name = "omap_gpio", | ||
| 167 | .id = 4, | ||
| 168 | .dev = { | ||
| 169 | .platform_data = &omap7xx_gpio4_config, | ||
| 170 | }, | ||
| 171 | .num_resources = ARRAY_SIZE(omap7xx_gpio4_resources), | ||
| 172 | .resource = omap7xx_gpio4_resources, | ||
| 173 | }; | ||
| 174 | |||
| 175 | /* gpio5 */ | ||
| 176 | static struct __initdata resource omap7xx_gpio5_resources[] = { | ||
| 177 | { | ||
| 178 | .start = OMAP7XX_GPIO5_BASE, | ||
| 179 | .end = OMAP7XX_GPIO5_BASE + SZ_2K - 1, | ||
| 180 | .flags = IORESOURCE_MEM, | ||
| 181 | }, | ||
| 182 | { | ||
| 183 | .start = INT_7XX_GPIO_BANK5, | ||
| 184 | .flags = IORESOURCE_IRQ, | ||
| 185 | }, | ||
| 186 | }; | ||
| 187 | |||
| 188 | static struct __initdata omap_gpio_platform_data omap7xx_gpio5_config = { | ||
| 189 | .virtual_irq_start = IH_GPIO_BASE + 128, | ||
| 190 | .bank_type = METHOD_GPIO_7XX, | ||
| 191 | .bank_width = 32, | ||
| 192 | }; | ||
| 193 | |||
| 194 | static struct __initdata platform_device omap7xx_gpio5 = { | ||
| 195 | .name = "omap_gpio", | ||
| 196 | .id = 5, | ||
| 197 | .dev = { | ||
| 198 | .platform_data = &omap7xx_gpio5_config, | ||
| 199 | }, | ||
| 200 | .num_resources = ARRAY_SIZE(omap7xx_gpio5_resources), | ||
| 201 | .resource = omap7xx_gpio5_resources, | ||
| 202 | }; | ||
| 203 | |||
| 204 | /* gpio6 */ | ||
| 205 | static struct __initdata resource omap7xx_gpio6_resources[] = { | ||
| 206 | { | ||
| 207 | .start = OMAP7XX_GPIO6_BASE, | ||
| 208 | .end = OMAP7XX_GPIO6_BASE + SZ_2K - 1, | ||
| 209 | .flags = IORESOURCE_MEM, | ||
| 210 | }, | ||
| 211 | { | ||
| 212 | .start = INT_7XX_GPIO_BANK6, | ||
| 213 | .flags = IORESOURCE_IRQ, | ||
| 214 | }, | ||
| 215 | }; | ||
| 216 | |||
| 217 | static struct __initdata omap_gpio_platform_data omap7xx_gpio6_config = { | ||
| 218 | .virtual_irq_start = IH_GPIO_BASE + 160, | ||
| 219 | .bank_type = METHOD_GPIO_7XX, | ||
| 220 | .bank_width = 32, | ||
| 221 | }; | ||
| 222 | |||
| 223 | static struct __initdata platform_device omap7xx_gpio6 = { | ||
| 224 | .name = "omap_gpio", | ||
| 225 | .id = 6, | ||
| 226 | .dev = { | ||
| 227 | .platform_data = &omap7xx_gpio6_config, | ||
| 228 | }, | ||
| 229 | .num_resources = ARRAY_SIZE(omap7xx_gpio6_resources), | ||
| 230 | .resource = omap7xx_gpio6_resources, | ||
| 231 | }; | ||
| 232 | |||
| 233 | static struct __initdata platform_device * omap7xx_gpio_dev[] = { | ||
| 234 | &omap7xx_mpu_gpio, | ||
| 235 | &omap7xx_gpio1, | ||
| 236 | &omap7xx_gpio2, | ||
| 237 | &omap7xx_gpio3, | ||
| 238 | &omap7xx_gpio4, | ||
| 239 | &omap7xx_gpio5, | ||
| 240 | &omap7xx_gpio6, | ||
| 241 | }; | ||
| 242 | |||
| 243 | /* | ||
| 244 | * omap7xx_gpio_init needs to be done before | ||
| 245 | * machine_init functions access gpio APIs. | ||
| 246 | * Hence omap7xx_gpio_init is a postcore_initcall. | ||
| 247 | */ | ||
| 248 | static int __init omap7xx_gpio_init(void) | ||
| 249 | { | ||
| 250 | int i; | ||
| 251 | |||
| 252 | if (!cpu_is_omap7xx()) | ||
| 253 | return -EINVAL; | ||
| 254 | |||
| 255 | for (i = 0; i < ARRAY_SIZE(omap7xx_gpio_dev); i++) | ||
| 256 | platform_device_register(omap7xx_gpio_dev[i]); | ||
| 257 | |||
| 258 | gpio_bank_count = ARRAY_SIZE(omap7xx_gpio_dev); | ||
| 259 | |||
| 260 | return 0; | ||
| 261 | } | ||
| 262 | postcore_initcall(omap7xx_gpio_init); | ||
diff --git a/arch/arm/mach-omap1/include/mach/entry-macro.S b/arch/arm/mach-omap1/include/mach/entry-macro.S index df9060edda28..c9be6d4d83e2 100644 --- a/arch/arm/mach-omap1/include/mach/entry-macro.S +++ b/arch/arm/mach-omap1/include/mach/entry-macro.S | |||
| @@ -14,18 +14,17 @@ | |||
| 14 | #include <mach/irqs.h> | 14 | #include <mach/irqs.h> |
| 15 | #include <asm/hardware/gic.h> | 15 | #include <asm/hardware/gic.h> |
| 16 | 16 | ||
| 17 | #if (defined(CONFIG_ARCH_OMAP730)||defined(CONFIG_ARCH_OMAP850)) && \ | 17 | /* |
| 18 | (defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)) | 18 | * We use __glue to avoid errors with multiple definitions of |
| 19 | #error "FIXME: OMAP7XX doesn't support multiple-OMAP" | 19 | * .globl omap_irq_flags as it's included from entry-armv.S but not |
| 20 | #elif defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) | 20 | * from entry-common.S. |
| 21 | #define INT_IH2_IRQ INT_7XX_IH2_IRQ | 21 | */ |
| 22 | #elif defined(CONFIG_ARCH_OMAP15XX) | 22 | #ifdef __glue |
| 23 | #define INT_IH2_IRQ INT_1510_IH2_IRQ | 23 | .pushsection .data |
| 24 | #elif defined(CONFIG_ARCH_OMAP16XX) | 24 | .globl omap_irq_flags |
| 25 | #define INT_IH2_IRQ INT_1610_IH2_IRQ | 25 | omap_irq_flags: |
| 26 | #else | 26 | .word 0 |
| 27 | #warning "IH2 IRQ defaulted" | 27 | .popsection |
| 28 | #define INT_IH2_IRQ INT_1510_IH2_IRQ | ||
| 29 | #endif | 28 | #endif |
| 30 | 29 | ||
| 31 | .macro disable_fiq | 30 | .macro disable_fiq |
| @@ -47,9 +46,11 @@ | |||
| 47 | beq 1510f | 46 | beq 1510f |
| 48 | 47 | ||
| 49 | ldr \irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET] | 48 | ldr \irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET] |
| 49 | ldr \tmp, =omap_irq_flags @ irq flags address | ||
| 50 | ldr \tmp, [\tmp, #0] @ irq flags value | ||
| 50 | cmp \irqnr, #0 | 51 | cmp \irqnr, #0 |
| 51 | ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET] | 52 | ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET] |
| 52 | cmpeq \irqnr, #INT_IH2_IRQ | 53 | cmpeq \irqnr, \tmp |
| 53 | ldreq \base, =OMAP1_IO_ADDRESS(OMAP_IH2_BASE) | 54 | ldreq \base, =OMAP1_IO_ADDRESS(OMAP_IH2_BASE) |
| 54 | ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET] | 55 | ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET] |
| 55 | addeqs \irqnr, \irqnr, #32 | 56 | addeqs \irqnr, \irqnr, #32 |
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c index 0ce3fec2d257..870886a29594 100644 --- a/arch/arm/mach-omap1/io.c +++ b/arch/arm/mach-omap1/io.c | |||
| @@ -142,3 +142,42 @@ void __init omap1_init_common_hw(void) | |||
| 142 | omap1_mux_init(); | 142 | omap1_mux_init(); |
| 143 | } | 143 | } |
| 144 | 144 | ||
| 145 | /* | ||
| 146 | * NOTE: Please use ioremap + __raw_read/write where possible instead of these | ||
| 147 | */ | ||
| 148 | |||
| 149 | u8 omap_readb(u32 pa) | ||
| 150 | { | ||
| 151 | return __raw_readb(OMAP1_IO_ADDRESS(pa)); | ||
| 152 | } | ||
| 153 | EXPORT_SYMBOL(omap_readb); | ||
| 154 | |||
| 155 | u16 omap_readw(u32 pa) | ||
| 156 | { | ||
| 157 | return __raw_readw(OMAP1_IO_ADDRESS(pa)); | ||
| 158 | } | ||
| 159 | EXPORT_SYMBOL(omap_readw); | ||
| 160 | |||
| 161 | u32 omap_readl(u32 pa) | ||
| 162 | { | ||
| 163 | return __raw_readl(OMAP1_IO_ADDRESS(pa)); | ||
| 164 | } | ||
| 165 | EXPORT_SYMBOL(omap_readl); | ||
| 166 | |||
| 167 | void omap_writeb(u8 v, u32 pa) | ||
| 168 | { | ||
| 169 | __raw_writeb(v, OMAP1_IO_ADDRESS(pa)); | ||
| 170 | } | ||
| 171 | EXPORT_SYMBOL(omap_writeb); | ||
| 172 | |||
| 173 | void omap_writew(u16 v, u32 pa) | ||
| 174 | { | ||
| 175 | __raw_writew(v, OMAP1_IO_ADDRESS(pa)); | ||
| 176 | } | ||
| 177 | EXPORT_SYMBOL(omap_writew); | ||
| 178 | |||
| 179 | void omap_writel(u32 v, u32 pa) | ||
| 180 | { | ||
| 181 | __raw_writel(v, OMAP1_IO_ADDRESS(pa)); | ||
| 182 | } | ||
| 183 | EXPORT_SYMBOL(omap_writel); | ||
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c index db913c34d1fe..6bddbc869f4c 100644 --- a/arch/arm/mach-omap1/irq.c +++ b/arch/arm/mach-omap1/irq.c | |||
| @@ -176,26 +176,31 @@ static struct irq_chip omap_irq_chip = { | |||
| 176 | 176 | ||
| 177 | void __init omap_init_irq(void) | 177 | void __init omap_init_irq(void) |
| 178 | { | 178 | { |
| 179 | extern unsigned int omap_irq_flags; | ||
| 179 | int i, j; | 180 | int i, j; |
| 180 | 181 | ||
| 181 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) | 182 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
| 182 | if (cpu_is_omap7xx()) { | 183 | if (cpu_is_omap7xx()) { |
| 184 | omap_irq_flags = INT_7XX_IH2_IRQ; | ||
| 183 | irq_banks = omap7xx_irq_banks; | 185 | irq_banks = omap7xx_irq_banks; |
| 184 | irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks); | 186 | irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks); |
| 185 | } | 187 | } |
| 186 | #endif | 188 | #endif |
| 187 | #ifdef CONFIG_ARCH_OMAP15XX | 189 | #ifdef CONFIG_ARCH_OMAP15XX |
| 188 | if (cpu_is_omap1510()) { | 190 | if (cpu_is_omap1510()) { |
| 191 | omap_irq_flags = INT_1510_IH2_IRQ; | ||
| 189 | irq_banks = omap1510_irq_banks; | 192 | irq_banks = omap1510_irq_banks; |
| 190 | irq_bank_count = ARRAY_SIZE(omap1510_irq_banks); | 193 | irq_bank_count = ARRAY_SIZE(omap1510_irq_banks); |
| 191 | } | 194 | } |
| 192 | if (cpu_is_omap310()) { | 195 | if (cpu_is_omap310()) { |
| 196 | omap_irq_flags = INT_1510_IH2_IRQ; | ||
| 193 | irq_banks = omap310_irq_banks; | 197 | irq_banks = omap310_irq_banks; |
| 194 | irq_bank_count = ARRAY_SIZE(omap310_irq_banks); | 198 | irq_bank_count = ARRAY_SIZE(omap310_irq_banks); |
| 195 | } | 199 | } |
| 196 | #endif | 200 | #endif |
| 197 | #if defined(CONFIG_ARCH_OMAP16XX) | 201 | #if defined(CONFIG_ARCH_OMAP16XX) |
| 198 | if (cpu_is_omap16xx()) { | 202 | if (cpu_is_omap16xx()) { |
| 203 | omap_irq_flags = INT_1510_IH2_IRQ; | ||
| 199 | irq_banks = omap1610_irq_banks; | 204 | irq_banks = omap1610_irq_banks; |
| 200 | irq_bank_count = ARRAY_SIZE(omap1610_irq_banks); | 205 | irq_bank_count = ARRAY_SIZE(omap1610_irq_banks); |
| 201 | } | 206 | } |
diff --git a/arch/arm/mach-omap1/lcd_dma.c b/arch/arm/mach-omap1/lcd_dma.c index 3be11af687bb..c9088d85da04 100644 --- a/arch/arm/mach-omap1/lcd_dma.c +++ b/arch/arm/mach-omap1/lcd_dma.c | |||
| @@ -424,6 +424,9 @@ static int __init omap_init_lcd_dma(void) | |||
| 424 | { | 424 | { |
| 425 | int r; | 425 | int r; |
| 426 | 426 | ||
| 427 | if (!cpu_class_is_omap1()) | ||
| 428 | return -ENODEV; | ||
| 429 | |||
| 427 | if (cpu_is_omap16xx()) { | 430 | if (cpu_is_omap16xx()) { |
| 428 | u16 w; | 431 | u16 w; |
| 429 | 432 | ||
diff --git a/arch/arm/mach-omap1/leds.c b/arch/arm/mach-omap1/leds.c index 277f356d4cd0..22eb11dde9e7 100644 --- a/arch/arm/mach-omap1/leds.c +++ b/arch/arm/mach-omap1/leds.c | |||
| @@ -17,6 +17,9 @@ | |||
| 17 | static int __init | 17 | static int __init |
| 18 | omap_leds_init(void) | 18 | omap_leds_init(void) |
| 19 | { | 19 | { |
| 20 | if (!cpu_class_is_omap1()) | ||
| 21 | return -ENODEV; | ||
| 22 | |||
| 20 | if (machine_is_omap_innovator()) | 23 | if (machine_is_omap_innovator()) |
| 21 | leds_event = innovator_leds_event; | 24 | leds_event = innovator_leds_event; |
| 22 | 25 | ||
diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c index 1a85a421007f..c0e1f48aa119 100644 --- a/arch/arm/mach-omap1/mailbox.c +++ b/arch/arm/mach-omap1/mailbox.c | |||
| @@ -133,19 +133,18 @@ static struct omap_mbox1_priv omap1_mbox_dsp_priv = { | |||
| 133 | }, | 133 | }, |
| 134 | }; | 134 | }; |
| 135 | 135 | ||
| 136 | struct omap_mbox mbox_dsp_info = { | 136 | static struct omap_mbox mbox_dsp_info = { |
| 137 | .name = "dsp", | 137 | .name = "dsp", |
| 138 | .ops = &omap1_mbox_ops, | 138 | .ops = &omap1_mbox_ops, |
| 139 | .priv = &omap1_mbox_dsp_priv, | 139 | .priv = &omap1_mbox_dsp_priv, |
| 140 | }; | 140 | }; |
| 141 | 141 | ||
| 142 | struct omap_mbox *omap1_mboxes[] = { &mbox_dsp_info, NULL }; | 142 | static struct omap_mbox *omap1_mboxes[] = { &mbox_dsp_info, NULL }; |
| 143 | 143 | ||
| 144 | static int __devinit omap1_mbox_probe(struct platform_device *pdev) | 144 | static int __devinit omap1_mbox_probe(struct platform_device *pdev) |
| 145 | { | 145 | { |
| 146 | struct resource *mem; | 146 | struct resource *mem; |
| 147 | int ret; | 147 | int ret; |
| 148 | int i; | ||
| 149 | struct omap_mbox **list; | 148 | struct omap_mbox **list; |
| 150 | 149 | ||
| 151 | list = omap1_mboxes; | 150 | list = omap1_mboxes; |
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c index b3a796a6da03..820973666f34 100644 --- a/arch/arm/mach-omap1/mcbsp.c +++ b/arch/arm/mach-omap1/mcbsp.c | |||
| @@ -174,8 +174,11 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = { | |||
| 174 | #define OMAP16XX_MCBSP_REG_NUM 0 | 174 | #define OMAP16XX_MCBSP_REG_NUM 0 |
| 175 | #endif | 175 | #endif |
| 176 | 176 | ||
| 177 | int __init omap1_mcbsp_init(void) | 177 | static int __init omap1_mcbsp_init(void) |
| 178 | { | 178 | { |
| 179 | if (!cpu_class_is_omap1()) | ||
| 180 | return -ENODEV; | ||
| 181 | |||
| 179 | if (cpu_is_omap7xx()) { | 182 | if (cpu_is_omap7xx()) { |
| 180 | omap_mcbsp_count = OMAP7XX_MCBSP_PDATA_SZ; | 183 | omap_mcbsp_count = OMAP7XX_MCBSP_PDATA_SZ; |
| 181 | omap_mcbsp_cache_size = OMAP7XX_MCBSP_REG_NUM * sizeof(u16); | 184 | omap_mcbsp_cache_size = OMAP7XX_MCBSP_REG_NUM * sizeof(u16); |
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c index 7835add00344..5fdef7a34828 100644 --- a/arch/arm/mach-omap1/mux.c +++ b/arch/arm/mach-omap1/mux.c | |||
| @@ -343,7 +343,7 @@ MUX_CFG("Y14_1610_CCP_DATAM", 9, 21, 6, 2, 3, 1, 2, 0, 0) | |||
| 343 | #define OMAP1XXX_PINS_SZ 0 | 343 | #define OMAP1XXX_PINS_SZ 0 |
| 344 | #endif /* CONFIG_ARCH_OMAP15XX || CONFIG_ARCH_OMAP16XX */ | 344 | #endif /* CONFIG_ARCH_OMAP15XX || CONFIG_ARCH_OMAP16XX */ |
| 345 | 345 | ||
| 346 | int __init_or_module omap1_cfg_reg(const struct pin_config *cfg) | 346 | static int __init_or_module omap1_cfg_reg(const struct pin_config *cfg) |
| 347 | { | 347 | { |
| 348 | static DEFINE_SPINLOCK(mux_spin_lock); | 348 | static DEFINE_SPINLOCK(mux_spin_lock); |
| 349 | unsigned long flags; | 349 | unsigned long flags; |
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c index b1d3f9fade23..0cca23a85175 100644 --- a/arch/arm/mach-omap1/pm.c +++ b/arch/arm/mach-omap1/pm.c | |||
| @@ -661,6 +661,9 @@ static int __init omap_pm_init(void) | |||
| 661 | int error; | 661 | int error; |
| 662 | #endif | 662 | #endif |
| 663 | 663 | ||
| 664 | if (!cpu_class_is_omap1()) | ||
| 665 | return -ENODEV; | ||
| 666 | |||
| 664 | printk("Power Management for TI OMAP.\n"); | 667 | printk("Power Management for TI OMAP.\n"); |
| 665 | 668 | ||
| 666 | /* | 669 | /* |
diff --git a/arch/arm/mach-omap1/pm_bus.c b/arch/arm/mach-omap1/pm_bus.c index 8b66392be745..6588c22b8a64 100644 --- a/arch/arm/mach-omap1/pm_bus.c +++ b/arch/arm/mach-omap1/pm_bus.c | |||
| @@ -48,7 +48,6 @@ static int omap1_pm_runtime_suspend(struct device *dev) | |||
| 48 | 48 | ||
| 49 | static int omap1_pm_runtime_resume(struct device *dev) | 49 | static int omap1_pm_runtime_resume(struct device *dev) |
| 50 | { | 50 | { |
| 51 | int ret = 0; | ||
| 52 | struct clk *iclk, *fclk; | 51 | struct clk *iclk, *fclk; |
| 53 | 52 | ||
| 54 | dev_dbg(dev, "%s\n", __func__); | 53 | dev_dbg(dev, "%s\n", __func__); |
| @@ -73,6 +72,9 @@ static int __init omap1_pm_runtime_init(void) | |||
| 73 | const struct dev_pm_ops *pm; | 72 | const struct dev_pm_ops *pm; |
| 74 | struct dev_pm_ops *omap_pm; | 73 | struct dev_pm_ops *omap_pm; |
| 75 | 74 | ||
| 75 | if (!cpu_class_is_omap1()) | ||
| 76 | return -ENODEV; | ||
| 77 | |||
| 76 | pm = platform_bus_get_pm_ops(); | 78 | pm = platform_bus_get_pm_ops(); |
| 77 | if (!pm) { | 79 | if (!pm) { |
| 78 | pr_err("%s: unable to get dev_pm_ops from platform_bus\n", | 80 | pr_err("%s: unable to get dev_pm_ops from platform_bus\n", |
diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c index b78d0749f13d..550ca9d9991d 100644 --- a/arch/arm/mach-omap1/serial.c +++ b/arch/arm/mach-omap1/serial.c | |||
| @@ -27,6 +27,8 @@ | |||
| 27 | #include <mach/gpio.h> | 27 | #include <mach/gpio.h> |
| 28 | #include <plat/fpga.h> | 28 | #include <plat/fpga.h> |
| 29 | 29 | ||
| 30 | #include "pm.h" | ||
| 31 | |||
| 30 | static struct clk * uart1_ck; | 32 | static struct clk * uart1_ck; |
| 31 | static struct clk * uart2_ck; | 33 | static struct clk * uart2_ck; |
| 32 | static struct clk * uart3_ck; | 34 | static struct clk * uart3_ck; |
| @@ -52,9 +54,11 @@ static inline void omap_serial_outp(struct plat_serial8250_port *p, int offset, | |||
| 52 | */ | 54 | */ |
| 53 | static void __init omap_serial_reset(struct plat_serial8250_port *p) | 55 | static void __init omap_serial_reset(struct plat_serial8250_port *p) |
| 54 | { | 56 | { |
| 55 | omap_serial_outp(p, UART_OMAP_MDR1, 0x07); /* disable UART */ | 57 | omap_serial_outp(p, UART_OMAP_MDR1, |
| 58 | UART_OMAP_MDR1_DISABLE); /* disable UART */ | ||
| 56 | omap_serial_outp(p, UART_OMAP_SCR, 0x08); /* TX watermark */ | 59 | omap_serial_outp(p, UART_OMAP_SCR, 0x08); /* TX watermark */ |
| 57 | omap_serial_outp(p, UART_OMAP_MDR1, 0x00); /* enable UART */ | 60 | omap_serial_outp(p, UART_OMAP_MDR1, |
| 61 | UART_OMAP_MDR1_16X_MODE); /* enable UART */ | ||
| 58 | 62 | ||
| 59 | if (!cpu_is_omap15xx()) { | 63 | if (!cpu_is_omap15xx()) { |
| 60 | omap_serial_outp(p, UART_OMAP_SYSC, 0x01); | 64 | omap_serial_outp(p, UART_OMAP_SYSC, 0x01); |
| @@ -254,6 +258,9 @@ late_initcall(omap_serial_wakeup_init); | |||
| 254 | 258 | ||
| 255 | static int __init omap_init(void) | 259 | static int __init omap_init(void) |
| 256 | { | 260 | { |
| 261 | if (!cpu_class_is_omap1()) | ||
| 262 | return -ENODEV; | ||
| 263 | |||
| 257 | return platform_device_register(&serial_device); | 264 | return platform_device_register(&serial_device); |
| 258 | } | 265 | } |
| 259 | arch_initcall(omap_init); | 266 | arch_initcall(omap_init); |
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c index 1be6a214d88d..ed7a61ff916a 100644 --- a/arch/arm/mach-omap1/time.c +++ b/arch/arm/mach-omap1/time.c | |||
| @@ -52,6 +52,7 @@ | |||
| 52 | #include <asm/mach/irq.h> | 52 | #include <asm/mach/irq.h> |
| 53 | #include <asm/mach/time.h> | 53 | #include <asm/mach/time.h> |
| 54 | 54 | ||
| 55 | #include <plat/common.h> | ||
| 55 | 56 | ||
| 56 | #define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE | 57 | #define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE |
| 57 | #define OMAP_MPU_TIMER_OFFSET 0x100 | 58 | #define OMAP_MPU_TIMER_OFFSET 0x100 |
| @@ -208,7 +209,6 @@ static struct clocksource clocksource_mpu = { | |||
| 208 | .rating = 300, | 209 | .rating = 300, |
| 209 | .read = mpu_read, | 210 | .read = mpu_read, |
| 210 | .mask = CLOCKSOURCE_MASK(32), | 211 | .mask = CLOCKSOURCE_MASK(32), |
| 211 | .shift = 24, | ||
| 212 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 212 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 213 | }; | 213 | }; |
| 214 | 214 | ||
| @@ -217,13 +217,10 @@ static void __init omap_init_clocksource(unsigned long rate) | |||
| 217 | static char err[] __initdata = KERN_ERR | 217 | static char err[] __initdata = KERN_ERR |
| 218 | "%s: can't register clocksource!\n"; | 218 | "%s: can't register clocksource!\n"; |
| 219 | 219 | ||
| 220 | clocksource_mpu.mult | ||
| 221 | = clocksource_khz2mult(rate/1000, clocksource_mpu.shift); | ||
| 222 | |||
| 223 | setup_irq(INT_TIMER2, &omap_mpu_timer2_irq); | 220 | setup_irq(INT_TIMER2, &omap_mpu_timer2_irq); |
| 224 | omap_mpu_timer_start(1, ~0, 1); | 221 | omap_mpu_timer_start(1, ~0, 1); |
| 225 | 222 | ||
| 226 | if (clocksource_register(&clocksource_mpu)) | 223 | if (clocksource_register_hz(&clocksource_mpu, rate)) |
| 227 | printk(err, clocksource_mpu.name); | 224 | printk(err, clocksource_mpu.name); |
| 228 | } | 225 | } |
| 229 | 226 | ||
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index ab784bfde908..1a2cf6226a55 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig | |||
| @@ -15,7 +15,7 @@ config ARCH_OMAP2PLUS_TYPICAL | |||
| 15 | select SERIAL_OMAP_CONSOLE | 15 | select SERIAL_OMAP_CONSOLE |
| 16 | select I2C | 16 | select I2C |
| 17 | select I2C_OMAP | 17 | select I2C_OMAP |
| 18 | select MFD | 18 | select MFD_SUPPORT |
| 19 | select MENELAUS if ARCH_OMAP2 | 19 | select MENELAUS if ARCH_OMAP2 |
| 20 | select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4 | 20 | select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4 |
| 21 | select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4 | 21 | select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4 |
| @@ -35,6 +35,8 @@ config ARCH_OMAP3 | |||
| 35 | select CPU_V7 | 35 | select CPU_V7 |
| 36 | select USB_ARCH_HAS_EHCI | 36 | select USB_ARCH_HAS_EHCI |
| 37 | select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4 | 37 | select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4 |
| 38 | select ARCH_HAS_OPP | ||
| 39 | select PM_OPP if PM | ||
| 38 | 40 | ||
| 39 | config ARCH_OMAP4 | 41 | config ARCH_OMAP4 |
| 40 | bool "TI OMAP4" | 42 | bool "TI OMAP4" |
| @@ -44,6 +46,9 @@ config ARCH_OMAP4 | |||
| 44 | select ARM_GIC | 46 | select ARM_GIC |
| 45 | select PL310_ERRATA_588369 | 47 | select PL310_ERRATA_588369 |
| 46 | select ARM_ERRATA_720789 | 48 | select ARM_ERRATA_720789 |
| 49 | select ARCH_HAS_OPP | ||
| 50 | select PM_OPP if PM | ||
| 51 | select USB_ARCH_HAS_EHCI | ||
| 47 | 52 | ||
| 48 | comment "OMAP Core Type" | 53 | comment "OMAP Core Type" |
| 49 | depends on ARCH_OMAP2 | 54 | depends on ARCH_OMAP2 |
| @@ -85,6 +90,12 @@ config OMAP_PACKAGE_CUS | |||
| 85 | config OMAP_PACKAGE_CBP | 90 | config OMAP_PACKAGE_CBP |
| 86 | bool | 91 | bool |
| 87 | 92 | ||
| 93 | config OMAP_PACKAGE_CBL | ||
| 94 | bool | ||
| 95 | |||
| 96 | config OMAP_PACKAGE_CBS | ||
| 97 | bool | ||
| 98 | |||
| 88 | comment "OMAP Board Type" | 99 | comment "OMAP Board Type" |
| 89 | depends on ARCH_OMAP2PLUS | 100 | depends on ARCH_OMAP2PLUS |
| 90 | 101 | ||
| @@ -128,7 +139,6 @@ config MACH_DEVKIT8000 | |||
| 128 | depends on ARCH_OMAP3 | 139 | depends on ARCH_OMAP3 |
| 129 | default y | 140 | default y |
| 130 | select OMAP_PACKAGE_CUS | 141 | select OMAP_PACKAGE_CUS |
| 131 | select OMAP_MUX | ||
| 132 | 142 | ||
| 133 | config MACH_OMAP_LDP | 143 | config MACH_OMAP_LDP |
| 134 | bool "OMAP3 LDP board" | 144 | bool "OMAP3 LDP board" |
| @@ -174,11 +184,17 @@ config MACH_OMAP3517EVM | |||
| 174 | default y | 184 | default y |
| 175 | select OMAP_PACKAGE_CBB | 185 | select OMAP_PACKAGE_CBB |
| 176 | 186 | ||
| 187 | config MACH_CRANEBOARD | ||
| 188 | bool "AM3517/05 CRANE board" | ||
| 189 | depends on ARCH_OMAP3 | ||
| 190 | select OMAP_PACKAGE_CBB | ||
| 191 | |||
| 177 | config MACH_OMAP3_PANDORA | 192 | config MACH_OMAP3_PANDORA |
| 178 | bool "OMAP3 Pandora" | 193 | bool "OMAP3 Pandora" |
| 179 | depends on ARCH_OMAP3 | 194 | depends on ARCH_OMAP3 |
| 180 | default y | 195 | default y |
| 181 | select OMAP_PACKAGE_CBB | 196 | select OMAP_PACKAGE_CBB |
| 197 | select REGULATOR_FIXED_VOLTAGE | ||
| 182 | 198 | ||
| 183 | config MACH_OMAP3_TOUCHBOOK | 199 | config MACH_OMAP3_TOUCHBOOK |
| 184 | bool "OMAP3 Touch Book" | 200 | bool "OMAP3 Touch Book" |
| @@ -210,6 +226,12 @@ config MACH_NOKIA_N8X0 | |||
| 210 | select MACH_NOKIA_N810 | 226 | select MACH_NOKIA_N810 |
| 211 | select MACH_NOKIA_N810_WIMAX | 227 | select MACH_NOKIA_N810_WIMAX |
| 212 | 228 | ||
| 229 | config MACH_NOKIA_RM680 | ||
| 230 | bool "Nokia RM-680 board" | ||
| 231 | depends on ARCH_OMAP3 | ||
| 232 | default y | ||
| 233 | select OMAP_PACKAGE_CBB | ||
| 234 | |||
| 213 | config MACH_NOKIA_RX51 | 235 | config MACH_NOKIA_RX51 |
| 214 | bool "Nokia RX-51 board" | 236 | bool "Nokia RX-51 board" |
| 215 | depends on ARCH_OMAP3 | 237 | depends on ARCH_OMAP3 |
| @@ -224,6 +246,7 @@ config MACH_OMAP_ZOOM2 | |||
| 224 | select SERIAL_8250 | 246 | select SERIAL_8250 |
| 225 | select SERIAL_CORE_CONSOLE | 247 | select SERIAL_CORE_CONSOLE |
| 226 | select SERIAL_8250_CONSOLE | 248 | select SERIAL_8250_CONSOLE |
| 249 | select REGULATOR_FIXED_VOLTAGE | ||
| 227 | 250 | ||
| 228 | config MACH_OMAP_ZOOM3 | 251 | config MACH_OMAP_ZOOM3 |
| 229 | bool "OMAP3630 Zoom3 board" | 252 | bool "OMAP3630 Zoom3 board" |
| @@ -233,20 +256,19 @@ config MACH_OMAP_ZOOM3 | |||
| 233 | select SERIAL_8250 | 256 | select SERIAL_8250 |
| 234 | select SERIAL_CORE_CONSOLE | 257 | select SERIAL_CORE_CONSOLE |
| 235 | select SERIAL_8250_CONSOLE | 258 | select SERIAL_8250_CONSOLE |
| 259 | select REGULATOR_FIXED_VOLTAGE | ||
| 236 | 260 | ||
| 237 | config MACH_CM_T35 | 261 | config MACH_CM_T35 |
| 238 | bool "CompuLab CM-T35 module" | 262 | bool "CompuLab CM-T35 module" |
| 239 | depends on ARCH_OMAP3 | 263 | depends on ARCH_OMAP3 |
| 240 | default y | 264 | default y |
| 241 | select OMAP_PACKAGE_CUS | 265 | select OMAP_PACKAGE_CUS |
| 242 | select OMAP_MUX | ||
| 243 | 266 | ||
| 244 | config MACH_CM_T3517 | 267 | config MACH_CM_T3517 |
| 245 | bool "CompuLab CM-T3517 module" | 268 | bool "CompuLab CM-T3517 module" |
| 246 | depends on ARCH_OMAP3 | 269 | depends on ARCH_OMAP3 |
| 247 | default y | 270 | default y |
| 248 | select OMAP_PACKAGE_CBB | 271 | select OMAP_PACKAGE_CBB |
| 249 | select OMAP_MUX | ||
| 250 | 272 | ||
| 251 | config MACH_IGEP0020 | 273 | config MACH_IGEP0020 |
| 252 | bool "IGEP v2 board" | 274 | bool "IGEP v2 board" |
| @@ -265,7 +287,6 @@ config MACH_SBC3530 | |||
| 265 | depends on ARCH_OMAP3 | 287 | depends on ARCH_OMAP3 |
| 266 | default y | 288 | default y |
| 267 | select OMAP_PACKAGE_CUS | 289 | select OMAP_PACKAGE_CUS |
| 268 | select OMAP_MUX | ||
| 269 | 290 | ||
| 270 | config MACH_OMAP_3630SDP | 291 | config MACH_OMAP_3630SDP |
| 271 | bool "OMAP3630 SDP board" | 292 | bool "OMAP3630 SDP board" |
| @@ -277,11 +298,15 @@ config MACH_OMAP_4430SDP | |||
| 277 | bool "OMAP 4430 SDP board" | 298 | bool "OMAP 4430 SDP board" |
| 278 | default y | 299 | default y |
| 279 | depends on ARCH_OMAP4 | 300 | depends on ARCH_OMAP4 |
| 301 | select OMAP_PACKAGE_CBL | ||
| 302 | select OMAP_PACKAGE_CBS | ||
| 280 | 303 | ||
| 281 | config MACH_OMAP4_PANDA | 304 | config MACH_OMAP4_PANDA |
| 282 | bool "OMAP4 Panda Board" | 305 | bool "OMAP4 Panda Board" |
| 283 | default y | 306 | default y |
| 284 | depends on ARCH_OMAP4 | 307 | depends on ARCH_OMAP4 |
| 308 | select OMAP_PACKAGE_CBL | ||
| 309 | select OMAP_PACKAGE_CBS | ||
| 285 | 310 | ||
| 286 | config OMAP3_EMU | 311 | config OMAP3_EMU |
| 287 | bool "OMAP3 debugging peripherals" | 312 | bool "OMAP3 debugging peripherals" |
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 60e51bcf53bd..cd7332f50b2d 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile | |||
| @@ -4,30 +4,31 @@ | |||
| 4 | 4 | ||
| 5 | # Common support | 5 | # Common support |
| 6 | obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \ | 6 | obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \ |
| 7 | common.o | 7 | common.o gpio.o dma.o wd_timer.o |
| 8 | 8 | ||
| 9 | omap-2-3-common = irq.o sdrc.o prm2xxx_3xxx.o | 9 | omap-2-3-common = irq.o sdrc.o |
| 10 | hwmod-common = omap_hwmod.o \ | 10 | hwmod-common = omap_hwmod.o \ |
| 11 | omap_hwmod_common_data.o | 11 | omap_hwmod_common_data.o |
| 12 | prcm-common = prcm.o powerdomain.o | ||
| 13 | clock-common = clock.o clock_common_data.o \ | 12 | clock-common = clock.o clock_common_data.o \ |
| 14 | clockdomain.o clkt_dpll.o \ | 13 | clkt_dpll.o clkt_clksel.o |
| 15 | clkt_clksel.o | ||
| 16 | 14 | ||
| 17 | obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(hwmod-common) | 15 | obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) |
| 18 | obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(hwmod-common) | 16 | obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) |
| 19 | obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common) prm44xx.o $(hwmod-common) | 17 | obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) |
| 20 | 18 | ||
| 21 | obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o | 19 | obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o |
| 22 | 20 | ||
| 21 | obj-$(CONFIG_TWL4030_CORE) += omap_twl.o | ||
| 22 | |||
| 23 | # SMP support ONLY available for OMAP4 | 23 | # SMP support ONLY available for OMAP4 |
| 24 | obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o | 24 | obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o |
| 25 | obj-$(CONFIG_LOCAL_TIMERS) += timer-mpu.o | 25 | obj-$(CONFIG_LOCAL_TIMERS) += timer-mpu.o |
| 26 | obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o | 26 | obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o |
| 27 | obj-$(CONFIG_ARCH_OMAP4) += omap44xx-smc.o omap4-common.o | 27 | obj-$(CONFIG_ARCH_OMAP4) += omap44xx-smc.o omap4-common.o |
| 28 | 28 | ||
| 29 | AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a | 29 | plus_sec := $(call as-instr,.arch_extension sec,+sec) |
| 30 | AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a | 30 | AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec) |
| 31 | AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a$(plus_sec) | ||
| 31 | 32 | ||
| 32 | # Functions loaded to SRAM | 33 | # Functions loaded to SRAM |
| 33 | obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o | 34 | obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o |
| @@ -42,18 +43,29 @@ AFLAGS_sram34xx.o :=-Wa,-march=armv7-a | |||
| 42 | obj-$(CONFIG_ARCH_OMAP2420) += mux2420.o | 43 | obj-$(CONFIG_ARCH_OMAP2420) += mux2420.o |
| 43 | obj-$(CONFIG_ARCH_OMAP2430) += mux2430.o | 44 | obj-$(CONFIG_ARCH_OMAP2430) += mux2430.o |
| 44 | obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o | 45 | obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o |
| 46 | obj-$(CONFIG_ARCH_OMAP4) += mux44xx.o | ||
| 45 | 47 | ||
| 46 | # SMS/SDRC | 48 | # SMS/SDRC |
| 47 | obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o | 49 | obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o |
| 48 | # obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o | 50 | # obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o |
| 49 | 51 | ||
| 52 | # OPP table initialization | ||
| 53 | ifeq ($(CONFIG_PM_OPP),y) | ||
| 54 | obj-y += opp.o | ||
| 55 | obj-$(CONFIG_ARCH_OMAP3) += opp3xxx_data.o | ||
| 56 | obj-$(CONFIG_ARCH_OMAP4) += opp4xxx_data.o | ||
| 57 | endif | ||
| 58 | |||
| 50 | # Power Management | 59 | # Power Management |
| 51 | ifeq ($(CONFIG_PM),y) | 60 | ifeq ($(CONFIG_PM),y) |
| 52 | obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o | 61 | obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o |
| 53 | obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o pm_bus.o | 62 | obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o pm_bus.o voltage.o |
| 54 | obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o pm_bus.o | 63 | obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o voltage.o \ |
| 55 | obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o pm_bus.o | 64 | cpuidle34xx.o pm_bus.o |
| 65 | obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o voltage.o pm_bus.o | ||
| 56 | obj-$(CONFIG_PM_DEBUG) += pm-debug.o | 66 | obj-$(CONFIG_PM_DEBUG) += pm-debug.o |
| 67 | obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o | ||
| 68 | obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3) += smartreflex-class3.o | ||
| 57 | 69 | ||
| 58 | AFLAGS_sleep24xx.o :=-Wa,-march=armv6 | 70 | AFLAGS_sleep24xx.o :=-Wa,-march=armv6 |
| 59 | AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a | 71 | AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a |
| @@ -65,10 +77,36 @@ endif | |||
| 65 | endif | 77 | endif |
| 66 | 78 | ||
| 67 | # PRCM | 79 | # PRCM |
| 68 | obj-$(CONFIG_ARCH_OMAP2) += cm.o | 80 | obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o |
| 69 | obj-$(CONFIG_ARCH_OMAP3) += cm.o | 81 | obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o |
| 70 | obj-$(CONFIG_ARCH_OMAP4) += cm4xxx.o | 82 | # XXX The presence of cm2xxx_3xxx.o on the line below is temporary and |
| 71 | 83 | # will be removed once the OMAP4 part of the codebase is converted to | |
| 84 | # use OMAP4-specific PRCM functions. | ||
| 85 | obj-$(CONFIG_ARCH_OMAP4) += prcm.o cm2xxx_3xxx.o cminst44xx.o \ | ||
| 86 | cm44xx.o prcm_mpu44xx.o \ | ||
| 87 | prminst44xx.o | ||
| 88 | |||
| 89 | # OMAP powerdomain framework | ||
| 90 | powerdomain-common += powerdomain.o powerdomain-common.o | ||
| 91 | obj-$(CONFIG_ARCH_OMAP2) += $(powerdomain-common) \ | ||
| 92 | powerdomain2xxx_3xxx.o \ | ||
| 93 | powerdomains2xxx_data.o \ | ||
| 94 | powerdomains2xxx_3xxx_data.o | ||
| 95 | obj-$(CONFIG_ARCH_OMAP3) += $(powerdomain-common) \ | ||
| 96 | powerdomain2xxx_3xxx.o \ | ||
| 97 | powerdomains3xxx_data.o \ | ||
| 98 | powerdomains2xxx_3xxx_data.o | ||
| 99 | obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) \ | ||
| 100 | powerdomain44xx.o \ | ||
| 101 | powerdomains44xx_data.o | ||
| 102 | |||
| 103 | # PRCM clockdomain control | ||
| 104 | obj-$(CONFIG_ARCH_OMAP2) += clockdomain.o \ | ||
| 105 | clockdomains2xxx_3xxx_data.o | ||
| 106 | obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o \ | ||
| 107 | clockdomains2xxx_3xxx_data.o | ||
| 108 | obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o \ | ||
| 109 | clockdomains44xx_data.o | ||
| 72 | # Clock framework | 110 | # Clock framework |
| 73 | obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o \ | 111 | obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o \ |
| 74 | clkt2xxx_sys.o \ | 112 | clkt2xxx_sys.o \ |
| @@ -139,17 +177,20 @@ obj-$(CONFIG_MACH_OMAP_3430SDP) += board-3430sdp.o \ | |||
| 139 | hsmmc.o \ | 177 | hsmmc.o \ |
| 140 | board-flash.o | 178 | board-flash.o |
| 141 | obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o | 179 | obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o |
| 180 | obj-$(CONFIG_MACH_NOKIA_RM680) += board-rm680.o \ | ||
| 181 | sdram-nokia.o \ | ||
| 182 | hsmmc.o | ||
| 142 | obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \ | 183 | obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \ |
| 143 | board-rx51-sdram.o \ | 184 | sdram-nokia.o \ |
| 144 | board-rx51-peripherals.o \ | 185 | board-rx51-peripherals.o \ |
| 145 | board-rx51-video.o \ | 186 | board-rx51-video.o \ |
| 146 | hsmmc.o | 187 | hsmmc.o |
| 147 | obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom2.o \ | 188 | obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom.o \ |
| 148 | board-zoom-peripherals.o \ | 189 | board-zoom-peripherals.o \ |
| 149 | board-flash.o \ | 190 | board-flash.o \ |
| 150 | hsmmc.o \ | 191 | hsmmc.o \ |
| 151 | board-zoom-debugboard.o | 192 | board-zoom-debugboard.o |
| 152 | obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom3.o \ | 193 | obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom.o \ |
| 153 | board-zoom-peripherals.o \ | 194 | board-zoom-peripherals.o \ |
| 154 | board-flash.o \ | 195 | board-flash.o \ |
| 155 | hsmmc.o \ | 196 | hsmmc.o \ |
| @@ -168,12 +209,16 @@ obj-$(CONFIG_MACH_IGEP0030) += board-igep0030.o \ | |||
| 168 | obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \ | 209 | obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \ |
| 169 | hsmmc.o | 210 | hsmmc.o |
| 170 | obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o \ | 211 | obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o \ |
| 171 | hsmmc.o | 212 | hsmmc.o \ |
| 213 | omap_phy_internal.o | ||
| 172 | obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o \ | 214 | obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o \ |
| 173 | hsmmc.o | 215 | hsmmc.o \ |
| 216 | omap_phy_internal.o | ||
| 174 | 217 | ||
| 175 | obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o | 218 | obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o |
| 176 | 219 | ||
| 220 | obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o | ||
| 221 | |||
| 177 | obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o \ | 222 | obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o \ |
| 178 | hsmmc.o | 223 | hsmmc.o |
| 179 | # Platform specific device init code | 224 | # Platform specific device init code |
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index b527f8d187ad..e0661777f599 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c | |||
| @@ -135,7 +135,7 @@ static inline void board_smc91x_init(void) | |||
| 135 | 135 | ||
| 136 | #endif | 136 | #endif |
| 137 | 137 | ||
| 138 | static struct omap_board_config_kernel sdp2430_config[] = { | 138 | static struct omap_board_config_kernel sdp2430_config[] __initdata = { |
| 139 | {OMAP_TAG_LCD, &sdp2430_lcd_config}, | 139 | {OMAP_TAG_LCD, &sdp2430_lcd_config}, |
| 140 | }; | 140 | }; |
| 141 | 141 | ||
| @@ -143,9 +143,9 @@ static void __init omap_2430sdp_init_irq(void) | |||
| 143 | { | 143 | { |
| 144 | omap_board_config = sdp2430_config; | 144 | omap_board_config = sdp2430_config; |
| 145 | omap_board_config_size = ARRAY_SIZE(sdp2430_config); | 145 | omap_board_config_size = ARRAY_SIZE(sdp2430_config); |
| 146 | omap2_init_common_hw(NULL, NULL); | 146 | omap2_init_common_infrastructure(); |
| 147 | omap2_init_common_devices(NULL, NULL); | ||
| 147 | omap_init_irq(); | 148 | omap_init_irq(); |
| 148 | omap_gpio_init(); | ||
| 149 | } | 149 | } |
| 150 | 150 | ||
| 151 | static struct twl4030_gpio_platform_data sdp2430_gpio_data = { | 151 | static struct twl4030_gpio_platform_data sdp2430_gpio_data = { |
| @@ -218,8 +218,6 @@ static struct omap_usb_config sdp2430_usb_config __initdata = { | |||
| 218 | static struct omap_board_mux board_mux[] __initdata = { | 218 | static struct omap_board_mux board_mux[] __initdata = { |
| 219 | { .reg_offset = OMAP_MUX_TERMINATOR }, | 219 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
| 220 | }; | 220 | }; |
| 221 | #else | ||
| 222 | #define board_mux NULL | ||
| 223 | #endif | 221 | #endif |
| 224 | 222 | ||
| 225 | static void __init omap_2430sdp_init(void) | 223 | static void __init omap_2430sdp_init(void) |
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index 4e3742c512b8..3b39ef1a680a 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c | |||
| @@ -326,9 +326,9 @@ static void __init omap_3430sdp_init_irq(void) | |||
| 326 | omap_board_config = sdp3430_config; | 326 | omap_board_config = sdp3430_config; |
| 327 | omap_board_config_size = ARRAY_SIZE(sdp3430_config); | 327 | omap_board_config_size = ARRAY_SIZE(sdp3430_config); |
| 328 | omap3_pm_init_cpuidle(omap3_cpuidle_params_table); | 328 | omap3_pm_init_cpuidle(omap3_cpuidle_params_table); |
| 329 | omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL); | 329 | omap2_init_common_infrastructure(); |
| 330 | omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL); | ||
| 330 | omap_init_irq(); | 331 | omap_init_irq(); |
| 331 | omap_gpio_init(); | ||
| 332 | } | 332 | } |
| 333 | 333 | ||
| 334 | static int sdp3430_batt_table[] = { | 334 | static int sdp3430_batt_table[] = { |
| @@ -663,8 +663,6 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { | |||
| 663 | static struct omap_board_mux board_mux[] __initdata = { | 663 | static struct omap_board_mux board_mux[] __initdata = { |
| 664 | { .reg_offset = OMAP_MUX_TERMINATOR }, | 664 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
| 665 | }; | 665 | }; |
| 666 | #else | ||
| 667 | #define board_mux NULL | ||
| 668 | #endif | 666 | #endif |
| 669 | 667 | ||
| 670 | /* | 668 | /* |
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c index bbcf580fa097..5d41dbe059a3 100644 --- a/arch/arm/mach-omap2/board-3630sdp.c +++ b/arch/arm/mach-omap2/board-3630sdp.c | |||
| @@ -73,18 +73,16 @@ static void __init omap_sdp_init_irq(void) | |||
| 73 | { | 73 | { |
| 74 | omap_board_config = sdp_config; | 74 | omap_board_config = sdp_config; |
| 75 | omap_board_config_size = ARRAY_SIZE(sdp_config); | 75 | omap_board_config_size = ARRAY_SIZE(sdp_config); |
| 76 | omap2_init_common_hw(h8mbx00u0mer0em_sdrc_params, | 76 | omap2_init_common_infrastructure(); |
| 77 | h8mbx00u0mer0em_sdrc_params); | 77 | omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params, |
| 78 | h8mbx00u0mer0em_sdrc_params); | ||
| 78 | omap_init_irq(); | 79 | omap_init_irq(); |
| 79 | omap_gpio_init(); | ||
| 80 | } | 80 | } |
| 81 | 81 | ||
| 82 | #ifdef CONFIG_OMAP_MUX | 82 | #ifdef CONFIG_OMAP_MUX |
| 83 | static struct omap_board_mux board_mux[] __initdata = { | 83 | static struct omap_board_mux board_mux[] __initdata = { |
| 84 | { .reg_offset = OMAP_MUX_TERMINATOR }, | 84 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
| 85 | }; | 85 | }; |
| 86 | #else | ||
| 87 | #define board_mux NULL | ||
| 88 | #endif | 86 | #endif |
| 89 | 87 | ||
| 90 | /* | 88 | /* |
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index df5a425a49d1..a70bdf28e2bc 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | #include <linux/gpio_keys.h> | 23 | #include <linux/gpio_keys.h> |
| 24 | #include <linux/regulator/machine.h> | 24 | #include <linux/regulator/machine.h> |
| 25 | #include <linux/leds.h> | 25 | #include <linux/leds.h> |
| 26 | #include <linux/leds_pwm.h> | ||
| 26 | 27 | ||
| 27 | #include <mach/hardware.h> | 28 | #include <mach/hardware.h> |
| 28 | #include <mach/omap4-common.h> | 29 | #include <mach/omap4-common.h> |
| @@ -35,6 +36,7 @@ | |||
| 35 | #include <plat/usb.h> | 36 | #include <plat/usb.h> |
| 36 | #include <plat/mmc.h> | 37 | #include <plat/mmc.h> |
| 37 | 38 | ||
| 39 | #include "mux.h" | ||
| 38 | #include "hsmmc.h" | 40 | #include "hsmmc.h" |
| 39 | #include "timer-gp.h" | 41 | #include "timer-gp.h" |
| 40 | #include "control.h" | 42 | #include "control.h" |
| @@ -42,6 +44,7 @@ | |||
| 42 | #define ETH_KS8851_IRQ 34 | 44 | #define ETH_KS8851_IRQ 34 |
| 43 | #define ETH_KS8851_POWER_ON 48 | 45 | #define ETH_KS8851_POWER_ON 48 |
| 44 | #define ETH_KS8851_QUART 138 | 46 | #define ETH_KS8851_QUART 138 |
| 47 | #define OMAP4SDP_MDM_PWR_EN_GPIO 157 | ||
| 45 | #define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184 | 48 | #define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184 |
| 46 | #define OMAP4_SFH7741_ENABLE_GPIO 188 | 49 | #define OMAP4_SFH7741_ENABLE_GPIO 188 |
| 47 | 50 | ||
| @@ -96,6 +99,28 @@ static struct gpio_led_platform_data sdp4430_led_data = { | |||
| 96 | .num_leds = ARRAY_SIZE(sdp4430_gpio_leds), | 99 | .num_leds = ARRAY_SIZE(sdp4430_gpio_leds), |
| 97 | }; | 100 | }; |
| 98 | 101 | ||
| 102 | static struct led_pwm sdp4430_pwm_leds[] = { | ||
| 103 | { | ||
| 104 | .name = "omap4:green:chrg", | ||
| 105 | .pwm_id = 1, | ||
| 106 | .max_brightness = 255, | ||
| 107 | .pwm_period_ns = 7812500, | ||
| 108 | }, | ||
| 109 | }; | ||
| 110 | |||
| 111 | static struct led_pwm_platform_data sdp4430_pwm_data = { | ||
| 112 | .num_leds = ARRAY_SIZE(sdp4430_pwm_leds), | ||
| 113 | .leds = sdp4430_pwm_leds, | ||
| 114 | }; | ||
| 115 | |||
| 116 | static struct platform_device sdp4430_leds_pwm = { | ||
| 117 | .name = "leds_pwm", | ||
| 118 | .id = -1, | ||
| 119 | .dev = { | ||
| 120 | .platform_data = &sdp4430_pwm_data, | ||
| 121 | }, | ||
| 122 | }; | ||
| 123 | |||
| 99 | static int omap_prox_activate(struct device *dev) | 124 | static int omap_prox_activate(struct device *dev) |
| 100 | { | 125 | { |
| 101 | gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 1); | 126 | gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 1); |
| @@ -203,6 +228,7 @@ static struct platform_device *sdp4430_devices[] __initdata = { | |||
| 203 | &sdp4430_lcd_device, | 228 | &sdp4430_lcd_device, |
| 204 | &sdp4430_gpio_keys_device, | 229 | &sdp4430_gpio_keys_device, |
| 205 | &sdp4430_leds_gpio, | 230 | &sdp4430_leds_gpio, |
| 231 | &sdp4430_leds_pwm, | ||
| 206 | }; | 232 | }; |
| 207 | 233 | ||
| 208 | static struct omap_lcd_config sdp4430_lcd_config __initdata = { | 234 | static struct omap_lcd_config sdp4430_lcd_config __initdata = { |
| @@ -217,20 +243,37 @@ static void __init omap_4430sdp_init_irq(void) | |||
| 217 | { | 243 | { |
| 218 | omap_board_config = sdp4430_config; | 244 | omap_board_config = sdp4430_config; |
| 219 | omap_board_config_size = ARRAY_SIZE(sdp4430_config); | 245 | omap_board_config_size = ARRAY_SIZE(sdp4430_config); |
| 220 | omap2_init_common_hw(NULL, NULL); | 246 | omap2_init_common_infrastructure(); |
| 247 | omap2_init_common_devices(NULL, NULL); | ||
| 221 | #ifdef CONFIG_OMAP_32K_TIMER | 248 | #ifdef CONFIG_OMAP_32K_TIMER |
| 222 | omap2_gp_clockevent_set_gptimer(1); | 249 | omap2_gp_clockevent_set_gptimer(1); |
| 223 | #endif | 250 | #endif |
| 224 | gic_init_irq(); | 251 | gic_init_irq(); |
| 225 | omap_gpio_init(); | ||
| 226 | } | 252 | } |
| 227 | 253 | ||
| 254 | static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { | ||
| 255 | .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, | ||
| 256 | .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN, | ||
| 257 | .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, | ||
| 258 | .phy_reset = false, | ||
| 259 | .reset_gpio_port[0] = -EINVAL, | ||
| 260 | .reset_gpio_port[1] = -EINVAL, | ||
| 261 | .reset_gpio_port[2] = -EINVAL, | ||
| 262 | }; | ||
| 263 | |||
| 228 | static struct omap_musb_board_data musb_board_data = { | 264 | static struct omap_musb_board_data musb_board_data = { |
| 229 | .interface_type = MUSB_INTERFACE_UTMI, | 265 | .interface_type = MUSB_INTERFACE_UTMI, |
| 230 | .mode = MUSB_PERIPHERAL, | 266 | .mode = MUSB_OTG, |
| 231 | .power = 100, | 267 | .power = 100, |
| 232 | }; | 268 | }; |
| 233 | 269 | ||
| 270 | static struct twl4030_usb_data omap4_usbphy_data = { | ||
| 271 | .phy_init = omap4430_phy_init, | ||
| 272 | .phy_exit = omap4430_phy_exit, | ||
| 273 | .phy_power = omap4430_phy_power, | ||
| 274 | .phy_set_clock = omap4430_phy_set_clk, | ||
| 275 | }; | ||
| 276 | |||
| 234 | static struct omap2_hsmmc_info mmc[] = { | 277 | static struct omap2_hsmmc_info mmc[] = { |
| 235 | { | 278 | { |
| 236 | .mmc = 1, | 279 | .mmc = 1, |
| @@ -450,6 +493,7 @@ static struct twl4030_platform_data sdp4430_twldata = { | |||
| 450 | .vaux1 = &sdp4430_vaux1, | 493 | .vaux1 = &sdp4430_vaux1, |
| 451 | .vaux2 = &sdp4430_vaux2, | 494 | .vaux2 = &sdp4430_vaux2, |
| 452 | .vaux3 = &sdp4430_vaux3, | 495 | .vaux3 = &sdp4430_vaux3, |
| 496 | .usb = &omap4_usbphy_data | ||
| 453 | }; | 497 | }; |
| 454 | 498 | ||
| 455 | static struct i2c_board_info __initdata sdp4430_i2c_boardinfo[] = { | 499 | static struct i2c_board_info __initdata sdp4430_i2c_boardinfo[] = { |
| @@ -464,6 +508,9 @@ static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = { | |||
| 464 | { | 508 | { |
| 465 | I2C_BOARD_INFO("tmp105", 0x48), | 509 | I2C_BOARD_INFO("tmp105", 0x48), |
| 466 | }, | 510 | }, |
| 511 | { | ||
| 512 | I2C_BOARD_INFO("bh1780", 0x29), | ||
| 513 | }, | ||
| 467 | }; | 514 | }; |
| 468 | static struct i2c_board_info __initdata sdp4430_i2c_4_boardinfo[] = { | 515 | static struct i2c_board_info __initdata sdp4430_i2c_4_boardinfo[] = { |
| 469 | { | 516 | { |
| @@ -505,20 +552,37 @@ static void __init omap_sfh7741prox_init(void) | |||
| 505 | } | 552 | } |
| 506 | } | 553 | } |
| 507 | 554 | ||
| 555 | #ifdef CONFIG_OMAP_MUX | ||
| 556 | static struct omap_board_mux board_mux[] __initdata = { | ||
| 557 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
| 558 | }; | ||
| 559 | #else | ||
| 560 | #define board_mux NULL | ||
| 561 | #endif | ||
| 562 | |||
| 508 | static void __init omap_4430sdp_init(void) | 563 | static void __init omap_4430sdp_init(void) |
| 509 | { | 564 | { |
| 510 | int status; | 565 | int status; |
| 566 | int package = OMAP_PACKAGE_CBS; | ||
| 567 | |||
| 568 | if (omap_rev() == OMAP4430_REV_ES1_0) | ||
| 569 | package = OMAP_PACKAGE_CBL; | ||
| 570 | omap4_mux_init(board_mux, package); | ||
| 511 | 571 | ||
| 512 | omap4_i2c_init(); | 572 | omap4_i2c_init(); |
| 513 | omap_sfh7741prox_init(); | 573 | omap_sfh7741prox_init(); |
| 514 | platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); | 574 | platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); |
| 515 | omap_serial_init(); | 575 | omap_serial_init(); |
| 516 | omap4_twl6030_hsmmc_init(mmc); | 576 | omap4_twl6030_hsmmc_init(mmc); |
| 517 | /* OMAP4 SDP uses internal transceiver so register nop transceiver */ | 577 | |
| 518 | usb_nop_xceiv_register(); | 578 | /* Power on the ULPI PHY */ |
| 519 | /* FIXME: allow multi-omap to boot until musb is updated for omap4 */ | 579 | if (gpio_is_valid(OMAP4SDP_MDM_PWR_EN_GPIO)) { |
| 520 | if (!cpu_is_omap44xx()) | 580 | /* FIXME: Assumes pad is already muxed for GPIO mode */ |
| 521 | usb_musb_init(&musb_board_data); | 581 | gpio_request(OMAP4SDP_MDM_PWR_EN_GPIO, "USBB1 PHY VMDM_3V3"); |
| 582 | gpio_direction_output(OMAP4SDP_MDM_PWR_EN_GPIO, 1); | ||
| 583 | } | ||
| 584 | usb_ehci_init(&ehci_pdata); | ||
| 585 | usb_musb_init(&musb_board_data); | ||
| 522 | 586 | ||
| 523 | status = omap_ethernet_init(); | 587 | status = omap_ethernet_init(); |
| 524 | if (status) { | 588 | if (status) { |
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c new file mode 100644 index 000000000000..71acb5ab281c --- /dev/null +++ b/arch/arm/mach-omap2/board-am3517crane.c | |||
| @@ -0,0 +1,116 @@ | |||
| 1 | /* | ||
| 2 | * Support for AM3517/05 Craneboard | ||
| 3 | * http://www.mistralsolutions.com/products/craneboard.php | ||
| 4 | * | ||
| 5 | * Copyright (C) 2010 Mistral Solutions Pvt Ltd. <www.mistralsolutions.com> | ||
| 6 | * Author: R.Srinath <srinath@mistralsolutions.com> | ||
| 7 | * | ||
| 8 | * Based on mach-omap2/board-am3517evm.c | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify it | ||
| 11 | * under the terms of the GNU General Public License as published by the | ||
| 12 | * Free Software Foundation version 2. | ||
| 13 | * | ||
| 14 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind, | ||
| 15 | * whether express or implied; without even the implied warranty of | ||
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
| 17 | * General Public License for more details. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #include <linux/kernel.h> | ||
| 21 | #include <linux/init.h> | ||
| 22 | #include <linux/gpio.h> | ||
| 23 | |||
| 24 | #include <mach/hardware.h> | ||
| 25 | #include <asm/mach-types.h> | ||
| 26 | #include <asm/mach/arch.h> | ||
| 27 | #include <asm/mach/map.h> | ||
| 28 | |||
| 29 | #include <plat/board.h> | ||
| 30 | #include <plat/common.h> | ||
| 31 | #include <plat/usb.h> | ||
| 32 | |||
| 33 | #include "mux.h" | ||
| 34 | #include "control.h" | ||
| 35 | |||
| 36 | #define GPIO_USB_POWER 35 | ||
| 37 | #define GPIO_USB_NRESET 38 | ||
| 38 | |||
| 39 | |||
| 40 | /* Board initialization */ | ||
| 41 | static struct omap_board_config_kernel am3517_crane_config[] __initdata = { | ||
| 42 | }; | ||
| 43 | |||
| 44 | #ifdef CONFIG_OMAP_MUX | ||
| 45 | static struct omap_board_mux board_mux[] __initdata = { | ||
| 46 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
| 47 | }; | ||
| 48 | #else | ||
| 49 | #define board_mux NULL | ||
| 50 | #endif | ||
| 51 | |||
| 52 | static void __init am3517_crane_init_irq(void) | ||
| 53 | { | ||
| 54 | omap_board_config = am3517_crane_config; | ||
| 55 | omap_board_config_size = ARRAY_SIZE(am3517_crane_config); | ||
| 56 | |||
| 57 | omap2_init_common_infrastructure(); | ||
| 58 | omap2_init_common_devices(NULL, NULL); | ||
| 59 | omap_init_irq(); | ||
| 60 | } | ||
| 61 | |||
| 62 | static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = { | ||
| 63 | .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, | ||
| 64 | .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN, | ||
| 65 | .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, | ||
| 66 | |||
| 67 | .phy_reset = true, | ||
| 68 | .reset_gpio_port[0] = GPIO_USB_NRESET, | ||
| 69 | .reset_gpio_port[1] = -EINVAL, | ||
| 70 | .reset_gpio_port[2] = -EINVAL | ||
| 71 | }; | ||
| 72 | |||
| 73 | static void __init am3517_crane_init(void) | ||
| 74 | { | ||
| 75 | int ret; | ||
| 76 | |||
| 77 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); | ||
| 78 | omap_serial_init(); | ||
| 79 | |||
| 80 | /* Configure GPIO for EHCI port */ | ||
| 81 | if (omap_mux_init_gpio(GPIO_USB_NRESET, OMAP_PIN_OUTPUT)) { | ||
| 82 | pr_err("Can not configure mux for GPIO_USB_NRESET %d\n", | ||
| 83 | GPIO_USB_NRESET); | ||
| 84 | return; | ||
| 85 | } | ||
| 86 | |||
| 87 | if (omap_mux_init_gpio(GPIO_USB_POWER, OMAP_PIN_OUTPUT)) { | ||
| 88 | pr_err("Can not configure mux for GPIO_USB_POWER %d\n", | ||
| 89 | GPIO_USB_POWER); | ||
| 90 | return; | ||
| 91 | } | ||
| 92 | |||
| 93 | ret = gpio_request(GPIO_USB_POWER, "usb_ehci_enable"); | ||
| 94 | if (ret < 0) { | ||
| 95 | pr_err("Can not request GPIO %d\n", GPIO_USB_POWER); | ||
| 96 | return; | ||
| 97 | } | ||
| 98 | |||
| 99 | ret = gpio_direction_output(GPIO_USB_POWER, 1); | ||
| 100 | if (ret < 0) { | ||
| 101 | gpio_free(GPIO_USB_POWER); | ||
| 102 | pr_err("Unable to initialize EHCI power\n"); | ||
| 103 | return; | ||
| 104 | } | ||
| 105 | |||
| 106 | usb_ehci_init(&ehci_pdata); | ||
| 107 | } | ||
| 108 | |||
| 109 | MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD") | ||
| 110 | .boot_params = 0x80000100, | ||
| 111 | .map_io = omap3_map_io, | ||
| 112 | .reserve = omap_reserve, | ||
| 113 | .init_irq = am3517_crane_init_irq, | ||
| 114 | .init_machine = am3517_crane_init, | ||
| 115 | .timer = &omap_timer, | ||
| 116 | MACHINE_END | ||
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 07399505312b..bc1562648020 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c | |||
| @@ -389,10 +389,9 @@ static void __init am3517_evm_init_irq(void) | |||
| 389 | { | 389 | { |
| 390 | omap_board_config = am3517_evm_config; | 390 | omap_board_config = am3517_evm_config; |
| 391 | omap_board_config_size = ARRAY_SIZE(am3517_evm_config); | 391 | omap_board_config_size = ARRAY_SIZE(am3517_evm_config); |
| 392 | 392 | omap2_init_common_infrastructure(); | |
| 393 | omap2_init_common_hw(NULL, NULL); | 393 | omap2_init_common_devices(NULL, NULL); |
| 394 | omap_init_irq(); | 394 | omap_init_irq(); |
| 395 | omap_gpio_init(); | ||
| 396 | } | 395 | } |
| 397 | 396 | ||
| 398 | static struct omap_musb_board_data musb_board_data = { | 397 | static struct omap_musb_board_data musb_board_data = { |
| @@ -442,8 +441,6 @@ static struct omap_board_mux board_mux[] __initdata = { | |||
| 442 | OMAP3_MUX(SAD2D_MCAD23, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), | 441 | OMAP3_MUX(SAD2D_MCAD23, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), |
| 443 | { .reg_offset = OMAP_MUX_TERMINATOR }, | 442 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
| 444 | }; | 443 | }; |
| 445 | #else | ||
| 446 | #define board_mux NULL | ||
| 447 | #endif | 444 | #endif |
| 448 | 445 | ||
| 449 | 446 | ||
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index 2c6db1aaeb29..9f55b68687f7 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c | |||
| @@ -270,7 +270,7 @@ static struct omap_lcd_config apollon_lcd_config __initdata = { | |||
| 270 | .ctrl_name = "internal", | 270 | .ctrl_name = "internal", |
| 271 | }; | 271 | }; |
| 272 | 272 | ||
| 273 | static struct omap_board_config_kernel apollon_config[] = { | 273 | static struct omap_board_config_kernel apollon_config[] __initdata = { |
| 274 | { OMAP_TAG_LCD, &apollon_lcd_config }, | 274 | { OMAP_TAG_LCD, &apollon_lcd_config }, |
| 275 | }; | 275 | }; |
| 276 | 276 | ||
| @@ -278,10 +278,9 @@ static void __init omap_apollon_init_irq(void) | |||
| 278 | { | 278 | { |
| 279 | omap_board_config = apollon_config; | 279 | omap_board_config = apollon_config; |
| 280 | omap_board_config_size = ARRAY_SIZE(apollon_config); | 280 | omap_board_config_size = ARRAY_SIZE(apollon_config); |
| 281 | omap2_init_common_hw(NULL, NULL); | 281 | omap2_init_common_infrastructure(); |
| 282 | omap2_init_common_devices(NULL, NULL); | ||
| 282 | omap_init_irq(); | 283 | omap_init_irq(); |
| 283 | omap_gpio_init(); | ||
| 284 | apollon_init_smc91x(); | ||
| 285 | } | 284 | } |
| 286 | 285 | ||
| 287 | static void __init apollon_led_init(void) | 286 | static void __init apollon_led_init(void) |
| @@ -314,8 +313,6 @@ static void __init apollon_usb_init(void) | |||
| 314 | static struct omap_board_mux board_mux[] __initdata = { | 313 | static struct omap_board_mux board_mux[] __initdata = { |
| 315 | { .reg_offset = OMAP_MUX_TERMINATOR }, | 314 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
| 316 | }; | 315 | }; |
| 317 | #else | ||
| 318 | #define board_mux NULL | ||
| 319 | #endif | 316 | #endif |
| 320 | 317 | ||
| 321 | static void __init omap_apollon_init(void) | 318 | static void __init omap_apollon_init(void) |
| @@ -324,6 +321,7 @@ static void __init omap_apollon_init(void) | |||
| 324 | 321 | ||
| 325 | omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC); | 322 | omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC); |
| 326 | 323 | ||
| 324 | apollon_init_smc91x(); | ||
| 327 | apollon_led_init(); | 325 | apollon_led_init(); |
| 328 | apollon_flash_init(); | 326 | apollon_flash_init(); |
| 329 | apollon_usb_init(); | 327 | apollon_usb_init(); |
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index 63f764e2af3f..486a3de5f401 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c | |||
| @@ -600,8 +600,8 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = { | |||
| 600 | .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, | 600 | .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, |
| 601 | 601 | ||
| 602 | .phy_reset = true, | 602 | .phy_reset = true, |
| 603 | .reset_gpio_port[0] = -EINVAL, | 603 | .reset_gpio_port[0] = OMAP_MAX_GPIO_LINES + 6, |
| 604 | .reset_gpio_port[1] = -EINVAL, | 604 | .reset_gpio_port[1] = OMAP_MAX_GPIO_LINES + 7, |
| 605 | .reset_gpio_port[2] = -EINVAL | 605 | .reset_gpio_port[2] = -EINVAL |
| 606 | }; | 606 | }; |
| 607 | 607 | ||
| @@ -630,12 +630,6 @@ static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio, | |||
| 630 | cm_t35_vmmc1_supply.dev = mmc[0].dev; | 630 | cm_t35_vmmc1_supply.dev = mmc[0].dev; |
| 631 | cm_t35_vsim_supply.dev = mmc[0].dev; | 631 | cm_t35_vsim_supply.dev = mmc[0].dev; |
| 632 | 632 | ||
| 633 | /* setup USB with proper PHY reset GPIOs */ | ||
| 634 | ehci_pdata.reset_gpio_port[0] = gpio + 6; | ||
| 635 | ehci_pdata.reset_gpio_port[1] = gpio + 7; | ||
| 636 | |||
| 637 | usb_ehci_init(&ehci_pdata); | ||
| 638 | |||
| 639 | return 0; | 633 | return 0; |
| 640 | } | 634 | } |
| 641 | 635 | ||
| @@ -683,10 +677,10 @@ static void __init cm_t35_init_irq(void) | |||
| 683 | omap_board_config = cm_t35_config; | 677 | omap_board_config = cm_t35_config; |
| 684 | omap_board_config_size = ARRAY_SIZE(cm_t35_config); | 678 | omap_board_config_size = ARRAY_SIZE(cm_t35_config); |
| 685 | 679 | ||
| 686 | omap2_init_common_hw(mt46h32m32lf6_sdrc_params, | 680 | omap2_init_common_infrastructure(); |
| 681 | omap2_init_common_devices(mt46h32m32lf6_sdrc_params, | ||
| 687 | mt46h32m32lf6_sdrc_params); | 682 | mt46h32m32lf6_sdrc_params); |
| 688 | omap_init_irq(); | 683 | omap_init_irq(); |
| 689 | omap_gpio_init(); | ||
| 690 | } | 684 | } |
| 691 | 685 | ||
| 692 | static struct omap_board_mux board_mux[] __initdata = { | 686 | static struct omap_board_mux board_mux[] __initdata = { |
| @@ -805,6 +799,7 @@ static void __init cm_t35_init(void) | |||
| 805 | cm_t35_init_display(); | 799 | cm_t35_init_display(); |
| 806 | 800 | ||
| 807 | usb_musb_init(&musb_board_data); | 801 | usb_musb_init(&musb_board_data); |
| 802 | usb_ehci_init(&ehci_pdata); | ||
| 808 | } | 803 | } |
| 809 | 804 | ||
| 810 | MACHINE_START(CM_T35, "Compulab CM-T35") | 805 | MACHINE_START(CM_T35, "Compulab CM-T35") |
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c index 1dd303e9a267..5b0c77732dfc 100644 --- a/arch/arm/mach-omap2/board-cm-t3517.c +++ b/arch/arm/mach-omap2/board-cm-t3517.c | |||
| @@ -248,9 +248,9 @@ static void __init cm_t3517_init_irq(void) | |||
| 248 | omap_board_config = cm_t3517_config; | 248 | omap_board_config = cm_t3517_config; |
| 249 | omap_board_config_size = ARRAY_SIZE(cm_t3517_config); | 249 | omap_board_config_size = ARRAY_SIZE(cm_t3517_config); |
| 250 | 250 | ||
| 251 | omap2_init_common_hw(NULL, NULL); | 251 | omap2_init_common_infrastructure(); |
| 252 | omap2_init_common_devices(NULL, NULL); | ||
| 252 | omap_init_irq(); | 253 | omap_init_irq(); |
| 253 | omap_gpio_init(); | ||
| 254 | } | 254 | } |
| 255 | 255 | ||
| 256 | static struct omap_board_mux board_mux[] __initdata = { | 256 | static struct omap_board_mux board_mux[] __initdata = { |
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 53ac762518bd..451e7ff08b18 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c | |||
| @@ -118,27 +118,27 @@ static int devkit8000_panel_enable_lcd(struct omap_dss_device *dssdev) | |||
| 118 | twl_i2c_write_u8(TWL4030_MODULE_LED, 0x0, 0x0); | 118 | twl_i2c_write_u8(TWL4030_MODULE_LED, 0x0, 0x0); |
| 119 | 119 | ||
| 120 | if (gpio_is_valid(dssdev->reset_gpio)) | 120 | if (gpio_is_valid(dssdev->reset_gpio)) |
| 121 | gpio_set_value(dssdev->reset_gpio, 1); | 121 | gpio_set_value_cansleep(dssdev->reset_gpio, 1); |
| 122 | return 0; | 122 | return 0; |
| 123 | } | 123 | } |
| 124 | 124 | ||
| 125 | static void devkit8000_panel_disable_lcd(struct omap_dss_device *dssdev) | 125 | static void devkit8000_panel_disable_lcd(struct omap_dss_device *dssdev) |
| 126 | { | 126 | { |
| 127 | if (gpio_is_valid(dssdev->reset_gpio)) | 127 | if (gpio_is_valid(dssdev->reset_gpio)) |
| 128 | gpio_set_value(dssdev->reset_gpio, 0); | 128 | gpio_set_value_cansleep(dssdev->reset_gpio, 0); |
| 129 | } | 129 | } |
| 130 | 130 | ||
| 131 | static int devkit8000_panel_enable_dvi(struct omap_dss_device *dssdev) | 131 | static int devkit8000_panel_enable_dvi(struct omap_dss_device *dssdev) |
| 132 | { | 132 | { |
| 133 | if (gpio_is_valid(dssdev->reset_gpio)) | 133 | if (gpio_is_valid(dssdev->reset_gpio)) |
| 134 | gpio_set_value(dssdev->reset_gpio, 1); | 134 | gpio_set_value_cansleep(dssdev->reset_gpio, 1); |
| 135 | return 0; | 135 | return 0; |
| 136 | } | 136 | } |
| 137 | 137 | ||
| 138 | static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev) | 138 | static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev) |
| 139 | { | 139 | { |
| 140 | if (gpio_is_valid(dssdev->reset_gpio)) | 140 | if (gpio_is_valid(dssdev->reset_gpio)) |
| 141 | gpio_set_value(dssdev->reset_gpio, 0); | 141 | gpio_set_value_cansleep(dssdev->reset_gpio, 0); |
| 142 | } | 142 | } |
| 143 | 143 | ||
| 144 | static struct regulator_consumer_supply devkit8000_vmmc1_supply = | 144 | static struct regulator_consumer_supply devkit8000_vmmc1_supply = |
| @@ -444,13 +444,13 @@ static struct platform_device keys_gpio = { | |||
| 444 | 444 | ||
| 445 | static void __init devkit8000_init_irq(void) | 445 | static void __init devkit8000_init_irq(void) |
| 446 | { | 446 | { |
| 447 | omap2_init_common_hw(mt46h32m32lf6_sdrc_params, | 447 | omap2_init_common_infrastructure(); |
| 448 | mt46h32m32lf6_sdrc_params); | 448 | omap2_init_common_devices(mt46h32m32lf6_sdrc_params, |
| 449 | mt46h32m32lf6_sdrc_params); | ||
| 449 | omap_init_irq(); | 450 | omap_init_irq(); |
| 450 | #ifdef CONFIG_OMAP_32K_TIMER | 451 | #ifdef CONFIG_OMAP_32K_TIMER |
| 451 | omap2_gp_clockevent_set_gptimer(12); | 452 | omap2_gp_clockevent_set_gptimer(12); |
| 452 | #endif | 453 | #endif |
| 453 | omap_gpio_init(); | ||
| 454 | } | 454 | } |
| 455 | 455 | ||
| 456 | static void __init devkit8000_ads7846_init(void) | 456 | static void __init devkit8000_ads7846_init(void) |
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index b1c2c9a11c38..0e3d81e09f89 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c | |||
| @@ -37,7 +37,8 @@ static void __init omap_generic_init_irq(void) | |||
| 37 | { | 37 | { |
| 38 | omap_board_config = generic_config; | 38 | omap_board_config = generic_config; |
| 39 | omap_board_config_size = ARRAY_SIZE(generic_config); | 39 | omap_board_config_size = ARRAY_SIZE(generic_config); |
| 40 | omap2_init_common_hw(NULL, NULL); | 40 | omap2_init_common_infrastructure(); |
| 41 | omap2_init_common_devices(NULL, NULL); | ||
| 41 | omap_init_irq(); | 42 | omap_init_irq(); |
| 42 | } | 43 | } |
| 43 | 44 | ||
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index 929993b4bf26..25cc9dad4b02 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c | |||
| @@ -51,38 +51,37 @@ | |||
| 51 | static unsigned int row_gpios[6] = { 88, 89, 124, 11, 6, 96 }; | 51 | static unsigned int row_gpios[6] = { 88, 89, 124, 11, 6, 96 }; |
| 52 | static unsigned int col_gpios[7] = { 90, 91, 100, 36, 12, 97, 98 }; | 52 | static unsigned int col_gpios[7] = { 90, 91, 100, 36, 12, 97, 98 }; |
| 53 | 53 | ||
| 54 | static int h4_keymap[] = { | 54 | static const unsigned int h4_keymap[] = { |
| 55 | KEY(0, 0, KEY_LEFT), | 55 | KEY(0, 0, KEY_LEFT), |
| 56 | KEY(0, 1, KEY_RIGHT), | 56 | KEY(1, 0, KEY_RIGHT), |
| 57 | KEY(0, 2, KEY_A), | 57 | KEY(2, 0, KEY_A), |
| 58 | KEY(0, 3, KEY_B), | 58 | KEY(3, 0, KEY_B), |
| 59 | KEY(0, 4, KEY_C), | 59 | KEY(4, 0, KEY_C), |
| 60 | KEY(1, 0, KEY_DOWN), | 60 | KEY(0, 1, KEY_DOWN), |
| 61 | KEY(1, 1, KEY_UP), | 61 | KEY(1, 1, KEY_UP), |
| 62 | KEY(1, 2, KEY_E), | 62 | KEY(2, 1, KEY_E), |
| 63 | KEY(1, 3, KEY_F), | 63 | KEY(3, 1, KEY_F), |
| 64 | KEY(1, 4, KEY_G), | 64 | KEY(4, 1, KEY_G), |
| 65 | KEY(2, 0, KEY_ENTER), | 65 | KEY(0, 2, KEY_ENTER), |
| 66 | KEY(2, 1, KEY_I), | 66 | KEY(1, 2, KEY_I), |
| 67 | KEY(2, 2, KEY_J), | 67 | KEY(2, 2, KEY_J), |
| 68 | KEY(2, 3, KEY_K), | 68 | KEY(3, 2, KEY_K), |
| 69 | KEY(2, 4, KEY_3), | 69 | KEY(4, 2, KEY_3), |
| 70 | KEY(3, 0, KEY_M), | 70 | KEY(0, 3, KEY_M), |
| 71 | KEY(3, 1, KEY_N), | 71 | KEY(1, 3, KEY_N), |
| 72 | KEY(3, 2, KEY_O), | 72 | KEY(2, 3, KEY_O), |
| 73 | KEY(3, 3, KEY_P), | 73 | KEY(3, 3, KEY_P), |
| 74 | KEY(3, 4, KEY_Q), | 74 | KEY(4, 3, KEY_Q), |
| 75 | KEY(4, 0, KEY_R), | 75 | KEY(0, 4, KEY_R), |
| 76 | KEY(4, 1, KEY_4), | 76 | KEY(1, 4, KEY_4), |
| 77 | KEY(4, 2, KEY_T), | 77 | KEY(2, 4, KEY_T), |
| 78 | KEY(4, 3, KEY_U), | 78 | KEY(3, 4, KEY_U), |
| 79 | KEY(4, 4, KEY_ENTER), | 79 | KEY(4, 4, KEY_ENTER), |
| 80 | KEY(5, 0, KEY_V), | 80 | KEY(0, 5, KEY_V), |
| 81 | KEY(5, 1, KEY_W), | 81 | KEY(1, 5, KEY_W), |
| 82 | KEY(5, 2, KEY_L), | 82 | KEY(2, 5, KEY_L), |
| 83 | KEY(5, 3, KEY_S), | 83 | KEY(3, 5, KEY_S), |
| 84 | KEY(5, 4, KEY_ENTER), | 84 | KEY(4, 5, KEY_ENTER), |
| 85 | 0 | ||
| 86 | }; | 85 | }; |
| 87 | 86 | ||
| 88 | static struct mtd_partition h4_partitions[] = { | 87 | static struct mtd_partition h4_partitions[] = { |
| @@ -136,12 +135,16 @@ static struct platform_device h4_flash_device = { | |||
| 136 | .resource = &h4_flash_resource, | 135 | .resource = &h4_flash_resource, |
| 137 | }; | 136 | }; |
| 138 | 137 | ||
| 138 | static const struct matrix_keymap_data h4_keymap_data = { | ||
| 139 | .keymap = h4_keymap, | ||
| 140 | .keymap_size = ARRAY_SIZE(h4_keymap), | ||
| 141 | }; | ||
| 142 | |||
| 139 | static struct omap_kp_platform_data h4_kp_data = { | 143 | static struct omap_kp_platform_data h4_kp_data = { |
| 140 | .rows = 6, | 144 | .rows = 6, |
| 141 | .cols = 7, | 145 | .cols = 7, |
| 142 | .keymap = h4_keymap, | 146 | .keymap_data = &h4_keymap_data, |
| 143 | .keymapsize = ARRAY_SIZE(h4_keymap), | 147 | .rep = true, |
| 144 | .rep = 1, | ||
| 145 | .row_gpios = row_gpios, | 148 | .row_gpios = row_gpios, |
| 146 | .col_gpios = col_gpios, | 149 | .col_gpios = col_gpios, |
| 147 | }; | 150 | }; |
| @@ -283,7 +286,7 @@ static struct omap_usb_config h4_usb_config __initdata = { | |||
| 283 | .hmc_mode = 0x00, /* 0:dev|otg 1:disable 2:disable */ | 286 | .hmc_mode = 0x00, /* 0:dev|otg 1:disable 2:disable */ |
| 284 | }; | 287 | }; |
| 285 | 288 | ||
| 286 | static struct omap_board_config_kernel h4_config[] = { | 289 | static struct omap_board_config_kernel h4_config[] __initdata = { |
| 287 | { OMAP_TAG_LCD, &h4_lcd_config }, | 290 | { OMAP_TAG_LCD, &h4_lcd_config }, |
| 288 | }; | 291 | }; |
| 289 | 292 | ||
| @@ -291,9 +294,9 @@ static void __init omap_h4_init_irq(void) | |||
| 291 | { | 294 | { |
| 292 | omap_board_config = h4_config; | 295 | omap_board_config = h4_config; |
| 293 | omap_board_config_size = ARRAY_SIZE(h4_config); | 296 | omap_board_config_size = ARRAY_SIZE(h4_config); |
| 294 | omap2_init_common_hw(NULL, NULL); | 297 | omap2_init_common_infrastructure(); |
| 298 | omap2_init_common_devices(NULL, NULL); | ||
| 295 | omap_init_irq(); | 299 | omap_init_irq(); |
| 296 | omap_gpio_init(); | ||
| 297 | h4_init_flash(); | 300 | h4_init_flash(); |
| 298 | } | 301 | } |
| 299 | 302 | ||
| @@ -321,8 +324,6 @@ static struct i2c_board_info __initdata h4_i2c_board_info[] = { | |||
| 321 | static struct omap_board_mux board_mux[] __initdata = { | 324 | static struct omap_board_mux board_mux[] __initdata = { |
| 322 | { .reg_offset = OMAP_MUX_TERMINATOR }, | 325 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
| 323 | }; | 326 | }; |
| 324 | #else | ||
| 325 | #define board_mux NULL | ||
| 326 | #endif | 327 | #endif |
| 327 | 328 | ||
| 328 | static void __init omap_h4_init(void) | 329 | static void __init omap_h4_init(void) |
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 5e035a58b809..0afa3011db0f 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c | |||
| @@ -19,6 +19,7 @@ | |||
| 19 | #include <linux/interrupt.h> | 19 | #include <linux/interrupt.h> |
| 20 | 20 | ||
| 21 | #include <linux/regulator/machine.h> | 21 | #include <linux/regulator/machine.h> |
| 22 | #include <linux/regulator/fixed.h> | ||
| 22 | #include <linux/i2c/twl.h> | 23 | #include <linux/i2c/twl.h> |
| 23 | #include <linux/mmc/host.h> | 24 | #include <linux/mmc/host.h> |
| 24 | 25 | ||
| @@ -136,16 +137,9 @@ static struct mtd_partition igep2_onenand_partitions[] = { | |||
| 136 | }, | 137 | }, |
| 137 | }; | 138 | }; |
| 138 | 139 | ||
| 139 | static int igep2_onenand_setup(void __iomem *onenand_base, int freq) | ||
| 140 | { | ||
| 141 | /* nothing is required to be setup for onenand as of now */ | ||
| 142 | return 0; | ||
| 143 | } | ||
| 144 | |||
| 145 | static struct omap_onenand_platform_data igep2_onenand_data = { | 140 | static struct omap_onenand_platform_data igep2_onenand_data = { |
| 146 | .parts = igep2_onenand_partitions, | 141 | .parts = igep2_onenand_partitions, |
| 147 | .nr_parts = ARRAY_SIZE(igep2_onenand_partitions), | 142 | .nr_parts = ARRAY_SIZE(igep2_onenand_partitions), |
| 148 | .onenand_setup = igep2_onenand_setup, | ||
| 149 | .dma_channel = -1, /* disable DMA in OMAP OneNAND driver */ | 143 | .dma_channel = -1, /* disable DMA in OMAP OneNAND driver */ |
| 150 | }; | 144 | }; |
| 151 | 145 | ||
| @@ -159,35 +153,34 @@ static struct platform_device igep2_onenand_device = { | |||
| 159 | 153 | ||
| 160 | static void __init igep2_flash_init(void) | 154 | static void __init igep2_flash_init(void) |
| 161 | { | 155 | { |
| 162 | u8 cs = 0; | 156 | u8 cs = 0; |
| 163 | u8 onenandcs = GPMC_CS_NUM + 1; | 157 | u8 onenandcs = GPMC_CS_NUM + 1; |
| 164 | 158 | ||
| 165 | while (cs < GPMC_CS_NUM) { | 159 | for (cs = 0; cs < GPMC_CS_NUM; cs++) { |
| 166 | u32 ret = 0; | 160 | u32 ret; |
| 167 | ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | 161 | ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); |
| 168 | 162 | ||
| 169 | /* Check if NAND/oneNAND is configured */ | 163 | /* Check if NAND/oneNAND is configured */ |
| 170 | if ((ret & 0xC00) == 0x800) | 164 | if ((ret & 0xC00) == 0x800) |
| 171 | /* NAND found */ | 165 | /* NAND found */ |
| 172 | pr_err("IGEP v2: Unsupported NAND found\n"); | 166 | pr_err("IGEP2: Unsupported NAND found\n"); |
| 173 | else { | 167 | else { |
| 174 | ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | 168 | ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); |
| 175 | if ((ret & 0x3F) == (ONENAND_MAP >> 24)) | 169 | if ((ret & 0x3F) == (ONENAND_MAP >> 24)) |
| 176 | /* ONENAND found */ | 170 | /* ONENAND found */ |
| 177 | onenandcs = cs; | 171 | onenandcs = cs; |
| 178 | } | 172 | } |
| 179 | cs++; | ||
| 180 | } | 173 | } |
| 174 | |||
| 181 | if (onenandcs > GPMC_CS_NUM) { | 175 | if (onenandcs > GPMC_CS_NUM) { |
| 182 | pr_err("IGEP v2: Unable to find configuration in GPMC\n"); | 176 | pr_err("IGEP2: Unable to find configuration in GPMC\n"); |
| 183 | return; | 177 | return; |
| 184 | } | 178 | } |
| 185 | 179 | ||
| 186 | if (onenandcs < GPMC_CS_NUM) { | 180 | igep2_onenand_data.cs = onenandcs; |
| 187 | igep2_onenand_data.cs = onenandcs; | 181 | |
| 188 | if (platform_device_register(&igep2_onenand_device) < 0) | 182 | if (platform_device_register(&igep2_onenand_device) < 0) |
| 189 | pr_err("IGEP v2: Unable to register OneNAND device\n"); | 183 | pr_err("IGEP2: Unable to register OneNAND device\n"); |
| 190 | } | ||
| 191 | } | 184 | } |
| 192 | 185 | ||
| 193 | #else | 186 | #else |
| @@ -254,12 +247,8 @@ static inline void __init igep2_init_smsc911x(void) | |||
| 254 | static inline void __init igep2_init_smsc911x(void) { } | 247 | static inline void __init igep2_init_smsc911x(void) { } |
| 255 | #endif | 248 | #endif |
| 256 | 249 | ||
| 257 | static struct omap_board_config_kernel igep2_config[] __initdata = { | 250 | static struct regulator_consumer_supply igep2_vmmc1_supply = |
| 258 | }; | 251 | REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); |
| 259 | |||
| 260 | static struct regulator_consumer_supply igep2_vmmc1_supply = { | ||
| 261 | .supply = "vmmc", | ||
| 262 | }; | ||
| 263 | 252 | ||
| 264 | /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ | 253 | /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ |
| 265 | static struct regulator_init_data igep2_vmmc1 = { | 254 | static struct regulator_init_data igep2_vmmc1 = { |
| @@ -276,6 +265,52 @@ static struct regulator_init_data igep2_vmmc1 = { | |||
| 276 | .consumer_supplies = &igep2_vmmc1_supply, | 265 | .consumer_supplies = &igep2_vmmc1_supply, |
| 277 | }; | 266 | }; |
| 278 | 267 | ||
| 268 | static struct regulator_consumer_supply igep2_vio_supply = | ||
| 269 | REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1"); | ||
| 270 | |||
| 271 | static struct regulator_init_data igep2_vio = { | ||
| 272 | .constraints = { | ||
| 273 | .min_uV = 1800000, | ||
| 274 | .max_uV = 1800000, | ||
| 275 | .apply_uV = 1, | ||
| 276 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 277 | | REGULATOR_MODE_STANDBY, | ||
| 278 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | ||
| 279 | | REGULATOR_CHANGE_MODE | ||
| 280 | | REGULATOR_CHANGE_STATUS, | ||
| 281 | }, | ||
| 282 | .num_consumer_supplies = 1, | ||
| 283 | .consumer_supplies = &igep2_vio_supply, | ||
| 284 | }; | ||
| 285 | |||
| 286 | static struct regulator_consumer_supply igep2_vmmc2_supply = | ||
| 287 | REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); | ||
| 288 | |||
| 289 | static struct regulator_init_data igep2_vmmc2 = { | ||
| 290 | .constraints = { | ||
| 291 | .valid_modes_mask = REGULATOR_MODE_NORMAL, | ||
| 292 | .always_on = 1, | ||
| 293 | }, | ||
| 294 | .num_consumer_supplies = 1, | ||
| 295 | .consumer_supplies = &igep2_vmmc2_supply, | ||
| 296 | }; | ||
| 297 | |||
| 298 | static struct fixed_voltage_config igep2_vwlan = { | ||
| 299 | .supply_name = "vwlan", | ||
| 300 | .microvolts = 3300000, | ||
| 301 | .gpio = -EINVAL, | ||
| 302 | .enabled_at_boot = 1, | ||
| 303 | .init_data = &igep2_vmmc2, | ||
| 304 | }; | ||
| 305 | |||
| 306 | static struct platform_device igep2_vwlan_device = { | ||
| 307 | .name = "reg-fixed-voltage", | ||
| 308 | .id = 0, | ||
| 309 | .dev = { | ||
| 310 | .platform_data = &igep2_vwlan, | ||
| 311 | }, | ||
| 312 | }; | ||
| 313 | |||
| 279 | static struct omap2_hsmmc_info mmc[] = { | 314 | static struct omap2_hsmmc_info mmc[] = { |
| 280 | { | 315 | { |
| 281 | .mmc = 1, | 316 | .mmc = 1, |
| @@ -317,6 +352,7 @@ static struct gpio_led igep2_gpio_leds[] = { | |||
| 317 | .name = "gpio-led:green:d1", | 352 | .name = "gpio-led:green:d1", |
| 318 | .default_trigger = "heartbeat", | 353 | .default_trigger = "heartbeat", |
| 319 | .gpio = -EINVAL, /* gets replaced */ | 354 | .gpio = -EINVAL, /* gets replaced */ |
| 355 | .active_low = 1, | ||
| 320 | }, | 356 | }, |
| 321 | }; | 357 | }; |
| 322 | 358 | ||
| @@ -342,24 +378,21 @@ static void __init igep2_leds_init(void) | |||
| 342 | static inline void igep2_leds_init(void) | 378 | static inline void igep2_leds_init(void) |
| 343 | { | 379 | { |
| 344 | if ((gpio_request(IGEP2_GPIO_LED0_RED, "gpio-led:red:d0") == 0) && | 380 | if ((gpio_request(IGEP2_GPIO_LED0_RED, "gpio-led:red:d0") == 0) && |
| 345 | (gpio_direction_output(IGEP2_GPIO_LED0_RED, 1) == 0)) { | 381 | (gpio_direction_output(IGEP2_GPIO_LED0_RED, 0) == 0)) |
| 346 | gpio_export(IGEP2_GPIO_LED0_RED, 0); | 382 | gpio_export(IGEP2_GPIO_LED0_RED, 0); |
| 347 | gpio_set_value(IGEP2_GPIO_LED0_RED, 0); | 383 | else |
| 348 | } else | ||
| 349 | pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_RED\n"); | 384 | pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_RED\n"); |
| 350 | 385 | ||
| 351 | if ((gpio_request(IGEP2_GPIO_LED0_GREEN, "gpio-led:green:d0") == 0) && | 386 | if ((gpio_request(IGEP2_GPIO_LED0_GREEN, "gpio-led:green:d0") == 0) && |
| 352 | (gpio_direction_output(IGEP2_GPIO_LED0_GREEN, 1) == 0)) { | 387 | (gpio_direction_output(IGEP2_GPIO_LED0_GREEN, 0) == 0)) |
| 353 | gpio_export(IGEP2_GPIO_LED0_GREEN, 0); | 388 | gpio_export(IGEP2_GPIO_LED0_GREEN, 0); |
| 354 | gpio_set_value(IGEP2_GPIO_LED0_GREEN, 0); | 389 | else |
| 355 | } else | ||
| 356 | pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_GREEN\n"); | 390 | pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_GREEN\n"); |
| 357 | 391 | ||
| 358 | if ((gpio_request(IGEP2_GPIO_LED1_RED, "gpio-led:red:d1") == 0) && | 392 | if ((gpio_request(IGEP2_GPIO_LED1_RED, "gpio-led:red:d1") == 0) && |
| 359 | (gpio_direction_output(IGEP2_GPIO_LED1_RED, 1) == 0)) { | 393 | (gpio_direction_output(IGEP2_GPIO_LED1_RED, 0) == 0)) |
| 360 | gpio_export(IGEP2_GPIO_LED1_RED, 0); | 394 | gpio_export(IGEP2_GPIO_LED1_RED, 0); |
| 361 | gpio_set_value(IGEP2_GPIO_LED1_RED, 0); | 395 | else |
| 362 | } else | ||
| 363 | pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_RED\n"); | 396 | pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_RED\n"); |
| 364 | 397 | ||
| 365 | } | 398 | } |
| @@ -373,12 +406,6 @@ static int igep2_twl_gpio_setup(struct device *dev, | |||
| 373 | omap2_hsmmc_init(mmc); | 406 | omap2_hsmmc_init(mmc); |
| 374 | 407 | ||
| 375 | /* | 408 | /* |
| 376 | * link regulators to MMC adapters ... we "know" the | ||
| 377 | * regulators will be set up only *after* we return. | ||
| 378 | */ | ||
| 379 | igep2_vmmc1_supply.dev = mmc[0].dev; | ||
| 380 | |||
| 381 | /* | ||
| 382 | * REVISIT: need ehci-omap hooks for external VBUS | 409 | * REVISIT: need ehci-omap hooks for external VBUS |
| 383 | * power switch and overcurrent detect | 410 | * power switch and overcurrent detect |
| 384 | */ | 411 | */ |
| @@ -397,10 +424,9 @@ static int igep2_twl_gpio_setup(struct device *dev, | |||
| 397 | /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */ | 424 | /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */ |
| 398 | #if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE) | 425 | #if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE) |
| 399 | if ((gpio_request(gpio+TWL4030_GPIO_MAX+1, "gpio-led:green:d1") == 0) | 426 | if ((gpio_request(gpio+TWL4030_GPIO_MAX+1, "gpio-led:green:d1") == 0) |
| 400 | && (gpio_direction_output(gpio + TWL4030_GPIO_MAX + 1, 1) == 0)) { | 427 | && (gpio_direction_output(gpio + TWL4030_GPIO_MAX + 1, 1) == 0)) |
| 401 | gpio_export(gpio + TWL4030_GPIO_MAX + 1, 0); | 428 | gpio_export(gpio + TWL4030_GPIO_MAX + 1, 0); |
| 402 | gpio_set_value(gpio + TWL4030_GPIO_MAX + 1, 0); | 429 | else |
| 403 | } else | ||
| 404 | pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_GREEN\n"); | 430 | pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_GREEN\n"); |
| 405 | #else | 431 | #else |
| 406 | igep2_gpio_leds[3].gpio = gpio + TWL4030_GPIO_MAX + 1; | 432 | igep2_gpio_leds[3].gpio = gpio + TWL4030_GPIO_MAX + 1; |
| @@ -489,15 +515,15 @@ static void __init igep2_display_init(void) | |||
| 489 | 515 | ||
| 490 | static struct platform_device *igep2_devices[] __initdata = { | 516 | static struct platform_device *igep2_devices[] __initdata = { |
| 491 | &igep2_dss_device, | 517 | &igep2_dss_device, |
| 518 | &igep2_vwlan_device, | ||
| 492 | }; | 519 | }; |
| 493 | 520 | ||
| 494 | static void __init igep2_init_irq(void) | 521 | static void __init igep2_init_irq(void) |
| 495 | { | 522 | { |
| 496 | omap_board_config = igep2_config; | 523 | omap2_init_common_infrastructure(); |
| 497 | omap_board_config_size = ARRAY_SIZE(igep2_config); | 524 | omap2_init_common_devices(m65kxxxxam_sdrc_params, |
| 498 | omap2_init_common_hw(m65kxxxxam_sdrc_params, m65kxxxxam_sdrc_params); | 525 | m65kxxxxam_sdrc_params); |
| 499 | omap_init_irq(); | 526 | omap_init_irq(); |
| 500 | omap_gpio_init(); | ||
| 501 | } | 527 | } |
| 502 | 528 | ||
| 503 | static struct twl4030_codec_audio_data igep2_audio_data = { | 529 | static struct twl4030_codec_audio_data igep2_audio_data = { |
| @@ -519,7 +545,7 @@ static struct twl4030_platform_data igep2_twldata = { | |||
| 519 | .gpio = &igep2_twl4030_gpio_pdata, | 545 | .gpio = &igep2_twl4030_gpio_pdata, |
| 520 | .vmmc1 = &igep2_vmmc1, | 546 | .vmmc1 = &igep2_vmmc1, |
| 521 | .vpll2 = &igep2_vpll2, | 547 | .vpll2 = &igep2_vpll2, |
| 522 | 548 | .vio = &igep2_vio, | |
| 523 | }; | 549 | }; |
| 524 | 550 | ||
| 525 | static struct i2c_board_info __initdata igep2_i2c1_boardinfo[] = { | 551 | static struct i2c_board_info __initdata igep2_i2c1_boardinfo[] = { |
| @@ -577,8 +603,6 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { | |||
| 577 | static struct omap_board_mux board_mux[] __initdata = { | 603 | static struct omap_board_mux board_mux[] __initdata = { |
| 578 | { .reg_offset = OMAP_MUX_TERMINATOR }, | 604 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
| 579 | }; | 605 | }; |
| 580 | #else | ||
| 581 | #define board_mux NULL | ||
| 582 | #endif | 606 | #endif |
| 583 | 607 | ||
| 584 | #if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE) | 608 | #if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE) |
diff --git a/arch/arm/mach-omap2/board-igep0030.c b/arch/arm/mach-omap2/board-igep0030.c index 22b0b253e16b..bcccd68f1856 100644 --- a/arch/arm/mach-omap2/board-igep0030.c +++ b/arch/arm/mach-omap2/board-igep0030.c | |||
| @@ -289,9 +289,10 @@ static struct twl4030_usb_data igep3_twl4030_usb_data = { | |||
| 289 | 289 | ||
| 290 | static void __init igep3_init_irq(void) | 290 | static void __init igep3_init_irq(void) |
| 291 | { | 291 | { |
| 292 | omap2_init_common_hw(m65kxxxxam_sdrc_params, m65kxxxxam_sdrc_params); | 292 | omap2_init_common_infrastructure(); |
| 293 | omap2_init_common_devices(m65kxxxxam_sdrc_params, | ||
| 294 | m65kxxxxam_sdrc_params); | ||
| 293 | omap_init_irq(); | 295 | omap_init_irq(); |
| 294 | omap_gpio_init(); | ||
| 295 | } | 296 | } |
| 296 | 297 | ||
| 297 | static struct twl4030_platform_data igep3_twl4030_pdata = { | 298 | static struct twl4030_platform_data igep3_twl4030_pdata = { |
| @@ -366,8 +367,6 @@ void __init igep3_wifi_bt_init(void) {} | |||
| 366 | static struct omap_board_mux board_mux[] __initdata = { | 367 | static struct omap_board_mux board_mux[] __initdata = { |
| 367 | { .reg_offset = OMAP_MUX_TERMINATOR }, | 368 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
| 368 | }; | 369 | }; |
| 369 | #else | ||
| 370 | #define board_mux NULL | ||
| 371 | #endif | 370 | #endif |
| 372 | 371 | ||
| 373 | static void __init igep3_init(void) | 372 | static void __init igep3_init(void) |
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index 001fd9713f39..e5dc74875f9d 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c | |||
| @@ -292,10 +292,9 @@ static void __init omap_ldp_init_irq(void) | |||
| 292 | { | 292 | { |
| 293 | omap_board_config = ldp_config; | 293 | omap_board_config = ldp_config; |
| 294 | omap_board_config_size = ARRAY_SIZE(ldp_config); | 294 | omap_board_config_size = ARRAY_SIZE(ldp_config); |
| 295 | omap2_init_common_hw(NULL, NULL); | 295 | omap2_init_common_infrastructure(); |
| 296 | omap2_init_common_devices(NULL, NULL); | ||
| 296 | omap_init_irq(); | 297 | omap_init_irq(); |
| 297 | omap_gpio_init(); | ||
| 298 | ldp_init_smsc911x(); | ||
| 299 | } | 298 | } |
| 300 | 299 | ||
| 301 | static struct twl4030_usb_data ldp_usb_data = { | 300 | static struct twl4030_usb_data ldp_usb_data = { |
| @@ -381,8 +380,6 @@ static struct platform_device *ldp_devices[] __initdata = { | |||
| 381 | static struct omap_board_mux board_mux[] __initdata = { | 380 | static struct omap_board_mux board_mux[] __initdata = { |
| 382 | { .reg_offset = OMAP_MUX_TERMINATOR }, | 381 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
| 383 | }; | 382 | }; |
| 384 | #else | ||
| 385 | #define board_mux NULL | ||
| 386 | #endif | 383 | #endif |
| 387 | 384 | ||
| 388 | static struct omap_musb_board_data musb_board_data = { | 385 | static struct omap_musb_board_data musb_board_data = { |
| @@ -426,6 +423,7 @@ static struct mtd_partition ldp_nand_partitions[] = { | |||
| 426 | static void __init omap_ldp_init(void) | 423 | static void __init omap_ldp_init(void) |
| 427 | { | 424 | { |
| 428 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); | 425 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); |
| 426 | ldp_init_smsc911x(); | ||
| 429 | omap_i2c_init(); | 427 | omap_i2c_init(); |
| 430 | platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices)); | 428 | platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices)); |
| 431 | ts_gpio = 54; | 429 | ts_gpio = 54; |
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index e823c7042ab3..f396756872b7 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c | |||
| @@ -46,8 +46,7 @@ static struct device *mmc_device; | |||
| 46 | #define TUSB6010_GPIO_ENABLE 0 | 46 | #define TUSB6010_GPIO_ENABLE 0 |
| 47 | #define TUSB6010_DMACHAN 0x3f | 47 | #define TUSB6010_DMACHAN 0x3f |
| 48 | 48 | ||
| 49 | #if defined(CONFIG_USB_TUSB6010) || \ | 49 | #ifdef CONFIG_USB_MUSB_TUSB6010 |
| 50 | defined(CONFIG_USB_TUSB6010_MODULE) | ||
| 51 | /* | 50 | /* |
| 52 | * Enable or disable power to TUSB6010. When enabling, turn on 3.3 V and | 51 | * Enable or disable power to TUSB6010. When enabling, turn on 3.3 V and |
| 53 | * 1.5 V voltage regulators of PM companion chip. Companion chip will then | 52 | * 1.5 V voltage regulators of PM companion chip. Companion chip will then |
| @@ -134,7 +133,7 @@ err: | |||
| 134 | 133 | ||
| 135 | static void __init n8x0_usb_init(void) {} | 134 | static void __init n8x0_usb_init(void) {} |
| 136 | 135 | ||
| 137 | #endif /*CONFIG_USB_TUSB6010 */ | 136 | #endif /*CONFIG_USB_MUSB_TUSB6010 */ |
| 138 | 137 | ||
| 139 | 138 | ||
| 140 | static struct omap2_mcspi_device_config p54spi_mcspi_config = { | 139 | static struct omap2_mcspi_device_config p54spi_mcspi_config = { |
| @@ -184,23 +183,15 @@ static struct mtd_partition onenand_partitions[] = { | |||
| 184 | }, | 183 | }, |
| 185 | }; | 184 | }; |
| 186 | 185 | ||
| 187 | static struct omap_onenand_platform_data board_onenand_data = { | 186 | static struct omap_onenand_platform_data board_onenand_data[] = { |
| 188 | .cs = 0, | 187 | { |
| 189 | .gpio_irq = 26, | 188 | .cs = 0, |
| 190 | .parts = onenand_partitions, | 189 | .gpio_irq = 26, |
| 191 | .nr_parts = ARRAY_SIZE(onenand_partitions), | 190 | .parts = onenand_partitions, |
| 192 | .flags = ONENAND_SYNC_READ, | 191 | .nr_parts = ARRAY_SIZE(onenand_partitions), |
| 192 | .flags = ONENAND_SYNC_READ, | ||
| 193 | } | ||
| 193 | }; | 194 | }; |
| 194 | |||
| 195 | static void __init n8x0_onenand_init(void) | ||
| 196 | { | ||
| 197 | gpmc_onenand_init(&board_onenand_data); | ||
| 198 | } | ||
| 199 | |||
| 200 | #else | ||
| 201 | |||
| 202 | static void __init n8x0_onenand_init(void) {} | ||
| 203 | |||
| 204 | #endif | 195 | #endif |
| 205 | 196 | ||
| 206 | #if defined(CONFIG_MENELAUS) && \ | 197 | #if defined(CONFIG_MENELAUS) && \ |
| @@ -639,9 +630,9 @@ static void __init n8x0_map_io(void) | |||
| 639 | 630 | ||
| 640 | static void __init n8x0_init_irq(void) | 631 | static void __init n8x0_init_irq(void) |
| 641 | { | 632 | { |
| 642 | omap2_init_common_hw(NULL, NULL); | 633 | omap2_init_common_infrastructure(); |
| 634 | omap2_init_common_devices(NULL, NULL); | ||
| 643 | omap_init_irq(); | 635 | omap_init_irq(); |
| 644 | omap_gpio_init(); | ||
| 645 | } | 636 | } |
| 646 | 637 | ||
| 647 | #ifdef CONFIG_OMAP_MUX | 638 | #ifdef CONFIG_OMAP_MUX |
| @@ -653,8 +644,43 @@ static struct omap_board_mux board_mux[] __initdata = { | |||
| 653 | OMAP2420_MUX(EAC_AC_DOUT, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), | 644 | OMAP2420_MUX(EAC_AC_DOUT, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), |
| 654 | { .reg_offset = OMAP_MUX_TERMINATOR }, | 645 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
| 655 | }; | 646 | }; |
| 647 | |||
| 648 | static struct omap_device_pad serial2_pads[] __initdata = { | ||
| 649 | { | ||
| 650 | .name = "uart3_rx_irrx.uart3_rx_irrx", | ||
| 651 | .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP, | ||
| 652 | .enable = OMAP_MUX_MODE0, | ||
| 653 | .idle = OMAP_MUX_MODE3 /* Mux as GPIO for idle */ | ||
| 654 | }, | ||
| 655 | }; | ||
| 656 | |||
| 657 | static inline void board_serial_init(void) | ||
| 658 | { | ||
| 659 | struct omap_board_data bdata; | ||
| 660 | |||
| 661 | bdata.flags = 0; | ||
| 662 | bdata.pads = NULL; | ||
| 663 | bdata.pads_cnt = 0; | ||
| 664 | |||
| 665 | bdata.id = 0; | ||
| 666 | omap_serial_init_port(&bdata); | ||
| 667 | |||
| 668 | bdata.id = 1; | ||
| 669 | omap_serial_init_port(&bdata); | ||
| 670 | |||
| 671 | bdata.id = 2; | ||
| 672 | bdata.pads = serial2_pads; | ||
| 673 | bdata.pads_cnt = ARRAY_SIZE(serial2_pads); | ||
| 674 | omap_serial_init_port(&bdata); | ||
| 675 | } | ||
| 676 | |||
| 656 | #else | 677 | #else |
| 657 | #define board_mux NULL | 678 | |
| 679 | static inline void board_serial_init(void) | ||
| 680 | { | ||
| 681 | omap_serial_init(); | ||
| 682 | } | ||
| 683 | |||
| 658 | #endif | 684 | #endif |
| 659 | 685 | ||
| 660 | static void __init n8x0_init_machine(void) | 686 | static void __init n8x0_init_machine(void) |
| @@ -669,9 +695,8 @@ static void __init n8x0_init_machine(void) | |||
| 669 | if (machine_is_nokia_n810()) | 695 | if (machine_is_nokia_n810()) |
| 670 | i2c_register_board_info(2, n810_i2c_board_info_2, | 696 | i2c_register_board_info(2, n810_i2c_board_info_2, |
| 671 | ARRAY_SIZE(n810_i2c_board_info_2)); | 697 | ARRAY_SIZE(n810_i2c_board_info_2)); |
| 672 | 698 | board_serial_init(); | |
| 673 | omap_serial_init(); | 699 | gpmc_onenand_init(board_onenand_data); |
| 674 | n8x0_onenand_init(); | ||
| 675 | n8x0_mmc_init(); | 700 | n8x0_mmc_init(); |
| 676 | n8x0_usb_init(); | 701 | n8x0_usb_init(); |
| 677 | } | 702 | } |
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 14f42240ae79..6c127605942f 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c | |||
| @@ -484,13 +484,13 @@ static struct platform_device keys_gpio = { | |||
| 484 | 484 | ||
| 485 | static void __init omap3_beagle_init_irq(void) | 485 | static void __init omap3_beagle_init_irq(void) |
| 486 | { | 486 | { |
| 487 | omap2_init_common_hw(mt46h32m32lf6_sdrc_params, | 487 | omap2_init_common_infrastructure(); |
| 488 | mt46h32m32lf6_sdrc_params); | 488 | omap2_init_common_devices(mt46h32m32lf6_sdrc_params, |
| 489 | mt46h32m32lf6_sdrc_params); | ||
| 489 | omap_init_irq(); | 490 | omap_init_irq(); |
| 490 | #ifdef CONFIG_OMAP_32K_TIMER | 491 | #ifdef CONFIG_OMAP_32K_TIMER |
| 491 | omap2_gp_clockevent_set_gptimer(12); | 492 | omap2_gp_clockevent_set_gptimer(12); |
| 492 | #endif | 493 | #endif |
| 493 | omap_gpio_init(); | ||
| 494 | } | 494 | } |
| 495 | 495 | ||
| 496 | static struct platform_device *omap3_beagle_devices[] __initdata = { | 496 | static struct platform_device *omap3_beagle_devices[] __initdata = { |
| @@ -548,8 +548,6 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { | |||
| 548 | static struct omap_board_mux board_mux[] __initdata = { | 548 | static struct omap_board_mux board_mux[] __initdata = { |
| 549 | { .reg_offset = OMAP_MUX_TERMINATOR }, | 549 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
| 550 | }; | 550 | }; |
| 551 | #else | ||
| 552 | #define board_mux NULL | ||
| 553 | #endif | 551 | #endif |
| 554 | 552 | ||
| 555 | static struct omap_musb_board_data musb_board_data = { | 553 | static struct omap_musb_board_data musb_board_data = { |
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index b04365c6bb10..3de8d9b8ec76 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c | |||
| @@ -623,9 +623,9 @@ static void __init omap3_evm_init_irq(void) | |||
| 623 | { | 623 | { |
| 624 | omap_board_config = omap3_evm_config; | 624 | omap_board_config = omap3_evm_config; |
| 625 | omap_board_config_size = ARRAY_SIZE(omap3_evm_config); | 625 | omap_board_config_size = ARRAY_SIZE(omap3_evm_config); |
| 626 | omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL); | 626 | omap2_init_common_infrastructure(); |
| 627 | omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL); | ||
| 627 | omap_init_irq(); | 628 | omap_init_irq(); |
| 628 | omap_gpio_init(); | ||
| 629 | } | 629 | } |
| 630 | 630 | ||
| 631 | static struct platform_device *omap3_evm_devices[] __initdata = { | 631 | static struct platform_device *omap3_evm_devices[] __initdata = { |
| @@ -654,8 +654,6 @@ static struct omap_board_mux board_mux[] __initdata = { | |||
| 654 | OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW), | 654 | OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW), |
| 655 | { .reg_offset = OMAP_MUX_TERMINATOR }, | 655 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
| 656 | }; | 656 | }; |
| 657 | #else | ||
| 658 | #define board_mux NULL | ||
| 659 | #endif | 657 | #endif |
| 660 | 658 | ||
| 661 | static struct omap_musb_board_data musb_board_data = { | 659 | static struct omap_musb_board_data musb_board_data = { |
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c index 5f7d2c1e7ef5..15e4b08e99ba 100644 --- a/arch/arm/mach-omap2/board-omap3logic.c +++ b/arch/arm/mach-omap2/board-omap3logic.c | |||
| @@ -197,17 +197,15 @@ static inline void __init board_smsc911x_init(void) | |||
| 197 | 197 | ||
| 198 | static void __init omap3logic_init_irq(void) | 198 | static void __init omap3logic_init_irq(void) |
| 199 | { | 199 | { |
| 200 | omap2_init_common_hw(NULL, NULL); | 200 | omap2_init_common_infrastructure(); |
| 201 | omap2_init_common_devices(NULL, NULL); | ||
| 201 | omap_init_irq(); | 202 | omap_init_irq(); |
| 202 | omap_gpio_init(); | ||
| 203 | } | 203 | } |
| 204 | 204 | ||
| 205 | #ifdef CONFIG_OMAP_MUX | 205 | #ifdef CONFIG_OMAP_MUX |
| 206 | static struct omap_board_mux board_mux[] __initdata = { | 206 | static struct omap_board_mux board_mux[] __initdata = { |
| 207 | { .reg_offset = OMAP_MUX_TERMINATOR }, | 207 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
| 208 | }; | 208 | }; |
| 209 | #else | ||
| 210 | #define board_mux NULL | ||
| 211 | #endif | 209 | #endif |
| 212 | 210 | ||
| 213 | static void __init omap3logic_init(void) | 211 | static void __init omap3logic_init(void) |
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index 89ed1be2d62e..0b34beded11f 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c | |||
| @@ -293,7 +293,7 @@ static struct omap2_hsmmc_info omap3pandora_mmc[] = { | |||
| 293 | }, | 293 | }, |
| 294 | { | 294 | { |
| 295 | .mmc = 3, | 295 | .mmc = 3, |
| 296 | .caps = MMC_CAP_4_BIT_DATA, | 296 | .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD, |
| 297 | .gpio_cd = -EINVAL, | 297 | .gpio_cd = -EINVAL, |
| 298 | .gpio_wp = -EINVAL, | 298 | .gpio_wp = -EINVAL, |
| 299 | .init_card = pandora_wl1251_init_card, | 299 | .init_card = pandora_wl1251_init_card, |
| @@ -636,37 +636,19 @@ static struct spi_board_info omap3pandora_spi_board_info[] __initdata = { | |||
| 636 | 636 | ||
| 637 | static void __init omap3pandora_init_irq(void) | 637 | static void __init omap3pandora_init_irq(void) |
| 638 | { | 638 | { |
| 639 | omap2_init_common_hw(mt46h32m32lf6_sdrc_params, | 639 | omap2_init_common_infrastructure(); |
| 640 | mt46h32m32lf6_sdrc_params); | 640 | omap2_init_common_devices(mt46h32m32lf6_sdrc_params, |
| 641 | mt46h32m32lf6_sdrc_params); | ||
| 641 | omap_init_irq(); | 642 | omap_init_irq(); |
| 642 | omap_gpio_init(); | ||
| 643 | } | ||
| 644 | |||
| 645 | static void pandora_wl1251_set_power(bool enable) | ||
| 646 | { | ||
| 647 | /* | ||
| 648 | * Keep power always on until wl1251_sdio driver learns to re-init | ||
| 649 | * the chip after powering it down and back up. | ||
| 650 | */ | ||
| 651 | } | 643 | } |
| 652 | 644 | ||
| 653 | static struct wl12xx_platform_data pandora_wl1251_pdata = { | 645 | static void __init pandora_wl1251_init(void) |
| 654 | .set_power = pandora_wl1251_set_power, | ||
| 655 | .use_eeprom = true, | ||
| 656 | }; | ||
| 657 | |||
| 658 | static struct platform_device pandora_wl1251_data = { | ||
| 659 | .name = "wl1251_data", | ||
| 660 | .id = -1, | ||
| 661 | .dev = { | ||
| 662 | .platform_data = &pandora_wl1251_pdata, | ||
| 663 | }, | ||
| 664 | }; | ||
| 665 | |||
| 666 | static void pandora_wl1251_init(void) | ||
| 667 | { | 646 | { |
| 647 | struct wl12xx_platform_data pandora_wl1251_pdata; | ||
| 668 | int ret; | 648 | int ret; |
| 669 | 649 | ||
| 650 | memset(&pandora_wl1251_pdata, 0, sizeof(pandora_wl1251_pdata)); | ||
| 651 | |||
| 670 | ret = gpio_request(PANDORA_WIFI_IRQ_GPIO, "wl1251 irq"); | 652 | ret = gpio_request(PANDORA_WIFI_IRQ_GPIO, "wl1251 irq"); |
| 671 | if (ret < 0) | 653 | if (ret < 0) |
| 672 | goto fail; | 654 | goto fail; |
| @@ -679,6 +661,11 @@ static void pandora_wl1251_init(void) | |||
| 679 | if (pandora_wl1251_pdata.irq < 0) | 661 | if (pandora_wl1251_pdata.irq < 0) |
| 680 | goto fail_irq; | 662 | goto fail_irq; |
| 681 | 663 | ||
| 664 | pandora_wl1251_pdata.use_eeprom = true; | ||
| 665 | ret = wl12xx_set_platform_data(&pandora_wl1251_pdata); | ||
| 666 | if (ret < 0) | ||
| 667 | goto fail_irq; | ||
| 668 | |||
| 682 | return; | 669 | return; |
| 683 | 670 | ||
| 684 | fail_irq: | 671 | fail_irq: |
| @@ -691,7 +678,6 @@ static struct platform_device *omap3pandora_devices[] __initdata = { | |||
| 691 | &pandora_leds_gpio, | 678 | &pandora_leds_gpio, |
| 692 | &pandora_keys_gpio, | 679 | &pandora_keys_gpio, |
| 693 | &pandora_dss_device, | 680 | &pandora_dss_device, |
| 694 | &pandora_wl1251_data, | ||
| 695 | &pandora_vwlan_device, | 681 | &pandora_vwlan_device, |
| 696 | }; | 682 | }; |
| 697 | 683 | ||
| @@ -711,8 +697,6 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { | |||
| 711 | static struct omap_board_mux board_mux[] __initdata = { | 697 | static struct omap_board_mux board_mux[] __initdata = { |
| 712 | { .reg_offset = OMAP_MUX_TERMINATOR }, | 698 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
| 713 | }; | 699 | }; |
| 714 | #else | ||
| 715 | #define board_mux NULL | ||
| 716 | #endif | 700 | #endif |
| 717 | 701 | ||
| 718 | static struct omap_musb_board_data musb_board_data = { | 702 | static struct omap_musb_board_data musb_board_data = { |
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index f25272125413..9df9d9367608 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c | |||
| @@ -584,12 +584,12 @@ static void __init omap3_stalker_init_irq(void) | |||
| 584 | { | 584 | { |
| 585 | omap_board_config = omap3_stalker_config; | 585 | omap_board_config = omap3_stalker_config; |
| 586 | omap_board_config_size = ARRAY_SIZE(omap3_stalker_config); | 586 | omap_board_config_size = ARRAY_SIZE(omap3_stalker_config); |
| 587 | omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL); | 587 | omap2_init_common_infrastructure(); |
| 588 | omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL); | ||
| 588 | omap_init_irq(); | 589 | omap_init_irq(); |
| 589 | #ifdef CONFIG_OMAP_32K_TIMER | 590 | #ifdef CONFIG_OMAP_32K_TIMER |
| 590 | omap2_gp_clockevent_set_gptimer(12); | 591 | omap2_gp_clockevent_set_gptimer(12); |
| 591 | #endif | 592 | #endif |
| 592 | omap_gpio_init(); | ||
| 593 | } | 593 | } |
| 594 | 594 | ||
| 595 | static struct platform_device *omap3_stalker_devices[] __initdata = { | 595 | static struct platform_device *omap3_stalker_devices[] __initdata = { |
| @@ -616,8 +616,6 @@ static struct omap_board_mux board_mux[] __initdata = { | |||
| 616 | OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE), | 616 | OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE), |
| 617 | {.reg_offset = OMAP_MUX_TERMINATOR}, | 617 | {.reg_offset = OMAP_MUX_TERMINATOR}, |
| 618 | }; | 618 | }; |
| 619 | #else | ||
| 620 | #define board_mux NULL | ||
| 621 | #endif | 619 | #endif |
| 622 | 620 | ||
| 623 | static struct omap_musb_board_data musb_board_data = { | 621 | static struct omap_musb_board_data musb_board_data = { |
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c index 41104bb8774c..db1f74fe6c4f 100644 --- a/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/arch/arm/mach-omap2/board-omap3touchbook.c | |||
| @@ -413,8 +413,6 @@ static struct omap_board_config_kernel omap3_touchbook_config[] __initdata = { | |||
| 413 | static struct omap_board_mux board_mux[] __initdata = { | 413 | static struct omap_board_mux board_mux[] __initdata = { |
| 414 | { .reg_offset = OMAP_MUX_TERMINATOR }, | 414 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
| 415 | }; | 415 | }; |
| 416 | #else | ||
| 417 | #define board_mux NULL | ||
| 418 | #endif | 416 | #endif |
| 419 | 417 | ||
| 420 | static void __init omap3_touchbook_init_irq(void) | 418 | static void __init omap3_touchbook_init_irq(void) |
| @@ -422,13 +420,13 @@ static void __init omap3_touchbook_init_irq(void) | |||
| 422 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); | 420 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); |
| 423 | omap_board_config = omap3_touchbook_config; | 421 | omap_board_config = omap3_touchbook_config; |
| 424 | omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config); | 422 | omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config); |
| 425 | omap2_init_common_hw(mt46h32m32lf6_sdrc_params, | 423 | omap2_init_common_infrastructure(); |
| 426 | mt46h32m32lf6_sdrc_params); | 424 | omap2_init_common_devices(mt46h32m32lf6_sdrc_params, |
| 425 | mt46h32m32lf6_sdrc_params); | ||
| 427 | omap_init_irq(); | 426 | omap_init_irq(); |
| 428 | #ifdef CONFIG_OMAP_32K_TIMER | 427 | #ifdef CONFIG_OMAP_32K_TIMER |
| 429 | omap2_gp_clockevent_set_gptimer(12); | 428 | omap2_gp_clockevent_set_gptimer(12); |
| 430 | #endif | 429 | #endif |
| 431 | omap_gpio_init(); | ||
| 432 | } | 430 | } |
| 433 | 431 | ||
| 434 | static struct platform_device *omap3_touchbook_devices[] __initdata = { | 432 | static struct platform_device *omap3_touchbook_devices[] __initdata = { |
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index 1ecd0a6cefb7..3094e2007844 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c | |||
| @@ -40,6 +40,7 @@ | |||
| 40 | 40 | ||
| 41 | #include "hsmmc.h" | 41 | #include "hsmmc.h" |
| 42 | #include "control.h" | 42 | #include "control.h" |
| 43 | #include "mux.h" | ||
| 43 | 44 | ||
| 44 | #define GPIO_HUB_POWER 1 | 45 | #define GPIO_HUB_POWER 1 |
| 45 | #define GPIO_HUB_NRESET 62 | 46 | #define GPIO_HUB_NRESET 62 |
| @@ -76,9 +77,9 @@ static struct platform_device *panda_devices[] __initdata = { | |||
| 76 | 77 | ||
| 77 | static void __init omap4_panda_init_irq(void) | 78 | static void __init omap4_panda_init_irq(void) |
| 78 | { | 79 | { |
| 79 | omap2_init_common_hw(NULL, NULL); | 80 | omap2_init_common_infrastructure(); |
| 81 | omap2_init_common_devices(NULL, NULL); | ||
| 80 | gic_init_irq(); | 82 | gic_init_irq(); |
| 81 | omap_gpio_init(); | ||
| 82 | } | 83 | } |
| 83 | 84 | ||
| 84 | static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { | 85 | static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { |
| @@ -133,15 +134,23 @@ error1: | |||
| 133 | 134 | ||
| 134 | static struct omap_musb_board_data musb_board_data = { | 135 | static struct omap_musb_board_data musb_board_data = { |
| 135 | .interface_type = MUSB_INTERFACE_UTMI, | 136 | .interface_type = MUSB_INTERFACE_UTMI, |
| 136 | .mode = MUSB_PERIPHERAL, | 137 | .mode = MUSB_OTG, |
| 137 | .power = 100, | 138 | .power = 100, |
| 138 | }; | 139 | }; |
| 139 | 140 | ||
| 141 | static struct twl4030_usb_data omap4_usbphy_data = { | ||
| 142 | .phy_init = omap4430_phy_init, | ||
| 143 | .phy_exit = omap4430_phy_exit, | ||
| 144 | .phy_power = omap4430_phy_power, | ||
| 145 | .phy_set_clock = omap4430_phy_set_clk, | ||
| 146 | }; | ||
| 147 | |||
| 140 | static struct omap2_hsmmc_info mmc[] = { | 148 | static struct omap2_hsmmc_info mmc[] = { |
| 141 | { | 149 | { |
| 142 | .mmc = 1, | 150 | .mmc = 1, |
| 143 | .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, | 151 | .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, |
| 144 | .gpio_wp = -EINVAL, | 152 | .gpio_wp = -EINVAL, |
| 153 | .gpio_cd = -EINVAL, | ||
| 145 | }, | 154 | }, |
| 146 | {} /* Terminator */ | 155 | {} /* Terminator */ |
| 147 | }; | 156 | }; |
| @@ -345,6 +354,7 @@ static struct twl4030_platform_data omap4_panda_twldata = { | |||
| 345 | .vaux1 = &omap4_panda_vaux1, | 354 | .vaux1 = &omap4_panda_vaux1, |
| 346 | .vaux2 = &omap4_panda_vaux2, | 355 | .vaux2 = &omap4_panda_vaux2, |
| 347 | .vaux3 = &omap4_panda_vaux3, | 356 | .vaux3 = &omap4_panda_vaux3, |
| 357 | .usb = &omap4_usbphy_data, | ||
| 348 | }; | 358 | }; |
| 349 | 359 | ||
| 350 | static struct i2c_board_info __initdata omap4_panda_i2c_boardinfo[] = { | 360 | static struct i2c_board_info __initdata omap4_panda_i2c_boardinfo[] = { |
| @@ -368,8 +378,23 @@ static int __init omap4_panda_i2c_init(void) | |||
| 368 | omap_register_i2c_bus(4, 400, NULL, 0); | 378 | omap_register_i2c_bus(4, 400, NULL, 0); |
| 369 | return 0; | 379 | return 0; |
| 370 | } | 380 | } |
| 381 | |||
| 382 | #ifdef CONFIG_OMAP_MUX | ||
| 383 | static struct omap_board_mux board_mux[] __initdata = { | ||
| 384 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
| 385 | }; | ||
| 386 | #else | ||
| 387 | #define board_mux NULL | ||
| 388 | #endif | ||
| 389 | |||
| 371 | static void __init omap4_panda_init(void) | 390 | static void __init omap4_panda_init(void) |
| 372 | { | 391 | { |
| 392 | int package = OMAP_PACKAGE_CBS; | ||
| 393 | |||
| 394 | if (omap_rev() == OMAP4430_REV_ES1_0) | ||
| 395 | package = OMAP_PACKAGE_CBL; | ||
| 396 | omap4_mux_init(board_mux, package); | ||
| 397 | |||
| 373 | omap4_panda_i2c_init(); | 398 | omap4_panda_i2c_init(); |
| 374 | platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices)); | 399 | platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices)); |
| 375 | omap_serial_init(); | 400 | omap_serial_init(); |
| @@ -377,9 +402,7 @@ static void __init omap4_panda_init(void) | |||
| 377 | /* OMAP4 Panda uses internal transceiver so register nop transceiver */ | 402 | /* OMAP4 Panda uses internal transceiver so register nop transceiver */ |
| 378 | usb_nop_xceiv_register(); | 403 | usb_nop_xceiv_register(); |
| 379 | omap4_ehci_init(); | 404 | omap4_ehci_init(); |
| 380 | /* FIXME: allow multi-omap to boot until musb is updated for omap4 */ | 405 | usb_musb_init(&musb_board_data); |
| 381 | if (!cpu_is_omap44xx()) | ||
| 382 | usb_musb_init(&musb_board_data); | ||
| 383 | } | 406 | } |
| 384 | 407 | ||
| 385 | static void __init omap4_panda_map_io(void) | 408 | static void __init omap4_panda_map_io(void) |
| @@ -391,6 +414,7 @@ static void __init omap4_panda_map_io(void) | |||
| 391 | MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board") | 414 | MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board") |
| 392 | /* Maintainer: David Anders - Texas Instruments Inc */ | 415 | /* Maintainer: David Anders - Texas Instruments Inc */ |
| 393 | .boot_params = 0x80000100, | 416 | .boot_params = 0x80000100, |
| 417 | .reserve = omap_reserve, | ||
| 394 | .map_io = omap4_panda_map_io, | 418 | .map_io = omap4_panda_map_io, |
| 395 | .init_irq = omap4_panda_init_irq, | 419 | .init_irq = omap4_panda_init_irq, |
| 396 | .init_machine = omap4_panda_init, | 420 | .init_machine = omap4_panda_init, |
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 7053bc0b46db..cb26e5d8268d 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c | |||
| @@ -413,10 +413,10 @@ static void __init overo_init_irq(void) | |||
| 413 | { | 413 | { |
| 414 | omap_board_config = overo_config; | 414 | omap_board_config = overo_config; |
| 415 | omap_board_config_size = ARRAY_SIZE(overo_config); | 415 | omap_board_config_size = ARRAY_SIZE(overo_config); |
| 416 | omap2_init_common_hw(mt46h32m32lf6_sdrc_params, | 416 | omap2_init_common_infrastructure(); |
| 417 | mt46h32m32lf6_sdrc_params); | 417 | omap2_init_common_devices(mt46h32m32lf6_sdrc_params, |
| 418 | mt46h32m32lf6_sdrc_params); | ||
| 418 | omap_init_irq(); | 419 | omap_init_irq(); |
| 419 | omap_gpio_init(); | ||
| 420 | } | 420 | } |
| 421 | 421 | ||
| 422 | static struct platform_device *overo_devices[] __initdata = { | 422 | static struct platform_device *overo_devices[] __initdata = { |
| @@ -438,8 +438,6 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { | |||
| 438 | static struct omap_board_mux board_mux[] __initdata = { | 438 | static struct omap_board_mux board_mux[] __initdata = { |
| 439 | { .reg_offset = OMAP_MUX_TERMINATOR }, | 439 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
| 440 | }; | 440 | }; |
| 441 | #else | ||
| 442 | #define board_mux NULL | ||
| 443 | #endif | 441 | #endif |
| 444 | 442 | ||
| 445 | static struct omap_musb_board_data musb_board_data = { | 443 | static struct omap_musb_board_data musb_board_data = { |
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c new file mode 100644 index 000000000000..cb77be7ac44f --- /dev/null +++ b/arch/arm/mach-omap2/board-rm680.c | |||
| @@ -0,0 +1,187 @@ | |||
| 1 | /* | ||
| 2 | * Board support file for Nokia RM-680. | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Nokia | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/io.h> | ||
| 12 | #include <linux/i2c.h> | ||
| 13 | #include <linux/gpio.h> | ||
| 14 | #include <linux/init.h> | ||
| 15 | #include <linux/i2c/twl.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <linux/regulator/fixed.h> | ||
| 18 | #include <linux/regulator/machine.h> | ||
| 19 | #include <linux/regulator/consumer.h> | ||
| 20 | |||
| 21 | #include <asm/mach/arch.h> | ||
| 22 | #include <asm/mach-types.h> | ||
| 23 | |||
| 24 | #include <plat/i2c.h> | ||
| 25 | #include <plat/mmc.h> | ||
| 26 | #include <plat/usb.h> | ||
| 27 | #include <plat/gpmc.h> | ||
| 28 | #include <plat/common.h> | ||
| 29 | #include <plat/onenand.h> | ||
| 30 | |||
| 31 | #include "mux.h" | ||
| 32 | #include "hsmmc.h" | ||
| 33 | #include "sdram-nokia.h" | ||
| 34 | |||
| 35 | static struct regulator_consumer_supply rm680_vemmc_consumers[] = { | ||
| 36 | REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"), | ||
| 37 | }; | ||
| 38 | |||
| 39 | /* Fixed regulator for internal eMMC */ | ||
| 40 | static struct regulator_init_data rm680_vemmc = { | ||
| 41 | .constraints = { | ||
| 42 | .name = "rm680_vemmc", | ||
| 43 | .min_uV = 2900000, | ||
| 44 | .max_uV = 2900000, | ||
| 45 | .apply_uV = 1, | ||
| 46 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 47 | | REGULATOR_MODE_STANDBY, | ||
| 48 | .valid_ops_mask = REGULATOR_CHANGE_STATUS | ||
| 49 | | REGULATOR_CHANGE_MODE, | ||
| 50 | }, | ||
| 51 | .num_consumer_supplies = ARRAY_SIZE(rm680_vemmc_consumers), | ||
| 52 | .consumer_supplies = rm680_vemmc_consumers, | ||
| 53 | }; | ||
| 54 | |||
| 55 | static struct fixed_voltage_config rm680_vemmc_config = { | ||
| 56 | .supply_name = "VEMMC", | ||
| 57 | .microvolts = 2900000, | ||
| 58 | .gpio = 157, | ||
| 59 | .startup_delay = 150, | ||
| 60 | .enable_high = 1, | ||
| 61 | .init_data = &rm680_vemmc, | ||
| 62 | }; | ||
| 63 | |||
| 64 | static struct platform_device rm680_vemmc_device = { | ||
| 65 | .name = "reg-fixed-voltage", | ||
| 66 | .dev = { | ||
| 67 | .platform_data = &rm680_vemmc_config, | ||
| 68 | }, | ||
| 69 | }; | ||
| 70 | |||
| 71 | static struct platform_device *rm680_peripherals_devices[] __initdata = { | ||
| 72 | &rm680_vemmc_device, | ||
| 73 | }; | ||
| 74 | |||
| 75 | /* TWL */ | ||
| 76 | static struct twl4030_gpio_platform_data rm680_gpio_data = { | ||
| 77 | .gpio_base = OMAP_MAX_GPIO_LINES, | ||
| 78 | .irq_base = TWL4030_GPIO_IRQ_BASE, | ||
| 79 | .irq_end = TWL4030_GPIO_IRQ_END, | ||
| 80 | .pullups = BIT(0), | ||
| 81 | .pulldowns = BIT(1) | BIT(2) | BIT(8) | BIT(15), | ||
| 82 | }; | ||
| 83 | |||
| 84 | static struct twl4030_usb_data rm680_usb_data = { | ||
| 85 | .usb_mode = T2_USB_MODE_ULPI, | ||
| 86 | }; | ||
| 87 | |||
| 88 | static struct twl4030_platform_data rm680_twl_data = { | ||
| 89 | .irq_base = TWL4030_IRQ_BASE, | ||
| 90 | .irq_end = TWL4030_IRQ_END, | ||
| 91 | .gpio = &rm680_gpio_data, | ||
| 92 | .usb = &rm680_usb_data, | ||
| 93 | /* add rest of the children here */ | ||
| 94 | }; | ||
| 95 | |||
| 96 | static struct i2c_board_info __initdata rm680_twl_i2c_board_info[] = { | ||
| 97 | { | ||
| 98 | I2C_BOARD_INFO("twl5031", 0x48), | ||
| 99 | .flags = I2C_CLIENT_WAKE, | ||
| 100 | .irq = INT_34XX_SYS_NIRQ, | ||
| 101 | .platform_data = &rm680_twl_data, | ||
| 102 | }, | ||
| 103 | }; | ||
| 104 | |||
| 105 | static void __init rm680_i2c_init(void) | ||
| 106 | { | ||
| 107 | omap_register_i2c_bus(1, 2900, rm680_twl_i2c_board_info, | ||
| 108 | ARRAY_SIZE(rm680_twl_i2c_board_info)); | ||
| 109 | omap_register_i2c_bus(2, 400, NULL, 0); | ||
| 110 | omap_register_i2c_bus(3, 400, NULL, 0); | ||
| 111 | } | ||
| 112 | |||
| 113 | #if defined(CONFIG_MTD_ONENAND_OMAP2) || \ | ||
| 114 | defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) | ||
| 115 | static struct omap_onenand_platform_data board_onenand_data[] = { | ||
| 116 | { | ||
| 117 | .gpio_irq = 65, | ||
| 118 | .flags = ONENAND_SYNC_READWRITE, | ||
| 119 | } | ||
| 120 | }; | ||
| 121 | #endif | ||
| 122 | |||
| 123 | /* eMMC */ | ||
| 124 | static struct omap2_hsmmc_info mmc[] __initdata = { | ||
| 125 | { | ||
| 126 | .name = "internal", | ||
| 127 | .mmc = 2, | ||
| 128 | .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED, | ||
| 129 | .gpio_cd = -EINVAL, | ||
| 130 | .gpio_wp = -EINVAL, | ||
| 131 | }, | ||
| 132 | { /* Terminator */ } | ||
| 133 | }; | ||
| 134 | |||
| 135 | static void __init rm680_peripherals_init(void) | ||
| 136 | { | ||
| 137 | platform_add_devices(rm680_peripherals_devices, | ||
| 138 | ARRAY_SIZE(rm680_peripherals_devices)); | ||
| 139 | rm680_i2c_init(); | ||
| 140 | gpmc_onenand_init(board_onenand_data); | ||
| 141 | omap2_hsmmc_init(mmc); | ||
| 142 | } | ||
| 143 | |||
| 144 | static void __init rm680_init_irq(void) | ||
| 145 | { | ||
| 146 | struct omap_sdrc_params *sdrc_params; | ||
| 147 | |||
| 148 | omap2_init_common_infrastructure(); | ||
| 149 | sdrc_params = nokia_get_sdram_timings(); | ||
| 150 | omap2_init_common_devices(sdrc_params, sdrc_params); | ||
| 151 | omap_init_irq(); | ||
| 152 | } | ||
| 153 | |||
| 154 | #ifdef CONFIG_OMAP_MUX | ||
| 155 | static struct omap_board_mux board_mux[] __initdata = { | ||
| 156 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
| 157 | }; | ||
| 158 | #endif | ||
| 159 | |||
| 160 | static struct omap_musb_board_data rm680_musb_data = { | ||
| 161 | .interface_type = MUSB_INTERFACE_ULPI, | ||
| 162 | .mode = MUSB_PERIPHERAL, | ||
| 163 | .power = 100, | ||
| 164 | }; | ||
| 165 | |||
| 166 | static void __init rm680_init(void) | ||
| 167 | { | ||
| 168 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); | ||
| 169 | omap_serial_init(); | ||
| 170 | usb_musb_init(&rm680_musb_data); | ||
| 171 | rm680_peripherals_init(); | ||
| 172 | } | ||
| 173 | |||
| 174 | static void __init rm680_map_io(void) | ||
| 175 | { | ||
| 176 | omap2_set_globals_3xxx(); | ||
| 177 | omap34xx_map_common_io(); | ||
| 178 | } | ||
| 179 | |||
| 180 | MACHINE_START(NOKIA_RM680, "Nokia RM-680 board") | ||
| 181 | .boot_params = 0x80000100, | ||
| 182 | .map_io = rm680_map_io, | ||
| 183 | .reserve = omap_reserve, | ||
| 184 | .init_irq = rm680_init_irq, | ||
| 185 | .init_machine = rm680_init, | ||
| 186 | .timer = &omap_timer, | ||
| 187 | MACHINE_END | ||
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 3fec4d62a91a..e75e240cad67 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c | |||
| @@ -23,7 +23,6 @@ | |||
| 23 | #include <linux/gpio.h> | 23 | #include <linux/gpio.h> |
| 24 | #include <linux/gpio_keys.h> | 24 | #include <linux/gpio_keys.h> |
| 25 | #include <linux/mmc/host.h> | 25 | #include <linux/mmc/host.h> |
| 26 | #include <sound/tlv320aic3x.h> | ||
| 27 | 26 | ||
| 28 | #include <plat/mcspi.h> | 27 | #include <plat/mcspi.h> |
| 29 | #include <plat/board.h> | 28 | #include <plat/board.h> |
| @@ -293,6 +292,8 @@ static struct omap_board_mux rx51_mmc2_off_mux[] = { | |||
| 293 | { .reg_offset = OMAP_MUX_TERMINATOR }, | 292 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
| 294 | }; | 293 | }; |
| 295 | 294 | ||
| 295 | static struct omap_mux_partition *partition; | ||
| 296 | |||
| 296 | /* | 297 | /* |
| 297 | * Current flows to eMMC when eMMC is off and the data lines are pulled up, | 298 | * Current flows to eMMC when eMMC is off and the data lines are pulled up, |
| 298 | * so pull them down. N.B. we pull 8 lines because we are using 8 lines. | 299 | * so pull them down. N.B. we pull 8 lines because we are using 8 lines. |
| @@ -300,9 +301,9 @@ static struct omap_board_mux rx51_mmc2_off_mux[] = { | |||
| 300 | static void rx51_mmc2_remux(struct device *dev, int slot, int power_on) | 301 | static void rx51_mmc2_remux(struct device *dev, int slot, int power_on) |
| 301 | { | 302 | { |
| 302 | if (power_on) | 303 | if (power_on) |
| 303 | omap_mux_write_array(rx51_mmc2_on_mux); | 304 | omap_mux_write_array(partition, rx51_mmc2_on_mux); |
| 304 | else | 305 | else |
| 305 | omap_mux_write_array(rx51_mmc2_off_mux); | 306 | omap_mux_write_array(partition, rx51_mmc2_off_mux); |
| 306 | } | 307 | } |
| 307 | 308 | ||
| 308 | static struct omap2_hsmmc_info mmc[] __initdata = { | 309 | static struct omap2_hsmmc_info mmc[] __initdata = { |
| @@ -342,6 +343,8 @@ static struct regulator_consumer_supply rx51_vmmc2_supplies[] = { | |||
| 342 | /* tlv320aic3x analog supplies */ | 343 | /* tlv320aic3x analog supplies */ |
| 343 | REGULATOR_SUPPLY("AVDD", "2-0018"), | 344 | REGULATOR_SUPPLY("AVDD", "2-0018"), |
| 344 | REGULATOR_SUPPLY("DRVDD", "2-0018"), | 345 | REGULATOR_SUPPLY("DRVDD", "2-0018"), |
| 346 | REGULATOR_SUPPLY("AVDD", "2-0019"), | ||
| 347 | REGULATOR_SUPPLY("DRVDD", "2-0019"), | ||
| 345 | /* tpa6130a2 */ | 348 | /* tpa6130a2 */ |
| 346 | REGULATOR_SUPPLY("Vdd", "2-0060"), | 349 | REGULATOR_SUPPLY("Vdd", "2-0060"), |
| 347 | /* Keep vmmc as last item. It is not iterated for newer boards */ | 350 | /* Keep vmmc as last item. It is not iterated for newer boards */ |
| @@ -352,19 +355,16 @@ static struct regulator_consumer_supply rx51_vio_supplies[] = { | |||
| 352 | /* tlv320aic3x digital supplies */ | 355 | /* tlv320aic3x digital supplies */ |
| 353 | REGULATOR_SUPPLY("IOVDD", "2-0018"), | 356 | REGULATOR_SUPPLY("IOVDD", "2-0018"), |
| 354 | REGULATOR_SUPPLY("DVDD", "2-0018"), | 357 | REGULATOR_SUPPLY("DVDD", "2-0018"), |
| 358 | REGULATOR_SUPPLY("IOVDD", "2-0019"), | ||
| 359 | REGULATOR_SUPPLY("DVDD", "2-0019"), | ||
| 355 | }; | 360 | }; |
| 356 | 361 | ||
| 357 | #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) | ||
| 358 | extern struct platform_device rx51_display_device; | ||
| 359 | #endif | ||
| 360 | |||
| 361 | static struct regulator_consumer_supply rx51_vaux1_consumers[] = { | 362 | static struct regulator_consumer_supply rx51_vaux1_consumers[] = { |
| 362 | #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) | 363 | REGULATOR_SUPPLY("vdds_sdi", "omapdss"), |
| 363 | { | 364 | }; |
| 364 | .supply = "vdds_sdi", | 365 | |
| 365 | .dev = &rx51_display_device.dev, | 366 | static struct regulator_consumer_supply rx51_vdac_supply[] = { |
| 366 | }, | 367 | REGULATOR_SUPPLY("vdda_dac", "omapdss"), |
| 367 | #endif | ||
| 368 | }; | 368 | }; |
| 369 | 369 | ||
| 370 | static struct regulator_init_data rx51_vaux1 = { | 370 | static struct regulator_init_data rx51_vaux1 = { |
| @@ -484,14 +484,17 @@ static struct regulator_init_data rx51_vsim = { | |||
| 484 | 484 | ||
| 485 | static struct regulator_init_data rx51_vdac = { | 485 | static struct regulator_init_data rx51_vdac = { |
| 486 | .constraints = { | 486 | .constraints = { |
| 487 | .name = "VDAC", | ||
| 487 | .min_uV = 1800000, | 488 | .min_uV = 1800000, |
| 488 | .max_uV = 1800000, | 489 | .max_uV = 1800000, |
| 490 | .apply_uV = true, | ||
| 489 | .valid_modes_mask = REGULATOR_MODE_NORMAL | 491 | .valid_modes_mask = REGULATOR_MODE_NORMAL |
| 490 | | REGULATOR_MODE_STANDBY, | 492 | | REGULATOR_MODE_STANDBY, |
| 491 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | 493 | .valid_ops_mask = REGULATOR_CHANGE_MODE |
| 492 | | REGULATOR_CHANGE_MODE | ||
| 493 | | REGULATOR_CHANGE_STATUS, | 494 | | REGULATOR_CHANGE_STATUS, |
| 494 | }, | 495 | }, |
| 496 | .num_consumer_supplies = 1, | ||
| 497 | .consumer_supplies = rx51_vdac_supply, | ||
| 495 | }; | 498 | }; |
| 496 | 499 | ||
| 497 | static struct regulator_init_data rx51_vio = { | 500 | static struct regulator_init_data rx51_vio = { |
| @@ -717,7 +720,7 @@ static struct twl4030_platform_data rx51_twldata __initdata = { | |||
| 717 | .vio = &rx51_vio, | 720 | .vio = &rx51_vio, |
| 718 | }; | 721 | }; |
| 719 | 722 | ||
| 720 | static struct tpa6130a2_platform_data rx51_tpa6130a2_data __initdata = { | 723 | static struct tpa6130a2_platform_data rx51_tpa6130a2_data __initdata_or_module = { |
| 721 | .id = TPA6130A2, | 724 | .id = TPA6130A2, |
| 722 | .power_gpio = 98, | 725 | .power_gpio = 98, |
| 723 | }; | 726 | }; |
| @@ -742,11 +745,19 @@ static struct aic3x_pdata rx51_aic3x_data = { | |||
| 742 | .gpio_reset = 60, | 745 | .gpio_reset = 60, |
| 743 | }; | 746 | }; |
| 744 | 747 | ||
| 748 | static struct aic3x_pdata rx51_aic3x_data2 = { | ||
| 749 | .gpio_reset = 60, | ||
| 750 | }; | ||
| 751 | |||
| 745 | static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = { | 752 | static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = { |
| 746 | { | 753 | { |
| 747 | I2C_BOARD_INFO("tlv320aic3x", 0x18), | 754 | I2C_BOARD_INFO("tlv320aic3x", 0x18), |
| 748 | .platform_data = &rx51_aic3x_data, | 755 | .platform_data = &rx51_aic3x_data, |
| 749 | }, | 756 | }, |
| 757 | { | ||
| 758 | I2C_BOARD_INFO("tlv320aic3x", 0x19), | ||
| 759 | .platform_data = &rx51_aic3x_data2, | ||
| 760 | }, | ||
| 750 | #if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE) | 761 | #if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE) |
| 751 | { | 762 | { |
| 752 | I2C_BOARD_INFO("tsl2563", 0x29), | 763 | I2C_BOARD_INFO("tsl2563", 0x29), |
| @@ -815,25 +826,15 @@ static struct mtd_partition onenand_partitions[] = { | |||
| 815 | }, | 826 | }, |
| 816 | }; | 827 | }; |
| 817 | 828 | ||
| 818 | static struct omap_onenand_platform_data board_onenand_data = { | 829 | static struct omap_onenand_platform_data board_onenand_data[] = { |
| 819 | .cs = 0, | 830 | { |
| 820 | .gpio_irq = 65, | 831 | .cs = 0, |
| 821 | .parts = onenand_partitions, | 832 | .gpio_irq = 65, |
| 822 | .nr_parts = ARRAY_SIZE(onenand_partitions), | 833 | .parts = onenand_partitions, |
| 823 | .flags = ONENAND_SYNC_READWRITE, | 834 | .nr_parts = ARRAY_SIZE(onenand_partitions), |
| 835 | .flags = ONENAND_SYNC_READWRITE, | ||
| 836 | } | ||
| 824 | }; | 837 | }; |
| 825 | |||
| 826 | static void __init board_onenand_init(void) | ||
| 827 | { | ||
| 828 | gpmc_onenand_init(&board_onenand_data); | ||
| 829 | } | ||
| 830 | |||
| 831 | #else | ||
| 832 | |||
| 833 | static inline void board_onenand_init(void) | ||
| 834 | { | ||
| 835 | } | ||
| 836 | |||
| 837 | #endif | 838 | #endif |
| 838 | 839 | ||
| 839 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | 840 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) |
| @@ -916,13 +917,17 @@ error: | |||
| 916 | void __init rx51_peripherals_init(void) | 917 | void __init rx51_peripherals_init(void) |
| 917 | { | 918 | { |
| 918 | rx51_i2c_init(); | 919 | rx51_i2c_init(); |
| 919 | board_onenand_init(); | 920 | gpmc_onenand_init(board_onenand_data); |
| 920 | board_smc91x_init(); | 921 | board_smc91x_init(); |
| 921 | rx51_add_gpio_keys(); | 922 | rx51_add_gpio_keys(); |
| 922 | rx51_init_wl1251(); | 923 | rx51_init_wl1251(); |
| 923 | spi_register_board_info(rx51_peripherals_spi_board_info, | 924 | spi_register_board_info(rx51_peripherals_spi_board_info, |
| 924 | ARRAY_SIZE(rx51_peripherals_spi_board_info)); | 925 | ARRAY_SIZE(rx51_peripherals_spi_board_info)); |
| 925 | omap2_hsmmc_init(mmc); | 926 | |
| 927 | partition = omap_mux_get("core"); | ||
| 928 | if (partition) | ||
| 929 | omap2_hsmmc_init(mmc); | ||
| 930 | |||
| 926 | platform_device_register(&rx51_charger_device); | 931 | platform_device_register(&rx51_charger_device); |
| 927 | } | 932 | } |
| 928 | 933 | ||
diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c index 85503fed4e13..acd670054d9a 100644 --- a/arch/arm/mach-omap2/board-rx51-video.c +++ b/arch/arm/mach-omap2/board-rx51-video.c | |||
| @@ -14,7 +14,6 @@ | |||
| 14 | #include <linux/gpio.h> | 14 | #include <linux/gpio.h> |
| 15 | #include <linux/spi/spi.h> | 15 | #include <linux/spi/spi.h> |
| 16 | #include <linux/mm.h> | 16 | #include <linux/mm.h> |
| 17 | |||
| 18 | #include <asm/mach-types.h> | 17 | #include <asm/mach-types.h> |
| 19 | #include <plat/display.h> | 18 | #include <plat/display.h> |
| 20 | #include <plat/vram.h> | 19 | #include <plat/vram.h> |
| @@ -49,8 +48,16 @@ static struct omap_dss_device rx51_lcd_device = { | |||
| 49 | .platform_disable = rx51_lcd_disable, | 48 | .platform_disable = rx51_lcd_disable, |
| 50 | }; | 49 | }; |
| 51 | 50 | ||
| 51 | static struct omap_dss_device rx51_tv_device = { | ||
| 52 | .name = "tv", | ||
| 53 | .type = OMAP_DISPLAY_TYPE_VENC, | ||
| 54 | .driver_name = "venc", | ||
| 55 | .phy.venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE, | ||
| 56 | }; | ||
| 57 | |||
| 52 | static struct omap_dss_device *rx51_dss_devices[] = { | 58 | static struct omap_dss_device *rx51_dss_devices[] = { |
| 53 | &rx51_lcd_device, | 59 | &rx51_lcd_device, |
| 60 | &rx51_tv_device, | ||
| 54 | }; | 61 | }; |
| 55 | 62 | ||
| 56 | static struct omap_dss_board_info rx51_dss_board_info = { | 63 | static struct omap_dss_board_info rx51_dss_board_info = { |
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index 36f2cf4efd57..f53fc551c58f 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c | |||
| @@ -32,10 +32,10 @@ | |||
| 32 | 32 | ||
| 33 | #include "mux.h" | 33 | #include "mux.h" |
| 34 | #include "pm.h" | 34 | #include "pm.h" |
| 35 | #include "sdram-nokia.h" | ||
| 35 | 36 | ||
| 36 | #define RX51_GPIO_SLEEP_IND 162 | 37 | #define RX51_GPIO_SLEEP_IND 162 |
| 37 | 38 | ||
| 38 | struct omap_sdrc_params *rx51_get_sdram_timings(void); | ||
| 39 | extern void rx51_video_mem_init(void); | 39 | extern void rx51_video_mem_init(void); |
| 40 | 40 | ||
| 41 | static struct gpio_led gpio_leds[] = { | 41 | static struct gpio_led gpio_leds[] = { |
| @@ -105,10 +105,10 @@ static void __init rx51_init_irq(void) | |||
| 105 | omap_board_config = rx51_config; | 105 | omap_board_config = rx51_config; |
| 106 | omap_board_config_size = ARRAY_SIZE(rx51_config); | 106 | omap_board_config_size = ARRAY_SIZE(rx51_config); |
| 107 | omap3_pm_init_cpuidle(rx51_cpuidle_params); | 107 | omap3_pm_init_cpuidle(rx51_cpuidle_params); |
| 108 | sdrc_params = rx51_get_sdram_timings(); | 108 | omap2_init_common_infrastructure(); |
| 109 | omap2_init_common_hw(sdrc_params, sdrc_params); | 109 | sdrc_params = nokia_get_sdram_timings(); |
| 110 | omap2_init_common_devices(sdrc_params, sdrc_params); | ||
| 110 | omap_init_irq(); | 111 | omap_init_irq(); |
| 111 | omap_gpio_init(); | ||
| 112 | } | 112 | } |
| 113 | 113 | ||
| 114 | extern void __init rx51_peripherals_init(void); | 114 | extern void __init rx51_peripherals_init(void); |
| @@ -117,8 +117,6 @@ extern void __init rx51_peripherals_init(void); | |||
| 117 | static struct omap_board_mux board_mux[] __initdata = { | 117 | static struct omap_board_mux board_mux[] __initdata = { |
| 118 | { .reg_offset = OMAP_MUX_TERMINATOR }, | 118 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
| 119 | }; | 119 | }; |
| 120 | #else | ||
| 121 | #define board_mux NULL | ||
| 122 | #endif | 120 | #endif |
| 123 | 121 | ||
| 124 | static struct omap_musb_board_data musb_board_data = { | 122 | static struct omap_musb_board_data musb_board_data = { |
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index 9db9203667df..3fbd0edd712e 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c | |||
| @@ -196,7 +196,7 @@ struct wl12xx_platform_data omap_zoom_wlan_data __initdata = { | |||
| 196 | .board_ref_clock = 1, | 196 | .board_ref_clock = 1, |
| 197 | }; | 197 | }; |
| 198 | 198 | ||
| 199 | static struct omap2_hsmmc_info mmc[] __initdata = { | 199 | static struct omap2_hsmmc_info mmc[] = { |
| 200 | { | 200 | { |
| 201 | .name = "external", | 201 | .name = "external", |
| 202 | .mmc = 1, | 202 | .mmc = 1, |
diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom.c index 5adde12c0395..e041c537ea37 100644 --- a/arch/arm/mach-omap2/board-zoom3.c +++ b/arch/arm/mach-omap2/board-zoom.c | |||
| @@ -1,6 +1,9 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) 2009 Texas Instruments Inc. | 2 | * Copyright (C) 2009-2010 Texas Instruments Inc. |
| 3 | * Mikkel Christensen <mlc@ti.com> | ||
| 4 | * Felipe Balbi <balbi@ti.com> | ||
| 3 | * | 5 | * |
| 6 | * Modified from mach-omap2/board-ldp.c | ||
| 4 | * | 7 | * |
| 5 | * This program is free software; you can redistribute it and/or modify | 8 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as | 9 | * it under the terms of the GNU General Public License version 2 as |
| @@ -12,22 +15,55 @@ | |||
| 12 | #include <linux/platform_device.h> | 15 | #include <linux/platform_device.h> |
| 13 | #include <linux/input.h> | 16 | #include <linux/input.h> |
| 14 | #include <linux/gpio.h> | 17 | #include <linux/gpio.h> |
| 18 | #include <linux/i2c/twl.h> | ||
| 15 | 19 | ||
| 16 | #include <asm/mach-types.h> | 20 | #include <asm/mach-types.h> |
| 17 | #include <asm/mach/arch.h> | 21 | #include <asm/mach/arch.h> |
| 18 | 22 | ||
| 19 | #include <mach/board-zoom.h> | ||
| 20 | |||
| 21 | #include <plat/common.h> | 23 | #include <plat/common.h> |
| 22 | #include <plat/board.h> | 24 | #include <plat/board.h> |
| 23 | #include <plat/usb.h> | 25 | #include <plat/usb.h> |
| 24 | 26 | ||
| 27 | #include <mach/board-zoom.h> | ||
| 28 | |||
| 25 | #include "board-flash.h" | 29 | #include "board-flash.h" |
| 26 | #include "mux.h" | 30 | #include "mux.h" |
| 31 | #include "sdram-micron-mt46h32m32lf-6.h" | ||
| 27 | #include "sdram-hynix-h8mbx00u0mer-0em.h" | 32 | #include "sdram-hynix-h8mbx00u0mer-0em.h" |
| 28 | 33 | ||
| 29 | static struct omap_board_config_kernel zoom_config[] __initdata = { | 34 | #define ZOOM3_EHCI_RESET_GPIO 64 |
| 35 | |||
| 36 | static void __init omap_zoom_init_irq(void) | ||
| 37 | { | ||
| 38 | omap2_init_common_infrastructure(); | ||
| 39 | if (machine_is_omap_zoom2()) | ||
| 40 | omap2_init_common_devices(mt46h32m32lf6_sdrc_params, | ||
| 41 | mt46h32m32lf6_sdrc_params); | ||
| 42 | else if (machine_is_omap_zoom3()) | ||
| 43 | omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params, | ||
| 44 | h8mbx00u0mer0em_sdrc_params); | ||
| 45 | |||
| 46 | omap_init_irq(); | ||
| 47 | } | ||
| 48 | |||
| 49 | #ifdef CONFIG_OMAP_MUX | ||
| 50 | static struct omap_board_mux board_mux[] __initdata = { | ||
| 51 | /* WLAN IRQ - GPIO 162 */ | ||
| 52 | OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), | ||
| 53 | /* WLAN POWER ENABLE - GPIO 101 */ | ||
| 54 | OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), | ||
| 55 | /* WLAN SDIO: MMC3 CMD */ | ||
| 56 | OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP), | ||
| 57 | /* WLAN SDIO: MMC3 CLK */ | ||
| 58 | OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), | ||
| 59 | /* WLAN SDIO: MMC3 DAT[0-3] */ | ||
| 60 | OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), | ||
| 61 | OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), | ||
| 62 | OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), | ||
| 63 | OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), | ||
| 64 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
| 30 | }; | 65 | }; |
| 66 | #endif | ||
| 31 | 67 | ||
| 32 | static struct mtd_partition zoom_nand_partitions[] = { | 68 | static struct mtd_partition zoom_nand_partitions[] = { |
| 33 | /* All the partition sizes are listed in terms of NAND block size */ | 69 | /* All the partition sizes are listed in terms of NAND block size */ |
| @@ -70,59 +106,41 @@ static struct mtd_partition zoom_nand_partitions[] = { | |||
| 70 | }, | 106 | }, |
| 71 | }; | 107 | }; |
| 72 | 108 | ||
| 73 | static void __init omap_zoom_init_irq(void) | ||
| 74 | { | ||
| 75 | omap_board_config = zoom_config; | ||
| 76 | omap_board_config_size = ARRAY_SIZE(zoom_config); | ||
| 77 | omap2_init_common_hw(h8mbx00u0mer0em_sdrc_params, | ||
| 78 | h8mbx00u0mer0em_sdrc_params); | ||
| 79 | omap_init_irq(); | ||
| 80 | omap_gpio_init(); | ||
| 81 | } | ||
| 82 | |||
| 83 | #ifdef CONFIG_OMAP_MUX | ||
| 84 | static struct omap_board_mux board_mux[] __initdata = { | ||
| 85 | /* WLAN IRQ - GPIO 162 */ | ||
| 86 | OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), | ||
| 87 | /* WLAN POWER ENABLE - GPIO 101 */ | ||
| 88 | OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), | ||
| 89 | /* WLAN SDIO: MMC3 CMD */ | ||
| 90 | OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP), | ||
| 91 | /* WLAN SDIO: MMC3 CLK */ | ||
| 92 | OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), | ||
| 93 | /* WLAN SDIO: MMC3 DAT[0-3] */ | ||
| 94 | OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), | ||
| 95 | OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), | ||
| 96 | OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), | ||
| 97 | OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), | ||
| 98 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
| 99 | }; | ||
| 100 | #else | ||
| 101 | #define board_mux NULL | ||
| 102 | #endif | ||
| 103 | |||
| 104 | static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { | 109 | static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { |
| 105 | .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN, | 110 | .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN, |
| 106 | .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, | 111 | .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, |
| 107 | .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, | 112 | .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, |
| 108 | .phy_reset = true, | 113 | .phy_reset = true, |
| 109 | .reset_gpio_port[0] = -EINVAL, | 114 | .reset_gpio_port[0] = -EINVAL, |
| 110 | .reset_gpio_port[1] = 64, | 115 | .reset_gpio_port[1] = ZOOM3_EHCI_RESET_GPIO, |
| 111 | .reset_gpio_port[2] = -EINVAL, | 116 | .reset_gpio_port[2] = -EINVAL, |
| 112 | }; | 117 | }; |
| 113 | 118 | ||
| 114 | static void __init omap_zoom_init(void) | 119 | static void __init omap_zoom_init(void) |
| 115 | { | 120 | { |
| 116 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); | 121 | if (machine_is_omap_zoom2()) { |
| 117 | zoom_peripherals_init(); | 122 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); |
| 123 | } else if (machine_is_omap_zoom3()) { | ||
| 124 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); | ||
| 125 | omap_mux_init_gpio(ZOOM3_EHCI_RESET_GPIO, OMAP_PIN_OUTPUT); | ||
| 126 | usb_ehci_init(&ehci_pdata); | ||
| 127 | } | ||
| 128 | |||
| 118 | board_nand_init(zoom_nand_partitions, | 129 | board_nand_init(zoom_nand_partitions, |
| 119 | ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS); | 130 | ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS); |
| 120 | zoom_debugboard_init(); | 131 | zoom_debugboard_init(); |
| 121 | 132 | zoom_peripherals_init(); | |
| 122 | omap_mux_init_gpio(64, OMAP_PIN_OUTPUT); | ||
| 123 | usb_ehci_init(&ehci_pdata); | ||
| 124 | } | 133 | } |
| 125 | 134 | ||
| 135 | MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") | ||
| 136 | .boot_params = 0x80000100, | ||
| 137 | .map_io = omap3_map_io, | ||
| 138 | .reserve = omap_reserve, | ||
| 139 | .init_irq = omap_zoom_init_irq, | ||
| 140 | .init_machine = omap_zoom_init, | ||
| 141 | .timer = &omap_timer, | ||
| 142 | MACHINE_END | ||
| 143 | |||
| 126 | MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board") | 144 | MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board") |
| 127 | .boot_params = 0x80000100, | 145 | .boot_params = 0x80000100, |
| 128 | .map_io = omap3_map_io, | 146 | .map_io = omap3_map_io, |
diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c deleted file mode 100644 index 2992a9f3a585..000000000000 --- a/arch/arm/mach-omap2/board-zoom2.c +++ /dev/null | |||
| @@ -1,117 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009 Texas Instruments Inc. | ||
| 3 | * Mikkel Christensen <mlc@ti.com> | ||
| 4 | * | ||
| 5 | * Modified from mach-omap2/board-ldp.c | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/init.h> | ||
| 14 | #include <linux/platform_device.h> | ||
| 15 | #include <linux/input.h> | ||
| 16 | #include <linux/gpio.h> | ||
| 17 | #include <linux/i2c/twl.h> | ||
| 18 | |||
| 19 | #include <asm/mach-types.h> | ||
| 20 | #include <asm/mach/arch.h> | ||
| 21 | |||
| 22 | #include <plat/common.h> | ||
| 23 | #include <plat/board.h> | ||
| 24 | |||
| 25 | #include <mach/board-zoom.h> | ||
| 26 | |||
| 27 | #include "board-flash.h" | ||
| 28 | #include "mux.h" | ||
| 29 | #include "sdram-micron-mt46h32m32lf-6.h" | ||
| 30 | |||
| 31 | static void __init omap_zoom2_init_irq(void) | ||
| 32 | { | ||
| 33 | omap2_init_common_hw(mt46h32m32lf6_sdrc_params, | ||
| 34 | mt46h32m32lf6_sdrc_params); | ||
| 35 | omap_init_irq(); | ||
| 36 | omap_gpio_init(); | ||
| 37 | } | ||
| 38 | |||
| 39 | #ifdef CONFIG_OMAP_MUX | ||
| 40 | static struct omap_board_mux board_mux[] __initdata = { | ||
| 41 | /* WLAN IRQ - GPIO 162 */ | ||
| 42 | OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), | ||
| 43 | /* WLAN POWER ENABLE - GPIO 101 */ | ||
| 44 | OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), | ||
| 45 | /* WLAN SDIO: MMC3 CMD */ | ||
| 46 | OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP), | ||
| 47 | /* WLAN SDIO: MMC3 CLK */ | ||
| 48 | OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), | ||
| 49 | /* WLAN SDIO: MMC3 DAT[0-3] */ | ||
| 50 | OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), | ||
| 51 | OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), | ||
| 52 | OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), | ||
| 53 | OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), | ||
| 54 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
| 55 | }; | ||
| 56 | #else | ||
| 57 | #define board_mux NULL | ||
| 58 | #endif | ||
| 59 | |||
| 60 | static struct mtd_partition zoom_nand_partitions[] = { | ||
| 61 | /* All the partition sizes are listed in terms of NAND block size */ | ||
| 62 | { | ||
| 63 | .name = "X-Loader-NAND", | ||
| 64 | .offset = 0, | ||
| 65 | .size = 4 * (64 * 2048), /* 512KB, 0x80000 */ | ||
| 66 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | ||
| 67 | }, | ||
| 68 | { | ||
| 69 | .name = "U-Boot-NAND", | ||
| 70 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ | ||
| 71 | .size = 10 * (64 * 2048), /* 1.25MB, 0x140000 */ | ||
| 72 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | ||
| 73 | }, | ||
| 74 | { | ||
| 75 | .name = "Boot Env-NAND", | ||
| 76 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */ | ||
| 77 | .size = 2 * (64 * 2048), /* 256KB, 0x40000 */ | ||
| 78 | }, | ||
| 79 | { | ||
| 80 | .name = "Kernel-NAND", | ||
| 81 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x0200000*/ | ||
| 82 | .size = 240 * (64 * 2048), /* 30M, 0x1E00000 */ | ||
| 83 | }, | ||
| 84 | { | ||
| 85 | .name = "system", | ||
| 86 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x2000000 */ | ||
| 87 | .size = 3328 * (64 * 2048), /* 416M, 0x1A000000 */ | ||
| 88 | }, | ||
| 89 | { | ||
| 90 | .name = "userdata", | ||
| 91 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x1C000000*/ | ||
| 92 | .size = 256 * (64 * 2048), /* 32M, 0x2000000 */ | ||
| 93 | }, | ||
| 94 | { | ||
| 95 | .name = "cache", | ||
| 96 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x1E000000*/ | ||
| 97 | .size = 256 * (64 * 2048), /* 32M, 0x2000000 */ | ||
| 98 | }, | ||
| 99 | }; | ||
| 100 | |||
| 101 | static void __init omap_zoom2_init(void) | ||
| 102 | { | ||
| 103 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); | ||
| 104 | zoom_peripherals_init(); | ||
| 105 | board_nand_init(zoom_nand_partitions, | ||
| 106 | ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS); | ||
| 107 | zoom_debugboard_init(); | ||
| 108 | } | ||
| 109 | |||
| 110 | MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") | ||
| 111 | .boot_params = 0x80000100, | ||
| 112 | .map_io = omap3_map_io, | ||
| 113 | .reserve = omap_reserve, | ||
| 114 | .init_irq = omap_zoom2_init_irq, | ||
| 115 | .init_machine = omap_zoom2_init, | ||
| 116 | .timer = &omap_timer, | ||
| 117 | MACHINE_END | ||
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c index 66e01acfd585..f51cffd1fc53 100644 --- a/arch/arm/mach-omap2/clkt2xxx_apll.c +++ b/arch/arm/mach-omap2/clkt2xxx_apll.c | |||
| @@ -26,7 +26,7 @@ | |||
| 26 | 26 | ||
| 27 | #include "clock.h" | 27 | #include "clock.h" |
| 28 | #include "clock2xxx.h" | 28 | #include "clock2xxx.h" |
| 29 | #include "cm.h" | 29 | #include "cm2xxx_3xxx.h" |
| 30 | #include "cm-regbits-24xx.h" | 30 | #include "cm-regbits-24xx.h" |
| 31 | 31 | ||
| 32 | /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */ | 32 | /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */ |
| @@ -49,14 +49,14 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask) | |||
| 49 | 49 | ||
| 50 | apll_mask = EN_APLL_LOCKED << clk->enable_bit; | 50 | apll_mask = EN_APLL_LOCKED << clk->enable_bit; |
| 51 | 51 | ||
| 52 | cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); | 52 | cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); |
| 53 | 53 | ||
| 54 | if ((cval & apll_mask) == apll_mask) | 54 | if ((cval & apll_mask) == apll_mask) |
| 55 | return 0; /* apll already enabled */ | 55 | return 0; /* apll already enabled */ |
| 56 | 56 | ||
| 57 | cval &= ~apll_mask; | 57 | cval &= ~apll_mask; |
| 58 | cval |= apll_mask; | 58 | cval |= apll_mask; |
| 59 | cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); | 59 | omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); |
| 60 | 60 | ||
| 61 | omap2_cm_wait_idlest(cm_idlest_pll, status_mask, | 61 | omap2_cm_wait_idlest(cm_idlest_pll, status_mask, |
| 62 | OMAP24XX_CM_IDLEST_VAL, clk->name); | 62 | OMAP24XX_CM_IDLEST_VAL, clk->name); |
| @@ -83,9 +83,9 @@ static void omap2_clk_apll_disable(struct clk *clk) | |||
| 83 | { | 83 | { |
| 84 | u32 cval; | 84 | u32 cval; |
| 85 | 85 | ||
| 86 | cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); | 86 | cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); |
| 87 | cval &= ~(EN_APLL_LOCKED << clk->enable_bit); | 87 | cval &= ~(EN_APLL_LOCKED << clk->enable_bit); |
| 88 | cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); | 88 | omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); |
| 89 | } | 89 | } |
| 90 | 90 | ||
| 91 | /* Public data */ | 91 | /* Public data */ |
| @@ -106,7 +106,7 @@ u32 omap2xxx_get_apll_clkin(void) | |||
| 106 | { | 106 | { |
| 107 | u32 aplls, srate = 0; | 107 | u32 aplls, srate = 0; |
| 108 | 108 | ||
| 109 | aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); | 109 | aplls = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); |
| 110 | aplls &= OMAP24XX_APLLS_CLKIN_MASK; | 110 | aplls &= OMAP24XX_APLLS_CLKIN_MASK; |
| 111 | aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT; | 111 | aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT; |
| 112 | 112 | ||
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c index 019048434f13..4ae439222085 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c | |||
| @@ -32,7 +32,7 @@ | |||
| 32 | #include "clock.h" | 32 | #include "clock.h" |
| 33 | #include "clock2xxx.h" | 33 | #include "clock2xxx.h" |
| 34 | #include "opp2xxx.h" | 34 | #include "opp2xxx.h" |
| 35 | #include "cm.h" | 35 | #include "cm2xxx_3xxx.h" |
| 36 | #include "cm-regbits-24xx.h" | 36 | #include "cm-regbits-24xx.h" |
| 37 | 37 | ||
| 38 | /* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */ | 38 | /* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */ |
| @@ -54,7 +54,7 @@ unsigned long omap2xxx_clk_get_core_rate(struct clk *clk) | |||
| 54 | 54 | ||
| 55 | core_clk = omap2_get_dpll_rate(clk); | 55 | core_clk = omap2_get_dpll_rate(clk); |
| 56 | 56 | ||
| 57 | v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | 57 | v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
| 58 | v &= OMAP24XX_CORE_CLK_SRC_MASK; | 58 | v &= OMAP24XX_CORE_CLK_SRC_MASK; |
| 59 | 59 | ||
| 60 | if (v == CORE_CLK_SRC_32K) | 60 | if (v == CORE_CLK_SRC_32K) |
| @@ -73,7 +73,7 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate) | |||
| 73 | { | 73 | { |
| 74 | u32 high, low, core_clk_src; | 74 | u32 high, low, core_clk_src; |
| 75 | 75 | ||
| 76 | core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | 76 | core_clk_src = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
| 77 | core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK; | 77 | core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK; |
| 78 | 78 | ||
| 79 | if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ | 79 | if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ |
| @@ -111,7 +111,7 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) | |||
| 111 | const struct dpll_data *dd; | 111 | const struct dpll_data *dd; |
| 112 | 112 | ||
| 113 | cur_rate = omap2xxx_clk_get_core_rate(dclk); | 113 | cur_rate = omap2xxx_clk_get_core_rate(dclk); |
| 114 | mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | 114 | mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
| 115 | mult &= OMAP24XX_CORE_CLK_SRC_MASK; | 115 | mult &= OMAP24XX_CORE_CLK_SRC_MASK; |
| 116 | 116 | ||
| 117 | if ((rate == (cur_rate / 2)) && (mult == 2)) { | 117 | if ((rate == (cur_rate / 2)) && (mult == 2)) { |
| @@ -136,7 +136,7 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) | |||
| 136 | tmpset.cm_clksel1_pll &= ~(dd->mult_mask | | 136 | tmpset.cm_clksel1_pll &= ~(dd->mult_mask | |
| 137 | dd->div1_mask); | 137 | dd->div1_mask); |
| 138 | div = ((curr_prcm_set->xtal_speed / 1000000) - 1); | 138 | div = ((curr_prcm_set->xtal_speed / 1000000) - 1); |
| 139 | tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | 139 | tmpset.cm_clksel2_pll = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
| 140 | tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; | 140 | tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; |
| 141 | if (rate > low) { | 141 | if (rate > low) { |
| 142 | tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; | 142 | tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; |
diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c index 2167be84a5bc..df7b80506483 100644 --- a/arch/arm/mach-omap2/clkt2xxx_osc.c +++ b/arch/arm/mach-omap2/clkt2xxx_osc.c | |||
| @@ -27,7 +27,7 @@ | |||
| 27 | 27 | ||
| 28 | #include "clock.h" | 28 | #include "clock.h" |
| 29 | #include "clock2xxx.h" | 29 | #include "clock2xxx.h" |
| 30 | #include "prm.h" | 30 | #include "prm2xxx_3xxx.h" |
| 31 | #include "prm-regbits-24xx.h" | 31 | #include "prm-regbits-24xx.h" |
| 32 | 32 | ||
| 33 | static int omap2_enable_osc_ck(struct clk *clk) | 33 | static int omap2_enable_osc_ck(struct clk *clk) |
diff --git a/arch/arm/mach-omap2/clkt2xxx_sys.c b/arch/arm/mach-omap2/clkt2xxx_sys.c index 822b5a79f457..8693cfdac49a 100644 --- a/arch/arm/mach-omap2/clkt2xxx_sys.c +++ b/arch/arm/mach-omap2/clkt2xxx_sys.c | |||
| @@ -26,7 +26,7 @@ | |||
| 26 | 26 | ||
| 27 | #include "clock.h" | 27 | #include "clock.h" |
| 28 | #include "clock2xxx.h" | 28 | #include "clock2xxx.h" |
| 29 | #include "prm.h" | 29 | #include "prm2xxx_3xxx.h" |
| 30 | #include "prm-regbits-24xx.h" | 30 | #include "prm-regbits-24xx.h" |
| 31 | 31 | ||
| 32 | void __iomem *prcm_clksrc_ctrl; | 32 | void __iomem *prcm_clksrc_ctrl; |
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index aef62918aaf0..39f9d5a58d0c 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | |||
| @@ -40,7 +40,7 @@ | |||
| 40 | #include "clock.h" | 40 | #include "clock.h" |
| 41 | #include "clock2xxx.h" | 41 | #include "clock2xxx.h" |
| 42 | #include "opp2xxx.h" | 42 | #include "opp2xxx.h" |
| 43 | #include "cm.h" | 43 | #include "cm2xxx_3xxx.h" |
| 44 | #include "cm-regbits-24xx.h" | 44 | #include "cm-regbits-24xx.h" |
| 45 | 45 | ||
| 46 | const struct prcm_config *curr_prcm_set; | 46 | const struct prcm_config *curr_prcm_set; |
| @@ -133,21 +133,21 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate) | |||
| 133 | done_rate = CORE_CLK_SRC_DPLL; | 133 | done_rate = CORE_CLK_SRC_DPLL; |
| 134 | 134 | ||
| 135 | /* MPU divider */ | 135 | /* MPU divider */ |
| 136 | cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL); | 136 | omap2_cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL); |
| 137 | 137 | ||
| 138 | /* dsp + iva1 div(2420), iva2.1(2430) */ | 138 | /* dsp + iva1 div(2420), iva2.1(2430) */ |
| 139 | cm_write_mod_reg(prcm->cm_clksel_dsp, | 139 | omap2_cm_write_mod_reg(prcm->cm_clksel_dsp, |
| 140 | OMAP24XX_DSP_MOD, CM_CLKSEL); | 140 | OMAP24XX_DSP_MOD, CM_CLKSEL); |
| 141 | 141 | ||
| 142 | cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL); | 142 | omap2_cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL); |
| 143 | 143 | ||
| 144 | /* Major subsystem dividers */ | 144 | /* Major subsystem dividers */ |
| 145 | tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; | 145 | tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; |
| 146 | cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, | 146 | omap2_cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, |
| 147 | CM_CLKSEL1); | 147 | CM_CLKSEL1); |
| 148 | 148 | ||
| 149 | if (cpu_is_omap2430()) | 149 | if (cpu_is_omap2430()) |
| 150 | cm_write_mod_reg(prcm->cm_clksel_mdm, | 150 | omap2_cm_write_mod_reg(prcm->cm_clksel_mdm, |
| 151 | OMAP2430_MDM_MOD, CM_CLKSEL); | 151 | OMAP2430_MDM_MOD, CM_CLKSEL); |
| 152 | 152 | ||
| 153 | /* x2 to enter omap2xxx_sdrc_init_params() */ | 153 | /* x2 to enter omap2xxx_sdrc_init_params() */ |
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index 6ce512e902c6..337392c3f549 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c | |||
| @@ -24,7 +24,6 @@ | |||
| 24 | #include <plat/clock.h> | 24 | #include <plat/clock.h> |
| 25 | 25 | ||
| 26 | #include "clock.h" | 26 | #include "clock.h" |
| 27 | #include "cm.h" | ||
| 28 | #include "cm-regbits-24xx.h" | 27 | #include "cm-regbits-24xx.h" |
| 29 | #include "cm-regbits-34xx.h" | 28 | #include "cm-regbits-34xx.h" |
| 30 | 29 | ||
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index b5babf5440e4..2a2f15213add 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c | |||
| @@ -24,14 +24,12 @@ | |||
| 24 | #include <linux/bitops.h> | 24 | #include <linux/bitops.h> |
| 25 | 25 | ||
| 26 | #include <plat/clock.h> | 26 | #include <plat/clock.h> |
| 27 | #include <plat/clockdomain.h> | 27 | #include "clockdomain.h" |
| 28 | #include <plat/cpu.h> | 28 | #include <plat/cpu.h> |
| 29 | #include <plat/prcm.h> | 29 | #include <plat/prcm.h> |
| 30 | 30 | ||
| 31 | #include "clock.h" | 31 | #include "clock.h" |
| 32 | #include "prm.h" | 32 | #include "cm2xxx_3xxx.h" |
| 33 | #include "prm-regbits-24xx.h" | ||
| 34 | #include "cm.h" | ||
| 35 | #include "cm-regbits-24xx.h" | 33 | #include "cm-regbits-24xx.h" |
| 36 | #include "cm-regbits-34xx.h" | 34 | #include "cm-regbits-34xx.h" |
| 37 | 35 | ||
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index a535c7a2a62a..896584e3c4ab 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h | |||
| @@ -49,7 +49,6 @@ | |||
| 49 | 49 | ||
| 50 | /* DPLL Type and DCO Selection Flags */ | 50 | /* DPLL Type and DCO Selection Flags */ |
| 51 | #define DPLL_J_TYPE 0x1 | 51 | #define DPLL_J_TYPE 0x1 |
| 52 | #define DPLL_NO_DCO_SEL 0x2 | ||
| 53 | 52 | ||
| 54 | int omap2_clk_enable(struct clk *clk); | 53 | int omap2_clk_enable(struct clk *clk); |
| 55 | void omap2_clk_disable(struct clk *clk); | 54 | void omap2_clk_disable(struct clk *clk); |
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 21f856252ad8..0a992bc8d0d8 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c | |||
| @@ -22,8 +22,8 @@ | |||
| 22 | #include "clock.h" | 22 | #include "clock.h" |
| 23 | #include "clock2xxx.h" | 23 | #include "clock2xxx.h" |
| 24 | #include "opp2xxx.h" | 24 | #include "opp2xxx.h" |
| 25 | #include "prm.h" | 25 | #include "cm2xxx_3xxx.h" |
| 26 | #include "cm.h" | 26 | #include "prm2xxx_3xxx.h" |
| 27 | #include "prm-regbits-24xx.h" | 27 | #include "prm-regbits-24xx.h" |
| 28 | #include "cm-regbits-24xx.h" | 28 | #include "cm-regbits-24xx.h" |
| 29 | #include "sdrc.h" | 29 | #include "sdrc.h" |
| @@ -812,7 +812,7 @@ static struct clk dss2_fck = { /* Alt clk used in power management */ | |||
| 812 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | 812 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 813 | .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK, | 813 | .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK, |
| 814 | .clksel = dss2_fck_clksel, | 814 | .clksel = dss2_fck_clksel, |
| 815 | .recalc = &followparent_recalc, | 815 | .recalc = &omap2_clksel_recalc, |
| 816 | }; | 816 | }; |
| 817 | 817 | ||
| 818 | static struct clk dss_54m_fck = { /* Alt clk used in power management */ | 818 | static struct clk dss_54m_fck = { /* Alt clk used in power management */ |
| @@ -1862,10 +1862,10 @@ static struct omap_clk omap2420_clks[] = { | |||
| 1862 | CLK(NULL, "eac_fck", &eac_fck, CK_242X), | 1862 | CLK(NULL, "eac_fck", &eac_fck, CK_242X), |
| 1863 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X), | 1863 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X), |
| 1864 | CLK("omap_hdq.1", "fck", &hdq_fck, CK_242X), | 1864 | CLK("omap_hdq.1", "fck", &hdq_fck, CK_242X), |
| 1865 | CLK("i2c_omap.1", "ick", &i2c1_ick, CK_242X), | 1865 | CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X), |
| 1866 | CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X), | 1866 | CLK("omap_i2c.1", "fck", &i2c1_fck, CK_242X), |
| 1867 | CLK("i2c_omap.2", "ick", &i2c2_ick, CK_242X), | 1867 | CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X), |
| 1868 | CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X), | 1868 | CLK("omap_i2c.2", "fck", &i2c2_fck, CK_242X), |
| 1869 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X), | 1869 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X), |
| 1870 | CLK(NULL, "sdma_fck", &sdma_fck, CK_242X), | 1870 | CLK(NULL, "sdma_fck", &sdma_fck, CK_242X), |
| 1871 | CLK(NULL, "sdma_ick", &sdma_ick, CK_242X), | 1871 | CLK(NULL, "sdma_ick", &sdma_ick, CK_242X), |
| @@ -1877,7 +1877,7 @@ static struct omap_clk omap2420_clks[] = { | |||
| 1877 | CLK("omap-aes", "ick", &aes_ick, CK_242X), | 1877 | CLK("omap-aes", "ick", &aes_ick, CK_242X), |
| 1878 | CLK(NULL, "pka_ick", &pka_ick, CK_242X), | 1878 | CLK(NULL, "pka_ick", &pka_ick, CK_242X), |
| 1879 | CLK(NULL, "usb_fck", &usb_fck, CK_242X), | 1879 | CLK(NULL, "usb_fck", &usb_fck, CK_242X), |
| 1880 | CLK("musb_hdrc", "fck", &osc_ck, CK_242X), | 1880 | CLK("musb-hdrc", "fck", &osc_ck, CK_242X), |
| 1881 | }; | 1881 | }; |
| 1882 | 1882 | ||
| 1883 | /* | 1883 | /* |
diff --git a/arch/arm/mach-omap2/clock2430.c b/arch/arm/mach-omap2/clock2430.c index 44d0cccc51a9..d87bc9cb2a36 100644 --- a/arch/arm/mach-omap2/clock2430.c +++ b/arch/arm/mach-omap2/clock2430.c | |||
| @@ -25,7 +25,7 @@ | |||
| 25 | 25 | ||
| 26 | #include "clock.h" | 26 | #include "clock.h" |
| 27 | #include "clock2xxx.h" | 27 | #include "clock2xxx.h" |
| 28 | #include "cm.h" | 28 | #include "cm2xxx_3xxx.h" |
| 29 | #include "cm-regbits-24xx.h" | 29 | #include "cm-regbits-24xx.h" |
| 30 | 30 | ||
| 31 | /** | 31 | /** |
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index e32afcbdfb88..c047dcd007e5 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c | |||
| @@ -22,8 +22,8 @@ | |||
| 22 | #include "clock.h" | 22 | #include "clock.h" |
| 23 | #include "clock2xxx.h" | 23 | #include "clock2xxx.h" |
| 24 | #include "opp2xxx.h" | 24 | #include "opp2xxx.h" |
| 25 | #include "prm.h" | 25 | #include "cm2xxx_3xxx.h" |
| 26 | #include "cm.h" | 26 | #include "prm2xxx_3xxx.h" |
| 27 | #include "prm-regbits-24xx.h" | 27 | #include "prm-regbits-24xx.h" |
| 28 | #include "cm-regbits-24xx.h" | 28 | #include "cm-regbits-24xx.h" |
| 29 | #include "sdrc.h" | 29 | #include "sdrc.h" |
| @@ -800,7 +800,7 @@ static struct clk dss2_fck = { /* Alt clk used in power management */ | |||
| 800 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | 800 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 801 | .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK, | 801 | .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK, |
| 802 | .clksel = dss2_fck_clksel, | 802 | .clksel = dss2_fck_clksel, |
| 803 | .recalc = &followparent_recalc, | 803 | .recalc = &omap2_clksel_recalc, |
| 804 | }; | 804 | }; |
| 805 | 805 | ||
| 806 | static struct clk dss_54m_fck = { /* Alt clk used in power management */ | 806 | static struct clk dss_54m_fck = { /* Alt clk used in power management */ |
| @@ -1969,10 +1969,10 @@ static struct omap_clk omap2430_clks[] = { | |||
| 1969 | CLK(NULL, "fac_fck", &fac_fck, CK_243X), | 1969 | CLK(NULL, "fac_fck", &fac_fck, CK_243X), |
| 1970 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X), | 1970 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X), |
| 1971 | CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X), | 1971 | CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X), |
| 1972 | CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X), | 1972 | CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X), |
| 1973 | CLK("i2c_omap.1", "fck", &i2chs1_fck, CK_243X), | 1973 | CLK("omap_i2c.1", "fck", &i2chs1_fck, CK_243X), |
| 1974 | CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X), | 1974 | CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X), |
| 1975 | CLK("i2c_omap.2", "fck", &i2chs2_fck, CK_243X), | 1975 | CLK("omap_i2c.2", "fck", &i2chs2_fck, CK_243X), |
| 1976 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X), | 1976 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X), |
| 1977 | CLK(NULL, "sdma_fck", &sdma_fck, CK_243X), | 1977 | CLK(NULL, "sdma_fck", &sdma_fck, CK_243X), |
| 1978 | CLK(NULL, "sdma_ick", &sdma_ick, CK_243X), | 1978 | CLK(NULL, "sdma_ick", &sdma_ick, CK_243X), |
| @@ -1983,7 +1983,7 @@ static struct omap_clk omap2430_clks[] = { | |||
| 1983 | CLK("omap-aes", "ick", &aes_ick, CK_243X), | 1983 | CLK("omap-aes", "ick", &aes_ick, CK_243X), |
| 1984 | CLK(NULL, "pka_ick", &pka_ick, CK_243X), | 1984 | CLK(NULL, "pka_ick", &pka_ick, CK_243X), |
| 1985 | CLK(NULL, "usb_fck", &usb_fck, CK_243X), | 1985 | CLK(NULL, "usb_fck", &usb_fck, CK_243X), |
| 1986 | CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X), | 1986 | CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X), |
| 1987 | CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X), | 1987 | CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X), |
| 1988 | CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X), | 1988 | CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X), |
| 1989 | CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X), | 1989 | CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X), |
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 6febd5f11e85..287abc480924 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c | |||
| @@ -25,7 +25,7 @@ | |||
| 25 | 25 | ||
| 26 | #include "clock.h" | 26 | #include "clock.h" |
| 27 | #include "clock34xx.h" | 27 | #include "clock34xx.h" |
| 28 | #include "cm.h" | 28 | #include "cm2xxx_3xxx.h" |
| 29 | #include "cm-regbits-34xx.h" | 29 | #include "cm-regbits-34xx.h" |
| 30 | 30 | ||
| 31 | /** | 31 | /** |
diff --git a/arch/arm/mach-omap2/clock3517.c b/arch/arm/mach-omap2/clock3517.c index b496a9305e1c..74116a3cf099 100644 --- a/arch/arm/mach-omap2/clock3517.c +++ b/arch/arm/mach-omap2/clock3517.c | |||
| @@ -25,7 +25,7 @@ | |||
| 25 | 25 | ||
| 26 | #include "clock.h" | 26 | #include "clock.h" |
| 27 | #include "clock3517.h" | 27 | #include "clock3517.h" |
| 28 | #include "cm.h" | 28 | #include "cm2xxx_3xxx.h" |
| 29 | #include "cm-regbits-34xx.h" | 29 | #include "cm-regbits-34xx.h" |
| 30 | 30 | ||
| 31 | /* | 31 | /* |
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c index a447c4d2c28a..e9f66b6dec18 100644 --- a/arch/arm/mach-omap2/clock3xxx.c +++ b/arch/arm/mach-omap2/clock3xxx.c | |||
| @@ -25,9 +25,9 @@ | |||
| 25 | 25 | ||
| 26 | #include "clock.h" | 26 | #include "clock.h" |
| 27 | #include "clock3xxx.h" | 27 | #include "clock3xxx.h" |
| 28 | #include "prm.h" | 28 | #include "prm2xxx_3xxx.h" |
| 29 | #include "prm-regbits-34xx.h" | 29 | #include "prm-regbits-34xx.h" |
| 30 | #include "cm.h" | 30 | #include "cm2xxx_3xxx.h" |
| 31 | #include "cm-regbits-34xx.h" | 31 | #include "cm-regbits-34xx.h" |
| 32 | 32 | ||
| 33 | /* | 33 | /* |
| @@ -94,7 +94,7 @@ static int __init omap3xxx_clk_arch_init(void) | |||
| 94 | 94 | ||
| 95 | ret = omap2_clk_switch_mpurate_at_boot("dpll1_ck"); | 95 | ret = omap2_clk_switch_mpurate_at_boot("dpll1_ck"); |
| 96 | if (!ret) | 96 | if (!ret) |
| 97 | omap2_clk_print_new_rates("osc_sys_ck", "arm_fck", "core_ck"); | 97 | omap2_clk_print_new_rates("osc_sys_ck", "core_ck", "arm_fck"); |
| 98 | 98 | ||
| 99 | return ret; | 99 | return ret; |
| 100 | } | 100 | } |
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index d85ecd5aebfd..d3ab1c9e50b0 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c | |||
| @@ -28,9 +28,9 @@ | |||
| 28 | #include "clock36xx.h" | 28 | #include "clock36xx.h" |
| 29 | #include "clock3517.h" | 29 | #include "clock3517.h" |
| 30 | 30 | ||
| 31 | #include "cm.h" | 31 | #include "cm2xxx_3xxx.h" |
| 32 | #include "cm-regbits-34xx.h" | 32 | #include "cm-regbits-34xx.h" |
| 33 | #include "prm.h" | 33 | #include "prm2xxx_3xxx.h" |
| 34 | #include "prm-regbits-34xx.h" | 34 | #include "prm-regbits-34xx.h" |
| 35 | #include "control.h" | 35 | #include "control.h" |
| 36 | 36 | ||
| @@ -120,7 +120,7 @@ static const struct clksel_rate osc_sys_13m_rates[] = { | |||
| 120 | }; | 120 | }; |
| 121 | 121 | ||
| 122 | static const struct clksel_rate osc_sys_16_8m_rates[] = { | 122 | static const struct clksel_rate osc_sys_16_8m_rates[] = { |
| 123 | { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS }, | 123 | { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 124 | { .div = 0 } | 124 | { .div = 0 } |
| 125 | }; | 125 | }; |
| 126 | 126 | ||
| @@ -452,35 +452,35 @@ static struct clk dpll3_x2_ck = { | |||
| 452 | static const struct clksel_rate div31_dpll3_rates[] = { | 452 | static const struct clksel_rate div31_dpll3_rates[] = { |
| 453 | { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, | 453 | { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, |
| 454 | { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, | 454 | { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, |
| 455 | { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS }, | 455 | { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 456 | { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS }, | 456 | { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 457 | { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS }, | 457 | { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 458 | { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS }, | 458 | { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 459 | { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS }, | 459 | { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 460 | { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS }, | 460 | { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 461 | { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS }, | 461 | { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 462 | { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS }, | 462 | { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 463 | { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS }, | 463 | { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 464 | { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS }, | 464 | { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 465 | { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS }, | 465 | { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 466 | { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS }, | 466 | { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 467 | { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS }, | 467 | { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 468 | { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS }, | 468 | { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 469 | { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS }, | 469 | { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 470 | { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS }, | 470 | { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 471 | { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS }, | 471 | { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 472 | { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS }, | 472 | { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 473 | { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS }, | 473 | { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 474 | { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS }, | 474 | { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 475 | { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS }, | 475 | { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 476 | { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS }, | 476 | { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 477 | { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS }, | 477 | { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 478 | { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS }, | 478 | { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 479 | { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS }, | 479 | { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 480 | { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS }, | 480 | { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 481 | { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS }, | 481 | { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 482 | { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS }, | 482 | { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 483 | { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS }, | 483 | { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS_36XX }, |
| 484 | { .div = 0 }, | 484 | { .div = 0 }, |
| 485 | }; | 485 | }; |
| 486 | 486 | ||
| @@ -602,6 +602,8 @@ static struct dpll_data dpll4_dd_3630 __initdata = { | |||
| 602 | .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, | 602 | .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, |
| 603 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | 603 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
| 604 | .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK, | 604 | .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
| 605 | .dco_mask = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK, | ||
| 606 | .sddiv_mask = OMAP3630_PERIPH_DPLL_SD_DIV_MASK, | ||
| 605 | .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT, | 607 | .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT, |
| 606 | .min_divider = 1, | 608 | .min_divider = 1, |
| 607 | .max_divider = OMAP3_MAX_DPLL_DIV, | 609 | .max_divider = OMAP3_MAX_DPLL_DIV, |
| @@ -1558,6 +1560,7 @@ static struct clk mcspi4_fck = { | |||
| 1558 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1560 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1559 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, | 1561 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, |
| 1560 | .recalc = &followparent_recalc, | 1562 | .recalc = &followparent_recalc, |
| 1563 | .clkdm_name = "core_l4_clkdm", | ||
| 1561 | }; | 1564 | }; |
| 1562 | 1565 | ||
| 1563 | static struct clk mcspi3_fck = { | 1566 | static struct clk mcspi3_fck = { |
| @@ -1567,6 +1570,7 @@ static struct clk mcspi3_fck = { | |||
| 1567 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1570 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1568 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, | 1571 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, |
| 1569 | .recalc = &followparent_recalc, | 1572 | .recalc = &followparent_recalc, |
| 1573 | .clkdm_name = "core_l4_clkdm", | ||
| 1570 | }; | 1574 | }; |
| 1571 | 1575 | ||
| 1572 | static struct clk mcspi2_fck = { | 1576 | static struct clk mcspi2_fck = { |
| @@ -1576,6 +1580,7 @@ static struct clk mcspi2_fck = { | |||
| 1576 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1580 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1577 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, | 1581 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, |
| 1578 | .recalc = &followparent_recalc, | 1582 | .recalc = &followparent_recalc, |
| 1583 | .clkdm_name = "core_l4_clkdm", | ||
| 1579 | }; | 1584 | }; |
| 1580 | 1585 | ||
| 1581 | static struct clk mcspi1_fck = { | 1586 | static struct clk mcspi1_fck = { |
| @@ -1585,6 +1590,7 @@ static struct clk mcspi1_fck = { | |||
| 1585 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1590 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1586 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, | 1591 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, |
| 1587 | .recalc = &followparent_recalc, | 1592 | .recalc = &followparent_recalc, |
| 1593 | .clkdm_name = "core_l4_clkdm", | ||
| 1588 | }; | 1594 | }; |
| 1589 | 1595 | ||
| 1590 | static struct clk uart2_fck = { | 1596 | static struct clk uart2_fck = { |
| @@ -3044,6 +3050,7 @@ static struct clk sr1_fck = { | |||
| 3044 | .parent = &sys_ck, | 3050 | .parent = &sys_ck, |
| 3045 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | 3051 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 3046 | .enable_bit = OMAP3430_EN_SR1_SHIFT, | 3052 | .enable_bit = OMAP3430_EN_SR1_SHIFT, |
| 3053 | .clkdm_name = "wkup_clkdm", | ||
| 3047 | .recalc = &followparent_recalc, | 3054 | .recalc = &followparent_recalc, |
| 3048 | }; | 3055 | }; |
| 3049 | 3056 | ||
| @@ -3054,6 +3061,7 @@ static struct clk sr2_fck = { | |||
| 3054 | .parent = &sys_ck, | 3061 | .parent = &sys_ck, |
| 3055 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | 3062 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 3056 | .enable_bit = OMAP3430_EN_SR2_SHIFT, | 3063 | .enable_bit = OMAP3430_EN_SR2_SHIFT, |
| 3064 | .clkdm_name = "wkup_clkdm", | ||
| 3057 | .recalc = &followparent_recalc, | 3065 | .recalc = &followparent_recalc, |
| 3058 | }; | 3066 | }; |
| 3059 | 3067 | ||
| @@ -3201,7 +3209,7 @@ static struct omap_clk omap3xxx_clks[] = { | |||
| 3201 | CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX), | 3209 | CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX), |
| 3202 | CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX), | 3210 | CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX), |
| 3203 | CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX), | 3211 | CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX), |
| 3204 | CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2 | CK_AM35XX), | 3212 | CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
| 3205 | CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX), | 3213 | CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX), |
| 3206 | CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_3XXX), | 3214 | CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_3XXX), |
| 3207 | CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX), | 3215 | CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX), |
| @@ -3218,8 +3226,8 @@ static struct omap_clk omap3xxx_clks[] = { | |||
| 3218 | CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX), | 3226 | CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX), |
| 3219 | CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX), | 3227 | CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX), |
| 3220 | CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX), | 3228 | CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX), |
| 3221 | CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X), | 3229 | CLK(NULL, "dpll2_ck", &dpll2_ck, CK_34XX | CK_36XX), |
| 3222 | CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X), | 3230 | CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_34XX | CK_36XX), |
| 3223 | CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX), | 3231 | CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX), |
| 3224 | CLK(NULL, "core_ck", &core_ck, CK_3XXX), | 3232 | CLK(NULL, "core_ck", &core_ck, CK_3XXX), |
| 3225 | CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX), | 3233 | CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX), |
| @@ -3248,8 +3256,8 @@ static struct omap_clk omap3xxx_clks[] = { | |||
| 3248 | CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX), | 3256 | CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX), |
| 3249 | CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX), | 3257 | CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX), |
| 3250 | CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX), | 3258 | CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX), |
| 3251 | CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2 | CK_AM35XX), | 3259 | CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
| 3252 | CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2 | CK_AM35XX), | 3260 | CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
| 3253 | CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX), | 3261 | CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX), |
| 3254 | CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX), | 3262 | CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX), |
| 3255 | CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX), | 3263 | CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX), |
| @@ -3257,8 +3265,8 @@ static struct omap_clk omap3xxx_clks[] = { | |||
| 3257 | CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX), | 3265 | CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX), |
| 3258 | CLK(NULL, "arm_fck", &arm_fck, CK_3XXX), | 3266 | CLK(NULL, "arm_fck", &arm_fck, CK_3XXX), |
| 3259 | CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX), | 3267 | CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX), |
| 3260 | CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X), | 3268 | CLK(NULL, "dpll2_fck", &dpll2_fck, CK_34XX | CK_36XX), |
| 3261 | CLK(NULL, "iva2_ck", &iva2_ck, CK_343X), | 3269 | CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX), |
| 3262 | CLK(NULL, "l3_ick", &l3_ick, CK_3XXX), | 3270 | CLK(NULL, "l3_ick", &l3_ick, CK_3XXX), |
| 3263 | CLK(NULL, "l4_ick", &l4_ick, CK_3XXX), | 3271 | CLK(NULL, "l4_ick", &l4_ick, CK_3XXX), |
| 3264 | CLK(NULL, "rm_ick", &rm_ick, CK_3XXX), | 3272 | CLK(NULL, "rm_ick", &rm_ick, CK_3XXX), |
| @@ -3267,27 +3275,28 @@ static struct omap_clk omap3xxx_clks[] = { | |||
| 3267 | CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), | 3275 | CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), |
| 3268 | CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), | 3276 | CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), |
| 3269 | CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), | 3277 | CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), |
| 3270 | CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2 | CK_3517), | 3278 | CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_3517 | CK_36XX), |
| 3271 | CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2 | CK_3517), | 3279 | CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_3517 | CK_36XX), |
| 3272 | CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), | 3280 | CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), |
| 3273 | CLK(NULL, "modem_fck", &modem_fck, CK_343X), | 3281 | CLK(NULL, "modem_fck", &modem_fck, CK_34XX | CK_36XX), |
| 3274 | CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X), | 3282 | CLK(NULL, "sad2d_ick", &sad2d_ick, CK_34XX | CK_36XX), |
| 3275 | CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X), | 3283 | CLK(NULL, "mad2d_ick", &mad2d_ick, CK_34XX | CK_36XX), |
| 3276 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX), | 3284 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX), |
| 3277 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX), | 3285 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX), |
| 3278 | CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2 | CK_AM35XX), | 3286 | CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
| 3279 | CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2 | CK_AM35XX), | 3287 | CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
| 3280 | CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2 | CK_AM35XX), | 3288 | CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
| 3289 | CLK("ehci-omap.0", "usbtll_fck", &usbtll_fck, CK_3430ES2 | CK_AM35XX), | ||
| 3281 | CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX), | 3290 | CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX), |
| 3282 | CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX), | 3291 | CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX), |
| 3283 | CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), | 3292 | CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), |
| 3284 | CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2 | CK_AM35XX), | 3293 | CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
| 3285 | CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX), | 3294 | CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX), |
| 3286 | CLK(NULL, "mspro_fck", &mspro_fck, CK_343X), | 3295 | CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX), |
| 3287 | CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_3XXX), | 3296 | CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_3XXX), |
| 3288 | CLK("i2c_omap.3", "fck", &i2c3_fck, CK_3XXX), | 3297 | CLK("omap_i2c.3", "fck", &i2c3_fck, CK_3XXX), |
| 3289 | CLK("i2c_omap.2", "fck", &i2c2_fck, CK_3XXX), | 3298 | CLK("omap_i2c.2", "fck", &i2c2_fck, CK_3XXX), |
| 3290 | CLK("i2c_omap.1", "fck", &i2c1_fck, CK_3XXX), | 3299 | CLK("omap_i2c.1", "fck", &i2c1_fck, CK_3XXX), |
| 3291 | CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_3XXX), | 3300 | CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_3XXX), |
| 3292 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_3XXX), | 3301 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_3XXX), |
| 3293 | CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX), | 3302 | CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX), |
| @@ -3301,34 +3310,35 @@ static struct omap_clk omap3xxx_clks[] = { | |||
| 3301 | CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX), | 3310 | CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX), |
| 3302 | CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX), | 3311 | CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX), |
| 3303 | CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1), | 3312 | CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1), |
| 3304 | CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2), | 3313 | CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX), |
| 3305 | CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1), | 3314 | CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1), |
| 3306 | CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2), | 3315 | CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2PLUS | CK_36XX), |
| 3307 | CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX), | 3316 | CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX), |
| 3308 | CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1), | 3317 | CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1, CK_3430ES1), |
| 3309 | CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2), | 3318 | CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX), |
| 3310 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX), | 3319 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX), |
| 3311 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX), | 3320 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX), |
| 3312 | CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X), | 3321 | CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX), |
| 3313 | CLK(NULL, "pka_ick", &pka_ick, CK_343X), | 3322 | CLK(NULL, "pka_ick", &pka_ick, CK_34XX | CK_36XX), |
| 3314 | CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX), | 3323 | CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX), |
| 3315 | CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2 | CK_AM35XX), | 3324 | CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
| 3316 | CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2 | CK_AM35XX), | 3325 | CLK("ehci-omap.0", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
| 3317 | CLK(NULL, "icr_ick", &icr_ick, CK_343X), | 3326 | CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
| 3318 | CLK("omap-aes", "ick", &aes2_ick, CK_343X), | 3327 | CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX), |
| 3319 | CLK("omap-sham", "ick", &sha12_ick, CK_343X), | 3328 | CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX), |
| 3320 | CLK(NULL, "des2_ick", &des2_ick, CK_343X), | 3329 | CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX), |
| 3330 | CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX), | ||
| 3321 | CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX), | 3331 | CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX), |
| 3322 | CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_3XXX), | 3332 | CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_3XXX), |
| 3323 | CLK(NULL, "mspro_ick", &mspro_ick, CK_343X), | 3333 | CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX), |
| 3324 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX), | 3334 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX), |
| 3325 | CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX), | 3335 | CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX), |
| 3326 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX), | 3336 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX), |
| 3327 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX), | 3337 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX), |
| 3328 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX), | 3338 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX), |
| 3329 | CLK("i2c_omap.3", "ick", &i2c3_ick, CK_3XXX), | 3339 | CLK("omap_i2c.3", "ick", &i2c3_ick, CK_3XXX), |
| 3330 | CLK("i2c_omap.2", "ick", &i2c2_ick, CK_3XXX), | 3340 | CLK("omap_i2c.2", "ick", &i2c2_ick, CK_3XXX), |
| 3331 | CLK("i2c_omap.1", "ick", &i2c1_ick, CK_3XXX), | 3341 | CLK("omap_i2c.1", "ick", &i2c1_ick, CK_3XXX), |
| 3332 | CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX), | 3342 | CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX), |
| 3333 | CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX), | 3343 | CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX), |
| 3334 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX), | 3344 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX), |
| @@ -3336,37 +3346,40 @@ static struct omap_clk omap3xxx_clks[] = { | |||
| 3336 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX), | 3346 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX), |
| 3337 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX), | 3347 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX), |
| 3338 | CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1), | 3348 | CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1), |
| 3339 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X), | 3349 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX), |
| 3340 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX), | 3350 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX), |
| 3341 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X), | 3351 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_34XX | CK_36XX), |
| 3342 | CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1), | 3352 | CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1), |
| 3343 | CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2), | 3353 | CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2PLUS | CK_36XX), |
| 3344 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1), | 3354 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1), |
| 3345 | CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X), | 3355 | CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX), |
| 3346 | CLK(NULL, "aes1_ick", &aes1_ick, CK_343X), | 3356 | CLK(NULL, "aes1_ick", &aes1_ick, CK_34XX | CK_36XX), |
| 3347 | CLK("omap_rng", "ick", &rng_ick, CK_343X), | 3357 | CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX), |
| 3348 | CLK(NULL, "sha11_ick", &sha11_ick, CK_343X), | 3358 | CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX), |
| 3349 | CLK(NULL, "des1_ick", &des1_ick, CK_343X), | 3359 | CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX), |
| 3350 | CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), | 3360 | CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), |
| 3351 | CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2 | CK_AM35XX), | 3361 | CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
| 3352 | CLK("omapdss", "tv_fck", &dss_tv_fck, CK_3XXX), | 3362 | CLK("omapdss", "tv_fck", &dss_tv_fck, CK_3XXX), |
| 3353 | CLK("omapdss", "video_fck", &dss_96m_fck, CK_3XXX), | 3363 | CLK("omapdss", "video_fck", &dss_96m_fck, CK_3XXX), |
| 3354 | CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_3XXX), | 3364 | CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_3XXX), |
| 3355 | CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1), | 3365 | CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1), |
| 3356 | CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2 | CK_AM35XX), | 3366 | CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
| 3357 | CLK(NULL, "cam_mclk", &cam_mclk, CK_343X), | 3367 | CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX), |
| 3358 | CLK(NULL, "cam_ick", &cam_ick, CK_343X), | 3368 | CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX), |
| 3359 | CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X), | 3369 | CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX), |
| 3360 | CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2 | CK_AM35XX), | 3370 | CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
| 3361 | CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2 | CK_AM35XX), | 3371 | CLK("ehci-omap.0", "hs_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
| 3362 | CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2 | CK_AM35XX), | 3372 | CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
| 3363 | CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2), | 3373 | CLK("ehci-omap.0", "fs_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
| 3374 | CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | ||
| 3375 | CLK("ehci-omap.0", "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | ||
| 3376 | CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX), | ||
| 3364 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX), | 3377 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX), |
| 3365 | CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX), | 3378 | CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX), |
| 3366 | CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX), | 3379 | CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX), |
| 3367 | CLK("omap_wdt", "fck", &wdt2_fck, CK_3XXX), | 3380 | CLK("omap_wdt", "fck", &wdt2_fck, CK_3XXX), |
| 3368 | CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X), | 3381 | CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX), |
| 3369 | CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2), | 3382 | CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX), |
| 3370 | CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX), | 3383 | CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX), |
| 3371 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX), | 3384 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX), |
| 3372 | CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX), | 3385 | CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX), |
| @@ -3424,9 +3437,9 @@ static struct omap_clk omap3xxx_clks[] = { | |||
| 3424 | CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX), | 3437 | CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX), |
| 3425 | CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX), | 3438 | CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX), |
| 3426 | CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX), | 3439 | CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX), |
| 3427 | CLK(NULL, "sr1_fck", &sr1_fck, CK_343X), | 3440 | CLK(NULL, "sr1_fck", &sr1_fck, CK_34XX | CK_36XX), |
| 3428 | CLK(NULL, "sr2_fck", &sr2_fck, CK_343X), | 3441 | CLK(NULL, "sr2_fck", &sr2_fck, CK_34XX | CK_36XX), |
| 3429 | CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X), | 3442 | CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_34XX | CK_36XX), |
| 3430 | CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX), | 3443 | CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX), |
| 3431 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX), | 3444 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX), |
| 3432 | CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX), | 3445 | CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX), |
| @@ -3437,8 +3450,8 @@ static struct omap_clk omap3xxx_clks[] = { | |||
| 3437 | CLK("davinci_emac", "phy_clk", &emac_fck, CK_AM35XX), | 3450 | CLK("davinci_emac", "phy_clk", &emac_fck, CK_AM35XX), |
| 3438 | CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX), | 3451 | CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX), |
| 3439 | CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX), | 3452 | CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX), |
| 3440 | CLK("musb_hdrc", "ick", &hsotgusb_ick_am35xx, CK_AM35XX), | 3453 | CLK("musb-am35x", "ick", &hsotgusb_ick_am35xx, CK_AM35XX), |
| 3441 | CLK("musb_hdrc", "fck", &hsotgusb_fck_am35xx, CK_AM35XX), | 3454 | CLK("musb-am35x", "fck", &hsotgusb_fck_am35xx, CK_AM35XX), |
| 3442 | CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX), | 3455 | CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX), |
| 3443 | CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX), | 3456 | CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX), |
| 3444 | }; | 3457 | }; |
| @@ -3447,38 +3460,37 @@ static struct omap_clk omap3xxx_clks[] = { | |||
| 3447 | int __init omap3xxx_clk_init(void) | 3460 | int __init omap3xxx_clk_init(void) |
| 3448 | { | 3461 | { |
| 3449 | struct omap_clk *c; | 3462 | struct omap_clk *c; |
| 3450 | u32 cpu_clkflg = CK_3XXX; | 3463 | u32 cpu_clkflg = 0; |
| 3451 | 3464 | ||
| 3452 | if (cpu_is_omap3517()) { | 3465 | if (cpu_is_omap3517()) { |
| 3453 | cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS; | 3466 | cpu_mask = RATE_IN_34XX; |
| 3454 | cpu_clkflg |= CK_3517; | 3467 | cpu_clkflg = CK_3517; |
| 3455 | } else if (cpu_is_omap3505()) { | 3468 | } else if (cpu_is_omap3505()) { |
| 3456 | cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS; | 3469 | cpu_mask = RATE_IN_34XX; |
| 3457 | cpu_clkflg |= CK_3505; | 3470 | cpu_clkflg = CK_3505; |
| 3471 | } else if (cpu_is_omap3630()) { | ||
| 3472 | cpu_mask = (RATE_IN_34XX | RATE_IN_36XX); | ||
| 3473 | cpu_clkflg = CK_36XX; | ||
| 3458 | } else if (cpu_is_omap34xx()) { | 3474 | } else if (cpu_is_omap34xx()) { |
| 3459 | cpu_mask = RATE_IN_3XXX; | ||
| 3460 | cpu_clkflg |= CK_343X; | ||
| 3461 | |||
| 3462 | /* | ||
| 3463 | * Update this if there are further clock changes between ES2 | ||
| 3464 | * and production parts | ||
| 3465 | */ | ||
| 3466 | if (omap_rev() == OMAP3430_REV_ES1_0) { | 3475 | if (omap_rev() == OMAP3430_REV_ES1_0) { |
| 3467 | /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */ | 3476 | cpu_mask = RATE_IN_3430ES1; |
| 3468 | cpu_clkflg |= CK_3430ES1; | 3477 | cpu_clkflg = CK_3430ES1; |
| 3469 | } else { | 3478 | } else { |
| 3470 | cpu_mask |= RATE_IN_3430ES2PLUS; | 3479 | /* |
| 3471 | cpu_clkflg |= CK_3430ES2; | 3480 | * Assume that anything that we haven't matched yet |
| 3481 | * has 3430ES2-type clocks. | ||
| 3482 | */ | ||
| 3483 | cpu_mask = RATE_IN_3430ES2PLUS; | ||
| 3484 | cpu_clkflg = CK_3430ES2PLUS; | ||
| 3472 | } | 3485 | } |
| 3486 | } else { | ||
| 3487 | WARN(1, "clock: could not identify OMAP3 variant\n"); | ||
| 3473 | } | 3488 | } |
| 3474 | 3489 | ||
| 3475 | if (omap3_has_192mhz_clk()) | 3490 | if (omap3_has_192mhz_clk()) |
| 3476 | omap_96m_alwon_fck = omap_96m_alwon_fck_3630; | 3491 | omap_96m_alwon_fck = omap_96m_alwon_fck_3630; |
| 3477 | 3492 | ||
| 3478 | if (cpu_is_omap3630()) { | 3493 | if (cpu_is_omap3630()) { |
| 3479 | cpu_mask |= RATE_IN_36XX; | ||
| 3480 | cpu_clkflg |= CK_36XX; | ||
| 3481 | |||
| 3482 | /* | 3494 | /* |
| 3483 | * XXX This type of dynamic rewriting of the clock tree is | 3495 | * XXX This type of dynamic rewriting of the clock tree is |
| 3484 | * deprecated and should be revised soon. | 3496 | * deprecated and should be revised soon. |
| @@ -3525,10 +3537,9 @@ int __init omap3xxx_clk_init(void) | |||
| 3525 | 3537 | ||
| 3526 | recalculate_root_clocks(); | 3538 | recalculate_root_clocks(); |
| 3527 | 3539 | ||
| 3528 | printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): " | 3540 | pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", |
| 3529 | "%ld.%01ld/%ld/%ld MHz\n", | 3541 | (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10, |
| 3530 | (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10, | 3542 | (core_ck.rate / 1000000), (arm_fck.rate / 1000000)); |
| 3531 | (core_ck.rate / 1000000), (arm_fck.rate / 1000000)); | ||
| 3532 | 3543 | ||
| 3533 | /* | 3544 | /* |
| 3534 | * Only enable those clocks we will need, let the drivers | 3545 | * Only enable those clocks we will need, let the drivers |
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 1599836ba3d9..e8cb32fd7f13 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c | |||
| @@ -30,11 +30,18 @@ | |||
| 30 | 30 | ||
| 31 | #include "clock.h" | 31 | #include "clock.h" |
| 32 | #include "clock44xx.h" | 32 | #include "clock44xx.h" |
| 33 | #include "cm.h" | 33 | #include "cm1_44xx.h" |
| 34 | #include "cm2_44xx.h" | ||
| 34 | #include "cm-regbits-44xx.h" | 35 | #include "cm-regbits-44xx.h" |
| 35 | #include "prm.h" | 36 | #include "prm44xx.h" |
| 37 | #include "prm44xx.h" | ||
| 36 | #include "prm-regbits-44xx.h" | 38 | #include "prm-regbits-44xx.h" |
| 37 | #include "control.h" | 39 | #include "control.h" |
| 40 | #include "scrm44xx.h" | ||
| 41 | |||
| 42 | /* OMAP4 modulemode control */ | ||
| 43 | #define OMAP4430_MODULEMODE_HWCTRL 0 | ||
| 44 | #define OMAP4430_MODULEMODE_SWCTRL 1 | ||
| 38 | 45 | ||
| 39 | /* Root clocks */ | 46 | /* Root clocks */ |
| 40 | 47 | ||
| @@ -47,7 +54,9 @@ static struct clk extalt_clkin_ck = { | |||
| 47 | static struct clk pad_clks_ck = { | 54 | static struct clk pad_clks_ck = { |
| 48 | .name = "pad_clks_ck", | 55 | .name = "pad_clks_ck", |
| 49 | .rate = 12000000, | 56 | .rate = 12000000, |
| 50 | .ops = &clkops_null, | 57 | .ops = &clkops_omap2_dflt, |
| 58 | .enable_reg = OMAP4430_CM_CLKSEL_ABE, | ||
| 59 | .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT, | ||
| 51 | }; | 60 | }; |
| 52 | 61 | ||
| 53 | static struct clk pad_slimbus_core_clks_ck = { | 62 | static struct clk pad_slimbus_core_clks_ck = { |
| @@ -65,7 +74,9 @@ static struct clk secure_32k_clk_src_ck = { | |||
| 65 | static struct clk slimbus_clk = { | 74 | static struct clk slimbus_clk = { |
| 66 | .name = "slimbus_clk", | 75 | .name = "slimbus_clk", |
| 67 | .rate = 12000000, | 76 | .rate = 12000000, |
| 68 | .ops = &clkops_null, | 77 | .ops = &clkops_omap2_dflt, |
| 78 | .enable_reg = OMAP4430_CM_CLKSEL_ABE, | ||
| 79 | .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT, | ||
| 69 | }; | 80 | }; |
| 70 | 81 | ||
| 71 | static struct clk sys_32k_ck = { | 82 | static struct clk sys_32k_ck = { |
| @@ -265,18 +276,71 @@ static struct clk dpll_abe_ck = { | |||
| 265 | .set_rate = &omap3_noncore_dpll_set_rate, | 276 | .set_rate = &omap3_noncore_dpll_set_rate, |
| 266 | }; | 277 | }; |
| 267 | 278 | ||
| 279 | static struct clk dpll_abe_x2_ck = { | ||
| 280 | .name = "dpll_abe_x2_ck", | ||
| 281 | .parent = &dpll_abe_ck, | ||
| 282 | .ops = &clkops_null, | ||
| 283 | .recalc = &omap3_clkoutx2_recalc, | ||
| 284 | }; | ||
| 285 | |||
| 286 | static const struct clksel_rate div31_1to31_rates[] = { | ||
| 287 | { .div = 1, .val = 1, .flags = RATE_IN_4430 }, | ||
| 288 | { .div = 2, .val = 2, .flags = RATE_IN_4430 }, | ||
| 289 | { .div = 3, .val = 3, .flags = RATE_IN_4430 }, | ||
| 290 | { .div = 4, .val = 4, .flags = RATE_IN_4430 }, | ||
| 291 | { .div = 5, .val = 5, .flags = RATE_IN_4430 }, | ||
| 292 | { .div = 6, .val = 6, .flags = RATE_IN_4430 }, | ||
| 293 | { .div = 7, .val = 7, .flags = RATE_IN_4430 }, | ||
| 294 | { .div = 8, .val = 8, .flags = RATE_IN_4430 }, | ||
| 295 | { .div = 9, .val = 9, .flags = RATE_IN_4430 }, | ||
| 296 | { .div = 10, .val = 10, .flags = RATE_IN_4430 }, | ||
| 297 | { .div = 11, .val = 11, .flags = RATE_IN_4430 }, | ||
| 298 | { .div = 12, .val = 12, .flags = RATE_IN_4430 }, | ||
| 299 | { .div = 13, .val = 13, .flags = RATE_IN_4430 }, | ||
| 300 | { .div = 14, .val = 14, .flags = RATE_IN_4430 }, | ||
| 301 | { .div = 15, .val = 15, .flags = RATE_IN_4430 }, | ||
| 302 | { .div = 16, .val = 16, .flags = RATE_IN_4430 }, | ||
| 303 | { .div = 17, .val = 17, .flags = RATE_IN_4430 }, | ||
| 304 | { .div = 18, .val = 18, .flags = RATE_IN_4430 }, | ||
| 305 | { .div = 19, .val = 19, .flags = RATE_IN_4430 }, | ||
| 306 | { .div = 20, .val = 20, .flags = RATE_IN_4430 }, | ||
| 307 | { .div = 21, .val = 21, .flags = RATE_IN_4430 }, | ||
| 308 | { .div = 22, .val = 22, .flags = RATE_IN_4430 }, | ||
| 309 | { .div = 23, .val = 23, .flags = RATE_IN_4430 }, | ||
| 310 | { .div = 24, .val = 24, .flags = RATE_IN_4430 }, | ||
| 311 | { .div = 25, .val = 25, .flags = RATE_IN_4430 }, | ||
| 312 | { .div = 26, .val = 26, .flags = RATE_IN_4430 }, | ||
| 313 | { .div = 27, .val = 27, .flags = RATE_IN_4430 }, | ||
| 314 | { .div = 28, .val = 28, .flags = RATE_IN_4430 }, | ||
| 315 | { .div = 29, .val = 29, .flags = RATE_IN_4430 }, | ||
| 316 | { .div = 30, .val = 30, .flags = RATE_IN_4430 }, | ||
| 317 | { .div = 31, .val = 31, .flags = RATE_IN_4430 }, | ||
| 318 | { .div = 0 }, | ||
| 319 | }; | ||
| 320 | |||
| 321 | static const struct clksel dpll_abe_m2x2_div[] = { | ||
| 322 | { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates }, | ||
| 323 | { .parent = NULL }, | ||
| 324 | }; | ||
| 325 | |||
| 268 | static struct clk dpll_abe_m2x2_ck = { | 326 | static struct clk dpll_abe_m2x2_ck = { |
| 269 | .name = "dpll_abe_m2x2_ck", | 327 | .name = "dpll_abe_m2x2_ck", |
| 270 | .parent = &dpll_abe_ck, | 328 | .parent = &dpll_abe_x2_ck, |
| 329 | .clksel = dpll_abe_m2x2_div, | ||
| 330 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, | ||
| 331 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, | ||
| 271 | .ops = &clkops_null, | 332 | .ops = &clkops_null, |
| 272 | .recalc = &followparent_recalc, | 333 | .recalc = &omap2_clksel_recalc, |
| 334 | .round_rate = &omap2_clksel_round_rate, | ||
| 335 | .set_rate = &omap2_clksel_set_rate, | ||
| 273 | }; | 336 | }; |
| 274 | 337 | ||
| 275 | static struct clk abe_24m_fclk = { | 338 | static struct clk abe_24m_fclk = { |
| 276 | .name = "abe_24m_fclk", | 339 | .name = "abe_24m_fclk", |
| 277 | .parent = &dpll_abe_m2x2_ck, | 340 | .parent = &dpll_abe_m2x2_ck, |
| 278 | .ops = &clkops_null, | 341 | .ops = &clkops_null, |
| 279 | .recalc = &followparent_recalc, | 342 | .fixed_div = 8, |
| 343 | .recalc = &omap_fixed_divisor_recalc, | ||
| 280 | }; | 344 | }; |
| 281 | 345 | ||
| 282 | static const struct clksel_rate div3_1to4_rates[] = { | 346 | static const struct clksel_rate div3_1to4_rates[] = { |
| @@ -326,50 +390,10 @@ static struct clk aess_fclk = { | |||
| 326 | .set_rate = &omap2_clksel_set_rate, | 390 | .set_rate = &omap2_clksel_set_rate, |
| 327 | }; | 391 | }; |
| 328 | 392 | ||
| 329 | static const struct clksel_rate div31_1to31_rates[] = { | 393 | static struct clk dpll_abe_m3x2_ck = { |
| 330 | { .div = 1, .val = 1, .flags = RATE_IN_4430 }, | 394 | .name = "dpll_abe_m3x2_ck", |
| 331 | { .div = 2, .val = 2, .flags = RATE_IN_4430 }, | 395 | .parent = &dpll_abe_x2_ck, |
| 332 | { .div = 3, .val = 3, .flags = RATE_IN_4430 }, | 396 | .clksel = dpll_abe_m2x2_div, |
| 333 | { .div = 4, .val = 4, .flags = RATE_IN_4430 }, | ||
| 334 | { .div = 5, .val = 5, .flags = RATE_IN_4430 }, | ||
| 335 | { .div = 6, .val = 6, .flags = RATE_IN_4430 }, | ||
| 336 | { .div = 7, .val = 7, .flags = RATE_IN_4430 }, | ||
| 337 | { .div = 8, .val = 8, .flags = RATE_IN_4430 }, | ||
| 338 | { .div = 9, .val = 9, .flags = RATE_IN_4430 }, | ||
| 339 | { .div = 10, .val = 10, .flags = RATE_IN_4430 }, | ||
| 340 | { .div = 11, .val = 11, .flags = RATE_IN_4430 }, | ||
| 341 | { .div = 12, .val = 12, .flags = RATE_IN_4430 }, | ||
| 342 | { .div = 13, .val = 13, .flags = RATE_IN_4430 }, | ||
| 343 | { .div = 14, .val = 14, .flags = RATE_IN_4430 }, | ||
| 344 | { .div = 15, .val = 15, .flags = RATE_IN_4430 }, | ||
| 345 | { .div = 16, .val = 16, .flags = RATE_IN_4430 }, | ||
| 346 | { .div = 17, .val = 17, .flags = RATE_IN_4430 }, | ||
| 347 | { .div = 18, .val = 18, .flags = RATE_IN_4430 }, | ||
| 348 | { .div = 19, .val = 19, .flags = RATE_IN_4430 }, | ||
| 349 | { .div = 20, .val = 20, .flags = RATE_IN_4430 }, | ||
| 350 | { .div = 21, .val = 21, .flags = RATE_IN_4430 }, | ||
| 351 | { .div = 22, .val = 22, .flags = RATE_IN_4430 }, | ||
| 352 | { .div = 23, .val = 23, .flags = RATE_IN_4430 }, | ||
| 353 | { .div = 24, .val = 24, .flags = RATE_IN_4430 }, | ||
| 354 | { .div = 25, .val = 25, .flags = RATE_IN_4430 }, | ||
| 355 | { .div = 26, .val = 26, .flags = RATE_IN_4430 }, | ||
| 356 | { .div = 27, .val = 27, .flags = RATE_IN_4430 }, | ||
| 357 | { .div = 28, .val = 28, .flags = RATE_IN_4430 }, | ||
| 358 | { .div = 29, .val = 29, .flags = RATE_IN_4430 }, | ||
| 359 | { .div = 30, .val = 30, .flags = RATE_IN_4430 }, | ||
| 360 | { .div = 31, .val = 31, .flags = RATE_IN_4430 }, | ||
| 361 | { .div = 0 }, | ||
| 362 | }; | ||
| 363 | |||
| 364 | static const struct clksel dpll_abe_m3_div[] = { | ||
| 365 | { .parent = &dpll_abe_ck, .rates = div31_1to31_rates }, | ||
| 366 | { .parent = NULL }, | ||
| 367 | }; | ||
| 368 | |||
| 369 | static struct clk dpll_abe_m3_ck = { | ||
| 370 | .name = "dpll_abe_m3_ck", | ||
| 371 | .parent = &dpll_abe_ck, | ||
| 372 | .clksel = dpll_abe_m3_div, | ||
| 373 | .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE, | 397 | .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE, |
| 374 | .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, | 398 | .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, |
| 375 | .ops = &clkops_null, | 399 | .ops = &clkops_null, |
| @@ -380,7 +404,7 @@ static struct clk dpll_abe_m3_ck = { | |||
| 380 | 404 | ||
| 381 | static const struct clksel core_hsd_byp_clk_mux_sel[] = { | 405 | static const struct clksel core_hsd_byp_clk_mux_sel[] = { |
| 382 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, | 406 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, |
| 383 | { .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates }, | 407 | { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates }, |
| 384 | { .parent = NULL }, | 408 | { .parent = NULL }, |
| 385 | }; | 409 | }; |
| 386 | 410 | ||
| @@ -424,15 +448,22 @@ static struct clk dpll_core_ck = { | |||
| 424 | .recalc = &omap3_dpll_recalc, | 448 | .recalc = &omap3_dpll_recalc, |
| 425 | }; | 449 | }; |
| 426 | 450 | ||
| 427 | static const struct clksel dpll_core_m6_div[] = { | 451 | static struct clk dpll_core_x2_ck = { |
| 428 | { .parent = &dpll_core_ck, .rates = div31_1to31_rates }, | 452 | .name = "dpll_core_x2_ck", |
| 453 | .parent = &dpll_core_ck, | ||
| 454 | .ops = &clkops_null, | ||
| 455 | .recalc = &omap3_clkoutx2_recalc, | ||
| 456 | }; | ||
| 457 | |||
| 458 | static const struct clksel dpll_core_m6x2_div[] = { | ||
| 459 | { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates }, | ||
| 429 | { .parent = NULL }, | 460 | { .parent = NULL }, |
| 430 | }; | 461 | }; |
| 431 | 462 | ||
| 432 | static struct clk dpll_core_m6_ck = { | 463 | static struct clk dpll_core_m6x2_ck = { |
| 433 | .name = "dpll_core_m6_ck", | 464 | .name = "dpll_core_m6x2_ck", |
| 434 | .parent = &dpll_core_ck, | 465 | .parent = &dpll_core_x2_ck, |
| 435 | .clksel = dpll_core_m6_div, | 466 | .clksel = dpll_core_m6x2_div, |
| 436 | .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE, | 467 | .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE, |
| 437 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, | 468 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, |
| 438 | .ops = &clkops_null, | 469 | .ops = &clkops_null, |
| @@ -443,7 +474,7 @@ static struct clk dpll_core_m6_ck = { | |||
| 443 | 474 | ||
| 444 | static const struct clksel dbgclk_mux_sel[] = { | 475 | static const struct clksel dbgclk_mux_sel[] = { |
| 445 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, | 476 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, |
| 446 | { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates }, | 477 | { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates }, |
| 447 | { .parent = NULL }, | 478 | { .parent = NULL }, |
| 448 | }; | 479 | }; |
| 449 | 480 | ||
| @@ -454,10 +485,15 @@ static struct clk dbgclk_mux_ck = { | |||
| 454 | .recalc = &followparent_recalc, | 485 | .recalc = &followparent_recalc, |
| 455 | }; | 486 | }; |
| 456 | 487 | ||
| 488 | static const struct clksel dpll_core_m2_div[] = { | ||
| 489 | { .parent = &dpll_core_ck, .rates = div31_1to31_rates }, | ||
| 490 | { .parent = NULL }, | ||
| 491 | }; | ||
| 492 | |||
| 457 | static struct clk dpll_core_m2_ck = { | 493 | static struct clk dpll_core_m2_ck = { |
| 458 | .name = "dpll_core_m2_ck", | 494 | .name = "dpll_core_m2_ck", |
| 459 | .parent = &dpll_core_ck, | 495 | .parent = &dpll_core_ck, |
| 460 | .clksel = dpll_core_m6_div, | 496 | .clksel = dpll_core_m2_div, |
| 461 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE, | 497 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE, |
| 462 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, | 498 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, |
| 463 | .ops = &clkops_null, | 499 | .ops = &clkops_null, |
| @@ -470,13 +506,14 @@ static struct clk ddrphy_ck = { | |||
| 470 | .name = "ddrphy_ck", | 506 | .name = "ddrphy_ck", |
| 471 | .parent = &dpll_core_m2_ck, | 507 | .parent = &dpll_core_m2_ck, |
| 472 | .ops = &clkops_null, | 508 | .ops = &clkops_null, |
| 473 | .recalc = &followparent_recalc, | 509 | .fixed_div = 2, |
| 510 | .recalc = &omap_fixed_divisor_recalc, | ||
| 474 | }; | 511 | }; |
| 475 | 512 | ||
| 476 | static struct clk dpll_core_m5_ck = { | 513 | static struct clk dpll_core_m5x2_ck = { |
| 477 | .name = "dpll_core_m5_ck", | 514 | .name = "dpll_core_m5x2_ck", |
| 478 | .parent = &dpll_core_ck, | 515 | .parent = &dpll_core_x2_ck, |
| 479 | .clksel = dpll_core_m6_div, | 516 | .clksel = dpll_core_m6x2_div, |
| 480 | .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE, | 517 | .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE, |
| 481 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, | 518 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, |
| 482 | .ops = &clkops_null, | 519 | .ops = &clkops_null, |
| @@ -486,13 +523,13 @@ static struct clk dpll_core_m5_ck = { | |||
| 486 | }; | 523 | }; |
| 487 | 524 | ||
| 488 | static const struct clksel div_core_div[] = { | 525 | static const struct clksel div_core_div[] = { |
| 489 | { .parent = &dpll_core_m5_ck, .rates = div2_1to2_rates }, | 526 | { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates }, |
| 490 | { .parent = NULL }, | 527 | { .parent = NULL }, |
| 491 | }; | 528 | }; |
| 492 | 529 | ||
| 493 | static struct clk div_core_ck = { | 530 | static struct clk div_core_ck = { |
| 494 | .name = "div_core_ck", | 531 | .name = "div_core_ck", |
| 495 | .parent = &dpll_core_m5_ck, | 532 | .parent = &dpll_core_m5x2_ck, |
| 496 | .clksel = div_core_div, | 533 | .clksel = div_core_div, |
| 497 | .clksel_reg = OMAP4430_CM_CLKSEL_CORE, | 534 | .clksel_reg = OMAP4430_CM_CLKSEL_CORE, |
| 498 | .clksel_mask = OMAP4430_CLKSEL_CORE_MASK, | 535 | .clksel_mask = OMAP4430_CLKSEL_CORE_MASK, |
| @@ -511,13 +548,13 @@ static const struct clksel_rate div4_1to8_rates[] = { | |||
| 511 | }; | 548 | }; |
| 512 | 549 | ||
| 513 | static const struct clksel div_iva_hs_clk_div[] = { | 550 | static const struct clksel div_iva_hs_clk_div[] = { |
| 514 | { .parent = &dpll_core_m5_ck, .rates = div4_1to8_rates }, | 551 | { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates }, |
| 515 | { .parent = NULL }, | 552 | { .parent = NULL }, |
| 516 | }; | 553 | }; |
| 517 | 554 | ||
| 518 | static struct clk div_iva_hs_clk = { | 555 | static struct clk div_iva_hs_clk = { |
| 519 | .name = "div_iva_hs_clk", | 556 | .name = "div_iva_hs_clk", |
| 520 | .parent = &dpll_core_m5_ck, | 557 | .parent = &dpll_core_m5x2_ck, |
| 521 | .clksel = div_iva_hs_clk_div, | 558 | .clksel = div_iva_hs_clk_div, |
| 522 | .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_IVA, | 559 | .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_IVA, |
| 523 | .clksel_mask = OMAP4430_CLKSEL_0_1_MASK, | 560 | .clksel_mask = OMAP4430_CLKSEL_0_1_MASK, |
| @@ -529,7 +566,7 @@ static struct clk div_iva_hs_clk = { | |||
| 529 | 566 | ||
| 530 | static struct clk div_mpu_hs_clk = { | 567 | static struct clk div_mpu_hs_clk = { |
| 531 | .name = "div_mpu_hs_clk", | 568 | .name = "div_mpu_hs_clk", |
| 532 | .parent = &dpll_core_m5_ck, | 569 | .parent = &dpll_core_m5x2_ck, |
| 533 | .clksel = div_iva_hs_clk_div, | 570 | .clksel = div_iva_hs_clk_div, |
| 534 | .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_MPU, | 571 | .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_MPU, |
| 535 | .clksel_mask = OMAP4430_CLKSEL_0_1_MASK, | 572 | .clksel_mask = OMAP4430_CLKSEL_0_1_MASK, |
| @@ -539,10 +576,10 @@ static struct clk div_mpu_hs_clk = { | |||
| 539 | .set_rate = &omap2_clksel_set_rate, | 576 | .set_rate = &omap2_clksel_set_rate, |
| 540 | }; | 577 | }; |
| 541 | 578 | ||
| 542 | static struct clk dpll_core_m4_ck = { | 579 | static struct clk dpll_core_m4x2_ck = { |
| 543 | .name = "dpll_core_m4_ck", | 580 | .name = "dpll_core_m4x2_ck", |
| 544 | .parent = &dpll_core_ck, | 581 | .parent = &dpll_core_x2_ck, |
| 545 | .clksel = dpll_core_m6_div, | 582 | .clksel = dpll_core_m6x2_div, |
| 546 | .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE, | 583 | .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE, |
| 547 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, | 584 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, |
| 548 | .ops = &clkops_null, | 585 | .ops = &clkops_null, |
| @@ -553,15 +590,21 @@ static struct clk dpll_core_m4_ck = { | |||
| 553 | 590 | ||
| 554 | static struct clk dll_clk_div_ck = { | 591 | static struct clk dll_clk_div_ck = { |
| 555 | .name = "dll_clk_div_ck", | 592 | .name = "dll_clk_div_ck", |
| 556 | .parent = &dpll_core_m4_ck, | 593 | .parent = &dpll_core_m4x2_ck, |
| 557 | .ops = &clkops_null, | 594 | .ops = &clkops_null, |
| 558 | .recalc = &followparent_recalc, | 595 | .fixed_div = 2, |
| 596 | .recalc = &omap_fixed_divisor_recalc, | ||
| 597 | }; | ||
| 598 | |||
| 599 | static const struct clksel dpll_abe_m2_div[] = { | ||
| 600 | { .parent = &dpll_abe_ck, .rates = div31_1to31_rates }, | ||
| 601 | { .parent = NULL }, | ||
| 559 | }; | 602 | }; |
| 560 | 603 | ||
| 561 | static struct clk dpll_abe_m2_ck = { | 604 | static struct clk dpll_abe_m2_ck = { |
| 562 | .name = "dpll_abe_m2_ck", | 605 | .name = "dpll_abe_m2_ck", |
| 563 | .parent = &dpll_abe_ck, | 606 | .parent = &dpll_abe_ck, |
| 564 | .clksel = dpll_abe_m3_div, | 607 | .clksel = dpll_abe_m2_div, |
| 565 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, | 608 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, |
| 566 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, | 609 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, |
| 567 | .ops = &clkops_null, | 610 | .ops = &clkops_null, |
| @@ -570,22 +613,24 @@ static struct clk dpll_abe_m2_ck = { | |||
| 570 | .set_rate = &omap2_clksel_set_rate, | 613 | .set_rate = &omap2_clksel_set_rate, |
| 571 | }; | 614 | }; |
| 572 | 615 | ||
| 573 | static struct clk dpll_core_m3_ck = { | 616 | static struct clk dpll_core_m3x2_ck = { |
| 574 | .name = "dpll_core_m3_ck", | 617 | .name = "dpll_core_m3x2_ck", |
| 575 | .parent = &dpll_core_ck, | 618 | .parent = &dpll_core_x2_ck, |
| 576 | .clksel = dpll_core_m6_div, | 619 | .clksel = dpll_core_m6x2_div, |
| 577 | .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, | 620 | .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, |
| 578 | .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, | 621 | .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, |
| 579 | .ops = &clkops_null, | 622 | .ops = &clkops_omap2_dflt, |
| 623 | .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, | ||
| 624 | .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, | ||
| 580 | .recalc = &omap2_clksel_recalc, | 625 | .recalc = &omap2_clksel_recalc, |
| 581 | .round_rate = &omap2_clksel_round_rate, | 626 | .round_rate = &omap2_clksel_round_rate, |
| 582 | .set_rate = &omap2_clksel_set_rate, | 627 | .set_rate = &omap2_clksel_set_rate, |
| 583 | }; | 628 | }; |
| 584 | 629 | ||
| 585 | static struct clk dpll_core_m7_ck = { | 630 | static struct clk dpll_core_m7x2_ck = { |
| 586 | .name = "dpll_core_m7_ck", | 631 | .name = "dpll_core_m7x2_ck", |
| 587 | .parent = &dpll_core_ck, | 632 | .parent = &dpll_core_x2_ck, |
| 588 | .clksel = dpll_core_m6_div, | 633 | .clksel = dpll_core_m6x2_div, |
| 589 | .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE, | 634 | .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE, |
| 590 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, | 635 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, |
| 591 | .ops = &clkops_null, | 636 | .ops = &clkops_null, |
| @@ -603,8 +648,12 @@ static const struct clksel iva_hsd_byp_clk_mux_sel[] = { | |||
| 603 | static struct clk iva_hsd_byp_clk_mux_ck = { | 648 | static struct clk iva_hsd_byp_clk_mux_ck = { |
| 604 | .name = "iva_hsd_byp_clk_mux_ck", | 649 | .name = "iva_hsd_byp_clk_mux_ck", |
| 605 | .parent = &sys_clkin_ck, | 650 | .parent = &sys_clkin_ck, |
| 651 | .clksel = iva_hsd_byp_clk_mux_sel, | ||
| 652 | .init = &omap2_init_clksel_parent, | ||
| 653 | .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, | ||
| 654 | .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, | ||
| 606 | .ops = &clkops_null, | 655 | .ops = &clkops_null, |
| 607 | .recalc = &followparent_recalc, | 656 | .recalc = &omap2_clksel_recalc, |
| 608 | }; | 657 | }; |
| 609 | 658 | ||
| 610 | /* DPLL_IVA */ | 659 | /* DPLL_IVA */ |
| @@ -638,15 +687,22 @@ static struct clk dpll_iva_ck = { | |||
| 638 | .set_rate = &omap3_noncore_dpll_set_rate, | 687 | .set_rate = &omap3_noncore_dpll_set_rate, |
| 639 | }; | 688 | }; |
| 640 | 689 | ||
| 641 | static const struct clksel dpll_iva_m4_div[] = { | 690 | static struct clk dpll_iva_x2_ck = { |
| 642 | { .parent = &dpll_iva_ck, .rates = div31_1to31_rates }, | 691 | .name = "dpll_iva_x2_ck", |
| 692 | .parent = &dpll_iva_ck, | ||
| 693 | .ops = &clkops_null, | ||
| 694 | .recalc = &omap3_clkoutx2_recalc, | ||
| 695 | }; | ||
| 696 | |||
| 697 | static const struct clksel dpll_iva_m4x2_div[] = { | ||
| 698 | { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates }, | ||
| 643 | { .parent = NULL }, | 699 | { .parent = NULL }, |
| 644 | }; | 700 | }; |
| 645 | 701 | ||
| 646 | static struct clk dpll_iva_m4_ck = { | 702 | static struct clk dpll_iva_m4x2_ck = { |
| 647 | .name = "dpll_iva_m4_ck", | 703 | .name = "dpll_iva_m4x2_ck", |
| 648 | .parent = &dpll_iva_ck, | 704 | .parent = &dpll_iva_x2_ck, |
| 649 | .clksel = dpll_iva_m4_div, | 705 | .clksel = dpll_iva_m4x2_div, |
| 650 | .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA, | 706 | .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA, |
| 651 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, | 707 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, |
| 652 | .ops = &clkops_null, | 708 | .ops = &clkops_null, |
| @@ -655,10 +711,10 @@ static struct clk dpll_iva_m4_ck = { | |||
| 655 | .set_rate = &omap2_clksel_set_rate, | 711 | .set_rate = &omap2_clksel_set_rate, |
| 656 | }; | 712 | }; |
| 657 | 713 | ||
| 658 | static struct clk dpll_iva_m5_ck = { | 714 | static struct clk dpll_iva_m5x2_ck = { |
| 659 | .name = "dpll_iva_m5_ck", | 715 | .name = "dpll_iva_m5x2_ck", |
| 660 | .parent = &dpll_iva_ck, | 716 | .parent = &dpll_iva_x2_ck, |
| 661 | .clksel = dpll_iva_m4_div, | 717 | .clksel = dpll_iva_m4x2_div, |
| 662 | .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA, | 718 | .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA, |
| 663 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, | 719 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, |
| 664 | .ops = &clkops_null, | 720 | .ops = &clkops_null, |
| @@ -717,9 +773,10 @@ static struct clk dpll_mpu_m2_ck = { | |||
| 717 | 773 | ||
| 718 | static struct clk per_hs_clk_div_ck = { | 774 | static struct clk per_hs_clk_div_ck = { |
| 719 | .name = "per_hs_clk_div_ck", | 775 | .name = "per_hs_clk_div_ck", |
| 720 | .parent = &dpll_abe_m3_ck, | 776 | .parent = &dpll_abe_m3x2_ck, |
| 721 | .ops = &clkops_null, | 777 | .ops = &clkops_null, |
| 722 | .recalc = &followparent_recalc, | 778 | .fixed_div = 2, |
| 779 | .recalc = &omap_fixed_divisor_recalc, | ||
| 723 | }; | 780 | }; |
| 724 | 781 | ||
| 725 | static const struct clksel per_hsd_byp_clk_mux_sel[] = { | 782 | static const struct clksel per_hsd_byp_clk_mux_sel[] = { |
| @@ -787,29 +844,48 @@ static struct clk dpll_per_m2_ck = { | |||
| 787 | .set_rate = &omap2_clksel_set_rate, | 844 | .set_rate = &omap2_clksel_set_rate, |
| 788 | }; | 845 | }; |
| 789 | 846 | ||
| 847 | static struct clk dpll_per_x2_ck = { | ||
| 848 | .name = "dpll_per_x2_ck", | ||
| 849 | .parent = &dpll_per_ck, | ||
| 850 | .ops = &clkops_null, | ||
| 851 | .recalc = &omap3_clkoutx2_recalc, | ||
| 852 | }; | ||
| 853 | |||
| 854 | static const struct clksel dpll_per_m2x2_div[] = { | ||
| 855 | { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates }, | ||
| 856 | { .parent = NULL }, | ||
| 857 | }; | ||
| 858 | |||
| 790 | static struct clk dpll_per_m2x2_ck = { | 859 | static struct clk dpll_per_m2x2_ck = { |
| 791 | .name = "dpll_per_m2x2_ck", | 860 | .name = "dpll_per_m2x2_ck", |
| 792 | .parent = &dpll_per_ck, | 861 | .parent = &dpll_per_x2_ck, |
| 862 | .clksel = dpll_per_m2x2_div, | ||
| 863 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, | ||
| 864 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, | ||
| 793 | .ops = &clkops_null, | 865 | .ops = &clkops_null, |
| 794 | .recalc = &followparent_recalc, | 866 | .recalc = &omap2_clksel_recalc, |
| 867 | .round_rate = &omap2_clksel_round_rate, | ||
| 868 | .set_rate = &omap2_clksel_set_rate, | ||
| 795 | }; | 869 | }; |
| 796 | 870 | ||
| 797 | static struct clk dpll_per_m3_ck = { | 871 | static struct clk dpll_per_m3x2_ck = { |
| 798 | .name = "dpll_per_m3_ck", | 872 | .name = "dpll_per_m3x2_ck", |
| 799 | .parent = &dpll_per_ck, | 873 | .parent = &dpll_per_x2_ck, |
| 800 | .clksel = dpll_per_m2_div, | 874 | .clksel = dpll_per_m2x2_div, |
| 801 | .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER, | 875 | .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER, |
| 802 | .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, | 876 | .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, |
| 803 | .ops = &clkops_null, | 877 | .ops = &clkops_omap2_dflt, |
| 878 | .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER, | ||
| 879 | .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, | ||
| 804 | .recalc = &omap2_clksel_recalc, | 880 | .recalc = &omap2_clksel_recalc, |
| 805 | .round_rate = &omap2_clksel_round_rate, | 881 | .round_rate = &omap2_clksel_round_rate, |
| 806 | .set_rate = &omap2_clksel_set_rate, | 882 | .set_rate = &omap2_clksel_set_rate, |
| 807 | }; | 883 | }; |
| 808 | 884 | ||
| 809 | static struct clk dpll_per_m4_ck = { | 885 | static struct clk dpll_per_m4x2_ck = { |
| 810 | .name = "dpll_per_m4_ck", | 886 | .name = "dpll_per_m4x2_ck", |
| 811 | .parent = &dpll_per_ck, | 887 | .parent = &dpll_per_x2_ck, |
| 812 | .clksel = dpll_per_m2_div, | 888 | .clksel = dpll_per_m2x2_div, |
| 813 | .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER, | 889 | .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER, |
| 814 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, | 890 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, |
| 815 | .ops = &clkops_null, | 891 | .ops = &clkops_null, |
| @@ -818,10 +894,10 @@ static struct clk dpll_per_m4_ck = { | |||
| 818 | .set_rate = &omap2_clksel_set_rate, | 894 | .set_rate = &omap2_clksel_set_rate, |
| 819 | }; | 895 | }; |
| 820 | 896 | ||
| 821 | static struct clk dpll_per_m5_ck = { | 897 | static struct clk dpll_per_m5x2_ck = { |
| 822 | .name = "dpll_per_m5_ck", | 898 | .name = "dpll_per_m5x2_ck", |
| 823 | .parent = &dpll_per_ck, | 899 | .parent = &dpll_per_x2_ck, |
| 824 | .clksel = dpll_per_m2_div, | 900 | .clksel = dpll_per_m2x2_div, |
| 825 | .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER, | 901 | .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER, |
| 826 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, | 902 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, |
| 827 | .ops = &clkops_null, | 903 | .ops = &clkops_null, |
| @@ -830,10 +906,10 @@ static struct clk dpll_per_m5_ck = { | |||
| 830 | .set_rate = &omap2_clksel_set_rate, | 906 | .set_rate = &omap2_clksel_set_rate, |
| 831 | }; | 907 | }; |
| 832 | 908 | ||
| 833 | static struct clk dpll_per_m6_ck = { | 909 | static struct clk dpll_per_m6x2_ck = { |
| 834 | .name = "dpll_per_m6_ck", | 910 | .name = "dpll_per_m6x2_ck", |
| 835 | .parent = &dpll_per_ck, | 911 | .parent = &dpll_per_x2_ck, |
| 836 | .clksel = dpll_per_m2_div, | 912 | .clksel = dpll_per_m2x2_div, |
| 837 | .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER, | 913 | .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER, |
| 838 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, | 914 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, |
| 839 | .ops = &clkops_null, | 915 | .ops = &clkops_null, |
| @@ -842,10 +918,10 @@ static struct clk dpll_per_m6_ck = { | |||
| 842 | .set_rate = &omap2_clksel_set_rate, | 918 | .set_rate = &omap2_clksel_set_rate, |
| 843 | }; | 919 | }; |
| 844 | 920 | ||
| 845 | static struct clk dpll_per_m7_ck = { | 921 | static struct clk dpll_per_m7x2_ck = { |
| 846 | .name = "dpll_per_m7_ck", | 922 | .name = "dpll_per_m7x2_ck", |
| 847 | .parent = &dpll_per_ck, | 923 | .parent = &dpll_per_x2_ck, |
| 848 | .clksel = dpll_per_m2_div, | 924 | .clksel = dpll_per_m2x2_div, |
| 849 | .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER, | 925 | .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER, |
| 850 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, | 926 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, |
| 851 | .ops = &clkops_null, | 927 | .ops = &clkops_null, |
| @@ -868,6 +944,7 @@ static struct dpll_data dpll_unipro_dd = { | |||
| 868 | .enable_mask = OMAP4430_DPLL_EN_MASK, | 944 | .enable_mask = OMAP4430_DPLL_EN_MASK, |
| 869 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | 945 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, |
| 870 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | 946 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, |
| 947 | .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK, | ||
| 871 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, | 948 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, |
| 872 | .max_divider = OMAP4430_MAX_DPLL_DIV, | 949 | .max_divider = OMAP4430_MAX_DPLL_DIV, |
| 873 | .min_divider = 1, | 950 | .min_divider = 1, |
| @@ -885,14 +962,21 @@ static struct clk dpll_unipro_ck = { | |||
| 885 | .set_rate = &omap3_noncore_dpll_set_rate, | 962 | .set_rate = &omap3_noncore_dpll_set_rate, |
| 886 | }; | 963 | }; |
| 887 | 964 | ||
| 965 | static struct clk dpll_unipro_x2_ck = { | ||
| 966 | .name = "dpll_unipro_x2_ck", | ||
| 967 | .parent = &dpll_unipro_ck, | ||
| 968 | .ops = &clkops_null, | ||
| 969 | .recalc = &omap3_clkoutx2_recalc, | ||
| 970 | }; | ||
| 971 | |||
| 888 | static const struct clksel dpll_unipro_m2x2_div[] = { | 972 | static const struct clksel dpll_unipro_m2x2_div[] = { |
| 889 | { .parent = &dpll_unipro_ck, .rates = div31_1to31_rates }, | 973 | { .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates }, |
| 890 | { .parent = NULL }, | 974 | { .parent = NULL }, |
| 891 | }; | 975 | }; |
| 892 | 976 | ||
| 893 | static struct clk dpll_unipro_m2x2_ck = { | 977 | static struct clk dpll_unipro_m2x2_ck = { |
| 894 | .name = "dpll_unipro_m2x2_ck", | 978 | .name = "dpll_unipro_m2x2_ck", |
| 895 | .parent = &dpll_unipro_ck, | 979 | .parent = &dpll_unipro_x2_ck, |
| 896 | .clksel = dpll_unipro_m2x2_div, | 980 | .clksel = dpll_unipro_m2x2_div, |
| 897 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO, | 981 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO, |
| 898 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, | 982 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, |
| @@ -904,16 +988,17 @@ static struct clk dpll_unipro_m2x2_ck = { | |||
| 904 | 988 | ||
| 905 | static struct clk usb_hs_clk_div_ck = { | 989 | static struct clk usb_hs_clk_div_ck = { |
| 906 | .name = "usb_hs_clk_div_ck", | 990 | .name = "usb_hs_clk_div_ck", |
| 907 | .parent = &dpll_abe_m3_ck, | 991 | .parent = &dpll_abe_m3x2_ck, |
| 908 | .ops = &clkops_null, | 992 | .ops = &clkops_null, |
| 909 | .recalc = &followparent_recalc, | 993 | .fixed_div = 3, |
| 994 | .recalc = &omap_fixed_divisor_recalc, | ||
| 910 | }; | 995 | }; |
| 911 | 996 | ||
| 912 | /* DPLL_USB */ | 997 | /* DPLL_USB */ |
| 913 | static struct dpll_data dpll_usb_dd = { | 998 | static struct dpll_data dpll_usb_dd = { |
| 914 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB, | 999 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB, |
| 915 | .clk_bypass = &usb_hs_clk_div_ck, | 1000 | .clk_bypass = &usb_hs_clk_div_ck, |
| 916 | .flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL, | 1001 | .flags = DPLL_J_TYPE, |
| 917 | .clk_ref = &sys_clkin_ck, | 1002 | .clk_ref = &sys_clkin_ck, |
| 918 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB, | 1003 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB, |
| 919 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | 1004 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), |
| @@ -967,7 +1052,7 @@ static struct clk dpll_usb_m2_ck = { | |||
| 967 | 1052 | ||
| 968 | static const struct clksel ducati_clk_mux_sel[] = { | 1053 | static const struct clksel ducati_clk_mux_sel[] = { |
| 969 | { .parent = &div_core_ck, .rates = div_1_0_rates }, | 1054 | { .parent = &div_core_ck, .rates = div_1_0_rates }, |
| 970 | { .parent = &dpll_per_m6_ck, .rates = div_1_1_rates }, | 1055 | { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates }, |
| 971 | { .parent = NULL }, | 1056 | { .parent = NULL }, |
| 972 | }; | 1057 | }; |
| 973 | 1058 | ||
| @@ -986,21 +1071,24 @@ static struct clk func_12m_fclk = { | |||
| 986 | .name = "func_12m_fclk", | 1071 | .name = "func_12m_fclk", |
| 987 | .parent = &dpll_per_m2x2_ck, | 1072 | .parent = &dpll_per_m2x2_ck, |
| 988 | .ops = &clkops_null, | 1073 | .ops = &clkops_null, |
| 989 | .recalc = &followparent_recalc, | 1074 | .fixed_div = 16, |
| 1075 | .recalc = &omap_fixed_divisor_recalc, | ||
| 990 | }; | 1076 | }; |
| 991 | 1077 | ||
| 992 | static struct clk func_24m_clk = { | 1078 | static struct clk func_24m_clk = { |
| 993 | .name = "func_24m_clk", | 1079 | .name = "func_24m_clk", |
| 994 | .parent = &dpll_per_m2_ck, | 1080 | .parent = &dpll_per_m2_ck, |
| 995 | .ops = &clkops_null, | 1081 | .ops = &clkops_null, |
| 996 | .recalc = &followparent_recalc, | 1082 | .fixed_div = 4, |
| 1083 | .recalc = &omap_fixed_divisor_recalc, | ||
| 997 | }; | 1084 | }; |
| 998 | 1085 | ||
| 999 | static struct clk func_24mc_fclk = { | 1086 | static struct clk func_24mc_fclk = { |
| 1000 | .name = "func_24mc_fclk", | 1087 | .name = "func_24mc_fclk", |
| 1001 | .parent = &dpll_per_m2x2_ck, | 1088 | .parent = &dpll_per_m2x2_ck, |
| 1002 | .ops = &clkops_null, | 1089 | .ops = &clkops_null, |
| 1003 | .recalc = &followparent_recalc, | 1090 | .fixed_div = 8, |
| 1091 | .recalc = &omap_fixed_divisor_recalc, | ||
| 1004 | }; | 1092 | }; |
| 1005 | 1093 | ||
| 1006 | static const struct clksel_rate div2_4to8_rates[] = { | 1094 | static const struct clksel_rate div2_4to8_rates[] = { |
| @@ -1030,7 +1118,8 @@ static struct clk func_48mc_fclk = { | |||
| 1030 | .name = "func_48mc_fclk", | 1118 | .name = "func_48mc_fclk", |
| 1031 | .parent = &dpll_per_m2x2_ck, | 1119 | .parent = &dpll_per_m2x2_ck, |
| 1032 | .ops = &clkops_null, | 1120 | .ops = &clkops_null, |
| 1033 | .recalc = &followparent_recalc, | 1121 | .fixed_div = 4, |
| 1122 | .recalc = &omap_fixed_divisor_recalc, | ||
| 1034 | }; | 1123 | }; |
| 1035 | 1124 | ||
| 1036 | static const struct clksel_rate div2_2to4_rates[] = { | 1125 | static const struct clksel_rate div2_2to4_rates[] = { |
| @@ -1040,13 +1129,13 @@ static const struct clksel_rate div2_2to4_rates[] = { | |||
| 1040 | }; | 1129 | }; |
| 1041 | 1130 | ||
| 1042 | static const struct clksel func_64m_fclk_div[] = { | 1131 | static const struct clksel func_64m_fclk_div[] = { |
| 1043 | { .parent = &dpll_per_m4_ck, .rates = div2_2to4_rates }, | 1132 | { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates }, |
| 1044 | { .parent = NULL }, | 1133 | { .parent = NULL }, |
| 1045 | }; | 1134 | }; |
| 1046 | 1135 | ||
| 1047 | static struct clk func_64m_fclk = { | 1136 | static struct clk func_64m_fclk = { |
| 1048 | .name = "func_64m_fclk", | 1137 | .name = "func_64m_fclk", |
| 1049 | .parent = &dpll_per_m4_ck, | 1138 | .parent = &dpll_per_m4x2_ck, |
| 1050 | .clksel = func_64m_fclk_div, | 1139 | .clksel = func_64m_fclk_div, |
| 1051 | .clksel_reg = OMAP4430_CM_SCALE_FCLK, | 1140 | .clksel_reg = OMAP4430_CM_SCALE_FCLK, |
| 1052 | .clksel_mask = OMAP4430_SCALE_FCLK_MASK, | 1141 | .clksel_mask = OMAP4430_SCALE_FCLK_MASK, |
| @@ -1147,7 +1236,8 @@ static struct clk lp_clk_div_ck = { | |||
| 1147 | .name = "lp_clk_div_ck", | 1236 | .name = "lp_clk_div_ck", |
| 1148 | .parent = &dpll_abe_m2x2_ck, | 1237 | .parent = &dpll_abe_m2x2_ck, |
| 1149 | .ops = &clkops_null, | 1238 | .ops = &clkops_null, |
| 1150 | .recalc = &followparent_recalc, | 1239 | .fixed_div = 16, |
| 1240 | .recalc = &omap_fixed_divisor_recalc, | ||
| 1151 | }; | 1241 | }; |
| 1152 | 1242 | ||
| 1153 | static const struct clksel l4_wkup_clk_mux_sel[] = { | 1243 | static const struct clksel l4_wkup_clk_mux_sel[] = { |
| @@ -1215,12 +1305,13 @@ static struct clk per_abe_24m_fclk = { | |||
| 1215 | .name = "per_abe_24m_fclk", | 1305 | .name = "per_abe_24m_fclk", |
| 1216 | .parent = &dpll_abe_m2_ck, | 1306 | .parent = &dpll_abe_m2_ck, |
| 1217 | .ops = &clkops_null, | 1307 | .ops = &clkops_null, |
| 1218 | .recalc = &followparent_recalc, | 1308 | .fixed_div = 4, |
| 1309 | .recalc = &omap_fixed_divisor_recalc, | ||
| 1219 | }; | 1310 | }; |
| 1220 | 1311 | ||
| 1221 | static const struct clksel pmd_stm_clock_mux_sel[] = { | 1312 | static const struct clksel pmd_stm_clock_mux_sel[] = { |
| 1222 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, | 1313 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, |
| 1223 | { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates }, | 1314 | { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates }, |
| 1224 | { .parent = &tie_low_clock_ck, .rates = div_1_2_rates }, | 1315 | { .parent = &tie_low_clock_ck, .rates = div_1_2_rates }, |
| 1225 | { .parent = NULL }, | 1316 | { .parent = NULL }, |
| 1226 | }; | 1317 | }; |
| @@ -1354,7 +1445,7 @@ static struct clk dsp_fck = { | |||
| 1354 | .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, | 1445 | .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, |
| 1355 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1446 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 1356 | .clkdm_name = "tesla_clkdm", | 1447 | .clkdm_name = "tesla_clkdm", |
| 1357 | .parent = &dpll_iva_m4_ck, | 1448 | .parent = &dpll_iva_m4x2_ck, |
| 1358 | .recalc = &followparent_recalc, | 1449 | .recalc = &followparent_recalc, |
| 1359 | }; | 1450 | }; |
| 1360 | 1451 | ||
| @@ -1384,7 +1475,7 @@ static struct clk dss_dss_clk = { | |||
| 1384 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, | 1475 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, |
| 1385 | .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, | 1476 | .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, |
| 1386 | .clkdm_name = "l3_dss_clkdm", | 1477 | .clkdm_name = "l3_dss_clkdm", |
| 1387 | .parent = &dpll_per_m5_ck, | 1478 | .parent = &dpll_per_m5x2_ck, |
| 1388 | .recalc = &followparent_recalc, | 1479 | .recalc = &followparent_recalc, |
| 1389 | }; | 1480 | }; |
| 1390 | 1481 | ||
| @@ -1441,14 +1532,14 @@ static struct clk emif2_fck = { | |||
| 1441 | }; | 1532 | }; |
| 1442 | 1533 | ||
| 1443 | static const struct clksel fdif_fclk_div[] = { | 1534 | static const struct clksel fdif_fclk_div[] = { |
| 1444 | { .parent = &dpll_per_m4_ck, .rates = div3_1to4_rates }, | 1535 | { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates }, |
| 1445 | { .parent = NULL }, | 1536 | { .parent = NULL }, |
| 1446 | }; | 1537 | }; |
| 1447 | 1538 | ||
| 1448 | /* Merged fdif_fclk into fdif */ | 1539 | /* Merged fdif_fclk into fdif */ |
| 1449 | static struct clk fdif_fck = { | 1540 | static struct clk fdif_fck = { |
| 1450 | .name = "fdif_fck", | 1541 | .name = "fdif_fck", |
| 1451 | .parent = &dpll_per_m4_ck, | 1542 | .parent = &dpll_per_m4x2_ck, |
| 1452 | .clksel = fdif_fclk_div, | 1543 | .clksel = fdif_fclk_div, |
| 1453 | .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, | 1544 | .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, |
| 1454 | .clksel_mask = OMAP4430_CLKSEL_FCLK_MASK, | 1545 | .clksel_mask = OMAP4430_CLKSEL_FCLK_MASK, |
| @@ -1602,15 +1693,15 @@ static struct clk gpmc_ick = { | |||
| 1602 | }; | 1693 | }; |
| 1603 | 1694 | ||
| 1604 | static const struct clksel sgx_clk_mux_sel[] = { | 1695 | static const struct clksel sgx_clk_mux_sel[] = { |
| 1605 | { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates }, | 1696 | { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates }, |
| 1606 | { .parent = &dpll_per_m7_ck, .rates = div_1_1_rates }, | 1697 | { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates }, |
| 1607 | { .parent = NULL }, | 1698 | { .parent = NULL }, |
| 1608 | }; | 1699 | }; |
| 1609 | 1700 | ||
| 1610 | /* Merged sgx_clk_mux into gpu */ | 1701 | /* Merged sgx_clk_mux into gpu */ |
| 1611 | static struct clk gpu_fck = { | 1702 | static struct clk gpu_fck = { |
| 1612 | .name = "gpu_fck", | 1703 | .name = "gpu_fck", |
| 1613 | .parent = &dpll_core_m7_ck, | 1704 | .parent = &dpll_core_m7x2_ck, |
| 1614 | .clksel = sgx_clk_mux_sel, | 1705 | .clksel = sgx_clk_mux_sel, |
| 1615 | .init = &omap2_init_clksel_parent, | 1706 | .init = &omap2_init_clksel_parent, |
| 1616 | .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, | 1707 | .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, |
| @@ -1729,7 +1820,7 @@ static struct clk iva_fck = { | |||
| 1729 | .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, | 1820 | .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, |
| 1730 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1821 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 1731 | .clkdm_name = "ivahd_clkdm", | 1822 | .clkdm_name = "ivahd_clkdm", |
| 1732 | .parent = &dpll_iva_m5_ck, | 1823 | .parent = &dpll_iva_m5x2_ck, |
| 1733 | .recalc = &followparent_recalc, | 1824 | .recalc = &followparent_recalc, |
| 1734 | }; | 1825 | }; |
| 1735 | 1826 | ||
| @@ -1749,6 +1840,7 @@ static struct clk l3_instr_ick = { | |||
| 1749 | .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, | 1840 | .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, |
| 1750 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1841 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 1751 | .clkdm_name = "l3_instr_clkdm", | 1842 | .clkdm_name = "l3_instr_clkdm", |
| 1843 | .flags = ENABLE_ON_INIT, | ||
| 1752 | .parent = &l3_div_ck, | 1844 | .parent = &l3_div_ck, |
| 1753 | .recalc = &followparent_recalc, | 1845 | .recalc = &followparent_recalc, |
| 1754 | }; | 1846 | }; |
| @@ -1759,6 +1851,7 @@ static struct clk l3_main_3_ick = { | |||
| 1759 | .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, | 1851 | .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, |
| 1760 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 1852 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 1761 | .clkdm_name = "l3_instr_clkdm", | 1853 | .clkdm_name = "l3_instr_clkdm", |
| 1854 | .flags = ENABLE_ON_INIT, | ||
| 1762 | .parent = &l3_div_ck, | 1855 | .parent = &l3_div_ck, |
| 1763 | .recalc = &followparent_recalc, | 1856 | .recalc = &followparent_recalc, |
| 1764 | }; | 1857 | }; |
| @@ -2063,6 +2156,7 @@ static struct clk ocp_wp_noc_ick = { | |||
| 2063 | .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, | 2156 | .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, |
| 2064 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 2157 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 2065 | .clkdm_name = "l3_instr_clkdm", | 2158 | .clkdm_name = "l3_instr_clkdm", |
| 2159 | .flags = ENABLE_ON_INIT, | ||
| 2066 | .parent = &l3_div_ck, | 2160 | .parent = &l3_div_ck, |
| 2067 | .recalc = &followparent_recalc, | 2161 | .recalc = &followparent_recalc, |
| 2068 | }; | 2162 | }; |
| @@ -2093,7 +2187,7 @@ static struct clk sl2if_ick = { | |||
| 2093 | .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL, | 2187 | .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL, |
| 2094 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | 2188 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 2095 | .clkdm_name = "ivahd_clkdm", | 2189 | .clkdm_name = "ivahd_clkdm", |
| 2096 | .parent = &dpll_iva_m5_ck, | 2190 | .parent = &dpll_iva_m5x2_ck, |
| 2097 | .recalc = &followparent_recalc, | 2191 | .recalc = &followparent_recalc, |
| 2098 | }; | 2192 | }; |
| 2099 | 2193 | ||
| @@ -2438,36 +2532,6 @@ static struct clk usb_host_fs_fck = { | |||
| 2438 | .recalc = &followparent_recalc, | 2532 | .recalc = &followparent_recalc, |
| 2439 | }; | 2533 | }; |
| 2440 | 2534 | ||
| 2441 | static struct clk usb_host_hs_utmi_p3_clk = { | ||
| 2442 | .name = "usb_host_hs_utmi_p3_clk", | ||
| 2443 | .ops = &clkops_omap2_dflt, | ||
| 2444 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | ||
| 2445 | .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, | ||
| 2446 | .clkdm_name = "l3_init_clkdm", | ||
| 2447 | .parent = &init_60m_fclk, | ||
| 2448 | .recalc = &followparent_recalc, | ||
| 2449 | }; | ||
| 2450 | |||
| 2451 | static struct clk usb_host_hs_hsic60m_p1_clk = { | ||
| 2452 | .name = "usb_host_hs_hsic60m_p1_clk", | ||
| 2453 | .ops = &clkops_omap2_dflt, | ||
| 2454 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | ||
| 2455 | .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, | ||
| 2456 | .clkdm_name = "l3_init_clkdm", | ||
| 2457 | .parent = &init_60m_fclk, | ||
| 2458 | .recalc = &followparent_recalc, | ||
| 2459 | }; | ||
| 2460 | |||
| 2461 | static struct clk usb_host_hs_hsic60m_p2_clk = { | ||
| 2462 | .name = "usb_host_hs_hsic60m_p2_clk", | ||
| 2463 | .ops = &clkops_omap2_dflt, | ||
| 2464 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | ||
| 2465 | .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, | ||
| 2466 | .clkdm_name = "l3_init_clkdm", | ||
| 2467 | .parent = &init_60m_fclk, | ||
| 2468 | .recalc = &followparent_recalc, | ||
| 2469 | }; | ||
| 2470 | |||
| 2471 | static const struct clksel utmi_p1_gfclk_sel[] = { | 2535 | static const struct clksel utmi_p1_gfclk_sel[] = { |
| 2472 | { .parent = &init_60m_fclk, .rates = div_1_0_rates }, | 2536 | { .parent = &init_60m_fclk, .rates = div_1_0_rates }, |
| 2473 | { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates }, | 2537 | { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates }, |
| @@ -2522,6 +2586,16 @@ static struct clk usb_host_hs_utmi_p2_clk = { | |||
| 2522 | .recalc = &followparent_recalc, | 2586 | .recalc = &followparent_recalc, |
| 2523 | }; | 2587 | }; |
| 2524 | 2588 | ||
| 2589 | static struct clk usb_host_hs_utmi_p3_clk = { | ||
| 2590 | .name = "usb_host_hs_utmi_p3_clk", | ||
| 2591 | .ops = &clkops_omap2_dflt, | ||
| 2592 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | ||
| 2593 | .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, | ||
| 2594 | .clkdm_name = "l3_init_clkdm", | ||
| 2595 | .parent = &init_60m_fclk, | ||
| 2596 | .recalc = &followparent_recalc, | ||
| 2597 | }; | ||
| 2598 | |||
| 2525 | static struct clk usb_host_hs_hsic480m_p1_clk = { | 2599 | static struct clk usb_host_hs_hsic480m_p1_clk = { |
| 2526 | .name = "usb_host_hs_hsic480m_p1_clk", | 2600 | .name = "usb_host_hs_hsic480m_p1_clk", |
| 2527 | .ops = &clkops_omap2_dflt, | 2601 | .ops = &clkops_omap2_dflt, |
| @@ -2532,6 +2606,26 @@ static struct clk usb_host_hs_hsic480m_p1_clk = { | |||
| 2532 | .recalc = &followparent_recalc, | 2606 | .recalc = &followparent_recalc, |
| 2533 | }; | 2607 | }; |
| 2534 | 2608 | ||
| 2609 | static struct clk usb_host_hs_hsic60m_p1_clk = { | ||
| 2610 | .name = "usb_host_hs_hsic60m_p1_clk", | ||
| 2611 | .ops = &clkops_omap2_dflt, | ||
| 2612 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | ||
| 2613 | .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, | ||
| 2614 | .clkdm_name = "l3_init_clkdm", | ||
| 2615 | .parent = &init_60m_fclk, | ||
| 2616 | .recalc = &followparent_recalc, | ||
| 2617 | }; | ||
| 2618 | |||
| 2619 | static struct clk usb_host_hs_hsic60m_p2_clk = { | ||
| 2620 | .name = "usb_host_hs_hsic60m_p2_clk", | ||
| 2621 | .ops = &clkops_omap2_dflt, | ||
| 2622 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | ||
| 2623 | .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, | ||
| 2624 | .clkdm_name = "l3_init_clkdm", | ||
| 2625 | .parent = &init_60m_fclk, | ||
| 2626 | .recalc = &followparent_recalc, | ||
| 2627 | }; | ||
| 2628 | |||
| 2535 | static struct clk usb_host_hs_hsic480m_p2_clk = { | 2629 | static struct clk usb_host_hs_hsic480m_p2_clk = { |
| 2536 | .name = "usb_host_hs_hsic480m_p2_clk", | 2630 | .name = "usb_host_hs_hsic480m_p2_clk", |
| 2537 | .ops = &clkops_omap2_dflt, | 2631 | .ops = &clkops_omap2_dflt, |
| @@ -2656,13 +2750,13 @@ static const struct clksel_rate div2_14to18_rates[] = { | |||
| 2656 | }; | 2750 | }; |
| 2657 | 2751 | ||
| 2658 | static const struct clksel usim_fclk_div[] = { | 2752 | static const struct clksel usim_fclk_div[] = { |
| 2659 | { .parent = &dpll_per_m4_ck, .rates = div2_14to18_rates }, | 2753 | { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates }, |
| 2660 | { .parent = NULL }, | 2754 | { .parent = NULL }, |
| 2661 | }; | 2755 | }; |
| 2662 | 2756 | ||
| 2663 | static struct clk usim_ck = { | 2757 | static struct clk usim_ck = { |
| 2664 | .name = "usim_ck", | 2758 | .name = "usim_ck", |
| 2665 | .parent = &dpll_per_m4_ck, | 2759 | .parent = &dpll_per_m4x2_ck, |
| 2666 | .clksel = usim_fclk_div, | 2760 | .clksel = usim_fclk_div, |
| 2667 | .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, | 2761 | .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, |
| 2668 | .clksel_mask = OMAP4430_CLKSEL_DIV_MASK, | 2762 | .clksel_mask = OMAP4430_CLKSEL_DIV_MASK, |
| @@ -2747,6 +2841,168 @@ static struct clk trace_clk_div_ck = { | |||
| 2747 | .set_rate = &omap2_clksel_set_rate, | 2841 | .set_rate = &omap2_clksel_set_rate, |
| 2748 | }; | 2842 | }; |
| 2749 | 2843 | ||
| 2844 | /* SCRM aux clk nodes */ | ||
| 2845 | |||
| 2846 | static const struct clksel auxclk_sel[] = { | ||
| 2847 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, | ||
| 2848 | { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates }, | ||
| 2849 | { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates }, | ||
| 2850 | { .parent = NULL }, | ||
| 2851 | }; | ||
| 2852 | |||
| 2853 | static struct clk auxclk0_ck = { | ||
| 2854 | .name = "auxclk0_ck", | ||
| 2855 | .parent = &sys_clkin_ck, | ||
| 2856 | .init = &omap2_init_clksel_parent, | ||
| 2857 | .ops = &clkops_omap2_dflt, | ||
| 2858 | .clksel = auxclk_sel, | ||
| 2859 | .clksel_reg = OMAP4_SCRM_AUXCLK0, | ||
| 2860 | .clksel_mask = OMAP4_SRCSELECT_MASK, | ||
| 2861 | .recalc = &omap2_clksel_recalc, | ||
| 2862 | .enable_reg = OMAP4_SCRM_AUXCLK0, | ||
| 2863 | .enable_bit = OMAP4_ENABLE_SHIFT, | ||
| 2864 | }; | ||
| 2865 | |||
| 2866 | static struct clk auxclk1_ck = { | ||
| 2867 | .name = "auxclk1_ck", | ||
| 2868 | .parent = &sys_clkin_ck, | ||
| 2869 | .init = &omap2_init_clksel_parent, | ||
| 2870 | .ops = &clkops_omap2_dflt, | ||
| 2871 | .clksel = auxclk_sel, | ||
| 2872 | .clksel_reg = OMAP4_SCRM_AUXCLK1, | ||
| 2873 | .clksel_mask = OMAP4_SRCSELECT_MASK, | ||
| 2874 | .recalc = &omap2_clksel_recalc, | ||
| 2875 | .enable_reg = OMAP4_SCRM_AUXCLK1, | ||
| 2876 | .enable_bit = OMAP4_ENABLE_SHIFT, | ||
| 2877 | }; | ||
| 2878 | |||
| 2879 | static struct clk auxclk2_ck = { | ||
| 2880 | .name = "auxclk2_ck", | ||
| 2881 | .parent = &sys_clkin_ck, | ||
| 2882 | .init = &omap2_init_clksel_parent, | ||
| 2883 | .ops = &clkops_omap2_dflt, | ||
| 2884 | .clksel = auxclk_sel, | ||
| 2885 | .clksel_reg = OMAP4_SCRM_AUXCLK2, | ||
| 2886 | .clksel_mask = OMAP4_SRCSELECT_MASK, | ||
| 2887 | .recalc = &omap2_clksel_recalc, | ||
| 2888 | .enable_reg = OMAP4_SCRM_AUXCLK2, | ||
| 2889 | .enable_bit = OMAP4_ENABLE_SHIFT, | ||
| 2890 | }; | ||
| 2891 | static struct clk auxclk3_ck = { | ||
| 2892 | .name = "auxclk3_ck", | ||
| 2893 | .parent = &sys_clkin_ck, | ||
| 2894 | .init = &omap2_init_clksel_parent, | ||
| 2895 | .ops = &clkops_omap2_dflt, | ||
| 2896 | .clksel = auxclk_sel, | ||
| 2897 | .clksel_reg = OMAP4_SCRM_AUXCLK3, | ||
| 2898 | .clksel_mask = OMAP4_SRCSELECT_MASK, | ||
| 2899 | .recalc = &omap2_clksel_recalc, | ||
| 2900 | .enable_reg = OMAP4_SCRM_AUXCLK3, | ||
| 2901 | .enable_bit = OMAP4_ENABLE_SHIFT, | ||
| 2902 | }; | ||
| 2903 | |||
| 2904 | static struct clk auxclk4_ck = { | ||
| 2905 | .name = "auxclk4_ck", | ||
| 2906 | .parent = &sys_clkin_ck, | ||
| 2907 | .init = &omap2_init_clksel_parent, | ||
| 2908 | .ops = &clkops_omap2_dflt, | ||
| 2909 | .clksel = auxclk_sel, | ||
| 2910 | .clksel_reg = OMAP4_SCRM_AUXCLK4, | ||
| 2911 | .clksel_mask = OMAP4_SRCSELECT_MASK, | ||
| 2912 | .recalc = &omap2_clksel_recalc, | ||
| 2913 | .enable_reg = OMAP4_SCRM_AUXCLK4, | ||
| 2914 | .enable_bit = OMAP4_ENABLE_SHIFT, | ||
| 2915 | }; | ||
| 2916 | |||
| 2917 | static struct clk auxclk5_ck = { | ||
| 2918 | .name = "auxclk5_ck", | ||
| 2919 | .parent = &sys_clkin_ck, | ||
| 2920 | .init = &omap2_init_clksel_parent, | ||
| 2921 | .ops = &clkops_omap2_dflt, | ||
| 2922 | .clksel = auxclk_sel, | ||
| 2923 | .clksel_reg = OMAP4_SCRM_AUXCLK5, | ||
| 2924 | .clksel_mask = OMAP4_SRCSELECT_MASK, | ||
| 2925 | .recalc = &omap2_clksel_recalc, | ||
| 2926 | .enable_reg = OMAP4_SCRM_AUXCLK5, | ||
| 2927 | .enable_bit = OMAP4_ENABLE_SHIFT, | ||
| 2928 | }; | ||
| 2929 | |||
| 2930 | static const struct clksel auxclkreq_sel[] = { | ||
| 2931 | { .parent = &auxclk0_ck, .rates = div_1_0_rates }, | ||
| 2932 | { .parent = &auxclk1_ck, .rates = div_1_1_rates }, | ||
| 2933 | { .parent = &auxclk2_ck, .rates = div_1_2_rates }, | ||
| 2934 | { .parent = &auxclk3_ck, .rates = div_1_3_rates }, | ||
| 2935 | { .parent = &auxclk4_ck, .rates = div_1_4_rates }, | ||
| 2936 | { .parent = &auxclk5_ck, .rates = div_1_5_rates }, | ||
| 2937 | { .parent = NULL }, | ||
| 2938 | }; | ||
| 2939 | |||
| 2940 | static struct clk auxclkreq0_ck = { | ||
| 2941 | .name = "auxclkreq0_ck", | ||
| 2942 | .parent = &auxclk0_ck, | ||
| 2943 | .init = &omap2_init_clksel_parent, | ||
| 2944 | .ops = &clkops_null, | ||
| 2945 | .clksel = auxclkreq_sel, | ||
| 2946 | .clksel_reg = OMAP4_SCRM_AUXCLKREQ0, | ||
| 2947 | .clksel_mask = OMAP4_MAPPING_MASK, | ||
| 2948 | .recalc = &omap2_clksel_recalc, | ||
| 2949 | }; | ||
| 2950 | |||
| 2951 | static struct clk auxclkreq1_ck = { | ||
| 2952 | .name = "auxclkreq1_ck", | ||
| 2953 | .parent = &auxclk1_ck, | ||
| 2954 | .init = &omap2_init_clksel_parent, | ||
| 2955 | .ops = &clkops_null, | ||
| 2956 | .clksel = auxclkreq_sel, | ||
| 2957 | .clksel_reg = OMAP4_SCRM_AUXCLKREQ1, | ||
| 2958 | .clksel_mask = OMAP4_MAPPING_MASK, | ||
| 2959 | .recalc = &omap2_clksel_recalc, | ||
| 2960 | }; | ||
| 2961 | |||
| 2962 | static struct clk auxclkreq2_ck = { | ||
| 2963 | .name = "auxclkreq2_ck", | ||
| 2964 | .parent = &auxclk2_ck, | ||
| 2965 | .init = &omap2_init_clksel_parent, | ||
| 2966 | .ops = &clkops_null, | ||
| 2967 | .clksel = auxclkreq_sel, | ||
| 2968 | .clksel_reg = OMAP4_SCRM_AUXCLKREQ2, | ||
| 2969 | .clksel_mask = OMAP4_MAPPING_MASK, | ||
| 2970 | .recalc = &omap2_clksel_recalc, | ||
| 2971 | }; | ||
| 2972 | |||
| 2973 | static struct clk auxclkreq3_ck = { | ||
| 2974 | .name = "auxclkreq3_ck", | ||
| 2975 | .parent = &auxclk3_ck, | ||
| 2976 | .init = &omap2_init_clksel_parent, | ||
| 2977 | .ops = &clkops_null, | ||
| 2978 | .clksel = auxclkreq_sel, | ||
| 2979 | .clksel_reg = OMAP4_SCRM_AUXCLKREQ3, | ||
| 2980 | .clksel_mask = OMAP4_MAPPING_MASK, | ||
| 2981 | .recalc = &omap2_clksel_recalc, | ||
| 2982 | }; | ||
| 2983 | |||
| 2984 | static struct clk auxclkreq4_ck = { | ||
| 2985 | .name = "auxclkreq4_ck", | ||
| 2986 | .parent = &auxclk4_ck, | ||
| 2987 | .init = &omap2_init_clksel_parent, | ||
| 2988 | .ops = &clkops_null, | ||
| 2989 | .clksel = auxclkreq_sel, | ||
| 2990 | .clksel_reg = OMAP4_SCRM_AUXCLKREQ4, | ||
| 2991 | .clksel_mask = OMAP4_MAPPING_MASK, | ||
| 2992 | .recalc = &omap2_clksel_recalc, | ||
| 2993 | }; | ||
| 2994 | |||
| 2995 | static struct clk auxclkreq5_ck = { | ||
| 2996 | .name = "auxclkreq5_ck", | ||
| 2997 | .parent = &auxclk5_ck, | ||
| 2998 | .init = &omap2_init_clksel_parent, | ||
| 2999 | .ops = &clkops_null, | ||
| 3000 | .clksel = auxclkreq_sel, | ||
| 3001 | .clksel_reg = OMAP4_SCRM_AUXCLKREQ5, | ||
| 3002 | .clksel_mask = OMAP4_MAPPING_MASK, | ||
| 3003 | .recalc = &omap2_clksel_recalc, | ||
| 3004 | }; | ||
| 3005 | |||
| 2750 | /* | 3006 | /* |
| 2751 | * clkdev | 3007 | * clkdev |
| 2752 | */ | 3008 | */ |
| @@ -2774,43 +3030,48 @@ static struct omap_clk omap44xx_clks[] = { | |||
| 2774 | CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X), | 3030 | CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X), |
| 2775 | CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X), | 3031 | CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X), |
| 2776 | CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X), | 3032 | CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X), |
| 3033 | CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X), | ||
| 2777 | CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X), | 3034 | CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X), |
| 2778 | CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X), | 3035 | CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X), |
| 2779 | CLK(NULL, "abe_clk", &abe_clk, CK_443X), | 3036 | CLK(NULL, "abe_clk", &abe_clk, CK_443X), |
| 2780 | CLK(NULL, "aess_fclk", &aess_fclk, CK_443X), | 3037 | CLK(NULL, "aess_fclk", &aess_fclk, CK_443X), |
| 2781 | CLK(NULL, "dpll_abe_m3_ck", &dpll_abe_m3_ck, CK_443X), | 3038 | CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X), |
| 2782 | CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X), | 3039 | CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X), |
| 2783 | CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X), | 3040 | CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X), |
| 2784 | CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_443X), | 3041 | CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X), |
| 3042 | CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X), | ||
| 2785 | CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X), | 3043 | CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X), |
| 2786 | CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X), | 3044 | CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X), |
| 2787 | CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X), | 3045 | CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X), |
| 2788 | CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_443X), | 3046 | CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X), |
| 2789 | CLK(NULL, "div_core_ck", &div_core_ck, CK_443X), | 3047 | CLK(NULL, "div_core_ck", &div_core_ck, CK_443X), |
| 2790 | CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X), | 3048 | CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X), |
| 2791 | CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X), | 3049 | CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X), |
| 2792 | CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_443X), | 3050 | CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X), |
| 2793 | CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X), | 3051 | CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X), |
| 2794 | CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X), | 3052 | CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X), |
| 2795 | CLK(NULL, "dpll_core_m3_ck", &dpll_core_m3_ck, CK_443X), | 3053 | CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X), |
| 2796 | CLK(NULL, "dpll_core_m7_ck", &dpll_core_m7_ck, CK_443X), | 3054 | CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X), |
| 2797 | CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X), | 3055 | CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X), |
| 2798 | CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X), | 3056 | CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X), |
| 2799 | CLK(NULL, "dpll_iva_m4_ck", &dpll_iva_m4_ck, CK_443X), | 3057 | CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X), |
| 2800 | CLK(NULL, "dpll_iva_m5_ck", &dpll_iva_m5_ck, CK_443X), | 3058 | CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X), |
| 3059 | CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X), | ||
| 2801 | CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X), | 3060 | CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X), |
| 2802 | CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X), | 3061 | CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X), |
| 2803 | CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X), | 3062 | CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X), |
| 2804 | CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X), | 3063 | CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X), |
| 2805 | CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X), | 3064 | CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X), |
| 2806 | CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X), | 3065 | CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X), |
| 3066 | CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X), | ||
| 2807 | CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X), | 3067 | CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X), |
| 2808 | CLK(NULL, "dpll_per_m3_ck", &dpll_per_m3_ck, CK_443X), | 3068 | CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X), |
| 2809 | CLK(NULL, "dpll_per_m4_ck", &dpll_per_m4_ck, CK_443X), | 3069 | CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X), |
| 2810 | CLK(NULL, "dpll_per_m5_ck", &dpll_per_m5_ck, CK_443X), | 3070 | CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X), |
| 2811 | CLK(NULL, "dpll_per_m6_ck", &dpll_per_m6_ck, CK_443X), | 3071 | CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X), |
| 2812 | CLK(NULL, "dpll_per_m7_ck", &dpll_per_m7_ck, CK_443X), | 3072 | CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X), |
| 2813 | CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X), | 3073 | CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X), |
| 3074 | CLK(NULL, "dpll_unipro_x2_ck", &dpll_unipro_x2_ck, CK_443X), | ||
| 2814 | CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X), | 3075 | CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X), |
| 2815 | CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X), | 3076 | CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X), |
| 2816 | CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X), | 3077 | CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X), |
| @@ -2856,26 +3117,26 @@ static struct omap_clk omap44xx_clks[] = { | |||
| 2856 | CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), | 3117 | CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), |
| 2857 | CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), | 3118 | CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), |
| 2858 | CLK(NULL, "fpka_fck", &fpka_fck, CK_443X), | 3119 | CLK(NULL, "fpka_fck", &fpka_fck, CK_443X), |
| 2859 | CLK(NULL, "gpio1_dbck", &gpio1_dbclk, CK_443X), | 3120 | CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X), |
| 2860 | CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), | 3121 | CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), |
| 2861 | CLK(NULL, "gpio2_dbck", &gpio2_dbclk, CK_443X), | 3122 | CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X), |
| 2862 | CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), | 3123 | CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), |
| 2863 | CLK(NULL, "gpio3_dbck", &gpio3_dbclk, CK_443X), | 3124 | CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X), |
| 2864 | CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), | 3125 | CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), |
| 2865 | CLK(NULL, "gpio4_dbck", &gpio4_dbclk, CK_443X), | 3126 | CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X), |
| 2866 | CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X), | 3127 | CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X), |
| 2867 | CLK(NULL, "gpio5_dbck", &gpio5_dbclk, CK_443X), | 3128 | CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X), |
| 2868 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), | 3129 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), |
| 2869 | CLK(NULL, "gpio6_dbck", &gpio6_dbclk, CK_443X), | 3130 | CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X), |
| 2870 | CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), | 3131 | CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), |
| 2871 | CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), | 3132 | CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), |
| 2872 | CLK(NULL, "gpu_fck", &gpu_fck, CK_443X), | 3133 | CLK(NULL, "gpu_fck", &gpu_fck, CK_443X), |
| 2873 | CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X), | 3134 | CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X), |
| 2874 | CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), | 3135 | CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), |
| 2875 | CLK("i2c_omap.1", "fck", &i2c1_fck, CK_443X), | 3136 | CLK("omap_i2c.1", "fck", &i2c1_fck, CK_443X), |
| 2876 | CLK("i2c_omap.2", "fck", &i2c2_fck, CK_443X), | 3137 | CLK("omap_i2c.2", "fck", &i2c2_fck, CK_443X), |
| 2877 | CLK("i2c_omap.3", "fck", &i2c3_fck, CK_443X), | 3138 | CLK("omap_i2c.3", "fck", &i2c3_fck, CK_443X), |
| 2878 | CLK("i2c_omap.4", "fck", &i2c4_fck, CK_443X), | 3139 | CLK("omap_i2c.4", "fck", &i2c4_fck, CK_443X), |
| 2879 | CLK(NULL, "ipu_fck", &ipu_fck, CK_443X), | 3140 | CLK(NULL, "ipu_fck", &ipu_fck, CK_443X), |
| 2880 | CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), | 3141 | CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), |
| 2881 | CLK(NULL, "iss_fck", &iss_fck, CK_443X), | 3142 | CLK(NULL, "iss_fck", &iss_fck, CK_443X), |
| @@ -2937,29 +3198,35 @@ static struct omap_clk omap44xx_clks[] = { | |||
| 2937 | CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), | 3198 | CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), |
| 2938 | CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), | 3199 | CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), |
| 2939 | CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), | 3200 | CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), |
| 2940 | CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X), | 3201 | CLK("ehci-omap.0", "fs_fck", &usb_host_fs_fck, CK_443X), |
| 2941 | CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X), | ||
| 2942 | CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), | ||
| 2943 | CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), | 3202 | CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), |
| 2944 | CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), | 3203 | CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), |
| 2945 | CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X), | 3204 | CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X), |
| 2946 | CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X), | 3205 | CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X), |
| 3206 | CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X), | ||
| 2947 | CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X), | 3207 | CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X), |
| 3208 | CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X), | ||
| 3209 | CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), | ||
| 2948 | CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), | 3210 | CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), |
| 2949 | CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), | 3211 | CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), |
| 2950 | CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X), | 3212 | CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X), |
| 3213 | CLK("ehci-omap.0", "hs_fck", &usb_host_hs_fck, CK_443X), | ||
| 3214 | CLK("ehci-omap.0", "usbhost_ick", &dummy_ck, CK_443X), | ||
| 2951 | CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), | 3215 | CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), |
| 2952 | CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), | 3216 | CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), |
| 2953 | CLK("musb_hdrc", "ick", &usb_otg_hs_ick, CK_443X), | 3217 | CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X), |
| 2954 | CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X), | 3218 | CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X), |
| 2955 | CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), | 3219 | CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), |
| 2956 | CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), | 3220 | CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), |
| 2957 | CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), | 3221 | CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), |
| 2958 | CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X), | 3222 | CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X), |
| 3223 | CLK("ehci-omap.0", "usbtll_ick", &usb_tll_hs_ick, CK_443X), | ||
| 3224 | CLK("ehci-omap.0", "usbtll_fck", &dummy_ck, CK_443X), | ||
| 2959 | CLK(NULL, "usim_ck", &usim_ck, CK_443X), | 3225 | CLK(NULL, "usim_ck", &usim_ck, CK_443X), |
| 2960 | CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), | 3226 | CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), |
| 2961 | CLK(NULL, "usim_fck", &usim_fck, CK_443X), | 3227 | CLK(NULL, "usim_fck", &usim_fck, CK_443X), |
| 2962 | CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X), | 3228 | CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X), |
| 3229 | CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X), | ||
| 2963 | CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), | 3230 | CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), |
| 2964 | CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), | 3231 | CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), |
| 2965 | CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), | 3232 | CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), |
| @@ -2975,10 +3242,10 @@ static struct omap_clk omap44xx_clks[] = { | |||
| 2975 | CLK(NULL, "gpt9_ick", &dummy_ck, CK_443X), | 3242 | CLK(NULL, "gpt9_ick", &dummy_ck, CK_443X), |
| 2976 | CLK(NULL, "gpt10_ick", &dummy_ck, CK_443X), | 3243 | CLK(NULL, "gpt10_ick", &dummy_ck, CK_443X), |
| 2977 | CLK(NULL, "gpt11_ick", &dummy_ck, CK_443X), | 3244 | CLK(NULL, "gpt11_ick", &dummy_ck, CK_443X), |
| 2978 | CLK("i2c_omap.1", "ick", &dummy_ck, CK_443X), | 3245 | CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X), |
| 2979 | CLK("i2c_omap.2", "ick", &dummy_ck, CK_443X), | 3246 | CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), |
| 2980 | CLK("i2c_omap.3", "ick", &dummy_ck, CK_443X), | 3247 | CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), |
| 2981 | CLK("i2c_omap.4", "ick", &dummy_ck, CK_443X), | 3248 | CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X), |
| 2982 | CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X), | 3249 | CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X), |
| 2983 | CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X), | 3250 | CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X), |
| 2984 | CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X), | 3251 | CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X), |
| @@ -2997,6 +3264,18 @@ static struct omap_clk omap44xx_clks[] = { | |||
| 2997 | CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), | 3264 | CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), |
| 2998 | CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), | 3265 | CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), |
| 2999 | CLK("omap_wdt", "ick", &dummy_ck, CK_443X), | 3266 | CLK("omap_wdt", "ick", &dummy_ck, CK_443X), |
| 3267 | CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X), | ||
| 3268 | CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X), | ||
| 3269 | CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X), | ||
| 3270 | CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X), | ||
| 3271 | CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X), | ||
| 3272 | CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X), | ||
| 3273 | CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X), | ||
| 3274 | CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X), | ||
| 3275 | CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X), | ||
| 3276 | CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X), | ||
| 3277 | CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X), | ||
| 3278 | CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X), | ||
| 3000 | }; | 3279 | }; |
| 3001 | 3280 | ||
| 3002 | int __init omap4xxx_clk_init(void) | 3281 | int __init omap4xxx_clk_init(void) |
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 6fb61b1a0d46..e20b98636ab4 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c | |||
| @@ -13,7 +13,6 @@ | |||
| 13 | */ | 13 | */ |
| 14 | #undef DEBUG | 14 | #undef DEBUG |
| 15 | 15 | ||
| 16 | #include <linux/module.h> | ||
| 17 | #include <linux/kernel.h> | 16 | #include <linux/kernel.h> |
| 18 | #include <linux/device.h> | 17 | #include <linux/device.h> |
| 19 | #include <linux/list.h> | 18 | #include <linux/list.h> |
| @@ -27,13 +26,16 @@ | |||
| 27 | 26 | ||
| 28 | #include <linux/bitops.h> | 27 | #include <linux/bitops.h> |
| 29 | 28 | ||
| 30 | #include "prm.h" | 29 | #include "prm2xxx_3xxx.h" |
| 31 | #include "prm-regbits-24xx.h" | 30 | #include "prm-regbits-24xx.h" |
| 32 | #include "cm.h" | 31 | #include "cm2xxx_3xxx.h" |
| 32 | #include "cm-regbits-24xx.h" | ||
| 33 | #include "cminst44xx.h" | ||
| 34 | #include "prcm44xx.h" | ||
| 33 | 35 | ||
| 34 | #include <plat/clock.h> | 36 | #include <plat/clock.h> |
| 35 | #include <plat/powerdomain.h> | 37 | #include "powerdomain.h" |
| 36 | #include <plat/clockdomain.h> | 38 | #include "clockdomain.h" |
| 37 | #include <plat/prcm.h> | 39 | #include <plat/prcm.h> |
| 38 | 40 | ||
| 39 | /* clkdm_list contains all registered struct clockdomains */ | 41 | /* clkdm_list contains all registered struct clockdomains */ |
| @@ -141,6 +143,9 @@ static struct clkdm_dep *_clkdm_deps_lookup(struct clockdomain *clkdm, | |||
| 141 | * clockdomain is in hardware-supervised mode. Meant to be called | 143 | * clockdomain is in hardware-supervised mode. Meant to be called |
| 142 | * once at clockdomain layer initialization, since these should remain | 144 | * once at clockdomain layer initialization, since these should remain |
| 143 | * fixed for a particular architecture. No return value. | 145 | * fixed for a particular architecture. No return value. |
| 146 | * | ||
| 147 | * XXX autodeps are deprecated and should be removed at the earliest | ||
| 148 | * opportunity | ||
| 144 | */ | 149 | */ |
| 145 | static void _autodep_lookup(struct clkdm_autodep *autodep) | 150 | static void _autodep_lookup(struct clkdm_autodep *autodep) |
| 146 | { | 151 | { |
| @@ -168,6 +173,9 @@ static void _autodep_lookup(struct clkdm_autodep *autodep) | |||
| 168 | * Add the "autodep" sleep & wakeup dependencies to clockdomain 'clkdm' | 173 | * Add the "autodep" sleep & wakeup dependencies to clockdomain 'clkdm' |
| 169 | * in hardware-supervised mode. Meant to be called from clock framework | 174 | * in hardware-supervised mode. Meant to be called from clock framework |
| 170 | * when a clock inside clockdomain 'clkdm' is enabled. No return value. | 175 | * when a clock inside clockdomain 'clkdm' is enabled. No return value. |
| 176 | * | ||
| 177 | * XXX autodeps are deprecated and should be removed at the earliest | ||
| 178 | * opportunity | ||
| 171 | */ | 179 | */ |
| 172 | static void _clkdm_add_autodeps(struct clockdomain *clkdm) | 180 | static void _clkdm_add_autodeps(struct clockdomain *clkdm) |
| 173 | { | 181 | { |
| @@ -199,6 +207,9 @@ static void _clkdm_add_autodeps(struct clockdomain *clkdm) | |||
| 199 | * Remove the "autodep" sleep & wakeup dependencies from clockdomain 'clkdm' | 207 | * Remove the "autodep" sleep & wakeup dependencies from clockdomain 'clkdm' |
| 200 | * in hardware-supervised mode. Meant to be called from clock framework | 208 | * in hardware-supervised mode. Meant to be called from clock framework |
| 201 | * when a clock inside clockdomain 'clkdm' is disabled. No return value. | 209 | * when a clock inside clockdomain 'clkdm' is disabled. No return value. |
| 210 | * | ||
| 211 | * XXX autodeps are deprecated and should be removed at the earliest | ||
| 212 | * opportunity | ||
| 202 | */ | 213 | */ |
| 203 | static void _clkdm_del_autodeps(struct clockdomain *clkdm) | 214 | static void _clkdm_del_autodeps(struct clockdomain *clkdm) |
| 204 | { | 215 | { |
| @@ -223,39 +234,56 @@ static void _clkdm_del_autodeps(struct clockdomain *clkdm) | |||
| 223 | } | 234 | } |
| 224 | } | 235 | } |
| 225 | 236 | ||
| 226 | /* | 237 | /** |
| 227 | * _omap2_clkdm_set_hwsup - set the hwsup idle transition bit | 238 | * _enable_hwsup - place a clockdomain into hardware-supervised idle |
| 228 | * @clkdm: struct clockdomain * | 239 | * @clkdm: struct clockdomain * |
| 229 | * @enable: int 0 to disable, 1 to enable | ||
| 230 | * | 240 | * |
| 231 | * Internal helper for actually switching the bit that controls hwsup | 241 | * Place the clockdomain into hardware-supervised idle mode. No return |
| 232 | * idle transitions for clkdm. | 242 | * value. |
| 243 | * | ||
| 244 | * XXX Should this return an error if the clockdomain does not support | ||
| 245 | * hardware-supervised idle mode? | ||
| 233 | */ | 246 | */ |
| 234 | static void _omap2_clkdm_set_hwsup(struct clockdomain *clkdm, int enable) | 247 | static void _enable_hwsup(struct clockdomain *clkdm) |
| 235 | { | 248 | { |
| 236 | u32 bits, v; | 249 | if (cpu_is_omap24xx()) |
| 237 | 250 | omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, | |
| 238 | if (cpu_is_omap24xx()) { | 251 | clkdm->clktrctrl_mask); |
| 239 | if (enable) | 252 | else if (cpu_is_omap34xx()) |
| 240 | bits = OMAP24XX_CLKSTCTRL_ENABLE_AUTO; | 253 | omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, |
| 241 | else | 254 | clkdm->clktrctrl_mask); |
| 242 | bits = OMAP24XX_CLKSTCTRL_DISABLE_AUTO; | 255 | else if (cpu_is_omap44xx()) |
| 243 | } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { | 256 | return omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition, |
| 244 | if (enable) | 257 | clkdm->cm_inst, |
| 245 | bits = OMAP34XX_CLKSTCTRL_ENABLE_AUTO; | 258 | clkdm->clkdm_offs); |
| 246 | else | 259 | else |
| 247 | bits = OMAP34XX_CLKSTCTRL_DISABLE_AUTO; | ||
| 248 | } else { | ||
| 249 | BUG(); | 260 | BUG(); |
| 250 | } | 261 | } |
| 251 | |||
| 252 | bits = bits << __ffs(clkdm->clktrctrl_mask); | ||
| 253 | |||
| 254 | v = __raw_readl(clkdm->clkstctrl_reg); | ||
| 255 | v &= ~(clkdm->clktrctrl_mask); | ||
| 256 | v |= bits; | ||
| 257 | __raw_writel(v, clkdm->clkstctrl_reg); | ||
| 258 | 262 | ||
| 263 | /** | ||
| 264 | * _disable_hwsup - place a clockdomain into software-supervised idle | ||
| 265 | * @clkdm: struct clockdomain * | ||
| 266 | * | ||
| 267 | * Place the clockdomain @clkdm into software-supervised idle mode. | ||
| 268 | * No return value. | ||
| 269 | * | ||
| 270 | * XXX Should this return an error if the clockdomain does not support | ||
| 271 | * software-supervised idle mode? | ||
| 272 | */ | ||
| 273 | static void _disable_hwsup(struct clockdomain *clkdm) | ||
| 274 | { | ||
| 275 | if (cpu_is_omap24xx()) | ||
| 276 | omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, | ||
| 277 | clkdm->clktrctrl_mask); | ||
| 278 | else if (cpu_is_omap34xx()) | ||
| 279 | omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, | ||
| 280 | clkdm->clktrctrl_mask); | ||
| 281 | else if (cpu_is_omap44xx()) | ||
| 282 | return omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition, | ||
| 283 | clkdm->cm_inst, | ||
| 284 | clkdm->clkdm_offs); | ||
| 285 | else | ||
| 286 | BUG(); | ||
| 259 | } | 287 | } |
| 260 | 288 | ||
| 261 | /* Public functions */ | 289 | /* Public functions */ |
| @@ -409,7 +437,7 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) | |||
| 409 | pr_debug("clockdomain: hardware will wake up %s when %s wakes " | 437 | pr_debug("clockdomain: hardware will wake up %s when %s wakes " |
| 410 | "up\n", clkdm1->name, clkdm2->name); | 438 | "up\n", clkdm1->name, clkdm2->name); |
| 411 | 439 | ||
| 412 | prm_set_mod_reg_bits((1 << clkdm2->dep_bit), | 440 | omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit), |
| 413 | clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); | 441 | clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); |
| 414 | } | 442 | } |
| 415 | 443 | ||
| @@ -444,7 +472,7 @@ int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) | |||
| 444 | pr_debug("clockdomain: hardware will no longer wake up %s " | 472 | pr_debug("clockdomain: hardware will no longer wake up %s " |
| 445 | "after %s wakes up\n", clkdm1->name, clkdm2->name); | 473 | "after %s wakes up\n", clkdm1->name, clkdm2->name); |
| 446 | 474 | ||
| 447 | prm_clear_mod_reg_bits((1 << clkdm2->dep_bit), | 475 | omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit), |
| 448 | clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); | 476 | clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); |
| 449 | } | 477 | } |
| 450 | 478 | ||
| @@ -480,7 +508,7 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) | |||
| 480 | } | 508 | } |
| 481 | 509 | ||
| 482 | /* XXX It's faster to return the atomic wkdep_usecount */ | 510 | /* XXX It's faster to return the atomic wkdep_usecount */ |
| 483 | return prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP, | 511 | return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP, |
| 484 | (1 << clkdm2->dep_bit)); | 512 | (1 << clkdm2->dep_bit)); |
| 485 | } | 513 | } |
| 486 | 514 | ||
| @@ -514,7 +542,7 @@ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm) | |||
| 514 | atomic_set(&cd->wkdep_usecount, 0); | 542 | atomic_set(&cd->wkdep_usecount, 0); |
| 515 | } | 543 | } |
| 516 | 544 | ||
| 517 | prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, PM_WKDEP); | 545 | omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, PM_WKDEP); |
| 518 | 546 | ||
| 519 | return 0; | 547 | return 0; |
| 520 | } | 548 | } |
| @@ -553,7 +581,7 @@ int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) | |||
| 553 | pr_debug("clockdomain: will prevent %s from sleeping if %s " | 581 | pr_debug("clockdomain: will prevent %s from sleeping if %s " |
| 554 | "is active\n", clkdm1->name, clkdm2->name); | 582 | "is active\n", clkdm1->name, clkdm2->name); |
| 555 | 583 | ||
| 556 | cm_set_mod_reg_bits((1 << clkdm2->dep_bit), | 584 | omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit), |
| 557 | clkdm1->pwrdm.ptr->prcm_offs, | 585 | clkdm1->pwrdm.ptr->prcm_offs, |
| 558 | OMAP3430_CM_SLEEPDEP); | 586 | OMAP3430_CM_SLEEPDEP); |
| 559 | } | 587 | } |
| @@ -596,7 +624,7 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) | |||
| 596 | "sleeping if %s is active\n", clkdm1->name, | 624 | "sleeping if %s is active\n", clkdm1->name, |
| 597 | clkdm2->name); | 625 | clkdm2->name); |
| 598 | 626 | ||
| 599 | cm_clear_mod_reg_bits((1 << clkdm2->dep_bit), | 627 | omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit), |
| 600 | clkdm1->pwrdm.ptr->prcm_offs, | 628 | clkdm1->pwrdm.ptr->prcm_offs, |
| 601 | OMAP3430_CM_SLEEPDEP); | 629 | OMAP3430_CM_SLEEPDEP); |
| 602 | } | 630 | } |
| @@ -639,7 +667,7 @@ int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) | |||
| 639 | } | 667 | } |
| 640 | 668 | ||
| 641 | /* XXX It's faster to return the atomic sleepdep_usecount */ | 669 | /* XXX It's faster to return the atomic sleepdep_usecount */ |
| 642 | return prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, | 670 | return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, |
| 643 | OMAP3430_CM_SLEEPDEP, | 671 | OMAP3430_CM_SLEEPDEP, |
| 644 | (1 << clkdm2->dep_bit)); | 672 | (1 << clkdm2->dep_bit)); |
| 645 | } | 673 | } |
| @@ -677,35 +705,13 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm) | |||
| 677 | atomic_set(&cd->sleepdep_usecount, 0); | 705 | atomic_set(&cd->sleepdep_usecount, 0); |
| 678 | } | 706 | } |
| 679 | 707 | ||
| 680 | prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, | 708 | omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, |
| 681 | OMAP3430_CM_SLEEPDEP); | 709 | OMAP3430_CM_SLEEPDEP); |
| 682 | 710 | ||
| 683 | return 0; | 711 | return 0; |
| 684 | } | 712 | } |
| 685 | 713 | ||
| 686 | /** | 714 | /** |
| 687 | * omap2_clkdm_clktrctrl_read - read the clkdm's current state transition mode | ||
| 688 | * @clkdm: struct clkdm * of a clockdomain | ||
| 689 | * | ||
| 690 | * Return the clockdomain @clkdm current state transition mode from the | ||
| 691 | * corresponding domain CM_CLKSTCTRL register. Returns -EINVAL if @clkdm | ||
| 692 | * is NULL or the current mode upon success. | ||
| 693 | */ | ||
| 694 | static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm) | ||
| 695 | { | ||
| 696 | u32 v; | ||
| 697 | |||
| 698 | if (!clkdm) | ||
| 699 | return -EINVAL; | ||
| 700 | |||
| 701 | v = __raw_readl(clkdm->clkstctrl_reg); | ||
| 702 | v &= clkdm->clktrctrl_mask; | ||
| 703 | v >>= __ffs(clkdm->clktrctrl_mask); | ||
| 704 | |||
| 705 | return v; | ||
| 706 | } | ||
| 707 | |||
| 708 | /** | ||
| 709 | * omap2_clkdm_sleep - force clockdomain sleep transition | 715 | * omap2_clkdm_sleep - force clockdomain sleep transition |
| 710 | * @clkdm: struct clockdomain * | 716 | * @clkdm: struct clockdomain * |
| 711 | * | 717 | * |
| @@ -729,18 +735,19 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm) | |||
| 729 | 735 | ||
| 730 | if (cpu_is_omap24xx()) { | 736 | if (cpu_is_omap24xx()) { |
| 731 | 737 | ||
| 732 | cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, | 738 | omap2_cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, |
| 733 | clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); | 739 | clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); |
| 734 | 740 | ||
| 735 | } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { | 741 | } else if (cpu_is_omap34xx()) { |
| 742 | |||
| 743 | omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs, | ||
| 744 | clkdm->clktrctrl_mask); | ||
| 736 | 745 | ||
| 737 | u32 bits = (OMAP34XX_CLKSTCTRL_FORCE_SLEEP << | 746 | } else if (cpu_is_omap44xx()) { |
| 738 | __ffs(clkdm->clktrctrl_mask)); | ||
| 739 | 747 | ||
| 740 | u32 v = __raw_readl(clkdm->clkstctrl_reg); | 748 | omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition, |
| 741 | v &= ~(clkdm->clktrctrl_mask); | 749 | clkdm->cm_inst, |
| 742 | v |= bits; | 750 | clkdm->clkdm_offs); |
| 743 | __raw_writel(v, clkdm->clkstctrl_reg); | ||
| 744 | 751 | ||
| 745 | } else { | 752 | } else { |
| 746 | BUG(); | 753 | BUG(); |
| @@ -773,18 +780,19 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm) | |||
| 773 | 780 | ||
| 774 | if (cpu_is_omap24xx()) { | 781 | if (cpu_is_omap24xx()) { |
| 775 | 782 | ||
| 776 | cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, | 783 | omap2_cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, |
| 777 | clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); | 784 | clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); |
| 778 | 785 | ||
| 779 | } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { | 786 | } else if (cpu_is_omap34xx()) { |
| 780 | 787 | ||
| 781 | u32 bits = (OMAP34XX_CLKSTCTRL_FORCE_WAKEUP << | 788 | omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs, |
| 782 | __ffs(clkdm->clktrctrl_mask)); | 789 | clkdm->clktrctrl_mask); |
| 783 | 790 | ||
| 784 | u32 v = __raw_readl(clkdm->clkstctrl_reg); | 791 | } else if (cpu_is_omap44xx()) { |
| 785 | v &= ~(clkdm->clktrctrl_mask); | 792 | |
| 786 | v |= bits; | 793 | omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition, |
| 787 | __raw_writel(v, clkdm->clkstctrl_reg); | 794 | clkdm->cm_inst, |
| 795 | clkdm->clkdm_offs); | ||
| 788 | 796 | ||
| 789 | } else { | 797 | } else { |
| 790 | BUG(); | 798 | BUG(); |
| @@ -829,7 +837,7 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm) | |||
| 829 | _clkdm_add_autodeps(clkdm); | 837 | _clkdm_add_autodeps(clkdm); |
| 830 | } | 838 | } |
| 831 | 839 | ||
| 832 | _omap2_clkdm_set_hwsup(clkdm, 1); | 840 | _enable_hwsup(clkdm); |
| 833 | 841 | ||
| 834 | pwrdm_clkdm_state_switch(clkdm); | 842 | pwrdm_clkdm_state_switch(clkdm); |
| 835 | } | 843 | } |
| @@ -857,7 +865,7 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm) | |||
| 857 | pr_debug("clockdomain: disabling automatic idle transitions for %s\n", | 865 | pr_debug("clockdomain: disabling automatic idle transitions for %s\n", |
| 858 | clkdm->name); | 866 | clkdm->name); |
| 859 | 867 | ||
| 860 | _omap2_clkdm_set_hwsup(clkdm, 0); | 868 | _disable_hwsup(clkdm); |
| 861 | 869 | ||
| 862 | /* | 870 | /* |
| 863 | * XXX This should be removed once TI adds wakeup/sleep | 871 | * XXX This should be removed once TI adds wakeup/sleep |
| @@ -891,7 +899,7 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm) | |||
| 891 | */ | 899 | */ |
| 892 | int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) | 900 | int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) |
| 893 | { | 901 | { |
| 894 | int v; | 902 | bool hwsup = false; |
| 895 | 903 | ||
| 896 | /* | 904 | /* |
| 897 | * XXX Rewrite this code to maintain a list of enabled | 905 | * XXX Rewrite this code to maintain a list of enabled |
| @@ -909,17 +917,27 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) | |||
| 909 | pr_debug("clockdomain: clkdm %s: clk %s now enabled\n", clkdm->name, | 917 | pr_debug("clockdomain: clkdm %s: clk %s now enabled\n", clkdm->name, |
| 910 | clk->name); | 918 | clk->name); |
| 911 | 919 | ||
| 912 | if (!clkdm->clkstctrl_reg) | 920 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { |
| 913 | return 0; | ||
| 914 | 921 | ||
| 915 | v = omap2_clkdm_clktrctrl_read(clkdm); | 922 | if (!clkdm->clktrctrl_mask) |
| 923 | return 0; | ||
| 916 | 924 | ||
| 917 | if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) || | 925 | hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs, |
| 918 | (cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO)) { | 926 | clkdm->clktrctrl_mask); |
| 927 | |||
| 928 | } else if (cpu_is_omap44xx()) { | ||
| 929 | |||
| 930 | hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition, | ||
| 931 | clkdm->cm_inst, | ||
| 932 | clkdm->clkdm_offs); | ||
| 933 | |||
| 934 | } | ||
| 935 | |||
| 936 | if (hwsup) { | ||
| 919 | /* Disable HW transitions when we are changing deps */ | 937 | /* Disable HW transitions when we are changing deps */ |
| 920 | _omap2_clkdm_set_hwsup(clkdm, 0); | 938 | _disable_hwsup(clkdm); |
| 921 | _clkdm_add_autodeps(clkdm); | 939 | _clkdm_add_autodeps(clkdm); |
| 922 | _omap2_clkdm_set_hwsup(clkdm, 1); | 940 | _enable_hwsup(clkdm); |
| 923 | } else { | 941 | } else { |
| 924 | omap2_clkdm_wakeup(clkdm); | 942 | omap2_clkdm_wakeup(clkdm); |
| 925 | } | 943 | } |
| @@ -946,7 +964,7 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) | |||
| 946 | */ | 964 | */ |
| 947 | int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) | 965 | int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) |
| 948 | { | 966 | { |
| 949 | int v; | 967 | bool hwsup = false; |
| 950 | 968 | ||
| 951 | /* | 969 | /* |
| 952 | * XXX Rewrite this code to maintain a list of enabled | 970 | * XXX Rewrite this code to maintain a list of enabled |
| @@ -971,17 +989,27 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) | |||
| 971 | pr_debug("clockdomain: clkdm %s: clk %s now disabled\n", clkdm->name, | 989 | pr_debug("clockdomain: clkdm %s: clk %s now disabled\n", clkdm->name, |
| 972 | clk->name); | 990 | clk->name); |
| 973 | 991 | ||
| 974 | if (!clkdm->clkstctrl_reg) | 992 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { |
| 975 | return 0; | ||
| 976 | 993 | ||
| 977 | v = omap2_clkdm_clktrctrl_read(clkdm); | 994 | if (!clkdm->clktrctrl_mask) |
| 995 | return 0; | ||
| 996 | |||
| 997 | hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs, | ||
| 998 | clkdm->clktrctrl_mask); | ||
| 999 | |||
| 1000 | } else if (cpu_is_omap44xx()) { | ||
| 1001 | |||
| 1002 | hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition, | ||
| 1003 | clkdm->cm_inst, | ||
| 1004 | clkdm->clkdm_offs); | ||
| 1005 | |||
| 1006 | } | ||
| 978 | 1007 | ||
| 979 | if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) || | 1008 | if (hwsup) { |
| 980 | (cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO)) { | ||
| 981 | /* Disable HW transitions when we are changing deps */ | 1009 | /* Disable HW transitions when we are changing deps */ |
| 982 | _omap2_clkdm_set_hwsup(clkdm, 0); | 1010 | _disable_hwsup(clkdm); |
| 983 | _clkdm_del_autodeps(clkdm); | 1011 | _clkdm_del_autodeps(clkdm); |
| 984 | _omap2_clkdm_set_hwsup(clkdm, 1); | 1012 | _enable_hwsup(clkdm); |
| 985 | } else { | 1013 | } else { |
| 986 | omap2_clkdm_sleep(clkdm); | 1014 | omap2_clkdm_sleep(clkdm); |
| 987 | } | 1015 | } |
diff --git a/arch/arm/plat-omap/include/plat/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index ba0a6c07c0fe..de3faa20b46b 100644 --- a/arch/arm/plat-omap/include/plat/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h | |||
| @@ -4,19 +4,21 @@ | |||
| 4 | * OMAP2/3 clockdomain framework functions | 4 | * OMAP2/3 clockdomain framework functions |
| 5 | * | 5 | * |
| 6 | * Copyright (C) 2008 Texas Instruments, Inc. | 6 | * Copyright (C) 2008 Texas Instruments, Inc. |
| 7 | * Copyright (C) 2008-2009 Nokia Corporation | 7 | * Copyright (C) 2008-2010 Nokia Corporation |
| 8 | * | 8 | * |
| 9 | * Written by Paul Walmsley | 9 | * Paul Walmsley |
| 10 | * | 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify | 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License version 2 as | 12 | * it under the terms of the GNU General Public License version 2 as |
| 13 | * published by the Free Software Foundation. | 13 | * published by the Free Software Foundation. |
| 14 | */ | 14 | */ |
| 15 | 15 | ||
| 16 | #ifndef __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H | 16 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAIN_H |
| 17 | #define __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H | 17 | #define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAIN_H |
| 18 | 18 | ||
| 19 | #include <plat/powerdomain.h> | 19 | #include <linux/init.h> |
| 20 | |||
| 21 | #include "powerdomain.h" | ||
| 20 | #include <plat/clock.h> | 22 | #include <plat/clock.h> |
| 21 | #include <plat/cpu.h> | 23 | #include <plat/cpu.h> |
| 22 | 24 | ||
| @@ -30,16 +32,6 @@ | |||
| 30 | #define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP) | 32 | #define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP) |
| 31 | #define CLKDM_CAN_HWSUP_SWSUP (CLKDM_CAN_SWSUP | CLKDM_CAN_HWSUP) | 33 | #define CLKDM_CAN_HWSUP_SWSUP (CLKDM_CAN_SWSUP | CLKDM_CAN_HWSUP) |
| 32 | 34 | ||
| 33 | /* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */ | ||
| 34 | #define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0 | ||
| 35 | #define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1 | ||
| 36 | |||
| 37 | /* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */ | ||
| 38 | #define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0 | ||
| 39 | #define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1 | ||
| 40 | #define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2 | ||
| 41 | #define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3 | ||
| 42 | |||
| 43 | /** | 35 | /** |
| 44 | * struct clkdm_autodep - clkdm deps to add when entering/exiting hwsup mode | 36 | * struct clkdm_autodep - clkdm deps to add when entering/exiting hwsup mode |
| 45 | * @clkdm: clockdomain to add wkdep+sleepdep on - set name member only | 37 | * @clkdm: clockdomain to add wkdep+sleepdep on - set name member only |
| @@ -90,11 +82,20 @@ struct clkdm_dep { | |||
| 90 | * @clktrctrl_mask: CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg | 82 | * @clktrctrl_mask: CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg |
| 91 | * @flags: Clockdomain capability flags | 83 | * @flags: Clockdomain capability flags |
| 92 | * @dep_bit: Bit shift of this clockdomain's PM_WKDEP/CM_SLEEPDEP bit | 84 | * @dep_bit: Bit shift of this clockdomain's PM_WKDEP/CM_SLEEPDEP bit |
| 85 | * @prcm_partition: (OMAP4 only) PRCM partition ID for this clkdm's registers | ||
| 86 | * @cm_inst: (OMAP4 only) CM instance register offset | ||
| 87 | * @clkdm_offs: (OMAP4 only) CM clockdomain register offset | ||
| 93 | * @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up | 88 | * @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up |
| 94 | * @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact | 89 | * @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact |
| 95 | * @omap_chip: OMAP chip types that this clockdomain is valid on | 90 | * @omap_chip: OMAP chip types that this clockdomain is valid on |
| 96 | * @usecount: Usecount tracking | 91 | * @usecount: Usecount tracking |
| 97 | * @node: list_head to link all clockdomains together | 92 | * @node: list_head to link all clockdomains together |
| 93 | * | ||
| 94 | * @prcm_partition should be a macro from mach-omap2/prcm44xx.h (OMAP4 only) | ||
| 95 | * @cm_inst should be a macro ending in _INST from the OMAP4 CM instance | ||
| 96 | * definitions (OMAP4 only) | ||
| 97 | * @clkdm_offs should be a macro ending in _CDOFFS from the OMAP4 CM instance | ||
| 98 | * definitions (OMAP4 only) | ||
| 98 | */ | 99 | */ |
| 99 | struct clockdomain { | 100 | struct clockdomain { |
| 100 | const char *name; | 101 | const char *name; |
| @@ -102,10 +103,14 @@ struct clockdomain { | |||
| 102 | const char *name; | 103 | const char *name; |
| 103 | struct powerdomain *ptr; | 104 | struct powerdomain *ptr; |
| 104 | } pwrdm; | 105 | } pwrdm; |
| 105 | void __iomem *clkstctrl_reg; | 106 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
| 106 | const u16 clktrctrl_mask; | 107 | const u16 clktrctrl_mask; |
| 108 | #endif | ||
| 107 | const u8 flags; | 109 | const u8 flags; |
| 108 | const u8 dep_bit; | 110 | const u8 dep_bit; |
| 111 | const u8 prcm_partition; | ||
| 112 | const s16 cm_inst; | ||
| 113 | const u16 clkdm_offs; | ||
| 109 | struct clkdm_dep *wkdep_srcs; | 114 | struct clkdm_dep *wkdep_srcs; |
| 110 | struct clkdm_dep *sleepdep_srcs; | 115 | struct clkdm_dep *sleepdep_srcs; |
| 111 | const struct omap_chip_id omap_chip; | 116 | const struct omap_chip_id omap_chip; |
| @@ -138,4 +143,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm); | |||
| 138 | int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk); | 143 | int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk); |
| 139 | int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk); | 144 | int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk); |
| 140 | 145 | ||
| 146 | extern void __init omap2_clockdomains_init(void); | ||
| 147 | extern void __init omap44xx_clockdomains_init(void); | ||
| 148 | |||
| 141 | #endif | 149 | #endif |
diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c index 8fc19ff2cd89..e4a7133ea3b3 100644 --- a/arch/arm/mach-omap2/clockdomains.h +++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c | |||
| @@ -4,7 +4,7 @@ | |||
| 4 | * Copyright (C) 2008-2009 Texas Instruments, Inc. | 4 | * Copyright (C) 2008-2009 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2008-2010 Nokia Corporation | 5 | * Copyright (C) 2008-2010 Nokia Corporation |
| 6 | * | 6 | * |
| 7 | * Written by Paul Walmsley and Jouni Högander | 7 | * Paul Walmsley, Jouni Högander |
| 8 | * | 8 | * |
| 9 | * This file contains clockdomains and clockdomain wakeup/sleep | 9 | * This file contains clockdomains and clockdomain wakeup/sleep |
| 10 | * dependencies for the OMAP2/3 chips. Some notes: | 10 | * dependencies for the OMAP2/3 chips. Some notes: |
| @@ -32,12 +32,17 @@ | |||
| 32 | * from the Power domain framework | 32 | * from the Power domain framework |
| 33 | */ | 33 | */ |
| 34 | 34 | ||
| 35 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H | 35 | #include <linux/kernel.h> |
| 36 | #define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H | 36 | #include <linux/io.h> |
| 37 | 37 | ||
| 38 | #include <plat/clockdomain.h> | 38 | #include "clockdomain.h" |
| 39 | #include "cm.h" | 39 | #include "prm2xxx_3xxx.h" |
| 40 | #include "prm.h" | 40 | #include "cm2xxx_3xxx.h" |
| 41 | #include "cm-regbits-24xx.h" | ||
| 42 | #include "cm-regbits-34xx.h" | ||
| 43 | #include "cm-regbits-44xx.h" | ||
| 44 | #include "prm-regbits-24xx.h" | ||
| 45 | #include "prm-regbits-34xx.h" | ||
| 41 | 46 | ||
| 42 | /* | 47 | /* |
| 43 | * Clockdomain dependencies for wkdeps/sleepdeps | 48 | * Clockdomain dependencies for wkdeps/sleepdeps |
| @@ -84,8 +89,6 @@ static struct clkdm_dep gfx_sgx_wkdeps[] = { | |||
| 84 | 89 | ||
| 85 | /* 24XX-specific possible dependencies */ | 90 | /* 24XX-specific possible dependencies */ |
| 86 | 91 | ||
| 87 | #ifdef CONFIG_ARCH_OMAP2 | ||
| 88 | |||
| 89 | /* Wakeup dependency source arrays */ | 92 | /* Wakeup dependency source arrays */ |
| 90 | 93 | ||
| 91 | /* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP */ | 94 | /* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP */ |
| @@ -165,8 +168,6 @@ static struct clkdm_dep core_24xx_wkdeps[] = { | |||
| 165 | { NULL }, | 168 | { NULL }, |
| 166 | }; | 169 | }; |
| 167 | 170 | ||
| 168 | #endif | ||
| 169 | |||
| 170 | 171 | ||
| 171 | /* 2430-specific possible wakeup dependencies */ | 172 | /* 2430-specific possible wakeup dependencies */ |
| 172 | 173 | ||
| @@ -425,8 +426,6 @@ static struct clkdm_dep gfx_sgx_sleepdeps[] = { | |||
| 425 | * sys_clkout/sys_clkout2. | 426 | * sys_clkout/sys_clkout2. |
| 426 | */ | 427 | */ |
| 427 | 428 | ||
| 428 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) | ||
| 429 | |||
| 430 | /* This is an implicit clockdomain - it is never defined as such in TRM */ | 429 | /* This is an implicit clockdomain - it is never defined as such in TRM */ |
| 431 | static struct clockdomain wkup_clkdm = { | 430 | static struct clockdomain wkup_clkdm = { |
| 432 | .name = "wkup_clkdm", | 431 | .name = "wkup_clkdm", |
| @@ -447,8 +446,6 @@ static struct clockdomain cm_clkdm = { | |||
| 447 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), | 446 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), |
| 448 | }; | 447 | }; |
| 449 | 448 | ||
| 450 | #endif | ||
| 451 | |||
| 452 | /* | 449 | /* |
| 453 | * 2420-only clockdomains | 450 | * 2420-only clockdomains |
| 454 | */ | 451 | */ |
| @@ -459,7 +456,6 @@ static struct clockdomain mpu_2420_clkdm = { | |||
| 459 | .name = "mpu_clkdm", | 456 | .name = "mpu_clkdm", |
| 460 | .pwrdm = { .name = "mpu_pwrdm" }, | 457 | .pwrdm = { .name = "mpu_pwrdm" }, |
| 461 | .flags = CLKDM_CAN_HWSUP, | 458 | .flags = CLKDM_CAN_HWSUP, |
| 462 | .clkstctrl_reg = OMAP2420_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL), | ||
| 463 | .wkdep_srcs = mpu_24xx_wkdeps, | 459 | .wkdep_srcs = mpu_24xx_wkdeps, |
| 464 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, | 460 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, |
| 465 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | 461 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| @@ -469,8 +465,6 @@ static struct clockdomain iva1_2420_clkdm = { | |||
| 469 | .name = "iva1_clkdm", | 465 | .name = "iva1_clkdm", |
| 470 | .pwrdm = { .name = "dsp_pwrdm" }, | 466 | .pwrdm = { .name = "dsp_pwrdm" }, |
| 471 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 467 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 472 | .clkstctrl_reg = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD, | ||
| 473 | OMAP2_CM_CLKSTCTRL), | ||
| 474 | .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT, | 468 | .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT, |
| 475 | .wkdep_srcs = dsp_24xx_wkdeps, | 469 | .wkdep_srcs = dsp_24xx_wkdeps, |
| 476 | .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK, | 470 | .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK, |
| @@ -481,8 +475,6 @@ static struct clockdomain dsp_2420_clkdm = { | |||
| 481 | .name = "dsp_clkdm", | 475 | .name = "dsp_clkdm", |
| 482 | .pwrdm = { .name = "dsp_pwrdm" }, | 476 | .pwrdm = { .name = "dsp_pwrdm" }, |
| 483 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 477 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 484 | .clkstctrl_reg = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD, | ||
| 485 | OMAP2_CM_CLKSTCTRL), | ||
| 486 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK, | 478 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK, |
| 487 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | 479 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 488 | }; | 480 | }; |
| @@ -491,7 +483,6 @@ static struct clockdomain gfx_2420_clkdm = { | |||
| 491 | .name = "gfx_clkdm", | 483 | .name = "gfx_clkdm", |
| 492 | .pwrdm = { .name = "gfx_pwrdm" }, | 484 | .pwrdm = { .name = "gfx_pwrdm" }, |
| 493 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 485 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 494 | .clkstctrl_reg = OMAP2420_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL), | ||
| 495 | .wkdep_srcs = gfx_sgx_wkdeps, | 486 | .wkdep_srcs = gfx_sgx_wkdeps, |
| 496 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK, | 487 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK, |
| 497 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | 488 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| @@ -501,7 +492,6 @@ static struct clockdomain core_l3_2420_clkdm = { | |||
| 501 | .name = "core_l3_clkdm", | 492 | .name = "core_l3_clkdm", |
| 502 | .pwrdm = { .name = "core_pwrdm" }, | 493 | .pwrdm = { .name = "core_pwrdm" }, |
| 503 | .flags = CLKDM_CAN_HWSUP, | 494 | .flags = CLKDM_CAN_HWSUP, |
| 504 | .clkstctrl_reg = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), | ||
| 505 | .wkdep_srcs = core_24xx_wkdeps, | 495 | .wkdep_srcs = core_24xx_wkdeps, |
| 506 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK, | 496 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK, |
| 507 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | 497 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| @@ -511,7 +501,6 @@ static struct clockdomain core_l4_2420_clkdm = { | |||
| 511 | .name = "core_l4_clkdm", | 501 | .name = "core_l4_clkdm", |
| 512 | .pwrdm = { .name = "core_pwrdm" }, | 502 | .pwrdm = { .name = "core_pwrdm" }, |
| 513 | .flags = CLKDM_CAN_HWSUP, | 503 | .flags = CLKDM_CAN_HWSUP, |
| 514 | .clkstctrl_reg = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), | ||
| 515 | .wkdep_srcs = core_24xx_wkdeps, | 504 | .wkdep_srcs = core_24xx_wkdeps, |
| 516 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK, | 505 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK, |
| 517 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | 506 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| @@ -521,7 +510,6 @@ static struct clockdomain dss_2420_clkdm = { | |||
| 521 | .name = "dss_clkdm", | 510 | .name = "dss_clkdm", |
| 522 | .pwrdm = { .name = "core_pwrdm" }, | 511 | .pwrdm = { .name = "core_pwrdm" }, |
| 523 | .flags = CLKDM_CAN_HWSUP, | 512 | .flags = CLKDM_CAN_HWSUP, |
| 524 | .clkstctrl_reg = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), | ||
| 525 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK, | 513 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK, |
| 526 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | 514 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 527 | }; | 515 | }; |
| @@ -539,8 +527,6 @@ static struct clockdomain mpu_2430_clkdm = { | |||
| 539 | .name = "mpu_clkdm", | 527 | .name = "mpu_clkdm", |
| 540 | .pwrdm = { .name = "mpu_pwrdm" }, | 528 | .pwrdm = { .name = "mpu_pwrdm" }, |
| 541 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 529 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 542 | .clkstctrl_reg = OMAP2430_CM_REGADDR(MPU_MOD, | ||
| 543 | OMAP2_CM_CLKSTCTRL), | ||
| 544 | .wkdep_srcs = mpu_24xx_wkdeps, | 530 | .wkdep_srcs = mpu_24xx_wkdeps, |
| 545 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, | 531 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, |
| 546 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | 532 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
| @@ -551,8 +537,6 @@ static struct clockdomain mdm_clkdm = { | |||
| 551 | .name = "mdm_clkdm", | 537 | .name = "mdm_clkdm", |
| 552 | .pwrdm = { .name = "mdm_pwrdm" }, | 538 | .pwrdm = { .name = "mdm_pwrdm" }, |
| 553 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 539 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 554 | .clkstctrl_reg = OMAP2430_CM_REGADDR(OMAP2430_MDM_MOD, | ||
| 555 | OMAP2_CM_CLKSTCTRL), | ||
| 556 | .dep_bit = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT, | 540 | .dep_bit = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT, |
| 557 | .wkdep_srcs = mdm_2430_wkdeps, | 541 | .wkdep_srcs = mdm_2430_wkdeps, |
| 558 | .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK, | 542 | .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK, |
| @@ -563,8 +547,6 @@ static struct clockdomain dsp_2430_clkdm = { | |||
| 563 | .name = "dsp_clkdm", | 547 | .name = "dsp_clkdm", |
| 564 | .pwrdm = { .name = "dsp_pwrdm" }, | 548 | .pwrdm = { .name = "dsp_pwrdm" }, |
| 565 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 549 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 566 | .clkstctrl_reg = OMAP2430_CM_REGADDR(OMAP24XX_DSP_MOD, | ||
| 567 | OMAP2_CM_CLKSTCTRL), | ||
| 568 | .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT, | 550 | .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT, |
| 569 | .wkdep_srcs = dsp_24xx_wkdeps, | 551 | .wkdep_srcs = dsp_24xx_wkdeps, |
| 570 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK, | 552 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK, |
| @@ -575,7 +557,6 @@ static struct clockdomain gfx_2430_clkdm = { | |||
| 575 | .name = "gfx_clkdm", | 557 | .name = "gfx_clkdm", |
| 576 | .pwrdm = { .name = "gfx_pwrdm" }, | 558 | .pwrdm = { .name = "gfx_pwrdm" }, |
| 577 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 559 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 578 | .clkstctrl_reg = OMAP2430_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL), | ||
| 579 | .wkdep_srcs = gfx_sgx_wkdeps, | 560 | .wkdep_srcs = gfx_sgx_wkdeps, |
| 580 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK, | 561 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK, |
| 581 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | 562 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
| @@ -590,7 +571,6 @@ static struct clockdomain core_l3_2430_clkdm = { | |||
| 590 | .name = "core_l3_clkdm", | 571 | .name = "core_l3_clkdm", |
| 591 | .pwrdm = { .name = "core_pwrdm" }, | 572 | .pwrdm = { .name = "core_pwrdm" }, |
| 592 | .flags = CLKDM_CAN_HWSUP, | 573 | .flags = CLKDM_CAN_HWSUP, |
| 593 | .clkstctrl_reg = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), | ||
| 594 | .dep_bit = OMAP24XX_EN_CORE_SHIFT, | 574 | .dep_bit = OMAP24XX_EN_CORE_SHIFT, |
| 595 | .wkdep_srcs = core_24xx_wkdeps, | 575 | .wkdep_srcs = core_24xx_wkdeps, |
| 596 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK, | 576 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK, |
| @@ -606,7 +586,6 @@ static struct clockdomain core_l4_2430_clkdm = { | |||
| 606 | .name = "core_l4_clkdm", | 586 | .name = "core_l4_clkdm", |
| 607 | .pwrdm = { .name = "core_pwrdm" }, | 587 | .pwrdm = { .name = "core_pwrdm" }, |
| 608 | .flags = CLKDM_CAN_HWSUP, | 588 | .flags = CLKDM_CAN_HWSUP, |
| 609 | .clkstctrl_reg = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), | ||
| 610 | .dep_bit = OMAP24XX_EN_CORE_SHIFT, | 589 | .dep_bit = OMAP24XX_EN_CORE_SHIFT, |
| 611 | .wkdep_srcs = core_24xx_wkdeps, | 590 | .wkdep_srcs = core_24xx_wkdeps, |
| 612 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK, | 591 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK, |
| @@ -617,7 +596,6 @@ static struct clockdomain dss_2430_clkdm = { | |||
| 617 | .name = "dss_clkdm", | 596 | .name = "dss_clkdm", |
| 618 | .pwrdm = { .name = "core_pwrdm" }, | 597 | .pwrdm = { .name = "core_pwrdm" }, |
| 619 | .flags = CLKDM_CAN_HWSUP, | 598 | .flags = CLKDM_CAN_HWSUP, |
| 620 | .clkstctrl_reg = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), | ||
| 621 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK, | 599 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK, |
| 622 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | 600 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
| 623 | }; | 601 | }; |
| @@ -635,7 +613,6 @@ static struct clockdomain mpu_3xxx_clkdm = { | |||
| 635 | .name = "mpu_clkdm", | 613 | .name = "mpu_clkdm", |
| 636 | .pwrdm = { .name = "mpu_pwrdm" }, | 614 | .pwrdm = { .name = "mpu_pwrdm" }, |
| 637 | .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP, | 615 | .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP, |
| 638 | .clkstctrl_reg = OMAP34XX_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL), | ||
| 639 | .dep_bit = OMAP3430_EN_MPU_SHIFT, | 616 | .dep_bit = OMAP3430_EN_MPU_SHIFT, |
| 640 | .wkdep_srcs = mpu_3xxx_wkdeps, | 617 | .wkdep_srcs = mpu_3xxx_wkdeps, |
| 641 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK, | 618 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK, |
| @@ -646,8 +623,6 @@ static struct clockdomain neon_clkdm = { | |||
| 646 | .name = "neon_clkdm", | 623 | .name = "neon_clkdm", |
| 647 | .pwrdm = { .name = "neon_pwrdm" }, | 624 | .pwrdm = { .name = "neon_pwrdm" }, |
| 648 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 625 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 649 | .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_NEON_MOD, | ||
| 650 | OMAP2_CM_CLKSTCTRL), | ||
| 651 | .wkdep_srcs = neon_wkdeps, | 626 | .wkdep_srcs = neon_wkdeps, |
| 652 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK, | 627 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK, |
| 653 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 628 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| @@ -657,8 +632,6 @@ static struct clockdomain iva2_clkdm = { | |||
| 657 | .name = "iva2_clkdm", | 632 | .name = "iva2_clkdm", |
| 658 | .pwrdm = { .name = "iva2_pwrdm" }, | 633 | .pwrdm = { .name = "iva2_pwrdm" }, |
| 659 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 634 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 660 | .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, | ||
| 661 | OMAP2_CM_CLKSTCTRL), | ||
| 662 | .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT, | 635 | .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT, |
| 663 | .wkdep_srcs = iva2_wkdeps, | 636 | .wkdep_srcs = iva2_wkdeps, |
| 664 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK, | 637 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK, |
| @@ -669,7 +642,6 @@ static struct clockdomain gfx_3430es1_clkdm = { | |||
| 669 | .name = "gfx_clkdm", | 642 | .name = "gfx_clkdm", |
| 670 | .pwrdm = { .name = "gfx_pwrdm" }, | 643 | .pwrdm = { .name = "gfx_pwrdm" }, |
| 671 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 644 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 672 | .clkstctrl_reg = OMAP34XX_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL), | ||
| 673 | .wkdep_srcs = gfx_sgx_wkdeps, | 645 | .wkdep_srcs = gfx_sgx_wkdeps, |
| 674 | .sleepdep_srcs = gfx_sgx_sleepdeps, | 646 | .sleepdep_srcs = gfx_sgx_sleepdeps, |
| 675 | .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK, | 647 | .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK, |
| @@ -680,8 +652,6 @@ static struct clockdomain sgx_clkdm = { | |||
| 680 | .name = "sgx_clkdm", | 652 | .name = "sgx_clkdm", |
| 681 | .pwrdm = { .name = "sgx_pwrdm" }, | 653 | .pwrdm = { .name = "sgx_pwrdm" }, |
| 682 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 654 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 683 | .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, | ||
| 684 | OMAP2_CM_CLKSTCTRL), | ||
| 685 | .wkdep_srcs = gfx_sgx_wkdeps, | 655 | .wkdep_srcs = gfx_sgx_wkdeps, |
| 686 | .sleepdep_srcs = gfx_sgx_sleepdeps, | 656 | .sleepdep_srcs = gfx_sgx_sleepdeps, |
| 687 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK, | 657 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK, |
| @@ -699,7 +669,6 @@ static struct clockdomain d2d_clkdm = { | |||
| 699 | .name = "d2d_clkdm", | 669 | .name = "d2d_clkdm", |
| 700 | .pwrdm = { .name = "core_pwrdm" }, | 670 | .pwrdm = { .name = "core_pwrdm" }, |
| 701 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 671 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 702 | .clkstctrl_reg = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), | ||
| 703 | .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK, | 672 | .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK, |
| 704 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 673 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 705 | }; | 674 | }; |
| @@ -713,7 +682,6 @@ static struct clockdomain core_l3_3xxx_clkdm = { | |||
| 713 | .name = "core_l3_clkdm", | 682 | .name = "core_l3_clkdm", |
| 714 | .pwrdm = { .name = "core_pwrdm" }, | 683 | .pwrdm = { .name = "core_pwrdm" }, |
| 715 | .flags = CLKDM_CAN_HWSUP, | 684 | .flags = CLKDM_CAN_HWSUP, |
| 716 | .clkstctrl_reg = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), | ||
| 717 | .dep_bit = OMAP3430_EN_CORE_SHIFT, | 685 | .dep_bit = OMAP3430_EN_CORE_SHIFT, |
| 718 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK, | 686 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK, |
| 719 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 687 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| @@ -728,7 +696,6 @@ static struct clockdomain core_l4_3xxx_clkdm = { | |||
| 728 | .name = "core_l4_clkdm", | 696 | .name = "core_l4_clkdm", |
| 729 | .pwrdm = { .name = "core_pwrdm" }, | 697 | .pwrdm = { .name = "core_pwrdm" }, |
| 730 | .flags = CLKDM_CAN_HWSUP, | 698 | .flags = CLKDM_CAN_HWSUP, |
| 731 | .clkstctrl_reg = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL), | ||
| 732 | .dep_bit = OMAP3430_EN_CORE_SHIFT, | 699 | .dep_bit = OMAP3430_EN_CORE_SHIFT, |
| 733 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK, | 700 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK, |
| 734 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 701 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| @@ -739,8 +706,6 @@ static struct clockdomain dss_3xxx_clkdm = { | |||
| 739 | .name = "dss_clkdm", | 706 | .name = "dss_clkdm", |
| 740 | .pwrdm = { .name = "dss_pwrdm" }, | 707 | .pwrdm = { .name = "dss_pwrdm" }, |
| 741 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 708 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 742 | .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, | ||
| 743 | OMAP2_CM_CLKSTCTRL), | ||
| 744 | .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT, | 709 | .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT, |
| 745 | .wkdep_srcs = dss_wkdeps, | 710 | .wkdep_srcs = dss_wkdeps, |
| 746 | .sleepdep_srcs = dss_sleepdeps, | 711 | .sleepdep_srcs = dss_sleepdeps, |
| @@ -752,8 +717,6 @@ static struct clockdomain cam_clkdm = { | |||
| 752 | .name = "cam_clkdm", | 717 | .name = "cam_clkdm", |
| 753 | .pwrdm = { .name = "cam_pwrdm" }, | 718 | .pwrdm = { .name = "cam_pwrdm" }, |
| 754 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 719 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 755 | .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, | ||
| 756 | OMAP2_CM_CLKSTCTRL), | ||
| 757 | .wkdep_srcs = cam_wkdeps, | 720 | .wkdep_srcs = cam_wkdeps, |
| 758 | .sleepdep_srcs = cam_sleepdeps, | 721 | .sleepdep_srcs = cam_sleepdeps, |
| 759 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK, | 722 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK, |
| @@ -764,8 +727,6 @@ static struct clockdomain usbhost_clkdm = { | |||
| 764 | .name = "usbhost_clkdm", | 727 | .name = "usbhost_clkdm", |
| 765 | .pwrdm = { .name = "usbhost_pwrdm" }, | 728 | .pwrdm = { .name = "usbhost_pwrdm" }, |
| 766 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 729 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 767 | .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, | ||
| 768 | OMAP2_CM_CLKSTCTRL), | ||
| 769 | .wkdep_srcs = usbhost_wkdeps, | 730 | .wkdep_srcs = usbhost_wkdeps, |
| 770 | .sleepdep_srcs = usbhost_sleepdeps, | 731 | .sleepdep_srcs = usbhost_sleepdeps, |
| 771 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK, | 732 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK, |
| @@ -776,8 +737,6 @@ static struct clockdomain per_clkdm = { | |||
| 776 | .name = "per_clkdm", | 737 | .name = "per_clkdm", |
| 777 | .pwrdm = { .name = "per_pwrdm" }, | 738 | .pwrdm = { .name = "per_pwrdm" }, |
| 778 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 739 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 779 | .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, | ||
| 780 | OMAP2_CM_CLKSTCTRL), | ||
| 781 | .dep_bit = OMAP3430_EN_PER_SHIFT, | 740 | .dep_bit = OMAP3430_EN_PER_SHIFT, |
| 782 | .wkdep_srcs = per_wkdeps, | 741 | .wkdep_srcs = per_wkdeps, |
| 783 | .sleepdep_srcs = per_sleepdeps, | 742 | .sleepdep_srcs = per_sleepdeps, |
| @@ -793,8 +752,6 @@ static struct clockdomain emu_clkdm = { | |||
| 793 | .name = "emu_clkdm", | 752 | .name = "emu_clkdm", |
| 794 | .pwrdm = { .name = "emu_pwrdm" }, | 753 | .pwrdm = { .name = "emu_pwrdm" }, |
| 795 | .flags = /* CLKDM_CAN_ENABLE_AUTO | */CLKDM_CAN_SWSUP, | 754 | .flags = /* CLKDM_CAN_ENABLE_AUTO | */CLKDM_CAN_SWSUP, |
| 796 | .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD, | ||
| 797 | OMAP2_CM_CLKSTCTRL), | ||
| 798 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK, | 755 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK, |
| 799 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 756 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 800 | }; | 757 | }; |
| @@ -831,8 +788,6 @@ static struct clockdomain dpll5_clkdm = { | |||
| 831 | 788 | ||
| 832 | #endif /* CONFIG_ARCH_OMAP3 */ | 789 | #endif /* CONFIG_ARCH_OMAP3 */ |
| 833 | 790 | ||
| 834 | #include "clockdomains44xx.h" | ||
| 835 | |||
| 836 | /* | 791 | /* |
| 837 | * Clockdomain hwsup dependencies (OMAP3 only) | 792 | * Clockdomain hwsup dependencies (OMAP3 only) |
| 838 | */ | 793 | */ |
| @@ -851,17 +806,10 @@ static struct clkdm_autodep clkdm_autodeps[] = { | |||
| 851 | } | 806 | } |
| 852 | }; | 807 | }; |
| 853 | 808 | ||
| 854 | /* | 809 | static struct clockdomain *clockdomains_omap2[] __initdata = { |
| 855 | * List of clockdomain pointers per platform | ||
| 856 | */ | ||
| 857 | |||
| 858 | static struct clockdomain *clockdomains_omap[] = { | ||
| 859 | |||
| 860 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) | ||
| 861 | &wkup_clkdm, | 810 | &wkup_clkdm, |
| 862 | &cm_clkdm, | 811 | &cm_clkdm, |
| 863 | &prm_clkdm, | 812 | &prm_clkdm, |
| 864 | #endif | ||
| 865 | 813 | ||
| 866 | #ifdef CONFIG_ARCH_OMAP2420 | 814 | #ifdef CONFIG_ARCH_OMAP2420 |
| 867 | &mpu_2420_clkdm, | 815 | &mpu_2420_clkdm, |
| @@ -903,35 +851,10 @@ static struct clockdomain *clockdomains_omap[] = { | |||
| 903 | &dpll4_clkdm, | 851 | &dpll4_clkdm, |
| 904 | &dpll5_clkdm, | 852 | &dpll5_clkdm, |
| 905 | #endif | 853 | #endif |
| 906 | |||
| 907 | #ifdef CONFIG_ARCH_OMAP4 | ||
| 908 | &l4_cefuse_44xx_clkdm, | ||
| 909 | &l4_cfg_44xx_clkdm, | ||
| 910 | &tesla_44xx_clkdm, | ||
| 911 | &l3_gfx_44xx_clkdm, | ||
| 912 | &ivahd_44xx_clkdm, | ||
| 913 | &l4_secure_44xx_clkdm, | ||
| 914 | &l4_per_44xx_clkdm, | ||
| 915 | &abe_44xx_clkdm, | ||
| 916 | &l3_instr_44xx_clkdm, | ||
| 917 | &l3_init_44xx_clkdm, | ||
| 918 | &mpuss_44xx_clkdm, | ||
| 919 | &mpu0_44xx_clkdm, | ||
| 920 | &mpu1_44xx_clkdm, | ||
| 921 | &l3_emif_44xx_clkdm, | ||
| 922 | &l4_ao_44xx_clkdm, | ||
| 923 | &ducati_44xx_clkdm, | ||
| 924 | &l3_2_44xx_clkdm, | ||
| 925 | &l3_1_44xx_clkdm, | ||
| 926 | &l3_d2d_44xx_clkdm, | ||
| 927 | &iss_44xx_clkdm, | ||
| 928 | &l3_dss_44xx_clkdm, | ||
| 929 | &l4_wkup_44xx_clkdm, | ||
| 930 | &emu_sys_44xx_clkdm, | ||
| 931 | &l3_dma_44xx_clkdm, | ||
| 932 | #endif | ||
| 933 | |||
| 934 | NULL, | 854 | NULL, |
| 935 | }; | 855 | }; |
| 936 | 856 | ||
| 937 | #endif | 857 | void __init omap2_clockdomains_init(void) |
| 858 | { | ||
| 859 | clkdm_init(clockdomains_omap2, clkdm_autodeps); | ||
| 860 | } | ||
diff --git a/arch/arm/mach-omap2/clockdomains44xx.h b/arch/arm/mach-omap2/clockdomains44xx_data.c index 7e5ba0f67925..51920fc7fc52 100644 --- a/arch/arm/mach-omap2/clockdomains44xx.h +++ b/arch/arm/mach-omap2/clockdomains44xx_data.c | |||
| @@ -23,18 +23,27 @@ | |||
| 23 | * -> Populate the Sleep/Wakeup dependencies for the domains | 23 | * -> Populate the Sleep/Wakeup dependencies for the domains |
| 24 | */ | 24 | */ |
| 25 | 25 | ||
| 26 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS44XX_H | 26 | #include <linux/kernel.h> |
| 27 | #define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS44XX_H | 27 | #include <linux/io.h> |
| 28 | 28 | ||
| 29 | #include <plat/clockdomain.h> | 29 | #include "clockdomain.h" |
| 30 | #include "cm1_44xx.h" | ||
| 31 | #include "cm2_44xx.h" | ||
| 32 | |||
| 33 | #include "cm1_44xx.h" | ||
| 34 | #include "cm2_44xx.h" | ||
| 35 | #include "cm-regbits-44xx.h" | ||
| 36 | #include "prm44xx.h" | ||
| 37 | #include "prcm44xx.h" | ||
| 38 | #include "prcm_mpu44xx.h" | ||
| 30 | 39 | ||
| 31 | #if defined(CONFIG_ARCH_OMAP4) | ||
| 32 | 40 | ||
| 33 | static struct clockdomain l4_cefuse_44xx_clkdm = { | 41 | static struct clockdomain l4_cefuse_44xx_clkdm = { |
| 34 | .name = "l4_cefuse_clkdm", | 42 | .name = "l4_cefuse_clkdm", |
| 35 | .pwrdm = { .name = "cefuse_pwrdm" }, | 43 | .pwrdm = { .name = "cefuse_pwrdm" }, |
| 36 | .clkstctrl_reg = OMAP4430_CM_CEFUSE_CLKSTCTRL, | 44 | .prcm_partition = OMAP4430_CM2_PARTITION, |
| 37 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | 45 | .cm_inst = OMAP4430_CM2_CEFUSE_INST, |
| 46 | .clkdm_offs = OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS, | ||
| 38 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, | 47 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, |
| 39 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 48 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 40 | }; | 49 | }; |
| @@ -42,8 +51,9 @@ static struct clockdomain l4_cefuse_44xx_clkdm = { | |||
| 42 | static struct clockdomain l4_cfg_44xx_clkdm = { | 51 | static struct clockdomain l4_cfg_44xx_clkdm = { |
| 43 | .name = "l4_cfg_clkdm", | 52 | .name = "l4_cfg_clkdm", |
| 44 | .pwrdm = { .name = "core_pwrdm" }, | 53 | .pwrdm = { .name = "core_pwrdm" }, |
| 45 | .clkstctrl_reg = OMAP4430_CM_L4CFG_CLKSTCTRL, | 54 | .prcm_partition = OMAP4430_CM2_PARTITION, |
| 46 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | 55 | .cm_inst = OMAP4430_CM2_CORE_INST, |
| 56 | .clkdm_offs = OMAP4430_CM2_CORE_L4CFG_CDOFFS, | ||
| 47 | .flags = CLKDM_CAN_HWSUP, | 57 | .flags = CLKDM_CAN_HWSUP, |
| 48 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 58 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 49 | }; | 59 | }; |
| @@ -51,8 +61,9 @@ static struct clockdomain l4_cfg_44xx_clkdm = { | |||
| 51 | static struct clockdomain tesla_44xx_clkdm = { | 61 | static struct clockdomain tesla_44xx_clkdm = { |
| 52 | .name = "tesla_clkdm", | 62 | .name = "tesla_clkdm", |
| 53 | .pwrdm = { .name = "tesla_pwrdm" }, | 63 | .pwrdm = { .name = "tesla_pwrdm" }, |
| 54 | .clkstctrl_reg = OMAP4430_CM_TESLA_CLKSTCTRL, | 64 | .prcm_partition = OMAP4430_CM1_PARTITION, |
| 55 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | 65 | .cm_inst = OMAP4430_CM1_TESLA_INST, |
| 66 | .clkdm_offs = OMAP4430_CM1_TESLA_TESLA_CDOFFS, | ||
| 56 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 67 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 57 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 68 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 58 | }; | 69 | }; |
| @@ -60,8 +71,9 @@ static struct clockdomain tesla_44xx_clkdm = { | |||
| 60 | static struct clockdomain l3_gfx_44xx_clkdm = { | 71 | static struct clockdomain l3_gfx_44xx_clkdm = { |
| 61 | .name = "l3_gfx_clkdm", | 72 | .name = "l3_gfx_clkdm", |
| 62 | .pwrdm = { .name = "gfx_pwrdm" }, | 73 | .pwrdm = { .name = "gfx_pwrdm" }, |
| 63 | .clkstctrl_reg = OMAP4430_CM_GFX_CLKSTCTRL, | 74 | .prcm_partition = OMAP4430_CM2_PARTITION, |
| 64 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | 75 | .cm_inst = OMAP4430_CM2_GFX_INST, |
| 76 | .clkdm_offs = OMAP4430_CM2_GFX_GFX_CDOFFS, | ||
| 65 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 77 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 66 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 78 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 67 | }; | 79 | }; |
| @@ -69,8 +81,9 @@ static struct clockdomain l3_gfx_44xx_clkdm = { | |||
| 69 | static struct clockdomain ivahd_44xx_clkdm = { | 81 | static struct clockdomain ivahd_44xx_clkdm = { |
| 70 | .name = "ivahd_clkdm", | 82 | .name = "ivahd_clkdm", |
| 71 | .pwrdm = { .name = "ivahd_pwrdm" }, | 83 | .pwrdm = { .name = "ivahd_pwrdm" }, |
| 72 | .clkstctrl_reg = OMAP4430_CM_IVAHD_CLKSTCTRL, | 84 | .prcm_partition = OMAP4430_CM2_PARTITION, |
| 73 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | 85 | .cm_inst = OMAP4430_CM2_IVAHD_INST, |
| 86 | .clkdm_offs = OMAP4430_CM2_IVAHD_IVAHD_CDOFFS, | ||
| 74 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 87 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 75 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 88 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 76 | }; | 89 | }; |
| @@ -78,8 +91,9 @@ static struct clockdomain ivahd_44xx_clkdm = { | |||
| 78 | static struct clockdomain l4_secure_44xx_clkdm = { | 91 | static struct clockdomain l4_secure_44xx_clkdm = { |
| 79 | .name = "l4_secure_clkdm", | 92 | .name = "l4_secure_clkdm", |
| 80 | .pwrdm = { .name = "l4per_pwrdm" }, | 93 | .pwrdm = { .name = "l4per_pwrdm" }, |
| 81 | .clkstctrl_reg = OMAP4430_CM_L4SEC_CLKSTCTRL, | 94 | .prcm_partition = OMAP4430_CM2_PARTITION, |
| 82 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | 95 | .cm_inst = OMAP4430_CM2_L4PER_INST, |
| 96 | .clkdm_offs = OMAP4430_CM2_L4PER_L4SEC_CDOFFS, | ||
| 83 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 97 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 84 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 98 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 85 | }; | 99 | }; |
| @@ -87,8 +101,9 @@ static struct clockdomain l4_secure_44xx_clkdm = { | |||
| 87 | static struct clockdomain l4_per_44xx_clkdm = { | 101 | static struct clockdomain l4_per_44xx_clkdm = { |
| 88 | .name = "l4_per_clkdm", | 102 | .name = "l4_per_clkdm", |
| 89 | .pwrdm = { .name = "l4per_pwrdm" }, | 103 | .pwrdm = { .name = "l4per_pwrdm" }, |
| 90 | .clkstctrl_reg = OMAP4430_CM_L4PER_CLKSTCTRL, | 104 | .prcm_partition = OMAP4430_CM2_PARTITION, |
| 91 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | 105 | .cm_inst = OMAP4430_CM2_L4PER_INST, |
| 106 | .clkdm_offs = OMAP4430_CM2_L4PER_L4PER_CDOFFS, | ||
| 92 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 107 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 93 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 108 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 94 | }; | 109 | }; |
| @@ -96,8 +111,9 @@ static struct clockdomain l4_per_44xx_clkdm = { | |||
| 96 | static struct clockdomain abe_44xx_clkdm = { | 111 | static struct clockdomain abe_44xx_clkdm = { |
| 97 | .name = "abe_clkdm", | 112 | .name = "abe_clkdm", |
| 98 | .pwrdm = { .name = "abe_pwrdm" }, | 113 | .pwrdm = { .name = "abe_pwrdm" }, |
| 99 | .clkstctrl_reg = OMAP4430_CM1_ABE_CLKSTCTRL, | 114 | .prcm_partition = OMAP4430_CM1_PARTITION, |
| 100 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | 115 | .cm_inst = OMAP4430_CM1_ABE_INST, |
| 116 | .clkdm_offs = OMAP4430_CM1_ABE_ABE_CDOFFS, | ||
| 101 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 117 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 102 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 118 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 103 | }; | 119 | }; |
| @@ -105,16 +121,18 @@ static struct clockdomain abe_44xx_clkdm = { | |||
| 105 | static struct clockdomain l3_instr_44xx_clkdm = { | 121 | static struct clockdomain l3_instr_44xx_clkdm = { |
| 106 | .name = "l3_instr_clkdm", | 122 | .name = "l3_instr_clkdm", |
| 107 | .pwrdm = { .name = "core_pwrdm" }, | 123 | .pwrdm = { .name = "core_pwrdm" }, |
| 108 | .clkstctrl_reg = OMAP4430_CM_L3INSTR_CLKSTCTRL, | 124 | .prcm_partition = OMAP4430_CM2_PARTITION, |
| 109 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | 125 | .cm_inst = OMAP4430_CM2_CORE_INST, |
| 126 | .clkdm_offs = OMAP4430_CM2_CORE_L3INSTR_CDOFFS, | ||
| 110 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 127 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 111 | }; | 128 | }; |
| 112 | 129 | ||
| 113 | static struct clockdomain l3_init_44xx_clkdm = { | 130 | static struct clockdomain l3_init_44xx_clkdm = { |
| 114 | .name = "l3_init_clkdm", | 131 | .name = "l3_init_clkdm", |
| 115 | .pwrdm = { .name = "l3init_pwrdm" }, | 132 | .pwrdm = { .name = "l3init_pwrdm" }, |
| 116 | .clkstctrl_reg = OMAP4430_CM_L3INIT_CLKSTCTRL, | 133 | .prcm_partition = OMAP4430_CM2_PARTITION, |
| 117 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | 134 | .cm_inst = OMAP4430_CM2_L3INIT_INST, |
| 135 | .clkdm_offs = OMAP4430_CM2_L3INIT_L3INIT_CDOFFS, | ||
| 118 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 136 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 119 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 137 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 120 | }; | 138 | }; |
| @@ -122,8 +140,9 @@ static struct clockdomain l3_init_44xx_clkdm = { | |||
| 122 | static struct clockdomain mpuss_44xx_clkdm = { | 140 | static struct clockdomain mpuss_44xx_clkdm = { |
| 123 | .name = "mpuss_clkdm", | 141 | .name = "mpuss_clkdm", |
| 124 | .pwrdm = { .name = "mpu_pwrdm" }, | 142 | .pwrdm = { .name = "mpu_pwrdm" }, |
| 125 | .clkstctrl_reg = OMAP4430_CM_MPU_CLKSTCTRL, | 143 | .prcm_partition = OMAP4430_CM1_PARTITION, |
| 126 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | 144 | .cm_inst = OMAP4430_CM1_MPU_INST, |
| 145 | .clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS, | ||
| 127 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, | 146 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, |
| 128 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 147 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 129 | }; | 148 | }; |
| @@ -131,8 +150,9 @@ static struct clockdomain mpuss_44xx_clkdm = { | |||
| 131 | static struct clockdomain mpu0_44xx_clkdm = { | 150 | static struct clockdomain mpu0_44xx_clkdm = { |
| 132 | .name = "mpu0_clkdm", | 151 | .name = "mpu0_clkdm", |
| 133 | .pwrdm = { .name = "cpu0_pwrdm" }, | 152 | .pwrdm = { .name = "cpu0_pwrdm" }, |
| 134 | .clkstctrl_reg = OMAP4430_CM_CPU0_CLKSTCTRL, | 153 | .prcm_partition = OMAP4430_PRCM_MPU_PARTITION, |
| 135 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | 154 | .cm_inst = OMAP4430_PRCM_MPU_CPU0_INST, |
| 155 | .clkdm_offs = OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS, | ||
| 136 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, | 156 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, |
| 137 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 157 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 138 | }; | 158 | }; |
| @@ -140,8 +160,9 @@ static struct clockdomain mpu0_44xx_clkdm = { | |||
| 140 | static struct clockdomain mpu1_44xx_clkdm = { | 160 | static struct clockdomain mpu1_44xx_clkdm = { |
| 141 | .name = "mpu1_clkdm", | 161 | .name = "mpu1_clkdm", |
| 142 | .pwrdm = { .name = "cpu1_pwrdm" }, | 162 | .pwrdm = { .name = "cpu1_pwrdm" }, |
| 143 | .clkstctrl_reg = OMAP4430_CM_CPU1_CLKSTCTRL, | 163 | .prcm_partition = OMAP4430_PRCM_MPU_PARTITION, |
| 144 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | 164 | .cm_inst = OMAP4430_PRCM_MPU_CPU1_INST, |
| 165 | .clkdm_offs = OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS, | ||
| 145 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, | 166 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, |
| 146 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 167 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 147 | }; | 168 | }; |
| @@ -149,8 +170,9 @@ static struct clockdomain mpu1_44xx_clkdm = { | |||
| 149 | static struct clockdomain l3_emif_44xx_clkdm = { | 170 | static struct clockdomain l3_emif_44xx_clkdm = { |
| 150 | .name = "l3_emif_clkdm", | 171 | .name = "l3_emif_clkdm", |
| 151 | .pwrdm = { .name = "core_pwrdm" }, | 172 | .pwrdm = { .name = "core_pwrdm" }, |
| 152 | .clkstctrl_reg = OMAP4430_CM_MEMIF_CLKSTCTRL, | 173 | .prcm_partition = OMAP4430_CM2_PARTITION, |
| 153 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | 174 | .cm_inst = OMAP4430_CM2_CORE_INST, |
| 175 | .clkdm_offs = OMAP4430_CM2_CORE_MEMIF_CDOFFS, | ||
| 154 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, | 176 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, |
| 155 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 177 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 156 | }; | 178 | }; |
| @@ -158,8 +180,9 @@ static struct clockdomain l3_emif_44xx_clkdm = { | |||
| 158 | static struct clockdomain l4_ao_44xx_clkdm = { | 180 | static struct clockdomain l4_ao_44xx_clkdm = { |
| 159 | .name = "l4_ao_clkdm", | 181 | .name = "l4_ao_clkdm", |
| 160 | .pwrdm = { .name = "always_on_core_pwrdm" }, | 182 | .pwrdm = { .name = "always_on_core_pwrdm" }, |
| 161 | .clkstctrl_reg = OMAP4430_CM_ALWON_CLKSTCTRL, | 183 | .prcm_partition = OMAP4430_CM2_PARTITION, |
| 162 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | 184 | .cm_inst = OMAP4430_CM2_ALWAYS_ON_INST, |
| 185 | .clkdm_offs = OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS, | ||
| 163 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, | 186 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, |
| 164 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 187 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 165 | }; | 188 | }; |
| @@ -167,8 +190,9 @@ static struct clockdomain l4_ao_44xx_clkdm = { | |||
| 167 | static struct clockdomain ducati_44xx_clkdm = { | 190 | static struct clockdomain ducati_44xx_clkdm = { |
| 168 | .name = "ducati_clkdm", | 191 | .name = "ducati_clkdm", |
| 169 | .pwrdm = { .name = "core_pwrdm" }, | 192 | .pwrdm = { .name = "core_pwrdm" }, |
| 170 | .clkstctrl_reg = OMAP4430_CM_DUCATI_CLKSTCTRL, | 193 | .prcm_partition = OMAP4430_CM2_PARTITION, |
| 171 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | 194 | .cm_inst = OMAP4430_CM2_CORE_INST, |
| 195 | .clkdm_offs = OMAP4430_CM2_CORE_DUCATI_CDOFFS, | ||
| 172 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 196 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 173 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 197 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 174 | }; | 198 | }; |
| @@ -176,8 +200,9 @@ static struct clockdomain ducati_44xx_clkdm = { | |||
| 176 | static struct clockdomain l3_2_44xx_clkdm = { | 200 | static struct clockdomain l3_2_44xx_clkdm = { |
| 177 | .name = "l3_2_clkdm", | 201 | .name = "l3_2_clkdm", |
| 178 | .pwrdm = { .name = "core_pwrdm" }, | 202 | .pwrdm = { .name = "core_pwrdm" }, |
| 179 | .clkstctrl_reg = OMAP4430_CM_L3_2_CLKSTCTRL, | 203 | .prcm_partition = OMAP4430_CM2_PARTITION, |
| 180 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | 204 | .cm_inst = OMAP4430_CM2_CORE_INST, |
| 205 | .clkdm_offs = OMAP4430_CM2_CORE_L3_2_CDOFFS, | ||
| 181 | .flags = CLKDM_CAN_HWSUP, | 206 | .flags = CLKDM_CAN_HWSUP, |
| 182 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 207 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 183 | }; | 208 | }; |
| @@ -185,8 +210,9 @@ static struct clockdomain l3_2_44xx_clkdm = { | |||
| 185 | static struct clockdomain l3_1_44xx_clkdm = { | 210 | static struct clockdomain l3_1_44xx_clkdm = { |
| 186 | .name = "l3_1_clkdm", | 211 | .name = "l3_1_clkdm", |
| 187 | .pwrdm = { .name = "core_pwrdm" }, | 212 | .pwrdm = { .name = "core_pwrdm" }, |
| 188 | .clkstctrl_reg = OMAP4430_CM_L3_1_CLKSTCTRL, | 213 | .prcm_partition = OMAP4430_CM2_PARTITION, |
| 189 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | 214 | .cm_inst = OMAP4430_CM2_CORE_INST, |
| 215 | .clkdm_offs = OMAP4430_CM2_CORE_L3_1_CDOFFS, | ||
| 190 | .flags = CLKDM_CAN_HWSUP, | 216 | .flags = CLKDM_CAN_HWSUP, |
| 191 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 217 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 192 | }; | 218 | }; |
| @@ -194,8 +220,9 @@ static struct clockdomain l3_1_44xx_clkdm = { | |||
| 194 | static struct clockdomain l3_d2d_44xx_clkdm = { | 220 | static struct clockdomain l3_d2d_44xx_clkdm = { |
| 195 | .name = "l3_d2d_clkdm", | 221 | .name = "l3_d2d_clkdm", |
| 196 | .pwrdm = { .name = "core_pwrdm" }, | 222 | .pwrdm = { .name = "core_pwrdm" }, |
| 197 | .clkstctrl_reg = OMAP4430_CM_D2D_CLKSTCTRL, | 223 | .prcm_partition = OMAP4430_CM2_PARTITION, |
| 198 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | 224 | .cm_inst = OMAP4430_CM2_CORE_INST, |
| 225 | .clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS, | ||
| 199 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, | 226 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, |
| 200 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 227 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 201 | }; | 228 | }; |
| @@ -203,8 +230,9 @@ static struct clockdomain l3_d2d_44xx_clkdm = { | |||
| 203 | static struct clockdomain iss_44xx_clkdm = { | 230 | static struct clockdomain iss_44xx_clkdm = { |
| 204 | .name = "iss_clkdm", | 231 | .name = "iss_clkdm", |
| 205 | .pwrdm = { .name = "cam_pwrdm" }, | 232 | .pwrdm = { .name = "cam_pwrdm" }, |
| 206 | .clkstctrl_reg = OMAP4430_CM_CAM_CLKSTCTRL, | 233 | .prcm_partition = OMAP4430_CM2_PARTITION, |
| 207 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | 234 | .cm_inst = OMAP4430_CM2_CAM_INST, |
| 235 | .clkdm_offs = OMAP4430_CM2_CAM_CAM_CDOFFS, | ||
| 208 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 236 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 209 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 237 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 210 | }; | 238 | }; |
| @@ -212,8 +240,9 @@ static struct clockdomain iss_44xx_clkdm = { | |||
| 212 | static struct clockdomain l3_dss_44xx_clkdm = { | 240 | static struct clockdomain l3_dss_44xx_clkdm = { |
| 213 | .name = "l3_dss_clkdm", | 241 | .name = "l3_dss_clkdm", |
| 214 | .pwrdm = { .name = "dss_pwrdm" }, | 242 | .pwrdm = { .name = "dss_pwrdm" }, |
| 215 | .clkstctrl_reg = OMAP4430_CM_DSS_CLKSTCTRL, | 243 | .prcm_partition = OMAP4430_CM2_PARTITION, |
| 216 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | 244 | .cm_inst = OMAP4430_CM2_DSS_INST, |
| 245 | .clkdm_offs = OMAP4430_CM2_DSS_DSS_CDOFFS, | ||
| 217 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 246 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 218 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 247 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 219 | }; | 248 | }; |
| @@ -221,8 +250,9 @@ static struct clockdomain l3_dss_44xx_clkdm = { | |||
| 221 | static struct clockdomain l4_wkup_44xx_clkdm = { | 250 | static struct clockdomain l4_wkup_44xx_clkdm = { |
| 222 | .name = "l4_wkup_clkdm", | 251 | .name = "l4_wkup_clkdm", |
| 223 | .pwrdm = { .name = "wkup_pwrdm" }, | 252 | .pwrdm = { .name = "wkup_pwrdm" }, |
| 224 | .clkstctrl_reg = OMAP4430_CM_WKUP_CLKSTCTRL, | 253 | .prcm_partition = OMAP4430_PRM_PARTITION, |
| 225 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | 254 | .cm_inst = OMAP4430_PRM_WKUP_CM_INST, |
| 255 | .clkdm_offs = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS, | ||
| 226 | .flags = CLKDM_CAN_HWSUP, | 256 | .flags = CLKDM_CAN_HWSUP, |
| 227 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 257 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 228 | }; | 258 | }; |
| @@ -230,8 +260,9 @@ static struct clockdomain l4_wkup_44xx_clkdm = { | |||
| 230 | static struct clockdomain emu_sys_44xx_clkdm = { | 260 | static struct clockdomain emu_sys_44xx_clkdm = { |
| 231 | .name = "emu_sys_clkdm", | 261 | .name = "emu_sys_clkdm", |
| 232 | .pwrdm = { .name = "emu_pwrdm" }, | 262 | .pwrdm = { .name = "emu_pwrdm" }, |
| 233 | .clkstctrl_reg = OMAP4430_CM_EMU_CLKSTCTRL, | 263 | .prcm_partition = OMAP4430_PRM_PARTITION, |
| 234 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | 264 | .cm_inst = OMAP4430_PRM_EMU_CM_INST, |
| 265 | .clkdm_offs = OMAP4430_PRM_EMU_CM_EMU_CDOFFS, | ||
| 235 | .flags = CLKDM_CAN_HWSUP, | 266 | .flags = CLKDM_CAN_HWSUP, |
| 236 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 267 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 237 | }; | 268 | }; |
| @@ -239,12 +270,42 @@ static struct clockdomain emu_sys_44xx_clkdm = { | |||
| 239 | static struct clockdomain l3_dma_44xx_clkdm = { | 270 | static struct clockdomain l3_dma_44xx_clkdm = { |
| 240 | .name = "l3_dma_clkdm", | 271 | .name = "l3_dma_clkdm", |
| 241 | .pwrdm = { .name = "core_pwrdm" }, | 272 | .pwrdm = { .name = "core_pwrdm" }, |
| 242 | .clkstctrl_reg = OMAP4430_CM_SDMA_CLKSTCTRL, | 273 | .prcm_partition = OMAP4430_CM2_PARTITION, |
| 243 | .clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK, | 274 | .cm_inst = OMAP4430_CM2_CORE_INST, |
| 275 | .clkdm_offs = OMAP4430_CM2_CORE_SDMA_CDOFFS, | ||
| 244 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, | 276 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, |
| 245 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 277 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 246 | }; | 278 | }; |
| 247 | 279 | ||
| 248 | #endif | 280 | static struct clockdomain *clockdomains_omap44xx[] __initdata = { |
| 281 | &l4_cefuse_44xx_clkdm, | ||
| 282 | &l4_cfg_44xx_clkdm, | ||
| 283 | &tesla_44xx_clkdm, | ||
| 284 | &l3_gfx_44xx_clkdm, | ||
| 285 | &ivahd_44xx_clkdm, | ||
| 286 | &l4_secure_44xx_clkdm, | ||
| 287 | &l4_per_44xx_clkdm, | ||
| 288 | &abe_44xx_clkdm, | ||
| 289 | &l3_instr_44xx_clkdm, | ||
| 290 | &l3_init_44xx_clkdm, | ||
| 291 | &mpuss_44xx_clkdm, | ||
| 292 | &mpu0_44xx_clkdm, | ||
| 293 | &mpu1_44xx_clkdm, | ||
| 294 | &l3_emif_44xx_clkdm, | ||
| 295 | &l4_ao_44xx_clkdm, | ||
| 296 | &ducati_44xx_clkdm, | ||
| 297 | &l3_2_44xx_clkdm, | ||
| 298 | &l3_1_44xx_clkdm, | ||
| 299 | &l3_d2d_44xx_clkdm, | ||
| 300 | &iss_44xx_clkdm, | ||
| 301 | &l3_dss_44xx_clkdm, | ||
| 302 | &l4_wkup_44xx_clkdm, | ||
| 303 | &emu_sys_44xx_clkdm, | ||
| 304 | &l3_dma_44xx_clkdm, | ||
| 305 | NULL, | ||
| 306 | }; | ||
| 249 | 307 | ||
| 250 | #endif | 308 | void __init omap44xx_clockdomains_init(void) |
| 309 | { | ||
| 310 | clkdm_init(clockdomains_omap44xx, NULL); | ||
| 311 | } | ||
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h index da51cc3ed7eb..d70660e82fe6 100644 --- a/arch/arm/mach-omap2/cm-regbits-24xx.h +++ b/arch/arm/mach-omap2/cm-regbits-24xx.h | |||
| @@ -14,8 +14,6 @@ | |||
| 14 | * published by the Free Software Foundation. | 14 | * published by the Free Software Foundation. |
| 15 | */ | 15 | */ |
| 16 | 16 | ||
| 17 | #include "cm.h" | ||
| 18 | |||
| 19 | /* Bits shared between registers */ | 17 | /* Bits shared between registers */ |
| 20 | 18 | ||
| 21 | /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ | 19 | /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ |
| @@ -126,8 +124,12 @@ | |||
| 126 | #define OMAP24XX_ST_HDQ_MASK (1 << 23) | 124 | #define OMAP24XX_ST_HDQ_MASK (1 << 23) |
| 127 | #define OMAP2420_ST_I2C2_SHIFT 20 | 125 | #define OMAP2420_ST_I2C2_SHIFT 20 |
| 128 | #define OMAP2420_ST_I2C2_MASK (1 << 20) | 126 | #define OMAP2420_ST_I2C2_MASK (1 << 20) |
| 127 | #define OMAP2430_ST_I2CHS1_SHIFT 19 | ||
| 128 | #define OMAP2430_ST_I2CHS1_MASK (1 << 19) | ||
| 129 | #define OMAP2420_ST_I2C1_SHIFT 19 | 129 | #define OMAP2420_ST_I2C1_SHIFT 19 |
| 130 | #define OMAP2420_ST_I2C1_MASK (1 << 19) | 130 | #define OMAP2420_ST_I2C1_MASK (1 << 19) |
| 131 | #define OMAP2430_ST_I2CHS2_SHIFT 20 | ||
| 132 | #define OMAP2430_ST_I2CHS2_MASK (1 << 20) | ||
| 131 | #define OMAP24XX_ST_MCBSP2_SHIFT 16 | 133 | #define OMAP24XX_ST_MCBSP2_SHIFT 16 |
| 132 | #define OMAP24XX_ST_MCBSP2_MASK (1 << 16) | 134 | #define OMAP24XX_ST_MCBSP2_MASK (1 << 16) |
| 133 | #define OMAP24XX_ST_MCBSP1_SHIFT 15 | 135 | #define OMAP24XX_ST_MCBSP1_SHIFT 15 |
| @@ -432,4 +434,9 @@ | |||
| 432 | #define OMAP2430_AUTOSTATE_MDM_SHIFT 0 | 434 | #define OMAP2430_AUTOSTATE_MDM_SHIFT 0 |
| 433 | #define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0) | 435 | #define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0) |
| 434 | 436 | ||
| 437 | /* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */ | ||
| 438 | #define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0 | ||
| 439 | #define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1 | ||
| 440 | |||
| 441 | |||
| 435 | #endif | 442 | #endif |
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index 4f959a7d881c..b91275908f33 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h | |||
| @@ -14,8 +14,6 @@ | |||
| 14 | * published by the Free Software Foundation. | 14 | * published by the Free Software Foundation. |
| 15 | */ | 15 | */ |
| 16 | 16 | ||
| 17 | #include "cm.h" | ||
| 18 | |||
| 19 | /* Bits shared between registers */ | 17 | /* Bits shared between registers */ |
| 20 | 18 | ||
| 21 | /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ | 19 | /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ |
| @@ -800,4 +798,15 @@ | |||
| 800 | #define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0 | 798 | #define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0 |
| 801 | #define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0) | 799 | #define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0) |
| 802 | 800 | ||
| 801 | /* | ||
| 802 | * | ||
| 803 | */ | ||
| 804 | |||
| 805 | /* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */ | ||
| 806 | #define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0 | ||
| 807 | #define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1 | ||
| 808 | #define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2 | ||
| 809 | #define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3 | ||
| 810 | |||
| 811 | |||
| 803 | #endif | 812 | #endif |
diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h index 0b72be433776..9d47a05b17b4 100644 --- a/arch/arm/mach-omap2/cm-regbits-44xx.h +++ b/arch/arm/mach-omap2/cm-regbits-44xx.h | |||
| @@ -22,9 +22,6 @@ | |||
| 22 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H | 22 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H |
| 23 | #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H | 23 | #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H |
| 24 | 24 | ||
| 25 | #include "cm.h" | ||
| 26 | |||
| 27 | |||
| 28 | /* | 25 | /* |
| 29 | * Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, | 26 | * Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, |
| 30 | * CM_TESLA_DYNAMICDEP | 27 | * CM_TESLA_DYNAMICDEP |
diff --git a/arch/arm/mach-omap2/cm.c b/arch/arm/mach-omap2/cm.c deleted file mode 100644 index 721c3b66740a..000000000000 --- a/arch/arm/mach-omap2/cm.c +++ /dev/null | |||
| @@ -1,68 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * OMAP2/3 CM module functions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Nokia Corporation | ||
| 5 | * Paul Walmsley | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/module.h> | ||
| 14 | #include <linux/types.h> | ||
| 15 | #include <linux/delay.h> | ||
| 16 | #include <linux/spinlock.h> | ||
| 17 | #include <linux/list.h> | ||
| 18 | #include <linux/errno.h> | ||
| 19 | #include <linux/err.h> | ||
| 20 | #include <linux/io.h> | ||
| 21 | |||
| 22 | #include <asm/atomic.h> | ||
| 23 | |||
| 24 | #include <plat/common.h> | ||
| 25 | |||
| 26 | #include "cm.h" | ||
| 27 | #include "cm-regbits-24xx.h" | ||
| 28 | #include "cm-regbits-34xx.h" | ||
| 29 | |||
| 30 | static const u8 cm_idlest_offs[] = { | ||
| 31 | CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3 | ||
| 32 | }; | ||
| 33 | |||
| 34 | /** | ||
| 35 | * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby | ||
| 36 | * @prcm_mod: PRCM module offset | ||
| 37 | * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3) | ||
| 38 | * @idlest_shift: shift of the bit in the CM_IDLEST* register to check | ||
| 39 | * | ||
| 40 | * XXX document | ||
| 41 | */ | ||
| 42 | int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift) | ||
| 43 | { | ||
| 44 | int ena = 0, i = 0; | ||
| 45 | u8 cm_idlest_reg; | ||
| 46 | u32 mask; | ||
| 47 | |||
| 48 | if (!idlest_id || (idlest_id > ARRAY_SIZE(cm_idlest_offs))) | ||
| 49 | return -EINVAL; | ||
| 50 | |||
| 51 | cm_idlest_reg = cm_idlest_offs[idlest_id - 1]; | ||
| 52 | |||
| 53 | mask = 1 << idlest_shift; | ||
| 54 | |||
| 55 | if (cpu_is_omap24xx()) | ||
| 56 | ena = mask; | ||
| 57 | else if (cpu_is_omap34xx()) | ||
| 58 | ena = 0; | ||
| 59 | else | ||
| 60 | BUG(); | ||
| 61 | |||
| 62 | /* XXX should be OMAP2 CM */ | ||
| 63 | omap_test_timeout(((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena), | ||
| 64 | MAX_MODULE_READY_TIME, i); | ||
| 65 | |||
| 66 | return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; | ||
| 67 | } | ||
| 68 | |||
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h index a02ca30423dc..a7bc096bd407 100644 --- a/arch/arm/mach-omap2/cm.h +++ b/arch/arm/mach-omap2/cm.h | |||
| @@ -1,8 +1,5 @@ | |||
| 1 | #ifndef __ARCH_ASM_MACH_OMAP2_CM_H | ||
| 2 | #define __ARCH_ASM_MACH_OMAP2_CM_H | ||
| 3 | |||
| 4 | /* | 1 | /* |
| 5 | * OMAP2/3 Clock Management (CM) register definitions | 2 | * OMAP2+ Clock Management prototypes |
| 6 | * | 3 | * |
| 7 | * Copyright (C) 2007-2009 Texas Instruments, Inc. | 4 | * Copyright (C) 2007-2009 Texas Instruments, Inc. |
| 8 | * Copyright (C) 2007-2009 Nokia Corporation | 5 | * Copyright (C) 2007-2009 Nokia Corporation |
| @@ -13,136 +10,8 @@ | |||
| 13 | * it under the terms of the GNU General Public License version 2 as | 10 | * it under the terms of the GNU General Public License version 2 as |
| 14 | * published by the Free Software Foundation. | 11 | * published by the Free Software Foundation. |
| 15 | */ | 12 | */ |
| 16 | 13 | #ifndef __ARCH_ASM_MACH_OMAP2_CM_H | |
| 17 | #include "prcm-common.h" | 14 | #define __ARCH_ASM_MACH_OMAP2_CM_H |
| 18 | |||
| 19 | #define OMAP2420_CM_REGADDR(module, reg) \ | ||
| 20 | OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) | ||
| 21 | #define OMAP2430_CM_REGADDR(module, reg) \ | ||
| 22 | OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) | ||
| 23 | #define OMAP34XX_CM_REGADDR(module, reg) \ | ||
| 24 | OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) | ||
| 25 | #define OMAP44XX_CM1_REGADDR(module, reg) \ | ||
| 26 | OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (module) + (reg)) | ||
| 27 | #define OMAP44XX_CM2_REGADDR(module, reg) \ | ||
| 28 | OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (module) + (reg)) | ||
| 29 | |||
| 30 | #include "cm44xx.h" | ||
| 31 | |||
| 32 | /* | ||
| 33 | * Architecture-specific global CM registers | ||
| 34 | * Use cm_{read,write}_reg() with these registers. | ||
| 35 | * These registers appear once per CM module. | ||
| 36 | */ | ||
| 37 | |||
| 38 | #define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000) | ||
| 39 | #define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010) | ||
| 40 | #define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c) | ||
| 41 | |||
| 42 | #define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070 | ||
| 43 | #define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070) | ||
| 44 | |||
| 45 | /* | ||
| 46 | * Module specific CM registers from CM_BASE + domain offset | ||
| 47 | * Use cm_{read,write}_mod_reg() with these registers. | ||
| 48 | * These register offsets generally appear in more than one PRCM submodule. | ||
| 49 | */ | ||
| 50 | |||
| 51 | /* Common between 24xx and 34xx */ | ||
| 52 | |||
| 53 | #define CM_FCLKEN 0x0000 | ||
| 54 | #define CM_FCLKEN1 CM_FCLKEN | ||
| 55 | #define CM_CLKEN CM_FCLKEN | ||
| 56 | #define CM_ICLKEN 0x0010 | ||
| 57 | #define CM_ICLKEN1 CM_ICLKEN | ||
| 58 | #define CM_ICLKEN2 0x0014 | ||
| 59 | #define CM_ICLKEN3 0x0018 | ||
| 60 | #define CM_IDLEST 0x0020 | ||
| 61 | #define CM_IDLEST1 CM_IDLEST | ||
| 62 | #define CM_IDLEST2 0x0024 | ||
| 63 | #define CM_AUTOIDLE 0x0030 | ||
| 64 | #define CM_AUTOIDLE1 CM_AUTOIDLE | ||
| 65 | #define CM_AUTOIDLE2 0x0034 | ||
| 66 | #define CM_AUTOIDLE3 0x0038 | ||
| 67 | #define CM_CLKSEL 0x0040 | ||
| 68 | #define CM_CLKSEL1 CM_CLKSEL | ||
| 69 | #define CM_CLKSEL2 0x0044 | ||
| 70 | #define OMAP2_CM_CLKSTCTRL 0x0048 | ||
| 71 | #define OMAP4_CM_CLKSTCTRL 0x0000 | ||
| 72 | |||
| 73 | |||
| 74 | /* Architecture-specific registers */ | ||
| 75 | |||
| 76 | #define OMAP24XX_CM_FCLKEN2 0x0004 | ||
| 77 | #define OMAP24XX_CM_ICLKEN4 0x001c | ||
| 78 | #define OMAP24XX_CM_AUTOIDLE4 0x003c | ||
| 79 | |||
| 80 | #define OMAP2430_CM_IDLEST3 0x0028 | ||
| 81 | |||
| 82 | #define OMAP3430_CM_CLKEN_PLL 0x0004 | ||
| 83 | #define OMAP3430ES2_CM_CLKEN2 0x0004 | ||
| 84 | #define OMAP3430ES2_CM_FCLKEN3 0x0008 | ||
| 85 | #define OMAP3430_CM_IDLEST_PLL CM_IDLEST2 | ||
| 86 | #define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2 | ||
| 87 | #define OMAP3430ES2_CM_AUTOIDLE2_PLL CM_AUTOIDLE2 | ||
| 88 | #define OMAP3430_CM_CLKSEL1 CM_CLKSEL | ||
| 89 | #define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL | ||
| 90 | #define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2 | ||
| 91 | #define OMAP3430_CM_SLEEPDEP CM_CLKSEL2 | ||
| 92 | #define OMAP3430_CM_CLKSEL3 OMAP2_CM_CLKSTCTRL | ||
| 93 | #define OMAP3430_CM_CLKSTST 0x004c | ||
| 94 | #define OMAP3430ES2_CM_CLKSEL4 0x004c | ||
| 95 | #define OMAP3430ES2_CM_CLKSEL5 0x0050 | ||
| 96 | #define OMAP3430_CM_CLKSEL2_EMU 0x0050 | ||
| 97 | #define OMAP3430_CM_CLKSEL3_EMU 0x0054 | ||
| 98 | |||
| 99 | /* CM2.CEFUSE_CM2 register offsets */ | ||
| 100 | |||
| 101 | /* OMAP4 modulemode control */ | ||
| 102 | #define OMAP4430_MODULEMODE_HWCTRL 0 | ||
| 103 | #define OMAP4430_MODULEMODE_SWCTRL 1 | ||
| 104 | |||
| 105 | /* Clock management domain register get/set */ | ||
| 106 | |||
| 107 | #ifndef __ASSEMBLER__ | ||
| 108 | |||
| 109 | extern u32 cm_read_mod_reg(s16 module, u16 idx); | ||
| 110 | extern void cm_write_mod_reg(u32 val, s16 module, u16 idx); | ||
| 111 | extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); | ||
| 112 | |||
| 113 | extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, | ||
| 114 | u8 idlest_shift); | ||
| 115 | extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg); | ||
| 116 | |||
| 117 | static inline u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) | ||
| 118 | { | ||
| 119 | return cm_rmw_mod_reg_bits(bits, bits, module, idx); | ||
| 120 | } | ||
| 121 | |||
| 122 | static inline u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) | ||
| 123 | { | ||
| 124 | return cm_rmw_mod_reg_bits(bits, 0x0, module, idx); | ||
| 125 | } | ||
| 126 | |||
| 127 | #endif | ||
| 128 | |||
| 129 | /* CM register bits shared between 24XX and 3430 */ | ||
| 130 | |||
| 131 | /* CM_CLKSEL_GFX */ | ||
| 132 | #define OMAP_CLKSEL_GFX_SHIFT 0 | ||
| 133 | #define OMAP_CLKSEL_GFX_MASK (0x7 << 0) | ||
| 134 | |||
| 135 | /* CM_ICLKEN_GFX */ | ||
| 136 | #define OMAP_EN_GFX_SHIFT 0 | ||
| 137 | #define OMAP_EN_GFX_MASK (1 << 0) | ||
| 138 | |||
| 139 | /* CM_IDLEST_GFX */ | ||
| 140 | #define OMAP_ST_GFX_MASK (1 << 0) | ||
| 141 | |||
| 142 | |||
| 143 | /* CM_IDLEST indicator */ | ||
| 144 | #define OMAP24XX_CM_IDLEST_VAL 0 | ||
| 145 | #define OMAP34XX_CM_IDLEST_VAL 1 | ||
| 146 | 15 | ||
| 147 | /* | 16 | /* |
| 148 | * MAX_MODULE_READY_TIME: max duration in microseconds to wait for the | 17 | * MAX_MODULE_READY_TIME: max duration in microseconds to wait for the |
diff --git a/arch/arm/mach-omap2/cm1_44xx.h b/arch/arm/mach-omap2/cm1_44xx.h new file mode 100644 index 000000000000..e2d7a56b2ad6 --- /dev/null +++ b/arch/arm/mach-omap2/cm1_44xx.h | |||
| @@ -0,0 +1,261 @@ | |||
| 1 | /* | ||
| 2 | * OMAP44xx CM1 instance offset macros | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2009-2010 Nokia Corporation | ||
| 6 | * | ||
| 7 | * Paul Walmsley (paul@pwsan.com) | ||
| 8 | * Rajendra Nayak (rnayak@ti.com) | ||
| 9 | * Benoit Cousson (b-cousson@ti.com) | ||
| 10 | * | ||
| 11 | * This file is automatically generated from the OMAP hardware databases. | ||
| 12 | * We respectfully ask that any modifications to this file be coordinated | ||
| 13 | * with the public linux-omap@vger.kernel.org mailing list and the | ||
| 14 | * authors above to ensure that the autogeneration scripts are kept | ||
| 15 | * up-to-date with the file contents. | ||
| 16 | * | ||
| 17 | * This program is free software; you can redistribute it and/or modify | ||
| 18 | * it under the terms of the GNU General Public License version 2 as | ||
| 19 | * published by the Free Software Foundation. | ||
| 20 | * | ||
| 21 | * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX", | ||
| 22 | * or "OMAP4430". | ||
| 23 | */ | ||
| 24 | |||
| 25 | #ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H | ||
| 26 | #define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H | ||
| 27 | |||
| 28 | /* CM1 base address */ | ||
| 29 | #define OMAP4430_CM1_BASE 0x4a004000 | ||
| 30 | |||
| 31 | #define OMAP44XX_CM1_REGADDR(inst, reg) \ | ||
| 32 | OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (inst) + (reg)) | ||
| 33 | |||
| 34 | /* CM1 instances */ | ||
| 35 | #define OMAP4430_CM1_OCP_SOCKET_INST 0x0000 | ||
| 36 | #define OMAP4430_CM1_CKGEN_INST 0x0100 | ||
| 37 | #define OMAP4430_CM1_MPU_INST 0x0300 | ||
| 38 | #define OMAP4430_CM1_TESLA_INST 0x0400 | ||
| 39 | #define OMAP4430_CM1_ABE_INST 0x0500 | ||
| 40 | #define OMAP4430_CM1_RESTORE_INST 0x0e00 | ||
| 41 | #define OMAP4430_CM1_INSTR_INST 0x0f00 | ||
| 42 | |||
| 43 | /* CM1 clockdomain register offsets (from instance start) */ | ||
| 44 | #define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000 | ||
| 45 | #define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000 | ||
| 46 | #define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000 | ||
| 47 | |||
| 48 | /* CM1 */ | ||
| 49 | |||
| 50 | /* CM1.OCP_SOCKET_CM1 register offsets */ | ||
| 51 | #define OMAP4_REVISION_CM1_OFFSET 0x0000 | ||
| 52 | #define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0000) | ||
| 53 | #define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET 0x0040 | ||
| 54 | #define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0040) | ||
| 55 | |||
| 56 | /* CM1.CKGEN_CM1 register offsets */ | ||
| 57 | #define OMAP4_CM_CLKSEL_CORE_OFFSET 0x0000 | ||
| 58 | #define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0000) | ||
| 59 | #define OMAP4_CM_CLKSEL_ABE_OFFSET 0x0008 | ||
| 60 | #define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0008) | ||
| 61 | #define OMAP4_CM_DLL_CTRL_OFFSET 0x0010 | ||
| 62 | #define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0010) | ||
| 63 | #define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020 | ||
| 64 | #define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0020) | ||
| 65 | #define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET 0x0024 | ||
| 66 | #define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0024) | ||
| 67 | #define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028 | ||
| 68 | #define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0028) | ||
| 69 | #define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c | ||
| 70 | #define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x002c) | ||
| 71 | #define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030 | ||
| 72 | #define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0030) | ||
| 73 | #define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034 | ||
| 74 | #define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0034) | ||
| 75 | #define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET 0x0038 | ||
| 76 | #define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0038) | ||
| 77 | #define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET 0x003c | ||
| 78 | #define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x003c) | ||
| 79 | #define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET 0x0040 | ||
| 80 | #define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0040) | ||
| 81 | #define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET 0x0044 | ||
| 82 | #define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044) | ||
| 83 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048 | ||
| 84 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048) | ||
| 85 | #define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_OFFSET 0x004c | ||
| 86 | #define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c) | ||
| 87 | #define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050 | ||
| 88 | #define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050) | ||
| 89 | #define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060 | ||
| 90 | #define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0060) | ||
| 91 | #define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET 0x0064 | ||
| 92 | #define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0064) | ||
| 93 | #define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068 | ||
| 94 | #define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0068) | ||
| 95 | #define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c | ||
| 96 | #define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x006c) | ||
| 97 | #define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070 | ||
| 98 | #define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070) | ||
| 99 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088 | ||
| 100 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088) | ||
| 101 | #define OMAP4_CM_SSC_INSTFREQDIV_DPLL_MPU_OFFSET 0x008c | ||
| 102 | #define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c) | ||
| 103 | #define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c | ||
| 104 | #define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c) | ||
| 105 | #define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0 | ||
| 106 | #define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a0) | ||
| 107 | #define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4 | ||
| 108 | #define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a4) | ||
| 109 | #define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8 | ||
| 110 | #define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a8) | ||
| 111 | #define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac | ||
| 112 | #define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ac) | ||
| 113 | #define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET 0x00b8 | ||
| 114 | #define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00b8) | ||
| 115 | #define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET 0x00bc | ||
| 116 | #define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc) | ||
| 117 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8 | ||
| 118 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8) | ||
| 119 | #define OMAP4_CM_SSC_INSTFREQDIV_DPLL_IVA_OFFSET 0x00cc | ||
| 120 | #define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc) | ||
| 121 | #define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc | ||
| 122 | #define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc) | ||
| 123 | #define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0 | ||
| 124 | #define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e0) | ||
| 125 | #define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4 | ||
| 126 | #define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e4) | ||
| 127 | #define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8 | ||
| 128 | #define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e8) | ||
| 129 | #define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec | ||
| 130 | #define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ec) | ||
| 131 | #define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0 | ||
| 132 | #define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f0) | ||
| 133 | #define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4 | ||
| 134 | #define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4) | ||
| 135 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108 | ||
| 136 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108) | ||
| 137 | #define OMAP4_CM_SSC_INSTFREQDIV_DPLL_ABE_OFFSET 0x010c | ||
| 138 | #define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c) | ||
| 139 | #define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120 | ||
| 140 | #define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120) | ||
| 141 | #define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124 | ||
| 142 | #define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0124) | ||
| 143 | #define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET 0x0128 | ||
| 144 | #define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0128) | ||
| 145 | #define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET 0x012c | ||
| 146 | #define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x012c) | ||
| 147 | #define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET 0x0130 | ||
| 148 | #define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0130) | ||
| 149 | #define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET 0x0138 | ||
| 150 | #define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0138) | ||
| 151 | #define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET 0x013c | ||
| 152 | #define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x013c) | ||
| 153 | #define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET 0x0140 | ||
| 154 | #define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140) | ||
| 155 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148 | ||
| 156 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148) | ||
| 157 | #define OMAP4_CM_SSC_INSTFREQDIV_DPLL_DDRPHY_OFFSET 0x014c | ||
| 158 | #define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c) | ||
| 159 | #define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160 | ||
| 160 | #define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160) | ||
| 161 | #define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164 | ||
| 162 | #define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0164) | ||
| 163 | #define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET 0x0170 | ||
| 164 | #define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0170) | ||
| 165 | #define OMAP4_CM_RESTORE_ST_OFFSET 0x0180 | ||
| 166 | #define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0180) | ||
| 167 | |||
| 168 | /* CM1.MPU_CM1 register offsets */ | ||
| 169 | #define OMAP4_CM_MPU_CLKSTCTRL_OFFSET 0x0000 | ||
| 170 | #define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0000) | ||
| 171 | #define OMAP4_CM_MPU_STATICDEP_OFFSET 0x0004 | ||
| 172 | #define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0004) | ||
| 173 | #define OMAP4_CM_MPU_DYNAMICDEP_OFFSET 0x0008 | ||
| 174 | #define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0008) | ||
| 175 | #define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 | ||
| 176 | #define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0020) | ||
| 177 | |||
| 178 | /* CM1.TESLA_CM1 register offsets */ | ||
| 179 | #define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET 0x0000 | ||
| 180 | #define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0000) | ||
| 181 | #define OMAP4_CM_TESLA_STATICDEP_OFFSET 0x0004 | ||
| 182 | #define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0004) | ||
| 183 | #define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET 0x0008 | ||
| 184 | #define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0008) | ||
| 185 | #define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET 0x0020 | ||
| 186 | #define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0020) | ||
| 187 | |||
| 188 | /* CM1.ABE_CM1 register offsets */ | ||
| 189 | #define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET 0x0000 | ||
| 190 | #define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0000) | ||
| 191 | #define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET 0x0020 | ||
| 192 | #define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0020) | ||
| 193 | #define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET 0x0028 | ||
| 194 | #define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0028) | ||
| 195 | #define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET 0x0030 | ||
| 196 | #define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0030) | ||
| 197 | #define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET 0x0038 | ||
| 198 | #define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0038) | ||
| 199 | #define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET 0x0040 | ||
| 200 | #define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0040) | ||
| 201 | #define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048 | ||
| 202 | #define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0048) | ||
| 203 | #define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050 | ||
| 204 | #define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0050) | ||
| 205 | #define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058 | ||
| 206 | #define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0058) | ||
| 207 | #define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET 0x0060 | ||
| 208 | #define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0060) | ||
| 209 | #define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET 0x0068 | ||
| 210 | #define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0068) | ||
| 211 | #define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET 0x0070 | ||
| 212 | #define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0070) | ||
| 213 | #define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET 0x0078 | ||
| 214 | #define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0078) | ||
| 215 | #define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET 0x0080 | ||
| 216 | #define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0080) | ||
| 217 | #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 | ||
| 218 | #define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088) | ||
| 219 | |||
| 220 | /* CM1.RESTORE_CM1 register offsets */ | ||
| 221 | #define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET 0x0000 | ||
| 222 | #define OMAP4430_CM_CLKSEL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0000) | ||
| 223 | #define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET 0x0004 | ||
| 224 | #define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0004) | ||
| 225 | #define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET 0x0008 | ||
| 226 | #define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0008) | ||
| 227 | #define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET 0x000c | ||
| 228 | #define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x000c) | ||
| 229 | #define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET 0x0010 | ||
| 230 | #define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0010) | ||
| 231 | #define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET 0x0014 | ||
| 232 | #define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0014) | ||
| 233 | #define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET 0x0018 | ||
| 234 | #define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0018) | ||
| 235 | #define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET 0x001c | ||
| 236 | #define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x001c) | ||
| 237 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET 0x0020 | ||
| 238 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0020) | ||
| 239 | #define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE_OFFSET 0x0024 | ||
| 240 | #define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0024) | ||
| 241 | #define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET 0x0028 | ||
| 242 | #define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0028) | ||
| 243 | #define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET 0x002c | ||
| 244 | #define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x002c) | ||
| 245 | #define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET 0x0030 | ||
| 246 | #define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0030) | ||
| 247 | #define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET 0x0034 | ||
| 248 | #define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0034) | ||
| 249 | #define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET 0x0038 | ||
| 250 | #define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0038) | ||
| 251 | #define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET 0x003c | ||
| 252 | #define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x003c) | ||
| 253 | #define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET 0x0040 | ||
| 254 | #define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0040) | ||
| 255 | |||
| 256 | /* Function prototypes */ | ||
| 257 | extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx); | ||
| 258 | extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx); | ||
| 259 | extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); | ||
| 260 | |||
| 261 | #endif | ||
diff --git a/arch/arm/mach-omap2/cm2_44xx.h b/arch/arm/mach-omap2/cm2_44xx.h new file mode 100644 index 000000000000..aa4745044065 --- /dev/null +++ b/arch/arm/mach-omap2/cm2_44xx.h | |||
| @@ -0,0 +1,508 @@ | |||
| 1 | /* | ||
| 2 | * OMAP44xx CM2 instance offset macros | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2009-2010 Nokia Corporation | ||
| 6 | * | ||
| 7 | * Paul Walmsley (paul@pwsan.com) | ||
| 8 | * Rajendra Nayak (rnayak@ti.com) | ||
| 9 | * Benoit Cousson (b-cousson@ti.com) | ||
| 10 | * | ||
| 11 | * This file is automatically generated from the OMAP hardware databases. | ||
| 12 | * We respectfully ask that any modifications to this file be coordinated | ||
| 13 | * with the public linux-omap@vger.kernel.org mailing list and the | ||
| 14 | * authors above to ensure that the autogeneration scripts are kept | ||
| 15 | * up-to-date with the file contents. | ||
| 16 | * | ||
| 17 | * This program is free software; you can redistribute it and/or modify | ||
| 18 | * it under the terms of the GNU General Public License version 2 as | ||
| 19 | * published by the Free Software Foundation. | ||
| 20 | * | ||
| 21 | * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX", | ||
| 22 | * or "OMAP4430". | ||
| 23 | */ | ||
| 24 | |||
| 25 | #ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H | ||
| 26 | #define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H | ||
| 27 | |||
| 28 | /* CM2 base address */ | ||
| 29 | #define OMAP4430_CM2_BASE 0x4a008000 | ||
| 30 | |||
| 31 | #define OMAP44XX_CM2_REGADDR(inst, reg) \ | ||
| 32 | OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (inst) + (reg)) | ||
| 33 | |||
| 34 | /* CM2 instances */ | ||
| 35 | #define OMAP4430_CM2_OCP_SOCKET_INST 0x0000 | ||
| 36 | #define OMAP4430_CM2_CKGEN_INST 0x0100 | ||
| 37 | #define OMAP4430_CM2_ALWAYS_ON_INST 0x0600 | ||
| 38 | #define OMAP4430_CM2_CORE_INST 0x0700 | ||
| 39 | #define OMAP4430_CM2_IVAHD_INST 0x0f00 | ||
| 40 | #define OMAP4430_CM2_CAM_INST 0x1000 | ||
| 41 | #define OMAP4430_CM2_DSS_INST 0x1100 | ||
| 42 | #define OMAP4430_CM2_GFX_INST 0x1200 | ||
| 43 | #define OMAP4430_CM2_L3INIT_INST 0x1300 | ||
| 44 | #define OMAP4430_CM2_L4PER_INST 0x1400 | ||
| 45 | #define OMAP4430_CM2_CEFUSE_INST 0x1600 | ||
| 46 | #define OMAP4430_CM2_RESTORE_INST 0x1e00 | ||
| 47 | #define OMAP4430_CM2_INSTR_INST 0x1f00 | ||
| 48 | |||
| 49 | /* CM2 clockdomain register offsets (from instance start) */ | ||
| 50 | #define OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS 0x0000 | ||
| 51 | #define OMAP4430_CM2_CORE_L3_1_CDOFFS 0x0000 | ||
| 52 | #define OMAP4430_CM2_CORE_L3_2_CDOFFS 0x0100 | ||
| 53 | #define OMAP4430_CM2_CORE_DUCATI_CDOFFS 0x0200 | ||
| 54 | #define OMAP4430_CM2_CORE_SDMA_CDOFFS 0x0300 | ||
| 55 | #define OMAP4430_CM2_CORE_MEMIF_CDOFFS 0x0400 | ||
| 56 | #define OMAP4430_CM2_CORE_D2D_CDOFFS 0x0500 | ||
| 57 | #define OMAP4430_CM2_CORE_L4CFG_CDOFFS 0x0600 | ||
| 58 | #define OMAP4430_CM2_CORE_L3INSTR_CDOFFS 0x0700 | ||
| 59 | #define OMAP4430_CM2_IVAHD_IVAHD_CDOFFS 0x0000 | ||
| 60 | #define OMAP4430_CM2_CAM_CAM_CDOFFS 0x0000 | ||
| 61 | #define OMAP4430_CM2_DSS_DSS_CDOFFS 0x0000 | ||
| 62 | #define OMAP4430_CM2_GFX_GFX_CDOFFS 0x0000 | ||
| 63 | #define OMAP4430_CM2_L3INIT_L3INIT_CDOFFS 0x0000 | ||
| 64 | #define OMAP4430_CM2_L4PER_L4PER_CDOFFS 0x0000 | ||
| 65 | #define OMAP4430_CM2_L4PER_L4SEC_CDOFFS 0x0180 | ||
| 66 | #define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS 0x0000 | ||
| 67 | |||
| 68 | |||
| 69 | /* CM2 */ | ||
| 70 | |||
| 71 | /* CM2.OCP_SOCKET_CM2 register offsets */ | ||
| 72 | #define OMAP4_REVISION_CM2_OFFSET 0x0000 | ||
| 73 | #define OMAP4430_REVISION_CM2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0000) | ||
| 74 | #define OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET 0x0040 | ||
| 75 | #define OMAP4430_CM_CM2_PROFILING_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0040) | ||
| 76 | |||
| 77 | /* CM2.CKGEN_CM2 register offsets */ | ||
| 78 | #define OMAP4_CM_CLKSEL_DUCATI_ISS_ROOT_OFFSET 0x0000 | ||
| 79 | #define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0000) | ||
| 80 | #define OMAP4_CM_CLKSEL_USB_60MHZ_OFFSET 0x0004 | ||
| 81 | #define OMAP4430_CM_CLKSEL_USB_60MHZ OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0004) | ||
| 82 | #define OMAP4_CM_SCALE_FCLK_OFFSET 0x0008 | ||
| 83 | #define OMAP4430_CM_SCALE_FCLK OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0008) | ||
| 84 | #define OMAP4_CM_CORE_DVFS_PERF1_OFFSET 0x0010 | ||
| 85 | #define OMAP4430_CM_CORE_DVFS_PERF1 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0010) | ||
| 86 | #define OMAP4_CM_CORE_DVFS_PERF2_OFFSET 0x0014 | ||
| 87 | #define OMAP4430_CM_CORE_DVFS_PERF2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0014) | ||
| 88 | #define OMAP4_CM_CORE_DVFS_PERF3_OFFSET 0x0018 | ||
| 89 | #define OMAP4430_CM_CORE_DVFS_PERF3 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0018) | ||
| 90 | #define OMAP4_CM_CORE_DVFS_PERF4_OFFSET 0x001c | ||
| 91 | #define OMAP4430_CM_CORE_DVFS_PERF4 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x001c) | ||
| 92 | #define OMAP4_CM_CORE_DVFS_CURRENT_OFFSET 0x0024 | ||
| 93 | #define OMAP4430_CM_CORE_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0024) | ||
| 94 | #define OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET 0x0028 | ||
| 95 | #define OMAP4430_CM_IVA_DVFS_PERF_TESLA OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0028) | ||
| 96 | #define OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET 0x002c | ||
| 97 | #define OMAP4430_CM_IVA_DVFS_PERF_IVAHD OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x002c) | ||
| 98 | #define OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET 0x0030 | ||
| 99 | #define OMAP4430_CM_IVA_DVFS_PERF_ABE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0030) | ||
| 100 | #define OMAP4_CM_IVA_DVFS_CURRENT_OFFSET 0x0038 | ||
| 101 | #define OMAP4430_CM_IVA_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0038) | ||
| 102 | #define OMAP4_CM_CLKMODE_DPLL_PER_OFFSET 0x0040 | ||
| 103 | #define OMAP4430_CM_CLKMODE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0040) | ||
| 104 | #define OMAP4_CM_IDLEST_DPLL_PER_OFFSET 0x0044 | ||
| 105 | #define OMAP4430_CM_IDLEST_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0044) | ||
| 106 | #define OMAP4_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0048 | ||
| 107 | #define OMAP4430_CM_AUTOIDLE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0048) | ||
| 108 | #define OMAP4_CM_CLKSEL_DPLL_PER_OFFSET 0x004c | ||
| 109 | #define OMAP4430_CM_CLKSEL_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x004c) | ||
| 110 | #define OMAP4_CM_DIV_M2_DPLL_PER_OFFSET 0x0050 | ||
| 111 | #define OMAP4430_CM_DIV_M2_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0050) | ||
| 112 | #define OMAP4_CM_DIV_M3_DPLL_PER_OFFSET 0x0054 | ||
| 113 | #define OMAP4430_CM_DIV_M3_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0054) | ||
| 114 | #define OMAP4_CM_DIV_M4_DPLL_PER_OFFSET 0x0058 | ||
| 115 | #define OMAP4430_CM_DIV_M4_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0058) | ||
| 116 | #define OMAP4_CM_DIV_M5_DPLL_PER_OFFSET 0x005c | ||
| 117 | #define OMAP4430_CM_DIV_M5_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x005c) | ||
| 118 | #define OMAP4_CM_DIV_M6_DPLL_PER_OFFSET 0x0060 | ||
| 119 | #define OMAP4430_CM_DIV_M6_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0060) | ||
| 120 | #define OMAP4_CM_DIV_M7_DPLL_PER_OFFSET 0x0064 | ||
| 121 | #define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064) | ||
| 122 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068 | ||
| 123 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068) | ||
| 124 | #define OMAP4_CM_SSC_INSTFREQDIV_DPLL_PER_OFFSET 0x006c | ||
| 125 | #define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c) | ||
| 126 | #define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080 | ||
| 127 | #define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080) | ||
| 128 | #define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084 | ||
| 129 | #define OMAP4430_CM_IDLEST_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0084) | ||
| 130 | #define OMAP4_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0088 | ||
| 131 | #define OMAP4430_CM_AUTOIDLE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0088) | ||
| 132 | #define OMAP4_CM_CLKSEL_DPLL_USB_OFFSET 0x008c | ||
| 133 | #define OMAP4430_CM_CLKSEL_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x008c) | ||
| 134 | #define OMAP4_CM_DIV_M2_DPLL_USB_OFFSET 0x0090 | ||
| 135 | #define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090) | ||
| 136 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8 | ||
| 137 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8) | ||
| 138 | #define OMAP4_CM_SSC_INSTFREQDIV_DPLL_USB_OFFSET 0x00ac | ||
| 139 | #define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac) | ||
| 140 | #define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4 | ||
| 141 | #define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4) | ||
| 142 | #define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0 | ||
| 143 | #define OMAP4430_CM_CLKMODE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c0) | ||
| 144 | #define OMAP4_CM_IDLEST_DPLL_UNIPRO_OFFSET 0x00c4 | ||
| 145 | #define OMAP4430_CM_IDLEST_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c4) | ||
| 146 | #define OMAP4_CM_AUTOIDLE_DPLL_UNIPRO_OFFSET 0x00c8 | ||
| 147 | #define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c8) | ||
| 148 | #define OMAP4_CM_CLKSEL_DPLL_UNIPRO_OFFSET 0x00cc | ||
| 149 | #define OMAP4430_CM_CLKSEL_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00cc) | ||
| 150 | #define OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET 0x00d0 | ||
| 151 | #define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0) | ||
| 152 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8 | ||
| 153 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8) | ||
| 154 | #define OMAP4_CM_SSC_INSTFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec | ||
| 155 | #define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec) | ||
| 156 | |||
| 157 | /* CM2.ALWAYS_ON_CM2 register offsets */ | ||
| 158 | #define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000 | ||
| 159 | #define OMAP4430_CM_ALWON_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0000) | ||
| 160 | #define OMAP4_CM_ALWON_MDMINTC_CLKCTRL_OFFSET 0x0020 | ||
| 161 | #define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0020) | ||
| 162 | #define OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET 0x0028 | ||
| 163 | #define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0028) | ||
| 164 | #define OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET 0x0030 | ||
| 165 | #define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0030) | ||
| 166 | #define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET 0x0038 | ||
| 167 | #define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0038) | ||
| 168 | #define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET 0x0040 | ||
| 169 | #define OMAP4430_CM_ALWON_USBPHY_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0040) | ||
| 170 | |||
| 171 | /* CM2.CORE_CM2 register offsets */ | ||
| 172 | #define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET 0x0000 | ||
| 173 | #define OMAP4430_CM_L3_1_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0000) | ||
| 174 | #define OMAP4_CM_L3_1_DYNAMICDEP_OFFSET 0x0008 | ||
| 175 | #define OMAP4430_CM_L3_1_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0008) | ||
| 176 | #define OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET 0x0020 | ||
| 177 | #define OMAP4430_CM_L3_1_L3_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0020) | ||
| 178 | #define OMAP4_CM_L3_2_CLKSTCTRL_OFFSET 0x0100 | ||
| 179 | #define OMAP4430_CM_L3_2_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0100) | ||
| 180 | #define OMAP4_CM_L3_2_DYNAMICDEP_OFFSET 0x0108 | ||
| 181 | #define OMAP4430_CM_L3_2_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0108) | ||
| 182 | #define OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET 0x0120 | ||
| 183 | #define OMAP4430_CM_L3_2_L3_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0120) | ||
| 184 | #define OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET 0x0128 | ||
| 185 | #define OMAP4430_CM_L3_2_GPMC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0128) | ||
| 186 | #define OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET 0x0130 | ||
| 187 | #define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0130) | ||
| 188 | #define OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET 0x0200 | ||
| 189 | #define OMAP4430_CM_DUCATI_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0200) | ||
| 190 | #define OMAP4_CM_DUCATI_STATICDEP_OFFSET 0x0204 | ||
| 191 | #define OMAP4430_CM_DUCATI_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0204) | ||
| 192 | #define OMAP4_CM_DUCATI_DYNAMICDEP_OFFSET 0x0208 | ||
| 193 | #define OMAP4430_CM_DUCATI_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0208) | ||
| 194 | #define OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET 0x0220 | ||
| 195 | #define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0220) | ||
| 196 | #define OMAP4_CM_SDMA_CLKSTCTRL_OFFSET 0x0300 | ||
| 197 | #define OMAP4430_CM_SDMA_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0300) | ||
| 198 | #define OMAP4_CM_SDMA_STATICDEP_OFFSET 0x0304 | ||
| 199 | #define OMAP4430_CM_SDMA_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0304) | ||
| 200 | #define OMAP4_CM_SDMA_DYNAMICDEP_OFFSET 0x0308 | ||
| 201 | #define OMAP4430_CM_SDMA_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0308) | ||
| 202 | #define OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET 0x0320 | ||
| 203 | #define OMAP4430_CM_SDMA_SDMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0320) | ||
| 204 | #define OMAP4_CM_MEMIF_CLKSTCTRL_OFFSET 0x0400 | ||
| 205 | #define OMAP4430_CM_MEMIF_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0400) | ||
| 206 | #define OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET 0x0420 | ||
| 207 | #define OMAP4430_CM_MEMIF_DMM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0420) | ||
| 208 | #define OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET 0x0428 | ||
| 209 | #define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0428) | ||
| 210 | #define OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET 0x0430 | ||
| 211 | #define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0430) | ||
| 212 | #define OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET 0x0438 | ||
| 213 | #define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0438) | ||
| 214 | #define OMAP4_CM_MEMIF_DLL_CLKCTRL_OFFSET 0x0440 | ||
| 215 | #define OMAP4430_CM_MEMIF_DLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0440) | ||
| 216 | #define OMAP4_CM_MEMIF_EMIF_H1_CLKCTRL_OFFSET 0x0450 | ||
| 217 | #define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0450) | ||
| 218 | #define OMAP4_CM_MEMIF_EMIF_H2_CLKCTRL_OFFSET 0x0458 | ||
| 219 | #define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0458) | ||
| 220 | #define OMAP4_CM_MEMIF_DLL_H_CLKCTRL_OFFSET 0x0460 | ||
| 221 | #define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0460) | ||
| 222 | #define OMAP4_CM_D2D_CLKSTCTRL_OFFSET 0x0500 | ||
| 223 | #define OMAP4430_CM_D2D_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0500) | ||
| 224 | #define OMAP4_CM_D2D_STATICDEP_OFFSET 0x0504 | ||
| 225 | #define OMAP4430_CM_D2D_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0504) | ||
| 226 | #define OMAP4_CM_D2D_DYNAMICDEP_OFFSET 0x0508 | ||
| 227 | #define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508) | ||
| 228 | #define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520 | ||
| 229 | #define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520) | ||
| 230 | #define OMAP4_CM_D2D_INSTEM_ICR_CLKCTRL_OFFSET 0x0528 | ||
| 231 | #define OMAP4430_CM_D2D_INSTEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528) | ||
| 232 | #define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530 | ||
| 233 | #define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530) | ||
| 234 | #define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600 | ||
| 235 | #define OMAP4430_CM_L4CFG_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0600) | ||
| 236 | #define OMAP4_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608 | ||
| 237 | #define OMAP4430_CM_L4CFG_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0608) | ||
| 238 | #define OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620 | ||
| 239 | #define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0620) | ||
| 240 | #define OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET 0x0628 | ||
| 241 | #define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0628) | ||
| 242 | #define OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET 0x0630 | ||
| 243 | #define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0630) | ||
| 244 | #define OMAP4_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638 | ||
| 245 | #define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0638) | ||
| 246 | #define OMAP4_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700 | ||
| 247 | #define OMAP4430_CM_L3INSTR_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0700) | ||
| 248 | #define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET 0x0720 | ||
| 249 | #define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0720) | ||
| 250 | #define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728 | ||
| 251 | #define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0728) | ||
| 252 | #define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET 0x0740 | ||
| 253 | #define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0740) | ||
| 254 | |||
| 255 | /* CM2.IVAHD_CM2 register offsets */ | ||
| 256 | #define OMAP4_CM_IVAHD_CLKSTCTRL_OFFSET 0x0000 | ||
| 257 | #define OMAP4430_CM_IVAHD_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0000) | ||
| 258 | #define OMAP4_CM_IVAHD_STATICDEP_OFFSET 0x0004 | ||
| 259 | #define OMAP4430_CM_IVAHD_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0004) | ||
| 260 | #define OMAP4_CM_IVAHD_DYNAMICDEP_OFFSET 0x0008 | ||
| 261 | #define OMAP4430_CM_IVAHD_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0008) | ||
| 262 | #define OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET 0x0020 | ||
| 263 | #define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0020) | ||
| 264 | #define OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET 0x0028 | ||
| 265 | #define OMAP4430_CM_IVAHD_SL2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0028) | ||
| 266 | |||
| 267 | /* CM2.CAM_CM2 register offsets */ | ||
| 268 | #define OMAP4_CM_CAM_CLKSTCTRL_OFFSET 0x0000 | ||
| 269 | #define OMAP4430_CM_CAM_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0000) | ||
| 270 | #define OMAP4_CM_CAM_STATICDEP_OFFSET 0x0004 | ||
| 271 | #define OMAP4430_CM_CAM_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0004) | ||
| 272 | #define OMAP4_CM_CAM_DYNAMICDEP_OFFSET 0x0008 | ||
| 273 | #define OMAP4430_CM_CAM_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0008) | ||
| 274 | #define OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET 0x0020 | ||
| 275 | #define OMAP4430_CM_CAM_ISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0020) | ||
| 276 | #define OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET 0x0028 | ||
| 277 | #define OMAP4430_CM_CAM_FDIF_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0028) | ||
| 278 | |||
| 279 | /* CM2.DSS_CM2 register offsets */ | ||
| 280 | #define OMAP4_CM_DSS_CLKSTCTRL_OFFSET 0x0000 | ||
| 281 | #define OMAP4430_CM_DSS_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0000) | ||
| 282 | #define OMAP4_CM_DSS_STATICDEP_OFFSET 0x0004 | ||
| 283 | #define OMAP4430_CM_DSS_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0004) | ||
| 284 | #define OMAP4_CM_DSS_DYNAMICDEP_OFFSET 0x0008 | ||
| 285 | #define OMAP4430_CM_DSS_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0008) | ||
| 286 | #define OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020 | ||
| 287 | #define OMAP4430_CM_DSS_DSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0020) | ||
| 288 | #define OMAP4_CM_DSS_DEISS_CLKCTRL_OFFSET 0x0028 | ||
| 289 | #define OMAP4430_CM_DSS_DEISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0028) | ||
| 290 | |||
| 291 | /* CM2.GFX_CM2 register offsets */ | ||
| 292 | #define OMAP4_CM_GFX_CLKSTCTRL_OFFSET 0x0000 | ||
| 293 | #define OMAP4430_CM_GFX_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0000) | ||
| 294 | #define OMAP4_CM_GFX_STATICDEP_OFFSET 0x0004 | ||
| 295 | #define OMAP4430_CM_GFX_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0004) | ||
| 296 | #define OMAP4_CM_GFX_DYNAMICDEP_OFFSET 0x0008 | ||
| 297 | #define OMAP4430_CM_GFX_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0008) | ||
| 298 | #define OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020 | ||
| 299 | #define OMAP4430_CM_GFX_GFX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0020) | ||
| 300 | |||
| 301 | /* CM2.L3INIT_CM2 register offsets */ | ||
| 302 | #define OMAP4_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000 | ||
| 303 | #define OMAP4430_CM_L3INIT_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0000) | ||
| 304 | #define OMAP4_CM_L3INIT_STATICDEP_OFFSET 0x0004 | ||
| 305 | #define OMAP4430_CM_L3INIT_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0004) | ||
| 306 | #define OMAP4_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008 | ||
| 307 | #define OMAP4430_CM_L3INIT_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0008) | ||
| 308 | #define OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028 | ||
| 309 | #define OMAP4430_CM_L3INIT_MMC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0028) | ||
| 310 | #define OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030 | ||
| 311 | #define OMAP4430_CM_L3INIT_MMC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0030) | ||
| 312 | #define OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET 0x0038 | ||
| 313 | #define OMAP4430_CM_L3INIT_HSI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0038) | ||
| 314 | #define OMAP4_CM_L3INIT_UNIPRO1_CLKCTRL_OFFSET 0x0040 | ||
| 315 | #define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0040) | ||
| 316 | #define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET 0x0058 | ||
| 317 | #define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0058) | ||
| 318 | #define OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET 0x0060 | ||
| 319 | #define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0060) | ||
| 320 | #define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET 0x0068 | ||
| 321 | #define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0068) | ||
| 322 | #define OMAP4_CM_L3INIT_P1500_CLKCTRL_OFFSET 0x0078 | ||
| 323 | #define OMAP4430_CM_L3INIT_P1500_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0078) | ||
| 324 | #define OMAP4_CM_L3INIT_EMAC_CLKCTRL_OFFSET 0x0080 | ||
| 325 | #define OMAP4430_CM_L3INIT_EMAC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0080) | ||
| 326 | #define OMAP4_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088 | ||
| 327 | #define OMAP4430_CM_L3INIT_SATA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0088) | ||
| 328 | #define OMAP4_CM_L3INIT_TPPSS_CLKCTRL_OFFSET 0x0090 | ||
| 329 | #define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0090) | ||
| 330 | #define OMAP4_CM_L3INIT_PCIESS_CLKCTRL_OFFSET 0x0098 | ||
| 331 | #define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0098) | ||
| 332 | #define OMAP4_CM_L3INIT_CCPTX_CLKCTRL_OFFSET 0x00a8 | ||
| 333 | #define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00a8) | ||
| 334 | #define OMAP4_CM_L3INIT_XHPI_CLKCTRL_OFFSET 0x00c0 | ||
| 335 | #define OMAP4430_CM_L3INIT_XHPI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c0) | ||
| 336 | #define OMAP4_CM_L3INIT_MMC6_CLKCTRL_OFFSET 0x00c8 | ||
| 337 | #define OMAP4430_CM_L3INIT_MMC6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c8) | ||
| 338 | #define OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET 0x00d0 | ||
| 339 | #define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00d0) | ||
| 340 | #define OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET 0x00e0 | ||
| 341 | #define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00e0) | ||
| 342 | |||
| 343 | /* CM2.L4PER_CM2 register offsets */ | ||
| 344 | #define OMAP4_CM_L4PER_CLKSTCTRL_OFFSET 0x0000 | ||
| 345 | #define OMAP4430_CM_L4PER_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0000) | ||
| 346 | #define OMAP4_CM_L4PER_DYNAMICDEP_OFFSET 0x0008 | ||
| 347 | #define OMAP4430_CM_L4PER_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0008) | ||
| 348 | #define OMAP4_CM_L4PER_ADC_CLKCTRL_OFFSET 0x0020 | ||
| 349 | #define OMAP4430_CM_L4PER_ADC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0020) | ||
| 350 | #define OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET 0x0028 | ||
| 351 | #define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0028) | ||
| 352 | #define OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET 0x0030 | ||
| 353 | #define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0030) | ||
| 354 | #define OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET 0x0038 | ||
| 355 | #define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0038) | ||
| 356 | #define OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET 0x0040 | ||
| 357 | #define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0040) | ||
| 358 | #define OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET 0x0048 | ||
| 359 | #define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0048) | ||
| 360 | #define OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET 0x0050 | ||
| 361 | #define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0050) | ||
| 362 | #define OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058 | ||
| 363 | #define OMAP4430_CM_L4PER_ELM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0058) | ||
| 364 | #define OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060 | ||
| 365 | #define OMAP4430_CM_L4PER_GPIO2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0060) | ||
| 366 | #define OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068 | ||
| 367 | #define OMAP4430_CM_L4PER_GPIO3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0068) | ||
| 368 | #define OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070 | ||
| 369 | #define OMAP4430_CM_L4PER_GPIO4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0070) | ||
| 370 | #define OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078 | ||
| 371 | #define OMAP4430_CM_L4PER_GPIO5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0078) | ||
| 372 | #define OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080 | ||
| 373 | #define OMAP4430_CM_L4PER_GPIO6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0080) | ||
| 374 | #define OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088 | ||
| 375 | #define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0088) | ||
| 376 | #define OMAP4_CM_L4PER_HECC1_CLKCTRL_OFFSET 0x0090 | ||
| 377 | #define OMAP4430_CM_L4PER_HECC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0090) | ||
| 378 | #define OMAP4_CM_L4PER_HECC2_CLKCTRL_OFFSET 0x0098 | ||
| 379 | #define OMAP4430_CM_L4PER_HECC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0098) | ||
| 380 | #define OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0 | ||
| 381 | #define OMAP4430_CM_L4PER_I2C1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a0) | ||
| 382 | #define OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8 | ||
| 383 | #define OMAP4430_CM_L4PER_I2C2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a8) | ||
| 384 | #define OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0 | ||
| 385 | #define OMAP4430_CM_L4PER_I2C3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b0) | ||
| 386 | #define OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8 | ||
| 387 | #define OMAP4430_CM_L4PER_I2C4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b8) | ||
| 388 | #define OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET 0x00c0 | ||
| 389 | #define OMAP4430_CM_L4PER_L4PER_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00c0) | ||
| 390 | #define OMAP4_CM_L4PER_MCASP2_CLKCTRL_OFFSET 0x00d0 | ||
| 391 | #define OMAP4430_CM_L4PER_MCASP2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d0) | ||
| 392 | #define OMAP4_CM_L4PER_MCASP3_CLKCTRL_OFFSET 0x00d8 | ||
| 393 | #define OMAP4430_CM_L4PER_MCASP3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d8) | ||
| 394 | #define OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET 0x00e0 | ||
| 395 | #define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e0) | ||
| 396 | #define OMAP4_CM_L4PER_MGATE_CLKCTRL_OFFSET 0x00e8 | ||
| 397 | #define OMAP4430_CM_L4PER_MGATE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e8) | ||
| 398 | #define OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0 | ||
| 399 | #define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f0) | ||
| 400 | #define OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8 | ||
| 401 | #define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f8) | ||
| 402 | #define OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100 | ||
| 403 | #define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0100) | ||
| 404 | #define OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108 | ||
| 405 | #define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0108) | ||
| 406 | #define OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET 0x0120 | ||
| 407 | #define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0120) | ||
| 408 | #define OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET 0x0128 | ||
| 409 | #define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0128) | ||
| 410 | #define OMAP4_CM_L4PER_MSPROHG_CLKCTRL_OFFSET 0x0130 | ||
| 411 | #define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0130) | ||
| 412 | #define OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET 0x0138 | ||
| 413 | #define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0138) | ||
| 414 | #define OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140 | ||
| 415 | #define OMAP4430_CM_L4PER_UART1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0140) | ||
| 416 | #define OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148 | ||
| 417 | #define OMAP4430_CM_L4PER_UART2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0148) | ||
| 418 | #define OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150 | ||
| 419 | #define OMAP4430_CM_L4PER_UART3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0150) | ||
| 420 | #define OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158 | ||
| 421 | #define OMAP4430_CM_L4PER_UART4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0158) | ||
| 422 | #define OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET 0x0160 | ||
| 423 | #define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0160) | ||
| 424 | #define OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0168 | ||
| 425 | #define OMAP4430_CM_L4PER_I2C5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0168) | ||
| 426 | #define OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180 | ||
| 427 | #define OMAP4430_CM_L4SEC_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0180) | ||
| 428 | #define OMAP4_CM_L4SEC_STATICDEP_OFFSET 0x0184 | ||
| 429 | #define OMAP4430_CM_L4SEC_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0184) | ||
| 430 | #define OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188 | ||
| 431 | #define OMAP4430_CM_L4SEC_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0188) | ||
| 432 | #define OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0 | ||
| 433 | #define OMAP4430_CM_L4SEC_AES1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a0) | ||
| 434 | #define OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8 | ||
| 435 | #define OMAP4430_CM_L4SEC_AES2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a8) | ||
| 436 | #define OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0 | ||
| 437 | #define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b0) | ||
| 438 | #define OMAP4_CM_L4SEC_PKAEIP29_CLKCTRL_OFFSET 0x01b8 | ||
| 439 | #define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b8) | ||
| 440 | #define OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0 | ||
| 441 | #define OMAP4430_CM_L4SEC_RNG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c0) | ||
| 442 | #define OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8 | ||
| 443 | #define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c8) | ||
| 444 | #define OMAP4_CM_L4SEC_CRYPTODMA_CLKCTRL_OFFSET 0x01d8 | ||
| 445 | #define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01d8) | ||
| 446 | |||
| 447 | /* CM2.CEFUSE_CM2 register offsets */ | ||
| 448 | #define OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000 | ||
| 449 | #define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0000) | ||
| 450 | #define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 | ||
| 451 | #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020) | ||
| 452 | |||
| 453 | /* CM2.RESTORE_CM2 register offsets */ | ||
| 454 | #define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET 0x0000 | ||
| 455 | #define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0000) | ||
| 456 | #define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET 0x0004 | ||
| 457 | #define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0004) | ||
| 458 | #define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET 0x0008 | ||
| 459 | #define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0008) | ||
| 460 | #define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET 0x000c | ||
| 461 | #define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x000c) | ||
| 462 | #define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET 0x0010 | ||
| 463 | #define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0010) | ||
| 464 | #define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET 0x0014 | ||
| 465 | #define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0014) | ||
| 466 | #define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET 0x0018 | ||
| 467 | #define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0018) | ||
| 468 | #define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET 0x001c | ||
| 469 | #define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x001c) | ||
| 470 | #define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET 0x0020 | ||
| 471 | #define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0020) | ||
| 472 | #define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET 0x0024 | ||
| 473 | #define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0024) | ||
| 474 | #define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET 0x0028 | ||
| 475 | #define OMAP4430_CM_D2D_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0028) | ||
| 476 | #define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET 0x002c | ||
| 477 | #define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x002c) | ||
| 478 | #define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET 0x0030 | ||
| 479 | #define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0030) | ||
| 480 | #define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET 0x0034 | ||
| 481 | #define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0034) | ||
| 482 | #define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET 0x0038 | ||
| 483 | #define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0038) | ||
| 484 | #define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET 0x003c | ||
| 485 | #define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x003c) | ||
| 486 | #define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET 0x0040 | ||
| 487 | #define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0040) | ||
| 488 | #define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET 0x0044 | ||
| 489 | #define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0044) | ||
| 490 | #define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET 0x0048 | ||
| 491 | #define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0048) | ||
| 492 | #define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET 0x004c | ||
| 493 | #define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x004c) | ||
| 494 | #define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET 0x0050 | ||
| 495 | #define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0050) | ||
| 496 | #define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET 0x0054 | ||
| 497 | #define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0054) | ||
| 498 | #define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET 0x0058 | ||
| 499 | #define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0058) | ||
| 500 | #define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET 0x005c | ||
| 501 | #define OMAP4430_CM_SDMA_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x005c) | ||
| 502 | |||
| 503 | /* Function prototypes */ | ||
| 504 | extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx); | ||
| 505 | extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx); | ||
| 506 | extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); | ||
| 507 | |||
| 508 | #endif | ||
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c new file mode 100644 index 000000000000..96954aa48671 --- /dev/null +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c | |||
| @@ -0,0 +1,471 @@ | |||
| 1 | /* | ||
| 2 | * OMAP2/3 CM module functions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Nokia Corporation | ||
| 5 | * Paul Walmsley | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/types.h> | ||
| 14 | #include <linux/delay.h> | ||
| 15 | #include <linux/spinlock.h> | ||
| 16 | #include <linux/list.h> | ||
| 17 | #include <linux/errno.h> | ||
| 18 | #include <linux/err.h> | ||
| 19 | #include <linux/io.h> | ||
| 20 | |||
| 21 | #include <plat/common.h> | ||
| 22 | |||
| 23 | #include "cm.h" | ||
| 24 | #include "cm2xxx_3xxx.h" | ||
| 25 | #include "cm-regbits-24xx.h" | ||
| 26 | #include "cm-regbits-34xx.h" | ||
| 27 | |||
| 28 | static const u8 cm_idlest_offs[] = { | ||
| 29 | CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3 | ||
| 30 | }; | ||
| 31 | |||
| 32 | u32 omap2_cm_read_mod_reg(s16 module, u16 idx) | ||
| 33 | { | ||
| 34 | return __raw_readl(cm_base + module + idx); | ||
| 35 | } | ||
| 36 | |||
| 37 | void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx) | ||
| 38 | { | ||
| 39 | __raw_writel(val, cm_base + module + idx); | ||
| 40 | } | ||
| 41 | |||
| 42 | /* Read-modify-write a register in a CM module. Caller must lock */ | ||
| 43 | u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) | ||
| 44 | { | ||
| 45 | u32 v; | ||
| 46 | |||
| 47 | v = omap2_cm_read_mod_reg(module, idx); | ||
| 48 | v &= ~mask; | ||
| 49 | v |= bits; | ||
| 50 | omap2_cm_write_mod_reg(v, module, idx); | ||
| 51 | |||
| 52 | return v; | ||
| 53 | } | ||
| 54 | |||
| 55 | u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) | ||
| 56 | { | ||
| 57 | return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx); | ||
| 58 | } | ||
| 59 | |||
| 60 | u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) | ||
| 61 | { | ||
| 62 | return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx); | ||
| 63 | } | ||
| 64 | |||
| 65 | /* | ||
| 66 | * | ||
| 67 | */ | ||
| 68 | |||
| 69 | static void _write_clktrctrl(u8 c, s16 module, u32 mask) | ||
| 70 | { | ||
| 71 | u32 v; | ||
| 72 | |||
| 73 | v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL); | ||
| 74 | v &= ~mask; | ||
| 75 | v |= c << __ffs(mask); | ||
| 76 | omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL); | ||
| 77 | } | ||
| 78 | |||
| 79 | bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask) | ||
| 80 | { | ||
| 81 | u32 v; | ||
| 82 | bool ret = 0; | ||
| 83 | |||
| 84 | BUG_ON(!cpu_is_omap24xx() && !cpu_is_omap34xx()); | ||
| 85 | |||
| 86 | v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL); | ||
| 87 | v &= mask; | ||
| 88 | v >>= __ffs(mask); | ||
| 89 | |||
| 90 | if (cpu_is_omap24xx()) | ||
| 91 | ret = (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0; | ||
| 92 | else | ||
| 93 | ret = (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0; | ||
| 94 | |||
| 95 | return ret; | ||
| 96 | } | ||
| 97 | |||
| 98 | void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask) | ||
| 99 | { | ||
| 100 | _write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask); | ||
| 101 | } | ||
| 102 | |||
| 103 | void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask) | ||
| 104 | { | ||
| 105 | _write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask); | ||
| 106 | } | ||
| 107 | |||
| 108 | void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask) | ||
| 109 | { | ||
| 110 | _write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, module, mask); | ||
| 111 | } | ||
| 112 | |||
| 113 | void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask) | ||
| 114 | { | ||
| 115 | _write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, module, mask); | ||
| 116 | } | ||
| 117 | |||
| 118 | void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask) | ||
| 119 | { | ||
| 120 | _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, module, mask); | ||
| 121 | } | ||
| 122 | |||
| 123 | void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask) | ||
| 124 | { | ||
| 125 | _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask); | ||
| 126 | } | ||
| 127 | |||
| 128 | |||
| 129 | /* | ||
| 130 | * | ||
| 131 | */ | ||
| 132 | |||
| 133 | /** | ||
| 134 | * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby | ||
| 135 | * @prcm_mod: PRCM module offset | ||
| 136 | * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3) | ||
| 137 | * @idlest_shift: shift of the bit in the CM_IDLEST* register to check | ||
| 138 | * | ||
| 139 | * XXX document | ||
| 140 | */ | ||
| 141 | int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift) | ||
| 142 | { | ||
| 143 | int ena = 0, i = 0; | ||
| 144 | u8 cm_idlest_reg; | ||
| 145 | u32 mask; | ||
| 146 | |||
| 147 | if (!idlest_id || (idlest_id > ARRAY_SIZE(cm_idlest_offs))) | ||
| 148 | return -EINVAL; | ||
| 149 | |||
| 150 | cm_idlest_reg = cm_idlest_offs[idlest_id - 1]; | ||
| 151 | |||
| 152 | mask = 1 << idlest_shift; | ||
| 153 | |||
| 154 | if (cpu_is_omap24xx()) | ||
| 155 | ena = mask; | ||
| 156 | else if (cpu_is_omap34xx()) | ||
| 157 | ena = 0; | ||
| 158 | else | ||
| 159 | BUG(); | ||
| 160 | |||
| 161 | omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena), | ||
| 162 | MAX_MODULE_READY_TIME, i); | ||
| 163 | |||
| 164 | return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; | ||
| 165 | } | ||
| 166 | |||
| 167 | /* | ||
| 168 | * Context save/restore code - OMAP3 only | ||
| 169 | */ | ||
| 170 | #ifdef CONFIG_ARCH_OMAP3 | ||
| 171 | struct omap3_cm_regs { | ||
| 172 | u32 iva2_cm_clksel1; | ||
| 173 | u32 iva2_cm_clksel2; | ||
| 174 | u32 cm_sysconfig; | ||
| 175 | u32 sgx_cm_clksel; | ||
| 176 | u32 dss_cm_clksel; | ||
| 177 | u32 cam_cm_clksel; | ||
| 178 | u32 per_cm_clksel; | ||
| 179 | u32 emu_cm_clksel; | ||
| 180 | u32 emu_cm_clkstctrl; | ||
| 181 | u32 pll_cm_autoidle2; | ||
| 182 | u32 pll_cm_clksel4; | ||
| 183 | u32 pll_cm_clksel5; | ||
| 184 | u32 pll_cm_clken2; | ||
| 185 | u32 cm_polctrl; | ||
| 186 | u32 iva2_cm_fclken; | ||
| 187 | u32 iva2_cm_clken_pll; | ||
| 188 | u32 core_cm_fclken1; | ||
| 189 | u32 core_cm_fclken3; | ||
| 190 | u32 sgx_cm_fclken; | ||
| 191 | u32 wkup_cm_fclken; | ||
| 192 | u32 dss_cm_fclken; | ||
| 193 | u32 cam_cm_fclken; | ||
| 194 | u32 per_cm_fclken; | ||
| 195 | u32 usbhost_cm_fclken; | ||
| 196 | u32 core_cm_iclken1; | ||
| 197 | u32 core_cm_iclken2; | ||
| 198 | u32 core_cm_iclken3; | ||
| 199 | u32 sgx_cm_iclken; | ||
| 200 | u32 wkup_cm_iclken; | ||
| 201 | u32 dss_cm_iclken; | ||
| 202 | u32 cam_cm_iclken; | ||
| 203 | u32 per_cm_iclken; | ||
| 204 | u32 usbhost_cm_iclken; | ||
| 205 | u32 iva2_cm_autoidle2; | ||
| 206 | u32 mpu_cm_autoidle2; | ||
| 207 | u32 iva2_cm_clkstctrl; | ||
| 208 | u32 mpu_cm_clkstctrl; | ||
| 209 | u32 core_cm_clkstctrl; | ||
| 210 | u32 sgx_cm_clkstctrl; | ||
| 211 | u32 dss_cm_clkstctrl; | ||
| 212 | u32 cam_cm_clkstctrl; | ||
| 213 | u32 per_cm_clkstctrl; | ||
| 214 | u32 neon_cm_clkstctrl; | ||
| 215 | u32 usbhost_cm_clkstctrl; | ||
| 216 | u32 core_cm_autoidle1; | ||
| 217 | u32 core_cm_autoidle2; | ||
| 218 | u32 core_cm_autoidle3; | ||
| 219 | u32 wkup_cm_autoidle; | ||
| 220 | u32 dss_cm_autoidle; | ||
| 221 | u32 cam_cm_autoidle; | ||
| 222 | u32 per_cm_autoidle; | ||
| 223 | u32 usbhost_cm_autoidle; | ||
| 224 | u32 sgx_cm_sleepdep; | ||
| 225 | u32 dss_cm_sleepdep; | ||
| 226 | u32 cam_cm_sleepdep; | ||
| 227 | u32 per_cm_sleepdep; | ||
| 228 | u32 usbhost_cm_sleepdep; | ||
| 229 | u32 cm_clkout_ctrl; | ||
| 230 | }; | ||
| 231 | |||
| 232 | static struct omap3_cm_regs cm_context; | ||
| 233 | |||
| 234 | void omap3_cm_save_context(void) | ||
| 235 | { | ||
| 236 | cm_context.iva2_cm_clksel1 = | ||
| 237 | omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1); | ||
| 238 | cm_context.iva2_cm_clksel2 = | ||
| 239 | omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2); | ||
| 240 | cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG); | ||
| 241 | cm_context.sgx_cm_clksel = | ||
| 242 | omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL); | ||
| 243 | cm_context.dss_cm_clksel = | ||
| 244 | omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL); | ||
| 245 | cm_context.cam_cm_clksel = | ||
| 246 | omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL); | ||
| 247 | cm_context.per_cm_clksel = | ||
| 248 | omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL); | ||
| 249 | cm_context.emu_cm_clksel = | ||
| 250 | omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1); | ||
| 251 | cm_context.emu_cm_clkstctrl = | ||
| 252 | omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL); | ||
| 253 | cm_context.pll_cm_autoidle2 = | ||
| 254 | omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2); | ||
| 255 | cm_context.pll_cm_clksel4 = | ||
| 256 | omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4); | ||
| 257 | cm_context.pll_cm_clksel5 = | ||
| 258 | omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5); | ||
| 259 | cm_context.pll_cm_clken2 = | ||
| 260 | omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2); | ||
| 261 | cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL); | ||
| 262 | cm_context.iva2_cm_fclken = | ||
| 263 | omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN); | ||
| 264 | cm_context.iva2_cm_clken_pll = | ||
| 265 | omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL); | ||
| 266 | cm_context.core_cm_fclken1 = | ||
| 267 | omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); | ||
| 268 | cm_context.core_cm_fclken3 = | ||
| 269 | omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3); | ||
| 270 | cm_context.sgx_cm_fclken = | ||
| 271 | omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN); | ||
| 272 | cm_context.wkup_cm_fclken = | ||
| 273 | omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN); | ||
| 274 | cm_context.dss_cm_fclken = | ||
| 275 | omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN); | ||
| 276 | cm_context.cam_cm_fclken = | ||
| 277 | omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN); | ||
| 278 | cm_context.per_cm_fclken = | ||
| 279 | omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN); | ||
| 280 | cm_context.usbhost_cm_fclken = | ||
| 281 | omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); | ||
| 282 | cm_context.core_cm_iclken1 = | ||
| 283 | omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1); | ||
| 284 | cm_context.core_cm_iclken2 = | ||
| 285 | omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2); | ||
| 286 | cm_context.core_cm_iclken3 = | ||
| 287 | omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3); | ||
| 288 | cm_context.sgx_cm_iclken = | ||
| 289 | omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN); | ||
| 290 | cm_context.wkup_cm_iclken = | ||
| 291 | omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN); | ||
| 292 | cm_context.dss_cm_iclken = | ||
| 293 | omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN); | ||
| 294 | cm_context.cam_cm_iclken = | ||
| 295 | omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN); | ||
| 296 | cm_context.per_cm_iclken = | ||
| 297 | omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN); | ||
| 298 | cm_context.usbhost_cm_iclken = | ||
| 299 | omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); | ||
| 300 | cm_context.iva2_cm_autoidle2 = | ||
| 301 | omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2); | ||
| 302 | cm_context.mpu_cm_autoidle2 = | ||
| 303 | omap2_cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2); | ||
| 304 | cm_context.iva2_cm_clkstctrl = | ||
| 305 | omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL); | ||
| 306 | cm_context.mpu_cm_clkstctrl = | ||
| 307 | omap2_cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL); | ||
| 308 | cm_context.core_cm_clkstctrl = | ||
| 309 | omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL); | ||
| 310 | cm_context.sgx_cm_clkstctrl = | ||
| 311 | omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL); | ||
| 312 | cm_context.dss_cm_clkstctrl = | ||
| 313 | omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL); | ||
| 314 | cm_context.cam_cm_clkstctrl = | ||
| 315 | omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL); | ||
| 316 | cm_context.per_cm_clkstctrl = | ||
| 317 | omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL); | ||
| 318 | cm_context.neon_cm_clkstctrl = | ||
| 319 | omap2_cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL); | ||
| 320 | cm_context.usbhost_cm_clkstctrl = | ||
| 321 | omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, | ||
| 322 | OMAP2_CM_CLKSTCTRL); | ||
| 323 | cm_context.core_cm_autoidle1 = | ||
| 324 | omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1); | ||
| 325 | cm_context.core_cm_autoidle2 = | ||
| 326 | omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2); | ||
| 327 | cm_context.core_cm_autoidle3 = | ||
| 328 | omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3); | ||
| 329 | cm_context.wkup_cm_autoidle = | ||
| 330 | omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE); | ||
| 331 | cm_context.dss_cm_autoidle = | ||
| 332 | omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE); | ||
| 333 | cm_context.cam_cm_autoidle = | ||
| 334 | omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE); | ||
| 335 | cm_context.per_cm_autoidle = | ||
| 336 | omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); | ||
| 337 | cm_context.usbhost_cm_autoidle = | ||
| 338 | omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); | ||
| 339 | cm_context.sgx_cm_sleepdep = | ||
| 340 | omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, | ||
| 341 | OMAP3430_CM_SLEEPDEP); | ||
| 342 | cm_context.dss_cm_sleepdep = | ||
| 343 | omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP); | ||
| 344 | cm_context.cam_cm_sleepdep = | ||
| 345 | omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP); | ||
| 346 | cm_context.per_cm_sleepdep = | ||
| 347 | omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP); | ||
| 348 | cm_context.usbhost_cm_sleepdep = | ||
| 349 | omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, | ||
| 350 | OMAP3430_CM_SLEEPDEP); | ||
| 351 | cm_context.cm_clkout_ctrl = | ||
| 352 | omap2_cm_read_mod_reg(OMAP3430_CCR_MOD, | ||
| 353 | OMAP3_CM_CLKOUT_CTRL_OFFSET); | ||
| 354 | } | ||
| 355 | |||
| 356 | void omap3_cm_restore_context(void) | ||
| 357 | { | ||
| 358 | omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD, | ||
| 359 | CM_CLKSEL1); | ||
| 360 | omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD, | ||
| 361 | CM_CLKSEL2); | ||
| 362 | __raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG); | ||
| 363 | omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD, | ||
| 364 | CM_CLKSEL); | ||
| 365 | omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD, | ||
| 366 | CM_CLKSEL); | ||
| 367 | omap2_cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD, | ||
| 368 | CM_CLKSEL); | ||
| 369 | omap2_cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD, | ||
| 370 | CM_CLKSEL); | ||
| 371 | omap2_cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD, | ||
| 372 | CM_CLKSEL1); | ||
| 373 | omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD, | ||
| 374 | OMAP2_CM_CLKSTCTRL); | ||
| 375 | omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD, | ||
| 376 | CM_AUTOIDLE2); | ||
| 377 | omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD, | ||
| 378 | OMAP3430ES2_CM_CLKSEL4); | ||
| 379 | omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD, | ||
| 380 | OMAP3430ES2_CM_CLKSEL5); | ||
| 381 | omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD, | ||
| 382 | OMAP3430ES2_CM_CLKEN2); | ||
| 383 | __raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL); | ||
| 384 | omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD, | ||
| 385 | CM_FCLKEN); | ||
| 386 | omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD, | ||
| 387 | OMAP3430_CM_CLKEN_PLL); | ||
| 388 | omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD, | ||
| 389 | CM_FCLKEN1); | ||
| 390 | omap2_cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD, | ||
| 391 | OMAP3430ES2_CM_FCLKEN3); | ||
| 392 | omap2_cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD, | ||
| 393 | CM_FCLKEN); | ||
| 394 | omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN); | ||
| 395 | omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD, | ||
| 396 | CM_FCLKEN); | ||
| 397 | omap2_cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD, | ||
| 398 | CM_FCLKEN); | ||
| 399 | omap2_cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD, | ||
| 400 | CM_FCLKEN); | ||
| 401 | omap2_cm_write_mod_reg(cm_context.usbhost_cm_fclken, | ||
| 402 | OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); | ||
| 403 | omap2_cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD, | ||
| 404 | CM_ICLKEN1); | ||
| 405 | omap2_cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD, | ||
| 406 | CM_ICLKEN2); | ||
| 407 | omap2_cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD, | ||
| 408 | CM_ICLKEN3); | ||
| 409 | omap2_cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD, | ||
| 410 | CM_ICLKEN); | ||
| 411 | omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN); | ||
| 412 | omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD, | ||
| 413 | CM_ICLKEN); | ||
| 414 | omap2_cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD, | ||
| 415 | CM_ICLKEN); | ||
| 416 | omap2_cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD, | ||
| 417 | CM_ICLKEN); | ||
| 418 | omap2_cm_write_mod_reg(cm_context.usbhost_cm_iclken, | ||
| 419 | OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); | ||
| 420 | omap2_cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD, | ||
| 421 | CM_AUTOIDLE2); | ||
| 422 | omap2_cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD, | ||
| 423 | CM_AUTOIDLE2); | ||
| 424 | omap2_cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD, | ||
| 425 | OMAP2_CM_CLKSTCTRL); | ||
| 426 | omap2_cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD, | ||
| 427 | OMAP2_CM_CLKSTCTRL); | ||
| 428 | omap2_cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD, | ||
| 429 | OMAP2_CM_CLKSTCTRL); | ||
| 430 | omap2_cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD, | ||
| 431 | OMAP2_CM_CLKSTCTRL); | ||
| 432 | omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD, | ||
| 433 | OMAP2_CM_CLKSTCTRL); | ||
| 434 | omap2_cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD, | ||
| 435 | OMAP2_CM_CLKSTCTRL); | ||
| 436 | omap2_cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD, | ||
| 437 | OMAP2_CM_CLKSTCTRL); | ||
| 438 | omap2_cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD, | ||
| 439 | OMAP2_CM_CLKSTCTRL); | ||
| 440 | omap2_cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl, | ||
| 441 | OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL); | ||
| 442 | omap2_cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD, | ||
| 443 | CM_AUTOIDLE1); | ||
| 444 | omap2_cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD, | ||
| 445 | CM_AUTOIDLE2); | ||
| 446 | omap2_cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD, | ||
| 447 | CM_AUTOIDLE3); | ||
| 448 | omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD, | ||
| 449 | CM_AUTOIDLE); | ||
| 450 | omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD, | ||
| 451 | CM_AUTOIDLE); | ||
| 452 | omap2_cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD, | ||
| 453 | CM_AUTOIDLE); | ||
| 454 | omap2_cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD, | ||
| 455 | CM_AUTOIDLE); | ||
| 456 | omap2_cm_write_mod_reg(cm_context.usbhost_cm_autoidle, | ||
| 457 | OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); | ||
| 458 | omap2_cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD, | ||
| 459 | OMAP3430_CM_SLEEPDEP); | ||
| 460 | omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD, | ||
| 461 | OMAP3430_CM_SLEEPDEP); | ||
| 462 | omap2_cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD, | ||
| 463 | OMAP3430_CM_SLEEPDEP); | ||
| 464 | omap2_cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD, | ||
| 465 | OMAP3430_CM_SLEEPDEP); | ||
| 466 | omap2_cm_write_mod_reg(cm_context.usbhost_cm_sleepdep, | ||
| 467 | OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP); | ||
| 468 | omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD, | ||
| 469 | OMAP3_CM_CLKOUT_CTRL_OFFSET); | ||
| 470 | } | ||
| 471 | #endif | ||
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h new file mode 100644 index 000000000000..5e9ea5bd60b9 --- /dev/null +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h | |||
| @@ -0,0 +1,147 @@ | |||
| 1 | /* | ||
| 2 | * OMAP2/3 Clock Management (CM) register definitions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007-2009 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2007-2010 Nokia Corporation | ||
| 6 | * Paul Walmsley | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | * The CM hardware modules on the OMAP2/3 are quite similar to each | ||
| 13 | * other. The CM modules/instances on OMAP4 are quite different, so | ||
| 14 | * they are handled in a separate file. | ||
| 15 | */ | ||
| 16 | #ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H | ||
| 17 | #define __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H | ||
| 18 | |||
| 19 | #include "prcm-common.h" | ||
| 20 | |||
| 21 | #define OMAP2420_CM_REGADDR(module, reg) \ | ||
| 22 | OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) | ||
| 23 | #define OMAP2430_CM_REGADDR(module, reg) \ | ||
| 24 | OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) | ||
| 25 | #define OMAP34XX_CM_REGADDR(module, reg) \ | ||
| 26 | OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) | ||
| 27 | |||
| 28 | |||
| 29 | /* | ||
| 30 | * OMAP3-specific global CM registers | ||
| 31 | * Use cm_{read,write}_reg() with these registers. | ||
| 32 | * These registers appear once per CM module. | ||
| 33 | */ | ||
| 34 | |||
| 35 | #define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000) | ||
| 36 | #define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010) | ||
| 37 | #define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c) | ||
| 38 | |||
| 39 | #define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070 | ||
| 40 | #define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070) | ||
| 41 | |||
| 42 | /* | ||
| 43 | * Module specific CM register offsets from CM_BASE + domain offset | ||
| 44 | * Use cm_{read,write}_mod_reg() with these registers. | ||
| 45 | * These register offsets generally appear in more than one PRCM submodule. | ||
| 46 | */ | ||
| 47 | |||
| 48 | /* Common between OMAP2 and OMAP3 */ | ||
| 49 | |||
| 50 | #define CM_FCLKEN 0x0000 | ||
| 51 | #define CM_FCLKEN1 CM_FCLKEN | ||
| 52 | #define CM_CLKEN CM_FCLKEN | ||
| 53 | #define CM_ICLKEN 0x0010 | ||
| 54 | #define CM_ICLKEN1 CM_ICLKEN | ||
| 55 | #define CM_ICLKEN2 0x0014 | ||
| 56 | #define CM_ICLKEN3 0x0018 | ||
| 57 | #define CM_IDLEST 0x0020 | ||
| 58 | #define CM_IDLEST1 CM_IDLEST | ||
| 59 | #define CM_IDLEST2 0x0024 | ||
| 60 | #define CM_AUTOIDLE 0x0030 | ||
| 61 | #define CM_AUTOIDLE1 CM_AUTOIDLE | ||
| 62 | #define CM_AUTOIDLE2 0x0034 | ||
| 63 | #define CM_AUTOIDLE3 0x0038 | ||
| 64 | #define CM_CLKSEL 0x0040 | ||
| 65 | #define CM_CLKSEL1 CM_CLKSEL | ||
| 66 | #define CM_CLKSEL2 0x0044 | ||
| 67 | #define OMAP2_CM_CLKSTCTRL 0x0048 | ||
| 68 | |||
| 69 | /* OMAP2-specific register offsets */ | ||
| 70 | |||
| 71 | #define OMAP24XX_CM_FCLKEN2 0x0004 | ||
| 72 | #define OMAP24XX_CM_ICLKEN4 0x001c | ||
| 73 | #define OMAP24XX_CM_AUTOIDLE4 0x003c | ||
| 74 | |||
| 75 | #define OMAP2430_CM_IDLEST3 0x0028 | ||
| 76 | |||
| 77 | /* OMAP3-specific register offsets */ | ||
| 78 | |||
| 79 | #define OMAP3430_CM_CLKEN_PLL 0x0004 | ||
| 80 | #define OMAP3430ES2_CM_CLKEN2 0x0004 | ||
| 81 | #define OMAP3430ES2_CM_FCLKEN3 0x0008 | ||
| 82 | #define OMAP3430_CM_IDLEST_PLL CM_IDLEST2 | ||
| 83 | #define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2 | ||
| 84 | #define OMAP3430ES2_CM_AUTOIDLE2_PLL CM_AUTOIDLE2 | ||
| 85 | #define OMAP3430_CM_CLKSEL1 CM_CLKSEL | ||
| 86 | #define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL | ||
| 87 | #define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2 | ||
| 88 | #define OMAP3430_CM_SLEEPDEP CM_CLKSEL2 | ||
| 89 | #define OMAP3430_CM_CLKSEL3 OMAP2_CM_CLKSTCTRL | ||
| 90 | #define OMAP3430_CM_CLKSTST 0x004c | ||
| 91 | #define OMAP3430ES2_CM_CLKSEL4 0x004c | ||
| 92 | #define OMAP3430ES2_CM_CLKSEL5 0x0050 | ||
| 93 | #define OMAP3430_CM_CLKSEL2_EMU 0x0050 | ||
| 94 | #define OMAP3430_CM_CLKSEL3_EMU 0x0054 | ||
| 95 | |||
| 96 | |||
| 97 | /* CM_IDLEST bit field values to indicate deasserted IdleReq */ | ||
| 98 | |||
| 99 | #define OMAP24XX_CM_IDLEST_VAL 0 | ||
| 100 | #define OMAP34XX_CM_IDLEST_VAL 1 | ||
| 101 | |||
| 102 | |||
| 103 | /* Clock management domain register get/set */ | ||
| 104 | |||
| 105 | #ifndef __ASSEMBLER__ | ||
| 106 | |||
| 107 | extern u32 omap2_cm_read_mod_reg(s16 module, u16 idx); | ||
| 108 | extern void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx); | ||
| 109 | extern u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); | ||
| 110 | |||
| 111 | extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, | ||
| 112 | u8 idlest_shift); | ||
| 113 | extern u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx); | ||
| 114 | extern u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx); | ||
| 115 | |||
| 116 | extern bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask); | ||
| 117 | extern void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask); | ||
| 118 | extern void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask); | ||
| 119 | |||
| 120 | extern void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask); | ||
| 121 | extern void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask); | ||
| 122 | extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask); | ||
| 123 | extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask); | ||
| 124 | |||
| 125 | #endif | ||
| 126 | |||
| 127 | /* CM register bits shared between 24XX and 3430 */ | ||
| 128 | |||
| 129 | /* CM_CLKSEL_GFX */ | ||
| 130 | #define OMAP_CLKSEL_GFX_SHIFT 0 | ||
| 131 | #define OMAP_CLKSEL_GFX_MASK (0x7 << 0) | ||
| 132 | |||
| 133 | /* CM_ICLKEN_GFX */ | ||
| 134 | #define OMAP_EN_GFX_SHIFT 0 | ||
| 135 | #define OMAP_EN_GFX_MASK (1 << 0) | ||
| 136 | |||
| 137 | /* CM_IDLEST_GFX */ | ||
| 138 | #define OMAP_ST_GFX_MASK (1 << 0) | ||
| 139 | |||
| 140 | |||
| 141 | /* Function prototypes */ | ||
| 142 | # ifndef __ASSEMBLER__ | ||
| 143 | extern void omap3_cm_save_context(void); | ||
| 144 | extern void omap3_cm_restore_context(void); | ||
| 145 | # endif | ||
| 146 | |||
| 147 | #endif | ||
diff --git a/arch/arm/mach-omap2/cm44xx.c b/arch/arm/mach-omap2/cm44xx.c new file mode 100644 index 000000000000..e96f53ea01a1 --- /dev/null +++ b/arch/arm/mach-omap2/cm44xx.c | |||
| @@ -0,0 +1,52 @@ | |||
| 1 | /* | ||
| 2 | * OMAP4 CM1, CM2 module low-level functions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Nokia Corporation | ||
| 5 | * Paul Walmsley | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | * | ||
| 11 | * These functions are intended to be used only by the cminst44xx.c file. | ||
| 12 | * XXX Perhaps we should just move them there and make them static. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/kernel.h> | ||
| 16 | #include <linux/types.h> | ||
| 17 | #include <linux/errno.h> | ||
| 18 | #include <linux/err.h> | ||
| 19 | #include <linux/io.h> | ||
| 20 | |||
| 21 | #include <plat/common.h> | ||
| 22 | |||
| 23 | #include "cm.h" | ||
| 24 | #include "cm1_44xx.h" | ||
| 25 | #include "cm2_44xx.h" | ||
| 26 | #include "cm-regbits-44xx.h" | ||
| 27 | |||
| 28 | /* CM1 hardware module low-level functions */ | ||
| 29 | |||
| 30 | /* Read a register in CM1 */ | ||
| 31 | u32 omap4_cm1_read_inst_reg(s16 inst, u16 reg) | ||
| 32 | { | ||
| 33 | return __raw_readl(OMAP44XX_CM1_REGADDR(inst, reg)); | ||
| 34 | } | ||
| 35 | |||
| 36 | /* Write into a register in CM1 */ | ||
| 37 | void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 reg) | ||
| 38 | { | ||
| 39 | __raw_writel(val, OMAP44XX_CM1_REGADDR(inst, reg)); | ||
| 40 | } | ||
| 41 | |||
| 42 | /* Read a register in CM2 */ | ||
| 43 | u32 omap4_cm2_read_inst_reg(s16 inst, u16 reg) | ||
| 44 | { | ||
| 45 | return __raw_readl(OMAP44XX_CM2_REGADDR(inst, reg)); | ||
| 46 | } | ||
| 47 | |||
| 48 | /* Write into a register in CM2 */ | ||
| 49 | void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 reg) | ||
| 50 | { | ||
| 51 | __raw_writel(val, OMAP44XX_CM2_REGADDR(inst, reg)); | ||
| 52 | } | ||
diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h index 3c35a87cb90c..48fc3f426fbd 100644 --- a/arch/arm/mach-omap2/cm44xx.h +++ b/arch/arm/mach-omap2/cm44xx.h | |||
| @@ -1,667 +1,31 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * OMAP44xx CM1 & CM2 instance offset macros | 2 | * OMAP4 Clock Management (CM) definitions |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. | 4 | * Copyright (C) 2007-2009 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2009-2010 Nokia Corporation | 5 | * Copyright (C) 2007-2009 Nokia Corporation |
| 6 | * | 6 | * |
| 7 | * Paul Walmsley (paul@pwsan.com) | 7 | * Written by Paul Walmsley |
| 8 | * Rajendra Nayak (rnayak@ti.com) | ||
| 9 | * Benoit Cousson (b-cousson@ti.com) | ||
| 10 | * | ||
| 11 | * This file is automatically generated from the OMAP hardware databases. | ||
| 12 | * We respectfully ask that any modifications to this file be coordinated | ||
| 13 | * with the public linux-omap@vger.kernel.org mailing list and the | ||
| 14 | * authors above to ensure that the autogeneration scripts are kept | ||
| 15 | * up-to-date with the file contents. | ||
| 16 | * | 8 | * |
| 17 | * This program is free software; you can redistribute it and/or modify | 9 | * This program is free software; you can redistribute it and/or modify |
| 18 | * it under the terms of the GNU General Public License version 2 as | 10 | * it under the terms of the GNU General Public License version 2 as |
| 19 | * published by the Free Software Foundation. | 11 | * published by the Free Software Foundation. |
| 12 | * | ||
| 13 | * OMAP4 has two separate CM blocks, CM1 and CM2. This file contains | ||
| 14 | * macros and function prototypes that are applicable to both. | ||
| 20 | */ | 15 | */ |
| 16 | #ifndef __ARCH_ASM_MACH_OMAP2_CM44XX_H | ||
| 17 | #define __ARCH_ASM_MACH_OMAP2_CM44XX_H | ||
| 21 | 18 | ||
| 22 | #ifndef __ARCH_ARM_MACH_OMAP2_CM44XX_H | ||
| 23 | #define __ARCH_ARM_MACH_OMAP2_CM44XX_H | ||
| 24 | |||
| 25 | |||
| 26 | /* CM1 */ | ||
| 27 | |||
| 28 | /* CM1.OCP_SOCKET_CM1 register offsets */ | ||
| 29 | #define OMAP4_REVISION_CM1_OFFSET 0x0000 | ||
| 30 | #define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0000) | ||
| 31 | #define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET 0x0040 | ||
| 32 | #define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0040) | ||
| 33 | |||
| 34 | /* CM1.CKGEN_CM1 register offsets */ | ||
| 35 | #define OMAP4_CM_CLKSEL_CORE_OFFSET 0x0000 | ||
| 36 | #define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0000) | ||
| 37 | #define OMAP4_CM_CLKSEL_ABE_OFFSET 0x0008 | ||
| 38 | #define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0008) | ||
| 39 | #define OMAP4_CM_DLL_CTRL_OFFSET 0x0010 | ||
| 40 | #define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0010) | ||
| 41 | #define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020 | ||
| 42 | #define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0020) | ||
| 43 | #define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET 0x0024 | ||
| 44 | #define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0024) | ||
| 45 | #define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028 | ||
| 46 | #define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0028) | ||
| 47 | #define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c | ||
| 48 | #define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x002c) | ||
| 49 | #define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030 | ||
| 50 | #define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0030) | ||
| 51 | #define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034 | ||
| 52 | #define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0034) | ||
| 53 | #define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET 0x0038 | ||
| 54 | #define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0038) | ||
| 55 | #define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET 0x003c | ||
| 56 | #define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x003c) | ||
| 57 | #define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET 0x0040 | ||
| 58 | #define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0040) | ||
| 59 | #define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET 0x0044 | ||
| 60 | #define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0044) | ||
| 61 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048 | ||
| 62 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0048) | ||
| 63 | #define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c | ||
| 64 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x004c) | ||
| 65 | #define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050 | ||
| 66 | #define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0050) | ||
| 67 | #define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060 | ||
| 68 | #define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0060) | ||
| 69 | #define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET 0x0064 | ||
| 70 | #define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0064) | ||
| 71 | #define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068 | ||
| 72 | #define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0068) | ||
| 73 | #define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c | ||
| 74 | #define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x006c) | ||
| 75 | #define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070 | ||
| 76 | #define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0070) | ||
| 77 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088 | ||
| 78 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0088) | ||
| 79 | #define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c | ||
| 80 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x008c) | ||
| 81 | #define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c | ||
| 82 | #define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x009c) | ||
| 83 | #define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0 | ||
| 84 | #define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a0) | ||
| 85 | #define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4 | ||
| 86 | #define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a4) | ||
| 87 | #define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8 | ||
| 88 | #define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a8) | ||
| 89 | #define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac | ||
| 90 | #define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ac) | ||
| 91 | #define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET 0x00b8 | ||
| 92 | #define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00b8) | ||
| 93 | #define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET 0x00bc | ||
| 94 | #define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00bc) | ||
| 95 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8 | ||
| 96 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00c8) | ||
| 97 | #define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc | ||
| 98 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00cc) | ||
| 99 | #define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc | ||
| 100 | #define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00dc) | ||
| 101 | #define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0 | ||
| 102 | #define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e0) | ||
| 103 | #define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4 | ||
| 104 | #define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e4) | ||
| 105 | #define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8 | ||
| 106 | #define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e8) | ||
| 107 | #define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec | ||
| 108 | #define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ec) | ||
| 109 | #define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0 | ||
| 110 | #define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f0) | ||
| 111 | #define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4 | ||
| 112 | #define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f4) | ||
| 113 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108 | ||
| 114 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0108) | ||
| 115 | #define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c | ||
| 116 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x010c) | ||
| 117 | #define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120 | ||
| 118 | #define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0120) | ||
| 119 | #define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124 | ||
| 120 | #define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0124) | ||
| 121 | #define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET 0x0128 | ||
| 122 | #define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0128) | ||
| 123 | #define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET 0x012c | ||
| 124 | #define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x012c) | ||
| 125 | #define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET 0x0130 | ||
| 126 | #define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0130) | ||
| 127 | #define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET 0x0138 | ||
| 128 | #define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0138) | ||
| 129 | #define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET 0x013c | ||
| 130 | #define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x013c) | ||
| 131 | #define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET 0x0140 | ||
| 132 | #define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0140) | ||
| 133 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148 | ||
| 134 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0148) | ||
| 135 | #define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c | ||
| 136 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x014c) | ||
| 137 | #define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160 | ||
| 138 | #define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0160) | ||
| 139 | #define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164 | ||
| 140 | #define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0164) | ||
| 141 | #define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET 0x0170 | ||
| 142 | #define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0170) | ||
| 143 | #define OMAP4_CM_RESTORE_ST_OFFSET 0x0180 | ||
| 144 | #define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0180) | ||
| 145 | |||
| 146 | /* CM1.MPU_CM1 register offsets */ | ||
| 147 | #define OMAP4_CM_MPU_CLKSTCTRL_OFFSET 0x0000 | ||
| 148 | #define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0000) | ||
| 149 | #define OMAP4_CM_MPU_STATICDEP_OFFSET 0x0004 | ||
| 150 | #define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0004) | ||
| 151 | #define OMAP4_CM_MPU_DYNAMICDEP_OFFSET 0x0008 | ||
| 152 | #define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0008) | ||
| 153 | #define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 | ||
| 154 | #define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0020) | ||
| 155 | |||
| 156 | /* CM1.TESLA_CM1 register offsets */ | ||
| 157 | #define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET 0x0000 | ||
| 158 | #define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0000) | ||
| 159 | #define OMAP4_CM_TESLA_STATICDEP_OFFSET 0x0004 | ||
| 160 | #define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0004) | ||
| 161 | #define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET 0x0008 | ||
| 162 | #define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0008) | ||
| 163 | #define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET 0x0020 | ||
| 164 | #define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0020) | ||
| 165 | |||
| 166 | /* CM1.ABE_CM1 register offsets */ | ||
| 167 | #define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET 0x0000 | ||
| 168 | #define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0000) | ||
| 169 | #define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET 0x0020 | ||
| 170 | #define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0020) | ||
| 171 | #define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET 0x0028 | ||
| 172 | #define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0028) | ||
| 173 | #define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET 0x0030 | ||
| 174 | #define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0030) | ||
| 175 | #define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET 0x0038 | ||
| 176 | #define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0038) | ||
| 177 | #define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET 0x0040 | ||
| 178 | #define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0040) | ||
| 179 | #define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048 | ||
| 180 | #define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0048) | ||
| 181 | #define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050 | ||
| 182 | #define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0050) | ||
| 183 | #define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058 | ||
| 184 | #define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0058) | ||
| 185 | #define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET 0x0060 | ||
| 186 | #define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0060) | ||
| 187 | #define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET 0x0068 | ||
| 188 | #define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0068) | ||
| 189 | #define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET 0x0070 | ||
| 190 | #define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0070) | ||
| 191 | #define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET 0x0078 | ||
| 192 | #define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0078) | ||
| 193 | #define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET 0x0080 | ||
| 194 | #define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0080) | ||
| 195 | #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 | ||
| 196 | #define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0088) | ||
| 197 | |||
| 198 | /* CM1.RESTORE_CM1 register offsets */ | ||
| 199 | #define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET 0x0000 | ||
| 200 | #define OMAP4430_CM_CLKSEL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0000) | ||
| 201 | #define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET 0x0004 | ||
| 202 | #define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0004) | ||
| 203 | #define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET 0x0008 | ||
| 204 | #define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0008) | ||
| 205 | #define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET 0x000c | ||
| 206 | #define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x000c) | ||
| 207 | #define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET 0x0010 | ||
| 208 | #define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0010) | ||
| 209 | #define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET 0x0014 | ||
| 210 | #define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0014) | ||
| 211 | #define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET 0x0018 | ||
| 212 | #define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0018) | ||
| 213 | #define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET 0x001c | ||
| 214 | #define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x001c) | ||
| 215 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET 0x0020 | ||
| 216 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0020) | ||
| 217 | #define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE_OFFSET 0x0024 | ||
| 218 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0024) | ||
| 219 | #define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET 0x0028 | ||
| 220 | #define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0028) | ||
| 221 | #define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET 0x002c | ||
| 222 | #define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x002c) | ||
| 223 | #define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET 0x0030 | ||
| 224 | #define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0030) | ||
| 225 | #define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET 0x0034 | ||
| 226 | #define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0034) | ||
| 227 | #define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET 0x0038 | ||
| 228 | #define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0038) | ||
| 229 | #define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET 0x003c | ||
| 230 | #define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x003c) | ||
| 231 | #define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET 0x0040 | ||
| 232 | #define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0040) | ||
| 233 | |||
| 234 | /* CM2 */ | ||
| 235 | |||
| 236 | /* CM2.OCP_SOCKET_CM2 register offsets */ | ||
| 237 | #define OMAP4_REVISION_CM2_OFFSET 0x0000 | ||
| 238 | #define OMAP4430_REVISION_CM2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0000) | ||
| 239 | #define OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET 0x0040 | ||
| 240 | #define OMAP4430_CM_CM2_PROFILING_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0040) | ||
| 241 | |||
| 242 | /* CM2.CKGEN_CM2 register offsets */ | ||
| 243 | #define OMAP4_CM_CLKSEL_DUCATI_ISS_ROOT_OFFSET 0x0000 | ||
| 244 | #define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0000) | ||
| 245 | #define OMAP4_CM_CLKSEL_USB_60MHZ_OFFSET 0x0004 | ||
| 246 | #define OMAP4430_CM_CLKSEL_USB_60MHZ OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0004) | ||
| 247 | #define OMAP4_CM_SCALE_FCLK_OFFSET 0x0008 | ||
| 248 | #define OMAP4430_CM_SCALE_FCLK OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0008) | ||
| 249 | #define OMAP4_CM_CORE_DVFS_PERF1_OFFSET 0x0010 | ||
| 250 | #define OMAP4430_CM_CORE_DVFS_PERF1 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0010) | ||
| 251 | #define OMAP4_CM_CORE_DVFS_PERF2_OFFSET 0x0014 | ||
| 252 | #define OMAP4430_CM_CORE_DVFS_PERF2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0014) | ||
| 253 | #define OMAP4_CM_CORE_DVFS_PERF3_OFFSET 0x0018 | ||
| 254 | #define OMAP4430_CM_CORE_DVFS_PERF3 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0018) | ||
| 255 | #define OMAP4_CM_CORE_DVFS_PERF4_OFFSET 0x001c | ||
| 256 | #define OMAP4430_CM_CORE_DVFS_PERF4 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x001c) | ||
| 257 | #define OMAP4_CM_CORE_DVFS_CURRENT_OFFSET 0x0024 | ||
| 258 | #define OMAP4430_CM_CORE_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0024) | ||
| 259 | #define OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET 0x0028 | ||
| 260 | #define OMAP4430_CM_IVA_DVFS_PERF_TESLA OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0028) | ||
| 261 | #define OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET 0x002c | ||
| 262 | #define OMAP4430_CM_IVA_DVFS_PERF_IVAHD OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x002c) | ||
| 263 | #define OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET 0x0030 | ||
| 264 | #define OMAP4430_CM_IVA_DVFS_PERF_ABE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0030) | ||
| 265 | #define OMAP4_CM_IVA_DVFS_CURRENT_OFFSET 0x0038 | ||
| 266 | #define OMAP4430_CM_IVA_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0038) | ||
| 267 | #define OMAP4_CM_CLKMODE_DPLL_PER_OFFSET 0x0040 | ||
| 268 | #define OMAP4430_CM_CLKMODE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0040) | ||
| 269 | #define OMAP4_CM_IDLEST_DPLL_PER_OFFSET 0x0044 | ||
| 270 | #define OMAP4430_CM_IDLEST_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0044) | ||
| 271 | #define OMAP4_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0048 | ||
| 272 | #define OMAP4430_CM_AUTOIDLE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0048) | ||
| 273 | #define OMAP4_CM_CLKSEL_DPLL_PER_OFFSET 0x004c | ||
| 274 | #define OMAP4430_CM_CLKSEL_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x004c) | ||
| 275 | #define OMAP4_CM_DIV_M2_DPLL_PER_OFFSET 0x0050 | ||
| 276 | #define OMAP4430_CM_DIV_M2_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0050) | ||
| 277 | #define OMAP4_CM_DIV_M3_DPLL_PER_OFFSET 0x0054 | ||
| 278 | #define OMAP4430_CM_DIV_M3_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0054) | ||
| 279 | #define OMAP4_CM_DIV_M4_DPLL_PER_OFFSET 0x0058 | ||
| 280 | #define OMAP4430_CM_DIV_M4_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0058) | ||
| 281 | #define OMAP4_CM_DIV_M5_DPLL_PER_OFFSET 0x005c | ||
| 282 | #define OMAP4430_CM_DIV_M5_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x005c) | ||
| 283 | #define OMAP4_CM_DIV_M6_DPLL_PER_OFFSET 0x0060 | ||
| 284 | #define OMAP4430_CM_DIV_M6_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0060) | ||
| 285 | #define OMAP4_CM_DIV_M7_DPLL_PER_OFFSET 0x0064 | ||
| 286 | #define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0064) | ||
| 287 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068 | ||
| 288 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0068) | ||
| 289 | #define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c | ||
| 290 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x006c) | ||
| 291 | #define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080 | ||
| 292 | #define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0080) | ||
| 293 | #define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084 | ||
| 294 | #define OMAP4430_CM_IDLEST_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0084) | ||
| 295 | #define OMAP4_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0088 | ||
| 296 | #define OMAP4430_CM_AUTOIDLE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0088) | ||
| 297 | #define OMAP4_CM_CLKSEL_DPLL_USB_OFFSET 0x008c | ||
| 298 | #define OMAP4430_CM_CLKSEL_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x008c) | ||
| 299 | #define OMAP4_CM_DIV_M2_DPLL_USB_OFFSET 0x0090 | ||
| 300 | #define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0090) | ||
| 301 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8 | ||
| 302 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00a8) | ||
| 303 | #define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac | ||
| 304 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ac) | ||
| 305 | #define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4 | ||
| 306 | #define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00b4) | ||
| 307 | #define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0 | ||
| 308 | #define OMAP4430_CM_CLKMODE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c0) | ||
| 309 | #define OMAP4_CM_IDLEST_DPLL_UNIPRO_OFFSET 0x00c4 | ||
| 310 | #define OMAP4430_CM_IDLEST_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c4) | ||
| 311 | #define OMAP4_CM_AUTOIDLE_DPLL_UNIPRO_OFFSET 0x00c8 | ||
| 312 | #define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c8) | ||
| 313 | #define OMAP4_CM_CLKSEL_DPLL_UNIPRO_OFFSET 0x00cc | ||
| 314 | #define OMAP4430_CM_CLKSEL_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00cc) | ||
| 315 | #define OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET 0x00d0 | ||
| 316 | #define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00d0) | ||
| 317 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8 | ||
| 318 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00e8) | ||
| 319 | #define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec | ||
| 320 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ec) | ||
| 321 | |||
| 322 | /* CM2.ALWAYS_ON_CM2 register offsets */ | ||
| 323 | #define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000 | ||
| 324 | #define OMAP4430_CM_ALWON_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0000) | ||
| 325 | #define OMAP4_CM_ALWON_MDMINTC_CLKCTRL_OFFSET 0x0020 | ||
| 326 | #define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0020) | ||
| 327 | #define OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET 0x0028 | ||
| 328 | #define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0028) | ||
| 329 | #define OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET 0x0030 | ||
| 330 | #define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0030) | ||
| 331 | #define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET 0x0038 | ||
| 332 | #define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0038) | ||
| 333 | #define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET 0x0040 | ||
| 334 | #define OMAP4430_CM_ALWON_USBPHY_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0040) | ||
| 335 | |||
| 336 | /* CM2.CORE_CM2 register offsets */ | ||
| 337 | #define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET 0x0000 | ||
| 338 | #define OMAP4430_CM_L3_1_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0000) | ||
| 339 | #define OMAP4_CM_L3_1_DYNAMICDEP_OFFSET 0x0008 | ||
| 340 | #define OMAP4430_CM_L3_1_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0008) | ||
| 341 | #define OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET 0x0020 | ||
| 342 | #define OMAP4430_CM_L3_1_L3_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0020) | ||
| 343 | #define OMAP4_CM_L3_2_CLKSTCTRL_OFFSET 0x0100 | ||
| 344 | #define OMAP4430_CM_L3_2_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0100) | ||
| 345 | #define OMAP4_CM_L3_2_DYNAMICDEP_OFFSET 0x0108 | ||
| 346 | #define OMAP4430_CM_L3_2_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0108) | ||
| 347 | #define OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET 0x0120 | ||
| 348 | #define OMAP4430_CM_L3_2_L3_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0120) | ||
| 349 | #define OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET 0x0128 | ||
| 350 | #define OMAP4430_CM_L3_2_GPMC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0128) | ||
| 351 | #define OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET 0x0130 | ||
| 352 | #define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0130) | ||
| 353 | #define OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET 0x0200 | ||
| 354 | #define OMAP4430_CM_DUCATI_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0200) | ||
| 355 | #define OMAP4_CM_DUCATI_STATICDEP_OFFSET 0x0204 | ||
| 356 | #define OMAP4430_CM_DUCATI_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0204) | ||
| 357 | #define OMAP4_CM_DUCATI_DYNAMICDEP_OFFSET 0x0208 | ||
| 358 | #define OMAP4430_CM_DUCATI_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0208) | ||
| 359 | #define OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET 0x0220 | ||
| 360 | #define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0220) | ||
| 361 | #define OMAP4_CM_SDMA_CLKSTCTRL_OFFSET 0x0300 | ||
| 362 | #define OMAP4430_CM_SDMA_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0300) | ||
| 363 | #define OMAP4_CM_SDMA_STATICDEP_OFFSET 0x0304 | ||
| 364 | #define OMAP4430_CM_SDMA_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0304) | ||
| 365 | #define OMAP4_CM_SDMA_DYNAMICDEP_OFFSET 0x0308 | ||
| 366 | #define OMAP4430_CM_SDMA_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0308) | ||
| 367 | #define OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET 0x0320 | ||
| 368 | #define OMAP4430_CM_SDMA_SDMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0320) | ||
| 369 | #define OMAP4_CM_MEMIF_CLKSTCTRL_OFFSET 0x0400 | ||
| 370 | #define OMAP4430_CM_MEMIF_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0400) | ||
| 371 | #define OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET 0x0420 | ||
| 372 | #define OMAP4430_CM_MEMIF_DMM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0420) | ||
| 373 | #define OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET 0x0428 | ||
| 374 | #define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0428) | ||
| 375 | #define OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET 0x0430 | ||
| 376 | #define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0430) | ||
| 377 | #define OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET 0x0438 | ||
| 378 | #define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0438) | ||
| 379 | #define OMAP4_CM_MEMIF_DLL_CLKCTRL_OFFSET 0x0440 | ||
| 380 | #define OMAP4430_CM_MEMIF_DLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0440) | ||
| 381 | #define OMAP4_CM_MEMIF_EMIF_H1_CLKCTRL_OFFSET 0x0450 | ||
| 382 | #define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0450) | ||
| 383 | #define OMAP4_CM_MEMIF_EMIF_H2_CLKCTRL_OFFSET 0x0458 | ||
| 384 | #define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0458) | ||
| 385 | #define OMAP4_CM_MEMIF_DLL_H_CLKCTRL_OFFSET 0x0460 | ||
| 386 | #define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0460) | ||
| 387 | #define OMAP4_CM_D2D_CLKSTCTRL_OFFSET 0x0500 | ||
| 388 | #define OMAP4430_CM_D2D_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0500) | ||
| 389 | #define OMAP4_CM_D2D_STATICDEP_OFFSET 0x0504 | ||
| 390 | #define OMAP4430_CM_D2D_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0504) | ||
| 391 | #define OMAP4_CM_D2D_DYNAMICDEP_OFFSET 0x0508 | ||
| 392 | #define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0508) | ||
| 393 | #define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520 | ||
| 394 | #define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0520) | ||
| 395 | #define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET 0x0528 | ||
| 396 | #define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0528) | ||
| 397 | #define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530 | ||
| 398 | #define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0530) | ||
| 399 | #define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600 | ||
| 400 | #define OMAP4430_CM_L4CFG_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0600) | ||
| 401 | #define OMAP4_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608 | ||
| 402 | #define OMAP4430_CM_L4CFG_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0608) | ||
| 403 | #define OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620 | ||
| 404 | #define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0620) | ||
| 405 | #define OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET 0x0628 | ||
| 406 | #define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0628) | ||
| 407 | #define OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET 0x0630 | ||
| 408 | #define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0630) | ||
| 409 | #define OMAP4_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638 | ||
| 410 | #define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0638) | ||
| 411 | #define OMAP4_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700 | ||
| 412 | #define OMAP4430_CM_L3INSTR_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0700) | ||
| 413 | #define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET 0x0720 | ||
| 414 | #define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0720) | ||
| 415 | #define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728 | ||
| 416 | #define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0728) | ||
| 417 | #define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET 0x0740 | ||
| 418 | #define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0740) | ||
| 419 | |||
| 420 | /* CM2.IVAHD_CM2 register offsets */ | ||
| 421 | #define OMAP4_CM_IVAHD_CLKSTCTRL_OFFSET 0x0000 | ||
| 422 | #define OMAP4430_CM_IVAHD_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0000) | ||
| 423 | #define OMAP4_CM_IVAHD_STATICDEP_OFFSET 0x0004 | ||
| 424 | #define OMAP4430_CM_IVAHD_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0004) | ||
| 425 | #define OMAP4_CM_IVAHD_DYNAMICDEP_OFFSET 0x0008 | ||
| 426 | #define OMAP4430_CM_IVAHD_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0008) | ||
| 427 | #define OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET 0x0020 | ||
| 428 | #define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0020) | ||
| 429 | #define OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET 0x0028 | ||
| 430 | #define OMAP4430_CM_IVAHD_SL2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0028) | ||
| 431 | |||
| 432 | /* CM2.CAM_CM2 register offsets */ | ||
| 433 | #define OMAP4_CM_CAM_CLKSTCTRL_OFFSET 0x0000 | ||
| 434 | #define OMAP4430_CM_CAM_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0000) | ||
| 435 | #define OMAP4_CM_CAM_STATICDEP_OFFSET 0x0004 | ||
| 436 | #define OMAP4430_CM_CAM_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0004) | ||
| 437 | #define OMAP4_CM_CAM_DYNAMICDEP_OFFSET 0x0008 | ||
| 438 | #define OMAP4430_CM_CAM_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0008) | ||
| 439 | #define OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET 0x0020 | ||
| 440 | #define OMAP4430_CM_CAM_ISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0020) | ||
| 441 | #define OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET 0x0028 | ||
| 442 | #define OMAP4430_CM_CAM_FDIF_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0028) | ||
| 443 | |||
| 444 | /* CM2.DSS_CM2 register offsets */ | ||
| 445 | #define OMAP4_CM_DSS_CLKSTCTRL_OFFSET 0x0000 | ||
| 446 | #define OMAP4430_CM_DSS_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0000) | ||
| 447 | #define OMAP4_CM_DSS_STATICDEP_OFFSET 0x0004 | ||
| 448 | #define OMAP4430_CM_DSS_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0004) | ||
| 449 | #define OMAP4_CM_DSS_DYNAMICDEP_OFFSET 0x0008 | ||
| 450 | #define OMAP4430_CM_DSS_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0008) | ||
| 451 | #define OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020 | ||
| 452 | #define OMAP4430_CM_DSS_DSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0020) | ||
| 453 | #define OMAP4_CM_DSS_DEISS_CLKCTRL_OFFSET 0x0028 | ||
| 454 | #define OMAP4430_CM_DSS_DEISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0028) | ||
| 455 | 19 | ||
| 456 | /* CM2.GFX_CM2 register offsets */ | 20 | #include "prcm-common.h" |
| 457 | #define OMAP4_CM_GFX_CLKSTCTRL_OFFSET 0x0000 | 21 | #include "cm.h" |
| 458 | #define OMAP4430_CM_GFX_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0000) | ||
| 459 | #define OMAP4_CM_GFX_STATICDEP_OFFSET 0x0004 | ||
| 460 | #define OMAP4430_CM_GFX_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0004) | ||
| 461 | #define OMAP4_CM_GFX_DYNAMICDEP_OFFSET 0x0008 | ||
| 462 | #define OMAP4430_CM_GFX_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0008) | ||
| 463 | #define OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020 | ||
| 464 | #define OMAP4430_CM_GFX_GFX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0020) | ||
| 465 | 22 | ||
| 466 | /* CM2.L3INIT_CM2 register offsets */ | 23 | #define OMAP4_CM_CLKSTCTRL 0x0000 |
| 467 | #define OMAP4_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000 | ||
| 468 | #define OMAP4430_CM_L3INIT_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0000) | ||
| 469 | #define OMAP4_CM_L3INIT_STATICDEP_OFFSET 0x0004 | ||
| 470 | #define OMAP4430_CM_L3INIT_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0004) | ||
| 471 | #define OMAP4_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008 | ||
| 472 | #define OMAP4430_CM_L3INIT_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0008) | ||
| 473 | #define OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028 | ||
| 474 | #define OMAP4430_CM_L3INIT_MMC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0028) | ||
| 475 | #define OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030 | ||
| 476 | #define OMAP4430_CM_L3INIT_MMC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0030) | ||
| 477 | #define OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET 0x0038 | ||
| 478 | #define OMAP4430_CM_L3INIT_HSI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0038) | ||
| 479 | #define OMAP4_CM_L3INIT_UNIPRO1_CLKCTRL_OFFSET 0x0040 | ||
| 480 | #define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0040) | ||
| 481 | #define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET 0x0058 | ||
| 482 | #define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0058) | ||
| 483 | #define OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET 0x0060 | ||
| 484 | #define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0060) | ||
| 485 | #define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET 0x0068 | ||
| 486 | #define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0068) | ||
| 487 | #define OMAP4_CM_L3INIT_P1500_CLKCTRL_OFFSET 0x0078 | ||
| 488 | #define OMAP4430_CM_L3INIT_P1500_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0078) | ||
| 489 | #define OMAP4_CM_L3INIT_EMAC_CLKCTRL_OFFSET 0x0080 | ||
| 490 | #define OMAP4430_CM_L3INIT_EMAC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0080) | ||
| 491 | #define OMAP4_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088 | ||
| 492 | #define OMAP4430_CM_L3INIT_SATA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0088) | ||
| 493 | #define OMAP4_CM_L3INIT_TPPSS_CLKCTRL_OFFSET 0x0090 | ||
| 494 | #define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0090) | ||
| 495 | #define OMAP4_CM_L3INIT_PCIESS_CLKCTRL_OFFSET 0x0098 | ||
| 496 | #define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0098) | ||
| 497 | #define OMAP4_CM_L3INIT_CCPTX_CLKCTRL_OFFSET 0x00a8 | ||
| 498 | #define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00a8) | ||
| 499 | #define OMAP4_CM_L3INIT_XHPI_CLKCTRL_OFFSET 0x00c0 | ||
| 500 | #define OMAP4430_CM_L3INIT_XHPI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c0) | ||
| 501 | #define OMAP4_CM_L3INIT_MMC6_CLKCTRL_OFFSET 0x00c8 | ||
| 502 | #define OMAP4430_CM_L3INIT_MMC6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c8) | ||
| 503 | #define OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET 0x00d0 | ||
| 504 | #define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00d0) | ||
| 505 | #define OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET 0x00e0 | ||
| 506 | #define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00e0) | ||
| 507 | 24 | ||
| 508 | /* CM2.L4PER_CM2 register offsets */ | 25 | /* Function prototypes */ |
| 509 | #define OMAP4_CM_L4PER_CLKSTCTRL_OFFSET 0x0000 | 26 | # ifndef __ASSEMBLER__ |
| 510 | #define OMAP4430_CM_L4PER_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0000) | ||
| 511 | #define OMAP4_CM_L4PER_DYNAMICDEP_OFFSET 0x0008 | ||
| 512 | #define OMAP4430_CM_L4PER_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0008) | ||
| 513 | #define OMAP4_CM_L4PER_ADC_CLKCTRL_OFFSET 0x0020 | ||
| 514 | #define OMAP4430_CM_L4PER_ADC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0020) | ||
| 515 | #define OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET 0x0028 | ||
| 516 | #define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0028) | ||
| 517 | #define OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET 0x0030 | ||
| 518 | #define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0030) | ||
| 519 | #define OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET 0x0038 | ||
| 520 | #define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0038) | ||
| 521 | #define OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET 0x0040 | ||
| 522 | #define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0040) | ||
| 523 | #define OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET 0x0048 | ||
| 524 | #define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0048) | ||
| 525 | #define OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET 0x0050 | ||
| 526 | #define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0050) | ||
| 527 | #define OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058 | ||
| 528 | #define OMAP4430_CM_L4PER_ELM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0058) | ||
| 529 | #define OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060 | ||
| 530 | #define OMAP4430_CM_L4PER_GPIO2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0060) | ||
| 531 | #define OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068 | ||
| 532 | #define OMAP4430_CM_L4PER_GPIO3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0068) | ||
| 533 | #define OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070 | ||
| 534 | #define OMAP4430_CM_L4PER_GPIO4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0070) | ||
| 535 | #define OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078 | ||
| 536 | #define OMAP4430_CM_L4PER_GPIO5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0078) | ||
| 537 | #define OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080 | ||
| 538 | #define OMAP4430_CM_L4PER_GPIO6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0080) | ||
| 539 | #define OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088 | ||
| 540 | #define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0088) | ||
| 541 | #define OMAP4_CM_L4PER_HECC1_CLKCTRL_OFFSET 0x0090 | ||
| 542 | #define OMAP4430_CM_L4PER_HECC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0090) | ||
| 543 | #define OMAP4_CM_L4PER_HECC2_CLKCTRL_OFFSET 0x0098 | ||
| 544 | #define OMAP4430_CM_L4PER_HECC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0098) | ||
| 545 | #define OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0 | ||
| 546 | #define OMAP4430_CM_L4PER_I2C1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a0) | ||
| 547 | #define OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8 | ||
| 548 | #define OMAP4430_CM_L4PER_I2C2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a8) | ||
| 549 | #define OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0 | ||
| 550 | #define OMAP4430_CM_L4PER_I2C3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b0) | ||
| 551 | #define OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8 | ||
| 552 | #define OMAP4430_CM_L4PER_I2C4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b8) | ||
| 553 | #define OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET 0x00c0 | ||
| 554 | #define OMAP4430_CM_L4PER_L4PER_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00c0) | ||
| 555 | #define OMAP4_CM_L4PER_MCASP2_CLKCTRL_OFFSET 0x00d0 | ||
| 556 | #define OMAP4430_CM_L4PER_MCASP2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d0) | ||
| 557 | #define OMAP4_CM_L4PER_MCASP3_CLKCTRL_OFFSET 0x00d8 | ||
| 558 | #define OMAP4430_CM_L4PER_MCASP3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d8) | ||
| 559 | #define OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET 0x00e0 | ||
| 560 | #define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e0) | ||
| 561 | #define OMAP4_CM_L4PER_MGATE_CLKCTRL_OFFSET 0x00e8 | ||
| 562 | #define OMAP4430_CM_L4PER_MGATE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e8) | ||
| 563 | #define OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0 | ||
| 564 | #define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f0) | ||
| 565 | #define OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8 | ||
| 566 | #define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f8) | ||
| 567 | #define OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100 | ||
| 568 | #define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0100) | ||
| 569 | #define OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108 | ||
| 570 | #define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0108) | ||
| 571 | #define OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET 0x0120 | ||
| 572 | #define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0120) | ||
| 573 | #define OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET 0x0128 | ||
| 574 | #define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0128) | ||
| 575 | #define OMAP4_CM_L4PER_MSPROHG_CLKCTRL_OFFSET 0x0130 | ||
| 576 | #define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0130) | ||
| 577 | #define OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET 0x0138 | ||
| 578 | #define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0138) | ||
| 579 | #define OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140 | ||
| 580 | #define OMAP4430_CM_L4PER_UART1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0140) | ||
| 581 | #define OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148 | ||
| 582 | #define OMAP4430_CM_L4PER_UART2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0148) | ||
| 583 | #define OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150 | ||
| 584 | #define OMAP4430_CM_L4PER_UART3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0150) | ||
| 585 | #define OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158 | ||
| 586 | #define OMAP4430_CM_L4PER_UART4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0158) | ||
| 587 | #define OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET 0x0160 | ||
| 588 | #define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0160) | ||
| 589 | #define OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0168 | ||
| 590 | #define OMAP4430_CM_L4PER_I2C5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0168) | ||
| 591 | #define OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180 | ||
| 592 | #define OMAP4430_CM_L4SEC_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0180) | ||
| 593 | #define OMAP4_CM_L4SEC_STATICDEP_OFFSET 0x0184 | ||
| 594 | #define OMAP4430_CM_L4SEC_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0184) | ||
| 595 | #define OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188 | ||
| 596 | #define OMAP4430_CM_L4SEC_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0188) | ||
| 597 | #define OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0 | ||
| 598 | #define OMAP4430_CM_L4SEC_AES1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a0) | ||
| 599 | #define OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8 | ||
| 600 | #define OMAP4430_CM_L4SEC_AES2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a8) | ||
| 601 | #define OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0 | ||
| 602 | #define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b0) | ||
| 603 | #define OMAP4_CM_L4SEC_PKAEIP29_CLKCTRL_OFFSET 0x01b8 | ||
| 604 | #define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b8) | ||
| 605 | #define OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0 | ||
| 606 | #define OMAP4430_CM_L4SEC_RNG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c0) | ||
| 607 | #define OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8 | ||
| 608 | #define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c8) | ||
| 609 | #define OMAP4_CM_L4SEC_CRYPTODMA_CLKCTRL_OFFSET 0x01d8 | ||
| 610 | #define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01d8) | ||
| 611 | 27 | ||
| 612 | /* CM2.CEFUSE_CM2 register offsets */ | 28 | extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg); |
| 613 | #define OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000 | ||
| 614 | #define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0000) | ||
| 615 | #define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 | ||
| 616 | #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0020) | ||
| 617 | 29 | ||
| 618 | /* CM2.RESTORE_CM2 register offsets */ | 30 | # endif |
| 619 | #define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET 0x0000 | ||
| 620 | #define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0000) | ||
| 621 | #define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET 0x0004 | ||
| 622 | #define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0004) | ||
| 623 | #define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET 0x0008 | ||
| 624 | #define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0008) | ||
| 625 | #define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET 0x000c | ||
| 626 | #define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x000c) | ||
| 627 | #define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET 0x0010 | ||
| 628 | #define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0010) | ||
| 629 | #define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET 0x0014 | ||
| 630 | #define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0014) | ||
| 631 | #define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET 0x0018 | ||
| 632 | #define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0018) | ||
| 633 | #define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET 0x001c | ||
| 634 | #define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x001c) | ||
| 635 | #define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET 0x0020 | ||
| 636 | #define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0020) | ||
| 637 | #define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET 0x0024 | ||
| 638 | #define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0024) | ||
| 639 | #define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET 0x0028 | ||
| 640 | #define OMAP4430_CM_D2D_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0028) | ||
| 641 | #define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET 0x002c | ||
| 642 | #define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x002c) | ||
| 643 | #define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET 0x0030 | ||
| 644 | #define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0030) | ||
| 645 | #define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET 0x0034 | ||
| 646 | #define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0034) | ||
| 647 | #define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET 0x0038 | ||
| 648 | #define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0038) | ||
| 649 | #define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET 0x003c | ||
| 650 | #define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x003c) | ||
| 651 | #define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET 0x0040 | ||
| 652 | #define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0040) | ||
| 653 | #define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET 0x0044 | ||
| 654 | #define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0044) | ||
| 655 | #define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET 0x0048 | ||
| 656 | #define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0048) | ||
| 657 | #define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET 0x004c | ||
| 658 | #define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x004c) | ||
| 659 | #define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET 0x0050 | ||
| 660 | #define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0050) | ||
| 661 | #define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET 0x0054 | ||
| 662 | #define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0054) | ||
| 663 | #define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET 0x0058 | ||
| 664 | #define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0058) | ||
| 665 | #define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET 0x005c | ||
| 666 | #define OMAP4430_CM_SDMA_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x005c) | ||
| 667 | #endif | 31 | #endif |
diff --git a/arch/arm/mach-omap2/cm4xxx.c b/arch/arm/mach-omap2/cm4xxx.c deleted file mode 100644 index f8a660a1a4a6..000000000000 --- a/arch/arm/mach-omap2/cm4xxx.c +++ /dev/null | |||
| @@ -1,62 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * OMAP4 CM module functions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Nokia Corporation | ||
| 5 | * Paul Walmsley | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/module.h> | ||
| 14 | #include <linux/types.h> | ||
| 15 | #include <linux/delay.h> | ||
| 16 | #include <linux/spinlock.h> | ||
| 17 | #include <linux/list.h> | ||
| 18 | #include <linux/errno.h> | ||
| 19 | #include <linux/err.h> | ||
| 20 | #include <linux/io.h> | ||
| 21 | |||
| 22 | #include <asm/atomic.h> | ||
| 23 | |||
| 24 | #include <plat/common.h> | ||
| 25 | |||
| 26 | #include "cm.h" | ||
| 27 | #include "cm-regbits-44xx.h" | ||
| 28 | |||
| 29 | /** | ||
| 30 | * omap4_cm_wait_module_ready - wait for a module to be in 'func' state | ||
| 31 | * @clkctrl_reg: CLKCTRL module address | ||
| 32 | * | ||
| 33 | * Wait for the module IDLEST to be functional. If the idle state is in any | ||
| 34 | * the non functional state (trans, idle or disabled), module and thus the | ||
| 35 | * sysconfig cannot be accessed and will probably lead to an "imprecise | ||
| 36 | * external abort" | ||
| 37 | * | ||
| 38 | * Module idle state: | ||
| 39 | * 0x0 func: Module is fully functional, including OCP | ||
| 40 | * 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep | ||
| 41 | * abortion | ||
| 42 | * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if | ||
| 43 | * using separate functional clock | ||
| 44 | * 0x3 disabled: Module is disabled and cannot be accessed | ||
| 45 | * | ||
| 46 | */ | ||
| 47 | int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg) | ||
| 48 | { | ||
| 49 | int i = 0; | ||
| 50 | |||
| 51 | if (!clkctrl_reg) | ||
| 52 | return 0; | ||
| 53 | |||
| 54 | omap_test_timeout(( | ||
| 55 | ((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) == 0) || | ||
| 56 | (((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) >> | ||
| 57 | OMAP4430_IDLEST_SHIFT) == 0x2)), | ||
| 58 | MAX_MODULE_READY_TIME, i); | ||
| 59 | |||
| 60 | return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; | ||
| 61 | } | ||
| 62 | |||
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c new file mode 100644 index 000000000000..c04bbbea17a5 --- /dev/null +++ b/arch/arm/mach-omap2/cminst44xx.c | |||
| @@ -0,0 +1,214 @@ | |||
| 1 | /* | ||
| 2 | * OMAP4 CM instance functions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Nokia Corporation | ||
| 5 | * Paul Walmsley | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | * | ||
| 11 | * This is needed since CM instances can be in the PRM, PRCM_MPU, CM1, | ||
| 12 | * or CM2 hardware modules. For example, the EMU_CM CM instance is in | ||
| 13 | * the PRM hardware module. What a mess... | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include <linux/kernel.h> | ||
| 17 | #include <linux/types.h> | ||
| 18 | #include <linux/errno.h> | ||
| 19 | #include <linux/err.h> | ||
| 20 | #include <linux/io.h> | ||
| 21 | |||
| 22 | #include <plat/common.h> | ||
| 23 | |||
| 24 | #include "cm.h" | ||
| 25 | #include "cm1_44xx.h" | ||
| 26 | #include "cm2_44xx.h" | ||
| 27 | #include "cm44xx.h" | ||
| 28 | #include "cminst44xx.h" | ||
| 29 | #include "cm-regbits-34xx.h" | ||
| 30 | #include "cm-regbits-44xx.h" | ||
| 31 | #include "prcm44xx.h" | ||
| 32 | #include "prm44xx.h" | ||
| 33 | #include "prcm_mpu44xx.h" | ||
| 34 | |||
| 35 | static u32 _cm_bases[OMAP4_MAX_PRCM_PARTITIONS] = { | ||
| 36 | [OMAP4430_INVALID_PRCM_PARTITION] = 0, | ||
| 37 | [OMAP4430_PRM_PARTITION] = OMAP4430_PRM_BASE, | ||
| 38 | [OMAP4430_CM1_PARTITION] = OMAP4430_CM1_BASE, | ||
| 39 | [OMAP4430_CM2_PARTITION] = OMAP4430_CM2_BASE, | ||
| 40 | [OMAP4430_SCRM_PARTITION] = 0, | ||
| 41 | [OMAP4430_PRCM_MPU_PARTITION] = OMAP4430_PRCM_MPU_BASE, | ||
| 42 | }; | ||
| 43 | |||
| 44 | /* Read a register in a CM instance */ | ||
| 45 | u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx) | ||
| 46 | { | ||
| 47 | BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || | ||
| 48 | part == OMAP4430_INVALID_PRCM_PARTITION || | ||
| 49 | !_cm_bases[part]); | ||
| 50 | return __raw_readl(OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx)); | ||
| 51 | } | ||
| 52 | |||
| 53 | /* Write into a register in a CM instance */ | ||
| 54 | void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx) | ||
| 55 | { | ||
| 56 | BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || | ||
| 57 | part == OMAP4430_INVALID_PRCM_PARTITION || | ||
| 58 | !_cm_bases[part]); | ||
| 59 | __raw_writel(val, OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx)); | ||
| 60 | } | ||
| 61 | |||
| 62 | /* Read-modify-write a register in CM1. Caller must lock */ | ||
| 63 | u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst, | ||
| 64 | s16 idx) | ||
| 65 | { | ||
| 66 | u32 v; | ||
| 67 | |||
| 68 | v = omap4_cminst_read_inst_reg(part, inst, idx); | ||
| 69 | v &= ~mask; | ||
| 70 | v |= bits; | ||
| 71 | omap4_cminst_write_inst_reg(v, part, inst, idx); | ||
| 72 | |||
| 73 | return v; | ||
| 74 | } | ||
| 75 | |||
| 76 | /* | ||
| 77 | * | ||
| 78 | */ | ||
| 79 | |||
| 80 | /** | ||
| 81 | * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield | ||
| 82 | * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted) | ||
| 83 | * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in | ||
| 84 | * @inst: CM instance register offset (*_INST macro) | ||
| 85 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
| 86 | * | ||
| 87 | * @c must be the unshifted value for CLKTRCTRL - i.e., this function | ||
| 88 | * will handle the shift itself. | ||
| 89 | */ | ||
| 90 | static void _clktrctrl_write(u8 c, u8 part, s16 inst, u16 cdoffs) | ||
| 91 | { | ||
| 92 | u32 v; | ||
| 93 | |||
| 94 | v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); | ||
| 95 | v &= ~OMAP4430_CLKTRCTRL_MASK; | ||
| 96 | v |= c << OMAP4430_CLKTRCTRL_SHIFT; | ||
| 97 | omap4_cminst_write_inst_reg(v, part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); | ||
| 98 | } | ||
| 99 | |||
| 100 | /** | ||
| 101 | * omap4_cminst_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode? | ||
| 102 | * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in | ||
| 103 | * @inst: CM instance register offset (*_INST macro) | ||
| 104 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
| 105 | * | ||
| 106 | * Returns true if the clockdomain referred to by (@part, @inst, @cdoffs) | ||
| 107 | * is in hardware-supervised idle mode, or 0 otherwise. | ||
| 108 | */ | ||
| 109 | bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs) | ||
| 110 | { | ||
| 111 | u32 v; | ||
| 112 | |||
| 113 | v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL); | ||
| 114 | v &= OMAP4430_CLKTRCTRL_MASK; | ||
| 115 | v >>= OMAP4430_CLKTRCTRL_SHIFT; | ||
| 116 | |||
| 117 | return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false; | ||
| 118 | } | ||
| 119 | |||
| 120 | /** | ||
| 121 | * omap4_cminst_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode | ||
| 122 | * @part: PRCM partition ID that the clockdomain registers exist in | ||
| 123 | * @inst: CM instance register offset (*_INST macro) | ||
| 124 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
| 125 | * | ||
| 126 | * Put a clockdomain referred to by (@part, @inst, @cdoffs) into | ||
| 127 | * hardware-supervised idle mode. No return value. | ||
| 128 | */ | ||
| 129 | void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs) | ||
| 130 | { | ||
| 131 | _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs); | ||
| 132 | } | ||
| 133 | |||
| 134 | /** | ||
| 135 | * omap4_cminst_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode | ||
| 136 | * @part: PRCM partition ID that the clockdomain registers exist in | ||
| 137 | * @inst: CM instance register offset (*_INST macro) | ||
| 138 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
| 139 | * | ||
| 140 | * Put a clockdomain referred to by (@part, @inst, @cdoffs) into | ||
| 141 | * software-supervised idle mode, i.e., controlled manually by the | ||
| 142 | * Linux OMAP clockdomain code. No return value. | ||
| 143 | */ | ||
| 144 | void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs) | ||
| 145 | { | ||
| 146 | _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs); | ||
| 147 | } | ||
| 148 | |||
| 149 | /** | ||
| 150 | * omap4_cminst_clkdm_force_sleep - try to put a clockdomain into idle | ||
| 151 | * @part: PRCM partition ID that the clockdomain registers exist in | ||
| 152 | * @inst: CM instance register offset (*_INST macro) | ||
| 153 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
| 154 | * | ||
| 155 | * Put a clockdomain referred to by (@part, @inst, @cdoffs) into idle | ||
| 156 | * No return value. | ||
| 157 | */ | ||
| 158 | void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs) | ||
| 159 | { | ||
| 160 | _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs); | ||
| 161 | } | ||
| 162 | |||
| 163 | /** | ||
| 164 | * omap4_cminst_clkdm_force_sleep - try to take a clockdomain out of idle | ||
| 165 | * @part: PRCM partition ID that the clockdomain registers exist in | ||
| 166 | * @inst: CM instance register offset (*_INST macro) | ||
| 167 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
| 168 | * | ||
| 169 | * Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle, | ||
| 170 | * waking it up. No return value. | ||
| 171 | */ | ||
| 172 | void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs) | ||
| 173 | { | ||
| 174 | _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs); | ||
| 175 | } | ||
| 176 | |||
| 177 | /* | ||
| 178 | * | ||
| 179 | */ | ||
| 180 | |||
| 181 | /** | ||
| 182 | * omap4_cm_wait_module_ready - wait for a module to be in 'func' state | ||
| 183 | * @clkctrl_reg: CLKCTRL module address | ||
| 184 | * | ||
| 185 | * Wait for the module IDLEST to be functional. If the idle state is in any | ||
| 186 | * the non functional state (trans, idle or disabled), module and thus the | ||
| 187 | * sysconfig cannot be accessed and will probably lead to an "imprecise | ||
| 188 | * external abort" | ||
| 189 | * | ||
| 190 | * Module idle state: | ||
| 191 | * 0x0 func: Module is fully functional, including OCP | ||
| 192 | * 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep | ||
| 193 | * abortion | ||
| 194 | * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if | ||
| 195 | * using separate functional clock | ||
| 196 | * 0x3 disabled: Module is disabled and cannot be accessed | ||
| 197 | * | ||
| 198 | */ | ||
| 199 | int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg) | ||
| 200 | { | ||
| 201 | int i = 0; | ||
| 202 | |||
| 203 | if (!clkctrl_reg) | ||
| 204 | return 0; | ||
| 205 | |||
| 206 | omap_test_timeout(( | ||
| 207 | ((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) == 0) || | ||
| 208 | (((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) >> | ||
| 209 | OMAP4430_IDLEST_SHIFT) == 0x2)), | ||
| 210 | MAX_MODULE_READY_TIME, i); | ||
| 211 | |||
| 212 | return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; | ||
| 213 | } | ||
| 214 | |||
diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h new file mode 100644 index 000000000000..a6abd0a8cb82 --- /dev/null +++ b/arch/arm/mach-omap2/cminst44xx.h | |||
| @@ -0,0 +1,31 @@ | |||
| 1 | /* | ||
| 2 | * OMAP4 Clock Management (CM) function prototypes | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Nokia Corporation | ||
| 5 | * Paul Walmsley | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #ifndef __ARCH_ASM_MACH_OMAP2_CMINST44XX_H | ||
| 12 | #define __ARCH_ASM_MACH_OMAP2_CMINST44XX_H | ||
| 13 | |||
| 14 | extern bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs); | ||
| 15 | extern void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs); | ||
| 16 | extern void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs); | ||
| 17 | extern void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs); | ||
| 18 | extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs); | ||
| 19 | |||
| 20 | /* | ||
| 21 | * In an ideal world, we would not export these low-level functions, | ||
| 22 | * but this will probably take some time to fix properly | ||
| 23 | */ | ||
| 24 | extern u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx); | ||
| 25 | extern void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx); | ||
| 26 | extern u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, | ||
| 27 | s16 inst, s16 idx); | ||
| 28 | |||
| 29 | extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg); | ||
| 30 | |||
| 31 | #endif | ||
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 1fa3294b6048..695279419020 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c | |||
| @@ -20,12 +20,16 @@ | |||
| 20 | 20 | ||
| 21 | #include "cm-regbits-34xx.h" | 21 | #include "cm-regbits-34xx.h" |
| 22 | #include "prm-regbits-34xx.h" | 22 | #include "prm-regbits-34xx.h" |
| 23 | #include "cm.h" | 23 | #include "prm2xxx_3xxx.h" |
| 24 | #include "prm.h" | 24 | #include "cm2xxx_3xxx.h" |
| 25 | #include "sdrc.h" | 25 | #include "sdrc.h" |
| 26 | #include "pm.h" | 26 | #include "pm.h" |
| 27 | #include "control.h" | 27 | #include "control.h" |
| 28 | 28 | ||
| 29 | /* Used by omap3_ctrl_save_padconf() */ | ||
| 30 | #define START_PADCONF_SAVE 0x2 | ||
| 31 | #define PADCONF_SAVE_DONE 0x1 | ||
| 32 | |||
| 29 | static void __iomem *omap2_ctrl_base; | 33 | static void __iomem *omap2_ctrl_base; |
| 30 | static void __iomem *omap4_ctrl_pad_base; | 34 | static void __iomem *omap4_ctrl_pad_base; |
| 31 | 35 | ||
| @@ -134,6 +138,7 @@ struct omap3_control_regs { | |||
| 134 | u32 sramldo4; | 138 | u32 sramldo4; |
| 135 | u32 sramldo5; | 139 | u32 sramldo5; |
| 136 | u32 csi; | 140 | u32 csi; |
| 141 | u32 padconf_sys_nirq; | ||
| 137 | }; | 142 | }; |
| 138 | 143 | ||
| 139 | static struct omap3_control_regs control_context; | 144 | static struct omap3_control_regs control_context; |
| @@ -209,6 +214,37 @@ void omap4_ctrl_pad_writel(u32 val, u16 offset) | |||
| 209 | __raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset)); | 214 | __raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset)); |
| 210 | } | 215 | } |
| 211 | 216 | ||
| 217 | #ifdef CONFIG_ARCH_OMAP3 | ||
| 218 | |||
| 219 | /** | ||
| 220 | * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot | ||
| 221 | * @bootmode: 8-bit value to pass to some boot code | ||
| 222 | * | ||
| 223 | * Set the bootmode in the scratchpad RAM. This is used after the | ||
| 224 | * system restarts. Not sure what actually uses this - it may be the | ||
| 225 | * bootloader, rather than the boot ROM - contrary to the preserved | ||
| 226 | * comment below. No return value. | ||
| 227 | */ | ||
| 228 | void omap3_ctrl_write_boot_mode(u8 bootmode) | ||
| 229 | { | ||
| 230 | u32 l; | ||
| 231 | |||
| 232 | l = ('B' << 24) | ('M' << 16) | bootmode; | ||
| 233 | |||
| 234 | /* | ||
| 235 | * Reserve the first word in scratchpad for communicating | ||
| 236 | * with the boot ROM. A pointer to a data structure | ||
| 237 | * describing the boot process can be stored there, | ||
| 238 | * cf. OMAP34xx TRM, Initialization / Software Booting | ||
| 239 | * Configuration. | ||
| 240 | * | ||
| 241 | * XXX This should use some omap_ctrl_writel()-type function | ||
| 242 | */ | ||
| 243 | __raw_writel(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4)); | ||
| 244 | } | ||
| 245 | |||
| 246 | #endif | ||
| 247 | |||
| 212 | #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) | 248 | #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) |
| 213 | /* | 249 | /* |
| 214 | * Clears the scratchpad contents in case of cold boot- | 250 | * Clears the scratchpad contents in case of cold boot- |
| @@ -220,13 +256,13 @@ void omap3_clear_scratchpad_contents(void) | |||
| 220 | void __iomem *v_addr; | 256 | void __iomem *v_addr; |
| 221 | u32 offset = 0; | 257 | u32 offset = 0; |
| 222 | v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); | 258 | v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); |
| 223 | if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & | 259 | if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & |
| 224 | OMAP3430_GLOBAL_COLD_RST_MASK) { | 260 | OMAP3430_GLOBAL_COLD_RST_MASK) { |
| 225 | for ( ; offset <= max_offset; offset += 0x4) | 261 | for ( ; offset <= max_offset; offset += 0x4) |
| 226 | __raw_writel(0x0, (v_addr + offset)); | 262 | __raw_writel(0x0, (v_addr + offset)); |
| 227 | prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK, | 263 | omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK, |
| 228 | OMAP3430_GR_MOD, | 264 | OMAP3430_GR_MOD, |
| 229 | OMAP3_PRM_RSTST_OFFSET); | 265 | OMAP3_PRM_RSTST_OFFSET); |
| 230 | } | 266 | } |
| 231 | } | 267 | } |
| 232 | 268 | ||
| @@ -239,9 +275,19 @@ void omap3_save_scratchpad_contents(void) | |||
| 239 | struct omap3_scratchpad_prcm_block prcm_block_contents; | 275 | struct omap3_scratchpad_prcm_block prcm_block_contents; |
| 240 | struct omap3_scratchpad_sdrc_block sdrc_block_contents; | 276 | struct omap3_scratchpad_sdrc_block sdrc_block_contents; |
| 241 | 277 | ||
| 242 | /* Populate the Scratchpad contents */ | 278 | /* |
| 279 | * Populate the Scratchpad contents | ||
| 280 | * | ||
| 281 | * The "get_*restore_pointer" functions are used to provide a | ||
| 282 | * physical restore address where the ROM code jumps while waking | ||
| 283 | * up from MPU OFF/OSWR state. | ||
| 284 | * The restore pointer is stored into the scratchpad. | ||
| 285 | */ | ||
| 243 | scratchpad_contents.boot_config_ptr = 0x0; | 286 | scratchpad_contents.boot_config_ptr = 0x0; |
| 244 | if (omap_rev() != OMAP3430_REV_ES3_0 && | 287 | if (cpu_is_omap3630()) |
| 288 | scratchpad_contents.public_restore_ptr = | ||
| 289 | virt_to_phys(get_omap3630_restore_pointer()); | ||
| 290 | else if (omap_rev() != OMAP3430_REV_ES3_0 && | ||
| 245 | omap_rev() != OMAP3430_REV_ES3_1) | 291 | omap_rev() != OMAP3430_REV_ES3_1) |
| 246 | scratchpad_contents.public_restore_ptr = | 292 | scratchpad_contents.public_restore_ptr = |
| 247 | virt_to_phys(get_restore_pointer()); | 293 | virt_to_phys(get_restore_pointer()); |
| @@ -258,32 +304,34 @@ void omap3_save_scratchpad_contents(void) | |||
| 258 | scratchpad_contents.sdrc_block_offset = 0x64; | 304 | scratchpad_contents.sdrc_block_offset = 0x64; |
| 259 | 305 | ||
| 260 | /* Populate the PRCM block contents */ | 306 | /* Populate the PRCM block contents */ |
| 261 | prcm_block_contents.prm_clksrc_ctrl = prm_read_mod_reg(OMAP3430_GR_MOD, | 307 | prcm_block_contents.prm_clksrc_ctrl = |
| 262 | OMAP3_PRM_CLKSRC_CTRL_OFFSET); | 308 | omap2_prm_read_mod_reg(OMAP3430_GR_MOD, |
| 263 | prcm_block_contents.prm_clksel = prm_read_mod_reg(OMAP3430_CCR_MOD, | 309 | OMAP3_PRM_CLKSRC_CTRL_OFFSET); |
| 264 | OMAP3_PRM_CLKSEL_OFFSET); | 310 | prcm_block_contents.prm_clksel = |
| 311 | omap2_prm_read_mod_reg(OMAP3430_CCR_MOD, | ||
| 312 | OMAP3_PRM_CLKSEL_OFFSET); | ||
| 265 | prcm_block_contents.cm_clksel_core = | 313 | prcm_block_contents.cm_clksel_core = |
| 266 | cm_read_mod_reg(CORE_MOD, CM_CLKSEL); | 314 | omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL); |
| 267 | prcm_block_contents.cm_clksel_wkup = | 315 | prcm_block_contents.cm_clksel_wkup = |
| 268 | cm_read_mod_reg(WKUP_MOD, CM_CLKSEL); | 316 | omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL); |
| 269 | prcm_block_contents.cm_clken_pll = | 317 | prcm_block_contents.cm_clken_pll = |
| 270 | cm_read_mod_reg(PLL_MOD, CM_CLKEN); | 318 | omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); |
| 271 | prcm_block_contents.cm_autoidle_pll = | 319 | prcm_block_contents.cm_autoidle_pll = |
| 272 | cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL); | 320 | omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL); |
| 273 | prcm_block_contents.cm_clksel1_pll = | 321 | prcm_block_contents.cm_clksel1_pll = |
| 274 | cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL); | 322 | omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL); |
| 275 | prcm_block_contents.cm_clksel2_pll = | 323 | prcm_block_contents.cm_clksel2_pll = |
| 276 | cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL); | 324 | omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL); |
| 277 | prcm_block_contents.cm_clksel3_pll = | 325 | prcm_block_contents.cm_clksel3_pll = |
| 278 | cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3); | 326 | omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3); |
| 279 | prcm_block_contents.cm_clken_pll_mpu = | 327 | prcm_block_contents.cm_clken_pll_mpu = |
| 280 | cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL); | 328 | omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL); |
| 281 | prcm_block_contents.cm_autoidle_pll_mpu = | 329 | prcm_block_contents.cm_autoidle_pll_mpu = |
| 282 | cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL); | 330 | omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL); |
| 283 | prcm_block_contents.cm_clksel1_pll_mpu = | 331 | prcm_block_contents.cm_clksel1_pll_mpu = |
| 284 | cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL); | 332 | omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL); |
| 285 | prcm_block_contents.cm_clksel2_pll_mpu = | 333 | prcm_block_contents.cm_clksel2_pll_mpu = |
| 286 | cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL); | 334 | omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL); |
| 287 | prcm_block_contents.prcm_block_size = 0x0; | 335 | prcm_block_contents.prcm_block_size = 0x0; |
| 288 | 336 | ||
| 289 | /* Populate the SDRC block contents */ | 337 | /* Populate the SDRC block contents */ |
| @@ -416,6 +464,8 @@ void omap3_control_save_context(void) | |||
| 416 | control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4); | 464 | control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4); |
| 417 | control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5); | 465 | control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5); |
| 418 | control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI); | 466 | control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI); |
| 467 | control_context.padconf_sys_nirq = | ||
| 468 | omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ); | ||
| 419 | return; | 469 | return; |
| 420 | } | 470 | } |
| 421 | 471 | ||
| @@ -472,6 +522,43 @@ void omap3_control_restore_context(void) | |||
| 472 | omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4); | 522 | omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4); |
| 473 | omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5); | 523 | omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5); |
| 474 | omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI); | 524 | omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI); |
| 525 | omap_ctrl_writel(control_context.padconf_sys_nirq, | ||
| 526 | OMAP343X_CONTROL_PADCONF_SYSNIRQ); | ||
| 475 | return; | 527 | return; |
| 476 | } | 528 | } |
| 529 | |||
| 530 | void omap3630_ctrl_disable_rta(void) | ||
| 531 | { | ||
| 532 | if (!cpu_is_omap3630()) | ||
| 533 | return; | ||
| 534 | omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL); | ||
| 535 | } | ||
| 536 | |||
| 537 | /** | ||
| 538 | * omap3_ctrl_save_padconf - save padconf registers to scratchpad RAM | ||
| 539 | * | ||
| 540 | * Tell the SCM to start saving the padconf registers, then wait for | ||
| 541 | * the process to complete. Returns 0 unconditionally, although it | ||
| 542 | * should also eventually be able to return -ETIMEDOUT, if the save | ||
| 543 | * does not complete. | ||
| 544 | * | ||
| 545 | * XXX This function is missing a timeout. What should it be? | ||
| 546 | */ | ||
| 547 | int omap3_ctrl_save_padconf(void) | ||
| 548 | { | ||
| 549 | u32 cpo; | ||
| 550 | |||
| 551 | /* Save the padconf registers */ | ||
| 552 | cpo = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF); | ||
| 553 | cpo |= START_PADCONF_SAVE; | ||
| 554 | omap_ctrl_writel(cpo, OMAP343X_CONTROL_PADCONF_OFF); | ||
| 555 | |||
| 556 | /* wait for the save to complete */ | ||
| 557 | while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) | ||
| 558 | & PADCONF_SAVE_DONE)) | ||
| 559 | udelay(1); | ||
| 560 | |||
| 561 | return 0; | ||
| 562 | } | ||
| 563 | |||
| 477 | #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ | 564 | #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ |
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index b6c6b7c450b3..f0629ae04102 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h | |||
| @@ -148,6 +148,15 @@ | |||
| 148 | #define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4) | 148 | #define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4) |
| 149 | #define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8) | 149 | #define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8) |
| 150 | #define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) | 150 | #define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) |
| 151 | #define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110) | ||
| 152 | #define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114) | ||
| 153 | #define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118) | ||
| 154 | #define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x011c) | ||
| 155 | #define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120) | ||
| 156 | #define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0124) | ||
| 157 | #define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128) | ||
| 158 | #define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c) | ||
| 159 | #define OMAP343X_CONTROL_FUSE_SR (OMAP2_CONTROL_GENERAL + 0x0130) | ||
| 151 | #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) | 160 | #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) |
| 152 | #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) | 161 | #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) |
| 153 | #define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \ | 162 | #define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \ |
| @@ -164,6 +173,26 @@ | |||
| 164 | #define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0) | 173 | #define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0) |
| 165 | #define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4) | 174 | #define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4) |
| 166 | 175 | ||
| 176 | /* OMAP3630 only CONTROL_GENERAL register offsets */ | ||
| 177 | #define OMAP3630_CONTROL_FUSE_OPP1G_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110) | ||
| 178 | #define OMAP3630_CONTROL_FUSE_OPP50_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114) | ||
| 179 | #define OMAP3630_CONTROL_FUSE_OPP100_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118) | ||
| 180 | #define OMAP3630_CONTROL_FUSE_OPP120_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120) | ||
| 181 | #define OMAP3630_CONTROL_FUSE_OPP50_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128) | ||
| 182 | #define OMAP3630_CONTROL_FUSE_OPP100_VDD2 (OMAP2_CONTROL_GENERAL + 0x012C) | ||
| 183 | |||
| 184 | /* OMAP44xx control efuse offsets */ | ||
| 185 | #define OMAP44XX_CONTROL_FUSE_IVA_OPP50 0x22C | ||
| 186 | #define OMAP44XX_CONTROL_FUSE_IVA_OPP100 0x22F | ||
| 187 | #define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO 0x232 | ||
| 188 | #define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO 0x235 | ||
| 189 | #define OMAP44XX_CONTROL_FUSE_MPU_OPP50 0x240 | ||
| 190 | #define OMAP44XX_CONTROL_FUSE_MPU_OPP100 0x243 | ||
| 191 | #define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO 0x246 | ||
| 192 | #define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO 0x249 | ||
| 193 | #define OMAP44XX_CONTROL_FUSE_CORE_OPP50 0x254 | ||
| 194 | #define OMAP44XX_CONTROL_FUSE_CORE_OPP100 0x257 | ||
| 195 | |||
| 167 | /* AM35XX only CONTROL_GENERAL register offsets */ | 196 | /* AM35XX only CONTROL_GENERAL register offsets */ |
| 168 | #define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038) | 197 | #define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038) |
| 169 | #define AM35XX_CONTROL_DEVCONF2 (OMAP2_CONTROL_GENERAL + 0x0310) | 198 | #define AM35XX_CONTROL_DEVCONF2 (OMAP2_CONTROL_GENERAL + 0x0310) |
| @@ -204,6 +233,10 @@ | |||
| 204 | #define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014) | 233 | #define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014) |
| 205 | #define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018) | 234 | #define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018) |
| 206 | 235 | ||
| 236 | /* 36xx-only RTA - Retention till Accesss control registers and bits */ | ||
| 237 | #define OMAP36XX_CONTROL_MEM_RTA_CTRL 0x40C | ||
| 238 | #define OMAP36XX_RTA_DISABLE 0x0 | ||
| 239 | |||
| 207 | /* 34xx D2D idle-related pins, handled by PM core */ | 240 | /* 34xx D2D idle-related pins, handled by PM core */ |
| 208 | #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 | 241 | #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 |
| 209 | #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 | 242 | #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 |
| @@ -270,6 +303,8 @@ | |||
| 270 | #define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860) | 303 | #define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860) |
| 271 | #define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910) | 304 | #define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910) |
| 272 | #define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C | 305 | #define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C |
| 306 | #define OMAP343X_SCRATCHPAD_REGADDR(reg) OMAP2_L4_IO_ADDRESS(\ | ||
| 307 | OMAP343X_SCRATCHPAD + reg) | ||
| 273 | 308 | ||
| 274 | /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */ | 309 | /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */ |
| 275 | #define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0 | 310 | #define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0 |
| @@ -309,7 +344,7 @@ | |||
| 309 | #define FEAT_SGX_NONE 2 | 344 | #define FEAT_SGX_NONE 2 |
| 310 | 345 | ||
| 311 | #define OMAP3_IVA_SHIFT 12 | 346 | #define OMAP3_IVA_SHIFT 12 |
| 312 | #define OMAP3_IVA_MASK (1 << OMAP3_SGX_SHIFT) | 347 | #define OMAP3_IVA_MASK (1 << OMAP3_IVA_SHIFT) |
| 313 | #define FEAT_IVA 0 | 348 | #define FEAT_IVA 0 |
| 314 | #define FEAT_IVA_NONE 1 | 349 | #define FEAT_IVA_NONE 1 |
| 315 | 350 | ||
| @@ -347,10 +382,13 @@ extern void omap3_save_scratchpad_contents(void); | |||
| 347 | extern void omap3_clear_scratchpad_contents(void); | 382 | extern void omap3_clear_scratchpad_contents(void); |
| 348 | extern u32 *get_restore_pointer(void); | 383 | extern u32 *get_restore_pointer(void); |
| 349 | extern u32 *get_es3_restore_pointer(void); | 384 | extern u32 *get_es3_restore_pointer(void); |
| 385 | extern u32 *get_omap3630_restore_pointer(void); | ||
| 350 | extern u32 omap3_arm_context[128]; | 386 | extern u32 omap3_arm_context[128]; |
| 351 | extern void omap3_control_save_context(void); | 387 | extern void omap3_control_save_context(void); |
| 352 | extern void omap3_control_restore_context(void); | 388 | extern void omap3_control_restore_context(void); |
| 353 | 389 | extern void omap3_ctrl_write_boot_mode(u8 bootmode); | |
| 390 | extern void omap3630_ctrl_disable_rta(void); | ||
| 391 | extern int omap3_ctrl_save_padconf(void); | ||
| 354 | #else | 392 | #else |
| 355 | #define omap_ctrl_base_get() 0 | 393 | #define omap_ctrl_base_get() 0 |
| 356 | #define omap_ctrl_readb(x) 0 | 394 | #define omap_ctrl_readb(x) 0 |
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index f9be4e3078bc..5bdfc443b77d 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c | |||
| @@ -27,8 +27,8 @@ | |||
| 27 | 27 | ||
| 28 | #include <plat/prcm.h> | 28 | #include <plat/prcm.h> |
| 29 | #include <plat/irqs.h> | 29 | #include <plat/irqs.h> |
| 30 | #include <plat/powerdomain.h> | 30 | #include "powerdomain.h" |
| 31 | #include <plat/clockdomain.h> | 31 | #include "clockdomain.h" |
| 32 | #include <plat/serial.h> | 32 | #include <plat/serial.h> |
| 33 | 33 | ||
| 34 | #include "pm.h" | 34 | #include "pm.h" |
| @@ -295,25 +295,26 @@ select_state: | |||
| 295 | DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); | 295 | DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); |
| 296 | 296 | ||
| 297 | /** | 297 | /** |
| 298 | * omap3_cpuidle_update_states - Update the cpuidle states. | 298 | * omap3_cpuidle_update_states() - Update the cpuidle states |
| 299 | * @mpu_deepest_state: Enable states upto and including this for mpu domain | ||
| 300 | * @core_deepest_state: Enable states upto and including this for core domain | ||
| 299 | * | 301 | * |
| 300 | * Currently, this function toggles the validity of idle states based upon | 302 | * This goes through the list of states available and enables and disables the |
| 301 | * the flag 'enable_off_mode'. When the flag is set all states are valid. | 303 | * validity of C states based on deepest state that can be achieved for the |
| 302 | * Else, states leading to OFF state set to be invalid. | 304 | * variable domain |
| 303 | */ | 305 | */ |
| 304 | void omap3_cpuidle_update_states(void) | 306 | void omap3_cpuidle_update_states(u32 mpu_deepest_state, u32 core_deepest_state) |
| 305 | { | 307 | { |
| 306 | int i; | 308 | int i; |
| 307 | 309 | ||
| 308 | for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) { | 310 | for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) { |
| 309 | struct omap3_processor_cx *cx = &omap3_power_states[i]; | 311 | struct omap3_processor_cx *cx = &omap3_power_states[i]; |
| 310 | 312 | ||
| 311 | if (enable_off_mode) { | 313 | if ((cx->mpu_state >= mpu_deepest_state) && |
| 314 | (cx->core_state >= core_deepest_state)) { | ||
| 312 | cx->valid = 1; | 315 | cx->valid = 1; |
| 313 | } else { | 316 | } else { |
| 314 | if ((cx->mpu_state == PWRDM_POWER_OFF) || | 317 | cx->valid = 0; |
| 315 | (cx->core_state == PWRDM_POWER_OFF)) | ||
| 316 | cx->valid = 0; | ||
| 317 | } | 318 | } |
| 318 | } | 319 | } |
| 319 | } | 320 | } |
| @@ -454,6 +455,18 @@ void omap_init_power_states(void) | |||
| 454 | omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF; | 455 | omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF; |
| 455 | omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID | | 456 | omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID | |
| 456 | CPUIDLE_FLAG_CHECK_BM; | 457 | CPUIDLE_FLAG_CHECK_BM; |
| 458 | |||
| 459 | /* | ||
| 460 | * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot | ||
| 461 | * enable OFF mode in a stable form for previous revisions. | ||
| 462 | * we disable C7 state as a result. | ||
| 463 | */ | ||
| 464 | if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) { | ||
| 465 | omap3_power_states[OMAP3_STATE_C7].valid = 0; | ||
| 466 | cpuidle_params_table[OMAP3_STATE_C7].valid = 0; | ||
| 467 | WARN_ONCE(1, "%s: core off state C7 disabled due to i583\n", | ||
| 468 | __func__); | ||
| 469 | } | ||
| 457 | } | 470 | } |
| 458 | 471 | ||
| 459 | struct cpuidle_driver omap3_idle_driver = { | 472 | struct cpuidle_driver omap3_idle_driver = { |
| @@ -506,7 +519,10 @@ int __init omap3_idle_init(void) | |||
| 506 | return -EINVAL; | 519 | return -EINVAL; |
| 507 | dev->state_count = count; | 520 | dev->state_count = count; |
| 508 | 521 | ||
| 509 | omap3_cpuidle_update_states(); | 522 | if (enable_off_mode) |
| 523 | omap3_cpuidle_update_states(PWRDM_POWER_OFF, PWRDM_POWER_OFF); | ||
| 524 | else | ||
| 525 | omap3_cpuidle_update_states(PWRDM_POWER_RET, PWRDM_POWER_RET); | ||
| 510 | 526 | ||
| 511 | if (cpuidle_register_device(dev)) { | 527 | if (cpuidle_register_device(dev)) { |
| 512 | printk(KERN_ERR "%s: CPUidle register device failed\n", | 528 | printk(KERN_ERR "%s: CPUidle register device failed\n", |
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 5a0c148e23bc..381f4eb92352 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c | |||
| @@ -638,6 +638,7 @@ static struct platform_device dummy_pdev = { | |||
| 638 | static void __init omap_hsmmc_reset(void) | 638 | static void __init omap_hsmmc_reset(void) |
| 639 | { | 639 | { |
| 640 | u32 i, nr_controllers; | 640 | u32 i, nr_controllers; |
| 641 | struct clk *iclk, *fclk; | ||
| 641 | 642 | ||
| 642 | if (cpu_is_omap242x()) | 643 | if (cpu_is_omap242x()) |
| 643 | return; | 644 | return; |
| @@ -647,7 +648,6 @@ static void __init omap_hsmmc_reset(void) | |||
| 647 | 648 | ||
| 648 | for (i = 0; i < nr_controllers; i++) { | 649 | for (i = 0; i < nr_controllers; i++) { |
| 649 | u32 v, base = 0; | 650 | u32 v, base = 0; |
| 650 | struct clk *iclk, *fclk; | ||
| 651 | struct device *dev = &dummy_pdev.dev; | 651 | struct device *dev = &dummy_pdev.dev; |
| 652 | 652 | ||
| 653 | switch (i) { | 653 | switch (i) { |
| @@ -678,19 +678,16 @@ static void __init omap_hsmmc_reset(void) | |||
| 678 | dummy_pdev.id = i; | 678 | dummy_pdev.id = i; |
| 679 | dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i); | 679 | dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i); |
| 680 | iclk = clk_get(dev, "ick"); | 680 | iclk = clk_get(dev, "ick"); |
| 681 | if (iclk && clk_enable(iclk)) | 681 | if (IS_ERR(iclk)) |
| 682 | iclk = NULL; | 682 | goto err1; |
| 683 | if (clk_enable(iclk)) | ||
| 684 | goto err2; | ||
| 683 | 685 | ||
| 684 | fclk = clk_get(dev, "fck"); | 686 | fclk = clk_get(dev, "fck"); |
| 685 | if (fclk && clk_enable(fclk)) | 687 | if (IS_ERR(fclk)) |
| 686 | fclk = NULL; | 688 | goto err3; |
| 687 | 689 | if (clk_enable(fclk)) | |
| 688 | if (!iclk || !fclk) { | 690 | goto err4; |
| 689 | printk(KERN_WARNING | ||
| 690 | "%s: Unable to enable clocks for MMC%d, " | ||
| 691 | "cannot reset.\n", __func__, i); | ||
| 692 | break; | ||
| 693 | } | ||
| 694 | 691 | ||
| 695 | omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG); | 692 | omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG); |
| 696 | v = omap_readl(base + MMCHS_SYSSTATUS); | 693 | v = omap_readl(base + MMCHS_SYSSTATUS); |
| @@ -698,15 +695,22 @@ static void __init omap_hsmmc_reset(void) | |||
| 698 | MMCHS_SYSSTATUS_RESETDONE)) | 695 | MMCHS_SYSSTATUS_RESETDONE)) |
| 699 | cpu_relax(); | 696 | cpu_relax(); |
| 700 | 697 | ||
| 701 | if (fclk) { | 698 | clk_disable(fclk); |
| 702 | clk_disable(fclk); | 699 | clk_put(fclk); |
| 703 | clk_put(fclk); | 700 | clk_disable(iclk); |
| 704 | } | 701 | clk_put(iclk); |
| 705 | if (iclk) { | ||
| 706 | clk_disable(iclk); | ||
| 707 | clk_put(iclk); | ||
| 708 | } | ||
| 709 | } | 702 | } |
| 703 | return; | ||
| 704 | |||
| 705 | err4: | ||
| 706 | clk_put(fclk); | ||
| 707 | err3: | ||
| 708 | clk_disable(iclk); | ||
| 709 | err2: | ||
| 710 | clk_put(iclk); | ||
| 711 | err1: | ||
| 712 | printk(KERN_WARNING "%s: Unable to enable clocks for MMC%d, " | ||
| 713 | "cannot reset.\n", __func__, i); | ||
| 710 | } | 714 | } |
| 711 | #else | 715 | #else |
| 712 | static inline void omap_hsmmc_reset(void) {} | 716 | static inline void omap_hsmmc_reset(void) {} |
| @@ -951,72 +955,12 @@ static inline void omap_init_vout(void) {} | |||
| 951 | 955 | ||
| 952 | /*-------------------------------------------------------------------------*/ | 956 | /*-------------------------------------------------------------------------*/ |
| 953 | 957 | ||
| 954 | /* | ||
| 955 | * Inorder to avoid any assumptions from bootloader regarding WDT | ||
| 956 | * settings, WDT module is reset during init. This enables the watchdog | ||
| 957 | * timer. Hence it is required to disable the watchdog after the WDT reset | ||
| 958 | * during init. Otherwise the system would reboot as per the default | ||
| 959 | * watchdog timer registers settings. | ||
| 960 | */ | ||
| 961 | #define OMAP_WDT_WPS (0x34) | ||
| 962 | #define OMAP_WDT_SPR (0x48) | ||
| 963 | |||
| 964 | static int omap2_disable_wdt(struct omap_hwmod *oh, void *unused) | ||
| 965 | { | ||
| 966 | void __iomem *base; | ||
| 967 | int ret; | ||
| 968 | |||
| 969 | if (!oh) { | ||
| 970 | pr_err("%s: Could not look up wdtimer_hwmod\n", __func__); | ||
| 971 | return -EINVAL; | ||
| 972 | } | ||
| 973 | |||
| 974 | base = omap_hwmod_get_mpu_rt_va(oh); | ||
| 975 | if (!base) { | ||
| 976 | pr_err("%s: Could not get the base address for %s\n", | ||
| 977 | oh->name, __func__); | ||
| 978 | return -EINVAL; | ||
| 979 | } | ||
| 980 | |||
| 981 | /* Enable the clocks before accessing the WDT registers */ | ||
| 982 | ret = omap_hwmod_enable(oh); | ||
| 983 | if (ret) { | ||
| 984 | pr_err("%s: Could not enable clocks for %s\n", | ||
| 985 | oh->name, __func__); | ||
| 986 | return ret; | ||
| 987 | } | ||
| 988 | |||
| 989 | /* sequence required to disable watchdog */ | ||
| 990 | __raw_writel(0xAAAA, base + OMAP_WDT_SPR); | ||
| 991 | while (__raw_readl(base + OMAP_WDT_WPS) & 0x10) | ||
| 992 | cpu_relax(); | ||
| 993 | |||
| 994 | __raw_writel(0x5555, base + OMAP_WDT_SPR); | ||
| 995 | while (__raw_readl(base + OMAP_WDT_WPS) & 0x10) | ||
| 996 | cpu_relax(); | ||
| 997 | |||
| 998 | ret = omap_hwmod_idle(oh); | ||
| 999 | if (ret) | ||
| 1000 | pr_err("%s: Could not disable clocks for %s\n", | ||
| 1001 | oh->name, __func__); | ||
| 1002 | |||
| 1003 | return ret; | ||
| 1004 | } | ||
| 1005 | |||
| 1006 | static void __init omap_disable_wdt(void) | ||
| 1007 | { | ||
| 1008 | if (cpu_class_is_omap2()) | ||
| 1009 | omap_hwmod_for_each_by_class("wd_timer", | ||
| 1010 | omap2_disable_wdt, NULL); | ||
| 1011 | return; | ||
| 1012 | } | ||
| 1013 | |||
| 1014 | static int __init omap2_init_devices(void) | 958 | static int __init omap2_init_devices(void) |
| 1015 | { | 959 | { |
| 1016 | /* please keep these calls, and their implementations above, | 960 | /* |
| 961 | * please keep these calls, and their implementations above, | ||
| 1017 | * in alphabetical order so they're easier to sort through. | 962 | * in alphabetical order so they're easier to sort through. |
| 1018 | */ | 963 | */ |
| 1019 | omap_disable_wdt(); | ||
| 1020 | omap_hsmmc_reset(); | 964 | omap_hsmmc_reset(); |
| 1021 | omap_init_audio(); | 965 | omap_init_audio(); |
| 1022 | omap_init_camera(); | 966 | omap_init_camera(); |
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c new file mode 100644 index 000000000000..d2f15f5cfd36 --- /dev/null +++ b/arch/arm/mach-omap2/dma.c | |||
| @@ -0,0 +1,297 @@ | |||
| 1 | /* | ||
| 2 | * OMAP2+ DMA driver | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 - 2008 Nokia Corporation | ||
| 5 | * Author: Juha Yrjölä <juha.yrjola@nokia.com> | ||
| 6 | * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com> | ||
| 7 | * Graphics DMA and LCD DMA graphics tranformations | ||
| 8 | * by Imre Deak <imre.deak@nokia.com> | ||
| 9 | * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc. | ||
| 10 | * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc. | ||
| 11 | * | ||
| 12 | * Copyright (C) 2009 Texas Instruments | ||
| 13 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | ||
| 14 | * | ||
| 15 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 16 | * Converted DMA library into platform driver | ||
| 17 | * - G, Manjunath Kondaiah <manjugk@ti.com> | ||
| 18 | * | ||
| 19 | * This program is free software; you can redistribute it and/or modify | ||
| 20 | * it under the terms of the GNU General Public License version 2 as | ||
| 21 | * published by the Free Software Foundation. | ||
| 22 | */ | ||
| 23 | |||
| 24 | #include <linux/err.h> | ||
| 25 | #include <linux/io.h> | ||
| 26 | #include <linux/slab.h> | ||
| 27 | #include <linux/module.h> | ||
| 28 | #include <linux/init.h> | ||
| 29 | #include <linux/device.h> | ||
| 30 | |||
| 31 | #include <plat/omap_hwmod.h> | ||
| 32 | #include <plat/omap_device.h> | ||
| 33 | #include <plat/dma.h> | ||
| 34 | |||
| 35 | #define OMAP2_DMA_STRIDE 0x60 | ||
| 36 | |||
| 37 | static u32 errata; | ||
| 38 | static u8 dma_stride; | ||
| 39 | |||
| 40 | static struct omap_dma_dev_attr *d; | ||
| 41 | |||
| 42 | static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end; | ||
| 43 | |||
| 44 | static u16 reg_map[] = { | ||
| 45 | [REVISION] = 0x00, | ||
| 46 | [GCR] = 0x78, | ||
| 47 | [IRQSTATUS_L0] = 0x08, | ||
| 48 | [IRQSTATUS_L1] = 0x0c, | ||
| 49 | [IRQSTATUS_L2] = 0x10, | ||
| 50 | [IRQSTATUS_L3] = 0x14, | ||
| 51 | [IRQENABLE_L0] = 0x18, | ||
| 52 | [IRQENABLE_L1] = 0x1c, | ||
| 53 | [IRQENABLE_L2] = 0x20, | ||
| 54 | [IRQENABLE_L3] = 0x24, | ||
| 55 | [SYSSTATUS] = 0x28, | ||
| 56 | [OCP_SYSCONFIG] = 0x2c, | ||
| 57 | [CAPS_0] = 0x64, | ||
| 58 | [CAPS_2] = 0x6c, | ||
| 59 | [CAPS_3] = 0x70, | ||
| 60 | [CAPS_4] = 0x74, | ||
| 61 | |||
| 62 | /* Common register offsets */ | ||
| 63 | [CCR] = 0x80, | ||
| 64 | [CLNK_CTRL] = 0x84, | ||
| 65 | [CICR] = 0x88, | ||
| 66 | [CSR] = 0x8c, | ||
| 67 | [CSDP] = 0x90, | ||
| 68 | [CEN] = 0x94, | ||
| 69 | [CFN] = 0x98, | ||
| 70 | [CSEI] = 0xa4, | ||
| 71 | [CSFI] = 0xa8, | ||
| 72 | [CDEI] = 0xac, | ||
| 73 | [CDFI] = 0xb0, | ||
| 74 | [CSAC] = 0xb4, | ||
| 75 | [CDAC] = 0xb8, | ||
| 76 | |||
| 77 | /* Channel specific register offsets */ | ||
| 78 | [CSSA] = 0x9c, | ||
| 79 | [CDSA] = 0xa0, | ||
| 80 | [CCEN] = 0xbc, | ||
| 81 | [CCFN] = 0xc0, | ||
| 82 | [COLOR] = 0xc4, | ||
| 83 | |||
| 84 | /* OMAP4 specific registers */ | ||
| 85 | [CDP] = 0xd0, | ||
| 86 | [CNDP] = 0xd4, | ||
| 87 | [CCDN] = 0xd8, | ||
| 88 | }; | ||
| 89 | |||
| 90 | static struct omap_device_pm_latency omap2_dma_latency[] = { | ||
| 91 | { | ||
| 92 | .deactivate_func = omap_device_idle_hwmods, | ||
| 93 | .activate_func = omap_device_enable_hwmods, | ||
| 94 | .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, | ||
| 95 | }, | ||
| 96 | }; | ||
| 97 | |||
| 98 | static void __iomem *dma_base; | ||
| 99 | static inline void dma_write(u32 val, int reg, int lch) | ||
| 100 | { | ||
| 101 | u8 stride; | ||
| 102 | u32 offset; | ||
| 103 | |||
| 104 | stride = (reg >= dma_common_ch_start) ? dma_stride : 0; | ||
| 105 | offset = reg_map[reg] + (stride * lch); | ||
| 106 | __raw_writel(val, dma_base + offset); | ||
| 107 | } | ||
| 108 | |||
| 109 | static inline u32 dma_read(int reg, int lch) | ||
| 110 | { | ||
| 111 | u8 stride; | ||
| 112 | u32 offset, val; | ||
| 113 | |||
| 114 | stride = (reg >= dma_common_ch_start) ? dma_stride : 0; | ||
| 115 | offset = reg_map[reg] + (stride * lch); | ||
| 116 | val = __raw_readl(dma_base + offset); | ||
| 117 | return val; | ||
| 118 | } | ||
| 119 | |||
| 120 | static inline void omap2_disable_irq_lch(int lch) | ||
| 121 | { | ||
| 122 | u32 val; | ||
| 123 | |||
| 124 | val = dma_read(IRQENABLE_L0, lch); | ||
| 125 | val &= ~(1 << lch); | ||
| 126 | dma_write(val, IRQENABLE_L0, lch); | ||
| 127 | } | ||
| 128 | |||
| 129 | static void omap2_clear_dma(int lch) | ||
| 130 | { | ||
| 131 | int i = dma_common_ch_start; | ||
| 132 | |||
| 133 | for (; i <= dma_common_ch_end; i += 1) | ||
| 134 | dma_write(0, i, lch); | ||
| 135 | } | ||
| 136 | |||
| 137 | static void omap2_show_dma_caps(void) | ||
| 138 | { | ||
| 139 | u8 revision = dma_read(REVISION, 0) & 0xff; | ||
| 140 | printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n", | ||
| 141 | revision >> 4, revision & 0xf); | ||
| 142 | return; | ||
| 143 | } | ||
| 144 | |||
| 145 | static u32 configure_dma_errata(void) | ||
| 146 | { | ||
| 147 | |||
| 148 | /* | ||
| 149 | * Errata applicable for OMAP2430ES1.0 and all omap2420 | ||
| 150 | * | ||
| 151 | * I. | ||
| 152 | * Erratum ID: Not Available | ||
| 153 | * Inter Frame DMA buffering issue DMA will wrongly | ||
| 154 | * buffer elements if packing and bursting is enabled. This might | ||
| 155 | * result in data gets stalled in FIFO at the end of the block. | ||
| 156 | * Workaround: DMA channels must have BUFFERING_DISABLED bit set to | ||
| 157 | * guarantee no data will stay in the DMA FIFO in case inter frame | ||
| 158 | * buffering occurs | ||
| 159 | * | ||
| 160 | * II. | ||
| 161 | * Erratum ID: Not Available | ||
| 162 | * DMA may hang when several channels are used in parallel | ||
| 163 | * In the following configuration, DMA channel hanging can occur: | ||
| 164 | * a. Channel i, hardware synchronized, is enabled | ||
| 165 | * b. Another channel (Channel x), software synchronized, is enabled. | ||
| 166 | * c. Channel i is disabled before end of transfer | ||
| 167 | * d. Channel i is reenabled. | ||
| 168 | * e. Steps 1 to 4 are repeated a certain number of times. | ||
| 169 | * f. A third channel (Channel y), software synchronized, is enabled. | ||
| 170 | * Channel x and Channel y may hang immediately after step 'f'. | ||
| 171 | * Workaround: | ||
| 172 | * For any channel used - make sure NextLCH_ID is set to the value j. | ||
| 173 | */ | ||
| 174 | if (cpu_is_omap2420() || (cpu_is_omap2430() && | ||
| 175 | (omap_type() == OMAP2430_REV_ES1_0))) { | ||
| 176 | |||
| 177 | SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING); | ||
| 178 | SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS); | ||
| 179 | } | ||
| 180 | |||
| 181 | /* | ||
| 182 | * Erratum ID: i378: OMAP2+: sDMA Channel is not disabled | ||
| 183 | * after a transaction error. | ||
| 184 | * Workaround: SW should explicitely disable the channel. | ||
| 185 | */ | ||
| 186 | if (cpu_class_is_omap2()) | ||
| 187 | SET_DMA_ERRATA(DMA_ERRATA_i378); | ||
| 188 | |||
| 189 | /* | ||
| 190 | * Erratum ID: i541: sDMA FIFO draining does not finish | ||
| 191 | * If sDMA channel is disabled on the fly, sDMA enters standby even | ||
| 192 | * through FIFO Drain is still in progress | ||
| 193 | * Workaround: Put sDMA in NoStandby more before a logical channel is | ||
| 194 | * disabled, then put it back to SmartStandby right after the channel | ||
| 195 | * finishes FIFO draining. | ||
| 196 | */ | ||
| 197 | if (cpu_is_omap34xx()) | ||
| 198 | SET_DMA_ERRATA(DMA_ERRATA_i541); | ||
| 199 | |||
| 200 | /* | ||
| 201 | * Erratum ID: i88 : Special programming model needed to disable DMA | ||
| 202 | * before end of block. | ||
| 203 | * Workaround: software must ensure that the DMA is configured in No | ||
| 204 | * Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01") | ||
| 205 | */ | ||
| 206 | if (omap_type() == OMAP3430_REV_ES1_0) | ||
| 207 | SET_DMA_ERRATA(DMA_ERRATA_i88); | ||
| 208 | |||
| 209 | /* | ||
| 210 | * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is | ||
| 211 | * read before the DMA controller finished disabling the channel. | ||
| 212 | */ | ||
| 213 | SET_DMA_ERRATA(DMA_ERRATA_3_3); | ||
| 214 | |||
| 215 | /* | ||
| 216 | * Erratum ID: Not Available | ||
| 217 | * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared | ||
| 218 | * after secure sram context save and restore. | ||
| 219 | * Work around: Hence we need to manually clear those IRQs to avoid | ||
| 220 | * spurious interrupts. This affects only secure devices. | ||
| 221 | */ | ||
| 222 | if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) | ||
| 223 | SET_DMA_ERRATA(DMA_ROMCODE_BUG); | ||
| 224 | |||
| 225 | return errata; | ||
| 226 | } | ||
| 227 | |||
| 228 | /* One time initializations */ | ||
| 229 | static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused) | ||
| 230 | { | ||
| 231 | struct omap_device *od; | ||
| 232 | struct omap_system_dma_plat_info *p; | ||
| 233 | struct resource *mem; | ||
| 234 | char *name = "omap_dma_system"; | ||
| 235 | |||
| 236 | dma_stride = OMAP2_DMA_STRIDE; | ||
| 237 | dma_common_ch_start = CSDP; | ||
| 238 | if (cpu_is_omap3630() || cpu_is_omap4430()) | ||
| 239 | dma_common_ch_end = CCDN; | ||
| 240 | else | ||
| 241 | dma_common_ch_end = CCFN; | ||
| 242 | |||
| 243 | p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL); | ||
| 244 | if (!p) { | ||
| 245 | pr_err("%s: Unable to allocate pdata for %s:%s\n", | ||
| 246 | __func__, name, oh->name); | ||
| 247 | return -ENOMEM; | ||
| 248 | } | ||
| 249 | |||
| 250 | p->dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr; | ||
| 251 | p->disable_irq_lch = omap2_disable_irq_lch; | ||
| 252 | p->show_dma_caps = omap2_show_dma_caps; | ||
| 253 | p->clear_dma = omap2_clear_dma; | ||
| 254 | p->dma_write = dma_write; | ||
| 255 | p->dma_read = dma_read; | ||
| 256 | |||
| 257 | p->clear_lch_regs = NULL; | ||
| 258 | |||
| 259 | p->errata = configure_dma_errata(); | ||
| 260 | |||
| 261 | od = omap_device_build(name, 0, oh, p, sizeof(*p), | ||
| 262 | omap2_dma_latency, ARRAY_SIZE(omap2_dma_latency), 0); | ||
| 263 | kfree(p); | ||
| 264 | if (IS_ERR(od)) { | ||
| 265 | pr_err("%s: Cant build omap_device for %s:%s.\n", | ||
| 266 | __func__, name, oh->name); | ||
| 267 | return IS_ERR(od); | ||
| 268 | } | ||
| 269 | |||
| 270 | mem = platform_get_resource(&od->pdev, IORESOURCE_MEM, 0); | ||
| 271 | if (!mem) { | ||
| 272 | dev_err(&od->pdev.dev, "%s: no mem resource\n", __func__); | ||
| 273 | return -EINVAL; | ||
| 274 | } | ||
| 275 | dma_base = ioremap(mem->start, resource_size(mem)); | ||
| 276 | if (!dma_base) { | ||
| 277 | dev_err(&od->pdev.dev, "%s: ioremap fail\n", __func__); | ||
| 278 | return -ENOMEM; | ||
| 279 | } | ||
| 280 | |||
| 281 | d = oh->dev_attr; | ||
| 282 | d->chan = kzalloc(sizeof(struct omap_dma_lch) * | ||
| 283 | (d->lch_count), GFP_KERNEL); | ||
| 284 | |||
| 285 | if (!d->chan) { | ||
| 286 | dev_err(&od->pdev.dev, "%s: kzalloc fail\n", __func__); | ||
| 287 | return -ENOMEM; | ||
| 288 | } | ||
| 289 | return 0; | ||
| 290 | } | ||
| 291 | |||
| 292 | static int __init omap2_system_dma_init(void) | ||
| 293 | { | ||
| 294 | return omap_hwmod_for_each_by_class("dma", | ||
| 295 | omap2_system_dma_init_dev, NULL); | ||
| 296 | } | ||
| 297 | arch_initcall(omap2_system_dma_init); | ||
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index ed8d330522f1..f77022be783d 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c | |||
| @@ -26,15 +26,13 @@ | |||
| 26 | #include <linux/clk.h> | 26 | #include <linux/clk.h> |
| 27 | #include <linux/io.h> | 27 | #include <linux/io.h> |
| 28 | #include <linux/bitops.h> | 28 | #include <linux/bitops.h> |
| 29 | #include <linux/clkdev.h> | ||
| 29 | 30 | ||
| 30 | #include <plat/cpu.h> | 31 | #include <plat/cpu.h> |
| 31 | #include <plat/clock.h> | 32 | #include <plat/clock.h> |
| 32 | #include <asm/clkdev.h> | ||
| 33 | 33 | ||
| 34 | #include "clock.h" | 34 | #include "clock.h" |
| 35 | #include "prm.h" | 35 | #include "cm2xxx_3xxx.h" |
| 36 | #include "prm-regbits-34xx.h" | ||
| 37 | #include "cm.h" | ||
| 38 | #include "cm-regbits-34xx.h" | 36 | #include "cm-regbits-34xx.h" |
| 39 | 37 | ||
| 40 | /* CM_AUTOIDLE_PLL*.AUTO_* bit values */ | 38 | /* CM_AUTOIDLE_PLL*.AUTO_* bit values */ |
| @@ -225,10 +223,9 @@ static int _omap3_noncore_dpll_stop(struct clk *clk) | |||
| 225 | } | 223 | } |
| 226 | 224 | ||
| 227 | /** | 225 | /** |
| 228 | * lookup_dco_sddiv - Set j-type DPLL4 compensation variables | 226 | * _lookup_dco - Lookup DCO used by j-type DPLL |
| 229 | * @clk: pointer to a DPLL struct clk | 227 | * @clk: pointer to a DPLL struct clk |
| 230 | * @dco: digital control oscillator selector | 228 | * @dco: digital control oscillator selector |
| 231 | * @sd_div: target sigma-delta divider | ||
| 232 | * @m: DPLL multiplier to set | 229 | * @m: DPLL multiplier to set |
| 233 | * @n: DPLL divider to set | 230 | * @n: DPLL divider to set |
| 234 | * | 231 | * |
| @@ -237,11 +234,9 @@ static int _omap3_noncore_dpll_stop(struct clk *clk) | |||
| 237 | * XXX This code is not needed for 3430/AM35xx; can it be optimized | 234 | * XXX This code is not needed for 3430/AM35xx; can it be optimized |
| 238 | * out in non-multi-OMAP builds for those chips? | 235 | * out in non-multi-OMAP builds for those chips? |
| 239 | */ | 236 | */ |
| 240 | static void lookup_dco_sddiv(struct clk *clk, u8 *dco, u8 *sd_div, u16 m, | 237 | static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n) |
| 241 | u8 n) | ||
| 242 | { | 238 | { |
| 243 | unsigned long fint, clkinp, sd; /* watch out for overflow */ | 239 | unsigned long fint, clkinp; /* watch out for overflow */ |
| 244 | int mod1, mod2; | ||
| 245 | 240 | ||
| 246 | clkinp = clk->parent->rate; | 241 | clkinp = clk->parent->rate; |
| 247 | fint = (clkinp / n) * m; | 242 | fint = (clkinp / n) * m; |
| @@ -250,6 +245,27 @@ static void lookup_dco_sddiv(struct clk *clk, u8 *dco, u8 *sd_div, u16 m, | |||
| 250 | *dco = 2; | 245 | *dco = 2; |
| 251 | else | 246 | else |
| 252 | *dco = 4; | 247 | *dco = 4; |
| 248 | } | ||
| 249 | |||
| 250 | /** | ||
| 251 | * _lookup_sddiv - Calculate sigma delta divider for j-type DPLL | ||
| 252 | * @clk: pointer to a DPLL struct clk | ||
| 253 | * @sd_div: target sigma-delta divider | ||
| 254 | * @m: DPLL multiplier to set | ||
| 255 | * @n: DPLL divider to set | ||
| 256 | * | ||
| 257 | * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)" | ||
| 258 | * | ||
| 259 | * XXX This code is not needed for 3430/AM35xx; can it be optimized | ||
| 260 | * out in non-multi-OMAP builds for those chips? | ||
| 261 | */ | ||
| 262 | static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n) | ||
| 263 | { | ||
| 264 | unsigned long clkinp, sd; /* watch out for overflow */ | ||
| 265 | int mod1, mod2; | ||
| 266 | |||
| 267 | clkinp = clk->parent->rate; | ||
| 268 | |||
| 253 | /* | 269 | /* |
| 254 | * target sigma-delta to near 250MHz | 270 | * target sigma-delta to near 250MHz |
| 255 | * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)] | 271 | * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)] |
| @@ -278,6 +294,7 @@ static void lookup_dco_sddiv(struct clk *clk, u8 *dco, u8 *sd_div, u16 m, | |||
| 278 | static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) | 294 | static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) |
| 279 | { | 295 | { |
| 280 | struct dpll_data *dd = clk->dpll_data; | 296 | struct dpll_data *dd = clk->dpll_data; |
| 297 | u8 dco, sd_div; | ||
| 281 | u32 v; | 298 | u32 v; |
| 282 | 299 | ||
| 283 | /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ | 300 | /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ |
| @@ -300,18 +317,16 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) | |||
| 300 | v |= m << __ffs(dd->mult_mask); | 317 | v |= m << __ffs(dd->mult_mask); |
| 301 | v |= (n - 1) << __ffs(dd->div1_mask); | 318 | v |= (n - 1) << __ffs(dd->div1_mask); |
| 302 | 319 | ||
| 303 | /* | 320 | /* Configure dco and sd_div for dplls that have these fields */ |
| 304 | * XXX This code is not needed for 3430/AM35XX; can it be optimized | 321 | if (dd->dco_mask) { |
| 305 | * out in non-multi-OMAP builds for those chips? | 322 | _lookup_dco(clk, &dco, m, n); |
| 306 | */ | 323 | v &= ~(dd->dco_mask); |
| 307 | if ((dd->flags & DPLL_J_TYPE) && !(dd->flags & DPLL_NO_DCO_SEL)) { | 324 | v |= dco << __ffs(dd->dco_mask); |
| 308 | u8 dco, sd_div; | 325 | } |
| 309 | lookup_dco_sddiv(clk, &dco, &sd_div, m, n); | 326 | if (dd->sddiv_mask) { |
| 310 | /* XXX This probably will need revision for OMAP4 */ | 327 | _lookup_sddiv(clk, &sd_div, m, n); |
| 311 | v &= ~(OMAP3630_PERIPH_DPLL_DCO_SEL_MASK | 328 | v &= ~(dd->sddiv_mask); |
| 312 | | OMAP3630_PERIPH_DPLL_SD_DIV_MASK); | 329 | v |= sd_div << __ffs(dd->sddiv_mask); |
| 313 | v |= dco << __ffs(OMAP3630_PERIPH_DPLL_DCO_SEL_MASK); | ||
| 314 | v |= sd_div << __ffs(OMAP3630_PERIPH_DPLL_SD_DIV_MASK); | ||
| 315 | } | 330 | } |
| 316 | 331 | ||
| 317 | __raw_writel(v, dd->mult_div1_reg); | 332 | __raw_writel(v, dd->mult_div1_reg); |
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c index 6feeeae6c21b..911cd2e68d46 100644 --- a/arch/arm/mach-omap2/dsp.c +++ b/arch/arm/mach-omap2/dsp.c | |||
| @@ -11,9 +11,16 @@ | |||
| 11 | * published by the Free Software Foundation. | 11 | * published by the Free Software Foundation. |
| 12 | */ | 12 | */ |
| 13 | 13 | ||
| 14 | /* | ||
| 15 | * XXX The function pointers to the PRM/CM functions are incorrect and | ||
| 16 | * should be removed. No device driver should be changing PRM/CM bits | ||
| 17 | * directly; that's a layering violation -- those bits are the responsibility | ||
| 18 | * of the OMAP PM core code. | ||
| 19 | */ | ||
| 20 | |||
| 14 | #include <linux/platform_device.h> | 21 | #include <linux/platform_device.h> |
| 15 | #include "prm.h" | 22 | #include "cm2xxx_3xxx.h" |
| 16 | #include "cm.h" | 23 | #include "prm2xxx_3xxx.h" |
| 17 | #ifdef CONFIG_BRIDGE_DVFS | 24 | #ifdef CONFIG_BRIDGE_DVFS |
| 18 | #include <plat/omap-pm.h> | 25 | #include <plat/omap-pm.h> |
| 19 | #endif | 26 | #endif |
| @@ -31,12 +38,12 @@ static struct omap_dsp_platform_data omap_dsp_pdata __initdata = { | |||
| 31 | .cpu_set_freq = omap_pm_cpu_set_freq, | 38 | .cpu_set_freq = omap_pm_cpu_set_freq, |
| 32 | .cpu_get_freq = omap_pm_cpu_get_freq, | 39 | .cpu_get_freq = omap_pm_cpu_get_freq, |
| 33 | #endif | 40 | #endif |
| 34 | .dsp_prm_read = prm_read_mod_reg, | 41 | .dsp_prm_read = omap2_prm_read_mod_reg, |
| 35 | .dsp_prm_write = prm_write_mod_reg, | 42 | .dsp_prm_write = omap2_prm_write_mod_reg, |
| 36 | .dsp_prm_rmw_bits = prm_rmw_mod_reg_bits, | 43 | .dsp_prm_rmw_bits = omap2_prm_rmw_mod_reg_bits, |
| 37 | .dsp_cm_read = cm_read_mod_reg, | 44 | .dsp_cm_read = omap2_cm_read_mod_reg, |
| 38 | .dsp_cm_write = cm_write_mod_reg, | 45 | .dsp_cm_write = omap2_cm_write_mod_reg, |
| 39 | .dsp_cm_rmw_bits = cm_rmw_mod_reg_bits, | 46 | .dsp_cm_rmw_bits = omap2_cm_rmw_mod_reg_bits, |
| 40 | }; | 47 | }; |
| 41 | 48 | ||
| 42 | static int __init omap_dsp_init(void) | 49 | static int __init omap_dsp_init(void) |
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c new file mode 100644 index 000000000000..413de18c1d2b --- /dev/null +++ b/arch/arm/mach-omap2/gpio.c | |||
| @@ -0,0 +1,104 @@ | |||
| 1 | /* | ||
| 2 | * OMAP2+ specific gpio initialization | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 5 | * | ||
| 6 | * Author: | ||
| 7 | * Charulatha V <charu@ti.com> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or | ||
| 10 | * modify it under the terms of the GNU General Public License as | ||
| 11 | * published by the Free Software Foundation version 2. | ||
| 12 | * | ||
| 13 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
| 14 | * kind, whether express or implied; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/gpio.h> | ||
| 20 | #include <linux/err.h> | ||
| 21 | #include <linux/slab.h> | ||
| 22 | #include <linux/interrupt.h> | ||
| 23 | |||
| 24 | #include <plat/omap_hwmod.h> | ||
| 25 | #include <plat/omap_device.h> | ||
| 26 | |||
| 27 | static struct omap_device_pm_latency omap_gpio_latency[] = { | ||
| 28 | [0] = { | ||
| 29 | .deactivate_func = omap_device_idle_hwmods, | ||
| 30 | .activate_func = omap_device_enable_hwmods, | ||
| 31 | .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, | ||
| 32 | }, | ||
| 33 | }; | ||
| 34 | |||
| 35 | static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) | ||
| 36 | { | ||
| 37 | struct omap_device *od; | ||
| 38 | struct omap_gpio_platform_data *pdata; | ||
| 39 | struct omap_gpio_dev_attr *dev_attr; | ||
| 40 | char *name = "omap_gpio"; | ||
| 41 | int id; | ||
| 42 | |||
| 43 | /* | ||
| 44 | * extract the device id from name field available in the | ||
| 45 | * hwmod database and use the same for constructing ids for | ||
| 46 | * gpio devices. | ||
| 47 | * CAUTION: Make sure the name in the hwmod database does | ||
| 48 | * not change. If changed, make corresponding change here | ||
| 49 | * or make use of static variable mechanism to handle this. | ||
| 50 | */ | ||
| 51 | sscanf(oh->name, "gpio%d", &id); | ||
| 52 | |||
| 53 | pdata = kzalloc(sizeof(struct omap_gpio_platform_data), GFP_KERNEL); | ||
| 54 | if (!pdata) { | ||
| 55 | pr_err("gpio%d: Memory allocation failed\n", id); | ||
| 56 | return -ENOMEM; | ||
| 57 | } | ||
| 58 | |||
| 59 | dev_attr = (struct omap_gpio_dev_attr *)oh->dev_attr; | ||
| 60 | pdata->bank_width = dev_attr->bank_width; | ||
| 61 | pdata->dbck_flag = dev_attr->dbck_flag; | ||
| 62 | pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1); | ||
| 63 | |||
| 64 | switch (oh->class->rev) { | ||
| 65 | case 0: | ||
| 66 | case 1: | ||
| 67 | pdata->bank_type = METHOD_GPIO_24XX; | ||
| 68 | break; | ||
| 69 | case 2: | ||
| 70 | pdata->bank_type = METHOD_GPIO_44XX; | ||
| 71 | break; | ||
| 72 | default: | ||
| 73 | WARN(1, "Invalid gpio bank_type\n"); | ||
| 74 | kfree(pdata); | ||
| 75 | return -EINVAL; | ||
| 76 | } | ||
| 77 | |||
| 78 | od = omap_device_build(name, id - 1, oh, pdata, | ||
| 79 | sizeof(*pdata), omap_gpio_latency, | ||
| 80 | ARRAY_SIZE(omap_gpio_latency), | ||
| 81 | false); | ||
| 82 | kfree(pdata); | ||
| 83 | |||
| 84 | if (IS_ERR(od)) { | ||
| 85 | WARN(1, "Cant build omap_device for %s:%s.\n", | ||
| 86 | name, oh->name); | ||
| 87 | return PTR_ERR(od); | ||
| 88 | } | ||
| 89 | |||
| 90 | gpio_bank_count++; | ||
| 91 | return 0; | ||
| 92 | } | ||
| 93 | |||
| 94 | /* | ||
| 95 | * gpio_init needs to be done before | ||
| 96 | * machine_init functions access gpio APIs. | ||
| 97 | * Hence gpio_init is a postcore_initcall. | ||
| 98 | */ | ||
| 99 | static int __init omap2_gpio_init(void) | ||
| 100 | { | ||
| 101 | return omap_hwmod_for_each_by_class("gpio", omap2_gpio_dev_init, | ||
| 102 | NULL); | ||
| 103 | } | ||
| 104 | postcore_initcall(omap2_gpio_init); | ||
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index 722209601927..2bb29c160702 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c | |||
| @@ -41,7 +41,7 @@ static int omap2_nand_gpmc_retime(void) | |||
| 41 | return 0; | 41 | return 0; |
| 42 | 42 | ||
| 43 | memset(&t, 0, sizeof(t)); | 43 | memset(&t, 0, sizeof(t)); |
| 44 | t.sync_clk = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->sync_clk); | 44 | t.sync_clk = gpmc_nand_data->gpmc_t->sync_clk; |
| 45 | t.cs_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_on); | 45 | t.cs_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_on); |
| 46 | t.adv_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->adv_on); | 46 | t.adv_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->adv_on); |
| 47 | 47 | ||
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c index 7bb69220adfa..3a7d25fb00ef 100644 --- a/arch/arm/mach-omap2/gpmc-onenand.c +++ b/arch/arm/mach-omap2/gpmc-onenand.c | |||
| @@ -173,8 +173,17 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, | |||
| 173 | } | 173 | } |
| 174 | 174 | ||
| 175 | switch (freq) { | 175 | switch (freq) { |
| 176 | case 104: | ||
| 177 | min_gpmc_clk_period = 9600; /* 104 MHz */ | ||
| 178 | t_ces = 3; | ||
| 179 | t_avds = 4; | ||
| 180 | t_avdh = 2; | ||
| 181 | t_ach = 3; | ||
| 182 | t_aavdh = 6; | ||
| 183 | t_rdyo = 9; | ||
| 184 | break; | ||
| 176 | case 83: | 185 | case 83: |
| 177 | min_gpmc_clk_period = 12; /* 83 MHz */ | 186 | min_gpmc_clk_period = 12000; /* 83 MHz */ |
| 178 | t_ces = 5; | 187 | t_ces = 5; |
| 179 | t_avds = 4; | 188 | t_avds = 4; |
| 180 | t_avdh = 2; | 189 | t_avdh = 2; |
| @@ -183,7 +192,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, | |||
| 183 | t_rdyo = 9; | 192 | t_rdyo = 9; |
| 184 | break; | 193 | break; |
| 185 | case 66: | 194 | case 66: |
| 186 | min_gpmc_clk_period = 15; /* 66 MHz */ | 195 | min_gpmc_clk_period = 15000; /* 66 MHz */ |
| 187 | t_ces = 6; | 196 | t_ces = 6; |
| 188 | t_avds = 5; | 197 | t_avds = 5; |
| 189 | t_avdh = 2; | 198 | t_avdh = 2; |
| @@ -192,7 +201,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, | |||
| 192 | t_rdyo = 11; | 201 | t_rdyo = 11; |
| 193 | break; | 202 | break; |
| 194 | default: | 203 | default: |
| 195 | min_gpmc_clk_period = 18; /* 54 MHz */ | 204 | min_gpmc_clk_period = 18500; /* 54 MHz */ |
| 196 | t_ces = 7; | 205 | t_ces = 7; |
| 197 | t_avds = 7; | 206 | t_avds = 7; |
| 198 | t_avdh = 7; | 207 | t_avdh = 7; |
| @@ -271,8 +280,8 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, | |||
| 271 | t.wr_cycle = t.rd_cycle; | 280 | t.wr_cycle = t.rd_cycle; |
| 272 | if (cpu_is_omap34xx()) { | 281 | if (cpu_is_omap34xx()) { |
| 273 | t.wr_data_mux_bus = gpmc_ticks_to_ns(fclk_offset + | 282 | t.wr_data_mux_bus = gpmc_ticks_to_ns(fclk_offset + |
| 274 | gpmc_ns_to_ticks(min_gpmc_clk_period + | 283 | gpmc_ps_to_ticks(min_gpmc_clk_period + |
| 275 | t_rdyo)); | 284 | t_rdyo * 1000)); |
| 276 | t.wr_access = t.access; | 285 | t.wr_access = t.access; |
| 277 | } | 286 | } |
| 278 | } else { | 287 | } else { |
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index f46933bc9373..1b7b3e7d02f7 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c | |||
| @@ -168,6 +168,16 @@ unsigned int gpmc_ns_to_ticks(unsigned int time_ns) | |||
| 168 | return (time_ns * 1000 + tick_ps - 1) / tick_ps; | 168 | return (time_ns * 1000 + tick_ps - 1) / tick_ps; |
| 169 | } | 169 | } |
| 170 | 170 | ||
| 171 | unsigned int gpmc_ps_to_ticks(unsigned int time_ps) | ||
| 172 | { | ||
| 173 | unsigned long tick_ps; | ||
| 174 | |||
| 175 | /* Calculate in picosecs to yield more exact results */ | ||
| 176 | tick_ps = gpmc_get_fclk_period(); | ||
| 177 | |||
| 178 | return (time_ps + tick_ps - 1) / tick_ps; | ||
| 179 | } | ||
| 180 | |||
| 171 | unsigned int gpmc_ticks_to_ns(unsigned int ticks) | 181 | unsigned int gpmc_ticks_to_ns(unsigned int ticks) |
| 172 | { | 182 | { |
| 173 | return ticks * gpmc_get_fclk_period() / 1000; | 183 | return ticks * gpmc_get_fclk_period() / 1000; |
| @@ -235,7 +245,7 @@ int gpmc_cs_calc_divider(int cs, unsigned int sync_clk) | |||
| 235 | int div; | 245 | int div; |
| 236 | u32 l; | 246 | u32 l; |
| 237 | 247 | ||
| 238 | l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1); | 248 | l = sync_clk + (gpmc_get_fclk_period() - 1); |
| 239 | div = l / gpmc_get_fclk_period(); | 249 | div = l / gpmc_get_fclk_period(); |
| 240 | if (div > 4) | 250 | if (div > 4) |
| 241 | return -1; | 251 | return -1; |
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S index 06e64e1fc28a..befa321c4c13 100644 --- a/arch/arm/mach-omap2/include/mach/entry-macro.S +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S | |||
| @@ -38,41 +38,27 @@ | |||
| 38 | */ | 38 | */ |
| 39 | 39 | ||
| 40 | #ifdef MULTI_OMAP2 | 40 | #ifdef MULTI_OMAP2 |
| 41 | |||
| 42 | /* | ||
| 43 | * We use __glue to avoid errors with multiple definitions of | ||
| 44 | * .globl omap_irq_base as it's included from entry-armv.S but not | ||
| 45 | * from entry-common.S. | ||
| 46 | */ | ||
| 47 | #ifdef __glue | ||
| 41 | .pushsection .data | 48 | .pushsection .data |
| 42 | omap_irq_base: .word 0 | 49 | .globl omap_irq_base |
| 50 | omap_irq_base: | ||
| 51 | .word 0 | ||
| 43 | .popsection | 52 | .popsection |
| 53 | #endif | ||
| 44 | 54 | ||
| 45 | /* Configure the interrupt base on the first interrupt */ | 55 | /* |
| 56 | * Configure the interrupt base on the first interrupt. | ||
| 57 | * See also omap_irq_base_init for setting omap_irq_base. | ||
| 58 | */ | ||
| 46 | .macro get_irqnr_preamble, base, tmp | 59 | .macro get_irqnr_preamble, base, tmp |
| 47 | 9: | ||
| 48 | ldr \base, =omap_irq_base @ irq base address | 60 | ldr \base, =omap_irq_base @ irq base address |
| 49 | ldr \base, [\base, #0] @ irq base value | 61 | ldr \base, [\base, #0] @ irq base value |
| 50 | cmp \base, #0 @ already configured? | ||
| 51 | bne 9997f @ nothing to do | ||
| 52 | |||
| 53 | mrc p15, 0, \tmp, c0, c0, 0 @ get processor revision | ||
| 54 | and \tmp, \tmp, #0x000f0000 @ only check architecture | ||
| 55 | cmp \tmp, #0x00070000 @ is v6? | ||
| 56 | beq 2400f @ found v6 so it's omap24xx | ||
| 57 | mrc p15, 0, \tmp, c0, c0, 0 @ get processor revision | ||
| 58 | and \tmp, \tmp, #0x000000f0 @ check cortex 8 or 9 | ||
| 59 | cmp \tmp, #0x00000080 @ cortex A-8? | ||
| 60 | beq 3400f @ found A-8 so it's omap34xx | ||
| 61 | cmp \tmp, #0x00000090 @ cortex A-9? | ||
| 62 | beq 4400f @ found A-9 so it's omap44xx | ||
| 63 | 2400: ldr \base, =OMAP2_IRQ_BASE | ||
| 64 | ldr \tmp, =omap_irq_base | ||
| 65 | str \base, [\tmp, #0] | ||
| 66 | b 9b | ||
| 67 | 3400: ldr \base, =OMAP3_IRQ_BASE | ||
| 68 | ldr \tmp, =omap_irq_base | ||
| 69 | str \base, [\tmp, #0] | ||
| 70 | b 9b | ||
| 71 | 4400: ldr \base, =OMAP4_IRQ_BASE | ||
| 72 | ldr \tmp, =omap_irq_base | ||
| 73 | str \base, [\tmp, #0] | ||
| 74 | b 9b | ||
| 75 | 9997: | ||
| 76 | .endm | 62 | .endm |
| 77 | 63 | ||
| 78 | /* Check the pending interrupts. Note that base already set */ | 64 | /* Check the pending interrupts. Note that base already set */ |
| @@ -105,6 +91,35 @@ omap_irq_base: .word 0 | |||
| 105 | 9999: | 91 | 9999: |
| 106 | .endm | 92 | .endm |
| 107 | 93 | ||
| 94 | #ifdef CONFIG_SMP | ||
| 95 | /* We assume that irqstat (the raw value of the IRQ acknowledge | ||
| 96 | * register) is preserved from the macro above. | ||
| 97 | * If there is an IPI, we immediately signal end of interrupt | ||
| 98 | * on the controller, since this requires the original irqstat | ||
| 99 | * value which we won't easily be able to recreate later. | ||
| 100 | */ | ||
| 101 | |||
| 102 | .macro test_for_ipi, irqnr, irqstat, base, tmp | ||
| 103 | bic \irqnr, \irqstat, #0x1c00 | ||
| 104 | cmp \irqnr, #16 | ||
| 105 | it cc | ||
| 106 | strcc \irqstat, [\base, #GIC_CPU_EOI] | ||
| 107 | it cs | ||
| 108 | cmpcs \irqnr, \irqnr | ||
| 109 | .endm | ||
| 110 | |||
| 111 | /* As above, this assumes that irqstat and base are preserved */ | ||
| 112 | |||
| 113 | .macro test_for_ltirq, irqnr, irqstat, base, tmp | ||
| 114 | bic \irqnr, \irqstat, #0x1c00 | ||
| 115 | mov \tmp, #0 | ||
| 116 | cmp \irqnr, #29 | ||
| 117 | itt eq | ||
| 118 | moveq \tmp, #1 | ||
| 119 | streq \irqstat, [\base, #GIC_CPU_EOI] | ||
| 120 | cmp \tmp, #0 | ||
| 121 | .endm | ||
| 122 | #endif /* CONFIG_SMP */ | ||
| 108 | 123 | ||
| 109 | #else /* MULTI_OMAP2 */ | 124 | #else /* MULTI_OMAP2 */ |
| 110 | 125 | ||
| @@ -141,74 +156,16 @@ omap_irq_base: .word 0 | |||
| 141 | 156 | ||
| 142 | 157 | ||
| 143 | #ifdef CONFIG_ARCH_OMAP4 | 158 | #ifdef CONFIG_ARCH_OMAP4 |
| 159 | #define HAVE_GET_IRQNR_PREAMBLE | ||
| 160 | #include <asm/hardware/entry-macro-gic.S> | ||
| 144 | 161 | ||
| 145 | .macro get_irqnr_preamble, base, tmp | 162 | .macro get_irqnr_preamble, base, tmp |
| 146 | ldr \base, =OMAP4_IRQ_BASE | 163 | ldr \base, =OMAP4_IRQ_BASE |
| 147 | .endm | 164 | .endm |
| 148 | 165 | ||
| 149 | /* | ||
| 150 | * The interrupt numbering scheme is defined in the | ||
| 151 | * interrupt controller spec. To wit: | ||
| 152 | * | ||
| 153 | * Interrupts 0-15 are IPI | ||
| 154 | * 16-28 are reserved | ||
| 155 | * 29-31 are local. We allow 30 to be used for the watchdog. | ||
| 156 | * 32-1020 are global | ||
| 157 | * 1021-1022 are reserved | ||
| 158 | * 1023 is "spurious" (no interrupt) | ||
| 159 | * | ||
| 160 | * For now, we ignore all local interrupts so only return an | ||
| 161 | * interrupt if it's between 30 and 1020. The test_for_ipi | ||
| 162 | * routine below will pick up on IPIs. | ||
| 163 | * A simple read from the controller will tell us the number | ||
| 164 | * of the highest priority enabled interrupt. | ||
| 165 | * We then just need to check whether it is in the | ||
| 166 | * valid range for an IRQ (30-1020 inclusive). | ||
| 167 | */ | ||
| 168 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 169 | ldr \irqstat, [\base, #GIC_CPU_INTACK] | ||
| 170 | |||
| 171 | ldr \tmp, =1021 | ||
| 172 | |||
| 173 | bic \irqnr, \irqstat, #0x1c00 | ||
| 174 | |||
| 175 | cmp \irqnr, #29 | ||
| 176 | cmpcc \irqnr, \irqnr | ||
| 177 | cmpne \irqnr, \tmp | ||
| 178 | cmpcs \irqnr, \irqnr | ||
| 179 | .endm | ||
| 180 | #endif | 166 | #endif |
| 181 | #endif /* MULTI_OMAP2 */ | ||
| 182 | |||
| 183 | #ifdef CONFIG_SMP | ||
| 184 | /* We assume that irqstat (the raw value of the IRQ acknowledge | ||
| 185 | * register) is preserved from the macro above. | ||
| 186 | * If there is an IPI, we immediately signal end of interrupt | ||
| 187 | * on the controller, since this requires the original irqstat | ||
| 188 | * value which we won't easily be able to recreate later. | ||
| 189 | */ | ||
| 190 | 167 | ||
| 191 | .macro test_for_ipi, irqnr, irqstat, base, tmp | 168 | #endif /* MULTI_OMAP2 */ |
| 192 | bic \irqnr, \irqstat, #0x1c00 | ||
| 193 | cmp \irqnr, #16 | ||
| 194 | it cc | ||
| 195 | strcc \irqstat, [\base, #GIC_CPU_EOI] | ||
| 196 | it cs | ||
| 197 | cmpcs \irqnr, \irqnr | ||
| 198 | .endm | ||
| 199 | |||
| 200 | /* As above, this assumes that irqstat and base are preserved */ | ||
| 201 | |||
| 202 | .macro test_for_ltirq, irqnr, irqstat, base, tmp | ||
| 203 | bic \irqnr, \irqstat, #0x1c00 | ||
| 204 | mov \tmp, #0 | ||
| 205 | cmp \irqnr, #29 | ||
| 206 | itt eq | ||
| 207 | moveq \tmp, #1 | ||
| 208 | streq \irqstat, [\base, #GIC_CPU_EOI] | ||
| 209 | cmp \tmp, #0 | ||
| 210 | .endm | ||
| 211 | #endif /* CONFIG_SMP */ | ||
| 212 | 169 | ||
| 213 | .macro irq_prio_table | 170 | .macro irq_prio_table |
| 214 | .endm | 171 | .endm |
diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h index 2744dfee1ff4..5b0270b28934 100644 --- a/arch/arm/mach-omap2/include/mach/omap4-common.h +++ b/arch/arm/mach-omap2/include/mach/omap4-common.h | |||
| @@ -24,7 +24,6 @@ | |||
| 24 | extern void __iomem *l2cache_base; | 24 | extern void __iomem *l2cache_base; |
| 25 | #endif | 25 | #endif |
| 26 | 26 | ||
| 27 | extern void __iomem *gic_cpu_base_addr; | ||
| 28 | extern void __iomem *gic_dist_base_addr; | 27 | extern void __iomem *gic_dist_base_addr; |
| 29 | 28 | ||
| 30 | extern void __init gic_init_irq(void); | 29 | extern void __init gic_init_irq(void); |
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index a1939b1e6f82..e66687b0b9de 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c | |||
| @@ -39,13 +39,11 @@ | |||
| 39 | #include "io.h" | 39 | #include "io.h" |
| 40 | 40 | ||
| 41 | #include <plat/omap-pm.h> | 41 | #include <plat/omap-pm.h> |
| 42 | #include <plat/powerdomain.h> | 42 | #include "powerdomain.h" |
| 43 | #include "powerdomains.h" | ||
| 44 | |||
| 45 | #include <plat/clockdomain.h> | ||
| 46 | #include "clockdomains.h" | ||
| 47 | 43 | ||
| 44 | #include "clockdomain.h" | ||
| 48 | #include <plat/omap_hwmod.h> | 45 | #include <plat/omap_hwmod.h> |
| 46 | #include <plat/multi.h> | ||
| 49 | 47 | ||
| 50 | /* | 48 | /* |
| 51 | * The machine specific code may provide the extra mapping besides the | 49 | * The machine specific code may provide the extra mapping besides the |
| @@ -311,24 +309,81 @@ static int __init _omap2_init_reprogram_sdrc(void) | |||
| 311 | return v; | 309 | return v; |
| 312 | } | 310 | } |
| 313 | 311 | ||
| 314 | void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, | 312 | static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data) |
| 315 | struct omap_sdrc_params *sdrc_cs1) | 313 | { |
| 314 | return omap_hwmod_set_postsetup_state(oh, *(u8 *)data); | ||
| 315 | } | ||
| 316 | |||
| 317 | /* | ||
| 318 | * Initialize asm_irq_base for entry-macro.S | ||
| 319 | */ | ||
| 320 | static inline void omap_irq_base_init(void) | ||
| 321 | { | ||
| 322 | extern void __iomem *omap_irq_base; | ||
| 323 | |||
| 324 | #ifdef MULTI_OMAP2 | ||
| 325 | if (cpu_is_omap24xx()) | ||
| 326 | omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE); | ||
| 327 | else if (cpu_is_omap34xx()) | ||
| 328 | omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE); | ||
| 329 | else if (cpu_is_omap44xx()) | ||
| 330 | omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE); | ||
| 331 | else | ||
| 332 | pr_err("Could not initialize omap_irq_base\n"); | ||
| 333 | #endif | ||
| 334 | } | ||
| 335 | |||
| 336 | void __init omap2_init_common_infrastructure(void) | ||
| 316 | { | 337 | { |
| 317 | u8 skip_setup_idle = 0; | 338 | u8 postsetup_state; |
| 318 | 339 | ||
| 319 | pwrdm_init(powerdomains_omap); | 340 | if (cpu_is_omap242x()) { |
| 320 | clkdm_init(clockdomains_omap, clkdm_autodeps); | 341 | omap2xxx_powerdomains_init(); |
| 321 | if (cpu_is_omap242x()) | 342 | omap2_clockdomains_init(); |
| 322 | omap2420_hwmod_init(); | 343 | omap2420_hwmod_init(); |
| 323 | else if (cpu_is_omap243x()) | 344 | } else if (cpu_is_omap243x()) { |
| 345 | omap2xxx_powerdomains_init(); | ||
| 346 | omap2_clockdomains_init(); | ||
| 324 | omap2430_hwmod_init(); | 347 | omap2430_hwmod_init(); |
| 325 | else if (cpu_is_omap34xx()) | 348 | } else if (cpu_is_omap34xx()) { |
| 349 | omap3xxx_powerdomains_init(); | ||
| 350 | omap2_clockdomains_init(); | ||
| 326 | omap3xxx_hwmod_init(); | 351 | omap3xxx_hwmod_init(); |
| 327 | else if (cpu_is_omap44xx()) | 352 | } else if (cpu_is_omap44xx()) { |
| 353 | omap44xx_powerdomains_init(); | ||
| 354 | omap44xx_clockdomains_init(); | ||
| 328 | omap44xx_hwmod_init(); | 355 | omap44xx_hwmod_init(); |
| 356 | } else { | ||
| 357 | pr_err("Could not init hwmod data - unknown SoC\n"); | ||
| 358 | } | ||
| 359 | |||
| 360 | /* Set the default postsetup state for all hwmods */ | ||
| 361 | #ifdef CONFIG_PM_RUNTIME | ||
| 362 | postsetup_state = _HWMOD_STATE_IDLE; | ||
| 363 | #else | ||
| 364 | postsetup_state = _HWMOD_STATE_ENABLED; | ||
| 365 | #endif | ||
| 366 | omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state); | ||
| 367 | |||
| 368 | /* | ||
| 369 | * Set the default postsetup state for unusual modules (like | ||
| 370 | * MPU WDT). | ||
| 371 | * | ||
| 372 | * The postsetup_state is not actually used until | ||
| 373 | * omap_hwmod_late_init(), so boards that desire full watchdog | ||
| 374 | * coverage of kernel initialization can reprogram the | ||
| 375 | * postsetup_state between the calls to | ||
| 376 | * omap2_init_common_infra() and omap2_init_common_devices(). | ||
| 377 | * | ||
| 378 | * XXX ideally we could detect whether the MPU WDT was currently | ||
| 379 | * enabled here and make this conditional | ||
| 380 | */ | ||
| 381 | postsetup_state = _HWMOD_STATE_DISABLED; | ||
| 382 | omap_hwmod_for_each_by_class("wd_timer", | ||
| 383 | _set_hwmod_postsetup_state, | ||
| 384 | &postsetup_state); | ||
| 329 | 385 | ||
| 330 | /* The OPP tables have to be registered before a clk init */ | 386 | omap_pm_if_early_init(); |
| 331 | omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps); | ||
| 332 | 387 | ||
| 333 | if (cpu_is_omap2420()) | 388 | if (cpu_is_omap2420()) |
| 334 | omap2420_clk_init(); | 389 | omap2420_clk_init(); |
| @@ -339,17 +394,61 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, | |||
| 339 | else if (cpu_is_omap44xx()) | 394 | else if (cpu_is_omap44xx()) |
| 340 | omap4xxx_clk_init(); | 395 | omap4xxx_clk_init(); |
| 341 | else | 396 | else |
| 342 | pr_err("Could not init clock framework - unknown CPU\n"); | 397 | pr_err("Could not init clock framework - unknown SoC\n"); |
| 398 | } | ||
| 343 | 399 | ||
| 400 | void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0, | ||
| 401 | struct omap_sdrc_params *sdrc_cs1) | ||
| 402 | { | ||
| 344 | omap_serial_early_init(); | 403 | omap_serial_early_init(); |
| 345 | 404 | ||
| 346 | #ifndef CONFIG_PM_RUNTIME | 405 | omap_hwmod_late_init(); |
| 347 | skip_setup_idle = 1; | 406 | |
| 348 | #endif | ||
| 349 | omap_hwmod_late_init(skip_setup_idle); | ||
| 350 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | 407 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { |
| 351 | omap2_sdrc_init(sdrc_cs0, sdrc_cs1); | 408 | omap2_sdrc_init(sdrc_cs0, sdrc_cs1); |
| 352 | _omap2_init_reprogram_sdrc(); | 409 | _omap2_init_reprogram_sdrc(); |
| 353 | } | 410 | } |
| 354 | gpmc_init(); | 411 | gpmc_init(); |
| 412 | |||
| 413 | omap_irq_base_init(); | ||
| 414 | } | ||
| 415 | |||
| 416 | /* | ||
| 417 | * NOTE: Please use ioremap + __raw_read/write where possible instead of these | ||
| 418 | */ | ||
| 419 | |||
| 420 | u8 omap_readb(u32 pa) | ||
| 421 | { | ||
| 422 | return __raw_readb(OMAP2_L4_IO_ADDRESS(pa)); | ||
| 423 | } | ||
| 424 | EXPORT_SYMBOL(omap_readb); | ||
| 425 | |||
| 426 | u16 omap_readw(u32 pa) | ||
| 427 | { | ||
| 428 | return __raw_readw(OMAP2_L4_IO_ADDRESS(pa)); | ||
| 429 | } | ||
| 430 | EXPORT_SYMBOL(omap_readw); | ||
| 431 | |||
| 432 | u32 omap_readl(u32 pa) | ||
| 433 | { | ||
| 434 | return __raw_readl(OMAP2_L4_IO_ADDRESS(pa)); | ||
| 435 | } | ||
| 436 | EXPORT_SYMBOL(omap_readl); | ||
| 437 | |||
| 438 | void omap_writeb(u8 v, u32 pa) | ||
| 439 | { | ||
| 440 | __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa)); | ||
| 441 | } | ||
| 442 | EXPORT_SYMBOL(omap_writeb); | ||
| 443 | |||
| 444 | void omap_writew(u16 v, u32 pa) | ||
| 445 | { | ||
| 446 | __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa)); | ||
| 447 | } | ||
| 448 | EXPORT_SYMBOL(omap_writew); | ||
| 449 | |||
| 450 | void omap_writel(u32 v, u32 pa) | ||
| 451 | { | ||
| 452 | __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa)); | ||
| 355 | } | 453 | } |
| 454 | EXPORT_SYMBOL(omap_writel); | ||
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index 32eeabe9d2ab..85bf8ca95fd3 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c | |||
| @@ -284,7 +284,10 @@ void omap3_intc_suspend(void) | |||
| 284 | 284 | ||
| 285 | void omap3_intc_prepare_idle(void) | 285 | void omap3_intc_prepare_idle(void) |
| 286 | { | 286 | { |
| 287 | /* Disable autoidle as it can stall interrupt controller */ | 287 | /* |
| 288 | * Disable autoidle as it can stall interrupt controller, | ||
| 289 | * cf. errata ID i540 for 3430 (all revisions up to 3.1.x) | ||
| 290 | */ | ||
| 288 | intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG); | 291 | intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG); |
| 289 | } | 292 | } |
| 290 | 293 | ||
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c index 40ddecab93a9..394413dc7deb 100644 --- a/arch/arm/mach-omap2/mailbox.c +++ b/arch/arm/mach-omap2/mailbox.c | |||
| @@ -281,7 +281,7 @@ static struct omap_mbox_ops omap2_mbox_ops = { | |||
| 281 | 281 | ||
| 282 | /* FIXME: the following structs should be filled automatically by the user id */ | 282 | /* FIXME: the following structs should be filled automatically by the user id */ |
| 283 | 283 | ||
| 284 | #if defined(CONFIG_ARCH_OMAP3430) || defined(CONFIG_ARCH_OMAP2420) | 284 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP2) |
| 285 | /* DSP */ | 285 | /* DSP */ |
| 286 | static struct omap_mbox2_priv omap2_mbox_dsp_priv = { | 286 | static struct omap_mbox2_priv omap2_mbox_dsp_priv = { |
| 287 | .tx_fifo = { | 287 | .tx_fifo = { |
| @@ -306,7 +306,7 @@ struct omap_mbox mbox_dsp_info = { | |||
| 306 | }; | 306 | }; |
| 307 | #endif | 307 | #endif |
| 308 | 308 | ||
| 309 | #if defined(CONFIG_ARCH_OMAP3430) | 309 | #if defined(CONFIG_ARCH_OMAP3) |
| 310 | struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL }; | 310 | struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL }; |
| 311 | #endif | 311 | #endif |
| 312 | 312 | ||
| @@ -394,15 +394,19 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev) | |||
| 394 | 394 | ||
| 395 | if (false) | 395 | if (false) |
| 396 | ; | 396 | ; |
| 397 | #if defined(CONFIG_ARCH_OMAP3430) | 397 | #if defined(CONFIG_ARCH_OMAP3) |
| 398 | else if (cpu_is_omap3430()) { | 398 | else if (cpu_is_omap34xx()) { |
| 399 | list = omap3_mboxes; | 399 | list = omap3_mboxes; |
| 400 | 400 | ||
| 401 | list[0]->irq = platform_get_irq_byname(pdev, "dsp"); | 401 | list[0]->irq = platform_get_irq_byname(pdev, "dsp"); |
| 402 | } | 402 | } |
| 403 | #endif | 403 | #endif |
| 404 | #if defined(CONFIG_ARCH_OMAP2420) | 404 | #if defined(CONFIG_ARCH_OMAP2) |
| 405 | else if (cpu_is_omap2420()) { | 405 | else if (cpu_is_omap2430()) { |
| 406 | list = omap2_mboxes; | ||
| 407 | |||
| 408 | list[0]->irq = platform_get_irq_byname(pdev, "dsp"); | ||
| 409 | } else if (cpu_is_omap2420()) { | ||
| 406 | list = omap2_mboxes; | 410 | list = omap2_mboxes; |
| 407 | 411 | ||
| 408 | list[0]->irq = platform_get_irq_byname(pdev, "dsp"); | 412 | list[0]->irq = platform_get_irq_byname(pdev, "dsp"); |
| @@ -432,9 +436,8 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev) | |||
| 432 | iounmap(mbox_base); | 436 | iounmap(mbox_base); |
| 433 | return ret; | 437 | return ret; |
| 434 | } | 438 | } |
| 435 | return 0; | ||
| 436 | 439 | ||
| 437 | return ret; | 440 | return 0; |
| 438 | } | 441 | } |
| 439 | 442 | ||
| 440 | static int __devexit omap2_mbox_remove(struct platform_device *pdev) | 443 | static int __devexit omap2_mbox_remove(struct platform_device *pdev) |
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 074536ae401f..17bd6394d224 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c | |||
| @@ -1,9 +1,9 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * linux/arch/arm/mach-omap2/mux.c | 2 | * linux/arch/arm/mach-omap2/mux.c |
| 3 | * | 3 | * |
| 4 | * OMAP2 and OMAP3 pin multiplexing configurations | 4 | * OMAP2, OMAP3 and OMAP4 pin multiplexing configurations |
| 5 | * | 5 | * |
| 6 | * Copyright (C) 2004 - 2008 Texas Instruments Inc. | 6 | * Copyright (C) 2004 - 2010 Texas Instruments Inc. |
| 7 | * Copyright (C) 2003 - 2008 Nokia Corporation | 7 | * Copyright (C) 2003 - 2008 Nokia Corporation |
| 8 | * | 8 | * |
| 9 | * Written by Tony Lindgren | 9 | * Written by Tony Lindgren |
| @@ -35,65 +35,79 @@ | |||
| 35 | 35 | ||
| 36 | #include <asm/system.h> | 36 | #include <asm/system.h> |
| 37 | 37 | ||
| 38 | #include <plat/omap_hwmod.h> | ||
| 39 | |||
| 38 | #include "control.h" | 40 | #include "control.h" |
| 39 | #include "mux.h" | 41 | #include "mux.h" |
| 40 | 42 | ||
| 41 | #define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */ | 43 | #define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */ |
| 42 | #define OMAP_MUX_BASE_SZ 0x5ca | 44 | #define OMAP_MUX_BASE_SZ 0x5ca |
| 43 | #define MUXABLE_GPIO_MODE3 BIT(0) | ||
| 44 | 45 | ||
| 45 | struct omap_mux_entry { | 46 | struct omap_mux_entry { |
| 46 | struct omap_mux mux; | 47 | struct omap_mux mux; |
| 47 | struct list_head node; | 48 | struct list_head node; |
| 48 | }; | 49 | }; |
| 49 | 50 | ||
| 50 | static unsigned long mux_phys; | 51 | static LIST_HEAD(mux_partitions); |
| 51 | static void __iomem *mux_base; | 52 | static DEFINE_MUTEX(muxmode_mutex); |
| 52 | static u8 omap_mux_flags; | 53 | |
| 54 | struct omap_mux_partition *omap_mux_get(const char *name) | ||
| 55 | { | ||
| 56 | struct omap_mux_partition *partition; | ||
| 57 | |||
| 58 | list_for_each_entry(partition, &mux_partitions, node) { | ||
| 59 | if (!strcmp(name, partition->name)) | ||
| 60 | return partition; | ||
| 61 | } | ||
| 62 | |||
| 63 | return NULL; | ||
| 64 | } | ||
| 53 | 65 | ||
| 54 | u16 omap_mux_read(u16 reg) | 66 | u16 omap_mux_read(struct omap_mux_partition *partition, u16 reg) |
| 55 | { | 67 | { |
| 56 | if (cpu_is_omap24xx()) | 68 | if (partition->flags & OMAP_MUX_REG_8BIT) |
| 57 | return __raw_readb(mux_base + reg); | 69 | return __raw_readb(partition->base + reg); |
| 58 | else | 70 | else |
| 59 | return __raw_readw(mux_base + reg); | 71 | return __raw_readw(partition->base + reg); |
| 60 | } | 72 | } |
| 61 | 73 | ||
| 62 | void omap_mux_write(u16 val, u16 reg) | 74 | void omap_mux_write(struct omap_mux_partition *partition, u16 val, |
| 75 | u16 reg) | ||
| 63 | { | 76 | { |
| 64 | if (cpu_is_omap24xx()) | 77 | if (partition->flags & OMAP_MUX_REG_8BIT) |
| 65 | __raw_writeb(val, mux_base + reg); | 78 | __raw_writeb(val, partition->base + reg); |
| 66 | else | 79 | else |
| 67 | __raw_writew(val, mux_base + reg); | 80 | __raw_writew(val, partition->base + reg); |
| 68 | } | 81 | } |
| 69 | 82 | ||
| 70 | void omap_mux_write_array(struct omap_board_mux *board_mux) | 83 | void omap_mux_write_array(struct omap_mux_partition *partition, |
| 84 | struct omap_board_mux *board_mux) | ||
| 71 | { | 85 | { |
| 72 | while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) { | 86 | while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) { |
| 73 | omap_mux_write(board_mux->value, board_mux->reg_offset); | 87 | omap_mux_write(partition, board_mux->value, |
| 88 | board_mux->reg_offset); | ||
| 74 | board_mux++; | 89 | board_mux++; |
| 75 | } | 90 | } |
| 76 | } | 91 | } |
| 77 | 92 | ||
| 78 | static LIST_HEAD(muxmodes); | ||
| 79 | static DEFINE_MUTEX(muxmode_mutex); | ||
| 80 | |||
| 81 | #ifdef CONFIG_OMAP_MUX | 93 | #ifdef CONFIG_OMAP_MUX |
| 82 | 94 | ||
| 83 | static char *omap_mux_options; | 95 | static char *omap_mux_options; |
| 84 | 96 | ||
| 85 | int __init omap_mux_init_gpio(int gpio, int val) | 97 | static int __init _omap_mux_init_gpio(struct omap_mux_partition *partition, |
| 98 | int gpio, int val) | ||
| 86 | { | 99 | { |
| 87 | struct omap_mux_entry *e; | 100 | struct omap_mux_entry *e; |
| 88 | struct omap_mux *gpio_mux = NULL; | 101 | struct omap_mux *gpio_mux = NULL; |
| 89 | u16 old_mode; | 102 | u16 old_mode; |
| 90 | u16 mux_mode; | 103 | u16 mux_mode; |
| 91 | int found = 0; | 104 | int found = 0; |
| 105 | struct list_head *muxmodes = &partition->muxmodes; | ||
| 92 | 106 | ||
| 93 | if (!gpio) | 107 | if (!gpio) |
| 94 | return -EINVAL; | 108 | return -EINVAL; |
| 95 | 109 | ||
| 96 | list_for_each_entry(e, &muxmodes, node) { | 110 | list_for_each_entry(e, muxmodes, node) { |
| 97 | struct omap_mux *m = &e->mux; | 111 | struct omap_mux *m = &e->mux; |
| 98 | if (gpio == m->gpio) { | 112 | if (gpio == m->gpio) { |
| 99 | gpio_mux = m; | 113 | gpio_mux = m; |
| @@ -102,34 +116,52 @@ int __init omap_mux_init_gpio(int gpio, int val) | |||
| 102 | } | 116 | } |
| 103 | 117 | ||
| 104 | if (found == 0) { | 118 | if (found == 0) { |
| 105 | printk(KERN_ERR "mux: Could not set gpio%i\n", gpio); | 119 | pr_err("%s: Could not set gpio%i\n", __func__, gpio); |
| 106 | return -ENODEV; | 120 | return -ENODEV; |
| 107 | } | 121 | } |
| 108 | 122 | ||
| 109 | if (found > 1) { | 123 | if (found > 1) { |
| 110 | printk(KERN_INFO "mux: Multiple gpio paths (%d) for gpio%i\n", | 124 | pr_info("%s: Multiple gpio paths (%d) for gpio%i\n", __func__, |
| 111 | found, gpio); | 125 | found, gpio); |
| 112 | return -EINVAL; | 126 | return -EINVAL; |
| 113 | } | 127 | } |
| 114 | 128 | ||
| 115 | old_mode = omap_mux_read(gpio_mux->reg_offset); | 129 | old_mode = omap_mux_read(partition, gpio_mux->reg_offset); |
| 116 | mux_mode = val & ~(OMAP_MUX_NR_MODES - 1); | 130 | mux_mode = val & ~(OMAP_MUX_NR_MODES - 1); |
| 117 | if (omap_mux_flags & MUXABLE_GPIO_MODE3) | 131 | if (partition->flags & OMAP_MUX_GPIO_IN_MODE3) |
| 118 | mux_mode |= OMAP_MUX_MODE3; | 132 | mux_mode |= OMAP_MUX_MODE3; |
| 119 | else | 133 | else |
| 120 | mux_mode |= OMAP_MUX_MODE4; | 134 | mux_mode |= OMAP_MUX_MODE4; |
| 121 | printk(KERN_DEBUG "mux: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n", | 135 | pr_debug("%s: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n", __func__, |
| 122 | gpio_mux->muxnames[0], gpio, old_mode, mux_mode); | 136 | gpio_mux->muxnames[0], gpio, old_mode, mux_mode); |
| 123 | omap_mux_write(mux_mode, gpio_mux->reg_offset); | 137 | omap_mux_write(partition, mux_mode, gpio_mux->reg_offset); |
| 124 | 138 | ||
| 125 | return 0; | 139 | return 0; |
| 126 | } | 140 | } |
| 127 | 141 | ||
| 128 | int __init omap_mux_init_signal(const char *muxname, int val) | 142 | int __init omap_mux_init_gpio(int gpio, int val) |
| 143 | { | ||
| 144 | struct omap_mux_partition *partition; | ||
| 145 | int ret; | ||
| 146 | |||
| 147 | list_for_each_entry(partition, &mux_partitions, node) { | ||
| 148 | ret = _omap_mux_init_gpio(partition, gpio, val); | ||
| 149 | if (!ret) | ||
| 150 | return ret; | ||
| 151 | } | ||
| 152 | |||
| 153 | return -ENODEV; | ||
| 154 | } | ||
| 155 | |||
| 156 | static int __init _omap_mux_get_by_name(struct omap_mux_partition *partition, | ||
| 157 | const char *muxname, | ||
| 158 | struct omap_mux **found_mux) | ||
| 129 | { | 159 | { |
| 160 | struct omap_mux *mux = NULL; | ||
| 130 | struct omap_mux_entry *e; | 161 | struct omap_mux_entry *e; |
| 131 | const char *mode_name; | 162 | const char *mode_name; |
| 132 | int found = 0, mode0_len = 0; | 163 | int found = 0, found_mode, mode0_len = 0; |
| 164 | struct list_head *muxmodes = &partition->muxmodes; | ||
| 133 | 165 | ||
| 134 | mode_name = strchr(muxname, '.'); | 166 | mode_name = strchr(muxname, '.'); |
| 135 | if (mode_name) { | 167 | if (mode_name) { |
| @@ -139,51 +171,200 @@ int __init omap_mux_init_signal(const char *muxname, int val) | |||
| 139 | mode_name = muxname; | 171 | mode_name = muxname; |
| 140 | } | 172 | } |
| 141 | 173 | ||
| 142 | list_for_each_entry(e, &muxmodes, node) { | 174 | list_for_each_entry(e, muxmodes, node) { |
| 143 | struct omap_mux *m = &e->mux; | 175 | char *m0_entry; |
| 144 | char *m0_entry = m->muxnames[0]; | ||
| 145 | int i; | 176 | int i; |
| 146 | 177 | ||
| 178 | mux = &e->mux; | ||
| 179 | m0_entry = mux->muxnames[0]; | ||
| 180 | |||
| 147 | /* First check for full name in mode0.muxmode format */ | 181 | /* First check for full name in mode0.muxmode format */ |
| 148 | if (mode0_len && strncmp(muxname, m0_entry, mode0_len)) | 182 | if (mode0_len && strncmp(muxname, m0_entry, mode0_len)) |
| 149 | continue; | 183 | continue; |
| 150 | 184 | ||
| 151 | /* Then check for muxmode only */ | 185 | /* Then check for muxmode only */ |
| 152 | for (i = 0; i < OMAP_MUX_NR_MODES; i++) { | 186 | for (i = 0; i < OMAP_MUX_NR_MODES; i++) { |
| 153 | char *mode_cur = m->muxnames[i]; | 187 | char *mode_cur = mux->muxnames[i]; |
| 154 | 188 | ||
| 155 | if (!mode_cur) | 189 | if (!mode_cur) |
| 156 | continue; | 190 | continue; |
| 157 | 191 | ||
| 158 | if (!strcmp(mode_name, mode_cur)) { | 192 | if (!strcmp(mode_name, mode_cur)) { |
| 159 | u16 old_mode; | 193 | *found_mux = mux; |
| 160 | u16 mux_mode; | ||
| 161 | |||
| 162 | old_mode = omap_mux_read(m->reg_offset); | ||
| 163 | mux_mode = val | i; | ||
| 164 | printk(KERN_DEBUG "mux: Setting signal " | ||
| 165 | "%s.%s 0x%04x -> 0x%04x\n", | ||
| 166 | m0_entry, muxname, old_mode, mux_mode); | ||
| 167 | omap_mux_write(mux_mode, m->reg_offset); | ||
| 168 | found++; | 194 | found++; |
| 195 | found_mode = i; | ||
| 169 | } | 196 | } |
| 170 | } | 197 | } |
| 171 | } | 198 | } |
| 172 | 199 | ||
| 173 | if (found == 1) | 200 | if (found == 1) { |
| 174 | return 0; | 201 | return found_mode; |
| 202 | } | ||
| 175 | 203 | ||
| 176 | if (found > 1) { | 204 | if (found > 1) { |
| 177 | printk(KERN_ERR "mux: Multiple signal paths (%i) for %s\n", | 205 | pr_err("%s: Multiple signal paths (%i) for %s\n", __func__, |
| 178 | found, muxname); | 206 | found, muxname); |
| 179 | return -EINVAL; | 207 | return -EINVAL; |
| 180 | } | 208 | } |
| 181 | 209 | ||
| 182 | printk(KERN_ERR "mux: Could not set signal %s\n", muxname); | 210 | pr_err("%s: Could not find signal %s\n", __func__, muxname); |
| 183 | 211 | ||
| 184 | return -ENODEV; | 212 | return -ENODEV; |
| 185 | } | 213 | } |
| 186 | 214 | ||
| 215 | static int __init | ||
| 216 | omap_mux_get_by_name(const char *muxname, | ||
| 217 | struct omap_mux_partition **found_partition, | ||
| 218 | struct omap_mux **found_mux) | ||
| 219 | { | ||
| 220 | struct omap_mux_partition *partition; | ||
| 221 | |||
| 222 | list_for_each_entry(partition, &mux_partitions, node) { | ||
| 223 | struct omap_mux *mux = NULL; | ||
| 224 | int mux_mode = _omap_mux_get_by_name(partition, muxname, &mux); | ||
| 225 | if (mux_mode < 0) | ||
| 226 | continue; | ||
| 227 | |||
| 228 | *found_partition = partition; | ||
| 229 | *found_mux = mux; | ||
| 230 | |||
| 231 | return mux_mode; | ||
| 232 | } | ||
| 233 | |||
| 234 | return -ENODEV; | ||
| 235 | } | ||
| 236 | |||
| 237 | int __init omap_mux_init_signal(const char *muxname, int val) | ||
| 238 | { | ||
| 239 | struct omap_mux_partition *partition = NULL; | ||
| 240 | struct omap_mux *mux = NULL; | ||
| 241 | u16 old_mode; | ||
| 242 | int mux_mode; | ||
| 243 | |||
| 244 | mux_mode = omap_mux_get_by_name(muxname, &partition, &mux); | ||
| 245 | if (mux_mode < 0) | ||
| 246 | return mux_mode; | ||
| 247 | |||
| 248 | old_mode = omap_mux_read(partition, mux->reg_offset); | ||
| 249 | mux_mode |= val; | ||
| 250 | pr_debug("%s: Setting signal %s 0x%04x -> 0x%04x\n", | ||
| 251 | __func__, muxname, old_mode, mux_mode); | ||
| 252 | omap_mux_write(partition, mux_mode, mux->reg_offset); | ||
| 253 | |||
| 254 | return 0; | ||
| 255 | } | ||
| 256 | |||
| 257 | struct omap_hwmod_mux_info * __init | ||
| 258 | omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads) | ||
| 259 | { | ||
| 260 | struct omap_hwmod_mux_info *hmux; | ||
| 261 | int i; | ||
| 262 | |||
| 263 | if (!bpads || nr_pads < 1) | ||
| 264 | return NULL; | ||
| 265 | |||
| 266 | hmux = kzalloc(sizeof(struct omap_hwmod_mux_info), GFP_KERNEL); | ||
| 267 | if (!hmux) | ||
| 268 | goto err1; | ||
| 269 | |||
| 270 | hmux->nr_pads = nr_pads; | ||
| 271 | |||
| 272 | hmux->pads = kzalloc(sizeof(struct omap_device_pad) * | ||
| 273 | nr_pads, GFP_KERNEL); | ||
| 274 | if (!hmux->pads) | ||
| 275 | goto err2; | ||
| 276 | |||
| 277 | for (i = 0; i < hmux->nr_pads; i++) { | ||
| 278 | struct omap_mux_partition *partition; | ||
| 279 | struct omap_device_pad *bpad = &bpads[i], *pad = &hmux->pads[i]; | ||
| 280 | struct omap_mux *mux; | ||
| 281 | int mux_mode; | ||
| 282 | |||
| 283 | mux_mode = omap_mux_get_by_name(bpad->name, &partition, &mux); | ||
| 284 | if (mux_mode < 0) | ||
| 285 | goto err3; | ||
| 286 | if (!pad->partition) | ||
| 287 | pad->partition = partition; | ||
| 288 | if (!pad->mux) | ||
| 289 | pad->mux = mux; | ||
| 290 | |||
| 291 | pad->name = kzalloc(strlen(bpad->name) + 1, GFP_KERNEL); | ||
| 292 | if (!pad->name) { | ||
| 293 | int j; | ||
| 294 | |||
| 295 | for (j = i - 1; j >= 0; j--) | ||
| 296 | kfree(hmux->pads[j].name); | ||
| 297 | goto err3; | ||
| 298 | } | ||
| 299 | strcpy(pad->name, bpad->name); | ||
| 300 | |||
| 301 | pad->flags = bpad->flags; | ||
| 302 | pad->enable = bpad->enable; | ||
| 303 | pad->idle = bpad->idle; | ||
| 304 | pad->off = bpad->off; | ||
| 305 | pr_debug("%s: Initialized %s\n", __func__, pad->name); | ||
| 306 | } | ||
| 307 | |||
| 308 | return hmux; | ||
| 309 | |||
| 310 | err3: | ||
| 311 | kfree(hmux->pads); | ||
| 312 | err2: | ||
| 313 | kfree(hmux); | ||
| 314 | err1: | ||
| 315 | pr_err("%s: Could not allocate device mux entry\n", __func__); | ||
| 316 | |||
| 317 | return NULL; | ||
| 318 | } | ||
| 319 | |||
| 320 | /* Assumes the calling function takes care of locking */ | ||
| 321 | void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state) | ||
| 322 | { | ||
| 323 | int i; | ||
| 324 | |||
| 325 | for (i = 0; i < hmux->nr_pads; i++) { | ||
| 326 | struct omap_device_pad *pad = &hmux->pads[i]; | ||
| 327 | int flags, val = -EINVAL; | ||
| 328 | |||
| 329 | flags = pad->flags; | ||
| 330 | |||
| 331 | switch (state) { | ||
| 332 | case _HWMOD_STATE_ENABLED: | ||
| 333 | if (flags & OMAP_DEVICE_PAD_ENABLED) | ||
| 334 | break; | ||
| 335 | flags |= OMAP_DEVICE_PAD_ENABLED; | ||
| 336 | val = pad->enable; | ||
| 337 | pr_debug("%s: Enabling %s %x\n", __func__, | ||
| 338 | pad->name, val); | ||
| 339 | break; | ||
| 340 | case _HWMOD_STATE_IDLE: | ||
| 341 | if (!(flags & OMAP_DEVICE_PAD_REMUX)) | ||
| 342 | break; | ||
| 343 | flags &= ~OMAP_DEVICE_PAD_ENABLED; | ||
| 344 | val = pad->idle; | ||
| 345 | pr_debug("%s: Idling %s %x\n", __func__, | ||
| 346 | pad->name, val); | ||
| 347 | break; | ||
| 348 | case _HWMOD_STATE_DISABLED: | ||
| 349 | default: | ||
| 350 | /* Use safe mode unless OMAP_DEVICE_PAD_REMUX */ | ||
| 351 | if (flags & OMAP_DEVICE_PAD_REMUX) | ||
| 352 | val = pad->off; | ||
| 353 | else | ||
| 354 | val = OMAP_MUX_MODE7; | ||
| 355 | flags &= ~OMAP_DEVICE_PAD_ENABLED; | ||
| 356 | pr_debug("%s: Disabling %s %x\n", __func__, | ||
| 357 | pad->name, val); | ||
| 358 | }; | ||
| 359 | |||
| 360 | if (val >= 0) { | ||
| 361 | omap_mux_write(pad->partition, val, | ||
| 362 | pad->mux->reg_offset); | ||
| 363 | pad->flags = flags; | ||
| 364 | } | ||
| 365 | } | ||
| 366 | } | ||
| 367 | |||
| 187 | #ifdef CONFIG_DEBUG_FS | 368 | #ifdef CONFIG_DEBUG_FS |
| 188 | 369 | ||
| 189 | #define OMAP_MUX_MAX_NR_FLAGS 10 | 370 | #define OMAP_MUX_MAX_NR_FLAGS 10 |
| @@ -248,13 +429,15 @@ static inline void omap_mux_decode(struct seq_file *s, u16 val) | |||
| 248 | } while (i-- > 0); | 429 | } while (i-- > 0); |
| 249 | } | 430 | } |
| 250 | 431 | ||
| 251 | #define OMAP_MUX_DEFNAME_LEN 16 | 432 | #define OMAP_MUX_DEFNAME_LEN 32 |
| 252 | 433 | ||
| 253 | static int omap_mux_dbg_board_show(struct seq_file *s, void *unused) | 434 | static int omap_mux_dbg_board_show(struct seq_file *s, void *unused) |
| 254 | { | 435 | { |
| 436 | struct omap_mux_partition *partition = s->private; | ||
| 255 | struct omap_mux_entry *e; | 437 | struct omap_mux_entry *e; |
| 438 | u8 omap_gen = omap_rev() >> 28; | ||
| 256 | 439 | ||
| 257 | list_for_each_entry(e, &muxmodes, node) { | 440 | list_for_each_entry(e, &partition->muxmodes, node) { |
| 258 | struct omap_mux *m = &e->mux; | 441 | struct omap_mux *m = &e->mux; |
| 259 | char m0_def[OMAP_MUX_DEFNAME_LEN]; | 442 | char m0_def[OMAP_MUX_DEFNAME_LEN]; |
| 260 | char *m0_name = m->muxnames[0]; | 443 | char *m0_name = m->muxnames[0]; |
| @@ -272,11 +455,16 @@ static int omap_mux_dbg_board_show(struct seq_file *s, void *unused) | |||
| 272 | } | 455 | } |
| 273 | m0_def[i] = toupper(m0_name[i]); | 456 | m0_def[i] = toupper(m0_name[i]); |
| 274 | } | 457 | } |
| 275 | val = omap_mux_read(m->reg_offset); | 458 | val = omap_mux_read(partition, m->reg_offset); |
| 276 | mode = val & OMAP_MUX_MODE7; | 459 | mode = val & OMAP_MUX_MODE7; |
| 277 | 460 | if (mode != 0) | |
| 278 | seq_printf(s, "OMAP%i_MUX(%s, ", | 461 | seq_printf(s, "/* %s */\n", m->muxnames[mode]); |
| 279 | cpu_is_omap34xx() ? 3 : 0, m0_def); | 462 | |
| 463 | /* | ||
| 464 | * XXX: Might be revisited to support differences accross | ||
| 465 | * same OMAP generation. | ||
| 466 | */ | ||
| 467 | seq_printf(s, "OMAP%d_MUX(%s, ", omap_gen, m0_def); | ||
| 280 | omap_mux_decode(s, val); | 468 | omap_mux_decode(s, val); |
| 281 | seq_printf(s, "),\n"); | 469 | seq_printf(s, "),\n"); |
| 282 | } | 470 | } |
| @@ -286,7 +474,7 @@ static int omap_mux_dbg_board_show(struct seq_file *s, void *unused) | |||
| 286 | 474 | ||
| 287 | static int omap_mux_dbg_board_open(struct inode *inode, struct file *file) | 475 | static int omap_mux_dbg_board_open(struct inode *inode, struct file *file) |
| 288 | { | 476 | { |
| 289 | return single_open(file, omap_mux_dbg_board_show, &inode->i_private); | 477 | return single_open(file, omap_mux_dbg_board_show, inode->i_private); |
| 290 | } | 478 | } |
| 291 | 479 | ||
| 292 | static const struct file_operations omap_mux_dbg_board_fops = { | 480 | static const struct file_operations omap_mux_dbg_board_fops = { |
| @@ -296,19 +484,43 @@ static const struct file_operations omap_mux_dbg_board_fops = { | |||
| 296 | .release = single_release, | 484 | .release = single_release, |
| 297 | }; | 485 | }; |
| 298 | 486 | ||
| 487 | static struct omap_mux_partition *omap_mux_get_partition(struct omap_mux *mux) | ||
| 488 | { | ||
| 489 | struct omap_mux_partition *partition; | ||
| 490 | |||
| 491 | list_for_each_entry(partition, &mux_partitions, node) { | ||
| 492 | struct list_head *muxmodes = &partition->muxmodes; | ||
| 493 | struct omap_mux_entry *e; | ||
| 494 | |||
| 495 | list_for_each_entry(e, muxmodes, node) { | ||
| 496 | struct omap_mux *m = &e->mux; | ||
| 497 | |||
| 498 | if (m == mux) | ||
| 499 | return partition; | ||
| 500 | } | ||
| 501 | } | ||
| 502 | |||
| 503 | return NULL; | ||
| 504 | } | ||
| 505 | |||
| 299 | static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused) | 506 | static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused) |
| 300 | { | 507 | { |
| 301 | struct omap_mux *m = s->private; | 508 | struct omap_mux *m = s->private; |
| 509 | struct omap_mux_partition *partition; | ||
| 302 | const char *none = "NA"; | 510 | const char *none = "NA"; |
| 303 | u16 val; | 511 | u16 val; |
| 304 | int mode; | 512 | int mode; |
| 305 | 513 | ||
| 306 | val = omap_mux_read(m->reg_offset); | 514 | partition = omap_mux_get_partition(m); |
| 515 | if (!partition) | ||
| 516 | return 0; | ||
| 517 | |||
| 518 | val = omap_mux_read(partition, m->reg_offset); | ||
| 307 | mode = val & OMAP_MUX_MODE7; | 519 | mode = val & OMAP_MUX_MODE7; |
| 308 | 520 | ||
| 309 | seq_printf(s, "name: %s.%s (0x%08lx/0x%03x = 0x%04x), b %s, t %s\n", | 521 | seq_printf(s, "name: %s.%s (0x%08x/0x%03x = 0x%04x), b %s, t %s\n", |
| 310 | m->muxnames[0], m->muxnames[mode], | 522 | m->muxnames[0], m->muxnames[mode], |
| 311 | mux_phys + m->reg_offset, m->reg_offset, val, | 523 | partition->phys + m->reg_offset, m->reg_offset, val, |
| 312 | m->balls[0] ? m->balls[0] : none, | 524 | m->balls[0] ? m->balls[0] : none, |
| 313 | m->balls[1] ? m->balls[1] : none); | 525 | m->balls[1] ? m->balls[1] : none); |
| 314 | seq_printf(s, "mode: "); | 526 | seq_printf(s, "mode: "); |
| @@ -330,14 +542,15 @@ static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused) | |||
| 330 | #define OMAP_MUX_MAX_ARG_CHAR 7 | 542 | #define OMAP_MUX_MAX_ARG_CHAR 7 |
| 331 | 543 | ||
| 332 | static ssize_t omap_mux_dbg_signal_write(struct file *file, | 544 | static ssize_t omap_mux_dbg_signal_write(struct file *file, |
| 333 | const char __user *user_buf, | 545 | const char __user *user_buf, |
| 334 | size_t count, loff_t *ppos) | 546 | size_t count, loff_t *ppos) |
| 335 | { | 547 | { |
| 336 | char buf[OMAP_MUX_MAX_ARG_CHAR]; | 548 | char buf[OMAP_MUX_MAX_ARG_CHAR]; |
| 337 | struct seq_file *seqf; | 549 | struct seq_file *seqf; |
| 338 | struct omap_mux *m; | 550 | struct omap_mux *m; |
| 339 | unsigned long val; | 551 | unsigned long val; |
| 340 | int buf_size, ret; | 552 | int buf_size, ret; |
| 553 | struct omap_mux_partition *partition; | ||
| 341 | 554 | ||
| 342 | if (count > OMAP_MUX_MAX_ARG_CHAR) | 555 | if (count > OMAP_MUX_MAX_ARG_CHAR) |
| 343 | return -EINVAL; | 556 | return -EINVAL; |
| @@ -358,7 +571,11 @@ static ssize_t omap_mux_dbg_signal_write(struct file *file, | |||
| 358 | seqf = file->private_data; | 571 | seqf = file->private_data; |
| 359 | m = seqf->private; | 572 | m = seqf->private; |
| 360 | 573 | ||
| 361 | omap_mux_write((u16)val, m->reg_offset); | 574 | partition = omap_mux_get_partition(m); |
| 575 | if (!partition) | ||
| 576 | return -ENODEV; | ||
| 577 | |||
| 578 | omap_mux_write(partition, (u16)val, m->reg_offset); | ||
| 362 | *ppos += count; | 579 | *ppos += count; |
| 363 | 580 | ||
| 364 | return count; | 581 | return count; |
| @@ -379,22 +596,38 @@ static const struct file_operations omap_mux_dbg_signal_fops = { | |||
| 379 | 596 | ||
| 380 | static struct dentry *mux_dbg_dir; | 597 | static struct dentry *mux_dbg_dir; |
| 381 | 598 | ||
| 382 | static void __init omap_mux_dbg_init(void) | 599 | static void __init omap_mux_dbg_create_entry( |
| 600 | struct omap_mux_partition *partition, | ||
| 601 | struct dentry *mux_dbg_dir) | ||
| 383 | { | 602 | { |
| 384 | struct omap_mux_entry *e; | 603 | struct omap_mux_entry *e; |
| 385 | 604 | ||
| 605 | list_for_each_entry(e, &partition->muxmodes, node) { | ||
| 606 | struct omap_mux *m = &e->mux; | ||
| 607 | |||
| 608 | (void)debugfs_create_file(m->muxnames[0], S_IWUGO, mux_dbg_dir, | ||
| 609 | m, &omap_mux_dbg_signal_fops); | ||
| 610 | } | ||
| 611 | } | ||
| 612 | |||
| 613 | static void __init omap_mux_dbg_init(void) | ||
| 614 | { | ||
| 615 | struct omap_mux_partition *partition; | ||
| 616 | static struct dentry *mux_dbg_board_dir; | ||
| 617 | |||
| 386 | mux_dbg_dir = debugfs_create_dir("omap_mux", NULL); | 618 | mux_dbg_dir = debugfs_create_dir("omap_mux", NULL); |
| 387 | if (!mux_dbg_dir) | 619 | if (!mux_dbg_dir) |
| 388 | return; | 620 | return; |
| 389 | 621 | ||
| 390 | (void)debugfs_create_file("board", S_IRUGO, mux_dbg_dir, | 622 | mux_dbg_board_dir = debugfs_create_dir("board", mux_dbg_dir); |
| 391 | NULL, &omap_mux_dbg_board_fops); | 623 | if (!mux_dbg_board_dir) |
| 392 | 624 | return; | |
| 393 | list_for_each_entry(e, &muxmodes, node) { | ||
| 394 | struct omap_mux *m = &e->mux; | ||
| 395 | 625 | ||
| 396 | (void)debugfs_create_file(m->muxnames[0], S_IWUGO, mux_dbg_dir, | 626 | list_for_each_entry(partition, &mux_partitions, node) { |
| 397 | m, &omap_mux_dbg_signal_fops); | 627 | omap_mux_dbg_create_entry(partition, mux_dbg_dir); |
| 628 | (void)debugfs_create_file(partition->name, S_IRUGO, | ||
| 629 | mux_dbg_board_dir, partition, | ||
| 630 | &omap_mux_dbg_board_fops); | ||
| 398 | } | 631 | } |
| 399 | } | 632 | } |
| 400 | 633 | ||
| @@ -421,23 +654,25 @@ static void __init omap_mux_free_names(struct omap_mux *m) | |||
| 421 | /* Free all data except for GPIO pins unless CONFIG_DEBUG_FS is set */ | 654 | /* Free all data except for GPIO pins unless CONFIG_DEBUG_FS is set */ |
| 422 | static int __init omap_mux_late_init(void) | 655 | static int __init omap_mux_late_init(void) |
| 423 | { | 656 | { |
| 424 | struct omap_mux_entry *e, *tmp; | 657 | struct omap_mux_partition *partition; |
| 425 | 658 | ||
| 426 | list_for_each_entry_safe(e, tmp, &muxmodes, node) { | 659 | list_for_each_entry(partition, &mux_partitions, node) { |
| 427 | struct omap_mux *m = &e->mux; | 660 | struct omap_mux_entry *e, *tmp; |
| 428 | u16 mode = omap_mux_read(m->reg_offset); | 661 | list_for_each_entry_safe(e, tmp, &partition->muxmodes, node) { |
| 662 | struct omap_mux *m = &e->mux; | ||
| 663 | u16 mode = omap_mux_read(partition, m->reg_offset); | ||
| 429 | 664 | ||
| 430 | if (OMAP_MODE_GPIO(mode)) | 665 | if (OMAP_MODE_GPIO(mode)) |
| 431 | continue; | 666 | continue; |
| 432 | 667 | ||
| 433 | #ifndef CONFIG_DEBUG_FS | 668 | #ifndef CONFIG_DEBUG_FS |
| 434 | mutex_lock(&muxmode_mutex); | 669 | mutex_lock(&muxmode_mutex); |
| 435 | list_del(&e->node); | 670 | list_del(&e->node); |
| 436 | mutex_unlock(&muxmode_mutex); | 671 | mutex_unlock(&muxmode_mutex); |
| 437 | omap_mux_free_names(m); | 672 | omap_mux_free_names(m); |
| 438 | kfree(m); | 673 | kfree(m); |
| 439 | #endif | 674 | #endif |
| 440 | 675 | } | |
| 441 | } | 676 | } |
| 442 | 677 | ||
| 443 | omap_mux_dbg_init(); | 678 | omap_mux_dbg_init(); |
| @@ -462,8 +697,8 @@ static void __init omap_mux_package_fixup(struct omap_mux *p, | |||
| 462 | s++; | 697 | s++; |
| 463 | } | 698 | } |
| 464 | if (!found) | 699 | if (!found) |
| 465 | printk(KERN_ERR "mux: Unknown entry offset 0x%x\n", | 700 | pr_err("%s: Unknown entry offset 0x%x\n", __func__, |
| 466 | p->reg_offset); | 701 | p->reg_offset); |
| 467 | p++; | 702 | p++; |
| 468 | } | 703 | } |
| 469 | } | 704 | } |
| @@ -487,8 +722,8 @@ static void __init omap_mux_package_init_balls(struct omap_ball *b, | |||
| 487 | s++; | 722 | s++; |
| 488 | } | 723 | } |
| 489 | if (!found) | 724 | if (!found) |
| 490 | printk(KERN_ERR "mux: Unknown ball offset 0x%x\n", | 725 | pr_err("%s: Unknown ball offset 0x%x\n", __func__, |
| 491 | b->reg_offset); | 726 | b->reg_offset); |
| 492 | b++; | 727 | b++; |
| 493 | } | 728 | } |
| 494 | } | 729 | } |
| @@ -554,7 +789,7 @@ static void __init omap_mux_set_cmdline_signals(void) | |||
| 554 | } | 789 | } |
| 555 | 790 | ||
| 556 | static int __init omap_mux_copy_names(struct omap_mux *src, | 791 | static int __init omap_mux_copy_names(struct omap_mux *src, |
| 557 | struct omap_mux *dst) | 792 | struct omap_mux *dst) |
| 558 | { | 793 | { |
| 559 | int i; | 794 | int i; |
| 560 | 795 | ||
| @@ -592,51 +827,63 @@ free: | |||
| 592 | 827 | ||
| 593 | #endif /* CONFIG_OMAP_MUX */ | 828 | #endif /* CONFIG_OMAP_MUX */ |
| 594 | 829 | ||
| 595 | static u16 omap_mux_get_by_gpio(int gpio) | 830 | static struct omap_mux *omap_mux_get_by_gpio( |
| 831 | struct omap_mux_partition *partition, | ||
| 832 | int gpio) | ||
| 596 | { | 833 | { |
| 597 | struct omap_mux_entry *e; | 834 | struct omap_mux_entry *e; |
| 598 | u16 offset = OMAP_MUX_TERMINATOR; | 835 | struct omap_mux *ret = NULL; |
| 599 | 836 | ||
| 600 | list_for_each_entry(e, &muxmodes, node) { | 837 | list_for_each_entry(e, &partition->muxmodes, node) { |
| 601 | struct omap_mux *m = &e->mux; | 838 | struct omap_mux *m = &e->mux; |
| 602 | if (m->gpio == gpio) { | 839 | if (m->gpio == gpio) { |
| 603 | offset = m->reg_offset; | 840 | ret = m; |
| 604 | break; | 841 | break; |
| 605 | } | 842 | } |
| 606 | } | 843 | } |
| 607 | 844 | ||
| 608 | return offset; | 845 | return ret; |
| 609 | } | 846 | } |
| 610 | 847 | ||
| 611 | /* Needed for dynamic muxing of GPIO pins for off-idle */ | 848 | /* Needed for dynamic muxing of GPIO pins for off-idle */ |
| 612 | u16 omap_mux_get_gpio(int gpio) | 849 | u16 omap_mux_get_gpio(int gpio) |
| 613 | { | 850 | { |
| 614 | u16 offset; | 851 | struct omap_mux_partition *partition; |
| 852 | struct omap_mux *m; | ||
| 615 | 853 | ||
| 616 | offset = omap_mux_get_by_gpio(gpio); | 854 | list_for_each_entry(partition, &mux_partitions, node) { |
| 617 | if (offset == OMAP_MUX_TERMINATOR) { | 855 | m = omap_mux_get_by_gpio(partition, gpio); |
| 618 | printk(KERN_ERR "mux: Could not get gpio%i\n", gpio); | 856 | if (m) |
| 619 | return offset; | 857 | return omap_mux_read(partition, m->reg_offset); |
| 620 | } | 858 | } |
| 621 | 859 | ||
| 622 | return omap_mux_read(offset); | 860 | if (!m || m->reg_offset == OMAP_MUX_TERMINATOR) |
| 861 | pr_err("%s: Could not get gpio%i\n", __func__, gpio); | ||
| 862 | |||
| 863 | return OMAP_MUX_TERMINATOR; | ||
| 623 | } | 864 | } |
| 624 | 865 | ||
| 625 | /* Needed for dynamic muxing of GPIO pins for off-idle */ | 866 | /* Needed for dynamic muxing of GPIO pins for off-idle */ |
| 626 | void omap_mux_set_gpio(u16 val, int gpio) | 867 | void omap_mux_set_gpio(u16 val, int gpio) |
| 627 | { | 868 | { |
| 628 | u16 offset; | 869 | struct omap_mux_partition *partition; |
| 870 | struct omap_mux *m = NULL; | ||
| 629 | 871 | ||
| 630 | offset = omap_mux_get_by_gpio(gpio); | 872 | list_for_each_entry(partition, &mux_partitions, node) { |
| 631 | if (offset == OMAP_MUX_TERMINATOR) { | 873 | m = omap_mux_get_by_gpio(partition, gpio); |
| 632 | printk(KERN_ERR "mux: Could not set gpio%i\n", gpio); | 874 | if (m) { |
| 633 | return; | 875 | omap_mux_write(partition, val, m->reg_offset); |
| 876 | return; | ||
| 877 | } | ||
| 634 | } | 878 | } |
| 635 | 879 | ||
| 636 | omap_mux_write(val, offset); | 880 | if (!m || m->reg_offset == OMAP_MUX_TERMINATOR) |
| 881 | pr_err("%s: Could not set gpio%i\n", __func__, gpio); | ||
| 637 | } | 882 | } |
| 638 | 883 | ||
| 639 | static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src) | 884 | static struct omap_mux * __init omap_mux_list_add( |
| 885 | struct omap_mux_partition *partition, | ||
| 886 | struct omap_mux *src) | ||
| 640 | { | 887 | { |
| 641 | struct omap_mux_entry *entry; | 888 | struct omap_mux_entry *entry; |
| 642 | struct omap_mux *m; | 889 | struct omap_mux *m; |
| @@ -656,7 +903,7 @@ static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src) | |||
| 656 | #endif | 903 | #endif |
| 657 | 904 | ||
| 658 | mutex_lock(&muxmode_mutex); | 905 | mutex_lock(&muxmode_mutex); |
| 659 | list_add_tail(&entry->node, &muxmodes); | 906 | list_add_tail(&entry->node, &partition->muxmodes); |
| 660 | mutex_unlock(&muxmode_mutex); | 907 | mutex_unlock(&muxmode_mutex); |
| 661 | 908 | ||
| 662 | return m; | 909 | return m; |
| @@ -667,7 +914,8 @@ static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src) | |||
| 667 | * the GPIO to mux offset mapping that is needed for dynamic muxing | 914 | * the GPIO to mux offset mapping that is needed for dynamic muxing |
| 668 | * of GPIO pins for off-idle. | 915 | * of GPIO pins for off-idle. |
| 669 | */ | 916 | */ |
| 670 | static void __init omap_mux_init_list(struct omap_mux *superset) | 917 | static void __init omap_mux_init_list(struct omap_mux_partition *partition, |
| 918 | struct omap_mux *superset) | ||
| 671 | { | 919 | { |
| 672 | while (superset->reg_offset != OMAP_MUX_TERMINATOR) { | 920 | while (superset->reg_offset != OMAP_MUX_TERMINATOR) { |
| 673 | struct omap_mux *entry; | 921 | struct omap_mux *entry; |
| @@ -679,15 +927,16 @@ static void __init omap_mux_init_list(struct omap_mux *superset) | |||
| 679 | } | 927 | } |
| 680 | #else | 928 | #else |
| 681 | /* Skip pins that are not muxed as GPIO by bootloader */ | 929 | /* Skip pins that are not muxed as GPIO by bootloader */ |
| 682 | if (!OMAP_MODE_GPIO(omap_mux_read(superset->reg_offset))) { | 930 | if (!OMAP_MODE_GPIO(omap_mux_read(partition, |
| 931 | superset->reg_offset))) { | ||
| 683 | superset++; | 932 | superset++; |
| 684 | continue; | 933 | continue; |
| 685 | } | 934 | } |
| 686 | #endif | 935 | #endif |
| 687 | 936 | ||
| 688 | entry = omap_mux_list_add(superset); | 937 | entry = omap_mux_list_add(partition, superset); |
| 689 | if (!entry) { | 938 | if (!entry) { |
| 690 | printk(KERN_ERR "mux: Could not add entry\n"); | 939 | pr_err("%s: Could not add entry\n", __func__); |
| 691 | return; | 940 | return; |
| 692 | } | 941 | } |
| 693 | superset++; | 942 | superset++; |
| @@ -706,10 +955,11 @@ static void omap_mux_init_package(struct omap_mux *superset, | |||
| 706 | omap_mux_package_init_balls(package_balls, superset); | 955 | omap_mux_package_init_balls(package_balls, superset); |
| 707 | } | 956 | } |
| 708 | 957 | ||
| 709 | static void omap_mux_init_signals(struct omap_board_mux *board_mux) | 958 | static void omap_mux_init_signals(struct omap_mux_partition *partition, |
| 959 | struct omap_board_mux *board_mux) | ||
| 710 | { | 960 | { |
| 711 | omap_mux_set_cmdline_signals(); | 961 | omap_mux_set_cmdline_signals(); |
| 712 | omap_mux_write_array(board_mux); | 962 | omap_mux_write_array(partition, board_mux); |
| 713 | } | 963 | } |
| 714 | 964 | ||
| 715 | #else | 965 | #else |
| @@ -720,34 +970,49 @@ static void omap_mux_init_package(struct omap_mux *superset, | |||
| 720 | { | 970 | { |
| 721 | } | 971 | } |
| 722 | 972 | ||
| 723 | static void omap_mux_init_signals(struct omap_board_mux *board_mux) | 973 | static void omap_mux_init_signals(struct omap_mux_partition *partition, |
| 974 | struct omap_board_mux *board_mux) | ||
| 724 | { | 975 | { |
| 725 | } | 976 | } |
| 726 | 977 | ||
| 727 | #endif | 978 | #endif |
| 728 | 979 | ||
| 729 | int __init omap_mux_init(u32 mux_pbase, u32 mux_size, | 980 | static u32 mux_partitions_cnt; |
| 730 | struct omap_mux *superset, | ||
| 731 | struct omap_mux *package_subset, | ||
| 732 | struct omap_board_mux *board_mux, | ||
| 733 | struct omap_ball *package_balls) | ||
| 734 | { | ||
| 735 | if (mux_base) | ||
| 736 | return -EBUSY; | ||
| 737 | 981 | ||
| 738 | mux_phys = mux_pbase; | 982 | int __init omap_mux_init(const char *name, u32 flags, |
| 739 | mux_base = ioremap(mux_pbase, mux_size); | 983 | u32 mux_pbase, u32 mux_size, |
| 740 | if (!mux_base) { | 984 | struct omap_mux *superset, |
| 741 | printk(KERN_ERR "mux: Could not ioremap\n"); | 985 | struct omap_mux *package_subset, |
| 986 | struct omap_board_mux *board_mux, | ||
| 987 | struct omap_ball *package_balls) | ||
| 988 | { | ||
| 989 | struct omap_mux_partition *partition; | ||
| 990 | |||
| 991 | partition = kzalloc(sizeof(struct omap_mux_partition), GFP_KERNEL); | ||
| 992 | if (!partition) | ||
| 993 | return -ENOMEM; | ||
| 994 | |||
| 995 | partition->name = name; | ||
| 996 | partition->flags = flags; | ||
| 997 | partition->size = mux_size; | ||
| 998 | partition->phys = mux_pbase; | ||
| 999 | partition->base = ioremap(mux_pbase, mux_size); | ||
| 1000 | if (!partition->base) { | ||
| 1001 | pr_err("%s: Could not ioremap mux partition at 0x%08x\n", | ||
| 1002 | __func__, partition->phys); | ||
| 742 | return -ENODEV; | 1003 | return -ENODEV; |
| 743 | } | 1004 | } |
| 744 | 1005 | ||
| 745 | if (cpu_is_omap24xx()) | 1006 | INIT_LIST_HEAD(&partition->muxmodes); |
| 746 | omap_mux_flags = MUXABLE_GPIO_MODE3; | 1007 | |
| 1008 | list_add_tail(&partition->node, &mux_partitions); | ||
| 1009 | mux_partitions_cnt++; | ||
| 1010 | pr_info("%s: Add partition: #%d: %s, flags: %x\n", __func__, | ||
| 1011 | mux_partitions_cnt, partition->name, partition->flags); | ||
| 747 | 1012 | ||
| 748 | omap_mux_init_package(superset, package_subset, package_balls); | 1013 | omap_mux_init_package(superset, package_subset, package_balls); |
| 749 | omap_mux_init_list(superset); | 1014 | omap_mux_init_list(partition, superset); |
| 750 | omap_mux_init_signals(board_mux); | 1015 | omap_mux_init_signals(partition, board_mux); |
| 751 | 1016 | ||
| 752 | return 0; | 1017 | return 0; |
| 753 | } | 1018 | } |
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h index 350c04f27383..a4ab17a737a6 100644 --- a/arch/arm/mach-omap2/mux.h +++ b/arch/arm/mach-omap2/mux.h | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) 2009 Nokia | 2 | * Copyright (C) 2009 Nokia |
| 3 | * Copyright (C) 2009 Texas Instruments | 3 | * Copyright (C) 2009-2010 Texas Instruments |
| 4 | * | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify | 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as | 6 | * it under the terms of the GNU General Public License version 2 as |
| @@ -10,6 +10,7 @@ | |||
| 10 | #include "mux2420.h" | 10 | #include "mux2420.h" |
| 11 | #include "mux2430.h" | 11 | #include "mux2430.h" |
| 12 | #include "mux34xx.h" | 12 | #include "mux34xx.h" |
| 13 | #include "mux44xx.h" | ||
| 13 | 14 | ||
| 14 | #define OMAP_MUX_TERMINATOR 0xffff | 15 | #define OMAP_MUX_TERMINATOR 0xffff |
| 15 | 16 | ||
| @@ -37,6 +38,9 @@ | |||
| 37 | #define OMAP_OFF_PULL_UP (1 << 13) | 38 | #define OMAP_OFF_PULL_UP (1 << 13) |
| 38 | #define OMAP_WAKEUP_EN (1 << 14) | 39 | #define OMAP_WAKEUP_EN (1 << 14) |
| 39 | 40 | ||
| 41 | /* 44xx specific mux bit defines */ | ||
| 42 | #define OMAP_WAKEUP_EVENT (1 << 15) | ||
| 43 | |||
| 40 | /* Active pin states */ | 44 | /* Active pin states */ |
| 41 | #define OMAP_PIN_OUTPUT 0 | 45 | #define OMAP_PIN_OUTPUT 0 |
| 42 | #define OMAP_PIN_INPUT OMAP_INPUT_EN | 46 | #define OMAP_PIN_INPUT OMAP_INPUT_EN |
| @@ -56,8 +60,10 @@ | |||
| 56 | 60 | ||
| 57 | #define OMAP_MODE_GPIO(x) (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE4) | 61 | #define OMAP_MODE_GPIO(x) (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE4) |
| 58 | 62 | ||
| 59 | /* Flags for omap_mux_init */ | 63 | /* Flags for omapX_mux_init */ |
| 60 | #define OMAP_PACKAGE_MASK 0xffff | 64 | #define OMAP_PACKAGE_MASK 0xffff |
| 65 | #define OMAP_PACKAGE_CBS 8 /* 547-pin 0.40 0.40 */ | ||
| 66 | #define OMAP_PACKAGE_CBL 7 /* 547-pin 0.40 0.40 */ | ||
| 61 | #define OMAP_PACKAGE_CBP 6 /* 515-pin 0.40 0.50 */ | 67 | #define OMAP_PACKAGE_CBP 6 /* 515-pin 0.40 0.50 */ |
| 62 | #define OMAP_PACKAGE_CUS 5 /* 423-pin 0.65 */ | 68 | #define OMAP_PACKAGE_CUS 5 /* 423-pin 0.65 */ |
| 63 | #define OMAP_PACKAGE_CBB 4 /* 515-pin 0.40 0.50 */ | 69 | #define OMAP_PACKAGE_CBB 4 /* 515-pin 0.40 0.50 */ |
| @@ -66,14 +72,61 @@ | |||
| 66 | #define OMAP_PACKAGE_ZAF 1 /* 2420 447-pin SIP */ | 72 | #define OMAP_PACKAGE_ZAF 1 /* 2420 447-pin SIP */ |
| 67 | 73 | ||
| 68 | 74 | ||
| 69 | #define OMAP_MUX_NR_MODES 8 /* Available modes */ | 75 | #define OMAP_MUX_NR_MODES 8 /* Available modes */ |
| 70 | #define OMAP_MUX_NR_SIDES 2 /* Bottom & top */ | 76 | #define OMAP_MUX_NR_SIDES 2 /* Bottom & top */ |
| 77 | |||
| 78 | /* | ||
| 79 | * omap_mux_init flags definition: | ||
| 80 | * | ||
| 81 | * OMAP_MUX_REG_8BIT: Ensure that access to padconf is done in 8 bits. | ||
| 82 | * The default value is 16 bits. | ||
| 83 | * OMAP_MUX_GPIO_IN_MODE3: The GPIO is selected in mode3. | ||
| 84 | * The default is mode4. | ||
| 85 | */ | ||
| 86 | #define OMAP_MUX_REG_8BIT (1 << 0) | ||
| 87 | #define OMAP_MUX_GPIO_IN_MODE3 (1 << 1) | ||
| 88 | |||
| 89 | /** | ||
| 90 | * struct omap_board_data - board specific device data | ||
| 91 | * @id: instance id | ||
| 92 | * @flags: additional flags for platform init code | ||
| 93 | * @pads: array of device specific pads | ||
| 94 | * @pads_cnt: ARRAY_SIZE() of pads | ||
| 95 | */ | ||
| 96 | struct omap_board_data { | ||
| 97 | int id; | ||
| 98 | u32 flags; | ||
| 99 | struct omap_device_pad *pads; | ||
| 100 | int pads_cnt; | ||
| 101 | }; | ||
| 102 | |||
| 103 | /** | ||
| 104 | * struct mux_partition - contain partition related information | ||
| 105 | * @name: name of the current partition | ||
| 106 | * @flags: flags specific to this partition | ||
| 107 | * @phys: physical address | ||
| 108 | * @size: partition size | ||
| 109 | * @base: virtual address after ioremap | ||
| 110 | * @muxmodes: list of nodes that belong to a partition | ||
| 111 | * @node: list node for the partitions linked list | ||
| 112 | */ | ||
| 113 | struct omap_mux_partition { | ||
| 114 | const char *name; | ||
| 115 | u32 flags; | ||
| 116 | u32 phys; | ||
| 117 | u32 size; | ||
| 118 | void __iomem *base; | ||
| 119 | struct list_head muxmodes; | ||
| 120 | struct list_head node; | ||
| 121 | }; | ||
| 71 | 122 | ||
| 72 | /** | 123 | /** |
| 73 | * struct omap_mux - data for omap mux register offset and it's value | 124 | * struct omap_mux - data for omap mux register offset and it's value |
| 74 | * @reg_offset: mux register offset from the mux base | 125 | * @reg_offset: mux register offset from the mux base |
| 75 | * @gpio: GPIO number | 126 | * @gpio: GPIO number |
| 76 | * @muxnames: available signal modes for a ball | 127 | * @muxnames: available signal modes for a ball |
| 128 | * @balls: available balls on the package | ||
| 129 | * @partition: mux partition | ||
| 77 | */ | 130 | */ |
| 78 | struct omap_mux { | 131 | struct omap_mux { |
| 79 | u16 reg_offset; | 132 | u16 reg_offset; |
| @@ -106,6 +159,34 @@ struct omap_board_mux { | |||
| 106 | u16 value; | 159 | u16 value; |
| 107 | }; | 160 | }; |
| 108 | 161 | ||
| 162 | #define OMAP_DEVICE_PAD_ENABLED BIT(7) /* Not needed for board-*.c */ | ||
| 163 | #define OMAP_DEVICE_PAD_REMUX BIT(1) /* Dynamically remux a pad, | ||
| 164 | needs enable, idle and off | ||
| 165 | values */ | ||
| 166 | #define OMAP_DEVICE_PAD_WAKEUP BIT(0) /* Pad is wake-up capable */ | ||
| 167 | |||
| 168 | /** | ||
| 169 | * struct omap_device_pad - device specific pad configuration | ||
| 170 | * @name: signal name | ||
| 171 | * @flags: pad specific runtime flags | ||
| 172 | * @enable: runtime value for a pad | ||
| 173 | * @idle: idle value for a pad | ||
| 174 | * @off: off value for a pad, defaults to safe mode | ||
| 175 | * @partition: mux partition | ||
| 176 | * @mux: mux register | ||
| 177 | */ | ||
| 178 | struct omap_device_pad { | ||
| 179 | char *name; | ||
| 180 | u8 flags; | ||
| 181 | u16 enable; | ||
| 182 | u16 idle; | ||
| 183 | u16 off; | ||
| 184 | struct omap_mux_partition *partition; | ||
| 185 | struct omap_mux *mux; | ||
| 186 | }; | ||
| 187 | |||
| 188 | struct omap_hwmod_mux_info; | ||
| 189 | |||
| 109 | #if defined(CONFIG_OMAP_MUX) | 190 | #if defined(CONFIG_OMAP_MUX) |
| 110 | 191 | ||
| 111 | /** | 192 | /** |
| @@ -122,6 +203,23 @@ int omap_mux_init_gpio(int gpio, int val); | |||
| 122 | */ | 203 | */ |
| 123 | int omap_mux_init_signal(const char *muxname, int val); | 204 | int omap_mux_init_signal(const char *muxname, int val); |
| 124 | 205 | ||
| 206 | /** | ||
| 207 | * omap_hwmod_mux_init - initialize hwmod specific mux data | ||
| 208 | * @bpads: Board specific device signal names | ||
| 209 | * @nr_pads: Number of signal names for the device | ||
| 210 | */ | ||
| 211 | extern struct omap_hwmod_mux_info * | ||
| 212 | omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads); | ||
| 213 | |||
| 214 | /** | ||
| 215 | * omap_hwmod_mux - omap hwmod specific pin muxing | ||
| 216 | * @hmux: Pads for a hwmod | ||
| 217 | * @state: Desired _HWMOD_STATE | ||
| 218 | * | ||
| 219 | * Called only from omap_hwmod.c, do not use. | ||
| 220 | */ | ||
| 221 | void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state); | ||
| 222 | |||
| 125 | #else | 223 | #else |
| 126 | 224 | ||
| 127 | static inline int omap_mux_init_gpio(int gpio, int val) | 225 | static inline int omap_mux_init_gpio(int gpio, int val) |
| @@ -133,6 +231,18 @@ static inline int omap_mux_init_signal(char *muxname, int val) | |||
| 133 | return 0; | 231 | return 0; |
| 134 | } | 232 | } |
| 135 | 233 | ||
| 234 | static inline struct omap_hwmod_mux_info * | ||
| 235 | omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads) | ||
| 236 | { | ||
| 237 | return NULL; | ||
| 238 | } | ||
| 239 | |||
| 240 | static inline void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state) | ||
| 241 | { | ||
| 242 | } | ||
| 243 | |||
| 244 | static struct omap_board_mux *board_mux __initdata __maybe_unused; | ||
| 245 | |||
| 136 | #endif | 246 | #endif |
| 137 | 247 | ||
| 138 | /** | 248 | /** |
| @@ -151,28 +261,39 @@ u16 omap_mux_get_gpio(int gpio); | |||
| 151 | void omap_mux_set_gpio(u16 val, int gpio); | 261 | void omap_mux_set_gpio(u16 val, int gpio); |
| 152 | 262 | ||
| 153 | /** | 263 | /** |
| 264 | * omap_mux_get() - get a mux partition by name | ||
| 265 | * @name: Name of the mux partition | ||
| 266 | * | ||
| 267 | */ | ||
| 268 | struct omap_mux_partition *omap_mux_get(const char *name); | ||
| 269 | |||
| 270 | /** | ||
| 154 | * omap_mux_read() - read mux register | 271 | * omap_mux_read() - read mux register |
| 272 | * @partition: Mux partition | ||
| 155 | * @mux_offset: Offset of the mux register | 273 | * @mux_offset: Offset of the mux register |
| 156 | * | 274 | * |
| 157 | */ | 275 | */ |
| 158 | u16 omap_mux_read(u16 mux_offset); | 276 | u16 omap_mux_read(struct omap_mux_partition *p, u16 mux_offset); |
| 159 | 277 | ||
| 160 | /** | 278 | /** |
| 161 | * omap_mux_write() - write mux register | 279 | * omap_mux_write() - write mux register |
| 280 | * @partition: Mux partition | ||
| 162 | * @val: New mux register value | 281 | * @val: New mux register value |
| 163 | * @mux_offset: Offset of the mux register | 282 | * @mux_offset: Offset of the mux register |
| 164 | * | 283 | * |
| 165 | * This should be only needed for dynamic remuxing of non-gpio signals. | 284 | * This should be only needed for dynamic remuxing of non-gpio signals. |
| 166 | */ | 285 | */ |
| 167 | void omap_mux_write(u16 val, u16 mux_offset); | 286 | void omap_mux_write(struct omap_mux_partition *p, u16 val, u16 mux_offset); |
| 168 | 287 | ||
| 169 | /** | 288 | /** |
| 170 | * omap_mux_write_array() - write an array of mux registers | 289 | * omap_mux_write_array() - write an array of mux registers |
| 290 | * @partition: Mux partition | ||
| 171 | * @board_mux: Array of mux registers terminated by MAP_MUX_TERMINATOR | 291 | * @board_mux: Array of mux registers terminated by MAP_MUX_TERMINATOR |
| 172 | * | 292 | * |
| 173 | * This should be only needed for dynamic remuxing of non-gpio signals. | 293 | * This should be only needed for dynamic remuxing of non-gpio signals. |
| 174 | */ | 294 | */ |
| 175 | void omap_mux_write_array(struct omap_board_mux *board_mux); | 295 | void omap_mux_write_array(struct omap_mux_partition *p, |
| 296 | struct omap_board_mux *board_mux); | ||
| 176 | 297 | ||
| 177 | /** | 298 | /** |
| 178 | * omap2420_mux_init() - initialize mux system with board specific set | 299 | * omap2420_mux_init() - initialize mux system with board specific set |
| @@ -196,10 +317,19 @@ int omap2430_mux_init(struct omap_board_mux *board_mux, int flags); | |||
| 196 | int omap3_mux_init(struct omap_board_mux *board_mux, int flags); | 317 | int omap3_mux_init(struct omap_board_mux *board_mux, int flags); |
| 197 | 318 | ||
| 198 | /** | 319 | /** |
| 320 | * omap4_mux_init() - initialize mux system with board specific set | ||
| 321 | * @board_mux: Board specific mux table | ||
| 322 | * @flags: OMAP package type used for the board | ||
| 323 | */ | ||
| 324 | int omap4_mux_init(struct omap_board_mux *board_mux, int flags); | ||
| 325 | |||
| 326 | /** | ||
| 199 | * omap_mux_init - private mux init function, do not call | 327 | * omap_mux_init - private mux init function, do not call |
| 200 | */ | 328 | */ |
| 201 | int omap_mux_init(u32 mux_pbase, u32 mux_size, | 329 | int omap_mux_init(const char *name, u32 flags, |
| 202 | struct omap_mux *superset, | 330 | u32 mux_pbase, u32 mux_size, |
| 203 | struct omap_mux *package_subset, | 331 | struct omap_mux *superset, |
| 204 | struct omap_board_mux *board_mux, | 332 | struct omap_mux *package_subset, |
| 205 | struct omap_ball *package_balls); | 333 | struct omap_board_mux *board_mux, |
| 334 | struct omap_ball *package_balls); | ||
| 335 | |||
diff --git a/arch/arm/mach-omap2/mux2420.c b/arch/arm/mach-omap2/mux2420.c index 414af5434456..cf6de0971c6c 100644 --- a/arch/arm/mach-omap2/mux2420.c +++ b/arch/arm/mach-omap2/mux2420.c | |||
| @@ -678,11 +678,13 @@ int __init omap2420_mux_init(struct omap_board_mux *board_subset, int flags) | |||
| 678 | case OMAP_PACKAGE_ZAF: | 678 | case OMAP_PACKAGE_ZAF: |
| 679 | /* REVISIT: Please add data */ | 679 | /* REVISIT: Please add data */ |
| 680 | default: | 680 | default: |
| 681 | pr_warning("mux: No ball data available for omap2420 package\n"); | 681 | pr_warning("%s: No ball data available for omap2420 package\n", |
| 682 | __func__); | ||
| 682 | } | 683 | } |
| 683 | 684 | ||
| 684 | return omap_mux_init(OMAP2420_CONTROL_PADCONF_MUX_PBASE, | 685 | return omap_mux_init("core", OMAP_MUX_REG_8BIT | OMAP_MUX_GPIO_IN_MODE3, |
| 686 | OMAP2420_CONTROL_PADCONF_MUX_PBASE, | ||
| 685 | OMAP2420_CONTROL_PADCONF_MUX_SIZE, | 687 | OMAP2420_CONTROL_PADCONF_MUX_SIZE, |
| 686 | omap2420_muxmodes, NULL, board_subset, | 688 | omap2420_muxmodes, NULL, board_subset, |
| 687 | package_balls); | 689 | package_balls); |
| 688 | } | 690 | } |
diff --git a/arch/arm/mach-omap2/mux2430.c b/arch/arm/mach-omap2/mux2430.c index 84d2c5a7ecd7..4185f92553db 100644 --- a/arch/arm/mach-omap2/mux2430.c +++ b/arch/arm/mach-omap2/mux2430.c | |||
| @@ -781,11 +781,13 @@ int __init omap2430_mux_init(struct omap_board_mux *board_subset, int flags) | |||
| 781 | package_balls = omap2430_pop_ball; | 781 | package_balls = omap2430_pop_ball; |
| 782 | break; | 782 | break; |
| 783 | default: | 783 | default: |
| 784 | pr_warning("mux: No ball data available for omap2420 package\n"); | 784 | pr_warning("%s: No ball data available for omap2420 package\n", |
| 785 | __func__); | ||
| 785 | } | 786 | } |
| 786 | 787 | ||
| 787 | return omap_mux_init(OMAP2430_CONTROL_PADCONF_MUX_PBASE, | 788 | return omap_mux_init("core", OMAP_MUX_REG_8BIT | OMAP_MUX_GPIO_IN_MODE3, |
| 789 | OMAP2430_CONTROL_PADCONF_MUX_PBASE, | ||
| 788 | OMAP2430_CONTROL_PADCONF_MUX_SIZE, | 790 | OMAP2430_CONTROL_PADCONF_MUX_SIZE, |
| 789 | omap2430_muxmodes, NULL, board_subset, | 791 | omap2430_muxmodes, NULL, board_subset, |
| 790 | package_balls); | 792 | package_balls); |
| 791 | } | 793 | } |
diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c index 574e54ea3ab7..440c98e9a510 100644 --- a/arch/arm/mach-omap2/mux34xx.c +++ b/arch/arm/mach-omap2/mux34xx.c | |||
| @@ -2049,12 +2049,13 @@ int __init omap3_mux_init(struct omap_board_mux *board_subset, int flags) | |||
| 2049 | package_balls = omap36xx_cbp_ball; | 2049 | package_balls = omap36xx_cbp_ball; |
| 2050 | break; | 2050 | break; |
| 2051 | default: | 2051 | default: |
| 2052 | printk(KERN_ERR "mux: Unknown omap package, mux disabled\n"); | 2052 | pr_err("%s Unknown omap package, mux disabled\n", __func__); |
| 2053 | return -EINVAL; | 2053 | return -EINVAL; |
| 2054 | } | 2054 | } |
| 2055 | 2055 | ||
| 2056 | return omap_mux_init(OMAP3_CONTROL_PADCONF_MUX_PBASE, | 2056 | return omap_mux_init("core", 0, |
| 2057 | OMAP3_CONTROL_PADCONF_MUX_PBASE, | ||
| 2057 | OMAP3_CONTROL_PADCONF_MUX_SIZE, | 2058 | OMAP3_CONTROL_PADCONF_MUX_SIZE, |
| 2058 | omap3_muxmodes, package_subset, board_subset, | 2059 | omap3_muxmodes, package_subset, board_subset, |
| 2059 | package_balls); | 2060 | package_balls); |
| 2060 | } | 2061 | } |
diff --git a/arch/arm/mach-omap2/mux44xx.c b/arch/arm/mach-omap2/mux44xx.c new file mode 100644 index 000000000000..980f11d45c79 --- /dev/null +++ b/arch/arm/mach-omap2/mux44xx.c | |||
| @@ -0,0 +1,1625 @@ | |||
| 1 | /* | ||
| 2 | * OMAP44xx ES1.0 pin mux definition | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Texas Instruments, Inc. | ||
| 5 | * | ||
| 6 | * Benoit Cousson (b-cousson@ti.com) | ||
| 7 | * | ||
| 8 | * - Based on mux34xx.c done by Tony Lindgren <tony@atomide.com> | ||
| 9 | * | ||
| 10 | * This file is automatically generated from the OMAP hardware databases. | ||
| 11 | * We respectfully ask that any modifications to this file be coordinated | ||
| 12 | * with the public linux-omap@vger.kernel.org mailing list and the | ||
| 13 | * authors above to ensure that the autogeneration scripts are kept | ||
| 14 | * up-to-date with the file contents. | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or modify | ||
| 17 | * it under the terms of the GNU General Public License version 2 as | ||
| 18 | * published by the Free Software Foundation. | ||
| 19 | */ | ||
| 20 | #include <linux/module.h> | ||
| 21 | #include <linux/init.h> | ||
| 22 | |||
| 23 | #include "mux.h" | ||
| 24 | |||
| 25 | #ifdef CONFIG_OMAP_MUX | ||
| 26 | |||
| 27 | #define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ | ||
| 28 | { \ | ||
| 29 | .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \ | ||
| 30 | .gpio = (g), \ | ||
| 31 | .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \ | ||
| 32 | } | ||
| 33 | |||
| 34 | #else | ||
| 35 | |||
| 36 | #define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ | ||
| 37 | { \ | ||
| 38 | .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \ | ||
| 39 | .gpio = (g), \ | ||
| 40 | } | ||
| 41 | |||
| 42 | #endif | ||
| 43 | |||
| 44 | #define _OMAP4_BALLENTRY(M0, bb, bt) \ | ||
| 45 | { \ | ||
| 46 | .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \ | ||
| 47 | .balls = { bb, bt }, \ | ||
| 48 | } | ||
| 49 | |||
| 50 | /* | ||
| 51 | * Superset of all mux modes for omap4 ES1.0 | ||
| 52 | */ | ||
| 53 | static struct omap_mux __initdata omap4_core_muxmodes[] = { | ||
| 54 | _OMAP4_MUXENTRY(GPMC_AD0, 0, "gpmc_ad0", "sdmmc2_dat0", NULL, NULL, | ||
| 55 | NULL, NULL, NULL, NULL), | ||
| 56 | _OMAP4_MUXENTRY(GPMC_AD1, 0, "gpmc_ad1", "sdmmc2_dat1", NULL, NULL, | ||
| 57 | NULL, NULL, NULL, NULL), | ||
| 58 | _OMAP4_MUXENTRY(GPMC_AD2, 0, "gpmc_ad2", "sdmmc2_dat2", NULL, NULL, | ||
| 59 | NULL, NULL, NULL, NULL), | ||
| 60 | _OMAP4_MUXENTRY(GPMC_AD3, 0, "gpmc_ad3", "sdmmc2_dat3", NULL, NULL, | ||
| 61 | NULL, NULL, NULL, NULL), | ||
| 62 | _OMAP4_MUXENTRY(GPMC_AD4, 0, "gpmc_ad4", "sdmmc2_dat4", | ||
| 63 | "sdmmc2_dir_dat0", NULL, NULL, NULL, NULL, NULL), | ||
| 64 | _OMAP4_MUXENTRY(GPMC_AD5, 0, "gpmc_ad5", "sdmmc2_dat5", | ||
| 65 | "sdmmc2_dir_dat1", NULL, NULL, NULL, NULL, NULL), | ||
| 66 | _OMAP4_MUXENTRY(GPMC_AD6, 0, "gpmc_ad6", "sdmmc2_dat6", | ||
| 67 | "sdmmc2_dir_cmd", NULL, NULL, NULL, NULL, NULL), | ||
| 68 | _OMAP4_MUXENTRY(GPMC_AD7, 0, "gpmc_ad7", "sdmmc2_dat7", | ||
| 69 | "sdmmc2_clk_fdbk", NULL, NULL, NULL, NULL, NULL), | ||
| 70 | _OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15", | ||
| 71 | "gpio_32", NULL, NULL, NULL, NULL), | ||
| 72 | _OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14", | ||
| 73 | "gpio_33", NULL, NULL, NULL, NULL), | ||
| 74 | _OMAP4_MUXENTRY(GPMC_AD10, 34, "gpmc_ad10", "kpd_row2", "c2c_data13", | ||
| 75 | "gpio_34", NULL, NULL, NULL, NULL), | ||
| 76 | _OMAP4_MUXENTRY(GPMC_AD11, 35, "gpmc_ad11", "kpd_row3", "c2c_data12", | ||
| 77 | "gpio_35", NULL, NULL, NULL, NULL), | ||
| 78 | _OMAP4_MUXENTRY(GPMC_AD12, 36, "gpmc_ad12", "kpd_col0", "c2c_data11", | ||
| 79 | "gpio_36", NULL, NULL, NULL, NULL), | ||
| 80 | _OMAP4_MUXENTRY(GPMC_AD13, 37, "gpmc_ad13", "kpd_col1", "c2c_data10", | ||
| 81 | "gpio_37", NULL, NULL, NULL, NULL), | ||
| 82 | _OMAP4_MUXENTRY(GPMC_AD14, 38, "gpmc_ad14", "kpd_col2", "c2c_data9", | ||
| 83 | "gpio_38", NULL, NULL, NULL, NULL), | ||
| 84 | _OMAP4_MUXENTRY(GPMC_AD15, 39, "gpmc_ad15", "kpd_col3", "c2c_data8", | ||
| 85 | "gpio_39", NULL, NULL, NULL, NULL), | ||
| 86 | _OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0", | ||
| 87 | "gpio_40", "venc_656_data0", NULL, NULL, NULL), | ||
| 88 | _OMAP4_MUXENTRY(GPMC_A17, 41, "gpmc_a17", "kpd_row5", "c2c_datain1", | ||
| 89 | "gpio_41", "venc_656_data1", NULL, NULL, "safe_mode"), | ||
| 90 | _OMAP4_MUXENTRY(GPMC_A18, 42, "gpmc_a18", "kpd_row6", "c2c_datain2", | ||
| 91 | "gpio_42", "venc_656_data2", NULL, NULL, "safe_mode"), | ||
| 92 | _OMAP4_MUXENTRY(GPMC_A19, 43, "gpmc_a19", "kpd_row7", "c2c_datain3", | ||
| 93 | "gpio_43", "venc_656_data3", NULL, NULL, "safe_mode"), | ||
| 94 | _OMAP4_MUXENTRY(GPMC_A20, 44, "gpmc_a20", "kpd_col4", "c2c_datain4", | ||
| 95 | "gpio_44", "venc_656_data4", NULL, NULL, "safe_mode"), | ||
| 96 | _OMAP4_MUXENTRY(GPMC_A21, 45, "gpmc_a21", "kpd_col5", "c2c_datain5", | ||
| 97 | "gpio_45", "venc_656_data5", NULL, NULL, "safe_mode"), | ||
| 98 | _OMAP4_MUXENTRY(GPMC_A22, 46, "gpmc_a22", "kpd_col6", "c2c_datain6", | ||
| 99 | "gpio_46", "venc_656_data6", NULL, NULL, "safe_mode"), | ||
| 100 | _OMAP4_MUXENTRY(GPMC_A23, 47, "gpmc_a23", "kpd_col7", "c2c_datain7", | ||
| 101 | "gpio_47", "venc_656_data7", NULL, NULL, "safe_mode"), | ||
| 102 | _OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", NULL, "c2c_clkout0", | ||
| 103 | "gpio_48", NULL, NULL, NULL, "safe_mode"), | ||
| 104 | _OMAP4_MUXENTRY(GPMC_A25, 49, "gpmc_a25", NULL, "c2c_clkout1", | ||
| 105 | "gpio_49", NULL, NULL, NULL, "safe_mode"), | ||
| 106 | _OMAP4_MUXENTRY(GPMC_NCS0, 50, "gpmc_ncs0", NULL, NULL, "gpio_50", | ||
| 107 | "sys_ndmareq0", NULL, NULL, NULL), | ||
| 108 | _OMAP4_MUXENTRY(GPMC_NCS1, 51, "gpmc_ncs1", NULL, "c2c_dataout6", | ||
| 109 | "gpio_51", NULL, NULL, NULL, "safe_mode"), | ||
| 110 | _OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", NULL, "c2c_dataout7", | ||
| 111 | "gpio_52", NULL, NULL, NULL, "safe_mode"), | ||
| 112 | _OMAP4_MUXENTRY(GPMC_NCS3, 53, "gpmc_ncs3", "gpmc_dir", | ||
| 113 | "c2c_dataout4", "gpio_53", NULL, NULL, NULL, | ||
| 114 | "safe_mode"), | ||
| 115 | _OMAP4_MUXENTRY(GPMC_NWP, 54, "gpmc_nwp", "dsi1_te0", NULL, "gpio_54", | ||
| 116 | "sys_ndmareq1", NULL, NULL, NULL), | ||
| 117 | _OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55", | ||
| 118 | "sys_ndmareq2", NULL, NULL, NULL), | ||
| 119 | _OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL, | ||
| 120 | "gpio_56", "sys_ndmareq3", NULL, NULL, NULL), | ||
| 121 | _OMAP4_MUXENTRY(GPMC_NOE, 0, "gpmc_noe", "sdmmc2_clk", NULL, NULL, | ||
| 122 | NULL, NULL, NULL, NULL), | ||
| 123 | _OMAP4_MUXENTRY(GPMC_NWE, 0, "gpmc_nwe", "sdmmc2_cmd", NULL, NULL, | ||
| 124 | NULL, NULL, NULL, NULL), | ||
| 125 | _OMAP4_MUXENTRY(GPMC_NBE0_CLE, 59, "gpmc_nbe0_cle", "dsi2_te0", NULL, | ||
| 126 | "gpio_59", NULL, NULL, NULL, NULL), | ||
| 127 | _OMAP4_MUXENTRY(GPMC_NBE1, 60, "gpmc_nbe1", NULL, "c2c_dataout5", | ||
| 128 | "gpio_60", NULL, NULL, NULL, "safe_mode"), | ||
| 129 | _OMAP4_MUXENTRY(GPMC_WAIT0, 61, "gpmc_wait0", "dsi2_te1", NULL, | ||
| 130 | "gpio_61", NULL, NULL, NULL, NULL), | ||
| 131 | _OMAP4_MUXENTRY(GPMC_WAIT1, 62, "gpmc_wait1", NULL, "c2c_dataout2", | ||
| 132 | "gpio_62", NULL, NULL, NULL, "safe_mode"), | ||
| 133 | _OMAP4_MUXENTRY(C2C_DATA11, 100, "c2c_data11", "usbc1_icusb_txen", | ||
| 134 | "c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL, | ||
| 135 | NULL, "safe_mode"), | ||
| 136 | _OMAP4_MUXENTRY(C2C_DATA12, 101, "c2c_data12", "dsi1_te0", | ||
| 137 | "c2c_clkin0", "gpio_101", "sys_ndmareq1", NULL, NULL, | ||
| 138 | "safe_mode"), | ||
| 139 | _OMAP4_MUXENTRY(C2C_DATA13, 102, "c2c_data13", "dsi1_te1", | ||
| 140 | "c2c_clkin1", "gpio_102", "sys_ndmareq2", NULL, NULL, | ||
| 141 | "safe_mode"), | ||
| 142 | _OMAP4_MUXENTRY(C2C_DATA14, 103, "c2c_data14", "dsi2_te0", | ||
| 143 | "c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL, | ||
| 144 | NULL, "safe_mode"), | ||
| 145 | _OMAP4_MUXENTRY(C2C_DATA15, 104, "c2c_data15", "dsi2_te1", | ||
| 146 | "c2c_dataout1", "gpio_104", NULL, NULL, NULL, | ||
| 147 | "safe_mode"), | ||
| 148 | _OMAP4_MUXENTRY(HDMI_HPD, 63, "hdmi_hpd", NULL, NULL, "gpio_63", NULL, | ||
| 149 | NULL, NULL, "safe_mode"), | ||
| 150 | _OMAP4_MUXENTRY(HDMI_CEC, 64, "hdmi_cec", NULL, NULL, "gpio_64", NULL, | ||
| 151 | NULL, NULL, "safe_mode"), | ||
| 152 | _OMAP4_MUXENTRY(HDMI_DDC_SCL, 65, "hdmi_ddc_scl", NULL, NULL, | ||
| 153 | "gpio_65", NULL, NULL, NULL, "safe_mode"), | ||
| 154 | _OMAP4_MUXENTRY(HDMI_DDC_SDA, 66, "hdmi_ddc_sda", NULL, NULL, | ||
| 155 | "gpio_66", NULL, NULL, NULL, "safe_mode"), | ||
| 156 | _OMAP4_MUXENTRY(CSI21_DX0, 0, "csi21_dx0", NULL, NULL, "gpi_67", NULL, | ||
| 157 | NULL, NULL, "safe_mode"), | ||
| 158 | _OMAP4_MUXENTRY(CSI21_DY0, 0, "csi21_dy0", NULL, NULL, "gpi_68", NULL, | ||
| 159 | NULL, NULL, "safe_mode"), | ||
| 160 | _OMAP4_MUXENTRY(CSI21_DX1, 0, "csi21_dx1", NULL, NULL, "gpi_69", NULL, | ||
| 161 | NULL, NULL, "safe_mode"), | ||
| 162 | _OMAP4_MUXENTRY(CSI21_DY1, 0, "csi21_dy1", NULL, NULL, "gpi_70", NULL, | ||
| 163 | NULL, NULL, "safe_mode"), | ||
| 164 | _OMAP4_MUXENTRY(CSI21_DX2, 0, "csi21_dx2", NULL, NULL, "gpi_71", NULL, | ||
| 165 | NULL, NULL, "safe_mode"), | ||
| 166 | _OMAP4_MUXENTRY(CSI21_DY2, 0, "csi21_dy2", NULL, NULL, "gpi_72", NULL, | ||
| 167 | NULL, NULL, "safe_mode"), | ||
| 168 | _OMAP4_MUXENTRY(CSI21_DX3, 0, "csi21_dx3", NULL, NULL, "gpi_73", NULL, | ||
| 169 | NULL, NULL, "safe_mode"), | ||
| 170 | _OMAP4_MUXENTRY(CSI21_DY3, 0, "csi21_dy3", NULL, NULL, "gpi_74", NULL, | ||
| 171 | NULL, NULL, "safe_mode"), | ||
| 172 | _OMAP4_MUXENTRY(CSI21_DX4, 0, "csi21_dx4", NULL, NULL, "gpi_75", NULL, | ||
| 173 | NULL, NULL, "safe_mode"), | ||
| 174 | _OMAP4_MUXENTRY(CSI21_DY4, 0, "csi21_dy4", NULL, NULL, "gpi_76", NULL, | ||
| 175 | NULL, NULL, "safe_mode"), | ||
| 176 | _OMAP4_MUXENTRY(CSI22_DX0, 0, "csi22_dx0", NULL, NULL, "gpi_77", NULL, | ||
| 177 | NULL, NULL, "safe_mode"), | ||
| 178 | _OMAP4_MUXENTRY(CSI22_DY0, 0, "csi22_dy0", NULL, NULL, "gpi_78", NULL, | ||
| 179 | NULL, NULL, "safe_mode"), | ||
| 180 | _OMAP4_MUXENTRY(CSI22_DX1, 0, "csi22_dx1", NULL, NULL, "gpi_79", NULL, | ||
| 181 | NULL, NULL, "safe_mode"), | ||
| 182 | _OMAP4_MUXENTRY(CSI22_DY1, 0, "csi22_dy1", NULL, NULL, "gpi_80", NULL, | ||
| 183 | NULL, NULL, "safe_mode"), | ||
| 184 | _OMAP4_MUXENTRY(CAM_SHUTTER, 81, "cam_shutter", NULL, NULL, "gpio_81", | ||
| 185 | NULL, NULL, NULL, "safe_mode"), | ||
| 186 | _OMAP4_MUXENTRY(CAM_STROBE, 82, "cam_strobe", NULL, NULL, "gpio_82", | ||
| 187 | NULL, NULL, NULL, "safe_mode"), | ||
| 188 | _OMAP4_MUXENTRY(CAM_GLOBALRESET, 83, "cam_globalreset", NULL, NULL, | ||
| 189 | "gpio_83", NULL, NULL, NULL, "safe_mode"), | ||
| 190 | _OMAP4_MUXENTRY(USBB1_ULPITLL_CLK, 84, "usbb1_ulpitll_clk", | ||
| 191 | "hsi1_cawake", NULL, "gpio_84", "usbb1_ulpiphy_clk", | ||
| 192 | NULL, "hw_dbg20", "safe_mode"), | ||
| 193 | _OMAP4_MUXENTRY(USBB1_ULPITLL_STP, 85, "usbb1_ulpitll_stp", | ||
| 194 | "hsi1_cadata", "mcbsp4_clkr", "gpio_85", | ||
| 195 | "usbb1_ulpiphy_stp", "usbb1_mm_rxdp", "hw_dbg21", | ||
| 196 | "safe_mode"), | ||
| 197 | _OMAP4_MUXENTRY(USBB1_ULPITLL_DIR, 86, "usbb1_ulpitll_dir", | ||
| 198 | "hsi1_caflag", "mcbsp4_fsr", "gpio_86", | ||
| 199 | "usbb1_ulpiphy_dir", NULL, "hw_dbg22", "safe_mode"), | ||
| 200 | _OMAP4_MUXENTRY(USBB1_ULPITLL_NXT, 87, "usbb1_ulpitll_nxt", | ||
| 201 | "hsi1_acready", "mcbsp4_fsx", "gpio_87", | ||
| 202 | "usbb1_ulpiphy_nxt", "usbb1_mm_rxdm", "hw_dbg23", | ||
| 203 | "safe_mode"), | ||
| 204 | _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0", | ||
| 205 | "hsi1_acwake", "mcbsp4_clkx", "gpio_88", | ||
| 206 | "usbb1_ulpiphy_dat0", "usbb1_mm_rxrcv", "hw_dbg24", | ||
| 207 | "safe_mode"), | ||
| 208 | _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, 89, "usbb1_ulpitll_dat1", | ||
| 209 | "hsi1_acdata", "mcbsp4_dx", "gpio_89", | ||
| 210 | "usbb1_ulpiphy_dat1", "usbb1_mm_txse0", "hw_dbg25", | ||
| 211 | "safe_mode"), | ||
| 212 | _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, 90, "usbb1_ulpitll_dat2", | ||
| 213 | "hsi1_acflag", "mcbsp4_dr", "gpio_90", | ||
| 214 | "usbb1_ulpiphy_dat2", "usbb1_mm_txdat", "hw_dbg26", | ||
| 215 | "safe_mode"), | ||
| 216 | _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3", | ||
| 217 | "hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3", | ||
| 218 | "usbb1_mm_txen", "hw_dbg27", "safe_mode"), | ||
| 219 | _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT4, 92, "usbb1_ulpitll_dat4", | ||
| 220 | "dmtimer8_pwm_evt", "abe_mcbsp3_dr", "gpio_92", | ||
| 221 | "usbb1_ulpiphy_dat4", NULL, "hw_dbg28", "safe_mode"), | ||
| 222 | _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT5, 93, "usbb1_ulpitll_dat5", | ||
| 223 | "dmtimer9_pwm_evt", "abe_mcbsp3_dx", "gpio_93", | ||
| 224 | "usbb1_ulpiphy_dat5", NULL, "hw_dbg29", "safe_mode"), | ||
| 225 | _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT6, 94, "usbb1_ulpitll_dat6", | ||
| 226 | "dmtimer10_pwm_evt", "abe_mcbsp3_clkx", "gpio_94", | ||
| 227 | "usbb1_ulpiphy_dat6", "abe_dmic_din3", "hw_dbg30", | ||
| 228 | "safe_mode"), | ||
| 229 | _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT7, 95, "usbb1_ulpitll_dat7", | ||
| 230 | "dmtimer11_pwm_evt", "abe_mcbsp3_fsx", "gpio_95", | ||
| 231 | "usbb1_ulpiphy_dat7", "abe_dmic_clk3", "hw_dbg31", | ||
| 232 | "safe_mode"), | ||
| 233 | _OMAP4_MUXENTRY(USBB1_HSIC_DATA, 96, "usbb1_hsic_data", NULL, NULL, | ||
| 234 | "gpio_96", NULL, NULL, NULL, "safe_mode"), | ||
| 235 | _OMAP4_MUXENTRY(USBB1_HSIC_STROBE, 97, "usbb1_hsic_strobe", NULL, | ||
| 236 | NULL, "gpio_97", NULL, NULL, NULL, "safe_mode"), | ||
| 237 | _OMAP4_MUXENTRY(USBC1_ICUSB_DP, 98, "usbc1_icusb_dp", NULL, NULL, | ||
| 238 | "gpio_98", NULL, NULL, NULL, "safe_mode"), | ||
| 239 | _OMAP4_MUXENTRY(USBC1_ICUSB_DM, 99, "usbc1_icusb_dm", NULL, NULL, | ||
| 240 | "gpio_99", NULL, NULL, NULL, "safe_mode"), | ||
| 241 | _OMAP4_MUXENTRY(SDMMC1_CLK, 100, "sdmmc1_clk", NULL, "dpm_emu19", | ||
| 242 | "gpio_100", NULL, NULL, NULL, "safe_mode"), | ||
| 243 | _OMAP4_MUXENTRY(SDMMC1_CMD, 101, "sdmmc1_cmd", NULL, "uart1_rx", | ||
| 244 | "gpio_101", NULL, NULL, NULL, "safe_mode"), | ||
| 245 | _OMAP4_MUXENTRY(SDMMC1_DAT0, 102, "sdmmc1_dat0", NULL, "dpm_emu18", | ||
| 246 | "gpio_102", NULL, NULL, NULL, "safe_mode"), | ||
| 247 | _OMAP4_MUXENTRY(SDMMC1_DAT1, 103, "sdmmc1_dat1", NULL, "dpm_emu17", | ||
| 248 | "gpio_103", NULL, NULL, NULL, "safe_mode"), | ||
| 249 | _OMAP4_MUXENTRY(SDMMC1_DAT2, 104, "sdmmc1_dat2", NULL, "dpm_emu16", | ||
| 250 | "gpio_104", "jtag_tms_tmsc", NULL, NULL, "safe_mode"), | ||
| 251 | _OMAP4_MUXENTRY(SDMMC1_DAT3, 105, "sdmmc1_dat3", NULL, "dpm_emu15", | ||
| 252 | "gpio_105", "jtag_tck", NULL, NULL, "safe_mode"), | ||
| 253 | _OMAP4_MUXENTRY(SDMMC1_DAT4, 106, "sdmmc1_dat4", NULL, NULL, | ||
| 254 | "gpio_106", NULL, NULL, NULL, "safe_mode"), | ||
| 255 | _OMAP4_MUXENTRY(SDMMC1_DAT5, 107, "sdmmc1_dat5", NULL, NULL, | ||
| 256 | "gpio_107", NULL, NULL, NULL, "safe_mode"), | ||
| 257 | _OMAP4_MUXENTRY(SDMMC1_DAT6, 108, "sdmmc1_dat6", NULL, NULL, | ||
| 258 | "gpio_108", NULL, NULL, NULL, "safe_mode"), | ||
| 259 | _OMAP4_MUXENTRY(SDMMC1_DAT7, 109, "sdmmc1_dat7", NULL, NULL, | ||
| 260 | "gpio_109", NULL, NULL, NULL, "safe_mode"), | ||
| 261 | _OMAP4_MUXENTRY(ABE_MCBSP2_CLKX, 110, "abe_mcbsp2_clkx", "mcspi2_clk", | ||
| 262 | "abe_mcasp_ahclkx", "gpio_110", "usbb2_mm_rxdm", | ||
| 263 | NULL, NULL, "safe_mode"), | ||
| 264 | _OMAP4_MUXENTRY(ABE_MCBSP2_DR, 111, "abe_mcbsp2_dr", "mcspi2_somi", | ||
| 265 | "abe_mcasp_axr", "gpio_111", "usbb2_mm_rxdp", NULL, | ||
| 266 | NULL, "safe_mode"), | ||
| 267 | _OMAP4_MUXENTRY(ABE_MCBSP2_DX, 112, "abe_mcbsp2_dx", "mcspi2_simo", | ||
| 268 | "abe_mcasp_amute", "gpio_112", "usbb2_mm_rxrcv", NULL, | ||
| 269 | NULL, "safe_mode"), | ||
| 270 | _OMAP4_MUXENTRY(ABE_MCBSP2_FSX, 113, "abe_mcbsp2_fsx", "mcspi2_cs0", | ||
| 271 | "abe_mcasp_afsx", "gpio_113", "usbb2_mm_txen", NULL, | ||
| 272 | NULL, "safe_mode"), | ||
| 273 | _OMAP4_MUXENTRY(ABE_MCBSP1_CLKX, 114, "abe_mcbsp1_clkx", | ||
| 274 | "abe_slimbus1_clock", NULL, "gpio_114", NULL, NULL, | ||
| 275 | NULL, "safe_mode"), | ||
| 276 | _OMAP4_MUXENTRY(ABE_MCBSP1_DR, 115, "abe_mcbsp1_dr", | ||
| 277 | "abe_slimbus1_data", NULL, "gpio_115", NULL, NULL, | ||
| 278 | NULL, "safe_mode"), | ||
| 279 | _OMAP4_MUXENTRY(ABE_MCBSP1_DX, 116, "abe_mcbsp1_dx", "sdmmc3_dat2", | ||
| 280 | "abe_mcasp_aclkx", "gpio_116", NULL, NULL, NULL, | ||
| 281 | "safe_mode"), | ||
| 282 | _OMAP4_MUXENTRY(ABE_MCBSP1_FSX, 117, "abe_mcbsp1_fsx", "sdmmc3_dat3", | ||
| 283 | "abe_mcasp_amutein", "gpio_117", NULL, NULL, NULL, | ||
| 284 | "safe_mode"), | ||
| 285 | _OMAP4_MUXENTRY(ABE_PDM_UL_DATA, 0, "abe_pdm_ul_data", | ||
| 286 | "abe_mcbsp3_dr", NULL, NULL, NULL, NULL, NULL, | ||
| 287 | "safe_mode"), | ||
| 288 | _OMAP4_MUXENTRY(ABE_PDM_DL_DATA, 0, "abe_pdm_dl_data", | ||
| 289 | "abe_mcbsp3_dx", NULL, NULL, NULL, NULL, NULL, | ||
| 290 | "safe_mode"), | ||
| 291 | _OMAP4_MUXENTRY(ABE_PDM_FRAME, 0, "abe_pdm_frame", "abe_mcbsp3_clkx", | ||
| 292 | NULL, NULL, NULL, NULL, NULL, "safe_mode"), | ||
| 293 | _OMAP4_MUXENTRY(ABE_PDM_LB_CLK, 0, "abe_pdm_lb_clk", "abe_mcbsp3_fsx", | ||
| 294 | NULL, NULL, NULL, NULL, NULL, "safe_mode"), | ||
| 295 | _OMAP4_MUXENTRY(ABE_CLKS, 118, "abe_clks", NULL, NULL, "gpio_118", | ||
| 296 | NULL, NULL, NULL, "safe_mode"), | ||
| 297 | _OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL, | ||
| 298 | "gpio_119", "usbb2_mm_txse0", NULL, NULL, | ||
| 299 | "safe_mode"), | ||
| 300 | _OMAP4_MUXENTRY(ABE_DMIC_DIN1, 120, "abe_dmic_din1", NULL, NULL, | ||
| 301 | "gpio_120", "usbb2_mm_txdat", NULL, NULL, | ||
| 302 | "safe_mode"), | ||
| 303 | _OMAP4_MUXENTRY(ABE_DMIC_DIN2, 121, "abe_dmic_din2", "slimbus2_clock", | ||
| 304 | NULL, "gpio_121", NULL, NULL, NULL, "safe_mode"), | ||
| 305 | _OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data", | ||
| 306 | "abe_dmic_clk2", "gpio_122", NULL, NULL, NULL, | ||
| 307 | "safe_mode"), | ||
| 308 | _OMAP4_MUXENTRY(UART2_CTS, 123, "uart2_cts", "sdmmc3_clk", NULL, | ||
| 309 | "gpio_123", NULL, NULL, NULL, "safe_mode"), | ||
| 310 | _OMAP4_MUXENTRY(UART2_RTS, 124, "uart2_rts", "sdmmc3_cmd", NULL, | ||
| 311 | "gpio_124", NULL, NULL, NULL, "safe_mode"), | ||
| 312 | _OMAP4_MUXENTRY(UART2_RX, 125, "uart2_rx", "sdmmc3_dat0", NULL, | ||
| 313 | "gpio_125", NULL, NULL, NULL, "safe_mode"), | ||
| 314 | _OMAP4_MUXENTRY(UART2_TX, 126, "uart2_tx", "sdmmc3_dat1", NULL, | ||
| 315 | "gpio_126", NULL, NULL, NULL, "safe_mode"), | ||
| 316 | _OMAP4_MUXENTRY(HDQ_SIO, 127, "hdq_sio", "i2c3_sccb", "i2c2_sccb", | ||
| 317 | "gpio_127", NULL, NULL, NULL, "safe_mode"), | ||
| 318 | _OMAP4_MUXENTRY(I2C1_SCL, 0, "i2c1_scl", NULL, NULL, NULL, NULL, NULL, | ||
| 319 | NULL, NULL), | ||
| 320 | _OMAP4_MUXENTRY(I2C1_SDA, 0, "i2c1_sda", NULL, NULL, NULL, NULL, NULL, | ||
| 321 | NULL, NULL), | ||
| 322 | _OMAP4_MUXENTRY(I2C2_SCL, 128, "i2c2_scl", "uart1_rx", NULL, | ||
| 323 | "gpio_128", NULL, NULL, NULL, "safe_mode"), | ||
| 324 | _OMAP4_MUXENTRY(I2C2_SDA, 129, "i2c2_sda", "uart1_tx", NULL, | ||
| 325 | "gpio_129", NULL, NULL, NULL, "safe_mode"), | ||
| 326 | _OMAP4_MUXENTRY(I2C3_SCL, 130, "i2c3_scl", NULL, NULL, "gpio_130", | ||
| 327 | NULL, NULL, NULL, "safe_mode"), | ||
| 328 | _OMAP4_MUXENTRY(I2C3_SDA, 131, "i2c3_sda", NULL, NULL, "gpio_131", | ||
| 329 | NULL, NULL, NULL, "safe_mode"), | ||
| 330 | _OMAP4_MUXENTRY(I2C4_SCL, 132, "i2c4_scl", NULL, NULL, "gpio_132", | ||
| 331 | NULL, NULL, NULL, "safe_mode"), | ||
| 332 | _OMAP4_MUXENTRY(I2C4_SDA, 133, "i2c4_sda", NULL, NULL, "gpio_133", | ||
| 333 | NULL, NULL, NULL, "safe_mode"), | ||
| 334 | _OMAP4_MUXENTRY(MCSPI1_CLK, 134, "mcspi1_clk", NULL, NULL, "gpio_134", | ||
| 335 | NULL, NULL, NULL, "safe_mode"), | ||
| 336 | _OMAP4_MUXENTRY(MCSPI1_SOMI, 135, "mcspi1_somi", NULL, NULL, | ||
| 337 | "gpio_135", NULL, NULL, NULL, "safe_mode"), | ||
| 338 | _OMAP4_MUXENTRY(MCSPI1_SIMO, 136, "mcspi1_simo", NULL, NULL, | ||
| 339 | "gpio_136", NULL, NULL, NULL, "safe_mode"), | ||
| 340 | _OMAP4_MUXENTRY(MCSPI1_CS0, 137, "mcspi1_cs0", NULL, NULL, "gpio_137", | ||
| 341 | NULL, NULL, NULL, "safe_mode"), | ||
| 342 | _OMAP4_MUXENTRY(MCSPI1_CS1, 138, "mcspi1_cs1", "uart1_rx", NULL, | ||
| 343 | "gpio_138", NULL, NULL, NULL, "safe_mode"), | ||
| 344 | _OMAP4_MUXENTRY(MCSPI1_CS2, 139, "mcspi1_cs2", "uart1_cts", | ||
| 345 | "slimbus2_clock", "gpio_139", NULL, NULL, NULL, | ||
| 346 | "safe_mode"), | ||
| 347 | _OMAP4_MUXENTRY(MCSPI1_CS3, 140, "mcspi1_cs3", "uart1_rts", | ||
| 348 | "slimbus2_data", "gpio_140", NULL, NULL, NULL, | ||
| 349 | "safe_mode"), | ||
| 350 | _OMAP4_MUXENTRY(UART3_CTS_RCTX, 141, "uart3_cts_rctx", "uart1_tx", | ||
| 351 | NULL, "gpio_141", NULL, NULL, NULL, "safe_mode"), | ||
| 352 | _OMAP4_MUXENTRY(UART3_RTS_SD, 142, "uart3_rts_sd", NULL, NULL, | ||
| 353 | "gpio_142", NULL, NULL, NULL, "safe_mode"), | ||
| 354 | _OMAP4_MUXENTRY(UART3_RX_IRRX, 143, "uart3_rx_irrx", | ||
| 355 | "dmtimer8_pwm_evt", NULL, "gpio_143", NULL, NULL, | ||
| 356 | NULL, "safe_mode"), | ||
| 357 | _OMAP4_MUXENTRY(UART3_TX_IRTX, 144, "uart3_tx_irtx", | ||
| 358 | "dmtimer9_pwm_evt", NULL, "gpio_144", NULL, NULL, | ||
| 359 | NULL, "safe_mode"), | ||
| 360 | _OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk", | ||
| 361 | "usbc1_icusb_dp", "gpio_145", NULL, NULL, NULL, | ||
| 362 | "safe_mode"), | ||
| 363 | _OMAP4_MUXENTRY(SDMMC5_CMD, 146, "sdmmc5_cmd", "mcspi2_simo", | ||
| 364 | "usbc1_icusb_dm", "gpio_146", NULL, NULL, NULL, | ||
| 365 | "safe_mode"), | ||
| 366 | _OMAP4_MUXENTRY(SDMMC5_DAT0, 147, "sdmmc5_dat0", "mcspi2_somi", | ||
| 367 | "usbc1_icusb_rcv", "gpio_147", NULL, NULL, NULL, | ||
| 368 | "safe_mode"), | ||
| 369 | _OMAP4_MUXENTRY(SDMMC5_DAT1, 148, "sdmmc5_dat1", NULL, | ||
| 370 | "usbc1_icusb_txen", "gpio_148", NULL, NULL, NULL, | ||
| 371 | "safe_mode"), | ||
| 372 | _OMAP4_MUXENTRY(SDMMC5_DAT2, 149, "sdmmc5_dat2", "mcspi2_cs1", NULL, | ||
| 373 | "gpio_149", NULL, NULL, NULL, "safe_mode"), | ||
| 374 | _OMAP4_MUXENTRY(SDMMC5_DAT3, 150, "sdmmc5_dat3", "mcspi2_cs0", NULL, | ||
| 375 | "gpio_150", NULL, NULL, NULL, "safe_mode"), | ||
| 376 | _OMAP4_MUXENTRY(MCSPI4_CLK, 151, "mcspi4_clk", "sdmmc4_clk", NULL, | ||
| 377 | "gpio_151", NULL, NULL, NULL, "safe_mode"), | ||
| 378 | _OMAP4_MUXENTRY(MCSPI4_SIMO, 152, "mcspi4_simo", "sdmmc4_cmd", NULL, | ||
| 379 | "gpio_152", NULL, NULL, NULL, "safe_mode"), | ||
| 380 | _OMAP4_MUXENTRY(MCSPI4_SOMI, 153, "mcspi4_somi", "sdmmc4_dat0", NULL, | ||
| 381 | "gpio_153", NULL, NULL, NULL, "safe_mode"), | ||
| 382 | _OMAP4_MUXENTRY(MCSPI4_CS0, 154, "mcspi4_cs0", "sdmmc4_dat3", NULL, | ||
| 383 | "gpio_154", NULL, NULL, NULL, "safe_mode"), | ||
| 384 | _OMAP4_MUXENTRY(UART4_RX, 155, "uart4_rx", "sdmmc4_dat2", NULL, | ||
| 385 | "gpio_155", NULL, NULL, NULL, "safe_mode"), | ||
| 386 | _OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", NULL, | ||
| 387 | "gpio_156", NULL, NULL, NULL, "safe_mode"), | ||
| 388 | _OMAP4_MUXENTRY(USBB2_ULPITLL_CLK, 157, "usbb2_ulpitll_clk", | ||
| 389 | "usbb2_ulpiphy_clk", "sdmmc4_cmd", "gpio_157", | ||
| 390 | "hsi2_cawake", NULL, NULL, "safe_mode"), | ||
| 391 | _OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp", | ||
| 392 | "usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158", | ||
| 393 | "hsi2_cadata", "dispc2_data23", NULL, "reserved"), | ||
| 394 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, 159, "usbb2_ulpitll_dir", | ||
| 395 | "usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159", | ||
| 396 | "hsi2_caflag", "dispc2_data22", NULL, "reserved"), | ||
| 397 | _OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, 160, "usbb2_ulpitll_nxt", | ||
| 398 | "usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160", | ||
| 399 | "hsi2_acready", "dispc2_data21", NULL, "reserved"), | ||
| 400 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, 161, "usbb2_ulpitll_dat0", | ||
| 401 | "usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161", | ||
| 402 | "hsi2_acwake", "dispc2_data20", NULL, "reserved"), | ||
| 403 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, 162, "usbb2_ulpitll_dat1", | ||
| 404 | "usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162", | ||
| 405 | "hsi2_acdata", "dispc2_data19", NULL, "reserved"), | ||
| 406 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, 163, "usbb2_ulpitll_dat2", | ||
| 407 | "usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163", | ||
| 408 | "hsi2_acflag", "dispc2_data18", NULL, "reserved"), | ||
| 409 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, 164, "usbb2_ulpitll_dat3", | ||
| 410 | "usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164", | ||
| 411 | "hsi2_caready", "dispc2_data15", NULL, "reserved"), | ||
| 412 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, 165, "usbb2_ulpitll_dat4", | ||
| 413 | "usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165", | ||
| 414 | "mcspi3_somi", "dispc2_data14", NULL, "reserved"), | ||
| 415 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, 166, "usbb2_ulpitll_dat5", | ||
| 416 | "usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166", | ||
| 417 | "mcspi3_cs0", "dispc2_data13", NULL, "reserved"), | ||
| 418 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, 167, "usbb2_ulpitll_dat6", | ||
| 419 | "usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167", | ||
| 420 | "mcspi3_simo", "dispc2_data12", NULL, "reserved"), | ||
| 421 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, 168, "usbb2_ulpitll_dat7", | ||
| 422 | "usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168", | ||
| 423 | "mcspi3_clk", "dispc2_data11", NULL, "reserved"), | ||
| 424 | _OMAP4_MUXENTRY(USBB2_HSIC_DATA, 169, "usbb2_hsic_data", NULL, NULL, | ||
| 425 | "gpio_169", NULL, NULL, NULL, "safe_mode"), | ||
| 426 | _OMAP4_MUXENTRY(USBB2_HSIC_STROBE, 170, "usbb2_hsic_strobe", NULL, | ||
| 427 | NULL, "gpio_170", NULL, NULL, NULL, "safe_mode"), | ||
| 428 | _OMAP4_MUXENTRY(UNIPRO_TX0, 171, "unipro_tx0", "kpd_col0", NULL, | ||
| 429 | "gpio_171", NULL, NULL, NULL, "safe_mode"), | ||
| 430 | _OMAP4_MUXENTRY(UNIPRO_TY0, 172, "unipro_ty0", "kpd_col1", NULL, | ||
| 431 | "gpio_172", NULL, NULL, NULL, "safe_mode"), | ||
| 432 | _OMAP4_MUXENTRY(UNIPRO_TX1, 173, "unipro_tx1", "kpd_col2", NULL, | ||
| 433 | "gpio_173", NULL, NULL, NULL, "safe_mode"), | ||
| 434 | _OMAP4_MUXENTRY(UNIPRO_TY1, 174, "unipro_ty1", "kpd_col3", NULL, | ||
| 435 | "gpio_174", NULL, NULL, NULL, "safe_mode"), | ||
| 436 | _OMAP4_MUXENTRY(UNIPRO_TX2, 0, "unipro_tx2", "kpd_col4", NULL, | ||
| 437 | "gpio_0", NULL, NULL, NULL, "safe_mode"), | ||
| 438 | _OMAP4_MUXENTRY(UNIPRO_TY2, 1, "unipro_ty2", "kpd_col5", NULL, | ||
| 439 | "gpio_1", NULL, NULL, NULL, "safe_mode"), | ||
| 440 | _OMAP4_MUXENTRY(UNIPRO_RX0, 0, "unipro_rx0", "kpd_row0", NULL, | ||
| 441 | "gpi_175", NULL, NULL, NULL, "safe_mode"), | ||
| 442 | _OMAP4_MUXENTRY(UNIPRO_RY0, 0, "unipro_ry0", "kpd_row1", NULL, | ||
| 443 | "gpi_176", NULL, NULL, NULL, "safe_mode"), | ||
| 444 | _OMAP4_MUXENTRY(UNIPRO_RX1, 0, "unipro_rx1", "kpd_row2", NULL, | ||
| 445 | "gpi_177", NULL, NULL, NULL, "safe_mode"), | ||
| 446 | _OMAP4_MUXENTRY(UNIPRO_RY1, 0, "unipro_ry1", "kpd_row3", NULL, | ||
| 447 | "gpi_178", NULL, NULL, NULL, "safe_mode"), | ||
| 448 | _OMAP4_MUXENTRY(UNIPRO_RX2, 0, "unipro_rx2", "kpd_row4", NULL, | ||
| 449 | "gpi_2", NULL, NULL, NULL, "safe_mode"), | ||
| 450 | _OMAP4_MUXENTRY(UNIPRO_RY2, 0, "unipro_ry2", "kpd_row5", NULL, | ||
| 451 | "gpi_3", NULL, NULL, NULL, "safe_mode"), | ||
| 452 | _OMAP4_MUXENTRY(USBA0_OTG_CE, 0, "usba0_otg_ce", NULL, NULL, NULL, | ||
| 453 | NULL, NULL, NULL, NULL), | ||
| 454 | _OMAP4_MUXENTRY(USBA0_OTG_DP, 179, "usba0_otg_dp", "uart3_rx_irrx", | ||
| 455 | "uart2_rx", "gpio_179", NULL, NULL, NULL, | ||
| 456 | "safe_mode"), | ||
| 457 | _OMAP4_MUXENTRY(USBA0_OTG_DM, 180, "usba0_otg_dm", "uart3_tx_irtx", | ||
| 458 | "uart2_tx", "gpio_180", NULL, NULL, NULL, | ||
| 459 | "safe_mode"), | ||
| 460 | _OMAP4_MUXENTRY(FREF_CLK1_OUT, 181, "fref_clk1_out", NULL, NULL, | ||
| 461 | "gpio_181", NULL, NULL, NULL, "safe_mode"), | ||
| 462 | _OMAP4_MUXENTRY(FREF_CLK2_OUT, 182, "fref_clk2_out", NULL, NULL, | ||
| 463 | "gpio_182", NULL, NULL, NULL, "safe_mode"), | ||
| 464 | _OMAP4_MUXENTRY(SYS_NIRQ1, 0, "sys_nirq1", NULL, NULL, NULL, NULL, | ||
| 465 | NULL, NULL, "safe_mode"), | ||
| 466 | _OMAP4_MUXENTRY(SYS_NIRQ2, 183, "sys_nirq2", NULL, NULL, "gpio_183", | ||
| 467 | NULL, NULL, NULL, "safe_mode"), | ||
| 468 | _OMAP4_MUXENTRY(SYS_BOOT0, 184, "sys_boot0", NULL, NULL, "gpio_184", | ||
| 469 | NULL, NULL, NULL, "safe_mode"), | ||
| 470 | _OMAP4_MUXENTRY(SYS_BOOT1, 185, "sys_boot1", NULL, NULL, "gpio_185", | ||
| 471 | NULL, NULL, NULL, "safe_mode"), | ||
| 472 | _OMAP4_MUXENTRY(SYS_BOOT2, 186, "sys_boot2", NULL, NULL, "gpio_186", | ||
| 473 | NULL, NULL, NULL, "safe_mode"), | ||
| 474 | _OMAP4_MUXENTRY(SYS_BOOT3, 187, "sys_boot3", NULL, NULL, "gpio_187", | ||
| 475 | NULL, NULL, NULL, "safe_mode"), | ||
| 476 | _OMAP4_MUXENTRY(SYS_BOOT4, 188, "sys_boot4", NULL, NULL, "gpio_188", | ||
| 477 | NULL, NULL, NULL, "safe_mode"), | ||
| 478 | _OMAP4_MUXENTRY(SYS_BOOT5, 189, "sys_boot5", NULL, NULL, "gpio_189", | ||
| 479 | NULL, NULL, NULL, "safe_mode"), | ||
| 480 | _OMAP4_MUXENTRY(DPM_EMU0, 11, "dpm_emu0", NULL, NULL, "gpio_11", NULL, | ||
| 481 | NULL, "hw_dbg0", "safe_mode"), | ||
| 482 | _OMAP4_MUXENTRY(DPM_EMU1, 12, "dpm_emu1", NULL, NULL, "gpio_12", NULL, | ||
| 483 | NULL, "hw_dbg1", "safe_mode"), | ||
| 484 | _OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL, | ||
| 485 | "gpio_13", NULL, "dispc2_fid", "hw_dbg2", "reserved"), | ||
| 486 | _OMAP4_MUXENTRY(DPM_EMU3, 14, "dpm_emu3", "usba0_ulpiphy_stp", NULL, | ||
| 487 | "gpio_14", NULL, "dispc2_data10", "hw_dbg3", | ||
| 488 | "reserved"), | ||
| 489 | _OMAP4_MUXENTRY(DPM_EMU4, 15, "dpm_emu4", "usba0_ulpiphy_dir", NULL, | ||
| 490 | "gpio_15", NULL, "dispc2_data9", "hw_dbg4", | ||
| 491 | "reserved"), | ||
| 492 | _OMAP4_MUXENTRY(DPM_EMU5, 16, "dpm_emu5", "usba0_ulpiphy_nxt", NULL, | ||
| 493 | "gpio_16", "rfbi_te_vsync0", "dispc2_data16", | ||
| 494 | "hw_dbg5", "reserved"), | ||
| 495 | _OMAP4_MUXENTRY(DPM_EMU6, 17, "dpm_emu6", "usba0_ulpiphy_dat0", | ||
| 496 | "uart3_tx_irtx", "gpio_17", "rfbi_hsync0", | ||
| 497 | "dispc2_data17", "hw_dbg6", "reserved"), | ||
| 498 | _OMAP4_MUXENTRY(DPM_EMU7, 18, "dpm_emu7", "usba0_ulpiphy_dat1", | ||
| 499 | "uart3_rx_irrx", "gpio_18", "rfbi_cs0", | ||
| 500 | "dispc2_hsync", "hw_dbg7", "reserved"), | ||
| 501 | _OMAP4_MUXENTRY(DPM_EMU8, 19, "dpm_emu8", "usba0_ulpiphy_dat2", | ||
| 502 | "uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk", | ||
| 503 | "hw_dbg8", "reserved"), | ||
| 504 | _OMAP4_MUXENTRY(DPM_EMU9, 20, "dpm_emu9", "usba0_ulpiphy_dat3", | ||
| 505 | "uart3_cts_rctx", "gpio_20", "rfbi_we", | ||
| 506 | "dispc2_vsync", "hw_dbg9", "reserved"), | ||
| 507 | _OMAP4_MUXENTRY(DPM_EMU10, 21, "dpm_emu10", "usba0_ulpiphy_dat4", | ||
| 508 | NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10", | ||
| 509 | "reserved"), | ||
| 510 | _OMAP4_MUXENTRY(DPM_EMU11, 22, "dpm_emu11", "usba0_ulpiphy_dat5", | ||
| 511 | NULL, "gpio_22", "rfbi_data8", "dispc2_data8", | ||
| 512 | "hw_dbg11", "reserved"), | ||
| 513 | _OMAP4_MUXENTRY(DPM_EMU12, 23, "dpm_emu12", "usba0_ulpiphy_dat6", | ||
| 514 | NULL, "gpio_23", "rfbi_data7", "dispc2_data7", | ||
| 515 | "hw_dbg12", "reserved"), | ||
| 516 | _OMAP4_MUXENTRY(DPM_EMU13, 24, "dpm_emu13", "usba0_ulpiphy_dat7", | ||
| 517 | NULL, "gpio_24", "rfbi_data6", "dispc2_data6", | ||
| 518 | "hw_dbg13", "reserved"), | ||
| 519 | _OMAP4_MUXENTRY(DPM_EMU14, 25, "dpm_emu14", "sys_drm_msecure", | ||
| 520 | "uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5", | ||
| 521 | "hw_dbg14", "reserved"), | ||
| 522 | _OMAP4_MUXENTRY(DPM_EMU15, 26, "dpm_emu15", "sys_secure_indicator", | ||
| 523 | NULL, "gpio_26", "rfbi_data4", "dispc2_data4", | ||
| 524 | "hw_dbg15", "reserved"), | ||
| 525 | _OMAP4_MUXENTRY(DPM_EMU16, 27, "dpm_emu16", "dmtimer8_pwm_evt", | ||
| 526 | "dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3", | ||
| 527 | "hw_dbg16", "reserved"), | ||
| 528 | _OMAP4_MUXENTRY(DPM_EMU17, 28, "dpm_emu17", "dmtimer9_pwm_evt", | ||
| 529 | "dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2", | ||
| 530 | "hw_dbg17", "reserved"), | ||
| 531 | _OMAP4_MUXENTRY(DPM_EMU18, 190, "dpm_emu18", "dmtimer10_pwm_evt", | ||
| 532 | "dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1", | ||
| 533 | "hw_dbg18", "reserved"), | ||
| 534 | _OMAP4_MUXENTRY(DPM_EMU19, 191, "dpm_emu19", "dmtimer11_pwm_evt", | ||
| 535 | "dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0", | ||
| 536 | "hw_dbg19", "reserved"), | ||
| 537 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
| 538 | }; | ||
| 539 | |||
| 540 | /* | ||
| 541 | * Balls for 44XX CBL package | ||
| 542 | * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top), | ||
| 543 | * 0.40mm Ball Pitch (Bottom) | ||
| 544 | */ | ||
| 545 | #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ | ||
| 546 | && defined(CONFIG_OMAP_PACKAGE_CBL) | ||
| 547 | struct omap_ball __initdata omap4_core_cbl_ball[] = { | ||
| 548 | _OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL), | ||
| 549 | _OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL), | ||
| 550 | _OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL), | ||
| 551 | _OMAP4_BALLENTRY(GPMC_AD3, "d13", NULL), | ||
| 552 | _OMAP4_BALLENTRY(GPMC_AD4, "c15", NULL), | ||
| 553 | _OMAP4_BALLENTRY(GPMC_AD5, "d15", NULL), | ||
| 554 | _OMAP4_BALLENTRY(GPMC_AD6, "a16", NULL), | ||
| 555 | _OMAP4_BALLENTRY(GPMC_AD7, "b16", NULL), | ||
| 556 | _OMAP4_BALLENTRY(GPMC_AD8, "c16", NULL), | ||
| 557 | _OMAP4_BALLENTRY(GPMC_AD9, "d16", NULL), | ||
| 558 | _OMAP4_BALLENTRY(GPMC_AD10, "c17", NULL), | ||
| 559 | _OMAP4_BALLENTRY(GPMC_AD11, "d17", NULL), | ||
| 560 | _OMAP4_BALLENTRY(GPMC_AD12, "c18", NULL), | ||
| 561 | _OMAP4_BALLENTRY(GPMC_AD13, "d18", NULL), | ||
| 562 | _OMAP4_BALLENTRY(GPMC_AD14, "c19", NULL), | ||
| 563 | _OMAP4_BALLENTRY(GPMC_AD15, "d19", NULL), | ||
| 564 | _OMAP4_BALLENTRY(GPMC_A16, "b17", NULL), | ||
| 565 | _OMAP4_BALLENTRY(GPMC_A17, "a18", NULL), | ||
| 566 | _OMAP4_BALLENTRY(GPMC_A18, "b18", NULL), | ||
| 567 | _OMAP4_BALLENTRY(GPMC_A19, "a19", NULL), | ||
| 568 | _OMAP4_BALLENTRY(GPMC_A20, "b19", NULL), | ||
| 569 | _OMAP4_BALLENTRY(GPMC_A21, "b20", NULL), | ||
| 570 | _OMAP4_BALLENTRY(GPMC_A22, "a21", NULL), | ||
| 571 | _OMAP4_BALLENTRY(GPMC_A23, "b21", NULL), | ||
| 572 | _OMAP4_BALLENTRY(GPMC_A24, "c20", NULL), | ||
| 573 | _OMAP4_BALLENTRY(GPMC_A25, "d20", NULL), | ||
| 574 | _OMAP4_BALLENTRY(GPMC_NCS0, "b25", NULL), | ||
| 575 | _OMAP4_BALLENTRY(GPMC_NCS1, "c21", NULL), | ||
| 576 | _OMAP4_BALLENTRY(GPMC_NCS2, "d21", NULL), | ||
| 577 | _OMAP4_BALLENTRY(GPMC_NCS3, "c22", NULL), | ||
| 578 | _OMAP4_BALLENTRY(GPMC_NWP, "c25", NULL), | ||
| 579 | _OMAP4_BALLENTRY(GPMC_CLK, "b22", NULL), | ||
| 580 | _OMAP4_BALLENTRY(GPMC_NADV_ALE, "d25", NULL), | ||
| 581 | _OMAP4_BALLENTRY(GPMC_NOE, "b11", NULL), | ||
| 582 | _OMAP4_BALLENTRY(GPMC_NWE, "b12", NULL), | ||
| 583 | _OMAP4_BALLENTRY(GPMC_NBE0_CLE, "c23", NULL), | ||
| 584 | _OMAP4_BALLENTRY(GPMC_NBE1, "d22", NULL), | ||
| 585 | _OMAP4_BALLENTRY(GPMC_WAIT0, "b26", NULL), | ||
| 586 | _OMAP4_BALLENTRY(GPMC_WAIT1, "b23", NULL), | ||
| 587 | _OMAP4_BALLENTRY(C2C_DATA11, "d23", NULL), | ||
| 588 | _OMAP4_BALLENTRY(C2C_DATA12, "a24", NULL), | ||
| 589 | _OMAP4_BALLENTRY(C2C_DATA13, "b24", NULL), | ||
| 590 | _OMAP4_BALLENTRY(C2C_DATA14, "c24", NULL), | ||
| 591 | _OMAP4_BALLENTRY(C2C_DATA15, "d24", NULL), | ||
| 592 | _OMAP4_BALLENTRY(HDMI_HPD, "b9", NULL), | ||
| 593 | _OMAP4_BALLENTRY(HDMI_CEC, "b10", NULL), | ||
| 594 | _OMAP4_BALLENTRY(HDMI_DDC_SCL, "a8", NULL), | ||
| 595 | _OMAP4_BALLENTRY(HDMI_DDC_SDA, "b8", NULL), | ||
| 596 | _OMAP4_BALLENTRY(CSI21_DX0, "r26", NULL), | ||
| 597 | _OMAP4_BALLENTRY(CSI21_DY0, "r25", NULL), | ||
| 598 | _OMAP4_BALLENTRY(CSI21_DX1, "t26", NULL), | ||
| 599 | _OMAP4_BALLENTRY(CSI21_DY1, "t25", NULL), | ||
| 600 | _OMAP4_BALLENTRY(CSI21_DX2, "u26", NULL), | ||
| 601 | _OMAP4_BALLENTRY(CSI21_DY2, "u25", NULL), | ||
| 602 | _OMAP4_BALLENTRY(CSI21_DX3, "v26", NULL), | ||
| 603 | _OMAP4_BALLENTRY(CSI21_DY3, "v25", NULL), | ||
| 604 | _OMAP4_BALLENTRY(CSI21_DX4, "w26", NULL), | ||
| 605 | _OMAP4_BALLENTRY(CSI21_DY4, "w25", NULL), | ||
| 606 | _OMAP4_BALLENTRY(CSI22_DX0, "m26", NULL), | ||
| 607 | _OMAP4_BALLENTRY(CSI22_DY0, "m25", NULL), | ||
| 608 | _OMAP4_BALLENTRY(CSI22_DX1, "n26", NULL), | ||
| 609 | _OMAP4_BALLENTRY(CSI22_DY1, "n25", NULL), | ||
| 610 | _OMAP4_BALLENTRY(CAM_SHUTTER, "t27", NULL), | ||
| 611 | _OMAP4_BALLENTRY(CAM_STROBE, "u27", NULL), | ||
| 612 | _OMAP4_BALLENTRY(CAM_GLOBALRESET, "v27", NULL), | ||
| 613 | _OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, "ae18", NULL), | ||
| 614 | _OMAP4_BALLENTRY(USBB1_ULPITLL_STP, "ag19", NULL), | ||
| 615 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, "af19", NULL), | ||
| 616 | _OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, "ae19", NULL), | ||
| 617 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, "af18", NULL), | ||
| 618 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, "ag18", NULL), | ||
| 619 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, "ae17", NULL), | ||
| 620 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, "af17", NULL), | ||
| 621 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, "ah17", NULL), | ||
| 622 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, "ae16", NULL), | ||
| 623 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, "af16", NULL), | ||
| 624 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, "ag16", NULL), | ||
| 625 | _OMAP4_BALLENTRY(USBB1_HSIC_DATA, "af14", NULL), | ||
| 626 | _OMAP4_BALLENTRY(USBB1_HSIC_STROBE, "ae14", NULL), | ||
| 627 | _OMAP4_BALLENTRY(USBC1_ICUSB_DP, "h2", NULL), | ||
| 628 | _OMAP4_BALLENTRY(USBC1_ICUSB_DM, "h3", NULL), | ||
| 629 | _OMAP4_BALLENTRY(SDMMC1_CLK, "d2", NULL), | ||
| 630 | _OMAP4_BALLENTRY(SDMMC1_CMD, "e3", NULL), | ||
| 631 | _OMAP4_BALLENTRY(SDMMC1_DAT0, "e4", NULL), | ||
| 632 | _OMAP4_BALLENTRY(SDMMC1_DAT1, "e2", NULL), | ||
| 633 | _OMAP4_BALLENTRY(SDMMC1_DAT2, "e1", NULL), | ||
| 634 | _OMAP4_BALLENTRY(SDMMC1_DAT3, "f4", NULL), | ||
| 635 | _OMAP4_BALLENTRY(SDMMC1_DAT4, "f3", NULL), | ||
| 636 | _OMAP4_BALLENTRY(SDMMC1_DAT5, "f1", NULL), | ||
| 637 | _OMAP4_BALLENTRY(SDMMC1_DAT6, "g4", NULL), | ||
| 638 | _OMAP4_BALLENTRY(SDMMC1_DAT7, "g3", NULL), | ||
| 639 | _OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, "ad27", NULL), | ||
| 640 | _OMAP4_BALLENTRY(ABE_MCBSP2_DR, "ad26", NULL), | ||
| 641 | _OMAP4_BALLENTRY(ABE_MCBSP2_DX, "ad25", NULL), | ||
| 642 | _OMAP4_BALLENTRY(ABE_MCBSP2_FSX, "ac28", NULL), | ||
| 643 | _OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, "ac26", NULL), | ||
| 644 | _OMAP4_BALLENTRY(ABE_MCBSP1_DR, "ac25", NULL), | ||
| 645 | _OMAP4_BALLENTRY(ABE_MCBSP1_DX, "ab25", NULL), | ||
| 646 | _OMAP4_BALLENTRY(ABE_MCBSP1_FSX, "ac27", NULL), | ||
| 647 | _OMAP4_BALLENTRY(ABE_PDM_UL_DATA, "ag25", NULL), | ||
| 648 | _OMAP4_BALLENTRY(ABE_PDM_DL_DATA, "af25", NULL), | ||
| 649 | _OMAP4_BALLENTRY(ABE_PDM_FRAME, "ae25", NULL), | ||
| 650 | _OMAP4_BALLENTRY(ABE_PDM_LB_CLK, "af26", NULL), | ||
| 651 | _OMAP4_BALLENTRY(ABE_CLKS, "ah26", NULL), | ||
| 652 | _OMAP4_BALLENTRY(ABE_DMIC_CLK1, "ae24", NULL), | ||
| 653 | _OMAP4_BALLENTRY(ABE_DMIC_DIN1, "af24", NULL), | ||
| 654 | _OMAP4_BALLENTRY(ABE_DMIC_DIN2, "ag24", NULL), | ||
| 655 | _OMAP4_BALLENTRY(ABE_DMIC_DIN3, "ah24", NULL), | ||
| 656 | _OMAP4_BALLENTRY(UART2_CTS, "ab26", NULL), | ||
| 657 | _OMAP4_BALLENTRY(UART2_RTS, "ab27", NULL), | ||
| 658 | _OMAP4_BALLENTRY(UART2_RX, "aa25", NULL), | ||
| 659 | _OMAP4_BALLENTRY(UART2_TX, "aa26", NULL), | ||
| 660 | _OMAP4_BALLENTRY(HDQ_SIO, "aa27", NULL), | ||
| 661 | _OMAP4_BALLENTRY(I2C1_SCL, "ae28", NULL), | ||
| 662 | _OMAP4_BALLENTRY(I2C1_SDA, "ae26", NULL), | ||
| 663 | _OMAP4_BALLENTRY(I2C2_SCL, "c26", NULL), | ||
| 664 | _OMAP4_BALLENTRY(I2C2_SDA, "d26", NULL), | ||
| 665 | _OMAP4_BALLENTRY(I2C3_SCL, "w27", NULL), | ||
| 666 | _OMAP4_BALLENTRY(I2C3_SDA, "y27", NULL), | ||
| 667 | _OMAP4_BALLENTRY(I2C4_SCL, "ag21", NULL), | ||
| 668 | _OMAP4_BALLENTRY(I2C4_SDA, "ah22", NULL), | ||
| 669 | _OMAP4_BALLENTRY(MCSPI1_CLK, "af22", NULL), | ||
| 670 | _OMAP4_BALLENTRY(MCSPI1_SOMI, "ae22", NULL), | ||
| 671 | _OMAP4_BALLENTRY(MCSPI1_SIMO, "ag22", NULL), | ||
| 672 | _OMAP4_BALLENTRY(MCSPI1_CS0, "ae23", NULL), | ||
| 673 | _OMAP4_BALLENTRY(MCSPI1_CS1, "af23", NULL), | ||
| 674 | _OMAP4_BALLENTRY(MCSPI1_CS2, "ag23", NULL), | ||
| 675 | _OMAP4_BALLENTRY(MCSPI1_CS3, "ah23", NULL), | ||
| 676 | _OMAP4_BALLENTRY(UART3_CTS_RCTX, "f27", NULL), | ||
| 677 | _OMAP4_BALLENTRY(UART3_RTS_SD, "f28", NULL), | ||
| 678 | _OMAP4_BALLENTRY(UART3_RX_IRRX, "g27", NULL), | ||
| 679 | _OMAP4_BALLENTRY(UART3_TX_IRTX, "g28", NULL), | ||
| 680 | _OMAP4_BALLENTRY(SDMMC5_CLK, "ae5", NULL), | ||
| 681 | _OMAP4_BALLENTRY(SDMMC5_CMD, "af5", NULL), | ||
| 682 | _OMAP4_BALLENTRY(SDMMC5_DAT0, "ae4", NULL), | ||
| 683 | _OMAP4_BALLENTRY(SDMMC5_DAT1, "af4", NULL), | ||
| 684 | _OMAP4_BALLENTRY(SDMMC5_DAT2, "ag3", NULL), | ||
| 685 | _OMAP4_BALLENTRY(SDMMC5_DAT3, "af3", NULL), | ||
| 686 | _OMAP4_BALLENTRY(MCSPI4_CLK, "ae21", NULL), | ||
| 687 | _OMAP4_BALLENTRY(MCSPI4_SIMO, "af20", NULL), | ||
| 688 | _OMAP4_BALLENTRY(MCSPI4_SOMI, "af21", NULL), | ||
| 689 | _OMAP4_BALLENTRY(MCSPI4_CS0, "ae20", NULL), | ||
| 690 | _OMAP4_BALLENTRY(UART4_RX, "ag20", NULL), | ||
| 691 | _OMAP4_BALLENTRY(UART4_TX, "ah19", NULL), | ||
| 692 | _OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, "ag12", NULL), | ||
| 693 | _OMAP4_BALLENTRY(USBB2_ULPITLL_STP, "af12", NULL), | ||
| 694 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, "ae12", NULL), | ||
| 695 | _OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, "ag13", NULL), | ||
| 696 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, "ae11", NULL), | ||
| 697 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, "af11", NULL), | ||
| 698 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, "ag11", NULL), | ||
| 699 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, "ah11", NULL), | ||
| 700 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, "ae10", NULL), | ||
| 701 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, "af10", NULL), | ||
| 702 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, "ag10", NULL), | ||
| 703 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, "ae9", NULL), | ||
| 704 | _OMAP4_BALLENTRY(USBB2_HSIC_DATA, "af13", NULL), | ||
| 705 | _OMAP4_BALLENTRY(USBB2_HSIC_STROBE, "ae13", NULL), | ||
| 706 | _OMAP4_BALLENTRY(UNIPRO_TX0, "g26", NULL), | ||
| 707 | _OMAP4_BALLENTRY(UNIPRO_TY0, "g25", NULL), | ||
| 708 | _OMAP4_BALLENTRY(UNIPRO_TX1, "h26", NULL), | ||
| 709 | _OMAP4_BALLENTRY(UNIPRO_TY1, "h25", NULL), | ||
| 710 | _OMAP4_BALLENTRY(UNIPRO_TX2, "j27", NULL), | ||
| 711 | _OMAP4_BALLENTRY(UNIPRO_TY2, "h27", NULL), | ||
| 712 | _OMAP4_BALLENTRY(UNIPRO_RX0, "j26", NULL), | ||
| 713 | _OMAP4_BALLENTRY(UNIPRO_RY0, "j25", NULL), | ||
| 714 | _OMAP4_BALLENTRY(UNIPRO_RX1, "k26", NULL), | ||
| 715 | _OMAP4_BALLENTRY(UNIPRO_RY1, "k25", NULL), | ||
| 716 | _OMAP4_BALLENTRY(UNIPRO_RX2, "l27", NULL), | ||
| 717 | _OMAP4_BALLENTRY(UNIPRO_RY2, "k27", NULL), | ||
| 718 | _OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL), | ||
| 719 | _OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL), | ||
| 720 | _OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL), | ||
| 721 | _OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL), | ||
| 722 | _OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL), | ||
| 723 | _OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL), | ||
| 724 | _OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL), | ||
| 725 | _OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL), | ||
| 726 | _OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL), | ||
| 727 | _OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL), | ||
| 728 | _OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL), | ||
| 729 | _OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL), | ||
| 730 | _OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL), | ||
| 731 | _OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL), | ||
| 732 | _OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL), | ||
| 733 | _OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL), | ||
| 734 | _OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL), | ||
| 735 | _OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL), | ||
| 736 | _OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL), | ||
| 737 | _OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL), | ||
| 738 | _OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL), | ||
| 739 | _OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL), | ||
| 740 | _OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL), | ||
| 741 | _OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL), | ||
| 742 | _OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL), | ||
| 743 | _OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL), | ||
| 744 | _OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL), | ||
| 745 | _OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL), | ||
| 746 | _OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL), | ||
| 747 | _OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL), | ||
| 748 | _OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL), | ||
| 749 | _OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL), | ||
| 750 | _OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL), | ||
| 751 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
| 752 | }; | ||
| 753 | #else | ||
| 754 | #define omap4_core_cbl_ball NULL | ||
| 755 | #endif | ||
| 756 | |||
| 757 | /* | ||
| 758 | * Superset of all mux modes for omap4 ES2.0 | ||
| 759 | */ | ||
| 760 | static struct omap_mux __initdata omap4_es2_core_muxmodes[] = { | ||
| 761 | _OMAP4_MUXENTRY(GPMC_AD0, 0, "gpmc_ad0", "sdmmc2_dat0", NULL, NULL, | ||
| 762 | NULL, NULL, NULL, NULL), | ||
| 763 | _OMAP4_MUXENTRY(GPMC_AD1, 0, "gpmc_ad1", "sdmmc2_dat1", NULL, NULL, | ||
| 764 | NULL, NULL, NULL, NULL), | ||
| 765 | _OMAP4_MUXENTRY(GPMC_AD2, 0, "gpmc_ad2", "sdmmc2_dat2", NULL, NULL, | ||
| 766 | NULL, NULL, NULL, NULL), | ||
| 767 | _OMAP4_MUXENTRY(GPMC_AD3, 0, "gpmc_ad3", "sdmmc2_dat3", NULL, NULL, | ||
| 768 | NULL, NULL, NULL, NULL), | ||
| 769 | _OMAP4_MUXENTRY(GPMC_AD4, 0, "gpmc_ad4", "sdmmc2_dat4", | ||
| 770 | "sdmmc2_dir_dat0", NULL, NULL, NULL, NULL, NULL), | ||
| 771 | _OMAP4_MUXENTRY(GPMC_AD5, 0, "gpmc_ad5", "sdmmc2_dat5", | ||
| 772 | "sdmmc2_dir_dat1", NULL, NULL, NULL, NULL, NULL), | ||
| 773 | _OMAP4_MUXENTRY(GPMC_AD6, 0, "gpmc_ad6", "sdmmc2_dat6", | ||
| 774 | "sdmmc2_dir_cmd", NULL, NULL, NULL, NULL, NULL), | ||
| 775 | _OMAP4_MUXENTRY(GPMC_AD7, 0, "gpmc_ad7", "sdmmc2_dat7", | ||
| 776 | "sdmmc2_clk_fdbk", NULL, NULL, NULL, NULL, NULL), | ||
| 777 | _OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15", | ||
| 778 | "gpio_32", NULL, "sdmmc1_dat0", NULL, NULL), | ||
| 779 | _OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14", | ||
| 780 | "gpio_33", NULL, "sdmmc1_dat1", NULL, NULL), | ||
| 781 | _OMAP4_MUXENTRY(GPMC_AD10, 34, "gpmc_ad10", "kpd_row2", "c2c_data13", | ||
| 782 | "gpio_34", NULL, "sdmmc1_dat2", NULL, NULL), | ||
| 783 | _OMAP4_MUXENTRY(GPMC_AD11, 35, "gpmc_ad11", "kpd_row3", "c2c_data12", | ||
| 784 | "gpio_35", NULL, "sdmmc1_dat3", NULL, NULL), | ||
| 785 | _OMAP4_MUXENTRY(GPMC_AD12, 36, "gpmc_ad12", "kpd_col0", "c2c_data11", | ||
| 786 | "gpio_36", NULL, "sdmmc1_dat4", NULL, NULL), | ||
| 787 | _OMAP4_MUXENTRY(GPMC_AD13, 37, "gpmc_ad13", "kpd_col1", "c2c_data10", | ||
| 788 | "gpio_37", NULL, "sdmmc1_dat5", NULL, NULL), | ||
| 789 | _OMAP4_MUXENTRY(GPMC_AD14, 38, "gpmc_ad14", "kpd_col2", "c2c_data9", | ||
| 790 | "gpio_38", NULL, "sdmmc1_dat6", NULL, NULL), | ||
| 791 | _OMAP4_MUXENTRY(GPMC_AD15, 39, "gpmc_ad15", "kpd_col3", "c2c_data8", | ||
| 792 | "gpio_39", NULL, "sdmmc1_dat7", NULL, NULL), | ||
| 793 | _OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0", | ||
| 794 | "gpio_40", "venc_656_data0", NULL, NULL, "safe_mode"), | ||
| 795 | _OMAP4_MUXENTRY(GPMC_A17, 41, "gpmc_a17", "kpd_row5", "c2c_datain1", | ||
| 796 | "gpio_41", "venc_656_data1", NULL, NULL, "safe_mode"), | ||
| 797 | _OMAP4_MUXENTRY(GPMC_A18, 42, "gpmc_a18", "kpd_row6", "c2c_datain2", | ||
| 798 | "gpio_42", "venc_656_data2", NULL, NULL, "safe_mode"), | ||
| 799 | _OMAP4_MUXENTRY(GPMC_A19, 43, "gpmc_a19", "kpd_row7", "c2c_datain3", | ||
| 800 | "gpio_43", "venc_656_data3", NULL, NULL, "safe_mode"), | ||
| 801 | _OMAP4_MUXENTRY(GPMC_A20, 44, "gpmc_a20", "kpd_col4", "c2c_datain4", | ||
| 802 | "gpio_44", "venc_656_data4", NULL, NULL, "safe_mode"), | ||
| 803 | _OMAP4_MUXENTRY(GPMC_A21, 45, "gpmc_a21", "kpd_col5", "c2c_datain5", | ||
| 804 | "gpio_45", "venc_656_data5", NULL, NULL, "safe_mode"), | ||
| 805 | _OMAP4_MUXENTRY(GPMC_A22, 46, "gpmc_a22", "kpd_col6", "c2c_datain6", | ||
| 806 | "gpio_46", "venc_656_data6", NULL, NULL, "safe_mode"), | ||
| 807 | _OMAP4_MUXENTRY(GPMC_A23, 47, "gpmc_a23", "kpd_col7", "c2c_datain7", | ||
| 808 | "gpio_47", "venc_656_data7", NULL, NULL, "safe_mode"), | ||
| 809 | _OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", "kpd_col8", "c2c_clkout0", | ||
| 810 | "gpio_48", NULL, NULL, NULL, "safe_mode"), | ||
| 811 | _OMAP4_MUXENTRY(GPMC_A25, 49, "gpmc_a25", NULL, "c2c_clkout1", | ||
| 812 | "gpio_49", NULL, NULL, NULL, "safe_mode"), | ||
| 813 | _OMAP4_MUXENTRY(GPMC_NCS0, 50, "gpmc_ncs0", NULL, NULL, "gpio_50", | ||
| 814 | "sys_ndmareq0", NULL, NULL, NULL), | ||
| 815 | _OMAP4_MUXENTRY(GPMC_NCS1, 51, "gpmc_ncs1", NULL, "c2c_dataout6", | ||
| 816 | "gpio_51", NULL, NULL, NULL, "safe_mode"), | ||
| 817 | _OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", "kpd_row8", | ||
| 818 | "c2c_dataout7", "gpio_52", NULL, NULL, NULL, | ||
| 819 | "safe_mode"), | ||
| 820 | _OMAP4_MUXENTRY(GPMC_NCS3, 53, "gpmc_ncs3", "gpmc_dir", | ||
| 821 | "c2c_dataout4", "gpio_53", NULL, NULL, NULL, | ||
| 822 | "safe_mode"), | ||
| 823 | _OMAP4_MUXENTRY(GPMC_NWP, 54, "gpmc_nwp", "dsi1_te0", NULL, "gpio_54", | ||
| 824 | "sys_ndmareq1", NULL, NULL, NULL), | ||
| 825 | _OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55", | ||
| 826 | "sys_ndmareq2", "sdmmc1_cmd", NULL, NULL), | ||
| 827 | _OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL, | ||
| 828 | "gpio_56", "sys_ndmareq3", "sdmmc1_clk", NULL, NULL), | ||
| 829 | _OMAP4_MUXENTRY(GPMC_NOE, 0, "gpmc_noe", "sdmmc2_clk", NULL, NULL, | ||
| 830 | NULL, NULL, NULL, NULL), | ||
| 831 | _OMAP4_MUXENTRY(GPMC_NWE, 0, "gpmc_nwe", "sdmmc2_cmd", NULL, NULL, | ||
| 832 | NULL, NULL, NULL, NULL), | ||
| 833 | _OMAP4_MUXENTRY(GPMC_NBE0_CLE, 59, "gpmc_nbe0_cle", "dsi2_te0", NULL, | ||
| 834 | "gpio_59", NULL, NULL, NULL, NULL), | ||
| 835 | _OMAP4_MUXENTRY(GPMC_NBE1, 60, "gpmc_nbe1", NULL, "c2c_dataout5", | ||
| 836 | "gpio_60", NULL, NULL, NULL, "safe_mode"), | ||
| 837 | _OMAP4_MUXENTRY(GPMC_WAIT0, 61, "gpmc_wait0", "dsi2_te1", NULL, | ||
| 838 | "gpio_61", NULL, NULL, NULL, NULL), | ||
| 839 | _OMAP4_MUXENTRY(GPMC_WAIT1, 62, "gpmc_wait1", NULL, "c2c_dataout2", | ||
| 840 | "gpio_62", NULL, NULL, NULL, "safe_mode"), | ||
| 841 | _OMAP4_MUXENTRY(GPMC_WAIT2, 100, "gpmc_wait2", "usbc1_icusb_txen", | ||
| 842 | "c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL, | ||
| 843 | NULL, "safe_mode"), | ||
| 844 | _OMAP4_MUXENTRY(GPMC_NCS4, 101, "gpmc_ncs4", "dsi1_te0", "c2c_clkin0", | ||
| 845 | "gpio_101", "sys_ndmareq1", NULL, NULL, "safe_mode"), | ||
| 846 | _OMAP4_MUXENTRY(GPMC_NCS5, 102, "gpmc_ncs5", "dsi1_te1", "c2c_clkin1", | ||
| 847 | "gpio_102", "sys_ndmareq2", NULL, NULL, "safe_mode"), | ||
| 848 | _OMAP4_MUXENTRY(GPMC_NCS6, 103, "gpmc_ncs6", "dsi2_te0", | ||
| 849 | "c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL, | ||
| 850 | NULL, "safe_mode"), | ||
| 851 | _OMAP4_MUXENTRY(GPMC_NCS7, 104, "gpmc_ncs7", "dsi2_te1", | ||
| 852 | "c2c_dataout1", "gpio_104", NULL, NULL, NULL, | ||
| 853 | "safe_mode"), | ||
| 854 | _OMAP4_MUXENTRY(HDMI_HPD, 63, "hdmi_hpd", NULL, NULL, "gpio_63", NULL, | ||
| 855 | NULL, NULL, "safe_mode"), | ||
| 856 | _OMAP4_MUXENTRY(HDMI_CEC, 64, "hdmi_cec", NULL, NULL, "gpio_64", NULL, | ||
| 857 | NULL, NULL, "safe_mode"), | ||
| 858 | _OMAP4_MUXENTRY(HDMI_DDC_SCL, 65, "hdmi_ddc_scl", NULL, NULL, | ||
| 859 | "gpio_65", NULL, NULL, NULL, "safe_mode"), | ||
| 860 | _OMAP4_MUXENTRY(HDMI_DDC_SDA, 66, "hdmi_ddc_sda", NULL, NULL, | ||
| 861 | "gpio_66", NULL, NULL, NULL, "safe_mode"), | ||
| 862 | _OMAP4_MUXENTRY(CSI21_DX0, 0, "csi21_dx0", NULL, NULL, "gpi_67", NULL, | ||
| 863 | NULL, NULL, "safe_mode"), | ||
| 864 | _OMAP4_MUXENTRY(CSI21_DY0, 0, "csi21_dy0", NULL, NULL, "gpi_68", NULL, | ||
| 865 | NULL, NULL, "safe_mode"), | ||
| 866 | _OMAP4_MUXENTRY(CSI21_DX1, 0, "csi21_dx1", NULL, NULL, "gpi_69", NULL, | ||
| 867 | NULL, NULL, "safe_mode"), | ||
| 868 | _OMAP4_MUXENTRY(CSI21_DY1, 0, "csi21_dy1", NULL, NULL, "gpi_70", NULL, | ||
| 869 | NULL, NULL, "safe_mode"), | ||
| 870 | _OMAP4_MUXENTRY(CSI21_DX2, 0, "csi21_dx2", NULL, NULL, "gpi_71", NULL, | ||
| 871 | NULL, NULL, "safe_mode"), | ||
| 872 | _OMAP4_MUXENTRY(CSI21_DY2, 0, "csi21_dy2", NULL, NULL, "gpi_72", NULL, | ||
| 873 | NULL, NULL, "safe_mode"), | ||
| 874 | _OMAP4_MUXENTRY(CSI21_DX3, 0, "csi21_dx3", NULL, NULL, "gpi_73", NULL, | ||
| 875 | NULL, NULL, "safe_mode"), | ||
| 876 | _OMAP4_MUXENTRY(CSI21_DY3, 0, "csi21_dy3", NULL, NULL, "gpi_74", NULL, | ||
| 877 | NULL, NULL, "safe_mode"), | ||
| 878 | _OMAP4_MUXENTRY(CSI21_DX4, 0, "csi21_dx4", NULL, NULL, "gpi_75", NULL, | ||
| 879 | NULL, NULL, "safe_mode"), | ||
| 880 | _OMAP4_MUXENTRY(CSI21_DY4, 0, "csi21_dy4", NULL, NULL, "gpi_76", NULL, | ||
| 881 | NULL, NULL, "safe_mode"), | ||
| 882 | _OMAP4_MUXENTRY(CSI22_DX0, 0, "csi22_dx0", NULL, NULL, "gpi_77", NULL, | ||
| 883 | NULL, NULL, "safe_mode"), | ||
| 884 | _OMAP4_MUXENTRY(CSI22_DY0, 0, "csi22_dy0", NULL, NULL, "gpi_78", NULL, | ||
| 885 | NULL, NULL, "safe_mode"), | ||
| 886 | _OMAP4_MUXENTRY(CSI22_DX1, 0, "csi22_dx1", NULL, NULL, "gpi_79", NULL, | ||
| 887 | NULL, NULL, "safe_mode"), | ||
| 888 | _OMAP4_MUXENTRY(CSI22_DY1, 0, "csi22_dy1", NULL, NULL, "gpi_80", NULL, | ||
| 889 | NULL, NULL, "safe_mode"), | ||
| 890 | _OMAP4_MUXENTRY(CAM_SHUTTER, 81, "cam_shutter", NULL, NULL, "gpio_81", | ||
| 891 | NULL, NULL, NULL, "safe_mode"), | ||
| 892 | _OMAP4_MUXENTRY(CAM_STROBE, 82, "cam_strobe", NULL, NULL, "gpio_82", | ||
| 893 | NULL, NULL, NULL, "safe_mode"), | ||
| 894 | _OMAP4_MUXENTRY(CAM_GLOBALRESET, 83, "cam_globalreset", NULL, NULL, | ||
| 895 | "gpio_83", NULL, NULL, NULL, "safe_mode"), | ||
| 896 | _OMAP4_MUXENTRY(USBB1_ULPITLL_CLK, 84, "usbb1_ulpitll_clk", | ||
| 897 | "hsi1_cawake", NULL, "gpio_84", "usbb1_ulpiphy_clk", | ||
| 898 | NULL, "hw_dbg20", "safe_mode"), | ||
| 899 | _OMAP4_MUXENTRY(USBB1_ULPITLL_STP, 85, "usbb1_ulpitll_stp", | ||
| 900 | "hsi1_cadata", "mcbsp4_clkr", "gpio_85", | ||
| 901 | "usbb1_ulpiphy_stp", "usbb1_mm_rxdp", "hw_dbg21", | ||
| 902 | "safe_mode"), | ||
| 903 | _OMAP4_MUXENTRY(USBB1_ULPITLL_DIR, 86, "usbb1_ulpitll_dir", | ||
| 904 | "hsi1_caflag", "mcbsp4_fsr", "gpio_86", | ||
| 905 | "usbb1_ulpiphy_dir", NULL, "hw_dbg22", "safe_mode"), | ||
| 906 | _OMAP4_MUXENTRY(USBB1_ULPITLL_NXT, 87, "usbb1_ulpitll_nxt", | ||
| 907 | "hsi1_acready", "mcbsp4_fsx", "gpio_87", | ||
| 908 | "usbb1_ulpiphy_nxt", "usbb1_mm_rxdm", "hw_dbg23", | ||
| 909 | "safe_mode"), | ||
| 910 | _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0", | ||
| 911 | "hsi1_acwake", "mcbsp4_clkx", "gpio_88", | ||
| 912 | "usbb1_ulpiphy_dat0", "usbb1_mm_txen", "hw_dbg24", | ||
| 913 | "safe_mode"), | ||
| 914 | _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, 89, "usbb1_ulpitll_dat1", | ||
| 915 | "hsi1_acdata", "mcbsp4_dx", "gpio_89", | ||
| 916 | "usbb1_ulpiphy_dat1", "usbb1_mm_txdat", "hw_dbg25", | ||
| 917 | "safe_mode"), | ||
| 918 | _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, 90, "usbb1_ulpitll_dat2", | ||
| 919 | "hsi1_acflag", "mcbsp4_dr", "gpio_90", | ||
| 920 | "usbb1_ulpiphy_dat2", "usbb1_mm_txse0", "hw_dbg26", | ||
| 921 | "safe_mode"), | ||
| 922 | _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3", | ||
| 923 | "hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3", | ||
| 924 | "usbb1_mm_rxrcv", "hw_dbg27", "safe_mode"), | ||
| 925 | _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT4, 92, "usbb1_ulpitll_dat4", | ||
| 926 | "dmtimer8_pwm_evt", "abe_mcbsp3_dr", "gpio_92", | ||
| 927 | "usbb1_ulpiphy_dat4", NULL, "hw_dbg28", "safe_mode"), | ||
| 928 | _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT5, 93, "usbb1_ulpitll_dat5", | ||
| 929 | "dmtimer9_pwm_evt", "abe_mcbsp3_dx", "gpio_93", | ||
| 930 | "usbb1_ulpiphy_dat5", NULL, "hw_dbg29", "safe_mode"), | ||
| 931 | _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT6, 94, "usbb1_ulpitll_dat6", | ||
| 932 | "dmtimer10_pwm_evt", "abe_mcbsp3_clkx", "gpio_94", | ||
| 933 | "usbb1_ulpiphy_dat6", "abe_dmic_din3", "hw_dbg30", | ||
| 934 | "safe_mode"), | ||
| 935 | _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT7, 95, "usbb1_ulpitll_dat7", | ||
| 936 | "dmtimer11_pwm_evt", "abe_mcbsp3_fsx", "gpio_95", | ||
| 937 | "usbb1_ulpiphy_dat7", "abe_dmic_clk3", "hw_dbg31", | ||
| 938 | "safe_mode"), | ||
| 939 | _OMAP4_MUXENTRY(USBB1_HSIC_DATA, 96, "usbb1_hsic_data", NULL, NULL, | ||
| 940 | "gpio_96", NULL, NULL, NULL, "safe_mode"), | ||
| 941 | _OMAP4_MUXENTRY(USBB1_HSIC_STROBE, 97, "usbb1_hsic_strobe", NULL, | ||
| 942 | NULL, "gpio_97", NULL, NULL, NULL, "safe_mode"), | ||
| 943 | _OMAP4_MUXENTRY(USBC1_ICUSB_DP, 98, "usbc1_icusb_dp", NULL, NULL, | ||
| 944 | "gpio_98", NULL, NULL, NULL, "safe_mode"), | ||
| 945 | _OMAP4_MUXENTRY(USBC1_ICUSB_DM, 99, "usbc1_icusb_dm", NULL, NULL, | ||
| 946 | "gpio_99", NULL, NULL, NULL, "safe_mode"), | ||
| 947 | _OMAP4_MUXENTRY(SDMMC1_CLK, 100, "sdmmc1_clk", NULL, "dpm_emu19", | ||
| 948 | "gpio_100", NULL, NULL, NULL, "safe_mode"), | ||
| 949 | _OMAP4_MUXENTRY(SDMMC1_CMD, 101, "sdmmc1_cmd", NULL, "uart1_rx", | ||
| 950 | "gpio_101", NULL, NULL, NULL, "safe_mode"), | ||
| 951 | _OMAP4_MUXENTRY(SDMMC1_DAT0, 102, "sdmmc1_dat0", NULL, "dpm_emu18", | ||
| 952 | "gpio_102", NULL, NULL, NULL, "safe_mode"), | ||
| 953 | _OMAP4_MUXENTRY(SDMMC1_DAT1, 103, "sdmmc1_dat1", NULL, "dpm_emu17", | ||
| 954 | "gpio_103", NULL, NULL, NULL, "safe_mode"), | ||
| 955 | _OMAP4_MUXENTRY(SDMMC1_DAT2, 104, "sdmmc1_dat2", NULL, "dpm_emu16", | ||
| 956 | "gpio_104", "jtag_tms_tmsc", NULL, NULL, "safe_mode"), | ||
| 957 | _OMAP4_MUXENTRY(SDMMC1_DAT3, 105, "sdmmc1_dat3", NULL, "dpm_emu15", | ||
| 958 | "gpio_105", "jtag_tck", NULL, NULL, "safe_mode"), | ||
| 959 | _OMAP4_MUXENTRY(SDMMC1_DAT4, 106, "sdmmc1_dat4", NULL, NULL, | ||
| 960 | "gpio_106", NULL, NULL, NULL, "safe_mode"), | ||
| 961 | _OMAP4_MUXENTRY(SDMMC1_DAT5, 107, "sdmmc1_dat5", NULL, NULL, | ||
| 962 | "gpio_107", NULL, NULL, NULL, "safe_mode"), | ||
| 963 | _OMAP4_MUXENTRY(SDMMC1_DAT6, 108, "sdmmc1_dat6", NULL, NULL, | ||
| 964 | "gpio_108", NULL, NULL, NULL, "safe_mode"), | ||
| 965 | _OMAP4_MUXENTRY(SDMMC1_DAT7, 109, "sdmmc1_dat7", NULL, NULL, | ||
| 966 | "gpio_109", NULL, NULL, NULL, "safe_mode"), | ||
| 967 | _OMAP4_MUXENTRY(ABE_MCBSP2_CLKX, 110, "abe_mcbsp2_clkx", "mcspi2_clk", | ||
| 968 | "abe_mcasp_ahclkx", "gpio_110", "usbb2_mm_rxdm", | ||
| 969 | NULL, NULL, "safe_mode"), | ||
| 970 | _OMAP4_MUXENTRY(ABE_MCBSP2_DR, 111, "abe_mcbsp2_dr", "mcspi2_somi", | ||
| 971 | "abe_mcasp_axr", "gpio_111", "usbb2_mm_rxdp", NULL, | ||
| 972 | NULL, "safe_mode"), | ||
| 973 | _OMAP4_MUXENTRY(ABE_MCBSP2_DX, 112, "abe_mcbsp2_dx", "mcspi2_simo", | ||
| 974 | "abe_mcasp_amute", "gpio_112", "usbb2_mm_rxrcv", NULL, | ||
| 975 | NULL, "safe_mode"), | ||
| 976 | _OMAP4_MUXENTRY(ABE_MCBSP2_FSX, 113, "abe_mcbsp2_fsx", "mcspi2_cs0", | ||
| 977 | "abe_mcasp_afsx", "gpio_113", "usbb2_mm_txen", NULL, | ||
| 978 | NULL, "safe_mode"), | ||
| 979 | _OMAP4_MUXENTRY(ABE_MCBSP1_CLKX, 114, "abe_mcbsp1_clkx", | ||
| 980 | "abe_slimbus1_clock", NULL, "gpio_114", NULL, NULL, | ||
| 981 | NULL, "safe_mode"), | ||
| 982 | _OMAP4_MUXENTRY(ABE_MCBSP1_DR, 115, "abe_mcbsp1_dr", | ||
| 983 | "abe_slimbus1_data", NULL, "gpio_115", NULL, NULL, | ||
| 984 | NULL, "safe_mode"), | ||
| 985 | _OMAP4_MUXENTRY(ABE_MCBSP1_DX, 116, "abe_mcbsp1_dx", "sdmmc3_dat2", | ||
| 986 | "abe_mcasp_aclkx", "gpio_116", NULL, NULL, NULL, | ||
| 987 | "safe_mode"), | ||
| 988 | _OMAP4_MUXENTRY(ABE_MCBSP1_FSX, 117, "abe_mcbsp1_fsx", "sdmmc3_dat3", | ||
| 989 | "abe_mcasp_amutein", "gpio_117", NULL, NULL, NULL, | ||
| 990 | "safe_mode"), | ||
| 991 | _OMAP4_MUXENTRY(ABE_PDM_UL_DATA, 0, "abe_pdm_ul_data", | ||
| 992 | "abe_mcbsp3_dr", NULL, NULL, NULL, NULL, NULL, | ||
| 993 | "safe_mode"), | ||
| 994 | _OMAP4_MUXENTRY(ABE_PDM_DL_DATA, 0, "abe_pdm_dl_data", | ||
| 995 | "abe_mcbsp3_dx", NULL, NULL, NULL, NULL, NULL, | ||
| 996 | "safe_mode"), | ||
| 997 | _OMAP4_MUXENTRY(ABE_PDM_FRAME, 0, "abe_pdm_frame", "abe_mcbsp3_clkx", | ||
| 998 | NULL, NULL, NULL, NULL, NULL, "safe_mode"), | ||
| 999 | _OMAP4_MUXENTRY(ABE_PDM_LB_CLK, 0, "abe_pdm_lb_clk", "abe_mcbsp3_fsx", | ||
| 1000 | NULL, NULL, NULL, NULL, NULL, "safe_mode"), | ||
| 1001 | _OMAP4_MUXENTRY(ABE_CLKS, 118, "abe_clks", NULL, NULL, "gpio_118", | ||
| 1002 | NULL, NULL, NULL, "safe_mode"), | ||
| 1003 | _OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL, | ||
| 1004 | "gpio_119", "usbb2_mm_txse0", "uart4_cts", NULL, | ||
| 1005 | "safe_mode"), | ||
| 1006 | _OMAP4_MUXENTRY(ABE_DMIC_DIN1, 120, "abe_dmic_din1", NULL, NULL, | ||
| 1007 | "gpio_120", "usbb2_mm_txdat", "uart4_rts", NULL, | ||
| 1008 | "safe_mode"), | ||
| 1009 | _OMAP4_MUXENTRY(ABE_DMIC_DIN2, 121, "abe_dmic_din2", "slimbus2_clock", | ||
| 1010 | "abe_mcasp_axr", "gpio_121", NULL, | ||
| 1011 | "dmtimer11_pwm_evt", NULL, "safe_mode"), | ||
| 1012 | _OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data", | ||
| 1013 | "abe_dmic_clk2", "gpio_122", NULL, "dmtimer9_pwm_evt", | ||
| 1014 | NULL, "safe_mode"), | ||
| 1015 | _OMAP4_MUXENTRY(UART2_CTS, 123, "uart2_cts", "sdmmc3_clk", NULL, | ||
| 1016 | "gpio_123", NULL, NULL, NULL, "safe_mode"), | ||
| 1017 | _OMAP4_MUXENTRY(UART2_RTS, 124, "uart2_rts", "sdmmc3_cmd", NULL, | ||
| 1018 | "gpio_124", NULL, NULL, NULL, "safe_mode"), | ||
| 1019 | _OMAP4_MUXENTRY(UART2_RX, 125, "uart2_rx", "sdmmc3_dat0", NULL, | ||
| 1020 | "gpio_125", NULL, NULL, NULL, "safe_mode"), | ||
| 1021 | _OMAP4_MUXENTRY(UART2_TX, 126, "uart2_tx", "sdmmc3_dat1", NULL, | ||
| 1022 | "gpio_126", NULL, NULL, NULL, "safe_mode"), | ||
| 1023 | _OMAP4_MUXENTRY(HDQ_SIO, 127, "hdq_sio", "i2c3_sccb", "i2c2_sccb", | ||
| 1024 | "gpio_127", NULL, NULL, NULL, "safe_mode"), | ||
| 1025 | _OMAP4_MUXENTRY(I2C1_SCL, 0, "i2c1_scl", NULL, NULL, NULL, NULL, NULL, | ||
| 1026 | NULL, NULL), | ||
| 1027 | _OMAP4_MUXENTRY(I2C1_SDA, 0, "i2c1_sda", NULL, NULL, NULL, NULL, NULL, | ||
| 1028 | NULL, NULL), | ||
| 1029 | _OMAP4_MUXENTRY(I2C2_SCL, 128, "i2c2_scl", "uart1_rx", NULL, | ||
| 1030 | "gpio_128", NULL, NULL, NULL, "safe_mode"), | ||
| 1031 | _OMAP4_MUXENTRY(I2C2_SDA, 129, "i2c2_sda", "uart1_tx", NULL, | ||
| 1032 | "gpio_129", NULL, NULL, NULL, "safe_mode"), | ||
| 1033 | _OMAP4_MUXENTRY(I2C3_SCL, 130, "i2c3_scl", NULL, NULL, "gpio_130", | ||
| 1034 | NULL, NULL, NULL, "safe_mode"), | ||
| 1035 | _OMAP4_MUXENTRY(I2C3_SDA, 131, "i2c3_sda", NULL, NULL, "gpio_131", | ||
| 1036 | NULL, NULL, NULL, "safe_mode"), | ||
| 1037 | _OMAP4_MUXENTRY(I2C4_SCL, 132, "i2c4_scl", NULL, NULL, "gpio_132", | ||
| 1038 | NULL, NULL, NULL, "safe_mode"), | ||
| 1039 | _OMAP4_MUXENTRY(I2C4_SDA, 133, "i2c4_sda", NULL, NULL, "gpio_133", | ||
| 1040 | NULL, NULL, NULL, "safe_mode"), | ||
| 1041 | _OMAP4_MUXENTRY(MCSPI1_CLK, 134, "mcspi1_clk", NULL, NULL, "gpio_134", | ||
| 1042 | NULL, NULL, NULL, "safe_mode"), | ||
| 1043 | _OMAP4_MUXENTRY(MCSPI1_SOMI, 135, "mcspi1_somi", NULL, NULL, | ||
| 1044 | "gpio_135", NULL, NULL, NULL, "safe_mode"), | ||
| 1045 | _OMAP4_MUXENTRY(MCSPI1_SIMO, 136, "mcspi1_simo", NULL, NULL, | ||
| 1046 | "gpio_136", NULL, NULL, NULL, "safe_mode"), | ||
| 1047 | _OMAP4_MUXENTRY(MCSPI1_CS0, 137, "mcspi1_cs0", NULL, NULL, "gpio_137", | ||
| 1048 | NULL, NULL, NULL, "safe_mode"), | ||
| 1049 | _OMAP4_MUXENTRY(MCSPI1_CS1, 138, "mcspi1_cs1", "uart1_rx", NULL, | ||
| 1050 | "gpio_138", NULL, NULL, NULL, "safe_mode"), | ||
| 1051 | _OMAP4_MUXENTRY(MCSPI1_CS2, 139, "mcspi1_cs2", "uart1_cts", | ||
| 1052 | "slimbus2_clock", "gpio_139", NULL, NULL, NULL, | ||
| 1053 | "safe_mode"), | ||
| 1054 | _OMAP4_MUXENTRY(MCSPI1_CS3, 140, "mcspi1_cs3", "uart1_rts", | ||
| 1055 | "slimbus2_data", "gpio_140", NULL, NULL, NULL, | ||
| 1056 | "safe_mode"), | ||
| 1057 | _OMAP4_MUXENTRY(UART3_CTS_RCTX, 141, "uart3_cts_rctx", "uart1_tx", | ||
| 1058 | NULL, "gpio_141", NULL, NULL, NULL, "safe_mode"), | ||
| 1059 | _OMAP4_MUXENTRY(UART3_RTS_SD, 142, "uart3_rts_sd", NULL, NULL, | ||
| 1060 | "gpio_142", NULL, NULL, NULL, "safe_mode"), | ||
| 1061 | _OMAP4_MUXENTRY(UART3_RX_IRRX, 143, "uart3_rx_irrx", | ||
| 1062 | "dmtimer8_pwm_evt", NULL, "gpio_143", NULL, NULL, | ||
| 1063 | NULL, "safe_mode"), | ||
| 1064 | _OMAP4_MUXENTRY(UART3_TX_IRTX, 144, "uart3_tx_irtx", | ||
| 1065 | "dmtimer9_pwm_evt", NULL, "gpio_144", NULL, NULL, | ||
| 1066 | NULL, "safe_mode"), | ||
| 1067 | _OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk", | ||
| 1068 | "usbc1_icusb_dp", "gpio_145", NULL, "sdmmc2_clk", | ||
| 1069 | NULL, "safe_mode"), | ||
| 1070 | _OMAP4_MUXENTRY(SDMMC5_CMD, 146, "sdmmc5_cmd", "mcspi2_simo", | ||
| 1071 | "usbc1_icusb_dm", "gpio_146", NULL, "sdmmc2_cmd", | ||
| 1072 | NULL, "safe_mode"), | ||
| 1073 | _OMAP4_MUXENTRY(SDMMC5_DAT0, 147, "sdmmc5_dat0", "mcspi2_somi", | ||
| 1074 | "usbc1_icusb_rcv", "gpio_147", NULL, "sdmmc2_dat0", | ||
| 1075 | NULL, "safe_mode"), | ||
| 1076 | _OMAP4_MUXENTRY(SDMMC5_DAT1, 148, "sdmmc5_dat1", NULL, | ||
| 1077 | "usbc1_icusb_txen", "gpio_148", NULL, "sdmmc2_dat1", | ||
| 1078 | NULL, "safe_mode"), | ||
| 1079 | _OMAP4_MUXENTRY(SDMMC5_DAT2, 149, "sdmmc5_dat2", "mcspi2_cs1", NULL, | ||
| 1080 | "gpio_149", NULL, "sdmmc2_dat2", NULL, "safe_mode"), | ||
| 1081 | _OMAP4_MUXENTRY(SDMMC5_DAT3, 150, "sdmmc5_dat3", "mcspi2_cs0", NULL, | ||
| 1082 | "gpio_150", NULL, "sdmmc2_dat3", NULL, "safe_mode"), | ||
| 1083 | _OMAP4_MUXENTRY(MCSPI4_CLK, 151, "mcspi4_clk", "sdmmc4_clk", | ||
| 1084 | "kpd_col6", "gpio_151", NULL, NULL, NULL, | ||
| 1085 | "safe_mode"), | ||
| 1086 | _OMAP4_MUXENTRY(MCSPI4_SIMO, 152, "mcspi4_simo", "sdmmc4_cmd", | ||
| 1087 | "kpd_col7", "gpio_152", NULL, NULL, NULL, | ||
| 1088 | "safe_mode"), | ||
| 1089 | _OMAP4_MUXENTRY(MCSPI4_SOMI, 153, "mcspi4_somi", "sdmmc4_dat0", | ||
| 1090 | "kpd_row6", "gpio_153", NULL, NULL, NULL, | ||
| 1091 | "safe_mode"), | ||
| 1092 | _OMAP4_MUXENTRY(MCSPI4_CS0, 154, "mcspi4_cs0", "sdmmc4_dat3", | ||
| 1093 | "kpd_row7", "gpio_154", NULL, NULL, NULL, | ||
| 1094 | "safe_mode"), | ||
| 1095 | _OMAP4_MUXENTRY(UART4_RX, 155, "uart4_rx", "sdmmc4_dat2", "kpd_row8", | ||
| 1096 | "gpio_155", NULL, NULL, NULL, "safe_mode"), | ||
| 1097 | _OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", "kpd_col8", | ||
| 1098 | "gpio_156", NULL, NULL, NULL, "safe_mode"), | ||
| 1099 | _OMAP4_MUXENTRY(USBB2_ULPITLL_CLK, 157, "usbb2_ulpitll_clk", | ||
| 1100 | "usbb2_ulpiphy_clk", "sdmmc4_cmd", "gpio_157", | ||
| 1101 | "hsi2_cawake", NULL, NULL, "safe_mode"), | ||
| 1102 | _OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp", | ||
| 1103 | "usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158", | ||
| 1104 | "hsi2_cadata", "dispc2_data23", NULL, "safe_mode"), | ||
| 1105 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, 159, "usbb2_ulpitll_dir", | ||
| 1106 | "usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159", | ||
| 1107 | "hsi2_caflag", "dispc2_data22", NULL, "safe_mode"), | ||
| 1108 | _OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, 160, "usbb2_ulpitll_nxt", | ||
| 1109 | "usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160", | ||
| 1110 | "hsi2_acready", "dispc2_data21", NULL, "safe_mode"), | ||
| 1111 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, 161, "usbb2_ulpitll_dat0", | ||
| 1112 | "usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161", | ||
| 1113 | "hsi2_acwake", "dispc2_data20", "usbb2_mm_txen", | ||
| 1114 | "safe_mode"), | ||
| 1115 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, 162, "usbb2_ulpitll_dat1", | ||
| 1116 | "usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162", | ||
| 1117 | "hsi2_acdata", "dispc2_data19", "usbb2_mm_txdat", | ||
| 1118 | "safe_mode"), | ||
| 1119 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, 163, "usbb2_ulpitll_dat2", | ||
| 1120 | "usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163", | ||
| 1121 | "hsi2_acflag", "dispc2_data18", "usbb2_mm_txse0", | ||
| 1122 | "safe_mode"), | ||
| 1123 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, 164, "usbb2_ulpitll_dat3", | ||
| 1124 | "usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164", | ||
| 1125 | "hsi2_caready", "dispc2_data15", "rfbi_data15", | ||
| 1126 | "safe_mode"), | ||
| 1127 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, 165, "usbb2_ulpitll_dat4", | ||
| 1128 | "usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165", | ||
| 1129 | "mcspi3_somi", "dispc2_data14", "rfbi_data14", | ||
| 1130 | "safe_mode"), | ||
| 1131 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, 166, "usbb2_ulpitll_dat5", | ||
| 1132 | "usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166", | ||
| 1133 | "mcspi3_cs0", "dispc2_data13", "rfbi_data13", | ||
| 1134 | "safe_mode"), | ||
| 1135 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, 167, "usbb2_ulpitll_dat6", | ||
| 1136 | "usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167", | ||
| 1137 | "mcspi3_simo", "dispc2_data12", "rfbi_data12", | ||
| 1138 | "safe_mode"), | ||
| 1139 | _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, 168, "usbb2_ulpitll_dat7", | ||
| 1140 | "usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168", | ||
| 1141 | "mcspi3_clk", "dispc2_data11", "rfbi_data11", | ||
| 1142 | "safe_mode"), | ||
| 1143 | _OMAP4_MUXENTRY(USBB2_HSIC_DATA, 169, "usbb2_hsic_data", NULL, NULL, | ||
| 1144 | "gpio_169", NULL, NULL, NULL, "safe_mode"), | ||
| 1145 | _OMAP4_MUXENTRY(USBB2_HSIC_STROBE, 170, "usbb2_hsic_strobe", NULL, | ||
| 1146 | NULL, "gpio_170", NULL, NULL, NULL, "safe_mode"), | ||
| 1147 | _OMAP4_MUXENTRY(KPD_COL3, 171, "kpd_col3", "kpd_col0", NULL, | ||
| 1148 | "gpio_171", NULL, NULL, NULL, "safe_mode"), | ||
| 1149 | _OMAP4_MUXENTRY(KPD_COL4, 172, "kpd_col4", "kpd_col1", NULL, | ||
| 1150 | "gpio_172", NULL, NULL, NULL, "safe_mode"), | ||
| 1151 | _OMAP4_MUXENTRY(KPD_COL5, 173, "kpd_col5", "kpd_col2", NULL, | ||
| 1152 | "gpio_173", NULL, NULL, NULL, "safe_mode"), | ||
| 1153 | _OMAP4_MUXENTRY(KPD_COL0, 174, "kpd_col0", "kpd_col3", NULL, | ||
| 1154 | "gpio_174", NULL, NULL, NULL, "safe_mode"), | ||
| 1155 | _OMAP4_MUXENTRY(KPD_COL1, 0, "kpd_col1", "kpd_col4", NULL, "gpio_0", | ||
| 1156 | NULL, NULL, NULL, "safe_mode"), | ||
| 1157 | _OMAP4_MUXENTRY(KPD_COL2, 1, "kpd_col2", "kpd_col5", NULL, "gpio_1", | ||
| 1158 | NULL, NULL, NULL, "safe_mode"), | ||
| 1159 | _OMAP4_MUXENTRY(KPD_ROW3, 175, "kpd_row3", "kpd_row0", NULL, | ||
| 1160 | "gpio_175", NULL, NULL, NULL, "safe_mode"), | ||
| 1161 | _OMAP4_MUXENTRY(KPD_ROW4, 176, "kpd_row4", "kpd_row1", NULL, | ||
| 1162 | "gpio_176", NULL, NULL, NULL, "safe_mode"), | ||
| 1163 | _OMAP4_MUXENTRY(KPD_ROW5, 177, "kpd_row5", "kpd_row2", NULL, | ||
| 1164 | "gpio_177", NULL, NULL, NULL, "safe_mode"), | ||
| 1165 | _OMAP4_MUXENTRY(KPD_ROW0, 178, "kpd_row0", "kpd_row3", NULL, | ||
| 1166 | "gpio_178", NULL, NULL, NULL, "safe_mode"), | ||
| 1167 | _OMAP4_MUXENTRY(KPD_ROW1, 2, "kpd_row1", "kpd_row4", NULL, "gpio_2", | ||
| 1168 | NULL, NULL, NULL, "safe_mode"), | ||
| 1169 | _OMAP4_MUXENTRY(KPD_ROW2, 3, "kpd_row2", "kpd_row5", NULL, "gpio_3", | ||
| 1170 | NULL, NULL, NULL, "safe_mode"), | ||
| 1171 | _OMAP4_MUXENTRY(USBA0_OTG_CE, 0, "usba0_otg_ce", NULL, NULL, NULL, | ||
| 1172 | NULL, NULL, NULL, NULL), | ||
| 1173 | _OMAP4_MUXENTRY(USBA0_OTG_DP, 0, "usba0_otg_dp", "uart3_rx_irrx", | ||
| 1174 | "uart2_rx", NULL, NULL, NULL, NULL, "safe_mode"), | ||
| 1175 | _OMAP4_MUXENTRY(USBA0_OTG_DM, 0, "usba0_otg_dm", "uart3_tx_irtx", | ||
| 1176 | "uart2_tx", NULL, NULL, NULL, NULL, "safe_mode"), | ||
| 1177 | _OMAP4_MUXENTRY(FREF_CLK1_OUT, 181, "fref_clk1_out", NULL, NULL, | ||
| 1178 | "gpio_181", NULL, NULL, NULL, "safe_mode"), | ||
| 1179 | _OMAP4_MUXENTRY(FREF_CLK2_OUT, 182, "fref_clk2_out", NULL, NULL, | ||
| 1180 | "gpio_182", NULL, NULL, NULL, "safe_mode"), | ||
| 1181 | _OMAP4_MUXENTRY(SYS_NIRQ1, 0, "sys_nirq1", NULL, NULL, NULL, NULL, | ||
| 1182 | NULL, NULL, "safe_mode"), | ||
| 1183 | _OMAP4_MUXENTRY(SYS_NIRQ2, 183, "sys_nirq2", NULL, NULL, "gpio_183", | ||
| 1184 | NULL, NULL, NULL, "safe_mode"), | ||
| 1185 | _OMAP4_MUXENTRY(SYS_BOOT0, 184, "sys_boot0", NULL, NULL, "gpio_184", | ||
| 1186 | NULL, NULL, NULL, "safe_mode"), | ||
| 1187 | _OMAP4_MUXENTRY(SYS_BOOT1, 185, "sys_boot1", NULL, NULL, "gpio_185", | ||
| 1188 | NULL, NULL, NULL, "safe_mode"), | ||
| 1189 | _OMAP4_MUXENTRY(SYS_BOOT2, 186, "sys_boot2", NULL, NULL, "gpio_186", | ||
| 1190 | NULL, NULL, NULL, "safe_mode"), | ||
| 1191 | _OMAP4_MUXENTRY(SYS_BOOT3, 187, "sys_boot3", NULL, NULL, "gpio_187", | ||
| 1192 | NULL, NULL, NULL, "safe_mode"), | ||
| 1193 | _OMAP4_MUXENTRY(SYS_BOOT4, 188, "sys_boot4", NULL, NULL, "gpio_188", | ||
| 1194 | NULL, NULL, NULL, "safe_mode"), | ||
| 1195 | _OMAP4_MUXENTRY(SYS_BOOT5, 189, "sys_boot5", NULL, NULL, "gpio_189", | ||
| 1196 | NULL, NULL, NULL, "safe_mode"), | ||
| 1197 | _OMAP4_MUXENTRY(DPM_EMU0, 11, "dpm_emu0", NULL, NULL, "gpio_11", NULL, | ||
| 1198 | NULL, "hw_dbg0", "safe_mode"), | ||
| 1199 | _OMAP4_MUXENTRY(DPM_EMU1, 12, "dpm_emu1", NULL, NULL, "gpio_12", NULL, | ||
| 1200 | NULL, "hw_dbg1", "safe_mode"), | ||
| 1201 | _OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL, | ||
| 1202 | "gpio_13", NULL, "dispc2_fid", "hw_dbg2", | ||
| 1203 | "safe_mode"), | ||
| 1204 | _OMAP4_MUXENTRY(DPM_EMU3, 14, "dpm_emu3", "usba0_ulpiphy_stp", NULL, | ||
| 1205 | "gpio_14", "rfbi_data10", "dispc2_data10", "hw_dbg3", | ||
| 1206 | "safe_mode"), | ||
| 1207 | _OMAP4_MUXENTRY(DPM_EMU4, 15, "dpm_emu4", "usba0_ulpiphy_dir", NULL, | ||
| 1208 | "gpio_15", "rfbi_data9", "dispc2_data9", "hw_dbg4", | ||
| 1209 | "safe_mode"), | ||
| 1210 | _OMAP4_MUXENTRY(DPM_EMU5, 16, "dpm_emu5", "usba0_ulpiphy_nxt", NULL, | ||
| 1211 | "gpio_16", "rfbi_te_vsync0", "dispc2_data16", | ||
| 1212 | "hw_dbg5", "safe_mode"), | ||
| 1213 | _OMAP4_MUXENTRY(DPM_EMU6, 17, "dpm_emu6", "usba0_ulpiphy_dat0", | ||
| 1214 | "uart3_tx_irtx", "gpio_17", "rfbi_hsync0", | ||
| 1215 | "dispc2_data17", "hw_dbg6", "safe_mode"), | ||
| 1216 | _OMAP4_MUXENTRY(DPM_EMU7, 18, "dpm_emu7", "usba0_ulpiphy_dat1", | ||
| 1217 | "uart3_rx_irrx", "gpio_18", "rfbi_cs0", | ||
| 1218 | "dispc2_hsync", "hw_dbg7", "safe_mode"), | ||
| 1219 | _OMAP4_MUXENTRY(DPM_EMU8, 19, "dpm_emu8", "usba0_ulpiphy_dat2", | ||
| 1220 | "uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk", | ||
| 1221 | "hw_dbg8", "safe_mode"), | ||
| 1222 | _OMAP4_MUXENTRY(DPM_EMU9, 20, "dpm_emu9", "usba0_ulpiphy_dat3", | ||
| 1223 | "uart3_cts_rctx", "gpio_20", "rfbi_we", | ||
| 1224 | "dispc2_vsync", "hw_dbg9", "safe_mode"), | ||
| 1225 | _OMAP4_MUXENTRY(DPM_EMU10, 21, "dpm_emu10", "usba0_ulpiphy_dat4", | ||
| 1226 | NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10", | ||
| 1227 | "safe_mode"), | ||
| 1228 | _OMAP4_MUXENTRY(DPM_EMU11, 22, "dpm_emu11", "usba0_ulpiphy_dat5", | ||
| 1229 | NULL, "gpio_22", "rfbi_data8", "dispc2_data8", | ||
| 1230 | "hw_dbg11", "safe_mode"), | ||
| 1231 | _OMAP4_MUXENTRY(DPM_EMU12, 23, "dpm_emu12", "usba0_ulpiphy_dat6", | ||
| 1232 | NULL, "gpio_23", "rfbi_data7", "dispc2_data7", | ||
| 1233 | "hw_dbg12", "safe_mode"), | ||
| 1234 | _OMAP4_MUXENTRY(DPM_EMU13, 24, "dpm_emu13", "usba0_ulpiphy_dat7", | ||
| 1235 | NULL, "gpio_24", "rfbi_data6", "dispc2_data6", | ||
| 1236 | "hw_dbg13", "safe_mode"), | ||
| 1237 | _OMAP4_MUXENTRY(DPM_EMU14, 25, "dpm_emu14", "sys_drm_msecure", | ||
| 1238 | "uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5", | ||
| 1239 | "hw_dbg14", "safe_mode"), | ||
| 1240 | _OMAP4_MUXENTRY(DPM_EMU15, 26, "dpm_emu15", "sys_secure_indicator", | ||
| 1241 | NULL, "gpio_26", "rfbi_data4", "dispc2_data4", | ||
| 1242 | "hw_dbg15", "safe_mode"), | ||
| 1243 | _OMAP4_MUXENTRY(DPM_EMU16, 27, "dpm_emu16", "dmtimer8_pwm_evt", | ||
| 1244 | "dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3", | ||
| 1245 | "hw_dbg16", "safe_mode"), | ||
| 1246 | _OMAP4_MUXENTRY(DPM_EMU17, 28, "dpm_emu17", "dmtimer9_pwm_evt", | ||
| 1247 | "dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2", | ||
| 1248 | "hw_dbg17", "safe_mode"), | ||
| 1249 | _OMAP4_MUXENTRY(DPM_EMU18, 190, "dpm_emu18", "dmtimer10_pwm_evt", | ||
| 1250 | "dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1", | ||
| 1251 | "hw_dbg18", "safe_mode"), | ||
| 1252 | _OMAP4_MUXENTRY(DPM_EMU19, 191, "dpm_emu19", "dmtimer11_pwm_evt", | ||
| 1253 | "dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0", | ||
| 1254 | "hw_dbg19", "safe_mode"), | ||
| 1255 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
| 1256 | }; | ||
| 1257 | |||
| 1258 | /* | ||
| 1259 | * Balls for 44XX CBS package | ||
| 1260 | * 547-pin CBL ES2.0 S-FPGA-N547, 0.40mm Ball Pitch (Top), | ||
| 1261 | * 0.40mm Ball Pitch (Bottom) | ||
| 1262 | */ | ||
| 1263 | #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ | ||
| 1264 | && defined(CONFIG_OMAP_PACKAGE_CBS) | ||
| 1265 | struct omap_ball __initdata omap4_core_cbs_ball[] = { | ||
| 1266 | _OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL), | ||
| 1267 | _OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL), | ||
| 1268 | _OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL), | ||
| 1269 | _OMAP4_BALLENTRY(GPMC_AD3, "d13", NULL), | ||
| 1270 | _OMAP4_BALLENTRY(GPMC_AD4, "c15", NULL), | ||
| 1271 | _OMAP4_BALLENTRY(GPMC_AD5, "d15", NULL), | ||
| 1272 | _OMAP4_BALLENTRY(GPMC_AD6, "a16", NULL), | ||
| 1273 | _OMAP4_BALLENTRY(GPMC_AD7, "b16", NULL), | ||
| 1274 | _OMAP4_BALLENTRY(GPMC_AD8, "c16", NULL), | ||
| 1275 | _OMAP4_BALLENTRY(GPMC_AD9, "d16", NULL), | ||
| 1276 | _OMAP4_BALLENTRY(GPMC_AD10, "c17", NULL), | ||
| 1277 | _OMAP4_BALLENTRY(GPMC_AD11, "d17", NULL), | ||
| 1278 | _OMAP4_BALLENTRY(GPMC_AD12, "c18", NULL), | ||
| 1279 | _OMAP4_BALLENTRY(GPMC_AD13, "d18", NULL), | ||
| 1280 | _OMAP4_BALLENTRY(GPMC_AD14, "c19", NULL), | ||
| 1281 | _OMAP4_BALLENTRY(GPMC_AD15, "d19", NULL), | ||
| 1282 | _OMAP4_BALLENTRY(GPMC_A16, "b17", NULL), | ||
| 1283 | _OMAP4_BALLENTRY(GPMC_A17, "a18", NULL), | ||
| 1284 | _OMAP4_BALLENTRY(GPMC_A18, "b18", NULL), | ||
| 1285 | _OMAP4_BALLENTRY(GPMC_A19, "a19", NULL), | ||
| 1286 | _OMAP4_BALLENTRY(GPMC_A20, "b19", NULL), | ||
| 1287 | _OMAP4_BALLENTRY(GPMC_A21, "b20", NULL), | ||
| 1288 | _OMAP4_BALLENTRY(GPMC_A22, "a21", NULL), | ||
| 1289 | _OMAP4_BALLENTRY(GPMC_A23, "b21", NULL), | ||
| 1290 | _OMAP4_BALLENTRY(GPMC_A24, "c20", NULL), | ||
| 1291 | _OMAP4_BALLENTRY(GPMC_A25, "d20", NULL), | ||
| 1292 | _OMAP4_BALLENTRY(GPMC_NCS0, "b25", NULL), | ||
| 1293 | _OMAP4_BALLENTRY(GPMC_NCS1, "c21", NULL), | ||
| 1294 | _OMAP4_BALLENTRY(GPMC_NCS2, "d21", NULL), | ||
| 1295 | _OMAP4_BALLENTRY(GPMC_NCS3, "c22", NULL), | ||
| 1296 | _OMAP4_BALLENTRY(GPMC_NWP, "c25", NULL), | ||
| 1297 | _OMAP4_BALLENTRY(GPMC_CLK, "b22", NULL), | ||
| 1298 | _OMAP4_BALLENTRY(GPMC_NADV_ALE, "d25", NULL), | ||
| 1299 | _OMAP4_BALLENTRY(GPMC_NOE, "b11", NULL), | ||
| 1300 | _OMAP4_BALLENTRY(GPMC_NWE, "b12", NULL), | ||
| 1301 | _OMAP4_BALLENTRY(GPMC_NBE0_CLE, "c23", NULL), | ||
| 1302 | _OMAP4_BALLENTRY(GPMC_NBE1, "d22", NULL), | ||
| 1303 | _OMAP4_BALLENTRY(GPMC_WAIT0, "b26", NULL), | ||
| 1304 | _OMAP4_BALLENTRY(GPMC_WAIT1, "b23", NULL), | ||
| 1305 | _OMAP4_BALLENTRY(GPMC_WAIT2, "d23", NULL), | ||
| 1306 | _OMAP4_BALLENTRY(GPMC_NCS4, "a24", NULL), | ||
| 1307 | _OMAP4_BALLENTRY(GPMC_NCS5, "b24", NULL), | ||
| 1308 | _OMAP4_BALLENTRY(GPMC_NCS6, "c24", NULL), | ||
| 1309 | _OMAP4_BALLENTRY(GPMC_NCS7, "d24", NULL), | ||
| 1310 | _OMAP4_BALLENTRY(HDMI_HPD, "b9", NULL), | ||
| 1311 | _OMAP4_BALLENTRY(HDMI_CEC, "b10", NULL), | ||
| 1312 | _OMAP4_BALLENTRY(HDMI_DDC_SCL, "a8", NULL), | ||
| 1313 | _OMAP4_BALLENTRY(HDMI_DDC_SDA, "b8", NULL), | ||
| 1314 | _OMAP4_BALLENTRY(CSI21_DX0, "r26", NULL), | ||
| 1315 | _OMAP4_BALLENTRY(CSI21_DY0, "r25", NULL), | ||
| 1316 | _OMAP4_BALLENTRY(CSI21_DX1, "t26", NULL), | ||
| 1317 | _OMAP4_BALLENTRY(CSI21_DY1, "t25", NULL), | ||
| 1318 | _OMAP4_BALLENTRY(CSI21_DX2, "u26", NULL), | ||
| 1319 | _OMAP4_BALLENTRY(CSI21_DY2, "u25", NULL), | ||
| 1320 | _OMAP4_BALLENTRY(CSI21_DX3, "v26", NULL), | ||
| 1321 | _OMAP4_BALLENTRY(CSI21_DY3, "v25", NULL), | ||
| 1322 | _OMAP4_BALLENTRY(CSI21_DX4, "w26", NULL), | ||
| 1323 | _OMAP4_BALLENTRY(CSI21_DY4, "w25", NULL), | ||
| 1324 | _OMAP4_BALLENTRY(CSI22_DX0, "m26", NULL), | ||
| 1325 | _OMAP4_BALLENTRY(CSI22_DY0, "m25", NULL), | ||
| 1326 | _OMAP4_BALLENTRY(CSI22_DX1, "n26", NULL), | ||
| 1327 | _OMAP4_BALLENTRY(CSI22_DY1, "n25", NULL), | ||
| 1328 | _OMAP4_BALLENTRY(CAM_SHUTTER, "t27", NULL), | ||
| 1329 | _OMAP4_BALLENTRY(CAM_STROBE, "u27", NULL), | ||
| 1330 | _OMAP4_BALLENTRY(CAM_GLOBALRESET, "v27", NULL), | ||
| 1331 | _OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, "ae18", NULL), | ||
| 1332 | _OMAP4_BALLENTRY(USBB1_ULPITLL_STP, "ag19", NULL), | ||
| 1333 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, "af19", NULL), | ||
| 1334 | _OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, "ae19", NULL), | ||
| 1335 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, "af18", NULL), | ||
| 1336 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, "ag18", NULL), | ||
| 1337 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, "ae17", NULL), | ||
| 1338 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, "af17", NULL), | ||
| 1339 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, "ah17", NULL), | ||
| 1340 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, "ae16", NULL), | ||
| 1341 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, "af16", NULL), | ||
| 1342 | _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, "ag16", NULL), | ||
| 1343 | _OMAP4_BALLENTRY(USBB1_HSIC_DATA, "af14", NULL), | ||
| 1344 | _OMAP4_BALLENTRY(USBB1_HSIC_STROBE, "ae14", NULL), | ||
| 1345 | _OMAP4_BALLENTRY(USBC1_ICUSB_DP, "h2", NULL), | ||
| 1346 | _OMAP4_BALLENTRY(USBC1_ICUSB_DM, "h3", NULL), | ||
| 1347 | _OMAP4_BALLENTRY(SDMMC1_CLK, "d2", NULL), | ||
| 1348 | _OMAP4_BALLENTRY(SDMMC1_CMD, "e3", NULL), | ||
| 1349 | _OMAP4_BALLENTRY(SDMMC1_DAT0, "e4", NULL), | ||
| 1350 | _OMAP4_BALLENTRY(SDMMC1_DAT1, "e2", NULL), | ||
| 1351 | _OMAP4_BALLENTRY(SDMMC1_DAT2, "e1", NULL), | ||
| 1352 | _OMAP4_BALLENTRY(SDMMC1_DAT3, "f4", NULL), | ||
| 1353 | _OMAP4_BALLENTRY(SDMMC1_DAT4, "f3", NULL), | ||
| 1354 | _OMAP4_BALLENTRY(SDMMC1_DAT5, "f1", NULL), | ||
| 1355 | _OMAP4_BALLENTRY(SDMMC1_DAT6, "g4", NULL), | ||
| 1356 | _OMAP4_BALLENTRY(SDMMC1_DAT7, "g3", NULL), | ||
| 1357 | _OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, "ad27", NULL), | ||
| 1358 | _OMAP4_BALLENTRY(ABE_MCBSP2_DR, "ad26", NULL), | ||
| 1359 | _OMAP4_BALLENTRY(ABE_MCBSP2_DX, "ad25", NULL), | ||
| 1360 | _OMAP4_BALLENTRY(ABE_MCBSP2_FSX, "ac28", NULL), | ||
| 1361 | _OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, "ac26", NULL), | ||
| 1362 | _OMAP4_BALLENTRY(ABE_MCBSP1_DR, "ac25", NULL), | ||
| 1363 | _OMAP4_BALLENTRY(ABE_MCBSP1_DX, "ab25", NULL), | ||
| 1364 | _OMAP4_BALLENTRY(ABE_MCBSP1_FSX, "ac27", NULL), | ||
| 1365 | _OMAP4_BALLENTRY(ABE_PDM_UL_DATA, "ag25", NULL), | ||
| 1366 | _OMAP4_BALLENTRY(ABE_PDM_DL_DATA, "af25", NULL), | ||
| 1367 | _OMAP4_BALLENTRY(ABE_PDM_FRAME, "ae25", NULL), | ||
| 1368 | _OMAP4_BALLENTRY(ABE_PDM_LB_CLK, "af26", NULL), | ||
| 1369 | _OMAP4_BALLENTRY(ABE_CLKS, "ah26", NULL), | ||
| 1370 | _OMAP4_BALLENTRY(ABE_DMIC_CLK1, "ae24", NULL), | ||
| 1371 | _OMAP4_BALLENTRY(ABE_DMIC_DIN1, "af24", NULL), | ||
| 1372 | _OMAP4_BALLENTRY(ABE_DMIC_DIN2, "ag24", NULL), | ||
| 1373 | _OMAP4_BALLENTRY(ABE_DMIC_DIN3, "ah24", NULL), | ||
| 1374 | _OMAP4_BALLENTRY(UART2_CTS, "ab26", NULL), | ||
| 1375 | _OMAP4_BALLENTRY(UART2_RTS, "ab27", NULL), | ||
| 1376 | _OMAP4_BALLENTRY(UART2_RX, "aa25", NULL), | ||
| 1377 | _OMAP4_BALLENTRY(UART2_TX, "aa26", NULL), | ||
| 1378 | _OMAP4_BALLENTRY(HDQ_SIO, "aa27", NULL), | ||
| 1379 | _OMAP4_BALLENTRY(I2C1_SCL, "ae28", NULL), | ||
| 1380 | _OMAP4_BALLENTRY(I2C1_SDA, "ae26", NULL), | ||
| 1381 | _OMAP4_BALLENTRY(I2C2_SCL, "c26", NULL), | ||
| 1382 | _OMAP4_BALLENTRY(I2C2_SDA, "d26", NULL), | ||
| 1383 | _OMAP4_BALLENTRY(I2C3_SCL, "w27", NULL), | ||
| 1384 | _OMAP4_BALLENTRY(I2C3_SDA, "y27", NULL), | ||
| 1385 | _OMAP4_BALLENTRY(I2C4_SCL, "ag21", NULL), | ||
| 1386 | _OMAP4_BALLENTRY(I2C4_SDA, "ah22", NULL), | ||
| 1387 | _OMAP4_BALLENTRY(MCSPI1_CLK, "af22", NULL), | ||
| 1388 | _OMAP4_BALLENTRY(MCSPI1_SOMI, "ae22", NULL), | ||
| 1389 | _OMAP4_BALLENTRY(MCSPI1_SIMO, "ag22", NULL), | ||
| 1390 | _OMAP4_BALLENTRY(MCSPI1_CS0, "ae23", NULL), | ||
| 1391 | _OMAP4_BALLENTRY(MCSPI1_CS1, "af23", NULL), | ||
| 1392 | _OMAP4_BALLENTRY(MCSPI1_CS2, "ag23", NULL), | ||
| 1393 | _OMAP4_BALLENTRY(MCSPI1_CS3, "ah23", NULL), | ||
| 1394 | _OMAP4_BALLENTRY(UART3_CTS_RCTX, "f27", NULL), | ||
| 1395 | _OMAP4_BALLENTRY(UART3_RTS_SD, "f28", NULL), | ||
| 1396 | _OMAP4_BALLENTRY(UART3_RX_IRRX, "g27", NULL), | ||
| 1397 | _OMAP4_BALLENTRY(UART3_TX_IRTX, "g28", NULL), | ||
| 1398 | _OMAP4_BALLENTRY(SDMMC5_CLK, "ae5", NULL), | ||
| 1399 | _OMAP4_BALLENTRY(SDMMC5_CMD, "af5", NULL), | ||
| 1400 | _OMAP4_BALLENTRY(SDMMC5_DAT0, "ae4", NULL), | ||
| 1401 | _OMAP4_BALLENTRY(SDMMC5_DAT1, "af4", NULL), | ||
| 1402 | _OMAP4_BALLENTRY(SDMMC5_DAT2, "ag3", NULL), | ||
| 1403 | _OMAP4_BALLENTRY(SDMMC5_DAT3, "af3", NULL), | ||
| 1404 | _OMAP4_BALLENTRY(MCSPI4_CLK, "ae21", NULL), | ||
| 1405 | _OMAP4_BALLENTRY(MCSPI4_SIMO, "af20", NULL), | ||
| 1406 | _OMAP4_BALLENTRY(MCSPI4_SOMI, "af21", NULL), | ||
| 1407 | _OMAP4_BALLENTRY(MCSPI4_CS0, "ae20", NULL), | ||
| 1408 | _OMAP4_BALLENTRY(UART4_RX, "ag20", NULL), | ||
| 1409 | _OMAP4_BALLENTRY(UART4_TX, "ah19", NULL), | ||
| 1410 | _OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, "ag12", NULL), | ||
| 1411 | _OMAP4_BALLENTRY(USBB2_ULPITLL_STP, "af12", NULL), | ||
| 1412 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, "ae12", NULL), | ||
| 1413 | _OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, "ag13", NULL), | ||
| 1414 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, "ae11", NULL), | ||
| 1415 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, "af11", NULL), | ||
| 1416 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, "ag11", NULL), | ||
| 1417 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, "ah11", NULL), | ||
| 1418 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, "ae10", NULL), | ||
| 1419 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, "af10", NULL), | ||
| 1420 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, "ag10", NULL), | ||
| 1421 | _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, "ae9", NULL), | ||
| 1422 | _OMAP4_BALLENTRY(USBB2_HSIC_DATA, "af13", NULL), | ||
| 1423 | _OMAP4_BALLENTRY(USBB2_HSIC_STROBE, "ae13", NULL), | ||
| 1424 | _OMAP4_BALLENTRY(KPD_COL3, "g26", NULL), | ||
| 1425 | _OMAP4_BALLENTRY(KPD_COL4, "g25", NULL), | ||
| 1426 | _OMAP4_BALLENTRY(KPD_COL5, "h26", NULL), | ||
| 1427 | _OMAP4_BALLENTRY(KPD_COL0, "h25", NULL), | ||
| 1428 | _OMAP4_BALLENTRY(KPD_COL1, "j27", NULL), | ||
| 1429 | _OMAP4_BALLENTRY(KPD_COL2, "h27", NULL), | ||
| 1430 | _OMAP4_BALLENTRY(KPD_ROW3, "j26", NULL), | ||
| 1431 | _OMAP4_BALLENTRY(KPD_ROW4, "j25", NULL), | ||
| 1432 | _OMAP4_BALLENTRY(KPD_ROW5, "k26", NULL), | ||
| 1433 | _OMAP4_BALLENTRY(KPD_ROW0, "k25", NULL), | ||
| 1434 | _OMAP4_BALLENTRY(KPD_ROW1, "l27", NULL), | ||
| 1435 | _OMAP4_BALLENTRY(KPD_ROW2, "k27", NULL), | ||
| 1436 | _OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL), | ||
| 1437 | _OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL), | ||
| 1438 | _OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL), | ||
| 1439 | _OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL), | ||
| 1440 | _OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL), | ||
| 1441 | _OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL), | ||
| 1442 | _OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL), | ||
| 1443 | _OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL), | ||
| 1444 | _OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL), | ||
| 1445 | _OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL), | ||
| 1446 | _OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL), | ||
| 1447 | _OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL), | ||
| 1448 | _OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL), | ||
| 1449 | _OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL), | ||
| 1450 | _OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL), | ||
| 1451 | _OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL), | ||
| 1452 | _OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL), | ||
| 1453 | _OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL), | ||
| 1454 | _OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL), | ||
| 1455 | _OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL), | ||
| 1456 | _OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL), | ||
| 1457 | _OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL), | ||
| 1458 | _OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL), | ||
| 1459 | _OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL), | ||
| 1460 | _OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL), | ||
| 1461 | _OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL), | ||
| 1462 | _OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL), | ||
| 1463 | _OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL), | ||
| 1464 | _OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL), | ||
| 1465 | _OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL), | ||
| 1466 | _OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL), | ||
| 1467 | _OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL), | ||
| 1468 | _OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL), | ||
| 1469 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
| 1470 | }; | ||
| 1471 | #else | ||
| 1472 | #define omap4_core_cbs_ball NULL | ||
| 1473 | #endif | ||
| 1474 | |||
| 1475 | /* | ||
| 1476 | * Superset of all mux modes for omap4 | ||
| 1477 | */ | ||
| 1478 | static struct omap_mux __initdata omap4_wkup_muxmodes[] = { | ||
| 1479 | _OMAP4_MUXENTRY(SIM_IO, 0, "sim_io", NULL, NULL, "gpio_wk0", NULL, | ||
| 1480 | NULL, NULL, "safe_mode"), | ||
| 1481 | _OMAP4_MUXENTRY(SIM_CLK, 1, "sim_clk", NULL, NULL, "gpio_wk1", NULL, | ||
| 1482 | NULL, NULL, "safe_mode"), | ||
| 1483 | _OMAP4_MUXENTRY(SIM_RESET, 2, "sim_reset", NULL, NULL, "gpio_wk2", | ||
| 1484 | NULL, NULL, NULL, "safe_mode"), | ||
| 1485 | _OMAP4_MUXENTRY(SIM_CD, 3, "sim_cd", NULL, NULL, "gpio_wk3", NULL, | ||
| 1486 | NULL, NULL, "safe_mode"), | ||
| 1487 | _OMAP4_MUXENTRY(SIM_PWRCTRL, 4, "sim_pwrctrl", NULL, NULL, "gpio_wk4", | ||
| 1488 | NULL, NULL, NULL, "safe_mode"), | ||
| 1489 | _OMAP4_MUXENTRY(SR_SCL, 0, "sr_scl", NULL, NULL, NULL, NULL, NULL, | ||
| 1490 | NULL, NULL), | ||
| 1491 | _OMAP4_MUXENTRY(SR_SDA, 0, "sr_sda", NULL, NULL, NULL, NULL, NULL, | ||
| 1492 | NULL, NULL), | ||
| 1493 | _OMAP4_MUXENTRY(FREF_XTAL_IN, 0, "fref_xtal_in", NULL, NULL, NULL, | ||
| 1494 | "c2c_wakereqin", NULL, NULL, NULL), | ||
| 1495 | _OMAP4_MUXENTRY(FREF_SLICER_IN, 0, "fref_slicer_in", NULL, NULL, | ||
| 1496 | "gpi_wk5", "c2c_wakereqin", NULL, NULL, "safe_mode"), | ||
| 1497 | _OMAP4_MUXENTRY(FREF_CLK_IOREQ, 0, "fref_clk_ioreq", NULL, NULL, NULL, | ||
| 1498 | NULL, NULL, NULL, NULL), | ||
| 1499 | _OMAP4_MUXENTRY(FREF_CLK0_OUT, 6, "fref_clk0_out", "fref_clk1_req", | ||
| 1500 | "sys_drm_msecure", "gpio_wk6", NULL, NULL, NULL, | ||
| 1501 | "safe_mode"), | ||
| 1502 | _OMAP4_MUXENTRY(FREF_CLK3_REQ, 30, "fref_clk3_req", "fref_clk1_req", | ||
| 1503 | "sys_drm_msecure", "gpio_wk30", "c2c_wakereqin", NULL, | ||
| 1504 | NULL, "safe_mode"), | ||
| 1505 | _OMAP4_MUXENTRY(FREF_CLK3_OUT, 31, "fref_clk3_out", "fref_clk2_req", | ||
| 1506 | "sys_secure_indicator", "gpio_wk31", "c2c_wakereqout", | ||
| 1507 | NULL, NULL, "safe_mode"), | ||
| 1508 | _OMAP4_MUXENTRY(FREF_CLK4_REQ, 7, "fref_clk4_req", "fref_clk5_out", | ||
| 1509 | NULL, "gpio_wk7", NULL, NULL, NULL, NULL), | ||
| 1510 | _OMAP4_MUXENTRY(FREF_CLK4_OUT, 8, "fref_clk4_out", NULL, NULL, | ||
| 1511 | "gpio_wk8", NULL, NULL, NULL, NULL), | ||
| 1512 | _OMAP4_MUXENTRY(SYS_32K, 0, "sys_32k", NULL, NULL, NULL, NULL, NULL, | ||
| 1513 | NULL, NULL), | ||
| 1514 | _OMAP4_MUXENTRY(SYS_NRESPWRON, 0, "sys_nrespwron", NULL, NULL, NULL, | ||
| 1515 | NULL, NULL, NULL, NULL), | ||
| 1516 | _OMAP4_MUXENTRY(SYS_NRESWARM, 0, "sys_nreswarm", NULL, NULL, NULL, | ||
| 1517 | NULL, NULL, NULL, NULL), | ||
| 1518 | _OMAP4_MUXENTRY(SYS_PWR_REQ, 0, "sys_pwr_req", NULL, NULL, NULL, NULL, | ||
| 1519 | NULL, NULL, NULL), | ||
| 1520 | _OMAP4_MUXENTRY(SYS_PWRON_RESET_OUT, 29, "sys_pwron_reset_out", NULL, | ||
| 1521 | NULL, "gpio_wk29", NULL, NULL, NULL, NULL), | ||
| 1522 | _OMAP4_MUXENTRY(SYS_BOOT6, 9, "sys_boot6", "dpm_emu18", NULL, | ||
| 1523 | "gpio_wk9", "c2c_wakereqout", NULL, NULL, | ||
| 1524 | "safe_mode"), | ||
| 1525 | _OMAP4_MUXENTRY(SYS_BOOT7, 10, "sys_boot7", "dpm_emu19", NULL, | ||
| 1526 | "gpio_wk10", NULL, NULL, NULL, "safe_mode"), | ||
| 1527 | _OMAP4_MUXENTRY(JTAG_NTRST, 0, "jtag_ntrst", NULL, NULL, NULL, NULL, | ||
| 1528 | NULL, NULL, NULL), | ||
| 1529 | _OMAP4_MUXENTRY(JTAG_TCK, 0, "jtag_tck", NULL, NULL, NULL, NULL, NULL, | ||
| 1530 | NULL, "safe_mode"), | ||
| 1531 | _OMAP4_MUXENTRY(JTAG_RTCK, 0, "jtag_rtck", NULL, NULL, NULL, NULL, | ||
| 1532 | NULL, NULL, NULL), | ||
| 1533 | _OMAP4_MUXENTRY(JTAG_TMS_TMSC, 0, "jtag_tms_tmsc", NULL, NULL, NULL, | ||
| 1534 | NULL, NULL, NULL, "safe_mode"), | ||
| 1535 | _OMAP4_MUXENTRY(JTAG_TDI, 0, "jtag_tdi", NULL, NULL, NULL, NULL, NULL, | ||
| 1536 | NULL, NULL), | ||
| 1537 | _OMAP4_MUXENTRY(JTAG_TDO, 0, "jtag_tdo", NULL, NULL, NULL, NULL, NULL, | ||
| 1538 | NULL, NULL), | ||
| 1539 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
| 1540 | }; | ||
| 1541 | |||
| 1542 | /* | ||
| 1543 | * Balls for 44XX CBL & CBS package - wakeup partition | ||
| 1544 | * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top), | ||
| 1545 | * 0.40mm Ball Pitch (Bottom) | ||
| 1546 | */ | ||
| 1547 | #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ | ||
| 1548 | && defined(CONFIG_OMAP_PACKAGE_CBL) | ||
| 1549 | struct omap_ball __initdata omap4_wkup_cbl_cbs_ball[] = { | ||
| 1550 | _OMAP4_BALLENTRY(SIM_IO, "h4", NULL), | ||
| 1551 | _OMAP4_BALLENTRY(SIM_CLK, "j2", NULL), | ||
| 1552 | _OMAP4_BALLENTRY(SIM_RESET, "g2", NULL), | ||
| 1553 | _OMAP4_BALLENTRY(SIM_CD, "j1", NULL), | ||
| 1554 | _OMAP4_BALLENTRY(SIM_PWRCTRL, "k1", NULL), | ||
| 1555 | _OMAP4_BALLENTRY(SR_SCL, "ag9", NULL), | ||
| 1556 | _OMAP4_BALLENTRY(SR_SDA, "af9", NULL), | ||
| 1557 | _OMAP4_BALLENTRY(FREF_XTAL_IN, "ah6", NULL), | ||
| 1558 | _OMAP4_BALLENTRY(FREF_SLICER_IN, "ag8", NULL), | ||
| 1559 | _OMAP4_BALLENTRY(FREF_CLK_IOREQ, "ad1", NULL), | ||
| 1560 | _OMAP4_BALLENTRY(FREF_CLK0_OUT, "ad2", NULL), | ||
| 1561 | _OMAP4_BALLENTRY(FREF_CLK3_REQ, "ad3", NULL), | ||
| 1562 | _OMAP4_BALLENTRY(FREF_CLK3_OUT, "ad4", NULL), | ||
| 1563 | _OMAP4_BALLENTRY(FREF_CLK4_REQ, "ac2", NULL), | ||
| 1564 | _OMAP4_BALLENTRY(FREF_CLK4_OUT, "ac3", NULL), | ||
| 1565 | _OMAP4_BALLENTRY(SYS_32K, "ag7", NULL), | ||
| 1566 | _OMAP4_BALLENTRY(SYS_NRESPWRON, "ae7", NULL), | ||
| 1567 | _OMAP4_BALLENTRY(SYS_NRESWARM, "af7", NULL), | ||
| 1568 | _OMAP4_BALLENTRY(SYS_PWR_REQ, "ah7", NULL), | ||
| 1569 | _OMAP4_BALLENTRY(SYS_PWRON_RESET_OUT, "ag6", NULL), | ||
| 1570 | _OMAP4_BALLENTRY(SYS_BOOT6, "af8", NULL), | ||
| 1571 | _OMAP4_BALLENTRY(SYS_BOOT7, "ae8", NULL), | ||
| 1572 | _OMAP4_BALLENTRY(JTAG_NTRST, "ah2", NULL), | ||
| 1573 | _OMAP4_BALLENTRY(JTAG_TCK, "ag1", NULL), | ||
| 1574 | _OMAP4_BALLENTRY(JTAG_RTCK, "ae3", NULL), | ||
| 1575 | _OMAP4_BALLENTRY(JTAG_TMS_TMSC, "ah1", NULL), | ||
| 1576 | _OMAP4_BALLENTRY(JTAG_TDI, "ae1", NULL), | ||
| 1577 | _OMAP4_BALLENTRY(JTAG_TDO, "ae2", NULL), | ||
| 1578 | { .reg_offset = OMAP_MUX_TERMINATOR }, | ||
| 1579 | }; | ||
| 1580 | #else | ||
| 1581 | #define omap4_wkup_cbl_cbs_ball NULL | ||
| 1582 | #endif | ||
| 1583 | |||
| 1584 | int __init omap4_mux_init(struct omap_board_mux *board_subset, int flags) | ||
| 1585 | { | ||
| 1586 | struct omap_ball *package_balls_core; | ||
| 1587 | struct omap_ball *package_balls_wkup = omap4_wkup_cbl_cbs_ball; | ||
| 1588 | struct omap_mux *core_muxmodes; | ||
| 1589 | int ret; | ||
| 1590 | |||
| 1591 | switch (flags & OMAP_PACKAGE_MASK) { | ||
| 1592 | case OMAP_PACKAGE_CBL: | ||
| 1593 | pr_debug("%s: OMAP4430 ES1.0 -> OMAP_PACKAGE_CBL\n", __func__); | ||
| 1594 | package_balls_core = omap4_core_cbl_ball; | ||
| 1595 | core_muxmodes = omap4_core_muxmodes; | ||
| 1596 | break; | ||
| 1597 | case OMAP_PACKAGE_CBS: | ||
| 1598 | pr_debug("%s: OMAP4430 ES2.X -> OMAP_PACKAGE_CBS\n", __func__); | ||
| 1599 | package_balls_core = omap4_core_cbs_ball; | ||
| 1600 | core_muxmodes = omap4_es2_core_muxmodes; | ||
| 1601 | break; | ||
| 1602 | default: | ||
| 1603 | pr_err("%s: Unknown omap package, mux disabled\n", __func__); | ||
| 1604 | return -EINVAL; | ||
| 1605 | } | ||
| 1606 | |||
| 1607 | ret = omap_mux_init("core", | ||
| 1608 | OMAP_MUX_GPIO_IN_MODE3, | ||
| 1609 | OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE, | ||
| 1610 | OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE, | ||
| 1611 | core_muxmodes, NULL, board_subset, | ||
| 1612 | package_balls_core); | ||
| 1613 | if (ret) | ||
| 1614 | return ret; | ||
| 1615 | |||
| 1616 | ret = omap_mux_init("wkup", | ||
| 1617 | OMAP_MUX_GPIO_IN_MODE3, | ||
| 1618 | OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE, | ||
| 1619 | OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE, | ||
| 1620 | omap4_wkup_muxmodes, NULL, board_subset, | ||
| 1621 | package_balls_wkup); | ||
| 1622 | |||
| 1623 | return ret; | ||
| 1624 | } | ||
| 1625 | |||
diff --git a/arch/arm/mach-omap2/mux44xx.h b/arch/arm/mach-omap2/mux44xx.h new file mode 100644 index 000000000000..c635026cd7e9 --- /dev/null +++ b/arch/arm/mach-omap2/mux44xx.h | |||
| @@ -0,0 +1,298 @@ | |||
| 1 | /* | ||
| 2 | * OMAP44xx MUX registers and bitfields | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. | ||
| 5 | * | ||
| 6 | * Benoit Cousson (b-cousson@ti.com) | ||
| 7 | * | ||
| 8 | * This file is automatically generated from the OMAP hardware databases. | ||
| 9 | * We respectfully ask that any modifications to this file be coordinated | ||
| 10 | * with the public linux-omap@vger.kernel.org mailing list and the | ||
| 11 | * authors above to ensure that the autogeneration scripts are kept | ||
| 12 | * up-to-date with the file contents. | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License version 2 as | ||
| 16 | * published by the Free Software Foundation. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef __ARCH_ARM_MACH_OMAP2_MUX_44XX_H | ||
| 20 | #define __ARCH_ARM_MACH_OMAP2_MUX_44XX_H | ||
| 21 | |||
| 22 | #define OMAP4_MUX(M0, mux_value) \ | ||
| 23 | { \ | ||
| 24 | .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \ | ||
| 25 | .value = (mux_value), \ | ||
| 26 | } | ||
| 27 | |||
| 28 | /* ctrl_module_pad_core base address */ | ||
| 29 | #define OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE 0x4a100000 | ||
| 30 | |||
| 31 | /* ctrl_module_pad_core registers offset */ | ||
| 32 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET 0x0040 | ||
| 33 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD1_OFFSET 0x0042 | ||
| 34 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD2_OFFSET 0x0044 | ||
| 35 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD3_OFFSET 0x0046 | ||
| 36 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD4_OFFSET 0x0048 | ||
| 37 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD5_OFFSET 0x004a | ||
| 38 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD6_OFFSET 0x004c | ||
| 39 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD7_OFFSET 0x004e | ||
| 40 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD8_OFFSET 0x0050 | ||
| 41 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD9_OFFSET 0x0052 | ||
| 42 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD10_OFFSET 0x0054 | ||
| 43 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD11_OFFSET 0x0056 | ||
| 44 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD12_OFFSET 0x0058 | ||
| 45 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD13_OFFSET 0x005a | ||
| 46 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD14_OFFSET 0x005c | ||
| 47 | #define OMAP4_CTRL_MODULE_PAD_GPMC_AD15_OFFSET 0x005e | ||
| 48 | #define OMAP4_CTRL_MODULE_PAD_GPMC_A16_OFFSET 0x0060 | ||
| 49 | #define OMAP4_CTRL_MODULE_PAD_GPMC_A17_OFFSET 0x0062 | ||
| 50 | #define OMAP4_CTRL_MODULE_PAD_GPMC_A18_OFFSET 0x0064 | ||
| 51 | #define OMAP4_CTRL_MODULE_PAD_GPMC_A19_OFFSET 0x0066 | ||
| 52 | #define OMAP4_CTRL_MODULE_PAD_GPMC_A20_OFFSET 0x0068 | ||
| 53 | #define OMAP4_CTRL_MODULE_PAD_GPMC_A21_OFFSET 0x006a | ||
| 54 | #define OMAP4_CTRL_MODULE_PAD_GPMC_A22_OFFSET 0x006c | ||
| 55 | #define OMAP4_CTRL_MODULE_PAD_GPMC_A23_OFFSET 0x006e | ||
| 56 | #define OMAP4_CTRL_MODULE_PAD_GPMC_A24_OFFSET 0x0070 | ||
| 57 | #define OMAP4_CTRL_MODULE_PAD_GPMC_A25_OFFSET 0x0072 | ||
| 58 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NCS0_OFFSET 0x0074 | ||
| 59 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NCS1_OFFSET 0x0076 | ||
| 60 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NCS2_OFFSET 0x0078 | ||
| 61 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NCS3_OFFSET 0x007a | ||
| 62 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NWP_OFFSET 0x007c | ||
| 63 | #define OMAP4_CTRL_MODULE_PAD_GPMC_CLK_OFFSET 0x007e | ||
| 64 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NADV_ALE_OFFSET 0x0080 | ||
| 65 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NOE_OFFSET 0x0082 | ||
| 66 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NWE_OFFSET 0x0084 | ||
| 67 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NBE0_CLE_OFFSET 0x0086 | ||
| 68 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NBE1_OFFSET 0x0088 | ||
| 69 | #define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT0_OFFSET 0x008a | ||
| 70 | #define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT1_OFFSET 0x008c | ||
| 71 | #define OMAP4_CTRL_MODULE_PAD_C2C_DATA11_OFFSET 0x008e | ||
| 72 | #define OMAP4_CTRL_MODULE_PAD_C2C_DATA12_OFFSET 0x0090 | ||
| 73 | #define OMAP4_CTRL_MODULE_PAD_C2C_DATA13_OFFSET 0x0092 | ||
| 74 | #define OMAP4_CTRL_MODULE_PAD_C2C_DATA14_OFFSET 0x0094 | ||
| 75 | #define OMAP4_CTRL_MODULE_PAD_C2C_DATA15_OFFSET 0x0096 | ||
| 76 | #define OMAP4_CTRL_MODULE_PAD_HDMI_HPD_OFFSET 0x0098 | ||
| 77 | #define OMAP4_CTRL_MODULE_PAD_HDMI_CEC_OFFSET 0x009a | ||
| 78 | #define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SCL_OFFSET 0x009c | ||
| 79 | #define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SDA_OFFSET 0x009e | ||
| 80 | #define OMAP4_CTRL_MODULE_PAD_CSI21_DX0_OFFSET 0x00a0 | ||
| 81 | #define OMAP4_CTRL_MODULE_PAD_CSI21_DY0_OFFSET 0x00a2 | ||
| 82 | #define OMAP4_CTRL_MODULE_PAD_CSI21_DX1_OFFSET 0x00a4 | ||
| 83 | #define OMAP4_CTRL_MODULE_PAD_CSI21_DY1_OFFSET 0x00a6 | ||
| 84 | #define OMAP4_CTRL_MODULE_PAD_CSI21_DX2_OFFSET 0x00a8 | ||
| 85 | #define OMAP4_CTRL_MODULE_PAD_CSI21_DY2_OFFSET 0x00aa | ||
| 86 | #define OMAP4_CTRL_MODULE_PAD_CSI21_DX3_OFFSET 0x00ac | ||
| 87 | #define OMAP4_CTRL_MODULE_PAD_CSI21_DY3_OFFSET 0x00ae | ||
| 88 | #define OMAP4_CTRL_MODULE_PAD_CSI21_DX4_OFFSET 0x00b0 | ||
| 89 | #define OMAP4_CTRL_MODULE_PAD_CSI21_DY4_OFFSET 0x00b2 | ||
| 90 | #define OMAP4_CTRL_MODULE_PAD_CSI22_DX0_OFFSET 0x00b4 | ||
| 91 | #define OMAP4_CTRL_MODULE_PAD_CSI22_DY0_OFFSET 0x00b6 | ||
| 92 | #define OMAP4_CTRL_MODULE_PAD_CSI22_DX1_OFFSET 0x00b8 | ||
| 93 | #define OMAP4_CTRL_MODULE_PAD_CSI22_DY1_OFFSET 0x00ba | ||
| 94 | #define OMAP4_CTRL_MODULE_PAD_CAM_SHUTTER_OFFSET 0x00bc | ||
| 95 | #define OMAP4_CTRL_MODULE_PAD_CAM_STROBE_OFFSET 0x00be | ||
| 96 | #define OMAP4_CTRL_MODULE_PAD_CAM_GLOBALRESET_OFFSET 0x00c0 | ||
| 97 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_CLK_OFFSET 0x00c2 | ||
| 98 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_STP_OFFSET 0x00c4 | ||
| 99 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DIR_OFFSET 0x00c6 | ||
| 100 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_NXT_OFFSET 0x00c8 | ||
| 101 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT0_OFFSET 0x00ca | ||
| 102 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT1_OFFSET 0x00cc | ||
| 103 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT2_OFFSET 0x00ce | ||
| 104 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT3_OFFSET 0x00d0 | ||
| 105 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT4_OFFSET 0x00d2 | ||
| 106 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT5_OFFSET 0x00d4 | ||
| 107 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT6_OFFSET 0x00d6 | ||
| 108 | #define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT7_OFFSET 0x00d8 | ||
| 109 | #define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_DATA_OFFSET 0x00da | ||
| 110 | #define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_STROBE_OFFSET 0x00dc | ||
| 111 | #define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DP_OFFSET 0x00de | ||
| 112 | #define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DM_OFFSET 0x00e0 | ||
| 113 | #define OMAP4_CTRL_MODULE_PAD_SDMMC1_CLK_OFFSET 0x00e2 | ||
| 114 | #define OMAP4_CTRL_MODULE_PAD_SDMMC1_CMD_OFFSET 0x00e4 | ||
| 115 | #define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT0_OFFSET 0x00e6 | ||
| 116 | #define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT1_OFFSET 0x00e8 | ||
| 117 | #define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT2_OFFSET 0x00ea | ||
| 118 | #define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT3_OFFSET 0x00ec | ||
| 119 | #define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT4_OFFSET 0x00ee | ||
| 120 | #define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT5_OFFSET 0x00f0 | ||
| 121 | #define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT6_OFFSET 0x00f2 | ||
| 122 | #define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT7_OFFSET 0x00f4 | ||
| 123 | #define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_CLKX_OFFSET 0x00f6 | ||
| 124 | #define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DR_OFFSET 0x00f8 | ||
| 125 | #define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DX_OFFSET 0x00fa | ||
| 126 | #define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_FSX_OFFSET 0x00fc | ||
| 127 | #define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_CLKX_OFFSET 0x00fe | ||
| 128 | #define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DR_OFFSET 0x0100 | ||
| 129 | #define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DX_OFFSET 0x0102 | ||
| 130 | #define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_FSX_OFFSET 0x0104 | ||
| 131 | #define OMAP4_CTRL_MODULE_PAD_ABE_PDM_UL_DATA_OFFSET 0x0106 | ||
| 132 | #define OMAP4_CTRL_MODULE_PAD_ABE_PDM_DL_DATA_OFFSET 0x0108 | ||
| 133 | #define OMAP4_CTRL_MODULE_PAD_ABE_PDM_FRAME_OFFSET 0x010a | ||
| 134 | #define OMAP4_CTRL_MODULE_PAD_ABE_PDM_LB_CLK_OFFSET 0x010c | ||
| 135 | #define OMAP4_CTRL_MODULE_PAD_ABE_CLKS_OFFSET 0x010e | ||
| 136 | #define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_CLK1_OFFSET 0x0110 | ||
| 137 | #define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN1_OFFSET 0x0112 | ||
| 138 | #define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN2_OFFSET 0x0114 | ||
| 139 | #define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN3_OFFSET 0x0116 | ||
| 140 | #define OMAP4_CTRL_MODULE_PAD_UART2_CTS_OFFSET 0x0118 | ||
| 141 | #define OMAP4_CTRL_MODULE_PAD_UART2_RTS_OFFSET 0x011a | ||
| 142 | #define OMAP4_CTRL_MODULE_PAD_UART2_RX_OFFSET 0x011c | ||
| 143 | #define OMAP4_CTRL_MODULE_PAD_UART2_TX_OFFSET 0x011e | ||
| 144 | #define OMAP4_CTRL_MODULE_PAD_HDQ_SIO_OFFSET 0x0120 | ||
| 145 | #define OMAP4_CTRL_MODULE_PAD_I2C1_SCL_OFFSET 0x0122 | ||
| 146 | #define OMAP4_CTRL_MODULE_PAD_I2C1_SDA_OFFSET 0x0124 | ||
| 147 | #define OMAP4_CTRL_MODULE_PAD_I2C2_SCL_OFFSET 0x0126 | ||
| 148 | #define OMAP4_CTRL_MODULE_PAD_I2C2_SDA_OFFSET 0x0128 | ||
| 149 | #define OMAP4_CTRL_MODULE_PAD_I2C3_SCL_OFFSET 0x012a | ||
| 150 | #define OMAP4_CTRL_MODULE_PAD_I2C3_SDA_OFFSET 0x012c | ||
| 151 | #define OMAP4_CTRL_MODULE_PAD_I2C4_SCL_OFFSET 0x012e | ||
| 152 | #define OMAP4_CTRL_MODULE_PAD_I2C4_SDA_OFFSET 0x0130 | ||
| 153 | #define OMAP4_CTRL_MODULE_PAD_MCSPI1_CLK_OFFSET 0x0132 | ||
| 154 | #define OMAP4_CTRL_MODULE_PAD_MCSPI1_SOMI_OFFSET 0x0134 | ||
| 155 | #define OMAP4_CTRL_MODULE_PAD_MCSPI1_SIMO_OFFSET 0x0136 | ||
| 156 | #define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS0_OFFSET 0x0138 | ||
| 157 | #define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS1_OFFSET 0x013a | ||
| 158 | #define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS2_OFFSET 0x013c | ||
| 159 | #define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS3_OFFSET 0x013e | ||
| 160 | #define OMAP4_CTRL_MODULE_PAD_UART3_CTS_RCTX_OFFSET 0x0140 | ||
| 161 | #define OMAP4_CTRL_MODULE_PAD_UART3_RTS_SD_OFFSET 0x0142 | ||
| 162 | #define OMAP4_CTRL_MODULE_PAD_UART3_RX_IRRX_OFFSET 0x0144 | ||
| 163 | #define OMAP4_CTRL_MODULE_PAD_UART3_TX_IRTX_OFFSET 0x0146 | ||
| 164 | #define OMAP4_CTRL_MODULE_PAD_SDMMC5_CLK_OFFSET 0x0148 | ||
| 165 | #define OMAP4_CTRL_MODULE_PAD_SDMMC5_CMD_OFFSET 0x014a | ||
| 166 | #define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT0_OFFSET 0x014c | ||
| 167 | #define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT1_OFFSET 0x014e | ||
| 168 | #define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT2_OFFSET 0x0150 | ||
| 169 | #define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT3_OFFSET 0x0152 | ||
| 170 | #define OMAP4_CTRL_MODULE_PAD_MCSPI4_CLK_OFFSET 0x0154 | ||
| 171 | #define OMAP4_CTRL_MODULE_PAD_MCSPI4_SIMO_OFFSET 0x0156 | ||
| 172 | #define OMAP4_CTRL_MODULE_PAD_MCSPI4_SOMI_OFFSET 0x0158 | ||
| 173 | #define OMAP4_CTRL_MODULE_PAD_MCSPI4_CS0_OFFSET 0x015a | ||
| 174 | #define OMAP4_CTRL_MODULE_PAD_UART4_RX_OFFSET 0x015c | ||
| 175 | #define OMAP4_CTRL_MODULE_PAD_UART4_TX_OFFSET 0x015e | ||
| 176 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_CLK_OFFSET 0x0160 | ||
| 177 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_STP_OFFSET 0x0162 | ||
| 178 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DIR_OFFSET 0x0164 | ||
| 179 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_NXT_OFFSET 0x0166 | ||
| 180 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT0_OFFSET 0x0168 | ||
| 181 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT1_OFFSET 0x016a | ||
| 182 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT2_OFFSET 0x016c | ||
| 183 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT3_OFFSET 0x016e | ||
| 184 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT4_OFFSET 0x0170 | ||
| 185 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT5_OFFSET 0x0172 | ||
| 186 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT6_OFFSET 0x0174 | ||
| 187 | #define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT7_OFFSET 0x0176 | ||
| 188 | #define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_DATA_OFFSET 0x0178 | ||
| 189 | #define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_STROBE_OFFSET 0x017a | ||
| 190 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX0_OFFSET 0x017c | ||
| 191 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY0_OFFSET 0x017e | ||
| 192 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX1_OFFSET 0x0180 | ||
| 193 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY1_OFFSET 0x0182 | ||
| 194 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX2_OFFSET 0x0184 | ||
| 195 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY2_OFFSET 0x0186 | ||
| 196 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX0_OFFSET 0x0188 | ||
| 197 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY0_OFFSET 0x018a | ||
| 198 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX1_OFFSET 0x018c | ||
| 199 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY1_OFFSET 0x018e | ||
| 200 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX2_OFFSET 0x0190 | ||
| 201 | #define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY2_OFFSET 0x0192 | ||
| 202 | #define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_CE_OFFSET 0x0194 | ||
| 203 | #define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DP_OFFSET 0x0196 | ||
| 204 | #define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DM_OFFSET 0x0198 | ||
| 205 | #define OMAP4_CTRL_MODULE_PAD_FREF_CLK1_OUT_OFFSET 0x019a | ||
| 206 | #define OMAP4_CTRL_MODULE_PAD_FREF_CLK2_OUT_OFFSET 0x019c | ||
| 207 | #define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ1_OFFSET 0x019e | ||
| 208 | #define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ2_OFFSET 0x01a0 | ||
| 209 | #define OMAP4_CTRL_MODULE_PAD_SYS_BOOT0_OFFSET 0x01a2 | ||
| 210 | #define OMAP4_CTRL_MODULE_PAD_SYS_BOOT1_OFFSET 0x01a4 | ||
| 211 | #define OMAP4_CTRL_MODULE_PAD_SYS_BOOT2_OFFSET 0x01a6 | ||
| 212 | #define OMAP4_CTRL_MODULE_PAD_SYS_BOOT3_OFFSET 0x01a8 | ||
| 213 | #define OMAP4_CTRL_MODULE_PAD_SYS_BOOT4_OFFSET 0x01aa | ||
| 214 | #define OMAP4_CTRL_MODULE_PAD_SYS_BOOT5_OFFSET 0x01ac | ||
| 215 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU0_OFFSET 0x01ae | ||
| 216 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU1_OFFSET 0x01b0 | ||
| 217 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU2_OFFSET 0x01b2 | ||
| 218 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU3_OFFSET 0x01b4 | ||
| 219 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU4_OFFSET 0x01b6 | ||
| 220 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU5_OFFSET 0x01b8 | ||
| 221 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU6_OFFSET 0x01ba | ||
| 222 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU7_OFFSET 0x01bc | ||
| 223 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU8_OFFSET 0x01be | ||
| 224 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU9_OFFSET 0x01c0 | ||
| 225 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU10_OFFSET 0x01c2 | ||
| 226 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU11_OFFSET 0x01c4 | ||
| 227 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU12_OFFSET 0x01c6 | ||
| 228 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU13_OFFSET 0x01c8 | ||
| 229 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU14_OFFSET 0x01ca | ||
| 230 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU15_OFFSET 0x01cc | ||
| 231 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU16_OFFSET 0x01ce | ||
| 232 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU17_OFFSET 0x01d0 | ||
| 233 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU18_OFFSET 0x01d2 | ||
| 234 | #define OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET 0x01d4 | ||
| 235 | |||
| 236 | /* ES2.0 only */ | ||
| 237 | #define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT2_OFFSET 0x008e | ||
| 238 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NCS4_OFFSET 0x0090 | ||
| 239 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NCS5_OFFSET 0x0092 | ||
| 240 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NCS6_OFFSET 0x0094 | ||
| 241 | #define OMAP4_CTRL_MODULE_PAD_GPMC_NCS7_OFFSET 0x0096 | ||
| 242 | |||
| 243 | #define OMAP4_CTRL_MODULE_PAD_KPD_COL3_OFFSET 0x017c | ||
| 244 | #define OMAP4_CTRL_MODULE_PAD_KPD_COL4_OFFSET 0x017e | ||
| 245 | #define OMAP4_CTRL_MODULE_PAD_KPD_COL5_OFFSET 0x0180 | ||
| 246 | #define OMAP4_CTRL_MODULE_PAD_KPD_COL0_OFFSET 0x0182 | ||
| 247 | #define OMAP4_CTRL_MODULE_PAD_KPD_COL1_OFFSET 0x0184 | ||
| 248 | #define OMAP4_CTRL_MODULE_PAD_KPD_COL2_OFFSET 0x0186 | ||
| 249 | #define OMAP4_CTRL_MODULE_PAD_KPD_ROW3_OFFSET 0x0188 | ||
| 250 | #define OMAP4_CTRL_MODULE_PAD_KPD_ROW4_OFFSET 0x018a | ||
| 251 | #define OMAP4_CTRL_MODULE_PAD_KPD_ROW5_OFFSET 0x018c | ||
| 252 | #define OMAP4_CTRL_MODULE_PAD_KPD_ROW0_OFFSET 0x018e | ||
| 253 | #define OMAP4_CTRL_MODULE_PAD_KPD_ROW1_OFFSET 0x0190 | ||
| 254 | #define OMAP4_CTRL_MODULE_PAD_KPD_ROW2_OFFSET 0x0192 | ||
| 255 | |||
| 256 | |||
| 257 | #define OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE \ | ||
| 258 | (OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET \ | ||
| 259 | - OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET + 2) | ||
| 260 | |||
| 261 | /* ctrl_module_pad_wkup base address */ | ||
| 262 | #define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE 0x4a31e000 | ||
| 263 | |||
| 264 | /* ctrl_module_pad_wkup registers offset */ | ||
| 265 | #define OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET 0x0040 | ||
| 266 | #define OMAP4_CTRL_MODULE_PAD_SIM_CLK_OFFSET 0x0042 | ||
| 267 | #define OMAP4_CTRL_MODULE_PAD_SIM_RESET_OFFSET 0x0044 | ||
| 268 | #define OMAP4_CTRL_MODULE_PAD_SIM_CD_OFFSET 0x0046 | ||
| 269 | #define OMAP4_CTRL_MODULE_PAD_SIM_PWRCTRL_OFFSET 0x0048 | ||
| 270 | #define OMAP4_CTRL_MODULE_PAD_SR_SCL_OFFSET 0x004a | ||
| 271 | #define OMAP4_CTRL_MODULE_PAD_SR_SDA_OFFSET 0x004c | ||
| 272 | #define OMAP4_CTRL_MODULE_PAD_FREF_XTAL_IN_OFFSET 0x004e | ||
| 273 | #define OMAP4_CTRL_MODULE_PAD_FREF_SLICER_IN_OFFSET 0x0050 | ||
| 274 | #define OMAP4_CTRL_MODULE_PAD_FREF_CLK_IOREQ_OFFSET 0x0052 | ||
| 275 | #define OMAP4_CTRL_MODULE_PAD_FREF_CLK0_OUT_OFFSET 0x0054 | ||
| 276 | #define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_REQ_OFFSET 0x0056 | ||
| 277 | #define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_OUT_OFFSET 0x0058 | ||
| 278 | #define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_REQ_OFFSET 0x005a | ||
| 279 | #define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_OUT_OFFSET 0x005c | ||
| 280 | #define OMAP4_CTRL_MODULE_PAD_SYS_32K_OFFSET 0x005e | ||
| 281 | #define OMAP4_CTRL_MODULE_PAD_SYS_NRESPWRON_OFFSET 0x0060 | ||
| 282 | #define OMAP4_CTRL_MODULE_PAD_SYS_NRESWARM_OFFSET 0x0062 | ||
| 283 | #define OMAP4_CTRL_MODULE_PAD_SYS_PWR_REQ_OFFSET 0x0064 | ||
| 284 | #define OMAP4_CTRL_MODULE_PAD_SYS_PWRON_RESET_OUT_OFFSET 0x0066 | ||
| 285 | #define OMAP4_CTRL_MODULE_PAD_SYS_BOOT6_OFFSET 0x0068 | ||
| 286 | #define OMAP4_CTRL_MODULE_PAD_SYS_BOOT7_OFFSET 0x006a | ||
| 287 | #define OMAP4_CTRL_MODULE_PAD_JTAG_NTRST_OFFSET 0x006c | ||
| 288 | #define OMAP4_CTRL_MODULE_PAD_JTAG_TCK_OFFSET 0x006e | ||
| 289 | #define OMAP4_CTRL_MODULE_PAD_JTAG_RTCK_OFFSET 0x0070 | ||
| 290 | #define OMAP4_CTRL_MODULE_PAD_JTAG_TMS_TMSC_OFFSET 0x0072 | ||
| 291 | #define OMAP4_CTRL_MODULE_PAD_JTAG_TDI_OFFSET 0x0074 | ||
| 292 | #define OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET 0x0076 | ||
| 293 | |||
| 294 | #define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE \ | ||
| 295 | (OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET \ | ||
| 296 | - OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET + 2) | ||
| 297 | |||
| 298 | #endif | ||
diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c index 6cee456ca542..4976b9393e49 100644 --- a/arch/arm/mach-omap2/omap-hotplug.c +++ b/arch/arm/mach-omap2/omap-hotplug.c | |||
| @@ -17,16 +17,13 @@ | |||
| 17 | #include <linux/kernel.h> | 17 | #include <linux/kernel.h> |
| 18 | #include <linux/errno.h> | 18 | #include <linux/errno.h> |
| 19 | #include <linux/smp.h> | 19 | #include <linux/smp.h> |
| 20 | #include <linux/completion.h> | ||
| 21 | 20 | ||
| 22 | #include <asm/cacheflush.h> | 21 | #include <asm/cacheflush.h> |
| 23 | #include <mach/omap4-common.h> | 22 | #include <mach/omap4-common.h> |
| 24 | 23 | ||
| 25 | static DECLARE_COMPLETION(cpu_killed); | ||
| 26 | |||
| 27 | int platform_cpu_kill(unsigned int cpu) | 24 | int platform_cpu_kill(unsigned int cpu) |
| 28 | { | 25 | { |
| 29 | return wait_for_completion_timeout(&cpu_killed, 5000); | 26 | return 1; |
| 30 | } | 27 | } |
| 31 | 28 | ||
| 32 | /* | 29 | /* |
| @@ -35,15 +32,6 @@ int platform_cpu_kill(unsigned int cpu) | |||
| 35 | */ | 32 | */ |
| 36 | void platform_cpu_die(unsigned int cpu) | 33 | void platform_cpu_die(unsigned int cpu) |
| 37 | { | 34 | { |
| 38 | unsigned int this_cpu = hard_smp_processor_id(); | ||
| 39 | |||
| 40 | if (cpu != this_cpu) { | ||
| 41 | pr_crit("platform_cpu_die running on %u, should be %u\n", | ||
| 42 | this_cpu, cpu); | ||
| 43 | BUG(); | ||
| 44 | } | ||
| 45 | pr_notice("CPU%u: shutdown\n", cpu); | ||
| 46 | complete(&cpu_killed); | ||
| 47 | flush_cache_all(); | 35 | flush_cache_all(); |
| 48 | dsb(); | 36 | dsb(); |
| 49 | 37 | ||
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c index f5a1aad1a5c0..3fc5dc7233da 100644 --- a/arch/arm/mach-omap2/omap-iommu.c +++ b/arch/arm/mach-omap2/omap-iommu.c | |||
| @@ -33,9 +33,11 @@ static struct iommu_device omap3_devices[] = { | |||
| 33 | .name = "isp", | 33 | .name = "isp", |
| 34 | .nr_tlb_entries = 8, | 34 | .nr_tlb_entries = 8, |
| 35 | .clk_name = "cam_ick", | 35 | .clk_name = "cam_ick", |
| 36 | .da_start = 0x0, | ||
| 37 | .da_end = 0xFFFFF000, | ||
| 36 | }, | 38 | }, |
| 37 | }, | 39 | }, |
| 38 | #if defined(CONFIG_MPU_BRIDGE_IOMMU) | 40 | #if defined(CONFIG_OMAP_IOMMU_IVA2) |
| 39 | { | 41 | { |
| 40 | .base = 0x5d000000, | 42 | .base = 0x5d000000, |
| 41 | .irq = 28, | 43 | .irq = 28, |
| @@ -43,6 +45,8 @@ static struct iommu_device omap3_devices[] = { | |||
| 43 | .name = "iva2", | 45 | .name = "iva2", |
| 44 | .nr_tlb_entries = 32, | 46 | .nr_tlb_entries = 32, |
| 45 | .clk_name = "iva2_ck", | 47 | .clk_name = "iva2_ck", |
| 48 | .da_start = 0x11000000, | ||
| 49 | .da_end = 0xFFFFF000, | ||
| 46 | }, | 50 | }, |
| 47 | }, | 51 | }, |
| 48 | #endif | 52 | #endif |
| @@ -64,6 +68,8 @@ static struct iommu_device omap4_devices[] = { | |||
| 64 | .name = "ducati", | 68 | .name = "ducati", |
| 65 | .nr_tlb_entries = 32, | 69 | .nr_tlb_entries = 32, |
| 66 | .clk_name = "ducati_ick", | 70 | .clk_name = "ducati_ick", |
| 71 | .da_start = 0x0, | ||
| 72 | .da_end = 0xFFFFF000, | ||
| 67 | }, | 73 | }, |
| 68 | }, | 74 | }, |
| 69 | #if defined(CONFIG_MPU_TESLA_IOMMU) | 75 | #if defined(CONFIG_MPU_TESLA_IOMMU) |
| @@ -74,6 +80,8 @@ static struct iommu_device omap4_devices[] = { | |||
| 74 | .name = "tesla", | 80 | .name = "tesla", |
| 75 | .nr_tlb_entries = 32, | 81 | .nr_tlb_entries = 32, |
| 76 | .clk_name = "tesla_ick", | 82 | .clk_name = "tesla_ick", |
| 83 | .da_start = 0x0, | ||
| 84 | .da_end = 0xFFFFF000, | ||
| 77 | }, | 85 | }, |
| 78 | }, | 86 | }, |
| 79 | #endif | 87 | #endif |
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index 9e9f70e18e3c..b66cfe8bc464 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c | |||
| @@ -21,7 +21,6 @@ | |||
| 21 | #include <linux/io.h> | 21 | #include <linux/io.h> |
| 22 | 22 | ||
| 23 | #include <asm/cacheflush.h> | 23 | #include <asm/cacheflush.h> |
| 24 | #include <asm/localtimer.h> | ||
| 25 | #include <asm/smp_scu.h> | 24 | #include <asm/smp_scu.h> |
| 26 | #include <mach/hardware.h> | 25 | #include <mach/hardware.h> |
| 27 | #include <mach/omap4-common.h> | 26 | #include <mach/omap4-common.h> |
| @@ -29,28 +28,16 @@ | |||
| 29 | /* SCU base address */ | 28 | /* SCU base address */ |
| 30 | static void __iomem *scu_base; | 29 | static void __iomem *scu_base; |
| 31 | 30 | ||
| 32 | /* | ||
| 33 | * Use SCU config register to count number of cores | ||
| 34 | */ | ||
| 35 | static inline unsigned int get_core_count(void) | ||
| 36 | { | ||
| 37 | if (scu_base) | ||
| 38 | return scu_get_core_count(scu_base); | ||
| 39 | return 1; | ||
| 40 | } | ||
| 41 | |||
| 42 | static DEFINE_SPINLOCK(boot_lock); | 31 | static DEFINE_SPINLOCK(boot_lock); |
| 43 | 32 | ||
| 44 | void __cpuinit platform_secondary_init(unsigned int cpu) | 33 | void __cpuinit platform_secondary_init(unsigned int cpu) |
| 45 | { | 34 | { |
| 46 | trace_hardirqs_off(); | ||
| 47 | |||
| 48 | /* | 35 | /* |
| 49 | * If any interrupts are already enabled for the primary | 36 | * If any interrupts are already enabled for the primary |
| 50 | * core (e.g. timer irq), then they will not have been enabled | 37 | * core (e.g. timer irq), then they will not have been enabled |
| 51 | * for us: do so | 38 | * for us: do so |
| 52 | */ | 39 | */ |
| 53 | gic_cpu_init(0, gic_cpu_base_addr); | 40 | gic_secondary_init(0); |
| 54 | 41 | ||
| 55 | /* | 42 | /* |
| 56 | * Synchronise with the boot thread. | 43 | * Synchronise with the boot thread. |
| @@ -76,7 +63,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) | |||
| 76 | omap_modify_auxcoreboot0(0x200, 0xfffffdff); | 63 | omap_modify_auxcoreboot0(0x200, 0xfffffdff); |
| 77 | flush_cache_all(); | 64 | flush_cache_all(); |
| 78 | smp_wmb(); | 65 | smp_wmb(); |
| 79 | smp_cross_call(cpumask_of(cpu)); | 66 | smp_cross_call(cpumask_of(cpu), 1); |
| 80 | 67 | ||
| 81 | /* | 68 | /* |
| 82 | * Now the secondary core is starting up let it run its | 69 | * Now the secondary core is starting up let it run its |
| @@ -118,25 +105,9 @@ void __init smp_init_cpus(void) | |||
| 118 | scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256); | 105 | scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256); |
| 119 | BUG_ON(!scu_base); | 106 | BUG_ON(!scu_base); |
| 120 | 107 | ||
| 121 | ncores = get_core_count(); | 108 | ncores = scu_get_core_count(scu_base); |
| 122 | |||
| 123 | for (i = 0; i < ncores; i++) | ||
| 124 | set_cpu_possible(i, true); | ||
| 125 | } | ||
| 126 | |||
| 127 | void __init smp_prepare_cpus(unsigned int max_cpus) | ||
| 128 | { | ||
| 129 | unsigned int ncores = get_core_count(); | ||
| 130 | unsigned int cpu = smp_processor_id(); | ||
| 131 | int i; | ||
| 132 | 109 | ||
| 133 | /* sanity check */ | 110 | /* sanity check */ |
| 134 | if (ncores == 0) { | ||
| 135 | printk(KERN_ERR | ||
| 136 | "OMAP4: strange core count of 0? Default to 1\n"); | ||
| 137 | ncores = 1; | ||
| 138 | } | ||
| 139 | |||
| 140 | if (ncores > NR_CPUS) { | 111 | if (ncores > NR_CPUS) { |
| 141 | printk(KERN_WARNING | 112 | printk(KERN_WARNING |
| 142 | "OMAP4: no. of cores (%d) greater than configured " | 113 | "OMAP4: no. of cores (%d) greater than configured " |
| @@ -144,13 +115,14 @@ void __init smp_prepare_cpus(unsigned int max_cpus) | |||
| 144 | ncores, NR_CPUS); | 115 | ncores, NR_CPUS); |
| 145 | ncores = NR_CPUS; | 116 | ncores = NR_CPUS; |
| 146 | } | 117 | } |
| 147 | smp_store_cpu_info(cpu); | ||
| 148 | 118 | ||
| 149 | /* | 119 | for (i = 0; i < ncores; i++) |
| 150 | * are we trying to boot more cores than exist? | 120 | set_cpu_possible(i, true); |
| 151 | */ | 121 | } |
| 152 | if (max_cpus > ncores) | 122 | |
| 153 | max_cpus = ncores; | 123 | void __init platform_smp_prepare_cpus(unsigned int max_cpus) |
| 124 | { | ||
| 125 | int i; | ||
| 154 | 126 | ||
| 155 | /* | 127 | /* |
| 156 | * Initialise the present map, which describes the set of CPUs | 128 | * Initialise the present map, which describes the set of CPUs |
| @@ -159,18 +131,10 @@ void __init smp_prepare_cpus(unsigned int max_cpus) | |||
| 159 | for (i = 0; i < max_cpus; i++) | 131 | for (i = 0; i < max_cpus; i++) |
| 160 | set_cpu_present(i, true); | 132 | set_cpu_present(i, true); |
| 161 | 133 | ||
| 162 | if (max_cpus > 1) { | 134 | /* |
| 163 | /* | 135 | * Initialise the SCU and wake up the secondary core using |
| 164 | * Enable the local timer or broadcast device for the | 136 | * wakeup_secondary(). |
| 165 | * boot CPU, but only if we have more than one CPU. | 137 | */ |
| 166 | */ | 138 | scu_enable(scu_base); |
| 167 | percpu_timer_setup(); | 139 | wakeup_secondary(); |
| 168 | |||
| 169 | /* | ||
| 170 | * Initialise the SCU and wake up the secondary core using | ||
| 171 | * wakeup_secondary(). | ||
| 172 | */ | ||
| 173 | scu_enable(scu_base); | ||
| 174 | wakeup_secondary(); | ||
| 175 | } | ||
| 176 | } | 140 | } |
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 2f895553e6a8..19268647ce36 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c | |||
| @@ -26,21 +26,22 @@ | |||
| 26 | void __iomem *l2cache_base; | 26 | void __iomem *l2cache_base; |
| 27 | #endif | 27 | #endif |
| 28 | 28 | ||
| 29 | void __iomem *gic_cpu_base_addr; | ||
| 30 | void __iomem *gic_dist_base_addr; | 29 | void __iomem *gic_dist_base_addr; |
| 31 | 30 | ||
| 32 | 31 | ||
| 33 | void __init gic_init_irq(void) | 32 | void __init gic_init_irq(void) |
| 34 | { | 33 | { |
| 34 | void __iomem *gic_cpu_base; | ||
| 35 | |||
| 35 | /* Static mapping, never released */ | 36 | /* Static mapping, never released */ |
| 36 | gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K); | 37 | gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K); |
| 37 | BUG_ON(!gic_dist_base_addr); | 38 | BUG_ON(!gic_dist_base_addr); |
| 38 | gic_dist_init(0, gic_dist_base_addr, 29); | ||
| 39 | 39 | ||
| 40 | /* Static mapping, never released */ | 40 | /* Static mapping, never released */ |
| 41 | gic_cpu_base_addr = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512); | 41 | gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512); |
| 42 | BUG_ON(!gic_cpu_base_addr); | 42 | BUG_ON(!gic_cpu_base); |
| 43 | gic_cpu_init(0, gic_cpu_base_addr); | 43 | |
| 44 | gic_init(0, 29, gic_dist_base_addr, gic_cpu_base); | ||
| 44 | } | 45 | } |
| 45 | 46 | ||
| 46 | #ifdef CONFIG_CACHE_L2X0 | 47 | #ifdef CONFIG_CACHE_L2X0 |
| @@ -53,6 +54,8 @@ static void omap4_l2x0_disable(void) | |||
| 53 | 54 | ||
| 54 | static int __init omap_l2_cache_init(void) | 55 | static int __init omap_l2_cache_init(void) |
| 55 | { | 56 | { |
| 57 | u32 aux_ctrl = 0; | ||
| 58 | |||
| 56 | /* | 59 | /* |
| 57 | * To avoid code running on other OMAPs in | 60 | * To avoid code running on other OMAPs in |
| 58 | * multi-omap builds | 61 | * multi-omap builds |
| @@ -64,18 +67,32 @@ static int __init omap_l2_cache_init(void) | |||
| 64 | l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K); | 67 | l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K); |
| 65 | BUG_ON(!l2cache_base); | 68 | BUG_ON(!l2cache_base); |
| 66 | 69 | ||
| 67 | /* Enable PL310 L2 Cache controller */ | ||
| 68 | omap_smc1(0x102, 0x1); | ||
| 69 | |||
| 70 | /* | 70 | /* |
| 71 | * 16-way associativity, parity disabled | 71 | * 16-way associativity, parity disabled |
| 72 | * Way size - 32KB (es1.0) | 72 | * Way size - 32KB (es1.0) |
| 73 | * Way size - 64KB (es2.0 +) | 73 | * Way size - 64KB (es2.0 +) |
| 74 | */ | 74 | */ |
| 75 | if (omap_rev() == OMAP4430_REV_ES1_0) | 75 | aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) | |
| 76 | l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff); | 76 | (0x1 << 25) | |
| 77 | else | 77 | (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) | |
| 78 | l2x0_init(l2cache_base, 0x0e070000, 0xc0000fff); | 78 | (0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT)); |
| 79 | |||
| 80 | if (omap_rev() == OMAP4430_REV_ES1_0) { | ||
| 81 | aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT; | ||
| 82 | } else { | ||
| 83 | aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | | ||
| 84 | (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) | | ||
| 85 | (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) | | ||
| 86 | (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) | | ||
| 87 | (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)); | ||
| 88 | } | ||
| 89 | if (omap_rev() != OMAP4430_REV_ES1_0) | ||
| 90 | omap_smc1(0x109, aux_ctrl); | ||
| 91 | |||
| 92 | /* Enable PL310 L2 Cache controller */ | ||
| 93 | omap_smc1(0x102, 0x1); | ||
| 94 | |||
| 95 | l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK); | ||
| 79 | 96 | ||
| 80 | /* | 97 | /* |
| 81 | * Override default outer_cache.disable with a OMAP4 | 98 | * Override default outer_cache.disable with a OMAP4 |
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 5a30658444d0..e282e35769fd 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c | |||
| @@ -116,7 +116,6 @@ | |||
| 116 | * - Open Core Protocol Specification 2.2 | 116 | * - Open Core Protocol Specification 2.2 |
| 117 | * | 117 | * |
| 118 | * To do: | 118 | * To do: |
| 119 | * - pin mux handling | ||
| 120 | * - handle IO mapping | 119 | * - handle IO mapping |
| 121 | * - bus throughput & module latency measurement code | 120 | * - bus throughput & module latency measurement code |
| 122 | * | 121 | * |
| @@ -135,17 +134,21 @@ | |||
| 135 | #include <linux/err.h> | 134 | #include <linux/err.h> |
| 136 | #include <linux/list.h> | 135 | #include <linux/list.h> |
| 137 | #include <linux/mutex.h> | 136 | #include <linux/mutex.h> |
| 137 | #include <linux/spinlock.h> | ||
| 138 | 138 | ||
| 139 | #include <plat/common.h> | 139 | #include <plat/common.h> |
| 140 | #include <plat/cpu.h> | 140 | #include <plat/cpu.h> |
| 141 | #include <plat/clockdomain.h> | 141 | #include "clockdomain.h" |
| 142 | #include <plat/powerdomain.h> | 142 | #include "powerdomain.h" |
| 143 | #include <plat/clock.h> | 143 | #include <plat/clock.h> |
| 144 | #include <plat/omap_hwmod.h> | 144 | #include <plat/omap_hwmod.h> |
| 145 | #include <plat/prcm.h> | 145 | #include <plat/prcm.h> |
| 146 | 146 | ||
| 147 | #include "cm.h" | 147 | #include "cm2xxx_3xxx.h" |
| 148 | #include "prm.h" | 148 | #include "cm44xx.h" |
| 149 | #include "prm2xxx_3xxx.h" | ||
| 150 | #include "prm44xx.h" | ||
| 151 | #include "mux.h" | ||
| 149 | 152 | ||
| 150 | /* Maximum microseconds to wait for OMAP module to softreset */ | 153 | /* Maximum microseconds to wait for OMAP module to softreset */ |
| 151 | #define MAX_MODULE_SOFTRESET_WAIT 10000 | 154 | #define MAX_MODULE_SOFTRESET_WAIT 10000 |
| @@ -156,8 +159,6 @@ | |||
| 156 | /* omap_hwmod_list contains all registered struct omap_hwmods */ | 159 | /* omap_hwmod_list contains all registered struct omap_hwmods */ |
| 157 | static LIST_HEAD(omap_hwmod_list); | 160 | static LIST_HEAD(omap_hwmod_list); |
| 158 | 161 | ||
| 159 | static DEFINE_MUTEX(omap_hwmod_mutex); | ||
| 160 | |||
| 161 | /* mpu_oh: used to add/remove MPU initiator from sleepdep list */ | 162 | /* mpu_oh: used to add/remove MPU initiator from sleepdep list */ |
| 162 | static struct omap_hwmod *mpu_oh; | 163 | static struct omap_hwmod *mpu_oh; |
| 163 | 164 | ||
| @@ -209,10 +210,9 @@ static void _write_sysconfig(u32 v, struct omap_hwmod *oh) | |||
| 209 | 210 | ||
| 210 | /* XXX ensure module interface clock is up */ | 211 | /* XXX ensure module interface clock is up */ |
| 211 | 212 | ||
| 212 | if (oh->_sysc_cache != v) { | 213 | /* Module might have lost context, always update cache and register */ |
| 213 | oh->_sysc_cache = v; | 214 | oh->_sysc_cache = v; |
| 214 | omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs); | 215 | omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs); |
| 215 | } | ||
| 216 | } | 216 | } |
| 217 | 217 | ||
| 218 | /** | 218 | /** |
| @@ -388,12 +388,13 @@ static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle, | |||
| 388 | * Allow the hardware module @oh to send wakeups. Returns -EINVAL | 388 | * Allow the hardware module @oh to send wakeups. Returns -EINVAL |
| 389 | * upon error or 0 upon success. | 389 | * upon error or 0 upon success. |
| 390 | */ | 390 | */ |
| 391 | static int _enable_wakeup(struct omap_hwmod *oh) | 391 | static int _enable_wakeup(struct omap_hwmod *oh, u32 *v) |
| 392 | { | 392 | { |
| 393 | u32 v, wakeup_mask; | 393 | u32 wakeup_mask; |
| 394 | 394 | ||
| 395 | if (!oh->class->sysc || | 395 | if (!oh->class->sysc || |
| 396 | !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) | 396 | !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || |
| 397 | (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP))) | ||
| 397 | return -EINVAL; | 398 | return -EINVAL; |
| 398 | 399 | ||
| 399 | if (!oh->class->sysc->sysc_fields) { | 400 | if (!oh->class->sysc->sysc_fields) { |
| @@ -403,9 +404,10 @@ static int _enable_wakeup(struct omap_hwmod *oh) | |||
| 403 | 404 | ||
| 404 | wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift); | 405 | wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift); |
| 405 | 406 | ||
| 406 | v = oh->_sysc_cache; | 407 | *v |= wakeup_mask; |
| 407 | v |= wakeup_mask; | 408 | |
| 408 | _write_sysconfig(v, oh); | 409 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) |
| 410 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | ||
| 409 | 411 | ||
| 410 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ | 412 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
| 411 | 413 | ||
| @@ -421,12 +423,13 @@ static int _enable_wakeup(struct omap_hwmod *oh) | |||
| 421 | * Prevent the hardware module @oh to send wakeups. Returns -EINVAL | 423 | * Prevent the hardware module @oh to send wakeups. Returns -EINVAL |
| 422 | * upon error or 0 upon success. | 424 | * upon error or 0 upon success. |
| 423 | */ | 425 | */ |
| 424 | static int _disable_wakeup(struct omap_hwmod *oh) | 426 | static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) |
| 425 | { | 427 | { |
| 426 | u32 v, wakeup_mask; | 428 | u32 wakeup_mask; |
| 427 | 429 | ||
| 428 | if (!oh->class->sysc || | 430 | if (!oh->class->sysc || |
| 429 | !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) | 431 | !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || |
| 432 | (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP))) | ||
| 430 | return -EINVAL; | 433 | return -EINVAL; |
| 431 | 434 | ||
| 432 | if (!oh->class->sysc->sysc_fields) { | 435 | if (!oh->class->sysc->sysc_fields) { |
| @@ -436,9 +439,10 @@ static int _disable_wakeup(struct omap_hwmod *oh) | |||
| 436 | 439 | ||
| 437 | wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift); | 440 | wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift); |
| 438 | 441 | ||
| 439 | v = oh->_sysc_cache; | 442 | *v &= ~wakeup_mask; |
| 440 | v &= ~wakeup_mask; | 443 | |
| 441 | _write_sysconfig(v, oh); | 444 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) |
| 445 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v); | ||
| 442 | 446 | ||
| 443 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ | 447 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
| 444 | 448 | ||
| @@ -675,7 +679,7 @@ static void _disable_optional_clocks(struct omap_hwmod *oh) | |||
| 675 | * Returns the array index of the OCP slave port that the MPU | 679 | * Returns the array index of the OCP slave port that the MPU |
| 676 | * addresses the device on, or -EINVAL upon error or not found. | 680 | * addresses the device on, or -EINVAL upon error or not found. |
| 677 | */ | 681 | */ |
| 678 | static int _find_mpu_port_index(struct omap_hwmod *oh) | 682 | static int __init _find_mpu_port_index(struct omap_hwmod *oh) |
| 679 | { | 683 | { |
| 680 | int i; | 684 | int i; |
| 681 | int found = 0; | 685 | int found = 0; |
| @@ -709,7 +713,7 @@ static int _find_mpu_port_index(struct omap_hwmod *oh) | |||
| 709 | * Return the virtual address of the base of the register target of | 713 | * Return the virtual address of the base of the register target of |
| 710 | * device @oh, or NULL on error. | 714 | * device @oh, or NULL on error. |
| 711 | */ | 715 | */ |
| 712 | static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index) | 716 | static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index) |
| 713 | { | 717 | { |
| 714 | struct omap_hwmod_ocp_if *os; | 718 | struct omap_hwmod_ocp_if *os; |
| 715 | struct omap_hwmod_addr_space *mem; | 719 | struct omap_hwmod_addr_space *mem; |
| @@ -786,11 +790,11 @@ static void _enable_sysc(struct omap_hwmod *oh) | |||
| 786 | (sf & SYSC_HAS_CLOCKACTIVITY)) | 790 | (sf & SYSC_HAS_CLOCKACTIVITY)) |
| 787 | _set_clockactivity(oh, oh->class->sysc->clockact, &v); | 791 | _set_clockactivity(oh, oh->class->sysc->clockact, &v); |
| 788 | 792 | ||
| 789 | _write_sysconfig(v, oh); | ||
| 790 | |||
| 791 | /* If slave is in SMARTIDLE, also enable wakeup */ | 793 | /* If slave is in SMARTIDLE, also enable wakeup */ |
| 792 | if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) | 794 | if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) |
| 793 | _enable_wakeup(oh); | 795 | _enable_wakeup(oh, &v); |
| 796 | |||
| 797 | _write_sysconfig(v, oh); | ||
| 794 | 798 | ||
| 795 | /* | 799 | /* |
| 796 | * Set the autoidle bit only after setting the smartidle bit | 800 | * Set the autoidle bit only after setting the smartidle bit |
| @@ -836,6 +840,10 @@ static void _idle_sysc(struct omap_hwmod *oh) | |||
| 836 | _set_master_standbymode(oh, idlemode, &v); | 840 | _set_master_standbymode(oh, idlemode, &v); |
| 837 | } | 841 | } |
| 838 | 842 | ||
| 843 | /* If slave is in SMARTIDLE, also enable wakeup */ | ||
| 844 | if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) | ||
| 845 | _enable_wakeup(oh, &v); | ||
| 846 | |||
| 839 | _write_sysconfig(v, oh); | 847 | _write_sysconfig(v, oh); |
| 840 | } | 848 | } |
| 841 | 849 | ||
| @@ -874,7 +882,6 @@ static void _shutdown_sysc(struct omap_hwmod *oh) | |||
| 874 | * @name: find an omap_hwmod by name | 882 | * @name: find an omap_hwmod by name |
| 875 | * | 883 | * |
| 876 | * Return a pointer to an omap_hwmod by name, or NULL if not found. | 884 | * Return a pointer to an omap_hwmod by name, or NULL if not found. |
| 877 | * Caller must hold omap_hwmod_mutex. | ||
| 878 | */ | 885 | */ |
| 879 | static struct omap_hwmod *_lookup(const char *name) | 886 | static struct omap_hwmod *_lookup(const char *name) |
| 880 | { | 887 | { |
| @@ -1089,7 +1096,7 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name) | |||
| 1089 | } | 1096 | } |
| 1090 | 1097 | ||
| 1091 | /** | 1098 | /** |
| 1092 | * _reset - reset an omap_hwmod | 1099 | * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit |
| 1093 | * @oh: struct omap_hwmod * | 1100 | * @oh: struct omap_hwmod * |
| 1094 | * | 1101 | * |
| 1095 | * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be | 1102 | * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be |
| @@ -1098,12 +1105,13 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name) | |||
| 1098 | * the module did not reset in time, or 0 upon success. | 1105 | * the module did not reset in time, or 0 upon success. |
| 1099 | * | 1106 | * |
| 1100 | * In OMAP3 a specific SYSSTATUS register is used to get the reset status. | 1107 | * In OMAP3 a specific SYSSTATUS register is used to get the reset status. |
| 1101 | * Starting in OMAP4, some IPs does not have SYSSTATUS register and instead | 1108 | * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead |
| 1102 | * use the SYSCONFIG softreset bit to provide the status. | 1109 | * use the SYSCONFIG softreset bit to provide the status. |
| 1103 | * | 1110 | * |
| 1104 | * Note that some IP like McBSP does have a reset control but no reset status. | 1111 | * Note that some IP like McBSP do have reset control but don't have |
| 1112 | * reset status. | ||
| 1105 | */ | 1113 | */ |
| 1106 | static int _reset(struct omap_hwmod *oh) | 1114 | static int _ocp_softreset(struct omap_hwmod *oh) |
| 1107 | { | 1115 | { |
| 1108 | u32 v; | 1116 | u32 v; |
| 1109 | int c = 0; | 1117 | int c = 0; |
| @@ -1124,7 +1132,7 @@ static int _reset(struct omap_hwmod *oh) | |||
| 1124 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | 1132 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) |
| 1125 | _enable_optional_clocks(oh); | 1133 | _enable_optional_clocks(oh); |
| 1126 | 1134 | ||
| 1127 | pr_debug("omap_hwmod: %s: resetting\n", oh->name); | 1135 | pr_debug("omap_hwmod: %s: resetting via OCP SOFTRESET\n", oh->name); |
| 1128 | 1136 | ||
| 1129 | v = oh->_sysc_cache; | 1137 | v = oh->_sysc_cache; |
| 1130 | ret = _set_softreset(oh, &v); | 1138 | ret = _set_softreset(oh, &v); |
| @@ -1164,17 +1172,41 @@ dis_opt_clks: | |||
| 1164 | } | 1172 | } |
| 1165 | 1173 | ||
| 1166 | /** | 1174 | /** |
| 1167 | * _omap_hwmod_enable - enable an omap_hwmod | 1175 | * _reset - reset an omap_hwmod |
| 1176 | * @oh: struct omap_hwmod * | ||
| 1177 | * | ||
| 1178 | * Resets an omap_hwmod @oh. The default software reset mechanism for | ||
| 1179 | * most OMAP IP blocks is triggered via the OCP_SYSCONFIG.SOFTRESET | ||
| 1180 | * bit. However, some hwmods cannot be reset via this method: some | ||
| 1181 | * are not targets and therefore have no OCP header registers to | ||
| 1182 | * access; others (like the IVA) have idiosyncratic reset sequences. | ||
| 1183 | * So for these relatively rare cases, custom reset code can be | ||
| 1184 | * supplied in the struct omap_hwmod_class .reset function pointer. | ||
| 1185 | * Passes along the return value from either _reset() or the custom | ||
| 1186 | * reset function - these must return -EINVAL if the hwmod cannot be | ||
| 1187 | * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if | ||
| 1188 | * the module did not reset in time, or 0 upon success. | ||
| 1189 | */ | ||
| 1190 | static int _reset(struct omap_hwmod *oh) | ||
| 1191 | { | ||
| 1192 | int ret; | ||
| 1193 | |||
| 1194 | pr_debug("omap_hwmod: %s: resetting\n", oh->name); | ||
| 1195 | |||
| 1196 | ret = (oh->class->reset) ? oh->class->reset(oh) : _ocp_softreset(oh); | ||
| 1197 | |||
| 1198 | return ret; | ||
| 1199 | } | ||
| 1200 | |||
| 1201 | /** | ||
| 1202 | * _enable - enable an omap_hwmod | ||
| 1168 | * @oh: struct omap_hwmod * | 1203 | * @oh: struct omap_hwmod * |
| 1169 | * | 1204 | * |
| 1170 | * Enables an omap_hwmod @oh such that the MPU can access the hwmod's | 1205 | * Enables an omap_hwmod @oh such that the MPU can access the hwmod's |
| 1171 | * register target. (This function has a full name -- | 1206 | * register target. Returns -EINVAL if the hwmod is in the wrong |
| 1172 | * _omap_hwmod_enable() rather than simply _enable() -- because it is | 1207 | * state or passes along the return value of _wait_target_ready(). |
| 1173 | * currently required by the pm34xx.c idle loop.) Returns -EINVAL if | ||
| 1174 | * the hwmod is in the wrong state or passes along the return value of | ||
| 1175 | * _wait_target_ready(). | ||
| 1176 | */ | 1208 | */ |
| 1177 | int _omap_hwmod_enable(struct omap_hwmod *oh) | 1209 | static int _enable(struct omap_hwmod *oh) |
| 1178 | { | 1210 | { |
| 1179 | int r; | 1211 | int r; |
| 1180 | 1212 | ||
| @@ -1197,7 +1229,9 @@ int _omap_hwmod_enable(struct omap_hwmod *oh) | |||
| 1197 | oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1) | 1229 | oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1) |
| 1198 | _deassert_hardreset(oh, oh->rst_lines[0].name); | 1230 | _deassert_hardreset(oh, oh->rst_lines[0].name); |
| 1199 | 1231 | ||
| 1200 | /* XXX mux balls */ | 1232 | /* Mux pins for device runtime if populated */ |
| 1233 | if (oh->mux) | ||
| 1234 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); | ||
| 1201 | 1235 | ||
| 1202 | _add_initiator_dep(oh, mpu_oh); | 1236 | _add_initiator_dep(oh, mpu_oh); |
| 1203 | _enable_clocks(oh); | 1237 | _enable_clocks(oh); |
| @@ -1213,6 +1247,7 @@ int _omap_hwmod_enable(struct omap_hwmod *oh) | |||
| 1213 | _enable_sysc(oh); | 1247 | _enable_sysc(oh); |
| 1214 | } | 1248 | } |
| 1215 | } else { | 1249 | } else { |
| 1250 | _disable_clocks(oh); | ||
| 1216 | pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", | 1251 | pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", |
| 1217 | oh->name, r); | 1252 | oh->name, r); |
| 1218 | } | 1253 | } |
| @@ -1221,16 +1256,14 @@ int _omap_hwmod_enable(struct omap_hwmod *oh) | |||
| 1221 | } | 1256 | } |
| 1222 | 1257 | ||
| 1223 | /** | 1258 | /** |
| 1224 | * _omap_hwmod_idle - idle an omap_hwmod | 1259 | * _idle - idle an omap_hwmod |
| 1225 | * @oh: struct omap_hwmod * | 1260 | * @oh: struct omap_hwmod * |
| 1226 | * | 1261 | * |
| 1227 | * Idles an omap_hwmod @oh. This should be called once the hwmod has | 1262 | * Idles an omap_hwmod @oh. This should be called once the hwmod has |
| 1228 | * no further work. (This function has a full name -- | 1263 | * no further work. Returns -EINVAL if the hwmod is in the wrong |
| 1229 | * _omap_hwmod_idle() rather than simply _idle() -- because it is | 1264 | * state or returns 0. |
| 1230 | * currently required by the pm34xx.c idle loop.) Returns -EINVAL if | ||
| 1231 | * the hwmod is in the wrong state or returns 0. | ||
| 1232 | */ | 1265 | */ |
| 1233 | int _omap_hwmod_idle(struct omap_hwmod *oh) | 1266 | static int _idle(struct omap_hwmod *oh) |
| 1234 | { | 1267 | { |
| 1235 | if (oh->_state != _HWMOD_STATE_ENABLED) { | 1268 | if (oh->_state != _HWMOD_STATE_ENABLED) { |
| 1236 | WARN(1, "omap_hwmod: %s: idle state can only be entered from " | 1269 | WARN(1, "omap_hwmod: %s: idle state can only be entered from " |
| @@ -1245,6 +1278,10 @@ int _omap_hwmod_idle(struct omap_hwmod *oh) | |||
| 1245 | _del_initiator_dep(oh, mpu_oh); | 1278 | _del_initiator_dep(oh, mpu_oh); |
| 1246 | _disable_clocks(oh); | 1279 | _disable_clocks(oh); |
| 1247 | 1280 | ||
| 1281 | /* Mux pins for device idle if populated */ | ||
| 1282 | if (oh->mux) | ||
| 1283 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE); | ||
| 1284 | |||
| 1248 | oh->_state = _HWMOD_STATE_IDLE; | 1285 | oh->_state = _HWMOD_STATE_IDLE; |
| 1249 | 1286 | ||
| 1250 | return 0; | 1287 | return 0; |
| @@ -1261,6 +1298,9 @@ int _omap_hwmod_idle(struct omap_hwmod *oh) | |||
| 1261 | */ | 1298 | */ |
| 1262 | static int _shutdown(struct omap_hwmod *oh) | 1299 | static int _shutdown(struct omap_hwmod *oh) |
| 1263 | { | 1300 | { |
| 1301 | int ret; | ||
| 1302 | u8 prev_state; | ||
| 1303 | |||
| 1264 | if (oh->_state != _HWMOD_STATE_IDLE && | 1304 | if (oh->_state != _HWMOD_STATE_IDLE && |
| 1265 | oh->_state != _HWMOD_STATE_ENABLED) { | 1305 | oh->_state != _HWMOD_STATE_ENABLED) { |
| 1266 | WARN(1, "omap_hwmod: %s: disabled state can only be entered " | 1306 | WARN(1, "omap_hwmod: %s: disabled state can only be entered " |
| @@ -1270,6 +1310,18 @@ static int _shutdown(struct omap_hwmod *oh) | |||
| 1270 | 1310 | ||
| 1271 | pr_debug("omap_hwmod: %s: disabling\n", oh->name); | 1311 | pr_debug("omap_hwmod: %s: disabling\n", oh->name); |
| 1272 | 1312 | ||
| 1313 | if (oh->class->pre_shutdown) { | ||
| 1314 | prev_state = oh->_state; | ||
| 1315 | if (oh->_state == _HWMOD_STATE_IDLE) | ||
| 1316 | _enable(oh); | ||
| 1317 | ret = oh->class->pre_shutdown(oh); | ||
| 1318 | if (ret) { | ||
| 1319 | if (prev_state == _HWMOD_STATE_IDLE) | ||
| 1320 | _idle(oh); | ||
| 1321 | return ret; | ||
| 1322 | } | ||
| 1323 | } | ||
| 1324 | |||
| 1273 | if (oh->class->sysc) | 1325 | if (oh->class->sysc) |
| 1274 | _shutdown_sysc(oh); | 1326 | _shutdown_sysc(oh); |
| 1275 | 1327 | ||
| @@ -1288,7 +1340,9 @@ static int _shutdown(struct omap_hwmod *oh) | |||
| 1288 | } | 1340 | } |
| 1289 | /* XXX Should this code also force-disable the optional clocks? */ | 1341 | /* XXX Should this code also force-disable the optional clocks? */ |
| 1290 | 1342 | ||
| 1291 | /* XXX mux any associated balls to safe mode */ | 1343 | /* Mux pins to safe mode or use populated off mode values */ |
| 1344 | if (oh->mux) | ||
| 1345 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED); | ||
| 1292 | 1346 | ||
| 1293 | oh->_state = _HWMOD_STATE_DISABLED; | 1347 | oh->_state = _HWMOD_STATE_DISABLED; |
| 1294 | 1348 | ||
| @@ -1298,23 +1352,15 @@ static int _shutdown(struct omap_hwmod *oh) | |||
| 1298 | /** | 1352 | /** |
| 1299 | * _setup - do initial configuration of omap_hwmod | 1353 | * _setup - do initial configuration of omap_hwmod |
| 1300 | * @oh: struct omap_hwmod * | 1354 | * @oh: struct omap_hwmod * |
| 1301 | * @skip_setup_idle_p: do not idle hwmods at the end of the fn if 1 | ||
| 1302 | * | 1355 | * |
| 1303 | * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh | 1356 | * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh |
| 1304 | * OCP_SYSCONFIG register. @skip_setup_idle is intended to be used on | 1357 | * OCP_SYSCONFIG register. Returns -EINVAL if the hwmod is in the |
| 1305 | * a system that will not call omap_hwmod_enable() to enable devices | 1358 | * wrong state or returns 0. |
| 1306 | * (e.g., a system without PM runtime). Returns -EINVAL if the hwmod | ||
| 1307 | * is in the wrong state or returns 0. | ||
| 1308 | */ | 1359 | */ |
| 1309 | static int _setup(struct omap_hwmod *oh, void *data) | 1360 | static int _setup(struct omap_hwmod *oh, void *data) |
| 1310 | { | 1361 | { |
| 1311 | int i, r; | 1362 | int i, r; |
| 1312 | u8 skip_setup_idle; | 1363 | u8 postsetup_state; |
| 1313 | |||
| 1314 | if (!oh || !data) | ||
| 1315 | return -EINVAL; | ||
| 1316 | |||
| 1317 | skip_setup_idle = *(u8 *)data; | ||
| 1318 | 1364 | ||
| 1319 | /* Set iclk autoidle mode */ | 1365 | /* Set iclk autoidle mode */ |
| 1320 | if (oh->slaves_cnt > 0) { | 1366 | if (oh->slaves_cnt > 0) { |
| @@ -1334,7 +1380,6 @@ static int _setup(struct omap_hwmod *oh, void *data) | |||
| 1334 | } | 1380 | } |
| 1335 | } | 1381 | } |
| 1336 | 1382 | ||
| 1337 | mutex_init(&oh->_mutex); | ||
| 1338 | oh->_state = _HWMOD_STATE_INITIALIZED; | 1383 | oh->_state = _HWMOD_STATE_INITIALIZED; |
| 1339 | 1384 | ||
| 1340 | /* | 1385 | /* |
| @@ -1347,7 +1392,7 @@ static int _setup(struct omap_hwmod *oh, void *data) | |||
| 1347 | if ((oh->flags & HWMOD_INIT_NO_RESET) && oh->rst_lines_cnt == 1) | 1392 | if ((oh->flags & HWMOD_INIT_NO_RESET) && oh->rst_lines_cnt == 1) |
| 1348 | return 0; | 1393 | return 0; |
| 1349 | 1394 | ||
| 1350 | r = _omap_hwmod_enable(oh); | 1395 | r = _enable(oh); |
| 1351 | if (r) { | 1396 | if (r) { |
| 1352 | pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n", | 1397 | pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n", |
| 1353 | oh->name, oh->_state); | 1398 | oh->name, oh->_state); |
| @@ -1359,7 +1404,7 @@ static int _setup(struct omap_hwmod *oh, void *data) | |||
| 1359 | 1404 | ||
| 1360 | /* | 1405 | /* |
| 1361 | * OCP_SYSCONFIG bits need to be reprogrammed after a softreset. | 1406 | * OCP_SYSCONFIG bits need to be reprogrammed after a softreset. |
| 1362 | * The _omap_hwmod_enable() function should be split to | 1407 | * The _enable() function should be split to |
| 1363 | * avoid the rewrite of the OCP_SYSCONFIG register. | 1408 | * avoid the rewrite of the OCP_SYSCONFIG register. |
| 1364 | */ | 1409 | */ |
| 1365 | if (oh->class->sysc) { | 1410 | if (oh->class->sysc) { |
| @@ -1368,12 +1413,77 @@ static int _setup(struct omap_hwmod *oh, void *data) | |||
| 1368 | } | 1413 | } |
| 1369 | } | 1414 | } |
| 1370 | 1415 | ||
| 1371 | if (!(oh->flags & HWMOD_INIT_NO_IDLE) && !skip_setup_idle) | 1416 | postsetup_state = oh->_postsetup_state; |
| 1372 | _omap_hwmod_idle(oh); | 1417 | if (postsetup_state == _HWMOD_STATE_UNKNOWN) |
| 1418 | postsetup_state = _HWMOD_STATE_ENABLED; | ||
| 1419 | |||
| 1420 | /* | ||
| 1421 | * XXX HWMOD_INIT_NO_IDLE does not belong in hwmod data - | ||
| 1422 | * it should be set by the core code as a runtime flag during startup | ||
| 1423 | */ | ||
| 1424 | if ((oh->flags & HWMOD_INIT_NO_IDLE) && | ||
| 1425 | (postsetup_state == _HWMOD_STATE_IDLE)) | ||
| 1426 | postsetup_state = _HWMOD_STATE_ENABLED; | ||
| 1427 | |||
| 1428 | if (postsetup_state == _HWMOD_STATE_IDLE) | ||
| 1429 | _idle(oh); | ||
| 1430 | else if (postsetup_state == _HWMOD_STATE_DISABLED) | ||
| 1431 | _shutdown(oh); | ||
| 1432 | else if (postsetup_state != _HWMOD_STATE_ENABLED) | ||
| 1433 | WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n", | ||
| 1434 | oh->name, postsetup_state); | ||
| 1373 | 1435 | ||
| 1374 | return 0; | 1436 | return 0; |
| 1375 | } | 1437 | } |
| 1376 | 1438 | ||
| 1439 | /** | ||
| 1440 | * _register - register a struct omap_hwmod | ||
| 1441 | * @oh: struct omap_hwmod * | ||
| 1442 | * | ||
| 1443 | * Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod | ||
| 1444 | * already has been registered by the same name; -EINVAL if the | ||
| 1445 | * omap_hwmod is in the wrong state, if @oh is NULL, if the | ||
| 1446 | * omap_hwmod's class field is NULL; if the omap_hwmod is missing a | ||
| 1447 | * name, or if the omap_hwmod's class is missing a name; or 0 upon | ||
| 1448 | * success. | ||
| 1449 | * | ||
| 1450 | * XXX The data should be copied into bootmem, so the original data | ||
| 1451 | * should be marked __initdata and freed after init. This would allow | ||
| 1452 | * unneeded omap_hwmods to be freed on multi-OMAP configurations. Note | ||
| 1453 | * that the copy process would be relatively complex due to the large number | ||
| 1454 | * of substructures. | ||
| 1455 | */ | ||
| 1456 | static int __init _register(struct omap_hwmod *oh) | ||
| 1457 | { | ||
| 1458 | int ret, ms_id; | ||
| 1459 | |||
| 1460 | if (!oh || !oh->name || !oh->class || !oh->class->name || | ||
| 1461 | (oh->_state != _HWMOD_STATE_UNKNOWN)) | ||
| 1462 | return -EINVAL; | ||
| 1463 | |||
| 1464 | pr_debug("omap_hwmod: %s: registering\n", oh->name); | ||
| 1465 | |||
| 1466 | if (_lookup(oh->name)) | ||
| 1467 | return -EEXIST; | ||
| 1468 | |||
| 1469 | ms_id = _find_mpu_port_index(oh); | ||
| 1470 | if (!IS_ERR_VALUE(ms_id)) { | ||
| 1471 | oh->_mpu_port_index = ms_id; | ||
| 1472 | oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index); | ||
| 1473 | } else { | ||
| 1474 | oh->_int_flags |= _HWMOD_NO_MPU_PORT; | ||
| 1475 | } | ||
| 1476 | |||
| 1477 | list_add_tail(&oh->node, &omap_hwmod_list); | ||
| 1478 | |||
| 1479 | spin_lock_init(&oh->_lock); | ||
| 1480 | |||
| 1481 | oh->_state = _HWMOD_STATE_REGISTERED; | ||
| 1482 | |||
| 1483 | ret = 0; | ||
| 1484 | |||
| 1485 | return ret; | ||
| 1486 | } | ||
| 1377 | 1487 | ||
| 1378 | 1488 | ||
| 1379 | /* Public functions */ | 1489 | /* Public functions */ |
| @@ -1427,59 +1537,6 @@ int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode) | |||
| 1427 | } | 1537 | } |
| 1428 | 1538 | ||
| 1429 | /** | 1539 | /** |
| 1430 | * omap_hwmod_register - register a struct omap_hwmod | ||
| 1431 | * @oh: struct omap_hwmod * | ||
| 1432 | * | ||
| 1433 | * Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod | ||
| 1434 | * already has been registered by the same name; -EINVAL if the | ||
| 1435 | * omap_hwmod is in the wrong state, if @oh is NULL, if the | ||
| 1436 | * omap_hwmod's class field is NULL; if the omap_hwmod is missing a | ||
| 1437 | * name, or if the omap_hwmod's class is missing a name; or 0 upon | ||
| 1438 | * success. | ||
| 1439 | * | ||
| 1440 | * XXX The data should be copied into bootmem, so the original data | ||
| 1441 | * should be marked __initdata and freed after init. This would allow | ||
| 1442 | * unneeded omap_hwmods to be freed on multi-OMAP configurations. Note | ||
| 1443 | * that the copy process would be relatively complex due to the large number | ||
| 1444 | * of substructures. | ||
| 1445 | */ | ||
| 1446 | int omap_hwmod_register(struct omap_hwmod *oh) | ||
| 1447 | { | ||
| 1448 | int ret, ms_id; | ||
| 1449 | |||
| 1450 | if (!oh || !oh->name || !oh->class || !oh->class->name || | ||
| 1451 | (oh->_state != _HWMOD_STATE_UNKNOWN)) | ||
| 1452 | return -EINVAL; | ||
| 1453 | |||
| 1454 | mutex_lock(&omap_hwmod_mutex); | ||
| 1455 | |||
| 1456 | pr_debug("omap_hwmod: %s: registering\n", oh->name); | ||
| 1457 | |||
| 1458 | if (_lookup(oh->name)) { | ||
| 1459 | ret = -EEXIST; | ||
| 1460 | goto ohr_unlock; | ||
| 1461 | } | ||
| 1462 | |||
| 1463 | ms_id = _find_mpu_port_index(oh); | ||
| 1464 | if (!IS_ERR_VALUE(ms_id)) { | ||
| 1465 | oh->_mpu_port_index = ms_id; | ||
| 1466 | oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index); | ||
| 1467 | } else { | ||
| 1468 | oh->_int_flags |= _HWMOD_NO_MPU_PORT; | ||
| 1469 | } | ||
| 1470 | |||
| 1471 | list_add_tail(&oh->node, &omap_hwmod_list); | ||
| 1472 | |||
| 1473 | oh->_state = _HWMOD_STATE_REGISTERED; | ||
| 1474 | |||
| 1475 | ret = 0; | ||
| 1476 | |||
| 1477 | ohr_unlock: | ||
| 1478 | mutex_unlock(&omap_hwmod_mutex); | ||
| 1479 | return ret; | ||
| 1480 | } | ||
| 1481 | |||
| 1482 | /** | ||
| 1483 | * omap_hwmod_lookup - look up a registered omap_hwmod by name | 1540 | * omap_hwmod_lookup - look up a registered omap_hwmod by name |
| 1484 | * @name: name of the omap_hwmod to look up | 1541 | * @name: name of the omap_hwmod to look up |
| 1485 | * | 1542 | * |
| @@ -1493,9 +1550,7 @@ struct omap_hwmod *omap_hwmod_lookup(const char *name) | |||
| 1493 | if (!name) | 1550 | if (!name) |
| 1494 | return NULL; | 1551 | return NULL; |
| 1495 | 1552 | ||
| 1496 | mutex_lock(&omap_hwmod_mutex); | ||
| 1497 | oh = _lookup(name); | 1553 | oh = _lookup(name); |
| 1498 | mutex_unlock(&omap_hwmod_mutex); | ||
| 1499 | 1554 | ||
| 1500 | return oh; | 1555 | return oh; |
| 1501 | } | 1556 | } |
| @@ -1521,13 +1576,11 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), | |||
| 1521 | if (!fn) | 1576 | if (!fn) |
| 1522 | return -EINVAL; | 1577 | return -EINVAL; |
| 1523 | 1578 | ||
| 1524 | mutex_lock(&omap_hwmod_mutex); | ||
| 1525 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { | 1579 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { |
| 1526 | ret = (*fn)(temp_oh, data); | 1580 | ret = (*fn)(temp_oh, data); |
| 1527 | if (ret) | 1581 | if (ret) |
| 1528 | break; | 1582 | break; |
| 1529 | } | 1583 | } |
| 1530 | mutex_unlock(&omap_hwmod_mutex); | ||
| 1531 | 1584 | ||
| 1532 | return ret; | 1585 | return ret; |
| 1533 | } | 1586 | } |
| @@ -1542,7 +1595,7 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), | |||
| 1542 | * listed in @ohs that are valid for this chip. Returns -EINVAL if | 1595 | * listed in @ohs that are valid for this chip. Returns -EINVAL if |
| 1543 | * omap_hwmod_init() has already been called or 0 otherwise. | 1596 | * omap_hwmod_init() has already been called or 0 otherwise. |
| 1544 | */ | 1597 | */ |
| 1545 | int omap_hwmod_init(struct omap_hwmod **ohs) | 1598 | int __init omap_hwmod_init(struct omap_hwmod **ohs) |
| 1546 | { | 1599 | { |
| 1547 | struct omap_hwmod *oh; | 1600 | struct omap_hwmod *oh; |
| 1548 | int r; | 1601 | int r; |
| @@ -1558,8 +1611,8 @@ int omap_hwmod_init(struct omap_hwmod **ohs) | |||
| 1558 | oh = *ohs; | 1611 | oh = *ohs; |
| 1559 | while (oh) { | 1612 | while (oh) { |
| 1560 | if (omap_chip_is(oh->omap_chip)) { | 1613 | if (omap_chip_is(oh->omap_chip)) { |
| 1561 | r = omap_hwmod_register(oh); | 1614 | r = _register(oh); |
| 1562 | WARN(r, "omap_hwmod: %s: omap_hwmod_register returned " | 1615 | WARN(r, "omap_hwmod: %s: _register returned " |
| 1563 | "%d\n", oh->name, r); | 1616 | "%d\n", oh->name, r); |
| 1564 | } | 1617 | } |
| 1565 | oh = *++ohs; | 1618 | oh = *++ohs; |
| @@ -1570,13 +1623,12 @@ int omap_hwmod_init(struct omap_hwmod **ohs) | |||
| 1570 | 1623 | ||
| 1571 | /** | 1624 | /** |
| 1572 | * omap_hwmod_late_init - do some post-clock framework initialization | 1625 | * omap_hwmod_late_init - do some post-clock framework initialization |
| 1573 | * @skip_setup_idle: if 1, do not idle hwmods in _setup() | ||
| 1574 | * | 1626 | * |
| 1575 | * Must be called after omap2_clk_init(). Resolves the struct clk names | 1627 | * Must be called after omap2_clk_init(). Resolves the struct clk names |
| 1576 | * to struct clk pointers for each registered omap_hwmod. Also calls | 1628 | * to struct clk pointers for each registered omap_hwmod. Also calls |
| 1577 | * _setup() on each hwmod. Returns 0. | 1629 | * _setup() on each hwmod. Returns 0. |
| 1578 | */ | 1630 | */ |
| 1579 | int omap_hwmod_late_init(u8 skip_setup_idle) | 1631 | int omap_hwmod_late_init(void) |
| 1580 | { | 1632 | { |
| 1581 | int r; | 1633 | int r; |
| 1582 | 1634 | ||
| @@ -1588,36 +1640,7 @@ int omap_hwmod_late_init(u8 skip_setup_idle) | |||
| 1588 | WARN(!mpu_oh, "omap_hwmod: could not find MPU initiator hwmod %s\n", | 1640 | WARN(!mpu_oh, "omap_hwmod: could not find MPU initiator hwmod %s\n", |
| 1589 | MPU_INITIATOR_NAME); | 1641 | MPU_INITIATOR_NAME); |
| 1590 | 1642 | ||
| 1591 | if (skip_setup_idle) | 1643 | omap_hwmod_for_each(_setup, NULL); |
| 1592 | pr_debug("omap_hwmod: will leave hwmods enabled during setup\n"); | ||
| 1593 | |||
| 1594 | omap_hwmod_for_each(_setup, &skip_setup_idle); | ||
| 1595 | |||
| 1596 | return 0; | ||
| 1597 | } | ||
| 1598 | |||
| 1599 | /** | ||
| 1600 | * omap_hwmod_unregister - unregister an omap_hwmod | ||
| 1601 | * @oh: struct omap_hwmod * | ||
| 1602 | * | ||
| 1603 | * Unregisters a previously-registered omap_hwmod @oh. There's probably | ||
| 1604 | * no use case for this, so it is likely to be removed in a later version. | ||
| 1605 | * | ||
| 1606 | * XXX Free all of the bootmem-allocated structures here when that is | ||
| 1607 | * implemented. Make it clear that core code is the only code that is | ||
| 1608 | * expected to unregister modules. | ||
| 1609 | */ | ||
| 1610 | int omap_hwmod_unregister(struct omap_hwmod *oh) | ||
| 1611 | { | ||
| 1612 | if (!oh) | ||
| 1613 | return -EINVAL; | ||
| 1614 | |||
| 1615 | pr_debug("omap_hwmod: %s: unregistering\n", oh->name); | ||
| 1616 | |||
| 1617 | mutex_lock(&omap_hwmod_mutex); | ||
| 1618 | iounmap(oh->_mpu_rt_va); | ||
| 1619 | list_del(&oh->node); | ||
| 1620 | mutex_unlock(&omap_hwmod_mutex); | ||
| 1621 | 1644 | ||
| 1622 | return 0; | 1645 | return 0; |
| 1623 | } | 1646 | } |
| @@ -1632,18 +1655,18 @@ int omap_hwmod_unregister(struct omap_hwmod *oh) | |||
| 1632 | int omap_hwmod_enable(struct omap_hwmod *oh) | 1655 | int omap_hwmod_enable(struct omap_hwmod *oh) |
| 1633 | { | 1656 | { |
| 1634 | int r; | 1657 | int r; |
| 1658 | unsigned long flags; | ||
| 1635 | 1659 | ||
| 1636 | if (!oh) | 1660 | if (!oh) |
| 1637 | return -EINVAL; | 1661 | return -EINVAL; |
| 1638 | 1662 | ||
| 1639 | mutex_lock(&oh->_mutex); | 1663 | spin_lock_irqsave(&oh->_lock, flags); |
| 1640 | r = _omap_hwmod_enable(oh); | 1664 | r = _enable(oh); |
| 1641 | mutex_unlock(&oh->_mutex); | 1665 | spin_unlock_irqrestore(&oh->_lock, flags); |
| 1642 | 1666 | ||
| 1643 | return r; | 1667 | return r; |
| 1644 | } | 1668 | } |
| 1645 | 1669 | ||
| 1646 | |||
| 1647 | /** | 1670 | /** |
| 1648 | * omap_hwmod_idle - idle an omap_hwmod | 1671 | * omap_hwmod_idle - idle an omap_hwmod |
| 1649 | * @oh: struct omap_hwmod * | 1672 | * @oh: struct omap_hwmod * |
| @@ -1653,12 +1676,14 @@ int omap_hwmod_enable(struct omap_hwmod *oh) | |||
| 1653 | */ | 1676 | */ |
| 1654 | int omap_hwmod_idle(struct omap_hwmod *oh) | 1677 | int omap_hwmod_idle(struct omap_hwmod *oh) |
| 1655 | { | 1678 | { |
| 1679 | unsigned long flags; | ||
| 1680 | |||
| 1656 | if (!oh) | 1681 | if (!oh) |
| 1657 | return -EINVAL; | 1682 | return -EINVAL; |
| 1658 | 1683 | ||
| 1659 | mutex_lock(&oh->_mutex); | 1684 | spin_lock_irqsave(&oh->_lock, flags); |
| 1660 | _omap_hwmod_idle(oh); | 1685 | _idle(oh); |
| 1661 | mutex_unlock(&oh->_mutex); | 1686 | spin_unlock_irqrestore(&oh->_lock, flags); |
| 1662 | 1687 | ||
| 1663 | return 0; | 1688 | return 0; |
| 1664 | } | 1689 | } |
| @@ -1673,12 +1698,14 @@ int omap_hwmod_idle(struct omap_hwmod *oh) | |||
| 1673 | */ | 1698 | */ |
| 1674 | int omap_hwmod_shutdown(struct omap_hwmod *oh) | 1699 | int omap_hwmod_shutdown(struct omap_hwmod *oh) |
| 1675 | { | 1700 | { |
| 1701 | unsigned long flags; | ||
| 1702 | |||
| 1676 | if (!oh) | 1703 | if (!oh) |
| 1677 | return -EINVAL; | 1704 | return -EINVAL; |
| 1678 | 1705 | ||
| 1679 | mutex_lock(&oh->_mutex); | 1706 | spin_lock_irqsave(&oh->_lock, flags); |
| 1680 | _shutdown(oh); | 1707 | _shutdown(oh); |
| 1681 | mutex_unlock(&oh->_mutex); | 1708 | spin_unlock_irqrestore(&oh->_lock, flags); |
| 1682 | 1709 | ||
| 1683 | return 0; | 1710 | return 0; |
| 1684 | } | 1711 | } |
| @@ -1691,9 +1718,11 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh) | |||
| 1691 | */ | 1718 | */ |
| 1692 | int omap_hwmod_enable_clocks(struct omap_hwmod *oh) | 1719 | int omap_hwmod_enable_clocks(struct omap_hwmod *oh) |
| 1693 | { | 1720 | { |
| 1694 | mutex_lock(&oh->_mutex); | 1721 | unsigned long flags; |
| 1722 | |||
| 1723 | spin_lock_irqsave(&oh->_lock, flags); | ||
| 1695 | _enable_clocks(oh); | 1724 | _enable_clocks(oh); |
| 1696 | mutex_unlock(&oh->_mutex); | 1725 | spin_unlock_irqrestore(&oh->_lock, flags); |
| 1697 | 1726 | ||
| 1698 | return 0; | 1727 | return 0; |
| 1699 | } | 1728 | } |
| @@ -1706,9 +1735,11 @@ int omap_hwmod_enable_clocks(struct omap_hwmod *oh) | |||
| 1706 | */ | 1735 | */ |
| 1707 | int omap_hwmod_disable_clocks(struct omap_hwmod *oh) | 1736 | int omap_hwmod_disable_clocks(struct omap_hwmod *oh) |
| 1708 | { | 1737 | { |
| 1709 | mutex_lock(&oh->_mutex); | 1738 | unsigned long flags; |
| 1739 | |||
| 1740 | spin_lock_irqsave(&oh->_lock, flags); | ||
| 1710 | _disable_clocks(oh); | 1741 | _disable_clocks(oh); |
| 1711 | mutex_unlock(&oh->_mutex); | 1742 | spin_unlock_irqrestore(&oh->_lock, flags); |
| 1712 | 1743 | ||
| 1713 | return 0; | 1744 | return 0; |
| 1714 | } | 1745 | } |
| @@ -1752,13 +1783,14 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh) | |||
| 1752 | int omap_hwmod_reset(struct omap_hwmod *oh) | 1783 | int omap_hwmod_reset(struct omap_hwmod *oh) |
| 1753 | { | 1784 | { |
| 1754 | int r; | 1785 | int r; |
| 1786 | unsigned long flags; | ||
| 1755 | 1787 | ||
| 1756 | if (!oh) | 1788 | if (!oh) |
| 1757 | return -EINVAL; | 1789 | return -EINVAL; |
| 1758 | 1790 | ||
| 1759 | mutex_lock(&oh->_mutex); | 1791 | spin_lock_irqsave(&oh->_lock, flags); |
| 1760 | r = _reset(oh); | 1792 | r = _reset(oh); |
| 1761 | mutex_unlock(&oh->_mutex); | 1793 | spin_unlock_irqrestore(&oh->_lock, flags); |
| 1762 | 1794 | ||
| 1763 | return r; | 1795 | return r; |
| 1764 | } | 1796 | } |
| @@ -1955,13 +1987,18 @@ int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh, | |||
| 1955 | */ | 1987 | */ |
| 1956 | int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) | 1988 | int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) |
| 1957 | { | 1989 | { |
| 1990 | unsigned long flags; | ||
| 1991 | u32 v; | ||
| 1992 | |||
| 1958 | if (!oh->class->sysc || | 1993 | if (!oh->class->sysc || |
| 1959 | !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) | 1994 | !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) |
| 1960 | return -EINVAL; | 1995 | return -EINVAL; |
| 1961 | 1996 | ||
| 1962 | mutex_lock(&oh->_mutex); | 1997 | spin_lock_irqsave(&oh->_lock, flags); |
| 1963 | _enable_wakeup(oh); | 1998 | v = oh->_sysc_cache; |
| 1964 | mutex_unlock(&oh->_mutex); | 1999 | _enable_wakeup(oh, &v); |
| 2000 | _write_sysconfig(v, oh); | ||
| 2001 | spin_unlock_irqrestore(&oh->_lock, flags); | ||
| 1965 | 2002 | ||
| 1966 | return 0; | 2003 | return 0; |
| 1967 | } | 2004 | } |
| @@ -1980,13 +2017,18 @@ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) | |||
| 1980 | */ | 2017 | */ |
| 1981 | int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) | 2018 | int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) |
| 1982 | { | 2019 | { |
| 2020 | unsigned long flags; | ||
| 2021 | u32 v; | ||
| 2022 | |||
| 1983 | if (!oh->class->sysc || | 2023 | if (!oh->class->sysc || |
| 1984 | !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) | 2024 | !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) |
| 1985 | return -EINVAL; | 2025 | return -EINVAL; |
| 1986 | 2026 | ||
| 1987 | mutex_lock(&oh->_mutex); | 2027 | spin_lock_irqsave(&oh->_lock, flags); |
| 1988 | _disable_wakeup(oh); | 2028 | v = oh->_sysc_cache; |
| 1989 | mutex_unlock(&oh->_mutex); | 2029 | _disable_wakeup(oh, &v); |
| 2030 | _write_sysconfig(v, oh); | ||
| 2031 | spin_unlock_irqrestore(&oh->_lock, flags); | ||
| 1990 | 2032 | ||
| 1991 | return 0; | 2033 | return 0; |
| 1992 | } | 2034 | } |
| @@ -2006,13 +2048,14 @@ int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) | |||
| 2006 | int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name) | 2048 | int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name) |
| 2007 | { | 2049 | { |
| 2008 | int ret; | 2050 | int ret; |
| 2051 | unsigned long flags; | ||
| 2009 | 2052 | ||
| 2010 | if (!oh) | 2053 | if (!oh) |
| 2011 | return -EINVAL; | 2054 | return -EINVAL; |
| 2012 | 2055 | ||
| 2013 | mutex_lock(&oh->_mutex); | 2056 | spin_lock_irqsave(&oh->_lock, flags); |
| 2014 | ret = _assert_hardreset(oh, name); | 2057 | ret = _assert_hardreset(oh, name); |
| 2015 | mutex_unlock(&oh->_mutex); | 2058 | spin_unlock_irqrestore(&oh->_lock, flags); |
| 2016 | 2059 | ||
| 2017 | return ret; | 2060 | return ret; |
| 2018 | } | 2061 | } |
| @@ -2032,13 +2075,14 @@ int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name) | |||
| 2032 | int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name) | 2075 | int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name) |
| 2033 | { | 2076 | { |
| 2034 | int ret; | 2077 | int ret; |
| 2078 | unsigned long flags; | ||
| 2035 | 2079 | ||
| 2036 | if (!oh) | 2080 | if (!oh) |
| 2037 | return -EINVAL; | 2081 | return -EINVAL; |
| 2038 | 2082 | ||
| 2039 | mutex_lock(&oh->_mutex); | 2083 | spin_lock_irqsave(&oh->_lock, flags); |
| 2040 | ret = _deassert_hardreset(oh, name); | 2084 | ret = _deassert_hardreset(oh, name); |
| 2041 | mutex_unlock(&oh->_mutex); | 2085 | spin_unlock_irqrestore(&oh->_lock, flags); |
| 2042 | 2086 | ||
| 2043 | return ret; | 2087 | return ret; |
| 2044 | } | 2088 | } |
| @@ -2057,13 +2101,14 @@ int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name) | |||
| 2057 | int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name) | 2101 | int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name) |
| 2058 | { | 2102 | { |
| 2059 | int ret; | 2103 | int ret; |
| 2104 | unsigned long flags; | ||
| 2060 | 2105 | ||
| 2061 | if (!oh) | 2106 | if (!oh) |
| 2062 | return -EINVAL; | 2107 | return -EINVAL; |
| 2063 | 2108 | ||
| 2064 | mutex_lock(&oh->_mutex); | 2109 | spin_lock_irqsave(&oh->_lock, flags); |
| 2065 | ret = _read_hardreset(oh, name); | 2110 | ret = _read_hardreset(oh, name); |
| 2066 | mutex_unlock(&oh->_mutex); | 2111 | spin_unlock_irqrestore(&oh->_lock, flags); |
| 2067 | 2112 | ||
| 2068 | return ret; | 2113 | return ret; |
| 2069 | } | 2114 | } |
| @@ -2075,9 +2120,8 @@ int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name) | |||
| 2075 | * @fn: callback function pointer to call for each hwmod in class @classname | 2120 | * @fn: callback function pointer to call for each hwmod in class @classname |
| 2076 | * @user: arbitrary context data to pass to the callback function | 2121 | * @user: arbitrary context data to pass to the callback function |
| 2077 | * | 2122 | * |
| 2078 | * For each omap_hwmod of class @classname, call @fn. Takes | 2123 | * For each omap_hwmod of class @classname, call @fn. |
| 2079 | * omap_hwmod_mutex to prevent the hwmod list from changing during the | 2124 | * If the callback function returns something other than |
| 2080 | * iteration. If the callback function returns something other than | ||
| 2081 | * zero, the iterator is terminated, and the callback function's return | 2125 | * zero, the iterator is terminated, and the callback function's return |
| 2082 | * value is passed back to the caller. Returns 0 upon success, -EINVAL | 2126 | * value is passed back to the caller. Returns 0 upon success, -EINVAL |
| 2083 | * if @classname or @fn are NULL, or passes back the error code from @fn. | 2127 | * if @classname or @fn are NULL, or passes back the error code from @fn. |
| @@ -2096,8 +2140,6 @@ int omap_hwmod_for_each_by_class(const char *classname, | |||
| 2096 | pr_debug("omap_hwmod: %s: looking for modules of class %s\n", | 2140 | pr_debug("omap_hwmod: %s: looking for modules of class %s\n", |
| 2097 | __func__, classname); | 2141 | __func__, classname); |
| 2098 | 2142 | ||
| 2099 | mutex_lock(&omap_hwmod_mutex); | ||
| 2100 | |||
| 2101 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { | 2143 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { |
| 2102 | if (!strcmp(temp_oh->class->name, classname)) { | 2144 | if (!strcmp(temp_oh->class->name, classname)) { |
| 2103 | pr_debug("omap_hwmod: %s: %s: calling callback fn\n", | 2145 | pr_debug("omap_hwmod: %s: %s: calling callback fn\n", |
| @@ -2108,8 +2150,6 @@ int omap_hwmod_for_each_by_class(const char *classname, | |||
| 2108 | } | 2150 | } |
| 2109 | } | 2151 | } |
| 2110 | 2152 | ||
| 2111 | mutex_unlock(&omap_hwmod_mutex); | ||
| 2112 | |||
| 2113 | if (ret) | 2153 | if (ret) |
| 2114 | pr_debug("omap_hwmod: %s: iterator terminated early: %d\n", | 2154 | pr_debug("omap_hwmod: %s: iterator terminated early: %d\n", |
| 2115 | __func__, ret); | 2155 | __func__, ret); |
| @@ -2117,3 +2157,64 @@ int omap_hwmod_for_each_by_class(const char *classname, | |||
| 2117 | return ret; | 2157 | return ret; |
| 2118 | } | 2158 | } |
| 2119 | 2159 | ||
| 2160 | /** | ||
| 2161 | * omap_hwmod_set_postsetup_state - set the post-_setup() state for this hwmod | ||
| 2162 | * @oh: struct omap_hwmod * | ||
| 2163 | * @state: state that _setup() should leave the hwmod in | ||
| 2164 | * | ||
| 2165 | * Sets the hwmod state that @oh will enter at the end of _setup() (called by | ||
| 2166 | * omap_hwmod_late_init()). Only valid to call between calls to | ||
| 2167 | * omap_hwmod_init() and omap_hwmod_late_init(). Returns 0 upon success or | ||
| 2168 | * -EINVAL if there is a problem with the arguments or if the hwmod is | ||
| 2169 | * in the wrong state. | ||
| 2170 | */ | ||
| 2171 | int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state) | ||
| 2172 | { | ||
| 2173 | int ret; | ||
| 2174 | unsigned long flags; | ||
| 2175 | |||
| 2176 | if (!oh) | ||
| 2177 | return -EINVAL; | ||
| 2178 | |||
| 2179 | if (state != _HWMOD_STATE_DISABLED && | ||
| 2180 | state != _HWMOD_STATE_ENABLED && | ||
| 2181 | state != _HWMOD_STATE_IDLE) | ||
| 2182 | return -EINVAL; | ||
| 2183 | |||
| 2184 | spin_lock_irqsave(&oh->_lock, flags); | ||
| 2185 | |||
| 2186 | if (oh->_state != _HWMOD_STATE_REGISTERED) { | ||
| 2187 | ret = -EINVAL; | ||
| 2188 | goto ohsps_unlock; | ||
| 2189 | } | ||
| 2190 | |||
| 2191 | oh->_postsetup_state = state; | ||
| 2192 | ret = 0; | ||
| 2193 | |||
| 2194 | ohsps_unlock: | ||
| 2195 | spin_unlock_irqrestore(&oh->_lock, flags); | ||
| 2196 | |||
| 2197 | return ret; | ||
| 2198 | } | ||
| 2199 | |||
| 2200 | /** | ||
| 2201 | * omap_hwmod_get_context_loss_count - get lost context count | ||
| 2202 | * @oh: struct omap_hwmod * | ||
| 2203 | * | ||
| 2204 | * Query the powerdomain of of @oh to get the context loss | ||
| 2205 | * count for this device. | ||
| 2206 | * | ||
| 2207 | * Returns the context loss count of the powerdomain assocated with @oh | ||
| 2208 | * upon success, or zero if no powerdomain exists for @oh. | ||
| 2209 | */ | ||
| 2210 | u32 omap_hwmod_get_context_loss_count(struct omap_hwmod *oh) | ||
| 2211 | { | ||
| 2212 | struct powerdomain *pwrdm; | ||
| 2213 | int ret = 0; | ||
| 2214 | |||
| 2215 | pwrdm = omap_hwmod_get_pwrdm(oh); | ||
| 2216 | if (pwrdm) | ||
| 2217 | ret = pwrdm_get_context_loss_count(pwrdm); | ||
| 2218 | |||
| 2219 | return ret; | ||
| 2220 | } | ||
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index adf6e3632a2b..b85c630b64d6 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c | |||
| @@ -16,11 +16,14 @@ | |||
| 16 | #include <plat/cpu.h> | 16 | #include <plat/cpu.h> |
| 17 | #include <plat/dma.h> | 17 | #include <plat/dma.h> |
| 18 | #include <plat/serial.h> | 18 | #include <plat/serial.h> |
| 19 | #include <plat/i2c.h> | ||
| 20 | #include <plat/gpio.h> | ||
| 19 | 21 | ||
| 20 | #include "omap_hwmod_common_data.h" | 22 | #include "omap_hwmod_common_data.h" |
| 21 | 23 | ||
| 22 | #include "prm-regbits-24xx.h" | ||
| 23 | #include "cm-regbits-24xx.h" | 24 | #include "cm-regbits-24xx.h" |
| 25 | #include "prm-regbits-24xx.h" | ||
| 26 | #include "wd_timer.h" | ||
| 24 | 27 | ||
| 25 | /* | 28 | /* |
| 26 | * OMAP2420 hardware module integration data | 29 | * OMAP2420 hardware module integration data |
| @@ -36,6 +39,11 @@ static struct omap_hwmod omap2420_iva_hwmod; | |||
| 36 | static struct omap_hwmod omap2420_l3_main_hwmod; | 39 | static struct omap_hwmod omap2420_l3_main_hwmod; |
| 37 | static struct omap_hwmod omap2420_l4_core_hwmod; | 40 | static struct omap_hwmod omap2420_l4_core_hwmod; |
| 38 | static struct omap_hwmod omap2420_wd_timer2_hwmod; | 41 | static struct omap_hwmod omap2420_wd_timer2_hwmod; |
| 42 | static struct omap_hwmod omap2420_gpio1_hwmod; | ||
| 43 | static struct omap_hwmod omap2420_gpio2_hwmod; | ||
| 44 | static struct omap_hwmod omap2420_gpio3_hwmod; | ||
| 45 | static struct omap_hwmod omap2420_gpio4_hwmod; | ||
| 46 | static struct omap_hwmod omap2420_dma_system_hwmod; | ||
| 39 | 47 | ||
| 40 | /* L3 -> L4_CORE interface */ | 48 | /* L3 -> L4_CORE interface */ |
| 41 | static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { | 49 | static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { |
| @@ -77,6 +85,8 @@ static struct omap_hwmod omap2420_l4_wkup_hwmod; | |||
| 77 | static struct omap_hwmod omap2420_uart1_hwmod; | 85 | static struct omap_hwmod omap2420_uart1_hwmod; |
| 78 | static struct omap_hwmod omap2420_uart2_hwmod; | 86 | static struct omap_hwmod omap2420_uart2_hwmod; |
| 79 | static struct omap_hwmod omap2420_uart3_hwmod; | 87 | static struct omap_hwmod omap2420_uart3_hwmod; |
| 88 | static struct omap_hwmod omap2420_i2c1_hwmod; | ||
| 89 | static struct omap_hwmod omap2420_i2c2_hwmod; | ||
| 80 | 90 | ||
| 81 | /* L4_CORE -> L4_WKUP interface */ | 91 | /* L4_CORE -> L4_WKUP interface */ |
| 82 | static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { | 92 | static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { |
| @@ -139,6 +149,45 @@ static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { | |||
| 139 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 149 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 140 | }; | 150 | }; |
| 141 | 151 | ||
| 152 | /* I2C IP block address space length (in bytes) */ | ||
| 153 | #define OMAP2_I2C_AS_LEN 128 | ||
| 154 | |||
| 155 | /* L4 CORE -> I2C1 interface */ | ||
| 156 | static struct omap_hwmod_addr_space omap2420_i2c1_addr_space[] = { | ||
| 157 | { | ||
| 158 | .pa_start = 0x48070000, | ||
| 159 | .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1, | ||
| 160 | .flags = ADDR_TYPE_RT, | ||
| 161 | }, | ||
| 162 | }; | ||
| 163 | |||
| 164 | static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { | ||
| 165 | .master = &omap2420_l4_core_hwmod, | ||
| 166 | .slave = &omap2420_i2c1_hwmod, | ||
| 167 | .clk = "i2c1_ick", | ||
| 168 | .addr = omap2420_i2c1_addr_space, | ||
| 169 | .addr_cnt = ARRAY_SIZE(omap2420_i2c1_addr_space), | ||
| 170 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 171 | }; | ||
| 172 | |||
| 173 | /* L4 CORE -> I2C2 interface */ | ||
| 174 | static struct omap_hwmod_addr_space omap2420_i2c2_addr_space[] = { | ||
| 175 | { | ||
| 176 | .pa_start = 0x48072000, | ||
| 177 | .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1, | ||
| 178 | .flags = ADDR_TYPE_RT, | ||
| 179 | }, | ||
| 180 | }; | ||
| 181 | |||
| 182 | static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { | ||
| 183 | .master = &omap2420_l4_core_hwmod, | ||
| 184 | .slave = &omap2420_i2c2_hwmod, | ||
| 185 | .clk = "i2c2_ick", | ||
| 186 | .addr = omap2420_i2c2_addr_space, | ||
| 187 | .addr_cnt = ARRAY_SIZE(omap2420_i2c2_addr_space), | ||
| 188 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 189 | }; | ||
| 190 | |||
| 142 | /* Slave interfaces on the L4_CORE interconnect */ | 191 | /* Slave interfaces on the L4_CORE interconnect */ |
| 143 | static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { | 192 | static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { |
| 144 | &omap2420_l3_main__l4_core, | 193 | &omap2420_l3_main__l4_core, |
| @@ -150,6 +199,8 @@ static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = { | |||
| 150 | &omap2_l4_core__uart1, | 199 | &omap2_l4_core__uart1, |
| 151 | &omap2_l4_core__uart2, | 200 | &omap2_l4_core__uart2, |
| 152 | &omap2_l4_core__uart3, | 201 | &omap2_l4_core__uart3, |
| 202 | &omap2420_l4_core__i2c1, | ||
| 203 | &omap2420_l4_core__i2c2 | ||
| 153 | }; | 204 | }; |
| 154 | 205 | ||
| 155 | /* L4 CORE */ | 206 | /* L4 CORE */ |
| @@ -262,8 +313,9 @@ static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = { | |||
| 262 | }; | 313 | }; |
| 263 | 314 | ||
| 264 | static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = { | 315 | static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = { |
| 265 | .name = "wd_timer", | 316 | .name = "wd_timer", |
| 266 | .sysc = &omap2420_wd_timer_sysc, | 317 | .sysc = &omap2420_wd_timer_sysc, |
| 318 | .pre_shutdown = &omap2_wd_timer_disable | ||
| 267 | }; | 319 | }; |
| 268 | 320 | ||
| 269 | /* wd_timer2 */ | 321 | /* wd_timer2 */ |
| @@ -418,6 +470,400 @@ static struct omap_hwmod omap2420_uart3_hwmod = { | |||
| 418 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | 470 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| 419 | }; | 471 | }; |
| 420 | 472 | ||
| 473 | /* I2C common */ | ||
| 474 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | ||
| 475 | .rev_offs = 0x00, | ||
| 476 | .sysc_offs = 0x20, | ||
| 477 | .syss_offs = 0x10, | ||
| 478 | .sysc_flags = SYSC_HAS_SOFTRESET, | ||
| 479 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
| 480 | }; | ||
| 481 | |||
| 482 | static struct omap_hwmod_class i2c_class = { | ||
| 483 | .name = "i2c", | ||
| 484 | .sysc = &i2c_sysc, | ||
| 485 | }; | ||
| 486 | |||
| 487 | static struct omap_i2c_dev_attr i2c_dev_attr; | ||
| 488 | |||
| 489 | /* I2C1 */ | ||
| 490 | |||
| 491 | static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { | ||
| 492 | { .irq = INT_24XX_I2C1_IRQ, }, | ||
| 493 | }; | ||
| 494 | |||
| 495 | static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { | ||
| 496 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, | ||
| 497 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, | ||
| 498 | }; | ||
| 499 | |||
| 500 | static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = { | ||
| 501 | &omap2420_l4_core__i2c1, | ||
| 502 | }; | ||
| 503 | |||
| 504 | static struct omap_hwmod omap2420_i2c1_hwmod = { | ||
| 505 | .name = "i2c1", | ||
| 506 | .mpu_irqs = i2c1_mpu_irqs, | ||
| 507 | .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), | ||
| 508 | .sdma_reqs = i2c1_sdma_reqs, | ||
| 509 | .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs), | ||
| 510 | .main_clk = "i2c1_fck", | ||
| 511 | .prcm = { | ||
| 512 | .omap2 = { | ||
| 513 | .module_offs = CORE_MOD, | ||
| 514 | .prcm_reg_id = 1, | ||
| 515 | .module_bit = OMAP2420_EN_I2C1_SHIFT, | ||
| 516 | .idlest_reg_id = 1, | ||
| 517 | .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT, | ||
| 518 | }, | ||
| 519 | }, | ||
| 520 | .slaves = omap2420_i2c1_slaves, | ||
| 521 | .slaves_cnt = ARRAY_SIZE(omap2420_i2c1_slaves), | ||
| 522 | .class = &i2c_class, | ||
| 523 | .dev_attr = &i2c_dev_attr, | ||
| 524 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | ||
| 525 | .flags = HWMOD_16BIT_REG, | ||
| 526 | }; | ||
| 527 | |||
| 528 | /* I2C2 */ | ||
| 529 | |||
| 530 | static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { | ||
| 531 | { .irq = INT_24XX_I2C2_IRQ, }, | ||
| 532 | }; | ||
| 533 | |||
| 534 | static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = { | ||
| 535 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, | ||
| 536 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, | ||
| 537 | }; | ||
| 538 | |||
| 539 | static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = { | ||
| 540 | &omap2420_l4_core__i2c2, | ||
| 541 | }; | ||
| 542 | |||
| 543 | static struct omap_hwmod omap2420_i2c2_hwmod = { | ||
| 544 | .name = "i2c2", | ||
| 545 | .mpu_irqs = i2c2_mpu_irqs, | ||
| 546 | .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), | ||
| 547 | .sdma_reqs = i2c2_sdma_reqs, | ||
| 548 | .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs), | ||
| 549 | .main_clk = "i2c2_fck", | ||
| 550 | .prcm = { | ||
| 551 | .omap2 = { | ||
| 552 | .module_offs = CORE_MOD, | ||
| 553 | .prcm_reg_id = 1, | ||
| 554 | .module_bit = OMAP2420_EN_I2C2_SHIFT, | ||
| 555 | .idlest_reg_id = 1, | ||
| 556 | .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT, | ||
| 557 | }, | ||
| 558 | }, | ||
| 559 | .slaves = omap2420_i2c2_slaves, | ||
| 560 | .slaves_cnt = ARRAY_SIZE(omap2420_i2c2_slaves), | ||
| 561 | .class = &i2c_class, | ||
| 562 | .dev_attr = &i2c_dev_attr, | ||
| 563 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | ||
| 564 | .flags = HWMOD_16BIT_REG, | ||
| 565 | }; | ||
| 566 | |||
| 567 | /* l4_wkup -> gpio1 */ | ||
| 568 | static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = { | ||
| 569 | { | ||
| 570 | .pa_start = 0x48018000, | ||
| 571 | .pa_end = 0x480181ff, | ||
| 572 | .flags = ADDR_TYPE_RT | ||
| 573 | }, | ||
| 574 | }; | ||
| 575 | |||
| 576 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { | ||
| 577 | .master = &omap2420_l4_wkup_hwmod, | ||
| 578 | .slave = &omap2420_gpio1_hwmod, | ||
| 579 | .clk = "gpios_ick", | ||
| 580 | .addr = omap2420_gpio1_addr_space, | ||
| 581 | .addr_cnt = ARRAY_SIZE(omap2420_gpio1_addr_space), | ||
| 582 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 583 | }; | ||
| 584 | |||
| 585 | /* l4_wkup -> gpio2 */ | ||
| 586 | static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = { | ||
| 587 | { | ||
| 588 | .pa_start = 0x4801a000, | ||
| 589 | .pa_end = 0x4801a1ff, | ||
| 590 | .flags = ADDR_TYPE_RT | ||
| 591 | }, | ||
| 592 | }; | ||
| 593 | |||
| 594 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { | ||
| 595 | .master = &omap2420_l4_wkup_hwmod, | ||
| 596 | .slave = &omap2420_gpio2_hwmod, | ||
| 597 | .clk = "gpios_ick", | ||
| 598 | .addr = omap2420_gpio2_addr_space, | ||
| 599 | .addr_cnt = ARRAY_SIZE(omap2420_gpio2_addr_space), | ||
| 600 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 601 | }; | ||
| 602 | |||
| 603 | /* l4_wkup -> gpio3 */ | ||
| 604 | static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = { | ||
| 605 | { | ||
| 606 | .pa_start = 0x4801c000, | ||
| 607 | .pa_end = 0x4801c1ff, | ||
| 608 | .flags = ADDR_TYPE_RT | ||
| 609 | }, | ||
| 610 | }; | ||
| 611 | |||
| 612 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { | ||
| 613 | .master = &omap2420_l4_wkup_hwmod, | ||
| 614 | .slave = &omap2420_gpio3_hwmod, | ||
| 615 | .clk = "gpios_ick", | ||
| 616 | .addr = omap2420_gpio3_addr_space, | ||
| 617 | .addr_cnt = ARRAY_SIZE(omap2420_gpio3_addr_space), | ||
| 618 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 619 | }; | ||
| 620 | |||
| 621 | /* l4_wkup -> gpio4 */ | ||
| 622 | static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = { | ||
| 623 | { | ||
| 624 | .pa_start = 0x4801e000, | ||
| 625 | .pa_end = 0x4801e1ff, | ||
| 626 | .flags = ADDR_TYPE_RT | ||
| 627 | }, | ||
| 628 | }; | ||
| 629 | |||
| 630 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { | ||
| 631 | .master = &omap2420_l4_wkup_hwmod, | ||
| 632 | .slave = &omap2420_gpio4_hwmod, | ||
| 633 | .clk = "gpios_ick", | ||
| 634 | .addr = omap2420_gpio4_addr_space, | ||
| 635 | .addr_cnt = ARRAY_SIZE(omap2420_gpio4_addr_space), | ||
| 636 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 637 | }; | ||
| 638 | |||
| 639 | /* gpio dev_attr */ | ||
| 640 | static struct omap_gpio_dev_attr gpio_dev_attr = { | ||
| 641 | .bank_width = 32, | ||
| 642 | .dbck_flag = false, | ||
| 643 | }; | ||
| 644 | |||
| 645 | static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = { | ||
| 646 | .rev_offs = 0x0000, | ||
| 647 | .sysc_offs = 0x0010, | ||
| 648 | .syss_offs = 0x0014, | ||
| 649 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | ||
| 650 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | ||
| 651 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
| 652 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
| 653 | }; | ||
| 654 | |||
| 655 | /* | ||
| 656 | * 'gpio' class | ||
| 657 | * general purpose io module | ||
| 658 | */ | ||
| 659 | static struct omap_hwmod_class omap242x_gpio_hwmod_class = { | ||
| 660 | .name = "gpio", | ||
| 661 | .sysc = &omap242x_gpio_sysc, | ||
| 662 | .rev = 0, | ||
| 663 | }; | ||
| 664 | |||
| 665 | /* gpio1 */ | ||
| 666 | static struct omap_hwmod_irq_info omap242x_gpio1_irqs[] = { | ||
| 667 | { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */ | ||
| 668 | }; | ||
| 669 | |||
| 670 | static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = { | ||
| 671 | &omap2420_l4_wkup__gpio1, | ||
| 672 | }; | ||
| 673 | |||
| 674 | static struct omap_hwmod omap2420_gpio1_hwmod = { | ||
| 675 | .name = "gpio1", | ||
| 676 | .mpu_irqs = omap242x_gpio1_irqs, | ||
| 677 | .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio1_irqs), | ||
| 678 | .main_clk = "gpios_fck", | ||
| 679 | .prcm = { | ||
| 680 | .omap2 = { | ||
| 681 | .prcm_reg_id = 1, | ||
| 682 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | ||
| 683 | .module_offs = WKUP_MOD, | ||
| 684 | .idlest_reg_id = 1, | ||
| 685 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | ||
| 686 | }, | ||
| 687 | }, | ||
| 688 | .slaves = omap2420_gpio1_slaves, | ||
| 689 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves), | ||
| 690 | .class = &omap242x_gpio_hwmod_class, | ||
| 691 | .dev_attr = &gpio_dev_attr, | ||
| 692 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | ||
| 693 | }; | ||
| 694 | |||
| 695 | /* gpio2 */ | ||
| 696 | static struct omap_hwmod_irq_info omap242x_gpio2_irqs[] = { | ||
| 697 | { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */ | ||
| 698 | }; | ||
| 699 | |||
| 700 | static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = { | ||
| 701 | &omap2420_l4_wkup__gpio2, | ||
| 702 | }; | ||
| 703 | |||
| 704 | static struct omap_hwmod omap2420_gpio2_hwmod = { | ||
| 705 | .name = "gpio2", | ||
| 706 | .mpu_irqs = omap242x_gpio2_irqs, | ||
| 707 | .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio2_irqs), | ||
| 708 | .main_clk = "gpios_fck", | ||
| 709 | .prcm = { | ||
| 710 | .omap2 = { | ||
| 711 | .prcm_reg_id = 1, | ||
| 712 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | ||
| 713 | .module_offs = WKUP_MOD, | ||
| 714 | .idlest_reg_id = 1, | ||
| 715 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | ||
| 716 | }, | ||
| 717 | }, | ||
| 718 | .slaves = omap2420_gpio2_slaves, | ||
| 719 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves), | ||
| 720 | .class = &omap242x_gpio_hwmod_class, | ||
| 721 | .dev_attr = &gpio_dev_attr, | ||
| 722 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | ||
| 723 | }; | ||
| 724 | |||
| 725 | /* gpio3 */ | ||
| 726 | static struct omap_hwmod_irq_info omap242x_gpio3_irqs[] = { | ||
| 727 | { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */ | ||
| 728 | }; | ||
| 729 | |||
| 730 | static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = { | ||
| 731 | &omap2420_l4_wkup__gpio3, | ||
| 732 | }; | ||
| 733 | |||
| 734 | static struct omap_hwmod omap2420_gpio3_hwmod = { | ||
| 735 | .name = "gpio3", | ||
| 736 | .mpu_irqs = omap242x_gpio3_irqs, | ||
| 737 | .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio3_irqs), | ||
| 738 | .main_clk = "gpios_fck", | ||
| 739 | .prcm = { | ||
| 740 | .omap2 = { | ||
| 741 | .prcm_reg_id = 1, | ||
| 742 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | ||
| 743 | .module_offs = WKUP_MOD, | ||
| 744 | .idlest_reg_id = 1, | ||
| 745 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | ||
| 746 | }, | ||
| 747 | }, | ||
| 748 | .slaves = omap2420_gpio3_slaves, | ||
| 749 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves), | ||
| 750 | .class = &omap242x_gpio_hwmod_class, | ||
| 751 | .dev_attr = &gpio_dev_attr, | ||
| 752 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | ||
| 753 | }; | ||
| 754 | |||
| 755 | /* gpio4 */ | ||
| 756 | static struct omap_hwmod_irq_info omap242x_gpio4_irqs[] = { | ||
| 757 | { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */ | ||
| 758 | }; | ||
| 759 | |||
| 760 | static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = { | ||
| 761 | &omap2420_l4_wkup__gpio4, | ||
| 762 | }; | ||
| 763 | |||
| 764 | static struct omap_hwmod omap2420_gpio4_hwmod = { | ||
| 765 | .name = "gpio4", | ||
| 766 | .mpu_irqs = omap242x_gpio4_irqs, | ||
| 767 | .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio4_irqs), | ||
| 768 | .main_clk = "gpios_fck", | ||
| 769 | .prcm = { | ||
| 770 | .omap2 = { | ||
| 771 | .prcm_reg_id = 1, | ||
| 772 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | ||
| 773 | .module_offs = WKUP_MOD, | ||
| 774 | .idlest_reg_id = 1, | ||
| 775 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | ||
| 776 | }, | ||
| 777 | }, | ||
| 778 | .slaves = omap2420_gpio4_slaves, | ||
| 779 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves), | ||
| 780 | .class = &omap242x_gpio_hwmod_class, | ||
| 781 | .dev_attr = &gpio_dev_attr, | ||
| 782 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | ||
| 783 | }; | ||
| 784 | |||
| 785 | /* system dma */ | ||
| 786 | static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = { | ||
| 787 | .rev_offs = 0x0000, | ||
| 788 | .sysc_offs = 0x002c, | ||
| 789 | .syss_offs = 0x0028, | ||
| 790 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE | | ||
| 791 | SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE | | ||
| 792 | SYSC_HAS_AUTOIDLE), | ||
| 793 | .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | ||
| 794 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
| 795 | }; | ||
| 796 | |||
| 797 | static struct omap_hwmod_class omap2420_dma_hwmod_class = { | ||
| 798 | .name = "dma", | ||
| 799 | .sysc = &omap2420_dma_sysc, | ||
| 800 | }; | ||
| 801 | |||
| 802 | /* dma attributes */ | ||
| 803 | static struct omap_dma_dev_attr dma_dev_attr = { | ||
| 804 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | ||
| 805 | IS_CSSA_32 | IS_CDSA_32, | ||
| 806 | .lch_count = 32, | ||
| 807 | }; | ||
| 808 | |||
| 809 | static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = { | ||
| 810 | { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */ | ||
| 811 | { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */ | ||
| 812 | { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */ | ||
| 813 | { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */ | ||
| 814 | }; | ||
| 815 | |||
| 816 | static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = { | ||
| 817 | { | ||
| 818 | .pa_start = 0x48056000, | ||
| 819 | .pa_end = 0x4a0560ff, | ||
| 820 | .flags = ADDR_TYPE_RT | ||
| 821 | }, | ||
| 822 | }; | ||
| 823 | |||
| 824 | /* dma_system -> L3 */ | ||
| 825 | static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = { | ||
| 826 | .master = &omap2420_dma_system_hwmod, | ||
| 827 | .slave = &omap2420_l3_main_hwmod, | ||
| 828 | .clk = "core_l3_ck", | ||
| 829 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 830 | }; | ||
| 831 | |||
| 832 | /* dma_system master ports */ | ||
| 833 | static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = { | ||
| 834 | &omap2420_dma_system__l3, | ||
| 835 | }; | ||
| 836 | |||
| 837 | /* l4_core -> dma_system */ | ||
| 838 | static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = { | ||
| 839 | .master = &omap2420_l4_core_hwmod, | ||
| 840 | .slave = &omap2420_dma_system_hwmod, | ||
| 841 | .clk = "sdma_ick", | ||
| 842 | .addr = omap2420_dma_system_addrs, | ||
| 843 | .addr_cnt = ARRAY_SIZE(omap2420_dma_system_addrs), | ||
| 844 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 845 | }; | ||
| 846 | |||
| 847 | /* dma_system slave ports */ | ||
| 848 | static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = { | ||
| 849 | &omap2420_l4_core__dma_system, | ||
| 850 | }; | ||
| 851 | |||
| 852 | static struct omap_hwmod omap2420_dma_system_hwmod = { | ||
| 853 | .name = "dma", | ||
| 854 | .class = &omap2420_dma_hwmod_class, | ||
| 855 | .mpu_irqs = omap2420_dma_system_irqs, | ||
| 856 | .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dma_system_irqs), | ||
| 857 | .main_clk = "core_l3_ck", | ||
| 858 | .slaves = omap2420_dma_system_slaves, | ||
| 859 | .slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves), | ||
| 860 | .masters = omap2420_dma_system_masters, | ||
| 861 | .masters_cnt = ARRAY_SIZE(omap2420_dma_system_masters), | ||
| 862 | .dev_attr = &dma_dev_attr, | ||
| 863 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | ||
| 864 | .flags = HWMOD_NO_IDLEST, | ||
| 865 | }; | ||
| 866 | |||
| 421 | static __initdata struct omap_hwmod *omap2420_hwmods[] = { | 867 | static __initdata struct omap_hwmod *omap2420_hwmods[] = { |
| 422 | &omap2420_l3_main_hwmod, | 868 | &omap2420_l3_main_hwmod, |
| 423 | &omap2420_l4_core_hwmod, | 869 | &omap2420_l4_core_hwmod, |
| @@ -428,6 +874,17 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = { | |||
| 428 | &omap2420_uart1_hwmod, | 874 | &omap2420_uart1_hwmod, |
| 429 | &omap2420_uart2_hwmod, | 875 | &omap2420_uart2_hwmod, |
| 430 | &omap2420_uart3_hwmod, | 876 | &omap2420_uart3_hwmod, |
| 877 | &omap2420_i2c1_hwmod, | ||
| 878 | &omap2420_i2c2_hwmod, | ||
| 879 | |||
| 880 | /* gpio class */ | ||
| 881 | &omap2420_gpio1_hwmod, | ||
| 882 | &omap2420_gpio2_hwmod, | ||
| 883 | &omap2420_gpio3_hwmod, | ||
| 884 | &omap2420_gpio4_hwmod, | ||
| 885 | |||
| 886 | /* dma_system class*/ | ||
| 887 | &omap2420_dma_system_hwmod, | ||
| 431 | NULL, | 888 | NULL, |
| 432 | }; | 889 | }; |
| 433 | 890 | ||
| @@ -435,5 +892,3 @@ int __init omap2420_hwmod_init(void) | |||
| 435 | { | 892 | { |
| 436 | return omap_hwmod_init(omap2420_hwmods); | 893 | return omap_hwmod_init(omap2420_hwmods); |
| 437 | } | 894 | } |
| 438 | |||
| 439 | |||
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 12d939e456cf..8ecfbcde13ba 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c | |||
| @@ -16,11 +16,14 @@ | |||
| 16 | #include <plat/cpu.h> | 16 | #include <plat/cpu.h> |
| 17 | #include <plat/dma.h> | 17 | #include <plat/dma.h> |
| 18 | #include <plat/serial.h> | 18 | #include <plat/serial.h> |
| 19 | #include <plat/i2c.h> | ||
| 20 | #include <plat/gpio.h> | ||
| 19 | 21 | ||
| 20 | #include "omap_hwmod_common_data.h" | 22 | #include "omap_hwmod_common_data.h" |
| 21 | 23 | ||
| 22 | #include "prm-regbits-24xx.h" | 24 | #include "prm-regbits-24xx.h" |
| 23 | #include "cm-regbits-24xx.h" | 25 | #include "cm-regbits-24xx.h" |
| 26 | #include "wd_timer.h" | ||
| 24 | 27 | ||
| 25 | /* | 28 | /* |
| 26 | * OMAP2430 hardware module integration data | 29 | * OMAP2430 hardware module integration data |
| @@ -36,6 +39,12 @@ static struct omap_hwmod omap2430_iva_hwmod; | |||
| 36 | static struct omap_hwmod omap2430_l3_main_hwmod; | 39 | static struct omap_hwmod omap2430_l3_main_hwmod; |
| 37 | static struct omap_hwmod omap2430_l4_core_hwmod; | 40 | static struct omap_hwmod omap2430_l4_core_hwmod; |
| 38 | static struct omap_hwmod omap2430_wd_timer2_hwmod; | 41 | static struct omap_hwmod omap2430_wd_timer2_hwmod; |
| 42 | static struct omap_hwmod omap2430_gpio1_hwmod; | ||
| 43 | static struct omap_hwmod omap2430_gpio2_hwmod; | ||
| 44 | static struct omap_hwmod omap2430_gpio3_hwmod; | ||
| 45 | static struct omap_hwmod omap2430_gpio4_hwmod; | ||
| 46 | static struct omap_hwmod omap2430_gpio5_hwmod; | ||
| 47 | static struct omap_hwmod omap2430_dma_system_hwmod; | ||
| 39 | 48 | ||
| 40 | /* L3 -> L4_CORE interface */ | 49 | /* L3 -> L4_CORE interface */ |
| 41 | static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { | 50 | static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { |
| @@ -77,6 +86,47 @@ static struct omap_hwmod omap2430_l4_wkup_hwmod; | |||
| 77 | static struct omap_hwmod omap2430_uart1_hwmod; | 86 | static struct omap_hwmod omap2430_uart1_hwmod; |
| 78 | static struct omap_hwmod omap2430_uart2_hwmod; | 87 | static struct omap_hwmod omap2430_uart2_hwmod; |
| 79 | static struct omap_hwmod omap2430_uart3_hwmod; | 88 | static struct omap_hwmod omap2430_uart3_hwmod; |
| 89 | static struct omap_hwmod omap2430_i2c1_hwmod; | ||
| 90 | static struct omap_hwmod omap2430_i2c2_hwmod; | ||
| 91 | |||
| 92 | /* I2C IP block address space length (in bytes) */ | ||
| 93 | #define OMAP2_I2C_AS_LEN 128 | ||
| 94 | |||
| 95 | /* L4 CORE -> I2C1 interface */ | ||
| 96 | static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = { | ||
| 97 | { | ||
| 98 | .pa_start = 0x48070000, | ||
| 99 | .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1, | ||
| 100 | .flags = ADDR_TYPE_RT, | ||
| 101 | }, | ||
| 102 | }; | ||
| 103 | |||
| 104 | static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { | ||
| 105 | .master = &omap2430_l4_core_hwmod, | ||
| 106 | .slave = &omap2430_i2c1_hwmod, | ||
| 107 | .clk = "i2c1_ick", | ||
| 108 | .addr = omap2430_i2c1_addr_space, | ||
| 109 | .addr_cnt = ARRAY_SIZE(omap2430_i2c1_addr_space), | ||
| 110 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 111 | }; | ||
| 112 | |||
| 113 | /* L4 CORE -> I2C2 interface */ | ||
| 114 | static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = { | ||
| 115 | { | ||
| 116 | .pa_start = 0x48072000, | ||
| 117 | .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1, | ||
| 118 | .flags = ADDR_TYPE_RT, | ||
| 119 | }, | ||
| 120 | }; | ||
| 121 | |||
| 122 | static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { | ||
| 123 | .master = &omap2430_l4_core_hwmod, | ||
| 124 | .slave = &omap2430_i2c2_hwmod, | ||
| 125 | .clk = "i2c2_ick", | ||
| 126 | .addr = omap2430_i2c2_addr_space, | ||
| 127 | .addr_cnt = ARRAY_SIZE(omap2430_i2c2_addr_space), | ||
| 128 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 129 | }; | ||
| 80 | 130 | ||
| 81 | /* L4_CORE -> L4_WKUP interface */ | 131 | /* L4_CORE -> L4_WKUP interface */ |
| 82 | static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { | 132 | static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { |
| @@ -262,8 +312,9 @@ static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = { | |||
| 262 | }; | 312 | }; |
| 263 | 313 | ||
| 264 | static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = { | 314 | static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = { |
| 265 | .name = "wd_timer", | 315 | .name = "wd_timer", |
| 266 | .sysc = &omap2430_wd_timer_sysc, | 316 | .sysc = &omap2430_wd_timer_sysc, |
| 317 | .pre_shutdown = &omap2_wd_timer_disable | ||
| 267 | }; | 318 | }; |
| 268 | 319 | ||
| 269 | /* wd_timer2 */ | 320 | /* wd_timer2 */ |
| @@ -418,6 +469,456 @@ static struct omap_hwmod omap2430_uart3_hwmod = { | |||
| 418 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | 469 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
| 419 | }; | 470 | }; |
| 420 | 471 | ||
| 472 | /* I2C common */ | ||
| 473 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | ||
| 474 | .rev_offs = 0x00, | ||
| 475 | .sysc_offs = 0x20, | ||
| 476 | .syss_offs = 0x10, | ||
| 477 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | ||
| 478 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
| 479 | }; | ||
| 480 | |||
| 481 | static struct omap_hwmod_class i2c_class = { | ||
| 482 | .name = "i2c", | ||
| 483 | .sysc = &i2c_sysc, | ||
| 484 | }; | ||
| 485 | |||
| 486 | static struct omap_i2c_dev_attr i2c_dev_attr = { | ||
| 487 | .fifo_depth = 8, /* bytes */ | ||
| 488 | }; | ||
| 489 | |||
| 490 | /* I2C1 */ | ||
| 491 | |||
| 492 | static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { | ||
| 493 | { .irq = INT_24XX_I2C1_IRQ, }, | ||
| 494 | }; | ||
| 495 | |||
| 496 | static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { | ||
| 497 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, | ||
| 498 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, | ||
| 499 | }; | ||
| 500 | |||
| 501 | static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = { | ||
| 502 | &omap2430_l4_core__i2c1, | ||
| 503 | }; | ||
| 504 | |||
| 505 | static struct omap_hwmod omap2430_i2c1_hwmod = { | ||
| 506 | .name = "i2c1", | ||
| 507 | .mpu_irqs = i2c1_mpu_irqs, | ||
| 508 | .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), | ||
| 509 | .sdma_reqs = i2c1_sdma_reqs, | ||
| 510 | .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs), | ||
| 511 | .main_clk = "i2chs1_fck", | ||
| 512 | .prcm = { | ||
| 513 | .omap2 = { | ||
| 514 | /* | ||
| 515 | * NOTE: The CM_FCLKEN* and CM_ICLKEN* for | ||
| 516 | * I2CHS IP's do not follow the usual pattern. | ||
| 517 | * prcm_reg_id alone cannot be used to program | ||
| 518 | * the iclk and fclk. Needs to be handled using | ||
| 519 | * additonal flags when clk handling is moved | ||
| 520 | * to hwmod framework. | ||
| 521 | */ | ||
| 522 | .module_offs = CORE_MOD, | ||
| 523 | .prcm_reg_id = 1, | ||
| 524 | .module_bit = OMAP2430_EN_I2CHS1_SHIFT, | ||
| 525 | .idlest_reg_id = 1, | ||
| 526 | .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, | ||
| 527 | }, | ||
| 528 | }, | ||
| 529 | .slaves = omap2430_i2c1_slaves, | ||
| 530 | .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves), | ||
| 531 | .class = &i2c_class, | ||
| 532 | .dev_attr = &i2c_dev_attr, | ||
| 533 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | ||
| 534 | }; | ||
| 535 | |||
| 536 | /* I2C2 */ | ||
| 537 | |||
| 538 | static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { | ||
| 539 | { .irq = INT_24XX_I2C2_IRQ, }, | ||
| 540 | }; | ||
| 541 | |||
| 542 | static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = { | ||
| 543 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, | ||
| 544 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, | ||
| 545 | }; | ||
| 546 | |||
| 547 | static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = { | ||
| 548 | &omap2430_l4_core__i2c2, | ||
| 549 | }; | ||
| 550 | |||
| 551 | static struct omap_hwmod omap2430_i2c2_hwmod = { | ||
| 552 | .name = "i2c2", | ||
| 553 | .mpu_irqs = i2c2_mpu_irqs, | ||
| 554 | .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), | ||
| 555 | .sdma_reqs = i2c2_sdma_reqs, | ||
| 556 | .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs), | ||
| 557 | .main_clk = "i2chs2_fck", | ||
| 558 | .prcm = { | ||
| 559 | .omap2 = { | ||
| 560 | .module_offs = CORE_MOD, | ||
| 561 | .prcm_reg_id = 1, | ||
| 562 | .module_bit = OMAP2430_EN_I2CHS2_SHIFT, | ||
| 563 | .idlest_reg_id = 1, | ||
| 564 | .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, | ||
| 565 | }, | ||
| 566 | }, | ||
| 567 | .slaves = omap2430_i2c2_slaves, | ||
| 568 | .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves), | ||
| 569 | .class = &i2c_class, | ||
| 570 | .dev_attr = &i2c_dev_attr, | ||
| 571 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | ||
| 572 | }; | ||
| 573 | |||
| 574 | /* l4_wkup -> gpio1 */ | ||
| 575 | static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { | ||
| 576 | { | ||
| 577 | .pa_start = 0x4900C000, | ||
| 578 | .pa_end = 0x4900C1ff, | ||
| 579 | .flags = ADDR_TYPE_RT | ||
| 580 | }, | ||
| 581 | }; | ||
| 582 | |||
| 583 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { | ||
| 584 | .master = &omap2430_l4_wkup_hwmod, | ||
| 585 | .slave = &omap2430_gpio1_hwmod, | ||
| 586 | .clk = "gpios_ick", | ||
| 587 | .addr = omap2430_gpio1_addr_space, | ||
| 588 | .addr_cnt = ARRAY_SIZE(omap2430_gpio1_addr_space), | ||
| 589 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 590 | }; | ||
| 591 | |||
| 592 | /* l4_wkup -> gpio2 */ | ||
| 593 | static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { | ||
| 594 | { | ||
| 595 | .pa_start = 0x4900E000, | ||
| 596 | .pa_end = 0x4900E1ff, | ||
| 597 | .flags = ADDR_TYPE_RT | ||
| 598 | }, | ||
| 599 | }; | ||
| 600 | |||
| 601 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { | ||
| 602 | .master = &omap2430_l4_wkup_hwmod, | ||
| 603 | .slave = &omap2430_gpio2_hwmod, | ||
| 604 | .clk = "gpios_ick", | ||
| 605 | .addr = omap2430_gpio2_addr_space, | ||
| 606 | .addr_cnt = ARRAY_SIZE(omap2430_gpio2_addr_space), | ||
| 607 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 608 | }; | ||
| 609 | |||
| 610 | /* l4_wkup -> gpio3 */ | ||
| 611 | static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { | ||
| 612 | { | ||
| 613 | .pa_start = 0x49010000, | ||
| 614 | .pa_end = 0x490101ff, | ||
| 615 | .flags = ADDR_TYPE_RT | ||
| 616 | }, | ||
| 617 | }; | ||
| 618 | |||
| 619 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { | ||
| 620 | .master = &omap2430_l4_wkup_hwmod, | ||
| 621 | .slave = &omap2430_gpio3_hwmod, | ||
| 622 | .clk = "gpios_ick", | ||
| 623 | .addr = omap2430_gpio3_addr_space, | ||
| 624 | .addr_cnt = ARRAY_SIZE(omap2430_gpio3_addr_space), | ||
| 625 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 626 | }; | ||
| 627 | |||
| 628 | /* l4_wkup -> gpio4 */ | ||
| 629 | static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { | ||
| 630 | { | ||
| 631 | .pa_start = 0x49012000, | ||
| 632 | .pa_end = 0x490121ff, | ||
| 633 | .flags = ADDR_TYPE_RT | ||
| 634 | }, | ||
| 635 | }; | ||
| 636 | |||
| 637 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { | ||
| 638 | .master = &omap2430_l4_wkup_hwmod, | ||
| 639 | .slave = &omap2430_gpio4_hwmod, | ||
| 640 | .clk = "gpios_ick", | ||
| 641 | .addr = omap2430_gpio4_addr_space, | ||
| 642 | .addr_cnt = ARRAY_SIZE(omap2430_gpio4_addr_space), | ||
| 643 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 644 | }; | ||
| 645 | |||
| 646 | /* l4_core -> gpio5 */ | ||
| 647 | static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { | ||
| 648 | { | ||
| 649 | .pa_start = 0x480B6000, | ||
| 650 | .pa_end = 0x480B61ff, | ||
| 651 | .flags = ADDR_TYPE_RT | ||
| 652 | }, | ||
| 653 | }; | ||
| 654 | |||
| 655 | static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { | ||
| 656 | .master = &omap2430_l4_core_hwmod, | ||
| 657 | .slave = &omap2430_gpio5_hwmod, | ||
| 658 | .clk = "gpio5_ick", | ||
| 659 | .addr = omap2430_gpio5_addr_space, | ||
| 660 | .addr_cnt = ARRAY_SIZE(omap2430_gpio5_addr_space), | ||
| 661 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 662 | }; | ||
| 663 | |||
| 664 | /* gpio dev_attr */ | ||
| 665 | static struct omap_gpio_dev_attr gpio_dev_attr = { | ||
| 666 | .bank_width = 32, | ||
| 667 | .dbck_flag = false, | ||
| 668 | }; | ||
| 669 | |||
| 670 | static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = { | ||
| 671 | .rev_offs = 0x0000, | ||
| 672 | .sysc_offs = 0x0010, | ||
| 673 | .syss_offs = 0x0014, | ||
| 674 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | ||
| 675 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | ||
| 676 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
| 677 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
| 678 | }; | ||
| 679 | |||
| 680 | /* | ||
| 681 | * 'gpio' class | ||
| 682 | * general purpose io module | ||
| 683 | */ | ||
| 684 | static struct omap_hwmod_class omap243x_gpio_hwmod_class = { | ||
| 685 | .name = "gpio", | ||
| 686 | .sysc = &omap243x_gpio_sysc, | ||
| 687 | .rev = 0, | ||
| 688 | }; | ||
| 689 | |||
| 690 | /* gpio1 */ | ||
| 691 | static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = { | ||
| 692 | { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */ | ||
| 693 | }; | ||
| 694 | |||
| 695 | static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = { | ||
| 696 | &omap2430_l4_wkup__gpio1, | ||
| 697 | }; | ||
| 698 | |||
| 699 | static struct omap_hwmod omap2430_gpio1_hwmod = { | ||
| 700 | .name = "gpio1", | ||
| 701 | .mpu_irqs = omap243x_gpio1_irqs, | ||
| 702 | .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs), | ||
| 703 | .main_clk = "gpios_fck", | ||
| 704 | .prcm = { | ||
| 705 | .omap2 = { | ||
| 706 | .prcm_reg_id = 1, | ||
| 707 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | ||
| 708 | .module_offs = WKUP_MOD, | ||
| 709 | .idlest_reg_id = 1, | ||
| 710 | .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT, | ||
| 711 | }, | ||
| 712 | }, | ||
| 713 | .slaves = omap2430_gpio1_slaves, | ||
| 714 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves), | ||
| 715 | .class = &omap243x_gpio_hwmod_class, | ||
| 716 | .dev_attr = &gpio_dev_attr, | ||
| 717 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | ||
| 718 | }; | ||
| 719 | |||
| 720 | /* gpio2 */ | ||
| 721 | static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = { | ||
| 722 | { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */ | ||
| 723 | }; | ||
| 724 | |||
| 725 | static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = { | ||
| 726 | &omap2430_l4_wkup__gpio2, | ||
| 727 | }; | ||
| 728 | |||
| 729 | static struct omap_hwmod omap2430_gpio2_hwmod = { | ||
| 730 | .name = "gpio2", | ||
| 731 | .mpu_irqs = omap243x_gpio2_irqs, | ||
| 732 | .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio2_irqs), | ||
| 733 | .main_clk = "gpios_fck", | ||
| 734 | .prcm = { | ||
| 735 | .omap2 = { | ||
| 736 | .prcm_reg_id = 1, | ||
| 737 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | ||
| 738 | .module_offs = WKUP_MOD, | ||
| 739 | .idlest_reg_id = 1, | ||
| 740 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | ||
| 741 | }, | ||
| 742 | }, | ||
| 743 | .slaves = omap2430_gpio2_slaves, | ||
| 744 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves), | ||
| 745 | .class = &omap243x_gpio_hwmod_class, | ||
| 746 | .dev_attr = &gpio_dev_attr, | ||
| 747 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | ||
| 748 | }; | ||
| 749 | |||
| 750 | /* gpio3 */ | ||
| 751 | static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = { | ||
| 752 | { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */ | ||
| 753 | }; | ||
| 754 | |||
| 755 | static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = { | ||
| 756 | &omap2430_l4_wkup__gpio3, | ||
| 757 | }; | ||
| 758 | |||
| 759 | static struct omap_hwmod omap2430_gpio3_hwmod = { | ||
| 760 | .name = "gpio3", | ||
| 761 | .mpu_irqs = omap243x_gpio3_irqs, | ||
| 762 | .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio3_irqs), | ||
| 763 | .main_clk = "gpios_fck", | ||
| 764 | .prcm = { | ||
| 765 | .omap2 = { | ||
| 766 | .prcm_reg_id = 1, | ||
| 767 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | ||
| 768 | .module_offs = WKUP_MOD, | ||
| 769 | .idlest_reg_id = 1, | ||
| 770 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | ||
| 771 | }, | ||
| 772 | }, | ||
| 773 | .slaves = omap2430_gpio3_slaves, | ||
| 774 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves), | ||
| 775 | .class = &omap243x_gpio_hwmod_class, | ||
| 776 | .dev_attr = &gpio_dev_attr, | ||
| 777 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | ||
| 778 | }; | ||
| 779 | |||
| 780 | /* gpio4 */ | ||
| 781 | static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = { | ||
| 782 | { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */ | ||
| 783 | }; | ||
| 784 | |||
| 785 | static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = { | ||
| 786 | &omap2430_l4_wkup__gpio4, | ||
| 787 | }; | ||
| 788 | |||
| 789 | static struct omap_hwmod omap2430_gpio4_hwmod = { | ||
| 790 | .name = "gpio4", | ||
| 791 | .mpu_irqs = omap243x_gpio4_irqs, | ||
| 792 | .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio4_irqs), | ||
| 793 | .main_clk = "gpios_fck", | ||
| 794 | .prcm = { | ||
| 795 | .omap2 = { | ||
| 796 | .prcm_reg_id = 1, | ||
| 797 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | ||
| 798 | .module_offs = WKUP_MOD, | ||
| 799 | .idlest_reg_id = 1, | ||
| 800 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | ||
| 801 | }, | ||
| 802 | }, | ||
| 803 | .slaves = omap2430_gpio4_slaves, | ||
| 804 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves), | ||
| 805 | .class = &omap243x_gpio_hwmod_class, | ||
| 806 | .dev_attr = &gpio_dev_attr, | ||
| 807 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | ||
| 808 | }; | ||
| 809 | |||
| 810 | /* gpio5 */ | ||
| 811 | static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { | ||
| 812 | { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */ | ||
| 813 | }; | ||
| 814 | |||
| 815 | static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = { | ||
| 816 | &omap2430_l4_core__gpio5, | ||
| 817 | }; | ||
| 818 | |||
| 819 | static struct omap_hwmod omap2430_gpio5_hwmod = { | ||
| 820 | .name = "gpio5", | ||
| 821 | .mpu_irqs = omap243x_gpio5_irqs, | ||
| 822 | .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio5_irqs), | ||
| 823 | .main_clk = "gpio5_fck", | ||
| 824 | .prcm = { | ||
| 825 | .omap2 = { | ||
| 826 | .prcm_reg_id = 2, | ||
| 827 | .module_bit = OMAP2430_EN_GPIO5_SHIFT, | ||
| 828 | .module_offs = CORE_MOD, | ||
| 829 | .idlest_reg_id = 2, | ||
| 830 | .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, | ||
| 831 | }, | ||
| 832 | }, | ||
| 833 | .slaves = omap2430_gpio5_slaves, | ||
| 834 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves), | ||
| 835 | .class = &omap243x_gpio_hwmod_class, | ||
| 836 | .dev_attr = &gpio_dev_attr, | ||
| 837 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | ||
| 838 | }; | ||
| 839 | |||
| 840 | /* dma_system */ | ||
| 841 | static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = { | ||
| 842 | .rev_offs = 0x0000, | ||
| 843 | .sysc_offs = 0x002c, | ||
| 844 | .syss_offs = 0x0028, | ||
| 845 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE | | ||
| 846 | SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE | | ||
| 847 | SYSC_HAS_AUTOIDLE), | ||
| 848 | .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | ||
| 849 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
| 850 | }; | ||
| 851 | |||
| 852 | static struct omap_hwmod_class omap2430_dma_hwmod_class = { | ||
| 853 | .name = "dma", | ||
| 854 | .sysc = &omap2430_dma_sysc, | ||
| 855 | }; | ||
| 856 | |||
| 857 | /* dma attributes */ | ||
| 858 | static struct omap_dma_dev_attr dma_dev_attr = { | ||
| 859 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | ||
| 860 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | ||
| 861 | .lch_count = 32, | ||
| 862 | }; | ||
| 863 | |||
| 864 | static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = { | ||
| 865 | { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */ | ||
| 866 | { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */ | ||
| 867 | { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */ | ||
| 868 | { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */ | ||
| 869 | }; | ||
| 870 | |||
| 871 | static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = { | ||
| 872 | { | ||
| 873 | .pa_start = 0x48056000, | ||
| 874 | .pa_end = 0x4a0560ff, | ||
| 875 | .flags = ADDR_TYPE_RT | ||
| 876 | }, | ||
| 877 | }; | ||
| 878 | |||
| 879 | /* dma_system -> L3 */ | ||
| 880 | static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { | ||
| 881 | .master = &omap2430_dma_system_hwmod, | ||
| 882 | .slave = &omap2430_l3_main_hwmod, | ||
| 883 | .clk = "core_l3_ck", | ||
| 884 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 885 | }; | ||
| 886 | |||
| 887 | /* dma_system master ports */ | ||
| 888 | static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = { | ||
| 889 | &omap2430_dma_system__l3, | ||
| 890 | }; | ||
| 891 | |||
| 892 | /* l4_core -> dma_system */ | ||
| 893 | static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { | ||
| 894 | .master = &omap2430_l4_core_hwmod, | ||
| 895 | .slave = &omap2430_dma_system_hwmod, | ||
| 896 | .clk = "sdma_ick", | ||
| 897 | .addr = omap2430_dma_system_addrs, | ||
| 898 | .addr_cnt = ARRAY_SIZE(omap2430_dma_system_addrs), | ||
| 899 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 900 | }; | ||
| 901 | |||
| 902 | /* dma_system slave ports */ | ||
| 903 | static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = { | ||
| 904 | &omap2430_l4_core__dma_system, | ||
| 905 | }; | ||
| 906 | |||
| 907 | static struct omap_hwmod omap2430_dma_system_hwmod = { | ||
| 908 | .name = "dma", | ||
| 909 | .class = &omap2430_dma_hwmod_class, | ||
| 910 | .mpu_irqs = omap2430_dma_system_irqs, | ||
| 911 | .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dma_system_irqs), | ||
| 912 | .main_clk = "core_l3_ck", | ||
| 913 | .slaves = omap2430_dma_system_slaves, | ||
| 914 | .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves), | ||
| 915 | .masters = omap2430_dma_system_masters, | ||
| 916 | .masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters), | ||
| 917 | .dev_attr = &dma_dev_attr, | ||
| 918 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | ||
| 919 | .flags = HWMOD_NO_IDLEST, | ||
| 920 | }; | ||
| 921 | |||
| 421 | static __initdata struct omap_hwmod *omap2430_hwmods[] = { | 922 | static __initdata struct omap_hwmod *omap2430_hwmods[] = { |
| 422 | &omap2430_l3_main_hwmod, | 923 | &omap2430_l3_main_hwmod, |
| 423 | &omap2430_l4_core_hwmod, | 924 | &omap2430_l4_core_hwmod, |
| @@ -428,6 +929,18 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = { | |||
| 428 | &omap2430_uart1_hwmod, | 929 | &omap2430_uart1_hwmod, |
| 429 | &omap2430_uart2_hwmod, | 930 | &omap2430_uart2_hwmod, |
| 430 | &omap2430_uart3_hwmod, | 931 | &omap2430_uart3_hwmod, |
| 932 | &omap2430_i2c1_hwmod, | ||
| 933 | &omap2430_i2c2_hwmod, | ||
| 934 | |||
| 935 | /* gpio class */ | ||
| 936 | &omap2430_gpio1_hwmod, | ||
| 937 | &omap2430_gpio2_hwmod, | ||
| 938 | &omap2430_gpio3_hwmod, | ||
| 939 | &omap2430_gpio4_hwmod, | ||
| 940 | &omap2430_gpio5_hwmod, | ||
| 941 | |||
| 942 | /* dma_system class*/ | ||
| 943 | &omap2430_dma_system_hwmod, | ||
| 431 | NULL, | 944 | NULL, |
| 432 | }; | 945 | }; |
| 433 | 946 | ||
| @@ -435,5 +948,3 @@ int __init omap2430_hwmod_init(void) | |||
| 435 | { | 948 | { |
| 436 | return omap_hwmod_init(omap2430_hwmods); | 949 | return omap_hwmod_init(omap2430_hwmods); |
| 437 | } | 950 | } |
| 438 | |||
| 439 | |||
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index cb97ecf0a3f6..8d8181334f86 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | |||
| @@ -18,11 +18,16 @@ | |||
| 18 | #include <plat/cpu.h> | 18 | #include <plat/cpu.h> |
| 19 | #include <plat/dma.h> | 19 | #include <plat/dma.h> |
| 20 | #include <plat/serial.h> | 20 | #include <plat/serial.h> |
| 21 | #include <plat/l4_3xxx.h> | ||
| 22 | #include <plat/i2c.h> | ||
| 23 | #include <plat/gpio.h> | ||
| 24 | #include <plat/smartreflex.h> | ||
| 21 | 25 | ||
| 22 | #include "omap_hwmod_common_data.h" | 26 | #include "omap_hwmod_common_data.h" |
| 23 | 27 | ||
| 24 | #include "prm-regbits-34xx.h" | 28 | #include "prm-regbits-34xx.h" |
| 25 | #include "cm-regbits-34xx.h" | 29 | #include "cm-regbits-34xx.h" |
| 30 | #include "wd_timer.h" | ||
| 26 | 31 | ||
| 27 | /* | 32 | /* |
| 28 | * OMAP3xxx hardware module integration data | 33 | * OMAP3xxx hardware module integration data |
| @@ -39,6 +44,19 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod; | |||
| 39 | static struct omap_hwmod omap3xxx_l4_core_hwmod; | 44 | static struct omap_hwmod omap3xxx_l4_core_hwmod; |
| 40 | static struct omap_hwmod omap3xxx_l4_per_hwmod; | 45 | static struct omap_hwmod omap3xxx_l4_per_hwmod; |
| 41 | static struct omap_hwmod omap3xxx_wd_timer2_hwmod; | 46 | static struct omap_hwmod omap3xxx_wd_timer2_hwmod; |
| 47 | static struct omap_hwmod omap3xxx_i2c1_hwmod; | ||
| 48 | static struct omap_hwmod omap3xxx_i2c2_hwmod; | ||
| 49 | static struct omap_hwmod omap3xxx_i2c3_hwmod; | ||
| 50 | static struct omap_hwmod omap3xxx_gpio1_hwmod; | ||
| 51 | static struct omap_hwmod omap3xxx_gpio2_hwmod; | ||
| 52 | static struct omap_hwmod omap3xxx_gpio3_hwmod; | ||
| 53 | static struct omap_hwmod omap3xxx_gpio4_hwmod; | ||
| 54 | static struct omap_hwmod omap3xxx_gpio5_hwmod; | ||
| 55 | static struct omap_hwmod omap3xxx_gpio6_hwmod; | ||
| 56 | static struct omap_hwmod omap34xx_sr1_hwmod; | ||
| 57 | static struct omap_hwmod omap34xx_sr2_hwmod; | ||
| 58 | |||
| 59 | static struct omap_hwmod omap3xxx_dma_system_hwmod; | ||
| 42 | 60 | ||
| 43 | /* L3 -> L4_CORE interface */ | 61 | /* L3 -> L4_CORE interface */ |
| 44 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { | 62 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { |
| @@ -169,9 +187,125 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = { | |||
| 169 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 187 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 170 | }; | 188 | }; |
| 171 | 189 | ||
| 190 | /* I2C IP block address space length (in bytes) */ | ||
| 191 | #define OMAP2_I2C_AS_LEN 128 | ||
| 192 | |||
| 193 | /* L4 CORE -> I2C1 interface */ | ||
| 194 | static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = { | ||
| 195 | { | ||
| 196 | .pa_start = 0x48070000, | ||
| 197 | .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1, | ||
| 198 | .flags = ADDR_TYPE_RT, | ||
| 199 | }, | ||
| 200 | }; | ||
| 201 | |||
| 202 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { | ||
| 203 | .master = &omap3xxx_l4_core_hwmod, | ||
| 204 | .slave = &omap3xxx_i2c1_hwmod, | ||
| 205 | .clk = "i2c1_ick", | ||
| 206 | .addr = omap3xxx_i2c1_addr_space, | ||
| 207 | .addr_cnt = ARRAY_SIZE(omap3xxx_i2c1_addr_space), | ||
| 208 | .fw = { | ||
| 209 | .omap2 = { | ||
| 210 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, | ||
| 211 | .l4_prot_group = 7, | ||
| 212 | .flags = OMAP_FIREWALL_L4, | ||
| 213 | } | ||
| 214 | }, | ||
| 215 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 216 | }; | ||
| 217 | |||
| 218 | /* L4 CORE -> I2C2 interface */ | ||
| 219 | static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = { | ||
| 220 | { | ||
| 221 | .pa_start = 0x48072000, | ||
| 222 | .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1, | ||
| 223 | .flags = ADDR_TYPE_RT, | ||
| 224 | }, | ||
| 225 | }; | ||
| 226 | |||
| 227 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { | ||
| 228 | .master = &omap3xxx_l4_core_hwmod, | ||
| 229 | .slave = &omap3xxx_i2c2_hwmod, | ||
| 230 | .clk = "i2c2_ick", | ||
| 231 | .addr = omap3xxx_i2c2_addr_space, | ||
| 232 | .addr_cnt = ARRAY_SIZE(omap3xxx_i2c2_addr_space), | ||
| 233 | .fw = { | ||
| 234 | .omap2 = { | ||
| 235 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, | ||
| 236 | .l4_prot_group = 7, | ||
| 237 | .flags = OMAP_FIREWALL_L4, | ||
| 238 | } | ||
| 239 | }, | ||
| 240 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 241 | }; | ||
| 242 | |||
| 243 | /* L4 CORE -> I2C3 interface */ | ||
| 244 | static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { | ||
| 245 | { | ||
| 246 | .pa_start = 0x48060000, | ||
| 247 | .pa_end = 0x48060000 + OMAP2_I2C_AS_LEN - 1, | ||
| 248 | .flags = ADDR_TYPE_RT, | ||
| 249 | }, | ||
| 250 | }; | ||
| 251 | |||
| 252 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { | ||
| 253 | .master = &omap3xxx_l4_core_hwmod, | ||
| 254 | .slave = &omap3xxx_i2c3_hwmod, | ||
| 255 | .clk = "i2c3_ick", | ||
| 256 | .addr = omap3xxx_i2c3_addr_space, | ||
| 257 | .addr_cnt = ARRAY_SIZE(omap3xxx_i2c3_addr_space), | ||
| 258 | .fw = { | ||
| 259 | .omap2 = { | ||
| 260 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, | ||
| 261 | .l4_prot_group = 7, | ||
| 262 | .flags = OMAP_FIREWALL_L4, | ||
| 263 | } | ||
| 264 | }, | ||
| 265 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 266 | }; | ||
| 267 | |||
| 268 | /* L4 CORE -> SR1 interface */ | ||
| 269 | static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { | ||
| 270 | { | ||
| 271 | .pa_start = OMAP34XX_SR1_BASE, | ||
| 272 | .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, | ||
| 273 | .flags = ADDR_TYPE_RT, | ||
| 274 | }, | ||
| 275 | }; | ||
| 276 | |||
| 277 | static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = { | ||
| 278 | .master = &omap3xxx_l4_core_hwmod, | ||
| 279 | .slave = &omap34xx_sr1_hwmod, | ||
| 280 | .clk = "sr_l4_ick", | ||
| 281 | .addr = omap3_sr1_addr_space, | ||
| 282 | .addr_cnt = ARRAY_SIZE(omap3_sr1_addr_space), | ||
| 283 | .user = OCP_USER_MPU, | ||
| 284 | }; | ||
| 285 | |||
| 286 | /* L4 CORE -> SR1 interface */ | ||
| 287 | static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { | ||
| 288 | { | ||
| 289 | .pa_start = OMAP34XX_SR2_BASE, | ||
| 290 | .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, | ||
| 291 | .flags = ADDR_TYPE_RT, | ||
| 292 | }, | ||
| 293 | }; | ||
| 294 | |||
| 295 | static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = { | ||
| 296 | .master = &omap3xxx_l4_core_hwmod, | ||
| 297 | .slave = &omap34xx_sr2_hwmod, | ||
| 298 | .clk = "sr_l4_ick", | ||
| 299 | .addr = omap3_sr2_addr_space, | ||
| 300 | .addr_cnt = ARRAY_SIZE(omap3_sr2_addr_space), | ||
| 301 | .user = OCP_USER_MPU, | ||
| 302 | }; | ||
| 303 | |||
| 172 | /* Slave interfaces on the L4_CORE interconnect */ | 304 | /* Slave interfaces on the L4_CORE interconnect */ |
| 173 | static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { | 305 | static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { |
| 174 | &omap3xxx_l3_main__l4_core, | 306 | &omap3xxx_l3_main__l4_core, |
| 307 | &omap3_l4_core__sr1, | ||
| 308 | &omap3_l4_core__sr2, | ||
| 175 | }; | 309 | }; |
| 176 | 310 | ||
| 177 | /* Master interfaces on the L4_CORE interconnect */ | 311 | /* Master interfaces on the L4_CORE interconnect */ |
| @@ -179,6 +313,9 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = { | |||
| 179 | &omap3xxx_l4_core__l4_wkup, | 313 | &omap3xxx_l4_core__l4_wkup, |
| 180 | &omap3_l4_core__uart1, | 314 | &omap3_l4_core__uart1, |
| 181 | &omap3_l4_core__uart2, | 315 | &omap3_l4_core__uart2, |
| 316 | &omap3_l4_core__i2c1, | ||
| 317 | &omap3_l4_core__i2c2, | ||
| 318 | &omap3_l4_core__i2c3, | ||
| 182 | }; | 319 | }; |
| 183 | 320 | ||
| 184 | /* L4 CORE */ | 321 | /* L4 CORE */ |
| @@ -315,9 +452,22 @@ static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { | |||
| 315 | .sysc_fields = &omap_hwmod_sysc_type1, | 452 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 316 | }; | 453 | }; |
| 317 | 454 | ||
| 455 | /* I2C common */ | ||
| 456 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | ||
| 457 | .rev_offs = 0x00, | ||
| 458 | .sysc_offs = 0x20, | ||
| 459 | .syss_offs = 0x10, | ||
| 460 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | ||
| 461 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | ||
| 462 | SYSC_HAS_AUTOIDLE), | ||
| 463 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
| 464 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
| 465 | }; | ||
| 466 | |||
| 318 | static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { | 467 | static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { |
| 319 | .name = "wd_timer", | 468 | .name = "wd_timer", |
| 320 | .sysc = &omap3xxx_wd_timer_sysc, | 469 | .sysc = &omap3xxx_wd_timer_sysc, |
| 470 | .pre_shutdown = &omap2_wd_timer_disable | ||
| 321 | }; | 471 | }; |
| 322 | 472 | ||
| 323 | /* wd_timer2 */ | 473 | /* wd_timer2 */ |
| @@ -509,6 +659,703 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = { | |||
| 509 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), | 659 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), |
| 510 | }; | 660 | }; |
| 511 | 661 | ||
| 662 | static struct omap_hwmod_class i2c_class = { | ||
| 663 | .name = "i2c", | ||
| 664 | .sysc = &i2c_sysc, | ||
| 665 | }; | ||
| 666 | |||
| 667 | /* I2C1 */ | ||
| 668 | |||
| 669 | static struct omap_i2c_dev_attr i2c1_dev_attr = { | ||
| 670 | .fifo_depth = 8, /* bytes */ | ||
| 671 | }; | ||
| 672 | |||
| 673 | static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { | ||
| 674 | { .irq = INT_24XX_I2C1_IRQ, }, | ||
| 675 | }; | ||
| 676 | |||
| 677 | static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { | ||
| 678 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, | ||
| 679 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, | ||
| 680 | }; | ||
| 681 | |||
| 682 | static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = { | ||
| 683 | &omap3_l4_core__i2c1, | ||
| 684 | }; | ||
| 685 | |||
| 686 | static struct omap_hwmod omap3xxx_i2c1_hwmod = { | ||
| 687 | .name = "i2c1", | ||
| 688 | .mpu_irqs = i2c1_mpu_irqs, | ||
| 689 | .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), | ||
| 690 | .sdma_reqs = i2c1_sdma_reqs, | ||
| 691 | .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs), | ||
| 692 | .main_clk = "i2c1_fck", | ||
| 693 | .prcm = { | ||
| 694 | .omap2 = { | ||
| 695 | .module_offs = CORE_MOD, | ||
| 696 | .prcm_reg_id = 1, | ||
| 697 | .module_bit = OMAP3430_EN_I2C1_SHIFT, | ||
| 698 | .idlest_reg_id = 1, | ||
| 699 | .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, | ||
| 700 | }, | ||
| 701 | }, | ||
| 702 | .slaves = omap3xxx_i2c1_slaves, | ||
| 703 | .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves), | ||
| 704 | .class = &i2c_class, | ||
| 705 | .dev_attr = &i2c1_dev_attr, | ||
| 706 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
| 707 | }; | ||
| 708 | |||
| 709 | /* I2C2 */ | ||
| 710 | |||
| 711 | static struct omap_i2c_dev_attr i2c2_dev_attr = { | ||
| 712 | .fifo_depth = 8, /* bytes */ | ||
| 713 | }; | ||
| 714 | |||
| 715 | static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { | ||
| 716 | { .irq = INT_24XX_I2C2_IRQ, }, | ||
| 717 | }; | ||
| 718 | |||
| 719 | static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = { | ||
| 720 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, | ||
| 721 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, | ||
| 722 | }; | ||
| 723 | |||
| 724 | static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = { | ||
| 725 | &omap3_l4_core__i2c2, | ||
| 726 | }; | ||
| 727 | |||
| 728 | static struct omap_hwmod omap3xxx_i2c2_hwmod = { | ||
| 729 | .name = "i2c2", | ||
| 730 | .mpu_irqs = i2c2_mpu_irqs, | ||
| 731 | .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), | ||
| 732 | .sdma_reqs = i2c2_sdma_reqs, | ||
| 733 | .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs), | ||
| 734 | .main_clk = "i2c2_fck", | ||
| 735 | .prcm = { | ||
| 736 | .omap2 = { | ||
| 737 | .module_offs = CORE_MOD, | ||
| 738 | .prcm_reg_id = 1, | ||
| 739 | .module_bit = OMAP3430_EN_I2C2_SHIFT, | ||
| 740 | .idlest_reg_id = 1, | ||
| 741 | .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, | ||
| 742 | }, | ||
| 743 | }, | ||
| 744 | .slaves = omap3xxx_i2c2_slaves, | ||
| 745 | .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves), | ||
| 746 | .class = &i2c_class, | ||
| 747 | .dev_attr = &i2c2_dev_attr, | ||
| 748 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
| 749 | }; | ||
| 750 | |||
| 751 | /* I2C3 */ | ||
| 752 | |||
| 753 | static struct omap_i2c_dev_attr i2c3_dev_attr = { | ||
| 754 | .fifo_depth = 64, /* bytes */ | ||
| 755 | }; | ||
| 756 | |||
| 757 | static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { | ||
| 758 | { .irq = INT_34XX_I2C3_IRQ, }, | ||
| 759 | }; | ||
| 760 | |||
| 761 | static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { | ||
| 762 | { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX }, | ||
| 763 | { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX }, | ||
| 764 | }; | ||
| 765 | |||
| 766 | static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = { | ||
| 767 | &omap3_l4_core__i2c3, | ||
| 768 | }; | ||
| 769 | |||
| 770 | static struct omap_hwmod omap3xxx_i2c3_hwmod = { | ||
| 771 | .name = "i2c3", | ||
| 772 | .mpu_irqs = i2c3_mpu_irqs, | ||
| 773 | .mpu_irqs_cnt = ARRAY_SIZE(i2c3_mpu_irqs), | ||
| 774 | .sdma_reqs = i2c3_sdma_reqs, | ||
| 775 | .sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs), | ||
| 776 | .main_clk = "i2c3_fck", | ||
| 777 | .prcm = { | ||
| 778 | .omap2 = { | ||
| 779 | .module_offs = CORE_MOD, | ||
| 780 | .prcm_reg_id = 1, | ||
| 781 | .module_bit = OMAP3430_EN_I2C3_SHIFT, | ||
| 782 | .idlest_reg_id = 1, | ||
| 783 | .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, | ||
| 784 | }, | ||
| 785 | }, | ||
| 786 | .slaves = omap3xxx_i2c3_slaves, | ||
| 787 | .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves), | ||
| 788 | .class = &i2c_class, | ||
| 789 | .dev_attr = &i2c3_dev_attr, | ||
| 790 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
| 791 | }; | ||
| 792 | |||
| 793 | /* l4_wkup -> gpio1 */ | ||
| 794 | static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = { | ||
| 795 | { | ||
| 796 | .pa_start = 0x48310000, | ||
| 797 | .pa_end = 0x483101ff, | ||
| 798 | .flags = ADDR_TYPE_RT | ||
| 799 | }, | ||
| 800 | }; | ||
| 801 | |||
| 802 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { | ||
| 803 | .master = &omap3xxx_l4_wkup_hwmod, | ||
| 804 | .slave = &omap3xxx_gpio1_hwmod, | ||
| 805 | .addr = omap3xxx_gpio1_addrs, | ||
| 806 | .addr_cnt = ARRAY_SIZE(omap3xxx_gpio1_addrs), | ||
| 807 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 808 | }; | ||
| 809 | |||
| 810 | /* l4_per -> gpio2 */ | ||
| 811 | static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = { | ||
| 812 | { | ||
| 813 | .pa_start = 0x49050000, | ||
| 814 | .pa_end = 0x490501ff, | ||
| 815 | .flags = ADDR_TYPE_RT | ||
| 816 | }, | ||
| 817 | }; | ||
| 818 | |||
| 819 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { | ||
| 820 | .master = &omap3xxx_l4_per_hwmod, | ||
| 821 | .slave = &omap3xxx_gpio2_hwmod, | ||
| 822 | .addr = omap3xxx_gpio2_addrs, | ||
| 823 | .addr_cnt = ARRAY_SIZE(omap3xxx_gpio2_addrs), | ||
| 824 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 825 | }; | ||
| 826 | |||
| 827 | /* l4_per -> gpio3 */ | ||
| 828 | static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = { | ||
| 829 | { | ||
| 830 | .pa_start = 0x49052000, | ||
| 831 | .pa_end = 0x490521ff, | ||
| 832 | .flags = ADDR_TYPE_RT | ||
| 833 | }, | ||
| 834 | }; | ||
| 835 | |||
| 836 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { | ||
| 837 | .master = &omap3xxx_l4_per_hwmod, | ||
| 838 | .slave = &omap3xxx_gpio3_hwmod, | ||
| 839 | .addr = omap3xxx_gpio3_addrs, | ||
| 840 | .addr_cnt = ARRAY_SIZE(omap3xxx_gpio3_addrs), | ||
| 841 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 842 | }; | ||
| 843 | |||
| 844 | /* l4_per -> gpio4 */ | ||
| 845 | static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { | ||
| 846 | { | ||
| 847 | .pa_start = 0x49054000, | ||
| 848 | .pa_end = 0x490541ff, | ||
| 849 | .flags = ADDR_TYPE_RT | ||
| 850 | }, | ||
| 851 | }; | ||
| 852 | |||
| 853 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { | ||
| 854 | .master = &omap3xxx_l4_per_hwmod, | ||
| 855 | .slave = &omap3xxx_gpio4_hwmod, | ||
| 856 | .addr = omap3xxx_gpio4_addrs, | ||
| 857 | .addr_cnt = ARRAY_SIZE(omap3xxx_gpio4_addrs), | ||
| 858 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 859 | }; | ||
| 860 | |||
| 861 | /* l4_per -> gpio5 */ | ||
| 862 | static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = { | ||
| 863 | { | ||
| 864 | .pa_start = 0x49056000, | ||
| 865 | .pa_end = 0x490561ff, | ||
| 866 | .flags = ADDR_TYPE_RT | ||
| 867 | }, | ||
| 868 | }; | ||
| 869 | |||
| 870 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { | ||
| 871 | .master = &omap3xxx_l4_per_hwmod, | ||
| 872 | .slave = &omap3xxx_gpio5_hwmod, | ||
| 873 | .addr = omap3xxx_gpio5_addrs, | ||
| 874 | .addr_cnt = ARRAY_SIZE(omap3xxx_gpio5_addrs), | ||
| 875 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 876 | }; | ||
| 877 | |||
| 878 | /* l4_per -> gpio6 */ | ||
| 879 | static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = { | ||
| 880 | { | ||
| 881 | .pa_start = 0x49058000, | ||
| 882 | .pa_end = 0x490581ff, | ||
| 883 | .flags = ADDR_TYPE_RT | ||
| 884 | }, | ||
| 885 | }; | ||
| 886 | |||
| 887 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { | ||
| 888 | .master = &omap3xxx_l4_per_hwmod, | ||
| 889 | .slave = &omap3xxx_gpio6_hwmod, | ||
| 890 | .addr = omap3xxx_gpio6_addrs, | ||
| 891 | .addr_cnt = ARRAY_SIZE(omap3xxx_gpio6_addrs), | ||
| 892 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 893 | }; | ||
| 894 | |||
| 895 | /* | ||
| 896 | * 'gpio' class | ||
| 897 | * general purpose io module | ||
| 898 | */ | ||
| 899 | |||
| 900 | static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = { | ||
| 901 | .rev_offs = 0x0000, | ||
| 902 | .sysc_offs = 0x0010, | ||
| 903 | .syss_offs = 0x0014, | ||
| 904 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | ||
| 905 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | ||
| 906 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
| 907 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
| 908 | }; | ||
| 909 | |||
| 910 | static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { | ||
| 911 | .name = "gpio", | ||
| 912 | .sysc = &omap3xxx_gpio_sysc, | ||
| 913 | .rev = 1, | ||
| 914 | }; | ||
| 915 | |||
| 916 | /* gpio_dev_attr*/ | ||
| 917 | static struct omap_gpio_dev_attr gpio_dev_attr = { | ||
| 918 | .bank_width = 32, | ||
| 919 | .dbck_flag = true, | ||
| 920 | }; | ||
| 921 | |||
| 922 | /* gpio1 */ | ||
| 923 | static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = { | ||
| 924 | { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */ | ||
| 925 | }; | ||
| 926 | |||
| 927 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { | ||
| 928 | { .role = "dbclk", .clk = "gpio1_dbck", }, | ||
| 929 | }; | ||
| 930 | |||
| 931 | static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = { | ||
| 932 | &omap3xxx_l4_wkup__gpio1, | ||
| 933 | }; | ||
| 934 | |||
| 935 | static struct omap_hwmod omap3xxx_gpio1_hwmod = { | ||
| 936 | .name = "gpio1", | ||
| 937 | .mpu_irqs = omap3xxx_gpio1_irqs, | ||
| 938 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs), | ||
| 939 | .main_clk = "gpio1_ick", | ||
| 940 | .opt_clks = gpio1_opt_clks, | ||
| 941 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | ||
| 942 | .prcm = { | ||
| 943 | .omap2 = { | ||
| 944 | .prcm_reg_id = 1, | ||
| 945 | .module_bit = OMAP3430_EN_GPIO1_SHIFT, | ||
| 946 | .module_offs = WKUP_MOD, | ||
| 947 | .idlest_reg_id = 1, | ||
| 948 | .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, | ||
| 949 | }, | ||
| 950 | }, | ||
| 951 | .slaves = omap3xxx_gpio1_slaves, | ||
| 952 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves), | ||
| 953 | .class = &omap3xxx_gpio_hwmod_class, | ||
| 954 | .dev_attr = &gpio_dev_attr, | ||
| 955 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
| 956 | }; | ||
| 957 | |||
| 958 | /* gpio2 */ | ||
| 959 | static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = { | ||
| 960 | { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */ | ||
| 961 | }; | ||
| 962 | |||
| 963 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { | ||
| 964 | { .role = "dbclk", .clk = "gpio2_dbck", }, | ||
| 965 | }; | ||
| 966 | |||
| 967 | static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = { | ||
| 968 | &omap3xxx_l4_per__gpio2, | ||
| 969 | }; | ||
| 970 | |||
| 971 | static struct omap_hwmod omap3xxx_gpio2_hwmod = { | ||
| 972 | .name = "gpio2", | ||
| 973 | .mpu_irqs = omap3xxx_gpio2_irqs, | ||
| 974 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs), | ||
| 975 | .main_clk = "gpio2_ick", | ||
| 976 | .opt_clks = gpio2_opt_clks, | ||
| 977 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | ||
| 978 | .prcm = { | ||
| 979 | .omap2 = { | ||
| 980 | .prcm_reg_id = 1, | ||
| 981 | .module_bit = OMAP3430_EN_GPIO2_SHIFT, | ||
| 982 | .module_offs = OMAP3430_PER_MOD, | ||
| 983 | .idlest_reg_id = 1, | ||
| 984 | .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, | ||
| 985 | }, | ||
| 986 | }, | ||
| 987 | .slaves = omap3xxx_gpio2_slaves, | ||
| 988 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves), | ||
| 989 | .class = &omap3xxx_gpio_hwmod_class, | ||
| 990 | .dev_attr = &gpio_dev_attr, | ||
| 991 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
| 992 | }; | ||
| 993 | |||
| 994 | /* gpio3 */ | ||
| 995 | static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = { | ||
| 996 | { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */ | ||
| 997 | }; | ||
| 998 | |||
| 999 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { | ||
| 1000 | { .role = "dbclk", .clk = "gpio3_dbck", }, | ||
| 1001 | }; | ||
| 1002 | |||
| 1003 | static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = { | ||
| 1004 | &omap3xxx_l4_per__gpio3, | ||
| 1005 | }; | ||
| 1006 | |||
| 1007 | static struct omap_hwmod omap3xxx_gpio3_hwmod = { | ||
| 1008 | .name = "gpio3", | ||
| 1009 | .mpu_irqs = omap3xxx_gpio3_irqs, | ||
| 1010 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs), | ||
| 1011 | .main_clk = "gpio3_ick", | ||
| 1012 | .opt_clks = gpio3_opt_clks, | ||
| 1013 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | ||
| 1014 | .prcm = { | ||
| 1015 | .omap2 = { | ||
| 1016 | .prcm_reg_id = 1, | ||
| 1017 | .module_bit = OMAP3430_EN_GPIO3_SHIFT, | ||
| 1018 | .module_offs = OMAP3430_PER_MOD, | ||
| 1019 | .idlest_reg_id = 1, | ||
| 1020 | .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, | ||
| 1021 | }, | ||
| 1022 | }, | ||
| 1023 | .slaves = omap3xxx_gpio3_slaves, | ||
| 1024 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves), | ||
| 1025 | .class = &omap3xxx_gpio_hwmod_class, | ||
| 1026 | .dev_attr = &gpio_dev_attr, | ||
| 1027 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
| 1028 | }; | ||
| 1029 | |||
| 1030 | /* gpio4 */ | ||
| 1031 | static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = { | ||
| 1032 | { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */ | ||
| 1033 | }; | ||
| 1034 | |||
| 1035 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { | ||
| 1036 | { .role = "dbclk", .clk = "gpio4_dbck", }, | ||
| 1037 | }; | ||
| 1038 | |||
| 1039 | static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = { | ||
| 1040 | &omap3xxx_l4_per__gpio4, | ||
| 1041 | }; | ||
| 1042 | |||
| 1043 | static struct omap_hwmod omap3xxx_gpio4_hwmod = { | ||
| 1044 | .name = "gpio4", | ||
| 1045 | .mpu_irqs = omap3xxx_gpio4_irqs, | ||
| 1046 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs), | ||
| 1047 | .main_clk = "gpio4_ick", | ||
| 1048 | .opt_clks = gpio4_opt_clks, | ||
| 1049 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | ||
| 1050 | .prcm = { | ||
| 1051 | .omap2 = { | ||
| 1052 | .prcm_reg_id = 1, | ||
| 1053 | .module_bit = OMAP3430_EN_GPIO4_SHIFT, | ||
| 1054 | .module_offs = OMAP3430_PER_MOD, | ||
| 1055 | .idlest_reg_id = 1, | ||
| 1056 | .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, | ||
| 1057 | }, | ||
| 1058 | }, | ||
| 1059 | .slaves = omap3xxx_gpio4_slaves, | ||
| 1060 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves), | ||
| 1061 | .class = &omap3xxx_gpio_hwmod_class, | ||
| 1062 | .dev_attr = &gpio_dev_attr, | ||
| 1063 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
| 1064 | }; | ||
| 1065 | |||
| 1066 | /* gpio5 */ | ||
| 1067 | static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { | ||
| 1068 | { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */ | ||
| 1069 | }; | ||
| 1070 | |||
| 1071 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { | ||
| 1072 | { .role = "dbclk", .clk = "gpio5_dbck", }, | ||
| 1073 | }; | ||
| 1074 | |||
| 1075 | static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = { | ||
| 1076 | &omap3xxx_l4_per__gpio5, | ||
| 1077 | }; | ||
| 1078 | |||
| 1079 | static struct omap_hwmod omap3xxx_gpio5_hwmod = { | ||
| 1080 | .name = "gpio5", | ||
| 1081 | .mpu_irqs = omap3xxx_gpio5_irqs, | ||
| 1082 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs), | ||
| 1083 | .main_clk = "gpio5_ick", | ||
| 1084 | .opt_clks = gpio5_opt_clks, | ||
| 1085 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | ||
| 1086 | .prcm = { | ||
| 1087 | .omap2 = { | ||
| 1088 | .prcm_reg_id = 1, | ||
| 1089 | .module_bit = OMAP3430_EN_GPIO5_SHIFT, | ||
| 1090 | .module_offs = OMAP3430_PER_MOD, | ||
| 1091 | .idlest_reg_id = 1, | ||
| 1092 | .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, | ||
| 1093 | }, | ||
| 1094 | }, | ||
| 1095 | .slaves = omap3xxx_gpio5_slaves, | ||
| 1096 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves), | ||
| 1097 | .class = &omap3xxx_gpio_hwmod_class, | ||
| 1098 | .dev_attr = &gpio_dev_attr, | ||
| 1099 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
| 1100 | }; | ||
| 1101 | |||
| 1102 | /* gpio6 */ | ||
| 1103 | static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { | ||
| 1104 | { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */ | ||
| 1105 | }; | ||
| 1106 | |||
| 1107 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { | ||
| 1108 | { .role = "dbclk", .clk = "gpio6_dbck", }, | ||
| 1109 | }; | ||
| 1110 | |||
| 1111 | static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = { | ||
| 1112 | &omap3xxx_l4_per__gpio6, | ||
| 1113 | }; | ||
| 1114 | |||
| 1115 | static struct omap_hwmod omap3xxx_gpio6_hwmod = { | ||
| 1116 | .name = "gpio6", | ||
| 1117 | .mpu_irqs = omap3xxx_gpio6_irqs, | ||
| 1118 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs), | ||
| 1119 | .main_clk = "gpio6_ick", | ||
| 1120 | .opt_clks = gpio6_opt_clks, | ||
| 1121 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | ||
| 1122 | .prcm = { | ||
| 1123 | .omap2 = { | ||
| 1124 | .prcm_reg_id = 1, | ||
| 1125 | .module_bit = OMAP3430_EN_GPIO6_SHIFT, | ||
| 1126 | .module_offs = OMAP3430_PER_MOD, | ||
| 1127 | .idlest_reg_id = 1, | ||
| 1128 | .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, | ||
| 1129 | }, | ||
| 1130 | }, | ||
| 1131 | .slaves = omap3xxx_gpio6_slaves, | ||
| 1132 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves), | ||
| 1133 | .class = &omap3xxx_gpio_hwmod_class, | ||
| 1134 | .dev_attr = &gpio_dev_attr, | ||
| 1135 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
| 1136 | }; | ||
| 1137 | |||
| 1138 | /* dma_system -> L3 */ | ||
| 1139 | static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { | ||
| 1140 | .master = &omap3xxx_dma_system_hwmod, | ||
| 1141 | .slave = &omap3xxx_l3_main_hwmod, | ||
| 1142 | .clk = "core_l3_ick", | ||
| 1143 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 1144 | }; | ||
| 1145 | |||
| 1146 | /* dma attributes */ | ||
| 1147 | static struct omap_dma_dev_attr dma_dev_attr = { | ||
| 1148 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | ||
| 1149 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | ||
| 1150 | .lch_count = 32, | ||
| 1151 | }; | ||
| 1152 | |||
| 1153 | static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = { | ||
| 1154 | .rev_offs = 0x0000, | ||
| 1155 | .sysc_offs = 0x002c, | ||
| 1156 | .syss_offs = 0x0028, | ||
| 1157 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | ||
| 1158 | SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | | ||
| 1159 | SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE), | ||
| 1160 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | ||
| 1161 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | ||
| 1162 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
| 1163 | }; | ||
| 1164 | |||
| 1165 | static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { | ||
| 1166 | .name = "dma", | ||
| 1167 | .sysc = &omap3xxx_dma_sysc, | ||
| 1168 | }; | ||
| 1169 | |||
| 1170 | /* dma_system */ | ||
| 1171 | static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = { | ||
| 1172 | { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */ | ||
| 1173 | { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */ | ||
| 1174 | { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */ | ||
| 1175 | { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */ | ||
| 1176 | }; | ||
| 1177 | |||
| 1178 | static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { | ||
| 1179 | { | ||
| 1180 | .pa_start = 0x48056000, | ||
| 1181 | .pa_end = 0x4a0560ff, | ||
| 1182 | .flags = ADDR_TYPE_RT | ||
| 1183 | }, | ||
| 1184 | }; | ||
| 1185 | |||
| 1186 | /* dma_system master ports */ | ||
| 1187 | static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = { | ||
| 1188 | &omap3xxx_dma_system__l3, | ||
| 1189 | }; | ||
| 1190 | |||
| 1191 | /* l4_cfg -> dma_system */ | ||
| 1192 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { | ||
| 1193 | .master = &omap3xxx_l4_core_hwmod, | ||
| 1194 | .slave = &omap3xxx_dma_system_hwmod, | ||
| 1195 | .clk = "core_l4_ick", | ||
| 1196 | .addr = omap3xxx_dma_system_addrs, | ||
| 1197 | .addr_cnt = ARRAY_SIZE(omap3xxx_dma_system_addrs), | ||
| 1198 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 1199 | }; | ||
| 1200 | |||
| 1201 | /* dma_system slave ports */ | ||
| 1202 | static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = { | ||
| 1203 | &omap3xxx_l4_core__dma_system, | ||
| 1204 | }; | ||
| 1205 | |||
| 1206 | static struct omap_hwmod omap3xxx_dma_system_hwmod = { | ||
| 1207 | .name = "dma", | ||
| 1208 | .class = &omap3xxx_dma_hwmod_class, | ||
| 1209 | .mpu_irqs = omap3xxx_dma_system_irqs, | ||
| 1210 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dma_system_irqs), | ||
| 1211 | .main_clk = "core_l3_ick", | ||
| 1212 | .prcm = { | ||
| 1213 | .omap2 = { | ||
| 1214 | .module_offs = CORE_MOD, | ||
| 1215 | .prcm_reg_id = 1, | ||
| 1216 | .module_bit = OMAP3430_ST_SDMA_SHIFT, | ||
| 1217 | .idlest_reg_id = 1, | ||
| 1218 | .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, | ||
| 1219 | }, | ||
| 1220 | }, | ||
| 1221 | .slaves = omap3xxx_dma_system_slaves, | ||
| 1222 | .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves), | ||
| 1223 | .masters = omap3xxx_dma_system_masters, | ||
| 1224 | .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters), | ||
| 1225 | .dev_attr = &dma_dev_attr, | ||
| 1226 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
| 1227 | .flags = HWMOD_NO_IDLEST, | ||
| 1228 | }; | ||
| 1229 | |||
| 1230 | /* SR common */ | ||
| 1231 | static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { | ||
| 1232 | .clkact_shift = 20, | ||
| 1233 | }; | ||
| 1234 | |||
| 1235 | static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = { | ||
| 1236 | .sysc_offs = 0x24, | ||
| 1237 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE), | ||
| 1238 | .clockact = CLOCKACT_TEST_ICLK, | ||
| 1239 | .sysc_fields = &omap34xx_sr_sysc_fields, | ||
| 1240 | }; | ||
| 1241 | |||
| 1242 | static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = { | ||
| 1243 | .name = "smartreflex", | ||
| 1244 | .sysc = &omap34xx_sr_sysc, | ||
| 1245 | .rev = 1, | ||
| 1246 | }; | ||
| 1247 | |||
| 1248 | static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { | ||
| 1249 | .sidle_shift = 24, | ||
| 1250 | .enwkup_shift = 26 | ||
| 1251 | }; | ||
| 1252 | |||
| 1253 | static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { | ||
| 1254 | .sysc_offs = 0x38, | ||
| 1255 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
| 1256 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | ||
| 1257 | SYSC_NO_CACHE), | ||
| 1258 | .sysc_fields = &omap36xx_sr_sysc_fields, | ||
| 1259 | }; | ||
| 1260 | |||
| 1261 | static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = { | ||
| 1262 | .name = "smartreflex", | ||
| 1263 | .sysc = &omap36xx_sr_sysc, | ||
| 1264 | .rev = 2, | ||
| 1265 | }; | ||
| 1266 | |||
| 1267 | /* SR1 */ | ||
| 1268 | static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = { | ||
| 1269 | &omap3_l4_core__sr1, | ||
| 1270 | }; | ||
| 1271 | |||
| 1272 | static struct omap_hwmod omap34xx_sr1_hwmod = { | ||
| 1273 | .name = "sr1_hwmod", | ||
| 1274 | .class = &omap34xx_smartreflex_hwmod_class, | ||
| 1275 | .main_clk = "sr1_fck", | ||
| 1276 | .vdd_name = "mpu", | ||
| 1277 | .prcm = { | ||
| 1278 | .omap2 = { | ||
| 1279 | .prcm_reg_id = 1, | ||
| 1280 | .module_bit = OMAP3430_EN_SR1_SHIFT, | ||
| 1281 | .module_offs = WKUP_MOD, | ||
| 1282 | .idlest_reg_id = 1, | ||
| 1283 | .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, | ||
| 1284 | }, | ||
| 1285 | }, | ||
| 1286 | .slaves = omap3_sr1_slaves, | ||
| 1287 | .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves), | ||
| 1288 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 | | ||
| 1289 | CHIP_IS_OMAP3430ES3_0 | | ||
| 1290 | CHIP_IS_OMAP3430ES3_1), | ||
| 1291 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | ||
| 1292 | }; | ||
| 1293 | |||
| 1294 | static struct omap_hwmod omap36xx_sr1_hwmod = { | ||
| 1295 | .name = "sr1_hwmod", | ||
| 1296 | .class = &omap36xx_smartreflex_hwmod_class, | ||
| 1297 | .main_clk = "sr1_fck", | ||
| 1298 | .vdd_name = "mpu", | ||
| 1299 | .prcm = { | ||
| 1300 | .omap2 = { | ||
| 1301 | .prcm_reg_id = 1, | ||
| 1302 | .module_bit = OMAP3430_EN_SR1_SHIFT, | ||
| 1303 | .module_offs = WKUP_MOD, | ||
| 1304 | .idlest_reg_id = 1, | ||
| 1305 | .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, | ||
| 1306 | }, | ||
| 1307 | }, | ||
| 1308 | .slaves = omap3_sr1_slaves, | ||
| 1309 | .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves), | ||
| 1310 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), | ||
| 1311 | }; | ||
| 1312 | |||
| 1313 | /* SR2 */ | ||
| 1314 | static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = { | ||
| 1315 | &omap3_l4_core__sr2, | ||
| 1316 | }; | ||
| 1317 | |||
| 1318 | static struct omap_hwmod omap34xx_sr2_hwmod = { | ||
| 1319 | .name = "sr2_hwmod", | ||
| 1320 | .class = &omap34xx_smartreflex_hwmod_class, | ||
| 1321 | .main_clk = "sr2_fck", | ||
| 1322 | .vdd_name = "core", | ||
| 1323 | .prcm = { | ||
| 1324 | .omap2 = { | ||
| 1325 | .prcm_reg_id = 1, | ||
| 1326 | .module_bit = OMAP3430_EN_SR2_SHIFT, | ||
| 1327 | .module_offs = WKUP_MOD, | ||
| 1328 | .idlest_reg_id = 1, | ||
| 1329 | .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, | ||
| 1330 | }, | ||
| 1331 | }, | ||
| 1332 | .slaves = omap3_sr2_slaves, | ||
| 1333 | .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves), | ||
| 1334 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 | | ||
| 1335 | CHIP_IS_OMAP3430ES3_0 | | ||
| 1336 | CHIP_IS_OMAP3430ES3_1), | ||
| 1337 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | ||
| 1338 | }; | ||
| 1339 | |||
| 1340 | static struct omap_hwmod omap36xx_sr2_hwmod = { | ||
| 1341 | .name = "sr2_hwmod", | ||
| 1342 | .class = &omap36xx_smartreflex_hwmod_class, | ||
| 1343 | .main_clk = "sr2_fck", | ||
| 1344 | .vdd_name = "core", | ||
| 1345 | .prcm = { | ||
| 1346 | .omap2 = { | ||
| 1347 | .prcm_reg_id = 1, | ||
| 1348 | .module_bit = OMAP3430_EN_SR2_SHIFT, | ||
| 1349 | .module_offs = WKUP_MOD, | ||
| 1350 | .idlest_reg_id = 1, | ||
| 1351 | .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, | ||
| 1352 | }, | ||
| 1353 | }, | ||
| 1354 | .slaves = omap3_sr2_slaves, | ||
| 1355 | .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves), | ||
| 1356 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), | ||
| 1357 | }; | ||
| 1358 | |||
| 512 | static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { | 1359 | static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { |
| 513 | &omap3xxx_l3_main_hwmod, | 1360 | &omap3xxx_l3_main_hwmod, |
| 514 | &omap3xxx_l4_core_hwmod, | 1361 | &omap3xxx_l4_core_hwmod, |
| @@ -521,6 +1368,25 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { | |||
| 521 | &omap3xxx_uart2_hwmod, | 1368 | &omap3xxx_uart2_hwmod, |
| 522 | &omap3xxx_uart3_hwmod, | 1369 | &omap3xxx_uart3_hwmod, |
| 523 | &omap3xxx_uart4_hwmod, | 1370 | &omap3xxx_uart4_hwmod, |
| 1371 | &omap3xxx_i2c1_hwmod, | ||
| 1372 | &omap3xxx_i2c2_hwmod, | ||
| 1373 | &omap3xxx_i2c3_hwmod, | ||
| 1374 | &omap34xx_sr1_hwmod, | ||
| 1375 | &omap34xx_sr2_hwmod, | ||
| 1376 | &omap36xx_sr1_hwmod, | ||
| 1377 | &omap36xx_sr2_hwmod, | ||
| 1378 | |||
| 1379 | |||
| 1380 | /* gpio class */ | ||
| 1381 | &omap3xxx_gpio1_hwmod, | ||
| 1382 | &omap3xxx_gpio2_hwmod, | ||
| 1383 | &omap3xxx_gpio3_hwmod, | ||
| 1384 | &omap3xxx_gpio4_hwmod, | ||
| 1385 | &omap3xxx_gpio5_hwmod, | ||
| 1386 | &omap3xxx_gpio6_hwmod, | ||
| 1387 | |||
| 1388 | /* dma_system class*/ | ||
| 1389 | &omap3xxx_dma_system_hwmod, | ||
| 524 | NULL, | 1390 | NULL, |
| 525 | }; | 1391 | }; |
| 526 | 1392 | ||
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 7274db4de487..c2806bd11fbf 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c | |||
| @@ -22,11 +22,16 @@ | |||
| 22 | 22 | ||
| 23 | #include <plat/omap_hwmod.h> | 23 | #include <plat/omap_hwmod.h> |
| 24 | #include <plat/cpu.h> | 24 | #include <plat/cpu.h> |
| 25 | #include <plat/gpio.h> | ||
| 26 | #include <plat/dma.h> | ||
| 25 | 27 | ||
| 26 | #include "omap_hwmod_common_data.h" | 28 | #include "omap_hwmod_common_data.h" |
| 27 | 29 | ||
| 28 | #include "cm.h" | 30 | #include "cm1_44xx.h" |
| 31 | #include "cm2_44xx.h" | ||
| 32 | #include "prm44xx.h" | ||
| 29 | #include "prm-regbits-44xx.h" | 33 | #include "prm-regbits-44xx.h" |
| 34 | #include "wd_timer.h" | ||
| 30 | 35 | ||
| 31 | /* Base offset for all OMAP4 interrupts external to MPUSS */ | 36 | /* Base offset for all OMAP4 interrupts external to MPUSS */ |
| 32 | #define OMAP44XX_IRQ_GIC_START 32 | 37 | #define OMAP44XX_IRQ_GIC_START 32 |
| @@ -35,8 +40,11 @@ | |||
| 35 | #define OMAP44XX_DMA_REQ_START 1 | 40 | #define OMAP44XX_DMA_REQ_START 1 |
| 36 | 41 | ||
| 37 | /* Backward references (IPs with Bus Master capability) */ | 42 | /* Backward references (IPs with Bus Master capability) */ |
| 43 | static struct omap_hwmod omap44xx_dma_system_hwmod; | ||
| 38 | static struct omap_hwmod omap44xx_dmm_hwmod; | 44 | static struct omap_hwmod omap44xx_dmm_hwmod; |
| 45 | static struct omap_hwmod omap44xx_dsp_hwmod; | ||
| 39 | static struct omap_hwmod omap44xx_emif_fw_hwmod; | 46 | static struct omap_hwmod omap44xx_emif_fw_hwmod; |
| 47 | static struct omap_hwmod omap44xx_iva_hwmod; | ||
| 40 | static struct omap_hwmod omap44xx_l3_instr_hwmod; | 48 | static struct omap_hwmod omap44xx_l3_instr_hwmod; |
| 41 | static struct omap_hwmod omap44xx_l3_main_1_hwmod; | 49 | static struct omap_hwmod omap44xx_l3_main_1_hwmod; |
| 42 | static struct omap_hwmod omap44xx_l3_main_2_hwmod; | 50 | static struct omap_hwmod omap44xx_l3_main_2_hwmod; |
| @@ -58,7 +66,7 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod; | |||
| 58 | * instance(s): dmm | 66 | * instance(s): dmm |
| 59 | */ | 67 | */ |
| 60 | static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { | 68 | static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { |
| 61 | .name = "dmm", | 69 | .name = "dmm", |
| 62 | }; | 70 | }; |
| 63 | 71 | ||
| 64 | /* dmm interface data */ | 72 | /* dmm interface data */ |
| @@ -67,7 +75,15 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { | |||
| 67 | .master = &omap44xx_l3_main_1_hwmod, | 75 | .master = &omap44xx_l3_main_1_hwmod, |
| 68 | .slave = &omap44xx_dmm_hwmod, | 76 | .slave = &omap44xx_dmm_hwmod, |
| 69 | .clk = "l3_div_ck", | 77 | .clk = "l3_div_ck", |
| 70 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 78 | .user = OCP_USER_SDMA, |
| 79 | }; | ||
| 80 | |||
| 81 | static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = { | ||
| 82 | { | ||
| 83 | .pa_start = 0x4e000000, | ||
| 84 | .pa_end = 0x4e0007ff, | ||
| 85 | .flags = ADDR_TYPE_RT | ||
| 86 | }, | ||
| 71 | }; | 87 | }; |
| 72 | 88 | ||
| 73 | /* mpu -> dmm */ | 89 | /* mpu -> dmm */ |
| @@ -75,7 +91,9 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { | |||
| 75 | .master = &omap44xx_mpu_hwmod, | 91 | .master = &omap44xx_mpu_hwmod, |
| 76 | .slave = &omap44xx_dmm_hwmod, | 92 | .slave = &omap44xx_dmm_hwmod, |
| 77 | .clk = "l3_div_ck", | 93 | .clk = "l3_div_ck", |
| 78 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 94 | .addr = omap44xx_dmm_addrs, |
| 95 | .addr_cnt = ARRAY_SIZE(omap44xx_dmm_addrs), | ||
| 96 | .user = OCP_USER_MPU, | ||
| 79 | }; | 97 | }; |
| 80 | 98 | ||
| 81 | /* dmm slave ports */ | 99 | /* dmm slave ports */ |
| @@ -103,7 +121,7 @@ static struct omap_hwmod omap44xx_dmm_hwmod = { | |||
| 103 | * instance(s): emif_fw | 121 | * instance(s): emif_fw |
| 104 | */ | 122 | */ |
| 105 | static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { | 123 | static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { |
| 106 | .name = "emif_fw", | 124 | .name = "emif_fw", |
| 107 | }; | 125 | }; |
| 108 | 126 | ||
| 109 | /* emif_fw interface data */ | 127 | /* emif_fw interface data */ |
| @@ -115,12 +133,22 @@ static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { | |||
| 115 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 133 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 116 | }; | 134 | }; |
| 117 | 135 | ||
| 136 | static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = { | ||
| 137 | { | ||
| 138 | .pa_start = 0x4a20c000, | ||
| 139 | .pa_end = 0x4a20c0ff, | ||
| 140 | .flags = ADDR_TYPE_RT | ||
| 141 | }, | ||
| 142 | }; | ||
| 143 | |||
| 118 | /* l4_cfg -> emif_fw */ | 144 | /* l4_cfg -> emif_fw */ |
| 119 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { | 145 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { |
| 120 | .master = &omap44xx_l4_cfg_hwmod, | 146 | .master = &omap44xx_l4_cfg_hwmod, |
| 121 | .slave = &omap44xx_emif_fw_hwmod, | 147 | .slave = &omap44xx_emif_fw_hwmod, |
| 122 | .clk = "l4_div_ck", | 148 | .clk = "l4_div_ck", |
| 123 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 149 | .addr = omap44xx_emif_fw_addrs, |
| 150 | .addr_cnt = ARRAY_SIZE(omap44xx_emif_fw_addrs), | ||
| 151 | .user = OCP_USER_MPU, | ||
| 124 | }; | 152 | }; |
| 125 | 153 | ||
| 126 | /* emif_fw slave ports */ | 154 | /* emif_fw slave ports */ |
| @@ -142,10 +170,18 @@ static struct omap_hwmod omap44xx_emif_fw_hwmod = { | |||
| 142 | * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 | 170 | * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 |
| 143 | */ | 171 | */ |
| 144 | static struct omap_hwmod_class omap44xx_l3_hwmod_class = { | 172 | static struct omap_hwmod_class omap44xx_l3_hwmod_class = { |
| 145 | .name = "l3", | 173 | .name = "l3", |
| 146 | }; | 174 | }; |
| 147 | 175 | ||
| 148 | /* l3_instr interface data */ | 176 | /* l3_instr interface data */ |
| 177 | /* iva -> l3_instr */ | ||
| 178 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { | ||
| 179 | .master = &omap44xx_iva_hwmod, | ||
| 180 | .slave = &omap44xx_l3_instr_hwmod, | ||
| 181 | .clk = "l3_div_ck", | ||
| 182 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 183 | }; | ||
| 184 | |||
| 149 | /* l3_main_3 -> l3_instr */ | 185 | /* l3_main_3 -> l3_instr */ |
| 150 | static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { | 186 | static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { |
| 151 | .master = &omap44xx_l3_main_3_hwmod, | 187 | .master = &omap44xx_l3_main_3_hwmod, |
| @@ -156,6 +192,7 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { | |||
| 156 | 192 | ||
| 157 | /* l3_instr slave ports */ | 193 | /* l3_instr slave ports */ |
| 158 | static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = { | 194 | static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = { |
| 195 | &omap44xx_iva__l3_instr, | ||
| 159 | &omap44xx_l3_main_3__l3_instr, | 196 | &omap44xx_l3_main_3__l3_instr, |
| 160 | }; | 197 | }; |
| 161 | 198 | ||
| @@ -167,6 +204,15 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = { | |||
| 167 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 204 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 168 | }; | 205 | }; |
| 169 | 206 | ||
| 207 | /* l3_main_1 interface data */ | ||
| 208 | /* dsp -> l3_main_1 */ | ||
| 209 | static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { | ||
| 210 | .master = &omap44xx_dsp_hwmod, | ||
| 211 | .slave = &omap44xx_l3_main_1_hwmod, | ||
| 212 | .clk = "l3_div_ck", | ||
| 213 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 214 | }; | ||
| 215 | |||
| 170 | /* l3_main_2 -> l3_main_1 */ | 216 | /* l3_main_2 -> l3_main_1 */ |
| 171 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { | 217 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { |
| 172 | .master = &omap44xx_l3_main_2_hwmod, | 218 | .master = &omap44xx_l3_main_2_hwmod, |
| @@ -193,6 +239,7 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { | |||
| 193 | 239 | ||
| 194 | /* l3_main_1 slave ports */ | 240 | /* l3_main_1 slave ports */ |
| 195 | static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = { | 241 | static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = { |
| 242 | &omap44xx_dsp__l3_main_1, | ||
| 196 | &omap44xx_l3_main_2__l3_main_1, | 243 | &omap44xx_l3_main_2__l3_main_1, |
| 197 | &omap44xx_l4_cfg__l3_main_1, | 244 | &omap44xx_l4_cfg__l3_main_1, |
| 198 | &omap44xx_mpu__l3_main_1, | 245 | &omap44xx_mpu__l3_main_1, |
| @@ -207,6 +254,22 @@ static struct omap_hwmod omap44xx_l3_main_1_hwmod = { | |||
| 207 | }; | 254 | }; |
| 208 | 255 | ||
| 209 | /* l3_main_2 interface data */ | 256 | /* l3_main_2 interface data */ |
| 257 | /* dma_system -> l3_main_2 */ | ||
| 258 | static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { | ||
| 259 | .master = &omap44xx_dma_system_hwmod, | ||
| 260 | .slave = &omap44xx_l3_main_2_hwmod, | ||
| 261 | .clk = "l3_div_ck", | ||
| 262 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 263 | }; | ||
| 264 | |||
| 265 | /* iva -> l3_main_2 */ | ||
| 266 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { | ||
| 267 | .master = &omap44xx_iva_hwmod, | ||
| 268 | .slave = &omap44xx_l3_main_2_hwmod, | ||
| 269 | .clk = "l3_div_ck", | ||
| 270 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 271 | }; | ||
| 272 | |||
| 210 | /* l3_main_1 -> l3_main_2 */ | 273 | /* l3_main_1 -> l3_main_2 */ |
| 211 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { | 274 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { |
| 212 | .master = &omap44xx_l3_main_1_hwmod, | 275 | .master = &omap44xx_l3_main_1_hwmod, |
| @@ -225,6 +288,8 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { | |||
| 225 | 288 | ||
| 226 | /* l3_main_2 slave ports */ | 289 | /* l3_main_2 slave ports */ |
| 227 | static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = { | 290 | static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = { |
| 291 | &omap44xx_dma_system__l3_main_2, | ||
| 292 | &omap44xx_iva__l3_main_2, | ||
| 228 | &omap44xx_l3_main_1__l3_main_2, | 293 | &omap44xx_l3_main_1__l3_main_2, |
| 229 | &omap44xx_l4_cfg__l3_main_2, | 294 | &omap44xx_l4_cfg__l3_main_2, |
| 230 | }; | 295 | }; |
| @@ -282,10 +347,18 @@ static struct omap_hwmod omap44xx_l3_main_3_hwmod = { | |||
| 282 | * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup | 347 | * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup |
| 283 | */ | 348 | */ |
| 284 | static struct omap_hwmod_class omap44xx_l4_hwmod_class = { | 349 | static struct omap_hwmod_class omap44xx_l4_hwmod_class = { |
| 285 | .name = "l4", | 350 | .name = "l4", |
| 286 | }; | 351 | }; |
| 287 | 352 | ||
| 288 | /* l4_abe interface data */ | 353 | /* l4_abe interface data */ |
| 354 | /* dsp -> l4_abe */ | ||
| 355 | static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { | ||
| 356 | .master = &omap44xx_dsp_hwmod, | ||
| 357 | .slave = &omap44xx_l4_abe_hwmod, | ||
| 358 | .clk = "ocp_abe_iclk", | ||
| 359 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 360 | }; | ||
| 361 | |||
| 289 | /* l3_main_1 -> l4_abe */ | 362 | /* l3_main_1 -> l4_abe */ |
| 290 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { | 363 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { |
| 291 | .master = &omap44xx_l3_main_1_hwmod, | 364 | .master = &omap44xx_l3_main_1_hwmod, |
| @@ -304,6 +377,7 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { | |||
| 304 | 377 | ||
| 305 | /* l4_abe slave ports */ | 378 | /* l4_abe slave ports */ |
| 306 | static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = { | 379 | static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = { |
| 380 | &omap44xx_dsp__l4_abe, | ||
| 307 | &omap44xx_l3_main_1__l4_abe, | 381 | &omap44xx_l3_main_1__l4_abe, |
| 308 | &omap44xx_mpu__l4_abe, | 382 | &omap44xx_mpu__l4_abe, |
| 309 | }; | 383 | }; |
| @@ -387,7 +461,7 @@ static struct omap_hwmod omap44xx_l4_wkup_hwmod = { | |||
| 387 | * instance(s): mpu_private | 461 | * instance(s): mpu_private |
| 388 | */ | 462 | */ |
| 389 | static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { | 463 | static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { |
| 390 | .name = "mpu_bus", | 464 | .name = "mpu_bus", |
| 391 | }; | 465 | }; |
| 392 | 466 | ||
| 393 | /* mpu_private interface data */ | 467 | /* mpu_private interface data */ |
| @@ -413,12 +487,960 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { | |||
| 413 | }; | 487 | }; |
| 414 | 488 | ||
| 415 | /* | 489 | /* |
| 490 | * Modules omap_hwmod structures | ||
| 491 | * | ||
| 492 | * The following IPs are excluded for the moment because: | ||
| 493 | * - They do not need an explicit SW control using omap_hwmod API. | ||
| 494 | * - They still need to be validated with the driver | ||
| 495 | * properly adapted to omap_hwmod / omap_device | ||
| 496 | * | ||
| 497 | * aess | ||
| 498 | * bandgap | ||
| 499 | * c2c | ||
| 500 | * c2c_target_fw | ||
| 501 | * cm_core | ||
| 502 | * cm_core_aon | ||
| 503 | * counter_32k | ||
| 504 | * ctrl_module_core | ||
| 505 | * ctrl_module_pad_core | ||
| 506 | * ctrl_module_pad_wkup | ||
| 507 | * ctrl_module_wkup | ||
| 508 | * debugss | ||
| 509 | * dmic | ||
| 510 | * dss | ||
| 511 | * dss_dispc | ||
| 512 | * dss_dsi1 | ||
| 513 | * dss_dsi2 | ||
| 514 | * dss_hdmi | ||
| 515 | * dss_rfbi | ||
| 516 | * dss_venc | ||
| 517 | * efuse_ctrl_cust | ||
| 518 | * efuse_ctrl_std | ||
| 519 | * elm | ||
| 520 | * emif1 | ||
| 521 | * emif2 | ||
| 522 | * fdif | ||
| 523 | * gpmc | ||
| 524 | * gpu | ||
| 525 | * hdq1w | ||
| 526 | * hsi | ||
| 527 | * ipu | ||
| 528 | * iss | ||
| 529 | * kbd | ||
| 530 | * mailbox | ||
| 531 | * mcasp | ||
| 532 | * mcbsp1 | ||
| 533 | * mcbsp2 | ||
| 534 | * mcbsp3 | ||
| 535 | * mcbsp4 | ||
| 536 | * mcpdm | ||
| 537 | * mcspi1 | ||
| 538 | * mcspi2 | ||
| 539 | * mcspi3 | ||
| 540 | * mcspi4 | ||
| 541 | * mmc1 | ||
| 542 | * mmc2 | ||
| 543 | * mmc3 | ||
| 544 | * mmc4 | ||
| 545 | * mmc5 | ||
| 546 | * mpu_c0 | ||
| 547 | * mpu_c1 | ||
| 548 | * ocmc_ram | ||
| 549 | * ocp2scp_usb_phy | ||
| 550 | * ocp_wp_noc | ||
| 551 | * prcm | ||
| 552 | * prcm_mpu | ||
| 553 | * prm | ||
| 554 | * scrm | ||
| 555 | * sl2if | ||
| 556 | * slimbus1 | ||
| 557 | * slimbus2 | ||
| 558 | * spinlock | ||
| 559 | * timer1 | ||
| 560 | * timer10 | ||
| 561 | * timer11 | ||
| 562 | * timer2 | ||
| 563 | * timer3 | ||
| 564 | * timer4 | ||
| 565 | * timer5 | ||
| 566 | * timer6 | ||
| 567 | * timer7 | ||
| 568 | * timer8 | ||
| 569 | * timer9 | ||
| 570 | * usb_host_fs | ||
| 571 | * usb_host_hs | ||
| 572 | * usb_otg_hs | ||
| 573 | * usb_phy_cm | ||
| 574 | * usb_tll_hs | ||
| 575 | * usim | ||
| 576 | */ | ||
| 577 | |||
| 578 | /* | ||
| 579 | * 'dma' class | ||
| 580 | * dma controller for data exchange between memory to memory (i.e. internal or | ||
| 581 | * external memory) and gp peripherals to memory or memory to gp peripherals | ||
| 582 | */ | ||
| 583 | |||
| 584 | static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = { | ||
| 585 | .rev_offs = 0x0000, | ||
| 586 | .sysc_offs = 0x002c, | ||
| 587 | .syss_offs = 0x0028, | ||
| 588 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | ||
| 589 | SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | | ||
| 590 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | ||
| 591 | SYSS_HAS_RESET_STATUS), | ||
| 592 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | ||
| 593 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | ||
| 594 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
| 595 | }; | ||
| 596 | |||
| 597 | static struct omap_hwmod_class omap44xx_dma_hwmod_class = { | ||
| 598 | .name = "dma", | ||
| 599 | .sysc = &omap44xx_dma_sysc, | ||
| 600 | }; | ||
| 601 | |||
| 602 | /* dma dev_attr */ | ||
| 603 | static struct omap_dma_dev_attr dma_dev_attr = { | ||
| 604 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | ||
| 605 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | ||
| 606 | .lch_count = 32, | ||
| 607 | }; | ||
| 608 | |||
| 609 | /* dma_system */ | ||
| 610 | static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = { | ||
| 611 | { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START }, | ||
| 612 | { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START }, | ||
| 613 | { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START }, | ||
| 614 | { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START }, | ||
| 615 | }; | ||
| 616 | |||
| 617 | /* dma_system master ports */ | ||
| 618 | static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = { | ||
| 619 | &omap44xx_dma_system__l3_main_2, | ||
| 620 | }; | ||
| 621 | |||
| 622 | static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { | ||
| 623 | { | ||
| 624 | .pa_start = 0x4a056000, | ||
| 625 | .pa_end = 0x4a0560ff, | ||
| 626 | .flags = ADDR_TYPE_RT | ||
| 627 | }, | ||
| 628 | }; | ||
| 629 | |||
| 630 | /* l4_cfg -> dma_system */ | ||
| 631 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { | ||
| 632 | .master = &omap44xx_l4_cfg_hwmod, | ||
| 633 | .slave = &omap44xx_dma_system_hwmod, | ||
| 634 | .clk = "l4_div_ck", | ||
| 635 | .addr = omap44xx_dma_system_addrs, | ||
| 636 | .addr_cnt = ARRAY_SIZE(omap44xx_dma_system_addrs), | ||
| 637 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 638 | }; | ||
| 639 | |||
| 640 | /* dma_system slave ports */ | ||
| 641 | static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = { | ||
| 642 | &omap44xx_l4_cfg__dma_system, | ||
| 643 | }; | ||
| 644 | |||
| 645 | static struct omap_hwmod omap44xx_dma_system_hwmod = { | ||
| 646 | .name = "dma_system", | ||
| 647 | .class = &omap44xx_dma_hwmod_class, | ||
| 648 | .mpu_irqs = omap44xx_dma_system_irqs, | ||
| 649 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dma_system_irqs), | ||
| 650 | .main_clk = "l3_div_ck", | ||
| 651 | .prcm = { | ||
| 652 | .omap4 = { | ||
| 653 | .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL, | ||
| 654 | }, | ||
| 655 | }, | ||
| 656 | .dev_attr = &dma_dev_attr, | ||
| 657 | .slaves = omap44xx_dma_system_slaves, | ||
| 658 | .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves), | ||
| 659 | .masters = omap44xx_dma_system_masters, | ||
| 660 | .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters), | ||
| 661 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 662 | }; | ||
| 663 | |||
| 664 | /* | ||
| 665 | * 'dsp' class | ||
| 666 | * dsp sub-system | ||
| 667 | */ | ||
| 668 | |||
| 669 | static struct omap_hwmod_class omap44xx_dsp_hwmod_class = { | ||
| 670 | .name = "dsp", | ||
| 671 | }; | ||
| 672 | |||
| 673 | /* dsp */ | ||
| 674 | static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = { | ||
| 675 | { .irq = 28 + OMAP44XX_IRQ_GIC_START }, | ||
| 676 | }; | ||
| 677 | |||
| 678 | static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { | ||
| 679 | { .name = "mmu_cache", .rst_shift = 1 }, | ||
| 680 | }; | ||
| 681 | |||
| 682 | static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = { | ||
| 683 | { .name = "dsp", .rst_shift = 0 }, | ||
| 684 | }; | ||
| 685 | |||
| 686 | /* dsp -> iva */ | ||
| 687 | static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { | ||
| 688 | .master = &omap44xx_dsp_hwmod, | ||
| 689 | .slave = &omap44xx_iva_hwmod, | ||
| 690 | .clk = "dpll_iva_m5x2_ck", | ||
| 691 | }; | ||
| 692 | |||
| 693 | /* dsp master ports */ | ||
| 694 | static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = { | ||
| 695 | &omap44xx_dsp__l3_main_1, | ||
| 696 | &omap44xx_dsp__l4_abe, | ||
| 697 | &omap44xx_dsp__iva, | ||
| 698 | }; | ||
| 699 | |||
| 700 | /* l4_cfg -> dsp */ | ||
| 701 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { | ||
| 702 | .master = &omap44xx_l4_cfg_hwmod, | ||
| 703 | .slave = &omap44xx_dsp_hwmod, | ||
| 704 | .clk = "l4_div_ck", | ||
| 705 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 706 | }; | ||
| 707 | |||
| 708 | /* dsp slave ports */ | ||
| 709 | static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = { | ||
| 710 | &omap44xx_l4_cfg__dsp, | ||
| 711 | }; | ||
| 712 | |||
| 713 | /* Pseudo hwmod for reset control purpose only */ | ||
| 714 | static struct omap_hwmod omap44xx_dsp_c0_hwmod = { | ||
| 715 | .name = "dsp_c0", | ||
| 716 | .class = &omap44xx_dsp_hwmod_class, | ||
| 717 | .flags = HWMOD_INIT_NO_RESET, | ||
| 718 | .rst_lines = omap44xx_dsp_c0_resets, | ||
| 719 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets), | ||
| 720 | .prcm = { | ||
| 721 | .omap4 = { | ||
| 722 | .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL, | ||
| 723 | }, | ||
| 724 | }, | ||
| 725 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 726 | }; | ||
| 727 | |||
| 728 | static struct omap_hwmod omap44xx_dsp_hwmod = { | ||
| 729 | .name = "dsp", | ||
| 730 | .class = &omap44xx_dsp_hwmod_class, | ||
| 731 | .mpu_irqs = omap44xx_dsp_irqs, | ||
| 732 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dsp_irqs), | ||
| 733 | .rst_lines = omap44xx_dsp_resets, | ||
| 734 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), | ||
| 735 | .main_clk = "dsp_fck", | ||
| 736 | .prcm = { | ||
| 737 | .omap4 = { | ||
| 738 | .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, | ||
| 739 | .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL, | ||
| 740 | }, | ||
| 741 | }, | ||
| 742 | .slaves = omap44xx_dsp_slaves, | ||
| 743 | .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves), | ||
| 744 | .masters = omap44xx_dsp_masters, | ||
| 745 | .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters), | ||
| 746 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 747 | }; | ||
| 748 | |||
| 749 | /* | ||
| 750 | * 'gpio' class | ||
| 751 | * general purpose io module | ||
| 752 | */ | ||
| 753 | |||
| 754 | static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = { | ||
| 755 | .rev_offs = 0x0000, | ||
| 756 | .sysc_offs = 0x0010, | ||
| 757 | .syss_offs = 0x0114, | ||
| 758 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | ||
| 759 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | ||
| 760 | SYSS_HAS_RESET_STATUS), | ||
| 761 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | ||
| 762 | SIDLE_SMART_WKUP), | ||
| 763 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
| 764 | }; | ||
| 765 | |||
| 766 | static struct omap_hwmod_class omap44xx_gpio_hwmod_class = { | ||
| 767 | .name = "gpio", | ||
| 768 | .sysc = &omap44xx_gpio_sysc, | ||
| 769 | .rev = 2, | ||
| 770 | }; | ||
| 771 | |||
| 772 | /* gpio dev_attr */ | ||
| 773 | static struct omap_gpio_dev_attr gpio_dev_attr = { | ||
| 774 | .bank_width = 32, | ||
| 775 | .dbck_flag = true, | ||
| 776 | }; | ||
| 777 | |||
| 778 | /* gpio1 */ | ||
| 779 | static struct omap_hwmod omap44xx_gpio1_hwmod; | ||
| 780 | static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { | ||
| 781 | { .irq = 29 + OMAP44XX_IRQ_GIC_START }, | ||
| 782 | }; | ||
| 783 | |||
| 784 | static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { | ||
| 785 | { | ||
| 786 | .pa_start = 0x4a310000, | ||
| 787 | .pa_end = 0x4a3101ff, | ||
| 788 | .flags = ADDR_TYPE_RT | ||
| 789 | }, | ||
| 790 | }; | ||
| 791 | |||
| 792 | /* l4_wkup -> gpio1 */ | ||
| 793 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { | ||
| 794 | .master = &omap44xx_l4_wkup_hwmod, | ||
| 795 | .slave = &omap44xx_gpio1_hwmod, | ||
| 796 | .clk = "l4_wkup_clk_mux_ck", | ||
| 797 | .addr = omap44xx_gpio1_addrs, | ||
| 798 | .addr_cnt = ARRAY_SIZE(omap44xx_gpio1_addrs), | ||
| 799 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 800 | }; | ||
| 801 | |||
| 802 | /* gpio1 slave ports */ | ||
| 803 | static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = { | ||
| 804 | &omap44xx_l4_wkup__gpio1, | ||
| 805 | }; | ||
| 806 | |||
| 807 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { | ||
| 808 | { .role = "dbclk", .clk = "gpio1_dbclk" }, | ||
| 809 | }; | ||
| 810 | |||
| 811 | static struct omap_hwmod omap44xx_gpio1_hwmod = { | ||
| 812 | .name = "gpio1", | ||
| 813 | .class = &omap44xx_gpio_hwmod_class, | ||
| 814 | .mpu_irqs = omap44xx_gpio1_irqs, | ||
| 815 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs), | ||
| 816 | .main_clk = "gpio1_ick", | ||
| 817 | .prcm = { | ||
| 818 | .omap4 = { | ||
| 819 | .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, | ||
| 820 | }, | ||
| 821 | }, | ||
| 822 | .opt_clks = gpio1_opt_clks, | ||
| 823 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | ||
| 824 | .dev_attr = &gpio_dev_attr, | ||
| 825 | .slaves = omap44xx_gpio1_slaves, | ||
| 826 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves), | ||
| 827 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 828 | }; | ||
| 829 | |||
| 830 | /* gpio2 */ | ||
| 831 | static struct omap_hwmod omap44xx_gpio2_hwmod; | ||
| 832 | static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { | ||
| 833 | { .irq = 30 + OMAP44XX_IRQ_GIC_START }, | ||
| 834 | }; | ||
| 835 | |||
| 836 | static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { | ||
| 837 | { | ||
| 838 | .pa_start = 0x48055000, | ||
| 839 | .pa_end = 0x480551ff, | ||
| 840 | .flags = ADDR_TYPE_RT | ||
| 841 | }, | ||
| 842 | }; | ||
| 843 | |||
| 844 | /* l4_per -> gpio2 */ | ||
| 845 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { | ||
| 846 | .master = &omap44xx_l4_per_hwmod, | ||
| 847 | .slave = &omap44xx_gpio2_hwmod, | ||
| 848 | .clk = "l4_div_ck", | ||
| 849 | .addr = omap44xx_gpio2_addrs, | ||
| 850 | .addr_cnt = ARRAY_SIZE(omap44xx_gpio2_addrs), | ||
| 851 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 852 | }; | ||
| 853 | |||
| 854 | /* gpio2 slave ports */ | ||
| 855 | static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = { | ||
| 856 | &omap44xx_l4_per__gpio2, | ||
| 857 | }; | ||
| 858 | |||
| 859 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { | ||
| 860 | { .role = "dbclk", .clk = "gpio2_dbclk" }, | ||
| 861 | }; | ||
| 862 | |||
| 863 | static struct omap_hwmod omap44xx_gpio2_hwmod = { | ||
| 864 | .name = "gpio2", | ||
| 865 | .class = &omap44xx_gpio_hwmod_class, | ||
| 866 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | ||
| 867 | .mpu_irqs = omap44xx_gpio2_irqs, | ||
| 868 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs), | ||
| 869 | .main_clk = "gpio2_ick", | ||
| 870 | .prcm = { | ||
| 871 | .omap4 = { | ||
| 872 | .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, | ||
| 873 | }, | ||
| 874 | }, | ||
| 875 | .opt_clks = gpio2_opt_clks, | ||
| 876 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | ||
| 877 | .dev_attr = &gpio_dev_attr, | ||
| 878 | .slaves = omap44xx_gpio2_slaves, | ||
| 879 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves), | ||
| 880 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 881 | }; | ||
| 882 | |||
| 883 | /* gpio3 */ | ||
| 884 | static struct omap_hwmod omap44xx_gpio3_hwmod; | ||
| 885 | static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { | ||
| 886 | { .irq = 31 + OMAP44XX_IRQ_GIC_START }, | ||
| 887 | }; | ||
| 888 | |||
| 889 | static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { | ||
| 890 | { | ||
| 891 | .pa_start = 0x48057000, | ||
| 892 | .pa_end = 0x480571ff, | ||
| 893 | .flags = ADDR_TYPE_RT | ||
| 894 | }, | ||
| 895 | }; | ||
| 896 | |||
| 897 | /* l4_per -> gpio3 */ | ||
| 898 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { | ||
| 899 | .master = &omap44xx_l4_per_hwmod, | ||
| 900 | .slave = &omap44xx_gpio3_hwmod, | ||
| 901 | .clk = "l4_div_ck", | ||
| 902 | .addr = omap44xx_gpio3_addrs, | ||
| 903 | .addr_cnt = ARRAY_SIZE(omap44xx_gpio3_addrs), | ||
| 904 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 905 | }; | ||
| 906 | |||
| 907 | /* gpio3 slave ports */ | ||
| 908 | static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = { | ||
| 909 | &omap44xx_l4_per__gpio3, | ||
| 910 | }; | ||
| 911 | |||
| 912 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { | ||
| 913 | { .role = "dbclk", .clk = "gpio3_dbclk" }, | ||
| 914 | }; | ||
| 915 | |||
| 916 | static struct omap_hwmod omap44xx_gpio3_hwmod = { | ||
| 917 | .name = "gpio3", | ||
| 918 | .class = &omap44xx_gpio_hwmod_class, | ||
| 919 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | ||
| 920 | .mpu_irqs = omap44xx_gpio3_irqs, | ||
| 921 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs), | ||
| 922 | .main_clk = "gpio3_ick", | ||
| 923 | .prcm = { | ||
| 924 | .omap4 = { | ||
| 925 | .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, | ||
| 926 | }, | ||
| 927 | }, | ||
| 928 | .opt_clks = gpio3_opt_clks, | ||
| 929 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | ||
| 930 | .dev_attr = &gpio_dev_attr, | ||
| 931 | .slaves = omap44xx_gpio3_slaves, | ||
| 932 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves), | ||
| 933 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 934 | }; | ||
| 935 | |||
| 936 | /* gpio4 */ | ||
| 937 | static struct omap_hwmod omap44xx_gpio4_hwmod; | ||
| 938 | static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { | ||
| 939 | { .irq = 32 + OMAP44XX_IRQ_GIC_START }, | ||
| 940 | }; | ||
| 941 | |||
| 942 | static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { | ||
| 943 | { | ||
| 944 | .pa_start = 0x48059000, | ||
| 945 | .pa_end = 0x480591ff, | ||
| 946 | .flags = ADDR_TYPE_RT | ||
| 947 | }, | ||
| 948 | }; | ||
| 949 | |||
| 950 | /* l4_per -> gpio4 */ | ||
| 951 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { | ||
| 952 | .master = &omap44xx_l4_per_hwmod, | ||
| 953 | .slave = &omap44xx_gpio4_hwmod, | ||
| 954 | .clk = "l4_div_ck", | ||
| 955 | .addr = omap44xx_gpio4_addrs, | ||
| 956 | .addr_cnt = ARRAY_SIZE(omap44xx_gpio4_addrs), | ||
| 957 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 958 | }; | ||
| 959 | |||
| 960 | /* gpio4 slave ports */ | ||
| 961 | static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = { | ||
| 962 | &omap44xx_l4_per__gpio4, | ||
| 963 | }; | ||
| 964 | |||
| 965 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { | ||
| 966 | { .role = "dbclk", .clk = "gpio4_dbclk" }, | ||
| 967 | }; | ||
| 968 | |||
| 969 | static struct omap_hwmod omap44xx_gpio4_hwmod = { | ||
| 970 | .name = "gpio4", | ||
| 971 | .class = &omap44xx_gpio_hwmod_class, | ||
| 972 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | ||
| 973 | .mpu_irqs = omap44xx_gpio4_irqs, | ||
| 974 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs), | ||
| 975 | .main_clk = "gpio4_ick", | ||
| 976 | .prcm = { | ||
| 977 | .omap4 = { | ||
| 978 | .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, | ||
| 979 | }, | ||
| 980 | }, | ||
| 981 | .opt_clks = gpio4_opt_clks, | ||
| 982 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | ||
| 983 | .dev_attr = &gpio_dev_attr, | ||
| 984 | .slaves = omap44xx_gpio4_slaves, | ||
| 985 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves), | ||
| 986 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 987 | }; | ||
| 988 | |||
| 989 | /* gpio5 */ | ||
| 990 | static struct omap_hwmod omap44xx_gpio5_hwmod; | ||
| 991 | static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { | ||
| 992 | { .irq = 33 + OMAP44XX_IRQ_GIC_START }, | ||
| 993 | }; | ||
| 994 | |||
| 995 | static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { | ||
| 996 | { | ||
| 997 | .pa_start = 0x4805b000, | ||
| 998 | .pa_end = 0x4805b1ff, | ||
| 999 | .flags = ADDR_TYPE_RT | ||
| 1000 | }, | ||
| 1001 | }; | ||
| 1002 | |||
| 1003 | /* l4_per -> gpio5 */ | ||
| 1004 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { | ||
| 1005 | .master = &omap44xx_l4_per_hwmod, | ||
| 1006 | .slave = &omap44xx_gpio5_hwmod, | ||
| 1007 | .clk = "l4_div_ck", | ||
| 1008 | .addr = omap44xx_gpio5_addrs, | ||
| 1009 | .addr_cnt = ARRAY_SIZE(omap44xx_gpio5_addrs), | ||
| 1010 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 1011 | }; | ||
| 1012 | |||
| 1013 | /* gpio5 slave ports */ | ||
| 1014 | static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = { | ||
| 1015 | &omap44xx_l4_per__gpio5, | ||
| 1016 | }; | ||
| 1017 | |||
| 1018 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { | ||
| 1019 | { .role = "dbclk", .clk = "gpio5_dbclk" }, | ||
| 1020 | }; | ||
| 1021 | |||
| 1022 | static struct omap_hwmod omap44xx_gpio5_hwmod = { | ||
| 1023 | .name = "gpio5", | ||
| 1024 | .class = &omap44xx_gpio_hwmod_class, | ||
| 1025 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | ||
| 1026 | .mpu_irqs = omap44xx_gpio5_irqs, | ||
| 1027 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs), | ||
| 1028 | .main_clk = "gpio5_ick", | ||
| 1029 | .prcm = { | ||
| 1030 | .omap4 = { | ||
| 1031 | .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, | ||
| 1032 | }, | ||
| 1033 | }, | ||
| 1034 | .opt_clks = gpio5_opt_clks, | ||
| 1035 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | ||
| 1036 | .dev_attr = &gpio_dev_attr, | ||
| 1037 | .slaves = omap44xx_gpio5_slaves, | ||
| 1038 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves), | ||
| 1039 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 1040 | }; | ||
| 1041 | |||
| 1042 | /* gpio6 */ | ||
| 1043 | static struct omap_hwmod omap44xx_gpio6_hwmod; | ||
| 1044 | static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { | ||
| 1045 | { .irq = 34 + OMAP44XX_IRQ_GIC_START }, | ||
| 1046 | }; | ||
| 1047 | |||
| 1048 | static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { | ||
| 1049 | { | ||
| 1050 | .pa_start = 0x4805d000, | ||
| 1051 | .pa_end = 0x4805d1ff, | ||
| 1052 | .flags = ADDR_TYPE_RT | ||
| 1053 | }, | ||
| 1054 | }; | ||
| 1055 | |||
| 1056 | /* l4_per -> gpio6 */ | ||
| 1057 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { | ||
| 1058 | .master = &omap44xx_l4_per_hwmod, | ||
| 1059 | .slave = &omap44xx_gpio6_hwmod, | ||
| 1060 | .clk = "l4_div_ck", | ||
| 1061 | .addr = omap44xx_gpio6_addrs, | ||
| 1062 | .addr_cnt = ARRAY_SIZE(omap44xx_gpio6_addrs), | ||
| 1063 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 1064 | }; | ||
| 1065 | |||
| 1066 | /* gpio6 slave ports */ | ||
| 1067 | static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = { | ||
| 1068 | &omap44xx_l4_per__gpio6, | ||
| 1069 | }; | ||
| 1070 | |||
| 1071 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { | ||
| 1072 | { .role = "dbclk", .clk = "gpio6_dbclk" }, | ||
| 1073 | }; | ||
| 1074 | |||
| 1075 | static struct omap_hwmod omap44xx_gpio6_hwmod = { | ||
| 1076 | .name = "gpio6", | ||
| 1077 | .class = &omap44xx_gpio_hwmod_class, | ||
| 1078 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | ||
| 1079 | .mpu_irqs = omap44xx_gpio6_irqs, | ||
| 1080 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs), | ||
| 1081 | .main_clk = "gpio6_ick", | ||
| 1082 | .prcm = { | ||
| 1083 | .omap4 = { | ||
| 1084 | .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, | ||
| 1085 | }, | ||
| 1086 | }, | ||
| 1087 | .opt_clks = gpio6_opt_clks, | ||
| 1088 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | ||
| 1089 | .dev_attr = &gpio_dev_attr, | ||
| 1090 | .slaves = omap44xx_gpio6_slaves, | ||
| 1091 | .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves), | ||
| 1092 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 1093 | }; | ||
| 1094 | |||
| 1095 | /* | ||
| 1096 | * 'i2c' class | ||
| 1097 | * multimaster high-speed i2c controller | ||
| 1098 | */ | ||
| 1099 | |||
| 1100 | static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = { | ||
| 1101 | .sysc_offs = 0x0010, | ||
| 1102 | .syss_offs = 0x0090, | ||
| 1103 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | ||
| 1104 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | ||
| 1105 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | ||
| 1106 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | ||
| 1107 | SIDLE_SMART_WKUP), | ||
| 1108 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
| 1109 | }; | ||
| 1110 | |||
| 1111 | static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { | ||
| 1112 | .name = "i2c", | ||
| 1113 | .sysc = &omap44xx_i2c_sysc, | ||
| 1114 | }; | ||
| 1115 | |||
| 1116 | /* i2c1 */ | ||
| 1117 | static struct omap_hwmod omap44xx_i2c1_hwmod; | ||
| 1118 | static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { | ||
| 1119 | { .irq = 56 + OMAP44XX_IRQ_GIC_START }, | ||
| 1120 | }; | ||
| 1121 | |||
| 1122 | static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { | ||
| 1123 | { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START }, | ||
| 1124 | { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START }, | ||
| 1125 | }; | ||
| 1126 | |||
| 1127 | static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { | ||
| 1128 | { | ||
| 1129 | .pa_start = 0x48070000, | ||
| 1130 | .pa_end = 0x480700ff, | ||
| 1131 | .flags = ADDR_TYPE_RT | ||
| 1132 | }, | ||
| 1133 | }; | ||
| 1134 | |||
| 1135 | /* l4_per -> i2c1 */ | ||
| 1136 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { | ||
| 1137 | .master = &omap44xx_l4_per_hwmod, | ||
| 1138 | .slave = &omap44xx_i2c1_hwmod, | ||
| 1139 | .clk = "l4_div_ck", | ||
| 1140 | .addr = omap44xx_i2c1_addrs, | ||
| 1141 | .addr_cnt = ARRAY_SIZE(omap44xx_i2c1_addrs), | ||
| 1142 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 1143 | }; | ||
| 1144 | |||
| 1145 | /* i2c1 slave ports */ | ||
| 1146 | static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = { | ||
| 1147 | &omap44xx_l4_per__i2c1, | ||
| 1148 | }; | ||
| 1149 | |||
| 1150 | static struct omap_hwmod omap44xx_i2c1_hwmod = { | ||
| 1151 | .name = "i2c1", | ||
| 1152 | .class = &omap44xx_i2c_hwmod_class, | ||
| 1153 | .flags = HWMOD_INIT_NO_RESET, | ||
| 1154 | .mpu_irqs = omap44xx_i2c1_irqs, | ||
| 1155 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs), | ||
| 1156 | .sdma_reqs = omap44xx_i2c1_sdma_reqs, | ||
| 1157 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs), | ||
| 1158 | .main_clk = "i2c1_fck", | ||
| 1159 | .prcm = { | ||
| 1160 | .omap4 = { | ||
| 1161 | .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, | ||
| 1162 | }, | ||
| 1163 | }, | ||
| 1164 | .slaves = omap44xx_i2c1_slaves, | ||
| 1165 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves), | ||
| 1166 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 1167 | }; | ||
| 1168 | |||
| 1169 | /* i2c2 */ | ||
| 1170 | static struct omap_hwmod omap44xx_i2c2_hwmod; | ||
| 1171 | static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { | ||
| 1172 | { .irq = 57 + OMAP44XX_IRQ_GIC_START }, | ||
| 1173 | }; | ||
| 1174 | |||
| 1175 | static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { | ||
| 1176 | { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START }, | ||
| 1177 | { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START }, | ||
| 1178 | }; | ||
| 1179 | |||
| 1180 | static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { | ||
| 1181 | { | ||
| 1182 | .pa_start = 0x48072000, | ||
| 1183 | .pa_end = 0x480720ff, | ||
| 1184 | .flags = ADDR_TYPE_RT | ||
| 1185 | }, | ||
| 1186 | }; | ||
| 1187 | |||
| 1188 | /* l4_per -> i2c2 */ | ||
| 1189 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { | ||
| 1190 | .master = &omap44xx_l4_per_hwmod, | ||
| 1191 | .slave = &omap44xx_i2c2_hwmod, | ||
| 1192 | .clk = "l4_div_ck", | ||
| 1193 | .addr = omap44xx_i2c2_addrs, | ||
| 1194 | .addr_cnt = ARRAY_SIZE(omap44xx_i2c2_addrs), | ||
| 1195 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 1196 | }; | ||
| 1197 | |||
| 1198 | /* i2c2 slave ports */ | ||
| 1199 | static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = { | ||
| 1200 | &omap44xx_l4_per__i2c2, | ||
| 1201 | }; | ||
| 1202 | |||
| 1203 | static struct omap_hwmod omap44xx_i2c2_hwmod = { | ||
| 1204 | .name = "i2c2", | ||
| 1205 | .class = &omap44xx_i2c_hwmod_class, | ||
| 1206 | .flags = HWMOD_INIT_NO_RESET, | ||
| 1207 | .mpu_irqs = omap44xx_i2c2_irqs, | ||
| 1208 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs), | ||
| 1209 | .sdma_reqs = omap44xx_i2c2_sdma_reqs, | ||
| 1210 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs), | ||
| 1211 | .main_clk = "i2c2_fck", | ||
| 1212 | .prcm = { | ||
| 1213 | .omap4 = { | ||
| 1214 | .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, | ||
| 1215 | }, | ||
| 1216 | }, | ||
| 1217 | .slaves = omap44xx_i2c2_slaves, | ||
| 1218 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves), | ||
| 1219 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 1220 | }; | ||
| 1221 | |||
| 1222 | /* i2c3 */ | ||
| 1223 | static struct omap_hwmod omap44xx_i2c3_hwmod; | ||
| 1224 | static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { | ||
| 1225 | { .irq = 61 + OMAP44XX_IRQ_GIC_START }, | ||
| 1226 | }; | ||
| 1227 | |||
| 1228 | static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { | ||
| 1229 | { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START }, | ||
| 1230 | { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START }, | ||
| 1231 | }; | ||
| 1232 | |||
| 1233 | static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { | ||
| 1234 | { | ||
| 1235 | .pa_start = 0x48060000, | ||
| 1236 | .pa_end = 0x480600ff, | ||
| 1237 | .flags = ADDR_TYPE_RT | ||
| 1238 | }, | ||
| 1239 | }; | ||
| 1240 | |||
| 1241 | /* l4_per -> i2c3 */ | ||
| 1242 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { | ||
| 1243 | .master = &omap44xx_l4_per_hwmod, | ||
| 1244 | .slave = &omap44xx_i2c3_hwmod, | ||
| 1245 | .clk = "l4_div_ck", | ||
| 1246 | .addr = omap44xx_i2c3_addrs, | ||
| 1247 | .addr_cnt = ARRAY_SIZE(omap44xx_i2c3_addrs), | ||
| 1248 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 1249 | }; | ||
| 1250 | |||
| 1251 | /* i2c3 slave ports */ | ||
| 1252 | static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = { | ||
| 1253 | &omap44xx_l4_per__i2c3, | ||
| 1254 | }; | ||
| 1255 | |||
| 1256 | static struct omap_hwmod omap44xx_i2c3_hwmod = { | ||
| 1257 | .name = "i2c3", | ||
| 1258 | .class = &omap44xx_i2c_hwmod_class, | ||
| 1259 | .flags = HWMOD_INIT_NO_RESET, | ||
| 1260 | .mpu_irqs = omap44xx_i2c3_irqs, | ||
| 1261 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs), | ||
| 1262 | .sdma_reqs = omap44xx_i2c3_sdma_reqs, | ||
| 1263 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs), | ||
| 1264 | .main_clk = "i2c3_fck", | ||
| 1265 | .prcm = { | ||
| 1266 | .omap4 = { | ||
| 1267 | .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, | ||
| 1268 | }, | ||
| 1269 | }, | ||
| 1270 | .slaves = omap44xx_i2c3_slaves, | ||
| 1271 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves), | ||
| 1272 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 1273 | }; | ||
| 1274 | |||
| 1275 | /* i2c4 */ | ||
| 1276 | static struct omap_hwmod omap44xx_i2c4_hwmod; | ||
| 1277 | static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { | ||
| 1278 | { .irq = 62 + OMAP44XX_IRQ_GIC_START }, | ||
| 1279 | }; | ||
| 1280 | |||
| 1281 | static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { | ||
| 1282 | { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START }, | ||
| 1283 | { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START }, | ||
| 1284 | }; | ||
| 1285 | |||
| 1286 | static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { | ||
| 1287 | { | ||
| 1288 | .pa_start = 0x48350000, | ||
| 1289 | .pa_end = 0x483500ff, | ||
| 1290 | .flags = ADDR_TYPE_RT | ||
| 1291 | }, | ||
| 1292 | }; | ||
| 1293 | |||
| 1294 | /* l4_per -> i2c4 */ | ||
| 1295 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { | ||
| 1296 | .master = &omap44xx_l4_per_hwmod, | ||
| 1297 | .slave = &omap44xx_i2c4_hwmod, | ||
| 1298 | .clk = "l4_div_ck", | ||
| 1299 | .addr = omap44xx_i2c4_addrs, | ||
| 1300 | .addr_cnt = ARRAY_SIZE(omap44xx_i2c4_addrs), | ||
| 1301 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 1302 | }; | ||
| 1303 | |||
| 1304 | /* i2c4 slave ports */ | ||
| 1305 | static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = { | ||
| 1306 | &omap44xx_l4_per__i2c4, | ||
| 1307 | }; | ||
| 1308 | |||
| 1309 | static struct omap_hwmod omap44xx_i2c4_hwmod = { | ||
| 1310 | .name = "i2c4", | ||
| 1311 | .class = &omap44xx_i2c_hwmod_class, | ||
| 1312 | .flags = HWMOD_INIT_NO_RESET, | ||
| 1313 | .mpu_irqs = omap44xx_i2c4_irqs, | ||
| 1314 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs), | ||
| 1315 | .sdma_reqs = omap44xx_i2c4_sdma_reqs, | ||
| 1316 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs), | ||
| 1317 | .main_clk = "i2c4_fck", | ||
| 1318 | .prcm = { | ||
| 1319 | .omap4 = { | ||
| 1320 | .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, | ||
| 1321 | }, | ||
| 1322 | }, | ||
| 1323 | .slaves = omap44xx_i2c4_slaves, | ||
| 1324 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves), | ||
| 1325 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 1326 | }; | ||
| 1327 | |||
| 1328 | /* | ||
| 1329 | * 'iva' class | ||
| 1330 | * multi-standard video encoder/decoder hardware accelerator | ||
| 1331 | */ | ||
| 1332 | |||
| 1333 | static struct omap_hwmod_class omap44xx_iva_hwmod_class = { | ||
| 1334 | .name = "iva", | ||
| 1335 | }; | ||
| 1336 | |||
| 1337 | /* iva */ | ||
| 1338 | static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = { | ||
| 1339 | { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START }, | ||
| 1340 | { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START }, | ||
| 1341 | { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START }, | ||
| 1342 | }; | ||
| 1343 | |||
| 1344 | static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { | ||
| 1345 | { .name = "logic", .rst_shift = 2 }, | ||
| 1346 | }; | ||
| 1347 | |||
| 1348 | static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = { | ||
| 1349 | { .name = "seq0", .rst_shift = 0 }, | ||
| 1350 | }; | ||
| 1351 | |||
| 1352 | static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = { | ||
| 1353 | { .name = "seq1", .rst_shift = 1 }, | ||
| 1354 | }; | ||
| 1355 | |||
| 1356 | /* iva master ports */ | ||
| 1357 | static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = { | ||
| 1358 | &omap44xx_iva__l3_main_2, | ||
| 1359 | &omap44xx_iva__l3_instr, | ||
| 1360 | }; | ||
| 1361 | |||
| 1362 | static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { | ||
| 1363 | { | ||
| 1364 | .pa_start = 0x5a000000, | ||
| 1365 | .pa_end = 0x5a07ffff, | ||
| 1366 | .flags = ADDR_TYPE_RT | ||
| 1367 | }, | ||
| 1368 | }; | ||
| 1369 | |||
| 1370 | /* l3_main_2 -> iva */ | ||
| 1371 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { | ||
| 1372 | .master = &omap44xx_l3_main_2_hwmod, | ||
| 1373 | .slave = &omap44xx_iva_hwmod, | ||
| 1374 | .clk = "l3_div_ck", | ||
| 1375 | .addr = omap44xx_iva_addrs, | ||
| 1376 | .addr_cnt = ARRAY_SIZE(omap44xx_iva_addrs), | ||
| 1377 | .user = OCP_USER_MPU, | ||
| 1378 | }; | ||
| 1379 | |||
| 1380 | /* iva slave ports */ | ||
| 1381 | static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = { | ||
| 1382 | &omap44xx_dsp__iva, | ||
| 1383 | &omap44xx_l3_main_2__iva, | ||
| 1384 | }; | ||
| 1385 | |||
| 1386 | /* Pseudo hwmod for reset control purpose only */ | ||
| 1387 | static struct omap_hwmod omap44xx_iva_seq0_hwmod = { | ||
| 1388 | .name = "iva_seq0", | ||
| 1389 | .class = &omap44xx_iva_hwmod_class, | ||
| 1390 | .flags = HWMOD_INIT_NO_RESET, | ||
| 1391 | .rst_lines = omap44xx_iva_seq0_resets, | ||
| 1392 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets), | ||
| 1393 | .prcm = { | ||
| 1394 | .omap4 = { | ||
| 1395 | .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL, | ||
| 1396 | }, | ||
| 1397 | }, | ||
| 1398 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 1399 | }; | ||
| 1400 | |||
| 1401 | /* Pseudo hwmod for reset control purpose only */ | ||
| 1402 | static struct omap_hwmod omap44xx_iva_seq1_hwmod = { | ||
| 1403 | .name = "iva_seq1", | ||
| 1404 | .class = &omap44xx_iva_hwmod_class, | ||
| 1405 | .flags = HWMOD_INIT_NO_RESET, | ||
| 1406 | .rst_lines = omap44xx_iva_seq1_resets, | ||
| 1407 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets), | ||
| 1408 | .prcm = { | ||
| 1409 | .omap4 = { | ||
| 1410 | .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL, | ||
| 1411 | }, | ||
| 1412 | }, | ||
| 1413 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 1414 | }; | ||
| 1415 | |||
| 1416 | static struct omap_hwmod omap44xx_iva_hwmod = { | ||
| 1417 | .name = "iva", | ||
| 1418 | .class = &omap44xx_iva_hwmod_class, | ||
| 1419 | .mpu_irqs = omap44xx_iva_irqs, | ||
| 1420 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iva_irqs), | ||
| 1421 | .rst_lines = omap44xx_iva_resets, | ||
| 1422 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), | ||
| 1423 | .main_clk = "iva_fck", | ||
| 1424 | .prcm = { | ||
| 1425 | .omap4 = { | ||
| 1426 | .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, | ||
| 1427 | .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL, | ||
| 1428 | }, | ||
| 1429 | }, | ||
| 1430 | .slaves = omap44xx_iva_slaves, | ||
| 1431 | .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves), | ||
| 1432 | .masters = omap44xx_iva_masters, | ||
| 1433 | .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters), | ||
| 1434 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 1435 | }; | ||
| 1436 | |||
| 1437 | /* | ||
| 416 | * 'mpu' class | 1438 | * 'mpu' class |
| 417 | * mpu sub-system | 1439 | * mpu sub-system |
| 418 | */ | 1440 | */ |
| 419 | 1441 | ||
| 420 | static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { | 1442 | static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { |
| 421 | .name = "mpu", | 1443 | .name = "mpu", |
| 422 | }; | 1444 | }; |
| 423 | 1445 | ||
| 424 | /* mpu */ | 1446 | /* mpu */ |
| @@ -453,58 +1475,189 @@ static struct omap_hwmod omap44xx_mpu_hwmod = { | |||
| 453 | }; | 1475 | }; |
| 454 | 1476 | ||
| 455 | /* | 1477 | /* |
| 456 | * 'wd_timer' class | 1478 | * 'smartreflex' class |
| 457 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | 1479 | * smartreflex module (monitor silicon performance and outputs a measure of |
| 458 | * overflow condition | 1480 | * performance error) |
| 459 | */ | 1481 | */ |
| 460 | 1482 | ||
| 461 | static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = { | 1483 | /* The IP is not compliant to type1 / type2 scheme */ |
| 462 | .rev_offs = 0x0000, | 1484 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = { |
| 463 | .sysc_offs = 0x0010, | 1485 | .sidle_shift = 24, |
| 464 | .syss_offs = 0x0014, | 1486 | .enwkup_shift = 26, |
| 465 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | | ||
| 466 | SYSC_HAS_SOFTRESET), | ||
| 467 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
| 468 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
| 469 | }; | 1487 | }; |
| 470 | 1488 | ||
| 471 | /* | 1489 | static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = { |
| 472 | * 'uart' class | 1490 | .sysc_offs = 0x0038, |
| 473 | * universal asynchronous receiver/transmitter (uart) | 1491 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), |
| 474 | */ | 1492 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 1493 | SIDLE_SMART_WKUP), | ||
| 1494 | .sysc_fields = &omap_hwmod_sysc_type_smartreflex, | ||
| 1495 | }; | ||
| 475 | 1496 | ||
| 476 | static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = { | 1497 | static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = { |
| 477 | .rev_offs = 0x0050, | 1498 | .name = "smartreflex", |
| 478 | .sysc_offs = 0x0054, | 1499 | .sysc = &omap44xx_smartreflex_sysc, |
| 479 | .syss_offs = 0x0058, | 1500 | .rev = 2, |
| 480 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | ||
| 481 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | ||
| 482 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
| 483 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
| 484 | }; | 1501 | }; |
| 485 | 1502 | ||
| 486 | static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { | 1503 | /* smartreflex_core */ |
| 487 | .name = "wd_timer", | 1504 | static struct omap_hwmod omap44xx_smartreflex_core_hwmod; |
| 488 | .sysc = &omap44xx_wd_timer_sysc, | 1505 | static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { |
| 1506 | { .irq = 19 + OMAP44XX_IRQ_GIC_START }, | ||
| 489 | }; | 1507 | }; |
| 490 | 1508 | ||
| 491 | /* wd_timer2 */ | 1509 | static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { |
| 492 | static struct omap_hwmod omap44xx_wd_timer2_hwmod; | 1510 | { |
| 493 | static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { | 1511 | .pa_start = 0x4a0dd000, |
| 494 | { .irq = 80 + OMAP44XX_IRQ_GIC_START }, | 1512 | .pa_end = 0x4a0dd03f, |
| 1513 | .flags = ADDR_TYPE_RT | ||
| 1514 | }, | ||
| 495 | }; | 1515 | }; |
| 496 | 1516 | ||
| 497 | static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { | 1517 | /* l4_cfg -> smartreflex_core */ |
| 1518 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { | ||
| 1519 | .master = &omap44xx_l4_cfg_hwmod, | ||
| 1520 | .slave = &omap44xx_smartreflex_core_hwmod, | ||
| 1521 | .clk = "l4_div_ck", | ||
| 1522 | .addr = omap44xx_smartreflex_core_addrs, | ||
| 1523 | .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_addrs), | ||
| 1524 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 1525 | }; | ||
| 1526 | |||
| 1527 | /* smartreflex_core slave ports */ | ||
| 1528 | static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = { | ||
| 1529 | &omap44xx_l4_cfg__smartreflex_core, | ||
| 1530 | }; | ||
| 1531 | |||
| 1532 | static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { | ||
| 1533 | .name = "smartreflex_core", | ||
| 1534 | .class = &omap44xx_smartreflex_hwmod_class, | ||
| 1535 | .mpu_irqs = omap44xx_smartreflex_core_irqs, | ||
| 1536 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_irqs), | ||
| 1537 | .main_clk = "smartreflex_core_fck", | ||
| 1538 | .vdd_name = "core", | ||
| 1539 | .prcm = { | ||
| 1540 | .omap4 = { | ||
| 1541 | .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, | ||
| 1542 | }, | ||
| 1543 | }, | ||
| 1544 | .slaves = omap44xx_smartreflex_core_slaves, | ||
| 1545 | .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves), | ||
| 1546 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 1547 | }; | ||
| 1548 | |||
| 1549 | /* smartreflex_iva */ | ||
| 1550 | static struct omap_hwmod omap44xx_smartreflex_iva_hwmod; | ||
| 1551 | static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { | ||
| 1552 | { .irq = 102 + OMAP44XX_IRQ_GIC_START }, | ||
| 1553 | }; | ||
| 1554 | |||
| 1555 | static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { | ||
| 498 | { | 1556 | { |
| 499 | .pa_start = 0x4a314000, | 1557 | .pa_start = 0x4a0db000, |
| 500 | .pa_end = 0x4a31407f, | 1558 | .pa_end = 0x4a0db03f, |
| 501 | .flags = ADDR_TYPE_RT | 1559 | .flags = ADDR_TYPE_RT |
| 502 | }, | 1560 | }, |
| 503 | }; | 1561 | }; |
| 504 | 1562 | ||
| 1563 | /* l4_cfg -> smartreflex_iva */ | ||
| 1564 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { | ||
| 1565 | .master = &omap44xx_l4_cfg_hwmod, | ||
| 1566 | .slave = &omap44xx_smartreflex_iva_hwmod, | ||
| 1567 | .clk = "l4_div_ck", | ||
| 1568 | .addr = omap44xx_smartreflex_iva_addrs, | ||
| 1569 | .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs), | ||
| 1570 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 1571 | }; | ||
| 1572 | |||
| 1573 | /* smartreflex_iva slave ports */ | ||
| 1574 | static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = { | ||
| 1575 | &omap44xx_l4_cfg__smartreflex_iva, | ||
| 1576 | }; | ||
| 1577 | |||
| 1578 | static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { | ||
| 1579 | .name = "smartreflex_iva", | ||
| 1580 | .class = &omap44xx_smartreflex_hwmod_class, | ||
| 1581 | .mpu_irqs = omap44xx_smartreflex_iva_irqs, | ||
| 1582 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs), | ||
| 1583 | .main_clk = "smartreflex_iva_fck", | ||
| 1584 | .vdd_name = "iva", | ||
| 1585 | .prcm = { | ||
| 1586 | .omap4 = { | ||
| 1587 | .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, | ||
| 1588 | }, | ||
| 1589 | }, | ||
| 1590 | .slaves = omap44xx_smartreflex_iva_slaves, | ||
| 1591 | .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves), | ||
| 1592 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 1593 | }; | ||
| 1594 | |||
| 1595 | /* smartreflex_mpu */ | ||
| 1596 | static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod; | ||
| 1597 | static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { | ||
| 1598 | { .irq = 18 + OMAP44XX_IRQ_GIC_START }, | ||
| 1599 | }; | ||
| 1600 | |||
| 1601 | static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { | ||
| 1602 | { | ||
| 1603 | .pa_start = 0x4a0d9000, | ||
| 1604 | .pa_end = 0x4a0d903f, | ||
| 1605 | .flags = ADDR_TYPE_RT | ||
| 1606 | }, | ||
| 1607 | }; | ||
| 1608 | |||
| 1609 | /* l4_cfg -> smartreflex_mpu */ | ||
| 1610 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { | ||
| 1611 | .master = &omap44xx_l4_cfg_hwmod, | ||
| 1612 | .slave = &omap44xx_smartreflex_mpu_hwmod, | ||
| 1613 | .clk = "l4_div_ck", | ||
| 1614 | .addr = omap44xx_smartreflex_mpu_addrs, | ||
| 1615 | .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs), | ||
| 1616 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 1617 | }; | ||
| 1618 | |||
| 1619 | /* smartreflex_mpu slave ports */ | ||
| 1620 | static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = { | ||
| 1621 | &omap44xx_l4_cfg__smartreflex_mpu, | ||
| 1622 | }; | ||
| 1623 | |||
| 1624 | static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { | ||
| 1625 | .name = "smartreflex_mpu", | ||
| 1626 | .class = &omap44xx_smartreflex_hwmod_class, | ||
| 1627 | .mpu_irqs = omap44xx_smartreflex_mpu_irqs, | ||
| 1628 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs), | ||
| 1629 | .main_clk = "smartreflex_mpu_fck", | ||
| 1630 | .vdd_name = "mpu", | ||
| 1631 | .prcm = { | ||
| 1632 | .omap4 = { | ||
| 1633 | .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, | ||
| 1634 | }, | ||
| 1635 | }, | ||
| 1636 | .slaves = omap44xx_smartreflex_mpu_slaves, | ||
| 1637 | .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves), | ||
| 1638 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 1639 | }; | ||
| 1640 | |||
| 1641 | /* | ||
| 1642 | * 'uart' class | ||
| 1643 | * universal asynchronous receiver/transmitter (uart) | ||
| 1644 | */ | ||
| 1645 | |||
| 1646 | static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = { | ||
| 1647 | .rev_offs = 0x0050, | ||
| 1648 | .sysc_offs = 0x0054, | ||
| 1649 | .syss_offs = 0x0058, | ||
| 1650 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | | ||
| 1651 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | ||
| 1652 | SYSS_HAS_RESET_STATUS), | ||
| 1653 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | ||
| 1654 | SIDLE_SMART_WKUP), | ||
| 1655 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
| 1656 | }; | ||
| 1657 | |||
| 505 | static struct omap_hwmod_class omap44xx_uart_hwmod_class = { | 1658 | static struct omap_hwmod_class omap44xx_uart_hwmod_class = { |
| 506 | .name = "uart", | 1659 | .name = "uart", |
| 507 | .sysc = &omap44xx_uart_sysc, | 1660 | .sysc = &omap44xx_uart_sysc, |
| 508 | }; | 1661 | }; |
| 509 | 1662 | ||
| 510 | /* uart1 */ | 1663 | /* uart1 */ |
| @@ -578,51 +1731,6 @@ static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { | |||
| 578 | }, | 1731 | }, |
| 579 | }; | 1732 | }; |
| 580 | 1733 | ||
| 581 | /* l4_wkup -> wd_timer2 */ | ||
| 582 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { | ||
| 583 | .master = &omap44xx_l4_wkup_hwmod, | ||
| 584 | .slave = &omap44xx_wd_timer2_hwmod, | ||
| 585 | .clk = "l4_wkup_clk_mux_ck", | ||
| 586 | .addr = omap44xx_wd_timer2_addrs, | ||
| 587 | .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs), | ||
| 588 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 589 | }; | ||
| 590 | |||
| 591 | /* wd_timer2 slave ports */ | ||
| 592 | static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = { | ||
| 593 | &omap44xx_l4_wkup__wd_timer2, | ||
| 594 | }; | ||
| 595 | |||
| 596 | static struct omap_hwmod omap44xx_wd_timer2_hwmod = { | ||
| 597 | .name = "wd_timer2", | ||
| 598 | .class = &omap44xx_wd_timer_hwmod_class, | ||
| 599 | .mpu_irqs = omap44xx_wd_timer2_irqs, | ||
| 600 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs), | ||
| 601 | .main_clk = "wd_timer2_fck", | ||
| 602 | .prcm = { | ||
| 603 | .omap4 = { | ||
| 604 | .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, | ||
| 605 | }, | ||
| 606 | }, | ||
| 607 | .slaves = omap44xx_wd_timer2_slaves, | ||
| 608 | .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves), | ||
| 609 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 610 | }; | ||
| 611 | |||
| 612 | /* wd_timer3 */ | ||
| 613 | static struct omap_hwmod omap44xx_wd_timer3_hwmod; | ||
| 614 | static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { | ||
| 615 | { .irq = 36 + OMAP44XX_IRQ_GIC_START }, | ||
| 616 | }; | ||
| 617 | |||
| 618 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { | ||
| 619 | { | ||
| 620 | .pa_start = 0x40130000, | ||
| 621 | .pa_end = 0x4013007f, | ||
| 622 | .flags = ADDR_TYPE_RT | ||
| 623 | }, | ||
| 624 | }; | ||
| 625 | |||
| 626 | /* l4_per -> uart2 */ | 1734 | /* l4_per -> uart2 */ |
| 627 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { | 1735 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { |
| 628 | .master = &omap44xx_l4_per_hwmod, | 1736 | .master = &omap44xx_l4_per_hwmod, |
| @@ -675,25 +1783,6 @@ static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { | |||
| 675 | }, | 1783 | }, |
| 676 | }; | 1784 | }; |
| 677 | 1785 | ||
| 678 | /* l4_abe -> wd_timer3 */ | ||
| 679 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { | ||
| 680 | .master = &omap44xx_l4_abe_hwmod, | ||
| 681 | .slave = &omap44xx_wd_timer3_hwmod, | ||
| 682 | .clk = "ocp_abe_iclk", | ||
| 683 | .addr = omap44xx_wd_timer3_addrs, | ||
| 684 | .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs), | ||
| 685 | .user = OCP_USER_MPU, | ||
| 686 | }; | ||
| 687 | |||
| 688 | /* l4_abe -> wd_timer3 (dma) */ | ||
| 689 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { | ||
| 690 | { | ||
| 691 | .pa_start = 0x49030000, | ||
| 692 | .pa_end = 0x4903007f, | ||
| 693 | .flags = ADDR_TYPE_RT | ||
| 694 | }, | ||
| 695 | }; | ||
| 696 | |||
| 697 | /* l4_per -> uart3 */ | 1786 | /* l4_per -> uart3 */ |
| 698 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { | 1787 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { |
| 699 | .master = &omap44xx_l4_per_hwmod, | 1788 | .master = &omap44xx_l4_per_hwmod, |
| @@ -747,37 +1836,6 @@ static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { | |||
| 747 | }, | 1836 | }, |
| 748 | }; | 1837 | }; |
| 749 | 1838 | ||
| 750 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { | ||
| 751 | .master = &omap44xx_l4_abe_hwmod, | ||
| 752 | .slave = &omap44xx_wd_timer3_hwmod, | ||
| 753 | .clk = "ocp_abe_iclk", | ||
| 754 | .addr = omap44xx_wd_timer3_dma_addrs, | ||
| 755 | .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs), | ||
| 756 | .user = OCP_USER_SDMA, | ||
| 757 | }; | ||
| 758 | |||
| 759 | /* wd_timer3 slave ports */ | ||
| 760 | static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = { | ||
| 761 | &omap44xx_l4_abe__wd_timer3, | ||
| 762 | &omap44xx_l4_abe__wd_timer3_dma, | ||
| 763 | }; | ||
| 764 | |||
| 765 | static struct omap_hwmod omap44xx_wd_timer3_hwmod = { | ||
| 766 | .name = "wd_timer3", | ||
| 767 | .class = &omap44xx_wd_timer_hwmod_class, | ||
| 768 | .mpu_irqs = omap44xx_wd_timer3_irqs, | ||
| 769 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs), | ||
| 770 | .main_clk = "wd_timer3_fck", | ||
| 771 | .prcm = { | ||
| 772 | .omap4 = { | ||
| 773 | .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, | ||
| 774 | }, | ||
| 775 | }, | ||
| 776 | .slaves = omap44xx_wd_timer3_slaves, | ||
| 777 | .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves), | ||
| 778 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 779 | }; | ||
| 780 | |||
| 781 | /* l4_per -> uart4 */ | 1839 | /* l4_per -> uart4 */ |
| 782 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { | 1840 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { |
| 783 | .master = &omap44xx_l4_per_hwmod, | 1841 | .master = &omap44xx_l4_per_hwmod, |
| @@ -811,35 +1869,205 @@ static struct omap_hwmod omap44xx_uart4_hwmod = { | |||
| 811 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 1869 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 812 | }; | 1870 | }; |
| 813 | 1871 | ||
| 1872 | /* | ||
| 1873 | * 'wd_timer' class | ||
| 1874 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | ||
| 1875 | * overflow condition | ||
| 1876 | */ | ||
| 1877 | |||
| 1878 | static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = { | ||
| 1879 | .rev_offs = 0x0000, | ||
| 1880 | .sysc_offs = 0x0010, | ||
| 1881 | .syss_offs = 0x0014, | ||
| 1882 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | | ||
| 1883 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | ||
| 1884 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | ||
| 1885 | SIDLE_SMART_WKUP), | ||
| 1886 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
| 1887 | }; | ||
| 1888 | |||
| 1889 | static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { | ||
| 1890 | .name = "wd_timer", | ||
| 1891 | .sysc = &omap44xx_wd_timer_sysc, | ||
| 1892 | .pre_shutdown = &omap2_wd_timer_disable, | ||
| 1893 | }; | ||
| 1894 | |||
| 1895 | /* wd_timer2 */ | ||
| 1896 | static struct omap_hwmod omap44xx_wd_timer2_hwmod; | ||
| 1897 | static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { | ||
| 1898 | { .irq = 80 + OMAP44XX_IRQ_GIC_START }, | ||
| 1899 | }; | ||
| 1900 | |||
| 1901 | static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { | ||
| 1902 | { | ||
| 1903 | .pa_start = 0x4a314000, | ||
| 1904 | .pa_end = 0x4a31407f, | ||
| 1905 | .flags = ADDR_TYPE_RT | ||
| 1906 | }, | ||
| 1907 | }; | ||
| 1908 | |||
| 1909 | /* l4_wkup -> wd_timer2 */ | ||
| 1910 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { | ||
| 1911 | .master = &omap44xx_l4_wkup_hwmod, | ||
| 1912 | .slave = &omap44xx_wd_timer2_hwmod, | ||
| 1913 | .clk = "l4_wkup_clk_mux_ck", | ||
| 1914 | .addr = omap44xx_wd_timer2_addrs, | ||
| 1915 | .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs), | ||
| 1916 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 1917 | }; | ||
| 1918 | |||
| 1919 | /* wd_timer2 slave ports */ | ||
| 1920 | static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = { | ||
| 1921 | &omap44xx_l4_wkup__wd_timer2, | ||
| 1922 | }; | ||
| 1923 | |||
| 1924 | static struct omap_hwmod omap44xx_wd_timer2_hwmod = { | ||
| 1925 | .name = "wd_timer2", | ||
| 1926 | .class = &omap44xx_wd_timer_hwmod_class, | ||
| 1927 | .mpu_irqs = omap44xx_wd_timer2_irqs, | ||
| 1928 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs), | ||
| 1929 | .main_clk = "wd_timer2_fck", | ||
| 1930 | .prcm = { | ||
| 1931 | .omap4 = { | ||
| 1932 | .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, | ||
| 1933 | }, | ||
| 1934 | }, | ||
| 1935 | .slaves = omap44xx_wd_timer2_slaves, | ||
| 1936 | .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves), | ||
| 1937 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 1938 | }; | ||
| 1939 | |||
| 1940 | /* wd_timer3 */ | ||
| 1941 | static struct omap_hwmod omap44xx_wd_timer3_hwmod; | ||
| 1942 | static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { | ||
| 1943 | { .irq = 36 + OMAP44XX_IRQ_GIC_START }, | ||
| 1944 | }; | ||
| 1945 | |||
| 1946 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { | ||
| 1947 | { | ||
| 1948 | .pa_start = 0x40130000, | ||
| 1949 | .pa_end = 0x4013007f, | ||
| 1950 | .flags = ADDR_TYPE_RT | ||
| 1951 | }, | ||
| 1952 | }; | ||
| 1953 | |||
| 1954 | /* l4_abe -> wd_timer3 */ | ||
| 1955 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { | ||
| 1956 | .master = &omap44xx_l4_abe_hwmod, | ||
| 1957 | .slave = &omap44xx_wd_timer3_hwmod, | ||
| 1958 | .clk = "ocp_abe_iclk", | ||
| 1959 | .addr = omap44xx_wd_timer3_addrs, | ||
| 1960 | .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs), | ||
| 1961 | .user = OCP_USER_MPU, | ||
| 1962 | }; | ||
| 1963 | |||
| 1964 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { | ||
| 1965 | { | ||
| 1966 | .pa_start = 0x49030000, | ||
| 1967 | .pa_end = 0x4903007f, | ||
| 1968 | .flags = ADDR_TYPE_RT | ||
| 1969 | }, | ||
| 1970 | }; | ||
| 1971 | |||
| 1972 | /* l4_abe -> wd_timer3 (dma) */ | ||
| 1973 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { | ||
| 1974 | .master = &omap44xx_l4_abe_hwmod, | ||
| 1975 | .slave = &omap44xx_wd_timer3_hwmod, | ||
| 1976 | .clk = "ocp_abe_iclk", | ||
| 1977 | .addr = omap44xx_wd_timer3_dma_addrs, | ||
| 1978 | .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs), | ||
| 1979 | .user = OCP_USER_SDMA, | ||
| 1980 | }; | ||
| 1981 | |||
| 1982 | /* wd_timer3 slave ports */ | ||
| 1983 | static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = { | ||
| 1984 | &omap44xx_l4_abe__wd_timer3, | ||
| 1985 | &omap44xx_l4_abe__wd_timer3_dma, | ||
| 1986 | }; | ||
| 1987 | |||
| 1988 | static struct omap_hwmod omap44xx_wd_timer3_hwmod = { | ||
| 1989 | .name = "wd_timer3", | ||
| 1990 | .class = &omap44xx_wd_timer_hwmod_class, | ||
| 1991 | .mpu_irqs = omap44xx_wd_timer3_irqs, | ||
| 1992 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs), | ||
| 1993 | .main_clk = "wd_timer3_fck", | ||
| 1994 | .prcm = { | ||
| 1995 | .omap4 = { | ||
| 1996 | .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, | ||
| 1997 | }, | ||
| 1998 | }, | ||
| 1999 | .slaves = omap44xx_wd_timer3_slaves, | ||
| 2000 | .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves), | ||
| 2001 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
| 2002 | }; | ||
| 2003 | |||
| 814 | static __initdata struct omap_hwmod *omap44xx_hwmods[] = { | 2004 | static __initdata struct omap_hwmod *omap44xx_hwmods[] = { |
| 2005 | |||
| 815 | /* dmm class */ | 2006 | /* dmm class */ |
| 816 | &omap44xx_dmm_hwmod, | 2007 | &omap44xx_dmm_hwmod, |
| 2008 | |||
| 817 | /* emif_fw class */ | 2009 | /* emif_fw class */ |
| 818 | &omap44xx_emif_fw_hwmod, | 2010 | &omap44xx_emif_fw_hwmod, |
| 2011 | |||
| 819 | /* l3 class */ | 2012 | /* l3 class */ |
| 820 | &omap44xx_l3_instr_hwmod, | 2013 | &omap44xx_l3_instr_hwmod, |
| 821 | &omap44xx_l3_main_1_hwmod, | 2014 | &omap44xx_l3_main_1_hwmod, |
| 822 | &omap44xx_l3_main_2_hwmod, | 2015 | &omap44xx_l3_main_2_hwmod, |
| 823 | &omap44xx_l3_main_3_hwmod, | 2016 | &omap44xx_l3_main_3_hwmod, |
| 2017 | |||
| 824 | /* l4 class */ | 2018 | /* l4 class */ |
| 825 | &omap44xx_l4_abe_hwmod, | 2019 | &omap44xx_l4_abe_hwmod, |
| 826 | &omap44xx_l4_cfg_hwmod, | 2020 | &omap44xx_l4_cfg_hwmod, |
| 827 | &omap44xx_l4_per_hwmod, | 2021 | &omap44xx_l4_per_hwmod, |
| 828 | &omap44xx_l4_wkup_hwmod, | 2022 | &omap44xx_l4_wkup_hwmod, |
| 2023 | |||
| 829 | /* mpu_bus class */ | 2024 | /* mpu_bus class */ |
| 830 | &omap44xx_mpu_private_hwmod, | 2025 | &omap44xx_mpu_private_hwmod, |
| 831 | 2026 | ||
| 2027 | /* dma class */ | ||
| 2028 | &omap44xx_dma_system_hwmod, | ||
| 2029 | |||
| 2030 | /* dsp class */ | ||
| 2031 | &omap44xx_dsp_hwmod, | ||
| 2032 | &omap44xx_dsp_c0_hwmod, | ||
| 2033 | |||
| 2034 | /* gpio class */ | ||
| 2035 | &omap44xx_gpio1_hwmod, | ||
| 2036 | &omap44xx_gpio2_hwmod, | ||
| 2037 | &omap44xx_gpio3_hwmod, | ||
| 2038 | &omap44xx_gpio4_hwmod, | ||
| 2039 | &omap44xx_gpio5_hwmod, | ||
| 2040 | &omap44xx_gpio6_hwmod, | ||
| 2041 | |||
| 2042 | /* i2c class */ | ||
| 2043 | &omap44xx_i2c1_hwmod, | ||
| 2044 | &omap44xx_i2c2_hwmod, | ||
| 2045 | &omap44xx_i2c3_hwmod, | ||
| 2046 | &omap44xx_i2c4_hwmod, | ||
| 2047 | |||
| 2048 | /* iva class */ | ||
| 2049 | &omap44xx_iva_hwmod, | ||
| 2050 | &omap44xx_iva_seq0_hwmod, | ||
| 2051 | &omap44xx_iva_seq1_hwmod, | ||
| 2052 | |||
| 832 | /* mpu class */ | 2053 | /* mpu class */ |
| 833 | &omap44xx_mpu_hwmod, | 2054 | &omap44xx_mpu_hwmod, |
| 834 | /* wd_timer class */ | 2055 | |
| 835 | &omap44xx_wd_timer2_hwmod, | 2056 | /* smartreflex class */ |
| 836 | &omap44xx_wd_timer3_hwmod, | 2057 | &omap44xx_smartreflex_core_hwmod, |
| 2058 | &omap44xx_smartreflex_iva_hwmod, | ||
| 2059 | &omap44xx_smartreflex_mpu_hwmod, | ||
| 837 | 2060 | ||
| 838 | /* uart class */ | 2061 | /* uart class */ |
| 839 | &omap44xx_uart1_hwmod, | 2062 | &omap44xx_uart1_hwmod, |
| 840 | &omap44xx_uart2_hwmod, | 2063 | &omap44xx_uart2_hwmod, |
| 841 | &omap44xx_uart3_hwmod, | 2064 | &omap44xx_uart3_hwmod, |
| 842 | &omap44xx_uart4_hwmod, | 2065 | &omap44xx_uart4_hwmod, |
| 2066 | |||
| 2067 | /* wd_timer class */ | ||
| 2068 | &omap44xx_wd_timer2_hwmod, | ||
| 2069 | &omap44xx_wd_timer3_hwmod, | ||
| 2070 | |||
| 843 | NULL, | 2071 | NULL, |
| 844 | }; | 2072 | }; |
| 845 | 2073 | ||
diff --git a/arch/arm/mach-omap2/omap_opp_data.h b/arch/arm/mach-omap2/omap_opp_data.h new file mode 100644 index 000000000000..46ac27dd6c84 --- /dev/null +++ b/arch/arm/mach-omap2/omap_opp_data.h | |||
| @@ -0,0 +1,72 @@ | |||
| 1 | /* | ||
| 2 | * OMAP SoC specific OPP Data helpers | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 5 | * Nishanth Menon | ||
| 6 | * Kevin Hilman | ||
| 7 | * Copyright (C) 2010 Nokia Corporation. | ||
| 8 | * Eduardo Valentin | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | * | ||
| 14 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
| 15 | * kind, whether express or implied; without even the implied warranty | ||
| 16 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 17 | * GNU General Public License for more details. | ||
| 18 | */ | ||
| 19 | #ifndef __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H | ||
| 20 | #define __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H | ||
| 21 | |||
| 22 | #include <plat/omap_hwmod.h> | ||
| 23 | |||
| 24 | /* | ||
| 25 | * *BIG FAT WARNING*: | ||
| 26 | * USE the following ONLY in opp data initialization common to an SoC. | ||
| 27 | * DO NOT USE these in board files/pm core etc. | ||
| 28 | */ | ||
| 29 | |||
| 30 | /** | ||
| 31 | * struct omap_opp_def - OMAP OPP Definition | ||
| 32 | * @hwmod_name: Name of the hwmod for this domain | ||
| 33 | * @freq: Frequency in hertz corresponding to this OPP | ||
| 34 | * @u_volt: Nominal voltage in microvolts corresponding to this OPP | ||
| 35 | * @default_available: True/false - is this OPP available by default | ||
| 36 | * | ||
| 37 | * OMAP SOCs have a standard set of tuples consisting of frequency and voltage | ||
| 38 | * pairs that the device will support per voltage domain. This is called | ||
| 39 | * Operating Points or OPP. The actual definitions of OMAP Operating Points | ||
| 40 | * varies over silicon within the same family of devices. For a specific | ||
| 41 | * domain, you can have a set of {frequency, voltage} pairs and this is denoted | ||
| 42 | * by an array of omap_opp_def. As the kernel boots and more information is | ||
| 43 | * available, a set of these are activated based on the precise nature of | ||
| 44 | * device the kernel boots up on. It is interesting to remember that each IP | ||
| 45 | * which belongs to a voltage domain may define their own set of OPPs on top | ||
| 46 | * of this - but this is handled by the appropriate driver. | ||
| 47 | */ | ||
| 48 | struct omap_opp_def { | ||
| 49 | char *hwmod_name; | ||
| 50 | |||
| 51 | unsigned long freq; | ||
| 52 | unsigned long u_volt; | ||
| 53 | |||
| 54 | bool default_available; | ||
| 55 | }; | ||
| 56 | |||
| 57 | /* | ||
| 58 | * Initialization wrapper used to define an OPP for OMAP variants. | ||
| 59 | */ | ||
| 60 | #define OPP_INITIALIZER(_hwmod_name, _enabled, _freq, _uv) \ | ||
| 61 | { \ | ||
| 62 | .hwmod_name = _hwmod_name, \ | ||
| 63 | .default_available = _enabled, \ | ||
| 64 | .freq = _freq, \ | ||
| 65 | .u_volt = _uv, \ | ||
| 66 | } | ||
| 67 | |||
| 68 | /* Use this to initialize the default table */ | ||
| 69 | extern int __init omap_init_opp_table(struct omap_opp_def *opp_def, | ||
| 70 | u32 opp_def_size); | ||
| 71 | |||
| 72 | #endif /* __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H */ | ||
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c new file mode 100644 index 000000000000..745252c60e32 --- /dev/null +++ b/arch/arm/mach-omap2/omap_phy_internal.c | |||
| @@ -0,0 +1,149 @@ | |||
| 1 | /* | ||
| 2 | * This file configures the internal USB PHY in OMAP4430. Used | ||
| 3 | * with TWL6030 transceiver and MUSB on OMAP4430. | ||
| 4 | * | ||
| 5 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * Author: Hema HK <hemahk@ti.com> | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License | ||
| 19 | * along with this program; if not, write to the Free Software | ||
| 20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 21 | * | ||
| 22 | */ | ||
| 23 | |||
| 24 | #include <linux/types.h> | ||
| 25 | #include <linux/delay.h> | ||
| 26 | #include <linux/clk.h> | ||
| 27 | #include <linux/io.h> | ||
| 28 | #include <linux/err.h> | ||
| 29 | #include <linux/usb.h> | ||
| 30 | |||
| 31 | #include <plat/usb.h> | ||
| 32 | |||
| 33 | /* OMAP control module register for UTMI PHY */ | ||
| 34 | #define CONTROL_DEV_CONF 0x300 | ||
| 35 | #define PHY_PD 0x1 | ||
| 36 | |||
| 37 | #define USBOTGHS_CONTROL 0x33c | ||
| 38 | #define AVALID BIT(0) | ||
| 39 | #define BVALID BIT(1) | ||
| 40 | #define VBUSVALID BIT(2) | ||
| 41 | #define SESSEND BIT(3) | ||
| 42 | #define IDDIG BIT(4) | ||
| 43 | |||
| 44 | static struct clk *phyclk, *clk48m, *clk32k; | ||
| 45 | static void __iomem *ctrl_base; | ||
| 46 | |||
| 47 | int omap4430_phy_init(struct device *dev) | ||
| 48 | { | ||
| 49 | ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K); | ||
| 50 | if (!ctrl_base) { | ||
| 51 | dev_err(dev, "control module ioremap failed\n"); | ||
| 52 | return -ENOMEM; | ||
| 53 | } | ||
| 54 | /* Power down the phy */ | ||
| 55 | __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF); | ||
| 56 | phyclk = clk_get(dev, "ocp2scp_usb_phy_ick"); | ||
| 57 | |||
| 58 | if (IS_ERR(phyclk)) { | ||
| 59 | dev_err(dev, "cannot clk_get ocp2scp_usb_phy_ick\n"); | ||
| 60 | iounmap(ctrl_base); | ||
| 61 | return PTR_ERR(phyclk); | ||
| 62 | } | ||
| 63 | |||
| 64 | clk48m = clk_get(dev, "ocp2scp_usb_phy_phy_48m"); | ||
| 65 | if (IS_ERR(clk48m)) { | ||
| 66 | dev_err(dev, "cannot clk_get ocp2scp_usb_phy_phy_48m\n"); | ||
| 67 | clk_put(phyclk); | ||
| 68 | iounmap(ctrl_base); | ||
| 69 | return PTR_ERR(clk48m); | ||
| 70 | } | ||
| 71 | |||
| 72 | clk32k = clk_get(dev, "usb_phy_cm_clk32k"); | ||
| 73 | if (IS_ERR(clk32k)) { | ||
| 74 | dev_err(dev, "cannot clk_get usb_phy_cm_clk32k\n"); | ||
| 75 | clk_put(phyclk); | ||
| 76 | clk_put(clk48m); | ||
| 77 | iounmap(ctrl_base); | ||
| 78 | return PTR_ERR(clk32k); | ||
| 79 | } | ||
| 80 | return 0; | ||
| 81 | } | ||
| 82 | |||
| 83 | int omap4430_phy_set_clk(struct device *dev, int on) | ||
| 84 | { | ||
| 85 | static int state; | ||
| 86 | |||
| 87 | if (on && !state) { | ||
| 88 | /* Enable the phy clocks */ | ||
| 89 | clk_enable(phyclk); | ||
| 90 | clk_enable(clk48m); | ||
| 91 | clk_enable(clk32k); | ||
| 92 | state = 1; | ||
| 93 | } else if (state) { | ||
| 94 | /* Disable the phy clocks */ | ||
| 95 | clk_disable(phyclk); | ||
| 96 | clk_disable(clk48m); | ||
| 97 | clk_disable(clk32k); | ||
| 98 | state = 0; | ||
| 99 | } | ||
| 100 | return 0; | ||
| 101 | } | ||
| 102 | |||
| 103 | int omap4430_phy_power(struct device *dev, int ID, int on) | ||
| 104 | { | ||
| 105 | if (on) { | ||
| 106 | /* enabled the clocks */ | ||
| 107 | omap4430_phy_set_clk(dev, 1); | ||
| 108 | /* power on the phy */ | ||
| 109 | if (__raw_readl(ctrl_base + CONTROL_DEV_CONF) & PHY_PD) { | ||
| 110 | __raw_writel(~PHY_PD, ctrl_base + CONTROL_DEV_CONF); | ||
| 111 | mdelay(200); | ||
| 112 | } | ||
| 113 | if (ID) | ||
| 114 | /* enable VBUS valid, IDDIG groung */ | ||
| 115 | __raw_writel(AVALID | VBUSVALID, ctrl_base + | ||
| 116 | USBOTGHS_CONTROL); | ||
| 117 | else | ||
| 118 | /* | ||
| 119 | * Enable VBUS Valid, AValid and IDDIG | ||
| 120 | * high impedence | ||
| 121 | */ | ||
| 122 | __raw_writel(IDDIG | AVALID | VBUSVALID, | ||
| 123 | ctrl_base + USBOTGHS_CONTROL); | ||
| 124 | } else { | ||
| 125 | /* Enable session END and IDIG to high impedence. */ | ||
| 126 | __raw_writel(SESSEND | IDDIG, ctrl_base + | ||
| 127 | USBOTGHS_CONTROL); | ||
| 128 | /* Disable the clocks */ | ||
| 129 | omap4430_phy_set_clk(dev, 0); | ||
| 130 | /* Power down the phy */ | ||
| 131 | __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF); | ||
| 132 | } | ||
| 133 | |||
| 134 | return 0; | ||
| 135 | } | ||
| 136 | |||
| 137 | int omap4430_phy_exit(struct device *dev) | ||
| 138 | { | ||
| 139 | if (ctrl_base) | ||
| 140 | iounmap(ctrl_base); | ||
| 141 | if (phyclk) | ||
| 142 | clk_put(phyclk); | ||
| 143 | if (clk48m) | ||
| 144 | clk_put(clk48m); | ||
| 145 | if (clk32k) | ||
| 146 | clk_put(clk32k); | ||
| 147 | |||
| 148 | return 0; | ||
| 149 | } | ||
diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c new file mode 100644 index 000000000000..15f8c6c1bb0f --- /dev/null +++ b/arch/arm/mach-omap2/omap_twl.c | |||
| @@ -0,0 +1,277 @@ | |||
| 1 | /** | ||
| 2 | * OMAP and TWL PMIC specific intializations. | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Texas Instruments Incorporated. | ||
| 5 | * Thara Gopinath | ||
| 6 | * Copyright (C) 2009 Texas Instruments Incorporated. | ||
| 7 | * Nishanth Menon | ||
| 8 | * Copyright (C) 2009 Nokia Corporation | ||
| 9 | * Paul Walmsley | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include <linux/err.h> | ||
| 17 | #include <linux/io.h> | ||
| 18 | #include <linux/kernel.h> | ||
| 19 | #include <linux/i2c/twl.h> | ||
| 20 | |||
| 21 | #include <plat/voltage.h> | ||
| 22 | |||
| 23 | #define OMAP3_SRI2C_SLAVE_ADDR 0x12 | ||
| 24 | #define OMAP3_VDD_MPU_SR_CONTROL_REG 0x00 | ||
| 25 | #define OMAP3_VDD_CORE_SR_CONTROL_REG 0x01 | ||
| 26 | #define OMAP3_VP_CONFIG_ERROROFFSET 0x00 | ||
| 27 | #define OMAP3_VP_VSTEPMIN_VSTEPMIN 0x1 | ||
| 28 | #define OMAP3_VP_VSTEPMAX_VSTEPMAX 0x04 | ||
| 29 | #define OMAP3_VP_VLIMITTO_TIMEOUT_US 200 | ||
| 30 | |||
| 31 | #define OMAP3430_VP1_VLIMITTO_VDDMIN 0x14 | ||
| 32 | #define OMAP3430_VP1_VLIMITTO_VDDMAX 0x42 | ||
| 33 | #define OMAP3430_VP2_VLIMITTO_VDDMIN 0x18 | ||
| 34 | #define OMAP3430_VP2_VLIMITTO_VDDMAX 0x2c | ||
| 35 | |||
| 36 | #define OMAP3630_VP1_VLIMITTO_VDDMIN 0x18 | ||
| 37 | #define OMAP3630_VP1_VLIMITTO_VDDMAX 0x3c | ||
| 38 | #define OMAP3630_VP2_VLIMITTO_VDDMIN 0x18 | ||
| 39 | #define OMAP3630_VP2_VLIMITTO_VDDMAX 0x30 | ||
| 40 | |||
| 41 | #define OMAP4_SRI2C_SLAVE_ADDR 0x12 | ||
| 42 | #define OMAP4_VDD_MPU_SR_VOLT_REG 0x55 | ||
| 43 | #define OMAP4_VDD_IVA_SR_VOLT_REG 0x5B | ||
| 44 | #define OMAP4_VDD_CORE_SR_VOLT_REG 0x61 | ||
| 45 | |||
| 46 | #define OMAP4_VP_CONFIG_ERROROFFSET 0x00 | ||
| 47 | #define OMAP4_VP_VSTEPMIN_VSTEPMIN 0x01 | ||
| 48 | #define OMAP4_VP_VSTEPMAX_VSTEPMAX 0x04 | ||
| 49 | #define OMAP4_VP_VLIMITTO_TIMEOUT_US 200 | ||
| 50 | |||
| 51 | #define OMAP4_VP_MPU_VLIMITTO_VDDMIN 0xA | ||
| 52 | #define OMAP4_VP_MPU_VLIMITTO_VDDMAX 0x39 | ||
| 53 | #define OMAP4_VP_IVA_VLIMITTO_VDDMIN 0xA | ||
| 54 | #define OMAP4_VP_IVA_VLIMITTO_VDDMAX 0x2D | ||
| 55 | #define OMAP4_VP_CORE_VLIMITTO_VDDMIN 0xA | ||
| 56 | #define OMAP4_VP_CORE_VLIMITTO_VDDMAX 0x28 | ||
| 57 | |||
| 58 | static bool is_offset_valid; | ||
| 59 | static u8 smps_offset; | ||
| 60 | |||
| 61 | #define REG_SMPS_OFFSET 0xE0 | ||
| 62 | |||
| 63 | unsigned long twl4030_vsel_to_uv(const u8 vsel) | ||
| 64 | { | ||
| 65 | return (((vsel * 125) + 6000)) * 100; | ||
| 66 | } | ||
| 67 | |||
| 68 | u8 twl4030_uv_to_vsel(unsigned long uv) | ||
| 69 | { | ||
| 70 | return DIV_ROUND_UP(uv - 600000, 12500); | ||
| 71 | } | ||
| 72 | |||
| 73 | unsigned long twl6030_vsel_to_uv(const u8 vsel) | ||
| 74 | { | ||
| 75 | /* | ||
| 76 | * In TWL6030 depending on the value of SMPS_OFFSET | ||
| 77 | * efuse register the voltage range supported in | ||
| 78 | * standard mode can be either between 0.6V - 1.3V or | ||
| 79 | * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse | ||
| 80 | * is programmed to all 0's where as starting from | ||
| 81 | * TWL6030 ES1.1 the efuse is programmed to 1 | ||
| 82 | */ | ||
| 83 | if (!is_offset_valid) { | ||
| 84 | twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset, | ||
| 85 | REG_SMPS_OFFSET); | ||
| 86 | is_offset_valid = true; | ||
| 87 | } | ||
| 88 | |||
| 89 | /* | ||
| 90 | * There is no specific formula for voltage to vsel | ||
| 91 | * conversion above 1.3V. There are special hardcoded | ||
| 92 | * values for voltages above 1.3V. Currently we are | ||
| 93 | * hardcoding only for 1.35 V which is used for 1GH OPP for | ||
| 94 | * OMAP4430. | ||
| 95 | */ | ||
| 96 | if (vsel == 0x3A) | ||
| 97 | return 1350000; | ||
| 98 | |||
| 99 | if (smps_offset & 0x8) | ||
| 100 | return ((((vsel - 1) * 125) + 7000)) * 100; | ||
| 101 | else | ||
| 102 | return ((((vsel - 1) * 125) + 6000)) * 100; | ||
| 103 | } | ||
| 104 | |||
| 105 | u8 twl6030_uv_to_vsel(unsigned long uv) | ||
| 106 | { | ||
| 107 | /* | ||
| 108 | * In TWL6030 depending on the value of SMPS_OFFSET | ||
| 109 | * efuse register the voltage range supported in | ||
| 110 | * standard mode can be either between 0.6V - 1.3V or | ||
| 111 | * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse | ||
| 112 | * is programmed to all 0's where as starting from | ||
| 113 | * TWL6030 ES1.1 the efuse is programmed to 1 | ||
| 114 | */ | ||
| 115 | if (!is_offset_valid) { | ||
| 116 | twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset, | ||
| 117 | REG_SMPS_OFFSET); | ||
| 118 | is_offset_valid = true; | ||
| 119 | } | ||
| 120 | |||
| 121 | /* | ||
| 122 | * There is no specific formula for voltage to vsel | ||
| 123 | * conversion above 1.3V. There are special hardcoded | ||
| 124 | * values for voltages above 1.3V. Currently we are | ||
| 125 | * hardcoding only for 1.35 V which is used for 1GH OPP for | ||
| 126 | * OMAP4430. | ||
| 127 | */ | ||
| 128 | if (uv == 1350000) | ||
| 129 | return 0x3A; | ||
| 130 | |||
| 131 | if (smps_offset & 0x8) | ||
| 132 | return DIV_ROUND_UP(uv - 700000, 12500) + 1; | ||
| 133 | else | ||
| 134 | return DIV_ROUND_UP(uv - 600000, 12500) + 1; | ||
| 135 | } | ||
| 136 | |||
| 137 | static struct omap_volt_pmic_info omap3_mpu_volt_info = { | ||
| 138 | .slew_rate = 4000, | ||
| 139 | .step_size = 12500, | ||
| 140 | .on_volt = 1200000, | ||
| 141 | .onlp_volt = 1000000, | ||
| 142 | .ret_volt = 975000, | ||
| 143 | .off_volt = 600000, | ||
| 144 | .volt_setup_time = 0xfff, | ||
| 145 | .vp_erroroffset = OMAP3_VP_CONFIG_ERROROFFSET, | ||
| 146 | .vp_vstepmin = OMAP3_VP_VSTEPMIN_VSTEPMIN, | ||
| 147 | .vp_vstepmax = OMAP3_VP_VSTEPMAX_VSTEPMAX, | ||
| 148 | .vp_vddmin = OMAP3430_VP1_VLIMITTO_VDDMIN, | ||
| 149 | .vp_vddmax = OMAP3430_VP1_VLIMITTO_VDDMAX, | ||
| 150 | .vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US, | ||
| 151 | .i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR, | ||
| 152 | .pmic_reg = OMAP3_VDD_MPU_SR_CONTROL_REG, | ||
| 153 | .vsel_to_uv = twl4030_vsel_to_uv, | ||
| 154 | .uv_to_vsel = twl4030_uv_to_vsel, | ||
| 155 | }; | ||
| 156 | |||
| 157 | static struct omap_volt_pmic_info omap3_core_volt_info = { | ||
| 158 | .slew_rate = 4000, | ||
| 159 | .step_size = 12500, | ||
| 160 | .on_volt = 1200000, | ||
| 161 | .onlp_volt = 1000000, | ||
| 162 | .ret_volt = 975000, | ||
| 163 | .off_volt = 600000, | ||
| 164 | .volt_setup_time = 0xfff, | ||
| 165 | .vp_erroroffset = OMAP3_VP_CONFIG_ERROROFFSET, | ||
| 166 | .vp_vstepmin = OMAP3_VP_VSTEPMIN_VSTEPMIN, | ||
| 167 | .vp_vstepmax = OMAP3_VP_VSTEPMAX_VSTEPMAX, | ||
| 168 | .vp_vddmin = OMAP3430_VP2_VLIMITTO_VDDMIN, | ||
| 169 | .vp_vddmax = OMAP3430_VP2_VLIMITTO_VDDMAX, | ||
| 170 | .vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US, | ||
| 171 | .i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR, | ||
| 172 | .pmic_reg = OMAP3_VDD_CORE_SR_CONTROL_REG, | ||
| 173 | .vsel_to_uv = twl4030_vsel_to_uv, | ||
| 174 | .uv_to_vsel = twl4030_uv_to_vsel, | ||
| 175 | }; | ||
| 176 | |||
| 177 | static struct omap_volt_pmic_info omap4_mpu_volt_info = { | ||
| 178 | .slew_rate = 4000, | ||
| 179 | .step_size = 12500, | ||
| 180 | .on_volt = 1350000, | ||
| 181 | .onlp_volt = 1350000, | ||
| 182 | .ret_volt = 837500, | ||
| 183 | .off_volt = 600000, | ||
| 184 | .volt_setup_time = 0, | ||
| 185 | .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET, | ||
| 186 | .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN, | ||
| 187 | .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX, | ||
| 188 | .vp_vddmin = OMAP4_VP_MPU_VLIMITTO_VDDMIN, | ||
| 189 | .vp_vddmax = OMAP4_VP_MPU_VLIMITTO_VDDMAX, | ||
| 190 | .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US, | ||
| 191 | .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR, | ||
| 192 | .pmic_reg = OMAP4_VDD_MPU_SR_VOLT_REG, | ||
| 193 | .vsel_to_uv = twl6030_vsel_to_uv, | ||
| 194 | .uv_to_vsel = twl6030_uv_to_vsel, | ||
| 195 | }; | ||
| 196 | |||
| 197 | static struct omap_volt_pmic_info omap4_iva_volt_info = { | ||
| 198 | .slew_rate = 4000, | ||
| 199 | .step_size = 12500, | ||
| 200 | .on_volt = 1100000, | ||
| 201 | .onlp_volt = 1100000, | ||
| 202 | .ret_volt = 837500, | ||
| 203 | .off_volt = 600000, | ||
| 204 | .volt_setup_time = 0, | ||
| 205 | .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET, | ||
| 206 | .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN, | ||
| 207 | .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX, | ||
| 208 | .vp_vddmin = OMAP4_VP_IVA_VLIMITTO_VDDMIN, | ||
| 209 | .vp_vddmax = OMAP4_VP_IVA_VLIMITTO_VDDMAX, | ||
| 210 | .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US, | ||
| 211 | .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR, | ||
| 212 | .pmic_reg = OMAP4_VDD_IVA_SR_VOLT_REG, | ||
| 213 | .vsel_to_uv = twl6030_vsel_to_uv, | ||
| 214 | .uv_to_vsel = twl6030_uv_to_vsel, | ||
| 215 | }; | ||
| 216 | |||
| 217 | static struct omap_volt_pmic_info omap4_core_volt_info = { | ||
| 218 | .slew_rate = 4000, | ||
| 219 | .step_size = 12500, | ||
| 220 | .on_volt = 1100000, | ||
| 221 | .onlp_volt = 1100000, | ||
| 222 | .ret_volt = 837500, | ||
| 223 | .off_volt = 600000, | ||
| 224 | .volt_setup_time = 0, | ||
| 225 | .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET, | ||
| 226 | .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN, | ||
| 227 | .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX, | ||
| 228 | .vp_vddmin = OMAP4_VP_CORE_VLIMITTO_VDDMIN, | ||
| 229 | .vp_vddmax = OMAP4_VP_CORE_VLIMITTO_VDDMAX, | ||
| 230 | .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US, | ||
| 231 | .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR, | ||
| 232 | .pmic_reg = OMAP4_VDD_CORE_SR_VOLT_REG, | ||
| 233 | .vsel_to_uv = twl6030_vsel_to_uv, | ||
| 234 | .uv_to_vsel = twl6030_uv_to_vsel, | ||
| 235 | }; | ||
| 236 | |||
| 237 | int __init omap4_twl_init(void) | ||
| 238 | { | ||
| 239 | struct voltagedomain *voltdm; | ||
| 240 | |||
| 241 | if (!cpu_is_omap44xx()) | ||
| 242 | return -ENODEV; | ||
| 243 | |||
| 244 | voltdm = omap_voltage_domain_lookup("mpu"); | ||
| 245 | omap_voltage_register_pmic(voltdm, &omap4_mpu_volt_info); | ||
| 246 | |||
| 247 | voltdm = omap_voltage_domain_lookup("iva"); | ||
| 248 | omap_voltage_register_pmic(voltdm, &omap4_iva_volt_info); | ||
| 249 | |||
| 250 | voltdm = omap_voltage_domain_lookup("core"); | ||
| 251 | omap_voltage_register_pmic(voltdm, &omap4_core_volt_info); | ||
| 252 | |||
| 253 | return 0; | ||
| 254 | } | ||
| 255 | |||
| 256 | int __init omap3_twl_init(void) | ||
| 257 | { | ||
| 258 | struct voltagedomain *voltdm; | ||
| 259 | |||
| 260 | if (!cpu_is_omap34xx()) | ||
| 261 | return -ENODEV; | ||
| 262 | |||
| 263 | if (cpu_is_omap3630()) { | ||
| 264 | omap3_mpu_volt_info.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN; | ||
| 265 | omap3_mpu_volt_info.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX; | ||
| 266 | omap3_core_volt_info.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN; | ||
| 267 | omap3_core_volt_info.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX; | ||
| 268 | } | ||
| 269 | |||
| 270 | voltdm = omap_voltage_domain_lookup("mpu"); | ||
| 271 | omap_voltage_register_pmic(voltdm, &omap3_mpu_volt_info); | ||
| 272 | |||
| 273 | voltdm = omap_voltage_domain_lookup("core"); | ||
| 274 | omap_voltage_register_pmic(voltdm, &omap3_core_volt_info); | ||
| 275 | |||
| 276 | return 0; | ||
| 277 | } | ||
diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c new file mode 100644 index 000000000000..ab8b35b780b5 --- /dev/null +++ b/arch/arm/mach-omap2/opp.c | |||
| @@ -0,0 +1,93 @@ | |||
| 1 | /* | ||
| 2 | * OMAP SoC specific OPP wrapper function | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 5 | * Nishanth Menon | ||
| 6 | * Kevin Hilman | ||
| 7 | * Copyright (C) 2010 Nokia Corporation. | ||
| 8 | * Eduardo Valentin | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | * | ||
| 14 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
| 15 | * kind, whether express or implied; without even the implied warranty | ||
| 16 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 17 | * GNU General Public License for more details. | ||
| 18 | */ | ||
| 19 | #include <linux/module.h> | ||
| 20 | #include <linux/opp.h> | ||
| 21 | |||
| 22 | #include <plat/omap_device.h> | ||
| 23 | |||
| 24 | #include "omap_opp_data.h" | ||
| 25 | |||
| 26 | /* Temp variable to allow multiple calls */ | ||
| 27 | static u8 __initdata omap_table_init; | ||
| 28 | |||
| 29 | /** | ||
| 30 | * omap_init_opp_table() - Initialize opp table as per the CPU type | ||
| 31 | * @opp_def: opp default list for this silicon | ||
| 32 | * @opp_def_size: number of opp entries for this silicon | ||
| 33 | * | ||
| 34 | * Register the initial OPP table with the OPP library based on the CPU | ||
| 35 | * type. This is meant to be used only by SoC specific registration. | ||
| 36 | */ | ||
| 37 | int __init omap_init_opp_table(struct omap_opp_def *opp_def, | ||
| 38 | u32 opp_def_size) | ||
| 39 | { | ||
| 40 | int i, r; | ||
| 41 | |||
| 42 | if (!opp_def || !opp_def_size) { | ||
| 43 | pr_err("%s: invalid params!\n", __func__); | ||
| 44 | return -EINVAL; | ||
| 45 | } | ||
| 46 | |||
| 47 | /* | ||
| 48 | * Initialize only if not already initialized even if the previous | ||
| 49 | * call failed, because, no reason we'd succeed again. | ||
| 50 | */ | ||
| 51 | if (omap_table_init) | ||
| 52 | return -EEXIST; | ||
| 53 | omap_table_init = 1; | ||
| 54 | |||
| 55 | /* Lets now register with OPP library */ | ||
| 56 | for (i = 0; i < opp_def_size; i++) { | ||
| 57 | struct omap_hwmod *oh; | ||
| 58 | struct device *dev; | ||
| 59 | |||
| 60 | if (!opp_def->hwmod_name) { | ||
| 61 | pr_err("%s: NULL name of omap_hwmod, failing [%d].\n", | ||
| 62 | __func__, i); | ||
| 63 | return -EINVAL; | ||
| 64 | } | ||
| 65 | oh = omap_hwmod_lookup(opp_def->hwmod_name); | ||
| 66 | if (!oh || !oh->od) { | ||
| 67 | pr_warn("%s: no hwmod or odev for %s, [%d] " | ||
| 68 | "cannot add OPPs.\n", __func__, | ||
| 69 | opp_def->hwmod_name, i); | ||
| 70 | return -EINVAL; | ||
| 71 | } | ||
| 72 | dev = &oh->od->pdev.dev; | ||
| 73 | |||
| 74 | r = opp_add(dev, opp_def->freq, opp_def->u_volt); | ||
| 75 | if (r) { | ||
| 76 | dev_err(dev, "%s: add OPP %ld failed for %s [%d] " | ||
| 77 | "result=%d\n", | ||
| 78 | __func__, opp_def->freq, | ||
| 79 | opp_def->hwmod_name, i, r); | ||
| 80 | } else { | ||
| 81 | if (!opp_def->default_available) | ||
| 82 | r = opp_disable(dev, opp_def->freq); | ||
| 83 | if (r) | ||
| 84 | dev_err(dev, "%s: disable %ld failed for %s " | ||
| 85 | "[%d] result=%d\n", | ||
| 86 | __func__, opp_def->freq, | ||
| 87 | opp_def->hwmod_name, i, r); | ||
| 88 | } | ||
| 89 | opp_def++; | ||
| 90 | } | ||
| 91 | |||
| 92 | return 0; | ||
| 93 | } | ||
diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c new file mode 100644 index 000000000000..0486fce8a92c --- /dev/null +++ b/arch/arm/mach-omap2/opp3xxx_data.c | |||
| @@ -0,0 +1,107 @@ | |||
| 1 | /* | ||
| 2 | * OMAP3 OPP table definitions. | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 5 | * Nishanth Menon | ||
| 6 | * Kevin Hilman | ||
| 7 | * Copyright (C) 2010 Nokia Corporation. | ||
| 8 | * Eduardo Valentin | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | * | ||
| 14 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
| 15 | * kind, whether express or implied; without even the implied warranty | ||
| 16 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 17 | * GNU General Public License for more details. | ||
| 18 | */ | ||
| 19 | #include <linux/module.h> | ||
| 20 | |||
| 21 | #include <plat/cpu.h> | ||
| 22 | |||
| 23 | #include "omap_opp_data.h" | ||
| 24 | |||
| 25 | static struct omap_opp_def __initdata omap34xx_opp_def_list[] = { | ||
| 26 | /* MPU OPP1 */ | ||
| 27 | OPP_INITIALIZER("mpu", true, 125000000, 975000), | ||
| 28 | /* MPU OPP2 */ | ||
| 29 | OPP_INITIALIZER("mpu", true, 250000000, 1075000), | ||
| 30 | /* MPU OPP3 */ | ||
| 31 | OPP_INITIALIZER("mpu", true, 500000000, 1200000), | ||
| 32 | /* MPU OPP4 */ | ||
| 33 | OPP_INITIALIZER("mpu", true, 550000000, 1270000), | ||
| 34 | /* MPU OPP5 */ | ||
| 35 | OPP_INITIALIZER("mpu", true, 600000000, 1350000), | ||
| 36 | |||
| 37 | /* | ||
| 38 | * L3 OPP1 - 41.5 MHz is disabled because: The voltage for that OPP is | ||
| 39 | * almost the same than the one at 83MHz thus providing very little | ||
| 40 | * gain for the power point of view. In term of energy it will even | ||
| 41 | * increase the consumption due to the very negative performance | ||
| 42 | * impact that frequency will do to the MPU and the whole system in | ||
| 43 | * general. | ||
| 44 | */ | ||
| 45 | OPP_INITIALIZER("l3_main", false, 41500000, 975000), | ||
| 46 | /* L3 OPP2 */ | ||
| 47 | OPP_INITIALIZER("l3_main", true, 83000000, 1050000), | ||
| 48 | /* L3 OPP3 */ | ||
| 49 | OPP_INITIALIZER("l3_main", true, 166000000, 1150000), | ||
| 50 | |||
| 51 | /* DSP OPP1 */ | ||
| 52 | OPP_INITIALIZER("iva", true, 90000000, 975000), | ||
| 53 | /* DSP OPP2 */ | ||
| 54 | OPP_INITIALIZER("iva", true, 180000000, 1075000), | ||
| 55 | /* DSP OPP3 */ | ||
| 56 | OPP_INITIALIZER("iva", true, 360000000, 1200000), | ||
| 57 | /* DSP OPP4 */ | ||
| 58 | OPP_INITIALIZER("iva", true, 400000000, 1270000), | ||
| 59 | /* DSP OPP5 */ | ||
| 60 | OPP_INITIALIZER("iva", true, 430000000, 1350000), | ||
| 61 | }; | ||
| 62 | |||
| 63 | static struct omap_opp_def __initdata omap36xx_opp_def_list[] = { | ||
| 64 | /* MPU OPP1 - OPP50 */ | ||
| 65 | OPP_INITIALIZER("mpu", true, 300000000, 1012500), | ||
| 66 | /* MPU OPP2 - OPP100 */ | ||
| 67 | OPP_INITIALIZER("mpu", true, 600000000, 1200000), | ||
| 68 | /* MPU OPP3 - OPP-Turbo */ | ||
| 69 | OPP_INITIALIZER("mpu", false, 800000000, 1325000), | ||
| 70 | /* MPU OPP4 - OPP-SB */ | ||
| 71 | OPP_INITIALIZER("mpu", false, 1000000000, 1375000), | ||
| 72 | |||
| 73 | /* L3 OPP1 - OPP50 */ | ||
| 74 | OPP_INITIALIZER("l3_main", true, 100000000, 1000000), | ||
| 75 | /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */ | ||
| 76 | OPP_INITIALIZER("l3_main", true, 200000000, 1200000), | ||
| 77 | |||
| 78 | /* DSP OPP1 - OPP50 */ | ||
| 79 | OPP_INITIALIZER("iva", true, 260000000, 1012500), | ||
| 80 | /* DSP OPP2 - OPP100 */ | ||
| 81 | OPP_INITIALIZER("iva", true, 520000000, 1200000), | ||
| 82 | /* DSP OPP3 - OPP-Turbo */ | ||
| 83 | OPP_INITIALIZER("iva", false, 660000000, 1325000), | ||
| 84 | /* DSP OPP4 - OPP-SB */ | ||
| 85 | OPP_INITIALIZER("iva", false, 800000000, 1375000), | ||
| 86 | }; | ||
| 87 | |||
| 88 | /** | ||
| 89 | * omap3_opp_init() - initialize omap3 opp table | ||
| 90 | */ | ||
| 91 | static int __init omap3_opp_init(void) | ||
| 92 | { | ||
| 93 | int r = -ENODEV; | ||
| 94 | |||
| 95 | if (!cpu_is_omap34xx()) | ||
| 96 | return r; | ||
| 97 | |||
| 98 | if (cpu_is_omap3630()) | ||
| 99 | r = omap_init_opp_table(omap36xx_opp_def_list, | ||
| 100 | ARRAY_SIZE(omap36xx_opp_def_list)); | ||
| 101 | else | ||
| 102 | r = omap_init_opp_table(omap34xx_opp_def_list, | ||
| 103 | ARRAY_SIZE(omap34xx_opp_def_list)); | ||
| 104 | |||
| 105 | return r; | ||
| 106 | } | ||
| 107 | device_initcall(omap3_opp_init); | ||
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c new file mode 100644 index 000000000000..a11fa566d8ee --- /dev/null +++ b/arch/arm/mach-omap2/opp4xxx_data.c | |||
| @@ -0,0 +1,57 @@ | |||
| 1 | /* | ||
| 2 | * OMAP4 OPP table definitions. | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 5 | * Nishanth Menon | ||
| 6 | * Kevin Hilman | ||
| 7 | * Thara Gopinath | ||
| 8 | * Copyright (C) 2010 Nokia Corporation. | ||
| 9 | * Eduardo Valentin | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | * | ||
| 15 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
| 16 | * kind, whether express or implied; without even the implied warranty | ||
| 17 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 18 | * GNU General Public License for more details. | ||
| 19 | */ | ||
| 20 | #include <linux/module.h> | ||
| 21 | |||
| 22 | #include <plat/cpu.h> | ||
| 23 | |||
| 24 | #include "omap_opp_data.h" | ||
| 25 | |||
| 26 | static struct omap_opp_def __initdata omap44xx_opp_def_list[] = { | ||
| 27 | /* MPU OPP1 - OPP50 */ | ||
| 28 | OPP_INITIALIZER("mpu", true, 300000000, 1100000), | ||
| 29 | /* MPU OPP2 - OPP100 */ | ||
| 30 | OPP_INITIALIZER("mpu", true, 600000000, 1200000), | ||
| 31 | /* MPU OPP3 - OPP-Turbo */ | ||
| 32 | OPP_INITIALIZER("mpu", false, 800000000, 1260000), | ||
| 33 | /* MPU OPP4 - OPP-SB */ | ||
| 34 | OPP_INITIALIZER("mpu", false, 1008000000, 1350000), | ||
| 35 | /* L3 OPP1 - OPP50 */ | ||
| 36 | OPP_INITIALIZER("l3_main_1", true, 100000000, 930000), | ||
| 37 | /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */ | ||
| 38 | OPP_INITIALIZER("l3_main_1", true, 200000000, 1100000), | ||
| 39 | /* TODO: add IVA, DSP, aess, fdif, gpu */ | ||
| 40 | }; | ||
| 41 | |||
| 42 | /** | ||
| 43 | * omap4_opp_init() - initialize omap4 opp table | ||
| 44 | */ | ||
| 45 | static int __init omap4_opp_init(void) | ||
| 46 | { | ||
| 47 | int r = -ENODEV; | ||
| 48 | |||
| 49 | if (!cpu_is_omap44xx()) | ||
| 50 | return r; | ||
| 51 | |||
| 52 | r = omap_init_opp_table(omap44xx_opp_def_list, | ||
| 53 | ARRAY_SIZE(omap44xx_opp_def_list)); | ||
| 54 | |||
| 55 | return r; | ||
| 56 | } | ||
| 57 | device_initcall(omap4_opp_init); | ||
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index a8afb610c7d8..125f56591fb5 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c | |||
| @@ -29,12 +29,13 @@ | |||
| 29 | 29 | ||
| 30 | #include <plat/clock.h> | 30 | #include <plat/clock.h> |
| 31 | #include <plat/board.h> | 31 | #include <plat/board.h> |
| 32 | #include <plat/powerdomain.h> | 32 | #include "powerdomain.h" |
| 33 | #include <plat/clockdomain.h> | 33 | #include "clockdomain.h" |
| 34 | #include <plat/dmtimer.h> | 34 | #include <plat/dmtimer.h> |
| 35 | #include <plat/omap-pm.h> | ||
| 35 | 36 | ||
| 36 | #include "prm.h" | 37 | #include "cm2xxx_3xxx.h" |
| 37 | #include "cm.h" | 38 | #include "prm2xxx_3xxx.h" |
| 38 | #include "pm.h" | 39 | #include "pm.h" |
| 39 | 40 | ||
| 40 | int omap2_pm_debug; | 41 | int omap2_pm_debug; |
| @@ -45,10 +46,10 @@ u32 wakeup_timer_milliseconds; | |||
| 45 | 46 | ||
| 46 | #define DUMP_PRM_MOD_REG(mod, reg) \ | 47 | #define DUMP_PRM_MOD_REG(mod, reg) \ |
| 47 | regs[reg_count].name = #mod "." #reg; \ | 48 | regs[reg_count].name = #mod "." #reg; \ |
| 48 | regs[reg_count++].val = prm_read_mod_reg(mod, reg) | 49 | regs[reg_count++].val = omap2_prm_read_mod_reg(mod, reg) |
| 49 | #define DUMP_CM_MOD_REG(mod, reg) \ | 50 | #define DUMP_CM_MOD_REG(mod, reg) \ |
| 50 | regs[reg_count].name = #mod "." #reg; \ | 51 | regs[reg_count].name = #mod "." #reg; \ |
| 51 | regs[reg_count++].val = cm_read_mod_reg(mod, reg) | 52 | regs[reg_count++].val = omap2_cm_read_mod_reg(mod, reg) |
| 52 | #define DUMP_PRM_REG(reg) \ | 53 | #define DUMP_PRM_REG(reg) \ |
| 53 | regs[reg_count].name = #reg; \ | 54 | regs[reg_count].name = #reg; \ |
| 54 | regs[reg_count++].val = __raw_readl(reg) | 55 | regs[reg_count++].val = __raw_readl(reg) |
| @@ -328,10 +329,10 @@ static void pm_dbg_regset_store(u32 *ptr) | |||
| 328 | for (j = pm_dbg_reg_modules[i].low; | 329 | for (j = pm_dbg_reg_modules[i].low; |
| 329 | j <= pm_dbg_reg_modules[i].high; j += 4) { | 330 | j <= pm_dbg_reg_modules[i].high; j += 4) { |
| 330 | if (pm_dbg_reg_modules[i].type == MOD_CM) | 331 | if (pm_dbg_reg_modules[i].type == MOD_CM) |
| 331 | val = cm_read_mod_reg( | 332 | val = omap2_cm_read_mod_reg( |
| 332 | pm_dbg_reg_modules[i].offset, j); | 333 | pm_dbg_reg_modules[i].offset, j); |
| 333 | else | 334 | else |
| 334 | val = prm_read_mod_reg( | 335 | val = omap2_prm_read_mod_reg( |
| 335 | pm_dbg_reg_modules[i].offset, j); | 336 | pm_dbg_reg_modules[i].offset, j); |
| 336 | *(ptr++) = val; | 337 | *(ptr++) = val; |
| 337 | } | 338 | } |
| @@ -581,6 +582,10 @@ static int option_set(void *data, u64 val) | |||
| 581 | *option = val; | 582 | *option = val; |
| 582 | 583 | ||
| 583 | if (option == &enable_off_mode) { | 584 | if (option == &enable_off_mode) { |
| 585 | if (val) | ||
| 586 | omap_pm_enable_off_mode(); | ||
| 587 | else | ||
| 588 | omap_pm_disable_off_mode(); | ||
| 584 | if (cpu_is_omap34xx()) | 589 | if (cpu_is_omap34xx()) |
| 585 | omap3_pm_off_mode_enable(val); | 590 | omap3_pm_off_mode_enable(val); |
| 586 | } | 591 | } |
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 59ca03b0e691..d5a102c71989 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c | |||
| @@ -13,13 +13,16 @@ | |||
| 13 | #include <linux/init.h> | 13 | #include <linux/init.h> |
| 14 | #include <linux/io.h> | 14 | #include <linux/io.h> |
| 15 | #include <linux/err.h> | 15 | #include <linux/err.h> |
| 16 | #include <linux/opp.h> | ||
| 16 | 17 | ||
| 17 | #include <plat/omap-pm.h> | 18 | #include <plat/omap-pm.h> |
| 18 | #include <plat/omap_device.h> | 19 | #include <plat/omap_device.h> |
| 19 | #include <plat/common.h> | 20 | #include <plat/common.h> |
| 21 | #include <plat/voltage.h> | ||
| 20 | 22 | ||
| 21 | #include <plat/powerdomain.h> | 23 | #include "powerdomain.h" |
| 22 | #include <plat/clockdomain.h> | 24 | #include "clockdomain.h" |
| 25 | #include "pm.h" | ||
| 23 | 26 | ||
| 24 | static struct omap_device_pm_latency *pm_lats; | 27 | static struct omap_device_pm_latency *pm_lats; |
| 25 | 28 | ||
| @@ -89,10 +92,13 @@ static void omap2_init_processor_devices(void) | |||
| 89 | } | 92 | } |
| 90 | } | 93 | } |
| 91 | 94 | ||
| 95 | /* Types of sleep_switch used in omap_set_pwrdm_state */ | ||
| 96 | #define FORCEWAKEUP_SWITCH 0 | ||
| 97 | #define LOWPOWERSTATE_SWITCH 1 | ||
| 98 | |||
| 92 | /* | 99 | /* |
| 93 | * This sets pwrdm state (other than mpu & core. Currently only ON & | 100 | * This sets pwrdm state (other than mpu & core. Currently only ON & |
| 94 | * RET are supported. Function is assuming that clkdm doesn't have | 101 | * RET are supported. |
| 95 | * hw_sup mode enabled. | ||
| 96 | */ | 102 | */ |
| 97 | int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state) | 103 | int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state) |
| 98 | { | 104 | { |
| @@ -114,9 +120,14 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state) | |||
| 114 | return ret; | 120 | return ret; |
| 115 | 121 | ||
| 116 | if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) { | 122 | if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) { |
| 117 | omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); | 123 | if ((pwrdm_read_pwrst(pwrdm) > state) && |
| 118 | sleep_switch = 1; | 124 | (pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE)) { |
| 119 | pwrdm_wait_transition(pwrdm); | 125 | sleep_switch = LOWPOWERSTATE_SWITCH; |
| 126 | } else { | ||
| 127 | omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); | ||
| 128 | pwrdm_wait_transition(pwrdm); | ||
| 129 | sleep_switch = FORCEWAKEUP_SWITCH; | ||
| 130 | } | ||
| 120 | } | 131 | } |
| 121 | 132 | ||
| 122 | ret = pwrdm_set_next_pwrst(pwrdm, state); | 133 | ret = pwrdm_set_next_pwrst(pwrdm, state); |
| @@ -126,16 +137,106 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state) | |||
| 126 | goto err; | 137 | goto err; |
| 127 | } | 138 | } |
| 128 | 139 | ||
| 129 | if (sleep_switch) { | 140 | switch (sleep_switch) { |
| 130 | omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); | 141 | case FORCEWAKEUP_SWITCH: |
| 131 | pwrdm_wait_transition(pwrdm); | 142 | if (pwrdm->pwrdm_clkdms[0]->flags & CLKDM_CAN_ENABLE_AUTO) |
| 132 | pwrdm_state_switch(pwrdm); | 143 | omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); |
| 144 | else | ||
| 145 | omap2_clkdm_sleep(pwrdm->pwrdm_clkdms[0]); | ||
| 146 | break; | ||
| 147 | case LOWPOWERSTATE_SWITCH: | ||
| 148 | pwrdm_set_lowpwrstchange(pwrdm); | ||
| 149 | break; | ||
| 150 | default: | ||
| 151 | return ret; | ||
| 133 | } | 152 | } |
| 134 | 153 | ||
| 154 | pwrdm_wait_transition(pwrdm); | ||
| 155 | pwrdm_state_switch(pwrdm); | ||
| 135 | err: | 156 | err: |
| 136 | return ret; | 157 | return ret; |
| 137 | } | 158 | } |
| 138 | 159 | ||
| 160 | /* | ||
| 161 | * This API is to be called during init to put the various voltage | ||
| 162 | * domains to the voltage as per the opp table. Typically we boot up | ||
| 163 | * at the nominal voltage. So this function finds out the rate of | ||
| 164 | * the clock associated with the voltage domain, finds out the correct | ||
| 165 | * opp entry and puts the voltage domain to the voltage specifies | ||
| 166 | * in the opp entry | ||
| 167 | */ | ||
| 168 | static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name, | ||
| 169 | struct device *dev) | ||
| 170 | { | ||
| 171 | struct voltagedomain *voltdm; | ||
| 172 | struct clk *clk; | ||
| 173 | struct opp *opp; | ||
| 174 | unsigned long freq, bootup_volt; | ||
| 175 | |||
| 176 | if (!vdd_name || !clk_name || !dev) { | ||
| 177 | printk(KERN_ERR "%s: Invalid parameters!\n", __func__); | ||
| 178 | goto exit; | ||
| 179 | } | ||
| 180 | |||
| 181 | voltdm = omap_voltage_domain_lookup(vdd_name); | ||
| 182 | if (IS_ERR(voltdm)) { | ||
| 183 | printk(KERN_ERR "%s: Unable to get vdd pointer for vdd_%s\n", | ||
| 184 | __func__, vdd_name); | ||
| 185 | goto exit; | ||
| 186 | } | ||
| 187 | |||
| 188 | clk = clk_get(NULL, clk_name); | ||
| 189 | if (IS_ERR(clk)) { | ||
| 190 | printk(KERN_ERR "%s: unable to get clk %s\n", | ||
| 191 | __func__, clk_name); | ||
| 192 | goto exit; | ||
| 193 | } | ||
| 194 | |||
| 195 | freq = clk->rate; | ||
| 196 | clk_put(clk); | ||
| 197 | |||
| 198 | opp = opp_find_freq_ceil(dev, &freq); | ||
| 199 | if (IS_ERR(opp)) { | ||
| 200 | printk(KERN_ERR "%s: unable to find boot up OPP for vdd_%s\n", | ||
| 201 | __func__, vdd_name); | ||
| 202 | goto exit; | ||
| 203 | } | ||
| 204 | |||
| 205 | bootup_volt = opp_get_voltage(opp); | ||
| 206 | if (!bootup_volt) { | ||
| 207 | printk(KERN_ERR "%s: unable to find voltage corresponding" | ||
| 208 | "to the bootup OPP for vdd_%s\n", __func__, vdd_name); | ||
| 209 | goto exit; | ||
| 210 | } | ||
| 211 | |||
| 212 | omap_voltage_scale_vdd(voltdm, bootup_volt); | ||
| 213 | return 0; | ||
| 214 | |||
| 215 | exit: | ||
| 216 | printk(KERN_ERR "%s: Unable to put vdd_%s to its init voltage\n\n", | ||
| 217 | __func__, vdd_name); | ||
| 218 | return -EINVAL; | ||
| 219 | } | ||
| 220 | |||
| 221 | static void __init omap3_init_voltages(void) | ||
| 222 | { | ||
| 223 | if (!cpu_is_omap34xx()) | ||
| 224 | return; | ||
| 225 | |||
| 226 | omap2_set_init_voltage("mpu", "dpll1_ck", mpu_dev); | ||
| 227 | omap2_set_init_voltage("core", "l3_ick", l3_dev); | ||
| 228 | } | ||
| 229 | |||
| 230 | static void __init omap4_init_voltages(void) | ||
| 231 | { | ||
| 232 | if (!cpu_is_omap44xx()) | ||
| 233 | return; | ||
| 234 | |||
| 235 | omap2_set_init_voltage("mpu", "dpll_mpu_ck", mpu_dev); | ||
| 236 | omap2_set_init_voltage("core", "l3_div_ck", l3_dev); | ||
| 237 | omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", iva_dev); | ||
| 238 | } | ||
| 239 | |||
| 139 | static int __init omap2_common_pm_init(void) | 240 | static int __init omap2_common_pm_init(void) |
| 140 | { | 241 | { |
| 141 | omap2_init_processor_devices(); | 242 | omap2_init_processor_devices(); |
| @@ -143,5 +244,24 @@ static int __init omap2_common_pm_init(void) | |||
| 143 | 244 | ||
| 144 | return 0; | 245 | return 0; |
| 145 | } | 246 | } |
| 146 | device_initcall(omap2_common_pm_init); | 247 | postcore_initcall(omap2_common_pm_init); |
| 248 | |||
| 249 | static int __init omap2_common_pm_late_init(void) | ||
| 250 | { | ||
| 251 | /* Init the OMAP TWL parameters */ | ||
| 252 | omap3_twl_init(); | ||
| 253 | omap4_twl_init(); | ||
| 254 | |||
| 255 | /* Init the voltage layer */ | ||
| 256 | omap_voltage_late_init(); | ||
| 147 | 257 | ||
| 258 | /* Initialize the voltages */ | ||
| 259 | omap3_init_voltages(); | ||
| 260 | omap4_init_voltages(); | ||
| 261 | |||
| 262 | /* Smartreflex device init */ | ||
| 263 | omap_devinit_smartreflex(); | ||
| 264 | |||
| 265 | return 0; | ||
| 266 | } | ||
| 267 | late_initcall(omap2_common_pm_late_init); | ||
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 0d75bfd1fdbe..1c1b0ab5b978 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h | |||
| @@ -11,7 +11,9 @@ | |||
| 11 | #ifndef __ARCH_ARM_MACH_OMAP2_PM_H | 11 | #ifndef __ARCH_ARM_MACH_OMAP2_PM_H |
| 12 | #define __ARCH_ARM_MACH_OMAP2_PM_H | 12 | #define __ARCH_ARM_MACH_OMAP2_PM_H |
| 13 | 13 | ||
| 14 | #include <plat/powerdomain.h> | 14 | #include <linux/err.h> |
| 15 | |||
| 16 | #include "powerdomain.h" | ||
| 15 | 17 | ||
| 16 | extern void *omap3_secure_ram_storage; | 18 | extern void *omap3_secure_ram_storage; |
| 17 | extern void omap3_pm_off_mode_enable(int); | 19 | extern void omap3_pm_off_mode_enable(int); |
| @@ -20,6 +22,20 @@ extern int omap3_can_sleep(void); | |||
| 20 | extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state); | 22 | extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state); |
| 21 | extern int omap3_idle_init(void); | 23 | extern int omap3_idle_init(void); |
| 22 | 24 | ||
| 25 | #if defined(CONFIG_PM_OPP) | ||
| 26 | extern int omap3_opp_init(void); | ||
| 27 | extern int omap4_opp_init(void); | ||
| 28 | #else | ||
| 29 | static inline int omap3_opp_init(void) | ||
| 30 | { | ||
| 31 | return -EINVAL; | ||
| 32 | } | ||
| 33 | static inline int omap4_opp_init(void) | ||
| 34 | { | ||
| 35 | return -EINVAL; | ||
| 36 | } | ||
| 37 | #endif | ||
| 38 | |||
| 23 | struct cpuidle_params { | 39 | struct cpuidle_params { |
| 24 | u8 valid; | 40 | u8 valid; |
| 25 | u32 sleep_latency; | 41 | u32 sleep_latency; |
| @@ -58,7 +74,7 @@ extern u32 sleep_while_idle; | |||
| 58 | #endif | 74 | #endif |
| 59 | 75 | ||
| 60 | #if defined(CONFIG_CPU_IDLE) | 76 | #if defined(CONFIG_CPU_IDLE) |
| 61 | extern void omap3_cpuidle_update_states(void); | 77 | extern void omap3_cpuidle_update_states(u32, u32); |
| 62 | #endif | 78 | #endif |
| 63 | 79 | ||
| 64 | #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) | 80 | #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) |
| @@ -80,9 +96,46 @@ extern void save_secure_ram_context(u32 *addr); | |||
| 80 | extern void omap3_save_scratchpad_contents(void); | 96 | extern void omap3_save_scratchpad_contents(void); |
| 81 | 97 | ||
| 82 | extern unsigned int omap24xx_idle_loop_suspend_sz; | 98 | extern unsigned int omap24xx_idle_loop_suspend_sz; |
| 83 | extern unsigned int omap34xx_suspend_sz; | ||
| 84 | extern unsigned int save_secure_ram_context_sz; | 99 | extern unsigned int save_secure_ram_context_sz; |
| 85 | extern unsigned int omap24xx_cpu_suspend_sz; | 100 | extern unsigned int omap24xx_cpu_suspend_sz; |
| 86 | extern unsigned int omap34xx_cpu_suspend_sz; | 101 | extern unsigned int omap34xx_cpu_suspend_sz; |
| 87 | 102 | ||
| 103 | #define PM_RTA_ERRATUM_i608 (1 << 0) | ||
| 104 | #define PM_SDRC_WAKEUP_ERRATUM_i583 (1 << 1) | ||
| 105 | |||
| 106 | #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) | ||
| 107 | extern u16 pm34xx_errata; | ||
| 108 | #define IS_PM34XX_ERRATUM(id) (pm34xx_errata & (id)) | ||
| 109 | extern void enable_omap3630_toggle_l2_on_restore(void); | ||
| 110 | #else | ||
| 111 | #define IS_PM34XX_ERRATUM(id) 0 | ||
| 112 | static inline void enable_omap3630_toggle_l2_on_restore(void) { } | ||
| 113 | #endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */ | ||
| 114 | |||
| 115 | #ifdef CONFIG_OMAP_SMARTREFLEX | ||
| 116 | extern int omap_devinit_smartreflex(void); | ||
| 117 | extern void omap_enable_smartreflex_on_init(void); | ||
| 118 | #else | ||
| 119 | static inline int omap_devinit_smartreflex(void) | ||
| 120 | { | ||
| 121 | return -EINVAL; | ||
| 122 | } | ||
| 123 | |||
| 124 | static inline void omap_enable_smartreflex_on_init(void) {} | ||
| 125 | #endif | ||
| 126 | |||
| 127 | #ifdef CONFIG_TWL4030_CORE | ||
| 128 | extern int omap3_twl_init(void); | ||
| 129 | extern int omap4_twl_init(void); | ||
| 130 | #else | ||
| 131 | static inline int omap3_twl_init(void) | ||
| 132 | { | ||
| 133 | return -EINVAL; | ||
| 134 | } | ||
| 135 | static inline int omap4_twl_init(void) | ||
| 136 | { | ||
| 137 | return -EINVAL; | ||
| 138 | } | ||
| 139 | #endif | ||
| 140 | |||
| 88 | #endif | 141 | #endif |
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index aaeea49b9bdd..dac2d1d9987d 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c | |||
| @@ -42,16 +42,16 @@ | |||
| 42 | #include <plat/dma.h> | 42 | #include <plat/dma.h> |
| 43 | #include <plat/board.h> | 43 | #include <plat/board.h> |
| 44 | 44 | ||
| 45 | #include "prm.h" | 45 | #include "prm2xxx_3xxx.h" |
| 46 | #include "prm-regbits-24xx.h" | 46 | #include "prm-regbits-24xx.h" |
| 47 | #include "cm.h" | 47 | #include "cm2xxx_3xxx.h" |
| 48 | #include "cm-regbits-24xx.h" | 48 | #include "cm-regbits-24xx.h" |
| 49 | #include "sdrc.h" | 49 | #include "sdrc.h" |
| 50 | #include "pm.h" | 50 | #include "pm.h" |
| 51 | #include "control.h" | 51 | #include "control.h" |
| 52 | 52 | ||
| 53 | #include <plat/powerdomain.h> | 53 | #include "powerdomain.h" |
| 54 | #include <plat/clockdomain.h> | 54 | #include "clockdomain.h" |
| 55 | 55 | ||
| 56 | #ifdef CONFIG_SUSPEND | 56 | #ifdef CONFIG_SUSPEND |
| 57 | static suspend_state_t suspend_state = PM_SUSPEND_ON; | 57 | static suspend_state_t suspend_state = PM_SUSPEND_ON; |
| @@ -79,8 +79,8 @@ static int omap2_fclks_active(void) | |||
| 79 | { | 79 | { |
| 80 | u32 f1, f2; | 80 | u32 f1, f2; |
| 81 | 81 | ||
| 82 | f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); | 82 | f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); |
| 83 | f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); | 83 | f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); |
| 84 | 84 | ||
| 85 | /* Ignore UART clocks. These are handled by UART core (serial.c) */ | 85 | /* Ignore UART clocks. These are handled by UART core (serial.c) */ |
| 86 | f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK); | 86 | f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK); |
| @@ -105,9 +105,9 @@ static void omap2_enter_full_retention(void) | |||
| 105 | 105 | ||
| 106 | /* Clear old wake-up events */ | 106 | /* Clear old wake-up events */ |
| 107 | /* REVISIT: These write to reserved bits? */ | 107 | /* REVISIT: These write to reserved bits? */ |
| 108 | prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); | 108 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); |
| 109 | prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); | 109 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); |
| 110 | prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); | 110 | omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); |
| 111 | 111 | ||
| 112 | /* | 112 | /* |
| 113 | * Set MPU powerdomain's next power state to RETENTION; | 113 | * Set MPU powerdomain's next power state to RETENTION; |
| @@ -120,7 +120,7 @@ static void omap2_enter_full_retention(void) | |||
| 120 | l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL; | 120 | l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL; |
| 121 | omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0); | 121 | omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0); |
| 122 | 122 | ||
| 123 | omap2_gpio_prepare_for_idle(PWRDM_POWER_RET); | 123 | omap2_gpio_prepare_for_idle(0); |
| 124 | 124 | ||
| 125 | if (omap2_pm_debug) { | 125 | if (omap2_pm_debug) { |
| 126 | omap2_pm_dump(0, 0, 0); | 126 | omap2_pm_dump(0, 0, 0); |
| @@ -167,30 +167,30 @@ no_sleep: | |||
| 167 | clk_enable(osc_ck); | 167 | clk_enable(osc_ck); |
| 168 | 168 | ||
| 169 | /* clear CORE wake-up events */ | 169 | /* clear CORE wake-up events */ |
| 170 | prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); | 170 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); |
| 171 | prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); | 171 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); |
| 172 | 172 | ||
| 173 | /* wakeup domain events - bit 1: GPT1, bit5 GPIO */ | 173 | /* wakeup domain events - bit 1: GPT1, bit5 GPIO */ |
| 174 | prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST); | 174 | omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST); |
| 175 | 175 | ||
| 176 | /* MPU domain wake events */ | 176 | /* MPU domain wake events */ |
| 177 | l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); | 177 | l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); |
| 178 | if (l & 0x01) | 178 | if (l & 0x01) |
| 179 | prm_write_mod_reg(0x01, OCP_MOD, | 179 | omap2_prm_write_mod_reg(0x01, OCP_MOD, |
| 180 | OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); | 180 | OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); |
| 181 | if (l & 0x20) | 181 | if (l & 0x20) |
| 182 | prm_write_mod_reg(0x20, OCP_MOD, | 182 | omap2_prm_write_mod_reg(0x20, OCP_MOD, |
| 183 | OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); | 183 | OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); |
| 184 | 184 | ||
| 185 | /* Mask future PRCM-to-MPU interrupts */ | 185 | /* Mask future PRCM-to-MPU interrupts */ |
| 186 | prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); | 186 | omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); |
| 187 | } | 187 | } |
| 188 | 188 | ||
| 189 | static int omap2_i2c_active(void) | 189 | static int omap2_i2c_active(void) |
| 190 | { | 190 | { |
| 191 | u32 l; | 191 | u32 l; |
| 192 | 192 | ||
| 193 | l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); | 193 | l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); |
| 194 | return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK); | 194 | return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK); |
| 195 | } | 195 | } |
| 196 | 196 | ||
| @@ -201,13 +201,13 @@ static int omap2_allow_mpu_retention(void) | |||
| 201 | u32 l; | 201 | u32 l; |
| 202 | 202 | ||
| 203 | /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */ | 203 | /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */ |
| 204 | l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); | 204 | l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); |
| 205 | if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK | | 205 | if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK | |
| 206 | OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK | | 206 | OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK | |
| 207 | OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK)) | 207 | OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK)) |
| 208 | return 0; | 208 | return 0; |
| 209 | /* Check for UART3. */ | 209 | /* Check for UART3. */ |
| 210 | l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); | 210 | l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); |
| 211 | if (l & OMAP24XX_EN_UART3_MASK) | 211 | if (l & OMAP24XX_EN_UART3_MASK) |
| 212 | return 0; | 212 | return 0; |
| 213 | if (sti_console_enabled) | 213 | if (sti_console_enabled) |
| @@ -230,18 +230,18 @@ static void omap2_enter_mpu_retention(void) | |||
| 230 | * it is in retention mode. */ | 230 | * it is in retention mode. */ |
| 231 | if (omap2_allow_mpu_retention()) { | 231 | if (omap2_allow_mpu_retention()) { |
| 232 | /* REVISIT: These write to reserved bits? */ | 232 | /* REVISIT: These write to reserved bits? */ |
| 233 | prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); | 233 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); |
| 234 | prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); | 234 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); |
| 235 | prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); | 235 | omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); |
| 236 | 236 | ||
| 237 | /* Try to enter MPU retention */ | 237 | /* Try to enter MPU retention */ |
| 238 | prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | | 238 | omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | |
| 239 | OMAP_LOGICRETSTATE_MASK, | 239 | OMAP_LOGICRETSTATE_MASK, |
| 240 | MPU_MOD, OMAP2_PM_PWSTCTRL); | 240 | MPU_MOD, OMAP2_PM_PWSTCTRL); |
| 241 | } else { | 241 | } else { |
| 242 | /* Block MPU retention */ | 242 | /* Block MPU retention */ |
| 243 | 243 | ||
| 244 | prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD, | 244 | omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD, |
| 245 | OMAP2_PM_PWSTCTRL); | 245 | OMAP2_PM_PWSTCTRL); |
| 246 | only_idle = 1; | 246 | only_idle = 1; |
| 247 | } | 247 | } |
| @@ -299,16 +299,11 @@ out: | |||
| 299 | local_irq_enable(); | 299 | local_irq_enable(); |
| 300 | } | 300 | } |
| 301 | 301 | ||
| 302 | #ifdef CONFIG_SUSPEND | ||
| 302 | static int omap2_pm_begin(suspend_state_t state) | 303 | static int omap2_pm_begin(suspend_state_t state) |
| 303 | { | 304 | { |
| 304 | suspend_state = state; | ||
| 305 | return 0; | ||
| 306 | } | ||
| 307 | |||
| 308 | static int omap2_pm_prepare(void) | ||
| 309 | { | ||
| 310 | /* We cannot sleep in idle until we have resumed */ | ||
| 311 | disable_hlt(); | 305 | disable_hlt(); |
| 306 | suspend_state = state; | ||
| 312 | return 0; | 307 | return 0; |
| 313 | } | 308 | } |
| 314 | 309 | ||
| @@ -316,9 +311,9 @@ static int omap2_pm_suspend(void) | |||
| 316 | { | 311 | { |
| 317 | u32 wken_wkup, mir1; | 312 | u32 wken_wkup, mir1; |
| 318 | 313 | ||
| 319 | wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN); | 314 | wken_wkup = omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN); |
| 320 | wken_wkup &= ~OMAP24XX_EN_GPT1_MASK; | 315 | wken_wkup &= ~OMAP24XX_EN_GPT1_MASK; |
| 321 | prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN); | 316 | omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN); |
| 322 | 317 | ||
| 323 | /* Mask GPT1 */ | 318 | /* Mask GPT1 */ |
| 324 | mir1 = omap_readl(0x480fe0a4); | 319 | mir1 = omap_readl(0x480fe0a4); |
| @@ -328,7 +323,7 @@ static int omap2_pm_suspend(void) | |||
| 328 | omap2_enter_full_retention(); | 323 | omap2_enter_full_retention(); |
| 329 | 324 | ||
| 330 | omap_writel(mir1, 0x480fe0a4); | 325 | omap_writel(mir1, 0x480fe0a4); |
| 331 | prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN); | 326 | omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN); |
| 332 | 327 | ||
| 333 | return 0; | 328 | return 0; |
| 334 | } | 329 | } |
| @@ -349,24 +344,21 @@ static int omap2_pm_enter(suspend_state_t state) | |||
| 349 | return ret; | 344 | return ret; |
| 350 | } | 345 | } |
| 351 | 346 | ||
| 352 | static void omap2_pm_finish(void) | ||
| 353 | { | ||
| 354 | enable_hlt(); | ||
| 355 | } | ||
| 356 | |||
| 357 | static void omap2_pm_end(void) | 347 | static void omap2_pm_end(void) |
| 358 | { | 348 | { |
| 359 | suspend_state = PM_SUSPEND_ON; | 349 | suspend_state = PM_SUSPEND_ON; |
| 350 | enable_hlt(); | ||
| 360 | } | 351 | } |
| 361 | 352 | ||
| 362 | static struct platform_suspend_ops omap_pm_ops = { | 353 | static struct platform_suspend_ops omap_pm_ops = { |
| 363 | .begin = omap2_pm_begin, | 354 | .begin = omap2_pm_begin, |
| 364 | .prepare = omap2_pm_prepare, | ||
| 365 | .enter = omap2_pm_enter, | 355 | .enter = omap2_pm_enter, |
| 366 | .finish = omap2_pm_finish, | ||
| 367 | .end = omap2_pm_end, | 356 | .end = omap2_pm_end, |
| 368 | .valid = suspend_valid_only_mem, | 357 | .valid = suspend_valid_only_mem, |
| 369 | }; | 358 | }; |
| 359 | #else | ||
| 360 | static const struct platform_suspend_ops __initdata omap_pm_ops; | ||
| 361 | #endif /* CONFIG_SUSPEND */ | ||
| 370 | 362 | ||
| 371 | /* XXX This function should be shareable between OMAP2xxx and OMAP3 */ | 363 | /* XXX This function should be shareable between OMAP2xxx and OMAP3 */ |
| 372 | static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) | 364 | static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) |
| @@ -388,7 +380,7 @@ static void __init prcm_setup_regs(void) | |||
| 388 | struct powerdomain *pwrdm; | 380 | struct powerdomain *pwrdm; |
| 389 | 381 | ||
| 390 | /* Enable autoidle */ | 382 | /* Enable autoidle */ |
| 391 | prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD, | 383 | omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD, |
| 392 | OMAP2_PRCM_SYSCONFIG_OFFSET); | 384 | OMAP2_PRCM_SYSCONFIG_OFFSET); |
| 393 | 385 | ||
| 394 | /* | 386 | /* |
| @@ -427,87 +419,87 @@ static void __init prcm_setup_regs(void) | |||
| 427 | clkdm_add_wkdep(mpu_clkdm, wkup_clkdm); | 419 | clkdm_add_wkdep(mpu_clkdm, wkup_clkdm); |
| 428 | 420 | ||
| 429 | /* Enable clock autoidle for all domains */ | 421 | /* Enable clock autoidle for all domains */ |
| 430 | cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK | | 422 | omap2_cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK | |
| 431 | OMAP24XX_AUTO_MAILBOXES_MASK | | 423 | OMAP24XX_AUTO_MAILBOXES_MASK | |
| 432 | OMAP24XX_AUTO_WDT4_MASK | | 424 | OMAP24XX_AUTO_WDT4_MASK | |
| 433 | OMAP2420_AUTO_WDT3_MASK | | 425 | OMAP2420_AUTO_WDT3_MASK | |
| 434 | OMAP24XX_AUTO_MSPRO_MASK | | 426 | OMAP24XX_AUTO_MSPRO_MASK | |
| 435 | OMAP2420_AUTO_MMC_MASK | | 427 | OMAP2420_AUTO_MMC_MASK | |
| 436 | OMAP24XX_AUTO_FAC_MASK | | 428 | OMAP24XX_AUTO_FAC_MASK | |
| 437 | OMAP2420_AUTO_EAC_MASK | | 429 | OMAP2420_AUTO_EAC_MASK | |
| 438 | OMAP24XX_AUTO_HDQ_MASK | | 430 | OMAP24XX_AUTO_HDQ_MASK | |
| 439 | OMAP24XX_AUTO_UART2_MASK | | 431 | OMAP24XX_AUTO_UART2_MASK | |
| 440 | OMAP24XX_AUTO_UART1_MASK | | 432 | OMAP24XX_AUTO_UART1_MASK | |
| 441 | OMAP24XX_AUTO_I2C2_MASK | | 433 | OMAP24XX_AUTO_I2C2_MASK | |
| 442 | OMAP24XX_AUTO_I2C1_MASK | | 434 | OMAP24XX_AUTO_I2C1_MASK | |
| 443 | OMAP24XX_AUTO_MCSPI2_MASK | | 435 | OMAP24XX_AUTO_MCSPI2_MASK | |
| 444 | OMAP24XX_AUTO_MCSPI1_MASK | | 436 | OMAP24XX_AUTO_MCSPI1_MASK | |
| 445 | OMAP24XX_AUTO_MCBSP2_MASK | | 437 | OMAP24XX_AUTO_MCBSP2_MASK | |
| 446 | OMAP24XX_AUTO_MCBSP1_MASK | | 438 | OMAP24XX_AUTO_MCBSP1_MASK | |
| 447 | OMAP24XX_AUTO_GPT12_MASK | | 439 | OMAP24XX_AUTO_GPT12_MASK | |
| 448 | OMAP24XX_AUTO_GPT11_MASK | | 440 | OMAP24XX_AUTO_GPT11_MASK | |
| 449 | OMAP24XX_AUTO_GPT10_MASK | | 441 | OMAP24XX_AUTO_GPT10_MASK | |
| 450 | OMAP24XX_AUTO_GPT9_MASK | | 442 | OMAP24XX_AUTO_GPT9_MASK | |
| 451 | OMAP24XX_AUTO_GPT8_MASK | | 443 | OMAP24XX_AUTO_GPT8_MASK | |
| 452 | OMAP24XX_AUTO_GPT7_MASK | | 444 | OMAP24XX_AUTO_GPT7_MASK | |
| 453 | OMAP24XX_AUTO_GPT6_MASK | | 445 | OMAP24XX_AUTO_GPT6_MASK | |
| 454 | OMAP24XX_AUTO_GPT5_MASK | | 446 | OMAP24XX_AUTO_GPT5_MASK | |
| 455 | OMAP24XX_AUTO_GPT4_MASK | | 447 | OMAP24XX_AUTO_GPT4_MASK | |
| 456 | OMAP24XX_AUTO_GPT3_MASK | | 448 | OMAP24XX_AUTO_GPT3_MASK | |
| 457 | OMAP24XX_AUTO_GPT2_MASK | | 449 | OMAP24XX_AUTO_GPT2_MASK | |
| 458 | OMAP2420_AUTO_VLYNQ_MASK | | 450 | OMAP2420_AUTO_VLYNQ_MASK | |
| 459 | OMAP24XX_AUTO_DSS_MASK, | 451 | OMAP24XX_AUTO_DSS_MASK, |
| 460 | CORE_MOD, CM_AUTOIDLE1); | 452 | CORE_MOD, CM_AUTOIDLE1); |
| 461 | cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK | | 453 | omap2_cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK | |
| 462 | OMAP24XX_AUTO_SSI_MASK | | 454 | OMAP24XX_AUTO_SSI_MASK | |
| 463 | OMAP24XX_AUTO_USB_MASK, | 455 | OMAP24XX_AUTO_USB_MASK, |
| 464 | CORE_MOD, CM_AUTOIDLE2); | 456 | CORE_MOD, CM_AUTOIDLE2); |
| 465 | cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK | | 457 | omap2_cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK | |
| 466 | OMAP24XX_AUTO_GPMC_MASK | | 458 | OMAP24XX_AUTO_GPMC_MASK | |
| 467 | OMAP24XX_AUTO_SDMA_MASK, | 459 | OMAP24XX_AUTO_SDMA_MASK, |
| 468 | CORE_MOD, CM_AUTOIDLE3); | 460 | CORE_MOD, CM_AUTOIDLE3); |
| 469 | cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK | | 461 | omap2_cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK | |
| 470 | OMAP24XX_AUTO_AES_MASK | | 462 | OMAP24XX_AUTO_AES_MASK | |
| 471 | OMAP24XX_AUTO_RNG_MASK | | 463 | OMAP24XX_AUTO_RNG_MASK | |
| 472 | OMAP24XX_AUTO_SHA_MASK | | 464 | OMAP24XX_AUTO_SHA_MASK | |
| 473 | OMAP24XX_AUTO_DES_MASK, | 465 | OMAP24XX_AUTO_DES_MASK, |
| 474 | CORE_MOD, OMAP24XX_CM_AUTOIDLE4); | 466 | CORE_MOD, OMAP24XX_CM_AUTOIDLE4); |
| 475 | 467 | ||
| 476 | cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD, | 468 | omap2_cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD, |
| 477 | CM_AUTOIDLE); | 469 | CM_AUTOIDLE); |
| 478 | 470 | ||
| 479 | /* Put DPLL and both APLLs into autoidle mode */ | 471 | /* Put DPLL and both APLLs into autoidle mode */ |
| 480 | cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) | | 472 | omap2_cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) | |
| 481 | (0x03 << OMAP24XX_AUTO_96M_SHIFT) | | 473 | (0x03 << OMAP24XX_AUTO_96M_SHIFT) | |
| 482 | (0x03 << OMAP24XX_AUTO_54M_SHIFT), | 474 | (0x03 << OMAP24XX_AUTO_54M_SHIFT), |
| 483 | PLL_MOD, CM_AUTOIDLE); | 475 | PLL_MOD, CM_AUTOIDLE); |
| 484 | 476 | ||
| 485 | cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK | | 477 | omap2_cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK | |
| 486 | OMAP24XX_AUTO_WDT1_MASK | | 478 | OMAP24XX_AUTO_WDT1_MASK | |
| 487 | OMAP24XX_AUTO_MPU_WDT_MASK | | 479 | OMAP24XX_AUTO_MPU_WDT_MASK | |
| 488 | OMAP24XX_AUTO_GPIOS_MASK | | 480 | OMAP24XX_AUTO_GPIOS_MASK | |
| 489 | OMAP24XX_AUTO_32KSYNC_MASK | | 481 | OMAP24XX_AUTO_32KSYNC_MASK | |
| 490 | OMAP24XX_AUTO_GPT1_MASK, | 482 | OMAP24XX_AUTO_GPT1_MASK, |
| 491 | WKUP_MOD, CM_AUTOIDLE); | 483 | WKUP_MOD, CM_AUTOIDLE); |
| 492 | 484 | ||
| 493 | /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk | 485 | /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk |
| 494 | * stabilisation */ | 486 | * stabilisation */ |
| 495 | prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, | 487 | omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, |
| 496 | OMAP2_PRCM_CLKSSETUP_OFFSET); | 488 | OMAP2_PRCM_CLKSSETUP_OFFSET); |
| 497 | 489 | ||
| 498 | /* Configure automatic voltage transition */ | 490 | /* Configure automatic voltage transition */ |
| 499 | prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, | 491 | omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, |
| 500 | OMAP2_PRCM_VOLTSETUP_OFFSET); | 492 | OMAP2_PRCM_VOLTSETUP_OFFSET); |
| 501 | prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK | | 493 | omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK | |
| 502 | (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) | | 494 | (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) | |
| 503 | OMAP24XX_MEMRETCTRL_MASK | | 495 | OMAP24XX_MEMRETCTRL_MASK | |
| 504 | (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) | | 496 | (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) | |
| 505 | (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT), | 497 | (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT), |
| 506 | OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET); | 498 | OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET); |
| 507 | 499 | ||
| 508 | /* Enable wake-up events */ | 500 | /* Enable wake-up events */ |
| 509 | prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK, | 501 | omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK, |
| 510 | WKUP_MOD, PM_WKEN); | 502 | WKUP_MOD, PM_WKEN); |
| 511 | } | 503 | } |
| 512 | 504 | ||
| 513 | static int __init omap2_pm_init(void) | 505 | static int __init omap2_pm_init(void) |
| @@ -518,7 +510,7 @@ static int __init omap2_pm_init(void) | |||
| 518 | return -ENODEV; | 510 | return -ENODEV; |
| 519 | 511 | ||
| 520 | printk(KERN_INFO "Power Management for OMAP2 initializing\n"); | 512 | printk(KERN_INFO "Power Management for OMAP2 initializing\n"); |
| 521 | l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET); | 513 | l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET); |
| 522 | printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); | 514 | printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); |
| 523 | 515 | ||
| 524 | /* Look up important powerdomains */ | 516 | /* Look up important powerdomains */ |
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 648b8c50d024..5b323f28da2d 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c | |||
| @@ -31,8 +31,8 @@ | |||
| 31 | #include <linux/console.h> | 31 | #include <linux/console.h> |
| 32 | 32 | ||
| 33 | #include <plat/sram.h> | 33 | #include <plat/sram.h> |
| 34 | #include <plat/clockdomain.h> | 34 | #include "clockdomain.h" |
| 35 | #include <plat/powerdomain.h> | 35 | #include "powerdomain.h" |
| 36 | #include <plat/serial.h> | 36 | #include <plat/serial.h> |
| 37 | #include <plat/sdrc.h> | 37 | #include <plat/sdrc.h> |
| 38 | #include <plat/prcm.h> | 38 | #include <plat/prcm.h> |
| @@ -41,11 +41,11 @@ | |||
| 41 | 41 | ||
| 42 | #include <asm/tlbflush.h> | 42 | #include <asm/tlbflush.h> |
| 43 | 43 | ||
| 44 | #include "cm.h" | 44 | #include "cm2xxx_3xxx.h" |
| 45 | #include "cm-regbits-34xx.h" | 45 | #include "cm-regbits-34xx.h" |
| 46 | #include "prm-regbits-34xx.h" | 46 | #include "prm-regbits-34xx.h" |
| 47 | 47 | ||
| 48 | #include "prm.h" | 48 | #include "prm2xxx_3xxx.h" |
| 49 | #include "pm.h" | 49 | #include "pm.h" |
| 50 | #include "sdrc.h" | 50 | #include "sdrc.h" |
| 51 | #include "control.h" | 51 | #include "control.h" |
| @@ -68,6 +68,9 @@ static inline bool is_suspending(void) | |||
| 68 | #define OMAP343X_TABLE_VALUE_OFFSET 0xc0 | 68 | #define OMAP343X_TABLE_VALUE_OFFSET 0xc0 |
| 69 | #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8 | 69 | #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8 |
| 70 | 70 | ||
| 71 | /* pm34xx errata defined in pm.h */ | ||
| 72 | u16 pm34xx_errata; | ||
| 73 | |||
| 71 | struct power_state { | 74 | struct power_state { |
| 72 | struct powerdomain *pwrdm; | 75 | struct powerdomain *pwrdm; |
| 73 | u32 next_state; | 76 | u32 next_state; |
| @@ -102,12 +105,12 @@ static void omap3_enable_io_chain(void) | |||
| 102 | int timeout = 0; | 105 | int timeout = 0; |
| 103 | 106 | ||
| 104 | if (omap_rev() >= OMAP3430_REV_ES3_1) { | 107 | if (omap_rev() >= OMAP3430_REV_ES3_1) { |
| 105 | prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, | 108 | omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, |
| 106 | PM_WKEN); | 109 | PM_WKEN); |
| 107 | /* Do a readback to assure write has been done */ | 110 | /* Do a readback to assure write has been done */ |
| 108 | prm_read_mod_reg(WKUP_MOD, PM_WKEN); | 111 | omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN); |
| 109 | 112 | ||
| 110 | while (!(prm_read_mod_reg(WKUP_MOD, PM_WKEN) & | 113 | while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) & |
| 111 | OMAP3430_ST_IO_CHAIN_MASK)) { | 114 | OMAP3430_ST_IO_CHAIN_MASK)) { |
| 112 | timeout++; | 115 | timeout++; |
| 113 | if (timeout > 1000) { | 116 | if (timeout > 1000) { |
| @@ -115,7 +118,7 @@ static void omap3_enable_io_chain(void) | |||
| 115 | "activation failed.\n"); | 118 | "activation failed.\n"); |
| 116 | return; | 119 | return; |
| 117 | } | 120 | } |
| 118 | prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, | 121 | omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, |
| 119 | WKUP_MOD, PM_WKEN); | 122 | WKUP_MOD, PM_WKEN); |
| 120 | } | 123 | } |
| 121 | } | 124 | } |
| @@ -124,26 +127,17 @@ static void omap3_enable_io_chain(void) | |||
| 124 | static void omap3_disable_io_chain(void) | 127 | static void omap3_disable_io_chain(void) |
| 125 | { | 128 | { |
| 126 | if (omap_rev() >= OMAP3430_REV_ES3_1) | 129 | if (omap_rev() >= OMAP3430_REV_ES3_1) |
| 127 | prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, | 130 | omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, |
| 128 | PM_WKEN); | 131 | PM_WKEN); |
| 129 | } | 132 | } |
| 130 | 133 | ||
| 131 | static void omap3_core_save_context(void) | 134 | static void omap3_core_save_context(void) |
| 132 | { | 135 | { |
| 133 | u32 control_padconf_off; | 136 | omap3_ctrl_save_padconf(); |
| 134 | |||
| 135 | /* Save the padconf registers */ | ||
| 136 | control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF); | ||
| 137 | control_padconf_off |= START_PADCONF_SAVE; | ||
| 138 | omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF); | ||
| 139 | /* wait for the save to complete */ | ||
| 140 | while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) | ||
| 141 | & PADCONF_SAVE_DONE)) | ||
| 142 | udelay(1); | ||
| 143 | 137 | ||
| 144 | /* | 138 | /* |
| 145 | * Force write last pad into memory, as this can fail in some | 139 | * Force write last pad into memory, as this can fail in some |
| 146 | * cases according to erratas 1.157, 1.185 | 140 | * cases according to errata 1.157, 1.185 |
| 147 | */ | 141 | */ |
| 148 | omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), | 142 | omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), |
| 149 | OMAP343X_CONTROL_MEM_WKUP + 0x2a0); | 143 | OMAP343X_CONTROL_MEM_WKUP + 0x2a0); |
| @@ -218,27 +212,27 @@ static int prcm_clear_mod_irqs(s16 module, u8 regs) | |||
| 218 | OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; | 212 | OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; |
| 219 | int c = 0; | 213 | int c = 0; |
| 220 | 214 | ||
| 221 | wkst = prm_read_mod_reg(module, wkst_off); | 215 | wkst = omap2_prm_read_mod_reg(module, wkst_off); |
| 222 | wkst &= prm_read_mod_reg(module, grpsel_off); | 216 | wkst &= omap2_prm_read_mod_reg(module, grpsel_off); |
| 223 | if (wkst) { | 217 | if (wkst) { |
| 224 | iclk = cm_read_mod_reg(module, iclk_off); | 218 | iclk = omap2_cm_read_mod_reg(module, iclk_off); |
| 225 | fclk = cm_read_mod_reg(module, fclk_off); | 219 | fclk = omap2_cm_read_mod_reg(module, fclk_off); |
| 226 | while (wkst) { | 220 | while (wkst) { |
| 227 | clken = wkst; | 221 | clken = wkst; |
| 228 | cm_set_mod_reg_bits(clken, module, iclk_off); | 222 | omap2_cm_set_mod_reg_bits(clken, module, iclk_off); |
| 229 | /* | 223 | /* |
| 230 | * For USBHOST, we don't know whether HOST1 or | 224 | * For USBHOST, we don't know whether HOST1 or |
| 231 | * HOST2 woke us up, so enable both f-clocks | 225 | * HOST2 woke us up, so enable both f-clocks |
| 232 | */ | 226 | */ |
| 233 | if (module == OMAP3430ES2_USBHOST_MOD) | 227 | if (module == OMAP3430ES2_USBHOST_MOD) |
| 234 | clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; | 228 | clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; |
| 235 | cm_set_mod_reg_bits(clken, module, fclk_off); | 229 | omap2_cm_set_mod_reg_bits(clken, module, fclk_off); |
| 236 | prm_write_mod_reg(wkst, module, wkst_off); | 230 | omap2_prm_write_mod_reg(wkst, module, wkst_off); |
| 237 | wkst = prm_read_mod_reg(module, wkst_off); | 231 | wkst = omap2_prm_read_mod_reg(module, wkst_off); |
| 238 | c++; | 232 | c++; |
| 239 | } | 233 | } |
| 240 | cm_write_mod_reg(iclk, module, iclk_off); | 234 | omap2_cm_write_mod_reg(iclk, module, iclk_off); |
| 241 | cm_write_mod_reg(fclk, module, fclk_off); | 235 | omap2_cm_write_mod_reg(fclk, module, fclk_off); |
| 242 | } | 236 | } |
| 243 | 237 | ||
| 244 | return c; | 238 | return c; |
| @@ -281,9 +275,9 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) | |||
| 281 | u32 irqenable_mpu, irqstatus_mpu; | 275 | u32 irqenable_mpu, irqstatus_mpu; |
| 282 | int c = 0; | 276 | int c = 0; |
| 283 | 277 | ||
| 284 | irqenable_mpu = prm_read_mod_reg(OCP_MOD, | 278 | irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD, |
| 285 | OMAP3_PRM_IRQENABLE_MPU_OFFSET); | 279 | OMAP3_PRM_IRQENABLE_MPU_OFFSET); |
| 286 | irqstatus_mpu = prm_read_mod_reg(OCP_MOD, | 280 | irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD, |
| 287 | OMAP3_PRM_IRQSTATUS_MPU_OFFSET); | 281 | OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
| 288 | irqstatus_mpu &= irqenable_mpu; | 282 | irqstatus_mpu &= irqenable_mpu; |
| 289 | 283 | ||
| @@ -304,10 +298,10 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) | |||
| 304 | "no code to handle it (%08x)\n", irqstatus_mpu); | 298 | "no code to handle it (%08x)\n", irqstatus_mpu); |
| 305 | } | 299 | } |
| 306 | 300 | ||
| 307 | prm_write_mod_reg(irqstatus_mpu, OCP_MOD, | 301 | omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD, |
| 308 | OMAP3_PRM_IRQSTATUS_MPU_OFFSET); | 302 | OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
| 309 | 303 | ||
| 310 | irqstatus_mpu = prm_read_mod_reg(OCP_MOD, | 304 | irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD, |
| 311 | OMAP3_PRM_IRQSTATUS_MPU_OFFSET); | 305 | OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
| 312 | irqstatus_mpu &= irqenable_mpu; | 306 | irqstatus_mpu &= irqenable_mpu; |
| 313 | 307 | ||
| @@ -357,6 +351,7 @@ void omap_sram_idle(void) | |||
| 357 | int mpu_next_state = PWRDM_POWER_ON; | 351 | int mpu_next_state = PWRDM_POWER_ON; |
| 358 | int per_next_state = PWRDM_POWER_ON; | 352 | int per_next_state = PWRDM_POWER_ON; |
| 359 | int core_next_state = PWRDM_POWER_ON; | 353 | int core_next_state = PWRDM_POWER_ON; |
| 354 | int per_going_off; | ||
| 360 | int core_prev_state, per_prev_state; | 355 | int core_prev_state, per_prev_state; |
| 361 | u32 sdrc_pwr = 0; | 356 | u32 sdrc_pwr = 0; |
| 362 | 357 | ||
| @@ -395,7 +390,7 @@ void omap_sram_idle(void) | |||
| 395 | if (omap3_has_io_wakeup() && | 390 | if (omap3_has_io_wakeup() && |
| 396 | (per_next_state < PWRDM_POWER_ON || | 391 | (per_next_state < PWRDM_POWER_ON || |
| 397 | core_next_state < PWRDM_POWER_ON)) { | 392 | core_next_state < PWRDM_POWER_ON)) { |
| 398 | prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); | 393 | omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); |
| 399 | omap3_enable_io_chain(); | 394 | omap3_enable_io_chain(); |
| 400 | } | 395 | } |
| 401 | 396 | ||
| @@ -408,9 +403,10 @@ void omap_sram_idle(void) | |||
| 408 | 403 | ||
| 409 | /* PER */ | 404 | /* PER */ |
| 410 | if (per_next_state < PWRDM_POWER_ON) { | 405 | if (per_next_state < PWRDM_POWER_ON) { |
| 406 | per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0; | ||
| 411 | omap_uart_prepare_idle(2); | 407 | omap_uart_prepare_idle(2); |
| 412 | omap_uart_prepare_idle(3); | 408 | omap_uart_prepare_idle(3); |
| 413 | omap2_gpio_prepare_for_idle(per_next_state); | 409 | omap2_gpio_prepare_for_idle(per_going_off); |
| 414 | if (per_next_state == PWRDM_POWER_OFF) | 410 | if (per_next_state == PWRDM_POWER_OFF) |
| 415 | omap3_per_save_context(); | 411 | omap3_per_save_context(); |
| 416 | } | 412 | } |
| @@ -421,7 +417,7 @@ void omap_sram_idle(void) | |||
| 421 | omap_uart_prepare_idle(1); | 417 | omap_uart_prepare_idle(1); |
| 422 | if (core_next_state == PWRDM_POWER_OFF) { | 418 | if (core_next_state == PWRDM_POWER_OFF) { |
| 423 | omap3_core_save_context(); | 419 | omap3_core_save_context(); |
| 424 | omap3_prcm_save_context(); | 420 | omap3_cm_save_context(); |
| 425 | } | 421 | } |
| 426 | } | 422 | } |
| 427 | 423 | ||
| @@ -430,7 +426,7 @@ void omap_sram_idle(void) | |||
| 430 | /* | 426 | /* |
| 431 | * On EMU/HS devices ROM code restores a SRDC value | 427 | * On EMU/HS devices ROM code restores a SRDC value |
| 432 | * from scratchpad which has automatic self refresh on timeout | 428 | * from scratchpad which has automatic self refresh on timeout |
| 433 | * of AUTO_CNT = 1 enabled. This takes care of errata 1.142. | 429 | * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443. |
| 434 | * Hence store/restore the SDRC_POWER register here. | 430 | * Hence store/restore the SDRC_POWER register here. |
| 435 | */ | 431 | */ |
| 436 | if (omap_rev() >= OMAP3430_REV_ES3_0 && | 432 | if (omap_rev() >= OMAP3430_REV_ES3_0 && |
| @@ -461,14 +457,14 @@ void omap_sram_idle(void) | |||
| 461 | core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); | 457 | core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); |
| 462 | if (core_prev_state == PWRDM_POWER_OFF) { | 458 | if (core_prev_state == PWRDM_POWER_OFF) { |
| 463 | omap3_core_restore_context(); | 459 | omap3_core_restore_context(); |
| 464 | omap3_prcm_restore_context(); | 460 | omap3_cm_restore_context(); |
| 465 | omap3_sram_restore_context(); | 461 | omap3_sram_restore_context(); |
| 466 | omap2_sms_restore_context(); | 462 | omap2_sms_restore_context(); |
| 467 | } | 463 | } |
| 468 | omap_uart_resume_idle(0); | 464 | omap_uart_resume_idle(0); |
| 469 | omap_uart_resume_idle(1); | 465 | omap_uart_resume_idle(1); |
| 470 | if (core_next_state == PWRDM_POWER_OFF) | 466 | if (core_next_state == PWRDM_POWER_OFF) |
| 471 | prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, | 467 | omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, |
| 472 | OMAP3430_GR_MOD, | 468 | OMAP3430_GR_MOD, |
| 473 | OMAP3_PRM_VOLTCTRL_OFFSET); | 469 | OMAP3_PRM_VOLTCTRL_OFFSET); |
| 474 | } | 470 | } |
| @@ -492,7 +488,8 @@ console_still_active: | |||
| 492 | if (omap3_has_io_wakeup() && | 488 | if (omap3_has_io_wakeup() && |
| 493 | (per_next_state < PWRDM_POWER_ON || | 489 | (per_next_state < PWRDM_POWER_ON || |
| 494 | core_next_state < PWRDM_POWER_ON)) { | 490 | core_next_state < PWRDM_POWER_ON)) { |
| 495 | prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); | 491 | omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, |
| 492 | PM_WKEN); | ||
| 496 | omap3_disable_io_chain(); | 493 | omap3_disable_io_chain(); |
| 497 | } | 494 | } |
| 498 | 495 | ||
| @@ -529,12 +526,6 @@ out: | |||
| 529 | } | 526 | } |
| 530 | 527 | ||
| 531 | #ifdef CONFIG_SUSPEND | 528 | #ifdef CONFIG_SUSPEND |
| 532 | static int omap3_pm_prepare(void) | ||
| 533 | { | ||
| 534 | disable_hlt(); | ||
| 535 | return 0; | ||
| 536 | } | ||
| 537 | |||
| 538 | static int omap3_pm_suspend(void) | 529 | static int omap3_pm_suspend(void) |
| 539 | { | 530 | { |
| 540 | struct power_state *pwrst; | 531 | struct power_state *pwrst; |
| @@ -597,14 +588,10 @@ static int omap3_pm_enter(suspend_state_t unused) | |||
| 597 | return ret; | 588 | return ret; |
| 598 | } | 589 | } |
| 599 | 590 | ||
| 600 | static void omap3_pm_finish(void) | ||
| 601 | { | ||
| 602 | enable_hlt(); | ||
| 603 | } | ||
| 604 | |||
| 605 | /* Hooks to enable / disable UART interrupts during suspend */ | 591 | /* Hooks to enable / disable UART interrupts during suspend */ |
| 606 | static int omap3_pm_begin(suspend_state_t state) | 592 | static int omap3_pm_begin(suspend_state_t state) |
| 607 | { | 593 | { |
| 594 | disable_hlt(); | ||
| 608 | suspend_state = state; | 595 | suspend_state = state; |
| 609 | omap_uart_enable_irqs(0); | 596 | omap_uart_enable_irqs(0); |
| 610 | return 0; | 597 | return 0; |
| @@ -614,15 +601,14 @@ static void omap3_pm_end(void) | |||
| 614 | { | 601 | { |
| 615 | suspend_state = PM_SUSPEND_ON; | 602 | suspend_state = PM_SUSPEND_ON; |
| 616 | omap_uart_enable_irqs(1); | 603 | omap_uart_enable_irqs(1); |
| 604 | enable_hlt(); | ||
| 617 | return; | 605 | return; |
| 618 | } | 606 | } |
| 619 | 607 | ||
| 620 | static struct platform_suspend_ops omap_pm_ops = { | 608 | static struct platform_suspend_ops omap_pm_ops = { |
| 621 | .begin = omap3_pm_begin, | 609 | .begin = omap3_pm_begin, |
| 622 | .end = omap3_pm_end, | 610 | .end = omap3_pm_end, |
| 623 | .prepare = omap3_pm_prepare, | ||
| 624 | .enter = omap3_pm_enter, | 611 | .enter = omap3_pm_enter, |
| 625 | .finish = omap3_pm_finish, | ||
| 626 | .valid = suspend_valid_only_mem, | 612 | .valid = suspend_valid_only_mem, |
| 627 | }; | 613 | }; |
| 628 | #endif /* CONFIG_SUSPEND */ | 614 | #endif /* CONFIG_SUSPEND */ |
| @@ -641,21 +627,21 @@ static struct platform_suspend_ops omap_pm_ops = { | |||
| 641 | static void __init omap3_iva_idle(void) | 627 | static void __init omap3_iva_idle(void) |
| 642 | { | 628 | { |
| 643 | /* ensure IVA2 clock is disabled */ | 629 | /* ensure IVA2 clock is disabled */ |
| 644 | cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); | 630 | omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); |
| 645 | 631 | ||
| 646 | /* if no clock activity, nothing else to do */ | 632 | /* if no clock activity, nothing else to do */ |
| 647 | if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & | 633 | if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & |
| 648 | OMAP3430_CLKACTIVITY_IVA2_MASK)) | 634 | OMAP3430_CLKACTIVITY_IVA2_MASK)) |
| 649 | return; | 635 | return; |
| 650 | 636 | ||
| 651 | /* Reset IVA2 */ | 637 | /* Reset IVA2 */ |
| 652 | prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | | 638 | omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | |
| 653 | OMAP3430_RST2_IVA2_MASK | | 639 | OMAP3430_RST2_IVA2_MASK | |
| 654 | OMAP3430_RST3_IVA2_MASK, | 640 | OMAP3430_RST3_IVA2_MASK, |
| 655 | OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); | 641 | OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); |
| 656 | 642 | ||
| 657 | /* Enable IVA2 clock */ | 643 | /* Enable IVA2 clock */ |
| 658 | cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, | 644 | omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, |
| 659 | OMAP3430_IVA2_MOD, CM_FCLKEN); | 645 | OMAP3430_IVA2_MOD, CM_FCLKEN); |
| 660 | 646 | ||
| 661 | /* Set IVA2 boot mode to 'idle' */ | 647 | /* Set IVA2 boot mode to 'idle' */ |
| @@ -663,13 +649,13 @@ static void __init omap3_iva_idle(void) | |||
| 663 | OMAP343X_CONTROL_IVA2_BOOTMOD); | 649 | OMAP343X_CONTROL_IVA2_BOOTMOD); |
| 664 | 650 | ||
| 665 | /* Un-reset IVA2 */ | 651 | /* Un-reset IVA2 */ |
| 666 | prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); | 652 | omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); |
| 667 | 653 | ||
| 668 | /* Disable IVA2 clock */ | 654 | /* Disable IVA2 clock */ |
| 669 | cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); | 655 | omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); |
| 670 | 656 | ||
| 671 | /* Reset IVA2 */ | 657 | /* Reset IVA2 */ |
| 672 | prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | | 658 | omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | |
| 673 | OMAP3430_RST2_IVA2_MASK | | 659 | OMAP3430_RST2_IVA2_MASK | |
| 674 | OMAP3430_RST3_IVA2_MASK, | 660 | OMAP3430_RST3_IVA2_MASK, |
| 675 | OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); | 661 | OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); |
| @@ -693,10 +679,10 @@ static void __init omap3_d2d_idle(void) | |||
| 693 | omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); | 679 | omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); |
| 694 | 680 | ||
| 695 | /* reset modem */ | 681 | /* reset modem */ |
| 696 | prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | | 682 | omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | |
| 697 | OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, | 683 | OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, |
| 698 | CORE_MOD, OMAP2_RM_RSTCTRL); | 684 | CORE_MOD, OMAP2_RM_RSTCTRL); |
| 699 | prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); | 685 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); |
| 700 | } | 686 | } |
| 701 | 687 | ||
| 702 | static void __init prcm_setup_regs(void) | 688 | static void __init prcm_setup_regs(void) |
| @@ -711,23 +697,23 @@ static void __init prcm_setup_regs(void) | |||
| 711 | 697 | ||
| 712 | /* XXX Reset all wkdeps. This should be done when initializing | 698 | /* XXX Reset all wkdeps. This should be done when initializing |
| 713 | * powerdomains */ | 699 | * powerdomains */ |
| 714 | prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); | 700 | omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); |
| 715 | prm_write_mod_reg(0, MPU_MOD, PM_WKDEP); | 701 | omap2_prm_write_mod_reg(0, MPU_MOD, PM_WKDEP); |
| 716 | prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP); | 702 | omap2_prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP); |
| 717 | prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP); | 703 | omap2_prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP); |
| 718 | prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP); | 704 | omap2_prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP); |
| 719 | prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP); | 705 | omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP); |
| 720 | if (omap_rev() > OMAP3430_REV_ES1_0) { | 706 | if (omap_rev() > OMAP3430_REV_ES1_0) { |
| 721 | prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP); | 707 | omap2_prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP); |
| 722 | prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP); | 708 | omap2_prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP); |
| 723 | } else | 709 | } else |
| 724 | prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); | 710 | omap2_prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); |
| 725 | 711 | ||
| 726 | /* | 712 | /* |
| 727 | * Enable interface clock autoidle for all modules. | 713 | * Enable interface clock autoidle for all modules. |
| 728 | * Note that in the long run this should be done by clockfw | 714 | * Note that in the long run this should be done by clockfw |
| 729 | */ | 715 | */ |
| 730 | cm_write_mod_reg( | 716 | omap2_cm_write_mod_reg( |
| 731 | OMAP3430_AUTO_MODEM_MASK | | 717 | OMAP3430_AUTO_MODEM_MASK | |
| 732 | OMAP3430ES2_AUTO_MMC3_MASK | | 718 | OMAP3430ES2_AUTO_MMC3_MASK | |
| 733 | OMAP3430ES2_AUTO_ICR_MASK | | 719 | OMAP3430ES2_AUTO_ICR_MASK | |
| @@ -760,7 +746,7 @@ static void __init prcm_setup_regs(void) | |||
| 760 | OMAP3430_AUTO_SSI_MASK, | 746 | OMAP3430_AUTO_SSI_MASK, |
| 761 | CORE_MOD, CM_AUTOIDLE1); | 747 | CORE_MOD, CM_AUTOIDLE1); |
| 762 | 748 | ||
| 763 | cm_write_mod_reg( | 749 | omap2_cm_write_mod_reg( |
| 764 | OMAP3430_AUTO_PKA_MASK | | 750 | OMAP3430_AUTO_PKA_MASK | |
| 765 | OMAP3430_AUTO_AES1_MASK | | 751 | OMAP3430_AUTO_AES1_MASK | |
| 766 | OMAP3430_AUTO_RNG_MASK | | 752 | OMAP3430_AUTO_RNG_MASK | |
| @@ -769,13 +755,13 @@ static void __init prcm_setup_regs(void) | |||
| 769 | CORE_MOD, CM_AUTOIDLE2); | 755 | CORE_MOD, CM_AUTOIDLE2); |
| 770 | 756 | ||
| 771 | if (omap_rev() > OMAP3430_REV_ES1_0) { | 757 | if (omap_rev() > OMAP3430_REV_ES1_0) { |
| 772 | cm_write_mod_reg( | 758 | omap2_cm_write_mod_reg( |
| 773 | OMAP3430_AUTO_MAD2D_MASK | | 759 | OMAP3430_AUTO_MAD2D_MASK | |
| 774 | OMAP3430ES2_AUTO_USBTLL_MASK, | 760 | OMAP3430ES2_AUTO_USBTLL_MASK, |
| 775 | CORE_MOD, CM_AUTOIDLE3); | 761 | CORE_MOD, CM_AUTOIDLE3); |
| 776 | } | 762 | } |
| 777 | 763 | ||
| 778 | cm_write_mod_reg( | 764 | omap2_cm_write_mod_reg( |
| 779 | OMAP3430_AUTO_WDT2_MASK | | 765 | OMAP3430_AUTO_WDT2_MASK | |
| 780 | OMAP3430_AUTO_WDT1_MASK | | 766 | OMAP3430_AUTO_WDT1_MASK | |
| 781 | OMAP3430_AUTO_GPIO1_MASK | | 767 | OMAP3430_AUTO_GPIO1_MASK | |
| @@ -784,17 +770,17 @@ static void __init prcm_setup_regs(void) | |||
| 784 | OMAP3430_AUTO_GPT1_MASK, | 770 | OMAP3430_AUTO_GPT1_MASK, |
| 785 | WKUP_MOD, CM_AUTOIDLE); | 771 | WKUP_MOD, CM_AUTOIDLE); |
| 786 | 772 | ||
| 787 | cm_write_mod_reg( | 773 | omap2_cm_write_mod_reg( |
| 788 | OMAP3430_AUTO_DSS_MASK, | 774 | OMAP3430_AUTO_DSS_MASK, |
| 789 | OMAP3430_DSS_MOD, | 775 | OMAP3430_DSS_MOD, |
| 790 | CM_AUTOIDLE); | 776 | CM_AUTOIDLE); |
| 791 | 777 | ||
| 792 | cm_write_mod_reg( | 778 | omap2_cm_write_mod_reg( |
| 793 | OMAP3430_AUTO_CAM_MASK, | 779 | OMAP3430_AUTO_CAM_MASK, |
| 794 | OMAP3430_CAM_MOD, | 780 | OMAP3430_CAM_MOD, |
| 795 | CM_AUTOIDLE); | 781 | CM_AUTOIDLE); |
| 796 | 782 | ||
| 797 | cm_write_mod_reg( | 783 | omap2_cm_write_mod_reg( |
| 798 | omap3630_auto_uart4_mask | | 784 | omap3630_auto_uart4_mask | |
| 799 | OMAP3430_AUTO_GPIO6_MASK | | 785 | OMAP3430_AUTO_GPIO6_MASK | |
| 800 | OMAP3430_AUTO_GPIO5_MASK | | 786 | OMAP3430_AUTO_GPIO5_MASK | |
| @@ -818,7 +804,7 @@ static void __init prcm_setup_regs(void) | |||
| 818 | CM_AUTOIDLE); | 804 | CM_AUTOIDLE); |
| 819 | 805 | ||
| 820 | if (omap_rev() > OMAP3430_REV_ES1_0) { | 806 | if (omap_rev() > OMAP3430_REV_ES1_0) { |
| 821 | cm_write_mod_reg( | 807 | omap2_cm_write_mod_reg( |
| 822 | OMAP3430ES2_AUTO_USBHOST_MASK, | 808 | OMAP3430ES2_AUTO_USBHOST_MASK, |
| 823 | OMAP3430ES2_USBHOST_MOD, | 809 | OMAP3430ES2_USBHOST_MOD, |
| 824 | CM_AUTOIDLE); | 810 | CM_AUTOIDLE); |
| @@ -830,16 +816,16 @@ static void __init prcm_setup_regs(void) | |||
| 830 | * Set all plls to autoidle. This is needed until autoidle is | 816 | * Set all plls to autoidle. This is needed until autoidle is |
| 831 | * enabled by clockfw | 817 | * enabled by clockfw |
| 832 | */ | 818 | */ |
| 833 | cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, | 819 | omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, |
| 834 | OMAP3430_IVA2_MOD, CM_AUTOIDLE2); | 820 | OMAP3430_IVA2_MOD, CM_AUTOIDLE2); |
| 835 | cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT, | 821 | omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT, |
| 836 | MPU_MOD, | 822 | MPU_MOD, |
| 837 | CM_AUTOIDLE2); | 823 | CM_AUTOIDLE2); |
| 838 | cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | | 824 | omap2_cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | |
| 839 | (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT), | 825 | (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT), |
| 840 | PLL_MOD, | 826 | PLL_MOD, |
| 841 | CM_AUTOIDLE); | 827 | CM_AUTOIDLE); |
| 842 | cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, | 828 | omap2_cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, |
| 843 | PLL_MOD, | 829 | PLL_MOD, |
| 844 | CM_AUTOIDLE2); | 830 | CM_AUTOIDLE2); |
| 845 | 831 | ||
| @@ -848,31 +834,31 @@ static void __init prcm_setup_regs(void) | |||
| 848 | * sys_clkreq. In the long run clock framework should | 834 | * sys_clkreq. In the long run clock framework should |
| 849 | * take care of this. | 835 | * take care of this. |
| 850 | */ | 836 | */ |
| 851 | prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, | 837 | omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, |
| 852 | 1 << OMAP_AUTOEXTCLKMODE_SHIFT, | 838 | 1 << OMAP_AUTOEXTCLKMODE_SHIFT, |
| 853 | OMAP3430_GR_MOD, | 839 | OMAP3430_GR_MOD, |
| 854 | OMAP3_PRM_CLKSRC_CTRL_OFFSET); | 840 | OMAP3_PRM_CLKSRC_CTRL_OFFSET); |
| 855 | 841 | ||
| 856 | /* setup wakup source */ | 842 | /* setup wakup source */ |
| 857 | prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | | 843 | omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | |
| 858 | OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, | 844 | OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, |
| 859 | WKUP_MOD, PM_WKEN); | 845 | WKUP_MOD, PM_WKEN); |
| 860 | /* No need to write EN_IO, that is always enabled */ | 846 | /* No need to write EN_IO, that is always enabled */ |
| 861 | prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | | 847 | omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | |
| 862 | OMAP3430_GRPSEL_GPT1_MASK | | 848 | OMAP3430_GRPSEL_GPT1_MASK | |
| 863 | OMAP3430_GRPSEL_GPT12_MASK, | 849 | OMAP3430_GRPSEL_GPT12_MASK, |
| 864 | WKUP_MOD, OMAP3430_PM_MPUGRPSEL); | 850 | WKUP_MOD, OMAP3430_PM_MPUGRPSEL); |
| 865 | /* For some reason IO doesn't generate wakeup event even if | 851 | /* For some reason IO doesn't generate wakeup event even if |
| 866 | * it is selected to mpu wakeup goup */ | 852 | * it is selected to mpu wakeup goup */ |
| 867 | prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK, | 853 | omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK, |
| 868 | OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); | 854 | OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); |
| 869 | 855 | ||
| 870 | /* Enable PM_WKEN to support DSS LPR */ | 856 | /* Enable PM_WKEN to support DSS LPR */ |
| 871 | prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, | 857 | omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, |
| 872 | OMAP3430_DSS_MOD, PM_WKEN); | 858 | OMAP3430_DSS_MOD, PM_WKEN); |
| 873 | 859 | ||
| 874 | /* Enable wakeups in PER */ | 860 | /* Enable wakeups in PER */ |
| 875 | prm_write_mod_reg(omap3630_en_uart4_mask | | 861 | omap2_prm_write_mod_reg(omap3630_en_uart4_mask | |
| 876 | OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | | 862 | OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | |
| 877 | OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | | 863 | OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | |
| 878 | OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | | 864 | OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | |
| @@ -880,7 +866,7 @@ static void __init prcm_setup_regs(void) | |||
| 880 | OMAP3430_EN_MCBSP4_MASK, | 866 | OMAP3430_EN_MCBSP4_MASK, |
| 881 | OMAP3430_PER_MOD, PM_WKEN); | 867 | OMAP3430_PER_MOD, PM_WKEN); |
| 882 | /* and allow them to wake up MPU */ | 868 | /* and allow them to wake up MPU */ |
| 883 | prm_write_mod_reg(omap3630_grpsel_uart4_mask | | 869 | omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask | |
| 884 | OMAP3430_GRPSEL_GPIO2_MASK | | 870 | OMAP3430_GRPSEL_GPIO2_MASK | |
| 885 | OMAP3430_GRPSEL_GPIO3_MASK | | 871 | OMAP3430_GRPSEL_GPIO3_MASK | |
| 886 | OMAP3430_GRPSEL_GPIO4_MASK | | 872 | OMAP3430_GRPSEL_GPIO4_MASK | |
| @@ -893,22 +879,22 @@ static void __init prcm_setup_regs(void) | |||
| 893 | OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); | 879 | OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); |
| 894 | 880 | ||
| 895 | /* Don't attach IVA interrupts */ | 881 | /* Don't attach IVA interrupts */ |
| 896 | prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); | 882 | omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); |
| 897 | prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); | 883 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); |
| 898 | prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); | 884 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); |
| 899 | prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); | 885 | omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); |
| 900 | 886 | ||
| 901 | /* Clear any pending 'reset' flags */ | 887 | /* Clear any pending 'reset' flags */ |
| 902 | prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); | 888 | omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); |
| 903 | prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); | 889 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); |
| 904 | prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); | 890 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); |
| 905 | prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); | 891 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); |
| 906 | prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); | 892 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); |
| 907 | prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); | 893 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); |
| 908 | prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); | 894 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); |
| 909 | 895 | ||
| 910 | /* Clear any pending PRCM interrupts */ | 896 | /* Clear any pending PRCM interrupts */ |
| 911 | prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); | 897 | omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
| 912 | 898 | ||
| 913 | omap3_iva_idle(); | 899 | omap3_iva_idle(); |
| 914 | omap3_d2d_idle(); | 900 | omap3_d2d_idle(); |
| @@ -925,12 +911,29 @@ void omap3_pm_off_mode_enable(int enable) | |||
| 925 | state = PWRDM_POWER_RET; | 911 | state = PWRDM_POWER_RET; |
| 926 | 912 | ||
| 927 | #ifdef CONFIG_CPU_IDLE | 913 | #ifdef CONFIG_CPU_IDLE |
| 928 | omap3_cpuidle_update_states(); | 914 | /* |
| 915 | * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot | ||
| 916 | * enable OFF mode in a stable form for previous revisions, restrict | ||
| 917 | * instead to RET | ||
| 918 | */ | ||
| 919 | if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) | ||
| 920 | omap3_cpuidle_update_states(state, PWRDM_POWER_RET); | ||
| 921 | else | ||
| 922 | omap3_cpuidle_update_states(state, state); | ||
| 929 | #endif | 923 | #endif |
| 930 | 924 | ||
| 931 | list_for_each_entry(pwrst, &pwrst_list, node) { | 925 | list_for_each_entry(pwrst, &pwrst_list, node) { |
| 932 | pwrst->next_state = state; | 926 | if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) && |
| 933 | omap_set_pwrdm_state(pwrst->pwrdm, state); | 927 | pwrst->pwrdm == core_pwrdm && |
| 928 | state == PWRDM_POWER_OFF) { | ||
| 929 | pwrst->next_state = PWRDM_POWER_RET; | ||
| 930 | WARN_ONCE(1, | ||
| 931 | "%s: Core OFF disabled due to errata i583\n", | ||
| 932 | __func__); | ||
| 933 | } else { | ||
| 934 | pwrst->next_state = state; | ||
| 935 | } | ||
| 936 | omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); | ||
| 934 | } | 937 | } |
| 935 | } | 938 | } |
| 936 | 939 | ||
| @@ -1002,6 +1005,17 @@ void omap_push_sram_idle(void) | |||
| 1002 | save_secure_ram_context_sz); | 1005 | save_secure_ram_context_sz); |
| 1003 | } | 1006 | } |
| 1004 | 1007 | ||
| 1008 | static void __init pm_errata_configure(void) | ||
| 1009 | { | ||
| 1010 | if (cpu_is_omap3630()) { | ||
| 1011 | pm34xx_errata |= PM_RTA_ERRATUM_i608; | ||
| 1012 | /* Enable the l2 cache toggling in sleep logic */ | ||
| 1013 | enable_omap3630_toggle_l2_on_restore(); | ||
| 1014 | if (omap_rev() < OMAP3630_REV_ES1_2) | ||
| 1015 | pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583; | ||
| 1016 | } | ||
| 1017 | } | ||
| 1018 | |||
| 1005 | static int __init omap3_pm_init(void) | 1019 | static int __init omap3_pm_init(void) |
| 1006 | { | 1020 | { |
| 1007 | struct power_state *pwrst, *tmp; | 1021 | struct power_state *pwrst, *tmp; |
| @@ -1011,6 +1025,8 @@ static int __init omap3_pm_init(void) | |||
| 1011 | if (!cpu_is_omap34xx()) | 1025 | if (!cpu_is_omap34xx()) |
| 1012 | return -ENODEV; | 1026 | return -ENODEV; |
| 1013 | 1027 | ||
| 1028 | pm_errata_configure(); | ||
| 1029 | |||
| 1014 | printk(KERN_ERR "Power Management for TI OMAP3.\n"); | 1030 | printk(KERN_ERR "Power Management for TI OMAP3.\n"); |
| 1015 | 1031 | ||
| 1016 | /* XXX prcm_setup_regs needs to be before enabling hw | 1032 | /* XXX prcm_setup_regs needs to be before enabling hw |
| @@ -1058,6 +1074,14 @@ static int __init omap3_pm_init(void) | |||
| 1058 | pm_idle = omap3_pm_idle; | 1074 | pm_idle = omap3_pm_idle; |
| 1059 | omap3_idle_init(); | 1075 | omap3_idle_init(); |
| 1060 | 1076 | ||
| 1077 | /* | ||
| 1078 | * RTA is disabled during initialization as per erratum i608 | ||
| 1079 | * it is safer to disable RTA by the bootloader, but we would like | ||
| 1080 | * to be doubly sure here and prevent any mishaps. | ||
| 1081 | */ | ||
| 1082 | if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608)) | ||
| 1083 | omap3630_ctrl_disable_rta(); | ||
| 1084 | |||
| 1061 | clkdm_add_wkdep(neon_clkdm, mpu_clkdm); | 1085 | clkdm_add_wkdep(neon_clkdm, mpu_clkdm); |
| 1062 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { | 1086 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { |
| 1063 | omap3_secure_ram_storage = | 1087 | omap3_secure_ram_storage = |
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c index 54544b4fc76b..e9f4862c4de4 100644 --- a/arch/arm/mach-omap2/pm44xx.c +++ b/arch/arm/mach-omap2/pm44xx.c | |||
| @@ -16,7 +16,7 @@ | |||
| 16 | #include <linux/err.h> | 16 | #include <linux/err.h> |
| 17 | #include <linux/slab.h> | 17 | #include <linux/slab.h> |
| 18 | 18 | ||
| 19 | #include <plat/powerdomain.h> | 19 | #include "powerdomain.h" |
| 20 | #include <mach/omap4-common.h> | 20 | #include <mach/omap4-common.h> |
| 21 | 21 | ||
| 22 | struct power_state { | 22 | struct power_state { |
| @@ -31,12 +31,6 @@ struct power_state { | |||
| 31 | static LIST_HEAD(pwrst_list); | 31 | static LIST_HEAD(pwrst_list); |
| 32 | 32 | ||
| 33 | #ifdef CONFIG_SUSPEND | 33 | #ifdef CONFIG_SUSPEND |
| 34 | static int omap4_pm_prepare(void) | ||
| 35 | { | ||
| 36 | disable_hlt(); | ||
| 37 | return 0; | ||
| 38 | } | ||
| 39 | |||
| 40 | static int omap4_pm_suspend(void) | 34 | static int omap4_pm_suspend(void) |
| 41 | { | 35 | { |
| 42 | do_wfi(); | 36 | do_wfi(); |
| @@ -59,28 +53,22 @@ static int omap4_pm_enter(suspend_state_t suspend_state) | |||
| 59 | return ret; | 53 | return ret; |
| 60 | } | 54 | } |
| 61 | 55 | ||
| 62 | static void omap4_pm_finish(void) | ||
| 63 | { | ||
| 64 | enable_hlt(); | ||
| 65 | return; | ||
| 66 | } | ||
| 67 | |||
| 68 | static int omap4_pm_begin(suspend_state_t state) | 56 | static int omap4_pm_begin(suspend_state_t state) |
| 69 | { | 57 | { |
| 58 | disable_hlt(); | ||
| 70 | return 0; | 59 | return 0; |
| 71 | } | 60 | } |
| 72 | 61 | ||
| 73 | static void omap4_pm_end(void) | 62 | static void omap4_pm_end(void) |
| 74 | { | 63 | { |
| 64 | enable_hlt(); | ||
| 75 | return; | 65 | return; |
| 76 | } | 66 | } |
| 77 | 67 | ||
| 78 | static struct platform_suspend_ops omap_pm_ops = { | 68 | static struct platform_suspend_ops omap_pm_ops = { |
| 79 | .begin = omap4_pm_begin, | 69 | .begin = omap4_pm_begin, |
| 80 | .end = omap4_pm_end, | 70 | .end = omap4_pm_end, |
| 81 | .prepare = omap4_pm_prepare, | ||
| 82 | .enter = omap4_pm_enter, | 71 | .enter = omap4_pm_enter, |
| 83 | .finish = omap4_pm_finish, | ||
| 84 | .valid = suspend_valid_only_mem, | 72 | .valid = suspend_valid_only_mem, |
| 85 | }; | 73 | }; |
| 86 | #endif /* CONFIG_SUSPEND */ | 74 | #endif /* CONFIG_SUSPEND */ |
diff --git a/arch/arm/mach-omap2/powerdomain-common.c b/arch/arm/mach-omap2/powerdomain-common.c new file mode 100644 index 000000000000..171fccd208c7 --- /dev/null +++ b/arch/arm/mach-omap2/powerdomain-common.c | |||
| @@ -0,0 +1,110 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-omap2/powerdomain-common.c | ||
| 3 | * Contains common powerdomain framework functions | ||
| 4 | * | ||
| 5 | * Copyright (C) 2010 Texas Instruments, Inc. | ||
| 6 | * Copyright (C) 2010 Nokia Corporation | ||
| 7 | * | ||
| 8 | * Derived from mach-omap2/powerdomain.c written by Paul Walmsley | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/errno.h> | ||
| 16 | #include <linux/kernel.h> | ||
| 17 | #include "pm.h" | ||
| 18 | #include "cm.h" | ||
| 19 | #include "cm-regbits-34xx.h" | ||
| 20 | #include "cm-regbits-44xx.h" | ||
| 21 | #include "prm-regbits-34xx.h" | ||
| 22 | #include "prm-regbits-44xx.h" | ||
| 23 | |||
| 24 | /* | ||
| 25 | * OMAP3 and OMAP4 specific register bit initialisations | ||
| 26 | * Notice that the names here are not according to each power | ||
| 27 | * domain but the bit mapping used applies to all of them | ||
| 28 | */ | ||
| 29 | /* OMAP3 and OMAP4 Memory Onstate Masks (common across all power domains) */ | ||
| 30 | #define OMAP_MEM0_ONSTATE_MASK OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK | ||
| 31 | #define OMAP_MEM1_ONSTATE_MASK OMAP3430_L1FLATMEMONSTATE_MASK | ||
| 32 | #define OMAP_MEM2_ONSTATE_MASK OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK | ||
| 33 | #define OMAP_MEM3_ONSTATE_MASK OMAP3430_L2FLATMEMONSTATE_MASK | ||
| 34 | #define OMAP_MEM4_ONSTATE_MASK OMAP4430_OCP_NRET_BANK_ONSTATE_MASK | ||
| 35 | |||
| 36 | /* OMAP3 and OMAP4 Memory Retstate Masks (common across all power domains) */ | ||
| 37 | #define OMAP_MEM0_RETSTATE_MASK OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK | ||
| 38 | #define OMAP_MEM1_RETSTATE_MASK OMAP3430_L1FLATMEMRETSTATE_MASK | ||
| 39 | #define OMAP_MEM2_RETSTATE_MASK OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK | ||
| 40 | #define OMAP_MEM3_RETSTATE_MASK OMAP3430_L2FLATMEMRETSTATE_MASK | ||
| 41 | #define OMAP_MEM4_RETSTATE_MASK OMAP4430_OCP_NRET_BANK_RETSTATE_MASK | ||
| 42 | |||
| 43 | /* OMAP3 and OMAP4 Memory Status bits */ | ||
| 44 | #define OMAP_MEM0_STATEST_MASK OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK | ||
| 45 | #define OMAP_MEM1_STATEST_MASK OMAP3430_L1FLATMEMSTATEST_MASK | ||
| 46 | #define OMAP_MEM2_STATEST_MASK OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK | ||
| 47 | #define OMAP_MEM3_STATEST_MASK OMAP3430_L2FLATMEMSTATEST_MASK | ||
| 48 | #define OMAP_MEM4_STATEST_MASK OMAP4430_OCP_NRET_BANK_STATEST_MASK | ||
| 49 | |||
| 50 | /* Common Internal functions used across OMAP rev's*/ | ||
| 51 | u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank) | ||
| 52 | { | ||
| 53 | switch (bank) { | ||
| 54 | case 0: | ||
| 55 | return OMAP_MEM0_ONSTATE_MASK; | ||
| 56 | case 1: | ||
| 57 | return OMAP_MEM1_ONSTATE_MASK; | ||
| 58 | case 2: | ||
| 59 | return OMAP_MEM2_ONSTATE_MASK; | ||
| 60 | case 3: | ||
| 61 | return OMAP_MEM3_ONSTATE_MASK; | ||
| 62 | case 4: | ||
| 63 | return OMAP_MEM4_ONSTATE_MASK; | ||
| 64 | default: | ||
| 65 | WARN_ON(1); /* should never happen */ | ||
| 66 | return -EEXIST; | ||
| 67 | } | ||
| 68 | return 0; | ||
| 69 | } | ||
| 70 | |||
| 71 | u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank) | ||
| 72 | { | ||
| 73 | switch (bank) { | ||
| 74 | case 0: | ||
| 75 | return OMAP_MEM0_RETSTATE_MASK; | ||
| 76 | case 1: | ||
| 77 | return OMAP_MEM1_RETSTATE_MASK; | ||
| 78 | case 2: | ||
| 79 | return OMAP_MEM2_RETSTATE_MASK; | ||
| 80 | case 3: | ||
| 81 | return OMAP_MEM3_RETSTATE_MASK; | ||
| 82 | case 4: | ||
| 83 | return OMAP_MEM4_RETSTATE_MASK; | ||
| 84 | default: | ||
| 85 | WARN_ON(1); /* should never happen */ | ||
| 86 | return -EEXIST; | ||
| 87 | } | ||
| 88 | return 0; | ||
| 89 | } | ||
| 90 | |||
| 91 | u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank) | ||
| 92 | { | ||
| 93 | switch (bank) { | ||
| 94 | case 0: | ||
| 95 | return OMAP_MEM0_STATEST_MASK; | ||
| 96 | case 1: | ||
| 97 | return OMAP_MEM1_STATEST_MASK; | ||
| 98 | case 2: | ||
| 99 | return OMAP_MEM2_STATEST_MASK; | ||
| 100 | case 3: | ||
| 101 | return OMAP_MEM3_STATEST_MASK; | ||
| 102 | case 4: | ||
| 103 | return OMAP_MEM4_STATEST_MASK; | ||
| 104 | default: | ||
| 105 | WARN_ON(1); /* should never happen */ | ||
| 106 | return -EEXIST; | ||
| 107 | } | ||
| 108 | return 0; | ||
| 109 | } | ||
| 110 | |||
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 6527ec30dc17..eaed0df16699 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c | |||
| @@ -15,27 +15,19 @@ | |||
| 15 | #undef DEBUG | 15 | #undef DEBUG |
| 16 | 16 | ||
| 17 | #include <linux/kernel.h> | 17 | #include <linux/kernel.h> |
| 18 | #include <linux/module.h> | ||
| 19 | #include <linux/types.h> | 18 | #include <linux/types.h> |
| 20 | #include <linux/delay.h> | ||
| 21 | #include <linux/spinlock.h> | ||
| 22 | #include <linux/list.h> | 19 | #include <linux/list.h> |
| 23 | #include <linux/errno.h> | 20 | #include <linux/errno.h> |
| 24 | #include <linux/err.h> | 21 | #include <linux/string.h> |
| 25 | #include <linux/io.h> | 22 | #include "cm2xxx_3xxx.h" |
| 26 | 23 | #include "prcm44xx.h" | |
| 27 | #include <asm/atomic.h> | 24 | #include "cm44xx.h" |
| 28 | 25 | #include "prm2xxx_3xxx.h" | |
| 29 | #include "cm.h" | 26 | #include "prm44xx.h" |
| 30 | #include "cm-regbits-34xx.h" | ||
| 31 | #include "cm-regbits-44xx.h" | ||
| 32 | #include "prm.h" | ||
| 33 | #include "prm-regbits-34xx.h" | ||
| 34 | #include "prm-regbits-44xx.h" | ||
| 35 | 27 | ||
| 36 | #include <plat/cpu.h> | 28 | #include <plat/cpu.h> |
| 37 | #include <plat/powerdomain.h> | 29 | #include "powerdomain.h" |
| 38 | #include <plat/clockdomain.h> | 30 | #include "clockdomain.h" |
| 39 | #include <plat/prcm.h> | 31 | #include <plat/prcm.h> |
| 40 | 32 | ||
| 41 | #include "pm.h" | 33 | #include "pm.h" |
| @@ -45,41 +37,12 @@ enum { | |||
| 45 | PWRDM_STATE_PREV, | 37 | PWRDM_STATE_PREV, |
| 46 | }; | 38 | }; |
| 47 | 39 | ||
| 48 | /* Variable holding value of the CPU dependent PWRSTCTRL Register Offset */ | ||
| 49 | static u16 pwrstctrl_reg_offs; | ||
| 50 | |||
| 51 | /* Variable holding value of the CPU dependent PWRSTST Register Offset */ | ||
| 52 | static u16 pwrstst_reg_offs; | ||
| 53 | |||
| 54 | /* OMAP3 and OMAP4 specific register bit initialisations | ||
| 55 | * Notice that the names here are not according to each power | ||
| 56 | * domain but the bit mapping used applies to all of them | ||
| 57 | */ | ||
| 58 | |||
| 59 | /* OMAP3 and OMAP4 Memory Onstate Masks (common across all power domains) */ | ||
| 60 | #define OMAP_MEM0_ONSTATE_MASK OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK | ||
| 61 | #define OMAP_MEM1_ONSTATE_MASK OMAP3430_L1FLATMEMONSTATE_MASK | ||
| 62 | #define OMAP_MEM2_ONSTATE_MASK OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK | ||
| 63 | #define OMAP_MEM3_ONSTATE_MASK OMAP3430_L2FLATMEMONSTATE_MASK | ||
| 64 | #define OMAP_MEM4_ONSTATE_MASK OMAP4430_OCP_NRET_BANK_ONSTATE_MASK | ||
| 65 | |||
| 66 | /* OMAP3 and OMAP4 Memory Retstate Masks (common across all power domains) */ | ||
| 67 | #define OMAP_MEM0_RETSTATE_MASK OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK | ||
| 68 | #define OMAP_MEM1_RETSTATE_MASK OMAP3430_L1FLATMEMRETSTATE_MASK | ||
| 69 | #define OMAP_MEM2_RETSTATE_MASK OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK | ||
| 70 | #define OMAP_MEM3_RETSTATE_MASK OMAP3430_L2FLATMEMRETSTATE_MASK | ||
| 71 | #define OMAP_MEM4_RETSTATE_MASK OMAP4430_OCP_NRET_BANK_RETSTATE_MASK | ||
| 72 | |||
| 73 | /* OMAP3 and OMAP4 Memory Status bits */ | ||
| 74 | #define OMAP_MEM0_STATEST_MASK OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK | ||
| 75 | #define OMAP_MEM1_STATEST_MASK OMAP3430_L1FLATMEMSTATEST_MASK | ||
| 76 | #define OMAP_MEM2_STATEST_MASK OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK | ||
| 77 | #define OMAP_MEM3_STATEST_MASK OMAP3430_L2FLATMEMSTATEST_MASK | ||
| 78 | #define OMAP_MEM4_STATEST_MASK OMAP4430_OCP_NRET_BANK_STATEST_MASK | ||
| 79 | 40 | ||
| 80 | /* pwrdm_list contains all registered struct powerdomains */ | 41 | /* pwrdm_list contains all registered struct powerdomains */ |
| 81 | static LIST_HEAD(pwrdm_list); | 42 | static LIST_HEAD(pwrdm_list); |
| 82 | 43 | ||
| 44 | static struct pwrdm_ops *arch_pwrdm; | ||
| 45 | |||
| 83 | /* Private functions */ | 46 | /* Private functions */ |
| 84 | 47 | ||
| 85 | static struct powerdomain *_pwrdm_lookup(const char *name) | 48 | static struct powerdomain *_pwrdm_lookup(const char *name) |
| @@ -110,12 +73,19 @@ static int _pwrdm_register(struct powerdomain *pwrdm) | |||
| 110 | { | 73 | { |
| 111 | int i; | 74 | int i; |
| 112 | 75 | ||
| 113 | if (!pwrdm) | 76 | if (!pwrdm || !pwrdm->name) |
| 114 | return -EINVAL; | 77 | return -EINVAL; |
| 115 | 78 | ||
| 116 | if (!omap_chip_is(pwrdm->omap_chip)) | 79 | if (!omap_chip_is(pwrdm->omap_chip)) |
| 117 | return -EINVAL; | 80 | return -EINVAL; |
| 118 | 81 | ||
| 82 | if (cpu_is_omap44xx() && | ||
| 83 | pwrdm->prcm_partition == OMAP4430_INVALID_PRCM_PARTITION) { | ||
| 84 | pr_err("powerdomain: %s: missing OMAP4 PRCM partition ID\n", | ||
| 85 | pwrdm->name); | ||
| 86 | return -EINVAL; | ||
| 87 | } | ||
| 88 | |||
| 119 | if (_pwrdm_lookup(pwrdm->name)) | 89 | if (_pwrdm_lookup(pwrdm->name)) |
| 120 | return -EEXIST; | 90 | return -EEXIST; |
| 121 | 91 | ||
| @@ -211,6 +181,7 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused) | |||
| 211 | /** | 181 | /** |
| 212 | * pwrdm_init - set up the powerdomain layer | 182 | * pwrdm_init - set up the powerdomain layer |
| 213 | * @pwrdm_list: array of struct powerdomain pointers to register | 183 | * @pwrdm_list: array of struct powerdomain pointers to register |
| 184 | * @custom_funcs: func pointers for arch specfic implementations | ||
| 214 | * | 185 | * |
| 215 | * Loop through the array of powerdomains @pwrdm_list, registering all | 186 | * Loop through the array of powerdomains @pwrdm_list, registering all |
| 216 | * that are available on the current CPU. If pwrdm_list is supplied | 187 | * that are available on the current CPU. If pwrdm_list is supplied |
| @@ -218,21 +189,14 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused) | |||
| 218 | * registered. No return value. XXX pwrdm_list is not really a | 189 | * registered. No return value. XXX pwrdm_list is not really a |
| 219 | * "list"; it is an array. Rename appropriately. | 190 | * "list"; it is an array. Rename appropriately. |
| 220 | */ | 191 | */ |
| 221 | void pwrdm_init(struct powerdomain **pwrdm_list) | 192 | void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs) |
| 222 | { | 193 | { |
| 223 | struct powerdomain **p = NULL; | 194 | struct powerdomain **p = NULL; |
| 224 | 195 | ||
| 225 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | 196 | if (!custom_funcs) |
| 226 | pwrstctrl_reg_offs = OMAP2_PM_PWSTCTRL; | 197 | WARN(1, "powerdomain: No custom pwrdm functions registered\n"); |
| 227 | pwrstst_reg_offs = OMAP2_PM_PWSTST; | 198 | else |
| 228 | } else if (cpu_is_omap44xx()) { | 199 | arch_pwrdm = custom_funcs; |
| 229 | pwrstctrl_reg_offs = OMAP4_PM_PWSTCTRL; | ||
| 230 | pwrstst_reg_offs = OMAP4_PM_PWSTST; | ||
| 231 | } else { | ||
| 232 | printk(KERN_ERR "Power Domain struct not supported for " \ | ||
| 233 | "this CPU\n"); | ||
| 234 | return; | ||
| 235 | } | ||
| 236 | 200 | ||
| 237 | if (pwrdm_list) { | 201 | if (pwrdm_list) { |
| 238 | for (p = pwrdm_list; *p; p++) | 202 | for (p = pwrdm_list; *p; p++) |
| @@ -431,6 +395,8 @@ int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm) | |||
| 431 | */ | 395 | */ |
| 432 | int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) | 396 | int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) |
| 433 | { | 397 | { |
| 398 | int ret = -EINVAL; | ||
| 399 | |||
| 434 | if (!pwrdm) | 400 | if (!pwrdm) |
| 435 | return -EINVAL; | 401 | return -EINVAL; |
| 436 | 402 | ||
| @@ -440,11 +406,10 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) | |||
| 440 | pr_debug("powerdomain: setting next powerstate for %s to %0x\n", | 406 | pr_debug("powerdomain: setting next powerstate for %s to %0x\n", |
| 441 | pwrdm->name, pwrst); | 407 | pwrdm->name, pwrst); |
| 442 | 408 | ||
| 443 | prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, | 409 | if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) |
| 444 | (pwrst << OMAP_POWERSTATE_SHIFT), | 410 | ret = arch_pwrdm->pwrdm_set_next_pwrst(pwrdm, pwrst); |
| 445 | pwrdm->prcm_offs, pwrstctrl_reg_offs); | ||
| 446 | 411 | ||
| 447 | return 0; | 412 | return ret; |
| 448 | } | 413 | } |
| 449 | 414 | ||
| 450 | /** | 415 | /** |
| @@ -457,11 +422,15 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) | |||
| 457 | */ | 422 | */ |
| 458 | int pwrdm_read_next_pwrst(struct powerdomain *pwrdm) | 423 | int pwrdm_read_next_pwrst(struct powerdomain *pwrdm) |
| 459 | { | 424 | { |
| 425 | int ret = -EINVAL; | ||
| 426 | |||
| 460 | if (!pwrdm) | 427 | if (!pwrdm) |
| 461 | return -EINVAL; | 428 | return -EINVAL; |
| 462 | 429 | ||
| 463 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, | 430 | if (arch_pwrdm && arch_pwrdm->pwrdm_read_next_pwrst) |
| 464 | pwrstctrl_reg_offs, OMAP_POWERSTATE_MASK); | 431 | ret = arch_pwrdm->pwrdm_read_next_pwrst(pwrdm); |
| 432 | |||
| 433 | return ret; | ||
| 465 | } | 434 | } |
| 466 | 435 | ||
| 467 | /** | 436 | /** |
| @@ -474,11 +443,15 @@ int pwrdm_read_next_pwrst(struct powerdomain *pwrdm) | |||
| 474 | */ | 443 | */ |
| 475 | int pwrdm_read_pwrst(struct powerdomain *pwrdm) | 444 | int pwrdm_read_pwrst(struct powerdomain *pwrdm) |
| 476 | { | 445 | { |
| 446 | int ret = -EINVAL; | ||
| 447 | |||
| 477 | if (!pwrdm) | 448 | if (!pwrdm) |
| 478 | return -EINVAL; | 449 | return -EINVAL; |
| 479 | 450 | ||
| 480 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, | 451 | if (arch_pwrdm && arch_pwrdm->pwrdm_read_pwrst) |
| 481 | pwrstst_reg_offs, OMAP_POWERSTATEST_MASK); | 452 | ret = arch_pwrdm->pwrdm_read_pwrst(pwrdm); |
| 453 | |||
| 454 | return ret; | ||
| 482 | } | 455 | } |
| 483 | 456 | ||
| 484 | /** | 457 | /** |
| @@ -491,11 +464,15 @@ int pwrdm_read_pwrst(struct powerdomain *pwrdm) | |||
| 491 | */ | 464 | */ |
| 492 | int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) | 465 | int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) |
| 493 | { | 466 | { |
| 467 | int ret = -EINVAL; | ||
| 468 | |||
| 494 | if (!pwrdm) | 469 | if (!pwrdm) |
| 495 | return -EINVAL; | 470 | return -EINVAL; |
| 496 | 471 | ||
| 497 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST, | 472 | if (arch_pwrdm && arch_pwrdm->pwrdm_read_prev_pwrst) |
| 498 | OMAP3430_LASTPOWERSTATEENTERED_MASK); | 473 | ret = arch_pwrdm->pwrdm_read_prev_pwrst(pwrdm); |
| 474 | |||
| 475 | return ret; | ||
| 499 | } | 476 | } |
| 500 | 477 | ||
| 501 | /** | 478 | /** |
| @@ -511,7 +488,7 @@ int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) | |||
| 511 | */ | 488 | */ |
| 512 | int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) | 489 | int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) |
| 513 | { | 490 | { |
| 514 | u32 v; | 491 | int ret = -EINVAL; |
| 515 | 492 | ||
| 516 | if (!pwrdm) | 493 | if (!pwrdm) |
| 517 | return -EINVAL; | 494 | return -EINVAL; |
| @@ -522,17 +499,10 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) | |||
| 522 | pr_debug("powerdomain: setting next logic powerstate for %s to %0x\n", | 499 | pr_debug("powerdomain: setting next logic powerstate for %s to %0x\n", |
| 523 | pwrdm->name, pwrst); | 500 | pwrdm->name, pwrst); |
| 524 | 501 | ||
| 525 | /* | 502 | if (arch_pwrdm && arch_pwrdm->pwrdm_set_logic_retst) |
| 526 | * The register bit names below may not correspond to the | 503 | ret = arch_pwrdm->pwrdm_set_logic_retst(pwrdm, pwrst); |
| 527 | * actual names of the bits in each powerdomain's register, | ||
| 528 | * but the type of value returned is the same for each | ||
| 529 | * powerdomain. | ||
| 530 | */ | ||
| 531 | v = pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE_MASK); | ||
| 532 | prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE_MASK, v, | ||
| 533 | pwrdm->prcm_offs, pwrstctrl_reg_offs); | ||
| 534 | 504 | ||
| 535 | return 0; | 505 | return ret; |
| 536 | } | 506 | } |
| 537 | 507 | ||
| 538 | /** | 508 | /** |
| @@ -552,7 +522,7 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) | |||
| 552 | */ | 522 | */ |
| 553 | int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) | 523 | int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) |
| 554 | { | 524 | { |
| 555 | u32 m; | 525 | int ret = -EINVAL; |
| 556 | 526 | ||
| 557 | if (!pwrdm) | 527 | if (!pwrdm) |
| 558 | return -EINVAL; | 528 | return -EINVAL; |
| @@ -566,37 +536,10 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) | |||
| 566 | pr_debug("powerdomain: setting next memory powerstate for domain %s " | 536 | pr_debug("powerdomain: setting next memory powerstate for domain %s " |
| 567 | "bank %0x while pwrdm-ON to %0x\n", pwrdm->name, bank, pwrst); | 537 | "bank %0x while pwrdm-ON to %0x\n", pwrdm->name, bank, pwrst); |
| 568 | 538 | ||
| 569 | /* | 539 | if (arch_pwrdm && arch_pwrdm->pwrdm_set_mem_onst) |
| 570 | * The register bit names below may not correspond to the | 540 | ret = arch_pwrdm->pwrdm_set_mem_onst(pwrdm, bank, pwrst); |
| 571 | * actual names of the bits in each powerdomain's register, | ||
| 572 | * but the type of value returned is the same for each | ||
| 573 | * powerdomain. | ||
| 574 | */ | ||
| 575 | switch (bank) { | ||
| 576 | case 0: | ||
| 577 | m = OMAP_MEM0_ONSTATE_MASK; | ||
| 578 | break; | ||
| 579 | case 1: | ||
| 580 | m = OMAP_MEM1_ONSTATE_MASK; | ||
| 581 | break; | ||
| 582 | case 2: | ||
| 583 | m = OMAP_MEM2_ONSTATE_MASK; | ||
| 584 | break; | ||
| 585 | case 3: | ||
| 586 | m = OMAP_MEM3_ONSTATE_MASK; | ||
| 587 | break; | ||
| 588 | case 4: | ||
| 589 | m = OMAP_MEM4_ONSTATE_MASK; | ||
| 590 | break; | ||
| 591 | default: | ||
| 592 | WARN_ON(1); /* should never happen */ | ||
| 593 | return -EEXIST; | ||
| 594 | } | ||
| 595 | 541 | ||
| 596 | prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), | 542 | return ret; |
| 597 | pwrdm->prcm_offs, pwrstctrl_reg_offs); | ||
| 598 | |||
| 599 | return 0; | ||
| 600 | } | 543 | } |
| 601 | 544 | ||
| 602 | /** | 545 | /** |
| @@ -617,7 +560,7 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) | |||
| 617 | */ | 560 | */ |
| 618 | int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) | 561 | int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) |
| 619 | { | 562 | { |
| 620 | u32 m; | 563 | int ret = -EINVAL; |
| 621 | 564 | ||
| 622 | if (!pwrdm) | 565 | if (!pwrdm) |
| 623 | return -EINVAL; | 566 | return -EINVAL; |
| @@ -631,37 +574,10 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) | |||
| 631 | pr_debug("powerdomain: setting next memory powerstate for domain %s " | 574 | pr_debug("powerdomain: setting next memory powerstate for domain %s " |
| 632 | "bank %0x while pwrdm-RET to %0x\n", pwrdm->name, bank, pwrst); | 575 | "bank %0x while pwrdm-RET to %0x\n", pwrdm->name, bank, pwrst); |
| 633 | 576 | ||
| 634 | /* | 577 | if (arch_pwrdm && arch_pwrdm->pwrdm_set_mem_retst) |
| 635 | * The register bit names below may not correspond to the | 578 | ret = arch_pwrdm->pwrdm_set_mem_retst(pwrdm, bank, pwrst); |
| 636 | * actual names of the bits in each powerdomain's register, | ||
| 637 | * but the type of value returned is the same for each | ||
| 638 | * powerdomain. | ||
| 639 | */ | ||
| 640 | switch (bank) { | ||
| 641 | case 0: | ||
| 642 | m = OMAP_MEM0_RETSTATE_MASK; | ||
| 643 | break; | ||
| 644 | case 1: | ||
| 645 | m = OMAP_MEM1_RETSTATE_MASK; | ||
| 646 | break; | ||
| 647 | case 2: | ||
| 648 | m = OMAP_MEM2_RETSTATE_MASK; | ||
| 649 | break; | ||
| 650 | case 3: | ||
| 651 | m = OMAP_MEM3_RETSTATE_MASK; | ||
| 652 | break; | ||
| 653 | case 4: | ||
| 654 | m = OMAP_MEM4_RETSTATE_MASK; | ||
| 655 | break; | ||
| 656 | default: | ||
| 657 | WARN_ON(1); /* should never happen */ | ||
| 658 | return -EEXIST; | ||
| 659 | } | ||
| 660 | |||
| 661 | prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, | ||
| 662 | pwrstctrl_reg_offs); | ||
| 663 | 579 | ||
| 664 | return 0; | 580 | return ret; |
| 665 | } | 581 | } |
| 666 | 582 | ||
| 667 | /** | 583 | /** |
| @@ -675,11 +591,15 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) | |||
| 675 | */ | 591 | */ |
| 676 | int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) | 592 | int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) |
| 677 | { | 593 | { |
| 594 | int ret = -EINVAL; | ||
| 595 | |||
| 678 | if (!pwrdm) | 596 | if (!pwrdm) |
| 679 | return -EINVAL; | 597 | return -EINVAL; |
| 680 | 598 | ||
| 681 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, pwrstst_reg_offs, | 599 | if (arch_pwrdm && arch_pwrdm->pwrdm_read_logic_pwrst) |
| 682 | OMAP3430_LOGICSTATEST_MASK); | 600 | ret = arch_pwrdm->pwrdm_read_logic_pwrst(pwrdm); |
| 601 | |||
| 602 | return ret; | ||
| 683 | } | 603 | } |
| 684 | 604 | ||
| 685 | /** | 605 | /** |
| @@ -692,17 +612,15 @@ int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) | |||
| 692 | */ | 612 | */ |
| 693 | int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) | 613 | int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) |
| 694 | { | 614 | { |
| 615 | int ret = -EINVAL; | ||
| 616 | |||
| 695 | if (!pwrdm) | 617 | if (!pwrdm) |
| 696 | return -EINVAL; | 618 | return -EINVAL; |
| 697 | 619 | ||
| 698 | /* | 620 | if (arch_pwrdm && arch_pwrdm->pwrdm_read_prev_logic_pwrst) |
| 699 | * The register bit names below may not correspond to the | 621 | ret = arch_pwrdm->pwrdm_read_prev_logic_pwrst(pwrdm); |
| 700 | * actual names of the bits in each powerdomain's register, | 622 | |
| 701 | * but the type of value returned is the same for each | 623 | return ret; |
| 702 | * powerdomain. | ||
| 703 | */ | ||
| 704 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST, | ||
| 705 | OMAP3430_LASTLOGICSTATEENTERED_MASK); | ||
| 706 | } | 624 | } |
| 707 | 625 | ||
| 708 | /** | 626 | /** |
| @@ -715,17 +633,15 @@ int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) | |||
| 715 | */ | 633 | */ |
| 716 | int pwrdm_read_logic_retst(struct powerdomain *pwrdm) | 634 | int pwrdm_read_logic_retst(struct powerdomain *pwrdm) |
| 717 | { | 635 | { |
| 636 | int ret = -EINVAL; | ||
| 637 | |||
| 718 | if (!pwrdm) | 638 | if (!pwrdm) |
| 719 | return -EINVAL; | 639 | return -EINVAL; |
| 720 | 640 | ||
| 721 | /* | 641 | if (arch_pwrdm && arch_pwrdm->pwrdm_read_logic_retst) |
| 722 | * The register bit names below may not correspond to the | 642 | ret = arch_pwrdm->pwrdm_read_logic_retst(pwrdm); |
| 723 | * actual names of the bits in each powerdomain's register, | 643 | |
| 724 | * but the type of value returned is the same for each | 644 | return ret; |
| 725 | * powerdomain. | ||
| 726 | */ | ||
| 727 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, pwrstctrl_reg_offs, | ||
| 728 | OMAP3430_LOGICSTATEST_MASK); | ||
| 729 | } | 645 | } |
| 730 | 646 | ||
| 731 | /** | 647 | /** |
| @@ -740,46 +656,21 @@ int pwrdm_read_logic_retst(struct powerdomain *pwrdm) | |||
| 740 | */ | 656 | */ |
| 741 | int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) | 657 | int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) |
| 742 | { | 658 | { |
| 743 | u32 m; | 659 | int ret = -EINVAL; |
| 744 | 660 | ||
| 745 | if (!pwrdm) | 661 | if (!pwrdm) |
| 746 | return -EINVAL; | 662 | return ret; |
| 747 | 663 | ||
| 748 | if (pwrdm->banks < (bank + 1)) | 664 | if (pwrdm->banks < (bank + 1)) |
| 749 | return -EEXIST; | 665 | return ret; |
| 750 | 666 | ||
| 751 | if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK) | 667 | if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK) |
| 752 | bank = 1; | 668 | bank = 1; |
| 753 | 669 | ||
| 754 | /* | 670 | if (arch_pwrdm && arch_pwrdm->pwrdm_read_mem_pwrst) |
| 755 | * The register bit names below may not correspond to the | 671 | ret = arch_pwrdm->pwrdm_read_mem_pwrst(pwrdm, bank); |
| 756 | * actual names of the bits in each powerdomain's register, | ||
| 757 | * but the type of value returned is the same for each | ||
| 758 | * powerdomain. | ||
| 759 | */ | ||
| 760 | switch (bank) { | ||
| 761 | case 0: | ||
| 762 | m = OMAP_MEM0_STATEST_MASK; | ||
| 763 | break; | ||
| 764 | case 1: | ||
| 765 | m = OMAP_MEM1_STATEST_MASK; | ||
| 766 | break; | ||
| 767 | case 2: | ||
| 768 | m = OMAP_MEM2_STATEST_MASK; | ||
| 769 | break; | ||
| 770 | case 3: | ||
| 771 | m = OMAP_MEM3_STATEST_MASK; | ||
| 772 | break; | ||
| 773 | case 4: | ||
| 774 | m = OMAP_MEM4_STATEST_MASK; | ||
| 775 | break; | ||
| 776 | default: | ||
| 777 | WARN_ON(1); /* should never happen */ | ||
| 778 | return -EEXIST; | ||
| 779 | } | ||
| 780 | 672 | ||
| 781 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, | 673 | return ret; |
| 782 | pwrstst_reg_offs, m); | ||
| 783 | } | 674 | } |
| 784 | 675 | ||
| 785 | /** | 676 | /** |
| @@ -795,43 +686,21 @@ int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) | |||
| 795 | */ | 686 | */ |
| 796 | int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) | 687 | int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) |
| 797 | { | 688 | { |
| 798 | u32 m; | 689 | int ret = -EINVAL; |
| 799 | 690 | ||
| 800 | if (!pwrdm) | 691 | if (!pwrdm) |
| 801 | return -EINVAL; | 692 | return ret; |
| 802 | 693 | ||
| 803 | if (pwrdm->banks < (bank + 1)) | 694 | if (pwrdm->banks < (bank + 1)) |
| 804 | return -EEXIST; | 695 | return ret; |
| 805 | 696 | ||
| 806 | if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK) | 697 | if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK) |
| 807 | bank = 1; | 698 | bank = 1; |
| 808 | 699 | ||
| 809 | /* | 700 | if (arch_pwrdm && arch_pwrdm->pwrdm_read_prev_mem_pwrst) |
| 810 | * The register bit names below may not correspond to the | 701 | ret = arch_pwrdm->pwrdm_read_prev_mem_pwrst(pwrdm, bank); |
| 811 | * actual names of the bits in each powerdomain's register, | ||
| 812 | * but the type of value returned is the same for each | ||
| 813 | * powerdomain. | ||
| 814 | */ | ||
| 815 | switch (bank) { | ||
| 816 | case 0: | ||
| 817 | m = OMAP3430_LASTMEM1STATEENTERED_MASK; | ||
| 818 | break; | ||
| 819 | case 1: | ||
| 820 | m = OMAP3430_LASTMEM2STATEENTERED_MASK; | ||
| 821 | break; | ||
| 822 | case 2: | ||
| 823 | m = OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK; | ||
| 824 | break; | ||
| 825 | case 3: | ||
| 826 | m = OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK; | ||
| 827 | break; | ||
| 828 | default: | ||
| 829 | WARN_ON(1); /* should never happen */ | ||
| 830 | return -EEXIST; | ||
| 831 | } | ||
| 832 | 702 | ||
| 833 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, | 703 | return ret; |
| 834 | OMAP3430_PM_PREPWSTST, m); | ||
| 835 | } | 704 | } |
| 836 | 705 | ||
| 837 | /** | 706 | /** |
| @@ -846,43 +715,18 @@ int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) | |||
| 846 | */ | 715 | */ |
| 847 | int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) | 716 | int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) |
| 848 | { | 717 | { |
| 849 | u32 m; | 718 | int ret = -EINVAL; |
| 850 | 719 | ||
| 851 | if (!pwrdm) | 720 | if (!pwrdm) |
| 852 | return -EINVAL; | 721 | return ret; |
| 853 | 722 | ||
| 854 | if (pwrdm->banks < (bank + 1)) | 723 | if (pwrdm->banks < (bank + 1)) |
| 855 | return -EEXIST; | 724 | return ret; |
| 856 | 725 | ||
| 857 | /* | 726 | if (arch_pwrdm && arch_pwrdm->pwrdm_read_mem_retst) |
| 858 | * The register bit names below may not correspond to the | 727 | ret = arch_pwrdm->pwrdm_read_mem_retst(pwrdm, bank); |
| 859 | * actual names of the bits in each powerdomain's register, | ||
| 860 | * but the type of value returned is the same for each | ||
| 861 | * powerdomain. | ||
| 862 | */ | ||
| 863 | switch (bank) { | ||
| 864 | case 0: | ||
| 865 | m = OMAP_MEM0_RETSTATE_MASK; | ||
| 866 | break; | ||
| 867 | case 1: | ||
| 868 | m = OMAP_MEM1_RETSTATE_MASK; | ||
| 869 | break; | ||
| 870 | case 2: | ||
| 871 | m = OMAP_MEM2_RETSTATE_MASK; | ||
| 872 | break; | ||
| 873 | case 3: | ||
| 874 | m = OMAP_MEM3_RETSTATE_MASK; | ||
| 875 | break; | ||
| 876 | case 4: | ||
| 877 | m = OMAP_MEM4_RETSTATE_MASK; | ||
| 878 | break; | ||
| 879 | default: | ||
| 880 | WARN_ON(1); /* should never happen */ | ||
| 881 | return -EEXIST; | ||
| 882 | } | ||
| 883 | 728 | ||
| 884 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, | 729 | return ret; |
| 885 | pwrstctrl_reg_offs, m); | ||
| 886 | } | 730 | } |
| 887 | 731 | ||
| 888 | /** | 732 | /** |
| @@ -896,8 +740,10 @@ int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) | |||
| 896 | */ | 740 | */ |
| 897 | int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) | 741 | int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) |
| 898 | { | 742 | { |
| 743 | int ret = -EINVAL; | ||
| 744 | |||
| 899 | if (!pwrdm) | 745 | if (!pwrdm) |
| 900 | return -EINVAL; | 746 | return ret; |
| 901 | 747 | ||
| 902 | /* | 748 | /* |
| 903 | * XXX should get the powerdomain's current state here; | 749 | * XXX should get the powerdomain's current state here; |
| @@ -907,9 +753,10 @@ int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) | |||
| 907 | pr_debug("powerdomain: clearing previous power state reg for %s\n", | 753 | pr_debug("powerdomain: clearing previous power state reg for %s\n", |
| 908 | pwrdm->name); | 754 | pwrdm->name); |
| 909 | 755 | ||
| 910 | prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST); | 756 | if (arch_pwrdm && arch_pwrdm->pwrdm_clear_all_prev_pwrst) |
| 757 | ret = arch_pwrdm->pwrdm_clear_all_prev_pwrst(pwrdm); | ||
| 911 | 758 | ||
| 912 | return 0; | 759 | return ret; |
| 913 | } | 760 | } |
| 914 | 761 | ||
| 915 | /** | 762 | /** |
| @@ -925,19 +772,21 @@ int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) | |||
| 925 | */ | 772 | */ |
| 926 | int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm) | 773 | int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm) |
| 927 | { | 774 | { |
| 775 | int ret = -EINVAL; | ||
| 776 | |||
| 928 | if (!pwrdm) | 777 | if (!pwrdm) |
| 929 | return -EINVAL; | 778 | return ret; |
| 930 | 779 | ||
| 931 | if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR)) | 780 | if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR)) |
| 932 | return -EINVAL; | 781 | return ret; |
| 933 | 782 | ||
| 934 | pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n", | 783 | pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n", |
| 935 | pwrdm->name); | 784 | pwrdm->name); |
| 936 | 785 | ||
| 937 | prm_rmw_mod_reg_bits(0, 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, | 786 | if (arch_pwrdm && arch_pwrdm->pwrdm_enable_hdwr_sar) |
| 938 | pwrdm->prcm_offs, pwrstctrl_reg_offs); | 787 | ret = arch_pwrdm->pwrdm_enable_hdwr_sar(pwrdm); |
| 939 | 788 | ||
| 940 | return 0; | 789 | return ret; |
| 941 | } | 790 | } |
| 942 | 791 | ||
| 943 | /** | 792 | /** |
| @@ -953,19 +802,21 @@ int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm) | |||
| 953 | */ | 802 | */ |
| 954 | int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm) | 803 | int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm) |
| 955 | { | 804 | { |
| 805 | int ret = -EINVAL; | ||
| 806 | |||
| 956 | if (!pwrdm) | 807 | if (!pwrdm) |
| 957 | return -EINVAL; | 808 | return ret; |
| 958 | 809 | ||
| 959 | if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR)) | 810 | if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR)) |
| 960 | return -EINVAL; | 811 | return ret; |
| 961 | 812 | ||
| 962 | pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n", | 813 | pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n", |
| 963 | pwrdm->name); | 814 | pwrdm->name); |
| 964 | 815 | ||
| 965 | prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, 0, | 816 | if (arch_pwrdm && arch_pwrdm->pwrdm_disable_hdwr_sar) |
| 966 | pwrdm->prcm_offs, pwrstctrl_reg_offs); | 817 | ret = arch_pwrdm->pwrdm_disable_hdwr_sar(pwrdm); |
| 967 | 818 | ||
| 968 | return 0; | 819 | return ret; |
| 969 | } | 820 | } |
| 970 | 821 | ||
| 971 | /** | 822 | /** |
| @@ -992,6 +843,8 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm) | |||
| 992 | */ | 843 | */ |
| 993 | int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) | 844 | int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) |
| 994 | { | 845 | { |
| 846 | int ret = -EINVAL; | ||
| 847 | |||
| 995 | if (!pwrdm) | 848 | if (!pwrdm) |
| 996 | return -EINVAL; | 849 | return -EINVAL; |
| 997 | 850 | ||
| @@ -1001,11 +854,10 @@ int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) | |||
| 1001 | pr_debug("powerdomain: %s: setting LOWPOWERSTATECHANGE bit\n", | 854 | pr_debug("powerdomain: %s: setting LOWPOWERSTATECHANGE bit\n", |
| 1002 | pwrdm->name); | 855 | pwrdm->name); |
| 1003 | 856 | ||
| 1004 | prm_rmw_mod_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK, | 857 | if (arch_pwrdm && arch_pwrdm->pwrdm_set_lowpwrstchange) |
| 1005 | (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT), | 858 | ret = arch_pwrdm->pwrdm_set_lowpwrstchange(pwrdm); |
| 1006 | pwrdm->prcm_offs, pwrstctrl_reg_offs); | ||
| 1007 | 859 | ||
| 1008 | return 0; | 860 | return ret; |
| 1009 | } | 861 | } |
| 1010 | 862 | ||
| 1011 | /** | 863 | /** |
| @@ -1020,32 +872,15 @@ int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) | |||
| 1020 | */ | 872 | */ |
| 1021 | int pwrdm_wait_transition(struct powerdomain *pwrdm) | 873 | int pwrdm_wait_transition(struct powerdomain *pwrdm) |
| 1022 | { | 874 | { |
| 1023 | u32 c = 0; | 875 | int ret = -EINVAL; |
| 1024 | 876 | ||
| 1025 | if (!pwrdm) | 877 | if (!pwrdm) |
| 1026 | return -EINVAL; | 878 | return -EINVAL; |
| 1027 | 879 | ||
| 1028 | /* | 880 | if (arch_pwrdm && arch_pwrdm->pwrdm_wait_transition) |
| 1029 | * REVISIT: pwrdm_wait_transition() may be better implemented | 881 | ret = arch_pwrdm->pwrdm_wait_transition(pwrdm); |
| 1030 | * via a callback and a periodic timer check -- how long do we expect | ||
| 1031 | * powerdomain transitions to take? | ||
| 1032 | */ | ||
| 1033 | |||
| 1034 | /* XXX Is this udelay() value meaningful? */ | ||
| 1035 | while ((prm_read_mod_reg(pwrdm->prcm_offs, pwrstst_reg_offs) & | ||
| 1036 | OMAP_INTRANSITION_MASK) && | ||
| 1037 | (c++ < PWRDM_TRANSITION_BAILOUT)) | ||
| 1038 | udelay(1); | ||
| 1039 | |||
| 1040 | if (c > PWRDM_TRANSITION_BAILOUT) { | ||
| 1041 | printk(KERN_ERR "powerdomain: waited too long for " | ||
| 1042 | "powerdomain %s to complete transition\n", pwrdm->name); | ||
| 1043 | return -EAGAIN; | ||
| 1044 | } | ||
| 1045 | |||
| 1046 | pr_debug("powerdomain: completed transition in %d loops\n", c); | ||
| 1047 | 882 | ||
| 1048 | return 0; | 883 | return ret; |
| 1049 | } | 884 | } |
| 1050 | 885 | ||
| 1051 | int pwrdm_state_switch(struct powerdomain *pwrdm) | 886 | int pwrdm_state_switch(struct powerdomain *pwrdm) |
| @@ -1075,3 +910,31 @@ int pwrdm_post_transition(void) | |||
| 1075 | return 0; | 910 | return 0; |
| 1076 | } | 911 | } |
| 1077 | 912 | ||
| 913 | /** | ||
| 914 | * pwrdm_get_context_loss_count - get powerdomain's context loss count | ||
| 915 | * @pwrdm: struct powerdomain * to wait for | ||
| 916 | * | ||
| 917 | * Context loss count is the sum of powerdomain off-mode counter, the | ||
| 918 | * logic off counter and the per-bank memory off counter. Returns 0 | ||
| 919 | * (and WARNs) upon error, otherwise, returns the context loss count. | ||
| 920 | */ | ||
| 921 | u32 pwrdm_get_context_loss_count(struct powerdomain *pwrdm) | ||
| 922 | { | ||
| 923 | int i, count; | ||
| 924 | |||
| 925 | if (!pwrdm) { | ||
| 926 | WARN(1, "powerdomain: %s: pwrdm is null\n", __func__); | ||
| 927 | return 0; | ||
| 928 | } | ||
| 929 | |||
| 930 | count = pwrdm->state_counter[PWRDM_POWER_OFF]; | ||
| 931 | count += pwrdm->ret_logic_off_counter; | ||
| 932 | |||
| 933 | for (i = 0; i < pwrdm->banks; i++) | ||
| 934 | count += pwrdm->ret_mem_off_counter[i]; | ||
| 935 | |||
| 936 | pr_debug("powerdomain: %s: context loss count = %u\n", | ||
| 937 | pwrdm->name, count); | ||
| 938 | |||
| 939 | return count; | ||
| 940 | } | ||
diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h index 9ca420dcd2f8..c66431edfeb7 100644 --- a/arch/arm/plat-omap/include/plat/powerdomain.h +++ b/arch/arm/mach-omap2/powerdomain.h | |||
| @@ -1,27 +1,29 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * OMAP2/3 powerdomain control | 2 | * OMAP2/3/4 powerdomain control |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | 4 | * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2007-2009 Nokia Corporation | 5 | * Copyright (C) 2007-2010 Nokia Corporation |
| 6 | * | 6 | * |
| 7 | * Written by Paul Walmsley | 7 | * Paul Walmsley |
| 8 | * | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify | 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as | 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. | 11 | * published by the Free Software Foundation. |
| 12 | * | ||
| 13 | * XXX This should be moved to the mach-omap2/ directory at the earliest | ||
| 14 | * opportunity. | ||
| 12 | */ | 15 | */ |
| 13 | 16 | ||
| 14 | #ifndef ASM_ARM_ARCH_OMAP_POWERDOMAIN | 17 | #ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H |
| 15 | #define ASM_ARM_ARCH_OMAP_POWERDOMAIN | 18 | #define __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H |
| 16 | 19 | ||
| 17 | #include <linux/types.h> | 20 | #include <linux/types.h> |
| 18 | #include <linux/list.h> | 21 | #include <linux/list.h> |
| 19 | 22 | ||
| 20 | #include <asm/atomic.h> | 23 | #include <linux/atomic.h> |
| 21 | 24 | ||
| 22 | #include <plat/cpu.h> | 25 | #include <plat/cpu.h> |
| 23 | 26 | ||
| 24 | |||
| 25 | /* Powerdomain basic power states */ | 27 | /* Powerdomain basic power states */ |
| 26 | #define PWRDM_POWER_OFF 0x0 | 28 | #define PWRDM_POWER_OFF 0x0 |
| 27 | #define PWRDM_POWER_RET 0x1 | 29 | #define PWRDM_POWER_RET 0x1 |
| @@ -81,6 +83,7 @@ struct powerdomain; | |||
| 81 | * @name: Powerdomain name | 83 | * @name: Powerdomain name |
| 82 | * @omap_chip: represents the OMAP chip types containing this pwrdm | 84 | * @omap_chip: represents the OMAP chip types containing this pwrdm |
| 83 | * @prcm_offs: the address offset from CM_BASE/PRM_BASE | 85 | * @prcm_offs: the address offset from CM_BASE/PRM_BASE |
| 86 | * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs | ||
| 84 | * @pwrsts: Possible powerdomain power states | 87 | * @pwrsts: Possible powerdomain power states |
| 85 | * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION | 88 | * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION |
| 86 | * @flags: Powerdomain flags | 89 | * @flags: Powerdomain flags |
| @@ -93,6 +96,8 @@ struct powerdomain; | |||
| 93 | * @state_counter: | 96 | * @state_counter: |
| 94 | * @timer: | 97 | * @timer: |
| 95 | * @state_timer: | 98 | * @state_timer: |
| 99 | * | ||
| 100 | * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h. | ||
| 96 | */ | 101 | */ |
| 97 | struct powerdomain { | 102 | struct powerdomain { |
| 98 | const char *name; | 103 | const char *name; |
| @@ -104,6 +109,7 @@ struct powerdomain { | |||
| 104 | const u8 banks; | 109 | const u8 banks; |
| 105 | const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS]; | 110 | const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS]; |
| 106 | const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS]; | 111 | const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS]; |
| 112 | const u8 prcm_partition; | ||
| 107 | struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS]; | 113 | struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS]; |
| 108 | struct list_head node; | 114 | struct list_head node; |
| 109 | int state; | 115 | int state; |
| @@ -117,8 +123,50 @@ struct powerdomain { | |||
| 117 | #endif | 123 | #endif |
| 118 | }; | 124 | }; |
| 119 | 125 | ||
| 126 | /** | ||
| 127 | * struct pwrdm_ops - Arch specfic function implementations | ||
| 128 | * @pwrdm_set_next_pwrst: Set the target power state for a pd | ||
| 129 | * @pwrdm_read_next_pwrst: Read the target power state set for a pd | ||
| 130 | * @pwrdm_read_pwrst: Read the current power state of a pd | ||
| 131 | * @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd | ||
| 132 | * @pwrdm_set_logic_retst: Set the logic state in RET for a pd | ||
| 133 | * @pwrdm_set_mem_onst: Set the Memory state in ON for a pd | ||
| 134 | * @pwrdm_set_mem_retst: Set the Memory state in RET for a pd | ||
| 135 | * @pwrdm_read_logic_pwrst: Read the current logic state of a pd | ||
| 136 | * @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd | ||
| 137 | * @pwrdm_read_logic_retst: Read the logic state in RET for a pd | ||
| 138 | * @pwrdm_read_mem_pwrst: Read the current memory state of a pd | ||
| 139 | * @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd | ||
| 140 | * @pwrdm_read_mem_retst: Read the memory state in RET for a pd | ||
| 141 | * @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd | ||
| 142 | * @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd | ||
| 143 | * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd | ||
| 144 | * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep | ||
| 145 | * @pwrdm_wait_transition: Wait for a pd state transition to complete | ||
| 146 | */ | ||
| 147 | struct pwrdm_ops { | ||
| 148 | int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst); | ||
| 149 | int (*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm); | ||
| 150 | int (*pwrdm_read_pwrst)(struct powerdomain *pwrdm); | ||
| 151 | int (*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm); | ||
| 152 | int (*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst); | ||
| 153 | int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst); | ||
| 154 | int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst); | ||
| 155 | int (*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm); | ||
| 156 | int (*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm); | ||
| 157 | int (*pwrdm_read_logic_retst)(struct powerdomain *pwrdm); | ||
| 158 | int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank); | ||
| 159 | int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank); | ||
| 160 | int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank); | ||
| 161 | int (*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm); | ||
| 162 | int (*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm); | ||
| 163 | int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm); | ||
| 164 | int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm); | ||
| 165 | int (*pwrdm_wait_transition)(struct powerdomain *pwrdm); | ||
| 166 | }; | ||
| 120 | 167 | ||
| 121 | void pwrdm_init(struct powerdomain **pwrdm_list); | 168 | void pwrdm_fw_init(void); |
| 169 | void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs); | ||
| 122 | 170 | ||
| 123 | struct powerdomain *pwrdm_lookup(const char *name); | 171 | struct powerdomain *pwrdm_lookup(const char *name); |
| 124 | 172 | ||
| @@ -163,5 +211,23 @@ int pwrdm_clkdm_state_switch(struct clockdomain *clkdm); | |||
| 163 | int pwrdm_pre_transition(void); | 211 | int pwrdm_pre_transition(void); |
| 164 | int pwrdm_post_transition(void); | 212 | int pwrdm_post_transition(void); |
| 165 | int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm); | 213 | int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm); |
| 214 | u32 pwrdm_get_context_loss_count(struct powerdomain *pwrdm); | ||
| 215 | |||
| 216 | extern void omap2xxx_powerdomains_init(void); | ||
| 217 | extern void omap3xxx_powerdomains_init(void); | ||
| 218 | extern void omap44xx_powerdomains_init(void); | ||
| 219 | |||
| 220 | extern struct pwrdm_ops omap2_pwrdm_operations; | ||
| 221 | extern struct pwrdm_ops omap3_pwrdm_operations; | ||
| 222 | extern struct pwrdm_ops omap4_pwrdm_operations; | ||
| 223 | |||
| 224 | /* Common Internal functions used across OMAP rev's */ | ||
| 225 | extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank); | ||
| 226 | extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank); | ||
| 227 | extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank); | ||
| 228 | |||
| 229 | extern struct powerdomain wkup_omap2_pwrdm; | ||
| 230 | extern struct powerdomain gfx_omap2_pwrdm; | ||
| 231 | |||
| 166 | 232 | ||
| 167 | #endif | 233 | #endif |
diff --git a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c new file mode 100644 index 000000000000..d5233890370c --- /dev/null +++ b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c | |||
| @@ -0,0 +1,242 @@ | |||
| 1 | /* | ||
| 2 | * OMAP2 and OMAP3 powerdomain control | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2007-2009 Nokia Corporation | ||
| 6 | * | ||
| 7 | * Derived from mach-omap2/powerdomain.c written by Paul Walmsley | ||
| 8 | * Rajendra Nayak <rnayak@ti.com> | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/io.h> | ||
| 16 | #include <linux/errno.h> | ||
| 17 | #include <linux/delay.h> | ||
| 18 | |||
| 19 | #include <plat/prcm.h> | ||
| 20 | |||
| 21 | #include "powerdomain.h" | ||
| 22 | #include "prm-regbits-34xx.h" | ||
| 23 | #include "prm.h" | ||
| 24 | #include "prm-regbits-24xx.h" | ||
| 25 | #include "prm-regbits-34xx.h" | ||
| 26 | |||
| 27 | |||
| 28 | /* Common functions across OMAP2 and OMAP3 */ | ||
| 29 | static int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) | ||
| 30 | { | ||
| 31 | omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, | ||
| 32 | (pwrst << OMAP_POWERSTATE_SHIFT), | ||
| 33 | pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); | ||
| 34 | return 0; | ||
| 35 | } | ||
| 36 | |||
| 37 | static int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) | ||
| 38 | { | ||
| 39 | return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, | ||
| 40 | OMAP2_PM_PWSTCTRL, | ||
| 41 | OMAP_POWERSTATE_MASK); | ||
| 42 | } | ||
| 43 | |||
| 44 | static int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm) | ||
| 45 | { | ||
| 46 | return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, | ||
| 47 | OMAP2_PM_PWSTST, | ||
| 48 | OMAP_POWERSTATEST_MASK); | ||
| 49 | } | ||
| 50 | |||
| 51 | static int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, | ||
| 52 | u8 pwrst) | ||
| 53 | { | ||
| 54 | u32 m; | ||
| 55 | |||
| 56 | m = omap2_pwrdm_get_mem_bank_onstate_mask(bank); | ||
| 57 | |||
| 58 | omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, | ||
| 59 | OMAP2_PM_PWSTCTRL); | ||
| 60 | |||
| 61 | return 0; | ||
| 62 | } | ||
| 63 | |||
| 64 | static int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, | ||
| 65 | u8 pwrst) | ||
| 66 | { | ||
| 67 | u32 m; | ||
| 68 | |||
| 69 | m = omap2_pwrdm_get_mem_bank_retst_mask(bank); | ||
| 70 | |||
| 71 | omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, | ||
| 72 | OMAP2_PM_PWSTCTRL); | ||
| 73 | |||
| 74 | return 0; | ||
| 75 | } | ||
| 76 | |||
| 77 | static int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) | ||
| 78 | { | ||
| 79 | u32 m; | ||
| 80 | |||
| 81 | m = omap2_pwrdm_get_mem_bank_stst_mask(bank); | ||
| 82 | |||
| 83 | return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST, | ||
| 84 | m); | ||
| 85 | } | ||
| 86 | |||
| 87 | static int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) | ||
| 88 | { | ||
| 89 | u32 m; | ||
| 90 | |||
| 91 | m = omap2_pwrdm_get_mem_bank_retst_mask(bank); | ||
| 92 | |||
| 93 | return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, | ||
| 94 | OMAP2_PM_PWSTCTRL, m); | ||
| 95 | } | ||
| 96 | |||
| 97 | static int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) | ||
| 98 | { | ||
| 99 | u32 v; | ||
| 100 | |||
| 101 | v = pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE_MASK); | ||
| 102 | omap2_prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE_MASK, v, | ||
| 103 | pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); | ||
| 104 | |||
| 105 | return 0; | ||
| 106 | } | ||
| 107 | |||
| 108 | static int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm) | ||
| 109 | { | ||
| 110 | u32 c = 0; | ||
| 111 | |||
| 112 | /* | ||
| 113 | * REVISIT: pwrdm_wait_transition() may be better implemented | ||
| 114 | * via a callback and a periodic timer check -- how long do we expect | ||
| 115 | * powerdomain transitions to take? | ||
| 116 | */ | ||
| 117 | |||
| 118 | /* XXX Is this udelay() value meaningful? */ | ||
| 119 | while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) & | ||
| 120 | OMAP_INTRANSITION_MASK) && | ||
| 121 | (c++ < PWRDM_TRANSITION_BAILOUT)) | ||
| 122 | udelay(1); | ||
| 123 | |||
| 124 | if (c > PWRDM_TRANSITION_BAILOUT) { | ||
| 125 | printk(KERN_ERR "powerdomain: waited too long for " | ||
| 126 | "powerdomain %s to complete transition\n", pwrdm->name); | ||
| 127 | return -EAGAIN; | ||
| 128 | } | ||
| 129 | |||
| 130 | pr_debug("powerdomain: completed transition in %d loops\n", c); | ||
| 131 | |||
| 132 | return 0; | ||
| 133 | } | ||
| 134 | |||
| 135 | /* Applicable only for OMAP3. Not supported on OMAP2 */ | ||
| 136 | static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) | ||
| 137 | { | ||
| 138 | return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, | ||
| 139 | OMAP3430_PM_PREPWSTST, | ||
| 140 | OMAP3430_LASTPOWERSTATEENTERED_MASK); | ||
| 141 | } | ||
| 142 | |||
| 143 | static int omap3_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) | ||
| 144 | { | ||
| 145 | return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, | ||
| 146 | OMAP2_PM_PWSTST, | ||
| 147 | OMAP3430_LOGICSTATEST_MASK); | ||
| 148 | } | ||
| 149 | |||
| 150 | static int omap3_pwrdm_read_logic_retst(struct powerdomain *pwrdm) | ||
| 151 | { | ||
| 152 | return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, | ||
| 153 | OMAP2_PM_PWSTCTRL, | ||
| 154 | OMAP3430_LOGICSTATEST_MASK); | ||
| 155 | } | ||
| 156 | |||
| 157 | static int omap3_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) | ||
| 158 | { | ||
| 159 | return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, | ||
| 160 | OMAP3430_PM_PREPWSTST, | ||
| 161 | OMAP3430_LASTLOGICSTATEENTERED_MASK); | ||
| 162 | } | ||
| 163 | |||
| 164 | static int omap3_get_mem_bank_lastmemst_mask(u8 bank) | ||
| 165 | { | ||
| 166 | switch (bank) { | ||
| 167 | case 0: | ||
| 168 | return OMAP3430_LASTMEM1STATEENTERED_MASK; | ||
| 169 | case 1: | ||
| 170 | return OMAP3430_LASTMEM2STATEENTERED_MASK; | ||
| 171 | case 2: | ||
| 172 | return OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK; | ||
| 173 | case 3: | ||
| 174 | return OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK; | ||
| 175 | default: | ||
| 176 | WARN_ON(1); /* should never happen */ | ||
| 177 | return -EEXIST; | ||
| 178 | } | ||
| 179 | return 0; | ||
| 180 | } | ||
| 181 | |||
| 182 | static int omap3_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) | ||
| 183 | { | ||
| 184 | u32 m; | ||
| 185 | |||
| 186 | m = omap3_get_mem_bank_lastmemst_mask(bank); | ||
| 187 | |||
| 188 | return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, | ||
| 189 | OMAP3430_PM_PREPWSTST, m); | ||
| 190 | } | ||
| 191 | |||
| 192 | static int omap3_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) | ||
| 193 | { | ||
| 194 | omap2_prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST); | ||
| 195 | return 0; | ||
| 196 | } | ||
| 197 | |||
| 198 | static int omap3_pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm) | ||
| 199 | { | ||
| 200 | return omap2_prm_rmw_mod_reg_bits(0, | ||
| 201 | 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, | ||
| 202 | pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); | ||
| 203 | } | ||
| 204 | |||
| 205 | static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm) | ||
| 206 | { | ||
| 207 | return omap2_prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, | ||
| 208 | 0, pwrdm->prcm_offs, | ||
| 209 | OMAP2_PM_PWSTCTRL); | ||
| 210 | } | ||
| 211 | |||
| 212 | struct pwrdm_ops omap2_pwrdm_operations = { | ||
| 213 | .pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst, | ||
| 214 | .pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst, | ||
| 215 | .pwrdm_read_pwrst = omap2_pwrdm_read_pwrst, | ||
| 216 | .pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst, | ||
| 217 | .pwrdm_set_mem_onst = omap2_pwrdm_set_mem_onst, | ||
| 218 | .pwrdm_set_mem_retst = omap2_pwrdm_set_mem_retst, | ||
| 219 | .pwrdm_read_mem_pwrst = omap2_pwrdm_read_mem_pwrst, | ||
| 220 | .pwrdm_read_mem_retst = omap2_pwrdm_read_mem_retst, | ||
| 221 | .pwrdm_wait_transition = omap2_pwrdm_wait_transition, | ||
| 222 | }; | ||
| 223 | |||
| 224 | struct pwrdm_ops omap3_pwrdm_operations = { | ||
| 225 | .pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst, | ||
| 226 | .pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst, | ||
| 227 | .pwrdm_read_pwrst = omap2_pwrdm_read_pwrst, | ||
| 228 | .pwrdm_read_prev_pwrst = omap3_pwrdm_read_prev_pwrst, | ||
| 229 | .pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst, | ||
| 230 | .pwrdm_read_logic_pwrst = omap3_pwrdm_read_logic_pwrst, | ||
| 231 | .pwrdm_read_logic_retst = omap3_pwrdm_read_logic_retst, | ||
| 232 | .pwrdm_read_prev_logic_pwrst = omap3_pwrdm_read_prev_logic_pwrst, | ||
| 233 | .pwrdm_set_mem_onst = omap2_pwrdm_set_mem_onst, | ||
| 234 | .pwrdm_set_mem_retst = omap2_pwrdm_set_mem_retst, | ||
| 235 | .pwrdm_read_mem_pwrst = omap2_pwrdm_read_mem_pwrst, | ||
| 236 | .pwrdm_read_mem_retst = omap2_pwrdm_read_mem_retst, | ||
| 237 | .pwrdm_read_prev_mem_pwrst = omap3_pwrdm_read_prev_mem_pwrst, | ||
| 238 | .pwrdm_clear_all_prev_pwrst = omap3_pwrdm_clear_all_prev_pwrst, | ||
| 239 | .pwrdm_enable_hdwr_sar = omap3_pwrdm_enable_hdwr_sar, | ||
| 240 | .pwrdm_disable_hdwr_sar = omap3_pwrdm_disable_hdwr_sar, | ||
| 241 | .pwrdm_wait_transition = omap2_pwrdm_wait_transition, | ||
| 242 | }; | ||
diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c new file mode 100644 index 000000000000..a7880af4b3d9 --- /dev/null +++ b/arch/arm/mach-omap2/powerdomain44xx.c | |||
| @@ -0,0 +1,225 @@ | |||
| 1 | /* | ||
| 2 | * OMAP4 powerdomain control | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2007-2009 Nokia Corporation | ||
| 6 | * | ||
| 7 | * Derived from mach-omap2/powerdomain.c written by Paul Walmsley | ||
| 8 | * Rajendra Nayak <rnayak@ti.com> | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/io.h> | ||
| 16 | #include <linux/errno.h> | ||
| 17 | #include <linux/delay.h> | ||
| 18 | |||
| 19 | #include "powerdomain.h" | ||
| 20 | #include <plat/prcm.h> | ||
| 21 | #include "prm2xxx_3xxx.h" | ||
| 22 | #include "prm44xx.h" | ||
| 23 | #include "prminst44xx.h" | ||
| 24 | #include "prm-regbits-44xx.h" | ||
| 25 | |||
| 26 | static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) | ||
| 27 | { | ||
| 28 | omap4_prminst_rmw_inst_reg_bits(OMAP_POWERSTATE_MASK, | ||
| 29 | (pwrst << OMAP_POWERSTATE_SHIFT), | ||
| 30 | pwrdm->prcm_partition, | ||
| 31 | pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); | ||
| 32 | return 0; | ||
| 33 | } | ||
| 34 | |||
| 35 | static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) | ||
| 36 | { | ||
| 37 | u32 v; | ||
| 38 | |||
| 39 | v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, | ||
| 40 | OMAP4_PM_PWSTCTRL); | ||
| 41 | v &= OMAP_POWERSTATE_MASK; | ||
| 42 | v >>= OMAP_POWERSTATE_SHIFT; | ||
| 43 | |||
| 44 | return v; | ||
| 45 | } | ||
| 46 | |||
| 47 | static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm) | ||
| 48 | { | ||
| 49 | u32 v; | ||
| 50 | |||
| 51 | v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, | ||
| 52 | OMAP4_PM_PWSTST); | ||
| 53 | v &= OMAP_POWERSTATEST_MASK; | ||
| 54 | v >>= OMAP_POWERSTATEST_SHIFT; | ||
| 55 | |||
| 56 | return v; | ||
| 57 | } | ||
| 58 | |||
| 59 | static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) | ||
| 60 | { | ||
| 61 | u32 v; | ||
| 62 | |||
| 63 | v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, | ||
| 64 | OMAP4_PM_PWSTST); | ||
| 65 | v &= OMAP4430_LASTPOWERSTATEENTERED_MASK; | ||
| 66 | v >>= OMAP4430_LASTPOWERSTATEENTERED_SHIFT; | ||
| 67 | |||
| 68 | return v; | ||
| 69 | } | ||
| 70 | |||
| 71 | static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) | ||
| 72 | { | ||
| 73 | omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK, | ||
| 74 | (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT), | ||
| 75 | pwrdm->prcm_partition, | ||
| 76 | pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); | ||
| 77 | return 0; | ||
| 78 | } | ||
| 79 | |||
| 80 | static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) | ||
| 81 | { | ||
| 82 | omap4_prminst_rmw_inst_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK, | ||
| 83 | OMAP4430_LASTPOWERSTATEENTERED_MASK, | ||
| 84 | pwrdm->prcm_partition, | ||
| 85 | pwrdm->prcm_offs, OMAP4_PM_PWSTST); | ||
| 86 | return 0; | ||
| 87 | } | ||
| 88 | |||
| 89 | static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) | ||
| 90 | { | ||
| 91 | u32 v; | ||
| 92 | |||
| 93 | v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK); | ||
| 94 | omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v, | ||
| 95 | pwrdm->prcm_partition, pwrdm->prcm_offs, | ||
| 96 | OMAP4_PM_PWSTCTRL); | ||
| 97 | |||
| 98 | return 0; | ||
| 99 | } | ||
| 100 | |||
| 101 | static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, | ||
| 102 | u8 pwrst) | ||
| 103 | { | ||
| 104 | u32 m; | ||
| 105 | |||
| 106 | m = omap2_pwrdm_get_mem_bank_onstate_mask(bank); | ||
| 107 | |||
| 108 | omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)), | ||
| 109 | pwrdm->prcm_partition, pwrdm->prcm_offs, | ||
| 110 | OMAP4_PM_PWSTCTRL); | ||
| 111 | |||
| 112 | return 0; | ||
| 113 | } | ||
| 114 | |||
| 115 | static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, | ||
| 116 | u8 pwrst) | ||
| 117 | { | ||
| 118 | u32 m; | ||
| 119 | |||
| 120 | m = omap2_pwrdm_get_mem_bank_retst_mask(bank); | ||
| 121 | |||
| 122 | omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)), | ||
| 123 | pwrdm->prcm_partition, pwrdm->prcm_offs, | ||
| 124 | OMAP4_PM_PWSTCTRL); | ||
| 125 | |||
| 126 | return 0; | ||
| 127 | } | ||
| 128 | |||
| 129 | static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) | ||
| 130 | { | ||
| 131 | u32 v; | ||
| 132 | |||
| 133 | v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, | ||
| 134 | OMAP4_PM_PWSTST); | ||
| 135 | v &= OMAP4430_LOGICSTATEST_MASK; | ||
| 136 | v >>= OMAP4430_LOGICSTATEST_SHIFT; | ||
| 137 | |||
| 138 | return v; | ||
| 139 | } | ||
| 140 | |||
| 141 | static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm) | ||
| 142 | { | ||
| 143 | u32 v; | ||
| 144 | |||
| 145 | v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, | ||
| 146 | OMAP4_PM_PWSTCTRL); | ||
| 147 | v &= OMAP4430_LOGICRETSTATE_MASK; | ||
| 148 | v >>= OMAP4430_LOGICRETSTATE_SHIFT; | ||
| 149 | |||
| 150 | return v; | ||
| 151 | } | ||
| 152 | |||
| 153 | static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) | ||
| 154 | { | ||
| 155 | u32 m, v; | ||
| 156 | |||
| 157 | m = omap2_pwrdm_get_mem_bank_stst_mask(bank); | ||
| 158 | |||
| 159 | v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, | ||
| 160 | OMAP4_PM_PWSTST); | ||
| 161 | v &= m; | ||
| 162 | v >>= __ffs(m); | ||
| 163 | |||
| 164 | return v; | ||
| 165 | } | ||
| 166 | |||
| 167 | static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) | ||
| 168 | { | ||
| 169 | u32 m, v; | ||
| 170 | |||
| 171 | m = omap2_pwrdm_get_mem_bank_retst_mask(bank); | ||
| 172 | |||
| 173 | v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, | ||
| 174 | OMAP4_PM_PWSTCTRL); | ||
| 175 | v &= m; | ||
| 176 | v >>= __ffs(m); | ||
| 177 | |||
| 178 | return v; | ||
| 179 | } | ||
| 180 | |||
| 181 | static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm) | ||
| 182 | { | ||
| 183 | u32 c = 0; | ||
| 184 | |||
| 185 | /* | ||
| 186 | * REVISIT: pwrdm_wait_transition() may be better implemented | ||
| 187 | * via a callback and a periodic timer check -- how long do we expect | ||
| 188 | * powerdomain transitions to take? | ||
| 189 | */ | ||
| 190 | |||
| 191 | /* XXX Is this udelay() value meaningful? */ | ||
| 192 | while ((omap4_prminst_read_inst_reg(pwrdm->prcm_partition, | ||
| 193 | pwrdm->prcm_offs, | ||
| 194 | OMAP4_PM_PWSTST) & | ||
| 195 | OMAP_INTRANSITION_MASK) && | ||
| 196 | (c++ < PWRDM_TRANSITION_BAILOUT)) | ||
| 197 | udelay(1); | ||
| 198 | |||
| 199 | if (c > PWRDM_TRANSITION_BAILOUT) { | ||
| 200 | printk(KERN_ERR "powerdomain: waited too long for " | ||
| 201 | "powerdomain %s to complete transition\n", pwrdm->name); | ||
| 202 | return -EAGAIN; | ||
| 203 | } | ||
| 204 | |||
| 205 | pr_debug("powerdomain: completed transition in %d loops\n", c); | ||
| 206 | |||
| 207 | return 0; | ||
| 208 | } | ||
| 209 | |||
| 210 | struct pwrdm_ops omap4_pwrdm_operations = { | ||
| 211 | .pwrdm_set_next_pwrst = omap4_pwrdm_set_next_pwrst, | ||
| 212 | .pwrdm_read_next_pwrst = omap4_pwrdm_read_next_pwrst, | ||
| 213 | .pwrdm_read_pwrst = omap4_pwrdm_read_pwrst, | ||
| 214 | .pwrdm_read_prev_pwrst = omap4_pwrdm_read_prev_pwrst, | ||
| 215 | .pwrdm_set_lowpwrstchange = omap4_pwrdm_set_lowpwrstchange, | ||
| 216 | .pwrdm_clear_all_prev_pwrst = omap4_pwrdm_clear_all_prev_pwrst, | ||
| 217 | .pwrdm_set_logic_retst = omap4_pwrdm_set_logic_retst, | ||
| 218 | .pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst, | ||
| 219 | .pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst, | ||
| 220 | .pwrdm_read_mem_pwrst = omap4_pwrdm_read_mem_pwrst, | ||
| 221 | .pwrdm_read_mem_retst = omap4_pwrdm_read_mem_retst, | ||
| 222 | .pwrdm_set_mem_onst = omap4_pwrdm_set_mem_onst, | ||
| 223 | .pwrdm_set_mem_retst = omap4_pwrdm_set_mem_retst, | ||
| 224 | .pwrdm_wait_transition = omap4_pwrdm_wait_transition, | ||
| 225 | }; | ||
diff --git a/arch/arm/mach-omap2/powerdomains.h b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c index 105cbcaefd3b..5b4dd971320a 100644 --- a/arch/arm/mach-omap2/powerdomains.h +++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c | |||
| @@ -2,10 +2,9 @@ | |||
| 2 | * OMAP2/3 common powerdomain definitions | 2 | * OMAP2/3 common powerdomain definitions |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | 4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2007-2009 Nokia Corporation | 5 | * Copyright (C) 2007-2010 Nokia Corporation |
| 6 | * | 6 | * |
| 7 | * Written by Paul Walmsley | 7 | * Paul Walmsley, Jouni Högander |
| 8 | * Debugging and integration fixes by Jouni Högander | ||
| 9 | * | 8 | * |
| 10 | * This program is free software; you can redistribute it and/or modify | 9 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as | 10 | * it under the terms of the GNU General Public License version 2 as |
| @@ -18,9 +17,6 @@ | |||
| 18 | * Clock Domain Framework | 17 | * Clock Domain Framework |
| 19 | */ | 18 | */ |
| 20 | 19 | ||
| 21 | #ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS | ||
| 22 | #define ARCH_ARM_MACH_OMAP2_POWERDOMAINS | ||
| 23 | |||
| 24 | /* | 20 | /* |
| 25 | * This file contains all of the powerdomains that have some element | 21 | * This file contains all of the powerdomains that have some element |
| 26 | * of software control for the OMAP24xx and OMAP34xx chips. | 22 | * of software control for the OMAP24xx and OMAP34xx chips. |
| @@ -49,24 +45,18 @@ | |||
| 49 | * address offset is different between the C55 and C64 DSPs. | 45 | * address offset is different between the C55 and C64 DSPs. |
| 50 | */ | 46 | */ |
| 51 | 47 | ||
| 52 | #include <plat/powerdomain.h> | 48 | #include "powerdomain.h" |
| 53 | 49 | ||
| 54 | #include "prcm-common.h" | 50 | #include "prcm-common.h" |
| 55 | #include "prm.h" | 51 | #include "prm.h" |
| 56 | #include "cm.h" | ||
| 57 | #include "powerdomains24xx.h" | ||
| 58 | #include "powerdomains34xx.h" | ||
| 59 | #include "powerdomains44xx.h" | ||
| 60 | 52 | ||
| 61 | /* OMAP2/3-common powerdomains */ | 53 | /* OMAP2/3-common powerdomains */ |
| 62 | 54 | ||
| 63 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) | ||
| 64 | |||
| 65 | /* | 55 | /* |
| 66 | * The GFX powerdomain is not present on 3430ES2, but currently we do not | 56 | * The GFX powerdomain is not present on 3430ES2, but currently we do not |
| 67 | * have a macro to filter it out at compile-time. | 57 | * have a macro to filter it out at compile-time. |
| 68 | */ | 58 | */ |
| 69 | static struct powerdomain gfx_omap2_pwrdm = { | 59 | struct powerdomain gfx_omap2_pwrdm = { |
| 70 | .name = "gfx_pwrdm", | 60 | .name = "gfx_pwrdm", |
| 71 | .prcm_offs = GFX_MOD, | 61 | .prcm_offs = GFX_MOD, |
| 72 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | | 62 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | |
| @@ -82,72 +72,8 @@ static struct powerdomain gfx_omap2_pwrdm = { | |||
| 82 | }, | 72 | }, |
| 83 | }; | 73 | }; |
| 84 | 74 | ||
| 85 | static struct powerdomain wkup_omap2_pwrdm = { | 75 | struct powerdomain wkup_omap2_pwrdm = { |
| 86 | .name = "wkup_pwrdm", | 76 | .name = "wkup_pwrdm", |
| 87 | .prcm_offs = WKUP_MOD, | 77 | .prcm_offs = WKUP_MOD, |
| 88 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), | 78 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), |
| 89 | }; | 79 | }; |
| 90 | |||
| 91 | #endif | ||
| 92 | |||
| 93 | |||
| 94 | /* As powerdomains are added or removed above, this list must also be changed */ | ||
| 95 | static struct powerdomain *powerdomains_omap[] __initdata = { | ||
| 96 | |||
| 97 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) | ||
| 98 | &wkup_omap2_pwrdm, | ||
| 99 | &gfx_omap2_pwrdm, | ||
| 100 | #endif | ||
| 101 | |||
| 102 | #ifdef CONFIG_ARCH_OMAP2 | ||
| 103 | &dsp_pwrdm, | ||
| 104 | &mpu_24xx_pwrdm, | ||
| 105 | &core_24xx_pwrdm, | ||
| 106 | #endif | ||
| 107 | |||
| 108 | #ifdef CONFIG_ARCH_OMAP2430 | ||
| 109 | &mdm_pwrdm, | ||
| 110 | #endif | ||
| 111 | |||
| 112 | #ifdef CONFIG_ARCH_OMAP3 | ||
| 113 | &iva2_pwrdm, | ||
| 114 | &mpu_3xxx_pwrdm, | ||
| 115 | &neon_pwrdm, | ||
| 116 | &core_3xxx_pre_es3_1_pwrdm, | ||
| 117 | &core_3xxx_es3_1_pwrdm, | ||
| 118 | &cam_pwrdm, | ||
| 119 | &dss_pwrdm, | ||
| 120 | &per_pwrdm, | ||
| 121 | &emu_pwrdm, | ||
| 122 | &sgx_pwrdm, | ||
| 123 | &usbhost_pwrdm, | ||
| 124 | &dpll1_pwrdm, | ||
| 125 | &dpll2_pwrdm, | ||
| 126 | &dpll3_pwrdm, | ||
| 127 | &dpll4_pwrdm, | ||
| 128 | &dpll5_pwrdm, | ||
| 129 | #endif | ||
| 130 | |||
| 131 | #ifdef CONFIG_ARCH_OMAP4 | ||
| 132 | &core_44xx_pwrdm, | ||
| 133 | &gfx_44xx_pwrdm, | ||
| 134 | &abe_44xx_pwrdm, | ||
| 135 | &dss_44xx_pwrdm, | ||
| 136 | &tesla_44xx_pwrdm, | ||
| 137 | &wkup_44xx_pwrdm, | ||
| 138 | &cpu0_44xx_pwrdm, | ||
| 139 | &cpu1_44xx_pwrdm, | ||
| 140 | &emu_44xx_pwrdm, | ||
| 141 | &mpu_44xx_pwrdm, | ||
| 142 | &ivahd_44xx_pwrdm, | ||
| 143 | &cam_44xx_pwrdm, | ||
| 144 | &l3init_44xx_pwrdm, | ||
| 145 | &l4per_44xx_pwrdm, | ||
| 146 | &always_on_core_44xx_pwrdm, | ||
| 147 | &cefuse_44xx_pwrdm, | ||
| 148 | #endif | ||
| 149 | NULL | ||
| 150 | }; | ||
| 151 | |||
| 152 | |||
| 153 | #endif | ||
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h new file mode 100644 index 000000000000..fa311669d53d --- /dev/null +++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h | |||
| @@ -0,0 +1,22 @@ | |||
| 1 | /* | ||
| 2 | * OMAP2/3 common powerdomains - prototypes | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2008-2010 Nokia Corporation | ||
| 6 | * | ||
| 7 | * Paul Walmsley | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAINS2XXX_3XXX_DATA_H | ||
| 15 | #define __ARCH_ARM_MACH_OMAP2_POWERDOMAINS2XXX_3XXX_DATA_H | ||
| 16 | |||
| 17 | #include "powerdomain.h" | ||
| 18 | |||
| 19 | extern struct powerdomain gfx_omap2_pwrdm; | ||
| 20 | extern struct powerdomain wkup_omap2_pwrdm; | ||
| 21 | |||
| 22 | #endif | ||
diff --git a/arch/arm/mach-omap2/powerdomains24xx.h b/arch/arm/mach-omap2/powerdomains2xxx_data.c index 775093add9b6..9b1a33500577 100644 --- a/arch/arm/mach-omap2/powerdomains24xx.h +++ b/arch/arm/mach-omap2/powerdomains2xxx_data.c | |||
| @@ -1,37 +1,28 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * OMAP24XX powerdomain definitions | 2 | * OMAP2XXX powerdomain definitions |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | 4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2007-2009 Nokia Corporation | 5 | * Copyright (C) 2007-2010 Nokia Corporation |
| 6 | * | 6 | * |
| 7 | * Written by Paul Walmsley | 7 | * Paul Walmsley, Jouni Högander |
| 8 | * Debugging and integration fixes by Jouni Högander | ||
| 9 | * | 8 | * |
| 10 | * This program is free software; you can redistribute it and/or modify | 9 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as | 10 | * it under the terms of the GNU General Public License version 2 as |
| 12 | * published by the Free Software Foundation. | 11 | * published by the Free Software Foundation. |
| 13 | */ | 12 | */ |
| 14 | 13 | ||
| 15 | #ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS24XX | 14 | #include <linux/kernel.h> |
| 16 | #define ARCH_ARM_MACH_OMAP2_POWERDOMAINS24XX | 15 | #include <linux/init.h> |
| 17 | 16 | ||
| 18 | /* | 17 | #include "powerdomain.h" |
| 19 | * N.B. If powerdomains are added or removed from this file, update | 18 | #include "powerdomains2xxx_3xxx_data.h" |
| 20 | * the array in mach-omap2/powerdomains.h. | ||
| 21 | */ | ||
| 22 | |||
| 23 | #include <plat/powerdomain.h> | ||
| 24 | 19 | ||
| 25 | #include "prcm-common.h" | 20 | #include "prcm-common.h" |
| 26 | #include "prm.h" | 21 | #include "prm2xxx_3xxx.h" |
| 27 | #include "prm-regbits-24xx.h" | 22 | #include "prm-regbits-24xx.h" |
| 28 | #include "cm.h" | ||
| 29 | #include "cm-regbits-24xx.h" | ||
| 30 | 23 | ||
| 31 | /* 24XX powerdomains and dependencies */ | 24 | /* 24XX powerdomains and dependencies */ |
| 32 | 25 | ||
| 33 | #ifdef CONFIG_ARCH_OMAP2 | ||
| 34 | |||
| 35 | /* Powerdomains */ | 26 | /* Powerdomains */ |
| 36 | 27 | ||
| 37 | static struct powerdomain dsp_pwrdm = { | 28 | static struct powerdomain dsp_pwrdm = { |
| @@ -82,9 +73,6 @@ static struct powerdomain core_24xx_pwrdm = { | |||
| 82 | }, | 73 | }, |
| 83 | }; | 74 | }; |
| 84 | 75 | ||
| 85 | #endif /* CONFIG_ARCH_OMAP2 */ | ||
| 86 | |||
| 87 | |||
| 88 | 76 | ||
| 89 | /* | 77 | /* |
| 90 | * 2430-specific powerdomains | 78 | * 2430-specific powerdomains |
| @@ -111,5 +99,25 @@ static struct powerdomain mdm_pwrdm = { | |||
| 111 | 99 | ||
| 112 | #endif /* CONFIG_ARCH_OMAP2430 */ | 100 | #endif /* CONFIG_ARCH_OMAP2430 */ |
| 113 | 101 | ||
| 102 | /* As powerdomains are added or removed above, this list must also be changed */ | ||
| 103 | static struct powerdomain *powerdomains_omap2xxx[] __initdata = { | ||
| 114 | 104 | ||
| 105 | &wkup_omap2_pwrdm, | ||
| 106 | &gfx_omap2_pwrdm, | ||
| 107 | |||
| 108 | #ifdef CONFIG_ARCH_OMAP2 | ||
| 109 | &dsp_pwrdm, | ||
| 110 | &mpu_24xx_pwrdm, | ||
| 111 | &core_24xx_pwrdm, | ||
| 115 | #endif | 112 | #endif |
| 113 | |||
| 114 | #ifdef CONFIG_ARCH_OMAP2430 | ||
| 115 | &mdm_pwrdm, | ||
| 116 | #endif | ||
| 117 | NULL | ||
| 118 | }; | ||
| 119 | |||
| 120 | void __init omap2xxx_powerdomains_init(void) | ||
| 121 | { | ||
| 122 | pwrdm_init(powerdomains_omap2xxx, &omap2_pwrdm_operations); | ||
| 123 | } | ||
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains3xxx_data.c index fa904861668b..e1bec562625b 100644 --- a/arch/arm/mach-omap2/powerdomains34xx.h +++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c | |||
| @@ -4,28 +4,23 @@ | |||
| 4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | 4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2007-2010 Nokia Corporation | 5 | * Copyright (C) 2007-2010 Nokia Corporation |
| 6 | * | 6 | * |
| 7 | * Written by Paul Walmsley | 7 | * Paul Walmsley, Jouni Högander |
| 8 | * Debugging and integration fixes by Jouni Högander | ||
| 9 | * | 8 | * |
| 10 | * This program is free software; you can redistribute it and/or modify | 9 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as | 10 | * it under the terms of the GNU General Public License version 2 as |
| 12 | * published by the Free Software Foundation. | 11 | * published by the Free Software Foundation. |
| 13 | */ | 12 | */ |
| 14 | 13 | ||
| 15 | #ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX | 14 | #include <linux/kernel.h> |
| 16 | #define ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX | 15 | #include <linux/init.h> |
| 17 | 16 | ||
| 18 | /* | 17 | #include "powerdomain.h" |
| 19 | * N.B. If powerdomains are added or removed from this file, update | 18 | #include "powerdomains2xxx_3xxx_data.h" |
| 20 | * the array in mach-omap2/powerdomains.h. | ||
| 21 | */ | ||
| 22 | |||
| 23 | #include <plat/powerdomain.h> | ||
| 24 | 19 | ||
| 25 | #include "prcm-common.h" | 20 | #include "prcm-common.h" |
| 26 | #include "prm.h" | 21 | #include "prm2xxx_3xxx.h" |
| 27 | #include "prm-regbits-34xx.h" | 22 | #include "prm-regbits-34xx.h" |
| 28 | #include "cm.h" | 23 | #include "cm2xxx_3xxx.h" |
| 29 | #include "cm-regbits-34xx.h" | 24 | #include "cm-regbits-34xx.h" |
| 30 | 25 | ||
| 31 | /* | 26 | /* |
| @@ -80,6 +75,10 @@ static struct powerdomain mpu_3xxx_pwrdm = { | |||
| 80 | * 3430s upto ES3.0 and 3630ES1.0. Hence this feature | 75 | * 3430s upto ES3.0 and 3630ES1.0. Hence this feature |
| 81 | * needs to be disabled on these chips. | 76 | * needs to be disabled on these chips. |
| 82 | * Refer: 3430 errata ID i459 and 3630 errata ID i579 | 77 | * Refer: 3430 errata ID i459 and 3630 errata ID i579 |
| 78 | * | ||
| 79 | * Note: setting the SAR flag could help for errata ID i478 | ||
| 80 | * which applies to 3430 <= ES3.1, but since the SAR feature | ||
| 81 | * is broken, do not use it. | ||
| 83 | */ | 82 | */ |
| 84 | static struct powerdomain core_3xxx_pre_es3_1_pwrdm = { | 83 | static struct powerdomain core_3xxx_pre_es3_1_pwrdm = { |
| 85 | .name = "core_pwrdm", | 84 | .name = "core_pwrdm", |
| @@ -108,6 +107,10 @@ static struct powerdomain core_3xxx_es3_1_pwrdm = { | |||
| 108 | CHIP_GE_OMAP3630ES1_1), | 107 | CHIP_GE_OMAP3630ES1_1), |
| 109 | .pwrsts = PWRSTS_OFF_RET_ON, | 108 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 110 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | 109 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
| 110 | /* | ||
| 111 | * Setting the SAR flag for errata ID i478 which applies | ||
| 112 | * to 3430 <= ES3.1 | ||
| 113 | */ | ||
| 111 | .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */ | 114 | .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */ |
| 112 | .banks = 2, | 115 | .banks = 2, |
| 113 | .pwrsts_mem_ret = { | 116 | .pwrsts_mem_ret = { |
| @@ -252,8 +255,33 @@ static struct powerdomain dpll5_pwrdm = { | |||
| 252 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), | 255 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), |
| 253 | }; | 256 | }; |
| 254 | 257 | ||
| 258 | /* As powerdomains are added or removed above, this list must also be changed */ | ||
| 259 | static struct powerdomain *powerdomains_omap3xxx[] __initdata = { | ||
| 255 | 260 | ||
| 256 | #endif /* CONFIG_ARCH_OMAP3 */ | 261 | &wkup_omap2_pwrdm, |
| 262 | &gfx_omap2_pwrdm, | ||
| 263 | &iva2_pwrdm, | ||
| 264 | &mpu_3xxx_pwrdm, | ||
| 265 | &neon_pwrdm, | ||
| 266 | &core_3xxx_pre_es3_1_pwrdm, | ||
| 267 | &core_3xxx_es3_1_pwrdm, | ||
| 268 | &cam_pwrdm, | ||
| 269 | &dss_pwrdm, | ||
| 270 | &per_pwrdm, | ||
| 271 | &emu_pwrdm, | ||
| 272 | &sgx_pwrdm, | ||
| 273 | &usbhost_pwrdm, | ||
| 274 | &dpll1_pwrdm, | ||
| 275 | &dpll2_pwrdm, | ||
| 276 | &dpll3_pwrdm, | ||
| 277 | &dpll4_pwrdm, | ||
| 278 | &dpll5_pwrdm, | ||
| 279 | #endif | ||
| 280 | NULL | ||
| 281 | }; | ||
| 257 | 282 | ||
| 258 | 283 | ||
| 259 | #endif | 284 | void __init omap3xxx_powerdomains_init(void) |
| 285 | { | ||
| 286 | pwrdm_init(powerdomains_omap3xxx, &omap3_pwrdm_operations); | ||
| 287 | } | ||
diff --git a/arch/arm/mach-omap2/powerdomains44xx.h b/arch/arm/mach-omap2/powerdomains44xx_data.c index 9c01b55d6102..26d7641076d7 100644 --- a/arch/arm/mach-omap2/powerdomains44xx.h +++ b/arch/arm/mach-omap2/powerdomains44xx_data.c | |||
| @@ -19,23 +19,22 @@ | |||
| 19 | * published by the Free Software Foundation. | 19 | * published by the Free Software Foundation. |
| 20 | */ | 20 | */ |
| 21 | 21 | ||
| 22 | #ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAINS44XX_H | 22 | #include <linux/kernel.h> |
| 23 | #define __ARCH_ARM_MACH_OMAP2_POWERDOMAINS44XX_H | 23 | #include <linux/init.h> |
| 24 | 24 | ||
| 25 | #include <plat/powerdomain.h> | 25 | #include "powerdomain.h" |
| 26 | 26 | ||
| 27 | #include "prcm-common.h" | 27 | #include "prcm-common.h" |
| 28 | #include "cm.h" | 28 | #include "prcm44xx.h" |
| 29 | #include "cm-regbits-44xx.h" | ||
| 30 | #include "prm.h" | ||
| 31 | #include "prm-regbits-44xx.h" | 29 | #include "prm-regbits-44xx.h" |
| 32 | 30 | #include "prm44xx.h" | |
| 33 | #if defined(CONFIG_ARCH_OMAP4) | 31 | #include "prcm_mpu44xx.h" |
| 34 | 32 | ||
| 35 | /* core_44xx_pwrdm: CORE power domain */ | 33 | /* core_44xx_pwrdm: CORE power domain */ |
| 36 | static struct powerdomain core_44xx_pwrdm = { | 34 | static struct powerdomain core_44xx_pwrdm = { |
| 37 | .name = "core_pwrdm", | 35 | .name = "core_pwrdm", |
| 38 | .prcm_offs = OMAP4430_PRM_CORE_MOD, | 36 | .prcm_offs = OMAP4430_PRM_CORE_INST, |
| 37 | .prcm_partition = OMAP4430_PRM_PARTITION, | ||
| 39 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 38 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 40 | .pwrsts = PWRSTS_RET_ON, | 39 | .pwrsts = PWRSTS_RET_ON, |
| 41 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | 40 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
| @@ -60,7 +59,8 @@ static struct powerdomain core_44xx_pwrdm = { | |||
| 60 | /* gfx_44xx_pwrdm: 3D accelerator power domain */ | 59 | /* gfx_44xx_pwrdm: 3D accelerator power domain */ |
| 61 | static struct powerdomain gfx_44xx_pwrdm = { | 60 | static struct powerdomain gfx_44xx_pwrdm = { |
| 62 | .name = "gfx_pwrdm", | 61 | .name = "gfx_pwrdm", |
| 63 | .prcm_offs = OMAP4430_PRM_GFX_MOD, | 62 | .prcm_offs = OMAP4430_PRM_GFX_INST, |
| 63 | .prcm_partition = OMAP4430_PRM_PARTITION, | ||
| 64 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 64 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 65 | .pwrsts = PWRSTS_OFF_ON, | 65 | .pwrsts = PWRSTS_OFF_ON, |
| 66 | .banks = 1, | 66 | .banks = 1, |
| @@ -76,7 +76,8 @@ static struct powerdomain gfx_44xx_pwrdm = { | |||
| 76 | /* abe_44xx_pwrdm: Audio back end power domain */ | 76 | /* abe_44xx_pwrdm: Audio back end power domain */ |
| 77 | static struct powerdomain abe_44xx_pwrdm = { | 77 | static struct powerdomain abe_44xx_pwrdm = { |
| 78 | .name = "abe_pwrdm", | 78 | .name = "abe_pwrdm", |
| 79 | .prcm_offs = OMAP4430_PRM_ABE_MOD, | 79 | .prcm_offs = OMAP4430_PRM_ABE_INST, |
| 80 | .prcm_partition = OMAP4430_PRM_PARTITION, | ||
| 80 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 81 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 81 | .pwrsts = PWRSTS_OFF_RET_ON, | 82 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 82 | .pwrsts_logic_ret = PWRDM_POWER_OFF, | 83 | .pwrsts_logic_ret = PWRDM_POWER_OFF, |
| @@ -95,7 +96,8 @@ static struct powerdomain abe_44xx_pwrdm = { | |||
| 95 | /* dss_44xx_pwrdm: Display subsystem power domain */ | 96 | /* dss_44xx_pwrdm: Display subsystem power domain */ |
| 96 | static struct powerdomain dss_44xx_pwrdm = { | 97 | static struct powerdomain dss_44xx_pwrdm = { |
| 97 | .name = "dss_pwrdm", | 98 | .name = "dss_pwrdm", |
| 98 | .prcm_offs = OMAP4430_PRM_DSS_MOD, | 99 | .prcm_offs = OMAP4430_PRM_DSS_INST, |
| 100 | .prcm_partition = OMAP4430_PRM_PARTITION, | ||
| 99 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 101 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 100 | .pwrsts = PWRSTS_OFF_RET_ON, | 102 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 101 | .pwrsts_logic_ret = PWRSTS_OFF, | 103 | .pwrsts_logic_ret = PWRSTS_OFF, |
| @@ -112,7 +114,8 @@ static struct powerdomain dss_44xx_pwrdm = { | |||
| 112 | /* tesla_44xx_pwrdm: Tesla processor power domain */ | 114 | /* tesla_44xx_pwrdm: Tesla processor power domain */ |
| 113 | static struct powerdomain tesla_44xx_pwrdm = { | 115 | static struct powerdomain tesla_44xx_pwrdm = { |
| 114 | .name = "tesla_pwrdm", | 116 | .name = "tesla_pwrdm", |
| 115 | .prcm_offs = OMAP4430_PRM_TESLA_MOD, | 117 | .prcm_offs = OMAP4430_PRM_TESLA_INST, |
| 118 | .prcm_partition = OMAP4430_PRM_PARTITION, | ||
| 116 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 119 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 117 | .pwrsts = PWRSTS_OFF_RET_ON, | 120 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 118 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | 121 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
| @@ -133,7 +136,8 @@ static struct powerdomain tesla_44xx_pwrdm = { | |||
| 133 | /* wkup_44xx_pwrdm: Wake-up power domain */ | 136 | /* wkup_44xx_pwrdm: Wake-up power domain */ |
| 134 | static struct powerdomain wkup_44xx_pwrdm = { | 137 | static struct powerdomain wkup_44xx_pwrdm = { |
| 135 | .name = "wkup_pwrdm", | 138 | .name = "wkup_pwrdm", |
| 136 | .prcm_offs = OMAP4430_PRM_WKUP_MOD, | 139 | .prcm_offs = OMAP4430_PRM_WKUP_INST, |
| 140 | .prcm_partition = OMAP4430_PRM_PARTITION, | ||
| 137 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 141 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 138 | .pwrsts = PWRSTS_ON, | 142 | .pwrsts = PWRSTS_ON, |
| 139 | .banks = 1, | 143 | .banks = 1, |
| @@ -148,7 +152,8 @@ static struct powerdomain wkup_44xx_pwrdm = { | |||
| 148 | /* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */ | 152 | /* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */ |
| 149 | static struct powerdomain cpu0_44xx_pwrdm = { | 153 | static struct powerdomain cpu0_44xx_pwrdm = { |
| 150 | .name = "cpu0_pwrdm", | 154 | .name = "cpu0_pwrdm", |
| 151 | .prcm_offs = OMAP4430_PRCM_MPU_CPU0_MOD, | 155 | .prcm_offs = OMAP4430_PRCM_MPU_CPU0_INST, |
| 156 | .prcm_partition = OMAP4430_PRCM_MPU_PARTITION, | ||
| 152 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 157 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 153 | .pwrsts = PWRSTS_OFF_RET_ON, | 158 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 154 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | 159 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
| @@ -164,7 +169,8 @@ static struct powerdomain cpu0_44xx_pwrdm = { | |||
| 164 | /* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */ | 169 | /* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */ |
| 165 | static struct powerdomain cpu1_44xx_pwrdm = { | 170 | static struct powerdomain cpu1_44xx_pwrdm = { |
| 166 | .name = "cpu1_pwrdm", | 171 | .name = "cpu1_pwrdm", |
| 167 | .prcm_offs = OMAP4430_PRCM_MPU_CPU1_MOD, | 172 | .prcm_offs = OMAP4430_PRCM_MPU_CPU1_INST, |
| 173 | .prcm_partition = OMAP4430_PRCM_MPU_PARTITION, | ||
| 168 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 174 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 169 | .pwrsts = PWRSTS_OFF_RET_ON, | 175 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 170 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | 176 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
| @@ -180,7 +186,8 @@ static struct powerdomain cpu1_44xx_pwrdm = { | |||
| 180 | /* emu_44xx_pwrdm: Emulation power domain */ | 186 | /* emu_44xx_pwrdm: Emulation power domain */ |
| 181 | static struct powerdomain emu_44xx_pwrdm = { | 187 | static struct powerdomain emu_44xx_pwrdm = { |
| 182 | .name = "emu_pwrdm", | 188 | .name = "emu_pwrdm", |
| 183 | .prcm_offs = OMAP4430_PRM_EMU_MOD, | 189 | .prcm_offs = OMAP4430_PRM_EMU_INST, |
| 190 | .prcm_partition = OMAP4430_PRM_PARTITION, | ||
| 184 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 191 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 185 | .pwrsts = PWRSTS_OFF_ON, | 192 | .pwrsts = PWRSTS_OFF_ON, |
| 186 | .banks = 1, | 193 | .banks = 1, |
| @@ -195,7 +202,8 @@ static struct powerdomain emu_44xx_pwrdm = { | |||
| 195 | /* mpu_44xx_pwrdm: Modena processor and the Neon coprocessor power domain */ | 202 | /* mpu_44xx_pwrdm: Modena processor and the Neon coprocessor power domain */ |
| 196 | static struct powerdomain mpu_44xx_pwrdm = { | 203 | static struct powerdomain mpu_44xx_pwrdm = { |
| 197 | .name = "mpu_pwrdm", | 204 | .name = "mpu_pwrdm", |
| 198 | .prcm_offs = OMAP4430_PRM_MPU_MOD, | 205 | .prcm_offs = OMAP4430_PRM_MPU_INST, |
| 206 | .prcm_partition = OMAP4430_PRM_PARTITION, | ||
| 199 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 207 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 200 | .pwrsts = PWRSTS_OFF_RET_ON, | 208 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 201 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | 209 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
| @@ -215,7 +223,8 @@ static struct powerdomain mpu_44xx_pwrdm = { | |||
| 215 | /* ivahd_44xx_pwrdm: IVA-HD power domain */ | 223 | /* ivahd_44xx_pwrdm: IVA-HD power domain */ |
| 216 | static struct powerdomain ivahd_44xx_pwrdm = { | 224 | static struct powerdomain ivahd_44xx_pwrdm = { |
| 217 | .name = "ivahd_pwrdm", | 225 | .name = "ivahd_pwrdm", |
| 218 | .prcm_offs = OMAP4430_PRM_IVAHD_MOD, | 226 | .prcm_offs = OMAP4430_PRM_IVAHD_INST, |
| 227 | .prcm_partition = OMAP4430_PRM_PARTITION, | ||
| 219 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 228 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 220 | .pwrsts = PWRSTS_OFF_RET_ON, | 229 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 221 | .pwrsts_logic_ret = PWRDM_POWER_OFF, | 230 | .pwrsts_logic_ret = PWRDM_POWER_OFF, |
| @@ -238,7 +247,8 @@ static struct powerdomain ivahd_44xx_pwrdm = { | |||
| 238 | /* cam_44xx_pwrdm: Camera subsystem power domain */ | 247 | /* cam_44xx_pwrdm: Camera subsystem power domain */ |
| 239 | static struct powerdomain cam_44xx_pwrdm = { | 248 | static struct powerdomain cam_44xx_pwrdm = { |
| 240 | .name = "cam_pwrdm", | 249 | .name = "cam_pwrdm", |
| 241 | .prcm_offs = OMAP4430_PRM_CAM_MOD, | 250 | .prcm_offs = OMAP4430_PRM_CAM_INST, |
| 251 | .prcm_partition = OMAP4430_PRM_PARTITION, | ||
| 242 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 252 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 243 | .pwrsts = PWRSTS_OFF_ON, | 253 | .pwrsts = PWRSTS_OFF_ON, |
| 244 | .banks = 1, | 254 | .banks = 1, |
| @@ -254,9 +264,10 @@ static struct powerdomain cam_44xx_pwrdm = { | |||
| 254 | /* l3init_44xx_pwrdm: L3 initators pheripherals power domain */ | 264 | /* l3init_44xx_pwrdm: L3 initators pheripherals power domain */ |
| 255 | static struct powerdomain l3init_44xx_pwrdm = { | 265 | static struct powerdomain l3init_44xx_pwrdm = { |
| 256 | .name = "l3init_pwrdm", | 266 | .name = "l3init_pwrdm", |
| 257 | .prcm_offs = OMAP4430_PRM_L3INIT_MOD, | 267 | .prcm_offs = OMAP4430_PRM_L3INIT_INST, |
| 268 | .prcm_partition = OMAP4430_PRM_PARTITION, | ||
| 258 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 269 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 259 | .pwrsts = PWRSTS_OFF_RET_ON, | 270 | .pwrsts = PWRSTS_RET_ON, |
| 260 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | 271 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
| 261 | .banks = 1, | 272 | .banks = 1, |
| 262 | .pwrsts_mem_ret = { | 273 | .pwrsts_mem_ret = { |
| @@ -271,9 +282,10 @@ static struct powerdomain l3init_44xx_pwrdm = { | |||
| 271 | /* l4per_44xx_pwrdm: Target peripherals power domain */ | 282 | /* l4per_44xx_pwrdm: Target peripherals power domain */ |
| 272 | static struct powerdomain l4per_44xx_pwrdm = { | 283 | static struct powerdomain l4per_44xx_pwrdm = { |
| 273 | .name = "l4per_pwrdm", | 284 | .name = "l4per_pwrdm", |
| 274 | .prcm_offs = OMAP4430_PRM_L4PER_MOD, | 285 | .prcm_offs = OMAP4430_PRM_L4PER_INST, |
| 286 | .prcm_partition = OMAP4430_PRM_PARTITION, | ||
| 275 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 287 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 276 | .pwrsts = PWRSTS_OFF_RET_ON, | 288 | .pwrsts = PWRSTS_RET_ON, |
| 277 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | 289 | .pwrsts_logic_ret = PWRSTS_OFF_RET, |
| 278 | .banks = 2, | 290 | .banks = 2, |
| 279 | .pwrsts_mem_ret = { | 291 | .pwrsts_mem_ret = { |
| @@ -293,7 +305,8 @@ static struct powerdomain l4per_44xx_pwrdm = { | |||
| 293 | */ | 305 | */ |
| 294 | static struct powerdomain always_on_core_44xx_pwrdm = { | 306 | static struct powerdomain always_on_core_44xx_pwrdm = { |
| 295 | .name = "always_on_core_pwrdm", | 307 | .name = "always_on_core_pwrdm", |
| 296 | .prcm_offs = OMAP4430_PRM_ALWAYS_ON_MOD, | 308 | .prcm_offs = OMAP4430_PRM_ALWAYS_ON_INST, |
| 309 | .prcm_partition = OMAP4430_PRM_PARTITION, | ||
| 297 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 310 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 298 | .pwrsts = PWRSTS_ON, | 311 | .pwrsts = PWRSTS_ON, |
| 299 | }; | 312 | }; |
| @@ -301,7 +314,8 @@ static struct powerdomain always_on_core_44xx_pwrdm = { | |||
| 301 | /* cefuse_44xx_pwrdm: Customer efuse controller power domain */ | 314 | /* cefuse_44xx_pwrdm: Customer efuse controller power domain */ |
| 302 | static struct powerdomain cefuse_44xx_pwrdm = { | 315 | static struct powerdomain cefuse_44xx_pwrdm = { |
| 303 | .name = "cefuse_pwrdm", | 316 | .name = "cefuse_pwrdm", |
| 304 | .prcm_offs = OMAP4430_PRM_CEFUSE_MOD, | 317 | .prcm_offs = OMAP4430_PRM_CEFUSE_INST, |
| 318 | .prcm_partition = OMAP4430_PRM_PARTITION, | ||
| 305 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 319 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 306 | .pwrsts = PWRSTS_OFF_ON, | 320 | .pwrsts = PWRSTS_OFF_ON, |
| 307 | }; | 321 | }; |
| @@ -314,6 +328,28 @@ static struct powerdomain cefuse_44xx_pwrdm = { | |||
| 314 | * stdefuse | 328 | * stdefuse |
| 315 | */ | 329 | */ |
| 316 | 330 | ||
| 317 | #endif | 331 | /* As powerdomains are added or removed above, this list must also be changed */ |
| 332 | static struct powerdomain *powerdomains_omap44xx[] __initdata = { | ||
| 333 | &core_44xx_pwrdm, | ||
| 334 | &gfx_44xx_pwrdm, | ||
| 335 | &abe_44xx_pwrdm, | ||
| 336 | &dss_44xx_pwrdm, | ||
| 337 | &tesla_44xx_pwrdm, | ||
| 338 | &wkup_44xx_pwrdm, | ||
| 339 | &cpu0_44xx_pwrdm, | ||
| 340 | &cpu1_44xx_pwrdm, | ||
| 341 | &emu_44xx_pwrdm, | ||
| 342 | &mpu_44xx_pwrdm, | ||
| 343 | &ivahd_44xx_pwrdm, | ||
| 344 | &cam_44xx_pwrdm, | ||
| 345 | &l3init_44xx_pwrdm, | ||
| 346 | &l4per_44xx_pwrdm, | ||
| 347 | &always_on_core_44xx_pwrdm, | ||
| 348 | &cefuse_44xx_pwrdm, | ||
| 349 | NULL | ||
| 350 | }; | ||
| 318 | 351 | ||
| 319 | #endif | 352 | void __init omap44xx_powerdomains_init(void) |
| 353 | { | ||
| 354 | pwrdm_init(powerdomains_omap44xx, &omap4_pwrdm_operations); | ||
| 355 | } | ||
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index f81acee4738d..87486f559784 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h | |||
| @@ -8,15 +8,12 @@ | |||
| 8 | * Copyright (C) 2007-2009 Nokia Corporation | 8 | * Copyright (C) 2007-2009 Nokia Corporation |
| 9 | * | 9 | * |
| 10 | * Written by Paul Walmsley | 10 | * Written by Paul Walmsley |
| 11 | * OMAP4 defines in this file are automatically generated from the OMAP hardware | ||
| 12 | * databases. | ||
| 13 | * | 11 | * |
| 14 | * This program is free software; you can redistribute it and/or modify | 12 | * This program is free software; you can redistribute it and/or modify |
| 15 | * it under the terms of the GNU General Public License version 2 as | 13 | * it under the terms of the GNU General Public License version 2 as |
| 16 | * published by the Free Software Foundation. | 14 | * published by the Free Software Foundation. |
| 17 | */ | 15 | */ |
| 18 | 16 | ||
| 19 | |||
| 20 | /* Module offsets from both CM_BASE & PRM_BASE */ | 17 | /* Module offsets from both CM_BASE & PRM_BASE */ |
| 21 | 18 | ||
| 22 | /* | 19 | /* |
| @@ -51,75 +48,6 @@ | |||
| 51 | #define OMAP3430_NEON_MOD 0xb00 | 48 | #define OMAP3430_NEON_MOD 0xb00 |
| 52 | #define OMAP3430ES2_USBHOST_MOD 0xc00 | 49 | #define OMAP3430ES2_USBHOST_MOD 0xc00 |
| 53 | 50 | ||
| 54 | #define BITS(n_bit) \ | ||
| 55 | (((1 << n_bit) - 1) | (1 << n_bit)) | ||
| 56 | |||
| 57 | #define BITFIELD(l_bit, u_bit) \ | ||
| 58 | (BITS(u_bit) & ~((BITS(l_bit)) >> 1)) | ||
| 59 | |||
| 60 | /* OMAP44XX specific module offsets */ | ||
| 61 | |||
| 62 | /* CM1 instances */ | ||
| 63 | |||
| 64 | #define OMAP4430_CM1_OCP_SOCKET_MOD 0x0000 | ||
| 65 | #define OMAP4430_CM1_CKGEN_MOD 0x0100 | ||
| 66 | #define OMAP4430_CM1_MPU_MOD 0x0300 | ||
| 67 | #define OMAP4430_CM1_TESLA_MOD 0x0400 | ||
| 68 | #define OMAP4430_CM1_ABE_MOD 0x0500 | ||
| 69 | #define OMAP4430_CM1_RESTORE_MOD 0x0e00 | ||
| 70 | #define OMAP4430_CM1_INSTR_MOD 0x0f00 | ||
| 71 | |||
| 72 | /* CM2 instances */ | ||
| 73 | |||
| 74 | #define OMAP4430_CM2_OCP_SOCKET_MOD 0x0000 | ||
| 75 | #define OMAP4430_CM2_CKGEN_MOD 0x0100 | ||
| 76 | #define OMAP4430_CM2_ALWAYS_ON_MOD 0x0600 | ||
| 77 | #define OMAP4430_CM2_CORE_MOD 0x0700 | ||
| 78 | #define OMAP4430_CM2_IVAHD_MOD 0x0f00 | ||
| 79 | #define OMAP4430_CM2_CAM_MOD 0x1000 | ||
| 80 | #define OMAP4430_CM2_DSS_MOD 0x1100 | ||
| 81 | #define OMAP4430_CM2_GFX_MOD 0x1200 | ||
| 82 | #define OMAP4430_CM2_L3INIT_MOD 0x1300 | ||
| 83 | #define OMAP4430_CM2_L4PER_MOD 0x1400 | ||
| 84 | #define OMAP4430_CM2_CEFUSE_MOD 0x1600 | ||
| 85 | #define OMAP4430_CM2_RESTORE_MOD 0x1e00 | ||
| 86 | #define OMAP4430_CM2_INSTR_MOD 0x1f00 | ||
| 87 | |||
| 88 | /* PRM instances */ | ||
| 89 | |||
| 90 | #define OMAP4430_PRM_OCP_SOCKET_MOD 0x0000 | ||
| 91 | #define OMAP4430_PRM_CKGEN_MOD 0x0100 | ||
| 92 | #define OMAP4430_PRM_MPU_MOD 0x0300 | ||
| 93 | #define OMAP4430_PRM_TESLA_MOD 0x0400 | ||
| 94 | #define OMAP4430_PRM_ABE_MOD 0x0500 | ||
| 95 | #define OMAP4430_PRM_ALWAYS_ON_MOD 0x0600 | ||
| 96 | #define OMAP4430_PRM_CORE_MOD 0x0700 | ||
| 97 | #define OMAP4430_PRM_IVAHD_MOD 0x0f00 | ||
| 98 | #define OMAP4430_PRM_CAM_MOD 0x1000 | ||
| 99 | #define OMAP4430_PRM_DSS_MOD 0x1100 | ||
| 100 | #define OMAP4430_PRM_GFX_MOD 0x1200 | ||
| 101 | #define OMAP4430_PRM_L3INIT_MOD 0x1300 | ||
| 102 | #define OMAP4430_PRM_L4PER_MOD 0x1400 | ||
| 103 | #define OMAP4430_PRM_CEFUSE_MOD 0x1600 | ||
| 104 | #define OMAP4430_PRM_WKUP_MOD 0x1700 | ||
| 105 | #define OMAP4430_PRM_WKUP_CM_MOD 0x1800 | ||
| 106 | #define OMAP4430_PRM_EMU_MOD 0x1900 | ||
| 107 | #define OMAP4430_PRM_EMU_CM_MOD 0x1a00 | ||
| 108 | #define OMAP4430_PRM_DEVICE_MOD 0x1b00 | ||
| 109 | #define OMAP4430_PRM_INSTR_MOD 0x1f00 | ||
| 110 | |||
| 111 | /* SCRM instances */ | ||
| 112 | |||
| 113 | #define OMAP4430_SCRM_SCRM_MOD 0x0000 | ||
| 114 | |||
| 115 | /* PRCM_MPU instances */ | ||
| 116 | |||
| 117 | #define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD 0x0000 | ||
| 118 | #define OMAP4430_PRCM_MPU_DEVICE_PRM_MOD 0x0200 | ||
| 119 | #define OMAP4430_PRCM_MPU_CPU0_MOD 0x0400 | ||
| 120 | #define OMAP4430_PRCM_MPU_CPU1_MOD 0x0800 | ||
| 121 | |||
| 122 | |||
| 123 | /* 24XX register bits shared between CM & PRM registers */ | 51 | /* 24XX register bits shared between CM & PRM registers */ |
| 124 | 52 | ||
| 125 | /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ | 53 | /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ |
| @@ -461,5 +389,18 @@ | |||
| 461 | #define OMAP3430_EN_CORE_SHIFT 0 | 389 | #define OMAP3430_EN_CORE_SHIFT 0 |
| 462 | #define OMAP3430_EN_CORE_MASK (1 << 0) | 390 | #define OMAP3430_EN_CORE_MASK (1 << 0) |
| 463 | 391 | ||
| 392 | |||
| 393 | /* | ||
| 394 | * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP | ||
| 395 | * submodule to exit hardreset | ||
| 396 | */ | ||
| 397 | #define MAX_MODULE_HARDRESET_WAIT 10000 | ||
| 398 | |||
| 399 | # ifndef __ASSEMBLER__ | ||
| 400 | extern void __iomem *prm_base; | ||
| 401 | extern void __iomem *cm_base; | ||
| 402 | extern void __iomem *cm2_base; | ||
| 403 | # endif | ||
| 404 | |||
| 464 | #endif | 405 | #endif |
| 465 | 406 | ||
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index a51846e3a6fa..679bcd28576e 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c | |||
| @@ -17,7 +17,8 @@ | |||
| 17 | * it under the terms of the GNU General Public License version 2 as | 17 | * it under the terms of the GNU General Public License version 2 as |
| 18 | * published by the Free Software Foundation. | 18 | * published by the Free Software Foundation. |
| 19 | */ | 19 | */ |
| 20 | #include <linux/module.h> | 20 | |
| 21 | #include <linux/kernel.h> | ||
| 21 | #include <linux/init.h> | 22 | #include <linux/init.h> |
| 22 | #include <linux/clk.h> | 23 | #include <linux/clk.h> |
| 23 | #include <linux/io.h> | 24 | #include <linux/io.h> |
| @@ -29,105 +30,27 @@ | |||
| 29 | 30 | ||
| 30 | #include "clock.h" | 31 | #include "clock.h" |
| 31 | #include "clock2xxx.h" | 32 | #include "clock2xxx.h" |
| 32 | #include "cm.h" | 33 | #include "cm2xxx_3xxx.h" |
| 33 | #include "prm.h" | 34 | #include "prm2xxx_3xxx.h" |
| 35 | #include "prm44xx.h" | ||
| 36 | #include "prminst44xx.h" | ||
| 34 | #include "prm-regbits-24xx.h" | 37 | #include "prm-regbits-24xx.h" |
| 35 | #include "prm-regbits-44xx.h" | 38 | #include "prm-regbits-44xx.h" |
| 36 | #include "control.h" | 39 | #include "control.h" |
| 37 | 40 | ||
| 38 | static void __iomem *prm_base; | 41 | void __iomem *prm_base; |
| 39 | static void __iomem *cm_base; | 42 | void __iomem *cm_base; |
| 40 | static void __iomem *cm2_base; | 43 | void __iomem *cm2_base; |
| 41 | 44 | ||
| 42 | #define MAX_MODULE_ENABLE_WAIT 100000 | 45 | #define MAX_MODULE_ENABLE_WAIT 100000 |
| 43 | 46 | ||
| 44 | struct omap3_prcm_regs { | ||
| 45 | u32 control_padconf_sys_nirq; | ||
| 46 | u32 iva2_cm_clksel1; | ||
| 47 | u32 iva2_cm_clksel2; | ||
| 48 | u32 cm_sysconfig; | ||
| 49 | u32 sgx_cm_clksel; | ||
| 50 | u32 dss_cm_clksel; | ||
| 51 | u32 cam_cm_clksel; | ||
| 52 | u32 per_cm_clksel; | ||
| 53 | u32 emu_cm_clksel; | ||
| 54 | u32 emu_cm_clkstctrl; | ||
| 55 | u32 pll_cm_autoidle2; | ||
| 56 | u32 pll_cm_clksel4; | ||
| 57 | u32 pll_cm_clksel5; | ||
| 58 | u32 pll_cm_clken2; | ||
| 59 | u32 cm_polctrl; | ||
| 60 | u32 iva2_cm_fclken; | ||
| 61 | u32 iva2_cm_clken_pll; | ||
| 62 | u32 core_cm_fclken1; | ||
| 63 | u32 core_cm_fclken3; | ||
| 64 | u32 sgx_cm_fclken; | ||
| 65 | u32 wkup_cm_fclken; | ||
| 66 | u32 dss_cm_fclken; | ||
| 67 | u32 cam_cm_fclken; | ||
| 68 | u32 per_cm_fclken; | ||
| 69 | u32 usbhost_cm_fclken; | ||
| 70 | u32 core_cm_iclken1; | ||
| 71 | u32 core_cm_iclken2; | ||
| 72 | u32 core_cm_iclken3; | ||
| 73 | u32 sgx_cm_iclken; | ||
| 74 | u32 wkup_cm_iclken; | ||
| 75 | u32 dss_cm_iclken; | ||
| 76 | u32 cam_cm_iclken; | ||
| 77 | u32 per_cm_iclken; | ||
| 78 | u32 usbhost_cm_iclken; | ||
| 79 | u32 iva2_cm_autiidle2; | ||
| 80 | u32 mpu_cm_autoidle2; | ||
| 81 | u32 iva2_cm_clkstctrl; | ||
| 82 | u32 mpu_cm_clkstctrl; | ||
| 83 | u32 core_cm_clkstctrl; | ||
| 84 | u32 sgx_cm_clkstctrl; | ||
| 85 | u32 dss_cm_clkstctrl; | ||
| 86 | u32 cam_cm_clkstctrl; | ||
| 87 | u32 per_cm_clkstctrl; | ||
| 88 | u32 neon_cm_clkstctrl; | ||
| 89 | u32 usbhost_cm_clkstctrl; | ||
| 90 | u32 core_cm_autoidle1; | ||
| 91 | u32 core_cm_autoidle2; | ||
| 92 | u32 core_cm_autoidle3; | ||
| 93 | u32 wkup_cm_autoidle; | ||
| 94 | u32 dss_cm_autoidle; | ||
| 95 | u32 cam_cm_autoidle; | ||
| 96 | u32 per_cm_autoidle; | ||
| 97 | u32 usbhost_cm_autoidle; | ||
| 98 | u32 sgx_cm_sleepdep; | ||
| 99 | u32 dss_cm_sleepdep; | ||
| 100 | u32 cam_cm_sleepdep; | ||
| 101 | u32 per_cm_sleepdep; | ||
| 102 | u32 usbhost_cm_sleepdep; | ||
| 103 | u32 cm_clkout_ctrl; | ||
| 104 | u32 prm_clkout_ctrl; | ||
| 105 | u32 sgx_pm_wkdep; | ||
| 106 | u32 dss_pm_wkdep; | ||
| 107 | u32 cam_pm_wkdep; | ||
| 108 | u32 per_pm_wkdep; | ||
| 109 | u32 neon_pm_wkdep; | ||
| 110 | u32 usbhost_pm_wkdep; | ||
| 111 | u32 core_pm_mpugrpsel1; | ||
| 112 | u32 iva2_pm_ivagrpsel1; | ||
| 113 | u32 core_pm_mpugrpsel3; | ||
| 114 | u32 core_pm_ivagrpsel3; | ||
| 115 | u32 wkup_pm_mpugrpsel; | ||
| 116 | u32 wkup_pm_ivagrpsel; | ||
| 117 | u32 per_pm_mpugrpsel; | ||
| 118 | u32 per_pm_ivagrpsel; | ||
| 119 | u32 wkup_pm_wken; | ||
| 120 | }; | ||
| 121 | |||
| 122 | static struct omap3_prcm_regs prcm_context; | ||
| 123 | |||
| 124 | u32 omap_prcm_get_reset_sources(void) | 47 | u32 omap_prcm_get_reset_sources(void) |
| 125 | { | 48 | { |
| 126 | /* XXX This presumably needs modification for 34XX */ | 49 | /* XXX This presumably needs modification for 34XX */ |
| 127 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | 50 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) |
| 128 | return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f; | 51 | return omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f; |
| 129 | if (cpu_is_omap44xx()) | 52 | if (cpu_is_omap44xx()) |
| 130 | return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f; | 53 | return omap2_prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f; |
| 131 | 54 | ||
| 132 | return 0; | 55 | return 0; |
| 133 | } | 56 | } |
| @@ -143,126 +66,46 @@ void omap_prcm_arch_reset(char mode, const char *cmd) | |||
| 143 | 66 | ||
| 144 | prcm_offs = WKUP_MOD; | 67 | prcm_offs = WKUP_MOD; |
| 145 | } else if (cpu_is_omap34xx()) { | 68 | } else if (cpu_is_omap34xx()) { |
| 146 | u32 l; | ||
| 147 | |||
| 148 | prcm_offs = OMAP3430_GR_MOD; | 69 | prcm_offs = OMAP3430_GR_MOD; |
| 149 | l = ('B' << 24) | ('M' << 16) | (cmd ? (u8)*cmd : 0); | 70 | omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0)); |
| 150 | /* Reserve the first word in scratchpad for communicating | 71 | } else if (cpu_is_omap44xx()) { |
| 151 | * with the boot ROM. A pointer to a data structure | 72 | omap4_prm_global_warm_sw_reset(); /* never returns */ |
| 152 | * describing the boot process can be stored there, | 73 | } else { |
| 153 | * cf. OMAP34xx TRM, Initialization / Software Booting | ||
| 154 | * Configuration. */ | ||
| 155 | omap_writel(l, OMAP343X_SCRATCHPAD + 4); | ||
| 156 | } else if (cpu_is_omap44xx()) | ||
| 157 | prcm_offs = OMAP4430_PRM_DEVICE_MOD; | ||
| 158 | else | ||
| 159 | WARN_ON(1); | 74 | WARN_ON(1); |
| 75 | } | ||
| 160 | 76 | ||
| 161 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | 77 | /* |
| 162 | prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, | 78 | * As per Errata i520, in some cases, user will not be able to |
| 163 | OMAP2_RM_RSTCTRL); | 79 | * access DDR memory after warm-reset. |
| 164 | if (cpu_is_omap44xx()) | 80 | * This situation occurs while the warm-reset happens during a read |
| 165 | prm_set_mod_reg_bits(OMAP4430_RST_GLOBAL_WARM_SW_MASK, | 81 | * access to DDR memory. In that particular condition, DDR memory |
| 166 | prcm_offs, OMAP4_RM_RSTCTRL); | 82 | * does not respond to a corrupted read command due to the warm |
| 167 | } | 83 | * reset occurrence but SDRC is waiting for read completion. |
| 168 | 84 | * SDRC is not sensitive to the warm reset, but the interconnect is | |
| 169 | static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg) | 85 | * reset on the fly, thus causing a misalignment between SDRC logic, |
| 170 | { | 86 | * interconnect logic and DDR memory state. |
| 171 | BUG_ON(!base); | 87 | * WORKAROUND: |
| 172 | return __raw_readl(base + module + reg); | 88 | * Steps to perform before a Warm reset is trigged: |
| 173 | } | 89 | * 1. enable self-refresh on idle request |
| 174 | 90 | * 2. put SDRC in idle | |
| 175 | static inline void __omap_prcm_write(u32 value, void __iomem *base, | 91 | * 3. wait until SDRC goes to idle |
| 176 | s16 module, u16 reg) | 92 | * 4. generate SW reset (Global SW reset) |
| 177 | { | 93 | * |
| 178 | BUG_ON(!base); | 94 | * Steps to be performed after warm reset occurs (in bootloader): |
| 179 | __raw_writel(value, base + module + reg); | 95 | * if HW warm reset is the source, apply below steps before any |
| 180 | } | 96 | * accesses to SDRAM: |
| 181 | 97 | * 1. Reset SMS and SDRC and wait till reset is complete | |
| 182 | /* Read a register in a PRM module */ | 98 | * 2. Re-initialize SMS, SDRC and memory |
| 183 | u32 prm_read_mod_reg(s16 module, u16 idx) | 99 | * |
| 184 | { | 100 | * NOTE: Above work around is required only if arch reset is implemented |
| 185 | return __omap_prcm_read(prm_base, module, idx); | 101 | * using Global SW reset(GLOBAL_SW_RST). DPLL3 reset does not need |
| 186 | } | 102 | * the WA since it resets SDRC as well as part of cold reset. |
| 187 | 103 | */ | |
| 188 | /* Write into a register in a PRM module */ | 104 | |
| 189 | void prm_write_mod_reg(u32 val, s16 module, u16 idx) | 105 | /* XXX should be moved to some OMAP2/3 specific code */ |
| 190 | { | 106 | omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, |
| 191 | __omap_prcm_write(val, prm_base, module, idx); | 107 | OMAP2_RM_RSTCTRL); |
| 192 | } | 108 | omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */ |
| 193 | |||
| 194 | /* Read-modify-write a register in a PRM module. Caller must lock */ | ||
| 195 | u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) | ||
| 196 | { | ||
| 197 | u32 v; | ||
| 198 | |||
| 199 | v = prm_read_mod_reg(module, idx); | ||
| 200 | v &= ~mask; | ||
| 201 | v |= bits; | ||
| 202 | prm_write_mod_reg(v, module, idx); | ||
| 203 | |||
| 204 | return v; | ||
| 205 | } | ||
| 206 | |||
| 207 | /* Read a PRM register, AND it, and shift the result down to bit 0 */ | ||
| 208 | u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) | ||
| 209 | { | ||
| 210 | u32 v; | ||
| 211 | |||
| 212 | v = prm_read_mod_reg(domain, idx); | ||
| 213 | v &= mask; | ||
| 214 | v >>= __ffs(mask); | ||
| 215 | |||
| 216 | return v; | ||
| 217 | } | ||
| 218 | |||
| 219 | /* Read a PRM register, AND it, and shift the result down to bit 0 */ | ||
| 220 | u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask) | ||
| 221 | { | ||
| 222 | u32 v; | ||
| 223 | |||
| 224 | v = __raw_readl(reg); | ||
| 225 | v &= mask; | ||
| 226 | v >>= __ffs(mask); | ||
| 227 | |||
| 228 | return v; | ||
| 229 | } | ||
| 230 | |||
| 231 | /* Read-modify-write a register in a PRM module. Caller must lock */ | ||
| 232 | u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg) | ||
| 233 | { | ||
| 234 | u32 v; | ||
| 235 | |||
| 236 | v = __raw_readl(reg); | ||
| 237 | v &= ~mask; | ||
| 238 | v |= bits; | ||
| 239 | __raw_writel(v, reg); | ||
| 240 | |||
| 241 | return v; | ||
| 242 | } | ||
| 243 | /* Read a register in a CM module */ | ||
| 244 | u32 cm_read_mod_reg(s16 module, u16 idx) | ||
| 245 | { | ||
| 246 | return __omap_prcm_read(cm_base, module, idx); | ||
| 247 | } | ||
| 248 | |||
| 249 | /* Write into a register in a CM module */ | ||
| 250 | void cm_write_mod_reg(u32 val, s16 module, u16 idx) | ||
| 251 | { | ||
| 252 | __omap_prcm_write(val, cm_base, module, idx); | ||
| 253 | } | ||
| 254 | |||
| 255 | /* Read-modify-write a register in a CM module. Caller must lock */ | ||
| 256 | u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) | ||
| 257 | { | ||
| 258 | u32 v; | ||
| 259 | |||
| 260 | v = cm_read_mod_reg(module, idx); | ||
| 261 | v &= ~mask; | ||
| 262 | v |= bits; | ||
| 263 | cm_write_mod_reg(v, module, idx); | ||
| 264 | |||
| 265 | return v; | ||
| 266 | } | 109 | } |
| 267 | 110 | ||
| 268 | /** | 111 | /** |
| @@ -274,6 +117,9 @@ u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) | |||
| 274 | * | 117 | * |
| 275 | * Returns 1 if the module indicated readiness in time, or 0 if it | 118 | * Returns 1 if the module indicated readiness in time, or 0 if it |
| 276 | * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds. | 119 | * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds. |
| 120 | * | ||
| 121 | * XXX This function is deprecated. It should be removed once the | ||
| 122 | * hwmod conversion is complete. | ||
| 277 | */ | 123 | */ |
| 278 | int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest, | 124 | int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest, |
| 279 | const char *name) | 125 | const char *name) |
| @@ -316,303 +162,3 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals) | |||
| 316 | WARN_ON(!cm2_base); | 162 | WARN_ON(!cm2_base); |
| 317 | } | 163 | } |
| 318 | } | 164 | } |
| 319 | |||
| 320 | #ifdef CONFIG_ARCH_OMAP3 | ||
| 321 | void omap3_prcm_save_context(void) | ||
| 322 | { | ||
| 323 | prcm_context.control_padconf_sys_nirq = | ||
| 324 | omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ); | ||
| 325 | prcm_context.iva2_cm_clksel1 = | ||
| 326 | cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1); | ||
| 327 | prcm_context.iva2_cm_clksel2 = | ||
| 328 | cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2); | ||
| 329 | prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG); | ||
| 330 | prcm_context.sgx_cm_clksel = | ||
| 331 | cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL); | ||
| 332 | prcm_context.dss_cm_clksel = | ||
| 333 | cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL); | ||
| 334 | prcm_context.cam_cm_clksel = | ||
| 335 | cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL); | ||
| 336 | prcm_context.per_cm_clksel = | ||
| 337 | cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL); | ||
| 338 | prcm_context.emu_cm_clksel = | ||
| 339 | cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1); | ||
| 340 | prcm_context.emu_cm_clkstctrl = | ||
| 341 | cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL); | ||
| 342 | prcm_context.pll_cm_autoidle2 = | ||
| 343 | cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2); | ||
| 344 | prcm_context.pll_cm_clksel4 = | ||
| 345 | cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4); | ||
| 346 | prcm_context.pll_cm_clksel5 = | ||
| 347 | cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5); | ||
| 348 | prcm_context.pll_cm_clken2 = | ||
| 349 | cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2); | ||
| 350 | prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL); | ||
| 351 | prcm_context.iva2_cm_fclken = | ||
| 352 | cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN); | ||
| 353 | prcm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD, | ||
| 354 | OMAP3430_CM_CLKEN_PLL); | ||
| 355 | prcm_context.core_cm_fclken1 = | ||
| 356 | cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); | ||
| 357 | prcm_context.core_cm_fclken3 = | ||
| 358 | cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3); | ||
| 359 | prcm_context.sgx_cm_fclken = | ||
| 360 | cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN); | ||
| 361 | prcm_context.wkup_cm_fclken = | ||
| 362 | cm_read_mod_reg(WKUP_MOD, CM_FCLKEN); | ||
| 363 | prcm_context.dss_cm_fclken = | ||
| 364 | cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN); | ||
| 365 | prcm_context.cam_cm_fclken = | ||
| 366 | cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN); | ||
| 367 | prcm_context.per_cm_fclken = | ||
| 368 | cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN); | ||
| 369 | prcm_context.usbhost_cm_fclken = | ||
| 370 | cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); | ||
| 371 | prcm_context.core_cm_iclken1 = | ||
| 372 | cm_read_mod_reg(CORE_MOD, CM_ICLKEN1); | ||
| 373 | prcm_context.core_cm_iclken2 = | ||
| 374 | cm_read_mod_reg(CORE_MOD, CM_ICLKEN2); | ||
| 375 | prcm_context.core_cm_iclken3 = | ||
| 376 | cm_read_mod_reg(CORE_MOD, CM_ICLKEN3); | ||
| 377 | prcm_context.sgx_cm_iclken = | ||
| 378 | cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN); | ||
| 379 | prcm_context.wkup_cm_iclken = | ||
| 380 | cm_read_mod_reg(WKUP_MOD, CM_ICLKEN); | ||
| 381 | prcm_context.dss_cm_iclken = | ||
| 382 | cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN); | ||
| 383 | prcm_context.cam_cm_iclken = | ||
| 384 | cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN); | ||
| 385 | prcm_context.per_cm_iclken = | ||
| 386 | cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN); | ||
| 387 | prcm_context.usbhost_cm_iclken = | ||
| 388 | cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); | ||
| 389 | prcm_context.iva2_cm_autiidle2 = | ||
| 390 | cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2); | ||
| 391 | prcm_context.mpu_cm_autoidle2 = | ||
| 392 | cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2); | ||
| 393 | prcm_context.iva2_cm_clkstctrl = | ||
| 394 | cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL); | ||
| 395 | prcm_context.mpu_cm_clkstctrl = | ||
| 396 | cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL); | ||
| 397 | prcm_context.core_cm_clkstctrl = | ||
| 398 | cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL); | ||
| 399 | prcm_context.sgx_cm_clkstctrl = | ||
| 400 | cm_read_mod_reg(OMAP3430ES2_SGX_MOD, | ||
| 401 | OMAP2_CM_CLKSTCTRL); | ||
| 402 | prcm_context.dss_cm_clkstctrl = | ||
| 403 | cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL); | ||
| 404 | prcm_context.cam_cm_clkstctrl = | ||
| 405 | cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL); | ||
| 406 | prcm_context.per_cm_clkstctrl = | ||
| 407 | cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL); | ||
| 408 | prcm_context.neon_cm_clkstctrl = | ||
| 409 | cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL); | ||
| 410 | prcm_context.usbhost_cm_clkstctrl = | ||
| 411 | cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, | ||
| 412 | OMAP2_CM_CLKSTCTRL); | ||
| 413 | prcm_context.core_cm_autoidle1 = | ||
| 414 | cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1); | ||
| 415 | prcm_context.core_cm_autoidle2 = | ||
| 416 | cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2); | ||
| 417 | prcm_context.core_cm_autoidle3 = | ||
| 418 | cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3); | ||
| 419 | prcm_context.wkup_cm_autoidle = | ||
| 420 | cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE); | ||
| 421 | prcm_context.dss_cm_autoidle = | ||
| 422 | cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE); | ||
| 423 | prcm_context.cam_cm_autoidle = | ||
| 424 | cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE); | ||
| 425 | prcm_context.per_cm_autoidle = | ||
| 426 | cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); | ||
| 427 | prcm_context.usbhost_cm_autoidle = | ||
| 428 | cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); | ||
| 429 | prcm_context.sgx_cm_sleepdep = | ||
| 430 | cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP); | ||
| 431 | prcm_context.dss_cm_sleepdep = | ||
| 432 | cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP); | ||
| 433 | prcm_context.cam_cm_sleepdep = | ||
| 434 | cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP); | ||
| 435 | prcm_context.per_cm_sleepdep = | ||
| 436 | cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP); | ||
| 437 | prcm_context.usbhost_cm_sleepdep = | ||
| 438 | cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP); | ||
| 439 | prcm_context.cm_clkout_ctrl = cm_read_mod_reg(OMAP3430_CCR_MOD, | ||
| 440 | OMAP3_CM_CLKOUT_CTRL_OFFSET); | ||
| 441 | prcm_context.prm_clkout_ctrl = prm_read_mod_reg(OMAP3430_CCR_MOD, | ||
| 442 | OMAP3_PRM_CLKOUT_CTRL_OFFSET); | ||
| 443 | prcm_context.sgx_pm_wkdep = | ||
| 444 | prm_read_mod_reg(OMAP3430ES2_SGX_MOD, PM_WKDEP); | ||
| 445 | prcm_context.dss_pm_wkdep = | ||
| 446 | prm_read_mod_reg(OMAP3430_DSS_MOD, PM_WKDEP); | ||
| 447 | prcm_context.cam_pm_wkdep = | ||
| 448 | prm_read_mod_reg(OMAP3430_CAM_MOD, PM_WKDEP); | ||
| 449 | prcm_context.per_pm_wkdep = | ||
| 450 | prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKDEP); | ||
| 451 | prcm_context.neon_pm_wkdep = | ||
| 452 | prm_read_mod_reg(OMAP3430_NEON_MOD, PM_WKDEP); | ||
| 453 | prcm_context.usbhost_pm_wkdep = | ||
| 454 | prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKDEP); | ||
| 455 | prcm_context.core_pm_mpugrpsel1 = | ||
| 456 | prm_read_mod_reg(CORE_MOD, OMAP3430_PM_MPUGRPSEL1); | ||
| 457 | prcm_context.iva2_pm_ivagrpsel1 = | ||
| 458 | prm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_PM_IVAGRPSEL1); | ||
| 459 | prcm_context.core_pm_mpugrpsel3 = | ||
| 460 | prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_MPUGRPSEL3); | ||
| 461 | prcm_context.core_pm_ivagrpsel3 = | ||
| 462 | prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); | ||
| 463 | prcm_context.wkup_pm_mpugrpsel = | ||
| 464 | prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_MPUGRPSEL); | ||
| 465 | prcm_context.wkup_pm_ivagrpsel = | ||
| 466 | prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_IVAGRPSEL); | ||
| 467 | prcm_context.per_pm_mpugrpsel = | ||
| 468 | prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); | ||
| 469 | prcm_context.per_pm_ivagrpsel = | ||
| 470 | prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); | ||
| 471 | prcm_context.wkup_pm_wken = prm_read_mod_reg(WKUP_MOD, PM_WKEN); | ||
| 472 | return; | ||
| 473 | } | ||
| 474 | |||
| 475 | void omap3_prcm_restore_context(void) | ||
| 476 | { | ||
| 477 | omap_ctrl_writel(prcm_context.control_padconf_sys_nirq, | ||
| 478 | OMAP343X_CONTROL_PADCONF_SYSNIRQ); | ||
| 479 | cm_write_mod_reg(prcm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD, | ||
| 480 | CM_CLKSEL1); | ||
| 481 | cm_write_mod_reg(prcm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD, | ||
| 482 | CM_CLKSEL2); | ||
| 483 | __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG); | ||
| 484 | cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD, | ||
| 485 | CM_CLKSEL); | ||
| 486 | cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD, | ||
| 487 | CM_CLKSEL); | ||
| 488 | cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD, | ||
| 489 | CM_CLKSEL); | ||
| 490 | cm_write_mod_reg(prcm_context.per_cm_clksel, OMAP3430_PER_MOD, | ||
| 491 | CM_CLKSEL); | ||
| 492 | cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD, | ||
| 493 | CM_CLKSEL1); | ||
| 494 | cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD, | ||
| 495 | OMAP2_CM_CLKSTCTRL); | ||
| 496 | cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD, | ||
| 497 | CM_AUTOIDLE2); | ||
| 498 | cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD, | ||
| 499 | OMAP3430ES2_CM_CLKSEL4); | ||
| 500 | cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD, | ||
| 501 | OMAP3430ES2_CM_CLKSEL5); | ||
| 502 | cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD, | ||
| 503 | OMAP3430ES2_CM_CLKEN2); | ||
| 504 | __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL); | ||
| 505 | cm_write_mod_reg(prcm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD, | ||
| 506 | CM_FCLKEN); | ||
| 507 | cm_write_mod_reg(prcm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD, | ||
| 508 | OMAP3430_CM_CLKEN_PLL); | ||
| 509 | cm_write_mod_reg(prcm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1); | ||
| 510 | cm_write_mod_reg(prcm_context.core_cm_fclken3, CORE_MOD, | ||
| 511 | OMAP3430ES2_CM_FCLKEN3); | ||
| 512 | cm_write_mod_reg(prcm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD, | ||
| 513 | CM_FCLKEN); | ||
| 514 | cm_write_mod_reg(prcm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN); | ||
| 515 | cm_write_mod_reg(prcm_context.dss_cm_fclken, OMAP3430_DSS_MOD, | ||
| 516 | CM_FCLKEN); | ||
| 517 | cm_write_mod_reg(prcm_context.cam_cm_fclken, OMAP3430_CAM_MOD, | ||
| 518 | CM_FCLKEN); | ||
| 519 | cm_write_mod_reg(prcm_context.per_cm_fclken, OMAP3430_PER_MOD, | ||
| 520 | CM_FCLKEN); | ||
| 521 | cm_write_mod_reg(prcm_context.usbhost_cm_fclken, | ||
| 522 | OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); | ||
| 523 | cm_write_mod_reg(prcm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1); | ||
| 524 | cm_write_mod_reg(prcm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2); | ||
| 525 | cm_write_mod_reg(prcm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3); | ||
| 526 | cm_write_mod_reg(prcm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD, | ||
| 527 | CM_ICLKEN); | ||
| 528 | cm_write_mod_reg(prcm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN); | ||
| 529 | cm_write_mod_reg(prcm_context.dss_cm_iclken, OMAP3430_DSS_MOD, | ||
| 530 | CM_ICLKEN); | ||
| 531 | cm_write_mod_reg(prcm_context.cam_cm_iclken, OMAP3430_CAM_MOD, | ||
| 532 | CM_ICLKEN); | ||
| 533 | cm_write_mod_reg(prcm_context.per_cm_iclken, OMAP3430_PER_MOD, | ||
| 534 | CM_ICLKEN); | ||
| 535 | cm_write_mod_reg(prcm_context.usbhost_cm_iclken, | ||
| 536 | OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); | ||
| 537 | cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD, | ||
| 538 | CM_AUTOIDLE2); | ||
| 539 | cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2); | ||
| 540 | cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD, | ||
| 541 | OMAP2_CM_CLKSTCTRL); | ||
| 542 | cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, | ||
| 543 | OMAP2_CM_CLKSTCTRL); | ||
| 544 | cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD, | ||
| 545 | OMAP2_CM_CLKSTCTRL); | ||
| 546 | cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD, | ||
| 547 | OMAP2_CM_CLKSTCTRL); | ||
| 548 | cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD, | ||
| 549 | OMAP2_CM_CLKSTCTRL); | ||
| 550 | cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD, | ||
| 551 | OMAP2_CM_CLKSTCTRL); | ||
| 552 | cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD, | ||
| 553 | OMAP2_CM_CLKSTCTRL); | ||
| 554 | cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD, | ||
| 555 | OMAP2_CM_CLKSTCTRL); | ||
| 556 | cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl, | ||
| 557 | OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL); | ||
| 558 | cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD, | ||
| 559 | CM_AUTOIDLE1); | ||
| 560 | cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD, | ||
| 561 | CM_AUTOIDLE2); | ||
| 562 | cm_write_mod_reg(prcm_context.core_cm_autoidle3, CORE_MOD, | ||
| 563 | CM_AUTOIDLE3); | ||
| 564 | cm_write_mod_reg(prcm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE); | ||
| 565 | cm_write_mod_reg(prcm_context.dss_cm_autoidle, OMAP3430_DSS_MOD, | ||
| 566 | CM_AUTOIDLE); | ||
| 567 | cm_write_mod_reg(prcm_context.cam_cm_autoidle, OMAP3430_CAM_MOD, | ||
| 568 | CM_AUTOIDLE); | ||
| 569 | cm_write_mod_reg(prcm_context.per_cm_autoidle, OMAP3430_PER_MOD, | ||
| 570 | CM_AUTOIDLE); | ||
| 571 | cm_write_mod_reg(prcm_context.usbhost_cm_autoidle, | ||
| 572 | OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); | ||
| 573 | cm_write_mod_reg(prcm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD, | ||
| 574 | OMAP3430_CM_SLEEPDEP); | ||
| 575 | cm_write_mod_reg(prcm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD, | ||
| 576 | OMAP3430_CM_SLEEPDEP); | ||
| 577 | cm_write_mod_reg(prcm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD, | ||
| 578 | OMAP3430_CM_SLEEPDEP); | ||
| 579 | cm_write_mod_reg(prcm_context.per_cm_sleepdep, OMAP3430_PER_MOD, | ||
| 580 | OMAP3430_CM_SLEEPDEP); | ||
| 581 | cm_write_mod_reg(prcm_context.usbhost_cm_sleepdep, | ||
| 582 | OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP); | ||
| 583 | cm_write_mod_reg(prcm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD, | ||
| 584 | OMAP3_CM_CLKOUT_CTRL_OFFSET); | ||
| 585 | prm_write_mod_reg(prcm_context.prm_clkout_ctrl, OMAP3430_CCR_MOD, | ||
| 586 | OMAP3_PRM_CLKOUT_CTRL_OFFSET); | ||
| 587 | prm_write_mod_reg(prcm_context.sgx_pm_wkdep, OMAP3430ES2_SGX_MOD, | ||
| 588 | PM_WKDEP); | ||
| 589 | prm_write_mod_reg(prcm_context.dss_pm_wkdep, OMAP3430_DSS_MOD, | ||
| 590 | PM_WKDEP); | ||
| 591 | prm_write_mod_reg(prcm_context.cam_pm_wkdep, OMAP3430_CAM_MOD, | ||
| 592 | PM_WKDEP); | ||
| 593 | prm_write_mod_reg(prcm_context.per_pm_wkdep, OMAP3430_PER_MOD, | ||
| 594 | PM_WKDEP); | ||
| 595 | prm_write_mod_reg(prcm_context.neon_pm_wkdep, OMAP3430_NEON_MOD, | ||
| 596 | PM_WKDEP); | ||
| 597 | prm_write_mod_reg(prcm_context.usbhost_pm_wkdep, | ||
| 598 | OMAP3430ES2_USBHOST_MOD, PM_WKDEP); | ||
| 599 | prm_write_mod_reg(prcm_context.core_pm_mpugrpsel1, CORE_MOD, | ||
| 600 | OMAP3430_PM_MPUGRPSEL1); | ||
| 601 | prm_write_mod_reg(prcm_context.iva2_pm_ivagrpsel1, OMAP3430_IVA2_MOD, | ||
| 602 | OMAP3430_PM_IVAGRPSEL1); | ||
| 603 | prm_write_mod_reg(prcm_context.core_pm_mpugrpsel3, CORE_MOD, | ||
| 604 | OMAP3430ES2_PM_MPUGRPSEL3); | ||
| 605 | prm_write_mod_reg(prcm_context.core_pm_ivagrpsel3, CORE_MOD, | ||
| 606 | OMAP3430ES2_PM_IVAGRPSEL3); | ||
| 607 | prm_write_mod_reg(prcm_context.wkup_pm_mpugrpsel, WKUP_MOD, | ||
| 608 | OMAP3430_PM_MPUGRPSEL); | ||
| 609 | prm_write_mod_reg(prcm_context.wkup_pm_ivagrpsel, WKUP_MOD, | ||
| 610 | OMAP3430_PM_IVAGRPSEL); | ||
| 611 | prm_write_mod_reg(prcm_context.per_pm_mpugrpsel, OMAP3430_PER_MOD, | ||
| 612 | OMAP3430_PM_MPUGRPSEL); | ||
| 613 | prm_write_mod_reg(prcm_context.per_pm_ivagrpsel, OMAP3430_PER_MOD, | ||
| 614 | OMAP3430_PM_IVAGRPSEL); | ||
| 615 | prm_write_mod_reg(prcm_context.wkup_pm_wken, WKUP_MOD, PM_WKEN); | ||
| 616 | return; | ||
| 617 | } | ||
| 618 | #endif | ||
diff --git a/arch/arm/mach-omap2/prcm44xx.h b/arch/arm/mach-omap2/prcm44xx.h new file mode 100644 index 000000000000..7334ffb9d2c1 --- /dev/null +++ b/arch/arm/mach-omap2/prcm44xx.h | |||
| @@ -0,0 +1,42 @@ | |||
| 1 | /* | ||
| 2 | * OMAP4 PRCM definitions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2010 Nokia Corporation | ||
| 6 | * | ||
| 7 | * Paul Walmsley | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | * This file contains macros and functions that are common to all of | ||
| 14 | * the PRM/CM/PRCM blocks on the OMAP4 devices: PRM, CM1, CM2, | ||
| 15 | * PRCM_MPU, SCRM | ||
| 16 | */ | ||
| 17 | |||
| 18 | #ifndef __ARCH_ARM_MACH_OMAP2_PRCM44XX_H | ||
| 19 | #define __ARCH_ARM_MACH_OMAP2_PRCM44XX_H | ||
| 20 | |||
| 21 | /* | ||
| 22 | * OMAP4 PRCM partition IDs | ||
| 23 | * | ||
| 24 | * The numbers and order are arbitrary, but 0 is reserved for the | ||
| 25 | * 'invalid' partition in case someone forgets to add a | ||
| 26 | * .prcm_partition field. | ||
| 27 | */ | ||
| 28 | #define OMAP4430_INVALID_PRCM_PARTITION 0 | ||
| 29 | #define OMAP4430_PRM_PARTITION 1 | ||
| 30 | #define OMAP4430_CM1_PARTITION 2 | ||
| 31 | #define OMAP4430_CM2_PARTITION 3 | ||
| 32 | #define OMAP4430_SCRM_PARTITION 4 | ||
| 33 | #define OMAP4430_PRCM_MPU_PARTITION 5 | ||
| 34 | |||
| 35 | /* | ||
| 36 | * OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition | ||
| 37 | * IDs, plus one | ||
| 38 | */ | ||
| 39 | #define OMAP4_MAX_PRCM_PARTITIONS 6 | ||
| 40 | |||
| 41 | |||
| 42 | #endif | ||
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.c b/arch/arm/mach-omap2/prcm_mpu44xx.c new file mode 100644 index 000000000000..171fe171a749 --- /dev/null +++ b/arch/arm/mach-omap2/prcm_mpu44xx.c | |||
| @@ -0,0 +1,45 @@ | |||
| 1 | /* | ||
| 2 | * OMAP4 PRCM_MPU module functions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Nokia Corporation | ||
| 5 | * Paul Walmsley | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/types.h> | ||
| 14 | #include <linux/errno.h> | ||
| 15 | #include <linux/err.h> | ||
| 16 | #include <linux/io.h> | ||
| 17 | |||
| 18 | #include <plat/common.h> | ||
| 19 | |||
| 20 | #include "prcm_mpu44xx.h" | ||
| 21 | #include "cm-regbits-44xx.h" | ||
| 22 | |||
| 23 | /* PRCM_MPU low-level functions */ | ||
| 24 | |||
| 25 | u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 reg) | ||
| 26 | { | ||
| 27 | return __raw_readl(OMAP44XX_PRCM_MPU_REGADDR(inst, reg)); | ||
| 28 | } | ||
| 29 | |||
| 30 | void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 reg) | ||
| 31 | { | ||
| 32 | __raw_writel(val, OMAP44XX_PRCM_MPU_REGADDR(inst, reg)); | ||
| 33 | } | ||
| 34 | |||
| 35 | u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg) | ||
| 36 | { | ||
| 37 | u32 v; | ||
| 38 | |||
| 39 | v = omap4_prcm_mpu_read_inst_reg(inst, reg); | ||
| 40 | v &= ~mask; | ||
| 41 | v |= bits; | ||
| 42 | omap4_prcm_mpu_write_inst_reg(v, inst, reg); | ||
| 43 | |||
| 44 | return v; | ||
| 45 | } | ||
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h new file mode 100644 index 000000000000..729a644ce852 --- /dev/null +++ b/arch/arm/mach-omap2/prcm_mpu44xx.h | |||
| @@ -0,0 +1,104 @@ | |||
| 1 | /* | ||
| 2 | * OMAP44xx PRCM MPU instance offset macros | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2010 Nokia Corporation | ||
| 6 | * | ||
| 7 | * Paul Walmsley (paul@pwsan.com) | ||
| 8 | * Rajendra Nayak (rnayak@ti.com) | ||
| 9 | * Benoit Cousson (b-cousson@ti.com) | ||
| 10 | * | ||
| 11 | * This file is automatically generated from the OMAP hardware databases. | ||
| 12 | * We respectfully ask that any modifications to this file be coordinated | ||
| 13 | * with the public linux-omap@vger.kernel.org mailing list and the | ||
| 14 | * authors above to ensure that the autogeneration scripts are kept | ||
| 15 | * up-to-date with the file contents. | ||
| 16 | * | ||
| 17 | * This program is free software; you can redistribute it and/or modify | ||
| 18 | * it under the terms of the GNU General Public License version 2 as | ||
| 19 | * published by the Free Software Foundation. | ||
| 20 | * | ||
| 21 | * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX", | ||
| 22 | * or "OMAP4430". | ||
| 23 | */ | ||
| 24 | |||
| 25 | #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H | ||
| 26 | #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H | ||
| 27 | |||
| 28 | #define OMAP4430_PRCM_MPU_BASE 0x48243000 | ||
| 29 | |||
| 30 | #define OMAP44XX_PRCM_MPU_REGADDR(inst, reg) \ | ||
| 31 | OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg)) | ||
| 32 | |||
| 33 | /* PRCM_MPU instances */ | ||
| 34 | |||
| 35 | #define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000 | ||
| 36 | #define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200 | ||
| 37 | #define OMAP4430_PRCM_MPU_CPU0_INST 0x0400 | ||
| 38 | #define OMAP4430_PRCM_MPU_CPU1_INST 0x0800 | ||
| 39 | |||
| 40 | /* PRCM_MPU clockdomain register offsets (from instance start) */ | ||
| 41 | #define OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS 0x0000 | ||
| 42 | #define OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS 0x0000 | ||
| 43 | |||
| 44 | |||
| 45 | /* | ||
| 46 | * PRCM_MPU | ||
| 47 | * | ||
| 48 | * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global) | ||
| 49 | * point of view the PRCM_MPU is a single entity. It shares the same | ||
| 50 | * programming model as the global PRCM and thus can be assimilate as two new | ||
| 51 | * MOD inside the PRCM | ||
| 52 | */ | ||
| 53 | |||
| 54 | /* PRCM_MPU.OCP_SOCKET_PRCM register offsets */ | ||
| 55 | #define OMAP4_REVISION_PRCM_OFFSET 0x0000 | ||
| 56 | #define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000) | ||
| 57 | |||
| 58 | /* PRCM_MPU.DEVICE_PRM register offsets */ | ||
| 59 | #define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000 | ||
| 60 | #define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000) | ||
| 61 | #define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004 | ||
| 62 | #define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004) | ||
| 63 | |||
| 64 | /* PRCM_MPU.CPU0 register offsets */ | ||
| 65 | #define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000 | ||
| 66 | #define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000) | ||
| 67 | #define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004 | ||
| 68 | #define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004) | ||
| 69 | #define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008 | ||
| 70 | #define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008) | ||
| 71 | #define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c | ||
| 72 | #define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c) | ||
| 73 | #define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010 | ||
| 74 | #define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010) | ||
| 75 | #define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014 | ||
| 76 | #define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014) | ||
| 77 | #define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018 | ||
| 78 | #define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018) | ||
| 79 | |||
| 80 | /* PRCM_MPU.CPU1 register offsets */ | ||
| 81 | #define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000 | ||
| 82 | #define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000) | ||
| 83 | #define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004 | ||
| 84 | #define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004) | ||
| 85 | #define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008 | ||
| 86 | #define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008) | ||
| 87 | #define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c | ||
| 88 | #define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c) | ||
| 89 | #define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010 | ||
| 90 | #define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010) | ||
| 91 | #define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014 | ||
| 92 | #define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014) | ||
| 93 | #define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018 | ||
| 94 | #define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018) | ||
| 95 | |||
| 96 | /* Function prototypes */ | ||
| 97 | # ifndef __ASSEMBLER__ | ||
| 98 | extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx); | ||
| 99 | extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx); | ||
| 100 | extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, | ||
| 101 | s16 idx); | ||
| 102 | # endif | ||
| 103 | |||
| 104 | #endif | ||
diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h index 0b188ffa710e..6ac966103f34 100644 --- a/arch/arm/mach-omap2/prm-regbits-24xx.h +++ b/arch/arm/mach-omap2/prm-regbits-24xx.h | |||
| @@ -14,7 +14,7 @@ | |||
| 14 | * published by the Free Software Foundation. | 14 | * published by the Free Software Foundation. |
| 15 | */ | 15 | */ |
| 16 | 16 | ||
| 17 | #include "prm.h" | 17 | #include "prm2xxx_3xxx.h" |
| 18 | 18 | ||
| 19 | /* Bits shared between registers */ | 19 | /* Bits shared between registers */ |
| 20 | 20 | ||
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h index 9e63cb743a97..64c087af6a8b 100644 --- a/arch/arm/mach-omap2/prm-regbits-34xx.h +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h | |||
| @@ -1,6 +1,3 @@ | |||
| 1 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H | ||
| 2 | #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H | ||
| 3 | |||
| 4 | /* | 1 | /* |
| 5 | * OMAP3430 Power/Reset Management register bits | 2 | * OMAP3430 Power/Reset Management register bits |
| 6 | * | 3 | * |
| @@ -13,8 +10,11 @@ | |||
| 13 | * it under the terms of the GNU General Public License version 2 as | 10 | * it under the terms of the GNU General Public License version 2 as |
| 14 | * published by the Free Software Foundation. | 11 | * published by the Free Software Foundation. |
| 15 | */ | 12 | */ |
| 13 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H | ||
| 14 | #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H | ||
| 15 | |||
| 16 | 16 | ||
| 17 | #include "prm.h" | 17 | #include "prm2xxx_3xxx.h" |
| 18 | 18 | ||
| 19 | /* Shared register bits */ | 19 | /* Shared register bits */ |
| 20 | 20 | ||
| @@ -101,8 +101,11 @@ | |||
| 101 | #define OMAP3430_GRPSEL_MCSPI3_MASK (1 << 20) | 101 | #define OMAP3430_GRPSEL_MCSPI3_MASK (1 << 20) |
| 102 | #define OMAP3430_GRPSEL_MCSPI2_MASK (1 << 19) | 102 | #define OMAP3430_GRPSEL_MCSPI2_MASK (1 << 19) |
| 103 | #define OMAP3430_GRPSEL_MCSPI1_MASK (1 << 18) | 103 | #define OMAP3430_GRPSEL_MCSPI1_MASK (1 << 18) |
| 104 | #define OMAP3430_GRPSEL_I2C3_SHIFT 17 | ||
| 104 | #define OMAP3430_GRPSEL_I2C3_MASK (1 << 17) | 105 | #define OMAP3430_GRPSEL_I2C3_MASK (1 << 17) |
| 106 | #define OMAP3430_GRPSEL_I2C2_SHIFT 16 | ||
| 105 | #define OMAP3430_GRPSEL_I2C2_MASK (1 << 16) | 107 | #define OMAP3430_GRPSEL_I2C2_MASK (1 << 16) |
| 108 | #define OMAP3430_GRPSEL_I2C1_SHIFT 15 | ||
| 106 | #define OMAP3430_GRPSEL_I2C1_MASK (1 << 15) | 109 | #define OMAP3430_GRPSEL_I2C1_MASK (1 << 15) |
| 107 | #define OMAP3430_GRPSEL_UART2_MASK (1 << 14) | 110 | #define OMAP3430_GRPSEL_UART2_MASK (1 << 14) |
| 108 | #define OMAP3430_GRPSEL_UART1_MASK (1 << 13) | 111 | #define OMAP3430_GRPSEL_UART1_MASK (1 << 13) |
diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h index 25b19b610177..6d2776f6fc08 100644 --- a/arch/arm/mach-omap2/prm-regbits-44xx.h +++ b/arch/arm/mach-omap2/prm-regbits-44xx.h | |||
| @@ -22,8 +22,6 @@ | |||
| 22 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H | 22 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H |
| 23 | #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H | 23 | #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H |
| 24 | 24 | ||
| 25 | #include "prm.h" | ||
| 26 | |||
| 27 | 25 | ||
| 28 | /* | 26 | /* |
| 29 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | 27 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, |
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index 7be040b2fdab..39d562169d18 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h | |||
| @@ -1,321 +1,20 @@ | |||
| 1 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM_H | ||
| 2 | #define __ARCH_ARM_MACH_OMAP2_PRM_H | ||
| 3 | |||
| 4 | /* | 1 | /* |
| 5 | * OMAP2/3 Power/Reset Management (PRM) register definitions | 2 | * OMAP2/3/4 Power/Reset Management (PRM) bitfield definitions |
| 6 | * | 3 | * |
| 7 | * Copyright (C) 2007-2009 Texas Instruments, Inc. | 4 | * Copyright (C) 2007-2009 Texas Instruments, Inc. |
| 8 | * Copyright (C) 2010 Nokia Corporation | 5 | * Copyright (C) 2010 Nokia Corporation |
| 9 | * | 6 | * |
| 10 | * Written by Paul Walmsley | 7 | * Paul Walmsley |
| 11 | * | 8 | * |
| 12 | * This program is free software; you can redistribute it and/or modify | 9 | * This program is free software; you can redistribute it and/or modify |
| 13 | * it under the terms of the GNU General Public License version 2 as | 10 | * it under the terms of the GNU General Public License version 2 as |
| 14 | * published by the Free Software Foundation. | 11 | * published by the Free Software Foundation. |
| 15 | */ | 12 | */ |
| 13 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM_H | ||
| 14 | #define __ARCH_ARM_MACH_OMAP2_PRM_H | ||
| 16 | 15 | ||
| 17 | #include "prcm-common.h" | 16 | #include "prcm-common.h" |
| 18 | 17 | ||
| 19 | #define OMAP2420_PRM_REGADDR(module, reg) \ | ||
| 20 | OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg)) | ||
| 21 | #define OMAP2430_PRM_REGADDR(module, reg) \ | ||
| 22 | OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg)) | ||
| 23 | #define OMAP34XX_PRM_REGADDR(module, reg) \ | ||
| 24 | OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) | ||
| 25 | #define OMAP44XX_PRM_REGADDR(module, reg) \ | ||
| 26 | OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg)) | ||
| 27 | #define OMAP44XX_PRCM_MPU_REGADDR(module, reg) \ | ||
| 28 | OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (module) + (reg)) | ||
| 29 | |||
| 30 | #include "prm44xx.h" | ||
| 31 | |||
| 32 | /* | ||
| 33 | * Architecture-specific global PRM registers | ||
| 34 | * Use __raw_{read,write}l() with these registers. | ||
| 35 | * | ||
| 36 | * With a few exceptions, these are the register names beginning with | ||
| 37 | * PRCM_* on 24xx, and PRM_* on 34xx. (The exceptions are the | ||
| 38 | * IRQSTATUS and IRQENABLE bits.) | ||
| 39 | * | ||
| 40 | */ | ||
| 41 | |||
| 42 | #define OMAP2_PRCM_REVISION_OFFSET 0x0000 | ||
| 43 | #define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000) | ||
| 44 | #define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010 | ||
| 45 | #define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010) | ||
| 46 | |||
| 47 | #define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018 | ||
| 48 | #define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018) | ||
| 49 | #define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c | ||
| 50 | #define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c) | ||
| 51 | |||
| 52 | #define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050 | ||
| 53 | #define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050) | ||
| 54 | #define OMAP2_PRCM_VOLTST_OFFSET 0x0054 | ||
| 55 | #define OMAP2420_PRCM_VOLTST OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054) | ||
| 56 | #define OMAP2_PRCM_CLKSRC_CTRL_OFFSET 0x0060 | ||
| 57 | #define OMAP2420_PRCM_CLKSRC_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060) | ||
| 58 | #define OMAP2_PRCM_CLKOUT_CTRL_OFFSET 0x0070 | ||
| 59 | #define OMAP2420_PRCM_CLKOUT_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070) | ||
| 60 | #define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET 0x0078 | ||
| 61 | #define OMAP2420_PRCM_CLKEMUL_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078) | ||
| 62 | #define OMAP2_PRCM_CLKCFG_CTRL_OFFSET 0x0080 | ||
| 63 | #define OMAP2420_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080) | ||
| 64 | #define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084 | ||
| 65 | #define OMAP2420_PRCM_CLKCFG_STATUS OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084) | ||
| 66 | #define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090 | ||
| 67 | #define OMAP2420_PRCM_VOLTSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090) | ||
| 68 | #define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094 | ||
| 69 | #define OMAP2420_PRCM_CLKSSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094) | ||
| 70 | #define OMAP2_PRCM_POLCTRL_OFFSET 0x0098 | ||
| 71 | #define OMAP2420_PRCM_POLCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098) | ||
| 72 | |||
| 73 | #define OMAP2430_PRCM_REVISION OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000) | ||
| 74 | #define OMAP2430_PRCM_SYSCONFIG OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010) | ||
| 75 | |||
| 76 | #define OMAP2430_PRCM_IRQSTATUS_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018) | ||
| 77 | #define OMAP2430_PRCM_IRQENABLE_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c) | ||
| 78 | |||
| 79 | #define OMAP2430_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050) | ||
| 80 | #define OMAP2430_PRCM_VOLTST OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054) | ||
| 81 | #define OMAP2430_PRCM_CLKSRC_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060) | ||
| 82 | #define OMAP2430_PRCM_CLKOUT_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070) | ||
| 83 | #define OMAP2430_PRCM_CLKEMUL_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078) | ||
| 84 | #define OMAP2430_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080) | ||
| 85 | #define OMAP2430_PRCM_CLKCFG_STATUS OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084) | ||
| 86 | #define OMAP2430_PRCM_VOLTSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090) | ||
| 87 | #define OMAP2430_PRCM_CLKSSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094) | ||
| 88 | #define OMAP2430_PRCM_POLCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098) | ||
| 89 | |||
| 90 | #define OMAP3_PRM_REVISION_OFFSET 0x0004 | ||
| 91 | #define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004) | ||
| 92 | #define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014 | ||
| 93 | #define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014) | ||
| 94 | |||
| 95 | #define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018 | ||
| 96 | #define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018) | ||
| 97 | #define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c | ||
| 98 | #define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c) | ||
| 99 | |||
| 100 | |||
| 101 | #define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020 | ||
| 102 | #define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020) | ||
| 103 | #define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024 | ||
| 104 | #define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024) | ||
| 105 | #define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028 | ||
| 106 | #define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028) | ||
| 107 | #define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c | ||
| 108 | #define OMAP3430_PRM_VC_CMD_VAL_0 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c) | ||
| 109 | #define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030 | ||
| 110 | #define OMAP3430_PRM_VC_CMD_VAL_1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030) | ||
| 111 | #define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034 | ||
| 112 | #define OMAP3430_PRM_VC_CH_CONF OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034) | ||
| 113 | #define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038 | ||
| 114 | #define OMAP3430_PRM_VC_I2C_CFG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038) | ||
| 115 | #define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c | ||
| 116 | #define OMAP3430_PRM_VC_BYPASS_VAL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c) | ||
| 117 | #define OMAP3_PRM_RSTCTRL_OFFSET 0x0050 | ||
| 118 | #define OMAP3430_PRM_RSTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050) | ||
| 119 | #define OMAP3_PRM_RSTTIME_OFFSET 0x0054 | ||
| 120 | #define OMAP3430_PRM_RSTTIME OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054) | ||
| 121 | #define OMAP3_PRM_RSTST_OFFSET 0x0058 | ||
| 122 | #define OMAP3430_PRM_RSTST OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058) | ||
| 123 | #define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060 | ||
| 124 | #define OMAP3430_PRM_VOLTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060) | ||
| 125 | #define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064 | ||
| 126 | #define OMAP3430_PRM_SRAM_PCHARGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064) | ||
| 127 | #define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070 | ||
| 128 | #define OMAP3430_PRM_CLKSRC_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070) | ||
| 129 | #define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090 | ||
| 130 | #define OMAP3430_PRM_VOLTSETUP1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090) | ||
| 131 | #define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094 | ||
| 132 | #define OMAP3430_PRM_VOLTOFFSET OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094) | ||
| 133 | #define OMAP3_PRM_CLKSETUP_OFFSET 0x0098 | ||
| 134 | #define OMAP3430_PRM_CLKSETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098) | ||
| 135 | #define OMAP3_PRM_POLCTRL_OFFSET 0x009c | ||
| 136 | #define OMAP3430_PRM_POLCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c) | ||
| 137 | #define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0 | ||
| 138 | #define OMAP3430_PRM_VOLTSETUP2 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0) | ||
| 139 | #define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0 | ||
| 140 | #define OMAP3430_PRM_VP1_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0) | ||
| 141 | #define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4 | ||
| 142 | #define OMAP3430_PRM_VP1_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4) | ||
| 143 | #define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8 | ||
| 144 | #define OMAP3430_PRM_VP1_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8) | ||
| 145 | #define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc | ||
| 146 | #define OMAP3430_PRM_VP1_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc) | ||
| 147 | #define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0 | ||
| 148 | #define OMAP3430_PRM_VP1_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0) | ||
| 149 | #define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4 | ||
| 150 | #define OMAP3430_PRM_VP1_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4) | ||
| 151 | #define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0 | ||
| 152 | #define OMAP3430_PRM_VP2_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0) | ||
| 153 | #define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4 | ||
| 154 | #define OMAP3430_PRM_VP2_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4) | ||
| 155 | #define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8 | ||
| 156 | #define OMAP3430_PRM_VP2_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8) | ||
| 157 | #define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc | ||
| 158 | #define OMAP3430_PRM_VP2_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc) | ||
| 159 | #define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0 | ||
| 160 | #define OMAP3430_PRM_VP2_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0) | ||
| 161 | #define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4 | ||
| 162 | #define OMAP3430_PRM_VP2_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4) | ||
| 163 | |||
| 164 | #define OMAP3_PRM_CLKSEL_OFFSET 0x0040 | ||
| 165 | #define OMAP3430_PRM_CLKSEL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040) | ||
| 166 | #define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070 | ||
| 167 | #define OMAP3430_PRM_CLKOUT_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070) | ||
| 168 | |||
| 169 | /* | ||
| 170 | * Module specific PRM registers from PRM_BASE + domain offset | ||
| 171 | * | ||
| 172 | * Use prm_{read,write}_mod_reg() with these registers. | ||
| 173 | * | ||
| 174 | * With a few exceptions, these are the register names beginning with | ||
| 175 | * {PM,RM}_* on both architectures. (The exceptions are the IRQSTATUS | ||
| 176 | * and IRQENABLE bits.) | ||
| 177 | * | ||
| 178 | */ | ||
| 179 | |||
| 180 | /* Registers appearing on both 24xx and 34xx */ | ||
| 181 | |||
| 182 | #define OMAP2_RM_RSTCTRL 0x0050 | ||
| 183 | #define OMAP2_RM_RSTTIME 0x0054 | ||
| 184 | #define OMAP2_RM_RSTST 0x0058 | ||
| 185 | #define OMAP2_PM_PWSTCTRL 0x00e0 | ||
| 186 | #define OMAP2_PM_PWSTST 0x00e4 | ||
| 187 | |||
| 188 | #define PM_WKEN 0x00a0 | ||
| 189 | #define PM_WKEN1 PM_WKEN | ||
| 190 | #define PM_WKST 0x00b0 | ||
| 191 | #define PM_WKST1 PM_WKST | ||
| 192 | #define PM_WKDEP 0x00c8 | ||
| 193 | #define PM_EVGENCTRL 0x00d4 | ||
| 194 | #define PM_EVGENONTIM 0x00d8 | ||
| 195 | #define PM_EVGENOFFTIM 0x00dc | ||
| 196 | |||
| 197 | /* Omap2 specific registers */ | ||
| 198 | #define OMAP24XX_PM_WKEN2 0x00a4 | ||
| 199 | #define OMAP24XX_PM_WKST2 0x00b4 | ||
| 200 | |||
| 201 | #define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */ | ||
| 202 | #define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */ | ||
| 203 | #define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8 | ||
| 204 | #define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc | ||
| 205 | |||
| 206 | /* Omap3 specific registers */ | ||
| 207 | #define OMAP3430ES2_PM_WKEN3 0x00f0 | ||
| 208 | #define OMAP3430ES2_PM_WKST3 0x00b8 | ||
| 209 | |||
| 210 | #define OMAP3430_PM_MPUGRPSEL 0x00a4 | ||
| 211 | #define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL | ||
| 212 | #define OMAP3430ES2_PM_MPUGRPSEL3 0x00f8 | ||
| 213 | |||
| 214 | #define OMAP3430_PM_IVAGRPSEL 0x00a8 | ||
| 215 | #define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL | ||
| 216 | #define OMAP3430ES2_PM_IVAGRPSEL3 0x00f4 | ||
| 217 | |||
| 218 | #define OMAP3430_PM_PREPWSTST 0x00e8 | ||
| 219 | |||
| 220 | #define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8 | ||
| 221 | #define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc | ||
| 222 | |||
| 223 | /* Omap4 specific registers */ | ||
| 224 | #define OMAP4_RM_RSTCTRL 0x0000 | ||
| 225 | #define OMAP4_RM_RSTTIME 0x0004 | ||
| 226 | #define OMAP4_RM_RSTST 0x0008 | ||
| 227 | #define OMAP4_PM_PWSTCTRL 0x0000 | ||
| 228 | #define OMAP4_PM_PWSTST 0x0004 | ||
| 229 | |||
| 230 | |||
| 231 | #ifndef __ASSEMBLER__ | ||
| 232 | |||
| 233 | /* Power/reset management domain register get/set */ | ||
| 234 | extern u32 prm_read_mod_reg(s16 module, u16 idx); | ||
| 235 | extern void prm_write_mod_reg(u32 val, s16 module, u16 idx); | ||
| 236 | extern u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); | ||
| 237 | |||
| 238 | /* Read-modify-write bits in a PRM register (by domain) */ | ||
| 239 | static inline u32 prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) | ||
| 240 | { | ||
| 241 | return prm_rmw_mod_reg_bits(bits, bits, module, idx); | ||
| 242 | } | ||
| 243 | |||
| 244 | static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) | ||
| 245 | { | ||
| 246 | return prm_rmw_mod_reg_bits(bits, 0x0, module, idx); | ||
| 247 | } | ||
| 248 | |||
| 249 | /* These omap2_ PRM functions apply to both OMAP2 and 3 */ | ||
| 250 | int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift); | ||
| 251 | int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift); | ||
| 252 | int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift); | ||
| 253 | |||
| 254 | int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift); | ||
| 255 | int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift); | ||
| 256 | int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift); | ||
| 257 | |||
| 258 | #endif | ||
| 259 | |||
| 260 | /* | ||
| 261 | * Bits common to specific registers | ||
| 262 | * | ||
| 263 | * The 3430 register and bit names are generally used, | ||
| 264 | * since they tend to make more sense | ||
| 265 | */ | ||
| 266 | |||
| 267 | /* PM_EVGENONTIM_MPU */ | ||
| 268 | /* Named PM_EVEGENONTIM_MPU on the 24XX */ | ||
| 269 | #define OMAP_ONTIMEVAL_SHIFT 0 | ||
| 270 | #define OMAP_ONTIMEVAL_MASK (0xffffffff << 0) | ||
| 271 | |||
| 272 | /* PM_EVGENOFFTIM_MPU */ | ||
| 273 | /* Named PM_EVEGENOFFTIM_MPU on the 24XX */ | ||
| 274 | #define OMAP_OFFTIMEVAL_SHIFT 0 | ||
| 275 | #define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0) | ||
| 276 | |||
| 277 | /* PRM_CLKSETUP and PRCM_VOLTSETUP */ | ||
| 278 | /* Named PRCM_CLKSSETUP on the 24XX */ | ||
| 279 | #define OMAP_SETUP_TIME_SHIFT 0 | ||
| 280 | #define OMAP_SETUP_TIME_MASK (0xffff << 0) | ||
| 281 | |||
| 282 | /* PRM_CLKSRC_CTRL */ | ||
| 283 | /* Named PRCM_CLKSRC_CTRL on the 24XX */ | ||
| 284 | #define OMAP_SYSCLKDIV_SHIFT 6 | ||
| 285 | #define OMAP_SYSCLKDIV_MASK (0x3 << 6) | ||
| 286 | #define OMAP_AUTOEXTCLKMODE_SHIFT 3 | ||
| 287 | #define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3) | ||
| 288 | #define OMAP_SYSCLKSEL_SHIFT 0 | ||
| 289 | #define OMAP_SYSCLKSEL_MASK (0x3 << 0) | ||
| 290 | |||
| 291 | /* PM_EVGENCTRL_MPU */ | ||
| 292 | #define OMAP_OFFLOADMODE_SHIFT 3 | ||
| 293 | #define OMAP_OFFLOADMODE_MASK (0x3 << 3) | ||
| 294 | #define OMAP_ONLOADMODE_SHIFT 1 | ||
| 295 | #define OMAP_ONLOADMODE_MASK (0x3 << 1) | ||
| 296 | #define OMAP_ENABLE_MASK (1 << 0) | ||
| 297 | |||
| 298 | /* PRM_RSTTIME */ | ||
| 299 | /* Named RM_RSTTIME_WKUP on the 24xx */ | ||
| 300 | #define OMAP_RSTTIME2_SHIFT 8 | ||
| 301 | #define OMAP_RSTTIME2_MASK (0x1f << 8) | ||
| 302 | #define OMAP_RSTTIME1_SHIFT 0 | ||
| 303 | #define OMAP_RSTTIME1_MASK (0xff << 0) | ||
| 304 | |||
| 305 | /* PRM_RSTCTRL */ | ||
| 306 | /* Named RM_RSTCTRL_WKUP on the 24xx */ | ||
| 307 | /* 2420 calls RST_DPLL3 'RST_DPLL' */ | ||
| 308 | #define OMAP_RST_DPLL3_MASK (1 << 2) | ||
| 309 | #define OMAP_RST_GS_MASK (1 << 1) | ||
| 310 | |||
| 311 | |||
| 312 | /* | ||
| 313 | * Bits common to module-shared registers | ||
| 314 | * | ||
| 315 | * Not all registers of a particular type support all of these bits - | ||
| 316 | * check TRM if you are unsure | ||
| 317 | */ | ||
| 318 | |||
| 319 | /* | 18 | /* |
| 320 | * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP | 19 | * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP |
| 321 | * | 20 | * |
| @@ -341,59 +40,6 @@ int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift); | |||
| 341 | #define OMAP_POWERSTATEST_MASK (0x3 << 0) | 40 | #define OMAP_POWERSTATEST_MASK (0x3 << 0) |
| 342 | 41 | ||
| 343 | /* | 42 | /* |
| 344 | * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is | ||
| 345 | * called 'COREWKUP_RST' | ||
| 346 | * | ||
| 347 | * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS, | ||
| 348 | * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON | ||
| 349 | */ | ||
| 350 | #define OMAP_COREDOMAINWKUP_RST_MASK (1 << 3) | ||
| 351 | |||
| 352 | /* | ||
| 353 | * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP | ||
| 354 | * | ||
| 355 | * 2430: RM_RSTST_MDM | ||
| 356 | * | ||
| 357 | * 3430: RM_RSTST_CORE, RM_RSTST_EMU | ||
| 358 | */ | ||
| 359 | #define OMAP_DOMAINWKUP_RST_MASK (1 << 2) | ||
| 360 | |||
| 361 | /* | ||
| 362 | * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP | ||
| 363 | * On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'. | ||
| 364 | * | ||
| 365 | * 2430: RM_RSTST_MDM | ||
| 366 | * | ||
| 367 | * 3430: RM_RSTST_CORE, RM_RSTST_EMU | ||
| 368 | */ | ||
| 369 | #define OMAP_GLOBALWARM_RST_MASK (1 << 1) | ||
| 370 | #define OMAP_GLOBALCOLD_RST_MASK (1 << 0) | ||
| 371 | |||
| 372 | /* | ||
| 373 | * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP | ||
| 374 | * 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP" | ||
| 375 | * | ||
| 376 | * 2430: PM_WKDEP_MDM | ||
| 377 | * | ||
| 378 | * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM, | ||
| 379 | * PM_WKDEP_PER | ||
| 380 | */ | ||
| 381 | #define OMAP_EN_WKUP_SHIFT 4 | ||
| 382 | #define OMAP_EN_WKUP_MASK (1 << 4) | ||
| 383 | |||
| 384 | /* | ||
| 385 | * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, | ||
| 386 | * PM_PWSTCTRL_DSP | ||
| 387 | * | ||
| 388 | * 2430: PM_PWSTCTRL_MDM | ||
| 389 | * | ||
| 390 | * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, | ||
| 391 | * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER, | ||
| 392 | * PM_PWSTCTRL_NEON | ||
| 393 | */ | ||
| 394 | #define OMAP_LOGICRETSTATE_MASK (1 << 2) | ||
| 395 | |||
| 396 | /* | ||
| 397 | * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, | 43 | * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, |
| 398 | * PM_PWSTCTRL_DSP, PM_PWSTST_MPU | 44 | * PM_PWSTCTRL_DSP, PM_PWSTST_MPU |
| 399 | * | 45 | * |
| @@ -407,11 +53,4 @@ int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift); | |||
| 407 | #define OMAP_POWERSTATE_MASK (0x3 << 0) | 53 | #define OMAP_POWERSTATE_MASK (0x3 << 0) |
| 408 | 54 | ||
| 409 | 55 | ||
| 410 | /* | ||
| 411 | * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP | ||
| 412 | * submodule to exit hardreset | ||
| 413 | */ | ||
| 414 | #define MAX_MODULE_HARDRESET_WAIT 10000 | ||
| 415 | |||
| 416 | |||
| 417 | #endif | 56 | #endif |
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c index 421771eee450..ec0362574b5e 100644 --- a/arch/arm/mach-omap2/prm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c | |||
| @@ -12,18 +12,65 @@ | |||
| 12 | */ | 12 | */ |
| 13 | 13 | ||
| 14 | #include <linux/kernel.h> | 14 | #include <linux/kernel.h> |
| 15 | #include <linux/delay.h> | ||
| 16 | #include <linux/errno.h> | 15 | #include <linux/errno.h> |
| 17 | #include <linux/err.h> | 16 | #include <linux/err.h> |
| 17 | #include <linux/io.h> | ||
| 18 | 18 | ||
| 19 | #include <plat/common.h> | 19 | #include <plat/common.h> |
| 20 | #include <plat/cpu.h> | 20 | #include <plat/cpu.h> |
| 21 | #include <plat/prcm.h> | 21 | #include <plat/prcm.h> |
| 22 | 22 | ||
| 23 | #include "prm.h" | 23 | #include "prm2xxx_3xxx.h" |
| 24 | #include "cm2xxx_3xxx.h" | ||
| 24 | #include "prm-regbits-24xx.h" | 25 | #include "prm-regbits-24xx.h" |
| 25 | #include "prm-regbits-34xx.h" | 26 | #include "prm-regbits-34xx.h" |
| 26 | 27 | ||
| 28 | u32 omap2_prm_read_mod_reg(s16 module, u16 idx) | ||
| 29 | { | ||
| 30 | return __raw_readl(prm_base + module + idx); | ||
| 31 | } | ||
| 32 | |||
| 33 | void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx) | ||
| 34 | { | ||
| 35 | __raw_writel(val, prm_base + module + idx); | ||
| 36 | } | ||
| 37 | |||
| 38 | /* Read-modify-write a register in a PRM module. Caller must lock */ | ||
| 39 | u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) | ||
| 40 | { | ||
| 41 | u32 v; | ||
| 42 | |||
| 43 | v = omap2_prm_read_mod_reg(module, idx); | ||
| 44 | v &= ~mask; | ||
| 45 | v |= bits; | ||
| 46 | omap2_prm_write_mod_reg(v, module, idx); | ||
| 47 | |||
| 48 | return v; | ||
| 49 | } | ||
| 50 | |||
| 51 | /* Read a PRM register, AND it, and shift the result down to bit 0 */ | ||
| 52 | u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) | ||
| 53 | { | ||
| 54 | u32 v; | ||
| 55 | |||
| 56 | v = omap2_prm_read_mod_reg(domain, idx); | ||
| 57 | v &= mask; | ||
| 58 | v >>= __ffs(mask); | ||
| 59 | |||
| 60 | return v; | ||
| 61 | } | ||
| 62 | |||
| 63 | u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) | ||
| 64 | { | ||
| 65 | return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx); | ||
| 66 | } | ||
| 67 | |||
| 68 | u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) | ||
| 69 | { | ||
| 70 | return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx); | ||
| 71 | } | ||
| 72 | |||
| 73 | |||
| 27 | /** | 74 | /** |
| 28 | * omap2_prm_is_hardreset_asserted - read the HW reset line state of | 75 | * omap2_prm_is_hardreset_asserted - read the HW reset line state of |
| 29 | * submodules contained in the hwmod module | 76 | * submodules contained in the hwmod module |
| @@ -39,7 +86,7 @@ int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift) | |||
| 39 | if (!(cpu_is_omap24xx() || cpu_is_omap34xx())) | 86 | if (!(cpu_is_omap24xx() || cpu_is_omap34xx())) |
| 40 | return -EINVAL; | 87 | return -EINVAL; |
| 41 | 88 | ||
| 42 | return prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, | 89 | return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, |
| 43 | (1 << shift)); | 90 | (1 << shift)); |
| 44 | } | 91 | } |
| 45 | 92 | ||
| @@ -63,7 +110,7 @@ int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift) | |||
| 63 | return -EINVAL; | 110 | return -EINVAL; |
| 64 | 111 | ||
| 65 | mask = 1 << shift; | 112 | mask = 1 << shift; |
| 66 | prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL); | 113 | omap2_prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL); |
| 67 | 114 | ||
| 68 | return 0; | 115 | return 0; |
| 69 | } | 116 | } |
| @@ -93,18 +140,17 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift) | |||
| 93 | mask = 1 << shift; | 140 | mask = 1 << shift; |
| 94 | 141 | ||
| 95 | /* Check the current status to avoid de-asserting the line twice */ | 142 | /* Check the current status to avoid de-asserting the line twice */ |
| 96 | if (prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, mask) == 0) | 143 | if (omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, mask) == 0) |
| 97 | return -EEXIST; | 144 | return -EEXIST; |
| 98 | 145 | ||
| 99 | /* Clear the reset status by writing 1 to the status bit */ | 146 | /* Clear the reset status by writing 1 to the status bit */ |
| 100 | prm_rmw_mod_reg_bits(0xffffffff, mask, prm_mod, OMAP2_RM_RSTST); | 147 | omap2_prm_rmw_mod_reg_bits(0xffffffff, mask, prm_mod, OMAP2_RM_RSTST); |
| 101 | /* de-assert the reset control line */ | 148 | /* de-assert the reset control line */ |
| 102 | prm_rmw_mod_reg_bits(mask, 0, prm_mod, OMAP2_RM_RSTCTRL); | 149 | omap2_prm_rmw_mod_reg_bits(mask, 0, prm_mod, OMAP2_RM_RSTCTRL); |
| 103 | /* wait the status to be set */ | 150 | /* wait the status to be set */ |
| 104 | omap_test_timeout(prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST, | 151 | omap_test_timeout(omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST, |
| 105 | mask), | 152 | mask), |
| 106 | MAX_MODULE_HARDRESET_WAIT, c); | 153 | MAX_MODULE_HARDRESET_WAIT, c); |
| 107 | 154 | ||
| 108 | return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; | 155 | return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; |
| 109 | } | 156 | } |
| 110 | |||
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h new file mode 100644 index 000000000000..53d44f6e3736 --- /dev/null +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h | |||
| @@ -0,0 +1,367 @@ | |||
| 1 | /* | ||
| 2 | * OMAP2/3 Power/Reset Management (PRM) register definitions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007-2009 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2008-2010 Nokia Corporation | ||
| 6 | * Paul Walmsley | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | * The PRM hardware modules on the OMAP2/3 are quite similar to each | ||
| 13 | * other. The PRM on OMAP4 has a new register layout, and is handled | ||
| 14 | * in a separate file. | ||
| 15 | */ | ||
| 16 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H | ||
| 17 | #define __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H | ||
| 18 | |||
| 19 | #include "prcm-common.h" | ||
| 20 | #include "prm.h" | ||
| 21 | |||
| 22 | #define OMAP2420_PRM_REGADDR(module, reg) \ | ||
| 23 | OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg)) | ||
| 24 | #define OMAP2430_PRM_REGADDR(module, reg) \ | ||
| 25 | OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg)) | ||
| 26 | #define OMAP34XX_PRM_REGADDR(module, reg) \ | ||
| 27 | OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) | ||
| 28 | |||
| 29 | |||
| 30 | /* | ||
| 31 | * OMAP2-specific global PRM registers | ||
| 32 | * Use __raw_{read,write}l() with these registers. | ||
| 33 | * | ||
| 34 | * With a few exceptions, these are the register names beginning with | ||
| 35 | * PRCM_* on 24xx. (The exceptions are the IRQSTATUS and IRQENABLE | ||
| 36 | * bits.) | ||
| 37 | * | ||
| 38 | */ | ||
| 39 | |||
| 40 | #define OMAP2_PRCM_REVISION_OFFSET 0x0000 | ||
| 41 | #define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000) | ||
| 42 | #define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010 | ||
| 43 | #define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010) | ||
| 44 | |||
| 45 | #define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018 | ||
| 46 | #define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018) | ||
| 47 | #define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c | ||
| 48 | #define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c) | ||
| 49 | |||
| 50 | #define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050 | ||
| 51 | #define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050) | ||
| 52 | #define OMAP2_PRCM_VOLTST_OFFSET 0x0054 | ||
| 53 | #define OMAP2420_PRCM_VOLTST OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054) | ||
| 54 | #define OMAP2_PRCM_CLKSRC_CTRL_OFFSET 0x0060 | ||
| 55 | #define OMAP2420_PRCM_CLKSRC_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060) | ||
| 56 | #define OMAP2_PRCM_CLKOUT_CTRL_OFFSET 0x0070 | ||
| 57 | #define OMAP2420_PRCM_CLKOUT_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070) | ||
| 58 | #define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET 0x0078 | ||
| 59 | #define OMAP2420_PRCM_CLKEMUL_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078) | ||
| 60 | #define OMAP2_PRCM_CLKCFG_CTRL_OFFSET 0x0080 | ||
| 61 | #define OMAP2420_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080) | ||
| 62 | #define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084 | ||
| 63 | #define OMAP2420_PRCM_CLKCFG_STATUS OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084) | ||
| 64 | #define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090 | ||
| 65 | #define OMAP2420_PRCM_VOLTSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090) | ||
| 66 | #define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094 | ||
| 67 | #define OMAP2420_PRCM_CLKSSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094) | ||
| 68 | #define OMAP2_PRCM_POLCTRL_OFFSET 0x0098 | ||
| 69 | #define OMAP2420_PRCM_POLCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098) | ||
| 70 | |||
| 71 | #define OMAP2430_PRCM_REVISION OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000) | ||
| 72 | #define OMAP2430_PRCM_SYSCONFIG OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010) | ||
| 73 | |||
| 74 | #define OMAP2430_PRCM_IRQSTATUS_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018) | ||
| 75 | #define OMAP2430_PRCM_IRQENABLE_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c) | ||
| 76 | |||
| 77 | #define OMAP2430_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050) | ||
| 78 | #define OMAP2430_PRCM_VOLTST OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054) | ||
| 79 | #define OMAP2430_PRCM_CLKSRC_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060) | ||
| 80 | #define OMAP2430_PRCM_CLKOUT_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070) | ||
| 81 | #define OMAP2430_PRCM_CLKEMUL_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078) | ||
| 82 | #define OMAP2430_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080) | ||
| 83 | #define OMAP2430_PRCM_CLKCFG_STATUS OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084) | ||
| 84 | #define OMAP2430_PRCM_VOLTSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090) | ||
| 85 | #define OMAP2430_PRCM_CLKSSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094) | ||
| 86 | #define OMAP2430_PRCM_POLCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098) | ||
| 87 | |||
| 88 | /* | ||
| 89 | * OMAP3-specific global PRM registers | ||
| 90 | * Use __raw_{read,write}l() with these registers. | ||
| 91 | * | ||
| 92 | * With a few exceptions, these are the register names beginning with | ||
| 93 | * PRM_* on 34xx. (The exceptions are the IRQSTATUS and IRQENABLE | ||
| 94 | * bits.) | ||
| 95 | */ | ||
| 96 | |||
| 97 | #define OMAP3_PRM_REVISION_OFFSET 0x0004 | ||
| 98 | #define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004) | ||
| 99 | #define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014 | ||
| 100 | #define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014) | ||
| 101 | |||
| 102 | #define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018 | ||
| 103 | #define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018) | ||
| 104 | #define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c | ||
| 105 | #define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c) | ||
| 106 | |||
| 107 | |||
| 108 | #define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020 | ||
| 109 | #define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020) | ||
| 110 | #define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024 | ||
| 111 | #define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024) | ||
| 112 | #define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028 | ||
| 113 | #define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028) | ||
| 114 | #define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c | ||
| 115 | #define OMAP3430_PRM_VC_CMD_VAL_0 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c) | ||
| 116 | #define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030 | ||
| 117 | #define OMAP3430_PRM_VC_CMD_VAL_1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030) | ||
| 118 | #define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034 | ||
| 119 | #define OMAP3430_PRM_VC_CH_CONF OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034) | ||
| 120 | #define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038 | ||
| 121 | #define OMAP3430_PRM_VC_I2C_CFG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038) | ||
| 122 | #define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c | ||
| 123 | #define OMAP3430_PRM_VC_BYPASS_VAL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c) | ||
| 124 | #define OMAP3_PRM_RSTCTRL_OFFSET 0x0050 | ||
| 125 | #define OMAP3430_PRM_RSTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050) | ||
| 126 | #define OMAP3_PRM_RSTTIME_OFFSET 0x0054 | ||
| 127 | #define OMAP3430_PRM_RSTTIME OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054) | ||
| 128 | #define OMAP3_PRM_RSTST_OFFSET 0x0058 | ||
| 129 | #define OMAP3430_PRM_RSTST OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058) | ||
| 130 | #define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060 | ||
| 131 | #define OMAP3430_PRM_VOLTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060) | ||
| 132 | #define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064 | ||
| 133 | #define OMAP3430_PRM_SRAM_PCHARGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064) | ||
| 134 | #define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070 | ||
| 135 | #define OMAP3430_PRM_CLKSRC_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070) | ||
| 136 | #define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090 | ||
| 137 | #define OMAP3430_PRM_VOLTSETUP1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090) | ||
| 138 | #define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094 | ||
| 139 | #define OMAP3430_PRM_VOLTOFFSET OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094) | ||
| 140 | #define OMAP3_PRM_CLKSETUP_OFFSET 0x0098 | ||
| 141 | #define OMAP3430_PRM_CLKSETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098) | ||
| 142 | #define OMAP3_PRM_POLCTRL_OFFSET 0x009c | ||
| 143 | #define OMAP3430_PRM_POLCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c) | ||
| 144 | #define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0 | ||
| 145 | #define OMAP3430_PRM_VOLTSETUP2 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0) | ||
| 146 | #define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0 | ||
| 147 | #define OMAP3430_PRM_VP1_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0) | ||
| 148 | #define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4 | ||
| 149 | #define OMAP3430_PRM_VP1_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4) | ||
| 150 | #define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8 | ||
| 151 | #define OMAP3430_PRM_VP1_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8) | ||
| 152 | #define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc | ||
| 153 | #define OMAP3430_PRM_VP1_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc) | ||
| 154 | #define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0 | ||
| 155 | #define OMAP3430_PRM_VP1_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0) | ||
| 156 | #define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4 | ||
| 157 | #define OMAP3430_PRM_VP1_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4) | ||
| 158 | #define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0 | ||
| 159 | #define OMAP3430_PRM_VP2_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0) | ||
| 160 | #define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4 | ||
| 161 | #define OMAP3430_PRM_VP2_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4) | ||
| 162 | #define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8 | ||
| 163 | #define OMAP3430_PRM_VP2_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8) | ||
| 164 | #define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc | ||
| 165 | #define OMAP3430_PRM_VP2_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc) | ||
| 166 | #define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0 | ||
| 167 | #define OMAP3430_PRM_VP2_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0) | ||
| 168 | #define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4 | ||
| 169 | #define OMAP3430_PRM_VP2_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4) | ||
| 170 | |||
| 171 | #define OMAP3_PRM_CLKSEL_OFFSET 0x0040 | ||
| 172 | #define OMAP3430_PRM_CLKSEL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040) | ||
| 173 | #define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070 | ||
| 174 | #define OMAP3430_PRM_CLKOUT_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070) | ||
| 175 | |||
| 176 | /* | ||
| 177 | * Module specific PRM register offsets from PRM_BASE + domain offset | ||
| 178 | * | ||
| 179 | * Use prm_{read,write}_mod_reg() with these registers. | ||
| 180 | * | ||
| 181 | * With a few exceptions, these are the register names beginning with | ||
| 182 | * {PM,RM}_* on both OMAP2/3 SoC families.. (The exceptions are the | ||
| 183 | * IRQSTATUS and IRQENABLE bits.) | ||
| 184 | */ | ||
| 185 | |||
| 186 | /* Register offsets appearing on both OMAP2 and OMAP3 */ | ||
| 187 | |||
| 188 | #define OMAP2_RM_RSTCTRL 0x0050 | ||
| 189 | #define OMAP2_RM_RSTTIME 0x0054 | ||
| 190 | #define OMAP2_RM_RSTST 0x0058 | ||
| 191 | #define OMAP2_PM_PWSTCTRL 0x00e0 | ||
| 192 | #define OMAP2_PM_PWSTST 0x00e4 | ||
| 193 | |||
| 194 | #define PM_WKEN 0x00a0 | ||
| 195 | #define PM_WKEN1 PM_WKEN | ||
| 196 | #define PM_WKST 0x00b0 | ||
| 197 | #define PM_WKST1 PM_WKST | ||
| 198 | #define PM_WKDEP 0x00c8 | ||
| 199 | #define PM_EVGENCTRL 0x00d4 | ||
| 200 | #define PM_EVGENONTIM 0x00d8 | ||
| 201 | #define PM_EVGENOFFTIM 0x00dc | ||
| 202 | |||
| 203 | /* OMAP2xxx specific register offsets */ | ||
| 204 | #define OMAP24XX_PM_WKEN2 0x00a4 | ||
| 205 | #define OMAP24XX_PM_WKST2 0x00b4 | ||
| 206 | |||
| 207 | #define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */ | ||
| 208 | #define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */ | ||
| 209 | #define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8 | ||
| 210 | #define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc | ||
| 211 | |||
| 212 | /* OMAP3 specific register offsets */ | ||
| 213 | #define OMAP3430ES2_PM_WKEN3 0x00f0 | ||
| 214 | #define OMAP3430ES2_PM_WKST3 0x00b8 | ||
| 215 | |||
| 216 | #define OMAP3430_PM_MPUGRPSEL 0x00a4 | ||
| 217 | #define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL | ||
| 218 | #define OMAP3430ES2_PM_MPUGRPSEL3 0x00f8 | ||
| 219 | |||
| 220 | #define OMAP3430_PM_IVAGRPSEL 0x00a8 | ||
| 221 | #define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL | ||
| 222 | #define OMAP3430ES2_PM_IVAGRPSEL3 0x00f4 | ||
| 223 | |||
| 224 | #define OMAP3430_PM_PREPWSTST 0x00e8 | ||
| 225 | |||
| 226 | #define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8 | ||
| 227 | #define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc | ||
| 228 | |||
| 229 | |||
| 230 | #ifndef __ASSEMBLER__ | ||
| 231 | |||
| 232 | /* Power/reset management domain register get/set */ | ||
| 233 | extern u32 omap2_prm_read_mod_reg(s16 module, u16 idx); | ||
| 234 | extern void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx); | ||
| 235 | extern u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); | ||
| 236 | extern u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx); | ||
| 237 | extern u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx); | ||
| 238 | extern u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask); | ||
| 239 | |||
| 240 | /* These omap2_ PRM functions apply to both OMAP2 and 3 */ | ||
| 241 | extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift); | ||
| 242 | extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift); | ||
| 243 | extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift); | ||
| 244 | |||
| 245 | #endif | ||
| 246 | |||
| 247 | /* | ||
| 248 | * Bits common to specific registers | ||
| 249 | * | ||
| 250 | * The 3430 register and bit names are generally used, | ||
| 251 | * since they tend to make more sense | ||
| 252 | */ | ||
| 253 | |||
| 254 | /* PM_EVGENONTIM_MPU */ | ||
| 255 | /* Named PM_EVEGENONTIM_MPU on the 24XX */ | ||
| 256 | #define OMAP_ONTIMEVAL_SHIFT 0 | ||
| 257 | #define OMAP_ONTIMEVAL_MASK (0xffffffff << 0) | ||
| 258 | |||
| 259 | /* PM_EVGENOFFTIM_MPU */ | ||
| 260 | /* Named PM_EVEGENOFFTIM_MPU on the 24XX */ | ||
| 261 | #define OMAP_OFFTIMEVAL_SHIFT 0 | ||
| 262 | #define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0) | ||
| 263 | |||
| 264 | /* PRM_CLKSETUP and PRCM_VOLTSETUP */ | ||
| 265 | /* Named PRCM_CLKSSETUP on the 24XX */ | ||
| 266 | #define OMAP_SETUP_TIME_SHIFT 0 | ||
| 267 | #define OMAP_SETUP_TIME_MASK (0xffff << 0) | ||
| 268 | |||
| 269 | /* PRM_CLKSRC_CTRL */ | ||
| 270 | /* Named PRCM_CLKSRC_CTRL on the 24XX */ | ||
| 271 | #define OMAP_SYSCLKDIV_SHIFT 6 | ||
| 272 | #define OMAP_SYSCLKDIV_MASK (0x3 << 6) | ||
| 273 | #define OMAP_AUTOEXTCLKMODE_SHIFT 3 | ||
| 274 | #define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3) | ||
| 275 | #define OMAP_SYSCLKSEL_SHIFT 0 | ||
| 276 | #define OMAP_SYSCLKSEL_MASK (0x3 << 0) | ||
| 277 | |||
| 278 | /* PM_EVGENCTRL_MPU */ | ||
| 279 | #define OMAP_OFFLOADMODE_SHIFT 3 | ||
| 280 | #define OMAP_OFFLOADMODE_MASK (0x3 << 3) | ||
| 281 | #define OMAP_ONLOADMODE_SHIFT 1 | ||
| 282 | #define OMAP_ONLOADMODE_MASK (0x3 << 1) | ||
| 283 | #define OMAP_ENABLE_MASK (1 << 0) | ||
| 284 | |||
| 285 | /* PRM_RSTTIME */ | ||
| 286 | /* Named RM_RSTTIME_WKUP on the 24xx */ | ||
| 287 | #define OMAP_RSTTIME2_SHIFT 8 | ||
| 288 | #define OMAP_RSTTIME2_MASK (0x1f << 8) | ||
| 289 | #define OMAP_RSTTIME1_SHIFT 0 | ||
| 290 | #define OMAP_RSTTIME1_MASK (0xff << 0) | ||
| 291 | |||
| 292 | /* PRM_RSTCTRL */ | ||
| 293 | /* Named RM_RSTCTRL_WKUP on the 24xx */ | ||
| 294 | /* 2420 calls RST_DPLL3 'RST_DPLL' */ | ||
| 295 | #define OMAP_RST_DPLL3_MASK (1 << 2) | ||
| 296 | #define OMAP_RST_GS_MASK (1 << 1) | ||
| 297 | |||
| 298 | |||
| 299 | /* | ||
| 300 | * Bits common to module-shared registers | ||
| 301 | * | ||
| 302 | * Not all registers of a particular type support all of these bits - | ||
| 303 | * check TRM if you are unsure | ||
| 304 | */ | ||
| 305 | |||
| 306 | /* | ||
| 307 | * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is | ||
| 308 | * called 'COREWKUP_RST' | ||
| 309 | * | ||
| 310 | * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS, | ||
| 311 | * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON | ||
| 312 | */ | ||
| 313 | #define OMAP_COREDOMAINWKUP_RST_MASK (1 << 3) | ||
| 314 | |||
| 315 | /* | ||
| 316 | * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP | ||
| 317 | * | ||
| 318 | * 2430: RM_RSTST_MDM | ||
| 319 | * | ||
| 320 | * 3430: RM_RSTST_CORE, RM_RSTST_EMU | ||
| 321 | */ | ||
| 322 | #define OMAP_DOMAINWKUP_RST_MASK (1 << 2) | ||
| 323 | |||
| 324 | /* | ||
| 325 | * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP | ||
| 326 | * On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'. | ||
| 327 | * | ||
| 328 | * 2430: RM_RSTST_MDM | ||
| 329 | * | ||
| 330 | * 3430: RM_RSTST_CORE, RM_RSTST_EMU | ||
| 331 | */ | ||
| 332 | #define OMAP_GLOBALWARM_RST_MASK (1 << 1) | ||
| 333 | #define OMAP_GLOBALCOLD_RST_MASK (1 << 0) | ||
| 334 | |||
| 335 | /* | ||
| 336 | * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP | ||
| 337 | * 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP" | ||
| 338 | * | ||
| 339 | * 2430: PM_WKDEP_MDM | ||
| 340 | * | ||
| 341 | * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM, | ||
| 342 | * PM_WKDEP_PER | ||
| 343 | */ | ||
| 344 | #define OMAP_EN_WKUP_SHIFT 4 | ||
| 345 | #define OMAP_EN_WKUP_MASK (1 << 4) | ||
| 346 | |||
| 347 | /* | ||
| 348 | * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, | ||
| 349 | * PM_PWSTCTRL_DSP | ||
| 350 | * | ||
| 351 | * 2430: PM_PWSTCTRL_MDM | ||
| 352 | * | ||
| 353 | * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, | ||
| 354 | * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER, | ||
| 355 | * PM_PWSTCTRL_NEON | ||
| 356 | */ | ||
| 357 | #define OMAP_LOGICRETSTATE_MASK (1 << 2) | ||
| 358 | |||
| 359 | |||
| 360 | /* | ||
| 361 | * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP | ||
| 362 | * submodule to exit hardreset | ||
| 363 | */ | ||
| 364 | #define MAX_MODULE_HARDRESET_WAIT 10000 | ||
| 365 | |||
| 366 | |||
| 367 | #endif | ||
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index a1ff918d9bed..a2a04bfa9628 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c | |||
| @@ -15,12 +15,13 @@ | |||
| 15 | #include <linux/delay.h> | 15 | #include <linux/delay.h> |
| 16 | #include <linux/errno.h> | 16 | #include <linux/errno.h> |
| 17 | #include <linux/err.h> | 17 | #include <linux/err.h> |
| 18 | #include <linux/io.h> | ||
| 18 | 19 | ||
| 19 | #include <plat/common.h> | 20 | #include <plat/common.h> |
| 20 | #include <plat/cpu.h> | 21 | #include <plat/cpu.h> |
| 21 | #include <plat/prcm.h> | 22 | #include <plat/prcm.h> |
| 22 | 23 | ||
| 23 | #include "prm.h" | 24 | #include "prm44xx.h" |
| 24 | #include "prm-regbits-44xx.h" | 25 | #include "prm-regbits-44xx.h" |
| 25 | 26 | ||
| 26 | /* | 27 | /* |
| @@ -29,6 +30,70 @@ | |||
| 29 | */ | 30 | */ |
| 30 | #define OMAP4_RST_CTRL_ST_OFFSET 4 | 31 | #define OMAP4_RST_CTRL_ST_OFFSET 4 |
| 31 | 32 | ||
| 33 | /* PRM low-level functions */ | ||
| 34 | |||
| 35 | /* Read a register in a CM/PRM instance in the PRM module */ | ||
| 36 | u32 omap4_prm_read_inst_reg(s16 inst, u16 reg) | ||
| 37 | { | ||
| 38 | return __raw_readl(OMAP44XX_PRM_REGADDR(inst, reg)); | ||
| 39 | } | ||
| 40 | |||
| 41 | /* Write into a register in a CM/PRM instance in the PRM module */ | ||
| 42 | void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg) | ||
| 43 | { | ||
| 44 | __raw_writel(val, OMAP44XX_PRM_REGADDR(inst, reg)); | ||
| 45 | } | ||
| 46 | |||
| 47 | /* Read-modify-write a register in a PRM module. Caller must lock */ | ||
| 48 | u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg) | ||
| 49 | { | ||
| 50 | u32 v; | ||
| 51 | |||
| 52 | v = omap4_prm_read_inst_reg(inst, reg); | ||
| 53 | v &= ~mask; | ||
| 54 | v |= bits; | ||
| 55 | omap4_prm_write_inst_reg(v, inst, reg); | ||
| 56 | |||
| 57 | return v; | ||
| 58 | } | ||
| 59 | |||
| 60 | /* Read a PRM register, AND it, and shift the result down to bit 0 */ | ||
| 61 | /* XXX deprecated */ | ||
| 62 | u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask) | ||
| 63 | { | ||
| 64 | u32 v; | ||
| 65 | |||
| 66 | v = __raw_readl(reg); | ||
| 67 | v &= mask; | ||
| 68 | v >>= __ffs(mask); | ||
| 69 | |||
| 70 | return v; | ||
| 71 | } | ||
| 72 | |||
| 73 | /* Read-modify-write a register in a PRM module. Caller must lock */ | ||
| 74 | /* XXX deprecated */ | ||
| 75 | u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg) | ||
| 76 | { | ||
| 77 | u32 v; | ||
| 78 | |||
| 79 | v = __raw_readl(reg); | ||
| 80 | v &= ~mask; | ||
| 81 | v |= bits; | ||
| 82 | __raw_writel(v, reg); | ||
| 83 | |||
| 84 | return v; | ||
| 85 | } | ||
| 86 | |||
| 87 | u32 omap4_prm_set_inst_reg_bits(u32 bits, s16 inst, s16 reg) | ||
| 88 | { | ||
| 89 | return omap4_prm_rmw_inst_reg_bits(bits, bits, inst, reg); | ||
| 90 | } | ||
| 91 | |||
| 92 | u32 omap4_prm_clear_inst_reg_bits(u32 bits, s16 inst, s16 reg) | ||
| 93 | { | ||
| 94 | return omap4_prm_rmw_inst_reg_bits(bits, 0x0, inst, reg); | ||
| 95 | } | ||
| 96 | |||
| 32 | /** | 97 | /** |
| 33 | * omap4_prm_is_hardreset_asserted - read the HW reset line state of | 98 | * omap4_prm_is_hardreset_asserted - read the HW reset line state of |
| 34 | * submodules contained in the hwmod module | 99 | * submodules contained in the hwmod module |
| @@ -114,3 +179,17 @@ int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift) | |||
| 114 | return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; | 179 | return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; |
| 115 | } | 180 | } |
| 116 | 181 | ||
| 182 | void omap4_prm_global_warm_sw_reset(void) | ||
| 183 | { | ||
| 184 | u32 v; | ||
| 185 | |||
| 186 | v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, | ||
| 187 | OMAP4_RM_RSTCTRL); | ||
| 188 | v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK; | ||
| 189 | omap4_prm_write_inst_reg(v, OMAP4430_PRM_DEVICE_INST, | ||
| 190 | OMAP4_RM_RSTCTRL); | ||
| 191 | |||
| 192 | /* OCP barrier */ | ||
| 193 | v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, | ||
| 194 | OMAP4_RM_RSTCTRL); | ||
| 195 | } | ||
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h index 59839dbabd84..67a0d3feb3f6 100644 --- a/arch/arm/mach-omap2/prm44xx.h +++ b/arch/arm/mach-omap2/prm44xx.h | |||
| @@ -17,736 +17,762 @@ | |||
| 17 | * This program is free software; you can redistribute it and/or modify | 17 | * This program is free software; you can redistribute it and/or modify |
| 18 | * it under the terms of the GNU General Public License version 2 as | 18 | * it under the terms of the GNU General Public License version 2 as |
| 19 | * published by the Free Software Foundation. | 19 | * published by the Free Software Foundation. |
| 20 | * | ||
| 21 | * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX", | ||
| 22 | * or "OMAP4430". | ||
| 20 | */ | 23 | */ |
| 21 | 24 | ||
| 22 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H | 25 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H |
| 23 | #define __ARCH_ARM_MACH_OMAP2_PRM44XX_H | 26 | #define __ARCH_ARM_MACH_OMAP2_PRM44XX_H |
| 24 | 27 | ||
| 28 | #include "prcm-common.h" | ||
| 29 | #include "prm.h" | ||
| 30 | |||
| 31 | #define OMAP4430_PRM_BASE 0x4a306000 | ||
| 32 | |||
| 33 | #define OMAP44XX_PRM_REGADDR(inst, reg) \ | ||
| 34 | OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg)) | ||
| 35 | |||
| 36 | |||
| 37 | /* PRM instances */ | ||
| 38 | #define OMAP4430_PRM_OCP_SOCKET_INST 0x0000 | ||
| 39 | #define OMAP4430_PRM_CKGEN_INST 0x0100 | ||
| 40 | #define OMAP4430_PRM_MPU_INST 0x0300 | ||
| 41 | #define OMAP4430_PRM_TESLA_INST 0x0400 | ||
| 42 | #define OMAP4430_PRM_ABE_INST 0x0500 | ||
| 43 | #define OMAP4430_PRM_ALWAYS_ON_INST 0x0600 | ||
| 44 | #define OMAP4430_PRM_CORE_INST 0x0700 | ||
| 45 | #define OMAP4430_PRM_IVAHD_INST 0x0f00 | ||
| 46 | #define OMAP4430_PRM_CAM_INST 0x1000 | ||
| 47 | #define OMAP4430_PRM_DSS_INST 0x1100 | ||
| 48 | #define OMAP4430_PRM_GFX_INST 0x1200 | ||
| 49 | #define OMAP4430_PRM_L3INIT_INST 0x1300 | ||
| 50 | #define OMAP4430_PRM_L4PER_INST 0x1400 | ||
| 51 | #define OMAP4430_PRM_CEFUSE_INST 0x1600 | ||
| 52 | #define OMAP4430_PRM_WKUP_INST 0x1700 | ||
| 53 | #define OMAP4430_PRM_WKUP_CM_INST 0x1800 | ||
| 54 | #define OMAP4430_PRM_EMU_INST 0x1900 | ||
| 55 | #define OMAP4430_PRM_EMU_CM_INST 0x1a00 | ||
| 56 | #define OMAP4430_PRM_DEVICE_INST 0x1b00 | ||
| 57 | #define OMAP4430_PRM_INSTR_INST 0x1f00 | ||
| 58 | |||
| 59 | /* PRM clockdomain register offsets (from instance start) */ | ||
| 60 | #define OMAP4430_PRM_MPU_MPU_CDOFFS 0x0000 | ||
| 61 | #define OMAP4430_PRM_TESLA_TESLA_CDOFFS 0x0000 | ||
| 62 | #define OMAP4430_PRM_ABE_ABE_CDOFFS 0x0000 | ||
| 63 | #define OMAP4430_PRM_CORE_CORE_CDOFFS 0x0000 | ||
| 64 | #define OMAP4430_PRM_IVAHD_IVAHD_CDOFFS 0x0000 | ||
| 65 | #define OMAP4430_PRM_CAM_CAM_CDOFFS 0x0000 | ||
| 66 | #define OMAP4430_PRM_DSS_DSS_CDOFFS 0x0000 | ||
| 67 | #define OMAP4430_PRM_GFX_GFX_CDOFFS 0x0000 | ||
| 68 | #define OMAP4430_PRM_L3INIT_L3INIT_CDOFFS 0x0000 | ||
| 69 | #define OMAP4430_PRM_L4PER_L4PER_CDOFFS 0x0000 | ||
| 70 | #define OMAP4430_PRM_CEFUSE_CEFUSE_CDOFFS 0x0000 | ||
| 71 | #define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS 0x0000 | ||
| 72 | #define OMAP4430_PRM_EMU_EMU_CDOFFS 0x0000 | ||
| 73 | #define OMAP4430_PRM_EMU_CM_EMU_CDOFFS 0x0000 | ||
| 74 | |||
| 75 | /* OMAP4 specific register offsets */ | ||
| 76 | #define OMAP4_RM_RSTCTRL 0x0000 | ||
| 77 | #define OMAP4_RM_RSTTIME 0x0004 | ||
| 78 | #define OMAP4_RM_RSTST 0x0008 | ||
| 79 | #define OMAP4_PM_PWSTCTRL 0x0000 | ||
| 80 | #define OMAP4_PM_PWSTST 0x0004 | ||
| 81 | |||
| 25 | 82 | ||
| 26 | /* PRM */ | 83 | /* PRM */ |
| 27 | 84 | ||
| 28 | /* PRM.OCP_SOCKET_PRM register offsets */ | 85 | /* PRM.OCP_SOCKET_PRM register offsets */ |
| 29 | #define OMAP4_REVISION_PRM_OFFSET 0x0000 | 86 | #define OMAP4_REVISION_PRM_OFFSET 0x0000 |
| 30 | #define OMAP4430_REVISION_PRM OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0000) | 87 | #define OMAP4430_REVISION_PRM OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0000) |
| 31 | #define OMAP4_PRM_IRQSTATUS_MPU_OFFSET 0x0010 | 88 | #define OMAP4_PRM_IRQSTATUS_MPU_OFFSET 0x0010 |
| 32 | #define OMAP4430_PRM_IRQSTATUS_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0010) | 89 | #define OMAP4430_PRM_IRQSTATUS_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0010) |
| 33 | #define OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014 | 90 | #define OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014 |
| 34 | #define OMAP4430_PRM_IRQSTATUS_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0014) | 91 | #define OMAP4430_PRM_IRQSTATUS_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0014) |
| 35 | #define OMAP4_PRM_IRQENABLE_MPU_OFFSET 0x0018 | 92 | #define OMAP4_PRM_IRQENABLE_MPU_OFFSET 0x0018 |
| 36 | #define OMAP4430_PRM_IRQENABLE_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0018) | 93 | #define OMAP4430_PRM_IRQENABLE_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0018) |
| 37 | #define OMAP4_PRM_IRQENABLE_MPU_2_OFFSET 0x001c | 94 | #define OMAP4_PRM_IRQENABLE_MPU_2_OFFSET 0x001c |
| 38 | #define OMAP4430_PRM_IRQENABLE_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x001c) | 95 | #define OMAP4430_PRM_IRQENABLE_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x001c) |
| 39 | #define OMAP4_PRM_IRQSTATUS_DUCATI_OFFSET 0x0020 | 96 | #define OMAP4_PRM_IRQSTATUS_DUCATI_OFFSET 0x0020 |
| 40 | #define OMAP4430_PRM_IRQSTATUS_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0020) | 97 | #define OMAP4430_PRM_IRQSTATUS_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0020) |
| 41 | #define OMAP4_PRM_IRQENABLE_DUCATI_OFFSET 0x0028 | 98 | #define OMAP4_PRM_IRQENABLE_DUCATI_OFFSET 0x0028 |
| 42 | #define OMAP4430_PRM_IRQENABLE_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0028) | 99 | #define OMAP4430_PRM_IRQENABLE_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0028) |
| 43 | #define OMAP4_PRM_IRQSTATUS_TESLA_OFFSET 0x0030 | 100 | #define OMAP4_PRM_IRQSTATUS_TESLA_OFFSET 0x0030 |
| 44 | #define OMAP4430_PRM_IRQSTATUS_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0030) | 101 | #define OMAP4430_PRM_IRQSTATUS_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0030) |
| 45 | #define OMAP4_PRM_IRQENABLE_TESLA_OFFSET 0x0038 | 102 | #define OMAP4_PRM_IRQENABLE_TESLA_OFFSET 0x0038 |
| 46 | #define OMAP4430_PRM_IRQENABLE_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0038) | 103 | #define OMAP4430_PRM_IRQENABLE_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0038) |
| 47 | #define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 | 104 | #define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 |
| 48 | #define OMAP4430_CM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040) | 105 | #define OMAP4430_CM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0040) |
| 49 | 106 | ||
| 50 | /* PRM.CKGEN_PRM register offsets */ | 107 | /* PRM.CKGEN_PRM register offsets */ |
| 51 | #define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET 0x0000 | 108 | #define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET 0x0000 |
| 52 | #define OMAP4430_CM_ABE_DSS_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0000) | 109 | #define OMAP4430_CM_ABE_DSS_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0000) |
| 53 | #define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET 0x0008 | 110 | #define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET 0x0008 |
| 54 | #define OMAP4430_CM_L4_WKUP_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0008) | 111 | #define OMAP4430_CM_L4_WKUP_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0008) |
| 55 | #define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET 0x000c | 112 | #define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET 0x000c |
| 56 | #define OMAP4430_CM_ABE_PLL_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x000c) | 113 | #define OMAP4430_CM_ABE_PLL_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x000c) |
| 57 | #define OMAP4_CM_SYS_CLKSEL_OFFSET 0x0010 | 114 | #define OMAP4_CM_SYS_CLKSEL_OFFSET 0x0010 |
| 58 | #define OMAP4430_CM_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0010) | 115 | #define OMAP4430_CM_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0010) |
| 59 | 116 | ||
| 60 | /* PRM.MPU_PRM register offsets */ | 117 | /* PRM.MPU_PRM register offsets */ |
| 61 | #define OMAP4_PM_MPU_PWRSTCTRL_OFFSET 0x0000 | 118 | #define OMAP4_PM_MPU_PWRSTCTRL_OFFSET 0x0000 |
| 62 | #define OMAP4430_PM_MPU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0000) | 119 | #define OMAP4430_PM_MPU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0000) |
| 63 | #define OMAP4_PM_MPU_PWRSTST_OFFSET 0x0004 | 120 | #define OMAP4_PM_MPU_PWRSTST_OFFSET 0x0004 |
| 64 | #define OMAP4430_PM_MPU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0004) | 121 | #define OMAP4430_PM_MPU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0004) |
| 65 | #define OMAP4_RM_MPU_RSTST_OFFSET 0x0014 | 122 | #define OMAP4_RM_MPU_RSTST_OFFSET 0x0014 |
| 66 | #define OMAP4430_RM_MPU_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0014) | 123 | #define OMAP4430_RM_MPU_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0014) |
| 67 | #define OMAP4_RM_MPU_MPU_CONTEXT_OFFSET 0x0024 | 124 | #define OMAP4_RM_MPU_MPU_CONTEXT_OFFSET 0x0024 |
| 68 | #define OMAP4430_RM_MPU_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0024) | 125 | #define OMAP4430_RM_MPU_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0024) |
| 69 | 126 | ||
| 70 | /* PRM.TESLA_PRM register offsets */ | 127 | /* PRM.TESLA_PRM register offsets */ |
| 71 | #define OMAP4_PM_TESLA_PWRSTCTRL_OFFSET 0x0000 | 128 | #define OMAP4_PM_TESLA_PWRSTCTRL_OFFSET 0x0000 |
| 72 | #define OMAP4430_PM_TESLA_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0000) | 129 | #define OMAP4430_PM_TESLA_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0000) |
| 73 | #define OMAP4_PM_TESLA_PWRSTST_OFFSET 0x0004 | 130 | #define OMAP4_PM_TESLA_PWRSTST_OFFSET 0x0004 |
| 74 | #define OMAP4430_PM_TESLA_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0004) | 131 | #define OMAP4430_PM_TESLA_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0004) |
| 75 | #define OMAP4_RM_TESLA_RSTCTRL_OFFSET 0x0010 | 132 | #define OMAP4_RM_TESLA_RSTCTRL_OFFSET 0x0010 |
| 76 | #define OMAP4430_RM_TESLA_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0010) | 133 | #define OMAP4430_RM_TESLA_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0010) |
| 77 | #define OMAP4_RM_TESLA_RSTST_OFFSET 0x0014 | 134 | #define OMAP4_RM_TESLA_RSTST_OFFSET 0x0014 |
| 78 | #define OMAP4430_RM_TESLA_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0014) | 135 | #define OMAP4430_RM_TESLA_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0014) |
| 79 | #define OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET 0x0024 | 136 | #define OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET 0x0024 |
| 80 | #define OMAP4430_RM_TESLA_TESLA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0024) | 137 | #define OMAP4430_RM_TESLA_TESLA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0024) |
| 81 | 138 | ||
| 82 | /* PRM.ABE_PRM register offsets */ | 139 | /* PRM.ABE_PRM register offsets */ |
| 83 | #define OMAP4_PM_ABE_PWRSTCTRL_OFFSET 0x0000 | 140 | #define OMAP4_PM_ABE_PWRSTCTRL_OFFSET 0x0000 |
| 84 | #define OMAP4430_PM_ABE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0000) | 141 | #define OMAP4430_PM_ABE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0000) |
| 85 | #define OMAP4_PM_ABE_PWRSTST_OFFSET 0x0004 | 142 | #define OMAP4_PM_ABE_PWRSTST_OFFSET 0x0004 |
| 86 | #define OMAP4430_PM_ABE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0004) | 143 | #define OMAP4430_PM_ABE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0004) |
| 87 | #define OMAP4_RM_ABE_AESS_CONTEXT_OFFSET 0x002c | 144 | #define OMAP4_RM_ABE_AESS_CONTEXT_OFFSET 0x002c |
| 88 | #define OMAP4430_RM_ABE_AESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x002c) | 145 | #define OMAP4430_RM_ABE_AESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x002c) |
| 89 | #define OMAP4_PM_ABE_PDM_WKDEP_OFFSET 0x0030 | 146 | #define OMAP4_PM_ABE_PDM_WKDEP_OFFSET 0x0030 |
| 90 | #define OMAP4430_PM_ABE_PDM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0030) | 147 | #define OMAP4430_PM_ABE_PDM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0030) |
| 91 | #define OMAP4_RM_ABE_PDM_CONTEXT_OFFSET 0x0034 | 148 | #define OMAP4_RM_ABE_PDM_CONTEXT_OFFSET 0x0034 |
| 92 | #define OMAP4430_RM_ABE_PDM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0034) | 149 | #define OMAP4430_RM_ABE_PDM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0034) |
| 93 | #define OMAP4_PM_ABE_DMIC_WKDEP_OFFSET 0x0038 | 150 | #define OMAP4_PM_ABE_DMIC_WKDEP_OFFSET 0x0038 |
| 94 | #define OMAP4430_PM_ABE_DMIC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0038) | 151 | #define OMAP4430_PM_ABE_DMIC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0038) |
| 95 | #define OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET 0x003c | 152 | #define OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET 0x003c |
| 96 | #define OMAP4430_RM_ABE_DMIC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x003c) | 153 | #define OMAP4430_RM_ABE_DMIC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x003c) |
| 97 | #define OMAP4_PM_ABE_MCASP_WKDEP_OFFSET 0x0040 | 154 | #define OMAP4_PM_ABE_MCASP_WKDEP_OFFSET 0x0040 |
| 98 | #define OMAP4430_PM_ABE_MCASP_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0040) | 155 | #define OMAP4430_PM_ABE_MCASP_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0040) |
| 99 | #define OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET 0x0044 | 156 | #define OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET 0x0044 |
| 100 | #define OMAP4430_RM_ABE_MCASP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0044) | 157 | #define OMAP4430_RM_ABE_MCASP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0044) |
| 101 | #define OMAP4_PM_ABE_MCBSP1_WKDEP_OFFSET 0x0048 | 158 | #define OMAP4_PM_ABE_MCBSP1_WKDEP_OFFSET 0x0048 |
| 102 | #define OMAP4430_PM_ABE_MCBSP1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0048) | 159 | #define OMAP4430_PM_ABE_MCBSP1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0048) |
| 103 | #define OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET 0x004c | 160 | #define OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET 0x004c |
| 104 | #define OMAP4430_RM_ABE_MCBSP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x004c) | 161 | #define OMAP4430_RM_ABE_MCBSP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x004c) |
| 105 | #define OMAP4_PM_ABE_MCBSP2_WKDEP_OFFSET 0x0050 | 162 | #define OMAP4_PM_ABE_MCBSP2_WKDEP_OFFSET 0x0050 |
| 106 | #define OMAP4430_PM_ABE_MCBSP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0050) | 163 | #define OMAP4430_PM_ABE_MCBSP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0050) |
| 107 | #define OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET 0x0054 | 164 | #define OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET 0x0054 |
| 108 | #define OMAP4430_RM_ABE_MCBSP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0054) | 165 | #define OMAP4430_RM_ABE_MCBSP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0054) |
| 109 | #define OMAP4_PM_ABE_MCBSP3_WKDEP_OFFSET 0x0058 | 166 | #define OMAP4_PM_ABE_MCBSP3_WKDEP_OFFSET 0x0058 |
| 110 | #define OMAP4430_PM_ABE_MCBSP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0058) | 167 | #define OMAP4430_PM_ABE_MCBSP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0058) |
| 111 | #define OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET 0x005c | 168 | #define OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET 0x005c |
| 112 | #define OMAP4430_RM_ABE_MCBSP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x005c) | 169 | #define OMAP4430_RM_ABE_MCBSP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x005c) |
| 113 | #define OMAP4_PM_ABE_SLIMBUS_WKDEP_OFFSET 0x0060 | 170 | #define OMAP4_PM_ABE_SLIMBUS_WKDEP_OFFSET 0x0060 |
| 114 | #define OMAP4430_PM_ABE_SLIMBUS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0060) | 171 | #define OMAP4430_PM_ABE_SLIMBUS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0060) |
| 115 | #define OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET 0x0064 | 172 | #define OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET 0x0064 |
| 116 | #define OMAP4430_RM_ABE_SLIMBUS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0064) | 173 | #define OMAP4430_RM_ABE_SLIMBUS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0064) |
| 117 | #define OMAP4_PM_ABE_TIMER5_WKDEP_OFFSET 0x0068 | 174 | #define OMAP4_PM_ABE_TIMER5_WKDEP_OFFSET 0x0068 |
| 118 | #define OMAP4430_PM_ABE_TIMER5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0068) | 175 | #define OMAP4430_PM_ABE_TIMER5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0068) |
| 119 | #define OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET 0x006c | 176 | #define OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET 0x006c |
| 120 | #define OMAP4430_RM_ABE_TIMER5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x006c) | 177 | #define OMAP4430_RM_ABE_TIMER5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x006c) |
| 121 | #define OMAP4_PM_ABE_TIMER6_WKDEP_OFFSET 0x0070 | 178 | #define OMAP4_PM_ABE_TIMER6_WKDEP_OFFSET 0x0070 |
| 122 | #define OMAP4430_PM_ABE_TIMER6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0070) | 179 | #define OMAP4430_PM_ABE_TIMER6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0070) |
| 123 | #define OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET 0x0074 | 180 | #define OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET 0x0074 |
| 124 | #define OMAP4430_RM_ABE_TIMER6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0074) | 181 | #define OMAP4430_RM_ABE_TIMER6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0074) |
| 125 | #define OMAP4_PM_ABE_TIMER7_WKDEP_OFFSET 0x0078 | 182 | #define OMAP4_PM_ABE_TIMER7_WKDEP_OFFSET 0x0078 |
| 126 | #define OMAP4430_PM_ABE_TIMER7_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0078) | 183 | #define OMAP4430_PM_ABE_TIMER7_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0078) |
| 127 | #define OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET 0x007c | 184 | #define OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET 0x007c |
| 128 | #define OMAP4430_RM_ABE_TIMER7_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x007c) | 185 | #define OMAP4430_RM_ABE_TIMER7_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x007c) |
| 129 | #define OMAP4_PM_ABE_TIMER8_WKDEP_OFFSET 0x0080 | 186 | #define OMAP4_PM_ABE_TIMER8_WKDEP_OFFSET 0x0080 |
| 130 | #define OMAP4430_PM_ABE_TIMER8_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0080) | 187 | #define OMAP4430_PM_ABE_TIMER8_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0080) |
| 131 | #define OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET 0x0084 | 188 | #define OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET 0x0084 |
| 132 | #define OMAP4430_RM_ABE_TIMER8_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0084) | 189 | #define OMAP4430_RM_ABE_TIMER8_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0084) |
| 133 | #define OMAP4_PM_ABE_WDT3_WKDEP_OFFSET 0x0088 | 190 | #define OMAP4_PM_ABE_WDT3_WKDEP_OFFSET 0x0088 |
| 134 | #define OMAP4430_PM_ABE_WDT3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0088) | 191 | #define OMAP4430_PM_ABE_WDT3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0088) |
| 135 | #define OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET 0x008c | 192 | #define OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET 0x008c |
| 136 | #define OMAP4430_RM_ABE_WDT3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x008c) | 193 | #define OMAP4430_RM_ABE_WDT3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x008c) |
| 137 | 194 | ||
| 138 | /* PRM.ALWAYS_ON_PRM register offsets */ | 195 | /* PRM.ALWAYS_ON_PRM register offsets */ |
| 139 | #define OMAP4_RM_ALWON_MDMINTC_CONTEXT_OFFSET 0x0024 | 196 | #define OMAP4_RM_ALWON_MDMINTC_CONTEXT_OFFSET 0x0024 |
| 140 | #define OMAP4430_RM_ALWON_MDMINTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0024) | 197 | #define OMAP4430_RM_ALWON_MDMINTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0024) |
| 141 | #define OMAP4_PM_ALWON_SR_MPU_WKDEP_OFFSET 0x0028 | 198 | #define OMAP4_PM_ALWON_SR_MPU_WKDEP_OFFSET 0x0028 |
| 142 | #define OMAP4430_PM_ALWON_SR_MPU_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0028) | 199 | #define OMAP4430_PM_ALWON_SR_MPU_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0028) |
| 143 | #define OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET 0x002c | 200 | #define OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET 0x002c |
| 144 | #define OMAP4430_RM_ALWON_SR_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x002c) | 201 | #define OMAP4430_RM_ALWON_SR_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x002c) |
| 145 | #define OMAP4_PM_ALWON_SR_IVA_WKDEP_OFFSET 0x0030 | 202 | #define OMAP4_PM_ALWON_SR_IVA_WKDEP_OFFSET 0x0030 |
| 146 | #define OMAP4430_PM_ALWON_SR_IVA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0030) | 203 | #define OMAP4430_PM_ALWON_SR_IVA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0030) |
| 147 | #define OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET 0x0034 | 204 | #define OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET 0x0034 |
| 148 | #define OMAP4430_RM_ALWON_SR_IVA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0034) | 205 | #define OMAP4430_RM_ALWON_SR_IVA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0034) |
| 149 | #define OMAP4_PM_ALWON_SR_CORE_WKDEP_OFFSET 0x0038 | 206 | #define OMAP4_PM_ALWON_SR_CORE_WKDEP_OFFSET 0x0038 |
| 150 | #define OMAP4430_PM_ALWON_SR_CORE_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0038) | 207 | #define OMAP4430_PM_ALWON_SR_CORE_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0038) |
| 151 | #define OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET 0x003c | 208 | #define OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET 0x003c |
| 152 | #define OMAP4430_RM_ALWON_SR_CORE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x003c) | 209 | #define OMAP4430_RM_ALWON_SR_CORE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x003c) |
| 153 | 210 | ||
| 154 | /* PRM.CORE_PRM register offsets */ | 211 | /* PRM.CORE_PRM register offsets */ |
| 155 | #define OMAP4_PM_CORE_PWRSTCTRL_OFFSET 0x0000 | 212 | #define OMAP4_PM_CORE_PWRSTCTRL_OFFSET 0x0000 |
| 156 | #define OMAP4430_PM_CORE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0000) | 213 | #define OMAP4430_PM_CORE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0000) |
| 157 | #define OMAP4_PM_CORE_PWRSTST_OFFSET 0x0004 | 214 | #define OMAP4_PM_CORE_PWRSTST_OFFSET 0x0004 |
| 158 | #define OMAP4430_PM_CORE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0004) | 215 | #define OMAP4430_PM_CORE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0004) |
| 159 | #define OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET 0x0024 | 216 | #define OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET 0x0024 |
| 160 | #define OMAP4430_RM_L3_1_L3_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0024) | 217 | #define OMAP4430_RM_L3_1_L3_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0024) |
| 161 | #define OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET 0x0124 | 218 | #define OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET 0x0124 |
| 162 | #define OMAP4430_RM_L3_2_L3_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0124) | 219 | #define OMAP4430_RM_L3_2_L3_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0124) |
| 163 | #define OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET 0x012c | 220 | #define OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET 0x012c |
| 164 | #define OMAP4430_RM_L3_2_GPMC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x012c) | 221 | #define OMAP4430_RM_L3_2_GPMC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x012c) |
| 165 | #define OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET 0x0134 | 222 | #define OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET 0x0134 |
| 166 | #define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0134) | 223 | #define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0134) |
| 167 | #define OMAP4_RM_DUCATI_RSTCTRL_OFFSET 0x0210 | 224 | #define OMAP4_RM_DUCATI_RSTCTRL_OFFSET 0x0210 |
| 168 | #define OMAP4430_RM_DUCATI_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0210) | 225 | #define OMAP4430_RM_DUCATI_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0210) |
| 169 | #define OMAP4_RM_DUCATI_RSTST_OFFSET 0x0214 | 226 | #define OMAP4_RM_DUCATI_RSTST_OFFSET 0x0214 |
| 170 | #define OMAP4430_RM_DUCATI_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0214) | 227 | #define OMAP4430_RM_DUCATI_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0214) |
| 171 | #define OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET 0x0224 | 228 | #define OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET 0x0224 |
| 172 | #define OMAP4430_RM_DUCATI_DUCATI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0224) | 229 | #define OMAP4430_RM_DUCATI_DUCATI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0224) |
| 173 | #define OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET 0x0324 | 230 | #define OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET 0x0324 |
| 174 | #define OMAP4430_RM_SDMA_SDMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0324) | 231 | #define OMAP4430_RM_SDMA_SDMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0324) |
| 175 | #define OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET 0x0424 | 232 | #define OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET 0x0424 |
| 176 | #define OMAP4430_RM_MEMIF_DMM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0424) | 233 | #define OMAP4430_RM_MEMIF_DMM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0424) |
| 177 | #define OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET 0x042c | 234 | #define OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET 0x042c |
| 178 | #define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x042c) | 235 | #define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x042c) |
| 179 | #define OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET 0x0434 | 236 | #define OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET 0x0434 |
| 180 | #define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0434) | 237 | #define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0434) |
| 181 | #define OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET 0x043c | 238 | #define OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET 0x043c |
| 182 | #define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x043c) | 239 | #define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x043c) |
| 183 | #define OMAP4_RM_MEMIF_DLL_CONTEXT_OFFSET 0x0444 | 240 | #define OMAP4_RM_MEMIF_DLL_CONTEXT_OFFSET 0x0444 |
| 184 | #define OMAP4430_RM_MEMIF_DLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0444) | 241 | #define OMAP4430_RM_MEMIF_DLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0444) |
| 185 | #define OMAP4_RM_MEMIF_EMIF_H1_CONTEXT_OFFSET 0x0454 | 242 | #define OMAP4_RM_MEMIF_EMIF_H1_CONTEXT_OFFSET 0x0454 |
| 186 | #define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0454) | 243 | #define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0454) |
| 187 | #define OMAP4_RM_MEMIF_EMIF_H2_CONTEXT_OFFSET 0x045c | 244 | #define OMAP4_RM_MEMIF_EMIF_H2_CONTEXT_OFFSET 0x045c |
| 188 | #define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x045c) | 245 | #define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x045c) |
| 189 | #define OMAP4_RM_MEMIF_DLL_H_CONTEXT_OFFSET 0x0464 | 246 | #define OMAP4_RM_MEMIF_DLL_H_CONTEXT_OFFSET 0x0464 |
| 190 | #define OMAP4430_RM_MEMIF_DLL_H_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0464) | 247 | #define OMAP4430_RM_MEMIF_DLL_H_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0464) |
| 191 | #define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET 0x0524 | 248 | #define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET 0x0524 |
| 192 | #define OMAP4430_RM_D2D_SAD2D_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0524) | 249 | #define OMAP4430_RM_D2D_SAD2D_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0524) |
| 193 | #define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET 0x052c | 250 | #define OMAP4_RM_D2D_INSTEM_ICR_CONTEXT_OFFSET 0x052c |
| 194 | #define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x052c) | 251 | #define OMAP4430_RM_D2D_INSTEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c) |
| 195 | #define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET 0x0534 | 252 | #define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET 0x0534 |
| 196 | #define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0534) | 253 | #define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0534) |
| 197 | #define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624 | 254 | #define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624 |
| 198 | #define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0624) | 255 | #define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0624) |
| 199 | #define OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET 0x062c | 256 | #define OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET 0x062c |
| 200 | #define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x062c) | 257 | #define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x062c) |
| 201 | #define OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET 0x0634 | 258 | #define OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET 0x0634 |
| 202 | #define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0634) | 259 | #define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0634) |
| 203 | #define OMAP4_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c | 260 | #define OMAP4_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c |
| 204 | #define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x063c) | 261 | #define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x063c) |
| 205 | #define OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET 0x0724 | 262 | #define OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET 0x0724 |
| 206 | #define OMAP4430_RM_L3INSTR_L3_3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0724) | 263 | #define OMAP4430_RM_L3INSTR_L3_3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0724) |
| 207 | #define OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c | 264 | #define OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c |
| 208 | #define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x072c) | 265 | #define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x072c) |
| 209 | #define OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET 0x0744 | 266 | #define OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET 0x0744 |
| 210 | #define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0744) | 267 | #define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0744) |
| 211 | 268 | ||
| 212 | /* PRM.IVAHD_PRM register offsets */ | 269 | /* PRM.IVAHD_PRM register offsets */ |
| 213 | #define OMAP4_PM_IVAHD_PWRSTCTRL_OFFSET 0x0000 | 270 | #define OMAP4_PM_IVAHD_PWRSTCTRL_OFFSET 0x0000 |
| 214 | #define OMAP4430_PM_IVAHD_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0000) | 271 | #define OMAP4430_PM_IVAHD_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0000) |
| 215 | #define OMAP4_PM_IVAHD_PWRSTST_OFFSET 0x0004 | 272 | #define OMAP4_PM_IVAHD_PWRSTST_OFFSET 0x0004 |
| 216 | #define OMAP4430_PM_IVAHD_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0004) | 273 | #define OMAP4430_PM_IVAHD_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0004) |
| 217 | #define OMAP4_RM_IVAHD_RSTCTRL_OFFSET 0x0010 | 274 | #define OMAP4_RM_IVAHD_RSTCTRL_OFFSET 0x0010 |
| 218 | #define OMAP4430_RM_IVAHD_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0010) | 275 | #define OMAP4430_RM_IVAHD_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0010) |
| 219 | #define OMAP4_RM_IVAHD_RSTST_OFFSET 0x0014 | 276 | #define OMAP4_RM_IVAHD_RSTST_OFFSET 0x0014 |
| 220 | #define OMAP4430_RM_IVAHD_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0014) | 277 | #define OMAP4430_RM_IVAHD_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0014) |
| 221 | #define OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET 0x0024 | 278 | #define OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET 0x0024 |
| 222 | #define OMAP4430_RM_IVAHD_IVAHD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0024) | 279 | #define OMAP4430_RM_IVAHD_IVAHD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0024) |
| 223 | #define OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET 0x002c | 280 | #define OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET 0x002c |
| 224 | #define OMAP4430_RM_IVAHD_SL2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x002c) | 281 | #define OMAP4430_RM_IVAHD_SL2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x002c) |
| 225 | 282 | ||
| 226 | /* PRM.CAM_PRM register offsets */ | 283 | /* PRM.CAM_PRM register offsets */ |
| 227 | #define OMAP4_PM_CAM_PWRSTCTRL_OFFSET 0x0000 | 284 | #define OMAP4_PM_CAM_PWRSTCTRL_OFFSET 0x0000 |
| 228 | #define OMAP4430_PM_CAM_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0000) | 285 | #define OMAP4430_PM_CAM_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0000) |
| 229 | #define OMAP4_PM_CAM_PWRSTST_OFFSET 0x0004 | 286 | #define OMAP4_PM_CAM_PWRSTST_OFFSET 0x0004 |
| 230 | #define OMAP4430_PM_CAM_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0004) | 287 | #define OMAP4430_PM_CAM_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0004) |
| 231 | #define OMAP4_RM_CAM_ISS_CONTEXT_OFFSET 0x0024 | 288 | #define OMAP4_RM_CAM_ISS_CONTEXT_OFFSET 0x0024 |
| 232 | #define OMAP4430_RM_CAM_ISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0024) | 289 | #define OMAP4430_RM_CAM_ISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0024) |
| 233 | #define OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET 0x002c | 290 | #define OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET 0x002c |
| 234 | #define OMAP4430_RM_CAM_FDIF_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x002c) | 291 | #define OMAP4430_RM_CAM_FDIF_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x002c) |
| 235 | 292 | ||
| 236 | /* PRM.DSS_PRM register offsets */ | 293 | /* PRM.DSS_PRM register offsets */ |
| 237 | #define OMAP4_PM_DSS_PWRSTCTRL_OFFSET 0x0000 | 294 | #define OMAP4_PM_DSS_PWRSTCTRL_OFFSET 0x0000 |
| 238 | #define OMAP4430_PM_DSS_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0000) | 295 | #define OMAP4430_PM_DSS_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0000) |
| 239 | #define OMAP4_PM_DSS_PWRSTST_OFFSET 0x0004 | 296 | #define OMAP4_PM_DSS_PWRSTST_OFFSET 0x0004 |
| 240 | #define OMAP4430_PM_DSS_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0004) | 297 | #define OMAP4430_PM_DSS_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0004) |
| 241 | #define OMAP4_PM_DSS_DSS_WKDEP_OFFSET 0x0020 | 298 | #define OMAP4_PM_DSS_DSS_WKDEP_OFFSET 0x0020 |
| 242 | #define OMAP4430_PM_DSS_DSS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0020) | 299 | #define OMAP4430_PM_DSS_DSS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0020) |
| 243 | #define OMAP4_RM_DSS_DSS_CONTEXT_OFFSET 0x0024 | 300 | #define OMAP4_RM_DSS_DSS_CONTEXT_OFFSET 0x0024 |
| 244 | #define OMAP4430_RM_DSS_DSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0024) | 301 | #define OMAP4430_RM_DSS_DSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0024) |
| 245 | #define OMAP4_RM_DSS_DEISS_CONTEXT_OFFSET 0x002c | 302 | #define OMAP4_RM_DSS_DEISS_CONTEXT_OFFSET 0x002c |
| 246 | #define OMAP4430_RM_DSS_DEISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x002c) | 303 | #define OMAP4430_RM_DSS_DEISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x002c) |
| 247 | 304 | ||
| 248 | /* PRM.GFX_PRM register offsets */ | 305 | /* PRM.GFX_PRM register offsets */ |
| 249 | #define OMAP4_PM_GFX_PWRSTCTRL_OFFSET 0x0000 | 306 | #define OMAP4_PM_GFX_PWRSTCTRL_OFFSET 0x0000 |
| 250 | #define OMAP4430_PM_GFX_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0000) | 307 | #define OMAP4430_PM_GFX_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0000) |
| 251 | #define OMAP4_PM_GFX_PWRSTST_OFFSET 0x0004 | 308 | #define OMAP4_PM_GFX_PWRSTST_OFFSET 0x0004 |
| 252 | #define OMAP4430_PM_GFX_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0004) | 309 | #define OMAP4430_PM_GFX_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0004) |
| 253 | #define OMAP4_RM_GFX_GFX_CONTEXT_OFFSET 0x0024 | 310 | #define OMAP4_RM_GFX_GFX_CONTEXT_OFFSET 0x0024 |
| 254 | #define OMAP4430_RM_GFX_GFX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0024) | 311 | #define OMAP4430_RM_GFX_GFX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0024) |
| 255 | 312 | ||
| 256 | /* PRM.L3INIT_PRM register offsets */ | 313 | /* PRM.L3INIT_PRM register offsets */ |
| 257 | #define OMAP4_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000 | 314 | #define OMAP4_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000 |
| 258 | #define OMAP4430_PM_L3INIT_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0000) | 315 | #define OMAP4430_PM_L3INIT_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0000) |
| 259 | #define OMAP4_PM_L3INIT_PWRSTST_OFFSET 0x0004 | 316 | #define OMAP4_PM_L3INIT_PWRSTST_OFFSET 0x0004 |
| 260 | #define OMAP4430_PM_L3INIT_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0004) | 317 | #define OMAP4430_PM_L3INIT_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0004) |
| 261 | #define OMAP4_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028 | 318 | #define OMAP4_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028 |
| 262 | #define OMAP4430_PM_L3INIT_MMC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0028) | 319 | #define OMAP4430_PM_L3INIT_MMC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0028) |
| 263 | #define OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c | 320 | #define OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c |
| 264 | #define OMAP4430_RM_L3INIT_MMC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x002c) | 321 | #define OMAP4430_RM_L3INIT_MMC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x002c) |
| 265 | #define OMAP4_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030 | 322 | #define OMAP4_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030 |
| 266 | #define OMAP4430_PM_L3INIT_MMC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0030) | 323 | #define OMAP4430_PM_L3INIT_MMC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0030) |
| 267 | #define OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034 | 324 | #define OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034 |
| 268 | #define OMAP4430_RM_L3INIT_MMC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0034) | 325 | #define OMAP4430_RM_L3INIT_MMC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0034) |
| 269 | #define OMAP4_PM_L3INIT_HSI_WKDEP_OFFSET 0x0038 | 326 | #define OMAP4_PM_L3INIT_HSI_WKDEP_OFFSET 0x0038 |
| 270 | #define OMAP4430_PM_L3INIT_HSI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0038) | 327 | #define OMAP4430_PM_L3INIT_HSI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0038) |
| 271 | #define OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET 0x003c | 328 | #define OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET 0x003c |
| 272 | #define OMAP4430_RM_L3INIT_HSI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x003c) | 329 | #define OMAP4430_RM_L3INIT_HSI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x003c) |
| 273 | #define OMAP4_PM_L3INIT_UNIPRO1_WKDEP_OFFSET 0x0040 | 330 | #define OMAP4_PM_L3INIT_UNIPRO1_WKDEP_OFFSET 0x0040 |
| 274 | #define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0040) | 331 | #define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0040) |
| 275 | #define OMAP4_RM_L3INIT_UNIPRO1_CONTEXT_OFFSET 0x0044 | 332 | #define OMAP4_RM_L3INIT_UNIPRO1_CONTEXT_OFFSET 0x0044 |
| 276 | #define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0044) | 333 | #define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0044) |
| 277 | #define OMAP4_PM_L3INIT_USB_HOST_WKDEP_OFFSET 0x0058 | 334 | #define OMAP4_PM_L3INIT_USB_HOST_WKDEP_OFFSET 0x0058 |
| 278 | #define OMAP4430_PM_L3INIT_USB_HOST_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0058) | 335 | #define OMAP4430_PM_L3INIT_USB_HOST_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0058) |
| 279 | #define OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET 0x005c | 336 | #define OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET 0x005c |
| 280 | #define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x005c) | 337 | #define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x005c) |
| 281 | #define OMAP4_PM_L3INIT_USB_OTG_WKDEP_OFFSET 0x0060 | 338 | #define OMAP4_PM_L3INIT_USB_OTG_WKDEP_OFFSET 0x0060 |
| 282 | #define OMAP4430_PM_L3INIT_USB_OTG_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0060) | 339 | #define OMAP4430_PM_L3INIT_USB_OTG_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0060) |
| 283 | #define OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET 0x0064 | 340 | #define OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET 0x0064 |
| 284 | #define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0064) | 341 | #define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0064) |
| 285 | #define OMAP4_PM_L3INIT_USB_TLL_WKDEP_OFFSET 0x0068 | 342 | #define OMAP4_PM_L3INIT_USB_TLL_WKDEP_OFFSET 0x0068 |
| 286 | #define OMAP4430_PM_L3INIT_USB_TLL_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0068) | 343 | #define OMAP4430_PM_L3INIT_USB_TLL_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0068) |
| 287 | #define OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET 0x006c | 344 | #define OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET 0x006c |
| 288 | #define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x006c) | 345 | #define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x006c) |
| 289 | #define OMAP4_RM_L3INIT_P1500_CONTEXT_OFFSET 0x007c | 346 | #define OMAP4_RM_L3INIT_P1500_CONTEXT_OFFSET 0x007c |
| 290 | #define OMAP4430_RM_L3INIT_P1500_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x007c) | 347 | #define OMAP4430_RM_L3INIT_P1500_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x007c) |
| 291 | #define OMAP4_RM_L3INIT_EMAC_CONTEXT_OFFSET 0x0084 | 348 | #define OMAP4_RM_L3INIT_EMAC_CONTEXT_OFFSET 0x0084 |
| 292 | #define OMAP4430_RM_L3INIT_EMAC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0084) | 349 | #define OMAP4430_RM_L3INIT_EMAC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0084) |
| 293 | #define OMAP4_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088 | 350 | #define OMAP4_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088 |
| 294 | #define OMAP4430_PM_L3INIT_SATA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0088) | 351 | #define OMAP4430_PM_L3INIT_SATA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0088) |
| 295 | #define OMAP4_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c | 352 | #define OMAP4_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c |
| 296 | #define OMAP4430_RM_L3INIT_SATA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x008c) | 353 | #define OMAP4430_RM_L3INIT_SATA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x008c) |
| 297 | #define OMAP4_RM_L3INIT_TPPSS_CONTEXT_OFFSET 0x0094 | 354 | #define OMAP4_RM_L3INIT_TPPSS_CONTEXT_OFFSET 0x0094 |
| 298 | #define OMAP4430_RM_L3INIT_TPPSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0094) | 355 | #define OMAP4430_RM_L3INIT_TPPSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0094) |
| 299 | #define OMAP4_PM_L3INIT_PCIESS_WKDEP_OFFSET 0x0098 | 356 | #define OMAP4_PM_L3INIT_PCIESS_WKDEP_OFFSET 0x0098 |
| 300 | #define OMAP4430_PM_L3INIT_PCIESS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0098) | 357 | #define OMAP4430_PM_L3INIT_PCIESS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0098) |
| 301 | #define OMAP4_RM_L3INIT_PCIESS_CONTEXT_OFFSET 0x009c | 358 | #define OMAP4_RM_L3INIT_PCIESS_CONTEXT_OFFSET 0x009c |
| 302 | #define OMAP4430_RM_L3INIT_PCIESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x009c) | 359 | #define OMAP4430_RM_L3INIT_PCIESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x009c) |
| 303 | #define OMAP4_RM_L3INIT_CCPTX_CONTEXT_OFFSET 0x00ac | 360 | #define OMAP4_RM_L3INIT_CCPTX_CONTEXT_OFFSET 0x00ac |
| 304 | #define OMAP4430_RM_L3INIT_CCPTX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00ac) | 361 | #define OMAP4430_RM_L3INIT_CCPTX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00ac) |
| 305 | #define OMAP4_PM_L3INIT_XHPI_WKDEP_OFFSET 0x00c0 | 362 | #define OMAP4_PM_L3INIT_XHPI_WKDEP_OFFSET 0x00c0 |
| 306 | #define OMAP4430_PM_L3INIT_XHPI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c0) | 363 | #define OMAP4430_PM_L3INIT_XHPI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c0) |
| 307 | #define OMAP4_RM_L3INIT_XHPI_CONTEXT_OFFSET 0x00c4 | 364 | #define OMAP4_RM_L3INIT_XHPI_CONTEXT_OFFSET 0x00c4 |
| 308 | #define OMAP4430_RM_L3INIT_XHPI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c4) | 365 | #define OMAP4430_RM_L3INIT_XHPI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c4) |
| 309 | #define OMAP4_PM_L3INIT_MMC6_WKDEP_OFFSET 0x00c8 | 366 | #define OMAP4_PM_L3INIT_MMC6_WKDEP_OFFSET 0x00c8 |
| 310 | #define OMAP4430_PM_L3INIT_MMC6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c8) | 367 | #define OMAP4430_PM_L3INIT_MMC6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c8) |
| 311 | #define OMAP4_RM_L3INIT_MMC6_CONTEXT_OFFSET 0x00cc | 368 | #define OMAP4_RM_L3INIT_MMC6_CONTEXT_OFFSET 0x00cc |
| 312 | #define OMAP4430_RM_L3INIT_MMC6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00cc) | 369 | #define OMAP4430_RM_L3INIT_MMC6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00cc) |
| 313 | #define OMAP4_PM_L3INIT_USB_HOST_FS_WKDEP_OFFSET 0x00d0 | 370 | #define OMAP4_PM_L3INIT_USB_HOST_FS_WKDEP_OFFSET 0x00d0 |
| 314 | #define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d0) | 371 | #define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00d0) |
| 315 | #define OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET 0x00d4 | 372 | #define OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET 0x00d4 |
| 316 | #define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d4) | 373 | #define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00d4) |
| 317 | #define OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET 0x00e4 | 374 | #define OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET 0x00e4 |
| 318 | #define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00e4) | 375 | #define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00e4) |
| 319 | 376 | ||
| 320 | /* PRM.L4PER_PRM register offsets */ | 377 | /* PRM.L4PER_PRM register offsets */ |
| 321 | #define OMAP4_PM_L4PER_PWRSTCTRL_OFFSET 0x0000 | 378 | #define OMAP4_PM_L4PER_PWRSTCTRL_OFFSET 0x0000 |
| 322 | #define OMAP4430_PM_L4PER_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0000) | 379 | #define OMAP4430_PM_L4PER_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0000) |
| 323 | #define OMAP4_PM_L4PER_PWRSTST_OFFSET 0x0004 | 380 | #define OMAP4_PM_L4PER_PWRSTST_OFFSET 0x0004 |
| 324 | #define OMAP4430_PM_L4PER_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0004) | 381 | #define OMAP4430_PM_L4PER_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0004) |
| 325 | #define OMAP4_RM_L4PER_ADC_CONTEXT_OFFSET 0x0024 | 382 | #define OMAP4_RM_L4PER_ADC_CONTEXT_OFFSET 0x0024 |
| 326 | #define OMAP4430_RM_L4PER_ADC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0024) | 383 | #define OMAP4430_RM_L4PER_ADC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0024) |
| 327 | #define OMAP4_PM_L4PER_DMTIMER10_WKDEP_OFFSET 0x0028 | 384 | #define OMAP4_PM_L4PER_DMTIMER10_WKDEP_OFFSET 0x0028 |
| 328 | #define OMAP4430_PM_L4PER_DMTIMER10_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0028) | 385 | #define OMAP4430_PM_L4PER_DMTIMER10_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0028) |
| 329 | #define OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET 0x002c | 386 | #define OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET 0x002c |
| 330 | #define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x002c) | 387 | #define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x002c) |
| 331 | #define OMAP4_PM_L4PER_DMTIMER11_WKDEP_OFFSET 0x0030 | 388 | #define OMAP4_PM_L4PER_DMTIMER11_WKDEP_OFFSET 0x0030 |
| 332 | #define OMAP4430_PM_L4PER_DMTIMER11_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0030) | 389 | #define OMAP4430_PM_L4PER_DMTIMER11_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0030) |
| 333 | #define OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET 0x0034 | 390 | #define OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET 0x0034 |
| 334 | #define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0034) | 391 | #define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0034) |
| 335 | #define OMAP4_PM_L4PER_DMTIMER2_WKDEP_OFFSET 0x0038 | 392 | #define OMAP4_PM_L4PER_DMTIMER2_WKDEP_OFFSET 0x0038 |
| 336 | #define OMAP4430_PM_L4PER_DMTIMER2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0038) | 393 | #define OMAP4430_PM_L4PER_DMTIMER2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0038) |
| 337 | #define OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET 0x003c | 394 | #define OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET 0x003c |
| 338 | #define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x003c) | 395 | #define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x003c) |
| 339 | #define OMAP4_PM_L4PER_DMTIMER3_WKDEP_OFFSET 0x0040 | 396 | #define OMAP4_PM_L4PER_DMTIMER3_WKDEP_OFFSET 0x0040 |
| 340 | #define OMAP4430_PM_L4PER_DMTIMER3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0040) | 397 | #define OMAP4430_PM_L4PER_DMTIMER3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0040) |
| 341 | #define OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET 0x0044 | 398 | #define OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET 0x0044 |
| 342 | #define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0044) | 399 | #define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0044) |
| 343 | #define OMAP4_PM_L4PER_DMTIMER4_WKDEP_OFFSET 0x0048 | 400 | #define OMAP4_PM_L4PER_DMTIMER4_WKDEP_OFFSET 0x0048 |
| 344 | #define OMAP4430_PM_L4PER_DMTIMER4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0048) | 401 | #define OMAP4430_PM_L4PER_DMTIMER4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0048) |
| 345 | #define OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET 0x004c | 402 | #define OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET 0x004c |
| 346 | #define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x004c) | 403 | #define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x004c) |
| 347 | #define OMAP4_PM_L4PER_DMTIMER9_WKDEP_OFFSET 0x0050 | 404 | #define OMAP4_PM_L4PER_DMTIMER9_WKDEP_OFFSET 0x0050 |
| 348 | #define OMAP4430_PM_L4PER_DMTIMER9_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0050) | 405 | #define OMAP4430_PM_L4PER_DMTIMER9_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0050) |
| 349 | #define OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET 0x0054 | 406 | #define OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET 0x0054 |
| 350 | #define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0054) | 407 | #define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0054) |
| 351 | #define OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET 0x005c | 408 | #define OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET 0x005c |
| 352 | #define OMAP4430_RM_L4PER_ELM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x005c) | 409 | #define OMAP4430_RM_L4PER_ELM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x005c) |
| 353 | #define OMAP4_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0060 | 410 | #define OMAP4_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0060 |
| 354 | #define OMAP4430_PM_L4PER_GPIO2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0060) | 411 | #define OMAP4430_PM_L4PER_GPIO2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0060) |
| 355 | #define OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0064 | 412 | #define OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0064 |
| 356 | #define OMAP4430_RM_L4PER_GPIO2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0064) | 413 | #define OMAP4430_RM_L4PER_GPIO2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0064) |
| 357 | #define OMAP4_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0068 | 414 | #define OMAP4_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0068 |
| 358 | #define OMAP4430_PM_L4PER_GPIO3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0068) | 415 | #define OMAP4430_PM_L4PER_GPIO3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0068) |
| 359 | #define OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x006c | 416 | #define OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x006c |
| 360 | #define OMAP4430_RM_L4PER_GPIO3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x006c) | 417 | #define OMAP4430_RM_L4PER_GPIO3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x006c) |
| 361 | #define OMAP4_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0070 | 418 | #define OMAP4_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0070 |
| 362 | #define OMAP4430_PM_L4PER_GPIO4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0070) | 419 | #define OMAP4430_PM_L4PER_GPIO4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0070) |
| 363 | #define OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0074 | 420 | #define OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0074 |
| 364 | #define OMAP4430_RM_L4PER_GPIO4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0074) | 421 | #define OMAP4430_RM_L4PER_GPIO4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0074) |
| 365 | #define OMAP4_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0078 | 422 | #define OMAP4_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0078 |
| 366 | #define OMAP4430_PM_L4PER_GPIO5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0078) | 423 | #define OMAP4430_PM_L4PER_GPIO5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0078) |
| 367 | #define OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x007c | 424 | #define OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x007c |
| 368 | #define OMAP4430_RM_L4PER_GPIO5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x007c) | 425 | #define OMAP4430_RM_L4PER_GPIO5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x007c) |
| 369 | #define OMAP4_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0080 | 426 | #define OMAP4_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0080 |
| 370 | #define OMAP4430_PM_L4PER_GPIO6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0080) | 427 | #define OMAP4430_PM_L4PER_GPIO6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0080) |
| 371 | #define OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0084 | 428 | #define OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0084 |
| 372 | #define OMAP4430_RM_L4PER_GPIO6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0084) | 429 | #define OMAP4430_RM_L4PER_GPIO6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0084) |
| 373 | #define OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x008c | 430 | #define OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x008c |
| 374 | #define OMAP4430_RM_L4PER_HDQ1W_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x008c) | 431 | #define OMAP4430_RM_L4PER_HDQ1W_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x008c) |
| 375 | #define OMAP4_PM_L4PER_HECC1_WKDEP_OFFSET 0x0090 | 432 | #define OMAP4_PM_L4PER_HECC1_WKDEP_OFFSET 0x0090 |
| 376 | #define OMAP4430_PM_L4PER_HECC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0090) | 433 | #define OMAP4430_PM_L4PER_HECC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0090) |
| 377 | #define OMAP4_RM_L4PER_HECC1_CONTEXT_OFFSET 0x0094 | 434 | #define OMAP4_RM_L4PER_HECC1_CONTEXT_OFFSET 0x0094 |
| 378 | #define OMAP4430_RM_L4PER_HECC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0094) | 435 | #define OMAP4430_RM_L4PER_HECC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0094) |
| 379 | #define OMAP4_PM_L4PER_HECC2_WKDEP_OFFSET 0x0098 | 436 | #define OMAP4_PM_L4PER_HECC2_WKDEP_OFFSET 0x0098 |
| 380 | #define OMAP4430_PM_L4PER_HECC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0098) | 437 | #define OMAP4430_PM_L4PER_HECC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0098) |
| 381 | #define OMAP4_RM_L4PER_HECC2_CONTEXT_OFFSET 0x009c | 438 | #define OMAP4_RM_L4PER_HECC2_CONTEXT_OFFSET 0x009c |
| 382 | #define OMAP4430_RM_L4PER_HECC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x009c) | 439 | #define OMAP4430_RM_L4PER_HECC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x009c) |
| 383 | #define OMAP4_PM_L4PER_I2C1_WKDEP_OFFSET 0x00a0 | 440 | #define OMAP4_PM_L4PER_I2C1_WKDEP_OFFSET 0x00a0 |
| 384 | #define OMAP4430_PM_L4PER_I2C1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a0) | 441 | #define OMAP4430_PM_L4PER_I2C1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a0) |
| 385 | #define OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET 0x00a4 | 442 | #define OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET 0x00a4 |
| 386 | #define OMAP4430_RM_L4PER_I2C1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a4) | 443 | #define OMAP4430_RM_L4PER_I2C1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a4) |
| 387 | #define OMAP4_PM_L4PER_I2C2_WKDEP_OFFSET 0x00a8 | 444 | #define OMAP4_PM_L4PER_I2C2_WKDEP_OFFSET 0x00a8 |
| 388 | #define OMAP4430_PM_L4PER_I2C2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a8) | 445 | #define OMAP4430_PM_L4PER_I2C2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a8) |
| 389 | #define OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET 0x00ac | 446 | #define OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET 0x00ac |
| 390 | #define OMAP4430_RM_L4PER_I2C2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ac) | 447 | #define OMAP4430_RM_L4PER_I2C2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00ac) |
| 391 | #define OMAP4_PM_L4PER_I2C3_WKDEP_OFFSET 0x00b0 | 448 | #define OMAP4_PM_L4PER_I2C3_WKDEP_OFFSET 0x00b0 |
| 392 | #define OMAP4430_PM_L4PER_I2C3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b0) | 449 | #define OMAP4430_PM_L4PER_I2C3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b0) |
| 393 | #define OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET 0x00b4 | 450 | #define OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET 0x00b4 |
| 394 | #define OMAP4430_RM_L4PER_I2C3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b4) | 451 | #define OMAP4430_RM_L4PER_I2C3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b4) |
| 395 | #define OMAP4_PM_L4PER_I2C4_WKDEP_OFFSET 0x00b8 | 452 | #define OMAP4_PM_L4PER_I2C4_WKDEP_OFFSET 0x00b8 |
| 396 | #define OMAP4430_PM_L4PER_I2C4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b8) | 453 | #define OMAP4430_PM_L4PER_I2C4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b8) |
| 397 | #define OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET 0x00bc | 454 | #define OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET 0x00bc |
| 398 | #define OMAP4430_RM_L4PER_I2C4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00bc) | 455 | #define OMAP4430_RM_L4PER_I2C4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00bc) |
| 399 | #define OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET 0x00c0 | 456 | #define OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET 0x00c0 |
| 400 | #define OMAP4430_RM_L4PER_L4_PER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00c0) | 457 | #define OMAP4430_RM_L4PER_L4_PER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00c0) |
| 401 | #define OMAP4_PM_L4PER_MCASP2_WKDEP_OFFSET 0x00d0 | 458 | #define OMAP4_PM_L4PER_MCASP2_WKDEP_OFFSET 0x00d0 |
| 402 | #define OMAP4430_PM_L4PER_MCASP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d0) | 459 | #define OMAP4430_PM_L4PER_MCASP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d0) |
| 403 | #define OMAP4_RM_L4PER_MCASP2_CONTEXT_OFFSET 0x00d4 | 460 | #define OMAP4_RM_L4PER_MCASP2_CONTEXT_OFFSET 0x00d4 |
| 404 | #define OMAP4430_RM_L4PER_MCASP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d4) | 461 | #define OMAP4430_RM_L4PER_MCASP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d4) |
| 405 | #define OMAP4_PM_L4PER_MCASP3_WKDEP_OFFSET 0x00d8 | 462 | #define OMAP4_PM_L4PER_MCASP3_WKDEP_OFFSET 0x00d8 |
| 406 | #define OMAP4430_PM_L4PER_MCASP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d8) | 463 | #define OMAP4430_PM_L4PER_MCASP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d8) |
| 407 | #define OMAP4_RM_L4PER_MCASP3_CONTEXT_OFFSET 0x00dc | 464 | #define OMAP4_RM_L4PER_MCASP3_CONTEXT_OFFSET 0x00dc |
| 408 | #define OMAP4430_RM_L4PER_MCASP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00dc) | 465 | #define OMAP4430_RM_L4PER_MCASP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00dc) |
| 409 | #define OMAP4_PM_L4PER_MCBSP4_WKDEP_OFFSET 0x00e0 | 466 | #define OMAP4_PM_L4PER_MCBSP4_WKDEP_OFFSET 0x00e0 |
| 410 | #define OMAP4430_PM_L4PER_MCBSP4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e0) | 467 | #define OMAP4430_PM_L4PER_MCBSP4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00e0) |
| 411 | #define OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET 0x00e4 | 468 | #define OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET 0x00e4 |
| 412 | #define OMAP4430_RM_L4PER_MCBSP4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e4) | 469 | #define OMAP4430_RM_L4PER_MCBSP4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00e4) |
| 413 | #define OMAP4_RM_L4PER_MGATE_CONTEXT_OFFSET 0x00ec | 470 | #define OMAP4_RM_L4PER_MGATE_CONTEXT_OFFSET 0x00ec |
| 414 | #define OMAP4430_RM_L4PER_MGATE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ec) | 471 | #define OMAP4430_RM_L4PER_MGATE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00ec) |
| 415 | #define OMAP4_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x00f0 | 472 | #define OMAP4_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x00f0 |
| 416 | #define OMAP4430_PM_L4PER_MCSPI1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f0) | 473 | #define OMAP4430_PM_L4PER_MCSPI1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f0) |
| 417 | #define OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x00f4 | 474 | #define OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x00f4 |
| 418 | #define OMAP4430_RM_L4PER_MCSPI1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f4) | 475 | #define OMAP4430_RM_L4PER_MCSPI1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f4) |
| 419 | #define OMAP4_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x00f8 | 476 | #define OMAP4_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x00f8 |
| 420 | #define OMAP4430_PM_L4PER_MCSPI2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f8) | 477 | #define OMAP4430_PM_L4PER_MCSPI2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f8) |
| 421 | #define OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x00fc | 478 | #define OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x00fc |
| 422 | #define OMAP4430_RM_L4PER_MCSPI2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00fc) | 479 | #define OMAP4430_RM_L4PER_MCSPI2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00fc) |
| 423 | #define OMAP4_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0100 | 480 | #define OMAP4_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0100 |
| 424 | #define OMAP4430_PM_L4PER_MCSPI3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0100) | 481 | #define OMAP4430_PM_L4PER_MCSPI3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0100) |
| 425 | #define OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0104 | 482 | #define OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0104 |
| 426 | #define OMAP4430_RM_L4PER_MCSPI3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0104) | 483 | #define OMAP4430_RM_L4PER_MCSPI3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0104) |
| 427 | #define OMAP4_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0108 | 484 | #define OMAP4_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0108 |
| 428 | #define OMAP4430_PM_L4PER_MCSPI4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0108) | 485 | #define OMAP4430_PM_L4PER_MCSPI4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0108) |
| 429 | #define OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x010c | 486 | #define OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x010c |
| 430 | #define OMAP4430_RM_L4PER_MCSPI4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x010c) | 487 | #define OMAP4430_RM_L4PER_MCSPI4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x010c) |
| 431 | #define OMAP4_PM_L4PER_MMCSD3_WKDEP_OFFSET 0x0120 | 488 | #define OMAP4_PM_L4PER_MMCSD3_WKDEP_OFFSET 0x0120 |
| 432 | #define OMAP4430_PM_L4PER_MMCSD3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0120) | 489 | #define OMAP4430_PM_L4PER_MMCSD3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0120) |
| 433 | #define OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET 0x0124 | 490 | #define OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET 0x0124 |
| 434 | #define OMAP4430_RM_L4PER_MMCSD3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0124) | 491 | #define OMAP4430_RM_L4PER_MMCSD3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0124) |
| 435 | #define OMAP4_PM_L4PER_MMCSD4_WKDEP_OFFSET 0x0128 | 492 | #define OMAP4_PM_L4PER_MMCSD4_WKDEP_OFFSET 0x0128 |
| 436 | #define OMAP4430_PM_L4PER_MMCSD4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0128) | 493 | #define OMAP4430_PM_L4PER_MMCSD4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0128) |
| 437 | #define OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET 0x012c | 494 | #define OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET 0x012c |
| 438 | #define OMAP4430_RM_L4PER_MMCSD4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x012c) | 495 | #define OMAP4430_RM_L4PER_MMCSD4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x012c) |
| 439 | #define OMAP4_RM_L4PER_MSPROHG_CONTEXT_OFFSET 0x0134 | 496 | #define OMAP4_RM_L4PER_MSPROHG_CONTEXT_OFFSET 0x0134 |
| 440 | #define OMAP4430_RM_L4PER_MSPROHG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0134) | 497 | #define OMAP4430_RM_L4PER_MSPROHG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0134) |
| 441 | #define OMAP4_PM_L4PER_SLIMBUS2_WKDEP_OFFSET 0x0138 | 498 | #define OMAP4_PM_L4PER_SLIMBUS2_WKDEP_OFFSET 0x0138 |
| 442 | #define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0138) | 499 | #define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0138) |
| 443 | #define OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET 0x013c | 500 | #define OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET 0x013c |
| 444 | #define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x013c) | 501 | #define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x013c) |
| 445 | #define OMAP4_PM_L4PER_UART1_WKDEP_OFFSET 0x0140 | 502 | #define OMAP4_PM_L4PER_UART1_WKDEP_OFFSET 0x0140 |
| 446 | #define OMAP4430_PM_L4PER_UART1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0140) | 503 | #define OMAP4430_PM_L4PER_UART1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0140) |
| 447 | #define OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET 0x0144 | 504 | #define OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET 0x0144 |
| 448 | #define OMAP4430_RM_L4PER_UART1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0144) | 505 | #define OMAP4430_RM_L4PER_UART1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0144) |
| 449 | #define OMAP4_PM_L4PER_UART2_WKDEP_OFFSET 0x0148 | 506 | #define OMAP4_PM_L4PER_UART2_WKDEP_OFFSET 0x0148 |
| 450 | #define OMAP4430_PM_L4PER_UART2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0148) | 507 | #define OMAP4430_PM_L4PER_UART2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0148) |
| 451 | #define OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET 0x014c | 508 | #define OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET 0x014c |
| 452 | #define OMAP4430_RM_L4PER_UART2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x014c) | 509 | #define OMAP4430_RM_L4PER_UART2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x014c) |
| 453 | #define OMAP4_PM_L4PER_UART3_WKDEP_OFFSET 0x0150 | 510 | #define OMAP4_PM_L4PER_UART3_WKDEP_OFFSET 0x0150 |
| 454 | #define OMAP4430_PM_L4PER_UART3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0150) | 511 | #define OMAP4430_PM_L4PER_UART3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0150) |
| 455 | #define OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET 0x0154 | 512 | #define OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET 0x0154 |
| 456 | #define OMAP4430_RM_L4PER_UART3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0154) | 513 | #define OMAP4430_RM_L4PER_UART3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0154) |
| 457 | #define OMAP4_PM_L4PER_UART4_WKDEP_OFFSET 0x0158 | 514 | #define OMAP4_PM_L4PER_UART4_WKDEP_OFFSET 0x0158 |
| 458 | #define OMAP4430_PM_L4PER_UART4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0158) | 515 | #define OMAP4430_PM_L4PER_UART4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0158) |
| 459 | #define OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET 0x015c | 516 | #define OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET 0x015c |
| 460 | #define OMAP4430_RM_L4PER_UART4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x015c) | 517 | #define OMAP4430_RM_L4PER_UART4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x015c) |
| 461 | #define OMAP4_PM_L4PER_MMCSD5_WKDEP_OFFSET 0x0160 | 518 | #define OMAP4_PM_L4PER_MMCSD5_WKDEP_OFFSET 0x0160 |
| 462 | #define OMAP4430_PM_L4PER_MMCSD5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0160) | 519 | #define OMAP4430_PM_L4PER_MMCSD5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0160) |
| 463 | #define OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET 0x0164 | 520 | #define OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET 0x0164 |
| 464 | #define OMAP4430_RM_L4PER_MMCSD5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0164) | 521 | #define OMAP4430_RM_L4PER_MMCSD5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0164) |
| 465 | #define OMAP4_PM_L4PER_I2C5_WKDEP_OFFSET 0x0168 | 522 | #define OMAP4_PM_L4PER_I2C5_WKDEP_OFFSET 0x0168 |
| 466 | #define OMAP4430_PM_L4PER_I2C5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0168) | 523 | #define OMAP4430_PM_L4PER_I2C5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0168) |
| 467 | #define OMAP4_RM_L4PER_I2C5_CONTEXT_OFFSET 0x016c | 524 | #define OMAP4_RM_L4PER_I2C5_CONTEXT_OFFSET 0x016c |
| 468 | #define OMAP4430_RM_L4PER_I2C5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x016c) | 525 | #define OMAP4430_RM_L4PER_I2C5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x016c) |
| 469 | #define OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET 0x01a4 | 526 | #define OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET 0x01a4 |
| 470 | #define OMAP4430_RM_L4SEC_AES1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01a4) | 527 | #define OMAP4430_RM_L4SEC_AES1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01a4) |
| 471 | #define OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET 0x01ac | 528 | #define OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET 0x01ac |
| 472 | #define OMAP4430_RM_L4SEC_AES2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01ac) | 529 | #define OMAP4430_RM_L4SEC_AES2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01ac) |
| 473 | #define OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x01b4 | 530 | #define OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x01b4 |
| 474 | #define OMAP4430_RM_L4SEC_DES3DES_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01b4) | 531 | #define OMAP4430_RM_L4SEC_DES3DES_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01b4) |
| 475 | #define OMAP4_RM_L4SEC_PKAEIP29_CONTEXT_OFFSET 0x01bc | 532 | #define OMAP4_RM_L4SEC_PKAEIP29_CONTEXT_OFFSET 0x01bc |
| 476 | #define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01bc) | 533 | #define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01bc) |
| 477 | #define OMAP4_RM_L4SEC_RNG_CONTEXT_OFFSET 0x01c4 | 534 | #define OMAP4_RM_L4SEC_RNG_CONTEXT_OFFSET 0x01c4 |
| 478 | #define OMAP4430_RM_L4SEC_RNG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01c4) | 535 | #define OMAP4430_RM_L4SEC_RNG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01c4) |
| 479 | #define OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET 0x01cc | 536 | #define OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET 0x01cc |
| 480 | #define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01cc) | 537 | #define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01cc) |
| 481 | #define OMAP4_RM_L4SEC_CRYPTODMA_CONTEXT_OFFSET 0x01dc | 538 | #define OMAP4_RM_L4SEC_CRYPTODMA_CONTEXT_OFFSET 0x01dc |
| 482 | #define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01dc) | 539 | #define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01dc) |
| 483 | 540 | ||
| 484 | /* PRM.CEFUSE_PRM register offsets */ | 541 | /* PRM.CEFUSE_PRM register offsets */ |
| 485 | #define OMAP4_PM_CEFUSE_PWRSTCTRL_OFFSET 0x0000 | 542 | #define OMAP4_PM_CEFUSE_PWRSTCTRL_OFFSET 0x0000 |
| 486 | #define OMAP4430_PM_CEFUSE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0000) | 543 | #define OMAP4430_PM_CEFUSE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0000) |
| 487 | #define OMAP4_PM_CEFUSE_PWRSTST_OFFSET 0x0004 | 544 | #define OMAP4_PM_CEFUSE_PWRSTST_OFFSET 0x0004 |
| 488 | #define OMAP4430_PM_CEFUSE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0004) | 545 | #define OMAP4430_PM_CEFUSE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0004) |
| 489 | #define OMAP4_RM_CEFUSE_CEFUSE_CONTEXT_OFFSET 0x0024 | 546 | #define OMAP4_RM_CEFUSE_CEFUSE_CONTEXT_OFFSET 0x0024 |
| 490 | #define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0024) | 547 | #define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0024) |
| 491 | 548 | ||
| 492 | /* PRM.WKUP_PRM register offsets */ | 549 | /* PRM.WKUP_PRM register offsets */ |
| 493 | #define OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET 0x0024 | 550 | #define OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET 0x0024 |
| 494 | #define OMAP4430_RM_WKUP_L4WKUP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0024) | 551 | #define OMAP4430_RM_WKUP_L4WKUP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0024) |
| 495 | #define OMAP4_RM_WKUP_WDT1_CONTEXT_OFFSET 0x002c | 552 | #define OMAP4_RM_WKUP_WDT1_CONTEXT_OFFSET 0x002c |
| 496 | #define OMAP4430_RM_WKUP_WDT1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x002c) | 553 | #define OMAP4430_RM_WKUP_WDT1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x002c) |
| 497 | #define OMAP4_PM_WKUP_WDT2_WKDEP_OFFSET 0x0030 | 554 | #define OMAP4_PM_WKUP_WDT2_WKDEP_OFFSET 0x0030 |
| 498 | #define OMAP4430_PM_WKUP_WDT2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0030) | 555 | #define OMAP4430_PM_WKUP_WDT2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0030) |
| 499 | #define OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET 0x0034 | 556 | #define OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET 0x0034 |
| 500 | #define OMAP4430_RM_WKUP_WDT2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0034) | 557 | #define OMAP4430_RM_WKUP_WDT2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0034) |
| 501 | #define OMAP4_PM_WKUP_GPIO1_WKDEP_OFFSET 0x0038 | 558 | #define OMAP4_PM_WKUP_GPIO1_WKDEP_OFFSET 0x0038 |
| 502 | #define OMAP4430_PM_WKUP_GPIO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0038) | 559 | #define OMAP4430_PM_WKUP_GPIO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0038) |
| 503 | #define OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET 0x003c | 560 | #define OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET 0x003c |
| 504 | #define OMAP4430_RM_WKUP_GPIO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x003c) | 561 | #define OMAP4430_RM_WKUP_GPIO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x003c) |
| 505 | #define OMAP4_PM_WKUP_TIMER1_WKDEP_OFFSET 0x0040 | 562 | #define OMAP4_PM_WKUP_TIMER1_WKDEP_OFFSET 0x0040 |
| 506 | #define OMAP4430_PM_WKUP_TIMER1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0040) | 563 | #define OMAP4430_PM_WKUP_TIMER1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0040) |
| 507 | #define OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET 0x0044 | 564 | #define OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET 0x0044 |
| 508 | #define OMAP4430_RM_WKUP_TIMER1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0044) | 565 | #define OMAP4430_RM_WKUP_TIMER1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0044) |
| 509 | #define OMAP4_PM_WKUP_TIMER12_WKDEP_OFFSET 0x0048 | 566 | #define OMAP4_PM_WKUP_TIMER12_WKDEP_OFFSET 0x0048 |
| 510 | #define OMAP4430_PM_WKUP_TIMER12_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0048) | 567 | #define OMAP4430_PM_WKUP_TIMER12_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0048) |
| 511 | #define OMAP4_RM_WKUP_TIMER12_CONTEXT_OFFSET 0x004c | 568 | #define OMAP4_RM_WKUP_TIMER12_CONTEXT_OFFSET 0x004c |
| 512 | #define OMAP4430_RM_WKUP_TIMER12_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x004c) | 569 | #define OMAP4430_RM_WKUP_TIMER12_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x004c) |
| 513 | #define OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET 0x0054 | 570 | #define OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET 0x0054 |
| 514 | #define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0054) | 571 | #define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0054) |
| 515 | #define OMAP4_PM_WKUP_USIM_WKDEP_OFFSET 0x0058 | 572 | #define OMAP4_PM_WKUP_USIM_WKDEP_OFFSET 0x0058 |
| 516 | #define OMAP4430_PM_WKUP_USIM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0058) | 573 | #define OMAP4430_PM_WKUP_USIM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0058) |
| 517 | #define OMAP4_RM_WKUP_USIM_CONTEXT_OFFSET 0x005c | 574 | #define OMAP4_RM_WKUP_USIM_CONTEXT_OFFSET 0x005c |
| 518 | #define OMAP4430_RM_WKUP_USIM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x005c) | 575 | #define OMAP4430_RM_WKUP_USIM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x005c) |
| 519 | #define OMAP4_RM_WKUP_SARRAM_CONTEXT_OFFSET 0x0064 | 576 | #define OMAP4_RM_WKUP_SARRAM_CONTEXT_OFFSET 0x0064 |
| 520 | #define OMAP4430_RM_WKUP_SARRAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0064) | 577 | #define OMAP4430_RM_WKUP_SARRAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0064) |
| 521 | #define OMAP4_PM_WKUP_KEYBOARD_WKDEP_OFFSET 0x0078 | 578 | #define OMAP4_PM_WKUP_KEYBOARD_WKDEP_OFFSET 0x0078 |
| 522 | #define OMAP4430_PM_WKUP_KEYBOARD_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0078) | 579 | #define OMAP4430_PM_WKUP_KEYBOARD_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0078) |
| 523 | #define OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET 0x007c | 580 | #define OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET 0x007c |
| 524 | #define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x007c) | 581 | #define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x007c) |
| 525 | #define OMAP4_PM_WKUP_RTC_WKDEP_OFFSET 0x0080 | 582 | #define OMAP4_PM_WKUP_RTC_WKDEP_OFFSET 0x0080 |
| 526 | #define OMAP4430_PM_WKUP_RTC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0080) | 583 | #define OMAP4430_PM_WKUP_RTC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0080) |
| 527 | #define OMAP4_RM_WKUP_RTC_CONTEXT_OFFSET 0x0084 | 584 | #define OMAP4_RM_WKUP_RTC_CONTEXT_OFFSET 0x0084 |
| 528 | #define OMAP4430_RM_WKUP_RTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0084) | 585 | #define OMAP4430_RM_WKUP_RTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0084) |
| 529 | 586 | ||
| 530 | /* PRM.WKUP_CM register offsets */ | 587 | /* PRM.WKUP_CM register offsets */ |
| 531 | #define OMAP4_CM_WKUP_CLKSTCTRL_OFFSET 0x0000 | 588 | #define OMAP4_CM_WKUP_CLKSTCTRL_OFFSET 0x0000 |
| 532 | #define OMAP4430_CM_WKUP_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0000) | 589 | #define OMAP4430_CM_WKUP_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0000) |
| 533 | #define OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x0020 | 590 | #define OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x0020 |
| 534 | #define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0020) | 591 | #define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0020) |
| 535 | #define OMAP4_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x0028 | 592 | #define OMAP4_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x0028 |
| 536 | #define OMAP4430_CM_WKUP_WDT1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0028) | 593 | #define OMAP4430_CM_WKUP_WDT1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0028) |
| 537 | #define OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET 0x0030 | 594 | #define OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET 0x0030 |
| 538 | #define OMAP4430_CM_WKUP_WDT2_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0030) | 595 | #define OMAP4430_CM_WKUP_WDT2_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0030) |
| 539 | #define OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET 0x0038 | 596 | #define OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET 0x0038 |
| 540 | #define OMAP4430_CM_WKUP_GPIO1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0038) | 597 | #define OMAP4430_CM_WKUP_GPIO1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0038) |
| 541 | #define OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x0040 | 598 | #define OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x0040 |
| 542 | #define OMAP4430_CM_WKUP_TIMER1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0040) | 599 | #define OMAP4430_CM_WKUP_TIMER1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0040) |
| 543 | #define OMAP4_CM_WKUP_TIMER12_CLKCTRL_OFFSET 0x0048 | 600 | #define OMAP4_CM_WKUP_TIMER12_CLKCTRL_OFFSET 0x0048 |
| 544 | #define OMAP4430_CM_WKUP_TIMER12_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0048) | 601 | #define OMAP4430_CM_WKUP_TIMER12_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0048) |
| 545 | #define OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET 0x0050 | 602 | #define OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET 0x0050 |
| 546 | #define OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0050) | 603 | #define OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0050) |
| 547 | #define OMAP4_CM_WKUP_USIM_CLKCTRL_OFFSET 0x0058 | 604 | #define OMAP4_CM_WKUP_USIM_CLKCTRL_OFFSET 0x0058 |
| 548 | #define OMAP4430_CM_WKUP_USIM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0058) | 605 | #define OMAP4430_CM_WKUP_USIM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0058) |
| 549 | #define OMAP4_CM_WKUP_SARRAM_CLKCTRL_OFFSET 0x0060 | 606 | #define OMAP4_CM_WKUP_SARRAM_CLKCTRL_OFFSET 0x0060 |
| 550 | #define OMAP4430_CM_WKUP_SARRAM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0060) | 607 | #define OMAP4430_CM_WKUP_SARRAM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0060) |
| 551 | #define OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET 0x0078 | 608 | #define OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET 0x0078 |
| 552 | #define OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0078) | 609 | #define OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0078) |
| 553 | #define OMAP4_CM_WKUP_RTC_CLKCTRL_OFFSET 0x0080 | 610 | #define OMAP4_CM_WKUP_RTC_CLKCTRL_OFFSET 0x0080 |
| 554 | #define OMAP4430_CM_WKUP_RTC_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0080) | 611 | #define OMAP4430_CM_WKUP_RTC_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0080) |
| 555 | #define OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET 0x0088 | 612 | #define OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET 0x0088 |
| 556 | #define OMAP4430_CM_WKUP_BANDGAP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0088) | 613 | #define OMAP4430_CM_WKUP_BANDGAP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0088) |
| 557 | 614 | ||
| 558 | /* PRM.EMU_PRM register offsets */ | 615 | /* PRM.EMU_PRM register offsets */ |
| 559 | #define OMAP4_PM_EMU_PWRSTCTRL_OFFSET 0x0000 | 616 | #define OMAP4_PM_EMU_PWRSTCTRL_OFFSET 0x0000 |
| 560 | #define OMAP4430_PM_EMU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0000) | 617 | #define OMAP4430_PM_EMU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0000) |
| 561 | #define OMAP4_PM_EMU_PWRSTST_OFFSET 0x0004 | 618 | #define OMAP4_PM_EMU_PWRSTST_OFFSET 0x0004 |
| 562 | #define OMAP4430_PM_EMU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0004) | 619 | #define OMAP4430_PM_EMU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0004) |
| 563 | #define OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024 | 620 | #define OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024 |
| 564 | #define OMAP4430_RM_EMU_DEBUGSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0024) | 621 | #define OMAP4430_RM_EMU_DEBUGSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0024) |
| 565 | 622 | ||
| 566 | /* PRM.EMU_CM register offsets */ | 623 | /* PRM.EMU_CM register offsets */ |
| 567 | #define OMAP4_CM_EMU_CLKSTCTRL_OFFSET 0x0000 | 624 | #define OMAP4_CM_EMU_CLKSTCTRL_OFFSET 0x0000 |
| 568 | #define OMAP4430_CM_EMU_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0000) | 625 | #define OMAP4430_CM_EMU_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0000) |
| 569 | #define OMAP4_CM_EMU_DYNAMICDEP_OFFSET 0x0008 | 626 | #define OMAP4_CM_EMU_DYNAMICDEP_OFFSET 0x0008 |
| 570 | #define OMAP4430_CM_EMU_DYNAMICDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0008) | 627 | #define OMAP4430_CM_EMU_DYNAMICDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0008) |
| 571 | #define OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0020 | 628 | #define OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0020 |
| 572 | #define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0020) | 629 | #define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0020) |
| 573 | 630 | ||
| 574 | /* PRM.DEVICE_PRM register offsets */ | 631 | /* PRM.DEVICE_PRM register offsets */ |
| 575 | #define OMAP4_PRM_RSTCTRL_OFFSET 0x0000 | 632 | #define OMAP4_PRM_RSTCTRL_OFFSET 0x0000 |
| 576 | #define OMAP4430_PRM_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0000) | 633 | #define OMAP4430_PRM_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0000) |
| 577 | #define OMAP4_PRM_RSTST_OFFSET 0x0004 | 634 | #define OMAP4_PRM_RSTST_OFFSET 0x0004 |
| 578 | #define OMAP4430_PRM_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0004) | 635 | #define OMAP4430_PRM_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0004) |
| 579 | #define OMAP4_PRM_RSTTIME_OFFSET 0x0008 | 636 | #define OMAP4_PRM_RSTTIME_OFFSET 0x0008 |
| 580 | #define OMAP4430_PRM_RSTTIME OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0008) | 637 | #define OMAP4430_PRM_RSTTIME OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0008) |
| 581 | #define OMAP4_PRM_CLKREQCTRL_OFFSET 0x000c | 638 | #define OMAP4_PRM_CLKREQCTRL_OFFSET 0x000c |
| 582 | #define OMAP4430_PRM_CLKREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x000c) | 639 | #define OMAP4430_PRM_CLKREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x000c) |
| 583 | #define OMAP4_PRM_VOLTCTRL_OFFSET 0x0010 | 640 | #define OMAP4_PRM_VOLTCTRL_OFFSET 0x0010 |
| 584 | #define OMAP4430_PRM_VOLTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0010) | 641 | #define OMAP4430_PRM_VOLTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0010) |
| 585 | #define OMAP4_PRM_PWRREQCTRL_OFFSET 0x0014 | 642 | #define OMAP4_PRM_PWRREQCTRL_OFFSET 0x0014 |
| 586 | #define OMAP4430_PRM_PWRREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0014) | 643 | #define OMAP4430_PRM_PWRREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0014) |
| 587 | #define OMAP4_PRM_PSCON_COUNT_OFFSET 0x0018 | 644 | #define OMAP4_PRM_PSCON_COUNT_OFFSET 0x0018 |
| 588 | #define OMAP4430_PRM_PSCON_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0018) | 645 | #define OMAP4430_PRM_PSCON_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0018) |
| 589 | #define OMAP4_PRM_IO_COUNT_OFFSET 0x001c | 646 | #define OMAP4_PRM_IO_COUNT_OFFSET 0x001c |
| 590 | #define OMAP4430_PRM_IO_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x001c) | 647 | #define OMAP4430_PRM_IO_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x001c) |
| 591 | #define OMAP4_PRM_IO_PMCTRL_OFFSET 0x0020 | 648 | #define OMAP4_PRM_IO_PMCTRL_OFFSET 0x0020 |
| 592 | #define OMAP4430_PRM_IO_PMCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0020) | 649 | #define OMAP4430_PRM_IO_PMCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0020) |
| 593 | #define OMAP4_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024 | 650 | #define OMAP4_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024 |
| 594 | #define OMAP4430_PRM_VOLTSETUP_WARMRESET OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0024) | 651 | #define OMAP4430_PRM_VOLTSETUP_WARMRESET OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0024) |
| 595 | #define OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028 | 652 | #define OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028 |
| 596 | #define OMAP4430_PRM_VOLTSETUP_CORE_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0028) | 653 | #define OMAP4430_PRM_VOLTSETUP_CORE_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0028) |
| 597 | #define OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c | 654 | #define OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c |
| 598 | #define OMAP4430_PRM_VOLTSETUP_MPU_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x002c) | 655 | #define OMAP4430_PRM_VOLTSETUP_MPU_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x002c) |
| 599 | #define OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET 0x0030 | 656 | #define OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET 0x0030 |
| 600 | #define OMAP4430_PRM_VOLTSETUP_IVA_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0030) | 657 | #define OMAP4430_PRM_VOLTSETUP_IVA_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0030) |
| 601 | #define OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034 | 658 | #define OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034 |
| 602 | #define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0034) | 659 | #define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0034) |
| 603 | #define OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038 | 660 | #define OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038 |
| 604 | #define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0038) | 661 | #define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0038) |
| 605 | #define OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET 0x003c | 662 | #define OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET 0x003c |
| 606 | #define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x003c) | 663 | #define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x003c) |
| 607 | #define OMAP4_PRM_VP_CORE_CONFIG_OFFSET 0x0040 | 664 | #define OMAP4_PRM_VP_CORE_CONFIG_OFFSET 0x0040 |
| 608 | #define OMAP4430_PRM_VP_CORE_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0040) | 665 | #define OMAP4430_PRM_VP_CORE_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0040) |
| 609 | #define OMAP4_PRM_VP_CORE_STATUS_OFFSET 0x0044 | 666 | #define OMAP4_PRM_VP_CORE_STATUS_OFFSET 0x0044 |
| 610 | #define OMAP4430_PRM_VP_CORE_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0044) | 667 | #define OMAP4430_PRM_VP_CORE_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0044) |
| 611 | #define OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET 0x0048 | 668 | #define OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET 0x0048 |
| 612 | #define OMAP4430_PRM_VP_CORE_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0048) | 669 | #define OMAP4430_PRM_VP_CORE_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0048) |
| 613 | #define OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET 0x004c | 670 | #define OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET 0x004c |
| 614 | #define OMAP4430_PRM_VP_CORE_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x004c) | 671 | #define OMAP4430_PRM_VP_CORE_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x004c) |
| 615 | #define OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET 0x0050 | 672 | #define OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET 0x0050 |
| 616 | #define OMAP4430_PRM_VP_CORE_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0050) | 673 | #define OMAP4430_PRM_VP_CORE_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0050) |
| 617 | #define OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET 0x0054 | 674 | #define OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET 0x0054 |
| 618 | #define OMAP4430_PRM_VP_CORE_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0054) | 675 | #define OMAP4430_PRM_VP_CORE_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0054) |
| 619 | #define OMAP4_PRM_VP_MPU_CONFIG_OFFSET 0x0058 | 676 | #define OMAP4_PRM_VP_MPU_CONFIG_OFFSET 0x0058 |
| 620 | #define OMAP4430_PRM_VP_MPU_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0058) | 677 | #define OMAP4430_PRM_VP_MPU_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0058) |
| 621 | #define OMAP4_PRM_VP_MPU_STATUS_OFFSET 0x005c | 678 | #define OMAP4_PRM_VP_MPU_STATUS_OFFSET 0x005c |
| 622 | #define OMAP4430_PRM_VP_MPU_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x005c) | 679 | #define OMAP4430_PRM_VP_MPU_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x005c) |
| 623 | #define OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET 0x0060 | 680 | #define OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET 0x0060 |
| 624 | #define OMAP4430_PRM_VP_MPU_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0060) | 681 | #define OMAP4430_PRM_VP_MPU_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0060) |
| 625 | #define OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET 0x0064 | 682 | #define OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET 0x0064 |
| 626 | #define OMAP4430_PRM_VP_MPU_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0064) | 683 | #define OMAP4430_PRM_VP_MPU_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0064) |
| 627 | #define OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET 0x0068 | 684 | #define OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET 0x0068 |
| 628 | #define OMAP4430_PRM_VP_MPU_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0068) | 685 | #define OMAP4430_PRM_VP_MPU_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0068) |
| 629 | #define OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET 0x006c | 686 | #define OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET 0x006c |
| 630 | #define OMAP4430_PRM_VP_MPU_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x006c) | 687 | #define OMAP4430_PRM_VP_MPU_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x006c) |
| 631 | #define OMAP4_PRM_VP_IVA_CONFIG_OFFSET 0x0070 | 688 | #define OMAP4_PRM_VP_IVA_CONFIG_OFFSET 0x0070 |
| 632 | #define OMAP4430_PRM_VP_IVA_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0070) | 689 | #define OMAP4430_PRM_VP_IVA_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0070) |
| 633 | #define OMAP4_PRM_VP_IVA_STATUS_OFFSET 0x0074 | 690 | #define OMAP4_PRM_VP_IVA_STATUS_OFFSET 0x0074 |
| 634 | #define OMAP4430_PRM_VP_IVA_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0074) | 691 | #define OMAP4430_PRM_VP_IVA_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0074) |
| 635 | #define OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET 0x0078 | 692 | #define OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET 0x0078 |
| 636 | #define OMAP4430_PRM_VP_IVA_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0078) | 693 | #define OMAP4430_PRM_VP_IVA_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0078) |
| 637 | #define OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET 0x007c | 694 | #define OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET 0x007c |
| 638 | #define OMAP4430_PRM_VP_IVA_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x007c) | 695 | #define OMAP4430_PRM_VP_IVA_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x007c) |
| 639 | #define OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET 0x0080 | 696 | #define OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET 0x0080 |
| 640 | #define OMAP4430_PRM_VP_IVA_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0080) | 697 | #define OMAP4430_PRM_VP_IVA_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0080) |
| 641 | #define OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET 0x0084 | 698 | #define OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET 0x0084 |
| 642 | #define OMAP4430_PRM_VP_IVA_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0084) | 699 | #define OMAP4430_PRM_VP_IVA_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0084) |
| 643 | #define OMAP4_PRM_VC_SMPS_SA_OFFSET 0x0088 | 700 | #define OMAP4_PRM_VC_SMPS_SA_OFFSET 0x0088 |
| 644 | #define OMAP4430_PRM_VC_SMPS_SA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0088) | 701 | #define OMAP4430_PRM_VC_SMPS_SA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0088) |
| 645 | #define OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET 0x008c | 702 | #define OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET 0x008c |
| 646 | #define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x008c) | 703 | #define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x008c) |
| 647 | #define OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET 0x0090 | 704 | #define OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET 0x0090 |
| 648 | #define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0090) | 705 | #define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0090) |
| 649 | #define OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET 0x0094 | 706 | #define OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET 0x0094 |
| 650 | #define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0094) | 707 | #define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0094) |
| 651 | #define OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET 0x0098 | 708 | #define OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET 0x0098 |
| 652 | #define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0098) | 709 | #define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0098) |
| 653 | #define OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET 0x009c | 710 | #define OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET 0x009c |
| 654 | #define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x009c) | 711 | #define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x009c) |
| 655 | #define OMAP4_PRM_VC_VAL_BYPASS_OFFSET 0x00a0 | 712 | #define OMAP4_PRM_VC_VAL_BYPASS_OFFSET 0x00a0 |
| 656 | #define OMAP4430_PRM_VC_VAL_BYPASS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a0) | 713 | #define OMAP4430_PRM_VC_VAL_BYPASS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a0) |
| 657 | #define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET 0x00a4 | 714 | #define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET 0x00a4 |
| 658 | #define OMAP4430_PRM_VC_CFG_CHANNEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a4) | 715 | #define OMAP4430_PRM_VC_CFG_CHANNEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a4) |
| 659 | #define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET 0x00a8 | 716 | #define OMAP4_PRM_VC_CFG_I2C_INSTE_OFFSET 0x00a8 |
| 660 | #define OMAP4430_PRM_VC_CFG_I2C_MODE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a8) | 717 | #define OMAP4430_PRM_VC_CFG_I2C_INSTE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8) |
| 661 | #define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET 0x00ac | 718 | #define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET 0x00ac |
| 662 | #define OMAP4430_PRM_VC_CFG_I2C_CLK OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ac) | 719 | #define OMAP4430_PRM_VC_CFG_I2C_CLK OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ac) |
| 663 | #define OMAP4_PRM_SRAM_COUNT_OFFSET 0x00b0 | 720 | #define OMAP4_PRM_SRAM_COUNT_OFFSET 0x00b0 |
| 664 | #define OMAP4430_PRM_SRAM_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b0) | 721 | #define OMAP4430_PRM_SRAM_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b0) |
| 665 | #define OMAP4_PRM_SRAM_WKUP_SETUP_OFFSET 0x00b4 | 722 | #define OMAP4_PRM_SRAM_WKUP_SETUP_OFFSET 0x00b4 |
| 666 | #define OMAP4430_PRM_SRAM_WKUP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b4) | 723 | #define OMAP4430_PRM_SRAM_WKUP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b4) |
| 667 | #define OMAP4_PRM_LDO_SRAM_CORE_SETUP_OFFSET 0x00b8 | 724 | #define OMAP4_PRM_LDO_SRAM_CORE_SETUP_OFFSET 0x00b8 |
| 668 | #define OMAP4430_PRM_LDO_SRAM_CORE_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b8) | 725 | #define OMAP4430_PRM_LDO_SRAM_CORE_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b8) |
| 669 | #define OMAP4_PRM_LDO_SRAM_CORE_CTRL_OFFSET 0x00bc | 726 | #define OMAP4_PRM_LDO_SRAM_CORE_CTRL_OFFSET 0x00bc |
| 670 | #define OMAP4430_PRM_LDO_SRAM_CORE_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00bc) | 727 | #define OMAP4430_PRM_LDO_SRAM_CORE_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00bc) |
| 671 | #define OMAP4_PRM_LDO_SRAM_MPU_SETUP_OFFSET 0x00c0 | 728 | #define OMAP4_PRM_LDO_SRAM_MPU_SETUP_OFFSET 0x00c0 |
| 672 | #define OMAP4430_PRM_LDO_SRAM_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c0) | 729 | #define OMAP4430_PRM_LDO_SRAM_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c0) |
| 673 | #define OMAP4_PRM_LDO_SRAM_MPU_CTRL_OFFSET 0x00c4 | 730 | #define OMAP4_PRM_LDO_SRAM_MPU_CTRL_OFFSET 0x00c4 |
| 674 | #define OMAP4430_PRM_LDO_SRAM_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c4) | 731 | #define OMAP4430_PRM_LDO_SRAM_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c4) |
| 675 | #define OMAP4_PRM_LDO_SRAM_IVA_SETUP_OFFSET 0x00c8 | 732 | #define OMAP4_PRM_LDO_SRAM_IVA_SETUP_OFFSET 0x00c8 |
| 676 | #define OMAP4430_PRM_LDO_SRAM_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c8) | 733 | #define OMAP4430_PRM_LDO_SRAM_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c8) |
| 677 | #define OMAP4_PRM_LDO_SRAM_IVA_CTRL_OFFSET 0x00cc | 734 | #define OMAP4_PRM_LDO_SRAM_IVA_CTRL_OFFSET 0x00cc |
| 678 | #define OMAP4430_PRM_LDO_SRAM_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00cc) | 735 | #define OMAP4430_PRM_LDO_SRAM_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00cc) |
| 679 | #define OMAP4_PRM_LDO_ABB_MPU_SETUP_OFFSET 0x00d0 | 736 | #define OMAP4_PRM_LDO_ABB_MPU_SETUP_OFFSET 0x00d0 |
| 680 | #define OMAP4430_PRM_LDO_ABB_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d0) | 737 | #define OMAP4430_PRM_LDO_ABB_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d0) |
| 681 | #define OMAP4_PRM_LDO_ABB_MPU_CTRL_OFFSET 0x00d4 | 738 | #define OMAP4_PRM_LDO_ABB_MPU_CTRL_OFFSET 0x00d4 |
| 682 | #define OMAP4430_PRM_LDO_ABB_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d4) | 739 | #define OMAP4430_PRM_LDO_ABB_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d4) |
| 683 | #define OMAP4_PRM_LDO_ABB_IVA_SETUP_OFFSET 0x00d8 | 740 | #define OMAP4_PRM_LDO_ABB_IVA_SETUP_OFFSET 0x00d8 |
| 684 | #define OMAP4430_PRM_LDO_ABB_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d8) | 741 | #define OMAP4430_PRM_LDO_ABB_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d8) |
| 685 | #define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET 0x00dc | 742 | #define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET 0x00dc |
| 686 | #define OMAP4430_PRM_LDO_ABB_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00dc) | 743 | #define OMAP4430_PRM_LDO_ABB_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00dc) |
| 687 | #define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET 0x00e0 | 744 | #define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET 0x00e0 |
| 688 | #define OMAP4430_PRM_LDO_BANDGAP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0) | 745 | #define OMAP4430_PRM_LDO_BANDGAP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e0) |
| 689 | #define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET 0x00e4 | 746 | #define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET 0x00e4 |
| 690 | #define OMAP4430_PRM_DEVICE_OFF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e4) | 747 | #define OMAP4430_PRM_DEVICE_OFF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e4) |
| 691 | #define OMAP4_PRM_PHASE1_CNDP_OFFSET 0x00e8 | 748 | #define OMAP4_PRM_PHASE1_CNDP_OFFSET 0x00e8 |
| 692 | #define OMAP4430_PRM_PHASE1_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e8) | 749 | #define OMAP4430_PRM_PHASE1_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e8) |
| 693 | #define OMAP4_PRM_PHASE2A_CNDP_OFFSET 0x00ec | 750 | #define OMAP4_PRM_PHASE2A_CNDP_OFFSET 0x00ec |
| 694 | #define OMAP4430_PRM_PHASE2A_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ec) | 751 | #define OMAP4430_PRM_PHASE2A_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ec) |
| 695 | #define OMAP4_PRM_PHASE2B_CNDP_OFFSET 0x00f0 | 752 | #define OMAP4_PRM_PHASE2B_CNDP_OFFSET 0x00f0 |
| 696 | #define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f0) | 753 | #define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f0) |
| 697 | #define OMAP4_PRM_MODEM_IF_CTRL_OFFSET 0x00f4 | 754 | #define OMAP4_PRM_INSTEM_IF_CTRL_OFFSET 0x00f4 |
| 698 | #define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f4) | 755 | #define OMAP4430_PRM_INSTEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4) |
| 699 | #define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8 | 756 | #define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8 |
| 700 | #define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f8) | 757 | #define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8) |
| 701 | 758 | ||
| 702 | /* | 759 | /* Function prototypes */ |
| 703 | * PRCM_MPU | 760 | # ifndef __ASSEMBLER__ |
| 704 | * | 761 | |
| 705 | * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global) | 762 | extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx); |
| 706 | * point of view the PRCM_MPU is a single entity. It shares the same | 763 | extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx); |
| 707 | * programming model as the global PRCM and thus can be assimilate as two new | 764 | extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); |
| 708 | * MOD inside the PRCM | 765 | extern u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg); |
| 709 | */ | 766 | extern u32 omap4_prm_set_inst_reg_bits(u32 bits, s16 inst, s16 idx); |
| 767 | extern u32 omap4_prm_clear_inst_reg_bits(u32 bits, s16 inst, s16 idx); | ||
| 768 | extern u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask); | ||
| 769 | |||
| 770 | extern int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift); | ||
| 771 | extern int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift); | ||
| 772 | extern int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift); | ||
| 773 | |||
| 774 | extern void omap4_prm_global_warm_sw_reset(void); | ||
| 775 | |||
| 776 | # endif | ||
| 710 | 777 | ||
| 711 | /* PRCM_MPU.OCP_SOCKET_PRCM register offsets */ | ||
| 712 | #define OMAP4_REVISION_PRCM_OFFSET 0x0000 | ||
| 713 | #define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD, 0x0000) | ||
| 714 | |||
| 715 | /* PRCM_MPU.DEVICE_PRM register offsets */ | ||
| 716 | #define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000 | ||
| 717 | #define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0000) | ||
| 718 | #define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004 | ||
| 719 | #define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0004) | ||
| 720 | |||
| 721 | /* PRCM_MPU.CPU0 register offsets */ | ||
| 722 | #define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000 | ||
| 723 | #define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0000) | ||
| 724 | #define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004 | ||
| 725 | #define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0004) | ||
| 726 | #define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008 | ||
| 727 | #define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0008) | ||
| 728 | #define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c | ||
| 729 | #define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x000c) | ||
| 730 | #define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010 | ||
| 731 | #define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0010) | ||
| 732 | #define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014 | ||
| 733 | #define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0014) | ||
| 734 | #define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018 | ||
| 735 | #define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0018) | ||
| 736 | |||
| 737 | /* PRCM_MPU.CPU1 register offsets */ | ||
| 738 | #define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000 | ||
| 739 | #define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0000) | ||
| 740 | #define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004 | ||
| 741 | #define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0004) | ||
| 742 | #define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008 | ||
| 743 | #define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0008) | ||
| 744 | #define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c | ||
| 745 | #define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x000c) | ||
| 746 | #define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010 | ||
| 747 | #define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0010) | ||
| 748 | #define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014 | ||
| 749 | #define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0014) | ||
| 750 | #define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018 | ||
| 751 | #define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0018) | ||
| 752 | #endif | 778 | #endif |
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c new file mode 100644 index 000000000000..a30324297278 --- /dev/null +++ b/arch/arm/mach-omap2/prminst44xx.c | |||
| @@ -0,0 +1,66 @@ | |||
| 1 | /* | ||
| 2 | * OMAP4 PRM instance functions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Nokia Corporation | ||
| 5 | * Paul Walmsley | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/types.h> | ||
| 14 | #include <linux/errno.h> | ||
| 15 | #include <linux/err.h> | ||
| 16 | #include <linux/io.h> | ||
| 17 | |||
| 18 | #include <plat/common.h> | ||
| 19 | |||
| 20 | #include "prm44xx.h" | ||
| 21 | #include "prminst44xx.h" | ||
| 22 | #include "prm-regbits-44xx.h" | ||
| 23 | #include "prcm44xx.h" | ||
| 24 | #include "prcm_mpu44xx.h" | ||
| 25 | |||
| 26 | static u32 _prm_bases[OMAP4_MAX_PRCM_PARTITIONS] = { | ||
| 27 | [OMAP4430_INVALID_PRCM_PARTITION] = 0, | ||
| 28 | [OMAP4430_PRM_PARTITION] = OMAP4430_PRM_BASE, | ||
| 29 | [OMAP4430_CM1_PARTITION] = 0, | ||
| 30 | [OMAP4430_CM2_PARTITION] = 0, | ||
| 31 | [OMAP4430_SCRM_PARTITION] = 0, | ||
| 32 | [OMAP4430_PRCM_MPU_PARTITION] = OMAP4430_PRCM_MPU_BASE, | ||
| 33 | }; | ||
| 34 | |||
| 35 | /* Read a register in a PRM instance */ | ||
| 36 | u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx) | ||
| 37 | { | ||
| 38 | BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || | ||
| 39 | part == OMAP4430_INVALID_PRCM_PARTITION || | ||
| 40 | !_prm_bases[part]); | ||
| 41 | return __raw_readl(OMAP2_L4_IO_ADDRESS(_prm_bases[part] + inst + | ||
| 42 | idx)); | ||
| 43 | } | ||
| 44 | |||
| 45 | /* Write into a register in a PRM instance */ | ||
| 46 | void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx) | ||
| 47 | { | ||
| 48 | BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS || | ||
| 49 | part == OMAP4430_INVALID_PRCM_PARTITION || | ||
| 50 | !_prm_bases[part]); | ||
| 51 | __raw_writel(val, OMAP2_L4_IO_ADDRESS(_prm_bases[part] + inst + idx)); | ||
| 52 | } | ||
| 53 | |||
| 54 | /* Read-modify-write a register in PRM. Caller must lock */ | ||
| 55 | u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst, | ||
| 56 | s16 idx) | ||
| 57 | { | ||
| 58 | u32 v; | ||
| 59 | |||
| 60 | v = omap4_prminst_read_inst_reg(part, inst, idx); | ||
| 61 | v &= ~mask; | ||
| 62 | v |= bits; | ||
| 63 | omap4_prminst_write_inst_reg(v, part, inst, idx); | ||
| 64 | |||
| 65 | return v; | ||
| 66 | } | ||
diff --git a/arch/arm/mach-omap2/prminst44xx.h b/arch/arm/mach-omap2/prminst44xx.h new file mode 100644 index 000000000000..02dd66ddda8b --- /dev/null +++ b/arch/arm/mach-omap2/prminst44xx.h | |||
| @@ -0,0 +1,25 @@ | |||
| 1 | /* | ||
| 2 | * OMAP4 Power/Reset Management (PRM) function prototypes | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Nokia Corporation | ||
| 5 | * Paul Walmsley | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #ifndef __ARCH_ASM_MACH_OMAP2_PRMINST44XX_H | ||
| 12 | #define __ARCH_ASM_MACH_OMAP2_PRMINST44XX_H | ||
| 13 | |||
| 14 | /* | ||
| 15 | * In an ideal world, we would not export these low-level functions, | ||
| 16 | * but this will probably take some time to fix properly | ||
| 17 | */ | ||
| 18 | extern u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx); | ||
| 19 | extern void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx); | ||
| 20 | extern u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, | ||
| 21 | s16 inst, s16 idx); | ||
| 22 | |||
| 23 | extern void omap4_prm_global_warm_sw_reset(void); | ||
| 24 | |||
| 25 | #endif | ||
diff --git a/arch/arm/mach-omap2/scrm44xx.h b/arch/arm/mach-omap2/scrm44xx.h new file mode 100644 index 000000000000..701bf2d32949 --- /dev/null +++ b/arch/arm/mach-omap2/scrm44xx.h | |||
| @@ -0,0 +1,175 @@ | |||
| 1 | /* | ||
| 2 | * OMAP44xx SCRM registers and bitfields | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Texas Instruments, Inc. | ||
| 5 | * | ||
| 6 | * Benoit Cousson (b-cousson@ti.com) | ||
| 7 | * | ||
| 8 | * This file is automatically generated from the OMAP hardware databases. | ||
| 9 | * We respectfully ask that any modifications to this file be coordinated | ||
| 10 | * with the public linux-omap@vger.kernel.org mailing list and the | ||
| 11 | * authors above to ensure that the autogeneration scripts are kept | ||
| 12 | * up-to-date with the file contents. | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License version 2 as | ||
| 16 | * published by the Free Software Foundation. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef __ARCH_ARM_MACH_OMAP2_SCRM_44XX_H | ||
| 20 | #define __ARCH_ARM_MACH_OMAP2_SCRM_44XX_H | ||
| 21 | |||
| 22 | #define OMAP4_SCRM_BASE 0x4a30a000 | ||
| 23 | |||
| 24 | #define OMAP44XX_SCRM_REGADDR(reg) \ | ||
| 25 | OMAP2_L4_IO_ADDRESS(OMAP4_SCRM_BASE + (reg)) | ||
| 26 | |||
| 27 | /* Registers offset */ | ||
| 28 | #define OMAP4_SCRM_REVISION_SCRM_OFFSET 0x0000 | ||
| 29 | #define OMAP4_SCRM_REVISION_SCRM OMAP44XX_SCRM_REGADDR(0x0000) | ||
| 30 | #define OMAP4_SCRM_CLKSETUPTIME_OFFSET 0x0100 | ||
| 31 | #define OMAP4_SCRM_CLKSETUPTIME OMAP44XX_SCRM_REGADDR(0x0100) | ||
| 32 | #define OMAP4_SCRM_PMICSETUPTIME_OFFSET 0x0104 | ||
| 33 | #define OMAP4_SCRM_PMICSETUPTIME OMAP44XX_SCRM_REGADDR(0x0104) | ||
| 34 | #define OMAP4_SCRM_ALTCLKSRC_OFFSET 0x0110 | ||
| 35 | #define OMAP4_SCRM_ALTCLKSRC OMAP44XX_SCRM_REGADDR(0x0110) | ||
| 36 | #define OMAP4_SCRM_MODEMCLKM_OFFSET 0x0118 | ||
| 37 | #define OMAP4_SCRM_MODEMCLKM OMAP44XX_SCRM_REGADDR(0x0118) | ||
| 38 | #define OMAP4_SCRM_D2DCLKM_OFFSET 0x011c | ||
| 39 | #define OMAP4_SCRM_D2DCLKM OMAP44XX_SCRM_REGADDR(0x011c) | ||
| 40 | #define OMAP4_SCRM_EXTCLKREQ_OFFSET 0x0200 | ||
| 41 | #define OMAP4_SCRM_EXTCLKREQ OMAP44XX_SCRM_REGADDR(0x0200) | ||
| 42 | #define OMAP4_SCRM_ACCCLKREQ_OFFSET 0x0204 | ||
| 43 | #define OMAP4_SCRM_ACCCLKREQ OMAP44XX_SCRM_REGADDR(0x0204) | ||
| 44 | #define OMAP4_SCRM_PWRREQ_OFFSET 0x0208 | ||
| 45 | #define OMAP4_SCRM_PWRREQ OMAP44XX_SCRM_REGADDR(0x0208) | ||
| 46 | #define OMAP4_SCRM_AUXCLKREQ0_OFFSET 0x0210 | ||
| 47 | #define OMAP4_SCRM_AUXCLKREQ0 OMAP44XX_SCRM_REGADDR(0x0210) | ||
| 48 | #define OMAP4_SCRM_AUXCLKREQ1_OFFSET 0x0214 | ||
| 49 | #define OMAP4_SCRM_AUXCLKREQ1 OMAP44XX_SCRM_REGADDR(0x0214) | ||
| 50 | #define OMAP4_SCRM_AUXCLKREQ2_OFFSET 0x0218 | ||
| 51 | #define OMAP4_SCRM_AUXCLKREQ2 OMAP44XX_SCRM_REGADDR(0x0218) | ||
| 52 | #define OMAP4_SCRM_AUXCLKREQ3_OFFSET 0x021c | ||
| 53 | #define OMAP4_SCRM_AUXCLKREQ3 OMAP44XX_SCRM_REGADDR(0x021c) | ||
| 54 | #define OMAP4_SCRM_AUXCLKREQ4_OFFSET 0x0220 | ||
| 55 | #define OMAP4_SCRM_AUXCLKREQ4 OMAP44XX_SCRM_REGADDR(0x0220) | ||
| 56 | #define OMAP4_SCRM_AUXCLKREQ5_OFFSET 0x0224 | ||
| 57 | #define OMAP4_SCRM_AUXCLKREQ5 OMAP44XX_SCRM_REGADDR(0x0224) | ||
| 58 | #define OMAP4_SCRM_D2DCLKREQ_OFFSET 0x0234 | ||
| 59 | #define OMAP4_SCRM_D2DCLKREQ OMAP44XX_SCRM_REGADDR(0x0234) | ||
| 60 | #define OMAP4_SCRM_AUXCLK0_OFFSET 0x0310 | ||
| 61 | #define OMAP4_SCRM_AUXCLK0 OMAP44XX_SCRM_REGADDR(0x0310) | ||
| 62 | #define OMAP4_SCRM_AUXCLK1_OFFSET 0x0314 | ||
| 63 | #define OMAP4_SCRM_AUXCLK1 OMAP44XX_SCRM_REGADDR(0x0314) | ||
| 64 | #define OMAP4_SCRM_AUXCLK2_OFFSET 0x0318 | ||
| 65 | #define OMAP4_SCRM_AUXCLK2 OMAP44XX_SCRM_REGADDR(0x0318) | ||
| 66 | #define OMAP4_SCRM_AUXCLK3_OFFSET 0x031c | ||
| 67 | #define OMAP4_SCRM_AUXCLK3 OMAP44XX_SCRM_REGADDR(0x031c) | ||
| 68 | #define OMAP4_SCRM_AUXCLK4_OFFSET 0x0320 | ||
| 69 | #define OMAP4_SCRM_AUXCLK4 OMAP44XX_SCRM_REGADDR(0x0320) | ||
| 70 | #define OMAP4_SCRM_AUXCLK5_OFFSET 0x0324 | ||
| 71 | #define OMAP4_SCRM_AUXCLK5 OMAP44XX_SCRM_REGADDR(0x0324) | ||
| 72 | #define OMAP4_SCRM_RSTTIME_OFFSET 0x0400 | ||
| 73 | #define OMAP4_SCRM_RSTTIME OMAP44XX_SCRM_REGADDR(0x0400) | ||
| 74 | #define OMAP4_SCRM_MODEMRSTCTRL_OFFSET 0x0418 | ||
| 75 | #define OMAP4_SCRM_MODEMRSTCTRL OMAP44XX_SCRM_REGADDR(0x0418) | ||
| 76 | #define OMAP4_SCRM_D2DRSTCTRL_OFFSET 0x041c | ||
| 77 | #define OMAP4_SCRM_D2DRSTCTRL OMAP44XX_SCRM_REGADDR(0x041c) | ||
| 78 | #define OMAP4_SCRM_EXTPWRONRSTCTRL_OFFSET 0x0420 | ||
| 79 | #define OMAP4_SCRM_EXTPWRONRSTCTRL OMAP44XX_SCRM_REGADDR(0x0420) | ||
| 80 | #define OMAP4_SCRM_EXTWARMRSTST_OFFSET 0x0510 | ||
| 81 | #define OMAP4_SCRM_EXTWARMRSTST OMAP44XX_SCRM_REGADDR(0x0510) | ||
| 82 | #define OMAP4_SCRM_APEWARMRSTST_OFFSET 0x0514 | ||
| 83 | #define OMAP4_SCRM_APEWARMRSTST OMAP44XX_SCRM_REGADDR(0x0514) | ||
| 84 | #define OMAP4_SCRM_MODEMWARMRSTST_OFFSET 0x0518 | ||
| 85 | #define OMAP4_SCRM_MODEMWARMRSTST OMAP44XX_SCRM_REGADDR(0x0518) | ||
| 86 | #define OMAP4_SCRM_D2DWARMRSTST_OFFSET 0x051c | ||
| 87 | #define OMAP4_SCRM_D2DWARMRSTST OMAP44XX_SCRM_REGADDR(0x051c) | ||
| 88 | |||
| 89 | /* Registers shifts and masks */ | ||
| 90 | |||
| 91 | /* REVISION_SCRM */ | ||
| 92 | #define OMAP4_REV_SHIFT 0 | ||
| 93 | #define OMAP4_REV_MASK (0xff << 0) | ||
| 94 | |||
| 95 | /* CLKSETUPTIME */ | ||
| 96 | #define OMAP4_DOWNTIME_SHIFT 16 | ||
| 97 | #define OMAP4_DOWNTIME_MASK (0x3f << 16) | ||
| 98 | #define OMAP4_SETUPTIME_SHIFT 0 | ||
| 99 | #define OMAP4_SETUPTIME_MASK (0xfff << 0) | ||
| 100 | |||
| 101 | /* PMICSETUPTIME */ | ||
| 102 | #define OMAP4_WAKEUPTIME_SHIFT 16 | ||
| 103 | #define OMAP4_WAKEUPTIME_MASK (0x3f << 16) | ||
| 104 | #define OMAP4_SLEEPTIME_SHIFT 0 | ||
| 105 | #define OMAP4_SLEEPTIME_MASK (0x3f << 0) | ||
| 106 | |||
| 107 | /* ALTCLKSRC */ | ||
| 108 | #define OMAP4_ENABLE_EXT_SHIFT 3 | ||
| 109 | #define OMAP4_ENABLE_EXT_MASK (1 << 3) | ||
| 110 | #define OMAP4_ENABLE_INT_SHIFT 2 | ||
| 111 | #define OMAP4_ENABLE_INT_MASK (1 << 2) | ||
| 112 | #define OMAP4_ALTCLKSRC_MODE_SHIFT 0 | ||
| 113 | #define OMAP4_ALTCLKSRC_MODE_MASK (0x3 << 0) | ||
| 114 | |||
| 115 | /* MODEMCLKM */ | ||
| 116 | #define OMAP4_CLK_32KHZ_SHIFT 0 | ||
| 117 | #define OMAP4_CLK_32KHZ_MASK (1 << 0) | ||
| 118 | |||
| 119 | /* D2DCLKM */ | ||
| 120 | #define OMAP4_SYSCLK_SHIFT 1 | ||
| 121 | #define OMAP4_SYSCLK_MASK (1 << 1) | ||
| 122 | |||
| 123 | /* EXTCLKREQ */ | ||
| 124 | #define OMAP4_POLARITY_SHIFT 0 | ||
| 125 | #define OMAP4_POLARITY_MASK (1 << 0) | ||
| 126 | |||
| 127 | /* AUXCLKREQ0 */ | ||
| 128 | #define OMAP4_MAPPING_SHIFT 2 | ||
| 129 | #define OMAP4_MAPPING_MASK (0x7 << 2) | ||
| 130 | #define OMAP4_ACCURACY_SHIFT 1 | ||
| 131 | #define OMAP4_ACCURACY_MASK (1 << 1) | ||
| 132 | |||
| 133 | /* AUXCLK0 */ | ||
| 134 | #define OMAP4_CLKDIV_SHIFT 16 | ||
| 135 | #define OMAP4_CLKDIV_MASK (0xf << 16) | ||
| 136 | #define OMAP4_DISABLECLK_SHIFT 9 | ||
| 137 | #define OMAP4_DISABLECLK_MASK (1 << 9) | ||
| 138 | #define OMAP4_ENABLE_SHIFT 8 | ||
| 139 | #define OMAP4_ENABLE_MASK (1 << 8) | ||
| 140 | #define OMAP4_SRCSELECT_SHIFT 1 | ||
| 141 | #define OMAP4_SRCSELECT_MASK (0x3 << 1) | ||
| 142 | |||
| 143 | /* RSTTIME */ | ||
| 144 | #define OMAP4_RSTTIME_SHIFT 0 | ||
| 145 | #define OMAP4_RSTTIME_MASK (0xf << 0) | ||
| 146 | |||
| 147 | /* MODEMRSTCTRL */ | ||
| 148 | #define OMAP4_WARMRST_SHIFT 1 | ||
| 149 | #define OMAP4_WARMRST_MASK (1 << 1) | ||
| 150 | #define OMAP4_COLDRST_SHIFT 0 | ||
| 151 | #define OMAP4_COLDRST_MASK (1 << 0) | ||
| 152 | |||
| 153 | /* EXTPWRONRSTCTRL */ | ||
| 154 | #define OMAP4_PWRONRST_SHIFT 1 | ||
| 155 | #define OMAP4_PWRONRST_MASK (1 << 1) | ||
| 156 | #define OMAP4_ENABLE_EXTPWRONRSTCTRL_SHIFT 0 | ||
| 157 | #define OMAP4_ENABLE_EXTPWRONRSTCTRL_MASK (1 << 0) | ||
| 158 | |||
| 159 | /* EXTWARMRSTST */ | ||
| 160 | #define OMAP4_EXTWARMRSTST_SHIFT 0 | ||
| 161 | #define OMAP4_EXTWARMRSTST_MASK (1 << 0) | ||
| 162 | |||
| 163 | /* APEWARMRSTST */ | ||
| 164 | #define OMAP4_APEWARMRSTST_SHIFT 1 | ||
| 165 | #define OMAP4_APEWARMRSTST_MASK (1 << 1) | ||
| 166 | |||
| 167 | /* MODEMWARMRSTST */ | ||
| 168 | #define OMAP4_MODEMWARMRSTST_SHIFT 2 | ||
| 169 | #define OMAP4_MODEMWARMRSTST_MASK (1 << 2) | ||
| 170 | |||
| 171 | /* D2DWARMRSTST */ | ||
| 172 | #define OMAP4_D2DWARMRSTST_SHIFT 3 | ||
| 173 | #define OMAP4_D2DWARMRSTST_MASK (1 << 3) | ||
| 174 | |||
| 175 | #endif | ||
diff --git a/arch/arm/mach-omap2/board-rx51-sdram.c b/arch/arm/mach-omap2/sdram-nokia.c index a43b2c5c838b..14caa228bc0d 100644 --- a/arch/arm/mach-omap2/board-rx51-sdram.c +++ b/arch/arm/mach-omap2/sdram-nokia.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * SDRC register values for RX51 | 2 | * SDRC register values for Nokia boards |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2008 Nokia Corporation | 4 | * Copyright (C) 2008, 2010 Nokia Corporation |
| 5 | * | 5 | * |
| 6 | * Lauri Leukkunen <lauri.leukkunen@nokia.com> | 6 | * Lauri Leukkunen <lauri.leukkunen@nokia.com> |
| 7 | * | 7 | * |
| @@ -22,6 +22,7 @@ | |||
| 22 | #include <plat/clock.h> | 22 | #include <plat/clock.h> |
| 23 | #include <plat/sdrc.h> | 23 | #include <plat/sdrc.h> |
| 24 | 24 | ||
| 25 | #include "sdram-nokia.h" | ||
| 25 | 26 | ||
| 26 | /* In picoseconds, except for tREF (ns), tXP, tCKE, tWTR (clks) */ | 27 | /* In picoseconds, except for tREF (ns), tXP, tCKE, tWTR (clks) */ |
| 27 | struct sdram_timings { | 28 | struct sdram_timings { |
| @@ -43,9 +44,28 @@ struct sdram_timings { | |||
| 43 | u32 tWTR; | 44 | u32 tWTR; |
| 44 | }; | 45 | }; |
| 45 | 46 | ||
| 46 | static struct omap_sdrc_params rx51_sdrc_params[4]; | 47 | static const struct sdram_timings nokia_97dot6mhz_timings[] = { |
| 48 | { | ||
| 49 | .casl = 3, | ||
| 50 | .tDAL = 30725, | ||
| 51 | .tDPL = 15362, | ||
| 52 | .tRRD = 10241, | ||
| 53 | .tRCD = 20483, | ||
| 54 | .tRP = 15362, | ||
| 55 | .tRAS = 40967, | ||
| 56 | .tRC = 56330, | ||
| 57 | .tRFC = 138266, | ||
| 58 | .tXSR = 204839, | ||
| 59 | |||
| 60 | .tREF = 7798, | ||
| 61 | |||
| 62 | .tXP = 2, | ||
| 63 | .tCKE = 4, | ||
| 64 | .tWTR = 2, | ||
| 65 | }, | ||
| 66 | }; | ||
| 47 | 67 | ||
| 48 | static const struct sdram_timings rx51_timings[] = { | 68 | static const struct sdram_timings nokia_166mhz_timings[] = { |
| 49 | { | 69 | { |
| 50 | .casl = 3, | 70 | .casl = 3, |
| 51 | .tDAL = 33000, | 71 | .tDAL = 33000, |
| @@ -66,6 +86,38 @@ static const struct sdram_timings rx51_timings[] = { | |||
| 66 | }, | 86 | }, |
| 67 | }; | 87 | }; |
| 68 | 88 | ||
| 89 | static const struct sdram_timings nokia_195dot2mhz_timings[] = { | ||
| 90 | { | ||
| 91 | .casl = 3, | ||
| 92 | .tDAL = 30725, | ||
| 93 | .tDPL = 15362, | ||
| 94 | .tRRD = 10241, | ||
| 95 | .tRCD = 20483, | ||
| 96 | .tRP = 15362, | ||
| 97 | .tRAS = 40967, | ||
| 98 | .tRC = 56330, | ||
| 99 | .tRFC = 138266, | ||
| 100 | .tXSR = 204839, | ||
| 101 | |||
| 102 | .tREF = 7752, | ||
| 103 | |||
| 104 | .tXP = 2, | ||
| 105 | .tCKE = 4, | ||
| 106 | .tWTR = 2, | ||
| 107 | }, | ||
| 108 | }; | ||
| 109 | |||
| 110 | static const struct { | ||
| 111 | long rate; | ||
| 112 | struct sdram_timings const *data; | ||
| 113 | } nokia_timings[] = { | ||
| 114 | { 83000000, nokia_166mhz_timings }, | ||
| 115 | { 97600000, nokia_97dot6mhz_timings }, | ||
| 116 | { 166000000, nokia_166mhz_timings }, | ||
| 117 | { 195200000, nokia_195dot2mhz_timings }, | ||
| 118 | }; | ||
| 119 | static struct omap_sdrc_params nokia_sdrc_params[ARRAY_SIZE(nokia_timings) + 1]; | ||
| 120 | |||
| 69 | static unsigned long sdrc_get_fclk_period(long rate) | 121 | static unsigned long sdrc_get_fclk_period(long rate) |
| 70 | { | 122 | { |
| 71 | /* In picoseconds */ | 123 | /* In picoseconds */ |
| @@ -110,12 +162,12 @@ static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit, | |||
| 110 | #ifdef DEBUG | 162 | #ifdef DEBUG |
| 111 | #define SDRC_SET_ONE(reg, st, end, field, rate) \ | 163 | #define SDRC_SET_ONE(reg, st, end, field, rate) \ |
| 112 | if (set_sdrc_timing_regval((reg), (st), (end), \ | 164 | if (set_sdrc_timing_regval((reg), (st), (end), \ |
| 113 | rx51_timings->field, (rate), #field) < 0) \ | 165 | memory_timings->field, (rate), #field) < 0) \ |
| 114 | err = -1; | 166 | err = -1; |
| 115 | #else | 167 | #else |
| 116 | #define SDRC_SET_ONE(reg, st, end, field, rate) \ | 168 | #define SDRC_SET_ONE(reg, st, end, field, rate) \ |
| 117 | if (set_sdrc_timing_regval((reg), (st), (end), \ | 169 | if (set_sdrc_timing_regval((reg), (st), (end), \ |
| 118 | rx51_timings->field) < 0) \ | 170 | memory_timings->field) < 0) \ |
| 119 | err = -1; | 171 | err = -1; |
| 120 | #endif | 172 | #endif |
| 121 | 173 | ||
| @@ -148,18 +200,19 @@ static int set_sdrc_timing_regval_ps(u32 *regval, int st_bit, int end_bit, | |||
| 148 | #ifdef DEBUG | 200 | #ifdef DEBUG |
| 149 | #define SDRC_SET_ONE_PS(reg, st, end, field, rate) \ | 201 | #define SDRC_SET_ONE_PS(reg, st, end, field, rate) \ |
| 150 | if (set_sdrc_timing_regval_ps((reg), (st), (end), \ | 202 | if (set_sdrc_timing_regval_ps((reg), (st), (end), \ |
| 151 | rx51_timings->field, \ | 203 | memory_timings->field, \ |
| 152 | (rate), #field) < 0) \ | 204 | (rate), #field) < 0) \ |
| 153 | err = -1; | 205 | err = -1; |
| 154 | 206 | ||
| 155 | #else | 207 | #else |
| 156 | #define SDRC_SET_ONE_PS(reg, st, end, field, rate) \ | 208 | #define SDRC_SET_ONE_PS(reg, st, end, field, rate) \ |
| 157 | if (set_sdrc_timing_regval_ps((reg), (st), (end), \ | 209 | if (set_sdrc_timing_regval_ps((reg), (st), (end), \ |
| 158 | rx51_timings->field, (rate)) < 0) \ | 210 | memory_timings->field, (rate)) < 0) \ |
| 159 | err = -1; | 211 | err = -1; |
| 160 | #endif | 212 | #endif |
| 161 | 213 | ||
| 162 | static int sdrc_timings(int id, long rate) | 214 | static int sdrc_timings(int id, long rate, |
| 215 | const struct sdram_timings *memory_timings) | ||
| 163 | { | 216 | { |
| 164 | u32 ticks_per_ms; | 217 | u32 ticks_per_ms; |
| 165 | u32 rfr, l; | 218 | u32 rfr, l; |
| @@ -184,7 +237,7 @@ static int sdrc_timings(int id, long rate) | |||
| 184 | SDRC_SET_ONE(&actim_ctrlb, 16, 17, tWTR, l3_rate); | 237 | SDRC_SET_ONE(&actim_ctrlb, 16, 17, tWTR, l3_rate); |
| 185 | 238 | ||
| 186 | ticks_per_ms = l3_rate; | 239 | ticks_per_ms = l3_rate; |
| 187 | rfr = rx51_timings[0].tREF * ticks_per_ms / 1000000; | 240 | rfr = memory_timings[0].tREF * ticks_per_ms / 1000000; |
| 188 | if (rfr > 65535 + 50) | 241 | if (rfr > 65535 + 50) |
| 189 | rfr = 65535; | 242 | rfr = 65535; |
| 190 | else | 243 | else |
| @@ -197,25 +250,30 @@ static int sdrc_timings(int id, long rate) | |||
| 197 | l = rfr << 8; | 250 | l = rfr << 8; |
| 198 | rfr_ctrl = l | 0x1; /* autorefresh, reload counter with 1xARCV */ | 251 | rfr_ctrl = l | 0x1; /* autorefresh, reload counter with 1xARCV */ |
| 199 | 252 | ||
| 200 | rx51_sdrc_params[id].rate = rate; | 253 | nokia_sdrc_params[id].rate = rate; |
| 201 | rx51_sdrc_params[id].actim_ctrla = actim_ctrla; | 254 | nokia_sdrc_params[id].actim_ctrla = actim_ctrla; |
| 202 | rx51_sdrc_params[id].actim_ctrlb = actim_ctrlb; | 255 | nokia_sdrc_params[id].actim_ctrlb = actim_ctrlb; |
| 203 | rx51_sdrc_params[id].rfr_ctrl = rfr_ctrl; | 256 | nokia_sdrc_params[id].rfr_ctrl = rfr_ctrl; |
| 204 | rx51_sdrc_params[id].mr = 0x32; | 257 | nokia_sdrc_params[id].mr = 0x32; |
| 205 | 258 | ||
| 206 | rx51_sdrc_params[id + 1].rate = 0; | 259 | nokia_sdrc_params[id + 1].rate = 0; |
| 207 | 260 | ||
| 208 | return err; | 261 | return err; |
| 209 | } | 262 | } |
| 210 | 263 | ||
| 211 | struct omap_sdrc_params *rx51_get_sdram_timings(void) | 264 | struct omap_sdrc_params *nokia_get_sdram_timings(void) |
| 212 | { | 265 | { |
| 213 | int err; | 266 | int err = 0; |
| 267 | int i; | ||
| 214 | 268 | ||
| 215 | err = sdrc_timings(0, 41500000); | 269 | for (i = 0; i < ARRAY_SIZE(nokia_timings); i++) { |
| 216 | err |= sdrc_timings(1, 83000000); | 270 | err |= sdrc_timings(i, nokia_timings[i].rate, |
| 217 | err |= sdrc_timings(2, 166000000); | 271 | nokia_timings[i].data); |
| 272 | if (err) | ||
| 273 | pr_err("%s: error with rate %ld: %d\n", __func__, | ||
| 274 | nokia_timings[i].rate, err); | ||
| 275 | } | ||
| 218 | 276 | ||
| 219 | return &rx51_sdrc_params[0]; | 277 | return err ? NULL : nokia_sdrc_params; |
| 220 | } | 278 | } |
| 221 | 279 | ||
diff --git a/arch/arm/mach-omap2/sdram-nokia.h b/arch/arm/mach-omap2/sdram-nokia.h new file mode 100644 index 000000000000..ee63da5f8df0 --- /dev/null +++ b/arch/arm/mach-omap2/sdram-nokia.h | |||
| @@ -0,0 +1,12 @@ | |||
| 1 | /* | ||
| 2 | * SDRC register values for Nokia boards | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Nokia | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | struct omap_sdrc_params *nokia_get_sdram_timings(void); | ||
| 12 | |||
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c index 4c65f5628b39..da6f3a63b5d5 100644 --- a/arch/arm/mach-omap2/sdrc.c +++ b/arch/arm/mach-omap2/sdrc.c | |||
| @@ -27,8 +27,6 @@ | |||
| 27 | #include <plat/clock.h> | 27 | #include <plat/clock.h> |
| 28 | #include <plat/sram.h> | 28 | #include <plat/sram.h> |
| 29 | 29 | ||
| 30 | #include "prm.h" | ||
| 31 | |||
| 32 | #include <plat/sdrc.h> | 30 | #include <plat/sdrc.h> |
| 33 | #include "sdrc.h" | 31 | #include "sdrc.h" |
| 34 | 32 | ||
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h index 68f57bb67fc5..b3f83799e6cf 100644 --- a/arch/arm/mach-omap2/sdrc.h +++ b/arch/arm/mach-omap2/sdrc.h | |||
| @@ -74,5 +74,4 @@ static inline u32 sms_read_reg(u16 reg) | |||
| 74 | */ | 74 | */ |
| 75 | #define SDRC_MPURATE_LOOPS 96 | 75 | #define SDRC_MPURATE_LOOPS 96 |
| 76 | 76 | ||
| 77 | |||
| 78 | #endif | 77 | #endif |
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c index 0f4d27aef44d..ccdb010f169d 100644 --- a/arch/arm/mach-omap2/sdrc2xxx.c +++ b/arch/arm/mach-omap2/sdrc2xxx.c | |||
| @@ -28,7 +28,7 @@ | |||
| 28 | #include <plat/clock.h> | 28 | #include <plat/clock.h> |
| 29 | #include <plat/sram.h> | 29 | #include <plat/sram.h> |
| 30 | 30 | ||
| 31 | #include "prm.h" | 31 | #include "prm2xxx_3xxx.h" |
| 32 | #include "clock.h" | 32 | #include "clock.h" |
| 33 | #include <plat/sdrc.h> | 33 | #include <plat/sdrc.h> |
| 34 | #include "sdrc.h" | 34 | #include "sdrc.h" |
| @@ -99,6 +99,10 @@ u32 omap2xxx_sdrc_reprogram(u32 level, u32 force) | |||
| 99 | m_type = omap2xxx_sdrc_get_type(); | 99 | m_type = omap2xxx_sdrc_get_type(); |
| 100 | 100 | ||
| 101 | local_irq_save(flags); | 101 | local_irq_save(flags); |
| 102 | /* | ||
| 103 | * XXX These calls should be abstracted out through a | ||
| 104 | * prm2xxx.c function | ||
| 105 | */ | ||
| 102 | if (cpu_is_omap2420()) | 106 | if (cpu_is_omap2420()) |
| 103 | __raw_writel(0xffff, OMAP2420_PRCM_VOLTSETUP); | 107 | __raw_writel(0xffff, OMAP2420_PRCM_VOLTSETUP); |
| 104 | else | 108 | else |
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index d17960a1be25..c64578853a8d 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c | |||
| @@ -40,11 +40,12 @@ | |||
| 40 | #include <plat/omap_hwmod.h> | 40 | #include <plat/omap_hwmod.h> |
| 41 | #include <plat/omap_device.h> | 41 | #include <plat/omap_device.h> |
| 42 | 42 | ||
| 43 | #include "prm.h" | 43 | #include "prm2xxx_3xxx.h" |
| 44 | #include "pm.h" | 44 | #include "pm.h" |
| 45 | #include "cm.h" | 45 | #include "cm2xxx_3xxx.h" |
| 46 | #include "prm-regbits-34xx.h" | 46 | #include "prm-regbits-34xx.h" |
| 47 | #include "control.h" | 47 | #include "control.h" |
| 48 | #include "mux.h" | ||
| 48 | 49 | ||
| 49 | #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52 | 50 | #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52 |
| 50 | #define UART_OMAP_WER 0x17 /* Wake-up enable register */ | 51 | #define UART_OMAP_WER 0x17 /* Wake-up enable register */ |
| @@ -106,21 +107,16 @@ struct omap_uart_state { | |||
| 106 | static LIST_HEAD(uart_list); | 107 | static LIST_HEAD(uart_list); |
| 107 | static u8 num_uarts; | 108 | static u8 num_uarts; |
| 108 | 109 | ||
| 109 | /* | ||
| 110 | * Since these idle/enable hooks are used in the idle path itself | ||
| 111 | * which has interrupts disabled, use the non-locking versions of | ||
| 112 | * the hwmod enable/disable functions. | ||
| 113 | */ | ||
| 114 | static int uart_idle_hwmod(struct omap_device *od) | 110 | static int uart_idle_hwmod(struct omap_device *od) |
| 115 | { | 111 | { |
| 116 | _omap_hwmod_idle(od->hwmods[0]); | 112 | omap_hwmod_idle(od->hwmods[0]); |
| 117 | 113 | ||
| 118 | return 0; | 114 | return 0; |
| 119 | } | 115 | } |
| 120 | 116 | ||
| 121 | static int uart_enable_hwmod(struct omap_device *od) | 117 | static int uart_enable_hwmod(struct omap_device *od) |
| 122 | { | 118 | { |
| 123 | _omap_hwmod_enable(od->hwmods[0]); | 119 | omap_hwmod_enable(od->hwmods[0]); |
| 124 | 120 | ||
| 125 | return 0; | 121 | return 0; |
| 126 | } | 122 | } |
| @@ -169,9 +165,9 @@ static inline void serial_write_reg(struct omap_uart_state *uart, int offset, | |||
| 169 | 165 | ||
| 170 | static inline void __init omap_uart_reset(struct omap_uart_state *uart) | 166 | static inline void __init omap_uart_reset(struct omap_uart_state *uart) |
| 171 | { | 167 | { |
| 172 | serial_write_reg(uart, UART_OMAP_MDR1, 0x07); | 168 | serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); |
| 173 | serial_write_reg(uart, UART_OMAP_SCR, 0x08); | 169 | serial_write_reg(uart, UART_OMAP_SCR, 0x08); |
| 174 | serial_write_reg(uart, UART_OMAP_MDR1, 0x00); | 170 | serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE); |
| 175 | } | 171 | } |
| 176 | 172 | ||
| 177 | #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) | 173 | #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) |
| @@ -219,7 +215,7 @@ static void omap_uart_save_context(struct omap_uart_state *uart) | |||
| 219 | return; | 215 | return; |
| 220 | 216 | ||
| 221 | lcr = serial_read_reg(uart, UART_LCR); | 217 | lcr = serial_read_reg(uart, UART_LCR); |
| 222 | serial_write_reg(uart, UART_LCR, 0xBF); | 218 | serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); |
| 223 | uart->dll = serial_read_reg(uart, UART_DLL); | 219 | uart->dll = serial_read_reg(uart, UART_DLL); |
| 224 | uart->dlh = serial_read_reg(uart, UART_DLM); | 220 | uart->dlh = serial_read_reg(uart, UART_DLM); |
| 225 | serial_write_reg(uart, UART_LCR, lcr); | 221 | serial_write_reg(uart, UART_LCR, lcr); |
| @@ -227,7 +223,7 @@ static void omap_uart_save_context(struct omap_uart_state *uart) | |||
| 227 | uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC); | 223 | uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC); |
| 228 | uart->scr = serial_read_reg(uart, UART_OMAP_SCR); | 224 | uart->scr = serial_read_reg(uart, UART_OMAP_SCR); |
| 229 | uart->wer = serial_read_reg(uart, UART_OMAP_WER); | 225 | uart->wer = serial_read_reg(uart, UART_OMAP_WER); |
| 230 | serial_write_reg(uart, UART_LCR, 0x80); | 226 | serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A); |
| 231 | uart->mcr = serial_read_reg(uart, UART_MCR); | 227 | uart->mcr = serial_read_reg(uart, UART_MCR); |
| 232 | serial_write_reg(uart, UART_LCR, lcr); | 228 | serial_write_reg(uart, UART_LCR, lcr); |
| 233 | 229 | ||
| @@ -247,32 +243,35 @@ static void omap_uart_restore_context(struct omap_uart_state *uart) | |||
| 247 | uart->context_valid = 0; | 243 | uart->context_valid = 0; |
| 248 | 244 | ||
| 249 | if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) | 245 | if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) |
| 250 | omap_uart_mdr1_errataset(uart, 0x07, 0xA0); | 246 | omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_DISABLE, 0xA0); |
| 251 | else | 247 | else |
| 252 | serial_write_reg(uart, UART_OMAP_MDR1, 0x7); | 248 | serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); |
| 253 | serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */ | 249 | |
| 250 | serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); | ||
| 254 | efr = serial_read_reg(uart, UART_EFR); | 251 | efr = serial_read_reg(uart, UART_EFR); |
| 255 | serial_write_reg(uart, UART_EFR, UART_EFR_ECB); | 252 | serial_write_reg(uart, UART_EFR, UART_EFR_ECB); |
| 256 | serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */ | 253 | serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */ |
| 257 | serial_write_reg(uart, UART_IER, 0x0); | 254 | serial_write_reg(uart, UART_IER, 0x0); |
| 258 | serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */ | 255 | serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); |
| 259 | serial_write_reg(uart, UART_DLL, uart->dll); | 256 | serial_write_reg(uart, UART_DLL, uart->dll); |
| 260 | serial_write_reg(uart, UART_DLM, uart->dlh); | 257 | serial_write_reg(uart, UART_DLM, uart->dlh); |
| 261 | serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */ | 258 | serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */ |
| 262 | serial_write_reg(uart, UART_IER, uart->ier); | 259 | serial_write_reg(uart, UART_IER, uart->ier); |
| 263 | serial_write_reg(uart, UART_LCR, 0x80); | 260 | serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A); |
| 264 | serial_write_reg(uart, UART_MCR, uart->mcr); | 261 | serial_write_reg(uart, UART_MCR, uart->mcr); |
| 265 | serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */ | 262 | serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); |
| 266 | serial_write_reg(uart, UART_EFR, efr); | 263 | serial_write_reg(uart, UART_EFR, efr); |
| 267 | serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8); | 264 | serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8); |
| 268 | serial_write_reg(uart, UART_OMAP_SCR, uart->scr); | 265 | serial_write_reg(uart, UART_OMAP_SCR, uart->scr); |
| 269 | serial_write_reg(uart, UART_OMAP_WER, uart->wer); | 266 | serial_write_reg(uart, UART_OMAP_WER, uart->wer); |
| 270 | serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc); | 267 | serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc); |
| 268 | |||
| 271 | if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) | 269 | if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) |
| 272 | omap_uart_mdr1_errataset(uart, 0x00, 0xA1); | 270 | omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_16X_MODE, 0xA1); |
| 273 | else | 271 | else |
| 274 | /* UART 16x mode */ | 272 | /* UART 16x mode */ |
| 275 | serial_write_reg(uart, UART_OMAP_MDR1, 0x00); | 273 | serial_write_reg(uart, UART_OMAP_MDR1, |
| 274 | UART_OMAP_MDR1_16X_MODE); | ||
| 276 | } | 275 | } |
| 277 | #else | 276 | #else |
| 278 | static inline void omap_uart_save_context(struct omap_uart_state *uart) {} | 277 | static inline void omap_uart_save_context(struct omap_uart_state *uart) {} |
| @@ -492,6 +491,7 @@ static void omap_uart_idle_init(struct omap_uart_state *uart) | |||
| 492 | u32 wk_mask = 0; | 491 | u32 wk_mask = 0; |
| 493 | u32 padconf = 0; | 492 | u32 padconf = 0; |
| 494 | 493 | ||
| 494 | /* XXX These PRM accesses do not belong here */ | ||
| 495 | uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1); | 495 | uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1); |
| 496 | uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1); | 496 | uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1); |
| 497 | switch (uart->num) { | 497 | switch (uart->num) { |
| @@ -695,16 +695,16 @@ void __init omap_serial_early_init(void) | |||
| 695 | 695 | ||
| 696 | /** | 696 | /** |
| 697 | * omap_serial_init_port() - initialize single serial port | 697 | * omap_serial_init_port() - initialize single serial port |
| 698 | * @port: serial port number (0-3) | 698 | * @bdata: port specific board data pointer |
| 699 | * | 699 | * |
| 700 | * This function initialies serial driver for given @port only. | 700 | * This function initialies serial driver for given port only. |
| 701 | * Platforms can call this function instead of omap_serial_init() | 701 | * Platforms can call this function instead of omap_serial_init() |
| 702 | * if they don't plan to use all available UARTs as serial ports. | 702 | * if they don't plan to use all available UARTs as serial ports. |
| 703 | * | 703 | * |
| 704 | * Don't mix calls to omap_serial_init_port() and omap_serial_init(), | 704 | * Don't mix calls to omap_serial_init_port() and omap_serial_init(), |
| 705 | * use only one of the two. | 705 | * use only one of the two. |
| 706 | */ | 706 | */ |
| 707 | void __init omap_serial_init_port(int port) | 707 | void __init omap_serial_init_port(struct omap_board_data *bdata) |
| 708 | { | 708 | { |
| 709 | struct omap_uart_state *uart; | 709 | struct omap_uart_state *uart; |
| 710 | struct omap_hwmod *oh; | 710 | struct omap_hwmod *oh; |
| @@ -722,13 +722,15 @@ void __init omap_serial_init_port(int port) | |||
| 722 | struct omap_uart_port_info omap_up; | 722 | struct omap_uart_port_info omap_up; |
| 723 | #endif | 723 | #endif |
| 724 | 724 | ||
| 725 | if (WARN_ON(port < 0)) | 725 | if (WARN_ON(!bdata)) |
| 726 | return; | ||
| 727 | if (WARN_ON(bdata->id < 0)) | ||
| 726 | return; | 728 | return; |
| 727 | if (WARN_ON(port >= num_uarts)) | 729 | if (WARN_ON(bdata->id >= num_uarts)) |
| 728 | return; | 730 | return; |
| 729 | 731 | ||
| 730 | list_for_each_entry(uart, &uart_list, node) | 732 | list_for_each_entry(uart, &uart_list, node) |
| 731 | if (port == uart->num) | 733 | if (bdata->id == uart->num) |
| 732 | break; | 734 | break; |
| 733 | 735 | ||
| 734 | oh = uart->oh; | 736 | oh = uart->oh; |
| @@ -800,6 +802,8 @@ void __init omap_serial_init_port(int port) | |||
| 800 | WARN(IS_ERR(od), "Could not build omap_device for %s: %s.\n", | 802 | WARN(IS_ERR(od), "Could not build omap_device for %s: %s.\n", |
| 801 | name, oh->name); | 803 | name, oh->name); |
| 802 | 804 | ||
| 805 | oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt); | ||
| 806 | |||
| 803 | uart->irq = oh->mpu_irqs[0].irq; | 807 | uart->irq = oh->mpu_irqs[0].irq; |
| 804 | uart->regshift = 2; | 808 | uart->regshift = 2; |
| 805 | uart->mapbase = oh->slaves[0]->addr->pa_start; | 809 | uart->mapbase = oh->slaves[0]->addr->pa_start; |
| @@ -857,7 +861,14 @@ void __init omap_serial_init_port(int port) | |||
| 857 | void __init omap_serial_init(void) | 861 | void __init omap_serial_init(void) |
| 858 | { | 862 | { |
| 859 | struct omap_uart_state *uart; | 863 | struct omap_uart_state *uart; |
| 864 | struct omap_board_data bdata; | ||
| 860 | 865 | ||
| 861 | list_for_each_entry(uart, &uart_list, node) | 866 | list_for_each_entry(uart, &uart_list, node) { |
| 862 | omap_serial_init_port(uart->num); | 867 | bdata.id = uart->num; |
| 868 | bdata.flags = 0; | ||
| 869 | bdata.pads = NULL; | ||
| 870 | bdata.pads_cnt = 0; | ||
| 871 | omap_serial_init_port(&bdata); | ||
| 872 | |||
| 873 | } | ||
| 863 | } | 874 | } |
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index 2fb205a7f285..98d8232808b8 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S | |||
| @@ -1,6 +1,4 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * linux/arch/arm/mach-omap2/sleep.S | ||
| 3 | * | ||
| 4 | * (C) Copyright 2007 | 2 | * (C) Copyright 2007 |
| 5 | * Texas Instruments | 3 | * Texas Instruments |
| 6 | * Karthik Dasu <karthik-dp@ti.com> | 4 | * Karthik Dasu <karthik-dp@ti.com> |
| @@ -26,28 +24,35 @@ | |||
| 26 | */ | 24 | */ |
| 27 | #include <linux/linkage.h> | 25 | #include <linux/linkage.h> |
| 28 | #include <asm/assembler.h> | 26 | #include <asm/assembler.h> |
| 27 | #include <plat/sram.h> | ||
| 29 | #include <mach/io.h> | 28 | #include <mach/io.h> |
| 30 | 29 | ||
| 31 | #include "cm.h" | 30 | #include "cm2xxx_3xxx.h" |
| 32 | #include "prm.h" | 31 | #include "prm2xxx_3xxx.h" |
| 33 | #include "sdrc.h" | 32 | #include "sdrc.h" |
| 34 | #include "control.h" | 33 | #include "control.h" |
| 35 | 34 | ||
| 36 | #define SDRC_SCRATCHPAD_SEM_V 0xfa00291c | 35 | /* |
| 37 | 36 | * Registers access definitions | |
| 38 | #define PM_PREPWSTST_CORE_V OMAP34XX_PRM_REGADDR(CORE_MOD, \ | 37 | */ |
| 39 | OMAP3430_PM_PREPWSTST) | 38 | #define SDRC_SCRATCHPAD_SEM_OFFS 0xc |
| 40 | #define PM_PREPWSTST_CORE_P 0x48306AE8 | 39 | #define SDRC_SCRATCHPAD_SEM_V OMAP343X_SCRATCHPAD_REGADDR\ |
| 41 | #define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \ | 40 | (SDRC_SCRATCHPAD_SEM_OFFS) |
| 42 | OMAP3430_PM_PREPWSTST) | 41 | #define PM_PREPWSTST_CORE_P OMAP3430_PRM_BASE + CORE_MOD +\ |
| 42 | OMAP3430_PM_PREPWSTST | ||
| 43 | #define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL | 43 | #define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL |
| 44 | #define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1) | 44 | #define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1) |
| 45 | #define SRAM_BASE_P 0x40200000 | 45 | #define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST) |
| 46 | #define CONTROL_STAT 0x480022F0 | 46 | #define SRAM_BASE_P OMAP3_SRAM_PA |
| 47 | #define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is | 47 | #define CONTROL_STAT OMAP343X_CTRL_BASE + OMAP343X_CONTROL_STATUS |
| 48 | * available */ | 48 | #define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE +\ |
| 49 | #define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE + OMAP343X_CONTROL_MEM_WKUP\ | 49 | OMAP36XX_CONTROL_MEM_RTA_CTRL) |
| 50 | + SCRATCHPAD_MEM_OFFS) | 50 | |
| 51 | /* Move this as correct place is available */ | ||
| 52 | #define SCRATCHPAD_MEM_OFFS 0x310 | ||
| 53 | #define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE +\ | ||
| 54 | OMAP343X_CONTROL_MEM_WKUP +\ | ||
| 55 | SCRATCHPAD_MEM_OFFS) | ||
| 51 | #define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER) | 56 | #define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER) |
| 52 | #define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG) | 57 | #define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG) |
| 53 | #define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0) | 58 | #define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0) |
| @@ -59,48 +64,38 @@ | |||
| 59 | #define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) | 64 | #define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) |
| 60 | #define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) | 65 | #define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) |
| 61 | 66 | ||
| 62 | .text | 67 | |
| 63 | /* Function to acquire the semaphore in scratchpad */ | 68 | /* |
| 64 | ENTRY(lock_scratchpad_sem) | 69 | * API functions |
| 65 | stmfd sp!, {lr} @ save registers on stack | 70 | */ |
| 66 | wait_sem: | 71 | |
| 67 | mov r0,#1 | 72 | /* |
| 68 | ldr r1, sdrc_scratchpad_sem | 73 | * The "get_*restore_pointer" functions are used to provide a |
| 69 | wait_loop: | 74 | * physical restore address where the ROM code jumps while waking |
| 70 | ldr r2, [r1] @ load the lock value | 75 | * up from MPU OFF/OSWR state. |
| 71 | cmp r2, r0 @ is the lock free ? | 76 | * The restore pointer is stored into the scratchpad. |
| 72 | beq wait_loop @ not free... | 77 | */ |
| 73 | swp r2, r0, [r1] @ semaphore free so lock it and proceed | ||
| 74 | cmp r2, r0 @ did we succeed ? | ||
| 75 | beq wait_sem @ no - try again | ||
| 76 | ldmfd sp!, {pc} @ restore regs and return | ||
| 77 | sdrc_scratchpad_sem: | ||
| 78 | .word SDRC_SCRATCHPAD_SEM_V | ||
| 79 | ENTRY(lock_scratchpad_sem_sz) | ||
| 80 | .word . - lock_scratchpad_sem | ||
| 81 | |||
| 82 | .text | ||
| 83 | /* Function to release the scratchpad semaphore */ | ||
| 84 | ENTRY(unlock_scratchpad_sem) | ||
| 85 | stmfd sp!, {lr} @ save registers on stack | ||
| 86 | ldr r3, sdrc_scratchpad_sem | ||
| 87 | mov r2,#0 | ||
| 88 | str r2,[r3] | ||
| 89 | ldmfd sp!, {pc} @ restore regs and return | ||
| 90 | ENTRY(unlock_scratchpad_sem_sz) | ||
| 91 | .word . - unlock_scratchpad_sem | ||
| 92 | 78 | ||
| 93 | .text | 79 | .text |
| 94 | /* Function call to get the restore pointer for resume from OFF */ | 80 | /* Function call to get the restore pointer for resume from OFF */ |
| 95 | ENTRY(get_restore_pointer) | 81 | ENTRY(get_restore_pointer) |
| 96 | stmfd sp!, {lr} @ save registers on stack | 82 | stmfd sp!, {lr} @ save registers on stack |
| 97 | adr r0, restore | 83 | adr r0, restore |
| 98 | ldmfd sp!, {pc} @ restore regs and return | 84 | ldmfd sp!, {pc} @ restore regs and return |
| 99 | ENTRY(get_restore_pointer_sz) | 85 | ENTRY(get_restore_pointer_sz) |
| 100 | .word . - get_restore_pointer | 86 | .word . - get_restore_pointer |
| 101 | 87 | ||
| 102 | .text | 88 | .text |
| 103 | /* Function call to get the restore pointer for for ES3 to resume from OFF */ | 89 | /* Function call to get the restore pointer for 3630 resume from OFF */ |
| 90 | ENTRY(get_omap3630_restore_pointer) | ||
| 91 | stmfd sp!, {lr} @ save registers on stack | ||
| 92 | adr r0, restore_3630 | ||
| 93 | ldmfd sp!, {pc} @ restore regs and return | ||
| 94 | ENTRY(get_omap3630_restore_pointer_sz) | ||
| 95 | .word . - get_omap3630_restore_pointer | ||
| 96 | |||
| 97 | .text | ||
| 98 | /* Function call to get the restore pointer for ES3 to resume from OFF */ | ||
| 104 | ENTRY(get_es3_restore_pointer) | 99 | ENTRY(get_es3_restore_pointer) |
| 105 | stmfd sp!, {lr} @ save registers on stack | 100 | stmfd sp!, {lr} @ save registers on stack |
| 106 | adr r0, restore_es3 | 101 | adr r0, restore_es3 |
| @@ -108,54 +103,23 @@ ENTRY(get_es3_restore_pointer) | |||
| 108 | ENTRY(get_es3_restore_pointer_sz) | 103 | ENTRY(get_es3_restore_pointer_sz) |
| 109 | .word . - get_es3_restore_pointer | 104 | .word . - get_es3_restore_pointer |
| 110 | 105 | ||
| 111 | ENTRY(es3_sdrc_fix) | 106 | .text |
| 112 | ldr r4, sdrc_syscfg @ get config addr | 107 | /* |
| 113 | ldr r5, [r4] @ get value | 108 | * L2 cache needs to be toggled for stable OFF mode functionality on 3630. |
| 114 | tst r5, #0x100 @ is part access blocked | 109 | * This function sets up a flag that will allow for this toggling to take |
| 115 | it eq | 110 | * place on 3630. Hopefully some version in the future may not need this. |
| 116 | biceq r5, r5, #0x100 @ clear bit if set | 111 | */ |
| 117 | str r5, [r4] @ write back change | 112 | ENTRY(enable_omap3630_toggle_l2_on_restore) |
| 118 | ldr r4, sdrc_mr_0 @ get config addr | 113 | stmfd sp!, {lr} @ save registers on stack |
| 119 | ldr r5, [r4] @ get value | 114 | /* Setup so that we will disable and enable l2 */ |
| 120 | str r5, [r4] @ write back change | 115 | mov r1, #0x1 |
| 121 | ldr r4, sdrc_emr2_0 @ get config addr | 116 | str r1, l2dis_3630 |
| 122 | ldr r5, [r4] @ get value | 117 | ldmfd sp!, {pc} @ restore regs and return |
| 123 | str r5, [r4] @ write back change | ||
| 124 | ldr r4, sdrc_manual_0 @ get config addr | ||
| 125 | mov r5, #0x2 @ autorefresh command | ||
| 126 | str r5, [r4] @ kick off refreshes | ||
| 127 | ldr r4, sdrc_mr_1 @ get config addr | ||
| 128 | ldr r5, [r4] @ get value | ||
| 129 | str r5, [r4] @ write back change | ||
| 130 | ldr r4, sdrc_emr2_1 @ get config addr | ||
| 131 | ldr r5, [r4] @ get value | ||
| 132 | str r5, [r4] @ write back change | ||
| 133 | ldr r4, sdrc_manual_1 @ get config addr | ||
| 134 | mov r5, #0x2 @ autorefresh command | ||
| 135 | str r5, [r4] @ kick off refreshes | ||
| 136 | bx lr | ||
| 137 | sdrc_syscfg: | ||
| 138 | .word SDRC_SYSCONFIG_P | ||
| 139 | sdrc_mr_0: | ||
| 140 | .word SDRC_MR_0_P | ||
| 141 | sdrc_emr2_0: | ||
| 142 | .word SDRC_EMR2_0_P | ||
| 143 | sdrc_manual_0: | ||
| 144 | .word SDRC_MANUAL_0_P | ||
| 145 | sdrc_mr_1: | ||
| 146 | .word SDRC_MR_1_P | ||
| 147 | sdrc_emr2_1: | ||
| 148 | .word SDRC_EMR2_1_P | ||
| 149 | sdrc_manual_1: | ||
| 150 | .word SDRC_MANUAL_1_P | ||
| 151 | ENTRY(es3_sdrc_fix_sz) | ||
| 152 | .word . - es3_sdrc_fix | ||
| 153 | 118 | ||
| 119 | .text | ||
| 154 | /* Function to call rom code to save secure ram context */ | 120 | /* Function to call rom code to save secure ram context */ |
| 155 | ENTRY(save_secure_ram_context) | 121 | ENTRY(save_secure_ram_context) |
| 156 | stmfd sp!, {r1-r12, lr} @ save registers on stack | 122 | stmfd sp!, {r1-r12, lr} @ save registers on stack |
| 157 | save_secure_ram_debug: | ||
| 158 | /* b save_secure_ram_debug */ @ enable to debug save code | ||
| 159 | adr r3, api_params @ r3 points to parameters | 123 | adr r3, api_params @ r3 points to parameters |
| 160 | str r0, [r3,#0x4] @ r0 has sdram address | 124 | str r0, [r3,#0x4] @ r0 has sdram address |
| 161 | ldr r12, high_mask | 125 | ldr r12, high_mask |
| @@ -185,35 +149,162 @@ ENTRY(save_secure_ram_context_sz) | |||
| 185 | .word . - save_secure_ram_context | 149 | .word . - save_secure_ram_context |
| 186 | 150 | ||
| 187 | /* | 151 | /* |
| 152 | * ====================== | ||
| 153 | * == Idle entry point == | ||
| 154 | * ====================== | ||
| 155 | */ | ||
| 156 | |||
| 157 | /* | ||
| 188 | * Forces OMAP into idle state | 158 | * Forces OMAP into idle state |
| 189 | * | 159 | * |
| 190 | * omap34xx_suspend() - This bit of code just executes the WFI | 160 | * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed |
| 191 | * for normal idles. | 161 | * and executes the WFI instruction. Calling WFI effectively changes the |
| 162 | * power domains states to the desired target power states. | ||
| 163 | * | ||
| 192 | * | 164 | * |
| 193 | * Note: This code get's copied to internal SRAM at boot. When the OMAP | 165 | * Notes: |
| 194 | * wakes up it continues execution at the point it went to sleep. | 166 | * - this code gets copied to internal SRAM at boot and after wake-up |
| 167 | * from OFF mode. The execution pointer in SRAM is _omap_sram_idle. | ||
| 168 | * - when the OMAP wakes up it continues at different execution points | ||
| 169 | * depending on the low power mode (non-OFF vs OFF modes), | ||
| 170 | * cf. 'Resume path for xxx mode' comments. | ||
| 195 | */ | 171 | */ |
| 196 | ENTRY(omap34xx_cpu_suspend) | 172 | ENTRY(omap34xx_cpu_suspend) |
| 197 | stmfd sp!, {r0-r12, lr} @ save registers on stack | 173 | stmfd sp!, {r0-r12, lr} @ save registers on stack |
| 198 | loop: | ||
| 199 | /*b loop*/ @Enable to debug by stepping through code | ||
| 200 | /* r0 contains restore pointer in sdram */ | ||
| 201 | /* r1 contains information about saving context */ | ||
| 202 | ldr r4, sdrc_power @ read the SDRC_POWER register | ||
| 203 | ldr r5, [r4] @ read the contents of SDRC_POWER | ||
| 204 | orr r5, r5, #0x40 @ enable self refresh on idle req | ||
| 205 | str r5, [r4] @ write back to SDRC_POWER register | ||
| 206 | 174 | ||
| 175 | /* | ||
| 176 | * r0 contains restore pointer in sdram | ||
| 177 | * r1 contains information about saving context: | ||
| 178 | * 0 - No context lost | ||
| 179 | * 1 - Only L1 and logic lost | ||
| 180 | * 2 - Only L2 lost | ||
| 181 | * 3 - Both L1 and L2 lost | ||
| 182 | */ | ||
| 183 | |||
| 184 | /* Directly jump to WFI is the context save is not required */ | ||
| 207 | cmp r1, #0x0 | 185 | cmp r1, #0x0 |
| 208 | /* If context save is required, do that and execute wfi */ | 186 | beq omap3_do_wfi |
| 209 | bne save_context_wfi | 187 | |
| 188 | /* Otherwise fall through to the save context code */ | ||
| 189 | save_context_wfi: | ||
| 190 | mov r8, r0 @ Store SDRAM address in r8 | ||
| 191 | mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register | ||
| 192 | mov r4, #0x1 @ Number of parameters for restore call | ||
| 193 | stmia r8!, {r4-r5} @ Push parameters for restore call | ||
| 194 | mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register | ||
| 195 | stmia r8!, {r4-r5} @ Push parameters for restore call | ||
| 196 | |||
| 197 | /* Check what that target sleep state is from r1 */ | ||
| 198 | cmp r1, #0x2 @ Only L2 lost, no need to save context | ||
| 199 | beq clean_caches | ||
| 200 | |||
| 201 | l1_logic_lost: | ||
| 202 | /* Store sp and spsr to SDRAM */ | ||
| 203 | mov r4, sp | ||
| 204 | mrs r5, spsr | ||
| 205 | mov r6, lr | ||
| 206 | stmia r8!, {r4-r6} | ||
| 207 | /* Save all ARM registers */ | ||
| 208 | /* Coprocessor access control register */ | ||
| 209 | mrc p15, 0, r6, c1, c0, 2 | ||
| 210 | stmia r8!, {r6} | ||
| 211 | /* TTBR0, TTBR1 and Translation table base control */ | ||
| 212 | mrc p15, 0, r4, c2, c0, 0 | ||
| 213 | mrc p15, 0, r5, c2, c0, 1 | ||
| 214 | mrc p15, 0, r6, c2, c0, 2 | ||
| 215 | stmia r8!, {r4-r6} | ||
| 216 | /* | ||
| 217 | * Domain access control register, data fault status register, | ||
| 218 | * and instruction fault status register | ||
| 219 | */ | ||
| 220 | mrc p15, 0, r4, c3, c0, 0 | ||
| 221 | mrc p15, 0, r5, c5, c0, 0 | ||
| 222 | mrc p15, 0, r6, c5, c0, 1 | ||
| 223 | stmia r8!, {r4-r6} | ||
| 224 | /* | ||
| 225 | * Data aux fault status register, instruction aux fault status, | ||
| 226 | * data fault address register and instruction fault address register | ||
| 227 | */ | ||
| 228 | mrc p15, 0, r4, c5, c1, 0 | ||
| 229 | mrc p15, 0, r5, c5, c1, 1 | ||
| 230 | mrc p15, 0, r6, c6, c0, 0 | ||
| 231 | mrc p15, 0, r7, c6, c0, 2 | ||
| 232 | stmia r8!, {r4-r7} | ||
| 233 | /* | ||
| 234 | * user r/w thread and process ID, user r/o thread and process ID, | ||
| 235 | * priv only thread and process ID, cache size selection | ||
| 236 | */ | ||
| 237 | mrc p15, 0, r4, c13, c0, 2 | ||
| 238 | mrc p15, 0, r5, c13, c0, 3 | ||
| 239 | mrc p15, 0, r6, c13, c0, 4 | ||
| 240 | mrc p15, 2, r7, c0, c0, 0 | ||
| 241 | stmia r8!, {r4-r7} | ||
| 242 | /* Data TLB lockdown, instruction TLB lockdown registers */ | ||
| 243 | mrc p15, 0, r5, c10, c0, 0 | ||
| 244 | mrc p15, 0, r6, c10, c0, 1 | ||
| 245 | stmia r8!, {r5-r6} | ||
| 246 | /* Secure or non secure vector base address, FCSE PID, Context PID*/ | ||
| 247 | mrc p15, 0, r4, c12, c0, 0 | ||
| 248 | mrc p15, 0, r5, c13, c0, 0 | ||
| 249 | mrc p15, 0, r6, c13, c0, 1 | ||
| 250 | stmia r8!, {r4-r6} | ||
| 251 | /* Primary remap, normal remap registers */ | ||
| 252 | mrc p15, 0, r4, c10, c2, 0 | ||
| 253 | mrc p15, 0, r5, c10, c2, 1 | ||
| 254 | stmia r8!,{r4-r5} | ||
| 255 | |||
| 256 | /* Store current cpsr*/ | ||
| 257 | mrs r2, cpsr | ||
| 258 | stmia r8!, {r2} | ||
| 259 | |||
| 260 | mrc p15, 0, r4, c1, c0, 0 | ||
| 261 | /* save control register */ | ||
| 262 | stmia r8!, {r4} | ||
| 263 | |||
| 264 | clean_caches: | ||
| 265 | /* | ||
| 266 | * Clean Data or unified cache to POU | ||
| 267 | * How to invalidate only L1 cache???? - #FIX_ME# | ||
| 268 | * mcr p15, 0, r11, c7, c11, 1 | ||
| 269 | */ | ||
| 270 | cmp r1, #0x1 @ Check whether L2 inval is required | ||
| 271 | beq omap3_do_wfi | ||
| 272 | |||
| 273 | clean_l2: | ||
| 274 | /* | ||
| 275 | * jump out to kernel flush routine | ||
| 276 | * - reuse that code is better | ||
| 277 | * - it executes in a cached space so is faster than refetch per-block | ||
| 278 | * - should be faster and will change with kernel | ||
| 279 | * - 'might' have to copy address, load and jump to it | ||
| 280 | */ | ||
| 281 | ldr r1, kernel_flush | ||
| 282 | mov lr, pc | ||
| 283 | bx r1 | ||
| 284 | |||
| 285 | omap3_do_wfi: | ||
| 286 | ldr r4, sdrc_power @ read the SDRC_POWER register | ||
| 287 | ldr r5, [r4] @ read the contents of SDRC_POWER | ||
| 288 | orr r5, r5, #0x40 @ enable self refresh on idle req | ||
| 289 | str r5, [r4] @ write back to SDRC_POWER register | ||
| 290 | |||
| 210 | /* Data memory barrier and Data sync barrier */ | 291 | /* Data memory barrier and Data sync barrier */ |
| 211 | mov r1, #0 | 292 | mov r1, #0 |
| 212 | mcr p15, 0, r1, c7, c10, 4 | 293 | mcr p15, 0, r1, c7, c10, 4 |
| 213 | mcr p15, 0, r1, c7, c10, 5 | 294 | mcr p15, 0, r1, c7, c10, 5 |
| 214 | 295 | ||
| 296 | /* | ||
| 297 | * =================================== | ||
| 298 | * == WFI instruction => Enter idle == | ||
| 299 | * =================================== | ||
| 300 | */ | ||
| 215 | wfi @ wait for interrupt | 301 | wfi @ wait for interrupt |
| 216 | 302 | ||
| 303 | /* | ||
| 304 | * =================================== | ||
| 305 | * == Resume path for non-OFF modes == | ||
| 306 | * =================================== | ||
| 307 | */ | ||
| 217 | nop | 308 | nop |
| 218 | nop | 309 | nop |
| 219 | nop | 310 | nop |
| @@ -226,9 +317,30 @@ loop: | |||
| 226 | nop | 317 | nop |
| 227 | bl wait_sdrc_ok | 318 | bl wait_sdrc_ok |
| 228 | 319 | ||
| 229 | ldmfd sp!, {r0-r12, pc} @ restore regs and return | 320 | /* |
| 321 | * =================================== | ||
| 322 | * == Exit point from non-OFF modes == | ||
| 323 | * =================================== | ||
| 324 | */ | ||
| 325 | ldmfd sp!, {r0-r12, pc} @ restore regs and return | ||
| 326 | |||
| 327 | |||
| 328 | /* | ||
| 329 | * ============================== | ||
| 330 | * == Resume path for OFF mode == | ||
| 331 | * ============================== | ||
| 332 | */ | ||
| 333 | |||
| 334 | /* | ||
| 335 | * The restore_* functions are called by the ROM code | ||
| 336 | * when back from WFI in OFF mode. | ||
| 337 | * Cf. the get_*restore_pointer functions. | ||
| 338 | * | ||
| 339 | * restore_es3: applies to 34xx >= ES3.0 | ||
| 340 | * restore_3630: applies to 36xx | ||
| 341 | * restore: common code for 3xxx | ||
| 342 | */ | ||
| 230 | restore_es3: | 343 | restore_es3: |
| 231 | /*b restore_es3*/ @ Enable to debug restore code | ||
| 232 | ldr r5, pm_prepwstst_core_p | 344 | ldr r5, pm_prepwstst_core_p |
| 233 | ldr r4, [r5] | 345 | ldr r4, [r5] |
| 234 | and r4, r4, #0x3 | 346 | and r4, r4, #0x3 |
| @@ -245,82 +357,117 @@ copy_to_sram: | |||
| 245 | bne copy_to_sram | 357 | bne copy_to_sram |
| 246 | ldr r1, sram_base | 358 | ldr r1, sram_base |
| 247 | blx r1 | 359 | blx r1 |
| 360 | b restore | ||
| 361 | |||
| 362 | restore_3630: | ||
| 363 | ldr r1, pm_prepwstst_core_p | ||
| 364 | ldr r2, [r1] | ||
| 365 | and r2, r2, #0x3 | ||
| 366 | cmp r2, #0x0 @ Check if previous power state of CORE is OFF | ||
| 367 | bne restore | ||
| 368 | /* Disable RTA before giving control */ | ||
| 369 | ldr r1, control_mem_rta | ||
| 370 | mov r2, #OMAP36XX_RTA_DISABLE | ||
| 371 | str r2, [r1] | ||
| 372 | |||
| 373 | /* Fall through to common code for the remaining logic */ | ||
| 374 | |||
| 248 | restore: | 375 | restore: |
| 249 | /* b restore*/ @ Enable to debug restore code | 376 | /* |
| 250 | /* Check what was the reason for mpu reset and store the reason in r9*/ | 377 | * Check what was the reason for mpu reset and store the reason in r9: |
| 251 | /* 1 - Only L1 and logic lost */ | 378 | * 0 - No context lost |
| 252 | /* 2 - Only L2 lost - In this case, we wont be here */ | 379 | * 1 - Only L1 and logic lost |
| 253 | /* 3 - Both L1 and L2 lost */ | 380 | * 2 - Only L2 lost - In this case, we wont be here |
| 254 | ldr r1, pm_pwstctrl_mpu | 381 | * 3 - Both L1 and L2 lost |
| 382 | */ | ||
| 383 | ldr r1, pm_pwstctrl_mpu | ||
| 255 | ldr r2, [r1] | 384 | ldr r2, [r1] |
| 256 | and r2, r2, #0x3 | 385 | and r2, r2, #0x3 |
| 257 | cmp r2, #0x0 @ Check if target power state was OFF or RET | 386 | cmp r2, #0x0 @ Check if target power state was OFF or RET |
| 258 | moveq r9, #0x3 @ MPU OFF => L1 and L2 lost | 387 | moveq r9, #0x3 @ MPU OFF => L1 and L2 lost |
| 259 | movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation | 388 | movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation |
| 260 | bne logic_l1_restore | 389 | bne logic_l1_restore |
| 390 | |||
| 391 | ldr r0, l2dis_3630 | ||
| 392 | cmp r0, #0x1 @ should we disable L2 on 3630? | ||
| 393 | bne skipl2dis | ||
| 394 | mrc p15, 0, r0, c1, c0, 1 | ||
| 395 | bic r0, r0, #2 @ disable L2 cache | ||
| 396 | mcr p15, 0, r0, c1, c0, 1 | ||
| 397 | skipl2dis: | ||
| 261 | ldr r0, control_stat | 398 | ldr r0, control_stat |
| 262 | ldr r1, [r0] | 399 | ldr r1, [r0] |
| 263 | and r1, #0x700 | 400 | and r1, #0x700 |
| 264 | cmp r1, #0x300 | 401 | cmp r1, #0x300 |
| 265 | beq l2_inv_gp | 402 | beq l2_inv_gp |
| 266 | mov r0, #40 @ set service ID for PPA | 403 | mov r0, #40 @ set service ID for PPA |
| 267 | mov r12, r0 @ copy secure Service ID in r12 | 404 | mov r12, r0 @ copy secure Service ID in r12 |
| 268 | mov r1, #0 @ set task id for ROM code in r1 | 405 | mov r1, #0 @ set task id for ROM code in r1 |
| 269 | mov r2, #4 @ set some flags in r2, r6 | 406 | mov r2, #4 @ set some flags in r2, r6 |
| 270 | mov r6, #0xff | 407 | mov r6, #0xff |
| 271 | adr r3, l2_inv_api_params @ r3 points to dummy parameters | 408 | adr r3, l2_inv_api_params @ r3 points to dummy parameters |
| 272 | mcr p15, 0, r0, c7, c10, 4 @ data write barrier | 409 | mcr p15, 0, r0, c7, c10, 4 @ data write barrier |
| 273 | mcr p15, 0, r0, c7, c10, 5 @ data memory barrier | 410 | mcr p15, 0, r0, c7, c10, 5 @ data memory barrier |
| 274 | .word 0xE1600071 @ call SMI monitor (smi #1) | 411 | .word 0xE1600071 @ call SMI monitor (smi #1) |
| 275 | /* Write to Aux control register to set some bits */ | 412 | /* Write to Aux control register to set some bits */ |
| 276 | mov r0, #42 @ set service ID for PPA | 413 | mov r0, #42 @ set service ID for PPA |
| 277 | mov r12, r0 @ copy secure Service ID in r12 | 414 | mov r12, r0 @ copy secure Service ID in r12 |
| 278 | mov r1, #0 @ set task id for ROM code in r1 | 415 | mov r1, #0 @ set task id for ROM code in r1 |
| 279 | mov r2, #4 @ set some flags in r2, r6 | 416 | mov r2, #4 @ set some flags in r2, r6 |
| 280 | mov r6, #0xff | 417 | mov r6, #0xff |
| 281 | ldr r4, scratchpad_base | 418 | ldr r4, scratchpad_base |
| 282 | ldr r3, [r4, #0xBC] @ r3 points to parameters | 419 | ldr r3, [r4, #0xBC] @ r3 points to parameters |
| 283 | mcr p15, 0, r0, c7, c10, 4 @ data write barrier | 420 | mcr p15, 0, r0, c7, c10, 4 @ data write barrier |
| 284 | mcr p15, 0, r0, c7, c10, 5 @ data memory barrier | 421 | mcr p15, 0, r0, c7, c10, 5 @ data memory barrier |
| 285 | .word 0xE1600071 @ call SMI monitor (smi #1) | 422 | .word 0xE1600071 @ call SMI monitor (smi #1) |
| 286 | 423 | ||
| 287 | #ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE | 424 | #ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE |
| 288 | /* Restore L2 aux control register */ | 425 | /* Restore L2 aux control register */ |
| 289 | @ set service ID for PPA | 426 | @ set service ID for PPA |
| 290 | mov r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID | 427 | mov r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID |
| 291 | mov r12, r0 @ copy service ID in r12 | 428 | mov r12, r0 @ copy service ID in r12 |
| 292 | mov r1, #0 @ set task ID for ROM code in r1 | 429 | mov r1, #0 @ set task ID for ROM code in r1 |
| 293 | mov r2, #4 @ set some flags in r2, r6 | 430 | mov r2, #4 @ set some flags in r2, r6 |
| 294 | mov r6, #0xff | 431 | mov r6, #0xff |
| 295 | ldr r4, scratchpad_base | 432 | ldr r4, scratchpad_base |
| 296 | ldr r3, [r4, #0xBC] | 433 | ldr r3, [r4, #0xBC] |
| 297 | adds r3, r3, #8 @ r3 points to parameters | 434 | adds r3, r3, #8 @ r3 points to parameters |
| 298 | mcr p15, 0, r0, c7, c10, 4 @ data write barrier | 435 | mcr p15, 0, r0, c7, c10, 4 @ data write barrier |
| 299 | mcr p15, 0, r0, c7, c10, 5 @ data memory barrier | 436 | mcr p15, 0, r0, c7, c10, 5 @ data memory barrier |
| 300 | .word 0xE1600071 @ call SMI monitor (smi #1) | 437 | .word 0xE1600071 @ call SMI monitor (smi #1) |
| 301 | #endif | 438 | #endif |
| 302 | b logic_l1_restore | 439 | b logic_l1_restore |
| 440 | |||
| 303 | l2_inv_api_params: | 441 | l2_inv_api_params: |
| 304 | .word 0x1, 0x00 | 442 | .word 0x1, 0x00 |
| 305 | l2_inv_gp: | 443 | l2_inv_gp: |
| 306 | /* Execute smi to invalidate L2 cache */ | 444 | /* Execute smi to invalidate L2 cache */ |
| 307 | mov r12, #0x1 @ set up to invalide L2 | 445 | mov r12, #0x1 @ set up to invalidate L2 |
| 308 | smi: .word 0xE1600070 @ Call SMI monitor (smieq) | 446 | .word 0xE1600070 @ Call SMI monitor (smieq) |
| 309 | /* Write to Aux control register to set some bits */ | 447 | /* Write to Aux control register to set some bits */ |
| 310 | ldr r4, scratchpad_base | 448 | ldr r4, scratchpad_base |
| 311 | ldr r3, [r4,#0xBC] | 449 | ldr r3, [r4,#0xBC] |
| 312 | ldr r0, [r3,#4] | 450 | ldr r0, [r3,#4] |
| 313 | mov r12, #0x3 | 451 | mov r12, #0x3 |
| 314 | .word 0xE1600070 @ Call SMI monitor (smieq) | 452 | .word 0xE1600070 @ Call SMI monitor (smieq) |
| 315 | ldr r4, scratchpad_base | 453 | ldr r4, scratchpad_base |
| 316 | ldr r3, [r4,#0xBC] | 454 | ldr r3, [r4,#0xBC] |
| 317 | ldr r0, [r3,#12] | 455 | ldr r0, [r3,#12] |
| 318 | mov r12, #0x2 | 456 | mov r12, #0x2 |
| 319 | .word 0xE1600070 @ Call SMI monitor (smieq) | 457 | .word 0xE1600070 @ Call SMI monitor (smieq) |
| 320 | logic_l1_restore: | 458 | logic_l1_restore: |
| 459 | ldr r1, l2dis_3630 | ||
| 460 | cmp r1, #0x1 @ Test if L2 re-enable needed on 3630 | ||
| 461 | bne skipl2reen | ||
| 462 | mrc p15, 0, r1, c1, c0, 1 | ||
| 463 | orr r1, r1, #2 @ re-enable L2 cache | ||
| 464 | mcr p15, 0, r1, c1, c0, 1 | ||
| 465 | skipl2reen: | ||
| 321 | mov r1, #0 | 466 | mov r1, #0 |
| 322 | /* Invalidate all instruction caches to PoU | 467 | /* |
| 323 | * and flush branch target cache */ | 468 | * Invalidate all instruction caches to PoU |
| 469 | * and flush branch target cache | ||
| 470 | */ | ||
| 324 | mcr p15, 0, r1, c7, c5, 0 | 471 | mcr p15, 0, r1, c7, c5, 0 |
| 325 | 472 | ||
| 326 | ldr r4, scratchpad_base | 473 | ldr r4, scratchpad_base |
| @@ -341,33 +488,33 @@ logic_l1_restore: | |||
| 341 | MCR p15, 0, r6, c2, c0, 1 | 488 | MCR p15, 0, r6, c2, c0, 1 |
| 342 | /* Translation table base control register */ | 489 | /* Translation table base control register */ |
| 343 | MCR p15, 0, r7, c2, c0, 2 | 490 | MCR p15, 0, r7, c2, c0, 2 |
| 344 | /*domain access Control Register */ | 491 | /* Domain access Control Register */ |
| 345 | MCR p15, 0, r8, c3, c0, 0 | 492 | MCR p15, 0, r8, c3, c0, 0 |
| 346 | /* data fault status Register */ | 493 | /* Data fault status Register */ |
| 347 | MCR p15, 0, r9, c5, c0, 0 | 494 | MCR p15, 0, r9, c5, c0, 0 |
| 348 | 495 | ||
| 349 | ldmia r3!,{r4-r8} | 496 | ldmia r3!,{r4-r8} |
| 350 | /* instruction fault status Register */ | 497 | /* Instruction fault status Register */ |
| 351 | MCR p15, 0, r4, c5, c0, 1 | 498 | MCR p15, 0, r4, c5, c0, 1 |
| 352 | /*Data Auxiliary Fault Status Register */ | 499 | /* Data Auxiliary Fault Status Register */ |
| 353 | MCR p15, 0, r5, c5, c1, 0 | 500 | MCR p15, 0, r5, c5, c1, 0 |
| 354 | /*Instruction Auxiliary Fault Status Register*/ | 501 | /* Instruction Auxiliary Fault Status Register*/ |
| 355 | MCR p15, 0, r6, c5, c1, 1 | 502 | MCR p15, 0, r6, c5, c1, 1 |
| 356 | /*Data Fault Address Register */ | 503 | /* Data Fault Address Register */ |
| 357 | MCR p15, 0, r7, c6, c0, 0 | 504 | MCR p15, 0, r7, c6, c0, 0 |
| 358 | /*Instruction Fault Address Register*/ | 505 | /* Instruction Fault Address Register*/ |
| 359 | MCR p15, 0, r8, c6, c0, 2 | 506 | MCR p15, 0, r8, c6, c0, 2 |
| 360 | ldmia r3!,{r4-r7} | 507 | ldmia r3!,{r4-r7} |
| 361 | 508 | ||
| 362 | /* user r/w thread and process ID */ | 509 | /* User r/w thread and process ID */ |
| 363 | MCR p15, 0, r4, c13, c0, 2 | 510 | MCR p15, 0, r4, c13, c0, 2 |
| 364 | /* user ro thread and process ID */ | 511 | /* User ro thread and process ID */ |
| 365 | MCR p15, 0, r5, c13, c0, 3 | 512 | MCR p15, 0, r5, c13, c0, 3 |
| 366 | /*Privileged only thread and process ID */ | 513 | /* Privileged only thread and process ID */ |
| 367 | MCR p15, 0, r6, c13, c0, 4 | 514 | MCR p15, 0, r6, c13, c0, 4 |
| 368 | /* cache size selection */ | 515 | /* Cache size selection */ |
| 369 | MCR p15, 2, r7, c0, c0, 0 | 516 | MCR p15, 2, r7, c0, c0, 0 |
| 370 | ldmia r3!,{r4-r8} | 517 | ldmia r3!,{r4-r8} |
| 371 | /* Data TLB lockdown registers */ | 518 | /* Data TLB lockdown registers */ |
| 372 | MCR p15, 0, r4, c10, c0, 0 | 519 | MCR p15, 0, r4, c10, c0, 0 |
| 373 | /* Instruction TLB lockdown registers */ | 520 | /* Instruction TLB lockdown registers */ |
| @@ -379,26 +526,27 @@ logic_l1_restore: | |||
| 379 | /* Context PID */ | 526 | /* Context PID */ |
| 380 | MCR p15, 0, r8, c13, c0, 1 | 527 | MCR p15, 0, r8, c13, c0, 1 |
| 381 | 528 | ||
| 382 | ldmia r3!,{r4-r5} | 529 | ldmia r3!,{r4-r5} |
| 383 | /* primary memory remap register */ | 530 | /* Primary memory remap register */ |
| 384 | MCR p15, 0, r4, c10, c2, 0 | 531 | MCR p15, 0, r4, c10, c2, 0 |
| 385 | /*normal memory remap register */ | 532 | /* Normal memory remap register */ |
| 386 | MCR p15, 0, r5, c10, c2, 1 | 533 | MCR p15, 0, r5, c10, c2, 1 |
| 387 | 534 | ||
| 388 | /* Restore cpsr */ | 535 | /* Restore cpsr */ |
| 389 | ldmia r3!,{r4} /*load CPSR from SDRAM*/ | 536 | ldmia r3!,{r4} @ load CPSR from SDRAM |
| 390 | msr cpsr, r4 /*store cpsr */ | 537 | msr cpsr, r4 @ store cpsr |
| 391 | 538 | ||
| 392 | /* Enabling MMU here */ | 539 | /* Enabling MMU here */ |
| 393 | mrc p15, 0, r7, c2, c0, 2 /* Read TTBRControl */ | 540 | mrc p15, 0, r7, c2, c0, 2 @ Read TTBRControl |
| 394 | /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1*/ | 541 | /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1 */ |
| 395 | and r7, #0x7 | 542 | and r7, #0x7 |
| 396 | cmp r7, #0x0 | 543 | cmp r7, #0x0 |
| 397 | beq usettbr0 | 544 | beq usettbr0 |
| 398 | ttbr_error: | 545 | ttbr_error: |
| 399 | /* More work needs to be done to support N[0:2] value other than 0 | 546 | /* |
| 400 | * So looping here so that the error can be detected | 547 | * More work needs to be done to support N[0:2] value other than 0 |
| 401 | */ | 548 | * So looping here so that the error can be detected |
| 549 | */ | ||
| 402 | b ttbr_error | 550 | b ttbr_error |
| 403 | usettbr0: | 551 | usettbr0: |
| 404 | mrc p15, 0, r2, c2, c0, 0 | 552 | mrc p15, 0, r2, c2, c0, 0 |
| @@ -406,21 +554,25 @@ usettbr0: | |||
| 406 | and r2, r5 | 554 | and r2, r5 |
| 407 | mov r4, pc | 555 | mov r4, pc |
| 408 | ldr r5, table_index_mask | 556 | ldr r5, table_index_mask |
| 409 | and r4, r5 /* r4 = 31 to 20 bits of pc */ | 557 | and r4, r5 @ r4 = 31 to 20 bits of pc |
| 410 | /* Extract the value to be written to table entry */ | 558 | /* Extract the value to be written to table entry */ |
| 411 | ldr r1, table_entry | 559 | ldr r1, table_entry |
| 412 | add r1, r1, r4 /* r1 has value to be written to table entry*/ | 560 | /* r1 has the value to be written to table entry*/ |
| 561 | add r1, r1, r4 | ||
| 413 | /* Getting the address of table entry to modify */ | 562 | /* Getting the address of table entry to modify */ |
| 414 | lsr r4, #18 | 563 | lsr r4, #18 |
| 415 | add r2, r4 /* r2 has the location which needs to be modified */ | 564 | /* r2 has the location which needs to be modified */ |
| 565 | add r2, r4 | ||
| 416 | /* Storing previous entry of location being modified */ | 566 | /* Storing previous entry of location being modified */ |
| 417 | ldr r5, scratchpad_base | 567 | ldr r5, scratchpad_base |
| 418 | ldr r4, [r2] | 568 | ldr r4, [r2] |
| 419 | str r4, [r5, #0xC0] | 569 | str r4, [r5, #0xC0] |
| 420 | /* Modify the table entry */ | 570 | /* Modify the table entry */ |
| 421 | str r1, [r2] | 571 | str r1, [r2] |
| 422 | /* Storing address of entry being modified | 572 | /* |
| 423 | * - will be restored after enabling MMU */ | 573 | * Storing address of entry being modified |
| 574 | * - will be restored after enabling MMU | ||
| 575 | */ | ||
| 424 | ldr r5, scratchpad_base | 576 | ldr r5, scratchpad_base |
| 425 | str r2, [r5, #0xC4] | 577 | str r2, [r5, #0xC4] |
| 426 | 578 | ||
| @@ -429,8 +581,11 @@ usettbr0: | |||
| 429 | mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array | 581 | mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array |
| 430 | mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB | 582 | mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB |
| 431 | mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB | 583 | mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB |
| 432 | /* Restore control register but dont enable caches here*/ | 584 | /* |
| 433 | /* Caches will be enabled after restoring MMU table entry */ | 585 | * Restore control register. This enables the MMU. |
| 586 | * The caches and prediction are not enabled here, they | ||
| 587 | * will be enabled after restoring the MMU table entry. | ||
| 588 | */ | ||
| 434 | ldmia r3!, {r4} | 589 | ldmia r3!, {r4} |
| 435 | /* Store previous value of control register in scratchpad */ | 590 | /* Store previous value of control register in scratchpad */ |
| 436 | str r4, [r5, #0xC8] | 591 | str r4, [r5, #0xC8] |
| @@ -438,212 +593,144 @@ usettbr0: | |||
| 438 | and r4, r2 | 593 | and r4, r2 |
| 439 | mcr p15, 0, r4, c1, c0, 0 | 594 | mcr p15, 0, r4, c1, c0, 0 |
| 440 | 595 | ||
| 441 | ldmfd sp!, {r0-r12, pc} @ restore regs and return | 596 | /* |
| 442 | save_context_wfi: | 597 | * ============================== |
| 443 | /*b save_context_wfi*/ @ enable to debug save code | 598 | * == Exit point from OFF mode == |
| 444 | mov r8, r0 /* Store SDRAM address in r8 */ | 599 | * ============================== |
| 445 | mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register | 600 | */ |
| 446 | mov r4, #0x1 @ Number of parameters for restore call | 601 | ldmfd sp!, {r0-r12, pc} @ restore regs and return |
| 447 | stmia r8!, {r4-r5} @ Push parameters for restore call | ||
| 448 | mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register | ||
| 449 | stmia r8!, {r4-r5} @ Push parameters for restore call | ||
| 450 | /* Check what that target sleep state is:stored in r1*/ | ||
| 451 | /* 1 - Only L1 and logic lost */ | ||
| 452 | /* 2 - Only L2 lost */ | ||
| 453 | /* 3 - Both L1 and L2 lost */ | ||
| 454 | cmp r1, #0x2 /* Only L2 lost */ | ||
| 455 | beq clean_l2 | ||
| 456 | cmp r1, #0x1 /* L2 retained */ | ||
| 457 | /* r9 stores whether to clean L2 or not*/ | ||
| 458 | moveq r9, #0x0 /* Dont Clean L2 */ | ||
| 459 | movne r9, #0x1 /* Clean L2 */ | ||
| 460 | l1_logic_lost: | ||
| 461 | /* Store sp and spsr to SDRAM */ | ||
| 462 | mov r4, sp | ||
| 463 | mrs r5, spsr | ||
| 464 | mov r6, lr | ||
| 465 | stmia r8!, {r4-r6} | ||
| 466 | /* Save all ARM registers */ | ||
| 467 | /* Coprocessor access control register */ | ||
| 468 | mrc p15, 0, r6, c1, c0, 2 | ||
| 469 | stmia r8!, {r6} | ||
| 470 | /* TTBR0, TTBR1 and Translation table base control */ | ||
| 471 | mrc p15, 0, r4, c2, c0, 0 | ||
| 472 | mrc p15, 0, r5, c2, c0, 1 | ||
| 473 | mrc p15, 0, r6, c2, c0, 2 | ||
| 474 | stmia r8!, {r4-r6} | ||
| 475 | /* Domain access control register, data fault status register, | ||
| 476 | and instruction fault status register */ | ||
| 477 | mrc p15, 0, r4, c3, c0, 0 | ||
| 478 | mrc p15, 0, r5, c5, c0, 0 | ||
| 479 | mrc p15, 0, r6, c5, c0, 1 | ||
| 480 | stmia r8!, {r4-r6} | ||
| 481 | /* Data aux fault status register, instruction aux fault status, | ||
| 482 | datat fault address register and instruction fault address register*/ | ||
| 483 | mrc p15, 0, r4, c5, c1, 0 | ||
| 484 | mrc p15, 0, r5, c5, c1, 1 | ||
| 485 | mrc p15, 0, r6, c6, c0, 0 | ||
| 486 | mrc p15, 0, r7, c6, c0, 2 | ||
| 487 | stmia r8!, {r4-r7} | ||
| 488 | /* user r/w thread and process ID, user r/o thread and process ID, | ||
| 489 | priv only thread and process ID, cache size selection */ | ||
| 490 | mrc p15, 0, r4, c13, c0, 2 | ||
| 491 | mrc p15, 0, r5, c13, c0, 3 | ||
| 492 | mrc p15, 0, r6, c13, c0, 4 | ||
| 493 | mrc p15, 2, r7, c0, c0, 0 | ||
| 494 | stmia r8!, {r4-r7} | ||
| 495 | /* Data TLB lockdown, instruction TLB lockdown registers */ | ||
| 496 | mrc p15, 0, r5, c10, c0, 0 | ||
| 497 | mrc p15, 0, r6, c10, c0, 1 | ||
| 498 | stmia r8!, {r5-r6} | ||
| 499 | /* Secure or non secure vector base address, FCSE PID, Context PID*/ | ||
| 500 | mrc p15, 0, r4, c12, c0, 0 | ||
| 501 | mrc p15, 0, r5, c13, c0, 0 | ||
| 502 | mrc p15, 0, r6, c13, c0, 1 | ||
| 503 | stmia r8!, {r4-r6} | ||
| 504 | /* Primary remap, normal remap registers */ | ||
| 505 | mrc p15, 0, r4, c10, c2, 0 | ||
| 506 | mrc p15, 0, r5, c10, c2, 1 | ||
| 507 | stmia r8!,{r4-r5} | ||
| 508 | 602 | ||
| 509 | /* Store current cpsr*/ | ||
| 510 | mrs r2, cpsr | ||
| 511 | stmia r8!, {r2} | ||
| 512 | 603 | ||
| 513 | mrc p15, 0, r4, c1, c0, 0 | 604 | /* |
| 514 | /* save control register */ | 605 | * Internal functions |
| 515 | stmia r8!, {r4} | 606 | */ |
| 516 | clean_caches: | ||
| 517 | /* Clean Data or unified cache to POU*/ | ||
| 518 | /* How to invalidate only L1 cache???? - #FIX_ME# */ | ||
| 519 | /* mcr p15, 0, r11, c7, c11, 1 */ | ||
| 520 | cmp r9, #1 /* Check whether L2 inval is required or not*/ | ||
| 521 | bne skip_l2_inval | ||
| 522 | clean_l2: | ||
| 523 | /* read clidr */ | ||
| 524 | mrc p15, 1, r0, c0, c0, 1 | ||
| 525 | /* extract loc from clidr */ | ||
| 526 | ands r3, r0, #0x7000000 | ||
| 527 | /* left align loc bit field */ | ||
| 528 | mov r3, r3, lsr #23 | ||
| 529 | /* if loc is 0, then no need to clean */ | ||
| 530 | beq finished | ||
| 531 | /* start clean at cache level 0 */ | ||
| 532 | mov r10, #0 | ||
| 533 | loop1: | ||
| 534 | /* work out 3x current cache level */ | ||
| 535 | add r2, r10, r10, lsr #1 | ||
| 536 | /* extract cache type bits from clidr*/ | ||
| 537 | mov r1, r0, lsr r2 | ||
| 538 | /* mask of the bits for current cache only */ | ||
| 539 | and r1, r1, #7 | ||
| 540 | /* see what cache we have at this level */ | ||
| 541 | cmp r1, #2 | ||
| 542 | /* skip if no cache, or just i-cache */ | ||
| 543 | blt skip | ||
| 544 | /* select current cache level in cssr */ | ||
| 545 | mcr p15, 2, r10, c0, c0, 0 | ||
| 546 | /* isb to sych the new cssr&csidr */ | ||
| 547 | isb | ||
| 548 | /* read the new csidr */ | ||
| 549 | mrc p15, 1, r1, c0, c0, 0 | ||
| 550 | /* extract the length of the cache lines */ | ||
| 551 | and r2, r1, #7 | ||
| 552 | /* add 4 (line length offset) */ | ||
| 553 | add r2, r2, #4 | ||
| 554 | ldr r4, assoc_mask | ||
| 555 | /* find maximum number on the way size */ | ||
| 556 | ands r4, r4, r1, lsr #3 | ||
| 557 | /* find bit position of way size increment */ | ||
| 558 | clz r5, r4 | ||
| 559 | ldr r7, numset_mask | ||
| 560 | /* extract max number of the index size*/ | ||
| 561 | ands r7, r7, r1, lsr #13 | ||
| 562 | loop2: | ||
| 563 | mov r9, r4 | ||
| 564 | /* create working copy of max way size*/ | ||
| 565 | loop3: | ||
| 566 | /* factor way and cache number into r11 */ | ||
| 567 | orr r11, r10, r9, lsl r5 | ||
| 568 | /* factor index number into r11 */ | ||
| 569 | orr r11, r11, r7, lsl r2 | ||
| 570 | /*clean & invalidate by set/way */ | ||
| 571 | mcr p15, 0, r11, c7, c10, 2 | ||
| 572 | /* decrement the way*/ | ||
| 573 | subs r9, r9, #1 | ||
| 574 | bge loop3 | ||
| 575 | /*decrement the index */ | ||
| 576 | subs r7, r7, #1 | ||
| 577 | bge loop2 | ||
| 578 | skip: | ||
| 579 | add r10, r10, #2 | ||
| 580 | /* increment cache number */ | ||
| 581 | cmp r3, r10 | ||
| 582 | bgt loop1 | ||
| 583 | finished: | ||
| 584 | /*swith back to cache level 0 */ | ||
| 585 | mov r10, #0 | ||
| 586 | /* select current cache level in cssr */ | ||
| 587 | mcr p15, 2, r10, c0, c0, 0 | ||
| 588 | isb | ||
| 589 | skip_l2_inval: | ||
| 590 | /* Data memory barrier and Data sync barrier */ | ||
| 591 | mov r1, #0 | ||
| 592 | mcr p15, 0, r1, c7, c10, 4 | ||
| 593 | mcr p15, 0, r1, c7, c10, 5 | ||
| 594 | 607 | ||
| 595 | wfi @ wait for interrupt | 608 | /* This function implements the erratum ID i443 WA, applies to 34xx >= ES3.0 */ |
| 596 | nop | 609 | .text |
| 597 | nop | 610 | ENTRY(es3_sdrc_fix) |
| 598 | nop | 611 | ldr r4, sdrc_syscfg @ get config addr |
| 599 | nop | 612 | ldr r5, [r4] @ get value |
| 600 | nop | 613 | tst r5, #0x100 @ is part access blocked |
| 601 | nop | 614 | it eq |
| 602 | nop | 615 | biceq r5, r5, #0x100 @ clear bit if set |
| 603 | nop | 616 | str r5, [r4] @ write back change |
| 604 | nop | 617 | ldr r4, sdrc_mr_0 @ get config addr |
| 605 | nop | 618 | ldr r5, [r4] @ get value |
| 606 | bl wait_sdrc_ok | 619 | str r5, [r4] @ write back change |
| 607 | /* restore regs and return */ | 620 | ldr r4, sdrc_emr2_0 @ get config addr |
| 608 | ldmfd sp!, {r0-r12, pc} | 621 | ldr r5, [r4] @ get value |
| 622 | str r5, [r4] @ write back change | ||
| 623 | ldr r4, sdrc_manual_0 @ get config addr | ||
| 624 | mov r5, #0x2 @ autorefresh command | ||
| 625 | str r5, [r4] @ kick off refreshes | ||
| 626 | ldr r4, sdrc_mr_1 @ get config addr | ||
| 627 | ldr r5, [r4] @ get value | ||
| 628 | str r5, [r4] @ write back change | ||
| 629 | ldr r4, sdrc_emr2_1 @ get config addr | ||
| 630 | ldr r5, [r4] @ get value | ||
| 631 | str r5, [r4] @ write back change | ||
| 632 | ldr r4, sdrc_manual_1 @ get config addr | ||
| 633 | mov r5, #0x2 @ autorefresh command | ||
| 634 | str r5, [r4] @ kick off refreshes | ||
| 635 | bx lr | ||
| 636 | |||
| 637 | sdrc_syscfg: | ||
| 638 | .word SDRC_SYSCONFIG_P | ||
| 639 | sdrc_mr_0: | ||
| 640 | .word SDRC_MR_0_P | ||
| 641 | sdrc_emr2_0: | ||
| 642 | .word SDRC_EMR2_0_P | ||
| 643 | sdrc_manual_0: | ||
| 644 | .word SDRC_MANUAL_0_P | ||
| 645 | sdrc_mr_1: | ||
| 646 | .word SDRC_MR_1_P | ||
| 647 | sdrc_emr2_1: | ||
| 648 | .word SDRC_EMR2_1_P | ||
| 649 | sdrc_manual_1: | ||
| 650 | .word SDRC_MANUAL_1_P | ||
| 651 | ENTRY(es3_sdrc_fix_sz) | ||
| 652 | .word . - es3_sdrc_fix | ||
| 653 | |||
| 654 | /* | ||
| 655 | * This function implements the erratum ID i581 WA: | ||
| 656 | * SDRC state restore before accessing the SDRAM | ||
| 657 | * | ||
| 658 | * Only used at return from non-OFF mode. For OFF | ||
| 659 | * mode the ROM code configures the SDRC and | ||
| 660 | * the DPLL before calling the restore code directly | ||
| 661 | * from DDR. | ||
| 662 | */ | ||
| 609 | 663 | ||
| 610 | /* Make sure SDRC accesses are ok */ | 664 | /* Make sure SDRC accesses are ok */ |
| 611 | wait_sdrc_ok: | 665 | wait_sdrc_ok: |
| 612 | ldr r4, cm_idlest1_core | 666 | |
| 613 | ldr r5, [r4] | 667 | /* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this */ |
| 614 | and r5, r5, #0x2 | 668 | ldr r4, cm_idlest_ckgen |
| 615 | cmp r5, #0 | 669 | wait_dpll3_lock: |
| 616 | bne wait_sdrc_ok | 670 | ldr r5, [r4] |
| 617 | ldr r4, sdrc_power | 671 | tst r5, #1 |
| 618 | ldr r5, [r4] | 672 | beq wait_dpll3_lock |
| 619 | bic r5, r5, #0x40 | 673 | |
| 620 | str r5, [r4] | 674 | ldr r4, cm_idlest1_core |
| 675 | wait_sdrc_ready: | ||
| 676 | ldr r5, [r4] | ||
| 677 | tst r5, #0x2 | ||
| 678 | bne wait_sdrc_ready | ||
| 679 | /* allow DLL powerdown upon hw idle req */ | ||
| 680 | ldr r4, sdrc_power | ||
| 681 | ldr r5, [r4] | ||
| 682 | bic r5, r5, #0x40 | ||
| 683 | str r5, [r4] | ||
| 684 | |||
| 685 | is_dll_in_lock_mode: | ||
| 686 | /* Is dll in lock mode? */ | ||
| 687 | ldr r4, sdrc_dlla_ctrl | ||
| 688 | ldr r5, [r4] | ||
| 689 | tst r5, #0x4 | ||
| 690 | bxne lr @ Return if locked | ||
| 691 | /* wait till dll locks */ | ||
| 692 | wait_dll_lock_timed: | ||
| 693 | ldr r4, wait_dll_lock_counter | ||
| 694 | add r4, r4, #1 | ||
| 695 | str r4, wait_dll_lock_counter | ||
| 696 | ldr r4, sdrc_dlla_status | ||
| 697 | /* Wait 20uS for lock */ | ||
| 698 | mov r6, #8 | ||
| 621 | wait_dll_lock: | 699 | wait_dll_lock: |
| 622 | /* Is dll in lock mode? */ | 700 | subs r6, r6, #0x1 |
| 623 | ldr r4, sdrc_dlla_ctrl | 701 | beq kick_dll |
| 624 | ldr r5, [r4] | 702 | ldr r5, [r4] |
| 625 | tst r5, #0x4 | 703 | and r5, r5, #0x4 |
| 626 | bxne lr | 704 | cmp r5, #0x4 |
| 627 | /* wait till dll locks */ | 705 | bne wait_dll_lock |
| 628 | ldr r4, sdrc_dlla_status | 706 | bx lr @ Return when locked |
| 629 | ldr r5, [r4] | 707 | |
| 630 | and r5, r5, #0x4 | 708 | /* disable/reenable DLL if not locked */ |
| 631 | cmp r5, #0x4 | 709 | kick_dll: |
| 632 | bne wait_dll_lock | 710 | ldr r4, sdrc_dlla_ctrl |
| 633 | bx lr | 711 | ldr r5, [r4] |
| 712 | mov r6, r5 | ||
| 713 | bic r6, #(1<<3) @ disable dll | ||
| 714 | str r6, [r4] | ||
| 715 | dsb | ||
| 716 | orr r6, r6, #(1<<3) @ enable dll | ||
| 717 | str r6, [r4] | ||
| 718 | dsb | ||
| 719 | ldr r4, kick_counter | ||
| 720 | add r4, r4, #1 | ||
| 721 | str r4, kick_counter | ||
| 722 | b wait_dll_lock_timed | ||
| 634 | 723 | ||
| 635 | cm_idlest1_core: | 724 | cm_idlest1_core: |
| 636 | .word CM_IDLEST1_CORE_V | 725 | .word CM_IDLEST1_CORE_V |
| 726 | cm_idlest_ckgen: | ||
| 727 | .word CM_IDLEST_CKGEN_V | ||
| 637 | sdrc_dlla_status: | 728 | sdrc_dlla_status: |
| 638 | .word SDRC_DLLA_STATUS_V | 729 | .word SDRC_DLLA_STATUS_V |
| 639 | sdrc_dlla_ctrl: | 730 | sdrc_dlla_ctrl: |
| 640 | .word SDRC_DLLA_CTRL_V | 731 | .word SDRC_DLLA_CTRL_V |
| 641 | pm_prepwstst_core: | ||
| 642 | .word PM_PREPWSTST_CORE_V | ||
| 643 | pm_prepwstst_core_p: | 732 | pm_prepwstst_core_p: |
| 644 | .word PM_PREPWSTST_CORE_P | 733 | .word PM_PREPWSTST_CORE_P |
| 645 | pm_prepwstst_mpu: | ||
| 646 | .word PM_PREPWSTST_MPU_V | ||
| 647 | pm_pwstctrl_mpu: | 734 | pm_pwstctrl_mpu: |
| 648 | .word PM_PWSTCTRL_MPU_P | 735 | .word PM_PWSTCTRL_MPU_P |
| 649 | scratchpad_base: | 736 | scratchpad_base: |
| @@ -651,13 +738,7 @@ scratchpad_base: | |||
| 651 | sram_base: | 738 | sram_base: |
| 652 | .word SRAM_BASE_P + 0x8000 | 739 | .word SRAM_BASE_P + 0x8000 |
| 653 | sdrc_power: | 740 | sdrc_power: |
| 654 | .word SDRC_POWER_V | 741 | .word SDRC_POWER_V |
| 655 | clk_stabilize_delay: | ||
| 656 | .word 0x000001FF | ||
| 657 | assoc_mask: | ||
| 658 | .word 0x3ff | ||
| 659 | numset_mask: | ||
| 660 | .word 0x7fff | ||
| 661 | ttbrbit_mask: | 742 | ttbrbit_mask: |
| 662 | .word 0xFFFFC000 | 743 | .word 0xFFFFC000 |
| 663 | table_index_mask: | 744 | table_index_mask: |
| @@ -668,5 +749,20 @@ cache_pred_disable_mask: | |||
| 668 | .word 0xFFFFE7FB | 749 | .word 0xFFFFE7FB |
| 669 | control_stat: | 750 | control_stat: |
| 670 | .word CONTROL_STAT | 751 | .word CONTROL_STAT |
| 752 | control_mem_rta: | ||
| 753 | .word CONTROL_MEM_RTA_CTRL | ||
| 754 | kernel_flush: | ||
| 755 | .word v7_flush_dcache_all | ||
| 756 | l2dis_3630: | ||
| 757 | .word 0 | ||
| 758 | /* | ||
| 759 | * When exporting to userspace while the counters are in SRAM, | ||
| 760 | * these 2 words need to be at the end to facilitate retrival! | ||
| 761 | */ | ||
| 762 | kick_counter: | ||
| 763 | .word 0 | ||
| 764 | wait_dll_lock_counter: | ||
| 765 | .word 0 | ||
| 766 | |||
| 671 | ENTRY(omap34xx_cpu_suspend_sz) | 767 | ENTRY(omap34xx_cpu_suspend_sz) |
| 672 | .word . - omap34xx_cpu_suspend | 768 | .word . - omap34xx_cpu_suspend |
diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c new file mode 100644 index 000000000000..60e70552b4c5 --- /dev/null +++ b/arch/arm/mach-omap2/smartreflex-class3.c | |||
| @@ -0,0 +1,59 @@ | |||
| 1 | /* | ||
| 2 | * Smart reflex Class 3 specific implementations | ||
| 3 | * | ||
| 4 | * Author: Thara Gopinath <thara@ti.com> | ||
| 5 | * | ||
| 6 | * Copyright (C) 2010 Texas Instruments, Inc. | ||
| 7 | * Thara Gopinath <thara@ti.com> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <plat/smartreflex.h> | ||
| 15 | |||
| 16 | static int sr_class3_enable(struct voltagedomain *voltdm) | ||
| 17 | { | ||
| 18 | unsigned long volt = omap_voltage_get_nom_volt(voltdm); | ||
| 19 | |||
| 20 | if (!volt) { | ||
| 21 | pr_warning("%s: Curr voltage unknown. Cannot enable sr_%s\n", | ||
| 22 | __func__, voltdm->name); | ||
| 23 | return -ENODATA; | ||
| 24 | } | ||
| 25 | |||
| 26 | omap_vp_enable(voltdm); | ||
| 27 | return sr_enable(voltdm, volt); | ||
| 28 | } | ||
| 29 | |||
| 30 | static int sr_class3_disable(struct voltagedomain *voltdm, int is_volt_reset) | ||
| 31 | { | ||
| 32 | omap_vp_disable(voltdm); | ||
| 33 | sr_disable(voltdm); | ||
| 34 | if (is_volt_reset) | ||
| 35 | omap_voltage_reset(voltdm); | ||
| 36 | |||
| 37 | return 0; | ||
| 38 | } | ||
| 39 | |||
| 40 | static int sr_class3_configure(struct voltagedomain *voltdm) | ||
| 41 | { | ||
| 42 | return sr_configure_errgen(voltdm); | ||
| 43 | } | ||
| 44 | |||
| 45 | /* SR class3 structure */ | ||
| 46 | static struct omap_sr_class_data class3_data = { | ||
| 47 | .enable = sr_class3_enable, | ||
| 48 | .disable = sr_class3_disable, | ||
| 49 | .configure = sr_class3_configure, | ||
| 50 | .class_type = SR_CLASS3, | ||
| 51 | }; | ||
| 52 | |||
| 53 | /* Smartreflex Class3 init API to be called from board file */ | ||
| 54 | static int __init sr_class3_init(void) | ||
| 55 | { | ||
| 56 | pr_info("SmartReflex Class3 initialized\n"); | ||
| 57 | return sr_register_class(&class3_data); | ||
| 58 | } | ||
| 59 | late_initcall(sr_class3_init); | ||
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c new file mode 100644 index 000000000000..77ecebf3fae2 --- /dev/null +++ b/arch/arm/mach-omap2/smartreflex.c | |||
| @@ -0,0 +1,1029 @@ | |||
| 1 | /* | ||
| 2 | * OMAP SmartReflex Voltage Control | ||
| 3 | * | ||
| 4 | * Author: Thara Gopinath <thara@ti.com> | ||
| 5 | * | ||
| 6 | * Copyright (C) 2010 Texas Instruments, Inc. | ||
| 7 | * Thara Gopinath <thara@ti.com> | ||
| 8 | * | ||
| 9 | * Copyright (C) 2008 Nokia Corporation | ||
| 10 | * Kalle Jokiniemi | ||
| 11 | * | ||
| 12 | * Copyright (C) 2007 Texas Instruments, Inc. | ||
| 13 | * Lesly A M <x0080970@ti.com> | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License version 2 as | ||
| 17 | * published by the Free Software Foundation. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #include <linux/interrupt.h> | ||
| 21 | #include <linux/clk.h> | ||
| 22 | #include <linux/io.h> | ||
| 23 | #include <linux/debugfs.h> | ||
| 24 | #include <linux/delay.h> | ||
| 25 | #include <linux/slab.h> | ||
| 26 | #include <linux/pm_runtime.h> | ||
| 27 | |||
| 28 | #include <plat/common.h> | ||
| 29 | #include <plat/smartreflex.h> | ||
| 30 | |||
| 31 | #include "pm.h" | ||
| 32 | |||
| 33 | #define SMARTREFLEX_NAME_LEN 16 | ||
| 34 | #define NVALUE_NAME_LEN 40 | ||
| 35 | #define SR_DISABLE_TIMEOUT 200 | ||
| 36 | |||
| 37 | struct omap_sr { | ||
| 38 | int srid; | ||
| 39 | int ip_type; | ||
| 40 | int nvalue_count; | ||
| 41 | bool autocomp_active; | ||
| 42 | u32 clk_length; | ||
| 43 | u32 err_weight; | ||
| 44 | u32 err_minlimit; | ||
| 45 | u32 err_maxlimit; | ||
| 46 | u32 accum_data; | ||
| 47 | u32 senn_avgweight; | ||
| 48 | u32 senp_avgweight; | ||
| 49 | u32 senp_mod; | ||
| 50 | u32 senn_mod; | ||
| 51 | unsigned int irq; | ||
| 52 | void __iomem *base; | ||
| 53 | struct platform_device *pdev; | ||
| 54 | struct list_head node; | ||
| 55 | struct omap_sr_nvalue_table *nvalue_table; | ||
| 56 | struct voltagedomain *voltdm; | ||
| 57 | }; | ||
| 58 | |||
| 59 | /* sr_list contains all the instances of smartreflex module */ | ||
| 60 | static LIST_HEAD(sr_list); | ||
| 61 | |||
| 62 | static struct omap_sr_class_data *sr_class; | ||
| 63 | static struct omap_sr_pmic_data *sr_pmic_data; | ||
| 64 | |||
| 65 | static inline void sr_write_reg(struct omap_sr *sr, unsigned offset, u32 value) | ||
| 66 | { | ||
| 67 | __raw_writel(value, (sr->base + offset)); | ||
| 68 | } | ||
| 69 | |||
| 70 | static inline void sr_modify_reg(struct omap_sr *sr, unsigned offset, u32 mask, | ||
| 71 | u32 value) | ||
| 72 | { | ||
| 73 | u32 reg_val; | ||
| 74 | u32 errconfig_offs = 0, errconfig_mask = 0; | ||
| 75 | |||
| 76 | reg_val = __raw_readl(sr->base + offset); | ||
| 77 | reg_val &= ~mask; | ||
| 78 | |||
| 79 | /* | ||
| 80 | * Smartreflex error config register is special as it contains | ||
| 81 | * certain status bits which if written a 1 into means a clear | ||
| 82 | * of those bits. So in order to make sure no accidental write of | ||
| 83 | * 1 happens to those status bits, do a clear of them in the read | ||
| 84 | * value. This mean this API doesn't rewrite values in these bits | ||
| 85 | * if they are currently set, but does allow the caller to write | ||
| 86 | * those bits. | ||
| 87 | */ | ||
| 88 | if (sr->ip_type == SR_TYPE_V1) { | ||
| 89 | errconfig_offs = ERRCONFIG_V1; | ||
| 90 | errconfig_mask = ERRCONFIG_STATUS_V1_MASK; | ||
| 91 | } else if (sr->ip_type == SR_TYPE_V2) { | ||
| 92 | errconfig_offs = ERRCONFIG_V2; | ||
| 93 | errconfig_mask = ERRCONFIG_VPBOUNDINTST_V2; | ||
| 94 | } | ||
| 95 | |||
| 96 | if (offset == errconfig_offs) | ||
| 97 | reg_val &= ~errconfig_mask; | ||
| 98 | |||
| 99 | reg_val |= value; | ||
| 100 | |||
| 101 | __raw_writel(reg_val, (sr->base + offset)); | ||
| 102 | } | ||
| 103 | |||
| 104 | static inline u32 sr_read_reg(struct omap_sr *sr, unsigned offset) | ||
| 105 | { | ||
| 106 | return __raw_readl(sr->base + offset); | ||
| 107 | } | ||
| 108 | |||
| 109 | static struct omap_sr *_sr_lookup(struct voltagedomain *voltdm) | ||
| 110 | { | ||
| 111 | struct omap_sr *sr_info; | ||
| 112 | |||
| 113 | if (!voltdm) { | ||
| 114 | pr_err("%s: Null voltage domain passed!\n", __func__); | ||
| 115 | return ERR_PTR(-EINVAL); | ||
| 116 | } | ||
| 117 | |||
| 118 | list_for_each_entry(sr_info, &sr_list, node) { | ||
| 119 | if (voltdm == sr_info->voltdm) | ||
| 120 | return sr_info; | ||
| 121 | } | ||
| 122 | |||
| 123 | return ERR_PTR(-ENODATA); | ||
| 124 | } | ||
| 125 | |||
| 126 | static irqreturn_t sr_interrupt(int irq, void *data) | ||
| 127 | { | ||
| 128 | struct omap_sr *sr_info = (struct omap_sr *)data; | ||
| 129 | u32 status = 0; | ||
| 130 | |||
| 131 | if (sr_info->ip_type == SR_TYPE_V1) { | ||
| 132 | /* Read the status bits */ | ||
| 133 | status = sr_read_reg(sr_info, ERRCONFIG_V1); | ||
| 134 | |||
| 135 | /* Clear them by writing back */ | ||
| 136 | sr_write_reg(sr_info, ERRCONFIG_V1, status); | ||
| 137 | } else if (sr_info->ip_type == SR_TYPE_V2) { | ||
| 138 | /* Read the status bits */ | ||
| 139 | sr_read_reg(sr_info, IRQSTATUS); | ||
| 140 | |||
| 141 | /* Clear them by writing back */ | ||
| 142 | sr_write_reg(sr_info, IRQSTATUS, status); | ||
| 143 | } | ||
| 144 | |||
| 145 | if (sr_class->class_type == SR_CLASS2 && sr_class->notify) | ||
| 146 | sr_class->notify(sr_info->voltdm, status); | ||
| 147 | |||
| 148 | return IRQ_HANDLED; | ||
| 149 | } | ||
| 150 | |||
| 151 | static void sr_set_clk_length(struct omap_sr *sr) | ||
| 152 | { | ||
| 153 | struct clk *sys_ck; | ||
| 154 | u32 sys_clk_speed; | ||
| 155 | |||
| 156 | if (cpu_is_omap34xx()) | ||
| 157 | sys_ck = clk_get(NULL, "sys_ck"); | ||
| 158 | else | ||
| 159 | sys_ck = clk_get(NULL, "sys_clkin_ck"); | ||
| 160 | |||
| 161 | if (IS_ERR(sys_ck)) { | ||
| 162 | dev_err(&sr->pdev->dev, "%s: unable to get sys clk\n", | ||
| 163 | __func__); | ||
| 164 | return; | ||
| 165 | } | ||
| 166 | sys_clk_speed = clk_get_rate(sys_ck); | ||
| 167 | clk_put(sys_ck); | ||
| 168 | |||
| 169 | switch (sys_clk_speed) { | ||
| 170 | case 12000000: | ||
| 171 | sr->clk_length = SRCLKLENGTH_12MHZ_SYSCLK; | ||
| 172 | break; | ||
| 173 | case 13000000: | ||
| 174 | sr->clk_length = SRCLKLENGTH_13MHZ_SYSCLK; | ||
| 175 | break; | ||
| 176 | case 19200000: | ||
| 177 | sr->clk_length = SRCLKLENGTH_19MHZ_SYSCLK; | ||
| 178 | break; | ||
| 179 | case 26000000: | ||
| 180 | sr->clk_length = SRCLKLENGTH_26MHZ_SYSCLK; | ||
| 181 | break; | ||
| 182 | case 38400000: | ||
| 183 | sr->clk_length = SRCLKLENGTH_38MHZ_SYSCLK; | ||
| 184 | break; | ||
| 185 | default: | ||
| 186 | dev_err(&sr->pdev->dev, "%s: Invalid sysclk value: %d\n", | ||
| 187 | __func__, sys_clk_speed); | ||
| 188 | break; | ||
| 189 | } | ||
| 190 | } | ||
| 191 | |||
| 192 | static void sr_set_regfields(struct omap_sr *sr) | ||
| 193 | { | ||
| 194 | /* | ||
| 195 | * For time being these values are defined in smartreflex.h | ||
| 196 | * and populated during init. May be they can be moved to board | ||
| 197 | * file or pmic specific data structure. In that case these structure | ||
| 198 | * fields will have to be populated using the pdata or pmic structure. | ||
| 199 | */ | ||
| 200 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) { | ||
| 201 | sr->err_weight = OMAP3430_SR_ERRWEIGHT; | ||
| 202 | sr->err_maxlimit = OMAP3430_SR_ERRMAXLIMIT; | ||
| 203 | sr->accum_data = OMAP3430_SR_ACCUMDATA; | ||
| 204 | if (!(strcmp(sr->voltdm->name, "mpu"))) { | ||
| 205 | sr->senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT; | ||
| 206 | sr->senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT; | ||
| 207 | } else { | ||
| 208 | sr->senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT; | ||
| 209 | sr->senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT; | ||
| 210 | } | ||
| 211 | } | ||
| 212 | } | ||
| 213 | |||
| 214 | static void sr_start_vddautocomp(struct omap_sr *sr) | ||
| 215 | { | ||
| 216 | if (!sr_class || !(sr_class->enable) || !(sr_class->configure)) { | ||
| 217 | dev_warn(&sr->pdev->dev, | ||
| 218 | "%s: smartreflex class driver not registered\n", | ||
| 219 | __func__); | ||
| 220 | return; | ||
| 221 | } | ||
| 222 | |||
| 223 | if (!sr_class->enable(sr->voltdm)) | ||
| 224 | sr->autocomp_active = true; | ||
| 225 | } | ||
| 226 | |||
| 227 | static void sr_stop_vddautocomp(struct omap_sr *sr) | ||
| 228 | { | ||
| 229 | if (!sr_class || !(sr_class->disable)) { | ||
| 230 | dev_warn(&sr->pdev->dev, | ||
| 231 | "%s: smartreflex class driver not registered\n", | ||
| 232 | __func__); | ||
| 233 | return; | ||
| 234 | } | ||
| 235 | |||
| 236 | if (sr->autocomp_active) { | ||
| 237 | sr_class->disable(sr->voltdm, 1); | ||
| 238 | sr->autocomp_active = false; | ||
| 239 | } | ||
| 240 | } | ||
| 241 | |||
| 242 | /* | ||
| 243 | * This function handles the intializations which have to be done | ||
| 244 | * only when both sr device and class driver regiter has | ||
| 245 | * completed. This will be attempted to be called from both sr class | ||
| 246 | * driver register and sr device intializtion API's. Only one call | ||
| 247 | * will ultimately succeed. | ||
| 248 | * | ||
| 249 | * Currenly this function registers interrrupt handler for a particular SR | ||
| 250 | * if smartreflex class driver is already registered and has | ||
| 251 | * requested for interrupts and the SR interrupt line in present. | ||
| 252 | */ | ||
| 253 | static int sr_late_init(struct omap_sr *sr_info) | ||
| 254 | { | ||
| 255 | char *name; | ||
| 256 | struct omap_sr_data *pdata = sr_info->pdev->dev.platform_data; | ||
| 257 | struct resource *mem; | ||
| 258 | int ret = 0; | ||
| 259 | |||
| 260 | if (sr_class->class_type == SR_CLASS2 && | ||
| 261 | sr_class->notify_flags && sr_info->irq) { | ||
| 262 | |||
| 263 | name = kzalloc(SMARTREFLEX_NAME_LEN + 1, GFP_KERNEL); | ||
| 264 | strcpy(name, "sr_"); | ||
| 265 | strcat(name, sr_info->voltdm->name); | ||
| 266 | ret = request_irq(sr_info->irq, sr_interrupt, | ||
| 267 | 0, name, (void *)sr_info); | ||
| 268 | if (ret) | ||
| 269 | goto error; | ||
| 270 | } | ||
| 271 | |||
| 272 | if (pdata && pdata->enable_on_init) | ||
| 273 | sr_start_vddautocomp(sr_info); | ||
| 274 | |||
| 275 | return ret; | ||
| 276 | |||
| 277 | error: | ||
| 278 | iounmap(sr_info->base); | ||
| 279 | mem = platform_get_resource(sr_info->pdev, IORESOURCE_MEM, 0); | ||
| 280 | release_mem_region(mem->start, resource_size(mem)); | ||
| 281 | list_del(&sr_info->node); | ||
| 282 | dev_err(&sr_info->pdev->dev, "%s: ERROR in registering" | ||
| 283 | "interrupt handler. Smartreflex will" | ||
| 284 | "not function as desired\n", __func__); | ||
| 285 | kfree(sr_info); | ||
| 286 | return ret; | ||
| 287 | } | ||
| 288 | |||
| 289 | static void sr_v1_disable(struct omap_sr *sr) | ||
| 290 | { | ||
| 291 | int timeout = 0; | ||
| 292 | |||
| 293 | /* Enable MCUDisableAcknowledge interrupt */ | ||
| 294 | sr_modify_reg(sr, ERRCONFIG_V1, | ||
| 295 | ERRCONFIG_MCUDISACKINTEN, ERRCONFIG_MCUDISACKINTEN); | ||
| 296 | |||
| 297 | /* SRCONFIG - disable SR */ | ||
| 298 | sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0); | ||
| 299 | |||
| 300 | /* Disable all other SR interrupts and clear the status */ | ||
| 301 | sr_modify_reg(sr, ERRCONFIG_V1, | ||
| 302 | (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN | | ||
| 303 | ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_VPBOUNDINTEN_V1), | ||
| 304 | (ERRCONFIG_MCUACCUMINTST | ERRCONFIG_MCUVALIDINTST | | ||
| 305 | ERRCONFIG_MCUBOUNDINTST | | ||
| 306 | ERRCONFIG_VPBOUNDINTST_V1)); | ||
| 307 | |||
| 308 | /* | ||
| 309 | * Wait for SR to be disabled. | ||
| 310 | * wait until ERRCONFIG.MCUDISACKINTST = 1. Typical latency is 1us. | ||
| 311 | */ | ||
| 312 | omap_test_timeout((sr_read_reg(sr, ERRCONFIG_V1) & | ||
| 313 | ERRCONFIG_MCUDISACKINTST), SR_DISABLE_TIMEOUT, | ||
| 314 | timeout); | ||
| 315 | |||
| 316 | if (timeout >= SR_DISABLE_TIMEOUT) | ||
| 317 | dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n", | ||
| 318 | __func__); | ||
| 319 | |||
| 320 | /* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */ | ||
| 321 | sr_modify_reg(sr, ERRCONFIG_V1, ERRCONFIG_MCUDISACKINTEN, | ||
| 322 | ERRCONFIG_MCUDISACKINTST); | ||
| 323 | } | ||
| 324 | |||
| 325 | static void sr_v2_disable(struct omap_sr *sr) | ||
| 326 | { | ||
| 327 | int timeout = 0; | ||
| 328 | |||
| 329 | /* Enable MCUDisableAcknowledge interrupt */ | ||
| 330 | sr_write_reg(sr, IRQENABLE_SET, IRQENABLE_MCUDISABLEACKINT); | ||
| 331 | |||
| 332 | /* SRCONFIG - disable SR */ | ||
| 333 | sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0); | ||
| 334 | |||
| 335 | /* Disable all other SR interrupts and clear the status */ | ||
| 336 | sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2, | ||
| 337 | ERRCONFIG_VPBOUNDINTST_V2); | ||
| 338 | sr_write_reg(sr, IRQENABLE_CLR, (IRQENABLE_MCUACCUMINT | | ||
| 339 | IRQENABLE_MCUVALIDINT | | ||
| 340 | IRQENABLE_MCUBOUNDSINT)); | ||
| 341 | sr_write_reg(sr, IRQSTATUS, (IRQSTATUS_MCUACCUMINT | | ||
| 342 | IRQSTATUS_MCVALIDINT | | ||
| 343 | IRQSTATUS_MCBOUNDSINT)); | ||
| 344 | |||
| 345 | /* | ||
| 346 | * Wait for SR to be disabled. | ||
| 347 | * wait until IRQSTATUS.MCUDISACKINTST = 1. Typical latency is 1us. | ||
| 348 | */ | ||
| 349 | omap_test_timeout((sr_read_reg(sr, IRQSTATUS) & | ||
| 350 | IRQSTATUS_MCUDISABLEACKINT), SR_DISABLE_TIMEOUT, | ||
| 351 | timeout); | ||
| 352 | |||
| 353 | if (timeout >= SR_DISABLE_TIMEOUT) | ||
| 354 | dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n", | ||
| 355 | __func__); | ||
| 356 | |||
| 357 | /* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */ | ||
| 358 | sr_write_reg(sr, IRQENABLE_CLR, IRQENABLE_MCUDISABLEACKINT); | ||
| 359 | sr_write_reg(sr, IRQSTATUS, IRQSTATUS_MCUDISABLEACKINT); | ||
| 360 | } | ||
| 361 | |||
| 362 | static u32 sr_retrieve_nvalue(struct omap_sr *sr, u32 efuse_offs) | ||
| 363 | { | ||
| 364 | int i; | ||
| 365 | |||
| 366 | if (!sr->nvalue_table) { | ||
| 367 | dev_warn(&sr->pdev->dev, "%s: Missing ntarget value table\n", | ||
| 368 | __func__); | ||
| 369 | return 0; | ||
| 370 | } | ||
| 371 | |||
| 372 | for (i = 0; i < sr->nvalue_count; i++) { | ||
| 373 | if (sr->nvalue_table[i].efuse_offs == efuse_offs) | ||
| 374 | return sr->nvalue_table[i].nvalue; | ||
| 375 | } | ||
| 376 | |||
| 377 | return 0; | ||
| 378 | } | ||
| 379 | |||
| 380 | /* Public Functions */ | ||
| 381 | |||
| 382 | /** | ||
| 383 | * sr_configure_errgen() - Configures the smrtreflex to perform AVS using the | ||
| 384 | * error generator module. | ||
| 385 | * @voltdm: VDD pointer to which the SR module to be configured belongs to. | ||
| 386 | * | ||
| 387 | * This API is to be called from the smartreflex class driver to | ||
| 388 | * configure the error generator module inside the smartreflex module. | ||
| 389 | * SR settings if using the ERROR module inside Smartreflex. | ||
| 390 | * SR CLASS 3 by default uses only the ERROR module where as | ||
| 391 | * SR CLASS 2 can choose between ERROR module and MINMAXAVG | ||
| 392 | * module. Returns 0 on success and error value in case of failure. | ||
| 393 | */ | ||
| 394 | int sr_configure_errgen(struct voltagedomain *voltdm) | ||
| 395 | { | ||
| 396 | u32 sr_config, sr_errconfig, errconfig_offs, vpboundint_en; | ||
| 397 | u32 vpboundint_st, senp_en = 0, senn_en = 0; | ||
| 398 | u8 senp_shift, senn_shift; | ||
| 399 | struct omap_sr *sr = _sr_lookup(voltdm); | ||
| 400 | |||
| 401 | if (IS_ERR(sr)) { | ||
| 402 | pr_warning("%s: omap_sr struct for sr_%s not found\n", | ||
| 403 | __func__, voltdm->name); | ||
| 404 | return -EINVAL; | ||
| 405 | } | ||
| 406 | |||
| 407 | if (!sr->clk_length) | ||
| 408 | sr_set_clk_length(sr); | ||
| 409 | |||
| 410 | senp_en = sr->senp_mod; | ||
| 411 | senn_en = sr->senn_mod; | ||
| 412 | |||
| 413 | sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) | | ||
| 414 | SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN; | ||
| 415 | |||
| 416 | if (sr->ip_type == SR_TYPE_V1) { | ||
| 417 | sr_config |= SRCONFIG_DELAYCTRL; | ||
| 418 | senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT; | ||
| 419 | senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT; | ||
| 420 | errconfig_offs = ERRCONFIG_V1; | ||
| 421 | vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V1; | ||
| 422 | vpboundint_st = ERRCONFIG_VPBOUNDINTST_V1; | ||
| 423 | } else if (sr->ip_type == SR_TYPE_V2) { | ||
| 424 | senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT; | ||
| 425 | senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT; | ||
| 426 | errconfig_offs = ERRCONFIG_V2; | ||
| 427 | vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V2; | ||
| 428 | vpboundint_st = ERRCONFIG_VPBOUNDINTST_V2; | ||
| 429 | } else { | ||
| 430 | dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex" | ||
| 431 | "module without specifying the ip\n", __func__); | ||
| 432 | return -EINVAL; | ||
| 433 | } | ||
| 434 | |||
| 435 | sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift)); | ||
| 436 | sr_write_reg(sr, SRCONFIG, sr_config); | ||
| 437 | sr_errconfig = (sr->err_weight << ERRCONFIG_ERRWEIGHT_SHIFT) | | ||
| 438 | (sr->err_maxlimit << ERRCONFIG_ERRMAXLIMIT_SHIFT) | | ||
| 439 | (sr->err_minlimit << ERRCONFIG_ERRMINLIMIT_SHIFT); | ||
| 440 | sr_modify_reg(sr, errconfig_offs, (SR_ERRWEIGHT_MASK | | ||
| 441 | SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK), | ||
| 442 | sr_errconfig); | ||
| 443 | |||
| 444 | /* Enabling the interrupts if the ERROR module is used */ | ||
| 445 | sr_modify_reg(sr, errconfig_offs, | ||
| 446 | vpboundint_en, (vpboundint_en | vpboundint_st)); | ||
| 447 | |||
| 448 | return 0; | ||
| 449 | } | ||
| 450 | |||
| 451 | /** | ||
| 452 | * sr_configure_minmax() - Configures the smrtreflex to perform AVS using the | ||
| 453 | * minmaxavg module. | ||
| 454 | * @voltdm: VDD pointer to which the SR module to be configured belongs to. | ||
| 455 | * | ||
| 456 | * This API is to be called from the smartreflex class driver to | ||
| 457 | * configure the minmaxavg module inside the smartreflex module. | ||
| 458 | * SR settings if using the ERROR module inside Smartreflex. | ||
| 459 | * SR CLASS 3 by default uses only the ERROR module where as | ||
| 460 | * SR CLASS 2 can choose between ERROR module and MINMAXAVG | ||
| 461 | * module. Returns 0 on success and error value in case of failure. | ||
| 462 | */ | ||
| 463 | int sr_configure_minmax(struct voltagedomain *voltdm) | ||
| 464 | { | ||
| 465 | u32 sr_config, sr_avgwt; | ||
| 466 | u32 senp_en = 0, senn_en = 0; | ||
| 467 | u8 senp_shift, senn_shift; | ||
| 468 | struct omap_sr *sr = _sr_lookup(voltdm); | ||
| 469 | |||
| 470 | if (IS_ERR(sr)) { | ||
| 471 | pr_warning("%s: omap_sr struct for sr_%s not found\n", | ||
| 472 | __func__, voltdm->name); | ||
| 473 | return -EINVAL; | ||
| 474 | } | ||
| 475 | |||
| 476 | if (!sr->clk_length) | ||
| 477 | sr_set_clk_length(sr); | ||
| 478 | |||
| 479 | senp_en = sr->senp_mod; | ||
| 480 | senn_en = sr->senn_mod; | ||
| 481 | |||
| 482 | sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) | | ||
| 483 | SRCONFIG_SENENABLE | | ||
| 484 | (sr->accum_data << SRCONFIG_ACCUMDATA_SHIFT); | ||
| 485 | |||
| 486 | if (sr->ip_type == SR_TYPE_V1) { | ||
| 487 | sr_config |= SRCONFIG_DELAYCTRL; | ||
| 488 | senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT; | ||
| 489 | senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT; | ||
| 490 | } else if (sr->ip_type == SR_TYPE_V2) { | ||
| 491 | senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT; | ||
| 492 | senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT; | ||
| 493 | } else { | ||
| 494 | dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex" | ||
| 495 | "module without specifying the ip\n", __func__); | ||
| 496 | return -EINVAL; | ||
| 497 | } | ||
| 498 | |||
| 499 | sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift)); | ||
| 500 | sr_write_reg(sr, SRCONFIG, sr_config); | ||
| 501 | sr_avgwt = (sr->senp_avgweight << AVGWEIGHT_SENPAVGWEIGHT_SHIFT) | | ||
| 502 | (sr->senn_avgweight << AVGWEIGHT_SENNAVGWEIGHT_SHIFT); | ||
| 503 | sr_write_reg(sr, AVGWEIGHT, sr_avgwt); | ||
| 504 | |||
| 505 | /* | ||
| 506 | * Enabling the interrupts if MINMAXAVG module is used. | ||
| 507 | * TODO: check if all the interrupts are mandatory | ||
| 508 | */ | ||
| 509 | if (sr->ip_type == SR_TYPE_V1) { | ||
| 510 | sr_modify_reg(sr, ERRCONFIG_V1, | ||
| 511 | (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN | | ||
| 512 | ERRCONFIG_MCUBOUNDINTEN), | ||
| 513 | (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUACCUMINTST | | ||
| 514 | ERRCONFIG_MCUVALIDINTEN | ERRCONFIG_MCUVALIDINTST | | ||
| 515 | ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_MCUBOUNDINTST)); | ||
| 516 | } else if (sr->ip_type == SR_TYPE_V2) { | ||
| 517 | sr_write_reg(sr, IRQSTATUS, | ||
| 518 | IRQSTATUS_MCUACCUMINT | IRQSTATUS_MCVALIDINT | | ||
| 519 | IRQSTATUS_MCBOUNDSINT | IRQSTATUS_MCUDISABLEACKINT); | ||
| 520 | sr_write_reg(sr, IRQENABLE_SET, | ||
| 521 | IRQENABLE_MCUACCUMINT | IRQENABLE_MCUVALIDINT | | ||
| 522 | IRQENABLE_MCUBOUNDSINT | IRQENABLE_MCUDISABLEACKINT); | ||
| 523 | } | ||
| 524 | |||
| 525 | return 0; | ||
| 526 | } | ||
| 527 | |||
| 528 | /** | ||
| 529 | * sr_enable() - Enables the smartreflex module. | ||
| 530 | * @voltdm: VDD pointer to which the SR module to be configured belongs to. | ||
| 531 | * @volt: The voltage at which the Voltage domain associated with | ||
| 532 | * the smartreflex module is operating at. | ||
| 533 | * This is required only to program the correct Ntarget value. | ||
| 534 | * | ||
| 535 | * This API is to be called from the smartreflex class driver to | ||
| 536 | * enable a smartreflex module. Returns 0 on success. Returns error | ||
| 537 | * value if the voltage passed is wrong or if ntarget value is wrong. | ||
| 538 | */ | ||
| 539 | int sr_enable(struct voltagedomain *voltdm, unsigned long volt) | ||
| 540 | { | ||
| 541 | u32 nvalue_reciprocal; | ||
| 542 | struct omap_volt_data *volt_data; | ||
| 543 | struct omap_sr *sr = _sr_lookup(voltdm); | ||
| 544 | int ret; | ||
| 545 | |||
| 546 | if (IS_ERR(sr)) { | ||
| 547 | pr_warning("%s: omap_sr struct for sr_%s not found\n", | ||
| 548 | __func__, voltdm->name); | ||
| 549 | return -EINVAL; | ||
| 550 | } | ||
| 551 | |||
| 552 | volt_data = omap_voltage_get_voltdata(sr->voltdm, volt); | ||
| 553 | |||
| 554 | if (IS_ERR(volt_data)) { | ||
| 555 | dev_warn(&sr->pdev->dev, "%s: Unable to get voltage table" | ||
| 556 | "for nominal voltage %ld\n", __func__, volt); | ||
| 557 | return -ENODATA; | ||
| 558 | } | ||
| 559 | |||
| 560 | nvalue_reciprocal = sr_retrieve_nvalue(sr, volt_data->sr_efuse_offs); | ||
| 561 | |||
| 562 | if (!nvalue_reciprocal) { | ||
| 563 | dev_warn(&sr->pdev->dev, "%s: NVALUE = 0 at voltage %ld\n", | ||
| 564 | __func__, volt); | ||
| 565 | return -ENODATA; | ||
| 566 | } | ||
| 567 | |||
| 568 | /* errminlimit is opp dependent and hence linked to voltage */ | ||
| 569 | sr->err_minlimit = volt_data->sr_errminlimit; | ||
| 570 | |||
| 571 | pm_runtime_get_sync(&sr->pdev->dev); | ||
| 572 | |||
| 573 | /* Check if SR is already enabled. If yes do nothing */ | ||
| 574 | if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE) | ||
| 575 | return 0; | ||
| 576 | |||
| 577 | /* Configure SR */ | ||
| 578 | ret = sr_class->configure(voltdm); | ||
| 579 | if (ret) | ||
| 580 | return ret; | ||
| 581 | |||
| 582 | sr_write_reg(sr, NVALUERECIPROCAL, nvalue_reciprocal); | ||
| 583 | |||
| 584 | /* SRCONFIG - enable SR */ | ||
| 585 | sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE); | ||
| 586 | return 0; | ||
| 587 | } | ||
| 588 | |||
| 589 | /** | ||
| 590 | * sr_disable() - Disables the smartreflex module. | ||
| 591 | * @voltdm: VDD pointer to which the SR module to be configured belongs to. | ||
| 592 | * | ||
| 593 | * This API is to be called from the smartreflex class driver to | ||
| 594 | * disable a smartreflex module. | ||
| 595 | */ | ||
| 596 | void sr_disable(struct voltagedomain *voltdm) | ||
| 597 | { | ||
| 598 | struct omap_sr *sr = _sr_lookup(voltdm); | ||
| 599 | |||
| 600 | if (IS_ERR(sr)) { | ||
| 601 | pr_warning("%s: omap_sr struct for sr_%s not found\n", | ||
| 602 | __func__, voltdm->name); | ||
| 603 | return; | ||
| 604 | } | ||
| 605 | |||
| 606 | /* Check if SR clocks are already disabled. If yes do nothing */ | ||
| 607 | if (pm_runtime_suspended(&sr->pdev->dev)) | ||
| 608 | return; | ||
| 609 | |||
| 610 | /* | ||
| 611 | * Disable SR if only it is indeed enabled. Else just | ||
| 612 | * disable the clocks. | ||
| 613 | */ | ||
| 614 | if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE) { | ||
| 615 | if (sr->ip_type == SR_TYPE_V1) | ||
| 616 | sr_v1_disable(sr); | ||
| 617 | else if (sr->ip_type == SR_TYPE_V2) | ||
| 618 | sr_v2_disable(sr); | ||
| 619 | } | ||
| 620 | |||
| 621 | pm_runtime_put_sync(&sr->pdev->dev); | ||
| 622 | } | ||
| 623 | |||
| 624 | /** | ||
| 625 | * sr_register_class() - API to register a smartreflex class parameters. | ||
| 626 | * @class_data: The structure containing various sr class specific data. | ||
| 627 | * | ||
| 628 | * This API is to be called by the smartreflex class driver to register itself | ||
| 629 | * with the smartreflex driver during init. Returns 0 on success else the | ||
| 630 | * error value. | ||
| 631 | */ | ||
| 632 | int sr_register_class(struct omap_sr_class_data *class_data) | ||
| 633 | { | ||
| 634 | struct omap_sr *sr_info; | ||
| 635 | |||
| 636 | if (!class_data) { | ||
| 637 | pr_warning("%s:, Smartreflex class data passed is NULL\n", | ||
| 638 | __func__); | ||
| 639 | return -EINVAL; | ||
| 640 | } | ||
| 641 | |||
| 642 | if (sr_class) { | ||
| 643 | pr_warning("%s: Smartreflex class driver already registered\n", | ||
| 644 | __func__); | ||
| 645 | return -EBUSY; | ||
| 646 | } | ||
| 647 | |||
| 648 | sr_class = class_data; | ||
| 649 | |||
| 650 | /* | ||
| 651 | * Call into late init to do intializations that require | ||
| 652 | * both sr driver and sr class driver to be initiallized. | ||
| 653 | */ | ||
| 654 | list_for_each_entry(sr_info, &sr_list, node) | ||
| 655 | sr_late_init(sr_info); | ||
| 656 | |||
| 657 | return 0; | ||
| 658 | } | ||
| 659 | |||
| 660 | /** | ||
| 661 | * omap_sr_enable() - API to enable SR clocks and to call into the | ||
| 662 | * registered smartreflex class enable API. | ||
| 663 | * @voltdm: VDD pointer to which the SR module to be configured belongs to. | ||
| 664 | * | ||
| 665 | * This API is to be called from the kernel in order to enable | ||
| 666 | * a particular smartreflex module. This API will do the initial | ||
| 667 | * configurations to turn on the smartreflex module and in turn call | ||
| 668 | * into the registered smartreflex class enable API. | ||
| 669 | */ | ||
| 670 | void omap_sr_enable(struct voltagedomain *voltdm) | ||
| 671 | { | ||
| 672 | struct omap_sr *sr = _sr_lookup(voltdm); | ||
| 673 | |||
| 674 | if (IS_ERR(sr)) { | ||
| 675 | pr_warning("%s: omap_sr struct for sr_%s not found\n", | ||
| 676 | __func__, voltdm->name); | ||
| 677 | return; | ||
| 678 | } | ||
| 679 | |||
| 680 | if (!sr->autocomp_active) | ||
| 681 | return; | ||
| 682 | |||
| 683 | if (!sr_class || !(sr_class->enable) || !(sr_class->configure)) { | ||
| 684 | dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not" | ||
| 685 | "registered\n", __func__); | ||
| 686 | return; | ||
| 687 | } | ||
| 688 | |||
| 689 | sr_class->enable(voltdm); | ||
| 690 | } | ||
| 691 | |||
| 692 | /** | ||
| 693 | * omap_sr_disable() - API to disable SR without resetting the voltage | ||
| 694 | * processor voltage | ||
| 695 | * @voltdm: VDD pointer to which the SR module to be configured belongs to. | ||
| 696 | * | ||
| 697 | * This API is to be called from the kernel in order to disable | ||
| 698 | * a particular smartreflex module. This API will in turn call | ||
| 699 | * into the registered smartreflex class disable API. This API will tell | ||
| 700 | * the smartreflex class disable not to reset the VP voltage after | ||
| 701 | * disabling smartreflex. | ||
| 702 | */ | ||
| 703 | void omap_sr_disable(struct voltagedomain *voltdm) | ||
| 704 | { | ||
| 705 | struct omap_sr *sr = _sr_lookup(voltdm); | ||
| 706 | |||
| 707 | if (IS_ERR(sr)) { | ||
| 708 | pr_warning("%s: omap_sr struct for sr_%s not found\n", | ||
| 709 | __func__, voltdm->name); | ||
| 710 | return; | ||
| 711 | } | ||
| 712 | |||
| 713 | if (!sr->autocomp_active) | ||
| 714 | return; | ||
| 715 | |||
| 716 | if (!sr_class || !(sr_class->disable)) { | ||
| 717 | dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not" | ||
| 718 | "registered\n", __func__); | ||
| 719 | return; | ||
| 720 | } | ||
| 721 | |||
| 722 | sr_class->disable(voltdm, 0); | ||
| 723 | } | ||
| 724 | |||
| 725 | /** | ||
| 726 | * omap_sr_disable_reset_volt() - API to disable SR and reset the | ||
| 727 | * voltage processor voltage | ||
| 728 | * @voltdm: VDD pointer to which the SR module to be configured belongs to. | ||
| 729 | * | ||
| 730 | * This API is to be called from the kernel in order to disable | ||
| 731 | * a particular smartreflex module. This API will in turn call | ||
| 732 | * into the registered smartreflex class disable API. This API will tell | ||
| 733 | * the smartreflex class disable to reset the VP voltage after | ||
| 734 | * disabling smartreflex. | ||
| 735 | */ | ||
| 736 | void omap_sr_disable_reset_volt(struct voltagedomain *voltdm) | ||
| 737 | { | ||
| 738 | struct omap_sr *sr = _sr_lookup(voltdm); | ||
| 739 | |||
| 740 | if (IS_ERR(sr)) { | ||
| 741 | pr_warning("%s: omap_sr struct for sr_%s not found\n", | ||
| 742 | __func__, voltdm->name); | ||
| 743 | return; | ||
| 744 | } | ||
| 745 | |||
| 746 | if (!sr->autocomp_active) | ||
| 747 | return; | ||
| 748 | |||
| 749 | if (!sr_class || !(sr_class->disable)) { | ||
| 750 | dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not" | ||
| 751 | "registered\n", __func__); | ||
| 752 | return; | ||
| 753 | } | ||
| 754 | |||
| 755 | sr_class->disable(voltdm, 1); | ||
| 756 | } | ||
| 757 | |||
| 758 | /** | ||
| 759 | * omap_sr_register_pmic() - API to register pmic specific info. | ||
| 760 | * @pmic_data: The structure containing pmic specific data. | ||
| 761 | * | ||
| 762 | * This API is to be called from the PMIC specific code to register with | ||
| 763 | * smartreflex driver pmic specific info. Currently the only info required | ||
| 764 | * is the smartreflex init on the PMIC side. | ||
| 765 | */ | ||
| 766 | void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data) | ||
| 767 | { | ||
| 768 | if (!pmic_data) { | ||
| 769 | pr_warning("%s: Trying to register NULL PMIC data structure" | ||
| 770 | "with smartreflex\n", __func__); | ||
| 771 | return; | ||
| 772 | } | ||
| 773 | |||
| 774 | sr_pmic_data = pmic_data; | ||
| 775 | } | ||
| 776 | |||
| 777 | /* PM Debug Fs enteries to enable disable smartreflex. */ | ||
| 778 | static int omap_sr_autocomp_show(void *data, u64 *val) | ||
| 779 | { | ||
| 780 | struct omap_sr *sr_info = (struct omap_sr *) data; | ||
| 781 | |||
| 782 | if (!sr_info) { | ||
| 783 | pr_warning("%s: omap_sr struct for sr_%s not found\n", | ||
| 784 | __func__, sr_info->voltdm->name); | ||
| 785 | return -EINVAL; | ||
| 786 | } | ||
| 787 | |||
| 788 | *val = sr_info->autocomp_active; | ||
| 789 | |||
| 790 | return 0; | ||
| 791 | } | ||
| 792 | |||
| 793 | static int omap_sr_autocomp_store(void *data, u64 val) | ||
| 794 | { | ||
| 795 | struct omap_sr *sr_info = (struct omap_sr *) data; | ||
| 796 | |||
| 797 | if (!sr_info) { | ||
| 798 | pr_warning("%s: omap_sr struct for sr_%s not found\n", | ||
| 799 | __func__, sr_info->voltdm->name); | ||
| 800 | return -EINVAL; | ||
| 801 | } | ||
| 802 | |||
| 803 | /* Sanity check */ | ||
| 804 | if (val && (val != 1)) { | ||
| 805 | pr_warning("%s: Invalid argument %lld\n", __func__, val); | ||
| 806 | return -EINVAL; | ||
| 807 | } | ||
| 808 | |||
| 809 | if (!val) | ||
| 810 | sr_stop_vddautocomp(sr_info); | ||
| 811 | else | ||
| 812 | sr_start_vddautocomp(sr_info); | ||
| 813 | |||
| 814 | return 0; | ||
| 815 | } | ||
| 816 | |||
| 817 | DEFINE_SIMPLE_ATTRIBUTE(pm_sr_fops, omap_sr_autocomp_show, | ||
| 818 | omap_sr_autocomp_store, "%llu\n"); | ||
| 819 | |||
| 820 | static int __init omap_sr_probe(struct platform_device *pdev) | ||
| 821 | { | ||
| 822 | struct omap_sr *sr_info = kzalloc(sizeof(struct omap_sr), GFP_KERNEL); | ||
| 823 | struct omap_sr_data *pdata = pdev->dev.platform_data; | ||
| 824 | struct resource *mem, *irq; | ||
| 825 | struct dentry *vdd_dbg_dir, *dbg_dir, *nvalue_dir; | ||
| 826 | struct omap_volt_data *volt_data; | ||
| 827 | int i, ret = 0; | ||
| 828 | |||
| 829 | if (!sr_info) { | ||
| 830 | dev_err(&pdev->dev, "%s: unable to allocate sr_info\n", | ||
| 831 | __func__); | ||
| 832 | return -ENOMEM; | ||
| 833 | } | ||
| 834 | |||
| 835 | if (!pdata) { | ||
| 836 | dev_err(&pdev->dev, "%s: platform data missing\n", __func__); | ||
| 837 | return -EINVAL; | ||
| 838 | } | ||
| 839 | |||
| 840 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
| 841 | if (!mem) { | ||
| 842 | dev_err(&pdev->dev, "%s: no mem resource\n", __func__); | ||
| 843 | ret = -ENODEV; | ||
| 844 | goto err_free_devinfo; | ||
| 845 | } | ||
| 846 | |||
| 847 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | ||
| 848 | |||
| 849 | pm_runtime_enable(&pdev->dev); | ||
| 850 | |||
| 851 | sr_info->pdev = pdev; | ||
| 852 | sr_info->srid = pdev->id; | ||
| 853 | sr_info->voltdm = pdata->voltdm; | ||
| 854 | sr_info->nvalue_table = pdata->nvalue_table; | ||
| 855 | sr_info->nvalue_count = pdata->nvalue_count; | ||
| 856 | sr_info->senn_mod = pdata->senn_mod; | ||
| 857 | sr_info->senp_mod = pdata->senp_mod; | ||
| 858 | sr_info->autocomp_active = false; | ||
| 859 | sr_info->ip_type = pdata->ip_type; | ||
| 860 | sr_info->base = ioremap(mem->start, resource_size(mem)); | ||
| 861 | if (!sr_info->base) { | ||
| 862 | dev_err(&pdev->dev, "%s: ioremap fail\n", __func__); | ||
| 863 | ret = -ENOMEM; | ||
| 864 | goto err_release_region; | ||
| 865 | } | ||
| 866 | |||
| 867 | if (irq) | ||
| 868 | sr_info->irq = irq->start; | ||
| 869 | |||
| 870 | sr_set_clk_length(sr_info); | ||
| 871 | sr_set_regfields(sr_info); | ||
| 872 | |||
| 873 | list_add(&sr_info->node, &sr_list); | ||
| 874 | |||
| 875 | /* | ||
| 876 | * Call into late init to do intializations that require | ||
| 877 | * both sr driver and sr class driver to be initiallized. | ||
| 878 | */ | ||
| 879 | if (sr_class) { | ||
| 880 | ret = sr_late_init(sr_info); | ||
| 881 | if (ret) { | ||
| 882 | pr_warning("%s: Error in SR late init\n", __func__); | ||
| 883 | return ret; | ||
| 884 | } | ||
| 885 | } | ||
| 886 | |||
| 887 | dev_info(&pdev->dev, "%s: SmartReflex driver initialized\n", __func__); | ||
| 888 | |||
| 889 | /* | ||
| 890 | * If the voltage domain debugfs directory is not created, do | ||
| 891 | * not try to create rest of the debugfs entries. | ||
| 892 | */ | ||
| 893 | vdd_dbg_dir = omap_voltage_get_dbgdir(sr_info->voltdm); | ||
| 894 | if (!vdd_dbg_dir) | ||
| 895 | return -EINVAL; | ||
| 896 | |||
| 897 | dbg_dir = debugfs_create_dir("smartreflex", vdd_dbg_dir); | ||
| 898 | if (IS_ERR(dbg_dir)) { | ||
| 899 | dev_err(&pdev->dev, "%s: Unable to create debugfs directory\n", | ||
| 900 | __func__); | ||
| 901 | return PTR_ERR(dbg_dir); | ||
| 902 | } | ||
| 903 | |||
| 904 | (void) debugfs_create_file("autocomp", S_IRUGO | S_IWUGO, dbg_dir, | ||
| 905 | (void *)sr_info, &pm_sr_fops); | ||
| 906 | (void) debugfs_create_x32("errweight", S_IRUGO, dbg_dir, | ||
| 907 | &sr_info->err_weight); | ||
| 908 | (void) debugfs_create_x32("errmaxlimit", S_IRUGO, dbg_dir, | ||
| 909 | &sr_info->err_maxlimit); | ||
| 910 | (void) debugfs_create_x32("errminlimit", S_IRUGO, dbg_dir, | ||
| 911 | &sr_info->err_minlimit); | ||
| 912 | |||
| 913 | nvalue_dir = debugfs_create_dir("nvalue", dbg_dir); | ||
| 914 | if (IS_ERR(nvalue_dir)) { | ||
| 915 | dev_err(&pdev->dev, "%s: Unable to create debugfs directory" | ||
| 916 | "for n-values\n", __func__); | ||
| 917 | return PTR_ERR(nvalue_dir); | ||
| 918 | } | ||
| 919 | |||
| 920 | omap_voltage_get_volttable(sr_info->voltdm, &volt_data); | ||
| 921 | if (!volt_data) { | ||
| 922 | dev_warn(&pdev->dev, "%s: No Voltage table for the" | ||
| 923 | " corresponding vdd vdd_%s. Cannot create debugfs" | ||
| 924 | "entries for n-values\n", | ||
| 925 | __func__, sr_info->voltdm->name); | ||
| 926 | return -ENODATA; | ||
| 927 | } | ||
| 928 | |||
| 929 | for (i = 0; i < sr_info->nvalue_count; i++) { | ||
| 930 | char *name; | ||
| 931 | char volt_name[32]; | ||
| 932 | |||
| 933 | name = kzalloc(NVALUE_NAME_LEN + 1, GFP_KERNEL); | ||
| 934 | if (!name) { | ||
| 935 | dev_err(&pdev->dev, "%s: Unable to allocate memory" | ||
| 936 | " for n-value directory name\n", __func__); | ||
| 937 | return -ENOMEM; | ||
| 938 | } | ||
| 939 | |||
| 940 | strcpy(name, "volt_"); | ||
| 941 | sprintf(volt_name, "%d", volt_data[i].volt_nominal); | ||
| 942 | strcat(name, volt_name); | ||
| 943 | (void) debugfs_create_x32(name, S_IRUGO | S_IWUGO, nvalue_dir, | ||
| 944 | &(sr_info->nvalue_table[i].nvalue)); | ||
| 945 | } | ||
| 946 | |||
| 947 | return ret; | ||
| 948 | |||
| 949 | err_release_region: | ||
| 950 | release_mem_region(mem->start, resource_size(mem)); | ||
| 951 | err_free_devinfo: | ||
| 952 | kfree(sr_info); | ||
| 953 | |||
| 954 | return ret; | ||
| 955 | } | ||
| 956 | |||
| 957 | static int __devexit omap_sr_remove(struct platform_device *pdev) | ||
| 958 | { | ||
| 959 | struct omap_sr_data *pdata = pdev->dev.platform_data; | ||
| 960 | struct omap_sr *sr_info; | ||
| 961 | struct resource *mem; | ||
| 962 | |||
| 963 | if (!pdata) { | ||
| 964 | dev_err(&pdev->dev, "%s: platform data missing\n", __func__); | ||
| 965 | return -EINVAL; | ||
| 966 | } | ||
| 967 | |||
| 968 | sr_info = _sr_lookup(pdata->voltdm); | ||
| 969 | if (!sr_info) { | ||
| 970 | dev_warn(&pdev->dev, "%s: omap_sr struct not found\n", | ||
| 971 | __func__); | ||
| 972 | return -EINVAL; | ||
| 973 | } | ||
| 974 | |||
| 975 | if (sr_info->autocomp_active) | ||
| 976 | sr_stop_vddautocomp(sr_info); | ||
| 977 | |||
| 978 | list_del(&sr_info->node); | ||
| 979 | iounmap(sr_info->base); | ||
| 980 | kfree(sr_info); | ||
| 981 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
| 982 | release_mem_region(mem->start, resource_size(mem)); | ||
| 983 | |||
| 984 | return 0; | ||
| 985 | } | ||
| 986 | |||
| 987 | static struct platform_driver smartreflex_driver = { | ||
| 988 | .remove = omap_sr_remove, | ||
| 989 | .driver = { | ||
| 990 | .name = "smartreflex", | ||
| 991 | }, | ||
| 992 | }; | ||
| 993 | |||
| 994 | static int __init sr_init(void) | ||
| 995 | { | ||
| 996 | int ret = 0; | ||
| 997 | |||
| 998 | /* | ||
| 999 | * sr_init is a late init. If by then a pmic specific API is not | ||
| 1000 | * registered either there is no need for anything to be done on | ||
| 1001 | * the PMIC side or somebody has forgotten to register a PMIC | ||
| 1002 | * handler. Warn for the second condition. | ||
| 1003 | */ | ||
| 1004 | if (sr_pmic_data && sr_pmic_data->sr_pmic_init) | ||
| 1005 | sr_pmic_data->sr_pmic_init(); | ||
| 1006 | else | ||
| 1007 | pr_warning("%s: No PMIC hook to init smartreflex\n", __func__); | ||
| 1008 | |||
| 1009 | ret = platform_driver_probe(&smartreflex_driver, omap_sr_probe); | ||
| 1010 | if (ret) { | ||
| 1011 | pr_err("%s: platform driver register failed for SR\n", | ||
| 1012 | __func__); | ||
| 1013 | return ret; | ||
| 1014 | } | ||
| 1015 | |||
| 1016 | return 0; | ||
| 1017 | } | ||
| 1018 | |||
| 1019 | static void __exit sr_exit(void) | ||
| 1020 | { | ||
| 1021 | platform_driver_unregister(&smartreflex_driver); | ||
| 1022 | } | ||
| 1023 | late_initcall(sr_init); | ||
| 1024 | module_exit(sr_exit); | ||
| 1025 | |||
| 1026 | MODULE_DESCRIPTION("OMAP Smartreflex Driver"); | ||
| 1027 | MODULE_LICENSE("GPL"); | ||
| 1028 | MODULE_ALIAS("platform:" DRIVER_NAME); | ||
| 1029 | MODULE_AUTHOR("Texas Instruments Inc"); | ||
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c new file mode 100644 index 000000000000..786d685c09a9 --- /dev/null +++ b/arch/arm/mach-omap2/sr_device.c | |||
| @@ -0,0 +1,146 @@ | |||
| 1 | /* | ||
| 2 | * OMAP3/OMAP4 smartreflex device file | ||
| 3 | * | ||
| 4 | * Author: Thara Gopinath <thara@ti.com> | ||
| 5 | * | ||
| 6 | * Based originally on code from smartreflex.c | ||
| 7 | * Copyright (C) 2010 Texas Instruments, Inc. | ||
| 8 | * Thara Gopinath <thara@ti.com> | ||
| 9 | * | ||
| 10 | * Copyright (C) 2008 Nokia Corporation | ||
| 11 | * Kalle Jokiniemi | ||
| 12 | * | ||
| 13 | * Copyright (C) 2007 Texas Instruments, Inc. | ||
| 14 | * Lesly A M <x0080970@ti.com> | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or modify | ||
| 17 | * it under the terms of the GNU General Public License version 2 as | ||
| 18 | * published by the Free Software Foundation. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include <linux/err.h> | ||
| 22 | #include <linux/slab.h> | ||
| 23 | #include <linux/io.h> | ||
| 24 | |||
| 25 | #include <plat/omap_device.h> | ||
| 26 | #include <plat/smartreflex.h> | ||
| 27 | #include <plat/voltage.h> | ||
| 28 | |||
| 29 | #include "control.h" | ||
| 30 | |||
| 31 | static bool sr_enable_on_init; | ||
| 32 | |||
| 33 | static struct omap_device_pm_latency omap_sr_latency[] = { | ||
| 34 | { | ||
| 35 | .deactivate_func = omap_device_idle_hwmods, | ||
| 36 | .activate_func = omap_device_enable_hwmods, | ||
| 37 | .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST | ||
| 38 | }, | ||
| 39 | }; | ||
| 40 | |||
| 41 | /* Read EFUSE values from control registers for OMAP3430 */ | ||
| 42 | static void __init sr_set_nvalues(struct omap_volt_data *volt_data, | ||
| 43 | struct omap_sr_data *sr_data) | ||
| 44 | { | ||
| 45 | struct omap_sr_nvalue_table *nvalue_table; | ||
| 46 | int i, count = 0; | ||
| 47 | |||
| 48 | while (volt_data[count].volt_nominal) | ||
| 49 | count++; | ||
| 50 | |||
| 51 | nvalue_table = kzalloc(sizeof(struct omap_sr_nvalue_table)*count, | ||
| 52 | GFP_KERNEL); | ||
| 53 | |||
| 54 | for (i = 0; i < count; i++) { | ||
| 55 | u32 v; | ||
| 56 | /* | ||
| 57 | * In OMAP4 the efuse registers are 24 bit aligned. | ||
| 58 | * A __raw_readl will fail for non-32 bit aligned address | ||
| 59 | * and hence the 8-bit read and shift. | ||
| 60 | */ | ||
| 61 | if (cpu_is_omap44xx()) { | ||
| 62 | u16 offset = volt_data[i].sr_efuse_offs; | ||
| 63 | |||
| 64 | v = omap_ctrl_readb(offset) | | ||
| 65 | omap_ctrl_readb(offset + 1) << 8 | | ||
| 66 | omap_ctrl_readb(offset + 2) << 16; | ||
| 67 | } else { | ||
| 68 | v = omap_ctrl_readl(volt_data[i].sr_efuse_offs); | ||
| 69 | } | ||
| 70 | |||
| 71 | nvalue_table[i].efuse_offs = volt_data[i].sr_efuse_offs; | ||
| 72 | nvalue_table[i].nvalue = v; | ||
| 73 | } | ||
| 74 | |||
| 75 | sr_data->nvalue_table = nvalue_table; | ||
| 76 | sr_data->nvalue_count = count; | ||
| 77 | } | ||
| 78 | |||
| 79 | static int sr_dev_init(struct omap_hwmod *oh, void *user) | ||
| 80 | { | ||
| 81 | struct omap_sr_data *sr_data; | ||
| 82 | struct omap_device *od; | ||
| 83 | struct omap_volt_data *volt_data; | ||
| 84 | char *name = "smartreflex"; | ||
| 85 | static int i; | ||
| 86 | |||
| 87 | sr_data = kzalloc(sizeof(struct omap_sr_data), GFP_KERNEL); | ||
| 88 | if (!sr_data) { | ||
| 89 | pr_err("%s: Unable to allocate memory for %s sr_data.Error!\n", | ||
| 90 | __func__, oh->name); | ||
| 91 | return -ENOMEM; | ||
| 92 | } | ||
| 93 | |||
| 94 | if (!oh->vdd_name) { | ||
| 95 | pr_err("%s: No voltage domain specified for %s." | ||
| 96 | "Cannot initialize\n", __func__, oh->name); | ||
| 97 | goto exit; | ||
| 98 | } | ||
| 99 | |||
| 100 | sr_data->ip_type = oh->class->rev; | ||
| 101 | sr_data->senn_mod = 0x1; | ||
| 102 | sr_data->senp_mod = 0x1; | ||
| 103 | |||
| 104 | sr_data->voltdm = omap_voltage_domain_lookup(oh->vdd_name); | ||
| 105 | if (IS_ERR(sr_data->voltdm)) { | ||
| 106 | pr_err("%s: Unable to get voltage domain pointer for VDD %s\n", | ||
| 107 | __func__, oh->vdd_name); | ||
| 108 | goto exit; | ||
| 109 | } | ||
| 110 | |||
| 111 | omap_voltage_get_volttable(sr_data->voltdm, &volt_data); | ||
| 112 | if (!volt_data) { | ||
| 113 | pr_warning("%s: No Voltage table registerd fo VDD%d." | ||
| 114 | "Something really wrong\n\n", __func__, i + 1); | ||
| 115 | goto exit; | ||
| 116 | } | ||
| 117 | |||
| 118 | sr_set_nvalues(volt_data, sr_data); | ||
| 119 | |||
| 120 | sr_data->enable_on_init = sr_enable_on_init; | ||
| 121 | |||
| 122 | od = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data), | ||
| 123 | omap_sr_latency, | ||
| 124 | ARRAY_SIZE(omap_sr_latency), 0); | ||
| 125 | if (IS_ERR(od)) | ||
| 126 | pr_warning("%s: Could not build omap_device for %s: %s.\n\n", | ||
| 127 | __func__, name, oh->name); | ||
| 128 | exit: | ||
| 129 | i++; | ||
| 130 | kfree(sr_data); | ||
| 131 | return 0; | ||
| 132 | } | ||
| 133 | |||
| 134 | /* | ||
| 135 | * API to be called from board files to enable smartreflex | ||
| 136 | * autocompensation at init. | ||
| 137 | */ | ||
| 138 | void __init omap_enable_smartreflex_on_init(void) | ||
| 139 | { | ||
| 140 | sr_enable_on_init = true; | ||
| 141 | } | ||
| 142 | |||
| 143 | int __init omap_devinit_smartreflex(void) | ||
| 144 | { | ||
| 145 | return omap_hwmod_for_each_by_class("smartreflex", sr_dev_init, NULL); | ||
| 146 | } | ||
diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S index 92e6e1a12af8..055310cc77de 100644 --- a/arch/arm/mach-omap2/sram242x.S +++ b/arch/arm/mach-omap2/sram242x.S | |||
| @@ -21,14 +21,20 @@ | |||
| 21 | * along with this program; if not, write to the Free Software | 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 23 | * MA 02111-1307 USA | 23 | * MA 02111-1307 USA |
| 24 | * | ||
| 25 | * Richard Woodruff notes that any changes to this code must be carefully | ||
| 26 | * audited and tested to ensure that they don't cause a TLB miss while | ||
| 27 | * the SDRAM is inaccessible. Such a situation will crash the system | ||
| 28 | * since it will cause the ARM MMU to attempt to walk the page tables. | ||
| 29 | * These crashes may be intermittent. | ||
| 24 | */ | 30 | */ |
| 25 | #include <linux/linkage.h> | 31 | #include <linux/linkage.h> |
| 26 | #include <asm/assembler.h> | 32 | #include <asm/assembler.h> |
| 27 | #include <mach/io.h> | 33 | #include <mach/io.h> |
| 28 | #include <mach/hardware.h> | 34 | #include <mach/hardware.h> |
| 29 | 35 | ||
| 30 | #include "prm.h" | 36 | #include "prm2xxx_3xxx.h" |
| 31 | #include "cm.h" | 37 | #include "cm2xxx_3xxx.h" |
| 32 | #include "sdrc.h" | 38 | #include "sdrc.h" |
| 33 | 39 | ||
| 34 | .text | 40 | .text |
diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S index ab4973695c71..f9007580aea3 100644 --- a/arch/arm/mach-omap2/sram243x.S +++ b/arch/arm/mach-omap2/sram243x.S | |||
| @@ -21,14 +21,20 @@ | |||
| 21 | * along with this program; if not, write to the Free Software | 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 23 | * MA 02111-1307 USA | 23 | * MA 02111-1307 USA |
| 24 | * | ||
| 25 | * Richard Woodruff notes that any changes to this code must be carefully | ||
| 26 | * audited and tested to ensure that they don't cause a TLB miss while | ||
| 27 | * the SDRAM is inaccessible. Such a situation will crash the system | ||
| 28 | * since it will cause the ARM MMU to attempt to walk the page tables. | ||
| 29 | * These crashes may be intermittent. | ||
| 24 | */ | 30 | */ |
| 25 | #include <linux/linkage.h> | 31 | #include <linux/linkage.h> |
| 26 | #include <asm/assembler.h> | 32 | #include <asm/assembler.h> |
| 27 | #include <mach/io.h> | 33 | #include <mach/io.h> |
| 28 | #include <mach/hardware.h> | 34 | #include <mach/hardware.h> |
| 29 | 35 | ||
| 30 | #include "prm.h" | 36 | #include "prm2xxx_3xxx.h" |
| 31 | #include "cm.h" | 37 | #include "cm2xxx_3xxx.h" |
| 32 | #include "sdrc.h" | 38 | #include "sdrc.h" |
| 33 | 39 | ||
| 34 | .text | 40 | .text |
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index 3637274af5be..7f893a29d500 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S | |||
| @@ -32,7 +32,7 @@ | |||
| 32 | #include <mach/io.h> | 32 | #include <mach/io.h> |
| 33 | 33 | ||
| 34 | #include "sdrc.h" | 34 | #include "sdrc.h" |
| 35 | #include "cm.h" | 35 | #include "cm2xxx_3xxx.h" |
| 36 | 36 | ||
| 37 | .text | 37 | .text |
| 38 | 38 | ||
| @@ -104,6 +104,12 @@ | |||
| 104 | * touching the SDRAM. Until that time, users who know that their use case | 104 | * touching the SDRAM. Until that time, users who know that their use case |
| 105 | * can satisfy the above requirement can enable the CONFIG_OMAP3_SDRC_AC_TIMING | 105 | * can satisfy the above requirement can enable the CONFIG_OMAP3_SDRC_AC_TIMING |
| 106 | * option. | 106 | * option. |
| 107 | * | ||
| 108 | * Richard Woodruff notes that any changes to this code must be carefully | ||
| 109 | * audited and tested to ensure that they don't cause a TLB miss while | ||
| 110 | * the SDRAM is inaccessible. Such a situation will crash the system | ||
| 111 | * since it will cause the ARM MMU to attempt to walk the page tables. | ||
| 112 | * These crashes may be intermittent. | ||
| 107 | */ | 113 | */ |
| 108 | ENTRY(omap3_sram_configure_core_dpll) | 114 | ENTRY(omap3_sram_configure_core_dpll) |
| 109 | stmfd sp!, {r1-r12, lr} @ store regs to stack | 115 | stmfd sp!, {r1-r12, lr} @ store regs to stack |
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c index e13c29eecf2b..4e48e786bec7 100644 --- a/arch/arm/mach-omap2/timer-gp.c +++ b/arch/arm/mach-omap2/timer-gp.c | |||
| @@ -195,7 +195,6 @@ static struct clocksource clocksource_gpt = { | |||
| 195 | .rating = 300, | 195 | .rating = 300, |
| 196 | .read = clocksource_read_cycles, | 196 | .read = clocksource_read_cycles, |
| 197 | .mask = CLOCKSOURCE_MASK(32), | 197 | .mask = CLOCKSOURCE_MASK(32), |
| 198 | .shift = 24, | ||
| 199 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 198 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 200 | }; | 199 | }; |
| 201 | 200 | ||
| @@ -203,7 +202,7 @@ static struct clocksource clocksource_gpt = { | |||
| 203 | static void __init omap2_gp_clocksource_init(void) | 202 | static void __init omap2_gp_clocksource_init(void) |
| 204 | { | 203 | { |
| 205 | static struct omap_dm_timer *gpt; | 204 | static struct omap_dm_timer *gpt; |
| 206 | u32 tick_rate, tick_period; | 205 | u32 tick_rate; |
| 207 | static char err1[] __initdata = KERN_ERR | 206 | static char err1[] __initdata = KERN_ERR |
| 208 | "%s: failed to request dm-timer\n"; | 207 | "%s: failed to request dm-timer\n"; |
| 209 | static char err2[] __initdata = KERN_ERR | 208 | static char err2[] __initdata = KERN_ERR |
| @@ -216,13 +215,10 @@ static void __init omap2_gp_clocksource_init(void) | |||
| 216 | 215 | ||
| 217 | omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK); | 216 | omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK); |
| 218 | tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt)); | 217 | tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt)); |
| 219 | tick_period = (tick_rate / HZ) - 1; | ||
| 220 | 218 | ||
| 221 | omap_dm_timer_set_load_start(gpt, 1, 0); | 219 | omap_dm_timer_set_load_start(gpt, 1, 0); |
| 222 | 220 | ||
| 223 | clocksource_gpt.mult = | 221 | if (clocksource_register_hz(&clocksource_gpt, tick_rate)) |
| 224 | clocksource_khz2mult(tick_rate/1000, clocksource_gpt.shift); | ||
| 225 | if (clocksource_register(&clocksource_gpt)) | ||
| 226 | printk(err2, clocksource_gpt.name); | 222 | printk(err2, clocksource_gpt.name); |
| 227 | } | 223 | } |
| 228 | #endif | 224 | #endif |
diff --git a/arch/arm/mach-omap2/usb-ehci.c b/arch/arm/mach-omap2/usb-ehci.c index b11bf385d360..25eeadabc39b 100644 --- a/arch/arm/mach-omap2/usb-ehci.c +++ b/arch/arm/mach-omap2/usb-ehci.c | |||
| @@ -34,22 +34,15 @@ | |||
| 34 | 34 | ||
| 35 | static struct resource ehci_resources[] = { | 35 | static struct resource ehci_resources[] = { |
| 36 | { | 36 | { |
| 37 | .start = OMAP34XX_EHCI_BASE, | ||
| 38 | .end = OMAP34XX_EHCI_BASE + SZ_1K - 1, | ||
| 39 | .flags = IORESOURCE_MEM, | 37 | .flags = IORESOURCE_MEM, |
| 40 | }, | 38 | }, |
| 41 | { | 39 | { |
| 42 | .start = OMAP34XX_UHH_CONFIG_BASE, | ||
| 43 | .end = OMAP34XX_UHH_CONFIG_BASE + SZ_1K - 1, | ||
| 44 | .flags = IORESOURCE_MEM, | 40 | .flags = IORESOURCE_MEM, |
| 45 | }, | 41 | }, |
| 46 | { | 42 | { |
| 47 | .start = OMAP34XX_USBTLL_BASE, | ||
| 48 | .end = OMAP34XX_USBTLL_BASE + SZ_4K - 1, | ||
| 49 | .flags = IORESOURCE_MEM, | 43 | .flags = IORESOURCE_MEM, |
| 50 | }, | 44 | }, |
| 51 | { /* general IRQ */ | 45 | { /* general IRQ */ |
| 52 | .start = INT_34XX_EHCI_IRQ, | ||
| 53 | .flags = IORESOURCE_IRQ, | 46 | .flags = IORESOURCE_IRQ, |
| 54 | } | 47 | } |
| 55 | }; | 48 | }; |
| @@ -214,13 +207,148 @@ static void setup_ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode) | |||
| 214 | return; | 207 | return; |
| 215 | } | 208 | } |
| 216 | 209 | ||
| 210 | static void setup_4430ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode) | ||
| 211 | { | ||
| 212 | switch (port_mode[0]) { | ||
| 213 | case EHCI_HCD_OMAP_MODE_PHY: | ||
| 214 | omap_mux_init_signal("usbb1_ulpiphy_stp", | ||
| 215 | OMAP_PIN_OUTPUT); | ||
| 216 | omap_mux_init_signal("usbb1_ulpiphy_clk", | ||
| 217 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 218 | omap_mux_init_signal("usbb1_ulpiphy_dir", | ||
| 219 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 220 | omap_mux_init_signal("usbb1_ulpiphy_nxt", | ||
| 221 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 222 | omap_mux_init_signal("usbb1_ulpiphy_dat0", | ||
| 223 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 224 | omap_mux_init_signal("usbb1_ulpiphy_dat1", | ||
| 225 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 226 | omap_mux_init_signal("usbb1_ulpiphy_dat2", | ||
| 227 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 228 | omap_mux_init_signal("usbb1_ulpiphy_dat3", | ||
| 229 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 230 | omap_mux_init_signal("usbb1_ulpiphy_dat4", | ||
| 231 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 232 | omap_mux_init_signal("usbb1_ulpiphy_dat5", | ||
| 233 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 234 | omap_mux_init_signal("usbb1_ulpiphy_dat6", | ||
| 235 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 236 | omap_mux_init_signal("usbb1_ulpiphy_dat7", | ||
| 237 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 238 | break; | ||
| 239 | case EHCI_HCD_OMAP_MODE_TLL: | ||
| 240 | omap_mux_init_signal("usbb1_ulpitll_stp", | ||
| 241 | OMAP_PIN_INPUT_PULLUP); | ||
| 242 | omap_mux_init_signal("usbb1_ulpitll_clk", | ||
| 243 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 244 | omap_mux_init_signal("usbb1_ulpitll_dir", | ||
| 245 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 246 | omap_mux_init_signal("usbb1_ulpitll_nxt", | ||
| 247 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 248 | omap_mux_init_signal("usbb1_ulpitll_dat0", | ||
| 249 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 250 | omap_mux_init_signal("usbb1_ulpitll_dat1", | ||
| 251 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 252 | omap_mux_init_signal("usbb1_ulpitll_dat2", | ||
| 253 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 254 | omap_mux_init_signal("usbb1_ulpitll_dat3", | ||
| 255 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 256 | omap_mux_init_signal("usbb1_ulpitll_dat4", | ||
| 257 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 258 | omap_mux_init_signal("usbb1_ulpitll_dat5", | ||
| 259 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 260 | omap_mux_init_signal("usbb1_ulpitll_dat6", | ||
| 261 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 262 | omap_mux_init_signal("usbb1_ulpitll_dat7", | ||
| 263 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 264 | break; | ||
| 265 | case EHCI_HCD_OMAP_MODE_UNKNOWN: | ||
| 266 | default: | ||
| 267 | break; | ||
| 268 | } | ||
| 269 | switch (port_mode[1]) { | ||
| 270 | case EHCI_HCD_OMAP_MODE_PHY: | ||
| 271 | omap_mux_init_signal("usbb2_ulpiphy_stp", | ||
| 272 | OMAP_PIN_OUTPUT); | ||
| 273 | omap_mux_init_signal("usbb2_ulpiphy_clk", | ||
| 274 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 275 | omap_mux_init_signal("usbb2_ulpiphy_dir", | ||
| 276 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 277 | omap_mux_init_signal("usbb2_ulpiphy_nxt", | ||
| 278 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 279 | omap_mux_init_signal("usbb2_ulpiphy_dat0", | ||
| 280 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 281 | omap_mux_init_signal("usbb2_ulpiphy_dat1", | ||
| 282 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 283 | omap_mux_init_signal("usbb2_ulpiphy_dat2", | ||
| 284 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 285 | omap_mux_init_signal("usbb2_ulpiphy_dat3", | ||
| 286 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 287 | omap_mux_init_signal("usbb2_ulpiphy_dat4", | ||
| 288 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 289 | omap_mux_init_signal("usbb2_ulpiphy_dat5", | ||
| 290 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 291 | omap_mux_init_signal("usbb2_ulpiphy_dat6", | ||
| 292 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 293 | omap_mux_init_signal("usbb2_ulpiphy_dat7", | ||
| 294 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 295 | break; | ||
| 296 | case EHCI_HCD_OMAP_MODE_TLL: | ||
| 297 | omap_mux_init_signal("usbb2_ulpitll_stp", | ||
| 298 | OMAP_PIN_INPUT_PULLUP); | ||
| 299 | omap_mux_init_signal("usbb2_ulpitll_clk", | ||
| 300 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 301 | omap_mux_init_signal("usbb2_ulpitll_dir", | ||
| 302 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 303 | omap_mux_init_signal("usbb2_ulpitll_nxt", | ||
| 304 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 305 | omap_mux_init_signal("usbb2_ulpitll_dat0", | ||
| 306 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 307 | omap_mux_init_signal("usbb2_ulpitll_dat1", | ||
| 308 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 309 | omap_mux_init_signal("usbb2_ulpitll_dat2", | ||
| 310 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 311 | omap_mux_init_signal("usbb2_ulpitll_dat3", | ||
| 312 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 313 | omap_mux_init_signal("usbb2_ulpitll_dat4", | ||
| 314 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 315 | omap_mux_init_signal("usbb2_ulpitll_dat5", | ||
| 316 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 317 | omap_mux_init_signal("usbb2_ulpitll_dat6", | ||
| 318 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 319 | omap_mux_init_signal("usbb2_ulpitll_dat7", | ||
| 320 | OMAP_PIN_INPUT_PULLDOWN); | ||
| 321 | break; | ||
| 322 | case EHCI_HCD_OMAP_MODE_UNKNOWN: | ||
| 323 | default: | ||
| 324 | break; | ||
| 325 | } | ||
| 326 | } | ||
| 327 | |||
| 217 | void __init usb_ehci_init(const struct ehci_hcd_omap_platform_data *pdata) | 328 | void __init usb_ehci_init(const struct ehci_hcd_omap_platform_data *pdata) |
| 218 | { | 329 | { |
| 219 | platform_device_add_data(&ehci_device, pdata, sizeof(*pdata)); | 330 | platform_device_add_data(&ehci_device, pdata, sizeof(*pdata)); |
| 220 | 331 | ||
| 221 | /* Setup Pin IO MUX for EHCI */ | 332 | /* Setup Pin IO MUX for EHCI */ |
| 222 | if (cpu_is_omap34xx()) | 333 | if (cpu_is_omap34xx()) { |
| 334 | ehci_resources[0].start = OMAP34XX_EHCI_BASE; | ||
| 335 | ehci_resources[0].end = OMAP34XX_EHCI_BASE + SZ_1K - 1; | ||
| 336 | ehci_resources[1].start = OMAP34XX_UHH_CONFIG_BASE; | ||
| 337 | ehci_resources[1].end = OMAP34XX_UHH_CONFIG_BASE + SZ_1K - 1; | ||
| 338 | ehci_resources[2].start = OMAP34XX_USBTLL_BASE; | ||
| 339 | ehci_resources[2].end = OMAP34XX_USBTLL_BASE + SZ_4K - 1; | ||
| 340 | ehci_resources[3].start = INT_34XX_EHCI_IRQ; | ||
| 223 | setup_ehci_io_mux(pdata->port_mode); | 341 | setup_ehci_io_mux(pdata->port_mode); |
| 342 | } else if (cpu_is_omap44xx()) { | ||
| 343 | ehci_resources[0].start = OMAP44XX_HSUSB_EHCI_BASE; | ||
| 344 | ehci_resources[0].end = OMAP44XX_HSUSB_EHCI_BASE + SZ_1K - 1; | ||
| 345 | ehci_resources[1].start = OMAP44XX_UHH_CONFIG_BASE; | ||
| 346 | ehci_resources[1].end = OMAP44XX_UHH_CONFIG_BASE + SZ_2K - 1; | ||
| 347 | ehci_resources[2].start = OMAP44XX_USBTLL_BASE; | ||
| 348 | ehci_resources[2].end = OMAP44XX_USBTLL_BASE + SZ_4K - 1; | ||
| 349 | ehci_resources[3].start = OMAP44XX_IRQ_EHCI; | ||
| 350 | setup_4430ehci_io_mux(pdata->port_mode); | ||
| 351 | } | ||
| 224 | 352 | ||
| 225 | if (platform_device_register(&ehci_device) < 0) { | 353 | if (platform_device_register(&ehci_device) < 0) { |
| 226 | printk(KERN_ERR "Unable to register HS-USB (EHCI) device\n"); | 354 | printk(KERN_ERR "Unable to register HS-USB (EHCI) device\n"); |
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c index 72605584bfff..5298949d4b11 100644 --- a/arch/arm/mach-omap2/usb-musb.c +++ b/arch/arm/mach-omap2/usb-musb.c | |||
| @@ -30,8 +30,101 @@ | |||
| 30 | #include <mach/irqs.h> | 30 | #include <mach/irqs.h> |
| 31 | #include <mach/am35xx.h> | 31 | #include <mach/am35xx.h> |
| 32 | #include <plat/usb.h> | 32 | #include <plat/usb.h> |
| 33 | #include "control.h" | ||
| 33 | 34 | ||
| 34 | #ifdef CONFIG_USB_MUSB_SOC | 35 | #if defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined (CONFIG_USB_MUSB_AM35X) |
| 36 | |||
| 37 | static void am35x_musb_reset(void) | ||
| 38 | { | ||
| 39 | u32 regval; | ||
| 40 | |||
| 41 | /* Reset the musb interface */ | ||
| 42 | regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); | ||
| 43 | |||
| 44 | regval |= AM35XX_USBOTGSS_SW_RST; | ||
| 45 | omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); | ||
| 46 | |||
| 47 | regval &= ~AM35XX_USBOTGSS_SW_RST; | ||
| 48 | omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); | ||
| 49 | |||
| 50 | regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); | ||
| 51 | } | ||
| 52 | |||
| 53 | static void am35x_musb_phy_power(u8 on) | ||
| 54 | { | ||
| 55 | unsigned long timeout = jiffies + msecs_to_jiffies(100); | ||
| 56 | u32 devconf2; | ||
| 57 | |||
| 58 | if (on) { | ||
| 59 | /* | ||
| 60 | * Start the on-chip PHY and its PLL. | ||
| 61 | */ | ||
| 62 | devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); | ||
| 63 | |||
| 64 | devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN); | ||
| 65 | devconf2 |= CONF2_PHY_PLLON; | ||
| 66 | |||
| 67 | omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); | ||
| 68 | |||
| 69 | pr_info(KERN_INFO "Waiting for PHY clock good...\n"); | ||
| 70 | while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2) | ||
| 71 | & CONF2_PHYCLKGD)) { | ||
| 72 | cpu_relax(); | ||
| 73 | |||
| 74 | if (time_after(jiffies, timeout)) { | ||
| 75 | pr_err(KERN_ERR "musb PHY clock good timed out\n"); | ||
| 76 | break; | ||
| 77 | } | ||
| 78 | } | ||
| 79 | } else { | ||
| 80 | /* | ||
| 81 | * Power down the on-chip PHY. | ||
| 82 | */ | ||
| 83 | devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); | ||
| 84 | |||
| 85 | devconf2 &= ~CONF2_PHY_PLLON; | ||
| 86 | devconf2 |= CONF2_PHYPWRDN | CONF2_OTGPWRDN; | ||
| 87 | omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); | ||
| 88 | } | ||
| 89 | } | ||
| 90 | |||
| 91 | static void am35x_musb_clear_irq(void) | ||
| 92 | { | ||
| 93 | u32 regval; | ||
| 94 | |||
| 95 | regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); | ||
| 96 | regval |= AM35XX_USBOTGSS_INT_CLR; | ||
| 97 | omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR); | ||
| 98 | regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); | ||
| 99 | } | ||
| 100 | |||
| 101 | static void am35x_musb_set_mode(u8 musb_mode) | ||
| 102 | { | ||
| 103 | u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); | ||
| 104 | |||
| 105 | devconf2 &= ~CONF2_OTGMODE; | ||
| 106 | switch (musb_mode) { | ||
| 107 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | ||
| 108 | case MUSB_HOST: /* Force VBUS valid, ID = 0 */ | ||
| 109 | devconf2 |= CONF2_FORCE_HOST; | ||
| 110 | break; | ||
| 111 | #endif | ||
| 112 | #ifdef CONFIG_USB_GADGET_MUSB_HDRC | ||
| 113 | case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */ | ||
| 114 | devconf2 |= CONF2_FORCE_DEVICE; | ||
| 115 | break; | ||
| 116 | #endif | ||
| 117 | #ifdef CONFIG_USB_MUSB_OTG | ||
| 118 | case MUSB_OTG: /* Don't override the VBUS/ID comparators */ | ||
| 119 | devconf2 |= CONF2_NO_OVERRIDE; | ||
| 120 | break; | ||
| 121 | #endif | ||
| 122 | default: | ||
| 123 | pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode); | ||
| 124 | } | ||
| 125 | |||
| 126 | omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); | ||
| 127 | } | ||
| 35 | 128 | ||
| 36 | static struct resource musb_resources[] = { | 129 | static struct resource musb_resources[] = { |
| 37 | [0] = { /* start and end set dynamically */ | 130 | [0] = { /* start and end set dynamically */ |
| @@ -40,10 +133,12 @@ static struct resource musb_resources[] = { | |||
| 40 | [1] = { /* general IRQ */ | 133 | [1] = { /* general IRQ */ |
| 41 | .start = INT_243X_HS_USB_MC, | 134 | .start = INT_243X_HS_USB_MC, |
| 42 | .flags = IORESOURCE_IRQ, | 135 | .flags = IORESOURCE_IRQ, |
| 136 | .name = "mc", | ||
| 43 | }, | 137 | }, |
| 44 | [2] = { /* DMA IRQ */ | 138 | [2] = { /* DMA IRQ */ |
| 45 | .start = INT_243X_HS_USB_DMA, | 139 | .start = INT_243X_HS_USB_DMA, |
| 46 | .flags = IORESOURCE_IRQ, | 140 | .flags = IORESOURCE_IRQ, |
| 141 | .name = "dma", | ||
| 47 | }, | 142 | }, |
| 48 | }; | 143 | }; |
| 49 | 144 | ||
| @@ -75,7 +170,7 @@ static struct musb_hdrc_platform_data musb_plat = { | |||
| 75 | static u64 musb_dmamask = DMA_BIT_MASK(32); | 170 | static u64 musb_dmamask = DMA_BIT_MASK(32); |
| 76 | 171 | ||
| 77 | static struct platform_device musb_device = { | 172 | static struct platform_device musb_device = { |
| 78 | .name = "musb_hdrc", | 173 | .name = "musb-omap2430", |
| 79 | .id = -1, | 174 | .id = -1, |
| 80 | .dev = { | 175 | .dev = { |
| 81 | .dma_mask = &musb_dmamask, | 176 | .dma_mask = &musb_dmamask, |
| @@ -91,8 +186,13 @@ void __init usb_musb_init(struct omap_musb_board_data *board_data) | |||
| 91 | if (cpu_is_omap243x()) { | 186 | if (cpu_is_omap243x()) { |
| 92 | musb_resources[0].start = OMAP243X_HS_BASE; | 187 | musb_resources[0].start = OMAP243X_HS_BASE; |
| 93 | } else if (cpu_is_omap3517() || cpu_is_omap3505()) { | 188 | } else if (cpu_is_omap3517() || cpu_is_omap3505()) { |
| 189 | musb_device.name = "musb-am35x"; | ||
| 94 | musb_resources[0].start = AM35XX_IPSS_USBOTGSS_BASE; | 190 | musb_resources[0].start = AM35XX_IPSS_USBOTGSS_BASE; |
| 95 | musb_resources[1].start = INT_35XX_USBOTG_IRQ; | 191 | musb_resources[1].start = INT_35XX_USBOTG_IRQ; |
| 192 | board_data->set_phy_power = am35x_musb_phy_power; | ||
| 193 | board_data->clear_irq = am35x_musb_clear_irq; | ||
| 194 | board_data->set_mode = am35x_musb_set_mode; | ||
| 195 | board_data->reset = am35x_musb_reset; | ||
| 96 | } else if (cpu_is_omap34xx()) { | 196 | } else if (cpu_is_omap34xx()) { |
| 97 | musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE; | 197 | musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE; |
| 98 | } else if (cpu_is_omap44xx()) { | 198 | } else if (cpu_is_omap44xx()) { |
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c index 64a0112b70a5..8a3c05f3c1d6 100644 --- a/arch/arm/mach-omap2/usb-tusb6010.c +++ b/arch/arm/mach-omap2/usb-tusb6010.c | |||
| @@ -120,8 +120,8 @@ static int tusb_set_sync_mode(unsigned sysclk_ps, unsigned fclk_ps) | |||
| 120 | t.adv_on = next_clk(t.cs_on, t_scsnh_advnh - 7000, fclk_ps); | 120 | t.adv_on = next_clk(t.cs_on, t_scsnh_advnh - 7000, fclk_ps); |
| 121 | 121 | ||
| 122 | /* GPMC_CLK rate = fclk rate / div */ | 122 | /* GPMC_CLK rate = fclk rate / div */ |
| 123 | t.sync_clk = 12 /* 11.1 nsec */; | 123 | t.sync_clk = 11100 /* 11.1 nsec */; |
| 124 | tmp = (t.sync_clk * 1000 + fclk_ps - 1) / fclk_ps; | 124 | tmp = (t.sync_clk + fclk_ps - 1) / fclk_ps; |
| 125 | if (tmp > 4) | 125 | if (tmp > 4) |
| 126 | return -ERANGE; | 126 | return -ERANGE; |
| 127 | if (tmp <= 0) | 127 | if (tmp <= 0) |
| @@ -216,6 +216,7 @@ static struct resource tusb_resources[] = { | |||
| 216 | .flags = IORESOURCE_MEM, | 216 | .flags = IORESOURCE_MEM, |
| 217 | }, | 217 | }, |
| 218 | { /* IRQ */ | 218 | { /* IRQ */ |
| 219 | .name = "mc", | ||
| 219 | .flags = IORESOURCE_IRQ, | 220 | .flags = IORESOURCE_IRQ, |
| 220 | }, | 221 | }, |
| 221 | }; | 222 | }; |
| @@ -223,7 +224,7 @@ static struct resource tusb_resources[] = { | |||
| 223 | static u64 tusb_dmamask = ~(u32)0; | 224 | static u64 tusb_dmamask = ~(u32)0; |
| 224 | 225 | ||
| 225 | static struct platform_device tusb_device = { | 226 | static struct platform_device tusb_device = { |
| 226 | .name = "musb_hdrc", | 227 | .name = "musb-tusb", |
| 227 | .id = -1, | 228 | .id = -1, |
| 228 | .dev = { | 229 | .dev = { |
| 229 | .dma_mask = &tusb_dmamask, | 230 | .dma_mask = &tusb_dmamask, |
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c new file mode 100644 index 000000000000..ed6079c94c57 --- /dev/null +++ b/arch/arm/mach-omap2/voltage.c | |||
| @@ -0,0 +1,1571 @@ | |||
| 1 | /* | ||
| 2 | * OMAP3/OMAP4 Voltage Management Routines | ||
| 3 | * | ||
| 4 | * Author: Thara Gopinath <thara@ti.com> | ||
| 5 | * | ||
| 6 | * Copyright (C) 2007 Texas Instruments, Inc. | ||
| 7 | * Rajendra Nayak <rnayak@ti.com> | ||
| 8 | * Lesly A M <x0080970@ti.com> | ||
| 9 | * | ||
| 10 | * Copyright (C) 2008 Nokia Corporation | ||
| 11 | * Kalle Jokiniemi | ||
| 12 | * | ||
| 13 | * Copyright (C) 2010 Texas Instruments, Inc. | ||
| 14 | * Thara Gopinath <thara@ti.com> | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or modify | ||
| 17 | * it under the terms of the GNU General Public License version 2 as | ||
| 18 | * published by the Free Software Foundation. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include <linux/delay.h> | ||
| 22 | #include <linux/io.h> | ||
| 23 | #include <linux/clk.h> | ||
| 24 | #include <linux/err.h> | ||
| 25 | #include <linux/debugfs.h> | ||
| 26 | #include <linux/slab.h> | ||
| 27 | |||
| 28 | #include <plat/common.h> | ||
| 29 | #include <plat/voltage.h> | ||
| 30 | |||
| 31 | #include "prm-regbits-34xx.h" | ||
| 32 | #include "prm-regbits-44xx.h" | ||
| 33 | #include "prm44xx.h" | ||
| 34 | #include "prcm44xx.h" | ||
| 35 | #include "prminst44xx.h" | ||
| 36 | #include "control.h" | ||
| 37 | |||
| 38 | #define VP_IDLE_TIMEOUT 200 | ||
| 39 | #define VP_TRANXDONE_TIMEOUT 300 | ||
| 40 | #define VOLTAGE_DIR_SIZE 16 | ||
| 41 | |||
| 42 | /* Voltage processor register offsets */ | ||
| 43 | struct vp_reg_offs { | ||
| 44 | u8 vpconfig; | ||
| 45 | u8 vstepmin; | ||
| 46 | u8 vstepmax; | ||
| 47 | u8 vlimitto; | ||
| 48 | u8 vstatus; | ||
| 49 | u8 voltage; | ||
| 50 | }; | ||
| 51 | |||
| 52 | /* Voltage Processor bit field values, shifts and masks */ | ||
| 53 | struct vp_reg_val { | ||
| 54 | /* PRM module */ | ||
| 55 | u16 prm_mod; | ||
| 56 | /* VPx_VPCONFIG */ | ||
| 57 | u32 vpconfig_erroroffset; | ||
| 58 | u16 vpconfig_errorgain; | ||
| 59 | u32 vpconfig_errorgain_mask; | ||
| 60 | u8 vpconfig_errorgain_shift; | ||
| 61 | u32 vpconfig_initvoltage_mask; | ||
| 62 | u8 vpconfig_initvoltage_shift; | ||
| 63 | u32 vpconfig_timeouten; | ||
| 64 | u32 vpconfig_initvdd; | ||
| 65 | u32 vpconfig_forceupdate; | ||
| 66 | u32 vpconfig_vpenable; | ||
| 67 | /* VPx_VSTEPMIN */ | ||
| 68 | u8 vstepmin_stepmin; | ||
| 69 | u16 vstepmin_smpswaittimemin; | ||
| 70 | u8 vstepmin_stepmin_shift; | ||
| 71 | u8 vstepmin_smpswaittimemin_shift; | ||
| 72 | /* VPx_VSTEPMAX */ | ||
| 73 | u8 vstepmax_stepmax; | ||
| 74 | u16 vstepmax_smpswaittimemax; | ||
| 75 | u8 vstepmax_stepmax_shift; | ||
| 76 | u8 vstepmax_smpswaittimemax_shift; | ||
| 77 | /* VPx_VLIMITTO */ | ||
| 78 | u8 vlimitto_vddmin; | ||
| 79 | u8 vlimitto_vddmax; | ||
| 80 | u16 vlimitto_timeout; | ||
| 81 | u8 vlimitto_vddmin_shift; | ||
| 82 | u8 vlimitto_vddmax_shift; | ||
| 83 | u8 vlimitto_timeout_shift; | ||
| 84 | /* PRM_IRQSTATUS*/ | ||
| 85 | u32 tranxdone_status; | ||
| 86 | }; | ||
| 87 | |||
| 88 | /* Voltage controller registers and offsets */ | ||
| 89 | struct vc_reg_info { | ||
| 90 | /* PRM module */ | ||
| 91 | u16 prm_mod; | ||
| 92 | /* VC register offsets */ | ||
| 93 | u8 smps_sa_reg; | ||
| 94 | u8 smps_volra_reg; | ||
| 95 | u8 bypass_val_reg; | ||
| 96 | u8 cmdval_reg; | ||
| 97 | u8 voltsetup_reg; | ||
| 98 | /*VC_SMPS_SA*/ | ||
| 99 | u8 smps_sa_shift; | ||
| 100 | u32 smps_sa_mask; | ||
| 101 | /* VC_SMPS_VOL_RA */ | ||
| 102 | u8 smps_volra_shift; | ||
| 103 | u32 smps_volra_mask; | ||
| 104 | /* VC_BYPASS_VAL */ | ||
| 105 | u8 data_shift; | ||
| 106 | u8 slaveaddr_shift; | ||
| 107 | u8 regaddr_shift; | ||
| 108 | u32 valid; | ||
| 109 | /* VC_CMD_VAL */ | ||
| 110 | u8 cmd_on_shift; | ||
| 111 | u8 cmd_onlp_shift; | ||
| 112 | u8 cmd_ret_shift; | ||
| 113 | u8 cmd_off_shift; | ||
| 114 | u32 cmd_on_mask; | ||
| 115 | /* PRM_VOLTSETUP */ | ||
| 116 | u8 voltsetup_shift; | ||
| 117 | u32 voltsetup_mask; | ||
| 118 | }; | ||
| 119 | |||
| 120 | /** | ||
| 121 | * omap_vdd_info - Per Voltage Domain info | ||
| 122 | * | ||
| 123 | * @volt_data : voltage table having the distinct voltages supported | ||
| 124 | * by the domain and other associated per voltage data. | ||
| 125 | * @pmic_info : pmic specific parameters which should be populted by | ||
| 126 | * the pmic drivers. | ||
| 127 | * @vp_offs : structure containing the offsets for various | ||
| 128 | * vp registers | ||
| 129 | * @vp_reg : the register values, shifts, masks for various | ||
| 130 | * vp registers | ||
| 131 | * @vc_reg : structure containing various various vc registers, | ||
| 132 | * shifts, masks etc. | ||
| 133 | * @voltdm : pointer to the voltage domain structure | ||
| 134 | * @debug_dir : debug directory for this voltage domain. | ||
| 135 | * @curr_volt : current voltage for this vdd. | ||
| 136 | * @ocp_mod : The prm module for accessing the prm irqstatus reg. | ||
| 137 | * @prm_irqst_reg : prm irqstatus register. | ||
| 138 | * @vp_enabled : flag to keep track of whether vp is enabled or not | ||
| 139 | * @volt_scale : API to scale the voltage of the vdd. | ||
| 140 | */ | ||
| 141 | struct omap_vdd_info { | ||
| 142 | struct omap_volt_data *volt_data; | ||
| 143 | struct omap_volt_pmic_info *pmic_info; | ||
| 144 | struct vp_reg_offs vp_offs; | ||
| 145 | struct vp_reg_val vp_reg; | ||
| 146 | struct vc_reg_info vc_reg; | ||
| 147 | struct voltagedomain voltdm; | ||
| 148 | struct dentry *debug_dir; | ||
| 149 | u32 curr_volt; | ||
| 150 | u16 ocp_mod; | ||
| 151 | u8 prm_irqst_reg; | ||
| 152 | bool vp_enabled; | ||
| 153 | u32 (*read_reg) (u16 mod, u8 offset); | ||
| 154 | void (*write_reg) (u32 val, u16 mod, u8 offset); | ||
| 155 | int (*volt_scale) (struct omap_vdd_info *vdd, | ||
| 156 | unsigned long target_volt); | ||
| 157 | }; | ||
| 158 | |||
| 159 | static struct omap_vdd_info *vdd_info; | ||
| 160 | /* | ||
| 161 | * Number of scalable voltage domains. | ||
| 162 | */ | ||
| 163 | static int nr_scalable_vdd; | ||
| 164 | |||
| 165 | /* OMAP3 VDD sturctures */ | ||
| 166 | static struct omap_vdd_info omap3_vdd_info[] = { | ||
| 167 | { | ||
| 168 | .vp_offs = { | ||
| 169 | .vpconfig = OMAP3_PRM_VP1_CONFIG_OFFSET, | ||
| 170 | .vstepmin = OMAP3_PRM_VP1_VSTEPMIN_OFFSET, | ||
| 171 | .vstepmax = OMAP3_PRM_VP1_VSTEPMAX_OFFSET, | ||
| 172 | .vlimitto = OMAP3_PRM_VP1_VLIMITTO_OFFSET, | ||
| 173 | .vstatus = OMAP3_PRM_VP1_STATUS_OFFSET, | ||
| 174 | .voltage = OMAP3_PRM_VP1_VOLTAGE_OFFSET, | ||
| 175 | }, | ||
| 176 | .voltdm = { | ||
| 177 | .name = "mpu", | ||
| 178 | }, | ||
| 179 | }, | ||
| 180 | { | ||
| 181 | .vp_offs = { | ||
| 182 | .vpconfig = OMAP3_PRM_VP2_CONFIG_OFFSET, | ||
| 183 | .vstepmin = OMAP3_PRM_VP2_VSTEPMIN_OFFSET, | ||
| 184 | .vstepmax = OMAP3_PRM_VP2_VSTEPMAX_OFFSET, | ||
| 185 | .vlimitto = OMAP3_PRM_VP2_VLIMITTO_OFFSET, | ||
| 186 | .vstatus = OMAP3_PRM_VP2_STATUS_OFFSET, | ||
| 187 | .voltage = OMAP3_PRM_VP2_VOLTAGE_OFFSET, | ||
| 188 | }, | ||
| 189 | .voltdm = { | ||
| 190 | .name = "core", | ||
| 191 | }, | ||
| 192 | }, | ||
| 193 | }; | ||
| 194 | |||
| 195 | #define OMAP3_NR_SCALABLE_VDD ARRAY_SIZE(omap3_vdd_info) | ||
| 196 | |||
| 197 | /* OMAP4 VDD sturctures */ | ||
| 198 | static struct omap_vdd_info omap4_vdd_info[] = { | ||
| 199 | { | ||
| 200 | .vp_offs = { | ||
| 201 | .vpconfig = OMAP4_PRM_VP_MPU_CONFIG_OFFSET, | ||
| 202 | .vstepmin = OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET, | ||
| 203 | .vstepmax = OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET, | ||
| 204 | .vlimitto = OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET, | ||
| 205 | .vstatus = OMAP4_PRM_VP_MPU_STATUS_OFFSET, | ||
| 206 | .voltage = OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET, | ||
| 207 | }, | ||
| 208 | .voltdm = { | ||
| 209 | .name = "mpu", | ||
| 210 | }, | ||
| 211 | }, | ||
| 212 | { | ||
| 213 | .vp_offs = { | ||
| 214 | .vpconfig = OMAP4_PRM_VP_IVA_CONFIG_OFFSET, | ||
| 215 | .vstepmin = OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET, | ||
| 216 | .vstepmax = OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET, | ||
| 217 | .vlimitto = OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET, | ||
| 218 | .vstatus = OMAP4_PRM_VP_IVA_STATUS_OFFSET, | ||
| 219 | .voltage = OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET, | ||
| 220 | }, | ||
| 221 | .voltdm = { | ||
| 222 | .name = "iva", | ||
| 223 | }, | ||
| 224 | }, | ||
| 225 | { | ||
| 226 | .vp_offs = { | ||
| 227 | .vpconfig = OMAP4_PRM_VP_CORE_CONFIG_OFFSET, | ||
| 228 | .vstepmin = OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET, | ||
| 229 | .vstepmax = OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET, | ||
| 230 | .vlimitto = OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET, | ||
| 231 | .vstatus = OMAP4_PRM_VP_CORE_STATUS_OFFSET, | ||
| 232 | .voltage = OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET, | ||
| 233 | }, | ||
| 234 | .voltdm = { | ||
| 235 | .name = "core", | ||
| 236 | }, | ||
| 237 | }, | ||
| 238 | }; | ||
| 239 | |||
| 240 | #define OMAP4_NR_SCALABLE_VDD ARRAY_SIZE(omap4_vdd_info) | ||
| 241 | |||
| 242 | /* | ||
| 243 | * Structures containing OMAP3430/OMAP3630 voltage supported and various | ||
| 244 | * voltage dependent data for each VDD. | ||
| 245 | */ | ||
| 246 | #define VOLT_DATA_DEFINE(_v_nom, _efuse_offs, _errminlimit, _errgain) \ | ||
| 247 | { \ | ||
| 248 | .volt_nominal = _v_nom, \ | ||
| 249 | .sr_efuse_offs = _efuse_offs, \ | ||
| 250 | .sr_errminlimit = _errminlimit, \ | ||
| 251 | .vp_errgain = _errgain \ | ||
| 252 | } | ||
| 253 | |||
| 254 | /* VDD1 */ | ||
| 255 | static struct omap_volt_data omap34xx_vddmpu_volt_data[] = { | ||
| 256 | VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD1, 0xf4, 0x0c), | ||
| 257 | VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD1, 0xf4, 0x0c), | ||
| 258 | VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD1, 0xf9, 0x18), | ||
| 259 | VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP4_UV, OMAP343X_CONTROL_FUSE_OPP4_VDD1, 0xf9, 0x18), | ||
| 260 | VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP5_UV, OMAP343X_CONTROL_FUSE_OPP5_VDD1, 0xf9, 0x18), | ||
| 261 | VOLT_DATA_DEFINE(0, 0, 0, 0), | ||
| 262 | }; | ||
| 263 | |||
| 264 | static struct omap_volt_data omap36xx_vddmpu_volt_data[] = { | ||
| 265 | VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD1, 0xf4, 0x0c), | ||
| 266 | VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD1, 0xf9, 0x16), | ||
| 267 | VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP120_UV, OMAP3630_CONTROL_FUSE_OPP120_VDD1, 0xfa, 0x23), | ||
| 268 | VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP1G_UV, OMAP3630_CONTROL_FUSE_OPP1G_VDD1, 0xfa, 0x27), | ||
| 269 | VOLT_DATA_DEFINE(0, 0, 0, 0), | ||
| 270 | }; | ||
| 271 | |||
| 272 | /* VDD2 */ | ||
| 273 | static struct omap_volt_data omap34xx_vddcore_volt_data[] = { | ||
| 274 | VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD2, 0xf4, 0x0c), | ||
| 275 | VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD2, 0xf4, 0x0c), | ||
| 276 | VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD2, 0xf9, 0x18), | ||
| 277 | VOLT_DATA_DEFINE(0, 0, 0, 0), | ||
| 278 | }; | ||
| 279 | |||
| 280 | static struct omap_volt_data omap36xx_vddcore_volt_data[] = { | ||
| 281 | VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD2, 0xf4, 0x0c), | ||
| 282 | VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD2, 0xf9, 0x16), | ||
| 283 | VOLT_DATA_DEFINE(0, 0, 0, 0), | ||
| 284 | }; | ||
| 285 | |||
| 286 | /* | ||
| 287 | * Structures containing OMAP4430 voltage supported and various | ||
| 288 | * voltage dependent data for each VDD. | ||
| 289 | */ | ||
| 290 | static struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = { | ||
| 291 | VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c), | ||
| 292 | VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP100_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16), | ||
| 293 | VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23), | ||
| 294 | VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPNITRO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO, 0xfa, 0x27), | ||
| 295 | VOLT_DATA_DEFINE(0, 0, 0, 0), | ||
| 296 | }; | ||
| 297 | |||
| 298 | static struct omap_volt_data omap44xx_vdd_iva_volt_data[] = { | ||
| 299 | VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP50_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c), | ||
| 300 | VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP100_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP100, 0xf9, 0x16), | ||
| 301 | VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO, 0xfa, 0x23), | ||
| 302 | VOLT_DATA_DEFINE(0, 0, 0, 0), | ||
| 303 | }; | ||
| 304 | |||
| 305 | static struct omap_volt_data omap44xx_vdd_core_volt_data[] = { | ||
| 306 | VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP50_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c), | ||
| 307 | VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP100_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP100, 0xf9, 0x16), | ||
| 308 | VOLT_DATA_DEFINE(0, 0, 0, 0), | ||
| 309 | }; | ||
| 310 | |||
| 311 | static struct dentry *voltage_dir; | ||
| 312 | |||
| 313 | /* Init function pointers */ | ||
| 314 | static void (*vc_init) (struct omap_vdd_info *vdd); | ||
| 315 | static int (*vdd_data_configure) (struct omap_vdd_info *vdd); | ||
| 316 | |||
| 317 | static u32 omap3_voltage_read_reg(u16 mod, u8 offset) | ||
| 318 | { | ||
| 319 | return omap2_prm_read_mod_reg(mod, offset); | ||
| 320 | } | ||
| 321 | |||
| 322 | static void omap3_voltage_write_reg(u32 val, u16 mod, u8 offset) | ||
| 323 | { | ||
| 324 | omap2_prm_write_mod_reg(val, mod, offset); | ||
| 325 | } | ||
| 326 | |||
| 327 | static u32 omap4_voltage_read_reg(u16 mod, u8 offset) | ||
| 328 | { | ||
| 329 | return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, | ||
| 330 | mod, offset); | ||
| 331 | } | ||
| 332 | |||
| 333 | static void omap4_voltage_write_reg(u32 val, u16 mod, u8 offset) | ||
| 334 | { | ||
| 335 | omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION, mod, offset); | ||
| 336 | } | ||
| 337 | |||
| 338 | /* Voltage debugfs support */ | ||
| 339 | static int vp_volt_debug_get(void *data, u64 *val) | ||
| 340 | { | ||
| 341 | struct omap_vdd_info *vdd = (struct omap_vdd_info *) data; | ||
| 342 | u8 vsel; | ||
| 343 | |||
| 344 | if (!vdd) { | ||
| 345 | pr_warning("Wrong paramater passed\n"); | ||
| 346 | return -EINVAL; | ||
| 347 | } | ||
| 348 | |||
| 349 | vsel = vdd->read_reg(vdd->vp_reg.prm_mod, vdd->vp_offs.voltage); | ||
| 350 | pr_notice("curr_vsel = %x\n", vsel); | ||
| 351 | |||
| 352 | if (!vdd->pmic_info->vsel_to_uv) { | ||
| 353 | pr_warning("PMIC function to convert vsel to voltage" | ||
| 354 | "in uV not registerd\n"); | ||
| 355 | return -EINVAL; | ||
| 356 | } | ||
| 357 | |||
| 358 | *val = vdd->pmic_info->vsel_to_uv(vsel); | ||
| 359 | return 0; | ||
| 360 | } | ||
| 361 | |||
| 362 | static int nom_volt_debug_get(void *data, u64 *val) | ||
| 363 | { | ||
| 364 | struct omap_vdd_info *vdd = (struct omap_vdd_info *) data; | ||
| 365 | |||
| 366 | if (!vdd) { | ||
| 367 | pr_warning("Wrong paramater passed\n"); | ||
| 368 | return -EINVAL; | ||
| 369 | } | ||
| 370 | |||
| 371 | *val = omap_voltage_get_nom_volt(&vdd->voltdm); | ||
| 372 | |||
| 373 | return 0; | ||
| 374 | } | ||
| 375 | |||
| 376 | DEFINE_SIMPLE_ATTRIBUTE(vp_volt_debug_fops, vp_volt_debug_get, NULL, "%llu\n"); | ||
| 377 | DEFINE_SIMPLE_ATTRIBUTE(nom_volt_debug_fops, nom_volt_debug_get, NULL, | ||
| 378 | "%llu\n"); | ||
| 379 | static void vp_latch_vsel(struct omap_vdd_info *vdd) | ||
| 380 | { | ||
| 381 | u32 vpconfig; | ||
| 382 | u16 mod; | ||
| 383 | unsigned long uvdc; | ||
| 384 | char vsel; | ||
| 385 | |||
| 386 | uvdc = omap_voltage_get_nom_volt(&vdd->voltdm); | ||
| 387 | if (!uvdc) { | ||
| 388 | pr_warning("%s: unable to find current voltage for vdd_%s\n", | ||
| 389 | __func__, vdd->voltdm.name); | ||
| 390 | return; | ||
| 391 | } | ||
| 392 | |||
| 393 | if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) { | ||
| 394 | pr_warning("%s: PMIC function to convert voltage in uV to" | ||
| 395 | " vsel not registered\n", __func__); | ||
| 396 | return; | ||
| 397 | } | ||
| 398 | |||
| 399 | mod = vdd->vp_reg.prm_mod; | ||
| 400 | |||
| 401 | vsel = vdd->pmic_info->uv_to_vsel(uvdc); | ||
| 402 | |||
| 403 | vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig); | ||
| 404 | vpconfig &= ~(vdd->vp_reg.vpconfig_initvoltage_mask | | ||
| 405 | vdd->vp_reg.vpconfig_initvdd); | ||
| 406 | vpconfig |= vsel << vdd->vp_reg.vpconfig_initvoltage_shift; | ||
| 407 | |||
| 408 | vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); | ||
| 409 | |||
| 410 | /* Trigger initVDD value copy to voltage processor */ | ||
| 411 | vdd->write_reg((vpconfig | vdd->vp_reg.vpconfig_initvdd), mod, | ||
| 412 | vdd->vp_offs.vpconfig); | ||
| 413 | |||
| 414 | /* Clear initVDD copy trigger bit */ | ||
| 415 | vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); | ||
| 416 | } | ||
| 417 | |||
| 418 | /* Generic voltage init functions */ | ||
| 419 | static void __init vp_init(struct omap_vdd_info *vdd) | ||
| 420 | { | ||
| 421 | u32 vp_val; | ||
| 422 | u16 mod; | ||
| 423 | |||
| 424 | if (!vdd->read_reg || !vdd->write_reg) { | ||
| 425 | pr_err("%s: No read/write API for accessing vdd_%s regs\n", | ||
| 426 | __func__, vdd->voltdm.name); | ||
| 427 | return; | ||
| 428 | } | ||
| 429 | |||
| 430 | mod = vdd->vp_reg.prm_mod; | ||
| 431 | |||
| 432 | vp_val = vdd->vp_reg.vpconfig_erroroffset | | ||
| 433 | (vdd->vp_reg.vpconfig_errorgain << | ||
| 434 | vdd->vp_reg.vpconfig_errorgain_shift) | | ||
| 435 | vdd->vp_reg.vpconfig_timeouten; | ||
| 436 | vdd->write_reg(vp_val, mod, vdd->vp_offs.vpconfig); | ||
| 437 | |||
| 438 | vp_val = ((vdd->vp_reg.vstepmin_smpswaittimemin << | ||
| 439 | vdd->vp_reg.vstepmin_smpswaittimemin_shift) | | ||
| 440 | (vdd->vp_reg.vstepmin_stepmin << | ||
| 441 | vdd->vp_reg.vstepmin_stepmin_shift)); | ||
| 442 | vdd->write_reg(vp_val, mod, vdd->vp_offs.vstepmin); | ||
| 443 | |||
| 444 | vp_val = ((vdd->vp_reg.vstepmax_smpswaittimemax << | ||
| 445 | vdd->vp_reg.vstepmax_smpswaittimemax_shift) | | ||
| 446 | (vdd->vp_reg.vstepmax_stepmax << | ||
| 447 | vdd->vp_reg.vstepmax_stepmax_shift)); | ||
| 448 | vdd->write_reg(vp_val, mod, vdd->vp_offs.vstepmax); | ||
| 449 | |||
| 450 | vp_val = ((vdd->vp_reg.vlimitto_vddmax << | ||
| 451 | vdd->vp_reg.vlimitto_vddmax_shift) | | ||
| 452 | (vdd->vp_reg.vlimitto_vddmin << | ||
| 453 | vdd->vp_reg.vlimitto_vddmin_shift) | | ||
| 454 | (vdd->vp_reg.vlimitto_timeout << | ||
| 455 | vdd->vp_reg.vlimitto_timeout_shift)); | ||
| 456 | vdd->write_reg(vp_val, mod, vdd->vp_offs.vlimitto); | ||
| 457 | } | ||
| 458 | |||
| 459 | static void __init vdd_debugfs_init(struct omap_vdd_info *vdd) | ||
| 460 | { | ||
| 461 | char *name; | ||
| 462 | |||
| 463 | name = kzalloc(VOLTAGE_DIR_SIZE, GFP_KERNEL); | ||
| 464 | if (!name) { | ||
| 465 | pr_warning("%s: Unable to allocate memory for debugfs" | ||
| 466 | " directory name for vdd_%s", | ||
| 467 | __func__, vdd->voltdm.name); | ||
| 468 | return; | ||
| 469 | } | ||
| 470 | strcpy(name, "vdd_"); | ||
| 471 | strcat(name, vdd->voltdm.name); | ||
| 472 | |||
| 473 | vdd->debug_dir = debugfs_create_dir(name, voltage_dir); | ||
| 474 | if (IS_ERR(vdd->debug_dir)) { | ||
| 475 | pr_warning("%s: Unable to create debugfs directory for" | ||
| 476 | " vdd_%s\n", __func__, vdd->voltdm.name); | ||
| 477 | vdd->debug_dir = NULL; | ||
| 478 | return; | ||
| 479 | } | ||
| 480 | |||
| 481 | (void) debugfs_create_x16("vp_errorgain", S_IRUGO, vdd->debug_dir, | ||
| 482 | &(vdd->vp_reg.vpconfig_errorgain)); | ||
| 483 | (void) debugfs_create_x16("vp_smpswaittimemin", S_IRUGO, | ||
| 484 | vdd->debug_dir, | ||
| 485 | &(vdd->vp_reg.vstepmin_smpswaittimemin)); | ||
| 486 | (void) debugfs_create_x8("vp_stepmin", S_IRUGO, vdd->debug_dir, | ||
| 487 | &(vdd->vp_reg.vstepmin_stepmin)); | ||
| 488 | (void) debugfs_create_x16("vp_smpswaittimemax", S_IRUGO, | ||
| 489 | vdd->debug_dir, | ||
| 490 | &(vdd->vp_reg.vstepmax_smpswaittimemax)); | ||
| 491 | (void) debugfs_create_x8("vp_stepmax", S_IRUGO, vdd->debug_dir, | ||
| 492 | &(vdd->vp_reg.vstepmax_stepmax)); | ||
| 493 | (void) debugfs_create_x8("vp_vddmax", S_IRUGO, vdd->debug_dir, | ||
| 494 | &(vdd->vp_reg.vlimitto_vddmax)); | ||
| 495 | (void) debugfs_create_x8("vp_vddmin", S_IRUGO, vdd->debug_dir, | ||
| 496 | &(vdd->vp_reg.vlimitto_vddmin)); | ||
| 497 | (void) debugfs_create_x16("vp_timeout", S_IRUGO, vdd->debug_dir, | ||
| 498 | &(vdd->vp_reg.vlimitto_timeout)); | ||
| 499 | (void) debugfs_create_file("curr_vp_volt", S_IRUGO, vdd->debug_dir, | ||
| 500 | (void *) vdd, &vp_volt_debug_fops); | ||
| 501 | (void) debugfs_create_file("curr_nominal_volt", S_IRUGO, | ||
| 502 | vdd->debug_dir, (void *) vdd, | ||
| 503 | &nom_volt_debug_fops); | ||
| 504 | } | ||
| 505 | |||
| 506 | /* Voltage scale and accessory APIs */ | ||
| 507 | static int _pre_volt_scale(struct omap_vdd_info *vdd, | ||
| 508 | unsigned long target_volt, u8 *target_vsel, u8 *current_vsel) | ||
| 509 | { | ||
| 510 | struct omap_volt_data *volt_data; | ||
| 511 | u32 vc_cmdval, vp_errgain_val; | ||
| 512 | u16 vp_mod, vc_mod; | ||
| 513 | |||
| 514 | /* Check if suffiecient pmic info is available for this vdd */ | ||
| 515 | if (!vdd->pmic_info) { | ||
| 516 | pr_err("%s: Insufficient pmic info to scale the vdd_%s\n", | ||
| 517 | __func__, vdd->voltdm.name); | ||
| 518 | return -EINVAL; | ||
| 519 | } | ||
| 520 | |||
| 521 | if (!vdd->pmic_info->uv_to_vsel) { | ||
| 522 | pr_err("%s: PMIC function to convert voltage in uV to" | ||
| 523 | "vsel not registered. Hence unable to scale voltage" | ||
| 524 | "for vdd_%s\n", __func__, vdd->voltdm.name); | ||
| 525 | return -ENODATA; | ||
| 526 | } | ||
| 527 | |||
| 528 | if (!vdd->read_reg || !vdd->write_reg) { | ||
| 529 | pr_err("%s: No read/write API for accessing vdd_%s regs\n", | ||
| 530 | __func__, vdd->voltdm.name); | ||
| 531 | return -EINVAL; | ||
| 532 | } | ||
| 533 | |||
| 534 | vp_mod = vdd->vp_reg.prm_mod; | ||
| 535 | vc_mod = vdd->vc_reg.prm_mod; | ||
| 536 | |||
| 537 | /* Get volt_data corresponding to target_volt */ | ||
| 538 | volt_data = omap_voltage_get_voltdata(&vdd->voltdm, target_volt); | ||
| 539 | if (IS_ERR(volt_data)) | ||
| 540 | volt_data = NULL; | ||
| 541 | |||
| 542 | *target_vsel = vdd->pmic_info->uv_to_vsel(target_volt); | ||
| 543 | *current_vsel = vdd->read_reg(vp_mod, vdd->vp_offs.voltage); | ||
| 544 | |||
| 545 | /* Setting the ON voltage to the new target voltage */ | ||
| 546 | vc_cmdval = vdd->read_reg(vc_mod, vdd->vc_reg.cmdval_reg); | ||
| 547 | vc_cmdval &= ~vdd->vc_reg.cmd_on_mask; | ||
| 548 | vc_cmdval |= (*target_vsel << vdd->vc_reg.cmd_on_shift); | ||
| 549 | vdd->write_reg(vc_cmdval, vc_mod, vdd->vc_reg.cmdval_reg); | ||
| 550 | |||
| 551 | /* Setting vp errorgain based on the voltage */ | ||
| 552 | if (volt_data) { | ||
| 553 | vp_errgain_val = vdd->read_reg(vp_mod, | ||
| 554 | vdd->vp_offs.vpconfig); | ||
| 555 | vdd->vp_reg.vpconfig_errorgain = volt_data->vp_errgain; | ||
| 556 | vp_errgain_val &= ~vdd->vp_reg.vpconfig_errorgain_mask; | ||
| 557 | vp_errgain_val |= vdd->vp_reg.vpconfig_errorgain << | ||
| 558 | vdd->vp_reg.vpconfig_errorgain_shift; | ||
| 559 | vdd->write_reg(vp_errgain_val, vp_mod, | ||
| 560 | vdd->vp_offs.vpconfig); | ||
| 561 | } | ||
| 562 | |||
| 563 | return 0; | ||
| 564 | } | ||
| 565 | |||
| 566 | static void _post_volt_scale(struct omap_vdd_info *vdd, | ||
| 567 | unsigned long target_volt, u8 target_vsel, u8 current_vsel) | ||
| 568 | { | ||
| 569 | u32 smps_steps = 0, smps_delay = 0; | ||
| 570 | |||
| 571 | smps_steps = abs(target_vsel - current_vsel); | ||
| 572 | /* SMPS slew rate / step size. 2us added as buffer. */ | ||
| 573 | smps_delay = ((smps_steps * vdd->pmic_info->step_size) / | ||
| 574 | vdd->pmic_info->slew_rate) + 2; | ||
| 575 | udelay(smps_delay); | ||
| 576 | |||
| 577 | vdd->curr_volt = target_volt; | ||
| 578 | } | ||
| 579 | |||
| 580 | /* vc_bypass_scale_voltage - VC bypass method of voltage scaling */ | ||
| 581 | static int vc_bypass_scale_voltage(struct omap_vdd_info *vdd, | ||
| 582 | unsigned long target_volt) | ||
| 583 | { | ||
| 584 | u32 loop_cnt = 0, retries_cnt = 0; | ||
| 585 | u32 vc_valid, vc_bypass_val_reg, vc_bypass_value; | ||
| 586 | u16 mod; | ||
| 587 | u8 target_vsel, current_vsel; | ||
| 588 | int ret; | ||
| 589 | |||
| 590 | ret = _pre_volt_scale(vdd, target_volt, &target_vsel, ¤t_vsel); | ||
| 591 | if (ret) | ||
| 592 | return ret; | ||
| 593 | |||
| 594 | mod = vdd->vc_reg.prm_mod; | ||
| 595 | |||
| 596 | vc_valid = vdd->vc_reg.valid; | ||
| 597 | vc_bypass_val_reg = vdd->vc_reg.bypass_val_reg; | ||
| 598 | vc_bypass_value = (target_vsel << vdd->vc_reg.data_shift) | | ||
| 599 | (vdd->pmic_info->pmic_reg << | ||
| 600 | vdd->vc_reg.regaddr_shift) | | ||
| 601 | (vdd->pmic_info->i2c_slave_addr << | ||
| 602 | vdd->vc_reg.slaveaddr_shift); | ||
| 603 | |||
| 604 | vdd->write_reg(vc_bypass_value, mod, vc_bypass_val_reg); | ||
| 605 | vdd->write_reg(vc_bypass_value | vc_valid, mod, vc_bypass_val_reg); | ||
| 606 | |||
| 607 | vc_bypass_value = vdd->read_reg(mod, vc_bypass_val_reg); | ||
| 608 | /* | ||
| 609 | * Loop till the bypass command is acknowledged from the SMPS. | ||
| 610 | * NOTE: This is legacy code. The loop count and retry count needs | ||
| 611 | * to be revisited. | ||
| 612 | */ | ||
| 613 | while (!(vc_bypass_value & vc_valid)) { | ||
| 614 | loop_cnt++; | ||
| 615 | |||
| 616 | if (retries_cnt > 10) { | ||
| 617 | pr_warning("%s: Retry count exceeded\n", __func__); | ||
| 618 | return -ETIMEDOUT; | ||
| 619 | } | ||
| 620 | |||
| 621 | if (loop_cnt > 50) { | ||
| 622 | retries_cnt++; | ||
| 623 | loop_cnt = 0; | ||
| 624 | udelay(10); | ||
| 625 | } | ||
| 626 | vc_bypass_value = vdd->read_reg(mod, vc_bypass_val_reg); | ||
| 627 | } | ||
| 628 | |||
| 629 | _post_volt_scale(vdd, target_volt, target_vsel, current_vsel); | ||
| 630 | return 0; | ||
| 631 | } | ||
| 632 | |||
| 633 | /* VP force update method of voltage scaling */ | ||
| 634 | static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd, | ||
| 635 | unsigned long target_volt) | ||
| 636 | { | ||
| 637 | u32 vpconfig; | ||
| 638 | u16 mod, ocp_mod; | ||
| 639 | u8 target_vsel, current_vsel, prm_irqst_reg; | ||
| 640 | int ret, timeout = 0; | ||
| 641 | |||
| 642 | ret = _pre_volt_scale(vdd, target_volt, &target_vsel, ¤t_vsel); | ||
| 643 | if (ret) | ||
| 644 | return ret; | ||
| 645 | |||
| 646 | mod = vdd->vp_reg.prm_mod; | ||
| 647 | ocp_mod = vdd->ocp_mod; | ||
| 648 | prm_irqst_reg = vdd->prm_irqst_reg; | ||
| 649 | |||
| 650 | /* | ||
| 651 | * Clear all pending TransactionDone interrupt/status. Typical latency | ||
| 652 | * is <3us | ||
| 653 | */ | ||
| 654 | while (timeout++ < VP_TRANXDONE_TIMEOUT) { | ||
| 655 | vdd->write_reg(vdd->vp_reg.tranxdone_status, | ||
| 656 | ocp_mod, prm_irqst_reg); | ||
| 657 | if (!(vdd->read_reg(ocp_mod, prm_irqst_reg) & | ||
| 658 | vdd->vp_reg.tranxdone_status)) | ||
| 659 | break; | ||
| 660 | udelay(1); | ||
| 661 | } | ||
| 662 | if (timeout >= VP_TRANXDONE_TIMEOUT) { | ||
| 663 | pr_warning("%s: vdd_%s TRANXDONE timeout exceeded." | ||
| 664 | "Voltage change aborted", __func__, vdd->voltdm.name); | ||
| 665 | return -ETIMEDOUT; | ||
| 666 | } | ||
| 667 | |||
| 668 | /* Configure for VP-Force Update */ | ||
| 669 | vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig); | ||
| 670 | vpconfig &= ~(vdd->vp_reg.vpconfig_initvdd | | ||
| 671 | vdd->vp_reg.vpconfig_forceupdate | | ||
| 672 | vdd->vp_reg.vpconfig_initvoltage_mask); | ||
| 673 | vpconfig |= ((target_vsel << | ||
| 674 | vdd->vp_reg.vpconfig_initvoltage_shift)); | ||
| 675 | vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); | ||
| 676 | |||
| 677 | /* Trigger initVDD value copy to voltage processor */ | ||
| 678 | vpconfig |= vdd->vp_reg.vpconfig_initvdd; | ||
| 679 | vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); | ||
| 680 | |||
| 681 | /* Force update of voltage */ | ||
| 682 | vpconfig |= vdd->vp_reg.vpconfig_forceupdate; | ||
| 683 | vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); | ||
| 684 | |||
| 685 | /* | ||
| 686 | * Wait for TransactionDone. Typical latency is <200us. | ||
| 687 | * Depends on SMPSWAITTIMEMIN/MAX and voltage change | ||
| 688 | */ | ||
| 689 | timeout = 0; | ||
| 690 | omap_test_timeout((vdd->read_reg(ocp_mod, prm_irqst_reg) & | ||
| 691 | vdd->vp_reg.tranxdone_status), | ||
| 692 | VP_TRANXDONE_TIMEOUT, timeout); | ||
| 693 | if (timeout >= VP_TRANXDONE_TIMEOUT) | ||
| 694 | pr_err("%s: vdd_%s TRANXDONE timeout exceeded." | ||
| 695 | "TRANXDONE never got set after the voltage update\n", | ||
| 696 | __func__, vdd->voltdm.name); | ||
| 697 | |||
| 698 | _post_volt_scale(vdd, target_volt, target_vsel, current_vsel); | ||
| 699 | |||
| 700 | /* | ||
| 701 | * Disable TransactionDone interrupt , clear all status, clear | ||
| 702 | * control registers | ||
| 703 | */ | ||
| 704 | timeout = 0; | ||
| 705 | while (timeout++ < VP_TRANXDONE_TIMEOUT) { | ||
| 706 | vdd->write_reg(vdd->vp_reg.tranxdone_status, | ||
| 707 | ocp_mod, prm_irqst_reg); | ||
| 708 | if (!(vdd->read_reg(ocp_mod, prm_irqst_reg) & | ||
| 709 | vdd->vp_reg.tranxdone_status)) | ||
| 710 | break; | ||
| 711 | udelay(1); | ||
| 712 | } | ||
| 713 | |||
| 714 | if (timeout >= VP_TRANXDONE_TIMEOUT) | ||
| 715 | pr_warning("%s: vdd_%s TRANXDONE timeout exceeded while trying" | ||
| 716 | "to clear the TRANXDONE status\n", | ||
| 717 | __func__, vdd->voltdm.name); | ||
| 718 | |||
| 719 | vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig); | ||
| 720 | /* Clear initVDD copy trigger bit */ | ||
| 721 | vpconfig &= ~vdd->vp_reg.vpconfig_initvdd;; | ||
| 722 | vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); | ||
| 723 | /* Clear force bit */ | ||
| 724 | vpconfig &= ~vdd->vp_reg.vpconfig_forceupdate; | ||
| 725 | vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); | ||
| 726 | |||
| 727 | return 0; | ||
| 728 | } | ||
| 729 | |||
| 730 | /* OMAP3 specific voltage init functions */ | ||
| 731 | |||
| 732 | /* | ||
| 733 | * Intializes the voltage controller registers with the PMIC and board | ||
| 734 | * specific parameters and voltage setup times for OMAP3. | ||
| 735 | */ | ||
| 736 | static void __init omap3_vc_init(struct omap_vdd_info *vdd) | ||
| 737 | { | ||
| 738 | u32 vc_val; | ||
| 739 | u16 mod; | ||
| 740 | u8 on_vsel, onlp_vsel, ret_vsel, off_vsel; | ||
| 741 | static bool is_initialized; | ||
| 742 | |||
| 743 | if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) { | ||
| 744 | pr_err("%s: PMIC info requried to configure vc for" | ||
| 745 | "vdd_%s not populated.Hence cannot initialize vc\n", | ||
| 746 | __func__, vdd->voltdm.name); | ||
| 747 | return; | ||
| 748 | } | ||
| 749 | |||
| 750 | if (!vdd->read_reg || !vdd->write_reg) { | ||
| 751 | pr_err("%s: No read/write API for accessing vdd_%s regs\n", | ||
| 752 | __func__, vdd->voltdm.name); | ||
| 753 | return; | ||
| 754 | } | ||
| 755 | |||
| 756 | mod = vdd->vc_reg.prm_mod; | ||
| 757 | |||
| 758 | /* Set up the SMPS_SA(i2c slave address in VC */ | ||
| 759 | vc_val = vdd->read_reg(mod, vdd->vc_reg.smps_sa_reg); | ||
| 760 | vc_val &= ~vdd->vc_reg.smps_sa_mask; | ||
| 761 | vc_val |= vdd->pmic_info->i2c_slave_addr << vdd->vc_reg.smps_sa_shift; | ||
| 762 | vdd->write_reg(vc_val, mod, vdd->vc_reg.smps_sa_reg); | ||
| 763 | |||
| 764 | /* Setup the VOLRA(pmic reg addr) in VC */ | ||
| 765 | vc_val = vdd->read_reg(mod, vdd->vc_reg.smps_volra_reg); | ||
| 766 | vc_val &= ~vdd->vc_reg.smps_volra_mask; | ||
| 767 | vc_val |= vdd->pmic_info->pmic_reg << vdd->vc_reg.smps_volra_shift; | ||
| 768 | vdd->write_reg(vc_val, mod, vdd->vc_reg.smps_volra_reg); | ||
| 769 | |||
| 770 | /*Configure the setup times */ | ||
| 771 | vc_val = vdd->read_reg(mod, vdd->vc_reg.voltsetup_reg); | ||
| 772 | vc_val &= ~vdd->vc_reg.voltsetup_mask; | ||
| 773 | vc_val |= vdd->pmic_info->volt_setup_time << | ||
| 774 | vdd->vc_reg.voltsetup_shift; | ||
| 775 | vdd->write_reg(vc_val, mod, vdd->vc_reg.voltsetup_reg); | ||
| 776 | |||
| 777 | /* Set up the on, inactive, retention and off voltage */ | ||
| 778 | on_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->on_volt); | ||
| 779 | onlp_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->onlp_volt); | ||
| 780 | ret_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->ret_volt); | ||
| 781 | off_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->off_volt); | ||
| 782 | vc_val = ((on_vsel << vdd->vc_reg.cmd_on_shift) | | ||
| 783 | (onlp_vsel << vdd->vc_reg.cmd_onlp_shift) | | ||
| 784 | (ret_vsel << vdd->vc_reg.cmd_ret_shift) | | ||
| 785 | (off_vsel << vdd->vc_reg.cmd_off_shift)); | ||
| 786 | vdd->write_reg(vc_val, mod, vdd->vc_reg.cmdval_reg); | ||
| 787 | |||
| 788 | if (is_initialized) | ||
| 789 | return; | ||
| 790 | |||
| 791 | /* Generic VC parameters init */ | ||
| 792 | vdd->write_reg(OMAP3430_CMD1_MASK | OMAP3430_RAV1_MASK, mod, | ||
| 793 | OMAP3_PRM_VC_CH_CONF_OFFSET); | ||
| 794 | vdd->write_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK, mod, | ||
| 795 | OMAP3_PRM_VC_I2C_CFG_OFFSET); | ||
| 796 | vdd->write_reg(OMAP3_CLKSETUP, mod, OMAP3_PRM_CLKSETUP_OFFSET); | ||
| 797 | vdd->write_reg(OMAP3_VOLTOFFSET, mod, OMAP3_PRM_VOLTOFFSET_OFFSET); | ||
| 798 | vdd->write_reg(OMAP3_VOLTSETUP2, mod, OMAP3_PRM_VOLTSETUP2_OFFSET); | ||
| 799 | is_initialized = true; | ||
| 800 | } | ||
| 801 | |||
| 802 | /* Sets up all the VDD related info for OMAP3 */ | ||
| 803 | static int __init omap3_vdd_data_configure(struct omap_vdd_info *vdd) | ||
| 804 | { | ||
| 805 | struct clk *sys_ck; | ||
| 806 | u32 sys_clk_speed, timeout_val, waittime; | ||
| 807 | |||
| 808 | if (!vdd->pmic_info) { | ||
| 809 | pr_err("%s: PMIC info requried to configure vdd_%s not" | ||
| 810 | "populated.Hence cannot initialize vdd_%s\n", | ||
| 811 | __func__, vdd->voltdm.name, vdd->voltdm.name); | ||
| 812 | return -EINVAL; | ||
| 813 | } | ||
| 814 | |||
| 815 | if (!strcmp(vdd->voltdm.name, "mpu")) { | ||
| 816 | if (cpu_is_omap3630()) | ||
| 817 | vdd->volt_data = omap36xx_vddmpu_volt_data; | ||
| 818 | else | ||
| 819 | vdd->volt_data = omap34xx_vddmpu_volt_data; | ||
| 820 | |||
| 821 | vdd->vp_reg.tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK; | ||
| 822 | vdd->vc_reg.cmdval_reg = OMAP3_PRM_VC_CMD_VAL_0_OFFSET; | ||
| 823 | vdd->vc_reg.smps_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT; | ||
| 824 | vdd->vc_reg.smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA0_MASK; | ||
| 825 | vdd->vc_reg.smps_volra_shift = OMAP3430_VOLRA0_SHIFT; | ||
| 826 | vdd->vc_reg.smps_volra_mask = OMAP3430_VOLRA0_MASK; | ||
| 827 | vdd->vc_reg.voltsetup_shift = OMAP3430_SETUP_TIME1_SHIFT; | ||
| 828 | vdd->vc_reg.voltsetup_mask = OMAP3430_SETUP_TIME1_MASK; | ||
| 829 | } else if (!strcmp(vdd->voltdm.name, "core")) { | ||
| 830 | if (cpu_is_omap3630()) | ||
| 831 | vdd->volt_data = omap36xx_vddcore_volt_data; | ||
| 832 | else | ||
| 833 | vdd->volt_data = omap34xx_vddcore_volt_data; | ||
| 834 | |||
| 835 | vdd->vp_reg.tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK; | ||
| 836 | vdd->vc_reg.cmdval_reg = OMAP3_PRM_VC_CMD_VAL_1_OFFSET; | ||
| 837 | vdd->vc_reg.smps_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT; | ||
| 838 | vdd->vc_reg.smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA1_MASK; | ||
| 839 | vdd->vc_reg.smps_volra_shift = OMAP3430_VOLRA1_SHIFT; | ||
| 840 | vdd->vc_reg.smps_volra_mask = OMAP3430_VOLRA1_MASK; | ||
| 841 | vdd->vc_reg.voltsetup_shift = OMAP3430_SETUP_TIME2_SHIFT; | ||
| 842 | vdd->vc_reg.voltsetup_mask = OMAP3430_SETUP_TIME2_MASK; | ||
| 843 | } else { | ||
| 844 | pr_warning("%s: vdd_%s does not exisit in OMAP3\n", | ||
| 845 | __func__, vdd->voltdm.name); | ||
| 846 | return -EINVAL; | ||
| 847 | } | ||
| 848 | |||
| 849 | /* | ||
| 850 | * Sys clk rate is require to calculate vp timeout value and | ||
| 851 | * smpswaittimemin and smpswaittimemax. | ||
| 852 | */ | ||
| 853 | sys_ck = clk_get(NULL, "sys_ck"); | ||
| 854 | if (IS_ERR(sys_ck)) { | ||
| 855 | pr_warning("%s: Could not get the sys clk to calculate" | ||
| 856 | "various vdd_%s params\n", __func__, vdd->voltdm.name); | ||
| 857 | return -EINVAL; | ||
| 858 | } | ||
| 859 | sys_clk_speed = clk_get_rate(sys_ck); | ||
| 860 | clk_put(sys_ck); | ||
| 861 | /* Divide to avoid overflow */ | ||
| 862 | sys_clk_speed /= 1000; | ||
| 863 | |||
| 864 | /* Generic voltage parameters */ | ||
| 865 | vdd->curr_volt = 1200000; | ||
| 866 | vdd->ocp_mod = OCP_MOD; | ||
| 867 | vdd->prm_irqst_reg = OMAP3_PRM_IRQSTATUS_MPU_OFFSET; | ||
| 868 | vdd->read_reg = omap3_voltage_read_reg; | ||
| 869 | vdd->write_reg = omap3_voltage_write_reg; | ||
| 870 | vdd->volt_scale = vp_forceupdate_scale_voltage; | ||
| 871 | vdd->vp_enabled = false; | ||
| 872 | |||
| 873 | /* VC parameters */ | ||
| 874 | vdd->vc_reg.prm_mod = OMAP3430_GR_MOD; | ||
| 875 | vdd->vc_reg.smps_sa_reg = OMAP3_PRM_VC_SMPS_SA_OFFSET; | ||
| 876 | vdd->vc_reg.smps_volra_reg = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET; | ||
| 877 | vdd->vc_reg.bypass_val_reg = OMAP3_PRM_VC_BYPASS_VAL_OFFSET; | ||
| 878 | vdd->vc_reg.voltsetup_reg = OMAP3_PRM_VOLTSETUP1_OFFSET; | ||
| 879 | vdd->vc_reg.data_shift = OMAP3430_DATA_SHIFT; | ||
| 880 | vdd->vc_reg.slaveaddr_shift = OMAP3430_SLAVEADDR_SHIFT; | ||
| 881 | vdd->vc_reg.regaddr_shift = OMAP3430_REGADDR_SHIFT; | ||
| 882 | vdd->vc_reg.valid = OMAP3430_VALID_MASK; | ||
| 883 | vdd->vc_reg.cmd_on_shift = OMAP3430_VC_CMD_ON_SHIFT; | ||
| 884 | vdd->vc_reg.cmd_on_mask = OMAP3430_VC_CMD_ON_MASK; | ||
| 885 | vdd->vc_reg.cmd_onlp_shift = OMAP3430_VC_CMD_ONLP_SHIFT; | ||
| 886 | vdd->vc_reg.cmd_ret_shift = OMAP3430_VC_CMD_RET_SHIFT; | ||
| 887 | vdd->vc_reg.cmd_off_shift = OMAP3430_VC_CMD_OFF_SHIFT; | ||
| 888 | |||
| 889 | vdd->vp_reg.prm_mod = OMAP3430_GR_MOD; | ||
| 890 | |||
| 891 | /* VPCONFIG bit fields */ | ||
| 892 | vdd->vp_reg.vpconfig_erroroffset = (vdd->pmic_info->vp_erroroffset << | ||
| 893 | OMAP3430_ERROROFFSET_SHIFT); | ||
| 894 | vdd->vp_reg.vpconfig_errorgain_mask = OMAP3430_ERRORGAIN_MASK; | ||
| 895 | vdd->vp_reg.vpconfig_errorgain_shift = OMAP3430_ERRORGAIN_SHIFT; | ||
| 896 | vdd->vp_reg.vpconfig_initvoltage_shift = OMAP3430_INITVOLTAGE_SHIFT; | ||
| 897 | vdd->vp_reg.vpconfig_initvoltage_mask = OMAP3430_INITVOLTAGE_MASK; | ||
| 898 | vdd->vp_reg.vpconfig_timeouten = OMAP3430_TIMEOUTEN_MASK; | ||
| 899 | vdd->vp_reg.vpconfig_initvdd = OMAP3430_INITVDD_MASK; | ||
| 900 | vdd->vp_reg.vpconfig_forceupdate = OMAP3430_FORCEUPDATE_MASK; | ||
| 901 | vdd->vp_reg.vpconfig_vpenable = OMAP3430_VPENABLE_MASK; | ||
| 902 | |||
| 903 | /* VSTEPMIN VSTEPMAX bit fields */ | ||
| 904 | waittime = ((vdd->pmic_info->step_size / vdd->pmic_info->slew_rate) * | ||
| 905 | sys_clk_speed) / 1000; | ||
| 906 | vdd->vp_reg.vstepmin_smpswaittimemin = waittime; | ||
| 907 | vdd->vp_reg.vstepmax_smpswaittimemax = waittime; | ||
| 908 | vdd->vp_reg.vstepmin_stepmin = vdd->pmic_info->vp_vstepmin; | ||
| 909 | vdd->vp_reg.vstepmax_stepmax = vdd->pmic_info->vp_vstepmax; | ||
| 910 | vdd->vp_reg.vstepmin_smpswaittimemin_shift = | ||
| 911 | OMAP3430_SMPSWAITTIMEMIN_SHIFT; | ||
| 912 | vdd->vp_reg.vstepmax_smpswaittimemax_shift = | ||
| 913 | OMAP3430_SMPSWAITTIMEMAX_SHIFT; | ||
| 914 | vdd->vp_reg.vstepmin_stepmin_shift = OMAP3430_VSTEPMIN_SHIFT; | ||
| 915 | vdd->vp_reg.vstepmax_stepmax_shift = OMAP3430_VSTEPMAX_SHIFT; | ||
| 916 | |||
| 917 | /* VLIMITTO bit fields */ | ||
| 918 | timeout_val = (sys_clk_speed * vdd->pmic_info->vp_timeout_us) / 1000; | ||
| 919 | vdd->vp_reg.vlimitto_timeout = timeout_val; | ||
| 920 | vdd->vp_reg.vlimitto_vddmin = vdd->pmic_info->vp_vddmin; | ||
| 921 | vdd->vp_reg.vlimitto_vddmax = vdd->pmic_info->vp_vddmax; | ||
| 922 | vdd->vp_reg.vlimitto_vddmin_shift = OMAP3430_VDDMIN_SHIFT; | ||
| 923 | vdd->vp_reg.vlimitto_vddmax_shift = OMAP3430_VDDMAX_SHIFT; | ||
| 924 | vdd->vp_reg.vlimitto_timeout_shift = OMAP3430_TIMEOUT_SHIFT; | ||
| 925 | |||
| 926 | return 0; | ||
| 927 | } | ||
| 928 | |||
| 929 | /* OMAP4 specific voltage init functions */ | ||
| 930 | static void __init omap4_vc_init(struct omap_vdd_info *vdd) | ||
| 931 | { | ||
| 932 | u32 vc_val; | ||
| 933 | u16 mod; | ||
| 934 | static bool is_initialized; | ||
| 935 | |||
| 936 | if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) { | ||
| 937 | pr_err("%s: PMIC info requried to configure vc for" | ||
| 938 | "vdd_%s not populated.Hence cannot initialize vc\n", | ||
| 939 | __func__, vdd->voltdm.name); | ||
| 940 | return; | ||
| 941 | } | ||
| 942 | |||
| 943 | if (!vdd->read_reg || !vdd->write_reg) { | ||
| 944 | pr_err("%s: No read/write API for accessing vdd_%s regs\n", | ||
| 945 | __func__, vdd->voltdm.name); | ||
| 946 | return; | ||
| 947 | } | ||
| 948 | |||
| 949 | mod = vdd->vc_reg.prm_mod; | ||
| 950 | |||
| 951 | /* Set up the SMPS_SA(i2c slave address in VC */ | ||
| 952 | vc_val = vdd->read_reg(mod, vdd->vc_reg.smps_sa_reg); | ||
| 953 | vc_val &= ~vdd->vc_reg.smps_sa_mask; | ||
| 954 | vc_val |= vdd->pmic_info->i2c_slave_addr << vdd->vc_reg.smps_sa_shift; | ||
| 955 | vdd->write_reg(vc_val, mod, vdd->vc_reg.smps_sa_reg); | ||
| 956 | |||
| 957 | /* Setup the VOLRA(pmic reg addr) in VC */ | ||
| 958 | vc_val = vdd->read_reg(mod, vdd->vc_reg.smps_volra_reg); | ||
| 959 | vc_val &= ~vdd->vc_reg.smps_volra_mask; | ||
| 960 | vc_val |= vdd->pmic_info->pmic_reg << vdd->vc_reg.smps_volra_shift; | ||
| 961 | vdd->write_reg(vc_val, mod, vdd->vc_reg.smps_volra_reg); | ||
| 962 | |||
| 963 | /* TODO: Configure setup times and CMD_VAL values*/ | ||
| 964 | |||
| 965 | if (is_initialized) | ||
| 966 | return; | ||
| 967 | |||
| 968 | /* Generic VC parameters init */ | ||
| 969 | vc_val = (OMAP4430_RAV_VDD_MPU_L_MASK | OMAP4430_CMD_VDD_MPU_L_MASK | | ||
| 970 | OMAP4430_RAV_VDD_IVA_L_MASK | OMAP4430_CMD_VDD_IVA_L_MASK | | ||
| 971 | OMAP4430_RAV_VDD_CORE_L_MASK | OMAP4430_CMD_VDD_CORE_L_MASK); | ||
| 972 | vdd->write_reg(vc_val, mod, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET); | ||
| 973 | |||
| 974 | vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT); | ||
| 975 | vdd->write_reg(vc_val, mod, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET); | ||
| 976 | |||
| 977 | is_initialized = true; | ||
| 978 | } | ||
| 979 | |||
| 980 | /* Sets up all the VDD related info for OMAP4 */ | ||
| 981 | static int __init omap4_vdd_data_configure(struct omap_vdd_info *vdd) | ||
| 982 | { | ||
| 983 | struct clk *sys_ck; | ||
| 984 | u32 sys_clk_speed, timeout_val, waittime; | ||
| 985 | |||
| 986 | if (!vdd->pmic_info) { | ||
| 987 | pr_err("%s: PMIC info requried to configure vdd_%s not" | ||
| 988 | "populated.Hence cannot initialize vdd_%s\n", | ||
| 989 | __func__, vdd->voltdm.name, vdd->voltdm.name); | ||
| 990 | return -EINVAL; | ||
| 991 | } | ||
| 992 | |||
| 993 | if (!strcmp(vdd->voltdm.name, "mpu")) { | ||
| 994 | vdd->volt_data = omap44xx_vdd_mpu_volt_data; | ||
| 995 | vdd->vp_reg.tranxdone_status = | ||
| 996 | OMAP4430_VP_MPU_TRANXDONE_ST_MASK; | ||
| 997 | vdd->vc_reg.cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET; | ||
| 998 | vdd->vc_reg.smps_sa_shift = | ||
| 999 | OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT; | ||
| 1000 | vdd->vc_reg.smps_sa_mask = | ||
| 1001 | OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK; | ||
| 1002 | vdd->vc_reg.smps_volra_shift = OMAP4430_VOLRA_VDD_MPU_L_SHIFT; | ||
| 1003 | vdd->vc_reg.smps_volra_mask = OMAP4430_VOLRA_VDD_MPU_L_MASK; | ||
| 1004 | vdd->vc_reg.voltsetup_reg = | ||
| 1005 | OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET; | ||
| 1006 | vdd->prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET; | ||
| 1007 | } else if (!strcmp(vdd->voltdm.name, "core")) { | ||
| 1008 | vdd->volt_data = omap44xx_vdd_core_volt_data; | ||
| 1009 | vdd->vp_reg.tranxdone_status = | ||
| 1010 | OMAP4430_VP_CORE_TRANXDONE_ST_MASK; | ||
| 1011 | vdd->vc_reg.cmdval_reg = | ||
| 1012 | OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET; | ||
| 1013 | vdd->vc_reg.smps_sa_shift = OMAP4430_SA_VDD_CORE_L_0_6_SHIFT; | ||
| 1014 | vdd->vc_reg.smps_sa_mask = OMAP4430_SA_VDD_CORE_L_0_6_MASK; | ||
| 1015 | vdd->vc_reg.smps_volra_shift = OMAP4430_VOLRA_VDD_CORE_L_SHIFT; | ||
| 1016 | vdd->vc_reg.smps_volra_mask = OMAP4430_VOLRA_VDD_CORE_L_MASK; | ||
| 1017 | vdd->vc_reg.voltsetup_reg = | ||
| 1018 | OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET; | ||
| 1019 | vdd->prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET; | ||
| 1020 | } else if (!strcmp(vdd->voltdm.name, "iva")) { | ||
| 1021 | vdd->volt_data = omap44xx_vdd_iva_volt_data; | ||
| 1022 | vdd->vp_reg.tranxdone_status = | ||
| 1023 | OMAP4430_VP_IVA_TRANXDONE_ST_MASK; | ||
| 1024 | vdd->vc_reg.cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET; | ||
| 1025 | vdd->vc_reg.smps_sa_shift = | ||
| 1026 | OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT; | ||
| 1027 | vdd->vc_reg.smps_sa_mask = | ||
| 1028 | OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK; | ||
| 1029 | vdd->vc_reg.smps_volra_shift = OMAP4430_VOLRA_VDD_IVA_L_SHIFT; | ||
| 1030 | vdd->vc_reg.smps_volra_mask = OMAP4430_VOLRA_VDD_IVA_L_MASK; | ||
| 1031 | vdd->vc_reg.voltsetup_reg = | ||
| 1032 | OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET; | ||
| 1033 | vdd->prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET; | ||
| 1034 | } else { | ||
| 1035 | pr_warning("%s: vdd_%s does not exisit in OMAP4\n", | ||
| 1036 | __func__, vdd->voltdm.name); | ||
| 1037 | return -EINVAL; | ||
| 1038 | } | ||
| 1039 | |||
| 1040 | /* | ||
| 1041 | * Sys clk rate is require to calculate vp timeout value and | ||
| 1042 | * smpswaittimemin and smpswaittimemax. | ||
| 1043 | */ | ||
| 1044 | sys_ck = clk_get(NULL, "sys_clkin_ck"); | ||
| 1045 | if (IS_ERR(sys_ck)) { | ||
| 1046 | pr_warning("%s: Could not get the sys clk to calculate" | ||
| 1047 | "various vdd_%s params\n", __func__, vdd->voltdm.name); | ||
| 1048 | return -EINVAL; | ||
| 1049 | } | ||
| 1050 | sys_clk_speed = clk_get_rate(sys_ck); | ||
| 1051 | clk_put(sys_ck); | ||
| 1052 | /* Divide to avoid overflow */ | ||
| 1053 | sys_clk_speed /= 1000; | ||
| 1054 | |||
| 1055 | /* Generic voltage parameters */ | ||
| 1056 | vdd->curr_volt = 1200000; | ||
| 1057 | vdd->ocp_mod = OMAP4430_PRM_OCP_SOCKET_INST; | ||
| 1058 | vdd->read_reg = omap4_voltage_read_reg; | ||
| 1059 | vdd->write_reg = omap4_voltage_write_reg; | ||
| 1060 | vdd->volt_scale = vp_forceupdate_scale_voltage; | ||
| 1061 | vdd->vp_enabled = false; | ||
| 1062 | |||
| 1063 | /* VC parameters */ | ||
| 1064 | vdd->vc_reg.prm_mod = OMAP4430_PRM_DEVICE_INST; | ||
| 1065 | vdd->vc_reg.smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET; | ||
| 1066 | vdd->vc_reg.smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET; | ||
| 1067 | vdd->vc_reg.bypass_val_reg = OMAP4_PRM_VC_VAL_BYPASS_OFFSET; | ||
| 1068 | vdd->vc_reg.data_shift = OMAP4430_DATA_SHIFT; | ||
| 1069 | vdd->vc_reg.slaveaddr_shift = OMAP4430_SLAVEADDR_SHIFT; | ||
| 1070 | vdd->vc_reg.regaddr_shift = OMAP4430_REGADDR_SHIFT; | ||
| 1071 | vdd->vc_reg.valid = OMAP4430_VALID_MASK; | ||
| 1072 | vdd->vc_reg.cmd_on_shift = OMAP4430_ON_SHIFT; | ||
| 1073 | vdd->vc_reg.cmd_on_mask = OMAP4430_ON_MASK; | ||
| 1074 | vdd->vc_reg.cmd_onlp_shift = OMAP4430_ONLP_SHIFT; | ||
| 1075 | vdd->vc_reg.cmd_ret_shift = OMAP4430_RET_SHIFT; | ||
| 1076 | vdd->vc_reg.cmd_off_shift = OMAP4430_OFF_SHIFT; | ||
| 1077 | |||
| 1078 | vdd->vp_reg.prm_mod = OMAP4430_PRM_DEVICE_INST; | ||
| 1079 | |||
| 1080 | /* VPCONFIG bit fields */ | ||
| 1081 | vdd->vp_reg.vpconfig_erroroffset = (vdd->pmic_info->vp_erroroffset << | ||
| 1082 | OMAP4430_ERROROFFSET_SHIFT); | ||
| 1083 | vdd->vp_reg.vpconfig_errorgain_mask = OMAP4430_ERRORGAIN_MASK; | ||
| 1084 | vdd->vp_reg.vpconfig_errorgain_shift = OMAP4430_ERRORGAIN_SHIFT; | ||
| 1085 | vdd->vp_reg.vpconfig_initvoltage_shift = OMAP4430_INITVOLTAGE_SHIFT; | ||
| 1086 | vdd->vp_reg.vpconfig_initvoltage_mask = OMAP4430_INITVOLTAGE_MASK; | ||
| 1087 | vdd->vp_reg.vpconfig_timeouten = OMAP4430_TIMEOUTEN_MASK; | ||
| 1088 | vdd->vp_reg.vpconfig_initvdd = OMAP4430_INITVDD_MASK; | ||
| 1089 | vdd->vp_reg.vpconfig_forceupdate = OMAP4430_FORCEUPDATE_MASK; | ||
| 1090 | vdd->vp_reg.vpconfig_vpenable = OMAP4430_VPENABLE_MASK; | ||
| 1091 | |||
| 1092 | /* VSTEPMIN VSTEPMAX bit fields */ | ||
| 1093 | waittime = ((vdd->pmic_info->step_size / vdd->pmic_info->slew_rate) * | ||
| 1094 | sys_clk_speed) / 1000; | ||
| 1095 | vdd->vp_reg.vstepmin_smpswaittimemin = waittime; | ||
| 1096 | vdd->vp_reg.vstepmax_smpswaittimemax = waittime; | ||
| 1097 | vdd->vp_reg.vstepmin_stepmin = vdd->pmic_info->vp_vstepmin; | ||
| 1098 | vdd->vp_reg.vstepmax_stepmax = vdd->pmic_info->vp_vstepmax; | ||
| 1099 | vdd->vp_reg.vstepmin_smpswaittimemin_shift = | ||
| 1100 | OMAP4430_SMPSWAITTIMEMIN_SHIFT; | ||
| 1101 | vdd->vp_reg.vstepmax_smpswaittimemax_shift = | ||
| 1102 | OMAP4430_SMPSWAITTIMEMAX_SHIFT; | ||
| 1103 | vdd->vp_reg.vstepmin_stepmin_shift = OMAP4430_VSTEPMIN_SHIFT; | ||
| 1104 | vdd->vp_reg.vstepmax_stepmax_shift = OMAP4430_VSTEPMAX_SHIFT; | ||
| 1105 | |||
| 1106 | /* VLIMITTO bit fields */ | ||
| 1107 | timeout_val = (sys_clk_speed * vdd->pmic_info->vp_timeout_us) / 1000; | ||
| 1108 | vdd->vp_reg.vlimitto_timeout = timeout_val; | ||
| 1109 | vdd->vp_reg.vlimitto_vddmin = vdd->pmic_info->vp_vddmin; | ||
| 1110 | vdd->vp_reg.vlimitto_vddmax = vdd->pmic_info->vp_vddmax; | ||
| 1111 | vdd->vp_reg.vlimitto_vddmin_shift = OMAP4430_VDDMIN_SHIFT; | ||
| 1112 | vdd->vp_reg.vlimitto_vddmax_shift = OMAP4430_VDDMAX_SHIFT; | ||
| 1113 | vdd->vp_reg.vlimitto_timeout_shift = OMAP4430_TIMEOUT_SHIFT; | ||
| 1114 | |||
| 1115 | return 0; | ||
| 1116 | } | ||
| 1117 | |||
| 1118 | /* Public functions */ | ||
| 1119 | /** | ||
| 1120 | * omap_voltage_get_nom_volt() - Gets the current non-auto-compensated voltage | ||
| 1121 | * @voltdm: pointer to the VDD for which current voltage info is needed | ||
| 1122 | * | ||
| 1123 | * API to get the current non-auto-compensated voltage for a VDD. | ||
| 1124 | * Returns 0 in case of error else returns the current voltage for the VDD. | ||
| 1125 | */ | ||
| 1126 | unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm) | ||
| 1127 | { | ||
| 1128 | struct omap_vdd_info *vdd; | ||
| 1129 | |||
| 1130 | if (!voltdm || IS_ERR(voltdm)) { | ||
| 1131 | pr_warning("%s: VDD specified does not exist!\n", __func__); | ||
| 1132 | return 0; | ||
| 1133 | } | ||
| 1134 | |||
| 1135 | vdd = container_of(voltdm, struct omap_vdd_info, voltdm); | ||
| 1136 | |||
| 1137 | return vdd->curr_volt; | ||
| 1138 | } | ||
| 1139 | |||
| 1140 | /** | ||
| 1141 | * omap_vp_get_curr_volt() - API to get the current vp voltage. | ||
| 1142 | * @voltdm: pointer to the VDD. | ||
| 1143 | * | ||
| 1144 | * This API returns the current voltage for the specified voltage processor | ||
| 1145 | */ | ||
| 1146 | unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm) | ||
| 1147 | { | ||
| 1148 | struct omap_vdd_info *vdd; | ||
| 1149 | u8 curr_vsel; | ||
| 1150 | |||
| 1151 | if (!voltdm || IS_ERR(voltdm)) { | ||
| 1152 | pr_warning("%s: VDD specified does not exist!\n", __func__); | ||
| 1153 | return 0; | ||
| 1154 | } | ||
| 1155 | |||
| 1156 | vdd = container_of(voltdm, struct omap_vdd_info, voltdm); | ||
| 1157 | if (!vdd->read_reg) { | ||
| 1158 | pr_err("%s: No read API for reading vdd_%s regs\n", | ||
| 1159 | __func__, voltdm->name); | ||
| 1160 | return 0; | ||
| 1161 | } | ||
| 1162 | |||
| 1163 | curr_vsel = vdd->read_reg(vdd->vp_reg.prm_mod, | ||
| 1164 | vdd->vp_offs.voltage); | ||
| 1165 | |||
| 1166 | if (!vdd->pmic_info || !vdd->pmic_info->vsel_to_uv) { | ||
| 1167 | pr_warning("%s: PMIC function to convert vsel to voltage" | ||
| 1168 | "in uV not registerd\n", __func__); | ||
| 1169 | return 0; | ||
| 1170 | } | ||
| 1171 | |||
| 1172 | return vdd->pmic_info->vsel_to_uv(curr_vsel); | ||
| 1173 | } | ||
| 1174 | |||
| 1175 | /** | ||
| 1176 | * omap_vp_enable() - API to enable a particular VP | ||
| 1177 | * @voltdm: pointer to the VDD whose VP is to be enabled. | ||
| 1178 | * | ||
| 1179 | * This API enables a particular voltage processor. Needed by the smartreflex | ||
| 1180 | * class drivers. | ||
| 1181 | */ | ||
| 1182 | void omap_vp_enable(struct voltagedomain *voltdm) | ||
| 1183 | { | ||
| 1184 | struct omap_vdd_info *vdd; | ||
| 1185 | u32 vpconfig; | ||
| 1186 | u16 mod; | ||
| 1187 | |||
| 1188 | if (!voltdm || IS_ERR(voltdm)) { | ||
| 1189 | pr_warning("%s: VDD specified does not exist!\n", __func__); | ||
| 1190 | return; | ||
| 1191 | } | ||
| 1192 | |||
| 1193 | vdd = container_of(voltdm, struct omap_vdd_info, voltdm); | ||
| 1194 | if (!vdd->read_reg || !vdd->write_reg) { | ||
| 1195 | pr_err("%s: No read/write API for accessing vdd_%s regs\n", | ||
| 1196 | __func__, voltdm->name); | ||
| 1197 | return; | ||
| 1198 | } | ||
| 1199 | |||
| 1200 | mod = vdd->vp_reg.prm_mod; | ||
| 1201 | |||
| 1202 | /* If VP is already enabled, do nothing. Return */ | ||
| 1203 | if (vdd->vp_enabled) | ||
| 1204 | return; | ||
| 1205 | |||
| 1206 | vp_latch_vsel(vdd); | ||
| 1207 | |||
| 1208 | /* Enable VP */ | ||
| 1209 | vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig); | ||
| 1210 | vpconfig |= vdd->vp_reg.vpconfig_vpenable; | ||
| 1211 | vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); | ||
| 1212 | vdd->vp_enabled = true; | ||
| 1213 | } | ||
| 1214 | |||
| 1215 | /** | ||
| 1216 | * omap_vp_disable() - API to disable a particular VP | ||
| 1217 | * @voltdm: pointer to the VDD whose VP is to be disabled. | ||
| 1218 | * | ||
| 1219 | * This API disables a particular voltage processor. Needed by the smartreflex | ||
| 1220 | * class drivers. | ||
| 1221 | */ | ||
| 1222 | void omap_vp_disable(struct voltagedomain *voltdm) | ||
| 1223 | { | ||
| 1224 | struct omap_vdd_info *vdd; | ||
| 1225 | u32 vpconfig; | ||
| 1226 | u16 mod; | ||
| 1227 | int timeout; | ||
| 1228 | |||
| 1229 | if (!voltdm || IS_ERR(voltdm)) { | ||
| 1230 | pr_warning("%s: VDD specified does not exist!\n", __func__); | ||
| 1231 | return; | ||
| 1232 | } | ||
| 1233 | |||
| 1234 | vdd = container_of(voltdm, struct omap_vdd_info, voltdm); | ||
| 1235 | if (!vdd->read_reg || !vdd->write_reg) { | ||
| 1236 | pr_err("%s: No read/write API for accessing vdd_%s regs\n", | ||
| 1237 | __func__, voltdm->name); | ||
| 1238 | return; | ||
| 1239 | } | ||
| 1240 | |||
| 1241 | mod = vdd->vp_reg.prm_mod; | ||
| 1242 | |||
| 1243 | /* If VP is already disabled, do nothing. Return */ | ||
| 1244 | if (!vdd->vp_enabled) { | ||
| 1245 | pr_warning("%s: Trying to disable VP for vdd_%s when" | ||
| 1246 | "it is already disabled\n", __func__, voltdm->name); | ||
| 1247 | return; | ||
| 1248 | } | ||
| 1249 | |||
| 1250 | /* Disable VP */ | ||
| 1251 | vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig); | ||
| 1252 | vpconfig &= ~vdd->vp_reg.vpconfig_vpenable; | ||
| 1253 | vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig); | ||
| 1254 | |||
| 1255 | /* | ||
| 1256 | * Wait for VP idle Typical latency is <2us. Maximum latency is ~100us | ||
| 1257 | */ | ||
| 1258 | omap_test_timeout((vdd->read_reg(mod, vdd->vp_offs.vstatus)), | ||
| 1259 | VP_IDLE_TIMEOUT, timeout); | ||
| 1260 | |||
| 1261 | if (timeout >= VP_IDLE_TIMEOUT) | ||
| 1262 | pr_warning("%s: vdd_%s idle timedout\n", | ||
| 1263 | __func__, voltdm->name); | ||
| 1264 | |||
| 1265 | vdd->vp_enabled = false; | ||
| 1266 | |||
| 1267 | return; | ||
| 1268 | } | ||
| 1269 | |||
| 1270 | /** | ||
| 1271 | * omap_voltage_scale_vdd() - API to scale voltage of a particular | ||
| 1272 | * voltage domain. | ||
| 1273 | * @voltdm: pointer to the VDD which is to be scaled. | ||
| 1274 | * @target_volt: The target voltage of the voltage domain | ||
| 1275 | * | ||
| 1276 | * This API should be called by the kernel to do the voltage scaling | ||
| 1277 | * for a particular voltage domain during dvfs or any other situation. | ||
| 1278 | */ | ||
| 1279 | int omap_voltage_scale_vdd(struct voltagedomain *voltdm, | ||
| 1280 | unsigned long target_volt) | ||
| 1281 | { | ||
| 1282 | struct omap_vdd_info *vdd; | ||
| 1283 | |||
| 1284 | if (!voltdm || IS_ERR(voltdm)) { | ||
| 1285 | pr_warning("%s: VDD specified does not exist!\n", __func__); | ||
| 1286 | return -EINVAL; | ||
| 1287 | } | ||
| 1288 | |||
| 1289 | vdd = container_of(voltdm, struct omap_vdd_info, voltdm); | ||
| 1290 | |||
| 1291 | if (!vdd->volt_scale) { | ||
| 1292 | pr_err("%s: No voltage scale API registered for vdd_%s\n", | ||
| 1293 | __func__, voltdm->name); | ||
| 1294 | return -ENODATA; | ||
| 1295 | } | ||
| 1296 | |||
| 1297 | return vdd->volt_scale(vdd, target_volt); | ||
| 1298 | } | ||
| 1299 | |||
| 1300 | /** | ||
| 1301 | * omap_voltage_reset() - Resets the voltage of a particular voltage domain | ||
| 1302 | * to that of the current OPP. | ||
| 1303 | * @voltdm: pointer to the VDD whose voltage is to be reset. | ||
| 1304 | * | ||
| 1305 | * This API finds out the correct voltage the voltage domain is supposed | ||
| 1306 | * to be at and resets the voltage to that level. Should be used expecially | ||
| 1307 | * while disabling any voltage compensation modules. | ||
| 1308 | */ | ||
| 1309 | void omap_voltage_reset(struct voltagedomain *voltdm) | ||
| 1310 | { | ||
| 1311 | unsigned long target_uvdc; | ||
| 1312 | |||
| 1313 | if (!voltdm || IS_ERR(voltdm)) { | ||
| 1314 | pr_warning("%s: VDD specified does not exist!\n", __func__); | ||
| 1315 | return; | ||
| 1316 | } | ||
| 1317 | |||
| 1318 | target_uvdc = omap_voltage_get_nom_volt(voltdm); | ||
| 1319 | if (!target_uvdc) { | ||
| 1320 | pr_err("%s: unable to find current voltage for vdd_%s\n", | ||
| 1321 | __func__, voltdm->name); | ||
| 1322 | return; | ||
| 1323 | } | ||
| 1324 | |||
| 1325 | omap_voltage_scale_vdd(voltdm, target_uvdc); | ||
| 1326 | } | ||
| 1327 | |||
| 1328 | /** | ||
| 1329 | * omap_voltage_get_volttable() - API to get the voltage table associated with a | ||
| 1330 | * particular voltage domain. | ||
| 1331 | * @voltdm: pointer to the VDD for which the voltage table is required | ||
| 1332 | * @volt_data: the voltage table for the particular vdd which is to be | ||
| 1333 | * populated by this API | ||
| 1334 | * | ||
| 1335 | * This API populates the voltage table associated with a VDD into the | ||
| 1336 | * passed parameter pointer. Returns the count of distinct voltages | ||
| 1337 | * supported by this vdd. | ||
| 1338 | * | ||
| 1339 | */ | ||
| 1340 | void omap_voltage_get_volttable(struct voltagedomain *voltdm, | ||
| 1341 | struct omap_volt_data **volt_data) | ||
| 1342 | { | ||
| 1343 | struct omap_vdd_info *vdd; | ||
| 1344 | |||
| 1345 | if (!voltdm || IS_ERR(voltdm)) { | ||
| 1346 | pr_warning("%s: VDD specified does not exist!\n", __func__); | ||
| 1347 | return; | ||
| 1348 | } | ||
| 1349 | |||
| 1350 | vdd = container_of(voltdm, struct omap_vdd_info, voltdm); | ||
| 1351 | |||
| 1352 | *volt_data = vdd->volt_data; | ||
| 1353 | } | ||
| 1354 | |||
| 1355 | /** | ||
| 1356 | * omap_voltage_get_voltdata() - API to get the voltage table entry for a | ||
| 1357 | * particular voltage | ||
| 1358 | * @voltdm: pointer to the VDD whose voltage table has to be searched | ||
| 1359 | * @volt: the voltage to be searched in the voltage table | ||
| 1360 | * | ||
| 1361 | * This API searches through the voltage table for the required voltage | ||
| 1362 | * domain and tries to find a matching entry for the passed voltage volt. | ||
| 1363 | * If a matching entry is found volt_data is populated with that entry. | ||
| 1364 | * This API searches only through the non-compensated voltages int the | ||
| 1365 | * voltage table. | ||
| 1366 | * Returns pointer to the voltage table entry corresponding to volt on | ||
| 1367 | * sucess. Returns -ENODATA if no voltage table exisits for the passed voltage | ||
| 1368 | * domain or if there is no matching entry. | ||
| 1369 | */ | ||
| 1370 | struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm, | ||
| 1371 | unsigned long volt) | ||
| 1372 | { | ||
| 1373 | struct omap_vdd_info *vdd; | ||
| 1374 | int i; | ||
| 1375 | |||
| 1376 | if (!voltdm || IS_ERR(voltdm)) { | ||
| 1377 | pr_warning("%s: VDD specified does not exist!\n", __func__); | ||
| 1378 | return ERR_PTR(-EINVAL); | ||
| 1379 | } | ||
| 1380 | |||
| 1381 | vdd = container_of(voltdm, struct omap_vdd_info, voltdm); | ||
| 1382 | |||
| 1383 | if (!vdd->volt_data) { | ||
| 1384 | pr_warning("%s: voltage table does not exist for vdd_%s\n", | ||
| 1385 | __func__, voltdm->name); | ||
| 1386 | return ERR_PTR(-ENODATA); | ||
| 1387 | } | ||
| 1388 | |||
| 1389 | for (i = 0; vdd->volt_data[i].volt_nominal != 0; i++) { | ||
| 1390 | if (vdd->volt_data[i].volt_nominal == volt) | ||
| 1391 | return &vdd->volt_data[i]; | ||
| 1392 | } | ||
| 1393 | |||
| 1394 | pr_notice("%s: Unable to match the current voltage with the voltage" | ||
| 1395 | "table for vdd_%s\n", __func__, voltdm->name); | ||
| 1396 | |||
| 1397 | return ERR_PTR(-ENODATA); | ||
| 1398 | } | ||
| 1399 | |||
| 1400 | /** | ||
| 1401 | * omap_voltage_register_pmic() - API to register PMIC specific data | ||
| 1402 | * @voltdm: pointer to the VDD for which the PMIC specific data is | ||
| 1403 | * to be registered | ||
| 1404 | * @pmic_info: the structure containing pmic info | ||
| 1405 | * | ||
| 1406 | * This API is to be called by the SOC/PMIC file to specify the | ||
| 1407 | * pmic specific info as present in omap_volt_pmic_info structure. | ||
| 1408 | */ | ||
| 1409 | int omap_voltage_register_pmic(struct voltagedomain *voltdm, | ||
| 1410 | struct omap_volt_pmic_info *pmic_info) | ||
| 1411 | { | ||
| 1412 | struct omap_vdd_info *vdd; | ||
| 1413 | |||
| 1414 | if (!voltdm || IS_ERR(voltdm)) { | ||
| 1415 | pr_warning("%s: VDD specified does not exist!\n", __func__); | ||
| 1416 | return -EINVAL; | ||
| 1417 | } | ||
| 1418 | |||
| 1419 | vdd = container_of(voltdm, struct omap_vdd_info, voltdm); | ||
| 1420 | |||
| 1421 | vdd->pmic_info = pmic_info; | ||
| 1422 | |||
| 1423 | return 0; | ||
| 1424 | } | ||
| 1425 | |||
| 1426 | /** | ||
| 1427 | * omap_voltage_get_dbgdir() - API to get pointer to the debugfs directory | ||
| 1428 | * corresponding to a voltage domain. | ||
| 1429 | * | ||
| 1430 | * @voltdm: pointer to the VDD whose debug directory is required. | ||
| 1431 | * | ||
| 1432 | * This API returns pointer to the debugfs directory corresponding | ||
| 1433 | * to the voltage domain. Should be used by drivers requiring to | ||
| 1434 | * add any debug entry for a particular voltage domain. Returns NULL | ||
| 1435 | * in case of error. | ||
| 1436 | */ | ||
| 1437 | struct dentry *omap_voltage_get_dbgdir(struct voltagedomain *voltdm) | ||
| 1438 | { | ||
| 1439 | struct omap_vdd_info *vdd; | ||
| 1440 | |||
| 1441 | if (!voltdm || IS_ERR(voltdm)) { | ||
| 1442 | pr_warning("%s: VDD specified does not exist!\n", __func__); | ||
| 1443 | return NULL; | ||
| 1444 | } | ||
| 1445 | |||
| 1446 | vdd = container_of(voltdm, struct omap_vdd_info, voltdm); | ||
| 1447 | |||
| 1448 | return vdd->debug_dir; | ||
| 1449 | } | ||
| 1450 | |||
| 1451 | /** | ||
| 1452 | * omap_change_voltscale_method() - API to change the voltage scaling method. | ||
| 1453 | * @voltdm: pointer to the VDD whose voltage scaling method | ||
| 1454 | * has to be changed. | ||
| 1455 | * @voltscale_method: the method to be used for voltage scaling. | ||
| 1456 | * | ||
| 1457 | * This API can be used by the board files to change the method of voltage | ||
| 1458 | * scaling between vpforceupdate and vcbypass. The parameter values are | ||
| 1459 | * defined in voltage.h | ||
| 1460 | */ | ||
| 1461 | void omap_change_voltscale_method(struct voltagedomain *voltdm, | ||
| 1462 | int voltscale_method) | ||
| 1463 | { | ||
| 1464 | struct omap_vdd_info *vdd; | ||
| 1465 | |||
| 1466 | if (!voltdm || IS_ERR(voltdm)) { | ||
| 1467 | pr_warning("%s: VDD specified does not exist!\n", __func__); | ||
| 1468 | return; | ||
| 1469 | } | ||
| 1470 | |||
| 1471 | vdd = container_of(voltdm, struct omap_vdd_info, voltdm); | ||
| 1472 | |||
| 1473 | switch (voltscale_method) { | ||
| 1474 | case VOLTSCALE_VPFORCEUPDATE: | ||
| 1475 | vdd->volt_scale = vp_forceupdate_scale_voltage; | ||
| 1476 | return; | ||
| 1477 | case VOLTSCALE_VCBYPASS: | ||
| 1478 | vdd->volt_scale = vc_bypass_scale_voltage; | ||
| 1479 | return; | ||
| 1480 | default: | ||
| 1481 | pr_warning("%s: Trying to change the method of voltage scaling" | ||
| 1482 | "to an unsupported one!\n", __func__); | ||
| 1483 | } | ||
| 1484 | } | ||
| 1485 | |||
| 1486 | /** | ||
| 1487 | * omap_voltage_domain_lookup() - API to get the voltage domain pointer | ||
| 1488 | * @name: Name of the voltage domain | ||
| 1489 | * | ||
| 1490 | * This API looks up in the global vdd_info struct for the | ||
| 1491 | * existence of voltage domain <name>. If it exists, the API returns | ||
| 1492 | * a pointer to the voltage domain structure corresponding to the | ||
| 1493 | * VDD<name>. Else retuns error pointer. | ||
| 1494 | */ | ||
| 1495 | struct voltagedomain *omap_voltage_domain_lookup(char *name) | ||
| 1496 | { | ||
| 1497 | int i; | ||
| 1498 | |||
| 1499 | if (!vdd_info) { | ||
| 1500 | pr_err("%s: Voltage driver init not yet happened.Faulting!\n", | ||
| 1501 | __func__); | ||
| 1502 | return ERR_PTR(-EINVAL); | ||
| 1503 | } | ||
| 1504 | |||
| 1505 | if (!name) { | ||
| 1506 | pr_err("%s: No name to get the votage domain!\n", __func__); | ||
| 1507 | return ERR_PTR(-EINVAL); | ||
| 1508 | } | ||
| 1509 | |||
| 1510 | for (i = 0; i < nr_scalable_vdd; i++) { | ||
| 1511 | if (!(strcmp(name, vdd_info[i].voltdm.name))) | ||
| 1512 | return &vdd_info[i].voltdm; | ||
| 1513 | } | ||
| 1514 | |||
| 1515 | return ERR_PTR(-EINVAL); | ||
| 1516 | } | ||
| 1517 | |||
| 1518 | /** | ||
| 1519 | * omap_voltage_late_init() - Init the various voltage parameters | ||
| 1520 | * | ||
| 1521 | * This API is to be called in the later stages of the | ||
| 1522 | * system boot to init the voltage controller and | ||
| 1523 | * voltage processors. | ||
| 1524 | */ | ||
| 1525 | int __init omap_voltage_late_init(void) | ||
| 1526 | { | ||
| 1527 | int i; | ||
| 1528 | |||
| 1529 | if (!vdd_info) { | ||
| 1530 | pr_err("%s: Voltage driver support not added\n", | ||
| 1531 | __func__); | ||
| 1532 | return -EINVAL; | ||
| 1533 | } | ||
| 1534 | |||
| 1535 | voltage_dir = debugfs_create_dir("voltage", NULL); | ||
| 1536 | if (IS_ERR(voltage_dir)) | ||
| 1537 | pr_err("%s: Unable to create voltage debugfs main dir\n", | ||
| 1538 | __func__); | ||
| 1539 | for (i = 0; i < nr_scalable_vdd; i++) { | ||
| 1540 | if (vdd_data_configure(&vdd_info[i])) | ||
| 1541 | continue; | ||
| 1542 | vc_init(&vdd_info[i]); | ||
| 1543 | vp_init(&vdd_info[i]); | ||
| 1544 | vdd_debugfs_init(&vdd_info[i]); | ||
| 1545 | } | ||
| 1546 | |||
| 1547 | return 0; | ||
| 1548 | } | ||
| 1549 | |||
| 1550 | /** | ||
| 1551 | * omap_voltage_early_init()- Volatage driver early init | ||
| 1552 | */ | ||
| 1553 | static int __init omap_voltage_early_init(void) | ||
| 1554 | { | ||
| 1555 | if (cpu_is_omap34xx()) { | ||
| 1556 | vdd_info = omap3_vdd_info; | ||
| 1557 | nr_scalable_vdd = OMAP3_NR_SCALABLE_VDD; | ||
| 1558 | vc_init = omap3_vc_init; | ||
| 1559 | vdd_data_configure = omap3_vdd_data_configure; | ||
| 1560 | } else if (cpu_is_omap44xx()) { | ||
| 1561 | vdd_info = omap4_vdd_info; | ||
| 1562 | nr_scalable_vdd = OMAP4_NR_SCALABLE_VDD; | ||
| 1563 | vc_init = omap4_vc_init; | ||
| 1564 | vdd_data_configure = omap4_vdd_data_configure; | ||
| 1565 | } else { | ||
| 1566 | pr_warning("%s: voltage driver support not added\n", __func__); | ||
| 1567 | } | ||
| 1568 | |||
| 1569 | return 0; | ||
| 1570 | } | ||
| 1571 | core_initcall(omap_voltage_early_init); | ||
diff --git a/arch/arm/mach-omap2/wd_timer.c b/arch/arm/mach-omap2/wd_timer.c new file mode 100644 index 000000000000..b0c4907ab3ca --- /dev/null +++ b/arch/arm/mach-omap2/wd_timer.c | |||
| @@ -0,0 +1,54 @@ | |||
| 1 | /* | ||
| 2 | * OMAP2+ MPU WD_TIMER-specific code | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include <linux/kernel.h> | ||
| 11 | #include <linux/io.h> | ||
| 12 | #include <linux/err.h> | ||
| 13 | |||
| 14 | #include <plat/omap_hwmod.h> | ||
| 15 | |||
| 16 | /* | ||
| 17 | * In order to avoid any assumptions from bootloader regarding WDT | ||
| 18 | * settings, WDT module is reset during init. This enables the watchdog | ||
| 19 | * timer. Hence it is required to disable the watchdog after the WDT reset | ||
| 20 | * during init. Otherwise the system would reboot as per the default | ||
| 21 | * watchdog timer registers settings. | ||
| 22 | */ | ||
| 23 | #define OMAP_WDT_WPS 0x34 | ||
| 24 | #define OMAP_WDT_SPR 0x48 | ||
| 25 | |||
| 26 | |||
| 27 | int omap2_wd_timer_disable(struct omap_hwmod *oh) | ||
| 28 | { | ||
| 29 | void __iomem *base; | ||
| 30 | |||
| 31 | if (!oh) { | ||
| 32 | pr_err("%s: Could not look up wdtimer_hwmod\n", __func__); | ||
| 33 | return -EINVAL; | ||
| 34 | } | ||
| 35 | |||
| 36 | base = omap_hwmod_get_mpu_rt_va(oh); | ||
| 37 | if (!base) { | ||
| 38 | pr_err("%s: Could not get the base address for %s\n", | ||
| 39 | oh->name, __func__); | ||
| 40 | return -EINVAL; | ||
| 41 | } | ||
| 42 | |||
| 43 | /* sequence required to disable watchdog */ | ||
| 44 | __raw_writel(0xAAAA, base + OMAP_WDT_SPR); | ||
| 45 | while (__raw_readl(base + OMAP_WDT_WPS) & 0x10) | ||
| 46 | cpu_relax(); | ||
| 47 | |||
| 48 | __raw_writel(0x5555, base + OMAP_WDT_SPR); | ||
| 49 | while (__raw_readl(base + OMAP_WDT_WPS) & 0x10) | ||
| 50 | cpu_relax(); | ||
| 51 | |||
| 52 | return 0; | ||
| 53 | } | ||
| 54 | |||
diff --git a/arch/arm/mach-omap2/wd_timer.h b/arch/arm/mach-omap2/wd_timer.h new file mode 100644 index 000000000000..e0054a2d5505 --- /dev/null +++ b/arch/arm/mach-omap2/wd_timer.h | |||
| @@ -0,0 +1,17 @@ | |||
| 1 | /* | ||
| 2 | * OMAP2+ MPU WD_TIMER-specific function prototypes | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __ARCH_ARM_MACH_OMAP2_WD_TIMER_H | ||
| 11 | #define __ARCH_ARM_MACH_OMAP2_WD_TIMER_H | ||
| 12 | |||
| 13 | #include <plat/omap_hwmod.h> | ||
| 14 | |||
| 15 | extern int omap2_wd_timer_disable(struct omap_hwmod *oh); | ||
| 16 | |||
| 17 | #endif | ||
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index c897e03e413d..6604fc6ca58a 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig | |||
| @@ -51,6 +51,13 @@ config MACH_LINKSTATION_PRO | |||
| 51 | Buffalo Linkstation Pro/Live platform. Both v1 and | 51 | Buffalo Linkstation Pro/Live platform. Both v1 and |
| 52 | v2 devices are supported. | 52 | v2 devices are supported. |
| 53 | 53 | ||
| 54 | config MACH_LINKSTATION_LSCHL | ||
| 55 | bool "Buffalo Linkstation Live v3 (LS-CHL)" | ||
| 56 | select I2C_BOARDINFO | ||
| 57 | help | ||
| 58 | Say 'Y' here if you want your kernel to support the | ||
| 59 | Buffalo Linkstation Live v3 (LS-CHL) platform. | ||
| 60 | |||
| 54 | config MACH_LINKSTATION_MINI | 61 | config MACH_LINKSTATION_MINI |
| 55 | bool "Buffalo Linkstation Mini" | 62 | bool "Buffalo Linkstation Mini" |
| 56 | select I2C_BOARDINFO | 63 | select I2C_BOARDINFO |
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index eb6eabcb41e4..7f18cdacd487 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile | |||
| @@ -21,3 +21,4 @@ obj-$(CONFIG_MACH_WNR854T) += wnr854t-setup.o | |||
| 21 | obj-$(CONFIG_MACH_RD88F5181L_GE) += rd88f5181l-ge-setup.o | 21 | obj-$(CONFIG_MACH_RD88F5181L_GE) += rd88f5181l-ge-setup.o |
| 22 | obj-$(CONFIG_MACH_RD88F5181L_FXO) += rd88f5181l-fxo-setup.o | 22 | obj-$(CONFIG_MACH_RD88F5181L_FXO) += rd88f5181l-fxo-setup.o |
| 23 | obj-$(CONFIG_MACH_RD88F6183AP_GE) += rd88f6183ap-ge-setup.o | 23 | obj-$(CONFIG_MACH_RD88F6183AP_GE) += rd88f6183ap-ge-setup.o |
| 24 | obj-$(CONFIG_MACH_LINKSTATION_LSCHL) += ls-chl-setup.o | ||
diff --git a/arch/arm/mach-orion5x/include/mach/io.h b/arch/arm/mach-orion5x/include/mach/io.h index c47b033bd999..c5196101a237 100644 --- a/arch/arm/mach-orion5x/include/mach/io.h +++ b/arch/arm/mach-orion5x/include/mach/io.h | |||
| @@ -38,8 +38,8 @@ __arch_iounmap(void __iomem *addr) | |||
| 38 | __iounmap(addr); | 38 | __iounmap(addr); |
| 39 | } | 39 | } |
| 40 | 40 | ||
| 41 | #define __arch_ioremap(p, s, m) __arch_ioremap(p, s, m) | 41 | #define __arch_ioremap __arch_ioremap |
| 42 | #define __arch_iounmap(a) __arch_iounmap(a) | 42 | #define __arch_iounmap __arch_iounmap |
| 43 | #define __io(a) __typesafe_io(a) | 43 | #define __io(a) __typesafe_io(a) |
| 44 | #define __mem_pci(a) (a) | 44 | #define __mem_pci(a) (a) |
| 45 | 45 | ||
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c new file mode 100644 index 000000000000..20a9b66cbafa --- /dev/null +++ b/arch/arm/mach-orion5x/ls-chl-setup.c | |||
| @@ -0,0 +1,327 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-orion5x/ls-chl-setup.c | ||
| 3 | * | ||
| 4 | * Maintainer: Ash Hughes <ashley.hughes@blueyonder.co.uk> | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/platform_device.h> | ||
| 14 | #include <linux/mtd/physmap.h> | ||
| 15 | #include <linux/mv643xx_eth.h> | ||
| 16 | #include <linux/leds.h> | ||
| 17 | #include <linux/gpio_keys.h> | ||
| 18 | #include <linux/gpio-fan.h> | ||
| 19 | #include <linux/input.h> | ||
| 20 | #include <linux/i2c.h> | ||
| 21 | #include <linux/ata_platform.h> | ||
| 22 | #include <linux/gpio.h> | ||
| 23 | #include <asm/mach-types.h> | ||
| 24 | #include <asm/mach/arch.h> | ||
| 25 | #include <asm/system.h> | ||
| 26 | #include <mach/orion5x.h> | ||
| 27 | #include "common.h" | ||
| 28 | #include "mpp.h" | ||
| 29 | |||
| 30 | /***************************************************************************** | ||
| 31 | * Linkstation LS-CHL Info | ||
| 32 | ****************************************************************************/ | ||
| 33 | |||
| 34 | /* | ||
| 35 | * 256K NOR flash Device bus boot chip select | ||
| 36 | */ | ||
| 37 | |||
| 38 | #define LSCHL_NOR_BOOT_BASE 0xf4000000 | ||
| 39 | #define LSCHL_NOR_BOOT_SIZE SZ_256K | ||
| 40 | |||
| 41 | /***************************************************************************** | ||
| 42 | * 256KB NOR Flash on BOOT Device | ||
| 43 | ****************************************************************************/ | ||
| 44 | |||
| 45 | static struct physmap_flash_data lschl_nor_flash_data = { | ||
| 46 | .width = 1, | ||
| 47 | }; | ||
| 48 | |||
| 49 | static struct resource lschl_nor_flash_resource = { | ||
| 50 | .flags = IORESOURCE_MEM, | ||
| 51 | .start = LSCHL_NOR_BOOT_BASE, | ||
| 52 | .end = LSCHL_NOR_BOOT_BASE + LSCHL_NOR_BOOT_SIZE - 1, | ||
| 53 | }; | ||
| 54 | |||
| 55 | static struct platform_device lschl_nor_flash = { | ||
| 56 | .name = "physmap-flash", | ||
| 57 | .id = 0, | ||
| 58 | .dev = { | ||
| 59 | .platform_data = &lschl_nor_flash_data, | ||
| 60 | }, | ||
| 61 | .num_resources = 1, | ||
| 62 | .resource = &lschl_nor_flash_resource, | ||
| 63 | }; | ||
| 64 | |||
| 65 | /***************************************************************************** | ||
| 66 | * Ethernet | ||
| 67 | ****************************************************************************/ | ||
| 68 | |||
| 69 | static struct mv643xx_eth_platform_data lschl_eth_data = { | ||
| 70 | .phy_addr = MV643XX_ETH_PHY_ADDR(8), | ||
| 71 | }; | ||
| 72 | |||
| 73 | /***************************************************************************** | ||
| 74 | * RTC 5C372a on I2C bus | ||
| 75 | ****************************************************************************/ | ||
| 76 | |||
| 77 | static struct i2c_board_info __initdata lschl_i2c_rtc = { | ||
| 78 | I2C_BOARD_INFO("rs5c372a", 0x32), | ||
| 79 | }; | ||
| 80 | |||
| 81 | /***************************************************************************** | ||
| 82 | * LEDs attached to GPIO | ||
| 83 | ****************************************************************************/ | ||
| 84 | |||
| 85 | #define LSCHL_GPIO_LED_ALARM 2 | ||
| 86 | #define LSCHL_GPIO_LED_INFO 3 | ||
| 87 | #define LSCHL_GPIO_LED_FUNC 17 | ||
| 88 | #define LSCHL_GPIO_LED_PWR 0 | ||
| 89 | |||
| 90 | static struct gpio_led lschl_led_pins[] = { | ||
| 91 | { | ||
| 92 | .name = "alarm:red", | ||
| 93 | .gpio = LSCHL_GPIO_LED_ALARM, | ||
| 94 | .active_low = 1, | ||
| 95 | }, { | ||
| 96 | .name = "info:amber", | ||
| 97 | .gpio = LSCHL_GPIO_LED_INFO, | ||
| 98 | .active_low = 1, | ||
| 99 | }, { | ||
| 100 | .name = "func:blue:top", | ||
| 101 | .gpio = LSCHL_GPIO_LED_FUNC, | ||
| 102 | .active_low = 1, | ||
| 103 | }, { | ||
| 104 | .name = "power:blue:bottom", | ||
| 105 | .gpio = LSCHL_GPIO_LED_PWR, | ||
| 106 | }, | ||
| 107 | }; | ||
| 108 | |||
| 109 | static struct gpio_led_platform_data lschl_led_data = { | ||
| 110 | .leds = lschl_led_pins, | ||
| 111 | .num_leds = ARRAY_SIZE(lschl_led_pins), | ||
| 112 | }; | ||
| 113 | |||
| 114 | static struct platform_device lschl_leds = { | ||
| 115 | .name = "leds-gpio", | ||
| 116 | .id = -1, | ||
| 117 | .dev = { | ||
| 118 | .platform_data = &lschl_led_data, | ||
| 119 | }, | ||
| 120 | }; | ||
| 121 | |||
| 122 | /***************************************************************************** | ||
| 123 | * SATA | ||
| 124 | ****************************************************************************/ | ||
| 125 | static struct mv_sata_platform_data lschl_sata_data = { | ||
| 126 | .n_ports = 2, | ||
| 127 | }; | ||
| 128 | |||
| 129 | /***************************************************************************** | ||
| 130 | * LS-CHL specific power off method: reboot | ||
| 131 | ****************************************************************************/ | ||
| 132 | /* | ||
| 133 | * On the LS-CHL, the shutdown process is following: | ||
| 134 | * - Userland monitors key events until the power switch goes to off position | ||
| 135 | * - The board reboots | ||
| 136 | * - U-boot starts and goes into an idle mode waiting for the user | ||
| 137 | * to move the switch to ON position | ||
| 138 | * | ||
| 139 | */ | ||
| 140 | |||
| 141 | static void lschl_power_off(void) | ||
| 142 | { | ||
| 143 | arm_machine_restart('h', NULL); | ||
| 144 | } | ||
| 145 | |||
| 146 | /***************************************************************************** | ||
| 147 | * General Setup | ||
| 148 | ****************************************************************************/ | ||
| 149 | #define LSCHL_GPIO_USB_POWER 9 | ||
| 150 | #define LSCHL_GPIO_AUTO_POWER 17 | ||
| 151 | #define LSCHL_GPIO_POWER 18 | ||
| 152 | |||
| 153 | /**************************************************************************** | ||
| 154 | * GPIO Attached Keys | ||
| 155 | ****************************************************************************/ | ||
| 156 | #define LSCHL_GPIO_KEY_FUNC 15 | ||
| 157 | #define LSCHL_GPIO_KEY_POWER 8 | ||
| 158 | #define LSCHL_GPIO_KEY_AUTOPOWER 10 | ||
| 159 | #define LSCHL_SW_POWER 0x00 | ||
| 160 | #define LSCHL_SW_AUTOPOWER 0x01 | ||
| 161 | #define LSCHL_SW_FUNC 0x02 | ||
| 162 | |||
| 163 | static struct gpio_keys_button lschl_buttons[] = { | ||
| 164 | { | ||
| 165 | .type = EV_SW, | ||
| 166 | .code = LSCHL_SW_POWER, | ||
| 167 | .gpio = LSCHL_GPIO_KEY_POWER, | ||
| 168 | .desc = "Power-on Switch", | ||
| 169 | .active_low = 1, | ||
| 170 | }, { | ||
| 171 | .type = EV_SW, | ||
| 172 | .code = LSCHL_SW_AUTOPOWER, | ||
| 173 | .gpio = LSCHL_GPIO_KEY_AUTOPOWER, | ||
| 174 | .desc = "Power-auto Switch", | ||
| 175 | .active_low = 1, | ||
| 176 | }, { | ||
| 177 | .type = EV_SW, | ||
| 178 | .code = LSCHL_SW_FUNC, | ||
| 179 | .gpio = LSCHL_GPIO_KEY_FUNC, | ||
| 180 | .desc = "Function Switch", | ||
| 181 | .active_low = 1, | ||
| 182 | }, | ||
| 183 | }; | ||
| 184 | |||
| 185 | static struct gpio_keys_platform_data lschl_button_data = { | ||
| 186 | .buttons = lschl_buttons, | ||
| 187 | .nbuttons = ARRAY_SIZE(lschl_buttons), | ||
| 188 | }; | ||
| 189 | |||
| 190 | static struct platform_device lschl_button_device = { | ||
| 191 | .name = "gpio-keys", | ||
| 192 | .id = -1, | ||
| 193 | .num_resources = 0, | ||
| 194 | .dev = { | ||
| 195 | .platform_data = &lschl_button_data, | ||
| 196 | }, | ||
| 197 | }; | ||
| 198 | |||
| 199 | #define LSCHL_GPIO_HDD_POWER 1 | ||
| 200 | |||
| 201 | /**************************************************************************** | ||
| 202 | * GPIO Fan | ||
| 203 | ****************************************************************************/ | ||
| 204 | |||
| 205 | #define LSCHL_GPIO_FAN_LOW 16 | ||
| 206 | #define LSCHL_GPIO_FAN_HIGH 14 | ||
| 207 | #define LSCHL_GPIO_FAN_LOCK 6 | ||
| 208 | |||
| 209 | static struct gpio_fan_alarm lschl_alarm = { | ||
| 210 | .gpio = LSCHL_GPIO_FAN_LOCK, | ||
| 211 | }; | ||
| 212 | |||
| 213 | static struct gpio_fan_speed lschl_speeds[] = { | ||
| 214 | { | ||
| 215 | .rpm = 0, | ||
| 216 | .ctrl_val = 3, | ||
| 217 | }, { | ||
| 218 | .rpm = 1500, | ||
| 219 | .ctrl_val = 2, | ||
| 220 | }, { | ||
| 221 | .rpm = 3250, | ||
| 222 | .ctrl_val = 1, | ||
| 223 | }, { | ||
| 224 | .rpm = 5000, | ||
| 225 | .ctrl_val = 0, | ||
| 226 | }, | ||
| 227 | }; | ||
| 228 | |||
| 229 | static int lschl_gpio_list[] = { | ||
| 230 | LSCHL_GPIO_FAN_HIGH, LSCHL_GPIO_FAN_LOW, | ||
| 231 | }; | ||
| 232 | |||
| 233 | static struct gpio_fan_platform_data lschl_fan_data = { | ||
| 234 | .num_ctrl = ARRAY_SIZE(lschl_gpio_list), | ||
| 235 | .ctrl = lschl_gpio_list, | ||
| 236 | .alarm = &lschl_alarm, | ||
| 237 | .num_speed = ARRAY_SIZE(lschl_speeds), | ||
| 238 | .speed = lschl_speeds, | ||
| 239 | }; | ||
| 240 | |||
| 241 | static struct platform_device lschl_fan_device = { | ||
| 242 | .name = "gpio-fan", | ||
| 243 | .id = -1, | ||
| 244 | .num_resources = 0, | ||
| 245 | .dev = { | ||
| 246 | .platform_data = &lschl_fan_data, | ||
| 247 | }, | ||
| 248 | }; | ||
| 249 | |||
| 250 | /**************************************************************************** | ||
| 251 | * GPIO Data | ||
| 252 | ****************************************************************************/ | ||
| 253 | |||
| 254 | static struct orion5x_mpp_mode lschl_mpp_modes[] __initdata = { | ||
| 255 | { 0, MPP_GPIO }, /* LED POWER */ | ||
| 256 | { 1, MPP_GPIO }, /* HDD POWER */ | ||
| 257 | { 2, MPP_GPIO }, /* LED ALARM */ | ||
| 258 | { 3, MPP_GPIO }, /* LED INFO */ | ||
| 259 | { 4, MPP_UNUSED }, | ||
| 260 | { 5, MPP_UNUSED }, | ||
| 261 | { 6, MPP_GPIO }, /* FAN LOCK */ | ||
| 262 | { 7, MPP_GPIO }, /* SW INIT */ | ||
| 263 | { 8, MPP_GPIO }, /* SW POWER */ | ||
| 264 | { 9, MPP_GPIO }, /* USB POWER */ | ||
| 265 | { 10, MPP_GPIO }, /* SW AUTO POWER */ | ||
| 266 | { 11, MPP_UNUSED }, | ||
| 267 | { 12, MPP_UNUSED }, | ||
| 268 | { 13, MPP_UNUSED }, | ||
| 269 | { 14, MPP_GPIO }, /* FAN HIGH */ | ||
| 270 | { 15, MPP_GPIO }, /* SW FUNC */ | ||
| 271 | { 16, MPP_GPIO }, /* FAN LOW */ | ||
| 272 | { 17, MPP_GPIO }, /* LED FUNC */ | ||
| 273 | { 18, MPP_UNUSED }, | ||
| 274 | { 19, MPP_UNUSED }, | ||
| 275 | { -1 }, | ||
| 276 | }; | ||
| 277 | |||
| 278 | static void __init lschl_init(void) | ||
| 279 | { | ||
| 280 | /* | ||
| 281 | * Setup basic Orion functions. Needs to be called early. | ||
| 282 | */ | ||
| 283 | orion5x_init(); | ||
| 284 | |||
| 285 | orion5x_mpp_conf(lschl_mpp_modes); | ||
| 286 | |||
| 287 | /* | ||
| 288 | * Configure peripherals. | ||
| 289 | */ | ||
| 290 | orion5x_ehci0_init(); | ||
| 291 | orion5x_ehci1_init(); | ||
| 292 | orion5x_eth_init(&lschl_eth_data); | ||
| 293 | orion5x_i2c_init(); | ||
| 294 | orion5x_sata_init(&lschl_sata_data); | ||
| 295 | orion5x_uart0_init(); | ||
| 296 | orion5x_xor_init(); | ||
| 297 | |||
| 298 | orion5x_setup_dev_boot_win(LSCHL_NOR_BOOT_BASE, | ||
| 299 | LSCHL_NOR_BOOT_SIZE); | ||
| 300 | platform_device_register(&lschl_nor_flash); | ||
| 301 | |||
| 302 | platform_device_register(&lschl_leds); | ||
| 303 | |||
| 304 | platform_device_register(&lschl_button_device); | ||
| 305 | |||
| 306 | platform_device_register(&lschl_fan_device); | ||
| 307 | |||
| 308 | i2c_register_board_info(0, &lschl_i2c_rtc, 1); | ||
| 309 | |||
| 310 | /* usb power on */ | ||
| 311 | gpio_set_value(LSCHL_GPIO_USB_POWER, 1); | ||
| 312 | |||
| 313 | /* register power-off method */ | ||
| 314 | pm_power_off = lschl_power_off; | ||
| 315 | |||
| 316 | pr_info("%s: finished\n", __func__); | ||
| 317 | } | ||
| 318 | |||
| 319 | MACHINE_START(LINKSTATION_LSCHL, "Buffalo Linkstation LiveV3 (LS-CHL)") | ||
| 320 | /* Maintainer: Ash Hughes <ashley.hughes@blueyonder.co.uk> */ | ||
| 321 | .boot_params = 0x00000100, | ||
| 322 | .init_machine = lschl_init, | ||
| 323 | .map_io = orion5x_map_io, | ||
| 324 | .init_irq = orion5x_init_irq, | ||
| 325 | .timer = &orion5x_timer, | ||
| 326 | .fixup = tag_fixup_mem32, | ||
| 327 | MACHINE_END | ||
diff --git a/arch/arm/mach-pnx4008/clock.c b/arch/arm/mach-pnx4008/clock.c index 9d1975fa4d9f..a4a3819c96cb 100644 --- a/arch/arm/mach-pnx4008/clock.c +++ b/arch/arm/mach-pnx4008/clock.c | |||
| @@ -21,8 +21,7 @@ | |||
| 21 | #include <linux/err.h> | 21 | #include <linux/err.h> |
| 22 | #include <linux/delay.h> | 22 | #include <linux/delay.h> |
| 23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
| 24 | 24 | #include <linux/clkdev.h> | |
| 25 | #include <asm/clkdev.h> | ||
| 26 | 25 | ||
| 27 | #include <mach/hardware.h> | 26 | #include <mach/hardware.h> |
| 28 | #include <mach/clock.h> | 27 | #include <mach/clock.h> |
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index c93e73d54dd1..2fc9f94cdd29 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig | |||
| @@ -50,6 +50,10 @@ config MACH_SAAR | |||
| 50 | select PXA3xx | 50 | select PXA3xx |
| 51 | select CPU_PXA930 | 51 | select CPU_PXA930 |
| 52 | 52 | ||
| 53 | config MACH_SAARB | ||
| 54 | bool "PXA955 Handheld Platform (aka SAARB)" | ||
| 55 | select CPU_PXA955 | ||
| 56 | |||
| 53 | comment "Third Party Dev Platforms (sorted by vendor name)" | 57 | comment "Third Party Dev Platforms (sorted by vendor name)" |
| 54 | 58 | ||
| 55 | config ARCH_PXA_IDP | 59 | config ARCH_PXA_IDP |
| @@ -94,6 +98,7 @@ config MACH_ARMCORE | |||
| 94 | select PXA27x | 98 | select PXA27x |
| 95 | select IWMMXT | 99 | select IWMMXT |
| 96 | select PXA25x | 100 | select PXA25x |
| 101 | select MIGHT_HAVE_PCI | ||
| 97 | 102 | ||
| 98 | config MACH_EM_X270 | 103 | config MACH_EM_X270 |
| 99 | bool "CompuLab EM-x270 platform" | 104 | bool "CompuLab EM-x270 platform" |
| @@ -232,10 +237,6 @@ config MACH_COLIBRI | |||
| 232 | bool "Toradex Colibri PXA270" | 237 | bool "Toradex Colibri PXA270" |
| 233 | select PXA27x | 238 | select PXA27x |
| 234 | 239 | ||
| 235 | config MACH_COLIBRI_PXA270_EVALBOARD | ||
| 236 | bool "Toradex Colibri Evaluation Carrier Board support (PXA270)" | ||
| 237 | depends on MACH_COLIBRI | ||
| 238 | |||
| 239 | config MACH_COLIBRI_PXA270_INCOME | 240 | config MACH_COLIBRI_PXA270_INCOME |
| 240 | bool "Income s.r.o. PXA270 SBC" | 241 | bool "Income s.r.o. PXA270 SBC" |
| 241 | depends on MACH_COLIBRI | 242 | depends on MACH_COLIBRI |
| @@ -253,6 +254,10 @@ config MACH_COLIBRI320 | |||
| 253 | select PXA3xx | 254 | select PXA3xx |
| 254 | select CPU_PXA320 | 255 | select CPU_PXA320 |
| 255 | 256 | ||
| 257 | config MACH_COLIBRI_EVALBOARD | ||
| 258 | bool "Toradex Colibri Evaluation Carrier Board support" | ||
| 259 | depends on MACH_COLIBRI || MACH_COLIBRI300 || MACH_COLIBRI320 | ||
| 260 | |||
| 256 | config MACH_VPAC270 | 261 | config MACH_VPAC270 |
| 257 | bool "Voipac PXA270" | 262 | bool "Voipac PXA270" |
| 258 | select PXA27x | 263 | select PXA27x |
| @@ -652,11 +657,17 @@ config CPU_PXA935 | |||
| 652 | help | 657 | help |
| 653 | PXA935 (codename Tavor-P65) | 658 | PXA935 (codename Tavor-P65) |
| 654 | 659 | ||
| 655 | config CPU_PXA950 | 660 | config PXA95x |
| 656 | bool | 661 | bool |
| 657 | select CPU_PXA930 | 662 | select CPU_PJ4 |
| 663 | help | ||
| 664 | Select code specific to PXA95x variants | ||
| 665 | |||
| 666 | config CPU_PXA955 | ||
| 667 | bool | ||
| 668 | select PXA95x | ||
| 658 | help | 669 | help |
| 659 | PXA950 (codename Tavor-PV2) | 670 | PXA950 (codename MG1) |
| 660 | 671 | ||
| 661 | config PXA_SHARP_C7xx | 672 | config PXA_SHARP_C7xx |
| 662 | bool | 673 | bool |
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index e2f89c2c6f49..cc39d17b2e07 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile | |||
| @@ -16,9 +16,10 @@ endif | |||
| 16 | # Generic drivers that other drivers may depend upon | 16 | # Generic drivers that other drivers may depend upon |
| 17 | 17 | ||
| 18 | # SoC-specific code | 18 | # SoC-specific code |
| 19 | obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o pxa2xx.o pxa25x.o | 19 | obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa25x.o |
| 20 | obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o pxa2xx.o pxa27x.o | 20 | obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa27x.o |
| 21 | obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o | 21 | obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o clock-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o |
| 22 | obj-$(CONFIG_PXA95x) += mfp-pxa3xx.o clock-pxa3xx.o pxa95x.o smemc.o | ||
| 22 | obj-$(CONFIG_CPU_PXA300) += pxa300.o | 23 | obj-$(CONFIG_CPU_PXA300) += pxa300.o |
| 23 | obj-$(CONFIG_CPU_PXA320) += pxa320.o | 24 | obj-$(CONFIG_CPU_PXA320) += pxa320.o |
| 24 | obj-$(CONFIG_CPU_PXA930) += pxa930.o | 25 | obj-$(CONFIG_CPU_PXA930) += pxa930.o |
| @@ -34,6 +35,7 @@ obj-$(CONFIG_MACH_LITTLETON) += littleton.o | |||
| 34 | obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o | 35 | obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o |
| 35 | obj-$(CONFIG_MACH_TAVOREVB3) += tavorevb3.o | 36 | obj-$(CONFIG_MACH_TAVOREVB3) += tavorevb3.o |
| 36 | obj-$(CONFIG_MACH_SAAR) += saar.o | 37 | obj-$(CONFIG_MACH_SAAR) += saar.o |
| 38 | obj-$(CONFIG_MACH_SAARB) += saarb.o | ||
| 37 | 39 | ||
| 38 | # 3rd Party Dev Platforms | 40 | # 3rd Party Dev Platforms |
| 39 | obj-$(CONFIG_ARCH_PXA_IDP) += idp.o | 41 | obj-$(CONFIG_ARCH_PXA_IDP) += idp.o |
| @@ -60,7 +62,7 @@ obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o | |||
| 60 | obj-$(CONFIG_MACH_PCM027) += pcm027.o | 62 | obj-$(CONFIG_MACH_PCM027) += pcm027.o |
| 61 | obj-$(CONFIG_MACH_PCM990_BASEBOARD) += pcm990-baseboard.o | 63 | obj-$(CONFIG_MACH_PCM990_BASEBOARD) += pcm990-baseboard.o |
| 62 | obj-$(CONFIG_MACH_COLIBRI) += colibri-pxa270.o | 64 | obj-$(CONFIG_MACH_COLIBRI) += colibri-pxa270.o |
| 63 | obj-$(CONFIG_MACH_COLIBRI_PXA270_EVALBOARD) += colibri-pxa270-evalboard.o | 65 | obj-$(CONFIG_MACH_COLIBRI_EVALBOARD) += colibri-evalboard.o |
| 64 | obj-$(CONFIG_MACH_COLIBRI_PXA270_INCOME) += colibri-pxa270-income.o | 66 | obj-$(CONFIG_MACH_COLIBRI_PXA270_INCOME) += colibri-pxa270-income.o |
| 65 | obj-$(CONFIG_MACH_COLIBRI300) += colibri-pxa3xx.o colibri-pxa300.o | 67 | obj-$(CONFIG_MACH_COLIBRI300) += colibri-pxa3xx.o colibri-pxa300.o |
| 66 | obj-$(CONFIG_MACH_COLIBRI320) += colibri-pxa3xx.o colibri-pxa320.o | 68 | obj-$(CONFIG_MACH_COLIBRI320) += colibri-pxa3xx.o colibri-pxa320.o |
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c index 21e188901935..ccb2d0cebcc3 100644 --- a/arch/arm/mach-pxa/balloon3.c +++ b/arch/arm/mach-pxa/balloon3.c | |||
| @@ -567,27 +567,29 @@ static inline void balloon3_i2c_init(void) {} | |||
| 567 | * NAND | 567 | * NAND |
| 568 | ******************************************************************************/ | 568 | ******************************************************************************/ |
| 569 | #if defined(CONFIG_MTD_NAND_PLATFORM)||defined(CONFIG_MTD_NAND_PLATFORM_MODULE) | 569 | #if defined(CONFIG_MTD_NAND_PLATFORM)||defined(CONFIG_MTD_NAND_PLATFORM_MODULE) |
| 570 | static uint16_t balloon3_ctl = | ||
| 571 | BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 | | ||
| 572 | BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3 | | ||
| 573 | BALLOON3_NAND_CONTROL_FLWP; | ||
| 574 | |||
| 575 | static void balloon3_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl) | 570 | static void balloon3_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
| 576 | { | 571 | { |
| 577 | struct nand_chip *this = mtd->priv; | 572 | struct nand_chip *this = mtd->priv; |
| 573 | uint8_t balloon3_ctl_set = 0, balloon3_ctl_clr = 0; | ||
| 578 | 574 | ||
| 579 | if (ctrl & NAND_CTRL_CHANGE) { | 575 | if (ctrl & NAND_CTRL_CHANGE) { |
| 580 | if (ctrl & NAND_CLE) | 576 | if (ctrl & NAND_CLE) |
| 581 | balloon3_ctl |= BALLOON3_NAND_CONTROL_FLCLE; | 577 | balloon3_ctl_set |= BALLOON3_NAND_CONTROL_FLCLE; |
| 582 | else | 578 | else |
| 583 | balloon3_ctl &= ~BALLOON3_NAND_CONTROL_FLCLE; | 579 | balloon3_ctl_clr |= BALLOON3_NAND_CONTROL_FLCLE; |
| 584 | 580 | ||
| 585 | if (ctrl & NAND_ALE) | 581 | if (ctrl & NAND_ALE) |
| 586 | balloon3_ctl |= BALLOON3_NAND_CONTROL_FLALE; | 582 | balloon3_ctl_set |= BALLOON3_NAND_CONTROL_FLALE; |
| 587 | else | 583 | else |
| 588 | balloon3_ctl &= ~BALLOON3_NAND_CONTROL_FLALE; | 584 | balloon3_ctl_clr |= BALLOON3_NAND_CONTROL_FLALE; |
| 589 | 585 | ||
| 590 | __raw_writel(balloon3_ctl, BALLOON3_NAND_CONTROL_REG); | 586 | if (balloon3_ctl_clr) |
| 587 | __raw_writel(balloon3_ctl_clr, | ||
| 588 | BALLOON3_NAND_CONTROL_REG); | ||
| 589 | if (balloon3_ctl_set) | ||
| 590 | __raw_writel(balloon3_ctl_set, | ||
| 591 | BALLOON3_NAND_CONTROL_REG | | ||
| 592 | BALLOON3_FPGA_SETnCLR); | ||
| 591 | } | 593 | } |
| 592 | 594 | ||
| 593 | if (cmd != NAND_CMD_NONE) | 595 | if (cmd != NAND_CMD_NONE) |
| @@ -599,28 +601,33 @@ static void balloon3_nand_select_chip(struct mtd_info *mtd, int chip) | |||
| 599 | if (chip < 0 || chip > 3) | 601 | if (chip < 0 || chip > 3) |
| 600 | return; | 602 | return; |
| 601 | 603 | ||
| 602 | balloon3_ctl |= BALLOON3_NAND_CONTROL_FLCE0 | | 604 | /* Assert all nCE lines */ |
| 603 | BALLOON3_NAND_CONTROL_FLCE1 | | 605 | __raw_writew( |
| 604 | BALLOON3_NAND_CONTROL_FLCE2 | | 606 | BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 | |
| 605 | BALLOON3_NAND_CONTROL_FLCE3; | 607 | BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3, |
| 608 | BALLOON3_NAND_CONTROL_REG | BALLOON3_FPGA_SETnCLR); | ||
| 606 | 609 | ||
| 607 | /* Deassert correct nCE line */ | 610 | /* Deassert correct nCE line */ |
| 608 | balloon3_ctl &= ~(BALLOON3_NAND_CONTROL_FLCE0 << chip); | 611 | __raw_writew(BALLOON3_NAND_CONTROL_FLCE0 << chip, |
| 612 | BALLOON3_NAND_CONTROL_REG); | ||
| 613 | } | ||
| 609 | 614 | ||
| 610 | __raw_writew(balloon3_ctl, BALLOON3_NAND_CONTROL_REG); | 615 | static int balloon3_nand_dev_ready(struct mtd_info *mtd) |
| 616 | { | ||
| 617 | return __raw_readl(BALLOON3_NAND_STAT_REG) & BALLOON3_NAND_STAT_RNB; | ||
| 611 | } | 618 | } |
| 612 | 619 | ||
| 613 | static int balloon3_nand_probe(struct platform_device *pdev) | 620 | static int balloon3_nand_probe(struct platform_device *pdev) |
| 614 | { | 621 | { |
| 615 | void __iomem *temp_map; | ||
| 616 | uint16_t ver; | 622 | uint16_t ver; |
| 617 | int ret; | 623 | int ret; |
| 618 | 624 | ||
| 619 | __raw_writew(BALLOON3_NAND_CONTROL2_16BIT, BALLOON3_NAND_CONTROL2_REG); | 625 | __raw_writew(BALLOON3_NAND_CONTROL2_16BIT, |
| 626 | BALLOON3_NAND_CONTROL2_REG | BALLOON3_FPGA_SETnCLR); | ||
| 620 | 627 | ||
| 621 | ver = __raw_readw(BALLOON3_FPGA_VER); | 628 | ver = __raw_readw(BALLOON3_FPGA_VER); |
| 622 | if (ver > 0x0201) | 629 | if (ver < 0x4f08) |
| 623 | pr_warn("The FPGA code, version 0x%04x, is newer than rel-0.3. " | 630 | pr_warn("The FPGA code, version 0x%04x, is too old. " |
| 624 | "NAND support might be broken in this version!", ver); | 631 | "NAND support might be broken in this version!", ver); |
| 625 | 632 | ||
| 626 | /* Power up the NAND chips */ | 633 | /* Power up the NAND chips */ |
| @@ -635,7 +642,11 @@ static int balloon3_nand_probe(struct platform_device *pdev) | |||
| 635 | gpio_set_value(BALLOON3_GPIO_RUN_NAND, 1); | 642 | gpio_set_value(BALLOON3_GPIO_RUN_NAND, 1); |
| 636 | 643 | ||
| 637 | /* Deassert all nCE lines and write protect line */ | 644 | /* Deassert all nCE lines and write protect line */ |
| 638 | __raw_writel(balloon3_ctl, BALLOON3_NAND_CONTROL_REG); | 645 | __raw_writel( |
| 646 | BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 | | ||
| 647 | BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3 | | ||
| 648 | BALLOON3_NAND_CONTROL_FLWP, | ||
| 649 | BALLOON3_NAND_CONTROL_REG | BALLOON3_FPGA_SETnCLR); | ||
| 639 | return 0; | 650 | return 0; |
| 640 | 651 | ||
| 641 | err2: | 652 | err2: |
| @@ -677,7 +688,7 @@ struct platform_nand_data balloon3_nand_pdata = { | |||
| 677 | }, | 688 | }, |
| 678 | .ctrl = { | 689 | .ctrl = { |
| 679 | .hwcontrol = 0, | 690 | .hwcontrol = 0, |
| 680 | .dev_ready = 0, | 691 | .dev_ready = balloon3_nand_dev_ready, |
| 681 | .select_chip = balloon3_nand_select_chip, | 692 | .select_chip = balloon3_nand_select_chip, |
| 682 | .cmd_ctrl = balloon3_nand_cmd_ctl, | 693 | .cmd_ctrl = balloon3_nand_cmd_ctl, |
| 683 | .probe = balloon3_nand_probe, | 694 | .probe = balloon3_nand_probe, |
| @@ -802,7 +813,7 @@ static struct map_desc balloon3_io_desc[] __initdata = { | |||
| 802 | 813 | ||
| 803 | static void __init balloon3_map_io(void) | 814 | static void __init balloon3_map_io(void) |
| 804 | { | 815 | { |
| 805 | pxa_map_io(); | 816 | pxa27x_map_io(); |
| 806 | iotable_init(balloon3_io_desc, ARRAY_SIZE(balloon3_io_desc)); | 817 | iotable_init(balloon3_io_desc, ARRAY_SIZE(balloon3_io_desc)); |
| 807 | } | 818 | } |
| 808 | 819 | ||
diff --git a/arch/arm/mach-pxa/capc7117.c b/arch/arm/mach-pxa/capc7117.c index 4bd7a3cda48c..4284513f396a 100644 --- a/arch/arm/mach-pxa/capc7117.c +++ b/arch/arm/mach-pxa/capc7117.c | |||
| @@ -149,7 +149,7 @@ static void __init capc7117_init(void) | |||
| 149 | MACHINE_START(CAPC7117, | 149 | MACHINE_START(CAPC7117, |
| 150 | "Embedian CAPC-7117 evaluation kit based on the MXM-8x10 CoM") | 150 | "Embedian CAPC-7117 evaluation kit based on the MXM-8x10 CoM") |
| 151 | .boot_params = 0xa0000100, | 151 | .boot_params = 0xa0000100, |
| 152 | .map_io = pxa_map_io, | 152 | .map_io = pxa3xx_map_io, |
| 153 | .init_irq = pxa3xx_init_irq, | 153 | .init_irq = pxa3xx_init_irq, |
| 154 | .timer = &pxa_timer, | 154 | .timer = &pxa_timer, |
| 155 | .init_machine = capc7117_init | 155 | .init_machine = capc7117_init |
diff --git a/arch/arm/mach-pxa/clock-pxa2xx.c b/arch/arm/mach-pxa/clock-pxa2xx.c new file mode 100644 index 000000000000..1ce090448493 --- /dev/null +++ b/arch/arm/mach-pxa/clock-pxa2xx.c | |||
| @@ -0,0 +1,64 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-pxa/clock-pxa2xx.c | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <linux/module.h> | ||
| 10 | #include <linux/kernel.h> | ||
| 11 | #include <linux/init.h> | ||
| 12 | #include <linux/sysdev.h> | ||
| 13 | |||
| 14 | #include <mach/pxa2xx-regs.h> | ||
| 15 | |||
| 16 | #include "clock.h" | ||
| 17 | |||
| 18 | void clk_pxa2xx_cken_enable(struct clk *clk) | ||
| 19 | { | ||
| 20 | CKEN |= 1 << clk->cken; | ||
| 21 | } | ||
| 22 | |||
| 23 | void clk_pxa2xx_cken_disable(struct clk *clk) | ||
| 24 | { | ||
| 25 | CKEN &= ~(1 << clk->cken); | ||
| 26 | } | ||
| 27 | |||
| 28 | const struct clkops clk_pxa2xx_cken_ops = { | ||
| 29 | .enable = clk_pxa2xx_cken_enable, | ||
| 30 | .disable = clk_pxa2xx_cken_disable, | ||
| 31 | }; | ||
| 32 | |||
| 33 | #ifdef CONFIG_PM | ||
| 34 | static uint32_t saved_cken; | ||
| 35 | |||
| 36 | static int pxa2xx_clock_suspend(struct sys_device *d, pm_message_t state) | ||
| 37 | { | ||
| 38 | saved_cken = CKEN; | ||
| 39 | return 0; | ||
| 40 | } | ||
| 41 | |||
| 42 | static int pxa2xx_clock_resume(struct sys_device *d) | ||
| 43 | { | ||
| 44 | CKEN = saved_cken; | ||
| 45 | return 0; | ||
| 46 | } | ||
| 47 | #else | ||
| 48 | #define pxa2xx_clock_suspend NULL | ||
| 49 | #define pxa2xx_clock_resume NULL | ||
| 50 | #endif | ||
| 51 | |||
| 52 | struct sysdev_class pxa2xx_clock_sysclass = { | ||
| 53 | .name = "pxa2xx-clock", | ||
| 54 | .suspend = pxa2xx_clock_suspend, | ||
| 55 | .resume = pxa2xx_clock_resume, | ||
| 56 | }; | ||
| 57 | |||
| 58 | static int __init pxa2xx_clock_init(void) | ||
| 59 | { | ||
| 60 | if (cpu_is_pxa2xx()) | ||
| 61 | return sysdev_class_register(&pxa2xx_clock_sysclass); | ||
| 62 | return 0; | ||
| 63 | } | ||
| 64 | postcore_initcall(pxa2xx_clock_init); | ||
diff --git a/arch/arm/mach-pxa/clock-pxa3xx.c b/arch/arm/mach-pxa/clock-pxa3xx.c new file mode 100644 index 000000000000..1b08a34ab234 --- /dev/null +++ b/arch/arm/mach-pxa/clock-pxa3xx.c | |||
| @@ -0,0 +1,218 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-pxa/clock-pxa3xx.c | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <linux/module.h> | ||
| 10 | #include <linux/kernel.h> | ||
| 11 | #include <linux/init.h> | ||
| 12 | #include <linux/io.h> | ||
| 13 | |||
| 14 | #include <mach/smemc.h> | ||
| 15 | #include <mach/pxa3xx-regs.h> | ||
| 16 | |||
| 17 | #include "clock.h" | ||
| 18 | |||
| 19 | /* Crystal clock: 13MHz */ | ||
| 20 | #define BASE_CLK 13000000 | ||
| 21 | |||
| 22 | /* Ring Oscillator Clock: 60MHz */ | ||
| 23 | #define RO_CLK 60000000 | ||
| 24 | |||
| 25 | #define ACCR_D0CS (1 << 26) | ||
| 26 | #define ACCR_PCCE (1 << 11) | ||
| 27 | |||
| 28 | /* crystal frequency to HSIO bus frequency multiplier (HSS) */ | ||
| 29 | static unsigned char hss_mult[4] = { 8, 12, 16, 24 }; | ||
| 30 | |||
| 31 | /* | ||
| 32 | * Get the clock frequency as reflected by CCSR and the turbo flag. | ||
| 33 | * We assume these values have been applied via a fcs. | ||
| 34 | * If info is not 0 we also display the current settings. | ||
| 35 | */ | ||
| 36 | unsigned int pxa3xx_get_clk_frequency_khz(int info) | ||
| 37 | { | ||
| 38 | unsigned long acsr, xclkcfg; | ||
| 39 | unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS; | ||
| 40 | |||
| 41 | /* Read XCLKCFG register turbo bit */ | ||
| 42 | __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); | ||
| 43 | t = xclkcfg & 0x1; | ||
| 44 | |||
| 45 | acsr = ACSR; | ||
| 46 | |||
| 47 | xl = acsr & 0x1f; | ||
| 48 | xn = (acsr >> 8) & 0x7; | ||
| 49 | hss = (acsr >> 14) & 0x3; | ||
| 50 | |||
| 51 | XL = xl * BASE_CLK; | ||
| 52 | XN = xn * XL; | ||
| 53 | |||
| 54 | ro = acsr & ACCR_D0CS; | ||
| 55 | |||
| 56 | CLK = (ro) ? RO_CLK : ((t) ? XN : XL); | ||
| 57 | HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK; | ||
| 58 | |||
| 59 | if (info) { | ||
| 60 | pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n", | ||
| 61 | RO_CLK / 1000000, (RO_CLK % 1000000) / 10000, | ||
| 62 | (ro) ? "" : "in"); | ||
| 63 | pr_info("Run Mode clock: %d.%02dMHz (*%d)\n", | ||
| 64 | XL / 1000000, (XL % 1000000) / 10000, xl); | ||
| 65 | pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n", | ||
| 66 | XN / 1000000, (XN % 1000000) / 10000, xn, | ||
| 67 | (t) ? "" : "in"); | ||
| 68 | pr_info("HSIO bus clock: %d.%02dMHz\n", | ||
| 69 | HSS / 1000000, (HSS % 1000000) / 10000); | ||
| 70 | } | ||
| 71 | |||
| 72 | return CLK / 1000; | ||
| 73 | } | ||
| 74 | |||
| 75 | /* | ||
| 76 | * Return the current AC97 clock frequency. | ||
| 77 | */ | ||
| 78 | static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk) | ||
| 79 | { | ||
| 80 | unsigned long rate = 312000000; | ||
| 81 | unsigned long ac97_div; | ||
| 82 | |||
| 83 | ac97_div = AC97_DIV; | ||
| 84 | |||
| 85 | /* This may loose precision for some rates but won't for the | ||
| 86 | * standard 24.576MHz. | ||
| 87 | */ | ||
| 88 | rate /= (ac97_div >> 12) & 0x7fff; | ||
| 89 | rate *= (ac97_div & 0xfff); | ||
| 90 | |||
| 91 | return rate; | ||
| 92 | } | ||
| 93 | |||
| 94 | /* | ||
| 95 | * Return the current HSIO bus clock frequency | ||
| 96 | */ | ||
| 97 | static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) | ||
| 98 | { | ||
| 99 | unsigned long acsr; | ||
| 100 | unsigned int hss, hsio_clk; | ||
| 101 | |||
| 102 | acsr = ACSR; | ||
| 103 | |||
| 104 | hss = (acsr >> 14) & 0x3; | ||
| 105 | hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK; | ||
| 106 | |||
| 107 | return hsio_clk; | ||
| 108 | } | ||
| 109 | |||
| 110 | /* crystal frequency to static memory controller multiplier (SMCFS) */ | ||
| 111 | static unsigned int smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; | ||
| 112 | static unsigned int df_clkdiv[4] = { 1, 2, 4, 1 }; | ||
| 113 | |||
| 114 | static unsigned long clk_pxa3xx_smemc_getrate(struct clk *clk) | ||
| 115 | { | ||
| 116 | unsigned long acsr = ACSR; | ||
| 117 | unsigned long memclkcfg = __raw_readl(MEMCLKCFG); | ||
| 118 | unsigned int smcfs = (acsr >> 23) & 0x7; | ||
| 119 | |||
| 120 | return BASE_CLK * smcfs_mult[(acsr >> 23) & 0x7] / | ||
| 121 | df_clkdiv[(memclkcfg >> 16) & 0x3]; | ||
| 122 | } | ||
| 123 | |||
| 124 | void clk_pxa3xx_cken_enable(struct clk *clk) | ||
| 125 | { | ||
| 126 | unsigned long mask = 1ul << (clk->cken & 0x1f); | ||
| 127 | |||
| 128 | if (clk->cken < 32) | ||
| 129 | CKENA |= mask; | ||
| 130 | else | ||
| 131 | CKENB |= mask; | ||
| 132 | } | ||
| 133 | |||
| 134 | void clk_pxa3xx_cken_disable(struct clk *clk) | ||
| 135 | { | ||
| 136 | unsigned long mask = 1ul << (clk->cken & 0x1f); | ||
| 137 | |||
| 138 | if (clk->cken < 32) | ||
| 139 | CKENA &= ~mask; | ||
| 140 | else | ||
| 141 | CKENB &= ~mask; | ||
| 142 | } | ||
| 143 | |||
| 144 | const struct clkops clk_pxa3xx_cken_ops = { | ||
| 145 | .enable = clk_pxa3xx_cken_enable, | ||
| 146 | .disable = clk_pxa3xx_cken_disable, | ||
| 147 | }; | ||
| 148 | |||
| 149 | const struct clkops clk_pxa3xx_hsio_ops = { | ||
| 150 | .enable = clk_pxa3xx_cken_enable, | ||
| 151 | .disable = clk_pxa3xx_cken_disable, | ||
| 152 | .getrate = clk_pxa3xx_hsio_getrate, | ||
| 153 | }; | ||
| 154 | |||
| 155 | const struct clkops clk_pxa3xx_ac97_ops = { | ||
| 156 | .enable = clk_pxa3xx_cken_enable, | ||
| 157 | .disable = clk_pxa3xx_cken_disable, | ||
| 158 | .getrate = clk_pxa3xx_ac97_getrate, | ||
| 159 | }; | ||
| 160 | |||
| 161 | const struct clkops clk_pxa3xx_smemc_ops = { | ||
| 162 | .enable = clk_pxa3xx_cken_enable, | ||
| 163 | .disable = clk_pxa3xx_cken_disable, | ||
| 164 | .getrate = clk_pxa3xx_smemc_getrate, | ||
| 165 | }; | ||
| 166 | |||
| 167 | static void clk_pout_enable(struct clk *clk) | ||
| 168 | { | ||
| 169 | OSCC |= OSCC_PEN; | ||
| 170 | } | ||
| 171 | |||
| 172 | static void clk_pout_disable(struct clk *clk) | ||
| 173 | { | ||
| 174 | OSCC &= ~OSCC_PEN; | ||
| 175 | } | ||
| 176 | |||
| 177 | const struct clkops clk_pxa3xx_pout_ops = { | ||
| 178 | .enable = clk_pout_enable, | ||
| 179 | .disable = clk_pout_disable, | ||
| 180 | }; | ||
| 181 | |||
| 182 | #ifdef CONFIG_PM | ||
| 183 | static uint32_t cken[2]; | ||
| 184 | static uint32_t accr; | ||
| 185 | |||
| 186 | static int pxa3xx_clock_suspend(struct sys_device *d, pm_message_t state) | ||
| 187 | { | ||
| 188 | cken[0] = CKENA; | ||
| 189 | cken[1] = CKENB; | ||
| 190 | accr = ACCR; | ||
| 191 | return 0; | ||
| 192 | } | ||
| 193 | |||
| 194 | static int pxa3xx_clock_resume(struct sys_device *d) | ||
| 195 | { | ||
| 196 | ACCR = accr; | ||
| 197 | CKENA = cken[0]; | ||
| 198 | CKENB = cken[1]; | ||
| 199 | return 0; | ||
| 200 | } | ||
| 201 | #else | ||
| 202 | #define pxa3xx_clock_suspend NULL | ||
| 203 | #define pxa3xx_clock_resume NULL | ||
| 204 | #endif | ||
| 205 | |||
| 206 | struct sysdev_class pxa3xx_clock_sysclass = { | ||
| 207 | .name = "pxa3xx-clock", | ||
| 208 | .suspend = pxa3xx_clock_suspend, | ||
| 209 | .resume = pxa3xx_clock_resume, | ||
| 210 | }; | ||
| 211 | |||
| 212 | static int __init pxa3xx_clock_init(void) | ||
| 213 | { | ||
| 214 | if (cpu_is_pxa3xx() || cpu_is_pxa95x()) | ||
| 215 | return sysdev_class_register(&pxa3xx_clock_sysclass); | ||
| 216 | return 0; | ||
| 217 | } | ||
| 218 | postcore_initcall(pxa3xx_clock_init); | ||
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c index abba0089a2ae..d5152220ce94 100644 --- a/arch/arm/mach-pxa/clock.c +++ b/arch/arm/mach-pxa/clock.c | |||
| @@ -3,21 +3,11 @@ | |||
| 3 | */ | 3 | */ |
| 4 | #include <linux/module.h> | 4 | #include <linux/module.h> |
| 5 | #include <linux/kernel.h> | 5 | #include <linux/kernel.h> |
| 6 | #include <linux/list.h> | ||
| 7 | #include <linux/errno.h> | ||
| 8 | #include <linux/err.h> | ||
| 9 | #include <linux/string.h> | ||
| 10 | #include <linux/clk.h> | 6 | #include <linux/clk.h> |
| 11 | #include <linux/spinlock.h> | 7 | #include <linux/spinlock.h> |
| 12 | #include <linux/platform_device.h> | ||
| 13 | #include <linux/delay.h> | 8 | #include <linux/delay.h> |
| 9 | #include <linux/clkdev.h> | ||
| 14 | 10 | ||
| 15 | #include <asm/clkdev.h> | ||
| 16 | #include <mach/pxa2xx-regs.h> | ||
| 17 | #include <mach/hardware.h> | ||
| 18 | |||
| 19 | #include "devices.h" | ||
| 20 | #include "generic.h" | ||
| 21 | #include "clock.h" | 11 | #include "clock.h" |
| 22 | 12 | ||
| 23 | static DEFINE_SPINLOCK(clocks_lock); | 13 | static DEFINE_SPINLOCK(clocks_lock); |
| @@ -63,18 +53,19 @@ unsigned long clk_get_rate(struct clk *clk) | |||
| 63 | } | 53 | } |
| 64 | EXPORT_SYMBOL(clk_get_rate); | 54 | EXPORT_SYMBOL(clk_get_rate); |
| 65 | 55 | ||
| 66 | 56 | void clk_dummy_enable(struct clk *clk) | |
| 67 | void clk_cken_enable(struct clk *clk) | ||
| 68 | { | 57 | { |
| 69 | CKEN |= 1 << clk->cken; | ||
| 70 | } | 58 | } |
| 71 | 59 | ||
| 72 | void clk_cken_disable(struct clk *clk) | 60 | void clk_dummy_disable(struct clk *clk) |
| 73 | { | 61 | { |
| 74 | CKEN &= ~(1 << clk->cken); | ||
| 75 | } | 62 | } |
| 76 | 63 | ||
| 77 | const struct clkops clk_cken_ops = { | 64 | const struct clkops clk_dummy_ops = { |
| 78 | .enable = clk_cken_enable, | 65 | .enable = clk_dummy_enable, |
| 79 | .disable = clk_cken_disable, | 66 | .disable = clk_dummy_disable, |
| 67 | }; | ||
| 68 | |||
| 69 | struct clk clk_dummy = { | ||
| 70 | .ops = &clk_dummy_ops, | ||
| 80 | }; | 71 | }; |
diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h index d8488742b807..f9f349a21b54 100644 --- a/arch/arm/mach-pxa/clock.h +++ b/arch/arm/mach-pxa/clock.h | |||
| @@ -1,4 +1,5 @@ | |||
| 1 | #include <asm/clkdev.h> | 1 | #include <linux/clkdev.h> |
| 2 | #include <linux/sysdev.h> | ||
| 2 | 3 | ||
| 3 | struct clkops { | 4 | struct clkops { |
| 4 | void (*enable)(struct clk *); | 5 | void (*enable)(struct clk *); |
| @@ -14,6 +15,12 @@ struct clk { | |||
| 14 | unsigned int enabled; | 15 | unsigned int enabled; |
| 15 | }; | 16 | }; |
| 16 | 17 | ||
| 18 | void clk_dummy_enable(struct clk *); | ||
| 19 | void clk_dummy_disable(struct clk *); | ||
| 20 | |||
| 21 | extern const struct clkops clk_dummy_ops; | ||
| 22 | extern struct clk clk_dummy; | ||
| 23 | |||
| 17 | #define INIT_CLKREG(_clk,_devname,_conname) \ | 24 | #define INIT_CLKREG(_clk,_devname,_conname) \ |
| 18 | { \ | 25 | { \ |
| 19 | .clk = _clk, \ | 26 | .clk = _clk, \ |
| @@ -21,14 +28,6 @@ struct clk { | |||
| 21 | .con_id = _conname, \ | 28 | .con_id = _conname, \ |
| 22 | } | 29 | } |
| 23 | 30 | ||
| 24 | #define DEFINE_CKEN(_name, _cken, _rate, _delay) \ | ||
| 25 | struct clk clk_##_name = { \ | ||
| 26 | .ops = &clk_cken_ops, \ | ||
| 27 | .rate = _rate, \ | ||
| 28 | .cken = CKEN_##_cken, \ | ||
| 29 | .delay = _delay, \ | ||
| 30 | } | ||
| 31 | |||
| 32 | #define DEFINE_CK(_name, _cken, _ops) \ | 31 | #define DEFINE_CK(_name, _cken, _ops) \ |
| 33 | struct clk clk_##_name = { \ | 32 | struct clk clk_##_name = { \ |
| 34 | .ops = _ops, \ | 33 | .ops = _ops, \ |
| @@ -42,28 +41,38 @@ struct clk clk_##_name = { \ | |||
| 42 | .delay = _delay, \ | 41 | .delay = _delay, \ |
| 43 | } | 42 | } |
| 44 | 43 | ||
| 45 | extern const struct clkops clk_cken_ops; | 44 | #define DEFINE_PXA2_CKEN(_name, _cken, _rate, _delay) \ |
| 46 | |||
| 47 | void clk_cken_enable(struct clk *clk); | ||
| 48 | void clk_cken_disable(struct clk *clk); | ||
| 49 | |||
| 50 | #ifdef CONFIG_PXA3xx | ||
| 51 | #define DEFINE_PXA3_CKEN(_name, _cken, _rate, _delay) \ | ||
| 52 | struct clk clk_##_name = { \ | 45 | struct clk clk_##_name = { \ |
| 53 | .ops = &clk_pxa3xx_cken_ops, \ | 46 | .ops = &clk_pxa2xx_cken_ops, \ |
| 54 | .rate = _rate, \ | 47 | .rate = _rate, \ |
| 55 | .cken = CKEN_##_cken, \ | 48 | .cken = CKEN_##_cken, \ |
| 56 | .delay = _delay, \ | 49 | .delay = _delay, \ |
| 57 | } | 50 | } |
| 58 | 51 | ||
| 59 | #define DEFINE_PXA3_CK(_name, _cken, _ops) \ | 52 | extern const struct clkops clk_pxa2xx_cken_ops; |
| 53 | |||
| 54 | void clk_pxa2xx_cken_enable(struct clk *clk); | ||
| 55 | void clk_pxa2xx_cken_disable(struct clk *clk); | ||
| 56 | |||
| 57 | extern struct sysdev_class pxa2xx_clock_sysclass; | ||
| 58 | |||
| 59 | #if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x) | ||
| 60 | #define DEFINE_PXA3_CKEN(_name, _cken, _rate, _delay) \ | ||
| 60 | struct clk clk_##_name = { \ | 61 | struct clk clk_##_name = { \ |
| 61 | .ops = _ops, \ | 62 | .ops = &clk_pxa3xx_cken_ops, \ |
| 63 | .rate = _rate, \ | ||
| 62 | .cken = CKEN_##_cken, \ | 64 | .cken = CKEN_##_cken, \ |
| 65 | .delay = _delay, \ | ||
| 63 | } | 66 | } |
| 64 | 67 | ||
| 65 | extern const struct clkops clk_pxa3xx_cken_ops; | 68 | extern const struct clkops clk_pxa3xx_cken_ops; |
| 69 | extern const struct clkops clk_pxa3xx_hsio_ops; | ||
| 70 | extern const struct clkops clk_pxa3xx_ac97_ops; | ||
| 71 | extern const struct clkops clk_pxa3xx_pout_ops; | ||
| 72 | extern const struct clkops clk_pxa3xx_smemc_ops; | ||
| 73 | |||
| 66 | extern void clk_pxa3xx_cken_enable(struct clk *); | 74 | extern void clk_pxa3xx_cken_enable(struct clk *); |
| 67 | extern void clk_pxa3xx_cken_disable(struct clk *); | 75 | extern void clk_pxa3xx_cken_disable(struct clk *); |
| 68 | #endif | ||
| 69 | 76 | ||
| 77 | extern struct sysdev_class pxa3xx_clock_sysclass; | ||
| 78 | #endif | ||
diff --git a/arch/arm/mach-pxa/cm-x255.c b/arch/arm/mach-pxa/cm-x255.c index f1a7703d771b..93f59f877fc6 100644 --- a/arch/arm/mach-pxa/cm-x255.c +++ b/arch/arm/mach-pxa/cm-x255.c | |||
| @@ -17,13 +17,13 @@ | |||
| 17 | #include <linux/mtd/nand-gpio.h> | 17 | #include <linux/mtd/nand-gpio.h> |
| 18 | 18 | ||
| 19 | #include <linux/spi/spi.h> | 19 | #include <linux/spi/spi.h> |
| 20 | #include <linux/spi/pxa2xx_spi.h> | ||
| 20 | 21 | ||
| 21 | #include <asm/mach/arch.h> | 22 | #include <asm/mach/arch.h> |
| 22 | #include <asm/mach-types.h> | 23 | #include <asm/mach-types.h> |
| 23 | #include <asm/mach/map.h> | 24 | #include <asm/mach/map.h> |
| 24 | 25 | ||
| 25 | #include <mach/pxa25x.h> | 26 | #include <mach/pxa25x.h> |
| 26 | #include <mach/pxa2xx_spi.h> | ||
| 27 | 27 | ||
| 28 | #include "generic.h" | 28 | #include "generic.h" |
| 29 | 29 | ||
diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c index a9926bb75922..b88d601a8090 100644 --- a/arch/arm/mach-pxa/cm-x270.c +++ b/arch/arm/mach-pxa/cm-x270.c | |||
| @@ -19,12 +19,12 @@ | |||
| 19 | #include <video/mbxfb.h> | 19 | #include <video/mbxfb.h> |
| 20 | 20 | ||
| 21 | #include <linux/spi/spi.h> | 21 | #include <linux/spi/spi.h> |
| 22 | #include <linux/spi/pxa2xx_spi.h> | ||
| 22 | #include <linux/spi/libertas_spi.h> | 23 | #include <linux/spi/libertas_spi.h> |
| 23 | 24 | ||
| 24 | #include <mach/pxa27x.h> | 25 | #include <mach/pxa27x.h> |
| 25 | #include <mach/ohci.h> | 26 | #include <mach/ohci.h> |
| 26 | #include <mach/mmc.h> | 27 | #include <mach/mmc.h> |
| 27 | #include <mach/pxa2xx_spi.h> | ||
| 28 | 28 | ||
| 29 | #include "generic.h" | 29 | #include "generic.h" |
| 30 | 30 | ||
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c index d34b99febeb9..b734d8468168 100644 --- a/arch/arm/mach-pxa/cm-x2xx.c +++ b/arch/arm/mach-pxa/cm-x2xx.c | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | #include <mach/pxa2xx-regs.h> | 24 | #include <mach/pxa2xx-regs.h> |
| 25 | #include <mach/audio.h> | 25 | #include <mach/audio.h> |
| 26 | #include <mach/pxafb.h> | 26 | #include <mach/pxafb.h> |
| 27 | #include <mach/smemc.h> | ||
| 27 | 28 | ||
| 28 | #include <asm/hardware/it8152.h> | 29 | #include <asm/hardware/it8152.h> |
| 29 | 30 | ||
| @@ -392,9 +393,9 @@ static int cmx2xx_suspend(struct sys_device *dev, pm_message_t state) | |||
| 392 | cmx2xx_pci_suspend(); | 393 | cmx2xx_pci_suspend(); |
| 393 | 394 | ||
| 394 | /* save MSC registers */ | 395 | /* save MSC registers */ |
| 395 | sleep_save_msc[0] = MSC0; | 396 | sleep_save_msc[0] = __raw_readl(MSC0); |
| 396 | sleep_save_msc[1] = MSC1; | 397 | sleep_save_msc[1] = __raw_readl(MSC1); |
| 397 | sleep_save_msc[2] = MSC2; | 398 | sleep_save_msc[2] = __raw_readl(MSC2); |
| 398 | 399 | ||
| 399 | /* setup power saving mode registers */ | 400 | /* setup power saving mode registers */ |
| 400 | PCFR = 0x0; | 401 | PCFR = 0x0; |
| @@ -416,9 +417,9 @@ static int cmx2xx_resume(struct sys_device *dev) | |||
| 416 | cmx2xx_pci_resume(); | 417 | cmx2xx_pci_resume(); |
| 417 | 418 | ||
| 418 | /* restore MSC registers */ | 419 | /* restore MSC registers */ |
| 419 | MSC0 = sleep_save_msc[0]; | 420 | __raw_writel(sleep_save_msc[0], MSC0); |
| 420 | MSC1 = sleep_save_msc[1]; | 421 | __raw_writel(sleep_save_msc[1], MSC1); |
| 421 | MSC2 = sleep_save_msc[2]; | 422 | __raw_writel(sleep_save_msc[2], MSC2); |
| 422 | 423 | ||
| 423 | return 0; | 424 | return 0; |
| 424 | } | 425 | } |
| @@ -498,7 +499,12 @@ static struct map_desc cmx2xx_io_desc[] __initdata = { | |||
| 498 | 499 | ||
| 499 | static void __init cmx2xx_map_io(void) | 500 | static void __init cmx2xx_map_io(void) |
| 500 | { | 501 | { |
| 501 | pxa_map_io(); | 502 | if (cpu_is_pxa25x()) |
| 503 | pxa25x_map_io(); | ||
| 504 | |||
| 505 | if (cpu_is_pxa27x()) | ||
| 506 | pxa27x_map_io(); | ||
| 507 | |||
| 502 | iotable_init(cmx2xx_io_desc, ARRAY_SIZE(cmx2xx_io_desc)); | 508 | iotable_init(cmx2xx_io_desc, ARRAY_SIZE(cmx2xx_io_desc)); |
| 503 | 509 | ||
| 504 | it8152_base_address = CMX2XX_IT8152_VIRT; | 510 | it8152_base_address = CMX2XX_IT8152_VIRT; |
| @@ -506,7 +512,11 @@ static void __init cmx2xx_map_io(void) | |||
| 506 | #else | 512 | #else |
| 507 | static void __init cmx2xx_map_io(void) | 513 | static void __init cmx2xx_map_io(void) |
| 508 | { | 514 | { |
| 509 | pxa_map_io(); | 515 | if (cpu_is_pxa25x()) |
| 516 | pxa25x_map_io(); | ||
| 517 | |||
| 518 | if (cpu_is_pxa27x()) | ||
| 519 | pxa27x_map_io(); | ||
| 510 | } | 520 | } |
| 511 | #endif | 521 | #endif |
| 512 | 522 | ||
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index 922b1075b9de..7984268508b6 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c | |||
| @@ -857,7 +857,7 @@ static void __init cm_x300_fixup(struct machine_desc *mdesc, struct tag *tags, | |||
| 857 | 857 | ||
| 858 | MACHINE_START(CM_X300, "CM-X300 module") | 858 | MACHINE_START(CM_X300, "CM-X300 module") |
| 859 | .boot_params = 0xa0000100, | 859 | .boot_params = 0xa0000100, |
| 860 | .map_io = pxa_map_io, | 860 | .map_io = pxa3xx_map_io, |
| 861 | .init_irq = pxa3xx_init_irq, | 861 | .init_irq = pxa3xx_init_irq, |
| 862 | .timer = &pxa_timer, | 862 | .timer = &pxa_timer, |
| 863 | .init_machine = cm_x300_init, | 863 | .init_machine = cm_x300_init, |
diff --git a/arch/arm/mach-pxa/colibri-pxa270-evalboard.c b/arch/arm/mach-pxa/colibri-evalboard.c index 0f3b632c3b14..6b2c800a1133 100644 --- a/arch/arm/mach-pxa/colibri-pxa270-evalboard.c +++ b/arch/arm/mach-pxa/colibri-evalboard.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * linux/arch/arm/mach-pxa/colibri-pxa270-evalboard.c | 2 | * linux/arch/arm/mach-pxa/colibri-evalboard.c |
| 3 | * | 3 | * |
| 4 | * Support for Toradex PXA270 based Colibri Evaluation Carrier Board | 4 | * Support for Toradex Colibri Evaluation Carrier Board |
| 5 | * Daniel Mack <daniel@caiaq.de> | 5 | * Daniel Mack <daniel@caiaq.de> |
| 6 | * Marek Vasut <marek.vasut@gmail.com> | 6 | * Marek Vasut <marek.vasut@gmail.com> |
| 7 | * | 7 | * |
| @@ -19,6 +19,7 @@ | |||
| 19 | #include <asm/mach-types.h> | 19 | #include <asm/mach-types.h> |
| 20 | #include <mach/hardware.h> | 20 | #include <mach/hardware.h> |
| 21 | #include <asm/mach/arch.h> | 21 | #include <asm/mach/arch.h> |
| 22 | #include <linux/i2c.h> | ||
| 22 | 23 | ||
| 23 | #include <mach/pxa27x.h> | 24 | #include <mach/pxa27x.h> |
| 24 | #include <mach/colibri.h> | 25 | #include <mach/colibri.h> |
| @@ -26,86 +27,95 @@ | |||
| 26 | #include <mach/ohci.h> | 27 | #include <mach/ohci.h> |
| 27 | #include <mach/pxa27x-udc.h> | 28 | #include <mach/pxa27x-udc.h> |
| 28 | 29 | ||
| 30 | #include <plat/i2c.h> | ||
| 31 | |||
| 29 | #include "generic.h" | 32 | #include "generic.h" |
| 30 | #include "devices.h" | 33 | #include "devices.h" |
| 31 | 34 | ||
| 32 | /****************************************************************************** | 35 | /****************************************************************************** |
| 33 | * Pin configuration | ||
| 34 | ******************************************************************************/ | ||
| 35 | static mfp_cfg_t colibri_pxa270_evalboard_pin_config[] __initdata = { | ||
| 36 | /* MMC */ | ||
| 37 | GPIO32_MMC_CLK, | ||
| 38 | GPIO92_MMC_DAT_0, | ||
| 39 | GPIO109_MMC_DAT_1, | ||
| 40 | GPIO110_MMC_DAT_2, | ||
| 41 | GPIO111_MMC_DAT_3, | ||
| 42 | GPIO112_MMC_CMD, | ||
| 43 | GPIO0_GPIO, /* SD detect */ | ||
| 44 | |||
| 45 | /* FFUART */ | ||
| 46 | GPIO39_FFUART_TXD, | ||
| 47 | GPIO34_FFUART_RXD, | ||
| 48 | |||
| 49 | /* UHC */ | ||
| 50 | GPIO88_USBH1_PWR, | ||
| 51 | GPIO89_USBH1_PEN, | ||
| 52 | GPIO119_USBH2_PWR, | ||
| 53 | GPIO120_USBH2_PEN, | ||
| 54 | }; | ||
| 55 | |||
| 56 | /****************************************************************************** | ||
| 57 | * SD/MMC card controller | 36 | * SD/MMC card controller |
| 58 | ******************************************************************************/ | 37 | ******************************************************************************/ |
| 59 | #if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) | 38 | #if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) |
| 60 | static struct pxamci_platform_data colibri_pxa270_mci_platform_data = { | 39 | static struct pxamci_platform_data colibri_mci_platform_data = { |
| 61 | .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, | 40 | .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, |
| 62 | .gpio_power = -1, | 41 | .gpio_power = -1, |
| 63 | .gpio_card_detect = GPIO0_COLIBRI_PXA270_SD_DETECT, | ||
| 64 | .gpio_card_ro = -1, | 42 | .gpio_card_ro = -1, |
| 65 | .detect_delay_ms = 200, | 43 | .detect_delay_ms = 200, |
| 66 | }; | 44 | }; |
| 67 | 45 | ||
| 68 | static void __init colibri_pxa270_mmc_init(void) | 46 | static void __init colibri_mmc_init(void) |
| 69 | { | 47 | { |
| 70 | pxa_set_mci_info(&colibri_pxa270_mci_platform_data); | 48 | if (machine_is_colibri()) /* PXA270 Colibri */ |
| 49 | colibri_mci_platform_data.gpio_card_detect = | ||
| 50 | GPIO0_COLIBRI_PXA270_SD_DETECT; | ||
| 51 | if (machine_is_colibri300()) /* PXA300 Colibri */ | ||
| 52 | colibri_mci_platform_data.gpio_card_detect = | ||
| 53 | GPIO39_COLIBRI_PXA300_SD_DETECT; | ||
| 54 | else /* PXA320 Colibri */ | ||
| 55 | colibri_mci_platform_data.gpio_card_detect = | ||
| 56 | GPIO28_COLIBRI_PXA320_SD_DETECT; | ||
| 57 | |||
| 58 | pxa_set_mci_info(&colibri_mci_platform_data); | ||
| 71 | } | 59 | } |
| 72 | #else | 60 | #else |
| 73 | static inline void colibri_pxa270_mmc_init(void) {} | 61 | static inline void colibri_mmc_init(void) {} |
| 74 | #endif | 62 | #endif |
| 75 | 63 | ||
| 76 | /****************************************************************************** | 64 | /****************************************************************************** |
| 77 | * USB Host | 65 | * USB Host |
| 78 | ******************************************************************************/ | 66 | ******************************************************************************/ |
| 79 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | 67 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) |
| 80 | static int colibri_pxa270_ohci_init(struct device *dev) | 68 | static int colibri_ohci_init(struct device *dev) |
| 81 | { | 69 | { |
| 82 | UP2OCR = UP2OCR_HXS | UP2OCR_HXOE | UP2OCR_DPPDE | UP2OCR_DMPDE; | 70 | UP2OCR = UP2OCR_HXS | UP2OCR_HXOE | UP2OCR_DPPDE | UP2OCR_DMPDE; |
| 83 | return 0; | 71 | return 0; |
| 84 | } | 72 | } |
| 85 | 73 | ||
| 86 | static struct pxaohci_platform_data colibri_pxa270_ohci_info = { | 74 | static struct pxaohci_platform_data colibri_ohci_info = { |
| 87 | .port_mode = PMM_PERPORT_MODE, | 75 | .port_mode = PMM_PERPORT_MODE, |
| 88 | .flags = ENABLE_PORT1 | ENABLE_PORT2 | | 76 | .flags = ENABLE_PORT1 | |
| 89 | POWER_CONTROL_LOW | POWER_SENSE_LOW, | 77 | POWER_CONTROL_LOW | POWER_SENSE_LOW, |
| 90 | .init = colibri_pxa270_ohci_init, | 78 | .init = colibri_ohci_init, |
| 91 | }; | 79 | }; |
| 92 | 80 | ||
| 93 | static void __init colibri_pxa270_uhc_init(void) | 81 | static void __init colibri_uhc_init(void) |
| 94 | { | 82 | { |
| 95 | pxa_set_ohci_info(&colibri_pxa270_ohci_info); | 83 | /* Colibri PXA270 has two usb ports, TBA for 320 */ |
| 84 | if (machine_is_colibri()) | ||
| 85 | colibri_ohci_info.flags |= ENABLE_PORT2; | ||
| 86 | |||
| 87 | pxa_set_ohci_info(&colibri_ohci_info); | ||
| 96 | } | 88 | } |
| 97 | #else | 89 | #else |
| 98 | static inline void colibri_pxa270_uhc_init(void) {} | 90 | static inline void colibri_uhc_init(void) {} |
| 99 | #endif | 91 | #endif |
| 100 | 92 | ||
| 101 | void __init colibri_pxa270_evalboard_init(void) | 93 | /****************************************************************************** |
| 94 | * I2C RTC | ||
| 95 | ******************************************************************************/ | ||
| 96 | #if defined(CONFIG_RTC_DRV_DS1307) || defined(CONFIG_RTC_DRV_DS1307_MODULE) | ||
| 97 | static struct i2c_board_info __initdata colibri_i2c_devs[] = { | ||
| 98 | { | ||
| 99 | I2C_BOARD_INFO("m41t00", 0x68), | ||
| 100 | }, | ||
| 101 | }; | ||
| 102 | |||
| 103 | static void __init colibri_rtc_init(void) | ||
| 104 | { | ||
| 105 | pxa_set_i2c_info(NULL); | ||
| 106 | i2c_register_board_info(0, ARRAY_AND_SIZE(colibri_i2c_devs)); | ||
| 107 | } | ||
| 108 | #else | ||
| 109 | static inline void colibri_rtc_init(void) {} | ||
| 110 | #endif | ||
| 111 | |||
| 112 | void __init colibri_evalboard_init(void) | ||
| 102 | { | 113 | { |
| 103 | pxa2xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa270_evalboard_pin_config)); | ||
| 104 | pxa_set_ffuart_info(NULL); | 114 | pxa_set_ffuart_info(NULL); |
| 105 | pxa_set_btuart_info(NULL); | 115 | pxa_set_btuart_info(NULL); |
| 106 | pxa_set_stuart_info(NULL); | 116 | pxa_set_stuart_info(NULL); |
| 107 | 117 | ||
| 108 | colibri_pxa270_mmc_init(); | 118 | colibri_mmc_init(); |
| 109 | colibri_pxa270_uhc_init(); | 119 | colibri_uhc_init(); |
| 120 | colibri_rtc_init(); | ||
| 110 | } | 121 | } |
| 111 | |||
diff --git a/arch/arm/mach-pxa/colibri-pxa270-income.c b/arch/arm/mach-pxa/colibri-pxa270-income.c index 37f0f3ed7c61..07b62a096f17 100644 --- a/arch/arm/mach-pxa/colibri-pxa270-income.c +++ b/arch/arm/mach-pxa/colibri-pxa270-income.c | |||
| @@ -46,52 +46,6 @@ | |||
| 46 | #define GPIO113_INCOME_TS_IRQ (113) | 46 | #define GPIO113_INCOME_TS_IRQ (113) |
| 47 | 47 | ||
| 48 | /****************************************************************************** | 48 | /****************************************************************************** |
| 49 | * Pin configuration | ||
| 50 | ******************************************************************************/ | ||
| 51 | static mfp_cfg_t income_pin_config[] __initdata = { | ||
| 52 | /* MMC */ | ||
| 53 | GPIO32_MMC_CLK, | ||
| 54 | GPIO92_MMC_DAT_0, | ||
| 55 | GPIO109_MMC_DAT_1, | ||
| 56 | GPIO110_MMC_DAT_2, | ||
| 57 | GPIO111_MMC_DAT_3, | ||
| 58 | GPIO112_MMC_CMD, | ||
| 59 | GPIO0_GPIO, /* SD detect */ | ||
| 60 | GPIO1_GPIO, /* SD read-only */ | ||
| 61 | |||
| 62 | /* FFUART */ | ||
| 63 | GPIO39_FFUART_TXD, | ||
| 64 | GPIO34_FFUART_RXD, | ||
| 65 | |||
| 66 | /* BFUART */ | ||
| 67 | GPIO42_BTUART_RXD, | ||
| 68 | GPIO43_BTUART_TXD, | ||
| 69 | GPIO45_BTUART_RTS, | ||
| 70 | |||
| 71 | /* STUART */ | ||
| 72 | GPIO46_STUART_RXD, | ||
| 73 | GPIO47_STUART_TXD, | ||
| 74 | |||
| 75 | /* UHC */ | ||
| 76 | GPIO88_USBH1_PWR, | ||
| 77 | GPIO89_USBH1_PEN, | ||
| 78 | |||
| 79 | /* LCD */ | ||
| 80 | GPIOxx_LCD_TFT_16BPP, | ||
| 81 | |||
| 82 | /* PWM */ | ||
| 83 | GPIO16_PWM0_OUT, | ||
| 84 | |||
| 85 | /* I2C */ | ||
| 86 | GPIO117_I2C_SCL, | ||
| 87 | GPIO118_I2C_SDA, | ||
| 88 | |||
| 89 | /* LED */ | ||
| 90 | GPIO54_GPIO, /* LED A */ | ||
| 91 | GPIO55_GPIO, /* LED B */ | ||
| 92 | }; | ||
| 93 | |||
| 94 | /****************************************************************************** | ||
| 95 | * SD/MMC card controller | 49 | * SD/MMC card controller |
| 96 | ******************************************************************************/ | 50 | ******************************************************************************/ |
| 97 | #if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) | 51 | #if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) |
| @@ -257,7 +211,6 @@ static inline void income_pwm_init(void) {} | |||
| 257 | 211 | ||
| 258 | void __init colibri_pxa270_income_boardinit(void) | 212 | void __init colibri_pxa270_income_boardinit(void) |
| 259 | { | 213 | { |
| 260 | pxa2xx_mfp_config(ARRAY_AND_SIZE(income_pin_config)); | ||
| 261 | pxa_set_ffuart_info(NULL); | 214 | pxa_set_ffuart_info(NULL); |
| 262 | pxa_set_btuart_info(NULL); | 215 | pxa_set_btuart_info(NULL); |
| 263 | pxa_set_stuart_info(NULL); | 216 | pxa_set_stuart_info(NULL); |
diff --git a/arch/arm/mach-pxa/colibri-pxa270.c b/arch/arm/mach-pxa/colibri-pxa270.c index bc045100ec15..6fc5d328ba7f 100644 --- a/arch/arm/mach-pxa/colibri-pxa270.c +++ b/arch/arm/mach-pxa/colibri-pxa270.c | |||
| @@ -33,6 +33,103 @@ | |||
| 33 | #include "generic.h" | 33 | #include "generic.h" |
| 34 | 34 | ||
| 35 | /****************************************************************************** | 35 | /****************************************************************************** |
| 36 | * Evaluation board MFP | ||
| 37 | ******************************************************************************/ | ||
| 38 | #ifdef CONFIG_MACH_COLIBRI_EVALBOARD | ||
| 39 | static mfp_cfg_t colibri_pxa270_evalboard_pin_config[] __initdata = { | ||
| 40 | /* MMC */ | ||
| 41 | GPIO32_MMC_CLK, | ||
| 42 | GPIO92_MMC_DAT_0, | ||
| 43 | GPIO109_MMC_DAT_1, | ||
| 44 | GPIO110_MMC_DAT_2, | ||
| 45 | GPIO111_MMC_DAT_3, | ||
| 46 | GPIO112_MMC_CMD, | ||
| 47 | GPIO0_GPIO, /* SD detect */ | ||
| 48 | |||
| 49 | /* FFUART */ | ||
| 50 | GPIO39_FFUART_TXD, | ||
| 51 | GPIO34_FFUART_RXD, | ||
| 52 | |||
| 53 | /* UHC */ | ||
| 54 | GPIO88_USBH1_PWR, | ||
| 55 | GPIO89_USBH1_PEN, | ||
| 56 | GPIO119_USBH2_PWR, | ||
| 57 | GPIO120_USBH2_PEN, | ||
| 58 | |||
| 59 | /* PCMCIA */ | ||
| 60 | GPIO85_nPCE_1, | ||
| 61 | GPIO54_nPCE_2, | ||
| 62 | GPIO55_nPREG, | ||
| 63 | GPIO50_nPIOR, | ||
| 64 | GPIO51_nPIOW, | ||
| 65 | GPIO49_nPWE, | ||
| 66 | GPIO48_nPOE, | ||
| 67 | GPIO57_nIOIS16, | ||
| 68 | GPIO56_nPWAIT, | ||
| 69 | GPIO104_PSKTSEL, | ||
| 70 | GPIO53_GPIO, /* RESET */ | ||
| 71 | GPIO83_GPIO, /* BVD1 */ | ||
| 72 | GPIO82_GPIO, /* BVD2 */ | ||
| 73 | GPIO1_GPIO, /* READY */ | ||
| 74 | GPIO84_GPIO, /* DETECT */ | ||
| 75 | GPIO107_GPIO, /* PPEN */ | ||
| 76 | |||
| 77 | /* I2C */ | ||
| 78 | GPIO117_I2C_SCL, | ||
| 79 | GPIO118_I2C_SDA, | ||
| 80 | }; | ||
| 81 | #else | ||
| 82 | static mfp_cfg_t colibri_pxa270_evalboard_pin_config[] __initdata = {}; | ||
| 83 | #endif | ||
| 84 | |||
| 85 | #ifdef CONFIG_MACH_COLIBRI_PXA270_INCOME | ||
| 86 | static mfp_cfg_t income_pin_config[] __initdata = { | ||
| 87 | /* MMC */ | ||
| 88 | GPIO32_MMC_CLK, | ||
| 89 | GPIO92_MMC_DAT_0, | ||
| 90 | GPIO109_MMC_DAT_1, | ||
| 91 | GPIO110_MMC_DAT_2, | ||
| 92 | GPIO111_MMC_DAT_3, | ||
| 93 | GPIO112_MMC_CMD, | ||
| 94 | GPIO0_GPIO, /* SD detect */ | ||
| 95 | GPIO1_GPIO, /* SD read-only */ | ||
| 96 | |||
| 97 | /* FFUART */ | ||
| 98 | GPIO39_FFUART_TXD, | ||
| 99 | GPIO34_FFUART_RXD, | ||
| 100 | |||
| 101 | /* BFUART */ | ||
| 102 | GPIO42_BTUART_RXD, | ||
| 103 | GPIO43_BTUART_TXD, | ||
| 104 | GPIO45_BTUART_RTS, | ||
| 105 | |||
| 106 | /* STUART */ | ||
| 107 | GPIO46_STUART_RXD, | ||
| 108 | GPIO47_STUART_TXD, | ||
| 109 | |||
| 110 | /* UHC */ | ||
| 111 | GPIO88_USBH1_PWR, | ||
| 112 | GPIO89_USBH1_PEN, | ||
| 113 | |||
| 114 | /* LCD */ | ||
| 115 | GPIOxx_LCD_TFT_16BPP, | ||
| 116 | |||
| 117 | /* PWM */ | ||
| 118 | GPIO16_PWM0_OUT, | ||
| 119 | |||
| 120 | /* I2C */ | ||
| 121 | GPIO117_I2C_SCL, | ||
| 122 | GPIO118_I2C_SDA, | ||
| 123 | |||
| 124 | /* LED */ | ||
| 125 | GPIO54_GPIO, /* LED A */ | ||
| 126 | GPIO55_GPIO, /* LED B */ | ||
| 127 | }; | ||
| 128 | #else | ||
| 129 | static mfp_cfg_t income_pin_config[] __initdata = {}; | ||
| 130 | #endif | ||
| 131 | |||
| 132 | /****************************************************************************** | ||
| 36 | * Pin configuration | 133 | * Pin configuration |
| 37 | ******************************************************************************/ | 134 | ******************************************************************************/ |
| 38 | static mfp_cfg_t colibri_pxa270_pin_config[] __initdata = { | 135 | static mfp_cfg_t colibri_pxa270_pin_config[] __initdata = { |
| @@ -184,10 +281,13 @@ static void __init colibri_pxa270_init(void) | |||
| 184 | colibri_pxa270_tsc_init(); | 281 | colibri_pxa270_tsc_init(); |
| 185 | 282 | ||
| 186 | switch (colibri_pxa270_baseboard) { | 283 | switch (colibri_pxa270_baseboard) { |
| 187 | case COLIBRI_PXA270_EVALBOARD: | 284 | case COLIBRI_EVALBOARD: |
| 188 | colibri_pxa270_evalboard_init(); | 285 | pxa2xx_mfp_config(ARRAY_AND_SIZE( |
| 286 | colibri_pxa270_evalboard_pin_config)); | ||
| 287 | colibri_evalboard_init(); | ||
| 189 | break; | 288 | break; |
| 190 | case COLIBRI_PXA270_INCOME: | 289 | case COLIBRI_PXA270_INCOME: |
| 290 | pxa2xx_mfp_config(ARRAY_AND_SIZE(income_pin_config)); | ||
| 191 | colibri_pxa270_income_boardinit(); | 291 | colibri_pxa270_income_boardinit(); |
| 192 | break; | 292 | break; |
| 193 | default: | 293 | default: |
| @@ -209,7 +309,7 @@ static void __init colibri_pxa270_income_init(void) | |||
| 209 | MACHINE_START(COLIBRI, "Toradex Colibri PXA270") | 309 | MACHINE_START(COLIBRI, "Toradex Colibri PXA270") |
| 210 | .boot_params = COLIBRI_SDRAM_BASE + 0x100, | 310 | .boot_params = COLIBRI_SDRAM_BASE + 0x100, |
| 211 | .init_machine = colibri_pxa270_init, | 311 | .init_machine = colibri_pxa270_init, |
| 212 | .map_io = pxa_map_io, | 312 | .map_io = pxa27x_map_io, |
| 213 | .init_irq = pxa27x_init_irq, | 313 | .init_irq = pxa27x_init_irq, |
| 214 | .timer = &pxa_timer, | 314 | .timer = &pxa_timer, |
| 215 | MACHINE_END | 315 | MACHINE_END |
| @@ -217,7 +317,7 @@ MACHINE_END | |||
| 217 | MACHINE_START(INCOME, "Income s.r.o. SH-Dmaster PXA270 SBC") | 317 | MACHINE_START(INCOME, "Income s.r.o. SH-Dmaster PXA270 SBC") |
| 218 | .boot_params = 0xa0000100, | 318 | .boot_params = 0xa0000100, |
| 219 | .init_machine = colibri_pxa270_income_init, | 319 | .init_machine = colibri_pxa270_income_init, |
| 220 | .map_io = pxa_map_io, | 320 | .map_io = pxa27x_map_io, |
| 221 | .init_irq = pxa27x_init_irq, | 321 | .init_irq = pxa27x_init_irq, |
| 222 | .timer = &pxa_timer, | 322 | .timer = &pxa_timer, |
| 223 | MACHINE_END | 323 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c index a70b256591e6..fddb16d07eb0 100644 --- a/arch/arm/mach-pxa/colibri-pxa300.c +++ b/arch/arm/mach-pxa/colibri-pxa300.c | |||
| @@ -31,9 +31,38 @@ | |||
| 31 | #include "generic.h" | 31 | #include "generic.h" |
| 32 | #include "devices.h" | 32 | #include "devices.h" |
| 33 | 33 | ||
| 34 | |||
| 35 | #ifdef CONFIG_MACH_COLIBRI_EVALBOARD | ||
| 36 | static mfp_cfg_t colibri_pxa300_evalboard_pin_config[] __initdata = { | ||
| 37 | /* MMC */ | ||
| 38 | GPIO7_MMC1_CLK, | ||
| 39 | GPIO14_MMC1_CMD, | ||
| 40 | GPIO3_MMC1_DAT0, | ||
| 41 | GPIO4_MMC1_DAT1, | ||
| 42 | GPIO5_MMC1_DAT2, | ||
| 43 | GPIO6_MMC1_DAT3, | ||
| 44 | GPIO39_GPIO, /* SD detect */ | ||
| 45 | |||
| 46 | /* UHC */ | ||
| 47 | GPIO0_2_USBH_PEN, | ||
| 48 | GPIO1_2_USBH_PWR, | ||
| 49 | GPIO77_USB_P3_1, | ||
| 50 | GPIO78_USB_P3_2, | ||
| 51 | GPIO79_USB_P3_3, | ||
| 52 | GPIO80_USB_P3_4, | ||
| 53 | GPIO81_USB_P3_5, | ||
| 54 | GPIO82_USB_P3_6, | ||
| 55 | |||
| 56 | /* I2C */ | ||
| 57 | GPIO21_I2C_SCL, | ||
| 58 | GPIO22_I2C_SDA, | ||
| 59 | }; | ||
| 60 | #else | ||
| 61 | static mfp_cfg_t colibri_pxa300_evalboard_pin_config[] __initdata = {}; | ||
| 62 | #endif | ||
| 63 | |||
| 34 | #if defined(CONFIG_AX88796) | 64 | #if defined(CONFIG_AX88796) |
| 35 | #define COLIBRI_ETH_IRQ_GPIO mfp_to_gpio(GPIO26_GPIO) | 65 | #define COLIBRI_ETH_IRQ_GPIO mfp_to_gpio(GPIO26_GPIO) |
| 36 | |||
| 37 | /* | 66 | /* |
| 38 | * Asix AX88796 Ethernet | 67 | * Asix AX88796 Ethernet |
| 39 | */ | 68 | */ |
| @@ -80,35 +109,6 @@ static void __init colibri_pxa300_init_eth(void) | |||
| 80 | static inline void __init colibri_pxa300_init_eth(void) {} | 109 | static inline void __init colibri_pxa300_init_eth(void) {} |
| 81 | #endif /* CONFIG_AX88796 */ | 110 | #endif /* CONFIG_AX88796 */ |
| 82 | 111 | ||
| 83 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | ||
| 84 | static mfp_cfg_t colibri_pxa300_usb_pin_config[] __initdata = { | ||
| 85 | GPIO0_2_USBH_PEN, | ||
| 86 | GPIO1_2_USBH_PWR, | ||
| 87 | }; | ||
| 88 | |||
| 89 | static struct pxaohci_platform_data colibri_pxa300_ohci_info = { | ||
| 90 | .port_mode = PMM_GLOBAL_MODE, | ||
| 91 | .flags = ENABLE_PORT1 | POWER_CONTROL_LOW | POWER_SENSE_LOW, | ||
| 92 | }; | ||
| 93 | |||
| 94 | void __init colibri_pxa300_init_ohci(void) | ||
| 95 | { | ||
| 96 | pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa300_usb_pin_config)); | ||
| 97 | pxa_set_ohci_info(&colibri_pxa300_ohci_info); | ||
| 98 | } | ||
| 99 | #else | ||
| 100 | static inline void colibri_pxa300_init_ohci(void) {} | ||
| 101 | #endif /* CONFIG_USB_OHCI_HCD || CONFIG_USB_OHCI_HCD_MODULE */ | ||
| 102 | |||
| 103 | static mfp_cfg_t colibri_pxa300_mmc_pin_config[] __initdata = { | ||
| 104 | GPIO7_MMC1_CLK, | ||
| 105 | GPIO14_MMC1_CMD, | ||
| 106 | GPIO3_MMC1_DAT0, | ||
| 107 | GPIO4_MMC1_DAT1, | ||
| 108 | GPIO5_MMC1_DAT2, | ||
| 109 | GPIO6_MMC1_DAT3, | ||
| 110 | }; | ||
| 111 | |||
| 112 | #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) | 112 | #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) |
| 113 | static mfp_cfg_t colibri_pxa300_lcd_pin_config[] __initdata = { | 113 | static mfp_cfg_t colibri_pxa300_lcd_pin_config[] __initdata = { |
| 114 | GPIO54_LCD_LDD_0, | 114 | GPIO54_LCD_LDD_0, |
| @@ -171,24 +171,21 @@ static inline void colibri_pxa310_init_ac97(void) {} | |||
| 171 | 171 | ||
| 172 | void __init colibri_pxa300_init(void) | 172 | void __init colibri_pxa300_init(void) |
| 173 | { | 173 | { |
| 174 | pxa_set_ffuart_info(NULL); | ||
| 175 | pxa_set_btuart_info(NULL); | ||
| 176 | pxa_set_stuart_info(NULL); | ||
| 177 | |||
| 178 | colibri_pxa300_init_eth(); | 174 | colibri_pxa300_init_eth(); |
| 179 | colibri_pxa300_init_ohci(); | ||
| 180 | colibri_pxa3xx_init_nand(); | 175 | colibri_pxa3xx_init_nand(); |
| 181 | colibri_pxa300_init_lcd(); | 176 | colibri_pxa300_init_lcd(); |
| 182 | colibri_pxa3xx_init_lcd(mfp_to_gpio(GPIO39_GPIO)); | 177 | colibri_pxa3xx_init_lcd(mfp_to_gpio(GPIO39_GPIO)); |
| 183 | colibri_pxa310_init_ac97(); | 178 | colibri_pxa310_init_ac97(); |
| 184 | colibri_pxa3xx_init_mmc(ARRAY_AND_SIZE(colibri_pxa300_mmc_pin_config), | 179 | |
| 185 | mfp_to_gpio(MFP_PIN_GPIO13)); | 180 | /* Evalboard init */ |
| 181 | pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa300_evalboard_pin_config)); | ||
| 182 | colibri_evalboard_init(); | ||
| 186 | } | 183 | } |
| 187 | 184 | ||
| 188 | MACHINE_START(COLIBRI300, "Toradex Colibri PXA300") | 185 | MACHINE_START(COLIBRI300, "Toradex Colibri PXA300") |
| 189 | .boot_params = COLIBRI_SDRAM_BASE + 0x100, | 186 | .boot_params = COLIBRI_SDRAM_BASE + 0x100, |
| 190 | .init_machine = colibri_pxa300_init, | 187 | .init_machine = colibri_pxa300_init, |
| 191 | .map_io = pxa_map_io, | 188 | .map_io = pxa3xx_map_io, |
| 192 | .init_irq = pxa3xx_init_irq, | 189 | .init_irq = pxa3xx_init_irq, |
| 193 | .timer = &pxa_timer, | 190 | .timer = &pxa_timer, |
| 194 | MACHINE_END | 191 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c index ca5f29e2e9cd..ff9ff5f4fc47 100644 --- a/arch/arm/mach-pxa/colibri-pxa320.c +++ b/arch/arm/mach-pxa/colibri-pxa320.c | |||
| @@ -35,9 +35,72 @@ | |||
| 35 | #include "generic.h" | 35 | #include "generic.h" |
| 36 | #include "devices.h" | 36 | #include "devices.h" |
| 37 | 37 | ||
| 38 | #ifdef CONFIG_MACH_COLIBRI_EVALBOARD | ||
| 39 | static mfp_cfg_t colibri_pxa320_evalboard_pin_config[] __initdata = { | ||
| 40 | /* MMC */ | ||
| 41 | GPIO22_MMC1_CLK, | ||
| 42 | GPIO23_MMC1_CMD, | ||
| 43 | GPIO18_MMC1_DAT0, | ||
| 44 | GPIO19_MMC1_DAT1, | ||
| 45 | GPIO20_MMC1_DAT2, | ||
| 46 | GPIO21_MMC1_DAT3, | ||
| 47 | GPIO28_GPIO, /* SD detect */ | ||
| 48 | |||
| 49 | /* UART 1 configuration (may be set by bootloader) */ | ||
| 50 | GPIO99_UART1_CTS, | ||
| 51 | GPIO104_UART1_RTS, | ||
| 52 | GPIO97_UART1_RXD, | ||
| 53 | GPIO98_UART1_TXD, | ||
| 54 | GPIO101_UART1_DTR, | ||
| 55 | GPIO103_UART1_DSR, | ||
| 56 | GPIO100_UART1_DCD, | ||
| 57 | GPIO102_UART1_RI, | ||
| 58 | |||
| 59 | /* UART 2 configuration */ | ||
| 60 | GPIO109_UART2_CTS, | ||
| 61 | GPIO112_UART2_RTS, | ||
| 62 | GPIO110_UART2_RXD, | ||
| 63 | GPIO111_UART2_TXD, | ||
| 64 | |||
| 65 | /* UART 3 configuration */ | ||
| 66 | GPIO30_UART3_RXD, | ||
| 67 | GPIO31_UART3_TXD, | ||
| 68 | |||
| 69 | /* UHC */ | ||
| 70 | GPIO2_2_USBH_PEN, | ||
| 71 | GPIO3_2_USBH_PWR, | ||
| 72 | |||
| 73 | /* I2C */ | ||
| 74 | GPIO32_I2C_SCL, | ||
| 75 | GPIO33_I2C_SDA, | ||
| 76 | |||
| 77 | /* PCMCIA */ | ||
| 78 | MFP_CFG(GPIO59, AF7), /* PRST ; AF7 to tristate */ | ||
| 79 | MFP_CFG(GPIO61, AF7), /* PCE1 ; AF7 to tristate */ | ||
| 80 | MFP_CFG(GPIO60, AF7), /* PCE2 ; AF7 to tristate */ | ||
| 81 | MFP_CFG(GPIO62, AF7), /* PCD ; AF7 to tristate */ | ||
| 82 | MFP_CFG(GPIO56, AF7), /* PSKTSEL ; AF7 to tristate */ | ||
| 83 | GPIO27_GPIO, /* RDnWR ; input/tristate */ | ||
| 84 | GPIO50_GPIO, /* PREG ; input/tristate */ | ||
| 85 | GPIO2_RDY, | ||
| 86 | GPIO5_NPIOR, | ||
| 87 | GPIO6_NPIOW, | ||
| 88 | GPIO7_NPIOS16, | ||
| 89 | GPIO8_NPWAIT, | ||
| 90 | GPIO29_GPIO, /* PRDY (READY GPIO) */ | ||
| 91 | GPIO57_GPIO, /* PPEN (POWER GPIO) */ | ||
| 92 | GPIO81_GPIO, /* PCD (DETECT GPIO) */ | ||
| 93 | GPIO77_GPIO, /* PRST (RESET GPIO) */ | ||
| 94 | GPIO53_GPIO, /* PBVD1 */ | ||
| 95 | GPIO79_GPIO, /* PBVD2 */ | ||
| 96 | GPIO54_GPIO, /* POE */ | ||
| 97 | }; | ||
| 98 | #else | ||
| 99 | static mfp_cfg_t colibri_pxa320_evalboard_pin_config[] __initdata = {}; | ||
| 100 | #endif | ||
| 101 | |||
| 38 | #if defined(CONFIG_AX88796) | 102 | #if defined(CONFIG_AX88796) |
| 39 | #define COLIBRI_ETH_IRQ_GPIO mfp_to_gpio(GPIO36_GPIO) | 103 | #define COLIBRI_ETH_IRQ_GPIO mfp_to_gpio(GPIO36_GPIO) |
| 40 | |||
| 41 | /* | 104 | /* |
| 42 | * Asix AX88796 Ethernet | 105 | * Asix AX88796 Ethernet |
| 43 | */ | 106 | */ |
| @@ -84,26 +147,6 @@ static void __init colibri_pxa320_init_eth(void) | |||
| 84 | static inline void __init colibri_pxa320_init_eth(void) {} | 147 | static inline void __init colibri_pxa320_init_eth(void) {} |
| 85 | #endif /* CONFIG_AX88796 */ | 148 | #endif /* CONFIG_AX88796 */ |
| 86 | 149 | ||
| 87 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | ||
| 88 | static mfp_cfg_t colibri_pxa320_usb_pin_config[] __initdata = { | ||
| 89 | GPIO2_2_USBH_PEN, | ||
| 90 | GPIO3_2_USBH_PWR, | ||
| 91 | }; | ||
| 92 | |||
| 93 | static struct pxaohci_platform_data colibri_pxa320_ohci_info = { | ||
| 94 | .port_mode = PMM_GLOBAL_MODE, | ||
| 95 | .flags = ENABLE_PORT1 | POWER_CONTROL_LOW | POWER_SENSE_LOW, | ||
| 96 | }; | ||
| 97 | |||
| 98 | void __init colibri_pxa320_init_ohci(void) | ||
| 99 | { | ||
| 100 | pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_usb_pin_config)); | ||
| 101 | pxa_set_ohci_info(&colibri_pxa320_ohci_info); | ||
| 102 | } | ||
| 103 | #else | ||
| 104 | static inline void colibri_pxa320_init_ohci(void) {} | ||
| 105 | #endif /* CONFIG_USB_OHCI_HCD || CONFIG_USB_OHCI_HCD_MODULE */ | ||
| 106 | |||
| 107 | #if defined(CONFIG_USB_GADGET_PXA27X)||defined(CONFIG_USB_GADGET_PXA27X_MODULE) | 150 | #if defined(CONFIG_USB_GADGET_PXA27X)||defined(CONFIG_USB_GADGET_PXA27X_MODULE) |
| 108 | static struct gpio_vbus_mach_info colibri_pxa320_gpio_vbus_info = { | 151 | static struct gpio_vbus_mach_info colibri_pxa320_gpio_vbus_info = { |
| 109 | .gpio_vbus = mfp_to_gpio(MFP_PIN_GPIO96), | 152 | .gpio_vbus = mfp_to_gpio(MFP_PIN_GPIO96), |
| @@ -140,15 +183,6 @@ static void __init colibri_pxa320_init_udc(void) | |||
| 140 | static inline void colibri_pxa320_init_udc(void) {} | 183 | static inline void colibri_pxa320_init_udc(void) {} |
| 141 | #endif | 184 | #endif |
| 142 | 185 | ||
| 143 | static mfp_cfg_t colibri_pxa320_mmc_pin_config[] __initdata = { | ||
| 144 | GPIO22_MMC1_CLK, | ||
| 145 | GPIO23_MMC1_CMD, | ||
| 146 | GPIO18_MMC1_DAT0, | ||
| 147 | GPIO19_MMC1_DAT1, | ||
| 148 | GPIO20_MMC1_DAT2, | ||
| 149 | GPIO21_MMC1_DAT3 | ||
| 150 | }; | ||
| 151 | |||
| 152 | #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) | 186 | #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) |
| 153 | static mfp_cfg_t colibri_pxa320_lcd_pin_config[] __initdata = { | 187 | static mfp_cfg_t colibri_pxa320_lcd_pin_config[] __initdata = { |
| 154 | GPIO6_2_LCD_LDD_0, | 188 | GPIO6_2_LCD_LDD_0, |
| @@ -205,59 +239,24 @@ static inline void __init colibri_pxa320_init_ac97(void) | |||
| 205 | static inline void colibri_pxa320_init_ac97(void) {} | 239 | static inline void colibri_pxa320_init_ac97(void) {} |
| 206 | #endif | 240 | #endif |
| 207 | 241 | ||
| 208 | /* | ||
| 209 | * The following configuration is verified to work with the Toradex Orchid | ||
| 210 | * carrier board | ||
| 211 | */ | ||
| 212 | static mfp_cfg_t colibri_pxa320_uart_pin_config[] __initdata = { | ||
| 213 | /* UART 1 configuration (may be set by bootloader) */ | ||
| 214 | GPIO99_UART1_CTS, | ||
| 215 | GPIO104_UART1_RTS, | ||
| 216 | GPIO97_UART1_RXD, | ||
| 217 | GPIO98_UART1_TXD, | ||
| 218 | GPIO101_UART1_DTR, | ||
| 219 | GPIO103_UART1_DSR, | ||
| 220 | GPIO100_UART1_DCD, | ||
| 221 | GPIO102_UART1_RI, | ||
| 222 | |||
| 223 | /* UART 2 configuration */ | ||
| 224 | GPIO109_UART2_CTS, | ||
| 225 | GPIO112_UART2_RTS, | ||
| 226 | GPIO110_UART2_RXD, | ||
| 227 | GPIO111_UART2_TXD, | ||
| 228 | |||
| 229 | /* UART 3 configuration */ | ||
| 230 | GPIO30_UART3_RXD, | ||
| 231 | GPIO31_UART3_TXD, | ||
| 232 | }; | ||
| 233 | |||
| 234 | static void __init colibri_pxa320_init_uart(void) | ||
| 235 | { | ||
| 236 | pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_uart_pin_config)); | ||
| 237 | } | ||
| 238 | |||
| 239 | void __init colibri_pxa320_init(void) | 242 | void __init colibri_pxa320_init(void) |
| 240 | { | 243 | { |
| 241 | pxa_set_ffuart_info(NULL); | ||
| 242 | pxa_set_btuart_info(NULL); | ||
| 243 | pxa_set_stuart_info(NULL); | ||
| 244 | |||
| 245 | colibri_pxa320_init_eth(); | 244 | colibri_pxa320_init_eth(); |
| 246 | colibri_pxa320_init_ohci(); | ||
| 247 | colibri_pxa3xx_init_nand(); | 245 | colibri_pxa3xx_init_nand(); |
| 248 | colibri_pxa320_init_lcd(); | 246 | colibri_pxa320_init_lcd(); |
| 249 | colibri_pxa3xx_init_lcd(mfp_to_gpio(GPIO49_GPIO)); | 247 | colibri_pxa3xx_init_lcd(mfp_to_gpio(GPIO49_GPIO)); |
| 250 | colibri_pxa320_init_ac97(); | 248 | colibri_pxa320_init_ac97(); |
| 251 | colibri_pxa3xx_init_mmc(ARRAY_AND_SIZE(colibri_pxa320_mmc_pin_config), | ||
| 252 | mfp_to_gpio(MFP_PIN_GPIO28)); | ||
| 253 | colibri_pxa320_init_uart(); | ||
| 254 | colibri_pxa320_init_udc(); | 249 | colibri_pxa320_init_udc(); |
| 250 | |||
| 251 | /* Evalboard init */ | ||
| 252 | pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_evalboard_pin_config)); | ||
| 253 | colibri_evalboard_init(); | ||
| 255 | } | 254 | } |
| 256 | 255 | ||
| 257 | MACHINE_START(COLIBRI320, "Toradex Colibri PXA320") | 256 | MACHINE_START(COLIBRI320, "Toradex Colibri PXA320") |
| 258 | .boot_params = COLIBRI_SDRAM_BASE + 0x100, | 257 | .boot_params = COLIBRI_SDRAM_BASE + 0x100, |
| 259 | .init_machine = colibri_pxa320_init, | 258 | .init_machine = colibri_pxa320_init, |
| 260 | .map_io = pxa_map_io, | 259 | .map_io = pxa3xx_map_io, |
| 261 | .init_irq = pxa3xx_init_irq, | 260 | .init_irq = pxa3xx_init_irq, |
| 262 | .timer = &pxa_timer, | 261 | .timer = &pxa_timer, |
| 263 | MACHINE_END | 262 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c b/arch/arm/mach-pxa/colibri-pxa3xx.c index 199afa2ae303..96b2d9fbfef0 100644 --- a/arch/arm/mach-pxa/colibri-pxa3xx.c +++ b/arch/arm/mach-pxa/colibri-pxa3xx.c | |||
| @@ -64,55 +64,6 @@ void __init colibri_pxa3xx_init_eth(struct ax_plat_data *plat_data) | |||
| 64 | } | 64 | } |
| 65 | #endif | 65 | #endif |
| 66 | 66 | ||
| 67 | #if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) | ||
| 68 | static int mmc_detect_pin; | ||
| 69 | |||
| 70 | static int colibri_pxa3xx_mci_init(struct device *dev, | ||
| 71 | irq_handler_t colibri_mmc_detect_int, | ||
| 72 | void *data) | ||
| 73 | { | ||
| 74 | int ret; | ||
| 75 | |||
| 76 | ret = gpio_request(mmc_detect_pin, "mmc card detect"); | ||
| 77 | if (ret) | ||
| 78 | return ret; | ||
| 79 | |||
| 80 | gpio_direction_input(mmc_detect_pin); | ||
| 81 | ret = request_irq(gpio_to_irq(mmc_detect_pin), colibri_mmc_detect_int, | ||
| 82 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, | ||
| 83 | "MMC card detect", data); | ||
| 84 | if (ret) { | ||
| 85 | gpio_free(mmc_detect_pin); | ||
| 86 | return ret; | ||
| 87 | } | ||
| 88 | |||
| 89 | return 0; | ||
| 90 | } | ||
| 91 | |||
| 92 | static void colibri_pxa3xx_mci_exit(struct device *dev, void *data) | ||
| 93 | { | ||
| 94 | free_irq(mmc_detect_pin, data); | ||
| 95 | gpio_free(gpio_to_irq(mmc_detect_pin)); | ||
| 96 | } | ||
| 97 | |||
| 98 | static struct pxamci_platform_data colibri_pxa3xx_mci_platform_data = { | ||
| 99 | .detect_delay_ms = 200, | ||
| 100 | .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, | ||
| 101 | .init = colibri_pxa3xx_mci_init, | ||
| 102 | .exit = colibri_pxa3xx_mci_exit, | ||
| 103 | .gpio_card_detect = -1, | ||
| 104 | .gpio_card_ro = -1, | ||
| 105 | .gpio_power = -1, | ||
| 106 | }; | ||
| 107 | |||
| 108 | void __init colibri_pxa3xx_init_mmc(mfp_cfg_t *pins, int len, int detect_pin) | ||
| 109 | { | ||
| 110 | pxa3xx_mfp_config(pins, len); | ||
| 111 | mmc_detect_pin = detect_pin; | ||
| 112 | pxa_set_mci_info(&colibri_pxa3xx_mci_platform_data); | ||
| 113 | } | ||
| 114 | #endif /* CONFIG_MMC_PXA || CONFIG_MMC_PXA_MODULE */ | ||
| 115 | |||
| 116 | #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) | 67 | #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) |
| 117 | static int lcd_bl_pin; | 68 | static int lcd_bl_pin; |
| 118 | 69 | ||
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index 821229acabe6..a5452a3a276d 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c | |||
| @@ -28,6 +28,7 @@ | |||
| 28 | #include <linux/spi/spi.h> | 28 | #include <linux/spi/spi.h> |
| 29 | #include <linux/spi/ads7846.h> | 29 | #include <linux/spi/ads7846.h> |
| 30 | #include <linux/spi/corgi_lcd.h> | 30 | #include <linux/spi/corgi_lcd.h> |
| 31 | #include <linux/spi/pxa2xx_spi.h> | ||
| 31 | #include <linux/mtd/sharpsl.h> | 32 | #include <linux/mtd/sharpsl.h> |
| 32 | #include <linux/input/matrix_keypad.h> | 33 | #include <linux/input/matrix_keypad.h> |
| 33 | #include <video/w100fb.h> | 34 | #include <video/w100fb.h> |
| @@ -48,7 +49,6 @@ | |||
| 48 | #include <mach/irda.h> | 49 | #include <mach/irda.h> |
| 49 | #include <mach/mmc.h> | 50 | #include <mach/mmc.h> |
| 50 | #include <mach/udc.h> | 51 | #include <mach/udc.h> |
| 51 | #include <mach/pxa2xx_spi.h> | ||
| 52 | #include <mach/corgi.h> | 52 | #include <mach/corgi.h> |
| 53 | #include <mach/sharpsl_pm.h> | 53 | #include <mach/sharpsl_pm.h> |
| 54 | 54 | ||
| @@ -721,7 +721,7 @@ static void __init fixup_corgi(struct machine_desc *desc, | |||
| 721 | #ifdef CONFIG_MACH_CORGI | 721 | #ifdef CONFIG_MACH_CORGI |
| 722 | MACHINE_START(CORGI, "SHARP Corgi") | 722 | MACHINE_START(CORGI, "SHARP Corgi") |
| 723 | .fixup = fixup_corgi, | 723 | .fixup = fixup_corgi, |
| 724 | .map_io = pxa_map_io, | 724 | .map_io = pxa25x_map_io, |
| 725 | .init_irq = pxa25x_init_irq, | 725 | .init_irq = pxa25x_init_irq, |
| 726 | .init_machine = corgi_init, | 726 | .init_machine = corgi_init, |
| 727 | .timer = &pxa_timer, | 727 | .timer = &pxa_timer, |
| @@ -731,7 +731,7 @@ MACHINE_END | |||
| 731 | #ifdef CONFIG_MACH_SHEPHERD | 731 | #ifdef CONFIG_MACH_SHEPHERD |
| 732 | MACHINE_START(SHEPHERD, "SHARP Shepherd") | 732 | MACHINE_START(SHEPHERD, "SHARP Shepherd") |
| 733 | .fixup = fixup_corgi, | 733 | .fixup = fixup_corgi, |
| 734 | .map_io = pxa_map_io, | 734 | .map_io = pxa25x_map_io, |
| 735 | .init_irq = pxa25x_init_irq, | 735 | .init_irq = pxa25x_init_irq, |
| 736 | .init_machine = corgi_init, | 736 | .init_machine = corgi_init, |
| 737 | .timer = &pxa_timer, | 737 | .timer = &pxa_timer, |
| @@ -741,7 +741,7 @@ MACHINE_END | |||
| 741 | #ifdef CONFIG_MACH_HUSKY | 741 | #ifdef CONFIG_MACH_HUSKY |
| 742 | MACHINE_START(HUSKY, "SHARP Husky") | 742 | MACHINE_START(HUSKY, "SHARP Husky") |
| 743 | .fixup = fixup_corgi, | 743 | .fixup = fixup_corgi, |
| 744 | .map_io = pxa_map_io, | 744 | .map_io = pxa25x_map_io, |
| 745 | .init_irq = pxa25x_init_irq, | 745 | .init_irq = pxa25x_init_irq, |
| 746 | .init_machine = corgi_init, | 746 | .init_machine = corgi_init, |
| 747 | .timer = &pxa_timer, | 747 | .timer = &pxa_timer, |
diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c b/arch/arm/mach-pxa/cpufreq-pxa2xx.c index 58093d9e07be..6a7aeab42f6c 100644 --- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c +++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c | |||
| @@ -38,8 +38,10 @@ | |||
| 38 | #include <linux/cpufreq.h> | 38 | #include <linux/cpufreq.h> |
| 39 | #include <linux/err.h> | 39 | #include <linux/err.h> |
| 40 | #include <linux/regulator/consumer.h> | 40 | #include <linux/regulator/consumer.h> |
| 41 | #include <linux/io.h> | ||
| 41 | 42 | ||
| 42 | #include <mach/pxa2xx-regs.h> | 43 | #include <mach/pxa2xx-regs.h> |
| 44 | #include <mach/smemc.h> | ||
| 43 | 45 | ||
| 44 | #ifdef DEBUG | 46 | #ifdef DEBUG |
| 45 | static unsigned int freq_debug; | 47 | static unsigned int freq_debug; |
| @@ -242,7 +244,7 @@ static void pxa27x_guess_max_freq(void) | |||
| 242 | 244 | ||
| 243 | static void init_sdram_rows(void) | 245 | static void init_sdram_rows(void) |
| 244 | { | 246 | { |
| 245 | uint32_t mdcnfg = MDCNFG; | 247 | uint32_t mdcnfg = __raw_readl(MDCNFG); |
| 246 | unsigned int drac2 = 0, drac0 = 0; | 248 | unsigned int drac2 = 0, drac0 = 0; |
| 247 | 249 | ||
| 248 | if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3)) | 250 | if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3)) |
| @@ -331,8 +333,8 @@ static int pxa_set_target(struct cpufreq_policy *policy, | |||
| 331 | * we need to preset the smaller DRI before the change. If we're | 333 | * we need to preset the smaller DRI before the change. If we're |
| 332 | * speeding up we need to set the larger DRI value after the change. | 334 | * speeding up we need to set the larger DRI value after the change. |
| 333 | */ | 335 | */ |
| 334 | preset_mdrefr = postset_mdrefr = MDREFR; | 336 | preset_mdrefr = postset_mdrefr = __raw_readl(MDREFR); |
| 335 | if ((MDREFR & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) { | 337 | if ((preset_mdrefr & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) { |
| 336 | preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK); | 338 | preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK); |
| 337 | preset_mdrefr |= mdrefr_dri(new_freq_mem); | 339 | preset_mdrefr |= mdrefr_dri(new_freq_mem); |
| 338 | } | 340 | } |
| @@ -370,7 +372,7 @@ static int pxa_set_target(struct cpufreq_policy *policy, | |||
| 370 | 3: nop \n\ | 372 | 3: nop \n\ |
| 371 | " | 373 | " |
| 372 | : "=&r" (unused) | 374 | : "=&r" (unused) |
| 373 | : "r" (&MDREFR), "r" (cclkcfg), | 375 | : "r" (MDREFR), "r" (cclkcfg), |
| 374 | "r" (preset_mdrefr), "r" (postset_mdrefr) | 376 | "r" (preset_mdrefr), "r" (postset_mdrefr) |
| 375 | : "r4", "r5"); | 377 | : "r4", "r5"); |
| 376 | local_irq_restore(flags); | 378 | local_irq_restore(flags); |
diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c index 57cacaff194d..a305424a967d 100644 --- a/arch/arm/mach-pxa/csb726.c +++ b/arch/arm/mach-pxa/csb726.c | |||
| @@ -27,6 +27,7 @@ | |||
| 27 | #include <mach/ohci.h> | 27 | #include <mach/ohci.h> |
| 28 | #include <mach/pxa2xx-regs.h> | 28 | #include <mach/pxa2xx-regs.h> |
| 29 | #include <mach/audio.h> | 29 | #include <mach/audio.h> |
| 30 | #include <mach/smemc.h> | ||
| 30 | 31 | ||
| 31 | #include "generic.h" | 32 | #include "generic.h" |
| 32 | #include "devices.h" | 33 | #include "devices.h" |
| @@ -255,9 +256,9 @@ static struct platform_device *devices[] __initdata = { | |||
| 255 | static void __init csb726_init(void) | 256 | static void __init csb726_init(void) |
| 256 | { | 257 | { |
| 257 | pxa2xx_mfp_config(ARRAY_AND_SIZE(csb726_pin_config)); | 258 | pxa2xx_mfp_config(ARRAY_AND_SIZE(csb726_pin_config)); |
| 258 | /* MSC1 = 0x7ffc3ffc; *//* LAN9215/EXP_CS */ | 259 | /* __raw_writel(0x7ffc3ffc, MSC1); *//* LAN9215/EXP_CS */ |
| 259 | /* MSC2 = 0x06697ff4; *//* none/SM501 */ | 260 | /* __raw_writel(0x06697ff4, MSC2); *//* none/SM501 */ |
| 260 | MSC2 = (MSC2 & ~0xffff) | 0x7ff4; /* SM501 */ | 261 | __raw_writel((__raw_readl(MSC2) & ~0xffff) | 0x7ff4, MSC2); /* SM501 */ |
| 261 | 262 | ||
| 262 | pxa_set_ffuart_info(NULL); | 263 | pxa_set_ffuart_info(NULL); |
| 263 | pxa_set_btuart_info(NULL); | 264 | pxa_set_btuart_info(NULL); |
| @@ -273,7 +274,7 @@ static void __init csb726_init(void) | |||
| 273 | 274 | ||
| 274 | MACHINE_START(CSB726, "Cogent CSB726") | 275 | MACHINE_START(CSB726, "Cogent CSB726") |
| 275 | .boot_params = 0xa0000100, | 276 | .boot_params = 0xa0000100, |
| 276 | .map_io = pxa_map_io, | 277 | .map_io = pxa27x_map_io, |
| 277 | .init_irq = pxa27x_init_irq, | 278 | .init_irq = pxa27x_init_irq, |
| 278 | .init_machine = csb726_init, | 279 | .init_machine = csb726_init, |
| 279 | .timer = &pxa_timer, | 280 | .timer = &pxa_timer, |
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index aaa1166df964..4c766e3b4af3 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c | |||
| @@ -3,6 +3,7 @@ | |||
| 3 | #include <linux/init.h> | 3 | #include <linux/init.h> |
| 4 | #include <linux/platform_device.h> | 4 | #include <linux/platform_device.h> |
| 5 | #include <linux/dma-mapping.h> | 5 | #include <linux/dma-mapping.h> |
| 6 | #include <linux/spi/pxa2xx_spi.h> | ||
| 6 | 7 | ||
| 7 | #include <asm/pmu.h> | 8 | #include <asm/pmu.h> |
| 8 | #include <mach/udc.h> | 9 | #include <mach/udc.h> |
| @@ -12,7 +13,6 @@ | |||
| 12 | #include <mach/irda.h> | 13 | #include <mach/irda.h> |
| 13 | #include <mach/ohci.h> | 14 | #include <mach/ohci.h> |
| 14 | #include <plat/pxa27x_keypad.h> | 15 | #include <plat/pxa27x_keypad.h> |
| 15 | #include <mach/pxa2xx_spi.h> | ||
| 16 | #include <mach/camera.h> | 16 | #include <mach/camera.h> |
| 17 | #include <mach/audio.h> | 17 | #include <mach/audio.h> |
| 18 | #include <mach/hardware.h> | 18 | #include <mach/hardware.h> |
| @@ -342,27 +342,6 @@ struct platform_device pxa27x_device_i2c_power = { | |||
| 342 | }; | 342 | }; |
| 343 | #endif | 343 | #endif |
| 344 | 344 | ||
| 345 | #ifdef CONFIG_PXA3xx | ||
| 346 | static struct resource pxa3xx_resources_i2c_power[] = { | ||
| 347 | { | ||
| 348 | .start = 0x40f500c0, | ||
| 349 | .end = 0x40f500d3, | ||
| 350 | .flags = IORESOURCE_MEM, | ||
| 351 | }, { | ||
| 352 | .start = IRQ_PWRI2C, | ||
| 353 | .end = IRQ_PWRI2C, | ||
| 354 | .flags = IORESOURCE_IRQ, | ||
| 355 | }, | ||
| 356 | }; | ||
| 357 | |||
| 358 | struct platform_device pxa3xx_device_i2c_power = { | ||
| 359 | .name = "pxa3xx-pwri2c", | ||
| 360 | .id = 1, | ||
| 361 | .resource = pxa3xx_resources_i2c_power, | ||
| 362 | .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power), | ||
| 363 | }; | ||
| 364 | #endif | ||
| 365 | |||
| 366 | static struct resource pxai2s_resources[] = { | 345 | static struct resource pxai2s_resources[] = { |
| 367 | { | 346 | { |
| 368 | .start = 0x40400000, | 347 | .start = 0x40400000, |
| @@ -633,30 +612,35 @@ struct platform_device pxa25x_device_assp = { | |||
| 633 | #endif /* CONFIG_PXA25x */ | 612 | #endif /* CONFIG_PXA25x */ |
| 634 | 613 | ||
| 635 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) | 614 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) |
| 636 | 615 | static struct resource pxa27x_resource_camera[] = { | |
| 637 | static struct resource pxa27x_resource_keypad[] = { | ||
| 638 | [0] = { | 616 | [0] = { |
| 639 | .start = 0x41500000, | 617 | .start = 0x50000000, |
| 640 | .end = 0x4150004c, | 618 | .end = 0x50000fff, |
| 641 | .flags = IORESOURCE_MEM, | 619 | .flags = IORESOURCE_MEM, |
| 642 | }, | 620 | }, |
| 643 | [1] = { | 621 | [1] = { |
| 644 | .start = IRQ_KEYPAD, | 622 | .start = IRQ_CAMERA, |
| 645 | .end = IRQ_KEYPAD, | 623 | .end = IRQ_CAMERA, |
| 646 | .flags = IORESOURCE_IRQ, | 624 | .flags = IORESOURCE_IRQ, |
| 647 | }, | 625 | }, |
| 648 | }; | 626 | }; |
| 649 | 627 | ||
| 650 | struct platform_device pxa27x_device_keypad = { | 628 | static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32); |
| 651 | .name = "pxa27x-keypad", | 629 | |
| 652 | .id = -1, | 630 | static struct platform_device pxa27x_device_camera = { |
| 653 | .resource = pxa27x_resource_keypad, | 631 | .name = "pxa27x-camera", |
| 654 | .num_resources = ARRAY_SIZE(pxa27x_resource_keypad), | 632 | .id = 0, /* This is used to put cameras on this interface */ |
| 633 | .dev = { | ||
| 634 | .dma_mask = &pxa27x_dma_mask_camera, | ||
| 635 | .coherent_dma_mask = 0xffffffff, | ||
| 636 | }, | ||
| 637 | .num_resources = ARRAY_SIZE(pxa27x_resource_camera), | ||
| 638 | .resource = pxa27x_resource_camera, | ||
| 655 | }; | 639 | }; |
| 656 | 640 | ||
| 657 | void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info) | 641 | void __init pxa_set_camera_info(struct pxacamera_platform_data *info) |
| 658 | { | 642 | { |
| 659 | pxa_register_device(&pxa27x_device_keypad, info); | 643 | pxa_register_device(&pxa27x_device_camera, info); |
| 660 | } | 644 | } |
| 661 | 645 | ||
| 662 | static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32); | 646 | static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32); |
| @@ -689,6 +673,33 @@ void __init pxa_set_ohci_info(struct pxaohci_platform_data *info) | |||
| 689 | { | 673 | { |
| 690 | pxa_register_device(&pxa27x_device_ohci, info); | 674 | pxa_register_device(&pxa27x_device_ohci, info); |
| 691 | } | 675 | } |
| 676 | #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */ | ||
| 677 | |||
| 678 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x) | ||
| 679 | static struct resource pxa27x_resource_keypad[] = { | ||
| 680 | [0] = { | ||
| 681 | .start = 0x41500000, | ||
| 682 | .end = 0x4150004c, | ||
| 683 | .flags = IORESOURCE_MEM, | ||
| 684 | }, | ||
| 685 | [1] = { | ||
| 686 | .start = IRQ_KEYPAD, | ||
| 687 | .end = IRQ_KEYPAD, | ||
| 688 | .flags = IORESOURCE_IRQ, | ||
| 689 | }, | ||
| 690 | }; | ||
| 691 | |||
| 692 | struct platform_device pxa27x_device_keypad = { | ||
| 693 | .name = "pxa27x-keypad", | ||
| 694 | .id = -1, | ||
| 695 | .resource = pxa27x_resource_keypad, | ||
| 696 | .num_resources = ARRAY_SIZE(pxa27x_resource_keypad), | ||
| 697 | }; | ||
| 698 | |||
| 699 | void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info) | ||
| 700 | { | ||
| 701 | pxa_register_device(&pxa27x_device_keypad, info); | ||
| 702 | } | ||
| 692 | 703 | ||
| 693 | static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32); | 704 | static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32); |
| 694 | 705 | ||
| @@ -833,79 +844,9 @@ struct platform_device pxa27x_device_pwm1 = { | |||
| 833 | .resource = pxa27x_resource_pwm1, | 844 | .resource = pxa27x_resource_pwm1, |
| 834 | .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1), | 845 | .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1), |
| 835 | }; | 846 | }; |
| 836 | 847 | #endif /* CONFIG_PXA27x || CONFIG_PXA3xx || CONFIG_PXA95x*/ | |
| 837 | static struct resource pxa27x_resource_camera[] = { | ||
| 838 | [0] = { | ||
| 839 | .start = 0x50000000, | ||
| 840 | .end = 0x50000fff, | ||
| 841 | .flags = IORESOURCE_MEM, | ||
| 842 | }, | ||
| 843 | [1] = { | ||
| 844 | .start = IRQ_CAMERA, | ||
| 845 | .end = IRQ_CAMERA, | ||
| 846 | .flags = IORESOURCE_IRQ, | ||
| 847 | }, | ||
| 848 | }; | ||
| 849 | |||
| 850 | static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32); | ||
| 851 | |||
| 852 | static struct platform_device pxa27x_device_camera = { | ||
| 853 | .name = "pxa27x-camera", | ||
| 854 | .id = 0, /* This is used to put cameras on this interface */ | ||
| 855 | .dev = { | ||
| 856 | .dma_mask = &pxa27x_dma_mask_camera, | ||
| 857 | .coherent_dma_mask = 0xffffffff, | ||
| 858 | }, | ||
| 859 | .num_resources = ARRAY_SIZE(pxa27x_resource_camera), | ||
| 860 | .resource = pxa27x_resource_camera, | ||
| 861 | }; | ||
| 862 | |||
| 863 | void __init pxa_set_camera_info(struct pxacamera_platform_data *info) | ||
| 864 | { | ||
| 865 | pxa_register_device(&pxa27x_device_camera, info); | ||
| 866 | } | ||
| 867 | #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */ | ||
| 868 | 848 | ||
| 869 | #ifdef CONFIG_PXA3xx | 849 | #ifdef CONFIG_PXA3xx |
| 870 | static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32); | ||
| 871 | |||
| 872 | static struct resource pxa3xx_resource_ssp4[] = { | ||
| 873 | [0] = { | ||
| 874 | .start = 0x41a00000, | ||
| 875 | .end = 0x41a0003f, | ||
| 876 | .flags = IORESOURCE_MEM, | ||
| 877 | }, | ||
| 878 | [1] = { | ||
| 879 | .start = IRQ_SSP4, | ||
| 880 | .end = IRQ_SSP4, | ||
| 881 | .flags = IORESOURCE_IRQ, | ||
| 882 | }, | ||
| 883 | [2] = { | ||
| 884 | /* DRCMR for RX */ | ||
| 885 | .start = 2, | ||
| 886 | .end = 2, | ||
| 887 | .flags = IORESOURCE_DMA, | ||
| 888 | }, | ||
| 889 | [3] = { | ||
| 890 | /* DRCMR for TX */ | ||
| 891 | .start = 3, | ||
| 892 | .end = 3, | ||
| 893 | .flags = IORESOURCE_DMA, | ||
| 894 | }, | ||
| 895 | }; | ||
| 896 | |||
| 897 | struct platform_device pxa3xx_device_ssp4 = { | ||
| 898 | /* PXA3xx SSP is basically equivalent to PXA27x */ | ||
| 899 | .name = "pxa27x-ssp", | ||
| 900 | .id = 3, | ||
| 901 | .dev = { | ||
| 902 | .dma_mask = &pxa3xx_ssp4_dma_mask, | ||
| 903 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 904 | }, | ||
| 905 | .resource = pxa3xx_resource_ssp4, | ||
| 906 | .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4), | ||
| 907 | }; | ||
| 908 | |||
| 909 | static struct resource pxa3xx_resources_mci2[] = { | 850 | static struct resource pxa3xx_resources_mci2[] = { |
| 910 | [0] = { | 851 | [0] = { |
| 911 | .start = 0x42000000, | 852 | .start = 0x42000000, |
| @@ -984,6 +925,54 @@ void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info) | |||
| 984 | pxa_register_device(&pxa3xx_device_mci3, info); | 925 | pxa_register_device(&pxa3xx_device_mci3, info); |
| 985 | } | 926 | } |
| 986 | 927 | ||
| 928 | static struct resource pxa3xx_resources_gcu[] = { | ||
| 929 | { | ||
| 930 | .start = 0x54000000, | ||
| 931 | .end = 0x54000fff, | ||
| 932 | .flags = IORESOURCE_MEM, | ||
| 933 | }, | ||
| 934 | { | ||
| 935 | .start = IRQ_GCU, | ||
| 936 | .end = IRQ_GCU, | ||
| 937 | .flags = IORESOURCE_IRQ, | ||
| 938 | }, | ||
| 939 | }; | ||
| 940 | |||
| 941 | static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32); | ||
| 942 | |||
| 943 | struct platform_device pxa3xx_device_gcu = { | ||
| 944 | .name = "pxa3xx-gcu", | ||
| 945 | .id = -1, | ||
| 946 | .num_resources = ARRAY_SIZE(pxa3xx_resources_gcu), | ||
| 947 | .resource = pxa3xx_resources_gcu, | ||
| 948 | .dev = { | ||
| 949 | .dma_mask = &pxa3xx_gcu_dmamask, | ||
| 950 | .coherent_dma_mask = 0xffffffff, | ||
| 951 | }, | ||
| 952 | }; | ||
| 953 | |||
| 954 | #endif /* CONFIG_PXA3xx */ | ||
| 955 | |||
| 956 | #if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x) | ||
| 957 | static struct resource pxa3xx_resources_i2c_power[] = { | ||
| 958 | { | ||
| 959 | .start = 0x40f500c0, | ||
| 960 | .end = 0x40f500d3, | ||
| 961 | .flags = IORESOURCE_MEM, | ||
| 962 | }, { | ||
| 963 | .start = IRQ_PWRI2C, | ||
| 964 | .end = IRQ_PWRI2C, | ||
| 965 | .flags = IORESOURCE_IRQ, | ||
| 966 | }, | ||
| 967 | }; | ||
| 968 | |||
| 969 | struct platform_device pxa3xx_device_i2c_power = { | ||
| 970 | .name = "pxa3xx-pwri2c", | ||
| 971 | .id = 1, | ||
| 972 | .resource = pxa3xx_resources_i2c_power, | ||
| 973 | .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power), | ||
| 974 | }; | ||
| 975 | |||
| 987 | static struct resource pxa3xx_resources_nand[] = { | 976 | static struct resource pxa3xx_resources_nand[] = { |
| 988 | [0] = { | 977 | [0] = { |
| 989 | .start = 0x43100000, | 978 | .start = 0x43100000, |
| @@ -1027,33 +1016,45 @@ void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info) | |||
| 1027 | pxa_register_device(&pxa3xx_device_nand, info); | 1016 | pxa_register_device(&pxa3xx_device_nand, info); |
| 1028 | } | 1017 | } |
| 1029 | 1018 | ||
| 1030 | static struct resource pxa3xx_resources_gcu[] = { | 1019 | static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32); |
| 1031 | { | 1020 | |
| 1032 | .start = 0x54000000, | 1021 | static struct resource pxa3xx_resource_ssp4[] = { |
| 1033 | .end = 0x54000fff, | 1022 | [0] = { |
| 1023 | .start = 0x41a00000, | ||
| 1024 | .end = 0x41a0003f, | ||
| 1034 | .flags = IORESOURCE_MEM, | 1025 | .flags = IORESOURCE_MEM, |
| 1035 | }, | 1026 | }, |
| 1036 | { | 1027 | [1] = { |
| 1037 | .start = IRQ_GCU, | 1028 | .start = IRQ_SSP4, |
| 1038 | .end = IRQ_GCU, | 1029 | .end = IRQ_SSP4, |
| 1039 | .flags = IORESOURCE_IRQ, | 1030 | .flags = IORESOURCE_IRQ, |
| 1040 | }, | 1031 | }, |
| 1032 | [2] = { | ||
| 1033 | /* DRCMR for RX */ | ||
| 1034 | .start = 2, | ||
| 1035 | .end = 2, | ||
| 1036 | .flags = IORESOURCE_DMA, | ||
| 1037 | }, | ||
| 1038 | [3] = { | ||
| 1039 | /* DRCMR for TX */ | ||
| 1040 | .start = 3, | ||
| 1041 | .end = 3, | ||
| 1042 | .flags = IORESOURCE_DMA, | ||
| 1043 | }, | ||
| 1041 | }; | 1044 | }; |
| 1042 | 1045 | ||
| 1043 | static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32); | 1046 | struct platform_device pxa3xx_device_ssp4 = { |
| 1044 | 1047 | /* PXA3xx SSP is basically equivalent to PXA27x */ | |
| 1045 | struct platform_device pxa3xx_device_gcu = { | 1048 | .name = "pxa27x-ssp", |
| 1046 | .name = "pxa3xx-gcu", | 1049 | .id = 3, |
| 1047 | .id = -1, | ||
| 1048 | .num_resources = ARRAY_SIZE(pxa3xx_resources_gcu), | ||
| 1049 | .resource = pxa3xx_resources_gcu, | ||
| 1050 | .dev = { | 1050 | .dev = { |
| 1051 | .dma_mask = &pxa3xx_gcu_dmamask, | 1051 | .dma_mask = &pxa3xx_ssp4_dma_mask, |
| 1052 | .coherent_dma_mask = 0xffffffff, | 1052 | .coherent_dma_mask = DMA_BIT_MASK(32), |
| 1053 | }, | 1053 | }, |
| 1054 | .resource = pxa3xx_resource_ssp4, | ||
| 1055 | .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4), | ||
| 1054 | }; | 1056 | }; |
| 1055 | 1057 | #endif /* CONFIG_PXA3xx || CONFIG_PXA95x */ | |
| 1056 | #endif /* CONFIG_PXA3xx */ | ||
| 1057 | 1058 | ||
| 1058 | /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1. | 1059 | /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1. |
| 1059 | * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */ | 1060 | * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */ |
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index ed0dbfdb22ed..a78bb3097739 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c | |||
| @@ -26,6 +26,7 @@ | |||
| 26 | #include <linux/spi/spi.h> | 26 | #include <linux/spi/spi.h> |
| 27 | #include <linux/spi/tdo24m.h> | 27 | #include <linux/spi/tdo24m.h> |
| 28 | #include <linux/spi/libertas_spi.h> | 28 | #include <linux/spi/libertas_spi.h> |
| 29 | #include <linux/spi/pxa2xx_spi.h> | ||
| 29 | #include <linux/power_supply.h> | 30 | #include <linux/power_supply.h> |
| 30 | #include <linux/apm-emulation.h> | 31 | #include <linux/apm-emulation.h> |
| 31 | #include <linux/i2c.h> | 32 | #include <linux/i2c.h> |
| @@ -46,7 +47,6 @@ | |||
| 46 | #include <plat/pxa27x_keypad.h> | 47 | #include <plat/pxa27x_keypad.h> |
| 47 | #include <plat/i2c.h> | 48 | #include <plat/i2c.h> |
| 48 | #include <mach/camera.h> | 49 | #include <mach/camera.h> |
| 49 | #include <mach/pxa2xx_spi.h> | ||
| 50 | 50 | ||
| 51 | #include "generic.h" | 51 | #include "generic.h" |
| 52 | #include "devices.h" | 52 | #include "devices.h" |
| @@ -1300,7 +1300,7 @@ static void __init em_x270_init(void) | |||
| 1300 | 1300 | ||
| 1301 | MACHINE_START(EM_X270, "Compulab EM-X270") | 1301 | MACHINE_START(EM_X270, "Compulab EM-X270") |
| 1302 | .boot_params = 0xa0000100, | 1302 | .boot_params = 0xa0000100, |
| 1303 | .map_io = pxa_map_io, | 1303 | .map_io = pxa27x_map_io, |
| 1304 | .init_irq = pxa27x_init_irq, | 1304 | .init_irq = pxa27x_init_irq, |
| 1305 | .timer = &pxa_timer, | 1305 | .timer = &pxa_timer, |
| 1306 | .init_machine = em_x270_init, | 1306 | .init_machine = em_x270_init, |
| @@ -1308,7 +1308,7 @@ MACHINE_END | |||
| 1308 | 1308 | ||
| 1309 | MACHINE_START(EXEDA, "Compulab eXeda") | 1309 | MACHINE_START(EXEDA, "Compulab eXeda") |
| 1310 | .boot_params = 0xa0000100, | 1310 | .boot_params = 0xa0000100, |
| 1311 | .map_io = pxa_map_io, | 1311 | .map_io = pxa27x_map_io, |
| 1312 | .init_irq = pxa27x_init_irq, | 1312 | .init_irq = pxa27x_init_irq, |
| 1313 | .timer = &pxa_timer, | 1313 | .timer = &pxa_timer, |
| 1314 | .init_machine = em_x270_init, | 1314 | .init_machine = em_x270_init, |
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c index b25690ccadc4..edca0a043293 100644 --- a/arch/arm/mach-pxa/eseries.c +++ b/arch/arm/mach-pxa/eseries.c | |||
| @@ -181,7 +181,7 @@ static void __init e330_init(void) | |||
| 181 | MACHINE_START(E330, "Toshiba e330") | 181 | MACHINE_START(E330, "Toshiba e330") |
| 182 | /* Maintainer: Ian Molton (spyro@f2s.com) */ | 182 | /* Maintainer: Ian Molton (spyro@f2s.com) */ |
| 183 | .boot_params = 0xa0000100, | 183 | .boot_params = 0xa0000100, |
| 184 | .map_io = pxa_map_io, | 184 | .map_io = pxa25x_map_io, |
| 185 | .nr_irqs = ESERIES_NR_IRQS, | 185 | .nr_irqs = ESERIES_NR_IRQS, |
| 186 | .init_irq = pxa25x_init_irq, | 186 | .init_irq = pxa25x_init_irq, |
| 187 | .fixup = eseries_fixup, | 187 | .fixup = eseries_fixup, |
| @@ -230,7 +230,7 @@ static void __init e350_init(void) | |||
| 230 | MACHINE_START(E350, "Toshiba e350") | 230 | MACHINE_START(E350, "Toshiba e350") |
| 231 | /* Maintainer: Ian Molton (spyro@f2s.com) */ | 231 | /* Maintainer: Ian Molton (spyro@f2s.com) */ |
| 232 | .boot_params = 0xa0000100, | 232 | .boot_params = 0xa0000100, |
| 233 | .map_io = pxa_map_io, | 233 | .map_io = pxa25x_map_io, |
| 234 | .nr_irqs = ESERIES_NR_IRQS, | 234 | .nr_irqs = ESERIES_NR_IRQS, |
| 235 | .init_irq = pxa25x_init_irq, | 235 | .init_irq = pxa25x_init_irq, |
| 236 | .fixup = eseries_fixup, | 236 | .fixup = eseries_fixup, |
| @@ -352,7 +352,7 @@ static void __init e400_init(void) | |||
| 352 | MACHINE_START(E400, "Toshiba e400") | 352 | MACHINE_START(E400, "Toshiba e400") |
| 353 | /* Maintainer: Ian Molton (spyro@f2s.com) */ | 353 | /* Maintainer: Ian Molton (spyro@f2s.com) */ |
| 354 | .boot_params = 0xa0000100, | 354 | .boot_params = 0xa0000100, |
| 355 | .map_io = pxa_map_io, | 355 | .map_io = pxa25x_map_io, |
| 356 | .nr_irqs = ESERIES_NR_IRQS, | 356 | .nr_irqs = ESERIES_NR_IRQS, |
| 357 | .init_irq = pxa25x_init_irq, | 357 | .init_irq = pxa25x_init_irq, |
| 358 | .fixup = eseries_fixup, | 358 | .fixup = eseries_fixup, |
| @@ -540,7 +540,7 @@ static void __init e740_init(void) | |||
| 540 | MACHINE_START(E740, "Toshiba e740") | 540 | MACHINE_START(E740, "Toshiba e740") |
| 541 | /* Maintainer: Ian Molton (spyro@f2s.com) */ | 541 | /* Maintainer: Ian Molton (spyro@f2s.com) */ |
| 542 | .boot_params = 0xa0000100, | 542 | .boot_params = 0xa0000100, |
| 543 | .map_io = pxa_map_io, | 543 | .map_io = pxa25x_map_io, |
| 544 | .nr_irqs = ESERIES_NR_IRQS, | 544 | .nr_irqs = ESERIES_NR_IRQS, |
| 545 | .init_irq = pxa25x_init_irq, | 545 | .init_irq = pxa25x_init_irq, |
| 546 | .fixup = eseries_fixup, | 546 | .fixup = eseries_fixup, |
| @@ -731,7 +731,7 @@ static void __init e750_init(void) | |||
| 731 | MACHINE_START(E750, "Toshiba e750") | 731 | MACHINE_START(E750, "Toshiba e750") |
| 732 | /* Maintainer: Ian Molton (spyro@f2s.com) */ | 732 | /* Maintainer: Ian Molton (spyro@f2s.com) */ |
| 733 | .boot_params = 0xa0000100, | 733 | .boot_params = 0xa0000100, |
| 734 | .map_io = pxa_map_io, | 734 | .map_io = pxa25x_map_io, |
| 735 | .nr_irqs = ESERIES_NR_IRQS, | 735 | .nr_irqs = ESERIES_NR_IRQS, |
| 736 | .init_irq = pxa25x_init_irq, | 736 | .init_irq = pxa25x_init_irq, |
| 737 | .fixup = eseries_fixup, | 737 | .fixup = eseries_fixup, |
| @@ -926,7 +926,7 @@ static void __init e800_init(void) | |||
| 926 | MACHINE_START(E800, "Toshiba e800") | 926 | MACHINE_START(E800, "Toshiba e800") |
| 927 | /* Maintainer: Ian Molton (spyro@f2s.com) */ | 927 | /* Maintainer: Ian Molton (spyro@f2s.com) */ |
| 928 | .boot_params = 0xa0000100, | 928 | .boot_params = 0xa0000100, |
| 929 | .map_io = pxa_map_io, | 929 | .map_io = pxa25x_map_io, |
| 930 | .nr_irqs = ESERIES_NR_IRQS, | 930 | .nr_irqs = ESERIES_NR_IRQS, |
| 931 | .init_irq = pxa25x_init_irq, | 931 | .init_irq = pxa25x_init_irq, |
| 932 | .fixup = eseries_fixup, | 932 | .fixup = eseries_fixup, |
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c index 142c711f4cda..87cec0abe5b0 100644 --- a/arch/arm/mach-pxa/ezx.c +++ b/arch/arm/mach-pxa/ezx.c | |||
| @@ -798,7 +798,7 @@ static void __init a780_init(void) | |||
| 798 | 798 | ||
| 799 | MACHINE_START(EZX_A780, "Motorola EZX A780") | 799 | MACHINE_START(EZX_A780, "Motorola EZX A780") |
| 800 | .boot_params = 0xa0000100, | 800 | .boot_params = 0xa0000100, |
| 801 | .map_io = pxa_map_io, | 801 | .map_io = pxa27x_map_io, |
| 802 | .nr_irqs = EZX_NR_IRQS, | 802 | .nr_irqs = EZX_NR_IRQS, |
| 803 | .init_irq = pxa27x_init_irq, | 803 | .init_irq = pxa27x_init_irq, |
| 804 | .timer = &pxa_timer, | 804 | .timer = &pxa_timer, |
| @@ -863,7 +863,7 @@ static void __init e680_init(void) | |||
| 863 | 863 | ||
| 864 | MACHINE_START(EZX_E680, "Motorola EZX E680") | 864 | MACHINE_START(EZX_E680, "Motorola EZX E680") |
| 865 | .boot_params = 0xa0000100, | 865 | .boot_params = 0xa0000100, |
| 866 | .map_io = pxa_map_io, | 866 | .map_io = pxa27x_map_io, |
| 867 | .nr_irqs = EZX_NR_IRQS, | 867 | .nr_irqs = EZX_NR_IRQS, |
| 868 | .init_irq = pxa27x_init_irq, | 868 | .init_irq = pxa27x_init_irq, |
| 869 | .timer = &pxa_timer, | 869 | .timer = &pxa_timer, |
| @@ -928,7 +928,7 @@ static void __init a1200_init(void) | |||
| 928 | 928 | ||
| 929 | MACHINE_START(EZX_A1200, "Motorola EZX A1200") | 929 | MACHINE_START(EZX_A1200, "Motorola EZX A1200") |
| 930 | .boot_params = 0xa0000100, | 930 | .boot_params = 0xa0000100, |
| 931 | .map_io = pxa_map_io, | 931 | .map_io = pxa27x_map_io, |
| 932 | .nr_irqs = EZX_NR_IRQS, | 932 | .nr_irqs = EZX_NR_IRQS, |
| 933 | .init_irq = pxa27x_init_irq, | 933 | .init_irq = pxa27x_init_irq, |
| 934 | .timer = &pxa_timer, | 934 | .timer = &pxa_timer, |
| @@ -1118,7 +1118,7 @@ static void __init a910_init(void) | |||
| 1118 | 1118 | ||
| 1119 | MACHINE_START(EZX_A910, "Motorola EZX A910") | 1119 | MACHINE_START(EZX_A910, "Motorola EZX A910") |
| 1120 | .boot_params = 0xa0000100, | 1120 | .boot_params = 0xa0000100, |
| 1121 | .map_io = pxa_map_io, | 1121 | .map_io = pxa27x_map_io, |
| 1122 | .nr_irqs = EZX_NR_IRQS, | 1122 | .nr_irqs = EZX_NR_IRQS, |
| 1123 | .init_irq = pxa27x_init_irq, | 1123 | .init_irq = pxa27x_init_irq, |
| 1124 | .timer = &pxa_timer, | 1124 | .timer = &pxa_timer, |
| @@ -1183,7 +1183,7 @@ static void __init e6_init(void) | |||
| 1183 | 1183 | ||
| 1184 | MACHINE_START(EZX_E6, "Motorola EZX E6") | 1184 | MACHINE_START(EZX_E6, "Motorola EZX E6") |
| 1185 | .boot_params = 0xa0000100, | 1185 | .boot_params = 0xa0000100, |
| 1186 | .map_io = pxa_map_io, | 1186 | .map_io = pxa27x_map_io, |
| 1187 | .nr_irqs = EZX_NR_IRQS, | 1187 | .nr_irqs = EZX_NR_IRQS, |
| 1188 | .init_irq = pxa27x_init_irq, | 1188 | .init_irq = pxa27x_init_irq, |
| 1189 | .timer = &pxa_timer, | 1189 | .timer = &pxa_timer, |
| @@ -1222,7 +1222,7 @@ static void __init e2_init(void) | |||
| 1222 | 1222 | ||
| 1223 | MACHINE_START(EZX_E2, "Motorola EZX E2") | 1223 | MACHINE_START(EZX_E2, "Motorola EZX E2") |
| 1224 | .boot_params = 0xa0000100, | 1224 | .boot_params = 0xa0000100, |
| 1225 | .map_io = pxa_map_io, | 1225 | .map_io = pxa27x_map_io, |
| 1226 | .nr_irqs = EZX_NR_IRQS, | 1226 | .nr_irqs = EZX_NR_IRQS, |
| 1227 | .init_irq = pxa27x_init_irq, | 1227 | .init_irq = pxa27x_init_irq, |
| 1228 | .timer = &pxa_timer, | 1228 | .timer = &pxa_timer, |
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c index 6451e9c3a93f..d6e15f71fc09 100644 --- a/arch/arm/mach-pxa/generic.c +++ b/arch/arm/mach-pxa/generic.c | |||
| @@ -28,6 +28,8 @@ | |||
| 28 | 28 | ||
| 29 | #include <mach/reset.h> | 29 | #include <mach/reset.h> |
| 30 | #include <mach/gpio.h> | 30 | #include <mach/gpio.h> |
| 31 | #include <mach/smemc.h> | ||
| 32 | #include <mach/pxa3xx-regs.h> | ||
| 31 | 33 | ||
| 32 | #include "generic.h" | 34 | #include "generic.h" |
| 33 | 35 | ||
| @@ -35,9 +37,10 @@ void clear_reset_status(unsigned int mask) | |||
| 35 | { | 37 | { |
| 36 | if (cpu_is_pxa2xx()) | 38 | if (cpu_is_pxa2xx()) |
| 37 | pxa2xx_clear_reset_status(mask); | 39 | pxa2xx_clear_reset_status(mask); |
| 38 | 40 | else { | |
| 39 | if (cpu_is_pxa3xx()) | 41 | /* RESET_STATUS_* has a 1:1 mapping with ARSR */ |
| 40 | pxa3xx_clear_reset_status(mask); | 42 | ARSR = mask; |
| 43 | } | ||
| 41 | } | 44 | } |
| 42 | 45 | ||
| 43 | unsigned long get_clock_tick_rate(void) | 46 | unsigned long get_clock_tick_rate(void) |
| @@ -71,47 +74,17 @@ unsigned int get_clk_frequency_khz(int info) | |||
| 71 | EXPORT_SYMBOL(get_clk_frequency_khz); | 74 | EXPORT_SYMBOL(get_clk_frequency_khz); |
| 72 | 75 | ||
| 73 | /* | 76 | /* |
| 74 | * Return the current memory clock frequency in units of 10kHz | ||
| 75 | */ | ||
| 76 | unsigned int get_memclk_frequency_10khz(void) | ||
| 77 | { | ||
| 78 | if (cpu_is_pxa25x()) | ||
| 79 | return pxa25x_get_memclk_frequency_10khz(); | ||
| 80 | else if (cpu_is_pxa27x()) | ||
| 81 | return pxa27x_get_memclk_frequency_10khz(); | ||
| 82 | return 0; | ||
| 83 | } | ||
| 84 | EXPORT_SYMBOL(get_memclk_frequency_10khz); | ||
| 85 | |||
| 86 | /* | ||
| 87 | * Intel PXA2xx internal register mapping. | 77 | * Intel PXA2xx internal register mapping. |
| 88 | * | 78 | * |
| 89 | * Note 1: not all PXA2xx variants implement all those addresses. | 79 | * Note: virtual 0xfffe0000-0xffffffff is reserved for the vector table |
| 90 | * | 80 | * and cache flush area. |
| 91 | * Note 2: virtual 0xfffe0000-0xffffffff is reserved for the vector table | ||
| 92 | * and cache flush area. | ||
| 93 | */ | 81 | */ |
| 94 | static struct map_desc standard_io_desc[] __initdata = { | 82 | static struct map_desc common_io_desc[] __initdata = { |
| 95 | { /* Devs */ | 83 | { /* Devs */ |
| 96 | .virtual = 0xf2000000, | 84 | .virtual = 0xf2000000, |
| 97 | .pfn = __phys_to_pfn(0x40000000), | 85 | .pfn = __phys_to_pfn(0x40000000), |
| 98 | .length = 0x02000000, | 86 | .length = 0x02000000, |
| 99 | .type = MT_DEVICE | 87 | .type = MT_DEVICE |
| 100 | }, { /* Mem Ctl */ | ||
| 101 | .virtual = 0xf6000000, | ||
| 102 | .pfn = __phys_to_pfn(0x48000000), | ||
| 103 | .length = 0x00200000, | ||
| 104 | .type = MT_DEVICE | ||
| 105 | }, { /* Camera */ | ||
| 106 | .virtual = 0xfa000000, | ||
| 107 | .pfn = __phys_to_pfn(0x50000000), | ||
| 108 | .length = 0x00100000, | ||
| 109 | .type = MT_DEVICE | ||
| 110 | }, { /* IMem ctl */ | ||
| 111 | .virtual = 0xfe000000, | ||
| 112 | .pfn = __phys_to_pfn(0x58000000), | ||
| 113 | .length = 0x00100000, | ||
| 114 | .type = MT_DEVICE | ||
| 115 | }, { /* UNCACHED_PHYS_0 */ | 88 | }, { /* UNCACHED_PHYS_0 */ |
| 116 | .virtual = 0xff000000, | 89 | .virtual = 0xff000000, |
| 117 | .pfn = __phys_to_pfn(0x00000000), | 90 | .pfn = __phys_to_pfn(0x00000000), |
| @@ -122,6 +95,5 @@ static struct map_desc standard_io_desc[] __initdata = { | |||
| 122 | 95 | ||
| 123 | void __init pxa_map_io(void) | 96 | void __init pxa_map_io(void) |
| 124 | { | 97 | { |
| 125 | iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); | 98 | iotable_init(ARRAY_AND_SIZE(common_io_desc)); |
| 126 | get_clk_frequency_khz(1); | ||
| 127 | } | 99 | } |
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h index 4b1ad2769ed7..6205dc9a2b9d 100644 --- a/arch/arm/mach-pxa/generic.h +++ b/arch/arm/mach-pxa/generic.h | |||
| @@ -20,7 +20,12 @@ extern void __init pxa26x_init_irq(void); | |||
| 20 | #endif | 20 | #endif |
| 21 | extern void __init pxa27x_init_irq(void); | 21 | extern void __init pxa27x_init_irq(void); |
| 22 | extern void __init pxa3xx_init_irq(void); | 22 | extern void __init pxa3xx_init_irq(void); |
| 23 | extern void __init pxa95x_init_irq(void); | ||
| 24 | |||
| 23 | extern void __init pxa_map_io(void); | 25 | extern void __init pxa_map_io(void); |
| 26 | extern void __init pxa25x_map_io(void); | ||
| 27 | extern void __init pxa27x_map_io(void); | ||
| 28 | extern void __init pxa3xx_map_io(void); | ||
| 24 | 29 | ||
| 25 | extern unsigned int get_clk_frequency_khz(int info); | 30 | extern unsigned int get_clk_frequency_khz(int info); |
| 26 | 31 | ||
| @@ -32,18 +37,14 @@ extern unsigned int get_clk_frequency_khz(int info); | |||
| 32 | 37 | ||
| 33 | #ifdef CONFIG_PXA25x | 38 | #ifdef CONFIG_PXA25x |
| 34 | extern unsigned pxa25x_get_clk_frequency_khz(int); | 39 | extern unsigned pxa25x_get_clk_frequency_khz(int); |
| 35 | extern unsigned pxa25x_get_memclk_frequency_10khz(void); | ||
| 36 | #else | 40 | #else |
| 37 | #define pxa25x_get_clk_frequency_khz(x) (0) | 41 | #define pxa25x_get_clk_frequency_khz(x) (0) |
| 38 | #define pxa25x_get_memclk_frequency_10khz() (0) | ||
| 39 | #endif | 42 | #endif |
| 40 | 43 | ||
| 41 | #ifdef CONFIG_PXA27x | 44 | #ifdef CONFIG_PXA27x |
| 42 | extern unsigned pxa27x_get_clk_frequency_khz(int); | 45 | extern unsigned pxa27x_get_clk_frequency_khz(int); |
| 43 | extern unsigned pxa27x_get_memclk_frequency_10khz(void); | ||
| 44 | #else | 46 | #else |
| 45 | #define pxa27x_get_clk_frequency_khz(x) (0) | 47 | #define pxa27x_get_clk_frequency_khz(x) (0) |
| 46 | #define pxa27x_get_memclk_frequency_10khz() (0) | ||
| 47 | #endif | 48 | #endif |
| 48 | 49 | ||
| 49 | #if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x) | 50 | #if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x) |
| @@ -54,10 +55,8 @@ static inline void pxa2xx_clear_reset_status(unsigned int mask) {} | |||
| 54 | 55 | ||
| 55 | #ifdef CONFIG_PXA3xx | 56 | #ifdef CONFIG_PXA3xx |
| 56 | extern unsigned pxa3xx_get_clk_frequency_khz(int); | 57 | extern unsigned pxa3xx_get_clk_frequency_khz(int); |
| 57 | extern void pxa3xx_clear_reset_status(unsigned int); | ||
| 58 | #else | 58 | #else |
| 59 | #define pxa3xx_get_clk_frequency_khz(x) (0) | 59 | #define pxa3xx_get_clk_frequency_khz(x) (0) |
| 60 | static inline void pxa3xx_clear_reset_status(unsigned int mask) {} | ||
| 61 | #endif | 60 | #endif |
| 62 | 61 | ||
| 63 | extern struct sysdev_class pxa_irq_sysclass; | 62 | extern struct sysdev_class pxa_irq_sysclass; |
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c index 1e2a9a13aec1..6fd319ea5284 100644 --- a/arch/arm/mach-pxa/gumstix.c +++ b/arch/arm/mach-pxa/gumstix.c | |||
| @@ -225,7 +225,7 @@ static void __init gumstix_init(void) | |||
| 225 | 225 | ||
| 226 | MACHINE_START(GUMSTIX, "Gumstix") | 226 | MACHINE_START(GUMSTIX, "Gumstix") |
| 227 | .boot_params = 0xa0000100, /* match u-boot bi_boot_params */ | 227 | .boot_params = 0xa0000100, /* match u-boot bi_boot_params */ |
| 228 | .map_io = pxa_map_io, | 228 | .map_io = pxa25x_map_io, |
| 229 | .init_irq = pxa25x_init_irq, | 229 | .init_irq = pxa25x_init_irq, |
| 230 | .timer = &pxa_timer, | 230 | .timer = &pxa_timer, |
| 231 | .init_machine = gumstix_init, | 231 | .init_machine = gumstix_init, |
diff --git a/arch/arm/mach-pxa/h5000.c b/arch/arm/mach-pxa/h5000.c index 7057a1f46db4..657db469de1f 100644 --- a/arch/arm/mach-pxa/h5000.c +++ b/arch/arm/mach-pxa/h5000.c | |||
| @@ -32,6 +32,7 @@ | |||
| 32 | #include <mach/pxa25x.h> | 32 | #include <mach/pxa25x.h> |
| 33 | #include <mach/h5000.h> | 33 | #include <mach/h5000.h> |
| 34 | #include <mach/udc.h> | 34 | #include <mach/udc.h> |
| 35 | #include <mach/smemc.h> | ||
| 35 | 36 | ||
| 36 | #include "generic.h" | 37 | #include "generic.h" |
| 37 | 38 | ||
| @@ -172,11 +173,11 @@ static unsigned long h5000_pin_config[] __initdata = { | |||
| 172 | 173 | ||
| 173 | static void fix_msc(void) | 174 | static void fix_msc(void) |
| 174 | { | 175 | { |
| 175 | MSC0 = 0x129c24f2; | 176 | __raw_writel(0x129c24f2, MSC0); |
| 176 | MSC1 = 0x7ff424fa; | 177 | __raw_writel(0x7ff424fa, MSC1); |
| 177 | MSC2 = 0x7ff47ff4; | 178 | __raw_writel(0x7ff47ff4, MSC2); |
| 178 | 179 | ||
| 179 | MDREFR |= 0x02080000; | 180 | __raw_writel(__raw_readl(MDREFR) | 0x02080000, MDREFR); |
| 180 | } | 181 | } |
| 181 | 182 | ||
| 182 | /* | 183 | /* |
| @@ -202,7 +203,7 @@ static void __init h5000_init(void) | |||
| 202 | 203 | ||
| 203 | MACHINE_START(H5400, "HP iPAQ H5000") | 204 | MACHINE_START(H5400, "HP iPAQ H5000") |
| 204 | .boot_params = 0xa0000100, | 205 | .boot_params = 0xa0000100, |
| 205 | .map_io = pxa_map_io, | 206 | .map_io = pxa25x_map_io, |
| 206 | .init_irq = pxa25x_init_irq, | 207 | .init_irq = pxa25x_init_irq, |
| 207 | .timer = &pxa_timer, | 208 | .timer = &pxa_timer, |
| 208 | .init_machine = h5000_init, | 209 | .init_machine = h5000_init, |
diff --git a/arch/arm/mach-pxa/himalaya.c b/arch/arm/mach-pxa/himalaya.c index 01b7f07ebad2..e8603eba54bd 100644 --- a/arch/arm/mach-pxa/himalaya.c +++ b/arch/arm/mach-pxa/himalaya.c | |||
| @@ -160,7 +160,7 @@ static void __init himalaya_init(void) | |||
| 160 | 160 | ||
| 161 | MACHINE_START(HIMALAYA, "HTC Himalaya") | 161 | MACHINE_START(HIMALAYA, "HTC Himalaya") |
| 162 | .boot_params = 0xa0000100, | 162 | .boot_params = 0xa0000100, |
| 163 | .map_io = pxa_map_io, | 163 | .map_io = pxa25x_map_io, |
| 164 | .init_irq = pxa25x_init_irq, | 164 | .init_irq = pxa25x_init_irq, |
| 165 | .init_machine = himalaya_init, | 165 | .init_machine = himalaya_init, |
| 166 | .timer = &pxa_timer, | 166 | .timer = &pxa_timer, |
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c index 76d93a25bab6..a908e0a5f396 100644 --- a/arch/arm/mach-pxa/hx4700.c +++ b/arch/arm/mach-pxa/hx4700.c | |||
| @@ -33,6 +33,7 @@ | |||
| 33 | #include <linux/regulator/max1586.h> | 33 | #include <linux/regulator/max1586.h> |
| 34 | #include <linux/spi/ads7846.h> | 34 | #include <linux/spi/ads7846.h> |
| 35 | #include <linux/spi/spi.h> | 35 | #include <linux/spi/spi.h> |
| 36 | #include <linux/spi/pxa2xx_spi.h> | ||
| 36 | #include <linux/usb/gpio_vbus.h> | 37 | #include <linux/usb/gpio_vbus.h> |
| 37 | 38 | ||
| 38 | #include <mach/hardware.h> | 39 | #include <mach/hardware.h> |
| @@ -43,7 +44,6 @@ | |||
| 43 | #include <mach/hx4700.h> | 44 | #include <mach/hx4700.h> |
| 44 | #include <plat/i2c.h> | 45 | #include <plat/i2c.h> |
| 45 | #include <mach/irda.h> | 46 | #include <mach/irda.h> |
| 46 | #include <mach/pxa2xx_spi.h> | ||
| 47 | 47 | ||
| 48 | #include <video/platform_lcd.h> | 48 | #include <video/platform_lcd.h> |
| 49 | #include <video/w100fb.h> | 49 | #include <video/w100fb.h> |
| @@ -871,7 +871,7 @@ static void __init hx4700_init(void) | |||
| 871 | 871 | ||
| 872 | MACHINE_START(H4700, "HP iPAQ HX4700") | 872 | MACHINE_START(H4700, "HP iPAQ HX4700") |
| 873 | .boot_params = 0xa0000100, | 873 | .boot_params = 0xa0000100, |
| 874 | .map_io = pxa_map_io, | 874 | .map_io = pxa27x_map_io, |
| 875 | .nr_irqs = HX4700_NR_IRQS, | 875 | .nr_irqs = HX4700_NR_IRQS, |
| 876 | .init_irq = pxa27x_init_irq, | 876 | .init_irq = pxa27x_init_irq, |
| 877 | .init_machine = hx4700_init, | 877 | .init_machine = hx4700_init, |
diff --git a/arch/arm/mach-pxa/icontrol.c b/arch/arm/mach-pxa/icontrol.c index d51ee3d25e70..6cedc81da3bc 100644 --- a/arch/arm/mach-pxa/icontrol.c +++ b/arch/arm/mach-pxa/icontrol.c | |||
| @@ -24,7 +24,7 @@ | |||
| 24 | #include <mach/mxm8x10.h> | 24 | #include <mach/mxm8x10.h> |
| 25 | 25 | ||
| 26 | #include <linux/spi/spi.h> | 26 | #include <linux/spi/spi.h> |
| 27 | #include <mach/pxa2xx_spi.h> | 27 | #include <linux/spi/pxa2xx_spi.h> |
| 28 | #include <linux/can/platform/mcp251x.h> | 28 | #include <linux/can/platform/mcp251x.h> |
| 29 | 29 | ||
| 30 | #include "generic.h" | 30 | #include "generic.h" |
| @@ -192,7 +192,7 @@ static void __init icontrol_init(void) | |||
| 192 | 192 | ||
| 193 | MACHINE_START(ICONTROL, "iControl/SafeTcam boards using Embedian MXM-8x10 CoM") | 193 | MACHINE_START(ICONTROL, "iControl/SafeTcam boards using Embedian MXM-8x10 CoM") |
| 194 | .boot_params = 0xa0000100, | 194 | .boot_params = 0xa0000100, |
| 195 | .map_io = pxa_map_io, | 195 | .map_io = pxa3xx_map_io, |
| 196 | .init_irq = pxa3xx_init_irq, | 196 | .init_irq = pxa3xx_init_irq, |
| 197 | .timer = &pxa_timer, | 197 | .timer = &pxa_timer, |
| 198 | .init_machine = icontrol_init | 198 | .init_machine = icontrol_init |
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c index e773dceeabc6..dd40e4a9291c 100644 --- a/arch/arm/mach-pxa/idp.c +++ b/arch/arm/mach-pxa/idp.c | |||
| @@ -187,7 +187,7 @@ static struct map_desc idp_io_desc[] __initdata = { | |||
| 187 | 187 | ||
| 188 | static void __init idp_map_io(void) | 188 | static void __init idp_map_io(void) |
| 189 | { | 189 | { |
| 190 | pxa_map_io(); | 190 | pxa25x_map_io(); |
| 191 | iotable_init(idp_io_desc, ARRAY_SIZE(idp_io_desc)); | 191 | iotable_init(idp_io_desc, ARRAY_SIZE(idp_io_desc)); |
| 192 | } | 192 | } |
| 193 | 193 | ||
diff --git a/arch/arm/mach-pxa/include/mach/addr-map.h b/arch/arm/mach-pxa/include/mach/addr-map.h new file mode 100644 index 000000000000..f4c03659168c --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/addr-map.h | |||
| @@ -0,0 +1,48 @@ | |||
| 1 | #ifndef __ASM_MACH_ADDR_MAP_H | ||
| 2 | #define __ASM_MACH_ADDR_MAP_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * Chip Selects | ||
| 6 | */ | ||
| 7 | #define PXA_CS0_PHYS 0x00000000 | ||
| 8 | #define PXA_CS1_PHYS 0x04000000 | ||
| 9 | #define PXA_CS2_PHYS 0x08000000 | ||
| 10 | #define PXA_CS3_PHYS 0x0C000000 | ||
| 11 | #define PXA_CS4_PHYS 0x10000000 | ||
| 12 | #define PXA_CS5_PHYS 0x14000000 | ||
| 13 | |||
| 14 | #define PXA300_CS0_PHYS 0x00000000 /* PXA300/PXA310 _only_ */ | ||
| 15 | #define PXA300_CS1_PHYS 0x30000000 /* PXA300/PXA310 _only_ */ | ||
| 16 | #define PXA3xx_CS2_PHYS 0x10000000 | ||
| 17 | #define PXA3xx_CS3_PHYS 0x14000000 | ||
| 18 | |||
| 19 | /* | ||
| 20 | * Peripheral Bus | ||
| 21 | */ | ||
| 22 | #define PERIPH_PHYS 0x40000000 | ||
| 23 | #define PERIPH_VIRT 0xf2000000 | ||
| 24 | #define PERIPH_SIZE 0x02000000 | ||
| 25 | |||
| 26 | /* | ||
| 27 | * Static Memory Controller (w/ SDRAM controls on PXA25x/PXA27x) | ||
| 28 | */ | ||
| 29 | #define PXA2XX_SMEMC_PHYS 0x48000000 | ||
| 30 | #define PXA3XX_SMEMC_PHYS 0x4a000000 | ||
| 31 | #define SMEMC_VIRT 0xf6000000 | ||
| 32 | #define SMEMC_SIZE 0x00100000 | ||
| 33 | |||
| 34 | /* | ||
| 35 | * Dynamic Memory Controller (only on PXA3xx) | ||
| 36 | */ | ||
| 37 | #define DMEMC_PHYS 0x48100000 | ||
| 38 | #define DMEMC_VIRT 0xf6100000 | ||
| 39 | #define DMEMC_SIZE 0x00100000 | ||
| 40 | |||
| 41 | /* | ||
| 42 | * Internal Memory Controller (PXA27x and later) | ||
| 43 | */ | ||
| 44 | #define IMEMC_PHYS 0x58000000 | ||
| 45 | #define IMEMC_VIRT 0xfe000000 | ||
| 46 | #define IMEMC_SIZE 0x00100000 | ||
| 47 | |||
| 48 | #endif /* __ASM_MACH_ADDR_MAP_H */ | ||
diff --git a/arch/arm/mach-pxa/include/mach/balloon3.h b/arch/arm/mach-pxa/include/mach/balloon3.h index 561562b4360b..7074e76146c9 100644 --- a/arch/arm/mach-pxa/include/mach/balloon3.h +++ b/arch/arm/mach-pxa/include/mach/balloon3.h | |||
| @@ -26,6 +26,8 @@ enum balloon3_features { | |||
| 26 | #define BALLOON3_FPGA_VIRT (0xf1000000) /* as per balloon2 */ | 26 | #define BALLOON3_FPGA_VIRT (0xf1000000) /* as per balloon2 */ |
| 27 | #define BALLOON3_FPGA_LENGTH 0x01000000 | 27 | #define BALLOON3_FPGA_LENGTH 0x01000000 |
| 28 | 28 | ||
| 29 | #define BALLOON3_FPGA_SETnCLR (0x1000) | ||
| 30 | |||
| 29 | /* FPGA / CPLD registers for CF socket */ | 31 | /* FPGA / CPLD registers for CF socket */ |
| 30 | #define BALLOON3_CF_STATUS_REG (BALLOON3_FPGA_VIRT + 0x00e00008) | 32 | #define BALLOON3_CF_STATUS_REG (BALLOON3_FPGA_VIRT + 0x00e00008) |
| 31 | #define BALLOON3_CF_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00008) | 33 | #define BALLOON3_CF_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00008) |
| @@ -35,7 +37,7 @@ enum balloon3_features { | |||
| 35 | #define BALLOON3_NAND_BASE (PXA_CS4_PHYS + 0x00e00000) | 37 | #define BALLOON3_NAND_BASE (PXA_CS4_PHYS + 0x00e00000) |
| 36 | #define BALLOON3_NAND_IO_REG (BALLOON3_FPGA_VIRT + 0x00e00000) | 38 | #define BALLOON3_NAND_IO_REG (BALLOON3_FPGA_VIRT + 0x00e00000) |
| 37 | #define BALLOON3_NAND_CONTROL2_REG (BALLOON3_FPGA_VIRT + 0x00e00010) | 39 | #define BALLOON3_NAND_CONTROL2_REG (BALLOON3_FPGA_VIRT + 0x00e00010) |
| 38 | #define BALLOON3_NAND_STAT_REG (BALLOON3_FPGA_VIRT + 0x00e00010) | 40 | #define BALLOON3_NAND_STAT_REG (BALLOON3_FPGA_VIRT + 0x00e00014) |
| 39 | #define BALLOON3_NAND_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00014) | 41 | #define BALLOON3_NAND_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00014) |
| 40 | 42 | ||
| 41 | /* fpga/cpld interrupt control register */ | 43 | /* fpga/cpld interrupt control register */ |
| @@ -174,7 +176,7 @@ enum balloon3_features { | |||
| 174 | #define BALLOON3_CODEC_IRQ IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ) | 176 | #define BALLOON3_CODEC_IRQ IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ) |
| 175 | #define BALLOON3_S0_CD_IRQ IRQ_GPIO(BALLOON3_GPIO_S0_CD) | 177 | #define BALLOON3_S0_CD_IRQ IRQ_GPIO(BALLOON3_GPIO_S0_CD) |
| 176 | 178 | ||
| 177 | #define BALLOON3_NR_IRQS (IRQ_BOARD_START + 4) | 179 | #define BALLOON3_NR_IRQS (IRQ_BOARD_START + 16) |
| 178 | 180 | ||
| 179 | extern int balloon3_has(enum balloon3_features feature); | 181 | extern int balloon3_has(enum balloon3_features feature); |
| 180 | 182 | ||
diff --git a/arch/arm/mach-pxa/include/mach/colibri.h b/arch/arm/mach-pxa/include/mach/colibri.h index 58dada11054f..388a96f1ef93 100644 --- a/arch/arm/mach-pxa/include/mach/colibri.h +++ b/arch/arm/mach-pxa/include/mach/colibri.h | |||
| @@ -9,14 +9,14 @@ | |||
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | enum { | 11 | enum { |
| 12 | COLIBRI_PXA270_EVALBOARD = 0, | 12 | COLIBRI_EVALBOARD = 0, |
| 13 | COLIBRI_PXA270_INCOME, | 13 | COLIBRI_PXA270_INCOME, |
| 14 | }; | 14 | }; |
| 15 | 15 | ||
| 16 | #if defined(CONFIG_MACH_COLIBRI_PXA270_EVALBOARD) | 16 | #if defined(CONFIG_MACH_COLIBRI_EVALBOARD) |
| 17 | extern void colibri_pxa270_evalboard_init(void); | 17 | extern void colibri_evalboard_init(void); |
| 18 | #else | 18 | #else |
| 19 | static inline void colibri_pxa270_evalboard_init(void) {} | 19 | static inline void colibri_evalboard_init(void) {} |
| 20 | #endif | 20 | #endif |
| 21 | 21 | ||
| 22 | #if defined(CONFIG_MACH_COLIBRI_PXA270_INCOME) | 22 | #if defined(CONFIG_MACH_COLIBRI_PXA270_INCOME) |
| @@ -59,5 +59,11 @@ static inline void colibri_pxa3xx_init_nand(void) {} | |||
| 59 | #define GPIO0_COLIBRI_PXA270_SD_DETECT 0 | 59 | #define GPIO0_COLIBRI_PXA270_SD_DETECT 0 |
| 60 | #define GPIO113_COLIBRI_PXA270_TS_IRQ 113 | 60 | #define GPIO113_COLIBRI_PXA270_TS_IRQ 113 |
| 61 | 61 | ||
| 62 | /* GPIO definitions for Colibri PXA300/310 */ | ||
| 63 | #define GPIO39_COLIBRI_PXA300_SD_DETECT 39 | ||
| 64 | |||
| 65 | /* GPIO definitions for Colibri PXA320 */ | ||
| 66 | #define GPIO28_COLIBRI_PXA320_SD_DETECT 28 | ||
| 67 | |||
| 62 | #endif /* _COLIBRI_H_ */ | 68 | #endif /* _COLIBRI_H_ */ |
| 63 | 69 | ||
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h index 814f1458a06a..6957ba56025b 100644 --- a/arch/arm/mach-pxa/include/mach/hardware.h +++ b/arch/arm/mach-pxa/include/mach/hardware.h | |||
| @@ -13,6 +13,8 @@ | |||
| 13 | #ifndef __ASM_ARCH_HARDWARE_H | 13 | #ifndef __ASM_ARCH_HARDWARE_H |
| 14 | #define __ASM_ARCH_HARDWARE_H | 14 | #define __ASM_ARCH_HARDWARE_H |
| 15 | 15 | ||
| 16 | #include <mach/addr-map.h> | ||
| 17 | |||
| 16 | /* | 18 | /* |
| 17 | * Workarounds for at least 2 errata so far require this. | 19 | * Workarounds for at least 2 errata so far require this. |
| 18 | * The mapping is set in mach-pxa/generic.c. | 20 | * The mapping is set in mach-pxa/generic.c. |
| @@ -193,14 +195,15 @@ | |||
| 193 | #define __cpu_is_pxa935(id) (0) | 195 | #define __cpu_is_pxa935(id) (0) |
| 194 | #endif | 196 | #endif |
| 195 | 197 | ||
| 196 | #ifdef CONFIG_CPU_PXA950 | 198 | #ifdef CONFIG_CPU_PXA955 |
| 197 | #define __cpu_is_pxa950(id) \ | 199 | #define __cpu_is_pxa955(id) \ |
| 198 | ({ \ | 200 | ({ \ |
| 199 | unsigned int _id = (id) >> 4 & 0xfff; \ | 201 | unsigned int _id = (id) >> 4 & 0xfff; \ |
| 200 | _id == 0x697; \ | 202 | _id == 0x581 || _id == 0xc08 \ |
| 201 | }) | 203 | || _id == 0xb76; \ |
| 204 | }) | ||
| 202 | #else | 205 | #else |
| 203 | #define __cpu_is_pxa950(id) (0) | 206 | #define __cpu_is_pxa955(id) (0) |
| 204 | #endif | 207 | #endif |
| 205 | 208 | ||
| 206 | #define cpu_is_pxa210() \ | 209 | #define cpu_is_pxa210() \ |
| @@ -253,16 +256,15 @@ | |||
| 253 | __cpu_is_pxa935(read_cpuid_id()); \ | 256 | __cpu_is_pxa935(read_cpuid_id()); \ |
| 254 | }) | 257 | }) |
| 255 | 258 | ||
| 256 | #define cpu_is_pxa950() \ | 259 | #define cpu_is_pxa955() \ |
| 257 | ({ \ | 260 | ({ \ |
| 258 | __cpu_is_pxa950(read_cpuid_id()); \ | 261 | __cpu_is_pxa955(read_cpuid_id()); \ |
| 259 | }) | 262 | }) |
| 260 | 263 | ||
| 261 | 264 | ||
| 262 | /* | 265 | /* |
| 263 | * CPUID Core Generation Bit | 266 | * CPUID Core Generation Bit |
| 264 | * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x | 267 | * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x |
| 265 | * == 0x3 for pxa300/pxa310/pxa320 | ||
| 266 | */ | 268 | */ |
| 267 | #if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x) | 269 | #if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x) |
| 268 | #define __cpu_is_pxa2xx(id) \ | 270 | #define __cpu_is_pxa2xx(id) \ |
| @@ -277,8 +279,10 @@ | |||
| 277 | #ifdef CONFIG_PXA3xx | 279 | #ifdef CONFIG_PXA3xx |
| 278 | #define __cpu_is_pxa3xx(id) \ | 280 | #define __cpu_is_pxa3xx(id) \ |
| 279 | ({ \ | 281 | ({ \ |
| 280 | unsigned int _id = (id) >> 13 & 0x7; \ | 282 | __cpu_is_pxa300(id) \ |
| 281 | _id == 0x3; \ | 283 | || __cpu_is_pxa310(id) \ |
| 284 | || __cpu_is_pxa320(id) \ | ||
| 285 | || __cpu_is_pxa93x(id); \ | ||
| 282 | }) | 286 | }) |
| 283 | #else | 287 | #else |
| 284 | #define __cpu_is_pxa3xx(id) (0) | 288 | #define __cpu_is_pxa3xx(id) (0) |
| @@ -287,13 +291,22 @@ | |||
| 287 | #if defined(CONFIG_CPU_PXA930) || defined(CONFIG_CPU_PXA935) | 291 | #if defined(CONFIG_CPU_PXA930) || defined(CONFIG_CPU_PXA935) |
| 288 | #define __cpu_is_pxa93x(id) \ | 292 | #define __cpu_is_pxa93x(id) \ |
| 289 | ({ \ | 293 | ({ \ |
| 290 | unsigned int _id = (id) >> 4 & 0xfff; \ | 294 | __cpu_is_pxa930(id) \ |
| 291 | _id == 0x683 || _id == 0x693; \ | 295 | || __cpu_is_pxa935(id); \ |
| 292 | }) | 296 | }) |
| 293 | #else | 297 | #else |
| 294 | #define __cpu_is_pxa93x(id) (0) | 298 | #define __cpu_is_pxa93x(id) (0) |
| 295 | #endif | 299 | #endif |
| 296 | 300 | ||
| 301 | #ifdef CONFIG_PXA95x | ||
| 302 | #define __cpu_is_pxa95x(id) \ | ||
| 303 | ({ \ | ||
| 304 | __cpu_is_pxa955(id); \ | ||
| 305 | }) | ||
| 306 | #else | ||
| 307 | #define __cpu_is_pxa95x(id) (0) | ||
| 308 | #endif | ||
| 309 | |||
| 297 | #define cpu_is_pxa2xx() \ | 310 | #define cpu_is_pxa2xx() \ |
| 298 | ({ \ | 311 | ({ \ |
| 299 | __cpu_is_pxa2xx(read_cpuid_id()); \ | 312 | __cpu_is_pxa2xx(read_cpuid_id()); \ |
| @@ -308,6 +321,12 @@ | |||
| 308 | ({ \ | 321 | ({ \ |
| 309 | __cpu_is_pxa93x(read_cpuid_id()); \ | 322 | __cpu_is_pxa93x(read_cpuid_id()); \ |
| 310 | }) | 323 | }) |
| 324 | |||
| 325 | #define cpu_is_pxa95x() \ | ||
| 326 | ({ \ | ||
| 327 | __cpu_is_pxa95x(read_cpuid_id()); \ | ||
| 328 | }) | ||
| 329 | |||
| 311 | /* | 330 | /* |
| 312 | * return current memory and LCD clock frequency in units of 10kHz | 331 | * return current memory and LCD clock frequency in units of 10kHz |
| 313 | */ | 332 | */ |
diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h index d372caa75dc7..a4285fc00878 100644 --- a/arch/arm/mach-pxa/include/mach/irqs.h +++ b/arch/arm/mach-pxa/include/mach/irqs.h | |||
| @@ -21,16 +21,14 @@ | |||
| 21 | 21 | ||
| 22 | #define PXA_IRQ(x) (PXA_ISA_IRQ_NUM + (x)) | 22 | #define PXA_IRQ(x) (PXA_ISA_IRQ_NUM + (x)) |
| 23 | 23 | ||
| 24 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) | ||
| 25 | #define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */ | 24 | #define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */ |
| 26 | #define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */ | 25 | #define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */ |
| 27 | #define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI) */ | 26 | #define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI,PXA27x) */ |
| 28 | #define IRQ_USBH1 PXA_IRQ(3) /* USB Host interrupt 2 (non-OHCI) */ | 27 | #define IRQ_USBH1 PXA_IRQ(3) /* USB Host interrupt 2 (non-OHCI,PXA27x) */ |
| 29 | #define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */ | 28 | #define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */ |
| 30 | #define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt */ | 29 | #define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt (PXA27x) */ |
| 30 | #define IRQ_ACIPC0 PXA_IRQ(5) /* AP-CP Communication (PXA930) */ | ||
| 31 | #define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */ | 31 | #define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */ |
| 32 | #endif | ||
| 33 | |||
| 34 | #define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */ | 32 | #define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */ |
| 35 | #define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */ | 33 | #define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */ |
| 36 | #define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */ | 34 | #define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */ |
| @@ -38,7 +36,8 @@ | |||
| 38 | #define IRQ_GPIO_2_x PXA_IRQ(10) /* GPIO[2-x] Edge Detect */ | 36 | #define IRQ_GPIO_2_x PXA_IRQ(10) /* GPIO[2-x] Edge Detect */ |
| 39 | #define IRQ_USB PXA_IRQ(11) /* USB Service */ | 37 | #define IRQ_USB PXA_IRQ(11) /* USB Service */ |
| 40 | #define IRQ_PMU PXA_IRQ(12) /* Performance Monitoring Unit */ | 38 | #define IRQ_PMU PXA_IRQ(12) /* Performance Monitoring Unit */ |
| 41 | #define IRQ_I2S PXA_IRQ(13) /* I2S Interrupt */ | 39 | #define IRQ_I2S PXA_IRQ(13) /* I2S Interrupt (PXA27x) */ |
| 40 | #define IRQ_SSP4 PXA_IRQ(13) /* SSP4 service request (PXA3xx) */ | ||
| 42 | #define IRQ_AC97 PXA_IRQ(14) /* AC97 Interrupt */ | 41 | #define IRQ_AC97 PXA_IRQ(14) /* AC97 Interrupt */ |
| 43 | #define IRQ_ASSP PXA_IRQ(15) /* Audio SSP Service Request (PXA25x) */ | 42 | #define IRQ_ASSP PXA_IRQ(15) /* Audio SSP Service Request (PXA25x) */ |
| 44 | #define IRQ_USIM PXA_IRQ(15) /* Smart Card interface interrupt (PXA27x) */ | 43 | #define IRQ_USIM PXA_IRQ(15) /* Smart Card interface interrupt (PXA27x) */ |
| @@ -47,6 +46,7 @@ | |||
| 47 | #define IRQ_LCD PXA_IRQ(17) /* LCD Controller Service Request */ | 46 | #define IRQ_LCD PXA_IRQ(17) /* LCD Controller Service Request */ |
| 48 | #define IRQ_I2C PXA_IRQ(18) /* I2C Service Request */ | 47 | #define IRQ_I2C PXA_IRQ(18) /* I2C Service Request */ |
| 49 | #define IRQ_ICP PXA_IRQ(19) /* ICP Transmit/Receive/Error */ | 48 | #define IRQ_ICP PXA_IRQ(19) /* ICP Transmit/Receive/Error */ |
| 49 | #define IRQ_ACIPC2 PXA_IRQ(19) /* AP-CP Communication (PXA930) */ | ||
| 50 | #define IRQ_STUART PXA_IRQ(20) /* STUART Transmit/Receive/Error */ | 50 | #define IRQ_STUART PXA_IRQ(20) /* STUART Transmit/Receive/Error */ |
| 51 | #define IRQ_BTUART PXA_IRQ(21) /* BTUART Transmit/Receive/Error */ | 51 | #define IRQ_BTUART PXA_IRQ(21) /* BTUART Transmit/Receive/Error */ |
| 52 | #define IRQ_FFUART PXA_IRQ(22) /* FFUART Transmit/Receive/Error*/ | 52 | #define IRQ_FFUART PXA_IRQ(22) /* FFUART Transmit/Receive/Error*/ |
| @@ -60,19 +60,17 @@ | |||
| 60 | #define IRQ_RTC1Hz PXA_IRQ(30) /* RTC HZ Clock Tick */ | 60 | #define IRQ_RTC1Hz PXA_IRQ(30) /* RTC HZ Clock Tick */ |
| 61 | #define IRQ_RTCAlrm PXA_IRQ(31) /* RTC Alarm */ | 61 | #define IRQ_RTCAlrm PXA_IRQ(31) /* RTC Alarm */ |
| 62 | 62 | ||
| 63 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) | ||
| 64 | #define IRQ_TPM PXA_IRQ(32) /* TPM interrupt */ | 63 | #define IRQ_TPM PXA_IRQ(32) /* TPM interrupt */ |
| 65 | #define IRQ_CAMERA PXA_IRQ(33) /* Camera Interface */ | 64 | #define IRQ_CAMERA PXA_IRQ(33) /* Camera Interface */ |
| 66 | #endif | ||
| 67 | |||
| 68 | #ifdef CONFIG_PXA3xx | ||
| 69 | #define IRQ_SSP4 PXA_IRQ(13) /* SSP4 service request */ | ||
| 70 | #define IRQ_CIR PXA_IRQ(34) /* Consumer IR */ | 65 | #define IRQ_CIR PXA_IRQ(34) /* Consumer IR */ |
| 71 | #define IRQ_COMM_WDT PXA_IRQ(35) /* Comm WDT interrupt */ | 66 | #define IRQ_COMM_WDT PXA_IRQ(35) /* Comm WDT interrupt */ |
| 72 | #define IRQ_TSI PXA_IRQ(36) /* Touch Screen Interface (PXA320) */ | 67 | #define IRQ_TSI PXA_IRQ(36) /* Touch Screen Interface (PXA320) */ |
| 68 | #define IRQ_ENHROT PXA_IRQ(37) /* Enhanced Rotary (PXA930) */ | ||
| 73 | #define IRQ_USIM2 PXA_IRQ(38) /* USIM2 Controller */ | 69 | #define IRQ_USIM2 PXA_IRQ(38) /* USIM2 Controller */ |
| 74 | #define IRQ_GCU PXA_IRQ(39) /* Graphics Controller */ | 70 | #define IRQ_GCU PXA_IRQ(39) /* Graphics Controller (PXA3xx) */ |
| 71 | #define IRQ_ACIPC1 PXA_IRQ(40) /* AP-CP Communication (PXA930) */ | ||
| 75 | #define IRQ_MMC2 PXA_IRQ(41) /* MMC2 Controller */ | 72 | #define IRQ_MMC2 PXA_IRQ(41) /* MMC2 Controller */ |
| 73 | #define IRQ_TRKBALL PXA_IRQ(43) /* Track Ball (PXA930) */ | ||
| 76 | #define IRQ_1WIRE PXA_IRQ(44) /* 1-Wire Controller */ | 74 | #define IRQ_1WIRE PXA_IRQ(44) /* 1-Wire Controller */ |
| 77 | #define IRQ_NAND PXA_IRQ(45) /* NAND Controller */ | 75 | #define IRQ_NAND PXA_IRQ(45) /* NAND Controller */ |
| 78 | #define IRQ_USB2 PXA_IRQ(46) /* USB 2.0 Device Controller */ | 76 | #define IRQ_USB2 PXA_IRQ(46) /* USB 2.0 Device Controller */ |
| @@ -80,30 +78,14 @@ | |||
| 80 | #define IRQ_WAKEUP1 PXA_IRQ(50) /* EXT_WAKEUP1 */ | 78 | #define IRQ_WAKEUP1 PXA_IRQ(50) /* EXT_WAKEUP1 */ |
| 81 | #define IRQ_DMEMC PXA_IRQ(51) /* Dynamic Memory Controller */ | 79 | #define IRQ_DMEMC PXA_IRQ(51) /* Dynamic Memory Controller */ |
| 82 | #define IRQ_MMC3 PXA_IRQ(55) /* MMC3 Controller (PXA310) */ | 80 | #define IRQ_MMC3 PXA_IRQ(55) /* MMC3 Controller (PXA310) */ |
| 83 | #endif | ||
| 84 | 81 | ||
| 85 | #ifdef CONFIG_CPU_PXA935 | ||
| 86 | #define IRQ_U2O PXA_IRQ(64) /* USB OTG 2.0 Controller (PXA935) */ | 82 | #define IRQ_U2O PXA_IRQ(64) /* USB OTG 2.0 Controller (PXA935) */ |
| 87 | #define IRQ_U2H PXA_IRQ(65) /* USB Host 2.0 Controller (PXA935) */ | 83 | #define IRQ_U2H PXA_IRQ(65) /* USB Host 2.0 Controller (PXA935) */ |
| 88 | 84 | #define IRQ_PXA935_MMC0 PXA_IRQ(72) /* MMC0 Controller (PXA935) */ | |
| 89 | #define IRQ_MMC3_PXA935 PXA_IRQ(72) /* MMC3 Controller (PXA935) */ | 85 | #define IRQ_PXA935_MMC1 PXA_IRQ(73) /* MMC1 Controller (PXA935) */ |
| 90 | #define IRQ_MMC4_PXA935 PXA_IRQ(73) /* MMC4 Controller (PXA935) */ | 86 | #define IRQ_PXA935_MMC2 PXA_IRQ(74) /* MMC2 Controller (PXA935) */ |
| 91 | #define IRQ_MMC5_PXA935 PXA_IRQ(74) /* MMC5 Controller (PXA935) */ | 87 | #define IRQ_PXA955_MMC3 PXA_IRQ(75) /* MMC3 Controller (PXA955) */ |
| 92 | |||
| 93 | #define IRQ_U2P PXA_IRQ(93) /* USB PHY D+/D- Lines (PXA935) */ | 88 | #define IRQ_U2P PXA_IRQ(93) /* USB PHY D+/D- Lines (PXA935) */ |
| 94 | #endif | ||
| 95 | |||
| 96 | #ifdef CONFIG_CPU_PXA930 | ||
| 97 | #define IRQ_ENHROT PXA_IRQ(37) /* Enhanced Rotary (PXA930) */ | ||
| 98 | #define IRQ_ACIPC0 PXA_IRQ(5) | ||
| 99 | #define IRQ_ACIPC1 PXA_IRQ(40) | ||
| 100 | #define IRQ_ACIPC2 PXA_IRQ(19) | ||
| 101 | #define IRQ_TRKBALL PXA_IRQ(43) /* Track Ball */ | ||
| 102 | #endif | ||
| 103 | |||
| 104 | #ifdef CONFIG_CPU_PXA950 | ||
| 105 | #define IRQ_GC500 PXA_IRQ(70) /* Graphics Controller (PXA950) */ | ||
| 106 | #endif | ||
| 107 | 89 | ||
| 108 | #define PXA_GPIO_IRQ_BASE PXA_IRQ(96) | 90 | #define PXA_GPIO_IRQ_BASE PXA_IRQ(96) |
| 109 | #define PXA_GPIO_IRQ_NUM (192) | 91 | #define PXA_GPIO_IRQ_NUM (192) |
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h index 4fcddd9cab76..ee6ced1cea7f 100644 --- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h | |||
| @@ -17,72 +17,6 @@ | |||
| 17 | #include <mach/hardware.h> | 17 | #include <mach/hardware.h> |
| 18 | 18 | ||
| 19 | /* | 19 | /* |
| 20 | * PXA Chip selects | ||
| 21 | */ | ||
| 22 | |||
| 23 | #define PXA_CS0_PHYS 0x00000000 | ||
| 24 | #define PXA_CS1_PHYS 0x04000000 | ||
| 25 | #define PXA_CS2_PHYS 0x08000000 | ||
| 26 | #define PXA_CS3_PHYS 0x0C000000 | ||
| 27 | #define PXA_CS4_PHYS 0x10000000 | ||
| 28 | #define PXA_CS5_PHYS 0x14000000 | ||
| 29 | |||
| 30 | /* | ||
| 31 | * Memory controller | ||
| 32 | */ | ||
| 33 | |||
| 34 | #define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */ | ||
| 35 | #define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */ | ||
| 36 | #define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */ | ||
| 37 | #define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */ | ||
| 38 | #define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */ | ||
| 39 | #define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ | ||
| 40 | #define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */ | ||
| 41 | #define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */ | ||
| 42 | #define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */ | ||
| 43 | #define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */ | ||
| 44 | #define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */ | ||
| 45 | #define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */ | ||
| 46 | #define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */ | ||
| 47 | #define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */ | ||
| 48 | #define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */ | ||
| 49 | #define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */ | ||
| 50 | #define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ | ||
| 51 | |||
| 52 | /* | ||
| 53 | * More handy macros for PCMCIA | ||
| 54 | * | ||
| 55 | * Arg is socket number | ||
| 56 | */ | ||
| 57 | #define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */ | ||
| 58 | #define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */ | ||
| 59 | #define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */ | ||
| 60 | |||
| 61 | /* MECR register defines */ | ||
| 62 | #define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */ | ||
| 63 | #define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */ | ||
| 64 | |||
| 65 | #define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */ | ||
| 66 | #define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */ | ||
| 67 | #define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */ | ||
| 68 | #define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */ | ||
| 69 | |||
| 70 | #define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ | ||
| 71 | #define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ | ||
| 72 | #define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ | ||
| 73 | #define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */ | ||
| 74 | #define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */ | ||
| 75 | #define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */ | ||
| 76 | #define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */ | ||
| 77 | #define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */ | ||
| 78 | #define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */ | ||
| 79 | #define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */ | ||
| 80 | #define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */ | ||
| 81 | #define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */ | ||
| 82 | #define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ | ||
| 83 | #define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ | ||
| 84 | |||
| 85 | /* | ||
| 86 | * Power Manager | 20 | * Power Manager |
| 87 | */ | 21 | */ |
| 88 | 22 | ||
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx_spi.h b/arch/arm/mach-pxa/include/mach/pxa2xx_spi.h deleted file mode 100644 index b87cecd9bbdc..000000000000 --- a/arch/arm/mach-pxa/include/mach/pxa2xx_spi.h +++ /dev/null | |||
| @@ -1,47 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef PXA2XX_SPI_H_ | ||
| 20 | #define PXA2XX_SPI_H_ | ||
| 21 | |||
| 22 | #define PXA2XX_CS_ASSERT (0x01) | ||
| 23 | #define PXA2XX_CS_DEASSERT (0x02) | ||
| 24 | |||
| 25 | /* device.platform_data for SSP controller devices */ | ||
| 26 | struct pxa2xx_spi_master { | ||
| 27 | u32 clock_enable; | ||
| 28 | u16 num_chipselect; | ||
| 29 | u8 enable_dma; | ||
| 30 | }; | ||
| 31 | |||
| 32 | /* spi_board_info.controller_data for SPI slave devices, | ||
| 33 | * copied to spi_device.platform_data ... mostly for dma tuning | ||
| 34 | */ | ||
| 35 | struct pxa2xx_spi_chip { | ||
| 36 | u8 tx_threshold; | ||
| 37 | u8 rx_threshold; | ||
| 38 | u8 dma_burst_size; | ||
| 39 | u32 timeout; | ||
| 40 | u8 enable_loopback; | ||
| 41 | int gpio_cs; | ||
| 42 | void (*cs_control)(u32 command); | ||
| 43 | }; | ||
| 44 | |||
| 45 | extern void pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info); | ||
| 46 | |||
| 47 | #endif /*PXA2XX_SPI_H_*/ | ||
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h index e91d63cfe811..e4fb4668c26e 100644 --- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h | |||
| @@ -16,15 +16,6 @@ | |||
| 16 | #include <mach/hardware.h> | 16 | #include <mach/hardware.h> |
| 17 | 17 | ||
| 18 | /* | 18 | /* |
| 19 | * Static Chip Selects | ||
| 20 | */ | ||
| 21 | |||
| 22 | #define PXA300_CS0_PHYS (0x00000000) /* PXA300/PXA310 _only_ */ | ||
| 23 | #define PXA300_CS1_PHYS (0x30000000) /* PXA300/PXA310 _only_ */ | ||
| 24 | #define PXA3xx_CS2_PHYS (0x10000000) | ||
| 25 | #define PXA3xx_CS3_PHYS (0x14000000) | ||
| 26 | |||
| 27 | /* | ||
| 28 | * Oscillator Configuration Register (OSCC) | 19 | * Oscillator Configuration Register (OSCC) |
| 29 | */ | 20 | */ |
| 30 | #define OSCC __REG(0x41350000) /* Oscillator Configuration Register */ | 21 | #define OSCC __REG(0x41350000) /* Oscillator Configuration Register */ |
diff --git a/arch/arm/mach-pxa/include/mach/regs-intc.h b/arch/arm/mach-pxa/include/mach/regs-intc.h index 68464ce1c1ea..662288eb6f95 100644 --- a/arch/arm/mach-pxa/include/mach/regs-intc.h +++ b/arch/arm/mach-pxa/include/mach/regs-intc.h | |||
| @@ -27,8 +27,4 @@ | |||
| 27 | #define ICFP3 __REG(0x40D0013C) /* Interrupt Controller FIQ Pending Register 3 */ | 27 | #define ICFP3 __REG(0x40D0013C) /* Interrupt Controller FIQ Pending Register 3 */ |
| 28 | #define ICPR3 __REG(0x40D00140) /* Interrupt Controller Pending Register 3 */ | 28 | #define ICPR3 __REG(0x40D00140) /* Interrupt Controller Pending Register 3 */ |
| 29 | 29 | ||
| 30 | #define IPR(x) __REG(0x40D0001C + (x < 32 ? (x << 2) \ | ||
| 31 | : (x < 64 ? (0x94 + ((x - 32) << 2)) \ | ||
| 32 | : (0x128 + ((x - 64) << 2))))) | ||
| 33 | |||
| 34 | #endif /* __ASM_MACH_REGS_INTC_H */ | 30 | #endif /* __ASM_MACH_REGS_INTC_H */ |
diff --git a/arch/arm/mach-pxa/include/mach/smemc.h b/arch/arm/mach-pxa/include/mach/smemc.h new file mode 100644 index 000000000000..654adc90c9a0 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/smemc.h | |||
| @@ -0,0 +1,74 @@ | |||
| 1 | /* | ||
| 2 | * Static memory controller register definitions for PXA CPUs | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __SMEMC_REGS_H | ||
| 12 | #define __SMEMC_REGS_H | ||
| 13 | |||
| 14 | #define PXA2XX_SMEMC_BASE 0x48000000 | ||
| 15 | #define PXA3XX_SMEMC_BASE 0x4a000000 | ||
| 16 | #define SMEMC_VIRT 0xf6000000 | ||
| 17 | |||
| 18 | #define MDCNFG (SMEMC_VIRT + 0x00) /* SDRAM Configuration Register 0 */ | ||
| 19 | #define MDREFR (SMEMC_VIRT + 0x04) /* SDRAM Refresh Control Register */ | ||
| 20 | #define MSC0 (SMEMC_VIRT + 0x08) /* Static Memory Control Register 0 */ | ||
| 21 | #define MSC1 (SMEMC_VIRT + 0x0C) /* Static Memory Control Register 1 */ | ||
| 22 | #define MSC2 (SMEMC_VIRT + 0x10) /* Static Memory Control Register 2 */ | ||
| 23 | #define MECR (SMEMC_VIRT + 0x14) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ | ||
| 24 | #define SXLCR (SMEMC_VIRT + 0x18) /* LCR value to be written to SDRAM-Timing Synchronous Flash */ | ||
| 25 | #define SXCNFG (SMEMC_VIRT + 0x1C) /* Synchronous Static Memory Control Register */ | ||
| 26 | #define SXMRS (SMEMC_VIRT + 0x24) /* MRS value to be written to Synchronous Flash or SMROM */ | ||
| 27 | #define MCMEM0 (SMEMC_VIRT + 0x28) /* Card interface Common Memory Space Socket 0 Timing */ | ||
| 28 | #define MCMEM1 (SMEMC_VIRT + 0x2C) /* Card interface Common Memory Space Socket 1 Timing */ | ||
| 29 | #define MCATT0 (SMEMC_VIRT + 0x30) /* Card interface Attribute Space Socket 0 Timing Configuration */ | ||
| 30 | #define MCATT1 (SMEMC_VIRT + 0x34) /* Card interface Attribute Space Socket 1 Timing Configuration */ | ||
| 31 | #define MCIO0 (SMEMC_VIRT + 0x38) /* Card interface I/O Space Socket 0 Timing Configuration */ | ||
| 32 | #define MCIO1 (SMEMC_VIRT + 0x3C) /* Card interface I/O Space Socket 1 Timing Configuration */ | ||
| 33 | #define MDMRS (SMEMC_VIRT + 0x40) /* MRS value to be written to SDRAM */ | ||
| 34 | #define BOOT_DEF (SMEMC_VIRT + 0x44) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ | ||
| 35 | #define MEMCLKCFG (SMEMC_VIRT + 0x68) /* Clock Configuration */ | ||
| 36 | #define CSADRCFG0 (SMEMC_VIRT + 0x80) /* Address Configuration Register for CS0 */ | ||
| 37 | #define CSADRCFG1 (SMEMC_VIRT + 0x84) /* Address Configuration Register for CS1 */ | ||
| 38 | #define CSADRCFG2 (SMEMC_VIRT + 0x88) /* Address Configuration Register for CS2 */ | ||
| 39 | #define CSADRCFG3 (SMEMC_VIRT + 0x8C) /* Address Configuration Register for CS3 */ | ||
| 40 | |||
| 41 | /* | ||
| 42 | * More handy macros for PCMCIA | ||
| 43 | * | ||
| 44 | * Arg is socket number | ||
| 45 | */ | ||
| 46 | #define MCMEM(s) (SMEMC_VIRT + 0x28 + ((s)<<2)) /* Card interface Common Memory Space Socket s Timing */ | ||
| 47 | #define MCATT(s) (SMEMC_VIRT + 0x30 + ((s)<<2)) /* Card interface Attribute Space Socket s Timing Configuration */ | ||
| 48 | #define MCIO(s) (SMEMC_VIRT + 0x38 + ((s)<<2)) /* Card interface I/O Space Socket s Timing Configuration */ | ||
| 49 | |||
| 50 | /* MECR register defines */ | ||
| 51 | #define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */ | ||
| 52 | #define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */ | ||
| 53 | |||
| 54 | #define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */ | ||
| 55 | #define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */ | ||
| 56 | #define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */ | ||
| 57 | #define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */ | ||
| 58 | |||
| 59 | #define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ | ||
| 60 | #define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ | ||
| 61 | #define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ | ||
| 62 | #define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */ | ||
| 63 | #define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */ | ||
| 64 | #define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */ | ||
| 65 | #define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */ | ||
| 66 | #define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */ | ||
| 67 | #define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */ | ||
| 68 | #define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */ | ||
| 69 | #define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */ | ||
| 70 | #define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */ | ||
| 71 | #define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ | ||
| 72 | #define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ | ||
| 73 | |||
| 74 | #endif | ||
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index 1beb40f692fc..54e91c9e71c8 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c | |||
| @@ -16,20 +16,31 @@ | |||
| 16 | #include <linux/module.h> | 16 | #include <linux/module.h> |
| 17 | #include <linux/interrupt.h> | 17 | #include <linux/interrupt.h> |
| 18 | #include <linux/sysdev.h> | 18 | #include <linux/sysdev.h> |
| 19 | #include <linux/io.h> | ||
| 20 | #include <linux/irq.h> | ||
| 19 | 21 | ||
| 20 | #include <mach/hardware.h> | 22 | #include <mach/hardware.h> |
| 21 | #include <asm/irq.h> | 23 | #include <mach/irqs.h> |
| 22 | #include <asm/mach/irq.h> | ||
| 23 | #include <mach/gpio.h> | 24 | #include <mach/gpio.h> |
| 24 | #include <mach/regs-intc.h> | ||
| 25 | 25 | ||
| 26 | #include "generic.h" | 26 | #include "generic.h" |
| 27 | 27 | ||
| 28 | #define MAX_INTERNAL_IRQS 128 | 28 | #define IRQ_BASE (void __iomem *)io_p2v(0x40d00000) |
| 29 | |||
| 30 | #define ICIP (0x000) | ||
| 31 | #define ICMR (0x004) | ||
| 32 | #define ICLR (0x008) | ||
| 33 | #define ICFR (0x00c) | ||
| 34 | #define ICPR (0x010) | ||
| 35 | #define ICCR (0x014) | ||
| 36 | #define ICHP (0x018) | ||
| 37 | #define IPR(i) (((i) < 32) ? (0x01c + ((i) << 2)) : \ | ||
| 38 | ((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) : \ | ||
| 39 | (0x144 + (((i) - 64) << 2))) | ||
| 40 | #define IPR_VALID (1 << 31) | ||
| 41 | #define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f) | ||
| 29 | 42 | ||
| 30 | #define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f) | 43 | #define MAX_INTERNAL_IRQS 128 |
| 31 | #define _ICMR(n) (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICMR2 : &ICMR)) | ||
| 32 | #define _ICLR(n) (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICLR2 : &ICLR)) | ||
| 33 | 44 | ||
| 34 | /* | 45 | /* |
| 35 | * This is for peripheral IRQs internal to the PXA chip. | 46 | * This is for peripheral IRQs internal to the PXA chip. |
| @@ -37,14 +48,27 @@ | |||
| 37 | 48 | ||
| 38 | static int pxa_internal_irq_nr; | 49 | static int pxa_internal_irq_nr; |
| 39 | 50 | ||
| 51 | static inline int cpu_has_ipr(void) | ||
| 52 | { | ||
| 53 | return !cpu_is_pxa25x(); | ||
| 54 | } | ||
| 55 | |||
| 40 | static void pxa_mask_irq(unsigned int irq) | 56 | static void pxa_mask_irq(unsigned int irq) |
| 41 | { | 57 | { |
| 42 | _ICMR(irq) &= ~(1 << IRQ_BIT(irq)); | 58 | void __iomem *base = get_irq_chip_data(irq); |
| 59 | uint32_t icmr = __raw_readl(base + ICMR); | ||
| 60 | |||
| 61 | icmr &= ~(1 << IRQ_BIT(irq)); | ||
| 62 | __raw_writel(icmr, base + ICMR); | ||
| 43 | } | 63 | } |
| 44 | 64 | ||
| 45 | static void pxa_unmask_irq(unsigned int irq) | 65 | static void pxa_unmask_irq(unsigned int irq) |
| 46 | { | 66 | { |
| 47 | _ICMR(irq) |= 1 << IRQ_BIT(irq); | 67 | void __iomem *base = get_irq_chip_data(irq); |
| 68 | uint32_t icmr = __raw_readl(base + ICMR); | ||
| 69 | |||
| 70 | icmr |= 1 << IRQ_BIT(irq); | ||
| 71 | __raw_writel(icmr, base + ICMR); | ||
| 48 | } | 72 | } |
| 49 | 73 | ||
| 50 | static struct irq_chip pxa_internal_irq_chip = { | 74 | static struct irq_chip pxa_internal_irq_chip = { |
| @@ -86,12 +110,16 @@ static void pxa_ack_low_gpio(unsigned int irq) | |||
| 86 | 110 | ||
| 87 | static void pxa_mask_low_gpio(unsigned int irq) | 111 | static void pxa_mask_low_gpio(unsigned int irq) |
| 88 | { | 112 | { |
| 89 | ICMR &= ~(1 << (irq - PXA_IRQ(0))); | 113 | struct irq_desc *desc = irq_to_desc(irq); |
| 114 | |||
| 115 | desc->chip->mask(irq); | ||
| 90 | } | 116 | } |
| 91 | 117 | ||
| 92 | static void pxa_unmask_low_gpio(unsigned int irq) | 118 | static void pxa_unmask_low_gpio(unsigned int irq) |
| 93 | { | 119 | { |
| 94 | ICMR |= 1 << (irq - PXA_IRQ(0)); | 120 | struct irq_desc *desc = irq_to_desc(irq); |
| 121 | |||
| 122 | desc->chip->unmask(irq); | ||
| 95 | } | 123 | } |
| 96 | 124 | ||
| 97 | static struct irq_chip pxa_low_gpio_chip = { | 125 | static struct irq_chip pxa_low_gpio_chip = { |
| @@ -120,33 +148,45 @@ static void __init pxa_init_low_gpio_irq(set_wake_t fn) | |||
| 120 | pxa_low_gpio_chip.set_wake = fn; | 148 | pxa_low_gpio_chip.set_wake = fn; |
| 121 | } | 149 | } |
| 122 | 150 | ||
| 151 | static inline void __iomem *irq_base(int i) | ||
| 152 | { | ||
| 153 | static unsigned long phys_base[] = { | ||
| 154 | 0x40d00000, | ||
| 155 | 0x40d0009c, | ||
| 156 | 0x40d00130, | ||
| 157 | }; | ||
| 158 | |||
| 159 | return (void __iomem *)io_p2v(phys_base[i >> 5]); | ||
| 160 | } | ||
| 161 | |||
| 123 | void __init pxa_init_irq(int irq_nr, set_wake_t fn) | 162 | void __init pxa_init_irq(int irq_nr, set_wake_t fn) |
| 124 | { | 163 | { |
| 125 | int irq, i; | 164 | int irq, i, n; |
| 126 | 165 | ||
| 127 | BUG_ON(irq_nr > MAX_INTERNAL_IRQS); | 166 | BUG_ON(irq_nr > MAX_INTERNAL_IRQS); |
| 128 | 167 | ||
| 129 | pxa_internal_irq_nr = irq_nr; | 168 | pxa_internal_irq_nr = irq_nr; |
| 130 | 169 | ||
| 131 | for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq += 32) { | 170 | for (n = 0; n < irq_nr; n += 32) { |
| 132 | _ICMR(irq) = 0; /* disable all IRQs */ | 171 | void __iomem *base = irq_base(n); |
| 133 | _ICLR(irq) = 0; /* all IRQs are IRQ, not FIQ */ | 172 | |
| 134 | } | 173 | __raw_writel(0, base + ICMR); /* disable all IRQs */ |
| 135 | 174 | __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ | |
| 136 | /* initialize interrupt priority */ | 175 | for (i = n; (i < (n + 32)) && (i < irq_nr); i++) { |
| 137 | if (cpu_is_pxa27x() || cpu_is_pxa3xx()) { | 176 | /* initialize interrupt priority */ |
| 138 | for (i = 0; i < irq_nr; i++) | 177 | if (cpu_has_ipr()) |
| 139 | IPR(i) = i | (1 << 31); | 178 | __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i)); |
| 179 | |||
| 180 | irq = PXA_IRQ(i); | ||
| 181 | set_irq_chip(irq, &pxa_internal_irq_chip); | ||
| 182 | set_irq_chip_data(irq, base); | ||
| 183 | set_irq_handler(irq, handle_level_irq); | ||
| 184 | set_irq_flags(irq, IRQF_VALID); | ||
| 185 | } | ||
| 140 | } | 186 | } |
| 141 | 187 | ||
| 142 | /* only unmasked interrupts kick us out of idle */ | 188 | /* only unmasked interrupts kick us out of idle */ |
| 143 | ICCR = 1; | 189 | __raw_writel(1, irq_base(0) + ICCR); |
| 144 | |||
| 145 | for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq++) { | ||
| 146 | set_irq_chip(irq, &pxa_internal_irq_chip); | ||
| 147 | set_irq_handler(irq, handle_level_irq); | ||
| 148 | set_irq_flags(irq, IRQF_VALID); | ||
| 149 | } | ||
| 150 | 190 | ||
| 151 | pxa_internal_irq_chip.set_wake = fn; | 191 | pxa_internal_irq_chip.set_wake = fn; |
| 152 | pxa_init_low_gpio_irq(fn); | 192 | pxa_init_low_gpio_irq(fn); |
| @@ -158,16 +198,18 @@ static unsigned long saved_ipr[MAX_INTERNAL_IRQS]; | |||
| 158 | 198 | ||
| 159 | static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state) | 199 | static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state) |
| 160 | { | 200 | { |
| 161 | int i, irq = PXA_IRQ(0); | 201 | int i; |
| 162 | 202 | ||
| 163 | for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) { | 203 | for (i = 0; i < pxa_internal_irq_nr; i += 32) { |
| 164 | saved_icmr[i] = _ICMR(irq); | 204 | void __iomem *base = irq_base(i); |
| 165 | _ICMR(irq) = 0; | 205 | |
| 206 | saved_icmr[i] = __raw_readl(base + ICMR); | ||
| 207 | __raw_writel(0, base + ICMR); | ||
| 166 | } | 208 | } |
| 167 | 209 | ||
| 168 | if (cpu_is_pxa27x() || cpu_is_pxa3xx()) { | 210 | if (cpu_has_ipr()) { |
| 169 | for (i = 0; i < pxa_internal_irq_nr; i++) | 211 | for (i = 0; i < pxa_internal_irq_nr; i++) |
| 170 | saved_ipr[i] = IPR(i); | 212 | saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i)); |
| 171 | } | 213 | } |
| 172 | 214 | ||
| 173 | return 0; | 215 | return 0; |
| @@ -175,19 +217,20 @@ static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state) | |||
| 175 | 217 | ||
| 176 | static int pxa_irq_resume(struct sys_device *dev) | 218 | static int pxa_irq_resume(struct sys_device *dev) |
| 177 | { | 219 | { |
| 178 | int i, irq = PXA_IRQ(0); | 220 | int i; |
| 179 | 221 | ||
| 180 | if (cpu_is_pxa27x() || cpu_is_pxa3xx()) { | 222 | for (i = 0; i < pxa_internal_irq_nr; i += 32) { |
| 181 | for (i = 0; i < pxa_internal_irq_nr; i++) | 223 | void __iomem *base = irq_base(i); |
| 182 | IPR(i) = saved_ipr[i]; | ||
| 183 | } | ||
| 184 | 224 | ||
| 185 | for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) { | 225 | __raw_writel(saved_icmr[i], base + ICMR); |
| 186 | _ICMR(irq) = saved_icmr[i]; | 226 | __raw_writel(0, base + ICLR); |
| 187 | _ICLR(irq) = 0; | ||
| 188 | } | 227 | } |
| 189 | 228 | ||
| 190 | ICCR = 1; | 229 | if (!cpu_is_pxa25x()) |
| 230 | for (i = 0; i < pxa_internal_irq_nr; i++) | ||
| 231 | __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i)); | ||
| 232 | |||
| 233 | __raw_writel(1, IRQ_BASE + ICCR); | ||
| 191 | return 0; | 234 | return 0; |
| 192 | } | 235 | } |
| 193 | #else | 236 | #else |
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c index 41aa89e35772..ccb7bfad17ca 100644 --- a/arch/arm/mach-pxa/littleton.c +++ b/arch/arm/mach-pxa/littleton.c | |||
| @@ -22,6 +22,7 @@ | |||
| 22 | #include <linux/clk.h> | 22 | #include <linux/clk.h> |
| 23 | #include <linux/gpio.h> | 23 | #include <linux/gpio.h> |
| 24 | #include <linux/spi/spi.h> | 24 | #include <linux/spi/spi.h> |
| 25 | #include <linux/spi/pxa2xx_spi.h> | ||
| 25 | #include <linux/smc91x.h> | 26 | #include <linux/smc91x.h> |
| 26 | #include <linux/i2c.h> | 27 | #include <linux/i2c.h> |
| 27 | #include <linux/leds.h> | 28 | #include <linux/leds.h> |
| @@ -42,7 +43,6 @@ | |||
| 42 | #include <mach/pxa300.h> | 43 | #include <mach/pxa300.h> |
| 43 | #include <mach/pxafb.h> | 44 | #include <mach/pxafb.h> |
| 44 | #include <mach/mmc.h> | 45 | #include <mach/mmc.h> |
| 45 | #include <mach/pxa2xx_spi.h> | ||
| 46 | #include <plat/pxa27x_keypad.h> | 46 | #include <plat/pxa27x_keypad.h> |
| 47 | #include <mach/littleton.h> | 47 | #include <mach/littleton.h> |
| 48 | #include <plat/i2c.h> | 48 | #include <plat/i2c.h> |
| @@ -438,7 +438,7 @@ static void __init littleton_init(void) | |||
| 438 | 438 | ||
| 439 | MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleton)") | 439 | MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleton)") |
| 440 | .boot_params = 0xa0000100, | 440 | .boot_params = 0xa0000100, |
| 441 | .map_io = pxa_map_io, | 441 | .map_io = pxa3xx_map_io, |
| 442 | .nr_irqs = LITTLETON_NR_IRQS, | 442 | .nr_irqs = LITTLETON_NR_IRQS, |
| 443 | .init_irq = pxa3xx_init_irq, | 443 | .init_irq = pxa3xx_init_irq, |
| 444 | .timer = &pxa_timer, | 444 | .timer = &pxa_timer, |
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index 623af0232a54..8ab62a677807 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c | |||
| @@ -46,6 +46,7 @@ | |||
| 46 | #include <mach/mmc.h> | 46 | #include <mach/mmc.h> |
| 47 | #include <mach/irda.h> | 47 | #include <mach/irda.h> |
| 48 | #include <mach/ohci.h> | 48 | #include <mach/ohci.h> |
| 49 | #include <mach/smemc.h> | ||
| 49 | 50 | ||
| 50 | #include "generic.h" | 51 | #include "generic.h" |
| 51 | #include "devices.h" | 52 | #include "devices.h" |
| @@ -463,7 +464,7 @@ static void __init lpd270_init(void) | |||
| 463 | pxa_set_btuart_info(NULL); | 464 | pxa_set_btuart_info(NULL); |
| 464 | pxa_set_stuart_info(NULL); | 465 | pxa_set_stuart_info(NULL); |
| 465 | 466 | ||
| 466 | lpd270_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4; | 467 | lpd270_flash_data[0].width = (__raw_readl(BOOT_DEF) & 1) ? 2 : 4; |
| 467 | lpd270_flash_data[1].width = 4; | 468 | lpd270_flash_data[1].width = 4; |
| 468 | 469 | ||
| 469 | /* | 470 | /* |
| @@ -495,7 +496,7 @@ static struct map_desc lpd270_io_desc[] __initdata = { | |||
| 495 | 496 | ||
| 496 | static void __init lpd270_map_io(void) | 497 | static void __init lpd270_map_io(void) |
| 497 | { | 498 | { |
| 498 | pxa_map_io(); | 499 | pxa27x_map_io(); |
| 499 | iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc)); | 500 | iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc)); |
| 500 | 501 | ||
| 501 | /* for use I SRAM as framebuffer. */ | 502 | /* for use I SRAM as framebuffer. */ |
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index 1499493cd070..3072dbea5c1f 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c | |||
| @@ -25,7 +25,7 @@ | |||
| 25 | 25 | ||
| 26 | #include <linux/spi/spi.h> | 26 | #include <linux/spi/spi.h> |
| 27 | #include <linux/spi/ads7846.h> | 27 | #include <linux/spi/ads7846.h> |
| 28 | #include <mach/pxa2xx_spi.h> | 28 | #include <linux/spi/pxa2xx_spi.h> |
| 29 | 29 | ||
| 30 | #include <asm/setup.h> | 30 | #include <asm/setup.h> |
| 31 | #include <asm/memory.h> | 31 | #include <asm/memory.h> |
| @@ -50,6 +50,7 @@ | |||
| 50 | #include <mach/pxafb.h> | 50 | #include <mach/pxafb.h> |
| 51 | #include <mach/mmc.h> | 51 | #include <mach/mmc.h> |
| 52 | #include <mach/pm.h> | 52 | #include <mach/pm.h> |
| 53 | #include <mach/smemc.h> | ||
| 53 | 54 | ||
| 54 | #include "generic.h" | 55 | #include "generic.h" |
| 55 | #include "clock.h" | 56 | #include "clock.h" |
| @@ -525,7 +526,7 @@ static void __init lubbock_init(void) | |||
| 525 | pxa_set_ac97_info(NULL); | 526 | pxa_set_ac97_info(NULL); |
| 526 | 527 | ||
| 527 | lubbock_flash_data[0].width = lubbock_flash_data[1].width = | 528 | lubbock_flash_data[0].width = lubbock_flash_data[1].width = |
| 528 | (BOOT_DEF & 1) ? 2 : 4; | 529 | (__raw_readl(BOOT_DEF) & 1) ? 2 : 4; |
| 529 | /* Compensate for the nROMBT switch which swaps the flash banks */ | 530 | /* Compensate for the nROMBT switch which swaps the flash banks */ |
| 530 | printk(KERN_NOTICE "Lubbock configured to boot from %s (bank %d)\n", | 531 | printk(KERN_NOTICE "Lubbock configured to boot from %s (bank %d)\n", |
| 531 | flashboot?"Flash":"ROM", flashboot); | 532 | flashboot?"Flash":"ROM", flashboot); |
| @@ -549,7 +550,7 @@ static struct map_desc lubbock_io_desc[] __initdata = { | |||
| 549 | 550 | ||
| 550 | static void __init lubbock_map_io(void) | 551 | static void __init lubbock_map_io(void) |
| 551 | { | 552 | { |
| 552 | pxa_map_io(); | 553 | pxa25x_map_io(); |
| 553 | iotable_init(lubbock_io_desc, ARRAY_SIZE(lubbock_io_desc)); | 554 | iotable_init(lubbock_io_desc, ARRAY_SIZE(lubbock_io_desc)); |
| 554 | 555 | ||
| 555 | PCFR |= PCFR_OPDE; | 556 | PCFR |= PCFR_OPDE; |
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index 90663760307a..41198f0dc3ac 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c | |||
| @@ -765,7 +765,7 @@ static void __init magician_init(void) | |||
| 765 | 765 | ||
| 766 | MACHINE_START(MAGICIAN, "HTC Magician") | 766 | MACHINE_START(MAGICIAN, "HTC Magician") |
| 767 | .boot_params = 0xa0000100, | 767 | .boot_params = 0xa0000100, |
| 768 | .map_io = pxa_map_io, | 768 | .map_io = pxa27x_map_io, |
| 769 | .nr_irqs = MAGICIAN_NR_IRQS, | 769 | .nr_irqs = MAGICIAN_NR_IRQS, |
| 770 | .init_irq = pxa27x_init_irq, | 770 | .init_irq = pxa27x_init_irq, |
| 771 | .init_machine = magician_init, | 771 | .init_machine = magician_init, |
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index a980a5c93e49..740c03590e3b 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c | |||
| @@ -51,6 +51,7 @@ | |||
| 51 | #include <mach/irda.h> | 51 | #include <mach/irda.h> |
| 52 | #include <mach/ohci.h> | 52 | #include <mach/ohci.h> |
| 53 | #include <plat/pxa27x_keypad.h> | 53 | #include <plat/pxa27x_keypad.h> |
| 54 | #include <mach/smemc.h> | ||
| 54 | 55 | ||
| 55 | #include "generic.h" | 56 | #include "generic.h" |
| 56 | #include "devices.h" | 57 | #include "devices.h" |
| @@ -565,7 +566,7 @@ static void __init mainstone_init(void) | |||
| 565 | pxa_set_btuart_info(NULL); | 566 | pxa_set_btuart_info(NULL); |
| 566 | pxa_set_stuart_info(NULL); | 567 | pxa_set_stuart_info(NULL); |
| 567 | 568 | ||
| 568 | mst_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4; | 569 | mst_flash_data[0].width = (__raw_readl(BOOT_DEF) & 1) ? 2 : 4; |
| 569 | mst_flash_data[1].width = 4; | 570 | mst_flash_data[1].width = 4; |
| 570 | 571 | ||
| 571 | /* Compensate for SW7 which swaps the flash banks */ | 572 | /* Compensate for SW7 which swaps the flash banks */ |
| @@ -614,7 +615,7 @@ static struct map_desc mainstone_io_desc[] __initdata = { | |||
| 614 | 615 | ||
| 615 | static void __init mainstone_map_io(void) | 616 | static void __init mainstone_map_io(void) |
| 616 | { | 617 | { |
| 617 | pxa_map_io(); | 618 | pxa27x_map_io(); |
| 618 | iotable_init(mainstone_io_desc, ARRAY_SIZE(mainstone_io_desc)); | 619 | iotable_init(mainstone_io_desc, ARRAY_SIZE(mainstone_io_desc)); |
| 619 | 620 | ||
| 620 | /* for use I SRAM as framebuffer. */ | 621 | /* for use I SRAM as framebuffer. */ |
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index f5fb915e1315..faafea3542fb 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c | |||
| @@ -819,7 +819,7 @@ static void mioa701_machine_exit(void) | |||
| 819 | 819 | ||
| 820 | MACHINE_START(MIOA701, "MIO A701") | 820 | MACHINE_START(MIOA701, "MIO A701") |
| 821 | .boot_params = 0xa0000100, | 821 | .boot_params = 0xa0000100, |
| 822 | .map_io = &pxa_map_io, | 822 | .map_io = &pxa27x_map_io, |
| 823 | .init_irq = &pxa27x_init_irq, | 823 | .init_irq = &pxa27x_init_irq, |
| 824 | .init_machine = mioa701_machine_init, | 824 | .init_machine = mioa701_machine_init, |
| 825 | .timer = &pxa_timer, | 825 | .timer = &pxa_timer, |
diff --git a/arch/arm/mach-pxa/mp900.c b/arch/arm/mach-pxa/mp900.c index 116167aaba68..59cce78aebd1 100644 --- a/arch/arm/mach-pxa/mp900.c +++ b/arch/arm/mach-pxa/mp900.c | |||
| @@ -94,7 +94,7 @@ static void __init mp900c_init(void) | |||
| 94 | MACHINE_START(NEC_MP900, "MobilePro900/C") | 94 | MACHINE_START(NEC_MP900, "MobilePro900/C") |
| 95 | .boot_params = 0xa0220100, | 95 | .boot_params = 0xa0220100, |
| 96 | .timer = &pxa_timer, | 96 | .timer = &pxa_timer, |
| 97 | .map_io = pxa_map_io, | 97 | .map_io = pxa25x_map_io, |
| 98 | .init_irq = pxa25x_init_irq, | 98 | .init_irq = pxa25x_init_irq, |
| 99 | .init_machine = mp900c_init, | 99 | .init_machine = mp900c_init, |
| 100 | MACHINE_END | 100 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c index ce092c521e6d..a6f898cbfac9 100644 --- a/arch/arm/mach-pxa/palmld.c +++ b/arch/arm/mach-pxa/palmld.c | |||
| @@ -313,7 +313,7 @@ static struct map_desc palmld_io_desc[] __initdata = { | |||
| 313 | 313 | ||
| 314 | static void __init palmld_map_io(void) | 314 | static void __init palmld_map_io(void) |
| 315 | { | 315 | { |
| 316 | pxa_map_io(); | 316 | pxa27x_map_io(); |
| 317 | iotable_init(palmld_io_desc, ARRAY_SIZE(palmld_io_desc)); | 317 | iotable_init(palmld_io_desc, ARRAY_SIZE(palmld_io_desc)); |
| 318 | } | 318 | } |
| 319 | 319 | ||
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c index 862da812cd10..df4d7d009fbb 100644 --- a/arch/arm/mach-pxa/palmt5.c +++ b/arch/arm/mach-pxa/palmt5.c | |||
| @@ -203,7 +203,7 @@ static void __init palmt5_init(void) | |||
| 203 | 203 | ||
| 204 | MACHINE_START(PALMT5, "Palm Tungsten|T5") | 204 | MACHINE_START(PALMT5, "Palm Tungsten|T5") |
| 205 | .boot_params = 0xa0000100, | 205 | .boot_params = 0xa0000100, |
| 206 | .map_io = pxa_map_io, | 206 | .map_io = pxa27x_map_io, |
| 207 | .reserve = palmt5_reserve, | 207 | .reserve = palmt5_reserve, |
| 208 | .init_irq = pxa27x_init_irq, | 208 | .init_irq = pxa27x_init_irq, |
| 209 | .timer = &pxa_timer, | 209 | .timer = &pxa_timer, |
diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c index 2131d5860919..a09a2374697b 100644 --- a/arch/arm/mach-pxa/palmtc.c +++ b/arch/arm/mach-pxa/palmtc.c | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | #include <linux/power_supply.h> | 25 | #include <linux/power_supply.h> |
| 26 | #include <linux/gpio_keys.h> | 26 | #include <linux/gpio_keys.h> |
| 27 | #include <linux/mtd/physmap.h> | 27 | #include <linux/mtd/physmap.h> |
| 28 | #include <linux/usb/gpio_vbus.h> | ||
| 28 | 29 | ||
| 29 | #include <asm/mach-types.h> | 30 | #include <asm/mach-types.h> |
| 30 | #include <asm/mach/arch.h> | 31 | #include <asm/mach/arch.h> |
| @@ -116,6 +117,7 @@ static unsigned long palmtc_pin_config[] __initdata = { | |||
| 116 | /****************************************************************************** | 117 | /****************************************************************************** |
| 117 | * SD/MMC card controller | 118 | * SD/MMC card controller |
| 118 | ******************************************************************************/ | 119 | ******************************************************************************/ |
| 120 | #if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) | ||
| 119 | static struct pxamci_platform_data palmtc_mci_platform_data = { | 121 | static struct pxamci_platform_data palmtc_mci_platform_data = { |
| 120 | .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, | 122 | .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, |
| 121 | .gpio_power = GPIO_NR_PALMTC_SD_POWER, | 123 | .gpio_power = GPIO_NR_PALMTC_SD_POWER, |
| @@ -124,9 +126,18 @@ static struct pxamci_platform_data palmtc_mci_platform_data = { | |||
| 124 | .detect_delay_ms = 200, | 126 | .detect_delay_ms = 200, |
| 125 | }; | 127 | }; |
| 126 | 128 | ||
| 129 | static void __init palmtc_mmc_init(void) | ||
| 130 | { | ||
| 131 | pxa_set_mci_info(&palmtc_mci_platform_data); | ||
| 132 | } | ||
| 133 | #else | ||
| 134 | static inline void palmtc_mmc_init(void) {} | ||
| 135 | #endif | ||
| 136 | |||
| 127 | /****************************************************************************** | 137 | /****************************************************************************** |
| 128 | * GPIO keys | 138 | * GPIO keys |
| 129 | ******************************************************************************/ | 139 | ******************************************************************************/ |
| 140 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) | ||
| 130 | static struct gpio_keys_button palmtc_pxa_buttons[] = { | 141 | static struct gpio_keys_button palmtc_pxa_buttons[] = { |
| 131 | {KEY_F8, GPIO_NR_PALMTC_HOTSYNC_BUTTON, 1, "HotSync Button", EV_KEY, 1}, | 142 | {KEY_F8, GPIO_NR_PALMTC_HOTSYNC_BUTTON, 1, "HotSync Button", EV_KEY, 1}, |
| 132 | }; | 143 | }; |
| @@ -144,9 +155,18 @@ static struct platform_device palmtc_pxa_keys = { | |||
| 144 | }, | 155 | }, |
| 145 | }; | 156 | }; |
| 146 | 157 | ||
| 158 | static void __init palmtc_keys_init(void) | ||
| 159 | { | ||
| 160 | platform_device_register(&palmtc_pxa_keys); | ||
| 161 | } | ||
| 162 | #else | ||
| 163 | static inline void palmtc_keys_init(void) {} | ||
| 164 | #endif | ||
| 165 | |||
| 147 | /****************************************************************************** | 166 | /****************************************************************************** |
| 148 | * Backlight | 167 | * Backlight |
| 149 | ******************************************************************************/ | 168 | ******************************************************************************/ |
| 169 | #if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE) | ||
| 150 | static int palmtc_backlight_init(struct device *dev) | 170 | static int palmtc_backlight_init(struct device *dev) |
| 151 | { | 171 | { |
| 152 | int ret; | 172 | int ret; |
| @@ -196,17 +216,35 @@ static struct platform_device palmtc_backlight = { | |||
| 196 | }, | 216 | }, |
| 197 | }; | 217 | }; |
| 198 | 218 | ||
| 219 | static void __init palmtc_pwm_init(void) | ||
| 220 | { | ||
| 221 | platform_device_register(&palmtc_backlight); | ||
| 222 | } | ||
| 223 | #else | ||
| 224 | static inline void palmtc_pwm_init(void) {} | ||
| 225 | #endif | ||
| 226 | |||
| 199 | /****************************************************************************** | 227 | /****************************************************************************** |
| 200 | * IrDA | 228 | * IrDA |
| 201 | ******************************************************************************/ | 229 | ******************************************************************************/ |
| 230 | #if defined(CONFIG_IRDA) || defined(CONFIG_IRDA_MODULE) | ||
| 202 | static struct pxaficp_platform_data palmtc_ficp_platform_data = { | 231 | static struct pxaficp_platform_data palmtc_ficp_platform_data = { |
| 203 | .gpio_pwdown = GPIO_NR_PALMTC_IR_DISABLE, | 232 | .gpio_pwdown = GPIO_NR_PALMTC_IR_DISABLE, |
| 204 | .transceiver_cap = IR_SIRMODE | IR_OFF, | 233 | .transceiver_cap = IR_SIRMODE | IR_OFF, |
| 205 | }; | 234 | }; |
| 206 | 235 | ||
| 236 | static void __init palmtc_irda_init(void) | ||
| 237 | { | ||
| 238 | pxa_set_ficp_info(&palmtc_ficp_platform_data); | ||
| 239 | } | ||
| 240 | #else | ||
| 241 | static inline void palmtc_irda_init(void) {} | ||
| 242 | #endif | ||
| 243 | |||
| 207 | /****************************************************************************** | 244 | /****************************************************************************** |
| 208 | * Keyboard | 245 | * Keyboard |
| 209 | ******************************************************************************/ | 246 | ******************************************************************************/ |
| 247 | #if defined(CONFIG_KEYBOARD_MATRIX) || defined(CONFIG_KEYBOARD_MATRIX_MODULE) | ||
| 210 | static const uint32_t palmtc_matrix_keys[] = { | 248 | static const uint32_t palmtc_matrix_keys[] = { |
| 211 | KEY(0, 0, KEY_F1), | 249 | KEY(0, 0, KEY_F1), |
| 212 | KEY(0, 1, KEY_X), | 250 | KEY(0, 1, KEY_X), |
| @@ -290,27 +328,103 @@ static struct platform_device palmtc_keyboard = { | |||
| 290 | .platform_data = &palmtc_keypad_platform_data, | 328 | .platform_data = &palmtc_keypad_platform_data, |
| 291 | }, | 329 | }, |
| 292 | }; | 330 | }; |
| 331 | static void __init palmtc_mkp_init(void) | ||
| 332 | { | ||
| 333 | platform_device_register(&palmtc_keyboard); | ||
| 334 | } | ||
| 335 | #else | ||
| 336 | static inline void palmtc_mkp_init(void) {} | ||
| 337 | #endif | ||
| 293 | 338 | ||
| 294 | /****************************************************************************** | 339 | /****************************************************************************** |
| 295 | * UDC | 340 | * UDC |
| 296 | ******************************************************************************/ | 341 | ******************************************************************************/ |
| 297 | static struct pxa2xx_udc_mach_info palmtc_udc_info __initdata = { | 342 | #if defined(CONFIG_USB_GADGET_PXA25X)||defined(CONFIG_USB_GADGET_PXA25X_MODULE) |
| 343 | static struct gpio_vbus_mach_info palmtc_udc_info = { | ||
| 298 | .gpio_vbus = GPIO_NR_PALMTC_USB_DETECT_N, | 344 | .gpio_vbus = GPIO_NR_PALMTC_USB_DETECT_N, |
| 299 | .gpio_vbus_inverted = 1, | 345 | .gpio_vbus_inverted = 1, |
| 300 | .gpio_pullup = GPIO_NR_PALMTC_USB_POWER, | 346 | .gpio_pullup = GPIO_NR_PALMTC_USB_POWER, |
| 301 | }; | 347 | }; |
| 302 | 348 | ||
| 349 | static struct platform_device palmtc_gpio_vbus = { | ||
| 350 | .name = "gpio-vbus", | ||
| 351 | .id = -1, | ||
| 352 | .dev = { | ||
| 353 | .platform_data = &palmtc_udc_info, | ||
| 354 | }, | ||
| 355 | }; | ||
| 356 | |||
| 357 | static void __init palmtc_udc_init(void) | ||
| 358 | { | ||
| 359 | platform_device_register(&palmtc_gpio_vbus); | ||
| 360 | }; | ||
| 361 | #else | ||
| 362 | static inline void palmtc_udc_init(void) {} | ||
| 363 | #endif | ||
| 364 | |||
| 303 | /****************************************************************************** | 365 | /****************************************************************************** |
| 304 | * Touchscreen / Battery / GPIO-extender | 366 | * Touchscreen / Battery / GPIO-extender |
| 305 | ******************************************************************************/ | 367 | ******************************************************************************/ |
| 306 | static struct platform_device palmtc_ucb1400_core = { | 368 | #if defined(CONFIG_TOUCHSCREEN_UCB1400) || \ |
| 369 | defined(CONFIG_TOUCHSCREEN_UCB1400_MODULE) | ||
| 370 | static struct platform_device palmtc_ucb1400_device = { | ||
| 307 | .name = "ucb1400_core", | 371 | .name = "ucb1400_core", |
| 308 | .id = -1, | 372 | .id = -1, |
| 309 | }; | 373 | }; |
| 310 | 374 | ||
| 375 | static void __init palmtc_ts_init(void) | ||
| 376 | { | ||
| 377 | pxa_set_ac97_info(NULL); | ||
| 378 | platform_device_register(&palmtc_ucb1400_device); | ||
| 379 | } | ||
| 380 | #else | ||
| 381 | static inline void palmtc_ts_init(void) {} | ||
| 382 | #endif | ||
| 383 | |||
| 384 | /****************************************************************************** | ||
| 385 | * LEDs | ||
| 386 | ******************************************************************************/ | ||
| 387 | #if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) | ||
| 388 | struct gpio_led palmtc_gpio_leds[] = { | ||
| 389 | { | ||
| 390 | .name = "palmtc:green:user", | ||
| 391 | .default_trigger = "none", | ||
| 392 | .gpio = GPIO_NR_PALMTC_LED_POWER, | ||
| 393 | .active_low = 1, | ||
| 394 | }, { | ||
| 395 | .name = "palmtc:vibra:vibra", | ||
| 396 | .default_trigger = "none", | ||
| 397 | .gpio = GPIO_NR_PALMTC_VIBRA_POWER, | ||
| 398 | .active_low = 1, | ||
| 399 | } | ||
| 400 | |||
| 401 | }; | ||
| 402 | |||
| 403 | static struct gpio_led_platform_data palmtc_gpio_led_info = { | ||
| 404 | .leds = palmtc_gpio_leds, | ||
| 405 | .num_leds = ARRAY_SIZE(palmtc_gpio_leds), | ||
| 406 | }; | ||
| 407 | |||
| 408 | static struct platform_device palmtc_leds = { | ||
| 409 | .name = "leds-gpio", | ||
| 410 | .id = -1, | ||
| 411 | .dev = { | ||
| 412 | .platform_data = &palmtc_gpio_led_info, | ||
| 413 | } | ||
| 414 | }; | ||
| 415 | |||
| 416 | static void __init palmtc_leds_init(void) | ||
| 417 | { | ||
| 418 | platform_device_register(&palmtc_leds); | ||
| 419 | } | ||
| 420 | #else | ||
| 421 | static inline void palmtc_leds_init(void) {} | ||
| 422 | #endif | ||
| 423 | |||
| 311 | /****************************************************************************** | 424 | /****************************************************************************** |
| 312 | * NOR Flash | 425 | * NOR Flash |
| 313 | ******************************************************************************/ | 426 | ******************************************************************************/ |
| 427 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) | ||
| 314 | static struct resource palmtc_flash_resource = { | 428 | static struct resource palmtc_flash_resource = { |
| 315 | .start = PXA_CS0_PHYS, | 429 | .start = PXA_CS0_PHYS, |
| 316 | .end = PXA_CS0_PHYS + SZ_16M - 1, | 430 | .end = PXA_CS0_PHYS + SZ_16M - 1, |
| @@ -356,24 +470,33 @@ static struct platform_device palmtc_flash = { | |||
| 356 | }, | 470 | }, |
| 357 | }; | 471 | }; |
| 358 | 472 | ||
| 473 | static void __init palmtc_nor_init(void) | ||
| 474 | { | ||
| 475 | platform_device_register(&palmtc_flash); | ||
| 476 | } | ||
| 477 | #else | ||
| 478 | static inline void palmtc_nor_init(void) {} | ||
| 479 | #endif | ||
| 480 | |||
| 359 | /****************************************************************************** | 481 | /****************************************************************************** |
| 360 | * Framebuffer | 482 | * Framebuffer |
| 361 | ******************************************************************************/ | 483 | ******************************************************************************/ |
| 484 | #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) | ||
| 362 | static struct pxafb_mode_info palmtc_lcd_modes[] = { | 485 | static struct pxafb_mode_info palmtc_lcd_modes[] = { |
| 363 | { | 486 | { |
| 364 | .pixclock = 115384, | 487 | .pixclock = 115384, |
| 365 | .xres = 320, | 488 | .xres = 320, |
| 366 | .yres = 320, | 489 | .yres = 320, |
| 367 | .bpp = 16, | 490 | .bpp = 16, |
| 368 | 491 | ||
| 369 | .left_margin = 27, | 492 | .left_margin = 27, |
| 370 | .right_margin = 7, | 493 | .right_margin = 7, |
| 371 | .upper_margin = 7, | 494 | .upper_margin = 7, |
| 372 | .lower_margin = 8, | 495 | .lower_margin = 8, |
| 373 | 496 | ||
| 374 | .hsync_len = 6, | 497 | .hsync_len = 6, |
| 375 | .vsync_len = 1, | 498 | .vsync_len = 1, |
| 376 | }, | 499 | }, |
| 377 | }; | 500 | }; |
| 378 | 501 | ||
| 379 | static struct pxafb_mach_info palmtc_lcd_screen = { | 502 | static struct pxafb_mach_info palmtc_lcd_screen = { |
| @@ -382,17 +505,17 @@ static struct pxafb_mach_info palmtc_lcd_screen = { | |||
| 382 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, | 505 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, |
| 383 | }; | 506 | }; |
| 384 | 507 | ||
| 508 | static void __init palmtc_lcd_init(void) | ||
| 509 | { | ||
| 510 | set_pxa_fb_info(&palmtc_lcd_screen); | ||
| 511 | } | ||
| 512 | #else | ||
| 513 | static inline void palmtc_lcd_init(void) {} | ||
| 514 | #endif | ||
| 515 | |||
| 385 | /****************************************************************************** | 516 | /****************************************************************************** |
| 386 | * Machine init | 517 | * Machine init |
| 387 | ******************************************************************************/ | 518 | ******************************************************************************/ |
| 388 | static struct platform_device *devices[] __initdata = { | ||
| 389 | &palmtc_backlight, | ||
| 390 | &palmtc_ucb1400_core, | ||
| 391 | &palmtc_keyboard, | ||
| 392 | &palmtc_pxa_keys, | ||
| 393 | &palmtc_flash, | ||
| 394 | }; | ||
| 395 | |||
| 396 | static void __init palmtc_init(void) | 519 | static void __init palmtc_init(void) |
| 397 | { | 520 | { |
| 398 | pxa2xx_mfp_config(ARRAY_AND_SIZE(palmtc_pin_config)); | 521 | pxa2xx_mfp_config(ARRAY_AND_SIZE(palmtc_pin_config)); |
| @@ -402,18 +525,21 @@ static void __init palmtc_init(void) | |||
| 402 | pxa_set_stuart_info(NULL); | 525 | pxa_set_stuart_info(NULL); |
| 403 | pxa_set_hwuart_info(NULL); | 526 | pxa_set_hwuart_info(NULL); |
| 404 | 527 | ||
| 405 | set_pxa_fb_info(&palmtc_lcd_screen); | 528 | palmtc_mmc_init(); |
| 406 | pxa_set_mci_info(&palmtc_mci_platform_data); | 529 | palmtc_keys_init(); |
| 407 | pxa_set_udc_info(&palmtc_udc_info); | 530 | palmtc_pwm_init(); |
| 408 | pxa_set_ac97_info(NULL); | 531 | palmtc_irda_init(); |
| 409 | pxa_set_ficp_info(&palmtc_ficp_platform_data); | 532 | palmtc_mkp_init(); |
| 410 | 533 | palmtc_udc_init(); | |
| 411 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 534 | palmtc_ts_init(); |
| 535 | palmtc_nor_init(); | ||
| 536 | palmtc_lcd_init(); | ||
| 537 | palmtc_leds_init(); | ||
| 412 | }; | 538 | }; |
| 413 | 539 | ||
| 414 | MACHINE_START(PALMTC, "Palm Tungsten|C") | 540 | MACHINE_START(PALMTC, "Palm Tungsten|C") |
| 415 | .boot_params = 0xa0000100, | 541 | .boot_params = 0xa0000100, |
| 416 | .map_io = pxa_map_io, | 542 | .map_io = pxa25x_map_io, |
| 417 | .init_irq = pxa25x_init_irq, | 543 | .init_irq = pxa25x_init_irq, |
| 418 | .timer = &pxa_timer, | 544 | .timer = &pxa_timer, |
| 419 | .init_machine = palmtc_init | 545 | .init_machine = palmtc_init |
diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c index a9dae7bc35d9..3f25014a136c 100644 --- a/arch/arm/mach-pxa/palmte2.c +++ b/arch/arm/mach-pxa/palmte2.c | |||
| @@ -374,7 +374,7 @@ static void __init palmte2_init(void) | |||
| 374 | 374 | ||
| 375 | MACHINE_START(PALMTE2, "Palm Tungsten|E2") | 375 | MACHINE_START(PALMTE2, "Palm Tungsten|E2") |
| 376 | .boot_params = 0xa0000100, | 376 | .boot_params = 0xa0000100, |
| 377 | .map_io = pxa_map_io, | 377 | .map_io = pxa25x_map_io, |
| 378 | .init_irq = pxa25x_init_irq, | 378 | .init_irq = pxa25x_init_irq, |
| 379 | .timer = &pxa_timer, | 379 | .timer = &pxa_timer, |
| 380 | .init_machine = palmte2_init | 380 | .init_machine = palmte2_init |
diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c index 00e2d7ba84ed..8aadad55fbe4 100644 --- a/arch/arm/mach-pxa/palmtreo.c +++ b/arch/arm/mach-pxa/palmtreo.c | |||
| @@ -442,7 +442,7 @@ static void __init centro_init(void) | |||
| 442 | 442 | ||
| 443 | MACHINE_START(TREO680, "Palm Treo 680") | 443 | MACHINE_START(TREO680, "Palm Treo 680") |
| 444 | .boot_params = 0xa0000100, | 444 | .boot_params = 0xa0000100, |
| 445 | .map_io = pxa_map_io, | 445 | .map_io = pxa27x_map_io, |
| 446 | .reserve = treo_reserve, | 446 | .reserve = treo_reserve, |
| 447 | .init_irq = pxa27x_init_irq, | 447 | .init_irq = pxa27x_init_irq, |
| 448 | .timer = &pxa_timer, | 448 | .timer = &pxa_timer, |
| @@ -451,7 +451,7 @@ MACHINE_END | |||
| 451 | 451 | ||
| 452 | MACHINE_START(CENTRO, "Palm Centro 685") | 452 | MACHINE_START(CENTRO, "Palm Centro 685") |
| 453 | .boot_params = 0xa0000100, | 453 | .boot_params = 0xa0000100, |
| 454 | .map_io = pxa_map_io, | 454 | .map_io = pxa27x_map_io, |
| 455 | .reserve = treo_reserve, | 455 | .reserve = treo_reserve, |
| 456 | .init_irq = pxa27x_init_irq, | 456 | .init_irq = pxa27x_init_irq, |
| 457 | .timer = &pxa_timer, | 457 | .timer = &pxa_timer, |
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c index e5c9932b7588..595f002066cc 100644 --- a/arch/arm/mach-pxa/palmtx.c +++ b/arch/arm/mach-pxa/palmtx.c | |||
| @@ -334,7 +334,7 @@ static struct map_desc palmtx_io_desc[] __initdata = { | |||
| 334 | 334 | ||
| 335 | static void __init palmtx_map_io(void) | 335 | static void __init palmtx_map_io(void) |
| 336 | { | 336 | { |
| 337 | pxa_map_io(); | 337 | pxa27x_map_io(); |
| 338 | iotable_init(palmtx_io_desc, ARRAY_SIZE(palmtx_io_desc)); | 338 | iotable_init(palmtx_io_desc, ARRAY_SIZE(palmtx_io_desc)); |
| 339 | } | 339 | } |
| 340 | 340 | ||
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c index af6203fbca9c..7bf4017326e3 100644 --- a/arch/arm/mach-pxa/palmz72.c +++ b/arch/arm/mach-pxa/palmz72.c | |||
| @@ -280,7 +280,7 @@ static void __init palmz72_init(void) | |||
| 280 | 280 | ||
| 281 | MACHINE_START(PALMZ72, "Palm Zire72") | 281 | MACHINE_START(PALMZ72, "Palm Zire72") |
| 282 | .boot_params = 0xa0000100, | 282 | .boot_params = 0xa0000100, |
| 283 | .map_io = pxa_map_io, | 283 | .map_io = pxa27x_map_io, |
| 284 | .init_irq = pxa27x_init_irq, | 284 | .init_irq = pxa27x_init_irq, |
| 285 | .timer = &pxa_timer, | 285 | .timer = &pxa_timer, |
| 286 | .init_machine = palmz72_init | 286 | .init_machine = palmz72_init |
diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c index c77e8f30a439..1fc8a66407ae 100644 --- a/arch/arm/mach-pxa/pcm027.c +++ b/arch/arm/mach-pxa/pcm027.c | |||
| @@ -25,12 +25,12 @@ | |||
| 25 | #include <linux/mtd/physmap.h> | 25 | #include <linux/mtd/physmap.h> |
| 26 | #include <linux/spi/spi.h> | 26 | #include <linux/spi/spi.h> |
| 27 | #include <linux/spi/max7301.h> | 27 | #include <linux/spi/max7301.h> |
| 28 | #include <linux/spi/pxa2xx_spi.h> | ||
| 28 | #include <linux/leds.h> | 29 | #include <linux/leds.h> |
| 29 | 30 | ||
| 30 | #include <asm/mach-types.h> | 31 | #include <asm/mach-types.h> |
| 31 | #include <asm/mach/arch.h> | 32 | #include <asm/mach/arch.h> |
| 32 | #include <mach/pxa27x.h> | 33 | #include <mach/pxa27x.h> |
| 33 | #include <mach/pxa2xx_spi.h> | ||
| 34 | #include <mach/pcm027.h> | 34 | #include <mach/pcm027.h> |
| 35 | #include "generic.h" | 35 | #include "generic.h" |
| 36 | 36 | ||
| @@ -244,7 +244,7 @@ static void __init pcm027_init(void) | |||
| 244 | 244 | ||
| 245 | static void __init pcm027_map_io(void) | 245 | static void __init pcm027_map_io(void) |
| 246 | { | 246 | { |
| 247 | pxa_map_io(); | 247 | pxa27x_map_io(); |
| 248 | 248 | ||
| 249 | /* initialize sleep mode regs (wake-up sources, etc) */ | 249 | /* initialize sleep mode regs (wake-up sources, etc) */ |
| 250 | PGSR0 = 0x01308000; | 250 | PGSR0 = 0x01308000; |
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index 93a191c889df..4f0ff1ab623d 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | #include <linux/i2c.h> | 25 | #include <linux/i2c.h> |
| 26 | #include <linux/spi/spi.h> | 26 | #include <linux/spi/spi.h> |
| 27 | #include <linux/spi/ads7846.h> | 27 | #include <linux/spi/ads7846.h> |
| 28 | #include <linux/spi/pxa2xx_spi.h> | ||
| 28 | #include <linux/mtd/sharpsl.h> | 29 | #include <linux/mtd/sharpsl.h> |
| 29 | 30 | ||
| 30 | #include <mach/hardware.h> | 31 | #include <mach/hardware.h> |
| @@ -43,7 +44,6 @@ | |||
| 43 | #include <mach/irda.h> | 44 | #include <mach/irda.h> |
| 44 | #include <mach/poodle.h> | 45 | #include <mach/poodle.h> |
| 45 | #include <mach/pxafb.h> | 46 | #include <mach/pxafb.h> |
| 46 | #include <mach/pxa2xx_spi.h> | ||
| 47 | #include <plat/i2c.h> | 47 | #include <plat/i2c.h> |
| 48 | 48 | ||
| 49 | #include <asm/hardware/scoop.h> | 49 | #include <asm/hardware/scoop.h> |
| @@ -466,7 +466,7 @@ static void __init fixup_poodle(struct machine_desc *desc, | |||
| 466 | 466 | ||
| 467 | MACHINE_START(POODLE, "SHARP Poodle") | 467 | MACHINE_START(POODLE, "SHARP Poodle") |
| 468 | .fixup = fixup_poodle, | 468 | .fixup = fixup_poodle, |
| 469 | .map_io = pxa_map_io, | 469 | .map_io = pxa25x_map_io, |
| 470 | .nr_irqs = POODLE_NR_IRQS, /* 4 for LoCoMo */ | 470 | .nr_irqs = POODLE_NR_IRQS, /* 4 for LoCoMo */ |
| 471 | .init_irq = pxa25x_init_irq, | 471 | .init_irq = pxa25x_init_irq, |
| 472 | .timer = &pxa_timer, | 472 | .timer = &pxa_timer, |
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index de53f2e4aa39..3f5241c84894 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | #include <linux/suspend.h> | 23 | #include <linux/suspend.h> |
| 24 | #include <linux/sysdev.h> | 24 | #include <linux/sysdev.h> |
| 25 | 25 | ||
| 26 | #include <asm/mach/map.h> | ||
| 26 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
| 27 | #include <mach/irqs.h> | 28 | #include <mach/irqs.h> |
| 28 | #include <mach/gpio.h> | 29 | #include <mach/gpio.h> |
| @@ -30,6 +31,7 @@ | |||
| 30 | #include <mach/reset.h> | 31 | #include <mach/reset.h> |
| 31 | #include <mach/pm.h> | 32 | #include <mach/pm.h> |
| 32 | #include <mach/dma.h> | 33 | #include <mach/dma.h> |
| 34 | #include <mach/smemc.h> | ||
| 33 | 35 | ||
| 34 | #include "generic.h" | 36 | #include "generic.h" |
| 35 | #include "devices.h" | 37 | #include "devices.h" |
| @@ -90,23 +92,21 @@ unsigned int pxa25x_get_clk_frequency_khz(int info) | |||
| 90 | return (turbo & 1) ? (N/1000) : (M/1000); | 92 | return (turbo & 1) ? (N/1000) : (M/1000); |
| 91 | } | 93 | } |
| 92 | 94 | ||
| 93 | /* | 95 | static unsigned long clk_pxa25x_mem_getrate(struct clk *clk) |
| 94 | * Return the current memory clock frequency in units of 10kHz | ||
| 95 | */ | ||
| 96 | unsigned int pxa25x_get_memclk_frequency_10khz(void) | ||
| 97 | { | 96 | { |
| 98 | return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000; | 97 | return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK; |
| 99 | } | 98 | } |
| 100 | 99 | ||
| 101 | static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk) | 100 | static const struct clkops clk_pxa25x_mem_ops = { |
| 102 | { | 101 | .enable = clk_dummy_enable, |
| 103 | return pxa25x_get_memclk_frequency_10khz() * 10000; | 102 | .disable = clk_dummy_disable, |
| 104 | } | 103 | .getrate = clk_pxa25x_mem_getrate, |
| 104 | }; | ||
| 105 | 105 | ||
| 106 | static const struct clkops clk_pxa25x_lcd_ops = { | 106 | static const struct clkops clk_pxa25x_lcd_ops = { |
| 107 | .enable = clk_cken_enable, | 107 | .enable = clk_pxa2xx_cken_enable, |
| 108 | .disable = clk_cken_disable, | 108 | .disable = clk_pxa2xx_cken_disable, |
| 109 | .getrate = clk_pxa25x_lcd_getrate, | 109 | .getrate = clk_pxa25x_mem_getrate, |
| 110 | }; | 110 | }; |
| 111 | 111 | ||
| 112 | static unsigned long gpio12_config_32k[] = { | 112 | static unsigned long gpio12_config_32k[] = { |
| @@ -160,31 +160,30 @@ static const struct clkops clk_pxa25x_gpio11_ops = { | |||
| 160 | * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz | 160 | * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz |
| 161 | * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly) | 161 | * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly) |
| 162 | */ | 162 | */ |
| 163 | static DEFINE_CKEN(pxa25x_hwuart, HWUART, 14745600, 1); | ||
| 164 | |||
| 165 | static struct clk_lookup pxa25x_hwuart_clkreg = | ||
| 166 | INIT_CLKREG(&clk_pxa25x_hwuart, "pxa2xx-uart.3", NULL); | ||
| 167 | 163 | ||
| 168 | /* | 164 | /* |
| 169 | * PXA 2xx clock declarations. | 165 | * PXA 2xx clock declarations. |
| 170 | */ | 166 | */ |
| 167 | static DEFINE_PXA2_CKEN(pxa25x_hwuart, HWUART, 14745600, 1); | ||
| 168 | static DEFINE_PXA2_CKEN(pxa25x_ffuart, FFUART, 14745600, 1); | ||
| 169 | static DEFINE_PXA2_CKEN(pxa25x_btuart, BTUART, 14745600, 1); | ||
| 170 | static DEFINE_PXA2_CKEN(pxa25x_stuart, STUART, 14745600, 1); | ||
| 171 | static DEFINE_PXA2_CKEN(pxa25x_usb, USB, 47923000, 5); | ||
| 172 | static DEFINE_PXA2_CKEN(pxa25x_mmc, MMC, 19169000, 0); | ||
| 173 | static DEFINE_PXA2_CKEN(pxa25x_i2c, I2C, 31949000, 0); | ||
| 174 | static DEFINE_PXA2_CKEN(pxa25x_ssp, SSP, 3686400, 0); | ||
| 175 | static DEFINE_PXA2_CKEN(pxa25x_nssp, NSSP, 3686400, 0); | ||
| 176 | static DEFINE_PXA2_CKEN(pxa25x_assp, ASSP, 3686400, 0); | ||
| 177 | static DEFINE_PXA2_CKEN(pxa25x_pwm0, PWM0, 3686400, 0); | ||
| 178 | static DEFINE_PXA2_CKEN(pxa25x_pwm1, PWM1, 3686400, 0); | ||
| 179 | static DEFINE_PXA2_CKEN(pxa25x_ac97, AC97, 24576000, 0); | ||
| 180 | static DEFINE_PXA2_CKEN(pxa25x_i2s, I2S, 14745600, 0); | ||
| 181 | static DEFINE_PXA2_CKEN(pxa25x_ficp, FICP, 47923000, 0); | ||
| 182 | |||
| 171 | static DEFINE_CK(pxa25x_lcd, LCD, &clk_pxa25x_lcd_ops); | 183 | static DEFINE_CK(pxa25x_lcd, LCD, &clk_pxa25x_lcd_ops); |
| 172 | static DEFINE_CKEN(pxa25x_ffuart, FFUART, 14745600, 1); | ||
| 173 | static DEFINE_CKEN(pxa25x_btuart, BTUART, 14745600, 1); | ||
| 174 | static DEFINE_CKEN(pxa25x_stuart, STUART, 14745600, 1); | ||
| 175 | static DEFINE_CKEN(pxa25x_usb, USB, 47923000, 5); | ||
| 176 | static DEFINE_CLK(pxa25x_gpio11, &clk_pxa25x_gpio11_ops, 3686400, 0); | 184 | static DEFINE_CLK(pxa25x_gpio11, &clk_pxa25x_gpio11_ops, 3686400, 0); |
| 177 | static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0); | 185 | static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0); |
| 178 | static DEFINE_CKEN(pxa25x_mmc, MMC, 19169000, 0); | 186 | static DEFINE_CLK(pxa25x_mem, &clk_pxa25x_mem_ops, 0, 0); |
| 179 | static DEFINE_CKEN(pxa25x_i2c, I2C, 31949000, 0); | ||
| 180 | static DEFINE_CKEN(pxa25x_ssp, SSP, 3686400, 0); | ||
| 181 | static DEFINE_CKEN(pxa25x_nssp, NSSP, 3686400, 0); | ||
| 182 | static DEFINE_CKEN(pxa25x_assp, ASSP, 3686400, 0); | ||
| 183 | static DEFINE_CKEN(pxa25x_pwm0, PWM0, 3686400, 0); | ||
| 184 | static DEFINE_CKEN(pxa25x_pwm1, PWM1, 3686400, 0); | ||
| 185 | static DEFINE_CKEN(pxa25x_ac97, AC97, 24576000, 0); | ||
| 186 | static DEFINE_CKEN(pxa25x_i2s, I2S, 14745600, 0); | ||
| 187 | static DEFINE_CKEN(pxa25x_ficp, FICP, 47923000, 0); | ||
| 188 | 187 | ||
| 189 | static struct clk_lookup pxa25x_clkregs[] = { | 188 | static struct clk_lookup pxa25x_clkregs[] = { |
| 190 | INIT_CLKREG(&clk_pxa25x_lcd, "pxa2xx-fb", NULL), | 189 | INIT_CLKREG(&clk_pxa25x_lcd, "pxa2xx-fb", NULL), |
| @@ -205,8 +204,12 @@ static struct clk_lookup pxa25x_clkregs[] = { | |||
| 205 | INIT_CLKREG(&clk_pxa25x_ac97, NULL, "AC97CLK"), | 204 | INIT_CLKREG(&clk_pxa25x_ac97, NULL, "AC97CLK"), |
| 206 | INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"), | 205 | INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"), |
| 207 | INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"), | 206 | INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"), |
| 207 | INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL), | ||
| 208 | }; | 208 | }; |
| 209 | 209 | ||
| 210 | static struct clk_lookup pxa25x_hwuart_clkreg = | ||
| 211 | INIT_CLKREG(&clk_pxa25x_hwuart, "pxa2xx-uart.3", NULL); | ||
| 212 | |||
| 210 | #ifdef CONFIG_PM | 213 | #ifdef CONFIG_PM |
| 211 | 214 | ||
| 212 | #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x | 215 | #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x |
| @@ -219,20 +222,17 @@ static struct clk_lookup pxa25x_clkregs[] = { | |||
| 219 | */ | 222 | */ |
| 220 | enum { | 223 | enum { |
| 221 | SLEEP_SAVE_PSTR, | 224 | SLEEP_SAVE_PSTR, |
| 222 | SLEEP_SAVE_CKEN, | ||
| 223 | SLEEP_SAVE_COUNT | 225 | SLEEP_SAVE_COUNT |
| 224 | }; | 226 | }; |
| 225 | 227 | ||
| 226 | 228 | ||
| 227 | static void pxa25x_cpu_pm_save(unsigned long *sleep_save) | 229 | static void pxa25x_cpu_pm_save(unsigned long *sleep_save) |
| 228 | { | 230 | { |
| 229 | SAVE(CKEN); | ||
| 230 | SAVE(PSTR); | 231 | SAVE(PSTR); |
| 231 | } | 232 | } |
| 232 | 233 | ||
| 233 | static void pxa25x_cpu_pm_restore(unsigned long *sleep_save) | 234 | static void pxa25x_cpu_pm_restore(unsigned long *sleep_save) |
| 234 | { | 235 | { |
| 235 | RESTORE(CKEN); | ||
| 236 | RESTORE(PSTR); | 236 | RESTORE(PSTR); |
| 237 | } | 237 | } |
| 238 | 238 | ||
| @@ -320,6 +320,22 @@ void __init pxa26x_init_irq(void) | |||
| 320 | } | 320 | } |
| 321 | #endif | 321 | #endif |
| 322 | 322 | ||
| 323 | static struct map_desc pxa25x_io_desc[] __initdata = { | ||
| 324 | { /* Mem Ctl */ | ||
| 325 | .virtual = SMEMC_VIRT, | ||
| 326 | .pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE), | ||
| 327 | .length = 0x00200000, | ||
| 328 | .type = MT_DEVICE | ||
| 329 | }, | ||
| 330 | }; | ||
| 331 | |||
| 332 | void __init pxa25x_map_io(void) | ||
| 333 | { | ||
| 334 | pxa_map_io(); | ||
| 335 | iotable_init(ARRAY_AND_SIZE(pxa25x_io_desc)); | ||
| 336 | pxa25x_get_clk_frequency_khz(1); | ||
| 337 | } | ||
| 338 | |||
| 323 | static struct platform_device *pxa25x_devices[] __initdata = { | 339 | static struct platform_device *pxa25x_devices[] __initdata = { |
| 324 | &pxa25x_device_udc, | 340 | &pxa25x_device_udc, |
| 325 | &pxa_device_pmu, | 341 | &pxa_device_pmu, |
| @@ -339,7 +355,9 @@ static struct sys_device pxa25x_sysdev[] = { | |||
| 339 | .cls = &pxa2xx_mfp_sysclass, | 355 | .cls = &pxa2xx_mfp_sysclass, |
| 340 | }, { | 356 | }, { |
| 341 | .cls = &pxa_gpio_sysclass, | 357 | .cls = &pxa_gpio_sysclass, |
| 342 | }, | 358 | }, { |
| 359 | .cls = &pxa2xx_clock_sysclass, | ||
| 360 | } | ||
| 343 | }; | 361 | }; |
| 344 | 362 | ||
| 345 | static int __init pxa25x_init(void) | 363 | static int __init pxa25x_init(void) |
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index d1fbf29d561c..b2130b7a7b52 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c | |||
| @@ -17,7 +17,9 @@ | |||
| 17 | #include <linux/suspend.h> | 17 | #include <linux/suspend.h> |
| 18 | #include <linux/platform_device.h> | 18 | #include <linux/platform_device.h> |
| 19 | #include <linux/sysdev.h> | 19 | #include <linux/sysdev.h> |
| 20 | #include <linux/io.h> | ||
| 20 | 21 | ||
| 22 | #include <asm/mach/map.h> | ||
| 21 | #include <mach/hardware.h> | 23 | #include <mach/hardware.h> |
| 22 | #include <asm/irq.h> | 24 | #include <asm/irq.h> |
| 23 | #include <mach/irqs.h> | 25 | #include <mach/irqs.h> |
| @@ -27,6 +29,8 @@ | |||
| 27 | #include <mach/ohci.h> | 29 | #include <mach/ohci.h> |
| 28 | #include <mach/pm.h> | 30 | #include <mach/pm.h> |
| 29 | #include <mach/dma.h> | 31 | #include <mach/dma.h> |
| 32 | #include <mach/smemc.h> | ||
| 33 | |||
| 30 | #include <plat/i2c.h> | 34 | #include <plat/i2c.h> |
| 31 | 35 | ||
| 32 | #include "generic.h" | 36 | #include "generic.h" |
| @@ -107,10 +111,9 @@ unsigned int pxa27x_get_clk_frequency_khz(int info) | |||
| 107 | } | 111 | } |
| 108 | 112 | ||
| 109 | /* | 113 | /* |
| 110 | * Return the current mem clock frequency in units of 10kHz as | 114 | * Return the current mem clock frequency as reflected by CCCR[A], B, and L |
| 111 | * reflected by CCCR[A], B, and L | ||
| 112 | */ | 115 | */ |
| 113 | unsigned int pxa27x_get_memclk_frequency_10khz(void) | 116 | static unsigned long clk_pxa27x_mem_getrate(struct clk *clk) |
| 114 | { | 117 | { |
| 115 | unsigned long ccsr, clkcfg; | 118 | unsigned long ccsr, clkcfg; |
| 116 | unsigned int l, L, m, M; | 119 | unsigned int l, L, m, M; |
| @@ -129,9 +132,15 @@ unsigned int pxa27x_get_memclk_frequency_10khz(void) | |||
| 129 | L = l * BASE_CLK; | 132 | L = l * BASE_CLK; |
| 130 | M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2)); | 133 | M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2)); |
| 131 | 134 | ||
| 132 | return (M / 10000); | 135 | return M; |
| 133 | } | 136 | } |
| 134 | 137 | ||
| 138 | static const struct clkops clk_pxa27x_mem_ops = { | ||
| 139 | .enable = clk_dummy_enable, | ||
| 140 | .disable = clk_dummy_disable, | ||
| 141 | .getrate = clk_pxa27x_mem_getrate, | ||
| 142 | }; | ||
| 143 | |||
| 135 | /* | 144 | /* |
| 136 | * Return the current LCD clock frequency in units of 10kHz as | 145 | * Return the current LCD clock frequency in units of 10kHz as |
| 137 | */ | 146 | */ |
| @@ -157,36 +166,38 @@ static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk) | |||
| 157 | } | 166 | } |
| 158 | 167 | ||
| 159 | static const struct clkops clk_pxa27x_lcd_ops = { | 168 | static const struct clkops clk_pxa27x_lcd_ops = { |
| 160 | .enable = clk_cken_enable, | 169 | .enable = clk_pxa2xx_cken_enable, |
| 161 | .disable = clk_cken_disable, | 170 | .disable = clk_pxa2xx_cken_disable, |
| 162 | .getrate = clk_pxa27x_lcd_getrate, | 171 | .getrate = clk_pxa27x_lcd_getrate, |
| 163 | }; | 172 | }; |
| 164 | 173 | ||
| 174 | static DEFINE_PXA2_CKEN(pxa27x_ffuart, FFUART, 14857000, 1); | ||
| 175 | static DEFINE_PXA2_CKEN(pxa27x_btuart, BTUART, 14857000, 1); | ||
| 176 | static DEFINE_PXA2_CKEN(pxa27x_stuart, STUART, 14857000, 1); | ||
| 177 | static DEFINE_PXA2_CKEN(pxa27x_i2s, I2S, 14682000, 0); | ||
| 178 | static DEFINE_PXA2_CKEN(pxa27x_i2c, I2C, 32842000, 0); | ||
| 179 | static DEFINE_PXA2_CKEN(pxa27x_usb, USB, 48000000, 5); | ||
| 180 | static DEFINE_PXA2_CKEN(pxa27x_mmc, MMC, 19500000, 0); | ||
| 181 | static DEFINE_PXA2_CKEN(pxa27x_ficp, FICP, 48000000, 0); | ||
| 182 | static DEFINE_PXA2_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0); | ||
| 183 | static DEFINE_PXA2_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0); | ||
| 184 | static DEFINE_PXA2_CKEN(pxa27x_keypad, KEYPAD, 32768, 0); | ||
| 185 | static DEFINE_PXA2_CKEN(pxa27x_ssp1, SSP1, 13000000, 0); | ||
| 186 | static DEFINE_PXA2_CKEN(pxa27x_ssp2, SSP2, 13000000, 0); | ||
| 187 | static DEFINE_PXA2_CKEN(pxa27x_ssp3, SSP3, 13000000, 0); | ||
| 188 | static DEFINE_PXA2_CKEN(pxa27x_pwm0, PWM0, 13000000, 0); | ||
| 189 | static DEFINE_PXA2_CKEN(pxa27x_pwm1, PWM1, 13000000, 0); | ||
| 190 | static DEFINE_PXA2_CKEN(pxa27x_ac97, AC97, 24576000, 0); | ||
| 191 | static DEFINE_PXA2_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0); | ||
| 192 | static DEFINE_PXA2_CKEN(pxa27x_msl, MSL, 48000000, 0); | ||
| 193 | static DEFINE_PXA2_CKEN(pxa27x_usim, USIM, 48000000, 0); | ||
| 194 | static DEFINE_PXA2_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0); | ||
| 195 | static DEFINE_PXA2_CKEN(pxa27x_im, IM, 0, 0); | ||
| 196 | static DEFINE_PXA2_CKEN(pxa27x_memc, MEMC, 0, 0); | ||
| 197 | |||
| 165 | static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops); | 198 | static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops); |
| 166 | static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops); | 199 | static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops); |
| 167 | static DEFINE_CKEN(pxa27x_ffuart, FFUART, 14857000, 1); | 200 | static DEFINE_CLK(pxa27x_mem, &clk_pxa27x_mem_ops, 0, 0); |
| 168 | static DEFINE_CKEN(pxa27x_btuart, BTUART, 14857000, 1); | ||
| 169 | static DEFINE_CKEN(pxa27x_stuart, STUART, 14857000, 1); | ||
| 170 | static DEFINE_CKEN(pxa27x_i2s, I2S, 14682000, 0); | ||
| 171 | static DEFINE_CKEN(pxa27x_i2c, I2C, 32842000, 0); | ||
| 172 | static DEFINE_CKEN(pxa27x_usb, USB, 48000000, 5); | ||
| 173 | static DEFINE_CKEN(pxa27x_mmc, MMC, 19500000, 0); | ||
| 174 | static DEFINE_CKEN(pxa27x_ficp, FICP, 48000000, 0); | ||
| 175 | static DEFINE_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0); | ||
| 176 | static DEFINE_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0); | ||
| 177 | static DEFINE_CKEN(pxa27x_keypad, KEYPAD, 32768, 0); | ||
| 178 | static DEFINE_CKEN(pxa27x_ssp1, SSP1, 13000000, 0); | ||
| 179 | static DEFINE_CKEN(pxa27x_ssp2, SSP2, 13000000, 0); | ||
| 180 | static DEFINE_CKEN(pxa27x_ssp3, SSP3, 13000000, 0); | ||
| 181 | static DEFINE_CKEN(pxa27x_pwm0, PWM0, 13000000, 0); | ||
| 182 | static DEFINE_CKEN(pxa27x_pwm1, PWM1, 13000000, 0); | ||
| 183 | static DEFINE_CKEN(pxa27x_ac97, AC97, 24576000, 0); | ||
| 184 | static DEFINE_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0); | ||
| 185 | static DEFINE_CKEN(pxa27x_msl, MSL, 48000000, 0); | ||
| 186 | static DEFINE_CKEN(pxa27x_usim, USIM, 48000000, 0); | ||
| 187 | static DEFINE_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0); | ||
| 188 | static DEFINE_CKEN(pxa27x_im, IM, 0, 0); | ||
| 189 | static DEFINE_CKEN(pxa27x_memc, MEMC, 0, 0); | ||
| 190 | 201 | ||
| 191 | static struct clk_lookup pxa27x_clkregs[] = { | 202 | static struct clk_lookup pxa27x_clkregs[] = { |
| 192 | INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL), | 203 | INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL), |
| @@ -215,6 +226,7 @@ static struct clk_lookup pxa27x_clkregs[] = { | |||
| 215 | INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"), | 226 | INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"), |
| 216 | INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"), | 227 | INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"), |
| 217 | INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"), | 228 | INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"), |
| 229 | INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL), | ||
| 218 | }; | 230 | }; |
| 219 | 231 | ||
| 220 | #ifdef CONFIG_PM | 232 | #ifdef CONFIG_PM |
| @@ -246,7 +258,6 @@ int __init pxa27x_set_pwrmode(unsigned int mode) | |||
| 246 | */ | 258 | */ |
| 247 | enum { | 259 | enum { |
| 248 | SLEEP_SAVE_PSTR, | 260 | SLEEP_SAVE_PSTR, |
| 249 | SLEEP_SAVE_CKEN, | ||
| 250 | SLEEP_SAVE_MDREFR, | 261 | SLEEP_SAVE_MDREFR, |
| 251 | SLEEP_SAVE_PCFR, | 262 | SLEEP_SAVE_PCFR, |
| 252 | SLEEP_SAVE_COUNT | 263 | SLEEP_SAVE_COUNT |
| @@ -254,21 +265,19 @@ enum { | |||
| 254 | 265 | ||
| 255 | void pxa27x_cpu_pm_save(unsigned long *sleep_save) | 266 | void pxa27x_cpu_pm_save(unsigned long *sleep_save) |
| 256 | { | 267 | { |
| 257 | SAVE(MDREFR); | 268 | sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR); |
| 258 | SAVE(PCFR); | 269 | SAVE(PCFR); |
| 259 | 270 | ||
| 260 | SAVE(CKEN); | ||
| 261 | SAVE(PSTR); | 271 | SAVE(PSTR); |
| 262 | } | 272 | } |
| 263 | 273 | ||
| 264 | void pxa27x_cpu_pm_restore(unsigned long *sleep_save) | 274 | void pxa27x_cpu_pm_restore(unsigned long *sleep_save) |
| 265 | { | 275 | { |
| 266 | RESTORE(MDREFR); | 276 | __raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR); |
| 267 | RESTORE(PCFR); | 277 | RESTORE(PCFR); |
| 268 | 278 | ||
| 269 | PSSR = PSSR_RDH | PSSR_PH; | 279 | PSSR = PSSR_RDH | PSSR_PH; |
| 270 | 280 | ||
| 271 | RESTORE(CKEN); | ||
| 272 | RESTORE(PSTR); | 281 | RESTORE(PSTR); |
| 273 | } | 282 | } |
| 274 | 283 | ||
| @@ -370,6 +379,27 @@ void __init pxa27x_init_irq(void) | |||
| 370 | pxa_init_gpio(IRQ_GPIO_2_x, 2, 120, pxa27x_set_wake); | 379 | pxa_init_gpio(IRQ_GPIO_2_x, 2, 120, pxa27x_set_wake); |
| 371 | } | 380 | } |
| 372 | 381 | ||
| 382 | static struct map_desc pxa27x_io_desc[] __initdata = { | ||
| 383 | { /* Mem Ctl */ | ||
| 384 | .virtual = SMEMC_VIRT, | ||
| 385 | .pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE), | ||
| 386 | .length = 0x00200000, | ||
| 387 | .type = MT_DEVICE | ||
| 388 | }, { /* IMem ctl */ | ||
| 389 | .virtual = 0xfe000000, | ||
| 390 | .pfn = __phys_to_pfn(0x58000000), | ||
| 391 | .length = 0x00100000, | ||
| 392 | .type = MT_DEVICE | ||
| 393 | }, | ||
| 394 | }; | ||
| 395 | |||
| 396 | void __init pxa27x_map_io(void) | ||
| 397 | { | ||
| 398 | pxa_map_io(); | ||
| 399 | iotable_init(ARRAY_AND_SIZE(pxa27x_io_desc)); | ||
| 400 | pxa27x_get_clk_frequency_khz(1); | ||
| 401 | } | ||
| 402 | |||
| 373 | /* | 403 | /* |
| 374 | * device registration specific to PXA27x. | 404 | * device registration specific to PXA27x. |
| 375 | */ | 405 | */ |
| @@ -405,7 +435,9 @@ static struct sys_device pxa27x_sysdev[] = { | |||
| 405 | .cls = &pxa2xx_mfp_sysclass, | 435 | .cls = &pxa2xx_mfp_sysclass, |
| 406 | }, { | 436 | }, { |
| 407 | .cls = &pxa_gpio_sysclass, | 437 | .cls = &pxa_gpio_sysclass, |
| 408 | }, | 438 | }, { |
| 439 | .cls = &pxa2xx_clock_sysclass, | ||
| 440 | } | ||
| 409 | }; | 441 | }; |
| 410 | 442 | ||
| 411 | static int __init pxa27x_init(void) | 443 | static int __init pxa27x_init(void) |
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index d1c747cdacf8..e14818f5d950 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c | |||
| @@ -22,6 +22,7 @@ | |||
| 22 | #include <linux/io.h> | 22 | #include <linux/io.h> |
| 23 | #include <linux/sysdev.h> | 23 | #include <linux/sysdev.h> |
| 24 | 24 | ||
| 25 | #include <asm/mach/map.h> | ||
| 25 | #include <mach/hardware.h> | 26 | #include <mach/hardware.h> |
| 26 | #include <mach/gpio.h> | 27 | #include <mach/gpio.h> |
| 27 | #include <mach/pxa3xx-regs.h> | 28 | #include <mach/pxa3xx-regs.h> |
| @@ -30,193 +31,16 @@ | |||
| 30 | #include <mach/pm.h> | 31 | #include <mach/pm.h> |
| 31 | #include <mach/dma.h> | 32 | #include <mach/dma.h> |
| 32 | #include <mach/regs-intc.h> | 33 | #include <mach/regs-intc.h> |
| 34 | #include <mach/smemc.h> | ||
| 33 | #include <plat/i2c.h> | 35 | #include <plat/i2c.h> |
| 34 | 36 | ||
| 35 | #include "generic.h" | 37 | #include "generic.h" |
| 36 | #include "devices.h" | 38 | #include "devices.h" |
| 37 | #include "clock.h" | 39 | #include "clock.h" |
| 38 | 40 | ||
| 39 | /* Crystal clock: 13MHz */ | ||
| 40 | #define BASE_CLK 13000000 | ||
| 41 | |||
| 42 | /* Ring Oscillator Clock: 60MHz */ | ||
| 43 | #define RO_CLK 60000000 | ||
| 44 | |||
| 45 | #define ACCR_D0CS (1 << 26) | ||
| 46 | #define ACCR_PCCE (1 << 11) | ||
| 47 | |||
| 48 | #define PECR_IE(n) ((1 << ((n) * 2)) << 28) | 41 | #define PECR_IE(n) ((1 << ((n) * 2)) << 28) |
| 49 | #define PECR_IS(n) ((1 << ((n) * 2)) << 29) | 42 | #define PECR_IS(n) ((1 << ((n) * 2)) << 29) |
| 50 | 43 | ||
| 51 | /* crystal frequency to static memory controller multiplier (SMCFS) */ | ||
| 52 | static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; | ||
| 53 | |||
| 54 | /* crystal frequency to HSIO bus frequency multiplier (HSS) */ | ||
| 55 | static unsigned char hss_mult[4] = { 8, 12, 16, 24 }; | ||
| 56 | |||
| 57 | /* | ||
| 58 | * Get the clock frequency as reflected by CCSR and the turbo flag. | ||
| 59 | * We assume these values have been applied via a fcs. | ||
| 60 | * If info is not 0 we also display the current settings. | ||
| 61 | */ | ||
| 62 | unsigned int pxa3xx_get_clk_frequency_khz(int info) | ||
| 63 | { | ||
| 64 | unsigned long acsr, xclkcfg; | ||
| 65 | unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS; | ||
| 66 | |||
| 67 | /* Read XCLKCFG register turbo bit */ | ||
| 68 | __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); | ||
| 69 | t = xclkcfg & 0x1; | ||
| 70 | |||
| 71 | acsr = ACSR; | ||
| 72 | |||
| 73 | xl = acsr & 0x1f; | ||
| 74 | xn = (acsr >> 8) & 0x7; | ||
| 75 | hss = (acsr >> 14) & 0x3; | ||
| 76 | |||
| 77 | XL = xl * BASE_CLK; | ||
| 78 | XN = xn * XL; | ||
| 79 | |||
| 80 | ro = acsr & ACCR_D0CS; | ||
| 81 | |||
| 82 | CLK = (ro) ? RO_CLK : ((t) ? XN : XL); | ||
| 83 | HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK; | ||
| 84 | |||
| 85 | if (info) { | ||
| 86 | pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n", | ||
| 87 | RO_CLK / 1000000, (RO_CLK % 1000000) / 10000, | ||
| 88 | (ro) ? "" : "in"); | ||
| 89 | pr_info("Run Mode clock: %d.%02dMHz (*%d)\n", | ||
| 90 | XL / 1000000, (XL % 1000000) / 10000, xl); | ||
| 91 | pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n", | ||
| 92 | XN / 1000000, (XN % 1000000) / 10000, xn, | ||
| 93 | (t) ? "" : "in"); | ||
| 94 | pr_info("HSIO bus clock: %d.%02dMHz\n", | ||
| 95 | HSS / 1000000, (HSS % 1000000) / 10000); | ||
| 96 | } | ||
| 97 | |||
| 98 | return CLK / 1000; | ||
| 99 | } | ||
| 100 | |||
| 101 | void pxa3xx_clear_reset_status(unsigned int mask) | ||
| 102 | { | ||
| 103 | /* RESET_STATUS_* has a 1:1 mapping with ARSR */ | ||
| 104 | ARSR = mask; | ||
| 105 | } | ||
| 106 | |||
| 107 | /* | ||
| 108 | * Return the current AC97 clock frequency. | ||
| 109 | */ | ||
| 110 | static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk) | ||
| 111 | { | ||
| 112 | unsigned long rate = 312000000; | ||
| 113 | unsigned long ac97_div; | ||
| 114 | |||
| 115 | ac97_div = AC97_DIV; | ||
| 116 | |||
| 117 | /* This may loose precision for some rates but won't for the | ||
| 118 | * standard 24.576MHz. | ||
| 119 | */ | ||
| 120 | rate /= (ac97_div >> 12) & 0x7fff; | ||
| 121 | rate *= (ac97_div & 0xfff); | ||
| 122 | |||
| 123 | return rate; | ||
| 124 | } | ||
| 125 | |||
| 126 | /* | ||
| 127 | * Return the current HSIO bus clock frequency | ||
| 128 | */ | ||
| 129 | static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) | ||
| 130 | { | ||
| 131 | unsigned long acsr; | ||
| 132 | unsigned int hss, hsio_clk; | ||
| 133 | |||
| 134 | acsr = ACSR; | ||
| 135 | |||
| 136 | hss = (acsr >> 14) & 0x3; | ||
| 137 | hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK; | ||
| 138 | |||
| 139 | return hsio_clk; | ||
| 140 | } | ||
| 141 | |||
| 142 | void clk_pxa3xx_cken_enable(struct clk *clk) | ||
| 143 | { | ||
| 144 | unsigned long mask = 1ul << (clk->cken & 0x1f); | ||
| 145 | |||
| 146 | if (clk->cken < 32) | ||
| 147 | CKENA |= mask; | ||
| 148 | else | ||
| 149 | CKENB |= mask; | ||
| 150 | } | ||
| 151 | |||
| 152 | void clk_pxa3xx_cken_disable(struct clk *clk) | ||
| 153 | { | ||
| 154 | unsigned long mask = 1ul << (clk->cken & 0x1f); | ||
| 155 | |||
| 156 | if (clk->cken < 32) | ||
| 157 | CKENA &= ~mask; | ||
| 158 | else | ||
| 159 | CKENB &= ~mask; | ||
| 160 | } | ||
| 161 | |||
| 162 | const struct clkops clk_pxa3xx_cken_ops = { | ||
| 163 | .enable = clk_pxa3xx_cken_enable, | ||
| 164 | .disable = clk_pxa3xx_cken_disable, | ||
| 165 | }; | ||
| 166 | |||
| 167 | static const struct clkops clk_pxa3xx_hsio_ops = { | ||
| 168 | .enable = clk_pxa3xx_cken_enable, | ||
| 169 | .disable = clk_pxa3xx_cken_disable, | ||
| 170 | .getrate = clk_pxa3xx_hsio_getrate, | ||
| 171 | }; | ||
| 172 | |||
| 173 | static const struct clkops clk_pxa3xx_ac97_ops = { | ||
| 174 | .enable = clk_pxa3xx_cken_enable, | ||
| 175 | .disable = clk_pxa3xx_cken_disable, | ||
| 176 | .getrate = clk_pxa3xx_ac97_getrate, | ||
| 177 | }; | ||
| 178 | |||
| 179 | static void clk_pout_enable(struct clk *clk) | ||
| 180 | { | ||
| 181 | OSCC |= OSCC_PEN; | ||
| 182 | } | ||
| 183 | |||
| 184 | static void clk_pout_disable(struct clk *clk) | ||
| 185 | { | ||
| 186 | OSCC &= ~OSCC_PEN; | ||
| 187 | } | ||
| 188 | |||
| 189 | static const struct clkops clk_pout_ops = { | ||
| 190 | .enable = clk_pout_enable, | ||
| 191 | .disable = clk_pout_disable, | ||
| 192 | }; | ||
| 193 | |||
| 194 | static void clk_dummy_enable(struct clk *clk) | ||
| 195 | { | ||
| 196 | } | ||
| 197 | |||
| 198 | static void clk_dummy_disable(struct clk *clk) | ||
| 199 | { | ||
| 200 | } | ||
| 201 | |||
| 202 | static const struct clkops clk_dummy_ops = { | ||
| 203 | .enable = clk_dummy_enable, | ||
| 204 | .disable = clk_dummy_disable, | ||
| 205 | }; | ||
| 206 | |||
| 207 | static struct clk clk_pxa3xx_pout = { | ||
| 208 | .ops = &clk_pout_ops, | ||
| 209 | .rate = 13000000, | ||
| 210 | .delay = 70, | ||
| 211 | }; | ||
| 212 | |||
| 213 | static struct clk clk_dummy = { | ||
| 214 | .ops = &clk_dummy_ops, | ||
| 215 | }; | ||
| 216 | |||
| 217 | static DEFINE_PXA3_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops); | ||
| 218 | static DEFINE_PXA3_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops); | ||
| 219 | static DEFINE_PXA3_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops); | ||
| 220 | static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1); | 44 | static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1); |
| 221 | static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1); | 45 | static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1); |
| 222 | static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); | 46 | static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); |
| @@ -234,6 +58,12 @@ static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0); | |||
| 234 | static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0); | 58 | static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0); |
| 235 | static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0); | 59 | static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0); |
| 236 | 60 | ||
| 61 | static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops); | ||
| 62 | static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops); | ||
| 63 | static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops); | ||
| 64 | static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops); | ||
| 65 | static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70); | ||
| 66 | |||
| 237 | static struct clk_lookup pxa3xx_clkregs[] = { | 67 | static struct clk_lookup pxa3xx_clkregs[] = { |
| 238 | INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"), | 68 | INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"), |
| 239 | /* Power I2C clock is always on */ | 69 | /* Power I2C clock is always on */ |
| @@ -258,6 +88,7 @@ static struct clk_lookup pxa3xx_clkregs[] = { | |||
| 258 | INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL), | 88 | INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL), |
| 259 | INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL), | 89 | INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL), |
| 260 | INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL), | 90 | INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL), |
| 91 | INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL), | ||
| 261 | }; | 92 | }; |
| 262 | 93 | ||
| 263 | #ifdef CONFIG_PM | 94 | #ifdef CONFIG_PM |
| @@ -268,30 +99,6 @@ static struct clk_lookup pxa3xx_clkregs[] = { | |||
| 268 | static void __iomem *sram; | 99 | static void __iomem *sram; |
| 269 | static unsigned long wakeup_src; | 100 | static unsigned long wakeup_src; |
| 270 | 101 | ||
| 271 | #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x | ||
| 272 | #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] | ||
| 273 | |||
| 274 | enum { SLEEP_SAVE_CKENA, | ||
| 275 | SLEEP_SAVE_CKENB, | ||
| 276 | SLEEP_SAVE_ACCR, | ||
| 277 | |||
| 278 | SLEEP_SAVE_COUNT, | ||
| 279 | }; | ||
| 280 | |||
| 281 | static void pxa3xx_cpu_pm_save(unsigned long *sleep_save) | ||
| 282 | { | ||
| 283 | SAVE(CKENA); | ||
| 284 | SAVE(CKENB); | ||
| 285 | SAVE(ACCR); | ||
| 286 | } | ||
| 287 | |||
| 288 | static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save) | ||
| 289 | { | ||
| 290 | RESTORE(ACCR); | ||
| 291 | RESTORE(CKENA); | ||
| 292 | RESTORE(CKENB); | ||
| 293 | } | ||
| 294 | |||
| 295 | /* | 102 | /* |
| 296 | * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic | 103 | * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic |
| 297 | * memory controller has to be reinitialised, so we place some code | 104 | * memory controller has to be reinitialised, so we place some code |
| @@ -390,9 +197,6 @@ static int pxa3xx_cpu_pm_valid(suspend_state_t state) | |||
| 390 | } | 197 | } |
| 391 | 198 | ||
| 392 | static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { | 199 | static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { |
| 393 | .save_count = SLEEP_SAVE_COUNT, | ||
| 394 | .save = pxa3xx_cpu_pm_save, | ||
| 395 | .restore = pxa3xx_cpu_pm_restore, | ||
| 396 | .valid = pxa3xx_cpu_pm_valid, | 200 | .valid = pxa3xx_cpu_pm_valid, |
| 397 | .enter = pxa3xx_cpu_pm_enter, | 201 | .enter = pxa3xx_cpu_pm_enter, |
| 398 | }; | 202 | }; |
| @@ -580,6 +384,22 @@ void __init pxa3xx_init_irq(void) | |||
| 580 | pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL); | 384 | pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL); |
| 581 | } | 385 | } |
| 582 | 386 | ||
| 387 | static struct map_desc pxa3xx_io_desc[] __initdata = { | ||
| 388 | { /* Mem Ctl */ | ||
| 389 | .virtual = SMEMC_VIRT, | ||
| 390 | .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE), | ||
| 391 | .length = 0x00200000, | ||
| 392 | .type = MT_DEVICE | ||
| 393 | } | ||
| 394 | }; | ||
| 395 | |||
| 396 | void __init pxa3xx_map_io(void) | ||
| 397 | { | ||
| 398 | pxa_map_io(); | ||
| 399 | iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc)); | ||
| 400 | pxa3xx_get_clk_frequency_khz(1); | ||
| 401 | } | ||
| 402 | |||
| 583 | /* | 403 | /* |
| 584 | * device registration specific to PXA3xx. | 404 | * device registration specific to PXA3xx. |
| 585 | */ | 405 | */ |
| @@ -615,7 +435,9 @@ static struct sys_device pxa3xx_sysdev[] = { | |||
| 615 | .cls = &pxa3xx_mfp_sysclass, | 435 | .cls = &pxa3xx_mfp_sysclass, |
| 616 | }, { | 436 | }, { |
| 617 | .cls = &pxa_gpio_sysclass, | 437 | .cls = &pxa_gpio_sysclass, |
| 618 | }, | 438 | }, { |
| 439 | .cls = &pxa3xx_clock_sysclass, | ||
| 440 | } | ||
| 619 | }; | 441 | }; |
| 620 | 442 | ||
| 621 | static int __init pxa3xx_init(void) | 443 | static int __init pxa3xx_init(void) |
diff --git a/arch/arm/mach-pxa/pxa930.c b/arch/arm/mach-pxa/pxa930.c index 7d29dd3af79d..8aeacf908784 100644 --- a/arch/arm/mach-pxa/pxa930.c +++ b/arch/arm/mach-pxa/pxa930.c | |||
| @@ -192,7 +192,7 @@ static struct mfp_addr_map pxa935_mfp_addr_map[] __initdata = { | |||
| 192 | 192 | ||
| 193 | static int __init pxa930_init(void) | 193 | static int __init pxa930_init(void) |
| 194 | { | 194 | { |
| 195 | if (cpu_is_pxa930() || cpu_is_pxa935() || cpu_is_pxa950()) { | 195 | if (cpu_is_pxa93x()) { |
| 196 | mfp_init_base(io_p2v(MFPR_BASE)); | 196 | mfp_init_base(io_p2v(MFPR_BASE)); |
| 197 | mfp_init_addr(pxa930_mfp_addr_map); | 197 | mfp_init_addr(pxa930_mfp_addr_map); |
| 198 | } | 198 | } |
diff --git a/arch/arm/mach-pxa/pxa95x.c b/arch/arm/mach-pxa/pxa95x.c new file mode 100644 index 000000000000..437980f72710 --- /dev/null +++ b/arch/arm/mach-pxa/pxa95x.c | |||
| @@ -0,0 +1,308 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-pxa/pxa95x.c | ||
| 3 | * | ||
| 4 | * code specific to PXA95x aka MGx | ||
| 5 | * | ||
| 6 | * Copyright (C) 2009-2010 Marvell International Ltd. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/module.h> | ||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/init.h> | ||
| 16 | #include <linux/pm.h> | ||
| 17 | #include <linux/platform_device.h> | ||
| 18 | #include <linux/irq.h> | ||
| 19 | #include <linux/io.h> | ||
| 20 | #include <linux/sysdev.h> | ||
| 21 | |||
| 22 | #include <mach/hardware.h> | ||
| 23 | #include <mach/gpio.h> | ||
| 24 | #include <mach/pxa3xx-regs.h> | ||
| 25 | #include <mach/pxa930.h> | ||
| 26 | #include <mach/reset.h> | ||
| 27 | #include <mach/pm.h> | ||
| 28 | #include <mach/dma.h> | ||
| 29 | #include <mach/regs-intc.h> | ||
| 30 | #include <plat/i2c.h> | ||
| 31 | |||
| 32 | #include "generic.h" | ||
| 33 | #include "devices.h" | ||
| 34 | #include "clock.h" | ||
| 35 | |||
| 36 | static struct mfp_addr_map pxa95x_mfp_addr_map[] __initdata = { | ||
| 37 | |||
| 38 | MFP_ADDR(GPIO0, 0x02e0), | ||
| 39 | MFP_ADDR(GPIO1, 0x02dc), | ||
| 40 | MFP_ADDR(GPIO2, 0x02e8), | ||
| 41 | MFP_ADDR(GPIO3, 0x02d8), | ||
| 42 | MFP_ADDR(GPIO4, 0x02e4), | ||
| 43 | MFP_ADDR(GPIO5, 0x02ec), | ||
| 44 | MFP_ADDR(GPIO6, 0x02f8), | ||
| 45 | MFP_ADDR(GPIO7, 0x02fc), | ||
| 46 | MFP_ADDR(GPIO8, 0x0300), | ||
| 47 | MFP_ADDR(GPIO9, 0x02d4), | ||
| 48 | MFP_ADDR(GPIO10, 0x02f4), | ||
| 49 | MFP_ADDR(GPIO11, 0x02f0), | ||
| 50 | MFP_ADDR(GPIO12, 0x0304), | ||
| 51 | MFP_ADDR(GPIO13, 0x0310), | ||
| 52 | MFP_ADDR(GPIO14, 0x0308), | ||
| 53 | MFP_ADDR(GPIO15, 0x030c), | ||
| 54 | MFP_ADDR(GPIO16, 0x04e8), | ||
| 55 | MFP_ADDR(GPIO17, 0x04f4), | ||
| 56 | MFP_ADDR(GPIO18, 0x04f8), | ||
| 57 | MFP_ADDR(GPIO19, 0x04fc), | ||
| 58 | MFP_ADDR(GPIO20, 0x0518), | ||
| 59 | MFP_ADDR(GPIO21, 0x051c), | ||
| 60 | MFP_ADDR(GPIO22, 0x04ec), | ||
| 61 | MFP_ADDR(GPIO23, 0x0500), | ||
| 62 | MFP_ADDR(GPIO24, 0x04f0), | ||
| 63 | MFP_ADDR(GPIO25, 0x0504), | ||
| 64 | MFP_ADDR(GPIO26, 0x0510), | ||
| 65 | MFP_ADDR(GPIO27, 0x0514), | ||
| 66 | MFP_ADDR(GPIO28, 0x0520), | ||
| 67 | MFP_ADDR(GPIO29, 0x0600), | ||
| 68 | MFP_ADDR(GPIO30, 0x0618), | ||
| 69 | MFP_ADDR(GPIO31, 0x0610), | ||
| 70 | MFP_ADDR(GPIO32, 0x060c), | ||
| 71 | MFP_ADDR(GPIO33, 0x061c), | ||
| 72 | MFP_ADDR(GPIO34, 0x0620), | ||
| 73 | MFP_ADDR(GPIO35, 0x0628), | ||
| 74 | MFP_ADDR(GPIO36, 0x062c), | ||
| 75 | MFP_ADDR(GPIO37, 0x0630), | ||
| 76 | MFP_ADDR(GPIO38, 0x0634), | ||
| 77 | MFP_ADDR(GPIO39, 0x0638), | ||
| 78 | MFP_ADDR(GPIO40, 0x063c), | ||
| 79 | MFP_ADDR(GPIO41, 0x0614), | ||
| 80 | MFP_ADDR(GPIO42, 0x0624), | ||
| 81 | MFP_ADDR(GPIO43, 0x0608), | ||
| 82 | MFP_ADDR(GPIO44, 0x0604), | ||
| 83 | MFP_ADDR(GPIO45, 0x050c), | ||
| 84 | MFP_ADDR(GPIO46, 0x0508), | ||
| 85 | MFP_ADDR(GPIO47, 0x02bc), | ||
| 86 | MFP_ADDR(GPIO48, 0x02b4), | ||
| 87 | MFP_ADDR(GPIO49, 0x02b8), | ||
| 88 | MFP_ADDR(GPIO50, 0x02c8), | ||
| 89 | MFP_ADDR(GPIO51, 0x02c0), | ||
| 90 | MFP_ADDR(GPIO52, 0x02c4), | ||
| 91 | MFP_ADDR(GPIO53, 0x02d0), | ||
| 92 | MFP_ADDR(GPIO54, 0x02cc), | ||
| 93 | MFP_ADDR(GPIO55, 0x029c), | ||
| 94 | MFP_ADDR(GPIO56, 0x02a0), | ||
| 95 | MFP_ADDR(GPIO57, 0x0294), | ||
| 96 | MFP_ADDR(GPIO58, 0x0298), | ||
| 97 | MFP_ADDR(GPIO59, 0x02a4), | ||
| 98 | MFP_ADDR(GPIO60, 0x02a8), | ||
| 99 | MFP_ADDR(GPIO61, 0x02b0), | ||
| 100 | MFP_ADDR(GPIO62, 0x02ac), | ||
| 101 | MFP_ADDR(GPIO63, 0x0640), | ||
| 102 | MFP_ADDR(GPIO64, 0x065c), | ||
| 103 | MFP_ADDR(GPIO65, 0x0648), | ||
| 104 | MFP_ADDR(GPIO66, 0x0644), | ||
| 105 | MFP_ADDR(GPIO67, 0x0674), | ||
| 106 | MFP_ADDR(GPIO68, 0x0658), | ||
| 107 | MFP_ADDR(GPIO69, 0x0654), | ||
| 108 | MFP_ADDR(GPIO70, 0x0660), | ||
| 109 | MFP_ADDR(GPIO71, 0x0668), | ||
| 110 | MFP_ADDR(GPIO72, 0x0664), | ||
| 111 | MFP_ADDR(GPIO73, 0x0650), | ||
| 112 | MFP_ADDR(GPIO74, 0x066c), | ||
| 113 | MFP_ADDR(GPIO75, 0x064c), | ||
| 114 | MFP_ADDR(GPIO76, 0x0670), | ||
| 115 | MFP_ADDR(GPIO77, 0x0678), | ||
| 116 | MFP_ADDR(GPIO78, 0x067c), | ||
| 117 | MFP_ADDR(GPIO79, 0x0694), | ||
| 118 | MFP_ADDR(GPIO80, 0x069c), | ||
| 119 | MFP_ADDR(GPIO81, 0x06a0), | ||
| 120 | MFP_ADDR(GPIO82, 0x06a4), | ||
| 121 | MFP_ADDR(GPIO83, 0x0698), | ||
| 122 | MFP_ADDR(GPIO84, 0x06bc), | ||
| 123 | MFP_ADDR(GPIO85, 0x06b4), | ||
| 124 | MFP_ADDR(GPIO86, 0x06b0), | ||
| 125 | MFP_ADDR(GPIO87, 0x06c0), | ||
| 126 | MFP_ADDR(GPIO88, 0x06c4), | ||
| 127 | MFP_ADDR(GPIO89, 0x06ac), | ||
| 128 | MFP_ADDR(GPIO90, 0x0680), | ||
| 129 | MFP_ADDR(GPIO91, 0x0684), | ||
| 130 | MFP_ADDR(GPIO92, 0x0688), | ||
| 131 | MFP_ADDR(GPIO93, 0x0690), | ||
| 132 | MFP_ADDR(GPIO94, 0x068c), | ||
| 133 | MFP_ADDR(GPIO95, 0x06a8), | ||
| 134 | MFP_ADDR(GPIO96, 0x06b8), | ||
| 135 | MFP_ADDR(GPIO97, 0x0410), | ||
| 136 | MFP_ADDR(GPIO98, 0x0418), | ||
| 137 | MFP_ADDR(GPIO99, 0x041c), | ||
| 138 | MFP_ADDR(GPIO100, 0x0414), | ||
| 139 | MFP_ADDR(GPIO101, 0x0408), | ||
| 140 | MFP_ADDR(GPIO102, 0x0324), | ||
| 141 | MFP_ADDR(GPIO103, 0x040c), | ||
| 142 | MFP_ADDR(GPIO104, 0x0400), | ||
| 143 | MFP_ADDR(GPIO105, 0x0328), | ||
| 144 | MFP_ADDR(GPIO106, 0x0404), | ||
| 145 | |||
| 146 | MFP_ADDR(GPIO159, 0x0524), | ||
| 147 | MFP_ADDR(GPIO163, 0x0534), | ||
| 148 | MFP_ADDR(GPIO167, 0x0544), | ||
| 149 | MFP_ADDR(GPIO168, 0x0548), | ||
| 150 | MFP_ADDR(GPIO169, 0x054c), | ||
| 151 | MFP_ADDR(GPIO170, 0x0550), | ||
| 152 | MFP_ADDR(GPIO171, 0x0554), | ||
| 153 | MFP_ADDR(GPIO172, 0x0558), | ||
| 154 | MFP_ADDR(GPIO173, 0x055c), | ||
| 155 | |||
| 156 | MFP_ADDR(nXCVREN, 0x0204), | ||
| 157 | MFP_ADDR(DF_CLE_nOE, 0x020c), | ||
| 158 | MFP_ADDR(DF_nADV1_ALE, 0x0218), | ||
| 159 | MFP_ADDR(DF_SCLK_E, 0x0214), | ||
| 160 | MFP_ADDR(DF_SCLK_S, 0x0210), | ||
| 161 | MFP_ADDR(nBE0, 0x021c), | ||
| 162 | MFP_ADDR(nBE1, 0x0220), | ||
| 163 | MFP_ADDR(DF_nADV2_ALE, 0x0224), | ||
| 164 | MFP_ADDR(DF_INT_RnB, 0x0228), | ||
| 165 | MFP_ADDR(DF_nCS0, 0x022c), | ||
| 166 | MFP_ADDR(DF_nCS1, 0x0230), | ||
| 167 | MFP_ADDR(nLUA, 0x0254), | ||
| 168 | MFP_ADDR(nLLA, 0x0258), | ||
| 169 | MFP_ADDR(DF_nWE, 0x0234), | ||
| 170 | MFP_ADDR(DF_nRE_nOE, 0x0238), | ||
| 171 | MFP_ADDR(DF_ADDR0, 0x024c), | ||
| 172 | MFP_ADDR(DF_ADDR1, 0x0250), | ||
| 173 | MFP_ADDR(DF_ADDR2, 0x025c), | ||
| 174 | MFP_ADDR(DF_ADDR3, 0x0260), | ||
| 175 | MFP_ADDR(DF_IO0, 0x023c), | ||
| 176 | MFP_ADDR(DF_IO1, 0x0240), | ||
| 177 | MFP_ADDR(DF_IO2, 0x0244), | ||
| 178 | MFP_ADDR(DF_IO3, 0x0248), | ||
| 179 | MFP_ADDR(DF_IO4, 0x0264), | ||
| 180 | MFP_ADDR(DF_IO5, 0x0268), | ||
| 181 | MFP_ADDR(DF_IO6, 0x026c), | ||
| 182 | MFP_ADDR(DF_IO7, 0x0270), | ||
| 183 | MFP_ADDR(DF_IO8, 0x0274), | ||
| 184 | MFP_ADDR(DF_IO9, 0x0278), | ||
| 185 | MFP_ADDR(DF_IO10, 0x027c), | ||
| 186 | MFP_ADDR(DF_IO11, 0x0280), | ||
| 187 | MFP_ADDR(DF_IO12, 0x0284), | ||
| 188 | MFP_ADDR(DF_IO13, 0x0288), | ||
| 189 | MFP_ADDR(DF_IO14, 0x028c), | ||
| 190 | MFP_ADDR(DF_IO15, 0x0290), | ||
| 191 | |||
| 192 | MFP_ADDR(GSIM_UIO, 0x0314), | ||
| 193 | MFP_ADDR(GSIM_UCLK, 0x0318), | ||
| 194 | MFP_ADDR(GSIM_UDET, 0x031c), | ||
| 195 | MFP_ADDR(GSIM_nURST, 0x0320), | ||
| 196 | |||
| 197 | MFP_ADDR(PMIC_INT, 0x06c8), | ||
| 198 | |||
| 199 | MFP_ADDR(RDY, 0x0200), | ||
| 200 | |||
| 201 | MFP_ADDR_END, | ||
| 202 | }; | ||
| 203 | |||
| 204 | static DEFINE_CK(pxa95x_lcd, LCD, &clk_pxa3xx_hsio_ops); | ||
| 205 | static DEFINE_CLK(pxa95x_pout, &clk_pxa3xx_pout_ops, 13000000, 70); | ||
| 206 | static DEFINE_PXA3_CKEN(pxa95x_ffuart, FFUART, 14857000, 1); | ||
| 207 | static DEFINE_PXA3_CKEN(pxa95x_btuart, BTUART, 14857000, 1); | ||
| 208 | static DEFINE_PXA3_CKEN(pxa95x_stuart, STUART, 14857000, 1); | ||
| 209 | static DEFINE_PXA3_CKEN(pxa95x_i2c, I2C, 32842000, 0); | ||
| 210 | static DEFINE_PXA3_CKEN(pxa95x_keypad, KEYPAD, 32768, 0); | ||
| 211 | static DEFINE_PXA3_CKEN(pxa95x_ssp1, SSP1, 13000000, 0); | ||
| 212 | static DEFINE_PXA3_CKEN(pxa95x_ssp2, SSP2, 13000000, 0); | ||
| 213 | static DEFINE_PXA3_CKEN(pxa95x_ssp3, SSP3, 13000000, 0); | ||
| 214 | static DEFINE_PXA3_CKEN(pxa95x_ssp4, SSP4, 13000000, 0); | ||
| 215 | static DEFINE_PXA3_CKEN(pxa95x_pwm0, PWM0, 13000000, 0); | ||
| 216 | static DEFINE_PXA3_CKEN(pxa95x_pwm1, PWM1, 13000000, 0); | ||
| 217 | |||
| 218 | static struct clk_lookup pxa95x_clkregs[] = { | ||
| 219 | INIT_CLKREG(&clk_pxa95x_pout, NULL, "CLK_POUT"), | ||
| 220 | /* Power I2C clock is always on */ | ||
| 221 | INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL), | ||
| 222 | INIT_CLKREG(&clk_pxa95x_lcd, "pxa2xx-fb", NULL), | ||
| 223 | INIT_CLKREG(&clk_pxa95x_ffuart, "pxa2xx-uart.0", NULL), | ||
| 224 | INIT_CLKREG(&clk_pxa95x_btuart, "pxa2xx-uart.1", NULL), | ||
| 225 | INIT_CLKREG(&clk_pxa95x_stuart, "pxa2xx-uart.2", NULL), | ||
| 226 | INIT_CLKREG(&clk_pxa95x_stuart, "pxa2xx-ir", "UARTCLK"), | ||
| 227 | INIT_CLKREG(&clk_pxa95x_i2c, "pxa2xx-i2c.0", NULL), | ||
| 228 | INIT_CLKREG(&clk_pxa95x_keypad, "pxa27x-keypad", NULL), | ||
| 229 | INIT_CLKREG(&clk_pxa95x_ssp1, "pxa27x-ssp.0", NULL), | ||
| 230 | INIT_CLKREG(&clk_pxa95x_ssp2, "pxa27x-ssp.1", NULL), | ||
| 231 | INIT_CLKREG(&clk_pxa95x_ssp3, "pxa27x-ssp.2", NULL), | ||
| 232 | INIT_CLKREG(&clk_pxa95x_ssp4, "pxa27x-ssp.3", NULL), | ||
| 233 | INIT_CLKREG(&clk_pxa95x_pwm0, "pxa27x-pwm.0", NULL), | ||
| 234 | INIT_CLKREG(&clk_pxa95x_pwm1, "pxa27x-pwm.1", NULL), | ||
| 235 | }; | ||
| 236 | |||
| 237 | void __init pxa95x_init_irq(void) | ||
| 238 | { | ||
| 239 | pxa_init_irq(96, NULL); | ||
| 240 | pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL); | ||
| 241 | } | ||
| 242 | |||
| 243 | /* | ||
| 244 | * device registration specific to PXA93x. | ||
| 245 | */ | ||
| 246 | |||
| 247 | void __init pxa95x_set_i2c_power_info(struct i2c_pxa_platform_data *info) | ||
| 248 | { | ||
| 249 | pxa_register_device(&pxa3xx_device_i2c_power, info); | ||
| 250 | } | ||
| 251 | |||
| 252 | static struct platform_device *devices[] __initdata = { | ||
| 253 | &sa1100_device_rtc, | ||
| 254 | &pxa_device_rtc, | ||
| 255 | &pxa27x_device_ssp1, | ||
| 256 | &pxa27x_device_ssp2, | ||
| 257 | &pxa27x_device_ssp3, | ||
| 258 | &pxa3xx_device_ssp4, | ||
| 259 | &pxa27x_device_pwm0, | ||
| 260 | &pxa27x_device_pwm1, | ||
| 261 | }; | ||
| 262 | |||
| 263 | static struct sys_device pxa95x_sysdev[] = { | ||
| 264 | { | ||
| 265 | .cls = &pxa_irq_sysclass, | ||
| 266 | }, { | ||
| 267 | .cls = &pxa_gpio_sysclass, | ||
| 268 | }, { | ||
| 269 | .cls = &pxa3xx_clock_sysclass, | ||
| 270 | } | ||
| 271 | }; | ||
| 272 | |||
| 273 | static int __init pxa95x_init(void) | ||
| 274 | { | ||
| 275 | int ret = 0, i; | ||
| 276 | |||
| 277 | if (cpu_is_pxa95x()) { | ||
| 278 | mfp_init_base(io_p2v(MFPR_BASE)); | ||
| 279 | mfp_init_addr(pxa95x_mfp_addr_map); | ||
| 280 | |||
| 281 | reset_status = ARSR; | ||
| 282 | |||
| 283 | /* | ||
| 284 | * clear RDH bit every time after reset | ||
| 285 | * | ||
| 286 | * Note: the last 3 bits DxS are write-1-to-clear so carefully | ||
| 287 | * preserve them here in case they will be referenced later | ||
| 288 | */ | ||
| 289 | ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); | ||
| 290 | |||
| 291 | clkdev_add_table(pxa95x_clkregs, ARRAY_SIZE(pxa95x_clkregs)); | ||
| 292 | |||
| 293 | if ((ret = pxa_init_dma(IRQ_DMA, 32))) | ||
| 294 | return ret; | ||
| 295 | |||
| 296 | for (i = 0; i < ARRAY_SIZE(pxa95x_sysdev); i++) { | ||
| 297 | ret = sysdev_register(&pxa95x_sysdev[i]); | ||
| 298 | if (ret) | ||
| 299 | pr_err("failed to register sysdev[%d]\n", i); | ||
| 300 | } | ||
| 301 | |||
| 302 | ret = platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
| 303 | } | ||
| 304 | |||
| 305 | return ret; | ||
| 306 | } | ||
| 307 | |||
| 308 | postcore_initcall(pxa95x_init); | ||
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c index 4121d03ea2c3..8361151be054 100644 --- a/arch/arm/mach-pxa/raumfeld.c +++ b/arch/arm/mach-pxa/raumfeld.c | |||
| @@ -588,6 +588,9 @@ static struct pxafb_mach_info raumfeld_sharp_lcd_info = { | |||
| 588 | .num_modes = 1, | 588 | .num_modes = 1, |
| 589 | .video_mem_size = 0x400000, | 589 | .video_mem_size = 0x400000, |
| 590 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, | 590 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, |
| 591 | #ifdef CONFIG_PXA3XX_GCU | ||
| 592 | .acceleration_enabled = 1, | ||
| 593 | #endif | ||
| 591 | }; | 594 | }; |
| 592 | 595 | ||
| 593 | static void __init raumfeld_lcd_init(void) | 596 | static void __init raumfeld_lcd_init(void) |
| @@ -616,6 +619,8 @@ static void __init raumfeld_lcd_init(void) | |||
| 616 | pr_warning("Unable to request GPIO_DISPLAY_ENABLE\n"); | 619 | pr_warning("Unable to request GPIO_DISPLAY_ENABLE\n"); |
| 617 | else | 620 | else |
| 618 | gpio_direction_output(GPIO_DISPLAY_ENABLE, 1); | 621 | gpio_direction_output(GPIO_DISPLAY_ENABLE, 1); |
| 622 | |||
| 623 | platform_device_register(&pxa3xx_device_gcu); | ||
| 619 | } | 624 | } |
| 620 | 625 | ||
| 621 | /** | 626 | /** |
| @@ -1085,7 +1090,7 @@ static void __init raumfeld_speaker_init(void) | |||
| 1085 | MACHINE_START(RAUMFELD_RC, "Raumfeld Controller") | 1090 | MACHINE_START(RAUMFELD_RC, "Raumfeld Controller") |
| 1086 | .boot_params = RAUMFELD_SDRAM_BASE + 0x100, | 1091 | .boot_params = RAUMFELD_SDRAM_BASE + 0x100, |
| 1087 | .init_machine = raumfeld_controller_init, | 1092 | .init_machine = raumfeld_controller_init, |
| 1088 | .map_io = pxa_map_io, | 1093 | .map_io = pxa3xx_map_io, |
| 1089 | .init_irq = pxa3xx_init_irq, | 1094 | .init_irq = pxa3xx_init_irq, |
| 1090 | .timer = &pxa_timer, | 1095 | .timer = &pxa_timer, |
| 1091 | MACHINE_END | 1096 | MACHINE_END |
| @@ -1095,7 +1100,7 @@ MACHINE_END | |||
| 1095 | MACHINE_START(RAUMFELD_CONNECTOR, "Raumfeld Connector") | 1100 | MACHINE_START(RAUMFELD_CONNECTOR, "Raumfeld Connector") |
| 1096 | .boot_params = RAUMFELD_SDRAM_BASE + 0x100, | 1101 | .boot_params = RAUMFELD_SDRAM_BASE + 0x100, |
| 1097 | .init_machine = raumfeld_connector_init, | 1102 | .init_machine = raumfeld_connector_init, |
| 1098 | .map_io = pxa_map_io, | 1103 | .map_io = pxa3xx_map_io, |
| 1099 | .init_irq = pxa3xx_init_irq, | 1104 | .init_irq = pxa3xx_init_irq, |
| 1100 | .timer = &pxa_timer, | 1105 | .timer = &pxa_timer, |
| 1101 | MACHINE_END | 1106 | MACHINE_END |
| @@ -1105,7 +1110,7 @@ MACHINE_END | |||
| 1105 | MACHINE_START(RAUMFELD_SPEAKER, "Raumfeld Speaker") | 1110 | MACHINE_START(RAUMFELD_SPEAKER, "Raumfeld Speaker") |
| 1106 | .boot_params = RAUMFELD_SDRAM_BASE + 0x100, | 1111 | .boot_params = RAUMFELD_SDRAM_BASE + 0x100, |
| 1107 | .init_machine = raumfeld_speaker_init, | 1112 | .init_machine = raumfeld_speaker_init, |
| 1108 | .map_io = pxa_map_io, | 1113 | .map_io = pxa3xx_map_io, |
| 1109 | .init_irq = pxa3xx_init_irq, | 1114 | .init_irq = pxa3xx_init_irq, |
| 1110 | .timer = &pxa_timer, | 1115 | .timer = &pxa_timer, |
| 1111 | MACHINE_END | 1116 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c index ffa50e633ee6..c1ca8cb467fc 100644 --- a/arch/arm/mach-pxa/saar.c +++ b/arch/arm/mach-pxa/saar.c | |||
| @@ -597,7 +597,7 @@ static void __init saar_init(void) | |||
| 597 | MACHINE_START(SAAR, "PXA930 Handheld Platform (aka SAAR)") | 597 | MACHINE_START(SAAR, "PXA930 Handheld Platform (aka SAAR)") |
| 598 | /* Maintainer: Eric Miao <eric.miao@marvell.com> */ | 598 | /* Maintainer: Eric Miao <eric.miao@marvell.com> */ |
| 599 | .boot_params = 0xa0000100, | 599 | .boot_params = 0xa0000100, |
| 600 | .map_io = pxa_map_io, | 600 | .map_io = pxa3xx_map_io, |
| 601 | .init_irq = pxa3xx_init_irq, | 601 | .init_irq = pxa3xx_init_irq, |
| 602 | .timer = &pxa_timer, | 602 | .timer = &pxa_timer, |
| 603 | .init_machine = saar_init, | 603 | .init_machine = saar_init, |
diff --git a/arch/arm/mach-pxa/saarb.c b/arch/arm/mach-pxa/saarb.c new file mode 100644 index 000000000000..e497922f761a --- /dev/null +++ b/arch/arm/mach-pxa/saarb.c | |||
| @@ -0,0 +1,114 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-pxa/saarb.c | ||
| 3 | * | ||
| 4 | * Support for the Marvell Handheld Platform (aka SAARB) | ||
| 5 | * | ||
| 6 | * Copyright (C) 2007-2010 Marvell International Ltd. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * publishhed by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/init.h> | ||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/i2c.h> | ||
| 16 | #include <linux/mfd/88pm860x.h> | ||
| 17 | |||
| 18 | #include <asm/mach-types.h> | ||
| 19 | #include <asm/mach/arch.h> | ||
| 20 | |||
| 21 | #include <mach/irqs.h> | ||
| 22 | #include <mach/hardware.h> | ||
| 23 | #include <mach/mfp.h> | ||
| 24 | #include <mach/mfp-pxa930.h> | ||
| 25 | #include <mach/gpio.h> | ||
| 26 | |||
| 27 | #include <plat/i2c.h> | ||
| 28 | |||
| 29 | #include "generic.h" | ||
| 30 | |||
| 31 | #define SAARB_NR_IRQS (IRQ_BOARD_START + 40) | ||
| 32 | |||
| 33 | static struct pm860x_touch_pdata saarb_touch = { | ||
| 34 | .gpadc_prebias = 1, | ||
| 35 | .slot_cycle = 1, | ||
| 36 | .tsi_prebias = 6, | ||
| 37 | .pen_prebias = 16, | ||
| 38 | .pen_prechg = 2, | ||
| 39 | .res_x = 300, | ||
| 40 | }; | ||
| 41 | |||
| 42 | static struct pm860x_backlight_pdata saarb_backlight[] = { | ||
| 43 | { | ||
| 44 | .id = PM8606_ID_BACKLIGHT, | ||
| 45 | .iset = PM8606_WLED_CURRENT(24), | ||
| 46 | .flags = PM8606_BACKLIGHT1, | ||
| 47 | }, | ||
| 48 | {}, | ||
| 49 | }; | ||
| 50 | |||
| 51 | static struct pm860x_led_pdata saarb_led[] = { | ||
| 52 | { | ||
| 53 | .id = PM8606_ID_LED, | ||
| 54 | .iset = PM8606_LED_CURRENT(12), | ||
| 55 | .flags = PM8606_LED1_RED, | ||
| 56 | }, { | ||
| 57 | .id = PM8606_ID_LED, | ||
| 58 | .iset = PM8606_LED_CURRENT(12), | ||
| 59 | .flags = PM8606_LED1_GREEN, | ||
| 60 | }, { | ||
| 61 | .id = PM8606_ID_LED, | ||
| 62 | .iset = PM8606_LED_CURRENT(12), | ||
| 63 | .flags = PM8606_LED1_BLUE, | ||
| 64 | }, { | ||
| 65 | .id = PM8606_ID_LED, | ||
| 66 | .iset = PM8606_LED_CURRENT(12), | ||
| 67 | .flags = PM8606_LED2_RED, | ||
| 68 | }, { | ||
| 69 | .id = PM8606_ID_LED, | ||
| 70 | .iset = PM8606_LED_CURRENT(12), | ||
| 71 | .flags = PM8606_LED2_GREEN, | ||
| 72 | }, { | ||
| 73 | .id = PM8606_ID_LED, | ||
| 74 | .iset = PM8606_LED_CURRENT(12), | ||
| 75 | .flags = PM8606_LED2_BLUE, | ||
| 76 | }, | ||
| 77 | }; | ||
| 78 | |||
| 79 | static struct pm860x_platform_data saarb_pm8607_info = { | ||
| 80 | .touch = &saarb_touch, | ||
| 81 | .backlight = &saarb_backlight[0], | ||
| 82 | .led = &saarb_led[0], | ||
| 83 | .companion_addr = 0x10, | ||
| 84 | .irq_mode = 0, | ||
| 85 | .irq_base = IRQ_BOARD_START, | ||
| 86 | |||
| 87 | .i2c_port = GI2C_PORT, | ||
| 88 | }; | ||
| 89 | |||
| 90 | static struct i2c_board_info saarb_i2c_info[] = { | ||
| 91 | { | ||
| 92 | .type = "88PM860x", | ||
| 93 | .addr = 0x34, | ||
| 94 | .platform_data = &saarb_pm8607_info, | ||
| 95 | .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)), | ||
| 96 | }, | ||
| 97 | }; | ||
| 98 | |||
| 99 | static void __init saarb_init(void) | ||
| 100 | { | ||
| 101 | pxa_set_ffuart_info(NULL); | ||
| 102 | pxa_set_i2c_info(NULL); | ||
| 103 | i2c_register_board_info(0, ARRAY_AND_SIZE(saarb_i2c_info)); | ||
| 104 | } | ||
| 105 | |||
| 106 | MACHINE_START(SAARB, "PXA955 Handheld Platform (aka SAARB)") | ||
| 107 | .boot_params = 0xa0000100, | ||
| 108 | .map_io = pxa_map_io, | ||
| 109 | .nr_irqs = SAARB_NR_IRQS, | ||
| 110 | .init_irq = pxa95x_init_irq, | ||
| 111 | .timer = &pxa_timer, | ||
| 112 | .init_machine = saarb_init, | ||
| 113 | MACHINE_END | ||
| 114 | |||
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c index 8fed027b12dc..e68d46d415f3 100644 --- a/arch/arm/mach-pxa/sharpsl_pm.c +++ b/arch/arm/mach-pxa/sharpsl_pm.c | |||
| @@ -579,7 +579,8 @@ static int sharpsl_ac_check(void) | |||
| 579 | static int sharpsl_pm_suspend(struct platform_device *pdev, pm_message_t state) | 579 | static int sharpsl_pm_suspend(struct platform_device *pdev, pm_message_t state) |
| 580 | { | 580 | { |
| 581 | sharpsl_pm.flags |= SHARPSL_SUSPENDED; | 581 | sharpsl_pm.flags |= SHARPSL_SUSPENDED; |
| 582 | flush_scheduled_work(); | 582 | flush_delayed_work_sync(&toggle_charger); |
| 583 | flush_delayed_work_sync(&sharpsl_bat); | ||
| 583 | 584 | ||
| 584 | if (sharpsl_pm.charge_mode == CHRG_ON) | 585 | if (sharpsl_pm.charge_mode == CHRG_ON) |
| 585 | sharpsl_pm.flags |= SHARPSL_DO_OFFLINE_CHRG; | 586 | sharpsl_pm.flags |= SHARPSL_DO_OFFLINE_CHRG; |
diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S index ae008110db4e..c551da86baf6 100644 --- a/arch/arm/mach-pxa/sleep.S +++ b/arch/arm/mach-pxa/sleep.S | |||
| @@ -14,7 +14,7 @@ | |||
| 14 | #include <linux/linkage.h> | 14 | #include <linux/linkage.h> |
| 15 | #include <asm/assembler.h> | 15 | #include <asm/assembler.h> |
| 16 | #include <mach/hardware.h> | 16 | #include <mach/hardware.h> |
| 17 | 17 | #include <mach/smemc.h> | |
| 18 | #include <mach/pxa2xx-regs.h> | 18 | #include <mach/pxa2xx-regs.h> |
| 19 | 19 | ||
| 20 | #define MDREFR_KDIV 0x200a4000 // all banks | 20 | #define MDREFR_KDIV 0x200a4000 // all banks |
diff --git a/arch/arm/mach-pxa/smemc.c b/arch/arm/mach-pxa/smemc.c index d6f6904132a6..232b7316ec08 100644 --- a/arch/arm/mach-pxa/smemc.c +++ b/arch/arm/mach-pxa/smemc.c | |||
| @@ -9,50 +9,37 @@ | |||
| 9 | #include <linux/sysdev.h> | 9 | #include <linux/sysdev.h> |
| 10 | 10 | ||
| 11 | #include <mach/hardware.h> | 11 | #include <mach/hardware.h> |
| 12 | 12 | #include <mach/smemc.h> | |
| 13 | #define SMEMC_PHYS_BASE (0x4A000000) | ||
| 14 | #define SMEMC_PHYS_SIZE (0x90) | ||
| 15 | |||
| 16 | #define MSC0 (0x08) /* Static Memory Controller Register 0 */ | ||
| 17 | #define MSC1 (0x0C) /* Static Memory Controller Register 1 */ | ||
| 18 | #define SXCNFG (0x1C) /* Synchronous Static Memory Control Register */ | ||
| 19 | #define MEMCLKCFG (0x68) /* Clock Configuration */ | ||
| 20 | #define CSADRCFG0 (0x80) /* Address Configuration Register for CS0 */ | ||
| 21 | #define CSADRCFG1 (0x84) /* Address Configuration Register for CS1 */ | ||
| 22 | #define CSADRCFG2 (0x88) /* Address Configuration Register for CS2 */ | ||
| 23 | #define CSADRCFG3 (0x8C) /* Address Configuration Register for CS3 */ | ||
| 24 | 13 | ||
| 25 | #ifdef CONFIG_PM | 14 | #ifdef CONFIG_PM |
| 26 | static void __iomem *smemc_mmio_base; | ||
| 27 | |||
| 28 | static unsigned long msc[2]; | 15 | static unsigned long msc[2]; |
| 29 | static unsigned long sxcnfg, memclkcfg; | 16 | static unsigned long sxcnfg, memclkcfg; |
| 30 | static unsigned long csadrcfg[4]; | 17 | static unsigned long csadrcfg[4]; |
| 31 | 18 | ||
| 32 | static int pxa3xx_smemc_suspend(struct sys_device *dev, pm_message_t state) | 19 | static int pxa3xx_smemc_suspend(struct sys_device *dev, pm_message_t state) |
| 33 | { | 20 | { |
| 34 | msc[0] = __raw_readl(smemc_mmio_base + MSC0); | 21 | msc[0] = __raw_readl(MSC0); |
| 35 | msc[1] = __raw_readl(smemc_mmio_base + MSC1); | 22 | msc[1] = __raw_readl(MSC1); |
| 36 | sxcnfg = __raw_readl(smemc_mmio_base + SXCNFG); | 23 | sxcnfg = __raw_readl(SXCNFG); |
| 37 | memclkcfg = __raw_readl(smemc_mmio_base + MEMCLKCFG); | 24 | memclkcfg = __raw_readl(MEMCLKCFG); |
| 38 | csadrcfg[0] = __raw_readl(smemc_mmio_base + CSADRCFG0); | 25 | csadrcfg[0] = __raw_readl(CSADRCFG0); |
| 39 | csadrcfg[1] = __raw_readl(smemc_mmio_base + CSADRCFG1); | 26 | csadrcfg[1] = __raw_readl(CSADRCFG1); |
| 40 | csadrcfg[2] = __raw_readl(smemc_mmio_base + CSADRCFG2); | 27 | csadrcfg[2] = __raw_readl(CSADRCFG2); |
| 41 | csadrcfg[3] = __raw_readl(smemc_mmio_base + CSADRCFG3); | 28 | csadrcfg[3] = __raw_readl(CSADRCFG3); |
| 42 | 29 | ||
| 43 | return 0; | 30 | return 0; |
| 44 | } | 31 | } |
| 45 | 32 | ||
| 46 | static int pxa3xx_smemc_resume(struct sys_device *dev) | 33 | static int pxa3xx_smemc_resume(struct sys_device *dev) |
| 47 | { | 34 | { |
| 48 | __raw_writel(msc[0], smemc_mmio_base + MSC0); | 35 | __raw_writel(msc[0], MSC0); |
| 49 | __raw_writel(msc[1], smemc_mmio_base + MSC1); | 36 | __raw_writel(msc[1], MSC1); |
| 50 | __raw_writel(sxcnfg, smemc_mmio_base + SXCNFG); | 37 | __raw_writel(sxcnfg, SXCNFG); |
| 51 | __raw_writel(memclkcfg, smemc_mmio_base + MEMCLKCFG); | 38 | __raw_writel(memclkcfg, MEMCLKCFG); |
| 52 | __raw_writel(csadrcfg[0], smemc_mmio_base + CSADRCFG0); | 39 | __raw_writel(csadrcfg[0], CSADRCFG0); |
| 53 | __raw_writel(csadrcfg[1], smemc_mmio_base + CSADRCFG1); | 40 | __raw_writel(csadrcfg[1], CSADRCFG1); |
| 54 | __raw_writel(csadrcfg[2], smemc_mmio_base + CSADRCFG2); | 41 | __raw_writel(csadrcfg[2], CSADRCFG2); |
| 55 | __raw_writel(csadrcfg[3], smemc_mmio_base + CSADRCFG3); | 42 | __raw_writel(csadrcfg[3], CSADRCFG3); |
| 56 | 43 | ||
| 57 | return 0; | 44 | return 0; |
| 58 | } | 45 | } |
| @@ -73,10 +60,6 @@ static int __init smemc_init(void) | |||
| 73 | int ret = 0; | 60 | int ret = 0; |
| 74 | 61 | ||
| 75 | if (cpu_is_pxa3xx()) { | 62 | if (cpu_is_pxa3xx()) { |
| 76 | smemc_mmio_base = ioremap(SMEMC_PHYS_BASE, SMEMC_PHYS_SIZE); | ||
| 77 | if (smemc_mmio_base == NULL) | ||
| 78 | return -ENODEV; | ||
| 79 | |||
| 80 | ret = sysdev_class_register(&smemc_sysclass); | 63 | ret = sysdev_class_register(&smemc_sysclass); |
| 81 | if (ret) | 64 | if (ret) |
| 82 | return ret; | 65 | return ret; |
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index f736119f1ebf..0bc938729c4c 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c | |||
| @@ -23,10 +23,11 @@ | |||
| 23 | #include <linux/spi/spi.h> | 23 | #include <linux/spi/spi.h> |
| 24 | #include <linux/spi/ads7846.h> | 24 | #include <linux/spi/ads7846.h> |
| 25 | #include <linux/spi/corgi_lcd.h> | 25 | #include <linux/spi/corgi_lcd.h> |
| 26 | #include <linux/mtd/physmap.h> | 26 | #include <linux/spi/pxa2xx_spi.h> |
| 27 | #include <linux/mtd/sharpsl.h> | 27 | #include <linux/mtd/sharpsl.h> |
| 28 | #include <linux/input/matrix_keypad.h> | 28 | #include <linux/input/matrix_keypad.h> |
| 29 | #include <linux/regulator/machine.h> | 29 | #include <linux/regulator/machine.h> |
| 30 | #include <linux/io.h> | ||
| 30 | 31 | ||
| 31 | #include <asm/setup.h> | 32 | #include <asm/setup.h> |
| 32 | #include <asm/mach-types.h> | 33 | #include <asm/mach-types.h> |
| @@ -41,9 +42,9 @@ | |||
| 41 | #include <mach/mmc.h> | 42 | #include <mach/mmc.h> |
| 42 | #include <mach/ohci.h> | 43 | #include <mach/ohci.h> |
| 43 | #include <mach/pxafb.h> | 44 | #include <mach/pxafb.h> |
| 44 | #include <mach/pxa2xx_spi.h> | ||
| 45 | #include <mach/spitz.h> | 45 | #include <mach/spitz.h> |
| 46 | #include <mach/sharpsl_pm.h> | 46 | #include <mach/sharpsl_pm.h> |
| 47 | #include <mach/smemc.h> | ||
| 47 | 48 | ||
| 48 | #include <plat/i2c.h> | 49 | #include <plat/i2c.h> |
| 49 | 50 | ||
| @@ -929,9 +930,10 @@ static void spitz_poweroff(void) | |||
| 929 | 930 | ||
| 930 | static void spitz_restart(char mode, const char *cmd) | 931 | static void spitz_restart(char mode, const char *cmd) |
| 931 | { | 932 | { |
| 933 | uint32_t msc0 = __raw_readl(MSC0); | ||
| 932 | /* Bootloader magic for a reboot */ | 934 | /* Bootloader magic for a reboot */ |
| 933 | if ((MSC0 & 0xffff0000) == 0x7ff00000) | 935 | if ((msc0 & 0xffff0000) == 0x7ff00000) |
| 934 | MSC0 = (MSC0 & 0xffff) | 0x7ee00000; | 936 | __raw_writel((msc0 & 0xffff) | 0x7ee00000, MSC0); |
| 935 | 937 | ||
| 936 | spitz_poweroff(); | 938 | spitz_poweroff(); |
| 937 | } | 939 | } |
| @@ -980,7 +982,7 @@ static void __init spitz_fixup(struct machine_desc *desc, | |||
| 980 | #ifdef CONFIG_MACH_SPITZ | 982 | #ifdef CONFIG_MACH_SPITZ |
| 981 | MACHINE_START(SPITZ, "SHARP Spitz") | 983 | MACHINE_START(SPITZ, "SHARP Spitz") |
| 982 | .fixup = spitz_fixup, | 984 | .fixup = spitz_fixup, |
| 983 | .map_io = pxa_map_io, | 985 | .map_io = pxa27x_map_io, |
| 984 | .init_irq = pxa27x_init_irq, | 986 | .init_irq = pxa27x_init_irq, |
| 985 | .init_machine = spitz_init, | 987 | .init_machine = spitz_init, |
| 986 | .timer = &pxa_timer, | 988 | .timer = &pxa_timer, |
| @@ -990,7 +992,7 @@ MACHINE_END | |||
| 990 | #ifdef CONFIG_MACH_BORZOI | 992 | #ifdef CONFIG_MACH_BORZOI |
| 991 | MACHINE_START(BORZOI, "SHARP Borzoi") | 993 | MACHINE_START(BORZOI, "SHARP Borzoi") |
| 992 | .fixup = spitz_fixup, | 994 | .fixup = spitz_fixup, |
| 993 | .map_io = pxa_map_io, | 995 | .map_io = pxa27x_map_io, |
| 994 | .init_irq = pxa27x_init_irq, | 996 | .init_irq = pxa27x_init_irq, |
| 995 | .init_machine = spitz_init, | 997 | .init_machine = spitz_init, |
| 996 | .timer = &pxa_timer, | 998 | .timer = &pxa_timer, |
| @@ -1000,7 +1002,7 @@ MACHINE_END | |||
| 1000 | #ifdef CONFIG_MACH_AKITA | 1002 | #ifdef CONFIG_MACH_AKITA |
| 1001 | MACHINE_START(AKITA, "SHARP Akita") | 1003 | MACHINE_START(AKITA, "SHARP Akita") |
| 1002 | .fixup = spitz_fixup, | 1004 | .fixup = spitz_fixup, |
| 1003 | .map_io = pxa_map_io, | 1005 | .map_io = pxa27x_map_io, |
| 1004 | .init_irq = pxa27x_init_irq, | 1006 | .init_irq = pxa27x_init_irq, |
| 1005 | .init_machine = spitz_init, | 1007 | .init_machine = spitz_init, |
| 1006 | .timer = &pxa_timer, | 1008 | .timer = &pxa_timer, |
diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c index 738adc1773fd..9a14fdb83c82 100644 --- a/arch/arm/mach-pxa/stargate2.c +++ b/arch/arm/mach-pxa/stargate2.c | |||
| @@ -46,10 +46,11 @@ | |||
| 46 | #include <plat/i2c.h> | 46 | #include <plat/i2c.h> |
| 47 | #include <mach/mmc.h> | 47 | #include <mach/mmc.h> |
| 48 | #include <mach/udc.h> | 48 | #include <mach/udc.h> |
| 49 | #include <mach/pxa2xx_spi.h> | ||
| 50 | #include <mach/pxa27x-udc.h> | 49 | #include <mach/pxa27x-udc.h> |
| 50 | #include <mach/smemc.h> | ||
| 51 | 51 | ||
| 52 | #include <linux/spi/spi.h> | 52 | #include <linux/spi/spi.h> |
| 53 | #include <linux/spi/pxa2xx_spi.h> | ||
| 53 | #include <linux/mfd/da903x.h> | 54 | #include <linux/mfd/da903x.h> |
| 54 | #include <linux/sht15.h> | 55 | #include <linux/sht15.h> |
| 55 | 56 | ||
| @@ -976,7 +977,7 @@ static void __init stargate2_init(void) | |||
| 976 | { | 977 | { |
| 977 | /* This is probably a board specific hack as this must be set | 978 | /* This is probably a board specific hack as this must be set |
| 978 | prior to connecting the MFP stuff up. */ | 979 | prior to connecting the MFP stuff up. */ |
| 979 | MECR &= ~MECR_NOS; | 980 | __raw_writel(__raw_readl(MECR) & ~MECR_NOS, MECR); |
| 980 | 981 | ||
| 981 | pxa2xx_mfp_config(ARRAY_AND_SIZE(stargate2_pin_config)); | 982 | pxa2xx_mfp_config(ARRAY_AND_SIZE(stargate2_pin_config)); |
| 982 | 983 | ||
| @@ -998,7 +999,7 @@ static void __init stargate2_init(void) | |||
| 998 | 999 | ||
| 999 | #ifdef CONFIG_MACH_INTELMOTE2 | 1000 | #ifdef CONFIG_MACH_INTELMOTE2 |
| 1000 | MACHINE_START(INTELMOTE2, "IMOTE 2") | 1001 | MACHINE_START(INTELMOTE2, "IMOTE 2") |
| 1001 | .map_io = pxa_map_io, | 1002 | .map_io = pxa27x_map_io, |
| 1002 | .init_irq = pxa27x_init_irq, | 1003 | .init_irq = pxa27x_init_irq, |
| 1003 | .timer = &pxa_timer, | 1004 | .timer = &pxa_timer, |
| 1004 | .init_machine = imote2_init, | 1005 | .init_machine = imote2_init, |
| @@ -1008,7 +1009,7 @@ MACHINE_END | |||
| 1008 | 1009 | ||
| 1009 | #ifdef CONFIG_MACH_STARGATE2 | 1010 | #ifdef CONFIG_MACH_STARGATE2 |
| 1010 | MACHINE_START(STARGATE2, "Stargate 2") | 1011 | MACHINE_START(STARGATE2, "Stargate 2") |
| 1011 | .map_io = pxa_map_io, | 1012 | .map_io = pxa27x_map_io, |
| 1012 | .nr_irqs = STARGATE_NR_IRQS, | 1013 | .nr_irqs = STARGATE_NR_IRQS, |
| 1013 | .init_irq = pxa27x_init_irq, | 1014 | .init_irq = pxa27x_init_irq, |
| 1014 | .timer = &pxa_timer, | 1015 | .timer = &pxa_timer, |
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c index 2ea7545273ad..9cecf8366db8 100644 --- a/arch/arm/mach-pxa/tavorevb.c +++ b/arch/arm/mach-pxa/tavorevb.c | |||
| @@ -490,7 +490,7 @@ static void __init tavorevb_init(void) | |||
| 490 | MACHINE_START(TAVOREVB, "PXA930 Evaluation Board (aka TavorEVB)") | 490 | MACHINE_START(TAVOREVB, "PXA930 Evaluation Board (aka TavorEVB)") |
| 491 | /* Maintainer: Eric Miao <eric.miao@marvell.com> */ | 491 | /* Maintainer: Eric Miao <eric.miao@marvell.com> */ |
| 492 | .boot_params = 0xa0000100, | 492 | .boot_params = 0xa0000100, |
| 493 | .map_io = pxa_map_io, | 493 | .map_io = pxa3xx_map_io, |
| 494 | .init_irq = pxa3xx_init_irq, | 494 | .init_irq = pxa3xx_init_irq, |
| 495 | .timer = &pxa_timer, | 495 | .timer = &pxa_timer, |
| 496 | .init_machine = tavorevb_init, | 496 | .init_machine = tavorevb_init, |
diff --git a/arch/arm/mach-pxa/tavorevb3.c b/arch/arm/mach-pxa/tavorevb3.c index dc3011697bbf..70191a9450eb 100644 --- a/arch/arm/mach-pxa/tavorevb3.c +++ b/arch/arm/mach-pxa/tavorevb3.c | |||
| @@ -127,7 +127,7 @@ static void __init evb3_init(void) | |||
| 127 | 127 | ||
| 128 | MACHINE_START(TAVOREVB3, "PXA950 Evaluation Board (aka TavorEVB3)") | 128 | MACHINE_START(TAVOREVB3, "PXA950 Evaluation Board (aka TavorEVB3)") |
| 129 | .boot_params = 0xa0000100, | 129 | .boot_params = 0xa0000100, |
| 130 | .map_io = pxa_map_io, | 130 | .map_io = pxa3xx_map_io, |
| 131 | .nr_irqs = TAVOREVB3_NR_IRQS, | 131 | .nr_irqs = TAVOREVB3_NR_IRQS, |
| 132 | .init_irq = pxa3xx_init_irq, | 132 | .init_irq = pxa3xx_init_irq, |
| 133 | .timer = &pxa_timer, | 133 | .timer = &pxa_timer, |
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c index 293e40aeaf29..e7f64d9b4f2d 100644 --- a/arch/arm/mach-pxa/time.c +++ b/arch/arm/mach-pxa/time.c | |||
| @@ -17,11 +17,11 @@ | |||
| 17 | #include <linux/interrupt.h> | 17 | #include <linux/interrupt.h> |
| 18 | #include <linux/clockchips.h> | 18 | #include <linux/clockchips.h> |
| 19 | #include <linux/sched.h> | 19 | #include <linux/sched.h> |
| 20 | #include <linux/cnt32_to_63.h> | ||
| 21 | 20 | ||
| 22 | #include <asm/div64.h> | 21 | #include <asm/div64.h> |
| 23 | #include <asm/mach/irq.h> | 22 | #include <asm/mach/irq.h> |
| 24 | #include <asm/mach/time.h> | 23 | #include <asm/mach/time.h> |
| 24 | #include <asm/sched_clock.h> | ||
| 25 | #include <mach/regs-ost.h> | 25 | #include <mach/regs-ost.h> |
| 26 | 26 | ||
| 27 | /* | 27 | /* |
| @@ -32,29 +32,18 @@ | |||
| 32 | * long as there is always less than 582 seconds between successive | 32 | * long as there is always less than 582 seconds between successive |
| 33 | * calls to sched_clock() which should always be the case in practice. | 33 | * calls to sched_clock() which should always be the case in practice. |
| 34 | */ | 34 | */ |
| 35 | static DEFINE_CLOCK_DATA(cd); | ||
| 35 | 36 | ||
| 36 | #define OSCR2NS_SCALE_FACTOR 10 | 37 | unsigned long long notrace sched_clock(void) |
| 37 | |||
| 38 | static unsigned long oscr2ns_scale; | ||
| 39 | |||
| 40 | static void __init set_oscr2ns_scale(unsigned long oscr_rate) | ||
| 41 | { | 38 | { |
| 42 | unsigned long long v = 1000000000ULL << OSCR2NS_SCALE_FACTOR; | 39 | u32 cyc = OSCR; |
| 43 | do_div(v, oscr_rate); | 40 | return cyc_to_sched_clock(&cd, cyc, (u32)~0); |
| 44 | oscr2ns_scale = v; | ||
| 45 | /* | ||
| 46 | * We want an even value to automatically clear the top bit | ||
| 47 | * returned by cnt32_to_63() without an additional run time | ||
| 48 | * instruction. So if the LSB is 1 then round it up. | ||
| 49 | */ | ||
| 50 | if (oscr2ns_scale & 1) | ||
| 51 | oscr2ns_scale++; | ||
| 52 | } | 41 | } |
| 53 | 42 | ||
| 54 | unsigned long long sched_clock(void) | 43 | static void notrace pxa_update_sched_clock(void) |
| 55 | { | 44 | { |
| 56 | unsigned long long v = cnt32_to_63(OSCR); | 45 | u32 cyc = OSCR; |
| 57 | return (v * oscr2ns_scale) >> OSCR2NS_SCALE_FACTOR; | 46 | update_sched_clock(&cd, cyc, (u32)~0); |
| 58 | } | 47 | } |
| 59 | 48 | ||
| 60 | 49 | ||
| @@ -127,7 +116,6 @@ static struct clocksource cksrc_pxa_oscr0 = { | |||
| 127 | .rating = 200, | 116 | .rating = 200, |
| 128 | .read = pxa_read_oscr, | 117 | .read = pxa_read_oscr, |
| 129 | .mask = CLOCKSOURCE_MASK(32), | 118 | .mask = CLOCKSOURCE_MASK(32), |
| 130 | .shift = 20, | ||
| 131 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 119 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 132 | }; | 120 | }; |
| 133 | 121 | ||
| @@ -145,7 +133,7 @@ static void __init pxa_timer_init(void) | |||
| 145 | OIER = 0; | 133 | OIER = 0; |
| 146 | OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3; | 134 | OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3; |
| 147 | 135 | ||
| 148 | set_oscr2ns_scale(clock_tick_rate); | 136 | init_sched_clock(&cd, pxa_update_sched_clock, 32, clock_tick_rate); |
| 149 | 137 | ||
| 150 | ckevt_pxa_osmr0.mult = | 138 | ckevt_pxa_osmr0.mult = |
| 151 | div_sc(clock_tick_rate, NSEC_PER_SEC, ckevt_pxa_osmr0.shift); | 139 | div_sc(clock_tick_rate, NSEC_PER_SEC, ckevt_pxa_osmr0.shift); |
| @@ -155,12 +143,9 @@ static void __init pxa_timer_init(void) | |||
| 155 | clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1; | 143 | clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1; |
| 156 | ckevt_pxa_osmr0.cpumask = cpumask_of(0); | 144 | ckevt_pxa_osmr0.cpumask = cpumask_of(0); |
| 157 | 145 | ||
| 158 | cksrc_pxa_oscr0.mult = | ||
| 159 | clocksource_hz2mult(clock_tick_rate, cksrc_pxa_oscr0.shift); | ||
| 160 | |||
| 161 | setup_irq(IRQ_OST0, &pxa_ost0_irq); | 146 | setup_irq(IRQ_OST0, &pxa_ost0_irq); |
| 162 | 147 | ||
| 163 | clocksource_register(&cksrc_pxa_oscr0); | 148 | clocksource_register_hz(&cksrc_pxa_oscr0, clock_tick_rate); |
| 164 | clockevents_register_device(&ckevt_pxa_osmr0); | 149 | clockevents_register_device(&ckevt_pxa_osmr0); |
| 165 | } | 150 | } |
| 166 | 151 | ||
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index 0ee1df49606d..af152e70cfcf 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c | |||
| @@ -32,6 +32,7 @@ | |||
| 32 | #include <linux/gpio.h> | 32 | #include <linux/gpio.h> |
| 33 | #include <linux/pda_power.h> | 33 | #include <linux/pda_power.h> |
| 34 | #include <linux/spi/spi.h> | 34 | #include <linux/spi/spi.h> |
| 35 | #include <linux/spi/pxa2xx_spi.h> | ||
| 35 | #include <linux/input/matrix_keypad.h> | 36 | #include <linux/input/matrix_keypad.h> |
| 36 | 37 | ||
| 37 | #include <asm/setup.h> | 38 | #include <asm/setup.h> |
| @@ -44,8 +45,8 @@ | |||
| 44 | #include <mach/mmc.h> | 45 | #include <mach/mmc.h> |
| 45 | #include <mach/udc.h> | 46 | #include <mach/udc.h> |
| 46 | #include <mach/tosa_bt.h> | 47 | #include <mach/tosa_bt.h> |
| 47 | #include <mach/pxa2xx_spi.h> | ||
| 48 | #include <mach/audio.h> | 48 | #include <mach/audio.h> |
| 49 | #include <mach/smemc.h> | ||
| 49 | 50 | ||
| 50 | #include <asm/mach/arch.h> | 51 | #include <asm/mach/arch.h> |
| 51 | #include <mach/tosa.h> | 52 | #include <mach/tosa.h> |
| @@ -893,9 +894,11 @@ static void tosa_poweroff(void) | |||
| 893 | 894 | ||
| 894 | static void tosa_restart(char mode, const char *cmd) | 895 | static void tosa_restart(char mode, const char *cmd) |
| 895 | { | 896 | { |
| 897 | uint32_t msc0 = __raw_readl(MSC0); | ||
| 898 | |||
| 896 | /* Bootloader magic for a reboot */ | 899 | /* Bootloader magic for a reboot */ |
| 897 | if((MSC0 & 0xffff0000) == 0x7ff00000) | 900 | if((msc0 & 0xffff0000) == 0x7ff00000) |
| 898 | MSC0 = (MSC0 & 0xffff) | 0x7ee00000; | 901 | __raw_writel((msc0 & 0xffff) | 0x7ee00000, MSC0); |
| 899 | 902 | ||
| 900 | tosa_poweroff(); | 903 | tosa_poweroff(); |
| 901 | } | 904 | } |
| @@ -953,7 +956,7 @@ static void __init fixup_tosa(struct machine_desc *desc, | |||
| 953 | 956 | ||
| 954 | MACHINE_START(TOSA, "SHARP Tosa") | 957 | MACHINE_START(TOSA, "SHARP Tosa") |
| 955 | .fixup = fixup_tosa, | 958 | .fixup = fixup_tosa, |
| 956 | .map_io = pxa_map_io, | 959 | .map_io = pxa25x_map_io, |
| 957 | .nr_irqs = TOSA_NR_IRQS, | 960 | .nr_irqs = TOSA_NR_IRQS, |
| 958 | .init_irq = pxa25x_init_irq, | 961 | .init_irq = pxa25x_init_irq, |
| 959 | .init_machine = tosa_init, | 962 | .init_machine = tosa_init, |
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c index 565d062f51d5..423261d63d07 100644 --- a/arch/arm/mach-pxa/trizeps4.c +++ b/arch/arm/mach-pxa/trizeps4.c | |||
| @@ -40,13 +40,13 @@ | |||
| 40 | #include <asm/mach/flash.h> | 40 | #include <asm/mach/flash.h> |
| 41 | 41 | ||
| 42 | #include <mach/pxa27x.h> | 42 | #include <mach/pxa27x.h> |
| 43 | #include <mach/pxa2xx_spi.h> | ||
| 44 | #include <mach/trizeps4.h> | 43 | #include <mach/trizeps4.h> |
| 45 | #include <mach/audio.h> | 44 | #include <mach/audio.h> |
| 46 | #include <mach/pxafb.h> | 45 | #include <mach/pxafb.h> |
| 47 | #include <mach/mmc.h> | 46 | #include <mach/mmc.h> |
| 48 | #include <mach/irda.h> | 47 | #include <mach/irda.h> |
| 49 | #include <mach/ohci.h> | 48 | #include <mach/ohci.h> |
| 49 | #include <mach/smemc.h> | ||
| 50 | #include <plat/i2c.h> | 50 | #include <plat/i2c.h> |
| 51 | 51 | ||
| 52 | #include "generic.h" | 52 | #include "generic.h" |
| @@ -539,10 +539,10 @@ static void __init trizeps4_init(void) | |||
| 539 | 539 | ||
| 540 | static void __init trizeps4_map_io(void) | 540 | static void __init trizeps4_map_io(void) |
| 541 | { | 541 | { |
| 542 | pxa_map_io(); | 542 | pxa27x_map_io(); |
| 543 | iotable_init(trizeps4_io_desc, ARRAY_SIZE(trizeps4_io_desc)); | 543 | iotable_init(trizeps4_io_desc, ARRAY_SIZE(trizeps4_io_desc)); |
| 544 | 544 | ||
| 545 | if ((MSC0 & 0x8) && (BOOT_DEF & 0x1)) { | 545 | if ((__raw_readl(MSC0) & 0x8) && (__raw_readl(BOOT_DEF) & 0x1)) { |
| 546 | /* if flash is 16 bit wide its a Trizeps4 WL */ | 546 | /* if flash is 16 bit wide its a Trizeps4 WL */ |
| 547 | __machine_arch_type = MACH_TYPE_TRIZEPS4WL; | 547 | __machine_arch_type = MACH_TYPE_TRIZEPS4WL; |
| 548 | trizeps4_flash_data[0].width = 2; | 548 | trizeps4_flash_data[0].width = 2; |
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c index 438fc9a5ed59..de69b203afa7 100644 --- a/arch/arm/mach-pxa/viper.c +++ b/arch/arm/mach-pxa/viper.c | |||
| @@ -983,7 +983,7 @@ static struct map_desc viper_io_desc[] __initdata = { | |||
| 983 | 983 | ||
| 984 | static void __init viper_map_io(void) | 984 | static void __init viper_map_io(void) |
| 985 | { | 985 | { |
| 986 | pxa_map_io(); | 986 | pxa25x_map_io(); |
| 987 | 987 | ||
| 988 | iotable_init(viper_io_desc, ARRAY_SIZE(viper_io_desc)); | 988 | iotable_init(viper_io_desc, ARRAY_SIZE(viper_io_desc)); |
| 989 | 989 | ||
diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c index f45ac0961778..b9b579715ff6 100644 --- a/arch/arm/mach-pxa/vpac270.c +++ b/arch/arm/mach-pxa/vpac270.c | |||
| @@ -719,7 +719,7 @@ static void __init vpac270_init(void) | |||
| 719 | 719 | ||
| 720 | MACHINE_START(VPAC270, "Voipac PXA270") | 720 | MACHINE_START(VPAC270, "Voipac PXA270") |
| 721 | .boot_params = 0xa0000100, | 721 | .boot_params = 0xa0000100, |
| 722 | .map_io = pxa_map_io, | 722 | .map_io = pxa27x_map_io, |
| 723 | .init_irq = pxa27x_init_irq, | 723 | .init_irq = pxa27x_init_irq, |
| 724 | .timer = &pxa_timer, | 724 | .timer = &pxa_timer, |
| 725 | .init_machine = vpac270_init | 725 | .init_machine = vpac270_init |
diff --git a/arch/arm/mach-pxa/xcep.c b/arch/arm/mach-pxa/xcep.c index 3260ce73d327..51c0281c6e0a 100644 --- a/arch/arm/mach-pxa/xcep.c +++ b/arch/arm/mach-pxa/xcep.c | |||
| @@ -31,6 +31,7 @@ | |||
| 31 | #include <mach/hardware.h> | 31 | #include <mach/hardware.h> |
| 32 | #include <mach/pxa2xx-regs.h> | 32 | #include <mach/pxa2xx-regs.h> |
| 33 | #include <mach/mfp-pxa25x.h> | 33 | #include <mach/mfp-pxa25x.h> |
| 34 | #include <mach/smemc.h> | ||
| 34 | 35 | ||
| 35 | #include "generic.h" | 36 | #include "generic.h" |
| 36 | 37 | ||
| @@ -172,9 +173,9 @@ static void __init xcep_init(void) | |||
| 172 | 173 | ||
| 173 | /* See Intel XScale Developer's Guide for details */ | 174 | /* See Intel XScale Developer's Guide for details */ |
| 174 | /* Set RDF and RDN to appropriate values (chip select 3 (smc91x)) */ | 175 | /* Set RDF and RDN to appropriate values (chip select 3 (smc91x)) */ |
| 175 | MSC1 = (MSC1 & 0xffff) | 0xD5540000; | 176 | __raw_writel((__raw_readl(MSC1) & 0xffff) | 0xD5540000, MSC1); |
| 176 | /* Set RDF and RDN to appropriate values (chip select 5 (fpga)) */ | 177 | /* Set RDF and RDN to appropriate values (chip select 5 (fpga)) */ |
| 177 | MSC2 = (MSC2 & 0xffff) | 0x72A00000; | 178 | __raw_writel((__raw_readl(MSC2) & 0xffff) | 0x72A00000, MSC2); |
| 178 | 179 | ||
| 179 | platform_add_devices(ARRAY_AND_SIZE(devices)); | 180 | platform_add_devices(ARRAY_AND_SIZE(devices)); |
| 180 | pxa_set_i2c_info(&xcep_i2c_platform_data); | 181 | pxa_set_i2c_info(&xcep_i2c_platform_data); |
| @@ -183,7 +184,7 @@ static void __init xcep_init(void) | |||
| 183 | MACHINE_START(XCEP, "Iskratel XCEP") | 184 | MACHINE_START(XCEP, "Iskratel XCEP") |
| 184 | .boot_params = 0xa0000100, | 185 | .boot_params = 0xa0000100, |
| 185 | .init_machine = xcep_init, | 186 | .init_machine = xcep_init, |
| 186 | .map_io = pxa_map_io, | 187 | .map_io = pxa25x_map_io, |
| 187 | .init_irq = pxa25x_init_irq, | 188 | .init_irq = pxa25x_init_irq, |
| 188 | .timer = &pxa_timer, | 189 | .timer = &pxa_timer, |
| 189 | MACHINE_END | 190 | MACHINE_END |
diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c index fefde9848d82..a323e076129e 100644 --- a/arch/arm/mach-pxa/z2.c +++ b/arch/arm/mach-pxa/z2.c | |||
| @@ -20,6 +20,7 @@ | |||
| 20 | #include <linux/z2_battery.h> | 20 | #include <linux/z2_battery.h> |
| 21 | #include <linux/dma-mapping.h> | 21 | #include <linux/dma-mapping.h> |
| 22 | #include <linux/spi/spi.h> | 22 | #include <linux/spi/spi.h> |
| 23 | #include <linux/spi/pxa2xx_spi.h> | ||
| 23 | #include <linux/spi/libertas_spi.h> | 24 | #include <linux/spi/libertas_spi.h> |
| 24 | #include <linux/spi/lms283gf05.h> | 25 | #include <linux/spi/lms283gf05.h> |
| 25 | #include <linux/power_supply.h> | 26 | #include <linux/power_supply.h> |
| @@ -38,7 +39,6 @@ | |||
| 38 | #include <mach/pxafb.h> | 39 | #include <mach/pxafb.h> |
| 39 | #include <mach/mmc.h> | 40 | #include <mach/mmc.h> |
| 40 | #include <plat/pxa27x_keypad.h> | 41 | #include <plat/pxa27x_keypad.h> |
| 41 | #include <mach/pxa2xx_spi.h> | ||
| 42 | 42 | ||
| 43 | #include <plat/i2c.h> | 43 | #include <plat/i2c.h> |
| 44 | 44 | ||
| @@ -704,7 +704,7 @@ static void __init z2_init(void) | |||
| 704 | 704 | ||
| 705 | MACHINE_START(ZIPIT2, "Zipit Z2") | 705 | MACHINE_START(ZIPIT2, "Zipit Z2") |
| 706 | .boot_params = 0xa0000100, | 706 | .boot_params = 0xa0000100, |
| 707 | .map_io = pxa_map_io, | 707 | .map_io = pxa27x_map_io, |
| 708 | .init_irq = pxa27x_init_irq, | 708 | .init_irq = pxa27x_init_irq, |
| 709 | .timer = &pxa_timer, | 709 | .timer = &pxa_timer, |
| 710 | .init_machine = z2_init, | 710 | .init_machine = z2_init, |
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c index dea46a2d089b..bf034c7670dd 100644 --- a/arch/arm/mach-pxa/zeus.c +++ b/arch/arm/mach-pxa/zeus.c | |||
| @@ -20,6 +20,7 @@ | |||
| 20 | #include <linux/dm9000.h> | 20 | #include <linux/dm9000.h> |
| 21 | #include <linux/mmc/host.h> | 21 | #include <linux/mmc/host.h> |
| 22 | #include <linux/spi/spi.h> | 22 | #include <linux/spi/spi.h> |
| 23 | #include <linux/spi/pxa2xx_spi.h> | ||
| 23 | #include <linux/mtd/mtd.h> | 24 | #include <linux/mtd/mtd.h> |
| 24 | #include <linux/mtd/partitions.h> | 25 | #include <linux/mtd/partitions.h> |
| 25 | #include <linux/mtd/physmap.h> | 26 | #include <linux/mtd/physmap.h> |
| @@ -41,12 +42,12 @@ | |||
| 41 | #include <mach/pxa27x-udc.h> | 42 | #include <mach/pxa27x-udc.h> |
| 42 | #include <mach/udc.h> | 43 | #include <mach/udc.h> |
| 43 | #include <mach/pxafb.h> | 44 | #include <mach/pxafb.h> |
| 44 | #include <mach/pxa2xx_spi.h> | ||
| 45 | #include <mach/mfp-pxa27x.h> | 45 | #include <mach/mfp-pxa27x.h> |
| 46 | #include <mach/pm.h> | 46 | #include <mach/pm.h> |
| 47 | #include <mach/audio.h> | 47 | #include <mach/audio.h> |
| 48 | #include <mach/arcom-pcmcia.h> | 48 | #include <mach/arcom-pcmcia.h> |
| 49 | #include <mach/zeus.h> | 49 | #include <mach/zeus.h> |
| 50 | #include <mach/smemc.h> | ||
| 50 | 51 | ||
| 51 | #include "generic.h" | 52 | #include "generic.h" |
| 52 | 53 | ||
| @@ -823,13 +824,16 @@ static mfp_cfg_t zeus_pin_config[] __initdata = { | |||
| 823 | static void __init zeus_init(void) | 824 | static void __init zeus_init(void) |
| 824 | { | 825 | { |
| 825 | u16 dm9000_msc = DM9K_MSC_VALUE; | 826 | u16 dm9000_msc = DM9K_MSC_VALUE; |
| 827 | u32 msc0, msc1; | ||
| 826 | 828 | ||
| 827 | system_rev = __raw_readw(ZEUS_CPLD_VERSION); | 829 | system_rev = __raw_readw(ZEUS_CPLD_VERSION); |
| 828 | pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f)); | 830 | pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f)); |
| 829 | 831 | ||
| 830 | /* Fix timings for dm9000s (CS1/CS2)*/ | 832 | /* Fix timings for dm9000s (CS1/CS2)*/ |
| 831 | MSC0 = (MSC0 & 0xffff) | (dm9000_msc << 16); | 833 | msc0 = __raw_readl(MSC0) & 0x0000ffff | (dm9000_msc << 16); |
| 832 | MSC1 = (MSC1 & 0xffff0000) | dm9000_msc; | 834 | msc1 = __raw_readl(MSC1) & 0xffff0000 | dm9000_msc; |
| 835 | __raw_writel(msc0, MSC0); | ||
| 836 | __raw_writel(msc1, MSC1); | ||
| 833 | 837 | ||
| 834 | pm_power_off = zeus_power_off; | 838 | pm_power_off = zeus_power_off; |
| 835 | zeus_setup_apm(); | 839 | zeus_setup_apm(); |
| @@ -883,7 +887,7 @@ static struct map_desc zeus_io_desc[] __initdata = { | |||
| 883 | 887 | ||
| 884 | static void __init zeus_map_io(void) | 888 | static void __init zeus_map_io(void) |
| 885 | { | 889 | { |
| 886 | pxa_map_io(); | 890 | pxa27x_map_io(); |
| 887 | 891 | ||
| 888 | iotable_init(zeus_io_desc, ARRAY_SIZE(zeus_io_desc)); | 892 | iotable_init(zeus_io_desc, ARRAY_SIZE(zeus_io_desc)); |
| 889 | 893 | ||
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c index 702f7a68e87d..a4c784aab764 100644 --- a/arch/arm/mach-pxa/zylonite.c +++ b/arch/arm/mach-pxa/zylonite.c | |||
| @@ -423,7 +423,7 @@ static void __init zylonite_init(void) | |||
| 423 | 423 | ||
| 424 | MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)") | 424 | MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)") |
| 425 | .boot_params = 0xa0000100, | 425 | .boot_params = 0xa0000100, |
| 426 | .map_io = pxa_map_io, | 426 | .map_io = pxa3xx_map_io, |
| 427 | .nr_irqs = ZYLONITE_NR_IRQS, | 427 | .nr_irqs = ZYLONITE_NR_IRQS, |
| 428 | .init_irq = pxa3xx_init_irq, | 428 | .init_irq = pxa3xx_init_irq, |
| 429 | .timer = &pxa_timer, | 429 | .timer = &pxa_timer, |
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 07c08151dfe6..1c6602cf50e4 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c | |||
| @@ -30,8 +30,8 @@ | |||
| 30 | #include <linux/ata_platform.h> | 30 | #include <linux/ata_platform.h> |
| 31 | #include <linux/amba/mmci.h> | 31 | #include <linux/amba/mmci.h> |
| 32 | #include <linux/gfp.h> | 32 | #include <linux/gfp.h> |
| 33 | #include <linux/clkdev.h> | ||
| 33 | 34 | ||
| 34 | #include <asm/clkdev.h> | ||
| 35 | #include <asm/system.h> | 35 | #include <asm/system.h> |
| 36 | #include <mach/hardware.h> | 36 | #include <mach/hardware.h> |
| 37 | #include <asm/irq.h> | 37 | #include <asm/irq.h> |
| @@ -47,15 +47,13 @@ | |||
| 47 | 47 | ||
| 48 | #include <asm/hardware/gic.h> | 48 | #include <asm/hardware/gic.h> |
| 49 | 49 | ||
| 50 | #include <mach/clkdev.h> | ||
| 51 | #include <mach/platform.h> | 50 | #include <mach/platform.h> |
| 52 | #include <mach/irqs.h> | 51 | #include <mach/irqs.h> |
| 53 | #include <plat/timer-sp.h> | 52 | #include <asm/hardware/timer-sp.h> |
| 54 | 53 | ||
| 55 | #include "core.h" | 54 | #include <plat/sched_clock.h> |
| 56 | 55 | ||
| 57 | /* used by entry-macro.S and platsmp.c */ | 56 | #include "core.h" |
| 58 | void __iomem *gic_cpu_base_addr; | ||
| 59 | 57 | ||
| 60 | #ifdef CONFIG_ZONE_DMA | 58 | #ifdef CONFIG_ZONE_DMA |
| 61 | /* | 59 | /* |
| @@ -658,6 +656,12 @@ void realview_leds_event(led_event_t ledevt) | |||
| 658 | #endif /* CONFIG_LEDS */ | 656 | #endif /* CONFIG_LEDS */ |
| 659 | 657 | ||
| 660 | /* | 658 | /* |
| 659 | * The sched_clock counter | ||
| 660 | */ | ||
| 661 | #define REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + \ | ||
| 662 | REALVIEW_SYS_24MHz_OFFSET) | ||
| 663 | |||
| 664 | /* | ||
| 661 | * Where is the timer (VA)? | 665 | * Where is the timer (VA)? |
| 662 | */ | 666 | */ |
| 663 | void __iomem *timer0_va_base; | 667 | void __iomem *timer0_va_base; |
| @@ -672,6 +676,8 @@ void __init realview_timer_init(unsigned int timer_irq) | |||
| 672 | { | 676 | { |
| 673 | u32 val; | 677 | u32 val; |
| 674 | 678 | ||
| 679 | versatile_sched_clock_init(REFCOUNTER, 24000000); | ||
| 680 | |||
| 675 | /* | 681 | /* |
| 676 | * set clock frequency: | 682 | * set clock frequency: |
| 677 | * REALVIEW_REFCLK is 32KHz | 683 | * REALVIEW_REFCLK is 32KHz |
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h index 781bca68a9fa..693239ddc39e 100644 --- a/arch/arm/mach-realview/core.h +++ b/arch/arm/mach-realview/core.h | |||
| @@ -53,7 +53,6 @@ extern struct platform_device realview_i2c_device; | |||
| 53 | extern struct mmci_platform_data realview_mmc0_plat_data; | 53 | extern struct mmci_platform_data realview_mmc0_plat_data; |
| 54 | extern struct mmci_platform_data realview_mmc1_plat_data; | 54 | extern struct mmci_platform_data realview_mmc1_plat_data; |
| 55 | extern struct clcd_board clcd_plat_data; | 55 | extern struct clcd_board clcd_plat_data; |
| 56 | extern void __iomem *gic_cpu_base_addr; | ||
| 57 | extern void __iomem *timer0_va_base; | 56 | extern void __iomem *timer0_va_base; |
| 58 | extern void __iomem *timer1_va_base; | 57 | extern void __iomem *timer1_va_base; |
| 59 | extern void __iomem *timer2_va_base; | 58 | extern void __iomem *timer2_va_base; |
diff --git a/arch/arm/mach-realview/hotplug.c b/arch/arm/mach-realview/hotplug.c index f95521a5e5ce..a87523d095e6 100644 --- a/arch/arm/mach-realview/hotplug.c +++ b/arch/arm/mach-realview/hotplug.c | |||
| @@ -11,14 +11,11 @@ | |||
| 11 | #include <linux/kernel.h> | 11 | #include <linux/kernel.h> |
| 12 | #include <linux/errno.h> | 12 | #include <linux/errno.h> |
| 13 | #include <linux/smp.h> | 13 | #include <linux/smp.h> |
| 14 | #include <linux/completion.h> | ||
| 15 | 14 | ||
| 16 | #include <asm/cacheflush.h> | 15 | #include <asm/cacheflush.h> |
| 17 | 16 | ||
| 18 | extern volatile int pen_release; | 17 | extern volatile int pen_release; |
| 19 | 18 | ||
| 20 | static DECLARE_COMPLETION(cpu_killed); | ||
| 21 | |||
| 22 | static inline void cpu_enter_lowpower(void) | 19 | static inline void cpu_enter_lowpower(void) |
| 23 | { | 20 | { |
| 24 | unsigned int v; | 21 | unsigned int v; |
| @@ -34,10 +31,10 @@ static inline void cpu_enter_lowpower(void) | |||
| 34 | " bic %0, %0, #0x20\n" | 31 | " bic %0, %0, #0x20\n" |
| 35 | " mcr p15, 0, %0, c1, c0, 1\n" | 32 | " mcr p15, 0, %0, c1, c0, 1\n" |
| 36 | " mrc p15, 0, %0, c1, c0, 0\n" | 33 | " mrc p15, 0, %0, c1, c0, 0\n" |
| 37 | " bic %0, %0, #0x04\n" | 34 | " bic %0, %0, %2\n" |
| 38 | " mcr p15, 0, %0, c1, c0, 0\n" | 35 | " mcr p15, 0, %0, c1, c0, 0\n" |
| 39 | : "=&r" (v) | 36 | : "=&r" (v) |
| 40 | : "r" (0) | 37 | : "r" (0), "Ir" (CR_C) |
| 41 | : "cc"); | 38 | : "cc"); |
| 42 | } | 39 | } |
| 43 | 40 | ||
| @@ -46,17 +43,17 @@ static inline void cpu_leave_lowpower(void) | |||
| 46 | unsigned int v; | 43 | unsigned int v; |
| 47 | 44 | ||
| 48 | asm volatile( "mrc p15, 0, %0, c1, c0, 0\n" | 45 | asm volatile( "mrc p15, 0, %0, c1, c0, 0\n" |
| 49 | " orr %0, %0, #0x04\n" | 46 | " orr %0, %0, %1\n" |
| 50 | " mcr p15, 0, %0, c1, c0, 0\n" | 47 | " mcr p15, 0, %0, c1, c0, 0\n" |
| 51 | " mrc p15, 0, %0, c1, c0, 1\n" | 48 | " mrc p15, 0, %0, c1, c0, 1\n" |
| 52 | " orr %0, %0, #0x20\n" | 49 | " orr %0, %0, #0x20\n" |
| 53 | " mcr p15, 0, %0, c1, c0, 1\n" | 50 | " mcr p15, 0, %0, c1, c0, 1\n" |
| 54 | : "=&r" (v) | 51 | : "=&r" (v) |
| 55 | : | 52 | : "Ir" (CR_C) |
| 56 | : "cc"); | 53 | : "cc"); |
| 57 | } | 54 | } |
| 58 | 55 | ||
| 59 | static inline void platform_do_lowpower(unsigned int cpu) | 56 | static inline void platform_do_lowpower(unsigned int cpu, int *spurious) |
| 60 | { | 57 | { |
| 61 | /* | 58 | /* |
| 62 | * there is no power-control hardware on this platform, so all | 59 | * there is no power-control hardware on this platform, so all |
| @@ -80,22 +77,19 @@ static inline void platform_do_lowpower(unsigned int cpu) | |||
| 80 | } | 77 | } |
| 81 | 78 | ||
| 82 | /* | 79 | /* |
| 83 | * getting here, means that we have come out of WFI without | 80 | * Getting here, means that we have come out of WFI without |
| 84 | * having been woken up - this shouldn't happen | 81 | * having been woken up - this shouldn't happen |
| 85 | * | 82 | * |
| 86 | * The trouble is, letting people know about this is not really | 83 | * Just note it happening - when we're woken, we can report |
| 87 | * possible, since we are currently running incoherently, and | 84 | * its occurrence. |
| 88 | * therefore cannot safely call printk() or anything else | ||
| 89 | */ | 85 | */ |
| 90 | #ifdef DEBUG | 86 | (*spurious)++; |
| 91 | printk("CPU%u: spurious wakeup call\n", cpu); | ||
| 92 | #endif | ||
| 93 | } | 87 | } |
| 94 | } | 88 | } |
| 95 | 89 | ||
| 96 | int platform_cpu_kill(unsigned int cpu) | 90 | int platform_cpu_kill(unsigned int cpu) |
| 97 | { | 91 | { |
| 98 | return wait_for_completion_timeout(&cpu_killed, 5000); | 92 | return 1; |
| 99 | } | 93 | } |
| 100 | 94 | ||
| 101 | /* | 95 | /* |
| @@ -105,30 +99,22 @@ int platform_cpu_kill(unsigned int cpu) | |||
| 105 | */ | 99 | */ |
| 106 | void platform_cpu_die(unsigned int cpu) | 100 | void platform_cpu_die(unsigned int cpu) |
| 107 | { | 101 | { |
| 108 | #ifdef DEBUG | 102 | int spurious = 0; |
| 109 | unsigned int this_cpu = hard_smp_processor_id(); | ||
| 110 | |||
| 111 | if (cpu != this_cpu) { | ||
| 112 | printk(KERN_CRIT "Eek! platform_cpu_die running on %u, should be %u\n", | ||
| 113 | this_cpu, cpu); | ||
| 114 | BUG(); | ||
| 115 | } | ||
| 116 | #endif | ||
| 117 | |||
| 118 | printk(KERN_NOTICE "CPU%u: shutdown\n", cpu); | ||
| 119 | complete(&cpu_killed); | ||
| 120 | 103 | ||
| 121 | /* | 104 | /* |
| 122 | * we're ready for shutdown now, so do it | 105 | * we're ready for shutdown now, so do it |
| 123 | */ | 106 | */ |
| 124 | cpu_enter_lowpower(); | 107 | cpu_enter_lowpower(); |
| 125 | platform_do_lowpower(cpu); | 108 | platform_do_lowpower(cpu, &spurious); |
| 126 | 109 | ||
| 127 | /* | 110 | /* |
| 128 | * bring this CPU back into the world of cache | 111 | * bring this CPU back into the world of cache |
| 129 | * coherency, and then restore interrupts | 112 | * coherency, and then restore interrupts |
| 130 | */ | 113 | */ |
| 131 | cpu_leave_lowpower(); | 114 | cpu_leave_lowpower(); |
| 115 | |||
| 116 | if (spurious) | ||
| 117 | pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious); | ||
| 132 | } | 118 | } |
| 133 | 119 | ||
| 134 | int platform_cpu_disable(unsigned int cpu) | 120 | int platform_cpu_disable(unsigned int cpu) |
diff --git a/arch/arm/mach-realview/include/mach/entry-macro.S b/arch/arm/mach-realview/include/mach/entry-macro.S index 340a5c276946..4071164aebaa 100644 --- a/arch/arm/mach-realview/include/mach/entry-macro.S +++ b/arch/arm/mach-realview/include/mach/entry-macro.S | |||
| @@ -8,74 +8,11 @@ | |||
| 8 | * warranty of any kind, whether express or implied. | 8 | * warranty of any kind, whether express or implied. |
| 9 | */ | 9 | */ |
| 10 | #include <mach/hardware.h> | 10 | #include <mach/hardware.h> |
| 11 | #include <asm/hardware/gic.h> | 11 | #include <asm/hardware/entry-macro-gic.S> |
| 12 | 12 | ||
| 13 | .macro disable_fiq | 13 | .macro disable_fiq |
| 14 | .endm | 14 | .endm |
| 15 | 15 | ||
| 16 | .macro get_irqnr_preamble, base, tmp | ||
| 17 | ldr \base, =gic_cpu_base_addr | ||
| 18 | ldr \base, [\base] | ||
| 19 | .endm | ||
| 20 | |||
| 21 | .macro arch_ret_to_user, tmp1, tmp2 | 16 | .macro arch_ret_to_user, tmp1, tmp2 |
| 22 | .endm | 17 | .endm |
| 23 | 18 | ||
| 24 | /* | ||
| 25 | * The interrupt numbering scheme is defined in the | ||
| 26 | * interrupt controller spec. To wit: | ||
| 27 | * | ||
| 28 | * Interrupts 0-15 are IPI | ||
| 29 | * 16-28 are reserved | ||
| 30 | * 29-31 are local. We allow 30 to be used for the watchdog. | ||
| 31 | * 32-1020 are global | ||
| 32 | * 1021-1022 are reserved | ||
| 33 | * 1023 is "spurious" (no interrupt) | ||
| 34 | * | ||
| 35 | * For now, we ignore all local interrupts so only return an interrupt if it's | ||
| 36 | * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs. | ||
| 37 | * | ||
| 38 | * A simple read from the controller will tell us the number of the highest | ||
| 39 | * priority enabled interrupt. We then just need to check whether it is in the | ||
| 40 | * valid range for an IRQ (30-1020 inclusive). | ||
| 41 | */ | ||
| 42 | |||
| 43 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 44 | |||
| 45 | ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */ | ||
| 46 | |||
| 47 | ldr \tmp, =1021 | ||
| 48 | |||
| 49 | bic \irqnr, \irqstat, #0x1c00 | ||
| 50 | |||
| 51 | cmp \irqnr, #29 | ||
| 52 | cmpcc \irqnr, \irqnr | ||
| 53 | cmpne \irqnr, \tmp | ||
| 54 | cmpcs \irqnr, \irqnr | ||
| 55 | |||
| 56 | .endm | ||
| 57 | |||
| 58 | /* We assume that irqstat (the raw value of the IRQ acknowledge | ||
| 59 | * register) is preserved from the macro above. | ||
| 60 | * If there is an IPI, we immediately signal end of interrupt on the | ||
| 61 | * controller, since this requires the original irqstat value which | ||
| 62 | * we won't easily be able to recreate later. | ||
| 63 | */ | ||
| 64 | |||
| 65 | .macro test_for_ipi, irqnr, irqstat, base, tmp | ||
| 66 | bic \irqnr, \irqstat, #0x1c00 | ||
| 67 | cmp \irqnr, #16 | ||
| 68 | strcc \irqstat, [\base, #GIC_CPU_EOI] | ||
| 69 | cmpcs \irqnr, \irqnr | ||
| 70 | .endm | ||
| 71 | |||
| 72 | /* As above, this assumes that irqstat and base are preserved.. */ | ||
| 73 | |||
| 74 | .macro test_for_ltirq, irqnr, irqstat, base, tmp | ||
| 75 | bic \irqnr, \irqstat, #0x1c00 | ||
| 76 | mov \tmp, #0 | ||
| 77 | cmp \irqnr, #29 | ||
| 78 | moveq \tmp, #1 | ||
| 79 | streq \irqstat, [\base, #GIC_CPU_EOI] | ||
| 80 | cmp \tmp, #0 | ||
| 81 | .endm | ||
diff --git a/arch/arm/mach-realview/include/mach/smp.h b/arch/arm/mach-realview/include/mach/smp.h index d3cd265cb058..c8221b38ee7c 100644 --- a/arch/arm/mach-realview/include/mach/smp.h +++ b/arch/arm/mach-realview/include/mach/smp.h | |||
| @@ -2,14 +2,13 @@ | |||
| 2 | #define ASMARM_ARCH_SMP_H | 2 | #define ASMARM_ARCH_SMP_H |
| 3 | 3 | ||
| 4 | #include <asm/hardware/gic.h> | 4 | #include <asm/hardware/gic.h> |
| 5 | #include <asm/smp_mpidr.h> | ||
| 6 | 5 | ||
| 7 | /* | 6 | /* |
| 8 | * We use IRQ1 as the IPI | 7 | * We use IRQ1 as the IPI |
| 9 | */ | 8 | */ |
| 10 | static inline void smp_cross_call(const struct cpumask *mask) | 9 | static inline void smp_cross_call(const struct cpumask *mask, int ipi) |
| 11 | { | 10 | { |
| 12 | gic_raise_softirq(mask, 1); | 11 | gic_raise_softirq(mask, ipi); |
| 13 | } | 12 | } |
| 14 | 13 | ||
| 15 | #endif | 14 | #endif |
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c index 009265818d55..a22bf67f2f78 100644 --- a/arch/arm/mach-realview/platsmp.c +++ b/arch/arm/mach-realview/platsmp.c | |||
| @@ -19,7 +19,6 @@ | |||
| 19 | #include <asm/cacheflush.h> | 19 | #include <asm/cacheflush.h> |
| 20 | #include <mach/hardware.h> | 20 | #include <mach/hardware.h> |
| 21 | #include <asm/mach-types.h> | 21 | #include <asm/mach-types.h> |
| 22 | #include <asm/localtimer.h> | ||
| 23 | #include <asm/unified.h> | 22 | #include <asm/unified.h> |
| 24 | 23 | ||
| 25 | #include <mach/board-eb.h> | 24 | #include <mach/board-eb.h> |
| @@ -37,6 +36,19 @@ extern void realview_secondary_startup(void); | |||
| 37 | */ | 36 | */ |
| 38 | volatile int __cpuinitdata pen_release = -1; | 37 | volatile int __cpuinitdata pen_release = -1; |
| 39 | 38 | ||
| 39 | /* | ||
| 40 | * Write pen_release in a way that is guaranteed to be visible to all | ||
| 41 | * observers, irrespective of whether they're taking part in coherency | ||
| 42 | * or not. This is necessary for the hotplug code to work reliably. | ||
| 43 | */ | ||
| 44 | static void write_pen_release(int val) | ||
| 45 | { | ||
| 46 | pen_release = val; | ||
| 47 | smp_wmb(); | ||
| 48 | __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); | ||
| 49 | outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); | ||
| 50 | } | ||
| 51 | |||
| 40 | static void __iomem *scu_base_addr(void) | 52 | static void __iomem *scu_base_addr(void) |
| 41 | { | 53 | { |
| 42 | if (machine_is_realview_eb_mp()) | 54 | if (machine_is_realview_eb_mp()) |
| @@ -50,33 +62,22 @@ static void __iomem *scu_base_addr(void) | |||
| 50 | return (void __iomem *)0; | 62 | return (void __iomem *)0; |
| 51 | } | 63 | } |
| 52 | 64 | ||
| 53 | static inline unsigned int get_core_count(void) | ||
| 54 | { | ||
| 55 | void __iomem *scu_base = scu_base_addr(); | ||
| 56 | if (scu_base) | ||
| 57 | return scu_get_core_count(scu_base); | ||
| 58 | return 1; | ||
| 59 | } | ||
| 60 | |||
| 61 | static DEFINE_SPINLOCK(boot_lock); | 65 | static DEFINE_SPINLOCK(boot_lock); |
| 62 | 66 | ||
| 63 | void __cpuinit platform_secondary_init(unsigned int cpu) | 67 | void __cpuinit platform_secondary_init(unsigned int cpu) |
| 64 | { | 68 | { |
| 65 | trace_hardirqs_off(); | ||
| 66 | |||
| 67 | /* | 69 | /* |
| 68 | * if any interrupts are already enabled for the primary | 70 | * if any interrupts are already enabled for the primary |
| 69 | * core (e.g. timer irq), then they will not have been enabled | 71 | * core (e.g. timer irq), then they will not have been enabled |
| 70 | * for us: do so | 72 | * for us: do so |
| 71 | */ | 73 | */ |
| 72 | gic_cpu_init(0, gic_cpu_base_addr); | 74 | gic_secondary_init(0); |
| 73 | 75 | ||
| 74 | /* | 76 | /* |
| 75 | * let the primary processor know we're out of the | 77 | * let the primary processor know we're out of the |
| 76 | * pen, then head off into the C entry point | 78 | * pen, then head off into the C entry point |
| 77 | */ | 79 | */ |
| 78 | pen_release = -1; | 80 | write_pen_release(-1); |
| 79 | smp_wmb(); | ||
| 80 | 81 | ||
| 81 | /* | 82 | /* |
| 82 | * Synchronise with the boot thread. | 83 | * Synchronise with the boot thread. |
| @@ -103,20 +104,14 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) | |||
| 103 | * Note that "pen_release" is the hardware CPU ID, whereas | 104 | * Note that "pen_release" is the hardware CPU ID, whereas |
| 104 | * "cpu" is Linux's internal ID. | 105 | * "cpu" is Linux's internal ID. |
| 105 | */ | 106 | */ |
| 106 | pen_release = cpu; | 107 | write_pen_release(cpu); |
| 107 | flush_cache_all(); | ||
| 108 | 108 | ||
| 109 | /* | 109 | /* |
| 110 | * XXX | 110 | * Send the secondary CPU a soft interrupt, thereby causing |
| 111 | * | 111 | * the boot monitor to read the system wide flags register, |
| 112 | * This is a later addition to the booting protocol: the | 112 | * and branch to the address found there. |
| 113 | * bootMonitor now puts secondary cores into WFI, so | ||
| 114 | * poke_milo() no longer gets the cores moving; we need | ||
| 115 | * to send a soft interrupt to wake the secondary core. | ||
| 116 | * Use smp_cross_call() for this, since there's little | ||
| 117 | * point duplicating the code here | ||
| 118 | */ | 113 | */ |
| 119 | smp_cross_call(cpumask_of(cpu)); | 114 | smp_cross_call(cpumask_of(cpu), 1); |
| 120 | 115 | ||
| 121 | timeout = jiffies + (1 * HZ); | 116 | timeout = jiffies + (1 * HZ); |
| 122 | while (time_before(jiffies, timeout)) { | 117 | while (time_before(jiffies, timeout)) { |
| @@ -136,48 +131,18 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) | |||
| 136 | return pen_release != -1 ? -ENOSYS : 0; | 131 | return pen_release != -1 ? -ENOSYS : 0; |
| 137 | } | 132 | } |
| 138 | 133 | ||
| 139 | static void __init poke_milo(void) | ||
| 140 | { | ||
| 141 | /* nobody is to be released from the pen yet */ | ||
| 142 | pen_release = -1; | ||
| 143 | |||
| 144 | /* | ||
| 145 | * Write the address of secondary startup into the system-wide flags | ||
| 146 | * register. The BootMonitor waits for this register to become | ||
| 147 | * non-zero. | ||
| 148 | */ | ||
| 149 | __raw_writel(BSYM(virt_to_phys(realview_secondary_startup)), | ||
| 150 | __io_address(REALVIEW_SYS_FLAGSSET)); | ||
| 151 | |||
| 152 | mb(); | ||
| 153 | } | ||
| 154 | |||
| 155 | /* | 134 | /* |
| 156 | * Initialise the CPU possible map early - this describes the CPUs | 135 | * Initialise the CPU possible map early - this describes the CPUs |
| 157 | * which may be present or become present in the system. | 136 | * which may be present or become present in the system. |
| 158 | */ | 137 | */ |
| 159 | void __init smp_init_cpus(void) | 138 | void __init smp_init_cpus(void) |
| 160 | { | 139 | { |
| 161 | unsigned int i, ncores = get_core_count(); | 140 | void __iomem *scu_base = scu_base_addr(); |
| 141 | unsigned int i, ncores; | ||
| 162 | 142 | ||
| 163 | for (i = 0; i < ncores; i++) | 143 | ncores = scu_base ? scu_get_core_count(scu_base) : 1; |
| 164 | set_cpu_possible(i, true); | ||
| 165 | } | ||
| 166 | |||
| 167 | void __init smp_prepare_cpus(unsigned int max_cpus) | ||
| 168 | { | ||
| 169 | unsigned int ncores = get_core_count(); | ||
| 170 | unsigned int cpu = smp_processor_id(); | ||
| 171 | int i; | ||
| 172 | 144 | ||
| 173 | /* sanity check */ | 145 | /* sanity check */ |
| 174 | if (ncores == 0) { | ||
| 175 | printk(KERN_ERR | ||
| 176 | "Realview: strange CM count of 0? Default to 1\n"); | ||
| 177 | |||
| 178 | ncores = 1; | ||
| 179 | } | ||
| 180 | |||
| 181 | if (ncores > NR_CPUS) { | 146 | if (ncores > NR_CPUS) { |
| 182 | printk(KERN_WARNING | 147 | printk(KERN_WARNING |
| 183 | "Realview: no. of cores (%d) greater than configured " | 148 | "Realview: no. of cores (%d) greater than configured " |
| @@ -186,13 +151,13 @@ void __init smp_prepare_cpus(unsigned int max_cpus) | |||
| 186 | ncores = NR_CPUS; | 151 | ncores = NR_CPUS; |
| 187 | } | 152 | } |
| 188 | 153 | ||
| 189 | smp_store_cpu_info(cpu); | 154 | for (i = 0; i < ncores; i++) |
| 155 | set_cpu_possible(i, true); | ||
| 156 | } | ||
| 190 | 157 | ||
| 191 | /* | 158 | void __init platform_smp_prepare_cpus(unsigned int max_cpus) |
| 192 | * are we trying to boot more cores than exist? | 159 | { |
| 193 | */ | 160 | int i; |
| 194 | if (max_cpus > ncores) | ||
| 195 | max_cpus = ncores; | ||
| 196 | 161 | ||
| 197 | /* | 162 | /* |
| 198 | * Initialise the present map, which describes the set of CPUs | 163 | * Initialise the present map, which describes the set of CPUs |
| @@ -201,21 +166,14 @@ void __init smp_prepare_cpus(unsigned int max_cpus) | |||
| 201 | for (i = 0; i < max_cpus; i++) | 166 | for (i = 0; i < max_cpus; i++) |
| 202 | set_cpu_present(i, true); | 167 | set_cpu_present(i, true); |
| 203 | 168 | ||
| 169 | scu_enable(scu_base_addr()); | ||
| 170 | |||
| 204 | /* | 171 | /* |
| 205 | * Initialise the SCU if there are more than one CPU and let | 172 | * Write the address of secondary startup into the |
| 206 | * them know where to start. Note that, on modern versions of | 173 | * system-wide flags register. The BootMonitor waits |
| 207 | * MILO, the "poke" doesn't actually do anything until each | 174 | * until it receives a soft interrupt, and then the |
| 208 | * individual core is sent a soft interrupt to get it out of | 175 | * secondary CPU branches to this address. |
| 209 | * WFI | ||
| 210 | */ | 176 | */ |
| 211 | if (max_cpus > 1) { | 177 | __raw_writel(BSYM(virt_to_phys(realview_secondary_startup)), |
| 212 | /* | 178 | __io_address(REALVIEW_SYS_FLAGSSET)); |
| 213 | * Enable the local timer or broadcast device for the | ||
| 214 | * boot CPU, but only if we have more than one CPU. | ||
| 215 | */ | ||
| 216 | percpu_timer_setup(); | ||
| 217 | |||
| 218 | scu_enable(scu_base_addr()); | ||
| 219 | poke_milo(); | ||
| 220 | } | ||
| 221 | } | 179 | } |
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index f2697106f809..6ef5c5e528b2 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c | |||
| @@ -364,21 +364,19 @@ static void __init gic_init_irq(void) | |||
| 364 | writel(0x00000000, __io_address(REALVIEW_SYS_LOCK)); | 364 | writel(0x00000000, __io_address(REALVIEW_SYS_LOCK)); |
| 365 | 365 | ||
| 366 | /* core tile GIC, primary */ | 366 | /* core tile GIC, primary */ |
| 367 | gic_cpu_base_addr = __io_address(REALVIEW_EB11MP_GIC_CPU_BASE); | 367 | gic_init(0, 29, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE), |
| 368 | gic_dist_init(0, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE), 29); | 368 | __io_address(REALVIEW_EB11MP_GIC_CPU_BASE)); |
| 369 | gic_cpu_init(0, gic_cpu_base_addr); | ||
| 370 | 369 | ||
| 371 | #ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB | 370 | #ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB |
| 372 | /* board GIC, secondary */ | 371 | /* board GIC, secondary */ |
| 373 | gic_dist_init(1, __io_address(REALVIEW_EB_GIC_DIST_BASE), 64); | 372 | gic_init(1, 64, __io_address(REALVIEW_EB_GIC_DIST_BASE), |
| 374 | gic_cpu_init(1, __io_address(REALVIEW_EB_GIC_CPU_BASE)); | 373 | __io_address(REALVIEW_EB_GIC_CPU_BASE)); |
| 375 | gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1); | 374 | gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1); |
| 376 | #endif | 375 | #endif |
| 377 | } else { | 376 | } else { |
| 378 | /* board GIC, primary */ | 377 | /* board GIC, primary */ |
| 379 | gic_cpu_base_addr = __io_address(REALVIEW_EB_GIC_CPU_BASE); | 378 | gic_init(0, 29, __io_address(REALVIEW_EB_GIC_DIST_BASE), |
| 380 | gic_dist_init(0, __io_address(REALVIEW_EB_GIC_DIST_BASE), 29); | 379 | __io_address(REALVIEW_EB_GIC_CPU_BASE)); |
| 381 | gic_cpu_init(0, gic_cpu_base_addr); | ||
| 382 | } | 380 | } |
| 383 | } | 381 | } |
| 384 | 382 | ||
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c index a4125619d71b..cbdc97a5685f 100644 --- a/arch/arm/mach-realview/realview_pb1176.c +++ b/arch/arm/mach-realview/realview_pb1176.c | |||
| @@ -304,13 +304,14 @@ static struct platform_device char_lcd_device = { | |||
| 304 | static void __init gic_init_irq(void) | 304 | static void __init gic_init_irq(void) |
| 305 | { | 305 | { |
| 306 | /* ARM1176 DevChip GIC, primary */ | 306 | /* ARM1176 DevChip GIC, primary */ |
| 307 | gic_cpu_base_addr = __io_address(REALVIEW_DC1176_GIC_CPU_BASE); | 307 | gic_init(0, IRQ_DC1176_GIC_START, |
| 308 | gic_dist_init(0, __io_address(REALVIEW_DC1176_GIC_DIST_BASE), IRQ_DC1176_GIC_START); | 308 | __io_address(REALVIEW_DC1176_GIC_DIST_BASE), |
| 309 | gic_cpu_init(0, gic_cpu_base_addr); | 309 | __io_address(REALVIEW_DC1176_GIC_CPU_BASE)); |
| 310 | 310 | ||
| 311 | /* board GIC, secondary */ | 311 | /* board GIC, secondary */ |
| 312 | gic_dist_init(1, __io_address(REALVIEW_PB1176_GIC_DIST_BASE), IRQ_PB1176_GIC_START); | 312 | gic_init(1, IRQ_PB1176_GIC_START, |
| 313 | gic_cpu_init(1, __io_address(REALVIEW_PB1176_GIC_CPU_BASE)); | 313 | __io_address(REALVIEW_PB1176_GIC_DIST_BASE), |
| 314 | __io_address(REALVIEW_PB1176_GIC_CPU_BASE)); | ||
| 314 | gic_cascade_irq(1, IRQ_DC1176_PB_IRQ1); | 315 | gic_cascade_irq(1, IRQ_DC1176_PB_IRQ1); |
| 315 | } | 316 | } |
| 316 | 317 | ||
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c index 117b95b2ca15..8e8ab7d29a6a 100644 --- a/arch/arm/mach-realview/realview_pb11mp.c +++ b/arch/arm/mach-realview/realview_pb11mp.c | |||
| @@ -309,13 +309,13 @@ static void __init gic_init_irq(void) | |||
| 309 | writel(0x00000000, __io_address(REALVIEW_SYS_LOCK)); | 309 | writel(0x00000000, __io_address(REALVIEW_SYS_LOCK)); |
| 310 | 310 | ||
| 311 | /* ARM11MPCore test chip GIC, primary */ | 311 | /* ARM11MPCore test chip GIC, primary */ |
| 312 | gic_cpu_base_addr = __io_address(REALVIEW_TC11MP_GIC_CPU_BASE); | 312 | gic_init(0, 29, __io_address(REALVIEW_TC11MP_GIC_DIST_BASE), |
| 313 | gic_dist_init(0, __io_address(REALVIEW_TC11MP_GIC_DIST_BASE), 29); | 313 | __io_address(REALVIEW_TC11MP_GIC_CPU_BASE)); |
| 314 | gic_cpu_init(0, gic_cpu_base_addr); | ||
| 315 | 314 | ||
| 316 | /* board GIC, secondary */ | 315 | /* board GIC, secondary */ |
| 317 | gic_dist_init(1, __io_address(REALVIEW_PB11MP_GIC_DIST_BASE), IRQ_PB11MP_GIC_START); | 316 | gic_init(1, IRQ_PB11MP_GIC_START, |
| 318 | gic_cpu_init(1, __io_address(REALVIEW_PB11MP_GIC_CPU_BASE)); | 317 | __io_address(REALVIEW_PB11MP_GIC_DIST_BASE), |
| 318 | __io_address(REALVIEW_PB11MP_GIC_CPU_BASE)); | ||
| 319 | gic_cascade_irq(1, IRQ_TC11MP_PB_IRQ1); | 319 | gic_cascade_irq(1, IRQ_TC11MP_PB_IRQ1); |
| 320 | } | 320 | } |
| 321 | 321 | ||
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c index 929b8dc12e81..841118e3e118 100644 --- a/arch/arm/mach-realview/realview_pba8.c +++ b/arch/arm/mach-realview/realview_pba8.c | |||
| @@ -273,9 +273,9 @@ static struct platform_device pmu_device = { | |||
| 273 | static void __init gic_init_irq(void) | 273 | static void __init gic_init_irq(void) |
| 274 | { | 274 | { |
| 275 | /* ARM PB-A8 on-board GIC */ | 275 | /* ARM PB-A8 on-board GIC */ |
| 276 | gic_cpu_base_addr = __io_address(REALVIEW_PBA8_GIC_CPU_BASE); | 276 | gic_init(0, IRQ_PBA8_GIC_START, |
| 277 | gic_dist_init(0, __io_address(REALVIEW_PBA8_GIC_DIST_BASE), IRQ_PBA8_GIC_START); | 277 | __io_address(REALVIEW_PBA8_GIC_DIST_BASE), |
| 278 | gic_cpu_init(0, __io_address(REALVIEW_PBA8_GIC_CPU_BASE)); | 278 | __io_address(REALVIEW_PBA8_GIC_CPU_BASE)); |
| 279 | } | 279 | } |
| 280 | 280 | ||
| 281 | static void __init realview_pba8_timer_init(void) | 281 | static void __init realview_pba8_timer_init(void) |
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c index b9f9e20031a7..02b755b009db 100644 --- a/arch/arm/mach-realview/realview_pbx.c +++ b/arch/arm/mach-realview/realview_pbx.c | |||
| @@ -313,15 +313,12 @@ static void __init gic_init_irq(void) | |||
| 313 | { | 313 | { |
| 314 | /* ARM PBX on-board GIC */ | 314 | /* ARM PBX on-board GIC */ |
| 315 | if (core_tile_pbx11mp() || core_tile_pbxa9mp()) { | 315 | if (core_tile_pbx11mp() || core_tile_pbxa9mp()) { |
| 316 | gic_cpu_base_addr = __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE); | 316 | gic_init(0, 29, __io_address(REALVIEW_PBX_TILE_GIC_DIST_BASE), |
| 317 | gic_dist_init(0, __io_address(REALVIEW_PBX_TILE_GIC_DIST_BASE), | 317 | __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE)); |
| 318 | 29); | ||
| 319 | gic_cpu_init(0, __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE)); | ||
| 320 | } else { | 318 | } else { |
| 321 | gic_cpu_base_addr = __io_address(REALVIEW_PBX_GIC_CPU_BASE); | 319 | gic_init(0, IRQ_PBX_GIC_START, |
| 322 | gic_dist_init(0, __io_address(REALVIEW_PBX_GIC_DIST_BASE), | 320 | __io_address(REALVIEW_PBX_GIC_DIST_BASE), |
| 323 | IRQ_PBX_GIC_START); | 321 | __io_address(REALVIEW_PBX_GIC_CPU_BASE)); |
| 324 | gic_cpu_init(0, __io_address(REALVIEW_PBX_GIC_CPU_BASE)); | ||
| 325 | } | 322 | } |
| 326 | } | 323 | } |
| 327 | 324 | ||
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig index 6983cb4d4cae..e82ab4aa7ab9 100644 --- a/arch/arm/mach-s3c2412/Kconfig +++ b/arch/arm/mach-s3c2412/Kconfig | |||
| @@ -59,7 +59,7 @@ config MACH_JIVE | |||
| 59 | Say Y here if you are using the Logitech Jive. | 59 | Say Y here if you are using the Logitech Jive. |
| 60 | 60 | ||
| 61 | config MACH_JIVE_SHOW_BOOTLOADER | 61 | config MACH_JIVE_SHOW_BOOTLOADER |
| 62 | bool "Allow access to bootloader partitions in MTD" | 62 | bool "Allow access to bootloader partitions in MTD (EXPERIMENTAL)" |
| 63 | depends on MACH_JIVE && EXPERIMENTAL | 63 | depends on MACH_JIVE && EXPERIMENTAL |
| 64 | 64 | ||
| 65 | config MACH_SMDK2413 | 65 | config MACH_SMDK2413 |
diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c index 82ce4aa6d61a..72ab289e7816 100644 --- a/arch/arm/mach-s5pv310/cpu.c +++ b/arch/arm/mach-s5pv310/cpu.c | |||
| @@ -24,8 +24,6 @@ | |||
| 24 | 24 | ||
| 25 | #include <mach/regs-irq.h> | 25 | #include <mach/regs-irq.h> |
| 26 | 26 | ||
| 27 | void __iomem *gic_cpu_base_addr; | ||
| 28 | |||
| 29 | extern int combiner_init(unsigned int combiner_nr, void __iomem *base, | 27 | extern int combiner_init(unsigned int combiner_nr, void __iomem *base, |
| 30 | unsigned int irq_start); | 28 | unsigned int irq_start); |
| 31 | extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq); | 29 | extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq); |
| @@ -122,9 +120,7 @@ void __init s5pv310_init_irq(void) | |||
| 122 | { | 120 | { |
| 123 | int irq; | 121 | int irq; |
| 124 | 122 | ||
| 125 | gic_cpu_base_addr = S5P_VA_GIC_CPU; | 123 | gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); |
| 126 | gic_dist_init(0, S5P_VA_GIC_DIST, IRQ_LOCALTIMER); | ||
| 127 | gic_cpu_init(0, S5P_VA_GIC_CPU); | ||
| 128 | 124 | ||
| 129 | for (irq = 0; irq < MAX_COMBINER_NR; irq++) { | 125 | for (irq = 0; irq < MAX_COMBINER_NR; irq++) { |
| 130 | combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), | 126 | combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), |
diff --git a/arch/arm/mach-s5pv310/hotplug.c b/arch/arm/mach-s5pv310/hotplug.c index 03652c3605f6..afa5392d9fc0 100644 --- a/arch/arm/mach-s5pv310/hotplug.c +++ b/arch/arm/mach-s5pv310/hotplug.c | |||
| @@ -13,14 +13,11 @@ | |||
| 13 | #include <linux/kernel.h> | 13 | #include <linux/kernel.h> |
| 14 | #include <linux/errno.h> | 14 | #include <linux/errno.h> |
| 15 | #include <linux/smp.h> | 15 | #include <linux/smp.h> |
| 16 | #include <linux/completion.h> | ||
| 17 | 16 | ||
| 18 | #include <asm/cacheflush.h> | 17 | #include <asm/cacheflush.h> |
| 19 | 18 | ||
| 20 | extern volatile int pen_release; | 19 | extern volatile int pen_release; |
| 21 | 20 | ||
| 22 | static DECLARE_COMPLETION(cpu_killed); | ||
| 23 | |||
| 24 | static inline void cpu_enter_lowpower(void) | 21 | static inline void cpu_enter_lowpower(void) |
| 25 | { | 22 | { |
| 26 | unsigned int v; | 23 | unsigned int v; |
| @@ -33,13 +30,13 @@ static inline void cpu_enter_lowpower(void) | |||
| 33 | * Turn off coherency | 30 | * Turn off coherency |
| 34 | */ | 31 | */ |
| 35 | " mrc p15, 0, %0, c1, c0, 1\n" | 32 | " mrc p15, 0, %0, c1, c0, 1\n" |
| 36 | " bic %0, %0, #0x20\n" | 33 | " bic %0, %0, %2\n" |
| 37 | " mcr p15, 0, %0, c1, c0, 1\n" | 34 | " mcr p15, 0, %0, c1, c0, 1\n" |
| 38 | " mrc p15, 0, %0, c1, c0, 0\n" | 35 | " mrc p15, 0, %0, c1, c0, 0\n" |
| 39 | " bic %0, %0, #0x04\n" | 36 | " bic %0, %0, #0x04\n" |
| 40 | " mcr p15, 0, %0, c1, c0, 0\n" | 37 | " mcr p15, 0, %0, c1, c0, 0\n" |
| 41 | : "=&r" (v) | 38 | : "=&r" (v) |
| 42 | : "r" (0) | 39 | : "r" (0), "Ir" (CR_C) |
| 43 | : "cc"); | 40 | : "cc"); |
| 44 | } | 41 | } |
| 45 | 42 | ||
| @@ -49,17 +46,17 @@ static inline void cpu_leave_lowpower(void) | |||
| 49 | 46 | ||
| 50 | asm volatile( | 47 | asm volatile( |
| 51 | "mrc p15, 0, %0, c1, c0, 0\n" | 48 | "mrc p15, 0, %0, c1, c0, 0\n" |
| 52 | " orr %0, %0, #0x04\n" | 49 | " orr %0, %0, %1\n" |
| 53 | " mcr p15, 0, %0, c1, c0, 0\n" | 50 | " mcr p15, 0, %0, c1, c0, 0\n" |
| 54 | " mrc p15, 0, %0, c1, c0, 1\n" | 51 | " mrc p15, 0, %0, c1, c0, 1\n" |
| 55 | " orr %0, %0, #0x20\n" | 52 | " orr %0, %0, #0x20\n" |
| 56 | " mcr p15, 0, %0, c1, c0, 1\n" | 53 | " mcr p15, 0, %0, c1, c0, 1\n" |
| 57 | : "=&r" (v) | 54 | : "=&r" (v) |
| 58 | : | 55 | : "Ir" (CR_C) |
| 59 | : "cc"); | 56 | : "cc"); |
| 60 | } | 57 | } |
| 61 | 58 | ||
| 62 | static inline void platform_do_lowpower(unsigned int cpu) | 59 | static inline void platform_do_lowpower(unsigned int cpu, int *spurious) |
| 63 | { | 60 | { |
| 64 | /* | 61 | /* |
| 65 | * there is no power-control hardware on this platform, so all | 62 | * there is no power-control hardware on this platform, so all |
| @@ -83,22 +80,19 @@ static inline void platform_do_lowpower(unsigned int cpu) | |||
| 83 | } | 80 | } |
| 84 | 81 | ||
| 85 | /* | 82 | /* |
| 86 | * getting here, means that we have come out of WFI without | 83 | * Getting here, means that we have come out of WFI without |
| 87 | * having been woken up - this shouldn't happen | 84 | * having been woken up - this shouldn't happen |
| 88 | * | 85 | * |
| 89 | * The trouble is, letting people know about this is not really | 86 | * Just note it happening - when we're woken, we can report |
| 90 | * possible, since we are currently running incoherently, and | 87 | * its occurrence. |
| 91 | * therefore cannot safely call printk() or anything else | ||
| 92 | */ | 88 | */ |
| 93 | #ifdef DEBUG | 89 | (*spurious)++; |
| 94 | printk(KERN_WARN "CPU%u: spurious wakeup call\n", cpu); | ||
| 95 | #endif | ||
| 96 | } | 90 | } |
| 97 | } | 91 | } |
| 98 | 92 | ||
| 99 | int platform_cpu_kill(unsigned int cpu) | 93 | int platform_cpu_kill(unsigned int cpu) |
| 100 | { | 94 | { |
| 101 | return wait_for_completion_timeout(&cpu_killed, 5000); | 95 | return 1; |
| 102 | } | 96 | } |
| 103 | 97 | ||
| 104 | /* | 98 | /* |
| @@ -108,30 +102,22 @@ int platform_cpu_kill(unsigned int cpu) | |||
| 108 | */ | 102 | */ |
| 109 | void platform_cpu_die(unsigned int cpu) | 103 | void platform_cpu_die(unsigned int cpu) |
| 110 | { | 104 | { |
| 111 | #ifdef DEBUG | 105 | int spurious = 0; |
| 112 | unsigned int this_cpu = hard_smp_processor_id(); | ||
| 113 | |||
| 114 | if (cpu != this_cpu) { | ||
| 115 | printk(KERN_CRIT "Eek! platform_cpu_die running on %u, should be %u\n", | ||
| 116 | this_cpu, cpu); | ||
| 117 | BUG(); | ||
| 118 | } | ||
| 119 | #endif | ||
| 120 | |||
| 121 | printk(KERN_NOTICE "CPU%u: shutdown\n", cpu); | ||
| 122 | complete(&cpu_killed); | ||
| 123 | 106 | ||
| 124 | /* | 107 | /* |
| 125 | * we're ready for shutdown now, so do it | 108 | * we're ready for shutdown now, so do it |
| 126 | */ | 109 | */ |
| 127 | cpu_enter_lowpower(); | 110 | cpu_enter_lowpower(); |
| 128 | platform_do_lowpower(cpu); | 111 | platform_do_lowpower(cpu, &spurious); |
| 129 | 112 | ||
| 130 | /* | 113 | /* |
| 131 | * bring this CPU back into the world of cache | 114 | * bring this CPU back into the world of cache |
| 132 | * coherency, and then restore interrupts | 115 | * coherency, and then restore interrupts |
| 133 | */ | 116 | */ |
| 134 | cpu_leave_lowpower(); | 117 | cpu_leave_lowpower(); |
| 118 | |||
| 119 | if (spurious) | ||
| 120 | pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious); | ||
| 135 | } | 121 | } |
| 136 | 122 | ||
| 137 | int platform_cpu_disable(unsigned int cpu) | 123 | int platform_cpu_disable(unsigned int cpu) |
diff --git a/arch/arm/mach-s5pv310/include/mach/smp.h b/arch/arm/mach-s5pv310/include/mach/smp.h index b7ec252384f4..393ccbd52c4a 100644 --- a/arch/arm/mach-s5pv310/include/mach/smp.h +++ b/arch/arm/mach-s5pv310/include/mach/smp.h | |||
| @@ -7,16 +7,13 @@ | |||
| 7 | #define ASM_ARCH_SMP_H __FILE__ | 7 | #define ASM_ARCH_SMP_H __FILE__ |
| 8 | 8 | ||
| 9 | #include <asm/hardware/gic.h> | 9 | #include <asm/hardware/gic.h> |
| 10 | #include <asm/smp_mpidr.h> | ||
| 11 | |||
| 12 | extern void __iomem *gic_cpu_base_addr; | ||
| 13 | 10 | ||
| 14 | /* | 11 | /* |
| 15 | * We use IRQ1 as the IPI | 12 | * We use IRQ1 as the IPI |
| 16 | */ | 13 | */ |
| 17 | static inline void smp_cross_call(const struct cpumask *mask) | 14 | static inline void smp_cross_call(const struct cpumask *mask, int ipi) |
| 18 | { | 15 | { |
| 19 | gic_raise_softirq(mask, 1); | 16 | gic_raise_softirq(mask, ipi); |
| 20 | } | 17 | } |
| 21 | 18 | ||
| 22 | #endif | 19 | #endif |
diff --git a/arch/arm/mach-s5pv310/platsmp.c b/arch/arm/mach-s5pv310/platsmp.c index d357c198edee..34093b069f67 100644 --- a/arch/arm/mach-s5pv310/platsmp.c +++ b/arch/arm/mach-s5pv310/platsmp.c | |||
| @@ -22,7 +22,6 @@ | |||
| 22 | #include <linux/io.h> | 22 | #include <linux/io.h> |
| 23 | 23 | ||
| 24 | #include <asm/cacheflush.h> | 24 | #include <asm/cacheflush.h> |
| 25 | #include <asm/localtimer.h> | ||
| 26 | #include <asm/smp_scu.h> | 25 | #include <asm/smp_scu.h> |
| 27 | #include <asm/unified.h> | 26 | #include <asm/unified.h> |
| 28 | 27 | ||
| @@ -38,6 +37,19 @@ extern void s5pv310_secondary_startup(void); | |||
| 38 | 37 | ||
| 39 | volatile int __cpuinitdata pen_release = -1; | 38 | volatile int __cpuinitdata pen_release = -1; |
| 40 | 39 | ||
| 40 | /* | ||
| 41 | * Write pen_release in a way that is guaranteed to be visible to all | ||
| 42 | * observers, irrespective of whether they're taking part in coherency | ||
| 43 | * or not. This is necessary for the hotplug code to work reliably. | ||
| 44 | */ | ||
| 45 | static void write_pen_release(int val) | ||
| 46 | { | ||
| 47 | pen_release = val; | ||
| 48 | smp_wmb(); | ||
| 49 | __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); | ||
| 50 | outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); | ||
| 51 | } | ||
| 52 | |||
| 41 | static void __iomem *scu_base_addr(void) | 53 | static void __iomem *scu_base_addr(void) |
| 42 | { | 54 | { |
| 43 | return (void __iomem *)(S5P_VA_SCU); | 55 | return (void __iomem *)(S5P_VA_SCU); |
| @@ -47,21 +59,18 @@ static DEFINE_SPINLOCK(boot_lock); | |||
| 47 | 59 | ||
| 48 | void __cpuinit platform_secondary_init(unsigned int cpu) | 60 | void __cpuinit platform_secondary_init(unsigned int cpu) |
| 49 | { | 61 | { |
| 50 | trace_hardirqs_off(); | ||
| 51 | |||
| 52 | /* | 62 | /* |
| 53 | * if any interrupts are already enabled for the primary | 63 | * if any interrupts are already enabled for the primary |
| 54 | * core (e.g. timer irq), then they will not have been enabled | 64 | * core (e.g. timer irq), then they will not have been enabled |
| 55 | * for us: do so | 65 | * for us: do so |
| 56 | */ | 66 | */ |
| 57 | gic_cpu_init(0, gic_cpu_base_addr); | 67 | gic_secondary_init(0); |
| 58 | 68 | ||
| 59 | /* | 69 | /* |
| 60 | * let the primary processor know we're out of the | 70 | * let the primary processor know we're out of the |
| 61 | * pen, then head off into the C entry point | 71 | * pen, then head off into the C entry point |
| 62 | */ | 72 | */ |
| 63 | pen_release = -1; | 73 | write_pen_release(-1); |
| 64 | smp_wmb(); | ||
| 65 | 74 | ||
| 66 | /* | 75 | /* |
| 67 | * Synchronise with the boot thread. | 76 | * Synchronise with the boot thread. |
| @@ -88,16 +97,14 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) | |||
| 88 | * Note that "pen_release" is the hardware CPU ID, whereas | 97 | * Note that "pen_release" is the hardware CPU ID, whereas |
| 89 | * "cpu" is Linux's internal ID. | 98 | * "cpu" is Linux's internal ID. |
| 90 | */ | 99 | */ |
| 91 | pen_release = cpu; | 100 | write_pen_release(cpu); |
| 92 | __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); | ||
| 93 | outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); | ||
| 94 | 101 | ||
| 95 | /* | 102 | /* |
| 96 | * Send the secondary CPU a soft interrupt, thereby causing | 103 | * Send the secondary CPU a soft interrupt, thereby causing |
| 97 | * the boot monitor to read the system wide flags register, | 104 | * the boot monitor to read the system wide flags register, |
| 98 | * and branch to the address found there. | 105 | * and branch to the address found there. |
| 99 | */ | 106 | */ |
| 100 | smp_cross_call(cpumask_of(cpu)); | 107 | smp_cross_call(cpumask_of(cpu), 1); |
| 101 | 108 | ||
| 102 | timeout = jiffies + (1 * HZ); | 109 | timeout = jiffies + (1 * HZ); |
| 103 | while (time_before(jiffies, timeout)) { | 110 | while (time_before(jiffies, timeout)) { |
| @@ -130,13 +137,6 @@ void __init smp_init_cpus(void) | |||
| 130 | ncores = scu_base ? scu_get_core_count(scu_base) : 1; | 137 | ncores = scu_base ? scu_get_core_count(scu_base) : 1; |
| 131 | 138 | ||
| 132 | /* sanity check */ | 139 | /* sanity check */ |
| 133 | if (ncores == 0) { | ||
| 134 | printk(KERN_ERR | ||
| 135 | "S5PV310: strange CM count of 0? Default to 1\n"); | ||
| 136 | |||
| 137 | ncores = 1; | ||
| 138 | } | ||
| 139 | |||
| 140 | if (ncores > NR_CPUS) { | 140 | if (ncores > NR_CPUS) { |
| 141 | printk(KERN_WARNING | 141 | printk(KERN_WARNING |
| 142 | "S5PV310: no. of cores (%d) greater than configured " | 142 | "S5PV310: no. of cores (%d) greater than configured " |
| @@ -149,18 +149,10 @@ void __init smp_init_cpus(void) | |||
| 149 | set_cpu_possible(i, true); | 149 | set_cpu_possible(i, true); |
| 150 | } | 150 | } |
| 151 | 151 | ||
| 152 | void __init smp_prepare_cpus(unsigned int max_cpus) | 152 | void __init platform_smp_prepare_cpus(unsigned int max_cpus) |
| 153 | { | 153 | { |
| 154 | unsigned int ncores = num_possible_cpus(); | ||
| 155 | unsigned int cpu = smp_processor_id(); | ||
| 156 | int i; | 154 | int i; |
| 157 | 155 | ||
| 158 | smp_store_cpu_info(cpu); | ||
| 159 | |||
| 160 | /* are we trying to boot more cores than exist? */ | ||
| 161 | if (max_cpus > ncores) | ||
| 162 | max_cpus = ncores; | ||
| 163 | |||
| 164 | /* | 156 | /* |
| 165 | * Initialise the present map, which describes the set of CPUs | 157 | * Initialise the present map, which describes the set of CPUs |
| 166 | * actually populated at the present time. | 158 | * actually populated at the present time. |
| @@ -168,25 +160,13 @@ void __init smp_prepare_cpus(unsigned int max_cpus) | |||
| 168 | for (i = 0; i < max_cpus; i++) | 160 | for (i = 0; i < max_cpus; i++) |
| 169 | set_cpu_present(i, true); | 161 | set_cpu_present(i, true); |
| 170 | 162 | ||
| 163 | scu_enable(scu_base_addr()); | ||
| 164 | |||
| 171 | /* | 165 | /* |
| 172 | * Initialise the SCU if there are more than one CPU and let | 166 | * Write the address of secondary startup into the |
| 173 | * them know where to start. | 167 | * system-wide flags register. The boot monitor waits |
| 168 | * until it receives a soft interrupt, and then the | ||
| 169 | * secondary CPU branches to this address. | ||
| 174 | */ | 170 | */ |
| 175 | if (max_cpus > 1) { | ||
| 176 | /* | ||
| 177 | * Enable the local timer or broadcast device for the | ||
| 178 | * boot CPU, but only if we have more than one CPU. | ||
| 179 | */ | ||
| 180 | percpu_timer_setup(); | ||
| 181 | |||
| 182 | scu_enable(scu_base_addr()); | ||
| 183 | |||
| 184 | /* | ||
| 185 | * Write the address of secondary startup into the | ||
| 186 | * system-wide flags register. The boot monitor waits | ||
| 187 | * until it receives a soft interrupt, and then the | ||
| 188 | * secondary CPU branches to this address. | ||
| 189 | */ | ||
| 190 | __raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup)), S5P_VA_SYSRAM); | 171 | __raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup)), S5P_VA_SYSRAM); |
| 191 | } | ||
| 192 | } | 172 | } |
diff --git a/arch/arm/mach-s5pv310/time.c b/arch/arm/mach-s5pv310/time.c index 01b012ad1bfd..b262d4615331 100644 --- a/arch/arm/mach-s5pv310/time.c +++ b/arch/arm/mach-s5pv310/time.c | |||
| @@ -211,7 +211,6 @@ struct clocksource pwm_clocksource = { | |||
| 211 | .rating = 250, | 211 | .rating = 250, |
| 212 | .read = s5pv310_pwm4_read, | 212 | .read = s5pv310_pwm4_read, |
| 213 | .mask = CLOCKSOURCE_MASK(32), | 213 | .mask = CLOCKSOURCE_MASK(32), |
| 214 | .shift = 20, | ||
| 215 | .flags = CLOCK_SOURCE_IS_CONTINUOUS , | 214 | .flags = CLOCK_SOURCE_IS_CONTINUOUS , |
| 216 | }; | 215 | }; |
| 217 | 216 | ||
| @@ -230,10 +229,7 @@ static void __init s5pv310_clocksource_init(void) | |||
| 230 | s5pv310_pwm_init(4, ~0); | 229 | s5pv310_pwm_init(4, ~0); |
| 231 | s5pv310_pwm_start(4, 1); | 230 | s5pv310_pwm_start(4, 1); |
| 232 | 231 | ||
| 233 | pwm_clocksource.mult = | 232 | if (clocksource_register_hz(&pwm_clocksource, clock_rate)) |
| 234 | clocksource_khz2mult(clock_rate/1000, pwm_clocksource.shift); | ||
| 235 | |||
| 236 | if (clocksource_register(&pwm_clocksource)) | ||
| 237 | panic("%s: can't register clocksource\n", pwm_clocksource.name); | 233 | panic("%s: can't register clocksource\n", pwm_clocksource.name); |
| 238 | } | 234 | } |
| 239 | 235 | ||
diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig index 5da8c35aa0de..42625e4d949a 100644 --- a/arch/arm/mach-sa1100/Kconfig +++ b/arch/arm/mach-sa1100/Kconfig | |||
| @@ -118,6 +118,16 @@ config SA1100_LART | |||
| 118 | (also known as the LART). See <http://www.lartmaker.nl/> for | 118 | (also known as the LART). See <http://www.lartmaker.nl/> for |
| 119 | information on the LART. | 119 | information on the LART. |
| 120 | 120 | ||
| 121 | config SA1100_NANOENGINE | ||
| 122 | bool "nanoEngine" | ||
| 123 | select CPU_FREQ_SA1110 | ||
| 124 | select PCI | ||
| 125 | select PCI_NANOENGINE | ||
| 126 | help | ||
| 127 | Say Y here if you are using the Bright Star Engineering nanoEngine. | ||
| 128 | See <http://www.brightstareng.com/arm/nanoeng.htm> for information | ||
| 129 | on the BSE nanoEngine. | ||
| 130 | |||
| 121 | config SA1100_PLEB | 131 | config SA1100_PLEB |
| 122 | bool "PLEB" | 132 | bool "PLEB" |
| 123 | select CPU_FREQ_SA1100 | 133 | select CPU_FREQ_SA1100 |
diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile index 89349c1dd7a6..e697691eed28 100644 --- a/arch/arm/mach-sa1100/Makefile +++ b/arch/arm/mach-sa1100/Makefile | |||
| @@ -37,6 +37,9 @@ obj-$(CONFIG_SA1100_JORNADA720_SSP) += jornada720_ssp.o | |||
| 37 | obj-$(CONFIG_SA1100_LART) += lart.o | 37 | obj-$(CONFIG_SA1100_LART) += lart.o |
| 38 | led-$(CONFIG_SA1100_LART) += leds-lart.o | 38 | led-$(CONFIG_SA1100_LART) += leds-lart.o |
| 39 | 39 | ||
| 40 | obj-$(CONFIG_SA1100_NANOENGINE) += nanoengine.o | ||
| 41 | obj-$(CONFIG_PCI_NANOENGINE) += pci-nanoengine.o | ||
| 42 | |||
| 40 | obj-$(CONFIG_SA1100_PLEB) += pleb.o | 43 | obj-$(CONFIG_SA1100_PLEB) += pleb.o |
| 41 | 44 | ||
| 42 | obj-$(CONFIG_SA1100_SHANNON) += shannon.o | 45 | obj-$(CONFIG_SA1100_SHANNON) += shannon.o |
diff --git a/arch/arm/mach-sa1100/cpu-sa1100.c b/arch/arm/mach-sa1100/cpu-sa1100.c index 96f7dc103b59..07d4e8ba3719 100644 --- a/arch/arm/mach-sa1100/cpu-sa1100.c +++ b/arch/arm/mach-sa1100/cpu-sa1100.c | |||
| @@ -94,48 +94,47 @@ | |||
| 94 | 94 | ||
| 95 | #include "generic.h" | 95 | #include "generic.h" |
| 96 | 96 | ||
| 97 | typedef struct { | 97 | struct sa1100_dram_regs { |
| 98 | int speed; | 98 | int speed; |
| 99 | u32 mdcnfg; | 99 | u32 mdcnfg; |
| 100 | u32 mdcas0; | 100 | u32 mdcas0; |
| 101 | u32 mdcas1; | 101 | u32 mdcas1; |
| 102 | u32 mdcas2; | 102 | u32 mdcas2; |
| 103 | } sa1100_dram_regs_t; | 103 | }; |
| 104 | 104 | ||
| 105 | 105 | ||
| 106 | static struct cpufreq_driver sa1100_driver; | 106 | static struct cpufreq_driver sa1100_driver; |
| 107 | 107 | ||
| 108 | static sa1100_dram_regs_t sa1100_dram_settings[] = | 108 | static struct sa1100_dram_regs sa1100_dram_settings[] = { |
| 109 | { | 109 | /*speed, mdcnfg, mdcas0, mdcas1, mdcas2, clock freq */ |
| 110 | /* speed, mdcnfg, mdcas0, mdcas1, mdcas2 clock frequency */ | 110 | { 59000, 0x00dc88a3, 0xcccccccf, 0xfffffffc, 0xffffffff},/* 59.0 MHz */ |
| 111 | { 59000, 0x00dc88a3, 0xcccccccf, 0xfffffffc, 0xffffffff }, /* 59.0 MHz */ | 111 | { 73700, 0x011490a3, 0xcccccccf, 0xfffffffc, 0xffffffff},/* 73.7 MHz */ |
| 112 | { 73700, 0x011490a3, 0xcccccccf, 0xfffffffc, 0xffffffff }, /* 73.7 MHz */ | 112 | { 88500, 0x014e90a3, 0xcccccccf, 0xfffffffc, 0xffffffff},/* 88.5 MHz */ |
| 113 | { 88500, 0x014e90a3, 0xcccccccf, 0xfffffffc, 0xffffffff }, /* 88.5 MHz */ | 113 | {103200, 0x01889923, 0xcccccccf, 0xfffffffc, 0xffffffff},/* 103.2 MHz */ |
| 114 | { 103200, 0x01889923, 0xcccccccf, 0xfffffffc, 0xffffffff }, /* 103.2 MHz */ | 114 | {118000, 0x01c29923, 0x9999998f, 0xfffffff9, 0xffffffff},/* 118.0 MHz */ |
| 115 | { 118000, 0x01c29923, 0x9999998f, 0xfffffff9, 0xffffffff }, /* 118.0 MHz */ | 115 | {132700, 0x01fb2123, 0x9999998f, 0xfffffff9, 0xffffffff},/* 132.7 MHz */ |
| 116 | { 132700, 0x01fb2123, 0x9999998f, 0xfffffff9, 0xffffffff }, /* 132.7 MHz */ | 116 | {147500, 0x02352123, 0x3333330f, 0xfffffff3, 0xffffffff},/* 147.5 MHz */ |
| 117 | { 147500, 0x02352123, 0x3333330f, 0xfffffff3, 0xffffffff }, /* 147.5 MHz */ | 117 | {162200, 0x026b29a3, 0x38e38e1f, 0xfff8e38e, 0xffffffff},/* 162.2 MHz */ |
| 118 | { 162200, 0x026b29a3, 0x38e38e1f, 0xfff8e38e, 0xffffffff }, /* 162.2 MHz */ | 118 | {176900, 0x02a329a3, 0x71c71c1f, 0xfff1c71c, 0xffffffff},/* 176.9 MHz */ |
| 119 | { 176900, 0x02a329a3, 0x71c71c1f, 0xfff1c71c, 0xffffffff }, /* 176.9 MHz */ | 119 | {191700, 0x02dd31a3, 0xe38e383f, 0xffe38e38, 0xffffffff},/* 191.7 MHz */ |
| 120 | { 191700, 0x02dd31a3, 0xe38e383f, 0xffe38e38, 0xffffffff }, /* 191.7 MHz */ | 120 | {206400, 0x03153223, 0xc71c703f, 0xffc71c71, 0xffffffff},/* 206.4 MHz */ |
| 121 | { 206400, 0x03153223, 0xc71c703f, 0xffc71c71, 0xffffffff }, /* 206.4 MHz */ | 121 | {221200, 0x034fba23, 0xc71c703f, 0xffc71c71, 0xffffffff},/* 221.2 MHz */ |
| 122 | { 221200, 0x034fba23, 0xc71c703f, 0xffc71c71, 0xffffffff }, /* 221.2 MHz */ | 122 | {235900, 0x03853a23, 0xe1e1e07f, 0xe1e1e1e1, 0xffffffe1},/* 235.9 MHz */ |
| 123 | { 235900, 0x03853a23, 0xe1e1e07f, 0xe1e1e1e1, 0xffffffe1 }, /* 235.9 MHz */ | 123 | {250700, 0x03bf3aa3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3},/* 250.7 MHz */ |
| 124 | { 250700, 0x03bf3aa3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3 }, /* 250.7 MHz */ | 124 | {265400, 0x03f7c2a3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3},/* 265.4 MHz */ |
| 125 | { 265400, 0x03f7c2a3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3 }, /* 265.4 MHz */ | 125 | {280200, 0x0431c2a3, 0x878780ff, 0x87878787, 0xffffff87},/* 280.2 MHz */ |
| 126 | { 280200, 0x0431c2a3, 0x878780ff, 0x87878787, 0xffffff87 }, /* 280.2 MHz */ | ||
| 127 | { 0, 0, 0, 0, 0 } /* last entry */ | 126 | { 0, 0, 0, 0, 0 } /* last entry */ |
| 128 | }; | 127 | }; |
| 129 | 128 | ||
| 130 | static void sa1100_update_dram_timings(int current_speed, int new_speed) | 129 | static void sa1100_update_dram_timings(int current_speed, int new_speed) |
| 131 | { | 130 | { |
| 132 | sa1100_dram_regs_t *settings = sa1100_dram_settings; | 131 | struct sa1100_dram_regs *settings = sa1100_dram_settings; |
| 133 | 132 | ||
| 134 | /* find speed */ | 133 | /* find speed */ |
| 135 | while (settings->speed != 0) { | 134 | while (settings->speed != 0) { |
| 136 | if(new_speed == settings->speed) | 135 | if (new_speed == settings->speed) |
| 137 | break; | 136 | break; |
| 138 | 137 | ||
| 139 | settings++; | 138 | settings++; |
| 140 | } | 139 | } |
| 141 | 140 | ||
| @@ -149,7 +148,7 @@ static void sa1100_update_dram_timings(int current_speed, int new_speed) | |||
| 149 | /* We're going FASTER, so first relax the memory | 148 | /* We're going FASTER, so first relax the memory |
| 150 | * timings before changing the core frequency | 149 | * timings before changing the core frequency |
| 151 | */ | 150 | */ |
| 152 | 151 | ||
| 153 | /* Half the memory access clock */ | 152 | /* Half the memory access clock */ |
| 154 | MDCNFG |= MDCNFG_CDB2; | 153 | MDCNFG |= MDCNFG_CDB2; |
| 155 | 154 | ||
| @@ -187,7 +186,7 @@ static int sa1100_target(struct cpufreq_policy *policy, | |||
| 187 | struct cpufreq_freqs freqs; | 186 | struct cpufreq_freqs freqs; |
| 188 | 187 | ||
| 189 | new_ppcr = sa11x0_freq_to_ppcr(target_freq); | 188 | new_ppcr = sa11x0_freq_to_ppcr(target_freq); |
| 190 | switch(relation){ | 189 | switch (relation) { |
| 191 | case CPUFREQ_RELATION_L: | 190 | case CPUFREQ_RELATION_L: |
| 192 | if (sa11x0_ppcr_to_freq(new_ppcr) > policy->max) | 191 | if (sa11x0_ppcr_to_freq(new_ppcr) > policy->max) |
| 193 | new_ppcr--; | 192 | new_ppcr--; |
diff --git a/arch/arm/mach-sa1100/cpu-sa1110.c b/arch/arm/mach-sa1100/cpu-sa1110.c index 7252874d328b..675bf8ef97e8 100644 --- a/arch/arm/mach-sa1100/cpu-sa1110.c +++ b/arch/arm/mach-sa1100/cpu-sa1110.c | |||
| @@ -16,28 +16,24 @@ | |||
| 16 | * | 16 | * |
| 17 | * The SDRAM type can be passed on the command line as cpu_sa1110.sdram=type | 17 | * The SDRAM type can be passed on the command line as cpu_sa1110.sdram=type |
| 18 | */ | 18 | */ |
| 19 | #include <linux/moduleparam.h> | ||
| 20 | #include <linux/types.h> | ||
| 21 | #include <linux/kernel.h> | ||
| 22 | #include <linux/sched.h> | ||
| 23 | #include <linux/cpufreq.h> | 19 | #include <linux/cpufreq.h> |
| 24 | #include <linux/delay.h> | 20 | #include <linux/delay.h> |
| 25 | #include <linux/init.h> | 21 | #include <linux/init.h> |
| 26 | #include <linux/io.h> | 22 | #include <linux/kernel.h> |
| 23 | #include <linux/moduleparam.h> | ||
| 24 | #include <linux/types.h> | ||
| 27 | 25 | ||
| 28 | #include <mach/hardware.h> | ||
| 29 | #include <asm/cputype.h> | 26 | #include <asm/cputype.h> |
| 30 | #include <asm/mach-types.h> | 27 | #include <asm/mach-types.h> |
| 31 | #include <asm/system.h> | 28 | |
| 29 | #include <mach/hardware.h> | ||
| 32 | 30 | ||
| 33 | #include "generic.h" | 31 | #include "generic.h" |
| 34 | 32 | ||
| 35 | #undef DEBUG | 33 | #undef DEBUG |
| 36 | 34 | ||
| 37 | static struct cpufreq_driver sa1110_driver; | ||
| 38 | |||
| 39 | struct sdram_params { | 35 | struct sdram_params { |
| 40 | const char name[16]; | 36 | const char name[20]; |
| 41 | u_char rows; /* bits */ | 37 | u_char rows; /* bits */ |
| 42 | u_char cas_latency; /* cycles */ | 38 | u_char cas_latency; /* cycles */ |
| 43 | u_char tck; /* clock cycle time (ns) */ | 39 | u_char tck; /* clock cycle time (ns) */ |
| @@ -107,6 +103,15 @@ static struct sdram_params sdram_tbl[] __initdata = { | |||
| 107 | .twr = 8, | 103 | .twr = 8, |
| 108 | .refresh = 64000, | 104 | .refresh = 64000, |
| 109 | .cas_latency = 3, | 105 | .cas_latency = 3, |
| 106 | }, { /* Micron MT48LC8M16A2TG-75 */ | ||
| 107 | .name = "MT48LC8M16A2TG-75", | ||
| 108 | .rows = 12, | ||
| 109 | .tck = 8, | ||
| 110 | .trcd = 20, | ||
| 111 | .trp = 20, | ||
| 112 | .twr = 8, | ||
| 113 | .refresh = 64000, | ||
| 114 | .cas_latency = 3, | ||
| 110 | }, | 115 | }, |
| 111 | }; | 116 | }; |
| 112 | 117 | ||
| @@ -180,11 +185,13 @@ sdram_calculate_timing(struct sdram_info *sd, u_int cpu_khz, | |||
| 180 | sd->mdrefr |= MDREFR_K1DB2; | 185 | sd->mdrefr |= MDREFR_K1DB2; |
| 181 | 186 | ||
| 182 | /* initial number of '1's in MDCAS + 1 */ | 187 | /* initial number of '1's in MDCAS + 1 */ |
| 183 | set_mdcas(sd->mdcas, sd_khz >= 62000, ns_to_cycles(sdram->trcd, mem_khz)); | 188 | set_mdcas(sd->mdcas, sd_khz >= 62000, |
| 189 | ns_to_cycles(sdram->trcd, mem_khz)); | ||
| 184 | 190 | ||
| 185 | #ifdef DEBUG | 191 | #ifdef DEBUG |
| 186 | printk("MDCNFG: %08x MDREFR: %08x MDCAS0: %08x MDCAS1: %08x MDCAS2: %08x\n", | 192 | printk(KERN_DEBUG "MDCNFG: %08x MDREFR: %08x MDCAS0: %08x MDCAS1: %08x MDCAS2: %08x\n", |
| 187 | sd->mdcnfg, sd->mdrefr, sd->mdcas[0], sd->mdcas[1], sd->mdcas[2]); | 193 | sd->mdcnfg, sd->mdrefr, sd->mdcas[0], sd->mdcas[1], |
| 194 | sd->mdcas[2]); | ||
| 188 | #endif | 195 | #endif |
| 189 | } | 196 | } |
| 190 | 197 | ||
| @@ -213,7 +220,7 @@ sdram_update_refresh(u_int cpu_khz, struct sdram_params *sdram) | |||
| 213 | 220 | ||
| 214 | #ifdef DEBUG | 221 | #ifdef DEBUG |
| 215 | mdelay(250); | 222 | mdelay(250); |
| 216 | printk("new dri value = %d\n", dri); | 223 | printk(KERN_DEBUG "new dri value = %d\n", dri); |
| 217 | #endif | 224 | #endif |
| 218 | 225 | ||
| 219 | sdram_set_refresh(dri); | 226 | sdram_set_refresh(dri); |
| @@ -232,7 +239,7 @@ static int sa1110_target(struct cpufreq_policy *policy, | |||
| 232 | unsigned long flags; | 239 | unsigned long flags; |
| 233 | unsigned int ppcr, unused; | 240 | unsigned int ppcr, unused; |
| 234 | 241 | ||
| 235 | switch(relation){ | 242 | switch (relation) { |
| 236 | case CPUFREQ_RELATION_L: | 243 | case CPUFREQ_RELATION_L: |
| 237 | ppcr = sa11x0_freq_to_ppcr(target_freq); | 244 | ppcr = sa11x0_freq_to_ppcr(target_freq); |
| 238 | if (sa11x0_ppcr_to_freq(ppcr) > policy->max) | 245 | if (sa11x0_ppcr_to_freq(ppcr) > policy->max) |
| @@ -280,11 +287,10 @@ static int sa1110_target(struct cpufreq_policy *policy, | |||
| 280 | * We wait 20ms to be safe. | 287 | * We wait 20ms to be safe. |
| 281 | */ | 288 | */ |
| 282 | sdram_set_refresh(2); | 289 | sdram_set_refresh(2); |
| 283 | if (!irqs_disabled()) { | 290 | if (!irqs_disabled()) |
| 284 | msleep(20); | 291 | msleep(20); |
| 285 | } else { | 292 | else |
| 286 | mdelay(20); | 293 | mdelay(20); |
| 287 | } | ||
| 288 | 294 | ||
| 289 | /* | 295 | /* |
| 290 | * Reprogram the DRAM timings with interrupts disabled, and | 296 | * Reprogram the DRAM timings with interrupts disabled, and |
| @@ -295,7 +301,7 @@ static int sa1110_target(struct cpufreq_policy *policy, | |||
| 295 | local_irq_save(flags); | 301 | local_irq_save(flags); |
| 296 | asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); | 302 | asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); |
| 297 | udelay(10); | 303 | udelay(10); |
| 298 | __asm__ __volatile__(" \n\ | 304 | __asm__ __volatile__("\n\ |
| 299 | b 2f \n\ | 305 | b 2f \n\ |
| 300 | .align 5 \n\ | 306 | .align 5 \n\ |
| 301 | 1: str %3, [%1, #0] @ MDCNFG \n\ | 307 | 1: str %3, [%1, #0] @ MDCNFG \n\ |
| @@ -336,7 +342,9 @@ static int __init sa1110_cpu_init(struct cpufreq_policy *policy) | |||
| 336 | return 0; | 342 | return 0; |
| 337 | } | 343 | } |
| 338 | 344 | ||
| 339 | static struct cpufreq_driver sa1110_driver = { | 345 | /* sa1110_driver needs __refdata because it must remain after init registers |
| 346 | * it with cpufreq_register_driver() */ | ||
| 347 | static struct cpufreq_driver sa1110_driver __refdata = { | ||
| 340 | .flags = CPUFREQ_STICKY, | 348 | .flags = CPUFREQ_STICKY, |
| 341 | .verify = sa11x0_verify_speed, | 349 | .verify = sa11x0_verify_speed, |
| 342 | .target = sa1110_target, | 350 | .target = sa1110_target, |
| @@ -349,7 +357,8 @@ static struct sdram_params *sa1110_find_sdram(const char *name) | |||
| 349 | { | 357 | { |
| 350 | struct sdram_params *sdram; | 358 | struct sdram_params *sdram; |
| 351 | 359 | ||
| 352 | for (sdram = sdram_tbl; sdram < sdram_tbl + ARRAY_SIZE(sdram_tbl); sdram++) | 360 | for (sdram = sdram_tbl; sdram < sdram_tbl + ARRAY_SIZE(sdram_tbl); |
| 361 | sdram++) | ||
| 353 | if (strcmp(name, sdram->name) == 0) | 362 | if (strcmp(name, sdram->name) == 0) |
| 354 | return sdram; | 363 | return sdram; |
| 355 | 364 | ||
| @@ -369,14 +378,14 @@ static int __init sa1110_clk_init(void) | |||
| 369 | if (!name[0]) { | 378 | if (!name[0]) { |
| 370 | if (machine_is_assabet()) | 379 | if (machine_is_assabet()) |
| 371 | name = "TC59SM716-CL3"; | 380 | name = "TC59SM716-CL3"; |
| 372 | |||
| 373 | if (machine_is_pt_system3()) | 381 | if (machine_is_pt_system3()) |
| 374 | name = "K4S641632D"; | 382 | name = "K4S641632D"; |
| 375 | |||
| 376 | if (machine_is_h3100()) | 383 | if (machine_is_h3100()) |
| 377 | name = "KM416S4030CT"; | 384 | name = "KM416S4030CT"; |
| 378 | if (machine_is_jornada720()) | 385 | if (machine_is_jornada720()) |
| 379 | name = "K4S281632B-1H"; | 386 | name = "K4S281632B-1H"; |
| 387 | if (machine_is_nanoengine()) | ||
| 388 | name = "MT48LC8M16A2TG-75"; | ||
| 380 | } | 389 | } |
| 381 | 390 | ||
| 382 | sdram = sa1110_find_sdram(name); | 391 | sdram = sa1110_find_sdram(name); |
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c index 3c1fcd696714..59d14f0fdcf8 100644 --- a/arch/arm/mach-sa1100/generic.c +++ b/arch/arm/mach-sa1100/generic.c | |||
| @@ -16,9 +16,7 @@ | |||
| 16 | #include <linux/pm.h> | 16 | #include <linux/pm.h> |
| 17 | #include <linux/cpufreq.h> | 17 | #include <linux/cpufreq.h> |
| 18 | #include <linux/ioport.h> | 18 | #include <linux/ioport.h> |
| 19 | #include <linux/sched.h> /* just for sched_clock() - funny that */ | ||
| 20 | #include <linux/platform_device.h> | 19 | #include <linux/platform_device.h> |
| 21 | #include <linux/cnt32_to_63.h> | ||
| 22 | 20 | ||
| 23 | #include <asm/div64.h> | 21 | #include <asm/div64.h> |
| 24 | #include <mach/hardware.h> | 22 | #include <mach/hardware.h> |
| @@ -110,27 +108,6 @@ unsigned int sa11x0_getspeed(unsigned int cpu) | |||
| 110 | } | 108 | } |
| 111 | 109 | ||
| 112 | /* | 110 | /* |
| 113 | * This is the SA11x0 sched_clock implementation. This has | ||
| 114 | * a resolution of 271ns, and a maximum value of 32025597s (370 days). | ||
| 115 | * | ||
| 116 | * The return value is guaranteed to be monotonic in that range as | ||
| 117 | * long as there is always less than 582 seconds between successive | ||
| 118 | * calls to this function. | ||
| 119 | * | ||
| 120 | * ( * 1E9 / 3686400 => * 78125 / 288) | ||
| 121 | */ | ||
| 122 | unsigned long long sched_clock(void) | ||
| 123 | { | ||
| 124 | unsigned long long v = cnt32_to_63(OSCR); | ||
| 125 | |||
| 126 | /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */ | ||
| 127 | v *= 78125<<1; | ||
| 128 | do_div(v, 288<<1); | ||
| 129 | |||
| 130 | return v; | ||
| 131 | } | ||
| 132 | |||
| 133 | /* | ||
| 134 | * Default power-off for SA1100 | 111 | * Default power-off for SA1100 |
| 135 | */ | 112 | */ |
| 136 | static void sa1100_power_off(void) | 113 | static void sa1100_power_off(void) |
| @@ -163,10 +140,15 @@ static void sa11x0_register_device(struct platform_device *dev, void *data) | |||
| 163 | 140 | ||
| 164 | static struct resource sa11x0udc_resources[] = { | 141 | static struct resource sa11x0udc_resources[] = { |
| 165 | [0] = { | 142 | [0] = { |
| 166 | .start = 0x80000000, | 143 | .start = __PREG(Ser0UDCCR), |
| 167 | .end = 0x8000ffff, | 144 | .end = __PREG(Ser0UDCCR) + 0xffff, |
| 168 | .flags = IORESOURCE_MEM, | 145 | .flags = IORESOURCE_MEM, |
| 169 | }, | 146 | }, |
| 147 | [1] = { | ||
| 148 | .start = IRQ_Ser0UDC, | ||
| 149 | .end = IRQ_Ser0UDC, | ||
| 150 | .flags = IORESOURCE_IRQ, | ||
| 151 | }, | ||
| 170 | }; | 152 | }; |
| 171 | 153 | ||
| 172 | static u64 sa11x0udc_dma_mask = 0xffffffffUL; | 154 | static u64 sa11x0udc_dma_mask = 0xffffffffUL; |
| @@ -184,10 +166,15 @@ static struct platform_device sa11x0udc_device = { | |||
| 184 | 166 | ||
| 185 | static struct resource sa11x0uart1_resources[] = { | 167 | static struct resource sa11x0uart1_resources[] = { |
| 186 | [0] = { | 168 | [0] = { |
| 187 | .start = 0x80010000, | 169 | .start = __PREG(Ser1UTCR0), |
| 188 | .end = 0x8001ffff, | 170 | .end = __PREG(Ser1UTCR0) + 0xffff, |
| 189 | .flags = IORESOURCE_MEM, | 171 | .flags = IORESOURCE_MEM, |
| 190 | }, | 172 | }, |
| 173 | [1] = { | ||
| 174 | .start = IRQ_Ser1UART, | ||
| 175 | .end = IRQ_Ser1UART, | ||
| 176 | .flags = IORESOURCE_IRQ, | ||
| 177 | }, | ||
| 191 | }; | 178 | }; |
| 192 | 179 | ||
| 193 | static struct platform_device sa11x0uart1_device = { | 180 | static struct platform_device sa11x0uart1_device = { |
| @@ -199,10 +186,15 @@ static struct platform_device sa11x0uart1_device = { | |||
| 199 | 186 | ||
| 200 | static struct resource sa11x0uart3_resources[] = { | 187 | static struct resource sa11x0uart3_resources[] = { |
| 201 | [0] = { | 188 | [0] = { |
| 202 | .start = 0x80050000, | 189 | .start = __PREG(Ser3UTCR0), |
| 203 | .end = 0x8005ffff, | 190 | .end = __PREG(Ser3UTCR0) + 0xffff, |
| 204 | .flags = IORESOURCE_MEM, | 191 | .flags = IORESOURCE_MEM, |
| 205 | }, | 192 | }, |
| 193 | [1] = { | ||
| 194 | .start = IRQ_Ser3UART, | ||
| 195 | .end = IRQ_Ser3UART, | ||
| 196 | .flags = IORESOURCE_IRQ, | ||
| 197 | }, | ||
| 206 | }; | 198 | }; |
| 207 | 199 | ||
| 208 | static struct platform_device sa11x0uart3_device = { | 200 | static struct platform_device sa11x0uart3_device = { |
| @@ -214,10 +206,15 @@ static struct platform_device sa11x0uart3_device = { | |||
| 214 | 206 | ||
| 215 | static struct resource sa11x0mcp_resources[] = { | 207 | static struct resource sa11x0mcp_resources[] = { |
| 216 | [0] = { | 208 | [0] = { |
| 217 | .start = 0x80060000, | 209 | .start = __PREG(Ser4MCCR0), |
| 218 | .end = 0x8006ffff, | 210 | .end = __PREG(Ser4MCCR0) + 0xffff, |
| 219 | .flags = IORESOURCE_MEM, | 211 | .flags = IORESOURCE_MEM, |
| 220 | }, | 212 | }, |
| 213 | [1] = { | ||
| 214 | .start = IRQ_Ser4MCP, | ||
| 215 | .end = IRQ_Ser4MCP, | ||
| 216 | .flags = IORESOURCE_IRQ, | ||
| 217 | }, | ||
| 221 | }; | 218 | }; |
| 222 | 219 | ||
| 223 | static u64 sa11x0mcp_dma_mask = 0xffffffffUL; | 220 | static u64 sa11x0mcp_dma_mask = 0xffffffffUL; |
| @@ -244,6 +241,11 @@ static struct resource sa11x0ssp_resources[] = { | |||
| 244 | .end = 0x8007ffff, | 241 | .end = 0x8007ffff, |
| 245 | .flags = IORESOURCE_MEM, | 242 | .flags = IORESOURCE_MEM, |
| 246 | }, | 243 | }, |
| 244 | [1] = { | ||
| 245 | .start = IRQ_Ser4SSP, | ||
| 246 | .end = IRQ_Ser4SSP, | ||
| 247 | .flags = IORESOURCE_IRQ, | ||
| 248 | }, | ||
| 247 | }; | 249 | }; |
| 248 | 250 | ||
| 249 | static u64 sa11x0ssp_dma_mask = 0xffffffffUL; | 251 | static u64 sa11x0ssp_dma_mask = 0xffffffffUL; |
diff --git a/arch/arm/mach-sa1100/include/mach/hardware.h b/arch/arm/mach-sa1100/include/mach/hardware.h index 99f5856d8de4..967ae7684390 100644 --- a/arch/arm/mach-sa1100/include/mach/hardware.h +++ b/arch/arm/mach-sa1100/include/mach/hardware.h | |||
| @@ -76,4 +76,12 @@ static inline unsigned long get_clock_tick_rate(void) | |||
| 76 | #include "SA-1101.h" | 76 | #include "SA-1101.h" |
| 77 | #endif | 77 | #endif |
| 78 | 78 | ||
| 79 | #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_PCI) | ||
| 80 | #define PCIBIOS_MIN_IO 0 | ||
| 81 | #define PCIBIOS_MIN_MEM 0 | ||
| 82 | #define pcibios_assign_all_busses() 1 | ||
| 83 | #define HAVE_ARCH_PCI_SET_DMA_MASK 1 | ||
| 84 | #endif | ||
| 85 | |||
| 86 | |||
| 79 | #endif /* _ASM_ARCH_HARDWARE_H */ | 87 | #endif /* _ASM_ARCH_HARDWARE_H */ |
diff --git a/arch/arm/mach-sa1100/include/mach/nanoengine.h b/arch/arm/mach-sa1100/include/mach/nanoengine.h new file mode 100644 index 000000000000..14f8382d0665 --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/nanoengine.h | |||
| @@ -0,0 +1,52 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-sa1100/include/mach/nanoengine.h | ||
| 3 | * | ||
| 4 | * This file contains the hardware specific definitions for nanoEngine. | ||
| 5 | * Only include this file from SA1100-specific files. | ||
| 6 | * | ||
| 7 | * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | */ | ||
| 14 | #ifndef __ASM_ARCH_NANOENGINE_H | ||
| 15 | #define __ASM_ARCH_NANOENGINE_H | ||
| 16 | |||
| 17 | #include <mach/irqs.h> | ||
| 18 | |||
| 19 | #define GPIO_PC_READY0 GPIO_GPIO(11) /* ready for socket 0 (active high)*/ | ||
| 20 | #define GPIO_PC_READY1 GPIO_GPIO(12) /* ready for socket 1 (active high) */ | ||
| 21 | #define GPIO_PC_CD0 GPIO_GPIO(13) /* detect for socket 0 (active low) */ | ||
| 22 | #define GPIO_PC_CD1 GPIO_GPIO(14) /* detect for socket 1 (active low) */ | ||
| 23 | #define GPIO_PC_RESET0 GPIO_GPIO(15) /* reset socket 0 */ | ||
| 24 | #define GPIO_PC_RESET1 GPIO_GPIO(16) /* reset socket 1 */ | ||
| 25 | |||
| 26 | #define NANOENGINE_IRQ_GPIO_PCI IRQ_GPIO0 | ||
| 27 | #define NANOENGINE_IRQ_GPIO_PC_READY0 IRQ_GPIO11 | ||
| 28 | #define NANOENGINE_IRQ_GPIO_PC_READY1 IRQ_GPIO12 | ||
| 29 | #define NANOENGINE_IRQ_GPIO_PC_CD0 IRQ_GPIO13 | ||
| 30 | #define NANOENGINE_IRQ_GPIO_PC_CD1 IRQ_GPIO14 | ||
| 31 | |||
| 32 | /* | ||
| 33 | * nanoEngine Memory Map: | ||
| 34 | * | ||
| 35 | * 0000.0000 - 003F.0000 - 4 MB Flash | ||
| 36 | * C000.0000 - C1FF.FFFF - 32 MB SDRAM | ||
| 37 | * 1860.0000 - 186F.FFFF - 1 MB Internal PCI Memory Read/Write | ||
| 38 | * 18A1.0000 - 18A1.FFFF - 64 KB Internal PCI Config Space | ||
| 39 | * 4000.0000 - 47FF.FFFF - 128 MB External Bus I/O - Multiplexed Mode | ||
| 40 | * 4800.0000 - 4FFF.FFFF - 128 MB External Bus I/O - Non-Multiplexed Mode | ||
| 41 | * | ||
| 42 | */ | ||
| 43 | |||
| 44 | #define NANO_PCI_MEM_RW_PHYS 0x18600000 | ||
| 45 | #define NANO_PCI_MEM_RW_VIRT 0xf1000000 | ||
| 46 | #define NANO_PCI_MEM_RW_SIZE SZ_1M | ||
| 47 | #define NANO_PCI_CONFIG_SPACE_PHYS 0x18A10000 | ||
| 48 | #define NANO_PCI_CONFIG_SPACE_VIRT 0xf2000000 | ||
| 49 | #define NANO_PCI_CONFIG_SPACE_SIZE SZ_64K | ||
| 50 | |||
| 51 | #endif | ||
| 52 | |||
diff --git a/arch/arm/mach-sa1100/nanoengine.c b/arch/arm/mach-sa1100/nanoengine.c new file mode 100644 index 000000000000..72087f0658b7 --- /dev/null +++ b/arch/arm/mach-sa1100/nanoengine.c | |||
| @@ -0,0 +1,119 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-sa1100/nanoengine.c | ||
| 3 | * | ||
| 4 | * Bright Star Engineering's nanoEngine board init code. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/init.h> | ||
| 15 | #include <linux/kernel.h> | ||
| 16 | #include <linux/mtd/mtd.h> | ||
| 17 | #include <linux/mtd/partitions.h> | ||
| 18 | #include <linux/root_dev.h> | ||
| 19 | |||
| 20 | #include <asm/mach-types.h> | ||
| 21 | #include <asm/setup.h> | ||
| 22 | |||
| 23 | #include <asm/mach/arch.h> | ||
| 24 | #include <asm/mach/flash.h> | ||
| 25 | #include <asm/mach/map.h> | ||
| 26 | #include <asm/mach/serial_sa1100.h> | ||
| 27 | |||
| 28 | #include <mach/hardware.h> | ||
| 29 | #include <mach/nanoengine.h> | ||
| 30 | |||
| 31 | #include "generic.h" | ||
| 32 | |||
| 33 | /* Flash bank 0 */ | ||
| 34 | static struct mtd_partition nanoengine_partitions[] = { | ||
| 35 | { | ||
| 36 | .name = "nanoEngine boot firmware and parameter table", | ||
| 37 | .size = 0x00010000, /* 32K */ | ||
| 38 | .offset = 0, | ||
| 39 | .mask_flags = MTD_WRITEABLE, | ||
| 40 | }, { | ||
| 41 | .name = "kernel/initrd reserved", | ||
| 42 | .size = 0x002f0000, | ||
| 43 | .offset = 0x00010000, | ||
| 44 | .mask_flags = MTD_WRITEABLE, | ||
| 45 | }, { | ||
| 46 | .name = "experimental filesystem allocation", | ||
| 47 | .size = 0x00100000, | ||
| 48 | .offset = 0x00300000, | ||
| 49 | .mask_flags = MTD_WRITEABLE, | ||
| 50 | } | ||
| 51 | }; | ||
| 52 | |||
| 53 | static struct flash_platform_data nanoengine_flash_data = { | ||
| 54 | .map_name = "jedec_probe", | ||
| 55 | .parts = nanoengine_partitions, | ||
| 56 | .nr_parts = ARRAY_SIZE(nanoengine_partitions), | ||
| 57 | }; | ||
| 58 | |||
| 59 | static struct resource nanoengine_flash_resources[] = { | ||
| 60 | { | ||
| 61 | .start = SA1100_CS0_PHYS, | ||
| 62 | .end = SA1100_CS0_PHYS + SZ_32M - 1, | ||
| 63 | .flags = IORESOURCE_MEM, | ||
| 64 | }, { | ||
| 65 | .start = SA1100_CS1_PHYS, | ||
| 66 | .end = SA1100_CS1_PHYS + SZ_32M - 1, | ||
| 67 | .flags = IORESOURCE_MEM, | ||
| 68 | } | ||
| 69 | }; | ||
| 70 | |||
| 71 | static struct map_desc nanoengine_io_desc[] __initdata = { | ||
| 72 | { | ||
| 73 | /* System Registers */ | ||
| 74 | .virtual = 0xf0000000, | ||
| 75 | .pfn = __phys_to_pfn(0x10000000), | ||
| 76 | .length = 0x00100000, | ||
| 77 | .type = MT_DEVICE | ||
| 78 | }, { | ||
| 79 | /* Internal PCI Memory Read/Write */ | ||
| 80 | .virtual = NANO_PCI_MEM_RW_VIRT, | ||
| 81 | .pfn = __phys_to_pfn(NANO_PCI_MEM_RW_PHYS), | ||
| 82 | .length = NANO_PCI_MEM_RW_SIZE, | ||
| 83 | .type = MT_DEVICE | ||
| 84 | }, { | ||
| 85 | /* Internal PCI Config Space */ | ||
| 86 | .virtual = NANO_PCI_CONFIG_SPACE_VIRT, | ||
| 87 | .pfn = __phys_to_pfn(NANO_PCI_CONFIG_SPACE_PHYS), | ||
| 88 | .length = NANO_PCI_CONFIG_SPACE_SIZE, | ||
| 89 | .type = MT_DEVICE | ||
| 90 | } | ||
| 91 | }; | ||
| 92 | |||
| 93 | static void __init nanoengine_map_io(void) | ||
| 94 | { | ||
| 95 | sa1100_map_io(); | ||
| 96 | iotable_init(nanoengine_io_desc, ARRAY_SIZE(nanoengine_io_desc)); | ||
| 97 | |||
| 98 | sa1100_register_uart(0, 1); | ||
| 99 | sa1100_register_uart(1, 2); | ||
| 100 | sa1100_register_uart(2, 3); | ||
| 101 | Ser1SDCR0 |= SDCR0_UART; | ||
| 102 | /* disable IRDA -- UART2 is used as a normal serial port */ | ||
| 103 | Ser2UTCR4 = 0; | ||
| 104 | Ser2HSCR0 = 0; | ||
| 105 | } | ||
| 106 | |||
| 107 | static void __init nanoengine_init(void) | ||
| 108 | { | ||
| 109 | sa11x0_register_mtd(&nanoengine_flash_data, nanoengine_flash_resources, | ||
| 110 | ARRAY_SIZE(nanoengine_flash_resources)); | ||
| 111 | } | ||
| 112 | |||
| 113 | MACHINE_START(NANOENGINE, "BSE nanoEngine") | ||
| 114 | .boot_params = 0xc0000000, | ||
| 115 | .map_io = nanoengine_map_io, | ||
| 116 | .init_irq = sa1100_init_irq, | ||
| 117 | .timer = &sa1100_timer, | ||
| 118 | .init_machine = nanoengine_init, | ||
| 119 | MACHINE_END | ||
diff --git a/arch/arm/mach-sa1100/pci-nanoengine.c b/arch/arm/mach-sa1100/pci-nanoengine.c new file mode 100644 index 000000000000..fba7a913f12b --- /dev/null +++ b/arch/arm/mach-sa1100/pci-nanoengine.c | |||
| @@ -0,0 +1,284 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-sa1100/pci-nanoengine.c | ||
| 3 | * | ||
| 4 | * PCI functions for BSE nanoEngine PCI | ||
| 5 | * | ||
| 6 | * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License | ||
| 19 | * along with this program; if not, write to the Free Software | ||
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 21 | */ | ||
| 22 | #include <linux/kernel.h> | ||
| 23 | #include <linux/irq.h> | ||
| 24 | #include <linux/pci.h> | ||
| 25 | #include <linux/spinlock.h> | ||
| 26 | |||
| 27 | #include <asm/mach/pci.h> | ||
| 28 | #include <asm/mach-types.h> | ||
| 29 | |||
| 30 | #include <mach/nanoengine.h> | ||
| 31 | |||
| 32 | static DEFINE_SPINLOCK(nano_lock); | ||
| 33 | |||
| 34 | static int nanoengine_get_pci_address(struct pci_bus *bus, | ||
| 35 | unsigned int devfn, int where, unsigned long *address) | ||
| 36 | { | ||
| 37 | int ret = PCIBIOS_DEVICE_NOT_FOUND; | ||
| 38 | unsigned int busnr = bus->number; | ||
| 39 | |||
| 40 | *address = NANO_PCI_CONFIG_SPACE_VIRT + | ||
| 41 | ((bus->number << 16) | (devfn << 8) | (where & ~3)); | ||
| 42 | |||
| 43 | ret = (busnr > 255 || devfn > 255 || where > 255) ? | ||
| 44 | PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; | ||
| 45 | |||
| 46 | return ret; | ||
| 47 | } | ||
| 48 | |||
| 49 | static int nanoengine_read_config(struct pci_bus *bus, unsigned int devfn, int where, | ||
| 50 | int size, u32 *val) | ||
| 51 | { | ||
| 52 | int ret; | ||
| 53 | unsigned long address; | ||
| 54 | unsigned long flags; | ||
| 55 | u32 v; | ||
| 56 | |||
| 57 | /* nanoEngine PCI bridge does not return -1 for a non-existing | ||
| 58 | * device. We must fake the answer. We know that the only valid | ||
| 59 | * device is device zero at bus 0, which is the network chip. */ | ||
| 60 | if (bus->number != 0 || (devfn >> 3) != 0) { | ||
| 61 | v = -1; | ||
| 62 | nanoengine_get_pci_address(bus, devfn, where, &address); | ||
| 63 | goto exit_function; | ||
| 64 | } | ||
| 65 | |||
| 66 | spin_lock_irqsave(&nano_lock, flags); | ||
| 67 | |||
| 68 | ret = nanoengine_get_pci_address(bus, devfn, where, &address); | ||
| 69 | if (ret != PCIBIOS_SUCCESSFUL) | ||
| 70 | return ret; | ||
| 71 | v = __raw_readl(address); | ||
| 72 | |||
| 73 | spin_unlock_irqrestore(&nano_lock, flags); | ||
| 74 | |||
| 75 | v >>= ((where & 3) * 8); | ||
| 76 | v &= (unsigned long)(-1) >> ((4 - size) * 8); | ||
| 77 | |||
| 78 | exit_function: | ||
| 79 | *val = v; | ||
| 80 | return PCIBIOS_SUCCESSFUL; | ||
| 81 | } | ||
| 82 | |||
| 83 | static int nanoengine_write_config(struct pci_bus *bus, unsigned int devfn, int where, | ||
| 84 | int size, u32 val) | ||
| 85 | { | ||
| 86 | int ret; | ||
| 87 | unsigned long address; | ||
| 88 | unsigned long flags; | ||
| 89 | unsigned shift; | ||
| 90 | u32 v; | ||
| 91 | |||
| 92 | shift = (where & 3) * 8; | ||
| 93 | |||
| 94 | spin_lock_irqsave(&nano_lock, flags); | ||
| 95 | |||
| 96 | ret = nanoengine_get_pci_address(bus, devfn, where, &address); | ||
| 97 | if (ret != PCIBIOS_SUCCESSFUL) | ||
| 98 | return ret; | ||
| 99 | v = __raw_readl(address); | ||
| 100 | switch (size) { | ||
| 101 | case 1: | ||
| 102 | v &= ~(0xFF << shift); | ||
| 103 | v |= val << shift; | ||
| 104 | break; | ||
| 105 | case 2: | ||
| 106 | v &= ~(0xFFFF << shift); | ||
| 107 | v |= val << shift; | ||
| 108 | break; | ||
| 109 | case 4: | ||
| 110 | v = val; | ||
| 111 | break; | ||
| 112 | } | ||
| 113 | __raw_writel(v, address); | ||
| 114 | |||
| 115 | spin_unlock_irqrestore(&nano_lock, flags); | ||
| 116 | |||
| 117 | return PCIBIOS_SUCCESSFUL; | ||
| 118 | } | ||
| 119 | |||
| 120 | static struct pci_ops pci_nano_ops = { | ||
| 121 | .read = nanoengine_read_config, | ||
| 122 | .write = nanoengine_write_config, | ||
| 123 | }; | ||
| 124 | |||
| 125 | static int __init pci_nanoengine_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | ||
| 126 | { | ||
| 127 | return NANOENGINE_IRQ_GPIO_PCI; | ||
| 128 | } | ||
| 129 | |||
| 130 | struct pci_bus * __init pci_nanoengine_scan_bus(int nr, struct pci_sys_data *sys) | ||
| 131 | { | ||
| 132 | return pci_scan_bus(sys->busnr, &pci_nano_ops, sys); | ||
| 133 | } | ||
| 134 | |||
| 135 | static struct resource pci_io_ports = { | ||
| 136 | .name = "PCI IO", | ||
| 137 | .start = 0x400, | ||
| 138 | .end = 0x7FF, | ||
| 139 | .flags = IORESOURCE_IO, | ||
| 140 | }; | ||
| 141 | |||
| 142 | static struct resource pci_non_prefetchable_memory = { | ||
| 143 | .name = "PCI non-prefetchable", | ||
| 144 | .start = NANO_PCI_MEM_RW_PHYS, | ||
| 145 | /* nanoEngine documentation says there is a 1 Megabyte window here, | ||
| 146 | * but PCI reports just 128 + 8 kbytes. */ | ||
| 147 | .end = NANO_PCI_MEM_RW_PHYS + NANO_PCI_MEM_RW_SIZE - 1, | ||
| 148 | /* .end = NANO_PCI_MEM_RW_PHYS + SZ_128K + SZ_8K - 1,*/ | ||
| 149 | .flags = IORESOURCE_MEM, | ||
| 150 | }; | ||
| 151 | |||
| 152 | /* | ||
| 153 | * nanoEngine PCI reports 1 Megabyte of prefetchable memory, but it | ||
| 154 | * overlaps with previously defined memory. | ||
| 155 | * | ||
| 156 | * Here is what happens: | ||
| 157 | * | ||
| 158 | # dmesg | ||
| 159 | ... | ||
| 160 | pci 0000:00:00.0: [8086:1209] type 0 class 0x000200 | ||
| 161 | pci 0000:00:00.0: reg 10: [mem 0x00021000-0x00021fff] | ||
| 162 | pci 0000:00:00.0: reg 14: [io 0x0000-0x003f] | ||
| 163 | pci 0000:00:00.0: reg 18: [mem 0x00000000-0x0001ffff] | ||
| 164 | pci 0000:00:00.0: reg 30: [mem 0x00000000-0x000fffff pref] | ||
| 165 | pci 0000:00:00.0: supports D1 D2 | ||
| 166 | pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot | ||
| 167 | pci 0000:00:00.0: PME# disabled | ||
| 168 | PCI: bus0: Fast back to back transfers enabled | ||
| 169 | pci 0000:00:00.0: BAR 6: can't assign mem pref (size 0x100000) | ||
| 170 | pci 0000:00:00.0: BAR 2: assigned [mem 0x18600000-0x1861ffff] | ||
| 171 | pci 0000:00:00.0: BAR 2: set to [mem 0x18600000-0x1861ffff] (PCI address [0x0-0x1ffff]) | ||
| 172 | pci 0000:00:00.0: BAR 0: assigned [mem 0x18620000-0x18620fff] | ||
| 173 | pci 0000:00:00.0: BAR 0: set to [mem 0x18620000-0x18620fff] (PCI address [0x20000-0x20fff]) | ||
| 174 | pci 0000:00:00.0: BAR 1: assigned [io 0x0400-0x043f] | ||
| 175 | pci 0000:00:00.0: BAR 1: set to [io 0x0400-0x043f] (PCI address [0x0-0x3f]) | ||
| 176 | * | ||
| 177 | * On the other hand, if we do not request the prefetchable memory resource, | ||
| 178 | * linux will alloc it first and the two non-prefetchable memory areas that | ||
| 179 | * are our real interest will not be mapped. So we choose to map it to an | ||
| 180 | * unused area. It gets recognized as expansion ROM, but becomes disabled. | ||
| 181 | * | ||
| 182 | * Here is what happens then: | ||
| 183 | * | ||
| 184 | # dmesg | ||
| 185 | ... | ||
| 186 | pci 0000:00:00.0: [8086:1209] type 0 class 0x000200 | ||
| 187 | pci 0000:00:00.0: reg 10: [mem 0x00021000-0x00021fff] | ||
| 188 | pci 0000:00:00.0: reg 14: [io 0x0000-0x003f] | ||
| 189 | pci 0000:00:00.0: reg 18: [mem 0x00000000-0x0001ffff] | ||
| 190 | pci 0000:00:00.0: reg 30: [mem 0x00000000-0x000fffff pref] | ||
| 191 | pci 0000:00:00.0: supports D1 D2 | ||
| 192 | pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot | ||
| 193 | pci 0000:00:00.0: PME# disabled | ||
| 194 | PCI: bus0: Fast back to back transfers enabled | ||
| 195 | pci 0000:00:00.0: BAR 6: assigned [mem 0x78000000-0x780fffff pref] | ||
| 196 | pci 0000:00:00.0: BAR 2: assigned [mem 0x18600000-0x1861ffff] | ||
| 197 | pci 0000:00:00.0: BAR 2: set to [mem 0x18600000-0x1861ffff] (PCI address [0x0-0x1ffff]) | ||
| 198 | pci 0000:00:00.0: BAR 0: assigned [mem 0x18620000-0x18620fff] | ||
| 199 | pci 0000:00:00.0: BAR 0: set to [mem 0x18620000-0x18620fff] (PCI address [0x20000-0x20fff]) | ||
| 200 | pci 0000:00:00.0: BAR 1: assigned [io 0x0400-0x043f] | ||
| 201 | pci 0000:00:00.0: BAR 1: set to [io 0x0400-0x043f] (PCI address [0x0-0x3f]) | ||
| 202 | |||
| 203 | # lspci -vv -s 0000:00:00.0 | ||
| 204 | 00:00.0 Class 0200: Device 8086:1209 (rev 09) | ||
| 205 | Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx- | ||
| 206 | Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR+ <PERR+ INTx- | ||
| 207 | Latency: 0 (2000ns min, 14000ns max), Cache Line Size: 32 bytes | ||
| 208 | Interrupt: pin A routed to IRQ 0 | ||
| 209 | Region 0: Memory at 18620000 (32-bit, non-prefetchable) [size=4K] | ||
| 210 | Region 1: I/O ports at 0400 [size=64] | ||
| 211 | Region 2: [virtual] Memory at 18600000 (32-bit, non-prefetchable) [size=128K] | ||
| 212 | [virtual] Expansion ROM at 78000000 [disabled] [size=1M] | ||
| 213 | Capabilities: [dc] Power Management version 2 | ||
| 214 | Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) | ||
| 215 | Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=2 PME- | ||
| 216 | Kernel driver in use: e100 | ||
| 217 | Kernel modules: e100 | ||
| 218 | * | ||
| 219 | */ | ||
| 220 | static struct resource pci_prefetchable_memory = { | ||
| 221 | .name = "PCI prefetchable", | ||
| 222 | .start = 0x78000000, | ||
| 223 | .end = 0x78000000 + NANO_PCI_MEM_RW_SIZE - 1, | ||
| 224 | .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH, | ||
| 225 | }; | ||
| 226 | |||
| 227 | static int __init pci_nanoengine_setup_resources(struct resource **resource) | ||
| 228 | { | ||
| 229 | if (request_resource(&ioport_resource, &pci_io_ports)) { | ||
| 230 | printk(KERN_ERR "PCI: unable to allocate io port region\n"); | ||
| 231 | return -EBUSY; | ||
| 232 | } | ||
| 233 | if (request_resource(&iomem_resource, &pci_non_prefetchable_memory)) { | ||
| 234 | release_resource(&pci_io_ports); | ||
| 235 | printk(KERN_ERR "PCI: unable to allocate non prefetchable\n"); | ||
| 236 | return -EBUSY; | ||
| 237 | } | ||
| 238 | if (request_resource(&iomem_resource, &pci_prefetchable_memory)) { | ||
| 239 | release_resource(&pci_io_ports); | ||
| 240 | release_resource(&pci_non_prefetchable_memory); | ||
| 241 | printk(KERN_ERR "PCI: unable to allocate prefetchable\n"); | ||
| 242 | return -EBUSY; | ||
| 243 | } | ||
| 244 | resource[0] = &pci_io_ports; | ||
| 245 | resource[1] = &pci_non_prefetchable_memory; | ||
| 246 | resource[2] = &pci_prefetchable_memory; | ||
| 247 | |||
| 248 | return 1; | ||
| 249 | } | ||
| 250 | |||
| 251 | int __init pci_nanoengine_setup(int nr, struct pci_sys_data *sys) | ||
| 252 | { | ||
| 253 | int ret = 0; | ||
| 254 | |||
| 255 | if (nr == 0) { | ||
| 256 | sys->mem_offset = NANO_PCI_MEM_RW_PHYS; | ||
| 257 | sys->io_offset = 0x400; | ||
| 258 | ret = pci_nanoengine_setup_resources(sys->resource); | ||
| 259 | /* Enable alternate memory bus master mode, see | ||
| 260 | * "Intel StrongARM SA1110 Developer's Manual", | ||
| 261 | * section 10.8, "Alternate Memory Bus Master Mode". */ | ||
| 262 | GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT; | ||
| 263 | GAFR |= GPIO_MBGNT | GPIO_MBREQ; | ||
| 264 | TUCR |= TUCR_MBGPIO; | ||
| 265 | } | ||
| 266 | |||
| 267 | return ret; | ||
| 268 | } | ||
| 269 | |||
| 270 | static struct hw_pci nanoengine_pci __initdata = { | ||
| 271 | .map_irq = pci_nanoengine_map_irq, | ||
| 272 | .nr_controllers = 1, | ||
| 273 | .scan = pci_nanoengine_scan_bus, | ||
| 274 | .setup = pci_nanoengine_setup, | ||
| 275 | }; | ||
| 276 | |||
| 277 | static int __init nanoengine_pci_init(void) | ||
| 278 | { | ||
| 279 | if (machine_is_nanoengine()) | ||
| 280 | pci_common_init(&nanoengine_pci); | ||
| 281 | return 0; | ||
| 282 | } | ||
| 283 | |||
| 284 | subsys_initcall(nanoengine_pci_init); | ||
diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c index 27692d0ffbe8..cfb76077bd25 100644 --- a/arch/arm/mach-sa1100/simpad.c +++ b/arch/arm/mach-sa1100/simpad.c | |||
| @@ -166,9 +166,6 @@ static void __init simpad_map_io(void) | |||
| 166 | PCFR = 0; | 166 | PCFR = 0; |
| 167 | PSDR = 0; | 167 | PSDR = 0; |
| 168 | 168 | ||
| 169 | sa11x0_register_mtd(&simpad_flash_data, simpad_flash_resources, | ||
| 170 | ARRAY_SIZE(simpad_flash_resources)); | ||
| 171 | sa11x0_register_mcp(&simpad_mcp_data); | ||
| 172 | } | 169 | } |
| 173 | 170 | ||
| 174 | static void simpad_power_off(void) | 171 | static void simpad_power_off(void) |
| @@ -216,6 +213,10 @@ static int __init simpad_init(void) | |||
| 216 | 213 | ||
| 217 | pm_power_off = simpad_power_off; | 214 | pm_power_off = simpad_power_off; |
| 218 | 215 | ||
| 216 | sa11x0_register_mtd(&simpad_flash_data, simpad_flash_resources, | ||
| 217 | ARRAY_SIZE(simpad_flash_resources)); | ||
| 218 | sa11x0_register_mcp(&simpad_mcp_data); | ||
| 219 | |||
| 219 | ret = platform_add_devices(devices, ARRAY_SIZE(devices)); | 220 | ret = platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 220 | if(ret) | 221 | if(ret) |
| 221 | printk(KERN_WARNING "simpad: Unable to register mq200 framebuffer device"); | 222 | printk(KERN_WARNING "simpad: Unable to register mq200 framebuffer device"); |
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c index 74b6e0e570b6..ae4f3d80416f 100644 --- a/arch/arm/mach-sa1100/time.c +++ b/arch/arm/mach-sa1100/time.c | |||
| @@ -12,12 +12,39 @@ | |||
| 12 | #include <linux/errno.h> | 12 | #include <linux/errno.h> |
| 13 | #include <linux/interrupt.h> | 13 | #include <linux/interrupt.h> |
| 14 | #include <linux/irq.h> | 14 | #include <linux/irq.h> |
| 15 | #include <linux/sched.h> /* just for sched_clock() - funny that */ | ||
| 15 | #include <linux/timex.h> | 16 | #include <linux/timex.h> |
| 16 | #include <linux/clockchips.h> | 17 | #include <linux/clockchips.h> |
| 17 | 18 | ||
| 18 | #include <asm/mach/time.h> | 19 | #include <asm/mach/time.h> |
| 20 | #include <asm/sched_clock.h> | ||
| 19 | #include <mach/hardware.h> | 21 | #include <mach/hardware.h> |
| 20 | 22 | ||
| 23 | /* | ||
| 24 | * This is the SA11x0 sched_clock implementation. | ||
| 25 | */ | ||
| 26 | static DEFINE_CLOCK_DATA(cd); | ||
| 27 | |||
| 28 | /* | ||
| 29 | * Constants generated by clocks_calc_mult_shift(m, s, 3.6864MHz, | ||
| 30 | * NSEC_PER_SEC, 60). | ||
| 31 | * This gives a resolution of about 271ns and a wrap period of about 19min. | ||
| 32 | */ | ||
| 33 | #define SC_MULT 2275555556u | ||
| 34 | #define SC_SHIFT 23 | ||
| 35 | |||
| 36 | unsigned long long notrace sched_clock(void) | ||
| 37 | { | ||
| 38 | u32 cyc = OSCR; | ||
| 39 | return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT); | ||
| 40 | } | ||
| 41 | |||
| 42 | static void notrace sa1100_update_sched_clock(void) | ||
| 43 | { | ||
| 44 | u32 cyc = OSCR; | ||
| 45 | update_sched_clock(&cd, cyc, (u32)~0); | ||
| 46 | } | ||
| 47 | |||
| 21 | #define MIN_OSCR_DELTA 2 | 48 | #define MIN_OSCR_DELTA 2 |
| 22 | 49 | ||
| 23 | static irqreturn_t sa1100_ost0_interrupt(int irq, void *dev_id) | 50 | static irqreturn_t sa1100_ost0_interrupt(int irq, void *dev_id) |
| @@ -81,7 +108,6 @@ static struct clocksource cksrc_sa1100_oscr = { | |||
| 81 | .rating = 200, | 108 | .rating = 200, |
| 82 | .read = sa1100_read_oscr, | 109 | .read = sa1100_read_oscr, |
| 83 | .mask = CLOCKSOURCE_MASK(32), | 110 | .mask = CLOCKSOURCE_MASK(32), |
| 84 | .shift = 20, | ||
| 85 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 111 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 86 | }; | 112 | }; |
| 87 | 113 | ||
| @@ -97,6 +123,9 @@ static void __init sa1100_timer_init(void) | |||
| 97 | OIER = 0; /* disable any timer interrupts */ | 123 | OIER = 0; /* disable any timer interrupts */ |
| 98 | OSSR = 0xf; /* clear status on all timers */ | 124 | OSSR = 0xf; /* clear status on all timers */ |
| 99 | 125 | ||
| 126 | init_fixed_sched_clock(&cd, sa1100_update_sched_clock, 32, | ||
| 127 | 3686400, SC_MULT, SC_SHIFT); | ||
| 128 | |||
| 100 | ckevt_sa1100_osmr0.mult = | 129 | ckevt_sa1100_osmr0.mult = |
| 101 | div_sc(3686400, NSEC_PER_SEC, ckevt_sa1100_osmr0.shift); | 130 | div_sc(3686400, NSEC_PER_SEC, ckevt_sa1100_osmr0.shift); |
| 102 | ckevt_sa1100_osmr0.max_delta_ns = | 131 | ckevt_sa1100_osmr0.max_delta_ns = |
| @@ -105,12 +134,9 @@ static void __init sa1100_timer_init(void) | |||
| 105 | clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_sa1100_osmr0) + 1; | 134 | clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_sa1100_osmr0) + 1; |
| 106 | ckevt_sa1100_osmr0.cpumask = cpumask_of(0); | 135 | ckevt_sa1100_osmr0.cpumask = cpumask_of(0); |
| 107 | 136 | ||
| 108 | cksrc_sa1100_oscr.mult = | ||
| 109 | clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_sa1100_oscr.shift); | ||
| 110 | |||
| 111 | setup_irq(IRQ_OST0, &sa1100_timer_irq); | 137 | setup_irq(IRQ_OST0, &sa1100_timer_irq); |
| 112 | 138 | ||
| 113 | clocksource_register(&cksrc_sa1100_oscr); | 139 | clocksource_register_hz(&cksrc_sa1100_oscr, CLOCK_TICK_RATE); |
| 114 | clockevents_register_device(&ckevt_sa1100_osmr0); | 140 | clockevents_register_device(&ckevt_sa1100_osmr0); |
| 115 | } | 141 | } |
| 116 | 142 | ||
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 51dcd59eda6a..4d1b4c5c9389 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig | |||
| @@ -5,26 +5,27 @@ comment "SH-Mobile System Type" | |||
| 5 | config ARCH_SH7367 | 5 | config ARCH_SH7367 |
| 6 | bool "SH-Mobile G3 (SH7367)" | 6 | bool "SH-Mobile G3 (SH7367)" |
| 7 | select CPU_V6 | 7 | select CPU_V6 |
| 8 | select HAVE_CLK | ||
| 9 | select COMMON_CLKDEV | ||
| 10 | select SH_CLK_CPG | 8 | select SH_CLK_CPG |
| 11 | select GENERIC_CLOCKEVENTS | 9 | select ARCH_WANT_OPTIONAL_GPIOLIB |
| 12 | 10 | ||
| 13 | config ARCH_SH7377 | 11 | config ARCH_SH7377 |
| 14 | bool "SH-Mobile G4 (SH7377)" | 12 | bool "SH-Mobile G4 (SH7377)" |
| 15 | select CPU_V7 | 13 | select CPU_V7 |
| 16 | select HAVE_CLK | ||
| 17 | select COMMON_CLKDEV | ||
| 18 | select SH_CLK_CPG | 14 | select SH_CLK_CPG |
| 19 | select GENERIC_CLOCKEVENTS | 15 | select ARCH_WANT_OPTIONAL_GPIOLIB |
| 20 | 16 | ||
| 21 | config ARCH_SH7372 | 17 | config ARCH_SH7372 |
| 22 | bool "SH-Mobile AP4 (SH7372)" | 18 | bool "SH-Mobile AP4 (SH7372)" |
| 23 | select CPU_V7 | 19 | select CPU_V7 |
| 24 | select HAVE_CLK | ||
| 25 | select COMMON_CLKDEV | ||
| 26 | select SH_CLK_CPG | 20 | select SH_CLK_CPG |
| 27 | select GENERIC_CLOCKEVENTS | 21 | select ARCH_WANT_OPTIONAL_GPIOLIB |
| 22 | |||
| 23 | config ARCH_SH73A0 | ||
| 24 | bool "SH-Mobile AG5 (R8A73A00)" | ||
| 25 | select CPU_V7 | ||
| 26 | select SH_CLK_CPG | ||
| 27 | select ARCH_WANT_OPTIONAL_GPIOLIB | ||
| 28 | select ARM_GIC | ||
| 28 | 29 | ||
| 29 | comment "SH-Mobile Board Type" | 30 | comment "SH-Mobile Board Type" |
| 30 | 31 | ||
| @@ -57,6 +58,15 @@ config AP4EVB_WVGA | |||
| 57 | 58 | ||
| 58 | endchoice | 59 | endchoice |
| 59 | 60 | ||
| 61 | config MACH_AG5EVM | ||
| 62 | bool "AG5EVM board" | ||
| 63 | depends on ARCH_SH73A0 | ||
| 64 | |||
| 65 | config MACH_MACKEREL | ||
| 66 | bool "mackerel board" | ||
| 67 | depends on ARCH_SH7372 | ||
| 68 | select ARCH_REQUIRE_GPIOLIB | ||
| 69 | |||
| 60 | comment "SH-Mobile System Configuration" | 70 | comment "SH-Mobile System Configuration" |
| 61 | 71 | ||
| 62 | menu "Memory configuration" | 72 | menu "Memory configuration" |
| @@ -64,8 +74,8 @@ menu "Memory configuration" | |||
| 64 | config MEMORY_START | 74 | config MEMORY_START |
| 65 | hex "Physical memory start address" | 75 | hex "Physical memory start address" |
| 66 | default "0x50000000" if MACH_G3EVM | 76 | default "0x50000000" if MACH_G3EVM |
| 67 | default "0x40000000" if MACH_G4EVM | 77 | default "0x40000000" if MACH_G4EVM || MACH_AP4EVB || MACH_AG5EVM || \ |
| 68 | default "0x40000000" if MACH_AP4EVB | 78 | MACH_MACKEREL |
| 69 | default "0x00000000" | 79 | default "0x00000000" |
| 70 | ---help--- | 80 | ---help--- |
| 71 | Tweak this only when porting to a new machine which does not | 81 | Tweak this only when porting to a new machine which does not |
| @@ -76,7 +86,8 @@ config MEMORY_SIZE | |||
| 76 | hex "Physical memory size" | 86 | hex "Physical memory size" |
| 77 | default "0x08000000" if MACH_G3EVM | 87 | default "0x08000000" if MACH_G3EVM |
| 78 | default "0x08000000" if MACH_G4EVM | 88 | default "0x08000000" if MACH_G4EVM |
| 79 | default "0x10000000" if MACH_AP4EVB | 89 | default "0x20000000" if MACH_AG5EVM |
| 90 | default "0x10000000" if MACH_AP4EVB || MACH_MACKEREL | ||
| 80 | default "0x04000000" | 91 | default "0x04000000" |
| 81 | help | 92 | help |
| 82 | This sets the default memory size assumed by your kernel. It can | 93 | This sets the default memory size assumed by your kernel. It can |
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index ae416fe7daf2..e2507f66f9d5 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile | |||
| @@ -9,14 +9,34 @@ obj-y := timer.o console.o clock.o pm_runtime.o | |||
| 9 | obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o | 9 | obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o |
| 10 | obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7377.o intc-sh7377.o | 10 | obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7377.o intc-sh7377.o |
| 11 | obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o | 11 | obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o |
| 12 | obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o | ||
| 13 | |||
| 14 | # SMP objects | ||
| 15 | smp-y := platsmp.o headsmp.o | ||
| 16 | smp-$(CONFIG_HOTPLUG_CPU) += hotplug.o | ||
| 17 | smp-$(CONFIG_LOCAL_TIMERS) += localtimer.o | ||
| 18 | smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o | ||
| 12 | 19 | ||
| 13 | # Pinmux setup | 20 | # Pinmux setup |
| 14 | pfc-$(CONFIG_ARCH_SH7367) := pfc-sh7367.o | 21 | pfc-y := |
| 15 | pfc-$(CONFIG_ARCH_SH7377) := pfc-sh7377.o | 22 | pfc-$(CONFIG_ARCH_SH7367) += pfc-sh7367.o |
| 16 | pfc-$(CONFIG_ARCH_SH7372) := pfc-sh7372.o | 23 | pfc-$(CONFIG_ARCH_SH7377) += pfc-sh7377.o |
| 17 | obj-$(CONFIG_GENERIC_GPIO) += $(pfc-y) | 24 | pfc-$(CONFIG_ARCH_SH7372) += pfc-sh7372.o |
| 25 | pfc-$(CONFIG_ARCH_SH73A0) += pfc-sh73a0.o | ||
| 26 | |||
| 27 | # IRQ objects | ||
| 28 | obj-$(CONFIG_ARCH_SH7367) += entry-intc.o | ||
| 29 | obj-$(CONFIG_ARCH_SH7377) += entry-intc.o | ||
| 30 | obj-$(CONFIG_ARCH_SH7372) += entry-intc.o | ||
| 31 | obj-$(CONFIG_ARCH_SH73A0) += entry-gic.o | ||
| 18 | 32 | ||
| 19 | # Board objects | 33 | # Board objects |
| 20 | obj-$(CONFIG_MACH_G3EVM) += board-g3evm.o | 34 | obj-$(CONFIG_MACH_G3EVM) += board-g3evm.o |
| 21 | obj-$(CONFIG_MACH_G4EVM) += board-g4evm.o | 35 | obj-$(CONFIG_MACH_G4EVM) += board-g4evm.o |
| 22 | obj-$(CONFIG_MACH_AP4EVB) += board-ap4evb.o | 36 | obj-$(CONFIG_MACH_AP4EVB) += board-ap4evb.o |
| 37 | obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o | ||
| 38 | obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o | ||
| 39 | |||
| 40 | # Framework support | ||
| 41 | obj-$(CONFIG_SMP) += $(smp-y) | ||
| 42 | obj-$(CONFIG_GENERIC_GPIO) += $(pfc-y) | ||
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c new file mode 100644 index 000000000000..c18a740a4159 --- /dev/null +++ b/arch/arm/mach-shmobile/board-ag5evm.c | |||
| @@ -0,0 +1,315 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-shmobile/board-ag5evm.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Takashi Yoshii <yoshii.takashi.zj@renesas.com> | ||
| 5 | * Copyright (C) 2009 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; version 2 of the License. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 19 | * | ||
| 20 | */ | ||
| 21 | |||
| 22 | #include <linux/kernel.h> | ||
| 23 | #include <linux/init.h> | ||
| 24 | #include <linux/interrupt.h> | ||
| 25 | #include <linux/irq.h> | ||
| 26 | #include <linux/platform_device.h> | ||
| 27 | #include <linux/delay.h> | ||
| 28 | #include <linux/io.h> | ||
| 29 | #include <linux/dma-mapping.h> | ||
| 30 | #include <linux/serial_sci.h> | ||
| 31 | #include <linux/smsc911x.h> | ||
| 32 | #include <linux/gpio.h> | ||
| 33 | #include <linux/input.h> | ||
| 34 | #include <linux/input/sh_keysc.h> | ||
| 35 | #include <linux/mmc/host.h> | ||
| 36 | #include <linux/mmc/sh_mmcif.h> | ||
| 37 | |||
| 38 | #include <sound/sh_fsi.h> | ||
| 39 | |||
| 40 | #include <mach/hardware.h> | ||
| 41 | #include <mach/sh73a0.h> | ||
| 42 | #include <mach/common.h> | ||
| 43 | #include <asm/mach-types.h> | ||
| 44 | #include <asm/mach/arch.h> | ||
| 45 | #include <asm/mach/map.h> | ||
| 46 | #include <asm/mach/time.h> | ||
| 47 | #include <asm/hardware/gic.h> | ||
| 48 | #include <asm/hardware/cache-l2x0.h> | ||
| 49 | #include <asm/traps.h> | ||
| 50 | |||
| 51 | static struct resource smsc9220_resources[] = { | ||
| 52 | [0] = { | ||
| 53 | .start = 0x14000000, | ||
| 54 | .end = 0x14000000 + SZ_64K - 1, | ||
| 55 | .flags = IORESOURCE_MEM, | ||
| 56 | }, | ||
| 57 | [1] = { | ||
| 58 | .start = gic_spi(33), /* PINT1 */ | ||
| 59 | .flags = IORESOURCE_IRQ, | ||
| 60 | }, | ||
| 61 | }; | ||
| 62 | |||
| 63 | static struct smsc911x_platform_config smsc9220_platdata = { | ||
| 64 | .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS, | ||
| 65 | .phy_interface = PHY_INTERFACE_MODE_MII, | ||
| 66 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, | ||
| 67 | .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, | ||
| 68 | }; | ||
| 69 | |||
| 70 | static struct platform_device eth_device = { | ||
| 71 | .name = "smsc911x", | ||
| 72 | .id = 0, | ||
| 73 | .dev = { | ||
| 74 | .platform_data = &smsc9220_platdata, | ||
| 75 | }, | ||
| 76 | .resource = smsc9220_resources, | ||
| 77 | .num_resources = ARRAY_SIZE(smsc9220_resources), | ||
| 78 | }; | ||
| 79 | |||
| 80 | static struct sh_keysc_info keysc_platdata = { | ||
| 81 | .mode = SH_KEYSC_MODE_6, | ||
| 82 | .scan_timing = 3, | ||
| 83 | .delay = 100, | ||
| 84 | .keycodes = { | ||
| 85 | KEY_A, KEY_B, KEY_C, KEY_D, KEY_E, KEY_F, KEY_G, | ||
| 86 | KEY_H, KEY_I, KEY_J, KEY_K, KEY_L, KEY_M, KEY_N, | ||
| 87 | KEY_O, KEY_P, KEY_Q, KEY_R, KEY_S, KEY_T, KEY_U, | ||
| 88 | KEY_V, KEY_W, KEY_X, KEY_Y, KEY_Z, KEY_HOME, KEY_SLEEP, | ||
| 89 | KEY_SPACE, KEY_9, KEY_6, KEY_3, KEY_WAKEUP, KEY_RIGHT, \ | ||
| 90 | KEY_COFFEE, | ||
| 91 | KEY_0, KEY_8, KEY_5, KEY_2, KEY_DOWN, KEY_ENTER, KEY_UP, | ||
| 92 | KEY_KPASTERISK, KEY_7, KEY_4, KEY_1, KEY_STOP, KEY_LEFT, \ | ||
| 93 | KEY_COMPUTER, | ||
| 94 | }, | ||
| 95 | }; | ||
| 96 | |||
| 97 | static struct resource keysc_resources[] = { | ||
| 98 | [0] = { | ||
| 99 | .name = "KEYSC", | ||
| 100 | .start = 0xe61b0000, | ||
| 101 | .end = 0xe61b0098 - 1, | ||
| 102 | .flags = IORESOURCE_MEM, | ||
| 103 | }, | ||
| 104 | [1] = { | ||
| 105 | .start = gic_spi(71), | ||
| 106 | .flags = IORESOURCE_IRQ, | ||
| 107 | }, | ||
| 108 | }; | ||
| 109 | |||
| 110 | static struct platform_device keysc_device = { | ||
| 111 | .name = "sh_keysc", | ||
| 112 | .id = 0, | ||
| 113 | .num_resources = ARRAY_SIZE(keysc_resources), | ||
| 114 | .resource = keysc_resources, | ||
| 115 | .dev = { | ||
| 116 | .platform_data = &keysc_platdata, | ||
| 117 | }, | ||
| 118 | }; | ||
| 119 | |||
| 120 | /* FSI A */ | ||
| 121 | static struct sh_fsi_platform_info fsi_info = { | ||
| 122 | .porta_flags = SH_FSI_OUT_SLAVE_MODE | | ||
| 123 | SH_FSI_IN_SLAVE_MODE | | ||
| 124 | SH_FSI_OFMT(I2S) | | ||
| 125 | SH_FSI_IFMT(I2S), | ||
| 126 | }; | ||
| 127 | |||
| 128 | static struct resource fsi_resources[] = { | ||
| 129 | [0] = { | ||
| 130 | .name = "FSI", | ||
| 131 | .start = 0xEC230000, | ||
| 132 | .end = 0xEC230400 - 1, | ||
| 133 | .flags = IORESOURCE_MEM, | ||
| 134 | }, | ||
| 135 | [1] = { | ||
| 136 | .start = gic_spi(146), | ||
| 137 | .flags = IORESOURCE_IRQ, | ||
| 138 | }, | ||
| 139 | }; | ||
| 140 | |||
| 141 | static struct platform_device fsi_device = { | ||
| 142 | .name = "sh_fsi2", | ||
| 143 | .id = -1, | ||
| 144 | .num_resources = ARRAY_SIZE(fsi_resources), | ||
| 145 | .resource = fsi_resources, | ||
| 146 | .dev = { | ||
| 147 | .platform_data = &fsi_info, | ||
| 148 | }, | ||
| 149 | }; | ||
| 150 | |||
| 151 | static struct resource sh_mmcif_resources[] = { | ||
| 152 | [0] = { | ||
| 153 | .name = "MMCIF", | ||
| 154 | .start = 0xe6bd0000, | ||
| 155 | .end = 0xe6bd00ff, | ||
| 156 | .flags = IORESOURCE_MEM, | ||
| 157 | }, | ||
| 158 | [1] = { | ||
| 159 | .start = gic_spi(141), | ||
| 160 | .flags = IORESOURCE_IRQ, | ||
| 161 | }, | ||
| 162 | [2] = { | ||
| 163 | .start = gic_spi(140), | ||
| 164 | .flags = IORESOURCE_IRQ, | ||
| 165 | }, | ||
| 166 | }; | ||
| 167 | |||
| 168 | static struct sh_mmcif_plat_data sh_mmcif_platdata = { | ||
| 169 | .sup_pclk = 0, | ||
| 170 | .ocr = MMC_VDD_165_195, | ||
| 171 | .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, | ||
| 172 | }; | ||
| 173 | |||
| 174 | static struct platform_device mmc_device = { | ||
| 175 | .name = "sh_mmcif", | ||
| 176 | .id = 0, | ||
| 177 | .dev = { | ||
| 178 | .dma_mask = NULL, | ||
| 179 | .coherent_dma_mask = 0xffffffff, | ||
| 180 | .platform_data = &sh_mmcif_platdata, | ||
| 181 | }, | ||
| 182 | .num_resources = ARRAY_SIZE(sh_mmcif_resources), | ||
| 183 | .resource = sh_mmcif_resources, | ||
| 184 | }; | ||
| 185 | |||
| 186 | static struct platform_device *ag5evm_devices[] __initdata = { | ||
| 187 | ð_device, | ||
| 188 | &keysc_device, | ||
| 189 | &fsi_device, | ||
| 190 | &mmc_device, | ||
| 191 | }; | ||
| 192 | |||
| 193 | static struct map_desc ag5evm_io_desc[] __initdata = { | ||
| 194 | /* create a 1:1 entity map for 0xe6xxxxxx | ||
| 195 | * used by CPGA, INTC and PFC. | ||
| 196 | */ | ||
| 197 | { | ||
| 198 | .virtual = 0xe6000000, | ||
| 199 | .pfn = __phys_to_pfn(0xe6000000), | ||
| 200 | .length = 256 << 20, | ||
| 201 | .type = MT_DEVICE_NONSHARED | ||
| 202 | }, | ||
| 203 | }; | ||
| 204 | |||
| 205 | static void __init ag5evm_map_io(void) | ||
| 206 | { | ||
| 207 | iotable_init(ag5evm_io_desc, ARRAY_SIZE(ag5evm_io_desc)); | ||
| 208 | |||
| 209 | /* setup early devices and console here as well */ | ||
| 210 | sh73a0_add_early_devices(); | ||
| 211 | shmobile_setup_console(); | ||
| 212 | } | ||
| 213 | |||
| 214 | #define PINTC_ADDR 0xe6900000 | ||
| 215 | #define PINTER0A (PINTC_ADDR + 0xa0) | ||
| 216 | #define PINTCR0A (PINTC_ADDR + 0xb0) | ||
| 217 | |||
| 218 | void __init ag5evm_init_irq(void) | ||
| 219 | { | ||
| 220 | sh73a0_init_irq(); | ||
| 221 | |||
| 222 | /* setup PINT: enable PINTA2 as active low */ | ||
| 223 | __raw_writel(__raw_readl(PINTER0A) | (1<<29), PINTER0A); | ||
| 224 | __raw_writew(__raw_readw(PINTCR0A) | (2<<10), PINTCR0A); | ||
| 225 | } | ||
| 226 | |||
| 227 | static void __init ag5evm_init(void) | ||
| 228 | { | ||
| 229 | sh73a0_pinmux_init(); | ||
| 230 | |||
| 231 | /* enable SCIFA2 */ | ||
| 232 | gpio_request(GPIO_FN_SCIFA2_TXD1, NULL); | ||
| 233 | gpio_request(GPIO_FN_SCIFA2_RXD1, NULL); | ||
| 234 | gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL); | ||
| 235 | gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL); | ||
| 236 | |||
| 237 | /* enable KEYSC */ | ||
| 238 | gpio_request(GPIO_FN_KEYIN0_PU, NULL); | ||
| 239 | gpio_request(GPIO_FN_KEYIN1_PU, NULL); | ||
| 240 | gpio_request(GPIO_FN_KEYIN2_PU, NULL); | ||
| 241 | gpio_request(GPIO_FN_KEYIN3_PU, NULL); | ||
| 242 | gpio_request(GPIO_FN_KEYIN4_PU, NULL); | ||
| 243 | gpio_request(GPIO_FN_KEYIN5_PU, NULL); | ||
| 244 | gpio_request(GPIO_FN_KEYIN6_PU, NULL); | ||
| 245 | gpio_request(GPIO_FN_KEYIN7_PU, NULL); | ||
| 246 | gpio_request(GPIO_FN_KEYOUT0, NULL); | ||
| 247 | gpio_request(GPIO_FN_KEYOUT1, NULL); | ||
| 248 | gpio_request(GPIO_FN_KEYOUT2, NULL); | ||
| 249 | gpio_request(GPIO_FN_KEYOUT3, NULL); | ||
| 250 | gpio_request(GPIO_FN_KEYOUT4, NULL); | ||
| 251 | gpio_request(GPIO_FN_KEYOUT5, NULL); | ||
| 252 | gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL); | ||
| 253 | gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL); | ||
| 254 | gpio_request(GPIO_FN_KEYOUT8, NULL); | ||
| 255 | gpio_request(GPIO_FN_PORT149_KEYOUT9, NULL); | ||
| 256 | |||
| 257 | /* enable I2C channel 2 and 3 */ | ||
| 258 | gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL); | ||
| 259 | gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL); | ||
| 260 | gpio_request(GPIO_FN_PORT248_I2C_SCL3, NULL); | ||
| 261 | gpio_request(GPIO_FN_PORT249_I2C_SDA3, NULL); | ||
| 262 | |||
| 263 | /* enable MMCIF */ | ||
| 264 | gpio_request(GPIO_FN_MMCCLK0, NULL); | ||
| 265 | gpio_request(GPIO_FN_MMCCMD0_PU, NULL); | ||
| 266 | gpio_request(GPIO_FN_MMCD0_0, NULL); | ||
| 267 | gpio_request(GPIO_FN_MMCD0_1, NULL); | ||
| 268 | gpio_request(GPIO_FN_MMCD0_2, NULL); | ||
| 269 | gpio_request(GPIO_FN_MMCD0_3, NULL); | ||
| 270 | gpio_request(GPIO_FN_MMCD0_4, NULL); | ||
| 271 | gpio_request(GPIO_FN_MMCD0_5, NULL); | ||
| 272 | gpio_request(GPIO_FN_MMCD0_6, NULL); | ||
| 273 | gpio_request(GPIO_FN_MMCD0_7, NULL); | ||
| 274 | gpio_request(GPIO_PORT208, NULL); /* Reset */ | ||
| 275 | gpio_direction_output(GPIO_PORT208, 1); | ||
| 276 | |||
| 277 | /* enable SMSC911X */ | ||
| 278 | gpio_request(GPIO_PORT144, NULL); /* PINTA2 */ | ||
| 279 | gpio_direction_input(GPIO_PORT144); | ||
| 280 | gpio_request(GPIO_PORT145, NULL); /* RESET */ | ||
| 281 | gpio_direction_output(GPIO_PORT145, 1); | ||
| 282 | |||
| 283 | /* FSI A */ | ||
| 284 | gpio_request(GPIO_FN_FSIACK, NULL); | ||
| 285 | gpio_request(GPIO_FN_FSIAILR, NULL); | ||
| 286 | gpio_request(GPIO_FN_FSIAIBT, NULL); | ||
| 287 | gpio_request(GPIO_FN_FSIAISLD, NULL); | ||
| 288 | gpio_request(GPIO_FN_FSIAOSLD, NULL); | ||
| 289 | |||
| 290 | #ifdef CONFIG_CACHE_L2X0 | ||
| 291 | /* Shared attribute override enable, 64K*8way */ | ||
| 292 | l2x0_init(__io(0xf0100000), 0x00460000, 0xc2000fff); | ||
| 293 | #endif | ||
| 294 | sh73a0_add_standard_devices(); | ||
| 295 | platform_add_devices(ag5evm_devices, ARRAY_SIZE(ag5evm_devices)); | ||
| 296 | } | ||
| 297 | |||
| 298 | static void __init ag5evm_timer_init(void) | ||
| 299 | { | ||
| 300 | sh73a0_clock_init(); | ||
| 301 | shmobile_timer.init(); | ||
| 302 | return; | ||
| 303 | } | ||
| 304 | |||
| 305 | struct sys_timer ag5evm_timer = { | ||
| 306 | .init = ag5evm_timer_init, | ||
| 307 | }; | ||
| 308 | |||
| 309 | MACHINE_START(AG5EVM, "ag5evm") | ||
| 310 | .map_io = ag5evm_map_io, | ||
| 311 | .init_irq = ag5evm_init_irq, | ||
| 312 | .handle_irq = shmobile_handle_irq_gic, | ||
| 313 | .init_machine = ag5evm_init, | ||
| 314 | .timer = &ag5evm_timer, | ||
| 315 | MACHINE_END | ||
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index d440e5f456ad..cd79d7c1ba0d 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c | |||
| @@ -61,6 +61,7 @@ | |||
| 61 | #include <asm/mach/arch.h> | 61 | #include <asm/mach/arch.h> |
| 62 | #include <asm/mach/map.h> | 62 | #include <asm/mach/map.h> |
| 63 | #include <asm/mach/time.h> | 63 | #include <asm/mach/time.h> |
| 64 | #include <asm/setup.h> | ||
| 64 | 65 | ||
| 65 | /* | 66 | /* |
| 66 | * Address Interface BusWidth note | 67 | * Address Interface BusWidth note |
| @@ -272,6 +273,15 @@ static struct resource sh_mmcif_resources[] = { | |||
| 272 | }, | 273 | }, |
| 273 | }; | 274 | }; |
| 274 | 275 | ||
| 276 | static struct sh_mmcif_dma sh_mmcif_dma = { | ||
| 277 | .chan_priv_rx = { | ||
| 278 | .slave_id = SHDMA_SLAVE_MMCIF_RX, | ||
| 279 | }, | ||
| 280 | .chan_priv_tx = { | ||
| 281 | .slave_id = SHDMA_SLAVE_MMCIF_TX, | ||
| 282 | }, | ||
| 283 | }; | ||
| 284 | |||
| 275 | static struct sh_mmcif_plat_data sh_mmcif_plat = { | 285 | static struct sh_mmcif_plat_data sh_mmcif_plat = { |
| 276 | .sup_pclk = 0, | 286 | .sup_pclk = 0, |
| 277 | .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, | 287 | .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, |
| @@ -279,6 +289,7 @@ static struct sh_mmcif_plat_data sh_mmcif_plat = { | |||
| 279 | MMC_CAP_8_BIT_DATA | | 289 | MMC_CAP_8_BIT_DATA | |
| 280 | MMC_CAP_NEEDS_POLL, | 290 | MMC_CAP_NEEDS_POLL, |
| 281 | .get_cd = slot_cn7_get_cd, | 291 | .get_cd = slot_cn7_get_cd, |
| 292 | .dma = &sh_mmcif_dma, | ||
| 282 | }; | 293 | }; |
| 283 | 294 | ||
| 284 | static struct platform_device sh_mmcif_device = { | 295 | static struct platform_device sh_mmcif_device = { |
| @@ -501,7 +512,12 @@ static struct platform_device keysc_device = { | |||
| 501 | static struct resource mipidsi0_resources[] = { | 512 | static struct resource mipidsi0_resources[] = { |
| 502 | [0] = { | 513 | [0] = { |
| 503 | .start = 0xffc60000, | 514 | .start = 0xffc60000, |
| 504 | .end = 0xffc68fff, | 515 | .end = 0xffc63073, |
| 516 | .flags = IORESOURCE_MEM, | ||
| 517 | }, | ||
| 518 | [1] = { | ||
| 519 | .start = 0xffc68000, | ||
| 520 | .end = 0xffc680ef, | ||
| 505 | .flags = IORESOURCE_MEM, | 521 | .flags = IORESOURCE_MEM, |
| 506 | }, | 522 | }, |
| 507 | }; | 523 | }; |
| @@ -509,6 +525,7 @@ static struct resource mipidsi0_resources[] = { | |||
| 509 | static struct sh_mipi_dsi_info mipidsi0_info = { | 525 | static struct sh_mipi_dsi_info mipidsi0_info = { |
| 510 | .data_format = MIPI_RGB888, | 526 | .data_format = MIPI_RGB888, |
| 511 | .lcd_chan = &lcdc_info.ch[0], | 527 | .lcd_chan = &lcdc_info.ch[0], |
| 528 | .vsynw_offset = 17, | ||
| 512 | }; | 529 | }; |
| 513 | 530 | ||
| 514 | static struct platform_device mipidsi0_device = { | 531 | static struct platform_device mipidsi0_device = { |
| @@ -521,44 +538,6 @@ static struct platform_device mipidsi0_device = { | |||
| 521 | }, | 538 | }, |
| 522 | }; | 539 | }; |
| 523 | 540 | ||
| 524 | /* This function will disappear when we switch to (runtime) PM */ | ||
| 525 | static int __init ap4evb_init_display_clk(void) | ||
| 526 | { | ||
| 527 | struct clk *lcdc_clk; | ||
| 528 | struct clk *dsitx_clk; | ||
| 529 | int ret; | ||
| 530 | |||
| 531 | lcdc_clk = clk_get(&lcdc_device.dev, "sh_mobile_lcdc_fb.0"); | ||
| 532 | if (IS_ERR(lcdc_clk)) | ||
| 533 | return PTR_ERR(lcdc_clk); | ||
| 534 | |||
| 535 | dsitx_clk = clk_get(&mipidsi0_device.dev, "sh-mipi-dsi.0"); | ||
| 536 | if (IS_ERR(dsitx_clk)) { | ||
| 537 | ret = PTR_ERR(dsitx_clk); | ||
| 538 | goto eclkdsitxget; | ||
| 539 | } | ||
| 540 | |||
| 541 | ret = clk_enable(lcdc_clk); | ||
| 542 | if (ret < 0) | ||
| 543 | goto eclklcdcon; | ||
| 544 | |||
| 545 | ret = clk_enable(dsitx_clk); | ||
| 546 | if (ret < 0) | ||
| 547 | goto eclkdsitxon; | ||
| 548 | |||
| 549 | return 0; | ||
| 550 | |||
| 551 | eclkdsitxon: | ||
| 552 | clk_disable(lcdc_clk); | ||
| 553 | eclklcdcon: | ||
| 554 | clk_put(dsitx_clk); | ||
| 555 | eclkdsitxget: | ||
| 556 | clk_put(lcdc_clk); | ||
| 557 | |||
| 558 | return ret; | ||
| 559 | } | ||
| 560 | device_initcall(ap4evb_init_display_clk); | ||
| 561 | |||
| 562 | static struct platform_device *qhd_devices[] __initdata = { | 541 | static struct platform_device *qhd_devices[] __initdata = { |
| 563 | &mipidsi0_device, | 542 | &mipidsi0_device, |
| 564 | &keysc_device, | 543 | &keysc_device, |
| @@ -664,9 +643,8 @@ static int fsi_hdmi_set_rate(struct device *dev, int rate, int enable) | |||
| 664 | return -EIO; | 643 | return -EIO; |
| 665 | 644 | ||
| 666 | ret = __fsi_set_round_rate(fsib_clk, fsib_rate, enable); | 645 | ret = __fsi_set_round_rate(fsib_clk, fsib_rate, enable); |
| 667 | clk_put(fsib_clk); | ||
| 668 | if (ret < 0) | 646 | if (ret < 0) |
| 669 | return ret; | 647 | goto fsi_set_rate_end; |
| 670 | 648 | ||
| 671 | /* FSI DIV setting */ | 649 | /* FSI DIV setting */ |
| 672 | ret = __fsi_set_round_rate(fdiv_clk, fdiv_rate, enable); | 650 | ret = __fsi_set_round_rate(fdiv_clk, fdiv_rate, enable); |
| @@ -674,10 +652,14 @@ static int fsi_hdmi_set_rate(struct device *dev, int rate, int enable) | |||
| 674 | /* disable FSI B */ | 652 | /* disable FSI B */ |
| 675 | if (enable) | 653 | if (enable) |
| 676 | __fsi_set_round_rate(fsib_clk, fsib_rate, 0); | 654 | __fsi_set_round_rate(fsib_clk, fsib_rate, 0); |
| 677 | return ret; | 655 | goto fsi_set_rate_end; |
| 678 | } | 656 | } |
| 679 | 657 | ||
| 680 | return ackmd_bpfmd; | 658 | ret = ackmd_bpfmd; |
| 659 | |||
| 660 | fsi_set_rate_end: | ||
| 661 | clk_put(fsib_clk); | ||
| 662 | return ret; | ||
| 681 | } | 663 | } |
| 682 | 664 | ||
| 683 | static int fsi_set_rate(struct device *dev, int is_porta, int rate, int enable) | 665 | static int fsi_set_rate(struct device *dev, int is_porta, int rate, int enable) |
| @@ -764,10 +746,15 @@ static struct platform_device lcdc1_device = { | |||
| 764 | }, | 746 | }, |
| 765 | }; | 747 | }; |
| 766 | 748 | ||
| 749 | static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq, | ||
| 750 | unsigned long *parent_freq); | ||
| 751 | |||
| 752 | |||
| 767 | static struct sh_mobile_hdmi_info hdmi_info = { | 753 | static struct sh_mobile_hdmi_info hdmi_info = { |
| 768 | .lcd_chan = &sh_mobile_lcdc1_info.ch[0], | 754 | .lcd_chan = &sh_mobile_lcdc1_info.ch[0], |
| 769 | .lcd_dev = &lcdc1_device.dev, | 755 | .lcd_dev = &lcdc1_device.dev, |
| 770 | .flags = HDMI_SND_SRC_SPDIF, | 756 | .flags = HDMI_SND_SRC_SPDIF, |
| 757 | .clk_optimize_parent = ap4evb_clk_optimize, | ||
| 771 | }; | 758 | }; |
| 772 | 759 | ||
| 773 | static struct resource hdmi_resources[] = { | 760 | static struct resource hdmi_resources[] = { |
| @@ -794,6 +781,25 @@ static struct platform_device hdmi_device = { | |||
| 794 | }, | 781 | }, |
| 795 | }; | 782 | }; |
| 796 | 783 | ||
| 784 | static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq, | ||
| 785 | unsigned long *parent_freq) | ||
| 786 | { | ||
| 787 | struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick"); | ||
| 788 | long error; | ||
| 789 | |||
| 790 | if (IS_ERR(hdmi_ick)) { | ||
| 791 | int ret = PTR_ERR(hdmi_ick); | ||
| 792 | pr_err("Cannot get HDMI ICK: %d\n", ret); | ||
| 793 | return ret; | ||
| 794 | } | ||
| 795 | |||
| 796 | error = clk_round_parent(hdmi_ick, target, best_freq, parent_freq, 1, 64); | ||
| 797 | |||
| 798 | clk_put(hdmi_ick); | ||
| 799 | |||
| 800 | return error; | ||
| 801 | } | ||
| 802 | |||
| 797 | static struct gpio_led ap4evb_leds[] = { | 803 | static struct gpio_led ap4evb_leds[] = { |
| 798 | { | 804 | { |
| 799 | .name = "led4", | 805 | .name = "led4", |
| @@ -1181,7 +1187,7 @@ static void __init ap4evb_init(void) | |||
| 1181 | gpio_request(GPIO_FN_OVCN2_1, NULL); | 1187 | gpio_request(GPIO_FN_OVCN2_1, NULL); |
| 1182 | 1188 | ||
| 1183 | /* setup USB phy */ | 1189 | /* setup USB phy */ |
| 1184 | __raw_writew(0x8a0a, 0xE6058130); /* USBCR2 */ | 1190 | __raw_writew(0x8a0a, 0xE6058130); /* USBCR4 */ |
| 1185 | 1191 | ||
| 1186 | /* enable FSI2 port A (ak4643) */ | 1192 | /* enable FSI2 port A (ak4643) */ |
| 1187 | gpio_request(GPIO_FN_FSIAIBT, NULL); | 1193 | gpio_request(GPIO_FN_FSIAIBT, NULL); |
| @@ -1355,6 +1361,7 @@ static struct sys_timer ap4evb_timer = { | |||
| 1355 | MACHINE_START(AP4EVB, "ap4evb") | 1361 | MACHINE_START(AP4EVB, "ap4evb") |
| 1356 | .map_io = ap4evb_map_io, | 1362 | .map_io = ap4evb_map_io, |
| 1357 | .init_irq = sh7372_init_irq, | 1363 | .init_irq = sh7372_init_irq, |
| 1364 | .handle_irq = shmobile_handle_irq_intc, | ||
| 1358 | .init_machine = ap4evb_init, | 1365 | .init_machine = ap4evb_init, |
| 1359 | .timer = &ap4evb_timer, | 1366 | .timer = &ap4evb_timer, |
| 1360 | MACHINE_END | 1367 | MACHINE_END |
diff --git a/arch/arm/mach-shmobile/board-g3evm.c b/arch/arm/mach-shmobile/board-g3evm.c index 3b83d6320bec..686b304a7708 100644 --- a/arch/arm/mach-shmobile/board-g3evm.c +++ b/arch/arm/mach-shmobile/board-g3evm.c | |||
| @@ -367,6 +367,7 @@ static struct sys_timer g3evm_timer = { | |||
| 367 | MACHINE_START(G3EVM, "g3evm") | 367 | MACHINE_START(G3EVM, "g3evm") |
| 368 | .map_io = g3evm_map_io, | 368 | .map_io = g3evm_map_io, |
| 369 | .init_irq = sh7367_init_irq, | 369 | .init_irq = sh7367_init_irq, |
| 370 | .handle_irq = shmobile_handle_irq_intc, | ||
| 370 | .init_machine = g3evm_init, | 371 | .init_machine = g3evm_init, |
| 371 | .timer = &g3evm_timer, | 372 | .timer = &g3evm_timer, |
| 372 | MACHINE_END | 373 | MACHINE_END |
diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c index 5b3b582ef3f2..c13f01280b7e 100644 --- a/arch/arm/mach-shmobile/board-g4evm.c +++ b/arch/arm/mach-shmobile/board-g4evm.c | |||
| @@ -394,6 +394,7 @@ static struct sys_timer g4evm_timer = { | |||
| 394 | MACHINE_START(G4EVM, "g4evm") | 394 | MACHINE_START(G4EVM, "g4evm") |
| 395 | .map_io = g4evm_map_io, | 395 | .map_io = g4evm_map_io, |
| 396 | .init_irq = sh7377_init_irq, | 396 | .init_irq = sh7377_init_irq, |
| 397 | .handle_irq = shmobile_handle_irq_intc, | ||
| 397 | .init_machine = g4evm_init, | 398 | .init_machine = g4evm_init, |
| 398 | .timer = &g4evm_timer, | 399 | .timer = &g4evm_timer, |
| 399 | MACHINE_END | 400 | MACHINE_END |
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c new file mode 100644 index 000000000000..5bcf5c1e1399 --- /dev/null +++ b/arch/arm/mach-shmobile/board-mackerel.c | |||
| @@ -0,0 +1,1200 @@ | |||
| 1 | /* | ||
| 2 | * mackerel board support | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Renesas Solutions Corp. | ||
| 5 | * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | ||
| 6 | * | ||
| 7 | * based on ap4evb | ||
| 8 | * Copyright (C) 2010 Magnus Damm | ||
| 9 | * Copyright (C) 2008 Yoshihiro Shimoda | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License as published by | ||
| 13 | * the Free Software Foundation; version 2 of the License. | ||
| 14 | * | ||
| 15 | * This program is distributed in the hope that it will be useful, | ||
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 18 | * GNU General Public License for more details. | ||
| 19 | * | ||
| 20 | * You should have received a copy of the GNU General Public License | ||
| 21 | * along with this program; if not, write to the Free Software | ||
| 22 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 23 | */ | ||
| 24 | #include <linux/delay.h> | ||
| 25 | #include <linux/kernel.h> | ||
| 26 | #include <linux/init.h> | ||
| 27 | #include <linux/interrupt.h> | ||
| 28 | #include <linux/irq.h> | ||
| 29 | #include <linux/platform_device.h> | ||
| 30 | #include <linux/gpio.h> | ||
| 31 | #include <linux/input.h> | ||
| 32 | #include <linux/io.h> | ||
| 33 | #include <linux/i2c.h> | ||
| 34 | #include <linux/leds.h> | ||
| 35 | #include <linux/mfd/sh_mobile_sdhi.h> | ||
| 36 | #include <linux/mfd/tmio.h> | ||
| 37 | #include <linux/mmc/host.h> | ||
| 38 | #include <linux/mmc/sh_mmcif.h> | ||
| 39 | #include <linux/mtd/mtd.h> | ||
| 40 | #include <linux/mtd/partitions.h> | ||
| 41 | #include <linux/mtd/physmap.h> | ||
| 42 | #include <linux/smsc911x.h> | ||
| 43 | #include <linux/sh_intc.h> | ||
| 44 | #include <linux/tca6416_keypad.h> | ||
| 45 | #include <linux/usb/r8a66597.h> | ||
| 46 | |||
| 47 | #include <video/sh_mobile_hdmi.h> | ||
| 48 | #include <video/sh_mobile_lcdc.h> | ||
| 49 | #include <media/sh_mobile_ceu.h> | ||
| 50 | #include <media/soc_camera.h> | ||
| 51 | #include <media/soc_camera_platform.h> | ||
| 52 | #include <sound/sh_fsi.h> | ||
| 53 | |||
| 54 | #include <mach/common.h> | ||
| 55 | #include <mach/sh7372.h> | ||
| 56 | |||
| 57 | #include <asm/mach/arch.h> | ||
| 58 | #include <asm/mach/time.h> | ||
| 59 | #include <asm/mach/map.h> | ||
| 60 | #include <asm/mach-types.h> | ||
| 61 | |||
| 62 | /* | ||
| 63 | * Address Interface BusWidth note | ||
| 64 | * ------------------------------------------------------------------ | ||
| 65 | * 0x0000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = ON | ||
| 66 | * 0x0800_0000 user area - | ||
| 67 | * 0x1000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = OFF | ||
| 68 | * 0x1400_0000 Ether (LAN9220) 16bit | ||
| 69 | * 0x1600_0000 user area - cannot use with NAND | ||
| 70 | * 0x1800_0000 user area - | ||
| 71 | * 0x1A00_0000 - | ||
| 72 | * 0x4000_0000 LPDDR2-SDRAM (POP) 32bit | ||
| 73 | */ | ||
| 74 | |||
| 75 | /* | ||
| 76 | * CPU mode | ||
| 77 | * | ||
| 78 | * SW4 | Boot Area| Master | Remarks | ||
| 79 | * 1 | 2 | 3 | 4 | 5 | 6 | 8 | | Processor| | ||
| 80 | * ----+-----+-----+-----+-----+-----+-----+----------+----------+-------------- | ||
| 81 | * ON | ON | OFF | ON | ON | OFF | OFF | External | System | External ROM | ||
| 82 | * ON | ON | ON | ON | ON | OFF | OFF | External | System | ROM Debug | ||
| 83 | * ON | ON | X | ON | OFF | OFF | OFF | Built-in | System | ROM Debug | ||
| 84 | * X | OFF | X | X | X | X | OFF | Built-in | System | MaskROM | ||
| 85 | * OFF | X | X | X | X | X | OFF | Built-in | System | MaskROM | ||
| 86 | * X | X | X | OFF | X | X | OFF | Built-in | System | MaskROM | ||
| 87 | * OFF | ON | OFF | X | X | OFF | ON | External | System | Standalone | ||
| 88 | * ON | OFF | OFF | X | X | OFF | ON | External | Realtime | Standalone | ||
| 89 | */ | ||
| 90 | |||
| 91 | /* | ||
| 92 | * NOR Flash ROM | ||
| 93 | * | ||
| 94 | * SW1 | SW2 | SW7 | NOR Flash ROM | ||
| 95 | * bit1 | bit1 bit2 | bit1 | Memory allocation | ||
| 96 | * ------+------------+------+------------------ | ||
| 97 | * OFF | ON OFF | ON | Area 0 | ||
| 98 | * OFF | ON OFF | OFF | Area 4 | ||
| 99 | */ | ||
| 100 | |||
| 101 | /* | ||
| 102 | * SMSC 9220 | ||
| 103 | * | ||
| 104 | * SW1 SMSC 9220 | ||
| 105 | * ----------------------- | ||
| 106 | * ON access disable | ||
| 107 | * OFF access enable | ||
| 108 | */ | ||
| 109 | |||
| 110 | /* | ||
| 111 | * NAND Flash ROM | ||
| 112 | * | ||
| 113 | * SW1 | SW2 | SW7 | NAND Flash ROM | ||
| 114 | * bit1 | bit1 bit2 | bit2 | Memory allocation | ||
| 115 | * ------+------------+------+------------------ | ||
| 116 | * OFF | ON OFF | ON | FCE 0 | ||
| 117 | * OFF | ON OFF | OFF | FCE 1 | ||
| 118 | */ | ||
| 119 | |||
| 120 | /* | ||
| 121 | * External interrupt pin settings | ||
| 122 | * | ||
| 123 | * IRQX | pin setting | device | level | ||
| 124 | * ------+--------------------+--------------------+------- | ||
| 125 | * IRQ0 | ICR1A.IRQ0SA=0010 | SDHI2 card detect | Low | ||
| 126 | * IRQ6 | ICR1A.IRQ6SA=0011 | Ether(LAN9220) | High | ||
| 127 | * IRQ7 | ICR1A.IRQ7SA=0010 | LCD Tuch Panel | Low | ||
| 128 | * IRQ8 | ICR2A.IRQ8SA=0010 | MMC/SD card detect | Low | ||
| 129 | * IRQ9 | ICR2A.IRQ9SA=0010 | KEY(TCA6408) | Low | ||
| 130 | * IRQ21 | ICR4A.IRQ21SA=0011 | Sensor(ADXL345) | High | ||
| 131 | * IRQ22 | ICR4A.IRQ22SA=0011 | Sensor(AK8975) | High | ||
| 132 | */ | ||
| 133 | |||
| 134 | /* | ||
| 135 | * USB | ||
| 136 | * | ||
| 137 | * USB0 : CN22 : Function | ||
| 138 | * USB1 : CN31 : Function/Host *1 | ||
| 139 | * | ||
| 140 | * J30 (for CN31) *1 | ||
| 141 | * ----------+---------------+------------- | ||
| 142 | * 1-2 short | VBUS 5V | Host | ||
| 143 | * open | external VBUS | Function | ||
| 144 | * | ||
| 145 | * *1 | ||
| 146 | * CN31 is used as Host in Linux. | ||
| 147 | */ | ||
| 148 | |||
| 149 | /* | ||
| 150 | * SDHI0 (CN12) | ||
| 151 | * | ||
| 152 | * SW56 : OFF | ||
| 153 | * | ||
| 154 | */ | ||
| 155 | |||
| 156 | /* MMC /SDHI1 (CN7) | ||
| 157 | * | ||
| 158 | * I/O voltage : 1.8v | ||
| 159 | * | ||
| 160 | * Power voltage : 1.8v or 3.3v | ||
| 161 | * J22 : select power voltage *1 | ||
| 162 | * 1-2 pin : 1.8v | ||
| 163 | * 2-3 pin : 3.3v | ||
| 164 | * | ||
| 165 | * *1 | ||
| 166 | * Please change J22 depends the card to be used. | ||
| 167 | * MMC's OCR field set to support either voltage for the card inserted. | ||
| 168 | * | ||
| 169 | * SW1 | SW33 | ||
| 170 | * | bit1 | bit2 | bit3 | bit4 | ||
| 171 | * -------------+------+------+------+------- | ||
| 172 | * MMC0 OFF | OFF | ON | ON | X | ||
| 173 | * MMC1 ON | OFF | ON | X | ON | ||
| 174 | * SDHI1 OFF | ON | X | OFF | ON | ||
| 175 | * | ||
| 176 | */ | ||
| 177 | |||
| 178 | /* | ||
| 179 | * SDHI2 (CN23) | ||
| 180 | * | ||
| 181 | * microSD card sloct | ||
| 182 | * | ||
| 183 | */ | ||
| 184 | |||
| 185 | /* | ||
| 186 | * FIXME !! | ||
| 187 | * | ||
| 188 | * gpio_no_direction | ||
| 189 | * are quick_hack. | ||
| 190 | * | ||
| 191 | * current gpio frame work doesn't have | ||
| 192 | * the method to control only pull up/down/free. | ||
| 193 | * this function should be replaced by correct gpio function | ||
| 194 | */ | ||
| 195 | static void __init gpio_no_direction(u32 addr) | ||
| 196 | { | ||
| 197 | __raw_writeb(0x00, addr); | ||
| 198 | } | ||
| 199 | |||
| 200 | /* MTD */ | ||
| 201 | static struct mtd_partition nor_flash_partitions[] = { | ||
| 202 | { | ||
| 203 | .name = "loader", | ||
| 204 | .offset = 0x00000000, | ||
| 205 | .size = 512 * 1024, | ||
| 206 | .mask_flags = MTD_WRITEABLE, | ||
| 207 | }, | ||
| 208 | { | ||
| 209 | .name = "bootenv", | ||
| 210 | .offset = MTDPART_OFS_APPEND, | ||
| 211 | .size = 512 * 1024, | ||
| 212 | .mask_flags = MTD_WRITEABLE, | ||
| 213 | }, | ||
| 214 | { | ||
| 215 | .name = "kernel_ro", | ||
| 216 | .offset = MTDPART_OFS_APPEND, | ||
| 217 | .size = 8 * 1024 * 1024, | ||
| 218 | .mask_flags = MTD_WRITEABLE, | ||
| 219 | }, | ||
| 220 | { | ||
| 221 | .name = "kernel", | ||
| 222 | .offset = MTDPART_OFS_APPEND, | ||
| 223 | .size = 8 * 1024 * 1024, | ||
| 224 | }, | ||
| 225 | { | ||
| 226 | .name = "data", | ||
| 227 | .offset = MTDPART_OFS_APPEND, | ||
| 228 | .size = MTDPART_SIZ_FULL, | ||
| 229 | }, | ||
| 230 | }; | ||
| 231 | |||
| 232 | static struct physmap_flash_data nor_flash_data = { | ||
| 233 | .width = 2, | ||
| 234 | .parts = nor_flash_partitions, | ||
| 235 | .nr_parts = ARRAY_SIZE(nor_flash_partitions), | ||
| 236 | }; | ||
| 237 | |||
| 238 | static struct resource nor_flash_resources[] = { | ||
| 239 | [0] = { | ||
| 240 | .start = 0x00000000, | ||
| 241 | .end = 0x08000000 - 1, | ||
| 242 | .flags = IORESOURCE_MEM, | ||
| 243 | } | ||
| 244 | }; | ||
| 245 | |||
| 246 | static struct platform_device nor_flash_device = { | ||
| 247 | .name = "physmap-flash", | ||
| 248 | .dev = { | ||
| 249 | .platform_data = &nor_flash_data, | ||
| 250 | }, | ||
| 251 | .num_resources = ARRAY_SIZE(nor_flash_resources), | ||
| 252 | .resource = nor_flash_resources, | ||
| 253 | }; | ||
| 254 | |||
| 255 | /* SMSC */ | ||
| 256 | static struct resource smc911x_resources[] = { | ||
| 257 | { | ||
| 258 | .start = 0x14000000, | ||
| 259 | .end = 0x16000000 - 1, | ||
| 260 | .flags = IORESOURCE_MEM, | ||
| 261 | }, { | ||
| 262 | .start = evt2irq(0x02c0) /* IRQ6A */, | ||
| 263 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, | ||
| 264 | }, | ||
| 265 | }; | ||
| 266 | |||
| 267 | static struct smsc911x_platform_config smsc911x_info = { | ||
| 268 | .flags = SMSC911X_USE_16BIT | SMSC911X_SAVE_MAC_ADDRESS, | ||
| 269 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, | ||
| 270 | .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, | ||
| 271 | }; | ||
| 272 | |||
| 273 | static struct platform_device smc911x_device = { | ||
| 274 | .name = "smsc911x", | ||
| 275 | .id = -1, | ||
| 276 | .num_resources = ARRAY_SIZE(smc911x_resources), | ||
| 277 | .resource = smc911x_resources, | ||
| 278 | .dev = { | ||
| 279 | .platform_data = &smsc911x_info, | ||
| 280 | }, | ||
| 281 | }; | ||
| 282 | |||
| 283 | /* LCDC */ | ||
| 284 | static struct fb_videomode mackerel_lcdc_modes[] = { | ||
| 285 | { | ||
| 286 | .name = "WVGA Panel", | ||
| 287 | .xres = 800, | ||
| 288 | .yres = 480, | ||
| 289 | .left_margin = 220, | ||
| 290 | .right_margin = 110, | ||
| 291 | .hsync_len = 70, | ||
| 292 | .upper_margin = 20, | ||
| 293 | .lower_margin = 5, | ||
| 294 | .vsync_len = 5, | ||
| 295 | .sync = 0, | ||
| 296 | }, | ||
| 297 | }; | ||
| 298 | |||
| 299 | static struct sh_mobile_lcdc_info lcdc_info = { | ||
| 300 | .clock_source = LCDC_CLK_BUS, | ||
| 301 | .ch[0] = { | ||
| 302 | .chan = LCDC_CHAN_MAINLCD, | ||
| 303 | .bpp = 16, | ||
| 304 | .lcd_cfg = mackerel_lcdc_modes, | ||
| 305 | .num_cfg = ARRAY_SIZE(mackerel_lcdc_modes), | ||
| 306 | .interface_type = RGB24, | ||
| 307 | .clock_divider = 2, | ||
| 308 | .flags = 0, | ||
| 309 | .lcd_size_cfg.width = 152, | ||
| 310 | .lcd_size_cfg.height = 91, | ||
| 311 | } | ||
| 312 | }; | ||
| 313 | |||
| 314 | static struct resource lcdc_resources[] = { | ||
| 315 | [0] = { | ||
| 316 | .name = "LCDC", | ||
| 317 | .start = 0xfe940000, | ||
| 318 | .end = 0xfe943fff, | ||
| 319 | .flags = IORESOURCE_MEM, | ||
| 320 | }, | ||
| 321 | [1] = { | ||
| 322 | .start = intcs_evt2irq(0x580), | ||
| 323 | .flags = IORESOURCE_IRQ, | ||
| 324 | }, | ||
| 325 | }; | ||
| 326 | |||
| 327 | static struct platform_device lcdc_device = { | ||
| 328 | .name = "sh_mobile_lcdc_fb", | ||
| 329 | .num_resources = ARRAY_SIZE(lcdc_resources), | ||
| 330 | .resource = lcdc_resources, | ||
| 331 | .dev = { | ||
| 332 | .platform_data = &lcdc_info, | ||
| 333 | .coherent_dma_mask = ~0, | ||
| 334 | }, | ||
| 335 | }; | ||
| 336 | |||
| 337 | /* HDMI */ | ||
| 338 | static struct sh_mobile_lcdc_info hdmi_lcdc_info = { | ||
| 339 | .clock_source = LCDC_CLK_EXTERNAL, | ||
| 340 | .ch[0] = { | ||
| 341 | .chan = LCDC_CHAN_MAINLCD, | ||
| 342 | .bpp = 16, | ||
| 343 | .interface_type = RGB24, | ||
| 344 | .clock_divider = 1, | ||
| 345 | .flags = LCDC_FLAGS_DWPOL, | ||
| 346 | } | ||
| 347 | }; | ||
| 348 | |||
| 349 | static struct resource hdmi_lcdc_resources[] = { | ||
| 350 | [0] = { | ||
| 351 | .name = "LCDC1", | ||
| 352 | .start = 0xfe944000, | ||
| 353 | .end = 0xfe947fff, | ||
| 354 | .flags = IORESOURCE_MEM, | ||
| 355 | }, | ||
| 356 | [1] = { | ||
| 357 | .start = intcs_evt2irq(0x1780), | ||
| 358 | .flags = IORESOURCE_IRQ, | ||
| 359 | }, | ||
| 360 | }; | ||
| 361 | |||
| 362 | static struct platform_device hdmi_lcdc_device = { | ||
| 363 | .name = "sh_mobile_lcdc_fb", | ||
| 364 | .num_resources = ARRAY_SIZE(hdmi_lcdc_resources), | ||
| 365 | .resource = hdmi_lcdc_resources, | ||
| 366 | .id = 1, | ||
| 367 | .dev = { | ||
| 368 | .platform_data = &hdmi_lcdc_info, | ||
| 369 | .coherent_dma_mask = ~0, | ||
| 370 | }, | ||
| 371 | }; | ||
| 372 | |||
| 373 | static struct sh_mobile_hdmi_info hdmi_info = { | ||
| 374 | .lcd_chan = &hdmi_lcdc_info.ch[0], | ||
| 375 | .lcd_dev = &hdmi_lcdc_device.dev, | ||
| 376 | .flags = HDMI_SND_SRC_SPDIF, | ||
| 377 | }; | ||
| 378 | |||
| 379 | static struct resource hdmi_resources[] = { | ||
| 380 | [0] = { | ||
| 381 | .name = "HDMI", | ||
| 382 | .start = 0xe6be0000, | ||
| 383 | .end = 0xe6be00ff, | ||
| 384 | .flags = IORESOURCE_MEM, | ||
| 385 | }, | ||
| 386 | [1] = { | ||
| 387 | /* There's also an HDMI interrupt on INTCS @ 0x18e0 */ | ||
| 388 | .start = evt2irq(0x17e0), | ||
| 389 | .flags = IORESOURCE_IRQ, | ||
| 390 | }, | ||
| 391 | }; | ||
| 392 | |||
| 393 | static struct platform_device hdmi_device = { | ||
| 394 | .name = "sh-mobile-hdmi", | ||
| 395 | .num_resources = ARRAY_SIZE(hdmi_resources), | ||
| 396 | .resource = hdmi_resources, | ||
| 397 | .id = -1, | ||
| 398 | .dev = { | ||
| 399 | .platform_data = &hdmi_info, | ||
| 400 | }, | ||
| 401 | }; | ||
| 402 | |||
| 403 | static int __init hdmi_init_pm_clock(void) | ||
| 404 | { | ||
| 405 | struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick"); | ||
| 406 | int ret; | ||
| 407 | long rate; | ||
| 408 | |||
| 409 | if (IS_ERR(hdmi_ick)) { | ||
| 410 | ret = PTR_ERR(hdmi_ick); | ||
| 411 | pr_err("Cannot get HDMI ICK: %d\n", ret); | ||
| 412 | goto out; | ||
| 413 | } | ||
| 414 | |||
| 415 | ret = clk_set_parent(&sh7372_pllc2_clk, &sh7372_dv_clki_div2_clk); | ||
| 416 | if (ret < 0) { | ||
| 417 | pr_err("Cannot set PLLC2 parent: %d, %d users\n", | ||
| 418 | ret, sh7372_pllc2_clk.usecount); | ||
| 419 | goto out; | ||
| 420 | } | ||
| 421 | |||
| 422 | pr_debug("PLLC2 initial frequency %lu\n", | ||
| 423 | clk_get_rate(&sh7372_pllc2_clk)); | ||
| 424 | |||
| 425 | rate = clk_round_rate(&sh7372_pllc2_clk, 594000000); | ||
| 426 | if (rate < 0) { | ||
| 427 | pr_err("Cannot get suitable rate: %ld\n", rate); | ||
| 428 | ret = rate; | ||
| 429 | goto out; | ||
| 430 | } | ||
| 431 | |||
| 432 | ret = clk_set_rate(&sh7372_pllc2_clk, rate); | ||
| 433 | if (ret < 0) { | ||
| 434 | pr_err("Cannot set rate %ld: %d\n", rate, ret); | ||
| 435 | goto out; | ||
| 436 | } | ||
| 437 | |||
| 438 | ret = clk_enable(&sh7372_pllc2_clk); | ||
| 439 | if (ret < 0) { | ||
| 440 | pr_err("Cannot enable pllc2 clock\n"); | ||
| 441 | goto out; | ||
| 442 | } | ||
| 443 | |||
| 444 | pr_debug("PLLC2 set frequency %lu\n", rate); | ||
| 445 | |||
| 446 | ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk); | ||
| 447 | if (ret < 0) { | ||
| 448 | pr_err("Cannot set HDMI parent: %d\n", ret); | ||
| 449 | goto out; | ||
| 450 | } | ||
| 451 | |||
| 452 | out: | ||
| 453 | if (!IS_ERR(hdmi_ick)) | ||
| 454 | clk_put(hdmi_ick); | ||
| 455 | return ret; | ||
| 456 | } | ||
| 457 | device_initcall(hdmi_init_pm_clock); | ||
| 458 | |||
| 459 | /* USB1 (Host) */ | ||
| 460 | static void usb1_host_port_power(int port, int power) | ||
| 461 | { | ||
| 462 | if (!power) /* only power-on is supported for now */ | ||
| 463 | return; | ||
| 464 | |||
| 465 | /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */ | ||
| 466 | __raw_writew(__raw_readw(0xE68B0008) | 0x600, 0xE68B0008); | ||
| 467 | } | ||
| 468 | |||
| 469 | static struct r8a66597_platdata usb1_host_data = { | ||
| 470 | .on_chip = 1, | ||
| 471 | .port_power = usb1_host_port_power, | ||
| 472 | }; | ||
| 473 | |||
| 474 | static struct resource usb1_host_resources[] = { | ||
| 475 | [0] = { | ||
| 476 | .name = "USBHS", | ||
| 477 | .start = 0xE68B0000, | ||
| 478 | .end = 0xE68B00E6 - 1, | ||
| 479 | .flags = IORESOURCE_MEM, | ||
| 480 | }, | ||
| 481 | [1] = { | ||
| 482 | .start = evt2irq(0x1ce0) /* USB1_USB1I0 */, | ||
| 483 | .flags = IORESOURCE_IRQ, | ||
| 484 | }, | ||
| 485 | }; | ||
| 486 | |||
| 487 | static struct platform_device usb1_host_device = { | ||
| 488 | .name = "r8a66597_hcd", | ||
| 489 | .id = 1, | ||
| 490 | .dev = { | ||
| 491 | .dma_mask = NULL, /* not use dma */ | ||
| 492 | .coherent_dma_mask = 0xffffffff, | ||
| 493 | .platform_data = &usb1_host_data, | ||
| 494 | }, | ||
| 495 | .num_resources = ARRAY_SIZE(usb1_host_resources), | ||
| 496 | .resource = usb1_host_resources, | ||
| 497 | }; | ||
| 498 | |||
| 499 | /* LED */ | ||
| 500 | static struct gpio_led mackerel_leds[] = { | ||
| 501 | { | ||
| 502 | .name = "led0", | ||
| 503 | .gpio = GPIO_PORT0, | ||
| 504 | .default_state = LEDS_GPIO_DEFSTATE_ON, | ||
| 505 | }, | ||
| 506 | { | ||
| 507 | .name = "led1", | ||
| 508 | .gpio = GPIO_PORT1, | ||
| 509 | .default_state = LEDS_GPIO_DEFSTATE_ON, | ||
| 510 | }, | ||
| 511 | { | ||
| 512 | .name = "led2", | ||
| 513 | .gpio = GPIO_PORT2, | ||
| 514 | .default_state = LEDS_GPIO_DEFSTATE_ON, | ||
| 515 | }, | ||
| 516 | { | ||
| 517 | .name = "led3", | ||
| 518 | .gpio = GPIO_PORT159, | ||
| 519 | .default_state = LEDS_GPIO_DEFSTATE_ON, | ||
| 520 | } | ||
| 521 | }; | ||
| 522 | |||
| 523 | static struct gpio_led_platform_data mackerel_leds_pdata = { | ||
| 524 | .leds = mackerel_leds, | ||
| 525 | .num_leds = ARRAY_SIZE(mackerel_leds), | ||
| 526 | }; | ||
| 527 | |||
| 528 | static struct platform_device leds_device = { | ||
| 529 | .name = "leds-gpio", | ||
| 530 | .id = 0, | ||
| 531 | .dev = { | ||
| 532 | .platform_data = &mackerel_leds_pdata, | ||
| 533 | }, | ||
| 534 | }; | ||
| 535 | |||
| 536 | /* FSI */ | ||
| 537 | #define IRQ_FSI evt2irq(0x1840) | ||
| 538 | static int __fsi_set_round_rate(struct clk *clk, long rate, int enable) | ||
| 539 | { | ||
| 540 | int ret; | ||
| 541 | |||
| 542 | if (rate <= 0) | ||
| 543 | return 0; | ||
| 544 | |||
| 545 | if (!enable) { | ||
| 546 | clk_disable(clk); | ||
| 547 | return 0; | ||
| 548 | } | ||
| 549 | |||
| 550 | ret = clk_set_rate(clk, clk_round_rate(clk, rate)); | ||
| 551 | if (ret < 0) | ||
| 552 | return ret; | ||
| 553 | |||
| 554 | return clk_enable(clk); | ||
| 555 | } | ||
| 556 | |||
| 557 | static int fsi_set_rate(struct device *dev, int is_porta, int rate, int enable) | ||
| 558 | { | ||
| 559 | struct clk *fsib_clk; | ||
| 560 | struct clk *fdiv_clk = &sh7372_fsidivb_clk; | ||
| 561 | long fsib_rate = 0; | ||
| 562 | long fdiv_rate = 0; | ||
| 563 | int ackmd_bpfmd; | ||
| 564 | int ret; | ||
| 565 | |||
| 566 | /* FSIA is slave mode. nothing to do here */ | ||
| 567 | if (is_porta) | ||
| 568 | return 0; | ||
| 569 | |||
| 570 | /* clock start */ | ||
| 571 | switch (rate) { | ||
| 572 | case 44100: | ||
| 573 | fsib_rate = rate * 256; | ||
| 574 | ackmd_bpfmd = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64; | ||
| 575 | break; | ||
| 576 | case 48000: | ||
| 577 | fsib_rate = 85428000; /* around 48kHz x 256 x 7 */ | ||
| 578 | fdiv_rate = rate * 256; | ||
| 579 | ackmd_bpfmd = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64; | ||
| 580 | break; | ||
| 581 | default: | ||
| 582 | pr_err("unsupported rate in FSI2 port B\n"); | ||
| 583 | return -EINVAL; | ||
| 584 | } | ||
| 585 | |||
| 586 | /* FSI B setting */ | ||
| 587 | fsib_clk = clk_get(dev, "ickb"); | ||
| 588 | if (IS_ERR(fsib_clk)) | ||
| 589 | return -EIO; | ||
| 590 | |||
| 591 | /* fsib */ | ||
| 592 | ret = __fsi_set_round_rate(fsib_clk, fsib_rate, enable); | ||
| 593 | if (ret < 0) | ||
| 594 | goto fsi_set_rate_end; | ||
| 595 | |||
| 596 | /* FSI DIV */ | ||
| 597 | ret = __fsi_set_round_rate(fdiv_clk, fdiv_rate, enable); | ||
| 598 | if (ret < 0) { | ||
| 599 | /* disable FSI B */ | ||
| 600 | if (enable) | ||
| 601 | __fsi_set_round_rate(fsib_clk, fsib_rate, 0); | ||
| 602 | goto fsi_set_rate_end; | ||
| 603 | } | ||
| 604 | |||
| 605 | ret = ackmd_bpfmd; | ||
| 606 | |||
| 607 | fsi_set_rate_end: | ||
| 608 | clk_put(fsib_clk); | ||
| 609 | return ret; | ||
| 610 | } | ||
| 611 | |||
| 612 | static struct sh_fsi_platform_info fsi_info = { | ||
| 613 | .porta_flags = SH_FSI_BRS_INV | | ||
| 614 | SH_FSI_OUT_SLAVE_MODE | | ||
| 615 | SH_FSI_IN_SLAVE_MODE | | ||
| 616 | SH_FSI_OFMT(PCM) | | ||
| 617 | SH_FSI_IFMT(PCM), | ||
| 618 | |||
| 619 | .portb_flags = SH_FSI_BRS_INV | | ||
| 620 | SH_FSI_BRM_INV | | ||
| 621 | SH_FSI_LRS_INV | | ||
| 622 | SH_FSI_OFMT(SPDIF), | ||
| 623 | |||
| 624 | .set_rate = fsi_set_rate, | ||
| 625 | }; | ||
| 626 | |||
| 627 | static struct resource fsi_resources[] = { | ||
| 628 | [0] = { | ||
| 629 | .name = "FSI", | ||
| 630 | .start = 0xFE3C0000, | ||
| 631 | .end = 0xFE3C0400 - 1, | ||
| 632 | .flags = IORESOURCE_MEM, | ||
| 633 | }, | ||
| 634 | [1] = { | ||
| 635 | .start = IRQ_FSI, | ||
| 636 | .flags = IORESOURCE_IRQ, | ||
| 637 | }, | ||
| 638 | }; | ||
| 639 | |||
| 640 | static struct platform_device fsi_device = { | ||
| 641 | .name = "sh_fsi2", | ||
| 642 | .id = -1, | ||
| 643 | .num_resources = ARRAY_SIZE(fsi_resources), | ||
| 644 | .resource = fsi_resources, | ||
| 645 | .dev = { | ||
| 646 | .platform_data = &fsi_info, | ||
| 647 | }, | ||
| 648 | }; | ||
| 649 | |||
| 650 | static struct platform_device fsi_ak4643_device = { | ||
| 651 | .name = "sh_fsi2_a_ak4643", | ||
| 652 | }; | ||
| 653 | |||
| 654 | /* | ||
| 655 | * The card detect pin of the top SD/MMC slot (CN7) is active low and is | ||
| 656 | * connected to GPIO A22 of SH7372 (GPIO_PORT41). | ||
| 657 | */ | ||
| 658 | static int slot_cn7_get_cd(struct platform_device *pdev) | ||
| 659 | { | ||
| 660 | if (gpio_is_valid(GPIO_PORT41)) | ||
| 661 | return !gpio_get_value(GPIO_PORT41); | ||
| 662 | else | ||
| 663 | return -ENXIO; | ||
| 664 | } | ||
| 665 | |||
| 666 | /* SDHI0 */ | ||
| 667 | static struct sh_mobile_sdhi_info sdhi0_info = { | ||
| 668 | .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, | ||
| 669 | .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, | ||
| 670 | .tmio_caps = MMC_CAP_SD_HIGHSPEED, | ||
| 671 | }; | ||
| 672 | |||
| 673 | static struct resource sdhi0_resources[] = { | ||
| 674 | [0] = { | ||
| 675 | .name = "SDHI0", | ||
| 676 | .start = 0xe6850000, | ||
| 677 | .end = 0xe68501ff, | ||
| 678 | .flags = IORESOURCE_MEM, | ||
| 679 | }, | ||
| 680 | [1] = { | ||
| 681 | .start = evt2irq(0x0e00) /* SDHI0 */, | ||
| 682 | .flags = IORESOURCE_IRQ, | ||
| 683 | }, | ||
| 684 | }; | ||
| 685 | |||
| 686 | static struct platform_device sdhi0_device = { | ||
| 687 | .name = "sh_mobile_sdhi", | ||
| 688 | .num_resources = ARRAY_SIZE(sdhi0_resources), | ||
| 689 | .resource = sdhi0_resources, | ||
| 690 | .id = 0, | ||
| 691 | .dev = { | ||
| 692 | .platform_data = &sdhi0_info, | ||
| 693 | }, | ||
| 694 | }; | ||
| 695 | |||
| 696 | #if !defined(CONFIG_MMC_SH_MMCIF) | ||
| 697 | /* SDHI1 */ | ||
| 698 | static struct sh_mobile_sdhi_info sdhi1_info = { | ||
| 699 | .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX, | ||
| 700 | .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX, | ||
| 701 | .tmio_ocr_mask = MMC_VDD_165_195, | ||
| 702 | .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE, | ||
| 703 | .tmio_caps = MMC_CAP_SD_HIGHSPEED | | ||
| 704 | MMC_CAP_NEEDS_POLL, | ||
| 705 | .get_cd = slot_cn7_get_cd, | ||
| 706 | }; | ||
| 707 | |||
| 708 | static struct resource sdhi1_resources[] = { | ||
| 709 | [0] = { | ||
| 710 | .name = "SDHI1", | ||
| 711 | .start = 0xe6860000, | ||
| 712 | .end = 0xe68601ff, | ||
| 713 | .flags = IORESOURCE_MEM, | ||
| 714 | }, | ||
| 715 | [1] = { | ||
| 716 | .start = evt2irq(0x0e80), | ||
| 717 | .flags = IORESOURCE_IRQ, | ||
| 718 | }, | ||
| 719 | }; | ||
| 720 | |||
| 721 | static struct platform_device sdhi1_device = { | ||
| 722 | .name = "sh_mobile_sdhi", | ||
| 723 | .num_resources = ARRAY_SIZE(sdhi1_resources), | ||
| 724 | .resource = sdhi1_resources, | ||
| 725 | .id = 1, | ||
| 726 | .dev = { | ||
| 727 | .platform_data = &sdhi1_info, | ||
| 728 | }, | ||
| 729 | }; | ||
| 730 | #endif | ||
| 731 | |||
| 732 | /* SDHI2 */ | ||
| 733 | static struct sh_mobile_sdhi_info sdhi2_info = { | ||
| 734 | .dma_slave_tx = SHDMA_SLAVE_SDHI2_TX, | ||
| 735 | .dma_slave_rx = SHDMA_SLAVE_SDHI2_RX, | ||
| 736 | .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE, | ||
| 737 | .tmio_caps = MMC_CAP_SD_HIGHSPEED | | ||
| 738 | MMC_CAP_NEEDS_POLL, | ||
| 739 | }; | ||
| 740 | |||
| 741 | static struct resource sdhi2_resources[] = { | ||
| 742 | [0] = { | ||
| 743 | .name = "SDHI2", | ||
| 744 | .start = 0xe6870000, | ||
| 745 | .end = 0xe68701ff, | ||
| 746 | .flags = IORESOURCE_MEM, | ||
| 747 | }, | ||
| 748 | [1] = { | ||
| 749 | .start = evt2irq(0x1200), | ||
| 750 | .flags = IORESOURCE_IRQ, | ||
| 751 | }, | ||
| 752 | }; | ||
| 753 | |||
| 754 | static struct platform_device sdhi2_device = { | ||
| 755 | .name = "sh_mobile_sdhi", | ||
| 756 | .num_resources = ARRAY_SIZE(sdhi2_resources), | ||
| 757 | .resource = sdhi2_resources, | ||
| 758 | .id = 2, | ||
| 759 | .dev = { | ||
| 760 | .platform_data = &sdhi2_info, | ||
| 761 | }, | ||
| 762 | }; | ||
| 763 | |||
| 764 | /* SH_MMCIF */ | ||
| 765 | static struct resource sh_mmcif_resources[] = { | ||
| 766 | [0] = { | ||
| 767 | .name = "MMCIF", | ||
| 768 | .start = 0xE6BD0000, | ||
| 769 | .end = 0xE6BD00FF, | ||
| 770 | .flags = IORESOURCE_MEM, | ||
| 771 | }, | ||
| 772 | [1] = { | ||
| 773 | /* MMC ERR */ | ||
| 774 | .start = evt2irq(0x1ac0), | ||
| 775 | .flags = IORESOURCE_IRQ, | ||
| 776 | }, | ||
| 777 | [2] = { | ||
| 778 | /* MMC NOR */ | ||
| 779 | .start = evt2irq(0x1ae0), | ||
| 780 | .flags = IORESOURCE_IRQ, | ||
| 781 | }, | ||
| 782 | }; | ||
| 783 | |||
| 784 | static struct sh_mmcif_plat_data sh_mmcif_plat = { | ||
| 785 | .sup_pclk = 0, | ||
| 786 | .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, | ||
| 787 | .caps = MMC_CAP_4_BIT_DATA | | ||
| 788 | MMC_CAP_8_BIT_DATA | | ||
| 789 | MMC_CAP_NEEDS_POLL, | ||
| 790 | .get_cd = slot_cn7_get_cd, | ||
| 791 | }; | ||
| 792 | |||
| 793 | static struct platform_device sh_mmcif_device = { | ||
| 794 | .name = "sh_mmcif", | ||
| 795 | .id = 0, | ||
| 796 | .dev = { | ||
| 797 | .dma_mask = NULL, | ||
| 798 | .coherent_dma_mask = 0xffffffff, | ||
| 799 | .platform_data = &sh_mmcif_plat, | ||
| 800 | }, | ||
| 801 | .num_resources = ARRAY_SIZE(sh_mmcif_resources), | ||
| 802 | .resource = sh_mmcif_resources, | ||
| 803 | }; | ||
| 804 | |||
| 805 | |||
| 806 | static int mackerel_camera_add(struct soc_camera_link *icl, struct device *dev); | ||
| 807 | static void mackerel_camera_del(struct soc_camera_link *icl); | ||
| 808 | |||
| 809 | static int camera_set_capture(struct soc_camera_platform_info *info, | ||
| 810 | int enable) | ||
| 811 | { | ||
| 812 | return 0; /* camera sensor always enabled */ | ||
| 813 | } | ||
| 814 | |||
| 815 | static struct soc_camera_platform_info camera_info = { | ||
| 816 | .format_name = "UYVY", | ||
| 817 | .format_depth = 16, | ||
| 818 | .format = { | ||
| 819 | .code = V4L2_MBUS_FMT_UYVY8_2X8, | ||
| 820 | .colorspace = V4L2_COLORSPACE_SMPTE170M, | ||
| 821 | .field = V4L2_FIELD_NONE, | ||
| 822 | .width = 640, | ||
| 823 | .height = 480, | ||
| 824 | }, | ||
| 825 | .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH | | ||
| 826 | SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8 | | ||
| 827 | SOCAM_DATA_ACTIVE_HIGH, | ||
| 828 | .set_capture = camera_set_capture, | ||
| 829 | }; | ||
| 830 | |||
| 831 | static struct soc_camera_link camera_link = { | ||
| 832 | .bus_id = 0, | ||
| 833 | .add_device = mackerel_camera_add, | ||
| 834 | .del_device = mackerel_camera_del, | ||
| 835 | .module_name = "soc_camera_platform", | ||
| 836 | .priv = &camera_info, | ||
| 837 | }; | ||
| 838 | |||
| 839 | static void dummy_release(struct device *dev) | ||
| 840 | { | ||
| 841 | } | ||
| 842 | |||
| 843 | static struct platform_device camera_device = { | ||
| 844 | .name = "soc_camera_platform", | ||
| 845 | .dev = { | ||
| 846 | .platform_data = &camera_info, | ||
| 847 | .release = dummy_release, | ||
| 848 | }, | ||
| 849 | }; | ||
| 850 | |||
| 851 | static int mackerel_camera_add(struct soc_camera_link *icl, | ||
| 852 | struct device *dev) | ||
| 853 | { | ||
| 854 | if (icl != &camera_link) | ||
| 855 | return -ENODEV; | ||
| 856 | |||
| 857 | camera_info.dev = dev; | ||
| 858 | |||
| 859 | return platform_device_register(&camera_device); | ||
| 860 | } | ||
| 861 | |||
| 862 | static void mackerel_camera_del(struct soc_camera_link *icl) | ||
| 863 | { | ||
| 864 | if (icl != &camera_link) | ||
| 865 | return; | ||
| 866 | |||
| 867 | platform_device_unregister(&camera_device); | ||
| 868 | memset(&camera_device.dev.kobj, 0, | ||
| 869 | sizeof(camera_device.dev.kobj)); | ||
| 870 | } | ||
| 871 | |||
| 872 | static struct sh_mobile_ceu_info sh_mobile_ceu_info = { | ||
| 873 | .flags = SH_CEU_FLAG_USE_8BIT_BUS, | ||
| 874 | }; | ||
| 875 | |||
| 876 | static struct resource ceu_resources[] = { | ||
| 877 | [0] = { | ||
| 878 | .name = "CEU", | ||
| 879 | .start = 0xfe910000, | ||
| 880 | .end = 0xfe91009f, | ||
| 881 | .flags = IORESOURCE_MEM, | ||
| 882 | }, | ||
| 883 | [1] = { | ||
| 884 | .start = intcs_evt2irq(0x880), | ||
| 885 | .flags = IORESOURCE_IRQ, | ||
| 886 | }, | ||
| 887 | [2] = { | ||
| 888 | /* place holder for contiguous memory */ | ||
| 889 | }, | ||
| 890 | }; | ||
| 891 | |||
| 892 | static struct platform_device ceu_device = { | ||
| 893 | .name = "sh_mobile_ceu", | ||
| 894 | .id = 0, /* "ceu0" clock */ | ||
| 895 | .num_resources = ARRAY_SIZE(ceu_resources), | ||
| 896 | .resource = ceu_resources, | ||
| 897 | .dev = { | ||
| 898 | .platform_data = &sh_mobile_ceu_info, | ||
| 899 | }, | ||
| 900 | }; | ||
| 901 | |||
| 902 | static struct platform_device mackerel_camera = { | ||
| 903 | .name = "soc-camera-pdrv", | ||
| 904 | .id = 0, | ||
| 905 | .dev = { | ||
| 906 | .platform_data = &camera_link, | ||
| 907 | }, | ||
| 908 | }; | ||
| 909 | |||
| 910 | static struct platform_device *mackerel_devices[] __initdata = { | ||
| 911 | &nor_flash_device, | ||
| 912 | &smc911x_device, | ||
| 913 | &lcdc_device, | ||
| 914 | &usb1_host_device, | ||
| 915 | &leds_device, | ||
| 916 | &fsi_device, | ||
| 917 | &fsi_ak4643_device, | ||
| 918 | &sdhi0_device, | ||
| 919 | #if !defined(CONFIG_MMC_SH_MMCIF) | ||
| 920 | &sdhi1_device, | ||
| 921 | #endif | ||
| 922 | &sdhi2_device, | ||
| 923 | &sh_mmcif_device, | ||
| 924 | &ceu_device, | ||
| 925 | &mackerel_camera, | ||
| 926 | &hdmi_lcdc_device, | ||
| 927 | &hdmi_device, | ||
| 928 | }; | ||
| 929 | |||
| 930 | /* Keypad Initialization */ | ||
| 931 | #define KEYPAD_BUTTON(ev_type, ev_code, act_low) \ | ||
| 932 | { \ | ||
| 933 | .type = ev_type, \ | ||
| 934 | .code = ev_code, \ | ||
| 935 | .active_low = act_low, \ | ||
| 936 | } | ||
| 937 | |||
| 938 | #define KEYPAD_BUTTON_LOW(event_code) KEYPAD_BUTTON(EV_KEY, event_code, 1) | ||
| 939 | |||
| 940 | static struct tca6416_button mackerel_gpio_keys[] = { | ||
| 941 | KEYPAD_BUTTON_LOW(KEY_HOME), | ||
| 942 | KEYPAD_BUTTON_LOW(KEY_MENU), | ||
| 943 | KEYPAD_BUTTON_LOW(KEY_BACK), | ||
| 944 | KEYPAD_BUTTON_LOW(KEY_POWER), | ||
| 945 | }; | ||
| 946 | |||
| 947 | static struct tca6416_keys_platform_data mackerel_tca6416_keys_info = { | ||
| 948 | .buttons = mackerel_gpio_keys, | ||
| 949 | .nbuttons = ARRAY_SIZE(mackerel_gpio_keys), | ||
| 950 | .rep = 1, | ||
| 951 | .use_polling = 0, | ||
| 952 | .pinmask = 0x000F, | ||
| 953 | }; | ||
| 954 | |||
| 955 | /* I2C */ | ||
| 956 | #define IRQ9 evt2irq(0x0320) | ||
| 957 | |||
| 958 | static struct i2c_board_info i2c0_devices[] = { | ||
| 959 | { | ||
| 960 | I2C_BOARD_INFO("ak4643", 0x13), | ||
| 961 | }, | ||
| 962 | /* Keypad */ | ||
| 963 | { | ||
| 964 | I2C_BOARD_INFO("tca6408-keys", 0x20), | ||
| 965 | .platform_data = &mackerel_tca6416_keys_info, | ||
| 966 | .irq = IRQ9, | ||
| 967 | }, | ||
| 968 | }; | ||
| 969 | |||
| 970 | #define IRQ21 evt2irq(0x32a0) | ||
| 971 | |||
| 972 | static struct i2c_board_info i2c1_devices[] = { | ||
| 973 | /* Accelerometer */ | ||
| 974 | { | ||
| 975 | I2C_BOARD_INFO("adxl34x", 0x53), | ||
| 976 | .irq = IRQ21, | ||
| 977 | }, | ||
| 978 | }; | ||
| 979 | |||
| 980 | static struct map_desc mackerel_io_desc[] __initdata = { | ||
| 981 | /* create a 1:1 entity map for 0xe6xxxxxx | ||
| 982 | * used by CPGA, INTC and PFC. | ||
| 983 | */ | ||
| 984 | { | ||
| 985 | .virtual = 0xe6000000, | ||
| 986 | .pfn = __phys_to_pfn(0xe6000000), | ||
| 987 | .length = 256 << 20, | ||
| 988 | .type = MT_DEVICE_NONSHARED | ||
| 989 | }, | ||
| 990 | }; | ||
| 991 | |||
| 992 | static void __init mackerel_map_io(void) | ||
| 993 | { | ||
| 994 | iotable_init(mackerel_io_desc, ARRAY_SIZE(mackerel_io_desc)); | ||
| 995 | |||
| 996 | /* setup early devices and console here as well */ | ||
| 997 | sh7372_add_early_devices(); | ||
| 998 | shmobile_setup_console(); | ||
| 999 | } | ||
| 1000 | |||
| 1001 | #define GPIO_PORT9CR 0xE6051009 | ||
| 1002 | #define GPIO_PORT10CR 0xE605100A | ||
| 1003 | #define SRCR4 0xe61580bc | ||
| 1004 | #define USCCR1 0xE6058144 | ||
| 1005 | static void __init mackerel_init(void) | ||
| 1006 | { | ||
| 1007 | u32 srcr4; | ||
| 1008 | struct clk *clk; | ||
| 1009 | |||
| 1010 | sh7372_pinmux_init(); | ||
| 1011 | |||
| 1012 | /* enable SCIFA0 */ | ||
| 1013 | gpio_request(GPIO_FN_SCIFA0_TXD, NULL); | ||
| 1014 | gpio_request(GPIO_FN_SCIFA0_RXD, NULL); | ||
| 1015 | |||
| 1016 | /* enable SMSC911X */ | ||
| 1017 | gpio_request(GPIO_FN_CS5A, NULL); | ||
| 1018 | gpio_request(GPIO_FN_IRQ6_39, NULL); | ||
| 1019 | |||
| 1020 | /* LCDC */ | ||
| 1021 | gpio_request(GPIO_FN_LCDD23, NULL); | ||
| 1022 | gpio_request(GPIO_FN_LCDD22, NULL); | ||
| 1023 | gpio_request(GPIO_FN_LCDD21, NULL); | ||
| 1024 | gpio_request(GPIO_FN_LCDD20, NULL); | ||
| 1025 | gpio_request(GPIO_FN_LCDD19, NULL); | ||
| 1026 | gpio_request(GPIO_FN_LCDD18, NULL); | ||
| 1027 | gpio_request(GPIO_FN_LCDD17, NULL); | ||
| 1028 | gpio_request(GPIO_FN_LCDD16, NULL); | ||
| 1029 | gpio_request(GPIO_FN_LCDD15, NULL); | ||
| 1030 | gpio_request(GPIO_FN_LCDD14, NULL); | ||
| 1031 | gpio_request(GPIO_FN_LCDD13, NULL); | ||
| 1032 | gpio_request(GPIO_FN_LCDD12, NULL); | ||
| 1033 | gpio_request(GPIO_FN_LCDD11, NULL); | ||
| 1034 | gpio_request(GPIO_FN_LCDD10, NULL); | ||
| 1035 | gpio_request(GPIO_FN_LCDD9, NULL); | ||
| 1036 | gpio_request(GPIO_FN_LCDD8, NULL); | ||
| 1037 | gpio_request(GPIO_FN_LCDD7, NULL); | ||
| 1038 | gpio_request(GPIO_FN_LCDD6, NULL); | ||
| 1039 | gpio_request(GPIO_FN_LCDD5, NULL); | ||
| 1040 | gpio_request(GPIO_FN_LCDD4, NULL); | ||
| 1041 | gpio_request(GPIO_FN_LCDD3, NULL); | ||
| 1042 | gpio_request(GPIO_FN_LCDD2, NULL); | ||
| 1043 | gpio_request(GPIO_FN_LCDD1, NULL); | ||
| 1044 | gpio_request(GPIO_FN_LCDD0, NULL); | ||
| 1045 | gpio_request(GPIO_FN_LCDDISP, NULL); | ||
| 1046 | gpio_request(GPIO_FN_LCDDCK, NULL); | ||
| 1047 | |||
| 1048 | gpio_request(GPIO_PORT31, NULL); /* backlight */ | ||
| 1049 | gpio_direction_output(GPIO_PORT31, 1); | ||
| 1050 | |||
| 1051 | gpio_request(GPIO_PORT151, NULL); /* LCDDON */ | ||
| 1052 | gpio_direction_output(GPIO_PORT151, 1); | ||
| 1053 | |||
| 1054 | /* USB enable */ | ||
| 1055 | gpio_request(GPIO_FN_VBUS0_1, NULL); | ||
| 1056 | gpio_request(GPIO_FN_IDIN_1_18, NULL); | ||
| 1057 | gpio_request(GPIO_FN_PWEN_1_115, NULL); | ||
| 1058 | gpio_request(GPIO_FN_OVCN_1_114, NULL); | ||
| 1059 | gpio_request(GPIO_FN_EXTLP_1, NULL); | ||
| 1060 | gpio_request(GPIO_FN_OVCN2_1, NULL); | ||
| 1061 | |||
| 1062 | /* setup USB phy */ | ||
| 1063 | __raw_writew(0x8a0a, 0xE6058130); /* USBCR4 */ | ||
| 1064 | |||
| 1065 | /* enable FSI2 port A (ak4643) */ | ||
| 1066 | gpio_request(GPIO_FN_FSIAIBT, NULL); | ||
| 1067 | gpio_request(GPIO_FN_FSIAILR, NULL); | ||
| 1068 | gpio_request(GPIO_FN_FSIAISLD, NULL); | ||
| 1069 | gpio_request(GPIO_FN_FSIAOSLD, NULL); | ||
| 1070 | gpio_request(GPIO_PORT161, NULL); | ||
| 1071 | gpio_direction_output(GPIO_PORT161, 0); /* slave */ | ||
| 1072 | |||
| 1073 | gpio_request(GPIO_PORT9, NULL); | ||
| 1074 | gpio_request(GPIO_PORT10, NULL); | ||
| 1075 | gpio_no_direction(GPIO_PORT9CR); /* FSIAOBT needs no direction */ | ||
| 1076 | gpio_no_direction(GPIO_PORT10CR); /* FSIAOLR needs no direction */ | ||
| 1077 | |||
| 1078 | intc_set_priority(IRQ_FSI, 3); /* irq priority FSI(3) > SMSC911X(2) */ | ||
| 1079 | |||
| 1080 | /* setup FSI2 port B (HDMI) */ | ||
| 1081 | gpio_request(GPIO_FN_FSIBCK, NULL); | ||
| 1082 | __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */ | ||
| 1083 | |||
| 1084 | /* set SPU2 clock to 119.6 MHz */ | ||
| 1085 | clk = clk_get(NULL, "spu_clk"); | ||
| 1086 | if (!IS_ERR(clk)) { | ||
| 1087 | clk_set_rate(clk, clk_round_rate(clk, 119600000)); | ||
| 1088 | clk_put(clk); | ||
| 1089 | } | ||
| 1090 | |||
| 1091 | /* enable Keypad */ | ||
| 1092 | gpio_request(GPIO_FN_IRQ9_42, NULL); | ||
| 1093 | set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH); | ||
| 1094 | |||
| 1095 | /* enable Accelerometer */ | ||
| 1096 | gpio_request(GPIO_FN_IRQ21, NULL); | ||
| 1097 | set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH); | ||
| 1098 | |||
| 1099 | /* enable SDHI0 */ | ||
| 1100 | gpio_request(GPIO_FN_SDHICD0, NULL); | ||
| 1101 | gpio_request(GPIO_FN_SDHIWP0, NULL); | ||
| 1102 | gpio_request(GPIO_FN_SDHICMD0, NULL); | ||
| 1103 | gpio_request(GPIO_FN_SDHICLK0, NULL); | ||
| 1104 | gpio_request(GPIO_FN_SDHID0_3, NULL); | ||
| 1105 | gpio_request(GPIO_FN_SDHID0_2, NULL); | ||
| 1106 | gpio_request(GPIO_FN_SDHID0_1, NULL); | ||
| 1107 | gpio_request(GPIO_FN_SDHID0_0, NULL); | ||
| 1108 | |||
| 1109 | #if !defined(CONFIG_MMC_SH_MMCIF) | ||
| 1110 | /* enable SDHI1 */ | ||
| 1111 | gpio_request(GPIO_FN_SDHICMD1, NULL); | ||
| 1112 | gpio_request(GPIO_FN_SDHICLK1, NULL); | ||
| 1113 | gpio_request(GPIO_FN_SDHID1_3, NULL); | ||
| 1114 | gpio_request(GPIO_FN_SDHID1_2, NULL); | ||
| 1115 | gpio_request(GPIO_FN_SDHID1_1, NULL); | ||
| 1116 | gpio_request(GPIO_FN_SDHID1_0, NULL); | ||
| 1117 | #endif | ||
| 1118 | /* card detect pin for MMC slot (CN7) */ | ||
| 1119 | gpio_request(GPIO_PORT41, NULL); | ||
| 1120 | gpio_direction_input(GPIO_PORT41); | ||
| 1121 | |||
| 1122 | /* enable SDHI2 */ | ||
| 1123 | gpio_request(GPIO_FN_SDHICMD2, NULL); | ||
| 1124 | gpio_request(GPIO_FN_SDHICLK2, NULL); | ||
| 1125 | gpio_request(GPIO_FN_SDHID2_3, NULL); | ||
| 1126 | gpio_request(GPIO_FN_SDHID2_2, NULL); | ||
| 1127 | gpio_request(GPIO_FN_SDHID2_1, NULL); | ||
| 1128 | gpio_request(GPIO_FN_SDHID2_0, NULL); | ||
| 1129 | |||
| 1130 | /* MMCIF */ | ||
| 1131 | gpio_request(GPIO_FN_MMCD0_0, NULL); | ||
| 1132 | gpio_request(GPIO_FN_MMCD0_1, NULL); | ||
| 1133 | gpio_request(GPIO_FN_MMCD0_2, NULL); | ||
| 1134 | gpio_request(GPIO_FN_MMCD0_3, NULL); | ||
| 1135 | gpio_request(GPIO_FN_MMCD0_4, NULL); | ||
| 1136 | gpio_request(GPIO_FN_MMCD0_5, NULL); | ||
| 1137 | gpio_request(GPIO_FN_MMCD0_6, NULL); | ||
| 1138 | gpio_request(GPIO_FN_MMCD0_7, NULL); | ||
| 1139 | gpio_request(GPIO_FN_MMCCMD0, NULL); | ||
| 1140 | gpio_request(GPIO_FN_MMCCLK0, NULL); | ||
| 1141 | |||
| 1142 | /* enable GPS module (GT-720F) */ | ||
| 1143 | gpio_request(GPIO_FN_SCIFA2_TXD1, NULL); | ||
| 1144 | gpio_request(GPIO_FN_SCIFA2_RXD1, NULL); | ||
| 1145 | |||
| 1146 | /* CEU */ | ||
| 1147 | gpio_request(GPIO_FN_VIO_CLK, NULL); | ||
| 1148 | gpio_request(GPIO_FN_VIO_VD, NULL); | ||
| 1149 | gpio_request(GPIO_FN_VIO_HD, NULL); | ||
| 1150 | gpio_request(GPIO_FN_VIO_FIELD, NULL); | ||
| 1151 | gpio_request(GPIO_FN_VIO_CKO, NULL); | ||
| 1152 | gpio_request(GPIO_FN_VIO_D7, NULL); | ||
| 1153 | gpio_request(GPIO_FN_VIO_D6, NULL); | ||
| 1154 | gpio_request(GPIO_FN_VIO_D5, NULL); | ||
| 1155 | gpio_request(GPIO_FN_VIO_D4, NULL); | ||
| 1156 | gpio_request(GPIO_FN_VIO_D3, NULL); | ||
| 1157 | gpio_request(GPIO_FN_VIO_D2, NULL); | ||
| 1158 | gpio_request(GPIO_FN_VIO_D1, NULL); | ||
| 1159 | gpio_request(GPIO_FN_VIO_D0, NULL); | ||
| 1160 | |||
| 1161 | /* HDMI */ | ||
| 1162 | gpio_request(GPIO_FN_HDMI_HPD, NULL); | ||
| 1163 | gpio_request(GPIO_FN_HDMI_CEC, NULL); | ||
| 1164 | |||
| 1165 | /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */ | ||
| 1166 | srcr4 = __raw_readl(SRCR4); | ||
| 1167 | __raw_writel(srcr4 | (1 << 13), SRCR4); | ||
| 1168 | udelay(50); | ||
| 1169 | __raw_writel(srcr4 & ~(1 << 13), SRCR4); | ||
| 1170 | |||
| 1171 | i2c_register_board_info(0, i2c0_devices, | ||
| 1172 | ARRAY_SIZE(i2c0_devices)); | ||
| 1173 | i2c_register_board_info(1, i2c1_devices, | ||
| 1174 | ARRAY_SIZE(i2c1_devices)); | ||
| 1175 | |||
| 1176 | sh7372_add_standard_devices(); | ||
| 1177 | |||
| 1178 | platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices)); | ||
| 1179 | } | ||
| 1180 | |||
| 1181 | static void __init mackerel_timer_init(void) | ||
| 1182 | { | ||
| 1183 | sh7372_clock_init(); | ||
| 1184 | shmobile_timer.init(); | ||
| 1185 | |||
| 1186 | /* External clock source */ | ||
| 1187 | clk_set_rate(&sh7372_dv_clki_clk, 27000000); | ||
| 1188 | } | ||
| 1189 | |||
| 1190 | static struct sys_timer mackerel_timer = { | ||
| 1191 | .init = mackerel_timer_init, | ||
| 1192 | }; | ||
| 1193 | |||
| 1194 | MACHINE_START(MACKEREL, "mackerel") | ||
| 1195 | .map_io = mackerel_map_io, | ||
| 1196 | .init_irq = sh7372_init_irq, | ||
| 1197 | .handle_irq = shmobile_handle_irq_intc, | ||
| 1198 | .init_machine = mackerel_init, | ||
| 1199 | .timer = &mackerel_timer, | ||
| 1200 | MACHINE_END | ||
diff --git a/arch/arm/mach-shmobile/clock-sh7367.c b/arch/arm/mach-shmobile/clock-sh7367.c index 9f78729098f2..6b186aefcbd6 100644 --- a/arch/arm/mach-shmobile/clock-sh7367.c +++ b/arch/arm/mach-shmobile/clock-sh7367.c | |||
| @@ -20,8 +20,8 @@ | |||
| 20 | #include <linux/kernel.h> | 20 | #include <linux/kernel.h> |
| 21 | #include <linux/io.h> | 21 | #include <linux/io.h> |
| 22 | #include <linux/sh_clk.h> | 22 | #include <linux/sh_clk.h> |
| 23 | #include <linux/clkdev.h> | ||
| 23 | #include <mach/common.h> | 24 | #include <mach/common.h> |
| 24 | #include <asm/clkdev.h> | ||
| 25 | 25 | ||
| 26 | /* SH7367 registers */ | 26 | /* SH7367 registers */ |
| 27 | #define RTFRQCR 0xe6150000 | 27 | #define RTFRQCR 0xe6150000 |
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c index 3aa026069435..9aa8d68d1a9c 100644 --- a/arch/arm/mach-shmobile/clock-sh7372.c +++ b/arch/arm/mach-shmobile/clock-sh7372.c | |||
| @@ -20,8 +20,8 @@ | |||
| 20 | #include <linux/kernel.h> | 20 | #include <linux/kernel.h> |
| 21 | #include <linux/io.h> | 21 | #include <linux/io.h> |
| 22 | #include <linux/sh_clk.h> | 22 | #include <linux/sh_clk.h> |
| 23 | #include <linux/clkdev.h> | ||
| 23 | #include <mach/common.h> | 24 | #include <mach/common.h> |
| 24 | #include <asm/clkdev.h> | ||
| 25 | 25 | ||
| 26 | /* SH7372 registers */ | 26 | /* SH7372 registers */ |
| 27 | #define FRQCRA 0xe6150000 | 27 | #define FRQCRA 0xe6150000 |
| @@ -507,7 +507,7 @@ enum { MSTP001, | |||
| 507 | MSTP223, | 507 | MSTP223, |
| 508 | MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, | 508 | MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, |
| 509 | MSTP329, MSTP328, MSTP323, MSTP322, MSTP314, MSTP313, MSTP312, | 509 | MSTP329, MSTP328, MSTP323, MSTP322, MSTP314, MSTP313, MSTP312, |
| 510 | MSTP415, MSTP413, MSTP411, MSTP410, MSTP406, MSTP403, | 510 | MSTP423, MSTP415, MSTP413, MSTP411, MSTP410, MSTP406, MSTP403, |
| 511 | MSTP_NR }; | 511 | MSTP_NR }; |
| 512 | 512 | ||
| 513 | #define MSTP(_parent, _reg, _bit, _flags) \ | 513 | #define MSTP(_parent, _reg, _bit, _flags) \ |
| @@ -543,6 +543,7 @@ static struct clk mstp_clks[MSTP_NR] = { | |||
| 543 | [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */ | 543 | [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */ |
| 544 | [MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */ | 544 | [MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */ |
| 545 | [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */ | 545 | [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */ |
| 546 | [MSTP423] = MSTP(&div4_clks[DIV4_B], SMSTPCR4, 23, 0), /* DSITX1 */ | ||
| 546 | [MSTP415] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */ | 547 | [MSTP415] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */ |
| 547 | [MSTP413] = MSTP(&pllc1_div2_clk, SMSTPCR4, 13, 0), /* HDMI */ | 548 | [MSTP413] = MSTP(&pllc1_div2_clk, SMSTPCR4, 13, 0), /* HDMI */ |
| 548 | [MSTP411] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 11, 0), /* IIC3 */ | 549 | [MSTP411] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 11, 0), /* IIC3 */ |
| @@ -596,9 +597,10 @@ static struct clk_lookup lookups[] = { | |||
| 596 | CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]), | 597 | CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]), |
| 597 | CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]), | 598 | CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]), |
| 598 | CLKDEV_CON_ID("hdmi_clk", &div6_reparent_clks[DIV6_HDMI]), | 599 | CLKDEV_CON_ID("hdmi_clk", &div6_reparent_clks[DIV6_HDMI]), |
| 599 | CLKDEV_CON_ID("dsit_clk", &div6_clks[DIV6_DSIT]), | 600 | CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]), |
| 600 | CLKDEV_CON_ID("dsi0p_clk", &div6_clks[DIV6_DSI0P]), | 601 | CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]), |
| 601 | CLKDEV_CON_ID("dsi1p_clk", &div6_clks[DIV6_DSI1P]), | 602 | CLKDEV_ICK_ID("dsi0p_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]), |
| 603 | CLKDEV_ICK_ID("dsi1p_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]), | ||
| 602 | 604 | ||
| 603 | /* MSTP32 clocks */ | 605 | /* MSTP32 clocks */ |
| 604 | CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */ | 606 | CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */ |
| @@ -610,7 +612,7 @@ static struct clk_lookup lookups[] = { | |||
| 610 | CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2 */ | 612 | CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2 */ |
| 611 | CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */ | 613 | CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */ |
| 612 | CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */ | 614 | CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */ |
| 613 | CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */ | 615 | CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX0 */ |
| 614 | CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */ | 616 | CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */ |
| 615 | CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */ | 617 | CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */ |
| 616 | CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */ | 618 | CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */ |
| @@ -633,6 +635,7 @@ static struct clk_lookup lookups[] = { | |||
| 633 | CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */ | 635 | CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */ |
| 634 | CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */ | 636 | CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */ |
| 635 | CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMC */ | 637 | CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMC */ |
| 638 | CLKDEV_DEV_ID("sh-mipi-dsi.1", &mstp_clks[MSTP423]), /* DSITX1 */ | ||
| 636 | CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), /* SDHI2 */ | 639 | CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), /* SDHI2 */ |
| 637 | CLKDEV_DEV_ID("sh-mobile-hdmi", &mstp_clks[MSTP413]), /* HDMI */ | 640 | CLKDEV_DEV_ID("sh-mobile-hdmi", &mstp_clks[MSTP413]), /* HDMI */ |
| 638 | CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* IIC3 */ | 641 | CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* IIC3 */ |
diff --git a/arch/arm/mach-shmobile/clock-sh7377.c b/arch/arm/mach-shmobile/clock-sh7377.c index f91395aeb9ab..95942466e63f 100644 --- a/arch/arm/mach-shmobile/clock-sh7377.c +++ b/arch/arm/mach-shmobile/clock-sh7377.c | |||
| @@ -20,8 +20,8 @@ | |||
| 20 | #include <linux/kernel.h> | 20 | #include <linux/kernel.h> |
| 21 | #include <linux/io.h> | 21 | #include <linux/io.h> |
| 22 | #include <linux/sh_clk.h> | 22 | #include <linux/sh_clk.h> |
| 23 | #include <linux/clkdev.h> | ||
| 23 | #include <mach/common.h> | 24 | #include <mach/common.h> |
| 24 | #include <asm/clkdev.h> | ||
| 25 | 25 | ||
| 26 | /* SH7377 registers */ | 26 | /* SH7377 registers */ |
| 27 | #define RTFRQCR 0xe6150000 | 27 | #define RTFRQCR 0xe6150000 |
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c new file mode 100644 index 000000000000..720a71433be6 --- /dev/null +++ b/arch/arm/mach-shmobile/clock-sh73a0.c | |||
| @@ -0,0 +1,356 @@ | |||
| 1 | /* | ||
| 2 | * sh73a0 clock framework support | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Magnus Damm | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 18 | */ | ||
| 19 | #include <linux/init.h> | ||
| 20 | #include <linux/kernel.h> | ||
| 21 | #include <linux/io.h> | ||
| 22 | #include <linux/sh_clk.h> | ||
| 23 | #include <linux/clkdev.h> | ||
| 24 | #include <mach/common.h> | ||
| 25 | |||
| 26 | #define FRQCRA 0xe6150000 | ||
| 27 | #define FRQCRB 0xe6150004 | ||
| 28 | #define FRQCRD 0xe61500e4 | ||
| 29 | #define VCLKCR1 0xe6150008 | ||
| 30 | #define VCLKCR2 0xe615000C | ||
| 31 | #define VCLKCR3 0xe615001C | ||
| 32 | #define ZBCKCR 0xe6150010 | ||
| 33 | #define FLCKCR 0xe6150014 | ||
| 34 | #define SD0CKCR 0xe6150074 | ||
| 35 | #define SD1CKCR 0xe6150078 | ||
| 36 | #define SD2CKCR 0xe615007C | ||
| 37 | #define FSIACKCR 0xe6150018 | ||
| 38 | #define FSIBCKCR 0xe6150090 | ||
| 39 | #define SUBCKCR 0xe6150080 | ||
| 40 | #define SPUACKCR 0xe6150084 | ||
| 41 | #define SPUVCKCR 0xe6150094 | ||
| 42 | #define MSUCKCR 0xe6150088 | ||
| 43 | #define HSICKCR 0xe615008C | ||
| 44 | #define MFCK1CR 0xe6150098 | ||
| 45 | #define MFCK2CR 0xe615009C | ||
| 46 | #define DSITCKCR 0xe6150060 | ||
| 47 | #define DSI0PCKCR 0xe6150064 | ||
| 48 | #define DSI1PCKCR 0xe6150068 | ||
| 49 | #define DSI0PHYCR 0xe615006C | ||
| 50 | #define DSI1PHYCR 0xe6150070 | ||
| 51 | #define PLLECR 0xe61500d0 | ||
| 52 | #define PLL0CR 0xe61500d8 | ||
| 53 | #define PLL1CR 0xe6150028 | ||
| 54 | #define PLL2CR 0xe615002c | ||
| 55 | #define PLL3CR 0xe61500dc | ||
| 56 | #define SMSTPCR0 0xe6150130 | ||
| 57 | #define SMSTPCR1 0xe6150134 | ||
| 58 | #define SMSTPCR2 0xe6150138 | ||
| 59 | #define SMSTPCR3 0xe615013c | ||
| 60 | #define SMSTPCR4 0xe6150140 | ||
| 61 | #define SMSTPCR5 0xe6150144 | ||
| 62 | #define CKSCR 0xe61500c0 | ||
| 63 | |||
| 64 | /* Fixed 32 KHz root clock from EXTALR pin */ | ||
| 65 | static struct clk r_clk = { | ||
| 66 | .rate = 32768, | ||
| 67 | }; | ||
| 68 | |||
| 69 | /* | ||
| 70 | * 26MHz default rate for the EXTAL1 root input clock. | ||
| 71 | * If needed, reset this with clk_set_rate() from the platform code. | ||
| 72 | */ | ||
| 73 | struct clk sh73a0_extal1_clk = { | ||
| 74 | .rate = 26000000, | ||
| 75 | }; | ||
| 76 | |||
| 77 | /* | ||
| 78 | * 48MHz default rate for the EXTAL2 root input clock. | ||
| 79 | * If needed, reset this with clk_set_rate() from the platform code. | ||
| 80 | */ | ||
| 81 | struct clk sh73a0_extal2_clk = { | ||
| 82 | .rate = 48000000, | ||
| 83 | }; | ||
| 84 | |||
| 85 | /* A fixed divide-by-2 block */ | ||
| 86 | static unsigned long div2_recalc(struct clk *clk) | ||
| 87 | { | ||
| 88 | return clk->parent->rate / 2; | ||
| 89 | } | ||
| 90 | |||
| 91 | static struct clk_ops div2_clk_ops = { | ||
| 92 | .recalc = div2_recalc, | ||
| 93 | }; | ||
| 94 | |||
| 95 | /* Divide extal1 by two */ | ||
| 96 | static struct clk extal1_div2_clk = { | ||
| 97 | .ops = &div2_clk_ops, | ||
| 98 | .parent = &sh73a0_extal1_clk, | ||
| 99 | }; | ||
| 100 | |||
| 101 | /* Divide extal2 by two */ | ||
| 102 | static struct clk extal2_div2_clk = { | ||
| 103 | .ops = &div2_clk_ops, | ||
| 104 | .parent = &sh73a0_extal2_clk, | ||
| 105 | }; | ||
| 106 | |||
| 107 | static struct clk_ops main_clk_ops = { | ||
| 108 | .recalc = followparent_recalc, | ||
| 109 | }; | ||
| 110 | |||
| 111 | /* Main clock */ | ||
| 112 | static struct clk main_clk = { | ||
| 113 | .ops = &main_clk_ops, | ||
| 114 | }; | ||
| 115 | |||
| 116 | /* PLL0, PLL1, PLL2, PLL3 */ | ||
| 117 | static unsigned long pll_recalc(struct clk *clk) | ||
| 118 | { | ||
| 119 | unsigned long mult = 1; | ||
| 120 | |||
| 121 | if (__raw_readl(PLLECR) & (1 << clk->enable_bit)) | ||
| 122 | mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1); | ||
| 123 | |||
| 124 | return clk->parent->rate * mult; | ||
| 125 | } | ||
| 126 | |||
| 127 | static struct clk_ops pll_clk_ops = { | ||
| 128 | .recalc = pll_recalc, | ||
| 129 | }; | ||
| 130 | |||
| 131 | static struct clk pll0_clk = { | ||
| 132 | .ops = &pll_clk_ops, | ||
| 133 | .flags = CLK_ENABLE_ON_INIT, | ||
| 134 | .parent = &main_clk, | ||
| 135 | .enable_reg = (void __iomem *)PLL0CR, | ||
| 136 | .enable_bit = 0, | ||
| 137 | }; | ||
| 138 | |||
| 139 | static struct clk pll1_clk = { | ||
| 140 | .ops = &pll_clk_ops, | ||
| 141 | .flags = CLK_ENABLE_ON_INIT, | ||
| 142 | .parent = &main_clk, | ||
| 143 | .enable_reg = (void __iomem *)PLL1CR, | ||
| 144 | .enable_bit = 1, | ||
| 145 | }; | ||
| 146 | |||
| 147 | static struct clk pll2_clk = { | ||
| 148 | .ops = &pll_clk_ops, | ||
| 149 | .flags = CLK_ENABLE_ON_INIT, | ||
| 150 | .parent = &main_clk, | ||
| 151 | .enable_reg = (void __iomem *)PLL2CR, | ||
| 152 | .enable_bit = 2, | ||
| 153 | }; | ||
| 154 | |||
| 155 | static struct clk pll3_clk = { | ||
| 156 | .ops = &pll_clk_ops, | ||
| 157 | .flags = CLK_ENABLE_ON_INIT, | ||
| 158 | .parent = &main_clk, | ||
| 159 | .enable_reg = (void __iomem *)PLL3CR, | ||
| 160 | .enable_bit = 3, | ||
| 161 | }; | ||
| 162 | |||
| 163 | /* Divide PLL1 by two */ | ||
| 164 | static struct clk pll1_div2_clk = { | ||
| 165 | .ops = &div2_clk_ops, | ||
| 166 | .parent = &pll1_clk, | ||
| 167 | }; | ||
| 168 | |||
| 169 | static struct clk *main_clks[] = { | ||
| 170 | &r_clk, | ||
| 171 | &sh73a0_extal1_clk, | ||
| 172 | &sh73a0_extal2_clk, | ||
| 173 | &extal1_div2_clk, | ||
| 174 | &extal2_div2_clk, | ||
| 175 | &main_clk, | ||
| 176 | &pll0_clk, | ||
| 177 | &pll1_clk, | ||
| 178 | &pll2_clk, | ||
| 179 | &pll3_clk, | ||
| 180 | &pll1_div2_clk, | ||
| 181 | }; | ||
| 182 | |||
| 183 | static void div4_kick(struct clk *clk) | ||
| 184 | { | ||
| 185 | unsigned long value; | ||
| 186 | |||
| 187 | /* set KICK bit in FRQCRB to update hardware setting */ | ||
| 188 | value = __raw_readl(FRQCRB); | ||
| 189 | value |= (1 << 31); | ||
| 190 | __raw_writel(value, FRQCRB); | ||
| 191 | } | ||
| 192 | |||
| 193 | static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, | ||
| 194 | 24, 0, 36, 48, 7 }; | ||
| 195 | |||
| 196 | static struct clk_div_mult_table div4_div_mult_table = { | ||
| 197 | .divisors = divisors, | ||
| 198 | .nr_divisors = ARRAY_SIZE(divisors), | ||
| 199 | }; | ||
| 200 | |||
| 201 | static struct clk_div4_table div4_table = { | ||
| 202 | .div_mult_table = &div4_div_mult_table, | ||
| 203 | .kick = div4_kick, | ||
| 204 | }; | ||
| 205 | |||
| 206 | enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2, | ||
| 207 | DIV4_Z, DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP, DIV4_NR }; | ||
| 208 | |||
| 209 | #define DIV4(_reg, _bit, _mask, _flags) \ | ||
| 210 | SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags) | ||
| 211 | |||
| 212 | static struct clk div4_clks[DIV4_NR] = { | ||
| 213 | [DIV4_I] = DIV4(FRQCRA, 20, 0xfff, CLK_ENABLE_ON_INIT), | ||
| 214 | [DIV4_ZG] = DIV4(FRQCRA, 16, 0xbff, CLK_ENABLE_ON_INIT), | ||
| 215 | [DIV4_M3] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT), | ||
| 216 | [DIV4_B] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT), | ||
| 217 | [DIV4_M1] = DIV4(FRQCRA, 4, 0xfff, 0), | ||
| 218 | [DIV4_M2] = DIV4(FRQCRA, 0, 0xfff, 0), | ||
| 219 | [DIV4_Z] = DIV4(FRQCRB, 24, 0xbff, 0), | ||
| 220 | [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xfff, 0), | ||
| 221 | [DIV4_ZT] = DIV4(FRQCRB, 16, 0xfff, 0), | ||
| 222 | [DIV4_ZX] = DIV4(FRQCRB, 12, 0xfff, 0), | ||
| 223 | [DIV4_HP] = DIV4(FRQCRB, 4, 0xfff, 0), | ||
| 224 | }; | ||
| 225 | |||
| 226 | enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1, | ||
| 227 | DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2, | ||
| 228 | DIV6_FSIA, DIV6_FSIB, DIV6_SUB, | ||
| 229 | DIV6_SPUA, DIV6_SPUV, DIV6_MSU, | ||
| 230 | DIV6_HSI, DIV6_MFG1, DIV6_MFG2, | ||
| 231 | DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P, | ||
| 232 | DIV6_NR }; | ||
| 233 | |||
| 234 | static struct clk div6_clks[DIV6_NR] = { | ||
| 235 | [DIV6_VCK1] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR1, 0), | ||
| 236 | [DIV6_VCK2] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR2, 0), | ||
| 237 | [DIV6_VCK3] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR3, 0), | ||
| 238 | [DIV6_ZB1] = SH_CLK_DIV6(&pll1_div2_clk, ZBCKCR, 0), | ||
| 239 | [DIV6_FLCTL] = SH_CLK_DIV6(&pll1_div2_clk, FLCKCR, 0), | ||
| 240 | [DIV6_SDHI0] = SH_CLK_DIV6(&pll1_div2_clk, SD0CKCR, 0), | ||
| 241 | [DIV6_SDHI1] = SH_CLK_DIV6(&pll1_div2_clk, SD1CKCR, 0), | ||
| 242 | [DIV6_SDHI2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0), | ||
| 243 | [DIV6_FSIA] = SH_CLK_DIV6(&pll1_div2_clk, FSIACKCR, 0), | ||
| 244 | [DIV6_FSIB] = SH_CLK_DIV6(&pll1_div2_clk, FSIBCKCR, 0), | ||
| 245 | [DIV6_SUB] = SH_CLK_DIV6(&sh73a0_extal2_clk, SUBCKCR, 0), | ||
| 246 | [DIV6_SPUA] = SH_CLK_DIV6(&pll1_div2_clk, SPUACKCR, 0), | ||
| 247 | [DIV6_SPUV] = SH_CLK_DIV6(&pll1_div2_clk, SPUVCKCR, 0), | ||
| 248 | [DIV6_MSU] = SH_CLK_DIV6(&pll1_div2_clk, MSUCKCR, 0), | ||
| 249 | [DIV6_HSI] = SH_CLK_DIV6(&pll1_div2_clk, HSICKCR, 0), | ||
| 250 | [DIV6_MFG1] = SH_CLK_DIV6(&pll1_div2_clk, MFCK1CR, 0), | ||
| 251 | [DIV6_MFG2] = SH_CLK_DIV6(&pll1_div2_clk, MFCK2CR, 0), | ||
| 252 | [DIV6_DSIT] = SH_CLK_DIV6(&pll1_div2_clk, DSITCKCR, 0), | ||
| 253 | [DIV6_DSI0P] = SH_CLK_DIV6(&pll1_div2_clk, DSI0PCKCR, 0), | ||
| 254 | [DIV6_DSI1P] = SH_CLK_DIV6(&pll1_div2_clk, DSI1PCKCR, 0), | ||
| 255 | }; | ||
| 256 | |||
| 257 | enum { MSTP001, | ||
| 258 | MSTP125, MSTP116, | ||
| 259 | MSTP219, | ||
| 260 | MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, | ||
| 261 | MSTP331, MSTP329, MSTP323, MSTP312, | ||
| 262 | MSTP411, MSTP410, MSTP403, | ||
| 263 | MSTP_NR }; | ||
| 264 | |||
| 265 | #define MSTP(_parent, _reg, _bit, _flags) \ | ||
| 266 | SH_CLK_MSTP32(_parent, _reg, _bit, _flags) | ||
| 267 | |||
| 268 | static struct clk mstp_clks[MSTP_NR] = { | ||
| 269 | [MSTP001] = MSTP(&div4_clks[DIV4_HP], SMSTPCR0, 1, 0), /* IIC2 */ | ||
| 270 | [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */ | ||
| 271 | [MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */ | ||
| 272 | [MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */ | ||
| 273 | [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */ | ||
| 274 | [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */ | ||
| 275 | [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */ | ||
| 276 | [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */ | ||
| 277 | [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */ | ||
| 278 | [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */ | ||
| 279 | [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */ | ||
| 280 | [MSTP331] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 31, 0), /* SCIFA6 */ | ||
| 281 | [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */ | ||
| 282 | [MSTP323] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */ | ||
| 283 | [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */ | ||
| 284 | [MSTP411] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */ | ||
| 285 | [MSTP410] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */ | ||
| 286 | [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */ | ||
| 287 | }; | ||
| 288 | |||
| 289 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } | ||
| 290 | #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk } | ||
| 291 | |||
| 292 | static struct clk_lookup lookups[] = { | ||
| 293 | /* main clocks */ | ||
| 294 | CLKDEV_CON_ID("r_clk", &r_clk), | ||
| 295 | |||
| 296 | /* MSTP32 clocks */ | ||
| 297 | CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */ | ||
| 298 | CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */ | ||
| 299 | CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */ | ||
| 300 | CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */ | ||
| 301 | CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */ | ||
| 302 | CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */ | ||
| 303 | CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */ | ||
| 304 | CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */ | ||
| 305 | CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */ | ||
| 306 | CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */ | ||
| 307 | CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */ | ||
| 308 | CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */ | ||
| 309 | CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */ | ||
| 310 | CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */ | ||
| 311 | CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */ | ||
| 312 | CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */ | ||
| 313 | CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* I2C3 */ | ||
| 314 | CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */ | ||
| 315 | CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */ | ||
| 316 | }; | ||
| 317 | |||
| 318 | void __init sh73a0_clock_init(void) | ||
| 319 | { | ||
| 320 | int k, ret = 0; | ||
| 321 | |||
| 322 | /* detect main clock parent */ | ||
| 323 | switch ((__raw_readl(CKSCR) >> 24) & 0x03) { | ||
| 324 | case 0: | ||
| 325 | main_clk.parent = &sh73a0_extal1_clk; | ||
| 326 | break; | ||
| 327 | case 1: | ||
| 328 | main_clk.parent = &extal1_div2_clk; | ||
| 329 | break; | ||
| 330 | case 2: | ||
| 331 | main_clk.parent = &sh73a0_extal2_clk; | ||
| 332 | break; | ||
| 333 | case 3: | ||
| 334 | main_clk.parent = &extal2_div2_clk; | ||
| 335 | break; | ||
| 336 | } | ||
| 337 | |||
| 338 | for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) | ||
| 339 | ret = clk_register(main_clks[k]); | ||
| 340 | |||
| 341 | if (!ret) | ||
| 342 | ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); | ||
| 343 | |||
| 344 | if (!ret) | ||
| 345 | ret = sh_clk_div6_register(div6_clks, DIV6_NR); | ||
| 346 | |||
| 347 | if (!ret) | ||
| 348 | ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); | ||
| 349 | |||
| 350 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); | ||
| 351 | |||
| 352 | if (!ret) | ||
| 353 | clk_init(); | ||
| 354 | else | ||
| 355 | panic("failed to setup sh73a0 clocks\n"); | ||
| 356 | } | ||
diff --git a/arch/arm/mach-shmobile/entry-gic.S b/arch/arm/mach-shmobile/entry-gic.S new file mode 100644 index 000000000000..e20239b08c83 --- /dev/null +++ b/arch/arm/mach-shmobile/entry-gic.S | |||
| @@ -0,0 +1,18 @@ | |||
| 1 | /* | ||
| 2 | * ARM Interrupt demux handler using GIC | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Magnus Damm | ||
| 5 | * Copyright (C) 2011 Paul Mundt | ||
| 6 | * Copyright (C) 2010 - 2011 Renesas Solutions Corp. | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <asm/assembler.h> | ||
| 14 | #include <asm/entry-macro-multi.S> | ||
| 15 | #include <asm/hardware/gic.h> | ||
| 16 | #include <asm/hardware/entry-macro-gic.S> | ||
| 17 | |||
| 18 | arch_irq_handler shmobile_handle_irq_gic | ||
diff --git a/arch/arm/mach-shmobile/entry-intc.S b/arch/arm/mach-shmobile/entry-intc.S new file mode 100644 index 000000000000..cac0a7ae2084 --- /dev/null +++ b/arch/arm/mach-shmobile/entry-intc.S | |||
| @@ -0,0 +1,57 @@ | |||
| 1 | /* | ||
| 2 | * ARM Interrupt demux handler using INTC | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Magnus Damm | ||
| 5 | * Copyright (C) 2008 Renesas Solutions Corp. | ||
| 6 | * | ||
| 7 | * This file is licensed under the terms of the GNU General Public | ||
| 8 | * License version 2. This program is licensed "as is" without any | ||
| 9 | * warranty of any kind, whether express or implied. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <asm/entry-macro-multi.S> | ||
| 13 | |||
| 14 | #define INTCA_BASE 0xe6980000 | ||
| 15 | #define INTFLGA_OFFS 0x00000018 /* accept pending interrupt */ | ||
| 16 | #define INTEVTA_OFFS 0x00000020 /* vector number of accepted interrupt */ | ||
| 17 | #define INTLVLA_OFFS 0x00000030 /* priority level of accepted interrupt */ | ||
| 18 | #define INTLVLB_OFFS 0x00000034 /* previous priority level */ | ||
| 19 | |||
| 20 | .macro get_irqnr_preamble, base, tmp | ||
| 21 | ldr \base, =INTCA_BASE | ||
| 22 | .endm | ||
| 23 | |||
| 24 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 25 | /* The single INTFLGA read access below results in the following: | ||
| 26 | * | ||
| 27 | * 1. INTLVLB is updated with old priority value from INTLVLA | ||
| 28 | * 2. Highest priority interrupt is accepted | ||
| 29 | * 3. INTLVLA is updated to contain priority of accepted interrupt | ||
| 30 | * 4. Accepted interrupt vector is stored in INTFLGA and INTEVTA | ||
| 31 | */ | ||
| 32 | ldr \irqnr, [\base, #INTFLGA_OFFS] | ||
| 33 | |||
| 34 | /* Restore INTLVLA with the value saved in INTLVLB. | ||
| 35 | * This is required to support interrupt priorities properly. | ||
| 36 | */ | ||
| 37 | ldrb \tmp, [\base, #INTLVLB_OFFS] | ||
| 38 | strb \tmp, [\base, #INTLVLA_OFFS] | ||
| 39 | |||
| 40 | /* Handle invalid vector number case */ | ||
| 41 | cmp \irqnr, #0 | ||
| 42 | beq 1000f | ||
| 43 | |||
| 44 | /* Convert vector to irq number, same as the evt2irq() macro */ | ||
| 45 | lsr \irqnr, \irqnr, #0x5 | ||
| 46 | subs \irqnr, \irqnr, #16 | ||
| 47 | |||
| 48 | 1000: | ||
| 49 | .endm | ||
| 50 | |||
| 51 | .macro test_for_ipi, irqnr, irqstat, base, tmp | ||
| 52 | .endm | ||
| 53 | |||
| 54 | .macro test_for_ltirq, irqnr, irqstat, base, tmp | ||
| 55 | .endm | ||
| 56 | |||
| 57 | arch_irq_handler shmobile_handle_irq_intc | ||
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S new file mode 100644 index 000000000000..d4cec6b4c7d9 --- /dev/null +++ b/arch/arm/mach-shmobile/headsmp.S | |||
| @@ -0,0 +1,27 @@ | |||
| 1 | /* | ||
| 2 | * SMP support for R-Mobile / SH-Mobile | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Magnus Damm | ||
| 5 | * Copyright (C) 2010 Takashi Yoshii | ||
| 6 | * | ||
| 7 | * Based on vexpress, Copyright (c) 2003 ARM Limited, All Rights Reserved | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | #include <linux/linkage.h> | ||
| 14 | #include <linux/init.h> | ||
| 15 | #include <asm/memory.h> | ||
| 16 | |||
| 17 | __INIT | ||
| 18 | |||
| 19 | /* | ||
| 20 | * Reset vector for secondary CPUs. | ||
| 21 | * This will be mapped at address 0 by SBAR register. | ||
| 22 | * We need _long_ jump to the physical address. | ||
| 23 | */ | ||
| 24 | .align 12 | ||
| 25 | ENTRY(shmobile_secondary_vector) | ||
| 26 | ldr pc, 1f | ||
| 27 | 1: .long secondary_startup - PAGE_OFFSET + PHYS_OFFSET | ||
diff --git a/arch/arm/mach-shmobile/hotplug.c b/arch/arm/mach-shmobile/hotplug.c new file mode 100644 index 000000000000..238a0d97d2d5 --- /dev/null +++ b/arch/arm/mach-shmobile/hotplug.c | |||
| @@ -0,0 +1,41 @@ | |||
| 1 | /* | ||
| 2 | * SMP support for R-Mobile / SH-Mobile | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Magnus Damm | ||
| 5 | * | ||
| 6 | * Based on realview, Copyright (C) 2002 ARM Ltd, All Rights Reserved | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/errno.h> | ||
| 14 | #include <linux/smp.h> | ||
| 15 | |||
| 16 | int platform_cpu_kill(unsigned int cpu) | ||
| 17 | { | ||
| 18 | return 1; | ||
| 19 | } | ||
| 20 | |||
| 21 | void platform_cpu_die(unsigned int cpu) | ||
| 22 | { | ||
| 23 | while (1) { | ||
| 24 | /* | ||
| 25 | * here's the WFI | ||
| 26 | */ | ||
| 27 | asm(".word 0xe320f003\n" | ||
| 28 | : | ||
| 29 | : | ||
| 30 | : "memory", "cc"); | ||
| 31 | } | ||
| 32 | } | ||
| 33 | |||
| 34 | int platform_cpu_disable(unsigned int cpu) | ||
| 35 | { | ||
| 36 | /* | ||
| 37 | * we don't allow CPU 0 to be shutdown (it is still too special | ||
| 38 | * e.g. clock tick interrupts) | ||
| 39 | */ | ||
| 40 | return cpu == 0 ? -EPERM : 0; | ||
| 41 | } | ||
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index efeef778a875..013ac0ee8256 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h | |||
| @@ -3,8 +3,11 @@ | |||
| 3 | 3 | ||
| 4 | extern struct sys_timer shmobile_timer; | 4 | extern struct sys_timer shmobile_timer; |
| 5 | extern void shmobile_setup_console(void); | 5 | extern void shmobile_setup_console(void); |
| 6 | extern void shmobile_secondary_vector(void); | ||
| 6 | struct clk; | 7 | struct clk; |
| 7 | extern int clk_init(void); | 8 | extern int clk_init(void); |
| 9 | extern void shmobile_handle_irq_intc(struct pt_regs *); | ||
| 10 | extern void shmobile_handle_irq_gic(struct pt_regs *); | ||
| 8 | 11 | ||
| 9 | extern void sh7367_init_irq(void); | 12 | extern void sh7367_init_irq(void); |
| 10 | extern void sh7367_add_early_devices(void); | 13 | extern void sh7367_add_early_devices(void); |
| @@ -30,4 +33,17 @@ extern void sh7372_pinmux_init(void); | |||
| 30 | extern struct clk sh7372_extal1_clk; | 33 | extern struct clk sh7372_extal1_clk; |
| 31 | extern struct clk sh7372_extal2_clk; | 34 | extern struct clk sh7372_extal2_clk; |
| 32 | 35 | ||
| 36 | extern void sh73a0_init_irq(void); | ||
| 37 | extern void sh73a0_add_early_devices(void); | ||
| 38 | extern void sh73a0_add_standard_devices(void); | ||
| 39 | extern void sh73a0_clock_init(void); | ||
| 40 | extern void sh73a0_pinmux_init(void); | ||
| 41 | extern struct clk sh73a0_extal1_clk; | ||
| 42 | extern struct clk sh73a0_extal2_clk; | ||
| 43 | |||
| 44 | extern unsigned int sh73a0_get_core_count(void); | ||
| 45 | extern void sh73a0_secondary_init(unsigned int cpu); | ||
| 46 | extern int sh73a0_boot_secondary(unsigned int cpu); | ||
| 47 | extern void sh73a0_smp_prepare_cpus(void); | ||
| 48 | |||
| 33 | #endif /* __ARCH_MACH_COMMON_H */ | 49 | #endif /* __ARCH_MACH_COMMON_H */ |
diff --git a/arch/arm/mach-shmobile/include/mach/entry-macro.S b/arch/arm/mach-shmobile/include/mach/entry-macro.S index f428c4db2b60..d791f10eeac7 100644 --- a/arch/arm/mach-shmobile/include/mach/entry-macro.S +++ b/arch/arm/mach-shmobile/include/mach/entry-macro.S | |||
| @@ -1,6 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) 2010 Magnus Damm | 2 | * Copyright (C) 2010 Paul Mundt |
| 3 | * Copyright (C) 2008 Renesas Solutions Corp. | ||
| 4 | * | 3 | * |
| 5 | * This program is free software; you can redistribute it and/or modify | 4 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by | 5 | * it under the terms of the GNU General Public License as published by |
| @@ -15,47 +14,21 @@ | |||
| 15 | * along with this program; if not, write to the Free Software | 14 | * along with this program; if not, write to the Free Software |
| 16 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | 15 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 17 | */ | 16 | */ |
| 18 | #include <mach/irqs.h> | ||
| 19 | |||
| 20 | #define INTCA_BASE 0xe6980000 | ||
| 21 | #define INTFLGA_OFFS 0x00000018 /* accept pending interrupt */ | ||
| 22 | #define INTEVTA_OFFS 0x00000020 /* vector number of accepted interrupt */ | ||
| 23 | #define INTLVLA_OFFS 0x00000030 /* priority level of accepted interrupt */ | ||
| 24 | #define INTLVLB_OFFS 0x00000034 /* previous priority level */ | ||
| 25 | 17 | ||
| 26 | .macro disable_fiq | 18 | .macro disable_fiq |
| 27 | .endm | 19 | .endm |
| 28 | 20 | ||
| 29 | .macro get_irqnr_preamble, base, tmp | 21 | .macro get_irqnr_preamble, base, tmp |
| 30 | ldr \base, =INTCA_BASE | ||
| 31 | .endm | ||
| 32 | |||
| 33 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 34 | .endm | 22 | .endm |
| 35 | 23 | ||
| 36 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | 24 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp |
| 37 | /* The single INTFLGA read access below results in the following: | 25 | .endm |
| 38 | * | ||
| 39 | * 1. INTLVLB is updated with old priority value from INTLVLA | ||
| 40 | * 2. Highest priority interrupt is accepted | ||
| 41 | * 3. INTLVLA is updated to contain priority of accepted interrupt | ||
| 42 | * 4. Accepted interrupt vector is stored in INTFLGA and INTEVTA | ||
| 43 | */ | ||
| 44 | ldr \irqnr, [\base, #INTFLGA_OFFS] | ||
| 45 | |||
| 46 | /* Restore INTLVLA with the value saved in INTLVLB. | ||
| 47 | * This is required to support interrupt priorities properly. | ||
| 48 | */ | ||
| 49 | ldrb \tmp, [\base, #INTLVLB_OFFS] | ||
| 50 | strb \tmp, [\base, #INTLVLA_OFFS] | ||
| 51 | 26 | ||
| 52 | /* Handle invalid vector number case */ | 27 | .macro test_for_ipi, irqnr, irqstat, base, tmp |
| 53 | cmp \irqnr, #0 | 28 | .endm |
| 54 | beq 1000f | ||
| 55 | 29 | ||
| 56 | /* Convert vector to irq number, same as the evt2irq() macro */ | 30 | .macro test_for_ltirq, irqnr, irqstat, base, tmp |
| 57 | lsr \irqnr, \irqnr, #0x5 | 31 | .endm |
| 58 | subs \irqnr, \irqnr, #16 | ||
| 59 | 32 | ||
| 60 | 1000: | 33 | .macro arch_ret_to_user, tmp1, tmp2 |
| 61 | .endm | 34 | .endm |
diff --git a/arch/arm/mach-shmobile/include/mach/hardware.h b/arch/arm/mach-shmobile/include/mach/hardware.h index 3f0ef194603e..99264a5ce5e4 100644 --- a/arch/arm/mach-shmobile/include/mach/hardware.h +++ b/arch/arm/mach-shmobile/include/mach/hardware.h | |||
| @@ -1,7 +1,4 @@ | |||
| 1 | #ifndef __ASM_MACH_HARDWARE_H | 1 | #ifndef __ASM_MACH_HARDWARE_H |
| 2 | #define __ASM_MACH_HARDWARE_H | 2 | #define __ASM_MACH_HARDWARE_H |
| 3 | 3 | ||
| 4 | /* INTFLGA register - used by low level interrupt code in entry-macro.S */ | ||
| 5 | #define INTFLGA 0xe6980018 | ||
| 6 | |||
| 7 | #endif /* __ASM_MACH_HARDWARE_H */ | 4 | #endif /* __ASM_MACH_HARDWARE_H */ |
diff --git a/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt b/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt new file mode 100644 index 000000000000..e3ebfa73956e --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt | |||
| @@ -0,0 +1,87 @@ | |||
| 1 | LIST "partner-jet-setup.txt" | ||
| 2 | LIST "(C) Copyright 2010 Renesas Solutions Corp" | ||
| 3 | LIST "Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>" | ||
| 4 | |||
| 5 | LIST "RWT Setting" | ||
| 6 | EW 0xE6020004, 0xA500 | ||
| 7 | EW 0xE6030004, 0xA500 | ||
| 8 | |||
| 9 | DD 0x01001000, 0x01001000 | ||
| 10 | |||
| 11 | LIST "GPIO Setting" | ||
| 12 | EB 0xE6051013, 0xA2 | ||
| 13 | |||
| 14 | LIST "CPG" | ||
| 15 | ED 0xE6150080, 0x00000180 | ||
| 16 | ED 0xE61500C0, 0x00000002 | ||
| 17 | |||
| 18 | WAIT 1, 0xFE40009C | ||
| 19 | |||
| 20 | LIST "FRQCR" | ||
| 21 | ED 0xE6150000, 0x2D1305C3 | ||
| 22 | ED 0xE61500E0, 0x9E40358E | ||
| 23 | ED 0xE6150004, 0x80331050 | ||
| 24 | |||
| 25 | WAIT 1, 0xFE40009C | ||
| 26 | |||
| 27 | ED 0xE61500E4, 0x00002000 | ||
| 28 | |||
| 29 | WAIT 1, 0xFE40009C | ||
| 30 | |||
| 31 | LIST "PLL" | ||
| 32 | ED 0xE6150028, 0x00004000 | ||
| 33 | |||
| 34 | WAIT 1, 0xFE40009C | ||
| 35 | |||
| 36 | ED 0xE615002C, 0x93000040 | ||
| 37 | |||
| 38 | WAIT 1, 0xFE40009C | ||
| 39 | |||
| 40 | LIST "BSC" | ||
| 41 | ED 0xFEC10000, 0x00E0001B | ||
| 42 | |||
| 43 | LIST "SBSC1" | ||
| 44 | ED 0xFE400354, 0x01AD8000 | ||
| 45 | ED 0xFE400354, 0x01AD8001 | ||
| 46 | |||
| 47 | WAIT 5, 0xFE40009C | ||
| 48 | |||
| 49 | ED 0xFE400008, 0xBCC90151 | ||
| 50 | ED 0xFE400040, 0x41774113 | ||
| 51 | ED 0xFE400044, 0x2712E229 | ||
| 52 | ED 0xFE400048, 0x20C18505 | ||
| 53 | ED 0xFE40004C, 0x00110209 | ||
| 54 | ED 0xFE400010, 0x00000087 | ||
| 55 | |||
| 56 | WAIT 10, 0xFE40009C | ||
| 57 | |||
| 58 | ED 0xFE400084, 0x0000003F | ||
| 59 | EB 0xFE500000, 0x00 | ||
| 60 | |||
| 61 | WAIT 5, 0xFE40009C | ||
| 62 | |||
| 63 | ED 0xFE400084, 0x0000FF0A | ||
| 64 | EB 0xFE500000, 0x00 | ||
| 65 | |||
| 66 | WAIT 1, 0xFE40009C | ||
| 67 | |||
| 68 | ED 0xFE400084, 0x00002201 | ||
| 69 | EB 0xFE500000, 0x00 | ||
| 70 | ED 0xFE400084, 0x00000302 | ||
| 71 | EB 0xFE500000, 0x00 | ||
| 72 | EB 0xFE5C0000, 0x00 | ||
| 73 | ED 0xFE400008, 0xBCC90159 | ||
| 74 | ED 0xFE40008C, 0x88800004 | ||
| 75 | ED 0xFE400094, 0x00000004 | ||
| 76 | ED 0xFE400028, 0xA55A0032 | ||
| 77 | ED 0xFE40002C, 0xA55A000C | ||
| 78 | ED 0xFE400020, 0xA55A2048 | ||
| 79 | ED 0xFE400008, 0xBCC90959 | ||
| 80 | |||
| 81 | LIST "Change CPGA setting" | ||
| 82 | ED 0xE61500E0, 0x9E40352E | ||
| 83 | ED 0xE6150004, 0x80331050 | ||
| 84 | |||
| 85 | WAIT 1, 0xFE40009C | ||
| 86 | |||
| 87 | ED 0xE6150354, 0x00000002 | ||
diff --git a/arch/arm/mach-shmobile/include/mach/head-mackerel.txt b/arch/arm/mach-shmobile/include/mach/head-mackerel.txt new file mode 100644 index 000000000000..e3ebfa73956e --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/head-mackerel.txt | |||
| @@ -0,0 +1,87 @@ | |||
| 1 | LIST "partner-jet-setup.txt" | ||
| 2 | LIST "(C) Copyright 2010 Renesas Solutions Corp" | ||
| 3 | LIST "Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>" | ||
| 4 | |||
| 5 | LIST "RWT Setting" | ||
| 6 | EW 0xE6020004, 0xA500 | ||
| 7 | EW 0xE6030004, 0xA500 | ||
| 8 | |||
| 9 | DD 0x01001000, 0x01001000 | ||
| 10 | |||
| 11 | LIST "GPIO Setting" | ||
| 12 | EB 0xE6051013, 0xA2 | ||
| 13 | |||
| 14 | LIST "CPG" | ||
| 15 | ED 0xE6150080, 0x00000180 | ||
| 16 | ED 0xE61500C0, 0x00000002 | ||
| 17 | |||
| 18 | WAIT 1, 0xFE40009C | ||
| 19 | |||
| 20 | LIST "FRQCR" | ||
| 21 | ED 0xE6150000, 0x2D1305C3 | ||
| 22 | ED 0xE61500E0, 0x9E40358E | ||
| 23 | ED 0xE6150004, 0x80331050 | ||
| 24 | |||
| 25 | WAIT 1, 0xFE40009C | ||
| 26 | |||
| 27 | ED 0xE61500E4, 0x00002000 | ||
| 28 | |||
| 29 | WAIT 1, 0xFE40009C | ||
| 30 | |||
| 31 | LIST "PLL" | ||
| 32 | ED 0xE6150028, 0x00004000 | ||
| 33 | |||
| 34 | WAIT 1, 0xFE40009C | ||
| 35 | |||
| 36 | ED 0xE615002C, 0x93000040 | ||
| 37 | |||
| 38 | WAIT 1, 0xFE40009C | ||
| 39 | |||
| 40 | LIST "BSC" | ||
| 41 | ED 0xFEC10000, 0x00E0001B | ||
| 42 | |||
| 43 | LIST "SBSC1" | ||
| 44 | ED 0xFE400354, 0x01AD8000 | ||
| 45 | ED 0xFE400354, 0x01AD8001 | ||
| 46 | |||
| 47 | WAIT 5, 0xFE40009C | ||
| 48 | |||
| 49 | ED 0xFE400008, 0xBCC90151 | ||
| 50 | ED 0xFE400040, 0x41774113 | ||
| 51 | ED 0xFE400044, 0x2712E229 | ||
| 52 | ED 0xFE400048, 0x20C18505 | ||
| 53 | ED 0xFE40004C, 0x00110209 | ||
| 54 | ED 0xFE400010, 0x00000087 | ||
| 55 | |||
| 56 | WAIT 10, 0xFE40009C | ||
| 57 | |||
| 58 | ED 0xFE400084, 0x0000003F | ||
| 59 | EB 0xFE500000, 0x00 | ||
| 60 | |||
| 61 | WAIT 5, 0xFE40009C | ||
| 62 | |||
| 63 | ED 0xFE400084, 0x0000FF0A | ||
| 64 | EB 0xFE500000, 0x00 | ||
| 65 | |||
| 66 | WAIT 1, 0xFE40009C | ||
| 67 | |||
| 68 | ED 0xFE400084, 0x00002201 | ||
| 69 | EB 0xFE500000, 0x00 | ||
| 70 | ED 0xFE400084, 0x00000302 | ||
| 71 | EB 0xFE500000, 0x00 | ||
| 72 | EB 0xFE5C0000, 0x00 | ||
| 73 | ED 0xFE400008, 0xBCC90159 | ||
| 74 | ED 0xFE40008C, 0x88800004 | ||
| 75 | ED 0xFE400094, 0x00000004 | ||
| 76 | ED 0xFE400028, 0xA55A0032 | ||
| 77 | ED 0xFE40002C, 0xA55A000C | ||
| 78 | ED 0xFE400020, 0xA55A2048 | ||
| 79 | ED 0xFE400008, 0xBCC90959 | ||
| 80 | |||
| 81 | LIST "Change CPGA setting" | ||
| 82 | ED 0xE61500E0, 0x9E40352E | ||
| 83 | ED 0xE6150004, 0x80331050 | ||
| 84 | |||
| 85 | WAIT 1, 0xFE40009C | ||
| 86 | |||
| 87 | ED 0xE6150354, 0x00000002 | ||
diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h index fa15b5f8a001..dcb714f4d75a 100644 --- a/arch/arm/mach-shmobile/include/mach/irqs.h +++ b/arch/arm/mach-shmobile/include/mach/irqs.h | |||
| @@ -1,7 +1,10 @@ | |||
| 1 | #ifndef __ASM_MACH_IRQS_H | 1 | #ifndef __ASM_MACH_IRQS_H |
| 2 | #define __ASM_MACH_IRQS_H | 2 | #define __ASM_MACH_IRQS_H |
| 3 | 3 | ||
| 4 | #define NR_IRQS 512 | 4 | #define NR_IRQS 1024 |
| 5 | |||
| 6 | /* GIC */ | ||
| 7 | #define gic_spi(nr) ((nr) + 32) | ||
| 5 | 8 | ||
| 6 | /* INTCA */ | 9 | /* INTCA */ |
| 7 | #define evt2irq(evt) (((evt) >> 5) - 16) | 10 | #define evt2irq(evt) (((evt) >> 5) - 16) |
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h index e4f9004e7103..5736efcca60c 100644 --- a/arch/arm/mach-shmobile/include/mach/sh7372.h +++ b/arch/arm/mach-shmobile/include/mach/sh7372.h | |||
| @@ -455,6 +455,8 @@ enum { | |||
| 455 | SHDMA_SLAVE_SDHI1_TX, | 455 | SHDMA_SLAVE_SDHI1_TX, |
| 456 | SHDMA_SLAVE_SDHI2_RX, | 456 | SHDMA_SLAVE_SDHI2_RX, |
| 457 | SHDMA_SLAVE_SDHI2_TX, | 457 | SHDMA_SLAVE_SDHI2_TX, |
| 458 | SHDMA_SLAVE_MMCIF_RX, | ||
| 459 | SHDMA_SLAVE_MMCIF_TX, | ||
| 458 | }; | 460 | }; |
| 459 | 461 | ||
| 460 | extern struct clk sh7372_extal1_clk; | 462 | extern struct clk sh7372_extal1_clk; |
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h new file mode 100644 index 000000000000..ceb2cdc92bf9 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h | |||
| @@ -0,0 +1,467 @@ | |||
| 1 | #ifndef __ASM_SH73A0_H__ | ||
| 2 | #define __ASM_SH73A0_H__ | ||
| 3 | |||
| 4 | /* Pin Function Controller: | ||
| 5 | * GPIO_FN_xx - GPIO used to select pin function and MSEL switch | ||
| 6 | * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU | ||
| 7 | */ | ||
| 8 | enum { | ||
| 9 | /* Hardware manual Table 25-1 (GPIO) */ | ||
| 10 | GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4, | ||
| 11 | GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9, | ||
| 12 | |||
| 13 | GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14, | ||
| 14 | GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19, | ||
| 15 | |||
| 16 | GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24, | ||
| 17 | GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29, | ||
| 18 | |||
| 19 | GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34, | ||
| 20 | GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39, | ||
| 21 | |||
| 22 | GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44, | ||
| 23 | GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49, | ||
| 24 | |||
| 25 | GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54, | ||
| 26 | GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59, | ||
| 27 | |||
| 28 | GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64, | ||
| 29 | GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69, | ||
| 30 | |||
| 31 | GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74, | ||
| 32 | GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79, | ||
| 33 | |||
| 34 | GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84, | ||
| 35 | GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89, | ||
| 36 | |||
| 37 | GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94, | ||
| 38 | GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99, | ||
| 39 | |||
| 40 | GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104, | ||
| 41 | GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109, | ||
| 42 | |||
| 43 | GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114, | ||
| 44 | GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, | ||
| 45 | |||
| 46 | GPIO_PORT128, GPIO_PORT129, | ||
| 47 | |||
| 48 | GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134, | ||
| 49 | GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139, | ||
| 50 | |||
| 51 | GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144, | ||
| 52 | GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149, | ||
| 53 | |||
| 54 | GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154, | ||
| 55 | GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159, | ||
| 56 | |||
| 57 | GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164, | ||
| 58 | |||
| 59 | GPIO_PORT192, GPIO_PORT193, GPIO_PORT194, | ||
| 60 | GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199, | ||
| 61 | |||
| 62 | GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204, | ||
| 63 | GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209, | ||
| 64 | |||
| 65 | GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214, | ||
| 66 | GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219, | ||
| 67 | |||
| 68 | GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224, | ||
| 69 | GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229, | ||
| 70 | |||
| 71 | GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234, | ||
| 72 | GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239, | ||
| 73 | |||
| 74 | GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244, | ||
| 75 | GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249, | ||
| 76 | |||
| 77 | GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254, | ||
| 78 | GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259, | ||
| 79 | |||
| 80 | GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264, | ||
| 81 | GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269, | ||
| 82 | |||
| 83 | GPIO_PORT270, GPIO_PORT271, GPIO_PORT272, GPIO_PORT273, GPIO_PORT274, | ||
| 84 | GPIO_PORT275, GPIO_PORT276, GPIO_PORT277, GPIO_PORT278, GPIO_PORT279, | ||
| 85 | |||
| 86 | GPIO_PORT280, GPIO_PORT281, GPIO_PORT282, | ||
| 87 | |||
| 88 | GPIO_PORT288, GPIO_PORT289, | ||
| 89 | |||
| 90 | GPIO_PORT290, GPIO_PORT291, GPIO_PORT292, GPIO_PORT293, GPIO_PORT294, | ||
| 91 | GPIO_PORT295, GPIO_PORT296, GPIO_PORT297, GPIO_PORT298, GPIO_PORT299, | ||
| 92 | |||
| 93 | GPIO_PORT300, GPIO_PORT301, GPIO_PORT302, GPIO_PORT303, GPIO_PORT304, | ||
| 94 | GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309, | ||
| 95 | |||
| 96 | /* Table 25-1 (Function 0-7) */ | ||
| 97 | GPIO_FN_VBUS_0, | ||
| 98 | GPIO_FN_GPI0, | ||
| 99 | GPIO_FN_GPI1, | ||
| 100 | GPIO_FN_GPI2, | ||
| 101 | GPIO_FN_GPI3, | ||
| 102 | GPIO_FN_GPI4, | ||
| 103 | GPIO_FN_GPI5, | ||
| 104 | GPIO_FN_GPI6, | ||
| 105 | GPIO_FN_GPI7, | ||
| 106 | GPIO_FN_SCIFA7_RXD, | ||
| 107 | GPIO_FN_SCIFA7_CTS_, | ||
| 108 | GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2, | ||
| 109 | GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2, | ||
| 110 | GPIO_FN_GPO5, GPIO_FN_SCIFA0_SCK, GPIO_FN_FSICOSLDT3, \ | ||
| 111 | GPIO_FN_PORT16_VIO_CKOR, | ||
| 112 | GPIO_FN_SCIFA0_TXD, | ||
| 113 | GPIO_FN_SCIFA7_TXD, | ||
| 114 | GPIO_FN_SCIFA7_RTS_, GPIO_FN_PORT19_VIO_CKO2, | ||
| 115 | GPIO_FN_GPO0, | ||
| 116 | GPIO_FN_GPO1, | ||
| 117 | GPIO_FN_GPO2, GPIO_FN_STATUS0, | ||
| 118 | GPIO_FN_GPO3, GPIO_FN_STATUS1, | ||
| 119 | GPIO_FN_GPO4, GPIO_FN_STATUS2, | ||
| 120 | GPIO_FN_VINT, | ||
| 121 | GPIO_FN_TCKON, | ||
| 122 | GPIO_FN_XDVFS1, GPIO_FN_PORT27_I2C_SCL2, GPIO_FN_PORT27_I2C_SCL3, \ | ||
| 123 | GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT, | ||
| 124 | GPIO_FN_XDVFS2, GPIO_FN_PORT28_I2C_SDA2, GPIO_FN_PORT28_I2C_SDA3, \ | ||
| 125 | GPIO_FN_PORT28_TPU1TO1, | ||
| 126 | GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1, | ||
| 127 | GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR, | ||
| 128 | GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT, | ||
| 129 | GPIO_FN_SCIFA4_TXD, | ||
| 130 | GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP, | ||
| 131 | GPIO_FN_SCIFA4_RTS_, | ||
| 132 | GPIO_FN_SCIFA4_CTS_, | ||
| 133 | GPIO_FN_FSIBOBT, GPIO_FN_FSIBIBT, | ||
| 134 | GPIO_FN_FSIBOLR, GPIO_FN_FSIBILR, | ||
| 135 | GPIO_FN_FSIBOSLD, | ||
| 136 | GPIO_FN_FSIBISLD, | ||
| 137 | GPIO_FN_VACK, | ||
| 138 | GPIO_FN_XTAL1L, | ||
| 139 | GPIO_FN_SCIFA0_RTS_, GPIO_FN_FSICOSLDT2, | ||
| 140 | GPIO_FN_SCIFA0_RXD, | ||
| 141 | GPIO_FN_SCIFA0_CTS_, GPIO_FN_FSICOSLDT1, | ||
| 142 | GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_FSIDOBT, GPIO_FN_FSIDIBT, | ||
| 143 | GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_FSIDOLR, GPIO_FN_FSIDILR, | ||
| 144 | GPIO_FN_FSICOSLD, GPIO_FN_PORT47_FSICSPDIF, | ||
| 145 | GPIO_FN_FSICISLD, GPIO_FN_FSIDISLD, | ||
| 146 | GPIO_FN_FSIACK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, \ | ||
| 147 | GPIO_FN_FSIAOMC, | ||
| 148 | GPIO_FN_FSIAOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_FSIAILR, | ||
| 149 | |||
| 150 | GPIO_FN_FSIAOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_FSIAIBT, | ||
| 151 | GPIO_FN_FSIAOSLD, GPIO_FN_BBIF2_TXD2, | ||
| 152 | GPIO_FN_FSIASPDIF, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, \ | ||
| 153 | GPIO_FN_FSIBSPDIF, GPIO_FN_PORT53_FSICSPDIF, | ||
| 154 | GPIO_FN_FSIBCK, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, \ | ||
| 155 | GPIO_FN_FSIBOMC, GPIO_FN_FSICCK, GPIO_FN_FSICOMC, | ||
| 156 | GPIO_FN_FSIAISLD, GPIO_FN_TPU0TO0, | ||
| 157 | GPIO_FN_A0, GPIO_FN_BS_, | ||
| 158 | GPIO_FN_A12, GPIO_FN_PORT58_KEYOUT7, GPIO_FN_TPU4TO2, | ||
| 159 | GPIO_FN_A13, GPIO_FN_PORT59_KEYOUT6, GPIO_FN_TPU0TO1, | ||
| 160 | GPIO_FN_A14, GPIO_FN_KEYOUT5, | ||
| 161 | GPIO_FN_A15, GPIO_FN_KEYOUT4, | ||
| 162 | GPIO_FN_A16, GPIO_FN_KEYOUT3, GPIO_FN_MSIOF0_SS1, | ||
| 163 | GPIO_FN_A17, GPIO_FN_KEYOUT2, GPIO_FN_MSIOF0_TSYNC, | ||
| 164 | GPIO_FN_A18, GPIO_FN_KEYOUT1, GPIO_FN_MSIOF0_TSCK, | ||
| 165 | GPIO_FN_A19, GPIO_FN_KEYOUT0, GPIO_FN_MSIOF0_TXD, | ||
| 166 | GPIO_FN_A20, GPIO_FN_KEYIN0, GPIO_FN_MSIOF0_RSCK, | ||
| 167 | GPIO_FN_A21, GPIO_FN_KEYIN1, GPIO_FN_MSIOF0_RSYNC, | ||
| 168 | GPIO_FN_A22, GPIO_FN_KEYIN2, GPIO_FN_MSIOF0_MCK0, | ||
| 169 | GPIO_FN_A23, GPIO_FN_KEYIN3, GPIO_FN_MSIOF0_MCK1, | ||
| 170 | GPIO_FN_A24, GPIO_FN_KEYIN4, GPIO_FN_MSIOF0_RXD, | ||
| 171 | GPIO_FN_A25, GPIO_FN_KEYIN5, GPIO_FN_MSIOF0_SS2, | ||
| 172 | GPIO_FN_A26, GPIO_FN_KEYIN6, | ||
| 173 | GPIO_FN_KEYIN7, | ||
| 174 | GPIO_FN_D0_NAF0, | ||
| 175 | GPIO_FN_D1_NAF1, | ||
| 176 | GPIO_FN_D2_NAF2, | ||
| 177 | GPIO_FN_D3_NAF3, | ||
| 178 | GPIO_FN_D4_NAF4, | ||
| 179 | GPIO_FN_D5_NAF5, | ||
| 180 | GPIO_FN_D6_NAF6, | ||
| 181 | GPIO_FN_D7_NAF7, | ||
| 182 | GPIO_FN_D8_NAF8, | ||
| 183 | GPIO_FN_D9_NAF9, | ||
| 184 | GPIO_FN_D10_NAF10, | ||
| 185 | GPIO_FN_D11_NAF11, | ||
| 186 | GPIO_FN_D12_NAF12, | ||
| 187 | GPIO_FN_D13_NAF13, | ||
| 188 | GPIO_FN_D14_NAF14, | ||
| 189 | GPIO_FN_D15_NAF15, | ||
| 190 | GPIO_FN_CS4_, | ||
| 191 | GPIO_FN_CS5A_, GPIO_FN_PORT91_RDWR, | ||
| 192 | GPIO_FN_CS5B_, GPIO_FN_FCE1_, | ||
| 193 | GPIO_FN_CS6B_, GPIO_FN_DACK0, | ||
| 194 | GPIO_FN_FCE0_, GPIO_FN_CS6A_, | ||
| 195 | GPIO_FN_WAIT_, GPIO_FN_DREQ0, | ||
| 196 | GPIO_FN_RD__FSC, | ||
| 197 | GPIO_FN_WE0__FWE, GPIO_FN_RDWR_FWE, | ||
| 198 | GPIO_FN_WE1_, | ||
| 199 | GPIO_FN_FRB, | ||
| 200 | GPIO_FN_CKO, | ||
| 201 | GPIO_FN_NBRSTOUT_, | ||
| 202 | GPIO_FN_NBRST_, | ||
| 203 | GPIO_FN_BBIF2_TXD, | ||
| 204 | GPIO_FN_BBIF2_RXD, | ||
| 205 | GPIO_FN_BBIF2_SYNC, | ||
| 206 | GPIO_FN_BBIF2_SCK, | ||
| 207 | GPIO_FN_SCIFA3_CTS_, GPIO_FN_MFG3_IN2, | ||
| 208 | GPIO_FN_SCIFA3_RXD, GPIO_FN_MFG3_IN1, | ||
| 209 | GPIO_FN_BBIF1_SS2, GPIO_FN_SCIFA3_RTS_, GPIO_FN_MFG3_OUT1, | ||
| 210 | GPIO_FN_SCIFA3_TXD, | ||
| 211 | GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD, | ||
| 212 | GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK, | ||
| 213 | GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC, | ||
| 214 | GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD, | ||
| 215 | GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, GPIO_FN_PORT115_I2C_SCL2, \ | ||
| 216 | GPIO_FN_PORT115_I2C_SCL3, | ||
| 217 | GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, GPIO_FN_PORT116_I2C_SDA2, \ | ||
| 218 | GPIO_FN_PORT116_I2C_SDA3, | ||
| 219 | GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW, | ||
| 220 | GPIO_FN_HSI_TX_FLAG, | ||
| 221 | GPIO_FN_VIO_VD, GPIO_FN_PORT128_LCD2VSYN, GPIO_FN_VIO2_VD, \ | ||
| 222 | GPIO_FN_LCD2D0, | ||
| 223 | |||
| 224 | GPIO_FN_VIO_HD, GPIO_FN_PORT129_LCD2HSYN, GPIO_FN_PORT129_LCD2CS_, \ | ||
| 225 | GPIO_FN_VIO2_HD, GPIO_FN_LCD2D1, | ||
| 226 | GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, GPIO_FN_LCD2D10, | ||
| 227 | GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT6, GPIO_FN_PORT131_MSIOF2_SS1, \ | ||
| 228 | GPIO_FN_PORT131_KEYOUT11, GPIO_FN_LCD2D11, | ||
| 229 | GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT7, GPIO_FN_PORT132_MSIOF2_SS2, \ | ||
| 230 | GPIO_FN_PORT132_KEYOUT10, GPIO_FN_LCD2D12, | ||
| 231 | GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_LCD2D13, | ||
| 232 | GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, GPIO_FN_LCD2D14, | ||
| 233 | GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, GPIO_FN_LCD2D15, | ||
| 234 | GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8, GPIO_FN_LCD2D16, | ||
| 235 | GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9, GPIO_FN_LCD2D17, | ||
| 236 | GPIO_FN_VIO_D8, GPIO_FN_PORT138_KEYOUT8, GPIO_FN_VIO2_D0, \ | ||
| 237 | GPIO_FN_LCD2D6, | ||
| 238 | GPIO_FN_VIO_D9, GPIO_FN_PORT139_KEYOUT9, GPIO_FN_VIO2_D1, \ | ||
| 239 | GPIO_FN_LCD2D7, | ||
| 240 | GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, GPIO_FN_LCD2D8, | ||
| 241 | GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, GPIO_FN_LCD2D9, | ||
| 242 | GPIO_FN_VIO_D12, GPIO_FN_PORT142_KEYOUT10, GPIO_FN_VIO2_D4, \ | ||
| 243 | GPIO_FN_LCD2D2, | ||
| 244 | GPIO_FN_VIO_D13, GPIO_FN_PORT143_KEYOUT11, GPIO_FN_PORT143_KEYOUT6, \ | ||
| 245 | GPIO_FN_VIO2_D5, GPIO_FN_LCD2D3, | ||
| 246 | GPIO_FN_VIO_D14, GPIO_FN_PORT144_KEYOUT7, GPIO_FN_VIO2_D6, \ | ||
| 247 | GPIO_FN_LCD2D4, | ||
| 248 | GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_LCD2DISP, \ | ||
| 249 | GPIO_FN_PORT145_LCD2RS, GPIO_FN_VIO2_D7, GPIO_FN_LCD2D5, | ||
| 250 | GPIO_FN_VIO_CLK, GPIO_FN_LCD2DCK, GPIO_FN_PORT146_LCD2WR_, \ | ||
| 251 | GPIO_FN_VIO2_CLK, GPIO_FN_LCD2D18, | ||
| 252 | GPIO_FN_VIO_FIELD, GPIO_FN_LCD2RD_, GPIO_FN_VIO2_FIELD, GPIO_FN_LCD2D19, | ||
| 253 | GPIO_FN_VIO_CKO, | ||
| 254 | GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \ | ||
| 255 | GPIO_FN_PORT149_KEYOUT9, | ||
| 256 | GPIO_FN_MFG0_IN2, | ||
| 257 | GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK, | ||
| 258 | GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC, | ||
| 259 | GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1, | ||
| 260 | GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0, | ||
| 261 | GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1, | ||
| 262 | GPIO_FN_SCIFA2_RTS1_, GPIO_FN_PORT156_MSIOF2_SS2, | ||
| 263 | GPIO_FN_SCIFA2_CTS1_, GPIO_FN_PORT157_MSIOF2_RXD, | ||
| 264 | GPIO_FN_DINT_, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3, | ||
| 265 | GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI, | ||
| 266 | GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD, | ||
| 267 | GPIO_FN_PORT161_SCIFB_CTS_, GPIO_FN_PORT161_SCIFA5_CTS_, | ||
| 268 | GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD, | ||
| 269 | GPIO_FN_PORT163_SCIFB_RTS_, GPIO_FN_PORT163_SCIFA5_RTS_, \ | ||
| 270 | GPIO_FN_TPU3TO0, | ||
| 271 | GPIO_FN_LCDD0, | ||
| 272 | GPIO_FN_LCDD1, GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1, | ||
| 273 | GPIO_FN_LCDD2, GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1, | ||
| 274 | GPIO_FN_LCDD3, GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1, | ||
| 275 | GPIO_FN_LCDD4, GPIO_FN_PORT196_SCIFA5_TXD, | ||
| 276 | GPIO_FN_LCDD5, GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2, \ | ||
| 277 | GPIO_FN_TPU2TO1, | ||
| 278 | GPIO_FN_LCDD6, | ||
| 279 | GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2, | ||
| 280 | GPIO_FN_LCDD8, GPIO_FN_D16, | ||
| 281 | GPIO_FN_LCDD9, GPIO_FN_D17, | ||
| 282 | GPIO_FN_LCDD10, GPIO_FN_D18, | ||
| 283 | GPIO_FN_LCDD11, GPIO_FN_D19, | ||
| 284 | GPIO_FN_LCDD12, GPIO_FN_D20, | ||
| 285 | GPIO_FN_LCDD13, GPIO_FN_D21, | ||
| 286 | GPIO_FN_LCDD14, GPIO_FN_D22, | ||
| 287 | GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23, | ||
| 288 | GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24, | ||
| 289 | GPIO_FN_LCDD17, GPIO_FN_D25, | ||
| 290 | GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26, | ||
| 291 | GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27, | ||
| 292 | GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28, | ||
| 293 | GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29, | ||
| 294 | GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30, | ||
| 295 | GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31, | ||
| 296 | GPIO_FN_LCDDCK, GPIO_FN_LCDWR_, | ||
| 297 | GPIO_FN_LCDRD_, GPIO_FN_DACK2, GPIO_FN_PORT217_LCD2RS, \ | ||
| 298 | GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, GPIO_FN_PORT217_LCD2DISP, | ||
| 299 | GPIO_FN_LCDHSYN, GPIO_FN_LCDCS_, GPIO_FN_LCDCS2_, GPIO_FN_DACK3, \ | ||
| 300 | GPIO_FN_PORT218_VIO_CKOR, | ||
| 301 | GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_PORT219_LCD2WR_, \ | ||
| 302 | GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \ | ||
| 303 | GPIO_FN_LCD2DCK_2, | ||
| 304 | GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2, | ||
| 305 | GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PORT221_LCD2CS_, \ | ||
| 306 | GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \ | ||
| 307 | GPIO_FN_PORT221_LCD2HSYN, | ||
| 308 | GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, \ | ||
| 309 | GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, GPIO_FN_PORT222_LCD2VSYN, | ||
| 310 | |||
| 311 | GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2, | ||
| 312 | GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_PORT226_VIO_CKO2, | ||
| 313 | GPIO_FN_SCIFA1_RTS_, GPIO_FN_IDIN, | ||
| 314 | GPIO_FN_SCIFA1_RXD, | ||
| 315 | GPIO_FN_SCIFA1_CTS_, GPIO_FN_MFG1_IN1, | ||
| 316 | GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2, | ||
| 317 | GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2_, | ||
| 318 | GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2, | ||
| 319 | GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2, | ||
| 320 | GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2_, GPIO_FN_VIO2_CLK2, \ | ||
| 321 | GPIO_FN_LCD2D20, | ||
| 322 | GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \ | ||
| 323 | GPIO_FN_LCD2D21, | ||
| 324 | GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2, | ||
| 325 | GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2, | ||
| 326 | GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_LCD2D22, | ||
| 327 | GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, GPIO_FN_LCD2D23, | ||
| 328 | GPIO_FN_SCIFA6_TXD, | ||
| 329 | GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \ | ||
| 330 | GPIO_FN_TPU4TO0, | ||
| 331 | GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2, | ||
| 332 | GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2, | ||
| 333 | GPIO_FN_PORT244_SCIFA5_CTS_, GPIO_FN_MFG2_IN1, \ | ||
| 334 | GPIO_FN_PORT244_SCIFB_CTS_, GPIO_FN_MSIOF2R_RXD, | ||
| 335 | GPIO_FN_PORT245_SCIFA5_RTS_, GPIO_FN_MFG2_IN2, \ | ||
| 336 | GPIO_FN_PORT245_SCIFB_RTS_, GPIO_FN_MSIOF2R_TXD, | ||
| 337 | GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, \ | ||
| 338 | GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0, | ||
| 339 | GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, \ | ||
| 340 | GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1, | ||
| 341 | GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, \ | ||
| 342 | GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, \ | ||
| 343 | GPIO_FN_PORT248_I2C_SCL3, GPIO_FN_MSIOF2R_TSCK, | ||
| 344 | GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \ | ||
| 345 | GPIO_FN_PORT249_I2C_SDA3, GPIO_FN_MSIOF2R_TSYNC, | ||
| 346 | GPIO_FN_SDHICLK0, | ||
| 347 | GPIO_FN_SDHICD0, | ||
| 348 | GPIO_FN_SDHID0_0, | ||
| 349 | GPIO_FN_SDHID0_1, | ||
| 350 | GPIO_FN_SDHID0_2, | ||
| 351 | GPIO_FN_SDHID0_3, | ||
| 352 | GPIO_FN_SDHICMD0, | ||
| 353 | GPIO_FN_SDHIWP0, | ||
| 354 | GPIO_FN_SDHICLK1, | ||
| 355 | GPIO_FN_SDHID1_0, GPIO_FN_TS_SPSYNC2, | ||
| 356 | GPIO_FN_SDHID1_1, GPIO_FN_TS_SDAT2, | ||
| 357 | GPIO_FN_SDHID1_2, GPIO_FN_TS_SDEN2, | ||
| 358 | GPIO_FN_SDHID1_3, GPIO_FN_TS_SCK2, | ||
| 359 | GPIO_FN_SDHICMD1, | ||
| 360 | GPIO_FN_SDHICLK2, | ||
| 361 | GPIO_FN_SDHID2_0, GPIO_FN_TS_SPSYNC4, | ||
| 362 | GPIO_FN_SDHID2_1, GPIO_FN_TS_SDAT4, | ||
| 363 | GPIO_FN_SDHID2_2, GPIO_FN_TS_SDEN4, | ||
| 364 | GPIO_FN_SDHID2_3, GPIO_FN_TS_SCK4, | ||
| 365 | GPIO_FN_SDHICMD2, | ||
| 366 | GPIO_FN_MMCCLK0, | ||
| 367 | GPIO_FN_MMCD0_0, | ||
| 368 | GPIO_FN_MMCD0_1, | ||
| 369 | GPIO_FN_MMCD0_2, | ||
| 370 | GPIO_FN_MMCD0_3, | ||
| 371 | GPIO_FN_MMCD0_4, GPIO_FN_TS_SPSYNC5, | ||
| 372 | GPIO_FN_MMCD0_5, GPIO_FN_TS_SDAT5, | ||
| 373 | GPIO_FN_MMCD0_6, GPIO_FN_TS_SDEN5, | ||
| 374 | GPIO_FN_MMCD0_7, GPIO_FN_TS_SCK5, | ||
| 375 | GPIO_FN_MMCCMD0, | ||
| 376 | GPIO_FN_RESETOUTS_, GPIO_FN_EXTAL2OUT, | ||
| 377 | GPIO_FN_MCP_WAIT__MCP_FRB, | ||
| 378 | GPIO_FN_MCP_CKO, GPIO_FN_MMCCLK1, | ||
| 379 | GPIO_FN_MCP_D15_MCP_NAF15, | ||
| 380 | GPIO_FN_MCP_D14_MCP_NAF14, | ||
| 381 | GPIO_FN_MCP_D13_MCP_NAF13, | ||
| 382 | GPIO_FN_MCP_D12_MCP_NAF12, | ||
| 383 | GPIO_FN_MCP_D11_MCP_NAF11, | ||
| 384 | GPIO_FN_MCP_D10_MCP_NAF10, | ||
| 385 | GPIO_FN_MCP_D9_MCP_NAF9, | ||
| 386 | GPIO_FN_MCP_D8_MCP_NAF8, GPIO_FN_MMCCMD1, | ||
| 387 | GPIO_FN_MCP_D7_MCP_NAF7, GPIO_FN_MMCD1_7, | ||
| 388 | |||
| 389 | GPIO_FN_MCP_D6_MCP_NAF6, GPIO_FN_MMCD1_6, | ||
| 390 | GPIO_FN_MCP_D5_MCP_NAF5, GPIO_FN_MMCD1_5, | ||
| 391 | GPIO_FN_MCP_D4_MCP_NAF4, GPIO_FN_MMCD1_4, | ||
| 392 | GPIO_FN_MCP_D3_MCP_NAF3, GPIO_FN_MMCD1_3, | ||
| 393 | GPIO_FN_MCP_D2_MCP_NAF2, GPIO_FN_MMCD1_2, | ||
| 394 | GPIO_FN_MCP_D1_MCP_NAF1, GPIO_FN_MMCD1_1, | ||
| 395 | GPIO_FN_MCP_D0_MCP_NAF0, GPIO_FN_MMCD1_0, | ||
| 396 | GPIO_FN_MCP_NBRSTOUT_, | ||
| 397 | GPIO_FN_MCP_WE0__MCP_FWE, GPIO_FN_MCP_RDWR_MCP_FWE, | ||
| 398 | |||
| 399 | /* MSEL2 special case */ | ||
| 400 | GPIO_FN_TSIF2_TS_XX1, | ||
| 401 | GPIO_FN_TSIF2_TS_XX2, | ||
| 402 | GPIO_FN_TSIF2_TS_XX3, | ||
| 403 | GPIO_FN_TSIF2_TS_XX4, | ||
| 404 | GPIO_FN_TSIF2_TS_XX5, | ||
| 405 | GPIO_FN_TSIF1_TS_XX1, | ||
| 406 | GPIO_FN_TSIF1_TS_XX2, | ||
| 407 | GPIO_FN_TSIF1_TS_XX3, | ||
| 408 | GPIO_FN_TSIF1_TS_XX4, | ||
| 409 | GPIO_FN_TSIF1_TS_XX5, | ||
| 410 | GPIO_FN_TSIF0_TS_XX1, | ||
| 411 | GPIO_FN_TSIF0_TS_XX2, | ||
| 412 | GPIO_FN_TSIF0_TS_XX3, | ||
| 413 | GPIO_FN_TSIF0_TS_XX4, | ||
| 414 | GPIO_FN_TSIF0_TS_XX5, | ||
| 415 | GPIO_FN_MST1_TS_XX1, | ||
| 416 | GPIO_FN_MST1_TS_XX2, | ||
| 417 | GPIO_FN_MST1_TS_XX3, | ||
| 418 | GPIO_FN_MST1_TS_XX4, | ||
| 419 | GPIO_FN_MST1_TS_XX5, | ||
| 420 | GPIO_FN_MST0_TS_XX1, | ||
| 421 | GPIO_FN_MST0_TS_XX2, | ||
| 422 | GPIO_FN_MST0_TS_XX3, | ||
| 423 | GPIO_FN_MST0_TS_XX4, | ||
| 424 | GPIO_FN_MST0_TS_XX5, | ||
| 425 | |||
| 426 | /* MSEL3 special cases */ | ||
| 427 | GPIO_FN_SDHI0_VCCQ_MC0_ON, | ||
| 428 | GPIO_FN_SDHI0_VCCQ_MC0_OFF, | ||
| 429 | GPIO_FN_DEBUG_MON_VIO, | ||
| 430 | GPIO_FN_DEBUG_MON_LCDD, | ||
| 431 | GPIO_FN_LCDC_LCDC0, | ||
| 432 | GPIO_FN_LCDC_LCDC1, | ||
| 433 | |||
| 434 | /* MSEL4 special cases */ | ||
| 435 | GPIO_FN_IRQ9_MEM_INT, | ||
| 436 | GPIO_FN_IRQ9_MCP_INT, | ||
| 437 | GPIO_FN_A11, | ||
| 438 | GPIO_FN_KEYOUT8, | ||
| 439 | GPIO_FN_TPU4TO3, | ||
| 440 | GPIO_FN_RESETA_N_PU_ON, | ||
| 441 | GPIO_FN_RESETA_N_PU_OFF, | ||
| 442 | GPIO_FN_EDBGREQ_PD, | ||
| 443 | GPIO_FN_EDBGREQ_PU, | ||
| 444 | |||
| 445 | /* Functions with pull-ups */ | ||
| 446 | GPIO_FN_KEYIN0_PU, | ||
| 447 | GPIO_FN_KEYIN1_PU, | ||
| 448 | GPIO_FN_KEYIN2_PU, | ||
| 449 | GPIO_FN_KEYIN3_PU, | ||
| 450 | GPIO_FN_KEYIN4_PU, | ||
| 451 | GPIO_FN_KEYIN5_PU, | ||
| 452 | GPIO_FN_KEYIN6_PU, | ||
| 453 | GPIO_FN_KEYIN7_PU, | ||
| 454 | GPIO_FN_SDHID1_0_PU, | ||
| 455 | GPIO_FN_SDHID1_1_PU, | ||
| 456 | GPIO_FN_SDHID1_2_PU, | ||
| 457 | GPIO_FN_SDHID1_3_PU, | ||
| 458 | GPIO_FN_SDHICMD1_PU, | ||
| 459 | GPIO_FN_MMCCMD0_PU, | ||
| 460 | GPIO_FN_MMCCMD1_PU, | ||
| 461 | GPIO_FN_FSIACK_PU, | ||
| 462 | GPIO_FN_FSIAILR_PU, | ||
| 463 | GPIO_FN_FSIAIBT_PU, | ||
| 464 | GPIO_FN_FSIAISLD_PU, | ||
| 465 | }; | ||
| 466 | |||
| 467 | #endif /* __ASM_SH73A0_H__ */ | ||
diff --git a/arch/arm/mach-shmobile/include/mach/smp.h b/arch/arm/mach-shmobile/include/mach/smp.h new file mode 100644 index 000000000000..50db94e927ad --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/smp.h | |||
| @@ -0,0 +1,16 @@ | |||
| 1 | #ifndef __MACH_SMP_H | ||
| 2 | #define __MACH_SMP_H | ||
| 3 | |||
| 4 | #include <asm/hardware/gic.h> | ||
| 5 | |||
| 6 | /* | ||
| 7 | * We use IRQ1 as the IPI | ||
| 8 | */ | ||
| 9 | static inline void smp_cross_call(const struct cpumask *mask, int ipi) | ||
| 10 | { | ||
| 11 | #if defined(CONFIG_ARM_GIC) | ||
| 12 | gic_raise_softirq(mask, ipi); | ||
| 13 | #endif | ||
| 14 | } | ||
| 15 | |||
| 16 | #endif | ||
diff --git a/arch/arm/mach-shmobile/include/mach/zboot.h b/arch/arm/mach-shmobile/include/mach/zboot.h new file mode 100644 index 000000000000..6d6a205bcf90 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/zboot.h | |||
| @@ -0,0 +1,23 @@ | |||
| 1 | #ifndef ZBOOT_H | ||
| 2 | #define ZBOOT_H | ||
| 3 | |||
| 4 | #include <asm/mach-types.h> | ||
| 5 | #include <mach/zboot_macros.h> | ||
| 6 | |||
| 7 | /************************************************** | ||
| 8 | * | ||
| 9 | * board specific settings | ||
| 10 | * | ||
| 11 | **************************************************/ | ||
| 12 | |||
| 13 | #ifdef CONFIG_MACH_AP4EVB | ||
| 14 | #define MACH_TYPE MACH_TYPE_AP4EVB | ||
| 15 | #include "mach/head-ap4evb.txt" | ||
| 16 | #elif CONFIG_MACH_MACKEREL | ||
| 17 | #define MACH_TYPE MACH_TYPE_MACKEREL | ||
| 18 | #include "mach/head-mackerel.txt" | ||
| 19 | #else | ||
| 20 | #error "unsupported board." | ||
| 21 | #endif | ||
| 22 | |||
| 23 | #endif /* ZBOOT_H */ | ||
diff --git a/arch/arm/mach-shmobile/include/mach/zboot_macros.h b/arch/arm/mach-shmobile/include/mach/zboot_macros.h new file mode 100644 index 000000000000..aa6111fbc989 --- /dev/null +++ b/arch/arm/mach-shmobile/include/mach/zboot_macros.h | |||
| @@ -0,0 +1,65 @@ | |||
| 1 | #ifndef __ZBOOT_MACRO_H | ||
| 2 | #define __ZBOOT_MACRO_H | ||
| 3 | |||
| 4 | /* The LIST command is used to include comments in the script */ | ||
| 5 | .macro LIST comment | ||
| 6 | .endm | ||
| 7 | |||
| 8 | /* The ED command is used to write a 32-bit word */ | ||
| 9 | .macro ED, addr, data | ||
| 10 | LDR r0, 1f | ||
| 11 | LDR r1, 2f | ||
| 12 | STR r1, [r0] | ||
| 13 | B 3f | ||
| 14 | 1 : .long \addr | ||
| 15 | 2 : .long \data | ||
| 16 | 3 : | ||
| 17 | .endm | ||
| 18 | |||
| 19 | /* The EW command is used to write a 16-bit word */ | ||
| 20 | .macro EW, addr, data | ||
| 21 | LDR r0, 1f | ||
| 22 | LDR r1, 2f | ||
| 23 | STRH r1, [r0] | ||
| 24 | B 3f | ||
| 25 | 1 : .long \addr | ||
| 26 | 2 : .long \data | ||
| 27 | 3 : | ||
| 28 | .endm | ||
| 29 | |||
| 30 | /* The EB command is used to write an 8-bit word */ | ||
| 31 | .macro EB, addr, data | ||
| 32 | LDR r0, 1f | ||
| 33 | LDR r1, 2f | ||
| 34 | STRB r1, [r0] | ||
| 35 | B 3f | ||
| 36 | 1 : .long \addr | ||
| 37 | 2 : .long \data | ||
| 38 | 3 : | ||
| 39 | .endm | ||
| 40 | |||
| 41 | /* The WAIT command is used to delay the execution */ | ||
| 42 | .macro WAIT, time, reg | ||
| 43 | LDR r1, 1f | ||
| 44 | LDR r0, 2f | ||
| 45 | STR r0, [r1] | ||
| 46 | 10 : | ||
| 47 | LDR r0, [r1] | ||
| 48 | CMP r0, #0x00000000 | ||
| 49 | BNE 10b | ||
| 50 | NOP | ||
| 51 | B 3f | ||
| 52 | 1 : .long \reg | ||
| 53 | 2 : .long \time * 100 | ||
| 54 | 3 : | ||
| 55 | .endm | ||
| 56 | |||
| 57 | /* The DD command is used to read a 32-bit word */ | ||
| 58 | .macro DD, start, end | ||
| 59 | LDR r1, 1f | ||
| 60 | B 2f | ||
| 61 | 1 : .long \start | ||
| 62 | 2 : | ||
| 63 | .endm | ||
| 64 | |||
| 65 | #endif /* __ZBOOT_MACRO_H */ | ||
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c new file mode 100644 index 000000000000..322d8d57cbcf --- /dev/null +++ b/arch/arm/mach-shmobile/intc-sh73a0.c | |||
| @@ -0,0 +1,267 @@ | |||
| 1 | /* | ||
| 2 | * sh73a0 processor support - INTC hardware block | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Magnus Damm | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; version 2 of the License. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 18 | */ | ||
| 19 | #include <linux/kernel.h> | ||
| 20 | #include <linux/init.h> | ||
| 21 | #include <linux/interrupt.h> | ||
| 22 | #include <linux/irq.h> | ||
| 23 | #include <linux/io.h> | ||
| 24 | #include <linux/sh_intc.h> | ||
| 25 | #include <asm/hardware/gic.h> | ||
| 26 | #include <asm/mach-types.h> | ||
| 27 | #include <asm/mach/arch.h> | ||
| 28 | |||
| 29 | enum { | ||
| 30 | UNUSED = 0, | ||
| 31 | |||
| 32 | /* interrupt sources INTCS */ | ||
| 33 | PINTCS_PINT1, PINTCS_PINT2, | ||
| 34 | RTDMAC_0_DEI0, RTDMAC_0_DEI1, RTDMAC_0_DEI2, RTDMAC_0_DEI3, | ||
| 35 | CEU, MFI, BBIF2, VPU, TSIF1, _3DG_SGX543, _2DDMAC_2DDM0, | ||
| 36 | RTDMAC_1_DEI4, RTDMAC_1_DEI5, RTDMAC_1_DADERR, | ||
| 37 | KEYSC_KEY, VINT, MSIOF, | ||
| 38 | TMU0_TUNI00, TMU0_TUNI01, TMU0_TUNI02, | ||
| 39 | CMT0, TSIF0, CMT2, LMB, MSUG, MSU_MSU, MSU_MSU2, | ||
| 40 | CTI, RWDT0, ICB, PEP, ASA, JPU_JPEG, LCDC, LCRC, | ||
| 41 | RTDMAC_2_DEI6, RTDMAC_2_DEI7, RTDMAC_2_DEI8, RTDMAC_2_DEI9, | ||
| 42 | RTDMAC_3_DEI10, RTDMAC_3_DEI11, | ||
| 43 | FRC, GCU, LCDC1, CSIRX, | ||
| 44 | DSITX0_DSITX00, DSITX0_DSITX01, | ||
| 45 | SPU2_SPU0, SPU2_SPU1, FSI, | ||
| 46 | TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, | ||
| 47 | TSIF2, CMT4, MFIS2, CPORTS2R, TSG, DMASCH1, SCUW, | ||
| 48 | VIO60, VIO61, CEU21, CSI21, DSITX1_DSITX10, DSITX1_DSITX11, | ||
| 49 | DISP, DSRV, EMUX2_EMUX20I, EMUX2_EMUX21I, | ||
| 50 | MSTIF0_MST00I, MSTIF0_MST01I, MSTIF1_MST10I, MSTIF1_MST11I, | ||
| 51 | SPUV, | ||
| 52 | |||
| 53 | /* interrupt groups INTCS */ | ||
| 54 | RTDMAC_0, RTDMAC_1, RTDMAC_2, RTDMAC_3, | ||
| 55 | DSITX0, SPU2, TMU1, MSU, | ||
| 56 | }; | ||
| 57 | |||
| 58 | static struct intc_vect intcs_vectors[] = { | ||
| 59 | INTCS_VECT(PINTCS_PINT1, 0x0600), INTCS_VECT(PINTCS_PINT2, 0x0620), | ||
| 60 | INTCS_VECT(RTDMAC_0_DEI0, 0x0800), INTCS_VECT(RTDMAC_0_DEI1, 0x0820), | ||
| 61 | INTCS_VECT(RTDMAC_0_DEI2, 0x0840), INTCS_VECT(RTDMAC_0_DEI3, 0x0860), | ||
| 62 | INTCS_VECT(CEU, 0x0880), INTCS_VECT(MFI, 0x0900), | ||
| 63 | INTCS_VECT(BBIF2, 0x0960), INTCS_VECT(VPU, 0x0980), | ||
| 64 | INTCS_VECT(TSIF1, 0x09a0), INTCS_VECT(_3DG_SGX543, 0x09e0), | ||
| 65 | INTCS_VECT(_2DDMAC_2DDM0, 0x0a00), | ||
| 66 | INTCS_VECT(RTDMAC_1_DEI4, 0x0b80), INTCS_VECT(RTDMAC_1_DEI5, 0x0ba0), | ||
| 67 | INTCS_VECT(RTDMAC_1_DADERR, 0x0bc0), | ||
| 68 | INTCS_VECT(KEYSC_KEY, 0x0be0), INTCS_VECT(VINT, 0x0c80), | ||
| 69 | INTCS_VECT(MSIOF, 0x0d20), | ||
| 70 | INTCS_VECT(TMU0_TUNI00, 0x0e80), INTCS_VECT(TMU0_TUNI01, 0x0ea0), | ||
| 71 | INTCS_VECT(TMU0_TUNI02, 0x0ec0), | ||
| 72 | INTCS_VECT(CMT0, 0x0f00), INTCS_VECT(TSIF0, 0x0f20), | ||
| 73 | INTCS_VECT(CMT2, 0x0f40), INTCS_VECT(LMB, 0x0f60), | ||
| 74 | INTCS_VECT(MSUG, 0x0f80), | ||
| 75 | INTCS_VECT(MSU_MSU, 0x0fa0), INTCS_VECT(MSU_MSU2, 0x0fc0), | ||
| 76 | INTCS_VECT(CTI, 0x0400), INTCS_VECT(RWDT0, 0x0440), | ||
| 77 | INTCS_VECT(ICB, 0x0480), INTCS_VECT(PEP, 0x04a0), | ||
| 78 | INTCS_VECT(ASA, 0x04c0), INTCS_VECT(JPU_JPEG, 0x0560), | ||
| 79 | INTCS_VECT(LCDC, 0x0580), INTCS_VECT(LCRC, 0x05a0), | ||
| 80 | INTCS_VECT(RTDMAC_2_DEI6, 0x1300), INTCS_VECT(RTDMAC_2_DEI7, 0x1320), | ||
| 81 | INTCS_VECT(RTDMAC_2_DEI8, 0x1340), INTCS_VECT(RTDMAC_2_DEI9, 0x1360), | ||
| 82 | INTCS_VECT(RTDMAC_3_DEI10, 0x1380), INTCS_VECT(RTDMAC_3_DEI11, 0x13a0), | ||
| 83 | INTCS_VECT(FRC, 0x1700), INTCS_VECT(GCU, 0x1760), | ||
| 84 | INTCS_VECT(LCDC1, 0x1780), INTCS_VECT(CSIRX, 0x17a0), | ||
| 85 | INTCS_VECT(DSITX0_DSITX00, 0x17c0), INTCS_VECT(DSITX0_DSITX01, 0x17e0), | ||
| 86 | INTCS_VECT(SPU2_SPU0, 0x1800), INTCS_VECT(SPU2_SPU1, 0x1820), | ||
| 87 | INTCS_VECT(FSI, 0x1840), | ||
| 88 | INTCS_VECT(TMU1_TUNI10, 0x1900), INTCS_VECT(TMU1_TUNI11, 0x1920), | ||
| 89 | INTCS_VECT(TMU1_TUNI12, 0x1940), | ||
| 90 | INTCS_VECT(TSIF2, 0x1960), INTCS_VECT(CMT4, 0x1980), | ||
| 91 | INTCS_VECT(MFIS2, 0x1a00), INTCS_VECT(CPORTS2R, 0x1a20), | ||
| 92 | INTCS_VECT(TSG, 0x1ae0), INTCS_VECT(DMASCH1, 0x1b00), | ||
| 93 | INTCS_VECT(SCUW, 0x1b40), | ||
| 94 | INTCS_VECT(VIO60, 0x1b60), INTCS_VECT(VIO61, 0x1b80), | ||
| 95 | INTCS_VECT(CEU21, 0x1ba0), INTCS_VECT(CSI21, 0x1be0), | ||
| 96 | INTCS_VECT(DSITX1_DSITX10, 0x1c00), INTCS_VECT(DSITX1_DSITX11, 0x1c20), | ||
| 97 | INTCS_VECT(DISP, 0x1c40), INTCS_VECT(DSRV, 0x1c60), | ||
| 98 | INTCS_VECT(EMUX2_EMUX20I, 0x1c80), INTCS_VECT(EMUX2_EMUX21I, 0x1ca0), | ||
| 99 | INTCS_VECT(MSTIF0_MST00I, 0x1cc0), INTCS_VECT(MSTIF0_MST01I, 0x1ce0), | ||
| 100 | INTCS_VECT(MSTIF1_MST10I, 0x1d00), INTCS_VECT(MSTIF1_MST11I, 0x1d20), | ||
| 101 | INTCS_VECT(SPUV, 0x2300), | ||
| 102 | }; | ||
| 103 | |||
| 104 | static struct intc_group intcs_groups[] __initdata = { | ||
| 105 | INTC_GROUP(RTDMAC_0, RTDMAC_0_DEI0, RTDMAC_0_DEI1, | ||
| 106 | RTDMAC_0_DEI2, RTDMAC_0_DEI3), | ||
| 107 | INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI4, RTDMAC_1_DEI5, RTDMAC_1_DADERR), | ||
| 108 | INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI6, RTDMAC_2_DEI7, | ||
| 109 | RTDMAC_2_DEI8, RTDMAC_2_DEI9), | ||
| 110 | INTC_GROUP(RTDMAC_3, RTDMAC_3_DEI10, RTDMAC_3_DEI11), | ||
| 111 | INTC_GROUP(TMU1, TMU1_TUNI12, TMU1_TUNI11, TMU1_TUNI10), | ||
| 112 | INTC_GROUP(DSITX0, DSITX0_DSITX00, DSITX0_DSITX01), | ||
| 113 | INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1), | ||
| 114 | INTC_GROUP(MSU, MSU_MSU, MSU_MSU2), | ||
| 115 | }; | ||
| 116 | |||
| 117 | static struct intc_mask_reg intcs_mask_registers[] = { | ||
| 118 | { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */ | ||
| 119 | { 0, 0, 0, CEU, | ||
| 120 | 0, 0, 0, 0 } }, | ||
| 121 | { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */ | ||
| 122 | { 0, 0, 0, VPU, | ||
| 123 | BBIF2, 0, 0, MFI } }, | ||
| 124 | { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */ | ||
| 125 | { 0, 0, 0, _2DDMAC_2DDM0, | ||
| 126 | 0, ASA, PEP, ICB } }, | ||
| 127 | { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */ | ||
| 128 | { 0, 0, 0, CTI, | ||
| 129 | JPU_JPEG, 0, LCRC, LCDC } }, | ||
| 130 | { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */ | ||
| 131 | { KEYSC_KEY, RTDMAC_1_DADERR, RTDMAC_1_DEI5, RTDMAC_1_DEI4, | ||
| 132 | RTDMAC_0_DEI3, RTDMAC_0_DEI2, RTDMAC_0_DEI1, RTDMAC_0_DEI0 } }, | ||
| 133 | { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */ | ||
| 134 | { 0, 0, MSIOF, 0, | ||
| 135 | _3DG_SGX543, 0, 0, 0 } }, | ||
| 136 | { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */ | ||
| 137 | { 0, TMU0_TUNI02, TMU0_TUNI01, TMU0_TUNI00, | ||
| 138 | 0, 0, 0, 0 } }, | ||
| 139 | { 0xffd201a0, 0xffd201e0, 8, /* IMR8SA / IMCR8SA */ | ||
| 140 | { 0, 0, 0, 0, | ||
| 141 | 0, MSU_MSU, MSU_MSU2, MSUG } }, | ||
| 142 | { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */ | ||
| 143 | { 0, RWDT0, CMT2, CMT0, | ||
| 144 | 0, 0, 0, 0 } }, | ||
| 145 | { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */ | ||
| 146 | { 0, 0, 0, 0, | ||
| 147 | 0, TSIF1, LMB, TSIF0 } }, | ||
| 148 | { 0xffd201b0, 0xffd201f0, 8, /* IMR12SA / IMCR12SA */ | ||
| 149 | { 0, 0, 0, 0, | ||
| 150 | 0, 0, PINTCS_PINT2, PINTCS_PINT1 } }, | ||
| 151 | { 0xffd50180, 0xffd501c0, 8, /* IMR0SA3 / IMCR0SA3 */ | ||
| 152 | { RTDMAC_2_DEI6, RTDMAC_2_DEI7, RTDMAC_2_DEI8, RTDMAC_2_DEI9, | ||
| 153 | RTDMAC_3_DEI10, RTDMAC_3_DEI11, 0, 0 } }, | ||
| 154 | { 0xffd50190, 0xffd501d0, 8, /* IMR4SA3 / IMCR4SA3 */ | ||
| 155 | { FRC, 0, 0, GCU, | ||
| 156 | LCDC1, CSIRX, DSITX0_DSITX00, DSITX0_DSITX01 } }, | ||
| 157 | { 0xffd50194, 0xffd501d4, 8, /* IMR5SA3 / IMCR5SA3 */ | ||
| 158 | { SPU2_SPU0, SPU2_SPU1, FSI, 0, | ||
| 159 | 0, 0, 0, 0 } }, | ||
| 160 | { 0xffd50198, 0xffd501d8, 8, /* IMR6SA3 / IMCR6SA3 */ | ||
| 161 | { TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, 0, | ||
| 162 | TSIF2, CMT4, 0, 0 } }, | ||
| 163 | { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */ | ||
| 164 | { MFIS2, CPORTS2R, 0, 0, | ||
| 165 | 0, 0, 0, TSG } }, | ||
| 166 | { 0xffd501a0, 0xffd501e0, 8, /* IMR8SA3 / IMCR8SA3 */ | ||
| 167 | { DMASCH1, 0, SCUW, VIO60, | ||
| 168 | VIO61, CEU21, 0, CSI21 } }, | ||
| 169 | { 0xffd501a4, 0xffd501e4, 8, /* IMR9SA3 / IMCR9SA3 */ | ||
| 170 | { DSITX1_DSITX10, DSITX1_DSITX11, DISP, DSRV, | ||
| 171 | EMUX2_EMUX20I, EMUX2_EMUX21I, MSTIF0_MST00I, MSTIF0_MST01I } }, | ||
| 172 | { 0xffd501a8, 0xffd501e8, 8, /* IMR10SA3 / IMCR10SA3 */ | ||
| 173 | { MSTIF0_MST00I, MSTIF0_MST01I, 0, 0, | ||
| 174 | 0, 0, 0, 0 } }, | ||
| 175 | { 0xffd60180, 0xffd601c0, 8, /* IMR0SA4 / IMCR0SA4 */ | ||
| 176 | { SPUV, 0, 0, 0, | ||
| 177 | 0, 0, 0, 0 } }, | ||
| 178 | }; | ||
| 179 | |||
| 180 | /* Priority is needed for INTCA to receive the INTCS interrupt */ | ||
| 181 | static struct intc_prio_reg intcs_prio_registers[] = { | ||
| 182 | { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC_2DDM0, ICB } }, | ||
| 183 | { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU_JPEG, LCDC, 0, LCRC } }, | ||
| 184 | { 0xffd20008, 0, 16, 4, /* IPRCS */ { BBIF2, 0, 0, 0 } }, | ||
| 185 | { 0xffd2000c, 0, 16, 4, /* IPRDS */ { PINTCS_PINT1, PINTCS_PINT2, | ||
| 186 | 0, 0 } }, | ||
| 187 | { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_0, CEU, MFI, VPU } }, | ||
| 188 | { 0xffd20014, 0, 16, 4, /* IPRFS */ { KEYSC_KEY, RTDMAC_1, | ||
| 189 | CMT2, CMT0 } }, | ||
| 190 | { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_TUNI00, TMU0_TUNI01, | ||
| 191 | TMU0_TUNI02, TSIF1 } }, | ||
| 192 | { 0xffd2001c, 0, 16, 4, /* IPRHS */ { VINT, 0, 0, 0 } }, | ||
| 193 | { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, 0 } }, | ||
| 194 | { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, _3DG_SGX543, MSUG, MSU } }, | ||
| 195 | { 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, ASA, LMB, PEP } }, | ||
| 196 | { 0xffd20030, 0, 16, 4, /* IPRMS */ { 0, 0, 0, RWDT0 } }, | ||
| 197 | { 0xffd50000, 0, 16, 4, /* IPRAS3 */ { RTDMAC_2, 0, 0, 0 } }, | ||
| 198 | { 0xffd50004, 0, 16, 4, /* IPRBS3 */ { RTDMAC_3, 0, 0, 0 } }, | ||
| 199 | { 0xffd50020, 0, 16, 4, /* IPRIS3 */ { FRC, 0, 0, 0 } }, | ||
| 200 | { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, CSIRX, DSITX0, 0 } }, | ||
| 201 | { 0xffd50028, 0, 16, 4, /* IPRKS3 */ { SPU2, 0, FSI, 0 } }, | ||
| 202 | { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, TSIF2 } }, | ||
| 203 | { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, 0, 0, 0 } }, | ||
| 204 | { 0xffd50038, 0, 16, 4, /* IPROS3 */ { MFIS2, CPORTS2R, 0, 0 } }, | ||
| 205 | { 0xffd50040, 0, 16, 4, /* IPRQS3 */ { DMASCH1, 0, SCUW, VIO60 } }, | ||
| 206 | { 0xffd50044, 0, 16, 4, /* IPRRS3 */ { VIO61, CEU21, 0, CSI21 } }, | ||
| 207 | { 0xffd50048, 0, 16, 4, /* IPRSS3 */ { DSITX1_DSITX10, DSITX1_DSITX11, | ||
| 208 | DISP, DSRV } }, | ||
| 209 | { 0xffd5004c, 0, 16, 4, /* IPRTS3 */ { EMUX2_EMUX20I, EMUX2_EMUX21I, | ||
| 210 | MSTIF0_MST00I, MSTIF0_MST01I } }, | ||
| 211 | { 0xffd50050, 0, 16, 4, /* IPRUS3 */ { MSTIF1_MST10I, MSTIF1_MST11I, | ||
| 212 | 0, 0 } }, | ||
| 213 | { 0xffd60000, 0, 16, 4, /* IPRAS4 */ { SPUV, 0, 0, 0 } }, | ||
| 214 | }; | ||
| 215 | |||
| 216 | static struct resource intcs_resources[] __initdata = { | ||
| 217 | [0] = { | ||
| 218 | .start = 0xffd20000, | ||
| 219 | .end = 0xffd201ff, | ||
| 220 | .flags = IORESOURCE_MEM, | ||
| 221 | }, | ||
| 222 | [1] = { | ||
| 223 | .start = 0xffd50000, | ||
| 224 | .end = 0xffd501ff, | ||
| 225 | .flags = IORESOURCE_MEM, | ||
| 226 | }, | ||
| 227 | [2] = { | ||
| 228 | .start = 0xffd60000, | ||
| 229 | .end = 0xffd601ff, | ||
| 230 | .flags = IORESOURCE_MEM, | ||
| 231 | } | ||
| 232 | }; | ||
| 233 | |||
| 234 | static struct intc_desc intcs_desc __initdata = { | ||
| 235 | .name = "sh73a0-intcs", | ||
| 236 | .resource = intcs_resources, | ||
| 237 | .num_resources = ARRAY_SIZE(intcs_resources), | ||
| 238 | .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers, | ||
| 239 | intcs_prio_registers, NULL, NULL), | ||
| 240 | }; | ||
| 241 | |||
| 242 | static struct irqaction sh73a0_intcs_cascade; | ||
| 243 | |||
| 244 | static irqreturn_t sh73a0_intcs_demux(int irq, void *dev_id) | ||
| 245 | { | ||
| 246 | unsigned int evtcodeas = ioread32((void __iomem *)dev_id); | ||
| 247 | |||
| 248 | generic_handle_irq(intcs_evt2irq(evtcodeas)); | ||
| 249 | |||
| 250 | return IRQ_HANDLED; | ||
| 251 | } | ||
| 252 | |||
| 253 | void __init sh73a0_init_irq(void) | ||
| 254 | { | ||
| 255 | void __iomem *gic_base = __io(0xf0001000); | ||
| 256 | void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); | ||
| 257 | |||
| 258 | gic_init(0, 29, gic_base, gic_base); | ||
| 259 | |||
| 260 | register_intc_controller(&intcs_desc); | ||
| 261 | |||
| 262 | /* demux using INTEVTSA */ | ||
| 263 | sh73a0_intcs_cascade.name = "INTCS cascade"; | ||
| 264 | sh73a0_intcs_cascade.handler = sh73a0_intcs_demux; | ||
| 265 | sh73a0_intcs_cascade.dev_id = intevtsa; | ||
| 266 | setup_irq(gic_spi(50), &sh73a0_intcs_cascade); | ||
| 267 | } | ||
diff --git a/arch/arm/mach-shmobile/localtimer.c b/arch/arm/mach-shmobile/localtimer.c new file mode 100644 index 000000000000..2111c28b724e --- /dev/null +++ b/arch/arm/mach-shmobile/localtimer.c | |||
| @@ -0,0 +1,25 @@ | |||
| 1 | /* | ||
| 2 | * SMP support for R-Mobile / SH-Mobile - local timer portion | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Magnus Damm | ||
| 5 | * | ||
| 6 | * Based on vexpress, Copyright (C) 2002 ARM Ltd, All Rights Reserved | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/smp.h> | ||
| 14 | #include <linux/clockchips.h> | ||
| 15 | #include <asm/smp_twd.h> | ||
| 16 | #include <asm/localtimer.h> | ||
| 17 | |||
| 18 | /* | ||
| 19 | * Setup the local clock events for a CPU. | ||
| 20 | */ | ||
| 21 | void __cpuinit local_timer_setup(struct clock_event_device *evt) | ||
| 22 | { | ||
| 23 | evt->irq = 29; | ||
| 24 | twd_timer_setup(evt); | ||
| 25 | } | ||
diff --git a/arch/arm/mach-shmobile/pfc-sh73a0.c b/arch/arm/mach-shmobile/pfc-sh73a0.c new file mode 100644 index 000000000000..3eed44eb98b4 --- /dev/null +++ b/arch/arm/mach-shmobile/pfc-sh73a0.c | |||
| @@ -0,0 +1,2746 @@ | |||
| 1 | /* | ||
| 2 | * sh73a0 processor support - PFC hardware block | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Renesas Solutions Corp. | ||
| 5 | * Copyright (C) 2010 NISHIMOTO Hiroki | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or | ||
| 8 | * modify it under the terms of the GNU General Public License as | ||
| 9 | * published by the Free Software Foundation; version 2 of the | ||
| 10 | * License. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 20 | */ | ||
| 21 | #include <linux/init.h> | ||
| 22 | #include <linux/kernel.h> | ||
| 23 | #include <linux/gpio.h> | ||
| 24 | #include <mach/sh73a0.h> | ||
| 25 | |||
| 26 | #define _1(fn, pfx, sfx) fn(pfx, sfx) | ||
| 27 | |||
| 28 | #define _10(fn, pfx, sfx) \ | ||
| 29 | _1(fn, pfx##0, sfx), _1(fn, pfx##1, sfx), \ | ||
| 30 | _1(fn, pfx##2, sfx), _1(fn, pfx##3, sfx), \ | ||
| 31 | _1(fn, pfx##4, sfx), _1(fn, pfx##5, sfx), \ | ||
| 32 | _1(fn, pfx##6, sfx), _1(fn, pfx##7, sfx), \ | ||
| 33 | _1(fn, pfx##8, sfx), _1(fn, pfx##9, sfx) | ||
| 34 | |||
| 35 | #define _310(fn, pfx, sfx) \ | ||
| 36 | _10(fn, pfx, sfx), _10(fn, pfx##1, sfx), \ | ||
| 37 | _10(fn, pfx##2, sfx), _10(fn, pfx##3, sfx), \ | ||
| 38 | _10(fn, pfx##4, sfx), _10(fn, pfx##5, sfx), \ | ||
| 39 | _10(fn, pfx##6, sfx), _10(fn, pfx##7, sfx), \ | ||
| 40 | _10(fn, pfx##8, sfx), _10(fn, pfx##9, sfx), \ | ||
| 41 | _10(fn, pfx##10, sfx), \ | ||
| 42 | _1(fn, pfx##110, sfx), _1(fn, pfx##111, sfx), \ | ||
| 43 | _1(fn, pfx##112, sfx), _1(fn, pfx##113, sfx), \ | ||
| 44 | _1(fn, pfx##114, sfx), _1(fn, pfx##115, sfx), \ | ||
| 45 | _1(fn, pfx##116, sfx), _1(fn, pfx##117, sfx), \ | ||
| 46 | _1(fn, pfx##118, sfx), \ | ||
| 47 | _1(fn, pfx##128, sfx), _1(fn, pfx##129, sfx), \ | ||
| 48 | _10(fn, pfx##13, sfx), _10(fn, pfx##14, sfx), \ | ||
| 49 | _10(fn, pfx##15, sfx), \ | ||
| 50 | _1(fn, pfx##160, sfx), _1(fn, pfx##161, sfx), \ | ||
| 51 | _1(fn, pfx##162, sfx), _1(fn, pfx##163, sfx), \ | ||
| 52 | _1(fn, pfx##164, sfx), \ | ||
| 53 | _1(fn, pfx##192, sfx), _1(fn, pfx##193, sfx), \ | ||
| 54 | _1(fn, pfx##194, sfx), _1(fn, pfx##195, sfx), \ | ||
| 55 | _1(fn, pfx##196, sfx), _1(fn, pfx##197, sfx), \ | ||
| 56 | _1(fn, pfx##198, sfx), _1(fn, pfx##199, sfx), \ | ||
| 57 | _10(fn, pfx##20, sfx), _10(fn, pfx##21, sfx), \ | ||
| 58 | _10(fn, pfx##22, sfx), _10(fn, pfx##23, sfx), \ | ||
| 59 | _10(fn, pfx##24, sfx), _10(fn, pfx##25, sfx), \ | ||
| 60 | _10(fn, pfx##26, sfx), _10(fn, pfx##27, sfx), \ | ||
| 61 | _1(fn, pfx##280, sfx), _1(fn, pfx##281, sfx), \ | ||
| 62 | _1(fn, pfx##282, sfx), \ | ||
| 63 | _1(fn, pfx##288, sfx), _1(fn, pfx##289, sfx), \ | ||
| 64 | _10(fn, pfx##29, sfx), _10(fn, pfx##30, sfx) | ||
| 65 | |||
| 66 | #define _PORT(pfx, sfx) pfx##_##sfx | ||
| 67 | #define PORT_310(str) _310(_PORT, PORT, str) | ||
| 68 | |||
| 69 | enum { | ||
| 70 | PINMUX_RESERVED = 0, | ||
| 71 | |||
| 72 | PINMUX_DATA_BEGIN, | ||
| 73 | PORT_310(DATA), /* PORT0_DATA -> PORT309_DATA */ | ||
| 74 | PINMUX_DATA_END, | ||
| 75 | |||
| 76 | PINMUX_INPUT_BEGIN, | ||
| 77 | PORT_310(IN), /* PORT0_IN -> PORT309_IN */ | ||
| 78 | PINMUX_INPUT_END, | ||
| 79 | |||
| 80 | PINMUX_INPUT_PULLUP_BEGIN, | ||
| 81 | PORT_310(IN_PU), /* PORT0_IN_PU -> PORT309_IN_PU */ | ||
| 82 | PINMUX_INPUT_PULLUP_END, | ||
| 83 | |||
| 84 | PINMUX_INPUT_PULLDOWN_BEGIN, | ||
| 85 | PORT_310(IN_PD), /* PORT0_IN_PD -> PORT309_IN_PD */ | ||
| 86 | PINMUX_INPUT_PULLDOWN_END, | ||
| 87 | |||
| 88 | PINMUX_OUTPUT_BEGIN, | ||
| 89 | PORT_310(OUT), /* PORT0_OUT -> PORT309_OUT */ | ||
| 90 | PINMUX_OUTPUT_END, | ||
| 91 | |||
| 92 | PINMUX_FUNCTION_BEGIN, | ||
| 93 | PORT_310(FN_IN), /* PORT0_FN_IN -> PORT309_FN_IN */ | ||
| 94 | PORT_310(FN_OUT), /* PORT0_FN_OUT -> PORT309_FN_OUT */ | ||
| 95 | PORT_310(FN0), /* PORT0_FN0 -> PORT309_FN0 */ | ||
| 96 | PORT_310(FN1), /* PORT0_FN1 -> PORT309_FN1 */ | ||
| 97 | PORT_310(FN2), /* PORT0_FN2 -> PORT309_FN2 */ | ||
| 98 | PORT_310(FN3), /* PORT0_FN3 -> PORT309_FN3 */ | ||
| 99 | PORT_310(FN4), /* PORT0_FN4 -> PORT309_FN4 */ | ||
| 100 | PORT_310(FN5), /* PORT0_FN5 -> PORT309_FN5 */ | ||
| 101 | PORT_310(FN6), /* PORT0_FN6 -> PORT309_FN6 */ | ||
| 102 | PORT_310(FN7), /* PORT0_FN7 -> PORT309_FN7 */ | ||
| 103 | |||
| 104 | MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1, | ||
| 105 | MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1, | ||
| 106 | MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1, | ||
| 107 | MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1, | ||
| 108 | MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1, | ||
| 109 | MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1, | ||
| 110 | MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1, | ||
| 111 | MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1, | ||
| 112 | MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1, | ||
| 113 | MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1, | ||
| 114 | MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1, | ||
| 115 | MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1, | ||
| 116 | MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1, | ||
| 117 | MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1, | ||
| 118 | MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1, | ||
| 119 | MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1, | ||
| 120 | MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1, | ||
| 121 | MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1, | ||
| 122 | MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1, | ||
| 123 | MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1, | ||
| 124 | MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1, | ||
| 125 | MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1, | ||
| 126 | MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1, | ||
| 127 | MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1, | ||
| 128 | MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1, | ||
| 129 | MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1, | ||
| 130 | MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1, | ||
| 131 | MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1, | ||
| 132 | MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1, | ||
| 133 | MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1, | ||
| 134 | MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1, | ||
| 135 | MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1, | ||
| 136 | MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1, | ||
| 137 | MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1, | ||
| 138 | MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1, | ||
| 139 | MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1, | ||
| 140 | MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1, | ||
| 141 | MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1, | ||
| 142 | MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1, | ||
| 143 | MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1, | ||
| 144 | MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1, | ||
| 145 | MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1, | ||
| 146 | PINMUX_FUNCTION_END, | ||
| 147 | |||
| 148 | PINMUX_MARK_BEGIN, | ||
| 149 | /* Hardware manual Table 25-1 (Function 0-7) */ | ||
| 150 | VBUS_0_MARK, | ||
| 151 | GPI0_MARK, | ||
| 152 | GPI1_MARK, | ||
| 153 | GPI2_MARK, | ||
| 154 | GPI3_MARK, | ||
| 155 | GPI4_MARK, | ||
| 156 | GPI5_MARK, | ||
| 157 | GPI6_MARK, | ||
| 158 | GPI7_MARK, | ||
| 159 | SCIFA7_RXD_MARK, | ||
| 160 | SCIFA7_CTS__MARK, | ||
| 161 | GPO7_MARK, MFG0_OUT2_MARK, | ||
| 162 | GPO6_MARK, MFG1_OUT2_MARK, | ||
| 163 | GPO5_MARK, SCIFA0_SCK_MARK, FSICOSLDT3_MARK, PORT16_VIO_CKOR_MARK, | ||
| 164 | SCIFA0_TXD_MARK, | ||
| 165 | SCIFA7_TXD_MARK, | ||
| 166 | SCIFA7_RTS__MARK, PORT19_VIO_CKO2_MARK, | ||
| 167 | GPO0_MARK, | ||
| 168 | GPO1_MARK, | ||
| 169 | GPO2_MARK, STATUS0_MARK, | ||
| 170 | GPO3_MARK, STATUS1_MARK, | ||
| 171 | GPO4_MARK, STATUS2_MARK, | ||
| 172 | VINT_MARK, | ||
| 173 | TCKON_MARK, | ||
| 174 | XDVFS1_MARK, PORT27_I2C_SCL2_MARK, PORT27_I2C_SCL3_MARK, \ | ||
| 175 | MFG0_OUT1_MARK, PORT27_IROUT_MARK, | ||
| 176 | XDVFS2_MARK, PORT28_I2C_SDA2_MARK, PORT28_I2C_SDA3_MARK, \ | ||
| 177 | PORT28_TPU1TO1_MARK, | ||
| 178 | SIM_RST_MARK, PORT29_TPU1TO1_MARK, | ||
| 179 | SIM_CLK_MARK, PORT30_VIO_CKOR_MARK, | ||
| 180 | SIM_D_MARK, PORT31_IROUT_MARK, | ||
| 181 | SCIFA4_TXD_MARK, | ||
| 182 | SCIFA4_RXD_MARK, XWUP_MARK, | ||
| 183 | SCIFA4_RTS__MARK, | ||
| 184 | SCIFA4_CTS__MARK, | ||
| 185 | FSIBOBT_MARK, FSIBIBT_MARK, | ||
| 186 | FSIBOLR_MARK, FSIBILR_MARK, | ||
| 187 | FSIBOSLD_MARK, | ||
| 188 | FSIBISLD_MARK, | ||
| 189 | VACK_MARK, | ||
| 190 | XTAL1L_MARK, | ||
| 191 | SCIFA0_RTS__MARK, FSICOSLDT2_MARK, | ||
| 192 | SCIFA0_RXD_MARK, | ||
| 193 | SCIFA0_CTS__MARK, FSICOSLDT1_MARK, | ||
| 194 | FSICOBT_MARK, FSICIBT_MARK, FSIDOBT_MARK, FSIDIBT_MARK, | ||
| 195 | FSICOLR_MARK, FSICILR_MARK, FSIDOLR_MARK, FSIDILR_MARK, | ||
| 196 | FSICOSLD_MARK, PORT47_FSICSPDIF_MARK, | ||
| 197 | FSICISLD_MARK, FSIDISLD_MARK, | ||
| 198 | FSIACK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, FSIAOMC_MARK, | ||
| 199 | FSIAOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, FSIAILR_MARK, | ||
| 200 | |||
| 201 | FSIAOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, FSIAIBT_MARK, | ||
| 202 | FSIAOSLD_MARK, BBIF2_TXD2_MARK, | ||
| 203 | FSIASPDIF_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, FSIBSPDIF_MARK, \ | ||
| 204 | PORT53_FSICSPDIF_MARK, | ||
| 205 | FSIBCK_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FSIBOMC_MARK, \ | ||
| 206 | FSICCK_MARK, FSICOMC_MARK, | ||
| 207 | FSIAISLD_MARK, TPU0TO0_MARK, | ||
| 208 | A0_MARK, BS__MARK, | ||
| 209 | A12_MARK, PORT58_KEYOUT7_MARK, TPU4TO2_MARK, | ||
| 210 | A13_MARK, PORT59_KEYOUT6_MARK, TPU0TO1_MARK, | ||
| 211 | A14_MARK, KEYOUT5_MARK, | ||
| 212 | A15_MARK, KEYOUT4_MARK, | ||
| 213 | A16_MARK, KEYOUT3_MARK, MSIOF0_SS1_MARK, | ||
| 214 | A17_MARK, KEYOUT2_MARK, MSIOF0_TSYNC_MARK, | ||
| 215 | A18_MARK, KEYOUT1_MARK, MSIOF0_TSCK_MARK, | ||
| 216 | A19_MARK, KEYOUT0_MARK, MSIOF0_TXD_MARK, | ||
| 217 | A20_MARK, KEYIN0_MARK, MSIOF0_RSCK_MARK, | ||
| 218 | A21_MARK, KEYIN1_MARK, MSIOF0_RSYNC_MARK, | ||
| 219 | A22_MARK, KEYIN2_MARK, MSIOF0_MCK0_MARK, | ||
| 220 | A23_MARK, KEYIN3_MARK, MSIOF0_MCK1_MARK, | ||
| 221 | A24_MARK, KEYIN4_MARK, MSIOF0_RXD_MARK, | ||
| 222 | A25_MARK, KEYIN5_MARK, MSIOF0_SS2_MARK, | ||
| 223 | A26_MARK, KEYIN6_MARK, | ||
| 224 | KEYIN7_MARK, | ||
| 225 | D0_NAF0_MARK, | ||
| 226 | D1_NAF1_MARK, | ||
| 227 | D2_NAF2_MARK, | ||
| 228 | D3_NAF3_MARK, | ||
| 229 | D4_NAF4_MARK, | ||
| 230 | D5_NAF5_MARK, | ||
| 231 | D6_NAF6_MARK, | ||
| 232 | D7_NAF7_MARK, | ||
| 233 | D8_NAF8_MARK, | ||
| 234 | D9_NAF9_MARK, | ||
| 235 | D10_NAF10_MARK, | ||
| 236 | D11_NAF11_MARK, | ||
| 237 | D12_NAF12_MARK, | ||
| 238 | D13_NAF13_MARK, | ||
| 239 | D14_NAF14_MARK, | ||
| 240 | D15_NAF15_MARK, | ||
| 241 | CS4__MARK, | ||
| 242 | CS5A__MARK, PORT91_RDWR_MARK, | ||
| 243 | CS5B__MARK, FCE1__MARK, | ||
| 244 | CS6B__MARK, DACK0_MARK, | ||
| 245 | FCE0__MARK, CS6A__MARK, | ||
| 246 | WAIT__MARK, DREQ0_MARK, | ||
| 247 | RD__FSC_MARK, | ||
| 248 | WE0__FWE_MARK, RDWR_FWE_MARK, | ||
| 249 | WE1__MARK, | ||
| 250 | FRB_MARK, | ||
| 251 | CKO_MARK, | ||
| 252 | NBRSTOUT__MARK, | ||
| 253 | NBRST__MARK, | ||
| 254 | BBIF2_TXD_MARK, | ||
| 255 | BBIF2_RXD_MARK, | ||
| 256 | BBIF2_SYNC_MARK, | ||
| 257 | BBIF2_SCK_MARK, | ||
| 258 | SCIFA3_CTS__MARK, MFG3_IN2_MARK, | ||
| 259 | SCIFA3_RXD_MARK, MFG3_IN1_MARK, | ||
| 260 | BBIF1_SS2_MARK, SCIFA3_RTS__MARK, MFG3_OUT1_MARK, | ||
| 261 | SCIFA3_TXD_MARK, | ||
| 262 | HSI_RX_DATA_MARK, BBIF1_RXD_MARK, | ||
| 263 | HSI_TX_WAKE_MARK, BBIF1_TSCK_MARK, | ||
| 264 | HSI_TX_DATA_MARK, BBIF1_TSYNC_MARK, | ||
| 265 | HSI_TX_READY_MARK, BBIF1_TXD_MARK, | ||
| 266 | HSI_RX_READY_MARK, BBIF1_RSCK_MARK, PORT115_I2C_SCL2_MARK, \ | ||
| 267 | PORT115_I2C_SCL3_MARK, | ||
| 268 | HSI_RX_WAKE_MARK, BBIF1_RSYNC_MARK, PORT116_I2C_SDA2_MARK, \ | ||
| 269 | PORT116_I2C_SDA3_MARK, | ||
| 270 | HSI_RX_FLAG_MARK, BBIF1_SS1_MARK, BBIF1_FLOW_MARK, | ||
| 271 | HSI_TX_FLAG_MARK, | ||
| 272 | VIO_VD_MARK, PORT128_LCD2VSYN_MARK, VIO2_VD_MARK, LCD2D0_MARK, | ||
| 273 | |||
| 274 | VIO_HD_MARK, PORT129_LCD2HSYN_MARK, PORT129_LCD2CS__MARK, \ | ||
| 275 | VIO2_HD_MARK, LCD2D1_MARK, | ||
| 276 | VIO_D0_MARK, PORT130_MSIOF2_RXD_MARK, LCD2D10_MARK, | ||
| 277 | VIO_D1_MARK, PORT131_KEYOUT6_MARK, PORT131_MSIOF2_SS1_MARK, \ | ||
| 278 | PORT131_KEYOUT11_MARK, LCD2D11_MARK, | ||
| 279 | VIO_D2_MARK, PORT132_KEYOUT7_MARK, PORT132_MSIOF2_SS2_MARK, \ | ||
| 280 | PORT132_KEYOUT10_MARK, LCD2D12_MARK, | ||
| 281 | VIO_D3_MARK, MSIOF2_TSYNC_MARK, LCD2D13_MARK, | ||
| 282 | VIO_D4_MARK, MSIOF2_TXD_MARK, LCD2D14_MARK, | ||
| 283 | VIO_D5_MARK, MSIOF2_TSCK_MARK, LCD2D15_MARK, | ||
| 284 | VIO_D6_MARK, PORT136_KEYOUT8_MARK, LCD2D16_MARK, | ||
| 285 | VIO_D7_MARK, PORT137_KEYOUT9_MARK, LCD2D17_MARK, | ||
| 286 | VIO_D8_MARK, PORT138_KEYOUT8_MARK, VIO2_D0_MARK, LCD2D6_MARK, | ||
| 287 | VIO_D9_MARK, PORT139_KEYOUT9_MARK, VIO2_D1_MARK, LCD2D7_MARK, | ||
| 288 | VIO_D10_MARK, TPU0TO2_MARK, VIO2_D2_MARK, LCD2D8_MARK, | ||
| 289 | VIO_D11_MARK, TPU0TO3_MARK, VIO2_D3_MARK, LCD2D9_MARK, | ||
| 290 | VIO_D12_MARK, PORT142_KEYOUT10_MARK, VIO2_D4_MARK, LCD2D2_MARK, | ||
| 291 | VIO_D13_MARK, PORT143_KEYOUT11_MARK, PORT143_KEYOUT6_MARK, \ | ||
| 292 | VIO2_D5_MARK, LCD2D3_MARK, | ||
| 293 | VIO_D14_MARK, PORT144_KEYOUT7_MARK, VIO2_D6_MARK, LCD2D4_MARK, | ||
| 294 | VIO_D15_MARK, TPU1TO3_MARK, PORT145_LCD2DISP_MARK, \ | ||
| 295 | PORT145_LCD2RS_MARK, VIO2_D7_MARK, LCD2D5_MARK, | ||
| 296 | VIO_CLK_MARK, LCD2DCK_MARK, PORT146_LCD2WR__MARK, VIO2_CLK_MARK, \ | ||
| 297 | LCD2D18_MARK, | ||
| 298 | VIO_FIELD_MARK, LCD2RD__MARK, VIO2_FIELD_MARK, LCD2D19_MARK, | ||
| 299 | VIO_CKO_MARK, | ||
| 300 | A27_MARK, PORT149_RDWR_MARK, MFG0_IN1_MARK, PORT149_KEYOUT9_MARK, | ||
| 301 | MFG0_IN2_MARK, | ||
| 302 | TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK, | ||
| 303 | TS_SDAT3_MARK, MSIOF2_RSYNC_MARK, | ||
| 304 | TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK, | ||
| 305 | SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK, | ||
| 306 | SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK, | ||
| 307 | SCIFA2_RTS1__MARK, PORT156_MSIOF2_SS2_MARK, | ||
| 308 | SCIFA2_CTS1__MARK, PORT157_MSIOF2_RXD_MARK, | ||
| 309 | DINT__MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK, | ||
| 310 | PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK, | ||
| 311 | PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK, | ||
| 312 | PORT161_SCIFB_CTS__MARK, PORT161_SCIFA5_CTS__MARK, | ||
| 313 | PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK, | ||
| 314 | PORT163_SCIFB_RTS__MARK, PORT163_SCIFA5_RTS__MARK, TPU3TO0_MARK, | ||
| 315 | LCDD0_MARK, | ||
| 316 | LCDD1_MARK, PORT193_SCIFA5_CTS__MARK, BBIF2_TSYNC1_MARK, | ||
| 317 | LCDD2_MARK, PORT194_SCIFA5_RTS__MARK, BBIF2_TSCK1_MARK, | ||
| 318 | LCDD3_MARK, PORT195_SCIFA5_RXD_MARK, BBIF2_TXD1_MARK, | ||
| 319 | LCDD4_MARK, PORT196_SCIFA5_TXD_MARK, | ||
| 320 | LCDD5_MARK, PORT197_SCIFA5_SCK_MARK, MFG2_OUT2_MARK, TPU2TO1_MARK, | ||
| 321 | LCDD6_MARK, | ||
| 322 | LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK, | ||
| 323 | LCDD8_MARK, D16_MARK, | ||
| 324 | LCDD9_MARK, D17_MARK, | ||
| 325 | LCDD10_MARK, D18_MARK, | ||
| 326 | LCDD11_MARK, D19_MARK, | ||
| 327 | LCDD12_MARK, D20_MARK, | ||
| 328 | LCDD13_MARK, D21_MARK, | ||
| 329 | LCDD14_MARK, D22_MARK, | ||
| 330 | LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, D23_MARK, | ||
| 331 | LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, D24_MARK, | ||
| 332 | LCDD17_MARK, D25_MARK, | ||
| 333 | LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK, | ||
| 334 | LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK, | ||
| 335 | LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK, | ||
| 336 | LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK, | ||
| 337 | LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK, | ||
| 338 | LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK, | ||
| 339 | LCDDCK_MARK, LCDWR__MARK, | ||
| 340 | LCDRD__MARK, DACK2_MARK, PORT217_LCD2RS_MARK, MSIOF0L_TSYNC_MARK, \ | ||
| 341 | VIO2_FIELD3_MARK, PORT217_LCD2DISP_MARK, | ||
| 342 | LCDHSYN_MARK, LCDCS__MARK, LCDCS2__MARK, DACK3_MARK, \ | ||
| 343 | PORT218_VIO_CKOR_MARK, | ||
| 344 | LCDDISP_MARK, LCDRS_MARK, PORT219_LCD2WR__MARK, DREQ3_MARK, \ | ||
| 345 | MSIOF0L_TSCK_MARK, VIO2_CLK3_MARK, LCD2DCK_2_MARK, | ||
| 346 | LCDVSYN_MARK, LCDVSYN2_MARK, | ||
| 347 | LCDLCLK_MARK, DREQ1_MARK, PORT221_LCD2CS__MARK, PWEN_MARK, \ | ||
| 348 | MSIOF0L_RXD_MARK, VIO2_HD3_MARK, PORT221_LCD2HSYN_MARK, | ||
| 349 | LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, \ | ||
| 350 | VIO2_VD3_MARK, PORT222_LCD2VSYN_MARK, | ||
| 351 | |||
| 352 | SCIFA1_TXD_MARK, OVCN2_MARK, | ||
| 353 | EXTLP_MARK, SCIFA1_SCK_MARK, PORT226_VIO_CKO2_MARK, | ||
| 354 | SCIFA1_RTS__MARK, IDIN_MARK, | ||
| 355 | SCIFA1_RXD_MARK, | ||
| 356 | SCIFA1_CTS__MARK, MFG1_IN1_MARK, | ||
| 357 | MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK, | ||
| 358 | MSIOF1_TSYNC_MARK, SCIFA2_CTS2__MARK, | ||
| 359 | MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK, | ||
| 360 | MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK, | ||
| 361 | MSIOF1_RSCK_MARK, SCIFA2_RTS2__MARK, VIO2_CLK2_MARK, LCD2D20_MARK, | ||
| 362 | MSIOF1_RSYNC_MARK, MFG1_IN2_MARK, VIO2_VD2_MARK, LCD2D21_MARK, | ||
| 363 | MSIOF1_MCK0_MARK, PORT236_I2C_SDA2_MARK, | ||
| 364 | MSIOF1_MCK1_MARK, PORT237_I2C_SCL2_MARK, | ||
| 365 | MSIOF1_SS1_MARK, VIO2_FIELD2_MARK, LCD2D22_MARK, | ||
| 366 | MSIOF1_SS2_MARK, VIO2_HD2_MARK, LCD2D23_MARK, | ||
| 367 | SCIFA6_TXD_MARK, | ||
| 368 | PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, TPU4TO0_MARK, | ||
| 369 | PORT242_IRDA_IN_MARK, MFG4_IN2_MARK, | ||
| 370 | PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK, | ||
| 371 | PORT244_SCIFA5_CTS__MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS__MARK, \ | ||
| 372 | MSIOF2R_RXD_MARK, | ||
| 373 | PORT245_SCIFA5_RTS__MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS__MARK, \ | ||
| 374 | MSIOF2R_TXD_MARK, | ||
| 375 | PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, \ | ||
| 376 | TPU1TO0_MARK, | ||
| 377 | PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, \ | ||
| 378 | TPU3TO1_MARK, | ||
| 379 | PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, \ | ||
| 380 | TPU2TO0_MARK, PORT248_I2C_SCL3_MARK, MSIOF2R_TSCK_MARK, | ||
| 381 | PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_I2C_SDA3_MARK, \ | ||
| 382 | MSIOF2R_TSYNC_MARK, | ||
| 383 | SDHICLK0_MARK, | ||
| 384 | SDHICD0_MARK, | ||
| 385 | SDHID0_0_MARK, | ||
| 386 | SDHID0_1_MARK, | ||
| 387 | SDHID0_2_MARK, | ||
| 388 | SDHID0_3_MARK, | ||
| 389 | SDHICMD0_MARK, | ||
| 390 | SDHIWP0_MARK, | ||
| 391 | SDHICLK1_MARK, | ||
| 392 | SDHID1_0_MARK, TS_SPSYNC2_MARK, | ||
| 393 | SDHID1_1_MARK, TS_SDAT2_MARK, | ||
| 394 | SDHID1_2_MARK, TS_SDEN2_MARK, | ||
| 395 | SDHID1_3_MARK, TS_SCK2_MARK, | ||
| 396 | SDHICMD1_MARK, | ||
| 397 | SDHICLK2_MARK, | ||
| 398 | SDHID2_0_MARK, TS_SPSYNC4_MARK, | ||
| 399 | SDHID2_1_MARK, TS_SDAT4_MARK, | ||
| 400 | SDHID2_2_MARK, TS_SDEN4_MARK, | ||
| 401 | SDHID2_3_MARK, TS_SCK4_MARK, | ||
| 402 | SDHICMD2_MARK, | ||
| 403 | MMCCLK0_MARK, | ||
| 404 | MMCD0_0_MARK, | ||
| 405 | MMCD0_1_MARK, | ||
| 406 | MMCD0_2_MARK, | ||
| 407 | MMCD0_3_MARK, | ||
| 408 | MMCD0_4_MARK, TS_SPSYNC5_MARK, | ||
| 409 | MMCD0_5_MARK, TS_SDAT5_MARK, | ||
| 410 | MMCD0_6_MARK, TS_SDEN5_MARK, | ||
| 411 | MMCD0_7_MARK, TS_SCK5_MARK, | ||
| 412 | MMCCMD0_MARK, | ||
| 413 | RESETOUTS__MARK, EXTAL2OUT_MARK, | ||
| 414 | MCP_WAIT__MCP_FRB_MARK, | ||
| 415 | MCP_CKO_MARK, MMCCLK1_MARK, | ||
| 416 | MCP_D15_MCP_NAF15_MARK, | ||
| 417 | MCP_D14_MCP_NAF14_MARK, | ||
| 418 | MCP_D13_MCP_NAF13_MARK, | ||
| 419 | MCP_D12_MCP_NAF12_MARK, | ||
| 420 | MCP_D11_MCP_NAF11_MARK, | ||
| 421 | MCP_D10_MCP_NAF10_MARK, | ||
| 422 | MCP_D9_MCP_NAF9_MARK, | ||
| 423 | MCP_D8_MCP_NAF8_MARK, MMCCMD1_MARK, | ||
| 424 | MCP_D7_MCP_NAF7_MARK, MMCD1_7_MARK, | ||
| 425 | |||
| 426 | MCP_D6_MCP_NAF6_MARK, MMCD1_6_MARK, | ||
| 427 | MCP_D5_MCP_NAF5_MARK, MMCD1_5_MARK, | ||
| 428 | MCP_D4_MCP_NAF4_MARK, MMCD1_4_MARK, | ||
| 429 | MCP_D3_MCP_NAF3_MARK, MMCD1_3_MARK, | ||
| 430 | MCP_D2_MCP_NAF2_MARK, MMCD1_2_MARK, | ||
| 431 | MCP_D1_MCP_NAF1_MARK, MMCD1_1_MARK, | ||
| 432 | MCP_D0_MCP_NAF0_MARK, MMCD1_0_MARK, | ||
| 433 | MCP_NBRSTOUT__MARK, | ||
| 434 | MCP_WE0__MCP_FWE_MARK, MCP_RDWR_MCP_FWE_MARK, | ||
| 435 | |||
| 436 | /* MSEL2 special cases */ | ||
| 437 | TSIF2_TS_XX1_MARK, | ||
| 438 | TSIF2_TS_XX2_MARK, | ||
| 439 | TSIF2_TS_XX3_MARK, | ||
| 440 | TSIF2_TS_XX4_MARK, | ||
| 441 | TSIF2_TS_XX5_MARK, | ||
| 442 | TSIF1_TS_XX1_MARK, | ||
| 443 | TSIF1_TS_XX2_MARK, | ||
| 444 | TSIF1_TS_XX3_MARK, | ||
| 445 | TSIF1_TS_XX4_MARK, | ||
| 446 | TSIF1_TS_XX5_MARK, | ||
| 447 | TSIF0_TS_XX1_MARK, | ||
| 448 | TSIF0_TS_XX2_MARK, | ||
| 449 | TSIF0_TS_XX3_MARK, | ||
| 450 | TSIF0_TS_XX4_MARK, | ||
| 451 | TSIF0_TS_XX5_MARK, | ||
| 452 | MST1_TS_XX1_MARK, | ||
| 453 | MST1_TS_XX2_MARK, | ||
| 454 | MST1_TS_XX3_MARK, | ||
| 455 | MST1_TS_XX4_MARK, | ||
| 456 | MST1_TS_XX5_MARK, | ||
| 457 | MST0_TS_XX1_MARK, | ||
| 458 | MST0_TS_XX2_MARK, | ||
| 459 | MST0_TS_XX3_MARK, | ||
| 460 | MST0_TS_XX4_MARK, | ||
| 461 | MST0_TS_XX5_MARK, | ||
| 462 | |||
| 463 | /* MSEL3 special cases */ | ||
| 464 | SDHI0_VCCQ_MC0_ON_MARK, | ||
| 465 | SDHI0_VCCQ_MC0_OFF_MARK, | ||
| 466 | DEBUG_MON_VIO_MARK, | ||
| 467 | DEBUG_MON_LCDD_MARK, | ||
| 468 | LCDC_LCDC0_MARK, | ||
| 469 | LCDC_LCDC1_MARK, | ||
| 470 | |||
| 471 | /* MSEL4 special cases */ | ||
| 472 | IRQ9_MEM_INT_MARK, | ||
| 473 | IRQ9_MCP_INT_MARK, | ||
| 474 | A11_MARK, | ||
| 475 | KEYOUT8_MARK, | ||
| 476 | TPU4TO3_MARK, | ||
| 477 | RESETA_N_PU_ON_MARK, | ||
| 478 | RESETA_N_PU_OFF_MARK, | ||
| 479 | EDBGREQ_PD_MARK, | ||
| 480 | EDBGREQ_PU_MARK, | ||
| 481 | |||
| 482 | /* Functions with pull-ups */ | ||
| 483 | KEYIN0_PU_MARK, | ||
| 484 | KEYIN1_PU_MARK, | ||
| 485 | KEYIN2_PU_MARK, | ||
| 486 | KEYIN3_PU_MARK, | ||
| 487 | KEYIN4_PU_MARK, | ||
| 488 | KEYIN5_PU_MARK, | ||
| 489 | KEYIN6_PU_MARK, | ||
| 490 | KEYIN7_PU_MARK, | ||
| 491 | SDHID1_0_PU_MARK, | ||
| 492 | SDHID1_1_PU_MARK, | ||
| 493 | SDHID1_2_PU_MARK, | ||
| 494 | SDHID1_3_PU_MARK, | ||
| 495 | SDHICMD1_PU_MARK, | ||
| 496 | MMCCMD0_PU_MARK, | ||
| 497 | MMCCMD1_PU_MARK, | ||
| 498 | FSIACK_PU_MARK, | ||
| 499 | FSIAILR_PU_MARK, | ||
| 500 | FSIAIBT_PU_MARK, | ||
| 501 | FSIAISLD_PU_MARK, | ||
| 502 | |||
| 503 | PINMUX_MARK_END, | ||
| 504 | }; | ||
| 505 | |||
| 506 | #define PORT_DATA_I(nr) \ | ||
| 507 | PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN) | ||
| 508 | |||
| 509 | #define PORT_DATA_I_PD(nr) \ | ||
| 510 | PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ | ||
| 511 | PORT##nr##_IN, PORT##nr##_IN_PD) | ||
| 512 | |||
| 513 | #define PORT_DATA_I_PU(nr) \ | ||
| 514 | PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ | ||
| 515 | PORT##nr##_IN, PORT##nr##_IN_PU) | ||
| 516 | |||
| 517 | #define PORT_DATA_I_PU_PD(nr) \ | ||
| 518 | PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ | ||
| 519 | PORT##nr##_IN, PORT##nr##_IN_PD, \ | ||
| 520 | PORT##nr##_IN_PU) | ||
| 521 | |||
| 522 | #define PORT_DATA_O(nr) \ | ||
| 523 | PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ | ||
| 524 | PORT##nr##_OUT) | ||
| 525 | |||
| 526 | #define PORT_DATA_IO(nr) \ | ||
| 527 | PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ | ||
| 528 | PORT##nr##_OUT, PORT##nr##_IN) | ||
| 529 | |||
| 530 | #define PORT_DATA_IO_PD(nr) \ | ||
| 531 | PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ | ||
| 532 | PORT##nr##_OUT, PORT##nr##_IN, \ | ||
| 533 | PORT##nr##_IN_PD) | ||
| 534 | |||
| 535 | #define PORT_DATA_IO_PU(nr) \ | ||
| 536 | PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ | ||
| 537 | PORT##nr##_OUT, PORT##nr##_IN, \ | ||
| 538 | PORT##nr##_IN_PU) | ||
| 539 | |||
| 540 | #define PORT_DATA_IO_PU_PD(nr) \ | ||
| 541 | PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \ | ||
| 542 | PORT##nr##_OUT, PORT##nr##_IN, \ | ||
| 543 | PORT##nr##_IN_PD, PORT##nr##_IN_PU) | ||
| 544 | |||
| 545 | static pinmux_enum_t pinmux_data[] = { | ||
| 546 | /* specify valid pin states for each pin in GPIO mode */ | ||
| 547 | |||
| 548 | /* Table 25-1 (I/O and Pull U/D) */ | ||
| 549 | PORT_DATA_I_PD(0), | ||
| 550 | PORT_DATA_I_PU(1), | ||
| 551 | PORT_DATA_I_PU(2), | ||
| 552 | PORT_DATA_I_PU(3), | ||
| 553 | PORT_DATA_I_PU(4), | ||
| 554 | PORT_DATA_I_PU(5), | ||
| 555 | PORT_DATA_I_PU(6), | ||
| 556 | PORT_DATA_I_PU(7), | ||
| 557 | PORT_DATA_I_PU(8), | ||
| 558 | PORT_DATA_I_PD(9), | ||
| 559 | PORT_DATA_I_PD(10), | ||
| 560 | PORT_DATA_I_PU_PD(11), | ||
| 561 | PORT_DATA_IO_PU_PD(12), | ||
| 562 | PORT_DATA_IO_PU_PD(13), | ||
| 563 | PORT_DATA_IO_PU_PD(14), | ||
| 564 | PORT_DATA_IO_PU_PD(15), | ||
| 565 | PORT_DATA_IO_PD(16), | ||
| 566 | PORT_DATA_IO_PD(17), | ||
| 567 | PORT_DATA_IO_PU(18), | ||
| 568 | PORT_DATA_IO_PU(19), | ||
| 569 | PORT_DATA_O(20), | ||
| 570 | PORT_DATA_O(21), | ||
| 571 | PORT_DATA_O(22), | ||
| 572 | PORT_DATA_O(23), | ||
| 573 | PORT_DATA_O(24), | ||
| 574 | PORT_DATA_I_PD(25), | ||
| 575 | PORT_DATA_I_PD(26), | ||
| 576 | PORT_DATA_IO_PU(27), | ||
| 577 | PORT_DATA_IO_PU(28), | ||
| 578 | PORT_DATA_IO_PD(29), | ||
| 579 | PORT_DATA_IO_PD(30), | ||
| 580 | PORT_DATA_IO_PU(31), | ||
| 581 | PORT_DATA_IO_PD(32), | ||
| 582 | PORT_DATA_I_PU_PD(33), | ||
| 583 | PORT_DATA_IO_PD(34), | ||
| 584 | PORT_DATA_I_PU_PD(35), | ||
| 585 | PORT_DATA_IO_PD(36), | ||
| 586 | PORT_DATA_IO(37), | ||
| 587 | PORT_DATA_O(38), | ||
| 588 | PORT_DATA_I_PU(39), | ||
| 589 | PORT_DATA_I_PU_PD(40), | ||
| 590 | PORT_DATA_O(41), | ||
| 591 | PORT_DATA_IO_PD(42), | ||
| 592 | PORT_DATA_IO_PU_PD(43), | ||
| 593 | PORT_DATA_IO_PU_PD(44), | ||
| 594 | PORT_DATA_IO_PD(45), | ||
| 595 | PORT_DATA_IO_PD(46), | ||
| 596 | PORT_DATA_IO_PD(47), | ||
| 597 | PORT_DATA_I_PD(48), | ||
| 598 | PORT_DATA_IO_PU_PD(49), | ||
| 599 | PORT_DATA_IO_PD(50), | ||
| 600 | |||
| 601 | PORT_DATA_IO_PD(51), | ||
| 602 | PORT_DATA_O(52), | ||
| 603 | PORT_DATA_IO_PU_PD(53), | ||
| 604 | PORT_DATA_IO_PU_PD(54), | ||
| 605 | PORT_DATA_IO_PD(55), | ||
| 606 | PORT_DATA_I_PU_PD(56), | ||
| 607 | PORT_DATA_IO(57), | ||
| 608 | PORT_DATA_IO(58), | ||
| 609 | PORT_DATA_IO(59), | ||
| 610 | PORT_DATA_IO(60), | ||
| 611 | PORT_DATA_IO(61), | ||
| 612 | PORT_DATA_IO_PD(62), | ||
| 613 | PORT_DATA_IO_PD(63), | ||
| 614 | PORT_DATA_IO_PU_PD(64), | ||
| 615 | PORT_DATA_IO_PD(65), | ||
| 616 | PORT_DATA_IO_PU_PD(66), | ||
| 617 | PORT_DATA_IO_PU_PD(67), | ||
| 618 | PORT_DATA_IO_PU_PD(68), | ||
| 619 | PORT_DATA_IO_PU_PD(69), | ||
| 620 | PORT_DATA_IO_PU_PD(70), | ||
| 621 | PORT_DATA_IO_PU_PD(71), | ||
| 622 | PORT_DATA_IO_PU_PD(72), | ||
| 623 | PORT_DATA_I_PU_PD(73), | ||
| 624 | PORT_DATA_IO_PU(74), | ||
| 625 | PORT_DATA_IO_PU(75), | ||
| 626 | PORT_DATA_IO_PU(76), | ||
| 627 | PORT_DATA_IO_PU(77), | ||
| 628 | PORT_DATA_IO_PU(78), | ||
| 629 | PORT_DATA_IO_PU(79), | ||
| 630 | PORT_DATA_IO_PU(80), | ||
| 631 | PORT_DATA_IO_PU(81), | ||
| 632 | PORT_DATA_IO_PU(82), | ||
| 633 | PORT_DATA_IO_PU(83), | ||
| 634 | PORT_DATA_IO_PU(84), | ||
| 635 | PORT_DATA_IO_PU(85), | ||
| 636 | PORT_DATA_IO_PU(86), | ||
| 637 | PORT_DATA_IO_PU(87), | ||
| 638 | PORT_DATA_IO_PU(88), | ||
| 639 | PORT_DATA_IO_PU(89), | ||
| 640 | PORT_DATA_O(90), | ||
| 641 | PORT_DATA_IO_PU(91), | ||
| 642 | PORT_DATA_O(92), | ||
| 643 | PORT_DATA_IO_PU(93), | ||
| 644 | PORT_DATA_O(94), | ||
| 645 | PORT_DATA_I_PU_PD(95), | ||
| 646 | PORT_DATA_IO(96), | ||
| 647 | PORT_DATA_IO(97), | ||
| 648 | PORT_DATA_IO(98), | ||
| 649 | PORT_DATA_I_PU(99), | ||
| 650 | PORT_DATA_O(100), | ||
| 651 | PORT_DATA_O(101), | ||
| 652 | PORT_DATA_I_PU(102), | ||
| 653 | PORT_DATA_IO_PD(103), | ||
| 654 | PORT_DATA_I_PU_PD(104), | ||
| 655 | PORT_DATA_I_PD(105), | ||
| 656 | PORT_DATA_I_PD(106), | ||
| 657 | PORT_DATA_I_PU_PD(107), | ||
| 658 | PORT_DATA_I_PU_PD(108), | ||
| 659 | PORT_DATA_IO_PD(109), | ||
| 660 | PORT_DATA_IO_PD(110), | ||
| 661 | PORT_DATA_IO_PU_PD(111), | ||
| 662 | PORT_DATA_IO_PU_PD(112), | ||
| 663 | PORT_DATA_IO_PU_PD(113), | ||
| 664 | PORT_DATA_IO_PD(114), | ||
| 665 | PORT_DATA_IO_PU(115), | ||
| 666 | PORT_DATA_IO_PU(116), | ||
| 667 | PORT_DATA_IO_PU_PD(117), | ||
| 668 | PORT_DATA_IO_PU_PD(118), | ||
| 669 | PORT_DATA_IO_PD(128), | ||
| 670 | |||
| 671 | PORT_DATA_IO_PD(129), | ||
| 672 | PORT_DATA_IO_PU_PD(130), | ||
| 673 | PORT_DATA_IO_PD(131), | ||
| 674 | PORT_DATA_IO_PD(132), | ||
| 675 | PORT_DATA_IO_PD(133), | ||
| 676 | PORT_DATA_IO_PU_PD(134), | ||
| 677 | PORT_DATA_IO_PU_PD(135), | ||
| 678 | PORT_DATA_IO_PU_PD(136), | ||
| 679 | PORT_DATA_IO_PU_PD(137), | ||
| 680 | PORT_DATA_IO_PD(138), | ||
| 681 | PORT_DATA_IO_PD(139), | ||
| 682 | PORT_DATA_IO_PD(140), | ||
| 683 | PORT_DATA_IO_PD(141), | ||
| 684 | PORT_DATA_IO_PD(142), | ||
| 685 | PORT_DATA_IO_PD(143), | ||
| 686 | PORT_DATA_IO_PU_PD(144), | ||
| 687 | PORT_DATA_IO_PD(145), | ||
| 688 | PORT_DATA_IO_PU_PD(146), | ||
| 689 | PORT_DATA_IO_PU_PD(147), | ||
| 690 | PORT_DATA_IO_PU_PD(148), | ||
| 691 | PORT_DATA_IO_PU_PD(149), | ||
| 692 | PORT_DATA_I_PU_PD(150), | ||
| 693 | PORT_DATA_IO_PU_PD(151), | ||
| 694 | PORT_DATA_IO_PU_PD(152), | ||
| 695 | PORT_DATA_IO_PD(153), | ||
| 696 | PORT_DATA_IO_PD(154), | ||
| 697 | PORT_DATA_I_PU_PD(155), | ||
| 698 | PORT_DATA_IO_PU_PD(156), | ||
| 699 | PORT_DATA_I_PD(157), | ||
| 700 | PORT_DATA_IO_PD(158), | ||
| 701 | PORT_DATA_IO_PU_PD(159), | ||
| 702 | PORT_DATA_IO_PU_PD(160), | ||
| 703 | PORT_DATA_I_PU_PD(161), | ||
| 704 | PORT_DATA_I_PU_PD(162), | ||
| 705 | PORT_DATA_IO_PU_PD(163), | ||
| 706 | PORT_DATA_I_PU_PD(164), | ||
| 707 | PORT_DATA_IO_PD(192), | ||
| 708 | PORT_DATA_IO_PU_PD(193), | ||
| 709 | PORT_DATA_IO_PD(194), | ||
| 710 | PORT_DATA_IO_PU_PD(195), | ||
| 711 | PORT_DATA_IO_PD(196), | ||
| 712 | PORT_DATA_IO_PD(197), | ||
| 713 | PORT_DATA_IO_PD(198), | ||
| 714 | PORT_DATA_IO_PD(199), | ||
| 715 | PORT_DATA_IO_PU_PD(200), | ||
| 716 | PORT_DATA_IO_PU_PD(201), | ||
| 717 | PORT_DATA_IO_PU_PD(202), | ||
| 718 | PORT_DATA_IO_PU_PD(203), | ||
| 719 | PORT_DATA_IO_PU_PD(204), | ||
| 720 | PORT_DATA_IO_PU_PD(205), | ||
| 721 | PORT_DATA_IO_PU_PD(206), | ||
| 722 | PORT_DATA_IO_PD(207), | ||
| 723 | PORT_DATA_IO_PD(208), | ||
| 724 | PORT_DATA_IO_PD(209), | ||
| 725 | PORT_DATA_IO_PD(210), | ||
| 726 | PORT_DATA_IO_PD(211), | ||
| 727 | PORT_DATA_IO_PD(212), | ||
| 728 | PORT_DATA_IO_PD(213), | ||
| 729 | PORT_DATA_IO_PU_PD(214), | ||
| 730 | PORT_DATA_IO_PU_PD(215), | ||
| 731 | PORT_DATA_IO_PD(216), | ||
| 732 | PORT_DATA_IO_PD(217), | ||
| 733 | PORT_DATA_O(218), | ||
| 734 | PORT_DATA_IO_PD(219), | ||
| 735 | PORT_DATA_IO_PD(220), | ||
| 736 | PORT_DATA_IO_PU_PD(221), | ||
| 737 | PORT_DATA_IO_PU_PD(222), | ||
| 738 | PORT_DATA_I_PU_PD(223), | ||
| 739 | PORT_DATA_I_PU_PD(224), | ||
| 740 | |||
| 741 | PORT_DATA_IO_PU_PD(225), | ||
| 742 | PORT_DATA_O(226), | ||
| 743 | PORT_DATA_IO_PU_PD(227), | ||
| 744 | PORT_DATA_I_PU_PD(228), | ||
| 745 | PORT_DATA_I_PD(229), | ||
| 746 | PORT_DATA_IO(230), | ||
| 747 | PORT_DATA_IO_PU_PD(231), | ||
| 748 | PORT_DATA_IO_PU_PD(232), | ||
| 749 | PORT_DATA_I_PU_PD(233), | ||
| 750 | PORT_DATA_IO_PU_PD(234), | ||
| 751 | PORT_DATA_IO_PU_PD(235), | ||
| 752 | PORT_DATA_IO_PU_PD(236), | ||
| 753 | PORT_DATA_IO_PD(237), | ||
| 754 | PORT_DATA_IO_PU_PD(238), | ||
| 755 | PORT_DATA_IO_PU_PD(239), | ||
| 756 | PORT_DATA_IO_PU_PD(240), | ||
| 757 | PORT_DATA_O(241), | ||
| 758 | PORT_DATA_I_PD(242), | ||
| 759 | PORT_DATA_IO_PU_PD(243), | ||
| 760 | PORT_DATA_IO_PU_PD(244), | ||
| 761 | PORT_DATA_IO_PU_PD(245), | ||
| 762 | PORT_DATA_IO_PU_PD(246), | ||
| 763 | PORT_DATA_IO_PU_PD(247), | ||
| 764 | PORT_DATA_IO_PU_PD(248), | ||
| 765 | PORT_DATA_IO_PU_PD(249), | ||
| 766 | PORT_DATA_IO_PU_PD(250), | ||
| 767 | PORT_DATA_IO_PU_PD(251), | ||
| 768 | PORT_DATA_IO_PU_PD(252), | ||
| 769 | PORT_DATA_IO_PU_PD(253), | ||
| 770 | PORT_DATA_IO_PU_PD(254), | ||
| 771 | PORT_DATA_IO_PU_PD(255), | ||
| 772 | PORT_DATA_IO_PU_PD(256), | ||
| 773 | PORT_DATA_IO_PU_PD(257), | ||
| 774 | PORT_DATA_IO_PU_PD(258), | ||
| 775 | PORT_DATA_IO_PU_PD(259), | ||
| 776 | PORT_DATA_IO_PU_PD(260), | ||
| 777 | PORT_DATA_IO_PU_PD(261), | ||
| 778 | PORT_DATA_IO_PU_PD(262), | ||
| 779 | PORT_DATA_IO_PU_PD(263), | ||
| 780 | PORT_DATA_IO_PU_PD(264), | ||
| 781 | PORT_DATA_IO_PU_PD(265), | ||
| 782 | PORT_DATA_IO_PU_PD(266), | ||
| 783 | PORT_DATA_IO_PU_PD(267), | ||
| 784 | PORT_DATA_IO_PU_PD(268), | ||
| 785 | PORT_DATA_IO_PU_PD(269), | ||
| 786 | PORT_DATA_IO_PU_PD(270), | ||
| 787 | PORT_DATA_IO_PU_PD(271), | ||
| 788 | PORT_DATA_IO_PU_PD(272), | ||
| 789 | PORT_DATA_IO_PU_PD(273), | ||
| 790 | PORT_DATA_IO_PU_PD(274), | ||
| 791 | PORT_DATA_IO_PU_PD(275), | ||
| 792 | PORT_DATA_IO_PU_PD(276), | ||
| 793 | PORT_DATA_IO_PU_PD(277), | ||
| 794 | PORT_DATA_IO_PU_PD(278), | ||
| 795 | PORT_DATA_IO_PU_PD(279), | ||
| 796 | PORT_DATA_IO_PU_PD(280), | ||
| 797 | PORT_DATA_O(281), | ||
| 798 | PORT_DATA_O(282), | ||
| 799 | PORT_DATA_I_PU(288), | ||
| 800 | PORT_DATA_IO_PU_PD(289), | ||
| 801 | PORT_DATA_IO_PU_PD(290), | ||
| 802 | PORT_DATA_IO_PU_PD(291), | ||
| 803 | PORT_DATA_IO_PU_PD(292), | ||
| 804 | PORT_DATA_IO_PU_PD(293), | ||
| 805 | PORT_DATA_IO_PU_PD(294), | ||
| 806 | PORT_DATA_IO_PU_PD(295), | ||
| 807 | PORT_DATA_IO_PU_PD(296), | ||
| 808 | PORT_DATA_IO_PU_PD(297), | ||
| 809 | PORT_DATA_IO_PU_PD(298), | ||
| 810 | |||
| 811 | PORT_DATA_IO_PU_PD(299), | ||
| 812 | PORT_DATA_IO_PU_PD(300), | ||
| 813 | PORT_DATA_IO_PU_PD(301), | ||
| 814 | PORT_DATA_IO_PU_PD(302), | ||
| 815 | PORT_DATA_IO_PU_PD(303), | ||
| 816 | PORT_DATA_IO_PU_PD(304), | ||
| 817 | PORT_DATA_IO_PU_PD(305), | ||
| 818 | PORT_DATA_O(306), | ||
| 819 | PORT_DATA_O(307), | ||
| 820 | PORT_DATA_I_PU(308), | ||
| 821 | PORT_DATA_O(309), | ||
| 822 | |||
| 823 | /* Table 25-1 (Function 0-7) */ | ||
| 824 | PINMUX_DATA(VBUS_0_MARK, PORT0_FN1), | ||
| 825 | PINMUX_DATA(GPI0_MARK, PORT1_FN1), | ||
| 826 | PINMUX_DATA(GPI1_MARK, PORT2_FN1), | ||
| 827 | PINMUX_DATA(GPI2_MARK, PORT3_FN1), | ||
| 828 | PINMUX_DATA(GPI3_MARK, PORT4_FN1), | ||
| 829 | PINMUX_DATA(GPI4_MARK, PORT5_FN1), | ||
| 830 | PINMUX_DATA(GPI5_MARK, PORT6_FN1), | ||
| 831 | PINMUX_DATA(GPI6_MARK, PORT7_FN1), | ||
| 832 | PINMUX_DATA(GPI7_MARK, PORT8_FN1), | ||
| 833 | PINMUX_DATA(SCIFA7_RXD_MARK, PORT12_FN2), | ||
| 834 | PINMUX_DATA(SCIFA7_CTS__MARK, PORT13_FN2), | ||
| 835 | PINMUX_DATA(GPO7_MARK, PORT14_FN1), \ | ||
| 836 | PINMUX_DATA(MFG0_OUT2_MARK, PORT14_FN4), | ||
| 837 | PINMUX_DATA(GPO6_MARK, PORT15_FN1), \ | ||
| 838 | PINMUX_DATA(MFG1_OUT2_MARK, PORT15_FN4), | ||
| 839 | PINMUX_DATA(GPO5_MARK, PORT16_FN1), \ | ||
| 840 | PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), \ | ||
| 841 | PINMUX_DATA(FSICOSLDT3_MARK, PORT16_FN3), \ | ||
| 842 | PINMUX_DATA(PORT16_VIO_CKOR_MARK, PORT16_FN4), | ||
| 843 | PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2), | ||
| 844 | PINMUX_DATA(SCIFA7_TXD_MARK, PORT18_FN2), | ||
| 845 | PINMUX_DATA(SCIFA7_RTS__MARK, PORT19_FN2), \ | ||
| 846 | PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3), | ||
| 847 | PINMUX_DATA(GPO0_MARK, PORT20_FN1), | ||
| 848 | PINMUX_DATA(GPO1_MARK, PORT21_FN1), | ||
| 849 | PINMUX_DATA(GPO2_MARK, PORT22_FN1), \ | ||
| 850 | PINMUX_DATA(STATUS0_MARK, PORT22_FN2), | ||
| 851 | PINMUX_DATA(GPO3_MARK, PORT23_FN1), \ | ||
| 852 | PINMUX_DATA(STATUS1_MARK, PORT23_FN2), | ||
| 853 | PINMUX_DATA(GPO4_MARK, PORT24_FN1), \ | ||
| 854 | PINMUX_DATA(STATUS2_MARK, PORT24_FN2), | ||
| 855 | PINMUX_DATA(VINT_MARK, PORT25_FN1), | ||
| 856 | PINMUX_DATA(TCKON_MARK, PORT26_FN1), | ||
| 857 | PINMUX_DATA(XDVFS1_MARK, PORT27_FN1), \ | ||
| 858 | PINMUX_DATA(PORT27_I2C_SCL2_MARK, PORT27_FN2, MSEL2CR_MSEL17_0, | ||
| 859 | MSEL2CR_MSEL16_1), \ | ||
| 860 | PINMUX_DATA(PORT27_I2C_SCL3_MARK, PORT27_FN3, MSEL2CR_MSEL19_0, | ||
| 861 | MSEL2CR_MSEL18_0), \ | ||
| 862 | PINMUX_DATA(MFG0_OUT1_MARK, PORT27_FN4), \ | ||
| 863 | PINMUX_DATA(PORT27_IROUT_MARK, PORT27_FN7), | ||
| 864 | PINMUX_DATA(XDVFS2_MARK, PORT28_FN1), \ | ||
| 865 | PINMUX_DATA(PORT28_I2C_SDA2_MARK, PORT28_FN2, MSEL2CR_MSEL17_0, | ||
| 866 | MSEL2CR_MSEL16_1), \ | ||
| 867 | PINMUX_DATA(PORT28_I2C_SDA3_MARK, PORT28_FN3, MSEL2CR_MSEL19_0, | ||
| 868 | MSEL2CR_MSEL18_0), \ | ||
| 869 | PINMUX_DATA(PORT28_TPU1TO1_MARK, PORT28_FN7), | ||
| 870 | PINMUX_DATA(SIM_RST_MARK, PORT29_FN1), \ | ||
| 871 | PINMUX_DATA(PORT29_TPU1TO1_MARK, PORT29_FN4), | ||
| 872 | PINMUX_DATA(SIM_CLK_MARK, PORT30_FN1), \ | ||
| 873 | PINMUX_DATA(PORT30_VIO_CKOR_MARK, PORT30_FN4), | ||
| 874 | PINMUX_DATA(SIM_D_MARK, PORT31_FN1), \ | ||
| 875 | PINMUX_DATA(PORT31_IROUT_MARK, PORT31_FN4), | ||
| 876 | PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2), | ||
| 877 | PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), \ | ||
| 878 | PINMUX_DATA(XWUP_MARK, PORT33_FN3), | ||
| 879 | PINMUX_DATA(SCIFA4_RTS__MARK, PORT34_FN2), | ||
| 880 | PINMUX_DATA(SCIFA4_CTS__MARK, PORT35_FN2), | ||
| 881 | PINMUX_DATA(FSIBOBT_MARK, PORT36_FN1), \ | ||
| 882 | PINMUX_DATA(FSIBIBT_MARK, PORT36_FN2), | ||
| 883 | PINMUX_DATA(FSIBOLR_MARK, PORT37_FN1), \ | ||
| 884 | PINMUX_DATA(FSIBILR_MARK, PORT37_FN2), | ||
| 885 | PINMUX_DATA(FSIBOSLD_MARK, PORT38_FN1), | ||
| 886 | PINMUX_DATA(FSIBISLD_MARK, PORT39_FN1), | ||
| 887 | PINMUX_DATA(VACK_MARK, PORT40_FN1), | ||
| 888 | PINMUX_DATA(XTAL1L_MARK, PORT41_FN1), | ||
| 889 | PINMUX_DATA(SCIFA0_RTS__MARK, PORT42_FN2), \ | ||
| 890 | PINMUX_DATA(FSICOSLDT2_MARK, PORT42_FN3), | ||
| 891 | PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2), | ||
| 892 | PINMUX_DATA(SCIFA0_CTS__MARK, PORT44_FN2), \ | ||
| 893 | PINMUX_DATA(FSICOSLDT1_MARK, PORT44_FN3), | ||
| 894 | PINMUX_DATA(FSICOBT_MARK, PORT45_FN1), \ | ||
| 895 | PINMUX_DATA(FSICIBT_MARK, PORT45_FN2), \ | ||
| 896 | PINMUX_DATA(FSIDOBT_MARK, PORT45_FN3), \ | ||
| 897 | PINMUX_DATA(FSIDIBT_MARK, PORT45_FN4), | ||
| 898 | PINMUX_DATA(FSICOLR_MARK, PORT46_FN1), \ | ||
| 899 | PINMUX_DATA(FSICILR_MARK, PORT46_FN2), \ | ||
| 900 | PINMUX_DATA(FSIDOLR_MARK, PORT46_FN3), \ | ||
| 901 | PINMUX_DATA(FSIDILR_MARK, PORT46_FN4), | ||
| 902 | PINMUX_DATA(FSICOSLD_MARK, PORT47_FN1), \ | ||
| 903 | PINMUX_DATA(PORT47_FSICSPDIF_MARK, PORT47_FN2), | ||
| 904 | PINMUX_DATA(FSICISLD_MARK, PORT48_FN1), \ | ||
| 905 | PINMUX_DATA(FSIDISLD_MARK, PORT48_FN3), | ||
| 906 | PINMUX_DATA(FSIACK_MARK, PORT49_FN1), \ | ||
| 907 | PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2, MSEL4CR_MSEL19_1), \ | ||
| 908 | PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN4), \ | ||
| 909 | PINMUX_DATA(FSIAOMC_MARK, PORT49_FN5), | ||
| 910 | PINMUX_DATA(FSIAOLR_MARK, PORT50_FN1), \ | ||
| 911 | PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), \ | ||
| 912 | PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), \ | ||
| 913 | PINMUX_DATA(FSIAILR_MARK, PORT50_FN5), | ||
| 914 | |||
| 915 | PINMUX_DATA(FSIAOBT_MARK, PORT51_FN1), \ | ||
| 916 | PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), \ | ||
| 917 | PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), \ | ||
| 918 | PINMUX_DATA(FSIAIBT_MARK, PORT51_FN5), | ||
| 919 | PINMUX_DATA(FSIAOSLD_MARK, PORT52_FN1), \ | ||
| 920 | PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2), | ||
| 921 | PINMUX_DATA(FSIASPDIF_MARK, PORT53_FN1), \ | ||
| 922 | PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2, MSEL4CR_MSEL19_1), \ | ||
| 923 | PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), \ | ||
| 924 | PINMUX_DATA(FSIBSPDIF_MARK, PORT53_FN5), \ | ||
| 925 | PINMUX_DATA(PORT53_FSICSPDIF_MARK, PORT53_FN6), | ||
| 926 | PINMUX_DATA(FSIBCK_MARK, PORT54_FN1), \ | ||
| 927 | PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2, MSEL4CR_MSEL19_1), \ | ||
| 928 | PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), \ | ||
| 929 | PINMUX_DATA(FSIBOMC_MARK, PORT54_FN5), \ | ||
| 930 | PINMUX_DATA(FSICCK_MARK, PORT54_FN6), \ | ||
| 931 | PINMUX_DATA(FSICOMC_MARK, PORT54_FN7), | ||
| 932 | PINMUX_DATA(FSIAISLD_MARK, PORT55_FN1), \ | ||
| 933 | PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3), | ||
| 934 | PINMUX_DATA(A0_MARK, PORT57_FN1), \ | ||
| 935 | PINMUX_DATA(BS__MARK, PORT57_FN2), | ||
| 936 | PINMUX_DATA(A12_MARK, PORT58_FN1), \ | ||
| 937 | PINMUX_DATA(PORT58_KEYOUT7_MARK, PORT58_FN2), \ | ||
| 938 | PINMUX_DATA(TPU4TO2_MARK, PORT58_FN4), | ||
| 939 | PINMUX_DATA(A13_MARK, PORT59_FN1), \ | ||
| 940 | PINMUX_DATA(PORT59_KEYOUT6_MARK, PORT59_FN2), \ | ||
| 941 | PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4), | ||
| 942 | PINMUX_DATA(A14_MARK, PORT60_FN1), \ | ||
| 943 | PINMUX_DATA(KEYOUT5_MARK, PORT60_FN2), | ||
| 944 | PINMUX_DATA(A15_MARK, PORT61_FN1), \ | ||
| 945 | PINMUX_DATA(KEYOUT4_MARK, PORT61_FN2), | ||
| 946 | PINMUX_DATA(A16_MARK, PORT62_FN1), \ | ||
| 947 | PINMUX_DATA(KEYOUT3_MARK, PORT62_FN2), \ | ||
| 948 | PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN4, MSEL3CR_MSEL11_0), | ||
| 949 | PINMUX_DATA(A17_MARK, PORT63_FN1), \ | ||
| 950 | PINMUX_DATA(KEYOUT2_MARK, PORT63_FN2), \ | ||
| 951 | PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN4, MSEL3CR_MSEL11_0), | ||
| 952 | PINMUX_DATA(A18_MARK, PORT64_FN1), \ | ||
| 953 | PINMUX_DATA(KEYOUT1_MARK, PORT64_FN2), \ | ||
| 954 | PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN4, MSEL3CR_MSEL11_0), | ||
| 955 | PINMUX_DATA(A19_MARK, PORT65_FN1), \ | ||
| 956 | PINMUX_DATA(KEYOUT0_MARK, PORT65_FN2), \ | ||
| 957 | PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN4, MSEL3CR_MSEL11_0), | ||
| 958 | PINMUX_DATA(A20_MARK, PORT66_FN1), \ | ||
| 959 | PINMUX_DATA(KEYIN0_MARK, PORT66_FN2), \ | ||
| 960 | PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN4, MSEL3CR_MSEL11_0), | ||
| 961 | PINMUX_DATA(A21_MARK, PORT67_FN1), \ | ||
| 962 | PINMUX_DATA(KEYIN1_MARK, PORT67_FN2), \ | ||
| 963 | PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN4, MSEL3CR_MSEL11_0), | ||
| 964 | PINMUX_DATA(A22_MARK, PORT68_FN1), \ | ||
| 965 | PINMUX_DATA(KEYIN2_MARK, PORT68_FN2), \ | ||
| 966 | PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN4, MSEL3CR_MSEL11_0), | ||
| 967 | PINMUX_DATA(A23_MARK, PORT69_FN1), \ | ||
| 968 | PINMUX_DATA(KEYIN3_MARK, PORT69_FN2), \ | ||
| 969 | PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN4, MSEL3CR_MSEL11_0), | ||
| 970 | PINMUX_DATA(A24_MARK, PORT70_FN1), \ | ||
| 971 | PINMUX_DATA(KEYIN4_MARK, PORT70_FN2), \ | ||
| 972 | PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN4, MSEL3CR_MSEL11_0), | ||
| 973 | PINMUX_DATA(A25_MARK, PORT71_FN1), \ | ||
| 974 | PINMUX_DATA(KEYIN5_MARK, PORT71_FN2), \ | ||
| 975 | PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN4, MSEL3CR_MSEL11_0), | ||
| 976 | PINMUX_DATA(A26_MARK, PORT72_FN1), \ | ||
| 977 | PINMUX_DATA(KEYIN6_MARK, PORT72_FN2), | ||
| 978 | PINMUX_DATA(KEYIN7_MARK, PORT73_FN2), | ||
| 979 | PINMUX_DATA(D0_NAF0_MARK, PORT74_FN1), | ||
| 980 | PINMUX_DATA(D1_NAF1_MARK, PORT75_FN1), | ||
| 981 | PINMUX_DATA(D2_NAF2_MARK, PORT76_FN1), | ||
| 982 | PINMUX_DATA(D3_NAF3_MARK, PORT77_FN1), | ||
| 983 | PINMUX_DATA(D4_NAF4_MARK, PORT78_FN1), | ||
| 984 | PINMUX_DATA(D5_NAF5_MARK, PORT79_FN1), | ||
| 985 | PINMUX_DATA(D6_NAF6_MARK, PORT80_FN1), | ||
| 986 | PINMUX_DATA(D7_NAF7_MARK, PORT81_FN1), | ||
| 987 | PINMUX_DATA(D8_NAF8_MARK, PORT82_FN1), | ||
| 988 | PINMUX_DATA(D9_NAF9_MARK, PORT83_FN1), | ||
| 989 | PINMUX_DATA(D10_NAF10_MARK, PORT84_FN1), | ||
| 990 | PINMUX_DATA(D11_NAF11_MARK, PORT85_FN1), | ||
| 991 | PINMUX_DATA(D12_NAF12_MARK, PORT86_FN1), | ||
| 992 | PINMUX_DATA(D13_NAF13_MARK, PORT87_FN1), | ||
| 993 | PINMUX_DATA(D14_NAF14_MARK, PORT88_FN1), | ||
| 994 | PINMUX_DATA(D15_NAF15_MARK, PORT89_FN1), | ||
| 995 | PINMUX_DATA(CS4__MARK, PORT90_FN1), | ||
| 996 | PINMUX_DATA(CS5A__MARK, PORT91_FN1), \ | ||
| 997 | PINMUX_DATA(PORT91_RDWR_MARK, PORT91_FN2), | ||
| 998 | PINMUX_DATA(CS5B__MARK, PORT92_FN1), \ | ||
| 999 | PINMUX_DATA(FCE1__MARK, PORT92_FN2), | ||
| 1000 | PINMUX_DATA(CS6B__MARK, PORT93_FN1), \ | ||
| 1001 | PINMUX_DATA(DACK0_MARK, PORT93_FN4), | ||
| 1002 | PINMUX_DATA(FCE0__MARK, PORT94_FN1), \ | ||
| 1003 | PINMUX_DATA(CS6A__MARK, PORT94_FN2), | ||
| 1004 | PINMUX_DATA(WAIT__MARK, PORT95_FN1), \ | ||
| 1005 | PINMUX_DATA(DREQ0_MARK, PORT95_FN2), | ||
| 1006 | PINMUX_DATA(RD__FSC_MARK, PORT96_FN1), | ||
| 1007 | PINMUX_DATA(WE0__FWE_MARK, PORT97_FN1), \ | ||
| 1008 | PINMUX_DATA(RDWR_FWE_MARK, PORT97_FN2), | ||
| 1009 | PINMUX_DATA(WE1__MARK, PORT98_FN1), | ||
| 1010 | PINMUX_DATA(FRB_MARK, PORT99_FN1), | ||
| 1011 | PINMUX_DATA(CKO_MARK, PORT100_FN1), | ||
| 1012 | PINMUX_DATA(NBRSTOUT__MARK, PORT101_FN1), | ||
| 1013 | PINMUX_DATA(NBRST__MARK, PORT102_FN1), | ||
| 1014 | PINMUX_DATA(BBIF2_TXD_MARK, PORT103_FN3), | ||
| 1015 | PINMUX_DATA(BBIF2_RXD_MARK, PORT104_FN3), | ||
| 1016 | PINMUX_DATA(BBIF2_SYNC_MARK, PORT105_FN3), | ||
| 1017 | PINMUX_DATA(BBIF2_SCK_MARK, PORT106_FN3), | ||
| 1018 | PINMUX_DATA(SCIFA3_CTS__MARK, PORT107_FN3), \ | ||
| 1019 | PINMUX_DATA(MFG3_IN2_MARK, PORT107_FN4), | ||
| 1020 | PINMUX_DATA(SCIFA3_RXD_MARK, PORT108_FN3), \ | ||
| 1021 | PINMUX_DATA(MFG3_IN1_MARK, PORT108_FN4), | ||
| 1022 | PINMUX_DATA(BBIF1_SS2_MARK, PORT109_FN2), \ | ||
| 1023 | PINMUX_DATA(SCIFA3_RTS__MARK, PORT109_FN3), \ | ||
| 1024 | PINMUX_DATA(MFG3_OUT1_MARK, PORT109_FN4), | ||
| 1025 | PINMUX_DATA(SCIFA3_TXD_MARK, PORT110_FN3), | ||
| 1026 | PINMUX_DATA(HSI_RX_DATA_MARK, PORT111_FN1), \ | ||
| 1027 | PINMUX_DATA(BBIF1_RXD_MARK, PORT111_FN3), | ||
| 1028 | PINMUX_DATA(HSI_TX_WAKE_MARK, PORT112_FN1), \ | ||
| 1029 | PINMUX_DATA(BBIF1_TSCK_MARK, PORT112_FN3), | ||
| 1030 | PINMUX_DATA(HSI_TX_DATA_MARK, PORT113_FN1), \ | ||
| 1031 | PINMUX_DATA(BBIF1_TSYNC_MARK, PORT113_FN3), | ||
| 1032 | PINMUX_DATA(HSI_TX_READY_MARK, PORT114_FN1), \ | ||
| 1033 | PINMUX_DATA(BBIF1_TXD_MARK, PORT114_FN3), | ||
| 1034 | PINMUX_DATA(HSI_RX_READY_MARK, PORT115_FN1), \ | ||
| 1035 | PINMUX_DATA(BBIF1_RSCK_MARK, PORT115_FN3), \ | ||
| 1036 | PINMUX_DATA(PORT115_I2C_SCL2_MARK, PORT115_FN5, MSEL2CR_MSEL17_1), \ | ||
| 1037 | PINMUX_DATA(PORT115_I2C_SCL3_MARK, PORT115_FN6, MSEL2CR_MSEL19_1), | ||
| 1038 | PINMUX_DATA(HSI_RX_WAKE_MARK, PORT116_FN1), \ | ||
| 1039 | PINMUX_DATA(BBIF1_RSYNC_MARK, PORT116_FN3), \ | ||
| 1040 | PINMUX_DATA(PORT116_I2C_SDA2_MARK, PORT116_FN5, MSEL2CR_MSEL17_1), \ | ||
| 1041 | PINMUX_DATA(PORT116_I2C_SDA3_MARK, PORT116_FN6, MSEL2CR_MSEL19_1), | ||
| 1042 | PINMUX_DATA(HSI_RX_FLAG_MARK, PORT117_FN1), \ | ||
| 1043 | PINMUX_DATA(BBIF1_SS1_MARK, PORT117_FN2), \ | ||
| 1044 | PINMUX_DATA(BBIF1_FLOW_MARK, PORT117_FN3), | ||
| 1045 | PINMUX_DATA(HSI_TX_FLAG_MARK, PORT118_FN1), | ||
| 1046 | PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), \ | ||
| 1047 | PINMUX_DATA(PORT128_LCD2VSYN_MARK, PORT128_FN4, MSEL3CR_MSEL2_0), \ | ||
| 1048 | PINMUX_DATA(VIO2_VD_MARK, PORT128_FN6, MSEL4CR_MSEL27_0), \ | ||
| 1049 | PINMUX_DATA(LCD2D0_MARK, PORT128_FN7), | ||
| 1050 | |||
| 1051 | PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), \ | ||
| 1052 | PINMUX_DATA(PORT129_LCD2HSYN_MARK, PORT129_FN4), \ | ||
| 1053 | PINMUX_DATA(PORT129_LCD2CS__MARK, PORT129_FN5), \ | ||
| 1054 | PINMUX_DATA(VIO2_HD_MARK, PORT129_FN6, MSEL4CR_MSEL27_0), \ | ||
| 1055 | PINMUX_DATA(LCD2D1_MARK, PORT129_FN7), | ||
| 1056 | PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), \ | ||
| 1057 | PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3, MSEL4CR_MSEL11_0, | ||
| 1058 | MSEL4CR_MSEL10_1), \ | ||
| 1059 | PINMUX_DATA(LCD2D10_MARK, PORT130_FN7), | ||
| 1060 | PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), \ | ||
| 1061 | PINMUX_DATA(PORT131_KEYOUT6_MARK, PORT131_FN2), \ | ||
| 1062 | PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), \ | ||
| 1063 | PINMUX_DATA(PORT131_KEYOUT11_MARK, PORT131_FN4), \ | ||
| 1064 | PINMUX_DATA(LCD2D11_MARK, PORT131_FN7), | ||
| 1065 | PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), \ | ||
| 1066 | PINMUX_DATA(PORT132_KEYOUT7_MARK, PORT132_FN2), \ | ||
| 1067 | PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), \ | ||
| 1068 | PINMUX_DATA(PORT132_KEYOUT10_MARK, PORT132_FN4), \ | ||
| 1069 | PINMUX_DATA(LCD2D12_MARK, PORT132_FN7), | ||
| 1070 | PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), \ | ||
| 1071 | PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT133_FN3, MSEL4CR_MSEL11_0), \ | ||
| 1072 | PINMUX_DATA(LCD2D13_MARK, PORT133_FN7), | ||
| 1073 | PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), \ | ||
| 1074 | PINMUX_DATA(MSIOF2_TXD_MARK, PORT134_FN3, MSEL4CR_MSEL11_0), \ | ||
| 1075 | PINMUX_DATA(LCD2D14_MARK, PORT134_FN7), | ||
| 1076 | PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), \ | ||
| 1077 | PINMUX_DATA(MSIOF2_TSCK_MARK, PORT135_FN3, MSEL4CR_MSEL11_0), \ | ||
| 1078 | PINMUX_DATA(LCD2D15_MARK, PORT135_FN7), | ||
| 1079 | PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), \ | ||
| 1080 | PINMUX_DATA(PORT136_KEYOUT8_MARK, PORT136_FN2), \ | ||
| 1081 | PINMUX_DATA(LCD2D16_MARK, PORT136_FN7), | ||
| 1082 | PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), \ | ||
| 1083 | PINMUX_DATA(PORT137_KEYOUT9_MARK, PORT137_FN2), \ | ||
| 1084 | PINMUX_DATA(LCD2D17_MARK, PORT137_FN7), | ||
| 1085 | PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), \ | ||
| 1086 | PINMUX_DATA(PORT138_KEYOUT8_MARK, PORT138_FN2), \ | ||
| 1087 | PINMUX_DATA(VIO2_D0_MARK, PORT138_FN6), \ | ||
| 1088 | PINMUX_DATA(LCD2D6_MARK, PORT138_FN7), | ||
| 1089 | PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), \ | ||
| 1090 | PINMUX_DATA(PORT139_KEYOUT9_MARK, PORT139_FN2), \ | ||
| 1091 | PINMUX_DATA(VIO2_D1_MARK, PORT139_FN6), \ | ||
| 1092 | PINMUX_DATA(LCD2D7_MARK, PORT139_FN7), | ||
| 1093 | PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), \ | ||
| 1094 | PINMUX_DATA(TPU0TO2_MARK, PORT140_FN4), \ | ||
| 1095 | PINMUX_DATA(VIO2_D2_MARK, PORT140_FN6), \ | ||
| 1096 | PINMUX_DATA(LCD2D8_MARK, PORT140_FN7), | ||
| 1097 | PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), \ | ||
| 1098 | PINMUX_DATA(TPU0TO3_MARK, PORT141_FN4), \ | ||
| 1099 | PINMUX_DATA(VIO2_D3_MARK, PORT141_FN6), \ | ||
| 1100 | PINMUX_DATA(LCD2D9_MARK, PORT141_FN7), | ||
| 1101 | PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), \ | ||
| 1102 | PINMUX_DATA(PORT142_KEYOUT10_MARK, PORT142_FN2), \ | ||
| 1103 | PINMUX_DATA(VIO2_D4_MARK, PORT142_FN6), \ | ||
| 1104 | PINMUX_DATA(LCD2D2_MARK, PORT142_FN7), | ||
| 1105 | PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), \ | ||
| 1106 | PINMUX_DATA(PORT143_KEYOUT11_MARK, PORT143_FN2), \ | ||
| 1107 | PINMUX_DATA(PORT143_KEYOUT6_MARK, PORT143_FN3), \ | ||
| 1108 | PINMUX_DATA(VIO2_D5_MARK, PORT143_FN6), \ | ||
| 1109 | PINMUX_DATA(LCD2D3_MARK, PORT143_FN7), | ||
| 1110 | PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), \ | ||
| 1111 | PINMUX_DATA(PORT144_KEYOUT7_MARK, PORT144_FN2), \ | ||
| 1112 | PINMUX_DATA(VIO2_D6_MARK, PORT144_FN6), \ | ||
| 1113 | PINMUX_DATA(LCD2D4_MARK, PORT144_FN7), | ||
| 1114 | PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), \ | ||
| 1115 | PINMUX_DATA(TPU1TO3_MARK, PORT145_FN3), \ | ||
| 1116 | PINMUX_DATA(PORT145_LCD2DISP_MARK, PORT145_FN4), \ | ||
| 1117 | PINMUX_DATA(PORT145_LCD2RS_MARK, PORT145_FN5), \ | ||
| 1118 | PINMUX_DATA(VIO2_D7_MARK, PORT145_FN6), \ | ||
| 1119 | PINMUX_DATA(LCD2D5_MARK, PORT145_FN7), | ||
| 1120 | PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), \ | ||
| 1121 | PINMUX_DATA(LCD2DCK_MARK, PORT146_FN4), \ | ||
| 1122 | PINMUX_DATA(PORT146_LCD2WR__MARK, PORT146_FN5), \ | ||
| 1123 | PINMUX_DATA(VIO2_CLK_MARK, PORT146_FN6, MSEL4CR_MSEL27_0), \ | ||
| 1124 | PINMUX_DATA(LCD2D18_MARK, PORT146_FN7), | ||
| 1125 | PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), \ | ||
| 1126 | PINMUX_DATA(LCD2RD__MARK, PORT147_FN4), \ | ||
| 1127 | PINMUX_DATA(VIO2_FIELD_MARK, PORT147_FN6, MSEL4CR_MSEL27_0), \ | ||
| 1128 | PINMUX_DATA(LCD2D19_MARK, PORT147_FN7), | ||
| 1129 | PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1), | ||
| 1130 | PINMUX_DATA(A27_MARK, PORT149_FN1), \ | ||
| 1131 | PINMUX_DATA(PORT149_RDWR_MARK, PORT149_FN2), \ | ||
| 1132 | PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), \ | ||
| 1133 | PINMUX_DATA(PORT149_KEYOUT9_MARK, PORT149_FN4), | ||
| 1134 | PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN3), | ||
| 1135 | PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN4), \ | ||
| 1136 | PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN5), | ||
| 1137 | PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN4), \ | ||
| 1138 | PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN5), | ||
| 1139 | PINMUX_DATA(TPU1TO2_MARK, PORT153_FN3), \ | ||
| 1140 | PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN4), \ | ||
| 1141 | PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN5), | ||
| 1142 | PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2, MSEL3CR_MSEL9_0), \ | ||
| 1143 | PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN5), | ||
| 1144 | PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2, MSEL3CR_MSEL9_0), \ | ||
| 1145 | PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN5), | ||
| 1146 | PINMUX_DATA(SCIFA2_RTS1__MARK, PORT156_FN2, MSEL3CR_MSEL9_0), \ | ||
| 1147 | PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN5), | ||
| 1148 | PINMUX_DATA(SCIFA2_CTS1__MARK, PORT157_FN2, MSEL3CR_MSEL9_0), \ | ||
| 1149 | PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN5, MSEL4CR_MSEL11_0, | ||
| 1150 | MSEL4CR_MSEL10_0), | ||
| 1151 | PINMUX_DATA(DINT__MARK, PORT158_FN1), \ | ||
| 1152 | PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2, MSEL3CR_MSEL9_0), \ | ||
| 1153 | PINMUX_DATA(TS_SCK3_MARK, PORT158_FN4), | ||
| 1154 | PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1, MSEL4CR_MSEL22_0), \ | ||
| 1155 | PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2, MSEL4CR_MSEL21_1), \ | ||
| 1156 | PINMUX_DATA(NMI_MARK, PORT159_FN3), | ||
| 1157 | PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1, MSEL4CR_MSEL22_0), \ | ||
| 1158 | PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2, MSEL4CR_MSEL21_1), | ||
| 1159 | PINMUX_DATA(PORT161_SCIFB_CTS__MARK, PORT161_FN1, MSEL4CR_MSEL22_0), \ | ||
| 1160 | PINMUX_DATA(PORT161_SCIFA5_CTS__MARK, PORT161_FN2, MSEL4CR_MSEL21_1), | ||
| 1161 | PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1, MSEL4CR_MSEL22_0), \ | ||
| 1162 | PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2, MSEL4CR_MSEL21_1), | ||
| 1163 | PINMUX_DATA(PORT163_SCIFB_RTS__MARK, PORT163_FN1, MSEL4CR_MSEL22_0), \ | ||
| 1164 | PINMUX_DATA(PORT163_SCIFA5_RTS__MARK, PORT163_FN2, MSEL4CR_MSEL21_1), \ | ||
| 1165 | PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5), | ||
| 1166 | PINMUX_DATA(LCDD0_MARK, PORT192_FN1), | ||
| 1167 | PINMUX_DATA(LCDD1_MARK, PORT193_FN1), \ | ||
| 1168 | PINMUX_DATA(PORT193_SCIFA5_CTS__MARK, PORT193_FN3, MSEL4CR_MSEL21_0, | ||
| 1169 | MSEL4CR_MSEL20_1), \ | ||
| 1170 | PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN5), | ||
| 1171 | PINMUX_DATA(LCDD2_MARK, PORT194_FN1), \ | ||
| 1172 | PINMUX_DATA(PORT194_SCIFA5_RTS__MARK, PORT194_FN3, MSEL4CR_MSEL21_0, | ||
| 1173 | MSEL4CR_MSEL20_1), \ | ||
| 1174 | PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN5), | ||
| 1175 | PINMUX_DATA(LCDD3_MARK, PORT195_FN1), \ | ||
| 1176 | PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3, MSEL4CR_MSEL21_0, | ||
| 1177 | MSEL4CR_MSEL20_1), \ | ||
| 1178 | PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN5), | ||
| 1179 | PINMUX_DATA(LCDD4_MARK, PORT196_FN1), \ | ||
| 1180 | PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3, MSEL4CR_MSEL21_0, | ||
| 1181 | MSEL4CR_MSEL20_1), | ||
| 1182 | PINMUX_DATA(LCDD5_MARK, PORT197_FN1), \ | ||
| 1183 | PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3, MSEL4CR_MSEL21_0, | ||
| 1184 | MSEL4CR_MSEL20_1), \ | ||
| 1185 | PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN5), \ | ||
| 1186 | PINMUX_DATA(TPU2TO1_MARK, PORT197_FN7), | ||
| 1187 | PINMUX_DATA(LCDD6_MARK, PORT198_FN1), | ||
| 1188 | PINMUX_DATA(LCDD7_MARK, PORT199_FN1), \ | ||
| 1189 | PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), \ | ||
| 1190 | PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN5), | ||
| 1191 | PINMUX_DATA(LCDD8_MARK, PORT200_FN1), \ | ||
| 1192 | PINMUX_DATA(D16_MARK, PORT200_FN6), | ||
| 1193 | PINMUX_DATA(LCDD9_MARK, PORT201_FN1), \ | ||
| 1194 | PINMUX_DATA(D17_MARK, PORT201_FN6), | ||
| 1195 | PINMUX_DATA(LCDD10_MARK, PORT202_FN1), \ | ||
| 1196 | PINMUX_DATA(D18_MARK, PORT202_FN6), | ||
| 1197 | PINMUX_DATA(LCDD11_MARK, PORT203_FN1), \ | ||
| 1198 | PINMUX_DATA(D19_MARK, PORT203_FN6), | ||
| 1199 | PINMUX_DATA(LCDD12_MARK, PORT204_FN1), \ | ||
| 1200 | PINMUX_DATA(D20_MARK, PORT204_FN6), | ||
| 1201 | PINMUX_DATA(LCDD13_MARK, PORT205_FN1), \ | ||
| 1202 | PINMUX_DATA(D21_MARK, PORT205_FN6), | ||
| 1203 | PINMUX_DATA(LCDD14_MARK, PORT206_FN1), \ | ||
| 1204 | PINMUX_DATA(D22_MARK, PORT206_FN6), | ||
| 1205 | PINMUX_DATA(LCDD15_MARK, PORT207_FN1), \ | ||
| 1206 | PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2, MSEL3CR_MSEL11_1), \ | ||
| 1207 | PINMUX_DATA(D23_MARK, PORT207_FN6), | ||
| 1208 | PINMUX_DATA(LCDD16_MARK, PORT208_FN1), \ | ||
| 1209 | PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2, MSEL3CR_MSEL11_1), \ | ||
| 1210 | PINMUX_DATA(D24_MARK, PORT208_FN6), | ||
| 1211 | PINMUX_DATA(LCDD17_MARK, PORT209_FN1), \ | ||
| 1212 | PINMUX_DATA(D25_MARK, PORT209_FN6), | ||
| 1213 | PINMUX_DATA(LCDD18_MARK, PORT210_FN1), \ | ||
| 1214 | PINMUX_DATA(DREQ2_MARK, PORT210_FN2), \ | ||
| 1215 | PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN5, MSEL3CR_MSEL11_1), \ | ||
| 1216 | PINMUX_DATA(D26_MARK, PORT210_FN6), | ||
| 1217 | PINMUX_DATA(LCDD19_MARK, PORT211_FN1), \ | ||
| 1218 | PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN5, MSEL3CR_MSEL11_1), \ | ||
| 1219 | PINMUX_DATA(D27_MARK, PORT211_FN6), | ||
| 1220 | PINMUX_DATA(LCDD20_MARK, PORT212_FN1), \ | ||
| 1221 | PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), \ | ||
| 1222 | PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN5, MSEL3CR_MSEL11_1), \ | ||
| 1223 | PINMUX_DATA(D28_MARK, PORT212_FN6), | ||
| 1224 | PINMUX_DATA(LCDD21_MARK, PORT213_FN1), \ | ||
| 1225 | PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), \ | ||
| 1226 | PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN5, MSEL3CR_MSEL11_1), \ | ||
| 1227 | PINMUX_DATA(D29_MARK, PORT213_FN6), | ||
| 1228 | PINMUX_DATA(LCDD22_MARK, PORT214_FN1), \ | ||
| 1229 | PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), \ | ||
| 1230 | PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN5, MSEL3CR_MSEL11_1), \ | ||
| 1231 | PINMUX_DATA(D30_MARK, PORT214_FN6), | ||
| 1232 | PINMUX_DATA(LCDD23_MARK, PORT215_FN1), \ | ||
| 1233 | PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), \ | ||
| 1234 | PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN5, MSEL3CR_MSEL11_1), \ | ||
| 1235 | PINMUX_DATA(D31_MARK, PORT215_FN6), | ||
| 1236 | PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), \ | ||
| 1237 | PINMUX_DATA(LCDWR__MARK, PORT216_FN2), | ||
| 1238 | PINMUX_DATA(LCDRD__MARK, PORT217_FN1), \ | ||
| 1239 | PINMUX_DATA(DACK2_MARK, PORT217_FN2), \ | ||
| 1240 | PINMUX_DATA(PORT217_LCD2RS_MARK, PORT217_FN3), \ | ||
| 1241 | PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN5, MSEL3CR_MSEL11_1), \ | ||
| 1242 | PINMUX_DATA(VIO2_FIELD3_MARK, PORT217_FN6, MSEL4CR_MSEL27_1, | ||
| 1243 | MSEL4CR_MSEL26_1), \ | ||
| 1244 | PINMUX_DATA(PORT217_LCD2DISP_MARK, PORT217_FN7), | ||
| 1245 | PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), \ | ||
| 1246 | PINMUX_DATA(LCDCS__MARK, PORT218_FN2), \ | ||
| 1247 | PINMUX_DATA(LCDCS2__MARK, PORT218_FN3), \ | ||
| 1248 | PINMUX_DATA(DACK3_MARK, PORT218_FN4), \ | ||
| 1249 | PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5), | ||
| 1250 | PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), \ | ||
| 1251 | PINMUX_DATA(LCDRS_MARK, PORT219_FN2), \ | ||
| 1252 | PINMUX_DATA(PORT219_LCD2WR__MARK, PORT219_FN3), \ | ||
| 1253 | PINMUX_DATA(DREQ3_MARK, PORT219_FN4), \ | ||
| 1254 | PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN5, MSEL3CR_MSEL11_1), \ | ||
| 1255 | PINMUX_DATA(VIO2_CLK3_MARK, PORT219_FN6, MSEL4CR_MSEL27_1, | ||
| 1256 | MSEL4CR_MSEL26_1), \ | ||
| 1257 | PINMUX_DATA(LCD2DCK_2_MARK, PORT219_FN7), | ||
| 1258 | PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), \ | ||
| 1259 | PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2), | ||
| 1260 | PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), \ | ||
| 1261 | PINMUX_DATA(DREQ1_MARK, PORT221_FN2), \ | ||
| 1262 | PINMUX_DATA(PORT221_LCD2CS__MARK, PORT221_FN3), \ | ||
| 1263 | PINMUX_DATA(PWEN_MARK, PORT221_FN4), \ | ||
| 1264 | PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN5, MSEL3CR_MSEL11_1), \ | ||
| 1265 | PINMUX_DATA(VIO2_HD3_MARK, PORT221_FN6, MSEL4CR_MSEL27_1, | ||
| 1266 | MSEL4CR_MSEL26_1), \ | ||
| 1267 | PINMUX_DATA(PORT221_LCD2HSYN_MARK, PORT221_FN7), | ||
| 1268 | PINMUX_DATA(LCDDON_MARK, PORT222_FN1), \ | ||
| 1269 | PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), \ | ||
| 1270 | PINMUX_DATA(DACK1_MARK, PORT222_FN3), \ | ||
| 1271 | PINMUX_DATA(OVCN_MARK, PORT222_FN4), \ | ||
| 1272 | PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5, MSEL3CR_MSEL11_1), \ | ||
| 1273 | PINMUX_DATA(VIO2_VD3_MARK, PORT222_FN6, MSEL4CR_MSEL27_1, | ||
| 1274 | MSEL4CR_MSEL26_1), \ | ||
| 1275 | PINMUX_DATA(PORT222_LCD2VSYN_MARK, PORT222_FN7, MSEL3CR_MSEL2_1), | ||
| 1276 | |||
| 1277 | PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN2), \ | ||
| 1278 | PINMUX_DATA(OVCN2_MARK, PORT225_FN4), | ||
| 1279 | PINMUX_DATA(EXTLP_MARK, PORT226_FN1), \ | ||
| 1280 | PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), \ | ||
| 1281 | PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN5), | ||
| 1282 | PINMUX_DATA(SCIFA1_RTS__MARK, PORT227_FN2), \ | ||
| 1283 | PINMUX_DATA(IDIN_MARK, PORT227_FN4), | ||
| 1284 | PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN2), | ||
| 1285 | PINMUX_DATA(SCIFA1_CTS__MARK, PORT229_FN2), \ | ||
| 1286 | PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN3), | ||
| 1287 | PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), \ | ||
| 1288 | PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2, MSEL3CR_MSEL9_1), | ||
| 1289 | PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), \ | ||
| 1290 | PINMUX_DATA(SCIFA2_CTS2__MARK, PORT231_FN2, MSEL3CR_MSEL9_1), | ||
| 1291 | PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), \ | ||
| 1292 | PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2, MSEL3CR_MSEL9_1), | ||
| 1293 | PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), \ | ||
| 1294 | PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2, MSEL3CR_MSEL9_1), | ||
| 1295 | PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), \ | ||
| 1296 | PINMUX_DATA(SCIFA2_RTS2__MARK, PORT234_FN2, MSEL3CR_MSEL9_1), \ | ||
| 1297 | PINMUX_DATA(VIO2_CLK2_MARK, PORT234_FN6, MSEL4CR_MSEL27_1, | ||
| 1298 | MSEL4CR_MSEL26_0), \ | ||
| 1299 | PINMUX_DATA(LCD2D20_MARK, PORT234_FN7), | ||
| 1300 | PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), \ | ||
| 1301 | PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), \ | ||
| 1302 | PINMUX_DATA(VIO2_VD2_MARK, PORT235_FN6, MSEL4CR_MSEL27_1, | ||
| 1303 | MSEL4CR_MSEL26_0), \ | ||
| 1304 | PINMUX_DATA(LCD2D21_MARK, PORT235_FN7), | ||
| 1305 | PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), \ | ||
| 1306 | PINMUX_DATA(PORT236_I2C_SDA2_MARK, PORT236_FN2, MSEL2CR_MSEL17_0, | ||
| 1307 | MSEL2CR_MSEL16_0), | ||
| 1308 | PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), \ | ||
| 1309 | PINMUX_DATA(PORT237_I2C_SCL2_MARK, PORT237_FN2, MSEL2CR_MSEL17_0, | ||
| 1310 | MSEL2CR_MSEL16_0), | ||
| 1311 | PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), \ | ||
| 1312 | PINMUX_DATA(VIO2_FIELD2_MARK, PORT238_FN6, MSEL4CR_MSEL27_1, | ||
| 1313 | MSEL4CR_MSEL26_0), \ | ||
| 1314 | PINMUX_DATA(LCD2D22_MARK, PORT238_FN7), | ||
| 1315 | PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), \ | ||
| 1316 | PINMUX_DATA(VIO2_HD2_MARK, PORT239_FN6, MSEL4CR_MSEL27_1, | ||
| 1317 | MSEL4CR_MSEL26_0), \ | ||
| 1318 | PINMUX_DATA(LCD2D23_MARK, PORT239_FN7), | ||
| 1319 | PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1), | ||
| 1320 | PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1, MSEL4CR_MSEL19_0), \ | ||
| 1321 | PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), \ | ||
| 1322 | PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), \ | ||
| 1323 | PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4), | ||
| 1324 | PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1, MSEL4CR_MSEL19_0), \ | ||
| 1325 | PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN3), | ||
| 1326 | PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1, MSEL4CR_MSEL19_0), \ | ||
| 1327 | PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2), | ||
| 1328 | PINMUX_DATA(PORT244_SCIFA5_CTS__MARK, PORT244_FN1, MSEL4CR_MSEL21_0, | ||
| 1329 | MSEL4CR_MSEL20_0), \ | ||
| 1330 | PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), \ | ||
| 1331 | PINMUX_DATA(PORT244_SCIFB_CTS__MARK, PORT244_FN3, MSEL4CR_MSEL22_1), \ | ||
| 1332 | PINMUX_DATA(MSIOF2R_RXD_MARK, PORT244_FN7, MSEL4CR_MSEL11_1), | ||
| 1333 | PINMUX_DATA(PORT245_SCIFA5_RTS__MARK, PORT245_FN1, MSEL4CR_MSEL21_0, | ||
| 1334 | MSEL4CR_MSEL20_0), \ | ||
| 1335 | PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), \ | ||
| 1336 | PINMUX_DATA(PORT245_SCIFB_RTS__MARK, PORT245_FN3, MSEL4CR_MSEL22_1), \ | ||
| 1337 | PINMUX_DATA(MSIOF2R_TXD_MARK, PORT245_FN7, MSEL4CR_MSEL11_1), | ||
| 1338 | PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1, MSEL4CR_MSEL21_0, | ||
| 1339 | MSEL4CR_MSEL20_0), \ | ||
| 1340 | PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), \ | ||
| 1341 | PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3, MSEL4CR_MSEL22_1), \ | ||
| 1342 | PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4), | ||
| 1343 | PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1, MSEL4CR_MSEL21_0, | ||
| 1344 | MSEL4CR_MSEL20_0), \ | ||
| 1345 | PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), \ | ||
| 1346 | PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3, MSEL4CR_MSEL22_1), \ | ||
| 1347 | PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4), | ||
| 1348 | PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1, MSEL4CR_MSEL21_0, | ||
| 1349 | MSEL4CR_MSEL20_0), \ | ||
| 1350 | PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), \ | ||
| 1351 | PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3, MSEL4CR_MSEL22_1), \ | ||
| 1352 | PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), \ | ||
| 1353 | PINMUX_DATA(PORT248_I2C_SCL3_MARK, PORT248_FN5, MSEL2CR_MSEL19_0, | ||
| 1354 | MSEL2CR_MSEL18_0), \ | ||
| 1355 | PINMUX_DATA(MSIOF2R_TSCK_MARK, PORT248_FN7, MSEL4CR_MSEL11_1), | ||
| 1356 | PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), \ | ||
| 1357 | PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), \ | ||
| 1358 | PINMUX_DATA(PORT249_I2C_SDA3_MARK, PORT249_FN5, MSEL2CR_MSEL19_0, | ||
| 1359 | MSEL2CR_MSEL18_0), \ | ||
| 1360 | PINMUX_DATA(MSIOF2R_TSYNC_MARK, PORT249_FN7, MSEL4CR_MSEL11_1), | ||
| 1361 | PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1), | ||
| 1362 | PINMUX_DATA(SDHICD0_MARK, PORT251_FN1), | ||
| 1363 | PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1), | ||
| 1364 | PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1), | ||
| 1365 | PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1), | ||
| 1366 | PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1), | ||
| 1367 | PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1), | ||
| 1368 | PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1), | ||
| 1369 | PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1), | ||
| 1370 | PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), \ | ||
| 1371 | PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3), | ||
| 1372 | PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), \ | ||
| 1373 | PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3), | ||
| 1374 | PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), \ | ||
| 1375 | PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3), | ||
| 1376 | PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), \ | ||
| 1377 | PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3), | ||
| 1378 | PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1), | ||
| 1379 | PINMUX_DATA(SDHICLK2_MARK, PORT264_FN1), | ||
| 1380 | PINMUX_DATA(SDHID2_0_MARK, PORT265_FN1), \ | ||
| 1381 | PINMUX_DATA(TS_SPSYNC4_MARK, PORT265_FN3), | ||
| 1382 | PINMUX_DATA(SDHID2_1_MARK, PORT266_FN1), \ | ||
| 1383 | PINMUX_DATA(TS_SDAT4_MARK, PORT266_FN3), | ||
| 1384 | PINMUX_DATA(SDHID2_2_MARK, PORT267_FN1), \ | ||
| 1385 | PINMUX_DATA(TS_SDEN4_MARK, PORT267_FN3), | ||
| 1386 | PINMUX_DATA(SDHID2_3_MARK, PORT268_FN1), \ | ||
| 1387 | PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3), | ||
| 1388 | PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1), | ||
| 1389 | PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0), | ||
| 1390 | PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0), | ||
| 1391 | PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0), | ||
| 1392 | PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0), | ||
| 1393 | PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0), | ||
| 1394 | PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0), \ | ||
| 1395 | PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3), | ||
| 1396 | PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0), \ | ||
| 1397 | PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3), | ||
| 1398 | PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0), \ | ||
| 1399 | PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3), | ||
| 1400 | PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0), \ | ||
| 1401 | PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3), | ||
| 1402 | PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0), | ||
| 1403 | PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \ | ||
| 1404 | PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2), | ||
| 1405 | PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1), | ||
| 1406 | PINMUX_DATA(MCP_CKO_MARK, PORT289_FN1), \ | ||
| 1407 | PINMUX_DATA(MMCCLK1_MARK, PORT289_FN2, MSEL4CR_MSEL15_1), | ||
| 1408 | PINMUX_DATA(MCP_D15_MCP_NAF15_MARK, PORT290_FN1), | ||
| 1409 | PINMUX_DATA(MCP_D14_MCP_NAF14_MARK, PORT291_FN1), | ||
| 1410 | PINMUX_DATA(MCP_D13_MCP_NAF13_MARK, PORT292_FN1), | ||
| 1411 | PINMUX_DATA(MCP_D12_MCP_NAF12_MARK, PORT293_FN1), | ||
| 1412 | PINMUX_DATA(MCP_D11_MCP_NAF11_MARK, PORT294_FN1), | ||
| 1413 | PINMUX_DATA(MCP_D10_MCP_NAF10_MARK, PORT295_FN1), | ||
| 1414 | PINMUX_DATA(MCP_D9_MCP_NAF9_MARK, PORT296_FN1), | ||
| 1415 | PINMUX_DATA(MCP_D8_MCP_NAF8_MARK, PORT297_FN1), \ | ||
| 1416 | PINMUX_DATA(MMCCMD1_MARK, PORT297_FN2, MSEL4CR_MSEL15_1), | ||
| 1417 | PINMUX_DATA(MCP_D7_MCP_NAF7_MARK, PORT298_FN1), \ | ||
| 1418 | PINMUX_DATA(MMCD1_7_MARK, PORT298_FN2, MSEL4CR_MSEL15_1), | ||
| 1419 | |||
| 1420 | PINMUX_DATA(MCP_D6_MCP_NAF6_MARK, PORT299_FN1), \ | ||
| 1421 | PINMUX_DATA(MMCD1_6_MARK, PORT299_FN2, MSEL4CR_MSEL15_1), | ||
| 1422 | PINMUX_DATA(MCP_D5_MCP_NAF5_MARK, PORT300_FN1), \ | ||
| 1423 | PINMUX_DATA(MMCD1_5_MARK, PORT300_FN2, MSEL4CR_MSEL15_1), | ||
| 1424 | PINMUX_DATA(MCP_D4_MCP_NAF4_MARK, PORT301_FN1), \ | ||
| 1425 | PINMUX_DATA(MMCD1_4_MARK, PORT301_FN2, MSEL4CR_MSEL15_1), | ||
| 1426 | PINMUX_DATA(MCP_D3_MCP_NAF3_MARK, PORT302_FN1), \ | ||
| 1427 | PINMUX_DATA(MMCD1_3_MARK, PORT302_FN2, MSEL4CR_MSEL15_1), | ||
| 1428 | PINMUX_DATA(MCP_D2_MCP_NAF2_MARK, PORT303_FN1), \ | ||
| 1429 | PINMUX_DATA(MMCD1_2_MARK, PORT303_FN2, MSEL4CR_MSEL15_1), | ||
| 1430 | PINMUX_DATA(MCP_D1_MCP_NAF1_MARK, PORT304_FN1), \ | ||
| 1431 | PINMUX_DATA(MMCD1_1_MARK, PORT304_FN2, MSEL4CR_MSEL15_1), | ||
| 1432 | PINMUX_DATA(MCP_D0_MCP_NAF0_MARK, PORT305_FN1), \ | ||
| 1433 | PINMUX_DATA(MMCD1_0_MARK, PORT305_FN2, MSEL4CR_MSEL15_1), | ||
| 1434 | PINMUX_DATA(MCP_NBRSTOUT__MARK, PORT306_FN1), | ||
| 1435 | PINMUX_DATA(MCP_WE0__MCP_FWE_MARK, PORT309_FN1), \ | ||
| 1436 | PINMUX_DATA(MCP_RDWR_MCP_FWE_MARK, PORT309_FN2), | ||
| 1437 | |||
| 1438 | /* MSEL2 special cases */ | ||
| 1439 | PINMUX_DATA(TSIF2_TS_XX1_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0, | ||
| 1440 | MSEL2CR_MSEL12_0), | ||
| 1441 | PINMUX_DATA(TSIF2_TS_XX2_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0, | ||
| 1442 | MSEL2CR_MSEL12_1), | ||
| 1443 | PINMUX_DATA(TSIF2_TS_XX3_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1, | ||
| 1444 | MSEL2CR_MSEL12_0), | ||
| 1445 | PINMUX_DATA(TSIF2_TS_XX4_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1, | ||
| 1446 | MSEL2CR_MSEL12_1), | ||
| 1447 | PINMUX_DATA(TSIF2_TS_XX5_MARK, MSEL2CR_MSEL14_1, MSEL2CR_MSEL13_0, | ||
| 1448 | MSEL2CR_MSEL12_0), | ||
| 1449 | PINMUX_DATA(TSIF1_TS_XX1_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0, | ||
| 1450 | MSEL2CR_MSEL9_0), | ||
| 1451 | PINMUX_DATA(TSIF1_TS_XX2_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0, | ||
| 1452 | MSEL2CR_MSEL9_1), | ||
| 1453 | PINMUX_DATA(TSIF1_TS_XX3_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1, | ||
| 1454 | MSEL2CR_MSEL9_0), | ||
| 1455 | PINMUX_DATA(TSIF1_TS_XX4_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1, | ||
| 1456 | MSEL2CR_MSEL9_1), | ||
| 1457 | PINMUX_DATA(TSIF1_TS_XX5_MARK, MSEL2CR_MSEL11_1, MSEL2CR_MSEL10_0, | ||
| 1458 | MSEL2CR_MSEL9_0), | ||
| 1459 | PINMUX_DATA(TSIF0_TS_XX1_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0, | ||
| 1460 | MSEL2CR_MSEL6_0), | ||
| 1461 | PINMUX_DATA(TSIF0_TS_XX2_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0, | ||
| 1462 | MSEL2CR_MSEL6_1), | ||
| 1463 | PINMUX_DATA(TSIF0_TS_XX3_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1, | ||
| 1464 | MSEL2CR_MSEL6_0), | ||
| 1465 | PINMUX_DATA(TSIF0_TS_XX4_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1, | ||
| 1466 | MSEL2CR_MSEL6_1), | ||
| 1467 | PINMUX_DATA(TSIF0_TS_XX5_MARK, MSEL2CR_MSEL8_1, MSEL2CR_MSEL7_0, | ||
| 1468 | MSEL2CR_MSEL6_0), | ||
| 1469 | PINMUX_DATA(MST1_TS_XX1_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0, | ||
| 1470 | MSEL2CR_MSEL3_0), | ||
| 1471 | PINMUX_DATA(MST1_TS_XX2_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0, | ||
| 1472 | MSEL2CR_MSEL3_1), | ||
| 1473 | PINMUX_DATA(MST1_TS_XX3_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1, | ||
| 1474 | MSEL2CR_MSEL3_0), | ||
| 1475 | PINMUX_DATA(MST1_TS_XX4_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1, | ||
| 1476 | MSEL2CR_MSEL3_1), | ||
| 1477 | PINMUX_DATA(MST1_TS_XX5_MARK, MSEL2CR_MSEL5_1, MSEL2CR_MSEL4_0, | ||
| 1478 | MSEL2CR_MSEL3_0), | ||
| 1479 | PINMUX_DATA(MST0_TS_XX1_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0, | ||
| 1480 | MSEL2CR_MSEL0_0), | ||
| 1481 | PINMUX_DATA(MST0_TS_XX2_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0, | ||
| 1482 | MSEL2CR_MSEL0_1), | ||
| 1483 | PINMUX_DATA(MST0_TS_XX3_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1, | ||
| 1484 | MSEL2CR_MSEL0_0), | ||
| 1485 | PINMUX_DATA(MST0_TS_XX4_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1, | ||
| 1486 | MSEL2CR_MSEL0_1), | ||
| 1487 | PINMUX_DATA(MST0_TS_XX5_MARK, MSEL2CR_MSEL2_1, MSEL2CR_MSEL1_0, | ||
| 1488 | MSEL2CR_MSEL0_0), | ||
| 1489 | |||
| 1490 | /* MSEL3 special cases */ | ||
| 1491 | PINMUX_DATA(SDHI0_VCCQ_MC0_ON_MARK, MSEL3CR_MSEL28_1), | ||
| 1492 | PINMUX_DATA(SDHI0_VCCQ_MC0_OFF_MARK, MSEL3CR_MSEL28_0), | ||
| 1493 | PINMUX_DATA(DEBUG_MON_VIO_MARK, MSEL3CR_MSEL15_0), | ||
| 1494 | PINMUX_DATA(DEBUG_MON_LCDD_MARK, MSEL3CR_MSEL15_1), | ||
| 1495 | PINMUX_DATA(LCDC_LCDC0_MARK, MSEL3CR_MSEL6_0), | ||
| 1496 | PINMUX_DATA(LCDC_LCDC1_MARK, MSEL3CR_MSEL6_1), | ||
| 1497 | |||
| 1498 | /* MSEL4 special cases */ | ||
| 1499 | PINMUX_DATA(IRQ9_MEM_INT_MARK, MSEL4CR_MSEL29_0), | ||
| 1500 | PINMUX_DATA(IRQ9_MCP_INT_MARK, MSEL4CR_MSEL29_1), | ||
| 1501 | PINMUX_DATA(A11_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_0), | ||
| 1502 | PINMUX_DATA(KEYOUT8_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_1), | ||
| 1503 | PINMUX_DATA(TPU4TO3_MARK, MSEL4CR_MSEL13_1, MSEL4CR_MSEL12_0), | ||
| 1504 | PINMUX_DATA(RESETA_N_PU_ON_MARK, MSEL4CR_MSEL4_0), | ||
| 1505 | PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1), | ||
| 1506 | PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0), | ||
| 1507 | PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1), | ||
| 1508 | |||
| 1509 | /* Functions with pull-ups */ | ||
| 1510 | PINMUX_DATA(KEYIN0_PU_MARK, PORT66_FN2, PORT66_IN_PU), | ||
| 1511 | PINMUX_DATA(KEYIN1_PU_MARK, PORT67_FN2, PORT67_IN_PU), | ||
| 1512 | PINMUX_DATA(KEYIN2_PU_MARK, PORT68_FN2, PORT68_IN_PU), | ||
| 1513 | PINMUX_DATA(KEYIN3_PU_MARK, PORT69_FN2, PORT69_IN_PU), | ||
| 1514 | PINMUX_DATA(KEYIN4_PU_MARK, PORT70_FN2, PORT70_IN_PU), | ||
| 1515 | PINMUX_DATA(KEYIN5_PU_MARK, PORT71_FN2, PORT71_IN_PU), | ||
| 1516 | PINMUX_DATA(KEYIN6_PU_MARK, PORT72_FN2, PORT72_IN_PU), | ||
| 1517 | PINMUX_DATA(KEYIN7_PU_MARK, PORT73_FN2, PORT73_IN_PU), | ||
| 1518 | |||
| 1519 | PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_IN_PU, PORT259_FN1), | ||
| 1520 | PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_IN_PU, PORT260_FN1), | ||
| 1521 | PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_IN_PU, PORT261_FN1), | ||
| 1522 | PINMUX_DATA(SDHID1_3_PU_MARK, PORT262_IN_PU, PORT262_FN1), | ||
| 1523 | PINMUX_DATA(SDHICMD1_PU_MARK, PORT263_IN_PU, PORT263_FN1), | ||
| 1524 | |||
| 1525 | PINMUX_DATA(MMCCMD0_PU_MARK, PORT279_FN1, PORT279_IN_PU, | ||
| 1526 | MSEL4CR_MSEL15_0), | ||
| 1527 | PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT279_IN_PU, | ||
| 1528 | MSEL4CR_MSEL15_1), | ||
| 1529 | PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU), | ||
| 1530 | PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU), | ||
| 1531 | PINMUX_DATA(FSIAIBT_PU_MARK, PORT51_FN5, PORT51_IN_PU), | ||
| 1532 | PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU), | ||
| 1533 | }; | ||
| 1534 | |||
| 1535 | #define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA) | ||
| 1536 | #define GPIO_PORT_310() _310(_GPIO_PORT, , unused) | ||
| 1537 | #define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK) | ||
| 1538 | |||
| 1539 | static struct pinmux_gpio pinmux_gpios[] = { | ||
| 1540 | GPIO_PORT_310(), | ||
| 1541 | |||
| 1542 | /* Table 25-1 (Functions 0-7) */ | ||
| 1543 | GPIO_FN(VBUS_0), | ||
| 1544 | GPIO_FN(GPI0), | ||
| 1545 | GPIO_FN(GPI1), | ||
| 1546 | GPIO_FN(GPI2), | ||
| 1547 | GPIO_FN(GPI3), | ||
| 1548 | GPIO_FN(GPI4), | ||
| 1549 | GPIO_FN(GPI5), | ||
| 1550 | GPIO_FN(GPI6), | ||
| 1551 | GPIO_FN(GPI7), | ||
| 1552 | GPIO_FN(SCIFA7_RXD), | ||
| 1553 | GPIO_FN(SCIFA7_CTS_), | ||
| 1554 | GPIO_FN(GPO7), \ | ||
| 1555 | GPIO_FN(MFG0_OUT2), | ||
| 1556 | GPIO_FN(GPO6), \ | ||
| 1557 | GPIO_FN(MFG1_OUT2), | ||
| 1558 | GPIO_FN(GPO5), \ | ||
| 1559 | GPIO_FN(SCIFA0_SCK), \ | ||
| 1560 | GPIO_FN(FSICOSLDT3), \ | ||
| 1561 | GPIO_FN(PORT16_VIO_CKOR), | ||
| 1562 | GPIO_FN(SCIFA0_TXD), | ||
| 1563 | GPIO_FN(SCIFA7_TXD), | ||
| 1564 | GPIO_FN(SCIFA7_RTS_), \ | ||
| 1565 | GPIO_FN(PORT19_VIO_CKO2), | ||
| 1566 | GPIO_FN(GPO0), | ||
| 1567 | GPIO_FN(GPO1), | ||
| 1568 | GPIO_FN(GPO2), \ | ||
| 1569 | GPIO_FN(STATUS0), | ||
| 1570 | GPIO_FN(GPO3), \ | ||
| 1571 | GPIO_FN(STATUS1), | ||
| 1572 | GPIO_FN(GPO4), \ | ||
| 1573 | GPIO_FN(STATUS2), | ||
| 1574 | GPIO_FN(VINT), | ||
| 1575 | GPIO_FN(TCKON), | ||
| 1576 | GPIO_FN(XDVFS1), \ | ||
| 1577 | GPIO_FN(PORT27_I2C_SCL2), \ | ||
| 1578 | GPIO_FN(PORT27_I2C_SCL3), \ | ||
| 1579 | GPIO_FN(MFG0_OUT1), \ | ||
| 1580 | GPIO_FN(PORT27_IROUT), | ||
| 1581 | GPIO_FN(XDVFS2), \ | ||
| 1582 | GPIO_FN(PORT28_I2C_SDA2), \ | ||
| 1583 | GPIO_FN(PORT28_I2C_SDA3), \ | ||
| 1584 | GPIO_FN(PORT28_TPU1TO1), | ||
| 1585 | GPIO_FN(SIM_RST), \ | ||
| 1586 | GPIO_FN(PORT29_TPU1TO1), | ||
| 1587 | GPIO_FN(SIM_CLK), \ | ||
| 1588 | GPIO_FN(PORT30_VIO_CKOR), | ||
| 1589 | GPIO_FN(SIM_D), \ | ||
| 1590 | GPIO_FN(PORT31_IROUT), | ||
| 1591 | GPIO_FN(SCIFA4_TXD), | ||
| 1592 | GPIO_FN(SCIFA4_RXD), \ | ||
| 1593 | GPIO_FN(XWUP), | ||
| 1594 | GPIO_FN(SCIFA4_RTS_), | ||
| 1595 | GPIO_FN(SCIFA4_CTS_), | ||
| 1596 | GPIO_FN(FSIBOBT), \ | ||
| 1597 | GPIO_FN(FSIBIBT), | ||
| 1598 | GPIO_FN(FSIBOLR), \ | ||
| 1599 | GPIO_FN(FSIBILR), | ||
| 1600 | GPIO_FN(FSIBOSLD), | ||
| 1601 | GPIO_FN(FSIBISLD), | ||
| 1602 | GPIO_FN(VACK), | ||
| 1603 | GPIO_FN(XTAL1L), | ||
| 1604 | GPIO_FN(SCIFA0_RTS_), \ | ||
| 1605 | GPIO_FN(FSICOSLDT2), | ||
| 1606 | GPIO_FN(SCIFA0_RXD), | ||
| 1607 | GPIO_FN(SCIFA0_CTS_), \ | ||
| 1608 | GPIO_FN(FSICOSLDT1), | ||
| 1609 | GPIO_FN(FSICOBT), \ | ||
| 1610 | GPIO_FN(FSICIBT), \ | ||
| 1611 | GPIO_FN(FSIDOBT), \ | ||
| 1612 | GPIO_FN(FSIDIBT), | ||
| 1613 | GPIO_FN(FSICOLR), \ | ||
| 1614 | GPIO_FN(FSICILR), \ | ||
| 1615 | GPIO_FN(FSIDOLR), \ | ||
| 1616 | GPIO_FN(FSIDILR), | ||
| 1617 | GPIO_FN(FSICOSLD), \ | ||
| 1618 | GPIO_FN(PORT47_FSICSPDIF), | ||
| 1619 | GPIO_FN(FSICISLD), \ | ||
| 1620 | GPIO_FN(FSIDISLD), | ||
| 1621 | GPIO_FN(FSIACK), \ | ||
| 1622 | GPIO_FN(PORT49_IRDA_OUT), \ | ||
| 1623 | GPIO_FN(PORT49_IROUT), \ | ||
| 1624 | GPIO_FN(FSIAOMC), | ||
| 1625 | GPIO_FN(FSIAOLR), \ | ||
| 1626 | GPIO_FN(BBIF2_TSYNC2), \ | ||
| 1627 | GPIO_FN(TPU2TO2), \ | ||
| 1628 | GPIO_FN(FSIAILR), | ||
| 1629 | |||
| 1630 | GPIO_FN(FSIAOBT), \ | ||
| 1631 | GPIO_FN(BBIF2_TSCK2), \ | ||
| 1632 | GPIO_FN(TPU2TO3), \ | ||
| 1633 | GPIO_FN(FSIAIBT), | ||
| 1634 | GPIO_FN(FSIAOSLD), \ | ||
| 1635 | GPIO_FN(BBIF2_TXD2), | ||
| 1636 | GPIO_FN(FSIASPDIF), \ | ||
| 1637 | GPIO_FN(PORT53_IRDA_IN), \ | ||
| 1638 | GPIO_FN(TPU3TO3), \ | ||
| 1639 | GPIO_FN(FSIBSPDIF), \ | ||
| 1640 | GPIO_FN(PORT53_FSICSPDIF), | ||
| 1641 | GPIO_FN(FSIBCK), \ | ||
| 1642 | GPIO_FN(PORT54_IRDA_FIRSEL), \ | ||
| 1643 | GPIO_FN(TPU3TO2), \ | ||
| 1644 | GPIO_FN(FSIBOMC), \ | ||
| 1645 | GPIO_FN(FSICCK), \ | ||
| 1646 | GPIO_FN(FSICOMC), | ||
| 1647 | GPIO_FN(FSIAISLD), \ | ||
| 1648 | GPIO_FN(TPU0TO0), | ||
| 1649 | GPIO_FN(A0), \ | ||
| 1650 | GPIO_FN(BS_), | ||
| 1651 | GPIO_FN(A12), \ | ||
| 1652 | GPIO_FN(PORT58_KEYOUT7), \ | ||
| 1653 | GPIO_FN(TPU4TO2), | ||
| 1654 | GPIO_FN(A13), \ | ||
| 1655 | GPIO_FN(PORT59_KEYOUT6), \ | ||
| 1656 | GPIO_FN(TPU0TO1), | ||
| 1657 | GPIO_FN(A14), \ | ||
| 1658 | GPIO_FN(KEYOUT5), | ||
| 1659 | GPIO_FN(A15), \ | ||
| 1660 | GPIO_FN(KEYOUT4), | ||
| 1661 | GPIO_FN(A16), \ | ||
| 1662 | GPIO_FN(KEYOUT3), \ | ||
| 1663 | GPIO_FN(MSIOF0_SS1), | ||
| 1664 | GPIO_FN(A17), \ | ||
| 1665 | GPIO_FN(KEYOUT2), \ | ||
| 1666 | GPIO_FN(MSIOF0_TSYNC), | ||
| 1667 | GPIO_FN(A18), \ | ||
| 1668 | GPIO_FN(KEYOUT1), \ | ||
| 1669 | GPIO_FN(MSIOF0_TSCK), | ||
| 1670 | GPIO_FN(A19), \ | ||
| 1671 | GPIO_FN(KEYOUT0), \ | ||
| 1672 | GPIO_FN(MSIOF0_TXD), | ||
| 1673 | GPIO_FN(A20), \ | ||
| 1674 | GPIO_FN(KEYIN0), \ | ||
| 1675 | GPIO_FN(MSIOF0_RSCK), | ||
| 1676 | GPIO_FN(A21), \ | ||
| 1677 | GPIO_FN(KEYIN1), \ | ||
| 1678 | GPIO_FN(MSIOF0_RSYNC), | ||
| 1679 | GPIO_FN(A22), \ | ||
| 1680 | GPIO_FN(KEYIN2), \ | ||
| 1681 | GPIO_FN(MSIOF0_MCK0), | ||
| 1682 | GPIO_FN(A23), \ | ||
| 1683 | GPIO_FN(KEYIN3), \ | ||
| 1684 | GPIO_FN(MSIOF0_MCK1), | ||
| 1685 | GPIO_FN(A24), \ | ||
| 1686 | GPIO_FN(KEYIN4), \ | ||
| 1687 | GPIO_FN(MSIOF0_RXD), | ||
| 1688 | GPIO_FN(A25), \ | ||
| 1689 | GPIO_FN(KEYIN5), \ | ||
| 1690 | GPIO_FN(MSIOF0_SS2), | ||
| 1691 | GPIO_FN(A26), \ | ||
| 1692 | GPIO_FN(KEYIN6), | ||
| 1693 | GPIO_FN(KEYIN7), | ||
| 1694 | GPIO_FN(D0_NAF0), | ||
| 1695 | GPIO_FN(D1_NAF1), | ||
| 1696 | GPIO_FN(D2_NAF2), | ||
| 1697 | GPIO_FN(D3_NAF3), | ||
| 1698 | GPIO_FN(D4_NAF4), | ||
| 1699 | GPIO_FN(D5_NAF5), | ||
| 1700 | GPIO_FN(D6_NAF6), | ||
| 1701 | GPIO_FN(D7_NAF7), | ||
| 1702 | GPIO_FN(D8_NAF8), | ||
| 1703 | GPIO_FN(D9_NAF9), | ||
| 1704 | GPIO_FN(D10_NAF10), | ||
| 1705 | GPIO_FN(D11_NAF11), | ||
| 1706 | GPIO_FN(D12_NAF12), | ||
| 1707 | GPIO_FN(D13_NAF13), | ||
| 1708 | GPIO_FN(D14_NAF14), | ||
| 1709 | GPIO_FN(D15_NAF15), | ||
| 1710 | GPIO_FN(CS4_), | ||
| 1711 | GPIO_FN(CS5A_), \ | ||
| 1712 | GPIO_FN(PORT91_RDWR), | ||
| 1713 | GPIO_FN(CS5B_), \ | ||
| 1714 | GPIO_FN(FCE1_), | ||
| 1715 | GPIO_FN(CS6B_), \ | ||
| 1716 | GPIO_FN(DACK0), | ||
| 1717 | GPIO_FN(FCE0_), \ | ||
| 1718 | GPIO_FN(CS6A_), | ||
| 1719 | GPIO_FN(WAIT_), \ | ||
| 1720 | GPIO_FN(DREQ0), | ||
| 1721 | GPIO_FN(RD__FSC), | ||
| 1722 | GPIO_FN(WE0__FWE), \ | ||
| 1723 | GPIO_FN(RDWR_FWE), | ||
| 1724 | GPIO_FN(WE1_), | ||
| 1725 | GPIO_FN(FRB), | ||
| 1726 | GPIO_FN(CKO), | ||
| 1727 | GPIO_FN(NBRSTOUT_), | ||
| 1728 | GPIO_FN(NBRST_), | ||
| 1729 | GPIO_FN(BBIF2_TXD), | ||
| 1730 | GPIO_FN(BBIF2_RXD), | ||
| 1731 | GPIO_FN(BBIF2_SYNC), | ||
| 1732 | GPIO_FN(BBIF2_SCK), | ||
| 1733 | GPIO_FN(SCIFA3_CTS_), \ | ||
| 1734 | GPIO_FN(MFG3_IN2), | ||
| 1735 | GPIO_FN(SCIFA3_RXD), \ | ||
| 1736 | GPIO_FN(MFG3_IN1), | ||
| 1737 | GPIO_FN(BBIF1_SS2), \ | ||
| 1738 | GPIO_FN(SCIFA3_RTS_), \ | ||
| 1739 | GPIO_FN(MFG3_OUT1), | ||
| 1740 | GPIO_FN(SCIFA3_TXD), | ||
| 1741 | GPIO_FN(HSI_RX_DATA), \ | ||
| 1742 | GPIO_FN(BBIF1_RXD), | ||
| 1743 | GPIO_FN(HSI_TX_WAKE), \ | ||
| 1744 | GPIO_FN(BBIF1_TSCK), | ||
| 1745 | GPIO_FN(HSI_TX_DATA), \ | ||
| 1746 | GPIO_FN(BBIF1_TSYNC), | ||
| 1747 | GPIO_FN(HSI_TX_READY), \ | ||
| 1748 | GPIO_FN(BBIF1_TXD), | ||
| 1749 | GPIO_FN(HSI_RX_READY), \ | ||
| 1750 | GPIO_FN(BBIF1_RSCK), \ | ||
| 1751 | GPIO_FN(PORT115_I2C_SCL2), \ | ||
| 1752 | GPIO_FN(PORT115_I2C_SCL3), | ||
| 1753 | GPIO_FN(HSI_RX_WAKE), \ | ||
| 1754 | GPIO_FN(BBIF1_RSYNC), \ | ||
| 1755 | GPIO_FN(PORT116_I2C_SDA2), \ | ||
| 1756 | GPIO_FN(PORT116_I2C_SDA3), | ||
| 1757 | GPIO_FN(HSI_RX_FLAG), \ | ||
| 1758 | GPIO_FN(BBIF1_SS1), \ | ||
| 1759 | GPIO_FN(BBIF1_FLOW), | ||
| 1760 | GPIO_FN(HSI_TX_FLAG), | ||
| 1761 | GPIO_FN(VIO_VD), \ | ||
| 1762 | GPIO_FN(PORT128_LCD2VSYN), \ | ||
| 1763 | GPIO_FN(VIO2_VD), \ | ||
| 1764 | GPIO_FN(LCD2D0), | ||
| 1765 | |||
| 1766 | GPIO_FN(VIO_HD), \ | ||
| 1767 | GPIO_FN(PORT129_LCD2HSYN), \ | ||
| 1768 | GPIO_FN(PORT129_LCD2CS_), \ | ||
| 1769 | GPIO_FN(VIO2_HD), \ | ||
| 1770 | GPIO_FN(LCD2D1), | ||
| 1771 | GPIO_FN(VIO_D0), \ | ||
| 1772 | GPIO_FN(PORT130_MSIOF2_RXD), \ | ||
| 1773 | GPIO_FN(LCD2D10), | ||
| 1774 | GPIO_FN(VIO_D1), \ | ||
| 1775 | GPIO_FN(PORT131_KEYOUT6), \ | ||
| 1776 | GPIO_FN(PORT131_MSIOF2_SS1), \ | ||
| 1777 | GPIO_FN(PORT131_KEYOUT11), \ | ||
| 1778 | GPIO_FN(LCD2D11), | ||
| 1779 | GPIO_FN(VIO_D2), \ | ||
| 1780 | GPIO_FN(PORT132_KEYOUT7), \ | ||
| 1781 | GPIO_FN(PORT132_MSIOF2_SS2), \ | ||
| 1782 | GPIO_FN(PORT132_KEYOUT10), \ | ||
| 1783 | GPIO_FN(LCD2D12), | ||
| 1784 | GPIO_FN(VIO_D3), \ | ||
| 1785 | GPIO_FN(MSIOF2_TSYNC), \ | ||
| 1786 | GPIO_FN(LCD2D13), | ||
| 1787 | GPIO_FN(VIO_D4), \ | ||
| 1788 | GPIO_FN(MSIOF2_TXD), \ | ||
| 1789 | GPIO_FN(LCD2D14), | ||
| 1790 | GPIO_FN(VIO_D5), \ | ||
| 1791 | GPIO_FN(MSIOF2_TSCK), \ | ||
| 1792 | GPIO_FN(LCD2D15), | ||
| 1793 | GPIO_FN(VIO_D6), \ | ||
| 1794 | GPIO_FN(PORT136_KEYOUT8), \ | ||
| 1795 | GPIO_FN(LCD2D16), | ||
| 1796 | GPIO_FN(VIO_D7), \ | ||
| 1797 | GPIO_FN(PORT137_KEYOUT9), \ | ||
| 1798 | GPIO_FN(LCD2D17), | ||
| 1799 | GPIO_FN(VIO_D8), \ | ||
| 1800 | GPIO_FN(PORT138_KEYOUT8), \ | ||
| 1801 | GPIO_FN(VIO2_D0), \ | ||
| 1802 | GPIO_FN(LCD2D6), | ||
| 1803 | GPIO_FN(VIO_D9), \ | ||
| 1804 | GPIO_FN(PORT139_KEYOUT9), \ | ||
| 1805 | GPIO_FN(VIO2_D1), \ | ||
| 1806 | GPIO_FN(LCD2D7), | ||
| 1807 | GPIO_FN(VIO_D10), \ | ||
| 1808 | GPIO_FN(TPU0TO2), \ | ||
| 1809 | GPIO_FN(VIO2_D2), \ | ||
| 1810 | GPIO_FN(LCD2D8), | ||
| 1811 | GPIO_FN(VIO_D11), \ | ||
| 1812 | GPIO_FN(TPU0TO3), \ | ||
| 1813 | GPIO_FN(VIO2_D3), \ | ||
| 1814 | GPIO_FN(LCD2D9), | ||
| 1815 | GPIO_FN(VIO_D12), \ | ||
| 1816 | GPIO_FN(PORT142_KEYOUT10), \ | ||
| 1817 | GPIO_FN(VIO2_D4), \ | ||
| 1818 | GPIO_FN(LCD2D2), | ||
| 1819 | GPIO_FN(VIO_D13), \ | ||
| 1820 | GPIO_FN(PORT143_KEYOUT11), \ | ||
| 1821 | GPIO_FN(PORT143_KEYOUT6), \ | ||
| 1822 | GPIO_FN(VIO2_D5), \ | ||
| 1823 | GPIO_FN(LCD2D3), | ||
| 1824 | GPIO_FN(VIO_D14), \ | ||
| 1825 | GPIO_FN(PORT144_KEYOUT7), \ | ||
| 1826 | GPIO_FN(VIO2_D6), \ | ||
| 1827 | GPIO_FN(LCD2D4), | ||
| 1828 | GPIO_FN(VIO_D15), \ | ||
| 1829 | GPIO_FN(TPU1TO3), \ | ||
| 1830 | GPIO_FN(PORT145_LCD2DISP), \ | ||
| 1831 | GPIO_FN(PORT145_LCD2RS), \ | ||
| 1832 | GPIO_FN(VIO2_D7), \ | ||
| 1833 | GPIO_FN(LCD2D5), | ||
| 1834 | GPIO_FN(VIO_CLK), \ | ||
| 1835 | GPIO_FN(LCD2DCK), \ | ||
| 1836 | GPIO_FN(PORT146_LCD2WR_), \ | ||
| 1837 | GPIO_FN(VIO2_CLK), \ | ||
| 1838 | GPIO_FN(LCD2D18), | ||
| 1839 | GPIO_FN(VIO_FIELD), \ | ||
| 1840 | GPIO_FN(LCD2RD_), \ | ||
| 1841 | GPIO_FN(VIO2_FIELD), \ | ||
| 1842 | GPIO_FN(LCD2D19), | ||
| 1843 | GPIO_FN(VIO_CKO), | ||
| 1844 | GPIO_FN(A27), \ | ||
| 1845 | GPIO_FN(PORT149_RDWR), \ | ||
| 1846 | GPIO_FN(MFG0_IN1), \ | ||
| 1847 | GPIO_FN(PORT149_KEYOUT9), | ||
| 1848 | GPIO_FN(MFG0_IN2), | ||
| 1849 | GPIO_FN(TS_SPSYNC3), \ | ||
| 1850 | GPIO_FN(MSIOF2_RSCK), | ||
| 1851 | GPIO_FN(TS_SDAT3), \ | ||
| 1852 | GPIO_FN(MSIOF2_RSYNC), | ||
| 1853 | GPIO_FN(TPU1TO2), \ | ||
| 1854 | GPIO_FN(TS_SDEN3), \ | ||
| 1855 | GPIO_FN(PORT153_MSIOF2_SS1), | ||
| 1856 | GPIO_FN(SCIFA2_TXD1), \ | ||
| 1857 | GPIO_FN(MSIOF2_MCK0), | ||
| 1858 | GPIO_FN(SCIFA2_RXD1), \ | ||
| 1859 | GPIO_FN(MSIOF2_MCK1), | ||
| 1860 | GPIO_FN(SCIFA2_RTS1_), \ | ||
| 1861 | GPIO_FN(PORT156_MSIOF2_SS2), | ||
| 1862 | GPIO_FN(SCIFA2_CTS1_), \ | ||
| 1863 | GPIO_FN(PORT157_MSIOF2_RXD), | ||
| 1864 | GPIO_FN(DINT_), \ | ||
| 1865 | GPIO_FN(SCIFA2_SCK1), \ | ||
| 1866 | GPIO_FN(TS_SCK3), | ||
| 1867 | GPIO_FN(PORT159_SCIFB_SCK), \ | ||
| 1868 | GPIO_FN(PORT159_SCIFA5_SCK), \ | ||
| 1869 | GPIO_FN(NMI), | ||
| 1870 | GPIO_FN(PORT160_SCIFB_TXD), \ | ||
| 1871 | GPIO_FN(PORT160_SCIFA5_TXD), | ||
| 1872 | GPIO_FN(PORT161_SCIFB_CTS_), \ | ||
| 1873 | GPIO_FN(PORT161_SCIFA5_CTS_), | ||
| 1874 | GPIO_FN(PORT162_SCIFB_RXD), \ | ||
| 1875 | GPIO_FN(PORT162_SCIFA5_RXD), | ||
| 1876 | GPIO_FN(PORT163_SCIFB_RTS_), \ | ||
| 1877 | GPIO_FN(PORT163_SCIFA5_RTS_), \ | ||
| 1878 | GPIO_FN(TPU3TO0), | ||
| 1879 | GPIO_FN(LCDD0), | ||
| 1880 | GPIO_FN(LCDD1), \ | ||
| 1881 | GPIO_FN(PORT193_SCIFA5_CTS_), \ | ||
| 1882 | GPIO_FN(BBIF2_TSYNC1), | ||
| 1883 | GPIO_FN(LCDD2), \ | ||
| 1884 | GPIO_FN(PORT194_SCIFA5_RTS_), \ | ||
| 1885 | GPIO_FN(BBIF2_TSCK1), | ||
| 1886 | GPIO_FN(LCDD3), \ | ||
| 1887 | GPIO_FN(PORT195_SCIFA5_RXD), \ | ||
| 1888 | GPIO_FN(BBIF2_TXD1), | ||
| 1889 | GPIO_FN(LCDD4), \ | ||
| 1890 | GPIO_FN(PORT196_SCIFA5_TXD), | ||
| 1891 | GPIO_FN(LCDD5), \ | ||
| 1892 | GPIO_FN(PORT197_SCIFA5_SCK), \ | ||
| 1893 | GPIO_FN(MFG2_OUT2), \ | ||
| 1894 | GPIO_FN(TPU2TO1), | ||
| 1895 | GPIO_FN(LCDD6), | ||
| 1896 | GPIO_FN(LCDD7), \ | ||
| 1897 | GPIO_FN(TPU4TO1), \ | ||
| 1898 | GPIO_FN(MFG4_OUT2), | ||
| 1899 | GPIO_FN(LCDD8), \ | ||
| 1900 | GPIO_FN(D16), | ||
| 1901 | GPIO_FN(LCDD9), \ | ||
| 1902 | GPIO_FN(D17), | ||
| 1903 | GPIO_FN(LCDD10), \ | ||
| 1904 | GPIO_FN(D18), | ||
| 1905 | GPIO_FN(LCDD11), \ | ||
| 1906 | GPIO_FN(D19), | ||
| 1907 | GPIO_FN(LCDD12), \ | ||
| 1908 | GPIO_FN(D20), | ||
| 1909 | GPIO_FN(LCDD13), \ | ||
| 1910 | GPIO_FN(D21), | ||
| 1911 | GPIO_FN(LCDD14), \ | ||
| 1912 | GPIO_FN(D22), | ||
| 1913 | GPIO_FN(LCDD15), \ | ||
| 1914 | GPIO_FN(PORT207_MSIOF0L_SS1), \ | ||
| 1915 | GPIO_FN(D23), | ||
| 1916 | GPIO_FN(LCDD16), \ | ||
| 1917 | GPIO_FN(PORT208_MSIOF0L_SS2), \ | ||
| 1918 | GPIO_FN(D24), | ||
| 1919 | GPIO_FN(LCDD17), \ | ||
| 1920 | GPIO_FN(D25), | ||
| 1921 | GPIO_FN(LCDD18), \ | ||
| 1922 | GPIO_FN(DREQ2), \ | ||
| 1923 | GPIO_FN(PORT210_MSIOF0L_SS1), \ | ||
| 1924 | GPIO_FN(D26), | ||
| 1925 | GPIO_FN(LCDD19), \ | ||
| 1926 | GPIO_FN(PORT211_MSIOF0L_SS2), \ | ||
| 1927 | GPIO_FN(D27), | ||
| 1928 | GPIO_FN(LCDD20), \ | ||
| 1929 | GPIO_FN(TS_SPSYNC1), \ | ||
| 1930 | GPIO_FN(MSIOF0L_MCK0), \ | ||
| 1931 | GPIO_FN(D28), | ||
| 1932 | GPIO_FN(LCDD21), \ | ||
| 1933 | GPIO_FN(TS_SDAT1), \ | ||
| 1934 | GPIO_FN(MSIOF0L_MCK1), \ | ||
| 1935 | GPIO_FN(D29), | ||
| 1936 | GPIO_FN(LCDD22), \ | ||
| 1937 | GPIO_FN(TS_SDEN1), \ | ||
| 1938 | GPIO_FN(MSIOF0L_RSCK), \ | ||
| 1939 | GPIO_FN(D30), | ||
| 1940 | GPIO_FN(LCDD23), \ | ||
| 1941 | GPIO_FN(TS_SCK1), \ | ||
| 1942 | GPIO_FN(MSIOF0L_RSYNC), \ | ||
| 1943 | GPIO_FN(D31), | ||
| 1944 | GPIO_FN(LCDDCK), \ | ||
| 1945 | GPIO_FN(LCDWR_), | ||
| 1946 | GPIO_FN(LCDRD_), \ | ||
| 1947 | GPIO_FN(DACK2), \ | ||
| 1948 | GPIO_FN(PORT217_LCD2RS), \ | ||
| 1949 | GPIO_FN(MSIOF0L_TSYNC), \ | ||
| 1950 | GPIO_FN(VIO2_FIELD3), \ | ||
| 1951 | GPIO_FN(PORT217_LCD2DISP), | ||
| 1952 | GPIO_FN(LCDHSYN), \ | ||
| 1953 | GPIO_FN(LCDCS_), \ | ||
| 1954 | GPIO_FN(LCDCS2_), \ | ||
| 1955 | GPIO_FN(DACK3), \ | ||
| 1956 | GPIO_FN(PORT218_VIO_CKOR), | ||
| 1957 | GPIO_FN(LCDDISP), \ | ||
| 1958 | GPIO_FN(LCDRS), \ | ||
| 1959 | GPIO_FN(PORT219_LCD2WR_), \ | ||
| 1960 | GPIO_FN(DREQ3), \ | ||
| 1961 | GPIO_FN(MSIOF0L_TSCK), \ | ||
| 1962 | GPIO_FN(VIO2_CLK3), \ | ||
| 1963 | GPIO_FN(LCD2DCK_2), | ||
| 1964 | GPIO_FN(LCDVSYN), \ | ||
| 1965 | GPIO_FN(LCDVSYN2), | ||
| 1966 | GPIO_FN(LCDLCLK), \ | ||
| 1967 | GPIO_FN(DREQ1), \ | ||
| 1968 | GPIO_FN(PORT221_LCD2CS_), \ | ||
| 1969 | GPIO_FN(PWEN), \ | ||
| 1970 | GPIO_FN(MSIOF0L_RXD), \ | ||
| 1971 | GPIO_FN(VIO2_HD3), \ | ||
| 1972 | GPIO_FN(PORT221_LCD2HSYN), | ||
| 1973 | GPIO_FN(LCDDON), \ | ||
| 1974 | GPIO_FN(LCDDON2), \ | ||
| 1975 | GPIO_FN(DACK1), \ | ||
| 1976 | GPIO_FN(OVCN), \ | ||
| 1977 | GPIO_FN(MSIOF0L_TXD), \ | ||
| 1978 | GPIO_FN(VIO2_VD3), \ | ||
| 1979 | GPIO_FN(PORT222_LCD2VSYN), | ||
| 1980 | |||
| 1981 | GPIO_FN(SCIFA1_TXD), \ | ||
| 1982 | GPIO_FN(OVCN2), | ||
| 1983 | GPIO_FN(EXTLP), \ | ||
| 1984 | GPIO_FN(SCIFA1_SCK), \ | ||
| 1985 | GPIO_FN(PORT226_VIO_CKO2), | ||
| 1986 | GPIO_FN(SCIFA1_RTS_), \ | ||
| 1987 | GPIO_FN(IDIN), | ||
| 1988 | GPIO_FN(SCIFA1_RXD), | ||
| 1989 | GPIO_FN(SCIFA1_CTS_), \ | ||
| 1990 | GPIO_FN(MFG1_IN1), | ||
| 1991 | GPIO_FN(MSIOF1_TXD), \ | ||
| 1992 | GPIO_FN(SCIFA2_TXD2), | ||
| 1993 | GPIO_FN(MSIOF1_TSYNC), \ | ||
| 1994 | GPIO_FN(SCIFA2_CTS2_), | ||
| 1995 | GPIO_FN(MSIOF1_TSCK), \ | ||
| 1996 | GPIO_FN(SCIFA2_SCK2), | ||
| 1997 | GPIO_FN(MSIOF1_RXD), \ | ||
| 1998 | GPIO_FN(SCIFA2_RXD2), | ||
| 1999 | GPIO_FN(MSIOF1_RSCK), \ | ||
| 2000 | GPIO_FN(SCIFA2_RTS2_), \ | ||
| 2001 | GPIO_FN(VIO2_CLK2), \ | ||
| 2002 | GPIO_FN(LCD2D20), | ||
| 2003 | GPIO_FN(MSIOF1_RSYNC), \ | ||
| 2004 | GPIO_FN(MFG1_IN2), \ | ||
| 2005 | GPIO_FN(VIO2_VD2), \ | ||
| 2006 | GPIO_FN(LCD2D21), | ||
| 2007 | GPIO_FN(MSIOF1_MCK0), \ | ||
| 2008 | GPIO_FN(PORT236_I2C_SDA2), | ||
| 2009 | GPIO_FN(MSIOF1_MCK1), \ | ||
| 2010 | GPIO_FN(PORT237_I2C_SCL2), | ||
| 2011 | GPIO_FN(MSIOF1_SS1), \ | ||
| 2012 | GPIO_FN(VIO2_FIELD2), \ | ||
| 2013 | GPIO_FN(LCD2D22), | ||
| 2014 | GPIO_FN(MSIOF1_SS2), \ | ||
| 2015 | GPIO_FN(VIO2_HD2), \ | ||
| 2016 | GPIO_FN(LCD2D23), | ||
| 2017 | GPIO_FN(SCIFA6_TXD), | ||
| 2018 | GPIO_FN(PORT241_IRDA_OUT), \ | ||
| 2019 | GPIO_FN(PORT241_IROUT), \ | ||
| 2020 | GPIO_FN(MFG4_OUT1), \ | ||
| 2021 | GPIO_FN(TPU4TO0), | ||
| 2022 | GPIO_FN(PORT242_IRDA_IN), \ | ||
| 2023 | GPIO_FN(MFG4_IN2), | ||
| 2024 | GPIO_FN(PORT243_IRDA_FIRSEL), \ | ||
| 2025 | GPIO_FN(PORT243_VIO_CKO2), | ||
| 2026 | GPIO_FN(PORT244_SCIFA5_CTS_), \ | ||
| 2027 | GPIO_FN(MFG2_IN1), \ | ||
| 2028 | GPIO_FN(PORT244_SCIFB_CTS_), \ | ||
| 2029 | GPIO_FN(MSIOF2R_RXD), | ||
| 2030 | GPIO_FN(PORT245_SCIFA5_RTS_), \ | ||
| 2031 | GPIO_FN(MFG2_IN2), \ | ||
| 2032 | GPIO_FN(PORT245_SCIFB_RTS_), \ | ||
| 2033 | GPIO_FN(MSIOF2R_TXD), | ||
| 2034 | GPIO_FN(PORT246_SCIFA5_RXD), \ | ||
| 2035 | GPIO_FN(MFG1_OUT1), \ | ||
| 2036 | GPIO_FN(PORT246_SCIFB_RXD), \ | ||
| 2037 | GPIO_FN(TPU1TO0), | ||
| 2038 | GPIO_FN(PORT247_SCIFA5_TXD), \ | ||
| 2039 | GPIO_FN(MFG3_OUT2), \ | ||
| 2040 | GPIO_FN(PORT247_SCIFB_TXD), \ | ||
| 2041 | GPIO_FN(TPU3TO1), | ||
| 2042 | GPIO_FN(PORT248_SCIFA5_SCK), \ | ||
| 2043 | GPIO_FN(MFG2_OUT1), \ | ||
| 2044 | GPIO_FN(PORT248_SCIFB_SCK), \ | ||
| 2045 | GPIO_FN(TPU2TO0), \ | ||
| 2046 | GPIO_FN(PORT248_I2C_SCL3), \ | ||
| 2047 | GPIO_FN(MSIOF2R_TSCK), | ||
| 2048 | GPIO_FN(PORT249_IROUT), \ | ||
| 2049 | GPIO_FN(MFG4_IN1), \ | ||
| 2050 | GPIO_FN(PORT249_I2C_SDA3), \ | ||
| 2051 | GPIO_FN(MSIOF2R_TSYNC), | ||
| 2052 | GPIO_FN(SDHICLK0), | ||
| 2053 | GPIO_FN(SDHICD0), | ||
| 2054 | GPIO_FN(SDHID0_0), | ||
| 2055 | GPIO_FN(SDHID0_1), | ||
| 2056 | GPIO_FN(SDHID0_2), | ||
| 2057 | GPIO_FN(SDHID0_3), | ||
| 2058 | GPIO_FN(SDHICMD0), | ||
| 2059 | GPIO_FN(SDHIWP0), | ||
| 2060 | GPIO_FN(SDHICLK1), | ||
| 2061 | GPIO_FN(SDHID1_0), \ | ||
| 2062 | GPIO_FN(TS_SPSYNC2), | ||
| 2063 | GPIO_FN(SDHID1_1), \ | ||
| 2064 | GPIO_FN(TS_SDAT2), | ||
| 2065 | GPIO_FN(SDHID1_2), \ | ||
| 2066 | GPIO_FN(TS_SDEN2), | ||
| 2067 | GPIO_FN(SDHID1_3), \ | ||
| 2068 | GPIO_FN(TS_SCK2), | ||
| 2069 | GPIO_FN(SDHICMD1), | ||
| 2070 | GPIO_FN(SDHICLK2), | ||
| 2071 | GPIO_FN(SDHID2_0), \ | ||
| 2072 | GPIO_FN(TS_SPSYNC4), | ||
| 2073 | GPIO_FN(SDHID2_1), \ | ||
| 2074 | GPIO_FN(TS_SDAT4), | ||
| 2075 | GPIO_FN(SDHID2_2), \ | ||
| 2076 | GPIO_FN(TS_SDEN4), | ||
| 2077 | GPIO_FN(SDHID2_3), \ | ||
| 2078 | GPIO_FN(TS_SCK4), | ||
| 2079 | GPIO_FN(SDHICMD2), | ||
| 2080 | GPIO_FN(MMCCLK0), | ||
| 2081 | GPIO_FN(MMCD0_0), | ||
| 2082 | GPIO_FN(MMCD0_1), | ||
| 2083 | GPIO_FN(MMCD0_2), | ||
| 2084 | GPIO_FN(MMCD0_3), | ||
| 2085 | GPIO_FN(MMCD0_4), \ | ||
| 2086 | GPIO_FN(TS_SPSYNC5), | ||
| 2087 | GPIO_FN(MMCD0_5), \ | ||
| 2088 | GPIO_FN(TS_SDAT5), | ||
| 2089 | GPIO_FN(MMCD0_6), \ | ||
| 2090 | GPIO_FN(TS_SDEN5), | ||
| 2091 | GPIO_FN(MMCD0_7), \ | ||
| 2092 | GPIO_FN(TS_SCK5), | ||
| 2093 | GPIO_FN(MMCCMD0), | ||
| 2094 | GPIO_FN(RESETOUTS_), \ | ||
| 2095 | GPIO_FN(EXTAL2OUT), | ||
| 2096 | GPIO_FN(MCP_WAIT__MCP_FRB), | ||
| 2097 | GPIO_FN(MCP_CKO), \ | ||
| 2098 | GPIO_FN(MMCCLK1), | ||
| 2099 | GPIO_FN(MCP_D15_MCP_NAF15), | ||
| 2100 | GPIO_FN(MCP_D14_MCP_NAF14), | ||
| 2101 | GPIO_FN(MCP_D13_MCP_NAF13), | ||
| 2102 | GPIO_FN(MCP_D12_MCP_NAF12), | ||
| 2103 | GPIO_FN(MCP_D11_MCP_NAF11), | ||
| 2104 | GPIO_FN(MCP_D10_MCP_NAF10), | ||
| 2105 | GPIO_FN(MCP_D9_MCP_NAF9), | ||
| 2106 | GPIO_FN(MCP_D8_MCP_NAF8), \ | ||
| 2107 | GPIO_FN(MMCCMD1), | ||
| 2108 | GPIO_FN(MCP_D7_MCP_NAF7), \ | ||
| 2109 | GPIO_FN(MMCD1_7), | ||
| 2110 | |||
| 2111 | GPIO_FN(MCP_D6_MCP_NAF6), \ | ||
| 2112 | GPIO_FN(MMCD1_6), | ||
| 2113 | GPIO_FN(MCP_D5_MCP_NAF5), \ | ||
| 2114 | GPIO_FN(MMCD1_5), | ||
| 2115 | GPIO_FN(MCP_D4_MCP_NAF4), \ | ||
| 2116 | GPIO_FN(MMCD1_4), | ||
| 2117 | GPIO_FN(MCP_D3_MCP_NAF3), \ | ||
| 2118 | GPIO_FN(MMCD1_3), | ||
| 2119 | GPIO_FN(MCP_D2_MCP_NAF2), \ | ||
| 2120 | GPIO_FN(MMCD1_2), | ||
| 2121 | GPIO_FN(MCP_D1_MCP_NAF1), \ | ||
| 2122 | GPIO_FN(MMCD1_1), | ||
| 2123 | GPIO_FN(MCP_D0_MCP_NAF0), \ | ||
| 2124 | GPIO_FN(MMCD1_0), | ||
| 2125 | GPIO_FN(MCP_NBRSTOUT_), | ||
| 2126 | GPIO_FN(MCP_WE0__MCP_FWE), \ | ||
| 2127 | GPIO_FN(MCP_RDWR_MCP_FWE), | ||
| 2128 | |||
| 2129 | /* MSEL2 special cases */ | ||
| 2130 | GPIO_FN(TSIF2_TS_XX1), | ||
| 2131 | GPIO_FN(TSIF2_TS_XX2), | ||
| 2132 | GPIO_FN(TSIF2_TS_XX3), | ||
| 2133 | GPIO_FN(TSIF2_TS_XX4), | ||
| 2134 | GPIO_FN(TSIF2_TS_XX5), | ||
| 2135 | GPIO_FN(TSIF1_TS_XX1), | ||
| 2136 | GPIO_FN(TSIF1_TS_XX2), | ||
| 2137 | GPIO_FN(TSIF1_TS_XX3), | ||
| 2138 | GPIO_FN(TSIF1_TS_XX4), | ||
| 2139 | GPIO_FN(TSIF1_TS_XX5), | ||
| 2140 | GPIO_FN(TSIF0_TS_XX1), | ||
| 2141 | GPIO_FN(TSIF0_TS_XX2), | ||
| 2142 | GPIO_FN(TSIF0_TS_XX3), | ||
| 2143 | GPIO_FN(TSIF0_TS_XX4), | ||
| 2144 | GPIO_FN(TSIF0_TS_XX5), | ||
| 2145 | GPIO_FN(MST1_TS_XX1), | ||
| 2146 | GPIO_FN(MST1_TS_XX2), | ||
| 2147 | GPIO_FN(MST1_TS_XX3), | ||
| 2148 | GPIO_FN(MST1_TS_XX4), | ||
| 2149 | GPIO_FN(MST1_TS_XX5), | ||
| 2150 | GPIO_FN(MST0_TS_XX1), | ||
| 2151 | GPIO_FN(MST0_TS_XX2), | ||
| 2152 | GPIO_FN(MST0_TS_XX3), | ||
| 2153 | GPIO_FN(MST0_TS_XX4), | ||
| 2154 | GPIO_FN(MST0_TS_XX5), | ||
| 2155 | |||
| 2156 | /* MSEL3 special cases */ | ||
| 2157 | GPIO_FN(SDHI0_VCCQ_MC0_ON), | ||
| 2158 | GPIO_FN(SDHI0_VCCQ_MC0_OFF), | ||
| 2159 | GPIO_FN(DEBUG_MON_VIO), | ||
| 2160 | GPIO_FN(DEBUG_MON_LCDD), | ||
| 2161 | GPIO_FN(LCDC_LCDC0), | ||
| 2162 | GPIO_FN(LCDC_LCDC1), | ||
| 2163 | |||
| 2164 | /* MSEL4 special cases */ | ||
| 2165 | GPIO_FN(IRQ9_MEM_INT), | ||
| 2166 | GPIO_FN(IRQ9_MCP_INT), | ||
| 2167 | GPIO_FN(A11), | ||
| 2168 | GPIO_FN(KEYOUT8), | ||
| 2169 | GPIO_FN(TPU4TO3), | ||
| 2170 | GPIO_FN(RESETA_N_PU_ON), | ||
| 2171 | GPIO_FN(RESETA_N_PU_OFF), | ||
| 2172 | GPIO_FN(EDBGREQ_PD), | ||
| 2173 | GPIO_FN(EDBGREQ_PU), | ||
| 2174 | |||
| 2175 | /* Functions with pull-ups */ | ||
| 2176 | GPIO_FN(KEYIN0_PU), | ||
| 2177 | GPIO_FN(KEYIN1_PU), | ||
| 2178 | GPIO_FN(KEYIN2_PU), | ||
| 2179 | GPIO_FN(KEYIN3_PU), | ||
| 2180 | GPIO_FN(KEYIN4_PU), | ||
| 2181 | GPIO_FN(KEYIN5_PU), | ||
| 2182 | GPIO_FN(KEYIN6_PU), | ||
| 2183 | GPIO_FN(KEYIN7_PU), | ||
| 2184 | GPIO_FN(SDHID1_0_PU), | ||
| 2185 | GPIO_FN(SDHID1_1_PU), | ||
| 2186 | GPIO_FN(SDHID1_2_PU), | ||
| 2187 | GPIO_FN(SDHID1_3_PU), | ||
| 2188 | GPIO_FN(SDHICMD1_PU), | ||
| 2189 | GPIO_FN(MMCCMD0_PU), | ||
| 2190 | GPIO_FN(MMCCMD1_PU), | ||
| 2191 | GPIO_FN(FSIACK_PU), | ||
| 2192 | GPIO_FN(FSIAILR_PU), | ||
| 2193 | GPIO_FN(FSIAIBT_PU), | ||
| 2194 | GPIO_FN(FSIAISLD_PU), | ||
| 2195 | }; | ||
| 2196 | |||
| 2197 | #define PORTCR(nr, reg) \ | ||
| 2198 | { PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ | ||
| 2199 | 0, \ | ||
| 2200 | /*0001*/ PORT##nr##_OUT , \ | ||
| 2201 | /*0010*/ PORT##nr##_IN , 0, 0, 0, 0, 0, 0, 0, \ | ||
| 2202 | /*1010*/ PORT##nr##_IN_PD, 0, 0, 0, \ | ||
| 2203 | /*1110*/ PORT##nr##_IN_PU, 0, \ | ||
| 2204 | PORT##nr##_FN0, PORT##nr##_FN1, PORT##nr##_FN2, \ | ||
| 2205 | PORT##nr##_FN3, PORT##nr##_FN4, PORT##nr##_FN5, \ | ||
| 2206 | PORT##nr##_FN6, PORT##nr##_FN7, 0, 0, 0, 0, 0, 0, 0, 0 } \ | ||
| 2207 | } | ||
| 2208 | |||
| 2209 | static struct pinmux_cfg_reg pinmux_config_regs[] = { | ||
| 2210 | PORTCR(0, 0xe6050000), /* PORT0CR */ | ||
| 2211 | PORTCR(1, 0xe6050001), /* PORT1CR */ | ||
| 2212 | PORTCR(2, 0xe6050002), /* PORT2CR */ | ||
| 2213 | PORTCR(3, 0xe6050003), /* PORT3CR */ | ||
| 2214 | PORTCR(4, 0xe6050004), /* PORT4CR */ | ||
| 2215 | PORTCR(5, 0xe6050005), /* PORT5CR */ | ||
| 2216 | PORTCR(6, 0xe6050006), /* PORT6CR */ | ||
| 2217 | PORTCR(7, 0xe6050007), /* PORT7CR */ | ||
| 2218 | PORTCR(8, 0xe6050008), /* PORT8CR */ | ||
| 2219 | PORTCR(9, 0xe6050009), /* PORT9CR */ | ||
| 2220 | |||
| 2221 | PORTCR(10, 0xe605000a), /* PORT10CR */ | ||
| 2222 | PORTCR(11, 0xe605000b), /* PORT11CR */ | ||
| 2223 | PORTCR(12, 0xe605000c), /* PORT12CR */ | ||
| 2224 | PORTCR(13, 0xe605000d), /* PORT13CR */ | ||
| 2225 | PORTCR(14, 0xe605000e), /* PORT14CR */ | ||
| 2226 | PORTCR(15, 0xe605000f), /* PORT15CR */ | ||
| 2227 | PORTCR(16, 0xe6050010), /* PORT16CR */ | ||
| 2228 | PORTCR(17, 0xe6050011), /* PORT17CR */ | ||
| 2229 | PORTCR(18, 0xe6050012), /* PORT18CR */ | ||
| 2230 | PORTCR(19, 0xe6050013), /* PORT19CR */ | ||
| 2231 | |||
| 2232 | PORTCR(20, 0xe6050014), /* PORT20CR */ | ||
| 2233 | PORTCR(21, 0xe6050015), /* PORT21CR */ | ||
| 2234 | PORTCR(22, 0xe6050016), /* PORT22CR */ | ||
| 2235 | PORTCR(23, 0xe6050017), /* PORT23CR */ | ||
| 2236 | PORTCR(24, 0xe6050018), /* PORT24CR */ | ||
| 2237 | PORTCR(25, 0xe6050019), /* PORT25CR */ | ||
| 2238 | PORTCR(26, 0xe605001a), /* PORT26CR */ | ||
| 2239 | PORTCR(27, 0xe605001b), /* PORT27CR */ | ||
| 2240 | PORTCR(28, 0xe605001c), /* PORT28CR */ | ||
| 2241 | PORTCR(29, 0xe605001d), /* PORT29CR */ | ||
| 2242 | |||
| 2243 | PORTCR(30, 0xe605001e), /* PORT30CR */ | ||
| 2244 | PORTCR(31, 0xe605001f), /* PORT31CR */ | ||
| 2245 | PORTCR(32, 0xe6051020), /* PORT32CR */ | ||
| 2246 | PORTCR(33, 0xe6051021), /* PORT33CR */ | ||
| 2247 | PORTCR(34, 0xe6051022), /* PORT34CR */ | ||
| 2248 | PORTCR(35, 0xe6051023), /* PORT35CR */ | ||
| 2249 | PORTCR(36, 0xe6051024), /* PORT36CR */ | ||
| 2250 | PORTCR(37, 0xe6051025), /* PORT37CR */ | ||
| 2251 | PORTCR(38, 0xe6051026), /* PORT38CR */ | ||
| 2252 | PORTCR(39, 0xe6051027), /* PORT39CR */ | ||
| 2253 | |||
| 2254 | PORTCR(40, 0xe6051028), /* PORT40CR */ | ||
| 2255 | PORTCR(41, 0xe6051029), /* PORT41CR */ | ||
| 2256 | PORTCR(42, 0xe605102a), /* PORT42CR */ | ||
| 2257 | PORTCR(43, 0xe605102b), /* PORT43CR */ | ||
| 2258 | PORTCR(44, 0xe605102c), /* PORT44CR */ | ||
| 2259 | PORTCR(45, 0xe605102d), /* PORT45CR */ | ||
| 2260 | PORTCR(46, 0xe605102e), /* PORT46CR */ | ||
| 2261 | PORTCR(47, 0xe605102f), /* PORT47CR */ | ||
| 2262 | PORTCR(48, 0xe6051030), /* PORT48CR */ | ||
| 2263 | PORTCR(49, 0xe6051031), /* PORT49CR */ | ||
| 2264 | |||
| 2265 | PORTCR(50, 0xe6051032), /* PORT50CR */ | ||
| 2266 | PORTCR(51, 0xe6051033), /* PORT51CR */ | ||
| 2267 | PORTCR(52, 0xe6051034), /* PORT52CR */ | ||
| 2268 | PORTCR(53, 0xe6051035), /* PORT53CR */ | ||
| 2269 | PORTCR(54, 0xe6051036), /* PORT54CR */ | ||
| 2270 | PORTCR(55, 0xe6051037), /* PORT55CR */ | ||
| 2271 | PORTCR(56, 0xe6051038), /* PORT56CR */ | ||
| 2272 | PORTCR(57, 0xe6051039), /* PORT57CR */ | ||
| 2273 | PORTCR(58, 0xe605103a), /* PORT58CR */ | ||
| 2274 | PORTCR(59, 0xe605103b), /* PORT59CR */ | ||
| 2275 | |||
| 2276 | PORTCR(60, 0xe605103c), /* PORT60CR */ | ||
| 2277 | PORTCR(61, 0xe605103d), /* PORT61CR */ | ||
| 2278 | PORTCR(62, 0xe605103e), /* PORT62CR */ | ||
| 2279 | PORTCR(63, 0xe605103f), /* PORT63CR */ | ||
| 2280 | PORTCR(64, 0xe6051040), /* PORT64CR */ | ||
| 2281 | PORTCR(65, 0xe6051041), /* PORT65CR */ | ||
| 2282 | PORTCR(66, 0xe6051042), /* PORT66CR */ | ||
| 2283 | PORTCR(67, 0xe6051043), /* PORT67CR */ | ||
| 2284 | PORTCR(68, 0xe6051044), /* PORT68CR */ | ||
| 2285 | PORTCR(69, 0xe6051045), /* PORT69CR */ | ||
| 2286 | |||
| 2287 | PORTCR(70, 0xe6051046), /* PORT70CR */ | ||
| 2288 | PORTCR(71, 0xe6051047), /* PORT71CR */ | ||
| 2289 | PORTCR(72, 0xe6051048), /* PORT72CR */ | ||
| 2290 | PORTCR(73, 0xe6051049), /* PORT73CR */ | ||
| 2291 | PORTCR(74, 0xe605104a), /* PORT74CR */ | ||
| 2292 | PORTCR(75, 0xe605104b), /* PORT75CR */ | ||
| 2293 | PORTCR(76, 0xe605104c), /* PORT76CR */ | ||
| 2294 | PORTCR(77, 0xe605104d), /* PORT77CR */ | ||
| 2295 | PORTCR(78, 0xe605104e), /* PORT78CR */ | ||
| 2296 | PORTCR(79, 0xe605104f), /* PORT79CR */ | ||
| 2297 | |||
| 2298 | PORTCR(80, 0xe6051050), /* PORT80CR */ | ||
| 2299 | PORTCR(81, 0xe6051051), /* PORT81CR */ | ||
| 2300 | PORTCR(82, 0xe6051052), /* PORT82CR */ | ||
| 2301 | PORTCR(83, 0xe6051053), /* PORT83CR */ | ||
| 2302 | PORTCR(84, 0xe6051054), /* PORT84CR */ | ||
| 2303 | PORTCR(85, 0xe6051055), /* PORT85CR */ | ||
| 2304 | PORTCR(86, 0xe6051056), /* PORT86CR */ | ||
| 2305 | PORTCR(87, 0xe6051057), /* PORT87CR */ | ||
| 2306 | PORTCR(88, 0xe6051058), /* PORT88CR */ | ||
| 2307 | PORTCR(89, 0xe6051059), /* PORT89CR */ | ||
| 2308 | |||
| 2309 | PORTCR(90, 0xe605105a), /* PORT90CR */ | ||
| 2310 | PORTCR(91, 0xe605105b), /* PORT91CR */ | ||
| 2311 | PORTCR(92, 0xe605105c), /* PORT92CR */ | ||
| 2312 | PORTCR(93, 0xe605105d), /* PORT93CR */ | ||
| 2313 | PORTCR(94, 0xe605105e), /* PORT94CR */ | ||
| 2314 | PORTCR(95, 0xe605105f), /* PORT95CR */ | ||
| 2315 | PORTCR(96, 0xe6052060), /* PORT96CR */ | ||
| 2316 | PORTCR(97, 0xe6052061), /* PORT97CR */ | ||
| 2317 | PORTCR(98, 0xe6052062), /* PORT98CR */ | ||
| 2318 | PORTCR(99, 0xe6052063), /* PORT99CR */ | ||
| 2319 | |||
| 2320 | PORTCR(100, 0xe6052064), /* PORT100CR */ | ||
| 2321 | PORTCR(101, 0xe6052065), /* PORT101CR */ | ||
| 2322 | PORTCR(102, 0xe6052066), /* PORT102CR */ | ||
| 2323 | PORTCR(103, 0xe6052067), /* PORT103CR */ | ||
| 2324 | PORTCR(104, 0xe6052068), /* PORT104CR */ | ||
| 2325 | PORTCR(105, 0xe6052069), /* PORT105CR */ | ||
| 2326 | PORTCR(106, 0xe605206a), /* PORT106CR */ | ||
| 2327 | PORTCR(107, 0xe605206b), /* PORT107CR */ | ||
| 2328 | PORTCR(108, 0xe605206c), /* PORT108CR */ | ||
| 2329 | PORTCR(109, 0xe605206d), /* PORT109CR */ | ||
| 2330 | |||
| 2331 | PORTCR(110, 0xe605206e), /* PORT110CR */ | ||
| 2332 | PORTCR(111, 0xe605206f), /* PORT111CR */ | ||
| 2333 | PORTCR(112, 0xe6052070), /* PORT112CR */ | ||
| 2334 | PORTCR(113, 0xe6052071), /* PORT113CR */ | ||
| 2335 | PORTCR(114, 0xe6052072), /* PORT114CR */ | ||
| 2336 | PORTCR(115, 0xe6052073), /* PORT115CR */ | ||
| 2337 | PORTCR(116, 0xe6052074), /* PORT116CR */ | ||
| 2338 | PORTCR(117, 0xe6052075), /* PORT117CR */ | ||
| 2339 | PORTCR(118, 0xe6052076), /* PORT118CR */ | ||
| 2340 | |||
| 2341 | PORTCR(128, 0xe6052080), /* PORT128CR */ | ||
| 2342 | PORTCR(129, 0xe6052081), /* PORT129CR */ | ||
| 2343 | |||
| 2344 | PORTCR(130, 0xe6052082), /* PORT130CR */ | ||
| 2345 | PORTCR(131, 0xe6052083), /* PORT131CR */ | ||
| 2346 | PORTCR(132, 0xe6052084), /* PORT132CR */ | ||
| 2347 | PORTCR(133, 0xe6052085), /* PORT133CR */ | ||
| 2348 | PORTCR(134, 0xe6052086), /* PORT134CR */ | ||
| 2349 | PORTCR(135, 0xe6052087), /* PORT135CR */ | ||
| 2350 | PORTCR(136, 0xe6052088), /* PORT136CR */ | ||
| 2351 | PORTCR(137, 0xe6052089), /* PORT137CR */ | ||
| 2352 | PORTCR(138, 0xe605208a), /* PORT138CR */ | ||
| 2353 | PORTCR(139, 0xe605208b), /* PORT139CR */ | ||
| 2354 | |||
| 2355 | PORTCR(140, 0xe605208c), /* PORT140CR */ | ||
| 2356 | PORTCR(141, 0xe605208d), /* PORT141CR */ | ||
| 2357 | PORTCR(142, 0xe605208e), /* PORT142CR */ | ||
| 2358 | PORTCR(143, 0xe605208f), /* PORT143CR */ | ||
| 2359 | PORTCR(144, 0xe6052090), /* PORT144CR */ | ||
| 2360 | PORTCR(145, 0xe6052091), /* PORT145CR */ | ||
| 2361 | PORTCR(146, 0xe6052092), /* PORT146CR */ | ||
| 2362 | PORTCR(147, 0xe6052093), /* PORT147CR */ | ||
| 2363 | PORTCR(148, 0xe6052094), /* PORT148CR */ | ||
| 2364 | PORTCR(149, 0xe6052095), /* PORT149CR */ | ||
| 2365 | |||
| 2366 | PORTCR(150, 0xe6052096), /* PORT150CR */ | ||
| 2367 | PORTCR(151, 0xe6052097), /* PORT151CR */ | ||
| 2368 | PORTCR(152, 0xe6052098), /* PORT152CR */ | ||
| 2369 | PORTCR(153, 0xe6052099), /* PORT153CR */ | ||
| 2370 | PORTCR(154, 0xe605209a), /* PORT154CR */ | ||
| 2371 | PORTCR(155, 0xe605209b), /* PORT155CR */ | ||
| 2372 | PORTCR(156, 0xe605209c), /* PORT156CR */ | ||
| 2373 | PORTCR(157, 0xe605209d), /* PORT157CR */ | ||
| 2374 | PORTCR(158, 0xe605209e), /* PORT158CR */ | ||
| 2375 | PORTCR(159, 0xe605209f), /* PORT159CR */ | ||
| 2376 | |||
| 2377 | PORTCR(160, 0xe60520a0), /* PORT160CR */ | ||
| 2378 | PORTCR(161, 0xe60520a1), /* PORT161CR */ | ||
| 2379 | PORTCR(162, 0xe60520a2), /* PORT162CR */ | ||
| 2380 | PORTCR(163, 0xe60520a3), /* PORT163CR */ | ||
| 2381 | PORTCR(164, 0xe60520a4), /* PORT164CR */ | ||
| 2382 | |||
| 2383 | PORTCR(192, 0xe60520c0), /* PORT192CR */ | ||
| 2384 | PORTCR(193, 0xe60520c1), /* PORT193CR */ | ||
| 2385 | PORTCR(194, 0xe60520c2), /* PORT194CR */ | ||
| 2386 | PORTCR(195, 0xe60520c3), /* PORT195CR */ | ||
| 2387 | PORTCR(196, 0xe60520c4), /* PORT196CR */ | ||
| 2388 | PORTCR(197, 0xe60520c5), /* PORT197CR */ | ||
| 2389 | PORTCR(198, 0xe60520c6), /* PORT198CR */ | ||
| 2390 | PORTCR(199, 0xe60520c7), /* PORT199CR */ | ||
| 2391 | |||
| 2392 | PORTCR(200, 0xe60520c8), /* PORT200CR */ | ||
| 2393 | PORTCR(201, 0xe60520c9), /* PORT201CR */ | ||
| 2394 | PORTCR(202, 0xe60520ca), /* PORT202CR */ | ||
| 2395 | PORTCR(203, 0xe60520cb), /* PORT203CR */ | ||
| 2396 | PORTCR(204, 0xe60520cc), /* PORT204CR */ | ||
| 2397 | PORTCR(205, 0xe60520cd), /* PORT205CR */ | ||
| 2398 | PORTCR(206, 0xe60520ce), /* PORT206CR */ | ||
| 2399 | PORTCR(207, 0xe60520cf), /* PORT207CR */ | ||
| 2400 | PORTCR(208, 0xe60520d0), /* PORT208CR */ | ||
| 2401 | PORTCR(209, 0xe60520d1), /* PORT209CR */ | ||
| 2402 | |||
| 2403 | PORTCR(210, 0xe60520d2), /* PORT210CR */ | ||
| 2404 | PORTCR(211, 0xe60520d3), /* PORT211CR */ | ||
| 2405 | PORTCR(212, 0xe60520d4), /* PORT212CR */ | ||
| 2406 | PORTCR(213, 0xe60520d5), /* PORT213CR */ | ||
| 2407 | PORTCR(214, 0xe60520d6), /* PORT214CR */ | ||
| 2408 | PORTCR(215, 0xe60520d7), /* PORT215CR */ | ||
| 2409 | PORTCR(216, 0xe60520d8), /* PORT216CR */ | ||
| 2410 | PORTCR(217, 0xe60520d9), /* PORT217CR */ | ||
| 2411 | PORTCR(218, 0xe60520da), /* PORT218CR */ | ||
| 2412 | PORTCR(219, 0xe60520db), /* PORT219CR */ | ||
| 2413 | |||
| 2414 | PORTCR(220, 0xe60520dc), /* PORT220CR */ | ||
| 2415 | PORTCR(221, 0xe60520dd), /* PORT221CR */ | ||
| 2416 | PORTCR(222, 0xe60520de), /* PORT222CR */ | ||
| 2417 | PORTCR(223, 0xe60520df), /* PORT223CR */ | ||
| 2418 | PORTCR(224, 0xe60530e0), /* PORT224CR */ | ||
| 2419 | PORTCR(225, 0xe60530e1), /* PORT225CR */ | ||
| 2420 | PORTCR(226, 0xe60530e2), /* PORT226CR */ | ||
| 2421 | PORTCR(227, 0xe60530e3), /* PORT227CR */ | ||
| 2422 | PORTCR(228, 0xe60530e4), /* PORT228CR */ | ||
| 2423 | PORTCR(229, 0xe60530e5), /* PORT229CR */ | ||
| 2424 | |||
| 2425 | PORTCR(230, 0xe60530e6), /* PORT230CR */ | ||
| 2426 | PORTCR(231, 0xe60530e7), /* PORT231CR */ | ||
| 2427 | PORTCR(232, 0xe60530e8), /* PORT232CR */ | ||
| 2428 | PORTCR(233, 0xe60530e9), /* PORT233CR */ | ||
| 2429 | PORTCR(234, 0xe60530ea), /* PORT234CR */ | ||
| 2430 | PORTCR(235, 0xe60530eb), /* PORT235CR */ | ||
| 2431 | PORTCR(236, 0xe60530ec), /* PORT236CR */ | ||
| 2432 | PORTCR(237, 0xe60530ed), /* PORT237CR */ | ||
| 2433 | PORTCR(238, 0xe60530ee), /* PORT238CR */ | ||
| 2434 | PORTCR(239, 0xe60530ef), /* PORT239CR */ | ||
| 2435 | |||
| 2436 | PORTCR(240, 0xe60530f0), /* PORT240CR */ | ||
| 2437 | PORTCR(241, 0xe60530f1), /* PORT241CR */ | ||
| 2438 | PORTCR(242, 0xe60530f2), /* PORT242CR */ | ||
| 2439 | PORTCR(243, 0xe60530f3), /* PORT243CR */ | ||
| 2440 | PORTCR(244, 0xe60530f4), /* PORT244CR */ | ||
| 2441 | PORTCR(245, 0xe60530f5), /* PORT245CR */ | ||
| 2442 | PORTCR(246, 0xe60530f6), /* PORT246CR */ | ||
| 2443 | PORTCR(247, 0xe60530f7), /* PORT247CR */ | ||
| 2444 | PORTCR(248, 0xe60530f8), /* PORT248CR */ | ||
| 2445 | PORTCR(249, 0xe60530f9), /* PORT249CR */ | ||
| 2446 | |||
| 2447 | PORTCR(250, 0xe60530fa), /* PORT250CR */ | ||
| 2448 | PORTCR(251, 0xe60530fb), /* PORT251CR */ | ||
| 2449 | PORTCR(252, 0xe60530fc), /* PORT252CR */ | ||
| 2450 | PORTCR(253, 0xe60530fd), /* PORT253CR */ | ||
| 2451 | PORTCR(254, 0xe60530fe), /* PORT254CR */ | ||
| 2452 | PORTCR(255, 0xe60530ff), /* PORT255CR */ | ||
| 2453 | PORTCR(256, 0xe6053100), /* PORT256CR */ | ||
| 2454 | PORTCR(257, 0xe6053101), /* PORT257CR */ | ||
| 2455 | PORTCR(258, 0xe6053102), /* PORT258CR */ | ||
| 2456 | PORTCR(259, 0xe6053103), /* PORT259CR */ | ||
| 2457 | |||
| 2458 | PORTCR(260, 0xe6053104), /* PORT260CR */ | ||
| 2459 | PORTCR(261, 0xe6053105), /* PORT261CR */ | ||
| 2460 | PORTCR(262, 0xe6053106), /* PORT262CR */ | ||
| 2461 | PORTCR(263, 0xe6053107), /* PORT263CR */ | ||
| 2462 | PORTCR(264, 0xe6053108), /* PORT264CR */ | ||
| 2463 | PORTCR(265, 0xe6053109), /* PORT265CR */ | ||
| 2464 | PORTCR(266, 0xe605310a), /* PORT266CR */ | ||
| 2465 | PORTCR(267, 0xe605310b), /* PORT267CR */ | ||
| 2466 | PORTCR(268, 0xe605310c), /* PORT268CR */ | ||
| 2467 | PORTCR(269, 0xe605310d), /* PORT269CR */ | ||
| 2468 | |||
| 2469 | PORTCR(270, 0xe605310e), /* PORT270CR */ | ||
| 2470 | PORTCR(271, 0xe605310f), /* PORT271CR */ | ||
| 2471 | PORTCR(272, 0xe6053110), /* PORT272CR */ | ||
| 2472 | PORTCR(273, 0xe6053111), /* PORT273CR */ | ||
| 2473 | PORTCR(274, 0xe6053112), /* PORT274CR */ | ||
| 2474 | PORTCR(275, 0xe6053113), /* PORT275CR */ | ||
| 2475 | PORTCR(276, 0xe6053114), /* PORT276CR */ | ||
| 2476 | PORTCR(277, 0xe6053115), /* PORT277CR */ | ||
| 2477 | PORTCR(278, 0xe6053116), /* PORT278CR */ | ||
| 2478 | PORTCR(279, 0xe6053117), /* PORT279CR */ | ||
| 2479 | |||
| 2480 | PORTCR(280, 0xe6053118), /* PORT280CR */ | ||
| 2481 | PORTCR(281, 0xe6053119), /* PORT281CR */ | ||
| 2482 | PORTCR(282, 0xe605311a), /* PORT282CR */ | ||
| 2483 | |||
| 2484 | PORTCR(288, 0xe6052120), /* PORT288CR */ | ||
| 2485 | PORTCR(289, 0xe6052121), /* PORT289CR */ | ||
| 2486 | |||
| 2487 | PORTCR(290, 0xe6052122), /* PORT290CR */ | ||
| 2488 | PORTCR(291, 0xe6052123), /* PORT291CR */ | ||
| 2489 | PORTCR(292, 0xe6052124), /* PORT292CR */ | ||
| 2490 | PORTCR(293, 0xe6052125), /* PORT293CR */ | ||
| 2491 | PORTCR(294, 0xe6052126), /* PORT294CR */ | ||
| 2492 | PORTCR(295, 0xe6052127), /* PORT295CR */ | ||
| 2493 | PORTCR(296, 0xe6052128), /* PORT296CR */ | ||
| 2494 | PORTCR(297, 0xe6052129), /* PORT297CR */ | ||
| 2495 | PORTCR(298, 0xe605212a), /* PORT298CR */ | ||
| 2496 | PORTCR(299, 0xe605212b), /* PORT299CR */ | ||
| 2497 | |||
| 2498 | PORTCR(300, 0xe605212c), /* PORT300CR */ | ||
| 2499 | PORTCR(301, 0xe605212d), /* PORT301CR */ | ||
| 2500 | PORTCR(302, 0xe605212e), /* PORT302CR */ | ||
| 2501 | PORTCR(303, 0xe605212f), /* PORT303CR */ | ||
| 2502 | PORTCR(304, 0xe6052130), /* PORT304CR */ | ||
| 2503 | PORTCR(305, 0xe6052131), /* PORT305CR */ | ||
| 2504 | PORTCR(306, 0xe6052132), /* PORT306CR */ | ||
| 2505 | PORTCR(307, 0xe6052133), /* PORT307CR */ | ||
| 2506 | PORTCR(308, 0xe6052134), /* PORT308CR */ | ||
| 2507 | PORTCR(309, 0xe6052135), /* PORT309CR */ | ||
| 2508 | |||
| 2509 | { PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1) { | ||
| 2510 | 0, 0, | ||
| 2511 | 0, 0, | ||
| 2512 | 0, 0, | ||
| 2513 | 0, 0, | ||
| 2514 | 0, 0, | ||
| 2515 | 0, 0, | ||
| 2516 | 0, 0, | ||
| 2517 | 0, 0, | ||
| 2518 | 0, 0, | ||
| 2519 | 0, 0, | ||
| 2520 | 0, 0, | ||
| 2521 | 0, 0, | ||
| 2522 | MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1, | ||
| 2523 | MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1, | ||
| 2524 | MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1, | ||
| 2525 | MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1, | ||
| 2526 | 0, 0, | ||
| 2527 | MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1, | ||
| 2528 | MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1, | ||
| 2529 | MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1, | ||
| 2530 | MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1, | ||
| 2531 | MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1, | ||
| 2532 | MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1, | ||
| 2533 | MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1, | ||
| 2534 | MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1, | ||
| 2535 | MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1, | ||
| 2536 | MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1, | ||
| 2537 | MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1, | ||
| 2538 | MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1, | ||
| 2539 | MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1, | ||
| 2540 | MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1, | ||
| 2541 | MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1, | ||
| 2542 | } | ||
| 2543 | }, | ||
| 2544 | { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) { | ||
| 2545 | 0, 0, | ||
| 2546 | 0, 0, | ||
| 2547 | 0, 0, | ||
| 2548 | MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1, | ||
| 2549 | 0, 0, | ||
| 2550 | 0, 0, | ||
| 2551 | 0, 0, | ||
| 2552 | 0, 0, | ||
| 2553 | 0, 0, | ||
| 2554 | 0, 0, | ||
| 2555 | 0, 0, | ||
| 2556 | 0, 0, | ||
| 2557 | 0, 0, | ||
| 2558 | 0, 0, | ||
| 2559 | 0, 0, | ||
| 2560 | 0, 0, | ||
| 2561 | MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1, | ||
| 2562 | 0, 0, | ||
| 2563 | 0, 0, | ||
| 2564 | 0, 0, | ||
| 2565 | MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1, | ||
| 2566 | 0, 0, | ||
| 2567 | MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1, | ||
| 2568 | 0, 0, | ||
| 2569 | 0, 0, | ||
| 2570 | MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1, | ||
| 2571 | 0, 0, | ||
| 2572 | 0, 0, | ||
| 2573 | 0, 0, | ||
| 2574 | MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1, | ||
| 2575 | 0, 0, | ||
| 2576 | 0, 0, | ||
| 2577 | } | ||
| 2578 | }, | ||
| 2579 | { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) { | ||
| 2580 | 0, 0, | ||
| 2581 | 0, 0, | ||
| 2582 | MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1, | ||
| 2583 | 0, 0, | ||
| 2584 | MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1, | ||
| 2585 | MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1, | ||
| 2586 | 0, 0, | ||
| 2587 | 0, 0, | ||
| 2588 | 0, 0, | ||
| 2589 | MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1, | ||
| 2590 | MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1, | ||
| 2591 | MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1, | ||
| 2592 | MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1, | ||
| 2593 | 0, 0, | ||
| 2594 | 0, 0, | ||
| 2595 | 0, 0, | ||
| 2596 | MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1, | ||
| 2597 | 0, 0, | ||
| 2598 | MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1, | ||
| 2599 | MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1, | ||
| 2600 | MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1, | ||
| 2601 | MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1, | ||
| 2602 | MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1, | ||
| 2603 | MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1, | ||
| 2604 | MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1, | ||
| 2605 | 0, 0, | ||
| 2606 | 0, 0, | ||
| 2607 | MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1, | ||
| 2608 | 0, 0, | ||
| 2609 | 0, 0, | ||
| 2610 | MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1, | ||
| 2611 | 0, 0, | ||
| 2612 | } | ||
| 2613 | }, | ||
| 2614 | { }, | ||
| 2615 | }; | ||
| 2616 | |||
| 2617 | static struct pinmux_data_reg pinmux_data_regs[] = { | ||
| 2618 | { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) { | ||
| 2619 | PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA, | ||
| 2620 | PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, | ||
| 2621 | PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA, | ||
| 2622 | PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA, | ||
| 2623 | PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA, | ||
| 2624 | PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA, | ||
| 2625 | PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA, | ||
| 2626 | PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA } | ||
| 2627 | }, | ||
| 2628 | { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) { | ||
| 2629 | PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA, | ||
| 2630 | PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA, | ||
| 2631 | PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA, | ||
| 2632 | PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA, | ||
| 2633 | PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA, | ||
| 2634 | PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA, | ||
| 2635 | PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA, | ||
| 2636 | PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA } | ||
| 2637 | }, | ||
| 2638 | { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32) { | ||
| 2639 | PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA, | ||
| 2640 | PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA, | ||
| 2641 | PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA, | ||
| 2642 | PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA, | ||
| 2643 | PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA, | ||
| 2644 | PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA, | ||
| 2645 | PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA, | ||
| 2646 | PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA } | ||
| 2647 | }, | ||
| 2648 | { PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32) { | ||
| 2649 | 0, 0, 0, 0, | ||
| 2650 | 0, 0, 0, 0, | ||
| 2651 | 0, PORT118_DATA, PORT117_DATA, PORT116_DATA, | ||
| 2652 | PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA, | ||
| 2653 | PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA, | ||
| 2654 | PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA, | ||
| 2655 | PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA, | ||
| 2656 | PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA } | ||
| 2657 | }, | ||
| 2658 | { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32) { | ||
| 2659 | PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA, | ||
| 2660 | PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA, | ||
| 2661 | PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA, | ||
| 2662 | PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA, | ||
| 2663 | PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA, | ||
| 2664 | PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA, | ||
| 2665 | PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA, | ||
| 2666 | PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA } | ||
| 2667 | }, | ||
| 2668 | { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32) { | ||
| 2669 | 0, 0, 0, 0, | ||
| 2670 | 0, 0, 0, 0, | ||
| 2671 | 0, 0, 0, 0, | ||
| 2672 | 0, 0, 0, 0, | ||
| 2673 | 0, 0, 0, 0, | ||
| 2674 | 0, 0, 0, 0, | ||
| 2675 | 0, 0, 0, PORT164_DATA, | ||
| 2676 | PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA } | ||
| 2677 | }, | ||
| 2678 | { PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32) { | ||
| 2679 | PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA, | ||
| 2680 | PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA, | ||
| 2681 | PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA, | ||
| 2682 | PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA, | ||
| 2683 | PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA, | ||
| 2684 | PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA, | ||
| 2685 | PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA, | ||
| 2686 | PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA } | ||
| 2687 | }, | ||
| 2688 | { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) { | ||
| 2689 | PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA, | ||
| 2690 | PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA, | ||
| 2691 | PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA, | ||
| 2692 | PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA, | ||
| 2693 | PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA, | ||
| 2694 | PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA, | ||
| 2695 | PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA, | ||
| 2696 | PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA } | ||
| 2697 | }, | ||
| 2698 | { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) { | ||
| 2699 | 0, 0, 0, 0, | ||
| 2700 | 0, PORT282_DATA, PORT281_DATA, PORT280_DATA, | ||
| 2701 | PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA, | ||
| 2702 | PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA, | ||
| 2703 | PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA, | ||
| 2704 | PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA, | ||
| 2705 | PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA, | ||
| 2706 | PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA } | ||
| 2707 | }, | ||
| 2708 | { PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32) { | ||
| 2709 | 0, 0, 0, 0, | ||
| 2710 | 0, 0, 0, 0, | ||
| 2711 | 0, 0, PORT309_DATA, PORT308_DATA, | ||
| 2712 | PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA, | ||
| 2713 | PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA, | ||
| 2714 | PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA, | ||
| 2715 | PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA, | ||
| 2716 | PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA } | ||
| 2717 | }, | ||
| 2718 | { }, | ||
| 2719 | }; | ||
| 2720 | |||
| 2721 | static struct pinmux_info sh73a0_pinmux_info = { | ||
| 2722 | .name = "sh73a0_pfc", | ||
| 2723 | .reserved_id = PINMUX_RESERVED, | ||
| 2724 | .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, | ||
| 2725 | .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, | ||
| 2726 | .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, | ||
| 2727 | .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, | ||
| 2728 | .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, | ||
| 2729 | .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, | ||
| 2730 | .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, | ||
| 2731 | |||
| 2732 | .first_gpio = GPIO_PORT0, | ||
| 2733 | .last_gpio = GPIO_FN_FSIAISLD_PU, | ||
| 2734 | |||
| 2735 | .gpios = pinmux_gpios, | ||
| 2736 | .cfg_regs = pinmux_config_regs, | ||
| 2737 | .data_regs = pinmux_data_regs, | ||
| 2738 | |||
| 2739 | .gpio_data = pinmux_data, | ||
| 2740 | .gpio_data_size = ARRAY_SIZE(pinmux_data), | ||
| 2741 | }; | ||
| 2742 | |||
| 2743 | void sh73a0_pinmux_init(void) | ||
| 2744 | { | ||
| 2745 | register_pinmux(&sh73a0_pinmux_info); | ||
| 2746 | } | ||
diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c new file mode 100644 index 000000000000..65e879bab4dc --- /dev/null +++ b/arch/arm/mach-shmobile/platsmp.c | |||
| @@ -0,0 +1,70 @@ | |||
| 1 | /* | ||
| 2 | * SMP support for R-Mobile / SH-Mobile | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Magnus Damm | ||
| 5 | * Copyright (C) 2011 Paul Mundt | ||
| 6 | * | ||
| 7 | * Based on vexpress, Copyright (C) 2002 ARM Ltd, All Rights Reserved | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | #include <linux/init.h> | ||
| 14 | #include <linux/errno.h> | ||
| 15 | #include <linux/delay.h> | ||
| 16 | #include <linux/device.h> | ||
| 17 | #include <linux/smp.h> | ||
| 18 | #include <linux/io.h> | ||
| 19 | #include <asm/localtimer.h> | ||
| 20 | #include <asm/mach-types.h> | ||
| 21 | #include <mach/common.h> | ||
| 22 | |||
| 23 | static unsigned int __init shmobile_smp_get_core_count(void) | ||
| 24 | { | ||
| 25 | if (machine_is_ag5evm()) | ||
| 26 | return sh73a0_get_core_count(); | ||
| 27 | |||
| 28 | return 1; | ||
| 29 | } | ||
| 30 | |||
| 31 | static void __init shmobile_smp_prepare_cpus(void) | ||
| 32 | { | ||
| 33 | if (machine_is_ag5evm()) | ||
| 34 | sh73a0_smp_prepare_cpus(); | ||
| 35 | } | ||
| 36 | |||
| 37 | void __cpuinit platform_secondary_init(unsigned int cpu) | ||
| 38 | { | ||
| 39 | trace_hardirqs_off(); | ||
| 40 | |||
| 41 | if (machine_is_ag5evm()) | ||
| 42 | sh73a0_secondary_init(cpu); | ||
| 43 | } | ||
| 44 | |||
| 45 | int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) | ||
| 46 | { | ||
| 47 | if (machine_is_ag5evm()) | ||
| 48 | return sh73a0_boot_secondary(cpu); | ||
| 49 | |||
| 50 | return -ENOSYS; | ||
| 51 | } | ||
| 52 | |||
| 53 | void __init smp_init_cpus(void) | ||
| 54 | { | ||
| 55 | unsigned int ncores = shmobile_smp_get_core_count(); | ||
| 56 | unsigned int i; | ||
| 57 | |||
| 58 | for (i = 0; i < ncores; i++) | ||
| 59 | set_cpu_possible(i, true); | ||
| 60 | } | ||
| 61 | |||
| 62 | void __init platform_smp_prepare_cpus(unsigned int max_cpus) | ||
| 63 | { | ||
| 64 | int i; | ||
| 65 | |||
| 66 | for (i = 0; i < max_cpus; i++) | ||
| 67 | set_cpu_present(i, true); | ||
| 68 | |||
| 69 | shmobile_smp_prepare_cpus(); | ||
| 70 | } | ||
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c index 564a6d0be473..2e3e11ee7c43 100644 --- a/arch/arm/mach-shmobile/setup-sh7372.c +++ b/arch/arm/mach-shmobile/setup-sh7372.c | |||
| @@ -416,6 +416,16 @@ static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = { | |||
| 416 | .addr = 0xe6870030, | 416 | .addr = 0xe6870030, |
| 417 | .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), | 417 | .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), |
| 418 | .mid_rid = 0xce, | 418 | .mid_rid = 0xce, |
| 419 | }, { | ||
| 420 | .slave_id = SHDMA_SLAVE_MMCIF_TX, | ||
| 421 | .addr = 0xe6bd0034, | ||
| 422 | .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), | ||
| 423 | .mid_rid = 0xd1, | ||
| 424 | }, { | ||
| 425 | .slave_id = SHDMA_SLAVE_MMCIF_RX, | ||
| 426 | .addr = 0xe6bd0034, | ||
| 427 | .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), | ||
| 428 | .mid_rid = 0xd2, | ||
| 419 | }, | 429 | }, |
| 420 | }; | 430 | }; |
| 421 | 431 | ||
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c new file mode 100644 index 000000000000..f1eff8b37bd6 --- /dev/null +++ b/arch/arm/mach-shmobile/setup-sh73a0.c | |||
| @@ -0,0 +1,412 @@ | |||
| 1 | /* | ||
| 2 | * sh73a0 processor support | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Takashi Yoshii | ||
| 5 | * Copyright (C) 2010 Magnus Damm | ||
| 6 | * Copyright (C) 2008 Yoshihiro Shimoda | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; version 2 of the License. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 20 | */ | ||
| 21 | #include <linux/kernel.h> | ||
| 22 | #include <linux/init.h> | ||
| 23 | #include <linux/interrupt.h> | ||
| 24 | #include <linux/irq.h> | ||
| 25 | #include <linux/platform_device.h> | ||
| 26 | #include <linux/delay.h> | ||
| 27 | #include <linux/input.h> | ||
| 28 | #include <linux/io.h> | ||
| 29 | #include <linux/serial_sci.h> | ||
| 30 | #include <linux/sh_intc.h> | ||
| 31 | #include <linux/sh_timer.h> | ||
| 32 | #include <mach/hardware.h> | ||
| 33 | #include <asm/mach-types.h> | ||
| 34 | #include <asm/mach/arch.h> | ||
| 35 | |||
| 36 | static struct plat_sci_port scif0_platform_data = { | ||
| 37 | .mapbase = 0xe6c40000, | ||
| 38 | .flags = UPF_BOOT_AUTOCONF, | ||
| 39 | .type = PORT_SCIFA, | ||
| 40 | .irqs = { gic_spi(72), gic_spi(72), | ||
| 41 | gic_spi(72), gic_spi(72) }, | ||
| 42 | }; | ||
| 43 | |||
| 44 | static struct platform_device scif0_device = { | ||
| 45 | .name = "sh-sci", | ||
| 46 | .id = 0, | ||
| 47 | .dev = { | ||
| 48 | .platform_data = &scif0_platform_data, | ||
| 49 | }, | ||
| 50 | }; | ||
| 51 | |||
| 52 | static struct plat_sci_port scif1_platform_data = { | ||
| 53 | .mapbase = 0xe6c50000, | ||
| 54 | .flags = UPF_BOOT_AUTOCONF, | ||
| 55 | .type = PORT_SCIFA, | ||
| 56 | .irqs = { gic_spi(73), gic_spi(73), | ||
| 57 | gic_spi(73), gic_spi(73) }, | ||
| 58 | }; | ||
| 59 | |||
| 60 | static struct platform_device scif1_device = { | ||
| 61 | .name = "sh-sci", | ||
| 62 | .id = 1, | ||
| 63 | .dev = { | ||
| 64 | .platform_data = &scif1_platform_data, | ||
| 65 | }, | ||
| 66 | }; | ||
| 67 | |||
| 68 | static struct plat_sci_port scif2_platform_data = { | ||
| 69 | .mapbase = 0xe6c60000, | ||
| 70 | .flags = UPF_BOOT_AUTOCONF, | ||
| 71 | .type = PORT_SCIFA, | ||
| 72 | .irqs = { gic_spi(74), gic_spi(74), | ||
| 73 | gic_spi(74), gic_spi(74) }, | ||
| 74 | }; | ||
| 75 | |||
| 76 | static struct platform_device scif2_device = { | ||
| 77 | .name = "sh-sci", | ||
| 78 | .id = 2, | ||
| 79 | .dev = { | ||
| 80 | .platform_data = &scif2_platform_data, | ||
| 81 | }, | ||
| 82 | }; | ||
| 83 | |||
| 84 | static struct plat_sci_port scif3_platform_data = { | ||
| 85 | .mapbase = 0xe6c70000, | ||
| 86 | .flags = UPF_BOOT_AUTOCONF, | ||
| 87 | .type = PORT_SCIFA, | ||
| 88 | .irqs = { gic_spi(75), gic_spi(75), | ||
| 89 | gic_spi(75), gic_spi(75) }, | ||
| 90 | }; | ||
| 91 | |||
| 92 | static struct platform_device scif3_device = { | ||
| 93 | .name = "sh-sci", | ||
| 94 | .id = 3, | ||
| 95 | .dev = { | ||
| 96 | .platform_data = &scif3_platform_data, | ||
| 97 | }, | ||
| 98 | }; | ||
| 99 | |||
| 100 | static struct plat_sci_port scif4_platform_data = { | ||
| 101 | .mapbase = 0xe6c80000, | ||
| 102 | .flags = UPF_BOOT_AUTOCONF, | ||
| 103 | .type = PORT_SCIFA, | ||
| 104 | .irqs = { gic_spi(78), gic_spi(78), | ||
| 105 | gic_spi(78), gic_spi(78) }, | ||
| 106 | }; | ||
| 107 | |||
| 108 | static struct platform_device scif4_device = { | ||
| 109 | .name = "sh-sci", | ||
| 110 | .id = 4, | ||
| 111 | .dev = { | ||
| 112 | .platform_data = &scif4_platform_data, | ||
| 113 | }, | ||
| 114 | }; | ||
| 115 | |||
| 116 | static struct plat_sci_port scif5_platform_data = { | ||
| 117 | .mapbase = 0xe6cb0000, | ||
| 118 | .flags = UPF_BOOT_AUTOCONF, | ||
| 119 | .type = PORT_SCIFA, | ||
| 120 | .irqs = { gic_spi(79), gic_spi(79), | ||
| 121 | gic_spi(79), gic_spi(79) }, | ||
| 122 | }; | ||
| 123 | |||
| 124 | static struct platform_device scif5_device = { | ||
| 125 | .name = "sh-sci", | ||
| 126 | .id = 5, | ||
| 127 | .dev = { | ||
| 128 | .platform_data = &scif5_platform_data, | ||
| 129 | }, | ||
| 130 | }; | ||
| 131 | |||
| 132 | static struct plat_sci_port scif6_platform_data = { | ||
| 133 | .mapbase = 0xe6cc0000, | ||
| 134 | .flags = UPF_BOOT_AUTOCONF, | ||
| 135 | .type = PORT_SCIFA, | ||
| 136 | .irqs = { gic_spi(156), gic_spi(156), | ||
| 137 | gic_spi(156), gic_spi(156) }, | ||
| 138 | }; | ||
| 139 | |||
| 140 | static struct platform_device scif6_device = { | ||
| 141 | .name = "sh-sci", | ||
| 142 | .id = 6, | ||
| 143 | .dev = { | ||
| 144 | .platform_data = &scif6_platform_data, | ||
| 145 | }, | ||
| 146 | }; | ||
| 147 | |||
| 148 | static struct plat_sci_port scif7_platform_data = { | ||
| 149 | .mapbase = 0xe6cd0000, | ||
| 150 | .flags = UPF_BOOT_AUTOCONF, | ||
| 151 | .type = PORT_SCIFA, | ||
| 152 | .irqs = { gic_spi(143), gic_spi(143), | ||
| 153 | gic_spi(143), gic_spi(143) }, | ||
| 154 | }; | ||
| 155 | |||
| 156 | static struct platform_device scif7_device = { | ||
| 157 | .name = "sh-sci", | ||
| 158 | .id = 7, | ||
| 159 | .dev = { | ||
| 160 | .platform_data = &scif7_platform_data, | ||
| 161 | }, | ||
| 162 | }; | ||
| 163 | |||
| 164 | static struct plat_sci_port scif8_platform_data = { | ||
| 165 | .mapbase = 0xe6c30000, | ||
| 166 | .flags = UPF_BOOT_AUTOCONF, | ||
| 167 | .type = PORT_SCIFB, | ||
| 168 | .irqs = { gic_spi(80), gic_spi(80), | ||
| 169 | gic_spi(80), gic_spi(80) }, | ||
| 170 | }; | ||
| 171 | |||
| 172 | static struct platform_device scif8_device = { | ||
| 173 | .name = "sh-sci", | ||
| 174 | .id = 8, | ||
| 175 | .dev = { | ||
| 176 | .platform_data = &scif8_platform_data, | ||
| 177 | }, | ||
| 178 | }; | ||
| 179 | |||
| 180 | static struct sh_timer_config cmt10_platform_data = { | ||
| 181 | .name = "CMT10", | ||
| 182 | .channel_offset = 0x10, | ||
| 183 | .timer_bit = 0, | ||
| 184 | .clockevent_rating = 125, | ||
| 185 | .clocksource_rating = 125, | ||
| 186 | }; | ||
| 187 | |||
| 188 | static struct resource cmt10_resources[] = { | ||
| 189 | [0] = { | ||
| 190 | .name = "CMT10", | ||
| 191 | .start = 0xe6138010, | ||
| 192 | .end = 0xe613801b, | ||
| 193 | .flags = IORESOURCE_MEM, | ||
| 194 | }, | ||
| 195 | [1] = { | ||
| 196 | .start = gic_spi(65), | ||
| 197 | .flags = IORESOURCE_IRQ, | ||
| 198 | }, | ||
| 199 | }; | ||
| 200 | |||
| 201 | static struct platform_device cmt10_device = { | ||
| 202 | .name = "sh_cmt", | ||
| 203 | .id = 10, | ||
| 204 | .dev = { | ||
| 205 | .platform_data = &cmt10_platform_data, | ||
| 206 | }, | ||
| 207 | .resource = cmt10_resources, | ||
| 208 | .num_resources = ARRAY_SIZE(cmt10_resources), | ||
| 209 | }; | ||
| 210 | |||
| 211 | /* TMU */ | ||
| 212 | static struct sh_timer_config tmu00_platform_data = { | ||
| 213 | .name = "TMU00", | ||
| 214 | .channel_offset = 0x4, | ||
| 215 | .timer_bit = 0, | ||
| 216 | .clockevent_rating = 200, | ||
| 217 | }; | ||
| 218 | |||
| 219 | static struct resource tmu00_resources[] = { | ||
| 220 | [0] = { | ||
| 221 | .name = "TMU00", | ||
| 222 | .start = 0xfff60008, | ||
| 223 | .end = 0xfff60013, | ||
| 224 | .flags = IORESOURCE_MEM, | ||
| 225 | }, | ||
| 226 | [1] = { | ||
| 227 | .start = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */ | ||
| 228 | .flags = IORESOURCE_IRQ, | ||
| 229 | }, | ||
| 230 | }; | ||
| 231 | |||
| 232 | static struct platform_device tmu00_device = { | ||
| 233 | .name = "sh_tmu", | ||
| 234 | .id = 0, | ||
| 235 | .dev = { | ||
| 236 | .platform_data = &tmu00_platform_data, | ||
| 237 | }, | ||
| 238 | .resource = tmu00_resources, | ||
| 239 | .num_resources = ARRAY_SIZE(tmu00_resources), | ||
| 240 | }; | ||
| 241 | |||
| 242 | static struct sh_timer_config tmu01_platform_data = { | ||
| 243 | .name = "TMU01", | ||
| 244 | .channel_offset = 0x10, | ||
| 245 | .timer_bit = 1, | ||
| 246 | .clocksource_rating = 200, | ||
| 247 | }; | ||
| 248 | |||
| 249 | static struct resource tmu01_resources[] = { | ||
| 250 | [0] = { | ||
| 251 | .name = "TMU01", | ||
| 252 | .start = 0xfff60014, | ||
| 253 | .end = 0xfff6001f, | ||
| 254 | .flags = IORESOURCE_MEM, | ||
| 255 | }, | ||
| 256 | [1] = { | ||
| 257 | .start = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */ | ||
| 258 | .flags = IORESOURCE_IRQ, | ||
| 259 | }, | ||
| 260 | }; | ||
| 261 | |||
| 262 | static struct platform_device tmu01_device = { | ||
| 263 | .name = "sh_tmu", | ||
| 264 | .id = 1, | ||
| 265 | .dev = { | ||
| 266 | .platform_data = &tmu01_platform_data, | ||
| 267 | }, | ||
| 268 | .resource = tmu01_resources, | ||
| 269 | .num_resources = ARRAY_SIZE(tmu01_resources), | ||
| 270 | }; | ||
| 271 | |||
| 272 | static struct resource i2c0_resources[] = { | ||
| 273 | [0] = { | ||
| 274 | .name = "IIC0", | ||
| 275 | .start = 0xe6820000, | ||
| 276 | .end = 0xe6820425 - 1, | ||
| 277 | .flags = IORESOURCE_MEM, | ||
| 278 | }, | ||
| 279 | [1] = { | ||
| 280 | .start = gic_spi(167), | ||
| 281 | .end = gic_spi(170), | ||
| 282 | .flags = IORESOURCE_IRQ, | ||
| 283 | }, | ||
| 284 | }; | ||
| 285 | |||
| 286 | static struct resource i2c1_resources[] = { | ||
| 287 | [0] = { | ||
| 288 | .name = "IIC1", | ||
| 289 | .start = 0xe6822000, | ||
| 290 | .end = 0xe6822425 - 1, | ||
| 291 | .flags = IORESOURCE_MEM, | ||
| 292 | }, | ||
| 293 | [1] = { | ||
| 294 | .start = gic_spi(51), | ||
| 295 | .end = gic_spi(54), | ||
| 296 | .flags = IORESOURCE_IRQ, | ||
| 297 | }, | ||
| 298 | }; | ||
| 299 | |||
| 300 | static struct resource i2c2_resources[] = { | ||
| 301 | [0] = { | ||
| 302 | .name = "IIC2", | ||
| 303 | .start = 0xe6824000, | ||
| 304 | .end = 0xe6824425 - 1, | ||
| 305 | .flags = IORESOURCE_MEM, | ||
| 306 | }, | ||
| 307 | [1] = { | ||
| 308 | .start = gic_spi(171), | ||
| 309 | .end = gic_spi(174), | ||
| 310 | .flags = IORESOURCE_IRQ, | ||
| 311 | }, | ||
| 312 | }; | ||
| 313 | |||
| 314 | static struct resource i2c3_resources[] = { | ||
| 315 | [0] = { | ||
| 316 | .name = "IIC3", | ||
| 317 | .start = 0xe6826000, | ||
| 318 | .end = 0xe6826425 - 1, | ||
| 319 | .flags = IORESOURCE_MEM, | ||
| 320 | }, | ||
| 321 | [1] = { | ||
| 322 | .start = gic_spi(183), | ||
| 323 | .end = gic_spi(186), | ||
| 324 | .flags = IORESOURCE_IRQ, | ||
| 325 | }, | ||
| 326 | }; | ||
| 327 | |||
| 328 | static struct resource i2c4_resources[] = { | ||
| 329 | [0] = { | ||
| 330 | .name = "IIC4", | ||
| 331 | .start = 0xe6828000, | ||
| 332 | .end = 0xe6828425 - 1, | ||
| 333 | .flags = IORESOURCE_MEM, | ||
| 334 | }, | ||
| 335 | [1] = { | ||
| 336 | .start = gic_spi(187), | ||
| 337 | .end = gic_spi(190), | ||
| 338 | .flags = IORESOURCE_IRQ, | ||
| 339 | }, | ||
| 340 | }; | ||
| 341 | |||
| 342 | static struct platform_device i2c0_device = { | ||
| 343 | .name = "i2c-sh_mobile", | ||
| 344 | .id = 0, | ||
| 345 | .resource = i2c0_resources, | ||
| 346 | .num_resources = ARRAY_SIZE(i2c0_resources), | ||
| 347 | }; | ||
| 348 | |||
| 349 | static struct platform_device i2c1_device = { | ||
| 350 | .name = "i2c-sh_mobile", | ||
| 351 | .id = 1, | ||
| 352 | .resource = i2c1_resources, | ||
| 353 | .num_resources = ARRAY_SIZE(i2c1_resources), | ||
| 354 | }; | ||
| 355 | |||
| 356 | static struct platform_device i2c2_device = { | ||
| 357 | .name = "i2c-sh_mobile", | ||
| 358 | .id = 2, | ||
| 359 | .resource = i2c2_resources, | ||
| 360 | .num_resources = ARRAY_SIZE(i2c2_resources), | ||
| 361 | }; | ||
| 362 | |||
| 363 | static struct platform_device i2c3_device = { | ||
| 364 | .name = "i2c-sh_mobile", | ||
| 365 | .id = 3, | ||
| 366 | .resource = i2c3_resources, | ||
| 367 | .num_resources = ARRAY_SIZE(i2c3_resources), | ||
| 368 | }; | ||
| 369 | |||
| 370 | static struct platform_device i2c4_device = { | ||
| 371 | .name = "i2c-sh_mobile", | ||
| 372 | .id = 4, | ||
| 373 | .resource = i2c4_resources, | ||
| 374 | .num_resources = ARRAY_SIZE(i2c4_resources), | ||
| 375 | }; | ||
| 376 | |||
| 377 | static struct platform_device *sh73a0_early_devices[] __initdata = { | ||
| 378 | &scif0_device, | ||
| 379 | &scif1_device, | ||
| 380 | &scif2_device, | ||
| 381 | &scif3_device, | ||
| 382 | &scif4_device, | ||
| 383 | &scif5_device, | ||
| 384 | &scif6_device, | ||
| 385 | &scif7_device, | ||
| 386 | &scif8_device, | ||
| 387 | &cmt10_device, | ||
| 388 | &tmu00_device, | ||
| 389 | &tmu01_device, | ||
| 390 | }; | ||
| 391 | |||
| 392 | static struct platform_device *sh73a0_late_devices[] __initdata = { | ||
| 393 | &i2c0_device, | ||
| 394 | &i2c1_device, | ||
| 395 | &i2c2_device, | ||
| 396 | &i2c3_device, | ||
| 397 | &i2c4_device, | ||
| 398 | }; | ||
| 399 | |||
| 400 | void __init sh73a0_add_standard_devices(void) | ||
| 401 | { | ||
| 402 | platform_add_devices(sh73a0_early_devices, | ||
| 403 | ARRAY_SIZE(sh73a0_early_devices)); | ||
| 404 | platform_add_devices(sh73a0_late_devices, | ||
| 405 | ARRAY_SIZE(sh73a0_late_devices)); | ||
| 406 | } | ||
| 407 | |||
| 408 | void __init sh73a0_add_early_devices(void) | ||
| 409 | { | ||
| 410 | early_platform_add_devices(sh73a0_early_devices, | ||
| 411 | ARRAY_SIZE(sh73a0_early_devices)); | ||
| 412 | } | ||
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c new file mode 100644 index 000000000000..a156d2108df1 --- /dev/null +++ b/arch/arm/mach-shmobile/smp-sh73a0.c | |||
| @@ -0,0 +1,97 @@ | |||
| 1 | /* | ||
| 2 | * SMP support for R-Mobile / SH-Mobile - sh73a0 portion | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Magnus Damm | ||
| 5 | * Copyright (C) 2010 Takashi Yoshii | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; version 2 of the License. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 19 | */ | ||
| 20 | #include <linux/kernel.h> | ||
| 21 | #include <linux/init.h> | ||
| 22 | #include <linux/smp.h> | ||
| 23 | #include <linux/spinlock.h> | ||
| 24 | #include <linux/io.h> | ||
| 25 | #include <mach/common.h> | ||
| 26 | #include <asm/smp_scu.h> | ||
| 27 | #include <asm/smp_twd.h> | ||
| 28 | #include <asm/hardware/gic.h> | ||
| 29 | |||
| 30 | #define WUPCR 0xe6151010 | ||
| 31 | #define SRESCR 0xe6151018 | ||
| 32 | #define PSTR 0xe6151040 | ||
| 33 | #define SBAR 0xe6180020 | ||
| 34 | #define APARMBAREA 0xe6f10020 | ||
| 35 | |||
| 36 | static void __iomem *scu_base_addr(void) | ||
| 37 | { | ||
| 38 | return (void __iomem *)0xf0000000; | ||
| 39 | } | ||
| 40 | |||
| 41 | static DEFINE_SPINLOCK(scu_lock); | ||
| 42 | static unsigned long tmp; | ||
| 43 | |||
| 44 | static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) | ||
| 45 | { | ||
| 46 | void __iomem *scu_base = scu_base_addr(); | ||
| 47 | |||
| 48 | spin_lock(&scu_lock); | ||
| 49 | tmp = __raw_readl(scu_base + 8); | ||
| 50 | tmp &= ~clr; | ||
| 51 | tmp |= set; | ||
| 52 | spin_unlock(&scu_lock); | ||
| 53 | |||
| 54 | /* disable cache coherency after releasing the lock */ | ||
| 55 | __raw_writel(tmp, scu_base + 8); | ||
| 56 | } | ||
| 57 | |||
| 58 | unsigned int __init sh73a0_get_core_count(void) | ||
| 59 | { | ||
| 60 | void __iomem *scu_base = scu_base_addr(); | ||
| 61 | |||
| 62 | return scu_get_core_count(scu_base); | ||
| 63 | } | ||
| 64 | |||
| 65 | void __cpuinit sh73a0_secondary_init(unsigned int cpu) | ||
| 66 | { | ||
| 67 | gic_secondary_init(0); | ||
| 68 | } | ||
| 69 | |||
| 70 | int __cpuinit sh73a0_boot_secondary(unsigned int cpu) | ||
| 71 | { | ||
| 72 | /* enable cache coherency */ | ||
| 73 | modify_scu_cpu_psr(0, 3 << (cpu * 8)); | ||
| 74 | |||
| 75 | if (((__raw_readw(__io(PSTR)) >> (4 * cpu)) & 3) == 3) | ||
| 76 | __raw_writel(1 << cpu, __io(WUPCR)); /* wake up */ | ||
| 77 | else | ||
| 78 | __raw_writel(1 << cpu, __io(SRESCR)); /* reset */ | ||
| 79 | |||
| 80 | return 0; | ||
| 81 | } | ||
| 82 | |||
| 83 | void __init sh73a0_smp_prepare_cpus(void) | ||
| 84 | { | ||
| 85 | #ifdef CONFIG_HAVE_ARM_TWD | ||
| 86 | twd_base = (void __iomem *)0xf0000600; | ||
| 87 | #endif | ||
| 88 | |||
| 89 | scu_enable(scu_base_addr()); | ||
| 90 | |||
| 91 | /* Map the reset vector (in headsmp.S) */ | ||
| 92 | __raw_writel(0, __io(APARMBAREA)); /* 4k */ | ||
| 93 | __raw_writel(__pa(shmobile_secondary_vector), __io(SBAR)); | ||
| 94 | |||
| 95 | /* enable cache coherency on CPU0 */ | ||
| 96 | modify_scu_cpu_psr(0, 3 << (0 * 8)); | ||
| 97 | } | ||
diff --git a/arch/arm/mach-tcc8k/clock.c b/arch/arm/mach-tcc8k/clock.c index ba32a15127ab..3970a9cdce26 100644 --- a/arch/arm/mach-tcc8k/clock.c +++ b/arch/arm/mach-tcc8k/clock.c | |||
| @@ -12,8 +12,7 @@ | |||
| 12 | #include <linux/io.h> | 12 | #include <linux/io.h> |
| 13 | #include <linux/module.h> | 13 | #include <linux/module.h> |
| 14 | #include <linux/spinlock.h> | 14 | #include <linux/spinlock.h> |
| 15 | 15 | #include <linux/clkdev.h> | |
| 16 | #include <asm/clkdev.h> | ||
| 17 | 16 | ||
| 18 | #include <mach/clock.h> | 17 | #include <mach/clock.h> |
| 19 | #include <mach/irqs.h> | 18 | #include <mach/irqs.h> |
diff --git a/arch/arm/mach-tcc8k/time.c b/arch/arm/mach-tcc8k/time.c index 78d06008841d..e0a8d609afe1 100644 --- a/arch/arm/mach-tcc8k/time.c +++ b/arch/arm/mach-tcc8k/time.c | |||
| @@ -35,7 +35,6 @@ static struct clocksource clocksource_tcc = { | |||
| 35 | .rating = 200, | 35 | .rating = 200, |
| 36 | .read = tcc_get_cycles, | 36 | .read = tcc_get_cycles, |
| 37 | .mask = CLOCKSOURCE_MASK(32), | 37 | .mask = CLOCKSOURCE_MASK(32), |
| 38 | .shift = 28, | ||
| 39 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 38 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 40 | }; | 39 | }; |
| 41 | 40 | ||
| @@ -103,9 +102,7 @@ static int __init tcc_clockevent_init(struct clk *clock) | |||
| 103 | { | 102 | { |
| 104 | unsigned int c = clk_get_rate(clock); | 103 | unsigned int c = clk_get_rate(clock); |
| 105 | 104 | ||
| 106 | clocksource_tcc.mult = clocksource_hz2mult(c, | 105 | clocksource_register_hz(&clocksource_tcc, c); |
| 107 | clocksource_tcc.shift); | ||
| 108 | clocksource_register(&clocksource_tcc); | ||
| 109 | 106 | ||
| 110 | clockevent_tcc.mult = div_sc(c, NSEC_PER_SEC, | 107 | clockevent_tcc.mult = div_sc(c, NSEC_PER_SEC, |
| 111 | clockevent_tcc.shift); | 108 | clockevent_tcc.shift); |
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index ae19f95585be..77948e0f4909 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c | |||
| @@ -25,7 +25,7 @@ | |||
| 25 | #include <linux/slab.h> | 25 | #include <linux/slab.h> |
| 26 | #include <linux/seq_file.h> | 26 | #include <linux/seq_file.h> |
| 27 | #include <linux/regulator/consumer.h> | 27 | #include <linux/regulator/consumer.h> |
| 28 | #include <asm/clkdev.h> | 28 | #include <linux/clkdev.h> |
| 29 | 29 | ||
| 30 | #include "clock.h" | 30 | #include "clock.h" |
| 31 | #include "board.h" | 31 | #include "board.h" |
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h index 94fd859770f1..083a4cfc6cf0 100644 --- a/arch/arm/mach-tegra/clock.h +++ b/arch/arm/mach-tegra/clock.h | |||
| @@ -21,7 +21,7 @@ | |||
| 21 | #define __MACH_TEGRA_CLOCK_H | 21 | #define __MACH_TEGRA_CLOCK_H |
| 22 | 22 | ||
| 23 | #include <linux/list.h> | 23 | #include <linux/list.h> |
| 24 | #include <asm/clkdev.h> | 24 | #include <linux/clkdev.h> |
| 25 | 25 | ||
| 26 | #define DIV_BUS (1 << 0) | 26 | #define DIV_BUS (1 << 0) |
| 27 | #define DIV_U71 (1 << 1) | 27 | #define DIV_U71 (1 << 1) |
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c index 8e7f115aa21e..a5cb1ce76ff2 100644 --- a/arch/arm/mach-tegra/hotplug.c +++ b/arch/arm/mach-tegra/hotplug.c | |||
| @@ -11,12 +11,9 @@ | |||
| 11 | #include <linux/kernel.h> | 11 | #include <linux/kernel.h> |
| 12 | #include <linux/errno.h> | 12 | #include <linux/errno.h> |
| 13 | #include <linux/smp.h> | 13 | #include <linux/smp.h> |
| 14 | #include <linux/completion.h> | ||
| 15 | 14 | ||
| 16 | #include <asm/cacheflush.h> | 15 | #include <asm/cacheflush.h> |
| 17 | 16 | ||
| 18 | static DECLARE_COMPLETION(cpu_killed); | ||
| 19 | |||
| 20 | static inline void cpu_enter_lowpower(void) | 17 | static inline void cpu_enter_lowpower(void) |
| 21 | { | 18 | { |
| 22 | unsigned int v; | 19 | unsigned int v; |
| @@ -29,13 +26,13 @@ static inline void cpu_enter_lowpower(void) | |||
| 29 | * Turn off coherency | 26 | * Turn off coherency |
| 30 | */ | 27 | */ |
| 31 | " mrc p15, 0, %0, c1, c0, 1\n" | 28 | " mrc p15, 0, %0, c1, c0, 1\n" |
| 32 | " bic %0, %0, #0x20\n" | 29 | " bic %0, %0, %2\n" |
| 33 | " mcr p15, 0, %0, c1, c0, 1\n" | 30 | " mcr p15, 0, %0, c1, c0, 1\n" |
| 34 | " mrc p15, 0, %0, c1, c0, 0\n" | 31 | " mrc p15, 0, %0, c1, c0, 0\n" |
| 35 | " bic %0, %0, #0x04\n" | 32 | " bic %0, %0, #0x04\n" |
| 36 | " mcr p15, 0, %0, c1, c0, 0\n" | 33 | " mcr p15, 0, %0, c1, c0, 0\n" |
| 37 | : "=&r" (v) | 34 | : "=&r" (v) |
| 38 | : "r" (0) | 35 | : "r" (0), "Ir" (CR_C) |
| 39 | : "cc"); | 36 | : "cc"); |
| 40 | } | 37 | } |
| 41 | 38 | ||
| @@ -45,17 +42,17 @@ static inline void cpu_leave_lowpower(void) | |||
| 45 | 42 | ||
| 46 | asm volatile( | 43 | asm volatile( |
| 47 | "mrc p15, 0, %0, c1, c0, 0\n" | 44 | "mrc p15, 0, %0, c1, c0, 0\n" |
| 48 | " orr %0, %0, #0x04\n" | 45 | " orr %0, %0, %1\n" |
| 49 | " mcr p15, 0, %0, c1, c0, 0\n" | 46 | " mcr p15, 0, %0, c1, c0, 0\n" |
| 50 | " mrc p15, 0, %0, c1, c0, 1\n" | 47 | " mrc p15, 0, %0, c1, c0, 1\n" |
| 51 | " orr %0, %0, #0x20\n" | 48 | " orr %0, %0, #0x20\n" |
| 52 | " mcr p15, 0, %0, c1, c0, 1\n" | 49 | " mcr p15, 0, %0, c1, c0, 1\n" |
| 53 | : "=&r" (v) | 50 | : "=&r" (v) |
| 54 | : | 51 | : "Ir" (CR_C) |
| 55 | : "cc"); | 52 | : "cc"); |
| 56 | } | 53 | } |
| 57 | 54 | ||
| 58 | static inline void platform_do_lowpower(unsigned int cpu) | 55 | static inline void platform_do_lowpower(unsigned int cpu, int *spurious) |
| 59 | { | 56 | { |
| 60 | /* | 57 | /* |
| 61 | * there is no power-control hardware on this platform, so all | 58 | * there is no power-control hardware on this platform, so all |
| @@ -79,22 +76,19 @@ static inline void platform_do_lowpower(unsigned int cpu) | |||
| 79 | /*}*/ | 76 | /*}*/ |
| 80 | 77 | ||
| 81 | /* | 78 | /* |
| 82 | * getting here, means that we have come out of WFI without | 79 | * Getting here, means that we have come out of WFI without |
| 83 | * having been woken up - this shouldn't happen | 80 | * having been woken up - this shouldn't happen |
| 84 | * | 81 | * |
| 85 | * The trouble is, letting people know about this is not really | 82 | * Just note it happening - when we're woken, we can report |
| 86 | * possible, since we are currently running incoherently, and | 83 | * its occurrence. |
| 87 | * therefore cannot safely call printk() or anything else | ||
| 88 | */ | 84 | */ |
| 89 | #ifdef DEBUG | 85 | (*spurious)++; |
| 90 | printk(KERN_WARN "CPU%u: spurious wakeup call\n", cpu); | ||
| 91 | #endif | ||
| 92 | } | 86 | } |
| 93 | } | 87 | } |
| 94 | 88 | ||
| 95 | int platform_cpu_kill(unsigned int cpu) | 89 | int platform_cpu_kill(unsigned int cpu) |
| 96 | { | 90 | { |
| 97 | return wait_for_completion_timeout(&cpu_killed, 5000); | 91 | return 1; |
| 98 | } | 92 | } |
| 99 | 93 | ||
| 100 | /* | 94 | /* |
| @@ -104,30 +98,22 @@ int platform_cpu_kill(unsigned int cpu) | |||
| 104 | */ | 98 | */ |
| 105 | void platform_cpu_die(unsigned int cpu) | 99 | void platform_cpu_die(unsigned int cpu) |
| 106 | { | 100 | { |
| 107 | #ifdef DEBUG | 101 | int spurious = 0; |
| 108 | unsigned int this_cpu = hard_smp_processor_id(); | ||
| 109 | |||
| 110 | if (cpu != this_cpu) { | ||
| 111 | printk(KERN_CRIT "Eek! platform_cpu_die running on %u, should be %u\n", | ||
| 112 | this_cpu, cpu); | ||
| 113 | BUG(); | ||
| 114 | } | ||
| 115 | #endif | ||
| 116 | |||
| 117 | printk(KERN_NOTICE "CPU%u: shutdown\n", cpu); | ||
| 118 | complete(&cpu_killed); | ||
| 119 | 102 | ||
| 120 | /* | 103 | /* |
| 121 | * we're ready for shutdown now, so do it | 104 | * we're ready for shutdown now, so do it |
| 122 | */ | 105 | */ |
| 123 | cpu_enter_lowpower(); | 106 | cpu_enter_lowpower(); |
| 124 | platform_do_lowpower(cpu); | 107 | platform_do_lowpower(cpu, &spurious); |
| 125 | 108 | ||
| 126 | /* | 109 | /* |
| 127 | * bring this CPU back into the world of cache | 110 | * bring this CPU back into the world of cache |
| 128 | * coherency, and then restore interrupts | 111 | * coherency, and then restore interrupts |
| 129 | */ | 112 | */ |
| 130 | cpu_leave_lowpower(); | 113 | cpu_leave_lowpower(); |
| 114 | |||
| 115 | if (spurious) | ||
| 116 | pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious); | ||
| 131 | } | 117 | } |
| 132 | 118 | ||
| 133 | int platform_cpu_disable(unsigned int cpu) | 119 | int platform_cpu_disable(unsigned int cpu) |
diff --git a/arch/arm/mach-tegra/include/mach/entry-macro.S b/arch/arm/mach-tegra/include/mach/entry-macro.S index 2ba9e5c9d2f6..dd165c53889d 100644 --- a/arch/arm/mach-tegra/include/mach/entry-macro.S +++ b/arch/arm/mach-tegra/include/mach/entry-macro.S | |||
| @@ -16,8 +16,8 @@ | |||
| 16 | #include <mach/io.h> | 16 | #include <mach/io.h> |
| 17 | 17 | ||
| 18 | #if defined(CONFIG_ARM_GIC) | 18 | #if defined(CONFIG_ARM_GIC) |
| 19 | 19 | #define HAVE_GET_IRQNR_PREAMBLE | |
| 20 | #include <asm/hardware/gic.h> | 20 | #include <asm/hardware/entry-macro-gic.S> |
| 21 | 21 | ||
| 22 | /* Uses the GIC interrupt controller built into the cpu */ | 22 | /* Uses the GIC interrupt controller built into the cpu */ |
| 23 | #define ICTRL_BASE (IO_CPU_VIRT + 0x100) | 23 | #define ICTRL_BASE (IO_CPU_VIRT + 0x100) |
| @@ -32,68 +32,6 @@ | |||
| 32 | 32 | ||
| 33 | .macro arch_ret_to_user, tmp1, tmp2 | 33 | .macro arch_ret_to_user, tmp1, tmp2 |
| 34 | .endm | 34 | .endm |
| 35 | |||
| 36 | /* | ||
| 37 | * The interrupt numbering scheme is defined in the | ||
| 38 | * interrupt controller spec. To wit: | ||
| 39 | * | ||
| 40 | * Interrupts 0-15 are IPI | ||
| 41 | * 16-28 are reserved | ||
| 42 | * 29-31 are local. We allow 30 to be used for the watchdog. | ||
| 43 | * 32-1020 are global | ||
| 44 | * 1021-1022 are reserved | ||
| 45 | * 1023 is "spurious" (no interrupt) | ||
| 46 | * | ||
| 47 | * For now, we ignore all local interrupts so only return an interrupt | ||
| 48 | * if it's between 30 and 1020. The test_for_ipi routine below will | ||
| 49 | * pick up on IPIs. | ||
| 50 | * | ||
| 51 | * A simple read from the controller will tell us the number of the | ||
| 52 | * highest priority enabled interrupt. We then just need to check | ||
| 53 | * whether it is in the valid range for an IRQ (30-1020 inclusive). | ||
| 54 | */ | ||
| 55 | |||
| 56 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 57 | |||
| 58 | /* bits 12-10 = src CPU, 9-0 = int # */ | ||
| 59 | ldr \irqstat, [\base, #GIC_CPU_INTACK] | ||
| 60 | |||
| 61 | ldr \tmp, =1021 | ||
| 62 | |||
| 63 | bic \irqnr, \irqstat, #0x1c00 | ||
| 64 | |||
| 65 | cmp \irqnr, #29 | ||
| 66 | cmpcc \irqnr, \irqnr | ||
| 67 | cmpne \irqnr, \tmp | ||
| 68 | cmpcs \irqnr, \irqnr | ||
| 69 | |||
| 70 | .endm | ||
| 71 | |||
| 72 | /* We assume that irqstat (the raw value of the IRQ acknowledge | ||
| 73 | * register) is preserved from the macro above. | ||
| 74 | * If there is an IPI, we immediately signal end of interrupt on the | ||
| 75 | * controller, since this requires the original irqstat value which | ||
| 76 | * we won't easily be able to recreate later. | ||
| 77 | */ | ||
| 78 | |||
| 79 | .macro test_for_ipi, irqnr, irqstat, base, tmp | ||
| 80 | bic \irqnr, \irqstat, #0x1c00 | ||
| 81 | cmp \irqnr, #16 | ||
| 82 | strcc \irqstat, [\base, #GIC_CPU_EOI] | ||
| 83 | cmpcs \irqnr, \irqnr | ||
| 84 | .endm | ||
| 85 | |||
| 86 | /* As above, this assumes that irqstat and base are preserved.. */ | ||
| 87 | |||
| 88 | .macro test_for_ltirq, irqnr, irqstat, base, tmp | ||
| 89 | bic \irqnr, \irqstat, #0x1c00 | ||
| 90 | mov \tmp, #0 | ||
| 91 | cmp \irqnr, #29 | ||
| 92 | moveq \tmp, #1 | ||
| 93 | streq \irqstat, [\base, #GIC_CPU_EOI] | ||
| 94 | cmp \tmp, #0 | ||
| 95 | .endm | ||
| 96 | |||
| 97 | #else | 35 | #else |
| 98 | /* legacy interrupt controller for AP16 */ | 36 | /* legacy interrupt controller for AP16 */ |
| 99 | .macro disable_fiq | 37 | .macro disable_fiq |
diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h index f0981b1ac59e..4cea2230c8dc 100644 --- a/arch/arm/mach-tegra/include/mach/io.h +++ b/arch/arm/mach-tegra/include/mach/io.h | |||
| @@ -65,8 +65,8 @@ | |||
| 65 | 65 | ||
| 66 | #ifndef __ASSEMBLER__ | 66 | #ifndef __ASSEMBLER__ |
| 67 | 67 | ||
| 68 | #define __arch_ioremap(p, s, t) tegra_ioremap(p, s, t) | 68 | #define __arch_ioremap tegra_ioremap |
| 69 | #define __arch_iounmap(v) tegra_iounmap(v) | 69 | #define __arch_iounmap tegra_iounmap |
| 70 | 70 | ||
| 71 | void __iomem *tegra_ioremap(unsigned long phys, size_t size, unsigned int type); | 71 | void __iomem *tegra_ioremap(unsigned long phys, size_t size, unsigned int type); |
| 72 | void tegra_iounmap(volatile void __iomem *addr); | 72 | void tegra_iounmap(volatile void __iomem *addr); |
diff --git a/arch/arm/mach-tegra/include/mach/sdhci.h b/arch/arm/mach-tegra/include/mach/sdhci.h new file mode 100644 index 000000000000..3ad086e859c3 --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/sdhci.h | |||
| @@ -0,0 +1,29 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-tegra/include/mach/sdhci.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Palm, Inc. | ||
| 5 | * Author: Yvonne Yip <y@palm.com> | ||
| 6 | * | ||
| 7 | * This software is licensed under the terms of the GNU General Public | ||
| 8 | * License version 2, as published by the Free Software Foundation, and | ||
| 9 | * may be copied, distributed, and modified under those terms. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | */ | ||
| 17 | #ifndef __ASM_ARM_ARCH_TEGRA_SDHCI_H | ||
| 18 | #define __ASM_ARM_ARCH_TEGRA_SDHCI_H | ||
| 19 | |||
| 20 | #include <linux/mmc/host.h> | ||
| 21 | |||
| 22 | struct tegra_sdhci_platform_data { | ||
| 23 | int cd_gpio; | ||
| 24 | int wp_gpio; | ||
| 25 | int power_gpio; | ||
| 26 | int is_8bit; | ||
| 27 | }; | ||
| 28 | |||
| 29 | #endif | ||
diff --git a/arch/arm/mach-tegra/include/mach/smp.h b/arch/arm/mach-tegra/include/mach/smp.h index e4a34a35a544..c8221b38ee7c 100644 --- a/arch/arm/mach-tegra/include/mach/smp.h +++ b/arch/arm/mach-tegra/include/mach/smp.h | |||
| @@ -2,21 +2,13 @@ | |||
| 2 | #define ASMARM_ARCH_SMP_H | 2 | #define ASMARM_ARCH_SMP_H |
| 3 | 3 | ||
| 4 | #include <asm/hardware/gic.h> | 4 | #include <asm/hardware/gic.h> |
| 5 | #include <asm/smp_mpidr.h> | ||
| 6 | 5 | ||
| 7 | /* | 6 | /* |
| 8 | * We use IRQ1 as the IPI | 7 | * We use IRQ1 as the IPI |
| 9 | */ | 8 | */ |
| 10 | static inline void smp_cross_call(const struct cpumask *mask) | 9 | static inline void smp_cross_call(const struct cpumask *mask, int ipi) |
| 11 | { | ||
| 12 | gic_raise_softirq(mask, 1); | ||
| 13 | } | ||
| 14 | |||
| 15 | /* | ||
| 16 | * Do nothing on MPcore. | ||
| 17 | */ | ||
| 18 | static inline void smp_cross_call_done(cpumask_t callmap) | ||
| 19 | { | 10 | { |
| 11 | gic_raise_softirq(mask, ipi); | ||
| 20 | } | 12 | } |
| 21 | 13 | ||
| 22 | #endif | 14 | #endif |
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index 50a8dfb9a0cf..5407de01abf0 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c | |||
| @@ -94,8 +94,8 @@ void __init tegra_init_irq(void) | |||
| 94 | writel(0, ictlr_to_virt(i) + ICTLR_CPU_IEP_CLASS); | 94 | writel(0, ictlr_to_virt(i) + ICTLR_CPU_IEP_CLASS); |
| 95 | } | 95 | } |
| 96 | 96 | ||
| 97 | gic_dist_init(0, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), 29); | 97 | gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), |
| 98 | gic_cpu_init(0, IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); | 98 | IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); |
| 99 | 99 | ||
| 100 | gic = get_irq_chip(29); | 100 | gic = get_irq_chip(29); |
| 101 | gic_unmask_irq = gic->unmask; | 101 | gic_unmask_irq = gic->unmask; |
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index 1c0fd92cab39..ec1f68924edf 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c | |||
| @@ -22,7 +22,6 @@ | |||
| 22 | #include <asm/cacheflush.h> | 22 | #include <asm/cacheflush.h> |
| 23 | #include <mach/hardware.h> | 23 | #include <mach/hardware.h> |
| 24 | #include <asm/mach-types.h> | 24 | #include <asm/mach-types.h> |
| 25 | #include <asm/localtimer.h> | ||
| 26 | #include <asm/smp_scu.h> | 25 | #include <asm/smp_scu.h> |
| 27 | 26 | ||
| 28 | #include <mach/iomap.h> | 27 | #include <mach/iomap.h> |
| @@ -41,14 +40,12 @@ static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE); | |||
| 41 | 40 | ||
| 42 | void __cpuinit platform_secondary_init(unsigned int cpu) | 41 | void __cpuinit platform_secondary_init(unsigned int cpu) |
| 43 | { | 42 | { |
| 44 | trace_hardirqs_off(); | ||
| 45 | |||
| 46 | /* | 43 | /* |
| 47 | * if any interrupts are already enabled for the primary | 44 | * if any interrupts are already enabled for the primary |
| 48 | * core (e.g. timer irq), then they will not have been enabled | 45 | * core (e.g. timer irq), then they will not have been enabled |
| 49 | * for us: do so | 46 | * for us: do so |
| 50 | */ | 47 | */ |
| 51 | gic_cpu_init(0, IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x100); | 48 | gic_secondary_init(0); |
| 52 | 49 | ||
| 53 | /* | 50 | /* |
| 54 | * Synchronise with the boot thread. | 51 | * Synchronise with the boot thread. |
| @@ -117,24 +114,20 @@ void __init smp_init_cpus(void) | |||
| 117 | { | 114 | { |
| 118 | unsigned int i, ncores = scu_get_core_count(scu_base); | 115 | unsigned int i, ncores = scu_get_core_count(scu_base); |
| 119 | 116 | ||
| 117 | if (ncores > NR_CPUS) { | ||
| 118 | printk(KERN_ERR "Tegra: no. of cores (%u) greater than configured (%u), clipping\n", | ||
| 119 | ncores, NR_CPUS); | ||
| 120 | ncores = NR_CPUS; | ||
| 121 | } | ||
| 122 | |||
| 120 | for (i = 0; i < ncores; i++) | 123 | for (i = 0; i < ncores; i++) |
| 121 | cpu_set(i, cpu_possible_map); | 124 | cpu_set(i, cpu_possible_map); |
| 122 | } | 125 | } |
| 123 | 126 | ||
| 124 | void __init smp_prepare_cpus(unsigned int max_cpus) | 127 | void __init platform_smp_prepare_cpus(unsigned int max_cpus) |
| 125 | { | 128 | { |
| 126 | unsigned int ncores = scu_get_core_count(scu_base); | ||
| 127 | unsigned int cpu = smp_processor_id(); | ||
| 128 | int i; | 129 | int i; |
| 129 | 130 | ||
| 130 | smp_store_cpu_info(cpu); | ||
| 131 | |||
| 132 | /* | ||
| 133 | * are we trying to boot more cores than exist? | ||
| 134 | */ | ||
| 135 | if (max_cpus > ncores) | ||
| 136 | max_cpus = ncores; | ||
| 137 | |||
| 138 | /* | 131 | /* |
| 139 | * Initialise the present map, which describes the set of CPUs | 132 | * Initialise the present map, which describes the set of CPUs |
| 140 | * actually populated at the present time. | 133 | * actually populated at the present time. |
| @@ -142,15 +135,5 @@ void __init smp_prepare_cpus(unsigned int max_cpus) | |||
| 142 | for (i = 0; i < max_cpus; i++) | 135 | for (i = 0; i < max_cpus; i++) |
| 143 | set_cpu_present(i, true); | 136 | set_cpu_present(i, true); |
| 144 | 137 | ||
| 145 | /* | 138 | scu_enable(scu_base); |
| 146 | * Initialise the SCU if there are more than one CPU and let | ||
| 147 | * them know where to start. Note that, on modern versions of | ||
| 148 | * MILO, the "poke" doesn't actually do anything until each | ||
| 149 | * individual core is sent a soft interrupt to get it out of | ||
| 150 | * WFI | ||
| 151 | */ | ||
| 152 | if (max_cpus > 1) { | ||
| 153 | percpu_timer_setup(); | ||
| 154 | scu_enable(scu_base); | ||
| 155 | } | ||
| 156 | } | 139 | } |
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index ae3b308e22a4..f0dae6d8ba52 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c | |||
| @@ -24,8 +24,7 @@ | |||
| 24 | #include <linux/delay.h> | 24 | #include <linux/delay.h> |
| 25 | #include <linux/io.h> | 25 | #include <linux/io.h> |
| 26 | #include <linux/hrtimer.h> | 26 | #include <linux/hrtimer.h> |
| 27 | 27 | #include <linux/clkdev.h> | |
| 28 | #include <asm/clkdev.h> | ||
| 29 | 28 | ||
| 30 | #include <mach/iomap.h> | 29 | #include <mach/iomap.h> |
| 31 | 30 | ||
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c index 9057d6fd1d31..7b8ad1f98f44 100644 --- a/arch/arm/mach-tegra/timer.c +++ b/arch/arm/mach-tegra/timer.c | |||
| @@ -18,6 +18,7 @@ | |||
| 18 | */ | 18 | */ |
| 19 | 19 | ||
| 20 | #include <linux/init.h> | 20 | #include <linux/init.h> |
| 21 | #include <linux/sched.h> | ||
| 21 | #include <linux/time.h> | 22 | #include <linux/time.h> |
| 22 | #include <linux/interrupt.h> | 23 | #include <linux/interrupt.h> |
| 23 | #include <linux/irq.h> | 24 | #include <linux/irq.h> |
| @@ -25,10 +26,10 @@ | |||
| 25 | #include <linux/clocksource.h> | 26 | #include <linux/clocksource.h> |
| 26 | #include <linux/clk.h> | 27 | #include <linux/clk.h> |
| 27 | #include <linux/io.h> | 28 | #include <linux/io.h> |
| 28 | #include <linux/cnt32_to_63.h> | ||
| 29 | 29 | ||
| 30 | #include <asm/mach/time.h> | 30 | #include <asm/mach/time.h> |
| 31 | #include <asm/localtimer.h> | 31 | #include <asm/localtimer.h> |
| 32 | #include <asm/sched_clock.h> | ||
| 32 | 33 | ||
| 33 | #include <mach/iomap.h> | 34 | #include <mach/iomap.h> |
| 34 | #include <mach/irqs.h> | 35 | #include <mach/irqs.h> |
| @@ -91,7 +92,7 @@ static void tegra_timer_set_mode(enum clock_event_mode mode, | |||
| 91 | 92 | ||
| 92 | static cycle_t tegra_clocksource_read(struct clocksource *cs) | 93 | static cycle_t tegra_clocksource_read(struct clocksource *cs) |
| 93 | { | 94 | { |
| 94 | return cnt32_to_63(timer_readl(TIMERUS_CNTR_1US)); | 95 | return timer_readl(TIMERUS_CNTR_1US); |
| 95 | } | 96 | } |
| 96 | 97 | ||
| 97 | static struct clock_event_device tegra_clockevent = { | 98 | static struct clock_event_device tegra_clockevent = { |
| @@ -106,14 +107,29 @@ static struct clocksource tegra_clocksource = { | |||
| 106 | .name = "timer_us", | 107 | .name = "timer_us", |
| 107 | .rating = 300, | 108 | .rating = 300, |
| 108 | .read = tegra_clocksource_read, | 109 | .read = tegra_clocksource_read, |
| 109 | .mask = 0x7FFFFFFFFFFFFFFFULL, | 110 | .mask = CLOCKSOURCE_MASK(32), |
| 110 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 111 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 111 | }; | 112 | }; |
| 112 | 113 | ||
| 113 | unsigned long long sched_clock(void) | 114 | static DEFINE_CLOCK_DATA(cd); |
| 115 | |||
| 116 | /* | ||
| 117 | * Constants generated by clocks_calc_mult_shift(m, s, 1MHz, NSEC_PER_SEC, 60). | ||
| 118 | * This gives a resolution of about 1us and a wrap period of about 1h11min. | ||
| 119 | */ | ||
| 120 | #define SC_MULT 4194304000u | ||
| 121 | #define SC_SHIFT 22 | ||
| 122 | |||
| 123 | unsigned long long notrace sched_clock(void) | ||
| 114 | { | 124 | { |
| 115 | return clocksource_cyc2ns(tegra_clocksource.read(&tegra_clocksource), | 125 | u32 cyc = timer_readl(TIMERUS_CNTR_1US); |
| 116 | tegra_clocksource.mult, tegra_clocksource.shift); | 126 | return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT); |
| 127 | } | ||
| 128 | |||
| 129 | static void notrace tegra_update_sched_clock(void) | ||
| 130 | { | ||
| 131 | u32 cyc = timer_readl(TIMERUS_CNTR_1US); | ||
| 132 | update_sched_clock(&cd, cyc, (u32)~0); | ||
| 117 | } | 133 | } |
| 118 | 134 | ||
| 119 | static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id) | 135 | static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id) |
| @@ -158,6 +174,9 @@ static void __init tegra_init_timer(void) | |||
| 158 | WARN(1, "Unknown clock rate"); | 174 | WARN(1, "Unknown clock rate"); |
| 159 | } | 175 | } |
| 160 | 176 | ||
| 177 | init_fixed_sched_clock(&cd, tegra_update_sched_clock, 32, | ||
| 178 | 1000000, SC_MULT, SC_SHIFT); | ||
| 179 | |||
| 161 | if (clocksource_register_hz(&tegra_clocksource, 1000000)) { | 180 | if (clocksource_register_hz(&tegra_clocksource, 1000000)) { |
| 162 | printk(KERN_ERR "Failed to register clocksource\n"); | 181 | printk(KERN_ERR "Failed to register clocksource\n"); |
| 163 | BUG(); | 182 | BUG(); |
diff --git a/arch/arm/mach-u300/clock.c b/arch/arm/mach-u300/clock.c index 7458fc6df5c6..fabcc49abe80 100644 --- a/arch/arm/mach-u300/clock.c +++ b/arch/arm/mach-u300/clock.c | |||
| @@ -25,8 +25,8 @@ | |||
| 25 | #include <linux/timer.h> | 25 | #include <linux/timer.h> |
| 26 | #include <linux/io.h> | 26 | #include <linux/io.h> |
| 27 | #include <linux/seq_file.h> | 27 | #include <linux/seq_file.h> |
| 28 | #include <linux/clkdev.h> | ||
| 28 | 29 | ||
| 29 | #include <asm/clkdev.h> | ||
| 30 | #include <mach/hardware.h> | 30 | #include <mach/hardware.h> |
| 31 | #include <mach/syscon.h> | 31 | #include <mach/syscon.h> |
| 32 | 32 | ||
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c index 3fc4472719be..3ec58bd2d6e4 100644 --- a/arch/arm/mach-u300/timer.c +++ b/arch/arm/mach-u300/timer.c | |||
| @@ -9,6 +9,7 @@ | |||
| 9 | * Author: Linus Walleij <linus.walleij@stericsson.com> | 9 | * Author: Linus Walleij <linus.walleij@stericsson.com> |
| 10 | */ | 10 | */ |
| 11 | #include <linux/interrupt.h> | 11 | #include <linux/interrupt.h> |
| 12 | #include <linux/sched.h> | ||
| 12 | #include <linux/time.h> | 13 | #include <linux/time.h> |
| 13 | #include <linux/timex.h> | 14 | #include <linux/timex.h> |
| 14 | #include <linux/clockchips.h> | 15 | #include <linux/clockchips.h> |
| @@ -21,6 +22,7 @@ | |||
| 21 | #include <mach/hardware.h> | 22 | #include <mach/hardware.h> |
| 22 | 23 | ||
| 23 | /* Generic stuff */ | 24 | /* Generic stuff */ |
| 25 | #include <asm/sched_clock.h> | ||
| 24 | #include <asm/mach/map.h> | 26 | #include <asm/mach/map.h> |
| 25 | #include <asm/mach/time.h> | 27 | #include <asm/mach/time.h> |
| 26 | #include <asm/mach/irq.h> | 28 | #include <asm/mach/irq.h> |
| @@ -352,12 +354,18 @@ static struct clocksource clocksource_u300_1mhz = { | |||
| 352 | * this wraps around for now, since it is just a relative time | 354 | * this wraps around for now, since it is just a relative time |
| 353 | * stamp. (Inspired by OMAP implementation.) | 355 | * stamp. (Inspired by OMAP implementation.) |
| 354 | */ | 356 | */ |
| 357 | static DEFINE_CLOCK_DATA(cd); | ||
| 358 | |||
| 355 | unsigned long long notrace sched_clock(void) | 359 | unsigned long long notrace sched_clock(void) |
| 356 | { | 360 | { |
| 357 | return clocksource_cyc2ns(clocksource_u300_1mhz.read( | 361 | u32 cyc = readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC); |
| 358 | &clocksource_u300_1mhz), | 362 | return cyc_to_sched_clock(&cd, cyc, (u32)~0); |
| 359 | clocksource_u300_1mhz.mult, | 363 | } |
| 360 | clocksource_u300_1mhz.shift); | 364 | |
| 365 | static void notrace u300_update_sched_clock(void) | ||
| 366 | { | ||
| 367 | u32 cyc = readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC); | ||
| 368 | update_sched_clock(&cd, cyc, (u32)~0); | ||
| 361 | } | 369 | } |
| 362 | 370 | ||
| 363 | 371 | ||
| @@ -375,6 +383,8 @@ static void __init u300_timer_init(void) | |||
| 375 | clk_enable(clk); | 383 | clk_enable(clk); |
| 376 | rate = clk_get_rate(clk); | 384 | rate = clk_get_rate(clk); |
| 377 | 385 | ||
| 386 | init_sched_clock(&cd, u300_update_sched_clock, 32, rate); | ||
| 387 | |||
| 378 | /* | 388 | /* |
| 379 | * Disable the "OS" and "DD" timers - these are designed for Symbian! | 389 | * Disable the "OS" and "DD" timers - these are designed for Symbian! |
| 380 | * Example usage in cnh1601578 cpu subsystem pd_timer_app.c | 390 | * Example usage in cnh1601578 cpu subsystem pd_timer_app.c |
| @@ -412,9 +422,7 @@ static void __init u300_timer_init(void) | |||
| 412 | writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE, | 422 | writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE, |
| 413 | U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2); | 423 | U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2); |
| 414 | 424 | ||
| 415 | clocksource_calc_mult_shift(&clocksource_u300_1mhz, | 425 | if (clocksource_register_hz(&clocksource_u300_1mhz, rate)) |
| 416 | rate, APPTIMER_MIN_RANGE); | ||
| 417 | if (clocksource_register(&clocksource_u300_1mhz)) | ||
| 418 | printk(KERN_ERR "timer: failed to initialize clock " | 426 | printk(KERN_ERR "timer: failed to initialize clock " |
| 419 | "source %s\n", clocksource_u300_1mhz.name); | 427 | "source %s\n", clocksource_u300_1mhz.name); |
| 420 | 428 | ||
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index 2dd44a0b4615..247caa3400d0 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig | |||
| @@ -7,28 +7,30 @@ config UX500_SOC_COMMON | |||
| 7 | select HAS_MTU | 7 | select HAS_MTU |
| 8 | select NOMADIK_GPIO | 8 | select NOMADIK_GPIO |
| 9 | 9 | ||
| 10 | config UX500_SOC_DB8500 | 10 | menu "Ux500 SoC" |
| 11 | bool | ||
| 12 | 11 | ||
| 13 | config UX500_SOC_DB5500 | 12 | config UX500_SOC_DB5500 |
| 14 | bool | 13 | bool "DB5500" |
| 14 | |||
| 15 | config UX500_SOC_DB8500 | ||
| 16 | bool "DB8500" | ||
| 17 | |||
| 18 | endmenu | ||
| 15 | 19 | ||
| 16 | choice | 20 | menu "Ux500 target platform" |
| 17 | prompt "Ux500 target platform" | ||
| 18 | default MACH_U8500_MOP | ||
| 19 | 21 | ||
| 20 | config MACH_U8500_MOP | 22 | config MACH_U8500 |
| 21 | bool "U8500 Development platform" | 23 | bool "U8500 Development platform" |
| 22 | select UX500_SOC_DB8500 | 24 | depends on UX500_SOC_DB8500 |
| 23 | help | 25 | help |
| 24 | Include support for the mop500 development platform. | 26 | Include support for the mop500 development platform. |
| 25 | 27 | ||
| 26 | config MACH_U5500 | 28 | config MACH_U5500 |
| 27 | bool "U5500 Development platform" | 29 | bool "U5500 Development platform" |
| 28 | select UX500_SOC_DB5500 | 30 | depends on UX500_SOC_DB5500 |
| 29 | help | 31 | help |
| 30 | Include support for the U5500 development platform. | 32 | Include support for the U5500 development platform. |
| 31 | endchoice | 33 | endmenu |
| 32 | 34 | ||
| 33 | config UX500_DEBUG_UART | 35 | config UX500_DEBUG_UART |
| 34 | int "Ux500 UART to use for low-level debug" | 36 | int "Ux500 UART to use for low-level debug" |
| @@ -39,14 +41,14 @@ config UX500_DEBUG_UART | |||
| 39 | 41 | ||
| 40 | config U5500_MODEM_IRQ | 42 | config U5500_MODEM_IRQ |
| 41 | bool "Modem IRQ support" | 43 | bool "Modem IRQ support" |
| 42 | depends on MACH_U5500 | 44 | depends on UX500_SOC_DB5500 |
| 43 | default y | 45 | default y |
| 44 | help | 46 | help |
| 45 | Add support for handling IRQ:s from modem side | 47 | Add support for handling IRQ:s from modem side |
| 46 | 48 | ||
| 47 | config U5500_MBOX | 49 | config U5500_MBOX |
| 48 | bool "Mailbox support" | 50 | bool "Mailbox support" |
| 49 | depends on MACH_U5500 && U5500_MODEM_IRQ | 51 | depends on U5500_MODEM_IRQ |
| 50 | default y | 52 | default y |
| 51 | help | 53 | help |
| 52 | Add support for U5500 mailbox communication with modem side | 54 | Add support for U5500 mailbox communication with modem side |
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile index 9e27a84433cb..53ebb429e971 100644 --- a/arch/arm/mach-ux500/Makefile +++ b/arch/arm/mach-ux500/Makefile | |||
| @@ -2,14 +2,17 @@ | |||
| 2 | # Makefile for the linux kernel, U8500 machine. | 2 | # Makefile for the linux kernel, U8500 machine. |
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | obj-y := clock.o cpu.o devices.o | 5 | obj-y := clock.o cpu.o devices.o devices-common.o \ |
| 6 | obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o devices-db5500.o | 6 | id.o |
| 7 | obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o dma-db5500.o | ||
| 7 | obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o prcmu.o | 8 | obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o prcmu.o |
| 8 | obj-$(CONFIG_MACH_U8500_MOP) += board-mop500.o board-mop500-sdi.o | 9 | obj-$(CONFIG_MACH_U8500) += board-mop500.o board-mop500-sdi.o \ |
| 9 | obj-$(CONFIG_MACH_U5500) += board-u5500.o | 10 | board-mop500-keypads.o |
| 11 | obj-$(CONFIG_MACH_U5500) += board-u5500.o board-u5500-sdi.o | ||
| 10 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o | 12 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o |
| 11 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o | 13 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o |
| 12 | obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o | 14 | obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o |
| 13 | obj-$(CONFIG_REGULATOR_AB8500) += board-mop500-regulators.o | 15 | obj-$(CONFIG_REGULATOR_AB8500) += board-mop500-regulators.o |
| 14 | obj-$(CONFIG_U5500_MODEM_IRQ) += modem_irq.o | 16 | obj-$(CONFIG_U5500_MODEM_IRQ) += modem-irq-db5500.o |
| 15 | obj-$(CONFIG_U5500_MBOX) += mbox.o | 17 | obj-$(CONFIG_U5500_MBOX) += mbox-db5500.o |
| 18 | obj-$(CONFIG_CPU_FREQ) += cpufreq.o | ||
diff --git a/arch/arm/mach-ux500/board-mop500-keypads.c b/arch/arm/mach-ux500/board-mop500-keypads.c new file mode 100644 index 000000000000..70318c354d32 --- /dev/null +++ b/arch/arm/mach-ux500/board-mop500-keypads.c | |||
| @@ -0,0 +1,229 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) ST-Ericsson SA 2010 | ||
| 3 | * | ||
| 4 | * License Terms: GNU General Public License v2 | ||
| 5 | * | ||
| 6 | * Keypad layouts for various boards | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <linux/i2c.h> | ||
| 10 | #include <linux/gpio.h> | ||
| 11 | #include <linux/interrupt.h> | ||
| 12 | #include <linux/platform_device.h> | ||
| 13 | #include <linux/mfd/stmpe.h> | ||
| 14 | #include <linux/mfd/tc3589x.h> | ||
| 15 | #include <linux/input/matrix_keypad.h> | ||
| 16 | |||
| 17 | #include <plat/pincfg.h> | ||
| 18 | #include <plat/ske.h> | ||
| 19 | |||
| 20 | #include <mach/devices.h> | ||
| 21 | #include <mach/hardware.h> | ||
| 22 | |||
| 23 | #include "devices-db8500.h" | ||
| 24 | #include "board-mop500.h" | ||
| 25 | |||
| 26 | /* STMPE/SKE keypad use this key layout */ | ||
| 27 | static const unsigned int mop500_keymap[] = { | ||
| 28 | KEY(2, 5, KEY_END), | ||
| 29 | KEY(4, 1, KEY_POWER), | ||
| 30 | KEY(3, 5, KEY_VOLUMEDOWN), | ||
| 31 | KEY(1, 3, KEY_3), | ||
| 32 | KEY(5, 2, KEY_RIGHT), | ||
| 33 | KEY(5, 0, KEY_9), | ||
| 34 | |||
| 35 | KEY(0, 5, KEY_MENU), | ||
| 36 | KEY(7, 6, KEY_ENTER), | ||
| 37 | KEY(4, 5, KEY_0), | ||
| 38 | KEY(6, 7, KEY_2), | ||
| 39 | KEY(3, 4, KEY_UP), | ||
| 40 | KEY(3, 3, KEY_DOWN), | ||
| 41 | |||
| 42 | KEY(6, 4, KEY_SEND), | ||
| 43 | KEY(6, 2, KEY_BACK), | ||
| 44 | KEY(4, 2, KEY_VOLUMEUP), | ||
| 45 | KEY(5, 5, KEY_1), | ||
| 46 | KEY(4, 3, KEY_LEFT), | ||
| 47 | KEY(3, 2, KEY_7), | ||
| 48 | }; | ||
| 49 | |||
| 50 | static const struct matrix_keymap_data mop500_keymap_data = { | ||
| 51 | .keymap = mop500_keymap, | ||
| 52 | .keymap_size = ARRAY_SIZE(mop500_keymap), | ||
| 53 | }; | ||
| 54 | |||
| 55 | /* | ||
| 56 | * Nomadik SKE keypad | ||
| 57 | */ | ||
| 58 | #define ROW_PIN_I0 164 | ||
| 59 | #define ROW_PIN_I1 163 | ||
| 60 | #define ROW_PIN_I2 162 | ||
| 61 | #define ROW_PIN_I3 161 | ||
| 62 | #define ROW_PIN_I4 156 | ||
| 63 | #define ROW_PIN_I5 155 | ||
| 64 | #define ROW_PIN_I6 154 | ||
| 65 | #define ROW_PIN_I7 153 | ||
| 66 | #define COL_PIN_O0 168 | ||
| 67 | #define COL_PIN_O1 167 | ||
| 68 | #define COL_PIN_O2 166 | ||
| 69 | #define COL_PIN_O3 165 | ||
| 70 | #define COL_PIN_O4 160 | ||
| 71 | #define COL_PIN_O5 159 | ||
| 72 | #define COL_PIN_O6 158 | ||
| 73 | #define COL_PIN_O7 157 | ||
| 74 | |||
| 75 | #define SKE_KPD_MAX_ROWS 8 | ||
| 76 | #define SKE_KPD_MAX_COLS 8 | ||
| 77 | |||
| 78 | static int ske_kp_rows[] = { | ||
| 79 | ROW_PIN_I0, ROW_PIN_I1, ROW_PIN_I2, ROW_PIN_I3, | ||
| 80 | ROW_PIN_I4, ROW_PIN_I5, ROW_PIN_I6, ROW_PIN_I7, | ||
| 81 | }; | ||
| 82 | |||
| 83 | /* | ||
| 84 | * ske_set_gpio_row: request and set gpio rows | ||
| 85 | */ | ||
| 86 | static int ske_set_gpio_row(int gpio) | ||
| 87 | { | ||
| 88 | int ret; | ||
| 89 | |||
| 90 | ret = gpio_request(gpio, "ske-kp"); | ||
| 91 | if (ret < 0) { | ||
| 92 | pr_err("ske_set_gpio_row: gpio request failed\n"); | ||
| 93 | return ret; | ||
| 94 | } | ||
| 95 | |||
| 96 | ret = gpio_direction_output(gpio, 1); | ||
| 97 | if (ret < 0) { | ||
| 98 | pr_err("ske_set_gpio_row: gpio direction failed\n"); | ||
| 99 | gpio_free(gpio); | ||
| 100 | } | ||
| 101 | |||
| 102 | return ret; | ||
| 103 | } | ||
| 104 | |||
| 105 | /* | ||
| 106 | * ske_kp_init - enable the gpio configuration | ||
| 107 | */ | ||
| 108 | static int ske_kp_init(void) | ||
| 109 | { | ||
| 110 | int ret, i; | ||
| 111 | |||
| 112 | for (i = 0; i < SKE_KPD_MAX_ROWS; i++) { | ||
| 113 | ret = ske_set_gpio_row(ske_kp_rows[i]); | ||
| 114 | if (ret < 0) { | ||
| 115 | pr_err("ske_kp_init: failed init\n"); | ||
| 116 | return ret; | ||
| 117 | } | ||
| 118 | } | ||
| 119 | |||
| 120 | return 0; | ||
| 121 | } | ||
| 122 | |||
| 123 | static struct ske_keypad_platform_data ske_keypad_board = { | ||
| 124 | .init = ske_kp_init, | ||
| 125 | .keymap_data = &mop500_keymap_data, | ||
| 126 | .no_autorepeat = true, | ||
| 127 | .krow = SKE_KPD_MAX_ROWS, /* 8x8 matrix */ | ||
| 128 | .kcol = SKE_KPD_MAX_COLS, | ||
| 129 | .debounce_ms = 40, /* in millisecs */ | ||
| 130 | }; | ||
| 131 | |||
| 132 | /* | ||
| 133 | * STMPE1601 | ||
| 134 | */ | ||
| 135 | static struct stmpe_keypad_platform_data stmpe1601_keypad_data = { | ||
| 136 | .debounce_ms = 64, | ||
| 137 | .scan_count = 8, | ||
| 138 | .no_autorepeat = true, | ||
| 139 | .keymap_data = &mop500_keymap_data, | ||
| 140 | }; | ||
| 141 | |||
| 142 | static struct stmpe_platform_data stmpe1601_data = { | ||
| 143 | .id = 1, | ||
| 144 | .blocks = STMPE_BLOCK_KEYPAD, | ||
| 145 | .irq_trigger = IRQF_TRIGGER_FALLING, | ||
| 146 | .irq_base = MOP500_STMPE1601_IRQ(0), | ||
| 147 | .keypad = &stmpe1601_keypad_data, | ||
| 148 | .autosleep = true, | ||
| 149 | .autosleep_timeout = 1024, | ||
| 150 | }; | ||
| 151 | |||
| 152 | static struct i2c_board_info mop500_i2c0_devices_stuib[] = { | ||
| 153 | { | ||
| 154 | I2C_BOARD_INFO("stmpe1601", 0x40), | ||
| 155 | .irq = NOMADIK_GPIO_TO_IRQ(218), | ||
| 156 | .platform_data = &stmpe1601_data, | ||
| 157 | .flags = I2C_CLIENT_WAKE, | ||
| 158 | }, | ||
| 159 | }; | ||
| 160 | |||
| 161 | /* | ||
| 162 | * TC35893 | ||
| 163 | */ | ||
| 164 | |||
| 165 | static const unsigned int uib_keymap[] = { | ||
| 166 | KEY(3, 1, KEY_END), | ||
| 167 | KEY(4, 1, KEY_POWER), | ||
| 168 | KEY(6, 4, KEY_VOLUMEDOWN), | ||
| 169 | KEY(4, 2, KEY_EMAIL), | ||
| 170 | KEY(3, 3, KEY_RIGHT), | ||
| 171 | KEY(2, 5, KEY_BACKSPACE), | ||
| 172 | |||
| 173 | KEY(6, 7, KEY_MENU), | ||
| 174 | KEY(5, 0, KEY_ENTER), | ||
| 175 | KEY(4, 3, KEY_0), | ||
| 176 | KEY(3, 4, KEY_DOT), | ||
| 177 | KEY(5, 2, KEY_UP), | ||
| 178 | KEY(3, 5, KEY_DOWN), | ||
| 179 | |||
| 180 | KEY(4, 5, KEY_SEND), | ||
| 181 | KEY(0, 5, KEY_BACK), | ||
| 182 | KEY(6, 2, KEY_VOLUMEUP), | ||
| 183 | KEY(1, 3, KEY_SPACE), | ||
| 184 | KEY(7, 6, KEY_LEFT), | ||
| 185 | KEY(5, 5, KEY_SEARCH), | ||
| 186 | }; | ||
| 187 | |||
| 188 | static struct matrix_keymap_data uib_keymap_data = { | ||
| 189 | .keymap = uib_keymap, | ||
| 190 | .keymap_size = ARRAY_SIZE(uib_keymap), | ||
| 191 | }; | ||
| 192 | |||
| 193 | static struct tc3589x_keypad_platform_data tc35893_data = { | ||
| 194 | .krow = TC_KPD_ROWS, | ||
| 195 | .kcol = TC_KPD_COLUMNS, | ||
| 196 | .debounce_period = TC_KPD_DEBOUNCE_PERIOD, | ||
| 197 | .settle_time = TC_KPD_SETTLE_TIME, | ||
| 198 | .irqtype = IRQF_TRIGGER_FALLING, | ||
| 199 | .enable_wakeup = true, | ||
| 200 | .keymap_data = &uib_keymap_data, | ||
| 201 | .no_autorepeat = true, | ||
| 202 | }; | ||
| 203 | |||
| 204 | static struct tc3589x_platform_data tc3589x_keypad_data = { | ||
| 205 | .block = TC3589x_BLOCK_KEYPAD, | ||
| 206 | .keypad = &tc35893_data, | ||
| 207 | .irq_base = MOP500_EGPIO_IRQ_BASE, | ||
| 208 | }; | ||
| 209 | |||
| 210 | static struct i2c_board_info mop500_i2c0_devices_uib[] = { | ||
| 211 | { | ||
| 212 | I2C_BOARD_INFO("tc3589x", 0x44), | ||
| 213 | .platform_data = &tc3589x_keypad_data, | ||
| 214 | .irq = NOMADIK_GPIO_TO_IRQ(218), | ||
| 215 | .flags = I2C_CLIENT_WAKE, | ||
| 216 | }, | ||
| 217 | }; | ||
| 218 | |||
| 219 | void mop500_keypad_init(void) | ||
| 220 | { | ||
| 221 | db8500_add_ske_keypad(&ske_keypad_board); | ||
| 222 | |||
| 223 | i2c_register_board_info(0, mop500_i2c0_devices_stuib, | ||
| 224 | ARRAY_SIZE(mop500_i2c0_devices_stuib)); | ||
| 225 | |||
| 226 | i2c_register_board_info(0, mop500_i2c0_devices_uib, | ||
| 227 | ARRAY_SIZE(mop500_i2c0_devices_uib)); | ||
| 228 | |||
| 229 | } | ||
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c index bac995665b58..4b996676594e 100644 --- a/arch/arm/mach-ux500/board-mop500-sdi.c +++ b/arch/arm/mach-ux500/board-mop500-sdi.c | |||
| @@ -16,10 +16,24 @@ | |||
| 16 | #include <mach/devices.h> | 16 | #include <mach/devices.h> |
| 17 | #include <mach/hardware.h> | 17 | #include <mach/hardware.h> |
| 18 | 18 | ||
| 19 | #include "devices-db8500.h" | ||
| 19 | #include "pins-db8500.h" | 20 | #include "pins-db8500.h" |
| 20 | #include "board-mop500.h" | 21 | #include "board-mop500.h" |
| 21 | 22 | ||
| 22 | static pin_cfg_t mop500_sdi_pins[] = { | 23 | static pin_cfg_t mop500_sdi_pins[] = { |
| 24 | /* SDI0 (MicroSD slot) */ | ||
| 25 | GPIO18_MC0_CMDDIR, | ||
| 26 | GPIO19_MC0_DAT0DIR, | ||
| 27 | GPIO20_MC0_DAT2DIR, | ||
| 28 | GPIO21_MC0_DAT31DIR, | ||
| 29 | GPIO22_MC0_FBCLK, | ||
| 30 | GPIO23_MC0_CLK, | ||
| 31 | GPIO24_MC0_CMD, | ||
| 32 | GPIO25_MC0_DAT0, | ||
| 33 | GPIO26_MC0_DAT1, | ||
| 34 | GPIO27_MC0_DAT2, | ||
| 35 | GPIO28_MC0_DAT3, | ||
| 36 | |||
| 23 | /* SDI4 (on-board eMMC) */ | 37 | /* SDI4 (on-board eMMC) */ |
| 24 | GPIO197_MC4_DAT3, | 38 | GPIO197_MC4_DAT3, |
| 25 | GPIO198_MC4_DAT2, | 39 | GPIO198_MC4_DAT2, |
| @@ -50,6 +64,55 @@ static pin_cfg_t mop500_sdi2_pins[] = { | |||
| 50 | }; | 64 | }; |
| 51 | 65 | ||
| 52 | /* | 66 | /* |
| 67 | * SDI 0 (MicroSD slot) | ||
| 68 | */ | ||
| 69 | |||
| 70 | /* MMCIPOWER bits */ | ||
| 71 | #define MCI_DATA2DIREN (1 << 2) | ||
| 72 | #define MCI_CMDDIREN (1 << 3) | ||
| 73 | #define MCI_DATA0DIREN (1 << 4) | ||
| 74 | #define MCI_DATA31DIREN (1 << 5) | ||
| 75 | #define MCI_FBCLKEN (1 << 7) | ||
| 76 | |||
| 77 | static u32 mop500_sdi0_vdd_handler(struct device *dev, unsigned int vdd, | ||
| 78 | unsigned char power_mode) | ||
| 79 | { | ||
| 80 | if (power_mode == MMC_POWER_UP) | ||
| 81 | gpio_set_value_cansleep(GPIO_SDMMC_EN, 1); | ||
| 82 | else if (power_mode == MMC_POWER_OFF) | ||
| 83 | gpio_set_value_cansleep(GPIO_SDMMC_EN, 0); | ||
| 84 | |||
| 85 | return MCI_FBCLKEN | MCI_CMDDIREN | MCI_DATA0DIREN | | ||
| 86 | MCI_DATA2DIREN | MCI_DATA31DIREN; | ||
| 87 | } | ||
| 88 | |||
| 89 | static struct mmci_platform_data mop500_sdi0_data = { | ||
| 90 | .vdd_handler = mop500_sdi0_vdd_handler, | ||
| 91 | .ocr_mask = MMC_VDD_29_30, | ||
| 92 | .f_max = 100000000, | ||
| 93 | .capabilities = MMC_CAP_4_BIT_DATA, | ||
| 94 | .gpio_cd = GPIO_SDMMC_CD, | ||
| 95 | .gpio_wp = -1, | ||
| 96 | }; | ||
| 97 | |||
| 98 | void mop500_sdi_tc35892_init(void) | ||
| 99 | { | ||
| 100 | int ret; | ||
| 101 | |||
| 102 | ret = gpio_request(GPIO_SDMMC_EN, "SDMMC_EN"); | ||
| 103 | if (!ret) | ||
| 104 | ret = gpio_request(GPIO_SDMMC_1V8_3V_SEL, | ||
| 105 | "GPIO_SDMMC_1V8_3V_SEL"); | ||
| 106 | if (ret) | ||
| 107 | return; | ||
| 108 | |||
| 109 | gpio_direction_output(GPIO_SDMMC_1V8_3V_SEL, 1); | ||
| 110 | gpio_direction_output(GPIO_SDMMC_EN, 0); | ||
| 111 | |||
| 112 | db8500_add_sdi0(&mop500_sdi0_data); | ||
| 113 | } | ||
| 114 | |||
| 115 | /* | ||
| 53 | * SDI 2 (POP eMMC, not on DB8500ed) | 116 | * SDI 2 (POP eMMC, not on DB8500ed) |
| 54 | */ | 117 | */ |
| 55 | 118 | ||
| @@ -74,18 +137,24 @@ static struct mmci_platform_data mop500_sdi4_data = { | |||
| 74 | .gpio_wp = -1, | 137 | .gpio_wp = -1, |
| 75 | }; | 138 | }; |
| 76 | 139 | ||
| 77 | void mop500_sdi_init(void) | 140 | void __init mop500_sdi_init(void) |
| 78 | { | 141 | { |
| 79 | nmk_config_pins(mop500_sdi_pins, ARRAY_SIZE(mop500_sdi_pins)); | 142 | nmk_config_pins(mop500_sdi_pins, ARRAY_SIZE(mop500_sdi_pins)); |
| 80 | 143 | ||
| 81 | u8500_sdi2_device.dev.platform_data = &mop500_sdi2_data; | 144 | /* |
| 82 | u8500_sdi4_device.dev.platform_data = &mop500_sdi4_data; | 145 | * sdi0 will finally be added when the TC35892 initializes and calls |
| 146 | * mop500_sdi_tc35892_init() above. | ||
| 147 | */ | ||
| 83 | 148 | ||
| 149 | /* PoP:ed eMMC */ | ||
| 84 | if (!cpu_is_u8500ed()) { | 150 | if (!cpu_is_u8500ed()) { |
| 85 | nmk_config_pins(mop500_sdi2_pins, ARRAY_SIZE(mop500_sdi2_pins)); | 151 | nmk_config_pins(mop500_sdi2_pins, ARRAY_SIZE(mop500_sdi2_pins)); |
| 86 | amba_device_register(&u8500_sdi2_device, &iomem_resource); | 152 | /* POP eMMC on v1.0 has problems with high speed */ |
| 153 | if (!cpu_is_u8500v10()) | ||
| 154 | mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED; | ||
| 155 | db8500_add_sdi2(&mop500_sdi2_data); | ||
| 87 | } | 156 | } |
| 88 | 157 | ||
| 89 | /* On-board eMMC */ | 158 | /* On-board eMMC */ |
| 90 | amba_device_register(&u8500_sdi4_device, &iomem_resource); | 159 | db8500_add_sdi4(&mop500_sdi4_data); |
| 91 | } | 160 | } |
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index cac83a694880..a1c9ea1a66df 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c | |||
| @@ -13,25 +13,26 @@ | |||
| 13 | #include <linux/interrupt.h> | 13 | #include <linux/interrupt.h> |
| 14 | #include <linux/platform_device.h> | 14 | #include <linux/platform_device.h> |
| 15 | #include <linux/io.h> | 15 | #include <linux/io.h> |
| 16 | #include <linux/i2c.h> | ||
| 16 | #include <linux/gpio.h> | 17 | #include <linux/gpio.h> |
| 17 | #include <linux/amba/bus.h> | 18 | #include <linux/amba/bus.h> |
| 18 | #include <linux/amba/pl022.h> | 19 | #include <linux/amba/pl022.h> |
| 19 | #include <linux/spi/spi.h> | 20 | #include <linux/spi/spi.h> |
| 20 | #include <linux/mfd/ab8500.h> | 21 | #include <linux/mfd/ab8500.h> |
| 21 | #include <linux/input/matrix_keypad.h> | 22 | #include <linux/mfd/tc3589x.h> |
| 22 | 23 | ||
| 23 | #include <asm/mach-types.h> | 24 | #include <asm/mach-types.h> |
| 24 | #include <asm/mach/arch.h> | 25 | #include <asm/mach/arch.h> |
| 25 | 26 | ||
| 26 | #include <plat/pincfg.h> | 27 | #include <plat/pincfg.h> |
| 27 | #include <plat/i2c.h> | 28 | #include <plat/i2c.h> |
| 28 | #include <plat/ske.h> | ||
| 29 | 29 | ||
| 30 | #include <mach/hardware.h> | 30 | #include <mach/hardware.h> |
| 31 | #include <mach/setup.h> | 31 | #include <mach/setup.h> |
| 32 | #include <mach/devices.h> | 32 | #include <mach/devices.h> |
| 33 | #include <mach/irqs.h> | 33 | #include <mach/irqs.h> |
| 34 | 34 | ||
| 35 | #include "devices-db8500.h" | ||
| 35 | #include "pins-db8500.h" | 36 | #include "pins-db8500.h" |
| 36 | #include "board-mop500.h" | 37 | #include "board-mop500.h" |
| 37 | 38 | ||
| @@ -69,22 +70,12 @@ static pin_cfg_t mop500_pins[] = { | |||
| 69 | GPIO166_KP_O2, | 70 | GPIO166_KP_O2, |
| 70 | GPIO167_KP_O1, | 71 | GPIO167_KP_O1, |
| 71 | GPIO168_KP_O0, | 72 | GPIO168_KP_O0, |
| 72 | }; | ||
| 73 | 73 | ||
| 74 | static void ab4500_spi_cs_control(u32 command) | 74 | /* GPIO_EXP_INT */ |
| 75 | { | 75 | GPIO217_GPIO, |
| 76 | /* set the FRM signal, which is CS - TODO */ | ||
| 77 | } | ||
| 78 | 76 | ||
| 79 | struct pl022_config_chip ab4500_chip_info = { | 77 | /* STMPE1601 IRQ */ |
| 80 | .com_mode = INTERRUPT_TRANSFER, | 78 | GPIO218_GPIO | PIN_INPUT_PULLUP, |
| 81 | .iface = SSP_INTERFACE_MOTOROLA_SPI, | ||
| 82 | /* we can act as master only */ | ||
| 83 | .hierarchy = SSP_MASTER, | ||
| 84 | .slave_tx_disable = 0, | ||
| 85 | .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, | ||
| 86 | .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, | ||
| 87 | .cs_control = ab4500_spi_cs_control, | ||
| 88 | }; | 79 | }; |
| 89 | 80 | ||
| 90 | static struct ab8500_platform_data ab8500_platdata = { | 81 | static struct ab8500_platform_data ab8500_platdata = { |
| @@ -93,9 +84,9 @@ static struct ab8500_platform_data ab8500_platdata = { | |||
| 93 | 84 | ||
| 94 | static struct resource ab8500_resources[] = { | 85 | static struct resource ab8500_resources[] = { |
| 95 | [0] = { | 86 | [0] = { |
| 96 | .start = IRQ_AB8500, | 87 | .start = IRQ_DB8500_AB8500, |
| 97 | .end = IRQ_AB8500, | 88 | .end = IRQ_DB8500_AB8500, |
| 98 | .flags = IORESOURCE_IRQ | 89 | .flags = IORESOURCE_IRQ |
| 99 | } | 90 | } |
| 100 | }; | 91 | }; |
| 101 | 92 | ||
| @@ -109,19 +100,6 @@ struct platform_device ab8500_device = { | |||
| 109 | .resource = ab8500_resources, | 100 | .resource = ab8500_resources, |
| 110 | }; | 101 | }; |
| 111 | 102 | ||
| 112 | static struct spi_board_info ab8500_spi_devices[] = { | ||
| 113 | { | ||
| 114 | .modalias = "ab8500-spi", | ||
| 115 | .controller_data = &ab4500_chip_info, | ||
| 116 | .platform_data = &ab8500_platdata, | ||
| 117 | .max_speed_hz = 12000000, | ||
| 118 | .bus_num = 0, | ||
| 119 | .chip_select = 0, | ||
| 120 | .mode = SPI_MODE_3, | ||
| 121 | .irq = IRQ_DB8500_AB8500, | ||
| 122 | }, | ||
| 123 | }; | ||
| 124 | |||
| 125 | static struct pl022_ssp_controller ssp0_platform_data = { | 103 | static struct pl022_ssp_controller ssp0_platform_data = { |
| 126 | .bus_id = 0, | 104 | .bus_id = 0, |
| 127 | /* pl022 not yet supports dma */ | 105 | /* pl022 not yet supports dma */ |
| @@ -132,6 +110,34 @@ static struct pl022_ssp_controller ssp0_platform_data = { | |||
| 132 | .num_chipselect = 5, | 110 | .num_chipselect = 5, |
| 133 | }; | 111 | }; |
| 134 | 112 | ||
| 113 | /* | ||
| 114 | * TC35892 | ||
| 115 | */ | ||
| 116 | |||
| 117 | static void mop500_tc35892_init(struct tc3589x *tc3589x, unsigned int base) | ||
| 118 | { | ||
| 119 | mop500_sdi_tc35892_init(); | ||
| 120 | } | ||
| 121 | |||
| 122 | static struct tc3589x_gpio_platform_data mop500_tc35892_gpio_data = { | ||
| 123 | .gpio_base = MOP500_EGPIO(0), | ||
| 124 | .setup = mop500_tc35892_init, | ||
| 125 | }; | ||
| 126 | |||
| 127 | static struct tc3589x_platform_data mop500_tc35892_data = { | ||
| 128 | .block = TC3589x_BLOCK_GPIO, | ||
| 129 | .gpio = &mop500_tc35892_gpio_data, | ||
| 130 | .irq_base = MOP500_EGPIO_IRQ_BASE, | ||
| 131 | }; | ||
| 132 | |||
| 133 | static struct i2c_board_info mop500_i2c0_devices[] = { | ||
| 134 | { | ||
| 135 | I2C_BOARD_INFO("tc3589x", 0x42), | ||
| 136 | .irq = NOMADIK_GPIO_TO_IRQ(217), | ||
| 137 | .platform_data = &mop500_tc35892_data, | ||
| 138 | }, | ||
| 139 | }; | ||
| 140 | |||
| 135 | #define U8500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, _sm) \ | 141 | #define U8500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, _sm) \ |
| 136 | static struct nmk_i2c_controller u8500_i2c##id##_data = { \ | 142 | static struct nmk_i2c_controller u8500_i2c##id##_data = { \ |
| 137 | /* \ | 143 | /* \ |
| @@ -161,159 +167,49 @@ U8500_I2C_CONTROLLER(1, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD); | |||
| 161 | U8500_I2C_CONTROLLER(2, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD); | 167 | U8500_I2C_CONTROLLER(2, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD); |
| 162 | U8500_I2C_CONTROLLER(3, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD); | 168 | U8500_I2C_CONTROLLER(3, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD); |
| 163 | 169 | ||
| 164 | static struct amba_device *amba_devs[] __initdata = { | 170 | static void __init mop500_i2c_init(void) |
| 165 | &ux500_uart0_device, | 171 | { |
| 166 | &ux500_uart1_device, | 172 | db8500_add_i2c0(&u8500_i2c0_data); |
| 167 | &ux500_uart2_device, | 173 | db8500_add_i2c1(&u8500_i2c1_data); |
| 168 | &u8500_ssp0_device, | 174 | db8500_add_i2c2(&u8500_i2c2_data); |
| 169 | }; | 175 | db8500_add_i2c3(&u8500_i2c3_data); |
| 170 | 176 | } | |
| 171 | static const unsigned int ux500_keymap[] = { | ||
| 172 | KEY(2, 5, KEY_END), | ||
| 173 | KEY(4, 1, KEY_POWER), | ||
| 174 | KEY(3, 5, KEY_VOLUMEDOWN), | ||
| 175 | KEY(1, 3, KEY_3), | ||
| 176 | KEY(5, 2, KEY_RIGHT), | ||
| 177 | KEY(5, 0, KEY_9), | ||
| 178 | |||
| 179 | KEY(0, 5, KEY_MENU), | ||
| 180 | KEY(7, 6, KEY_ENTER), | ||
| 181 | KEY(4, 5, KEY_0), | ||
| 182 | KEY(6, 7, KEY_2), | ||
| 183 | KEY(3, 4, KEY_UP), | ||
| 184 | KEY(3, 3, KEY_DOWN), | ||
| 185 | |||
| 186 | KEY(6, 4, KEY_SEND), | ||
| 187 | KEY(6, 2, KEY_BACK), | ||
| 188 | KEY(4, 2, KEY_VOLUMEUP), | ||
| 189 | KEY(5, 5, KEY_1), | ||
| 190 | KEY(4, 3, KEY_LEFT), | ||
| 191 | KEY(3, 2, KEY_7), | ||
| 192 | }; | ||
| 193 | |||
| 194 | static const struct matrix_keymap_data ux500_keymap_data = { | ||
| 195 | .keymap = ux500_keymap, | ||
| 196 | .keymap_size = ARRAY_SIZE(ux500_keymap), | ||
| 197 | }; | ||
| 198 | 177 | ||
| 199 | /* | 178 | /* add any platform devices here - TODO */ |
| 200 | * Nomadik SKE keypad | 179 | static struct platform_device *platform_devs[] __initdata = { |
| 201 | */ | ||
| 202 | #define ROW_PIN_I0 164 | ||
| 203 | #define ROW_PIN_I1 163 | ||
| 204 | #define ROW_PIN_I2 162 | ||
| 205 | #define ROW_PIN_I3 161 | ||
| 206 | #define ROW_PIN_I4 156 | ||
| 207 | #define ROW_PIN_I5 155 | ||
| 208 | #define ROW_PIN_I6 154 | ||
| 209 | #define ROW_PIN_I7 153 | ||
| 210 | #define COL_PIN_O0 168 | ||
| 211 | #define COL_PIN_O1 167 | ||
| 212 | #define COL_PIN_O2 166 | ||
| 213 | #define COL_PIN_O3 165 | ||
| 214 | #define COL_PIN_O4 160 | ||
| 215 | #define COL_PIN_O5 159 | ||
| 216 | #define COL_PIN_O6 158 | ||
| 217 | #define COL_PIN_O7 157 | ||
| 218 | |||
| 219 | #define SKE_KPD_MAX_ROWS 8 | ||
| 220 | #define SKE_KPD_MAX_COLS 8 | ||
| 221 | |||
| 222 | static int ske_kp_rows[] = { | ||
| 223 | ROW_PIN_I0, ROW_PIN_I1, ROW_PIN_I2, ROW_PIN_I3, | ||
| 224 | ROW_PIN_I4, ROW_PIN_I5, ROW_PIN_I6, ROW_PIN_I7, | ||
| 225 | }; | 180 | }; |
| 226 | 181 | ||
| 227 | /* | 182 | static void __init mop500_spi_init(void) |
| 228 | * ske_set_gpio_row: request and set gpio rows | ||
| 229 | */ | ||
| 230 | static int ske_set_gpio_row(int gpio) | ||
| 231 | { | 183 | { |
| 232 | int ret; | 184 | db8500_add_ssp0(&ssp0_platform_data); |
| 233 | |||
| 234 | ret = gpio_request(gpio, "ske-kp"); | ||
| 235 | if (ret < 0) { | ||
| 236 | pr_err("ske_set_gpio_row: gpio request failed\n"); | ||
| 237 | return ret; | ||
| 238 | } | ||
| 239 | |||
| 240 | ret = gpio_direction_output(gpio, 1); | ||
| 241 | if (ret < 0) { | ||
| 242 | pr_err("ske_set_gpio_row: gpio direction failed\n"); | ||
| 243 | gpio_free(gpio); | ||
| 244 | } | ||
| 245 | |||
| 246 | return ret; | ||
| 247 | } | 185 | } |
| 248 | 186 | ||
| 249 | /* | 187 | static void __init mop500_uart_init(void) |
| 250 | * ske_kp_init - enable the gpio configuration | ||
| 251 | */ | ||
| 252 | static int ske_kp_init(void) | ||
| 253 | { | 188 | { |
| 254 | int ret, i; | 189 | db8500_add_uart0(); |
| 255 | 190 | db8500_add_uart1(); | |
| 256 | for (i = 0; i < SKE_KPD_MAX_ROWS; i++) { | 191 | db8500_add_uart2(); |
| 257 | ret = ske_set_gpio_row(ske_kp_rows[i]); | ||
| 258 | if (ret < 0) { | ||
| 259 | pr_err("ske_kp_init: failed init\n"); | ||
| 260 | return ret; | ||
| 261 | } | ||
| 262 | } | ||
| 263 | |||
| 264 | return 0; | ||
| 265 | } | 192 | } |
| 266 | 193 | ||
| 267 | static struct ske_keypad_platform_data ske_keypad_board = { | ||
| 268 | .init = ske_kp_init, | ||
| 269 | .keymap_data = &ux500_keymap_data, | ||
| 270 | .no_autorepeat = true, | ||
| 271 | .krow = SKE_KPD_MAX_ROWS, /* 8x8 matrix */ | ||
| 272 | .kcol = SKE_KPD_MAX_COLS, | ||
| 273 | .debounce_ms = 40, /* in millsecs */ | ||
| 274 | }; | ||
| 275 | |||
| 276 | |||
| 277 | |||
| 278 | /* add any platform devices here - TODO */ | ||
| 279 | static struct platform_device *platform_devs[] __initdata = { | ||
| 280 | &u8500_i2c0_device, | ||
| 281 | &ux500_i2c1_device, | ||
| 282 | &ux500_i2c2_device, | ||
| 283 | &ux500_i2c3_device, | ||
| 284 | &ux500_ske_keypad_device, | ||
| 285 | }; | ||
| 286 | |||
| 287 | static void __init u8500_init_machine(void) | 194 | static void __init u8500_init_machine(void) |
| 288 | { | 195 | { |
| 289 | int i; | ||
| 290 | |||
| 291 | u8500_init_devices(); | 196 | u8500_init_devices(); |
| 292 | 197 | ||
| 293 | nmk_config_pins(mop500_pins, ARRAY_SIZE(mop500_pins)); | 198 | nmk_config_pins(mop500_pins, ARRAY_SIZE(mop500_pins)); |
| 294 | 199 | ||
| 295 | u8500_i2c0_device.dev.platform_data = &u8500_i2c0_data; | ||
| 296 | ux500_i2c1_device.dev.platform_data = &u8500_i2c1_data; | ||
| 297 | ux500_i2c2_device.dev.platform_data = &u8500_i2c2_data; | ||
| 298 | ux500_i2c3_device.dev.platform_data = &u8500_i2c3_data; | ||
| 299 | ux500_ske_keypad_device.dev.platform_data = &ske_keypad_board; | ||
| 300 | |||
| 301 | u8500_ssp0_device.dev.platform_data = &ssp0_platform_data; | ||
| 302 | |||
| 303 | /* Register the active AMBA devices on this board */ | ||
| 304 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) | ||
| 305 | amba_device_register(amba_devs[i], &iomem_resource); | ||
| 306 | |||
| 307 | platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); | 200 | platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); |
| 308 | 201 | ||
| 202 | mop500_i2c_init(); | ||
| 309 | mop500_sdi_init(); | 203 | mop500_sdi_init(); |
| 204 | mop500_spi_init(); | ||
| 205 | mop500_uart_init(); | ||
| 206 | |||
| 207 | mop500_keypad_init(); | ||
| 208 | |||
| 209 | platform_device_register(&ab8500_device); | ||
| 310 | 210 | ||
| 311 | /* If HW is early drop (ED) or V1.0 then use SPI to access AB8500 */ | 211 | i2c_register_board_info(0, mop500_i2c0_devices, |
| 312 | if (cpu_is_u8500ed() || cpu_is_u8500v10()) | 212 | ARRAY_SIZE(mop500_i2c0_devices)); |
| 313 | spi_register_board_info(ab8500_spi_devices, | ||
| 314 | ARRAY_SIZE(ab8500_spi_devices)); | ||
| 315 | else /* If HW is v.1.1 or later use I2C to access AB8500 */ | ||
| 316 | platform_device_register(&ab8500_device); | ||
| 317 | } | 213 | } |
| 318 | 214 | ||
| 319 | MACHINE_START(U8500, "ST-Ericsson MOP500 platform") | 215 | MACHINE_START(U8500, "ST-Ericsson MOP500 platform") |
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h index 2d240322fa6f..3104ae2a02c2 100644 --- a/arch/arm/mach-ux500/board-mop500.h +++ b/arch/arm/mach-ux500/board-mop500.h | |||
| @@ -7,6 +7,15 @@ | |||
| 7 | #ifndef __BOARD_MOP500_H | 7 | #ifndef __BOARD_MOP500_H |
| 8 | #define __BOARD_MOP500_H | 8 | #define __BOARD_MOP500_H |
| 9 | 9 | ||
| 10 | #define MOP500_EGPIO(x) (NOMADIK_NR_GPIO + (x)) | ||
| 11 | |||
| 12 | /* GPIOs on the TC35892 expander */ | ||
| 13 | #define GPIO_SDMMC_CD MOP500_EGPIO(3) | ||
| 14 | #define GPIO_SDMMC_EN MOP500_EGPIO(17) | ||
| 15 | #define GPIO_SDMMC_1V8_3V_SEL MOP500_EGPIO(18) | ||
| 16 | |||
| 10 | extern void mop500_sdi_init(void); | 17 | extern void mop500_sdi_init(void); |
| 18 | extern void mop500_sdi_tc35892_init(void); | ||
| 19 | extern void mop500_keypad_init(void); | ||
| 11 | 20 | ||
| 12 | #endif | 21 | #endif |
diff --git a/arch/arm/mach-ux500/board-u5500-sdi.c b/arch/arm/mach-ux500/board-u5500-sdi.c new file mode 100644 index 000000000000..54712acc0394 --- /dev/null +++ b/arch/arm/mach-ux500/board-u5500-sdi.c | |||
| @@ -0,0 +1,49 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) ST-Ericsson SA 2010 | ||
| 3 | * | ||
| 4 | * Author: Hanumath Prasad <ulf.hansson@stericsson.com> | ||
| 5 | * License terms: GNU General Public License (GPL) version 2 | ||
| 6 | */ | ||
| 7 | |||
| 8 | #include <linux/amba/mmci.h> | ||
| 9 | #include <linux/mmc/host.h> | ||
| 10 | #include <linux/gpio.h> | ||
| 11 | |||
| 12 | #include <plat/pincfg.h> | ||
| 13 | #include <mach/db5500-regs.h> | ||
| 14 | #include <plat/ste_dma40.h> | ||
| 15 | |||
| 16 | #include "pins-db5500.h" | ||
| 17 | #include "devices-db5500.h" | ||
| 18 | #include "ste-dma40-db5500.h" | ||
| 19 | |||
| 20 | static pin_cfg_t u5500_sdi_pins[] = { | ||
| 21 | /* SDI0 (POP eMMC) */ | ||
| 22 | GPIO5_MC0_DAT0 | PIN_DIR_INPUT | PIN_PULL_UP, | ||
| 23 | GPIO6_MC0_DAT1 | PIN_DIR_INPUT | PIN_PULL_UP, | ||
| 24 | GPIO7_MC0_DAT2 | PIN_DIR_INPUT | PIN_PULL_UP, | ||
| 25 | GPIO8_MC0_DAT3 | PIN_DIR_INPUT | PIN_PULL_UP, | ||
| 26 | GPIO9_MC0_DAT4 | PIN_DIR_INPUT | PIN_PULL_UP, | ||
| 27 | GPIO10_MC0_DAT5 | PIN_DIR_INPUT | PIN_PULL_UP, | ||
| 28 | GPIO11_MC0_DAT6 | PIN_DIR_INPUT | PIN_PULL_UP, | ||
| 29 | GPIO12_MC0_DAT7 | PIN_DIR_INPUT | PIN_PULL_UP, | ||
| 30 | GPIO13_MC0_CMD | PIN_DIR_INPUT | PIN_PULL_UP, | ||
| 31 | GPIO14_MC0_CLK | PIN_DIR_OUTPUT | PIN_VAL_LOW, | ||
| 32 | }; | ||
| 33 | |||
| 34 | static struct mmci_platform_data u5500_sdi0_data = { | ||
| 35 | .ocr_mask = MMC_VDD_165_195, | ||
| 36 | .f_max = 50000000, | ||
| 37 | .capabilities = MMC_CAP_4_BIT_DATA | | ||
| 38 | MMC_CAP_8_BIT_DATA | | ||
| 39 | MMC_CAP_MMC_HIGHSPEED, | ||
| 40 | .gpio_cd = -1, | ||
| 41 | .gpio_wp = -1, | ||
| 42 | }; | ||
| 43 | |||
| 44 | void __init u5500_sdi_init(void) | ||
| 45 | { | ||
| 46 | nmk_config_pins(u5500_sdi_pins, ARRAY_SIZE(u5500_sdi_pins)); | ||
| 47 | |||
| 48 | db5500_add_sdi0(&u5500_sdi0_data); | ||
| 49 | } | ||
diff --git a/arch/arm/mach-ux500/board-u5500.c b/arch/arm/mach-ux500/board-u5500.c index 1ca094a45e71..39d370c1f3b4 100644 --- a/arch/arm/mach-ux500/board-u5500.c +++ b/arch/arm/mach-ux500/board-u5500.c | |||
| @@ -9,6 +9,7 @@ | |||
| 9 | #include <linux/platform_device.h> | 9 | #include <linux/platform_device.h> |
| 10 | #include <linux/amba/bus.h> | 10 | #include <linux/amba/bus.h> |
| 11 | #include <linux/gpio.h> | 11 | #include <linux/gpio.h> |
| 12 | #include <linux/irq.h> | ||
| 12 | 13 | ||
| 13 | #include <asm/mach/arch.h> | 14 | #include <asm/mach/arch.h> |
| 14 | #include <asm/mach-types.h> | 15 | #include <asm/mach-types.h> |
| @@ -17,20 +18,24 @@ | |||
| 17 | #include <mach/devices.h> | 18 | #include <mach/devices.h> |
| 18 | #include <mach/setup.h> | 19 | #include <mach/setup.h> |
| 19 | 20 | ||
| 20 | static struct amba_device *amba_board_devs[] __initdata = { | 21 | #include "devices-db5500.h" |
| 21 | &ux500_uart0_device, | 22 | |
| 22 | &ux500_uart1_device, | 23 | static void __init u5500_uart_init(void) |
| 23 | &ux500_uart2_device, | 24 | { |
| 24 | }; | 25 | db5500_add_uart0(); |
| 26 | db5500_add_uart1(); | ||
| 27 | db5500_add_uart2(); | ||
| 28 | } | ||
| 25 | 29 | ||
| 26 | static void __init u5500_init_machine(void) | 30 | static void __init u5500_init_machine(void) |
| 27 | { | 31 | { |
| 28 | u5500_init_devices(); | 32 | u5500_init_devices(); |
| 29 | 33 | ||
| 30 | amba_add_devices(amba_board_devs, ARRAY_SIZE(amba_board_devs)); | 34 | u5500_sdi_init(); |
| 35 | u5500_uart_init(); | ||
| 31 | } | 36 | } |
| 32 | 37 | ||
| 33 | MACHINE_START(U8500, "ST-Ericsson U5500 Platform") | 38 | MACHINE_START(U5500, "ST-Ericsson U5500 Platform") |
| 34 | .boot_params = 0x00000100, | 39 | .boot_params = 0x00000100, |
| 35 | .map_io = u5500_map_io, | 40 | .map_io = u5500_map_io, |
| 36 | .init_irq = ux500_init_irq, | 41 | .init_irq = ux500_init_irq, |
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c index 1675047daf20..b2b0a3b9be8f 100644 --- a/arch/arm/mach-ux500/clock.c +++ b/arch/arm/mach-ux500/clock.c | |||
| @@ -13,13 +13,18 @@ | |||
| 13 | #include <linux/err.h> | 13 | #include <linux/err.h> |
| 14 | #include <linux/clk.h> | 14 | #include <linux/clk.h> |
| 15 | #include <linux/io.h> | 15 | #include <linux/io.h> |
| 16 | 16 | #include <linux/clkdev.h> | |
| 17 | #include <asm/clkdev.h> | ||
| 18 | 17 | ||
| 19 | #include <plat/mtu.h> | 18 | #include <plat/mtu.h> |
| 20 | #include <mach/hardware.h> | 19 | #include <mach/hardware.h> |
| 21 | #include "clock.h" | 20 | #include "clock.h" |
| 22 | 21 | ||
| 22 | #ifdef CONFIG_DEBUG_FS | ||
| 23 | #include <linux/debugfs.h> | ||
| 24 | #include <linux/uaccess.h> /* for copy_from_user */ | ||
| 25 | static LIST_HEAD(clk_list); | ||
| 26 | #endif | ||
| 27 | |||
| 23 | #define PRCC_PCKEN 0x00 | 28 | #define PRCC_PCKEN 0x00 |
| 24 | #define PRCC_PCKDIS 0x04 | 29 | #define PRCC_PCKDIS 0x04 |
| 25 | #define PRCC_KCKEN 0x08 | 30 | #define PRCC_KCKEN 0x08 |
| @@ -131,9 +136,8 @@ EXPORT_SYMBOL(clk_disable); | |||
| 131 | */ | 136 | */ |
| 132 | static unsigned long clk_mtu_get_rate(struct clk *clk) | 137 | static unsigned long clk_mtu_get_rate(struct clk *clk) |
| 133 | { | 138 | { |
| 134 | void __iomem *addr = __io_address(UX500_PRCMU_BASE) | 139 | void __iomem *addr; |
| 135 | + PRCM_TCR; | 140 | u32 tcr; |
| 136 | u32 tcr = readl(addr); | ||
| 137 | int mtu = (int) clk->data; | 141 | int mtu = (int) clk->data; |
| 138 | /* | 142 | /* |
| 139 | * One of these is selected eventually | 143 | * One of these is selected eventually |
| @@ -144,6 +148,21 @@ static unsigned long clk_mtu_get_rate(struct clk *clk) | |||
| 144 | unsigned long mturate; | 148 | unsigned long mturate; |
| 145 | unsigned long retclk; | 149 | unsigned long retclk; |
| 146 | 150 | ||
| 151 | if (cpu_is_u5500()) | ||
| 152 | addr = __io_address(U5500_PRCMU_BASE); | ||
| 153 | else if (cpu_is_u8500()) | ||
| 154 | addr = __io_address(U8500_PRCMU_BASE); | ||
| 155 | else | ||
| 156 | ux500_unknown_soc(); | ||
| 157 | |||
| 158 | /* | ||
| 159 | * On a startup, always conifgure the TCR to the doze mode; | ||
| 160 | * bootloaders do it for us. Do this in the kernel too. | ||
| 161 | */ | ||
| 162 | writel(PRCM_TCR_DOZE_MODE, addr + PRCM_TCR); | ||
| 163 | |||
| 164 | tcr = readl(addr + PRCM_TCR); | ||
| 165 | |||
| 147 | /* Get the rate from the parent as a default */ | 166 | /* Get the rate from the parent as a default */ |
| 148 | if (clk->parent_periph) | 167 | if (clk->parent_periph) |
| 149 | mturate = clk_get_rate(clk->parent_periph); | 168 | mturate = clk_get_rate(clk->parent_periph); |
| @@ -153,45 +172,6 @@ static unsigned long clk_mtu_get_rate(struct clk *clk) | |||
| 153 | /* We need to be connected SOMEWHERE */ | 172 | /* We need to be connected SOMEWHERE */ |
| 154 | BUG(); | 173 | BUG(); |
| 155 | 174 | ||
| 156 | /* | ||
| 157 | * Are we in doze mode? | ||
| 158 | * In this mode the parent peripheral or the fixed 32768 Hz | ||
| 159 | * clock is fed into the block. | ||
| 160 | */ | ||
| 161 | if (!(tcr & PRCM_TCR_DOZE_MODE)) { | ||
| 162 | /* | ||
| 163 | * Here we're using the clock input from the APE ULP | ||
| 164 | * clock domain. But first: are the timers stopped? | ||
| 165 | */ | ||
| 166 | if (tcr & PRCM_TCR_STOPPED) { | ||
| 167 | clk32k = 0; | ||
| 168 | mturate = 0; | ||
| 169 | } else { | ||
| 170 | /* Else default mode: 0 and 2.4 MHz */ | ||
| 171 | clk32k = 0; | ||
| 172 | if (cpu_is_u5500()) | ||
| 173 | /* DB5500 divides by 8 */ | ||
| 174 | mturate /= 8; | ||
| 175 | else if (cpu_is_u8500ed()) { | ||
| 176 | /* | ||
| 177 | * This clocking setting must not be used | ||
| 178 | * in the ED chip, it is simply not | ||
| 179 | * connected anywhere! | ||
| 180 | */ | ||
| 181 | mturate = 0; | ||
| 182 | BUG(); | ||
| 183 | } else | ||
| 184 | /* | ||
| 185 | * In this mode the ulp38m4 clock is divided | ||
| 186 | * by a factor 16, on the DB8500 typically | ||
| 187 | * 38400000 / 16 ~ 2.4 MHz. | ||
| 188 | * TODO: Replace the constant with a reference | ||
| 189 | * to the ULP source once this is modeled. | ||
| 190 | */ | ||
| 191 | mturate = 38400000 / 16; | ||
| 192 | } | ||
| 193 | } | ||
| 194 | |||
| 195 | /* Return the clock selected for this MTU */ | 175 | /* Return the clock selected for this MTU */ |
| 196 | if (tcr & (1 << mtu)) | 176 | if (tcr & (1 << mtu)) |
| 197 | retclk = clk32k; | 177 | retclk = clk32k; |
| @@ -317,6 +297,7 @@ static struct clkops clk_prcc_ops = { | |||
| 317 | }; | 297 | }; |
| 318 | 298 | ||
| 319 | static struct clk clk_32khz = { | 299 | static struct clk clk_32khz = { |
| 300 | .name = "clk_32khz", | ||
| 320 | .rate = 32000, | 301 | .rate = 32000, |
| 321 | }; | 302 | }; |
| 322 | 303 | ||
| @@ -366,94 +347,96 @@ static DEFINE_PRCMU_CLK(uiccclk, 0x4, 1, UICCCLK); /* v1 */ | |||
| 366 | */ | 347 | */ |
| 367 | 348 | ||
| 368 | /* Peripheral Cluster #1 */ | 349 | /* Peripheral Cluster #1 */ |
| 369 | static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk); | 350 | static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk); |
| 370 | static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL); | 351 | static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL); |
| 371 | static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk); | 352 | static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk); |
| 372 | static DEFINE_PRCC_CLK(1, spi3_ed, 7, 7, NULL); | 353 | static DEFINE_PRCC_CLK(1, spi3_ed, 7, 7, NULL); |
| 373 | static DEFINE_PRCC_CLK(1, spi3_v1, 7, -1, NULL); | 354 | static DEFINE_PRCC_CLK(1, spi3_v1, 7, -1, NULL); |
| 374 | static DEFINE_PRCC_CLK(1, i2c2, 6, 6, &clk_i2cclk); | 355 | static DEFINE_PRCC_CLK(1, i2c2, 6, 6, &clk_i2cclk); |
| 375 | static DEFINE_PRCC_CLK(1, sdi0, 5, 5, &clk_sdmmcclk); | 356 | static DEFINE_PRCC_CLK(1, sdi0, 5, 5, &clk_sdmmcclk); |
| 376 | static DEFINE_PRCC_CLK(1, msp1_ed, 4, 4, &clk_msp02clk); | 357 | static DEFINE_PRCC_CLK(1, msp1_ed, 4, 4, &clk_msp02clk); |
| 377 | static DEFINE_PRCC_CLK(1, msp1_v1, 4, 4, &clk_msp1clk); | 358 | static DEFINE_PRCC_CLK(1, msp1_v1, 4, 4, &clk_msp1clk); |
| 378 | static DEFINE_PRCC_CLK(1, msp0, 3, 3, &clk_msp02clk); | 359 | static DEFINE_PRCC_CLK(1, msp0, 3, 3, &clk_msp02clk); |
| 379 | static DEFINE_PRCC_CLK(1, i2c1, 2, 2, &clk_i2cclk); | 360 | static DEFINE_PRCC_CLK(1, i2c1, 2, 2, &clk_i2cclk); |
| 380 | static DEFINE_PRCC_CLK(1, uart1, 1, 1, &clk_uartclk); | 361 | static DEFINE_PRCC_CLK(1, uart1, 1, 1, &clk_uartclk); |
| 381 | static DEFINE_PRCC_CLK(1, uart0, 0, 0, &clk_uartclk); | 362 | static DEFINE_PRCC_CLK(1, uart0, 0, 0, &clk_uartclk); |
| 382 | 363 | ||
| 383 | /* Peripheral Cluster #2 */ | 364 | /* Peripheral Cluster #2 */ |
| 384 | 365 | ||
| 385 | static DEFINE_PRCC_CLK(2, gpio1_ed, 12, -1, NULL); | 366 | static DEFINE_PRCC_CLK(2, gpio1_ed, 12, -1, NULL); |
| 386 | static DEFINE_PRCC_CLK(2, ssitx_ed, 11, -1, NULL); | 367 | static DEFINE_PRCC_CLK(2, ssitx_ed, 11, -1, NULL); |
| 387 | static DEFINE_PRCC_CLK(2, ssirx_ed, 10, -1, NULL); | 368 | static DEFINE_PRCC_CLK(2, ssirx_ed, 10, -1, NULL); |
| 388 | static DEFINE_PRCC_CLK(2, spi0_ed, 9, -1, NULL); | 369 | static DEFINE_PRCC_CLK(2, spi0_ed, 9, -1, NULL); |
| 389 | static DEFINE_PRCC_CLK(2, sdi3_ed, 8, 6, &clk_sdmmcclk); | 370 | static DEFINE_PRCC_CLK(2, sdi3_ed, 8, 6, &clk_sdmmcclk); |
| 390 | static DEFINE_PRCC_CLK(2, sdi1_ed, 7, 5, &clk_sdmmcclk); | 371 | static DEFINE_PRCC_CLK(2, sdi1_ed, 7, 5, &clk_sdmmcclk); |
| 391 | static DEFINE_PRCC_CLK(2, msp2_ed, 6, 4, &clk_msp02clk); | 372 | static DEFINE_PRCC_CLK(2, msp2_ed, 6, 4, &clk_msp02clk); |
| 392 | static DEFINE_PRCC_CLK(2, sdi4_ed, 4, 2, &clk_sdmmcclk); | 373 | static DEFINE_PRCC_CLK(2, sdi4_ed, 4, 2, &clk_sdmmcclk); |
| 393 | static DEFINE_PRCC_CLK(2, pwl_ed, 3, 1, NULL); | 374 | static DEFINE_PRCC_CLK(2, pwl_ed, 3, 1, NULL); |
| 394 | static DEFINE_PRCC_CLK(2, spi1_ed, 2, -1, NULL); | 375 | static DEFINE_PRCC_CLK(2, spi1_ed, 2, -1, NULL); |
| 395 | static DEFINE_PRCC_CLK(2, spi2_ed, 1, -1, NULL); | 376 | static DEFINE_PRCC_CLK(2, spi2_ed, 1, -1, NULL); |
| 396 | static DEFINE_PRCC_CLK(2, i2c3_ed, 0, 0, &clk_i2cclk); | 377 | static DEFINE_PRCC_CLK(2, i2c3_ed, 0, 0, &clk_i2cclk); |
| 397 | 378 | ||
| 398 | static DEFINE_PRCC_CLK(2, gpio1_v1, 11, -1, NULL); | 379 | static DEFINE_PRCC_CLK(2, gpio1_v1, 11, -1, NULL); |
| 399 | static DEFINE_PRCC_CLK(2, ssitx_v1, 10, 7, NULL); | 380 | static DEFINE_PRCC_CLK(2, ssitx_v1, 10, 7, NULL); |
| 400 | static DEFINE_PRCC_CLK(2, ssirx_v1, 9, 6, NULL); | 381 | static DEFINE_PRCC_CLK(2, ssirx_v1, 9, 6, NULL); |
| 401 | static DEFINE_PRCC_CLK(2, spi0_v1, 8, -1, NULL); | 382 | static DEFINE_PRCC_CLK(2, spi0_v1, 8, -1, NULL); |
| 402 | static DEFINE_PRCC_CLK(2, sdi3_v1, 7, 5, &clk_sdmmcclk); | 383 | static DEFINE_PRCC_CLK(2, sdi3_v1, 7, 5, &clk_sdmmcclk); |
| 403 | static DEFINE_PRCC_CLK(2, sdi1_v1, 6, 4, &clk_sdmmcclk); | 384 | static DEFINE_PRCC_CLK(2, sdi1_v1, 6, 4, &clk_sdmmcclk); |
| 404 | static DEFINE_PRCC_CLK(2, msp2_v1, 5, 3, &clk_msp02clk); | 385 | static DEFINE_PRCC_CLK(2, msp2_v1, 5, 3, &clk_msp02clk); |
| 405 | static DEFINE_PRCC_CLK(2, sdi4_v1, 4, 2, &clk_sdmmcclk); | 386 | static DEFINE_PRCC_CLK(2, sdi4_v1, 4, 2, &clk_sdmmcclk); |
| 406 | static DEFINE_PRCC_CLK(2, pwl_v1, 3, 1, NULL); | 387 | static DEFINE_PRCC_CLK(2, pwl_v1, 3, 1, NULL); |
| 407 | static DEFINE_PRCC_CLK(2, spi1_v1, 2, -1, NULL); | 388 | static DEFINE_PRCC_CLK(2, spi1_v1, 2, -1, NULL); |
| 408 | static DEFINE_PRCC_CLK(2, spi2_v1, 1, -1, NULL); | 389 | static DEFINE_PRCC_CLK(2, spi2_v1, 1, -1, NULL); |
| 409 | static DEFINE_PRCC_CLK(2, i2c3_v1, 0, 0, &clk_i2cclk); | 390 | static DEFINE_PRCC_CLK(2, i2c3_v1, 0, 0, &clk_i2cclk); |
| 410 | 391 | ||
| 411 | /* Peripheral Cluster #3 */ | 392 | /* Peripheral Cluster #3 */ |
| 412 | static DEFINE_PRCC_CLK(3, gpio2, 8, -1, NULL); | 393 | static DEFINE_PRCC_CLK(3, gpio2, 8, -1, NULL); |
| 413 | static DEFINE_PRCC_CLK(3, sdi5, 7, 7, &clk_sdmmcclk); | 394 | static DEFINE_PRCC_CLK(3, sdi5, 7, 7, &clk_sdmmcclk); |
| 414 | static DEFINE_PRCC_CLK(3, uart2, 6, 6, &clk_uartclk); | 395 | static DEFINE_PRCC_CLK(3, uart2, 6, 6, &clk_uartclk); |
| 415 | static DEFINE_PRCC_CLK(3, ske, 5, 5, &clk_32khz); | 396 | static DEFINE_PRCC_CLK(3, ske, 5, 5, &clk_32khz); |
| 416 | static DEFINE_PRCC_CLK(3, sdi2, 4, 4, &clk_sdmmcclk); | 397 | static DEFINE_PRCC_CLK(3, sdi2, 4, 4, &clk_sdmmcclk); |
| 417 | static DEFINE_PRCC_CLK(3, i2c0, 3, 3, &clk_i2cclk); | 398 | static DEFINE_PRCC_CLK(3, i2c0, 3, 3, &clk_i2cclk); |
| 418 | static DEFINE_PRCC_CLK(3, ssp1_ed, 2, 2, &clk_i2cclk); | 399 | static DEFINE_PRCC_CLK(3, ssp1_ed, 2, 2, &clk_i2cclk); |
| 419 | static DEFINE_PRCC_CLK(3, ssp0_ed, 1, 1, &clk_i2cclk); | 400 | static DEFINE_PRCC_CLK(3, ssp0_ed, 1, 1, &clk_i2cclk); |
| 420 | static DEFINE_PRCC_CLK(3, ssp1_v1, 2, 2, &clk_sspclk); | 401 | static DEFINE_PRCC_CLK(3, ssp1_v1, 2, 2, &clk_sspclk); |
| 421 | static DEFINE_PRCC_CLK(3, ssp0_v1, 1, 1, &clk_sspclk); | 402 | static DEFINE_PRCC_CLK(3, ssp0_v1, 1, 1, &clk_sspclk); |
| 422 | static DEFINE_PRCC_CLK(3, fsmc, 0, -1, NULL); | 403 | static DEFINE_PRCC_CLK(3, fsmc, 0, -1, NULL); |
| 423 | 404 | ||
| 424 | /* Peripheral Cluster #4 is in the always on domain */ | 405 | /* Peripheral Cluster #4 is in the always on domain */ |
| 425 | 406 | ||
| 426 | /* Peripheral Cluster #5 */ | 407 | /* Peripheral Cluster #5 */ |
| 427 | static DEFINE_PRCC_CLK(5, gpio3, 1, -1, NULL); | 408 | static DEFINE_PRCC_CLK(5, gpio3, 1, -1, NULL); |
| 428 | static DEFINE_PRCC_CLK(5, usb_ed, 0, 0, &clk_i2cclk); | 409 | static DEFINE_PRCC_CLK(5, usb_ed, 0, 0, &clk_i2cclk); |
| 429 | static DEFINE_PRCC_CLK(5, usb_v1, 0, 0, NULL); | 410 | static DEFINE_PRCC_CLK(5, usb_v1, 0, 0, NULL); |
| 430 | 411 | ||
| 431 | /* Peripheral Cluster #6 */ | 412 | /* Peripheral Cluster #6 */ |
| 432 | 413 | ||
| 433 | /* MTU ID in data */ | 414 | /* MTU ID in data */ |
| 434 | static DEFINE_PRCC_CLK_CUSTOM(6, mtu1_v1, 8, -1, NULL, clk_mtu_get_rate, 1); | 415 | static DEFINE_PRCC_CLK_CUSTOM(6, mtu1_v1, 8, -1, NULL, clk_mtu_get_rate, 1); |
| 435 | static DEFINE_PRCC_CLK_CUSTOM(6, mtu0_v1, 7, -1, NULL, clk_mtu_get_rate, 0); | 416 | static DEFINE_PRCC_CLK_CUSTOM(6, mtu0_v1, 7, -1, NULL, clk_mtu_get_rate, 0); |
| 436 | static DEFINE_PRCC_CLK(6, cfgreg_v1, 6, 6, NULL); | 417 | static DEFINE_PRCC_CLK(6, cfgreg_v1, 6, 6, NULL); |
| 437 | static DEFINE_PRCC_CLK(6, dmc_ed, 6, 6, NULL); | 418 | static DEFINE_PRCC_CLK(6, dmc_ed, 6, 6, NULL); |
| 438 | static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL); | 419 | static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL); |
| 439 | static DEFINE_PRCC_CLK(6, unipro_v1, 4, 1, &clk_uniproclk); | 420 | static DEFINE_PRCC_CLK(6, unipro_v1, 4, 1, &clk_uniproclk); |
| 440 | static DEFINE_PRCC_CLK(6, cryp1_ed, 4, -1, NULL); | 421 | static DEFINE_PRCC_CLK(6, cryp1_ed, 4, -1, NULL); |
| 441 | static DEFINE_PRCC_CLK(6, pka, 3, -1, NULL); | 422 | static DEFINE_PRCC_CLK(6, pka, 3, -1, NULL); |
| 442 | static DEFINE_PRCC_CLK(6, hash0, 2, -1, NULL); | 423 | static DEFINE_PRCC_CLK(6, hash0, 2, -1, NULL); |
| 443 | static DEFINE_PRCC_CLK(6, cryp0, 1, -1, NULL); | 424 | static DEFINE_PRCC_CLK(6, cryp0, 1, -1, NULL); |
| 444 | static DEFINE_PRCC_CLK(6, rng_ed, 0, 0, &clk_i2cclk); | 425 | static DEFINE_PRCC_CLK(6, rng_ed, 0, 0, &clk_i2cclk); |
| 445 | static DEFINE_PRCC_CLK(6, rng_v1, 0, 0, &clk_rngclk); | 426 | static DEFINE_PRCC_CLK(6, rng_v1, 0, 0, &clk_rngclk); |
| 446 | 427 | ||
| 447 | /* Peripheral Cluster #7 */ | 428 | /* Peripheral Cluster #7 */ |
| 448 | 429 | ||
| 449 | static DEFINE_PRCC_CLK(7, tzpc0_ed, 4, -1, NULL); | 430 | static DEFINE_PRCC_CLK(7, tzpc0_ed, 4, -1, NULL); |
| 450 | /* MTU ID in data */ | 431 | /* MTU ID in data */ |
| 451 | static DEFINE_PRCC_CLK_CUSTOM(7, mtu1_ed, 3, -1, NULL, clk_mtu_get_rate, 1); | 432 | static DEFINE_PRCC_CLK_CUSTOM(7, mtu1_ed, 3, -1, NULL, clk_mtu_get_rate, 1); |
| 452 | static DEFINE_PRCC_CLK_CUSTOM(7, mtu0_ed, 2, -1, NULL, clk_mtu_get_rate, 0); | 433 | static DEFINE_PRCC_CLK_CUSTOM(7, mtu0_ed, 2, -1, NULL, clk_mtu_get_rate, 0); |
| 453 | static DEFINE_PRCC_CLK(7, wdg_ed, 1, -1, NULL); | 434 | static DEFINE_PRCC_CLK(7, wdg_ed, 1, -1, NULL); |
| 454 | static DEFINE_PRCC_CLK(7, cfgreg_ed, 0, -1, NULL); | 435 | static DEFINE_PRCC_CLK(7, cfgreg_ed, 0, -1, NULL); |
| 455 | 436 | ||
| 456 | static struct clk clk_dummy_apb_pclk; | 437 | static struct clk clk_dummy_apb_pclk = { |
| 438 | .name = "apb_pclk", | ||
| 439 | }; | ||
| 457 | 440 | ||
| 458 | static struct clk_lookup u8500_common_clks[] = { | 441 | static struct clk_lookup u8500_common_clks[] = { |
| 459 | CLK(dummy_apb_pclk, NULL, "apb_pclk"), | 442 | CLK(dummy_apb_pclk, NULL, "apb_pclk"), |
| @@ -554,7 +537,7 @@ static struct clk_lookup u8500_ed_clks[] = { | |||
| 554 | 537 | ||
| 555 | static struct clk_lookup u8500_v1_clks[] = { | 538 | static struct clk_lookup u8500_v1_clks[] = { |
| 556 | /* Peripheral Cluster #1 */ | 539 | /* Peripheral Cluster #1 */ |
| 557 | CLK(i2c4, "nmk-i2c.4", NULL), | 540 | CLK(i2c4, "nmk-i2c.4", NULL), |
| 558 | CLK(spi3_v1, "spi3", NULL), | 541 | CLK(spi3_v1, "spi3", NULL), |
| 559 | CLK(msp1_v1, "msp1", NULL), | 542 | CLK(msp1_v1, "msp1", NULL), |
| 560 | 543 | ||
| @@ -599,6 +582,183 @@ static struct clk_lookup u8500_v1_clks[] = { | |||
| 599 | CLK(uiccclk, "uicc", NULL), | 582 | CLK(uiccclk, "uicc", NULL), |
| 600 | }; | 583 | }; |
| 601 | 584 | ||
| 585 | #ifdef CONFIG_DEBUG_FS | ||
| 586 | /* | ||
| 587 | * debugfs support to trace clock tree hierarchy and attributes with | ||
| 588 | * powerdebug | ||
| 589 | */ | ||
| 590 | static struct dentry *clk_debugfs_root; | ||
| 591 | |||
| 592 | void __init clk_debugfs_add_table(struct clk_lookup *cl, size_t num) | ||
| 593 | { | ||
| 594 | while (num--) { | ||
| 595 | /* Check that the clock has not been already registered */ | ||
| 596 | if (!(cl->clk->list.prev != cl->clk->list.next)) | ||
| 597 | list_add_tail(&cl->clk->list, &clk_list); | ||
| 598 | |||
| 599 | cl++; | ||
| 600 | } | ||
| 601 | } | ||
| 602 | |||
| 603 | static ssize_t usecount_dbg_read(struct file *file, char __user *buf, | ||
| 604 | size_t size, loff_t *off) | ||
| 605 | { | ||
| 606 | struct clk *clk = file->f_dentry->d_inode->i_private; | ||
| 607 | char cusecount[128]; | ||
| 608 | unsigned int len; | ||
| 609 | |||
| 610 | len = sprintf(cusecount, "%u\n", clk->enabled); | ||
| 611 | return simple_read_from_buffer(buf, size, off, cusecount, len); | ||
| 612 | } | ||
| 613 | |||
| 614 | static ssize_t rate_dbg_read(struct file *file, char __user *buf, | ||
| 615 | size_t size, loff_t *off) | ||
| 616 | { | ||
| 617 | struct clk *clk = file->f_dentry->d_inode->i_private; | ||
| 618 | char crate[128]; | ||
| 619 | unsigned int rate; | ||
| 620 | unsigned int len; | ||
| 621 | |||
| 622 | rate = clk_get_rate(clk); | ||
| 623 | len = sprintf(crate, "%u\n", rate); | ||
| 624 | return simple_read_from_buffer(buf, size, off, crate, len); | ||
| 625 | } | ||
| 626 | |||
| 627 | static const struct file_operations usecount_fops = { | ||
| 628 | .read = usecount_dbg_read, | ||
| 629 | }; | ||
| 630 | |||
| 631 | static const struct file_operations set_rate_fops = { | ||
| 632 | .read = rate_dbg_read, | ||
| 633 | }; | ||
| 634 | |||
| 635 | static struct dentry *clk_debugfs_register_dir(struct clk *c, | ||
| 636 | struct dentry *p_dentry) | ||
| 637 | { | ||
| 638 | struct dentry *d, *clk_d, *child, *child_tmp; | ||
| 639 | char s[255]; | ||
| 640 | char *p = s; | ||
| 641 | |||
| 642 | if (c->name == NULL) | ||
| 643 | p += sprintf(p, "BUG"); | ||
| 644 | else | ||
| 645 | p += sprintf(p, "%s", c->name); | ||
| 646 | |||
| 647 | clk_d = debugfs_create_dir(s, p_dentry); | ||
| 648 | if (!clk_d) | ||
| 649 | return NULL; | ||
| 650 | |||
| 651 | d = debugfs_create_file("usecount", S_IRUGO, | ||
| 652 | clk_d, c, &usecount_fops); | ||
| 653 | if (!d) | ||
| 654 | goto err_out; | ||
| 655 | d = debugfs_create_file("rate", S_IRUGO, | ||
| 656 | clk_d, c, &set_rate_fops); | ||
| 657 | if (!d) | ||
| 658 | goto err_out; | ||
| 659 | /* | ||
| 660 | * TODO : not currently available in ux500 | ||
| 661 | * d = debugfs_create_x32("flags", S_IRUGO, clk_d, (u32 *)&c->flags); | ||
| 662 | * if (!d) | ||
| 663 | * goto err_out; | ||
| 664 | */ | ||
| 665 | |||
| 666 | return clk_d; | ||
| 667 | |||
| 668 | err_out: | ||
| 669 | d = clk_d; | ||
| 670 | list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child) | ||
| 671 | debugfs_remove(child); | ||
| 672 | debugfs_remove(clk_d); | ||
| 673 | return NULL; | ||
| 674 | } | ||
| 675 | |||
| 676 | static void clk_debugfs_remove_dir(struct dentry *cdentry) | ||
| 677 | { | ||
| 678 | struct dentry *d, *child, *child_tmp; | ||
| 679 | |||
| 680 | d = cdentry; | ||
| 681 | list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child) | ||
| 682 | debugfs_remove(child); | ||
| 683 | debugfs_remove(cdentry); | ||
| 684 | return ; | ||
| 685 | } | ||
| 686 | |||
| 687 | static int clk_debugfs_register_one(struct clk *c) | ||
| 688 | { | ||
| 689 | struct clk *pa = c->parent_periph; | ||
| 690 | struct clk *bpa = c->parent_cluster; | ||
| 691 | |||
| 692 | if (!(bpa && !pa)) { | ||
| 693 | c->dent = clk_debugfs_register_dir(c, | ||
| 694 | pa ? pa->dent : clk_debugfs_root); | ||
| 695 | if (!c->dent) | ||
| 696 | return -ENOMEM; | ||
| 697 | } | ||
| 698 | |||
| 699 | if (bpa) { | ||
| 700 | c->dent_bus = clk_debugfs_register_dir(c, | ||
| 701 | bpa->dent_bus ? bpa->dent_bus : bpa->dent); | ||
| 702 | if ((!c->dent_bus) && (c->dent)) { | ||
| 703 | clk_debugfs_remove_dir(c->dent); | ||
| 704 | c->dent = NULL; | ||
| 705 | return -ENOMEM; | ||
| 706 | } | ||
| 707 | } | ||
| 708 | return 0; | ||
| 709 | } | ||
| 710 | |||
| 711 | static int clk_debugfs_register(struct clk *c) | ||
| 712 | { | ||
| 713 | int err; | ||
| 714 | struct clk *pa = c->parent_periph; | ||
| 715 | struct clk *bpa = c->parent_cluster; | ||
| 716 | |||
| 717 | if (pa && (!pa->dent && !pa->dent_bus)) { | ||
| 718 | err = clk_debugfs_register(pa); | ||
| 719 | if (err) | ||
| 720 | return err; | ||
| 721 | } | ||
| 722 | |||
| 723 | if (bpa && (!bpa->dent && !bpa->dent_bus)) { | ||
| 724 | err = clk_debugfs_register(bpa); | ||
| 725 | if (err) | ||
| 726 | return err; | ||
| 727 | } | ||
| 728 | |||
| 729 | if ((!c->dent) && (!c->dent_bus)) { | ||
| 730 | err = clk_debugfs_register_one(c); | ||
| 731 | if (err) | ||
| 732 | return err; | ||
| 733 | } | ||
| 734 | return 0; | ||
| 735 | } | ||
| 736 | |||
| 737 | static int __init clk_debugfs_init(void) | ||
| 738 | { | ||
| 739 | struct clk *c; | ||
| 740 | struct dentry *d; | ||
| 741 | int err; | ||
| 742 | |||
| 743 | d = debugfs_create_dir("clock", NULL); | ||
| 744 | if (!d) | ||
| 745 | return -ENOMEM; | ||
| 746 | clk_debugfs_root = d; | ||
| 747 | |||
| 748 | list_for_each_entry(c, &clk_list, list) { | ||
| 749 | err = clk_debugfs_register(c); | ||
| 750 | if (err) | ||
| 751 | goto err_out; | ||
| 752 | } | ||
| 753 | return 0; | ||
| 754 | err_out: | ||
| 755 | debugfs_remove_recursive(clk_debugfs_root); | ||
| 756 | return err; | ||
| 757 | } | ||
| 758 | |||
| 759 | late_initcall(clk_debugfs_init); | ||
| 760 | #endif /* defined(CONFIG_DEBUG_FS) */ | ||
| 761 | |||
| 602 | int __init clk_init(void) | 762 | int __init clk_init(void) |
| 603 | { | 763 | { |
| 604 | if (cpu_is_u8500ed()) { | 764 | if (cpu_is_u8500ed()) { |
| @@ -609,7 +769,8 @@ int __init clk_init(void) | |||
| 609 | /* Clock tree for U5500 not implemented yet */ | 769 | /* Clock tree for U5500 not implemented yet */ |
| 610 | clk_prcc_ops.enable = clk_prcc_ops.disable = NULL; | 770 | clk_prcc_ops.enable = clk_prcc_ops.disable = NULL; |
| 611 | clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL; | 771 | clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL; |
| 612 | clk_per6clk.rate = 26000000; | 772 | clk_uartclk.rate = 36360000; |
| 773 | clk_sdmmcclk.rate = 99900000; | ||
| 613 | } | 774 | } |
| 614 | 775 | ||
| 615 | clkdev_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks)); | 776 | clkdev_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks)); |
| @@ -618,5 +779,12 @@ int __init clk_init(void) | |||
| 618 | else | 779 | else |
| 619 | clkdev_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks)); | 780 | clkdev_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks)); |
| 620 | 781 | ||
| 782 | #ifdef CONFIG_DEBUG_FS | ||
| 783 | clk_debugfs_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks)); | ||
| 784 | if (cpu_is_u8500ed()) | ||
| 785 | clk_debugfs_add_table(u8500_ed_clks, ARRAY_SIZE(u8500_ed_clks)); | ||
| 786 | else | ||
| 787 | clk_debugfs_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks)); | ||
| 788 | #endif | ||
| 621 | return 0; | 789 | return 0; |
| 622 | } | 790 | } |
diff --git a/arch/arm/mach-ux500/clock.h b/arch/arm/mach-ux500/clock.h index a05802501527..074490705229 100644 --- a/arch/arm/mach-ux500/clock.h +++ b/arch/arm/mach-ux500/clock.h | |||
| @@ -90,6 +90,10 @@ struct clk { | |||
| 90 | 90 | ||
| 91 | struct clk *parent_cluster; | 91 | struct clk *parent_cluster; |
| 92 | struct clk *parent_periph; | 92 | struct clk *parent_periph; |
| 93 | #if defined(CONFIG_DEBUG_FS) | ||
| 94 | struct dentry *dent; /* For visible tree hierarchy */ | ||
| 95 | struct dentry *dent_bus; /* For visible tree hierarchy */ | ||
| 96 | #endif | ||
| 93 | }; | 97 | }; |
| 94 | 98 | ||
| 95 | #define DEFINE_PRCMU_CLK(_name, _cg_off, _cg_bit, _reg) \ | 99 | #define DEFINE_PRCMU_CLK(_name, _cg_off, _cg_bit, _reg) \ |
diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c index 2f87075e9d6f..af04e0891a78 100644 --- a/arch/arm/mach-ux500/cpu-db5500.c +++ b/arch/arm/mach-ux500/cpu-db5500.c | |||
| @@ -8,15 +8,33 @@ | |||
| 8 | #include <linux/platform_device.h> | 8 | #include <linux/platform_device.h> |
| 9 | #include <linux/amba/bus.h> | 9 | #include <linux/amba/bus.h> |
| 10 | #include <linux/io.h> | 10 | #include <linux/io.h> |
| 11 | #include <linux/irq.h> | ||
| 11 | 12 | ||
| 12 | #include <asm/mach/map.h> | 13 | #include <asm/mach/map.h> |
| 13 | 14 | ||
| 15 | #include <plat/gpio.h> | ||
| 16 | |||
| 14 | #include <mach/hardware.h> | 17 | #include <mach/hardware.h> |
| 15 | #include <mach/devices.h> | 18 | #include <mach/devices.h> |
| 16 | #include <mach/setup.h> | 19 | #include <mach/setup.h> |
| 17 | #include <mach/irqs.h> | 20 | #include <mach/irqs.h> |
| 18 | 21 | ||
| 22 | #include "devices-db5500.h" | ||
| 23 | |||
| 24 | static struct map_desc u5500_uart_io_desc[] __initdata = { | ||
| 25 | __IO_DEV_DESC(U5500_UART0_BASE, SZ_4K), | ||
| 26 | __IO_DEV_DESC(U5500_UART2_BASE, SZ_4K), | ||
| 27 | }; | ||
| 28 | |||
| 19 | static struct map_desc u5500_io_desc[] __initdata = { | 29 | static struct map_desc u5500_io_desc[] __initdata = { |
| 30 | __IO_DEV_DESC(U5500_GIC_CPU_BASE, SZ_4K), | ||
| 31 | __IO_DEV_DESC(U5500_GIC_DIST_BASE, SZ_4K), | ||
| 32 | __IO_DEV_DESC(U5500_L2CC_BASE, SZ_4K), | ||
| 33 | __IO_DEV_DESC(U5500_TWD_BASE, SZ_4K), | ||
| 34 | __IO_DEV_DESC(U5500_MTU0_BASE, SZ_4K), | ||
| 35 | __IO_DEV_DESC(U5500_SCU_BASE, SZ_4K), | ||
| 36 | __IO_DEV_DESC(U5500_BACKUPRAM0_BASE, SZ_8K), | ||
| 37 | |||
| 20 | __IO_DEV_DESC(U5500_GPIO0_BASE, SZ_4K), | 38 | __IO_DEV_DESC(U5500_GPIO0_BASE, SZ_4K), |
| 21 | __IO_DEV_DESC(U5500_GPIO1_BASE, SZ_4K), | 39 | __IO_DEV_DESC(U5500_GPIO1_BASE, SZ_4K), |
| 22 | __IO_DEV_DESC(U5500_GPIO2_BASE, SZ_4K), | 40 | __IO_DEV_DESC(U5500_GPIO2_BASE, SZ_4K), |
| @@ -110,21 +128,39 @@ static struct platform_device mbox2_device = { | |||
| 110 | }; | 128 | }; |
| 111 | 129 | ||
| 112 | static struct platform_device *u5500_platform_devs[] __initdata = { | 130 | static struct platform_device *u5500_platform_devs[] __initdata = { |
| 113 | &u5500_gpio_devs[0], | ||
| 114 | &u5500_gpio_devs[1], | ||
| 115 | &u5500_gpio_devs[2], | ||
| 116 | &u5500_gpio_devs[3], | ||
| 117 | &u5500_gpio_devs[4], | ||
| 118 | &u5500_gpio_devs[5], | ||
| 119 | &u5500_gpio_devs[6], | ||
| 120 | &u5500_gpio_devs[7], | ||
| 121 | &mbox0_device, | 131 | &mbox0_device, |
| 122 | &mbox1_device, | 132 | &mbox1_device, |
| 123 | &mbox2_device, | 133 | &mbox2_device, |
| 124 | }; | 134 | }; |
| 125 | 135 | ||
| 136 | static resource_size_t __initdata db5500_gpio_base[] = { | ||
| 137 | U5500_GPIOBANK0_BASE, | ||
| 138 | U5500_GPIOBANK1_BASE, | ||
| 139 | U5500_GPIOBANK2_BASE, | ||
| 140 | U5500_GPIOBANK3_BASE, | ||
| 141 | U5500_GPIOBANK4_BASE, | ||
| 142 | U5500_GPIOBANK5_BASE, | ||
| 143 | U5500_GPIOBANK6_BASE, | ||
| 144 | U5500_GPIOBANK7_BASE, | ||
| 145 | }; | ||
| 146 | |||
| 147 | static void __init db5500_add_gpios(void) | ||
| 148 | { | ||
| 149 | struct nmk_gpio_platform_data pdata = { | ||
| 150 | /* No custom data yet */ | ||
| 151 | }; | ||
| 152 | |||
| 153 | dbx500_add_gpios(ARRAY_AND_SIZE(db5500_gpio_base), | ||
| 154 | IRQ_DB5500_GPIO0, &pdata); | ||
| 155 | } | ||
| 156 | |||
| 126 | void __init u5500_map_io(void) | 157 | void __init u5500_map_io(void) |
| 127 | { | 158 | { |
| 159 | /* | ||
| 160 | * Map the UARTs early so that the DEBUG_LL stuff continues to work. | ||
| 161 | */ | ||
| 162 | iotable_init(u5500_uart_io_desc, ARRAY_SIZE(u5500_uart_io_desc)); | ||
| 163 | |||
| 128 | ux500_map_io(); | 164 | ux500_map_io(); |
| 129 | 165 | ||
| 130 | iotable_init(u5500_io_desc, ARRAY_SIZE(u5500_io_desc)); | 166 | iotable_init(u5500_io_desc, ARRAY_SIZE(u5500_io_desc)); |
| @@ -132,7 +168,9 @@ void __init u5500_map_io(void) | |||
| 132 | 168 | ||
| 133 | void __init u5500_init_devices(void) | 169 | void __init u5500_init_devices(void) |
| 134 | { | 170 | { |
| 135 | ux500_init_devices(); | 171 | db5500_add_gpios(); |
| 172 | db5500_dma_init(); | ||
| 173 | db5500_add_rtc(); | ||
| 136 | 174 | ||
| 137 | platform_add_devices(u5500_platform_devs, | 175 | platform_add_devices(u5500_platform_devs, |
| 138 | ARRAY_SIZE(u5500_platform_devs)); | 176 | ARRAY_SIZE(u5500_platform_devs)); |
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 4acab7544b3c..1748fbc58530 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c | |||
| @@ -22,115 +22,93 @@ | |||
| 22 | #include <mach/setup.h> | 22 | #include <mach/setup.h> |
| 23 | #include <mach/devices.h> | 23 | #include <mach/devices.h> |
| 24 | 24 | ||
| 25 | #include "devices-db8500.h" | ||
| 26 | |||
| 25 | static struct platform_device *platform_devs[] __initdata = { | 27 | static struct platform_device *platform_devs[] __initdata = { |
| 26 | &u8500_gpio_devs[0], | ||
| 27 | &u8500_gpio_devs[1], | ||
| 28 | &u8500_gpio_devs[2], | ||
| 29 | &u8500_gpio_devs[3], | ||
| 30 | &u8500_gpio_devs[4], | ||
| 31 | &u8500_gpio_devs[5], | ||
| 32 | &u8500_gpio_devs[6], | ||
| 33 | &u8500_gpio_devs[7], | ||
| 34 | &u8500_gpio_devs[8], | ||
| 35 | &u8500_dma40_device, | 28 | &u8500_dma40_device, |
| 36 | }; | 29 | }; |
| 37 | 30 | ||
| 38 | /* minimum static i/o mapping required to boot U8500 platforms */ | 31 | /* minimum static i/o mapping required to boot U8500 platforms */ |
| 32 | static struct map_desc u8500_uart_io_desc[] __initdata = { | ||
| 33 | __IO_DEV_DESC(U8500_UART0_BASE, SZ_4K), | ||
| 34 | __IO_DEV_DESC(U8500_UART2_BASE, SZ_4K), | ||
| 35 | }; | ||
| 36 | |||
| 39 | static struct map_desc u8500_io_desc[] __initdata = { | 37 | static struct map_desc u8500_io_desc[] __initdata = { |
| 38 | __IO_DEV_DESC(U8500_GIC_CPU_BASE, SZ_4K), | ||
| 39 | __IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K), | ||
| 40 | __IO_DEV_DESC(U8500_L2CC_BASE, SZ_4K), | ||
| 41 | __IO_DEV_DESC(U8500_TWD_BASE, SZ_4K), | ||
| 42 | __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K), | ||
| 43 | __IO_DEV_DESC(U8500_SCU_BASE, SZ_4K), | ||
| 44 | __IO_DEV_DESC(U8500_BACKUPRAM0_BASE, SZ_8K), | ||
| 45 | |||
| 46 | __IO_DEV_DESC(U8500_CLKRST1_BASE, SZ_4K), | ||
| 47 | __IO_DEV_DESC(U8500_CLKRST2_BASE, SZ_4K), | ||
| 48 | __IO_DEV_DESC(U8500_CLKRST3_BASE, SZ_4K), | ||
| 49 | __IO_DEV_DESC(U8500_CLKRST5_BASE, SZ_4K), | ||
| 50 | __IO_DEV_DESC(U8500_CLKRST6_BASE, SZ_4K), | ||
| 51 | |||
| 40 | __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K), | 52 | __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K), |
| 41 | __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K), | ||
| 42 | __IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K), | 53 | __IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K), |
| 43 | __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K), | 54 | __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K), |
| 44 | __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K), | 55 | __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K), |
| 45 | __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K), | 56 | __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K), |
| 46 | __MEM_DEV_DESC(U8500_BOOT_ROM_BASE, SZ_1M), | ||
| 47 | }; | 57 | }; |
| 48 | 58 | ||
| 49 | static struct map_desc u8500ed_io_desc[] __initdata = { | 59 | static struct map_desc u8500_ed_io_desc[] __initdata = { |
| 50 | __IO_DEV_DESC(U8500_MTU0_BASE_ED, SZ_4K), | 60 | __IO_DEV_DESC(U8500_MTU0_BASE_ED, SZ_4K), |
| 51 | __IO_DEV_DESC(U8500_CLKRST7_BASE_ED, SZ_8K), | 61 | __IO_DEV_DESC(U8500_CLKRST7_BASE_ED, SZ_8K), |
| 52 | }; | 62 | }; |
| 53 | 63 | ||
| 54 | static struct map_desc u8500v1_io_desc[] __initdata = { | 64 | static struct map_desc u8500_v1_io_desc[] __initdata = { |
| 55 | __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K), | 65 | __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K), |
| 66 | __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE_V1, SZ_4K), | ||
| 56 | }; | 67 | }; |
| 57 | 68 | ||
| 58 | /* | 69 | static struct map_desc u8500_v2_io_desc[] __initdata = { |
| 59 | * Functions to differentiate between later ASICs | 70 | __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K), |
| 60 | * We look into the end of the ROM to locate the hardcoded ASIC ID. | ||
| 61 | * This is only needed to differentiate between minor revisions and | ||
| 62 | * process variants of an ASIC, the major revisions are encoded in | ||
| 63 | * the cpuid. | ||
| 64 | */ | ||
| 65 | #define U8500_ASIC_ID_LOC_ED_V1 (U8500_BOOT_ROM_BASE + 0x1FFF4) | ||
| 66 | #define U8500_ASIC_ID_LOC_V2 (U8500_BOOT_ROM_BASE + 0x1DBF4) | ||
| 67 | #define U8500_ASIC_REV_ED 0x01 | ||
| 68 | #define U8500_ASIC_REV_V10 0xA0 | ||
| 69 | #define U8500_ASIC_REV_V11 0xA1 | ||
| 70 | #define U8500_ASIC_REV_V20 0xB0 | ||
| 71 | |||
| 72 | /** | ||
| 73 | * struct db8500_asic_id - fields of the ASIC ID | ||
| 74 | * @process: the manufacturing process, 0x40 is 40 nm | ||
| 75 | * 0x00 is "standard" | ||
| 76 | * @partnumber: hithereto 0x8500 for DB8500 | ||
| 77 | * @revision: version code in the series | ||
| 78 | * This field definion is not formally defined but makes | ||
| 79 | * sense. | ||
| 80 | */ | ||
| 81 | struct db8500_asic_id { | ||
| 82 | u8 process; | ||
| 83 | u16 partnumber; | ||
| 84 | u8 revision; | ||
| 85 | }; | 71 | }; |
| 86 | 72 | ||
| 87 | /* This isn't going to change at runtime */ | 73 | void __init u8500_map_io(void) |
| 88 | static struct db8500_asic_id db8500_id; | ||
| 89 | |||
| 90 | static void __init get_db8500_asic_id(void) | ||
| 91 | { | 74 | { |
| 92 | u32 asicid; | 75 | /* |
| 76 | * Map the UARTs early so that the DEBUG_LL stuff continues to work. | ||
| 77 | */ | ||
| 78 | iotable_init(u8500_uart_io_desc, ARRAY_SIZE(u8500_uart_io_desc)); | ||
| 93 | 79 | ||
| 94 | if (cpu_is_u8500v1() || cpu_is_u8500ed()) | 80 | ux500_map_io(); |
| 95 | asicid = readl(__io_address(U8500_ASIC_ID_LOC_ED_V1)); | ||
| 96 | else if (cpu_is_u8500v2()) | ||
| 97 | asicid = readl(__io_address(U8500_ASIC_ID_LOC_V2)); | ||
| 98 | else | ||
| 99 | BUG(); | ||
| 100 | |||
| 101 | db8500_id.process = (asicid >> 24); | ||
| 102 | db8500_id.partnumber = (asicid >> 16) & 0xFFFFU; | ||
| 103 | db8500_id.revision = asicid & 0xFFU; | ||
| 104 | } | ||
| 105 | 81 | ||
| 106 | bool cpu_is_u8500v10(void) | 82 | iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc)); |
| 107 | { | ||
| 108 | return (db8500_id.revision == U8500_ASIC_REV_V10); | ||
| 109 | } | ||
| 110 | 83 | ||
| 111 | bool cpu_is_u8500v11(void) | 84 | if (cpu_is_u8500ed()) |
| 112 | { | 85 | iotable_init(u8500_ed_io_desc, ARRAY_SIZE(u8500_ed_io_desc)); |
| 113 | return (db8500_id.revision == U8500_ASIC_REV_V11); | 86 | else if (cpu_is_u8500v1()) |
| 87 | iotable_init(u8500_v1_io_desc, ARRAY_SIZE(u8500_v1_io_desc)); | ||
| 88 | else if (cpu_is_u8500v2()) | ||
| 89 | iotable_init(u8500_v2_io_desc, ARRAY_SIZE(u8500_v2_io_desc)); | ||
| 114 | } | 90 | } |
| 115 | 91 | ||
| 116 | bool cpu_is_u8500v20(void) | 92 | static resource_size_t __initdata db8500_gpio_base[] = { |
| 117 | { | 93 | U8500_GPIOBANK0_BASE, |
| 118 | return (db8500_id.revision == U8500_ASIC_REV_V20); | 94 | U8500_GPIOBANK1_BASE, |
| 119 | } | 95 | U8500_GPIOBANK2_BASE, |
| 96 | U8500_GPIOBANK3_BASE, | ||
| 97 | U8500_GPIOBANK4_BASE, | ||
| 98 | U8500_GPIOBANK5_BASE, | ||
| 99 | U8500_GPIOBANK6_BASE, | ||
| 100 | U8500_GPIOBANK7_BASE, | ||
| 101 | U8500_GPIOBANK8_BASE, | ||
| 102 | }; | ||
| 120 | 103 | ||
| 121 | void __init u8500_map_io(void) | 104 | static void __init db8500_add_gpios(void) |
| 122 | { | 105 | { |
| 123 | ux500_map_io(); | 106 | struct nmk_gpio_platform_data pdata = { |
| 124 | 107 | /* No custom data yet */ | |
| 125 | iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc)); | 108 | }; |
| 126 | |||
| 127 | if (cpu_is_u8500ed()) | ||
| 128 | iotable_init(u8500ed_io_desc, ARRAY_SIZE(u8500ed_io_desc)); | ||
| 129 | else | ||
| 130 | iotable_init(u8500v1_io_desc, ARRAY_SIZE(u8500v1_io_desc)); | ||
| 131 | 109 | ||
| 132 | /* Read out the ASIC ID as early as we can */ | 110 | dbx500_add_gpios(ARRAY_AND_SIZE(db8500_gpio_base), |
| 133 | get_db8500_asic_id(); | 111 | IRQ_DB8500_GPIO0, &pdata); |
| 134 | } | 112 | } |
| 135 | 113 | ||
| 136 | /* | 114 | /* |
| @@ -138,26 +116,13 @@ void __init u8500_map_io(void) | |||
| 138 | */ | 116 | */ |
| 139 | void __init u8500_init_devices(void) | 117 | void __init u8500_init_devices(void) |
| 140 | { | 118 | { |
| 141 | /* Display some ASIC boilerplate */ | ||
| 142 | pr_info("DB8500: process: %02x, revision ID: 0x%02x\n", | ||
| 143 | db8500_id.process, db8500_id.revision); | ||
| 144 | if (cpu_is_u8500ed()) | ||
| 145 | pr_info("DB8500: Early Drop (ED)\n"); | ||
| 146 | else if (cpu_is_u8500v10()) | ||
| 147 | pr_info("DB8500: version 1.0\n"); | ||
| 148 | else if (cpu_is_u8500v11()) | ||
| 149 | pr_info("DB8500: version 1.1\n"); | ||
| 150 | else if (cpu_is_u8500v20()) | ||
| 151 | pr_info("DB8500: version 2.0\n"); | ||
| 152 | else | ||
| 153 | pr_warning("ASIC: UNKNOWN SILICON VERSION!\n"); | ||
| 154 | |||
| 155 | ux500_init_devices(); | ||
| 156 | |||
| 157 | if (cpu_is_u8500ed()) | 119 | if (cpu_is_u8500ed()) |
| 158 | dma40_u8500ed_fixup(); | 120 | dma40_u8500ed_fixup(); |
| 159 | 121 | ||
| 160 | /* Register the platform devices */ | 122 | db8500_add_rtc(); |
| 123 | db8500_add_gpios(); | ||
| 124 | |||
| 125 | platform_device_register_simple("cpufreq-u8500", -1, NULL, 0); | ||
| 161 | platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); | 126 | platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); |
| 162 | 127 | ||
| 163 | return ; | 128 | return ; |
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index 608a1372b172..5a43107c6232 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c | |||
| @@ -6,7 +6,6 @@ | |||
| 6 | */ | 6 | */ |
| 7 | 7 | ||
| 8 | #include <linux/platform_device.h> | 8 | #include <linux/platform_device.h> |
| 9 | #include <linux/amba/bus.h> | ||
| 10 | #include <linux/io.h> | 9 | #include <linux/io.h> |
| 11 | #include <linux/clk.h> | 10 | #include <linux/clk.h> |
| 12 | 11 | ||
| @@ -20,54 +19,36 @@ | |||
| 20 | #include <mach/hardware.h> | 19 | #include <mach/hardware.h> |
| 21 | #include <mach/setup.h> | 20 | #include <mach/setup.h> |
| 22 | #include <mach/devices.h> | 21 | #include <mach/devices.h> |
| 22 | #include <mach/prcmu.h> | ||
| 23 | 23 | ||
| 24 | #include "clock.h" | 24 | #include "clock.h" |
| 25 | 25 | ||
| 26 | static struct map_desc ux500_io_desc[] __initdata = { | 26 | #ifdef CONFIG_CACHE_L2X0 |
| 27 | __IO_DEV_DESC(UX500_UART0_BASE, SZ_4K), | 27 | static void __iomem *l2x0_base; |
| 28 | __IO_DEV_DESC(UX500_UART2_BASE, SZ_4K), | 28 | #endif |
| 29 | |||
| 30 | __IO_DEV_DESC(UX500_GIC_CPU_BASE, SZ_4K), | ||
| 31 | __IO_DEV_DESC(UX500_GIC_DIST_BASE, SZ_4K), | ||
| 32 | __IO_DEV_DESC(UX500_L2CC_BASE, SZ_4K), | ||
| 33 | __IO_DEV_DESC(UX500_TWD_BASE, SZ_4K), | ||
| 34 | __IO_DEV_DESC(UX500_SCU_BASE, SZ_4K), | ||
| 35 | |||
| 36 | __IO_DEV_DESC(UX500_CLKRST1_BASE, SZ_4K), | ||
| 37 | __IO_DEV_DESC(UX500_CLKRST2_BASE, SZ_4K), | ||
| 38 | __IO_DEV_DESC(UX500_CLKRST3_BASE, SZ_4K), | ||
| 39 | __IO_DEV_DESC(UX500_CLKRST5_BASE, SZ_4K), | ||
| 40 | __IO_DEV_DESC(UX500_CLKRST6_BASE, SZ_4K), | ||
| 41 | |||
| 42 | __IO_DEV_DESC(UX500_MTU0_BASE, SZ_4K), | ||
| 43 | __IO_DEV_DESC(UX500_MTU1_BASE, SZ_4K), | ||
| 44 | |||
| 45 | __IO_DEV_DESC(UX500_BACKUPRAM0_BASE, SZ_8K), | ||
| 46 | }; | ||
| 47 | |||
| 48 | static struct amba_device *ux500_amba_devs[] __initdata = { | ||
| 49 | &ux500_pl031_device, | ||
| 50 | }; | ||
| 51 | 29 | ||
| 52 | void __init ux500_map_io(void) | 30 | void __init ux500_init_irq(void) |
| 53 | { | 31 | { |
| 54 | iotable_init(ux500_io_desc, ARRAY_SIZE(ux500_io_desc)); | 32 | void __iomem *dist_base; |
| 55 | } | 33 | void __iomem *cpu_base; |
| 56 | 34 | ||
| 57 | void __init ux500_init_devices(void) | 35 | if (cpu_is_u5500()) { |
| 58 | { | 36 | dist_base = __io_address(U5500_GIC_DIST_BASE); |
| 59 | amba_add_devices(ux500_amba_devs, ARRAY_SIZE(ux500_amba_devs)); | 37 | cpu_base = __io_address(U5500_GIC_CPU_BASE); |
| 60 | } | 38 | } else if (cpu_is_u8500()) { |
| 39 | dist_base = __io_address(U8500_GIC_DIST_BASE); | ||
| 40 | cpu_base = __io_address(U8500_GIC_CPU_BASE); | ||
| 41 | } else | ||
| 42 | ux500_unknown_soc(); | ||
| 61 | 43 | ||
| 62 | void __init ux500_init_irq(void) | 44 | gic_init(0, 29, dist_base, cpu_base); |
| 63 | { | ||
| 64 | gic_dist_init(0, __io_address(UX500_GIC_DIST_BASE), 29); | ||
| 65 | gic_cpu_init(0, __io_address(UX500_GIC_CPU_BASE)); | ||
| 66 | 45 | ||
| 67 | /* | 46 | /* |
| 68 | * Init clocks here so that they are available for system timer | 47 | * Init clocks here so that they are available for system timer |
| 69 | * initialization. | 48 | * initialization. |
| 70 | */ | 49 | */ |
| 50 | if (cpu_is_u8500()) | ||
| 51 | prcmu_early_init(); | ||
| 71 | clk_init(); | 52 | clk_init(); |
| 72 | } | 53 | } |
| 73 | 54 | ||
| @@ -81,7 +62,8 @@ static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask) | |||
| 81 | 62 | ||
| 82 | static inline void ux500_cache_sync(void) | 63 | static inline void ux500_cache_sync(void) |
| 83 | { | 64 | { |
| 84 | void __iomem *base = __io_address(UX500_L2CC_BASE); | 65 | void __iomem *base = l2x0_base; |
| 66 | |||
| 85 | writel_relaxed(0, base + L2X0_CACHE_SYNC); | 67 | writel_relaxed(0, base + L2X0_CACHE_SYNC); |
| 86 | ux500_cache_wait(base + L2X0_CACHE_SYNC, 1); | 68 | ux500_cache_wait(base + L2X0_CACHE_SYNC, 1); |
| 87 | } | 69 | } |
| @@ -103,20 +85,23 @@ static void ux500_l2x0_disable(void) | |||
| 103 | */ | 85 | */ |
| 104 | static void ux500_l2x0_inv_all(void) | 86 | static void ux500_l2x0_inv_all(void) |
| 105 | { | 87 | { |
| 106 | void __iomem *l2x0_base = __io_address(UX500_L2CC_BASE); | 88 | void __iomem *base = l2x0_base; |
| 107 | uint32_t l2x0_way_mask = (1<<16) - 1; /* Bitmask of active ways */ | 89 | uint32_t l2x0_way_mask = (1<<16) - 1; /* Bitmask of active ways */ |
| 108 | 90 | ||
| 109 | /* invalidate all ways */ | 91 | /* invalidate all ways */ |
| 110 | writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY); | 92 | writel_relaxed(l2x0_way_mask, base + L2X0_INV_WAY); |
| 111 | ux500_cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask); | 93 | ux500_cache_wait(base + L2X0_INV_WAY, l2x0_way_mask); |
| 112 | ux500_cache_sync(); | 94 | ux500_cache_sync(); |
| 113 | } | 95 | } |
| 114 | 96 | ||
| 115 | static int ux500_l2x0_init(void) | 97 | static int ux500_l2x0_init(void) |
| 116 | { | 98 | { |
| 117 | void __iomem *l2x0_base; | 99 | if (cpu_is_u5500()) |
| 118 | 100 | l2x0_base = __io_address(U5500_L2CC_BASE); | |
| 119 | l2x0_base = __io_address(UX500_L2CC_BASE); | 101 | else if (cpu_is_u8500()) |
| 102 | l2x0_base = __io_address(U8500_L2CC_BASE); | ||
| 103 | else | ||
| 104 | ux500_unknown_soc(); | ||
| 120 | 105 | ||
| 121 | /* 64KB way size, 8 way associativity, force WA */ | 106 | /* 64KB way size, 8 way associativity, force WA */ |
| 122 | l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff); | 107 | l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff); |
| @@ -134,13 +119,21 @@ static void __init ux500_timer_init(void) | |||
| 134 | { | 119 | { |
| 135 | #ifdef CONFIG_LOCAL_TIMERS | 120 | #ifdef CONFIG_LOCAL_TIMERS |
| 136 | /* Setup the local timer base */ | 121 | /* Setup the local timer base */ |
| 137 | twd_base = __io_address(UX500_TWD_BASE); | 122 | if (cpu_is_u5500()) |
| 123 | twd_base = __io_address(U5500_TWD_BASE); | ||
| 124 | else if (cpu_is_u8500()) | ||
| 125 | twd_base = __io_address(U8500_TWD_BASE); | ||
| 126 | else | ||
| 127 | ux500_unknown_soc(); | ||
| 138 | #endif | 128 | #endif |
| 139 | /* Setup the MTU base */ | 129 | if (cpu_is_u5500()) |
| 140 | if (cpu_is_u8500ed()) | 130 | mtu_base = __io_address(U5500_MTU0_BASE); |
| 131 | else if (cpu_is_u8500ed()) | ||
| 141 | mtu_base = __io_address(U8500_MTU0_BASE_ED); | 132 | mtu_base = __io_address(U8500_MTU0_BASE_ED); |
| 133 | else if (cpu_is_u8500()) | ||
| 134 | mtu_base = __io_address(U8500_MTU0_BASE); | ||
| 142 | else | 135 | else |
| 143 | mtu_base = __io_address(UX500_MTU0_BASE); | 136 | ux500_unknown_soc(); |
| 144 | 137 | ||
| 145 | nmdk_timer_init(); | 138 | nmdk_timer_init(); |
| 146 | } | 139 | } |
diff --git a/arch/arm/mach-ux500/cpufreq.c b/arch/arm/mach-ux500/cpufreq.c new file mode 100644 index 000000000000..5c5b747f134d --- /dev/null +++ b/arch/arm/mach-ux500/cpufreq.c | |||
| @@ -0,0 +1,211 @@ | |||
| 1 | /* | ||
| 2 | * CPU frequency scaling for u8500 | ||
| 3 | * Inspired by linux/arch/arm/mach-davinci/cpufreq.c | ||
| 4 | * | ||
| 5 | * Copyright (C) STMicroelectronics 2009 | ||
| 6 | * Copyright (C) ST-Ericsson SA 2010 | ||
| 7 | * | ||
| 8 | * License Terms: GNU General Public License v2 | ||
| 9 | * | ||
| 10 | * Author: Sundar Iyer <sundar.iyer@stericsson.com> | ||
| 11 | * Author: Martin Persson <martin.persson@stericsson.com> | ||
| 12 | * Author: Jonas Aaberg <jonas.aberg@stericsson.com> | ||
| 13 | * | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <linux/kernel.h> | ||
| 18 | #include <linux/cpufreq.h> | ||
| 19 | #include <linux/delay.h> | ||
| 20 | |||
| 21 | #include <mach/hardware.h> | ||
| 22 | #include <mach/prcmu.h> | ||
| 23 | #include <mach/prcmu-defs.h> | ||
| 24 | |||
| 25 | #define DRIVER_NAME "cpufreq-u8500" | ||
| 26 | #define CPUFREQ_NAME "u8500" | ||
| 27 | |||
| 28 | static struct device *dev; | ||
| 29 | |||
| 30 | static struct cpufreq_frequency_table freq_table[] = { | ||
| 31 | [0] = { | ||
| 32 | .index = 0, | ||
| 33 | .frequency = 200000, | ||
| 34 | }, | ||
| 35 | [1] = { | ||
| 36 | .index = 1, | ||
| 37 | .frequency = 300000, | ||
| 38 | }, | ||
| 39 | [2] = { | ||
| 40 | .index = 2, | ||
| 41 | .frequency = 600000, | ||
| 42 | }, | ||
| 43 | [3] = { | ||
| 44 | /* Used for CPU_OPP_MAX, if available */ | ||
| 45 | .index = 3, | ||
| 46 | .frequency = CPUFREQ_TABLE_END, | ||
| 47 | }, | ||
| 48 | [4] = { | ||
| 49 | .index = 4, | ||
| 50 | .frequency = CPUFREQ_TABLE_END, | ||
| 51 | }, | ||
| 52 | }; | ||
| 53 | |||
| 54 | static enum prcmu_cpu_opp index2opp[] = { | ||
| 55 | CPU_OPP_EXT_CLK, | ||
| 56 | CPU_OPP_50, | ||
| 57 | CPU_OPP_100, | ||
| 58 | CPU_OPP_MAX | ||
| 59 | }; | ||
| 60 | |||
| 61 | static int u8500_cpufreq_verify_speed(struct cpufreq_policy *policy) | ||
| 62 | { | ||
| 63 | return cpufreq_frequency_table_verify(policy, freq_table); | ||
| 64 | } | ||
| 65 | |||
| 66 | static int u8500_cpufreq_target(struct cpufreq_policy *policy, | ||
| 67 | unsigned int target_freq, | ||
| 68 | unsigned int relation) | ||
| 69 | { | ||
| 70 | struct cpufreq_freqs freqs; | ||
| 71 | unsigned int index; | ||
| 72 | int ret = 0; | ||
| 73 | |||
| 74 | /* | ||
| 75 | * Ensure desired rate is within allowed range. Some govenors | ||
| 76 | * (ondemand) will just pass target_freq=0 to get the minimum. | ||
| 77 | */ | ||
| 78 | if (target_freq < policy->cpuinfo.min_freq) | ||
| 79 | target_freq = policy->cpuinfo.min_freq; | ||
| 80 | if (target_freq > policy->cpuinfo.max_freq) | ||
| 81 | target_freq = policy->cpuinfo.max_freq; | ||
| 82 | |||
| 83 | ret = cpufreq_frequency_table_target(policy, freq_table, | ||
| 84 | target_freq, relation, &index); | ||
| 85 | if (ret < 0) { | ||
| 86 | dev_err(dev, "Could not look up next frequency\n"); | ||
| 87 | return ret; | ||
| 88 | } | ||
| 89 | |||
| 90 | freqs.old = policy->cur; | ||
| 91 | freqs.new = freq_table[index].frequency; | ||
| 92 | freqs.cpu = policy->cpu; | ||
| 93 | |||
| 94 | if (freqs.old == freqs.new) { | ||
| 95 | dev_dbg(dev, "Current and target frequencies are equal\n"); | ||
| 96 | return 0; | ||
| 97 | } | ||
| 98 | |||
| 99 | dev_dbg(dev, "transition: %u --> %u\n", freqs.old, freqs.new); | ||
| 100 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); | ||
| 101 | |||
| 102 | ret = prcmu_set_cpu_opp(index2opp[index]); | ||
| 103 | if (ret < 0) { | ||
| 104 | dev_err(dev, "Failed to set OPP level\n"); | ||
| 105 | return ret; | ||
| 106 | } | ||
| 107 | |||
| 108 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | ||
| 109 | |||
| 110 | return ret; | ||
| 111 | } | ||
| 112 | |||
| 113 | static unsigned int u8500_cpufreq_getspeed(unsigned int cpu) | ||
| 114 | { | ||
| 115 | int i; | ||
| 116 | |||
| 117 | for (i = 0; prcmu_get_cpu_opp() != index2opp[i]; i++) | ||
| 118 | ; | ||
| 119 | return freq_table[i].frequency; | ||
| 120 | } | ||
| 121 | |||
| 122 | static int __cpuinit u8500_cpu_init(struct cpufreq_policy *policy) | ||
| 123 | { | ||
| 124 | int res; | ||
| 125 | |||
| 126 | BUILD_BUG_ON(ARRAY_SIZE(index2opp) + 1 != ARRAY_SIZE(freq_table)); | ||
| 127 | |||
| 128 | if (cpu_is_u8500v2()) { | ||
| 129 | freq_table[1].frequency = 400000; | ||
| 130 | freq_table[2].frequency = 800000; | ||
| 131 | if (prcmu_has_arm_maxopp()) | ||
| 132 | freq_table[3].frequency = 1000000; | ||
| 133 | } | ||
| 134 | |||
| 135 | /* get policy fields based on the table */ | ||
| 136 | res = cpufreq_frequency_table_cpuinfo(policy, freq_table); | ||
| 137 | if (!res) | ||
| 138 | cpufreq_frequency_table_get_attr(freq_table, policy->cpu); | ||
| 139 | else { | ||
| 140 | dev_err(dev, "u8500-cpufreq : Failed to read policy table\n"); | ||
| 141 | return res; | ||
| 142 | } | ||
| 143 | |||
| 144 | policy->min = policy->cpuinfo.min_freq; | ||
| 145 | policy->max = policy->cpuinfo.max_freq; | ||
| 146 | policy->cur = u8500_cpufreq_getspeed(policy->cpu); | ||
| 147 | policy->governor = CPUFREQ_DEFAULT_GOVERNOR; | ||
| 148 | |||
| 149 | /* | ||
| 150 | * FIXME : Need to take time measurement across the target() | ||
| 151 | * function with no/some/all drivers in the notification | ||
| 152 | * list. | ||
| 153 | */ | ||
| 154 | policy->cpuinfo.transition_latency = 200 * 1000; /* in ns */ | ||
| 155 | |||
| 156 | /* policy sharing between dual CPUs */ | ||
| 157 | cpumask_copy(policy->cpus, &cpu_present_map); | ||
| 158 | |||
| 159 | policy->shared_type = CPUFREQ_SHARED_TYPE_ALL; | ||
| 160 | |||
| 161 | return res; | ||
| 162 | } | ||
| 163 | |||
| 164 | static struct freq_attr *u8500_cpufreq_attr[] = { | ||
| 165 | &cpufreq_freq_attr_scaling_available_freqs, | ||
| 166 | NULL, | ||
| 167 | }; | ||
| 168 | static int u8500_cpu_exit(struct cpufreq_policy *policy) | ||
| 169 | { | ||
| 170 | cpufreq_frequency_table_put_attr(policy->cpu); | ||
| 171 | return 0; | ||
| 172 | } | ||
| 173 | |||
| 174 | static struct cpufreq_driver u8500_driver = { | ||
| 175 | .owner = THIS_MODULE, | ||
| 176 | .flags = CPUFREQ_STICKY, | ||
| 177 | .verify = u8500_cpufreq_verify_speed, | ||
| 178 | .target = u8500_cpufreq_target, | ||
| 179 | .get = u8500_cpufreq_getspeed, | ||
| 180 | .init = u8500_cpu_init, | ||
| 181 | .exit = u8500_cpu_exit, | ||
| 182 | .name = CPUFREQ_NAME, | ||
| 183 | .attr = u8500_cpufreq_attr, | ||
| 184 | }; | ||
| 185 | |||
| 186 | static int __init u8500_cpufreq_probe(struct platform_device *pdev) | ||
| 187 | { | ||
| 188 | dev = &pdev->dev; | ||
| 189 | return cpufreq_register_driver(&u8500_driver); | ||
| 190 | } | ||
| 191 | |||
| 192 | static int __exit u8500_cpufreq_remove(struct platform_device *pdev) | ||
| 193 | { | ||
| 194 | return cpufreq_unregister_driver(&u8500_driver); | ||
| 195 | } | ||
| 196 | |||
| 197 | static struct platform_driver u8500_cpufreq_driver = { | ||
| 198 | .driver = { | ||
| 199 | .name = DRIVER_NAME, | ||
| 200 | .owner = THIS_MODULE, | ||
| 201 | }, | ||
| 202 | .remove = __exit_p(u8500_cpufreq_remove), | ||
| 203 | }; | ||
| 204 | |||
| 205 | static int __init u8500_cpufreq_init(void) | ||
| 206 | { | ||
| 207 | return platform_driver_probe(&u8500_cpufreq_driver, | ||
| 208 | &u8500_cpufreq_probe); | ||
| 209 | } | ||
| 210 | |||
| 211 | device_initcall(u8500_cpufreq_init); | ||
diff --git a/arch/arm/mach-ux500/devices-common.c b/arch/arm/mach-ux500/devices-common.c new file mode 100644 index 000000000000..fe69f5fac1bb --- /dev/null +++ b/arch/arm/mach-ux500/devices-common.c | |||
| @@ -0,0 +1,145 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) ST-Ericsson SA 2010 | ||
| 3 | * | ||
| 4 | * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson | ||
| 5 | * License terms: GNU General Public License (GPL), version 2. | ||
| 6 | */ | ||
| 7 | |||
| 8 | #include <linux/kernel.h> | ||
| 9 | #include <linux/dma-mapping.h> | ||
| 10 | #include <linux/err.h> | ||
| 11 | #include <linux/irq.h> | ||
| 12 | #include <linux/slab.h> | ||
| 13 | #include <linux/platform_device.h> | ||
| 14 | #include <linux/amba/bus.h> | ||
| 15 | |||
| 16 | #include <plat/gpio.h> | ||
| 17 | |||
| 18 | #include <mach/hardware.h> | ||
| 19 | |||
| 20 | #include "devices-common.h" | ||
| 21 | |||
| 22 | struct amba_device * | ||
| 23 | dbx500_add_amba_device(const char *name, resource_size_t base, | ||
| 24 | int irq, void *pdata, unsigned int periphid) | ||
| 25 | { | ||
| 26 | struct amba_device *dev; | ||
| 27 | int ret; | ||
| 28 | |||
| 29 | dev = kzalloc(sizeof *dev, GFP_KERNEL); | ||
| 30 | if (!dev) | ||
| 31 | return ERR_PTR(-ENOMEM); | ||
| 32 | |||
| 33 | dev->dev.init_name = name; | ||
| 34 | |||
| 35 | dev->res.start = base; | ||
| 36 | dev->res.end = base + SZ_4K - 1; | ||
| 37 | dev->res.flags = IORESOURCE_MEM; | ||
| 38 | |||
| 39 | dev->dma_mask = DMA_BIT_MASK(32); | ||
| 40 | dev->dev.coherent_dma_mask = DMA_BIT_MASK(32); | ||
| 41 | |||
| 42 | dev->irq[0] = irq; | ||
| 43 | dev->irq[1] = NO_IRQ; | ||
| 44 | |||
| 45 | dev->periphid = periphid; | ||
| 46 | |||
| 47 | dev->dev.platform_data = pdata; | ||
| 48 | |||
| 49 | ret = amba_device_register(dev, &iomem_resource); | ||
| 50 | if (ret) { | ||
| 51 | kfree(dev); | ||
| 52 | return ERR_PTR(ret); | ||
| 53 | } | ||
| 54 | |||
| 55 | return dev; | ||
| 56 | } | ||
| 57 | |||
| 58 | static struct platform_device * | ||
| 59 | dbx500_add_platform_device(const char *name, int id, void *pdata, | ||
| 60 | struct resource *res, int resnum) | ||
| 61 | { | ||
| 62 | struct platform_device *dev; | ||
| 63 | int ret; | ||
| 64 | |||
| 65 | dev = platform_device_alloc(name, id); | ||
| 66 | if (!dev) | ||
| 67 | return ERR_PTR(-ENOMEM); | ||
| 68 | |||
| 69 | dev->dev.coherent_dma_mask = DMA_BIT_MASK(32); | ||
| 70 | dev->dev.dma_mask = &dev->dev.coherent_dma_mask; | ||
| 71 | |||
| 72 | ret = platform_device_add_resources(dev, res, resnum); | ||
| 73 | if (ret) | ||
| 74 | goto out_free; | ||
| 75 | |||
| 76 | dev->dev.platform_data = pdata; | ||
| 77 | |||
| 78 | ret = platform_device_add(dev); | ||
| 79 | if (ret) | ||
| 80 | goto out_free; | ||
| 81 | |||
| 82 | return dev; | ||
| 83 | |||
| 84 | out_free: | ||
| 85 | platform_device_put(dev); | ||
| 86 | return ERR_PTR(ret); | ||
| 87 | } | ||
| 88 | |||
| 89 | struct platform_device * | ||
| 90 | dbx500_add_platform_device_4k1irq(const char *name, int id, | ||
| 91 | resource_size_t base, | ||
| 92 | int irq, void *pdata) | ||
| 93 | { | ||
| 94 | struct resource resources[] = { | ||
| 95 | [0] = { | ||
| 96 | .start = base, | ||
| 97 | .end = base + SZ_4K - 1, | ||
| 98 | .flags = IORESOURCE_MEM, | ||
| 99 | }, | ||
| 100 | [1] = { | ||
| 101 | .start = irq, | ||
| 102 | .end = irq, | ||
| 103 | .flags = IORESOURCE_IRQ, | ||
| 104 | } | ||
| 105 | }; | ||
| 106 | |||
| 107 | return dbx500_add_platform_device(name, id, pdata, resources, | ||
| 108 | ARRAY_SIZE(resources)); | ||
| 109 | } | ||
| 110 | |||
| 111 | static struct platform_device * | ||
| 112 | dbx500_add_gpio(int id, resource_size_t addr, int irq, | ||
| 113 | struct nmk_gpio_platform_data *pdata) | ||
| 114 | { | ||
| 115 | struct resource resources[] = { | ||
| 116 | { | ||
| 117 | .start = addr, | ||
| 118 | .end = addr + 127, | ||
| 119 | .flags = IORESOURCE_MEM, | ||
| 120 | }, | ||
| 121 | { | ||
| 122 | .start = irq, | ||
| 123 | .end = irq, | ||
| 124 | .flags = IORESOURCE_IRQ, | ||
| 125 | } | ||
| 126 | }; | ||
| 127 | |||
| 128 | return platform_device_register_resndata(NULL, "gpio", id, | ||
| 129 | resources, ARRAY_SIZE(resources), | ||
| 130 | pdata, sizeof(*pdata)); | ||
| 131 | } | ||
| 132 | |||
| 133 | void dbx500_add_gpios(resource_size_t *base, int num, int irq, | ||
| 134 | struct nmk_gpio_platform_data *pdata) | ||
| 135 | { | ||
| 136 | int first = 0; | ||
| 137 | int i; | ||
| 138 | |||
| 139 | for (i = 0; i < num; i++, first += 32, irq++) { | ||
| 140 | pdata->first_gpio = first; | ||
| 141 | pdata->first_irq = NOMADIK_GPIO_TO_IRQ(first); | ||
| 142 | |||
| 143 | dbx500_add_gpio(i, base[i], irq, pdata); | ||
| 144 | } | ||
| 145 | } | ||
diff --git a/arch/arm/mach-ux500/devices-common.h b/arch/arm/mach-ux500/devices-common.h new file mode 100644 index 000000000000..cbadc117d2db --- /dev/null +++ b/arch/arm/mach-ux500/devices-common.h | |||
| @@ -0,0 +1,82 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) ST-Ericsson SA 2010 | ||
| 3 | * | ||
| 4 | * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson | ||
| 5 | * License terms: GNU General Public License (GPL), version 2. | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifndef __DEVICES_COMMON_H | ||
| 9 | #define __DEVICES_COMMON_H | ||
| 10 | |||
| 11 | extern struct amba_device * | ||
| 12 | dbx500_add_amba_device(const char *name, resource_size_t base, | ||
| 13 | int irq, void *pdata, unsigned int periphid); | ||
| 14 | |||
| 15 | extern struct platform_device * | ||
| 16 | dbx500_add_platform_device_4k1irq(const char *name, int id, | ||
| 17 | resource_size_t base, | ||
| 18 | int irq, void *pdata); | ||
| 19 | |||
| 20 | struct spi_master_cntlr; | ||
| 21 | |||
| 22 | static inline struct amba_device * | ||
| 23 | dbx500_add_msp_spi(const char *name, resource_size_t base, int irq, | ||
| 24 | struct spi_master_cntlr *pdata) | ||
| 25 | { | ||
| 26 | return dbx500_add_amba_device(name, base, irq, pdata, 0); | ||
| 27 | } | ||
| 28 | |||
| 29 | static inline struct amba_device * | ||
| 30 | dbx500_add_spi(const char *name, resource_size_t base, int irq, | ||
| 31 | struct spi_master_cntlr *pdata) | ||
| 32 | { | ||
| 33 | return dbx500_add_amba_device(name, base, irq, pdata, 0); | ||
| 34 | } | ||
| 35 | |||
| 36 | struct mmci_platform_data; | ||
| 37 | |||
| 38 | static inline struct amba_device * | ||
| 39 | dbx500_add_sdi(const char *name, resource_size_t base, int irq, | ||
| 40 | struct mmci_platform_data *pdata) | ||
| 41 | { | ||
| 42 | return dbx500_add_amba_device(name, base, irq, pdata, 0); | ||
| 43 | } | ||
| 44 | |||
| 45 | static inline struct amba_device * | ||
| 46 | dbx500_add_uart(const char *name, resource_size_t base, int irq) | ||
| 47 | { | ||
| 48 | return dbx500_add_amba_device(name, base, irq, NULL, 0); | ||
| 49 | } | ||
| 50 | |||
| 51 | struct nmk_i2c_controller; | ||
| 52 | |||
| 53 | static inline struct platform_device * | ||
| 54 | dbx500_add_i2c(int id, resource_size_t base, int irq, | ||
| 55 | struct nmk_i2c_controller *pdata) | ||
| 56 | { | ||
| 57 | return dbx500_add_platform_device_4k1irq("nmk-i2c", id, base, irq, | ||
| 58 | pdata); | ||
| 59 | } | ||
| 60 | |||
| 61 | struct msp_i2s_platform_data; | ||
| 62 | |||
| 63 | static inline struct platform_device * | ||
| 64 | dbx500_add_msp_i2s(int id, resource_size_t base, int irq, | ||
| 65 | struct msp_i2s_platform_data *pdata) | ||
| 66 | { | ||
| 67 | return dbx500_add_platform_device_4k1irq("MSP_I2S", id, base, irq, | ||
| 68 | pdata); | ||
| 69 | } | ||
| 70 | |||
| 71 | static inline struct amba_device * | ||
| 72 | dbx500_add_rtc(resource_size_t base, int irq) | ||
| 73 | { | ||
| 74 | return dbx500_add_amba_device("rtc-pl031", base, irq, NULL, 0); | ||
| 75 | } | ||
| 76 | |||
| 77 | struct nmk_gpio_platform_data; | ||
| 78 | |||
| 79 | void dbx500_add_gpios(resource_size_t *base, int num, int irq, | ||
| 80 | struct nmk_gpio_platform_data *pdata); | ||
| 81 | |||
| 82 | #endif | ||
diff --git a/arch/arm/mach-ux500/devices-db5500.c b/arch/arm/mach-ux500/devices-db5500.c deleted file mode 100644 index 33e5b56bebb6..000000000000 --- a/arch/arm/mach-ux500/devices-db5500.c +++ /dev/null | |||
| @@ -1,46 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) ST-Ericsson SA 2010 | ||
| 3 | * | ||
| 4 | * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson | ||
| 5 | * License terms: GNU General Public License (GPL) version 2 | ||
| 6 | */ | ||
| 7 | |||
| 8 | #include <linux/platform_device.h> | ||
| 9 | #include <linux/interrupt.h> | ||
| 10 | #include <linux/gpio.h> | ||
| 11 | |||
| 12 | #include <mach/hardware.h> | ||
| 13 | #include <mach/devices.h> | ||
| 14 | |||
| 15 | static struct nmk_gpio_platform_data u5500_gpio_data[] = { | ||
| 16 | GPIO_DATA("GPIO-0-31", 0), | ||
| 17 | GPIO_DATA("GPIO-32-63", 32), /* 36..63 not routed to pin */ | ||
| 18 | GPIO_DATA("GPIO-64-95", 64), /* 83..95 not routed to pin */ | ||
| 19 | GPIO_DATA("GPIO-96-127", 96), /* 102..127 not routed to pin */ | ||
| 20 | GPIO_DATA("GPIO-128-159", 128), /* 149..159 not routed to pin */ | ||
| 21 | GPIO_DATA("GPIO-160-191", 160), | ||
| 22 | GPIO_DATA("GPIO-192-223", 192), | ||
| 23 | GPIO_DATA("GPIO-224-255", 224), /* 228..255 not routed to pin */ | ||
| 24 | }; | ||
| 25 | |||
| 26 | static struct resource u5500_gpio_resources[] = { | ||
| 27 | GPIO_RESOURCE(0), | ||
| 28 | GPIO_RESOURCE(1), | ||
| 29 | GPIO_RESOURCE(2), | ||
| 30 | GPIO_RESOURCE(3), | ||
| 31 | GPIO_RESOURCE(4), | ||
| 32 | GPIO_RESOURCE(5), | ||
| 33 | GPIO_RESOURCE(6), | ||
| 34 | GPIO_RESOURCE(7), | ||
| 35 | }; | ||
| 36 | |||
| 37 | struct platform_device u5500_gpio_devs[] = { | ||
| 38 | GPIO_DEVICE(0), | ||
| 39 | GPIO_DEVICE(1), | ||
| 40 | GPIO_DEVICE(2), | ||
| 41 | GPIO_DEVICE(3), | ||
| 42 | GPIO_DEVICE(4), | ||
| 43 | GPIO_DEVICE(5), | ||
| 44 | GPIO_DEVICE(6), | ||
| 45 | GPIO_DEVICE(7), | ||
| 46 | }; | ||
diff --git a/arch/arm/mach-ux500/devices-db5500.h b/arch/arm/mach-ux500/devices-db5500.h new file mode 100644 index 000000000000..c8d7901c1f2d --- /dev/null +++ b/arch/arm/mach-ux500/devices-db5500.h | |||
| @@ -0,0 +1,66 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) ST-Ericsson SA 2010 | ||
| 3 | * | ||
| 4 | * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson | ||
| 5 | * License terms: GNU General Public License (GPL), version 2. | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifndef __DEVICES_DB5500_H | ||
| 9 | #define __DEVICES_DB5500_H | ||
| 10 | |||
| 11 | #include "devices-common.h" | ||
| 12 | |||
| 13 | #define db5500_add_i2c1(pdata) \ | ||
| 14 | dbx500_add_i2c(1, U5500_I2C1_BASE, IRQ_DB5500_I2C1, pdata) | ||
| 15 | #define db5500_add_i2c2(pdata) \ | ||
| 16 | dbx500_add_i2c(2, U5500_I2C2_BASE, IRQ_DB5500_I2C2, pdata) | ||
| 17 | #define db5500_add_i2c3(pdata) \ | ||
| 18 | dbx500_add_i2c(3, U5500_I2C3_BASE, IRQ_DB5500_I2C3, pdata) | ||
| 19 | |||
| 20 | #define db5500_add_msp0_i2s(pdata) \ | ||
| 21 | dbx500_add_msp_i2s(0, U5500_MSP0_BASE, IRQ_DB5500_MSP0, pdata) | ||
| 22 | #define db5500_add_msp1_i2s(pdata) \ | ||
| 23 | dbx500_add_msp_i2s(1, U5500_MSP1_BASE, IRQ_DB5500_MSP1, pdata) | ||
| 24 | #define db5500_add_msp2_i2s(pdata) \ | ||
| 25 | dbx500_add_msp_i2s(2, U5500_MSP2_BASE, IRQ_DB5500_MSP2, pdata) | ||
| 26 | |||
| 27 | #define db5500_add_msp0_spi(pdata) \ | ||
| 28 | dbx500_add_msp_spi("msp0", U5500_MSP0_BASE, IRQ_DB5500_MSP0, pdata) | ||
| 29 | #define db5500_add_msp1_spi(pdata) \ | ||
| 30 | dbx500_add_msp_spi("msp1", U5500_MSP1_BASE, IRQ_DB5500_MSP1, pdata) | ||
| 31 | #define db5500_add_msp2_spi(pdata) \ | ||
| 32 | dbx500_add_msp_spi("msp2", U5500_MSP2_BASE, IRQ_DB5500_MSP2, pdata) | ||
| 33 | |||
| 34 | #define db5500_add_rtc() \ | ||
| 35 | dbx500_add_rtc(U5500_RTC_BASE, IRQ_DB5500_RTC); | ||
| 36 | |||
| 37 | #define db5500_add_sdi0(pdata) \ | ||
| 38 | dbx500_add_sdi("sdi0", U5500_SDI0_BASE, IRQ_DB5500_SDMMC0, pdata) | ||
| 39 | #define db5500_add_sdi1(pdata) \ | ||
| 40 | dbx500_add_sdi("sdi1", U5500_SDI1_BASE, IRQ_DB5500_SDMMC1, pdata) | ||
| 41 | #define db5500_add_sdi2(pdata) \ | ||
| 42 | dbx500_add_sdi("sdi2", U5500_SDI2_BASE, IRQ_DB5500_SDMMC2, pdata) | ||
| 43 | #define db5500_add_sdi3(pdata) \ | ||
| 44 | dbx500_add_sdi("sdi3", U5500_SDI3_BASE, IRQ_DB5500_SDMMC3, pdata) | ||
| 45 | #define db5500_add_sdi4(pdata) \ | ||
| 46 | dbx500_add_sdi("sdi4", U5500_SDI4_BASE, IRQ_DB5500_SDMMC4, pdata) | ||
| 47 | |||
| 48 | #define db5500_add_spi0(pdata) \ | ||
| 49 | dbx500_add_spi("spi0", U5500_SPI0_BASE, IRQ_DB5500_SPI0, pdata) | ||
| 50 | #define db5500_add_spi1(pdata) \ | ||
| 51 | dbx500_add_spi("spi1", U5500_SPI1_BASE, IRQ_DB5500_SPI1, pdata) | ||
| 52 | #define db5500_add_spi2(pdata) \ | ||
| 53 | dbx500_add_spi("spi2", U5500_SPI2_BASE, IRQ_DB5500_SPI2, pdata) | ||
| 54 | #define db5500_add_spi3(pdata) \ | ||
| 55 | dbx500_add_spi("spi3", U5500_SPI3_BASE, IRQ_DB5500_SPI3, pdata) | ||
| 56 | |||
| 57 | #define db5500_add_uart0() \ | ||
| 58 | dbx500_add_uart("uart0", U5500_UART0_BASE, IRQ_DB5500_UART0) | ||
| 59 | #define db5500_add_uart1() \ | ||
| 60 | dbx500_add_uart("uart1", U5500_UART1_BASE, IRQ_DB5500_UART1) | ||
| 61 | #define db5500_add_uart2() \ | ||
| 62 | dbx500_add_uart("uart2", U5500_UART2_BASE, IRQ_DB5500_UART2) | ||
| 63 | #define db5500_add_uart3() \ | ||
| 64 | dbx500_add_uart("uart3", U5500_UART3_BASE, IRQ_DB5500_UART3) | ||
| 65 | |||
| 66 | #endif | ||
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c index 4a94be3304b9..23c695d54977 100644 --- a/arch/arm/mach-ux500/devices-db8500.c +++ b/arch/arm/mach-ux500/devices-db8500.c | |||
| @@ -19,173 +19,6 @@ | |||
| 19 | 19 | ||
| 20 | #include "ste-dma40-db8500.h" | 20 | #include "ste-dma40-db8500.h" |
| 21 | 21 | ||
| 22 | static struct nmk_gpio_platform_data u8500_gpio_data[] = { | ||
| 23 | GPIO_DATA("GPIO-0-31", 0), | ||
| 24 | GPIO_DATA("GPIO-32-63", 32), /* 37..63 not routed to pin */ | ||
| 25 | GPIO_DATA("GPIO-64-95", 64), | ||
| 26 | GPIO_DATA("GPIO-96-127", 96), /* 98..127 not routed to pin */ | ||
| 27 | GPIO_DATA("GPIO-128-159", 128), | ||
| 28 | GPIO_DATA("GPIO-160-191", 160), /* 172..191 not routed to pin */ | ||
| 29 | GPIO_DATA("GPIO-192-223", 192), | ||
| 30 | GPIO_DATA("GPIO-224-255", 224), /* 231..255 not routed to pin */ | ||
| 31 | GPIO_DATA("GPIO-256-288", 256), /* 268..288 not routed to pin */ | ||
| 32 | }; | ||
| 33 | |||
| 34 | static struct resource u8500_gpio_resources[] = { | ||
| 35 | GPIO_RESOURCE(0), | ||
| 36 | GPIO_RESOURCE(1), | ||
| 37 | GPIO_RESOURCE(2), | ||
| 38 | GPIO_RESOURCE(3), | ||
| 39 | GPIO_RESOURCE(4), | ||
| 40 | GPIO_RESOURCE(5), | ||
| 41 | GPIO_RESOURCE(6), | ||
| 42 | GPIO_RESOURCE(7), | ||
| 43 | GPIO_RESOURCE(8), | ||
| 44 | }; | ||
| 45 | |||
| 46 | struct platform_device u8500_gpio_devs[] = { | ||
| 47 | GPIO_DEVICE(0), | ||
| 48 | GPIO_DEVICE(1), | ||
| 49 | GPIO_DEVICE(2), | ||
| 50 | GPIO_DEVICE(3), | ||
| 51 | GPIO_DEVICE(4), | ||
| 52 | GPIO_DEVICE(5), | ||
| 53 | GPIO_DEVICE(6), | ||
| 54 | GPIO_DEVICE(7), | ||
| 55 | GPIO_DEVICE(8), | ||
| 56 | }; | ||
| 57 | |||
| 58 | struct amba_device u8500_ssp0_device = { | ||
| 59 | .dev = { | ||
| 60 | .coherent_dma_mask = ~0, | ||
| 61 | .init_name = "ssp0", | ||
| 62 | }, | ||
| 63 | .res = { | ||
| 64 | .start = U8500_SSP0_BASE, | ||
| 65 | .end = U8500_SSP0_BASE + SZ_4K - 1, | ||
| 66 | .flags = IORESOURCE_MEM, | ||
| 67 | }, | ||
| 68 | .irq = {IRQ_DB8500_SSP0, NO_IRQ }, | ||
| 69 | /* ST-Ericsson modified id */ | ||
| 70 | .periphid = SSP_PER_ID, | ||
| 71 | }; | ||
| 72 | |||
| 73 | static struct resource u8500_i2c0_resources[] = { | ||
| 74 | [0] = { | ||
| 75 | .start = U8500_I2C0_BASE, | ||
| 76 | .end = U8500_I2C0_BASE + SZ_4K - 1, | ||
| 77 | .flags = IORESOURCE_MEM, | ||
| 78 | }, | ||
| 79 | [1] = { | ||
| 80 | .start = IRQ_DB8500_I2C0, | ||
| 81 | .end = IRQ_DB8500_I2C0, | ||
| 82 | .flags = IORESOURCE_IRQ, | ||
| 83 | } | ||
| 84 | }; | ||
| 85 | |||
| 86 | struct platform_device u8500_i2c0_device = { | ||
| 87 | .name = "nmk-i2c", | ||
| 88 | .id = 0, | ||
| 89 | .resource = u8500_i2c0_resources, | ||
| 90 | .num_resources = ARRAY_SIZE(u8500_i2c0_resources), | ||
| 91 | }; | ||
| 92 | |||
| 93 | static struct resource u8500_i2c4_resources[] = { | ||
| 94 | [0] = { | ||
| 95 | .start = U8500_I2C4_BASE, | ||
| 96 | .end = U8500_I2C4_BASE + SZ_4K - 1, | ||
| 97 | .flags = IORESOURCE_MEM, | ||
| 98 | }, | ||
| 99 | [1] = { | ||
| 100 | .start = IRQ_DB8500_I2C4, | ||
| 101 | .end = IRQ_DB8500_I2C4, | ||
| 102 | .flags = IORESOURCE_IRQ, | ||
| 103 | } | ||
| 104 | }; | ||
| 105 | |||
| 106 | struct platform_device u8500_i2c4_device = { | ||
| 107 | .name = "nmk-i2c", | ||
| 108 | .id = 4, | ||
| 109 | .resource = u8500_i2c4_resources, | ||
| 110 | .num_resources = ARRAY_SIZE(u8500_i2c4_resources), | ||
| 111 | }; | ||
| 112 | |||
| 113 | /* | ||
| 114 | * SD/MMC | ||
| 115 | */ | ||
| 116 | |||
| 117 | struct amba_device u8500_sdi0_device = { | ||
| 118 | .dev = { | ||
| 119 | .init_name = "sdi0", | ||
| 120 | }, | ||
| 121 | .res = { | ||
| 122 | .start = U8500_SDI0_BASE, | ||
| 123 | .end = U8500_SDI0_BASE + SZ_4K - 1, | ||
| 124 | .flags = IORESOURCE_MEM, | ||
| 125 | }, | ||
| 126 | .irq = {IRQ_DB8500_SDMMC0, NO_IRQ}, | ||
| 127 | }; | ||
| 128 | |||
| 129 | struct amba_device u8500_sdi1_device = { | ||
| 130 | .dev = { | ||
| 131 | .init_name = "sdi1", | ||
| 132 | }, | ||
| 133 | .res = { | ||
| 134 | .start = U8500_SDI1_BASE, | ||
| 135 | .end = U8500_SDI1_BASE + SZ_4K - 1, | ||
| 136 | .flags = IORESOURCE_MEM, | ||
| 137 | }, | ||
| 138 | .irq = {IRQ_DB8500_SDMMC1, NO_IRQ}, | ||
| 139 | }; | ||
| 140 | |||
| 141 | struct amba_device u8500_sdi2_device = { | ||
| 142 | .dev = { | ||
| 143 | .init_name = "sdi2", | ||
| 144 | }, | ||
| 145 | .res = { | ||
| 146 | .start = U8500_SDI2_BASE, | ||
| 147 | .end = U8500_SDI2_BASE + SZ_4K - 1, | ||
| 148 | .flags = IORESOURCE_MEM, | ||
| 149 | }, | ||
| 150 | .irq = {IRQ_DB8500_SDMMC2, NO_IRQ}, | ||
| 151 | }; | ||
| 152 | |||
| 153 | struct amba_device u8500_sdi3_device = { | ||
| 154 | .dev = { | ||
| 155 | .init_name = "sdi3", | ||
| 156 | }, | ||
| 157 | .res = { | ||
| 158 | .start = U8500_SDI3_BASE, | ||
| 159 | .end = U8500_SDI3_BASE + SZ_4K - 1, | ||
| 160 | .flags = IORESOURCE_MEM, | ||
| 161 | }, | ||
| 162 | .irq = {IRQ_DB8500_SDMMC3, NO_IRQ}, | ||
| 163 | }; | ||
| 164 | |||
| 165 | struct amba_device u8500_sdi4_device = { | ||
| 166 | .dev = { | ||
| 167 | .init_name = "sdi4", | ||
| 168 | }, | ||
| 169 | .res = { | ||
| 170 | .start = U8500_SDI4_BASE, | ||
| 171 | .end = U8500_SDI4_BASE + SZ_4K - 1, | ||
| 172 | .flags = IORESOURCE_MEM, | ||
| 173 | }, | ||
| 174 | .irq = {IRQ_DB8500_SDMMC4, NO_IRQ}, | ||
| 175 | }; | ||
| 176 | |||
| 177 | struct amba_device u8500_sdi5_device = { | ||
| 178 | .dev = { | ||
| 179 | .init_name = "sdi5", | ||
| 180 | }, | ||
| 181 | .res = { | ||
| 182 | .start = U8500_SDI5_BASE, | ||
| 183 | .end = U8500_SDI5_BASE + SZ_4K - 1, | ||
| 184 | .flags = IORESOURCE_MEM, | ||
| 185 | }, | ||
| 186 | .irq = {IRQ_DB8500_SDMMC5, NO_IRQ}, | ||
| 187 | }; | ||
| 188 | |||
| 189 | static struct resource dma40_resources[] = { | 22 | static struct resource dma40_resources[] = { |
| 190 | [0] = { | 23 | [0] = { |
| 191 | .start = U8500_DMA_BASE, | 24 | .start = U8500_DMA_BASE, |
| @@ -295,7 +128,7 @@ struct resource keypad_resources[] = { | |||
| 295 | }, | 128 | }, |
| 296 | }; | 129 | }; |
| 297 | 130 | ||
| 298 | struct platform_device ux500_ske_keypad_device = { | 131 | struct platform_device u8500_ske_keypad_device = { |
| 299 | .name = "nmk-ske-keypad", | 132 | .name = "nmk-ske-keypad", |
| 300 | .id = -1, | 133 | .id = -1, |
| 301 | .num_resources = ARRAY_SIZE(keypad_resources), | 134 | .num_resources = ARRAY_SIZE(keypad_resources), |
diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h new file mode 100644 index 000000000000..3a770c756979 --- /dev/null +++ b/arch/arm/mach-ux500/devices-db8500.h | |||
| @@ -0,0 +1,98 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) ST-Ericsson SA 2010 | ||
| 3 | * | ||
| 4 | * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson | ||
| 5 | * License terms: GNU General Public License (GPL), version 2. | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifndef __DEVICES_DB8500_H | ||
| 9 | #define __DEVICES_DB8500_H | ||
| 10 | |||
| 11 | #include "devices-common.h" | ||
| 12 | |||
| 13 | struct ske_keypad_platform_data; | ||
| 14 | struct pl022_ssp_controller; | ||
| 15 | |||
| 16 | static inline struct platform_device * | ||
| 17 | db8500_add_ske_keypad(struct ske_keypad_platform_data *pdata) | ||
| 18 | { | ||
| 19 | return dbx500_add_platform_device_4k1irq("nmk-ske-keypad", -1, | ||
| 20 | U8500_SKE_BASE, | ||
| 21 | IRQ_DB8500_KB, pdata); | ||
| 22 | } | ||
| 23 | |||
| 24 | static inline struct amba_device * | ||
| 25 | db8500_add_ssp(const char *name, resource_size_t base, int irq, | ||
| 26 | struct pl022_ssp_controller *pdata) | ||
| 27 | { | ||
| 28 | return dbx500_add_amba_device(name, base, irq, pdata, SSP_PER_ID); | ||
| 29 | } | ||
| 30 | |||
| 31 | |||
| 32 | #define db8500_add_i2c0(pdata) \ | ||
| 33 | dbx500_add_i2c(0, U8500_I2C0_BASE, IRQ_DB8500_I2C0, pdata) | ||
| 34 | #define db8500_add_i2c1(pdata) \ | ||
| 35 | dbx500_add_i2c(1, U8500_I2C1_BASE, IRQ_DB8500_I2C1, pdata) | ||
| 36 | #define db8500_add_i2c2(pdata) \ | ||
| 37 | dbx500_add_i2c(2, U8500_I2C2_BASE, IRQ_DB8500_I2C2, pdata) | ||
| 38 | #define db8500_add_i2c3(pdata) \ | ||
| 39 | dbx500_add_i2c(3, U8500_I2C3_BASE, IRQ_DB8500_I2C3, pdata) | ||
| 40 | #define db8500_add_i2c4(pdata) \ | ||
| 41 | dbx500_add_i2c(4, U8500_I2C4_BASE, IRQ_DB8500_I2C4, pdata) | ||
| 42 | |||
| 43 | #define db8500_add_msp0_i2s(pdata) \ | ||
| 44 | dbx500_add_msp_i2s(0, U8500_MSP0_BASE, IRQ_DB8500_MSP0, pdata) | ||
| 45 | #define db8500_add_msp1_i2s(pdata) \ | ||
| 46 | dbx500_add_msp_i2s(1, U8500_MSP1_BASE, IRQ_DB8500_MSP1, pdata) | ||
| 47 | #define db8500_add_msp2_i2s(pdata) \ | ||
| 48 | dbx500_add_msp_i2s(2, U8500_MSP2_BASE, IRQ_DB8500_MSP2, pdata) | ||
| 49 | #define db8500_add_msp3_i2s(pdata) \ | ||
| 50 | dbx500_add_msp_i2s(3, U8500_MSP3_BASE, IRQ_DB8500_MSP1, pdata) | ||
| 51 | |||
| 52 | #define db8500_add_msp0_spi(pdata) \ | ||
| 53 | dbx500_add_msp_spi("msp0", U8500_MSP0_BASE, IRQ_DB8500_MSP0, pdata) | ||
| 54 | #define db8500_add_msp1_spi(pdata) \ | ||
| 55 | dbx500_add_msp_spi("msp1", U8500_MSP1_BASE, IRQ_DB8500_MSP1, pdata) | ||
| 56 | #define db8500_add_msp2_spi(pdata) \ | ||
| 57 | dbx500_add_msp_spi("msp2", U8500_MSP2_BASE, IRQ_DB8500_MSP2, pdata) | ||
| 58 | #define db8500_add_msp3_spi(pdata) \ | ||
| 59 | dbx500_add_msp_spi("msp3", U8500_MSP3_BASE, IRQ_DB8500_MSP1, pdata) | ||
| 60 | |||
| 61 | #define db8500_add_rtc() \ | ||
| 62 | dbx500_add_rtc(U8500_RTC_BASE, IRQ_DB8500_RTC); | ||
| 63 | |||
| 64 | #define db8500_add_sdi0(pdata) \ | ||
| 65 | dbx500_add_sdi("sdi0", U8500_SDI0_BASE, IRQ_DB8500_SDMMC0, pdata) | ||
| 66 | #define db8500_add_sdi1(pdata) \ | ||
| 67 | dbx500_add_sdi("sdi1", U8500_SDI1_BASE, IRQ_DB8500_SDMMC1, pdata) | ||
| 68 | #define db8500_add_sdi2(pdata) \ | ||
| 69 | dbx500_add_sdi("sdi2", U8500_SDI2_BASE, IRQ_DB8500_SDMMC2, pdata) | ||
| 70 | #define db8500_add_sdi3(pdata) \ | ||
| 71 | dbx500_add_sdi("sdi3", U8500_SDI3_BASE, IRQ_DB8500_SDMMC3, pdata) | ||
| 72 | #define db8500_add_sdi4(pdata) \ | ||
| 73 | dbx500_add_sdi("sdi4", U8500_SDI4_BASE, IRQ_DB8500_SDMMC4, pdata) | ||
| 74 | #define db8500_add_sdi5(pdata) \ | ||
| 75 | dbx500_add_sdi("sdi5", U8500_SDI5_BASE, IRQ_DB8500_SDMMC5, pdata) | ||
| 76 | |||
| 77 | #define db8500_add_ssp0(pdata) \ | ||
| 78 | db8500_add_ssp("ssp0", U8500_SSP0_BASE, IRQ_DB8500_SSP0, pdata) | ||
| 79 | #define db8500_add_ssp1(pdata) \ | ||
| 80 | db8500_add_ssp("ssp1", U8500_SSP1_BASE, IRQ_DB8500_SSP1, pdata) | ||
| 81 | |||
| 82 | #define db8500_add_spi0(pdata) \ | ||
| 83 | dbx500_add_spi("spi0", U8500_SPI0_BASE, IRQ_DB8500_SPI0, pdata) | ||
| 84 | #define db8500_add_spi1(pdata) \ | ||
| 85 | dbx500_add_spi("spi1", U8500_SPI1_BASE, IRQ_DB8500_SPI1, pdata) | ||
| 86 | #define db8500_add_spi2(pdata) \ | ||
| 87 | dbx500_add_spi("spi2", U8500_SPI2_BASE, IRQ_DB8500_SPI2, pdata) | ||
| 88 | #define db8500_add_spi3(pdata) \ | ||
| 89 | dbx500_add_spi("spi3", U8500_SPI3_BASE, IRQ_DB8500_SPI3, pdata) | ||
| 90 | |||
| 91 | #define db8500_add_uart0() \ | ||
| 92 | dbx500_add_uart("uart0", U8500_UART0_BASE, IRQ_DB8500_UART0) | ||
| 93 | #define db8500_add_uart1() \ | ||
| 94 | dbx500_add_uart("uart1", U8500_UART1_BASE, IRQ_DB8500_UART1) | ||
| 95 | #define db8500_add_uart2() \ | ||
| 96 | dbx500_add_uart("uart2", U8500_UART2_BASE, IRQ_DB8500_UART2) | ||
| 97 | |||
| 98 | #endif | ||
diff --git a/arch/arm/mach-ux500/devices.c b/arch/arm/mach-ux500/devices.c index 8a268893cb7f..ea0a2f92ca70 100644 --- a/arch/arm/mach-ux500/devices.c +++ b/arch/arm/mach-ux500/devices.c | |||
| @@ -14,69 +14,6 @@ | |||
| 14 | #include <mach/hardware.h> | 14 | #include <mach/hardware.h> |
| 15 | #include <mach/setup.h> | 15 | #include <mach/setup.h> |
| 16 | 16 | ||
| 17 | #define __MEM_4K_RESOURCE(x) \ | ||
| 18 | .res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM} | ||
| 19 | |||
| 20 | struct amba_device ux500_pl031_device = { | ||
| 21 | .dev = { | ||
| 22 | .init_name = "pl031", | ||
| 23 | }, | ||
| 24 | .res = { | ||
| 25 | .start = UX500_RTC_BASE, | ||
| 26 | .end = UX500_RTC_BASE + SZ_4K - 1, | ||
| 27 | .flags = IORESOURCE_MEM, | ||
| 28 | }, | ||
| 29 | .irq = {IRQ_RTC_RTT, NO_IRQ}, | ||
| 30 | }; | ||
| 31 | |||
| 32 | struct amba_device ux500_uart0_device = { | ||
| 33 | .dev = { .init_name = "uart0" }, | ||
| 34 | __MEM_4K_RESOURCE(UX500_UART0_BASE), | ||
| 35 | .irq = {IRQ_UART0, NO_IRQ}, | ||
| 36 | }; | ||
| 37 | |||
| 38 | struct amba_device ux500_uart1_device = { | ||
| 39 | .dev = { .init_name = "uart1" }, | ||
| 40 | __MEM_4K_RESOURCE(UX500_UART1_BASE), | ||
| 41 | .irq = {IRQ_UART1, NO_IRQ}, | ||
| 42 | }; | ||
| 43 | |||
| 44 | struct amba_device ux500_uart2_device = { | ||
| 45 | .dev = { .init_name = "uart2" }, | ||
| 46 | __MEM_4K_RESOURCE(UX500_UART2_BASE), | ||
| 47 | .irq = {IRQ_UART2, NO_IRQ}, | ||
| 48 | }; | ||
| 49 | |||
| 50 | #define UX500_I2C_RESOURCES(id, size) \ | ||
| 51 | static struct resource ux500_i2c##id##_resources[] = { \ | ||
| 52 | [0] = { \ | ||
| 53 | .start = UX500_I2C##id##_BASE, \ | ||
| 54 | .end = UX500_I2C##id##_BASE + size - 1, \ | ||
| 55 | .flags = IORESOURCE_MEM, \ | ||
| 56 | }, \ | ||
| 57 | [1] = { \ | ||
| 58 | .start = IRQ_I2C##id, \ | ||
| 59 | .end = IRQ_I2C##id, \ | ||
| 60 | .flags = IORESOURCE_IRQ \ | ||
| 61 | } \ | ||
| 62 | } | ||
| 63 | |||
| 64 | UX500_I2C_RESOURCES(1, SZ_4K); | ||
| 65 | UX500_I2C_RESOURCES(2, SZ_4K); | ||
| 66 | UX500_I2C_RESOURCES(3, SZ_4K); | ||
| 67 | |||
| 68 | #define UX500_I2C_PDEVICE(cid) \ | ||
| 69 | struct platform_device ux500_i2c##cid##_device = { \ | ||
| 70 | .name = "nmk-i2c", \ | ||
| 71 | .id = cid, \ | ||
| 72 | .num_resources = 2, \ | ||
| 73 | .resource = ux500_i2c##cid##_resources, \ | ||
| 74 | } | ||
| 75 | |||
| 76 | UX500_I2C_PDEVICE(1); | ||
| 77 | UX500_I2C_PDEVICE(2); | ||
| 78 | UX500_I2C_PDEVICE(3); | ||
| 79 | |||
| 80 | void __init amba_add_devices(struct amba_device *devs[], int num) | 17 | void __init amba_add_devices(struct amba_device *devs[], int num) |
| 81 | { | 18 | { |
| 82 | int i; | 19 | int i; |
diff --git a/arch/arm/mach-ux500/dma-db5500.c b/arch/arm/mach-ux500/dma-db5500.c new file mode 100644 index 000000000000..32a061f8a95b --- /dev/null +++ b/arch/arm/mach-ux500/dma-db5500.c | |||
| @@ -0,0 +1,120 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) ST-Ericsson SA 2010 | ||
| 3 | * | ||
| 4 | * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson | ||
| 5 | * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson | ||
| 6 | * Author: Rabin Vincent <rabinv.vincent@stericsson.com> for ST-Ericsson | ||
| 7 | * | ||
| 8 | * License terms: GNU General Public License (GPL), version 2 | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/platform_device.h> | ||
| 13 | |||
| 14 | #include <plat/ste_dma40.h> | ||
| 15 | #include <mach/setup.h> | ||
| 16 | #include <mach/hardware.h> | ||
| 17 | |||
| 18 | #include "ste-dma40-db5500.h" | ||
| 19 | |||
| 20 | static struct resource dma40_resources[] = { | ||
| 21 | [0] = { | ||
| 22 | .start = U5500_DMA_BASE, | ||
| 23 | .end = U5500_DMA_BASE + SZ_4K - 1, | ||
| 24 | .flags = IORESOURCE_MEM, | ||
| 25 | .name = "base", | ||
| 26 | }, | ||
| 27 | [1] = { | ||
| 28 | .start = U5500_DMA_LCPA_BASE, | ||
| 29 | .end = U5500_DMA_LCPA_BASE + 2 * SZ_1K - 1, | ||
| 30 | .flags = IORESOURCE_MEM, | ||
| 31 | .name = "lcpa", | ||
| 32 | }, | ||
| 33 | [2] = { | ||
| 34 | .start = IRQ_DB5500_DMA, | ||
| 35 | .end = IRQ_DB5500_DMA, | ||
| 36 | .flags = IORESOURCE_IRQ | ||
| 37 | } | ||
| 38 | }; | ||
| 39 | |||
| 40 | /* Default configuration for physical memcpy */ | ||
| 41 | static struct stedma40_chan_cfg dma40_memcpy_conf_phy = { | ||
| 42 | .mode = STEDMA40_MODE_PHYSICAL, | ||
| 43 | .dir = STEDMA40_MEM_TO_MEM, | ||
| 44 | |||
| 45 | .src_info.data_width = STEDMA40_BYTE_WIDTH, | ||
| 46 | .src_info.psize = STEDMA40_PSIZE_PHY_1, | ||
| 47 | .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, | ||
| 48 | |||
| 49 | .dst_info.data_width = STEDMA40_BYTE_WIDTH, | ||
| 50 | .dst_info.psize = STEDMA40_PSIZE_PHY_1, | ||
| 51 | .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, | ||
| 52 | }; | ||
| 53 | |||
| 54 | /* Default configuration for logical memcpy */ | ||
| 55 | static struct stedma40_chan_cfg dma40_memcpy_conf_log = { | ||
| 56 | .dir = STEDMA40_MEM_TO_MEM, | ||
| 57 | |||
| 58 | .src_info.data_width = STEDMA40_BYTE_WIDTH, | ||
| 59 | .src_info.psize = STEDMA40_PSIZE_LOG_1, | ||
| 60 | .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, | ||
| 61 | |||
| 62 | .dst_info.data_width = STEDMA40_BYTE_WIDTH, | ||
| 63 | .dst_info.psize = STEDMA40_PSIZE_LOG_1, | ||
| 64 | .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL, | ||
| 65 | }; | ||
| 66 | |||
| 67 | /* | ||
| 68 | * Mapping between soruce event lines and physical device address This was | ||
| 69 | * created assuming that the event line is tied to a device and therefore the | ||
| 70 | * address is constant, however this is not true for at least USB, and the | ||
| 71 | * values are just placeholders for USB. This table is preserved and used for | ||
| 72 | * now. | ||
| 73 | */ | ||
| 74 | static const dma_addr_t dma40_rx_map[DB5500_DMA_NR_DEV] = { | ||
| 75 | [DB5500_DMA_DEV24_SDMMC0_RX] = -1, | ||
| 76 | }; | ||
| 77 | |||
| 78 | /* Mapping between destination event lines and physical device address */ | ||
| 79 | static const dma_addr_t dma40_tx_map[DB5500_DMA_NR_DEV] = { | ||
| 80 | [DB5500_DMA_DEV24_SDMMC0_TX] = -1, | ||
| 81 | }; | ||
| 82 | |||
| 83 | static int dma40_memcpy_event[] = { | ||
| 84 | DB5500_DMA_MEMCPY_TX_1, | ||
| 85 | DB5500_DMA_MEMCPY_TX_2, | ||
| 86 | DB5500_DMA_MEMCPY_TX_3, | ||
| 87 | DB5500_DMA_MEMCPY_TX_4, | ||
| 88 | DB5500_DMA_MEMCPY_TX_5, | ||
| 89 | }; | ||
| 90 | |||
| 91 | static struct stedma40_platform_data dma40_plat_data = { | ||
| 92 | .dev_len = ARRAY_SIZE(dma40_rx_map), | ||
| 93 | .dev_rx = dma40_rx_map, | ||
| 94 | .dev_tx = dma40_tx_map, | ||
| 95 | .memcpy = dma40_memcpy_event, | ||
| 96 | .memcpy_len = ARRAY_SIZE(dma40_memcpy_event), | ||
| 97 | .memcpy_conf_phy = &dma40_memcpy_conf_phy, | ||
| 98 | .memcpy_conf_log = &dma40_memcpy_conf_log, | ||
| 99 | .disabled_channels = {-1}, | ||
| 100 | }; | ||
| 101 | |||
| 102 | static struct platform_device dma40_device = { | ||
| 103 | .dev = { | ||
| 104 | .platform_data = &dma40_plat_data, | ||
| 105 | }, | ||
| 106 | .name = "dma40", | ||
| 107 | .id = 0, | ||
| 108 | .num_resources = ARRAY_SIZE(dma40_resources), | ||
| 109 | .resource = dma40_resources | ||
| 110 | }; | ||
| 111 | |||
| 112 | void __init db5500_dma_init(void) | ||
| 113 | { | ||
| 114 | int ret; | ||
| 115 | |||
| 116 | ret = platform_device_register(&dma40_device); | ||
| 117 | if (ret) | ||
| 118 | dev_err(&dma40_device.dev, "unable to register device: %d\n", ret); | ||
| 119 | |||
| 120 | } | ||
diff --git a/arch/arm/mach-ux500/headsmp.S b/arch/arm/mach-ux500/headsmp.S index a6be2cdf2b2f..64fa451edcfd 100644 --- a/arch/arm/mach-ux500/headsmp.S +++ b/arch/arm/mach-ux500/headsmp.S | |||
| @@ -23,7 +23,6 @@ ENTRY(u8500_secondary_startup) | |||
| 23 | ldmia r4, {r5, r6} | 23 | ldmia r4, {r5, r6} |
| 24 | sub r4, r4, r5 | 24 | sub r4, r4, r5 |
| 25 | add r6, r6, r4 | 25 | add r6, r6, r4 |
| 26 | dsb | ||
| 27 | pen: ldr r7, [r6] | 26 | pen: ldr r7, [r6] |
| 28 | cmp r7, r0 | 27 | cmp r7, r0 |
| 29 | bne pen | 28 | bne pen |
diff --git a/arch/arm/mach-ux500/hotplug.c b/arch/arm/mach-ux500/hotplug.c index b782a03024be..dd8037ebccf8 100644 --- a/arch/arm/mach-ux500/hotplug.c +++ b/arch/arm/mach-ux500/hotplug.c | |||
| @@ -11,14 +11,11 @@ | |||
| 11 | #include <linux/kernel.h> | 11 | #include <linux/kernel.h> |
| 12 | #include <linux/errno.h> | 12 | #include <linux/errno.h> |
| 13 | #include <linux/smp.h> | 13 | #include <linux/smp.h> |
| 14 | #include <linux/completion.h> | ||
| 15 | 14 | ||
| 16 | #include <asm/cacheflush.h> | 15 | #include <asm/cacheflush.h> |
| 17 | 16 | ||
| 18 | extern volatile int pen_release; | 17 | extern volatile int pen_release; |
| 19 | 18 | ||
| 20 | static DECLARE_COMPLETION(cpu_killed); | ||
| 21 | |||
| 22 | static inline void platform_do_lowpower(unsigned int cpu) | 19 | static inline void platform_do_lowpower(unsigned int cpu) |
| 23 | { | 20 | { |
| 24 | flush_cache_all(); | 21 | flush_cache_all(); |
| @@ -38,7 +35,7 @@ static inline void platform_do_lowpower(unsigned int cpu) | |||
| 38 | 35 | ||
| 39 | int platform_cpu_kill(unsigned int cpu) | 36 | int platform_cpu_kill(unsigned int cpu) |
| 40 | { | 37 | { |
| 41 | return wait_for_completion_timeout(&cpu_killed, 5000); | 38 | return 1; |
| 42 | } | 39 | } |
| 43 | 40 | ||
| 44 | /* | 41 | /* |
| @@ -48,19 +45,6 @@ int platform_cpu_kill(unsigned int cpu) | |||
| 48 | */ | 45 | */ |
| 49 | void platform_cpu_die(unsigned int cpu) | 46 | void platform_cpu_die(unsigned int cpu) |
| 50 | { | 47 | { |
| 51 | #ifdef DEBUG | ||
| 52 | unsigned int this_cpu = hard_smp_processor_id(); | ||
| 53 | |||
| 54 | if (cpu != this_cpu) { | ||
| 55 | printk(KERN_CRIT "Eek! platform_cpu_die running on %u, should be %u\n", | ||
| 56 | this_cpu, cpu); | ||
| 57 | BUG(); | ||
| 58 | } | ||
| 59 | #endif | ||
| 60 | |||
| 61 | printk(KERN_NOTICE "CPU%u: shutdown\n", cpu); | ||
| 62 | complete(&cpu_killed); | ||
| 63 | |||
| 64 | /* directly enter low power state, skipping secure registers */ | 48 | /* directly enter low power state, skipping secure registers */ |
| 65 | platform_do_lowpower(cpu); | 49 | platform_do_lowpower(cpu); |
| 66 | } | 50 | } |
diff --git a/arch/arm/mach-ux500/id.c b/arch/arm/mach-ux500/id.c new file mode 100644 index 000000000000..d35122ebc67b --- /dev/null +++ b/arch/arm/mach-ux500/id.c | |||
| @@ -0,0 +1,107 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) ST-Ericsson SA 2010 | ||
| 3 | * | ||
| 4 | * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson | ||
| 5 | * License terms: GNU General Public License (GPL) version 2 | ||
| 6 | */ | ||
| 7 | |||
| 8 | #include <linux/kernel.h> | ||
| 9 | #include <linux/init.h> | ||
| 10 | #include <linux/io.h> | ||
| 11 | |||
| 12 | #include <asm/cputype.h> | ||
| 13 | #include <asm/tlbflush.h> | ||
| 14 | #include <asm/cacheflush.h> | ||
| 15 | #include <asm/mach/map.h> | ||
| 16 | |||
| 17 | #include <mach/hardware.h> | ||
| 18 | #include <mach/setup.h> | ||
| 19 | |||
| 20 | struct dbx500_asic_id dbx500_id; | ||
| 21 | |||
| 22 | static unsigned int ux500_read_asicid(phys_addr_t addr) | ||
| 23 | { | ||
| 24 | phys_addr_t base = addr & ~0xfff; | ||
| 25 | struct map_desc desc = { | ||
| 26 | .virtual = IO_ADDRESS(base), | ||
| 27 | .pfn = __phys_to_pfn(base), | ||
| 28 | .length = SZ_16K, | ||
| 29 | .type = MT_DEVICE, | ||
| 30 | }; | ||
| 31 | |||
| 32 | iotable_init(&desc, 1); | ||
| 33 | |||
| 34 | /* As in devicemaps_init() */ | ||
| 35 | local_flush_tlb_all(); | ||
| 36 | flush_cache_all(); | ||
| 37 | |||
| 38 | return readl(__io_address(addr)); | ||
| 39 | } | ||
| 40 | |||
| 41 | static void ux500_print_soc_info(unsigned int asicid) | ||
| 42 | { | ||
| 43 | unsigned int rev = dbx500_revision(); | ||
| 44 | |||
| 45 | pr_info("DB%4x ", dbx500_partnumber()); | ||
| 46 | |||
| 47 | if (rev == 0x01) | ||
| 48 | pr_cont("Early Drop"); | ||
| 49 | else if (rev >= 0xA0) | ||
| 50 | pr_cont("v%d.%d" , (rev >> 4) - 0xA + 1, rev & 0xf); | ||
| 51 | else | ||
| 52 | pr_cont("Unknown"); | ||
| 53 | |||
| 54 | pr_cont(" [%#010x]\n", asicid); | ||
| 55 | } | ||
| 56 | |||
| 57 | static unsigned int partnumber(unsigned int asicid) | ||
| 58 | { | ||
| 59 | return (asicid >> 8) & 0xffff; | ||
| 60 | } | ||
| 61 | |||
| 62 | /* | ||
| 63 | * SOC MIDR ASICID ADDRESS ASICID VALUE | ||
| 64 | * DB8500ed 0x410fc090 0x9001FFF4 0x00850001 | ||
| 65 | * DB8500v1 0x411fc091 0x9001FFF4 0x008500A0 | ||
| 66 | * DB8500v1.1 0x411fc091 0x9001FFF4 0x008500A1 | ||
| 67 | * DB8500v2 0x412fc091 0x9001DBF4 0x008500B0 | ||
| 68 | * DB5500v1 0x412fc091 0x9001FFF4 0x005500A0 | ||
| 69 | */ | ||
| 70 | |||
| 71 | void __init ux500_map_io(void) | ||
| 72 | { | ||
| 73 | unsigned int cpuid = read_cpuid_id(); | ||
| 74 | unsigned int asicid = 0; | ||
| 75 | phys_addr_t addr = 0; | ||
| 76 | |||
| 77 | switch (cpuid) { | ||
| 78 | case 0x410fc090: /* DB8500ed */ | ||
| 79 | case 0x411fc091: /* DB8500v1 */ | ||
| 80 | addr = 0x9001FFF4; | ||
| 81 | break; | ||
| 82 | |||
| 83 | case 0x412fc091: /* DB8500v2 / DB5500v1 */ | ||
| 84 | asicid = ux500_read_asicid(0x9001DBF4); | ||
| 85 | if (partnumber(asicid) == 0x8500) | ||
| 86 | /* DB8500v2 */ | ||
| 87 | break; | ||
| 88 | |||
| 89 | /* DB5500v1 */ | ||
| 90 | addr = 0x9001FFF4; | ||
| 91 | break; | ||
| 92 | } | ||
| 93 | |||
| 94 | if (addr) | ||
| 95 | asicid = ux500_read_asicid(addr); | ||
| 96 | |||
| 97 | if (!asicid) { | ||
| 98 | pr_err("Unable to identify SoC\n"); | ||
| 99 | ux500_unknown_soc(); | ||
| 100 | } | ||
| 101 | |||
| 102 | dbx500_id.process = asicid >> 24; | ||
| 103 | dbx500_id.partnumber = partnumber(asicid); | ||
| 104 | dbx500_id.revision = asicid & 0xff; | ||
| 105 | |||
| 106 | ux500_print_soc_info(asicid); | ||
| 107 | } | ||
diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h index 3eafc0e24ba5..bd88c1e74060 100644 --- a/arch/arm/mach-ux500/include/mach/db5500-regs.h +++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h | |||
| @@ -114,4 +114,8 @@ | |||
| 114 | #define U5500_MBOX2_LOCAL_START (U5500_MBOX_BASE + 0x20) | 114 | #define U5500_MBOX2_LOCAL_START (U5500_MBOX_BASE + 0x20) |
| 115 | #define U5500_MBOX2_LOCAL_END (U5500_MBOX_BASE + 0x3F) | 115 | #define U5500_MBOX2_LOCAL_END (U5500_MBOX_BASE + 0x3F) |
| 116 | 116 | ||
| 117 | #define U5500_ESRAM_BASE 0x40000000 | ||
| 118 | #define U5500_ESRAM_DMA_LCPA_OFFSET 0x10000 | ||
| 119 | #define U5500_DMA_LCPA_BASE (U5500_ESRAM_BASE + U5500_ESRAM_DMA_LCPA_OFFSET) | ||
| 120 | |||
| 117 | #endif | 121 | #endif |
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h index f07d0986409d..0fefb34c11e4 100644 --- a/arch/arm/mach-ux500/include/mach/db8500-regs.h +++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h | |||
| @@ -92,7 +92,8 @@ | |||
| 92 | #define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000) | 92 | #define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000) |
| 93 | #define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000) | 93 | #define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000) |
| 94 | #define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) | 94 | #define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) |
| 95 | #define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x0f000) | 95 | #define U8500_PRCMU_TCDM_BASE_V1 (U8500_PER4_BASE + 0x0f000) |
| 96 | #define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000) | ||
| 96 | 97 | ||
| 97 | /* per3 base addresses */ | 98 | /* per3 base addresses */ |
| 98 | #define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000) | 99 | #define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000) |
diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S index be7c0f14e310..700fb05ee815 100644 --- a/arch/arm/mach-ux500/include/mach/debug-macro.S +++ b/arch/arm/mach-ux500/include/mach/debug-macro.S | |||
| @@ -14,7 +14,24 @@ | |||
| 14 | #error Invalid Ux500 debug UART | 14 | #error Invalid Ux500 debug UART |
| 15 | #endif | 15 | #endif |
| 16 | 16 | ||
| 17 | #define __UX500_UART(n) UX500_UART##n##_BASE | 17 | /* |
| 18 | * DEBUG_LL only works if only one SOC is built in. We don't use #else below | ||
| 19 | * in order to get "__UX500_UART redefined" warnings if more than one SOC is | ||
| 20 | * built, so that there's some hint during the build that something is wrong. | ||
| 21 | */ | ||
| 22 | |||
| 23 | #ifdef CONFIG_UX500_SOC_DB5500 | ||
| 24 | #define __UX500_UART(n) U5500_UART##n##_BASE | ||
| 25 | #endif | ||
| 26 | |||
| 27 | #ifdef CONFIG_UX500_SOC_DB8500 | ||
| 28 | #define __UX500_UART(n) U8500_UART##n##_BASE | ||
| 29 | #endif | ||
| 30 | |||
| 31 | #ifndef __UX500_UART | ||
| 32 | #error Unknown SOC | ||
| 33 | #endif | ||
| 34 | |||
| 18 | #define UX500_UART(n) __UX500_UART(n) | 35 | #define UX500_UART(n) __UX500_UART(n) |
| 19 | #define UART_BASE UX500_UART(CONFIG_UX500_DEBUG_UART) | 36 | #define UART_BASE UX500_UART(CONFIG_UX500_DEBUG_UART) |
| 20 | 37 | ||
diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h index b91a4d1211a2..020b6369a30a 100644 --- a/arch/arm/mach-ux500/include/mach/devices.h +++ b/arch/arm/mach-ux500/include/mach/devices.h | |||
| @@ -14,27 +14,10 @@ extern struct platform_device u5500_gpio_devs[]; | |||
| 14 | extern struct platform_device u8500_gpio_devs[]; | 14 | extern struct platform_device u8500_gpio_devs[]; |
| 15 | 15 | ||
| 16 | extern struct amba_device ux500_pl031_device; | 16 | extern struct amba_device ux500_pl031_device; |
| 17 | extern struct amba_device u8500_ssp0_device; | ||
| 18 | extern struct amba_device ux500_uart0_device; | ||
| 19 | extern struct amba_device ux500_uart1_device; | ||
| 20 | extern struct amba_device ux500_uart2_device; | ||
| 21 | 17 | ||
| 22 | extern struct platform_device ux500_i2c1_device; | ||
| 23 | extern struct platform_device ux500_i2c2_device; | ||
| 24 | extern struct platform_device ux500_i2c3_device; | ||
| 25 | |||
| 26 | extern struct platform_device u8500_i2c0_device; | ||
| 27 | extern struct platform_device u8500_i2c4_device; | ||
| 28 | extern struct platform_device u8500_dma40_device; | 18 | extern struct platform_device u8500_dma40_device; |
| 29 | extern struct platform_device ux500_ske_keypad_device; | 19 | extern struct platform_device ux500_ske_keypad_device; |
| 30 | 20 | ||
| 31 | extern struct amba_device u8500_sdi0_device; | ||
| 32 | extern struct amba_device u8500_sdi1_device; | ||
| 33 | extern struct amba_device u8500_sdi2_device; | ||
| 34 | extern struct amba_device u8500_sdi3_device; | ||
| 35 | extern struct amba_device u8500_sdi4_device; | ||
| 36 | extern struct amba_device u8500_sdi5_device; | ||
| 37 | |||
| 38 | void dma40_u8500ed_fixup(void); | 21 | void dma40_u8500ed_fixup(void); |
| 39 | 22 | ||
| 40 | #endif | 23 | #endif |
diff --git a/arch/arm/mach-ux500/include/mach/entry-macro.S b/arch/arm/mach-ux500/include/mach/entry-macro.S index 60ea88db8283..071bba94f727 100644 --- a/arch/arm/mach-ux500/include/mach/entry-macro.S +++ b/arch/arm/mach-ux500/include/mach/entry-macro.S | |||
| @@ -11,79 +11,10 @@ | |||
| 11 | * warranty of any kind, whether express or implied. | 11 | * warranty of any kind, whether express or implied. |
| 12 | */ | 12 | */ |
| 13 | #include <mach/hardware.h> | 13 | #include <mach/hardware.h> |
| 14 | #include <asm/hardware/gic.h> | 14 | #include <asm/hardware/entry-macro-gic.S> |
| 15 | 15 | ||
| 16 | .macro disable_fiq | 16 | .macro disable_fiq |
| 17 | .endm | 17 | .endm |
| 18 | 18 | ||
| 19 | .macro get_irqnr_preamble, base, tmp | ||
| 20 | ldr \base, =IO_ADDRESS(UX500_GIC_CPU_BASE) | ||
| 21 | .endm | ||
| 22 | |||
| 23 | .macro arch_ret_to_user, tmp1, tmp2 | 19 | .macro arch_ret_to_user, tmp1, tmp2 |
| 24 | .endm | 20 | .endm |
| 25 | |||
| 26 | /* | ||
| 27 | * The interrupt numbering scheme is defined in the | ||
| 28 | * interrupt controller spec. To wit: | ||
| 29 | * | ||
| 30 | * Interrupts 0-15 are IPI | ||
| 31 | * 16-28 are reserved | ||
| 32 | * 29-31 are local. We allow 30 to be used for the watchdog. | ||
| 33 | * 32-1020 are global | ||
| 34 | * 1021-1022 are reserved | ||
| 35 | * 1023 is "spurious" (no interrupt) | ||
| 36 | * | ||
| 37 | * For now, we ignore all local interrupts so only return an | ||
| 38 | * interrupt if it's between 30 and 1020. The test_for_ipi | ||
| 39 | * routine below will pick up on IPIs. | ||
| 40 | * | ||
| 41 | * A simple read from the controller will tell us the number | ||
| 42 | * of the highest priority enabled interrupt. We then just | ||
| 43 | * need to check whether it is in the valid range for an | ||
| 44 | * IRQ (30-1020 inclusive). | ||
| 45 | */ | ||
| 46 | |||
| 47 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 48 | |||
| 49 | /* bits 12-10 = src CPU, 9-0 = int # */ | ||
| 50 | ldr \irqstat, [\base, #GIC_CPU_INTACK] | ||
| 51 | |||
| 52 | ldr \tmp, =1021 | ||
| 53 | |||
| 54 | bic \irqnr, \irqstat, #0x1c00 | ||
| 55 | |||
| 56 | cmp \irqnr, #29 | ||
| 57 | cmpcc \irqnr, \irqnr | ||
| 58 | cmpne \irqnr, \tmp | ||
| 59 | cmpcs \irqnr, \irqnr | ||
| 60 | |||
| 61 | .endm | ||
| 62 | |||
| 63 | /* We assume that irqstat (the raw value of the IRQ | ||
| 64 | * acknowledge register) is preserved from the macro above. | ||
| 65 | * If there is an IPI, we immediately signal end of | ||
| 66 | * interrupt on the controller, since this requires the | ||
| 67 | * original irqstat value which we won't easily be able | ||
| 68 | * to recreate later. | ||
| 69 | */ | ||
| 70 | |||
| 71 | .macro test_for_ipi, irqnr, irqstat, base, tmp | ||
| 72 | bic \irqnr, \irqstat, #0x1c00 | ||
| 73 | cmp \irqnr, #16 | ||
| 74 | strcc \irqstat, [\base, #GIC_CPU_EOI] | ||
| 75 | cmpcs \irqnr, \irqnr | ||
| 76 | .endm | ||
| 77 | |||
| 78 | /* As above, this assumes that irqstat and base | ||
| 79 | * are preserved.. | ||
| 80 | */ | ||
| 81 | |||
| 82 | .macro test_for_ltirq, irqnr, irqstat, base, tmp | ||
| 83 | bic \irqnr, \irqstat, #0x1c00 | ||
| 84 | mov \tmp, #0 | ||
| 85 | cmp \irqnr, #29 | ||
| 86 | moveq \tmp, #1 | ||
| 87 | streq \irqstat, [\base, #GIC_CPU_EOI] | ||
| 88 | cmp \tmp, #0 | ||
| 89 | .endm | ||
diff --git a/arch/arm/mach-ux500/include/mach/gpio.h b/arch/arm/mach-ux500/include/mach/gpio.h index d548a622e7d2..3c4cd31ad9f7 100644 --- a/arch/arm/mach-ux500/include/mach/gpio.h +++ b/arch/arm/mach-ux500/include/mach/gpio.h | |||
| @@ -9,42 +9,4 @@ | |||
| 9 | 9 | ||
| 10 | #include <plat/gpio.h> | 10 | #include <plat/gpio.h> |
| 11 | 11 | ||
| 12 | #define __GPIO_RESOURCE(soc, block) \ | ||
| 13 | { \ | ||
| 14 | .start = soc##_GPIOBANK##block##_BASE, \ | ||
| 15 | .end = soc##_GPIOBANK##block##_BASE + 127, \ | ||
| 16 | .flags = IORESOURCE_MEM, \ | ||
| 17 | }, \ | ||
| 18 | { \ | ||
| 19 | .start = IRQ_GPIO##block, \ | ||
| 20 | .end = IRQ_GPIO##block, \ | ||
| 21 | .flags = IORESOURCE_IRQ, \ | ||
| 22 | } | ||
| 23 | |||
| 24 | #define __GPIO_DEVICE(soc, block) \ | ||
| 25 | { \ | ||
| 26 | .name = "gpio", \ | ||
| 27 | .id = block, \ | ||
| 28 | .num_resources = 2, \ | ||
| 29 | .resource = &soc##_gpio_resources[block * 2], \ | ||
| 30 | .dev = { \ | ||
| 31 | .platform_data = &soc##_gpio_data[block], \ | ||
| 32 | }, \ | ||
| 33 | } | ||
| 34 | |||
| 35 | #define GPIO_DATA(_name, first) \ | ||
| 36 | { \ | ||
| 37 | .name = _name, \ | ||
| 38 | .first_gpio = first, \ | ||
| 39 | .first_irq = NOMADIK_GPIO_TO_IRQ(first), \ | ||
| 40 | } | ||
| 41 | |||
| 42 | #ifdef CONFIG_UX500_SOC_DB8500 | ||
| 43 | #define GPIO_RESOURCE(block) __GPIO_RESOURCE(U8500, block) | ||
| 44 | #define GPIO_DEVICE(block) __GPIO_DEVICE(u8500, block) | ||
| 45 | #elif defined(CONFIG_UX500_SOC_DB5500) | ||
| 46 | #define GPIO_RESOURCE(block) __GPIO_RESOURCE(U5500, block) | ||
| 47 | #define GPIO_DEVICE(block) __GPIO_DEVICE(u5500, block) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #endif /* __ASM_ARCH_GPIO_H */ | 12 | #endif /* __ASM_ARCH_GPIO_H */ |
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h index 32e883a8f2a2..bf63f2631ba0 100644 --- a/arch/arm/mach-ux500/include/mach/hardware.h +++ b/arch/arm/mach-ux500/include/mach/hardware.h | |||
| @@ -29,118 +29,14 @@ | |||
| 29 | #include <mach/db8500-regs.h> | 29 | #include <mach/db8500-regs.h> |
| 30 | #include <mach/db5500-regs.h> | 30 | #include <mach/db5500-regs.h> |
| 31 | 31 | ||
| 32 | #ifdef CONFIG_UX500_SOC_DB8500 | ||
| 33 | #define UX500(periph) U8500_##periph##_BASE | ||
| 34 | #elif defined(CONFIG_UX500_SOC_DB5500) | ||
| 35 | #define UX500(periph) U5500_##periph##_BASE | ||
| 36 | #endif | ||
| 37 | |||
| 38 | #define UX500_BACKUPRAM0_BASE UX500(BACKUPRAM0) | ||
| 39 | #define UX500_BACKUPRAM1_BASE UX500(BACKUPRAM1) | ||
| 40 | #define UX500_B2R2_BASE UX500(B2R2) | ||
| 41 | |||
| 42 | #define UX500_CLKRST1_BASE UX500(CLKRST1) | ||
| 43 | #define UX500_CLKRST2_BASE UX500(CLKRST2) | ||
| 44 | #define UX500_CLKRST3_BASE UX500(CLKRST3) | ||
| 45 | #define UX500_CLKRST5_BASE UX500(CLKRST5) | ||
| 46 | #define UX500_CLKRST6_BASE UX500(CLKRST6) | ||
| 47 | |||
| 48 | #define UX500_DMA_BASE UX500(DMA) | ||
| 49 | #define UX500_FSMC_BASE UX500(FSMC) | ||
| 50 | |||
| 51 | #define UX500_GIC_CPU_BASE UX500(GIC_CPU) | ||
| 52 | #define UX500_GIC_DIST_BASE UX500(GIC_DIST) | ||
| 53 | |||
| 54 | #define UX500_I2C1_BASE UX500(I2C1) | ||
| 55 | #define UX500_I2C2_BASE UX500(I2C2) | ||
| 56 | #define UX500_I2C3_BASE UX500(I2C3) | ||
| 57 | |||
| 58 | #define UX500_L2CC_BASE UX500(L2CC) | ||
| 59 | #define UX500_MCDE_BASE UX500(MCDE) | ||
| 60 | #define UX500_MTU0_BASE UX500(MTU0) | ||
| 61 | #define UX500_MTU1_BASE UX500(MTU1) | ||
| 62 | #define UX500_PRCMU_BASE UX500(PRCMU) | ||
| 63 | |||
| 64 | #define UX500_RNG_BASE UX500(RNG) | ||
| 65 | #define UX500_RTC_BASE UX500(RTC) | ||
| 66 | |||
| 67 | #define UX500_SCU_BASE UX500(SCU) | ||
| 68 | |||
| 69 | #define UX500_SDI0_BASE UX500(SDI0) | ||
| 70 | #define UX500_SDI1_BASE UX500(SDI1) | ||
| 71 | #define UX500_SDI2_BASE UX500(SDI2) | ||
| 72 | #define UX500_SDI3_BASE UX500(SDI3) | ||
| 73 | #define UX500_SDI4_BASE UX500(SDI4) | ||
| 74 | |||
| 75 | #define UX500_SPI0_BASE UX500(SPI0) | ||
| 76 | #define UX500_SPI1_BASE UX500(SPI1) | ||
| 77 | #define UX500_SPI2_BASE UX500(SPI2) | ||
| 78 | #define UX500_SPI3_BASE UX500(SPI3) | ||
| 79 | |||
| 80 | #define UX500_SIA_BASE UX500(SIA) | ||
| 81 | #define UX500_SVA_BASE UX500(SVA) | ||
| 82 | |||
| 83 | #define UX500_TWD_BASE UX500(TWD) | ||
| 84 | |||
| 85 | #define UX500_UART0_BASE UX500(UART0) | ||
| 86 | #define UX500_UART1_BASE UX500(UART1) | ||
| 87 | #define UX500_UART2_BASE UX500(UART2) | ||
| 88 | |||
| 89 | #define UX500_USBOTG_BASE UX500(USBOTG) | ||
| 90 | |||
| 91 | /* ST-Ericsson modified pl022 id */ | 32 | /* ST-Ericsson modified pl022 id */ |
| 92 | #define SSP_PER_ID 0x01080022 | 33 | #define SSP_PER_ID 0x01080022 |
| 93 | 34 | ||
| 94 | #ifndef __ASSEMBLY__ | 35 | #ifndef __ASSEMBLY__ |
| 95 | 36 | ||
| 96 | #include <asm/cputype.h> | 37 | #include <mach/id.h> |
| 97 | |||
| 98 | static inline bool cpu_is_u8500(void) | ||
| 99 | { | ||
| 100 | #ifdef CONFIG_UX500_SOC_DB8500 | ||
| 101 | return 1; | ||
| 102 | #else | ||
| 103 | return 0; | ||
| 104 | #endif | ||
| 105 | } | ||
| 106 | |||
| 107 | #define CPUID_DB8500ED 0x410fc090 | ||
| 108 | #define CPUID_DB8500V1 0x411fc091 | ||
| 109 | #define CPUID_DB8500V2 0x412fc091 | ||
| 110 | 38 | ||
| 111 | static inline bool cpu_is_u8500ed(void) | 39 | #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) |
| 112 | { | ||
| 113 | return cpu_is_u8500() && (read_cpuid_id() == CPUID_DB8500ED); | ||
| 114 | } | ||
| 115 | |||
| 116 | static inline bool cpu_is_u8500v1(void) | ||
| 117 | { | ||
| 118 | return cpu_is_u8500() && (read_cpuid_id() == CPUID_DB8500V1); | ||
| 119 | } | ||
| 120 | |||
| 121 | static inline bool cpu_is_u8500v2(void) | ||
| 122 | { | ||
| 123 | return cpu_is_u8500() && (read_cpuid_id() == CPUID_DB8500V2); | ||
| 124 | } | ||
| 125 | |||
| 126 | #ifdef CONFIG_UX500_SOC_DB8500 | ||
| 127 | bool cpu_is_u8500v10(void); | ||
| 128 | bool cpu_is_u8500v11(void); | ||
| 129 | bool cpu_is_u8500v20(void); | ||
| 130 | #else | ||
| 131 | static inline bool cpu_is_u8500v10(void) { return false; } | ||
| 132 | static inline bool cpu_is_u8500v11(void) { return false; } | ||
| 133 | static inline bool cpu_is_u8500v20(void) { return false; } | ||
| 134 | #endif | ||
| 135 | |||
| 136 | static inline bool cpu_is_u5500(void) | ||
| 137 | { | ||
| 138 | #ifdef CONFIG_UX500_SOC_DB5500 | ||
| 139 | return 1; | ||
| 140 | #else | ||
| 141 | return 0; | ||
| 142 | #endif | ||
| 143 | } | ||
| 144 | 40 | ||
| 145 | #endif | 41 | #endif |
| 146 | 42 | ||
diff --git a/arch/arm/mach-ux500/include/mach/id.h b/arch/arm/mach-ux500/include/mach/id.h new file mode 100644 index 000000000000..f1288d10b6ab --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/id.h | |||
| @@ -0,0 +1,80 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) ST-Ericsson SA 2010 | ||
| 3 | * | ||
| 4 | * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson | ||
| 5 | * License terms: GNU General Public License (GPL) version 2 | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifndef __MACH_UX500_ID | ||
| 9 | #define __MACH_UX500_ID | ||
| 10 | |||
| 11 | /** | ||
| 12 | * struct dbx500_asic_id - fields of the ASIC ID | ||
| 13 | * @process: the manufacturing process, 0x40 is 40 nm 0x00 is "standard" | ||
| 14 | * @partnumber: hithereto 0x8500 for DB8500 | ||
| 15 | * @revision: version code in the series | ||
| 16 | */ | ||
| 17 | struct dbx500_asic_id { | ||
| 18 | u16 partnumber; | ||
| 19 | u8 revision; | ||
| 20 | u8 process; | ||
| 21 | }; | ||
| 22 | |||
| 23 | extern struct dbx500_asic_id dbx500_id; | ||
| 24 | |||
| 25 | static inline unsigned int __attribute_const__ dbx500_partnumber(void) | ||
| 26 | { | ||
| 27 | return dbx500_id.partnumber; | ||
| 28 | } | ||
| 29 | |||
| 30 | static inline unsigned int __attribute_const__ dbx500_revision(void) | ||
| 31 | { | ||
| 32 | return dbx500_id.revision; | ||
| 33 | } | ||
| 34 | |||
| 35 | /* | ||
| 36 | * SOCs | ||
| 37 | */ | ||
| 38 | |||
| 39 | static inline bool __attribute_const__ cpu_is_u8500(void) | ||
| 40 | { | ||
| 41 | return dbx500_partnumber() == 0x8500; | ||
| 42 | } | ||
| 43 | |||
| 44 | static inline bool __attribute_const__ cpu_is_u5500(void) | ||
| 45 | { | ||
| 46 | return dbx500_partnumber() == 0x5500; | ||
| 47 | } | ||
| 48 | |||
| 49 | /* | ||
| 50 | * 8500 revisions | ||
| 51 | */ | ||
| 52 | |||
| 53 | static inline bool __attribute_const__ cpu_is_u8500ed(void) | ||
| 54 | { | ||
| 55 | return cpu_is_u8500() && dbx500_revision() == 0x00; | ||
| 56 | } | ||
| 57 | |||
| 58 | static inline bool __attribute_const__ cpu_is_u8500v1(void) | ||
| 59 | { | ||
| 60 | return cpu_is_u8500() && (dbx500_revision() & 0xf0) == 0xA0; | ||
| 61 | } | ||
| 62 | |||
| 63 | static inline bool __attribute_const__ cpu_is_u8500v10(void) | ||
| 64 | { | ||
| 65 | return cpu_is_u8500() && dbx500_revision() == 0xA0; | ||
| 66 | } | ||
| 67 | |||
| 68 | static inline bool __attribute_const__ cpu_is_u8500v11(void) | ||
| 69 | { | ||
| 70 | return cpu_is_u8500() && dbx500_revision() == 0xA1; | ||
| 71 | } | ||
| 72 | |||
| 73 | static inline bool __attribute_const__ cpu_is_u8500v2(void) | ||
| 74 | { | ||
| 75 | return cpu_is_u8500() && ((dbx500_revision() & 0xf0) == 0xB0); | ||
| 76 | } | ||
| 77 | |||
| 78 | #define ux500_unknown_soc() BUG() | ||
| 79 | |||
| 80 | #endif | ||
diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h index cca4f705601e..7cdeb2af0ebb 100644 --- a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h +++ b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h | |||
| @@ -8,12 +8,36 @@ | |||
| 8 | #ifndef __MACH_IRQS_BOARD_MOP500_H | 8 | #ifndef __MACH_IRQS_BOARD_MOP500_H |
| 9 | #define __MACH_IRQS_BOARD_MOP500_H | 9 | #define __MACH_IRQS_BOARD_MOP500_H |
| 10 | 10 | ||
| 11 | #define AB8500_NR_IRQS 104 | 11 | /* Number of AB8500 irqs is taken from header file */ |
| 12 | #include <linux/mfd/ab8500.h> | ||
| 12 | 13 | ||
| 13 | #define MOP500_AB8500_IRQ_BASE IRQ_BOARD_START | 14 | #define MOP500_AB8500_IRQ_BASE IRQ_BOARD_START |
| 14 | #define MOP500_AB8500_IRQ_END (MOP500_AB8500_IRQ_BASE \ | 15 | #define MOP500_AB8500_IRQ_END (MOP500_AB8500_IRQ_BASE \ |
| 15 | + AB8500_NR_IRQS) | 16 | + AB8500_NR_IRQS) |
| 16 | #define MOP500_IRQ_END MOP500_AB8500_IRQ_END | 17 | |
| 18 | /* TC35892 */ | ||
| 19 | #define TC35892_NR_INTERNAL_IRQS 8 | ||
| 20 | #define TC35892_INT_GPIO(x) (TC35892_NR_INTERNAL_IRQS + (x)) | ||
| 21 | #define TC35892_NR_GPIOS 24 | ||
| 22 | #define TC35892_NR_IRQS TC35892_INT_GPIO(TC35892_NR_GPIOS) | ||
| 23 | |||
| 24 | #define MOP500_EGPIO_NR_IRQS TC35892_NR_IRQS | ||
| 25 | |||
| 26 | #define MOP500_EGPIO_IRQ_BASE MOP500_AB8500_IRQ_END | ||
| 27 | #define MOP500_EGPIO_IRQ_END (MOP500_EGPIO_IRQ_BASE \ | ||
| 28 | + MOP500_EGPIO_NR_IRQS) | ||
| 29 | /* STMPE1601 irqs */ | ||
| 30 | #define STMPE_NR_INTERNAL_IRQS 9 | ||
| 31 | #define STMPE_INT_GPIO(x) (STMPE_NR_INTERNAL_IRQS + (x)) | ||
| 32 | #define STMPE_NR_GPIOS 24 | ||
| 33 | #define STMPE_NR_IRQS STMPE_INT_GPIO(STMPE_NR_GPIOS) | ||
| 34 | |||
| 35 | #define MOP500_STMPE1601_IRQBASE MOP500_EGPIO_IRQ_END | ||
| 36 | #define MOP500_STMPE1601_IRQ(x) (MOP500_STMPE1601_IRQBASE + (x)) | ||
| 37 | |||
| 38 | #define MOP500_NR_IRQS MOP500_STMPE1601_IRQ(STMPE_NR_INTERNAL_IRQS) | ||
| 39 | |||
| 40 | #define MOP500_IRQ_END MOP500_NR_IRQS | ||
| 17 | 41 | ||
| 18 | #if MOP500_IRQ_END > IRQ_BOARD_END | 42 | #if MOP500_IRQ_END > IRQ_BOARD_END |
| 19 | #undef IRQ_BOARD_END | 43 | #undef IRQ_BOARD_END |
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h index 693aa57de88d..ba1294c13c4d 100644 --- a/arch/arm/mach-ux500/include/mach/irqs.h +++ b/arch/arm/mach-ux500/include/mach/irqs.h | |||
| @@ -21,50 +21,6 @@ | |||
| 21 | 21 | ||
| 22 | /* Interrupt numbers generic for shared peripheral */ | 22 | /* Interrupt numbers generic for shared peripheral */ |
| 23 | #define IRQ_MTU0 (IRQ_SHPI_START + 4) | 23 | #define IRQ_MTU0 (IRQ_SHPI_START + 4) |
| 24 | #define IRQ_SPI2 (IRQ_SHPI_START + 6) | ||
| 25 | #define IRQ_SPI0 (IRQ_SHPI_START + 8) | ||
| 26 | #define IRQ_UART0 (IRQ_SHPI_START + 11) | ||
| 27 | #define IRQ_I2C3 (IRQ_SHPI_START + 12) | ||
| 28 | #define IRQ_SSP0 (IRQ_SHPI_START + 14) | ||
| 29 | #define IRQ_MTU1 (IRQ_SHPI_START + 17) | ||
| 30 | #define IRQ_RTC_RTT (IRQ_SHPI_START + 18) | ||
| 31 | #define IRQ_UART1 (IRQ_SHPI_START + 19) | ||
| 32 | #define IRQ_I2C0 (IRQ_SHPI_START + 21) | ||
| 33 | #define IRQ_I2C1 (IRQ_SHPI_START + 22) | ||
| 34 | #define IRQ_USBOTG (IRQ_SHPI_START + 23) | ||
| 35 | #define IRQ_DMA (IRQ_SHPI_START + 25) | ||
| 36 | #define IRQ_UART2 (IRQ_SHPI_START + 26) | ||
| 37 | #define IRQ_HSIR_EXCEP (IRQ_SHPI_START + 29) | ||
| 38 | #define IRQ_MSP0 (IRQ_SHPI_START + 31) | ||
| 39 | #define IRQ_HSIR_CH0_OVRRUN (IRQ_SHPI_START + 32) | ||
| 40 | #define IRQ_HSIR_CH1_OVRRUN (IRQ_SHPI_START + 33) | ||
| 41 | #define IRQ_HSIR_CH2_OVRRUN (IRQ_SHPI_START + 34) | ||
| 42 | #define IRQ_HSIR_CH3_OVRRUN (IRQ_SHPI_START + 35) | ||
| 43 | #define IRQ_AB8500 (IRQ_SHPI_START + 40) | ||
| 44 | #define IRQ_PRCMU (IRQ_SHPI_START + 47) | ||
| 45 | #define IRQ_DISP (IRQ_SHPI_START + 48) | ||
| 46 | #define IRQ_SiPI3 (IRQ_SHPI_START + 49) | ||
| 47 | #define IRQ_I2C4 (IRQ_SHPI_START + 51) | ||
| 48 | #define IRQ_SSP1 (IRQ_SHPI_START + 52) | ||
| 49 | #define IRQ_I2C2 (IRQ_SHPI_START + 55) | ||
| 50 | #define IRQ_SDMMC0 (IRQ_SHPI_START + 60) | ||
| 51 | #define IRQ_MSP1 (IRQ_SHPI_START + 62) | ||
| 52 | #define IRQ_SPI1 (IRQ_SHPI_START + 96) | ||
| 53 | #define IRQ_MSP2 (IRQ_SHPI_START + 98) | ||
| 54 | #define IRQ_SDMMC4 (IRQ_SHPI_START + 99) | ||
| 55 | #define IRQ_HSIRD0 (IRQ_SHPI_START + 104) | ||
| 56 | #define IRQ_HSIRD1 (IRQ_SHPI_START + 105) | ||
| 57 | #define IRQ_HSITD0 (IRQ_SHPI_START + 106) | ||
| 58 | #define IRQ_HSITD1 (IRQ_SHPI_START + 107) | ||
| 59 | #define IRQ_GPIO0 (IRQ_SHPI_START + 119) | ||
| 60 | #define IRQ_GPIO1 (IRQ_SHPI_START + 120) | ||
| 61 | #define IRQ_GPIO2 (IRQ_SHPI_START + 121) | ||
| 62 | #define IRQ_GPIO3 (IRQ_SHPI_START + 122) | ||
| 63 | #define IRQ_GPIO4 (IRQ_SHPI_START + 123) | ||
| 64 | #define IRQ_GPIO5 (IRQ_SHPI_START + 124) | ||
| 65 | #define IRQ_GPIO6 (IRQ_SHPI_START + 125) | ||
| 66 | #define IRQ_GPIO7 (IRQ_SHPI_START + 126) | ||
| 67 | #define IRQ_GPIO8 (IRQ_SHPI_START + 127) | ||
| 68 | 24 | ||
| 69 | /* There are 128 shared peripheral interrupts assigned to | 25 | /* There are 128 shared peripheral interrupts assigned to |
| 70 | * INTID[160:32]. The first 32 interrupts are reserved. | 26 | * INTID[160:32]. The first 32 interrupts are reserved. |
| @@ -80,7 +36,7 @@ | |||
| 80 | /* This will be overridden by board-specific irq headers */ | 36 | /* This will be overridden by board-specific irq headers */ |
| 81 | #define IRQ_BOARD_END IRQ_BOARD_START | 37 | #define IRQ_BOARD_END IRQ_BOARD_START |
| 82 | 38 | ||
| 83 | #ifdef CONFIG_MACH_U8500_MOP | 39 | #ifdef CONFIG_MACH_U8500 |
| 84 | #include <mach/irqs-board-mop500.h> | 40 | #include <mach/irqs-board-mop500.h> |
| 85 | #endif | 41 | #endif |
| 86 | 42 | ||
diff --git a/arch/arm/mach-ux500/include/mach/mbox.h b/arch/arm/mach-ux500/include/mach/mbox-db5500.h index 7f9da4d2fbda..7f9da4d2fbda 100644 --- a/arch/arm/mach-ux500/include/mach/mbox.h +++ b/arch/arm/mach-ux500/include/mach/mbox-db5500.h | |||
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-defs.h b/arch/arm/mach-ux500/include/mach/prcmu-defs.h new file mode 100644 index 000000000000..848ba64b561f --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/prcmu-defs.h | |||
| @@ -0,0 +1,30 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) STMicroelectronics 2009 | ||
| 3 | * Copyright (C) ST-Ericsson SA 2010 | ||
| 4 | * | ||
| 5 | * Author: Sundar Iyer <sundar.iyer@stericsson.com> | ||
| 6 | * Author: Martin Persson <martin.persson@stericsson.com> | ||
| 7 | * | ||
| 8 | * License Terms: GNU General Public License v2 | ||
| 9 | * | ||
| 10 | * PRCM Unit definitions | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __MACH_PRCMU_DEFS_H | ||
| 14 | #define __MACH_PRCMU_DEFS_H | ||
| 15 | |||
| 16 | enum prcmu_cpu_opp { | ||
| 17 | CPU_OPP_INIT = 0x00, | ||
| 18 | CPU_OPP_NO_CHANGE = 0x01, | ||
| 19 | CPU_OPP_100 = 0x02, | ||
| 20 | CPU_OPP_50 = 0x03, | ||
| 21 | CPU_OPP_MAX = 0x04, | ||
| 22 | CPU_OPP_EXT_CLK = 0x07 | ||
| 23 | }; | ||
| 24 | enum prcmu_ape_opp { | ||
| 25 | APE_OPP_NO_CHANGE = 0x00, | ||
| 26 | APE_OPP_100 = 0x02, | ||
| 27 | APE_OPP_50 = 0x03, | ||
| 28 | }; | ||
| 29 | |||
| 30 | #endif /* __MACH_PRCMU_DEFS_H */ | ||
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-regs.h b/arch/arm/mach-ux500/include/mach/prcmu-regs.h index 8885f39a6421..455467e88791 100644 --- a/arch/arm/mach-ux500/include/mach/prcmu-regs.h +++ b/arch/arm/mach-ux500/include/mach/prcmu-regs.h | |||
| @@ -1,10 +1,15 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright (c) 2009 ST-Ericsson SA | 2 | * Copyright (C) STMicroelectronics 2009 |
| 3 | * Copyright (C) ST-Ericsson SA 2010 | ||
| 3 | * | 4 | * |
| 4 | * This program is free software; you can redistribute it and/or modify | 5 | * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> |
| 5 | * it under the terms of the GNU General Public License version 2 | 6 | * Author: Sundar Iyer <sundar.iyer@stericsson.com> |
| 6 | * as published by the Free Software Foundation. | 7 | * |
| 8 | * License Terms: GNU General Public License v2 | ||
| 9 | * | ||
| 10 | * PRCM Unit registers | ||
| 7 | */ | 11 | */ |
| 12 | |||
| 8 | #ifndef __MACH_PRCMU_REGS_H | 13 | #ifndef __MACH_PRCMU_REGS_H |
| 9 | #define __MACH_PRCMU_REGS_H | 14 | #define __MACH_PRCMU_REGS_H |
| 10 | 15 | ||
| @@ -88,4 +93,4 @@ | |||
| 88 | /* Miscellaneous unit registers */ | 93 | /* Miscellaneous unit registers */ |
| 89 | #define PRCM_DSI_SW_RESET (_PRCMU_BASE + 0x324) | 94 | #define PRCM_DSI_SW_RESET (_PRCMU_BASE + 0x324) |
| 90 | 95 | ||
| 91 | #endif /* __MACH_PRCMU__REGS_H */ | 96 | #endif /* __MACH_PRCMU_REGS_H */ |
diff --git a/arch/arm/mach-ux500/include/mach/prcmu.h b/arch/arm/mach-ux500/include/mach/prcmu.h index 549843ff6dbe..c49e456162ef 100644 --- a/arch/arm/mach-ux500/include/mach/prcmu.h +++ b/arch/arm/mach-ux500/include/mach/prcmu.h | |||
| @@ -2,14 +2,27 @@ | |||
| 2 | * Copyright (C) STMicroelectronics 2009 | 2 | * Copyright (C) STMicroelectronics 2009 |
| 3 | * Copyright (C) ST-Ericsson SA 2010 | 3 | * Copyright (C) ST-Ericsson SA 2010 |
| 4 | * | 4 | * |
| 5 | * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> | ||
| 6 | * Author: Sundar Iyer <sundar.iyer@stericsson.com> | ||
| 7 | * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> | ||
| 8 | * | ||
| 5 | * License Terms: GNU General Public License v2 | 9 | * License Terms: GNU General Public License v2 |
| 6 | * | 10 | * |
| 7 | * PRCMU f/w APIs | 11 | * PRCM Unit f/w API |
| 8 | */ | 12 | */ |
| 9 | #ifndef __MACH_PRCMU_H | 13 | #ifndef __MACH_PRCMU_H |
| 10 | #define __MACH_PRCMU_H | 14 | #define __MACH_PRCMU_H |
| 15 | #include <mach/prcmu-defs.h> | ||
| 11 | 16 | ||
| 17 | void __init prcmu_early_init(void); | ||
| 12 | int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); | 18 | int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); |
| 13 | int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); | 19 | int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); |
| 20 | int prcmu_set_ape_opp(enum prcmu_ape_opp opp); | ||
| 21 | int prcmu_set_cpu_opp(enum prcmu_cpu_opp opp); | ||
| 22 | int prcmu_set_ape_cpu_opps(enum prcmu_ape_opp ape_opp, | ||
| 23 | enum prcmu_cpu_opp cpu_opp); | ||
| 24 | int prcmu_get_ape_opp(void); | ||
| 25 | int prcmu_get_cpu_opp(void); | ||
| 26 | bool prcmu_has_arm_maxopp(void); | ||
| 14 | 27 | ||
| 15 | #endif /* __MACH_PRCMU_H */ | 28 | #endif /* __MACH_PRCMU_H */ |
diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h index 54bbe648bf58..a7d363fdb4cd 100644 --- a/arch/arm/mach-ux500/include/mach/setup.h +++ b/arch/arm/mach-ux500/include/mach/setup.h | |||
| @@ -14,18 +14,23 @@ | |||
| 14 | #include <asm/mach/time.h> | 14 | #include <asm/mach/time.h> |
| 15 | #include <linux/init.h> | 15 | #include <linux/init.h> |
| 16 | 16 | ||
| 17 | extern void __init ux500_map_io(void); | 17 | void __init ux500_map_io(void); |
| 18 | extern void __init u5500_map_io(void); | 18 | extern void __init u5500_map_io(void); |
| 19 | extern void __init u8500_map_io(void); | 19 | extern void __init u8500_map_io(void); |
| 20 | 20 | ||
| 21 | extern void __init ux500_init_devices(void); | ||
| 22 | extern void __init u5500_init_devices(void); | 21 | extern void __init u5500_init_devices(void); |
| 23 | extern void __init u8500_init_devices(void); | 22 | extern void __init u8500_init_devices(void); |
| 24 | 23 | ||
| 25 | extern void __init ux500_init_irq(void); | 24 | extern void __init ux500_init_irq(void); |
| 25 | |||
| 26 | extern void __init u5500_sdi_init(void); | ||
| 27 | |||
| 28 | extern void __init db5500_dma_init(void); | ||
| 29 | |||
| 26 | /* We re-use nomadik_timer for this platform */ | 30 | /* We re-use nomadik_timer for this platform */ |
| 27 | extern void nmdk_timer_init(void); | 31 | extern void nmdk_timer_init(void); |
| 28 | 32 | ||
| 33 | struct amba_device; | ||
| 29 | extern void __init amba_add_devices(struct amba_device *devs[], int num); | 34 | extern void __init amba_add_devices(struct amba_device *devs[], int num); |
| 30 | 35 | ||
| 31 | struct sys_timer; | 36 | struct sys_timer; |
diff --git a/arch/arm/mach-ux500/include/mach/smp.h b/arch/arm/mach-ux500/include/mach/smp.h index 197e8417375e..ca2b15b1b3b1 100644 --- a/arch/arm/mach-ux500/include/mach/smp.h +++ b/arch/arm/mach-ux500/include/mach/smp.h | |||
| @@ -10,7 +10,6 @@ | |||
| 10 | #define ASMARM_ARCH_SMP_H | 10 | #define ASMARM_ARCH_SMP_H |
| 11 | 11 | ||
| 12 | #include <asm/hardware/gic.h> | 12 | #include <asm/hardware/gic.h> |
| 13 | #include <asm/smp_mpidr.h> | ||
| 14 | 13 | ||
| 15 | /* This is required to wakeup the secondary core */ | 14 | /* This is required to wakeup the secondary core */ |
| 16 | extern void u8500_secondary_startup(void); | 15 | extern void u8500_secondary_startup(void); |
| @@ -18,8 +17,8 @@ extern void u8500_secondary_startup(void); | |||
| 18 | /* | 17 | /* |
| 19 | * We use IRQ1 as the IPI | 18 | * We use IRQ1 as the IPI |
| 20 | */ | 19 | */ |
| 21 | static inline void smp_cross_call(const struct cpumask *mask) | 20 | static inline void smp_cross_call(const struct cpumask *mask, int ipi) |
| 22 | { | 21 | { |
| 23 | gic_raise_softirq(mask, 1); | 22 | gic_raise_softirq(mask, ipi); |
| 24 | } | 23 | } |
| 25 | #endif | 24 | #endif |
diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h index 0271ca0a83df..9a6614c6808e 100644 --- a/arch/arm/mach-ux500/include/mach/uncompress.h +++ b/arch/arm/mach-ux500/include/mach/uncompress.h | |||
| @@ -19,38 +19,43 @@ | |||
| 19 | #define __ASM_ARCH_UNCOMPRESS_H | 19 | #define __ASM_ARCH_UNCOMPRESS_H |
| 20 | 20 | ||
| 21 | #include <asm/setup.h> | 21 | #include <asm/setup.h> |
| 22 | #include <asm/mach-types.h> | ||
| 22 | #include <linux/io.h> | 23 | #include <linux/io.h> |
| 24 | #include <linux/amba/serial.h> | ||
| 23 | #include <mach/hardware.h> | 25 | #include <mach/hardware.h> |
| 24 | 26 | ||
| 25 | #define U8500_UART_DR 0x80007000 | 27 | static u32 ux500_uart_base; |
| 26 | #define U8500_UART_LCRH 0x8000702c | ||
| 27 | #define U8500_UART_CR 0x80007030 | ||
| 28 | #define U8500_UART_FR 0x80007018 | ||
| 29 | 28 | ||
| 30 | static void putc(const char c) | 29 | static void putc(const char c) |
| 31 | { | 30 | { |
| 32 | /* Do nothing if the UART is not enabled. */ | 31 | /* Do nothing if the UART is not enabled. */ |
| 33 | if (!(__raw_readb(U8500_UART_CR) & 0x1)) | 32 | if (!(__raw_readb(ux500_uart_base + UART011_CR) & 0x1)) |
| 34 | return; | 33 | return; |
| 35 | 34 | ||
| 36 | if (c == '\n') | 35 | if (c == '\n') |
| 37 | putc('\r'); | 36 | putc('\r'); |
| 38 | 37 | ||
| 39 | while (__raw_readb(U8500_UART_FR) & (1 << 5)) | 38 | while (__raw_readb(ux500_uart_base + UART01x_FR) & (1 << 5)) |
| 40 | barrier(); | 39 | barrier(); |
| 41 | __raw_writeb(c, U8500_UART_DR); | 40 | __raw_writeb(c, ux500_uart_base + UART01x_DR); |
| 42 | } | 41 | } |
| 43 | 42 | ||
| 44 | static void flush(void) | 43 | static void flush(void) |
| 45 | { | 44 | { |
| 46 | if (!(__raw_readb(U8500_UART_CR) & 0x1)) | 45 | if (!(__raw_readb(ux500_uart_base + UART011_CR) & 0x1)) |
| 47 | return; | 46 | return; |
| 48 | while (__raw_readb(U8500_UART_FR) & (1 << 3)) | 47 | while (__raw_readb(ux500_uart_base + UART01x_FR) & (1 << 3)) |
| 49 | barrier(); | 48 | barrier(); |
| 50 | } | 49 | } |
| 51 | 50 | ||
| 52 | static inline void arch_decomp_setup(void) | 51 | static inline void arch_decomp_setup(void) |
| 53 | { | 52 | { |
| 53 | if (machine_is_u8500()) | ||
| 54 | ux500_uart_base = U8500_UART2_BASE; | ||
| 55 | else if (machine_is_u5500()) | ||
| 56 | ux500_uart_base = U5500_UART0_BASE; | ||
| 57 | else /* not much can be done to help here */ | ||
| 58 | ux500_uart_base = U8500_UART2_BASE; | ||
| 54 | } | 59 | } |
| 55 | 60 | ||
| 56 | #define arch_decomp_wdog() /* nothing to do here */ | 61 | #define arch_decomp_wdog() /* nothing to do here */ |
diff --git a/arch/arm/mach-ux500/mbox.c b/arch/arm/mach-ux500/mbox-db5500.c index 63435389c544..cbf15718fc3c 100644 --- a/arch/arm/mach-ux500/mbox.c +++ b/arch/arm/mach-ux500/mbox-db5500.c | |||
| @@ -38,7 +38,7 @@ | |||
| 38 | #include <linux/debugfs.h> | 38 | #include <linux/debugfs.h> |
| 39 | #include <linux/seq_file.h> | 39 | #include <linux/seq_file.h> |
| 40 | #include <linux/completion.h> | 40 | #include <linux/completion.h> |
| 41 | #include <mach/mbox.h> | 41 | #include <mach/mbox-db5500.h> |
| 42 | 42 | ||
| 43 | #define MBOX_NAME "mbox" | 43 | #define MBOX_NAME "mbox" |
| 44 | 44 | ||
diff --git a/arch/arm/mach-ux500/modem_irq.c b/arch/arm/mach-ux500/modem-irq-db5500.c index 3187f8871169..e1296a7447c8 100644 --- a/arch/arm/mach-ux500/modem_irq.c +++ b/arch/arm/mach-ux500/modem-irq-db5500.c | |||
| @@ -12,6 +12,8 @@ | |||
| 12 | #include <linux/io.h> | 12 | #include <linux/io.h> |
| 13 | #include <linux/slab.h> | 13 | #include <linux/slab.h> |
| 14 | 14 | ||
| 15 | #include <mach/id.h> | ||
| 16 | |||
| 15 | #define MODEM_INTCON_BASE_ADDR 0xBFFD3000 | 17 | #define MODEM_INTCON_BASE_ADDR 0xBFFD3000 |
| 16 | #define MODEM_INTCON_SIZE 0xFFF | 18 | #define MODEM_INTCON_SIZE 0xFFF |
| 17 | 19 | ||
| @@ -101,6 +103,9 @@ static int modem_irq_init(void) | |||
| 101 | static struct irq_chip modem_irq_chip; | 103 | static struct irq_chip modem_irq_chip; |
| 102 | struct modem_irq *mi; | 104 | struct modem_irq *mi; |
| 103 | 105 | ||
| 106 | if (!cpu_is_u5500()) | ||
| 107 | return -ENODEV; | ||
| 108 | |||
| 104 | pr_info("modem_irq: Set up IRQ handler for incoming modem IRQ %d\n", | 109 | pr_info("modem_irq: Set up IRQ handler for incoming modem IRQ %d\n", |
| 105 | IRQ_DB5500_MODEM); | 110 | IRQ_DB5500_MODEM); |
| 106 | 111 | ||
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c index 9e4c678de785..4fff4d408417 100644 --- a/arch/arm/mach-ux500/platsmp.c +++ b/arch/arm/mach-ux500/platsmp.c | |||
| @@ -18,39 +18,57 @@ | |||
| 18 | #include <linux/io.h> | 18 | #include <linux/io.h> |
| 19 | 19 | ||
| 20 | #include <asm/cacheflush.h> | 20 | #include <asm/cacheflush.h> |
| 21 | #include <asm/localtimer.h> | ||
| 22 | #include <asm/smp_scu.h> | 21 | #include <asm/smp_scu.h> |
| 23 | #include <mach/hardware.h> | 22 | #include <mach/hardware.h> |
| 23 | #include <mach/setup.h> | ||
| 24 | 24 | ||
| 25 | /* | 25 | /* |
| 26 | * control for which core is the next to come out of the secondary | 26 | * control for which core is the next to come out of the secondary |
| 27 | * boot "holding pen" | 27 | * boot "holding pen" |
| 28 | */ | 28 | */ |
| 29 | volatile int __cpuinitdata pen_release = -1; | 29 | volatile int pen_release = -1; |
| 30 | 30 | ||
| 31 | static unsigned int __init get_core_count(void) | 31 | /* |
| 32 | * Write pen_release in a way that is guaranteed to be visible to all | ||
| 33 | * observers, irrespective of whether they're taking part in coherency | ||
| 34 | * or not. This is necessary for the hotplug code to work reliably. | ||
| 35 | */ | ||
| 36 | static void write_pen_release(int val) | ||
| 32 | { | 37 | { |
| 33 | return scu_get_core_count(__io_address(UX500_SCU_BASE)); | 38 | pen_release = val; |
| 39 | smp_wmb(); | ||
| 40 | __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); | ||
| 41 | outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); | ||
| 42 | } | ||
| 43 | |||
| 44 | static void __iomem *scu_base_addr(void) | ||
| 45 | { | ||
| 46 | if (cpu_is_u5500()) | ||
| 47 | return __io_address(U5500_SCU_BASE); | ||
| 48 | else if (cpu_is_u8500()) | ||
| 49 | return __io_address(U8500_SCU_BASE); | ||
| 50 | else | ||
| 51 | ux500_unknown_soc(); | ||
| 52 | |||
| 53 | return NULL; | ||
| 34 | } | 54 | } |
| 35 | 55 | ||
| 36 | static DEFINE_SPINLOCK(boot_lock); | 56 | static DEFINE_SPINLOCK(boot_lock); |
| 37 | 57 | ||
| 38 | void __cpuinit platform_secondary_init(unsigned int cpu) | 58 | void __cpuinit platform_secondary_init(unsigned int cpu) |
| 39 | { | 59 | { |
| 40 | trace_hardirqs_off(); | ||
| 41 | |||
| 42 | /* | 60 | /* |
| 43 | * if any interrupts are already enabled for the primary | 61 | * if any interrupts are already enabled for the primary |
| 44 | * core (e.g. timer irq), then they will not have been enabled | 62 | * core (e.g. timer irq), then they will not have been enabled |
| 45 | * for us: do so | 63 | * for us: do so |
| 46 | */ | 64 | */ |
| 47 | gic_cpu_init(0, __io_address(UX500_GIC_CPU_BASE)); | 65 | gic_secondary_init(0); |
| 48 | 66 | ||
| 49 | /* | 67 | /* |
| 50 | * let the primary processor know we're out of the | 68 | * let the primary processor know we're out of the |
| 51 | * pen, then head off into the C entry point | 69 | * pen, then head off into the C entry point |
| 52 | */ | 70 | */ |
| 53 | pen_release = -1; | 71 | write_pen_release(-1); |
| 54 | 72 | ||
| 55 | /* | 73 | /* |
| 56 | * Synchronise with the boot thread. | 74 | * Synchronise with the boot thread. |
| @@ -74,11 +92,9 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) | |||
| 74 | * the holding pen - release it, then wait for it to flag | 92 | * the holding pen - release it, then wait for it to flag |
| 75 | * that it has been released by resetting pen_release. | 93 | * that it has been released by resetting pen_release. |
| 76 | */ | 94 | */ |
| 77 | pen_release = cpu; | 95 | write_pen_release(cpu); |
| 78 | __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); | ||
| 79 | outer_clean_range(__pa(&pen_release), __pa(&pen_release) + 1); | ||
| 80 | 96 | ||
| 81 | smp_cross_call(cpumask_of(cpu)); | 97 | smp_cross_call(cpumask_of(cpu), 1); |
| 82 | 98 | ||
| 83 | timeout = jiffies + (1 * HZ); | 99 | timeout = jiffies + (1 * HZ); |
| 84 | while (time_before(jiffies, timeout)) { | 100 | while (time_before(jiffies, timeout)) { |
| @@ -97,8 +113,14 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) | |||
| 97 | 113 | ||
| 98 | static void __init wakeup_secondary(void) | 114 | static void __init wakeup_secondary(void) |
| 99 | { | 115 | { |
| 100 | /* nobody is to be released from the pen yet */ | 116 | void __iomem *backupram; |
| 101 | pen_release = -1; | 117 | |
| 118 | if (cpu_is_u5500()) | ||
| 119 | backupram = __io_address(U5500_BACKUPRAM0_BASE); | ||
| 120 | else if (cpu_is_u8500()) | ||
| 121 | backupram = __io_address(U8500_BACKUPRAM0_BASE); | ||
| 122 | else | ||
| 123 | ux500_unknown_soc(); | ||
| 102 | 124 | ||
| 103 | /* | 125 | /* |
| 104 | * write the address of secondary startup into the backup ram register | 126 | * write the address of secondary startup into the backup ram register |
| @@ -106,15 +128,13 @@ static void __init wakeup_secondary(void) | |||
| 106 | * backup ram register at offset 0x1FF0, which is what boot rom code | 128 | * backup ram register at offset 0x1FF0, which is what boot rom code |
| 107 | * is waiting for. This would wake up the secondary core from WFE | 129 | * is waiting for. This would wake up the secondary core from WFE |
| 108 | */ | 130 | */ |
| 109 | #define U8500_CPU1_JUMPADDR_OFFSET 0x1FF4 | 131 | #define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4 |
| 110 | __raw_writel(virt_to_phys(u8500_secondary_startup), | 132 | __raw_writel(virt_to_phys(u8500_secondary_startup), |
| 111 | __io_address(UX500_BACKUPRAM0_BASE) + | 133 | backupram + UX500_CPU1_JUMPADDR_OFFSET); |
| 112 | U8500_CPU1_JUMPADDR_OFFSET); | ||
| 113 | 134 | ||
| 114 | #define U8500_CPU1_WAKEMAGIC_OFFSET 0x1FF0 | 135 | #define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0 |
| 115 | __raw_writel(0xA1FEED01, | 136 | __raw_writel(0xA1FEED01, |
| 116 | __io_address(UX500_BACKUPRAM0_BASE) + | 137 | backupram + UX500_CPU1_WAKEMAGIC_OFFSET); |
| 117 | U8500_CPU1_WAKEMAGIC_OFFSET); | ||
| 118 | 138 | ||
| 119 | /* make sure write buffer is drained */ | 139 | /* make sure write buffer is drained */ |
| 120 | mb(); | 140 | mb(); |
| @@ -126,40 +146,27 @@ static void __init wakeup_secondary(void) | |||
| 126 | */ | 146 | */ |
| 127 | void __init smp_init_cpus(void) | 147 | void __init smp_init_cpus(void) |
| 128 | { | 148 | { |
| 129 | unsigned int i, ncores = get_core_count(); | 149 | void __iomem *scu_base = scu_base_addr(); |
| 150 | unsigned int i, ncores; | ||
| 130 | 151 | ||
| 131 | for (i = 0; i < ncores; i++) | 152 | ncores = scu_base ? scu_get_core_count(scu_base) : 1; |
| 132 | set_cpu_possible(i, true); | ||
| 133 | } | ||
| 134 | |||
| 135 | void __init smp_prepare_cpus(unsigned int max_cpus) | ||
| 136 | { | ||
| 137 | unsigned int ncores = get_core_count(); | ||
| 138 | unsigned int cpu = smp_processor_id(); | ||
| 139 | int i; | ||
| 140 | 153 | ||
| 141 | /* sanity check */ | 154 | /* sanity check */ |
| 142 | if (ncores == 0) { | 155 | if (ncores > NR_CPUS) { |
| 143 | printk(KERN_ERR | ||
| 144 | "U8500: strange CM count of 0? Default to 1\n"); | ||
| 145 | ncores = 1; | ||
| 146 | } | ||
| 147 | |||
| 148 | if (ncores > num_possible_cpus()) { | ||
| 149 | printk(KERN_WARNING | 156 | printk(KERN_WARNING |
| 150 | "U8500: no. of cores (%d) greater than configured " | 157 | "U8500: no. of cores (%d) greater than configured " |
| 151 | "maximum of %d - clipping\n", | 158 | "maximum of %d - clipping\n", |
| 152 | ncores, num_possible_cpus()); | 159 | ncores, NR_CPUS); |
| 153 | ncores = num_possible_cpus(); | 160 | ncores = NR_CPUS; |
| 154 | } | 161 | } |
| 155 | 162 | ||
| 156 | smp_store_cpu_info(cpu); | 163 | for (i = 0; i < ncores; i++) |
| 164 | set_cpu_possible(i, true); | ||
| 165 | } | ||
| 157 | 166 | ||
| 158 | /* | 167 | void __init platform_smp_prepare_cpus(unsigned int max_cpus) |
| 159 | * are we trying to boot more cores than exist? | 168 | { |
| 160 | */ | 169 | int i; |
| 161 | if (max_cpus > ncores) | ||
| 162 | max_cpus = ncores; | ||
| 163 | 170 | ||
| 164 | /* | 171 | /* |
| 165 | * Initialise the present map, which describes the set of CPUs | 172 | * Initialise the present map, which describes the set of CPUs |
| @@ -168,13 +175,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus) | |||
| 168 | for (i = 0; i < max_cpus; i++) | 175 | for (i = 0; i < max_cpus; i++) |
| 169 | set_cpu_present(i, true); | 176 | set_cpu_present(i, true); |
| 170 | 177 | ||
| 171 | if (max_cpus > 1) { | 178 | scu_enable(scu_base_addr()); |
| 172 | /* | 179 | wakeup_secondary(); |
| 173 | * Enable the local timer or broadcast device for the | ||
| 174 | * boot CPU, but only if we have more than one CPU. | ||
| 175 | */ | ||
| 176 | percpu_timer_setup(); | ||
| 177 | scu_enable(__io_address(UX500_SCU_BASE)); | ||
| 178 | wakeup_secondary(); | ||
| 179 | } | ||
| 180 | } | 180 | } |
diff --git a/arch/arm/mach-ux500/prcmu.c b/arch/arm/mach-ux500/prcmu.c index 293274d1342a..c522d26ef348 100644 --- a/arch/arm/mach-ux500/prcmu.c +++ b/arch/arm/mach-ux500/prcmu.c | |||
| @@ -1,10 +1,14 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) ST Ericsson SA 2010 | 2 | * Copyright (C) STMicroelectronics 2009 |
| 3 | * Copyright (C) ST-Ericsson SA 2010 | ||
| 3 | * | 4 | * |
| 4 | * License Terms: GNU General Public License v2 | 5 | * License Terms: GNU General Public License v2 |
| 6 | * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> | ||
| 7 | * Author: Sundar Iyer <sundar.iyer@stericsson.com> | ||
| 5 | * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> | 8 | * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> |
| 6 | * | 9 | * |
| 7 | * U8500 PRCMU driver. | 10 | * U8500 PRCM Unit interface driver |
| 11 | * | ||
| 8 | */ | 12 | */ |
| 9 | #include <linux/kernel.h> | 13 | #include <linux/kernel.h> |
| 10 | #include <linux/module.h> | 14 | #include <linux/module.h> |
| @@ -19,11 +23,26 @@ | |||
| 19 | 23 | ||
| 20 | #include <mach/hardware.h> | 24 | #include <mach/hardware.h> |
| 21 | #include <mach/prcmu-regs.h> | 25 | #include <mach/prcmu-regs.h> |
| 26 | #include <mach/prcmu-defs.h> | ||
| 27 | |||
| 28 | /* Global var to runtime determine TCDM base for v2 or v1 */ | ||
| 29 | static __iomem void *tcdm_base; | ||
| 30 | |||
| 31 | #define _MBOX_HEADER (tcdm_base + 0xFE8) | ||
| 32 | #define MBOX_HEADER_REQ_MB0 (_MBOX_HEADER + 0x0) | ||
| 33 | |||
| 34 | #define REQ_MB1 (tcdm_base + 0xFD0) | ||
| 35 | #define REQ_MB5 (tcdm_base + 0xE44) | ||
| 22 | 36 | ||
| 23 | #define PRCMU_TCDM_BASE __io_address(U8500_PRCMU_TCDM_BASE) | 37 | #define REQ_MB1_ARMOPP (REQ_MB1 + 0x0) |
| 38 | #define REQ_MB1_APEOPP (REQ_MB1 + 0x1) | ||
| 39 | #define REQ_MB1_BOOSTOPP (REQ_MB1 + 0x2) | ||
| 24 | 40 | ||
| 25 | #define REQ_MB5 (PRCMU_TCDM_BASE + 0xE44) | 41 | #define ACK_MB1 (tcdm_base + 0xE04) |
| 26 | #define ACK_MB5 (PRCMU_TCDM_BASE + 0xDF4) | 42 | #define ACK_MB5 (tcdm_base + 0xDF4) |
| 43 | |||
| 44 | #define ACK_MB1_CURR_ARMOPP (ACK_MB1 + 0x0) | ||
| 45 | #define ACK_MB1_CURR_APEOPP (ACK_MB1 + 0x1) | ||
| 27 | 46 | ||
| 28 | #define REQ_MB5_I2C_SLAVE_OP (REQ_MB5) | 47 | #define REQ_MB5_I2C_SLAVE_OP (REQ_MB5) |
| 29 | #define REQ_MB5_I2C_HW_BITS (REQ_MB5 + 1) | 48 | #define REQ_MB5_I2C_HW_BITS (REQ_MB5 + 1) |
| @@ -33,10 +52,33 @@ | |||
| 33 | #define ACK_MB5_I2C_STATUS (ACK_MB5 + 1) | 52 | #define ACK_MB5_I2C_STATUS (ACK_MB5 + 1) |
| 34 | #define ACK_MB5_I2C_VAL (ACK_MB5 + 3) | 53 | #define ACK_MB5_I2C_VAL (ACK_MB5 + 3) |
| 35 | 54 | ||
| 36 | #define I2C_WRITE(slave) ((slave) << 1) | 55 | #define PRCM_AVS_VARM_MAX_OPP (tcdm_base + 0x2E4) |
| 37 | #define I2C_READ(slave) (((slave) << 1) | BIT(0)) | 56 | #define PRCM_AVS_ISMODEENABLE 7 |
| 57 | #define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE) | ||
| 58 | |||
| 59 | #define I2C_WRITE(slave) \ | ||
| 60 | (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0)) | ||
| 61 | #define I2C_READ(slave) \ | ||
| 62 | (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0) | BIT(0)) | ||
| 38 | #define I2C_STOP_EN BIT(3) | 63 | #define I2C_STOP_EN BIT(3) |
| 39 | 64 | ||
| 65 | enum mb1_h { | ||
| 66 | MB1H_ARM_OPP = 1, | ||
| 67 | MB1H_APE_OPP, | ||
| 68 | MB1H_ARM_APE_OPP, | ||
| 69 | }; | ||
| 70 | |||
| 71 | static struct { | ||
| 72 | struct mutex lock; | ||
| 73 | struct completion work; | ||
| 74 | struct { | ||
| 75 | u8 arm_opp; | ||
| 76 | u8 ape_opp; | ||
| 77 | u8 arm_status; | ||
| 78 | u8 ape_status; | ||
| 79 | } ack; | ||
| 80 | } mb1_transfer; | ||
| 81 | |||
| 40 | enum ack_mb5_status { | 82 | enum ack_mb5_status { |
| 41 | I2C_WR_OK = 0x01, | 83 | I2C_WR_OK = 0x01, |
| 42 | I2C_RD_OK = 0x02, | 84 | I2C_RD_OK = 0x02, |
| @@ -145,6 +187,104 @@ unlock_and_return: | |||
| 145 | } | 187 | } |
| 146 | EXPORT_SYMBOL(prcmu_abb_write); | 188 | EXPORT_SYMBOL(prcmu_abb_write); |
| 147 | 189 | ||
| 190 | static int set_ape_cpu_opps(u8 header, enum prcmu_ape_opp ape_opp, | ||
| 191 | enum prcmu_cpu_opp cpu_opp) | ||
| 192 | { | ||
| 193 | bool do_ape; | ||
| 194 | bool do_arm; | ||
| 195 | int err = 0; | ||
| 196 | |||
| 197 | do_ape = ((header == MB1H_APE_OPP) || (header == MB1H_ARM_APE_OPP)); | ||
| 198 | do_arm = ((header == MB1H_ARM_OPP) || (header == MB1H_ARM_APE_OPP)); | ||
| 199 | |||
| 200 | mutex_lock(&mb1_transfer.lock); | ||
| 201 | |||
| 202 | while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1)) | ||
| 203 | cpu_relax(); | ||
| 204 | |||
| 205 | writeb(0, MBOX_HEADER_REQ_MB0); | ||
| 206 | writeb(cpu_opp, REQ_MB1_ARMOPP); | ||
| 207 | writeb(ape_opp, REQ_MB1_APEOPP); | ||
| 208 | writeb(0, REQ_MB1_BOOSTOPP); | ||
| 209 | writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET); | ||
| 210 | wait_for_completion(&mb1_transfer.work); | ||
| 211 | if ((do_ape) && (mb1_transfer.ack.ape_status != 0)) | ||
| 212 | err = -EIO; | ||
| 213 | if ((do_arm) && (mb1_transfer.ack.arm_status != 0)) | ||
| 214 | err = -EIO; | ||
| 215 | |||
| 216 | mutex_unlock(&mb1_transfer.lock); | ||
| 217 | |||
| 218 | return err; | ||
| 219 | } | ||
| 220 | |||
| 221 | /** | ||
| 222 | * prcmu_set_ape_opp() - Set the OPP of the APE. | ||
| 223 | * @opp: The OPP to set. | ||
| 224 | * | ||
| 225 | * This function sets the OPP of the APE. | ||
| 226 | */ | ||
| 227 | int prcmu_set_ape_opp(enum prcmu_ape_opp opp) | ||
| 228 | { | ||
| 229 | return set_ape_cpu_opps(MB1H_APE_OPP, opp, APE_OPP_NO_CHANGE); | ||
| 230 | } | ||
| 231 | EXPORT_SYMBOL(prcmu_set_ape_opp); | ||
| 232 | |||
| 233 | /** | ||
| 234 | * prcmu_set_cpu_opp() - Set the OPP of the CPU. | ||
| 235 | * @opp: The OPP to set. | ||
| 236 | * | ||
| 237 | * This function sets the OPP of the CPU. | ||
| 238 | */ | ||
| 239 | int prcmu_set_cpu_opp(enum prcmu_cpu_opp opp) | ||
| 240 | { | ||
| 241 | return set_ape_cpu_opps(MB1H_ARM_OPP, CPU_OPP_NO_CHANGE, opp); | ||
| 242 | } | ||
| 243 | EXPORT_SYMBOL(prcmu_set_cpu_opp); | ||
| 244 | |||
| 245 | /** | ||
| 246 | * prcmu_set_ape_cpu_opps() - Set the OPPs of the APE and the CPU. | ||
| 247 | * @ape_opp: The APE OPP to set. | ||
| 248 | * @cpu_opp: The CPU OPP to set. | ||
| 249 | * | ||
| 250 | * This function sets the OPPs of the APE and the CPU. | ||
| 251 | */ | ||
| 252 | int prcmu_set_ape_cpu_opps(enum prcmu_ape_opp ape_opp, | ||
| 253 | enum prcmu_cpu_opp cpu_opp) | ||
| 254 | { | ||
| 255 | return set_ape_cpu_opps(MB1H_ARM_APE_OPP, ape_opp, cpu_opp); | ||
| 256 | } | ||
| 257 | EXPORT_SYMBOL(prcmu_set_ape_cpu_opps); | ||
| 258 | |||
| 259 | /** | ||
| 260 | * prcmu_get_ape_opp() - Get the OPP of the APE. | ||
| 261 | * | ||
| 262 | * This function gets the OPP of the APE. | ||
| 263 | */ | ||
| 264 | enum prcmu_ape_opp prcmu_get_ape_opp(void) | ||
| 265 | { | ||
| 266 | return readb(ACK_MB1_CURR_APEOPP); | ||
| 267 | } | ||
| 268 | EXPORT_SYMBOL(prcmu_get_ape_opp); | ||
| 269 | |||
| 270 | /** | ||
| 271 | * prcmu_get_cpu_opp() - Get the OPP of the CPU. | ||
| 272 | * | ||
| 273 | * This function gets the OPP of the CPU. The OPP is specified in %%. | ||
| 274 | * PRCMU_OPP_EXT is a special OPP value, not specified in %%. | ||
| 275 | */ | ||
| 276 | int prcmu_get_cpu_opp(void) | ||
| 277 | { | ||
| 278 | return readb(ACK_MB1_CURR_ARMOPP); | ||
| 279 | } | ||
| 280 | EXPORT_SYMBOL(prcmu_get_cpu_opp); | ||
| 281 | |||
| 282 | bool prcmu_has_arm_maxopp(void) | ||
| 283 | { | ||
| 284 | return (readb(PRCM_AVS_VARM_MAX_OPP) & PRCM_AVS_ISMODEENABLE_MASK) | ||
| 285 | == PRCM_AVS_ISMODEENABLE_MASK; | ||
| 286 | } | ||
| 287 | |||
| 148 | static void read_mailbox_0(void) | 288 | static void read_mailbox_0(void) |
| 149 | { | 289 | { |
| 150 | writel(MBOX_BIT(0), PRCM_ARM_IT1_CLEAR); | 290 | writel(MBOX_BIT(0), PRCM_ARM_IT1_CLEAR); |
| @@ -152,6 +292,9 @@ static void read_mailbox_0(void) | |||
| 152 | 292 | ||
| 153 | static void read_mailbox_1(void) | 293 | static void read_mailbox_1(void) |
| 154 | { | 294 | { |
| 295 | mb1_transfer.ack.arm_opp = readb(ACK_MB1_CURR_ARMOPP); | ||
| 296 | mb1_transfer.ack.ape_opp = readb(ACK_MB1_CURR_APEOPP); | ||
| 297 | complete(&mb1_transfer.work); | ||
| 155 | writel(MBOX_BIT(1), PRCM_ARM_IT1_CLEAR); | 298 | writel(MBOX_BIT(1), PRCM_ARM_IT1_CLEAR); |
| 156 | } | 299 | } |
| 157 | 300 | ||
| @@ -217,15 +360,35 @@ static irqreturn_t prcmu_irq_handler(int irq, void *data) | |||
| 217 | return IRQ_HANDLED; | 360 | return IRQ_HANDLED; |
| 218 | } | 361 | } |
| 219 | 362 | ||
| 363 | void __init prcmu_early_init(void) | ||
| 364 | { | ||
| 365 | if (cpu_is_u8500v11() || cpu_is_u8500ed()) { | ||
| 366 | tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE_V1); | ||
| 367 | } else if (cpu_is_u8500v2()) { | ||
| 368 | tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE); | ||
| 369 | } else { | ||
| 370 | pr_err("prcmu: Unsupported chip version\n"); | ||
| 371 | BUG(); | ||
| 372 | } | ||
| 373 | } | ||
| 374 | |||
| 220 | static int __init prcmu_init(void) | 375 | static int __init prcmu_init(void) |
| 221 | { | 376 | { |
| 377 | if (cpu_is_u8500ed()) { | ||
| 378 | pr_err("prcmu: Unsupported chip version\n"); | ||
| 379 | return 0; | ||
| 380 | } | ||
| 381 | |||
| 382 | mutex_init(&mb1_transfer.lock); | ||
| 383 | init_completion(&mb1_transfer.work); | ||
| 222 | mutex_init(&mb5_transfer.lock); | 384 | mutex_init(&mb5_transfer.lock); |
| 223 | init_completion(&mb5_transfer.work); | 385 | init_completion(&mb5_transfer.work); |
| 224 | 386 | ||
| 225 | /* Clean up the mailbox interrupts after pre-kernel code. */ | 387 | /* Clean up the mailbox interrupts after pre-kernel code. */ |
| 226 | writel((MBOX_BIT(NUM_MBOX) - 1), PRCM_ARM_IT1_CLEAR); | 388 | writel((MBOX_BIT(NUM_MBOX) - 1), PRCM_ARM_IT1_CLEAR); |
| 227 | 389 | ||
| 228 | return request_irq(IRQ_PRCMU, prcmu_irq_handler, 0, "prcmu", NULL); | 390 | return request_irq(IRQ_DB8500_PRCMU1, prcmu_irq_handler, 0, |
| 391 | "prcmu", NULL); | ||
| 229 | } | 392 | } |
| 230 | 393 | ||
| 231 | arch_initcall(prcmu_init); | 394 | arch_initcall(prcmu_init); |
diff --git a/arch/arm/mach-versatile/Kconfig b/arch/arm/mach-versatile/Kconfig index c781f30c8368..3f7b5e9d83c5 100644 --- a/arch/arm/mach-versatile/Kconfig +++ b/arch/arm/mach-versatile/Kconfig | |||
| @@ -4,6 +4,7 @@ menu "Versatile platform type" | |||
| 4 | config ARCH_VERSATILE_PB | 4 | config ARCH_VERSATILE_PB |
| 5 | bool "Support Versatile/PB platform" | 5 | bool "Support Versatile/PB platform" |
| 6 | select CPU_ARM926T | 6 | select CPU_ARM926T |
| 7 | select MIGHT_HAVE_PCI | ||
| 7 | default y | 8 | default y |
| 8 | help | 9 | help |
| 9 | Include support for the ARM(R) Versatile/PB platform. | 10 | Include support for the ARM(R) Versatile/PB platform. |
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index e38acb0f89c8..13a83e45a33b 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c | |||
| @@ -31,8 +31,8 @@ | |||
| 31 | #include <linux/amba/pl022.h> | 31 | #include <linux/amba/pl022.h> |
| 32 | #include <linux/io.h> | 32 | #include <linux/io.h> |
| 33 | #include <linux/gfp.h> | 33 | #include <linux/gfp.h> |
| 34 | #include <linux/clkdev.h> | ||
| 34 | 35 | ||
| 35 | #include <asm/clkdev.h> | ||
| 36 | #include <asm/system.h> | 36 | #include <asm/system.h> |
| 37 | #include <asm/irq.h> | 37 | #include <asm/irq.h> |
| 38 | #include <asm/leds.h> | 38 | #include <asm/leds.h> |
| @@ -46,10 +46,11 @@ | |||
| 46 | #include <asm/mach/irq.h> | 46 | #include <asm/mach/irq.h> |
| 47 | #include <asm/mach/time.h> | 47 | #include <asm/mach/time.h> |
| 48 | #include <asm/mach/map.h> | 48 | #include <asm/mach/map.h> |
| 49 | #include <mach/clkdev.h> | ||
| 50 | #include <mach/hardware.h> | 49 | #include <mach/hardware.h> |
| 51 | #include <mach/platform.h> | 50 | #include <mach/platform.h> |
| 52 | #include <plat/timer-sp.h> | 51 | #include <asm/hardware/timer-sp.h> |
| 52 | |||
| 53 | #include <plat/sched_clock.h> | ||
| 53 | 54 | ||
| 54 | #include "core.h" | 55 | #include "core.h" |
| 55 | 56 | ||
| @@ -886,6 +887,12 @@ void __init versatile_init(void) | |||
| 886 | } | 887 | } |
| 887 | 888 | ||
| 888 | /* | 889 | /* |
| 890 | * The sched_clock counter | ||
| 891 | */ | ||
| 892 | #define REFCOUNTER (__io_address(VERSATILE_SYS_BASE) + \ | ||
| 893 | VERSATILE_SYS_24MHz_OFFSET) | ||
| 894 | |||
| 895 | /* | ||
| 889 | * Where is the timer (VA)? | 896 | * Where is the timer (VA)? |
| 890 | */ | 897 | */ |
| 891 | #define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE) | 898 | #define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE) |
| @@ -900,6 +907,8 @@ static void __init versatile_timer_init(void) | |||
| 900 | { | 907 | { |
| 901 | u32 val; | 908 | u32 val; |
| 902 | 909 | ||
| 910 | versatile_sched_clock_init(REFCOUNTER, 24000000); | ||
| 911 | |||
| 903 | /* | 912 | /* |
| 904 | * set clock frequency: | 913 | * set clock frequency: |
| 905 | * VERSATILE_REFCLK is 32KHz | 914 | * VERSATILE_REFCLK is 32KHz |
diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile index 1b71b77ade22..2c0ac7de2814 100644 --- a/arch/arm/mach-vexpress/Makefile +++ b/arch/arm/mach-vexpress/Makefile | |||
| @@ -5,4 +5,5 @@ | |||
| 5 | obj-y := v2m.o | 5 | obj-y := v2m.o |
| 6 | obj-$(CONFIG_ARCH_VEXPRESS_CA9X4) += ct-ca9x4.o | 6 | obj-$(CONFIG_ARCH_VEXPRESS_CA9X4) += ct-ca9x4.o |
| 7 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o | 7 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o |
| 8 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o | ||
| 8 | obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o | 9 | obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o |
diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h index 57dd95ce41f9..362780d868de 100644 --- a/arch/arm/mach-vexpress/core.h +++ b/arch/arm/mach-vexpress/core.h | |||
| @@ -22,5 +22,3 @@ struct map_desc; | |||
| 22 | 22 | ||
| 23 | void v2m_map_io(struct map_desc *tile, size_t num); | 23 | void v2m_map_io(struct map_desc *tile, size_t num); |
| 24 | extern struct sys_timer v2m_timer; | 24 | extern struct sys_timer v2m_timer; |
| 25 | |||
| 26 | extern void __iomem *gic_cpu_base_addr; | ||
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c index fd25ccd7272f..e628402b754c 100644 --- a/arch/arm/mach-vexpress/ct-ca9x4.c +++ b/arch/arm/mach-vexpress/ct-ca9x4.c | |||
| @@ -8,8 +8,8 @@ | |||
| 8 | #include <linux/platform_device.h> | 8 | #include <linux/platform_device.h> |
| 9 | #include <linux/amba/bus.h> | 9 | #include <linux/amba/bus.h> |
| 10 | #include <linux/amba/clcd.h> | 10 | #include <linux/amba/clcd.h> |
| 11 | #include <linux/clkdev.h> | ||
| 11 | 12 | ||
| 12 | #include <asm/clkdev.h> | ||
| 13 | #include <asm/pgtable.h> | 13 | #include <asm/pgtable.h> |
| 14 | #include <asm/hardware/arm_timer.h> | 14 | #include <asm/hardware/arm_timer.h> |
| 15 | #include <asm/hardware/cache-l2x0.h> | 15 | #include <asm/hardware/cache-l2x0.h> |
| @@ -18,10 +18,9 @@ | |||
| 18 | #include <asm/pmu.h> | 18 | #include <asm/pmu.h> |
| 19 | #include <asm/smp_twd.h> | 19 | #include <asm/smp_twd.h> |
| 20 | 20 | ||
| 21 | #include <mach/clkdev.h> | ||
| 22 | #include <mach/ct-ca9x4.h> | 21 | #include <mach/ct-ca9x4.h> |
| 23 | 22 | ||
| 24 | #include <plat/timer-sp.h> | 23 | #include <asm/hardware/timer-sp.h> |
| 25 | 24 | ||
| 26 | #include <asm/mach/arch.h> | 25 | #include <asm/mach/arch.h> |
| 27 | #include <asm/mach/map.h> | 26 | #include <asm/mach/map.h> |
| @@ -60,13 +59,10 @@ static void __init ct_ca9x4_map_io(void) | |||
| 60 | v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc)); | 59 | v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc)); |
| 61 | } | 60 | } |
| 62 | 61 | ||
| 63 | void __iomem *gic_cpu_base_addr; | ||
| 64 | |||
| 65 | static void __init ct_ca9x4_init_irq(void) | 62 | static void __init ct_ca9x4_init_irq(void) |
| 66 | { | 63 | { |
| 67 | gic_cpu_base_addr = MMIO_P2V(A9_MPCORE_GIC_CPU); | 64 | gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST), |
| 68 | gic_dist_init(0, MMIO_P2V(A9_MPCORE_GIC_DIST), 29); | 65 | MMIO_P2V(A9_MPCORE_GIC_CPU)); |
| 69 | gic_cpu_init(0, gic_cpu_base_addr); | ||
| 70 | } | 66 | } |
| 71 | 67 | ||
| 72 | #if 0 | 68 | #if 0 |
diff --git a/arch/arm/mach-vexpress/hotplug.c b/arch/arm/mach-vexpress/hotplug.c new file mode 100644 index 000000000000..ea4cbfb90a66 --- /dev/null +++ b/arch/arm/mach-vexpress/hotplug.c | |||
| @@ -0,0 +1,128 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-realview/hotplug.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2002 ARM Ltd. | ||
| 5 | * All Rights Reserved | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/errno.h> | ||
| 13 | #include <linux/smp.h> | ||
| 14 | |||
| 15 | #include <asm/cacheflush.h> | ||
| 16 | |||
| 17 | extern volatile int pen_release; | ||
| 18 | |||
| 19 | static inline void cpu_enter_lowpower(void) | ||
| 20 | { | ||
| 21 | unsigned int v; | ||
| 22 | |||
| 23 | flush_cache_all(); | ||
| 24 | asm volatile( | ||
| 25 | "mcr p15, 0, %1, c7, c5, 0\n" | ||
| 26 | " mcr p15, 0, %1, c7, c10, 4\n" | ||
| 27 | /* | ||
| 28 | * Turn off coherency | ||
| 29 | */ | ||
| 30 | " mrc p15, 0, %0, c1, c0, 1\n" | ||
| 31 | " bic %0, %0, %3\n" | ||
| 32 | " mcr p15, 0, %0, c1, c0, 1\n" | ||
| 33 | " mrc p15, 0, %0, c1, c0, 0\n" | ||
| 34 | " bic %0, %0, %2\n" | ||
| 35 | " mcr p15, 0, %0, c1, c0, 0\n" | ||
| 36 | : "=&r" (v) | ||
| 37 | : "r" (0), "Ir" (CR_C), "Ir" (0x40) | ||
| 38 | : "cc"); | ||
| 39 | } | ||
| 40 | |||
| 41 | static inline void cpu_leave_lowpower(void) | ||
| 42 | { | ||
| 43 | unsigned int v; | ||
| 44 | |||
| 45 | asm volatile( | ||
| 46 | "mrc p15, 0, %0, c1, c0, 0\n" | ||
| 47 | " orr %0, %0, %1\n" | ||
| 48 | " mcr p15, 0, %0, c1, c0, 0\n" | ||
| 49 | " mrc p15, 0, %0, c1, c0, 1\n" | ||
| 50 | " orr %0, %0, %2\n" | ||
| 51 | " mcr p15, 0, %0, c1, c0, 1\n" | ||
| 52 | : "=&r" (v) | ||
| 53 | : "Ir" (CR_C), "Ir" (0x40) | ||
| 54 | : "cc"); | ||
| 55 | } | ||
| 56 | |||
| 57 | static inline void platform_do_lowpower(unsigned int cpu, int *spurious) | ||
| 58 | { | ||
| 59 | /* | ||
| 60 | * there is no power-control hardware on this platform, so all | ||
| 61 | * we can do is put the core into WFI; this is safe as the calling | ||
| 62 | * code will have already disabled interrupts | ||
| 63 | */ | ||
| 64 | for (;;) { | ||
| 65 | /* | ||
| 66 | * here's the WFI | ||
| 67 | */ | ||
| 68 | asm(".word 0xe320f003\n" | ||
| 69 | : | ||
| 70 | : | ||
| 71 | : "memory", "cc"); | ||
| 72 | |||
| 73 | if (pen_release == cpu) { | ||
| 74 | /* | ||
| 75 | * OK, proper wakeup, we're done | ||
| 76 | */ | ||
| 77 | break; | ||
| 78 | } | ||
| 79 | |||
| 80 | /* | ||
| 81 | * Getting here, means that we have come out of WFI without | ||
| 82 | * having been woken up - this shouldn't happen | ||
| 83 | * | ||
| 84 | * Just note it happening - when we're woken, we can report | ||
| 85 | * its occurrence. | ||
| 86 | */ | ||
| 87 | (*spurious)++; | ||
| 88 | } | ||
| 89 | } | ||
| 90 | |||
| 91 | int platform_cpu_kill(unsigned int cpu) | ||
| 92 | { | ||
| 93 | return 1; | ||
| 94 | } | ||
| 95 | |||
| 96 | /* | ||
| 97 | * platform-specific code to shutdown a CPU | ||
| 98 | * | ||
| 99 | * Called with IRQs disabled | ||
| 100 | */ | ||
| 101 | void platform_cpu_die(unsigned int cpu) | ||
| 102 | { | ||
| 103 | int spurious = 0; | ||
| 104 | |||
| 105 | /* | ||
| 106 | * we're ready for shutdown now, so do it | ||
| 107 | */ | ||
| 108 | cpu_enter_lowpower(); | ||
| 109 | platform_do_lowpower(cpu, &spurious); | ||
| 110 | |||
| 111 | /* | ||
| 112 | * bring this CPU back into the world of cache | ||
| 113 | * coherency, and then restore interrupts | ||
| 114 | */ | ||
| 115 | cpu_leave_lowpower(); | ||
| 116 | |||
| 117 | if (spurious) | ||
| 118 | pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious); | ||
| 119 | } | ||
| 120 | |||
| 121 | int platform_cpu_disable(unsigned int cpu) | ||
| 122 | { | ||
| 123 | /* | ||
| 124 | * we don't allow CPU 0 to be shutdown (it is still too special | ||
| 125 | * e.g. clock tick interrupts) | ||
| 126 | */ | ||
| 127 | return cpu == 0 ? -EPERM : 0; | ||
| 128 | } | ||
diff --git a/arch/arm/mach-vexpress/include/mach/entry-macro.S b/arch/arm/mach-vexpress/include/mach/entry-macro.S index 20e9fb514f0a..73c11297509e 100644 --- a/arch/arm/mach-vexpress/include/mach/entry-macro.S +++ b/arch/arm/mach-vexpress/include/mach/entry-macro.S | |||
| @@ -1,67 +1,7 @@ | |||
| 1 | #include <asm/hardware/gic.h> | 1 | #include <asm/hardware/entry-macro-gic.S> |
| 2 | 2 | ||
| 3 | .macro disable_fiq | 3 | .macro disable_fiq |
| 4 | .endm | 4 | .endm |
| 5 | 5 | ||
| 6 | .macro get_irqnr_preamble, base, tmp | ||
| 7 | ldr \base, =gic_cpu_base_addr | ||
| 8 | ldr \base, [\base] | ||
| 9 | .endm | ||
| 10 | |||
| 11 | .macro arch_ret_to_user, tmp1, tmp2 | 6 | .macro arch_ret_to_user, tmp1, tmp2 |
| 12 | .endm | 7 | .endm |
| 13 | |||
| 14 | /* | ||
| 15 | * The interrupt numbering scheme is defined in the | ||
| 16 | * interrupt controller spec. To wit: | ||
| 17 | * | ||
| 18 | * Interrupts 0-15 are IPI | ||
| 19 | * 16-28 are reserved | ||
| 20 | * 29-31 are local. We allow 30 to be used for the watchdog. | ||
| 21 | * 32-1020 are global | ||
| 22 | * 1021-1022 are reserved | ||
| 23 | * 1023 is "spurious" (no interrupt) | ||
| 24 | * | ||
| 25 | * For now, we ignore all local interrupts so only return an interrupt if it's | ||
| 26 | * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs. | ||
| 27 | * | ||
| 28 | * A simple read from the controller will tell us the number of the highest | ||
| 29 | * priority enabled interrupt. We then just need to check whether it is in the | ||
| 30 | * valid range for an IRQ (30-1020 inclusive). | ||
| 31 | */ | ||
| 32 | |||
| 33 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 34 | ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */ | ||
| 35 | ldr \tmp, =1021 | ||
| 36 | bic \irqnr, \irqstat, #0x1c00 | ||
| 37 | cmp \irqnr, #29 | ||
| 38 | cmpcc \irqnr, \irqnr | ||
| 39 | cmpne \irqnr, \tmp | ||
| 40 | cmpcs \irqnr, \irqnr | ||
| 41 | .endm | ||
| 42 | |||
| 43 | /* We assume that irqstat (the raw value of the IRQ acknowledge | ||
| 44 | * register) is preserved from the macro above. | ||
| 45 | * If there is an IPI, we immediately signal end of interrupt on the | ||
| 46 | * controller, since this requires the original irqstat value which | ||
| 47 | * we won't easily be able to recreate later. | ||
| 48 | */ | ||
| 49 | |||
| 50 | .macro test_for_ipi, irqnr, irqstat, base, tmp | ||
| 51 | bic \irqnr, \irqstat, #0x1c00 | ||
| 52 | cmp \irqnr, #16 | ||
| 53 | strcc \irqstat, [\base, #GIC_CPU_EOI] | ||
| 54 | cmpcs \irqnr, \irqnr | ||
| 55 | .endm | ||
| 56 | |||
| 57 | /* As above, this assumes that irqstat and base are preserved.. */ | ||
| 58 | |||
| 59 | .macro test_for_ltirq, irqnr, irqstat, base, tmp | ||
| 60 | bic \irqnr, \irqstat, #0x1c00 | ||
| 61 | mov \tmp, #0 | ||
| 62 | cmp \irqnr, #29 | ||
| 63 | moveq \tmp, #1 | ||
| 64 | streq \irqstat, [\base, #GIC_CPU_EOI] | ||
| 65 | cmp \tmp, #0 | ||
| 66 | .endm | ||
| 67 | |||
diff --git a/arch/arm/mach-vexpress/include/mach/smp.h b/arch/arm/mach-vexpress/include/mach/smp.h index 5a6da4fd247e..4c05e4a9713a 100644 --- a/arch/arm/mach-vexpress/include/mach/smp.h +++ b/arch/arm/mach-vexpress/include/mach/smp.h | |||
| @@ -2,13 +2,12 @@ | |||
| 2 | #define __MACH_SMP_H | 2 | #define __MACH_SMP_H |
| 3 | 3 | ||
| 4 | #include <asm/hardware/gic.h> | 4 | #include <asm/hardware/gic.h> |
| 5 | #include <asm/smp_mpidr.h> | ||
| 6 | 5 | ||
| 7 | /* | 6 | /* |
| 8 | * We use IRQ1 as the IPI | 7 | * We use IRQ1 as the IPI |
| 9 | */ | 8 | */ |
| 10 | static inline void smp_cross_call(const struct cpumask *mask) | 9 | static inline void smp_cross_call(const struct cpumask *mask, int ipi) |
| 11 | { | 10 | { |
| 12 | gic_raise_softirq(mask, 1); | 11 | gic_raise_softirq(mask, ipi); |
| 13 | } | 12 | } |
| 14 | #endif | 13 | #endif |
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c index 670970699ba9..b1687b6abe63 100644 --- a/arch/arm/mach-vexpress/platsmp.c +++ b/arch/arm/mach-vexpress/platsmp.c | |||
| @@ -17,7 +17,6 @@ | |||
| 17 | #include <linux/io.h> | 17 | #include <linux/io.h> |
| 18 | 18 | ||
| 19 | #include <asm/cacheflush.h> | 19 | #include <asm/cacheflush.h> |
| 20 | #include <asm/localtimer.h> | ||
| 21 | #include <asm/smp_scu.h> | 20 | #include <asm/smp_scu.h> |
| 22 | #include <asm/unified.h> | 21 | #include <asm/unified.h> |
| 23 | 22 | ||
| @@ -35,6 +34,19 @@ extern void vexpress_secondary_startup(void); | |||
| 35 | */ | 34 | */ |
| 36 | volatile int __cpuinitdata pen_release = -1; | 35 | volatile int __cpuinitdata pen_release = -1; |
| 37 | 36 | ||
| 37 | /* | ||
| 38 | * Write pen_release in a way that is guaranteed to be visible to all | ||
| 39 | * observers, irrespective of whether they're taking part in coherency | ||
| 40 | * or not. This is necessary for the hotplug code to work reliably. | ||
| 41 | */ | ||
| 42 | static void write_pen_release(int val) | ||
| 43 | { | ||
| 44 | pen_release = val; | ||
| 45 | smp_wmb(); | ||
| 46 | __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); | ||
| 47 | outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); | ||
| 48 | } | ||
| 49 | |||
| 38 | static void __iomem *scu_base_addr(void) | 50 | static void __iomem *scu_base_addr(void) |
| 39 | { | 51 | { |
| 40 | return MMIO_P2V(A9_MPCORE_SCU); | 52 | return MMIO_P2V(A9_MPCORE_SCU); |
| @@ -44,21 +56,18 @@ static DEFINE_SPINLOCK(boot_lock); | |||
| 44 | 56 | ||
| 45 | void __cpuinit platform_secondary_init(unsigned int cpu) | 57 | void __cpuinit platform_secondary_init(unsigned int cpu) |
| 46 | { | 58 | { |
| 47 | trace_hardirqs_off(); | ||
| 48 | |||
| 49 | /* | 59 | /* |
| 50 | * if any interrupts are already enabled for the primary | 60 | * if any interrupts are already enabled for the primary |
| 51 | * core (e.g. timer irq), then they will not have been enabled | 61 | * core (e.g. timer irq), then they will not have been enabled |
| 52 | * for us: do so | 62 | * for us: do so |
| 53 | */ | 63 | */ |
| 54 | gic_cpu_init(0, gic_cpu_base_addr); | 64 | gic_secondary_init(0); |
| 55 | 65 | ||
| 56 | /* | 66 | /* |
| 57 | * let the primary processor know we're out of the | 67 | * let the primary processor know we're out of the |
| 58 | * pen, then head off into the C entry point | 68 | * pen, then head off into the C entry point |
| 59 | */ | 69 | */ |
| 60 | pen_release = -1; | 70 | write_pen_release(-1); |
| 61 | smp_wmb(); | ||
| 62 | 71 | ||
| 63 | /* | 72 | /* |
| 64 | * Synchronise with the boot thread. | 73 | * Synchronise with the boot thread. |
| @@ -83,16 +92,14 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) | |||
| 83 | * since we haven't sent them a soft interrupt, they shouldn't | 92 | * since we haven't sent them a soft interrupt, they shouldn't |
| 84 | * be there. | 93 | * be there. |
| 85 | */ | 94 | */ |
| 86 | pen_release = cpu; | 95 | write_pen_release(cpu); |
| 87 | __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); | ||
| 88 | outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); | ||
| 89 | 96 | ||
| 90 | /* | 97 | /* |
| 91 | * Send the secondary CPU a soft interrupt, thereby causing | 98 | * Send the secondary CPU a soft interrupt, thereby causing |
| 92 | * the boot monitor to read the system wide flags register, | 99 | * the boot monitor to read the system wide flags register, |
| 93 | * and branch to the address found there. | 100 | * and branch to the address found there. |
| 94 | */ | 101 | */ |
| 95 | smp_cross_call(cpumask_of(cpu)); | 102 | smp_cross_call(cpumask_of(cpu), 1); |
| 96 | 103 | ||
| 97 | timeout = jiffies + (1 * HZ); | 104 | timeout = jiffies + (1 * HZ); |
| 98 | while (time_before(jiffies, timeout)) { | 105 | while (time_before(jiffies, timeout)) { |
| @@ -124,13 +131,6 @@ void __init smp_init_cpus(void) | |||
| 124 | ncores = scu_base ? scu_get_core_count(scu_base) : 1; | 131 | ncores = scu_base ? scu_get_core_count(scu_base) : 1; |
| 125 | 132 | ||
| 126 | /* sanity check */ | 133 | /* sanity check */ |
| 127 | if (ncores == 0) { | ||
| 128 | printk(KERN_ERR | ||
| 129 | "vexpress: strange CM count of 0? Default to 1\n"); | ||
| 130 | |||
| 131 | ncores = 1; | ||
| 132 | } | ||
| 133 | |||
| 134 | if (ncores > NR_CPUS) { | 134 | if (ncores > NR_CPUS) { |
| 135 | printk(KERN_WARNING | 135 | printk(KERN_WARNING |
| 136 | "vexpress: no. of cores (%d) greater than configured " | 136 | "vexpress: no. of cores (%d) greater than configured " |
| @@ -143,20 +143,10 @@ void __init smp_init_cpus(void) | |||
| 143 | set_cpu_possible(i, true); | 143 | set_cpu_possible(i, true); |
| 144 | } | 144 | } |
| 145 | 145 | ||
| 146 | void __init smp_prepare_cpus(unsigned int max_cpus) | 146 | void __init platform_smp_prepare_cpus(unsigned int max_cpus) |
| 147 | { | 147 | { |
| 148 | unsigned int ncores = num_possible_cpus(); | ||
| 149 | unsigned int cpu = smp_processor_id(); | ||
| 150 | int i; | 148 | int i; |
| 151 | 149 | ||
| 152 | smp_store_cpu_info(cpu); | ||
| 153 | |||
| 154 | /* | ||
| 155 | * are we trying to boot more cores than exist? | ||
| 156 | */ | ||
| 157 | if (max_cpus > ncores) | ||
| 158 | max_cpus = ncores; | ||
| 159 | |||
| 160 | /* | 150 | /* |
| 161 | * Initialise the present map, which describes the set of CPUs | 151 | * Initialise the present map, which describes the set of CPUs |
| 162 | * actually populated at the present time. | 152 | * actually populated at the present time. |
| @@ -164,27 +154,15 @@ void __init smp_prepare_cpus(unsigned int max_cpus) | |||
| 164 | for (i = 0; i < max_cpus; i++) | 154 | for (i = 0; i < max_cpus; i++) |
| 165 | set_cpu_present(i, true); | 155 | set_cpu_present(i, true); |
| 166 | 156 | ||
| 157 | scu_enable(scu_base_addr()); | ||
| 158 | |||
| 167 | /* | 159 | /* |
| 168 | * Initialise the SCU if there are more than one CPU and let | 160 | * Write the address of secondary startup into the |
| 169 | * them know where to start. | 161 | * system-wide flags register. The boot monitor waits |
| 162 | * until it receives a soft interrupt, and then the | ||
| 163 | * secondary CPU branches to this address. | ||
| 170 | */ | 164 | */ |
| 171 | if (max_cpus > 1) { | 165 | writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR)); |
| 172 | /* | 166 | writel(BSYM(virt_to_phys(vexpress_secondary_startup)), |
| 173 | * Enable the local timer or broadcast device for the | 167 | MMIO_P2V(V2M_SYS_FLAGSSET)); |
| 174 | * boot CPU, but only if we have more than one CPU. | ||
| 175 | */ | ||
| 176 | percpu_timer_setup(); | ||
| 177 | |||
| 178 | scu_enable(scu_base_addr()); | ||
| 179 | |||
| 180 | /* | ||
| 181 | * Write the address of secondary startup into the | ||
| 182 | * system-wide flags register. The boot monitor waits | ||
| 183 | * until it receives a soft interrupt, and then the | ||
| 184 | * secondary CPU branches to this address. | ||
| 185 | */ | ||
| 186 | writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR)); | ||
| 187 | writel(BSYM(virt_to_phys(vexpress_secondary_startup)), | ||
| 188 | MMIO_P2V(V2M_SYS_FLAGSSET)); | ||
| 189 | } | ||
| 190 | } | 168 | } |
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c index 7eaa232180a5..a9ed3428a2fa 100644 --- a/arch/arm/mach-vexpress/v2m.c +++ b/arch/arm/mach-vexpress/v2m.c | |||
| @@ -11,18 +11,18 @@ | |||
| 11 | #include <linux/spinlock.h> | 11 | #include <linux/spinlock.h> |
| 12 | #include <linux/sysdev.h> | 12 | #include <linux/sysdev.h> |
| 13 | #include <linux/usb/isp1760.h> | 13 | #include <linux/usb/isp1760.h> |
| 14 | #include <linux/clkdev.h> | ||
| 14 | 15 | ||
| 15 | #include <asm/clkdev.h> | ||
| 16 | #include <asm/sizes.h> | 16 | #include <asm/sizes.h> |
| 17 | #include <asm/mach/flash.h> | 17 | #include <asm/mach/flash.h> |
| 18 | #include <asm/mach/map.h> | 18 | #include <asm/mach/map.h> |
| 19 | #include <asm/mach/time.h> | 19 | #include <asm/mach/time.h> |
| 20 | #include <asm/hardware/arm_timer.h> | 20 | #include <asm/hardware/arm_timer.h> |
| 21 | #include <asm/hardware/timer-sp.h> | ||
| 21 | 22 | ||
| 22 | #include <mach/clkdev.h> | ||
| 23 | #include <mach/motherboard.h> | 23 | #include <mach/motherboard.h> |
| 24 | 24 | ||
| 25 | #include <plat/timer-sp.h> | 25 | #include <plat/sched_clock.h> |
| 26 | 26 | ||
| 27 | #include "core.h" | 27 | #include "core.h" |
| 28 | 28 | ||
| @@ -50,6 +50,8 @@ void __init v2m_map_io(struct map_desc *tile, size_t num) | |||
| 50 | 50 | ||
| 51 | static void __init v2m_timer_init(void) | 51 | static void __init v2m_timer_init(void) |
| 52 | { | 52 | { |
| 53 | versatile_sched_clock_init(MMIO_P2V(V2M_SYS_24MHZ), 24000000); | ||
| 54 | |||
| 53 | writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL); | 55 | writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL); |
| 54 | writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL); | 56 | writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL); |
| 55 | 57 | ||
diff --git a/arch/arm/mach-w90x900/clock.h b/arch/arm/mach-w90x900/clock.h index c56ddab3d912..b88a1b16b2e9 100644 --- a/arch/arm/mach-w90x900/clock.h +++ b/arch/arm/mach-w90x900/clock.h | |||
| @@ -10,7 +10,7 @@ | |||
| 10 | * the Free Software Foundation; either version 2 of the License. | 10 | * the Free Software Foundation; either version 2 of the License. |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | #include <asm/clkdev.h> | 13 | #include <linux/clkdev.h> |
| 14 | 14 | ||
| 15 | void nuc900_clk_enable(struct clk *clk, int enable); | 15 | void nuc900_clk_enable(struct clk *clk, int enable); |
| 16 | void nuc900_subclk_enable(struct clk *clk, int enable); | 16 | void nuc900_subclk_enable(struct clk *clk, int enable); |
diff --git a/arch/arm/mach-w90x900/time.c b/arch/arm/mach-w90x900/time.c index b80f769bc135..4b089cb930dc 100644 --- a/arch/arm/mach-w90x900/time.c +++ b/arch/arm/mach-w90x900/time.c | |||
| @@ -153,7 +153,6 @@ static struct clocksource clocksource_nuc900 = { | |||
| 153 | .rating = 200, | 153 | .rating = 200, |
| 154 | .read = nuc900_get_cycles, | 154 | .read = nuc900_get_cycles, |
| 155 | .mask = CLOCKSOURCE_MASK(TDR_SHIFT), | 155 | .mask = CLOCKSOURCE_MASK(TDR_SHIFT), |
| 156 | .shift = 10, | ||
| 157 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 156 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 158 | }; | 157 | }; |
| 159 | 158 | ||
| @@ -176,9 +175,7 @@ static void __init nuc900_clocksource_init(void) | |||
| 176 | val |= (COUNTEN | PERIOD | PRESCALE); | 175 | val |= (COUNTEN | PERIOD | PRESCALE); |
| 177 | __raw_writel(val, REG_TCSR1); | 176 | __raw_writel(val, REG_TCSR1); |
| 178 | 177 | ||
| 179 | clocksource_nuc900.mult = | 178 | clocksource_register_hz(&clocksource_nuc900, rate); |
| 180 | clocksource_khz2mult((rate / 1000), clocksource_nuc900.shift); | ||
| 181 | clocksource_register(&clocksource_nuc900); | ||
| 182 | } | 179 | } |
| 183 | 180 | ||
| 184 | static void __init nuc900_timer_init(void) | 181 | static void __init nuc900_timer_init(void) |
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 4414a01e1e8a..fcc1e628e050 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig | |||
| @@ -382,6 +382,12 @@ config CPU_FEROCEON_OLD_ID | |||
| 382 | for which the CPU ID is equal to the ARM926 ID. | 382 | for which the CPU ID is equal to the ARM926 ID. |
| 383 | Relevant for Feroceon-1850 and early Feroceon-2850. | 383 | Relevant for Feroceon-1850 and early Feroceon-2850. |
| 384 | 384 | ||
| 385 | # Marvell PJ4 | ||
| 386 | config CPU_PJ4 | ||
| 387 | bool | ||
| 388 | select CPU_V7 | ||
| 389 | select ARM_THUMBEE | ||
| 390 | |||
| 385 | # ARMv6 | 391 | # ARMv6 |
| 386 | config CPU_V6 | 392 | config CPU_V6 |
| 387 | bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || ARCH_DOVE | 393 | bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || ARCH_DOVE |
| @@ -599,6 +605,14 @@ config CPU_CP15_MPU | |||
| 599 | help | 605 | help |
| 600 | Processor has the CP15 register, which has MPU related registers. | 606 | Processor has the CP15 register, which has MPU related registers. |
| 601 | 607 | ||
| 608 | config CPU_USE_DOMAINS | ||
| 609 | bool | ||
| 610 | depends on MMU | ||
| 611 | default y if !CPU_32v6K | ||
| 612 | help | ||
| 613 | This option enables or disables the use of domain switching | ||
| 614 | via the set_fs() function. | ||
| 615 | |||
| 602 | # | 616 | # |
| 603 | # CPU supports 36-bit I/O | 617 | # CPU supports 36-bit I/O |
| 604 | # | 618 | # |
| @@ -628,6 +642,33 @@ config ARM_THUMBEE | |||
| 628 | Say Y here if you have a CPU with the ThumbEE extension and code to | 642 | Say Y here if you have a CPU with the ThumbEE extension and code to |
| 629 | make use of it. Say N for code that can run on CPUs without ThumbEE. | 643 | make use of it. Say N for code that can run on CPUs without ThumbEE. |
| 630 | 644 | ||
| 645 | config SWP_EMULATE | ||
| 646 | bool "Emulate SWP/SWPB instructions" | ||
| 647 | depends on CPU_V7 | ||
| 648 | select HAVE_PROC_CPU if PROC_FS | ||
| 649 | default y if SMP | ||
| 650 | help | ||
| 651 | ARMv6 architecture deprecates use of the SWP/SWPB instructions. | ||
| 652 | ARMv7 multiprocessing extensions introduce the ability to disable | ||
| 653 | these instructions, triggering an undefined instruction exception | ||
| 654 | when executed. Say Y here to enable software emulation of these | ||
| 655 | instructions for userspace (not kernel) using LDREX/STREX. | ||
| 656 | Also creates /proc/cpu/swp_emulation for statistics. | ||
| 657 | |||
| 658 | In some older versions of glibc [<=2.8] SWP is used during futex | ||
| 659 | trylock() operations with the assumption that the code will not | ||
| 660 | be preempted. This invalid assumption may be more likely to fail | ||
| 661 | with SWP emulation enabled, leading to deadlock of the user | ||
| 662 | application. | ||
| 663 | |||
| 664 | NOTE: when accessing uncached shared regions, LDREX/STREX rely | ||
| 665 | on an external transaction monitoring block called a global | ||
| 666 | monitor to maintain update atomicity. If your system does not | ||
| 667 | implement a global monitor, this option can cause programs that | ||
| 668 | perform SWP operations to uncached memory to deadlock. | ||
| 669 | |||
| 670 | If unsure, say Y. | ||
| 671 | |||
| 631 | config CPU_BIG_ENDIAN | 672 | config CPU_BIG_ENDIAN |
| 632 | bool "Build big-endian kernel" | 673 | bool "Build big-endian kernel" |
| 633 | depends on ARCH_SUPPORTS_BIG_ENDIAN | 674 | depends on ARCH_SUPPORTS_BIG_ENDIAN |
| @@ -772,7 +813,7 @@ config CACHE_L2X0 | |||
| 772 | depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ | 813 | depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ |
| 773 | REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \ | 814 | REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \ |
| 774 | ARCH_NOMADIK || ARCH_OMAP4 || ARCH_S5PV310 || ARCH_TEGRA || \ | 815 | ARCH_NOMADIK || ARCH_OMAP4 || ARCH_S5PV310 || ARCH_TEGRA || \ |
| 775 | ARCH_U8500 || ARCH_VEXPRESS_CA9X4 | 816 | ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE |
| 776 | default y | 817 | default y |
| 777 | select OUTER_CACHE | 818 | select OUTER_CACHE |
| 778 | select OUTER_CACHE_SYNC | 819 | select OUTER_CACHE_SYNC |
| @@ -789,7 +830,7 @@ config CACHE_PL310 | |||
| 789 | 830 | ||
| 790 | config CACHE_TAUROS2 | 831 | config CACHE_TAUROS2 |
| 791 | bool "Enable the Tauros2 L2 cache controller" | 832 | bool "Enable the Tauros2 L2 cache controller" |
| 792 | depends on (ARCH_DOVE || ARCH_MMP) | 833 | depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4) |
| 793 | default y | 834 | default y |
| 794 | select OUTER_CACHE | 835 | select OUTER_CACHE |
| 795 | help | 836 | help |
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index d63b6c413758..00d74a04af3a 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile | |||
| @@ -5,8 +5,8 @@ | |||
| 5 | obj-y := dma-mapping.o extable.o fault.o init.o \ | 5 | obj-y := dma-mapping.o extable.o fault.o init.o \ |
| 6 | iomap.o | 6 | iomap.o |
| 7 | 7 | ||
| 8 | obj-$(CONFIG_MMU) += fault-armv.o flush.o ioremap.o mmap.o \ | 8 | obj-$(CONFIG_MMU) += fault-armv.o flush.o idmap.o ioremap.o \ |
| 9 | pgd.o mmu.o vmregion.o | 9 | mmap.o pgd.o mmu.o vmregion.o |
| 10 | 10 | ||
| 11 | ifneq ($(CONFIG_MMU),y) | 11 | ifneq ($(CONFIG_MMU),y) |
| 12 | obj-y += nommu.o | 12 | obj-y += nommu.o |
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 809f1bf9fa29..6b48e0a3d7aa 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c | |||
| @@ -312,7 +312,7 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp, | |||
| 312 | addr = page_address(page); | 312 | addr = page_address(page); |
| 313 | 313 | ||
| 314 | if (addr) | 314 | if (addr) |
| 315 | *handle = page_to_dma(dev, page); | 315 | *handle = pfn_to_dma(dev, page_to_pfn(page)); |
| 316 | 316 | ||
| 317 | return addr; | 317 | return addr; |
| 318 | } | 318 | } |
| @@ -407,7 +407,7 @@ void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr | |||
| 407 | if (!arch_is_coherent()) | 407 | if (!arch_is_coherent()) |
| 408 | __dma_free_remap(cpu_addr, size); | 408 | __dma_free_remap(cpu_addr, size); |
| 409 | 409 | ||
| 410 | __dma_free_buffer(dma_to_page(dev, handle), size); | 410 | __dma_free_buffer(pfn_to_page(dma_to_pfn(dev, handle)), size); |
| 411 | } | 411 | } |
| 412 | EXPORT_SYMBOL(dma_free_coherent); | 412 | EXPORT_SYMBOL(dma_free_coherent); |
| 413 | 413 | ||
| @@ -555,17 +555,20 @@ int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, | |||
| 555 | struct scatterlist *s; | 555 | struct scatterlist *s; |
| 556 | int i, j; | 556 | int i, j; |
| 557 | 557 | ||
| 558 | BUG_ON(!valid_dma_direction(dir)); | ||
| 559 | |||
| 558 | for_each_sg(sg, s, nents, i) { | 560 | for_each_sg(sg, s, nents, i) { |
| 559 | s->dma_address = dma_map_page(dev, sg_page(s), s->offset, | 561 | s->dma_address = __dma_map_page(dev, sg_page(s), s->offset, |
| 560 | s->length, dir); | 562 | s->length, dir); |
| 561 | if (dma_mapping_error(dev, s->dma_address)) | 563 | if (dma_mapping_error(dev, s->dma_address)) |
| 562 | goto bad_mapping; | 564 | goto bad_mapping; |
| 563 | } | 565 | } |
| 566 | debug_dma_map_sg(dev, sg, nents, nents, dir); | ||
| 564 | return nents; | 567 | return nents; |
| 565 | 568 | ||
| 566 | bad_mapping: | 569 | bad_mapping: |
| 567 | for_each_sg(sg, s, i, j) | 570 | for_each_sg(sg, s, i, j) |
| 568 | dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir); | 571 | __dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir); |
| 569 | return 0; | 572 | return 0; |
| 570 | } | 573 | } |
| 571 | EXPORT_SYMBOL(dma_map_sg); | 574 | EXPORT_SYMBOL(dma_map_sg); |
| @@ -586,8 +589,10 @@ void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, | |||
| 586 | struct scatterlist *s; | 589 | struct scatterlist *s; |
| 587 | int i; | 590 | int i; |
| 588 | 591 | ||
| 592 | debug_dma_unmap_sg(dev, sg, nents, dir); | ||
| 593 | |||
| 589 | for_each_sg(sg, s, nents, i) | 594 | for_each_sg(sg, s, nents, i) |
| 590 | dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir); | 595 | __dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir); |
| 591 | } | 596 | } |
| 592 | EXPORT_SYMBOL(dma_unmap_sg); | 597 | EXPORT_SYMBOL(dma_unmap_sg); |
| 593 | 598 | ||
| @@ -612,6 +617,8 @@ void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, | |||
| 612 | __dma_page_dev_to_cpu(sg_page(s), s->offset, | 617 | __dma_page_dev_to_cpu(sg_page(s), s->offset, |
| 613 | s->length, dir); | 618 | s->length, dir); |
| 614 | } | 619 | } |
| 620 | |||
| 621 | debug_dma_sync_sg_for_cpu(dev, sg, nents, dir); | ||
| 615 | } | 622 | } |
| 616 | EXPORT_SYMBOL(dma_sync_sg_for_cpu); | 623 | EXPORT_SYMBOL(dma_sync_sg_for_cpu); |
| 617 | 624 | ||
| @@ -636,5 +643,16 @@ void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, | |||
| 636 | __dma_page_cpu_to_dev(sg_page(s), s->offset, | 643 | __dma_page_cpu_to_dev(sg_page(s), s->offset, |
| 637 | s->length, dir); | 644 | s->length, dir); |
| 638 | } | 645 | } |
| 646 | |||
| 647 | debug_dma_sync_sg_for_device(dev, sg, nents, dir); | ||
| 639 | } | 648 | } |
| 640 | EXPORT_SYMBOL(dma_sync_sg_for_device); | 649 | EXPORT_SYMBOL(dma_sync_sg_for_device); |
| 650 | |||
| 651 | #define PREALLOC_DMA_DEBUG_ENTRIES 4096 | ||
| 652 | |||
| 653 | static int __init dma_debug_do_init(void) | ||
| 654 | { | ||
| 655 | dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES); | ||
| 656 | return 0; | ||
| 657 | } | ||
| 658 | fs_initcall(dma_debug_do_init); | ||
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c index 83e59f870426..01210dba0221 100644 --- a/arch/arm/mm/fault-armv.c +++ b/arch/arm/mm/fault-armv.c | |||
| @@ -26,7 +26,7 @@ | |||
| 26 | 26 | ||
| 27 | #include "mm.h" | 27 | #include "mm.h" |
| 28 | 28 | ||
| 29 | static unsigned long shared_pte_mask = L_PTE_MT_BUFFERABLE; | 29 | static pteval_t shared_pte_mask = L_PTE_MT_BUFFERABLE; |
| 30 | 30 | ||
| 31 | #if __LINUX_ARM_ARCH__ < 6 | 31 | #if __LINUX_ARM_ARCH__ < 6 |
| 32 | /* | 32 | /* |
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index 1e21e125fe3a..f10f9bac2206 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c | |||
| @@ -108,7 +108,7 @@ void show_pte(struct mm_struct *mm, unsigned long addr) | |||
| 108 | 108 | ||
| 109 | pte = pte_offset_map(pmd, addr); | 109 | pte = pte_offset_map(pmd, addr); |
| 110 | printk(", *pte=%08lx", pte_val(*pte)); | 110 | printk(", *pte=%08lx", pte_val(*pte)); |
| 111 | printk(", *ppte=%08lx", pte_val(pte[-PTRS_PER_PTE])); | 111 | printk(", *ppte=%08lx", pte_val(pte[PTE_HWTABLE_PTRS])); |
| 112 | pte_unmap(pte); | 112 | pte_unmap(pte); |
| 113 | } while(0); | 113 | } while(0); |
| 114 | 114 | ||
diff --git a/arch/arm/mm/idmap.c b/arch/arm/mm/idmap.c new file mode 100644 index 000000000000..57299446f787 --- /dev/null +++ b/arch/arm/mm/idmap.c | |||
| @@ -0,0 +1,67 @@ | |||
| 1 | #include <linux/kernel.h> | ||
| 2 | |||
| 3 | #include <asm/cputype.h> | ||
| 4 | #include <asm/pgalloc.h> | ||
| 5 | #include <asm/pgtable.h> | ||
| 6 | |||
| 7 | static void idmap_add_pmd(pgd_t *pgd, unsigned long addr, unsigned long end, | ||
| 8 | unsigned long prot) | ||
| 9 | { | ||
| 10 | pmd_t *pmd = pmd_offset(pgd, addr); | ||
| 11 | |||
| 12 | addr = (addr & PMD_MASK) | prot; | ||
| 13 | pmd[0] = __pmd(addr); | ||
| 14 | addr += SECTION_SIZE; | ||
| 15 | pmd[1] = __pmd(addr); | ||
| 16 | flush_pmd_entry(pmd); | ||
| 17 | } | ||
| 18 | |||
| 19 | void identity_mapping_add(pgd_t *pgd, unsigned long addr, unsigned long end) | ||
| 20 | { | ||
| 21 | unsigned long prot, next; | ||
| 22 | |||
| 23 | prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE; | ||
| 24 | if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale()) | ||
| 25 | prot |= PMD_BIT4; | ||
| 26 | |||
| 27 | pgd += pgd_index(addr); | ||
| 28 | do { | ||
| 29 | next = pgd_addr_end(addr, end); | ||
| 30 | idmap_add_pmd(pgd, addr, next, prot); | ||
| 31 | } while (pgd++, addr = next, addr != end); | ||
| 32 | } | ||
| 33 | |||
| 34 | #ifdef CONFIG_SMP | ||
| 35 | static void idmap_del_pmd(pgd_t *pgd, unsigned long addr, unsigned long end) | ||
| 36 | { | ||
| 37 | pmd_t *pmd = pmd_offset(pgd, addr); | ||
| 38 | pmd_clear(pmd); | ||
| 39 | } | ||
| 40 | |||
| 41 | void identity_mapping_del(pgd_t *pgd, unsigned long addr, unsigned long end) | ||
| 42 | { | ||
| 43 | unsigned long next; | ||
| 44 | |||
| 45 | pgd += pgd_index(addr); | ||
| 46 | do { | ||
| 47 | next = pgd_addr_end(addr, end); | ||
| 48 | idmap_del_pmd(pgd, addr, next); | ||
| 49 | } while (pgd++, addr = next, addr != end); | ||
| 50 | } | ||
| 51 | #endif | ||
| 52 | |||
| 53 | /* | ||
| 54 | * In order to soft-boot, we need to insert a 1:1 mapping in place of | ||
| 55 | * the user-mode pages. This will then ensure that we have predictable | ||
| 56 | * results when turning the mmu off | ||
| 57 | */ | ||
| 58 | void setup_mm_for_reboot(char mode) | ||
| 59 | { | ||
| 60 | /* | ||
| 61 | * We need to access to user-mode page tables here. For kernel threads | ||
| 62 | * we don't have any user-mode mappings so we use the context that we | ||
| 63 | * "borrowed". | ||
| 64 | */ | ||
| 65 | identity_mapping_add(current->active_mm->pgd, 0, TASK_SIZE); | ||
| 66 | local_flush_tlb_all(); | ||
| 67 | } | ||
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c index 55c17a6fb22f..ab506272b2d3 100644 --- a/arch/arm/mm/ioremap.c +++ b/arch/arm/mm/ioremap.c | |||
| @@ -204,12 +204,8 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn, | |||
| 204 | /* | 204 | /* |
| 205 | * Don't allow RAM to be mapped - this causes problems with ARMv6+ | 205 | * Don't allow RAM to be mapped - this causes problems with ARMv6+ |
| 206 | */ | 206 | */ |
| 207 | if (pfn_valid(pfn)) { | 207 | if (WARN_ON(pfn_valid(pfn))) |
| 208 | printk(KERN_WARNING "BUG: Your driver calls ioremap() on system memory. This leads\n" | 208 | return NULL; |
| 209 | "to architecturally unpredictable behaviour on ARMv6+, and ioremap()\n" | ||
| 210 | "will fail in the next kernel release. Please fix your driver.\n"); | ||
| 211 | WARN_ON(1); | ||
| 212 | } | ||
| 213 | 209 | ||
| 214 | type = get_mem_type(mtype); | 210 | type = get_mem_type(mtype); |
| 215 | if (!type) | 211 | if (!type) |
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h index 6630620380a4..36960df5fb76 100644 --- a/arch/arm/mm/mm.h +++ b/arch/arm/mm/mm.h | |||
| @@ -16,7 +16,7 @@ static inline pmd_t *pmd_off_k(unsigned long virt) | |||
| 16 | } | 16 | } |
| 17 | 17 | ||
| 18 | struct mem_type { | 18 | struct mem_type { |
| 19 | unsigned int prot_pte; | 19 | pteval_t prot_pte; |
| 20 | unsigned int prot_l1; | 20 | unsigned int prot_l1; |
| 21 | unsigned int prot_sect; | 21 | unsigned int prot_sect; |
| 22 | unsigned int domain; | 22 | unsigned int domain; |
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 72ad3e1f56cf..3c67e92f7d59 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | #include <asm/smp_plat.h> | 24 | #include <asm/smp_plat.h> |
| 25 | #include <asm/tlb.h> | 25 | #include <asm/tlb.h> |
| 26 | #include <asm/highmem.h> | 26 | #include <asm/highmem.h> |
| 27 | #include <asm/traps.h> | ||
| 27 | 28 | ||
| 28 | #include <asm/mach/arch.h> | 29 | #include <asm/mach/arch.h> |
| 29 | #include <asm/mach/map.h> | 30 | #include <asm/mach/map.h> |
| @@ -62,7 +63,7 @@ struct cachepolicy { | |||
| 62 | const char policy[16]; | 63 | const char policy[16]; |
| 63 | unsigned int cr_mask; | 64 | unsigned int cr_mask; |
| 64 | unsigned int pmd; | 65 | unsigned int pmd; |
| 65 | unsigned int pte; | 66 | pteval_t pte; |
| 66 | }; | 67 | }; |
| 67 | 68 | ||
| 68 | static struct cachepolicy cache_policies[] __initdata = { | 69 | static struct cachepolicy cache_policies[] __initdata = { |
| @@ -190,7 +191,7 @@ void adjust_cr(unsigned long mask, unsigned long set) | |||
| 190 | } | 191 | } |
| 191 | #endif | 192 | #endif |
| 192 | 193 | ||
| 193 | #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_WRITE | 194 | #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN |
| 194 | #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE | 195 | #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE |
| 195 | 196 | ||
| 196 | static struct mem_type mem_types[] = { | 197 | static struct mem_type mem_types[] = { |
| @@ -235,19 +236,18 @@ static struct mem_type mem_types[] = { | |||
| 235 | }, | 236 | }, |
| 236 | [MT_LOW_VECTORS] = { | 237 | [MT_LOW_VECTORS] = { |
| 237 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | 238 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
| 238 | L_PTE_EXEC, | 239 | L_PTE_RDONLY, |
| 239 | .prot_l1 = PMD_TYPE_TABLE, | 240 | .prot_l1 = PMD_TYPE_TABLE, |
| 240 | .domain = DOMAIN_USER, | 241 | .domain = DOMAIN_USER, |
| 241 | }, | 242 | }, |
| 242 | [MT_HIGH_VECTORS] = { | 243 | [MT_HIGH_VECTORS] = { |
| 243 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | 244 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
| 244 | L_PTE_USER | L_PTE_EXEC, | 245 | L_PTE_USER | L_PTE_RDONLY, |
| 245 | .prot_l1 = PMD_TYPE_TABLE, | 246 | .prot_l1 = PMD_TYPE_TABLE, |
| 246 | .domain = DOMAIN_USER, | 247 | .domain = DOMAIN_USER, |
| 247 | }, | 248 | }, |
| 248 | [MT_MEMORY] = { | 249 | [MT_MEMORY] = { |
| 249 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | 250 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, |
| 250 | L_PTE_WRITE | L_PTE_EXEC, | ||
| 251 | .prot_l1 = PMD_TYPE_TABLE, | 251 | .prot_l1 = PMD_TYPE_TABLE, |
| 252 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, | 252 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
| 253 | .domain = DOMAIN_KERNEL, | 253 | .domain = DOMAIN_KERNEL, |
| @@ -258,21 +258,20 @@ static struct mem_type mem_types[] = { | |||
| 258 | }, | 258 | }, |
| 259 | [MT_MEMORY_NONCACHED] = { | 259 | [MT_MEMORY_NONCACHED] = { |
| 260 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | 260 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
| 261 | L_PTE_WRITE | L_PTE_EXEC | L_PTE_MT_BUFFERABLE, | 261 | L_PTE_MT_BUFFERABLE, |
| 262 | .prot_l1 = PMD_TYPE_TABLE, | 262 | .prot_l1 = PMD_TYPE_TABLE, |
| 263 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, | 263 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
| 264 | .domain = DOMAIN_KERNEL, | 264 | .domain = DOMAIN_KERNEL, |
| 265 | }, | 265 | }, |
| 266 | [MT_MEMORY_DTCM] = { | 266 | [MT_MEMORY_DTCM] = { |
| 267 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | 267 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
| 268 | L_PTE_WRITE, | 268 | L_PTE_XN, |
| 269 | .prot_l1 = PMD_TYPE_TABLE, | 269 | .prot_l1 = PMD_TYPE_TABLE, |
| 270 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, | 270 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, |
| 271 | .domain = DOMAIN_KERNEL, | 271 | .domain = DOMAIN_KERNEL, |
| 272 | }, | 272 | }, |
| 273 | [MT_MEMORY_ITCM] = { | 273 | [MT_MEMORY_ITCM] = { |
| 274 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | 274 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, |
| 275 | L_PTE_WRITE | L_PTE_EXEC, | ||
| 276 | .prot_l1 = PMD_TYPE_TABLE, | 275 | .prot_l1 = PMD_TYPE_TABLE, |
| 277 | .domain = DOMAIN_KERNEL, | 276 | .domain = DOMAIN_KERNEL, |
| 278 | }, | 277 | }, |
| @@ -479,7 +478,7 @@ static void __init build_mem_type_table(void) | |||
| 479 | 478 | ||
| 480 | pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot); | 479 | pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot); |
| 481 | pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | | 480 | pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | |
| 482 | L_PTE_DIRTY | L_PTE_WRITE | kern_pgprot); | 481 | L_PTE_DIRTY | kern_pgprot); |
| 483 | 482 | ||
| 484 | mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; | 483 | mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; |
| 485 | mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; | 484 | mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; |
| @@ -535,7 +534,7 @@ static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned l | |||
| 535 | { | 534 | { |
| 536 | if (pmd_none(*pmd)) { | 535 | if (pmd_none(*pmd)) { |
| 537 | pte_t *pte = early_alloc(2 * PTRS_PER_PTE * sizeof(pte_t)); | 536 | pte_t *pte = early_alloc(2 * PTRS_PER_PTE * sizeof(pte_t)); |
| 538 | __pmd_populate(pmd, __pa(pte) | prot); | 537 | __pmd_populate(pmd, __pa(pte), prot); |
| 539 | } | 538 | } |
| 540 | BUG_ON(pmd_bad(*pmd)); | 539 | BUG_ON(pmd_bad(*pmd)); |
| 541 | return pte_offset_kernel(pmd, addr); | 540 | return pte_offset_kernel(pmd, addr); |
| @@ -553,7 +552,7 @@ static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, | |||
| 553 | } | 552 | } |
| 554 | 553 | ||
| 555 | static void __init alloc_init_section(pgd_t *pgd, unsigned long addr, | 554 | static void __init alloc_init_section(pgd_t *pgd, unsigned long addr, |
| 556 | unsigned long end, unsigned long phys, | 555 | unsigned long end, phys_addr_t phys, |
| 557 | const struct mem_type *type) | 556 | const struct mem_type *type) |
| 558 | { | 557 | { |
| 559 | pmd_t *pmd = pmd_offset(pgd, addr); | 558 | pmd_t *pmd = pmd_offset(pgd, addr); |
| @@ -588,7 +587,8 @@ static void __init alloc_init_section(pgd_t *pgd, unsigned long addr, | |||
| 588 | static void __init create_36bit_mapping(struct map_desc *md, | 587 | static void __init create_36bit_mapping(struct map_desc *md, |
| 589 | const struct mem_type *type) | 588 | const struct mem_type *type) |
| 590 | { | 589 | { |
| 591 | unsigned long phys, addr, length, end; | 590 | unsigned long addr, length, end; |
| 591 | phys_addr_t phys; | ||
| 592 | pgd_t *pgd; | 592 | pgd_t *pgd; |
| 593 | 593 | ||
| 594 | addr = md->virtual; | 594 | addr = md->virtual; |
| @@ -914,12 +914,11 @@ static void __init devicemaps_init(struct machine_desc *mdesc) | |||
| 914 | { | 914 | { |
| 915 | struct map_desc map; | 915 | struct map_desc map; |
| 916 | unsigned long addr; | 916 | unsigned long addr; |
| 917 | void *vectors; | ||
| 918 | 917 | ||
| 919 | /* | 918 | /* |
| 920 | * Allocate the vector page early. | 919 | * Allocate the vector page early. |
| 921 | */ | 920 | */ |
| 922 | vectors = early_alloc(PAGE_SIZE); | 921 | vectors_page = early_alloc(PAGE_SIZE); |
| 923 | 922 | ||
| 924 | for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE) | 923 | for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE) |
| 925 | pmd_clear(pmd_off_k(addr)); | 924 | pmd_clear(pmd_off_k(addr)); |
| @@ -959,7 +958,7 @@ static void __init devicemaps_init(struct machine_desc *mdesc) | |||
| 959 | * location (0xffff0000). If we aren't using high-vectors, also | 958 | * location (0xffff0000). If we aren't using high-vectors, also |
| 960 | * create a mapping at the low-vectors virtual address. | 959 | * create a mapping at the low-vectors virtual address. |
| 961 | */ | 960 | */ |
| 962 | map.pfn = __phys_to_pfn(virt_to_phys(vectors)); | 961 | map.pfn = __phys_to_pfn(virt_to_phys(vectors_page)); |
| 963 | map.virtual = 0xffff0000; | 962 | map.virtual = 0xffff0000; |
| 964 | map.length = PAGE_SIZE; | 963 | map.length = PAGE_SIZE; |
| 965 | map.type = MT_HIGH_VECTORS; | 964 | map.type = MT_HIGH_VECTORS; |
| @@ -1044,38 +1043,3 @@ void __init paging_init(struct machine_desc *mdesc) | |||
| 1044 | empty_zero_page = virt_to_page(zero_page); | 1043 | empty_zero_page = virt_to_page(zero_page); |
| 1045 | __flush_dcache_page(NULL, empty_zero_page); | 1044 | __flush_dcache_page(NULL, empty_zero_page); |
| 1046 | } | 1045 | } |
| 1047 | |||
| 1048 | /* | ||
| 1049 | * In order to soft-boot, we need to insert a 1:1 mapping in place of | ||
| 1050 | * the user-mode pages. This will then ensure that we have predictable | ||
| 1051 | * results when turning the mmu off | ||
| 1052 | */ | ||
| 1053 | void setup_mm_for_reboot(char mode) | ||
| 1054 | { | ||
| 1055 | unsigned long base_pmdval; | ||
| 1056 | pgd_t *pgd; | ||
| 1057 | int i; | ||
| 1058 | |||
| 1059 | /* | ||
| 1060 | * We need to access to user-mode page tables here. For kernel threads | ||
| 1061 | * we don't have any user-mode mappings so we use the context that we | ||
| 1062 | * "borrowed". | ||
| 1063 | */ | ||
| 1064 | pgd = current->active_mm->pgd; | ||
| 1065 | |||
| 1066 | base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT; | ||
| 1067 | if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale()) | ||
| 1068 | base_pmdval |= PMD_BIT4; | ||
| 1069 | |||
| 1070 | for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) { | ||
| 1071 | unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval; | ||
| 1072 | pmd_t *pmd; | ||
| 1073 | |||
| 1074 | pmd = pmd_off(pgd, i << PGDIR_SHIFT); | ||
| 1075 | pmd[0] = __pmd(pmdval); | ||
| 1076 | pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1))); | ||
| 1077 | flush_pmd_entry(pmd); | ||
| 1078 | } | ||
| 1079 | |||
| 1080 | local_flush_tlb_all(); | ||
| 1081 | } | ||
diff --git a/arch/arm/mm/pgd.c b/arch/arm/mm/pgd.c index 69bbfc6645a6..93292a18cf77 100644 --- a/arch/arm/mm/pgd.c +++ b/arch/arm/mm/pgd.c | |||
| @@ -17,12 +17,10 @@ | |||
| 17 | 17 | ||
| 18 | #include "mm.h" | 18 | #include "mm.h" |
| 19 | 19 | ||
| 20 | #define FIRST_KERNEL_PGD_NR (FIRST_USER_PGD_NR + USER_PTRS_PER_PGD) | ||
| 21 | |||
| 22 | /* | 20 | /* |
| 23 | * need to get a 16k page for level 1 | 21 | * need to get a 16k page for level 1 |
| 24 | */ | 22 | */ |
| 25 | pgd_t *get_pgd_slow(struct mm_struct *mm) | 23 | pgd_t *pgd_alloc(struct mm_struct *mm) |
| 26 | { | 24 | { |
| 27 | pgd_t *new_pgd, *init_pgd; | 25 | pgd_t *new_pgd, *init_pgd; |
| 28 | pmd_t *new_pmd, *init_pmd; | 26 | pmd_t *new_pmd, *init_pmd; |
| @@ -32,14 +30,14 @@ pgd_t *get_pgd_slow(struct mm_struct *mm) | |||
| 32 | if (!new_pgd) | 30 | if (!new_pgd) |
| 33 | goto no_pgd; | 31 | goto no_pgd; |
| 34 | 32 | ||
| 35 | memset(new_pgd, 0, FIRST_KERNEL_PGD_NR * sizeof(pgd_t)); | 33 | memset(new_pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t)); |
| 36 | 34 | ||
| 37 | /* | 35 | /* |
| 38 | * Copy over the kernel and IO PGD entries | 36 | * Copy over the kernel and IO PGD entries |
| 39 | */ | 37 | */ |
| 40 | init_pgd = pgd_offset_k(0); | 38 | init_pgd = pgd_offset_k(0); |
| 41 | memcpy(new_pgd + FIRST_KERNEL_PGD_NR, init_pgd + FIRST_KERNEL_PGD_NR, | 39 | memcpy(new_pgd + USER_PTRS_PER_PGD, init_pgd + USER_PTRS_PER_PGD, |
| 42 | (PTRS_PER_PGD - FIRST_KERNEL_PGD_NR) * sizeof(pgd_t)); | 40 | (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t)); |
| 43 | 41 | ||
| 44 | clean_dcache_area(new_pgd, PTRS_PER_PGD * sizeof(pgd_t)); | 42 | clean_dcache_area(new_pgd, PTRS_PER_PGD * sizeof(pgd_t)); |
| 45 | 43 | ||
| @@ -73,28 +71,29 @@ no_pgd: | |||
| 73 | return NULL; | 71 | return NULL; |
| 74 | } | 72 | } |
| 75 | 73 | ||
| 76 | void free_pgd_slow(struct mm_struct *mm, pgd_t *pgd) | 74 | void pgd_free(struct mm_struct *mm, pgd_t *pgd_base) |
| 77 | { | 75 | { |
| 76 | pgd_t *pgd; | ||
| 78 | pmd_t *pmd; | 77 | pmd_t *pmd; |
| 79 | pgtable_t pte; | 78 | pgtable_t pte; |
| 80 | 79 | ||
| 81 | if (!pgd) | 80 | if (!pgd_base) |
| 82 | return; | 81 | return; |
| 83 | 82 | ||
| 84 | /* pgd is always present and good */ | 83 | pgd = pgd_base + pgd_index(0); |
| 85 | pmd = pmd_off(pgd, 0); | 84 | if (pgd_none_or_clear_bad(pgd)) |
| 86 | if (pmd_none(*pmd)) | 85 | goto no_pgd; |
| 87 | goto free; | 86 | |
| 88 | if (pmd_bad(*pmd)) { | 87 | pmd = pmd_offset(pgd, 0); |
| 89 | pmd_ERROR(*pmd); | 88 | if (pmd_none_or_clear_bad(pmd)) |
| 90 | pmd_clear(pmd); | 89 | goto no_pmd; |
| 91 | goto free; | ||
| 92 | } | ||
| 93 | 90 | ||
| 94 | pte = pmd_pgtable(*pmd); | 91 | pte = pmd_pgtable(*pmd); |
| 95 | pmd_clear(pmd); | 92 | pmd_clear(pmd); |
| 96 | pte_free(mm, pte); | 93 | pte_free(mm, pte); |
| 94 | no_pmd: | ||
| 95 | pgd_clear(pgd); | ||
| 97 | pmd_free(mm, pmd); | 96 | pmd_free(mm, pmd); |
| 98 | free: | 97 | no_pgd: |
| 99 | free_pages((unsigned long) pgd, 2); | 98 | free_pages((unsigned long) pgd_base, 2); |
| 100 | } | 99 | } |
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index b795afd0a2c6..e32fa499194c 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S | |||
| @@ -91,7 +91,7 @@ | |||
| 91 | #if L_PTE_SHARED != PTE_EXT_SHARED | 91 | #if L_PTE_SHARED != PTE_EXT_SHARED |
| 92 | #error PTE shared bit mismatch | 92 | #error PTE shared bit mismatch |
| 93 | #endif | 93 | #endif |
| 94 | #if (L_PTE_EXEC+L_PTE_USER+L_PTE_WRITE+L_PTE_DIRTY+L_PTE_YOUNG+\ | 94 | #if (L_PTE_XN+L_PTE_USER+L_PTE_RDONLY+L_PTE_DIRTY+L_PTE_YOUNG+\ |
| 95 | L_PTE_FILE+L_PTE_PRESENT) > L_PTE_SHARED | 95 | L_PTE_FILE+L_PTE_PRESENT) > L_PTE_SHARED |
| 96 | #error Invalid Linux PTE bit settings | 96 | #error Invalid Linux PTE bit settings |
| 97 | #endif | 97 | #endif |
| @@ -109,6 +109,10 @@ | |||
| 109 | * 110x 0 1 0 r/w r/o | 109 | * 110x 0 1 0 r/w r/o |
| 110 | * 11x0 0 1 0 r/w r/o | 110 | * 11x0 0 1 0 r/w r/o |
| 111 | * 1111 0 1 1 r/w r/w | 111 | * 1111 0 1 1 r/w r/w |
| 112 | * | ||
| 113 | * If !CONFIG_CPU_USE_DOMAINS, the following permissions are changed: | ||
| 114 | * 110x 1 1 1 r/o r/o | ||
| 115 | * 11x0 1 1 1 r/o r/o | ||
| 112 | */ | 116 | */ |
| 113 | .macro armv6_mt_table pfx | 117 | .macro armv6_mt_table pfx |
| 114 | \pfx\()_mt_table: | 118 | \pfx\()_mt_table: |
| @@ -131,7 +135,7 @@ | |||
| 131 | .endm | 135 | .endm |
| 132 | 136 | ||
| 133 | .macro armv6_set_pte_ext pfx | 137 | .macro armv6_set_pte_ext pfx |
| 134 | str r1, [r0], #-2048 @ linux version | 138 | str r1, [r0], #2048 @ linux version |
| 135 | 139 | ||
| 136 | bic r3, r1, #0x000003fc | 140 | bic r3, r1, #0x000003fc |
| 137 | bic r3, r3, #PTE_TYPE_MASK | 141 | bic r3, r3, #PTE_TYPE_MASK |
| @@ -142,17 +146,20 @@ | |||
| 142 | and r2, r1, #L_PTE_MT_MASK | 146 | and r2, r1, #L_PTE_MT_MASK |
| 143 | ldr r2, [ip, r2] | 147 | ldr r2, [ip, r2] |
| 144 | 148 | ||
| 145 | tst r1, #L_PTE_WRITE | 149 | eor r1, r1, #L_PTE_DIRTY |
| 146 | tstne r1, #L_PTE_DIRTY | 150 | tst r1, #L_PTE_DIRTY|L_PTE_RDONLY |
| 147 | orreq r3, r3, #PTE_EXT_APX | 151 | orrne r3, r3, #PTE_EXT_APX |
| 148 | 152 | ||
| 149 | tst r1, #L_PTE_USER | 153 | tst r1, #L_PTE_USER |
| 150 | orrne r3, r3, #PTE_EXT_AP1 | 154 | orrne r3, r3, #PTE_EXT_AP1 |
| 155 | #ifdef CONFIG_CPU_USE_DOMAINS | ||
| 156 | @ allow kernel read/write access to read-only user pages | ||
| 151 | tstne r3, #PTE_EXT_APX | 157 | tstne r3, #PTE_EXT_APX |
| 152 | bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0 | 158 | bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0 |
| 159 | #endif | ||
| 153 | 160 | ||
| 154 | tst r1, #L_PTE_EXEC | 161 | tst r1, #L_PTE_XN |
| 155 | orreq r3, r3, #PTE_EXT_XN | 162 | orrne r3, r3, #PTE_EXT_XN |
| 156 | 163 | ||
| 157 | orr r3, r3, r2 | 164 | orr r3, r3, r2 |
| 158 | 165 | ||
| @@ -180,9 +187,9 @@ | |||
| 180 | * 1111 0xff r/w r/w | 187 | * 1111 0xff r/w r/w |
| 181 | */ | 188 | */ |
| 182 | .macro armv3_set_pte_ext wc_disable=1 | 189 | .macro armv3_set_pte_ext wc_disable=1 |
| 183 | str r1, [r0], #-2048 @ linux version | 190 | str r1, [r0], #2048 @ linux version |
| 184 | 191 | ||
| 185 | eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY | 192 | eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
| 186 | 193 | ||
| 187 | bic r2, r1, #PTE_SMALL_AP_MASK @ keep C, B bits | 194 | bic r2, r1, #PTE_SMALL_AP_MASK @ keep C, B bits |
| 188 | bic r2, r2, #PTE_TYPE_MASK | 195 | bic r2, r2, #PTE_TYPE_MASK |
| @@ -191,7 +198,7 @@ | |||
| 191 | tst r3, #L_PTE_USER @ user? | 198 | tst r3, #L_PTE_USER @ user? |
| 192 | orrne r2, r2, #PTE_SMALL_AP_URO_SRW | 199 | orrne r2, r2, #PTE_SMALL_AP_URO_SRW |
| 193 | 200 | ||
| 194 | tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ write and dirty? | 201 | tst r3, #L_PTE_RDONLY | L_PTE_DIRTY @ write and dirty? |
| 195 | orreq r2, r2, #PTE_SMALL_AP_UNO_SRW | 202 | orreq r2, r2, #PTE_SMALL_AP_UNO_SRW |
| 196 | 203 | ||
| 197 | tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ present and young? | 204 | tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ present and young? |
| @@ -203,7 +210,7 @@ | |||
| 203 | bicne r2, r2, #PTE_BUFFERABLE | 210 | bicne r2, r2, #PTE_BUFFERABLE |
| 204 | #endif | 211 | #endif |
| 205 | .endif | 212 | .endif |
| 206 | str r2, [r0] @ hardware version | 213 | str r2, [r0] @ hardware version |
| 207 | .endm | 214 | .endm |
| 208 | 215 | ||
| 209 | 216 | ||
| @@ -223,9 +230,9 @@ | |||
| 223 | * 1111 11 r/w r/w | 230 | * 1111 11 r/w r/w |
| 224 | */ | 231 | */ |
| 225 | .macro xscale_set_pte_ext_prologue | 232 | .macro xscale_set_pte_ext_prologue |
| 226 | str r1, [r0], #-2048 @ linux version | 233 | str r1, [r0] @ linux version |
| 227 | 234 | ||
| 228 | eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY | 235 | eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
| 229 | 236 | ||
| 230 | bic r2, r1, #PTE_SMALL_AP_MASK @ keep C, B bits | 237 | bic r2, r1, #PTE_SMALL_AP_MASK @ keep C, B bits |
| 231 | orr r2, r2, #PTE_TYPE_EXT @ extended page | 238 | orr r2, r2, #PTE_TYPE_EXT @ extended page |
| @@ -233,7 +240,7 @@ | |||
| 233 | tst r3, #L_PTE_USER @ user? | 240 | tst r3, #L_PTE_USER @ user? |
| 234 | orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w | 241 | orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w |
| 235 | 242 | ||
| 236 | tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ write and dirty? | 243 | tst r3, #L_PTE_RDONLY | L_PTE_DIRTY @ write and dirty? |
| 237 | orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w | 244 | orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w |
| 238 | @ combined with user -> user r/w | 245 | @ combined with user -> user r/w |
| 239 | .endm | 246 | .endm |
| @@ -242,7 +249,7 @@ | |||
| 242 | tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ present and young? | 249 | tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ present and young? |
| 243 | movne r2, #0 @ no -> fault | 250 | movne r2, #0 @ no -> fault |
| 244 | 251 | ||
| 245 | str r2, [r0] @ hardware version | 252 | str r2, [r0, #2048]! @ hardware version |
| 246 | mov ip, #0 | 253 | mov ip, #0 |
| 247 | mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line | 254 | mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line |
| 248 | mcr p15, 0, ip, c7, c10, 4 @ data write barrier | 255 | mcr p15, 0, ip, c7, c10, 4 @ data write barrier |
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 9b9ff5d949fd..b49fab21517c 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S | |||
| @@ -124,15 +124,13 @@ ENDPROC(cpu_v7_switch_mm) | |||
| 124 | * Set a level 2 translation table entry. | 124 | * Set a level 2 translation table entry. |
| 125 | * | 125 | * |
| 126 | * - ptep - pointer to level 2 translation table entry | 126 | * - ptep - pointer to level 2 translation table entry |
| 127 | * (hardware version is stored at -1024 bytes) | 127 | * (hardware version is stored at +2048 bytes) |
| 128 | * - pte - PTE value to store | 128 | * - pte - PTE value to store |
| 129 | * - ext - value for extended PTE bits | 129 | * - ext - value for extended PTE bits |
| 130 | */ | 130 | */ |
| 131 | ENTRY(cpu_v7_set_pte_ext) | 131 | ENTRY(cpu_v7_set_pte_ext) |
| 132 | #ifdef CONFIG_MMU | 132 | #ifdef CONFIG_MMU |
| 133 | ARM( str r1, [r0], #-2048 ) @ linux version | 133 | str r1, [r0] @ linux version |
| 134 | THUMB( str r1, [r0] ) @ linux version | ||
| 135 | THUMB( sub r0, r0, #2048 ) | ||
| 136 | 134 | ||
| 137 | bic r3, r1, #0x000003f0 | 135 | bic r3, r1, #0x000003f0 |
| 138 | bic r3, r3, #PTE_TYPE_MASK | 136 | bic r3, r3, #PTE_TYPE_MASK |
| @@ -142,23 +140,26 @@ ENTRY(cpu_v7_set_pte_ext) | |||
| 142 | tst r1, #1 << 4 | 140 | tst r1, #1 << 4 |
| 143 | orrne r3, r3, #PTE_EXT_TEX(1) | 141 | orrne r3, r3, #PTE_EXT_TEX(1) |
| 144 | 142 | ||
| 145 | tst r1, #L_PTE_WRITE | 143 | eor r1, r1, #L_PTE_DIRTY |
| 146 | tstne r1, #L_PTE_DIRTY | 144 | tst r1, #L_PTE_RDONLY | L_PTE_DIRTY |
| 147 | orreq r3, r3, #PTE_EXT_APX | 145 | orrne r3, r3, #PTE_EXT_APX |
| 148 | 146 | ||
| 149 | tst r1, #L_PTE_USER | 147 | tst r1, #L_PTE_USER |
| 150 | orrne r3, r3, #PTE_EXT_AP1 | 148 | orrne r3, r3, #PTE_EXT_AP1 |
| 149 | #ifdef CONFIG_CPU_USE_DOMAINS | ||
| 150 | @ allow kernel read/write access to read-only user pages | ||
| 151 | tstne r3, #PTE_EXT_APX | 151 | tstne r3, #PTE_EXT_APX |
| 152 | bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0 | 152 | bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0 |
| 153 | #endif | ||
| 153 | 154 | ||
| 154 | tst r1, #L_PTE_EXEC | 155 | tst r1, #L_PTE_XN |
| 155 | orreq r3, r3, #PTE_EXT_XN | 156 | orrne r3, r3, #PTE_EXT_XN |
| 156 | 157 | ||
| 157 | tst r1, #L_PTE_YOUNG | 158 | tst r1, #L_PTE_YOUNG |
| 158 | tstne r1, #L_PTE_PRESENT | 159 | tstne r1, #L_PTE_PRESENT |
| 159 | moveq r3, #0 | 160 | moveq r3, #0 |
| 160 | 161 | ||
| 161 | str r3, [r0] | 162 | str r3, [r0, #2048]! |
| 162 | mcr p15, 0, r0, c7, c10, 1 @ flush_pte | 163 | mcr p15, 0, r0, c7, c10, 1 @ flush_pte |
| 163 | #endif | 164 | #endif |
| 164 | mov pc, lr | 165 | mov pc, lr |
| @@ -273,8 +274,6 @@ __v7_setup: | |||
| 273 | ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) | 274 | ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) |
| 274 | ALT_UP(orr r4, r4, #TTB_FLAGS_UP) | 275 | ALT_UP(orr r4, r4, #TTB_FLAGS_UP) |
| 275 | mcr p15, 0, r4, c2, c0, 1 @ load TTB1 | 276 | mcr p15, 0, r4, c2, c0, 1 @ load TTB1 |
| 276 | mov r10, #0x1f @ domains 0, 1 = manager | ||
| 277 | mcr p15, 0, r10, c3, c0, 0 @ load domain access register | ||
| 278 | /* | 277 | /* |
| 279 | * Memory region attributes with SCTLR.TRE=1 | 278 | * Memory region attributes with SCTLR.TRE=1 |
| 280 | * | 279 | * |
| @@ -313,6 +312,10 @@ __v7_setup: | |||
| 313 | #ifdef CONFIG_CPU_ENDIAN_BE8 | 312 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
| 314 | orr r6, r6, #1 << 25 @ big-endian page tables | 313 | orr r6, r6, #1 << 25 @ big-endian page tables |
| 315 | #endif | 314 | #endif |
| 315 | #ifdef CONFIG_SWP_EMULATE | ||
| 316 | orr r5, r5, #(1 << 10) @ set SW bit in "clear" | ||
| 317 | bic r6, r6, #(1 << 10) @ clear it in "mmuset" | ||
| 318 | #endif | ||
| 316 | mrc p15, 0, r0, c1, c0, 0 @ read control register | 319 | mrc p15, 0, r0, c1, c0, 0 @ read control register |
| 317 | bic r0, r0, r5 @ clear bits them | 320 | bic r0, r0, r5 @ clear bits them |
| 318 | orr r0, r0, r6 @ set them | 321 | orr r0, r0, r6 @ set them |
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index 523408c0bb38..5a37c5e45c41 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S | |||
| @@ -500,8 +500,8 @@ ENTRY(cpu_xscale_set_pte_ext) | |||
| 500 | @ | 500 | @ |
| 501 | @ Erratum 40: must set memory to write-through for user read-only pages | 501 | @ Erratum 40: must set memory to write-through for user read-only pages |
| 502 | @ | 502 | @ |
| 503 | and ip, r1, #(L_PTE_MT_MASK | L_PTE_USER | L_PTE_WRITE) & ~(4 << 2) | 503 | and ip, r1, #(L_PTE_MT_MASK | L_PTE_USER | L_PTE_RDONLY) & ~(4 << 2) |
| 504 | teq ip, #L_PTE_MT_WRITEBACK | L_PTE_USER | 504 | teq ip, #L_PTE_MT_WRITEBACK | L_PTE_USER | L_PTE_RDONLY |
| 505 | 505 | ||
| 506 | moveq r1, #L_PTE_MT_WRITETHROUGH | 506 | moveq r1, #L_PTE_MT_WRITETHROUGH |
| 507 | and r1, r1, #L_PTE_MT_MASK | 507 | and r1, r1, #L_PTE_MT_MASK |
diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c index 558cdfaf76b6..07f23bb42bed 100644 --- a/arch/arm/plat-iop/time.c +++ b/arch/arm/plat-iop/time.c | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | #include <linux/interrupt.h> | 17 | #include <linux/interrupt.h> |
| 18 | #include <linux/time.h> | 18 | #include <linux/time.h> |
| 19 | #include <linux/init.h> | 19 | #include <linux/init.h> |
| 20 | #include <linux/sched.h> | ||
| 20 | #include <linux/timex.h> | 21 | #include <linux/timex.h> |
| 21 | #include <linux/sched.h> | 22 | #include <linux/sched.h> |
| 22 | #include <linux/io.h> | 23 | #include <linux/io.h> |
| @@ -24,6 +25,7 @@ | |||
| 24 | #include <linux/clockchips.h> | 25 | #include <linux/clockchips.h> |
| 25 | #include <mach/hardware.h> | 26 | #include <mach/hardware.h> |
| 26 | #include <asm/irq.h> | 27 | #include <asm/irq.h> |
| 28 | #include <asm/sched_clock.h> | ||
| 27 | #include <asm/uaccess.h> | 29 | #include <asm/uaccess.h> |
| 28 | #include <asm/mach/irq.h> | 30 | #include <asm/mach/irq.h> |
| 29 | #include <asm/mach/time.h> | 31 | #include <asm/mach/time.h> |
| @@ -50,15 +52,21 @@ static struct clocksource iop_clocksource = { | |||
| 50 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 52 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 51 | }; | 53 | }; |
| 52 | 54 | ||
| 55 | static DEFINE_CLOCK_DATA(cd); | ||
| 56 | |||
| 53 | /* | 57 | /* |
| 54 | * IOP sched_clock() implementation via its clocksource. | 58 | * IOP sched_clock() implementation via its clocksource. |
| 55 | */ | 59 | */ |
| 56 | unsigned long long sched_clock(void) | 60 | unsigned long long notrace sched_clock(void) |
| 57 | { | 61 | { |
| 58 | cycle_t cyc = iop_clocksource_read(NULL); | 62 | u32 cyc = 0xffffffffu - read_tcr1(); |
| 59 | struct clocksource *cs = &iop_clocksource; | 63 | return cyc_to_sched_clock(&cd, cyc, (u32)~0); |
| 64 | } | ||
| 60 | 65 | ||
| 61 | return clocksource_cyc2ns(cyc, cs->mult, cs->shift); | 66 | static void notrace iop_update_sched_clock(void) |
| 67 | { | ||
| 68 | u32 cyc = 0xffffffffu - read_tcr1(); | ||
| 69 | update_sched_clock(&cd, cyc, (u32)~0); | ||
| 62 | } | 70 | } |
| 63 | 71 | ||
| 64 | /* | 72 | /* |
| @@ -88,6 +96,7 @@ static void iop_set_mode(enum clock_event_mode mode, | |||
| 88 | case CLOCK_EVT_MODE_PERIODIC: | 96 | case CLOCK_EVT_MODE_PERIODIC: |
| 89 | write_tmr0(tmr & ~IOP_TMR_EN); | 97 | write_tmr0(tmr & ~IOP_TMR_EN); |
| 90 | write_tcr0(ticks_per_jiffy - 1); | 98 | write_tcr0(ticks_per_jiffy - 1); |
| 99 | write_trr0(ticks_per_jiffy - 1); | ||
| 91 | tmr |= (IOP_TMR_RELOAD | IOP_TMR_EN); | 100 | tmr |= (IOP_TMR_RELOAD | IOP_TMR_EN); |
| 92 | break; | 101 | break; |
| 93 | case CLOCK_EVT_MODE_ONESHOT: | 102 | case CLOCK_EVT_MODE_ONESHOT: |
| @@ -143,6 +152,8 @@ void __init iop_init_time(unsigned long tick_rate) | |||
| 143 | { | 152 | { |
| 144 | u32 timer_ctl; | 153 | u32 timer_ctl; |
| 145 | 154 | ||
| 155 | init_sched_clock(&cd, iop_update_sched_clock, 32, tick_rate); | ||
| 156 | |||
| 146 | ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ); | 157 | ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ); |
| 147 | iop_tick_rate = tick_rate; | 158 | iop_tick_rate = tick_rate; |
| 148 | 159 | ||
| @@ -153,6 +164,7 @@ void __init iop_init_time(unsigned long tick_rate) | |||
| 153 | * Set up interrupting clockevent timer 0. | 164 | * Set up interrupting clockevent timer 0. |
| 154 | */ | 165 | */ |
| 155 | write_tmr0(timer_ctl & ~IOP_TMR_EN); | 166 | write_tmr0(timer_ctl & ~IOP_TMR_EN); |
| 167 | write_tisr(1); | ||
| 156 | setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq); | 168 | setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq); |
| 157 | clockevents_calc_mult_shift(&iop_clockevent, | 169 | clockevents_calc_mult_shift(&iop_clockevent, |
| 158 | tick_rate, IOP_MIN_RANGE); | 170 | tick_rate, IOP_MIN_RANGE); |
| @@ -162,9 +174,6 @@ void __init iop_init_time(unsigned long tick_rate) | |||
| 162 | clockevent_delta2ns(0xf, &iop_clockevent); | 174 | clockevent_delta2ns(0xf, &iop_clockevent); |
| 163 | iop_clockevent.cpumask = cpumask_of(0); | 175 | iop_clockevent.cpumask = cpumask_of(0); |
| 164 | clockevents_register_device(&iop_clockevent); | 176 | clockevents_register_device(&iop_clockevent); |
| 165 | write_trr0(ticks_per_jiffy - 1); | ||
| 166 | write_tcr0(ticks_per_jiffy - 1); | ||
| 167 | write_tmr0(timer_ctl); | ||
| 168 | 177 | ||
| 169 | /* | 178 | /* |
| 170 | * Set up free-running clocksource timer 1. | 179 | * Set up free-running clocksource timer 1. |
| @@ -172,7 +181,5 @@ void __init iop_init_time(unsigned long tick_rate) | |||
| 172 | write_trr1(0xffffffff); | 181 | write_trr1(0xffffffff); |
| 173 | write_tcr1(0xffffffff); | 182 | write_tcr1(0xffffffff); |
| 174 | write_tmr1(timer_ctl); | 183 | write_tmr1(timer_ctl); |
| 175 | clocksource_calc_mult_shift(&iop_clocksource, tick_rate, | 184 | clocksource_register_hz(&iop_clocksource, tick_rate); |
| 176 | IOP_MIN_RANGE); | ||
| 177 | clocksource_register(&iop_clocksource); | ||
| 178 | } | 185 | } |
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index 64e3a64520e0..389f21795015 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig | |||
| @@ -21,10 +21,6 @@ config ARCH_MX2 | |||
| 21 | 21 | ||
| 22 | config ARCH_MX25 | 22 | config ARCH_MX25 |
| 23 | bool "MX25-based" | 23 | bool "MX25-based" |
| 24 | select CPU_ARM926T | ||
| 25 | select ARCH_MXC_IOMUX_V3 | ||
| 26 | select HAVE_FB_IMX | ||
| 27 | select ARCH_MXC_AUDMUX_V2 | ||
| 28 | help | 24 | help |
| 29 | This enables support for systems based on the Freescale i.MX25 family | 25 | This enables support for systems based on the Freescale i.MX25 family |
| 30 | 26 | ||
| @@ -51,7 +47,6 @@ endchoice | |||
| 51 | 47 | ||
| 52 | source "arch/arm/mach-imx/Kconfig" | 48 | source "arch/arm/mach-imx/Kconfig" |
| 53 | source "arch/arm/mach-mx3/Kconfig" | 49 | source "arch/arm/mach-mx3/Kconfig" |
| 54 | source "arch/arm/mach-mx25/Kconfig" | ||
| 55 | source "arch/arm/mach-mxc91231/Kconfig" | 50 | source "arch/arm/mach-mxc91231/Kconfig" |
| 56 | source "arch/arm/mach-mx5/Kconfig" | 51 | source "arch/arm/mach-mx5/Kconfig" |
| 57 | 52 | ||
| @@ -68,12 +63,10 @@ config MXC_IRQ_PRIOR | |||
| 68 | Say N here, unless you have a specialized requirement. | 63 | Say N here, unless you have a specialized requirement. |
| 69 | 64 | ||
| 70 | config MXC_TZIC | 65 | config MXC_TZIC |
| 71 | bool "Enable TrustZone Interrupt Controller" | 66 | bool |
| 72 | depends on ARCH_MX51 | 67 | |
| 73 | help | 68 | config MXC_AVIC |
| 74 | This will be automatically selected for all processors | 69 | bool |
| 75 | containing this interrupt controller. | ||
| 76 | Say N here only if you are really sure. | ||
| 77 | 70 | ||
| 78 | config MXC_PWM | 71 | config MXC_PWM |
| 79 | tristate "Enable PWM driver" | 72 | tristate "Enable PWM driver" |
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index 372670952789..5fd20e96876c 100644 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile | |||
| @@ -3,10 +3,11 @@ | |||
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | # Common support | 5 | # Common support |
| 6 | obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o | 6 | obj-y := clock.o gpio.o time.o devices.o cpu.o system.o irq-common.o |
| 7 | 7 | ||
| 8 | # MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o) | 8 | # MX51 uses the TZIC interrupt controller, older platforms use AVIC |
| 9 | obj-$(CONFIG_MXC_TZIC) += tzic.o | 9 | obj-$(CONFIG_MXC_TZIC) += tzic.o |
| 10 | obj-$(CONFIG_MXC_AVIC) += avic.o | ||
| 10 | 11 | ||
| 11 | obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o | 12 | obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o |
| 12 | obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o | 13 | obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o |
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c index 0be1ac7f421b..175e3647bb27 100644 --- a/arch/arm/plat-mxc/audmux-v2.c +++ b/arch/arm/plat-mxc/audmux-v2.c | |||
| @@ -209,7 +209,7 @@ static int mxc_audmux_v2_init(void) | |||
| 209 | audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR); | 209 | audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR); |
| 210 | } | 210 | } |
| 211 | #endif | 211 | #endif |
| 212 | #if defined(CONFIG_ARCH_MX25) | 212 | #if defined(CONFIG_SOC_IMX25) |
| 213 | if (cpu_is_mx25()) { | 213 | if (cpu_is_mx25()) { |
| 214 | audmux_clk = clk_get(NULL, "audmux"); | 214 | audmux_clk = clk_get(NULL, "audmux"); |
| 215 | if (IS_ERR(audmux_clk)) { | 215 | if (IS_ERR(audmux_clk)) { |
| @@ -220,7 +220,7 @@ static int mxc_audmux_v2_init(void) | |||
| 220 | } | 220 | } |
| 221 | audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR); | 221 | audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR); |
| 222 | } | 222 | } |
| 223 | #endif | 223 | #endif /* if defined(CONFIG_SOC_IMX25) */ |
| 224 | audmux_debugfs_init(); | 224 | audmux_debugfs_init(); |
| 225 | 225 | ||
| 226 | return 0; | 226 | return 0; |
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/avic.c index 7331f2ace5fe..9a4e8a22dd0a 100644 --- a/arch/arm/plat-mxc/irq.c +++ b/arch/arm/plat-mxc/avic.c | |||
| @@ -24,6 +24,8 @@ | |||
| 24 | #include <asm/mach/irq.h> | 24 | #include <asm/mach/irq.h> |
| 25 | #include <mach/hardware.h> | 25 | #include <mach/hardware.h> |
| 26 | 26 | ||
| 27 | #include "irq-common.h" | ||
| 28 | |||
| 27 | #define AVIC_INTCNTL 0x00 /* int control reg */ | 29 | #define AVIC_INTCNTL 0x00 /* int control reg */ |
| 28 | #define AVIC_NIMASK 0x04 /* int mask reg */ | 30 | #define AVIC_NIMASK 0x04 /* int mask reg */ |
| 29 | #define AVIC_INTENNUM 0x08 /* int enable number reg */ | 31 | #define AVIC_INTENNUM 0x08 /* int enable number reg */ |
| @@ -46,9 +48,9 @@ | |||
| 46 | 48 | ||
| 47 | void __iomem *avic_base; | 49 | void __iomem *avic_base; |
| 48 | 50 | ||
| 49 | int imx_irq_set_priority(unsigned char irq, unsigned char prio) | ||
| 50 | { | ||
| 51 | #ifdef CONFIG_MXC_IRQ_PRIOR | 51 | #ifdef CONFIG_MXC_IRQ_PRIOR |
| 52 | static int avic_irq_set_priority(unsigned char irq, unsigned char prio) | ||
| 53 | { | ||
| 52 | unsigned int temp; | 54 | unsigned int temp; |
| 53 | unsigned int mask = 0x0F << irq % 8 * 4; | 55 | unsigned int mask = 0x0F << irq % 8 * 4; |
| 54 | 56 | ||
| @@ -62,14 +64,11 @@ int imx_irq_set_priority(unsigned char irq, unsigned char prio) | |||
| 62 | __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8)); | 64 | __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8)); |
| 63 | 65 | ||
| 64 | return 0; | 66 | return 0; |
| 65 | #else | ||
| 66 | return -ENOSYS; | ||
| 67 | #endif | ||
| 68 | } | 67 | } |
| 69 | EXPORT_SYMBOL(imx_irq_set_priority); | 68 | #endif |
| 70 | 69 | ||
| 71 | #ifdef CONFIG_FIQ | 70 | #ifdef CONFIG_FIQ |
| 72 | int mxc_set_irq_fiq(unsigned int irq, unsigned int type) | 71 | static int avic_set_irq_fiq(unsigned int irq, unsigned int type) |
| 73 | { | 72 | { |
| 74 | unsigned int irqt; | 73 | unsigned int irqt; |
| 75 | 74 | ||
| @@ -87,7 +86,6 @@ int mxc_set_irq_fiq(unsigned int irq, unsigned int type) | |||
| 87 | 86 | ||
| 88 | return 0; | 87 | return 0; |
| 89 | } | 88 | } |
| 90 | EXPORT_SYMBOL(mxc_set_irq_fiq); | ||
| 91 | #endif /* CONFIG_FIQ */ | 89 | #endif /* CONFIG_FIQ */ |
| 92 | 90 | ||
| 93 | /* Disable interrupt number "irq" in the AVIC */ | 91 | /* Disable interrupt number "irq" in the AVIC */ |
| @@ -102,10 +100,18 @@ static void mxc_unmask_irq(unsigned int irq) | |||
| 102 | __raw_writel(irq, avic_base + AVIC_INTENNUM); | 100 | __raw_writel(irq, avic_base + AVIC_INTENNUM); |
| 103 | } | 101 | } |
| 104 | 102 | ||
| 105 | static struct irq_chip mxc_avic_chip = { | 103 | static struct mxc_irq_chip mxc_avic_chip = { |
| 106 | .ack = mxc_mask_irq, | 104 | .base = { |
| 107 | .mask = mxc_mask_irq, | 105 | .ack = mxc_mask_irq, |
| 108 | .unmask = mxc_unmask_irq, | 106 | .mask = mxc_mask_irq, |
| 107 | .unmask = mxc_unmask_irq, | ||
| 108 | }, | ||
| 109 | #ifdef CONFIG_MXC_IRQ_PRIOR | ||
| 110 | .set_priority = avic_irq_set_priority, | ||
| 111 | #endif | ||
| 112 | #ifdef CONFIG_FIQ | ||
| 113 | .set_irq_fiq = avic_set_irq_fiq, | ||
| 114 | #endif | ||
| 109 | }; | 115 | }; |
| 110 | 116 | ||
| 111 | /* | 117 | /* |
| @@ -133,7 +139,7 @@ void __init mxc_init_irq(void __iomem *irqbase) | |||
| 133 | __raw_writel(0, avic_base + AVIC_INTTYPEH); | 139 | __raw_writel(0, avic_base + AVIC_INTTYPEH); |
| 134 | __raw_writel(0, avic_base + AVIC_INTTYPEL); | 140 | __raw_writel(0, avic_base + AVIC_INTTYPEL); |
| 135 | for (i = 0; i < MXC_INTERNAL_IRQS; i++) { | 141 | for (i = 0; i < MXC_INTERNAL_IRQS; i++) { |
| 136 | set_irq_chip(i, &mxc_avic_chip); | 142 | set_irq_chip(i, &mxc_avic_chip.base); |
| 137 | set_irq_handler(i, handle_level_irq); | 143 | set_irq_handler(i, handle_level_irq); |
| 138 | set_irq_flags(i, IRQF_VALID); | 144 | set_irq_flags(i, IRQF_VALID); |
| 139 | } | 145 | } |
diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c index 039538e68793..ce81481becf1 100644 --- a/arch/arm/plat-mxc/cpufreq.c +++ b/arch/arm/plat-mxc/cpufreq.c | |||
| @@ -144,7 +144,6 @@ static int __init mxc_cpufreq_init(struct cpufreq_policy *policy) | |||
| 144 | imx_freq_table[i].frequency = CPUFREQ_TABLE_END; | 144 | imx_freq_table[i].frequency = CPUFREQ_TABLE_END; |
| 145 | 145 | ||
| 146 | policy->cur = clk_get_rate(cpu_clk) / 1000; | 146 | policy->cur = clk_get_rate(cpu_clk) / 1000; |
| 147 | policy->governor = CPUFREQ_DEFAULT_GOVERNOR; | ||
| 148 | policy->min = policy->cpuinfo.min_freq = cpu_freq_khz_min; | 147 | policy->min = policy->cpuinfo.min_freq = cpu_freq_khz_min; |
| 149 | policy->max = policy->cpuinfo.max_freq = cpu_freq_khz_max; | 148 | policy->max = policy->cpuinfo.max_freq = cpu_freq_khz_max; |
| 150 | 149 | ||
diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c index 735776d84956..e9bcefe79a43 100644 --- a/arch/arm/plat-mxc/devices.c +++ b/arch/arm/plat-mxc/devices.c | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | */ | 17 | */ |
| 18 | 18 | ||
| 19 | #include <linux/kernel.h> | 19 | #include <linux/kernel.h> |
| 20 | #include <linux/slab.h> | ||
| 20 | #include <linux/init.h> | 21 | #include <linux/init.h> |
| 21 | #include <linux/err.h> | 22 | #include <linux/err.h> |
| 22 | #include <linux/platform_device.h> | 23 | #include <linux/platform_device.h> |
| @@ -36,9 +37,10 @@ int __init mxc_register_device(struct platform_device *pdev, void *data) | |||
| 36 | return ret; | 37 | return ret; |
| 37 | } | 38 | } |
| 38 | 39 | ||
| 39 | struct platform_device *__init imx_add_platform_device(const char *name, int id, | 40 | struct platform_device *__init imx_add_platform_device_dmamask( |
| 41 | const char *name, int id, | ||
| 40 | const struct resource *res, unsigned int num_resources, | 42 | const struct resource *res, unsigned int num_resources, |
| 41 | const void *data, size_t size_data) | 43 | const void *data, size_t size_data, u64 dmamask) |
| 42 | { | 44 | { |
| 43 | int ret = -ENOMEM; | 45 | int ret = -ENOMEM; |
| 44 | struct platform_device *pdev; | 46 | struct platform_device *pdev; |
| @@ -47,6 +49,23 @@ struct platform_device *__init imx_add_platform_device(const char *name, int id, | |||
| 47 | if (!pdev) | 49 | if (!pdev) |
| 48 | goto err; | 50 | goto err; |
| 49 | 51 | ||
| 52 | if (dmamask) { | ||
| 53 | /* | ||
| 54 | * This memory isn't freed when the device is put, | ||
| 55 | * I don't have a nice idea for that though. Conceptually | ||
| 56 | * dma_mask in struct device should not be a pointer. | ||
| 57 | * See http://thread.gmane.org/gmane.linux.kernel.pci/9081 | ||
| 58 | */ | ||
| 59 | pdev->dev.dma_mask = | ||
| 60 | kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL); | ||
| 61 | if (!pdev->dev.dma_mask) | ||
| 62 | /* ret is still -ENOMEM; */ | ||
| 63 | goto err; | ||
| 64 | |||
| 65 | *pdev->dev.dma_mask = dmamask; | ||
| 66 | pdev->dev.coherent_dma_mask = dmamask; | ||
| 67 | } | ||
| 68 | |||
| 50 | if (res) { | 69 | if (res) { |
| 51 | ret = platform_device_add_resources(pdev, res, num_resources); | 70 | ret = platform_device_add_resources(pdev, res, num_resources); |
| 52 | if (ret) | 71 | if (ret) |
diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index 9aa6f3ea9012..2537166468ac 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig | |||
| @@ -1,29 +1,73 @@ | |||
| 1 | config IMX_HAVE_PLATFORM_ESDHC | ||
| 2 | bool | ||
| 3 | |||
| 4 | config IMX_HAVE_PLATFORM_FEC | 1 | config IMX_HAVE_PLATFORM_FEC |
| 5 | bool | 2 | bool |
| 6 | default y if ARCH_MX25 || SOC_IMX27 || ARCH_MX35 || ARCH_MX51 | 3 | default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX51 |
| 7 | 4 | ||
| 8 | config IMX_HAVE_PLATFORM_FLEXCAN | 5 | config IMX_HAVE_PLATFORM_FLEXCAN |
| 9 | select HAVE_CAN_FLEXCAN if CAN | 6 | select HAVE_CAN_FLEXCAN if CAN |
| 10 | bool | 7 | bool |
| 11 | 8 | ||
| 9 | config IMX_HAVE_PLATFORM_FSL_USB2_UDC | ||
| 10 | bool | ||
| 11 | |||
| 12 | config IMX_HAVE_PLATFORM_GPIO_KEYS | 12 | config IMX_HAVE_PLATFORM_GPIO_KEYS |
| 13 | bool | 13 | bool |
| 14 | default y if ARCH_MX51 | 14 | default y if SOC_IMX51 |
| 15 | |||
| 16 | config IMX_HAVE_PLATFORM_IMX21_HCD | ||
| 17 | bool | ||
| 15 | 18 | ||
| 19 | config IMX_HAVE_PLATFORM_IMX2_WDT | ||
| 20 | bool | ||
| 21 | |||
| 22 | config IMX_HAVE_PLATFORM_IMXDI_RTC | ||
| 23 | bool | ||
| 24 | |||
| 25 | config IMX_HAVE_PLATFORM_IMX_FB | ||
| 26 | bool | ||
| 27 | select HAVE_FB_IMX | ||
| 28 | |||
| 16 | config IMX_HAVE_PLATFORM_IMX_I2C | 29 | config IMX_HAVE_PLATFORM_IMX_I2C |
| 17 | bool | 30 | bool |
| 18 | 31 | ||
| 32 | config IMX_HAVE_PLATFORM_IMX_KEYPAD | ||
| 33 | bool | ||
| 34 | |||
| 19 | config IMX_HAVE_PLATFORM_IMX_SSI | 35 | config IMX_HAVE_PLATFORM_IMX_SSI |
| 20 | bool | 36 | bool |
| 21 | 37 | ||
| 22 | config IMX_HAVE_PLATFORM_IMX_UART | 38 | config IMX_HAVE_PLATFORM_IMX_UART |
| 23 | bool | 39 | bool |
| 24 | 40 | ||
| 41 | config IMX_HAVE_PLATFORM_IMX_UDC | ||
| 42 | bool | ||
| 43 | |||
| 44 | config IMX_HAVE_PLATFORM_MX1_CAMERA | ||
| 45 | bool | ||
| 46 | |||
| 47 | config IMX_HAVE_PLATFORM_MX2_CAMERA | ||
| 48 | bool | ||
| 49 | |||
| 50 | config IMX_HAVE_PLATFORM_MXC_EHCI | ||
| 51 | bool | ||
| 52 | |||
| 53 | config IMX_HAVE_PLATFORM_MXC_MMC | ||
| 54 | bool | ||
| 55 | |||
| 25 | config IMX_HAVE_PLATFORM_MXC_NAND | 56 | config IMX_HAVE_PLATFORM_MXC_NAND |
| 26 | bool | 57 | bool |
| 27 | 58 | ||
| 59 | config IMX_HAVE_PLATFORM_MXC_PWM | ||
| 60 | bool | ||
| 61 | |||
| 62 | config IMX_HAVE_PLATFORM_MXC_RNGA | ||
| 63 | bool | ||
| 64 | select ARCH_HAS_RNGA | ||
| 65 | |||
| 66 | config IMX_HAVE_PLATFORM_MXC_W1 | ||
| 67 | bool | ||
| 68 | |||
| 69 | config IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | ||
| 70 | bool | ||
| 71 | |||
| 28 | config IMX_HAVE_PLATFORM_SPI_IMX | 72 | config IMX_HAVE_PLATFORM_SPI_IMX |
| 29 | bool | 73 | bool |
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index 45aefeb283ba..75cd2ece9053 100644 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile | |||
| @@ -1,10 +1,24 @@ | |||
| 1 | obj-$(CONFIG_IMX_HAVE_PLATFORM_ESDHC) += platform-esdhc.o | ||
| 2 | obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o | 1 | obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o |
| 3 | obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o | 2 | obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o |
| 3 | obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC) += platform-fsl-usb2-udc.o | ||
| 4 | obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o | 4 | obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o |
| 5 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o | ||
| 6 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o | ||
| 7 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o | ||
| 5 | obj-y += platform-imx-dma.o | 8 | obj-y += platform-imx-dma.o |
| 9 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o | ||
| 6 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o | 10 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o |
| 11 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD) += platform-imx-keypad.o | ||
| 7 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o | 12 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o |
| 8 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o | 13 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o |
| 14 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o | ||
| 15 | obj-$(CONFIG_IMX_HAVE_PLATFORM_MX1_CAMERA) += platform-mx1-camera.o | ||
| 16 | obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o | ||
| 17 | obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o | ||
| 18 | obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o | ||
| 9 | obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o | 19 | obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o |
| 20 | obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o | ||
| 21 | obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA) += platform-mxc_rnga.o | ||
| 22 | obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o | ||
| 23 | obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o | ||
| 10 | obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o | 24 | obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o |
diff --git a/arch/arm/plat-mxc/devices/platform-esdhc.c b/arch/arm/plat-mxc/devices/platform-esdhc.c deleted file mode 100644 index 2605bfa0dfb0..000000000000 --- a/arch/arm/plat-mxc/devices/platform-esdhc.c +++ /dev/null | |||
| @@ -1,71 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix, Wolfram Sang <w.sang@pengutronix.de> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it under | ||
| 5 | * the terms of the GNU General Public License version 2 as published by the | ||
| 6 | * Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <mach/hardware.h> | ||
| 10 | #include <mach/devices-common.h> | ||
| 11 | #include <mach/esdhc.h> | ||
| 12 | |||
| 13 | #define imx_esdhc_imx_data_entry_single(soc, _id, hwid) \ | ||
| 14 | { \ | ||
| 15 | .id = _id, \ | ||
| 16 | .iobase = soc ## _ESDHC ## hwid ## _BASE_ADDR, \ | ||
| 17 | .irq = soc ## _INT_ESDHC ## hwid, \ | ||
| 18 | } | ||
| 19 | |||
| 20 | #define imx_esdhc_imx_data_entry(soc, id, hwid) \ | ||
| 21 | [id] = imx_esdhc_imx_data_entry_single(soc, id, hwid) | ||
| 22 | |||
| 23 | #ifdef CONFIG_ARCH_MX25 | ||
| 24 | const struct imx_esdhc_imx_data imx25_esdhc_data[] __initconst = { | ||
| 25 | #define imx25_esdhc_data_entry(_id, _hwid) \ | ||
| 26 | imx_esdhc_imx_data_entry(MX25, _id, _hwid) | ||
| 27 | imx25_esdhc_data_entry(0, 1), | ||
| 28 | imx25_esdhc_data_entry(1, 2), | ||
| 29 | }; | ||
| 30 | #endif /* ifdef CONFIG_ARCH_MX25 */ | ||
| 31 | |||
| 32 | #ifdef CONFIG_ARCH_MX35 | ||
| 33 | const struct imx_esdhc_imx_data imx35_esdhc_data[] __initconst = { | ||
| 34 | #define imx35_esdhc_data_entry(_id, _hwid) \ | ||
| 35 | imx_esdhc_imx_data_entry(MX35, _id, _hwid) | ||
| 36 | imx35_esdhc_data_entry(0, 1), | ||
| 37 | imx35_esdhc_data_entry(1, 2), | ||
| 38 | imx35_esdhc_data_entry(2, 3), | ||
| 39 | }; | ||
| 40 | #endif /* ifdef CONFIG_ARCH_MX35 */ | ||
| 41 | |||
| 42 | #ifdef CONFIG_ARCH_MX51 | ||
| 43 | const struct imx_esdhc_imx_data imx51_esdhc_data[] __initconst = { | ||
| 44 | #define imx51_esdhc_data_entry(_id, _hwid) \ | ||
| 45 | imx_esdhc_imx_data_entry(MX51, _id, _hwid) | ||
| 46 | imx51_esdhc_data_entry(0, 1), | ||
| 47 | imx51_esdhc_data_entry(1, 2), | ||
| 48 | imx51_esdhc_data_entry(2, 3), | ||
| 49 | imx51_esdhc_data_entry(3, 4), | ||
| 50 | }; | ||
| 51 | #endif /* ifdef CONFIG_ARCH_MX51 */ | ||
| 52 | |||
| 53 | struct platform_device *__init imx_add_esdhc( | ||
| 54 | const struct imx_esdhc_imx_data *data, | ||
| 55 | const struct esdhc_platform_data *pdata) | ||
| 56 | { | ||
| 57 | struct resource res[] = { | ||
| 58 | { | ||
| 59 | .start = data->iobase, | ||
| 60 | .end = data->iobase + SZ_16K - 1, | ||
| 61 | .flags = IORESOURCE_MEM, | ||
| 62 | }, { | ||
| 63 | .start = data->irq, | ||
| 64 | .end = data->irq, | ||
| 65 | .flags = IORESOURCE_IRQ, | ||
| 66 | }, | ||
| 67 | }; | ||
| 68 | |||
| 69 | return imx_add_platform_device("sdhci-esdhc-imx", data->id, res, | ||
| 70 | ARRAY_SIZE(res), pdata, sizeof(*pdata)); | ||
| 71 | } | ||
diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/plat-mxc/devices/platform-fec.c index 11d087f4e219..269ec78aba77 100644 --- a/arch/arm/plat-mxc/devices/platform-fec.c +++ b/arch/arm/plat-mxc/devices/platform-fec.c | |||
| @@ -16,22 +16,22 @@ | |||
| 16 | .irq = soc ## _INT_FEC, \ | 16 | .irq = soc ## _INT_FEC, \ |
| 17 | } | 17 | } |
| 18 | 18 | ||
| 19 | #ifdef CONFIG_ARCH_MX25 | 19 | #ifdef CONFIG_SOC_IMX25 |
| 20 | const struct imx_fec_data imx25_fec_data __initconst = | 20 | const struct imx_fec_data imx25_fec_data __initconst = |
| 21 | imx_fec_data_entry_single(MX25); | 21 | imx_fec_data_entry_single(MX25); |
| 22 | #endif /* ifdef CONFIG_ARCH_MX25 */ | 22 | #endif /* ifdef CONFIG_SOC_IMX25 */ |
| 23 | 23 | ||
| 24 | #ifdef CONFIG_SOC_IMX27 | 24 | #ifdef CONFIG_SOC_IMX27 |
| 25 | const struct imx_fec_data imx27_fec_data __initconst = | 25 | const struct imx_fec_data imx27_fec_data __initconst = |
| 26 | imx_fec_data_entry_single(MX27); | 26 | imx_fec_data_entry_single(MX27); |
| 27 | #endif /* ifdef CONFIG_SOC_IMX27 */ | 27 | #endif /* ifdef CONFIG_SOC_IMX27 */ |
| 28 | 28 | ||
| 29 | #ifdef CONFIG_ARCH_MX35 | 29 | #ifdef CONFIG_SOC_IMX35 |
| 30 | const struct imx_fec_data imx35_fec_data __initconst = | 30 | const struct imx_fec_data imx35_fec_data __initconst = |
| 31 | imx_fec_data_entry_single(MX35); | 31 | imx_fec_data_entry_single(MX35); |
| 32 | #endif | 32 | #endif |
| 33 | 33 | ||
| 34 | #ifdef CONFIG_ARCH_MX51 | 34 | #ifdef CONFIG_SOC_IMX51 |
| 35 | const struct imx_fec_data imx51_fec_data __initconst = | 35 | const struct imx_fec_data imx51_fec_data __initconst = |
| 36 | imx_fec_data_entry_single(MX51); | 36 | imx_fec_data_entry_single(MX51); |
| 37 | #endif | 37 | #endif |
diff --git a/arch/arm/plat-mxc/devices/platform-flexcan.c b/arch/arm/plat-mxc/devices/platform-flexcan.c index 5e97a01f14f3..4e8497af2eb1 100644 --- a/arch/arm/plat-mxc/devices/platform-flexcan.c +++ b/arch/arm/plat-mxc/devices/platform-flexcan.c | |||
| @@ -5,26 +5,54 @@ | |||
| 5 | * the terms of the GNU General Public License version 2 as published by the | 5 | * the terms of the GNU General Public License version 2 as published by the |
| 6 | * Free Software Foundation. | 6 | * Free Software Foundation. |
| 7 | */ | 7 | */ |
| 8 | 8 | #include <mach/hardware.h> | |
| 9 | #include <mach/devices-common.h> | 9 | #include <mach/devices-common.h> |
| 10 | 10 | ||
| 11 | struct platform_device *__init imx_add_flexcan(int id, | 11 | #define imx_flexcan_data_entry_single(soc, _id, _hwid, _size) \ |
| 12 | resource_size_t iobase, resource_size_t iosize, | 12 | { \ |
| 13 | resource_size_t irq, | 13 | .id = _id, \ |
| 14 | .iobase = soc ## _CAN ## _hwid ## _BASE_ADDR, \ | ||
| 15 | .iosize = _size, \ | ||
| 16 | .irq = soc ## _INT_CAN ## _hwid, \ | ||
| 17 | } | ||
| 18 | |||
| 19 | #define imx_flexcan_data_entry(soc, _id, _hwid, _size) \ | ||
| 20 | [_id] = imx_flexcan_data_entry_single(soc, _id, _hwid, _size) | ||
| 21 | |||
| 22 | #ifdef CONFIG_SOC_IMX25 | ||
| 23 | const struct imx_flexcan_data imx25_flexcan_data[] __initconst = { | ||
| 24 | #define imx25_flexcan_data_entry(_id, _hwid) \ | ||
| 25 | imx_flexcan_data_entry(MX25, _id, _hwid, SZ_16K) | ||
| 26 | imx25_flexcan_data_entry(0, 1), | ||
| 27 | imx25_flexcan_data_entry(1, 2), | ||
| 28 | }; | ||
| 29 | #endif /* ifdef CONFIG_SOC_IMX25 */ | ||
| 30 | |||
| 31 | #ifdef CONFIG_SOC_IMX35 | ||
| 32 | const struct imx_flexcan_data imx35_flexcan_data[] __initconst = { | ||
| 33 | #define imx35_flexcan_data_entry(_id, _hwid) \ | ||
| 34 | imx_flexcan_data_entry(MX35, _id, _hwid, SZ_16K) | ||
| 35 | imx35_flexcan_data_entry(0, 1), | ||
| 36 | imx35_flexcan_data_entry(1, 2), | ||
| 37 | }; | ||
| 38 | #endif /* ifdef CONFIG_SOC_IMX35 */ | ||
| 39 | |||
| 40 | struct platform_device *__init imx_add_flexcan( | ||
| 41 | const struct imx_flexcan_data *data, | ||
| 14 | const struct flexcan_platform_data *pdata) | 42 | const struct flexcan_platform_data *pdata) |
| 15 | { | 43 | { |
| 16 | struct resource res[] = { | 44 | struct resource res[] = { |
| 17 | { | 45 | { |
| 18 | .start = iobase, | 46 | .start = data->iobase, |
| 19 | .end = iobase + iosize - 1, | 47 | .end = data->iobase + data->iosize - 1, |
| 20 | .flags = IORESOURCE_MEM, | 48 | .flags = IORESOURCE_MEM, |
| 21 | }, { | 49 | }, { |
| 22 | .start = irq, | 50 | .start = data->irq, |
| 23 | .end = irq, | 51 | .end = data->irq, |
| 24 | .flags = IORESOURCE_IRQ, | 52 | .flags = IORESOURCE_IRQ, |
| 25 | }, | 53 | }, |
| 26 | }; | 54 | }; |
| 27 | 55 | ||
| 28 | return imx_add_platform_device("flexcan", id, res, ARRAY_SIZE(res), | 56 | return imx_add_platform_device("flexcan", data->id, |
| 29 | pdata, sizeof(*pdata)); | 57 | res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); |
| 30 | } | 58 | } |
diff --git a/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c new file mode 100644 index 000000000000..59c33f6e401c --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c | |||
| @@ -0,0 +1,56 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <mach/hardware.h> | ||
| 10 | #include <mach/devices-common.h> | ||
| 11 | |||
| 12 | #define imx_fsl_usb2_udc_data_entry_single(soc) \ | ||
| 13 | { \ | ||
| 14 | .iobase = soc ## _USB_OTG_BASE_ADDR, \ | ||
| 15 | .irq = soc ## _INT_USB_OTG, \ | ||
| 16 | } | ||
| 17 | |||
| 18 | #ifdef CONFIG_SOC_IMX25 | ||
| 19 | const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst = | ||
| 20 | imx_fsl_usb2_udc_data_entry_single(MX25); | ||
| 21 | #endif /* ifdef CONFIG_SOC_IMX25 */ | ||
| 22 | |||
| 23 | #ifdef CONFIG_SOC_IMX27 | ||
| 24 | const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst = | ||
| 25 | imx_fsl_usb2_udc_data_entry_single(MX27); | ||
| 26 | #endif /* ifdef CONFIG_SOC_IMX27 */ | ||
| 27 | |||
| 28 | #ifdef CONFIG_SOC_IMX31 | ||
| 29 | const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst = | ||
| 30 | imx_fsl_usb2_udc_data_entry_single(MX31); | ||
| 31 | #endif /* ifdef CONFIG_SOC_IMX31 */ | ||
| 32 | |||
| 33 | #ifdef CONFIG_SOC_IMX35 | ||
| 34 | const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst = | ||
| 35 | imx_fsl_usb2_udc_data_entry_single(MX35); | ||
| 36 | #endif /* ifdef CONFIG_SOC_IMX35 */ | ||
| 37 | |||
| 38 | struct platform_device *__init imx_add_fsl_usb2_udc( | ||
| 39 | const struct imx_fsl_usb2_udc_data *data, | ||
| 40 | const struct fsl_usb2_platform_data *pdata) | ||
| 41 | { | ||
| 42 | struct resource res[] = { | ||
| 43 | { | ||
| 44 | .start = data->iobase, | ||
| 45 | .end = data->iobase + SZ_512 - 1, | ||
| 46 | .flags = IORESOURCE_MEM, | ||
| 47 | }, { | ||
| 48 | .start = data->irq, | ||
| 49 | .end = data->irq, | ||
| 50 | .flags = IORESOURCE_IRQ, | ||
| 51 | }, | ||
| 52 | }; | ||
| 53 | return imx_add_platform_device_dmamask("fsl-usb2-udc", -1, | ||
| 54 | res, ARRAY_SIZE(res), | ||
| 55 | pdata, sizeof(*pdata), DMA_BIT_MASK(32)); | ||
| 56 | } | ||
diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c index 3a705c7877dd..33530d2d5ed1 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-dma.c +++ b/arch/arm/plat-mxc/devices/platform-imx-dma.c | |||
| @@ -31,25 +31,25 @@ struct imx_imx_sdma_data { | |||
| 31 | }, \ | 31 | }, \ |
| 32 | } | 32 | } |
| 33 | 33 | ||
| 34 | #ifdef CONFIG_ARCH_MX25 | 34 | #ifdef CONFIG_SOC_IMX25 |
| 35 | const struct imx_imx_sdma_data imx25_imx_sdma_data __initconst = | 35 | struct imx_imx_sdma_data imx25_imx_sdma_data __initconst = |
| 36 | imx_imx_sdma_data_entry_single(MX25, 1, "imx25", 0); | 36 | imx_imx_sdma_data_entry_single(MX25, 1, "imx25", 0); |
| 37 | #endif /* ifdef CONFIG_ARCH_MX25 */ | 37 | #endif /* ifdef CONFIG_SOC_IMX25 */ |
| 38 | 38 | ||
| 39 | #ifdef CONFIG_ARCH_MX31 | 39 | #ifdef CONFIG_SOC_IMX31 |
| 40 | struct imx_imx_sdma_data imx31_imx_sdma_data __initdata = | 40 | struct imx_imx_sdma_data imx31_imx_sdma_data __initdata = |
| 41 | imx_imx_sdma_data_entry_single(MX31, 1, "imx31", 0); | 41 | imx_imx_sdma_data_entry_single(MX31, 1, "imx31", 0); |
| 42 | #endif /* ifdef CONFIG_ARCH_MX31 */ | 42 | #endif /* ifdef CONFIG_SOC_IMX31 */ |
| 43 | 43 | ||
| 44 | #ifdef CONFIG_ARCH_MX35 | 44 | #ifdef CONFIG_SOC_IMX35 |
| 45 | struct imx_imx_sdma_data imx35_imx_sdma_data __initdata = | 45 | struct imx_imx_sdma_data imx35_imx_sdma_data __initdata = |
| 46 | imx_imx_sdma_data_entry_single(MX35, 2, "imx35", 0); | 46 | imx_imx_sdma_data_entry_single(MX35, 2, "imx35", 0); |
| 47 | #endif /* ifdef CONFIG_ARCH_MX35 */ | 47 | #endif /* ifdef CONFIG_SOC_IMX35 */ |
| 48 | 48 | ||
| 49 | #ifdef CONFIG_ARCH_MX51 | 49 | #ifdef CONFIG_SOC_IMX51 |
| 50 | const struct imx_imx_sdma_data imx51_imx_sdma_data __initconst = | 50 | struct imx_imx_sdma_data imx51_imx_sdma_data __initconst = |
| 51 | imx_imx_sdma_data_entry_single(MX51, 2, "imx51", 0); | 51 | imx_imx_sdma_data_entry_single(MX51, 2, "imx51", 0); |
| 52 | #endif /* ifdef CONFIG_ARCH_MX51 */ | 52 | #endif /* ifdef CONFIG_SOC_IMX51 */ |
| 53 | 53 | ||
| 54 | static struct platform_device __init __maybe_unused *imx_add_imx_sdma( | 54 | static struct platform_device __init __maybe_unused *imx_add_imx_sdma( |
| 55 | const struct imx_imx_sdma_data *data) | 55 | const struct imx_imx_sdma_data *data) |
| @@ -76,6 +76,83 @@ static struct platform_device __init __maybe_unused *imx_add_imx_dma(void) | |||
| 76 | return imx_add_platform_device("imx-dma", -1, NULL, 0, NULL, 0); | 76 | return imx_add_platform_device("imx-dma", -1, NULL, 0, NULL, 0); |
| 77 | } | 77 | } |
| 78 | 78 | ||
| 79 | #ifdef CONFIG_ARCH_MX25 | ||
| 80 | static struct sdma_script_start_addrs addr_imx25_to1 = { | ||
| 81 | .ap_2_ap_addr = 729, | ||
| 82 | .uart_2_mcu_addr = 904, | ||
| 83 | .per_2_app_addr = 1255, | ||
| 84 | .mcu_2_app_addr = 834, | ||
| 85 | .uartsh_2_mcu_addr = 1120, | ||
| 86 | .per_2_shp_addr = 1329, | ||
| 87 | .mcu_2_shp_addr = 1048, | ||
| 88 | .ata_2_mcu_addr = 1560, | ||
| 89 | .mcu_2_ata_addr = 1479, | ||
| 90 | .app_2_per_addr = 1189, | ||
| 91 | .app_2_mcu_addr = 770, | ||
| 92 | .shp_2_per_addr = 1407, | ||
| 93 | .shp_2_mcu_addr = 979, | ||
| 94 | }; | ||
| 95 | #endif | ||
| 96 | |||
| 97 | #ifdef CONFIG_ARCH_MX31 | ||
| 98 | static struct sdma_script_start_addrs addr_imx31_to1 = { | ||
| 99 | .per_2_per_addr = 1677, | ||
| 100 | }; | ||
| 101 | |||
| 102 | static struct sdma_script_start_addrs addr_imx31_to2 = { | ||
| 103 | .ap_2_ap_addr = 423, | ||
| 104 | .ap_2_bp_addr = 829, | ||
| 105 | .bp_2_ap_addr = 1029, | ||
| 106 | }; | ||
| 107 | #endif | ||
| 108 | |||
| 109 | #ifdef CONFIG_ARCH_MX35 | ||
| 110 | static struct sdma_script_start_addrs addr_imx35_to1 = { | ||
| 111 | .ap_2_ap_addr = 642, | ||
| 112 | .uart_2_mcu_addr = 817, | ||
| 113 | .mcu_2_app_addr = 747, | ||
| 114 | .uartsh_2_mcu_addr = 1183, | ||
| 115 | .per_2_shp_addr = 1033, | ||
| 116 | .mcu_2_shp_addr = 961, | ||
| 117 | .ata_2_mcu_addr = 1333, | ||
| 118 | .mcu_2_ata_addr = 1252, | ||
| 119 | .app_2_mcu_addr = 683, | ||
| 120 | .shp_2_per_addr = 1111, | ||
| 121 | .shp_2_mcu_addr = 892, | ||
| 122 | }; | ||
| 123 | |||
| 124 | static struct sdma_script_start_addrs addr_imx35_to2 = { | ||
| 125 | .ap_2_ap_addr = 729, | ||
| 126 | .uart_2_mcu_addr = 904, | ||
| 127 | .per_2_app_addr = 1597, | ||
| 128 | .mcu_2_app_addr = 834, | ||
| 129 | .uartsh_2_mcu_addr = 1270, | ||
| 130 | .per_2_shp_addr = 1120, | ||
| 131 | .mcu_2_shp_addr = 1048, | ||
| 132 | .ata_2_mcu_addr = 1429, | ||
| 133 | .mcu_2_ata_addr = 1339, | ||
| 134 | .app_2_per_addr = 1531, | ||
| 135 | .app_2_mcu_addr = 770, | ||
| 136 | .shp_2_per_addr = 1198, | ||
| 137 | .shp_2_mcu_addr = 979, | ||
| 138 | }; | ||
| 139 | #endif | ||
| 140 | |||
| 141 | #ifdef CONFIG_SOC_IMX51 | ||
| 142 | static struct sdma_script_start_addrs addr_imx51_to1 = { | ||
| 143 | .ap_2_ap_addr = 642, | ||
| 144 | .uart_2_mcu_addr = 817, | ||
| 145 | .mcu_2_app_addr = 747, | ||
| 146 | .mcu_2_shp_addr = 961, | ||
| 147 | .ata_2_mcu_addr = 1473, | ||
| 148 | .mcu_2_ata_addr = 1392, | ||
| 149 | .app_2_per_addr = 1033, | ||
| 150 | .app_2_mcu_addr = 683, | ||
| 151 | .shp_2_per_addr = 1251, | ||
| 152 | .shp_2_mcu_addr = 892, | ||
| 153 | }; | ||
| 154 | #endif | ||
| 155 | |||
| 79 | static int __init imxXX_add_imx_dma(void) | 156 | static int __init imxXX_add_imx_dma(void) |
| 80 | { | 157 | { |
| 81 | struct platform_device *ret; | 158 | struct platform_device *ret; |
| @@ -86,30 +163,42 @@ static int __init imxXX_add_imx_dma(void) | |||
| 86 | else | 163 | else |
| 87 | #endif | 164 | #endif |
| 88 | 165 | ||
| 89 | #if defined(CONFIG_ARCH_MX25) | 166 | #if defined(CONFIG_SOC_IMX25) |
| 90 | if (cpu_is_mx25()) | 167 | if (cpu_is_mx25()) { |
| 168 | imx25_imx_sdma_data.pdata.script_addrs = &addr_imx25_to1; | ||
| 91 | ret = imx_add_imx_sdma(&imx25_imx_sdma_data); | 169 | ret = imx_add_imx_sdma(&imx25_imx_sdma_data); |
| 92 | else | 170 | } else |
| 93 | #endif | 171 | #endif |
| 94 | 172 | ||
| 95 | #if defined(CONFIG_ARCH_MX31) | 173 | #if defined(CONFIG_SOC_IMX31) |
| 96 | if (cpu_is_mx31()) { | 174 | if (cpu_is_mx31()) { |
| 97 | imx31_imx_sdma_data.pdata.to_version = mx31_revision() >> 4; | 175 | int to_version = mx31_revision() >> 4; |
| 176 | imx31_imx_sdma_data.pdata.to_version = to_version; | ||
| 177 | if (to_version == 1) | ||
| 178 | imx31_imx_sdma_data.pdata.script_addrs = &addr_imx31_to1; | ||
| 179 | else | ||
| 180 | imx31_imx_sdma_data.pdata.script_addrs = &addr_imx31_to2; | ||
| 98 | ret = imx_add_imx_sdma(&imx31_imx_sdma_data); | 181 | ret = imx_add_imx_sdma(&imx31_imx_sdma_data); |
| 99 | } else | 182 | } else |
| 100 | #endif | 183 | #endif |
| 101 | 184 | ||
| 102 | #if defined(CONFIG_ARCH_MX35) | 185 | #if defined(CONFIG_SOC_IMX35) |
| 103 | if (cpu_is_mx35()) { | 186 | if (cpu_is_mx35()) { |
| 104 | imx35_imx_sdma_data.pdata.to_version = mx35_revision() >> 4; | 187 | int to_version = mx35_revision() >> 4; |
| 188 | imx35_imx_sdma_data.pdata.to_version = to_version; | ||
| 189 | if (to_version == 1) | ||
| 190 | imx35_imx_sdma_data.pdata.script_addrs = &addr_imx35_to1; | ||
| 191 | else | ||
| 192 | imx35_imx_sdma_data.pdata.script_addrs = &addr_imx35_to2; | ||
| 105 | ret = imx_add_imx_sdma(&imx35_imx_sdma_data); | 193 | ret = imx_add_imx_sdma(&imx35_imx_sdma_data); |
| 106 | } else | 194 | } else |
| 107 | #endif | 195 | #endif |
| 108 | 196 | ||
| 109 | #if defined(CONFIG_ARCH_MX51) | 197 | #if defined(CONFIG_ARCH_MX51) |
| 110 | if (cpu_is_mx51()) | 198 | if (cpu_is_mx51()) { |
| 199 | imx51_imx_sdma_data.pdata.script_addrs = &addr_imx51_to1; | ||
| 111 | ret = imx_add_imx_sdma(&imx51_imx_sdma_data); | 200 | ret = imx_add_imx_sdma(&imx51_imx_sdma_data); |
| 112 | else | 201 | } else |
| 113 | #endif | 202 | #endif |
| 114 | ret = ERR_PTR(-ENODEV); | 203 | ret = ERR_PTR(-ENODEV); |
| 115 | 204 | ||
diff --git a/arch/arm/plat-mxc/devices/platform-imx-fb.c b/arch/arm/plat-mxc/devices/platform-imx-fb.c new file mode 100644 index 000000000000..6100a7d824dd --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-fb.c | |||
| @@ -0,0 +1,52 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <mach/hardware.h> | ||
| 10 | #include <mach/devices-common.h> | ||
| 11 | |||
| 12 | #define imx_imx_fb_data_entry_single(soc, _size) \ | ||
| 13 | { \ | ||
| 14 | .iobase = soc ## _LCDC_BASE_ADDR, \ | ||
| 15 | .iosize = _size, \ | ||
| 16 | .irq = soc ## _INT_LCDC, \ | ||
| 17 | } | ||
| 18 | |||
| 19 | #ifdef CONFIG_SOC_IMX21 | ||
| 20 | const struct imx_imx_fb_data imx21_imx_fb_data __initconst = | ||
| 21 | imx_imx_fb_data_entry_single(MX21, SZ_4K); | ||
| 22 | #endif /* ifdef CONFIG_SOC_IMX21 */ | ||
| 23 | |||
| 24 | #ifdef CONFIG_SOC_IMX25 | ||
| 25 | const struct imx_imx_fb_data imx25_imx_fb_data __initconst = | ||
| 26 | imx_imx_fb_data_entry_single(MX25, SZ_16K); | ||
| 27 | #endif /* ifdef CONFIG_SOC_IMX25 */ | ||
| 28 | |||
| 29 | #ifdef CONFIG_SOC_IMX27 | ||
| 30 | const struct imx_imx_fb_data imx27_imx_fb_data __initconst = | ||
| 31 | imx_imx_fb_data_entry_single(MX27, SZ_4K); | ||
| 32 | #endif /* ifdef CONFIG_SOC_IMX27 */ | ||
| 33 | |||
| 34 | struct platform_device *__init imx_add_imx_fb( | ||
| 35 | const struct imx_imx_fb_data *data, | ||
| 36 | const struct imx_fb_platform_data *pdata) | ||
| 37 | { | ||
| 38 | struct resource res[] = { | ||
| 39 | { | ||
| 40 | .start = data->iobase, | ||
| 41 | .end = data->iobase + data->iosize - 1, | ||
| 42 | .flags = IORESOURCE_MEM, | ||
| 43 | }, { | ||
| 44 | .start = data->irq, | ||
| 45 | .end = data->irq, | ||
| 46 | .flags = IORESOURCE_IRQ, | ||
| 47 | }, | ||
| 48 | }; | ||
| 49 | return imx_add_platform_device_dmamask("imx-fb", 0, | ||
| 50 | res, ARRAY_SIZE(res), | ||
| 51 | pdata, sizeof(*pdata), DMA_BIT_MASK(32)); | ||
| 52 | } | ||
diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c index 679588453aad..72ba880c75af 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c +++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c | |||
| @@ -30,7 +30,7 @@ const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst = | |||
| 30 | imx_imx_i2c_data_entry_single(MX21, 0, , SZ_4K); | 30 | imx_imx_i2c_data_entry_single(MX21, 0, , SZ_4K); |
| 31 | #endif /* ifdef CONFIG_SOC_IMX21 */ | 31 | #endif /* ifdef CONFIG_SOC_IMX21 */ |
| 32 | 32 | ||
| 33 | #ifdef CONFIG_ARCH_MX25 | 33 | #ifdef CONFIG_SOC_IMX25 |
| 34 | const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = { | 34 | const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = { |
| 35 | #define imx25_imx_i2c_data_entry(_id, _hwid) \ | 35 | #define imx25_imx_i2c_data_entry(_id, _hwid) \ |
| 36 | imx_imx_i2c_data_entry(MX25, _id, _hwid, SZ_16K) | 36 | imx_imx_i2c_data_entry(MX25, _id, _hwid, SZ_16K) |
| @@ -38,7 +38,7 @@ const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = { | |||
| 38 | imx25_imx_i2c_data_entry(1, 2), | 38 | imx25_imx_i2c_data_entry(1, 2), |
| 39 | imx25_imx_i2c_data_entry(2, 3), | 39 | imx25_imx_i2c_data_entry(2, 3), |
| 40 | }; | 40 | }; |
| 41 | #endif /* ifdef CONFIG_ARCH_MX25 */ | 41 | #endif /* ifdef CONFIG_SOC_IMX25 */ |
| 42 | 42 | ||
| 43 | #ifdef CONFIG_SOC_IMX27 | 43 | #ifdef CONFIG_SOC_IMX27 |
| 44 | const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = { | 44 | const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = { |
| @@ -49,7 +49,7 @@ const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = { | |||
| 49 | }; | 49 | }; |
| 50 | #endif /* ifdef CONFIG_SOC_IMX27 */ | 50 | #endif /* ifdef CONFIG_SOC_IMX27 */ |
| 51 | 51 | ||
| 52 | #ifdef CONFIG_ARCH_MX31 | 52 | #ifdef CONFIG_SOC_IMX31 |
| 53 | const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = { | 53 | const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = { |
| 54 | #define imx31_imx_i2c_data_entry(_id, _hwid) \ | 54 | #define imx31_imx_i2c_data_entry(_id, _hwid) \ |
| 55 | imx_imx_i2c_data_entry(MX31, _id, _hwid, SZ_4K) | 55 | imx_imx_i2c_data_entry(MX31, _id, _hwid, SZ_4K) |
| @@ -57,9 +57,9 @@ const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = { | |||
| 57 | imx31_imx_i2c_data_entry(1, 2), | 57 | imx31_imx_i2c_data_entry(1, 2), |
| 58 | imx31_imx_i2c_data_entry(2, 3), | 58 | imx31_imx_i2c_data_entry(2, 3), |
| 59 | }; | 59 | }; |
| 60 | #endif /* ifdef CONFIG_ARCH_MX31 */ | 60 | #endif /* ifdef CONFIG_SOC_IMX31 */ |
| 61 | 61 | ||
| 62 | #ifdef CONFIG_ARCH_MX35 | 62 | #ifdef CONFIG_SOC_IMX35 |
| 63 | const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = { | 63 | const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = { |
| 64 | #define imx35_imx_i2c_data_entry(_id, _hwid) \ | 64 | #define imx35_imx_i2c_data_entry(_id, _hwid) \ |
| 65 | imx_imx_i2c_data_entry(MX35, _id, _hwid, SZ_4K) | 65 | imx_imx_i2c_data_entry(MX35, _id, _hwid, SZ_4K) |
| @@ -67,16 +67,16 @@ const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = { | |||
| 67 | imx35_imx_i2c_data_entry(1, 2), | 67 | imx35_imx_i2c_data_entry(1, 2), |
| 68 | imx35_imx_i2c_data_entry(2, 3), | 68 | imx35_imx_i2c_data_entry(2, 3), |
| 69 | }; | 69 | }; |
| 70 | #endif /* ifdef CONFIG_ARCH_MX35 */ | 70 | #endif /* ifdef CONFIG_SOC_IMX35 */ |
| 71 | 71 | ||
| 72 | #ifdef CONFIG_ARCH_MX51 | 72 | #ifdef CONFIG_SOC_IMX51 |
| 73 | const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = { | 73 | const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = { |
| 74 | #define imx51_imx_i2c_data_entry(_id, _hwid) \ | 74 | #define imx51_imx_i2c_data_entry(_id, _hwid) \ |
| 75 | imx_imx_i2c_data_entry(MX51, _id, _hwid, SZ_4K) | 75 | imx_imx_i2c_data_entry(MX51, _id, _hwid, SZ_4K) |
| 76 | imx51_imx_i2c_data_entry(0, 1), | 76 | imx51_imx_i2c_data_entry(0, 1), |
| 77 | imx51_imx_i2c_data_entry(1, 2), | 77 | imx51_imx_i2c_data_entry(1, 2), |
| 78 | }; | 78 | }; |
| 79 | #endif /* ifdef CONFIG_ARCH_MX51 */ | 79 | #endif /* ifdef CONFIG_SOC_IMX51 */ |
| 80 | 80 | ||
| 81 | struct platform_device *__init imx_add_imx_i2c( | 81 | struct platform_device *__init imx_add_imx_i2c( |
| 82 | const struct imx_imx_i2c_data *data, | 82 | const struct imx_imx_i2c_data *data, |
diff --git a/arch/arm/plat-mxc/devices/platform-imx-keypad.c b/arch/arm/plat-mxc/devices/platform-imx-keypad.c new file mode 100644 index 000000000000..40238f0b8643 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-keypad.c | |||
| @@ -0,0 +1,62 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <mach/hardware.h> | ||
| 10 | #include <mach/devices-common.h> | ||
| 11 | |||
| 12 | #define imx_imx_keypad_data_entry_single(soc, _size) \ | ||
| 13 | { \ | ||
| 14 | .iobase = soc ## _KPP_BASE_ADDR, \ | ||
| 15 | .iosize = _size, \ | ||
| 16 | .irq = soc ## _INT_KPP, \ | ||
| 17 | } | ||
| 18 | |||
| 19 | #ifdef CONFIG_SOC_IMX21 | ||
| 20 | const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst = | ||
| 21 | imx_imx_keypad_data_entry_single(MX21, SZ_16); | ||
| 22 | #endif /* ifdef CONFIG_SOC_IMX21 */ | ||
| 23 | |||
| 24 | #ifdef CONFIG_SOC_IMX25 | ||
| 25 | const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst = | ||
| 26 | imx_imx_keypad_data_entry_single(MX25, SZ_16K); | ||
| 27 | #endif /* ifdef CONFIG_SOC_IMX25 */ | ||
| 28 | |||
| 29 | #ifdef CONFIG_SOC_IMX27 | ||
| 30 | const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst = | ||
| 31 | imx_imx_keypad_data_entry_single(MX27, SZ_16); | ||
| 32 | #endif /* ifdef CONFIG_SOC_IMX27 */ | ||
| 33 | |||
| 34 | #ifdef CONFIG_SOC_IMX31 | ||
| 35 | const struct imx_imx_keypad_data imx31_imx_keypad_data __initconst = | ||
| 36 | imx_imx_keypad_data_entry_single(MX31, SZ_16); | ||
| 37 | #endif /* ifdef CONFIG_SOC_IMX31 */ | ||
| 38 | |||
| 39 | #ifdef CONFIG_SOC_IMX35 | ||
| 40 | const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst = | ||
| 41 | imx_imx_keypad_data_entry_single(MX35, SZ_16); | ||
| 42 | #endif /* ifdef CONFIG_SOC_IMX35 */ | ||
| 43 | |||
| 44 | struct platform_device *__init imx_add_imx_keypad( | ||
| 45 | const struct imx_imx_keypad_data *data, | ||
| 46 | const struct matrix_keymap_data *pdata) | ||
| 47 | { | ||
| 48 | struct resource res[] = { | ||
| 49 | { | ||
| 50 | .start = data->iobase, | ||
| 51 | .end = data->iobase + data->iosize - 1, | ||
| 52 | .flags = IORESOURCE_MEM, | ||
| 53 | }, { | ||
| 54 | .start = data->irq, | ||
| 55 | .end = data->irq, | ||
| 56 | .flags = IORESOURCE_IRQ, | ||
| 57 | }, | ||
| 58 | }; | ||
| 59 | |||
| 60 | return imx_add_platform_device("imx-keypad", -1, | ||
| 61 | res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); | ||
| 62 | } | ||
diff --git a/arch/arm/plat-mxc/devices/platform-imx-ssi.c b/arch/arm/plat-mxc/devices/platform-imx-ssi.c index 38a7a0b8f2f1..2569c8d8a2ef 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-ssi.c +++ b/arch/arm/plat-mxc/devices/platform-imx-ssi.c | |||
| @@ -30,14 +30,14 @@ const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst = { | |||
| 30 | }; | 30 | }; |
| 31 | #endif /* ifdef CONFIG_SOC_IMX21 */ | 31 | #endif /* ifdef CONFIG_SOC_IMX21 */ |
| 32 | 32 | ||
| 33 | #ifdef CONFIG_ARCH_MX25 | 33 | #ifdef CONFIG_SOC_IMX25 |
| 34 | const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst = { | 34 | const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst = { |
| 35 | #define imx25_imx_ssi_data_entry(_id, _hwid) \ | 35 | #define imx25_imx_ssi_data_entry(_id, _hwid) \ |
| 36 | imx_imx_ssi_data_entry(MX25, _id, _hwid, SZ_4K) | 36 | imx_imx_ssi_data_entry(MX25, _id, _hwid, SZ_4K) |
| 37 | imx25_imx_ssi_data_entry(0, 1), | 37 | imx25_imx_ssi_data_entry(0, 1), |
| 38 | imx25_imx_ssi_data_entry(1, 2), | 38 | imx25_imx_ssi_data_entry(1, 2), |
| 39 | }; | 39 | }; |
| 40 | #endif /* ifdef CONFIG_ARCH_MX25 */ | 40 | #endif /* ifdef CONFIG_SOC_IMX25 */ |
| 41 | 41 | ||
| 42 | #ifdef CONFIG_SOC_IMX27 | 42 | #ifdef CONFIG_SOC_IMX27 |
| 43 | const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = { | 43 | const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = { |
| @@ -48,32 +48,33 @@ const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = { | |||
| 48 | }; | 48 | }; |
| 49 | #endif /* ifdef CONFIG_SOC_IMX27 */ | 49 | #endif /* ifdef CONFIG_SOC_IMX27 */ |
| 50 | 50 | ||
| 51 | #ifdef CONFIG_ARCH_MX31 | 51 | #ifdef CONFIG_SOC_IMX31 |
| 52 | const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst = { | 52 | const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst = { |
| 53 | #define imx31_imx_ssi_data_entry(_id, _hwid) \ | 53 | #define imx31_imx_ssi_data_entry(_id, _hwid) \ |
| 54 | imx_imx_ssi_data_entry(MX31, _id, _hwid, SZ_4K) | 54 | imx_imx_ssi_data_entry(MX31, _id, _hwid, SZ_4K) |
| 55 | imx31_imx_ssi_data_entry(0, 1), | 55 | imx31_imx_ssi_data_entry(0, 1), |
| 56 | imx31_imx_ssi_data_entry(1, 2), | 56 | imx31_imx_ssi_data_entry(1, 2), |
| 57 | }; | 57 | }; |
| 58 | #endif /* ifdef CONFIG_ARCH_MX31 */ | 58 | #endif /* ifdef CONFIG_SOC_IMX31 */ |
| 59 | 59 | ||
| 60 | #ifdef CONFIG_ARCH_MX35 | 60 | #ifdef CONFIG_SOC_IMX35 |
| 61 | const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = { | 61 | const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = { |
| 62 | #define imx35_imx_ssi_data_entry(_id, _hwid) \ | 62 | #define imx35_imx_ssi_data_entry(_id, _hwid) \ |
| 63 | imx_imx_ssi_data_entry(MX35, _id, _hwid, SZ_4K) | 63 | imx_imx_ssi_data_entry(MX35, _id, _hwid, SZ_4K) |
| 64 | imx35_imx_ssi_data_entry(0, 1), | 64 | imx35_imx_ssi_data_entry(0, 1), |
| 65 | imx35_imx_ssi_data_entry(1, 2), | 65 | imx35_imx_ssi_data_entry(1, 2), |
| 66 | }; | 66 | }; |
| 67 | #endif /* ifdef CONFIG_ARCH_MX35 */ | 67 | #endif /* ifdef CONFIG_SOC_IMX35 */ |
| 68 | 68 | ||
| 69 | #ifdef CONFIG_ARCH_MX51 | 69 | #ifdef CONFIG_SOC_IMX51 |
| 70 | const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = { | 70 | const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = { |
| 71 | #define imx51_imx_ssi_data_entry(_id, _hwid) \ | 71 | #define imx51_imx_ssi_data_entry(_id, _hwid) \ |
| 72 | imx_imx_ssi_data_entry(MX51, _id, _hwid, SZ_4K) | 72 | imx_imx_ssi_data_entry(MX51, _id, _hwid, SZ_4K) |
| 73 | imx51_imx_ssi_data_entry(0, 1), | 73 | imx51_imx_ssi_data_entry(0, 1), |
| 74 | imx51_imx_ssi_data_entry(1, 2), | 74 | imx51_imx_ssi_data_entry(1, 2), |
| 75 | imx51_imx_ssi_data_entry(2, 3), | ||
| 75 | }; | 76 | }; |
| 76 | #endif /* ifdef CONFIG_ARCH_MX51 */ | 77 | #endif /* ifdef CONFIG_SOC_IMX51 */ |
| 77 | 78 | ||
| 78 | struct platform_device *__init imx_add_imx_ssi( | 79 | struct platform_device *__init imx_add_imx_ssi( |
| 79 | const struct imx_imx_ssi_data *data, | 80 | const struct imx_imx_ssi_data *data, |
diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c index 2039640adf27..3c854c2cc6dd 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-uart.c +++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c | |||
| @@ -47,7 +47,7 @@ const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = { | |||
| 47 | }; | 47 | }; |
| 48 | #endif | 48 | #endif |
| 49 | 49 | ||
| 50 | #ifdef CONFIG_ARCH_MX25 | 50 | #ifdef CONFIG_SOC_IMX25 |
| 51 | const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = { | 51 | const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = { |
| 52 | #define imx25_imx_uart_data_entry(_id, _hwid) \ | 52 | #define imx25_imx_uart_data_entry(_id, _hwid) \ |
| 53 | imx_imx_uart_1irq_data_entry(MX25, _id, _hwid, SZ_16K) | 53 | imx_imx_uart_1irq_data_entry(MX25, _id, _hwid, SZ_16K) |
| @@ -57,7 +57,7 @@ const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = { | |||
| 57 | imx25_imx_uart_data_entry(3, 4), | 57 | imx25_imx_uart_data_entry(3, 4), |
| 58 | imx25_imx_uart_data_entry(4, 5), | 58 | imx25_imx_uart_data_entry(4, 5), |
| 59 | }; | 59 | }; |
| 60 | #endif /* ifdef CONFIG_ARCH_MX25 */ | 60 | #endif /* ifdef CONFIG_SOC_IMX25 */ |
| 61 | 61 | ||
| 62 | #ifdef CONFIG_SOC_IMX27 | 62 | #ifdef CONFIG_SOC_IMX27 |
| 63 | const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = { | 63 | const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = { |
| @@ -72,7 +72,7 @@ const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = { | |||
| 72 | }; | 72 | }; |
| 73 | #endif /* ifdef CONFIG_SOC_IMX27 */ | 73 | #endif /* ifdef CONFIG_SOC_IMX27 */ |
| 74 | 74 | ||
| 75 | #ifdef CONFIG_ARCH_MX31 | 75 | #ifdef CONFIG_SOC_IMX31 |
| 76 | const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = { | 76 | const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = { |
| 77 | #define imx31_imx_uart_data_entry(_id, _hwid) \ | 77 | #define imx31_imx_uart_data_entry(_id, _hwid) \ |
| 78 | imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_4K) | 78 | imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_4K) |
| @@ -82,9 +82,9 @@ const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = { | |||
| 82 | imx31_imx_uart_data_entry(3, 4), | 82 | imx31_imx_uart_data_entry(3, 4), |
| 83 | imx31_imx_uart_data_entry(4, 5), | 83 | imx31_imx_uart_data_entry(4, 5), |
| 84 | }; | 84 | }; |
| 85 | #endif /* ifdef CONFIG_ARCH_MX31 */ | 85 | #endif /* ifdef CONFIG_SOC_IMX31 */ |
| 86 | 86 | ||
| 87 | #ifdef CONFIG_ARCH_MX35 | 87 | #ifdef CONFIG_SOC_IMX35 |
| 88 | const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = { | 88 | const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = { |
| 89 | #define imx35_imx_uart_data_entry(_id, _hwid) \ | 89 | #define imx35_imx_uart_data_entry(_id, _hwid) \ |
| 90 | imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_16K) | 90 | imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_16K) |
| @@ -92,9 +92,21 @@ const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = { | |||
| 92 | imx35_imx_uart_data_entry(1, 2), | 92 | imx35_imx_uart_data_entry(1, 2), |
| 93 | imx35_imx_uart_data_entry(2, 3), | 93 | imx35_imx_uart_data_entry(2, 3), |
| 94 | }; | 94 | }; |
| 95 | #endif /* ifdef CONFIG_ARCH_MX35 */ | 95 | #endif /* ifdef CONFIG_SOC_IMX35 */ |
| 96 | 96 | ||
| 97 | #ifdef CONFIG_ARCH_MX51 | 97 | #ifdef CONFIG_SOC_IMX50 |
| 98 | const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst = { | ||
| 99 | #define imx50_imx_uart_data_entry(_id, _hwid) \ | ||
| 100 | imx_imx_uart_1irq_data_entry(MX50, _id, _hwid, SZ_4K) | ||
| 101 | imx50_imx_uart_data_entry(0, 1), | ||
| 102 | imx50_imx_uart_data_entry(1, 2), | ||
| 103 | imx50_imx_uart_data_entry(2, 3), | ||
| 104 | imx50_imx_uart_data_entry(3, 4), | ||
| 105 | imx50_imx_uart_data_entry(4, 5), | ||
| 106 | }; | ||
| 107 | #endif /* ifdef CONFIG_SOC_IMX50 */ | ||
| 108 | |||
| 109 | #ifdef CONFIG_SOC_IMX51 | ||
| 98 | const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = { | 110 | const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = { |
| 99 | #define imx51_imx_uart_data_entry(_id, _hwid) \ | 111 | #define imx51_imx_uart_data_entry(_id, _hwid) \ |
| 100 | imx_imx_uart_1irq_data_entry(MX51, _id, _hwid, SZ_4K) | 112 | imx_imx_uart_1irq_data_entry(MX51, _id, _hwid, SZ_4K) |
| @@ -102,7 +114,17 @@ const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = { | |||
| 102 | imx51_imx_uart_data_entry(1, 2), | 114 | imx51_imx_uart_data_entry(1, 2), |
| 103 | imx51_imx_uart_data_entry(2, 3), | 115 | imx51_imx_uart_data_entry(2, 3), |
| 104 | }; | 116 | }; |
| 105 | #endif /* ifdef CONFIG_ARCH_MX51 */ | 117 | #endif /* ifdef CONFIG_SOC_IMX51 */ |
| 118 | |||
| 119 | #ifdef CONFIG_SOC_IMX53 | ||
| 120 | const struct imx_imx_uart_1irq_data imx53_imx_uart_data[] __initconst = { | ||
| 121 | #define imx53_imx_uart_data_entry(_id, _hwid) \ | ||
| 122 | imx_imx_uart_1irq_data_entry(MX53, _id, _hwid, SZ_4K) | ||
| 123 | imx53_imx_uart_data_entry(0, 1), | ||
| 124 | imx53_imx_uart_data_entry(1, 2), | ||
| 125 | imx53_imx_uart_data_entry(2, 3), | ||
| 126 | }; | ||
| 127 | #endif /* ifdef CONFIG_SOC_IMX53 */ | ||
| 106 | 128 | ||
| 107 | struct platform_device *__init imx_add_imx_uart_3irq( | 129 | struct platform_device *__init imx_add_imx_uart_3irq( |
| 108 | const struct imx_imx_uart_3irq_data *data, | 130 | const struct imx_imx_uart_3irq_data *data, |
diff --git a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c new file mode 100644 index 000000000000..e0aec61177f4 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c | |||
| @@ -0,0 +1,68 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <asm/sizes.h> | ||
| 10 | #include <mach/hardware.h> | ||
| 11 | #include <mach/devices-common.h> | ||
| 12 | |||
| 13 | #define imx_imx2_wdt_data_entry_single(soc, _id, _hwid, _size) \ | ||
| 14 | { \ | ||
| 15 | .id = _id, \ | ||
| 16 | .iobase = soc ## _WDOG ## _hwid ## _BASE_ADDR, \ | ||
| 17 | .iosize = _size, \ | ||
| 18 | } | ||
| 19 | #define imx_imx2_wdt_data_entry(soc, _id, _hwid, _size) \ | ||
| 20 | [_id] = imx_imx2_wdt_data_entry_single(soc, _id, _hwid, _size) | ||
| 21 | |||
| 22 | #ifdef CONFIG_SOC_IMX21 | ||
| 23 | const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst = | ||
| 24 | imx_imx2_wdt_data_entry_single(MX21, 0, , SZ_4K); | ||
| 25 | #endif /* ifdef CONFIG_SOC_IMX21 */ | ||
| 26 | |||
| 27 | #ifdef CONFIG_SOC_IMX25 | ||
| 28 | const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst = | ||
| 29 | imx_imx2_wdt_data_entry_single(MX25, 0, , SZ_16K); | ||
| 30 | #endif /* ifdef CONFIG_SOC_IMX25 */ | ||
| 31 | |||
| 32 | #ifdef CONFIG_SOC_IMX27 | ||
| 33 | const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst = | ||
| 34 | imx_imx2_wdt_data_entry_single(MX27, 0, , SZ_4K); | ||
| 35 | #endif /* ifdef CONFIG_SOC_IMX27 */ | ||
| 36 | |||
| 37 | #ifdef CONFIG_SOC_IMX31 | ||
| 38 | const struct imx_imx2_wdt_data imx31_imx2_wdt_data __initconst = | ||
| 39 | imx_imx2_wdt_data_entry_single(MX31, 0, , SZ_16K); | ||
| 40 | #endif /* ifdef CONFIG_SOC_IMX31 */ | ||
| 41 | |||
| 42 | #ifdef CONFIG_SOC_IMX35 | ||
| 43 | const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst = | ||
| 44 | imx_imx2_wdt_data_entry_single(MX35, 0, , SZ_16K); | ||
| 45 | #endif /* ifdef CONFIG_SOC_IMX35 */ | ||
| 46 | |||
| 47 | #ifdef CONFIG_SOC_IMX51 | ||
| 48 | const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst = { | ||
| 49 | #define imx51_imx2_wdt_data_entry(_id, _hwid) \ | ||
| 50 | imx_imx2_wdt_data_entry(MX51, _id, _hwid, SZ_16K) | ||
| 51 | imx51_imx2_wdt_data_entry(0, 1), | ||
| 52 | imx51_imx2_wdt_data_entry(1, 2), | ||
| 53 | }; | ||
| 54 | #endif /* ifdef CONFIG_SOC_IMX51 */ | ||
| 55 | |||
| 56 | struct platform_device *__init imx_add_imx2_wdt( | ||
| 57 | const struct imx_imx2_wdt_data *data) | ||
| 58 | { | ||
| 59 | struct resource res[] = { | ||
| 60 | { | ||
| 61 | .start = data->iobase, | ||
| 62 | .end = data->iobase + data->iosize - 1, | ||
| 63 | .flags = IORESOURCE_MEM, | ||
| 64 | }, | ||
| 65 | }; | ||
| 66 | return imx_add_platform_device("imx2-wdt", data->id, | ||
| 67 | res, ARRAY_SIZE(res), NULL, 0); | ||
| 68 | } | ||
diff --git a/arch/arm/plat-mxc/devices/platform-imx21-hcd.c b/arch/arm/plat-mxc/devices/platform-imx21-hcd.c new file mode 100644 index 000000000000..5770a42f33bf --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx21-hcd.c | |||
| @@ -0,0 +1,41 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <mach/hardware.h> | ||
| 10 | #include <mach/devices-common.h> | ||
| 11 | |||
| 12 | #define imx_imx21_hcd_data_entry_single(soc) \ | ||
| 13 | { \ | ||
| 14 | .iobase = soc ## _USBOTG_BASE_ADDR, \ | ||
| 15 | .irq = soc ## _INT_USBHOST, \ | ||
| 16 | } | ||
| 17 | |||
| 18 | #ifdef CONFIG_SOC_IMX21 | ||
| 19 | const struct imx_imx21_hcd_data imx21_imx21_hcd_data __initconst = | ||
| 20 | imx_imx21_hcd_data_entry_single(MX21); | ||
| 21 | #endif /* ifdef CONFIG_SOC_IMX21 */ | ||
| 22 | |||
| 23 | struct platform_device *__init imx_add_imx21_hcd( | ||
| 24 | const struct imx_imx21_hcd_data *data, | ||
| 25 | const struct mx21_usbh_platform_data *pdata) | ||
| 26 | { | ||
| 27 | struct resource res[] = { | ||
| 28 | { | ||
| 29 | .start = data->iobase, | ||
| 30 | .end = data->iobase + SZ_8K - 1, | ||
| 31 | .flags = IORESOURCE_MEM, | ||
| 32 | }, { | ||
| 33 | .start = data->irq, | ||
| 34 | .end = data->irq, | ||
| 35 | .flags = IORESOURCE_IRQ, | ||
| 36 | }, | ||
| 37 | }; | ||
| 38 | return imx_add_platform_device_dmamask("imx21-hcd", 0, | ||
| 39 | res, ARRAY_SIZE(res), | ||
| 40 | pdata, sizeof(*pdata), DMA_BIT_MASK(32)); | ||
| 41 | } | ||
diff --git a/arch/arm/plat-mxc/devices/platform-imx_udc.c b/arch/arm/plat-mxc/devices/platform-imx_udc.c new file mode 100644 index 000000000000..6fd675dfce14 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx_udc.c | |||
| @@ -0,0 +1,75 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <mach/hardware.h> | ||
| 10 | #include <mach/devices-common.h> | ||
| 11 | |||
| 12 | #define imx_imx_udc_data_entry_single(soc, _size) \ | ||
| 13 | { \ | ||
| 14 | .iobase = soc ## _USBD_BASE_ADDR, \ | ||
| 15 | .iosize = _size, \ | ||
| 16 | .irq0 = soc ## _INT_USBD0, \ | ||
| 17 | .irq1 = soc ## _INT_USBD1, \ | ||
| 18 | .irq2 = soc ## _INT_USBD2, \ | ||
| 19 | .irq3 = soc ## _INT_USBD3, \ | ||
| 20 | .irq4 = soc ## _INT_USBD4, \ | ||
| 21 | .irq5 = soc ## _INT_USBD5, \ | ||
| 22 | .irq6 = soc ## _INT_USBD6, \ | ||
| 23 | } | ||
| 24 | |||
| 25 | #define imx_imx_udc_data_entry(soc, _size) \ | ||
| 26 | [_id] = imx_imx_udc_data_entry_single(soc, _size) | ||
| 27 | |||
| 28 | #ifdef CONFIG_SOC_IMX1 | ||
| 29 | const struct imx_imx_udc_data imx1_imx_udc_data __initconst = | ||
| 30 | imx_imx_udc_data_entry_single(MX1, SZ_4K); | ||
| 31 | #endif /* ifdef CONFIG_SOC_IMX1 */ | ||
| 32 | |||
| 33 | struct platform_device *__init imx_add_imx_udc( | ||
| 34 | const struct imx_imx_udc_data *data, | ||
| 35 | const struct imxusb_platform_data *pdata) | ||
| 36 | { | ||
| 37 | struct resource res[] = { | ||
| 38 | { | ||
| 39 | .start = data->iobase, | ||
| 40 | .end = data->iobase + data->iosize - 1, | ||
| 41 | .flags = IORESOURCE_MEM, | ||
| 42 | }, { | ||
| 43 | .start = data->irq0, | ||
| 44 | .end = data->irq0, | ||
| 45 | .flags = IORESOURCE_IRQ, | ||
| 46 | }, { | ||
| 47 | .start = data->irq1, | ||
| 48 | .end = data->irq1, | ||
| 49 | .flags = IORESOURCE_IRQ, | ||
| 50 | }, { | ||
| 51 | .start = data->irq2, | ||
| 52 | .end = data->irq2, | ||
| 53 | .flags = IORESOURCE_IRQ, | ||
| 54 | }, { | ||
| 55 | .start = data->irq3, | ||
| 56 | .end = data->irq3, | ||
| 57 | .flags = IORESOURCE_IRQ, | ||
| 58 | }, { | ||
| 59 | .start = data->irq4, | ||
| 60 | .end = data->irq4, | ||
| 61 | .flags = IORESOURCE_IRQ, | ||
| 62 | }, { | ||
| 63 | .start = data->irq5, | ||
| 64 | .end = data->irq5, | ||
| 65 | .flags = IORESOURCE_IRQ, | ||
| 66 | }, { | ||
| 67 | .start = data->irq6, | ||
| 68 | .end = data->irq6, | ||
| 69 | .flags = IORESOURCE_IRQ, | ||
| 70 | }, | ||
| 71 | }; | ||
| 72 | |||
| 73 | return imx_add_platform_device("imx_udc", 0, | ||
| 74 | res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); | ||
| 75 | } | ||
diff --git a/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c new file mode 100644 index 000000000000..10653cc8d1fa --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c | |||
| @@ -0,0 +1,41 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <asm/sizes.h> | ||
| 10 | #include <mach/hardware.h> | ||
| 11 | #include <mach/devices-common.h> | ||
| 12 | |||
| 13 | #define imx_imxdi_rtc_data_entry_single(soc) \ | ||
| 14 | { \ | ||
| 15 | .iobase = soc ## _DRYICE_BASE_ADDR, \ | ||
| 16 | .irq = soc ## _INT_DRYICE, \ | ||
| 17 | } | ||
| 18 | |||
| 19 | #ifdef CONFIG_SOC_IMX25 | ||
| 20 | const struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst = | ||
| 21 | imx_imxdi_rtc_data_entry_single(MX25); | ||
| 22 | #endif /* ifdef CONFIG_SOC_IMX25 */ | ||
| 23 | |||
| 24 | struct platform_device *__init imx_add_imxdi_rtc( | ||
| 25 | const struct imx_imxdi_rtc_data *data) | ||
| 26 | { | ||
| 27 | struct resource res[] = { | ||
| 28 | { | ||
| 29 | .start = data->iobase, | ||
| 30 | .end = data->iobase + SZ_16K, | ||
| 31 | .flags = IORESOURCE_MEM, | ||
| 32 | }, { | ||
| 33 | .start = data->irq, | ||
| 34 | .end = data->irq, | ||
| 35 | .flags = IORESOURCE_IRQ, | ||
| 36 | }, | ||
| 37 | }; | ||
| 38 | |||
| 39 | return imx_add_platform_device("imxdi_rtc", 0, | ||
| 40 | res, ARRAY_SIZE(res), NULL, 0); | ||
| 41 | } | ||
diff --git a/arch/arm/plat-mxc/devices/platform-mx1-camera.c b/arch/arm/plat-mxc/devices/platform-mx1-camera.c new file mode 100644 index 000000000000..edcc581a30a9 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mx1-camera.c | |||
| @@ -0,0 +1,42 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <mach/hardware.h> | ||
| 10 | #include <mach/devices-common.h> | ||
| 11 | |||
| 12 | #define imx_mx1_camera_data_entry_single(soc, _size) \ | ||
| 13 | { \ | ||
| 14 | .iobase = soc ## _CSI ## _BASE_ADDR, \ | ||
| 15 | .iosize = _size, \ | ||
| 16 | .irq = soc ## _INT_CSI, \ | ||
| 17 | } | ||
| 18 | |||
| 19 | #ifdef CONFIG_SOC_IMX1 | ||
| 20 | const struct imx_mx1_camera_data imx1_mx1_camera_data __initconst = | ||
| 21 | imx_mx1_camera_data_entry_single(MX1, 10); | ||
| 22 | #endif /* ifdef CONFIG_SOC_IMX1 */ | ||
| 23 | |||
| 24 | struct platform_device *__init imx_add_mx1_camera( | ||
| 25 | const struct imx_mx1_camera_data *data, | ||
| 26 | const struct mx1_camera_pdata *pdata) | ||
| 27 | { | ||
| 28 | struct resource res[] = { | ||
| 29 | { | ||
| 30 | .start = data->iobase, | ||
| 31 | .end = data->iobase + data->iosize - 1, | ||
| 32 | .flags = IORESOURCE_MEM, | ||
| 33 | }, { | ||
| 34 | .start = data->irq, | ||
| 35 | .end = data->irq, | ||
| 36 | .flags = IORESOURCE_IRQ, | ||
| 37 | }, | ||
| 38 | }; | ||
| 39 | return imx_add_platform_device_dmamask("mx1-camera", 0, | ||
| 40 | res, ARRAY_SIZE(res), | ||
| 41 | pdata, sizeof(*pdata), DMA_BIT_MASK(32)); | ||
| 42 | } | ||
diff --git a/arch/arm/plat-mxc/devices/platform-mx2-camera.c b/arch/arm/plat-mxc/devices/platform-mx2-camera.c new file mode 100644 index 000000000000..b3f4828dc447 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mx2-camera.c | |||
| @@ -0,0 +1,64 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <mach/hardware.h> | ||
| 10 | #include <mach/devices-common.h> | ||
| 11 | |||
| 12 | #define imx_mx2_camera_data_entry_single(soc) \ | ||
| 13 | { \ | ||
| 14 | .iobasecsi = soc ## _CSI_BASE_ADDR, \ | ||
| 15 | .iosizecsi = SZ_4K, \ | ||
| 16 | .irqcsi = soc ## _INT_CSI, \ | ||
| 17 | } | ||
| 18 | #define imx_mx2_camera_data_entry_single_emma(soc) \ | ||
| 19 | { \ | ||
| 20 | .iobasecsi = soc ## _CSI_BASE_ADDR, \ | ||
| 21 | .iosizecsi = SZ_32, \ | ||
| 22 | .irqcsi = soc ## _INT_CSI, \ | ||
| 23 | .iobaseemmaprp = soc ## _EMMAPRP_BASE_ADDR, \ | ||
| 24 | .iosizeemmaprp = SZ_32, \ | ||
| 25 | .irqemmaprp = soc ## _INT_EMMAPRP, \ | ||
| 26 | } | ||
| 27 | |||
| 28 | #ifdef CONFIG_SOC_IMX25 | ||
| 29 | const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst = | ||
| 30 | imx_mx2_camera_data_entry_single(MX25); | ||
| 31 | #endif /* ifdef CONFIG_SOC_IMX25 */ | ||
| 32 | |||
| 33 | #ifdef CONFIG_SOC_IMX27 | ||
| 34 | const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst = | ||
| 35 | imx_mx2_camera_data_entry_single_emma(MX27); | ||
| 36 | #endif /* ifdef CONFIG_SOC_IMX27 */ | ||
| 37 | |||
| 38 | struct platform_device *__init imx_add_mx2_camera( | ||
| 39 | const struct imx_mx2_camera_data *data, | ||
| 40 | const struct mx2_camera_platform_data *pdata) | ||
| 41 | { | ||
| 42 | struct resource res[] = { | ||
| 43 | { | ||
| 44 | .start = data->iobasecsi, | ||
| 45 | .end = data->iobasecsi + data->iosizecsi - 1, | ||
| 46 | .flags = IORESOURCE_MEM, | ||
| 47 | }, { | ||
| 48 | .start = data->irqcsi, | ||
| 49 | .end = data->irqcsi, | ||
| 50 | .flags = IORESOURCE_IRQ, | ||
| 51 | }, { | ||
| 52 | .start = data->iobaseemmaprp, | ||
| 53 | .end = data->iobaseemmaprp + data->iosizeemmaprp - 1, | ||
| 54 | .flags = IORESOURCE_MEM, | ||
| 55 | }, { | ||
| 56 | .start = data->irqemmaprp, | ||
| 57 | .end = data->irqemmaprp, | ||
| 58 | .flags = IORESOURCE_IRQ, | ||
| 59 | }, | ||
| 60 | }; | ||
| 61 | return imx_add_platform_device_dmamask("mx2-camera", 0, | ||
| 62 | res, data->iobaseemmaprp ? 4 : 2, | ||
| 63 | pdata, sizeof(*pdata), DMA_BIT_MASK(32)); | ||
| 64 | } | ||
diff --git a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c new file mode 100644 index 000000000000..cc488f4b6204 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c | |||
| @@ -0,0 +1,69 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <mach/hardware.h> | ||
| 10 | #include <mach/devices-common.h> | ||
| 11 | |||
| 12 | #define imx_mxc_ehci_data_entry_single(soc, _id, hs) \ | ||
| 13 | { \ | ||
| 14 | .id = _id, \ | ||
| 15 | .iobase = soc ## _USB_ ## hs ## _BASE_ADDR, \ | ||
| 16 | .irq = soc ## _INT_USB_ ## hs, \ | ||
| 17 | } | ||
| 18 | |||
| 19 | #ifdef CONFIG_SOC_IMX25 | ||
| 20 | const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst = | ||
| 21 | imx_mxc_ehci_data_entry_single(MX25, 0, OTG); | ||
| 22 | const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst = | ||
| 23 | imx_mxc_ehci_data_entry_single(MX25, 1, HS); | ||
| 24 | #endif /* ifdef CONFIG_SOC_IMX25 */ | ||
| 25 | |||
| 26 | #ifdef CONFIG_SOC_IMX27 | ||
| 27 | const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst = | ||
| 28 | imx_mxc_ehci_data_entry_single(MX27, 0, OTG); | ||
| 29 | const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[] __initconst = { | ||
| 30 | imx_mxc_ehci_data_entry_single(MX27, 1, HS1), | ||
| 31 | imx_mxc_ehci_data_entry_single(MX27, 2, HS2), | ||
| 32 | }; | ||
| 33 | #endif /* ifdef CONFIG_SOC_IMX27 */ | ||
| 34 | |||
| 35 | #ifdef CONFIG_SOC_IMX31 | ||
| 36 | const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data __initconst = | ||
| 37 | imx_mxc_ehci_data_entry_single(MX31, 0, OTG); | ||
| 38 | const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[] __initconst = { | ||
| 39 | imx_mxc_ehci_data_entry_single(MX31, 1, HS1), | ||
| 40 | imx_mxc_ehci_data_entry_single(MX31, 2, HS2), | ||
| 41 | }; | ||
| 42 | #endif /* ifdef CONFIG_SOC_IMX31 */ | ||
| 43 | |||
| 44 | #ifdef CONFIG_SOC_IMX35 | ||
| 45 | const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data __initconst = | ||
| 46 | imx_mxc_ehci_data_entry_single(MX35, 0, OTG); | ||
| 47 | const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst = | ||
| 48 | imx_mxc_ehci_data_entry_single(MX35, 1, HS); | ||
| 49 | #endif /* ifdef CONFIG_SOC_IMX35 */ | ||
| 50 | |||
| 51 | struct platform_device *__init imx_add_mxc_ehci( | ||
| 52 | const struct imx_mxc_ehci_data *data, | ||
| 53 | const struct mxc_usbh_platform_data *pdata) | ||
| 54 | { | ||
| 55 | struct resource res[] = { | ||
| 56 | { | ||
| 57 | .start = data->iobase, | ||
| 58 | .end = data->iobase + SZ_512 - 1, | ||
| 59 | .flags = IORESOURCE_MEM, | ||
| 60 | }, { | ||
| 61 | .start = data->irq, | ||
| 62 | .end = data->irq, | ||
| 63 | .flags = IORESOURCE_IRQ, | ||
| 64 | }, | ||
| 65 | }; | ||
| 66 | return imx_add_platform_device_dmamask("mxc-ehci", data->id, | ||
| 67 | res, ARRAY_SIZE(res), | ||
| 68 | pdata, sizeof(*pdata), DMA_BIT_MASK(32)); | ||
| 69 | } | ||
diff --git a/arch/arm/plat-mxc/devices/platform-mxc-mmc.c b/arch/arm/plat-mxc/devices/platform-mxc-mmc.c new file mode 100644 index 000000000000..90d762f6f93b --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc-mmc.c | |||
| @@ -0,0 +1,72 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <mach/hardware.h> | ||
| 10 | #include <mach/devices-common.h> | ||
| 11 | |||
| 12 | #define imx_mxc_mmc_data_entry_single(soc, _id, _hwid, _size) \ | ||
| 13 | { \ | ||
| 14 | .id = _id, \ | ||
| 15 | .iobase = soc ## _SDHC ## _hwid ## _BASE_ADDR, \ | ||
| 16 | .iosize = _size, \ | ||
| 17 | .irq = soc ## _INT_SDHC ## _hwid, \ | ||
| 18 | .dmareq = soc ## _DMA_REQ_SDHC ## _hwid, \ | ||
| 19 | } | ||
| 20 | #define imx_mxc_mmc_data_entry(soc, _id, _hwid, _size) \ | ||
| 21 | [_id] = imx_mxc_mmc_data_entry_single(soc, _id, _hwid, _size) | ||
| 22 | |||
| 23 | #ifdef CONFIG_SOC_IMX21 | ||
| 24 | const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst = { | ||
| 25 | #define imx21_mxc_mmc_data_entry(_id, _hwid) \ | ||
| 26 | imx_mxc_mmc_data_entry(MX21, _id, _hwid, SZ_4K) | ||
| 27 | imx21_mxc_mmc_data_entry(0, 1), | ||
| 28 | imx21_mxc_mmc_data_entry(1, 2), | ||
| 29 | }; | ||
| 30 | #endif /* ifdef CONFIG_SOC_IMX21 */ | ||
| 31 | |||
| 32 | #ifdef CONFIG_SOC_IMX27 | ||
| 33 | const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst = { | ||
| 34 | #define imx27_mxc_mmc_data_entry(_id, _hwid) \ | ||
| 35 | imx_mxc_mmc_data_entry(MX27, _id, _hwid, SZ_4K) | ||
| 36 | imx27_mxc_mmc_data_entry(0, 1), | ||
| 37 | imx27_mxc_mmc_data_entry(1, 2), | ||
| 38 | }; | ||
| 39 | #endif /* ifdef CONFIG_SOC_IMX27 */ | ||
| 40 | |||
| 41 | #ifdef CONFIG_SOC_IMX31 | ||
| 42 | const struct imx_mxc_mmc_data imx31_mxc_mmc_data[] __initconst = { | ||
| 43 | #define imx31_mxc_mmc_data_entry(_id, _hwid) \ | ||
| 44 | imx_mxc_mmc_data_entry(MX31, _id, _hwid, SZ_16K) | ||
| 45 | imx31_mxc_mmc_data_entry(0, 1), | ||
| 46 | imx31_mxc_mmc_data_entry(1, 2), | ||
| 47 | }; | ||
| 48 | #endif /* ifdef CONFIG_SOC_IMX31 */ | ||
| 49 | |||
| 50 | struct platform_device *__init imx_add_mxc_mmc( | ||
| 51 | const struct imx_mxc_mmc_data *data, | ||
| 52 | const struct imxmmc_platform_data *pdata) | ||
| 53 | { | ||
| 54 | struct resource res[] = { | ||
| 55 | { | ||
| 56 | .start = data->iobase, | ||
| 57 | .end = data->iobase + SZ_4K - 1, | ||
| 58 | .flags = IORESOURCE_MEM, | ||
| 59 | }, { | ||
| 60 | .start = data->irq, | ||
| 61 | .end = data->irq, | ||
| 62 | .flags = IORESOURCE_IRQ, | ||
| 63 | }, { | ||
| 64 | .start = data->dmareq, | ||
| 65 | .end = data->dmareq, | ||
| 66 | .flags = IORESOURCE_DMA, | ||
| 67 | }, | ||
| 68 | }; | ||
| 69 | return imx_add_platform_device_dmamask("mxc-mmc", data->id, | ||
| 70 | res, ARRAY_SIZE(res), | ||
| 71 | pdata, sizeof(*pdata), DMA_BIT_MASK(32)); | ||
| 72 | } | ||
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/plat-mxc/devices/platform-mxc_nand.c index 3fdcc32e3d67..1568f39fba8b 100644 --- a/arch/arm/plat-mxc/devices/platform-mxc_nand.c +++ b/arch/arm/plat-mxc/devices/platform-mxc_nand.c | |||
| @@ -31,27 +31,27 @@ const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst = | |||
| 31 | imx_mxc_nand_data_entry_single(MX21, SZ_4K); | 31 | imx_mxc_nand_data_entry_single(MX21, SZ_4K); |
| 32 | #endif /* ifdef CONFIG_SOC_IMX21 */ | 32 | #endif /* ifdef CONFIG_SOC_IMX21 */ |
| 33 | 33 | ||
| 34 | #ifdef CONFIG_ARCH_MX25 | 34 | #ifdef CONFIG_SOC_IMX25 |
| 35 | const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst = | 35 | const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst = |
| 36 | imx_mxc_nand_data_entry_single(MX25, SZ_8K); | 36 | imx_mxc_nand_data_entry_single(MX25, SZ_8K); |
| 37 | #endif /* ifdef CONFIG_ARCH_MX25 */ | 37 | #endif /* ifdef CONFIG_SOC_IMX25 */ |
| 38 | 38 | ||
| 39 | #ifdef CONFIG_SOC_IMX27 | 39 | #ifdef CONFIG_SOC_IMX27 |
| 40 | const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst = | 40 | const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst = |
| 41 | imx_mxc_nand_data_entry_single(MX27, SZ_4K); | 41 | imx_mxc_nand_data_entry_single(MX27, SZ_4K); |
| 42 | #endif /* ifdef CONFIG_SOC_IMX27 */ | 42 | #endif /* ifdef CONFIG_SOC_IMX27 */ |
| 43 | 43 | ||
| 44 | #ifdef CONFIG_ARCH_MX31 | 44 | #ifdef CONFIG_SOC_IMX31 |
| 45 | const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst = | 45 | const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst = |
| 46 | imx_mxc_nand_data_entry_single(MX31, SZ_4K); | 46 | imx_mxc_nand_data_entry_single(MX31, SZ_4K); |
| 47 | #endif | 47 | #endif |
| 48 | 48 | ||
| 49 | #ifdef CONFIG_ARCH_MX35 | 49 | #ifdef CONFIG_SOC_IMX35 |
| 50 | const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst = | 50 | const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst = |
| 51 | imx_mxc_nand_data_entry_single(MX35, SZ_8K); | 51 | imx_mxc_nand_data_entry_single(MX35, SZ_8K); |
| 52 | #endif | 52 | #endif |
| 53 | 53 | ||
| 54 | #ifdef CONFIG_ARCH_MX51 | 54 | #ifdef CONFIG_SOC_IMX51 |
| 55 | const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst = | 55 | const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst = |
| 56 | imx_mxc_nandv3_data_entry_single(MX51, SZ_16K); | 56 | imx_mxc_nandv3_data_entry_single(MX51, SZ_16K); |
| 57 | #endif | 57 | #endif |
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_pwm.c b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c new file mode 100644 index 000000000000..3d8ebdba38ee --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c | |||
| @@ -0,0 +1,60 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009-2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <mach/hardware.h> | ||
| 10 | #include <mach/devices-common.h> | ||
| 11 | |||
| 12 | #define imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size) \ | ||
| 13 | { \ | ||
| 14 | .id = _id, \ | ||
| 15 | .iobase = soc ## _PWM ## _hwid ## _BASE_ADDR, \ | ||
| 16 | .iosize = _size, \ | ||
| 17 | .irq = soc ## _INT_PWM ## _hwid, \ | ||
| 18 | } | ||
| 19 | #define imx_mxc_pwm_data_entry(soc, _id, _hwid, _size) \ | ||
| 20 | [_id] = imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size) | ||
| 21 | |||
| 22 | #ifdef CONFIG_SOC_IMX21 | ||
| 23 | const struct imx_mxc_pwm_data imx21_mxc_pwm_data __initconst = | ||
| 24 | imx_mxc_pwm_data_entry_single(MX21, 0, , SZ_4K); | ||
| 25 | #endif /* ifdef CONFIG_SOC_IMX21 */ | ||
| 26 | |||
| 27 | #ifdef CONFIG_SOC_IMX25 | ||
| 28 | const struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst = { | ||
| 29 | #define imx25_mxc_pwm_data_entry(_id, _hwid) \ | ||
| 30 | imx_mxc_pwm_data_entry(MX25, _id, _hwid, SZ_16K) | ||
| 31 | imx25_mxc_pwm_data_entry(0, 1), | ||
| 32 | imx25_mxc_pwm_data_entry(1, 2), | ||
| 33 | imx25_mxc_pwm_data_entry(2, 3), | ||
| 34 | imx25_mxc_pwm_data_entry(3, 4), | ||
| 35 | }; | ||
| 36 | #endif /* ifdef CONFIG_SOC_IMX25 */ | ||
| 37 | |||
| 38 | #ifdef CONFIG_SOC_IMX27 | ||
| 39 | const struct imx_mxc_pwm_data imx27_mxc_pwm_data __initconst = | ||
| 40 | imx_mxc_pwm_data_entry_single(MX27, 0, , SZ_4K); | ||
| 41 | #endif /* ifdef CONFIG_SOC_IMX27 */ | ||
| 42 | |||
| 43 | struct platform_device *__init imx_add_mxc_pwm( | ||
| 44 | const struct imx_mxc_pwm_data *data) | ||
| 45 | { | ||
| 46 | struct resource res[] = { | ||
| 47 | { | ||
| 48 | .start = data->iobase, | ||
| 49 | .end = data->iobase + data->iosize - 1, | ||
| 50 | .flags = IORESOURCE_MEM, | ||
| 51 | }, { | ||
| 52 | .start = data->irq, | ||
| 53 | .end = data->irq, | ||
| 54 | .flags = IORESOURCE_IRQ, | ||
| 55 | }, | ||
| 56 | }; | ||
| 57 | |||
| 58 | return imx_add_platform_device("mxc_pwm", data->id, | ||
| 59 | res, ARRAY_SIZE(res), NULL, 0); | ||
| 60 | } | ||
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_rnga.c b/arch/arm/plat-mxc/devices/platform-mxc_rnga.c new file mode 100644 index 000000000000..b4b7612b6e17 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_rnga.c | |||
| @@ -0,0 +1,56 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <mach/hardware.h> | ||
| 10 | #include <mach/devices-common.h> | ||
| 11 | |||
| 12 | struct imx_mxc_rnga_data { | ||
| 13 | resource_size_t iobase; | ||
| 14 | }; | ||
| 15 | |||
| 16 | #define imx_mxc_rnga_data_entry_single(soc) \ | ||
| 17 | { \ | ||
| 18 | .iobase = soc ## _RNGA_BASE_ADDR, \ | ||
| 19 | } | ||
| 20 | |||
| 21 | #ifdef CONFIG_SOC_IMX31 | ||
| 22 | static const struct imx_mxc_rnga_data imx31_mxc_rnga_data __initconst = | ||
| 23 | imx_mxc_rnga_data_entry_single(MX31); | ||
| 24 | #endif /* ifdef CONFIG_SOC_IMX31 */ | ||
| 25 | |||
| 26 | static struct platform_device *__init imx_add_mxc_rnga( | ||
| 27 | const struct imx_mxc_rnga_data *data) | ||
| 28 | { | ||
| 29 | struct resource res[] = { | ||
| 30 | { | ||
| 31 | .start = data->iobase, | ||
| 32 | .end = data->iobase + SZ_16K - 1, | ||
| 33 | .flags = IORESOURCE_MEM, | ||
| 34 | }, | ||
| 35 | }; | ||
| 36 | return imx_add_platform_device("mxc_rnga", -1, | ||
| 37 | res, ARRAY_SIZE(res), NULL, 0); | ||
| 38 | } | ||
| 39 | |||
| 40 | static int __init imxXX_add_mxc_rnga(void) | ||
| 41 | { | ||
| 42 | struct platform_device *ret; | ||
| 43 | |||
| 44 | #if defined(CONFIG_SOC_IMX31) | ||
| 45 | if (cpu_is_mx31()) | ||
| 46 | ret = imx_add_mxc_rnga(&imx31_mxc_rnga_data); | ||
| 47 | else | ||
| 48 | #endif /* if defined(CONFIG_SOC_IMX31) */ | ||
| 49 | ret = ERR_PTR(-ENODEV); | ||
| 50 | |||
| 51 | if (IS_ERR(ret)) | ||
| 52 | return PTR_ERR(ret); | ||
| 53 | |||
| 54 | return 0; | ||
| 55 | } | ||
| 56 | arch_initcall(imxXX_add_mxc_rnga); | ||
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_w1.c b/arch/arm/plat-mxc/devices/platform-mxc_w1.c new file mode 100644 index 000000000000..96fa5ea91fe8 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-mxc_w1.c | |||
| @@ -0,0 +1,50 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix | ||
| 3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify it under | ||
| 6 | * the terms of the GNU General Public License version 2 as published by the | ||
| 7 | * Free Software Foundation. | ||
| 8 | */ | ||
| 9 | #include <mach/hardware.h> | ||
| 10 | #include <mach/devices-common.h> | ||
| 11 | |||
| 12 | #define imx_mxc_w1_data_entry_single(soc) \ | ||
| 13 | { \ | ||
| 14 | .iobase = soc ## _OWIRE_BASE_ADDR, \ | ||
| 15 | } | ||
| 16 | |||
| 17 | #ifdef CONFIG_SOC_IMX21 | ||
| 18 | const struct imx_mxc_w1_data imx21_mxc_w1_data __initconst = | ||
| 19 | imx_mxc_w1_data_entry_single(MX21); | ||
| 20 | #endif /* ifdef CONFIG_SOC_IMX21 */ | ||
| 21 | |||
| 22 | #ifdef CONFIG_SOC_IMX27 | ||
| 23 | const struct imx_mxc_w1_data imx27_mxc_w1_data __initconst = | ||
| 24 | imx_mxc_w1_data_entry_single(MX27); | ||
| 25 | #endif /* ifdef CONFIG_SOC_IMX27 */ | ||
| 26 | |||
| 27 | #ifdef CONFIG_SOC_IMX31 | ||
| 28 | const struct imx_mxc_w1_data imx31_mxc_w1_data __initconst = | ||
| 29 | imx_mxc_w1_data_entry_single(MX31); | ||
| 30 | #endif /* ifdef CONFIG_SOC_IMX31 */ | ||
| 31 | |||
| 32 | #ifdef CONFIG_SOC_IMX35 | ||
| 33 | const struct imx_mxc_w1_data imx35_mxc_w1_data __initconst = | ||
| 34 | imx_mxc_w1_data_entry_single(MX35); | ||
| 35 | #endif /* ifdef CONFIG_SOC_IMX35 */ | ||
| 36 | |||
| 37 | struct platform_device *__init imx_add_mxc_w1( | ||
| 38 | const struct imx_mxc_w1_data *data) | ||
| 39 | { | ||
| 40 | struct resource res[] = { | ||
| 41 | { | ||
| 42 | .start = data->iobase, | ||
| 43 | .end = data->iobase + SZ_4K - 1, | ||
| 44 | .flags = IORESOURCE_MEM, | ||
| 45 | }, | ||
| 46 | }; | ||
| 47 | |||
| 48 | return imx_add_platform_device("mxc_w1", 0, | ||
| 49 | res, ARRAY_SIZE(res), NULL, 0); | ||
| 50 | } | ||
diff --git a/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c new file mode 100644 index 000000000000..b3525648a01d --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c | |||
| @@ -0,0 +1,74 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Pengutronix, Wolfram Sang <w.sang@pengutronix.de> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it under | ||
| 5 | * the terms of the GNU General Public License version 2 as published by the | ||
| 6 | * Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <mach/hardware.h> | ||
| 10 | #include <mach/devices-common.h> | ||
| 11 | #include <mach/esdhc.h> | ||
| 12 | |||
| 13 | #define imx_sdhci_esdhc_imx_data_entry_single(soc, _id, hwid) \ | ||
| 14 | { \ | ||
| 15 | .id = _id, \ | ||
| 16 | .iobase = soc ## _ESDHC ## hwid ## _BASE_ADDR, \ | ||
| 17 | .irq = soc ## _INT_ESDHC ## hwid, \ | ||
| 18 | } | ||
| 19 | |||
| 20 | #define imx_sdhci_esdhc_imx_data_entry(soc, id, hwid) \ | ||
| 21 | [id] = imx_sdhci_esdhc_imx_data_entry_single(soc, id, hwid) | ||
| 22 | |||
| 23 | #ifdef CONFIG_SOC_IMX25 | ||
| 24 | const struct imx_sdhci_esdhc_imx_data | ||
| 25 | imx25_sdhci_esdhc_imx_data[] __initconst = { | ||
| 26 | #define imx25_sdhci_esdhc_imx_data_entry(_id, _hwid) \ | ||
| 27 | imx_sdhci_esdhc_imx_data_entry(MX25, _id, _hwid) | ||
| 28 | imx25_sdhci_esdhc_imx_data_entry(0, 1), | ||
| 29 | imx25_sdhci_esdhc_imx_data_entry(1, 2), | ||
| 30 | }; | ||
| 31 | #endif /* ifdef CONFIG_SOC_IMX25 */ | ||
| 32 | |||
| 33 | #ifdef CONFIG_SOC_IMX35 | ||
| 34 | const struct imx_sdhci_esdhc_imx_data | ||
| 35 | imx35_sdhci_esdhc_imx_data[] __initconst = { | ||
| 36 | #define imx35_sdhci_esdhc_imx_data_entry(_id, _hwid) \ | ||
| 37 | imx_sdhci_esdhc_imx_data_entry(MX35, _id, _hwid) | ||
| 38 | imx35_sdhci_esdhc_imx_data_entry(0, 1), | ||
| 39 | imx35_sdhci_esdhc_imx_data_entry(1, 2), | ||
| 40 | imx35_sdhci_esdhc_imx_data_entry(2, 3), | ||
| 41 | }; | ||
| 42 | #endif /* ifdef CONFIG_SOC_IMX35 */ | ||
| 43 | |||
| 44 | #ifdef CONFIG_SOC_IMX51 | ||
| 45 | const struct imx_sdhci_esdhc_imx_data | ||
| 46 | imx51_sdhci_esdhc_imx_data[] __initconst = { | ||
| 47 | #define imx51_sdhci_esdhc_imx_data_entry(_id, _hwid) \ | ||
| 48 | imx_sdhci_esdhc_imx_data_entry(MX51, _id, _hwid) | ||
| 49 | imx51_sdhci_esdhc_imx_data_entry(0, 1), | ||
| 50 | imx51_sdhci_esdhc_imx_data_entry(1, 2), | ||
| 51 | imx51_sdhci_esdhc_imx_data_entry(2, 3), | ||
| 52 | imx51_sdhci_esdhc_imx_data_entry(3, 4), | ||
| 53 | }; | ||
| 54 | #endif /* ifdef CONFIG_SOC_IMX51 */ | ||
| 55 | |||
| 56 | struct platform_device *__init imx_add_sdhci_esdhc_imx( | ||
| 57 | const struct imx_sdhci_esdhc_imx_data *data, | ||
| 58 | const struct esdhc_platform_data *pdata) | ||
| 59 | { | ||
| 60 | struct resource res[] = { | ||
| 61 | { | ||
| 62 | .start = data->iobase, | ||
| 63 | .end = data->iobase + SZ_16K - 1, | ||
| 64 | .flags = IORESOURCE_MEM, | ||
| 65 | }, { | ||
| 66 | .start = data->irq, | ||
| 67 | .end = data->irq, | ||
| 68 | .flags = IORESOURCE_IRQ, | ||
| 69 | }, | ||
| 70 | }; | ||
| 71 | |||
| 72 | return imx_add_platform_device("sdhci-esdhc-imx", data->id, res, | ||
| 73 | ARRAY_SIZE(res), pdata, sizeof(*pdata)); | ||
| 74 | } | ||
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c index 17f724c9452d..8ea49adcdfc1 100644 --- a/arch/arm/plat-mxc/devices/platform-spi_imx.c +++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c | |||
| @@ -30,7 +30,7 @@ const struct imx_spi_imx_data imx21_cspi_data[] __initconst = { | |||
| 30 | }; | 30 | }; |
| 31 | #endif | 31 | #endif |
| 32 | 32 | ||
| 33 | #ifdef CONFIG_ARCH_MX25 | 33 | #ifdef CONFIG_SOC_IMX25 |
| 34 | const struct imx_spi_imx_data imx25_cspi_data[] __initconst = { | 34 | const struct imx_spi_imx_data imx25_cspi_data[] __initconst = { |
| 35 | #define imx25_cspi_data_entry(_id, _hwid) \ | 35 | #define imx25_cspi_data_entry(_id, _hwid) \ |
| 36 | imx_spi_imx_data_entry(MX25, CSPI, "imx25-cspi", _id, _hwid, SZ_16K) | 36 | imx_spi_imx_data_entry(MX25, CSPI, "imx25-cspi", _id, _hwid, SZ_16K) |
| @@ -38,7 +38,7 @@ const struct imx_spi_imx_data imx25_cspi_data[] __initconst = { | |||
| 38 | imx25_cspi_data_entry(1, 2), | 38 | imx25_cspi_data_entry(1, 2), |
| 39 | imx25_cspi_data_entry(2, 3), | 39 | imx25_cspi_data_entry(2, 3), |
| 40 | }; | 40 | }; |
| 41 | #endif /* ifdef CONFIG_ARCH_MX25 */ | 41 | #endif /* ifdef CONFIG_SOC_IMX25 */ |
| 42 | 42 | ||
| 43 | #ifdef CONFIG_SOC_IMX27 | 43 | #ifdef CONFIG_SOC_IMX27 |
| 44 | const struct imx_spi_imx_data imx27_cspi_data[] __initconst = { | 44 | const struct imx_spi_imx_data imx27_cspi_data[] __initconst = { |
| @@ -50,7 +50,7 @@ const struct imx_spi_imx_data imx27_cspi_data[] __initconst = { | |||
| 50 | }; | 50 | }; |
| 51 | #endif /* ifdef CONFIG_SOC_IMX27 */ | 51 | #endif /* ifdef CONFIG_SOC_IMX27 */ |
| 52 | 52 | ||
| 53 | #ifdef CONFIG_ARCH_MX31 | 53 | #ifdef CONFIG_SOC_IMX31 |
| 54 | const struct imx_spi_imx_data imx31_cspi_data[] __initconst = { | 54 | const struct imx_spi_imx_data imx31_cspi_data[] __initconst = { |
| 55 | #define imx31_cspi_data_entry(_id, _hwid) \ | 55 | #define imx31_cspi_data_entry(_id, _hwid) \ |
| 56 | imx_spi_imx_data_entry(MX31, CSPI, "imx31-cspi", _id, _hwid, SZ_4K) | 56 | imx_spi_imx_data_entry(MX31, CSPI, "imx31-cspi", _id, _hwid, SZ_4K) |
| @@ -58,18 +58,18 @@ const struct imx_spi_imx_data imx31_cspi_data[] __initconst = { | |||
| 58 | imx31_cspi_data_entry(1, 2), | 58 | imx31_cspi_data_entry(1, 2), |
| 59 | imx31_cspi_data_entry(2, 3), | 59 | imx31_cspi_data_entry(2, 3), |
| 60 | }; | 60 | }; |
| 61 | #endif /* ifdef CONFIG_ARCH_MX31 */ | 61 | #endif /* ifdef CONFIG_SOC_IMX31 */ |
| 62 | 62 | ||
| 63 | #ifdef CONFIG_ARCH_MX35 | 63 | #ifdef CONFIG_SOC_IMX35 |
| 64 | const struct imx_spi_imx_data imx35_cspi_data[] __initconst = { | 64 | const struct imx_spi_imx_data imx35_cspi_data[] __initconst = { |
| 65 | #define imx35_cspi_data_entry(_id, _hwid) \ | 65 | #define imx35_cspi_data_entry(_id, _hwid) \ |
| 66 | imx_spi_imx_data_entry(MX35, CSPI, "imx35-cspi", _id, _hwid, SZ_4K) | 66 | imx_spi_imx_data_entry(MX35, CSPI, "imx35-cspi", _id, _hwid, SZ_4K) |
| 67 | imx35_cspi_data_entry(0, 1), | 67 | imx35_cspi_data_entry(0, 1), |
| 68 | imx35_cspi_data_entry(1, 2), | 68 | imx35_cspi_data_entry(1, 2), |
| 69 | }; | 69 | }; |
| 70 | #endif /* ifdef CONFIG_ARCH_MX35 */ | 70 | #endif /* ifdef CONFIG_SOC_IMX35 */ |
| 71 | 71 | ||
| 72 | #ifdef CONFIG_ARCH_MX51 | 72 | #ifdef CONFIG_SOC_IMX51 |
| 73 | const struct imx_spi_imx_data imx51_cspi_data __initconst = | 73 | const struct imx_spi_imx_data imx51_cspi_data __initconst = |
| 74 | imx_spi_imx_data_entry_single(MX51, CSPI, "imx51-cspi", 0, , SZ_4K); | 74 | imx_spi_imx_data_entry_single(MX51, CSPI, "imx51-cspi", 0, , SZ_4K); |
| 75 | 75 | ||
| @@ -79,7 +79,7 @@ const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = { | |||
| 79 | imx51_ecspi_data_entry(0, 1), | 79 | imx51_ecspi_data_entry(0, 1), |
| 80 | imx51_ecspi_data_entry(1, 2), | 80 | imx51_ecspi_data_entry(1, 2), |
| 81 | }; | 81 | }; |
| 82 | #endif /* ifdef CONFIG_ARCH_MX51 */ | 82 | #endif /* ifdef CONFIG_SOC_IMX51 */ |
| 83 | 83 | ||
| 84 | struct platform_device *__init imx_add_spi_imx( | 84 | struct platform_device *__init imx_add_spi_imx( |
| 85 | const struct imx_spi_imx_data *data, | 85 | const struct imx_spi_imx_data *data, |
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index 9915607683de..8772ce346a58 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c | |||
| @@ -49,6 +49,7 @@ | |||
| 49 | 49 | ||
| 50 | #define MXC_OTG_OFFSET 0 | 50 | #define MXC_OTG_OFFSET 0 |
| 51 | #define MXC_H1_OFFSET 0x200 | 51 | #define MXC_H1_OFFSET 0x200 |
| 52 | #define MXC_H2_OFFSET 0x400 | ||
| 52 | 53 | ||
| 53 | /* USB_CTRL */ | 54 | /* USB_CTRL */ |
| 54 | #define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */ | 55 | #define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */ |
| @@ -61,6 +62,11 @@ | |||
| 61 | #define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */ | 62 | #define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */ |
| 62 | #define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */ | 63 | #define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */ |
| 63 | 64 | ||
| 65 | /* USBH2CTRL */ | ||
| 66 | #define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) | ||
| 67 | #define MXC_H2_UCTRL_H2WIE_BIT (1 << 7) | ||
| 68 | #define MXC_H2_UCTRL_H2PM_BIT (1 << 4) | ||
| 69 | |||
| 64 | #define MXC_USBCMD_OFFSET 0x140 | 70 | #define MXC_USBCMD_OFFSET 0x140 |
| 65 | 71 | ||
| 66 | /* USBCMD */ | 72 | /* USBCMD */ |
| @@ -69,9 +75,9 @@ | |||
| 69 | int mxc_initialize_usb_hw(int port, unsigned int flags) | 75 | int mxc_initialize_usb_hw(int port, unsigned int flags) |
| 70 | { | 76 | { |
| 71 | unsigned int v; | 77 | unsigned int v; |
| 72 | #if defined(CONFIG_ARCH_MX25) | 78 | #if defined(CONFIG_SOC_IMX25) |
| 73 | if (cpu_is_mx25()) { | 79 | if (cpu_is_mx25()) { |
| 74 | v = readl(MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR + | 80 | v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + |
| 75 | USBCTRL_OTGBASE_OFFSET)); | 81 | USBCTRL_OTGBASE_OFFSET)); |
| 76 | 82 | ||
| 77 | switch (port) { | 83 | switch (port) { |
| @@ -108,14 +114,14 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) | |||
| 108 | return -EINVAL; | 114 | return -EINVAL; |
| 109 | } | 115 | } |
| 110 | 116 | ||
| 111 | writel(v, MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR + | 117 | writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + |
| 112 | USBCTRL_OTGBASE_OFFSET)); | 118 | USBCTRL_OTGBASE_OFFSET)); |
| 113 | return 0; | 119 | return 0; |
| 114 | } | 120 | } |
| 115 | #endif /* CONFIG_ARCH_MX25 */ | 121 | #endif /* if defined(CONFIG_SOC_IMX25) */ |
| 116 | #if defined(CONFIG_ARCH_MX3) | 122 | #if defined(CONFIG_ARCH_MX3) |
| 117 | if (cpu_is_mx31()) { | 123 | if (cpu_is_mx31()) { |
| 118 | v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + | 124 | v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + |
| 119 | USBCTRL_OTGBASE_OFFSET)); | 125 | USBCTRL_OTGBASE_OFFSET)); |
| 120 | 126 | ||
| 121 | switch (port) { | 127 | switch (port) { |
| @@ -153,13 +159,13 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) | |||
| 153 | return -EINVAL; | 159 | return -EINVAL; |
| 154 | } | 160 | } |
| 155 | 161 | ||
| 156 | writel(v, MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + | 162 | writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + |
| 157 | USBCTRL_OTGBASE_OFFSET)); | 163 | USBCTRL_OTGBASE_OFFSET)); |
| 158 | return 0; | 164 | return 0; |
| 159 | } | 165 | } |
| 160 | 166 | ||
| 161 | if (cpu_is_mx35()) { | 167 | if (cpu_is_mx35()) { |
| 162 | v = readl(MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR + | 168 | v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + |
| 163 | USBCTRL_OTGBASE_OFFSET)); | 169 | USBCTRL_OTGBASE_OFFSET)); |
| 164 | 170 | ||
| 165 | switch (port) { | 171 | switch (port) { |
| @@ -196,7 +202,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) | |||
| 196 | return -EINVAL; | 202 | return -EINVAL; |
| 197 | } | 203 | } |
| 198 | 204 | ||
| 199 | writel(v, MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR + | 205 | writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + |
| 200 | USBCTRL_OTGBASE_OFFSET)); | 206 | USBCTRL_OTGBASE_OFFSET)); |
| 201 | return 0; | 207 | return 0; |
| 202 | } | 208 | } |
| @@ -206,7 +212,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) | |||
| 206 | /* On i.MX27 we can use the i.MX31 USBCTRL bits, they | 212 | /* On i.MX27 we can use the i.MX31 USBCTRL bits, they |
| 207 | * are identical | 213 | * are identical |
| 208 | */ | 214 | */ |
| 209 | v = readl(MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR + | 215 | v = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + |
| 210 | USBCTRL_OTGBASE_OFFSET)); | 216 | USBCTRL_OTGBASE_OFFSET)); |
| 211 | switch (port) { | 217 | switch (port) { |
| 212 | case 0: /* OTG port */ | 218 | case 0: /* OTG port */ |
| @@ -241,12 +247,12 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) | |||
| 241 | default: | 247 | default: |
| 242 | return -EINVAL; | 248 | return -EINVAL; |
| 243 | } | 249 | } |
| 244 | writel(v, MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR + | 250 | writel(v, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + |
| 245 | USBCTRL_OTGBASE_OFFSET)); | 251 | USBCTRL_OTGBASE_OFFSET)); |
| 246 | return 0; | 252 | return 0; |
| 247 | } | 253 | } |
| 248 | #endif /* CONFIG_MACH_MX27 */ | 254 | #endif /* CONFIG_MACH_MX27 */ |
| 249 | #ifdef CONFIG_ARCH_MX51 | 255 | #ifdef CONFIG_SOC_IMX51 |
| 250 | if (cpu_is_mx51()) { | 256 | if (cpu_is_mx51()) { |
| 251 | void __iomem *usb_base; | 257 | void __iomem *usb_base; |
| 252 | void __iomem *usbotg_base; | 258 | void __iomem *usbotg_base; |
| @@ -254,6 +260,10 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) | |||
| 254 | int ret = 0; | 260 | int ret = 0; |
| 255 | 261 | ||
| 256 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); | 262 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); |
| 263 | if (!usb_base) { | ||
| 264 | printk(KERN_ERR "%s(): ioremap failed\n", __func__); | ||
| 265 | return -ENOMEM; | ||
| 266 | } | ||
| 257 | 267 | ||
| 258 | switch (port) { | 268 | switch (port) { |
| 259 | case 0: /* OTG port */ | 269 | case 0: /* OTG port */ |
| @@ -262,6 +272,9 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) | |||
| 262 | case 1: /* Host 1 port */ | 272 | case 1: /* Host 1 port */ |
| 263 | usbotg_base = usb_base + MXC_H1_OFFSET; | 273 | usbotg_base = usb_base + MXC_H1_OFFSET; |
| 264 | break; | 274 | break; |
| 275 | case 2: /* Host 2 port */ | ||
| 276 | usbotg_base = usb_base + MXC_H2_OFFSET; | ||
| 277 | break; | ||
| 265 | default: | 278 | default: |
| 266 | printk(KERN_ERR"%s no such port %d\n", __func__, port); | 279 | printk(KERN_ERR"%s no such port %d\n", __func__, port); |
| 267 | ret = -ENOENT; | 280 | ret = -ENOENT; |
| @@ -274,10 +287,13 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) | |||
| 274 | if (flags & MXC_EHCI_INTERNAL_PHY) { | 287 | if (flags & MXC_EHCI_INTERNAL_PHY) { |
| 275 | v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); | 288 | v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); |
| 276 | 289 | ||
| 277 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) | 290 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) { |
| 278 | v |= (MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is not used */ | 291 | /* OC/USBPWR is not used */ |
| 279 | else | 292 | v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; |
| 280 | v &= ~(MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is used */ | 293 | } else { |
| 294 | /* OC/USBPWR is used */ | ||
| 295 | v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT; | ||
| 296 | } | ||
| 281 | __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); | 297 | __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); |
| 282 | 298 | ||
| 283 | v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); | 299 | v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); |
| @@ -285,16 +301,23 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) | |||
| 285 | v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */ | 301 | v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */ |
| 286 | else | 302 | else |
| 287 | v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */ | 303 | v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */ |
| 304 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) | ||
| 305 | v |= MXC_OTG_UCTRL_OPM_BIT; | ||
| 306 | else | ||
| 307 | v &= ~MXC_OTG_UCTRL_OPM_BIT; | ||
| 288 | __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); | 308 | __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); |
| 289 | } | 309 | } |
| 290 | break; | 310 | break; |
| 291 | case 1: /* Host 1 */ | 311 | case 1: /* Host 1 */ |
| 292 | /*Host ULPI */ | 312 | /*Host ULPI */ |
| 293 | v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); | 313 | v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); |
| 294 | if (flags & MXC_EHCI_WAKEUP_ENABLED) | 314 | if (flags & MXC_EHCI_WAKEUP_ENABLED) { |
| 295 | v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */ | 315 | /* HOST1 wakeup/ULPI intr enable */ |
| 296 | else | 316 | v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT); |
| 297 | v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */ | 317 | } else { |
| 318 | /* HOST1 wakeup/ULPI intr disable */ | ||
| 319 | v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT); | ||
| 320 | } | ||
| 298 | 321 | ||
| 299 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) | 322 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) |
| 300 | v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ | 323 | v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ |
| @@ -315,6 +338,22 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) | |||
| 315 | v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK; | 338 | v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK; |
| 316 | __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET); | 339 | __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET); |
| 317 | break; | 340 | break; |
| 341 | case 2: /* Host 2 ULPI */ | ||
| 342 | v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET); | ||
| 343 | if (flags & MXC_EHCI_WAKEUP_ENABLED) { | ||
| 344 | /* HOST1 wakeup/ULPI intr enable */ | ||
| 345 | v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT); | ||
| 346 | } else { | ||
| 347 | /* HOST1 wakeup/ULPI intr disable */ | ||
| 348 | v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT); | ||
| 349 | } | ||
| 350 | |||
| 351 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) | ||
| 352 | v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/ | ||
| 353 | else | ||
| 354 | v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/ | ||
| 355 | __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); | ||
| 356 | break; | ||
| 318 | } | 357 | } |
| 319 | 358 | ||
| 320 | error: | 359 | error: |
diff --git a/arch/arm/plat-mxc/epit.c b/arch/arm/plat-mxc/epit.c index ee9582f4972e..d69d343ff61f 100644 --- a/arch/arm/plat-mxc/epit.c +++ b/arch/arm/plat-mxc/epit.c | |||
| @@ -93,7 +93,6 @@ static struct clocksource clocksource_epit = { | |||
| 93 | .rating = 200, | 93 | .rating = 200, |
| 94 | .read = epit_read, | 94 | .read = epit_read, |
| 95 | .mask = CLOCKSOURCE_MASK(32), | 95 | .mask = CLOCKSOURCE_MASK(32), |
| 96 | .shift = 20, | ||
| 97 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 96 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 98 | }; | 97 | }; |
| 99 | 98 | ||
| @@ -101,9 +100,7 @@ static int __init epit_clocksource_init(struct clk *timer_clk) | |||
| 101 | { | 100 | { |
| 102 | unsigned int c = clk_get_rate(timer_clk); | 101 | unsigned int c = clk_get_rate(timer_clk); |
| 103 | 102 | ||
| 104 | clocksource_epit.mult = clocksource_hz2mult(c, | 103 | clocksource_register_hz(&clocksource_epit, c); |
| 105 | clocksource_epit.shift); | ||
| 106 | clocksource_register(&clocksource_epit); | ||
| 107 | 104 | ||
| 108 | return 0; | 105 | return 0; |
| 109 | } | 106 | } |
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index 9c3e36232b5b..bc2c7bc6f10a 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c | |||
| @@ -175,7 +175,7 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) | |||
| 175 | static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) | 175 | static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) |
| 176 | { | 176 | { |
| 177 | u32 irq_stat; | 177 | u32 irq_stat; |
| 178 | struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq); | 178 | struct mxc_gpio_port *port = get_irq_data(irq); |
| 179 | 179 | ||
| 180 | irq_stat = __raw_readl(port->base + GPIO_ISR) & | 180 | irq_stat = __raw_readl(port->base + GPIO_ISR) & |
| 181 | __raw_readl(port->base + GPIO_IMR); | 181 | __raw_readl(port->base + GPIO_IMR); |
| @@ -188,7 +188,7 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc) | |||
| 188 | { | 188 | { |
| 189 | int i; | 189 | int i; |
| 190 | u32 irq_msk, irq_stat; | 190 | u32 irq_msk, irq_stat; |
| 191 | struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq); | 191 | struct mxc_gpio_port *port = get_irq_data(irq); |
| 192 | 192 | ||
| 193 | /* walk through all interrupt status registers */ | 193 | /* walk through all interrupt status registers */ |
| 194 | for (i = 0; i < gpio_table_size; i++) { | 194 | for (i = 0; i < gpio_table_size; i++) { |
| @@ -349,3 +349,113 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) | |||
| 349 | 349 | ||
| 350 | return 0; | 350 | return 0; |
| 351 | } | 351 | } |
| 352 | |||
| 353 | #define DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, _irq_high) \ | ||
| 354 | { \ | ||
| 355 | .chip.label = "gpio-" #_id, \ | ||
| 356 | .irq = _irq, \ | ||
| 357 | .irq_high = _irq_high, \ | ||
| 358 | .base = soc ## _IO_ADDRESS( \ | ||
| 359 | soc ## _GPIO ## _hwid ## _BASE_ADDR), \ | ||
| 360 | .virtual_irq_start = MXC_GPIO_IRQ_START + (_id) * 32, \ | ||
| 361 | } | ||
| 362 | |||
| 363 | #define DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, _irq) \ | ||
| 364 | DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, 0) | ||
| 365 | #define DEFINE_IMX_GPIO_PORT(soc, _id, _hwid) \ | ||
| 366 | DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, 0) | ||
| 367 | |||
| 368 | #define DEFINE_REGISTER_FUNCTION(prefix) \ | ||
| 369 | int __init prefix ## _register_gpios(void) \ | ||
| 370 | { \ | ||
| 371 | return mxc_gpio_init(prefix ## _gpio_ports, \ | ||
| 372 | ARRAY_SIZE(prefix ## _gpio_ports)); \ | ||
| 373 | } | ||
| 374 | |||
| 375 | #if defined(CONFIG_SOC_IMX1) | ||
| 376 | static struct mxc_gpio_port imx1_gpio_ports[] = { | ||
| 377 | DEFINE_IMX_GPIO_PORT_IRQ(MX1, 0, 1, MX1_GPIO_INT_PORTA), | ||
| 378 | DEFINE_IMX_GPIO_PORT_IRQ(MX1, 1, 2, MX1_GPIO_INT_PORTB), | ||
| 379 | DEFINE_IMX_GPIO_PORT_IRQ(MX1, 2, 3, MX1_GPIO_INT_PORTC), | ||
| 380 | DEFINE_IMX_GPIO_PORT_IRQ(MX1, 3, 4, MX1_GPIO_INT_PORTD), | ||
| 381 | }; | ||
| 382 | |||
| 383 | DEFINE_REGISTER_FUNCTION(imx1) | ||
| 384 | |||
| 385 | #endif /* if defined(CONFIG_SOC_IMX1) */ | ||
| 386 | |||
| 387 | #if defined(CONFIG_SOC_IMX21) | ||
| 388 | static struct mxc_gpio_port imx21_gpio_ports[] = { | ||
| 389 | DEFINE_IMX_GPIO_PORT_IRQ(MX21, 0, 1, MX21_INT_GPIO), | ||
| 390 | DEFINE_IMX_GPIO_PORT(MX21, 1, 2), | ||
| 391 | DEFINE_IMX_GPIO_PORT(MX21, 2, 3), | ||
| 392 | DEFINE_IMX_GPIO_PORT(MX21, 3, 4), | ||
| 393 | DEFINE_IMX_GPIO_PORT(MX21, 4, 5), | ||
| 394 | DEFINE_IMX_GPIO_PORT(MX21, 5, 6), | ||
| 395 | }; | ||
| 396 | |||
| 397 | DEFINE_REGISTER_FUNCTION(imx21) | ||
| 398 | |||
| 399 | #endif /* if defined(CONFIG_SOC_IMX21) */ | ||
| 400 | |||
| 401 | #if defined(CONFIG_SOC_IMX25) | ||
| 402 | static struct mxc_gpio_port imx25_gpio_ports[] = { | ||
| 403 | DEFINE_IMX_GPIO_PORT_IRQ(MX25, 0, 1, MX25_INT_GPIO1), | ||
| 404 | DEFINE_IMX_GPIO_PORT_IRQ(MX25, 1, 2, MX25_INT_GPIO2), | ||
| 405 | DEFINE_IMX_GPIO_PORT_IRQ(MX25, 2, 3, MX25_INT_GPIO3), | ||
| 406 | DEFINE_IMX_GPIO_PORT_IRQ(MX25, 3, 4, MX25_INT_GPIO4), | ||
| 407 | }; | ||
| 408 | |||
| 409 | DEFINE_REGISTER_FUNCTION(imx25) | ||
| 410 | |||
| 411 | #endif /* if defined(CONFIG_SOC_IMX25) */ | ||
| 412 | |||
| 413 | #if defined(CONFIG_SOC_IMX27) | ||
| 414 | static struct mxc_gpio_port imx27_gpio_ports[] = { | ||
| 415 | DEFINE_IMX_GPIO_PORT_IRQ(MX27, 0, 1, MX27_INT_GPIO), | ||
| 416 | DEFINE_IMX_GPIO_PORT(MX27, 1, 2), | ||
| 417 | DEFINE_IMX_GPIO_PORT(MX27, 2, 3), | ||
| 418 | DEFINE_IMX_GPIO_PORT(MX27, 3, 4), | ||
| 419 | DEFINE_IMX_GPIO_PORT(MX27, 4, 5), | ||
| 420 | DEFINE_IMX_GPIO_PORT(MX27, 5, 6), | ||
| 421 | }; | ||
| 422 | |||
| 423 | DEFINE_REGISTER_FUNCTION(imx27) | ||
| 424 | |||
| 425 | #endif /* if defined(CONFIG_SOC_IMX27) */ | ||
| 426 | |||
| 427 | #if defined(CONFIG_SOC_IMX31) | ||
| 428 | static struct mxc_gpio_port imx31_gpio_ports[] = { | ||
| 429 | DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1), | ||
| 430 | DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2), | ||
| 431 | DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3), | ||
| 432 | }; | ||
| 433 | |||
| 434 | DEFINE_REGISTER_FUNCTION(imx31) | ||
| 435 | |||
| 436 | #endif /* if defined(CONFIG_SOC_IMX31) */ | ||
| 437 | |||
| 438 | #if defined(CONFIG_SOC_IMX35) | ||
| 439 | static struct mxc_gpio_port imx35_gpio_ports[] = { | ||
| 440 | DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1), | ||
| 441 | DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2), | ||
| 442 | DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3), | ||
| 443 | }; | ||
| 444 | |||
| 445 | DEFINE_REGISTER_FUNCTION(imx35) | ||
| 446 | |||
| 447 | #endif /* if defined(CONFIG_SOC_IMX35) */ | ||
| 448 | |||
| 449 | #if defined(CONFIG_SOC_IMX50) | ||
| 450 | static struct mxc_gpio_port imx50_gpio_ports[] = { | ||
| 451 | DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 0, 1, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH), | ||
| 452 | DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 1, 2, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH), | ||
| 453 | DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 2, 3, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH), | ||
| 454 | DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 3, 4, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH), | ||
| 455 | DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 4, 5, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH), | ||
| 456 | DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 5, 6, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH), | ||
| 457 | }; | ||
| 458 | |||
| 459 | DEFINE_REGISTER_FUNCTION(imx50) | ||
| 460 | |||
| 461 | #endif /* if defined(CONFIG_SOC_IMX50) */ | ||
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 7a1e1f89ff09..aea2cd3b6d15 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h | |||
| @@ -20,7 +20,9 @@ extern void mx25_map_io(void); | |||
| 20 | extern void mx27_map_io(void); | 20 | extern void mx27_map_io(void); |
| 21 | extern void mx31_map_io(void); | 21 | extern void mx31_map_io(void); |
| 22 | extern void mx35_map_io(void); | 22 | extern void mx35_map_io(void); |
| 23 | extern void mx50_map_io(void); | ||
| 23 | extern void mx51_map_io(void); | 24 | extern void mx51_map_io(void); |
| 25 | extern void mx53_map_io(void); | ||
| 24 | extern void mxc91231_map_io(void); | 26 | extern void mxc91231_map_io(void); |
| 25 | extern void mxc_init_irq(void __iomem *); | 27 | extern void mxc_init_irq(void __iomem *); |
| 26 | extern void tzic_init_irq(void __iomem *); | 28 | extern void tzic_init_irq(void __iomem *); |
| @@ -30,7 +32,9 @@ extern void mx25_init_irq(void); | |||
| 30 | extern void mx27_init_irq(void); | 32 | extern void mx27_init_irq(void); |
| 31 | extern void mx31_init_irq(void); | 33 | extern void mx31_init_irq(void); |
| 32 | extern void mx35_init_irq(void); | 34 | extern void mx35_init_irq(void); |
| 35 | extern void mx50_init_irq(void); | ||
| 33 | extern void mx51_init_irq(void); | 36 | extern void mx51_init_irq(void); |
| 37 | extern void mx53_init_irq(void); | ||
| 34 | extern void mxc91231_init_irq(void); | 38 | extern void mxc91231_init_irq(void); |
| 35 | extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq); | 39 | extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq); |
| 36 | extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); | 40 | extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); |
| @@ -42,6 +46,8 @@ extern int mx31_clocks_init(unsigned long fref); | |||
| 42 | extern int mx35_clocks_init(void); | 46 | extern int mx35_clocks_init(void); |
| 43 | extern int mx51_clocks_init(unsigned long ckil, unsigned long osc, | 47 | extern int mx51_clocks_init(unsigned long ckil, unsigned long osc, |
| 44 | unsigned long ckih1, unsigned long ckih2); | 48 | unsigned long ckih1, unsigned long ckih2); |
| 49 | extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, | ||
| 50 | unsigned long ckih1, unsigned long ckih2); | ||
| 45 | extern int mxc91231_clocks_init(unsigned long fref); | 51 | extern int mxc91231_clocks_init(unsigned long fref); |
| 46 | extern int mxc_register_gpios(void); | 52 | extern int mxc_register_gpios(void); |
| 47 | extern int mxc_register_device(struct platform_device *pdev, void *data); | 53 | extern int mxc_register_device(struct platform_device *pdev, void *data); |
| @@ -50,5 +56,6 @@ extern void mxc_arch_reset_init(void __iomem *); | |||
| 50 | extern void mxc91231_power_off(void); | 56 | extern void mxc91231_power_off(void); |
| 51 | extern void mxc91231_arch_reset(int, const char *); | 57 | extern void mxc91231_arch_reset(int, const char *); |
| 52 | extern void mxc91231_prepare_idle(void); | 58 | extern void mxc91231_prepare_idle(void); |
| 53 | 59 | extern void mx51_efikamx_reset(void); | |
| 60 | extern int mx53_revision(void); | ||
| 54 | #endif | 61 | #endif |
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S index d56213fb901b..3b3a37c25c56 100644 --- a/arch/arm/plat-mxc/include/mach/debug-macro.S +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S | |||
| @@ -10,58 +10,49 @@ | |||
| 10 | * published by the Free Software Foundation. | 10 | * published by the Free Software Foundation. |
| 11 | * | 11 | * |
| 12 | */ | 12 | */ |
| 13 | #define IMX_NEEDS_DEPRECATED_SYMBOLS | 13 | #include <mach/hardware.h> |
| 14 | 14 | ||
| 15 | #ifdef CONFIG_ARCH_MX1 | 15 | #ifdef CONFIG_ARCH_MX1 |
| 16 | #include <mach/mx1.h> | 16 | #define UART_PADDR MX1_UART1_BASE_ADDR |
| 17 | #define UART_PADDR UART1_BASE_ADDR | ||
| 18 | #define UART_VADDR IO_ADDRESS(UART1_BASE_ADDR) | ||
| 19 | #endif | 17 | #endif |
| 20 | 18 | ||
| 21 | #ifdef CONFIG_ARCH_MX25 | 19 | #ifdef CONFIG_ARCH_MX25 |
| 22 | #ifdef UART_PADDR | 20 | #ifdef UART_PADDR |
| 23 | #error "CONFIG_DEBUG_LL is incompatible with multiple archs" | 21 | #error "CONFIG_DEBUG_LL is incompatible with multiple archs" |
| 24 | #endif | 22 | #endif |
| 25 | #include <mach/mx25.h> | ||
| 26 | #define UART_PADDR MX25_UART1_BASE_ADDR | 23 | #define UART_PADDR MX25_UART1_BASE_ADDR |
| 27 | #define UART_VADDR MX25_AIPS1_IO_ADDRESS(MX25_UART1_BASE_ADDR) | ||
| 28 | #endif | 24 | #endif |
| 29 | 25 | ||
| 30 | #ifdef CONFIG_ARCH_MX2 | 26 | #ifdef CONFIG_ARCH_MX2 |
| 31 | #ifdef UART_PADDR | 27 | #ifdef UART_PADDR |
| 32 | #error "CONFIG_DEBUG_LL is incompatible with multiple archs" | 28 | #error "CONFIG_DEBUG_LL is incompatible with multiple archs" |
| 33 | #endif | 29 | #endif |
| 34 | #include <mach/mx2x.h> | 30 | #define UART_PADDR MX2x_UART1_BASE_ADDR |
| 35 | #define UART_PADDR UART1_BASE_ADDR | ||
| 36 | #define UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR) | ||
| 37 | #endif | 31 | #endif |
| 38 | 32 | ||
| 39 | #ifdef CONFIG_ARCH_MX3 | 33 | #ifdef CONFIG_ARCH_MX3 |
| 40 | #ifdef UART_PADDR | 34 | #ifdef UART_PADDR |
| 41 | #error "CONFIG_DEBUG_LL is incompatible with multiple archs" | 35 | #error "CONFIG_DEBUG_LL is incompatible with multiple archs" |
| 42 | #endif | 36 | #endif |
| 43 | #include <mach/mx3x.h> | 37 | #define UART_PADDR MX3x_UART1_BASE_ADDR |
| 44 | #define UART_PADDR UART1_BASE_ADDR | ||
| 45 | #define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) | ||
| 46 | #endif | 38 | #endif |
| 47 | 39 | ||
| 48 | #ifdef CONFIG_ARCH_MX5 | 40 | #ifdef CONFIG_ARCH_MX5 |
| 49 | #ifdef UART_PADDR | 41 | #ifdef UART_PADDR |
| 50 | #error "CONFIG_DEBUG_LL is incompatible with multiple archs" | 42 | #error "CONFIG_DEBUG_LL is incompatible with multiple archs" |
| 51 | #endif | 43 | #endif |
| 52 | #include <mach/mx51.h> | ||
| 53 | #define UART_PADDR MX51_UART1_BASE_ADDR | 44 | #define UART_PADDR MX51_UART1_BASE_ADDR |
| 54 | #define UART_VADDR MX51_AIPS1_IO_ADDRESS(MX51_UART1_BASE_ADDR) | ||
| 55 | #endif | 45 | #endif |
| 56 | 46 | ||
| 57 | #ifdef CONFIG_ARCH_MXC91231 | 47 | #ifdef CONFIG_ARCH_MXC91231 |
| 58 | #ifdef UART_PADDR | 48 | #ifdef UART_PADDR |
| 59 | #error "CONFIG_DEBUG_LL is incompatible with multiple archs" | 49 | #error "CONFIG_DEBUG_LL is incompatible with multiple archs" |
| 60 | #endif | 50 | #endif |
| 61 | #include <mach/mxc91231.h> | ||
| 62 | #define UART_PADDR MXC91231_UART2_BASE_ADDR | 51 | #define UART_PADDR MXC91231_UART2_BASE_ADDR |
| 63 | #define UART_VADDR MXC91231_IO_ADDRESS(MXC91231_UART2_BASE_ADDR) | ||
| 64 | #endif | 52 | #endif |
| 53 | |||
| 54 | #define UART_VADDR IMX_IO_ADDRESS(UART_PADDR) | ||
| 55 | |||
| 65 | .macro addruart, rp, rv | 56 | .macro addruart, rp, rv |
| 66 | ldr \rp, =UART_PADDR @ physical | 57 | ldr \rp, =UART_PADDR @ physical |
| 67 | ldr \rv, =UART_VADDR @ virtual | 58 | ldr \rv, =UART_VADDR @ virtual |
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 8c6896fd1e5f..8658c9caa650 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h | |||
| @@ -10,9 +10,19 @@ | |||
| 10 | #include <linux/platform_device.h> | 10 | #include <linux/platform_device.h> |
| 11 | #include <linux/init.h> | 11 | #include <linux/init.h> |
| 12 | 12 | ||
| 13 | struct platform_device *imx_add_platform_device(const char *name, int id, | 13 | struct platform_device *imx_add_platform_device_dmamask( |
| 14 | const char *name, int id, | ||
| 14 | const struct resource *res, unsigned int num_resources, | 15 | const struct resource *res, unsigned int num_resources, |
| 15 | const void *data, size_t size_data); | 16 | const void *data, size_t size_data, u64 dmamask); |
| 17 | |||
| 18 | static inline struct platform_device *imx_add_platform_device( | ||
| 19 | const char *name, int id, | ||
| 20 | const struct resource *res, unsigned int num_resources, | ||
| 21 | const void *data, size_t size_data) | ||
| 22 | { | ||
| 23 | return imx_add_platform_device_dmamask( | ||
| 24 | name, id, res, num_resources, data, size_data, 0); | ||
| 25 | } | ||
| 16 | 26 | ||
| 17 | #include <linux/fec.h> | 27 | #include <linux/fec.h> |
| 18 | struct imx_fec_data { | 28 | struct imx_fec_data { |
| @@ -24,15 +34,63 @@ struct platform_device *__init imx_add_fec( | |||
| 24 | const struct fec_platform_data *pdata); | 34 | const struct fec_platform_data *pdata); |
| 25 | 35 | ||
| 26 | #include <linux/can/platform/flexcan.h> | 36 | #include <linux/can/platform/flexcan.h> |
| 27 | struct platform_device *__init imx_add_flexcan(int id, | 37 | struct imx_flexcan_data { |
| 28 | resource_size_t iobase, resource_size_t iosize, | 38 | int id; |
| 29 | resource_size_t irq, | 39 | resource_size_t iobase; |
| 40 | resource_size_t iosize; | ||
| 41 | resource_size_t irq; | ||
| 42 | }; | ||
| 43 | struct platform_device *__init imx_add_flexcan( | ||
| 44 | const struct imx_flexcan_data *data, | ||
| 30 | const struct flexcan_platform_data *pdata); | 45 | const struct flexcan_platform_data *pdata); |
| 31 | 46 | ||
| 47 | #include <linux/fsl_devices.h> | ||
| 48 | struct imx_fsl_usb2_udc_data { | ||
| 49 | resource_size_t iobase; | ||
| 50 | resource_size_t irq; | ||
| 51 | }; | ||
| 52 | struct platform_device *__init imx_add_fsl_usb2_udc( | ||
| 53 | const struct imx_fsl_usb2_udc_data *data, | ||
| 54 | const struct fsl_usb2_platform_data *pdata); | ||
| 55 | |||
| 32 | #include <linux/gpio_keys.h> | 56 | #include <linux/gpio_keys.h> |
| 33 | struct platform_device *__init imx_add_gpio_keys( | 57 | struct platform_device *__init imx_add_gpio_keys( |
| 34 | const struct gpio_keys_platform_data *pdata); | 58 | const struct gpio_keys_platform_data *pdata); |
| 35 | 59 | ||
| 60 | #include <mach/mx21-usbhost.h> | ||
| 61 | struct imx_imx21_hcd_data { | ||
| 62 | resource_size_t iobase; | ||
| 63 | resource_size_t irq; | ||
| 64 | }; | ||
| 65 | struct platform_device *__init imx_add_imx21_hcd( | ||
| 66 | const struct imx_imx21_hcd_data *data, | ||
| 67 | const struct mx21_usbh_platform_data *pdata); | ||
| 68 | |||
| 69 | struct imx_imx2_wdt_data { | ||
| 70 | int id; | ||
| 71 | resource_size_t iobase; | ||
| 72 | resource_size_t iosize; | ||
| 73 | }; | ||
| 74 | struct platform_device *__init imx_add_imx2_wdt( | ||
| 75 | const struct imx_imx2_wdt_data *data); | ||
| 76 | |||
| 77 | struct imx_imxdi_rtc_data { | ||
| 78 | resource_size_t iobase; | ||
| 79 | resource_size_t irq; | ||
| 80 | }; | ||
| 81 | struct platform_device *__init imx_add_imxdi_rtc( | ||
| 82 | const struct imx_imxdi_rtc_data *data); | ||
| 83 | |||
| 84 | #include <mach/imxfb.h> | ||
| 85 | struct imx_imx_fb_data { | ||
| 86 | resource_size_t iobase; | ||
| 87 | resource_size_t iosize; | ||
| 88 | resource_size_t irq; | ||
| 89 | }; | ||
| 90 | struct platform_device *__init imx_add_imx_fb( | ||
| 91 | const struct imx_imx_fb_data *data, | ||
| 92 | const struct imx_fb_platform_data *pdata); | ||
| 93 | |||
| 36 | #include <mach/i2c.h> | 94 | #include <mach/i2c.h> |
| 37 | struct imx_imx_i2c_data { | 95 | struct imx_imx_i2c_data { |
| 38 | int id; | 96 | int id; |
| @@ -44,6 +102,16 @@ struct platform_device *__init imx_add_imx_i2c( | |||
| 44 | const struct imx_imx_i2c_data *data, | 102 | const struct imx_imx_i2c_data *data, |
| 45 | const struct imxi2c_platform_data *pdata); | 103 | const struct imxi2c_platform_data *pdata); |
| 46 | 104 | ||
| 105 | #include <linux/input/matrix_keypad.h> | ||
| 106 | struct imx_imx_keypad_data { | ||
| 107 | resource_size_t iobase; | ||
| 108 | resource_size_t iosize; | ||
| 109 | resource_size_t irq; | ||
| 110 | }; | ||
| 111 | struct platform_device *__init imx_add_imx_keypad( | ||
| 112 | const struct imx_imx_keypad_data *data, | ||
| 113 | const struct matrix_keymap_data *pdata); | ||
| 114 | |||
| 47 | #include <mach/ssi.h> | 115 | #include <mach/ssi.h> |
| 48 | struct imx_imx_ssi_data { | 116 | struct imx_imx_ssi_data { |
| 49 | int id; | 117 | int id; |
| @@ -82,6 +150,67 @@ struct platform_device *__init imx_add_imx_uart_1irq( | |||
| 82 | const struct imx_imx_uart_1irq_data *data, | 150 | const struct imx_imx_uart_1irq_data *data, |
| 83 | const struct imxuart_platform_data *pdata); | 151 | const struct imxuart_platform_data *pdata); |
| 84 | 152 | ||
| 153 | #include <mach/usb.h> | ||
| 154 | struct imx_imx_udc_data { | ||
| 155 | resource_size_t iobase; | ||
| 156 | resource_size_t iosize; | ||
| 157 | resource_size_t irq0; | ||
| 158 | resource_size_t irq1; | ||
| 159 | resource_size_t irq2; | ||
| 160 | resource_size_t irq3; | ||
| 161 | resource_size_t irq4; | ||
| 162 | resource_size_t irq5; | ||
| 163 | resource_size_t irq6; | ||
| 164 | }; | ||
| 165 | struct platform_device *__init imx_add_imx_udc( | ||
| 166 | const struct imx_imx_udc_data *data, | ||
| 167 | const struct imxusb_platform_data *pdata); | ||
| 168 | |||
| 169 | #include <mach/mx1_camera.h> | ||
| 170 | struct imx_mx1_camera_data { | ||
| 171 | resource_size_t iobase; | ||
| 172 | resource_size_t iosize; | ||
| 173 | resource_size_t irq; | ||
| 174 | }; | ||
| 175 | struct platform_device *__init imx_add_mx1_camera( | ||
| 176 | const struct imx_mx1_camera_data *data, | ||
| 177 | const struct mx1_camera_pdata *pdata); | ||
| 178 | |||
| 179 | #include <mach/mx2_cam.h> | ||
| 180 | struct imx_mx2_camera_data { | ||
| 181 | resource_size_t iobasecsi; | ||
| 182 | resource_size_t iosizecsi; | ||
| 183 | resource_size_t irqcsi; | ||
| 184 | resource_size_t iobaseemmaprp; | ||
| 185 | resource_size_t iosizeemmaprp; | ||
| 186 | resource_size_t irqemmaprp; | ||
| 187 | }; | ||
| 188 | struct platform_device *__init imx_add_mx2_camera( | ||
| 189 | const struct imx_mx2_camera_data *data, | ||
| 190 | const struct mx2_camera_platform_data *pdata); | ||
| 191 | |||
| 192 | #include <mach/mxc_ehci.h> | ||
| 193 | struct imx_mxc_ehci_data { | ||
| 194 | int id; | ||
| 195 | resource_size_t iobase; | ||
| 196 | resource_size_t irq; | ||
| 197 | }; | ||
| 198 | struct platform_device *__init imx_add_mxc_ehci( | ||
| 199 | const struct imx_mxc_ehci_data *data, | ||
| 200 | const struct mxc_usbh_platform_data *pdata); | ||
| 201 | |||
| 202 | #include <mach/mmc.h> | ||
| 203 | struct imx_mxc_mmc_data { | ||
| 204 | int id; | ||
| 205 | resource_size_t iobase; | ||
| 206 | resource_size_t iosize; | ||
| 207 | resource_size_t irq; | ||
| 208 | resource_size_t dmareq; | ||
| 209 | }; | ||
| 210 | struct platform_device *__init imx_add_mxc_mmc( | ||
| 211 | const struct imx_mxc_mmc_data *data, | ||
| 212 | const struct imxmmc_platform_data *pdata); | ||
| 213 | |||
| 85 | #include <mach/mxc_nand.h> | 214 | #include <mach/mxc_nand.h> |
| 86 | struct imx_mxc_nand_data { | 215 | struct imx_mxc_nand_data { |
| 87 | /* | 216 | /* |
| @@ -99,24 +228,39 @@ struct platform_device *__init imx_add_mxc_nand( | |||
| 99 | const struct imx_mxc_nand_data *data, | 228 | const struct imx_mxc_nand_data *data, |
| 100 | const struct mxc_nand_platform_data *pdata); | 229 | const struct mxc_nand_platform_data *pdata); |
| 101 | 230 | ||
| 102 | #include <mach/spi.h> | 231 | struct imx_mxc_pwm_data { |
| 103 | struct imx_spi_imx_data { | ||
| 104 | const char *devid; | ||
| 105 | int id; | 232 | int id; |
| 106 | resource_size_t iobase; | 233 | resource_size_t iobase; |
| 107 | resource_size_t iosize; | 234 | resource_size_t iosize; |
| 108 | int irq; | 235 | resource_size_t irq; |
| 109 | }; | 236 | }; |
| 110 | struct platform_device *__init imx_add_spi_imx( | 237 | struct platform_device *__init imx_add_mxc_pwm( |
| 111 | const struct imx_spi_imx_data *data, | 238 | const struct imx_mxc_pwm_data *data); |
| 112 | const struct spi_imx_master *pdata); | 239 | |
| 240 | struct imx_mxc_w1_data { | ||
| 241 | resource_size_t iobase; | ||
| 242 | }; | ||
| 243 | struct platform_device *__init imx_add_mxc_w1( | ||
| 244 | const struct imx_mxc_w1_data *data); | ||
| 113 | 245 | ||
| 114 | #include <mach/esdhc.h> | 246 | #include <mach/esdhc.h> |
| 115 | struct imx_esdhc_imx_data { | 247 | struct imx_sdhci_esdhc_imx_data { |
| 116 | int id; | 248 | int id; |
| 117 | resource_size_t iobase; | 249 | resource_size_t iobase; |
| 118 | resource_size_t irq; | 250 | resource_size_t irq; |
| 119 | }; | 251 | }; |
| 120 | struct platform_device *__init imx_add_esdhc( | 252 | struct platform_device *__init imx_add_sdhci_esdhc_imx( |
| 121 | const struct imx_esdhc_imx_data *data, | 253 | const struct imx_sdhci_esdhc_imx_data *data, |
| 122 | const struct esdhc_platform_data *pdata); | 254 | const struct esdhc_platform_data *pdata); |
| 255 | |||
| 256 | #include <mach/spi.h> | ||
| 257 | struct imx_spi_imx_data { | ||
| 258 | const char *devid; | ||
| 259 | int id; | ||
| 260 | resource_size_t iobase; | ||
| 261 | resource_size_t iosize; | ||
| 262 | int irq; | ||
| 263 | }; | ||
| 264 | struct platform_device *__init imx_add_spi_imx( | ||
| 265 | const struct imx_spi_imx_data *data, | ||
| 266 | const struct spi_imx_master *pdata); | ||
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S index aeb08697726b..bd9bb9799141 100644 --- a/arch/arm/plat-mxc/include/mach/entry-macro.S +++ b/arch/arm/plat-mxc/include/mach/entry-macro.S | |||
| @@ -54,15 +54,15 @@ | |||
| 54 | #elif defined CONFIG_MXC_TZIC | 54 | #elif defined CONFIG_MXC_TZIC |
| 55 | @ Load offset & priority of the highest priority | 55 | @ Load offset & priority of the highest priority |
| 56 | @ interrupt pending. | 56 | @ interrupt pending. |
| 57 | @ 0x080 is INTSEC0 register | ||
| 57 | @ 0xD80 is HIPND0 register | 58 | @ 0xD80 is HIPND0 register |
| 58 | mov \irqnr, #0 | 59 | mov \irqnr, #0 |
| 59 | mov \irqstat, #0x0D80 | 60 | 1000: add \irqstat, \base, \irqnr, lsr #3 |
| 60 | 1000: | 61 | ldr \tmp, [\irqstat, #0xd80] |
| 61 | ldr \tmp, [\irqstat, \base] | 62 | ldr \irqstat, [\irqstat, #0x080] |
| 62 | cmp \tmp, #0 | 63 | ands \tmp, \tmp, \irqstat |
| 63 | bne 1001f | 64 | bne 1001f |
| 64 | addeq \irqnr, \irqnr, #32 | 65 | add \irqnr, \irqnr, #32 |
| 65 | addeq \irqstat, \irqstat, #4 | ||
| 66 | cmp \irqnr, #128 | 66 | cmp \irqnr, #128 |
| 67 | blo 1000b | 67 | blo 1000b |
| 68 | b 2001f | 68 | b 2001f |
diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h index af33b74f569e..0044e2f1bea8 100644 --- a/arch/arm/plat-mxc/include/mach/gpio.h +++ b/arch/arm/plat-mxc/include/mach/gpio.h | |||
| @@ -23,6 +23,11 @@ | |||
| 23 | #include <mach/hardware.h> | 23 | #include <mach/hardware.h> |
| 24 | #include <asm-generic/gpio.h> | 24 | #include <asm-generic/gpio.h> |
| 25 | 25 | ||
| 26 | |||
| 27 | /* There's a off-by-one betweem the gpio bank number and the gpiochip */ | ||
| 28 | /* range e.g. GPIO_1_5 is gpio 5 under linux */ | ||
| 29 | #define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr)) | ||
| 30 | |||
| 26 | /* use gpiolib dispatchers */ | 31 | /* use gpiolib dispatchers */ |
| 27 | #define gpio_get_value __gpio_get_value | 32 | #define gpio_get_value __gpio_get_value |
| 28 | #define gpio_set_value __gpio_set_value | 33 | #define gpio_set_value __gpio_set_value |
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index ebadf4ac43fc..26bb1bab4aeb 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h | |||
| @@ -22,13 +22,92 @@ | |||
| 22 | 22 | ||
| 23 | #include <asm/sizes.h> | 23 | #include <asm/sizes.h> |
| 24 | 24 | ||
| 25 | #define IMX_IO_ADDRESS(addr, module) \ | 25 | #ifdef __ASSEMBLER__ |
| 26 | ((void __force __iomem *) \ | 26 | #define IOMEM(addr) (addr) |
| 27 | (((unsigned long)((addr) - (module ## _BASE_ADDR)) < module ## _SIZE) ?\ | 27 | #else |
| 28 | (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)) | 28 | #define IOMEM(addr) ((void __force __iomem *)(addr)) |
| 29 | #endif | ||
| 30 | |||
| 31 | #define IMX_IO_P2V_MODULE(addr, module) \ | ||
| 32 | (((addr) - module ## _BASE_ADDR) < module ## _SIZE ? \ | ||
| 33 | (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0) | ||
| 34 | |||
| 35 | /* | ||
| 36 | * This is rather complicated for humans and ugly to verify, but for a machine | ||
| 37 | * it's OK. Still more as it is usually only applied to constants. The upsides | ||
| 38 | * on using this approach are: | ||
| 39 | * | ||
| 40 | * - same mapping on all i.MX machines | ||
| 41 | * - works for assembler, too | ||
| 42 | * - no need to nurture #defines for virtual addresses | ||
| 43 | * | ||
| 44 | * The downside it, it's hard to verify (but I have a script for that). | ||
| 45 | * | ||
| 46 | * Obviously this needs to be injective for each SoC. In general it maps the | ||
| 47 | * whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff] | ||
| 48 | * is free for per-machine use (e.g. KZM_ARM11_01 uses 64MiB there). | ||
| 49 | * | ||
| 50 | * It applies the following mappings for the different SoCs: | ||
| 51 | * | ||
| 52 | * mx1: | ||
| 53 | * IO 0x00200000+0x100000 -> 0xf4000000+0x100000 | ||
| 54 | * mx21: | ||
| 55 | * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000 | ||
| 56 | * SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000 | ||
| 57 | * X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000 | ||
| 58 | * mx25: | ||
| 59 | * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 | ||
| 60 | * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 | ||
| 61 | * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 | ||
| 62 | * mx27: | ||
| 63 | * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000 | ||
| 64 | * SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000 | ||
| 65 | * X_MEMC 0xd8000000+0x100000 -> 0xf5c00000+0x100000 | ||
| 66 | * mx31: | ||
| 67 | * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 | ||
| 68 | * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 | ||
| 69 | * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 | ||
| 70 | * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000 | ||
| 71 | * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 | ||
| 72 | * mx35: | ||
| 73 | * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 | ||
| 74 | * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 | ||
| 75 | * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000 | ||
| 76 | * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000 | ||
| 77 | * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 | ||
| 78 | * mx50: | ||
| 79 | * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000 | ||
| 80 | * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 | ||
| 81 | * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000 | ||
| 82 | * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000 | ||
| 83 | * mx51: | ||
| 84 | * IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000 | ||
| 85 | * DEBUG 0x60000000+0x100000 -> 0xf5000000+0x100000 | ||
| 86 | * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000 | ||
| 87 | * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000 | ||
| 88 | * AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000 | ||
| 89 | * mxc91231: | ||
| 90 | * L2CC 0x30000000+0x010000 -> 0xf4400000+0x010000 | ||
| 91 | * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000 | ||
| 92 | * ROMP 0x60000000+0x010000 -> 0xf5000000+0x010000 | ||
| 93 | * AVIC 0x68000000+0x010000 -> 0xf5800000+0x010000 | ||
| 94 | * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000 | ||
| 95 | * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 | ||
| 96 | * SPBA1 0x52000000+0x100000 -> 0xf5600000+0x100000 | ||
| 97 | * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000 | ||
| 98 | */ | ||
| 99 | #define IMX_IO_P2V(x) ( \ | ||
| 100 | 0xf4000000 + \ | ||
| 101 | (((x) & 0x50000000) >> 6) + \ | ||
| 102 | (((x) & 0x0b000000) >> 4) + \ | ||
| 103 | (((x) & 0x000fffff))) | ||
| 104 | |||
| 105 | #define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x)) | ||
| 29 | 106 | ||
| 30 | #ifdef CONFIG_ARCH_MX5 | 107 | #ifdef CONFIG_ARCH_MX5 |
| 108 | #include <mach/mx50.h> | ||
| 31 | #include <mach/mx51.h> | 109 | #include <mach/mx51.h> |
| 110 | #include <mach/mx53.h> | ||
| 32 | #endif | 111 | #endif |
| 33 | 112 | ||
| 34 | #ifdef CONFIG_ARCH_MX3 | 113 | #ifdef CONFIG_ARCH_MX3 |
| @@ -61,4 +140,11 @@ | |||
| 61 | 140 | ||
| 62 | #include <mach/mxc.h> | 141 | #include <mach/mxc.h> |
| 63 | 142 | ||
| 143 | #define imx_map_entry(soc, name, _type) { \ | ||
| 144 | .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \ | ||
| 145 | .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \ | ||
| 146 | .length = soc ## _ ## name ## _SIZE, \ | ||
| 147 | .type = _type, \ | ||
| 148 | } | ||
| 149 | |||
| 64 | #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ | 150 | #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/imxfb.h b/arch/arm/plat-mxc/include/mach/imxfb.h index 5263506b7ddf..9de8f062ad5d 100644 --- a/arch/arm/plat-mxc/include/mach/imxfb.h +++ b/arch/arm/plat-mxc/include/mach/imxfb.h | |||
| @@ -1,6 +1,8 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * This structure describes the machine which we are running on. | 2 | * This structure describes the machine which we are running on. |
| 3 | */ | 3 | */ |
| 4 | #ifndef __MACH_IMXFB_H__ | ||
| 5 | #define __MACH_IMXFB_H__ | ||
| 4 | 6 | ||
| 5 | #include <linux/fb.h> | 7 | #include <linux/fb.h> |
| 6 | 8 | ||
| @@ -79,3 +81,4 @@ struct imx_fb_platform_data { | |||
| 79 | }; | 81 | }; |
| 80 | 82 | ||
| 81 | void set_imx_fb_info(struct imx_fb_platform_data *); | 83 | void set_imx_fb_info(struct imx_fb_platform_data *); |
| 84 | #endif /* ifndef __MACH_IMXFB_H__ */ | ||
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx50.h b/arch/arm/plat-mxc/include/mach/iomux-mx50.h new file mode 100644 index 000000000000..058a922ca147 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx50.h | |||
| @@ -0,0 +1,977 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | |||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | |||
| 14 | * You should have received a copy of the GNU General Public License along | ||
| 15 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef __MACH_IOMUX_MX50_H__ | ||
| 20 | #define __MACH_IOMUX_MX50_H__ | ||
| 21 | |||
| 22 | #include <mach/iomux-v3.h> | ||
| 23 | |||
| 24 | #define MX50_ELCDIF_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH) | ||
| 25 | |||
| 26 | #define MX50_SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ | ||
| 27 | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH) | ||
| 28 | |||
| 29 | #define MX50_UART_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE) | ||
| 30 | |||
| 31 | #define MX50_I2C_PAD_CTRL (PAD_CTL_ODE | PAD_CTL_DSE_HIGH | \ | ||
| 32 | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS) | ||
| 33 | |||
| 34 | #define MX50_USB_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ | ||
| 35 | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP) | ||
| 36 | |||
| 37 | #define MX50_FEC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ | ||
| 38 | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | \ | ||
| 39 | PAD_CTL_DSE_HIGH) | ||
| 40 | |||
| 41 | #define MX50_OWIRE_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ | ||
| 42 | PAD_CTL_PUS_100K_UP | PAD_CTL_ODE | \ | ||
| 43 | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST) | ||
| 44 | |||
| 45 | #define MX50_KEYPAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ | ||
| 46 | PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH) | ||
| 47 | |||
| 48 | #define MX50_CSPI_SS_PAD (PAD_CTL_PKE | PAD_CTL_PUE | \ | ||
| 49 | PAD_CTL_PUS_22K_UP | PAD_CTL_DSE_HIGH) | ||
| 50 | |||
| 51 | #define MX50_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x2CC, 0x20, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 52 | #define MX50_PAD_KEY_COL0__GPIO_4_0 IOMUX_PAD(0x2CC, 0x20, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 53 | #define MX50_PAD_KEY_COL0__NANDF_CLE IOMUX_PAD(0x2CC, 0x20, 2, 0x0, 0, PAD_CTL_DSE_HIGH) | ||
| 54 | |||
| 55 | #define MX50_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x2D0, 0x24, 0, 0x0, 0, MX50_KEYPAD_CTRL) | ||
| 56 | #define MX50_PAD_KEY_ROW0__GPIO_4_1 IOMUX_PAD(0x2D0, 0x24, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 57 | #define MX50_PAD_KEY_ROW0__NANDF_ALE IOMUX_PAD(0x2D0, 0x24, 2, 0x0, 0, PAD_CTL_DSE_HIGH) | ||
| 58 | |||
| 59 | #define MX50_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x2D4, 0x28, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 60 | #define MX50_PAD_KEY_COL1__GPIO_4_2 IOMUX_PAD(0x2D4, 0x28, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 61 | #define MX50_PAD_KEY_COL1__NANDF_CE0 IOMUX_PAD(0x2D4, 0x28, 2, 0x0, 0, PAD_CTL_DSE_HIGH) | ||
| 62 | |||
| 63 | #define MX50_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x2D8, 0x2C, 0, 0x0, 0, MX50_KEYPAD_CTRL) | ||
| 64 | #define MX50_PAD_KEY_ROW1__GPIO_4_3 IOMUX_PAD(0x2D8, 0x2C, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 65 | #define MX50_PAD_KEY_ROW1__NANDF_CE1 IOMUX_PAD(0x2D8, 0x2C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) | ||
| 66 | |||
| 67 | #define MX50_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x2DC, 0x30, 0, 0x0, 0, MX50_KEYPAD_CTRL) | ||
| 68 | #define MX50_PAD_KEY_COL2__GPIO_4_4 IOMUX_PAD(0x2DC, 0x30, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 69 | #define MX50_PAD_KEY_COL2__NANDF_CE2 IOMUX_PAD(0x2DC, 0x30, 2, 0x0, 0, PAD_CTL_DSE_HIGH) | ||
| 70 | |||
| 71 | #define MX50_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x2E0, 0x34, 0, 0x0, 0, MX50_KEYPAD_CTRL) | ||
| 72 | #define MX50_PAD_KEY_ROW2__GPIO_4_5 IOMUX_PAD(0x2E0, 0x34, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 73 | #define MX50_PAD_KEY_ROW2__NANDF_CE3 IOMUX_PAD(0x2E0, 0x34, 2, 0x0, 0, PAD_CTL_DSE_HIGH) | ||
| 74 | |||
| 75 | #define MX50_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x2E4, 0x38, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 76 | #define MX50_PAD_KEY_COL3__GPIO_4_6 IOMUX_PAD(0x2E4, 0x38, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 77 | #define MX50_PAD_KEY_COL3__NANDF_READY IOMUX_PAD(0x2E4, 0x38, 2, 0x7b4, 0, PAD_CTL_PKE | \ | ||
| 78 | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) | ||
| 79 | #define MX50_PAD_KEY_COL3__SDMA_EXT0 IOMUX_PAD(0x2E4, 0x38, 6, 0x7b8, 0, NO_PAD_CTRL) | ||
| 80 | |||
| 81 | #define MX50_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x2E8, 0x3C, 0, 0x0, 0, MX50_KEYPAD_CTRL) | ||
| 82 | #define MX50_PAD_KEY_ROW3__GPIO_4_7 IOMUX_PAD(0x2E8, 0x3C, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 83 | #define MX50_PAD_KEY_ROW3__NANDF_DQS IOMUX_PAD(0x2E8, 0x3C, 2, 0x7b0, 0, PAD_CTL_DSE_HIGH) | ||
| 84 | #define MX50_PAD_KEY_ROW3__SDMA_EXT1 IOMUX_PAD(0x2E8, 0x3C, 6, 0x7bc, 0, NO_PAD_CTRL) | ||
| 85 | |||
| 86 | #define MX50_PAD_I2C1_SCL__I2C1_SCL IOMUX_PAD(0x2EC, 0x40, IOMUX_CONFIG_SION, 0x0, 0, \ | ||
| 87 | MX50_I2C_PAD_CTRL) | ||
| 88 | #define MX50_PAD_I2C1_SCL__GPIO_6_18 IOMUX_PAD(0x2EC, 0x40, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 89 | #define MX50_PAD_I2C1_SCL__UART2_TXD IOMUX_PAD(0x2EC, 0x40, 2, 0x7cc, 0, MX50_UART_PAD_CTRL) | ||
| 90 | |||
| 91 | #define MX50_PAD_I2C1_SDA__I2C1_SDA IOMUX_PAD(0x2F0, 0x44, IOMUX_CONFIG_SION, 0x0, 0, \ | ||
| 92 | MX50_I2C_PAD_CTRL) | ||
| 93 | #define MX50_PAD_I2C1_SDA__GPIO_6_19 IOMUX_PAD(0x2F0, 0x44, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 94 | #define MX50_PAD_I2C1_SDA__UART2_RXD IOMUX_PAD(0x2F0, 0x44, 2, 0x7cc, 1, MX50_UART_PAD_CTRL) | ||
| 95 | |||
| 96 | #define MX50_PAD_I2C2_SCL__I2C2_SCL IOMUX_PAD(0x2F4, 0x48, IOMUX_CONFIG_SION, 0x0, 0, \ | ||
| 97 | MX50_I2C_PAD_CTRL) | ||
| 98 | #define MX50_PAD_I2C2_SCL__GPIO_6_20 IOMUX_PAD(0x2F4, 0x48, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 99 | #define MX50_PAD_I2C2_SCL__UART2_CTS IOMUX_PAD(0x2F4, 0x48, 2, 0x7c8, 0, MX50_UART_PAD_CTRL) | ||
| 100 | #define MX50_PAD_I2C2_SCL__DCDC_OK IOMUX_PAD(0x2F4, 0x48, 7, 0x0, 0, NO_PAD_CTRL) | ||
| 101 | |||
| 102 | #define MX50_PAD_I2C2_SDA__I2C2_SDA IOMUX_PAD(0x2F8, 0x4C, IOMUX_CONFIG_SION, 0x0, 0, \ | ||
| 103 | MX50_I2C_PAD_CTRL) | ||
| 104 | #define MX50_PAD_I2C2_SDA__GPIO_6_21 IOMUX_PAD(0x2F8, 0x4C, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 105 | #define MX50_PAD_I2C2_SDA__UART2_RTS IOMUX_PAD(0x2F8, 0x4C, 2, 0x7c8, 1, MX50_UART_PAD_CTRL) | ||
| 106 | #define MX50_PAD_I2C2_SDA__PWRSTABLE IOMUX_PAD(0x2F8, 0x4C, 7, 0x0, 0, NO_PAD_CTRL) | ||
| 107 | |||
| 108 | #define MX50_PAD_I2C3_SCL__I2C3_SCL IOMUX_PAD(0x2FC, 0x50, IOMUX_CONFIG_SION, 0x0, 0, \ | ||
| 109 | MX50_I2C_PAD_CTRL) | ||
| 110 | #define MX50_PAD_I2C3_SCL__GPIO_6_22 IOMUX_PAD(0x2FC, 0x50, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 111 | #define MX50_PAD_I2C3_SCL__FEC_MDC IOMUX_PAD(0x2FC, 0x50, 2, 0x0, 0, PAD_CTL_DSE_HIGH) | ||
| 112 | #define MX50_PAD_I2C3_SCL__PMIC_RDY IOMUX_PAD(0x2FC, 0x50, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 113 | #define MX50_PAD_I2C3_SCL__GPT_CAPIN1 IOMUX_PAD(0x2FC, 0x50, 5, 0x0, 0, NO_PAD_CTRL) | ||
| 114 | #define MX50_PAD_I2C3_SCL__USBOTG_OC IOMUX_PAD(0x2FC, 0x50, 7, 0x7E8, 0, MX50_USB_PAD_CTRL) | ||
| 115 | |||
| 116 | #define MX50_PAD_I2C3_SDA__I2C3_SDA IOMUX_PAD(0x300, 0x54, IOMUX_CONFIG_SION, 0x0, 0, \ | ||
| 117 | MX50_I2C_PAD_CTRL) | ||
| 118 | #define MX50_PAD_I2C3_SDA__GPIO_6_23 IOMUX_PAD(0x300, 0x54, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 119 | #define MX50_PAD_I2C3_SDA__FEC_MDIO IOMUX_PAD(0x300, 0x54, 2, 0x774, 0, MX50_FEC_PAD_CTRL) | ||
| 120 | #define MX50_PAD_I2C3_SDA__PWRFAIL_INT IOMUX_PAD(0x300, 0x54, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 121 | #define MX50_PAD_I2C3_SDA__ALARM_DEB IOMUX_PAD(0x300, 0x54, 4, 0x0, 0, NO_PAD_CTRL) | ||
| 122 | #define MX50_PAD_I2C3_SDA__GPT_CAPIN1 IOMUX_PAD(0x300, 0x54, 5, 0x0, 0, NO_PAD_CTRL) | ||
| 123 | #define MX50_PAD_I2C3_SDA__USBOTG_PWR IOMUX_PAD(0x300, 0x54, 7, 0x0, 0, \ | ||
| 124 | PAD_CTL_PKE | PAD_CTL_DSE_HIGH) | ||
| 125 | |||
| 126 | #define MX50_PAD_PWM1__PWM1_PWMO IOMUX_PAD(0x304, 0x58, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 127 | #define MX50_PAD_PWM1__GPIO_6_24 IOMUX_PAD(0x304, 0x58, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 128 | #define MX50_PAD_PWM1__USBOTG_OC IOMUX_PAD(0x304, 0x58, 2, 0x7E8, 1, MX50_USB_PAD_CTRL) | ||
| 129 | #define MX50_PAD_PWM1__GPT_CMPOUT1 IOMUX_PAD(0x304, 0x58, 5, 0x0, 0, NO_PAD_CTRL) | ||
| 130 | |||
| 131 | #define MX50_PAD_PWM2__PWM2_PWMO IOMUX_PAD(0x308, 0x5C, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 132 | #define MX50_PAD_PWM2__GPIO_6_25 IOMUX_PAD(0x308, 0x5C, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 133 | #define MX50_PAD_PWM2__USBOTG_PWR IOMUX_PAD(0x308, 0x5C, 2, 0x0, 0, \ | ||
| 134 | PAD_CTL_PKE | PAD_CTL_DSE_HIGH) | ||
| 135 | #define MX50_PAD_PWM2__DCDC_PWM IOMUX_PAD(0x308, 0x5C, 4, 0x0, 0, NO_PAD_CTRL) | ||
| 136 | #define MX50_PAD_PWM2__GPT_CMPOUT2 IOMUX_PAD(0x308, 0x5C, 5, 0x0, 0, NO_PAD_CTRL) | ||
| 137 | #define MX50_PAD_PWM2__ANY_PU_RST IOMUX_PAD(0x308, 0x5C, 7, 0x0, 0, NO_PAD_CTRL) | ||
| 138 | |||
| 139 | #define MX50_PAD_OWIRE__OWIRE IOMUX_PAD(0x30C, 0x60, 0, 0x0, 0, MX50_OWIRE_PAD_CTRL) | ||
| 140 | #define MX50_PAD_OWIRE__GPIO_6_26 IOMUX_PAD(0x30C, 0x60, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 141 | #define MX50_PAD_OWIRE__USBH1_OC IOMUX_PAD(0x30C, 0x60, 2, 0x0, 0, MX50_USB_PAD_CTRL) | ||
| 142 | #define MX50_PAD_OWIRE__SSI_EXT1_CLK IOMUX_PAD(0x30C, 0x60, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 143 | #define MX50_PAD_OWIRE__EPDC_PWRIRQ IOMUX_PAD(0x30C, 0x60, 4, 0x0, 0, NO_PAD_CTRL) | ||
| 144 | #define MX50_PAD_OWIRE__GPT_CMPOUT3 IOMUX_PAD(0x30C, 0x60, 5, 0x0, 0, NO_PAD_CTRL) | ||
| 145 | |||
| 146 | #define MX50_PAD_EPITO__EPITO IOMUX_PAD(0x310, 0x64, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 147 | #define MX50_PAD_EPITO__GPIO_6_27 IOMUX_PAD(0x310, 0x64, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 148 | #define MX50_PAD_EPITO__USBH1_PWR IOMUX_PAD(0x310, 0x64, 2, 0x0, 0, \ | ||
| 149 | PAD_CTL_PKE | PAD_CTL_DSE_HIGH) | ||
| 150 | #define MX50_PAD_EPITO__SSI_EXT2_CLK IOMUX_PAD(0x310, 0x64, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 151 | #define MX50_PAD_EPITO__TOG_EN IOMUX_PAD(0x310, 0x64, 4, 0x0, 0, NO_PAD_CTRL) | ||
| 152 | #define MX50_PAD_EPITO__GPT_CLKIN IOMUX_PAD(0x310, 0x64, 5, 0x0, 0, NO_PAD_CTRL) | ||
| 153 | |||
| 154 | #define MX50_PAD_WDOG__WDOG IOMUX_PAD(0x314, 0x68, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 155 | #define MX50_PAD_WDOG__GPIO_6_28 IOMUX_PAD(0x314, 0x68, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 156 | #define MX50_PAD_WDOG__WDOG_RST IOMUX_PAD(0x314, 0x68, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 157 | #define MX50_PAD_WDOG__XTAL32K IOMUX_PAD(0x314, 0x68, 6, 0x0, 0, NO_PAD_CTRL) | ||
| 158 | |||
| 159 | #define MX50_PAD_SSI_TXFS__SSI_TXFS IOMUX_PAD(0x318, 0x6C, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 160 | #define MX50_PAD_SSI_TXFS__GPIO_6_0 IOMUX_PAD(0x318, 0x6C, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 161 | |||
| 162 | #define MX50_PAD_SSI_TXC__SSI_TXC IOMUX_PAD(0x31C, 0x70, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 163 | #define MX50_PAD_SSI_TXC__GPIO_6_1 IOMUX_PAD(0x31C, 0x70, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 164 | |||
| 165 | #define MX50_PAD_SSI_TXD__SSI_TXD IOMUX_PAD(0x320, 0x74, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 166 | #define MX50_PAD_SSI_TXD__GPIO_6_2 IOMUX_PAD(0x320, 0x74, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 167 | #define MX50_PAD_SSI_TXD__CSPI_RDY IOMUX_PAD(0x320, 0x74, 4, 0x6e8, 0, NO_PAD_CTRL) | ||
| 168 | |||
| 169 | #define MX50_PAD_SSI_RXD__SSI_RXD IOMUX_PAD(0x324, 0x78, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 170 | #define MX50_PAD_SSI_RXD__GPIO_6_3 IOMUX_PAD(0x324, 0x78, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 171 | #define MX50_PAD_SSI_RXD__CSPI_SS3 IOMUX_PAD(0x324, 0x78, 4, 0x6f4, 0, MX50_CSPI_SS_PAD) | ||
| 172 | |||
| 173 | #define MX50_PAD_SSI_RXFS__AUD3_RXFS IOMUX_PAD(0x328, 0x7C, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 174 | #define MX50_PAD_SSI_RXFS__GPIO_6_4 IOMUX_PAD(0x328, 0x7C, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 175 | #define MX50_PAD_SSI_RXFS__UART5_TXD IOMUX_PAD(0x328, 0x7C, 2, 0x7e4, 0, MX50_UART_PAD_CTRL) | ||
| 176 | #define MX50_PAD_SSI_RXFS__WEIM_D6 IOMUX_PAD(0x328, 0x7C, 3, 0x804, 0, NO_PAD_CTRL) | ||
| 177 | #define MX50_PAD_SSI_RXFS__CSPI_SS2 IOMUX_PAD(0x328, 0x7C, 4, 0x6f0, 0, MX50_CSPI_SS_PAD) | ||
| 178 | #define MX50_PAD_SSI_RXFS__FEC_COL IOMUX_PAD(0x328, 0x7C, 5, 0x770, 0, PAD_CTL_DSE_HIGH) | ||
| 179 | #define MX50_PAD_SSI_RXFS__FEC_MDC IOMUX_PAD(0x328, 0x7C, 6, 0x0, 0, PAD_CTL_DSE_HIGH) | ||
| 180 | |||
| 181 | #define MX50_PAD_SSI_RXC__AUD3_RXC IOMUX_PAD(0x32C, 0x80, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 182 | #define MX50_PAD_SSI_RXC__GPIO_6_5 IOMUX_PAD(0x32C, 0x80, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 183 | #define MX50_PAD_SSI_RXC__UART5_RXD IOMUX_PAD(0x32C, 0x80, 2, 0x7e4, 1, MX50_UART_PAD_CTRL) | ||
| 184 | #define MX50_PAD_SSI_RXC__WEIM_D7 IOMUX_PAD(0x32C, 0x80, 3, 0x808, 0, NO_PAD_CTRL) | ||
| 185 | #define MX50_PAD_SSI_RXC__CSPI_SS1 IOMUX_PAD(0x32C, 0x80, 4, 0x6ec, 0, MX50_CSPI_SS_PAD) | ||
| 186 | #define MX50_PAD_SSI_RXC__FEC_RX_CLK IOMUX_PAD(0x32C, 0x80, 5, 0x780, 0, NO_PAD_CTRL) | ||
| 187 | #define MX50_PAD_SSI_RXC__FEC_MDIO IOMUX_PAD(0x32C, 0x80, 6, 0x774, 1, MX50_FEC_PAD_CTRL) | ||
| 188 | |||
| 189 | #define MX50_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x330, 0x84, 0, 0x7c4, 0, MX50_UART_PAD_CTRL) | ||
| 190 | #define MX50_PAD_UART1_TXD__GPIO_6_6 IOMUX_PAD(0x330, 0x84, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 191 | |||
| 192 | #define MX50_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x334, 0x88, 0, 0x7c4, 1, MX50_UART_PAD_CTRL) | ||
| 193 | #define MX50_PAD_UART1_RXD__GPIO_6_7 IOMUX_PAD(0x334, 0x88, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 194 | |||
| 195 | #define MX50_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x338, 0x8C, 0, 0x7c0, 0, MX50_UART_PAD_CTRL) | ||
| 196 | #define MX50_PAD_UART1_CTS__GPIO_6_8 IOMUX_PAD(0x338, 0x8C, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 197 | #define MX50_PAD_UART1_CTS__UART5_TXD IOMUX_PAD(0x338, 0x8C, 2, 0x7e4, 2, MX50_UART_PAD_CTRL) | ||
| 198 | #define MX50_PAD_UART1_CTS__SD4_D4 IOMUX_PAD(0x338, 0x8C, 4, 0x760, 0, MX50_SD_PAD_CTRL) | ||
| 199 | #define MX50_PAD_UART1_CTS__SD4_CMD IOMUX_PAD(0x338, 0x8C, 5, 0x74c, 0, MX50_SD_PAD_CTRL) | ||
| 200 | |||
| 201 | #define MX50_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x33C, 0x90, 0, 0x7c0, 1, MX50_UART_PAD_CTRL) | ||
| 202 | #define MX50_PAD_UART1_RTS__GPIO_6_9 IOMUX_PAD(0x33C, 0x90, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 203 | #define MX50_PAD_UART1_RTS__UART5_RXD IOMUX_PAD(0x33C, 0x90, 2, 0x7e4, 3, MX50_UART_PAD_CTRL) | ||
| 204 | #define MX50_PAD_UART1_RTS__SD4_D5 IOMUX_PAD(0x33C, 0x90, 4, 0x0, 1, MX50_SD_PAD_CTRL) | ||
| 205 | #define MX50_PAD_UART1_RTS__SD4_CLK IOMUX_PAD(0x33C, 0x90, 5, 0x0, 1, MX50_SD_PAD_CTRL) | ||
| 206 | |||
| 207 | #define MX50_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x340, 0x94, 0, 0x7cc, 2, MX50_UART_PAD_CTRL) | ||
| 208 | #define MX50_PAD_UART2_TXD__GPIO_6_10 IOMUX_PAD(0x340, 0x94, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 209 | #define MX50_PAD_UART2_TXD__SD4_D6 IOMUX_PAD(0x340, 0x94, 4, 0x768, 0, MX50_SD_PAD_CTRL) | ||
| 210 | #define MX50_PAD_UART2_TXD__SD4_D4 IOMUX_PAD(0x340, 0x94, 5, 0x760, 1, MX50_SD_PAD_CTRL) | ||
| 211 | |||
| 212 | #define MX50_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x344, 0x98, 0, 0x7cc, 3, MX50_UART_PAD_CTRL) | ||
| 213 | #define MX50_PAD_UART2_RXD__GPIO_6_11 IOMUX_PAD(0x344, 0x98, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 214 | #define MX50_PAD_UART2_RXD__SD4_D7 IOMUX_PAD(0x344, 0x98, 4, 0x76c, 0, MX50_SD_PAD_CTRL) | ||
| 215 | #define MX50_PAD_UART2_RXD__SD4_D5 IOMUX_PAD(0x344, 0x98, 5, 0x764, 1, MX50_SD_PAD_CTRL) | ||
| 216 | |||
| 217 | #define MX50_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x348, 0x9C, 0, 0x7c8, 2, MX50_UART_PAD_CTRL) | ||
| 218 | #define MX50_PAD_UART2_CTS__GPIO_6_12 IOMUX_PAD(0x348, 0x9C, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 219 | #define MX50_PAD_UART2_CTS__SD4_CMD IOMUX_PAD(0x348, 0x9C, 4, 0x74c, 1, MX50_SD_PAD_CTRL) | ||
| 220 | #define MX50_PAD_UART2_CTS__SD4_D6 IOMUX_PAD(0x348, 0x9C, 5, 0x768, 1, MX50_SD_PAD_CTRL) | ||
| 221 | |||
| 222 | #define MX50_PAD_UART2_RTS__UART2_RTS IOMUX_PAD(0x34C, 0xA0, 0, 0x7c8, 3, MX50_UART_PAD_CTRL) | ||
| 223 | #define MX50_PAD_UART2_RTS__GPIO_6_13 IOMUX_PAD(0x34C, 0xA0, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 224 | #define MX50_PAD_UART2_RTS__SD4_CLK IOMUX_PAD(0x34C, 0xA0, 4, 0x748, 1, MX50_SD_PAD_CTRL) | ||
| 225 | #define MX50_PAD_UART2_RTS__SD4_D7 IOMUX_PAD(0x34C, 0xA0, 5, 0x76c, 1, MX50_SD_PAD_CTRL) | ||
| 226 | |||
| 227 | #define MX50_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x350, 0xA4, 0, 0x7d4, 0, MX50_UART_PAD_CTRL) | ||
| 228 | #define MX50_PAD_UART3_TXD__GPIO_6_14 IOMUX_PAD(0x350, 0xA4, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 229 | #define MX50_PAD_UART3_TXD__SD1_D4 IOMUX_PAD(0x350, 0xA4, 3, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 230 | #define MX50_PAD_UART3_TXD__SD4_D0 IOMUX_PAD(0x350, 0xA4, 4, 0x750, 0, MX50_SD_PAD_CTRL) | ||
| 231 | #define MX50_PAD_UART3_TXD__SD2_WP IOMUX_PAD(0x350, 0xA4, 5, 0x744, 0, MX50_SD_PAD_CTRL) | ||
| 232 | #define MX50_PAD_UART3_TXD__WEIM_D12 IOMUX_PAD(0x350, 0xA4, 6, 0x81c, 0, NO_PAD_CTRL) | ||
| 233 | |||
| 234 | #define MX50_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x354, 0xA8, 0, 0x7d4, 1, MX50_UART_PAD_CTRL) | ||
| 235 | #define MX50_PAD_UART3_RXD__GPIO_6_15 IOMUX_PAD(0x354, 0xA8, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 236 | #define MX50_PAD_UART3_RXD__SD1_D5 IOMUX_PAD(0x354, 0xA8, 3, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 237 | #define MX50_PAD_UART3_RXD__SD4_D1 IOMUX_PAD(0x354, 0xA8, 4, 0x754, 0, MX50_SD_PAD_CTRL) | ||
| 238 | #define MX50_PAD_UART3_RXD__SD2_CD IOMUX_PAD(0x354, 0xA8, 5, 0x740, 0, MX50_SD_PAD_CTRL) | ||
| 239 | #define MX50_PAD_UART3_RXD__WEIM_D13 IOMUX_PAD(0x354, 0xA8, 6, 0x820, 0, NO_PAD_CTRL) | ||
| 240 | |||
| 241 | #define MX50_PAD_UART4_TXD__UART4_TXD IOMUX_PAD(0x358, 0xAC, 0, 0x7dc, 0, MX50_UART_PAD_CTRL) | ||
| 242 | #define MX50_PAD_UART4_TXD__GPIO_6_16 IOMUX_PAD(0x358, 0xAC, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 243 | #define MX50_PAD_UART4_TXD__UART3_CTS IOMUX_PAD(0x358, 0xAC, 2, 0x7d0, 0, MX50_UART_PAD_CTRL) | ||
| 244 | #define MX50_PAD_UART4_TXD__SD1_D6 IOMUX_PAD(0x358, 0xAC, 3, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 245 | #define MX50_PAD_UART4_TXD__SD4_D2 IOMUX_PAD(0x358, 0xAC, 4, 0x758, 0, MX50_SD_PAD_CTRL) | ||
| 246 | #define MX50_PAD_UART4_TXD__SD2_LCTL IOMUX_PAD(0x358, 0xAC, 5, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 247 | #define MX50_PAD_UART4_TXD__WEIM_D14 IOMUX_PAD(0x358, 0xAC, 6, 0x824, 0, NO_PAD_CTRL) | ||
| 248 | |||
| 249 | #define MX50_PAD_UART4_RXD__UART4_RXD IOMUX_PAD(0x35C, 0xB0, 0, 0x7dc, 1, MX50_UART_PAD_CTRL) | ||
| 250 | #define MX50_PAD_UART4_RXD__GPIO_6_17 IOMUX_PAD(0x35C, 0xB0, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 251 | #define MX50_PAD_UART4_RXD__UART3_RTS IOMUX_PAD(0x35C, 0xB0, 2, 0x7d0, 1, MX50_UART_PAD_CTRL) | ||
| 252 | #define MX50_PAD_UART4_RXD__SD1_D7 IOMUX_PAD(0x35C, 0xB0, 3, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 253 | #define MX50_PAD_UART4_RXD__SD4_D3 IOMUX_PAD(0x35C, 0xB0, 4, 0x75c, 0, MX50_SD_PAD_CTRL) | ||
| 254 | #define MX50_PAD_UART4_RXD__SD1_LCTL IOMUX_PAD(0x35C, 0xB0, 5, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 255 | #define MX50_PAD_UART4_RXD__WEIM_D15 IOMUX_PAD(0x35C, 0xB0, 6, 0x828, 0, NO_PAD_CTRL) | ||
| 256 | |||
| 257 | #define MX50_PAD_CSPI_SCLK__CSPI_SCLK IOMUX_PAD(0x360, 0xB4, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 258 | #define MX50_PAD_CSPI_SCLK__GPIO_4_8 IOMUX_PAD(0x360, 0xB4, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 259 | |||
| 260 | #define MX50_PAD_CSPI_MOSI__CSPI_MOSI IOMUX_PAD(0x364, 0xB8, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 261 | #define MX50_PAD_CSPI_MOSI__GPIO_4_9 IOMUX_PAD(0x364, 0xB8, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 262 | |||
| 263 | #define MX50_PAD_CSPI_MISO__CSPI_MISO IOMUX_PAD(0x368, 0xBC, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 264 | #define MX50_PAD_CSPI_MISO__GPIO_4_10 IOMUX_PAD(0x368, 0xBC, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 265 | |||
| 266 | #define MX50_PAD_CSPI_SS0__CSPI_SS0 IOMUX_PAD(0x36C, 0xC0, 0, 0x0, 0, MX50_CSPI_SS_PAD) | ||
| 267 | #define MX50_PAD_CSPI_SS0__GPIO_4_11 IOMUX_PAD(0x36C, 0xC0, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 268 | |||
| 269 | #define MX50_PAD_ECSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x370, 0xC4, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 270 | #define MX50_PAD_ECSPI1_SCLK__GPIO_4_12 IOMUX_PAD(0x370, 0xC4, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 271 | #define MX50_PAD_ECSPI1_SCLK__CSPI_RDY IOMUX_PAD(0x370, 0xC4, 2, 0x6e8, 1, NO_PAD_CTRL) | ||
| 272 | #define MX50_PAD_ECSPI1_SCLK__ECSPI2_RDY IOMUX_PAD(0x370, 0xC4, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 273 | #define MX50_PAD_ECSPI1_SCLK__UART3_RTS IOMUX_PAD(0x370, 0xC4, 4, 0x7d0, 2, MX50_UART_PAD_CTRL) | ||
| 274 | #define MX50_PAD_ECSPI1_SCLK__EPDC_SDCE6 IOMUX_PAD(0x370, 0xC4, 5, 0x0, 0, NO_PAD_CTRL) | ||
| 275 | #define MX50_PAD_ECSPI1_SCLK__WEIM_D8 IOMUX_PAD(0x370, 0xC4, 7, 0x80c, 0, NO_PAD_CTRL) | ||
| 276 | |||
| 277 | #define MX50_PAD_ECSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x374, 0xC8, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 278 | #define MX50_PAD_ECSPI1_MOSI__GPIO_4_13 IOMUX_PAD(0x374, 0xC8, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 279 | #define MX50_PAD_ECSPI1_MOSI__CSPI_SS1 IOMUX_PAD(0x374, 0xC8, 2, 0x6ec, 1, MX50_CSPI_SS_PAD) | ||
| 280 | #define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1 IOMUX_PAD(0x374, 0xC8, 3, 0x0, 0, MX50_CSPI_SS_PAD) | ||
| 281 | #define MX50_PAD_ECSPI1_MOSI__UART3_CTS IOMUX_PAD(0x374, 0xC8, 4, 0x7d0, 3, MX50_UART_PAD_CTRL) | ||
| 282 | #define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE7 IOMUX_PAD(0x374, 0xC8, 5, 0x0, 0, NO_PAD_CTRL) | ||
| 283 | #define MX50_PAD_ECSPI1_MOSI__WEIM_D9 IOMUX_PAD(0x374, 0xC8, 7, 0x810, 0, NO_PAD_CTRL) | ||
| 284 | |||
| 285 | #define MX50_PAD_ECSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x378, 0xCC, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 286 | #define MX50_PAD_ECSPI1_MISO__GPIO_4_14 IOMUX_PAD(0x378, 0xCC, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 287 | #define MX50_PAD_ECSPI1_MISO__CSPI_SS2 IOMUX_PAD(0x378, 0xCC, 2, 0x6f0, 1, MX50_CSPI_SS_PAD) | ||
| 288 | #define MX50_PAD_ECSPI1_MISO__ECSPI2_SS2 IOMUX_PAD(0x378, 0xCC, 3, 0x0, 0, MX50_CSPI_SS_PAD) | ||
| 289 | #define MX50_PAD_ECSPI1_MISO__UART4_RTS IOMUX_PAD(0x378, 0xCC, 4, 0x7d8, 0, MX50_UART_PAD_CTRL) | ||
| 290 | #define MX50_PAD_ECSPI1_MISO__EPDC_SDCE8 IOMUX_PAD(0x378, 0xCC, 5, 0x0, 0, NO_PAD_CTRL) | ||
| 291 | #define MX50_PAD_ECSPI1_MISO__WEIM_D10 IOMUX_PAD(0x378, 0xCC, 7, 0x814, 0, NO_PAD_CTRL) | ||
| 292 | |||
| 293 | #define MX50_PAD_ECSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x37C, 0xD0, 0, 0x0, 0, MX50_CSPI_SS_PAD) | ||
| 294 | #define MX50_PAD_ECSPI1_SS0__GPIO_4_15 IOMUX_PAD(0x37C, 0xD0, 1, 0x0, 0, PAD_CTL_PUS_100K_UP) | ||
| 295 | #define MX50_PAD_ECSPI1_SS0__CSPI_SS3 IOMUX_PAD(0x37C, 0xD0, 2, 0x6f4, 1, MX50_CSPI_SS_PAD) | ||
| 296 | #define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3 IOMUX_PAD(0x37C, 0xD0, 3, 0x0, 0, MX50_CSPI_SS_PAD) | ||
| 297 | #define MX50_PAD_ECSPI1_SS0__UART4_CTS IOMUX_PAD(0x37C, 0xD0, 4, 0x7d8, 1, MX50_UART_PAD_CTRL) | ||
| 298 | #define MX50_PAD_ECSPI1_SS0__EPDC_SDCE9 IOMUX_PAD(0x37C, 0xD0, 5, 0x0, 0, NO_PAD_CTRL) | ||
| 299 | #define MX50_PAD_ECSPI1_SS0__WEIM_D11 IOMUX_PAD(0x37C, 0xD0, 7, 0x818, 0, NO_PAD_CTRL) | ||
| 300 | |||
| 301 | #define MX50_PAD_ECSPI2_SCLK__ECSPI2_SCLK IOMUX_PAD(0x380, 0xD4, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 302 | #define MX50_PAD_ECSPI2_SCLK__GPIO_4_16 IOMUX_PAD(0x380, 0xD4, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 303 | #define MX50_PAD_ECSPI2_SCLK__ELCDIF_WR IOMUX_PAD(0x380, 0xD4, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 304 | #define MX50_PAD_ECSPI2_SCLK__ECSPI1_RDY IOMUX_PAD(0x380, 0xD4, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 305 | #define MX50_PAD_ECSPI2_SCLK__UART5_RTS IOMUX_PAD(0x380, 0xD4, 4, 0x7e0, 0, MX50_UART_PAD_CTRL) | ||
| 306 | #define MX50_PAD_ECSPI2_SCLK__ELCDIF_DOTCLK IOMUX_PAD(0x380, 0xD4, 5, 0x0, 0, NO_PAD_CTRL) | ||
| 307 | #define MX50_PAD_ECSPI2_SCLK__NANDF_CEN4 IOMUX_PAD(0x380, 0xD4, 6, 0x0, 0, NO_PAD_CTRL) | ||
| 308 | #define MX50_PAD_ECSPI2_SCLK__WEIM_D8 IOMUX_PAD(0x380, 0xD4, 7, 0x80c, 1, NO_PAD_CTRL) | ||
| 309 | |||
| 310 | #define MX50_PAD_ECSPI2_MOSI__ECSPI2_MOSI IOMUX_PAD(0x384, 0xD8, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 311 | #define MX50_PAD_ECSPI2_MOSI__GPIO_4_17 IOMUX_PAD(0x384, 0xD8, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 312 | #define MX50_PAD_ECSPI2_MOSI__ELCDIF_RD IOMUX_PAD(0x384, 0xD8, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 313 | #define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1 IOMUX_PAD(0x384, 0xD8, 3, 0x0, 0, MX50_CSPI_SS_PAD) | ||
| 314 | #define MX50_PAD_ECSPI2_MOSI__UART5_CTS IOMUX_PAD(0x384, 0xD8, 4, 0x7e0, 1, MX50_UART_PAD_CTRL) | ||
| 315 | #define MX50_PAD_ECSPI2_MOSI__ELCDIF_EN IOMUX_PAD(0x384, 0xD8, 5, 0x0, 0, NO_PAD_CTRL) | ||
| 316 | #define MX50_PAD_ECSPI2_MOSI__NANDF_CEN5 IOMUX_PAD(0x384, 0xD8, 6, 0x0, 0, NO_PAD_CTRL) | ||
| 317 | #define MX50_PAD_ECSPI2_MOSI__WEIM_D9 IOMUX_PAD(0x384, 0xD8, 7, 0x810, 1, NO_PAD_CTRL) | ||
| 318 | |||
| 319 | #define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO IOMUX_PAD(0x388, 0xDC, 0, 0x73c, 0, NO_PAD_CTRL) | ||
| 320 | #define MX50_PAD_ECSPI2_MISO__GPIO_4_18 IOMUX_PAD(0x388, 0xDC, 1, 0x0, 0, PAD_CTL_PUS_100K_UP) | ||
| 321 | #define MX50_PAD_ECSPI2_MISO__ELCDIF_RS IOMUX_PAD(0x388, 0xDC, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 322 | #define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2 IOMUX_PAD(0x388, 0xDC, 3, 0x0, 0, MX50_CSPI_SS_PAD) | ||
| 323 | #define MX50_PAD_ECSPI2_MISO__UART5_TXD IOMUX_PAD(0x388, 0xDC, 4, 0x7e4, 4, MX50_UART_PAD_CTRL) | ||
| 324 | #define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC IOMUX_PAD(0x388, 0xDC, 5, 0x0, 0, NO_PAD_CTRL) | ||
| 325 | #define MX50_PAD_ECSPI2_MISO__NANDF_CEN6 IOMUX_PAD(0x388, 0xDC, 6, 0x0, 0, NO_PAD_CTRL) | ||
| 326 | #define MX50_PAD_ECSPI2_MISO__WEIM_D10 IOMUX_PAD(0x388, 0xDC, 7, 0x814, 1, NO_PAD_CTRL) | ||
| 327 | |||
| 328 | #define MX50_PAD_ECSPI2_SS0__ECSPI2_SS0 IOMUX_PAD(0x38C, 0xE0, 0, 0x0, 0, MX50_CSPI_SS_PAD) | ||
| 329 | #define MX50_PAD_ECSPI2_SS0__GPIO_4_19 IOMUX_PAD(0x38C, 0xE0, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 330 | #define MX50_PAD_ECSPI2_SS0__ELCDIF_CS IOMUX_PAD(0x38C, 0xE0, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 331 | #define MX50_PAD_ECSPI2_SS0__ECSPI1_SS3 IOMUX_PAD(0x38C, 0xE0, 3, 0x0, 0, MX50_CSPI_SS_PAD) | ||
| 332 | #define MX50_PAD_ECSPI2_SS0__UART5_RXD IOMUX_PAD(0x38C, 0xE0, 4, 0x7e4, 5, MX50_UART_PAD_CTRL) | ||
| 333 | #define MX50_PAD_ECSPI2_SS0__ELCDIF_HSYNC IOMUX_PAD(0x38C, 0xE0, 5, 0x6f8, 0, NO_PAD_CTRL) | ||
| 334 | #define MX50_PAD_ECSPI2_SS0__NANDF_CEN7 IOMUX_PAD(0x38C, 0xE0, 6, 0x0, 0, NO_PAD_CTRL) | ||
| 335 | #define MX50_PAD_ECSPI2_SS0__WEIM_D11 IOMUX_PAD(0x38C, 0xE0, 7, 0x818, 1, NO_PAD_CTRL) | ||
| 336 | |||
| 337 | #define MX50_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x390, 0xE4, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 338 | #define MX50_PAD_SD1_CLK__GPIO_5_0 IOMUX_PAD(0x390, 0xE4, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 339 | #define MX50_PAD_SD1_CLK__CLKO IOMUX_PAD(0x390, 0xE4, 7, 0x0, 0, NO_PAD_CTRL) | ||
| 340 | |||
| 341 | #define MX50_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x394, 0xE8, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 342 | #define MX50_PAD_SD1_CMD__GPIO_5_1 IOMUX_PAD(0x394, 0xE8, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 343 | #define MX50_PAD_SD1_CMD__CLKO2 IOMUX_PAD(0x394, 0xE8, 7, 0x0, 0, NO_PAD_CTRL) | ||
| 344 | |||
| 345 | #define MX50_PAD_SD1_D0__SD1_D0 IOMUX_PAD(0x398, 0xEC, 0, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 346 | #define MX50_PAD_SD1_D0__GPIO_5_2 IOMUX_PAD(0x398, 0xEC, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 347 | #define MX50_PAD_SD1_D0__PLL1_BYP IOMUX_PAD(0x398, 0xEC, 7, 0x6dc, 0, NO_PAD_CTRL) | ||
| 348 | |||
| 349 | #define MX50_PAD_SD1_D1__SD1_D1 IOMUX_PAD(0x39C, 0xF0, 0, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 350 | #define MX50_PAD_SD1_D1__GPIO_5_3 IOMUX_PAD(0x39C, 0xF0, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 351 | #define MX50_PAD_SD1_D1__PLL2_BYP IOMUX_PAD(0x39C, 0xF0, 7, 0x6e0, 0, NO_PAD_CTRL) | ||
| 352 | |||
| 353 | #define MX50_PAD_SD1_D2__SD1_D2 IOMUX_PAD(0x3A0, 0xF4, 0, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 354 | #define MX50_PAD_SD1_D2__GPIO_5_4 IOMUX_PAD(0x3A0, 0xF4, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 355 | #define MX50_PAD_SD1_D2__PLL3_BYP IOMUX_PAD(0x3A0, 0xF4, 7, 0x6e4, 0, NO_PAD_CTRL) | ||
| 356 | |||
| 357 | #define MX50_PAD_SD1_D3__SD1_D3 IOMUX_PAD(0x3A4, 0xF8, 0, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 358 | #define MX50_PAD_SD1_D3__GPIO_5_5 IOMUX_PAD(0x3A4, 0xF8, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 359 | |||
| 360 | #define MX50_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x3A8, 0xFC, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 361 | #define MX50_PAD_SD2_CLK__GPIO_5_6 IOMUX_PAD(0x3A8, 0xFC, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 362 | #define MX50_PAD_SD2_CLK__MSHC_SCLK IOMUX_PAD(0x3A8, 0xFC, 2, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 363 | |||
| 364 | #define MX50_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x3AC, 0x100, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 365 | #define MX50_PAD_SD2_CMD__GPIO_5_7 IOMUX_PAD(0x3AC, 0x100, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 366 | #define MX50_PAD_SD2_CMD__MSHC_BS IOMUX_PAD(0x3AC, 0x100, 2, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 367 | |||
| 368 | #define MX50_PAD_SD2_D0__SD2_D0 IOMUX_PAD(0x3B0, 0x104, 0, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 369 | #define MX50_PAD_SD2_D0__GPIO_5_8 IOMUX_PAD(0x3B0, 0x104, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 370 | #define MX50_PAD_SD2_D0__MSHC_D0 IOMUX_PAD(0x3B0, 0x104, 2, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 371 | #define MX50_PAD_SD2_D0__KEY_COL4 IOMUX_PAD(0x3B0, 0x104, 3, 0x790, 0, NO_PAD_CTRL) | ||
| 372 | |||
| 373 | #define MX50_PAD_SD2_D1__SD2_D1 IOMUX_PAD(0x3B4, 0x108, 0, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 374 | #define MX50_PAD_SD2_D1__GPIO_5_9 IOMUX_PAD(0x3B4, 0x108, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 375 | #define MX50_PAD_SD2_D1__MSHC_D1 IOMUX_PAD(0x3B4, 0x108, 2, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 376 | #define MX50_PAD_SD2_D1__KEY_ROW4 IOMUX_PAD(0x3B4, 0x108, 3, 0x7a0, 0, NO_PAD_CTRL) | ||
| 377 | |||
| 378 | #define MX50_PAD_SD2_D2__SD2_D2 IOMUX_PAD(0x3B8, 0x10C, 0, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 379 | #define MX50_PAD_SD2_D2__GPIO_5_10 IOMUX_PAD(0x3B8, 0x10C, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 380 | #define MX50_PAD_SD2_D2__MSHC_D2 IOMUX_PAD(0x3B8, 0x10C, 2, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 381 | #define MX50_PAD_SD2_D2__KEY_COL5 IOMUX_PAD(0x3B8, 0x10C, 3, 0x794, 0, NO_PAD_CTRL) | ||
| 382 | |||
| 383 | #define MX50_PAD_SD2_D3__SD2_D3 IOMUX_PAD(0x3BC, 0x110, 0, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 384 | #define MX50_PAD_SD2_D3__GPIO_5_11 IOMUX_PAD(0x3BC, 0x110, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 385 | #define MX50_PAD_SD2_D3__MSHC_D3 IOMUX_PAD(0x3BC, 0x110, 2, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 386 | #define MX50_PAD_SD2_D3__KEY_ROW5 IOMUX_PAD(0x3BC, 0x110, 3, 0x7a4, 0, NO_PAD_CTRL) | ||
| 387 | |||
| 388 | #define MX50_PAD_SD2_D4__SD2_D4 IOMUX_PAD(0x3C0, 0x114, 0, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 389 | #define MX50_PAD_SD2_D4__GPIO_5_12 IOMUX_PAD(0x3C0, 0x114, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 390 | #define MX50_PAD_SD2_D4__AUD4_RXFS IOMUX_PAD(0x3C0, 0x114, 2, 0x6d0, 0, NO_PAD_CTRL) | ||
| 391 | #define MX50_PAD_SD2_D4__KEY_COL6 IOMUX_PAD(0x3C0, 0x114, 3, 0x798, 0, NO_PAD_CTRL) | ||
| 392 | #define MX50_PAD_SD2_D4__WEIM_D0 IOMUX_PAD(0x3C0, 0x114, 4, 0x7ec, 0, NO_PAD_CTRL) | ||
| 393 | #define MX50_PAD_SD2_D4__CCM_OUT0 IOMUX_PAD(0x3C0, 0x114, 7, 0x0, 0, NO_PAD_CTRL) | ||
| 394 | |||
| 395 | #define MX50_PAD_SD2_D5__SD2_D5 IOMUX_PAD(0x3C4, 0x118, 0, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 396 | #define MX50_PAD_SD2_D5__GPIO_5_13 IOMUX_PAD(0x3C4, 0x118, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 397 | #define MX50_PAD_SD2_D5__AUD4_RXC IOMUX_PAD(0x3C4, 0x118, 2, 0x6cc, 0, NO_PAD_CTRL) | ||
| 398 | #define MX50_PAD_SD2_D5__KEY_ROW6 IOMUX_PAD(0x3C4, 0x118, 3, 0x7a8, 0, NO_PAD_CTRL) | ||
| 399 | #define MX50_PAD_SD2_D5__WEIM_D1 IOMUX_PAD(0x3C4, 0x118, 4, 0x7f0, 0, NO_PAD_CTRL) | ||
| 400 | #define MX50_PAD_SD2_D5__CCM_OUT1 IOMUX_PAD(0x3C4, 0x118, 7, 0x0, 0, NO_PAD_CTRL) | ||
| 401 | |||
| 402 | #define MX50_PAD_SD2_D6__SD2_D6 IOMUX_PAD(0x3C8, 0x11C, 0, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 403 | #define MX50_PAD_SD2_D6__GPIO_5_14 IOMUX_PAD(0x3C8, 0x11C, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 404 | #define MX50_PAD_SD2_D6__AUD4_RXD IOMUX_PAD(0x3C8, 0x11C, 2, 0x6c4, 0, NO_PAD_CTRL) | ||
| 405 | #define MX50_PAD_SD2_D6__KEY_COL7 IOMUX_PAD(0x3C8, 0x11C, 3, 0x79c, 0, NO_PAD_CTRL) | ||
| 406 | #define MX50_PAD_SD2_D6__WEIM_D2 IOMUX_PAD(0x3C8, 0x11C, 4, 0x7f4, 0, NO_PAD_CTRL) | ||
| 407 | #define MX50_PAD_SD2_D6__CCM_OUT2 IOMUX_PAD(0x3C8, 0x11C, 7, 0x0, 0, NO_PAD_CTRL) | ||
| 408 | |||
| 409 | #define MX50_PAD_SD2_D7__SD2_D7 IOMUX_PAD(0x3CC, 0x120, 0, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 410 | #define MX50_PAD_SD2_D7__GPIO_5_15 IOMUX_PAD(0x3CC, 0x120, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 411 | #define MX50_PAD_SD2_D7__AUD4_TXFS IOMUX_PAD(0x3CC, 0x120, 2, 0x6d8, 0, NO_PAD_CTRL) | ||
| 412 | #define MX50_PAD_SD2_D7__KEY_ROW7 IOMUX_PAD(0x3CC, 0x120, 3, 0x7ac, 0, NO_PAD_CTRL) | ||
| 413 | #define MX50_PAD_SD2_D7__WEIM_D3 IOMUX_PAD(0x3CC, 0x120, 4, 0x7f8, 0, NO_PAD_CTRL) | ||
| 414 | #define MX50_PAD_SD2_D7__CCM_STOP IOMUX_PAD(0x3CC, 0x120, 7, 0x0, 0, NO_PAD_CTRL) | ||
| 415 | |||
| 416 | #define MX50_PAD_SD2_WP__SD2_WP IOMUX_PAD(0x3D0, 0x124, 0, 0x744, 1, MX50_SD_PAD_CTRL) | ||
| 417 | #define MX50_PAD_SD2_WP__GPIO_5_16 IOMUX_PAD(0x3D0, 0x124, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 418 | #define MX50_PAD_SD2_WP__AUD4_TXD IOMUX_PAD(0x3D0, 0x124, 2, 0x6c8, 0, NO_PAD_CTRL) | ||
| 419 | #define MX50_PAD_SD2_WP__WEIM_D4 IOMUX_PAD(0x3D0, 0x124, 4, 0x7fc, 0, NO_PAD_CTRL) | ||
| 420 | #define MX50_PAD_SD2_WP__CCM_WAIT IOMUX_PAD(0x3D0, 0x124, 7, 0x0, 0, NO_PAD_CTRL) | ||
| 421 | |||
| 422 | #define MX50_PAD_SD2_CD__SD2_CD IOMUX_PAD(0x3D4, 0x128, 0, 0x740, 1, MX50_SD_PAD_CTRL) | ||
| 423 | #define MX50_PAD_SD2_CD__GPIO_5_17 IOMUX_PAD(0x3D4, 0x128, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 424 | #define MX50_PAD_SD2_CD__AUD4_TXC IOMUX_PAD(0x3D4, 0x128, 2, 0x6d4, 0, NO_PAD_CTRL) | ||
| 425 | #define MX50_PAD_SD2_CD__WEIM_D5 IOMUX_PAD(0x3D4, 0x128, 4, 0x800, 0, NO_PAD_CTRL) | ||
| 426 | #define MX50_PAD_SD2_CD__CCM_REF_EN IOMUX_PAD(0x3D4, 0x128, 7, 0x0, 0, NO_PAD_CTRL) | ||
| 427 | |||
| 428 | #define MX50_PAD_PMIC_ON_REQ__PMIC_ON_REQ IOMUX_PAD(0x3D8, 0, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 429 | |||
| 430 | #define MX50_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ IOMUX_PAD(0x3DC, 0, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 431 | |||
| 432 | #define MX50_PAD_PMIC_PORT_B__PMIC_PORT_B IOMUX_PAD(0x3E0, 0, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 433 | |||
| 434 | #define MX50_PAD_PMIC_BOOT_MODE1__PMIC_BOOT_MODE1 IOMUX_PAD(0x3E4, 0, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 435 | |||
| 436 | #define MX50_PAD_PMIC_RESET_IN_B__PMIC_RESET_IN_B IOMUX_PAD(0x3E8, 0, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 437 | |||
| 438 | #define MX50_PAD_PMIC_BOOT_MODE0__PMIC_BOOT_MODE0 IOMUX_PAD(0x3EC, 0, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 439 | |||
| 440 | #define MX50_PAD_PMIC_TEST_MODE__PMIC_TEST_MODE IOMUX_PAD(0x3F0, 0, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 441 | |||
| 442 | #define MX50_PAD_PMIC_JTAG_TMS__PMIC_JTAG_TMS IOMUX_PAD(0x3F4, 0, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 443 | |||
| 444 | #define MX50_PAD_PMIC_JTAG_MOD__PMIC_JTAG_MOD IOMUX_PAD(0x3F8, 0, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 445 | |||
| 446 | #define MX50_PAD_PMIC_JTAG_TRSTB__PMIC_JTAG_TRSTB IOMUX_PAD(0x3FC, 0, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 447 | |||
| 448 | #define MX50_PAD_PMIC_JTAG_TDI__PMIC_JTAG_TDI IOMUX_PAD(0x400, 0, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 449 | |||
| 450 | #define MX50_PAD_PMIC_JTAG_TCK__PMIC_JTAG_TCK IOMUX_PAD(0x404, 0, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 451 | |||
| 452 | #define MX50_PAD_PMIC_JTAG_TDO__PMIC_JTAG_TDO IOMUX_PAD(0x408, 0, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 453 | |||
| 454 | #define MX50_PAD_DISP_D0__DISP_D0 IOMUX_PAD(0x40C, 0x12C, 0, 0x6fc, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 455 | #define MX50_PAD_DISP_D0__GPIO_2_0 IOMUX_PAD(0x40C, 0x12C, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 456 | #define MX50_PAD_DISP_D0__FEC_TXCLK IOMUX_PAD(0x40C, 0x12C, 2, 0x78c, 0, PAD_CTL_HYS | PAD_CTL_PKE) | ||
| 457 | |||
| 458 | #define MX50_PAD_DISP_D1__DISP_D1 IOMUX_PAD(0x410, 0x130, 0, 0x700, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 459 | #define MX50_PAD_DISP_D1__GPIO_2_1 IOMUX_PAD(0x410, 0x130, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 460 | #define MX50_PAD_DISP_D1__FEC_RX_ER IOMUX_PAD(0x410, 0x130, 2, 0x788, 0, PAD_CTL_HYS | PAD_CTL_PKE) | ||
| 461 | #define MX50_PAD_DISP_D1__WEIM_A17 IOMUX_PAD(0x410, 0x130, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 462 | |||
| 463 | #define MX50_PAD_DISP_D2__DISP_D2 IOMUX_PAD(0x414, 0x134, 0, 0x704, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 464 | #define MX50_PAD_DISP_D2__GPIO_2_2 IOMUX_PAD(0x414, 0x134, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 465 | #define MX50_PAD_DISP_D2__FEC_RX_DV IOMUX_PAD(0x414, 0x134, 2, 0x784, 0, PAD_CTL_HYS | PAD_CTL_PKE) | ||
| 466 | #define MX50_PAD_DISP_D2__WEIM_A18 IOMUX_PAD(0x414, 0x134, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 467 | |||
| 468 | #define MX50_PAD_DISP_D3__DISP_D3 IOMUX_PAD(0x418, 0x138, 0, 0x708, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 469 | #define MX50_PAD_DISP_D3__GPIO_2_3 IOMUX_PAD(0x418, 0x138, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 470 | #define MX50_PAD_DISP_D3__FEC_RXD1 IOMUX_PAD(0x418, 0x138, 2, 0x77C, 0, PAD_CTL_HYS | PAD_CTL_PKE) | ||
| 471 | #define MX50_PAD_DISP_D3__WEIM_A19 IOMUX_PAD(0x418, 0x138, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 472 | #define MX50_PAD_DISP_D3__FEC_COL IOMUX_PAD(0x418, 0x138, 4, 0x770, 1, NO_PAD_CTRL) | ||
| 473 | |||
| 474 | #define MX50_PAD_DISP_D4__DISP_D4 IOMUX_PAD(0x41C, 0x13C, 0, 0x70c, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 475 | #define MX50_PAD_DISP_D4__GPIO_2_4 IOMUX_PAD(0x41C, 0x13C, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 476 | #define MX50_PAD_DISP_D4__FEC_RXD0 IOMUX_PAD(0x41C, 0x13C, 2, 0x778, 0, PAD_CTL_HYS | PAD_CTL_PKE) | ||
| 477 | #define MX50_PAD_DISP_D4__WEIM_A20 IOMUX_PAD(0x41C, 0x13C, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 478 | |||
| 479 | #define MX50_PAD_DISP_D5__DISP_D5 IOMUX_PAD(0x420, 0x140, 0, 0x710, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 480 | #define MX50_PAD_DISP_D5__GPIO_2_5 IOMUX_PAD(0x420, 0x140, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 481 | #define MX50_PAD_DISP_D5__FEC_TX_EN IOMUX_PAD(0x420, 0x140, 2, 0x0, 0, PAD_CTL_DSE_HIGH) | ||
| 482 | #define MX50_PAD_DISP_D5__WEIM_A21 IOMUX_PAD(0x420, 0x140, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 483 | |||
| 484 | #define MX50_PAD_DISP_D6__DISP_D6 IOMUX_PAD(0x424, 0x144, 0, 0x714, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 485 | #define MX50_PAD_DISP_D6__GPIO_2_6 IOMUX_PAD(0x424, 0x144, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 486 | #define MX50_PAD_DISP_D6__FEC_TXD1 IOMUX_PAD(0x424, 0x144, 2, 0x0, 0, PAD_CTL_DSE_HIGH) | ||
| 487 | #define MX50_PAD_DISP_D6__WEIM_A22 IOMUX_PAD(0x424, 0x144, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 488 | #define MX50_PAD_DISP_D6__FEC_RX_CLK IOMUX_PAD(0x424, 0x144, 4, 0x780, 1, NO_PAD_CTRL) | ||
| 489 | |||
| 490 | #define MX50_PAD_DISP_D7__DISP_D7 IOMUX_PAD(0x428, 0x148, 0, 0x718, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 491 | #define MX50_PAD_DISP_D7__GPIO_2_7 IOMUX_PAD(0x428, 0x148, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 492 | #define MX50_PAD_DISP_D7__FEC_TXD0 IOMUX_PAD(0x428, 0x148, 2, 0x0, 0, PAD_CTL_DSE_HIGH) | ||
| 493 | #define MX50_PAD_DISP_D7__WEIM_A23 IOMUX_PAD(0x428, 0x148, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 494 | |||
| 495 | |||
| 496 | #define MX50_PAD_DISP_WR__ELCDIF_WR IOMUX_PAD(0x42C, 0x14C, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 497 | #define MX50_PAD_DISP_WR__GPIO_2_16 IOMUX_PAD(0x42C, 0x14C, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 498 | #define MX50_PAD_DISP_WR__ELCDIF_PIXCLK IOMUX_PAD(0x42C, 0x14C, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 499 | #define MX50_PAD_DISP_WR__WEIM_A24 IOMUX_PAD(0x42C, 0x14C, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 500 | |||
| 501 | #define MX50_PAD_DISP_RD__ELCDIF_RD IOMUX_PAD(0x430, 0x150, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 502 | #define MX50_PAD_DISP_RD__GPIO_2_19 IOMUX_PAD(0x430, 0x150, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 503 | #define MX50_PAD_DISP_RD__ELCDIF_EN IOMUX_PAD(0x430, 0x150, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 504 | #define MX50_PAD_DISP_RD__WEIM_A25 IOMUX_PAD(0x430, 0x150, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 505 | |||
| 506 | #define MX50_PAD_DISP_RS__ELCDIF_RS IOMUX_PAD(0x434, 0x154, 0, 0x73c, 1, MX50_ELCDIF_PAD_CTRL) | ||
| 507 | #define MX50_PAD_DISP_RS__GPIO_2_17 IOMUX_PAD(0x434, 0x154, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 508 | #define MX50_PAD_DISP_RS__ELCDIF_VSYNC IOMUX_PAD(0x434, 0x154, 2, 0x73c, 1, MX50_ELCDIF_PAD_CTRL) | ||
| 509 | #define MX50_PAD_DISP_RS__WEIM_A26 IOMUX_PAD(0x434, 0x154, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 510 | |||
| 511 | #define MX50_PAD_DISP_CS__ELCDIF_CS IOMUX_PAD(0x438, 0x158, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 512 | #define MX50_PAD_DISP_CS__GPIO_2_21 IOMUX_PAD(0x438, 0x158, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 513 | #define MX50_PAD_DISP_CS__ELCDIF_HSYNC IOMUX_PAD(0x438, 0x158, 2, 0x6f8, 1, MX50_ELCDIF_PAD_CTRL) | ||
| 514 | #define MX50_PAD_DISP_CS__WEIM_A27 IOMUX_PAD(0x438, 0x158, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 515 | #define MX50_PAD_DISP_CS__WEIM_CS3 IOMUX_PAD(0x438, 0x158, 4, 0x0, 0, NO_PAD_CTRL) | ||
| 516 | |||
| 517 | #define MX50_PAD_DISP_BUSY__ELCDIF_HSYNC IOMUX_PAD(0x43C, 0x15C, 0, 0x6f8, 2, MX50_ELCDIF_PAD_CTRL) | ||
| 518 | #define MX50_PAD_DISP_BUSY__GPIO_2_18 IOMUX_PAD(0x43C, 0x15C, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 519 | #define MX50_PAD_DISP_BUSY__WEIM_CS3 IOMUX_PAD(0x43C, 0x15C, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 520 | |||
| 521 | #define MX50_PAD_DISP_RESET__ELCDIF_RST IOMUX_PAD(0x440, 0x160, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 522 | #define MX50_PAD_DISP_RESET__GPIO_2_20 IOMUX_PAD(0x440, 0x160, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 523 | #define MX50_PAD_DISP_RESET__WEIM_CS3 IOMUX_PAD(0x440, 0x160, 4, 0x0, 0, NO_PAD_CTRL) | ||
| 524 | |||
| 525 | #define MX50_PAD_SD3_CMD__SD3_CMD IOMUX_PAD(0x444, 0x164, 0, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 526 | #define MX50_PAD_SD3_CMD__GPIO_5_18 IOMUX_PAD(0x444, 0x164, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 527 | #define MX50_PIN_SD3_CMD__NANDF_WRN IOMUX_PAD(0x444, 0x164, 2, 0x0, 0, PAD_CTL_DSE_HIGH) | ||
| 528 | #define MX50_PAD_SD3_CMD__SSP_CMD IOMUX_PAD(0x444, 0x164, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 529 | |||
| 530 | #define MX50_PAD_SD3_CLK__SD3_CLK IOMUX_PAD(0x448, 0x168, 0, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 531 | #define MX50_PAD_SD3_CLK__GPIO_5_19 IOMUX_PAD(0x448, 0x168, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 532 | #define MX50_PIN_SD3_CLK__NANDF_RDN IOMUX_PAD(0x448, 0x168, 2, 0x0, 0, PAD_CTL_DSE_HIGH) | ||
| 533 | #define MX50_PAD_SD3_CLK__SSP_CLK IOMUX_PAD(0x448, 0x168, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 534 | |||
| 535 | #define MX50_PAD_SD3_D0__SD3_D0 IOMUX_PAD(0x44C, 0x16C, 0, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 536 | #define MX50_PAD_SD3_D0__GPIO_5_20 IOMUX_PAD(0x44C, 0x16C, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 537 | #define MX50_PIN_SD3_D0__NANDF_D4 IOMUX_PAD(0x44C, 0x16C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) | ||
| 538 | #define MX50_PAD_SD3_D0__SSP_D0 IOMUX_PAD(0x44C, 0x16C, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 539 | #define MX50_PAD_SD3_D0__PLL1_BYP IOMUX_PAD(0x44C, 0x16C, 7, 0x6dc, 1, NO_PAD_CTRL) | ||
| 540 | |||
| 541 | #define MX50_PAD_SD3_D1__SD3_D1 IOMUX_PAD(0x450, 0x170, 0, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 542 | #define MX50_PAD_SD3_D1__GPIO_5_21 IOMUX_PAD(0x450, 0x170, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 543 | #define MX50_PIN_SD3_D1__NANDF_D5 IOMUX_PAD(0x450, 0x170, 2, 0x0, 0, PAD_CTL_DSE_HIGH) | ||
| 544 | #define MX50_PAD_SD3_D1__PLL2_BYP IOMUX_PAD(0x450, 0x170, 7, 0x6e0, 1, NO_PAD_CTRL) | ||
| 545 | |||
| 546 | #define MX50_PAD_SD3_D2__SD3_D2 IOMUX_PAD(0x454, 0x174, 0, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 547 | #define MX50_PAD_SD3_D2__GPIO_5_22 IOMUX_PAD(0x454, 0x174, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 548 | #define MX50_PIN_SD3_D2__NANDF_D6 IOMUX_PAD(0x454, 0x174, 2, 0x0, 0, PAD_CTL_DSE_HIGH) | ||
| 549 | #define MX50_PAD_SD3_D2__SSP_D2 IOMUX_PAD(0x454, 0x174, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 550 | #define MX50_PAD_SD3_D2__PLL3_BYP IOMUX_PAD(0x454, 0x174, 7, 0x6e4, 1, NO_PAD_CTRL) | ||
| 551 | |||
| 552 | #define MX50_PAD_SD3_D3__SD3_D3 IOMUX_PAD(0x458, 0x178, 0, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 553 | #define MX50_PAD_SD3_D3__GPIO_5_23 IOMUX_PAD(0x458, 0x178, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 554 | #define MX50_PIN_SD3_D3__NANDF_D7 IOMUX_PAD(0x458, 0x178, 2, 0x0, 0, PAD_CTL_DSE_HIGH) | ||
| 555 | #define MX50_PAD_SD3_D3__SSP_D3 IOMUX_PAD(0x458, 0x178, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 556 | |||
| 557 | #define MX50_PAD_SD3_D4__SD3_D4 IOMUX_PAD(0x45C, 0x17C, 0, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 558 | #define MX50_PAD_SD3_D4__GPIO_5_24 IOMUX_PAD(0x45C, 0x17C, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 559 | #define MX50_PIN_SD3_D4__NANDF_D0 IOMUX_PAD(0x45C, 0x17C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) | ||
| 560 | #define MX50_PAD_SD3_D4__SSP_D4 IOMUX_PAD(0x45C, 0x17C, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 561 | |||
| 562 | #define MX50_PAD_SD3_D5__SD3_D5 IOMUX_PAD(0x460, 0x180, 0, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 563 | #define MX50_PAD_SD3_D5__GPIO_5_25 IOMUX_PAD(0x460, 0x180, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 564 | #define MX50_PIN_SD3_D5__NANDF_D1 IOMUX_PAD(0x460, 0x180, 2, 0x0, 0, PAD_CTL_DSE_HIGH) | ||
| 565 | #define MX50_PAD_SD3_D5__SSP_D5 IOMUX_PAD(0x460, 0x180, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 566 | |||
| 567 | #define MX50_PAD_SD3_D6__SD3_D6 IOMUX_PAD(0x464, 0x184, 0, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 568 | #define MX50_PAD_SD3_D6__GPIO_5_26 IOMUX_PAD(0x464, 0x184, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 569 | #define MX50_PIN_SD3_D6__NANDF_D2 IOMUX_PAD(0x464, 0x184, 2, 0x0, 0, PAD_CTL_DSE_HIGH) | ||
| 570 | #define MX50_PAD_SD3_D6__SSP_D6 IOMUX_PAD(0x464, 0x184, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 571 | |||
| 572 | #define MX50_PAD_SD3_D7__SD3_D7 IOMUX_PAD(0x468, 0x188, 0, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 573 | #define MX50_PAD_SD3_D7__GPIO_5_27 IOMUX_PAD(0x468, 0x188, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 574 | #define MX50_PIN_SD3_D7__NANDF_D3 IOMUX_PAD(0x468, 0x188, 2, 0x0, 0, PAD_CTL_DSE_HIGH) | ||
| 575 | #define MX50_PAD_SD3_D7__SSP_D7 IOMUX_PAD(0x468, 0x188, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 576 | |||
| 577 | #define MX50_PAD_SD3_WP__SD3_WP IOMUX_PAD(0x46C, 0x18C, 0, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 578 | #define MX50_PAD_SD3_WP__GPIO_5_28 IOMUX_PAD(0x46C, 0x18C, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 579 | #define MX50_PIN_SD3_WP__NANDF_RESETN IOMUX_PAD(0x46C, 0x18C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) | ||
| 580 | #define MX50_PAD_SD3_WP__SSP_CD IOMUX_PAD(0x46C, 0x18C, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 581 | #define MX50_PAD_SD3_WP__SD4_LCTL IOMUX_PAD(0x46C, 0x18C, 4, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 582 | #define MX50_PAD_SD3_WP__WEIM_CS3 IOMUX_PAD(0x46C, 0x18C, 5, 0x0, 0, NO_PAD_CTRL) | ||
| 583 | |||
| 584 | #define MX50_PAD_DISP_D8__DISP_D8 IOMUX_PAD(0x470, 0x190, 0, 0x71c, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 585 | #define MX50_PAD_DISP_D8__GPIO_2_8 IOMUX_PAD(0x470, 0x190, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 586 | #define MX50_PAD_DISP_D8__NANDF_CLE IOMUX_PAD(0x470, 0x190, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 587 | #define MX50_PAD_DISP_D8__SD1_LCTL IOMUX_PAD(0x470, 0x190, 3, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 588 | #define MX50_PAD_DISP_D8__SD4_CMD IOMUX_PAD(0x470, 0x190, 4, 0x74c, 2, MX50_SD_PAD_CTRL) | ||
| 589 | #define MX50_PAD_DISP_D8__KEY_COL4 IOMUX_PAD(0x470, 0x190, 5, 0x790, 1, NO_PAD_CTRL) | ||
| 590 | #define MX50_PAD_DISP_D8__FEC_TX_CLK IOMUX_PAD(0x470, 0x190, 6, 0x78c, 1, NO_PAD_CTRL) | ||
| 591 | |||
| 592 | #define MX50_PAD_DISP_D9__DISP_D9 IOMUX_PAD(0x474, 0x194, 0, 0x720, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 593 | #define MX50_PAD_DISP_D9__GPIO_2_9 IOMUX_PAD(0x474, 0x194, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 594 | #define MX50_PAD_DISP_D9__NANDF_ALE IOMUX_PAD(0x474, 0x194, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 595 | #define MX50_PAD_DISP_D9__SD2_LCTL IOMUX_PAD(0x474, 0x194, 3, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 596 | #define MX50_PAD_DISP_D9__SD4_CLK IOMUX_PAD(0x474, 0x194, 4, 0x748, 2, MX50_SD_PAD_CTRL) | ||
| 597 | #define MX50_PAD_DISP_D9__KEY_ROW4 IOMUX_PAD(0x474, 0x194, 5, 0x7a0, 1, NO_PAD_CTRL) | ||
| 598 | #define MX50_PAD_DISP_D9__FEC_RX_ER IOMUX_PAD(0x474, 0x194, 6, 0x788, 1, NO_PAD_CTRL) | ||
| 599 | |||
| 600 | #define MX50_PAD_DISP_D10__DISP_D10 IOMUX_PAD(0x478, 0x198, 0, 0x724, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 601 | #define MX50_PAD_DISP_D10__GPIO_2_10 IOMUX_PAD(0x478, 0x198, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 602 | #define MX50_PAD_DISP_D10__NANDF_CEN0 IOMUX_PAD(0x478, 0x198, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 603 | #define MX50_PAD_DISP_D10__SD3_LCTL IOMUX_PAD(0x478, 0x198, 3, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 604 | #define MX50_PAD_DISP_D10__SD4_D0 IOMUX_PAD(0x478, 0x198, 4, 0x750, 1, MX50_SD_PAD_CTRL) | ||
| 605 | #define MX50_PAD_DISP_D10__KEY_COL5 IOMUX_PAD(0x478, 0x198, 5, 0x794, 1, NO_PAD_CTRL) | ||
| 606 | #define MX50_PAD_DISP_D10__FEC_RX_DV IOMUX_PAD(0x478, 0x198, 6, 0x784, 1, NO_PAD_CTRL) | ||
| 607 | |||
| 608 | #define MX50_PAD_DISP_D11__DISP_D11 IOMUX_PAD(0x47C, 0x19C, 0, 0x728, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 609 | #define MX50_PAD_DISP_D11__GPIO_2_11 IOMUX_PAD(0x47C, 0x19C, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 610 | #define MX50_PAD_DISP_D11__NANDF_CEN1 IOMUX_PAD(0x47C, 0x19C, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 611 | #define MX50_PAD_DISP_D11__SD4_D1 IOMUX_PAD(0x47C, 0x19C, 4, 0x754, 1, MX50_SD_PAD_CTRL) | ||
| 612 | #define MX50_PAD_DISP_D11__KEY_ROW5 IOMUX_PAD(0x47C, 0x19C, 5, 0x7a4, 1, NO_PAD_CTRL) | ||
| 613 | #define MX50_PAD_DISP_D11__FEC_RDAT1 IOMUX_PAD(0x47C, 0x19C, 6, 0x77c, 1, NO_PAD_CTRL) | ||
| 614 | |||
| 615 | #define MX50_PAD_DISP_D12__DISP_D12 IOMUX_PAD(0x480, 0x1A0, 0, 0x72c, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 616 | #define MX50_PAD_DISP_D12__GPIO_2_12 IOMUX_PAD(0x480, 0x1A0, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 617 | #define MX50_PAD_DISP_D12__NANDF_CEN2 IOMUX_PAD(0x480, 0x1A0, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 618 | #define MX50_PAD_DISP_D12__SD1_CD IOMUX_PAD(0x480, 0x1A0, 3, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 619 | #define MX50_PAD_DISP_D12__SD4_D2 IOMUX_PAD(0x480, 0x1A0, 4, 0x758, 1, MX50_SD_PAD_CTRL) | ||
| 620 | #define MX50_PAD_DISP_D12__KEY_COL6 IOMUX_PAD(0x480, 0x1A0, 5, 0x798, 1, NO_PAD_CTRL) | ||
| 621 | #define MX50_PAD_DISP_D12__FEC_RDAT0 IOMUX_PAD(0x480, 0x1A0, 6, 0x778, 1, NO_PAD_CTRL) | ||
| 622 | |||
| 623 | #define MX50_PAD_DISP_D13__DISP_D13 IOMUX_PAD(0x484, 0x1A4, 0, 0x730, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 624 | #define MX50_PAD_DISP_D13__GPIO_2_13 IOMUX_PAD(0x484, 0x1A4, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 625 | #define MX50_PAD_DISP_D13__NANDF_CEN3 IOMUX_PAD(0x484, 0x1A4, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 626 | #define MX50_PAD_DISP_D13__SD3_CD IOMUX_PAD(0x484, 0x1A4, 3, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 627 | #define MX50_PAD_DISP_D13__SD4_D3 IOMUX_PAD(0x484, 0x1A4, 4, 0x75c, 1, MX50_SD_PAD_CTRL) | ||
| 628 | #define MX50_PAD_DISP_D13__KEY_ROW6 IOMUX_PAD(0x484, 0x1A4, 5, 0x7a8, 1, NO_PAD_CTRL) | ||
| 629 | #define MX50_PAD_DISP_D13__FEC_TX_EN IOMUX_PAD(0x484, 0x1A4, 6, 0x0, 0, NO_PAD_CTRL) | ||
| 630 | |||
| 631 | #define MX50_PAD_DISP_D14__DISP_D14 IOMUX_PAD(0x488, 0x1A8, 0, 0x734, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 632 | #define MX50_PAD_DISP_D14__GPIO_2_14 IOMUX_PAD(0x488, 0x1A8, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 633 | #define MX50_PAD_DISP_D14__NANDF_RDY0 IOMUX_PAD(0x488, 0x1A8, 2, 0x7b4, 1, NO_PAD_CTRL) | ||
| 634 | #define MX50_PAD_DISP_D14__SD1_WP IOMUX_PAD(0x488, 0x1A8, 3, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 635 | #define MX50_PAD_DISP_D14__SD4_WP IOMUX_PAD(0x488, 0x1A8, 4, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 636 | #define MX50_PAD_DISP_D14__KEY_COL7 IOMUX_PAD(0x488, 0x1A8, 5, 0x79c, 1, NO_PAD_CTRL) | ||
| 637 | #define MX50_PAD_DISP_D14__FEC_TDAT1 IOMUX_PAD(0x488, 0x1A8, 6, 0x0, 0, NO_PAD_CTRL) | ||
| 638 | |||
| 639 | #define MX50_PAD_DISP_D15__DISP_D15 IOMUX_PAD(0x48C, 0x1AC, 0, 0x738, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 640 | #define MX50_PAD_DISP_D15__GPIO_2_15 IOMUX_PAD(0x48C, 0x1AC, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 641 | #define MX50_PAD_DISP_D15__NANDF_DQS IOMUX_PAD(0x48C, 0x1AC, 2, 0x7b0, 1, NO_PAD_CTRL) | ||
| 642 | #define MX50_PAD_DISP_D15__SD3_RST IOMUX_PAD(0x48C, 0x1AC, 3, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 643 | #define MX50_PAD_DISP_D15__SD4_CD IOMUX_PAD(0x48C, 0x1AC, 4, 0x0, 0, MX50_SD_PAD_CTRL) | ||
| 644 | #define MX50_PAD_DISP_D15__KEY_ROW7 IOMUX_PAD(0x48C, 0x1AC, 5, 0x7ac, 1, NO_PAD_CTRL) | ||
| 645 | #define MX50_PAD_DISP_D15__FEC_TDAT0 IOMUX_PAD(0x48C, 0x1AC, 6, 0x0, 0, NO_PAD_CTRL) | ||
| 646 | |||
| 647 | #define MX50_PAD_EPDC_D0__EPDC_D0 IOMUX_PAD(0x54C, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 648 | #define MX50_PAD_EPDC_D0__GPIO_3_0 IOMUX_PAD(0x54C, 0x1B0, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 649 | #define MX50_PAD_EPDC_D0__WEIM_D0 IOMUX_PAD(0x54C, 0x1B0, 2, 0x7ec, 1, NO_PAD_CTRL) | ||
| 650 | #define MX50_PAD_EPDC_D0__ELCDIF_RS IOMUX_PAD(0x54C, 0x1B0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 651 | #define MX50_PAD_EPDC_D0__ELCDIF_PIXCLK IOMUX_PAD(0x54C, 0x1B0, 4, 0x0, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 652 | |||
| 653 | #define MX50_PAD_EPDC_D1__EPDC_D1 IOMUX_PAD(0x550, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 654 | #define MX50_PAD_EPDC_D1__GPIO_3_1 IOMUX_PAD(0x550, 0x1B4, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 655 | #define MX50_PAD_EPDC_D1__WEIM_D1 IOMUX_PAD(0x550, 0x1B4, 2, 0x7f0, 1, NO_PAD_CTRL) | ||
| 656 | #define MX50_PAD_EPDC_D1__ELCDIF_CS IOMUX_PAD(0x550, 0x1B4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 657 | #define MX50_PAD_EPDC_D1__ELCDIF_EN IOMUX_PAD(0x550, 0x1B4, 4, 0x0, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 658 | |||
| 659 | #define MX50_PAD_EPDC_D2__EPDC_D2 IOMUX_PAD(0x554, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 660 | #define MX50_PAD_EPDC_D2__GPIO_3_2 IOMUX_PAD(0x554, 0x1B8, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 661 | #define MX50_PAD_EPDC_D2__WEIM_D2 IOMUX_PAD(0x554, 0x1B8, 2, 0x7f4, 1, NO_PAD_CTRL) | ||
| 662 | #define MX50_PAD_EPDC_D2__ELCDIF_WR IOMUX_PAD(0x554, 0x1B8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 663 | #define MX50_PAD_EPDC_D2__ELCDIF_VSYNC IOMUX_PAD(0x554, 0x1B8, 4, 0x73c, 2, MX50_ELCDIF_PAD_CTRL) | ||
| 664 | |||
| 665 | #define MX50_PAD_EPDC_D3__EPDC_D3 IOMUX_PAD(0x558, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 666 | #define MX50_PAD_EPDC_D3__GPIO_3_3 IOMUX_PAD(0x558, 0x1BC, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 667 | #define MX50_PAD_EPDC_D3__WEIM_D3 IOMUX_PAD(0x558, 0x1BC, 2, 0x7f8, 1, NO_PAD_CTRL) | ||
| 668 | #define MX50_PAD_EPDC_D3__ELCDIF_RD IOMUX_PAD(0x558, 0x1BC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 669 | #define MX50_PAD_EPDC_D3__ELCDIF_HSYNC IOMUX_PAD(0x558, 0x1BC, 4, 0x6f8, 3, MX50_ELCDIF_PAD_CTRL) | ||
| 670 | |||
| 671 | #define MX50_PAD_EPDC_D4__EPDC_D4 IOMUX_PAD(0x55C, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 672 | #define MX50_PAD_EPDC_D4__GPIO_3_4 IOMUX_PAD(0x55C, 0x1C0, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 673 | #define MX50_PAD_EPDC_D4__WEIM_D4 IOMUX_PAD(0x55C, 0x1C0, 2, 0x7fc, 1, NO_PAD_CTRL) | ||
| 674 | |||
| 675 | #define MX50_PAD_EPDC_D5__EPDC_D5 IOMUX_PAD(0x560, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 676 | #define MX50_PAD_EPDC_D5__GPIO_3_5 IOMUX_PAD(0x560, 0x1C4, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 677 | #define MX50_PAD_EPDC_D5__WEIM_D5 IOMUX_PAD(0x560, 0x1C4, 2, 0x800, 1, NO_PAD_CTRL) | ||
| 678 | |||
| 679 | #define MX50_PAD_EPDC_D6__EPDC_D6 IOMUX_PAD(0x564, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 680 | #define MX50_PAD_EPDC_D6__GPIO_3_6 IOMUX_PAD(0x564, 0x1C8, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 681 | #define MX50_PAD_EPDC_D6__WEIM_D6 IOMUX_PAD(0x564, 0x1C8, 2, 0x804, 1, NO_PAD_CTRL) | ||
| 682 | |||
| 683 | #define MX50_PAD_EPDC_D7__EPDC_D7 IOMUX_PAD(0x568, 0x1CC, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 684 | #define MX50_PAD_EPDC_D7__GPIO_3_7 IOMUX_PAD(0x568, 0x1CC, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 685 | #define MX50_PAD_EPDC_D7__WEIM_D7 IOMUX_PAD(0x568, 0x1CC, 2, 0x808, 1, NO_PAD_CTRL) | ||
| 686 | |||
| 687 | #define MX50_PAD_EPDC_D8__EPDC_D8 IOMUX_PAD(0x56C, 0x1D0, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 688 | #define MX50_PAD_EPDC_D8__GPIO_3_8 IOMUX_PAD(0x56C, 0x1D0, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 689 | #define MX50_PAD_EPDC_D8__WEIM_D8 IOMUX_PAD(0x56C, 0x1D0, 2, 0x80c, 2, NO_PAD_CTRL) | ||
| 690 | #define MX50_PAD_EPDC_D8__ELCDIF_D24 IOMUX_PAD(0x56C, 0x1D0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 691 | |||
| 692 | #define MX50_PAD_EPDC_D9__EPDC_D9 IOMUX_PAD(0x570, 0x1D4, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 693 | #define MX50_PAD_EPDC_D9__GPIO_3_9 IOMUX_PAD(0x570, 0x1D4, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 694 | #define MX50_PAD_EPDC_D9__WEIM_D9 IOMUX_PAD(0x570, 0x1D4, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 695 | #define MX50_PAD_EPDC_D9__ELCDIF_D25 IOMUX_PAD(0x570, 0x1D4, 3, 0x810, 2, MX50_ELCDIF_PAD_CTRL) | ||
| 696 | |||
| 697 | #define MX50_PAD_EPDC_D10__EPDC_D10 IOMUX_PAD(0x574, 0x1D8, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 698 | #define MX50_PAD_EPDC_D10__GPIO_3_10 IOMUX_PAD(0x574, 0x1D8, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 699 | #define MX50_PAD_EPDC_D10__WEIM_D10 IOMUX_PAD(0x574, 0x1D8, 2, 0x814, 2, NO_PAD_CTRL) | ||
| 700 | #define MX50_PAD_EPDC_D10__ELCDIF_D26 IOMUX_PAD(0x574, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 701 | |||
| 702 | #define MX50_PAD_EPDC_D11__EPDC_D11 IOMUX_PAD(0x578, 0x1DC, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 703 | #define MX50_PAD_EPDC_D11__GPIO_3_11 IOMUX_PAD(0x578, 0x1DC, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 704 | #define MX50_PAD_EPDC_D11__WEIM_D11 IOMUX_PAD(0x578, 0x1DC, 2, 0x818, 2, NO_PAD_CTRL) | ||
| 705 | #define MX50_PAD_EPDC_D11__ELCDIF_D27 IOMUX_PAD(0x578, 0x1DC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 706 | |||
| 707 | #define MX50_PAD_EPDC_D12__EPDC_D12 IOMUX_PAD(0x57C, 0x1E0, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 708 | #define MX50_PAD_EPDC_D12__GPIO_3_12 IOMUX_PAD(0x57C, 0x1E0, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 709 | #define MX50_PAD_EPDC_D12__WEIM_D12 IOMUX_PAD(0x57C, 0x1E0, 2, 0x81c, 1, NO_PAD_CTRL) | ||
| 710 | #define MX50_PAD_EPDC_D12__ELCDIF_D28 IOMUX_PAD(0x57C, 0x1E0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 711 | |||
| 712 | #define MX50_PAD_EPDC_D13__EPDC_D13 IOMUX_PAD(0x580, 0x1E4, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 713 | #define MX50_PAD_EPDC_D13__GPIO_3_13 IOMUX_PAD(0x580, 0x1E4, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 714 | #define MX50_PAD_EPDC_D13__WEIM_D13 IOMUX_PAD(0x580, 0x1E4, 2, 0x820, 1, NO_PAD_CTRL) | ||
| 715 | #define MX50_PAD_EPDC_D13__ELCDIF_D29 IOMUX_PAD(0x580, 0x1E4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 716 | |||
| 717 | #define MX50_PAD_EPDC_D14__EPDC_D14 IOMUX_PAD(0x584, 0x1E8, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 718 | #define MX50_PAD_EPDC_D14__GPIO_3_14 IOMUX_PAD(0x584, 0x1E8, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 719 | #define MX50_PAD_EPDC_D14__WEIM_D14 IOMUX_PAD(0x584, 0x1E8, 2, 0x824, 1, NO_PAD_CTRL) | ||
| 720 | #define MX50_PAD_EPDC_D14__ELCDIF_D30 IOMUX_PAD(0x584, 0x1E8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 721 | #define MX50_PAD_EPDC_D14__AUD6_TXD IOMUX_PAD(0x584, 0x1E8, 4, 0x0, 0, NO_PAD_CTRL) | ||
| 722 | |||
| 723 | #define MX50_PAD_EPDC_D15__EPDC_D15 IOMUX_PAD(0x588, 0x1EC, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 724 | #define MX50_PAD_EPDC_D15__GPIO_3_15 IOMUX_PAD(0x588, 0x1EC, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 725 | #define MX50_PAD_EPDC_D15__WEIM_D15 IOMUX_PAD(0x588, 0x1EC, 2, 0x828, 1, NO_PAD_CTRL) | ||
| 726 | #define MX50_PAD_EPDC_D15__ELCDIF_D31 IOMUX_PAD(0x588, 0x1EC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 727 | #define MX50_PAD_EPDC_D15__AUD6_TXC IOMUX_PAD(0x588, 0x1EC, 4, 0x0, 0, NO_PAD_CTRL) | ||
| 728 | |||
| 729 | #define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK IOMUX_PAD(0x58C, 0x1F0, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 730 | #define MX50_PAD_EPDC_GDCLK__GPIO_3_16 IOMUX_PAD(0x58C, 0x1F0, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 731 | #define MX50_PAD_EPDC_GDCLK__WEIM_D16 IOMUX_PAD(0x58C, 0x1F0, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 732 | #define MX50_PAD_EPDC_GDCLK__ELCDIF_D16 IOMUX_PAD(0x58C, 0x1F0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 733 | #define MX50_PAD_EPDC_GDCLK__AUD6_TXFS IOMUX_PAD(0x58C, 0x1F0, 4, 0x0, 0, NO_PAD_CTRL) | ||
| 734 | |||
| 735 | #define MX50_PAD_EPDC_GDSP__EPDC_GDSP IOMUX_PAD(0x590, 0x1F4, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 736 | #define MX50_PAD_EPDC_GDSP__GPIO_3_17 IOMUX_PAD(0x590, 0x1F4, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 737 | #define MX50_PAD_EPDC_GDSP__WEIM_D17 IOMUX_PAD(0x590, 0x1F4, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 738 | #define MX50_PAD_EPDC_GDSP__ELCDIF_D17 IOMUX_PAD(0x590, 0x1F4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 739 | #define MX50_PAD_EPDC_GDSP__AUD6_RXD IOMUX_PAD(0x590, 0x1F4, 4, 0x0, 0, NO_PAD_CTRL) | ||
| 740 | |||
| 741 | #define MX50_PAD_EPDC_GDOE__EPDC_GDOE IOMUX_PAD(0x594, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 742 | #define MX50_PAD_EPDC_GDOE__GPIO_3_18 IOMUX_PAD(0x594, 0x1F8, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 743 | #define MX50_PAD_EPDC_GDOE__WEIM_D18 IOMUX_PAD(0x594, 0x1F8, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 744 | #define MX50_PAD_EPDC_GDOE__ELCDIF_D18 IOMUX_PAD(0x594, 0x1F8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 745 | #define MX50_PAD_EPDC_GDOE__AUD6_RXC IOMUX_PAD(0x594, 0x1F8, 4, 0x0, 0, NO_PAD_CTRL) | ||
| 746 | |||
| 747 | #define MX50_PAD_EPDC_GDRL__EPDC_GDRL IOMUX_PAD(0x598, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 748 | #define MX50_PAD_EPDC_GDRL__GPIO_3_19 IOMUX_PAD(0x598, 0x1FC, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 749 | #define MX50_PAD_EPDC_GDRL__WEIM_D19 IOMUX_PAD(0x598, 0x1FC, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 750 | #define MX50_PAD_EPDC_GDRL__ELCDIF_D19 IOMUX_PAD(0x598, 0x1FC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 751 | #define MX50_PAD_EPDC_GDRL__AUD6_RXFS IOMUX_PAD(0x598, 0x1FC, 4, 0x0, 0, NO_PAD_CTRL) | ||
| 752 | |||
| 753 | #define MX50_PAD_EPDC_SDCLK__EPDC_SDCLK IOMUX_PAD(0x59C, 0x200, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 754 | #define MX50_PAD_EPDC_SDCLK__GPIO_3_20 IOMUX_PAD(0x59C, 0x200, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 755 | #define MX50_PAD_EPDC_SDCLK__WEIM_D20 IOMUX_PAD(0x59C, 0x200, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 756 | #define MX50_PAD_EPDC_SDCLK__ELCDIF_D20 IOMUX_PAD(0x59C, 0x200, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 757 | #define MX50_PAD_EPDC_SDCLK__AUD5_TXD IOMUX_PAD(0x59C, 0x200, 4, 0x0, 0, NO_PAD_CTRL) | ||
| 758 | |||
| 759 | #define MX50_PAD_EPDC_SDOEZ__EPDC_SDOEZ IOMUX_PAD(0x5A0, 0x204, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 760 | #define MX50_PAD_EPDC_SDOEZ__GPIO_3_21 IOMUX_PAD(0x5A0, 0x204, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 761 | #define MX50_PAD_EPDC_SDOEZ__WEIM_D21 IOMUX_PAD(0x5A0, 0x204, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 762 | #define MX50_PAD_EPDC_SDOEZ__ELCDIF_D21 IOMUX_PAD(0x5A0, 0x204, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 763 | #define MX50_PAD_EPDC_SDOEZ__AUD5_TXC IOMUX_PAD(0x5A0, 0x204, 4, 0x0, 0, NO_PAD_CTRL) | ||
| 764 | |||
| 765 | #define MX50_PAD_EPDC_SDOED__EPDC_SDOED IOMUX_PAD(0x5A4, 0x208, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 766 | #define MX50_PAD_EPDC_SDOED__GPIO_3_22 IOMUX_PAD(0x5A4, 0x208, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 767 | #define MX50_PAD_EPDC_SDOED__WEIM_D22 IOMUX_PAD(0x5A4, 0x208, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 768 | #define MX50_PAD_EPDC_SDOED__ELCDIF_D22 IOMUX_PAD(0x5A4, 0x208, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 769 | #define MX50_PAD_EPDC_SDOED__AUD5_TXFS IOMUX_PAD(0x5A4, 0x208, 4, 0x0, 0, NO_PAD_CTRL) | ||
| 770 | |||
| 771 | #define MX50_PAD_EPDC_SDOE__EPDC_SDOE IOMUX_PAD(0x5A8, 0x20C, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 772 | #define MX50_PAD_EPDC_SDOE__GPIO_3_23 IOMUX_PAD(0x5A8, 0x20C, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 773 | #define MX50_PAD_EPDC_SDOE__WEIM_D23 IOMUX_PAD(0x5A8, 0x20C, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 774 | #define MX50_PAD_EPDC_SDOE__ELCDIF_D23 IOMUX_PAD(0x5A8, 0x20C, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL) | ||
| 775 | #define MX50_PAD_EPDC_SDOE__AUD5_RXD IOMUX_PAD(0x5A8, 0x20C, 4, 0x0, 0, NO_PAD_CTRL) | ||
| 776 | |||
| 777 | #define MX50_PAD_EPDC_SDLE__EPDC_SDLE IOMUX_PAD(0x5AC, 0x210, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 778 | #define MX50_PAD_EPDC_SDLE__GPIO_3_24 IOMUX_PAD(0x5AC, 0x210, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 779 | #define MX50_PAD_EPDC_SDLE__WEIM_D24 IOMUX_PAD(0x5AC, 0x210, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 780 | #define MX50_PAD_EPDC_SDLE__ELCDIF_D8 IOMUX_PAD(0x5AC, 0x210, 3, 0x71c, 1, MX50_ELCDIF_PAD_CTRL) | ||
| 781 | #define MX50_PAD_EPDC_SDLE__AUD5_RXC IOMUX_PAD(0x5AC, 0x210, 4, 0x0, 0, NO_PAD_CTRL) | ||
| 782 | |||
| 783 | #define MX50_PAD_EPDC_SDCLKN__EPDC_SDCLKN IOMUX_PAD(0x5B0, 0x214, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 784 | #define MX50_PAD_EPDC_SDCLKN__GPIO_3_25 IOMUX_PAD(0x5B0, 0x214, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 785 | #define MX50_PAD_EPDC_SDCLKN__WEIM_D25 IOMUX_PAD(0x5B0, 0x214, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 786 | #define MX50_PAD_EPDC_SDCLKN__ELCDIF_D9 IOMUX_PAD(0x5B0, 0x214, 3, 0x720, 1, MX50_ELCDIF_PAD_CTRL) | ||
| 787 | #define MX50_PAD_EPDC_SDCLKN__AUD5_RXFS IOMUX_PAD(0x5B0, 0x214, 4, 0x0, 0, NO_PAD_CTRL) | ||
| 788 | |||
| 789 | #define MX50_PAD_EPDC_SDSHR__EPDC_SDSHR IOMUX_PAD(0x5B4, 0x218, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 790 | #define MX50_PAD_EPDC_SDSHR__GPIO_3_26 IOMUX_PAD(0x5B4, 0x218, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 791 | #define MX50_PAD_EPDC_SDSHR__WEIM_D26 IOMUX_PAD(0x5B4, 0x218, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 792 | #define MX50_PAD_EPDC_SDSHR__ELCDIF_D10 IOMUX_PAD(0x5B4, 0x218, 3, 0x724, 1, MX50_ELCDIF_PAD_CTRL) | ||
| 793 | #define MX50_PAD_EPDC_SDSHR__AUD4_TXD IOMUX_PAD(0x5B4, 0x218, 4, 0x6c8, 1, NO_PAD_CTRL) | ||
| 794 | |||
| 795 | #define MX50_PAD_EPDC_PWRCOM__EPDC_PWRCOM IOMUX_PAD(0x5B8, 0x21C, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 796 | #define MX50_PAD_EPDC_PWRCOM__GPIO_3_27 IOMUX_PAD(0x5B8, 0x21C, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 797 | #define MX50_PAD_EPDC_PWRCOM__WEIM_D27 IOMUX_PAD(0x5B8, 0x21C, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 798 | #define MX50_PAD_EPDC_PWRCOM__ELCDIF_D11 IOMUX_PAD(0x5B8, 0x21C, 3, 0x728, 1, MX50_ELCDIF_PAD_CTRL) | ||
| 799 | #define MX50_PAD_EPDC_PWRCOM__AUD4_TXC IOMUX_PAD(0x5B8, 0x21C, 4, 0x6d4, 1, NO_PAD_CTRL) | ||
| 800 | |||
| 801 | #define MX50_PAD_EPDC_PWRSTAT__EPDC_PWRSTAT IOMUX_PAD(0x5BC, 0x220, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 802 | #define MX50_PAD_EPDC_PWRSTAT__GPIO_3_28 IOMUX_PAD(0x5BC, 0x220, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 803 | #define MX50_PAD_EPDC_PWRSTAT__WEIM_D28 IOMUX_PAD(0x5BC, 0x220, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 804 | #define MX50_PAD_EPDC_PWRSTAT__ELCDIF_D12 IOMUX_PAD(0x5BC, 0x220, 3, 0x72c, 1, MX50_ELCDIF_PAD_CTRL) | ||
| 805 | #define MX50_PAD_EPDC_PWRSTAT__AUD4_TXFS IOMUX_PAD(0x5BC, 0x220, 4, 0x6d8, 1, NO_PAD_CTRL) | ||
| 806 | |||
| 807 | #define MX50_PAD_EPDC_PWRCTRL0__EPDC_PWRCTRL0 IOMUX_PAD(0x5C0, 0x224, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 808 | #define MX50_PAD_EPDC_PWRCTRL0__GPIO_3_29 IOMUX_PAD(0x5C0, 0x224, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 809 | #define MX50_PAD_EPDC_PWRCTRL0__WEIM_D29 IOMUX_PAD(0x5C0, 0x224, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 810 | #define MX50_PAD_EPDC_PWRCTRL0__ELCDIF_D13 IOMUX_PAD(0x5C0, 0x224, 3, 0x730, 1, MX50_ELCDIF_PAD_CTRL) | ||
| 811 | #define MX50_PAD_EPDC_PWRCTRL0__AUD4_RXD IOMUX_PAD(0x5C0, 0x224, 4, 0x6c4, 1, NO_PAD_CTRL) | ||
| 812 | |||
| 813 | #define MX50_PAD_EPDC_PWRCTRL1__EPDC_PWRCTRL1 IOMUX_PAD(0x5C4, 0x228, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 814 | #define MX50_PAD_EPDC_PWRCTRL1__GPIO_3_30 IOMUX_PAD(0x5C4, 0x228, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 815 | #define MX50_PAD_EPDC_PWRCTRL1__WEIM_D30 IOMUX_PAD(0x5C4, 0x228, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 816 | #define MX50_PAD_EPDC_PWRCTRL1__ELCDIF_D14 IOMUX_PAD(0x5C4, 0x228, 3, 0x734, 1, MX50_ELCDIF_PAD_CTRL) | ||
| 817 | #define MX50_PAD_EPDC_PWRCTRL1__AUD4_RXC IOMUX_PAD(0x5C4, 0x228, 4, 0x6cc, 1, NO_PAD_CTRL) | ||
| 818 | |||
| 819 | #define MX50_PAD_EPDC_PWRCTRL2__EPDC_PWRCTRL2 IOMUX_PAD(0x5C8, 0x22C, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 820 | #define MX50_PAD_EPDC_PWRCTRL2__GPIO_3_31 IOMUX_PAD(0x5C8, 0x22C, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 821 | #define MX50_PAD_EPDC_PWRCTRL2__WEIM_D31 IOMUX_PAD(0x5C8, 0x22C, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 822 | #define MX50_PAD_EPDC_PWRCTRL2__ELCDIF_D15 IOMUX_PAD(0x5C8, 0x22C, 3, 0x738, 1, MX50_ELCDIF_PAD_CTRL) | ||
| 823 | #define MX50_PAD_EPDC_PWRCTRL2__AUD4_RXFS IOMUX_PAD(0x5C8, 0x22C, 4, 0x6d0, 1, NO_PAD_CTRL) | ||
| 824 | #define MX50_PAD_EPDC_PWRCTRL2__SDMA_EXT0 IOMUX_PAD(0x5C8, 0x22C, 6, 0x7b8, 1, NO_PAD_CTRL) | ||
| 825 | |||
| 826 | #define MX50_PAD_EPDC_PWRCTRL3__PWRCTRL3 IOMUX_PAD(0x5CC, 0x230, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 827 | #define MX50_PAD_EPDC_PWRCTRL3__GPIO_4_20 IOMUX_PAD(0x5CC, 0x230, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 828 | #define MX50_PAD_EPDC_PWRCTRL3__WEIM_EB2 IOMUX_PAD(0x5CC, 0x230, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 829 | #define MX50_PAD_EPDC_PWRCTRL3__SDMA_EXT1 IOMUX_PAD(0x5CC, 0x230, 6, 0x7bc, 1, NO_PAD_CTRL) | ||
| 830 | |||
| 831 | #define MX50_PAD_EPDC_VCOM0__EPDC_VCOM0 IOMUX_PAD(0x5D0, 0x234, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 832 | #define MX50_PAD_EPDC_VCOM0__GPIO_4_21 IOMUX_PAD(0x5D0, 0x234, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 833 | #define MX50_PAD_EPDC_VCOM0__WEIM_EB3 IOMUX_PAD(0x5D0, 0x234, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 834 | |||
| 835 | #define MX50_PAD_EPDC_VCOM1__EPDC_VCOM1 IOMUX_PAD(0x5D4, 0x238, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 836 | #define MX50_PAD_EPDC_VCOM1__GPIO_4_22 IOMUX_PAD(0x5D4, 0x238, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 837 | #define MX50_PAD_EPDC_VCOM1__WEIM_CS3 IOMUX_PAD(0x5D4, 0x238, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 838 | |||
| 839 | #define MX50_PAD_EPDC_BDR0__EPDC_BDR0 IOMUX_PAD(0x5D8, 0x23C, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 840 | #define MX50_PAD_EPDC_BDR0__GPIO_4_23 IOMUX_PAD(0x5D8, 0x23C, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 841 | #define MX50_PAD_EPDC_BDR0__ELCDIF_D7 IOMUX_PAD(0x5D8, 0x23C, 3, 0x718, 1, MX50_ELCDIF_PAD_CTRL) | ||
| 842 | |||
| 843 | #define MX50_PAD_EPDC_BDR1__EPDC_BDR1 IOMUX_PAD(0x5DC, 0x240, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 844 | #define MX50_PAD_EPDC_BDR1__GPIO_4_24 IOMUX_PAD(0x5DC, 0x240, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 845 | #define MX50_PAD_EPDC_BDR1__ELCDIF_D6 IOMUX_PAD(0x5DC, 0x240, 3, 0x714, 1, MX50_ELCDIF_PAD_CTRL) | ||
| 846 | |||
| 847 | #define MX50_PAD_EPDC_SDCE0__EPDC_SDCE0 IOMUX_PAD(0x5E0, 0x244, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 848 | #define MX50_PAD_EPDC_SDCE0__GPIO_4_25 IOMUX_PAD(0x5E0, 0x244, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 849 | #define MX50_PAD_EPDC_SDCE0__ELCDIF_D5 IOMUX_PAD(0x5E0, 0x244, 3, 0x710, 1, MX50_ELCDIF_PAD_CTRL) | ||
| 850 | |||
| 851 | #define MX50_PAD_EPDC_SDCE1__EPDC_SDCE1 IOMUX_PAD(0x5E4, 0x248, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 852 | #define MX50_PAD_EPDC_SDCE1__GPIO_4_26 IOMUX_PAD(0x5E4, 0x248, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 853 | #define MX50_PAD_EPDC_SDCE1__ELCDIF_D4 IOMUX_PAD(0x5E4, 0x248, 2, 0x70c, 1, MX50_ELCDIF_PAD_CTRL) | ||
| 854 | |||
| 855 | #define MX50_PAD_EPDC_SDCE2__EPDC_SDCE2 IOMUX_PAD(0x5E8, 0x24C, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 856 | #define MX50_PAD_EPDC_SDCE2__GPIO_4_27 IOMUX_PAD(0x5E8, 0x24C, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 857 | #define MX50_PAD_EPDC_SDCE2__ELCDIF_DAT3 IOMUX_PAD(0x5E8, 0x24C, 3, 0x708, 1, MX50_ELCDIF_PAD_CTRL) | ||
| 858 | |||
| 859 | #define MX50_PAD_EPDC_SDCE3__EPDC_SDCE3 IOMUX_PAD(0x5EC, 0x250, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 860 | #define MX50_PAD_EPDC_SDCE3__GPIO_4_28 IOMUX_PAD(0x5EC, 0x250, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 861 | #define MX50_PAD_EPDC_SDCE3__ELCDIF_D2 IOMUX_PAD(0x5EC, 0x250, 3, 0x704, 1, MX50_ELCDIF_PAD_CTRL) | ||
| 862 | |||
| 863 | #define MX50_PAD_EPDC_SDCE4__EPDC_SDCE4 IOMUX_PAD(0x5F0, 0x254, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 864 | #define MX50_PAD_EPDC_SDCE4__GPIO_4_29 IOMUX_PAD(0x5F0, 0x254, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 865 | #define MX50_PAD_EPDC_SDCE4__ELCDIF_D1 IOMUX_PAD(0x5F0, 0x254, 3, 0x700, 1, MX50_ELCDIF_PAD_CTRL) | ||
| 866 | |||
| 867 | #define MX50_PAD_EPDC_SDCE5__EPDC_SDCE5 IOMUX_PAD(0x5F4, 0x258, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 868 | #define MX50_PAD_EPDC_SDCE5__GPIO_4_30 IOMUX_PAD(0x5F4, 0x258, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 869 | #define MX50_PAD_EPDC_SDCE5__ELCDIF_D0 IOMUX_PAD(0x5F4, 0x258, 3, 0x6fc, 1, MX50_ELCDIF_PAD_CTRL) | ||
| 870 | |||
| 871 | #define MX50_PAD_EIM_DA0__WEIM_A0 IOMUX_PAD(0x5F8, 0x25C, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 872 | #define MX50_PAD_EIM_DA0__GPIO_1_0 IOMUX_PAD(0x5F8, 0x25C, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 873 | #define MX50_PAD_EIM_DA0__KEY_COL4 IOMUX_PAD(0x5f8, 0x25C, 3, 0x790, 2, NO_PAD_CTRL) | ||
| 874 | |||
| 875 | #define MX50_PAD_EIM_DA1__WEIM_A1 IOMUX_PAD(0x5FC, 0x260, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 876 | #define MX50_PAD_EIM_DA1__GPIO_1_1 IOMUX_PAD(0x5FC, 0x260, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 877 | #define MX50_PAD_EIM_DA1__KEY_ROW4 IOMUX_PAD(0x5fc, 0x260, 3, 0x7a0, 2, MX50_KEYPAD_CTRL) | ||
| 878 | |||
| 879 | #define MX50_PAD_EIM_DA2__WEIM_A2 IOMUX_PAD(0x600, 0x264, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 880 | #define MX50_PAD_EIM_DA2__GPIO_1_2 IOMUX_PAD(0x600, 0x264, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 881 | #define MX50_PAD_EIM_DA2__KEY_COL5 IOMUX_PAD(0x600, 0x264, 3, 0x794, 2, NO_PAD_CTRL) | ||
| 882 | |||
| 883 | #define MX50_PAD_EIM_DA3__WEIM_A3 IOMUX_PAD(0x604, 0x268, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 884 | #define MX50_PAD_EIM_DA3__GPIO_1_3 IOMUX_PAD(0x604, 0x268, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 885 | #define MX50_PAD_EIM_DA3__KEY_ROW5 IOMUX_PAD(0x604, 0x268, 3, 0x7a4, 2, MX50_KEYPAD_CTRL) | ||
| 886 | |||
| 887 | #define MX50_PAD_EIM_DA4__WEIM_A4 IOMUX_PAD(0x608, 0x26C, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 888 | #define MX50_PAD_EIM_DA4__GPIO_1_4 IOMUX_PAD(0x608, 0x26C, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 889 | #define MX50_PAD_EIM_DA4__KEY_COL6 IOMUX_PAD(0x608, 0x26C, 3, 0x798, 2, NO_PAD_CTRL) | ||
| 890 | |||
| 891 | #define MX50_PAD_EIM_DA5__WEIM_A5 IOMUX_PAD(0x60C, 0x270, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 892 | #define MX50_PAD_EIM_DA5__GPIO_1_5 IOMUX_PAD(0x60C, 0x270, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 893 | #define MX50_PAD_EIM_DA5__KEY_ROW6 IOMUX_PAD(0x60C, 0x270, 3, 0x7a8, 2, MX50_KEYPAD_CTRL) | ||
| 894 | |||
| 895 | #define MX50_PAD_EIM_DA6__WEIM_A6 IOMUX_PAD(0x610, 0x274, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 896 | #define MX50_PAD_EIM_DA6__GPIO_1_6 IOMUX_PAD(0x610, 0x274, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 897 | #define MX50_PAD_EIM_DA6__KEY_COL7 IOMUX_PAD(0x610, 0x274, 3, 0x79c, 2, NO_PAD_CTRL) | ||
| 898 | |||
| 899 | #define MX50_PAD_EIM_DA7__WEIM_A7 IOMUX_PAD(0x614, 0x278, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 900 | #define MX50_PAD_EIM_DA7__GPIO_1_7 IOMUX_PAD(0x614, 0x278, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 901 | #define MX50_PAD_EIM_DA7__KEY_ROW7 IOMUX_PAD(0x614, 0x278, 3, 0x7ac, 2, MX50_KEYPAD_CTRL) | ||
| 902 | |||
| 903 | #define MX50_PAD_EIM_DA8__WEIM_A8 IOMUX_PAD(0x618, 0x27C, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 904 | #define MX50_PAD_EIM_DA8__GPIO_1_8 IOMUX_PAD(0x618, 0x27C, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 905 | #define MX50_PIN_EIM_DA8__NANDF_CLE IOMUX_PAD(0x618, 0x27C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) | ||
| 906 | |||
| 907 | #define MX50_PAD_EIM_DA9__WEIM_A9 IOMUX_PAD(0x61C, 0x280, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 908 | #define MX50_PAD_EIM_DA9__GPIO_1_9 IOMUX_PAD(0x61C, 0x280, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 909 | #define MX50_PIN_EIM_DA9__NANDF_ALE IOMUX_PAD(0x61C, 0x280, 2, 0x0, 0, PAD_CTL_DSE_HIGH) | ||
| 910 | |||
| 911 | #define MX50_PAD_EIM_DA10__WEIM_A10 IOMUX_PAD(0x620, 0x284, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 912 | #define MX50_PAD_EIM_DA10__GPIO_1_10 IOMUX_PAD(0x620, 0x284, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 913 | #define MX50_PIN_EIM_DA10__NANDF_CE0 IOMUX_PAD(0x620, 0x284, 2, 0x0, 0, PAD_CTL_DSE_HIGH) | ||
| 914 | |||
| 915 | #define MX50_PAD_EIM_DA11__WEIM_A11 IOMUX_PAD(0x624, 0x288, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 916 | #define MX50_PAD_EIM_DA11__GPIO_1_11 IOMUX_PAD(0x624, 0x288, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 917 | #define MX50_PIN_EIM_DA11__NANDF_CE1 IOMUX_PAD(0x624, 0x288, 2, 0x0, 0, PAD_CTL_DSE_HIGH) | ||
| 918 | |||
| 919 | #define MX50_PAD_EIM_DA12__WEIM_A12 IOMUX_PAD(0x628, 0x28C, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 920 | #define MX50_PAD_EIM_DA12__GPIO_1_12 IOMUX_PAD(0x628, 0x28C, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 921 | #define MX50_PIN_EIM_DA12__NANDF_CE2 IOMUX_PAD(0x628, 0x28C, 2, 0x0, 0, PAD_CTL_DSE_HIGH) | ||
| 922 | #define MX50_PAD_EIM_DA12__EPDC_SDCE6 IOMUX_PAD(0x628, 0x28C, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 923 | |||
| 924 | #define MX50_PAD_EIM_DA13__WEIM_A13 IOMUX_PAD(0x62C, 0x290, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 925 | #define MX50_PAD_EIM_DA13__GPIO_1_13 IOMUX_PAD(0x62C, 0x290, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 926 | #define MX50_PIN_EIM_DA13__NANDF_CE3 IOMUX_PAD(0x62C, 0x290, 2, 0x0, 0, PAD_CTL_DSE_HIGH) | ||
| 927 | #define MX50_PIN_EIM_DA13__EPDC_SDCE7 IOMUX_PAD(0x62C, 0x290, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 928 | |||
| 929 | #define MX50_PAD_EIM_DA14__WEIM_A14 IOMUX_PAD(0x630, 0x294, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 930 | #define MX50_PAD_EIM_DA14__GPIO_1_14 IOMUX_PAD(0x630, 0x294, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 931 | #define MX50_PAD_EIM_DA14__NANDF_READY IOMUX_PAD(0x630, 0x294, 2, 0x7B4, 2, PAD_CTL_PKE | \ | ||
| 932 | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) | ||
| 933 | #define MX50_PAD_EIM_DA14__EPDC_SDCE8 IOMUX_PAD(0x630, 0x294, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 934 | |||
| 935 | #define MX50_PAD_EIM_DA15__WEIM_A15 IOMUX_PAD(0x634, 0x298, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 936 | #define MX50_PAD_EIM_DA15__GPIO_1_15 IOMUX_PAD(0x634, 0x298, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 937 | #define MX50_PIN_EIM_DA15__NANDF_DQS IOMUX_PAD(0x634, 0x298, 2, 0x7B0, 2, PAD_CTL_DSE_HIGH) | ||
| 938 | #define MX50_PAD_EIM_DA15__EPDC_SDCE9 IOMUX_PAD(0x634, 0x298, 3, 0x0, 0, NO_PAD_CTRL) | ||
| 939 | |||
| 940 | #define MX50_PAD_EIM_CS2__WEIM_CS2 IOMUX_PAD(0x638, 0x29C, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 941 | #define MX50_PAD_EIM_CS2__GPIO_1_16 IOMUX_PAD(0x638, 0x29C, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 942 | #define MX50_PAD_EIM_CS2__WEIM_A27 IOMUX_PAD(0x638, 0x29C, 2, 0x0, 0, NO_PAD_CTRL) | ||
| 943 | |||
| 944 | #define MX50_PAD_EIM_CS1__WEIM_CS1 IOMUX_PAD(0x63C, 0x2A0, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 945 | #define MX50_PAD_EIM_CS1__GPIO_1_17 IOMUX_PAD(0x63C, 0x2A0, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 946 | |||
| 947 | #define MX50_PAD_EIM_CS0__WEIM_CS0 IOMUX_PAD(0x640, 0x2A4, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 948 | #define MX50_PAD_EIM_CS0__GPIO_1_18 IOMUX_PAD(0x640, 0x2A4, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 949 | |||
| 950 | #define MX50_PAD_EIM_EB0__WEIM_EB0 IOMUX_PAD(0x644, 0x2A8, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 951 | #define MX50_PAD_EIM_EB0__GPIO_1_19 IOMUX_PAD(0x644, 0x2A8, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 952 | |||
| 953 | #define MX50_PAD_EIM_EB1__WEIM_EB1 IOMUX_PAD(0x648, 0x2AC, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 954 | #define MX50_PAD_EIM_EB1__GPIO_1_20 IOMUX_PAD(0x648, 0x2AC, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 955 | |||
| 956 | #define MX50_PAD_EIM_WAIT__WEIM_WAIT IOMUX_PAD(0x64C, 0x2B0, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 957 | #define MX50_PAD_EIM_WAIT__GPIO_1_21 IOMUX_PAD(0x64C, 0x2B0, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 958 | |||
| 959 | #define MX50_PAD_EIM_BCLK__WEIM_BCLK IOMUX_PAD(0x650, 0x2B4, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 960 | #define MX50_PAD_EIM_BCLK__GPIO_1_22 IOMUX_PAD(0x650, 0x2B4, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 961 | |||
| 962 | #define MX50_PAD_EIM_RDY__WEIM_RDY IOMUX_PAD(0x654, 0x2B8, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 963 | #define MX50_PAD_EIM_RDY__GPIO_1_23 IOMUX_PAD(0x654, 0x2B8, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 964 | |||
| 965 | #define MX50_PAD_EIM_OE__WEIM_OE IOMUX_PAD(0x658, 0x2BC, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 966 | #define MX50_PAD_EIM_OE__GPIO_1_24 IOMUX_PAD(0x658, 0x2BC, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 967 | |||
| 968 | #define MX50_PAD_EIM_RW__WEIM_RW IOMUX_PAD(0x65C, 0x2C0, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 969 | #define MX50_PAD_EIM_RW__GPIO_1_25 IOMUX_PAD(0x65C, 0x2C0, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 970 | |||
| 971 | #define MX50_PAD_EIM_LBA__WEIM_LBA IOMUX_PAD(0x660, 0x2C4, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 972 | #define MX50_PAD_EIM_LBA__GPIO_1_26 IOMUX_PAD(0x660, 0x2C4, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 973 | |||
| 974 | #define MX50_PAD_EIM_CRE__WEIM_CRE IOMUX_PAD(0x664, 0x2C8, 0, 0x0, 0, NO_PAD_CTRL) | ||
| 975 | #define MX50_PAD_EIM_CRE__GPIO_1_27 IOMUX_PAD(0x664, 0x2C8, 1, 0x0, 0, NO_PAD_CTRL) | ||
| 976 | |||
| 977 | #endif /* __MACH_IOMUX_MX50_H__ */ | ||
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h index d7a41e9a2605..b6767f90ef14 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h | |||
| @@ -15,373 +15,1553 @@ | |||
| 15 | 15 | ||
| 16 | #include <mach/iomux-v3.h> | 16 | #include <mach/iomux-v3.h> |
| 17 | 17 | ||
| 18 | /* | ||
| 19 | * various IOMUX alternate output functions (1-7) | ||
| 20 | */ | ||
| 21 | typedef enum iomux_config { | ||
| 22 | IOMUX_CONFIG_ALT0, | ||
| 23 | IOMUX_CONFIG_ALT1, | ||
| 24 | IOMUX_CONFIG_ALT2, | ||
| 25 | IOMUX_CONFIG_ALT3, | ||
| 26 | IOMUX_CONFIG_ALT4, | ||
| 27 | IOMUX_CONFIG_ALT5, | ||
| 28 | IOMUX_CONFIG_ALT6, | ||
| 29 | IOMUX_CONFIG_ALT7, | ||
| 30 | IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */ | ||
| 31 | IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */ | ||
| 32 | } iomux_pin_cfg_t; | ||
| 33 | |||
| 34 | /* Pad control groupings */ | 18 | /* Pad control groupings */ |
| 35 | #define MX51_UART1_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ | 19 | #define MX51_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \ |
| 36 | PAD_CTL_DSE_HIGH) | 20 | PAD_CTL_HYS | PAD_CTL_SRE_FAST) |
| 37 | #define MX51_UART2_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \ | ||
| 38 | PAD_CTL_SRE_FAST) | ||
| 39 | #define MX51_UART3_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ | ||
| 40 | PAD_CTL_SRE_FAST) | ||
| 41 | #define MX51_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ | 21 | #define MX51_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ |
| 42 | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS) | 22 | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ |
| 43 | #define MX51_USBH1_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ | 23 | PAD_CTL_HYS) |
| 44 | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ | 24 | #define MX51_ESDHC_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ |
| 45 | PAD_CTL_PKE | PAD_CTL_HYS) | 25 | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ |
| 46 | #define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \ | 26 | PAD_CTL_HYS) |
| 47 | PAD_CTL_SRE_FAST) | 27 | #define MX51_USBH1_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SRE_FAST | \ |
| 48 | #define MX51_GPIO_PAD_CTRL_2 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ | 28 | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ |
| 49 | PAD_CTL_PUS_100K_UP) | 29 | PAD_CTL_HYS | PAD_CTL_PUE) |
| 50 | #define MX51_ECSPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ | 30 | #define MX51_ECSPI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_HYS | \ |
| 51 | PAD_CTL_SRE_FAST) | 31 | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST) |
| 52 | #define MX51_SDHCI_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP | \ | 32 | #define MX51_SDHCI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ |
| 53 | PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_SRE_FAST | \ | 33 | PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | \ |
| 54 | PAD_CTL_DVS) | 34 | PAD_CTL_SRE_FAST | PAD_CTL_DVS) |
| 35 | #define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST) | ||
| 55 | 36 | ||
| 56 | #define MX51_PAD_CTRL_1 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ | 37 | #define MX51_PAD_CTRL_2 (PAD_CTL_PKE | PAD_CTL_HYS) |
| 57 | PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_HYS) | 38 | #define MX51_PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) |
| 58 | #define MX51_PAD_CTRL_2 (PAD_CTL_HYS | PAD_CTL_PKE) | 39 | #define MX51_PAD_CTRL_4 (PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS) |
| 59 | #define MX51_PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) | 40 | #define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH) |
| 60 | #define MX51_PAD_CTRL_4 (PAD_CTL_DVS | PAD_CTL_HYS | PAD_CTL_PKE) | ||
| 61 | #define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH) | ||
| 62 | 41 | ||
| 63 | /* | 42 | /* |
| 64 | * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode> | 43 | * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode> |
| 65 | * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> | 44 | * If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num> |
| 66 | * See also iomux-v3.h | 45 | * See also iomux-v3.h |
| 67 | */ | 46 | */ |
| 68 | 47 | ||
| 69 | /* PAD MUX ALT INPSE PATH PADCTRL */ | 48 | /* Raw pin modes without pad control */ |
| 70 | #define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x7a8, 0x01c, 0, 0x0, 0, NO_PAD_CTRL) | 49 | /* PAD MUX ALT INPSE PATH PADCTRL */ |
| 71 | #define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x7a8, 0x020, 0, 0x0, 0, NO_PAD_CTRL) | 50 | #define _MX51_PAD_EIM_D16__AUD4_RXFS IOMUX_PAD(0x3f0, 0x5c, 5, 0x0000, 0, 0) |
| 72 | #define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x7a8, 0x024, 0, 0x0, 0, NO_PAD_CTRL) | 51 | #define _MX51_PAD_EIM_D16__AUD5_TXD IOMUX_PAD(0x3f0, 0x5c, 7, 0x08d8, 0, 0) |
| 73 | #define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x7a8, 0x028, 0, 0x0, 0, NO_PAD_CTRL) | 52 | #define _MX51_PAD_EIM_D16__EIM_D16 IOMUX_PAD(0x3f0, 0x5c, 0, 0x0000, 0, 0) |
| 74 | #define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x7ac, 0x02c, 0, 0x0, 0, NO_PAD_CTRL) | 53 | #define _MX51_PAD_EIM_D16__GPIO2_0 IOMUX_PAD(0x3f0, 0x5c, 1, 0x0000, 0, 0) |
| 75 | #define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x7ac, 0x030, 0, 0x0, 0, NO_PAD_CTRL) | 54 | #define _MX51_PAD_EIM_D16__I2C1_SDA IOMUX_PAD(0x3f0, 0x5c, 0x14, 0x09b4, 0, 0) |
| 76 | #define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x7ac, 0x034, 0, 0x0, 0, NO_PAD_CTRL) | 55 | #define _MX51_PAD_EIM_D16__UART2_CTS IOMUX_PAD(0x3f0, 0x5c, 3, 0x0000, 0, 0) |
| 77 | #define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x7ac, 0x038, 0, 0x0, 0, NO_PAD_CTRL) | 56 | #define _MX51_PAD_EIM_D16__USBH2_DATA0 IOMUX_PAD(0x3f0, 0x5c, 2, 0x0000, 0, 0) |
| 78 | #define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x7b0, 0x03c, 0, 0x0, 0, NO_PAD_CTRL) | 57 | #define _MX51_PAD_EIM_D17__AUD5_RXD IOMUX_PAD(0x3f4, 0x60, 7, 0x08d4, 0, 0) |
| 79 | #define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x7b0, 0x040, 0, 0x0, 0, NO_PAD_CTRL) | 58 | #define _MX51_PAD_EIM_D17__EIM_D17 IOMUX_PAD(0x3f4, 0x60, 0, 0x0000, 0, 0) |
| 80 | #define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x7b0, 0x044, 0, 0x0, 0, NO_PAD_CTRL) | 59 | #define _MX51_PAD_EIM_D17__GPIO2_1 IOMUX_PAD(0x3f4, 0x60, 1, 0x0000, 0, 0) |
| 81 | #define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x7b0, 0x048, 0, 0x0, 0, NO_PAD_CTRL) | 60 | #define _MX51_PAD_EIM_D17__UART2_RXD IOMUX_PAD(0x3f4, 0x60, 3, 0x09ec, 0, 0) |
| 82 | #define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x7bc, 0x04c, 0, 0x0, 0, NO_PAD_CTRL) | 61 | #define _MX51_PAD_EIM_D17__UART3_CTS IOMUX_PAD(0x3f4, 0x60, 4, 0x0000, 0, 0) |
| 83 | #define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x7bc, 0x050, 0, 0x0, 0, NO_PAD_CTRL) | 62 | #define _MX51_PAD_EIM_D17__USBH2_DATA1 IOMUX_PAD(0x3f4, 0x60, 2, 0x0000, 0, 0) |
| 84 | #define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x7bc, 0x054, 0, 0x0, 0, NO_PAD_CTRL) | 63 | #define _MX51_PAD_EIM_D18__AUD5_TXC IOMUX_PAD(0x3f8, 0x64, 7, 0x08e4, 0, 0) |
| 85 | #define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x7bc, 0x058, 0, 0x0, 0, NO_PAD_CTRL) | 64 | #define _MX51_PAD_EIM_D18__EIM_D18 IOMUX_PAD(0x3f8, 0x64, 0, 0x0000, 0, 0) |
| 86 | #define MX51_PAD_EIM_D16__GPIO_2_0 IOMUX_PAD(0x3f0, 0x05c, 1, 0x0, 0, NO_PAD_CTRL) | 65 | #define _MX51_PAD_EIM_D18__GPIO2_2 IOMUX_PAD(0x3f8, 0x64, 1, 0x0000, 0, 0) |
| 87 | #define MX51_PAD_EIM_D16__I2C1_SDA IOMUX_PAD(0x3f0, 0x05c, (4 | IOMUX_CONFIG_SION), \ | 66 | #define _MX51_PAD_EIM_D18__UART2_TXD IOMUX_PAD(0x3f8, 0x64, 3, 0x0000, 0, 0) |
| 88 | 0x09b4, 0, MX51_I2C_PAD_CTRL) | 67 | #define _MX51_PAD_EIM_D18__UART3_RTS IOMUX_PAD(0x3f8, 0x64, 4, 0x09f0, 1, 0) |
| 89 | #define MX51_PAD_EIM_D17__GPIO_2_1 IOMUX_PAD(0x3f4, 0x060, 1, 0x0, 0, NO_PAD_CTRL) | 68 | #define _MX51_PAD_EIM_D18__USBH2_DATA2 IOMUX_PAD(0x3f8, 0x64, 2, 0x0000, 0, 0) |
| 90 | #define MX51_PAD_EIM_D18__GPIO_2_2 IOMUX_PAD(0x3f8, 0x064, 1, 0x0, 0, NO_PAD_CTRL) | 69 | #define _MX51_PAD_EIM_D19__AUD4_RXC IOMUX_PAD(0x3fc, 0x68, 5, 0x0000, 0, 0) |
| 91 | #define MX51_PAD_EIM_D19__GPIO_2_3 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL) | 70 | #define _MX51_PAD_EIM_D19__AUD5_TXFS IOMUX_PAD(0x3fc, 0x68, 7, 0x08e8, 0, 0) |
| 92 | #define MX51_PAD_EIM_D19__I2C1_SCL IOMUX_PAD(0x3fc, 0x068, (4 | IOMUX_CONFIG_SION), \ | 71 | #define _MX51_PAD_EIM_D19__EIM_D19 IOMUX_PAD(0x3fc, 0x68, 0, 0x0000, 0, 0) |
| 93 | 0x09b0, 0, MX51_I2C_PAD_CTRL) | 72 | #define _MX51_PAD_EIM_D19__GPIO2_3 IOMUX_PAD(0x3fc, 0x68, 1, 0x0000, 0, 0) |
| 94 | #define MX51_PAD_EIM_D20__GPIO_2_4 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL) | 73 | #define _MX51_PAD_EIM_D19__I2C1_SCL IOMUX_PAD(0x3fc, 0x68, 0x14, 0x09b0, 0, 0) |
| 95 | #define MX51_PAD_EIM_D21__GPIO_2_5 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) | 74 | #define _MX51_PAD_EIM_D19__UART2_RTS IOMUX_PAD(0x3fc, 0x68, 3, 0x09e8, 1, 0) |
| 96 | #define MX51_PAD_EIM_D22__GPIO_2_6 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL) | 75 | #define _MX51_PAD_EIM_D19__USBH2_DATA3 IOMUX_PAD(0x3fc, 0x68, 2, 0x0000, 0, 0) |
| 97 | #define MX51_PAD_EIM_D23__GPIO_2_7 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, NO_PAD_CTRL) | 76 | #define _MX51_PAD_EIM_D20__AUD4_TXD IOMUX_PAD(0x400, 0x6c, 5, 0x08c8, 0, 0) |
| 98 | #define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, 3, 0x0, 0, MX51_UART3_PAD_CTRL) | 77 | #define _MX51_PAD_EIM_D20__EIM_D20 IOMUX_PAD(0x400, 0x6c, 0, 0x0000, 0, 0) |
| 99 | #define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART3_PAD_CTRL) | 78 | #define _MX51_PAD_EIM_D20__GPIO2_4 IOMUX_PAD(0x400, 0x6c, 1, 0x0000, 0, 0) |
| 100 | #define MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x080, 4, 0x0, 0, MX51_UART2_PAD_CTRL) | 79 | #define _MX51_PAD_EIM_D20__SRTC_ALARM_DEB IOMUX_PAD(0x400, 0x6c, 4, 0x0000, 0, 0) |
| 101 | #define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, 3, 0x0, 0, MX51_UART3_PAD_CTRL) | 80 | #define _MX51_PAD_EIM_D20__USBH2_DATA4 IOMUX_PAD(0x400, 0x6c, 2, 0x0000, 0, 0) |
| 102 | #define MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART2_PAD_CTRL) | 81 | #define _MX51_PAD_EIM_D21__AUD4_RXD IOMUX_PAD(0x404, 0x70, 5, 0x08c4, 0, 0) |
| 103 | #define MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART3_PAD_CTRL) | 82 | #define _MX51_PAD_EIM_D21__EIM_D21 IOMUX_PAD(0x404, 0x70, 0, 0x0000, 0, 0) |
| 104 | #define MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x08c, 0, 0x0, 0, NO_PAD_CTRL) | 83 | #define _MX51_PAD_EIM_D21__GPIO2_5 IOMUX_PAD(0x404, 0x70, 1, 0x0000, 0, 0) |
| 105 | #define MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x090, 0, 0x0, 0, NO_PAD_CTRL) | 84 | #define _MX51_PAD_EIM_D21__SRTC_ALARM_DEB IOMUX_PAD(0x404, 0x70, 3, 0x0000, 0, 0) |
| 106 | #define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x094, 0, 0x0, 0, NO_PAD_CTRL) | 85 | #define _MX51_PAD_EIM_D21__USBH2_DATA5 IOMUX_PAD(0x404, 0x70, 2, 0x0000, 0, 0) |
| 107 | #define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x09c, 0, 0x0, 0, NO_PAD_CTRL) | 86 | #define _MX51_PAD_EIM_D22__AUD4_TXC IOMUX_PAD(0x408, 0x74, 5, 0x08cc, 0, 0) |
| 108 | #define MX51_PAD_EIM_A16__GPIO_2_10 IOMUX_PAD(0x430, 0x09c, 1, 0x0, 0, NO_PAD_CTRL) | 87 | #define _MX51_PAD_EIM_D22__EIM_D22 IOMUX_PAD(0x408, 0x74, 0, 0x0000, 0, 0) |
| 109 | #define MX51_PAD_EIM_A17__GPIO_2_11 IOMUX_PAD(0x434, 0x0a0, 1, 0x0, 0, NO_PAD_CTRL) | 88 | #define _MX51_PAD_EIM_D22__GPIO2_6 IOMUX_PAD(0x408, 0x74, 1, 0x0000, 0, 0) |
| 110 | #define MX51_PAD_EIM_A18__GPIO_2_12 IOMUX_PAD(0x438, 0x0a4, 1, 0x0, 0, NO_PAD_CTRL) | 89 | #define _MX51_PAD_EIM_D22__USBH2_DATA6 IOMUX_PAD(0x408, 0x74, 2, 0x0000, 0, 0) |
| 111 | #define MX51_PAD_EIM_A19__GPIO_2_13 IOMUX_PAD(0x43c, 0x0a8, 1, 0x0, 0, NO_PAD_CTRL) | 90 | #define _MX51_PAD_EIM_D23__AUD4_TXFS IOMUX_PAD(0x40c, 0x78, 5, 0x08d0, 0, 0) |
| 112 | #define MX51_PAD_EIM_A20__GPIO_2_14 IOMUX_PAD(0x440, 0x0ac, 1, 0x0, 0, NO_PAD_CTRL) | 91 | #define _MX51_PAD_EIM_D23__EIM_D23 IOMUX_PAD(0x40c, 0x78, 0, 0x0000, 0, 0) |
| 113 | #define MX51_PAD_EIM_A21__GPIO_2_15 IOMUX_PAD(0x444, 0x0b0, 1, 0x0, 0, NO_PAD_CTRL) | 92 | #define _MX51_PAD_EIM_D23__GPIO2_7 IOMUX_PAD(0x40c, 0x78, 1, 0x0000, 0, 0) |
| 114 | #define MX51_PAD_EIM_A22__GPIO_2_16 IOMUX_PAD(0x448, 0x0b4, 1, 0x0, 0, NO_PAD_CTRL) | 93 | #define _MX51_PAD_EIM_D23__SPDIF_OUT1 IOMUX_PAD(0x40c, 0x78, 4, 0x0000, 0, 0) |
| 115 | #define MX51_PAD_EIM_A23__GPIO_2_17 IOMUX_PAD(0x44c, 0x0b8, 1, 0x0, 0, NO_PAD_CTRL) | 94 | #define _MX51_PAD_EIM_D23__USBH2_DATA7 IOMUX_PAD(0x40c, 0x78, 2, 0x0000, 0, 0) |
| 116 | #define MX51_PAD_EIM_A24__GPIO_2_18 IOMUX_PAD(0x450, 0x0bc, 1, 0x0, 0, NO_PAD_CTRL) | 95 | #define _MX51_PAD_EIM_D24__AUD6_RXFS IOMUX_PAD(0x410, 0x7c, 5, 0x08f8, 0, 0) |
| 117 | #define MX51_PAD_EIM_A25__GPIO_2_19 IOMUX_PAD(0x454, 0x0c0, 1, 0x0, 0, NO_PAD_CTRL) | 96 | #define _MX51_PAD_EIM_D24__EIM_D24 IOMUX_PAD(0x410, 0x7c, 0, 0x0000, 0, 0) |
| 118 | #define MX51_PAD_EIM_A26__GPIO_2_20 IOMUX_PAD(0x458, 0x0c4, 1, 0x0, 0, NO_PAD_CTRL) | 97 | #define _MX51_PAD_EIM_D24__GPIO2_8 IOMUX_PAD(0x410, 0x7c, 1, 0x0000, 0, 0) |
| 119 | #define MX51_PAD_EIM_A27__GPIO_2_21 IOMUX_PAD(0x45c, 0x0c8, 1, 0x0, 0, NO_PAD_CTRL) | 98 | #define _MX51_PAD_EIM_D24__I2C2_SDA IOMUX_PAD(0x410, 0x7c, 0x14, 0x09bc, 0, 0) |
| 120 | #define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL) | 99 | #define _MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x7c, 3, 0x0000, 0, 0) |
| 121 | #define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL) | 100 | #define _MX51_PAD_EIM_D24__USBOTG_DATA0 IOMUX_PAD(0x410, 0x7c, 2, 0x0000, 0, 0) |
| 122 | #define MX51_PAD_EIM_EB2__GPIO_2_22 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL) | 101 | #define _MX51_PAD_EIM_D25__EIM_D25 IOMUX_PAD(0x414, 0x80, 0, 0x0000, 0, 0) |
| 123 | #define MX51_PAD_EIM_EB2__FEC_MDIO IOMUX_PAD(0x468, 0x0d4, 3, 0x0, 0, MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP) | 102 | #define _MX51_PAD_EIM_D25__KEY_COL6 IOMUX_PAD(0x414, 0x80, 1, 0x09c8, 0, 0) |
| 124 | #define MX51_PAD_EIM_EB3__GPIO_2_23 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL) | 103 | #define _MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x80, 4, 0x0000, 0, 0) |
| 125 | #define MX51_PAD_EIM_EB3__FEC_RDAT1 IOMUX_PAD(0x46c, 0x0d8, 3, 0x0, 0, MX51_PAD_CTRL_2) | 104 | #define _MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x80, 3, 0x09f4, 0, 0) |
| 126 | #define MX51_PAD_EIM_OE__GPIO_2_24 IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL) | 105 | #define _MX51_PAD_EIM_D25__USBOTG_DATA1 IOMUX_PAD(0x414, 0x80, 2, 0x0000, 0, 0) |
| 127 | #define MX51_PAD_EIM_CS0__GPIO_2_25 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL) | 106 | #define _MX51_PAD_EIM_D26__EIM_D26 IOMUX_PAD(0x418, 0x84, 0, 0x0000, 0, 0) |
| 128 | #define MX51_PAD_EIM_CS1__GPIO_2_26 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL) | 107 | #define _MX51_PAD_EIM_D26__KEY_COL7 IOMUX_PAD(0x418, 0x84, 1, 0x09cc, 0, 0) |
| 129 | #define MX51_PAD_EIM_CS2__GPIO_2_27 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL) | 108 | #define _MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x84, 4, 0x09e8, 3, 0) |
| 130 | #define MX51_PAD_EIM_CS2__FEC_RDAT2 IOMUX_PAD(0x47c, 0x0e8, 3, 0x0, 0, MX51_PAD_CTRL_2) | 109 | #define _MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x84, 3, 0x0000, 0, 0) |
| 131 | #define MX51_PAD_EIM_CS3__GPIO_2_28 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL) | 110 | #define _MX51_PAD_EIM_D26__USBOTG_DATA2 IOMUX_PAD(0x418, 0x84, 2, 0x0000, 0, 0) |
| 132 | #define MX51_PAD_EIM_CS3__FEC_RDAT3 IOMUX_PAD(0x480, 0x0ec, 3, 0x0, 0, MX51_PAD_CTRL_2) | 111 | #define _MX51_PAD_EIM_D27__AUD6_RXC IOMUX_PAD(0x41c, 0x88, 5, 0x08f4, 0, 0) |
| 133 | #define MX51_PAD_EIM_CS4__GPIO_2_29 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL) | 112 | #define _MX51_PAD_EIM_D27__EIM_D27 IOMUX_PAD(0x41c, 0x88, 0, 0x0000, 0, 0) |
| 134 | #define MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0x0f0, 3, 0x0, 0, MX51_PAD_CTRL_2) | 113 | #define _MX51_PAD_EIM_D27__GPIO2_9 IOMUX_PAD(0x41c, 0x88, 1, 0x0000, 0, 0) |
| 135 | #define MX51_PAD_EIM_CS5__GPIO_2_30 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL) | 114 | #define _MX51_PAD_EIM_D27__I2C2_SCL IOMUX_PAD(0x41c, 0x88, 0x14, 0x09b8, 0, 0) |
| 136 | #define MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x488, 0x0f4, 3, 0x0, 0, MX51_PAD_CTRL_2) | 115 | #define _MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x88, 3, 0x09f0, 3, 0) |
| 137 | #define MX51_PAD_EIM_DTACK__GPIO_2_31 IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL) | 116 | #define _MX51_PAD_EIM_D27__USBOTG_DATA3 IOMUX_PAD(0x41c, 0x88, 2, 0x0000, 0, 0) |
| 138 | #define MX51_PAD_EIM_LBA__GPIO_3_1 IOMUX_PAD(0x494, 0x0FC, 1, 0x0, 0, NO_PAD_CTRL) | 117 | #define _MX51_PAD_EIM_D28__AUD6_TXD IOMUX_PAD(0x420, 0x8c, 5, 0x08f0, 0, 0) |
| 139 | #define MX51_PAD_EIM_CRE__GPIO_3_2 IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL) | 118 | #define _MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x8c, 0, 0x0000, 0, 0) |
| 140 | #define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL) | 119 | #define _MX51_PAD_EIM_D28__KEY_ROW4 IOMUX_PAD(0x420, 0x8c, 1, 0x09d0, 0, 0) |
| 141 | #define MX51_PAD_NANDF_WE_B__GPIO_3_3 IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL) | 120 | #define _MX51_PAD_EIM_D28__USBOTG_DATA4 IOMUX_PAD(0x420, 0x8c, 2, 0x0000, 0, 0) |
| 142 | #define MX51_PAD_NANDF_RE_B__GPIO_3_4 IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL) | 121 | #define _MX51_PAD_EIM_D29__AUD6_RXD IOMUX_PAD(0x424, 0x90, 5, 0x08ec, 0, 0) |
| 143 | #define MX51_PAD_NANDF_ALE__GPIO_3_5 IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL) | 122 | #define _MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x90, 0, 0x0000, 0, 0) |
| 144 | #define MX51_PAD_NANDF_CLE__GPIO_3_6 IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL) | 123 | #define _MX51_PAD_EIM_D29__KEY_ROW5 IOMUX_PAD(0x424, 0x90, 1, 0x09d4, 0, 0) |
| 145 | #define MX51_PAD_NANDF_WP_B__GPIO_3_7 IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL) | 124 | #define _MX51_PAD_EIM_D29__USBOTG_DATA5 IOMUX_PAD(0x424, 0x90, 2, 0x0000, 0, 0) |
| 146 | #define MX51_PAD_NANDF_RB0__GPIO_3_8 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL) | 125 | #define _MX51_PAD_EIM_D30__AUD6_TXC IOMUX_PAD(0x428, 0x94, 5, 0x08fc, 0, 0) |
| 147 | #define MX51_PAD_NANDF_RB1__GPIO_3_9 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL) | 126 | #define _MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x94, 0, 0x0000, 0, 0) |
| 148 | #define MX51_PAD_NANDF_RB2__GPIO_3_10 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL) | 127 | #define _MX51_PAD_EIM_D30__KEY_ROW6 IOMUX_PAD(0x428, 0x94, 1, 0x09d8, 0, 0) |
| 149 | #define MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, 0x0, 0, MX51_ECSPI_PAD_CTRL) | 128 | #define _MX51_PAD_EIM_D30__USBOTG_DATA6 IOMUX_PAD(0x428, 0x94, 2, 0x0000, 0, 0) |
| 150 | #define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x0, 0, MX51_PAD_CTRL_2) | 129 | #define _MX51_PAD_EIM_D31__AUD6_TXFS IOMUX_PAD(0x42c, 0x98, 5, 0x0900, 0, 0) |
| 151 | #define MX51_PAD_NANDF_RB3__GPIO_3_11 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL) | 130 | #define _MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x98, 0, 0x0000, 0, 0) |
| 152 | #define MX51_PAD_NANDF_RB3__ECSPI2_MISO IOMUX_PAD(0x504, 0x128, 2, 0x0, 0, MX51_ECSPI_PAD_CTRL) | 131 | #define _MX51_PAD_EIM_D31__KEY_ROW7 IOMUX_PAD(0x42c, 0x98, 1, 0x09dc, 0, 0) |
| 153 | #define MX51_PAD_NANDF_RB3__FEC_RXCLK IOMUX_PAD(0x504, 0x128, 1, 0x0, 0, MX51_PAD_CTRL_2) | 132 | #define _MX51_PAD_EIM_D31__USBOTG_DATA7 IOMUX_PAD(0x42c, 0x98, 2, 0x0000, 0, 0) |
| 154 | #define MX51_PAD_NANDF_RB6__FEC_RDAT0 IOMUX_PAD(0x5DC, 0x134, 1, 0x0, 0, MX51_PAD_CTRL_4) | 133 | #define _MX51_PAD_EIM_A16__EIM_A16 IOMUX_PAD(0x430, 0x9c, 0, 0x0000, 0, 0) |
| 155 | #define MX51_PAD_NANDF_RB7__FEC_TDAT0 IOMUX_PAD(0x5E0, 0x138, 1, 0x0, 0, MX51_PAD_CTRL_5) | 134 | #define _MX51_PAD_EIM_A16__GPIO2_10 IOMUX_PAD(0x430, 0x9c, 1, 0x0000, 0, 0) |
| 156 | #define MX51_PAD_GPIO_NAND__GPIO_3_12 IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL) | 135 | #define _MX51_PAD_EIM_A16__OSC_FREQ_SEL0 IOMUX_PAD(0x430, 0x9c, 7, 0x0000, 0, 0) |
| 157 | #define MX51_PAD_NANDF_CS0__GPIO_3_16 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL) | 136 | #define _MX51_PAD_EIM_A17__EIM_A17 IOMUX_PAD(0x434, 0xa0, 0, 0x0000, 0, 0) |
| 158 | #define MX51_PAD_NANDF_CS1__GPIO_3_17 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL) | 137 | #define _MX51_PAD_EIM_A17__GPIO2_11 IOMUX_PAD(0x434, 0xa0, 1, 0x0000, 0, 0) |
| 159 | #define MX51_PAD_NANDF_CS2__GPIO_3_18 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL) | 138 | #define _MX51_PAD_EIM_A17__OSC_FREQ_SEL1 IOMUX_PAD(0x434, 0xa0, 7, 0x0000, 0, 0) |
| 160 | #define MX51_PAD_NANDF_CS2__FEC_TX_ER IOMUX_PAD(0x520, 0x138, 2, 0x0, 0, MX51_PAD_CTRL_5) | 139 | #define _MX51_PAD_EIM_A18__BOOT_LPB0 IOMUX_PAD(0x438, 0xa4, 7, 0x0000, 0, 0) |
| 161 | #define MX51_PAD_NANDF_CS3__GPIO_3_19 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL) | 140 | #define _MX51_PAD_EIM_A18__EIM_A18 IOMUX_PAD(0x438, 0xa4, 0, 0x0000, 0, 0) |
| 162 | #define MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13C, 2, 0x0, 0, MX51_PAD_CTRL_5) | 141 | #define _MX51_PAD_EIM_A18__GPIO2_12 IOMUX_PAD(0x438, 0xa4, 1, 0x0000, 0, 0) |
| 163 | #define MX51_PAD_NANDF_CS4__GPIO_3_20 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL) | 142 | #define _MX51_PAD_EIM_A19__BOOT_LPB1 IOMUX_PAD(0x43c, 0xa8, 7, 0x0000, 0, 0) |
| 164 | #define MX51_PAD_NANDF_CS4__FEC_TDAT1 IOMUX_PAD(0x528, 0x140, 2, 0x0, 0, MX51_PAD_CTRL_5) | 143 | #define _MX51_PAD_EIM_A19__EIM_A19 IOMUX_PAD(0x43c, 0xa8, 0, 0x0000, 0, 0) |
| 165 | #define MX51_PAD_NANDF_CS5__GPIO_3_21 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL) | 144 | #define _MX51_PAD_EIM_A19__GPIO2_13 IOMUX_PAD(0x43c, 0xa8, 1, 0x0000, 0, 0) |
| 166 | #define MX51_PAD_NANDF_CS5__FEC_TDAT2 IOMUX_PAD(0x52C, 0x144, 2, 0x0, 0, MX51_PAD_CTRL_5) | 145 | #define _MX51_PAD_EIM_A20__BOOT_UART_SRC0 IOMUX_PAD(0x440, 0xac, 7, 0x0000, 0, 0) |
| 167 | #define MX51_PAD_NANDF_CS6__GPIO_3_22 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL) | 146 | #define _MX51_PAD_EIM_A20__EIM_A20 IOMUX_PAD(0x440, 0xac, 0, 0x0000, 0, 0) |
| 168 | #define MX51_PAD_NANDF_CS6__FEC_TDAT3 IOMUX_PAD(0x530, 0x148, 2, 0x0, 0, MX51_PAD_CTRL_5) | 147 | #define _MX51_PAD_EIM_A20__GPIO2_14 IOMUX_PAD(0x440, 0xac, 1, 0x0000, 0, 0) |
| 169 | #define MX51_PAD_NANDF_CS7__GPIO_3_23 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL) | 148 | #define _MX51_PAD_EIM_A21__BOOT_UART_SRC1 IOMUX_PAD(0x444, 0xb0, 7, 0x0000, 0, 0) |
| 170 | #define MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14C, 1, 0x0, 0, MX51_PAD_CTRL_5) | 149 | #define _MX51_PAD_EIM_A21__EIM_A21 IOMUX_PAD(0x444, 0xb0, 0, 0x0000, 0, 0) |
| 171 | #define MX51_PAD_NANDF_RDY_INT__GPIO_3_24 IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL) | 150 | #define _MX51_PAD_EIM_A21__GPIO2_15 IOMUX_PAD(0x444, 0xb0, 1, 0x0000, 0, 0) |
| 172 | #define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x0, 0, MX51_PAD_CTRL_4) | 151 | #define _MX51_PAD_EIM_A22__EIM_A22 IOMUX_PAD(0x448, 0xb4, 0, 0x0000, 0, 0) |
| 173 | #define MX51_PAD_NANDF_D15__GPIO_3_25 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL) | 152 | #define _MX51_PAD_EIM_A22__GPIO2_16 IOMUX_PAD(0x448, 0xb4, 1, 0x0000, 0, 0) |
| 174 | #define MX51_PAD_NANDF_D15__ECSPI2_MOSI IOMUX_PAD(0x53C, 0x154, 2, 0x0, 0, MX51_ECSPI_PAD_CTRL) | 153 | #define _MX51_PAD_EIM_A23__BOOT_HPN_EN IOMUX_PAD(0x44c, 0xb8, 7, 0x0000, 0, 0) |
| 175 | #define MX51_PAD_NANDF_D14__GPIO_3_26 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL) | 154 | #define _MX51_PAD_EIM_A23__EIM_A23 IOMUX_PAD(0x44c, 0xb8, 0, 0x0000, 0, 0) |
| 176 | #define MX51_PAD_NANDF_D13__GPIO_3_27 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL) | 155 | #define _MX51_PAD_EIM_A23__GPIO2_17 IOMUX_PAD(0x44c, 0xb8, 1, 0x0000, 0, 0) |
| 177 | #define MX51_PAD_NANDF_D12__GPIO_3_28 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL) | 156 | #define _MX51_PAD_EIM_A24__EIM_A24 IOMUX_PAD(0x450, 0xbc, 0, 0x0000, 0, 0) |
| 178 | #define MX51_PAD_NANDF_D11__GPIO_3_29 IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL) | 157 | #define _MX51_PAD_EIM_A24__GPIO2_18 IOMUX_PAD(0x450, 0xbc, 1, 0x0000, 0, 0) |
| 179 | #define MX51_PAD_NANDF_D10__GPIO_3_30 IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL) | 158 | #define _MX51_PAD_EIM_A24__USBH2_CLK IOMUX_PAD(0x450, 0xbc, 2, 0x0000, 0, 0) |
| 180 | #define MX51_PAD_NANDF_D9__GPIO_3_31 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL) | 159 | #define _MX51_PAD_EIM_A25__DISP1_PIN4 IOMUX_PAD(0x454, 0xc0, 6, 0x0000, 0, 0) |
| 181 | #define MX51_PAD_NANDF_D8__GPIO_4_0 IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL) | 160 | #define _MX51_PAD_EIM_A25__EIM_A25 IOMUX_PAD(0x454, 0xc0, 0, 0x0000, 0, 0) |
| 182 | #define MX51_PAD_NANDF_D7__GPIO_4_1 IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL) | 161 | #define _MX51_PAD_EIM_A25__GPIO2_19 IOMUX_PAD(0x454, 0xc0, 1, 0x0000, 0, 0) |
| 183 | #define MX51_PAD_NANDF_D6__GPIO_4_2 IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL) | 162 | #define _MX51_PAD_EIM_A25__USBH2_DIR IOMUX_PAD(0x454, 0xc0, 2, 0x0000, 0, 0) |
| 184 | #define MX51_PAD_NANDF_D5__GPIO_4_3 IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL) | 163 | #define _MX51_PAD_EIM_A26__CSI1_DATA_EN IOMUX_PAD(0x458, 0xc4, 5, 0x09a0, 0, 0) |
| 185 | #define MX51_PAD_NANDF_D4__GPIO_4_4 IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL) | 164 | #define _MX51_PAD_EIM_A26__DISP2_EXT_CLK IOMUX_PAD(0x458, 0xc4, 6, 0x0908, 0, 0) |
| 186 | #define MX51_PAD_NANDF_D3__GPIO_4_5 IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL) | 165 | #define _MX51_PAD_EIM_A26__EIM_A26 IOMUX_PAD(0x458, 0xc4, 0, 0x0000, 0, 0) |
| 187 | #define MX51_PAD_NANDF_D2__GPIO_4_6 IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL) | 166 | #define _MX51_PAD_EIM_A26__GPIO2_20 IOMUX_PAD(0x458, 0xc4, 1, 0x0000, 0, 0) |
| 188 | #define MX51_PAD_NANDF_D1__GPIO_4_7 IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL) | 167 | #define _MX51_PAD_EIM_A26__USBH2_STP IOMUX_PAD(0x458, 0xc4, 2, 0x0000, 0, 0) |
| 189 | #define MX51_PAD_NANDF_D0__GPIO_4_8 IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL) | 168 | #define _MX51_PAD_EIM_A27__CSI2_DATA_EN IOMUX_PAD(0x45c, 0xc8, 5, 0x099c, 0, 0) |
| 190 | #define MX51_PAD_CSI1_D8__GPIO_3_12 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL) | 169 | #define _MX51_PAD_EIM_A27__DISP1_PIN1 IOMUX_PAD(0x45c, 0xc8, 6, 0x09a4, 0, 0) |
| 191 | #define MX51_PAD_CSI1_D9__GPIO_3_13 IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL) | 170 | #define _MX51_PAD_EIM_A27__EIM_A27 IOMUX_PAD(0x45c, 0xc8, 0, 0x0000, 0, 0) |
| 192 | #define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL) | 171 | #define _MX51_PAD_EIM_A27__GPIO2_21 IOMUX_PAD(0x45c, 0xc8, 1, 0x0000, 0, 0) |
| 193 | #define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL) | 172 | #define _MX51_PAD_EIM_A27__USBH2_NXT IOMUX_PAD(0x45c, 0xc8, 2, 0x0000, 0, 0) |
| 194 | #define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL) | 173 | #define _MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0xcc, 0, 0x0000, 0, 0) |
| 195 | #define MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL) | 174 | #define _MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0xd0, 0, 0x0000, 0, 0) |
| 196 | #define MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL) | 175 | #define _MX51_PAD_EIM_EB2__AUD5_RXFS IOMUX_PAD(0x468, 0xd4, 6, 0x08e0, 0, 0) |
| 197 | #define MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL) | 176 | #define _MX51_PAD_EIM_EB2__CSI1_D2 IOMUX_PAD(0x468, 0xd4, 5, 0x0000, 0, 0) |
| 198 | #define MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL) | 177 | #define _MX51_PAD_EIM_EB2__EIM_EB2 IOMUX_PAD(0x468, 0xd4, 0, 0x0000, 0, 0) |
| 199 | #define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL) | 178 | #define _MX51_PAD_EIM_EB2__FEC_MDIO IOMUX_PAD(0x468, 0xd4, 3, 0x0954, 0, 0) |
| 200 | #define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL) | 179 | #define _MX51_PAD_EIM_EB2__GPIO2_22 IOMUX_PAD(0x468, 0xd4, 1, 0x0000, 0, 0) |
| 201 | #define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL) | 180 | #define _MX51_PAD_EIM_EB2__GPT_CMPOUT1 IOMUX_PAD(0x468, 0xd4, 7, 0x0000, 0, 0) |
| 202 | #define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL) | 181 | #define _MX51_PAD_EIM_EB3__AUD5_RXC IOMUX_PAD(0x46c, 0xd8, 6, 0x08dc, 0, 0) |
| 203 | #define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL) | 182 | #define _MX51_PAD_EIM_EB3__CSI1_D3 IOMUX_PAD(0x46c, 0xd8, 5, 0x0000, 0, 0) |
| 204 | #define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5B4, 0x000, 0, 0x0, 0, NO_PAD_CTRL) | 183 | #define _MX51_PAD_EIM_EB3__EIM_EB3 IOMUX_PAD(0x46c, 0xd8, 0, 0x0000, 0, 0) |
| 205 | #define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5B8, 0x000, 0, 0x0, 0, NO_PAD_CTRL) | 184 | #define _MX51_PAD_EIM_EB3__FEC_RDATA1 IOMUX_PAD(0x46c, 0xd8, 3, 0x095c, 0, 0) |
| 206 | #define MX51_PAD_CSI1_PKE0__CSI1_PKE0 IOMUX_PAD(0x860, 0x000, 0, 0x0, 0, NO_PAD_CTRL) | 185 | #define _MX51_PAD_EIM_EB3__GPIO2_23 IOMUX_PAD(0x46c, 0xd8, 1, 0x0000, 0, 0) |
| 207 | #define MX51_PAD_CSI2_D12__GPIO_4_9 IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL) | 186 | #define _MX51_PAD_EIM_EB3__GPT_CMPOUT2 IOMUX_PAD(0x46c, 0xd8, 7, 0x0000, 0, 0) |
| 208 | #define MX51_PAD_CSI2_D13__GPIO_4_10 IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL) | 187 | #define _MX51_PAD_EIM_OE__EIM_OE IOMUX_PAD(0x470, 0xdc, 0, 0x0000, 0, 0) |
| 209 | #define MX51_PAD_CSI2_D14__GPIO_4_11 IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL) | 188 | #define _MX51_PAD_EIM_OE__GPIO2_24 IOMUX_PAD(0x470, 0xdc, 1, 0x0000, 0, 0) |
| 210 | #define MX51_PAD_CSI2_D15__GPIO_4_12 IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL) | 189 | #define _MX51_PAD_EIM_CS0__EIM_CS0 IOMUX_PAD(0x474, 0xe0, 0, 0x0000, 0, 0) |
| 211 | #define MX51_PAD_CSI2_D16__GPIO_4_11 IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL) | 190 | #define _MX51_PAD_EIM_CS0__GPIO2_25 IOMUX_PAD(0x474, 0xe0, 1, 0x0000, 0, 0) |
| 212 | #define MX51_PAD_CSI2_D17__GPIO_4_12 IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL) | 191 | #define _MX51_PAD_EIM_CS1__EIM_CS1 IOMUX_PAD(0x478, 0xe4, 0, 0x0000, 0, 0) |
| 213 | #define MX51_PAD_CSI2_D18__GPIO_4_11 IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL) | 192 | #define _MX51_PAD_EIM_CS1__GPIO2_26 IOMUX_PAD(0x478, 0xe4, 1, 0x0000, 0, 0) |
| 214 | #define MX51_PAD_CSI2_D19__GPIO_4_12 IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL) | 193 | #define _MX51_PAD_EIM_CS2__AUD5_TXD IOMUX_PAD(0x47c, 0xe8, 6, 0x08d8, 1, 0) |
| 215 | #define MX51_PAD_CSI2_VSYNC__GPIO_4_13 IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL) | 194 | #define _MX51_PAD_EIM_CS2__CSI1_D4 IOMUX_PAD(0x47c, 0xe8, 5, 0x0000, 0, 0) |
| 216 | #define MX51_PAD_CSI2_HSYNC__GPIO_4_14 IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL) | 195 | #define _MX51_PAD_EIM_CS2__EIM_CS2 IOMUX_PAD(0x47c, 0xe8, 0, 0x0000, 0, 0) |
| 217 | #define MX51_PAD_CSI2_PIXCLK__GPIO_4_15 IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL) | 196 | #define _MX51_PAD_EIM_CS2__FEC_RDATA2 IOMUX_PAD(0x47c, 0xe8, 3, 0x0960, 0, 0) |
| 218 | #define MX51_PAD_I2C1_CLK__GPIO_4_16 IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL) | 197 | #define _MX51_PAD_EIM_CS2__GPIO2_27 IOMUX_PAD(0x47c, 0xe8, 1, 0x0000, 0, 0) |
| 219 | #define MX51_PAD_I2C1_CLK__HSI2C_CLK IOMUX_PAD(0x5E8, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL) | 198 | #define _MX51_PAD_EIM_CS2__USBOTG_STP IOMUX_PAD(0x47c, 0xe8, 2, 0x0000, 0, 0) |
| 220 | #define MX51_PAD_I2C1_DAT__GPIO_4_17 IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL) | 199 | #define _MX51_PAD_EIM_CS3__AUD5_RXD IOMUX_PAD(0x480, 0xec, 6, 0x08d4, 1, 0) |
| 221 | #define MX51_PAD_I2C1_DAT__HSI2C_DAT IOMUX_PAD(0x5EC, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL) | 200 | #define _MX51_PAD_EIM_CS3__CSI1_D5 IOMUX_PAD(0x480, 0xec, 5, 0x0000, 0, 0) |
| 222 | #define MX51_PAD_AUD3_BB_TXD__AUD3_BB_TXD IOMUX_PAD(0x5F0, 0x200, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL) | 201 | #define _MX51_PAD_EIM_CS3__EIM_CS3 IOMUX_PAD(0x480, 0xec, 0, 0x0000, 0, 0) |
| 223 | #define MX51_PAD_AUD3_BB_TXD__GPIO_4_18 IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL) | 202 | #define _MX51_PAD_EIM_CS3__FEC_RDATA3 IOMUX_PAD(0x480, 0xec, 3, 0x0964, 0, 0) |
| 224 | #define MX51_PAD_AUD3_BB_RXD__AUD3_BB_RXD IOMUX_PAD(0x5F4, 0x204, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL) | 203 | #define _MX51_PAD_EIM_CS3__GPIO2_28 IOMUX_PAD(0x480, 0xec, 1, 0x0000, 0, 0) |
| 225 | #define MX51_PAD_AUD3_BB_RXD__GPIO_4_19 IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL) | 204 | #define _MX51_PAD_EIM_CS3__USBOTG_NXT IOMUX_PAD(0x480, 0xec, 2, 0x0000, 0, 0) |
| 226 | #define MX51_PAD_AUD3_BB_CK__AUD3_BB_CK IOMUX_PAD(0x5F8, 0x208, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL) | 205 | #define _MX51_PAD_EIM_CS4__AUD5_TXC IOMUX_PAD(0x484, 0xf0, 6, 0x08e4, 1, 0) |
| 227 | #define MX51_PAD_AUD3_BB_CK__GPIO_4_20 IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL) | 206 | #define _MX51_PAD_EIM_CS4__CSI1_D6 IOMUX_PAD(0x484, 0xf0, 5, 0x0000, 0, 0) |
| 228 | #define MX51_PAD_AUD3_BB_FS__AUD3_BB_FS IOMUX_PAD(0x5FC, 0x20C, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL) | 207 | #define _MX51_PAD_EIM_CS4__EIM_CS4 IOMUX_PAD(0x484, 0xf0, 0, 0x0000, 0, 0) |
| 229 | #define MX51_PAD_AUD3_BB_FS__GPIO_4_21 IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL) | 208 | #define _MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0xf0, 3, 0x0970, 0, 0) |
| 230 | #define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x600, 0x210, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) | 209 | #define _MX51_PAD_EIM_CS4__GPIO2_29 IOMUX_PAD(0x484, 0xf0, 1, 0x0000, 0, 0) |
| 231 | #define MX51_PAD_CSPI1_MOSI__GPIO_4_22 IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL) | 210 | #define _MX51_PAD_EIM_CS4__USBOTG_CLK IOMUX_PAD(0x484, 0xf0, 2, 0x0000, 0, 0) |
| 232 | #define MX51_PAD_CSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x604, 0x214, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) | 211 | #define _MX51_PAD_EIM_CS5__AUD5_TXFS IOMUX_PAD(0x488, 0xf4, 6, 0x08e8, 1, 0) |
| 233 | #define MX51_PAD_CSPI1_MISO__GPIO_4_23 IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL) | 212 | #define _MX51_PAD_EIM_CS5__CSI1_D7 IOMUX_PAD(0x488, 0xf4, 5, 0x0000, 0, 0) |
| 234 | #define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) | 213 | #define _MX51_PAD_EIM_CS5__DISP1_EXT_CLK IOMUX_PAD(0x488, 0xf4, 4, 0x0904, 0, 0) |
| 235 | #define MX51_PAD_CSPI1_SS0__GPIO_4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL) | 214 | #define _MX51_PAD_EIM_CS5__EIM_CS5 IOMUX_PAD(0x488, 0xf4, 0, 0x0000, 0, 0) |
| 236 | #define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 IOMUX_PAD(0x60C, 0x21C, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) | 215 | #define _MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x488, 0xf4, 3, 0x0950, 0, 0) |
| 237 | #define MX51_PAD_CSPI1_SS1__GPIO_4_25 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL) | 216 | #define _MX51_PAD_EIM_CS5__GPIO2_30 IOMUX_PAD(0x488, 0xf4, 1, 0x0000, 0, 0) |
| 238 | #define MX51_PAD_CSPI1_RDY__ECSPI1_RDY IOMUX_PAD(0x610, 0x220, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) | 217 | #define _MX51_PAD_EIM_CS5__USBOTG_DIR IOMUX_PAD(0x488, 0xf4, 2, 0x0000, 0, 0) |
| 239 | #define MX51_PAD_CSPI1_RDY__GPIO_4_26 IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL) | 218 | #define _MX51_PAD_EIM_DTACK__EIM_DTACK IOMUX_PAD(0x48c, 0xf8, 0, 0x0000, 0, 0) |
| 240 | #define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x614, 0x224, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) | 219 | #define _MX51_PAD_EIM_DTACK__GPIO2_31 IOMUX_PAD(0x48c, 0xf8, 1, 0x0000, 0, 0) |
| 241 | #define MX51_PAD_CSPI1_SCLK__GPIO_4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL) | 220 | #define _MX51_PAD_EIM_LBA__EIM_LBA IOMUX_PAD(0x494, 0xfc, 0, 0x0000, 0, 0) |
| 242 | #define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) | 221 | #define _MX51_PAD_EIM_LBA__GPIO3_1 IOMUX_PAD(0x494, 0xfc, 1, 0x0978, 0, 0) |
| 243 | #define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, 0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) | 222 | #define _MX51_PAD_EIM_CRE__EIM_CRE IOMUX_PAD(0x4a0, 0x100, 0, 0x0000, 0, 0) |
| 244 | #define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART1_PAD_CTRL) | 223 | #define _MX51_PAD_EIM_CRE__GPIO3_2 IOMUX_PAD(0x4a0, 0x100, 1, 0x097c, 0, 0) |
| 245 | #define MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, 0, 0x0, 0, MX51_UART1_PAD_CTRL) | 224 | #define _MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4d0, 0x104, 0, 0x0000, 0, 0) |
| 246 | #define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART2_PAD_CTRL) | 225 | #define _MX51_PAD_NANDF_WE_B__GPIO3_3 IOMUX_PAD(0x4e4, 0x108, 3, 0x0980, 0, 0) |
| 247 | #define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62C, 0x23C, 0, 0x0, 0, MX51_UART2_PAD_CTRL) | 226 | #define _MX51_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x4e4, 0x108, 0, 0x0000, 0, 0) |
| 248 | #define MX51_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART3_PAD_CTRL) | 227 | #define _MX51_PAD_NANDF_WE_B__PATA_DIOW IOMUX_PAD(0x4e4, 0x108, 1, 0x0000, 0, 0) |
| 249 | #define MX51_PAD_UART3_RXD__GPIO_1_22 IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL) | 228 | #define _MX51_PAD_NANDF_WE_B__SD3_DATA0 IOMUX_PAD(0x4e4, 0x108, 2, 0x093c, 0, 0) |
| 250 | #define MX51_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x634, 0x244, 1, 0x0, 0, MX51_UART3_PAD_CTRL) | 229 | #define _MX51_PAD_NANDF_RE_B__GPIO3_4 IOMUX_PAD(0x4e8, 0x10c, 3, 0x0984, 0, 0) |
| 251 | #define MX51_PAD_UART3_TXD__GPIO_1_23 IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL) | 230 | #define _MX51_PAD_NANDF_RE_B__NANDF_RE_B IOMUX_PAD(0x4e8, 0x10c, 0, 0x0000, 0, 0) |
| 252 | #define MX51_PAD_OWIRE_LINE__GPIO_1_24 IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL) | 231 | #define _MX51_PAD_NANDF_RE_B__PATA_DIOR IOMUX_PAD(0x4e8, 0x10c, 1, 0x0000, 0, 0) |
| 253 | #define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL) | 232 | #define _MX51_PAD_NANDF_RE_B__SD3_DATA1 IOMUX_PAD(0x4e8, 0x10c, 2, 0x0940, 0, 0) |
| 254 | #define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL) | 233 | #define _MX51_PAD_NANDF_ALE__GPIO3_5 IOMUX_PAD(0x4ec, 0x110, 3, 0x0988, 0, 0) |
| 255 | #define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL) | 234 | #define _MX51_PAD_NANDF_ALE__NANDF_ALE IOMUX_PAD(0x4ec, 0x110, 0, 0x0000, 0, 0) |
| 256 | #define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL) | 235 | #define _MX51_PAD_NANDF_ALE__PATA_BUFFER_EN IOMUX_PAD(0x4ec, 0x110, 1, 0x0000, 0, 0) |
| 257 | #define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL) | 236 | #define _MX51_PAD_NANDF_CLE__GPIO3_6 IOMUX_PAD(0x4f0, 0x114, 3, 0x098c, 0, 0) |
| 258 | #define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL) | 237 | #define _MX51_PAD_NANDF_CLE__NANDF_CLE IOMUX_PAD(0x4f0, 0x114, 0, 0x0000, 0, 0) |
| 259 | #define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL) | 238 | #define _MX51_PAD_NANDF_CLE__PATA_RESET_B IOMUX_PAD(0x4f0, 0x114, 1, 0x0000, 0, 0) |
| 260 | #define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL) | 239 | #define _MX51_PAD_NANDF_WP_B__GPIO3_7 IOMUX_PAD(0x4f4, 0x118, 3, 0x0990, 0, 0) |
| 261 | #define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL) | 240 | #define _MX51_PAD_NANDF_WP_B__NANDF_WP_B IOMUX_PAD(0x4f4, 0x118, 0, 0x0000, 0, 0) |
| 262 | #define MX51_PAD_KEY_COL4__UART3_RTS IOMUX_PAD(0x65C, 0x26C, 2, 0x9f0, 4, MX51_UART3_PAD_CTRL) | 241 | #define _MX51_PAD_NANDF_WP_B__PATA_DMACK IOMUX_PAD(0x4f4, 0x118, 1, 0x0000, 0, 0) |
| 263 | #define MX51_PAD_KEY_COL4__I2C2_SCL IOMUX_PAD(0x65C, 0x26C, (3 | IOMUX_CONFIG_SION), \ | 242 | #define _MX51_PAD_NANDF_WP_B__SD3_DATA2 IOMUX_PAD(0x4f4, 0x118, 2, 0x0944, 0, 0) |
| 264 | 0x09b8, 1, MX51_I2C_PAD_CTRL) | 243 | #define _MX51_PAD_NANDF_RB0__ECSPI2_SS1 IOMUX_PAD(0x4f8, 0x11c, 5, 0x0930, 0, 0) |
| 265 | #define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL) | 244 | #define _MX51_PAD_NANDF_RB0__GPIO3_8 IOMUX_PAD(0x4f8, 0x11c, 3, 0x0994, 0, 0) |
| 266 | #define MX51_PAD_KEY_COL5__UART3_CTS IOMUX_PAD(0x660, 0x270, 2, 0, 0, MX51_UART3_PAD_CTRL) | 245 | #define _MX51_PAD_NANDF_RB0__NANDF_RB0 IOMUX_PAD(0x4f8, 0x11c, 0, 0x0000, 0, 0) |
| 267 | #define MX51_PAD_KEY_COL5__I2C2_SDA IOMUX_PAD(0x660, 0x270, (3 | IOMUX_CONFIG_SION), \ | 246 | #define _MX51_PAD_NANDF_RB0__PATA_DMARQ IOMUX_PAD(0x4f8, 0x11c, 1, 0x0000, 0, 0) |
| 268 | 0x09bc, 1, MX51_I2C_PAD_CTRL) | 247 | #define _MX51_PAD_NANDF_RB0__SD3_DATA3 IOMUX_PAD(0x4f8, 0x11c, 2, 0x0948, 0, 0) |
| 269 | #define MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) | 248 | #define _MX51_PAD_NANDF_RB1__CSPI_MOSI IOMUX_PAD(0x4fc, 0x120, 6, 0x091c, 0, 0) |
| 270 | #define MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) | 249 | #define _MX51_PAD_NANDF_RB1__ECSPI2_RDY IOMUX_PAD(0x4fc, 0x120, 2, 0x0000, 0, 0) |
| 271 | #define MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) | 250 | #define _MX51_PAD_NANDF_RB1__GPIO3_9 IOMUX_PAD(0x4fc, 0x120, 3, 0x0000, 0, 0) |
| 272 | #define MX51_PAD_USBH1_STP__GPIO_1_27 IOMUX_PAD(0x680, 0x280, 2, 0x0, 0, MX51_USBH1_PAD_CTRL) | 251 | #define _MX51_PAD_NANDF_RB1__NANDF_RB1 IOMUX_PAD(0x4fc, 0x120, 0, 0x0000, 0, 0) |
| 273 | #define MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) | 252 | #define _MX51_PAD_NANDF_RB1__PATA_IORDY IOMUX_PAD(0x4fc, 0x120, 1, 0x0000, 0, 0) |
| 274 | #define MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) | 253 | #define _MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 5, 0x0000, 0, 0) |
| 275 | #define MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) | 254 | #define _MX51_PAD_NANDF_RB2__DISP2_WAIT IOMUX_PAD(0x500, 0x124, 5, 0x09a8, 0, 0) |
| 276 | #define MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) | 255 | #define _MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, 0x0000, 0, 0) |
| 277 | #define MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) | 256 | #define _MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x094c, 0, 0) |
| 278 | #define MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) | 257 | #define _MX51_PAD_NANDF_RB2__GPIO3_10 IOMUX_PAD(0x500, 0x124, 3, 0x0000, 0, 0) |
| 279 | #define MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) | 258 | #define _MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, 0x0000, 0, 0) |
| 280 | #define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) | 259 | #define _MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 7, 0x0000, 0, 0) |
| 281 | #define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) | 260 | #define _MX51_PAD_NANDF_RB2__USBH3_NXT IOMUX_PAD(0x500, 0x124, 6, 0x0a20, 0, 0) |
| 282 | #define MX51_PAD_DI1_PIN11__GPIO_3_0 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL) | 261 | #define _MX51_PAD_NANDF_RB3__DISP1_WAIT IOMUX_PAD(0x504, 0x128, 5, 0x0000, 0, 0) |
| 283 | #define MX51_PAD_DI1_PIN12__GPIO_3_1 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x978, 1, NO_PAD_CTRL) | 262 | #define _MX51_PAD_NANDF_RB3__ECSPI2_MISO IOMUX_PAD(0x504, 0x128, 2, 0x0000, 0, 0) |
| 284 | #define MX51_PAD_DI1_PIN13__GPIO_3_2 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x97c, 1, NO_PAD_CTRL) | 263 | #define _MX51_PAD_NANDF_RB3__FEC_RX_CLK IOMUX_PAD(0x504, 0x128, 1, 0x0968, 0, 0) |
| 285 | #define MX51_PAD_DI1_D0_CS__GPIO_3_3 IOMUX_PAD(0x6B4, 0x2B4, 4, 0x980, 1, NO_PAD_CTRL) | 264 | #define _MX51_PAD_NANDF_RB3__GPIO3_11 IOMUX_PAD(0x504, 0x128, 3, 0x0000, 0, 0) |
| 286 | #define MX51_PAD_DI1_D1_CS__GPIO_3_4 IOMUX_PAD(0x6B8, 0x2B8, 4, 0x984, 1, NO_PAD_CTRL) | 265 | #define _MX51_PAD_NANDF_RB3__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 0, 0x0000, 0, 0) |
| 287 | #define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5 IOMUX_PAD(0x6BC, 0x2BC, 4, 0x988, 1, NO_PAD_CTRL) | 266 | #define _MX51_PAD_NANDF_RB3__USBH3_CLK IOMUX_PAD(0x504, 0x128, 6, 0x09f8, 0, 0) |
| 288 | #define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6 IOMUX_PAD(0x6C0, 0x2C0, 4, 0x98c, 1, NO_PAD_CTRL) | 267 | #define _MX51_PAD_NANDF_RB3__USBH3_H3_DM IOMUX_PAD(0x504, 0x128, 7, 0x0000, 0, 0) |
| 289 | #define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7 IOMUX_PAD(0x6C4, 0x2C4, 4, 0x990, 1, NO_PAD_CTRL) | 268 | #define _MX51_PAD_GPIO_NAND__GPIO_NAND IOMUX_PAD(0x514, 0x12c, 0, 0x0998, 0, 0) |
| 290 | #define MX51_PAD_DISPB2_SER_RS__GPIO_3_8 IOMUX_PAD(0x6C8, 0x2C8, 4, 0x994, 1, NO_PAD_CTRL) | 269 | #define _MX51_PAD_GPIO_NAND__PATA_INTRQ IOMUX_PAD(0x514, 0x12c, 1, 0x0000, 0, 0) |
| 291 | #define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL) | 270 | #define _MX51_PAD_NANDF_CS0__GPIO3_16 IOMUX_PAD(0x518, 0x130, 3, 0x0000, 0, 0) |
| 292 | #define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL) | 271 | #define _MX51_PAD_NANDF_CS0__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 0, 0x0000, 0, 0) |
| 293 | #define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL) | 272 | #define _MX51_PAD_NANDF_CS1__GPIO3_17 IOMUX_PAD(0x51c, 0x134, 3, 0x0000, 0, 0) |
| 294 | #define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL) | 273 | #define _MX51_PAD_NANDF_CS1__NANDF_CS1 IOMUX_PAD(0x51c, 0x134, 0, 0x0000, 0, 0) |
| 295 | #define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL) | 274 | #define _MX51_PAD_NANDF_CS2__CSPI_SCLK IOMUX_PAD(0x520, 0x138, 6, 0x0914, 0, 0) |
| 296 | #define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL) | 275 | #define _MX51_PAD_NANDF_CS2__FEC_TX_ER IOMUX_PAD(0x520, 0x138, 2, 0x0000, 0, 0) |
| 297 | #define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL) | 276 | #define _MX51_PAD_NANDF_CS2__GPIO3_18 IOMUX_PAD(0x520, 0x138, 3, 0x0000, 0, 0) |
| 298 | #define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL) | 277 | #define _MX51_PAD_NANDF_CS2__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 0, 0x0000, 0, 0) |
| 299 | #define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL) | 278 | #define _MX51_PAD_NANDF_CS2__PATA_CS_0 IOMUX_PAD(0x520, 0x138, 1, 0x0000, 0, 0) |
| 300 | #define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL) | 279 | #define _MX51_PAD_NANDF_CS2__SD4_CLK IOMUX_PAD(0x520, 0x138, 5, 0x0000, 0, 0) |
| 301 | #define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL) | 280 | #define _MX51_PAD_NANDF_CS2__USBH3_H1_DP IOMUX_PAD(0x520, 0x138, 7, 0x0000, 0, 0) |
| 302 | #define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL) | 281 | #define _MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13c, 2, 0x0000, 0, 0) |
| 303 | #define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL) | 282 | #define _MX51_PAD_NANDF_CS3__GPIO3_19 IOMUX_PAD(0x524, 0x13c, 3, 0x0000, 0, 0) |
| 304 | #define MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL) | 283 | #define _MX51_PAD_NANDF_CS3__NANDF_CS3 IOMUX_PAD(0x524, 0x13c, 0, 0x0000, 0, 0) |
| 305 | #define MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL) | 284 | #define _MX51_PAD_NANDF_CS3__PATA_CS_1 IOMUX_PAD(0x524, 0x13c, 1, 0x0000, 0, 0) |
| 306 | #define MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL) | 285 | #define _MX51_PAD_NANDF_CS3__SD4_DAT0 IOMUX_PAD(0x524, 0x13c, 5, 0x0000, 0, 0) |
| 307 | #define MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL) | 286 | #define _MX51_PAD_NANDF_CS3__USBH3_H1_DM IOMUX_PAD(0x524, 0x13c, 7, 0x0000, 0, 0) |
| 308 | #define MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL) | 287 | #define _MX51_PAD_NANDF_CS4__FEC_TDATA1 IOMUX_PAD(0x528, 0x140, 2, 0x0000, 0, 0) |
| 309 | #define MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL) | 288 | #define _MX51_PAD_NANDF_CS4__GPIO3_20 IOMUX_PAD(0x528, 0x140, 3, 0x0000, 0, 0) |
| 310 | #define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL) | 289 | #define _MX51_PAD_NANDF_CS4__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 0, 0x0000, 0, 0) |
| 311 | #define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL) | 290 | #define _MX51_PAD_NANDF_CS4__PATA_DA_0 IOMUX_PAD(0x528, 0x140, 1, 0x0000, 0, 0) |
| 312 | #define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL) | 291 | #define _MX51_PAD_NANDF_CS4__SD4_DAT1 IOMUX_PAD(0x528, 0x140, 5, 0x0000, 0, 0) |
| 313 | #define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL) | 292 | #define _MX51_PAD_NANDF_CS4__USBH3_STP IOMUX_PAD(0x528, 0x140, 7, 0x0a24, 0, 0) |
| 314 | #define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL) | 293 | #define _MX51_PAD_NANDF_CS5__FEC_TDATA2 IOMUX_PAD(0x52c, 0x144, 2, 0x0000, 0, 0) |
| 315 | #define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL) | 294 | #define _MX51_PAD_NANDF_CS5__GPIO3_21 IOMUX_PAD(0x52c, 0x144, 3, 0x0000, 0, 0) |
| 316 | #define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL) | 295 | #define _MX51_PAD_NANDF_CS5__NANDF_CS5 IOMUX_PAD(0x52c, 0x144, 0, 0x0000, 0, 0) |
| 317 | #define MX51_PAD_DI_GP1__DI_GP1 IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL) | 296 | #define _MX51_PAD_NANDF_CS5__PATA_DA_1 IOMUX_PAD(0x52c, 0x144, 1, 0x0000, 0, 0) |
| 318 | #define MX51_PAD_DI_GP2__DI_GP2 IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL) | 297 | #define _MX51_PAD_NANDF_CS5__SD4_DAT2 IOMUX_PAD(0x52c, 0x144, 5, 0x0000, 0, 0) |
| 319 | #define MX51_PAD_DI_GP3__DI_GP3 IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL) | 298 | #define _MX51_PAD_NANDF_CS5__USBH3_DIR IOMUX_PAD(0x52c, 0x144, 7, 0x0a1c, 0, 0) |
| 320 | #define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL) | 299 | #define _MX51_PAD_NANDF_CS6__CSPI_SS3 IOMUX_PAD(0x530, 0x148, 7, 0x0928, 0, 0) |
| 321 | #define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL) | 300 | #define _MX51_PAD_NANDF_CS6__FEC_TDATA3 IOMUX_PAD(0x530, 0x148, 2, 0x0000, 0, 0) |
| 322 | #define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL) | 301 | #define _MX51_PAD_NANDF_CS6__GPIO3_22 IOMUX_PAD(0x530, 0x148, 3, 0x0000, 0, 0) |
| 323 | #define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL) | 302 | #define _MX51_PAD_NANDF_CS6__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 0, 0x0000, 0, 0) |
| 324 | #define MX51_PAD_DI_GP4__DI_GP4 IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL) | 303 | #define _MX51_PAD_NANDF_CS6__PATA_DA_2 IOMUX_PAD(0x530, 0x148, 1, 0x0000, 0, 0) |
| 325 | #define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL) | 304 | #define _MX51_PAD_NANDF_CS6__SD4_DAT3 IOMUX_PAD(0x530, 0x148, 5, 0x0000, 0, 0) |
| 326 | #define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL) | 305 | #define _MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14c, 1, 0x0000, 0, 0) |
| 327 | #define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL) | 306 | #define _MX51_PAD_NANDF_CS7__GPIO3_23 IOMUX_PAD(0x534, 0x14c, 3, 0x0000, 0, 0) |
| 328 | #define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL) | 307 | #define _MX51_PAD_NANDF_CS7__NANDF_CS7 IOMUX_PAD(0x534, 0x14c, 0, 0x0000, 0, 0) |
| 329 | #define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL) | 308 | #define _MX51_PAD_NANDF_CS7__SD3_CLK IOMUX_PAD(0x534, 0x14c, 5, 0x0000, 0, 0) |
| 330 | #define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL) | 309 | #define _MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 IOMUX_PAD(0x538, 0x150, 2, 0x0000, 0, 0) |
| 331 | #define MX51_PAD_DISP2_DAT6__GPIO_1_19 IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL) | 310 | #define _MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x0974, 0, 0) |
| 332 | #define MX51_PAD_DISP2_DAT7__GPIO_1_29 IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL) | 311 | #define _MX51_PAD_NANDF_RDY_INT__GPIO3_24 IOMUX_PAD(0x538, 0x150, 3, 0x0000, 0, 0) |
| 333 | #define MX51_PAD_DISP2_DAT8__GPIO_1_30 IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL) | 312 | #define _MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 0, 0x0938, 0, 0) |
| 334 | #define MX51_PAD_DISP2_DAT9__GPIO_1_31 IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL) | 313 | #define _MX51_PAD_NANDF_RDY_INT__SD3_CMD IOMUX_PAD(0x538, 0x150, 5, 0x0000, 0, 0) |
| 335 | #define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL) | 314 | #define _MX51_PAD_NANDF_D15__ECSPI2_MOSI IOMUX_PAD(0x53c, 0x154, 2, 0x0000, 0, 0) |
| 336 | #define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL) | 315 | #define _MX51_PAD_NANDF_D15__GPIO3_25 IOMUX_PAD(0x53c, 0x154, 3, 0x0000, 0, 0) |
| 337 | #define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL) | 316 | #define _MX51_PAD_NANDF_D15__NANDF_D15 IOMUX_PAD(0x53c, 0x154, 0, 0x0000, 0, 0) |
| 338 | #define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL) | 317 | #define _MX51_PAD_NANDF_D15__PATA_DATA15 IOMUX_PAD(0x53c, 0x154, 1, 0x0000, 0, 0) |
| 339 | #define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL) | 318 | #define _MX51_PAD_NANDF_D15__SD3_DAT7 IOMUX_PAD(0x53c, 0x154, 5, 0x0000, 0, 0) |
| 340 | #define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL) | 319 | #define _MX51_PAD_NANDF_D14__ECSPI2_SS3 IOMUX_PAD(0x540, 0x158, 2, 0x0934, 0, 0) |
| 341 | #define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, IOMUX_CONFIG_SION, 0x0, 0, \ | 320 | #define _MX51_PAD_NANDF_D14__GPIO3_26 IOMUX_PAD(0x540, 0x158, 3, 0x0000, 0, 0) |
| 342 | MX51_SDHCI_PAD_CTRL) | 321 | #define _MX51_PAD_NANDF_D14__NANDF_D14 IOMUX_PAD(0x540, 0x158, 0, 0x0000, 0, 0) |
| 343 | #define MX51_PAD_SD1_CMD__AUD5_RXFS IOMUX_PAD(0x79C, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL) | 322 | #define _MX51_PAD_NANDF_D14__PATA_DATA14 IOMUX_PAD(0x540, 0x158, 1, 0x0000, 0, 0) |
| 344 | #define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, IOMUX_CONFIG_SION, 0x0, 0, \ | 323 | #define _MX51_PAD_NANDF_D14__SD3_DAT6 IOMUX_PAD(0x540, 0x158, 5, 0x0000, 0, 0) |
| 345 | MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) | 324 | #define _MX51_PAD_NANDF_D13__ECSPI2_SS2 IOMUX_PAD(0x544, 0x15c, 2, 0x0000, 0, 0) |
| 346 | #define MX51_PAD_SD1_CLK__AUD5_RXC IOMUX_PAD(0x7A0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL) | 325 | #define _MX51_PAD_NANDF_D13__GPIO3_27 IOMUX_PAD(0x544, 0x15c, 3, 0x0000, 0, 0) |
| 347 | #define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, IOMUX_CONFIG_SION, 0x0, 0, \ | 326 | #define _MX51_PAD_NANDF_D13__NANDF_D13 IOMUX_PAD(0x544, 0x15c, 0, 0x0000, 0, 0) |
| 348 | MX51_SDHCI_PAD_CTRL) | 327 | #define _MX51_PAD_NANDF_D13__PATA_DATA13 IOMUX_PAD(0x544, 0x15c, 1, 0x0000, 0, 0) |
| 349 | #define MX51_PAD_SD1_DATA0__AUD5_TXD IOMUX_PAD(0x7A4, 0x39C, 1, 0x8d8, 2, NO_PAD_CTRL) | 328 | #define _MX51_PAD_NANDF_D13__SD3_DAT5 IOMUX_PAD(0x544, 0x15c, 5, 0x0000, 0, 0) |
| 350 | #define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, IOMUX_CONFIG_SION, 0x0, 0, \ | 329 | #define _MX51_PAD_NANDF_D12__ECSPI2_SS1 IOMUX_PAD(0x548, 0x160, 2, 0x0930, 1, 0) |
| 351 | MX51_SDHCI_PAD_CTRL) | 330 | #define _MX51_PAD_NANDF_D12__GPIO3_28 IOMUX_PAD(0x548, 0x160, 3, 0x0000, 0, 0) |
| 352 | #define MX51_PAD_SD1_DATA1__AUD5_RXD IOMUX_PAD(0x7A8, 0x3A0, 1, 0x8d4, 2, NO_PAD_CTRL) | 331 | #define _MX51_PAD_NANDF_D12__NANDF_D12 IOMUX_PAD(0x548, 0x160, 0, 0x0000, 0, 0) |
| 353 | #define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, IOMUX_CONFIG_SION, 0x0, 0, \ | 332 | #define _MX51_PAD_NANDF_D12__PATA_DATA12 IOMUX_PAD(0x548, 0x160, 1, 0x0000, 0, 0) |
| 354 | MX51_SDHCI_PAD_CTRL) | 333 | #define _MX51_PAD_NANDF_D12__SD3_DAT4 IOMUX_PAD(0x548, 0x160, 5, 0x0000, 0, 0) |
| 355 | #define MX51_PAD_SD1_DATA2__AUD5_TXC IOMUX_PAD(0x7AC, 0x3A4, 1, 0x8e4, 2, NO_PAD_CTRL) | 334 | #define _MX51_PAD_NANDF_D11__FEC_RX_DV IOMUX_PAD(0x54c, 0x164, 2, 0x096c, 0, 0) |
| 356 | #define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, IOMUX_CONFIG_SION, 0x0, 0, \ | 335 | #define _MX51_PAD_NANDF_D11__GPIO3_29 IOMUX_PAD(0x54c, 0x164, 3, 0x0000, 0, 0) |
| 357 | MX51_SDHCI_PAD_CTRL) | 336 | #define _MX51_PAD_NANDF_D11__NANDF_D11 IOMUX_PAD(0x54c, 0x164, 0, 0x0000, 0, 0) |
| 358 | #define MX51_PAD_SD1_DATA3__AUD5_TXFS IOMUX_PAD(0x7B0, 0x3A8, 1, 0x8e8, 2, NO_PAD_CTRL) | 337 | #define _MX51_PAD_NANDF_D11__PATA_DATA11 IOMUX_PAD(0x54c, 0x164, 1, 0x0000, 0, 0) |
| 359 | #define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, IOMUX_CONFIG_SION, 0x0, 1, \ | 338 | #define _MX51_PAD_NANDF_D11__SD3_DATA3 IOMUX_PAD(0x54c, 0x164, 5, 0x0948, 1, 0) |
| 360 | MX51_SDHCI_PAD_CTRL) | 339 | #define _MX51_PAD_NANDF_D10__GPIO3_30 IOMUX_PAD(0x550, 0x168, 3, 0x0000, 0, 0) |
| 361 | #define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, IOMUX_CONFIG_SION, 0x0, 0, \ | 340 | #define _MX51_PAD_NANDF_D10__NANDF_D10 IOMUX_PAD(0x550, 0x168, 0, 0x0000, 0, 0) |
| 362 | MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) | 341 | #define _MX51_PAD_NANDF_D10__PATA_DATA10 IOMUX_PAD(0x550, 0x168, 1, 0x0000, 0, 0) |
| 363 | #define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, IOMUX_CONFIG_SION, 0x0, 0, \ | 342 | #define _MX51_PAD_NANDF_D10__SD3_DATA2 IOMUX_PAD(0x550, 0x168, 5, 0x0944, 1, 0) |
| 364 | MX51_SDHCI_PAD_CTRL) | 343 | #define _MX51_PAD_NANDF_D9__FEC_RDATA0 IOMUX_PAD(0x554, 0x16c, 0x12, 0x0958, 0, 0) |
| 365 | #define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, IOMUX_CONFIG_SION, 0x0, 0, \ | 344 | #define _MX51_PAD_NANDF_D9__GPIO3_31 IOMUX_PAD(0x554, 0x16c, 3, 0x0000, 0, 0) |
| 366 | MX51_SDHCI_PAD_CTRL) | 345 | #define _MX51_PAD_NANDF_D9__NANDF_D9 IOMUX_PAD(0x554, 0x16c, 0, 0x0000, 0, 0) |
| 367 | #define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, IOMUX_CONFIG_SION, 0x0, 0, \ | 346 | #define _MX51_PAD_NANDF_D9__PATA_DATA9 IOMUX_PAD(0x554, 0x16c, 1, 0x0000, 0, 0) |
| 368 | MX51_SDHCI_PAD_CTRL) | 347 | #define _MX51_PAD_NANDF_D9__SD3_DATA1 IOMUX_PAD(0x554, 0x16c, 5, 0x0940, 1, 0) |
| 369 | #define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, IOMUX_CONFIG_SION, 0x0, 0, \ | 348 | #define _MX51_PAD_NANDF_D8__FEC_TDATA0 IOMUX_PAD(0x558, 0x170, 2, 0x0000, 0, 0) |
| 370 | MX51_SDHCI_PAD_CTRL) | 349 | #define _MX51_PAD_NANDF_D8__GPIO4_0 IOMUX_PAD(0x558, 0x170, 3, 0x0000, 0, 0) |
| 371 | #define MX51_PAD_GPIO_1_0__GPIO_1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) | 350 | #define _MX51_PAD_NANDF_D8__NANDF_D8 IOMUX_PAD(0x558, 0x170, 0, 0x0000, 0, 0) |
| 372 | #define MX51_PAD_GPIO_1_1__GPIO_1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) | 351 | #define _MX51_PAD_NANDF_D8__PATA_DATA8 IOMUX_PAD(0x558, 0x170, 1, 0x0000, 0, 0) |
| 373 | #define MX51_PAD_GPIO_1_2__GPIO_1_2 IOMUX_PAD(0x7D4, 0x3CC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) | 352 | #define _MX51_PAD_NANDF_D8__SD3_DATA0 IOMUX_PAD(0x558, 0x170, 5, 0x093c, 1, 0) |
| 374 | #define MX51_PAD_GPIO_1_2__I2C2_SCL IOMUX_PAD(0x7D4, 0x3CC, (2 | IOMUX_CONFIG_SION), \ | 353 | #define _MX51_PAD_NANDF_D7__GPIO4_1 IOMUX_PAD(0x55c, 0x174, 3, 0x0000, 0, 0) |
| 375 | 0x9b8, 3, MX51_I2C_PAD_CTRL) | 354 | #define _MX51_PAD_NANDF_D7__NANDF_D7 IOMUX_PAD(0x55c, 0x174, 0, 0x0000, 0, 0) |
| 376 | #define MX51_PAD_GPIO_1_3__GPIO_1_3 IOMUX_PAD(0x7D8, 0x3D0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) | 355 | #define _MX51_PAD_NANDF_D7__PATA_DATA7 IOMUX_PAD(0x55c, 0x174, 1, 0x0000, 0, 0) |
| 377 | #define MX51_PAD_GPIO_1_3__I2C2_SDA IOMUX_PAD(0x7D8, 0x3D0, (2 | IOMUX_CONFIG_SION), \ | 356 | #define _MX51_PAD_NANDF_D7__USBH3_DATA0 IOMUX_PAD(0x55c, 0x174, 5, 0x09fc, 0, 0) |
| 378 | 0x9bc, 3, MX51_I2C_PAD_CTRL) | 357 | #define _MX51_PAD_NANDF_D6__GPIO4_2 IOMUX_PAD(0x560, 0x178, 3, 0x0000, 0, 0) |
| 379 | #define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL) | 358 | #define _MX51_PAD_NANDF_D6__NANDF_D6 IOMUX_PAD(0x560, 0x178, 0, 0x0000, 0, 0) |
| 380 | #define MX51_PAD_GPIO_1_4__GPIO_1_4 IOMUX_PAD(0x804, 0x3D8, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) | 359 | #define _MX51_PAD_NANDF_D6__PATA_DATA6 IOMUX_PAD(0x560, 0x178, 1, 0x0000, 0, 0) |
| 381 | #define MX51_PAD_GPIO_1_5__GPIO_1_5 IOMUX_PAD(0x808, 0x3DC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) | 360 | #define _MX51_PAD_NANDF_D6__SD4_LCTL IOMUX_PAD(0x560, 0x178, 2, 0x0000, 0, 0) |
| 382 | #define MX51_PAD_GPIO_1_6__GPIO_1_6 IOMUX_PAD(0x80C, 0x3E0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) | 361 | #define _MX51_PAD_NANDF_D6__USBH3_DATA1 IOMUX_PAD(0x560, 0x178, 5, 0x0a00, 0, 0) |
| 383 | #define MX51_PAD_GPIO_1_7__GPIO_1_7 IOMUX_PAD(0x810, 0x3E4, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) | 362 | #define _MX51_PAD_NANDF_D5__GPIO4_3 IOMUX_PAD(0x564, 0x17c, 3, 0x0000, 0, 0) |
| 384 | #define MX51_PAD_GPIO_1_8__GPIO_1_8 IOMUX_PAD(0x814, 0x3E8, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) | 363 | #define _MX51_PAD_NANDF_D5__NANDF_D5 IOMUX_PAD(0x564, 0x17c, 0, 0x0000, 0, 0) |
| 385 | #define MX51_PAD_GPIO_1_9__GPIO_1_9 IOMUX_PAD(0x818, 0x3EC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) | 364 | #define _MX51_PAD_NANDF_D5__PATA_DATA5 IOMUX_PAD(0x564, 0x17c, 1, 0x0000, 0, 0) |
| 365 | #define _MX51_PAD_NANDF_D5__SD4_WP IOMUX_PAD(0x564, 0x17c, 2, 0x0000, 0, 0) | ||
| 366 | #define _MX51_PAD_NANDF_D5__USBH3_DATA2 IOMUX_PAD(0x564, 0x17c, 5, 0x0a04, 0, 0) | ||
| 367 | #define _MX51_PAD_NANDF_D4__GPIO4_4 IOMUX_PAD(0x568, 0x180, 3, 0x0000, 0, 0) | ||
| 368 | #define _MX51_PAD_NANDF_D4__NANDF_D4 IOMUX_PAD(0x568, 0x180, 0, 0x0000, 0, 0) | ||
| 369 | #define _MX51_PAD_NANDF_D4__PATA_DATA4 IOMUX_PAD(0x568, 0x180, 1, 0x0000, 0, 0) | ||
| 370 | #define _MX51_PAD_NANDF_D4__SD4_CD IOMUX_PAD(0x568, 0x180, 2, 0x0000, 0, 0) | ||
| 371 | #define _MX51_PAD_NANDF_D4__USBH3_DATA3 IOMUX_PAD(0x568, 0x180, 5, 0x0a08, 0, 0) | ||
| 372 | #define _MX51_PAD_NANDF_D3__GPIO4_5 IOMUX_PAD(0x56c, 0x184, 3, 0x0000, 0, 0) | ||
| 373 | #define _MX51_PAD_NANDF_D3__NANDF_D3 IOMUX_PAD(0x56c, 0x184, 0, 0x0000, 0, 0) | ||
| 374 | #define _MX51_PAD_NANDF_D3__PATA_DATA3 IOMUX_PAD(0x56c, 0x184, 1, 0x0000, 0, 0) | ||
| 375 | #define _MX51_PAD_NANDF_D3__SD4_DAT4 IOMUX_PAD(0x56c, 0x184, 2, 0x0000, 0, 0) | ||
| 376 | #define _MX51_PAD_NANDF_D3__USBH3_DATA4 IOMUX_PAD(0x56c, 0x184, 5, 0x0a0c, 0, 0) | ||
| 377 | #define _MX51_PAD_NANDF_D2__GPIO4_6 IOMUX_PAD(0x570, 0x188, 3, 0x0000, 0, 0) | ||
| 378 | #define _MX51_PAD_NANDF_D2__NANDF_D2 IOMUX_PAD(0x570, 0x188, 0, 0x0000, 0, 0) | ||
| 379 | #define _MX51_PAD_NANDF_D2__PATA_DATA2 IOMUX_PAD(0x570, 0x188, 1, 0x0000, 0, 0) | ||
| 380 | #define _MX51_PAD_NANDF_D2__SD4_DAT5 IOMUX_PAD(0x570, 0x188, 2, 0x0000, 0, 0) | ||
| 381 | #define _MX51_PAD_NANDF_D2__USBH3_DATA5 IOMUX_PAD(0x570, 0x188, 5, 0x0a10, 0, 0) | ||
| 382 | #define _MX51_PAD_NANDF_D1__GPIO4_7 IOMUX_PAD(0x574, 0x18c, 3, 0x0000, 0, 0) | ||
| 383 | #define _MX51_PAD_NANDF_D1__NANDF_D1 IOMUX_PAD(0x574, 0x18c, 0, 0x0000, 0, 0) | ||
| 384 | #define _MX51_PAD_NANDF_D1__PATA_DATA1 IOMUX_PAD(0x574, 0x18c, 1, 0x0000, 0, 0) | ||
| 385 | #define _MX51_PAD_NANDF_D1__SD4_DAT6 IOMUX_PAD(0x574, 0x18c, 2, 0x0000, 0, 0) | ||
| 386 | #define _MX51_PAD_NANDF_D1__USBH3_DATA6 IOMUX_PAD(0x574, 0x18c, 5, 0x0a14, 0, 0) | ||
| 387 | #define _MX51_PAD_NANDF_D0__GPIO4_8 IOMUX_PAD(0x578, 0x190, 3, 0x0000, 0, 0) | ||
| 388 | #define _MX51_PAD_NANDF_D0__NANDF_D0 IOMUX_PAD(0x578, 0x190, 0, 0x0000, 0, 0) | ||
| 389 | #define _MX51_PAD_NANDF_D0__PATA_DATA0 IOMUX_PAD(0x578, 0x190, 1, 0x0000, 0, 0) | ||
| 390 | #define _MX51_PAD_NANDF_D0__SD4_DAT7 IOMUX_PAD(0x578, 0x190, 2, 0x0000, 0, 0) | ||
| 391 | #define _MX51_PAD_NANDF_D0__USBH3_DATA7 IOMUX_PAD(0x578, 0x190, 5, 0x0a18, 0, 0) | ||
| 392 | #define _MX51_PAD_CSI1_D8__CSI1_D8 IOMUX_PAD(0x57c, 0x194, 0, 0x0000, 0, 0) | ||
| 393 | #define _MX51_PAD_CSI1_D8__GPIO3_12 IOMUX_PAD(0x57c, 0x194, 3, 0x0998, 1, 0) | ||
| 394 | #define _MX51_PAD_CSI1_D9__CSI1_D9 IOMUX_PAD(0x580, 0x198, 0, 0x0000, 0, 0) | ||
| 395 | #define _MX51_PAD_CSI1_D9__GPIO3_13 IOMUX_PAD(0x580, 0x198, 3, 0x0000, 0, 0) | ||
| 396 | #define _MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19c, 0, 0x0000, 0, 0) | ||
| 397 | #define _MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1a0, 0, 0x0000, 0, 0) | ||
| 398 | #define _MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58c, 0x1a4, 0, 0x0000, 0, 0) | ||
| 399 | #define _MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1a8, 0, 0x0000, 0, 0) | ||
| 400 | #define _MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1ac, 0, 0x0000, 0, 0) | ||
| 401 | #define _MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1b0, 0, 0x0000, 0, 0) | ||
| 402 | #define _MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59c, 0x1b4, 0, 0x0000, 0, 0) | ||
| 403 | #define _MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5a0, 0x1b8, 0, 0x0000, 0, 0) | ||
| 404 | #define _MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5a4, 0x1bc, 0, 0x0000, 0, 0) | ||
| 405 | #define _MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5a8, 0x1c0, 0, 0x0000, 0, 0) | ||
| 406 | #define _MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5ac, 0x1c4, 0, 0x0000, 0, 0) | ||
| 407 | #define _MX51_PAD_CSI1_VSYNC__GPIO3_14 IOMUX_PAD(0x5ac, 0x1c4, 3, 0x0000, 0, 0) | ||
| 408 | #define _MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5b0, 0x1c8, 0, 0x0000, 0, 0) | ||
| 409 | #define _MX51_PAD_CSI1_HSYNC__GPIO3_15 IOMUX_PAD(0x5b0, 0x1c8, 3, 0x0000, 0, 0) | ||
| 410 | #define _MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5b4, 0x000, 0, 0x0000, 0, 0) | ||
| 411 | #define _MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5b8, 0x000, 0, 0x0000, 0, 0) | ||
| 412 | #define _MX51_PAD_CSI2_D12__CSI2_D12 IOMUX_PAD(0x5bc, 0x1cc, 0, 0x0000, 0, 0) | ||
| 413 | #define _MX51_PAD_CSI2_D12__GPIO4_9 IOMUX_PAD(0x5bc, 0x1cc, 3, 0x0000, 0, 0) | ||
| 414 | #define _MX51_PAD_CSI2_D13__CSI2_D13 IOMUX_PAD(0x5c0, 0x1d0, 0, 0x0000, 0, 0) | ||
| 415 | #define _MX51_PAD_CSI2_D13__GPIO4_10 IOMUX_PAD(0x5c0, 0x1d0, 3, 0x0000, 0, 0) | ||
| 416 | #define _MX51_PAD_CSI2_D14__CSI2_D14 IOMUX_PAD(0x5c4, 0x1d4, 0, 0x0000, 0, 0) | ||
| 417 | #define _MX51_PAD_CSI2_D15__CSI2_D15 IOMUX_PAD(0x5c8, 0x1d8, 0, 0x0000, 0, 0) | ||
| 418 | #define _MX51_PAD_CSI2_D16__CSI2_D16 IOMUX_PAD(0x5cc, 0x1dc, 0, 0x0000, 0, 0) | ||
| 419 | #define _MX51_PAD_CSI2_D17__CSI2_D17 IOMUX_PAD(0x5d0, 0x1e0, 0, 0x0000, 0, 0) | ||
| 420 | #define _MX51_PAD_CSI2_D18__CSI2_D18 IOMUX_PAD(0x5d4, 0x1e4, 0, 0x0000, 0, 0) | ||
| 421 | #define _MX51_PAD_CSI2_D18__GPIO4_11 IOMUX_PAD(0x5d4, 0x1e4, 3, 0x0000, 0, 0) | ||
| 422 | #define _MX51_PAD_CSI2_D19__CSI2_D19 IOMUX_PAD(0x5d8, 0x1e8, 0, 0x0000, 0, 0) | ||
| 423 | #define _MX51_PAD_CSI2_D19__GPIO4_12 IOMUX_PAD(0x5d8, 0x1e8, 3, 0x0000, 0, 0) | ||
| 424 | #define _MX51_PAD_CSI2_VSYNC__CSI2_VSYNC IOMUX_PAD(0x5dc, 0x1ec, 0, 0x0000, 0, 0) | ||
| 425 | #define _MX51_PAD_CSI2_VSYNC__GPIO4_13 IOMUX_PAD(0x5dc, 0x1ec, 3, 0x0000, 0, 0) | ||
| 426 | #define _MX51_PAD_CSI2_HSYNC__CSI2_HSYNC IOMUX_PAD(0x5e0, 0x1f0, 0, 0x0000, 0, 0) | ||
| 427 | #define _MX51_PAD_CSI2_HSYNC__GPIO4_14 IOMUX_PAD(0x5e0, 0x1f0, 3, 0x0000, 0, 0) | ||
| 428 | #define _MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK IOMUX_PAD(0x5e4, 0x1f4, 0, 0x0000, 0, 0) | ||
| 429 | #define _MX51_PAD_CSI2_PIXCLK__GPIO4_15 IOMUX_PAD(0x5e4, 0x1f4, 3, 0x0000, 0, 0) | ||
| 430 | #define _MX51_PAD_I2C1_CLK__GPIO4_16 IOMUX_PAD(0x5e8, 0x1f8, 3, 0x0000, 0, 0) | ||
| 431 | #define _MX51_PAD_I2C1_CLK__I2C1_CLK IOMUX_PAD(0x5e8, 0x1f8, 0x10, 0x0000, 0, 0) | ||
| 432 | #define _MX51_PAD_I2C1_DAT__GPIO4_17 IOMUX_PAD(0x5ec, 0x1fc, 3, 0x0000, 0, 0) | ||
| 433 | #define _MX51_PAD_I2C1_DAT__I2C1_DAT IOMUX_PAD(0x5ec, 0x1fc, 0x10, 0x0000, 0, 0) | ||
| 434 | #define _MX51_PAD_AUD3_BB_TXD__AUD3_TXD IOMUX_PAD(0x5f0, 0x200, 0, 0x0000, 0, 0) | ||
| 435 | #define _MX51_PAD_AUD3_BB_TXD__GPIO4_18 IOMUX_PAD(0x5f0, 0x200, 3, 0x0000, 0, 0) | ||
| 436 | #define _MX51_PAD_AUD3_BB_RXD__AUD3_RXD IOMUX_PAD(0x5f4, 0x204, 0, 0x0000, 0, 0) | ||
| 437 | #define _MX51_PAD_AUD3_BB_RXD__GPIO4_19 IOMUX_PAD(0x5f4, 0x204, 3, 0x0000, 0, 0) | ||
| 438 | #define _MX51_PAD_AUD3_BB_RXD__UART3_RXD IOMUX_PAD(0x5f4, 0x204, 1, 0x09f4, 2, 0) | ||
| 439 | #define _MX51_PAD_AUD3_BB_CK__AUD3_TXC IOMUX_PAD(0x5f8, 0x208, 0, 0x0000, 0, 0) | ||
| 440 | #define _MX51_PAD_AUD3_BB_CK__GPIO4_20 IOMUX_PAD(0x5f8, 0x208, 3, 0x0000, 0, 0) | ||
| 441 | #define _MX51_PAD_AUD3_BB_FS__AUD3_TXFS IOMUX_PAD(0x5fc, 0x20c, 0, 0x0000, 0, 0) | ||
| 442 | #define _MX51_PAD_AUD3_BB_FS__GPIO4_21 IOMUX_PAD(0x5fc, 0x20c, 3, 0x0000, 0, 0) | ||
| 443 | #define _MX51_PAD_AUD3_BB_FS__UART3_TXD IOMUX_PAD(0x5fc, 0x20c, 1, 0x0000, 0, 0) | ||
| 444 | #define _MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x600, 0x210, 0, 0x0000, 0, 0) | ||
| 445 | #define _MX51_PAD_CSPI1_MOSI__GPIO4_22 IOMUX_PAD(0x600, 0x210, 3, 0x0000, 0, 0) | ||
| 446 | #define _MX51_PAD_CSPI1_MOSI__I2C1_SDA IOMUX_PAD(0x600, 0x210, 0x11, 0x09b4, 1, 0) | ||
| 447 | #define _MX51_PAD_CSPI1_MISO__AUD4_RXD IOMUX_PAD(0x604, 0x214, 1, 0x08c4, 1, 0) | ||
| 448 | #define _MX51_PAD_CSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x604, 0x214, 0, 0x0000, 0, 0) | ||
| 449 | #define _MX51_PAD_CSPI1_MISO__GPIO4_23 IOMUX_PAD(0x604, 0x214, 3, 0x0000, 0, 0) | ||
| 450 | #define _MX51_PAD_CSPI1_SS0__AUD4_TXC IOMUX_PAD(0x608, 0x218, 1, 0x08cc, 1, 0) | ||
| 451 | #define _MX51_PAD_CSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, 0x0000, 0, 0) | ||
| 452 | #define _MX51_PAD_CSPI1_SS0__GPIO4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0000, 0, 0) | ||
| 453 | #define _MX51_PAD_CSPI1_SS1__AUD4_TXD IOMUX_PAD(0x60c, 0x21c, 1, 0x08c8, 1, 0) | ||
| 454 | #define _MX51_PAD_CSPI1_SS1__ECSPI1_SS1 IOMUX_PAD(0x60c, 0x21c, 0, 0x0000, 0, 0) | ||
| 455 | #define _MX51_PAD_CSPI1_SS1__GPIO4_25 IOMUX_PAD(0x60c, 0x21c, 3, 0x0000, 0, 0) | ||
| 456 | #define _MX51_PAD_CSPI1_RDY__AUD4_TXFS IOMUX_PAD(0x610, 0x220, 1, 0x08d0, 1, 0) | ||
| 457 | #define _MX51_PAD_CSPI1_RDY__ECSPI1_RDY IOMUX_PAD(0x610, 0x220, 0, 0x0000, 0, 0) | ||
| 458 | #define _MX51_PAD_CSPI1_RDY__GPIO4_26 IOMUX_PAD(0x610, 0x220, 3, 0x0000, 0, 0) | ||
| 459 | #define _MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x614, 0x224, 0, 0x0000, 0, 0) | ||
| 460 | #define _MX51_PAD_CSPI1_SCLK__GPIO4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0000, 0, 0) | ||
| 461 | #define _MX51_PAD_CSPI1_SCLK__I2C1_SCL IOMUX_PAD(0x614, 0x224, 0x11, 0x09b0, 1, 0) | ||
| 462 | #define _MX51_PAD_UART1_RXD__GPIO4_28 IOMUX_PAD(0x618, 0x228, 3, 0x0000, 0, 0) | ||
| 463 | #define _MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x09e4, 0, 0) | ||
| 464 | #define _MX51_PAD_UART1_TXD__GPIO4_29 IOMUX_PAD(0x61c, 0x22c, 3, 0x0000, 0, 0) | ||
| 465 | #define _MX51_PAD_UART1_TXD__PWM2_PWMO IOMUX_PAD(0x61c, 0x22c, 1, 0x0000, 0, 0) | ||
| 466 | #define _MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61c, 0x22c, 0, 0x0000, 0, 0) | ||
| 467 | #define _MX51_PAD_UART1_RTS__GPIO4_30 IOMUX_PAD(0x620, 0x230, 3, 0x0000, 0, 0) | ||
| 468 | #define _MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, 0, 0x09e0, 0, 0) | ||
| 469 | #define _MX51_PAD_UART1_CTS__GPIO4_31 IOMUX_PAD(0x624, 0x234, 3, 0x0000, 0, 0) | ||
| 470 | #define _MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, 0, 0x0000, 0, 0) | ||
| 471 | #define _MX51_PAD_UART2_RXD__FIRI_TXD IOMUX_PAD(0x628, 0x238, 1, 0x0000, 0, 0) | ||
| 472 | #define _MX51_PAD_UART2_RXD__GPIO1_20 IOMUX_PAD(0x628, 0x238, 3, 0x0000, 0, 0) | ||
| 473 | #define _MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x09ec, 2, 0) | ||
| 474 | #define _MX51_PAD_UART2_TXD__FIRI_RXD IOMUX_PAD(0x62c, 0x23c, 1, 0x0000, 0, 0) | ||
| 475 | #define _MX51_PAD_UART2_TXD__GPIO1_21 IOMUX_PAD(0x62c, 0x23c, 3, 0x0000, 0, 0) | ||
| 476 | #define _MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62c, 0x23c, 0, 0x09ec, 3, 0) | ||
| 477 | #define _MX51_PAD_UART3_RXD__CSI1_D0 IOMUX_PAD(0x630, 0x240, 2, 0x0000, 0, 0) | ||
| 478 | #define _MX51_PAD_UART3_RXD__GPIO1_22 IOMUX_PAD(0x630, 0x240, 3, 0x0000, 0, 0) | ||
| 479 | #define _MX51_PAD_UART3_RXD__UART1_DTR IOMUX_PAD(0x630, 0x240, 0, 0x0000, 0, 0) | ||
| 480 | #define _MX51_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x630, 0x240, 1, 0x09f4, 4, 0) | ||
| 481 | #define _MX51_PAD_UART3_TXD__CSI1_D1 IOMUX_PAD(0x634, 0x244, 2, 0x0000, 0, 0) | ||
| 482 | #define _MX51_PAD_UART3_TXD__GPIO1_23 IOMUX_PAD(0x634, 0x244, 3, 0x0000, 0, 0) | ||
| 483 | #define _MX51_PAD_UART3_TXD__UART1_DSR IOMUX_PAD(0x634, 0x244, 0, 0x0000, 0, 0) | ||
| 484 | #define _MX51_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x634, 0x244, 1, 0x0000, 0, 0) | ||
| 485 | #define _MX51_PAD_OWIRE_LINE__GPIO1_24 IOMUX_PAD(0x638, 0x248, 3, 0x0000, 0, 0) | ||
| 486 | #define _MX51_PAD_OWIRE_LINE__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 0, 0x0000, 0, 0) | ||
| 487 | #define _MX51_PAD_OWIRE_LINE__SPDIF_OUT IOMUX_PAD(0x638, 0x248, 6, 0x0000, 0, 0) | ||
| 488 | #define _MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63c, 0x24c, 0, 0x0000, 0, 0) | ||
| 489 | #define _MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0000, 0, 0) | ||
| 490 | #define _MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0000, 0, 0) | ||
| 491 | #define _MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0000, 0, 0) | ||
| 492 | #define _MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64c, 0x25c, 0, 0x0000, 0, 0) | ||
| 493 | #define _MX51_PAD_KEY_COL0__PLL1_BYP IOMUX_PAD(0x64c, 0x25c, 7, 0x090c, 0, 0) | ||
| 494 | #define _MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0000, 0, 0) | ||
| 495 | #define _MX51_PAD_KEY_COL1__PLL2_BYP IOMUX_PAD(0x650, 0x260, 7, 0x0910, 0, 0) | ||
| 496 | #define _MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0000, 0, 0) | ||
| 497 | #define _MX51_PAD_KEY_COL2__PLL3_BYP IOMUX_PAD(0x654, 0x264, 7, 0x0000, 0, 0) | ||
| 498 | #define _MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0000, 0, 0) | ||
| 499 | #define _MX51_PAD_KEY_COL4__I2C2_SCL IOMUX_PAD(0x65c, 0x26c, 0x13, 0x09b8, 1, 0) | ||
| 500 | #define _MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65c, 0x26c, 0, 0x0000, 0, 0) | ||
| 501 | #define _MX51_PAD_KEY_COL4__SPDIF_OUT1 IOMUX_PAD(0x65c, 0x26c, 6, 0x0000, 0, 0) | ||
| 502 | #define _MX51_PAD_KEY_COL4__UART1_RI IOMUX_PAD(0x65c, 0x26c, 1, 0x0000, 0, 0) | ||
| 503 | #define _MX51_PAD_KEY_COL4__UART3_RTS IOMUX_PAD(0x65c, 0x26c, 2, 0x09f0, 4, 0) | ||
| 504 | #define _MX51_PAD_KEY_COL5__I2C2_SDA IOMUX_PAD(0x660, 0x270, 0x13, 0x09bc, 1, 0) | ||
| 505 | #define _MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0000, 0, 0) | ||
| 506 | #define _MX51_PAD_KEY_COL5__UART1_DCD IOMUX_PAD(0x660, 0x270, 1, 0x0000, 0, 0) | ||
| 507 | #define _MX51_PAD_KEY_COL5__UART3_CTS IOMUX_PAD(0x660, 0x270, 2, 0x0000, 0, 0) | ||
| 508 | #define _MX51_PAD_USBH1_CLK__CSPI_SCLK IOMUX_PAD(0x678, 0x278, 1, 0x0914, 1, 0) | ||
| 509 | #define _MX51_PAD_USBH1_CLK__GPIO1_25 IOMUX_PAD(0x678, 0x278, 2, 0x0000, 0, 0) | ||
| 510 | #define _MX51_PAD_USBH1_CLK__I2C2_SCL IOMUX_PAD(0x678, 0x278, 0x15, 0x09b8, 2, 0) | ||
| 511 | #define _MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, 0, 0x0000, 0, 0) | ||
| 512 | #define _MX51_PAD_USBH1_DIR__CSPI_MOSI IOMUX_PAD(0x67c, 0x27c, 1, 0x091c, 1, 0) | ||
| 513 | #define _MX51_PAD_USBH1_DIR__GPIO1_26 IOMUX_PAD(0x67c, 0x27c, 2, 0x0000, 0, 0) | ||
| 514 | #define _MX51_PAD_USBH1_DIR__I2C2_SDA IOMUX_PAD(0x67c, 0x27c, 0x15, 0x09bc, 2, 0) | ||
| 515 | #define _MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67c, 0x27c, 0, 0x0000, 0, 0) | ||
| 516 | #define _MX51_PAD_USBH1_STP__CSPI_RDY IOMUX_PAD(0x680, 0x280, 1, 0x0000, 0, 0) | ||
| 517 | #define _MX51_PAD_USBH1_STP__GPIO1_27 IOMUX_PAD(0x680, 0x280, 2, 0x0000, 0, 0) | ||
| 518 | #define _MX51_PAD_USBH1_STP__UART3_RXD IOMUX_PAD(0x680, 0x280, 5, 0x09f4, 6, 0) | ||
| 519 | #define _MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, 0, 0x0000, 0, 0) | ||
| 520 | #define _MX51_PAD_USBH1_NXT__CSPI_MISO IOMUX_PAD(0x684, 0x284, 1, 0x0918, 0, 0) | ||
| 521 | #define _MX51_PAD_USBH1_NXT__GPIO1_28 IOMUX_PAD(0x684, 0x284, 2, 0x0000, 0, 0) | ||
| 522 | #define _MX51_PAD_USBH1_NXT__UART3_TXD IOMUX_PAD(0x684, 0x284, 5, 0x0000, 0, 0) | ||
| 523 | #define _MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, 0, 0x0000, 0, 0) | ||
| 524 | #define _MX51_PAD_USBH1_DATA0__GPIO1_11 IOMUX_PAD(0x688, 0x288, 2, 0x0000, 0, 0) | ||
| 525 | #define _MX51_PAD_USBH1_DATA0__UART2_CTS IOMUX_PAD(0x688, 0x288, 1, 0x0000, 0, 0) | ||
| 526 | #define _MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 0, 0x0000, 0, 0) | ||
| 527 | #define _MX51_PAD_USBH1_DATA1__GPIO1_12 IOMUX_PAD(0x68c, 0x28c, 2, 0x0000, 0, 0) | ||
| 528 | #define _MX51_PAD_USBH1_DATA1__UART2_RXD IOMUX_PAD(0x68c, 0x28c, 1, 0x09ec, 4, 0) | ||
| 529 | #define _MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68c, 0x28c, 0, 0x0000, 0, 0) | ||
| 530 | #define _MX51_PAD_USBH1_DATA2__GPIO1_13 IOMUX_PAD(0x690, 0x290, 2, 0x0000, 0, 0) | ||
| 531 | #define _MX51_PAD_USBH1_DATA2__UART2_TXD IOMUX_PAD(0x690, 0x290, 1, 0x09ec, 5, 0) | ||
| 532 | #define _MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, 0x0000, 0, 0) | ||
| 533 | #define _MX51_PAD_USBH1_DATA3__GPIO1_14 IOMUX_PAD(0x694, 0x294, 2, 0x0000, 0, 0) | ||
| 534 | #define _MX51_PAD_USBH1_DATA3__UART2_RTS IOMUX_PAD(0x694, 0x294, 1, 0x09e8, 5, 0) | ||
| 535 | #define _MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 0, 0x0000, 0, 0) | ||
| 536 | #define _MX51_PAD_USBH1_DATA4__CSPI_SS0 IOMUX_PAD(0x698, 0x298, 1, 0x0000, 0, 0) | ||
| 537 | #define _MX51_PAD_USBH1_DATA4__GPIO1_15 IOMUX_PAD(0x698, 0x298, 2, 0x0000, 0, 0) | ||
| 538 | #define _MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 0, 0x0000, 0, 0) | ||
| 539 | #define _MX51_PAD_USBH1_DATA5__CSPI_SS1 IOMUX_PAD(0x69c, 0x29c, 1, 0x0920, 0, 0) | ||
| 540 | #define _MX51_PAD_USBH1_DATA5__GPIO1_16 IOMUX_PAD(0x69c, 0x29c, 2, 0x0000, 0, 0) | ||
| 541 | #define _MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69c, 0x29c, 0, 0x0000, 0, 0) | ||
| 542 | #define _MX51_PAD_USBH1_DATA6__CSPI_SS3 IOMUX_PAD(0x6a0, 0x2a0, 1, 0x0928, 1, 0) | ||
| 543 | #define _MX51_PAD_USBH1_DATA6__GPIO1_17 IOMUX_PAD(0x6a0, 0x2a0, 2, 0x0000, 0, 0) | ||
| 544 | #define _MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6a0, 0x2a0, 0, 0x0000, 0, 0) | ||
| 545 | #define _MX51_PAD_USBH1_DATA7__ECSPI1_SS3 IOMUX_PAD(0x6a4, 0x2a4, 1, 0x0000, 0, 0) | ||
| 546 | #define _MX51_PAD_USBH1_DATA7__ECSPI2_SS3 IOMUX_PAD(0x6a4, 0x2a4, 5, 0x0934, 1, 0) | ||
| 547 | #define _MX51_PAD_USBH1_DATA7__GPIO1_18 IOMUX_PAD(0x6a4, 0x2a4, 2, 0x0000, 0, 0) | ||
| 548 | #define _MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6a4, 0x2a4, 0, 0x0000, 0, 0) | ||
| 549 | #define _MX51_PAD_DI1_PIN11__DI1_PIN11 IOMUX_PAD(0x6a8, 0x2a8, 0, 0x0000, 0, 0) | ||
| 550 | #define _MX51_PAD_DI1_PIN11__ECSPI1_SS2 IOMUX_PAD(0x6a8, 0x2a8, 7, 0x0000, 0, 0) | ||
| 551 | #define _MX51_PAD_DI1_PIN11__GPIO3_0 IOMUX_PAD(0x6a8, 0x2a8, 4, 0x0000, 0, 0) | ||
| 552 | #define _MX51_PAD_DI1_PIN12__DI1_PIN12 IOMUX_PAD(0x6ac, 0x2ac, 0, 0x0000, 0, 0) | ||
| 553 | #define _MX51_PAD_DI1_PIN12__GPIO3_1 IOMUX_PAD(0x6ac, 0x2ac, 4, 0x0978, 1, 0) | ||
| 554 | #define _MX51_PAD_DI1_PIN13__DI1_PIN13 IOMUX_PAD(0x6b0, 0x2b0, 0, 0x0000, 0, 0) | ||
| 555 | #define _MX51_PAD_DI1_PIN13__GPIO3_2 IOMUX_PAD(0x6b0, 0x2b0, 4, 0x097c, 1, 0) | ||
| 556 | #define _MX51_PAD_DI1_D0_CS__DI1_D0_CS IOMUX_PAD(0x6b4, 0x2b4, 0, 0x0000, 0, 0) | ||
| 557 | #define _MX51_PAD_DI1_D0_CS__GPIO3_3 IOMUX_PAD(0x6b4, 0x2b4, 4, 0x0980, 1, 0) | ||
| 558 | #define _MX51_PAD_DI1_D1_CS__DI1_D1_CS IOMUX_PAD(0x6b8, 0x2b8, 0, 0x0000, 0, 0) | ||
| 559 | #define _MX51_PAD_DI1_D1_CS__DISP1_PIN14 IOMUX_PAD(0x6b8, 0x2b8, 2, 0x0000, 0, 0) | ||
| 560 | #define _MX51_PAD_DI1_D1_CS__DISP1_PIN5 IOMUX_PAD(0x6b8, 0x2b8, 3, 0x0000, 0, 0) | ||
| 561 | #define _MX51_PAD_DI1_D1_CS__GPIO3_4 IOMUX_PAD(0x6b8, 0x2b8, 4, 0x0984, 1, 0) | ||
| 562 | #define _MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 IOMUX_PAD(0x6bc, 0x2bc, 2, 0x09a4, 1, 0) | ||
| 563 | #define _MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN IOMUX_PAD(0x6bc, 0x2bc, 0, 0x09c4, 0, 0) | ||
| 564 | #define _MX51_PAD_DISPB2_SER_DIN__GPIO3_5 IOMUX_PAD(0x6bc, 0x2bc, 4, 0x0988, 1, 0) | ||
| 565 | #define _MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 IOMUX_PAD(0x6c0, 0x2c0, 3, 0x0000, 0, 0) | ||
| 566 | #define _MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO IOMUX_PAD(0x6c0, 0x2c0, 0, 0x09c4, 1, 0) | ||
| 567 | #define _MX51_PAD_DISPB2_SER_DIO__GPIO3_6 IOMUX_PAD(0x6c0, 0x2c0, 4, 0x098c, 1, 0) | ||
| 568 | #define _MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 IOMUX_PAD(0x6c4, 0x2c4, 2, 0x0000, 0, 0) | ||
| 569 | #define _MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 IOMUX_PAD(0x6c4, 0x2c4, 3, 0x0000, 0, 0) | ||
| 570 | #define _MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK IOMUX_PAD(0x6c4, 0x2c4, 0, 0x0000, 0, 0) | ||
| 571 | #define _MX51_PAD_DISPB2_SER_CLK__GPIO3_7 IOMUX_PAD(0x6c4, 0x2c4, 4, 0x0990, 1, 0) | ||
| 572 | #define _MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK IOMUX_PAD(0x6c8, 0x2c8, 2, 0x0000, 0, 0) | ||
| 573 | #define _MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 IOMUX_PAD(0x6c8, 0x2c8, 2, 0x0000, 0, 0) | ||
| 574 | #define _MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 IOMUX_PAD(0x6c8, 0x2c8, 3, 0x0000, 0, 0) | ||
| 575 | #define _MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, 0x0000, 0, 0) | ||
| 576 | #define _MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, 0x0000, 0, 0) | ||
| 577 | #define _MX51_PAD_DISPB2_SER_RS__GPIO3_8 IOMUX_PAD(0x6c8, 0x2c8, 4, 0x0994, 1, 0) | ||
| 578 | #define _MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6cc, 0x2cc, 0, 0x0000, 0, 0) | ||
| 579 | #define _MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6d0, 0x2d0, 0, 0x0000, 0, 0) | ||
| 580 | #define _MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6d4, 0x2d4, 0, 0x0000, 0, 0) | ||
| 581 | #define _MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6d8, 0x2d8, 0, 0x0000, 0, 0) | ||
| 582 | #define _MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6dc, 0x2dc, 0, 0x0000, 0, 0) | ||
| 583 | #define _MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6e0, 0x2e0, 0, 0x0000, 0, 0) | ||
| 584 | #define _MX51_PAD_DISP1_DAT6__BOOT_USB_SRC IOMUX_PAD(0x6e4, 0x2e4, 7, 0x0000, 0, 0) | ||
| 585 | #define _MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6e4, 0x2e4, 0, 0x0000, 0, 0) | ||
| 586 | #define _MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG IOMUX_PAD(0x6e8, 0x2e8, 7, 0x0000, 0, 0) | ||
| 587 | #define _MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6e8, 0x2e8, 0, 0x0000, 0, 0) | ||
| 588 | #define _MX51_PAD_DISP1_DAT8__BOOT_SRC0 IOMUX_PAD(0x6ec, 0x2ec, 7, 0x0000, 0, 0) | ||
| 589 | #define _MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6ec, 0x2ec, 0, 0x0000, 0, 0) | ||
| 590 | #define _MX51_PAD_DISP1_DAT9__BOOT_SRC1 IOMUX_PAD(0x6f0, 0x2f0, 7, 0x0000, 0, 0) | ||
| 591 | #define _MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6f0, 0x2f0, 0, 0x0000, 0, 0) | ||
| 592 | #define _MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE IOMUX_PAD(0x6f4, 0x2f4, 7, 0x0000, 0, 0) | ||
| 593 | #define _MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6f4, 0x2f4, 0, 0x0000, 0, 0) | ||
| 594 | #define _MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 IOMUX_PAD(0x6f8, 0x2f8, 7, 0x0000, 0, 0) | ||
| 595 | #define _MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6f8, 0x2f8, 0, 0x0000, 0, 0) | ||
| 596 | #define _MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL IOMUX_PAD(0x6fc, 0x2fc, 7, 0x0000, 0, 0) | ||
| 597 | #define _MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6fc, 0x2fc, 0, 0x0000, 0, 0) | ||
| 598 | #define _MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 IOMUX_PAD(0x700, 0x300, 7, 0x0000, 0, 0) | ||
| 599 | #define _MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, 0x0000, 0, 0) | ||
| 600 | #define _MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 IOMUX_PAD(0x704, 0x304, 7, 0x0000, 0, 0) | ||
| 601 | #define _MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, 0x0000, 0, 0) | ||
| 602 | #define _MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH IOMUX_PAD(0x708, 0x308, 7, 0x0000, 0, 0) | ||
| 603 | #define _MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, 0x0000, 0, 0) | ||
| 604 | #define _MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 IOMUX_PAD(0x70c, 0x30c, 7, 0x0000, 0, 0) | ||
| 605 | #define _MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70c, 0x30c, 0, 0x0000, 0, 0) | ||
| 606 | #define _MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 IOMUX_PAD(0x710, 0x310, 7, 0x0000, 0, 0) | ||
| 607 | #define _MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, 0x0000, 0, 0) | ||
| 608 | #define _MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 IOMUX_PAD(0x714, 0x314, 7, 0x0000, 0, 0) | ||
| 609 | #define _MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, 0x0000, 0, 0) | ||
| 610 | #define _MX51_PAD_DISP1_DAT18__DISP2_PIN11 IOMUX_PAD(0x714, 0x314, 5, 0x0000, 0, 0) | ||
| 611 | #define _MX51_PAD_DISP1_DAT18__DISP2_PIN5 IOMUX_PAD(0x714, 0x314, 4, 0x0000, 0, 0) | ||
| 612 | #define _MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 IOMUX_PAD(0x718, 0x318, 7, 0x0000, 0, 0) | ||
| 613 | #define _MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0000, 0, 0) | ||
| 614 | #define _MX51_PAD_DISP1_DAT19__DISP2_PIN12 IOMUX_PAD(0x718, 0x318, 5, 0x0000, 0, 0) | ||
| 615 | #define _MX51_PAD_DISP1_DAT19__DISP2_PIN6 IOMUX_PAD(0x718, 0x318, 4, 0x0000, 0, 0) | ||
| 616 | #define _MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 IOMUX_PAD(0x71c, 0x31c, 7, 0x0000, 0, 0) | ||
| 617 | #define _MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71c, 0x31c, 0, 0x0000, 0, 0) | ||
| 618 | #define _MX51_PAD_DISP1_DAT20__DISP2_PIN13 IOMUX_PAD(0x71c, 0x31c, 5, 0x0000, 0, 0) | ||
| 619 | #define _MX51_PAD_DISP1_DAT20__DISP2_PIN7 IOMUX_PAD(0x71c, 0x31c, 4, 0x0000, 0, 0) | ||
| 620 | #define _MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 IOMUX_PAD(0x720, 0x320, 7, 0x0000, 0, 0) | ||
| 621 | #define _MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0000, 0, 0) | ||
| 622 | #define _MX51_PAD_DISP1_DAT21__DISP2_PIN14 IOMUX_PAD(0x720, 0x320, 5, 0x0000, 0, 0) | ||
| 623 | #define _MX51_PAD_DISP1_DAT21__DISP2_PIN8 IOMUX_PAD(0x720, 0x320, 4, 0x0000, 0, 0) | ||
| 624 | #define _MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 IOMUX_PAD(0x724, 0x324, 7, 0x0000, 0, 0) | ||
| 625 | #define _MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0000, 0, 0) | ||
| 626 | #define _MX51_PAD_DISP1_DAT22__DISP2_D0_CS IOMUX_PAD(0x724, 0x324, 6, 0x0000, 0, 0) | ||
| 627 | #define _MX51_PAD_DISP1_DAT22__DISP2_DAT16 IOMUX_PAD(0x724, 0x324, 5, 0x0000, 0, 0) | ||
| 628 | #define _MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 IOMUX_PAD(0x728, 0x328, 7, 0x0000, 0, 0) | ||
| 629 | #define _MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0000, 0, 0) | ||
| 630 | #define _MX51_PAD_DISP1_DAT23__DISP2_D1_CS IOMUX_PAD(0x728, 0x328, 6, 0x0000, 0, 0) | ||
| 631 | #define _MX51_PAD_DISP1_DAT23__DISP2_DAT17 IOMUX_PAD(0x728, 0x328, 5, 0x0000, 0, 0) | ||
| 632 | #define _MX51_PAD_DISP1_DAT23__DISP2_SER_CS IOMUX_PAD(0x728, 0x328, 4, 0x0000, 0, 0) | ||
| 633 | #define _MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72c, 0x32c, 0, 0x0000, 0, 0) | ||
| 634 | #define _MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0000, 0, 0) | ||
| 635 | #define _MX51_PAD_DI_GP2__DISP1_SER_CLK IOMUX_PAD(0x740, 0x338, 0, 0x0000, 0, 0) | ||
| 636 | #define _MX51_PAD_DI_GP2__DISP2_WAIT IOMUX_PAD(0x740, 0x338, 2, 0x09a8, 1, 0) | ||
| 637 | #define _MX51_PAD_DI_GP3__CSI1_DATA_EN IOMUX_PAD(0x744, 0x33c, 3, 0x09a0, 1, 0) | ||
| 638 | #define _MX51_PAD_DI_GP3__DISP1_SER_DIO IOMUX_PAD(0x744, 0x33c, 0, 0x09c0, 0, 0) | ||
| 639 | #define _MX51_PAD_DI_GP3__FEC_TX_ER IOMUX_PAD(0x744, 0x33c, 2, 0x0000, 0, 0) | ||
| 640 | #define _MX51_PAD_DI2_PIN4__CSI2_DATA_EN IOMUX_PAD(0x748, 0x340, 3, 0x099c, 1, 0) | ||
| 641 | #define _MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0000, 0, 0) | ||
| 642 | #define _MX51_PAD_DI2_PIN4__FEC_CRS IOMUX_PAD(0x748, 0x340, 2, 0x0950, 1, 0) | ||
| 643 | #define _MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74c, 0x344, 0, 0x0000, 0, 0) | ||
| 644 | #define _MX51_PAD_DI2_PIN2__FEC_MDC IOMUX_PAD(0x74c, 0x344, 2, 0x0000, 0, 0) | ||
| 645 | #define _MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0000, 0, 0) | ||
| 646 | #define _MX51_PAD_DI2_PIN3__FEC_MDIO IOMUX_PAD(0x750, 0x348, 2, 0x0954, 1, 0) | ||
| 647 | #define _MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34c, 0, 0x0000, 0, 0) | ||
| 648 | #define _MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 IOMUX_PAD(0x754, 0x34c, 2, 0x095c, 1, 0) | ||
| 649 | #define _MX51_PAD_DI_GP4__DI2_PIN15 IOMUX_PAD(0x758, 0x350, 4, 0x0000, 0, 0) | ||
| 650 | #define _MX51_PAD_DI_GP4__DISP1_SER_DIN IOMUX_PAD(0x758, 0x350, 0, 0x09c0, 1, 0) | ||
| 651 | #define _MX51_PAD_DI_GP4__DISP2_PIN1 IOMUX_PAD(0x758, 0x350, 3, 0x0000, 0, 0) | ||
| 652 | #define _MX51_PAD_DI_GP4__FEC_RDATA2 IOMUX_PAD(0x758, 0x350, 2, 0x0960, 1, 0) | ||
| 653 | #define _MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75c, 0x354, 0, 0x0000, 0, 0) | ||
| 654 | #define _MX51_PAD_DISP2_DAT0__FEC_RDATA3 IOMUX_PAD(0x75c, 0x354, 2, 0x0964, 1, 0) | ||
| 655 | #define _MX51_PAD_DISP2_DAT0__KEY_COL6 IOMUX_PAD(0x75c, 0x354, 4, 0x09c8, 1, 0) | ||
| 656 | #define _MX51_PAD_DISP2_DAT0__UART3_RXD IOMUX_PAD(0x75c, 0x354, 5, 0x09f4, 8, 0) | ||
| 657 | #define _MX51_PAD_DISP2_DAT0__USBH3_CLK IOMUX_PAD(0x75c, 0x354, 3, 0x09f8, 1, 0) | ||
| 658 | #define _MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0000, 0, 0) | ||
| 659 | #define _MX51_PAD_DISP2_DAT1__FEC_RX_ER IOMUX_PAD(0x760, 0x358, 2, 0x0970, 1, 0) | ||
| 660 | #define _MX51_PAD_DISP2_DAT1__KEY_COL7 IOMUX_PAD(0x760, 0x358, 4, 0x09cc, 1, 0) | ||
| 661 | #define _MX51_PAD_DISP2_DAT1__UART3_TXD IOMUX_PAD(0x760, 0x358, 5, 0x0000, 0, 0) | ||
| 662 | #define _MX51_PAD_DISP2_DAT1__USBH3_DIR IOMUX_PAD(0x760, 0x358, 3, 0x0a1c, 1, 0) | ||
| 663 | #define _MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35c, 0, 0x0000, 0, 0) | ||
| 664 | #define _MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0000, 0, 0) | ||
| 665 | #define _MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76c, 0x364, 0, 0x0000, 0, 0) | ||
| 666 | #define _MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0000, 0, 0) | ||
| 667 | #define _MX51_PAD_DISP2_DAT6__DISP2_DAT6 IOMUX_PAD(0x774, 0x36c, 0, 0x0000, 0, 0) | ||
| 668 | #define _MX51_PAD_DISP2_DAT6__FEC_TDATA1 IOMUX_PAD(0x774, 0x36c, 2, 0x0000, 0, 0) | ||
| 669 | #define _MX51_PAD_DISP2_DAT6__GPIO1_19 IOMUX_PAD(0x774, 0x36c, 5, 0x0000, 0, 0) | ||
| 670 | #define _MX51_PAD_DISP2_DAT6__KEY_ROW4 IOMUX_PAD(0x774, 0x36c, 4, 0x09d0, 1, 0) | ||
| 671 | #define _MX51_PAD_DISP2_DAT6__USBH3_STP IOMUX_PAD(0x774, 0x36c, 3, 0x0a24, 1, 0) | ||
| 672 | #define _MX51_PAD_DISP2_DAT7__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 0, 0x0000, 0, 0) | ||
| 673 | #define _MX51_PAD_DISP2_DAT7__FEC_TDATA2 IOMUX_PAD(0x778, 0x370, 2, 0x0000, 0, 0) | ||
| 674 | #define _MX51_PAD_DISP2_DAT7__GPIO1_29 IOMUX_PAD(0x778, 0x370, 5, 0x0000, 0, 0) | ||
| 675 | #define _MX51_PAD_DISP2_DAT7__KEY_ROW5 IOMUX_PAD(0x778, 0x370, 4, 0x09d4, 1, 0) | ||
| 676 | #define _MX51_PAD_DISP2_DAT7__USBH3_NXT IOMUX_PAD(0x778, 0x370, 3, 0x0a20, 1, 0) | ||
| 677 | #define _MX51_PAD_DISP2_DAT8__DISP2_DAT8 IOMUX_PAD(0x77c, 0x374, 0, 0x0000, 0, 0) | ||
| 678 | #define _MX51_PAD_DISP2_DAT8__FEC_TDATA3 IOMUX_PAD(0x77c, 0x374, 2, 0x0000, 0, 0) | ||
| 679 | #define _MX51_PAD_DISP2_DAT8__GPIO1_30 IOMUX_PAD(0x77c, 0x374, 5, 0x0000, 0, 0) | ||
| 680 | #define _MX51_PAD_DISP2_DAT8__KEY_ROW6 IOMUX_PAD(0x77c, 0x374, 4, 0x09d8, 1, 0) | ||
| 681 | #define _MX51_PAD_DISP2_DAT8__USBH3_DATA0 IOMUX_PAD(0x77c, 0x374, 3, 0x09fc, 1, 0) | ||
| 682 | #define _MX51_PAD_DISP2_DAT9__AUD6_RXC IOMUX_PAD(0x780, 0x378, 4, 0x08f4, 1, 0) | ||
| 683 | #define _MX51_PAD_DISP2_DAT9__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 0, 0x0000, 0, 0) | ||
| 684 | #define _MX51_PAD_DISP2_DAT9__FEC_TX_EN IOMUX_PAD(0x780, 0x378, 2, 0x0000, 0, 0) | ||
| 685 | #define _MX51_PAD_DISP2_DAT9__GPIO1_31 IOMUX_PAD(0x780, 0x378, 5, 0x0000, 0, 0) | ||
| 686 | #define _MX51_PAD_DISP2_DAT9__USBH3_DATA1 IOMUX_PAD(0x780, 0x378, 3, 0x0a00, 1, 0) | ||
| 687 | #define _MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37c, 0, 0x0000, 0, 0) | ||
| 688 | #define _MX51_PAD_DISP2_DAT10__DISP2_SER_CS IOMUX_PAD(0x784, 0x37c, 5, 0x0000, 0, 0) | ||
| 689 | #define _MX51_PAD_DISP2_DAT10__FEC_COL IOMUX_PAD(0x784, 0x37c, 2, 0x094c, 1, 0) | ||
| 690 | #define _MX51_PAD_DISP2_DAT10__KEY_ROW7 IOMUX_PAD(0x784, 0x37c, 4, 0x09dc, 1, 0) | ||
| 691 | #define _MX51_PAD_DISP2_DAT10__USBH3_DATA2 IOMUX_PAD(0x784, 0x37c, 3, 0x0a04, 1, 0) | ||
| 692 | #define _MX51_PAD_DISP2_DAT11__AUD6_TXD IOMUX_PAD(0x788, 0x380, 4, 0x08f0, 1, 0) | ||
| 693 | #define _MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0000, 0, 0) | ||
| 694 | #define _MX51_PAD_DISP2_DAT11__FEC_RX_CLK IOMUX_PAD(0x788, 0x380, 2, 0x0968, 1, 0) | ||
| 695 | #define _MX51_PAD_DISP2_DAT11__GPIO1_10 IOMUX_PAD(0x788, 0x380, 7, 0x0000, 0, 0) | ||
| 696 | #define _MX51_PAD_DISP2_DAT11__USBH3_DATA3 IOMUX_PAD(0x788, 0x380, 3, 0x0a08, 1, 0) | ||
| 697 | #define _MX51_PAD_DISP2_DAT12__AUD6_RXD IOMUX_PAD(0x78c, 0x384, 4, 0x08ec, 1, 0) | ||
| 698 | #define _MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78c, 0x384, 0, 0x0000, 0, 0) | ||
| 699 | #define _MX51_PAD_DISP2_DAT12__FEC_RX_DV IOMUX_PAD(0x78c, 0x384, 2, 0x096c, 1, 0) | ||
| 700 | #define _MX51_PAD_DISP2_DAT12__USBH3_DATA4 IOMUX_PAD(0x78c, 0x384, 3, 0x0a0c, 1, 0) | ||
| 701 | #define _MX51_PAD_DISP2_DAT13__AUD6_TXC IOMUX_PAD(0x790, 0x388, 4, 0x08fc, 1, 0) | ||
| 702 | #define _MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0000, 0, 0) | ||
| 703 | #define _MX51_PAD_DISP2_DAT13__FEC_TX_CLK IOMUX_PAD(0x790, 0x388, 2, 0x0974, 1, 0) | ||
| 704 | #define _MX51_PAD_DISP2_DAT13__USBH3_DATA5 IOMUX_PAD(0x790, 0x388, 3, 0x0a10, 1, 0) | ||
| 705 | #define _MX51_PAD_DISP2_DAT14__AUD6_TXFS IOMUX_PAD(0x794, 0x38c, 4, 0x0900, 1, 0) | ||
| 706 | #define _MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38c, 0, 0x0000, 0, 0) | ||
| 707 | #define _MX51_PAD_DISP2_DAT14__FEC_RDATA0 IOMUX_PAD(0x794, 0x38c, 2, 0x0958, 1, 0) | ||
| 708 | #define _MX51_PAD_DISP2_DAT14__USBH3_DATA6 IOMUX_PAD(0x794, 0x38c, 3, 0x0a14, 1, 0) | ||
| 709 | #define _MX51_PAD_DISP2_DAT15__AUD6_RXFS IOMUX_PAD(0x798, 0x390, 4, 0x08f8, 1, 0) | ||
| 710 | #define _MX51_PAD_DISP2_DAT15__DISP1_SER_CS IOMUX_PAD(0x798, 0x390, 5, 0x0000, 0, 0) | ||
| 711 | #define _MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0000, 0, 0) | ||
| 712 | #define _MX51_PAD_DISP2_DAT15__FEC_TDATA0 IOMUX_PAD(0x798, 0x390, 2, 0x0000, 0, 0) | ||
| 713 | #define _MX51_PAD_DISP2_DAT15__USBH3_DATA7 IOMUX_PAD(0x798, 0x390, 3, 0x0a18, 1, 0) | ||
| 714 | #define _MX51_PAD_SD1_CMD__AUD5_RXFS IOMUX_PAD(0x79c, 0x394, 1, 0x08e0, 1, 0) | ||
| 715 | #define _MX51_PAD_SD1_CMD__CSPI_MOSI IOMUX_PAD(0x79c, 0x394, 2, 0x091c, 2, 0) | ||
| 716 | #define _MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79c, 0x394, 0x10, 0x0000, 0, 0) | ||
| 717 | #define _MX51_PAD_SD1_CLK__AUD5_RXC IOMUX_PAD(0x7a0, 0x398, 1, 0x08dc, 1, 0) | ||
| 718 | #define _MX51_PAD_SD1_CLK__CSPI_SCLK IOMUX_PAD(0x7a0, 0x398, 2, 0x0914, 2, 0) | ||
| 719 | #define _MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7a0, 0x398, 0x10, 0x0000, 0, 0) | ||
| 720 | #define _MX51_PAD_SD1_DATA0__AUD5_TXD IOMUX_PAD(0x7a4, 0x39c, 1, 0x08d8, 2, 0) | ||
| 721 | #define _MX51_PAD_SD1_DATA0__CSPI_MISO IOMUX_PAD(0x7a4, 0x39c, 2, 0x0918, 1, 0) | ||
| 722 | #define _MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7a4, 0x39c, 0x10, 0x0000, 0, 0) | ||
| 723 | #define _MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x000, 0x01c, 0, 0x0000, 0, 0) | ||
| 724 | #define _MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x000, 0x020, 0, 0x0000, 0, 0) | ||
| 725 | #define _MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x000, 0x024, 0, 0x0000, 0, 0) | ||
| 726 | #define _MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x000, 0x028, 0, 0x0000, 0, 0) | ||
| 727 | #define _MX51_PAD_SD1_DATA1__AUD5_RXD IOMUX_PAD(0x7a8, 0x3a0, 1, 0x08d4, 2, 0) | ||
| 728 | #define _MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7a8, 0x3a0, 0x10, 0x0000, 0, 0) | ||
| 729 | #define _MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x000, 0x02c, 0, 0x0000, 0, 0) | ||
| 730 | #define _MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x000, 0x030, 0, 0x0000, 0, 0) | ||
| 731 | #define _MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x000, 0x034, 0, 0x0000, 0, 0) | ||
| 732 | #define _MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x000, 0x038, 0, 0x0000, 0, 0) | ||
| 733 | #define _MX51_PAD_SD1_DATA2__AUD5_TXC IOMUX_PAD(0x7ac, 0x3a4, 1, 0x08e4, 2, 0) | ||
| 734 | #define _MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7ac, 0x3a4, 0x10, 0x0000, 0, 0) | ||
| 735 | #define _MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x000, 0x044, 0, 0x0000, 0, 0) | ||
| 736 | #define _MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x000, 0x048, 0, 0x0000, 0, 0) | ||
| 737 | #define _MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x000, 0x03c, 0, 0x0000, 0, 0) | ||
| 738 | #define _MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x000, 0x040, 0, 0x0000, 0, 0) | ||
| 739 | #define _MX51_PAD_SD1_DATA3__AUD5_TXFS IOMUX_PAD(0x7b0, 0x3a8, 1, 0x08e8, 2, 0) | ||
| 740 | #define _MX51_PAD_SD1_DATA3__CSPI_SS1 IOMUX_PAD(0x7b0, 0x3a8, 2, 0x0920, 1, 0) | ||
| 741 | #define _MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7b0, 0x3a8, 0x10, 0x0000, 0, 0) | ||
| 742 | #define _MX51_PAD_GPIO1_0__CSPI_SS2 IOMUX_PAD(0x7b4, 0x3ac, 2, 0x0924, 0, 0) | ||
| 743 | #define _MX51_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x7b4, 0x3ac, 1, 0x0000, 0, 0) | ||
| 744 | #define _MX51_PAD_GPIO1_0__SD1_CD IOMUX_PAD(0x7b4, 0x3ac, 0, 0x0000, 0, 0) | ||
| 745 | #define _MX51_PAD_GPIO1_1__CSPI_MISO IOMUX_PAD(0x7b8, 0x3b0, 2, 0x0918, 2, 0) | ||
| 746 | #define _MX51_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x7b8, 0x3b0, 1, 0x0000, 0, 0) | ||
| 747 | #define _MX51_PAD_GPIO1_1__SD1_WP IOMUX_PAD(0x7b8, 0x3b0, 0, 0x0000, 0, 0) | ||
| 748 | #define _MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x000, 0x04c, 0, 0x0000, 0, 0) | ||
| 749 | #define _MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x000, 0x050, 0, 0x0000, 0, 0) | ||
| 750 | #define _MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x000, 0x054, 0, 0x0000, 0, 0) | ||
| 751 | #define _MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x000, 0x058, 0, 0x0000, 0, 0) | ||
| 752 | #define _MX51_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(0x000, 0x3b4, 2, 0x091c, 3, 0) | ||
| 753 | #define _MX51_PAD_SD2_CMD__I2C1_SCL IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x09b0, 2, 0) | ||
| 754 | #define _MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7bc, 0x3b4, 0x10, 0x0000, 0, 0) | ||
| 755 | #define _MX51_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x7c0, 0x3b8, 2, 0x0914, 3, 0) | ||
| 756 | #define _MX51_PAD_SD2_CLK__I2C1_SDA IOMUX_PAD(0x7c0, 0x3b8, 0x11, 0x09b4, 2, 0) | ||
| 757 | #define _MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7c0, 0x3b8, 0x10, 0x0000, 0, 0) | ||
| 758 | #define _MX51_PAD_SD2_DATA0__CSPI_MISO IOMUX_PAD(0x7c4, 0x3bc, 2, 0x0918, 3, 0) | ||
| 759 | #define _MX51_PAD_SD2_DATA0__SD1_DAT4 IOMUX_PAD(0x7c4, 0x3bc, 1, 0x0000, 0, 0) | ||
| 760 | #define _MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7c4, 0x3bc, 0x10, 0x0000, 0, 0) | ||
| 761 | #define _MX51_PAD_SD2_DATA1__SD1_DAT5 IOMUX_PAD(0x7c8, 0x3c0, 1, 0x0000, 0, 0) | ||
| 762 | #define _MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7c8, 0x3c0, 0x10, 0x0000, 0, 0) | ||
| 763 | #define _MX51_PAD_SD2_DATA1__USBH3_H2_DP IOMUX_PAD(0x7c8, 0x3c0, 2, 0x0000, 0, 0) | ||
| 764 | #define _MX51_PAD_SD2_DATA2__SD1_DAT6 IOMUX_PAD(0x7cc, 0x3c4, 1, 0x0000, 0, 0) | ||
| 765 | #define _MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7cc, 0x3c4, 0x10, 0x0000, 0, 0) | ||
| 766 | #define _MX51_PAD_SD2_DATA2__USBH3_H2_DM IOMUX_PAD(0x7cc, 0x3c4, 2, 0x0000, 0, 0) | ||
| 767 | #define _MX51_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x7d0, 0x3c8, 2, 0x0924, 1, 0) | ||
| 768 | #define _MX51_PAD_SD2_DATA3__SD1_DAT7 IOMUX_PAD(0x7d0, 0x3c8, 1, 0x0000, 0, 0) | ||
| 769 | #define _MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7d0, 0x3c8, 0x10, 0x0000, 0, 0) | ||
| 770 | #define _MX51_PAD_GPIO1_2__CCM_OUT_2 IOMUX_PAD(0x7d4, 0x3cc, 5, 0x0000, 0, 0) | ||
| 771 | #define _MX51_PAD_GPIO1_2__GPIO1_2 IOMUX_PAD(0x7d4, 0x3cc, 0, 0x0000, 0, 0) | ||
| 772 | #define _MX51_PAD_GPIO1_2__I2C2_SCL IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x09b8, 3, 0) | ||
| 773 | #define _MX51_PAD_GPIO1_2__PLL1_BYP IOMUX_PAD(0x7d4, 0x3cc, 7, 0x090c, 1, 0) | ||
| 774 | #define _MX51_PAD_GPIO1_2__PWM1_PWMO IOMUX_PAD(0x7d4, 0x3cc, 1, 0x0000, 0, 0) | ||
| 775 | #define _MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, 0x0000, 0, 0) | ||
| 776 | #define _MX51_PAD_GPIO1_3__I2C2_SDA IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x09bc, 3, 0) | ||
| 777 | #define _MX51_PAD_GPIO1_3__PLL2_BYP IOMUX_PAD(0x7d8, 0x3d0, 7, 0x0910, 1, 0) | ||
| 778 | #define _MX51_PAD_GPIO1_3__PWM2_PWMO IOMUX_PAD(0x7d8, 0x3d0, 1, 0x0000, 0, 0) | ||
| 779 | #define _MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7fc, 0x3d4, 0, 0x0000, 0, 0) | ||
| 780 | #define _MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B IOMUX_PAD(0x7fc, 0x3d4, 1, 0x0000, 0, 0) | ||
| 781 | #define _MX51_PAD_GPIO1_4__DISP2_EXT_CLK IOMUX_PAD(0x804, 0x3d8, 4, 0x0908, 1, 0) | ||
| 782 | #define _MX51_PAD_GPIO1_4__EIM_RDY IOMUX_PAD(0x804, 0x3d8, 3, 0x0938, 1, 0) | ||
| 783 | #define _MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, 0x0000, 0, 0) | ||
| 784 | #define _MX51_PAD_GPIO1_4__WDOG1_WDOG_B IOMUX_PAD(0x804, 0x3d8, 2, 0x0000, 0, 0) | ||
| 785 | #define _MX51_PAD_GPIO1_5__CSI2_MCLK IOMUX_PAD(0x808, 0x3dc, 6, 0x0000, 0, 0) | ||
| 786 | #define _MX51_PAD_GPIO1_5__DISP2_PIN16 IOMUX_PAD(0x808, 0x3dc, 3, 0x0000, 0, 0) | ||
| 787 | #define _MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, 0x0000, 0, 0) | ||
| 788 | #define _MX51_PAD_GPIO1_5__WDOG2_WDOG_B IOMUX_PAD(0x808, 0x3dc, 2, 0x0000, 0, 0) | ||
| 789 | #define _MX51_PAD_GPIO1_6__DISP2_PIN17 IOMUX_PAD(0x80c, 0x3e0, 4, 0x0000, 0, 0) | ||
| 790 | #define _MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, 0x0000, 0, 0) | ||
| 791 | #define _MX51_PAD_GPIO1_6__REF_EN_B IOMUX_PAD(0x80c, 0x3e0, 3, 0x0000, 0, 0) | ||
| 792 | #define _MX51_PAD_GPIO1_7__CCM_OUT_0 IOMUX_PAD(0x810, 0x3e4, 3, 0x0000, 0, 0) | ||
| 793 | #define _MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, 0x0000, 0, 0) | ||
| 794 | #define _MX51_PAD_GPIO1_7__SD2_WP IOMUX_PAD(0x810, 0x3e4, 6, 0x0000, 0, 0) | ||
| 795 | #define _MX51_PAD_GPIO1_7__SPDIF_OUT1 IOMUX_PAD(0x810, 0x3e4, 2, 0x0000, 0, 0) | ||
| 796 | #define _MX51_PAD_GPIO1_8__CSI2_DATA_EN IOMUX_PAD(0x814, 0x3e8, 2, 0x099c, 2, 0) | ||
| 797 | #define _MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, 0x0000, 0, 0) | ||
| 798 | #define _MX51_PAD_GPIO1_8__SD2_CD IOMUX_PAD(0x814, 0x3e8, 6, 0x0000, 0, 0) | ||
| 799 | #define _MX51_PAD_GPIO1_8__USBH3_PWR IOMUX_PAD(0x814, 0x3e8, 1, 0x0000, 0, 0) | ||
| 800 | #define _MX51_PAD_GPIO1_9__CCM_OUT_1 IOMUX_PAD(0x818, 0x3ec, 3, 0x0000, 0, 0) | ||
| 801 | #define _MX51_PAD_GPIO1_9__DISP2_D1_CS IOMUX_PAD(0x818, 0x3ec, 2, 0x0000, 0, 0) | ||
| 802 | #define _MX51_PAD_GPIO1_9__DISP2_SER_CS IOMUX_PAD(0x818, 0x3ec, 7, 0x0000, 0, 0) | ||
| 803 | #define _MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, 0x0000, 0, 0) | ||
| 804 | #define _MX51_PAD_GPIO1_9__SD2_LCTL IOMUX_PAD(0x818, 0x3ec, 6, 0x0000, 0, 0) | ||
| 805 | #define _MX51_PAD_GPIO1_9__USBH3_OC IOMUX_PAD(0x818, 0x3ec, 1, 0x0000, 0, 0) | ||
| 806 | |||
| 807 | /* The same pins as above but with the default pad control values applied */ | ||
| 808 | #define MX51_PAD_EIM_D16__AUD4_RXFS (_MX51_PAD_EIM_D16__AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 809 | #define MX51_PAD_EIM_D16__AUD5_TXD (_MX51_PAD_EIM_D16__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 810 | #define MX51_PAD_EIM_D16__EIM_D16 (_MX51_PAD_EIM_D16__EIM_D16 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 811 | #define MX51_PAD_EIM_D16__GPIO2_0 (_MX51_PAD_EIM_D16__GPIO2_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 812 | #define MX51_PAD_EIM_D16__I2C1_SDA (_MX51_PAD_EIM_D16__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | ||
| 813 | #define MX51_PAD_EIM_D16__UART2_CTS (_MX51_PAD_EIM_D16__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 814 | #define MX51_PAD_EIM_D16__USBH2_DATA0 (_MX51_PAD_EIM_D16__USBH2_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 815 | #define MX51_PAD_EIM_D17__AUD5_RXD (_MX51_PAD_EIM_D17__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 816 | #define MX51_PAD_EIM_D17__EIM_D17 (_MX51_PAD_EIM_D17__EIM_D17 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 817 | #define MX51_PAD_EIM_D17__GPIO2_1 (_MX51_PAD_EIM_D17__GPIO2_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 818 | #define MX51_PAD_EIM_D17__UART2_RXD (_MX51_PAD_EIM_D17__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 819 | #define MX51_PAD_EIM_D17__UART3_CTS (_MX51_PAD_EIM_D17__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 820 | #define MX51_PAD_EIM_D17__USBH2_DATA1 (_MX51_PAD_EIM_D17__USBH2_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 821 | #define MX51_PAD_EIM_D18__AUD5_TXC (_MX51_PAD_EIM_D18__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 822 | #define MX51_PAD_EIM_D18__EIM_D18 (_MX51_PAD_EIM_D18__EIM_D18 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 823 | #define MX51_PAD_EIM_D18__GPIO2_2 (_MX51_PAD_EIM_D18__GPIO2_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 824 | #define MX51_PAD_EIM_D18__UART2_TXD (_MX51_PAD_EIM_D18__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 825 | #define MX51_PAD_EIM_D18__UART3_RTS (_MX51_PAD_EIM_D18__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 826 | #define MX51_PAD_EIM_D18__USBH2_DATA2 (_MX51_PAD_EIM_D18__USBH2_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 827 | #define MX51_PAD_EIM_D19__AUD4_RXC (_MX51_PAD_EIM_D19__AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 828 | #define MX51_PAD_EIM_D19__AUD5_TXFS (_MX51_PAD_EIM_D19__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 829 | #define MX51_PAD_EIM_D19__EIM_D19 (_MX51_PAD_EIM_D19__EIM_D19 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 830 | #define MX51_PAD_EIM_D19__GPIO2_3 (_MX51_PAD_EIM_D19__GPIO2_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 831 | #define MX51_PAD_EIM_D19__I2C1_SCL (_MX51_PAD_EIM_D19__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | ||
| 832 | #define MX51_PAD_EIM_D19__UART2_RTS (_MX51_PAD_EIM_D19__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 833 | #define MX51_PAD_EIM_D19__USBH2_DATA3 (_MX51_PAD_EIM_D19__USBH2_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 834 | #define MX51_PAD_EIM_D20__AUD4_TXD (_MX51_PAD_EIM_D20__AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 835 | #define MX51_PAD_EIM_D20__EIM_D20 (_MX51_PAD_EIM_D20__EIM_D20 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 836 | #define MX51_PAD_EIM_D20__GPIO2_4 (_MX51_PAD_EIM_D20__GPIO2_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 837 | #define MX51_PAD_EIM_D20__SRTC_ALARM_DEB (_MX51_PAD_EIM_D20__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 838 | #define MX51_PAD_EIM_D20__USBH2_DATA4 (_MX51_PAD_EIM_D20__USBH2_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 839 | #define MX51_PAD_EIM_D21__AUD4_RXD (_MX51_PAD_EIM_D21__AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 840 | #define MX51_PAD_EIM_D21__EIM_D21 (_MX51_PAD_EIM_D21__EIM_D21 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 841 | #define MX51_PAD_EIM_D21__GPIO2_5 (_MX51_PAD_EIM_D21__GPIO2_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 842 | #define MX51_PAD_EIM_D21__SRTC_ALARM_DEB (_MX51_PAD_EIM_D21__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 843 | #define MX51_PAD_EIM_D21__USBH2_DATA5 (_MX51_PAD_EIM_D21__USBH2_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 844 | #define MX51_PAD_EIM_D22__AUD4_TXC (_MX51_PAD_EIM_D22__AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 845 | #define MX51_PAD_EIM_D22__EIM_D22 (_MX51_PAD_EIM_D22__EIM_D22 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 846 | #define MX51_PAD_EIM_D22__GPIO2_6 (_MX51_PAD_EIM_D22__GPIO2_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 847 | #define MX51_PAD_EIM_D22__USBH2_DATA6 (_MX51_PAD_EIM_D22__USBH2_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 848 | #define MX51_PAD_EIM_D23__AUD4_TXFS (_MX51_PAD_EIM_D23__AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 849 | #define MX51_PAD_EIM_D23__EIM_D23 (_MX51_PAD_EIM_D23__EIM_D23 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 850 | #define MX51_PAD_EIM_D23__GPIO2_7 (_MX51_PAD_EIM_D23__GPIO2_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 851 | #define MX51_PAD_EIM_D23__SPDIF_OUT1 (_MX51_PAD_EIM_D23__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 852 | #define MX51_PAD_EIM_D23__USBH2_DATA7 (_MX51_PAD_EIM_D23__USBH2_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 853 | #define MX51_PAD_EIM_D24__AUD6_RXFS (_MX51_PAD_EIM_D24__AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 854 | #define MX51_PAD_EIM_D24__EIM_D24 (_MX51_PAD_EIM_D24__EIM_D24 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 855 | #define MX51_PAD_EIM_D24__GPIO2_8 (_MX51_PAD_EIM_D24__GPIO2_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 856 | #define MX51_PAD_EIM_D24__I2C2_SDA (_MX51_PAD_EIM_D24__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | ||
| 857 | #define MX51_PAD_EIM_D24__UART3_CTS (_MX51_PAD_EIM_D24__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 858 | #define MX51_PAD_EIM_D24__USBOTG_DATA0 (_MX51_PAD_EIM_D24__USBOTG_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 859 | #define MX51_PAD_EIM_D25__EIM_D25 (_MX51_PAD_EIM_D25__EIM_D25 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 860 | #define MX51_PAD_EIM_D25__KEY_COL6 (_MX51_PAD_EIM_D25__KEY_COL6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 861 | #define MX51_PAD_EIM_D25__UART2_CTS (_MX51_PAD_EIM_D25__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 862 | #define MX51_PAD_EIM_D25__UART3_RXD (_MX51_PAD_EIM_D25__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 863 | #define MX51_PAD_EIM_D25__USBOTG_DATA1 (_MX51_PAD_EIM_D25__USBOTG_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 864 | #define MX51_PAD_EIM_D26__EIM_D26 (_MX51_PAD_EIM_D26__EIM_D26 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 865 | #define MX51_PAD_EIM_D26__KEY_COL7 (_MX51_PAD_EIM_D26__KEY_COL7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 866 | #define MX51_PAD_EIM_D26__UART2_RTS (_MX51_PAD_EIM_D26__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 867 | #define MX51_PAD_EIM_D26__UART3_TXD (_MX51_PAD_EIM_D26__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 868 | #define MX51_PAD_EIM_D26__USBOTG_DATA2 (_MX51_PAD_EIM_D26__USBOTG_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 869 | #define MX51_PAD_EIM_D27__AUD6_RXC (_MX51_PAD_EIM_D27__AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 870 | #define MX51_PAD_EIM_D27__EIM_D27 (_MX51_PAD_EIM_D27__EIM_D27 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 871 | #define MX51_PAD_EIM_D27__GPIO2_9 (_MX51_PAD_EIM_D27__GPIO2_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 872 | #define MX51_PAD_EIM_D27__I2C2_SCL (_MX51_PAD_EIM_D27__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | ||
| 873 | #define MX51_PAD_EIM_D27__UART3_RTS (_MX51_PAD_EIM_D27__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 874 | #define MX51_PAD_EIM_D27__USBOTG_DATA3 (_MX51_PAD_EIM_D27__USBOTG_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 875 | #define MX51_PAD_EIM_D28__AUD6_TXD (_MX51_PAD_EIM_D28__AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 876 | #define MX51_PAD_EIM_D28__EIM_D28 (_MX51_PAD_EIM_D28__EIM_D28 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 877 | #define MX51_PAD_EIM_D28__KEY_ROW4 (_MX51_PAD_EIM_D28__KEY_ROW4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 878 | #define MX51_PAD_EIM_D28__USBOTG_DATA4 (_MX51_PAD_EIM_D28__USBOTG_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 879 | #define MX51_PAD_EIM_D29__AUD6_RXD (_MX51_PAD_EIM_D29__AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 880 | #define MX51_PAD_EIM_D29__EIM_D29 (_MX51_PAD_EIM_D29__EIM_D29 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 881 | #define MX51_PAD_EIM_D29__KEY_ROW5 (_MX51_PAD_EIM_D29__KEY_ROW5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 882 | #define MX51_PAD_EIM_D29__USBOTG_DATA5 (_MX51_PAD_EIM_D29__USBOTG_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 883 | #define MX51_PAD_EIM_D30__AUD6_TXC (_MX51_PAD_EIM_D30__AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 884 | #define MX51_PAD_EIM_D30__EIM_D30 (_MX51_PAD_EIM_D30__EIM_D30 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 885 | #define MX51_PAD_EIM_D30__KEY_ROW6 (_MX51_PAD_EIM_D30__KEY_ROW6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 886 | #define MX51_PAD_EIM_D30__USBOTG_DATA6 (_MX51_PAD_EIM_D30__USBOTG_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 887 | #define MX51_PAD_EIM_D31__AUD6_TXFS (_MX51_PAD_EIM_D31__AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 888 | #define MX51_PAD_EIM_D31__EIM_D31 (_MX51_PAD_EIM_D31__EIM_D31 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 889 | #define MX51_PAD_EIM_D31__KEY_ROW7 (_MX51_PAD_EIM_D31__KEY_ROW7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 890 | #define MX51_PAD_EIM_D31__USBOTG_DATA7 (_MX51_PAD_EIM_D31__USBOTG_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 891 | #define MX51_PAD_EIM_A16__EIM_A16 (_MX51_PAD_EIM_A16__EIM_A16 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 892 | #define MX51_PAD_EIM_A16__GPIO2_10 (_MX51_PAD_EIM_A16__GPIO2_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 893 | #define MX51_PAD_EIM_A16__OSC_FREQ_SEL0 (_MX51_PAD_EIM_A16__OSC_FREQ_SEL0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 894 | #define MX51_PAD_EIM_A17__EIM_A17 (_MX51_PAD_EIM_A17__EIM_A17 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 895 | #define MX51_PAD_EIM_A17__GPIO2_11 (_MX51_PAD_EIM_A17__GPIO2_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 896 | #define MX51_PAD_EIM_A17__OSC_FREQ_SEL1 (_MX51_PAD_EIM_A17__OSC_FREQ_SEL1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 897 | #define MX51_PAD_EIM_A18__BOOT_LPB0 (_MX51_PAD_EIM_A18__BOOT_LPB0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 898 | #define MX51_PAD_EIM_A18__EIM_A18 (_MX51_PAD_EIM_A18__EIM_A18 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 899 | #define MX51_PAD_EIM_A18__GPIO2_12 (_MX51_PAD_EIM_A18__GPIO2_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 900 | #define MX51_PAD_EIM_A19__BOOT_LPB1 (_MX51_PAD_EIM_A19__BOOT_LPB1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 901 | #define MX51_PAD_EIM_A19__EIM_A19 (_MX51_PAD_EIM_A19__EIM_A19 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 902 | #define MX51_PAD_EIM_A19__GPIO2_13 (_MX51_PAD_EIM_A19__GPIO2_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 903 | #define MX51_PAD_EIM_A20__BOOT_UART_SRC0 (_MX51_PAD_EIM_A20__BOOT_UART_SRC0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 904 | #define MX51_PAD_EIM_A20__EIM_A20 (_MX51_PAD_EIM_A20__EIM_A20 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 905 | #define MX51_PAD_EIM_A20__GPIO2_14 (_MX51_PAD_EIM_A20__GPIO2_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 906 | #define MX51_PAD_EIM_A21__BOOT_UART_SRC1 (_MX51_PAD_EIM_A21__BOOT_UART_SRC1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 907 | #define MX51_PAD_EIM_A21__EIM_A21 (_MX51_PAD_EIM_A21__EIM_A21 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 908 | #define MX51_PAD_EIM_A21__GPIO2_15 (_MX51_PAD_EIM_A21__GPIO2_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 909 | #define MX51_PAD_EIM_A22__EIM_A22 (_MX51_PAD_EIM_A22__EIM_A22 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 910 | #define MX51_PAD_EIM_A22__GPIO2_16 (_MX51_PAD_EIM_A22__GPIO2_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 911 | #define MX51_PAD_EIM_A23__BOOT_HPN_EN (_MX51_PAD_EIM_A23__BOOT_HPN_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 912 | #define MX51_PAD_EIM_A23__EIM_A23 (_MX51_PAD_EIM_A23__EIM_A23 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 913 | #define MX51_PAD_EIM_A23__GPIO2_17 (_MX51_PAD_EIM_A23__GPIO2_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 914 | #define MX51_PAD_EIM_A24__EIM_A24 (_MX51_PAD_EIM_A24__EIM_A24 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 915 | #define MX51_PAD_EIM_A24__GPIO2_18 (_MX51_PAD_EIM_A24__GPIO2_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 916 | #define MX51_PAD_EIM_A24__USBH2_CLK (_MX51_PAD_EIM_A24__USBH2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 917 | #define MX51_PAD_EIM_A25__DISP1_PIN4 (_MX51_PAD_EIM_A25__DISP1_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 918 | #define MX51_PAD_EIM_A25__EIM_A25 (_MX51_PAD_EIM_A25__EIM_A25 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 919 | #define MX51_PAD_EIM_A25__GPIO2_19 (_MX51_PAD_EIM_A25__GPIO2_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 920 | #define MX51_PAD_EIM_A25__USBH2_DIR (_MX51_PAD_EIM_A25__USBH2_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 921 | #define MX51_PAD_EIM_A26__CSI1_DATA_EN (_MX51_PAD_EIM_A26__CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 922 | #define MX51_PAD_EIM_A26__DISP2_EXT_CLK (_MX51_PAD_EIM_A26__DISP2_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 923 | #define MX51_PAD_EIM_A26__EIM_A26 (_MX51_PAD_EIM_A26__EIM_A26 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 924 | #define MX51_PAD_EIM_A26__GPIO2_20 (_MX51_PAD_EIM_A26__GPIO2_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 925 | #define MX51_PAD_EIM_A26__USBH2_STP (_MX51_PAD_EIM_A26__USBH2_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 926 | #define MX51_PAD_EIM_A27__CSI2_DATA_EN (_MX51_PAD_EIM_A27__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 927 | #define MX51_PAD_EIM_A27__DISP1_PIN1 (_MX51_PAD_EIM_A27__DISP1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 928 | #define MX51_PAD_EIM_A27__EIM_A27 (_MX51_PAD_EIM_A27__EIM_A27 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 929 | #define MX51_PAD_EIM_A27__GPIO2_21 (_MX51_PAD_EIM_A27__GPIO2_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 930 | #define MX51_PAD_EIM_A27__USBH2_NXT (_MX51_PAD_EIM_A27__USBH2_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 931 | #define MX51_PAD_EIM_EB0__EIM_EB0 (_MX51_PAD_EIM_EB0__EIM_EB0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 932 | #define MX51_PAD_EIM_EB1__EIM_EB1 (_MX51_PAD_EIM_EB1__EIM_EB1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 933 | #define MX51_PAD_EIM_EB2__AUD5_RXFS (_MX51_PAD_EIM_EB2__AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 934 | #define MX51_PAD_EIM_EB2__CSI1_D2 (_MX51_PAD_EIM_EB2__CSI1_D2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 935 | #define MX51_PAD_EIM_EB2__EIM_EB2 (_MX51_PAD_EIM_EB2__EIM_EB2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 936 | #define MX51_PAD_EIM_EB2__FEC_MDIO (_MX51_PAD_EIM_EB2__FEC_MDIO | \ | ||
| 937 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | PAD_CTL_PKE | PAD_CTL_SRE_FAST | \ | ||
| 938 | PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS)) | ||
| 939 | #define MX51_PAD_EIM_EB2__GPIO2_22 (_MX51_PAD_EIM_EB2__GPIO2_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 940 | #define MX51_PAD_EIM_EB2__GPT_CMPOUT1 (_MX51_PAD_EIM_EB2__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 941 | #define MX51_PAD_EIM_EB3__AUD5_RXC (_MX51_PAD_EIM_EB3__AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 942 | #define MX51_PAD_EIM_EB3__CSI1_D3 (_MX51_PAD_EIM_EB3__CSI1_D3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 943 | #define MX51_PAD_EIM_EB3__EIM_EB3 (_MX51_PAD_EIM_EB3__EIM_EB3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 944 | #define MX51_PAD_EIM_EB3__FEC_RDATA1 (_MX51_PAD_EIM_EB3__FEC_RDATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 945 | #define MX51_PAD_EIM_EB3__GPIO2_23 (_MX51_PAD_EIM_EB3__GPIO2_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 946 | #define MX51_PAD_EIM_EB3__GPT_CMPOUT2 (_MX51_PAD_EIM_EB3__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 947 | #define MX51_PAD_EIM_OE__EIM_OE (_MX51_PAD_EIM_OE__EIM_OE | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 948 | #define MX51_PAD_EIM_OE__GPIO2_24 (_MX51_PAD_EIM_OE__GPIO2_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 949 | #define MX51_PAD_EIM_CS0__EIM_CS0 (_MX51_PAD_EIM_CS0__EIM_CS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 950 | #define MX51_PAD_EIM_CS0__GPIO2_25 (_MX51_PAD_EIM_CS0__GPIO2_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 951 | #define MX51_PAD_EIM_CS1__EIM_CS1 (_MX51_PAD_EIM_CS1__EIM_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 952 | #define MX51_PAD_EIM_CS1__GPIO2_26 (_MX51_PAD_EIM_CS1__GPIO2_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 953 | #define MX51_PAD_EIM_CS2__AUD5_TXD (_MX51_PAD_EIM_CS2__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 954 | #define MX51_PAD_EIM_CS2__CSI1_D4 (_MX51_PAD_EIM_CS2__CSI1_D4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 955 | #define MX51_PAD_EIM_CS2__EIM_CS2 (_MX51_PAD_EIM_CS2__EIM_CS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 956 | #define MX51_PAD_EIM_CS2__FEC_RDATA2 (_MX51_PAD_EIM_CS2__FEC_RDATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 957 | #define MX51_PAD_EIM_CS2__GPIO2_27 (_MX51_PAD_EIM_CS2__GPIO2_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 958 | #define MX51_PAD_EIM_CS2__USBOTG_STP (_MX51_PAD_EIM_CS2__USBOTG_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 959 | #define MX51_PAD_EIM_CS3__AUD5_RXD (_MX51_PAD_EIM_CS3__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 960 | #define MX51_PAD_EIM_CS3__CSI1_D5 (_MX51_PAD_EIM_CS3__CSI1_D5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 961 | #define MX51_PAD_EIM_CS3__EIM_CS3 (_MX51_PAD_EIM_CS3__EIM_CS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 962 | #define MX51_PAD_EIM_CS3__FEC_RDATA3 (_MX51_PAD_EIM_CS3__FEC_RDATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 963 | #define MX51_PAD_EIM_CS3__GPIO2_28 (_MX51_PAD_EIM_CS3__GPIO2_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 964 | #define MX51_PAD_EIM_CS3__USBOTG_NXT (_MX51_PAD_EIM_CS3__USBOTG_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 965 | #define MX51_PAD_EIM_CS4__AUD5_TXC (_MX51_PAD_EIM_CS4__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 966 | #define MX51_PAD_EIM_CS4__CSI1_D6 (_MX51_PAD_EIM_CS4__CSI1_D6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 967 | #define MX51_PAD_EIM_CS4__EIM_CS4 (_MX51_PAD_EIM_CS4__EIM_CS4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 968 | #define MX51_PAD_EIM_CS4__FEC_RX_ER (_MX51_PAD_EIM_CS4__FEC_RX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_2)) | ||
| 969 | #define MX51_PAD_EIM_CS4__GPIO2_29 (_MX51_PAD_EIM_CS4__GPIO2_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 970 | #define MX51_PAD_EIM_CS4__USBOTG_CLK (_MX51_PAD_EIM_CS4__USBOTG_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 971 | #define MX51_PAD_EIM_CS5__AUD5_TXFS (_MX51_PAD_EIM_CS5__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 972 | #define MX51_PAD_EIM_CS5__CSI1_D7 (_MX51_PAD_EIM_CS5__CSI1_D7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 973 | #define MX51_PAD_EIM_CS5__DISP1_EXT_CLK (_MX51_PAD_EIM_CS5__DISP1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 974 | #define MX51_PAD_EIM_CS5__EIM_CS5 (_MX51_PAD_EIM_CS5__EIM_CS5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 975 | #define MX51_PAD_EIM_CS5__FEC_CRS (_MX51_PAD_EIM_CS5__FEC_CRS | MUX_PAD_CTRL(MX51_PAD_CTRL_2)) | ||
| 976 | #define MX51_PAD_EIM_CS5__GPIO2_30 (_MX51_PAD_EIM_CS5__GPIO2_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 977 | #define MX51_PAD_EIM_CS5__USBOTG_DIR (_MX51_PAD_EIM_CS5__USBOTG_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 978 | #define MX51_PAD_EIM_DTACK__EIM_DTACK (_MX51_PAD_EIM_DTACK__EIM_DTACK | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 979 | #define MX51_PAD_EIM_DTACK__GPIO2_31 (_MX51_PAD_EIM_DTACK__GPIO2_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 980 | #define MX51_PAD_EIM_LBA__EIM_LBA (_MX51_PAD_EIM_LBA__EIM_LBA | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 981 | #define MX51_PAD_EIM_LBA__GPIO3_1 (_MX51_PAD_EIM_LBA__GPIO3_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 982 | #define MX51_PAD_EIM_CRE__EIM_CRE (_MX51_PAD_EIM_CRE__EIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 983 | #define MX51_PAD_EIM_CRE__GPIO3_2 (_MX51_PAD_EIM_CRE__GPIO3_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 984 | #define MX51_PAD_DRAM_CS1__DRAM_CS1 (_MX51_PAD_DRAM_CS1__DRAM_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 985 | #define MX51_PAD_NANDF_WE_B__GPIO3_3 (_MX51_PAD_NANDF_WE_B__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 986 | #define MX51_PAD_NANDF_WE_B__NANDF_WE_B (_MX51_PAD_NANDF_WE_B__NANDF_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 987 | #define MX51_PAD_NANDF_WE_B__PATA_DIOW (_MX51_PAD_NANDF_WE_B__PATA_DIOW | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 988 | #define MX51_PAD_NANDF_WE_B__SD3_DATA0 (_MX51_PAD_NANDF_WE_B__SD3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 989 | #define MX51_PAD_NANDF_RE_B__GPIO3_4 (_MX51_PAD_NANDF_RE_B__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 990 | #define MX51_PAD_NANDF_RE_B__NANDF_RE_B (_MX51_PAD_NANDF_RE_B__NANDF_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 991 | #define MX51_PAD_NANDF_RE_B__PATA_DIOR (_MX51_PAD_NANDF_RE_B__PATA_DIOR | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 992 | #define MX51_PAD_NANDF_RE_B__SD3_DATA1 (_MX51_PAD_NANDF_RE_B__SD3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 993 | #define MX51_PAD_NANDF_ALE__GPIO3_5 (_MX51_PAD_NANDF_ALE__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 994 | #define MX51_PAD_NANDF_ALE__NANDF_ALE (_MX51_PAD_NANDF_ALE__NANDF_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 995 | #define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN (_MX51_PAD_NANDF_ALE__PATA_BUFFER_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 996 | #define MX51_PAD_NANDF_CLE__GPIO3_6 (_MX51_PAD_NANDF_CLE__GPIO3_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 997 | #define MX51_PAD_NANDF_CLE__NANDF_CLE (_MX51_PAD_NANDF_CLE__NANDF_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 998 | #define MX51_PAD_NANDF_CLE__PATA_RESET_B (_MX51_PAD_NANDF_CLE__PATA_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 999 | #define MX51_PAD_NANDF_WP_B__GPIO3_7 (_MX51_PAD_NANDF_WP_B__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1000 | #define MX51_PAD_NANDF_WP_B__NANDF_WP_B (_MX51_PAD_NANDF_WP_B__NANDF_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1001 | #define MX51_PAD_NANDF_WP_B__PATA_DMACK (_MX51_PAD_NANDF_WP_B__PATA_DMACK | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1002 | #define MX51_PAD_NANDF_WP_B__SD3_DATA2 (_MX51_PAD_NANDF_WP_B__SD3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1003 | #define MX51_PAD_NANDF_RB0__ECSPI2_SS1 (_MX51_PAD_NANDF_RB0__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1004 | #define MX51_PAD_NANDF_RB0__GPIO3_8 (_MX51_PAD_NANDF_RB0__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1005 | #define MX51_PAD_NANDF_RB0__NANDF_RB0 (_MX51_PAD_NANDF_RB0__NANDF_RB0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1006 | #define MX51_PAD_NANDF_RB0__PATA_DMARQ (_MX51_PAD_NANDF_RB0__PATA_DMARQ | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1007 | #define MX51_PAD_NANDF_RB0__SD3_DATA3 (_MX51_PAD_NANDF_RB0__SD3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1008 | #define MX51_PAD_NANDF_RB1__CSPI_MOSI (_MX51_PAD_NANDF_RB1__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1009 | #define MX51_PAD_NANDF_RB1__ECSPI2_RDY (_MX51_PAD_NANDF_RB1__ECSPI2_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1010 | #define MX51_PAD_NANDF_RB1__GPIO3_9 (_MX51_PAD_NANDF_RB1__GPIO3_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1011 | #define MX51_PAD_NANDF_RB1__NANDF_RB1 (_MX51_PAD_NANDF_RB1__NANDF_RB1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1012 | #define MX51_PAD_NANDF_RB1__PATA_IORDY (_MX51_PAD_NANDF_RB1__PATA_IORDY | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1013 | #define MX51_PAD_NANDF_RB1__SD4_CMD (_MX51_PAD_NANDF_RB1__SD4_CMD | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1014 | #define MX51_PAD_NANDF_RB2__DISP2_WAIT (_MX51_PAD_NANDF_RB2__DISP2_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1015 | #define MX51_PAD_NANDF_RB2__ECSPI2_SCLK (_MX51_PAD_NANDF_RB2__ECSPI2_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1016 | #define MX51_PAD_NANDF_RB2__FEC_COL (_MX51_PAD_NANDF_RB2__FEC_COL | MUX_PAD_CTRL(MX51_PAD_CTRL_2)) | ||
| 1017 | #define MX51_PAD_NANDF_RB2__GPIO3_10 (_MX51_PAD_NANDF_RB2__GPIO3_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1018 | #define MX51_PAD_NANDF_RB2__NANDF_RB2 (_MX51_PAD_NANDF_RB2__NANDF_RB2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1019 | #define MX51_PAD_NANDF_RB2__USBH3_H3_DP (_MX51_PAD_NANDF_RB2__USBH3_H3_DP | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1020 | #define MX51_PAD_NANDF_RB2__USBH3_NXT (_MX51_PAD_NANDF_RB2__USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1021 | #define MX51_PAD_NANDF_RB3__DISP1_WAIT (_MX51_PAD_NANDF_RB3__DISP1_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1022 | #define MX51_PAD_NANDF_RB3__ECSPI2_MISO (_MX51_PAD_NANDF_RB3__ECSPI2_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1023 | #define MX51_PAD_NANDF_RB3__FEC_RX_CLK (_MX51_PAD_NANDF_RB3__FEC_RX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_2)) | ||
| 1024 | #define MX51_PAD_NANDF_RB3__GPIO3_11 (_MX51_PAD_NANDF_RB3__GPIO3_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1025 | #define MX51_PAD_NANDF_RB3__NANDF_RB3 (_MX51_PAD_NANDF_RB3__NANDF_RB3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1026 | #define MX51_PAD_NANDF_RB3__USBH3_CLK (_MX51_PAD_NANDF_RB3__USBH3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1027 | #define MX51_PAD_NANDF_RB3__USBH3_H3_DM (_MX51_PAD_NANDF_RB3__USBH3_H3_DM | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1028 | #define MX51_PAD_GPIO_NAND__GPIO_NAND (_MX51_PAD_GPIO_NAND__GPIO_NAND | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1029 | #define MX51_PAD_GPIO_NAND__PATA_INTRQ (_MX51_PAD_GPIO_NAND__PATA_INTRQ | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1030 | #define MX51_PAD_NANDF_CS0__GPIO3_16 (_MX51_PAD_NANDF_CS0__GPIO3_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1031 | #define MX51_PAD_NANDF_CS0__NANDF_CS0 (_MX51_PAD_NANDF_CS0__NANDF_CS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1032 | #define MX51_PAD_NANDF_CS1__GPIO3_17 (_MX51_PAD_NANDF_CS1__GPIO3_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1033 | #define MX51_PAD_NANDF_CS1__NANDF_CS1 (_MX51_PAD_NANDF_CS1__NANDF_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1034 | #define MX51_PAD_NANDF_CS2__CSPI_SCLK (_MX51_PAD_NANDF_CS2__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1035 | #define MX51_PAD_NANDF_CS2__FEC_TX_ER (_MX51_PAD_NANDF_CS2__FEC_TX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) | ||
| 1036 | #define MX51_PAD_NANDF_CS2__GPIO3_18 (_MX51_PAD_NANDF_CS2__GPIO3_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1037 | #define MX51_PAD_NANDF_CS2__NANDF_CS2 (_MX51_PAD_NANDF_CS2__NANDF_CS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1038 | #define MX51_PAD_NANDF_CS2__PATA_CS_0 (_MX51_PAD_NANDF_CS2__PATA_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1039 | #define MX51_PAD_NANDF_CS2__SD4_CLK (_MX51_PAD_NANDF_CS2__SD4_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1040 | #define MX51_PAD_NANDF_CS2__USBH3_H1_DP (_MX51_PAD_NANDF_CS2__USBH3_H1_DP | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1041 | #define MX51_PAD_NANDF_CS3__FEC_MDC (_MX51_PAD_NANDF_CS3__FEC_MDC | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) | ||
| 1042 | #define MX51_PAD_NANDF_CS3__GPIO3_19 (_MX51_PAD_NANDF_CS3__GPIO3_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1043 | #define MX51_PAD_NANDF_CS3__NANDF_CS3 (_MX51_PAD_NANDF_CS3__NANDF_CS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1044 | #define MX51_PAD_NANDF_CS3__PATA_CS_1 (_MX51_PAD_NANDF_CS3__PATA_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1045 | #define MX51_PAD_NANDF_CS3__SD4_DAT0 (_MX51_PAD_NANDF_CS3__SD4_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1046 | #define MX51_PAD_NANDF_CS3__USBH3_H1_DM (_MX51_PAD_NANDF_CS3__USBH3_H1_DM | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1047 | #define MX51_PAD_NANDF_CS4__FEC_TDATA1 (_MX51_PAD_NANDF_CS4__FEC_TDATA1 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) | ||
| 1048 | #define MX51_PAD_NANDF_CS4__GPIO3_20 (_MX51_PAD_NANDF_CS4__GPIO3_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1049 | #define MX51_PAD_NANDF_CS4__NANDF_CS4 (_MX51_PAD_NANDF_CS4__NANDF_CS4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1050 | #define MX51_PAD_NANDF_CS4__PATA_DA_0 (_MX51_PAD_NANDF_CS4__PATA_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1051 | #define MX51_PAD_NANDF_CS4__SD4_DAT1 (_MX51_PAD_NANDF_CS4__SD4_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1052 | #define MX51_PAD_NANDF_CS4__USBH3_STP (_MX51_PAD_NANDF_CS4__USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1053 | #define MX51_PAD_NANDF_CS5__FEC_TDATA2 (_MX51_PAD_NANDF_CS5__FEC_TDATA2 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) | ||
| 1054 | #define MX51_PAD_NANDF_CS5__GPIO3_21 (_MX51_PAD_NANDF_CS5__GPIO3_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1055 | #define MX51_PAD_NANDF_CS5__NANDF_CS5 (_MX51_PAD_NANDF_CS5__NANDF_CS5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1056 | #define MX51_PAD_NANDF_CS5__PATA_DA_1 (_MX51_PAD_NANDF_CS5__PATA_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1057 | #define MX51_PAD_NANDF_CS5__SD4_DAT2 (_MX51_PAD_NANDF_CS5__SD4_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1058 | #define MX51_PAD_NANDF_CS5__USBH3_DIR (_MX51_PAD_NANDF_CS5__USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1059 | #define MX51_PAD_NANDF_CS6__CSPI_SS3 (_MX51_PAD_NANDF_CS6__CSPI_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1060 | #define MX51_PAD_NANDF_CS6__FEC_TDATA3 (_MX51_PAD_NANDF_CS6__FEC_TDATA3 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) | ||
| 1061 | #define MX51_PAD_NANDF_CS6__GPIO3_22 (_MX51_PAD_NANDF_CS6__GPIO3_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1062 | #define MX51_PAD_NANDF_CS6__NANDF_CS6 (_MX51_PAD_NANDF_CS6__NANDF_CS6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1063 | #define MX51_PAD_NANDF_CS6__PATA_DA_2 (_MX51_PAD_NANDF_CS6__PATA_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1064 | #define MX51_PAD_NANDF_CS6__SD4_DAT3 (_MX51_PAD_NANDF_CS6__SD4_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1065 | #define MX51_PAD_NANDF_CS7__FEC_TX_EN (_MX51_PAD_NANDF_CS7__FEC_TX_EN | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) | ||
| 1066 | #define MX51_PAD_NANDF_CS7__GPIO3_23 (_MX51_PAD_NANDF_CS7__GPIO3_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1067 | #define MX51_PAD_NANDF_CS7__NANDF_CS7 (_MX51_PAD_NANDF_CS7__NANDF_CS7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1068 | #define MX51_PAD_NANDF_CS7__SD3_CLK (_MX51_PAD_NANDF_CS7__SD3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1069 | #define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 (_MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1070 | #define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK (_MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_4)) | ||
| 1071 | #define MX51_PAD_NANDF_RDY_INT__GPIO3_24 (_MX51_PAD_NANDF_RDY_INT__GPIO3_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1072 | #define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT (_MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1073 | #define MX51_PAD_NANDF_RDY_INT__SD3_CMD (_MX51_PAD_NANDF_RDY_INT__SD3_CMD | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1074 | #define MX51_PAD_NANDF_D15__ECSPI2_MOSI (_MX51_PAD_NANDF_D15__ECSPI2_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1075 | #define MX51_PAD_NANDF_D15__GPIO3_25 (_MX51_PAD_NANDF_D15__GPIO3_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1076 | #define MX51_PAD_NANDF_D15__NANDF_D15 (_MX51_PAD_NANDF_D15__NANDF_D15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1077 | #define MX51_PAD_NANDF_D15__PATA_DATA15 (_MX51_PAD_NANDF_D15__PATA_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1078 | #define MX51_PAD_NANDF_D15__SD3_DAT7 (_MX51_PAD_NANDF_D15__SD3_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1079 | #define MX51_PAD_NANDF_D14__ECSPI2_SS3 (_MX51_PAD_NANDF_D14__ECSPI2_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1080 | #define MX51_PAD_NANDF_D14__GPIO3_26 (_MX51_PAD_NANDF_D14__GPIO3_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1081 | #define MX51_PAD_NANDF_D14__NANDF_D14 (_MX51_PAD_NANDF_D14__NANDF_D14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1082 | #define MX51_PAD_NANDF_D14__PATA_DATA14 (_MX51_PAD_NANDF_D14__PATA_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1083 | #define MX51_PAD_NANDF_D14__SD3_DAT6 (_MX51_PAD_NANDF_D14__SD3_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1084 | #define MX51_PAD_NANDF_D13__ECSPI2_SS2 (_MX51_PAD_NANDF_D13__ECSPI2_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1085 | #define MX51_PAD_NANDF_D13__GPIO3_27 (_MX51_PAD_NANDF_D13__GPIO3_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1086 | #define MX51_PAD_NANDF_D13__NANDF_D13 (_MX51_PAD_NANDF_D13__NANDF_D13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1087 | #define MX51_PAD_NANDF_D13__PATA_DATA13 (_MX51_PAD_NANDF_D13__PATA_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1088 | #define MX51_PAD_NANDF_D13__SD3_DAT5 (_MX51_PAD_NANDF_D13__SD3_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1089 | #define MX51_PAD_NANDF_D12__ECSPI2_SS1 (_MX51_PAD_NANDF_D12__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1090 | #define MX51_PAD_NANDF_D12__GPIO3_28 (_MX51_PAD_NANDF_D12__GPIO3_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1091 | #define MX51_PAD_NANDF_D12__NANDF_D12 (_MX51_PAD_NANDF_D12__NANDF_D12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1092 | #define MX51_PAD_NANDF_D12__PATA_DATA12 (_MX51_PAD_NANDF_D12__PATA_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1093 | #define MX51_PAD_NANDF_D12__SD3_DAT4 (_MX51_PAD_NANDF_D12__SD3_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1094 | #define MX51_PAD_NANDF_D11__FEC_RX_DV (_MX51_PAD_NANDF_D11__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1095 | #define MX51_PAD_NANDF_D11__GPIO3_29 (_MX51_PAD_NANDF_D11__GPIO3_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1096 | #define MX51_PAD_NANDF_D11__NANDF_D11 (_MX51_PAD_NANDF_D11__NANDF_D11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1097 | #define MX51_PAD_NANDF_D11__PATA_DATA11 (_MX51_PAD_NANDF_D11__PATA_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1098 | #define MX51_PAD_NANDF_D11__SD3_DATA3 (_MX51_PAD_NANDF_D11__SD3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1099 | #define MX51_PAD_NANDF_D10__GPIO3_30 (_MX51_PAD_NANDF_D10__GPIO3_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1100 | #define MX51_PAD_NANDF_D10__NANDF_D10 (_MX51_PAD_NANDF_D10__NANDF_D10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1101 | #define MX51_PAD_NANDF_D10__PATA_DATA10 (_MX51_PAD_NANDF_D10__PATA_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1102 | #define MX51_PAD_NANDF_D10__SD3_DATA2 (_MX51_PAD_NANDF_D10__SD3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1103 | #define MX51_PAD_NANDF_D9__FEC_RDATA0 (_MX51_PAD_NANDF_D9__FEC_RDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_4)) | ||
| 1104 | #define MX51_PAD_NANDF_D9__GPIO3_31 (_MX51_PAD_NANDF_D9__GPIO3_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1105 | #define MX51_PAD_NANDF_D9__NANDF_D9 (_MX51_PAD_NANDF_D9__NANDF_D9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1106 | #define MX51_PAD_NANDF_D9__PATA_DATA9 (_MX51_PAD_NANDF_D9__PATA_DATA9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1107 | #define MX51_PAD_NANDF_D9__SD3_DATA1 (_MX51_PAD_NANDF_D9__SD3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1108 | #define MX51_PAD_NANDF_D8__FEC_TDATA0 (_MX51_PAD_NANDF_D8__FEC_TDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) | ||
| 1109 | #define MX51_PAD_NANDF_D8__GPIO4_0 (_MX51_PAD_NANDF_D8__GPIO4_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1110 | #define MX51_PAD_NANDF_D8__NANDF_D8 (_MX51_PAD_NANDF_D8__NANDF_D8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1111 | #define MX51_PAD_NANDF_D8__PATA_DATA8 (_MX51_PAD_NANDF_D8__PATA_DATA8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1112 | #define MX51_PAD_NANDF_D8__SD3_DATA0 (_MX51_PAD_NANDF_D8__SD3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1113 | #define MX51_PAD_NANDF_D7__GPIO4_1 (_MX51_PAD_NANDF_D7__GPIO4_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1114 | #define MX51_PAD_NANDF_D7__NANDF_D7 (_MX51_PAD_NANDF_D7__NANDF_D7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1115 | #define MX51_PAD_NANDF_D7__PATA_DATA7 (_MX51_PAD_NANDF_D7__PATA_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1116 | #define MX51_PAD_NANDF_D7__USBH3_DATA0 (_MX51_PAD_NANDF_D7__USBH3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1117 | #define MX51_PAD_NANDF_D6__GPIO4_2 (_MX51_PAD_NANDF_D6__GPIO4_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1118 | #define MX51_PAD_NANDF_D6__NANDF_D6 (_MX51_PAD_NANDF_D6__NANDF_D6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1119 | #define MX51_PAD_NANDF_D6__PATA_DATA6 (_MX51_PAD_NANDF_D6__PATA_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1120 | #define MX51_PAD_NANDF_D6__SD4_LCTL (_MX51_PAD_NANDF_D6__SD4_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1121 | #define MX51_PAD_NANDF_D6__USBH3_DATA1 (_MX51_PAD_NANDF_D6__USBH3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1122 | #define MX51_PAD_NANDF_D5__GPIO4_3 (_MX51_PAD_NANDF_D5__GPIO4_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1123 | #define MX51_PAD_NANDF_D5__NANDF_D5 (_MX51_PAD_NANDF_D5__NANDF_D5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1124 | #define MX51_PAD_NANDF_D5__PATA_DATA5 (_MX51_PAD_NANDF_D5__PATA_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1125 | #define MX51_PAD_NANDF_D5__SD4_WP (_MX51_PAD_NANDF_D5__SD4_WP | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1126 | #define MX51_PAD_NANDF_D5__USBH3_DATA2 (_MX51_PAD_NANDF_D5__USBH3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1127 | #define MX51_PAD_NANDF_D4__GPIO4_4 (_MX51_PAD_NANDF_D4__GPIO4_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1128 | #define MX51_PAD_NANDF_D4__NANDF_D4 (_MX51_PAD_NANDF_D4__NANDF_D4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1129 | #define MX51_PAD_NANDF_D4__PATA_DATA4 (_MX51_PAD_NANDF_D4__PATA_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1130 | #define MX51_PAD_NANDF_D4__SD4_CD (_MX51_PAD_NANDF_D4__SD4_CD | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1131 | #define MX51_PAD_NANDF_D4__USBH3_DATA3 (_MX51_PAD_NANDF_D4__USBH3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1132 | #define MX51_PAD_NANDF_D3__GPIO4_5 (_MX51_PAD_NANDF_D3__GPIO4_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1133 | #define MX51_PAD_NANDF_D3__NANDF_D3 (_MX51_PAD_NANDF_D3__NANDF_D3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1134 | #define MX51_PAD_NANDF_D3__PATA_DATA3 (_MX51_PAD_NANDF_D3__PATA_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1135 | #define MX51_PAD_NANDF_D3__SD4_DAT4 (_MX51_PAD_NANDF_D3__SD4_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1136 | #define MX51_PAD_NANDF_D3__USBH3_DATA4 (_MX51_PAD_NANDF_D3__USBH3_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1137 | #define MX51_PAD_NANDF_D2__GPIO4_6 (_MX51_PAD_NANDF_D2__GPIO4_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1138 | #define MX51_PAD_NANDF_D2__NANDF_D2 (_MX51_PAD_NANDF_D2__NANDF_D2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1139 | #define MX51_PAD_NANDF_D2__PATA_DATA2 (_MX51_PAD_NANDF_D2__PATA_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1140 | #define MX51_PAD_NANDF_D2__SD4_DAT5 (_MX51_PAD_NANDF_D2__SD4_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1141 | #define MX51_PAD_NANDF_D2__USBH3_DATA5 (_MX51_PAD_NANDF_D2__USBH3_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1142 | #define MX51_PAD_NANDF_D1__GPIO4_7 (_MX51_PAD_NANDF_D1__GPIO4_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1143 | #define MX51_PAD_NANDF_D1__NANDF_D1 (_MX51_PAD_NANDF_D1__NANDF_D1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1144 | #define MX51_PAD_NANDF_D1__PATA_DATA1 (_MX51_PAD_NANDF_D1__PATA_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1145 | #define MX51_PAD_NANDF_D1__SD4_DAT6 (_MX51_PAD_NANDF_D1__SD4_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1146 | #define MX51_PAD_NANDF_D1__USBH3_DATA6 (_MX51_PAD_NANDF_D1__USBH3_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1147 | #define MX51_PAD_NANDF_D0__GPIO4_8 (_MX51_PAD_NANDF_D0__GPIO4_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1148 | #define MX51_PAD_NANDF_D0__NANDF_D0 (_MX51_PAD_NANDF_D0__NANDF_D0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1149 | #define MX51_PAD_NANDF_D0__PATA_DATA0 (_MX51_PAD_NANDF_D0__PATA_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1150 | #define MX51_PAD_NANDF_D0__SD4_DAT7 (_MX51_PAD_NANDF_D0__SD4_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1151 | #define MX51_PAD_NANDF_D0__USBH3_DATA7 (_MX51_PAD_NANDF_D0__USBH3_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1152 | #define MX51_PAD_CSI1_D8__CSI1_D8 (_MX51_PAD_CSI1_D8__CSI1_D8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1153 | #define MX51_PAD_CSI1_D8__GPIO3_12 (_MX51_PAD_CSI1_D8__GPIO3_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1154 | #define MX51_PAD_CSI1_D9__CSI1_D9 (_MX51_PAD_CSI1_D9__CSI1_D9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1155 | #define MX51_PAD_CSI1_D9__GPIO3_13 (_MX51_PAD_CSI1_D9__GPIO3_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1156 | #define MX51_PAD_CSI1_D10__CSI1_D10 (_MX51_PAD_CSI1_D10__CSI1_D10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1157 | #define MX51_PAD_CSI1_D11__CSI1_D11 (_MX51_PAD_CSI1_D11__CSI1_D11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1158 | #define MX51_PAD_CSI1_D12__CSI1_D12 (_MX51_PAD_CSI1_D12__CSI1_D12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1159 | #define MX51_PAD_CSI1_D13__CSI1_D13 (_MX51_PAD_CSI1_D13__CSI1_D13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1160 | #define MX51_PAD_CSI1_D14__CSI1_D14 (_MX51_PAD_CSI1_D14__CSI1_D14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1161 | #define MX51_PAD_CSI1_D15__CSI1_D15 (_MX51_PAD_CSI1_D15__CSI1_D15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1162 | #define MX51_PAD_CSI1_D16__CSI1_D16 (_MX51_PAD_CSI1_D16__CSI1_D16 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1163 | #define MX51_PAD_CSI1_D17__CSI1_D17 (_MX51_PAD_CSI1_D17__CSI1_D17 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1164 | #define MX51_PAD_CSI1_D18__CSI1_D18 (_MX51_PAD_CSI1_D18__CSI1_D18 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1165 | #define MX51_PAD_CSI1_D19__CSI1_D19 (_MX51_PAD_CSI1_D19__CSI1_D19 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1166 | #define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC (_MX51_PAD_CSI1_VSYNC__CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1167 | #define MX51_PAD_CSI1_VSYNC__GPIO3_14 (_MX51_PAD_CSI1_VSYNC__GPIO3_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1168 | #define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC (_MX51_PAD_CSI1_HSYNC__CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1169 | #define MX51_PAD_CSI1_HSYNC__GPIO3_15 (_MX51_PAD_CSI1_HSYNC__GPIO3_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1170 | #define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK (_MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1171 | #define MX51_PAD_CSI1_MCLK__CSI1_MCLK (_MX51_PAD_CSI1_MCLK__CSI1_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1172 | #define MX51_PAD_CSI2_D12__CSI2_D12 (_MX51_PAD_CSI2_D12__CSI2_D12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1173 | #define MX51_PAD_CSI2_D12__GPIO4_9 (_MX51_PAD_CSI2_D12__GPIO4_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1174 | #define MX51_PAD_CSI2_D13__CSI2_D13 (_MX51_PAD_CSI2_D13__CSI2_D13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1175 | #define MX51_PAD_CSI2_D13__GPIO4_10 (_MX51_PAD_CSI2_D13__GPIO4_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1176 | #define MX51_PAD_CSI2_D14__CSI2_D14 (_MX51_PAD_CSI2_D14__CSI2_D14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1177 | #define MX51_PAD_CSI2_D15__CSI2_D15 (_MX51_PAD_CSI2_D15__CSI2_D15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1178 | #define MX51_PAD_CSI2_D16__CSI2_D16 (_MX51_PAD_CSI2_D16__CSI2_D16 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1179 | #define MX51_PAD_CSI2_D17__CSI2_D17 (_MX51_PAD_CSI2_D17__CSI2_D17 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1180 | #define MX51_PAD_CSI2_D18__CSI2_D18 (_MX51_PAD_CSI2_D18__CSI2_D18 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1181 | #define MX51_PAD_CSI2_D18__GPIO4_11 (_MX51_PAD_CSI2_D18__GPIO4_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1182 | #define MX51_PAD_CSI2_D19__CSI2_D19 (_MX51_PAD_CSI2_D19__CSI2_D19 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1183 | #define MX51_PAD_CSI2_D19__GPIO4_12 (_MX51_PAD_CSI2_D19__GPIO4_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1184 | #define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC (_MX51_PAD_CSI2_VSYNC__CSI2_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1185 | #define MX51_PAD_CSI2_VSYNC__GPIO4_13 (_MX51_PAD_CSI2_VSYNC__GPIO4_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1186 | #define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC (_MX51_PAD_CSI2_HSYNC__CSI2_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1187 | #define MX51_PAD_CSI2_HSYNC__GPIO4_14 (_MX51_PAD_CSI2_HSYNC__GPIO4_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1188 | #define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK (_MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1189 | #define MX51_PAD_CSI2_PIXCLK__GPIO4_15 (_MX51_PAD_CSI2_PIXCLK__GPIO4_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1190 | #define MX51_PAD_I2C1_CLK__GPIO4_16 (_MX51_PAD_I2C1_CLK__GPIO4_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1191 | #define MX51_PAD_I2C1_CLK__I2C1_CLK (_MX51_PAD_I2C1_CLK__I2C1_CLK | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | ||
| 1192 | #define MX51_PAD_I2C1_DAT__GPIO4_17 (_MX51_PAD_I2C1_DAT__GPIO4_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1193 | #define MX51_PAD_I2C1_DAT__I2C1_DAT (_MX51_PAD_I2C1_DAT__I2C1_DAT | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | ||
| 1194 | #define MX51_PAD_AUD3_BB_TXD__AUD3_TXD (_MX51_PAD_AUD3_BB_TXD__AUD3_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1195 | #define MX51_PAD_AUD3_BB_TXD__GPIO4_18 (_MX51_PAD_AUD3_BB_TXD__GPIO4_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1196 | #define MX51_PAD_AUD3_BB_RXD__AUD3_RXD (_MX51_PAD_AUD3_BB_RXD__AUD3_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1197 | #define MX51_PAD_AUD3_BB_RXD__GPIO4_19 (_MX51_PAD_AUD3_BB_RXD__GPIO4_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1198 | #define MX51_PAD_AUD3_BB_RXD__UART3_RXD (_MX51_PAD_AUD3_BB_RXD__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 1199 | #define MX51_PAD_AUD3_BB_CK__AUD3_TXC (_MX51_PAD_AUD3_BB_CK__AUD3_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1200 | #define MX51_PAD_AUD3_BB_CK__GPIO4_20 (_MX51_PAD_AUD3_BB_CK__GPIO4_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1201 | #define MX51_PAD_AUD3_BB_FS__AUD3_TXFS (_MX51_PAD_AUD3_BB_FS__AUD3_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1202 | #define MX51_PAD_AUD3_BB_FS__GPIO4_21 (_MX51_PAD_AUD3_BB_FS__GPIO4_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1203 | #define MX51_PAD_AUD3_BB_FS__UART3_TXD (_MX51_PAD_AUD3_BB_FS__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 1204 | #define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI (_MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1205 | #define MX51_PAD_CSPI1_MOSI__GPIO4_22 (_MX51_PAD_CSPI1_MOSI__GPIO4_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1206 | #define MX51_PAD_CSPI1_MOSI__I2C1_SDA (_MX51_PAD_CSPI1_MOSI__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | ||
| 1207 | #define MX51_PAD_CSPI1_MISO__AUD4_RXD (_MX51_PAD_CSPI1_MISO__AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1208 | #define MX51_PAD_CSPI1_MISO__ECSPI1_MISO (_MX51_PAD_CSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1209 | #define MX51_PAD_CSPI1_MISO__GPIO4_23 (_MX51_PAD_CSPI1_MISO__GPIO4_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1210 | #define MX51_PAD_CSPI1_SS0__AUD4_TXC (_MX51_PAD_CSPI1_SS0__AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1211 | #define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 (_MX51_PAD_CSPI1_SS0__ECSPI1_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1212 | #define MX51_PAD_CSPI1_SS0__GPIO4_24 (_MX51_PAD_CSPI1_SS0__GPIO4_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1213 | #define MX51_PAD_CSPI1_SS1__AUD4_TXD (_MX51_PAD_CSPI1_SS1__AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1214 | #define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 (_MX51_PAD_CSPI1_SS1__ECSPI1_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1215 | #define MX51_PAD_CSPI1_SS1__GPIO4_25 (_MX51_PAD_CSPI1_SS1__GPIO4_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1216 | #define MX51_PAD_CSPI1_RDY__AUD4_TXFS (_MX51_PAD_CSPI1_RDY__AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1217 | #define MX51_PAD_CSPI1_RDY__ECSPI1_RDY (_MX51_PAD_CSPI1_RDY__ECSPI1_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1218 | #define MX51_PAD_CSPI1_RDY__GPIO4_26 (_MX51_PAD_CSPI1_RDY__GPIO4_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1219 | #define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK (_MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1220 | #define MX51_PAD_CSPI1_SCLK__GPIO4_27 (_MX51_PAD_CSPI1_SCLK__GPIO4_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1221 | #define MX51_PAD_CSPI1_SCLK__I2C1_SCL (_MX51_PAD_CSPI1_SCLK__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | ||
| 1222 | #define MX51_PAD_UART1_RXD__GPIO4_28 (_MX51_PAD_UART1_RXD__GPIO4_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1223 | #define MX51_PAD_UART1_RXD__UART1_RXD (_MX51_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 1224 | #define MX51_PAD_UART1_TXD__GPIO4_29 (_MX51_PAD_UART1_TXD__GPIO4_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1225 | #define MX51_PAD_UART1_TXD__PWM2_PWMO (_MX51_PAD_UART1_TXD__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1226 | #define MX51_PAD_UART1_TXD__UART1_TXD (_MX51_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 1227 | #define MX51_PAD_UART1_RTS__GPIO4_30 (_MX51_PAD_UART1_RTS__GPIO4_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1228 | #define MX51_PAD_UART1_RTS__UART1_RTS (_MX51_PAD_UART1_RTS__UART1_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 1229 | #define MX51_PAD_UART1_CTS__GPIO4_31 (_MX51_PAD_UART1_CTS__GPIO4_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1230 | #define MX51_PAD_UART1_CTS__UART1_CTS (_MX51_PAD_UART1_CTS__UART1_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 1231 | #define MX51_PAD_UART2_RXD__FIRI_TXD (_MX51_PAD_UART2_RXD__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1232 | #define MX51_PAD_UART2_RXD__GPIO1_20 (_MX51_PAD_UART2_RXD__GPIO1_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1233 | #define MX51_PAD_UART2_RXD__UART2_RXD (_MX51_PAD_UART2_RXD__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 1234 | #define MX51_PAD_UART2_TXD__FIRI_RXD (_MX51_PAD_UART2_TXD__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1235 | #define MX51_PAD_UART2_TXD__GPIO1_21 (_MX51_PAD_UART2_TXD__GPIO1_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1236 | #define MX51_PAD_UART2_TXD__UART2_TXD (_MX51_PAD_UART2_TXD__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 1237 | #define MX51_PAD_UART3_RXD__CSI1_D0 (_MX51_PAD_UART3_RXD__CSI1_D0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1238 | #define MX51_PAD_UART3_RXD__GPIO1_22 (_MX51_PAD_UART3_RXD__GPIO1_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1239 | #define MX51_PAD_UART3_RXD__UART1_DTR (_MX51_PAD_UART3_RXD__UART1_DTR | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1240 | #define MX51_PAD_UART3_RXD__UART3_RXD (_MX51_PAD_UART3_RXD__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 1241 | #define MX51_PAD_UART3_TXD__CSI1_D1 (_MX51_PAD_UART3_TXD__CSI1_D1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1242 | #define MX51_PAD_UART3_TXD__GPIO1_23 (_MX51_PAD_UART3_TXD__GPIO1_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1243 | #define MX51_PAD_UART3_TXD__UART1_DSR (_MX51_PAD_UART3_TXD__UART1_DSR | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 1244 | #define MX51_PAD_UART3_TXD__UART3_TXD (_MX51_PAD_UART3_TXD__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 1245 | #define MX51_PAD_OWIRE_LINE__GPIO1_24 (_MX51_PAD_OWIRE_LINE__GPIO1_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1246 | #define MX51_PAD_OWIRE_LINE__OWIRE_LINE (_MX51_PAD_OWIRE_LINE__OWIRE_LINE | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1247 | #define MX51_PAD_OWIRE_LINE__SPDIF_OUT (_MX51_PAD_OWIRE_LINE__SPDIF_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1248 | #define MX51_PAD_KEY_ROW0__KEY_ROW0 (_MX51_PAD_KEY_ROW0__KEY_ROW0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1249 | #define MX51_PAD_KEY_ROW1__KEY_ROW1 (_MX51_PAD_KEY_ROW1__KEY_ROW1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1250 | #define MX51_PAD_KEY_ROW2__KEY_ROW2 (_MX51_PAD_KEY_ROW2__KEY_ROW2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1251 | #define MX51_PAD_KEY_ROW3__KEY_ROW3 (_MX51_PAD_KEY_ROW3__KEY_ROW3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1252 | #define MX51_PAD_KEY_COL0__KEY_COL0 (_MX51_PAD_KEY_COL0__KEY_COL0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1253 | #define MX51_PAD_KEY_COL0__PLL1_BYP (_MX51_PAD_KEY_COL0__PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1254 | #define MX51_PAD_KEY_COL1__KEY_COL1 (_MX51_PAD_KEY_COL1__KEY_COL1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1255 | #define MX51_PAD_KEY_COL1__PLL2_BYP (_MX51_PAD_KEY_COL1__PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1256 | #define MX51_PAD_KEY_COL2__KEY_COL2 (_MX51_PAD_KEY_COL2__KEY_COL2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1257 | #define MX51_PAD_KEY_COL2__PLL3_BYP (_MX51_PAD_KEY_COL2__PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1258 | #define MX51_PAD_KEY_COL3__KEY_COL3 (_MX51_PAD_KEY_COL3__KEY_COL3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1259 | #define MX51_PAD_KEY_COL4__I2C2_SCL (_MX51_PAD_KEY_COL4__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | ||
| 1260 | #define MX51_PAD_KEY_COL4__KEY_COL4 (_MX51_PAD_KEY_COL4__KEY_COL4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1261 | #define MX51_PAD_KEY_COL4__SPDIF_OUT1 (_MX51_PAD_KEY_COL4__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1262 | #define MX51_PAD_KEY_COL4__UART1_RI (_MX51_PAD_KEY_COL4__UART1_RI | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 1263 | #define MX51_PAD_KEY_COL4__UART3_RTS (_MX51_PAD_KEY_COL4__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 1264 | #define MX51_PAD_KEY_COL5__I2C2_SDA (_MX51_PAD_KEY_COL5__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | ||
| 1265 | #define MX51_PAD_KEY_COL5__KEY_COL5 (_MX51_PAD_KEY_COL5__KEY_COL5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1266 | #define MX51_PAD_KEY_COL5__UART1_DCD (_MX51_PAD_KEY_COL5__UART1_DCD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 1267 | #define MX51_PAD_KEY_COL5__UART3_CTS (_MX51_PAD_KEY_COL5__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 1268 | #define MX51_PAD_USBH1_CLK__CSPI_SCLK (_MX51_PAD_USBH1_CLK__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1269 | #define MX51_PAD_USBH1_CLK__GPIO1_25 (_MX51_PAD_USBH1_CLK__GPIO1_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1270 | #define MX51_PAD_USBH1_CLK__I2C2_SCL (_MX51_PAD_USBH1_CLK__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | ||
| 1271 | #define MX51_PAD_USBH1_CLK__USBH1_CLK (_MX51_PAD_USBH1_CLK__USBH1_CLK | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) | ||
| 1272 | #define MX51_PAD_USBH1_DIR__CSPI_MOSI (_MX51_PAD_USBH1_DIR__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1273 | #define MX51_PAD_USBH1_DIR__GPIO1_26 (_MX51_PAD_USBH1_DIR__GPIO1_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1274 | #define MX51_PAD_USBH1_DIR__I2C2_SDA (_MX51_PAD_USBH1_DIR__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | ||
| 1275 | #define MX51_PAD_USBH1_DIR__USBH1_DIR (_MX51_PAD_USBH1_DIR__USBH1_DIR | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) | ||
| 1276 | #define MX51_PAD_USBH1_STP__CSPI_RDY (_MX51_PAD_USBH1_STP__CSPI_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1277 | #define MX51_PAD_USBH1_STP__GPIO1_27 (_MX51_PAD_USBH1_STP__GPIO1_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1278 | #define MX51_PAD_USBH1_STP__UART3_RXD (_MX51_PAD_USBH1_STP__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 1279 | #define MX51_PAD_USBH1_STP__USBH1_STP (_MX51_PAD_USBH1_STP__USBH1_STP | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) | ||
| 1280 | #define MX51_PAD_USBH1_NXT__CSPI_MISO (_MX51_PAD_USBH1_NXT__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1281 | #define MX51_PAD_USBH1_NXT__GPIO1_28 (_MX51_PAD_USBH1_NXT__GPIO1_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1282 | #define MX51_PAD_USBH1_NXT__UART3_TXD (_MX51_PAD_USBH1_NXT__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 1283 | #define MX51_PAD_USBH1_NXT__USBH1_NXT (_MX51_PAD_USBH1_NXT__USBH1_NXT | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) | ||
| 1284 | #define MX51_PAD_USBH1_DATA0__GPIO1_11 (_MX51_PAD_USBH1_DATA0__GPIO1_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1285 | #define MX51_PAD_USBH1_DATA0__UART2_CTS (_MX51_PAD_USBH1_DATA0__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 1286 | #define MX51_PAD_USBH1_DATA0__USBH1_DATA0 (_MX51_PAD_USBH1_DATA0__USBH1_DATA0 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) | ||
| 1287 | #define MX51_PAD_USBH1_DATA1__GPIO1_12 (_MX51_PAD_USBH1_DATA1__GPIO1_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1288 | #define MX51_PAD_USBH1_DATA1__UART2_RXD (_MX51_PAD_USBH1_DATA1__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 1289 | #define MX51_PAD_USBH1_DATA1__USBH1_DATA1 (_MX51_PAD_USBH1_DATA1__USBH1_DATA1 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) | ||
| 1290 | #define MX51_PAD_USBH1_DATA2__GPIO1_13 (_MX51_PAD_USBH1_DATA2__GPIO1_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1291 | #define MX51_PAD_USBH1_DATA2__UART2_TXD (_MX51_PAD_USBH1_DATA2__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 1292 | #define MX51_PAD_USBH1_DATA2__USBH1_DATA2 (_MX51_PAD_USBH1_DATA2__USBH1_DATA2 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) | ||
| 1293 | #define MX51_PAD_USBH1_DATA3__GPIO1_14 (_MX51_PAD_USBH1_DATA3__GPIO1_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1294 | #define MX51_PAD_USBH1_DATA3__UART2_RTS (_MX51_PAD_USBH1_DATA3__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 1295 | #define MX51_PAD_USBH1_DATA3__USBH1_DATA3 (_MX51_PAD_USBH1_DATA3__USBH1_DATA3 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) | ||
| 1296 | #define MX51_PAD_USBH1_DATA4__CSPI_SS0 (_MX51_PAD_USBH1_DATA4__CSPI_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1297 | #define MX51_PAD_USBH1_DATA4__GPIO1_15 (_MX51_PAD_USBH1_DATA4__GPIO1_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1298 | #define MX51_PAD_USBH1_DATA4__USBH1_DATA4 (_MX51_PAD_USBH1_DATA4__USBH1_DATA4 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) | ||
| 1299 | #define MX51_PAD_USBH1_DATA5__CSPI_SS1 (_MX51_PAD_USBH1_DATA5__CSPI_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1300 | #define MX51_PAD_USBH1_DATA5__GPIO1_16 (_MX51_PAD_USBH1_DATA5__GPIO1_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1301 | #define MX51_PAD_USBH1_DATA5__USBH1_DATA5 (_MX51_PAD_USBH1_DATA5__USBH1_DATA5 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) | ||
| 1302 | #define MX51_PAD_USBH1_DATA6__CSPI_SS3 (_MX51_PAD_USBH1_DATA6__CSPI_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1303 | #define MX51_PAD_USBH1_DATA6__GPIO1_17 (_MX51_PAD_USBH1_DATA6__GPIO1_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1304 | #define MX51_PAD_USBH1_DATA6__USBH1_DATA6 (_MX51_PAD_USBH1_DATA6__USBH1_DATA6 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) | ||
| 1305 | #define MX51_PAD_USBH1_DATA7__ECSPI1_SS3 (_MX51_PAD_USBH1_DATA7__ECSPI1_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1306 | #define MX51_PAD_USBH1_DATA7__ECSPI2_SS3 (_MX51_PAD_USBH1_DATA7__ECSPI2_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1307 | #define MX51_PAD_USBH1_DATA7__GPIO1_18 (_MX51_PAD_USBH1_DATA7__GPIO1_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1308 | #define MX51_PAD_USBH1_DATA7__USBH1_DATA7 (_MX51_PAD_USBH1_DATA7__USBH1_DATA7 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) | ||
| 1309 | #define MX51_PAD_DI1_PIN11__DI1_PIN11 (_MX51_PAD_DI1_PIN11__DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1310 | #define MX51_PAD_DI1_PIN11__ECSPI1_SS2 (_MX51_PAD_DI1_PIN11__ECSPI1_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1311 | #define MX51_PAD_DI1_PIN11__GPIO3_0 (_MX51_PAD_DI1_PIN11__GPIO3_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1312 | #define MX51_PAD_DI1_PIN12__DI1_PIN12 (_MX51_PAD_DI1_PIN12__DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1313 | #define MX51_PAD_DI1_PIN12__GPIO3_1 (_MX51_PAD_DI1_PIN12__GPIO3_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1314 | #define MX51_PAD_DI1_PIN13__DI1_PIN13 (_MX51_PAD_DI1_PIN13__DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1315 | #define MX51_PAD_DI1_PIN13__GPIO3_2 (_MX51_PAD_DI1_PIN13__GPIO3_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1316 | #define MX51_PAD_DI1_D0_CS__DI1_D0_CS (_MX51_PAD_DI1_D0_CS__DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1317 | #define MX51_PAD_DI1_D0_CS__GPIO3_3 (_MX51_PAD_DI1_D0_CS__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1318 | #define MX51_PAD_DI1_D1_CS__DI1_D1_CS (_MX51_PAD_DI1_D1_CS__DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1319 | #define MX51_PAD_DI1_D1_CS__DISP1_PIN14 (_MX51_PAD_DI1_D1_CS__DISP1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1320 | #define MX51_PAD_DI1_D1_CS__DISP1_PIN5 (_MX51_PAD_DI1_D1_CS__DISP1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1321 | #define MX51_PAD_DI1_D1_CS__GPIO3_4 (_MX51_PAD_DI1_D1_CS__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1322 | #define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 (_MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1323 | #define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN (_MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1324 | #define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 (_MX51_PAD_DISPB2_SER_DIN__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1325 | #define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 (_MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1326 | #define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO (_MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1327 | #define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 (_MX51_PAD_DISPB2_SER_DIO__GPIO3_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1328 | #define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 (_MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1329 | #define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 (_MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1330 | #define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK (_MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1331 | #define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 (_MX51_PAD_DISPB2_SER_CLK__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1332 | #define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK (_MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1333 | #define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 (_MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1334 | #define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 (_MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1335 | #define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS (_MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1336 | #define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS (_MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1337 | #define MX51_PAD_DISPB2_SER_RS__GPIO3_8 (_MX51_PAD_DISPB2_SER_RS__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | ||
| 1338 | #define MX51_PAD_DISP1_DAT0__DISP1_DAT0 (_MX51_PAD_DISP1_DAT0__DISP1_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1339 | #define MX51_PAD_DISP1_DAT1__DISP1_DAT1 (_MX51_PAD_DISP1_DAT1__DISP1_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1340 | #define MX51_PAD_DISP1_DAT2__DISP1_DAT2 (_MX51_PAD_DISP1_DAT2__DISP1_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1341 | #define MX51_PAD_DISP1_DAT3__DISP1_DAT3 (_MX51_PAD_DISP1_DAT3__DISP1_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1342 | #define MX51_PAD_DISP1_DAT4__DISP1_DAT4 (_MX51_PAD_DISP1_DAT4__DISP1_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1343 | #define MX51_PAD_DISP1_DAT5__DISP1_DAT5 (_MX51_PAD_DISP1_DAT5__DISP1_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1344 | #define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC (_MX51_PAD_DISP1_DAT6__BOOT_USB_SRC | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1345 | #define MX51_PAD_DISP1_DAT6__DISP1_DAT6 (_MX51_PAD_DISP1_DAT6__DISP1_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1346 | #define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG (_MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1347 | #define MX51_PAD_DISP1_DAT7__DISP1_DAT7 (_MX51_PAD_DISP1_DAT7__DISP1_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1348 | #define MX51_PAD_DISP1_DAT8__BOOT_SRC0 (_MX51_PAD_DISP1_DAT8__BOOT_SRC0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1349 | #define MX51_PAD_DISP1_DAT8__DISP1_DAT8 (_MX51_PAD_DISP1_DAT8__DISP1_DAT8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1350 | #define MX51_PAD_DISP1_DAT9__BOOT_SRC1 (_MX51_PAD_DISP1_DAT9__BOOT_SRC1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1351 | #define MX51_PAD_DISP1_DAT9__DISP1_DAT9 (_MX51_PAD_DISP1_DAT9__DISP1_DAT9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1352 | #define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE (_MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1353 | #define MX51_PAD_DISP1_DAT10__DISP1_DAT10 (_MX51_PAD_DISP1_DAT10__DISP1_DAT10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1354 | #define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 (_MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1355 | #define MX51_PAD_DISP1_DAT11__DISP1_DAT11 (_MX51_PAD_DISP1_DAT11__DISP1_DAT11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1356 | #define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL (_MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1357 | #define MX51_PAD_DISP1_DAT12__DISP1_DAT12 (_MX51_PAD_DISP1_DAT12__DISP1_DAT12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1358 | #define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 (_MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1359 | #define MX51_PAD_DISP1_DAT13__DISP1_DAT13 (_MX51_PAD_DISP1_DAT13__DISP1_DAT13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1360 | #define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 (_MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1361 | #define MX51_PAD_DISP1_DAT14__DISP1_DAT14 (_MX51_PAD_DISP1_DAT14__DISP1_DAT14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1362 | #define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH (_MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1363 | #define MX51_PAD_DISP1_DAT15__DISP1_DAT15 (_MX51_PAD_DISP1_DAT15__DISP1_DAT15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1364 | #define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 (_MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1365 | #define MX51_PAD_DISP1_DAT16__DISP1_DAT16 (_MX51_PAD_DISP1_DAT16__DISP1_DAT16 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1366 | #define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 (_MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1367 | #define MX51_PAD_DISP1_DAT17__DISP1_DAT17 (_MX51_PAD_DISP1_DAT17__DISP1_DAT17 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1368 | #define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 (_MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1369 | #define MX51_PAD_DISP1_DAT18__DISP1_DAT18 (_MX51_PAD_DISP1_DAT18__DISP1_DAT18 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1370 | #define MX51_PAD_DISP1_DAT18__DISP2_PIN11 (_MX51_PAD_DISP1_DAT18__DISP2_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1371 | #define MX51_PAD_DISP1_DAT18__DISP2_PIN5 (_MX51_PAD_DISP1_DAT18__DISP2_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1372 | #define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 (_MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1373 | #define MX51_PAD_DISP1_DAT19__DISP1_DAT19 (_MX51_PAD_DISP1_DAT19__DISP1_DAT19 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1374 | #define MX51_PAD_DISP1_DAT19__DISP2_PIN12 (_MX51_PAD_DISP1_DAT19__DISP2_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1375 | #define MX51_PAD_DISP1_DAT19__DISP2_PIN6 (_MX51_PAD_DISP1_DAT19__DISP2_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1376 | #define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 (_MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1377 | #define MX51_PAD_DISP1_DAT20__DISP1_DAT20 (_MX51_PAD_DISP1_DAT20__DISP1_DAT20 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1378 | #define MX51_PAD_DISP1_DAT20__DISP2_PIN13 (_MX51_PAD_DISP1_DAT20__DISP2_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1379 | #define MX51_PAD_DISP1_DAT20__DISP2_PIN7 (_MX51_PAD_DISP1_DAT20__DISP2_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1380 | #define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 (_MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1381 | #define MX51_PAD_DISP1_DAT21__DISP1_DAT21 (_MX51_PAD_DISP1_DAT21__DISP1_DAT21 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1382 | #define MX51_PAD_DISP1_DAT21__DISP2_PIN14 (_MX51_PAD_DISP1_DAT21__DISP2_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1383 | #define MX51_PAD_DISP1_DAT21__DISP2_PIN8 (_MX51_PAD_DISP1_DAT21__DISP2_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1384 | #define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 (_MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1385 | #define MX51_PAD_DISP1_DAT22__DISP1_DAT22 (_MX51_PAD_DISP1_DAT22__DISP1_DAT22 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1386 | #define MX51_PAD_DISP1_DAT22__DISP2_D0_CS (_MX51_PAD_DISP1_DAT22__DISP2_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1387 | #define MX51_PAD_DISP1_DAT22__DISP2_DAT16 (_MX51_PAD_DISP1_DAT22__DISP2_DAT16 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1388 | #define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 (_MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1389 | #define MX51_PAD_DISP1_DAT23__DISP1_DAT23 (_MX51_PAD_DISP1_DAT23__DISP1_DAT23 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1390 | #define MX51_PAD_DISP1_DAT23__DISP2_D1_CS (_MX51_PAD_DISP1_DAT23__DISP2_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1391 | #define MX51_PAD_DISP1_DAT23__DISP2_DAT17 (_MX51_PAD_DISP1_DAT23__DISP2_DAT17 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1392 | #define MX51_PAD_DISP1_DAT23__DISP2_SER_CS (_MX51_PAD_DISP1_DAT23__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1393 | #define MX51_PAD_DI1_PIN3__DI1_PIN3 (_MX51_PAD_DI1_PIN3__DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1394 | #define MX51_PAD_DI1_PIN2__DI1_PIN2 (_MX51_PAD_DI1_PIN2__DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1395 | #define MX51_PAD_DI_GP2__DISP1_SER_CLK (_MX51_PAD_DI_GP2__DISP1_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1396 | #define MX51_PAD_DI_GP2__DISP2_WAIT (_MX51_PAD_DI_GP2__DISP2_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1397 | #define MX51_PAD_DI_GP3__CSI1_DATA_EN (_MX51_PAD_DI_GP3__CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1398 | #define MX51_PAD_DI_GP3__DISP1_SER_DIO (_MX51_PAD_DI_GP3__DISP1_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1399 | #define MX51_PAD_DI_GP3__FEC_TX_ER (_MX51_PAD_DI_GP3__FEC_TX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) | ||
| 1400 | #define MX51_PAD_DI2_PIN4__CSI2_DATA_EN (_MX51_PAD_DI2_PIN4__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1401 | #define MX51_PAD_DI2_PIN4__DI2_PIN4 (_MX51_PAD_DI2_PIN4__DI2_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1402 | #define MX51_PAD_DI2_PIN4__FEC_CRS (_MX51_PAD_DI2_PIN4__FEC_CRS | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1403 | #define MX51_PAD_DI2_PIN2__DI2_PIN2 (_MX51_PAD_DI2_PIN2__DI2_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1404 | #define MX51_PAD_DI2_PIN2__FEC_MDC (_MX51_PAD_DI2_PIN2__FEC_MDC | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) | ||
| 1405 | #define MX51_PAD_DI2_PIN3__DI2_PIN3 (_MX51_PAD_DI2_PIN3__DI2_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1406 | #define MX51_PAD_DI2_PIN3__FEC_MDIO (_MX51_PAD_DI2_PIN3__FEC_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1407 | #define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK (_MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1408 | #define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 (_MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1409 | #define MX51_PAD_DI_GP4__DI2_PIN15 (_MX51_PAD_DI_GP4__DI2_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1410 | #define MX51_PAD_DI_GP4__DISP1_SER_DIN (_MX51_PAD_DI_GP4__DISP1_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1411 | #define MX51_PAD_DI_GP4__DISP2_PIN1 (_MX51_PAD_DI_GP4__DISP2_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1412 | #define MX51_PAD_DI_GP4__FEC_RDATA2 (_MX51_PAD_DI_GP4__FEC_RDATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1413 | #define MX51_PAD_DISP2_DAT0__DISP2_DAT0 (_MX51_PAD_DISP2_DAT0__DISP2_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1414 | #define MX51_PAD_DISP2_DAT0__FEC_RDATA3 (_MX51_PAD_DISP2_DAT0__FEC_RDATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1415 | #define MX51_PAD_DISP2_DAT0__KEY_COL6 (_MX51_PAD_DISP2_DAT0__KEY_COL6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1416 | #define MX51_PAD_DISP2_DAT0__UART3_RXD (_MX51_PAD_DISP2_DAT0__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 1417 | #define MX51_PAD_DISP2_DAT0__USBH3_CLK (_MX51_PAD_DISP2_DAT0__USBH3_CLK | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 1418 | #define MX51_PAD_DISP2_DAT1__DISP2_DAT1 (_MX51_PAD_DISP2_DAT1__DISP2_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1419 | #define MX51_PAD_DISP2_DAT1__FEC_RX_ER (_MX51_PAD_DISP2_DAT1__FEC_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1420 | #define MX51_PAD_DISP2_DAT1__KEY_COL7 (_MX51_PAD_DISP2_DAT1__KEY_COL7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1421 | #define MX51_PAD_DISP2_DAT1__UART3_TXD (_MX51_PAD_DISP2_DAT1__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | ||
| 1422 | #define MX51_PAD_DISP2_DAT1__USBH3_DIR (_MX51_PAD_DISP2_DAT1__USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1423 | #define MX51_PAD_DISP2_DAT2__DISP2_DAT2 (_MX51_PAD_DISP2_DAT2__DISP2_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1424 | #define MX51_PAD_DISP2_DAT3__DISP2_DAT3 (_MX51_PAD_DISP2_DAT3__DISP2_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1425 | #define MX51_PAD_DISP2_DAT4__DISP2_DAT4 (_MX51_PAD_DISP2_DAT4__DISP2_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1426 | #define MX51_PAD_DISP2_DAT5__DISP2_DAT5 (_MX51_PAD_DISP2_DAT5__DISP2_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1427 | #define MX51_PAD_DISP2_DAT6__DISP2_DAT6 (_MX51_PAD_DISP2_DAT6__DISP2_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1428 | #define MX51_PAD_DISP2_DAT6__FEC_TDATA1 (_MX51_PAD_DISP2_DAT6__FEC_TDATA1 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) | ||
| 1429 | #define MX51_PAD_DISP2_DAT6__GPIO1_19 (_MX51_PAD_DISP2_DAT6__GPIO1_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1430 | #define MX51_PAD_DISP2_DAT6__KEY_ROW4 (_MX51_PAD_DISP2_DAT6__KEY_ROW4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1431 | #define MX51_PAD_DISP2_DAT6__USBH3_STP (_MX51_PAD_DISP2_DAT6__USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1432 | #define MX51_PAD_DISP2_DAT7__DISP2_DAT7 (_MX51_PAD_DISP2_DAT7__DISP2_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1433 | #define MX51_PAD_DISP2_DAT7__FEC_TDATA2 (_MX51_PAD_DISP2_DAT7__FEC_TDATA2 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) | ||
| 1434 | #define MX51_PAD_DISP2_DAT7__GPIO1_29 (_MX51_PAD_DISP2_DAT7__GPIO1_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1435 | #define MX51_PAD_DISP2_DAT7__KEY_ROW5 (_MX51_PAD_DISP2_DAT7__KEY_ROW5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1436 | #define MX51_PAD_DISP2_DAT7__USBH3_NXT (_MX51_PAD_DISP2_DAT7__USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1437 | #define MX51_PAD_DISP2_DAT8__DISP2_DAT8 (_MX51_PAD_DISP2_DAT8__DISP2_DAT8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1438 | #define MX51_PAD_DISP2_DAT8__FEC_TDATA3 (_MX51_PAD_DISP2_DAT8__FEC_TDATA3 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) | ||
| 1439 | #define MX51_PAD_DISP2_DAT8__GPIO1_30 (_MX51_PAD_DISP2_DAT8__GPIO1_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1440 | #define MX51_PAD_DISP2_DAT8__KEY_ROW6 (_MX51_PAD_DISP2_DAT8__KEY_ROW6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1441 | #define MX51_PAD_DISP2_DAT8__USBH3_DATA0 (_MX51_PAD_DISP2_DAT8__USBH3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1442 | #define MX51_PAD_DISP2_DAT9__AUD6_RXC (_MX51_PAD_DISP2_DAT9__AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1443 | #define MX51_PAD_DISP2_DAT9__DISP2_DAT9 (_MX51_PAD_DISP2_DAT9__DISP2_DAT9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1444 | #define MX51_PAD_DISP2_DAT9__FEC_TX_EN (_MX51_PAD_DISP2_DAT9__FEC_TX_EN | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) | ||
| 1445 | #define MX51_PAD_DISP2_DAT9__GPIO1_31 (_MX51_PAD_DISP2_DAT9__GPIO1_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1446 | #define MX51_PAD_DISP2_DAT9__USBH3_DATA1 (_MX51_PAD_DISP2_DAT9__USBH3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1447 | #define MX51_PAD_DISP2_DAT10__DISP2_DAT10 (_MX51_PAD_DISP2_DAT10__DISP2_DAT10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1448 | #define MX51_PAD_DISP2_DAT10__DISP2_SER_CS (_MX51_PAD_DISP2_DAT10__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1449 | #define MX51_PAD_DISP2_DAT10__FEC_COL (_MX51_PAD_DISP2_DAT10__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1450 | #define MX51_PAD_DISP2_DAT10__KEY_ROW7 (_MX51_PAD_DISP2_DAT10__KEY_ROW7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1451 | #define MX51_PAD_DISP2_DAT10__USBH3_DATA2 (_MX51_PAD_DISP2_DAT10__USBH3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1452 | #define MX51_PAD_DISP2_DAT11__AUD6_TXD (_MX51_PAD_DISP2_DAT11__AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1453 | #define MX51_PAD_DISP2_DAT11__DISP2_DAT11 (_MX51_PAD_DISP2_DAT11__DISP2_DAT11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1454 | #define MX51_PAD_DISP2_DAT11__FEC_RX_CLK (_MX51_PAD_DISP2_DAT11__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1455 | #define MX51_PAD_DISP2_DAT11__GPIO1_10 (_MX51_PAD_DISP2_DAT11__GPIO1_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1456 | #define MX51_PAD_DISP2_DAT11__USBH3_DATA3 (_MX51_PAD_DISP2_DAT11__USBH3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1457 | #define MX51_PAD_DISP2_DAT12__AUD6_RXD (_MX51_PAD_DISP2_DAT12__AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1458 | #define MX51_PAD_DISP2_DAT12__DISP2_DAT12 (_MX51_PAD_DISP2_DAT12__DISP2_DAT12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1459 | #define MX51_PAD_DISP2_DAT12__FEC_RX_DV (_MX51_PAD_DISP2_DAT12__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1460 | #define MX51_PAD_DISP2_DAT12__USBH3_DATA4 (_MX51_PAD_DISP2_DAT12__USBH3_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1461 | #define MX51_PAD_DISP2_DAT13__AUD6_TXC (_MX51_PAD_DISP2_DAT13__AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1462 | #define MX51_PAD_DISP2_DAT13__DISP2_DAT13 (_MX51_PAD_DISP2_DAT13__DISP2_DAT13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1463 | #define MX51_PAD_DISP2_DAT13__FEC_TX_CLK (_MX51_PAD_DISP2_DAT13__FEC_TX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_4)) | ||
| 1464 | #define MX51_PAD_DISP2_DAT13__USBH3_DATA5 (_MX51_PAD_DISP2_DAT13__USBH3_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1465 | #define MX51_PAD_DISP2_DAT14__AUD6_TXFS (_MX51_PAD_DISP2_DAT14__AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1466 | #define MX51_PAD_DISP2_DAT14__DISP2_DAT14 (_MX51_PAD_DISP2_DAT14__DISP2_DAT14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1467 | #define MX51_PAD_DISP2_DAT14__FEC_RDATA0 (_MX51_PAD_DISP2_DAT14__FEC_RDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_4)) | ||
| 1468 | #define MX51_PAD_DISP2_DAT14__USBH3_DATA6 (_MX51_PAD_DISP2_DAT14__USBH3_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1469 | #define MX51_PAD_DISP2_DAT15__AUD6_RXFS (_MX51_PAD_DISP2_DAT15__AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1470 | #define MX51_PAD_DISP2_DAT15__DISP1_SER_CS (_MX51_PAD_DISP2_DAT15__DISP1_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1471 | #define MX51_PAD_DISP2_DAT15__DISP2_DAT15 (_MX51_PAD_DISP2_DAT15__DISP2_DAT15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1472 | #define MX51_PAD_DISP2_DAT15__FEC_TDATA0 (_MX51_PAD_DISP2_DAT15__FEC_TDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) | ||
| 1473 | #define MX51_PAD_DISP2_DAT15__USBH3_DATA7 (_MX51_PAD_DISP2_DAT15__USBH3_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1474 | #define MX51_PAD_SD1_CMD__AUD5_RXFS (_MX51_PAD_SD1_CMD__AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1475 | #define MX51_PAD_SD1_CMD__CSPI_MOSI (_MX51_PAD_SD1_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1476 | #define MX51_PAD_SD1_CMD__SD1_CMD (_MX51_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) | ||
| 1477 | #define MX51_PAD_SD1_CLK__AUD5_RXC (_MX51_PAD_SD1_CLK__AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1478 | #define MX51_PAD_SD1_CLK__CSPI_SCLK (_MX51_PAD_SD1_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1479 | #define MX51_PAD_SD1_CLK__SD1_CLK (_MX51_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)) | ||
| 1480 | #define MX51_PAD_SD1_DATA0__AUD5_TXD (_MX51_PAD_SD1_DATA0__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1481 | #define MX51_PAD_SD1_DATA0__CSPI_MISO (_MX51_PAD_SD1_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1482 | #define MX51_PAD_SD1_DATA0__SD1_DATA0 (_MX51_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1483 | #define MX51_PAD_EIM_DA0__EIM_DA0 (_MX51_PAD_EIM_DA0__EIM_DA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1484 | #define MX51_PAD_EIM_DA1__EIM_DA1 (_MX51_PAD_EIM_DA1__EIM_DA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1485 | #define MX51_PAD_EIM_DA2__EIM_DA2 (_MX51_PAD_EIM_DA2__EIM_DA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1486 | #define MX51_PAD_EIM_DA3__EIM_DA3 (_MX51_PAD_EIM_DA3__EIM_DA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1487 | #define MX51_PAD_SD1_DATA1__AUD5_RXD (_MX51_PAD_SD1_DATA1__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1488 | #define MX51_PAD_SD1_DATA1__SD1_DATA1 (_MX51_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1489 | #define MX51_PAD_EIM_DA4__EIM_DA4 (_MX51_PAD_EIM_DA4__EIM_DA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1490 | #define MX51_PAD_EIM_DA5__EIM_DA5 (_MX51_PAD_EIM_DA5__EIM_DA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1491 | #define MX51_PAD_EIM_DA6__EIM_DA6 (_MX51_PAD_EIM_DA6__EIM_DA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1492 | #define MX51_PAD_EIM_DA7__EIM_DA7 (_MX51_PAD_EIM_DA7__EIM_DA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1493 | #define MX51_PAD_SD1_DATA2__AUD5_TXC (_MX51_PAD_SD1_DATA2__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1494 | #define MX51_PAD_SD1_DATA2__SD1_DATA2 (_MX51_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1495 | #define MX51_PAD_EIM_DA10__EIM_DA10 (_MX51_PAD_EIM_DA10__EIM_DA10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1496 | #define MX51_PAD_EIM_DA11__EIM_DA11 (_MX51_PAD_EIM_DA11__EIM_DA11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1497 | #define MX51_PAD_EIM_DA8__EIM_DA8 (_MX51_PAD_EIM_DA8__EIM_DA8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1498 | #define MX51_PAD_EIM_DA9__EIM_DA9 (_MX51_PAD_EIM_DA9__EIM_DA9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1499 | #define MX51_PAD_SD1_DATA3__AUD5_TXFS (_MX51_PAD_SD1_DATA3__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1500 | #define MX51_PAD_SD1_DATA3__CSPI_SS1 (_MX51_PAD_SD1_DATA3__CSPI_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1501 | #define MX51_PAD_SD1_DATA3__SD1_DATA3 (_MX51_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1502 | #define MX51_PAD_GPIO1_0__CSPI_SS2 (_MX51_PAD_GPIO1_0__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1503 | #define MX51_PAD_GPIO1_0__GPIO1_0 (_MX51_PAD_GPIO1_0__GPIO1_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1504 | #define MX51_PAD_GPIO1_0__SD1_CD (_MX51_PAD_GPIO1_0__SD1_CD | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL)) | ||
| 1505 | #define MX51_PAD_GPIO1_1__CSPI_MISO (_MX51_PAD_GPIO1_1__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1506 | #define MX51_PAD_GPIO1_1__GPIO1_1 (_MX51_PAD_GPIO1_1__GPIO1_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1507 | #define MX51_PAD_GPIO1_1__SD1_WP (_MX51_PAD_GPIO1_1__SD1_WP | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL)) | ||
| 1508 | #define MX51_PAD_EIM_DA12__EIM_DA12 (_MX51_PAD_EIM_DA12__EIM_DA12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1509 | #define MX51_PAD_EIM_DA13__EIM_DA13 (_MX51_PAD_EIM_DA13__EIM_DA13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1510 | #define MX51_PAD_EIM_DA14__EIM_DA14 (_MX51_PAD_EIM_DA14__EIM_DA14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1511 | #define MX51_PAD_EIM_DA15__EIM_DA15 (_MX51_PAD_EIM_DA15__EIM_DA15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1512 | #define MX51_PAD_SD2_CMD__CSPI_MOSI (_MX51_PAD_SD2_CMD__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1513 | #define MX51_PAD_SD2_CMD__I2C1_SCL (_MX51_PAD_SD2_CMD__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | ||
| 1514 | #define MX51_PAD_SD2_CMD__SD2_CMD (_MX51_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) | ||
| 1515 | #define MX51_PAD_SD2_CLK__CSPI_SCLK (_MX51_PAD_SD2_CLK__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1516 | #define MX51_PAD_SD2_CLK__I2C1_SDA (_MX51_PAD_SD2_CLK__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | ||
| 1517 | #define MX51_PAD_SD2_CLK__SD2_CLK (_MX51_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)) | ||
| 1518 | #define MX51_PAD_SD2_DATA0__CSPI_MISO (_MX51_PAD_SD2_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1519 | #define MX51_PAD_SD2_DATA0__SD1_DAT4 (_MX51_PAD_SD2_DATA0__SD1_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1520 | #define MX51_PAD_SD2_DATA0__SD2_DATA0 (_MX51_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1521 | #define MX51_PAD_SD2_DATA1__SD1_DAT5 (_MX51_PAD_SD2_DATA1__SD1_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1522 | #define MX51_PAD_SD2_DATA1__SD2_DATA1 (_MX51_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1523 | #define MX51_PAD_SD2_DATA1__USBH3_H2_DP (_MX51_PAD_SD2_DATA1__USBH3_H2_DP | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1524 | #define MX51_PAD_SD2_DATA2__SD1_DAT6 (_MX51_PAD_SD2_DATA2__SD1_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1525 | #define MX51_PAD_SD2_DATA2__SD2_DATA2 (_MX51_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1526 | #define MX51_PAD_SD2_DATA2__USBH3_H2_DM (_MX51_PAD_SD2_DATA2__USBH3_H2_DM | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1527 | #define MX51_PAD_SD2_DATA3__CSPI_SS2 (_MX51_PAD_SD2_DATA3__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | ||
| 1528 | #define MX51_PAD_SD2_DATA3__SD1_DAT7 (_MX51_PAD_SD2_DATA3__SD1_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1529 | #define MX51_PAD_SD2_DATA3__SD2_DATA3 (_MX51_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1530 | #define MX51_PAD_GPIO1_2__CCM_OUT_2 (_MX51_PAD_GPIO1_2__CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1531 | #define MX51_PAD_GPIO1_2__GPIO1_2 (_MX51_PAD_GPIO1_2__GPIO1_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1532 | #define MX51_PAD_GPIO1_2__I2C2_SCL (_MX51_PAD_GPIO1_2__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | ||
| 1533 | #define MX51_PAD_GPIO1_2__PLL1_BYP (_MX51_PAD_GPIO1_2__PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1534 | #define MX51_PAD_GPIO1_2__PWM1_PWMO (_MX51_PAD_GPIO1_2__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1535 | #define MX51_PAD_GPIO1_3__GPIO1_3 (_MX51_PAD_GPIO1_3__GPIO1_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1536 | #define MX51_PAD_GPIO1_3__I2C2_SDA (_MX51_PAD_GPIO1_3__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | ||
| 1537 | #define MX51_PAD_GPIO1_3__PLL2_BYP (_MX51_PAD_GPIO1_3__PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1538 | #define MX51_PAD_GPIO1_3__PWM2_PWMO (_MX51_PAD_GPIO1_3__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1539 | #define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ (_MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1540 | #define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B (_MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1541 | #define MX51_PAD_GPIO1_4__DISP2_EXT_CLK (_MX51_PAD_GPIO1_4__DISP2_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1542 | #define MX51_PAD_GPIO1_4__EIM_RDY (_MX51_PAD_GPIO1_4__EIM_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1543 | #define MX51_PAD_GPIO1_4__GPIO1_4 (_MX51_PAD_GPIO1_4__GPIO1_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1544 | #define MX51_PAD_GPIO1_4__WDOG1_WDOG_B (_MX51_PAD_GPIO1_4__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1545 | #define MX51_PAD_GPIO1_5__CSI2_MCLK (_MX51_PAD_GPIO1_5__CSI2_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1546 | #define MX51_PAD_GPIO1_5__DISP2_PIN16 (_MX51_PAD_GPIO1_5__DISP2_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1547 | #define MX51_PAD_GPIO1_5__GPIO1_5 (_MX51_PAD_GPIO1_5__GPIO1_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1548 | #define MX51_PAD_GPIO1_5__WDOG2_WDOG_B (_MX51_PAD_GPIO1_5__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1549 | #define MX51_PAD_GPIO1_6__DISP2_PIN17 (_MX51_PAD_GPIO1_6__DISP2_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1550 | #define MX51_PAD_GPIO1_6__GPIO1_6 (_MX51_PAD_GPIO1_6__GPIO1_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1551 | #define MX51_PAD_GPIO1_6__REF_EN_B (_MX51_PAD_GPIO1_6__REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1552 | #define MX51_PAD_GPIO1_7__CCM_OUT_0 (_MX51_PAD_GPIO1_7__CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1553 | #define MX51_PAD_GPIO1_7__GPIO1_7 (_MX51_PAD_GPIO1_7__GPIO1_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1554 | #define MX51_PAD_GPIO1_7__SD2_WP (_MX51_PAD_GPIO1_7__SD2_WP | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL)) | ||
| 1555 | #define MX51_PAD_GPIO1_7__SPDIF_OUT1 (_MX51_PAD_GPIO1_7__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1556 | #define MX51_PAD_GPIO1_8__CSI2_DATA_EN (_MX51_PAD_GPIO1_8__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1557 | #define MX51_PAD_GPIO1_8__GPIO1_8 (_MX51_PAD_GPIO1_8__GPIO1_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1558 | #define MX51_PAD_GPIO1_8__SD2_CD (_MX51_PAD_GPIO1_8__SD2_CD | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL)) | ||
| 1559 | #define MX51_PAD_GPIO1_8__USBH3_PWR (_MX51_PAD_GPIO1_8__USBH3_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1560 | #define MX51_PAD_GPIO1_9__CCM_OUT_1 (_MX51_PAD_GPIO1_9__CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1561 | #define MX51_PAD_GPIO1_9__DISP2_D1_CS (_MX51_PAD_GPIO1_9__DISP2_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1562 | #define MX51_PAD_GPIO1_9__DISP2_SER_CS (_MX51_PAD_GPIO1_9__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1563 | #define MX51_PAD_GPIO1_9__GPIO1_9 (_MX51_PAD_GPIO1_9__GPIO1_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1564 | #define MX51_PAD_GPIO1_9__SD2_LCTL (_MX51_PAD_GPIO1_9__SD2_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 1565 | #define MX51_PAD_GPIO1_9__USBH3_OC (_MX51_PAD_GPIO1_9__USBH3_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) | ||
| 386 | 1566 | ||
| 387 | #endif /* __MACH_IOMUX_MX51_H__ */ | 1567 | #endif /* __MACH_IOMUX_MX51_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h new file mode 100644 index 000000000000..5deee019c29e --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h | |||
| @@ -0,0 +1,323 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License along | ||
| 15 | * with this program; if not, write to the Free Software Foundation, Inc.. | ||
| 16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef __MACH_IOMUX_MX53_H__ | ||
| 20 | #define __MACH_IOMUX_MX53_H__ | ||
| 21 | |||
| 22 | #include <mach/iomux-v3.h> | ||
| 23 | |||
| 24 | /* | ||
| 25 | * various IOMUX alternate output functions (1-7) | ||
| 26 | */ | ||
| 27 | typedef enum iomux_config { | ||
| 28 | IOMUX_CONFIG_ALT0, | ||
| 29 | IOMUX_CONFIG_ALT1, | ||
| 30 | IOMUX_CONFIG_ALT2, | ||
| 31 | IOMUX_CONFIG_ALT3, | ||
| 32 | IOMUX_CONFIG_ALT4, | ||
| 33 | IOMUX_CONFIG_ALT5, | ||
| 34 | IOMUX_CONFIG_ALT6, | ||
| 35 | IOMUX_CONFIG_ALT7, | ||
| 36 | IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */ | ||
| 37 | IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */ | ||
| 38 | } iomux_pin_cfg_t; | ||
| 39 | |||
| 40 | /* These 2 defines are for pins that may not have a mux register, but could | ||
| 41 | * have a pad setting register, and vice-versa. */ | ||
| 42 | #define NON_MUX_I 0x00 | ||
| 43 | #define NON_PAD_I 0x00 | ||
| 44 | |||
| 45 | #define MX53_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ | ||
| 46 | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS) | ||
| 47 | /* UART1 */ | ||
| 48 | #define MX53_PAD_CSI0_D10__UART1_TXD IOMUX_PAD(0x414, 0xE8, 2, 0x0, 0, MX53_UART_PAD_CTRL) | ||
| 49 | #define MX53_PAD_CSI0_D11__UART1_RXD IOMUX_PAD(0x418, 0xEC, 2, 0x878, 1, MX53_UART_PAD_CTRL) | ||
| 50 | #define MX53_PAD_ATA_DIOW__UART1_TXD IOMUX_PAD(0x5F0, 0x270, 3, 0x0, 0, MX53_UART_PAD_CTRL) | ||
| 51 | #define MX53_PAD_ATA_DMACK__UART1_RXD IOMUX_PAD(0x5F4, 0x274, 3, 0x880, 3, MX53_UART_PAD_CTRL) | ||
| 52 | |||
| 53 | /* UART2 */ | ||
| 54 | #define MX53_PAD_ATA_BUFFER_EN__UART2_RXD IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL) | ||
| 55 | #define MX53_PAD_ATA_DMARQ__UART2_TXD IOMUX_PAD(0x5F8, 0x278, 3, 0x0, 0, MX53_UART_PAD_CTRL) | ||
| 56 | #define MX53_PAD_ATA_DIOR__UART2_RTS IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL) | ||
| 57 | #define MX53_PAD_ATA_INTRQ__UART2_CTS IOMUX_PAD(0x600, 0x280, 3, 0x0, 0, MX53_UART_PAD_CTRL) | ||
| 58 | |||
| 59 | /* UART3 */ | ||
| 60 | #define MX53_PAD_ATA_CS_0__UART3_TXD IOMUX_PAD(0x61C, 0x29C, 4, 0x0, 0, MX53_UART_PAD_CTRL) | ||
| 61 | #define MX53_PAD_ATA_CS_1__UART3_RXD IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL) | ||
| 62 | #define MX53_PAD_ATA_DA_1__UART3_CTS IOMUX_PAD(0x614, 0x294, 4, 0x0, 0, MX53_UART_PAD_CTRL) | ||
| 63 | #define MX53_PAD_ATA_DA_2__UART3_RTS IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL) | ||
| 64 | |||
| 65 | #define MX53_PAD_GPIO_19__GPIO_4_5 IOMUX_PAD(0x348, 0x20,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 66 | #define MX53_PAD_KEY_COL0__GPIO_4_6 IOMUX_PAD(0x34C, 0x24,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 67 | #define MX53_PAD_KEY_ROW0__GPIO_4_7 IOMUX_PAD(0x350, 0x28,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 68 | #define MX53_PAD_KEY_COL1__GPIO_4_8 IOMUX_PAD(0x354, 0x2C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 69 | #define MX53_PAD_KEY_ROW1__GPIO_4_9 IOMUX_PAD(0x358, 0x30,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 70 | #define MX53_PAD_KEY_COL2__GPIO_4_10 IOMUX_PAD(0x35C, 0x34,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 71 | #define MX53_PAD_KEY_ROW2__GPIO_4_11 IOMUX_PAD(0x360, 0x38,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 72 | #define MX53_PAD_KEY_COL3__GPIO_4_12 IOMUX_PAD(0x364, 0x3C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 73 | #define MX53_PAD_KEY_ROW3__GPIO_4_13 IOMUX_PAD(0x368, 0x40,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 74 | #define MX53_PAD_KEY_COL4__GPIO_4_14 IOMUX_PAD(0x36C, 0x44,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 75 | #define MX53_PAD_KEY_ROW4__GPIO_4_15 IOMUX_PAD(0x370, 0x48,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 76 | #define MX53_PAD_NVCC_KEYPAD__NVCC_KEYPAD IOMUX_PAD(0x374, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 77 | #define MX53_PAD_DI0_DISP_CLK__GPIO_4_16 IOMUX_PAD(0x378, 0x4C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 78 | #define MX53_PAD_DI0_PIN15__GPIO_4_17 IOMUX_PAD(0x37C, 0x50,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 79 | #define MX53_PAD_DI0_PIN2__GPIO_4_18 IOMUX_PAD(0x380, 0x54,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 80 | #define MX53_PAD_DI0_PIN3__GPIO_4_19 IOMUX_PAD(0x384, 0x58,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 81 | #define MX53_PAD_DI0_PIN4__GPIO_4_20 IOMUX_PAD(0x388, 0x5C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 82 | #define MX53_PAD_DISP0_DAT0__GPIO_4_21 IOMUX_PAD(0x38C, 0x60,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 83 | #define MX53_PAD_DISP0_DAT1__GPIO_4_22 IOMUX_PAD(0x390, 0x64,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 84 | #define MX53_PAD_DISP0_DAT2__GPIO_4_23 IOMUX_PAD(0x394, 0x68,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 85 | #define MX53_PAD_DISP0_DAT3__GPIO_4_24 IOMUX_PAD(0x398, 0x6C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 86 | #define MX53_PAD_DISP0_DAT4__GPIO_4_25 IOMUX_PAD(0x39C, 0x70,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 87 | #define MX53_PAD_DISP0_DAT5__GPIO_4_26 IOMUX_PAD(0x3A0, 0x74,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 88 | #define MX53_PAD_DISP0_DAT6__GPIO_4_27 IOMUX_PAD(0x3A4, 0x78,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 89 | #define MX53_PAD_DISP0_DAT7__GPIO_4_28 IOMUX_PAD(0x3A8, 0x7C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 90 | #define MX53_PAD_DISP0_DAT8__GPIO_4_29 IOMUX_PAD(0x3AC, 0x80,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 91 | #define MX53_PAD_DISP0_DAT9__GPIO_4_30 IOMUX_PAD(0x3B0, 0x84,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 92 | #define MX53_PAD_DISP0_DAT10__GPIO_4_31 IOMUX_PAD(0x3B4, 0x88,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 93 | #define MX53_PAD_DISP0_DAT11__GPIO_5_5 IOMUX_PAD(0x3B8, 0x8C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 94 | #define MX53_PAD_DISP0_DAT12__GPIO_5_6 IOMUX_PAD(0x3BC, 0x90,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 95 | #define MX53_PAD_DISP0_DAT13__GPIO_5_7 IOMUX_PAD(0x3C0, 0x94,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 96 | #define MX53_PAD_DISP0_DAT14__GPIO_5_8 IOMUX_PAD(0x3C4, 0x98,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 97 | #define MX53_PAD_DISP0_DAT15__GPIO_5_9 IOMUX_PAD(0x3C8, 0x9C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 98 | #define MX53_PAD_DISP0_DAT16__GPIO_5_10 IOMUX_PAD(0x3CC, 0xA0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 99 | #define MX53_PAD_DISP0_DAT17__GPIO_5_11 IOMUX_PAD(0x3D0, 0xA4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 100 | #define MX53_PAD_DISP0_DAT18__GPIO_5_12 IOMUX_PAD(0x3D4, 0xA8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 101 | #define MX53_PAD_DISP0_DAT19__GPIO_5_13 IOMUX_PAD(0x3D8, 0xAC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 102 | #define MX53_PAD_DISP0_DAT20__GPIO_5_14 IOMUX_PAD(0x3DC, 0xB0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 103 | #define MX53_PAD_DISP0_DAT21__GPIO_5_15 IOMUX_PAD(0x3E0, 0xB4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 104 | #define MX53_PAD_DISP0_DAT22__GPIO_5_16 IOMUX_PAD(0x3E4, 0xB8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 105 | #define MX53_PAD_DISP0_DAT23__GPIO_5_17 IOMUX_PAD(0x3E8, 0xBC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 106 | #define MX53_PAD_CSI0_PIXCLK__GPIO_5_18 IOMUX_PAD(0x3EC, 0xC0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 107 | #define MX53_PAD_CSI0_MCLK__GPIO_5_19 IOMUX_PAD(0x3F0, 0xC4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 108 | #define MX53_PAD_CSI0_DATA_EN__GPIO_5_20 IOMUX_PAD(0x3F4, 0xC8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 109 | #define MX53_PAD_CSI0_VSYNC__GPIO_5_21 IOMUX_PAD(0x3F8, 0xCC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 110 | #define MX53_PAD_CSI0_D4__GPIO_5_22 IOMUX_PAD(0x3FC, 0xD0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 111 | #define MX53_PAD_CSI0_D5__GPIO_5_23 IOMUX_PAD(0x400, 0xD4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 112 | #define MX53_PAD_CSI0_D6__GPIO_5_24 IOMUX_PAD(0x404, 0xD8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 113 | #define MX53_PAD_CSI0_D7__GPIO_5_25 IOMUX_PAD(0x408, 0xDC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 114 | #define MX53_PAD_CSI0_D8__GPIO_5_26 IOMUX_PAD(0x40C, 0xE0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 115 | #define MX53_PAD_CSI0_D9__GPIO_5_27 IOMUX_PAD(0x410, 0xE4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 116 | #define MX53_PAD_CSI0_D10__GPIO_5_28 IOMUX_PAD(0x414, 0xE8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 117 | #define MX53_PAD_CSI0_D11__GPIO_5_29 IOMUX_PAD(0x418, 0xEC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 118 | #define MX53_PAD_CSI0_D12__GPIO_5_30 IOMUX_PAD(0x41C, 0xF0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 119 | #define MX53_PAD_CSI0_D13__GPIO_5_31 IOMUX_PAD(0x420, 0xF4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 120 | #define MX53_PAD_CSI0_D14__GPIO_6_0 IOMUX_PAD(0x424, 0xF8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 121 | #define MX53_PAD_CSI0_D15__GPIO_6_1 IOMUX_PAD(0x428, 0xFC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 122 | #define MX53_PAD_CSI0_D16__GPIO_6_2 IOMUX_PAD(0x42C, 0x100,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 123 | #define MX53_PAD_CSI0_D17__GPIO_6_3 IOMUX_PAD(0x430, 0x104,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 124 | #define MX53_PAD_CSI0_D18__GPIO_6_4 IOMUX_PAD(0x434, 0x108,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 125 | #define MX53_PAD_CSI0_D19__GPIO_6_5 IOMUX_PAD(0x438, 0x10C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 126 | #define MX53_PAD_NVCC_CSI0__NVCC_CSI0 IOMUX_PAD(0x43C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 127 | #define MX53_PAD_JTAG_TMS__JTAG_TMS IOMUX_PAD(0x440, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 128 | #define MX53_PAD_JTAG_MOD__JTAG_MOD IOMUX_PAD(0x444, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 129 | #define MX53_PAD_JTAG_TRSTB__JTAG_TRSTB IOMUX_PAD(0x448, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 130 | #define MX53_PAD_JTAG_TDI__JTAG_TDI IOMUX_PAD(0x44C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 131 | #define MX53_PAD_JTAG_TCK__JTAG_TCK IOMUX_PAD(0x450, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 132 | #define MX53_PAD_JTAG_TDO__JTAG_TDO IOMUX_PAD(0x454, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 133 | #define MX53_PAD_EIM_A25__GPIO_5_2 IOMUX_PAD(0x458, 0x110,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 134 | #define MX53_PAD_EIM_EB2__GPIO_2_30 IOMUX_PAD(0x45C, 0x114,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 135 | #define MX53_PAD_EIM_D16__GPIO_3_16 IOMUX_PAD(0x460, 0x118,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 136 | #define MX53_PAD_EIM_D17__GPIO_3_17 IOMUX_PAD(0x464, 0x11C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 137 | #define MX53_PAD_EIM_D18__GPIO_3_18 IOMUX_PAD(0x468, 0x120,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 138 | #define MX53_PAD_EIM_D19__GPIO_3_19 IOMUX_PAD(0x46C, 0x124,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 139 | #define MX53_PAD_EIM_D20__GPIO_3_20 IOMUX_PAD(0x470, 0x128,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 140 | #define MX53_PAD_EIM_D21__GPIO_3_21 IOMUX_PAD(0x474, 0x12C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 141 | #define MX53_PAD_EIM_D22__GPIO_3_22 IOMUX_PAD(0x478, 0x130,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 142 | #define MX53_PAD_EIM_D23__GPIO_3_23 IOMUX_PAD(0x47C, 0x134,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 143 | #define MX53_PAD_EIM_EB3__GPIO_2_31 IOMUX_PAD(0x480, 0x138,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 144 | #define MX53_PAD_EIM_D24__GPIO_3_24 IOMUX_PAD(0x484, 0x13C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 145 | #define MX53_PAD_EIM_D25__GPIO_3_25 IOMUX_PAD(0x488, 0x140,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 146 | #define MX53_PAD_EIM_D26__GPIO_3_26 IOMUX_PAD(0x48C, 0x144,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 147 | #define MX53_PAD_EIM_D27__GPIO_3_27 IOMUX_PAD(0x490, 0x148,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 148 | #define MX53_PAD_EIM_D28__GPIO_3_28 IOMUX_PAD(0x494, 0x14C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 149 | #define MX53_PAD_EIM_D29__GPIO_3_29 IOMUX_PAD(0x498, 0x150,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 150 | #define MX53_PAD_EIM_D30__GPIO_3_30 IOMUX_PAD(0x49C, 0x154,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 151 | #define MX53_PAD_EIM_D31__GPIO_3_31 IOMUX_PAD(0x4A0, 0x158,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 152 | #define MX53_PAD_NVCC_EIM1__NVCC_EIM1 IOMUX_PAD(0x4A4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 153 | #define MX53_PAD_EIM_A24__GPIO_5_4 IOMUX_PAD(0x4A8, 0x15C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 154 | #define MX53_PAD_EIM_A23__GPIO_6_6 IOMUX_PAD(0x4AC, 0x160,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 155 | #define MX53_PAD_EIM_A22__GPIO_2_16 IOMUX_PAD(0x4B0, 0x164,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 156 | #define MX53_PAD_EIM_A21__GPIO_2_17 IOMUX_PAD(0x4B4, 0x168,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 157 | #define MX53_PAD_EIM_A20__GPIO_2_18 IOMUX_PAD(0x4B8, 0x16C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 158 | #define MX53_PAD_EIM_A19__GPIO_2_19 IOMUX_PAD(0x4BC, 0x170,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 159 | #define MX53_PAD_EIM_A18__GPIO_2_20 IOMUX_PAD(0x4C0, 0x174,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 160 | #define MX53_PAD_EIM_A17__GPIO_2_21 IOMUX_PAD(0x4C4, 0x178,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 161 | #define MX53_PAD_EIM_A16__GPIO_2_22 IOMUX_PAD(0x4C8, 0x17C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 162 | #define MX53_PAD_EIM_CS0__GPIO_2_23 IOMUX_PAD(0x4CC, 0x180,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 163 | #define MX53_PAD_EIM_CS1__GPIO_2_24 IOMUX_PAD(0x4D0, 0x184,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 164 | #define MX53_PAD_EIM_OE__GPIO_2_25 IOMUX_PAD(0x4D4, 0x188,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 165 | #define MX53_PAD_EIM_RW__GPIO_2_26 IOMUX_PAD(0x4D8, 0x18C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 166 | #define MX53_PAD_EIM_LBA__GPIO_2_27 IOMUX_PAD(0x4DC, 0x190,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 167 | #define MX53_PAD_NVCC_EIM4__NVCC_EIM4 IOMUX_PAD(0x4E0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 168 | #define MX53_PAD_EIM_EB0__GPIO_2_28 IOMUX_PAD(0x4E4, 0x194,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 169 | #define MX53_PAD_EIM_EB1__GPIO_2_29 IOMUX_PAD(0x4E8, 0x198,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 170 | #define MX53_PAD_EIM_DA0__GPIO_3_0 IOMUX_PAD(0x4EC, 0x19C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 171 | #define MX53_PAD_EIM_DA1__GPIO_3_1 IOMUX_PAD(0x4F0, 0x1A0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 172 | #define MX53_PAD_EIM_DA2__GPIO_3_2 IOMUX_PAD(0x4F4, 0x1A4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 173 | #define MX53_PAD_EIM_DA3__GPIO_3_3 IOMUX_PAD(0x4F8, 0x1A8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 174 | #define MX53_PAD_EIM_DA4__GPIO_3_4 IOMUX_PAD(0x4FC, 0x1AC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 175 | #define MX53_PAD_EIM_DA5__GPIO_3_5 IOMUX_PAD(0x500, 0x1B0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 176 | #define MX53_PAD_EIM_DA6__GPIO_3_6 IOMUX_PAD(0x504, 0x1B4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 177 | #define MX53_PAD_EIM_DA7__GPIO_3_7 IOMUX_PAD(0x508, 0x1B8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 178 | #define MX53_PAD_EIM_DA8__GPIO_3_8 IOMUX_PAD(0x50C, 0x1BC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 179 | #define MX53_PAD_EIM_DA9__GPIO_3_9 IOMUX_PAD(0x510, 0x1C0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 180 | #define MX53_PAD_EIM_DA10__GPIO_3_10 IOMUX_PAD(0x514, 0x1C4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 181 | #define MX53_PAD_EIM_DA11__GPIO_3_11 IOMUX_PAD(0x518, 0x1C8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 182 | #define MX53_PAD_EIM_DA12__GPIO_3_12 IOMUX_PAD(0x51C, 0x1CC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 183 | #define MX53_PAD_EIM_DA13__GPIO_3_13 IOMUX_PAD(0x520, 0x1D0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 184 | #define MX53_PAD_EIM_DA14__GPIO_3_14 IOMUX_PAD(0x524, 0x1D4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 185 | #define MX53_PAD_EIM_DA15__GPIO_3_15 IOMUX_PAD(0x528, 0x1D8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 186 | #define MX53_PAD_NANDF_WE_B__GPIO_6_12 IOMUX_PAD(0x52C, 0x1DC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 187 | #define MX53_PAD_NANDF_RE_B__GPIO_6_13 IOMUX_PAD(0x530, 0x1E0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 188 | #define MX53_PAD_EIM_WAIT__GPIO_5_0 IOMUX_PAD(0x534, 0x1E4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 189 | #define MX53_PAD_EIM_BCLK__EIM_BCLK IOMUX_PAD(0x538, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 190 | #define MX53_PAD_NVCC_EIM7__NVCC_EIM7 IOMUX_PAD(0x53C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 191 | #define MX53_PAD_LVDS1_TX3_P__GPIO_6_22 IOMUX_PAD(NON_PAD_I, 0x1EC, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 192 | #define MX53_PAD_LVDS1_TX2_P__GPIO_6_24 IOMUX_PAD(NON_PAD_I, 0x1F0, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 193 | #define MX53_PAD_LVDS1_CLK_P__GPIO_6_26 IOMUX_PAD(NON_PAD_I, 0x1F4, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 194 | #define MX53_PAD_LVDS1_TX1_P__GPIO_6_28 IOMUX_PAD(NON_PAD_I, 0x1F8, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 195 | #define MX53_PAD_LVDS1_TX0_P__GPIO_6_30 IOMUX_PAD(NON_PAD_I, 0x1FC, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 196 | #define MX53_PAD_LVDS0_TX3_P__GPIO_7_22 IOMUX_PAD(NON_PAD_I, 0x200, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 197 | #define MX53_PAD_LVDS0_CLK_P__GPIO_7_24 IOMUX_PAD(NON_PAD_I, 0x204, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 198 | #define MX53_PAD_LVDS0_TX2_P__GPIO_7_26 IOMUX_PAD(NON_PAD_I, 0x208, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 199 | #define MX53_PAD_LVDS0_TX1_P__GPIO_7_28 IOMUX_PAD(NON_PAD_I, 0x20C, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 200 | #define MX53_PAD_LVDS0_TX0_P__GPIO_7_30 IOMUX_PAD(NON_PAD_I, 0x210, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 201 | #define MX53_PAD_GPIO_10__GPIO_4_0 IOMUX_PAD(0x540, 0x214, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 202 | #define MX53_PAD_GPIO_11__GPIO_4_1 IOMUX_PAD(0x544, 0x218, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 203 | #define MX53_PAD_GPIO_12__GPIO_4_2 IOMUX_PAD(0x548, 0x21C, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 204 | #define MX53_PAD_GPIO_13__GPIO_4_3 IOMUX_PAD(0x54C, 0x220, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 205 | #define MX53_PAD_GPIO_14__GPIO_4_4 IOMUX_PAD(0x550, 0x224, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 206 | #define MX53_PAD_DRAM_DQM3__DRAM_DQM3 IOMUX_PAD(0x554, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 207 | #define MX53_PAD_DRAM_SDQS3__DRAM_SDQS3 IOMUX_PAD(0x558, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 208 | #define MX53_PAD_DRAM_SDCKE1__DRAM_SDCKE1 IOMUX_PAD(0x55C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 209 | #define MX53_PAD_DRAM_DQM2__DRAM_DQM2 IOMUX_PAD(0x560, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 210 | #define MX53_PAD_DRAM_SDODT1__DRAM_SDODT1 IOMUX_PAD(0x564, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 211 | #define MX53_PAD_DRAM_SDQS2__DRAM_SDQS2 IOMUX_PAD(0x568, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 212 | #define MX53_PAD_DRAM_RESET__DRAM_RESET IOMUX_PAD(0x56C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 213 | #define MX53_PAD_DRAM_SDCLK1__DRAM_SDCLK1 IOMUX_PAD(0x570, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 214 | #define MX53_PAD_DRAM_CAS__DRAM_CAS IOMUX_PAD(0x574, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 215 | #define MX53_PAD_DRAM_SDCLK0__DRAM_SDCLK0 IOMUX_PAD(0x578, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 216 | #define MX53_PAD_DRAM_SDQS0__DRAM_SDQS0 IOMUX_PAD(0x57C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 217 | #define MX53_PAD_DRAM_SDODT0__DRAM_SDODT0 IOMUX_PAD(0x580, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 218 | #define MX53_PAD_DRAM_DQM0__DRAM_DQM0 IOMUX_PAD(0x584, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 219 | #define MX53_PAD_DRAM_RAS__DRAM_RAS IOMUX_PAD(0x588, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 220 | #define MX53_PAD_DRAM_SDCKE0__DRAM_SDCKE0 IOMUX_PAD(0x58C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 221 | #define MX53_PAD_DRAM_SDQS1__DRAM_SDQS1 IOMUX_PAD(0x590, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 222 | #define MX53_PAD_DRAM_DQM1__DRAM_DQM1 IOMUX_PAD(0x594, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 223 | #define MX53_PAD_PMIC_ON_REQ__PMIC_ON_REQ IOMUX_PAD(0x598, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 224 | #define MX53_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ IOMUX_PAD(0x59C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 225 | #define MX53_PAD_NANDF_CLE__GPIO_6_7 IOMUX_PAD(0x5A0, 0x228,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 226 | #define MX53_PAD_NANDF_ALE__GPIO_6_8 IOMUX_PAD(0x5A4, 0x22C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 227 | #define MX53_PAD_NANDF_WP_B__GPIO_6_9 IOMUX_PAD(0x5A8, 0x230,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 228 | #define MX53_PAD_NANDF_RB0__GPIO_6_10 IOMUX_PAD(0x5AC, 0x234,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 229 | #define MX53_PAD_NANDF_CS0__GPIO_6_11 IOMUX_PAD(0x5B0, 0x238,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 230 | #define MX53_PAD_NANDF_CS1__GPIO_6_14 IOMUX_PAD(0x5B4, 0x23C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 231 | #define MX53_PAD_NANDF_CS2__GPIO_6_15 IOMUX_PAD(0x5B8, 0x240,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 232 | #define MX53_PAD_NANDF_CS3__GPIO_6_16 IOMUX_PAD(0x5BC, 0x244,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 233 | #define MX53_PAD_NVCC_NANDF__NVCC_NANDF IOMUX_PAD(0x5C0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 234 | #define MX53_PAD_FEC_MDIO__GPIO_1_22 IOMUX_PAD(0x5C4, 0x248,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 235 | #define MX53_PAD_FEC_REF_CLK__GPIO_1_23 IOMUX_PAD(0x5C8, 0x24C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 236 | #define MX53_PAD_FEC_RX_ER__GPIO_1_24 IOMUX_PAD(0x5CC, 0x250,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 237 | #define MX53_PAD_FEC_CRS_DV__GPIO_1_25 IOMUX_PAD(0x5D0, 0x254,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 238 | #define MX53_PAD_FEC_RXD1__GPIO_1_26 IOMUX_PAD(0x5D4, 0x258,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 239 | #define MX53_PAD_FEC_RXD0__GPIO_1_27 IOMUX_PAD(0x5D8, 0x25C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 240 | #define MX53_PAD_FEC_TX_EN__GPIO_1_28 IOMUX_PAD(0x5DC, 0x260,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 241 | #define MX53_PAD_FEC_TXD1__GPIO_1_29 IOMUX_PAD(0x5E0, 0x264,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 242 | #define MX53_PAD_FEC_TXD0__GPIO_1_30 IOMUX_PAD(0x5E4, 0x268,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 243 | #define MX53_PAD_FEC_MDC__GPIO_1_31 IOMUX_PAD(0x5E8, 0x26C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 244 | #define MX53_PAD_NVCC_FEC__NVCC_FEC IOMUX_PAD(0x5EC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 245 | #define MX53_PAD_ATA_DIOW__GPIO_6_17 IOMUX_PAD(0x5F0, 0x270,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 246 | #define MX53_PAD_ATA_DMACK__GPIO_6_18 IOMUX_PAD(0x5F4, 0x274,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 247 | #define MX53_PAD_ATA_DMARQ__GPIO_7_0 IOMUX_PAD(0x5F8, 0x278,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 248 | #define MX53_PAD_ATA_BUFFER_EN__GPIO_7_1 IOMUX_PAD(0x5FC, 0x27C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 249 | #define MX53_PAD_ATA_INTRQ__GPIO_7_2 IOMUX_PAD(0x600, 0x280,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 250 | #define MX53_PAD_ATA_DIOR__GPIO_7_3 IOMUX_PAD(0x604, 0x284,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 251 | #define MX53_PAD_ATA_RESET_B__GPIO_7_4 IOMUX_PAD(0x608, 0x288,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 252 | #define MX53_PAD_ATA_IORDY__GPIO_7_5 IOMUX_PAD(0x60C, 0x28C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 253 | #define MX53_PAD_ATA_DA_0__GPIO_7_6 IOMUX_PAD(0x610, 0x290,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 254 | #define MX53_PAD_ATA_DA_1__GPIO_7_7 IOMUX_PAD(0x614, 0x294,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 255 | #define MX53_PAD_ATA_DA_2__GPIO_7_8 IOMUX_PAD(0x618, 0x298,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 256 | #define MX53_PAD_ATA_CS_0__GPIO_7_9 IOMUX_PAD(0x61C, 0x29C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 257 | #define MX53_PAD_ATA_CS_1__GPIO_7_10 IOMUX_PAD(0x620, 0x2A0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 258 | #define MX53_PAD_NVCC_ATA2__NVCC_ATA2 IOMUX_PAD(0x624, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 259 | #define MX53_PAD_ATA_DATA0__GPIO_2_0 IOMUX_PAD(0x628, 0x2A4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 260 | #define MX53_PAD_ATA_DATA1__GPIO_2_1 IOMUX_PAD(0x62C, 0x2A8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 261 | #define MX53_PAD_ATA_DATA2__GPIO_2_2 IOMUX_PAD(0x630, 0x2AC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 262 | #define MX53_PAD_ATA_DATA3__GPIO_2_3 IOMUX_PAD(0x634, 0x2B0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 263 | #define MX53_PAD_ATA_DATA4__GPIO_2_4 IOMUX_PAD(0x638, 0x2B4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 264 | #define MX53_PAD_ATA_DATA5__GPIO_2_5 IOMUX_PAD(0x63C, 0x2B8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 265 | #define MX53_PAD_ATA_DATA6__GPIO_2_6 IOMUX_PAD(0x640, 0x2BC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 266 | #define MX53_PAD_ATA_DATA7__GPIO_2_7 IOMUX_PAD(0x644, 0x2C0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 267 | #define MX53_PAD_ATA_DATA8__GPIO_2_8 IOMUX_PAD(0x648, 0x2C4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 268 | #define MX53_PAD_ATA_DATA9__GPIO_2_9 IOMUX_PAD(0x64C, 0x2C8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 269 | #define MX53_PAD_ATA_DATA10__GPIO_2_10 IOMUX_PAD(0x650, 0x2CC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 270 | #define MX53_PAD_ATA_DATA11__GPIO_2_11 IOMUX_PAD(0x654, 0x2D0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 271 | #define MX53_PAD_ATA_DATA12__GPIO_2_12 IOMUX_PAD(0x658, 0x2D4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 272 | #define MX53_PAD_ATA_DATA13__GPIO_2_13 IOMUX_PAD(0x65C, 0x2D8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 273 | #define MX53_PAD_ATA_DATA14__GPIO_2_14 IOMUX_PAD(0x660, 0x2DC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 274 | #define MX53_PAD_ATA_DATA15__GPIO_2_15 IOMUX_PAD(0x664, 0x2E0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 275 | #define MX53_PAD_NVCC_ATA0__NVCC_ATA0 IOMUX_PAD(0x668, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 276 | #define MX53_PAD_SD1_DATA0__GPIO_1_16 IOMUX_PAD(0x66C, 0x2E4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 277 | #define MX53_PAD_SD1_DATA1__GPIO_1_17 IOMUX_PAD(0x670, 0x2E8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 278 | #define MX53_PAD_SD1_CMD__GPIO_1_18 IOMUX_PAD(0x674, 0x2EC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 279 | #define MX53_PAD_SD1_DATA2__GPIO_1_19 IOMUX_PAD(0x678, 0x2F0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 280 | #define MX53_PAD_SD1_CLK__GPIO_1_20 IOMUX_PAD(0x67C, 0x2F4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 281 | #define MX53_PAD_SD1_DATA3__GPIO_1_21 IOMUX_PAD(0x680, 0x2F8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 282 | #define MX53_PAD_NVCC_SD1__NVCC_SD1 IOMUX_PAD(0x684, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 283 | #define MX53_PAD_SD2_CLK__GPIO_1_10 IOMUX_PAD(0x688, 0x2FC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 284 | #define MX53_PAD_SD2_CMD__GPIO_1_11 IOMUX_PAD(0x68C, 0x300,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 285 | #define MX53_PAD_SD2_DATA3__GPIO_1_12 IOMUX_PAD(0x690, 0x304,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 286 | #define MX53_PAD_SD2_DATA2__GPIO_1_13 IOMUX_PAD(0x694, 0x308,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 287 | #define MX53_PAD_SD2_DATA1__GPIO_1_14 IOMUX_PAD(0x698, 0x30C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 288 | #define MX53_PAD_SD2_DATA0__GPIO_1_15 IOMUX_PAD(0x69C, 0x310,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 289 | #define MX53_PAD_NVCC_SD2__NVCC_SD2 IOMUX_PAD(0x6A0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 290 | #define MX53_PAD_GPIO_0__GPIO_1_0 IOMUX_PAD(0x6A4, 0x314,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 291 | #define MX53_PAD_GPIO_1__GPIO_1_1 IOMUX_PAD(0x6A8, 0x318,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 292 | #define MX53_PAD_GPIO_9__GPIO_1_9 IOMUX_PAD(0x6AC, 0x31C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 293 | #define MX53_PAD_GPIO_3__GPIO_1_3 IOMUX_PAD(0x6B0, 0x320,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 294 | #define MX53_PAD_GPIO_6__GPIO_1_6 IOMUX_PAD(0x6B4, 0x324,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 295 | #define MX53_PAD_GPIO_2__GPIO_1_2 IOMUX_PAD(0x6B8, 0x328,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 296 | #define MX53_PAD_GPIO_4__GPIO_1_4 IOMUX_PAD(0x6BC, 0x32C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 297 | #define MX53_PAD_GPIO_5__GPIO_1_5 IOMUX_PAD(0x6C0, 0x330,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 298 | #define MX53_PAD_GPIO_7__GPIO_1_7 IOMUX_PAD(0x6C4, 0x334,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 299 | #define MX53_PAD_GPIO_8__GPIO_1_8 IOMUX_PAD(0x6C8, 0x338,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 300 | #define MX53_PAD_GPIO_16__GPIO_7_11 IOMUX_PAD(0x6CC, 0x33C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 301 | #define MX53_PAD_GPIO_17__GPIO_7_12 IOMUX_PAD(0x6D0, 0x340,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 302 | #define MX53_PAD_GPIO_18__GPIO_7_13 IOMUX_PAD(0x6D4, 0x344,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) | ||
| 303 | #define MX53_PAD_NVCC_GPIO__NVCC_GPIO IOMUX_PAD(0x6D8, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 304 | #define MX53_PAD_POR_B__POR_B IOMUX_PAD(0x6DC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 305 | #define MX53_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x6E0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 306 | #define MX53_PAD_RESET_IN_B__RESET_IN_B IOMUX_PAD(0x6E4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 307 | #define MX53_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x6E8, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 308 | #define MX53_PAD_TEST_MODE__TEST_MODE IOMUX_PAD(0x6EC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 309 | #define MX53_PAD_GRP_ADDDS__GRP_ADDDS IOMUX_PAD(0x6F0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 310 | #define MX53_PAD_GRP_DDRMODE_CTL__GRP_DDRMODE_CTL IOMUX_PAD(0x6F4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 311 | #define MX53_PAD_GRP_DDRPKE__GRP_DDRPKE IOMUX_PAD(0x6FC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 312 | #define MX53_PAD_GRP_DDRPK__GRP_DDRPK IOMUX_PAD(0x708, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 313 | #define MX53_PAD_GRP_TERM_CTL3__GRP_TERM_CTL3 IOMUX_PAD(0x70C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 314 | #define MX53_PAD_GRP_DDRHYS__GRP_DDRHYS IOMUX_PAD(0x710, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 315 | #define MX53_PAD_GRP_DDRMODE__GRP_DDRMODE IOMUX_PAD(0x714, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 316 | #define MX53_PAD_GRP_B0DS__GRP_B0DS IOMUX_PAD(0x718, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 317 | #define MX53_PAD_GRP_B1DS__GRP_B1DS IOMUX_PAD(0x71C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 318 | #define MX53_PAD_GRP_CTLDS__GRP_CTLDS IOMUX_PAD(0x720, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 319 | #define MX53_PAD_GRP_DDR_TYPE__GRP_DDR_TYPE IOMUX_PAD(0x724, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 320 | #define MX53_PAD_GRP_B2DS__GRP_B2DS IOMUX_PAD(0x728, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 321 | #define MX53_PAD_GRP_B3DS__GRP_B3DS IOMUX_PAD(0x72C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) | ||
| 322 | |||
| 323 | #endif /* __MACH_IOMUX_MX53_H__ */ | ||
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h index 0880a4a1aed1..2277b01c855d 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-v3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h | |||
| @@ -42,28 +42,44 @@ | |||
| 42 | * If <padname> or <padmode> refers to a GPIO, it is named | 42 | * If <padname> or <padmode> refers to a GPIO, it is named |
| 43 | * GPIO_<unit>_<num> | 43 | * GPIO_<unit>_<num> |
| 44 | * | 44 | * |
| 45 | */ | 45 | * IOMUX/PAD Bit field definitions |
| 46 | 46 | * | |
| 47 | struct pad_desc { | 47 | * MUX_CTRL_OFS: 0..11 (12) |
| 48 | unsigned mux_ctrl_ofs:12; /* IOMUXC_SW_MUX_CTL_PAD offset */ | 48 | * PAD_CTRL_OFS: 12..23 (12) |
| 49 | unsigned mux_mode:8; | 49 | * SEL_INPUT_OFS: 24..35 (12) |
| 50 | unsigned pad_ctrl_ofs:12; /* IOMUXC_SW_PAD_CTRL offset */ | 50 | * MUX_MODE + SION: 36..40 (5) |
| 51 | #define NO_PAD_CTRL (1 << 16) | 51 | * PAD_CTRL + NO_PAD_CTRL: 41..57 (17) |
| 52 | unsigned pad_ctrl:17; | 52 | * SEL_INP: 58..61 (4) |
| 53 | unsigned select_input_ofs:12; /* IOMUXC_SELECT_INPUT offset */ | 53 | * reserved: 63 (1) |
| 54 | unsigned select_input:3; | 54 | */ |
| 55 | }; | 55 | |
| 56 | 56 | typedef u64 iomux_v3_cfg_t; | |
| 57 | #define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _select_input_ofs, \ | 57 | |
| 58 | _select_input, _pad_ctrl) \ | 58 | #define MUX_CTRL_OFS_SHIFT 0 |
| 59 | { \ | 59 | #define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT) |
| 60 | .mux_ctrl_ofs = _mux_ctrl_ofs, \ | 60 | #define MUX_PAD_CTRL_OFS_SHIFT 12 |
| 61 | .mux_mode = _mux_mode, \ | 61 | #define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_PAD_CTRL_OFS_SHIFT) |
| 62 | .pad_ctrl_ofs = _pad_ctrl_ofs, \ | 62 | #define MUX_SEL_INPUT_OFS_SHIFT 24 |
| 63 | .pad_ctrl = _pad_ctrl, \ | 63 | #define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_SEL_INPUT_OFS_SHIFT) |
| 64 | .select_input_ofs = _select_input_ofs, \ | 64 | |
| 65 | .select_input = _select_input, \ | 65 | #define MUX_MODE_SHIFT 36 |
| 66 | } | 66 | #define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT) |
| 67 | #define MUX_PAD_CTRL_SHIFT 41 | ||
| 68 | #define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x1ffff << MUX_PAD_CTRL_SHIFT) | ||
| 69 | #define NO_PAD_CTRL ((iomux_v3_cfg_t)1 << (MUX_PAD_CTRL_SHIFT + 16)) | ||
| 70 | #define MUX_SEL_INPUT_SHIFT 58 | ||
| 71 | #define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) | ||
| 72 | |||
| 73 | #define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) | ||
| 74 | |||
| 75 | #define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _sel_input_ofs, \ | ||
| 76 | _sel_input, _pad_ctrl) \ | ||
| 77 | (((iomux_v3_cfg_t)(_mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \ | ||
| 78 | ((iomux_v3_cfg_t)(_mux_mode) << MUX_MODE_SHIFT) | \ | ||
| 79 | ((iomux_v3_cfg_t)(_pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \ | ||
| 80 | ((iomux_v3_cfg_t)(_pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \ | ||
| 81 | ((iomux_v3_cfg_t)(_sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT) | \ | ||
| 82 | ((iomux_v3_cfg_t)(_sel_input) << MUX_SEL_INPUT_SHIFT)) | ||
| 67 | 83 | ||
| 68 | /* | 84 | /* |
| 69 | * Use to set PAD control | 85 | * Use to set PAD control |
| @@ -107,13 +123,13 @@ struct pad_desc { | |||
| 107 | /* | 123 | /* |
| 108 | * setups a single pad in the iomuxer | 124 | * setups a single pad in the iomuxer |
| 109 | */ | 125 | */ |
| 110 | int mxc_iomux_v3_setup_pad(struct pad_desc *pad); | 126 | int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad); |
| 111 | 127 | ||
| 112 | /* | 128 | /* |
| 113 | * setups mutliple pads | 129 | * setups mutliple pads |
| 114 | * convenient way to call the above function with tables | 130 | * convenient way to call the above function with tables |
| 115 | */ | 131 | */ |
| 116 | int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count); | 132 | int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count); |
| 117 | 133 | ||
| 118 | /* | 134 | /* |
| 119 | * Initialise the iomux controller | 135 | * Initialise the iomux controller |
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index 86781f7b0c0c..58a49cc83797 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h | |||
| @@ -23,13 +23,17 @@ | |||
| 23 | #define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS | 23 | #define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS |
| 24 | 24 | ||
| 25 | /* these are ordered by size to support multi-SoC kernels */ | 25 | /* these are ordered by size to support multi-SoC kernels */ |
| 26 | #if defined CONFIG_ARCH_MX2 | 26 | #if defined CONFIG_ARCH_MX53 |
| 27 | #define MXC_GPIO_IRQS (32 * 7) | ||
| 28 | #elif defined CONFIG_ARCH_MX2 | ||
| 29 | #define MXC_GPIO_IRQS (32 * 6) | ||
| 30 | #elif defined CONFIG_ARCH_MX50 | ||
| 27 | #define MXC_GPIO_IRQS (32 * 6) | 31 | #define MXC_GPIO_IRQS (32 * 6) |
| 28 | #elif defined CONFIG_ARCH_MX1 | 32 | #elif defined CONFIG_ARCH_MX1 |
| 29 | #define MXC_GPIO_IRQS (32 * 4) | 33 | #define MXC_GPIO_IRQS (32 * 4) |
| 30 | #elif defined CONFIG_ARCH_MX25 | 34 | #elif defined CONFIG_ARCH_MX25 |
| 31 | #define MXC_GPIO_IRQS (32 * 4) | 35 | #define MXC_GPIO_IRQS (32 * 4) |
| 32 | #elif defined CONFIG_ARCH_MX5 | 36 | #elif defined CONFIG_ARCH_MX51 |
| 33 | #define MXC_GPIO_IRQS (32 * 4) | 37 | #define MXC_GPIO_IRQS (32 * 4) |
| 34 | #elif defined CONFIG_ARCH_MXC91231 | 38 | #elif defined CONFIG_ARCH_MXC91231 |
| 35 | #define MXC_GPIO_IRQS (32 * 4) | 39 | #define MXC_GPIO_IRQS (32 * 4) |
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index 564ec9dbc93d..83861408133f 100644 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h | |||
| @@ -16,7 +16,9 @@ | |||
| 16 | #define MX25_PHYS_OFFSET UL(0x80000000) | 16 | #define MX25_PHYS_OFFSET UL(0x80000000) |
| 17 | #define MX27_PHYS_OFFSET UL(0xa0000000) | 17 | #define MX27_PHYS_OFFSET UL(0xa0000000) |
| 18 | #define MX3x_PHYS_OFFSET UL(0x80000000) | 18 | #define MX3x_PHYS_OFFSET UL(0x80000000) |
| 19 | #define MX50_PHYS_OFFSET UL(0x70000000) | ||
| 19 | #define MX51_PHYS_OFFSET UL(0x90000000) | 20 | #define MX51_PHYS_OFFSET UL(0x90000000) |
| 21 | #define MX53_PHYS_OFFSET UL(0x70000000) | ||
| 20 | #define MXC91231_PHYS_OFFSET UL(0x90000000) | 22 | #define MXC91231_PHYS_OFFSET UL(0x90000000) |
| 21 | 23 | ||
| 22 | #if !defined(CONFIG_RUNTIME_PHYS_OFFSET) | 24 | #if !defined(CONFIG_RUNTIME_PHYS_OFFSET) |
| @@ -32,8 +34,12 @@ | |||
| 32 | # define PHYS_OFFSET MX3x_PHYS_OFFSET | 34 | # define PHYS_OFFSET MX3x_PHYS_OFFSET |
| 33 | # elif defined CONFIG_ARCH_MXC91231 | 35 | # elif defined CONFIG_ARCH_MXC91231 |
| 34 | # define PHYS_OFFSET MXC91231_PHYS_OFFSET | 36 | # define PHYS_OFFSET MXC91231_PHYS_OFFSET |
| 35 | # elif defined CONFIG_ARCH_MX5 | 37 | # elif defined CONFIG_ARCH_MX50 |
| 38 | # define PHYS_OFFSET MX50_PHYS_OFFSET | ||
| 39 | # elif defined CONFIG_ARCH_MX51 | ||
| 36 | # define PHYS_OFFSET MX51_PHYS_OFFSET | 40 | # define PHYS_OFFSET MX51_PHYS_OFFSET |
| 41 | # elif defined CONFIG_ARCH_MX53 | ||
| 42 | # define PHYS_OFFSET MX53_PHYS_OFFSET | ||
| 37 | # endif | 43 | # endif |
| 38 | #endif | 44 | #endif |
| 39 | 45 | ||
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h index 641b24618239..75d96214b831 100644 --- a/arch/arm/plat-mxc/include/mach/mx1.h +++ b/arch/arm/plat-mxc/include/mach/mx1.h | |||
| @@ -19,7 +19,6 @@ | |||
| 19 | */ | 19 | */ |
| 20 | #define MX1_IO_BASE_ADDR 0x00200000 | 20 | #define MX1_IO_BASE_ADDR 0x00200000 |
| 21 | #define MX1_IO_SIZE SZ_1M | 21 | #define MX1_IO_SIZE SZ_1M |
| 22 | #define MX1_IO_BASE_ADDR_VIRT VMALLOC_END | ||
| 23 | 22 | ||
| 24 | #define MX1_CS0_PHYS 0x10000000 | 23 | #define MX1_CS0_PHYS 0x10000000 |
| 25 | #define MX1_CS0_SIZE 0x02000000 | 24 | #define MX1_CS0_SIZE 0x02000000 |
| @@ -66,6 +65,10 @@ | |||
| 66 | #define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR) | 65 | #define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR) |
| 67 | #define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR) | 66 | #define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR) |
| 68 | #define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) | 67 | #define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) |
| 68 | #define MX1_GPIO1_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) | ||
| 69 | #define MX1_GPIO2_BASE_ADDR (0x1C100 + MX1_IO_BASE_ADDR) | ||
| 70 | #define MX1_GPIO3_BASE_ADDR (0x1C200 + MX1_IO_BASE_ADDR) | ||
| 71 | #define MX1_GPIO4_BASE_ADDR (0x1C300 + MX1_IO_BASE_ADDR) | ||
| 69 | #define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR) | 72 | #define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR) |
| 70 | #define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR) | 73 | #define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR) |
| 71 | #define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR) | 74 | #define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR) |
| @@ -73,12 +76,12 @@ | |||
| 73 | #define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR) | 76 | #define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR) |
| 74 | 77 | ||
| 75 | /* macro to get at IO space when running virtually */ | 78 | /* macro to get at IO space when running virtually */ |
| 76 | #define MX1_IO_ADDRESS(x) ( \ | 79 | #define MX1_IO_P2V(x) IMX_IO_P2V(x) |
| 77 | IMX_IO_ADDRESS(x, MX1_IO)) | 80 | #define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x)) |
| 78 | 81 | ||
| 79 | /* fixed interrput numbers */ | 82 | /* fixed interrput numbers */ |
| 80 | #define MX1_INT_SOFTINT 0 | 83 | #define MX1_INT_SOFTINT 0 |
| 81 | #define MX1_CSI_INT 6 | 84 | #define MX1_INT_CSI 6 |
| 82 | #define MX1_DSPA_MAC_INT 7 | 85 | #define MX1_DSPA_MAC_INT 7 |
| 83 | #define MX1_DSPA_INT 8 | 86 | #define MX1_DSPA_INT 8 |
| 84 | #define MX1_COMP_INT 9 | 87 | #define MX1_COMP_INT 9 |
| @@ -115,13 +118,13 @@ | |||
| 115 | #define MX1_SSI_RX_INT 44 | 118 | #define MX1_SSI_RX_INT 44 |
| 116 | #define MX1_SSI_RX_ERR_INT 45 | 119 | #define MX1_SSI_RX_ERR_INT 45 |
| 117 | #define MX1_TOUCH_INT 46 | 120 | #define MX1_TOUCH_INT 46 |
| 118 | #define MX1_USBD_INT0 47 | 121 | #define MX1_INT_USBD0 47 |
| 119 | #define MX1_USBD_INT1 48 | 122 | #define MX1_INT_USBD1 48 |
| 120 | #define MX1_USBD_INT2 49 | 123 | #define MX1_INT_USBD2 49 |
| 121 | #define MX1_USBD_INT3 50 | 124 | #define MX1_INT_USBD3 50 |
| 122 | #define MX1_USBD_INT4 51 | 125 | #define MX1_INT_USBD4 51 |
| 123 | #define MX1_USBD_INT5 52 | 126 | #define MX1_INT_USBD5 52 |
| 124 | #define MX1_USBD_INT6 53 | 127 | #define MX1_INT_USBD6 53 |
| 125 | #define MX1_BTSYS_INT 55 | 128 | #define MX1_BTSYS_INT 55 |
| 126 | #define MX1_BTTIM_INT 56 | 129 | #define MX1_BTTIM_INT 56 |
| 127 | #define MX1_BTWUI_INT 57 | 130 | #define MX1_BTWUI_INT 57 |
| @@ -164,134 +167,6 @@ | |||
| 164 | * to not break drivers/usb/gadget/imx_udc. Should go | 167 | * to not break drivers/usb/gadget/imx_udc. Should go |
| 165 | * away after this driver uses the new name. | 168 | * away after this driver uses the new name. |
| 166 | */ | 169 | */ |
| 167 | #define USBD_INT0 MX1_USBD_INT0 | 170 | #define USBD_INT0 MX1_INT_USBD0 |
| 168 | |||
| 169 | #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS | ||
| 170 | /* these should go away */ | ||
| 171 | #define IMX_IO_PHYS MX1_IO_BASE_ADDR | ||
| 172 | #define IMX_IO_SIZE MX1_IO_SIZE | ||
| 173 | #define IMX_IO_BASE MX1_IO_BASE_ADDR_VIRT | ||
| 174 | #define IMX_CS0_PHYS MX1_CS0_PHYS | ||
| 175 | #define IMX_CS0_SIZE MX1_CS0_SIZE | ||
| 176 | #define IMX_CS1_PHYS MX1_CS1_PHYS | ||
| 177 | #define IMX_CS1_SIZE MX1_CS1_SIZE | ||
| 178 | #define IMX_CS2_PHYS MX1_CS2_PHYS | ||
| 179 | #define IMX_CS2_SIZE MX1_CS2_SIZE | ||
| 180 | #define IMX_CS3_PHYS MX1_CS3_PHYS | ||
| 181 | #define IMX_CS3_SIZE MX1_CS3_SIZE | ||
| 182 | #define IMX_CS4_PHYS MX1_CS4_PHYS | ||
| 183 | #define IMX_CS4_SIZE MX1_CS4_SIZE | ||
| 184 | #define IMX_CS5_PHYS MX1_CS5_PHYS | ||
| 185 | #define IMX_CS5_SIZE MX1_CS5_SIZE | ||
| 186 | #define AIPI1_BASE_ADDR MX1_AIPI1_BASE_ADDR | ||
| 187 | #define WDT_BASE_ADDR MX1_WDT_BASE_ADDR | ||
| 188 | #define TIM1_BASE_ADDR MX1_TIM1_BASE_ADDR | ||
| 189 | #define TIM2_BASE_ADDR MX1_TIM2_BASE_ADDR | ||
| 190 | #define RTC_BASE_ADDR MX1_RTC_BASE_ADDR | ||
| 191 | #define LCDC_BASE_ADDR MX1_LCDC_BASE_ADDR | ||
| 192 | #define UART1_BASE_ADDR MX1_UART1_BASE_ADDR | ||
| 193 | #define UART2_BASE_ADDR MX1_UART2_BASE_ADDR | ||
| 194 | #define PWM_BASE_ADDR MX1_PWM_BASE_ADDR | ||
| 195 | #define DMA_BASE_ADDR MX1_DMA_BASE_ADDR | ||
| 196 | #define AIPI2_BASE_ADDR MX1_AIPI2_BASE_ADDR | ||
| 197 | #define SIM_BASE_ADDR MX1_SIM_BASE_ADDR | ||
| 198 | #define USBD_BASE_ADDR MX1_USBD_BASE_ADDR | ||
| 199 | #define SPI1_BASE_ADDR MX1_SPI1_BASE_ADDR | ||
| 200 | #define MMC_BASE_ADDR MX1_MMC_BASE_ADDR | ||
| 201 | #define ASP_BASE_ADDR MX1_ASP_BASE_ADDR | ||
| 202 | #define BTA_BASE_ADDR MX1_BTA_BASE_ADDR | ||
| 203 | #define I2C_BASE_ADDR MX1_I2C_BASE_ADDR | ||
| 204 | #define SSI_BASE_ADDR MX1_SSI_BASE_ADDR | ||
| 205 | #define SPI2_BASE_ADDR MX1_SPI2_BASE_ADDR | ||
| 206 | #define MSHC_BASE_ADDR MX1_MSHC_BASE_ADDR | ||
| 207 | #define CCM_BASE_ADDR MX1_CCM_BASE_ADDR | ||
| 208 | #define SCM_BASE_ADDR MX1_SCM_BASE_ADDR | ||
| 209 | #define GPIO_BASE_ADDR MX1_GPIO_BASE_ADDR | ||
| 210 | #define EIM_BASE_ADDR MX1_EIM_BASE_ADDR | ||
| 211 | #define SDRAMC_BASE_ADDR MX1_SDRAMC_BASE_ADDR | ||
| 212 | #define MMA_BASE_ADDR MX1_MMA_BASE_ADDR | ||
| 213 | #define AVIC_BASE_ADDR MX1_AVIC_BASE_ADDR | ||
| 214 | #define CSI_BASE_ADDR MX1_CSI_BASE_ADDR | ||
| 215 | #define IO_ADDRESS(x) MX1_IO_ADDRESS(x) | ||
| 216 | #define AVIC_IO_ADDRESS(x) IO_ADDRESS(x) | ||
| 217 | #define INT_SOFTINT MX1_INT_SOFTINT | ||
| 218 | #define CSI_INT MX1_CSI_INT | ||
| 219 | #define DSPA_MAC_INT MX1_DSPA_MAC_INT | ||
| 220 | #define DSPA_INT MX1_DSPA_INT | ||
| 221 | #define COMP_INT MX1_COMP_INT | ||
| 222 | #define MSHC_XINT MX1_MSHC_XINT | ||
| 223 | #define GPIO_INT_PORTA MX1_GPIO_INT_PORTA | ||
| 224 | #define GPIO_INT_PORTB MX1_GPIO_INT_PORTB | ||
| 225 | #define GPIO_INT_PORTC MX1_GPIO_INT_PORTC | ||
| 226 | #define LCDC_INT MX1_LCDC_INT | ||
| 227 | #define SIM_INT MX1_SIM_INT | ||
| 228 | #define SIM_DATA_INT MX1_SIM_DATA_INT | ||
| 229 | #define RTC_INT MX1_RTC_INT | ||
| 230 | #define RTC_SAMINT MX1_RTC_SAMINT | ||
| 231 | #define UART2_MINT_PFERR MX1_UART2_MINT_PFERR | ||
| 232 | #define UART2_MINT_RTS MX1_UART2_MINT_RTS | ||
| 233 | #define UART2_MINT_DTR MX1_UART2_MINT_DTR | ||
| 234 | #define UART2_MINT_UARTC MX1_UART2_MINT_UARTC | ||
| 235 | #define UART2_MINT_TX MX1_UART2_MINT_TX | ||
| 236 | #define UART2_MINT_RX MX1_UART2_MINT_RX | ||
| 237 | #define UART1_MINT_PFERR MX1_UART1_MINT_PFERR | ||
| 238 | #define UART1_MINT_RTS MX1_UART1_MINT_RTS | ||
| 239 | #define UART1_MINT_DTR MX1_UART1_MINT_DTR | ||
| 240 | #define UART1_MINT_UARTC MX1_UART1_MINT_UARTC | ||
| 241 | #define UART1_MINT_TX MX1_UART1_MINT_TX | ||
| 242 | #define UART1_MINT_RX MX1_UART1_MINT_RX | ||
| 243 | #define VOICE_DAC_INT MX1_VOICE_DAC_INT | ||
| 244 | #define VOICE_ADC_INT MX1_VOICE_ADC_INT | ||
| 245 | #define PEN_DATA_INT MX1_PEN_DATA_INT | ||
| 246 | #define PWM_INT MX1_PWM_INT | ||
| 247 | #define SDHC_INT MX1_SDHC_INT | ||
| 248 | #define I2C_INT MX1_INT_I2C | ||
| 249 | #define CSPI_INT MX1_CSPI_INT | ||
| 250 | #define SSI_TX_INT MX1_SSI_TX_INT | ||
| 251 | #define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT | ||
| 252 | #define SSI_RX_INT MX1_SSI_RX_INT | ||
| 253 | #define SSI_RX_ERR_INT MX1_SSI_RX_ERR_INT | ||
| 254 | #define TOUCH_INT MX1_TOUCH_INT | ||
| 255 | #define USBD_INT1 MX1_USBD_INT1 | ||
| 256 | #define USBD_INT2 MX1_USBD_INT2 | ||
| 257 | #define USBD_INT3 MX1_USBD_INT3 | ||
| 258 | #define USBD_INT4 MX1_USBD_INT4 | ||
| 259 | #define USBD_INT5 MX1_USBD_INT5 | ||
| 260 | #define USBD_INT6 MX1_USBD_INT6 | ||
| 261 | #define BTSYS_INT MX1_BTSYS_INT | ||
| 262 | #define BTTIM_INT MX1_BTTIM_INT | ||
| 263 | #define BTWUI_INT MX1_BTWUI_INT | ||
| 264 | #define TIM2_INT MX1_TIM2_INT | ||
| 265 | #define TIM1_INT MX1_TIM1_INT | ||
| 266 | #define DMA_ERR MX1_DMA_ERR | ||
| 267 | #define DMA_INT MX1_DMA_INT | ||
| 268 | #define GPIO_INT_PORTD MX1_GPIO_INT_PORTD | ||
| 269 | #define WDT_INT MX1_WDT_INT | ||
| 270 | #define DMA_REQ_UART3_T MX1_DMA_REQ_UART3_T | ||
| 271 | #define DMA_REQ_UART3_R MX1_DMA_REQ_UART3_R | ||
| 272 | #define DMA_REQ_SSI2_T MX1_DMA_REQ_SSI2_T | ||
| 273 | #define DMA_REQ_SSI2_R MX1_DMA_REQ_SSI2_R | ||
| 274 | #define DMA_REQ_CSI_STAT MX1_DMA_REQ_CSI_STAT | ||
| 275 | #define DMA_REQ_CSI_R MX1_DMA_REQ_CSI_R | ||
| 276 | #define DMA_REQ_MSHC MX1_DMA_REQ_MSHC | ||
| 277 | #define DMA_REQ_DSPA_DCT_DOUT MX1_DMA_REQ_DSPA_DCT_DOUT | ||
| 278 | #define DMA_REQ_DSPA_DCT_DIN MX1_DMA_REQ_DSPA_DCT_DIN | ||
| 279 | #define DMA_REQ_DSPA_MAC MX1_DMA_REQ_DSPA_MAC | ||
| 280 | #define DMA_REQ_EXT MX1_DMA_REQ_EXT | ||
| 281 | #define DMA_REQ_SDHC MX1_DMA_REQ_SDHC | ||
| 282 | #define DMA_REQ_SPI1_R MX1_DMA_REQ_SPI1_R | ||
| 283 | #define DMA_REQ_SPI1_T MX1_DMA_REQ_SPI1_T | ||
| 284 | #define DMA_REQ_SSI_T MX1_DMA_REQ_SSI_T | ||
| 285 | #define DMA_REQ_SSI_R MX1_DMA_REQ_SSI_R | ||
| 286 | #define DMA_REQ_ASP_DAC MX1_DMA_REQ_ASP_DAC | ||
| 287 | #define DMA_REQ_ASP_ADC MX1_DMA_REQ_ASP_ADC | ||
| 288 | #define DMA_REQ_USP_EP(x) MX1_DMA_REQ_USP_EP(x) | ||
| 289 | #define DMA_REQ_SPI2_R MX1_DMA_REQ_SPI2_R | ||
| 290 | #define DMA_REQ_SPI2_T MX1_DMA_REQ_SPI2_T | ||
| 291 | #define DMA_REQ_UART2_T MX1_DMA_REQ_UART2_T | ||
| 292 | #define DMA_REQ_UART2_R MX1_DMA_REQ_UART2_R | ||
| 293 | #define DMA_REQ_UART1_T MX1_DMA_REQ_UART1_T | ||
| 294 | #define DMA_REQ_UART1_R MX1_DMA_REQ_UART1_R | ||
| 295 | #endif /* ifdef IMX_NEEDS_DEPRECATED_SYMBOLS */ | ||
| 296 | 171 | ||
| 297 | #endif /* ifndef __MACH_MX1_H__ */ | 172 | #endif /* ifndef __MACH_MX1_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h index 8bc59720b6e4..6cd049ebbd8d 100644 --- a/arch/arm/plat-mxc/include/mach/mx21.h +++ b/arch/arm/plat-mxc/include/mach/mx21.h | |||
| @@ -26,7 +26,6 @@ | |||
| 26 | #define __MACH_MX21_H__ | 26 | #define __MACH_MX21_H__ |
| 27 | 27 | ||
| 28 | #define MX21_AIPI_BASE_ADDR 0x10000000 | 28 | #define MX21_AIPI_BASE_ADDR 0x10000000 |
| 29 | #define MX21_AIPI_BASE_ADDR_VIRT 0xf4000000 | ||
| 30 | #define MX21_AIPI_SIZE SZ_1M | 29 | #define MX21_AIPI_SIZE SZ_1M |
| 31 | #define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000) | 30 | #define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000) |
| 32 | #define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000) | 31 | #define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000) |
| @@ -49,6 +48,12 @@ | |||
| 49 | #define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000) | 48 | #define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000) |
| 50 | #define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000) | 49 | #define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000) |
| 51 | #define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000) | 50 | #define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000) |
| 51 | #define MX21_GPIO1_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x000) | ||
| 52 | #define MX21_GPIO2_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x100) | ||
| 53 | #define MX21_GPIO3_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x200) | ||
| 54 | #define MX21_GPIO4_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x300) | ||
| 55 | #define MX21_GPIO5_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x400) | ||
| 56 | #define MX21_GPIO6_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x500) | ||
| 52 | #define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000) | 57 | #define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000) |
| 53 | #define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000) | 58 | #define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000) |
| 54 | #define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000) | 59 | #define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000) |
| @@ -64,7 +69,6 @@ | |||
| 64 | #define MX21_AVIC_BASE_ADDR 0x10040000 | 69 | #define MX21_AVIC_BASE_ADDR 0x10040000 |
| 65 | 70 | ||
| 66 | #define MX21_SAHB1_BASE_ADDR 0x80000000 | 71 | #define MX21_SAHB1_BASE_ADDR 0x80000000 |
| 67 | #define MX21_SAHB1_BASE_ADDR_VIRT 0xf4100000 | ||
| 68 | #define MX21_SAHB1_SIZE SZ_1M | 72 | #define MX21_SAHB1_SIZE SZ_1M |
| 69 | #define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) | 73 | #define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) |
| 70 | 74 | ||
| @@ -82,7 +86,6 @@ | |||
| 82 | 86 | ||
| 83 | /* NAND, SDRAM, WEIM etc controllers */ | 87 | /* NAND, SDRAM, WEIM etc controllers */ |
| 84 | #define MX21_X_MEMC_BASE_ADDR 0xdf000000 | 88 | #define MX21_X_MEMC_BASE_ADDR 0xdf000000 |
| 85 | #define MX21_X_MEMC_BASE_ADDR_VIRT 0xf4200000 | ||
| 86 | #define MX21_X_MEMC_SIZE SZ_256K | 89 | #define MX21_X_MEMC_SIZE SZ_256K |
| 87 | 90 | ||
| 88 | #define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000) | 91 | #define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000) |
| @@ -92,10 +95,8 @@ | |||
| 92 | 95 | ||
| 93 | #define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */ | 96 | #define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */ |
| 94 | 97 | ||
| 95 | #define MX21_IO_ADDRESS(x) ( \ | 98 | #define MX21_IO_P2V(x) IMX_IO_P2V(x) |
| 96 | IMX_IO_ADDRESS(x, MX21_AIPI) ?: \ | 99 | #define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x)) |
| 97 | IMX_IO_ADDRESS(x, MX21_SAHB1) ?: \ | ||
| 98 | IMX_IO_ADDRESS(x, MX21_X_MEMC)) | ||
| 99 | 100 | ||
| 100 | /* fixed interrupt numbers */ | 101 | /* fixed interrupt numbers */ |
| 101 | #define MX21_INT_CSPI3 6 | 102 | #define MX21_INT_CSPI3 6 |
| @@ -184,39 +185,4 @@ | |||
| 184 | #define MX21_DMA_REQ_CSI_STAT 30 | 185 | #define MX21_DMA_REQ_CSI_STAT 30 |
| 185 | #define MX21_DMA_REQ_CSI_RX 31 | 186 | #define MX21_DMA_REQ_CSI_RX 31 |
| 186 | 187 | ||
| 187 | #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS | ||
| 188 | /* these should go away */ | ||
| 189 | #define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR | ||
| 190 | #define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR | ||
| 191 | #define CS0_BASE_ADDR MX21_CS0_BASE_ADDR | ||
| 192 | #define CS1_BASE_ADDR MX21_CS1_BASE_ADDR | ||
| 193 | #define CS2_BASE_ADDR MX21_CS2_BASE_ADDR | ||
| 194 | #define CS3_BASE_ADDR MX21_CS3_BASE_ADDR | ||
| 195 | #define CS4_BASE_ADDR MX21_CS4_BASE_ADDR | ||
| 196 | #define PCMCIA_MEM_BASE_ADDR MX21_PCMCIA_MEM_BASE_ADDR | ||
| 197 | #define CS5_BASE_ADDR MX21_CS5_BASE_ADDR | ||
| 198 | #define X_MEMC_BASE_ADDR MX21_X_MEMC_BASE_ADDR | ||
| 199 | #define X_MEMC_BASE_ADDR_VIRT MX21_X_MEMC_BASE_ADDR_VIRT | ||
| 200 | #define X_MEMC_SIZE MX21_X_MEMC_SIZE | ||
| 201 | #define SDRAMC_BASE_ADDR MX21_SDRAMC_BASE_ADDR | ||
| 202 | #define EIM_BASE_ADDR MX21_EIM_BASE_ADDR | ||
| 203 | #define PCMCIA_CTL_BASE_ADDR MX21_PCMCIA_CTL_BASE_ADDR | ||
| 204 | #define NFC_BASE_ADDR MX21_NFC_BASE_ADDR | ||
| 205 | #define IRAM_BASE_ADDR MX21_IRAM_BASE_ADDR | ||
| 206 | #define MXC_INT_FIRI MX21_INT_FIRI | ||
| 207 | #define MXC_INT_BMI MX21_INT_BMI | ||
| 208 | #define MXC_INT_EMMAENC MX21_INT_EMMAENC | ||
| 209 | #define MXC_INT_EMMADEC MX21_INT_EMMADEC | ||
| 210 | #define MXC_INT_USBWKUP MX21_INT_USBWKUP | ||
| 211 | #define MXC_INT_USBDMA MX21_INT_USBDMA | ||
| 212 | #define MXC_INT_USBHOST MX21_INT_USBHOST | ||
| 213 | #define MXC_INT_USBFUNC MX21_INT_USBFUNC | ||
| 214 | #define MXC_INT_USBMNP MX21_INT_USBMNP | ||
| 215 | #define MXC_INT_USBCTRL MX21_INT_USBCTRL | ||
| 216 | #define MXC_INT_USBCTRL MX21_INT_USBCTRL | ||
| 217 | #define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX | ||
| 218 | #define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX | ||
| 219 | #define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX | ||
| 220 | #endif | ||
| 221 | |||
| 222 | #endif /* ifndef __MACH_MX21_H__ */ | 188 | #endif /* ifndef __MACH_MX21_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index cf46a45b0d4e..087cd7ac8d52 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h | |||
| @@ -2,13 +2,10 @@ | |||
| 2 | #define __MACH_MX25_H__ | 2 | #define __MACH_MX25_H__ |
| 3 | 3 | ||
| 4 | #define MX25_AIPS1_BASE_ADDR 0x43f00000 | 4 | #define MX25_AIPS1_BASE_ADDR 0x43f00000 |
| 5 | #define MX25_AIPS1_BASE_ADDR_VIRT 0xfc000000 | ||
| 6 | #define MX25_AIPS1_SIZE SZ_1M | 5 | #define MX25_AIPS1_SIZE SZ_1M |
| 7 | #define MX25_AIPS2_BASE_ADDR 0x53f00000 | 6 | #define MX25_AIPS2_BASE_ADDR 0x53f00000 |
| 8 | #define MX25_AIPS2_BASE_ADDR_VIRT 0xfc200000 | ||
| 9 | #define MX25_AIPS2_SIZE SZ_1M | 7 | #define MX25_AIPS2_SIZE SZ_1M |
| 10 | #define MX25_AVIC_BASE_ADDR 0x68000000 | 8 | #define MX25_AVIC_BASE_ADDR 0x68000000 |
| 11 | #define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000 | ||
| 12 | #define MX25_AVIC_SIZE SZ_1M | 9 | #define MX25_AVIC_SIZE SZ_1M |
| 13 | 10 | ||
| 14 | #define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000) | 11 | #define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000) |
| @@ -21,20 +18,15 @@ | |||
| 21 | 18 | ||
| 22 | #define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) | 19 | #define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) |
| 23 | #define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000) | 20 | #define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000) |
| 21 | #define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000) | ||
| 22 | #define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000) | ||
| 23 | #define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000) | ||
| 24 | #define MX25_PWM3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa8000) | ||
| 25 | #define MX25_PWM4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc8000) | ||
| 26 | #define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000) | ||
| 27 | #define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000) | ||
| 24 | #define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000) | 28 | #define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000) |
| 25 | 29 | #define MX25_PWM1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xe0000) | |
| 26 | #define MX25_GPIO1_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xcc000) | ||
| 27 | #define MX25_GPIO2_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xd0000) | ||
| 28 | #define MX25_GPIO3_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000) | ||
| 29 | #define MX25_GPIO4_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000) | ||
| 30 | |||
| 31 | #define MX25_IO_ADDRESS(x) ( \ | ||
| 32 | IMX_IO_ADDRESS(x, MX25_AIPS1) ?: \ | ||
| 33 | IMX_IO_ADDRESS(x, MX25_AIPS2) ?: \ | ||
| 34 | IMX_IO_ADDRESS(x, MX25_AVIC)) | ||
| 35 | |||
| 36 | #define MX25_AIPS1_IO_ADDRESS(x) \ | ||
| 37 | (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT) | ||
| 38 | 30 | ||
| 39 | #define MX25_UART1_BASE_ADDR 0x43f90000 | 31 | #define MX25_UART1_BASE_ADDR 0x43f90000 |
| 40 | #define MX25_UART2_BASE_ADDR 0x43f94000 | 32 | #define MX25_UART2_BASE_ADDR 0x43f94000 |
| @@ -55,9 +47,19 @@ | |||
| 55 | #define MX25_LCDC_BASE_ADDR 0x53fbc000 | 47 | #define MX25_LCDC_BASE_ADDR 0x53fbc000 |
| 56 | #define MX25_KPP_BASE_ADDR 0x43fa8000 | 48 | #define MX25_KPP_BASE_ADDR 0x43fa8000 |
| 57 | #define MX25_SDMA_BASE_ADDR 0x53fd4000 | 49 | #define MX25_SDMA_BASE_ADDR 0x53fd4000 |
| 58 | #define MX25_OTG_BASE_ADDR 0x53ff4000 | 50 | #define MX25_USB_BASE_ADDR 0x53ff4000 |
| 51 | #define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000) | ||
| 52 | /* | ||
| 53 | * The reference manual (IMX25RM, Rev. 1, 06/2009) specifies an offset of 0x200 | ||
| 54 | * for the host controller. Early documentation drafts specified 0x400 and | ||
| 55 | * Freescale internal sources confirm only the latter value to work. | ||
| 56 | */ | ||
| 57 | #define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0400) | ||
| 59 | #define MX25_CSI_BASE_ADDR 0x53ff8000 | 58 | #define MX25_CSI_BASE_ADDR 0x53ff8000 |
| 60 | 59 | ||
| 60 | #define MX25_IO_P2V(x) IMX_IO_P2V(x) | ||
| 61 | #define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x)) | ||
| 62 | |||
| 61 | #define MX25_INT_CSPI3 0 | 63 | #define MX25_INT_CSPI3 0 |
| 62 | #define MX25_INT_I2C1 3 | 64 | #define MX25_INT_I2C1 3 |
| 63 | #define MX25_INT_I2C2 4 | 65 | #define MX25_INT_I2C2 4 |
| @@ -69,18 +71,28 @@ | |||
| 69 | #define MX25_INT_SSI1 12 | 71 | #define MX25_INT_SSI1 12 |
| 70 | #define MX25_INT_CSPI2 13 | 72 | #define MX25_INT_CSPI2 13 |
| 71 | #define MX25_INT_CSPI1 14 | 73 | #define MX25_INT_CSPI1 14 |
| 74 | #define MX25_INT_GPIO3 16 | ||
| 72 | #define MX25_INT_CSI 17 | 75 | #define MX25_INT_CSI 17 |
| 73 | #define MX25_INT_UART3 18 | 76 | #define MX25_INT_UART3 18 |
| 77 | #define MX25_INT_GPIO4 23 | ||
| 74 | #define MX25_INT_KPP 24 | 78 | #define MX25_INT_KPP 24 |
| 75 | #define MX25_INT_DRYICE 25 | 79 | #define MX25_INT_DRYICE 25 |
| 80 | #define MX25_INT_PWM1 26 | ||
| 76 | #define MX25_INT_UART2 32 | 81 | #define MX25_INT_UART2 32 |
| 77 | #define MX25_INT_NFC 33 | 82 | #define MX25_INT_NFC 33 |
| 78 | #define MX25_INT_SDMA 34 | 83 | #define MX25_INT_SDMA 34 |
| 84 | #define MX25_INT_USB_HS 35 | ||
| 85 | #define MX25_INT_PWM2 36 | ||
| 86 | #define MX25_INT_USB_OTG 37 | ||
| 79 | #define MX25_INT_LCDC 39 | 87 | #define MX25_INT_LCDC 39 |
| 80 | #define MX25_INT_UART5 40 | 88 | #define MX25_INT_UART5 40 |
| 89 | #define MX25_INT_PWM3 41 | ||
| 90 | #define MX25_INT_PWM4 42 | ||
| 81 | #define MX25_INT_CAN1 43 | 91 | #define MX25_INT_CAN1 43 |
| 82 | #define MX25_INT_CAN2 44 | 92 | #define MX25_INT_CAN2 44 |
| 83 | #define MX25_INT_UART1 45 | 93 | #define MX25_INT_UART1 45 |
| 94 | #define MX25_INT_GPIO2 51 | ||
| 95 | #define MX25_INT_GPIO1 52 | ||
| 84 | #define MX25_INT_FEC 57 | 96 | #define MX25_INT_FEC 57 |
| 85 | 97 | ||
| 86 | #define MX25_DMA_REQ_SSI2_RX1 22 | 98 | #define MX25_DMA_REQ_SSI2_RX1 22 |
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index 2237ba2e5351..cbc43ad5ef48 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h | |||
| @@ -29,7 +29,6 @@ | |||
| 29 | #endif | 29 | #endif |
| 30 | 30 | ||
| 31 | #define MX27_AIPI_BASE_ADDR 0x10000000 | 31 | #define MX27_AIPI_BASE_ADDR 0x10000000 |
| 32 | #define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000 | ||
| 33 | #define MX27_AIPI_SIZE SZ_1M | 32 | #define MX27_AIPI_SIZE SZ_1M |
| 34 | #define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000) | 33 | #define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000) |
| 35 | #define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000) | 34 | #define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000) |
| @@ -52,6 +51,12 @@ | |||
| 52 | #define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000) | 51 | #define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000) |
| 53 | #define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000) | 52 | #define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000) |
| 54 | #define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000) | 53 | #define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000) |
| 54 | #define MX27_GPIO1_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x000) | ||
| 55 | #define MX27_GPIO2_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x100) | ||
| 56 | #define MX27_GPIO3_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x200) | ||
| 57 | #define MX27_GPIO4_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x300) | ||
| 58 | #define MX27_GPIO5_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x400) | ||
| 59 | #define MX27_GPIO6_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x500) | ||
| 55 | #define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000) | 60 | #define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000) |
| 56 | #define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000) | 61 | #define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000) |
| 57 | #define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000) | 62 | #define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000) |
| @@ -65,11 +70,13 @@ | |||
| 65 | #define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000) | 70 | #define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000) |
| 66 | #define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000) | 71 | #define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000) |
| 67 | #define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000) | 72 | #define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000) |
| 68 | #define MX27_USBOTG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000) | 73 | #define MX27_USB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000) |
| 69 | #define MX27_OTG_BASE_ADDR MX27_USBOTG_BASE_ADDR | 74 | #define MX27_USB_OTG_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0000) |
| 75 | #define MX27_USB_HS1_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0200) | ||
| 76 | #define MX27_USB_HS2_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0400) | ||
| 70 | #define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000) | 77 | #define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000) |
| 71 | #define MX27_EMMA_PP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000) | 78 | #define MX27_EMMAPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000) |
| 72 | #define MX27_EMMA_PRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400) | 79 | #define MX27_EMMAPRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400) |
| 73 | #define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000) | 80 | #define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000) |
| 74 | #define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800) | 81 | #define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800) |
| 75 | #define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000) | 82 | #define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000) |
| @@ -87,7 +94,6 @@ | |||
| 87 | #define MX27_ROMP_BASE_ADDR 0x10041000 | 94 | #define MX27_ROMP_BASE_ADDR 0x10041000 |
| 88 | 95 | ||
| 89 | #define MX27_SAHB1_BASE_ADDR 0x80000000 | 96 | #define MX27_SAHB1_BASE_ADDR 0x80000000 |
| 90 | #define MX27_SAHB1_BASE_ADDR_VIRT 0xf4100000 | ||
| 91 | #define MX27_SAHB1_SIZE SZ_1M | 97 | #define MX27_SAHB1_SIZE SZ_1M |
| 92 | #define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000) | 98 | #define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000) |
| 93 | #define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000) | 99 | #define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000) |
| @@ -105,7 +111,6 @@ | |||
| 105 | 111 | ||
| 106 | /* NAND, SDRAM, WEIM, M3IF, EMI controllers */ | 112 | /* NAND, SDRAM, WEIM, M3IF, EMI controllers */ |
| 107 | #define MX27_X_MEMC_BASE_ADDR 0xd8000000 | 113 | #define MX27_X_MEMC_BASE_ADDR 0xd8000000 |
| 108 | #define MX27_X_MEMC_BASE_ADDR_VIRT 0xf4200000 | ||
| 109 | #define MX27_X_MEMC_SIZE SZ_1M | 114 | #define MX27_X_MEMC_SIZE SZ_1M |
| 110 | #define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR) | 115 | #define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR) |
| 111 | #define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000) | 116 | #define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000) |
| @@ -123,10 +128,8 @@ | |||
| 123 | /* IRAM */ | 128 | /* IRAM */ |
| 124 | #define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */ | 129 | #define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */ |
| 125 | 130 | ||
| 126 | #define MX27_IO_ADDRESS(x) ( \ | 131 | #define MX27_IO_P2V(x) IMX_IO_P2V(x) |
| 127 | IMX_IO_ADDRESS(x, MX27_AIPI) ?: \ | 132 | #define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x)) |
| 128 | IMX_IO_ADDRESS(x, MX27_SAHB1) ?: \ | ||
| 129 | IMX_IO_ADDRESS(x, MX27_X_MEMC)) | ||
| 130 | 133 | ||
| 131 | #ifndef __ASSEMBLER__ | 134 | #ifndef __ASSEMBLER__ |
| 132 | static inline void mx27_setup_weimcs(size_t cs, | 135 | static inline void mx27_setup_weimcs(size_t cs, |
| @@ -192,9 +195,9 @@ static inline void mx27_setup_weimcs(size_t cs, | |||
| 192 | #define MX27_INT_EMMAPRP 51 | 195 | #define MX27_INT_EMMAPRP 51 |
| 193 | #define MX27_INT_EMMAPP 52 | 196 | #define MX27_INT_EMMAPP 52 |
| 194 | #define MX27_INT_VPU 53 | 197 | #define MX27_INT_VPU 53 |
| 195 | #define MX27_INT_USB1 54 | 198 | #define MX27_INT_USB_HS1 54 |
| 196 | #define MX27_INT_USB2 55 | 199 | #define MX27_INT_USB_HS2 55 |
| 197 | #define MX27_INT_USB3 56 | 200 | #define MX27_INT_USB_OTG 56 |
| 198 | #define MX27_INT_SCC_SMN 57 | 201 | #define MX27_INT_SCC_SMN 57 |
| 199 | #define MX27_INT_SCC_SCM 58 | 202 | #define MX27_INT_SCC_SCM 58 |
| 200 | #define MX27_INT_SAHARA 59 | 203 | #define MX27_INT_SAHARA 59 |
| @@ -241,82 +244,8 @@ static inline void mx27_setup_weimcs(size_t cs, | |||
| 241 | #define MX27_DMA_REQ_SDHC3 36 | 244 | #define MX27_DMA_REQ_SDHC3 36 |
| 242 | #define MX27_DMA_REQ_NFC 37 | 245 | #define MX27_DMA_REQ_NFC 37 |
| 243 | 246 | ||
| 244 | /* silicon revisions specific to i.MX27 */ | ||
| 245 | #define CHIP_REV_1_0 0x00 | ||
| 246 | #define CHIP_REV_2_0 0x01 | ||
| 247 | |||
| 248 | #ifndef __ASSEMBLY__ | 247 | #ifndef __ASSEMBLY__ |
| 249 | extern int mx27_revision(void); | 248 | extern int mx27_revision(void); |
| 250 | #endif | 249 | #endif |
| 251 | 250 | ||
| 252 | #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS | ||
| 253 | /* these should go away */ | ||
| 254 | #define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR | ||
| 255 | #define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR | ||
| 256 | #define GPT4_BASE_ADDR MX27_GPT4_BASE_ADDR | ||
| 257 | #define UART5_BASE_ADDR MX27_UART5_BASE_ADDR | ||
| 258 | #define UART6_BASE_ADDR MX27_UART6_BASE_ADDR | ||
| 259 | #define I2C2_BASE_ADDR MX27_I2C2_BASE_ADDR | ||
| 260 | #define SDHC3_BASE_ADDR MX27_SDHC3_BASE_ADDR | ||
| 261 | #define GPT6_BASE_ADDR MX27_GPT6_BASE_ADDR | ||
| 262 | #define VPU_BASE_ADDR MX27_VPU_BASE_ADDR | ||
| 263 | #define OTG_BASE_ADDR MX27_OTG_BASE_ADDR | ||
| 264 | #define SAHARA_BASE_ADDR MX27_SAHARA_BASE_ADDR | ||
| 265 | #define IIM_BASE_ADDR MX27_IIM_BASE_ADDR | ||
| 266 | #define RTIC_BASE_ADDR MX27_RTIC_BASE_ADDR | ||
| 267 | #define FEC_BASE_ADDR MX27_FEC_BASE_ADDR | ||
| 268 | #define SCC_BASE_ADDR MX27_SCC_BASE_ADDR | ||
| 269 | #define ETB_BASE_ADDR MX27_ETB_BASE_ADDR | ||
| 270 | #define ETB_RAM_BASE_ADDR MX27_ETB_RAM_BASE_ADDR | ||
| 271 | #define ROMP_BASE_ADDR MX27_ROMP_BASE_ADDR | ||
| 272 | #define ATA_BASE_ADDR MX27_ATA_BASE_ADDR | ||
| 273 | #define SDRAM_BASE_ADDR MX27_SDRAM_BASE_ADDR | ||
| 274 | #define CSD1_BASE_ADDR MX27_CSD1_BASE_ADDR | ||
| 275 | #define CS0_BASE_ADDR MX27_CS0_BASE_ADDR | ||
| 276 | #define CS1_BASE_ADDR MX27_CS1_BASE_ADDR | ||
| 277 | #define CS2_BASE_ADDR MX27_CS2_BASE_ADDR | ||
| 278 | #define CS3_BASE_ADDR MX27_CS3_BASE_ADDR | ||
| 279 | #define CS4_BASE_ADDR MX27_CS4_BASE_ADDR | ||
| 280 | #define CS5_BASE_ADDR MX27_CS5_BASE_ADDR | ||
| 281 | #define X_MEMC_BASE_ADDR MX27_X_MEMC_BASE_ADDR | ||
| 282 | #define X_MEMC_BASE_ADDR_VIRT MX27_X_MEMC_BASE_ADDR_VIRT | ||
| 283 | #define X_MEMC_SIZE MX27_X_MEMC_SIZE | ||
| 284 | #define NFC_BASE_ADDR MX27_NFC_BASE_ADDR | ||
| 285 | #define SDRAMC_BASE_ADDR MX27_SDRAMC_BASE_ADDR | ||
| 286 | #define WEIM_BASE_ADDR MX27_WEIM_BASE_ADDR | ||
| 287 | #define M3IF_BASE_ADDR MX27_M3IF_BASE_ADDR | ||
| 288 | #define PCMCIA_CTL_BASE_ADDR MX27_PCMCIA_CTL_BASE_ADDR | ||
| 289 | #define PCMCIA_MEM_BASE_ADDR MX27_PCMCIA_MEM_BASE_ADDR | ||
| 290 | #define IRAM_BASE_ADDR MX27_IRAM_BASE_ADDR | ||
| 291 | #define MXC_INT_I2C2 MX27_INT_I2C2 | ||
| 292 | #define MXC_INT_GPT6 MX27_INT_GPT6 | ||
| 293 | #define MXC_INT_GPT5 MX27_INT_GPT5 | ||
| 294 | #define MXC_INT_GPT4 MX27_INT_GPT4 | ||
| 295 | #define MXC_INT_RTIC MX27_INT_RTIC | ||
| 296 | #define MXC_INT_SDHC MX27_INT_SDHC | ||
| 297 | #define MXC_INT_SDHC3 MX27_INT_SDHC3 | ||
| 298 | #define MXC_INT_ATA MX27_INT_ATA | ||
| 299 | #define MXC_INT_UART6 MX27_INT_UART6 | ||
| 300 | #define MXC_INT_UART5 MX27_INT_UART5 | ||
| 301 | #define MXC_INT_FEC MX27_INT_FEC | ||
| 302 | #define MXC_INT_VPU MX27_INT_VPU | ||
| 303 | #define MXC_INT_USB1 MX27_INT_USB1 | ||
| 304 | #define MXC_INT_USB2 MX27_INT_USB2 | ||
| 305 | #define MXC_INT_USB3 MX27_INT_USB3 | ||
| 306 | #define MXC_INT_SCC_SMN MX27_INT_SCC_SMN | ||
| 307 | #define MXC_INT_SCC_SCM MX27_INT_SCC_SCM | ||
| 308 | #define MXC_INT_SAHARA MX27_INT_SAHARA | ||
| 309 | #define MXC_INT_IIM MX27_INT_IIM | ||
| 310 | #define MXC_INT_CCM MX27_INT_CCM | ||
| 311 | #define DMA_REQ_MSHC MX27_DMA_REQ_MSHC | ||
| 312 | #define DMA_REQ_ATA_TX MX27_DMA_REQ_ATA_TX | ||
| 313 | #define DMA_REQ_ATA_RCV MX27_DMA_REQ_ATA_RCV | ||
| 314 | #define DMA_REQ_UART5_TX MX27_DMA_REQ_UART5_TX | ||
| 315 | #define DMA_REQ_UART5_RX MX27_DMA_REQ_UART5_RX | ||
| 316 | #define DMA_REQ_UART6_TX MX27_DMA_REQ_UART6_TX | ||
| 317 | #define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX | ||
| 318 | #define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3 | ||
| 319 | #define DMA_REQ_NFC MX27_DMA_REQ_NFC | ||
| 320 | #endif | ||
| 321 | |||
| 322 | #endif /* ifndef __MACH_MX27_H__ */ | 251 | #endif /* ifndef __MACH_MX27_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h index afb895a0b5b8..6d07839fdec2 100644 --- a/arch/arm/plat-mxc/include/mach/mx2x.h +++ b/arch/arm/plat-mxc/include/mach/mx2x.h | |||
| @@ -27,7 +27,6 @@ | |||
| 27 | 27 | ||
| 28 | /* Register offsets */ | 28 | /* Register offsets */ |
| 29 | #define MX2x_AIPI_BASE_ADDR 0x10000000 | 29 | #define MX2x_AIPI_BASE_ADDR 0x10000000 |
| 30 | #define MX2x_AIPI_BASE_ADDR_VIRT 0xf4000000 | ||
| 31 | #define MX2x_AIPI_SIZE SZ_1M | 30 | #define MX2x_AIPI_SIZE SZ_1M |
| 32 | #define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000) | 31 | #define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000) |
| 33 | #define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000) | 32 | #define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000) |
| @@ -65,43 +64,9 @@ | |||
| 65 | #define MX2x_AVIC_BASE_ADDR 0x10040000 | 64 | #define MX2x_AVIC_BASE_ADDR 0x10040000 |
| 66 | 65 | ||
| 67 | #define MX2x_SAHB1_BASE_ADDR 0x80000000 | 66 | #define MX2x_SAHB1_BASE_ADDR 0x80000000 |
| 68 | #define MX2x_SAHB1_BASE_ADDR_VIRT 0xf4100000 | ||
| 69 | #define MX2x_SAHB1_SIZE SZ_1M | 67 | #define MX2x_SAHB1_SIZE SZ_1M |
| 70 | #define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) | 68 | #define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) |
| 71 | 69 | ||
| 72 | /* | ||
| 73 | * This macro defines the physical to virtual address mapping for all the | ||
| 74 | * peripheral modules. It is used by passing in the physical address as x | ||
| 75 | * and returning the virtual address. If the physical address is not mapped, | ||
| 76 | * it returns 0xDEADBEEF | ||
| 77 | */ | ||
| 78 | #define IO_ADDRESS(x) \ | ||
| 79 | (void __force __iomem *) \ | ||
| 80 | (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \ | ||
| 81 | AIPI_IO_ADDRESS(x) : \ | ||
| 82 | ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \ | ||
| 83 | SAHB1_IO_ADDRESS(x) : \ | ||
| 84 | ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \ | ||
| 85 | X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF) | ||
| 86 | |||
| 87 | /* define the address mapping macros: in physical address order */ | ||
| 88 | #define AIPI_IO_ADDRESS(x) \ | ||
| 89 | (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT) | ||
| 90 | |||
| 91 | #define AVIC_IO_ADDRESS(x) AIPI_IO_ADDRESS(x) | ||
| 92 | |||
| 93 | #define SAHB1_IO_ADDRESS(x) \ | ||
| 94 | (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT) | ||
| 95 | |||
| 96 | #define CS4_IO_ADDRESS(x) \ | ||
| 97 | (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT) | ||
| 98 | |||
| 99 | #define X_MEMC_IO_ADDRESS(x) \ | ||
| 100 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) | ||
| 101 | |||
| 102 | #define PCMCIA_IO_ADDRESS(x) \ | ||
| 103 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) | ||
| 104 | |||
| 105 | /* fixed interrupt numbers */ | 70 | /* fixed interrupt numbers */ |
| 106 | #define MX2x_INT_CSPI3 6 | 71 | #define MX2x_INT_CSPI3 6 |
| 107 | #define MX2x_INT_GPIO 8 | 72 | #define MX2x_INT_GPIO 8 |
| @@ -176,118 +141,4 @@ | |||
| 176 | #define MX2x_DMA_REQ_CSI_STAT 30 | 141 | #define MX2x_DMA_REQ_CSI_STAT 30 |
| 177 | #define MX2x_DMA_REQ_CSI_RX 31 | 142 | #define MX2x_DMA_REQ_CSI_RX 31 |
| 178 | 143 | ||
| 179 | #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS | ||
| 180 | /* these should go away */ | ||
| 181 | #define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR | ||
| 182 | #define AIPI_BASE_ADDR_VIRT MX2x_AIPI_BASE_ADDR_VIRT | ||
| 183 | #define AIPI_SIZE MX2x_AIPI_SIZE | ||
| 184 | #define DMA_BASE_ADDR MX2x_DMA_BASE_ADDR | ||
| 185 | #define WDOG_BASE_ADDR MX2x_WDOG_BASE_ADDR | ||
| 186 | #define GPT1_BASE_ADDR MX2x_GPT1_BASE_ADDR | ||
| 187 | #define GPT2_BASE_ADDR MX2x_GPT2_BASE_ADDR | ||
| 188 | #define GPT3_BASE_ADDR MX2x_GPT3_BASE_ADDR | ||
| 189 | #define PWM_BASE_ADDR MX2x_PWM_BASE_ADDR | ||
| 190 | #define RTC_BASE_ADDR MX2x_RTC_BASE_ADDR | ||
| 191 | #define KPP_BASE_ADDR MX2x_KPP_BASE_ADDR | ||
| 192 | #define OWIRE_BASE_ADDR MX2x_OWIRE_BASE_ADDR | ||
| 193 | #define UART1_BASE_ADDR MX2x_UART1_BASE_ADDR | ||
| 194 | #define UART2_BASE_ADDR MX2x_UART2_BASE_ADDR | ||
| 195 | #define UART3_BASE_ADDR MX2x_UART3_BASE_ADDR | ||
| 196 | #define UART4_BASE_ADDR MX2x_UART4_BASE_ADDR | ||
| 197 | #define CSPI1_BASE_ADDR MX2x_CSPI1_BASE_ADDR | ||
| 198 | #define CSPI2_BASE_ADDR MX2x_CSPI2_BASE_ADDR | ||
| 199 | #define SSI1_BASE_ADDR MX2x_SSI1_BASE_ADDR | ||
| 200 | #define SSI2_BASE_ADDR MX2x_SSI2_BASE_ADDR | ||
| 201 | #define I2C_BASE_ADDR MX2x_I2C_BASE_ADDR | ||
| 202 | #define SDHC1_BASE_ADDR MX2x_SDHC1_BASE_ADDR | ||
| 203 | #define SDHC2_BASE_ADDR MX2x_SDHC2_BASE_ADDR | ||
| 204 | #define GPIO_BASE_ADDR MX2x_GPIO_BASE_ADDR | ||
| 205 | #define AUDMUX_BASE_ADDR MX2x_AUDMUX_BASE_ADDR | ||
| 206 | #define CSPI3_BASE_ADDR MX2x_CSPI3_BASE_ADDR | ||
| 207 | #define LCDC_BASE_ADDR MX2x_LCDC_BASE_ADDR | ||
| 208 | #define SLCDC_BASE_ADDR MX2x_SLCDC_BASE_ADDR | ||
| 209 | #define USBOTG_BASE_ADDR MX2x_USBOTG_BASE_ADDR | ||
| 210 | #define EMMA_PP_BASE_ADDR MX2x_EMMA_PP_BASE_ADDR | ||
| 211 | #define EMMA_PRP_BASE_ADDR MX2x_EMMA_PRP_BASE_ADDR | ||
| 212 | #define CCM_BASE_ADDR MX2x_CCM_BASE_ADDR | ||
| 213 | #define SYSCTRL_BASE_ADDR MX2x_SYSCTRL_BASE_ADDR | ||
| 214 | #define JAM_BASE_ADDR MX2x_JAM_BASE_ADDR | ||
| 215 | #define MAX_BASE_ADDR MX2x_MAX_BASE_ADDR | ||
| 216 | #define AVIC_BASE_ADDR MX2x_AVIC_BASE_ADDR | ||
| 217 | #define SAHB1_BASE_ADDR MX2x_SAHB1_BASE_ADDR | ||
| 218 | #define SAHB1_BASE_ADDR_VIRT MX2x_SAHB1_BASE_ADDR_VIRT | ||
| 219 | #define SAHB1_SIZE MX2x_SAHB1_SIZE | ||
| 220 | #define CSI_BASE_ADDR MX2x_CSI_BASE_ADDR | ||
| 221 | #define MXC_INT_CSPI3 MX2x_INT_CSPI3 | ||
| 222 | #define MXC_INT_GPIO MX2x_INT_GPIO | ||
| 223 | #define MXC_INT_SDHC2 MX2x_INT_SDHC2 | ||
| 224 | #define MXC_INT_SDHC1 MX2x_INT_SDHC1 | ||
| 225 | #define MXC_INT_I2C MX2x_INT_I2C | ||
| 226 | #define MXC_INT_SSI2 MX2x_INT_SSI2 | ||
| 227 | #define MXC_INT_SSI1 MX2x_INT_SSI1 | ||
| 228 | #define MXC_INT_CSPI2 MX2x_INT_CSPI2 | ||
| 229 | #define MXC_INT_CSPI1 MX2x_INT_CSPI1 | ||
| 230 | #define MXC_INT_UART4 MX2x_INT_UART4 | ||
| 231 | #define MXC_INT_UART3 MX2x_INT_UART3 | ||
| 232 | #define MXC_INT_UART2 MX2x_INT_UART2 | ||
| 233 | #define MXC_INT_UART1 MX2x_INT_UART1 | ||
| 234 | #define MXC_INT_KPP MX2x_INT_KPP | ||
| 235 | #define MXC_INT_RTC MX2x_INT_RTC | ||
| 236 | #define MXC_INT_PWM MX2x_INT_PWM | ||
| 237 | #define MXC_INT_GPT3 MX2x_INT_GPT3 | ||
| 238 | #define MXC_INT_GPT2 MX2x_INT_GPT2 | ||
| 239 | #define MXC_INT_GPT1 MX2x_INT_GPT1 | ||
| 240 | #define MXC_INT_WDOG MX2x_INT_WDOG | ||
| 241 | #define MXC_INT_PCMCIA MX2x_INT_PCMCIA | ||
| 242 | #define MXC_INT_NANDFC MX2x_INT_NANDFC | ||
| 243 | #define MXC_INT_CSI MX2x_INT_CSI | ||
| 244 | #define MXC_INT_DMACH0 MX2x_INT_DMACH0 | ||
| 245 | #define MXC_INT_DMACH1 MX2x_INT_DMACH1 | ||
| 246 | #define MXC_INT_DMACH2 MX2x_INT_DMACH2 | ||
| 247 | #define MXC_INT_DMACH3 MX2x_INT_DMACH3 | ||
| 248 | #define MXC_INT_DMACH4 MX2x_INT_DMACH4 | ||
| 249 | #define MXC_INT_DMACH5 MX2x_INT_DMACH5 | ||
| 250 | #define MXC_INT_DMACH6 MX2x_INT_DMACH6 | ||
| 251 | #define MXC_INT_DMACH7 MX2x_INT_DMACH7 | ||
| 252 | #define MXC_INT_DMACH8 MX2x_INT_DMACH8 | ||
| 253 | #define MXC_INT_DMACH9 MX2x_INT_DMACH9 | ||
| 254 | #define MXC_INT_DMACH10 MX2x_INT_DMACH10 | ||
| 255 | #define MXC_INT_DMACH11 MX2x_INT_DMACH11 | ||
| 256 | #define MXC_INT_DMACH12 MX2x_INT_DMACH12 | ||
| 257 | #define MXC_INT_DMACH13 MX2x_INT_DMACH13 | ||
| 258 | #define MXC_INT_DMACH14 MX2x_INT_DMACH14 | ||
| 259 | #define MXC_INT_DMACH15 MX2x_INT_DMACH15 | ||
| 260 | #define MXC_INT_EMMAPRP MX2x_INT_EMMAPRP | ||
| 261 | #define MXC_INT_EMMAPP MX2x_INT_EMMAPP | ||
| 262 | #define MXC_INT_SLCDC MX2x_INT_SLCDC | ||
| 263 | #define MXC_INT_LCDC MX2x_INT_LCDC | ||
| 264 | #define DMA_REQ_CSPI3_RX MX2x_DMA_REQ_CSPI3_RX | ||
| 265 | #define DMA_REQ_CSPI3_TX MX2x_DMA_REQ_CSPI3_TX | ||
| 266 | #define DMA_REQ_EXT MX2x_DMA_REQ_EXT | ||
| 267 | #define DMA_REQ_SDHC2 MX2x_DMA_REQ_SDHC2 | ||
| 268 | #define DMA_REQ_SDHC1 MX2x_DMA_REQ_SDHC1 | ||
| 269 | #define DMA_REQ_SSI2_RX0 MX2x_DMA_REQ_SSI2_RX0 | ||
| 270 | #define DMA_REQ_SSI2_TX0 MX2x_DMA_REQ_SSI2_TX0 | ||
| 271 | #define DMA_REQ_SSI2_RX1 MX2x_DMA_REQ_SSI2_RX1 | ||
| 272 | #define DMA_REQ_SSI2_TX1 MX2x_DMA_REQ_SSI2_TX1 | ||
| 273 | #define DMA_REQ_SSI1_RX0 MX2x_DMA_REQ_SSI1_RX0 | ||
| 274 | #define DMA_REQ_SSI1_TX0 MX2x_DMA_REQ_SSI1_TX0 | ||
| 275 | #define DMA_REQ_SSI1_RX1 MX2x_DMA_REQ_SSI1_RX1 | ||
| 276 | #define DMA_REQ_SSI1_TX1 MX2x_DMA_REQ_SSI1_TX1 | ||
| 277 | #define DMA_REQ_CSPI2_RX MX2x_DMA_REQ_CSPI2_RX | ||
| 278 | #define DMA_REQ_CSPI2_TX MX2x_DMA_REQ_CSPI2_TX | ||
| 279 | #define DMA_REQ_CSPI1_RX MX2x_DMA_REQ_CSPI1_RX | ||
| 280 | #define DMA_REQ_CSPI1_TX MX2x_DMA_REQ_CSPI1_TX | ||
| 281 | #define DMA_REQ_UART4_RX MX2x_DMA_REQ_UART4_RX | ||
| 282 | #define DMA_REQ_UART4_TX MX2x_DMA_REQ_UART4_TX | ||
| 283 | #define DMA_REQ_UART3_RX MX2x_DMA_REQ_UART3_RX | ||
| 284 | #define DMA_REQ_UART3_TX MX2x_DMA_REQ_UART3_TX | ||
| 285 | #define DMA_REQ_UART2_RX MX2x_DMA_REQ_UART2_RX | ||
| 286 | #define DMA_REQ_UART2_TX MX2x_DMA_REQ_UART2_TX | ||
| 287 | #define DMA_REQ_UART1_RX MX2x_DMA_REQ_UART1_RX | ||
| 288 | #define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX | ||
| 289 | #define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT | ||
| 290 | #define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX | ||
| 291 | #endif | ||
| 292 | |||
| 293 | #endif /* ifndef __MACH_MX2x_H__ */ | 144 | #endif /* ifndef __MACH_MX2x_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index 61cfe827498b..79e7fc01bb59 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h | |||
| @@ -15,7 +15,6 @@ | |||
| 15 | #define MX31_L2CC_SIZE SZ_1M | 15 | #define MX31_L2CC_SIZE SZ_1M |
| 16 | 16 | ||
| 17 | #define MX31_AIPS1_BASE_ADDR 0x43f00000 | 17 | #define MX31_AIPS1_BASE_ADDR 0x43f00000 |
| 18 | #define MX31_AIPS1_BASE_ADDR_VIRT 0xfc000000 | ||
| 19 | #define MX31_AIPS1_SIZE SZ_1M | 18 | #define MX31_AIPS1_SIZE SZ_1M |
| 20 | #define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000) | 19 | #define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000) |
| 21 | #define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000) | 20 | #define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000) |
| @@ -25,7 +24,10 @@ | |||
| 25 | #define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000) | 24 | #define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000) |
| 26 | #define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000) | 25 | #define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000) |
| 27 | #define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000) | 26 | #define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000) |
| 28 | #define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) | 27 | #define MX31_USB_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) |
| 28 | #define MX31_USB_OTG_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0000) | ||
| 29 | #define MX31_USB_HS1_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0200) | ||
| 30 | #define MX31_USB_HS2_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0400) | ||
| 29 | #define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000) | 31 | #define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000) |
| 30 | #define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000) | 32 | #define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000) |
| 31 | #define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000) | 33 | #define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000) |
| @@ -41,10 +43,9 @@ | |||
| 41 | #define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000) | 43 | #define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000) |
| 42 | 44 | ||
| 43 | #define MX31_SPBA0_BASE_ADDR 0x50000000 | 45 | #define MX31_SPBA0_BASE_ADDR 0x50000000 |
| 44 | #define MX31_SPBA0_BASE_ADDR_VIRT 0xfc100000 | ||
| 45 | #define MX31_SPBA0_SIZE SZ_1M | 46 | #define MX31_SPBA0_SIZE SZ_1M |
| 46 | #define MX31_MMC_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000) | 47 | #define MX31_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000) |
| 47 | #define MX31_MMC_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000) | 48 | #define MX31_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000) |
| 48 | #define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000) | 49 | #define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000) |
| 49 | #define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000) | 50 | #define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000) |
| 50 | #define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000) | 51 | #define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000) |
| @@ -55,7 +56,6 @@ | |||
| 55 | #define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000) | 56 | #define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000) |
| 56 | 57 | ||
| 57 | #define MX31_AIPS2_BASE_ADDR 0x53f00000 | 58 | #define MX31_AIPS2_BASE_ADDR 0x53f00000 |
| 58 | #define MX31_AIPS2_BASE_ADDR_VIRT 0xfc200000 | ||
| 59 | #define MX31_AIPS2_SIZE SZ_1M | 59 | #define MX31_AIPS2_SIZE SZ_1M |
| 60 | #define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000) | 60 | #define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000) |
| 61 | #define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000) | 61 | #define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000) |
| @@ -84,7 +84,6 @@ | |||
| 84 | #define MX31_ROMP_SIZE SZ_1M | 84 | #define MX31_ROMP_SIZE SZ_1M |
| 85 | 85 | ||
| 86 | #define MX31_AVIC_BASE_ADDR 0x68000000 | 86 | #define MX31_AVIC_BASE_ADDR 0x68000000 |
| 87 | #define MX31_AVIC_BASE_ADDR_VIRT 0xfc400000 | ||
| 88 | #define MX31_AVIC_SIZE SZ_1M | 87 | #define MX31_AVIC_SIZE SZ_1M |
| 89 | 88 | ||
| 90 | #define MX31_IPU_MEM_BASE_ADDR 0x70000000 | 89 | #define MX31_IPU_MEM_BASE_ADDR 0x70000000 |
| @@ -97,15 +96,14 @@ | |||
| 97 | #define MX31_CS3_BASE_ADDR 0xb2000000 | 96 | #define MX31_CS3_BASE_ADDR 0xb2000000 |
| 98 | 97 | ||
| 99 | #define MX31_CS4_BASE_ADDR 0xb4000000 | 98 | #define MX31_CS4_BASE_ADDR 0xb4000000 |
| 100 | #define MX31_CS4_BASE_ADDR_VIRT 0xf4000000 | 99 | #define MX31_CS4_BASE_ADDR_VIRT 0xf6000000 |
| 101 | #define MX31_CS4_SIZE SZ_32M | 100 | #define MX31_CS4_SIZE SZ_32M |
| 102 | 101 | ||
| 103 | #define MX31_CS5_BASE_ADDR 0xb6000000 | 102 | #define MX31_CS5_BASE_ADDR 0xb6000000 |
| 104 | #define MX31_CS5_BASE_ADDR_VIRT 0xf6000000 | 103 | #define MX31_CS5_BASE_ADDR_VIRT 0xf8000000 |
| 105 | #define MX31_CS5_SIZE SZ_32M | 104 | #define MX31_CS5_SIZE SZ_32M |
| 106 | 105 | ||
| 107 | #define MX31_X_MEMC_BASE_ADDR 0xb8000000 | 106 | #define MX31_X_MEMC_BASE_ADDR 0xb8000000 |
| 108 | #define MX31_X_MEMC_BASE_ADDR_VIRT 0xfc320000 | ||
| 109 | #define MX31_X_MEMC_SIZE SZ_64K | 107 | #define MX31_X_MEMC_SIZE SZ_64K |
| 110 | #define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000) | 108 | #define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000) |
| 111 | #define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000) | 109 | #define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000) |
| @@ -121,12 +119,8 @@ | |||
| 121 | 119 | ||
| 122 | #define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000 | 120 | #define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000 |
| 123 | 121 | ||
| 124 | #define MX31_IO_ADDRESS(x) ( \ | 122 | #define MX31_IO_P2V(x) IMX_IO_P2V(x) |
| 125 | IMX_IO_ADDRESS(x, MX31_AIPS1) ?: \ | 123 | #define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x)) |
| 126 | IMX_IO_ADDRESS(x, MX31_AIPS2) ?: \ | ||
| 127 | IMX_IO_ADDRESS(x, MX31_AVIC) ?: \ | ||
| 128 | IMX_IO_ADDRESS(x, MX31_X_MEMC) ?: \ | ||
| 129 | IMX_IO_ADDRESS(x, MX31_SPBA0)) | ||
| 130 | 124 | ||
| 131 | #ifndef __ASSEMBLER__ | 125 | #ifndef __ASSEMBLER__ |
| 132 | static inline void mx31_setup_weimcs(size_t cs, | 126 | static inline void mx31_setup_weimcs(size_t cs, |
| @@ -143,8 +137,8 @@ static inline void mx31_setup_weimcs(size_t cs, | |||
| 143 | #define MX31_INT_MPEG4_ENCODER 5 | 137 | #define MX31_INT_MPEG4_ENCODER 5 |
| 144 | #define MX31_INT_RTIC 6 | 138 | #define MX31_INT_RTIC 6 |
| 145 | #define MX31_INT_FIRI 7 | 139 | #define MX31_INT_FIRI 7 |
| 146 | #define MX31_INT_MMC_SDHC2 8 | 140 | #define MX31_INT_SDHC2 8 |
| 147 | #define MX31_INT_MMC_SDHC1 9 | 141 | #define MX31_INT_SDHC1 9 |
| 148 | #define MX31_INT_I2C1 10 | 142 | #define MX31_INT_I2C1 10 |
| 149 | #define MX31_INT_SSI2 11 | 143 | #define MX31_INT_SSI2 11 |
| 150 | #define MX31_INT_SSI1 12 | 144 | #define MX31_INT_SSI1 12 |
| @@ -170,10 +164,9 @@ static inline void mx31_setup_weimcs(size_t cs, | |||
| 170 | #define MX31_INT_UART2 32 | 164 | #define MX31_INT_UART2 32 |
| 171 | #define MX31_INT_NFC 33 | 165 | #define MX31_INT_NFC 33 |
| 172 | #define MX31_INT_SDMA 34 | 166 | #define MX31_INT_SDMA 34 |
| 173 | #define MX31_INT_USB1 35 | 167 | #define MX31_INT_USB_HS1 35 |
| 174 | #define MX31_INT_USB2 36 | 168 | #define MX31_INT_USB_HS2 36 |
| 175 | #define MX31_INT_USB3 37 | 169 | #define MX31_INT_USB_OTG 37 |
| 176 | #define MX31_INT_USB4 38 | ||
| 177 | #define MX31_INT_MSHC1 39 | 170 | #define MX31_INT_MSHC1 39 |
| 178 | #define MX31_INT_MSHC2 40 | 171 | #define MX31_INT_MSHC2 40 |
| 179 | #define MX31_INT_IPU_ERR 41 | 172 | #define MX31_INT_IPU_ERR 41 |
| @@ -197,6 +190,8 @@ static inline void mx31_setup_weimcs(size_t cs, | |||
| 197 | #define MX31_INT_EXT_WDOG 62 | 190 | #define MX31_INT_EXT_WDOG 62 |
| 198 | #define MX31_INT_EXT_TV 63 | 191 | #define MX31_INT_EXT_TV 63 |
| 199 | 192 | ||
| 193 | #define MX31_DMA_REQ_SDHC1 20 | ||
| 194 | #define MX31_DMA_REQ_SDHC2 21 | ||
| 200 | #define MX31_DMA_REQ_SSI2_RX1 22 | 195 | #define MX31_DMA_REQ_SSI2_RX1 22 |
| 201 | #define MX31_DMA_REQ_SSI2_TX1 23 | 196 | #define MX31_DMA_REQ_SSI2_TX1 23 |
| 202 | #define MX31_DMA_REQ_SSI2_RX0 24 | 197 | #define MX31_DMA_REQ_SSI2_RX0 24 |
| @@ -208,52 +203,4 @@ static inline void mx31_setup_weimcs(size_t cs, | |||
| 208 | 203 | ||
| 209 | #define MX31_PROD_SIGNATURE 0x1 /* For MX31 */ | 204 | #define MX31_PROD_SIGNATURE 0x1 /* For MX31 */ |
| 210 | 205 | ||
| 211 | /* silicon revisions specific to i.MX31 */ | ||
| 212 | #define MX31_CHIP_REV_1_0 0x10 | ||
| 213 | #define MX31_CHIP_REV_1_1 0x11 | ||
| 214 | #define MX31_CHIP_REV_1_2 0x12 | ||
| 215 | #define MX31_CHIP_REV_1_3 0x13 | ||
| 216 | #define MX31_CHIP_REV_2_0 0x20 | ||
| 217 | #define MX31_CHIP_REV_2_1 0x21 | ||
| 218 | #define MX31_CHIP_REV_2_2 0x22 | ||
| 219 | #define MX31_CHIP_REV_2_3 0x23 | ||
| 220 | #define MX31_CHIP_REV_3_0 0x30 | ||
| 221 | #define MX31_CHIP_REV_3_1 0x31 | ||
| 222 | #define MX31_CHIP_REV_3_2 0x32 | ||
| 223 | |||
| 224 | #define MX31_SYSTEM_REV_MIN MX31_CHIP_REV_1_0 | ||
| 225 | #define MX31_SYSTEM_REV_NUM 3 | ||
| 226 | |||
| 227 | #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS | ||
| 228 | /* these should go away */ | ||
| 229 | #define ATA_BASE_ADDR MX31_ATA_BASE_ADDR | ||
| 230 | #define UART4_BASE_ADDR MX31_UART4_BASE_ADDR | ||
| 231 | #define UART5_BASE_ADDR MX31_UART5_BASE_ADDR | ||
| 232 | #define MMC_SDHC1_BASE_ADDR MX31_MMC_SDHC1_BASE_ADDR | ||
| 233 | #define MMC_SDHC2_BASE_ADDR MX31_MMC_SDHC2_BASE_ADDR | ||
| 234 | #define SIM1_BASE_ADDR MX31_SIM1_BASE_ADDR | ||
| 235 | #define IIM_BASE_ADDR MX31_IIM_BASE_ADDR | ||
| 236 | #define CSPI3_BASE_ADDR MX31_CSPI3_BASE_ADDR | ||
| 237 | #define FIRI_BASE_ADDR MX31_FIRI_BASE_ADDR | ||
| 238 | #define SCM_BASE_ADDR MX31_SCM_BASE_ADDR | ||
| 239 | #define SMN_BASE_ADDR MX31_SMN_BASE_ADDR | ||
| 240 | #define MPEG4_ENC_BASE_ADDR MX31_MPEG4_ENC_BASE_ADDR | ||
| 241 | #define MXC_INT_MPEG4_ENCODER MX31_INT_MPEG4_ENCODER | ||
| 242 | #define MXC_INT_FIRI MX31_INT_FIRI | ||
| 243 | #define MXC_INT_MBX MX31_INT_MBX | ||
| 244 | #define MXC_INT_CSPI3 MX31_INT_CSPI3 | ||
| 245 | #define MXC_INT_SIM2 MX31_INT_SIM2 | ||
| 246 | #define MXC_INT_SIM1 MX31_INT_SIM1 | ||
| 247 | #define MXC_INT_CCM_DVFS MX31_INT_CCM_DVFS | ||
| 248 | #define MXC_INT_USB1 MX31_INT_USB1 | ||
| 249 | #define MXC_INT_USB2 MX31_INT_USB2 | ||
| 250 | #define MXC_INT_USB3 MX31_INT_USB3 | ||
| 251 | #define MXC_INT_USB4 MX31_INT_USB4 | ||
| 252 | #define MXC_INT_MSHC2 MX31_INT_MSHC2 | ||
| 253 | #define MXC_INT_UART4 MX31_INT_UART4 | ||
| 254 | #define MXC_INT_UART5 MX31_INT_UART5 | ||
| 255 | #define MXC_INT_CCM MX31_INT_CCM | ||
| 256 | #define MXC_INT_PCMCIA MX31_INT_PCMCIA | ||
| 257 | #endif | ||
| 258 | |||
| 259 | #endif /* ifndef __MACH_MX31_H__ */ | 206 | #endif /* ifndef __MACH_MX31_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h index 6267cff6035d..d13dbfeef08a 100644 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ b/arch/arm/plat-mxc/include/mach/mx35.h | |||
| @@ -11,7 +11,6 @@ | |||
| 11 | #define MX35_L2CC_SIZE SZ_1M | 11 | #define MX35_L2CC_SIZE SZ_1M |
| 12 | 12 | ||
| 13 | #define MX35_AIPS1_BASE_ADDR 0x43f00000 | 13 | #define MX35_AIPS1_BASE_ADDR 0x43f00000 |
| 14 | #define MX35_AIPS1_BASE_ADDR_VIRT 0xfc000000 | ||
| 15 | #define MX35_AIPS1_SIZE SZ_1M | 14 | #define MX35_AIPS1_SIZE SZ_1M |
| 16 | #define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000) | 15 | #define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000) |
| 17 | #define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000) | 16 | #define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000) |
| @@ -33,7 +32,6 @@ | |||
| 33 | #define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000) | 32 | #define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000) |
| 34 | 33 | ||
| 35 | #define MX35_SPBA0_BASE_ADDR 0x50000000 | 34 | #define MX35_SPBA0_BASE_ADDR 0x50000000 |
| 36 | #define MX35_SPBA0_BASE_ADDR_VIRT 0xfc100000 | ||
| 37 | #define MX35_SPBA0_SIZE SZ_1M | 35 | #define MX35_SPBA0_SIZE SZ_1M |
| 38 | #define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000) | 36 | #define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000) |
| 39 | #define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000) | 37 | #define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000) |
| @@ -44,7 +42,6 @@ | |||
| 44 | #define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000) | 42 | #define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000) |
| 45 | 43 | ||
| 46 | #define MX35_AIPS2_BASE_ADDR 0x53f00000 | 44 | #define MX35_AIPS2_BASE_ADDR 0x53f00000 |
| 47 | #define MX35_AIPS2_BASE_ADDR_VIRT 0xfc200000 | ||
| 48 | #define MX35_AIPS2_SIZE SZ_1M | 45 | #define MX35_AIPS2_SIZE SZ_1M |
| 49 | #define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000) | 46 | #define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000) |
| 50 | #define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000) | 47 | #define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000) |
| @@ -68,15 +65,19 @@ | |||
| 68 | #define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000) | 65 | #define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000) |
| 69 | #define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000) | 66 | #define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000) |
| 70 | #define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000) | 67 | #define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000) |
| 71 | 68 | #define MX35_USB_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf4000) | |
| 72 | #define MX35_OTG_BASE_ADDR 0x53ff4000 | 69 | #define MX35_USB_OTG_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0000) |
| 70 | /* | ||
| 71 | * The Reference Manual (IMX35RM, Rev. 2, 3/2009) claims an offset of 0x200 for | ||
| 72 | * HS. When host support was implemented only a preliminary document was | ||
| 73 | * available, which told 0x400. This works fine. | ||
| 74 | */ | ||
| 75 | #define MX35_USB_HS_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0400) | ||
| 73 | 76 | ||
| 74 | #define MX35_ROMP_BASE_ADDR 0x60000000 | 77 | #define MX35_ROMP_BASE_ADDR 0x60000000 |
| 75 | #define MX35_ROMP_BASE_ADDR_VIRT 0xfc500000 | ||
| 76 | #define MX35_ROMP_SIZE SZ_1M | 78 | #define MX35_ROMP_SIZE SZ_1M |
| 77 | 79 | ||
| 78 | #define MX35_AVIC_BASE_ADDR 0x68000000 | 80 | #define MX35_AVIC_BASE_ADDR 0x68000000 |
| 79 | #define MX35_AVIC_BASE_ADDR_VIRT 0xfc400000 | ||
| 80 | #define MX35_AVIC_SIZE SZ_1M | 81 | #define MX35_AVIC_SIZE SZ_1M |
| 81 | 82 | ||
| 82 | /* | 83 | /* |
| @@ -92,18 +93,17 @@ | |||
| 92 | #define MX35_CS3_BASE_ADDR 0xb2000000 | 93 | #define MX35_CS3_BASE_ADDR 0xb2000000 |
| 93 | 94 | ||
| 94 | #define MX35_CS4_BASE_ADDR 0xb4000000 | 95 | #define MX35_CS4_BASE_ADDR 0xb4000000 |
| 95 | #define MX35_CS4_BASE_ADDR_VIRT 0xf4000000 | 96 | #define MX35_CS4_BASE_ADDR_VIRT 0xf6000000 |
| 96 | #define MX35_CS4_SIZE SZ_32M | 97 | #define MX35_CS4_SIZE SZ_32M |
| 97 | 98 | ||
| 98 | #define MX35_CS5_BASE_ADDR 0xb6000000 | 99 | #define MX35_CS5_BASE_ADDR 0xb6000000 |
| 99 | #define MX35_CS5_BASE_ADDR_VIRT 0xf6000000 | 100 | #define MX35_CS5_BASE_ADDR_VIRT 0xf8000000 |
| 100 | #define MX35_CS5_SIZE SZ_32M | 101 | #define MX35_CS5_SIZE SZ_32M |
| 101 | 102 | ||
| 102 | /* | 103 | /* |
| 103 | * NAND, SDRAM, WEIM, M3IF, EMI controllers | 104 | * NAND, SDRAM, WEIM, M3IF, EMI controllers |
| 104 | */ | 105 | */ |
| 105 | #define MX35_X_MEMC_BASE_ADDR 0xb8000000 | 106 | #define MX35_X_MEMC_BASE_ADDR 0xb8000000 |
| 106 | #define MX35_X_MEMC_BASE_ADDR_VIRT 0xfc320000 | ||
| 107 | #define MX35_X_MEMC_SIZE SZ_64K | 107 | #define MX35_X_MEMC_SIZE SZ_64K |
| 108 | #define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000) | 108 | #define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000) |
| 109 | #define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000) | 109 | #define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000) |
| @@ -114,12 +114,8 @@ | |||
| 114 | #define MX35_NFC_BASE_ADDR 0xbb000000 | 114 | #define MX35_NFC_BASE_ADDR 0xbb000000 |
| 115 | #define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000 | 115 | #define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000 |
| 116 | 116 | ||
| 117 | #define MX35_IO_ADDRESS(x) ( \ | 117 | #define MX35_IO_P2V(x) IMX_IO_P2V(x) |
| 118 | IMX_IO_ADDRESS(x, MX35_AIPS1) ?: \ | 118 | #define MX35_IO_ADDRESS(x) IOMEM(MX35_IO_P2V(x)) |
| 119 | IMX_IO_ADDRESS(x, MX35_AIPS2) ?: \ | ||
| 120 | IMX_IO_ADDRESS(x, MX35_AVIC) ?: \ | ||
| 121 | IMX_IO_ADDRESS(x, MX35_X_MEMC) ?: \ | ||
| 122 | IMX_IO_ADDRESS(x, MX35_SPBA0)) | ||
| 123 | 119 | ||
| 124 | /* | 120 | /* |
| 125 | * Interrupt numbers | 121 | * Interrupt numbers |
| @@ -153,8 +149,8 @@ | |||
| 153 | #define MX35_INT_UART2 32 | 149 | #define MX35_INT_UART2 32 |
| 154 | #define MX35_INT_NFC 33 | 150 | #define MX35_INT_NFC 33 |
| 155 | #define MX35_INT_SDMA 34 | 151 | #define MX35_INT_SDMA 34 |
| 156 | #define MX35_INT_USBHS 35 | 152 | #define MX35_INT_USB_HS 35 |
| 157 | #define MX35_INT_USBOTG 37 | 153 | #define MX35_INT_USB_OTG 37 |
| 158 | #define MX35_INT_MSHC1 39 | 154 | #define MX35_INT_MSHC1 39 |
| 159 | #define MX35_INT_ESAI 40 | 155 | #define MX35_INT_ESAI 40 |
| 160 | #define MX35_INT_IPU_ERR 41 | 156 | #define MX35_INT_IPU_ERR 41 |
| @@ -190,23 +186,4 @@ | |||
| 190 | 186 | ||
| 191 | #define MX35_PROD_SIGNATURE 0x1 /* For MX31 */ | 187 | #define MX35_PROD_SIGNATURE 0x1 /* For MX31 */ |
| 192 | 188 | ||
| 193 | #define MX35_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0 | ||
| 194 | #define MX35_SYSTEM_REV_NUM 3 | ||
| 195 | |||
| 196 | #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS | ||
| 197 | /* these should go away */ | ||
| 198 | #define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR | ||
| 199 | #define MXC_INT_OWIRE MX35_INT_OWIRE | ||
| 200 | #define MXC_INT_GPU2D MX35_INT_GPU2D | ||
| 201 | #define MXC_INT_ASRC MX35_INT_ASRC | ||
| 202 | #define MXC_INT_USBHS MX35_INT_USBHS | ||
| 203 | #define MXC_INT_USBOTG MX35_INT_USBOTG | ||
| 204 | #define MXC_INT_ESAI MX35_INT_ESAI | ||
| 205 | #define MXC_INT_CAN1 MX35_INT_CAN1 | ||
| 206 | #define MXC_INT_CAN2 MX35_INT_CAN2 | ||
| 207 | #define MXC_INT_MLB MX35_INT_MLB | ||
| 208 | #define MXC_INT_SPDIF MX35_INT_SPDIF | ||
| 209 | #define MXC_INT_FEC MX35_INT_FEC | ||
| 210 | #endif | ||
| 211 | |||
| 212 | #endif /* ifndef __MACH_MX35_H__ */ | 189 | #endif /* ifndef __MACH_MX35_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h index d1bd26d7b8a6..388a407d72d6 100644 --- a/arch/arm/plat-mxc/include/mach/mx3x.h +++ b/arch/arm/plat-mxc/include/mach/mx3x.h | |||
| @@ -44,7 +44,6 @@ | |||
| 44 | * AIPS 1 | 44 | * AIPS 1 |
| 45 | */ | 45 | */ |
| 46 | #define MX3x_AIPS1_BASE_ADDR 0x43f00000 | 46 | #define MX3x_AIPS1_BASE_ADDR 0x43f00000 |
| 47 | #define MX3x_AIPS1_BASE_ADDR_VIRT 0xfc000000 | ||
| 48 | #define MX3x_AIPS1_SIZE SZ_1M | 47 | #define MX3x_AIPS1_SIZE SZ_1M |
| 49 | #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000) | 48 | #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000) |
| 50 | #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000) | 49 | #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000) |
| @@ -69,7 +68,6 @@ | |||
| 69 | * SPBA global module enabled #0 | 68 | * SPBA global module enabled #0 |
| 70 | */ | 69 | */ |
| 71 | #define MX3x_SPBA0_BASE_ADDR 0x50000000 | 70 | #define MX3x_SPBA0_BASE_ADDR 0x50000000 |
| 72 | #define MX3x_SPBA0_BASE_ADDR_VIRT 0xfc100000 | ||
| 73 | #define MX3x_SPBA0_SIZE SZ_1M | 71 | #define MX3x_SPBA0_SIZE SZ_1M |
| 74 | #define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000) | 72 | #define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000) |
| 75 | #define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000) | 73 | #define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000) |
| @@ -82,7 +80,6 @@ | |||
| 82 | * AIPS 2 | 80 | * AIPS 2 |
| 83 | */ | 81 | */ |
| 84 | #define MX3x_AIPS2_BASE_ADDR 0x53f00000 | 82 | #define MX3x_AIPS2_BASE_ADDR 0x53f00000 |
| 85 | #define MX3x_AIPS2_BASE_ADDR_VIRT 0xfc200000 | ||
| 86 | #define MX3x_AIPS2_SIZE SZ_1M | 83 | #define MX3x_AIPS2_SIZE SZ_1M |
| 87 | #define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000) | 84 | #define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000) |
| 88 | #define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000) | 85 | #define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000) |
| @@ -105,11 +102,9 @@ | |||
| 105 | * ROMP and AVIC | 102 | * ROMP and AVIC |
| 106 | */ | 103 | */ |
| 107 | #define MX3x_ROMP_BASE_ADDR 0x60000000 | 104 | #define MX3x_ROMP_BASE_ADDR 0x60000000 |
| 108 | #define MX3x_ROMP_BASE_ADDR_VIRT 0xfc500000 | ||
| 109 | #define MX3x_ROMP_SIZE SZ_1M | 105 | #define MX3x_ROMP_SIZE SZ_1M |
| 110 | 106 | ||
| 111 | #define MX3x_AVIC_BASE_ADDR 0x68000000 | 107 | #define MX3x_AVIC_BASE_ADDR 0x68000000 |
| 112 | #define MX3x_AVIC_BASE_ADDR_VIRT 0xfc400000 | ||
| 113 | #define MX3x_AVIC_SIZE SZ_1M | 108 | #define MX3x_AVIC_SIZE SZ_1M |
| 114 | 109 | ||
| 115 | /* | 110 | /* |
| @@ -125,18 +120,17 @@ | |||
| 125 | #define MX3x_CS3_BASE_ADDR 0xb2000000 | 120 | #define MX3x_CS3_BASE_ADDR 0xb2000000 |
| 126 | 121 | ||
| 127 | #define MX3x_CS4_BASE_ADDR 0xb4000000 | 122 | #define MX3x_CS4_BASE_ADDR 0xb4000000 |
| 128 | #define MX3x_CS4_BASE_ADDR_VIRT 0xf4000000 | 123 | #define MX3x_CS4_BASE_ADDR_VIRT 0xf6000000 |
| 129 | #define MX3x_CS4_SIZE SZ_32M | 124 | #define MX3x_CS4_SIZE SZ_32M |
| 130 | 125 | ||
| 131 | #define MX3x_CS5_BASE_ADDR 0xb6000000 | 126 | #define MX3x_CS5_BASE_ADDR 0xb6000000 |
| 132 | #define MX3x_CS5_BASE_ADDR_VIRT 0xf6000000 | 127 | #define MX3x_CS5_BASE_ADDR_VIRT 0xf8000000 |
| 133 | #define MX3x_CS5_SIZE SZ_32M | 128 | #define MX3x_CS5_SIZE SZ_32M |
| 134 | 129 | ||
| 135 | /* | 130 | /* |
| 136 | * NAND, SDRAM, WEIM, M3IF, EMI controllers | 131 | * NAND, SDRAM, WEIM, M3IF, EMI controllers |
| 137 | */ | 132 | */ |
| 138 | #define MX3x_X_MEMC_BASE_ADDR 0xb8000000 | 133 | #define MX3x_X_MEMC_BASE_ADDR 0xb8000000 |
| 139 | #define MX3x_X_MEMC_BASE_ADDR_VIRT 0xfc320000 | ||
| 140 | #define MX3x_X_MEMC_SIZE SZ_64K | 134 | #define MX3x_X_MEMC_SIZE SZ_64K |
| 141 | #define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000) | 135 | #define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000) |
| 142 | #define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000) | 136 | #define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000) |
| @@ -146,56 +140,6 @@ | |||
| 146 | 140 | ||
| 147 | #define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000 | 141 | #define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000 |
| 148 | 142 | ||
| 149 | /*! | ||
| 150 | * This macro defines the physical to virtual address mapping for all the | ||
| 151 | * peripheral modules. It is used by passing in the physical address as x | ||
| 152 | * and returning the virtual address. If the physical address is not mapped, | ||
| 153 | * it returns 0xDEADBEEF | ||
| 154 | */ | ||
| 155 | #define IO_ADDRESS(x) \ | ||
| 156 | (void __force __iomem *) \ | ||
| 157 | (((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\ | ||
| 158 | ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\ | ||
| 159 | ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\ | ||
| 160 | ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\ | ||
| 161 | ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\ | ||
| 162 | ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\ | ||
| 163 | ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\ | ||
| 164 | 0xDEADBEEF) | ||
| 165 | |||
| 166 | /* | ||
| 167 | * define the address mapping macros: in physical address order | ||
| 168 | */ | ||
| 169 | #define L2CC_IO_ADDRESS(x) \ | ||
| 170 | (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT) | ||
| 171 | |||
| 172 | #define AIPS1_IO_ADDRESS(x) \ | ||
| 173 | (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT) | ||
| 174 | |||
| 175 | #define SPBA0_IO_ADDRESS(x) \ | ||
| 176 | (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT) | ||
| 177 | |||
| 178 | #define AIPS2_IO_ADDRESS(x) \ | ||
| 179 | (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT) | ||
| 180 | |||
| 181 | #define ROMP_IO_ADDRESS(x) \ | ||
| 182 | (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT) | ||
| 183 | |||
| 184 | #define AVIC_IO_ADDRESS(x) \ | ||
| 185 | (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT) | ||
| 186 | |||
| 187 | #define CS4_IO_ADDRESS(x) \ | ||
| 188 | (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT) | ||
| 189 | |||
| 190 | #define CS5_IO_ADDRESS(x) \ | ||
| 191 | (((x) - CS5_BASE_ADDR) + CS5_BASE_ADDR_VIRT) | ||
| 192 | |||
| 193 | #define X_MEMC_IO_ADDRESS(x) \ | ||
| 194 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) | ||
| 195 | |||
| 196 | #define PCMCIA_IO_ADDRESS(x) \ | ||
| 197 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) | ||
| 198 | |||
| 199 | /* | 143 | /* |
| 200 | * Interrupt numbers | 144 | * Interrupt numbers |
| 201 | */ | 145 | */ |
| @@ -240,22 +184,6 @@ | |||
| 240 | 184 | ||
| 241 | #define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */ | 185 | #define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */ |
| 242 | 186 | ||
| 243 | /* silicon revisions specific to i.MX31 and i.MX35 */ | ||
| 244 | #define MX3x_CHIP_REV_1_0 0x10 | ||
| 245 | #define MX3x_CHIP_REV_1_1 0x11 | ||
| 246 | #define MX3x_CHIP_REV_1_2 0x12 | ||
| 247 | #define MX3x_CHIP_REV_1_3 0x13 | ||
| 248 | #define MX3x_CHIP_REV_2_0 0x20 | ||
| 249 | #define MX3x_CHIP_REV_2_1 0x21 | ||
| 250 | #define MX3x_CHIP_REV_2_2 0x22 | ||
| 251 | #define MX3x_CHIP_REV_2_3 0x23 | ||
| 252 | #define MX3x_CHIP_REV_3_0 0x30 | ||
| 253 | #define MX3x_CHIP_REV_3_1 0x31 | ||
| 254 | #define MX3x_CHIP_REV_3_2 0x32 | ||
| 255 | |||
| 256 | #define MX3x_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0 | ||
| 257 | #define MX3x_SYSTEM_REV_NUM 3 | ||
| 258 | |||
| 259 | /* Mandatory defines used globally */ | 187 | /* Mandatory defines used globally */ |
| 260 | 188 | ||
| 261 | #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) | 189 | #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) |
| @@ -277,126 +205,4 @@ static inline int mx35_revision(void) | |||
| 277 | } | 205 | } |
| 278 | #endif | 206 | #endif |
| 279 | 207 | ||
| 280 | #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS | ||
| 281 | /* these should go away */ | ||
| 282 | #define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR | ||
| 283 | #define L2CC_SIZE MX3x_L2CC_SIZE | ||
| 284 | #define AIPS1_BASE_ADDR MX3x_AIPS1_BASE_ADDR | ||
| 285 | #define AIPS1_BASE_ADDR_VIRT MX3x_AIPS1_BASE_ADDR_VIRT | ||
| 286 | #define AIPS1_SIZE MX3x_AIPS1_SIZE | ||
| 287 | #define MAX_BASE_ADDR MX3x_MAX_BASE_ADDR | ||
| 288 | #define EVTMON_BASE_ADDR MX3x_EVTMON_BASE_ADDR | ||
| 289 | #define CLKCTL_BASE_ADDR MX3x_CLKCTL_BASE_ADDR | ||
| 290 | #define ETB_SLOT4_BASE_ADDR MX3x_ETB_SLOT4_BASE_ADDR | ||
| 291 | #define ETB_SLOT5_BASE_ADDR MX3x_ETB_SLOT5_BASE_ADDR | ||
| 292 | #define ECT_CTIO_BASE_ADDR MX3x_ECT_CTIO_BASE_ADDR | ||
| 293 | #define I2C_BASE_ADDR MX3x_I2C_BASE_ADDR | ||
| 294 | #define I2C3_BASE_ADDR MX3x_I2C3_BASE_ADDR | ||
| 295 | #define UART1_BASE_ADDR MX3x_UART1_BASE_ADDR | ||
| 296 | #define UART2_BASE_ADDR MX3x_UART2_BASE_ADDR | ||
| 297 | #define I2C2_BASE_ADDR MX3x_I2C2_BASE_ADDR | ||
| 298 | #define OWIRE_BASE_ADDR MX3x_OWIRE_BASE_ADDR | ||
| 299 | #define SSI1_BASE_ADDR MX3x_SSI1_BASE_ADDR | ||
| 300 | #define CSPI1_BASE_ADDR MX3x_CSPI1_BASE_ADDR | ||
| 301 | #define KPP_BASE_ADDR MX3x_KPP_BASE_ADDR | ||
| 302 | #define IOMUXC_BASE_ADDR MX3x_IOMUXC_BASE_ADDR | ||
| 303 | #define ECT_IP1_BASE_ADDR MX3x_ECT_IP1_BASE_ADDR | ||
| 304 | #define ECT_IP2_BASE_ADDR MX3x_ECT_IP2_BASE_ADDR | ||
| 305 | #define SPBA0_BASE_ADDR MX3x_SPBA0_BASE_ADDR | ||
| 306 | #define SPBA0_BASE_ADDR_VIRT MX3x_SPBA0_BASE_ADDR_VIRT | ||
| 307 | #define SPBA0_SIZE MX3x_SPBA0_SIZE | ||
| 308 | #define UART3_BASE_ADDR MX3x_UART3_BASE_ADDR | ||
| 309 | #define CSPI2_BASE_ADDR MX3x_CSPI2_BASE_ADDR | ||
| 310 | #define SSI2_BASE_ADDR MX3x_SSI2_BASE_ADDR | ||
| 311 | #define ATA_DMA_BASE_ADDR MX3x_ATA_DMA_BASE_ADDR | ||
| 312 | #define MSHC1_BASE_ADDR MX3x_MSHC1_BASE_ADDR | ||
| 313 | #define SPBA_CTRL_BASE_ADDR MX3x_SPBA_CTRL_BASE_ADDR | ||
| 314 | #define AIPS2_BASE_ADDR MX3x_AIPS2_BASE_ADDR | ||
| 315 | #define AIPS2_BASE_ADDR_VIRT MX3x_AIPS2_BASE_ADDR_VIRT | ||
| 316 | #define AIPS2_SIZE MX3x_AIPS2_SIZE | ||
| 317 | #define CCM_BASE_ADDR MX3x_CCM_BASE_ADDR | ||
| 318 | #define GPT1_BASE_ADDR MX3x_GPT1_BASE_ADDR | ||
| 319 | #define EPIT1_BASE_ADDR MX3x_EPIT1_BASE_ADDR | ||
| 320 | #define EPIT2_BASE_ADDR MX3x_EPIT2_BASE_ADDR | ||
| 321 | #define GPIO3_BASE_ADDR MX3x_GPIO3_BASE_ADDR | ||
| 322 | #define SCC_BASE_ADDR MX3x_SCC_BASE_ADDR | ||
| 323 | #define RNGA_BASE_ADDR MX3x_RNGA_BASE_ADDR | ||
| 324 | #define IPU_CTRL_BASE_ADDR MX3x_IPU_CTRL_BASE_ADDR | ||
| 325 | #define AUDMUX_BASE_ADDR MX3x_AUDMUX_BASE_ADDR | ||
| 326 | #define GPIO1_BASE_ADDR MX3x_GPIO1_BASE_ADDR | ||
| 327 | #define GPIO2_BASE_ADDR MX3x_GPIO2_BASE_ADDR | ||
| 328 | #define SDMA_BASE_ADDR MX3x_SDMA_BASE_ADDR | ||
| 329 | #define RTC_BASE_ADDR MX3x_RTC_BASE_ADDR | ||
| 330 | #define WDOG_BASE_ADDR MX3x_WDOG_BASE_ADDR | ||
| 331 | #define PWM_BASE_ADDR MX3x_PWM_BASE_ADDR | ||
| 332 | #define RTIC_BASE_ADDR MX3x_RTIC_BASE_ADDR | ||
| 333 | #define ROMP_BASE_ADDR MX3x_ROMP_BASE_ADDR | ||
| 334 | #define ROMP_BASE_ADDR_VIRT MX3x_ROMP_BASE_ADDR_VIRT | ||
| 335 | #define ROMP_SIZE MX3x_ROMP_SIZE | ||
| 336 | #define AVIC_BASE_ADDR MX3x_AVIC_BASE_ADDR | ||
| 337 | #define AVIC_BASE_ADDR_VIRT MX3x_AVIC_BASE_ADDR_VIRT | ||
| 338 | #define AVIC_SIZE MX3x_AVIC_SIZE | ||
| 339 | #define IPU_MEM_BASE_ADDR MX3x_IPU_MEM_BASE_ADDR | ||
| 340 | #define CSD0_BASE_ADDR MX3x_CSD0_BASE_ADDR | ||
| 341 | #define CSD1_BASE_ADDR MX3x_CSD1_BASE_ADDR | ||
| 342 | #define CS0_BASE_ADDR MX3x_CS0_BASE_ADDR | ||
| 343 | #define CS1_BASE_ADDR MX3x_CS1_BASE_ADDR | ||
| 344 | #define CS2_BASE_ADDR MX3x_CS2_BASE_ADDR | ||
| 345 | #define CS3_BASE_ADDR MX3x_CS3_BASE_ADDR | ||
| 346 | #define CS4_BASE_ADDR MX3x_CS4_BASE_ADDR | ||
| 347 | #define CS4_BASE_ADDR_VIRT MX3x_CS4_BASE_ADDR_VIRT | ||
| 348 | #define CS4_SIZE MX3x_CS4_SIZE | ||
| 349 | #define CS5_BASE_ADDR MX3x_CS5_BASE_ADDR | ||
| 350 | #define CS5_BASE_ADDR_VIRT MX3x_CS5_BASE_ADDR_VIRT | ||
| 351 | #define CS5_SIZE MX3x_CS5_SIZE | ||
| 352 | #define X_MEMC_BASE_ADDR MX3x_X_MEMC_BASE_ADDR | ||
| 353 | #define X_MEMC_BASE_ADDR_VIRT MX3x_X_MEMC_BASE_ADDR_VIRT | ||
| 354 | #define X_MEMC_SIZE MX3x_X_MEMC_SIZE | ||
| 355 | #define ESDCTL_BASE_ADDR MX3x_ESDCTL_BASE_ADDR | ||
| 356 | #define WEIM_BASE_ADDR MX3x_WEIM_BASE_ADDR | ||
| 357 | #define M3IF_BASE_ADDR MX3x_M3IF_BASE_ADDR | ||
| 358 | #define EMI_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR | ||
| 359 | #define PCMCIA_CTL_BASE_ADDR MX3x_PCMCIA_CTL_BASE_ADDR | ||
| 360 | #define PCMCIA_MEM_BASE_ADDR MX3x_PCMCIA_MEM_BASE_ADDR | ||
| 361 | #define MXC_INT_I2C3 MX3x_INT_I2C3 | ||
| 362 | #define MXC_INT_I2C2 MX3x_INT_I2C2 | ||
| 363 | #define MXC_INT_RTIC MX3x_INT_RTIC | ||
| 364 | #define MXC_INT_I2C MX3x_INT_I2C | ||
| 365 | #define MXC_INT_CSPI2 MX3x_INT_CSPI2 | ||
| 366 | #define MXC_INT_CSPI1 MX3x_INT_CSPI1 | ||
| 367 | #define MXC_INT_ATA MX3x_INT_ATA | ||
| 368 | #define MXC_INT_UART3 MX3x_INT_UART3 | ||
| 369 | #define MXC_INT_IIM MX3x_INT_IIM | ||
| 370 | #define MXC_INT_RNGA MX3x_INT_RNGA | ||
| 371 | #define MXC_INT_EVTMON MX3x_INT_EVTMON | ||
| 372 | #define MXC_INT_KPP MX3x_INT_KPP | ||
| 373 | #define MXC_INT_RTC MX3x_INT_RTC | ||
| 374 | #define MXC_INT_PWM MX3x_INT_PWM | ||
| 375 | #define MXC_INT_EPIT2 MX3x_INT_EPIT2 | ||
| 376 | #define MXC_INT_EPIT1 MX3x_INT_EPIT1 | ||
| 377 | #define MXC_INT_GPT MX3x_INT_GPT | ||
| 378 | #define MXC_INT_POWER_FAIL MX3x_INT_POWER_FAIL | ||
| 379 | #define MXC_INT_UART2 MX3x_INT_UART2 | ||
| 380 | #define MXC_INT_NANDFC MX3x_INT_NANDFC | ||
| 381 | #define MXC_INT_SDMA MX3x_INT_SDMA | ||
| 382 | #define MXC_INT_MSHC1 MX3x_INT_MSHC1 | ||
| 383 | #define MXC_INT_IPU_ERR MX3x_INT_IPU_ERR | ||
| 384 | #define MXC_INT_IPU_SYN MX3x_INT_IPU_SYN | ||
| 385 | #define MXC_INT_UART1 MX3x_INT_UART1 | ||
| 386 | #define MXC_INT_ECT MX3x_INT_ECT | ||
| 387 | #define MXC_INT_SCC_SCM MX3x_INT_SCC_SCM | ||
| 388 | #define MXC_INT_SCC_SMN MX3x_INT_SCC_SMN | ||
| 389 | #define MXC_INT_GPIO2 MX3x_INT_GPIO2 | ||
| 390 | #define MXC_INT_GPIO1 MX3x_INT_GPIO1 | ||
| 391 | #define MXC_INT_WDOG MX3x_INT_WDOG | ||
| 392 | #define MXC_INT_GPIO3 MX3x_INT_GPIO3 | ||
| 393 | #define MXC_INT_EXT_POWER MX3x_INT_EXT_POWER | ||
| 394 | #define MXC_INT_EXT_TEMPER MX3x_INT_EXT_TEMPER | ||
| 395 | #define MXC_INT_EXT_SENSOR60 MX3x_INT_EXT_SENSOR60 | ||
| 396 | #define MXC_INT_EXT_SENSOR61 MX3x_INT_EXT_SENSOR61 | ||
| 397 | #define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG | ||
| 398 | #define MXC_INT_EXT_TV MX3x_INT_EXT_TV | ||
| 399 | #define PROD_SIGNATURE MX3x_PROD_SIGNATURE | ||
| 400 | #endif | ||
| 401 | |||
| 402 | #endif /* ifndef __MACH_MX3x_H__ */ | 208 | #endif /* ifndef __MACH_MX3x_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/mx50.h b/arch/arm/plat-mxc/include/mach/mx50.h new file mode 100644 index 000000000000..aaec2a6e7b3a --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx50.h | |||
| @@ -0,0 +1,285 @@ | |||
| 1 | #ifndef __MACH_MX50_H__ | ||
| 2 | #define __MACH_MX50_H__ | ||
| 3 | |||
| 4 | /* | ||
| 5 | * IROM | ||
| 6 | */ | ||
| 7 | #define MX50_IROM_BASE_ADDR 0x0 | ||
| 8 | #define MX50_IROM_SIZE SZ_64K | ||
| 9 | |||
| 10 | /* TZIC */ | ||
| 11 | #define MX50_TZIC_BASE_ADDR 0x0fffc000 | ||
| 12 | #define MX50_TZIC_SIZE SZ_16K | ||
| 13 | |||
| 14 | /* | ||
| 15 | * IRAM | ||
| 16 | */ | ||
| 17 | #define MX50_IRAM_BASE_ADDR 0xf8000000 /* internal ram */ | ||
| 18 | #define MX50_IRAM_PARTITIONS 16 | ||
| 19 | #define MX50_IRAM_SIZE (MX50_IRAM_PARTITIONS * SZ_8K) /* 128KB */ | ||
| 20 | |||
| 21 | /* | ||
| 22 | * Databahn | ||
| 23 | */ | ||
| 24 | #define MX50_DATABAHN_BASE_ADDR 0x14000000 | ||
| 25 | |||
| 26 | /* | ||
| 27 | * Graphics Memory of GPU | ||
| 28 | */ | ||
| 29 | #define MX50_GPU2D_BASE_ADDR 0x20000000 | ||
| 30 | |||
| 31 | #define MX50_DEBUG_BASE_ADDR 0x40000000 | ||
| 32 | #define MX50_DEBUG_SIZE SZ_1M | ||
| 33 | #define MX50_ETB_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00001000) | ||
| 34 | #define MX50_ETM_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00002000) | ||
| 35 | #define MX50_TPIU_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00003000) | ||
| 36 | #define MX50_CTI0_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00004000) | ||
| 37 | #define MX50_CTI1_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00005000) | ||
| 38 | #define MX50_CTI2_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00006000) | ||
| 39 | #define MX50_CTI3_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00007000) | ||
| 40 | #define MX50_CORTEX_DBG_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00008000) | ||
| 41 | |||
| 42 | #define MX50_APBHDMA_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01000000) | ||
| 43 | #define MX50_OCOTP_CTRL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01002000) | ||
| 44 | #define MX50_DIGCTL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01004000) | ||
| 45 | #define MX50_GPMI_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01006000) | ||
| 46 | #define MX50_BCH_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01008000) | ||
| 47 | #define MX50_ELCDIF_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100a000) | ||
| 48 | #define MX50_EPXP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100c000) | ||
| 49 | #define MX50_DCP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100e000) | ||
| 50 | #define MX50_EPDC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01010000) | ||
| 51 | #define MX50_QOSC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01012000) | ||
| 52 | #define MX50_PERFMON_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01014000) | ||
| 53 | #define MX50_SSP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01016000) | ||
| 54 | #define MX50_ANATOP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01018000) | ||
| 55 | #define MX50_NIC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x08000000) | ||
| 56 | |||
| 57 | /* | ||
| 58 | * SPBA global module enabled #0 | ||
| 59 | */ | ||
| 60 | #define MX50_SPBA0_BASE_ADDR 0x50000000 | ||
| 61 | #define MX50_SPBA0_SIZE SZ_1M | ||
| 62 | |||
| 63 | #define MX50_MMC_SDHC1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00004000) | ||
| 64 | #define MX50_MMC_SDHC2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00008000) | ||
| 65 | #define MX50_UART3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x0000c000) | ||
| 66 | #define MX50_CSPI1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00010000) | ||
| 67 | #define MX50_SSI2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00014000) | ||
| 68 | #define MX50_MMC_SDHC3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00020000) | ||
| 69 | #define MX50_MMC_SDHC4_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00024000) | ||
| 70 | |||
| 71 | /* | ||
| 72 | * AIPS 1 | ||
| 73 | */ | ||
| 74 | #define MX50_AIPS1_BASE_ADDR 0x53f00000 | ||
| 75 | #define MX50_AIPS1_SIZE SZ_1M | ||
| 76 | |||
| 77 | #define MX50_OTG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00080000) | ||
| 78 | #define MX50_GPIO1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00084000) | ||
| 79 | #define MX50_GPIO2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00088000) | ||
| 80 | #define MX50_GPIO3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x0008c000) | ||
| 81 | #define MX50_GPIO4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00090000) | ||
| 82 | #define MX50_KPP_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00094000) | ||
| 83 | #define MX50_WDOG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00098000) | ||
| 84 | #define MX50_GPT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a0000) | ||
| 85 | #define MX50_SRTC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a4000) | ||
| 86 | #define MX50_IOMUXC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a8000) | ||
| 87 | #define MX50_EPIT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ac000) | ||
| 88 | #define MX50_PWM1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b4000) | ||
| 89 | #define MX50_PWM2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b8000) | ||
| 90 | #define MX50_UART1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000bc000) | ||
| 91 | #define MX50_UART2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000c0000) | ||
| 92 | #define MX50_SRC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d0000) | ||
| 93 | #define MX50_CCM_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d4000) | ||
| 94 | #define MX50_GPC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d8000) | ||
| 95 | #define MX50_GPIO5_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000dc000) | ||
| 96 | #define MX50_GPIO6_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000e0000) | ||
| 97 | #define MX50_I2C3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ec000) | ||
| 98 | #define MX50_UART4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f0000) | ||
| 99 | |||
| 100 | #define MX50_MSHC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f4000) | ||
| 101 | #define MX50_RNGB_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f8000) | ||
| 102 | |||
| 103 | /* | ||
| 104 | * AIPS 2 | ||
| 105 | */ | ||
| 106 | #define MX50_AIPS2_BASE_ADDR 0x63f00000 | ||
| 107 | #define MX50_AIPS2_SIZE SZ_1M | ||
| 108 | |||
| 109 | #define MX50_PLL1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00080000) | ||
| 110 | #define MX50_PLL2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00084000) | ||
| 111 | #define MX50_PLL3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00088000) | ||
| 112 | #define MX50_UART5_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00090000) | ||
| 113 | #define MX50_AHBMAX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00094000) | ||
| 114 | #define MX50_ARM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a0000) | ||
| 115 | #define MX50_OWIRE_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a4000) | ||
| 116 | #define MX50_CSPI2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ac000) | ||
| 117 | #define MX50_SDMA_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b0000) | ||
| 118 | #define MX50_ROMCP_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b8000) | ||
| 119 | #define MX50_CSPI3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c0000) | ||
| 120 | #define MX50_I2C2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c4000) | ||
| 121 | #define MX50_I2C1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c8000) | ||
| 122 | #define MX50_SSI1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000cc000) | ||
| 123 | #define MX50_AUDMUX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d0000) | ||
| 124 | #define MX50_WEIM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d8000) | ||
| 125 | #define MX50_FEC_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ec000) | ||
| 126 | |||
| 127 | /* | ||
| 128 | * Memory regions and CS | ||
| 129 | */ | ||
| 130 | #define MX50_CSD0_BASE_ADDR 0x70000000 | ||
| 131 | #define MX50_CSD1_BASE_ADDR 0xb0000000 | ||
| 132 | #define MX50_CS0_BASE_ADDR 0xf0000000 | ||
| 133 | |||
| 134 | #define MX50_IO_P2V(x) IMX_IO_P2V(x) | ||
| 135 | #define MX50_IO_ADDRESS(x) IOMEM(MX50_IO_P2V(x)) | ||
| 136 | |||
| 137 | /* | ||
| 138 | * defines for SPBA modules | ||
| 139 | */ | ||
| 140 | #define MX50_SPBA_SDHC1 0x04 | ||
| 141 | #define MX50_SPBA_SDHC2 0x08 | ||
| 142 | #define MX50_SPBA_UART3 0x0c | ||
| 143 | #define MX50_SPBA_CSPI1 0x10 | ||
| 144 | #define MX50_SPBA_SSI2 0x14 | ||
| 145 | #define MX50_SPBA_SDHC3 0x20 | ||
| 146 | #define MX50_SPBA_SDHC4 0x24 | ||
| 147 | #define MX50_SPBA_SPDIF 0x28 | ||
| 148 | #define MX50_SPBA_ATA 0x30 | ||
| 149 | #define MX50_SPBA_SLIM 0x34 | ||
| 150 | #define MX50_SPBA_HSI2C 0x38 | ||
| 151 | #define MX50_SPBA_CTRL 0x3c | ||
| 152 | |||
| 153 | /* | ||
| 154 | * DMA request assignments | ||
| 155 | */ | ||
| 156 | #define MX50_DMA_REQ_GPC 1 | ||
| 157 | #define MX50_DMA_REQ_ATA_UART4_RX 2 | ||
| 158 | #define MX50_DMA_REQ_ATA_UART4_TX 3 | ||
| 159 | #define MX50_DMA_REQ_CSPI1_RX 6 | ||
| 160 | #define MX50_DMA_REQ_CSPI1_TX 7 | ||
| 161 | #define MX50_DMA_REQ_CSPI2_RX 8 | ||
| 162 | #define MX50_DMA_REQ_CSPI2_TX 9 | ||
| 163 | #define MX50_DMA_REQ_I2C3_SDHC3 10 | ||
| 164 | #define MX50_DMA_REQ_SDHC4 11 | ||
| 165 | #define MX50_DMA_REQ_UART2_FIRI_RX 12 | ||
| 166 | #define MX50_DMA_REQ_UART2_FIRI_TX 13 | ||
| 167 | #define MX50_DMA_REQ_EXT0 14 | ||
| 168 | #define MX50_DMA_REQ_EXT1 15 | ||
| 169 | #define MX50_DMA_REQ_UART5_RX 16 | ||
| 170 | #define MX50_DMA_REQ_UART5_TX 17 | ||
| 171 | #define MX50_DMA_REQ_UART1_RX 18 | ||
| 172 | #define MX50_DMA_REQ_UART1_TX 19 | ||
| 173 | #define MX50_DMA_REQ_I2C1_SDHC1 20 | ||
| 174 | #define MX50_DMA_REQ_I2C2_SDHC2 21 | ||
| 175 | #define MX50_DMA_REQ_SSI2_RX2 22 | ||
| 176 | #define MX50_DMA_REQ_SSI2_TX2 23 | ||
| 177 | #define MX50_DMA_REQ_SSI2_RX1 24 | ||
| 178 | #define MX50_DMA_REQ_SSI2_TX1 25 | ||
| 179 | #define MX50_DMA_REQ_SSI1_RX2 26 | ||
| 180 | #define MX50_DMA_REQ_SSI1_TX2 27 | ||
| 181 | #define MX50_DMA_REQ_SSI1_RX1 28 | ||
| 182 | #define MX50_DMA_REQ_SSI1_TX1 29 | ||
| 183 | #define MX50_DMA_REQ_CSPI_RX 38 | ||
| 184 | #define MX50_DMA_REQ_CSPI_TX 39 | ||
| 185 | #define MX50_DMA_REQ_UART3_RX 42 | ||
| 186 | #define MX50_DMA_REQ_UART3_TX 43 | ||
| 187 | |||
| 188 | /* | ||
| 189 | * Interrupt numbers | ||
| 190 | */ | ||
| 191 | #define MX50_INT_MMC_SDHC1 1 | ||
| 192 | #define MX50_INT_MMC_SDHC2 2 | ||
| 193 | #define MX50_INT_MMC_SDHC3 3 | ||
| 194 | #define MX50_INT_MMC_SDHC4 4 | ||
| 195 | #define MX50_INT_DAP 5 | ||
| 196 | #define MX50_INT_SDMA 6 | ||
| 197 | #define MX50_INT_IOMUX 7 | ||
| 198 | #define MX50_INT_UART4 13 | ||
| 199 | #define MX50_INT_USB_H1 14 | ||
| 200 | #define MX50_INT_USB_OTG 18 | ||
| 201 | #define MX50_INT_DATABAHN 19 | ||
| 202 | #define MX50_INT_ELCDIF 20 | ||
| 203 | #define MX50_INT_EPXP 21 | ||
| 204 | #define MX50_INT_SRTC_NTZ 24 | ||
| 205 | #define MX50_INT_SRTC_TZ 25 | ||
| 206 | #define MX50_INT_EPDC 27 | ||
| 207 | #define MX50_INT_NIC 28 | ||
| 208 | #define MX50_INT_SSI1 29 | ||
| 209 | #define MX50_INT_SSI2 30 | ||
| 210 | #define MX50_INT_UART1 31 | ||
| 211 | #define MX50_INT_UART2 32 | ||
| 212 | #define MX50_INT_UART3 33 | ||
| 213 | #define MX50_INT_RESV34 34 | ||
| 214 | #define MX50_INT_RESV35 35 | ||
| 215 | #define MX50_INT_CSPI1 36 | ||
| 216 | #define MX50_INT_CSPI2 37 | ||
| 217 | #define MX50_INT_CSPI 38 | ||
| 218 | #define MX50_INT_GPT 39 | ||
| 219 | #define MX50_INT_EPIT1 40 | ||
| 220 | #define MX50_INT_GPIO1_INT7 42 | ||
| 221 | #define MX50_INT_GPIO1_INT6 43 | ||
| 222 | #define MX50_INT_GPIO1_INT5 44 | ||
| 223 | #define MX50_INT_GPIO1_INT4 45 | ||
| 224 | #define MX50_INT_GPIO1_INT3 46 | ||
| 225 | #define MX50_INT_GPIO1_INT2 47 | ||
| 226 | #define MX50_INT_GPIO1_INT1 48 | ||
| 227 | #define MX50_INT_GPIO1_INT0 49 | ||
| 228 | #define MX50_INT_GPIO1_LOW 50 | ||
| 229 | #define MX50_INT_GPIO1_HIGH 51 | ||
| 230 | #define MX50_INT_GPIO2_LOW 52 | ||
| 231 | #define MX50_INT_GPIO2_HIGH 53 | ||
| 232 | #define MX50_INT_GPIO3_LOW 54 | ||
| 233 | #define MX50_INT_GPIO3_HIGH 55 | ||
| 234 | #define MX50_INT_GPIO4_LOW 56 | ||
| 235 | #define MX50_INT_GPIO4_HIGH 57 | ||
| 236 | #define MX50_INT_WDOG1 58 | ||
| 237 | #define MX50_INT_KPP 60 | ||
| 238 | #define MX50_INT_PWM1 61 | ||
| 239 | #define MX50_INT_I2C1 62 | ||
| 240 | #define MX50_INT_I2C2 63 | ||
| 241 | #define MX50_INT_I2C3 64 | ||
| 242 | #define MX50_INT_RESV65 65 | ||
| 243 | #define MX50_INT_DCDC 66 | ||
| 244 | #define MX50_INT_THERMAL_ALARM 67 | ||
| 245 | #define MX50_INT_ANA3 68 | ||
| 246 | #define MX50_INT_ANA4 69 | ||
| 247 | #define MX50_INT_CCM1 71 | ||
| 248 | #define MX50_INT_CCM2 72 | ||
| 249 | #define MX50_INT_GPC1 73 | ||
| 250 | #define MX50_INT_GPC2 74 | ||
| 251 | #define MX50_INT_SRC 75 | ||
| 252 | #define MX50_INT_NM 76 | ||
| 253 | #define MX50_INT_PMU 77 | ||
| 254 | #define MX50_INT_CTI_IRQ 78 | ||
| 255 | #define MX50_INT_CTI1_TG0 79 | ||
| 256 | #define MX50_INT_CTI1_TG1 80 | ||
| 257 | #define MX50_INT_GPU2_IRQ 84 | ||
| 258 | #define MX50_INT_GPU2_BUSY 85 | ||
| 259 | #define MX50_INT_UART5 86 | ||
| 260 | #define MX50_INT_FEC 87 | ||
| 261 | #define MX50_INT_OWIRE 88 | ||
| 262 | #define MX50_INT_CTI1_TG2 89 | ||
| 263 | #define MX50_INT_SJC 90 | ||
| 264 | #define MX50_INT_DCP_CHAN1_3 91 | ||
| 265 | #define MX50_INT_DCP_CHAN0 92 | ||
| 266 | #define MX50_INT_PWM2 94 | ||
| 267 | #define MX50_INT_RNGB 97 | ||
| 268 | #define MX50_INT_CTI1_TG3 98 | ||
| 269 | #define MX50_INT_RAWNAND_BCH 100 | ||
| 270 | #define MX50_INT_RAWNAND_GPMI 102 | ||
| 271 | #define MX50_INT_GPIO5_LOW 103 | ||
| 272 | #define MX50_INT_GPIO5_HIGH 104 | ||
| 273 | #define MX50_INT_GPIO6_LOW 105 | ||
| 274 | #define MX50_INT_GPIO6_HIGH 106 | ||
| 275 | #define MX50_INT_MSHC 109 | ||
| 276 | #define MX50_INT_APBHDMA_CHAN0 110 | ||
| 277 | #define MX50_INT_APBHDMA_CHAN1 111 | ||
| 278 | #define MX50_INT_APBHDMA_CHAN2 112 | ||
| 279 | #define MX50_INT_APBHDMA_CHAN3 113 | ||
| 280 | #define MX50_INT_APBHDMA_CHAN4 114 | ||
| 281 | #define MX50_INT_APBHDMA_CHAN5 115 | ||
| 282 | #define MX50_INT_APBHDMA_CHAN6 116 | ||
| 283 | #define MX50_INT_APBHDMA_CHAN7 117 | ||
| 284 | |||
| 285 | #endif /* ifndef __MACH_MX50_H__ */ | ||
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index 2af7a1056fc1..873807f96d70 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h | |||
| @@ -2,31 +2,6 @@ | |||
| 2 | #define __MACH_MX51_H__ | 2 | #define __MACH_MX51_H__ |
| 3 | 3 | ||
| 4 | /* | 4 | /* |
| 5 | * MX51 memory map: | ||
| 6 | * | ||
| 7 | * | ||
| 8 | * Virt Phys Size What | ||
| 9 | * --------------------------------------------------------------------------- | ||
| 10 | * fa3e0000 1ffe0000 128K IRAM (SCCv2 RAM) | ||
| 11 | * 30000000 256M GPU | ||
| 12 | * 40000000 512M IPU | ||
| 13 | * fa200000 60000000 1M DEBUG | ||
| 14 | * fb100000 70000000 1M SPBA 0 | ||
| 15 | * fb000000 73f00000 1M AIPS 1 | ||
| 16 | * fb200000 83f00000 1M AIPS 2 | ||
| 17 | * 8fffc000 16K TZIC (interrupt controller) | ||
| 18 | * 90000000 256M CSD0 SDRAM/DDR | ||
| 19 | * a0000000 256M CSD1 SDRAM/DDR | ||
| 20 | * b0000000 128M CS0 Flash | ||
| 21 | * b8000000 128M CS1 Flash | ||
| 22 | * c0000000 128M CS2 Flash | ||
| 23 | * c8000000 64M CS3 Flash | ||
| 24 | * cc000000 32M CS4 SRAM | ||
| 25 | * ce000000 32M CS5 SRAM | ||
| 26 | * cfff0000 64K NFC (NAND Flash AXI) | ||
| 27 | */ | ||
| 28 | |||
| 29 | /* | ||
| 30 | * IROM | 5 | * IROM |
| 31 | */ | 6 | */ |
| 32 | #define MX51_IROM_BASE_ADDR 0x0 | 7 | #define MX51_IROM_BASE_ADDR 0x0 |
| @@ -36,7 +11,6 @@ | |||
| 36 | * IRAM | 11 | * IRAM |
| 37 | */ | 12 | */ |
| 38 | #define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */ | 13 | #define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */ |
| 39 | #define MX51_IRAM_BASE_ADDR_VIRT 0xfa3e0000 | ||
| 40 | #define MX51_IRAM_PARTITIONS 16 | 14 | #define MX51_IRAM_PARTITIONS 16 |
| 41 | #define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */ | 15 | #define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */ |
| 42 | 16 | ||
| @@ -45,7 +19,6 @@ | |||
| 45 | #define MX51_IPU_CTRL_BASE_ADDR 0x40000000 | 19 | #define MX51_IPU_CTRL_BASE_ADDR 0x40000000 |
| 46 | 20 | ||
| 47 | #define MX51_DEBUG_BASE_ADDR 0x60000000 | 21 | #define MX51_DEBUG_BASE_ADDR 0x60000000 |
| 48 | #define MX51_DEBUG_BASE_ADDR_VIRT 0xfa200000 | ||
| 49 | #define MX51_DEBUG_SIZE SZ_1M | 22 | #define MX51_DEBUG_SIZE SZ_1M |
| 50 | 23 | ||
| 51 | #define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x01000) | 24 | #define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x01000) |
| @@ -61,7 +34,6 @@ | |||
| 61 | * SPBA global module enabled #0 | 34 | * SPBA global module enabled #0 |
| 62 | */ | 35 | */ |
| 63 | #define MX51_SPBA0_BASE_ADDR 0x70000000 | 36 | #define MX51_SPBA0_BASE_ADDR 0x70000000 |
| 64 | #define MX51_SPBA0_BASE_ADDR_VIRT 0xfb100000 | ||
| 65 | #define MX51_SPBA0_SIZE SZ_1M | 37 | #define MX51_SPBA0_SIZE SZ_1M |
| 66 | 38 | ||
| 67 | #define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000) | 39 | #define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000) |
| @@ -81,7 +53,6 @@ | |||
| 81 | * AIPS 1 | 53 | * AIPS 1 |
| 82 | */ | 54 | */ |
| 83 | #define MX51_AIPS1_BASE_ADDR 0x73f00000 | 55 | #define MX51_AIPS1_BASE_ADDR 0x73f00000 |
| 84 | #define MX51_AIPS1_BASE_ADDR_VIRT 0xfb000000 | ||
| 85 | #define MX51_AIPS1_SIZE SZ_1M | 56 | #define MX51_AIPS1_SIZE SZ_1M |
| 86 | 57 | ||
| 87 | #define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000) | 58 | #define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000) |
| @@ -90,7 +61,7 @@ | |||
| 90 | #define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x8c000) | 61 | #define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x8c000) |
| 91 | #define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x90000) | 62 | #define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x90000) |
| 92 | #define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x94000) | 63 | #define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x94000) |
| 93 | #define MX51_WDOG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x98000) | 64 | #define MX51_WDOG1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x98000) |
| 94 | #define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x9c000) | 65 | #define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x9c000) |
| 95 | #define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa0000) | 66 | #define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa0000) |
| 96 | #define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa4000) | 67 | #define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa4000) |
| @@ -109,7 +80,6 @@ | |||
| 109 | * AIPS 2 | 80 | * AIPS 2 |
| 110 | */ | 81 | */ |
| 111 | #define MX51_AIPS2_BASE_ADDR 0x83f00000 | 82 | #define MX51_AIPS2_BASE_ADDR 0x83f00000 |
| 112 | #define MX51_AIPS2_BASE_ADDR_VIRT 0xfb200000 | ||
| 113 | #define MX51_AIPS2_SIZE SZ_1M | 83 | #define MX51_AIPS2_SIZE SZ_1M |
| 114 | 84 | ||
| 115 | #define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000) | 85 | #define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000) |
| @@ -139,7 +109,7 @@ | |||
| 139 | #define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdc000) | 109 | #define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdc000) |
| 140 | #define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe0000) | 110 | #define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe0000) |
| 141 | #define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe4000) | 111 | #define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe4000) |
| 142 | #define MX51_SSI3BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000) | 112 | #define MX51_SSI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000) |
| 143 | #define MX51_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xec000) | 113 | #define MX51_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xec000) |
| 144 | #define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf0000) | 114 | #define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf0000) |
| 145 | #define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf4000) | 115 | #define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf4000) |
| @@ -163,16 +133,8 @@ | |||
| 163 | #define MX51_GPU2D_BASE_ADDR 0xd0000000 | 133 | #define MX51_GPU2D_BASE_ADDR 0xd0000000 |
| 164 | #define MX51_TZIC_BASE_ADDR 0xe0000000 | 134 | #define MX51_TZIC_BASE_ADDR 0xe0000000 |
| 165 | 135 | ||
| 166 | #define MX51_IO_ADDRESS(x) ( \ | 136 | #define MX51_IO_P2V(x) IMX_IO_P2V(x) |
| 167 | IMX_IO_ADDRESS(x, MX51_IRAM) ?: \ | 137 | #define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x)) |
| 168 | IMX_IO_ADDRESS(x, MX51_DEBUG) ?: \ | ||
| 169 | IMX_IO_ADDRESS(x, MX51_SPBA0) ?: \ | ||
| 170 | IMX_IO_ADDRESS(x, MX51_AIPS1) ?: \ | ||
| 171 | IMX_IO_ADDRESS(x, MX51_AIPS2)) | ||
| 172 | |||
| 173 | /* This is currently used in <mach/debug-macro.S>, but should go away */ | ||
| 174 | #define MX51_AIPS1_IO_ADDRESS(x) \ | ||
| 175 | (((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT) | ||
| 176 | 138 | ||
| 177 | /* | 139 | /* |
| 178 | * defines for SPBA modules | 140 | * defines for SPBA modules |
| @@ -261,9 +223,9 @@ | |||
| 261 | #define MX51_DMA_REQ_EMI_WR 32 | 223 | #define MX51_DMA_REQ_EMI_WR 32 |
| 262 | #define MX51_DMA_REQ_CTI2_1 33 | 224 | #define MX51_DMA_REQ_CTI2_1 33 |
| 263 | #define MX51_DMA_REQ_EPIT2 34 | 225 | #define MX51_DMA_REQ_EPIT2 34 |
| 264 | #define MX51_DMA_REQ_SSI3_RX2 35 | 226 | #define MX51_DMA_REQ_SSI3_RX1 35 |
| 265 | #define MX51_DMA_REQ_IPU 36 | 227 | #define MX51_DMA_REQ_IPU 36 |
| 266 | #define MX51_DMA_REQ_SSI3_TX2 37 | 228 | #define MX51_DMA_REQ_SSI3_TX1 37 |
| 267 | #define MX51_DMA_REQ_CSPI_RX 38 | 229 | #define MX51_DMA_REQ_CSPI_RX 38 |
| 268 | #define MX51_DMA_REQ_CSPI_TX 39 | 230 | #define MX51_DMA_REQ_CSPI_TX 39 |
| 269 | #define MX51_DMA_REQ_SDHC3 40 | 231 | #define MX51_DMA_REQ_SDHC3 40 |
| @@ -272,8 +234,8 @@ | |||
| 272 | #define MX51_DMA_REQ_UART3_RX 43 | 234 | #define MX51_DMA_REQ_UART3_RX 43 |
| 273 | #define MX51_DMA_REQ_UART3_TX 44 | 235 | #define MX51_DMA_REQ_UART3_TX 44 |
| 274 | #define MX51_DMA_REQ_SPDIF 45 | 236 | #define MX51_DMA_REQ_SPDIF 45 |
| 275 | #define MX51_DMA_REQ_SSI3_RX1 46 | 237 | #define MX51_DMA_REQ_SSI3_RX0 46 |
| 276 | #define MX51_DMA_REQ_SSI3_TX1 47 | 238 | #define MX51_DMA_REQ_SSI3_TX0 47 |
| 277 | 239 | ||
| 278 | /* | 240 | /* |
| 279 | * Interrupt numbers | 241 | * Interrupt numbers |
| @@ -289,8 +251,8 @@ | |||
| 289 | #define MX51_MXC_INT_IOMUX 7 | 251 | #define MX51_MXC_INT_IOMUX 7 |
| 290 | #define MX51_INT_NFC 8 | 252 | #define MX51_INT_NFC 8 |
| 291 | #define MX51_MXC_INT_VPU 9 | 253 | #define MX51_MXC_INT_VPU 9 |
| 292 | #define MX51_MXC_INT_IPU_ERR 10 | 254 | #define MX51_INT_IPU_ERR 10 |
| 293 | #define MX51_MXC_INT_IPU_SYN 11 | 255 | #define MX51_INT_IPU_SYN 11 |
| 294 | #define MX51_MXC_INT_GPU 12 | 256 | #define MX51_MXC_INT_GPU 12 |
| 295 | #define MX51_MXC_INT_RESV13 13 | 257 | #define MX51_MXC_INT_RESV13 13 |
| 296 | #define MX51_MXC_INT_USB_H1 14 | 258 | #define MX51_MXC_INT_USB_H1 14 |
| @@ -375,7 +337,7 @@ | |||
| 375 | #define MX51_MXC_INT_FIRI 93 | 337 | #define MX51_MXC_INT_FIRI 93 |
| 376 | #define MX51_MXC_INT_PWM2 94 | 338 | #define MX51_MXC_INT_PWM2 94 |
| 377 | #define MX51_MXC_INT_SLIM_EXP 95 | 339 | #define MX51_MXC_INT_SLIM_EXP 95 |
| 378 | #define MX51_MXC_INT_SSI3 96 | 340 | #define MX51_INT_SSI3 96 |
| 379 | #define MX51_MXC_INT_EMI_BOOT 97 | 341 | #define MX51_MXC_INT_EMI_BOOT 97 |
| 380 | #define MX51_MXC_INT_CTI1_TG3 98 | 342 | #define MX51_MXC_INT_CTI1_TG3 98 |
| 381 | #define MX51_MXC_INT_SMC_RX 99 | 343 | #define MX51_MXC_INT_SMC_RX 99 |
| @@ -383,19 +345,6 @@ | |||
| 383 | #define MX51_MXC_INT_EMI_NFC 101 | 345 | #define MX51_MXC_INT_EMI_NFC 101 |
| 384 | #define MX51_MXC_INT_GPU_IDLE 102 | 346 | #define MX51_MXC_INT_GPU_IDLE 102 |
| 385 | 347 | ||
| 386 | /* silicon revisions specific to i.MX51 */ | ||
| 387 | #define MX51_CHIP_REV_1_0 0x10 | ||
| 388 | #define MX51_CHIP_REV_1_1 0x11 | ||
| 389 | #define MX51_CHIP_REV_1_2 0x12 | ||
| 390 | #define MX51_CHIP_REV_1_3 0x13 | ||
| 391 | #define MX51_CHIP_REV_2_0 0x20 | ||
| 392 | #define MX51_CHIP_REV_2_1 0x21 | ||
| 393 | #define MX51_CHIP_REV_2_2 0x22 | ||
| 394 | #define MX51_CHIP_REV_2_3 0x23 | ||
| 395 | #define MX51_CHIP_REV_3_0 0x30 | ||
| 396 | #define MX51_CHIP_REV_3_1 0x31 | ||
| 397 | #define MX51_CHIP_REV_3_2 0x32 | ||
| 398 | |||
| 399 | #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) | 348 | #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) |
| 400 | extern int mx51_revision(void); | 349 | extern int mx51_revision(void); |
| 401 | #endif | 350 | #endif |
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h new file mode 100644 index 000000000000..9577cdbf7fad --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx53.h | |||
| @@ -0,0 +1,353 @@ | |||
| 1 | #ifndef __MACH_MX53_H__ | ||
| 2 | #define __MACH_MX53_H__ | ||
| 3 | |||
| 4 | /* | ||
| 5 | * IROM | ||
| 6 | */ | ||
| 7 | #define MX53_IROM_BASE_ADDR 0x0 | ||
| 8 | #define MX53_IROM_SIZE SZ_64K | ||
| 9 | |||
| 10 | /* TZIC */ | ||
| 11 | #define MX53_TZIC_BASE_ADDR 0x0FFFC000 | ||
| 12 | |||
| 13 | /* | ||
| 14 | * AHCI SATA | ||
| 15 | */ | ||
| 16 | #define MX53_SATA_BASE_ADDR 0x10000000 | ||
| 17 | |||
| 18 | /* | ||
| 19 | * NFC | ||
| 20 | */ | ||
| 21 | #define MX53_NFC_AXI_BASE_ADDR 0xF7FF0000 /* NAND flash AXI */ | ||
| 22 | #define MX53_NFC_AXI_SIZE SZ_64K | ||
| 23 | |||
| 24 | /* | ||
| 25 | * IRAM | ||
| 26 | */ | ||
| 27 | #define MX53_IRAM_BASE_ADDR 0xF8000000 /* internal ram */ | ||
| 28 | #define MX53_IRAM_PARTITIONS 16 | ||
| 29 | #define MX53_IRAM_SIZE (MX53_IRAM_PARTITIONS * SZ_8K) /* 128KB */ | ||
| 30 | |||
| 31 | /* | ||
| 32 | * Graphics Memory of GPU | ||
| 33 | */ | ||
| 34 | #define MX53_IPU_CTRL_BASE_ADDR 0x18000000 | ||
| 35 | #define MX53_GPU2D_BASE_ADDR 0x20000000 | ||
| 36 | #define MX53_GPU_BASE_ADDR 0x30000000 | ||
| 37 | #define MX53_GPU_GMEM_BASE_ADDR 0xF8020000 | ||
| 38 | |||
| 39 | #define MX53_DEBUG_BASE_ADDR 0x40000000 | ||
| 40 | #define MX53_DEBUG_SIZE SZ_1M | ||
| 41 | #define MX53_ETB_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00001000) | ||
| 42 | #define MX53_ETM_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00002000) | ||
| 43 | #define MX53_TPIU_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00003000) | ||
| 44 | #define MX53_CTI0_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00004000) | ||
| 45 | #define MX53_CTI1_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00005000) | ||
| 46 | #define MX53_CTI2_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00006000) | ||
| 47 | #define MX53_CTI3_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00007000) | ||
| 48 | #define MX53_CORTEX_DBG_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00008000) | ||
| 49 | |||
| 50 | /* | ||
| 51 | * SPBA global module enabled #0 | ||
| 52 | */ | ||
| 53 | #define MX53_SPBA0_BASE_ADDR 0x50000000 | ||
| 54 | #define MX53_SPBA0_SIZE SZ_1M | ||
| 55 | |||
| 56 | #define MX53_MMC_SDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000) | ||
| 57 | #define MX53_MMC_SDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000) | ||
| 58 | #define MX53_UART3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0000C000) | ||
| 59 | #define MX53_CSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000) | ||
| 60 | #define MX53_SSI2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00014000) | ||
| 61 | #define MX53_MMC_SDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000) | ||
| 62 | #define MX53_MMC_SDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000) | ||
| 63 | #define MX53_SPDIF_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00028000) | ||
| 64 | #define MX53_ASRC_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0002C000) | ||
| 65 | #define MX53_ATA_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00030000) | ||
| 66 | #define MX53_SLIM_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00034000) | ||
| 67 | #define MX53_HSI2C_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00038000) | ||
| 68 | #define MX53_SPBA_CTRL_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0003C000) | ||
| 69 | |||
| 70 | /* | ||
| 71 | * AIPS 1 | ||
| 72 | */ | ||
| 73 | #define MX53_AIPS1_BASE_ADDR 0x53F00000 | ||
| 74 | #define MX53_AIPS1_SIZE SZ_1M | ||
| 75 | |||
| 76 | #define MX53_OTG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00080000) | ||
| 77 | #define MX53_GPIO1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00084000) | ||
| 78 | #define MX53_GPIO2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00088000) | ||
| 79 | #define MX53_GPIO3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0008C000) | ||
| 80 | #define MX53_GPIO4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00090000) | ||
| 81 | #define MX53_KPP_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00094000) | ||
| 82 | #define MX53_WDOG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00098000) | ||
| 83 | #define MX53_WDOG2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0009C000) | ||
| 84 | #define MX53_GPT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A0000) | ||
| 85 | #define MX53_SRTC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A4000) | ||
| 86 | #define MX53_IOMUXC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A8000) | ||
| 87 | #define MX53_EPIT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000AC000) | ||
| 88 | #define MX53_EPIT2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B0000) | ||
| 89 | #define MX53_PWM1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B4000) | ||
| 90 | #define MX53_PWM2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B8000) | ||
| 91 | #define MX53_UART1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000BC000) | ||
| 92 | #define MX53_UART2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000C0000) | ||
| 93 | #define MX53_SRC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D0000) | ||
| 94 | #define MX53_CCM_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D4000) | ||
| 95 | #define MX53_GPC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D8000) | ||
| 96 | #define MX53_GPIO5_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000DC000) | ||
| 97 | #define MX53_GPIO6_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E0000) | ||
| 98 | #define MX53_GPIO7_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E4000) | ||
| 99 | #define MX53_ATA_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E8000) | ||
| 100 | #define MX53_I2C3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000EC000) | ||
| 101 | #define MX53_UART4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000F0000) | ||
| 102 | |||
| 103 | /* | ||
| 104 | * AIPS 2 | ||
| 105 | */ | ||
| 106 | #define MX53_AIPS2_BASE_ADDR 0x63F00000 | ||
| 107 | #define MX53_AIPS2_SIZE SZ_1M | ||
| 108 | |||
| 109 | #define MX53_PLL1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00080000) | ||
| 110 | #define MX53_PLL2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00084000) | ||
| 111 | #define MX53_PLL3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00088000) | ||
| 112 | #define MX53_PLL4_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0008C000) | ||
| 113 | #define MX53_UART5_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00090000) | ||
| 114 | #define MX53_AHBMAX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00094000) | ||
| 115 | #define MX53_IIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00098000) | ||
| 116 | #define MX53_CSU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0009C000) | ||
| 117 | #define MX53_ARM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A0000) | ||
| 118 | #define MX53_OWIRE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A4000) | ||
| 119 | #define MX53_FIRI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A8000) | ||
| 120 | #define MX53_CSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000) | ||
| 121 | #define MX53_SDMA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B0000) | ||
| 122 | #define MX53_SCC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B4000) | ||
| 123 | #define MX53_ROMCP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B8000) | ||
| 124 | #define MX53_RTIC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000BC000) | ||
| 125 | #define MX53_CSPI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000) | ||
| 126 | #define MX53_I2C2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C4000) | ||
| 127 | #define MX53_I2C1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C8000) | ||
| 128 | #define MX53_SSI1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000CC000) | ||
| 129 | #define MX53_AUDMUX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D0000) | ||
| 130 | #define MX53_RTC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D4000) | ||
| 131 | #define MX53_M4IF_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D8000) | ||
| 132 | #define MX53_ESDCTL_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D9000) | ||
| 133 | #define MX53_WEIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DA000) | ||
| 134 | #define MX53_NFC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DB000) | ||
| 135 | #define MX53_EMI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DBF00) | ||
| 136 | #define MX53_MIPI_HSC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DC000) | ||
| 137 | #define MX53_MLB_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E4000) | ||
| 138 | #define MX53_SSI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E8000) | ||
| 139 | #define MX53_MXC_FEC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000EC000) | ||
| 140 | #define MX53_TVE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F0000) | ||
| 141 | #define MX53_VPU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F4000) | ||
| 142 | #define MX53_SAHARA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F8000) | ||
| 143 | #define MX53_PTP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000FC000) | ||
| 144 | |||
| 145 | /* | ||
| 146 | * Memory regions and CS | ||
| 147 | */ | ||
| 148 | #define MX53_CSD0_BASE_ADDR 0x90000000 | ||
| 149 | #define MX53_CSD1_BASE_ADDR 0xA0000000 | ||
| 150 | #define MX53_CS0_BASE_ADDR 0xB0000000 | ||
| 151 | #define MX53_CS1_BASE_ADDR 0xB8000000 | ||
| 152 | #define MX53_CS2_BASE_ADDR 0xC0000000 | ||
| 153 | #define MX53_CS3_BASE_ADDR 0xC8000000 | ||
| 154 | #define MX53_CS4_BASE_ADDR 0xCC000000 | ||
| 155 | #define MX53_CS5_BASE_ADDR 0xCE000000 | ||
| 156 | |||
| 157 | #define MX53_IO_P2V(x) IMX_IO_P2V(x) | ||
| 158 | #define MX53_IO_ADDRESS(x) IOMEM(MX53_IO_P2V(x)) | ||
| 159 | |||
| 160 | /* | ||
| 161 | * defines for SPBA modules | ||
| 162 | */ | ||
| 163 | #define MX53_SPBA_SDHC1 0x04 | ||
| 164 | #define MX53_SPBA_SDHC2 0x08 | ||
| 165 | #define MX53_SPBA_UART3 0x0C | ||
| 166 | #define MX53_SPBA_CSPI1 0x10 | ||
| 167 | #define MX53_SPBA_SSI2 0x14 | ||
| 168 | #define MX53_SPBA_SDHC3 0x20 | ||
| 169 | #define MX53_SPBA_SDHC4 0x24 | ||
| 170 | #define MX53_SPBA_SPDIF 0x28 | ||
| 171 | #define MX53_SPBA_ATA 0x30 | ||
| 172 | #define MX53_SPBA_SLIM 0x34 | ||
| 173 | #define MX53_SPBA_HSI2C 0x38 | ||
| 174 | #define MX53_SPBA_CTRL 0x3C | ||
| 175 | |||
| 176 | /* | ||
| 177 | * DMA request assignments | ||
| 178 | */ | ||
| 179 | #define MX53_DMA_REQ_SSI3_TX1 47 | ||
| 180 | #define MX53_DMA_REQ_SSI3_RX1 46 | ||
| 181 | #define MX53_DMA_REQ_SSI3_TX2 45 | ||
| 182 | #define MX53_DMA_REQ_SSI3_RX2 44 | ||
| 183 | #define MX53_DMA_REQ_UART3_TX 43 | ||
| 184 | #define MX53_DMA_REQ_UART3_RX 42 | ||
| 185 | #define MX53_DMA_REQ_ESAI_TX 41 | ||
| 186 | #define MX53_DMA_REQ_ESAI_RX 40 | ||
| 187 | #define MX53_DMA_REQ_CSPI_TX 39 | ||
| 188 | #define MX53_DMA_REQ_CSPI_RX 38 | ||
| 189 | #define MX53_DMA_REQ_ASRC_DMA6 37 | ||
| 190 | #define MX53_DMA_REQ_ASRC_DMA5 36 | ||
| 191 | #define MX53_DMA_REQ_ASRC_DMA4 35 | ||
| 192 | #define MX53_DMA_REQ_ASRC_DMA3 34 | ||
| 193 | #define MX53_DMA_REQ_ASRC_DMA2 33 | ||
| 194 | #define MX53_DMA_REQ_ASRC_DMA1 32 | ||
| 195 | #define MX53_DMA_REQ_EMI_WR 31 | ||
| 196 | #define MX53_DMA_REQ_EMI_RD 30 | ||
| 197 | #define MX53_DMA_REQ_SSI1_TX1 29 | ||
| 198 | #define MX53_DMA_REQ_SSI1_RX1 28 | ||
| 199 | #define MX53_DMA_REQ_SSI1_TX2 27 | ||
| 200 | #define MX53_DMA_REQ_SSI1_RX2 26 | ||
| 201 | #define MX53_DMA_REQ_SSI2_TX1 25 | ||
| 202 | #define MX53_DMA_REQ_SSI2_RX1 24 | ||
| 203 | #define MX53_DMA_REQ_SSI2_TX2 23 | ||
| 204 | #define MX53_DMA_REQ_SSI2_RX2 22 | ||
| 205 | #define MX53_DMA_REQ_I2C2_SDHC2 21 | ||
| 206 | #define MX53_DMA_REQ_I2C1_SDHC1 20 | ||
| 207 | #define MX53_DMA_REQ_UART1_TX 19 | ||
| 208 | #define MX53_DMA_REQ_UART1_RX 18 | ||
| 209 | #define MX53_DMA_REQ_UART5_TX 17 | ||
| 210 | #define MX53_DMA_REQ_UART5_RX 16 | ||
| 211 | #define MX53_DMA_REQ_SPDIF_TX 15 | ||
| 212 | #define MX53_DMA_REQ_SPDIF_RX 14 | ||
| 213 | #define MX53_DMA_REQ_UART2_FIRI_TX 13 | ||
| 214 | #define MX53_DMA_REQ_UART2_FIRI_RX 12 | ||
| 215 | #define MX53_DMA_REQ_SDHC4 11 | ||
| 216 | #define MX53_DMA_REQ_I2C3_SDHC3 10 | ||
| 217 | #define MX53_DMA_REQ_CSPI2_TX 9 | ||
| 218 | #define MX53_DMA_REQ_CSPI2_RX 8 | ||
| 219 | #define MX53_DMA_REQ_CSPI1_TX 7 | ||
| 220 | #define MX53_DMA_REQ_CSPI1_RX 6 | ||
| 221 | #define MX53_DMA_REQ_IPU 5 | ||
| 222 | #define MX53_DMA_REQ_ATA_TX_END 4 | ||
| 223 | #define MX53_DMA_REQ_ATA_UART4_TX 3 | ||
| 224 | #define MX53_DMA_REQ_ATA_UART4_RX 2 | ||
| 225 | #define MX53_DMA_REQ_GPC 1 | ||
| 226 | #define MX53_DMA_REQ_VPU 0 | ||
| 227 | |||
| 228 | /* | ||
| 229 | * Interrupt numbers | ||
| 230 | */ | ||
| 231 | #define MX53_INT_RESV0 0 | ||
| 232 | #define MX53_INT_MMC_SDHC1 1 | ||
| 233 | #define MX53_INT_MMC_SDHC2 2 | ||
| 234 | #define MX53_INT_MMC_SDHC3 3 | ||
| 235 | #define MX53_INT_MMC_SDHC4 4 | ||
| 236 | #define MX53_INT_RESV5 5 | ||
| 237 | #define MX53_INT_SDMA 6 | ||
| 238 | #define MX53_INT_IOMUX 7 | ||
| 239 | #define MX53_INT_NFC 8 | ||
| 240 | #define MX53_INT_VPU 9 | ||
| 241 | #define MX53_INT_IPU_ERR 10 | ||
| 242 | #define MX53_INT_IPU_SYN 11 | ||
| 243 | #define MX53_INT_GPU 12 | ||
| 244 | #define MX53_INT_RESV13 13 | ||
| 245 | #define MX53_INT_USB_H1 14 | ||
| 246 | #define MX53_INT_EMI 15 | ||
| 247 | #define MX53_INT_USB_H2 16 | ||
| 248 | #define MX53_INT_USB_H3 17 | ||
| 249 | #define MX53_INT_USB_OTG 18 | ||
| 250 | #define MX53_INT_SAHARA_H0 19 | ||
| 251 | #define MX53_INT_SAHARA_H1 20 | ||
| 252 | #define MX53_INT_SCC_SMN 21 | ||
| 253 | #define MX53_INT_SCC_STZ 22 | ||
| 254 | #define MX53_INT_SCC_SCM 23 | ||
| 255 | #define MX53_INT_SRTC_NTZ 24 | ||
| 256 | #define MX53_INT_SRTC_TZ 25 | ||
| 257 | #define MX53_INT_RTIC 26 | ||
| 258 | #define MX53_INT_CSU 27 | ||
| 259 | #define MX53_INT_SATA 28 | ||
| 260 | #define MX53_INT_SSI1 29 | ||
| 261 | #define MX53_INT_SSI2 30 | ||
| 262 | #define MX53_INT_UART1 31 | ||
| 263 | #define MX53_INT_UART2 32 | ||
| 264 | #define MX53_INT_UART3 33 | ||
| 265 | #define MX53_INT_RESV34 34 | ||
| 266 | #define MX53_INT_RESV35 35 | ||
| 267 | #define MX53_INT_CSPI1 36 | ||
| 268 | #define MX53_INT_CSPI2 37 | ||
| 269 | #define MX53_INT_CSPI 38 | ||
| 270 | #define MX53_INT_GPT 39 | ||
| 271 | #define MX53_INT_EPIT1 40 | ||
| 272 | #define MX53_INT_EPIT2 41 | ||
| 273 | #define MX53_INT_GPIO1_INT7 42 | ||
| 274 | #define MX53_INT_GPIO1_INT6 43 | ||
| 275 | #define MX53_INT_GPIO1_INT5 44 | ||
| 276 | #define MX53_INT_GPIO1_INT4 45 | ||
| 277 | #define MX53_INT_GPIO1_INT3 46 | ||
| 278 | #define MX53_INT_GPIO1_INT2 47 | ||
| 279 | #define MX53_INT_GPIO1_INT1 48 | ||
| 280 | #define MX53_INT_GPIO1_INT0 49 | ||
| 281 | #define MX53_INT_GPIO1_LOW 50 | ||
| 282 | #define MX53_INT_GPIO1_HIGH 51 | ||
| 283 | #define MX53_INT_GPIO2_LOW 52 | ||
| 284 | #define MX53_INT_GPIO2_HIGH 53 | ||
| 285 | #define MX53_INT_GPIO3_LOW 54 | ||
| 286 | #define MX53_INT_GPIO3_HIGH 55 | ||
| 287 | #define MX53_INT_GPIO4_LOW 56 | ||
| 288 | #define MX53_INT_GPIO4_HIGH 57 | ||
| 289 | #define MX53_INT_WDOG1 58 | ||
| 290 | #define MX53_INT_WDOG2 59 | ||
| 291 | #define MX53_INT_KPP 60 | ||
| 292 | #define MX53_INT_PWM1 61 | ||
| 293 | #define MX53_INT_I2C1 62 | ||
| 294 | #define MX53_INT_I2C2 63 | ||
| 295 | #define MX53_INT_I2C3 64 | ||
| 296 | #define MX53_INT_RESV65 65 | ||
| 297 | #define MX53_INT_RESV66 66 | ||
| 298 | #define MX53_INT_SPDIF 67 | ||
| 299 | #define MX53_INT_SIM_DAT 68 | ||
| 300 | #define MX53_INT_IIM 69 | ||
| 301 | #define MX53_INT_ATA 70 | ||
| 302 | #define MX53_INT_CCM1 71 | ||
| 303 | #define MX53_INT_CCM2 72 | ||
| 304 | #define MX53_INT_GPC1 73 | ||
| 305 | #define MX53_INT_GPC2 74 | ||
| 306 | #define MX53_INT_SRC 75 | ||
| 307 | #define MX53_INT_NM 76 | ||
| 308 | #define MX53_INT_PMU 77 | ||
| 309 | #define MX53_INT_CTI_IRQ 78 | ||
| 310 | #define MX53_INT_CTI1_TG0 79 | ||
| 311 | #define MX53_INT_CTI1_TG1 80 | ||
| 312 | #define MX53_INT_ESAI 81 | ||
| 313 | #define MX53_INT_CAN1 82 | ||
| 314 | #define MX53_INT_CAN2 83 | ||
| 315 | #define MX53_INT_GPU2_IRQ 84 | ||
| 316 | #define MX53_INT_GPU2_BUSY 85 | ||
| 317 | #define MX53_INT_RESV86 86 | ||
| 318 | #define MX53_INT_FEC 87 | ||
| 319 | #define MX53_INT_OWIRE 88 | ||
| 320 | #define MX53_INT_CTI1_TG2 89 | ||
| 321 | #define MX53_INT_SJC 90 | ||
| 322 | #define MX53_INT_TVE 92 | ||
| 323 | #define MX53_INT_FIRI 93 | ||
| 324 | #define MX53_INT_PWM2 94 | ||
| 325 | #define MX53_INT_SLIM_EXP 95 | ||
| 326 | #define MX53_INT_SSI3 96 | ||
| 327 | #define MX53_INT_EMI_BOOT 97 | ||
| 328 | #define MX53_INT_CTI1_TG3 98 | ||
| 329 | #define MX53_INT_SMC_RX 99 | ||
| 330 | #define MX53_INT_VPU_IDLE 100 | ||
| 331 | #define MX53_INT_EMI_NFC 101 | ||
| 332 | #define MX53_INT_GPU_IDLE 102 | ||
| 333 | #define MX53_INT_GPIO5_LOW 103 | ||
| 334 | #define MX53_INT_GPIO5_HIGH 104 | ||
| 335 | #define MX53_INT_GPIO6_LOW 105 | ||
| 336 | #define MX53_INT_GPIO6_HIGH 106 | ||
| 337 | #define MX53_INT_GPIO7_LOW 107 | ||
| 338 | #define MX53_INT_GPIO7_HIGH 108 | ||
| 339 | |||
| 340 | /* silicon revisions specific to i.MX53 */ | ||
| 341 | #define MX53_CHIP_REV_1_0 0x10 | ||
| 342 | #define MX53_CHIP_REV_1_1 0x11 | ||
| 343 | #define MX53_CHIP_REV_1_2 0x12 | ||
| 344 | #define MX53_CHIP_REV_1_3 0x13 | ||
| 345 | #define MX53_CHIP_REV_2_0 0x20 | ||
| 346 | #define MX53_CHIP_REV_2_1 0x21 | ||
| 347 | #define MX53_CHIP_REV_2_2 0x22 | ||
| 348 | #define MX53_CHIP_REV_2_3 0x23 | ||
| 349 | #define MX53_CHIP_REV_3_0 0x30 | ||
| 350 | #define MX53_CHIP_REV_3_1 0x31 | ||
| 351 | #define MX53_CHIP_REV_3_2 0x32 | ||
| 352 | |||
| 353 | #endif /* ifndef __MACH_MX53_H__ */ | ||
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index a42c7207082d..04c7a26b1f26 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h | |||
| @@ -32,9 +32,25 @@ | |||
| 32 | #define MXC_CPU_MX27 27 | 32 | #define MXC_CPU_MX27 27 |
| 33 | #define MXC_CPU_MX31 31 | 33 | #define MXC_CPU_MX31 31 |
| 34 | #define MXC_CPU_MX35 35 | 34 | #define MXC_CPU_MX35 35 |
| 35 | #define MXC_CPU_MX50 50 | ||
| 35 | #define MXC_CPU_MX51 51 | 36 | #define MXC_CPU_MX51 51 |
| 37 | #define MXC_CPU_MX53 53 | ||
| 36 | #define MXC_CPU_MXC91231 91231 | 38 | #define MXC_CPU_MXC91231 91231 |
| 37 | 39 | ||
| 40 | #define IMX_CHIP_REVISION_1_0 0x10 | ||
| 41 | #define IMX_CHIP_REVISION_1_1 0x11 | ||
| 42 | #define IMX_CHIP_REVISION_1_2 0x12 | ||
| 43 | #define IMX_CHIP_REVISION_1_3 0x13 | ||
| 44 | #define IMX_CHIP_REVISION_2_0 0x20 | ||
| 45 | #define IMX_CHIP_REVISION_2_1 0x21 | ||
| 46 | #define IMX_CHIP_REVISION_2_2 0x22 | ||
| 47 | #define IMX_CHIP_REVISION_2_3 0x23 | ||
| 48 | #define IMX_CHIP_REVISION_3_0 0x30 | ||
| 49 | #define IMX_CHIP_REVISION_3_1 0x31 | ||
| 50 | #define IMX_CHIP_REVISION_3_2 0x32 | ||
| 51 | #define IMX_CHIP_REVISION_3_3 0x33 | ||
| 52 | #define IMX_CHIP_REVISION_UNKNOWN 0xff | ||
| 53 | |||
| 38 | #ifndef __ASSEMBLY__ | 54 | #ifndef __ASSEMBLY__ |
| 39 | extern unsigned int __mxc_cpu_type; | 55 | extern unsigned int __mxc_cpu_type; |
| 40 | #endif | 56 | #endif |
| @@ -111,7 +127,19 @@ extern unsigned int __mxc_cpu_type; | |||
| 111 | # define cpu_is_mx35() (0) | 127 | # define cpu_is_mx35() (0) |
| 112 | #endif | 128 | #endif |
| 113 | 129 | ||
| 114 | #ifdef CONFIG_ARCH_MX5 | 130 | #ifdef CONFIG_ARCH_MX50 |
| 131 | # ifdef mxc_cpu_type | ||
| 132 | # undef mxc_cpu_type | ||
| 133 | # define mxc_cpu_type __mxc_cpu_type | ||
| 134 | # else | ||
| 135 | # define mxc_cpu_type MXC_CPU_MX50 | ||
| 136 | # endif | ||
| 137 | # define cpu_is_mx50() (mxc_cpu_type == MXC_CPU_MX50) | ||
| 138 | #else | ||
| 139 | # define cpu_is_mx50() (0) | ||
| 140 | #endif | ||
| 141 | |||
| 142 | #ifdef CONFIG_ARCH_MX51 | ||
| 115 | # ifdef mxc_cpu_type | 143 | # ifdef mxc_cpu_type |
| 116 | # undef mxc_cpu_type | 144 | # undef mxc_cpu_type |
| 117 | # define mxc_cpu_type __mxc_cpu_type | 145 | # define mxc_cpu_type __mxc_cpu_type |
| @@ -123,6 +151,18 @@ extern unsigned int __mxc_cpu_type; | |||
| 123 | # define cpu_is_mx51() (0) | 151 | # define cpu_is_mx51() (0) |
| 124 | #endif | 152 | #endif |
| 125 | 153 | ||
| 154 | #ifdef CONFIG_ARCH_MX53 | ||
| 155 | # ifdef mxc_cpu_type | ||
| 156 | # undef mxc_cpu_type | ||
| 157 | # define mxc_cpu_type __mxc_cpu_type | ||
| 158 | # else | ||
| 159 | # define mxc_cpu_type MXC_CPU_MX53 | ||
| 160 | # endif | ||
| 161 | # define cpu_is_mx53() (mxc_cpu_type == MXC_CPU_MX53) | ||
| 162 | #else | ||
| 163 | # define cpu_is_mx53() (0) | ||
| 164 | #endif | ||
| 165 | |||
| 126 | #ifdef CONFIG_ARCH_MXC91231 | 166 | #ifdef CONFIG_ARCH_MXC91231 |
| 127 | # ifdef mxc_cpu_type | 167 | # ifdef mxc_cpu_type |
| 128 | # undef mxc_cpu_type | 168 | # undef mxc_cpu_type |
diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h index 0ca3101ebf36..765190fe6332 100644 --- a/arch/arm/plat-mxc/include/mach/mxc91231.h +++ b/arch/arm/plat-mxc/include/mach/mxc91231.h | |||
| @@ -21,14 +21,12 @@ | |||
| 21 | * L2CC | 21 | * L2CC |
| 22 | */ | 22 | */ |
| 23 | #define MXC91231_L2CC_BASE_ADDR 0x30000000 | 23 | #define MXC91231_L2CC_BASE_ADDR 0x30000000 |
| 24 | #define MXC91231_L2CC_BASE_ADDR_VIRT 0xF9000000 | ||
| 25 | #define MXC91231_L2CC_SIZE SZ_64K | 24 | #define MXC91231_L2CC_SIZE SZ_64K |
| 26 | 25 | ||
| 27 | /* | 26 | /* |
| 28 | * AIPS 1 | 27 | * AIPS 1 |
| 29 | */ | 28 | */ |
| 30 | #define MXC91231_AIPS1_BASE_ADDR 0x43F00000 | 29 | #define MXC91231_AIPS1_BASE_ADDR 0x43F00000 |
| 31 | #define MXC91231_AIPS1_BASE_ADDR_VIRT 0xFC000000 | ||
| 32 | #define MXC91231_AIPS1_SIZE SZ_1M | 30 | #define MXC91231_AIPS1_SIZE SZ_1M |
| 33 | 31 | ||
| 34 | #define MXC91231_AIPS1_CTRL_BASE_ADDR MXC91231_AIPS1_BASE_ADDR | 32 | #define MXC91231_AIPS1_CTRL_BASE_ADDR MXC91231_AIPS1_BASE_ADDR |
| @@ -53,7 +51,6 @@ | |||
| 53 | * AIPS 2 | 51 | * AIPS 2 |
| 54 | */ | 52 | */ |
| 55 | #define MXC91231_AIPS2_BASE_ADDR 0x53F00000 | 53 | #define MXC91231_AIPS2_BASE_ADDR 0x53F00000 |
| 56 | #define MXC91231_AIPS2_BASE_ADDR_VIRT 0xFC100000 | ||
| 57 | #define MXC91231_AIPS2_SIZE SZ_1M | 54 | #define MXC91231_AIPS2_SIZE SZ_1M |
| 58 | 55 | ||
| 59 | #define MXC91231_GEMK_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x8C000) | 56 | #define MXC91231_GEMK_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x8C000) |
| @@ -79,7 +76,6 @@ | |||
| 79 | * SPBA global module 0 | 76 | * SPBA global module 0 |
| 80 | */ | 77 | */ |
| 81 | #define MXC91231_SPBA0_BASE_ADDR 0x50000000 | 78 | #define MXC91231_SPBA0_BASE_ADDR 0x50000000 |
| 82 | #define MXC91231_SPBA0_BASE_ADDR_VIRT 0xFC200000 | ||
| 83 | #define MXC91231_SPBA0_SIZE SZ_1M | 79 | #define MXC91231_SPBA0_SIZE SZ_1M |
| 84 | 80 | ||
| 85 | #define MXC91231_MMC_SDHC1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x04000) | 81 | #define MXC91231_MMC_SDHC1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x04000) |
| @@ -109,7 +105,6 @@ | |||
| 109 | * SPBA global module 1 | 105 | * SPBA global module 1 |
| 110 | */ | 106 | */ |
| 111 | #define MXC91231_SPBA1_BASE_ADDR 0x52000000 | 107 | #define MXC91231_SPBA1_BASE_ADDR 0x52000000 |
| 112 | #define MXC91231_SPBA1_BASE_ADDR_VIRT 0xFC300000 | ||
| 113 | #define MXC91231_SPBA1_SIZE SZ_1M | 108 | #define MXC91231_SPBA1_SIZE SZ_1M |
| 114 | 109 | ||
| 115 | #define MXC91231_MQSPI_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x34000) | 110 | #define MXC91231_MQSPI_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x34000) |
| @@ -144,18 +139,15 @@ | |||
| 144 | * ROMP and AVIC | 139 | * ROMP and AVIC |
| 145 | */ | 140 | */ |
| 146 | #define MXC91231_ROMP_BASE_ADDR 0x60000000 | 141 | #define MXC91231_ROMP_BASE_ADDR 0x60000000 |
| 147 | #define MXC91231_ROMP_BASE_ADDR_VIRT 0xFC400000 | ||
| 148 | #define MXC91231_ROMP_SIZE SZ_64K | 142 | #define MXC91231_ROMP_SIZE SZ_64K |
| 149 | 143 | ||
| 150 | #define MXC91231_AVIC_BASE_ADDR 0x68000000 | 144 | #define MXC91231_AVIC_BASE_ADDR 0x68000000 |
| 151 | #define MXC91231_AVIC_BASE_ADDR_VIRT 0xFC410000 | ||
| 152 | #define MXC91231_AVIC_SIZE SZ_64K | 145 | #define MXC91231_AVIC_SIZE SZ_64K |
| 153 | 146 | ||
| 154 | /* | 147 | /* |
| 155 | * NAND, SDRAM, WEIM, M3IF, EMI controllers | 148 | * NAND, SDRAM, WEIM, M3IF, EMI controllers |
| 156 | */ | 149 | */ |
| 157 | #define MXC91231_X_MEMC_BASE_ADDR 0xB8000000 | 150 | #define MXC91231_X_MEMC_BASE_ADDR 0xB8000000 |
| 158 | #define MXC91231_X_MEMC_BASE_ADDR_VIRT 0xFC420000 | ||
| 159 | #define MXC91231_X_MEMC_SIZE SZ_64K | 151 | #define MXC91231_X_MEMC_SIZE SZ_64K |
| 160 | 152 | ||
| 161 | #define MXC91231_NFC_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x0000) | 153 | #define MXC91231_NFC_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x0000) |
| @@ -183,19 +175,10 @@ | |||
| 183 | /* | 175 | /* |
| 184 | * This macro defines the physical to virtual address mapping for all the | 176 | * This macro defines the physical to virtual address mapping for all the |
| 185 | * peripheral modules. It is used by passing in the physical address as x | 177 | * peripheral modules. It is used by passing in the physical address as x |
| 186 | * and returning the virtual address. If the physical address is not mapped, | 178 | * and returning the virtual address. |
| 187 | * it returns 0. | ||
| 188 | */ | 179 | */ |
| 189 | 180 | #define MXC91231_IO_P2V(x) IMX_IO_P2V(x) | |
| 190 | #define MXC91231_IO_ADDRESS(x) ( \ | 181 | #define MXC91231_IO_ADDRESS(x) IOMEM(MXC91231_IO_P2V(x)) |
| 191 | IMX_IO_ADDRESS(x, MXC91231_L2CC) ?: \ | ||
| 192 | IMX_IO_ADDRESS(x, MXC91231_X_MEMC) ?: \ | ||
| 193 | IMX_IO_ADDRESS(x, MXC91231_ROMP) ?: \ | ||
| 194 | IMX_IO_ADDRESS(x, MXC91231_AVIC) ?: \ | ||
| 195 | IMX_IO_ADDRESS(x, MXC91231_AIPS1) ?: \ | ||
| 196 | IMX_IO_ADDRESS(x, MXC91231_SPBA0) ?: \ | ||
| 197 | IMX_IO_ADDRESS(x, MXC91231_SPBA1) ?: \ | ||
| 198 | IMX_IO_ADDRESS(x, MXC91231_AIPS2)) | ||
| 199 | 182 | ||
| 200 | /* | 183 | /* |
| 201 | * Interrupt numbers | 184 | * Interrupt numbers |
diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h index 7fc5f9946199..a523a4079299 100644 --- a/arch/arm/plat-mxc/include/mach/mxc_ehci.h +++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h | |||
| @@ -31,6 +31,7 @@ | |||
| 31 | #define MXC_USBCTRL_OFFSET 0 | 31 | #define MXC_USBCTRL_OFFSET 0 |
| 32 | #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 | 32 | #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 |
| 33 | #define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc | 33 | #define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc |
| 34 | #define MXC_USBH2CTRL_OFFSET 0x14 | ||
| 34 | 35 | ||
| 35 | #define MX5_USBOTHER_REGS_OFFSET 0x800 | 36 | #define MX5_USBOTHER_REGS_OFFSET 0x800 |
| 36 | 37 | ||
diff --git a/arch/arm/plat-mxc/include/mach/sdma.h b/arch/arm/plat-mxc/include/mach/sdma.h index 9be112227ac4..913e0432e40e 100644 --- a/arch/arm/plat-mxc/include/mach/sdma.h +++ b/arch/arm/plat-mxc/include/mach/sdma.h | |||
| @@ -2,16 +2,62 @@ | |||
| 2 | #define __MACH_MXC_SDMA_H__ | 2 | #define __MACH_MXC_SDMA_H__ |
| 3 | 3 | ||
| 4 | /** | 4 | /** |
| 5 | * struct sdma_script_start_addrs - SDMA script start pointers | ||
| 6 | * | ||
| 7 | * start addresses of the different functions in the physical | ||
| 8 | * address space of the SDMA engine. | ||
| 9 | */ | ||
| 10 | struct sdma_script_start_addrs { | ||
| 11 | s32 ap_2_ap_addr; | ||
| 12 | s32 ap_2_bp_addr; | ||
| 13 | s32 ap_2_ap_fixed_addr; | ||
| 14 | s32 bp_2_ap_addr; | ||
| 15 | s32 loopback_on_dsp_side_addr; | ||
| 16 | s32 mcu_interrupt_only_addr; | ||
| 17 | s32 firi_2_per_addr; | ||
| 18 | s32 firi_2_mcu_addr; | ||
| 19 | s32 per_2_firi_addr; | ||
| 20 | s32 mcu_2_firi_addr; | ||
| 21 | s32 uart_2_per_addr; | ||
| 22 | s32 uart_2_mcu_addr; | ||
| 23 | s32 per_2_app_addr; | ||
| 24 | s32 mcu_2_app_addr; | ||
| 25 | s32 per_2_per_addr; | ||
| 26 | s32 uartsh_2_per_addr; | ||
| 27 | s32 uartsh_2_mcu_addr; | ||
| 28 | s32 per_2_shp_addr; | ||
| 29 | s32 mcu_2_shp_addr; | ||
| 30 | s32 ata_2_mcu_addr; | ||
| 31 | s32 mcu_2_ata_addr; | ||
| 32 | s32 app_2_per_addr; | ||
| 33 | s32 app_2_mcu_addr; | ||
| 34 | s32 shp_2_per_addr; | ||
| 35 | s32 shp_2_mcu_addr; | ||
| 36 | s32 mshc_2_mcu_addr; | ||
| 37 | s32 mcu_2_mshc_addr; | ||
| 38 | s32 spdif_2_mcu_addr; | ||
| 39 | s32 mcu_2_spdif_addr; | ||
| 40 | s32 asrc_2_mcu_addr; | ||
| 41 | s32 ext_mem_2_ipu_addr; | ||
| 42 | s32 descrambler_addr; | ||
| 43 | s32 dptc_dvfs_addr; | ||
| 44 | s32 utra_addr; | ||
| 45 | s32 ram_code_start_addr; | ||
| 46 | }; | ||
| 47 | |||
| 48 | /** | ||
| 5 | * struct sdma_platform_data - platform specific data for SDMA engine | 49 | * struct sdma_platform_data - platform specific data for SDMA engine |
| 6 | * | 50 | * |
| 7 | * @sdma_version The version of this SDMA engine | 51 | * @sdma_version The version of this SDMA engine |
| 8 | * @cpu_name used to generate the firmware name | 52 | * @cpu_name used to generate the firmware name |
| 9 | * @to_version CPU Tape out version | 53 | * @to_version CPU Tape out version |
| 54 | * @script_addrs SDMA scripts addresses in SDMA ROM | ||
| 10 | */ | 55 | */ |
| 11 | struct sdma_platform_data { | 56 | struct sdma_platform_data { |
| 12 | int sdma_version; | 57 | int sdma_version; |
| 13 | char *cpu_name; | 58 | char *cpu_name; |
| 14 | int to_version; | 59 | int to_version; |
| 60 | struct sdma_script_start_addrs *script_addrs; | ||
| 15 | }; | 61 | }; |
| 16 | 62 | ||
| 17 | #endif /* __MACH_MXC_SDMA_H__ */ | 63 | #endif /* __MACH_MXC_SDMA_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index 9dd9c2085aad..3a70ebf0477f 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h | |||
| @@ -63,6 +63,8 @@ static inline void flush(void) | |||
| 63 | #define MX3X_UART1_BASE_ADDR 0x43F90000 | 63 | #define MX3X_UART1_BASE_ADDR 0x43F90000 |
| 64 | #define MX3X_UART2_BASE_ADDR 0x43F94000 | 64 | #define MX3X_UART2_BASE_ADDR 0x43F94000 |
| 65 | #define MX51_UART1_BASE_ADDR 0x73fbc000 | 65 | #define MX51_UART1_BASE_ADDR 0x73fbc000 |
| 66 | #define MX50_UART1_BASE_ADDR 0x53fbc000 | ||
| 67 | #define MX53_UART1_BASE_ADDR 0x53fbc000 | ||
| 66 | 68 | ||
| 67 | static __inline__ void __arch_decomp_setup(unsigned long arch_id) | 69 | static __inline__ void __arch_decomp_setup(unsigned long arch_id) |
| 68 | { | 70 | { |
| @@ -102,6 +104,12 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id) | |||
| 102 | case MACH_TYPE_EUKREA_CPUIMX51SD: | 104 | case MACH_TYPE_EUKREA_CPUIMX51SD: |
| 103 | uart_base = MX51_UART1_BASE_ADDR; | 105 | uart_base = MX51_UART1_BASE_ADDR; |
| 104 | break; | 106 | break; |
| 107 | case MACH_TYPE_MX50_RDP: | ||
| 108 | uart_base = MX50_UART1_BASE_ADDR; | ||
| 109 | break; | ||
| 110 | case MACH_TYPE_MX53_EVK: | ||
| 111 | uart_base = MX53_UART1_BASE_ADDR; | ||
| 112 | break; | ||
| 105 | default: | 113 | default: |
| 106 | break; | 114 | break; |
| 107 | } | 115 | } |
diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/plat-mxc/iomux-v3.c index b318c6a222d5..99a9cdb9d6be 100644 --- a/arch/arm/plat-mxc/iomux-v3.c +++ b/arch/arm/plat-mxc/iomux-v3.c | |||
| @@ -32,31 +32,38 @@ | |||
| 32 | static void __iomem *base; | 32 | static void __iomem *base; |
| 33 | 33 | ||
| 34 | /* | 34 | /* |
| 35 | * setups a single pad in the iomuxer | 35 | * configures a single pad in the iomuxer |
| 36 | */ | 36 | */ |
| 37 | int mxc_iomux_v3_setup_pad(struct pad_desc *pad) | 37 | int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad) |
| 38 | { | 38 | { |
| 39 | if (pad->mux_ctrl_ofs) | 39 | u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT; |
| 40 | __raw_writel(pad->mux_mode, base + pad->mux_ctrl_ofs); | 40 | u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT; |
| 41 | u32 sel_input_ofs = (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT; | ||
| 42 | u32 sel_input = (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT; | ||
| 43 | u32 pad_ctrl_ofs = (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT; | ||
| 44 | u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; | ||
| 41 | 45 | ||
| 42 | if (pad->select_input_ofs) | 46 | if (mux_ctrl_ofs) |
| 43 | __raw_writel(pad->select_input, | 47 | __raw_writel(mux_mode, base + mux_ctrl_ofs); |
| 44 | base + pad->select_input_ofs); | 48 | |
| 49 | if (sel_input_ofs) | ||
| 50 | __raw_writel(sel_input, base + sel_input_ofs); | ||
| 51 | |||
| 52 | if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs) | ||
| 53 | __raw_writel(pad_ctrl, base + pad_ctrl_ofs); | ||
| 45 | 54 | ||
| 46 | if (!(pad->pad_ctrl & NO_PAD_CTRL) && pad->pad_ctrl_ofs) | ||
| 47 | __raw_writel(pad->pad_ctrl, base + pad->pad_ctrl_ofs); | ||
| 48 | return 0; | 55 | return 0; |
| 49 | } | 56 | } |
| 50 | EXPORT_SYMBOL(mxc_iomux_v3_setup_pad); | 57 | EXPORT_SYMBOL(mxc_iomux_v3_setup_pad); |
| 51 | 58 | ||
| 52 | int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count) | 59 | int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count) |
| 53 | { | 60 | { |
| 54 | struct pad_desc *p = pad_list; | 61 | iomux_v3_cfg_t *p = pad_list; |
| 55 | int i; | 62 | int i; |
| 56 | int ret; | 63 | int ret; |
| 57 | 64 | ||
| 58 | for (i = 0; i < count; i++) { | 65 | for (i = 0; i < count; i++) { |
| 59 | ret = mxc_iomux_v3_setup_pad(p); | 66 | ret = mxc_iomux_v3_setup_pad(*p); |
| 60 | if (ret) | 67 | if (ret) |
| 61 | return ret; | 68 | return ret; |
| 62 | p++; | 69 | p++; |
diff --git a/arch/arm/plat-mxc/irq-common.c b/arch/arm/plat-mxc/irq-common.c new file mode 100644 index 000000000000..0c799ac27730 --- /dev/null +++ b/arch/arm/plat-mxc/irq-common.c | |||
| @@ -0,0 +1,60 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) BitBox Ltd 2010 | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation; either version 2 | ||
| 7 | * of the License, or (at your option) any later version. | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License | ||
| 14 | * along with this program; if not, write to the Free Software | ||
| 15 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 16 | * MA 02110-1301, USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/module.h> | ||
| 20 | #include <linux/irq.h> | ||
| 21 | |||
| 22 | #include "irq-common.h" | ||
| 23 | |||
| 24 | int imx_irq_set_priority(unsigned char irq, unsigned char prio) | ||
| 25 | { | ||
| 26 | struct mxc_irq_chip *chip; | ||
| 27 | struct irq_chip *base; | ||
| 28 | int ret; | ||
| 29 | |||
| 30 | ret = -ENOSYS; | ||
| 31 | |||
| 32 | base = get_irq_chip(irq); | ||
| 33 | if (base) { | ||
| 34 | chip = container_of(base, struct mxc_irq_chip, base); | ||
| 35 | if (chip->set_priority) | ||
| 36 | ret = chip->set_priority(irq, prio); | ||
| 37 | } | ||
| 38 | |||
| 39 | return ret; | ||
| 40 | } | ||
| 41 | EXPORT_SYMBOL(imx_irq_set_priority); | ||
| 42 | |||
| 43 | int mxc_set_irq_fiq(unsigned int irq, unsigned int type) | ||
| 44 | { | ||
| 45 | struct mxc_irq_chip *chip; | ||
| 46 | struct irq_chip *base; | ||
| 47 | int ret; | ||
| 48 | |||
| 49 | ret = -ENOSYS; | ||
| 50 | |||
| 51 | base = get_irq_chip(irq); | ||
| 52 | if (base) { | ||
| 53 | chip = container_of(base, struct mxc_irq_chip, base); | ||
| 54 | if (chip->set_irq_fiq) | ||
| 55 | ret = chip->set_irq_fiq(irq, type); | ||
| 56 | } | ||
| 57 | |||
| 58 | return ret; | ||
| 59 | } | ||
| 60 | EXPORT_SYMBOL(mxc_set_irq_fiq); | ||
diff --git a/arch/arm/plat-mxc/irq-common.h b/arch/arm/plat-mxc/irq-common.h new file mode 100644 index 000000000000..7203543fb1b3 --- /dev/null +++ b/arch/arm/plat-mxc/irq-common.h | |||
| @@ -0,0 +1,29 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) BitBox Ltd 2010 | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation; either version 2 | ||
| 7 | * of the License, or (at your option) any later version. | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License | ||
| 14 | * along with this program; if not, write to the Free Software | ||
| 15 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 16 | * MA 02110-1301, USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef __PLAT_MXC_IRQ_COMMON_H__ | ||
| 20 | #define __PLAT_MXC_IRQ_COMMON_H__ | ||
| 21 | |||
| 22 | struct mxc_irq_chip | ||
| 23 | { | ||
| 24 | struct irq_chip base; | ||
| 25 | int (*set_priority)(unsigned char irq, unsigned char prio); | ||
| 26 | int (*set_irq_fiq)(unsigned int irq, unsigned int type); | ||
| 27 | }; | ||
| 28 | |||
| 29 | #endif | ||
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c index 925bce4607e7..3455fc0575a6 100644 --- a/arch/arm/plat-mxc/system.c +++ b/arch/arm/plat-mxc/system.c | |||
| @@ -26,6 +26,7 @@ | |||
| 26 | #include <mach/common.h> | 26 | #include <mach/common.h> |
| 27 | #include <asm/proc-fns.h> | 27 | #include <asm/proc-fns.h> |
| 28 | #include <asm/system.h> | 28 | #include <asm/system.h> |
| 29 | #include <asm/mach-types.h> | ||
| 29 | 30 | ||
| 30 | static void __iomem *wdog_base; | 31 | static void __iomem *wdog_base; |
| 31 | 32 | ||
| @@ -42,12 +43,19 @@ void arch_reset(char mode, const char *cmd) | |||
| 42 | return; | 43 | return; |
| 43 | } | 44 | } |
| 44 | #endif | 45 | #endif |
| 46 | #ifdef CONFIG_MACH_MX51_EFIKAMX | ||
| 47 | if (machine_is_mx51_efikamx()) { | ||
| 48 | mx51_efikamx_reset(); | ||
| 49 | return; | ||
| 50 | } | ||
| 51 | #endif | ||
| 52 | |||
| 45 | if (cpu_is_mx1()) { | 53 | if (cpu_is_mx1()) { |
| 46 | wcr_enable = (1 << 0); | 54 | wcr_enable = (1 << 0); |
| 47 | } else { | 55 | } else { |
| 48 | struct clk *clk; | 56 | struct clk *clk; |
| 49 | 57 | ||
| 50 | clk = clk_get_sys("imx-wdt.0", NULL); | 58 | clk = clk_get_sys("imx2-wdt.0", NULL); |
| 51 | if (!IS_ERR(clk)) | 59 | if (!IS_ERR(clk)) |
| 52 | clk_enable(clk); | 60 | clk_enable(clk); |
| 53 | wcr_enable = (1 << 2); | 61 | wcr_enable = (1 << 2); |
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c index f9a1b059a76c..9f0c2610595e 100644 --- a/arch/arm/plat-mxc/time.c +++ b/arch/arm/plat-mxc/time.c | |||
| @@ -120,7 +120,6 @@ static struct clocksource clocksource_mxc = { | |||
| 120 | .rating = 200, | 120 | .rating = 200, |
| 121 | .read = mx1_2_get_cycles, | 121 | .read = mx1_2_get_cycles, |
| 122 | .mask = CLOCKSOURCE_MASK(32), | 122 | .mask = CLOCKSOURCE_MASK(32), |
| 123 | .shift = 20, | ||
| 124 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 123 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 125 | }; | 124 | }; |
| 126 | 125 | ||
| @@ -131,9 +130,7 @@ static int __init mxc_clocksource_init(struct clk *timer_clk) | |||
| 131 | if (timer_is_v2()) | 130 | if (timer_is_v2()) |
| 132 | clocksource_mxc.read = v2_get_cycles; | 131 | clocksource_mxc.read = v2_get_cycles; |
| 133 | 132 | ||
| 134 | clocksource_mxc.mult = clocksource_hz2mult(c, | 133 | clocksource_register_hz(&clocksource_mxc, c); |
| 135 | clocksource_mxc.shift); | ||
| 136 | clocksource_register(&clocksource_mxc); | ||
| 137 | 134 | ||
| 138 | return 0; | 135 | return 0; |
| 139 | } | 136 | } |
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c index 3703ab28257f..e69ed8a8c203 100644 --- a/arch/arm/plat-mxc/tzic.c +++ b/arch/arm/plat-mxc/tzic.c | |||
| @@ -21,6 +21,8 @@ | |||
| 21 | #include <mach/hardware.h> | 21 | #include <mach/hardware.h> |
| 22 | #include <mach/common.h> | 22 | #include <mach/common.h> |
| 23 | 23 | ||
| 24 | #include "irq-common.h" | ||
| 25 | |||
| 24 | /* | 26 | /* |
| 25 | ***************************************** | 27 | ***************************************** |
| 26 | * TZIC Registers * | 28 | * TZIC Registers * |
| @@ -47,6 +49,25 @@ | |||
| 47 | 49 | ||
| 48 | void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */ | 50 | void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */ |
| 49 | 51 | ||
| 52 | #ifdef CONFIG_FIQ | ||
| 53 | static int tzic_set_irq_fiq(unsigned int irq, unsigned int type) | ||
| 54 | { | ||
| 55 | unsigned int index, mask, value; | ||
| 56 | |||
| 57 | index = irq >> 5; | ||
| 58 | if (unlikely(index >= 4)) | ||
| 59 | return -EINVAL; | ||
| 60 | mask = 1U << (irq & 0x1F); | ||
| 61 | |||
| 62 | value = __raw_readl(tzic_base + TZIC_INTSEC0(index)) | mask; | ||
| 63 | if (type) | ||
| 64 | value &= ~mask; | ||
| 65 | __raw_writel(value, tzic_base + TZIC_INTSEC0(index)); | ||
| 66 | |||
| 67 | return 0; | ||
| 68 | } | ||
| 69 | #endif | ||
| 70 | |||
| 50 | /** | 71 | /** |
| 51 | * tzic_mask_irq() - Disable interrupt number "irq" in the TZIC | 72 | * tzic_mask_irq() - Disable interrupt number "irq" in the TZIC |
| 52 | * | 73 | * |
| @@ -104,12 +125,17 @@ static int tzic_set_wake_irq(unsigned int irq, unsigned int enable) | |||
| 104 | return 0; | 125 | return 0; |
| 105 | } | 126 | } |
| 106 | 127 | ||
| 107 | static struct irq_chip mxc_tzic_chip = { | 128 | static struct mxc_irq_chip mxc_tzic_chip = { |
| 108 | .name = "MXC_TZIC", | 129 | .base = { |
| 109 | .ack = tzic_mask_irq, | 130 | .name = "MXC_TZIC", |
| 110 | .mask = tzic_mask_irq, | 131 | .ack = tzic_mask_irq, |
| 111 | .unmask = tzic_unmask_irq, | 132 | .mask = tzic_mask_irq, |
| 112 | .set_wake = tzic_set_wake_irq, | 133 | .unmask = tzic_unmask_irq, |
| 134 | .set_wake = tzic_set_wake_irq, | ||
| 135 | }, | ||
| 136 | #ifdef CONFIG_FIQ | ||
| 137 | .set_irq_fiq = tzic_set_irq_fiq, | ||
| 138 | #endif | ||
| 113 | }; | 139 | }; |
| 114 | 140 | ||
| 115 | /* | 141 | /* |
| @@ -141,10 +167,16 @@ void __init tzic_init_irq(void __iomem *irqbase) | |||
| 141 | /* all IRQ no FIQ Warning :: No selection */ | 167 | /* all IRQ no FIQ Warning :: No selection */ |
| 142 | 168 | ||
| 143 | for (i = 0; i < MXC_INTERNAL_IRQS; i++) { | 169 | for (i = 0; i < MXC_INTERNAL_IRQS; i++) { |
| 144 | set_irq_chip(i, &mxc_tzic_chip); | 170 | set_irq_chip(i, &mxc_tzic_chip.base); |
| 145 | set_irq_handler(i, handle_level_irq); | 171 | set_irq_handler(i, handle_level_irq); |
| 146 | set_irq_flags(i, IRQF_VALID); | 172 | set_irq_flags(i, IRQF_VALID); |
| 147 | } | 173 | } |
| 174 | |||
| 175 | #ifdef CONFIG_FIQ | ||
| 176 | /* Initialize FIQ */ | ||
| 177 | init_FIQ(); | ||
| 178 | #endif | ||
| 179 | |||
| 148 | pr_info("TrustZone Interrupt Controller (TZIC) initialized\n"); | 180 | pr_info("TrustZone Interrupt Controller (TZIC) initialized\n"); |
| 149 | } | 181 | } |
| 150 | 182 | ||
diff --git a/arch/arm/plat-nomadik/Kconfig b/arch/arm/plat-nomadik/Kconfig index 5da3f97c537b..187f4e84bb22 100644 --- a/arch/arm/plat-nomadik/Kconfig +++ b/arch/arm/plat-nomadik/Kconfig | |||
| @@ -14,6 +14,7 @@ if PLAT_NOMADIK | |||
| 14 | 14 | ||
| 15 | config HAS_MTU | 15 | config HAS_MTU |
| 16 | bool | 16 | bool |
| 17 | select HAVE_SCHED_CLOCK | ||
| 17 | help | 18 | help |
| 18 | Support for Multi Timer Unit. MTU provides access | 19 | Support for Multi Timer Unit. MTU provides access |
| 19 | to multiple interrupt generating programmable | 20 | to multiple interrupt generating programmable |
diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c index 85e6fd212a41..eda4e3a11a3d 100644 --- a/arch/arm/plat-nomadik/gpio.c +++ b/arch/arm/plat-nomadik/gpio.c | |||
| @@ -119,7 +119,7 @@ static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, | |||
| 119 | } | 119 | } |
| 120 | 120 | ||
| 121 | static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, | 121 | static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, |
| 122 | pin_cfg_t cfg) | 122 | pin_cfg_t cfg, bool sleep) |
| 123 | { | 123 | { |
| 124 | static const char *afnames[] = { | 124 | static const char *afnames[] = { |
| 125 | [NMK_GPIO_ALT_GPIO] = "GPIO", | 125 | [NMK_GPIO_ALT_GPIO] = "GPIO", |
| @@ -145,11 +145,34 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, | |||
| 145 | int output = PIN_DIR(cfg); | 145 | int output = PIN_DIR(cfg); |
| 146 | int val = PIN_VAL(cfg); | 146 | int val = PIN_VAL(cfg); |
| 147 | 147 | ||
| 148 | dev_dbg(nmk_chip->chip.dev, "pin %d: af %s, pull %s, slpm %s (%s%s)\n", | 148 | dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n", |
| 149 | pin, afnames[af], pullnames[pull], slpmnames[slpm], | 149 | pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm], |
| 150 | output ? "output " : "input", | 150 | output ? "output " : "input", |
| 151 | output ? (val ? "high" : "low") : ""); | 151 | output ? (val ? "high" : "low") : ""); |
| 152 | 152 | ||
| 153 | if (sleep) { | ||
| 154 | int slpm_pull = PIN_SLPM_PULL(cfg); | ||
| 155 | int slpm_output = PIN_SLPM_DIR(cfg); | ||
| 156 | int slpm_val = PIN_SLPM_VAL(cfg); | ||
| 157 | |||
| 158 | /* | ||
| 159 | * The SLPM_* values are normal values + 1 to allow zero to | ||
| 160 | * mean "same as normal". | ||
| 161 | */ | ||
| 162 | if (slpm_pull) | ||
| 163 | pull = slpm_pull - 1; | ||
| 164 | if (slpm_output) | ||
| 165 | output = slpm_output - 1; | ||
| 166 | if (slpm_val) | ||
| 167 | val = slpm_val - 1; | ||
| 168 | |||
| 169 | dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n", | ||
| 170 | pin, | ||
| 171 | slpm_pull ? pullnames[pull] : "same", | ||
| 172 | slpm_output ? (output ? "output" : "input") : "same", | ||
| 173 | slpm_val ? (val ? "high" : "low") : "same"); | ||
| 174 | } | ||
| 175 | |||
| 153 | if (output) | 176 | if (output) |
| 154 | __nmk_gpio_make_output(nmk_chip, offset, val); | 177 | __nmk_gpio_make_output(nmk_chip, offset, val); |
| 155 | else { | 178 | else { |
| @@ -175,7 +198,7 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, | |||
| 175 | * side-effects. The gpio can be manipulated later using standard GPIO API | 198 | * side-effects. The gpio can be manipulated later using standard GPIO API |
| 176 | * calls. | 199 | * calls. |
| 177 | */ | 200 | */ |
| 178 | int nmk_config_pin(pin_cfg_t cfg) | 201 | int nmk_config_pin(pin_cfg_t cfg, bool sleep) |
| 179 | { | 202 | { |
| 180 | struct nmk_gpio_chip *nmk_chip; | 203 | struct nmk_gpio_chip *nmk_chip; |
| 181 | int gpio = PIN_NUM(cfg); | 204 | int gpio = PIN_NUM(cfg); |
| @@ -186,7 +209,7 @@ int nmk_config_pin(pin_cfg_t cfg) | |||
| 186 | return -EINVAL; | 209 | return -EINVAL; |
| 187 | 210 | ||
| 188 | spin_lock_irqsave(&nmk_chip->lock, flags); | 211 | spin_lock_irqsave(&nmk_chip->lock, flags); |
| 189 | __nmk_config_pin(nmk_chip, gpio - nmk_chip->chip.base, cfg); | 212 | __nmk_config_pin(nmk_chip, gpio - nmk_chip->chip.base, cfg, sleep); |
| 190 | spin_unlock_irqrestore(&nmk_chip->lock, flags); | 213 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
| 191 | 214 | ||
| 192 | return 0; | 215 | return 0; |
| @@ -207,7 +230,7 @@ int nmk_config_pins(pin_cfg_t *cfgs, int num) | |||
| 207 | int i; | 230 | int i; |
| 208 | 231 | ||
| 209 | for (i = 0; i < num; i++) { | 232 | for (i = 0; i < num; i++) { |
| 210 | int ret = nmk_config_pin(cfgs[i]); | 233 | ret = nmk_config_pin(cfgs[i], false); |
| 211 | if (ret) | 234 | if (ret) |
| 212 | break; | 235 | break; |
| 213 | } | 236 | } |
| @@ -216,6 +239,21 @@ int nmk_config_pins(pin_cfg_t *cfgs, int num) | |||
| 216 | } | 239 | } |
| 217 | EXPORT_SYMBOL(nmk_config_pins); | 240 | EXPORT_SYMBOL(nmk_config_pins); |
| 218 | 241 | ||
| 242 | int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num) | ||
| 243 | { | ||
| 244 | int ret = 0; | ||
| 245 | int i; | ||
| 246 | |||
| 247 | for (i = 0; i < num; i++) { | ||
| 248 | ret = nmk_config_pin(cfgs[i], true); | ||
| 249 | if (ret) | ||
| 250 | break; | ||
| 251 | } | ||
| 252 | |||
| 253 | return ret; | ||
| 254 | } | ||
| 255 | EXPORT_SYMBOL(nmk_config_pins_sleep); | ||
| 256 | |||
| 219 | /** | 257 | /** |
| 220 | * nmk_gpio_set_slpm() - configure the sleep mode of a pin | 258 | * nmk_gpio_set_slpm() - configure the sleep mode of a pin |
| 221 | * @gpio: pin number | 259 | * @gpio: pin number |
| @@ -634,7 +672,7 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev) | |||
| 634 | 672 | ||
| 635 | chip = &nmk_chip->chip; | 673 | chip = &nmk_chip->chip; |
| 636 | chip->base = pdata->first_gpio; | 674 | chip->base = pdata->first_gpio; |
| 637 | chip->label = pdata->name; | 675 | chip->label = pdata->name ?: dev_name(&dev->dev); |
| 638 | chip->dev = &dev->dev; | 676 | chip->dev = &dev->dev; |
| 639 | chip->owner = THIS_MODULE; | 677 | chip->owner = THIS_MODULE; |
| 640 | 678 | ||
diff --git a/arch/arm/plat-nomadik/include/plat/pincfg.h b/arch/arm/plat-nomadik/include/plat/pincfg.h index 8c5ae3f2acf8..05a3936ae6d1 100644 --- a/arch/arm/plat-nomadik/include/plat/pincfg.h +++ b/arch/arm/plat-nomadik/include/plat/pincfg.h | |||
| @@ -19,16 +19,22 @@ | |||
| 19 | * bit 9..10 - Alternate Function Selection | 19 | * bit 9..10 - Alternate Function Selection |
| 20 | * bit 11..12 - Pull up/down state | 20 | * bit 11..12 - Pull up/down state |
| 21 | * bit 13 - Sleep mode behaviour | 21 | * bit 13 - Sleep mode behaviour |
| 22 | * bit 14 - (sleep mode) Direction | 22 | * bit 14 - Direction |
| 23 | * bit 15 - (sleep mode) Value (if output) | 23 | * bit 15 - Value (if output) |
| 24 | * bit 16..18 - SLPM pull up/down state | ||
| 25 | * bit 19..20 - SLPM direction | ||
| 26 | * bit 21..22 - SLPM Value (if output) | ||
| 24 | * | 27 | * |
| 25 | * to facilitate the definition, the following macros are provided | 28 | * to facilitate the definition, the following macros are provided |
| 26 | * | 29 | * |
| 27 | * PIN_CFG_DEFAULT - default config (0): | 30 | * PIN_CFG_DEFAULT - default config (0): |
| 28 | * pull up/down = disabled | 31 | * pull up/down = disabled |
| 29 | * sleep mode = input/wakeup | 32 | * sleep mode = input/wakeup |
| 30 | * (sleep mode) direction = input | 33 | * direction = input |
| 31 | * (sleep mode) value = low | 34 | * value = low |
| 35 | * SLPM direction = same as normal | ||
| 36 | * SLPM pull = same as normal | ||
| 37 | * SLPM value = same as normal | ||
| 32 | * | 38 | * |
| 33 | * PIN_CFG - default config with alternate function | 39 | * PIN_CFG - default config with alternate function |
| 34 | * PIN_CFG_PULL - default config with alternate function and pull up/down | 40 | * PIN_CFG_PULL - default config with alternate function and pull up/down |
| @@ -75,30 +81,64 @@ typedef unsigned long pin_cfg_t; | |||
| 75 | #define PIN_VAL_LOW (0 << PIN_VAL_SHIFT) | 81 | #define PIN_VAL_LOW (0 << PIN_VAL_SHIFT) |
| 76 | #define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT) | 82 | #define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT) |
| 77 | 83 | ||
| 78 | /* Shortcuts. Use these instead of separate DIR and VAL. */ | 84 | #define PIN_SLPM_PULL_SHIFT 16 |
| 79 | #define PIN_INPUT PIN_DIR_INPUT | 85 | #define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT) |
| 86 | #define PIN_SLPM_PULL(x) \ | ||
| 87 | (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT) | ||
| 88 | #define PIN_SLPM_PULL_NONE \ | ||
| 89 | ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT) | ||
| 90 | #define PIN_SLPM_PULL_UP \ | ||
| 91 | ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT) | ||
| 92 | #define PIN_SLPM_PULL_DOWN \ | ||
| 93 | ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT) | ||
| 94 | |||
| 95 | #define PIN_SLPM_DIR_SHIFT 19 | ||
| 96 | #define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT) | ||
| 97 | #define PIN_SLPM_DIR(x) \ | ||
| 98 | (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT) | ||
| 99 | #define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT) | ||
| 100 | #define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT) | ||
| 101 | |||
| 102 | #define PIN_SLPM_VAL_SHIFT 21 | ||
| 103 | #define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT) | ||
| 104 | #define PIN_SLPM_VAL(x) \ | ||
| 105 | (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT) | ||
| 106 | #define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT) | ||
| 107 | #define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT) | ||
| 108 | |||
| 109 | /* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */ | ||
| 110 | #define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN) | ||
| 111 | #define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP) | ||
| 112 | #define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE) | ||
| 80 | #define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW) | 113 | #define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW) |
| 81 | #define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH) | 114 | #define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH) |
| 82 | 115 | ||
| 83 | /* | 116 | #define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN) |
| 84 | * These are the same as the ones above, but should make more sense to the | 117 | #define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP) |
| 85 | * reader when seen along with a setting a pin to AF mode. | 118 | #define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE) |
| 86 | */ | 119 | #define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW) |
| 87 | #define PIN_SLPM_INPUT PIN_INPUT | 120 | #define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH) |
| 88 | #define PIN_SLPM_OUTPUT_LOW PIN_OUTPUT_LOW | ||
| 89 | #define PIN_SLPM_OUTPUT_HIGH PIN_OUTPUT_HIGH | ||
| 90 | 121 | ||
| 91 | #define PIN_CFG_DEFAULT (PIN_PULL_NONE | PIN_SLPM_INPUT) | 122 | #define PIN_CFG_DEFAULT (0) |
| 92 | 123 | ||
| 93 | #define PIN_CFG(num, alt) \ | 124 | #define PIN_CFG(num, alt) \ |
| 94 | (PIN_CFG_DEFAULT |\ | 125 | (PIN_CFG_DEFAULT |\ |
| 95 | (PIN_NUM(num) | PIN_##alt)) | 126 | (PIN_NUM(num) | PIN_##alt)) |
| 96 | 127 | ||
| 128 | #define PIN_CFG_INPUT(num, alt, pull) \ | ||
| 129 | (PIN_CFG_DEFAULT |\ | ||
| 130 | (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull)) | ||
| 131 | |||
| 132 | #define PIN_CFG_OUTPUT(num, alt, val) \ | ||
| 133 | (PIN_CFG_DEFAULT |\ | ||
| 134 | (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val)) | ||
| 135 | |||
| 97 | #define PIN_CFG_PULL(num, alt, pull) \ | 136 | #define PIN_CFG_PULL(num, alt, pull) \ |
| 98 | ((PIN_CFG_DEFAULT & ~PIN_PULL_MASK) |\ | 137 | ((PIN_CFG_DEFAULT & ~PIN_PULL_MASK) |\ |
| 99 | (PIN_NUM(num) | PIN_##alt | PIN_PULL_##pull)) | 138 | (PIN_NUM(num) | PIN_##alt | PIN_PULL_##pull)) |
| 100 | 139 | ||
| 101 | extern int nmk_config_pin(pin_cfg_t cfg); | 140 | extern int nmk_config_pin(pin_cfg_t cfg, bool sleep); |
| 102 | extern int nmk_config_pins(pin_cfg_t *cfgs, int num); | 141 | extern int nmk_config_pins(pin_cfg_t *cfgs, int num); |
| 142 | extern int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num); | ||
| 103 | 143 | ||
| 104 | #endif | 144 | #endif |
diff --git a/arch/arm/plat-nomadik/timer.c b/arch/arm/plat-nomadik/timer.c index 63cdc6025bd7..41723402006b 100644 --- a/arch/arm/plat-nomadik/timer.c +++ b/arch/arm/plat-nomadik/timer.c | |||
| @@ -17,9 +17,9 @@ | |||
| 17 | #include <linux/clk.h> | 17 | #include <linux/clk.h> |
| 18 | #include <linux/jiffies.h> | 18 | #include <linux/jiffies.h> |
| 19 | #include <linux/err.h> | 19 | #include <linux/err.h> |
| 20 | #include <linux/cnt32_to_63.h> | 20 | #include <linux/sched.h> |
| 21 | #include <linux/timer.h> | ||
| 22 | #include <asm/mach/time.h> | 21 | #include <asm/mach/time.h> |
| 22 | #include <asm/sched_clock.h> | ||
| 23 | 23 | ||
| 24 | #include <plat/mtu.h> | 24 | #include <plat/mtu.h> |
| 25 | 25 | ||
| @@ -52,81 +52,24 @@ static struct clocksource nmdk_clksrc = { | |||
| 52 | * Override the global weak sched_clock symbol with this | 52 | * Override the global weak sched_clock symbol with this |
| 53 | * local implementation which uses the clocksource to get some | 53 | * local implementation which uses the clocksource to get some |
| 54 | * better resolution when scheduling the kernel. | 54 | * better resolution when scheduling the kernel. |
| 55 | * | ||
| 56 | * Because the hardware timer period may be quite short | ||
| 57 | * (32.3 secs on the 133 MHz MTU timer selection on ux500) | ||
| 58 | * and because cnt32_to_63() needs to be called at least once per | ||
| 59 | * half period to work properly, a kernel keepwarm() timer is set up | ||
| 60 | * to ensure this requirement is always met. | ||
| 61 | * | ||
| 62 | * Also the sched_clock timer will wrap around at some point, | ||
| 63 | * here we set it to run continously for a year. | ||
| 64 | */ | 55 | */ |
| 65 | #define SCHED_CLOCK_MIN_WRAP 3600*24*365 | 56 | static DEFINE_CLOCK_DATA(cd); |
| 66 | static struct timer_list cnt32_to_63_keepwarm_timer; | ||
| 67 | static u32 sched_mult; | ||
| 68 | static u32 sched_shift; | ||
| 69 | 57 | ||
| 70 | unsigned long long notrace sched_clock(void) | 58 | unsigned long long notrace sched_clock(void) |
| 71 | { | 59 | { |
| 72 | u64 cycles; | 60 | u32 cyc; |
| 73 | 61 | ||
| 74 | if (unlikely(!mtu_base)) | 62 | if (unlikely(!mtu_base)) |
| 75 | return 0; | 63 | return 0; |
| 76 | 64 | ||
| 77 | cycles = cnt32_to_63(-readl(mtu_base + MTU_VAL(0))); | 65 | cyc = -readl(mtu_base + MTU_VAL(0)); |
| 78 | /* | 66 | return cyc_to_sched_clock(&cd, cyc, (u32)~0); |
| 79 | * sched_mult is guaranteed to be even so will | ||
| 80 | * shift out bit 63 | ||
| 81 | */ | ||
| 82 | return (cycles * sched_mult) >> sched_shift; | ||
| 83 | } | 67 | } |
| 84 | 68 | ||
| 85 | /* Just kick sched_clock every so often */ | 69 | static void notrace nomadik_update_sched_clock(void) |
| 86 | static void cnt32_to_63_keepwarm(unsigned long data) | ||
| 87 | { | 70 | { |
| 88 | mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data)); | 71 | u32 cyc = -readl(mtu_base + MTU_VAL(0)); |
| 89 | (void) sched_clock(); | 72 | update_sched_clock(&cd, cyc, (u32)~0); |
| 90 | } | ||
| 91 | |||
| 92 | /* | ||
| 93 | * Set up a timer to keep sched_clock():s 32_to_63 algorithm warm | ||
| 94 | * once in half a 32bit timer wrap interval. | ||
| 95 | */ | ||
| 96 | static void __init nmdk_sched_clock_init(unsigned long rate) | ||
| 97 | { | ||
| 98 | u32 v; | ||
| 99 | unsigned long delta; | ||
| 100 | u64 days; | ||
| 101 | |||
| 102 | /* Find the apropriate mult and shift factors */ | ||
| 103 | clocks_calc_mult_shift(&sched_mult, &sched_shift, | ||
| 104 | rate, NSEC_PER_SEC, SCHED_CLOCK_MIN_WRAP); | ||
| 105 | /* We need to multiply by an even number to get rid of bit 63 */ | ||
| 106 | if (sched_mult & 1) | ||
| 107 | sched_mult++; | ||
| 108 | |||
| 109 | /* Let's see what we get, take max counter and scale it */ | ||
| 110 | days = (0xFFFFFFFFFFFFFFFFLLU * sched_mult) >> sched_shift; | ||
| 111 | do_div(days, NSEC_PER_SEC); | ||
| 112 | do_div(days, (3600*24)); | ||
| 113 | |||
| 114 | pr_info("sched_clock: using %d bits @ %lu Hz wrap in %lu days\n", | ||
| 115 | (64 - sched_shift), rate, (unsigned long) days); | ||
| 116 | |||
| 117 | /* | ||
| 118 | * Program a timer to kick us at half 32bit wraparound | ||
| 119 | * Formula: seconds per wrap = (2^32) / f | ||
| 120 | */ | ||
| 121 | v = 0xFFFFFFFFUL / rate; | ||
| 122 | /* We want half of the wrap time to keep cnt32_to_63 warm */ | ||
| 123 | v /= 2; | ||
| 124 | pr_debug("sched_clock: prescaled timer rate: %lu Hz, " | ||
| 125 | "initialize keepwarm timer every %d seconds\n", rate, v); | ||
| 126 | /* Convert seconds to jiffies */ | ||
| 127 | delta = msecs_to_jiffies(v*1000); | ||
| 128 | setup_timer(&cnt32_to_63_keepwarm_timer, cnt32_to_63_keepwarm, delta); | ||
| 129 | mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + delta)); | ||
| 130 | } | 73 | } |
| 131 | 74 | ||
| 132 | /* Clockevent device: use one-shot mode */ | 75 | /* Clockevent device: use one-shot mode */ |
| @@ -222,7 +165,6 @@ void __init nmdk_timer_init(void) | |||
| 222 | } else { | 165 | } else { |
| 223 | cr |= MTU_CRn_PRESCALE_1; | 166 | cr |= MTU_CRn_PRESCALE_1; |
| 224 | } | 167 | } |
| 225 | clocksource_calc_mult_shift(&nmdk_clksrc, rate, MTU_MIN_RANGE); | ||
| 226 | 168 | ||
| 227 | /* Timer 0 is the free running clocksource */ | 169 | /* Timer 0 is the free running clocksource */ |
| 228 | writel(cr, mtu_base + MTU_CR(0)); | 170 | writel(cr, mtu_base + MTU_CR(0)); |
| @@ -233,11 +175,11 @@ void __init nmdk_timer_init(void) | |||
| 233 | /* Now the clock source is ready */ | 175 | /* Now the clock source is ready */ |
| 234 | nmdk_clksrc.read = nmdk_read_timer; | 176 | nmdk_clksrc.read = nmdk_read_timer; |
| 235 | 177 | ||
| 236 | if (clocksource_register(&nmdk_clksrc)) | 178 | if (clocksource_register_hz(&nmdk_clksrc, rate)) |
| 237 | pr_err("timer: failed to initialize clock source %s\n", | 179 | pr_err("timer: failed to initialize clock source %s\n", |
| 238 | nmdk_clksrc.name); | 180 | nmdk_clksrc.name); |
| 239 | 181 | ||
| 240 | nmdk_sched_clock_init(rate); | 182 | init_sched_clock(&cd, nomadik_update_sched_clock, 32, rate); |
| 241 | 183 | ||
| 242 | /* Timer 1 is used for events */ | 184 | /* Timer 1 is used for events */ |
| 243 | 185 | ||
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index 92c5bb7909f5..18fe3cb195dc 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig | |||
| @@ -11,13 +11,14 @@ choice | |||
| 11 | 11 | ||
| 12 | config ARCH_OMAP1 | 12 | config ARCH_OMAP1 |
| 13 | bool "TI OMAP1" | 13 | bool "TI OMAP1" |
| 14 | select COMMON_CLKDEV | 14 | select CLKDEV_LOOKUP |
| 15 | help | 15 | help |
| 16 | "Systems based on omap7xx, omap15xx or omap16xx" | 16 | "Systems based on omap7xx, omap15xx or omap16xx" |
| 17 | 17 | ||
| 18 | config ARCH_OMAP2PLUS | 18 | config ARCH_OMAP2PLUS |
| 19 | bool "TI OMAP2/3/4" | 19 | bool "TI OMAP2/3/4" |
| 20 | select COMMON_CLKDEV | 20 | select CLKDEV_LOOKUP |
| 21 | select OMAP_DM_TIMER | ||
| 21 | help | 22 | help |
| 22 | "Systems based on OMAP2, OMAP3 or OMAP4" | 23 | "Systems based on OMAP2, OMAP3 or OMAP4" |
| 23 | 24 | ||
| @@ -35,6 +36,37 @@ config OMAP_DEBUG_LEDS | |||
| 35 | depends on OMAP_DEBUG_DEVICES | 36 | depends on OMAP_DEBUG_DEVICES |
| 36 | default y if LEDS_CLASS | 37 | default y if LEDS_CLASS |
| 37 | 38 | ||
| 39 | config OMAP_SMARTREFLEX | ||
| 40 | bool "SmartReflex support" | ||
| 41 | depends on (ARCH_OMAP3 || ARCH_OMAP4) && PM | ||
| 42 | help | ||
| 43 | Say Y if you want to enable SmartReflex. | ||
| 44 | |||
| 45 | SmartReflex can perform continuous dynamic voltage | ||
| 46 | scaling around the nominal operating point voltage | ||
| 47 | according to silicon characteristics and operating | ||
| 48 | conditions. Enabling SmartReflex reduces power | ||
| 49 | consumption. | ||
| 50 | |||
| 51 | Please note, that by default SmartReflex is only | ||
| 52 | initialized. To enable the automatic voltage | ||
| 53 | compensation for vdd mpu and vdd core from user space, | ||
| 54 | user must write 1 to | ||
| 55 | /debug/voltage/vdd_<X>/smartreflex/autocomp, | ||
| 56 | where X is mpu or core for OMAP3. | ||
| 57 | Optionallly autocompensation can be enabled in the kernel | ||
| 58 | by default during system init via the enable_on_init flag | ||
| 59 | which an be passed as platform data to the smartreflex driver. | ||
| 60 | |||
| 61 | config OMAP_SMARTREFLEX_CLASS3 | ||
| 62 | bool "Class 3 mode of Smartreflex Implementation" | ||
| 63 | depends on OMAP_SMARTREFLEX && TWL4030_CORE | ||
| 64 | help | ||
| 65 | Say Y to enable Class 3 implementation of Smartreflex | ||
| 66 | |||
| 67 | Class 3 implementation of Smartreflex employs continuous hardware | ||
| 68 | voltage calibration. | ||
| 69 | |||
| 38 | config OMAP_RESET_CLOCKS | 70 | config OMAP_RESET_CLOCKS |
| 39 | bool "Reset unused clocks during boot" | 71 | bool "Reset unused clocks during boot" |
| 40 | depends on ARCH_OMAP | 72 | depends on ARCH_OMAP |
| @@ -109,6 +141,9 @@ config OMAP_IOMMU_DEBUG | |||
| 109 | 141 | ||
| 110 | Say N unless you know you need this. | 142 | Say N unless you know you need this. |
| 111 | 143 | ||
| 144 | config OMAP_IOMMU_IVA2 | ||
| 145 | bool | ||
| 146 | |||
| 112 | choice | 147 | choice |
| 113 | prompt "System timer" | 148 | prompt "System timer" |
| 114 | default OMAP_32K_TIMER if !ARCH_OMAP15XX | 149 | default OMAP_32K_TIMER if !ARCH_OMAP15XX |
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c index 8722a136f3a5..ea4644021fb9 100644 --- a/arch/arm/plat-omap/counter_32k.c +++ b/arch/arm/plat-omap/counter_32k.c | |||
| @@ -15,8 +15,11 @@ | |||
| 15 | #include <linux/kernel.h> | 15 | #include <linux/kernel.h> |
| 16 | #include <linux/init.h> | 16 | #include <linux/init.h> |
| 17 | #include <linux/clk.h> | 17 | #include <linux/clk.h> |
| 18 | #include <linux/io.h> | ||
| 19 | #include <linux/err.h> | 18 | #include <linux/err.h> |
| 19 | #include <linux/io.h> | ||
| 20 | #include <linux/sched.h> | ||
| 21 | |||
| 22 | #include <asm/sched_clock.h> | ||
| 20 | 23 | ||
| 21 | #include <plat/common.h> | 24 | #include <plat/common.h> |
| 22 | #include <plat/board.h> | 25 | #include <plat/board.h> |
| @@ -45,7 +48,7 @@ | |||
| 45 | static u32 offset_32k __read_mostly; | 48 | static u32 offset_32k __read_mostly; |
| 46 | 49 | ||
| 47 | #ifdef CONFIG_ARCH_OMAP16XX | 50 | #ifdef CONFIG_ARCH_OMAP16XX |
| 48 | static cycle_t omap16xx_32k_read(struct clocksource *cs) | 51 | static cycle_t notrace omap16xx_32k_read(struct clocksource *cs) |
| 49 | { | 52 | { |
| 50 | return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED) - offset_32k; | 53 | return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED) - offset_32k; |
| 51 | } | 54 | } |
| @@ -54,7 +57,7 @@ static cycle_t omap16xx_32k_read(struct clocksource *cs) | |||
| 54 | #endif | 57 | #endif |
| 55 | 58 | ||
| 56 | #ifdef CONFIG_ARCH_OMAP2420 | 59 | #ifdef CONFIG_ARCH_OMAP2420 |
| 57 | static cycle_t omap2420_32k_read(struct clocksource *cs) | 60 | static cycle_t notrace omap2420_32k_read(struct clocksource *cs) |
| 58 | { | 61 | { |
| 59 | return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10) - offset_32k; | 62 | return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10) - offset_32k; |
| 60 | } | 63 | } |
| @@ -63,7 +66,7 @@ static cycle_t omap2420_32k_read(struct clocksource *cs) | |||
| 63 | #endif | 66 | #endif |
| 64 | 67 | ||
| 65 | #ifdef CONFIG_ARCH_OMAP2430 | 68 | #ifdef CONFIG_ARCH_OMAP2430 |
| 66 | static cycle_t omap2430_32k_read(struct clocksource *cs) | 69 | static cycle_t notrace omap2430_32k_read(struct clocksource *cs) |
| 67 | { | 70 | { |
| 68 | return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10) - offset_32k; | 71 | return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10) - offset_32k; |
| 69 | } | 72 | } |
| @@ -72,7 +75,7 @@ static cycle_t omap2430_32k_read(struct clocksource *cs) | |||
| 72 | #endif | 75 | #endif |
| 73 | 76 | ||
| 74 | #ifdef CONFIG_ARCH_OMAP3 | 77 | #ifdef CONFIG_ARCH_OMAP3 |
| 75 | static cycle_t omap34xx_32k_read(struct clocksource *cs) | 78 | static cycle_t notrace omap34xx_32k_read(struct clocksource *cs) |
| 76 | { | 79 | { |
| 77 | return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10) - offset_32k; | 80 | return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10) - offset_32k; |
| 78 | } | 81 | } |
| @@ -81,7 +84,7 @@ static cycle_t omap34xx_32k_read(struct clocksource *cs) | |||
| 81 | #endif | 84 | #endif |
| 82 | 85 | ||
| 83 | #ifdef CONFIG_ARCH_OMAP4 | 86 | #ifdef CONFIG_ARCH_OMAP4 |
| 84 | static cycle_t omap44xx_32k_read(struct clocksource *cs) | 87 | static cycle_t notrace omap44xx_32k_read(struct clocksource *cs) |
| 85 | { | 88 | { |
| 86 | return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10) - offset_32k; | 89 | return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10) - offset_32k; |
| 87 | } | 90 | } |
| @@ -93,7 +96,7 @@ static cycle_t omap44xx_32k_read(struct clocksource *cs) | |||
| 93 | * Kernel assumes that sched_clock can be called early but may not have | 96 | * Kernel assumes that sched_clock can be called early but may not have |
| 94 | * things ready yet. | 97 | * things ready yet. |
| 95 | */ | 98 | */ |
| 96 | static cycle_t omap_32k_read_dummy(struct clocksource *cs) | 99 | static cycle_t notrace omap_32k_read_dummy(struct clocksource *cs) |
| 97 | { | 100 | { |
| 98 | return 0; | 101 | return 0; |
| 99 | } | 102 | } |
| @@ -103,7 +106,6 @@ static struct clocksource clocksource_32k = { | |||
| 103 | .rating = 250, | 106 | .rating = 250, |
| 104 | .read = omap_32k_read_dummy, | 107 | .read = omap_32k_read_dummy, |
| 105 | .mask = CLOCKSOURCE_MASK(32), | 108 | .mask = CLOCKSOURCE_MASK(32), |
| 106 | .shift = 10, | ||
| 107 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 109 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 108 | }; | 110 | }; |
| 109 | 111 | ||
| @@ -111,10 +113,25 @@ static struct clocksource clocksource_32k = { | |||
| 111 | * Returns current time from boot in nsecs. It's OK for this to wrap | 113 | * Returns current time from boot in nsecs. It's OK for this to wrap |
| 112 | * around for now, as it's just a relative time stamp. | 114 | * around for now, as it's just a relative time stamp. |
| 113 | */ | 115 | */ |
| 114 | unsigned long long sched_clock(void) | 116 | static DEFINE_CLOCK_DATA(cd); |
| 117 | |||
| 118 | /* | ||
| 119 | * Constants generated by clocks_calc_mult_shift(m, s, 32768, NSEC_PER_SEC, 60). | ||
| 120 | * This gives a resolution of about 30us and a wrap period of about 36hrs. | ||
| 121 | */ | ||
| 122 | #define SC_MULT 4000000000u | ||
| 123 | #define SC_SHIFT 17 | ||
| 124 | |||
| 125 | unsigned long long notrace sched_clock(void) | ||
| 126 | { | ||
| 127 | u32 cyc = clocksource_32k.read(&clocksource_32k); | ||
| 128 | return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT); | ||
| 129 | } | ||
| 130 | |||
| 131 | static void notrace omap_update_sched_clock(void) | ||
| 115 | { | 132 | { |
| 116 | return clocksource_cyc2ns(clocksource_32k.read(&clocksource_32k), | 133 | u32 cyc = clocksource_32k.read(&clocksource_32k); |
| 117 | clocksource_32k.mult, clocksource_32k.shift); | 134 | update_sched_clock(&cd, cyc, (u32)~0); |
| 118 | } | 135 | } |
| 119 | 136 | ||
| 120 | /** | 137 | /** |
| @@ -168,13 +185,13 @@ static int __init omap_init_clocksource_32k(void) | |||
| 168 | if (!IS_ERR(sync_32k_ick)) | 185 | if (!IS_ERR(sync_32k_ick)) |
| 169 | clk_enable(sync_32k_ick); | 186 | clk_enable(sync_32k_ick); |
| 170 | 187 | ||
| 171 | clocksource_32k.mult = clocksource_hz2mult(32768, | ||
| 172 | clocksource_32k.shift); | ||
| 173 | |||
| 174 | offset_32k = clocksource_32k.read(&clocksource_32k); | 188 | offset_32k = clocksource_32k.read(&clocksource_32k); |
| 175 | 189 | ||
| 176 | if (clocksource_register(&clocksource_32k)) | 190 | if (clocksource_register_hz(&clocksource_32k, 32768)) |
| 177 | printk(err, clocksource_32k.name); | 191 | printk(err, clocksource_32k.name); |
| 192 | |||
| 193 | init_fixed_sched_clock(&cd, omap_update_sched_clock, 32, | ||
| 194 | 32768, SC_MULT, SC_SHIFT); | ||
| 178 | } | 195 | } |
| 179 | return 0; | 196 | return 0; |
| 180 | } | 197 | } |
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c index fc819120978d..10245b837c10 100644 --- a/arch/arm/plat-omap/devices.c +++ b/arch/arm/plat-omap/devices.c | |||
| @@ -232,46 +232,6 @@ static void omap_init_uwire(void) | |||
| 232 | static inline void omap_init_uwire(void) {} | 232 | static inline void omap_init_uwire(void) {} |
| 233 | #endif | 233 | #endif |
| 234 | 234 | ||
| 235 | /*-------------------------------------------------------------------------*/ | ||
| 236 | |||
| 237 | #if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE) | ||
| 238 | |||
| 239 | static struct resource wdt_resources[] = { | ||
| 240 | { | ||
| 241 | .flags = IORESOURCE_MEM, | ||
| 242 | }, | ||
| 243 | }; | ||
| 244 | |||
| 245 | static struct platform_device omap_wdt_device = { | ||
| 246 | .name = "omap_wdt", | ||
| 247 | .id = -1, | ||
| 248 | .num_resources = ARRAY_SIZE(wdt_resources), | ||
| 249 | .resource = wdt_resources, | ||
| 250 | }; | ||
| 251 | |||
| 252 | static void omap_init_wdt(void) | ||
| 253 | { | ||
| 254 | if (cpu_is_omap16xx()) | ||
| 255 | wdt_resources[0].start = 0xfffeb000; | ||
| 256 | else if (cpu_is_omap2420()) | ||
| 257 | wdt_resources[0].start = 0x48022000; /* WDT2 */ | ||
| 258 | else if (cpu_is_omap2430()) | ||
| 259 | wdt_resources[0].start = 0x49016000; /* WDT2 */ | ||
| 260 | else if (cpu_is_omap343x()) | ||
| 261 | wdt_resources[0].start = 0x48314000; /* WDT2 */ | ||
| 262 | else if (cpu_is_omap44xx()) | ||
| 263 | wdt_resources[0].start = 0x4a314000; | ||
| 264 | else | ||
| 265 | return; | ||
| 266 | |||
| 267 | wdt_resources[0].end = wdt_resources[0].start + 0x4f; | ||
| 268 | |||
| 269 | (void) platform_device_register(&omap_wdt_device); | ||
| 270 | } | ||
| 271 | #else | ||
| 272 | static inline void omap_init_wdt(void) {} | ||
| 273 | #endif | ||
| 274 | |||
| 275 | #if defined(CONFIG_TIDSPBRIDGE) || defined(CONFIG_TIDSPBRIDGE_MODULE) | 235 | #if defined(CONFIG_TIDSPBRIDGE) || defined(CONFIG_TIDSPBRIDGE_MODULE) |
| 276 | 236 | ||
| 277 | static phys_addr_t omap_dsp_phys_mempool_base; | 237 | static phys_addr_t omap_dsp_phys_mempool_base; |
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 2c2826571d45..c4b2b478b1a5 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c | |||
| @@ -15,6 +15,10 @@ | |||
| 15 | * | 15 | * |
| 16 | * Support functions for the OMAP internal DMA channels. | 16 | * Support functions for the OMAP internal DMA channels. |
| 17 | * | 17 | * |
| 18 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 19 | * Converted DMA library into DMA platform driver. | ||
| 20 | * - G, Manjunath Kondaiah <manjugk@ti.com> | ||
| 21 | * | ||
| 18 | * This program is free software; you can redistribute it and/or modify | 22 | * This program is free software; you can redistribute it and/or modify |
| 19 | * it under the terms of the GNU General Public License version 2 as | 23 | * it under the terms of the GNU General Public License version 2 as |
| 20 | * published by the Free Software Foundation. | 24 | * published by the Free Software Foundation. |
| @@ -53,7 +57,11 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED }; | |||
| 53 | 57 | ||
| 54 | #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec) | 58 | #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec) |
| 55 | 59 | ||
| 60 | static struct omap_system_dma_plat_info *p; | ||
| 61 | static struct omap_dma_dev_attr *d; | ||
| 62 | |||
| 56 | static int enable_1510_mode; | 63 | static int enable_1510_mode; |
| 64 | static u32 errata; | ||
| 57 | 65 | ||
| 58 | static struct omap_dma_global_context_registers { | 66 | static struct omap_dma_global_context_registers { |
| 59 | u32 dma_irqenable_l0; | 67 | u32 dma_irqenable_l0; |
| @@ -61,27 +69,6 @@ static struct omap_dma_global_context_registers { | |||
| 61 | u32 dma_gcr; | 69 | u32 dma_gcr; |
| 62 | } omap_dma_global_context; | 70 | } omap_dma_global_context; |
| 63 | 71 | ||
| 64 | struct omap_dma_lch { | ||
| 65 | int next_lch; | ||
| 66 | int dev_id; | ||
| 67 | u16 saved_csr; | ||
| 68 | u16 enabled_irqs; | ||
| 69 | const char *dev_name; | ||
| 70 | void (*callback)(int lch, u16 ch_status, void *data); | ||
| 71 | void *data; | ||
| 72 | |||
| 73 | #ifndef CONFIG_ARCH_OMAP1 | ||
| 74 | /* required for Dynamic chaining */ | ||
| 75 | int prev_linked_ch; | ||
| 76 | int next_linked_ch; | ||
| 77 | int state; | ||
| 78 | int chain_id; | ||
| 79 | |||
| 80 | int status; | ||
| 81 | #endif | ||
| 82 | long flags; | ||
| 83 | }; | ||
| 84 | |||
| 85 | struct dma_link_info { | 72 | struct dma_link_info { |
| 86 | int *linked_dmach_q; | 73 | int *linked_dmach_q; |
| 87 | int no_of_lchs_linked; | 74 | int no_of_lchs_linked; |
| @@ -137,15 +124,6 @@ static int omap_dma_reserve_channels; | |||
| 137 | 124 | ||
| 138 | static spinlock_t dma_chan_lock; | 125 | static spinlock_t dma_chan_lock; |
| 139 | static struct omap_dma_lch *dma_chan; | 126 | static struct omap_dma_lch *dma_chan; |
| 140 | static void __iomem *omap_dma_base; | ||
| 141 | |||
| 142 | static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = { | ||
| 143 | INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3, | ||
| 144 | INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7, | ||
| 145 | INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10, | ||
| 146 | INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13, | ||
| 147 | INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD | ||
| 148 | }; | ||
| 149 | 127 | ||
| 150 | static inline void disable_lnk(int lch); | 128 | static inline void disable_lnk(int lch); |
| 151 | static void omap_disable_channel_irq(int lch); | 129 | static void omap_disable_channel_irq(int lch); |
| @@ -154,24 +132,6 @@ static inline void omap_enable_channel_irq(int lch); | |||
| 154 | #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \ | 132 | #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \ |
| 155 | __func__); | 133 | __func__); |
| 156 | 134 | ||
| 157 | #define dma_read(reg) \ | ||
| 158 | ({ \ | ||
| 159 | u32 __val; \ | ||
| 160 | if (cpu_class_is_omap1()) \ | ||
| 161 | __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg); \ | ||
| 162 | else \ | ||
| 163 | __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg); \ | ||
| 164 | __val; \ | ||
| 165 | }) | ||
| 166 | |||
| 167 | #define dma_write(val, reg) \ | ||
| 168 | ({ \ | ||
| 169 | if (cpu_class_is_omap1()) \ | ||
| 170 | __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \ | ||
| 171 | else \ | ||
| 172 | __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg); \ | ||
| 173 | }) | ||
| 174 | |||
| 175 | #ifdef CONFIG_ARCH_OMAP15XX | 135 | #ifdef CONFIG_ARCH_OMAP15XX |
| 176 | /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */ | 136 | /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */ |
| 177 | int omap_dma_in_1510_mode(void) | 137 | int omap_dma_in_1510_mode(void) |
| @@ -206,16 +166,6 @@ static inline void set_gdma_dev(int req, int dev) | |||
| 206 | #define set_gdma_dev(req, dev) do {} while (0) | 166 | #define set_gdma_dev(req, dev) do {} while (0) |
| 207 | #endif | 167 | #endif |
| 208 | 168 | ||
| 209 | /* Omap1 only */ | ||
| 210 | static void clear_lch_regs(int lch) | ||
| 211 | { | ||
| 212 | int i; | ||
| 213 | void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch); | ||
| 214 | |||
| 215 | for (i = 0; i < 0x2c; i += 2) | ||
| 216 | __raw_writew(0, lch_base + i); | ||
| 217 | } | ||
| 218 | |||
| 219 | void omap_set_dma_priority(int lch, int dst_port, int priority) | 169 | void omap_set_dma_priority(int lch, int dst_port, int priority) |
| 220 | { | 170 | { |
| 221 | unsigned long reg; | 171 | unsigned long reg; |
| @@ -248,12 +198,12 @@ void omap_set_dma_priority(int lch, int dst_port, int priority) | |||
| 248 | if (cpu_class_is_omap2()) { | 198 | if (cpu_class_is_omap2()) { |
| 249 | u32 ccr; | 199 | u32 ccr; |
| 250 | 200 | ||
| 251 | ccr = dma_read(CCR(lch)); | 201 | ccr = p->dma_read(CCR, lch); |
| 252 | if (priority) | 202 | if (priority) |
| 253 | ccr |= (1 << 6); | 203 | ccr |= (1 << 6); |
| 254 | else | 204 | else |
| 255 | ccr &= ~(1 << 6); | 205 | ccr &= ~(1 << 6); |
| 256 | dma_write(ccr, CCR(lch)); | 206 | p->dma_write(ccr, CCR, lch); |
| 257 | } | 207 | } |
| 258 | } | 208 | } |
| 259 | EXPORT_SYMBOL(omap_set_dma_priority); | 209 | EXPORT_SYMBOL(omap_set_dma_priority); |
| @@ -264,31 +214,31 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, | |||
| 264 | { | 214 | { |
| 265 | u32 l; | 215 | u32 l; |
| 266 | 216 | ||
| 267 | l = dma_read(CSDP(lch)); | 217 | l = p->dma_read(CSDP, lch); |
| 268 | l &= ~0x03; | 218 | l &= ~0x03; |
| 269 | l |= data_type; | 219 | l |= data_type; |
| 270 | dma_write(l, CSDP(lch)); | 220 | p->dma_write(l, CSDP, lch); |
| 271 | 221 | ||
| 272 | if (cpu_class_is_omap1()) { | 222 | if (cpu_class_is_omap1()) { |
| 273 | u16 ccr; | 223 | u16 ccr; |
| 274 | 224 | ||
| 275 | ccr = dma_read(CCR(lch)); | 225 | ccr = p->dma_read(CCR, lch); |
| 276 | ccr &= ~(1 << 5); | 226 | ccr &= ~(1 << 5); |
| 277 | if (sync_mode == OMAP_DMA_SYNC_FRAME) | 227 | if (sync_mode == OMAP_DMA_SYNC_FRAME) |
| 278 | ccr |= 1 << 5; | 228 | ccr |= 1 << 5; |
| 279 | dma_write(ccr, CCR(lch)); | 229 | p->dma_write(ccr, CCR, lch); |
| 280 | 230 | ||
| 281 | ccr = dma_read(CCR2(lch)); | 231 | ccr = p->dma_read(CCR2, lch); |
| 282 | ccr &= ~(1 << 2); | 232 | ccr &= ~(1 << 2); |
| 283 | if (sync_mode == OMAP_DMA_SYNC_BLOCK) | 233 | if (sync_mode == OMAP_DMA_SYNC_BLOCK) |
| 284 | ccr |= 1 << 2; | 234 | ccr |= 1 << 2; |
| 285 | dma_write(ccr, CCR2(lch)); | 235 | p->dma_write(ccr, CCR2, lch); |
| 286 | } | 236 | } |
| 287 | 237 | ||
| 288 | if (cpu_class_is_omap2() && dma_trigger) { | 238 | if (cpu_class_is_omap2() && dma_trigger) { |
| 289 | u32 val; | 239 | u32 val; |
| 290 | 240 | ||
| 291 | val = dma_read(CCR(lch)); | 241 | val = p->dma_read(CCR, lch); |
| 292 | 242 | ||
| 293 | /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */ | 243 | /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */ |
| 294 | val &= ~((1 << 23) | (3 << 19) | 0x1f); | 244 | val &= ~((1 << 23) | (3 << 19) | 0x1f); |
| @@ -313,11 +263,11 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, | |||
| 313 | } else { | 263 | } else { |
| 314 | val &= ~(1 << 24); /* dest synch */ | 264 | val &= ~(1 << 24); /* dest synch */ |
| 315 | } | 265 | } |
| 316 | dma_write(val, CCR(lch)); | 266 | p->dma_write(val, CCR, lch); |
| 317 | } | 267 | } |
| 318 | 268 | ||
| 319 | dma_write(elem_count, CEN(lch)); | 269 | p->dma_write(elem_count, CEN, lch); |
| 320 | dma_write(frame_count, CFN(lch)); | 270 | p->dma_write(frame_count, CFN, lch); |
| 321 | } | 271 | } |
| 322 | EXPORT_SYMBOL(omap_set_dma_transfer_params); | 272 | EXPORT_SYMBOL(omap_set_dma_transfer_params); |
| 323 | 273 | ||
| @@ -328,7 +278,7 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color) | |||
| 328 | if (cpu_class_is_omap1()) { | 278 | if (cpu_class_is_omap1()) { |
| 329 | u16 w; | 279 | u16 w; |
| 330 | 280 | ||
| 331 | w = dma_read(CCR2(lch)); | 281 | w = p->dma_read(CCR2, lch); |
| 332 | w &= ~0x03; | 282 | w &= ~0x03; |
| 333 | 283 | ||
| 334 | switch (mode) { | 284 | switch (mode) { |
| @@ -343,23 +293,22 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color) | |||
| 343 | default: | 293 | default: |
| 344 | BUG(); | 294 | BUG(); |
| 345 | } | 295 | } |
| 346 | dma_write(w, CCR2(lch)); | 296 | p->dma_write(w, CCR2, lch); |
| 347 | 297 | ||
| 348 | w = dma_read(LCH_CTRL(lch)); | 298 | w = p->dma_read(LCH_CTRL, lch); |
| 349 | w &= ~0x0f; | 299 | w &= ~0x0f; |
| 350 | /* Default is channel type 2D */ | 300 | /* Default is channel type 2D */ |
| 351 | if (mode) { | 301 | if (mode) { |
| 352 | dma_write((u16)color, COLOR_L(lch)); | 302 | p->dma_write(color, COLOR, lch); |
| 353 | dma_write((u16)(color >> 16), COLOR_U(lch)); | ||
| 354 | w |= 1; /* Channel type G */ | 303 | w |= 1; /* Channel type G */ |
| 355 | } | 304 | } |
| 356 | dma_write(w, LCH_CTRL(lch)); | 305 | p->dma_write(w, LCH_CTRL, lch); |
| 357 | } | 306 | } |
| 358 | 307 | ||
| 359 | if (cpu_class_is_omap2()) { | 308 | if (cpu_class_is_omap2()) { |
| 360 | u32 val; | 309 | u32 val; |
| 361 | 310 | ||
| 362 | val = dma_read(CCR(lch)); | 311 | val = p->dma_read(CCR, lch); |
| 363 | val &= ~((1 << 17) | (1 << 16)); | 312 | val &= ~((1 << 17) | (1 << 16)); |
| 364 | 313 | ||
| 365 | switch (mode) { | 314 | switch (mode) { |
| @@ -374,10 +323,10 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color) | |||
| 374 | default: | 323 | default: |
| 375 | BUG(); | 324 | BUG(); |
| 376 | } | 325 | } |
| 377 | dma_write(val, CCR(lch)); | 326 | p->dma_write(val, CCR, lch); |
| 378 | 327 | ||
| 379 | color &= 0xffffff; | 328 | color &= 0xffffff; |
| 380 | dma_write(color, COLOR(lch)); | 329 | p->dma_write(color, COLOR, lch); |
| 381 | } | 330 | } |
| 382 | } | 331 | } |
| 383 | EXPORT_SYMBOL(omap_set_dma_color_mode); | 332 | EXPORT_SYMBOL(omap_set_dma_color_mode); |
| @@ -387,10 +336,10 @@ void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode) | |||
| 387 | if (cpu_class_is_omap2()) { | 336 | if (cpu_class_is_omap2()) { |
| 388 | u32 csdp; | 337 | u32 csdp; |
| 389 | 338 | ||
| 390 | csdp = dma_read(CSDP(lch)); | 339 | csdp = p->dma_read(CSDP, lch); |
| 391 | csdp &= ~(0x3 << 16); | 340 | csdp &= ~(0x3 << 16); |
| 392 | csdp |= (mode << 16); | 341 | csdp |= (mode << 16); |
| 393 | dma_write(csdp, CSDP(lch)); | 342 | p->dma_write(csdp, CSDP, lch); |
| 394 | } | 343 | } |
| 395 | } | 344 | } |
| 396 | EXPORT_SYMBOL(omap_set_dma_write_mode); | 345 | EXPORT_SYMBOL(omap_set_dma_write_mode); |
| @@ -400,10 +349,10 @@ void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode) | |||
| 400 | if (cpu_class_is_omap1() && !cpu_is_omap15xx()) { | 349 | if (cpu_class_is_omap1() && !cpu_is_omap15xx()) { |
| 401 | u32 l; | 350 | u32 l; |
| 402 | 351 | ||
| 403 | l = dma_read(LCH_CTRL(lch)); | 352 | l = p->dma_read(LCH_CTRL, lch); |
| 404 | l &= ~0x7; | 353 | l &= ~0x7; |
| 405 | l |= mode; | 354 | l |= mode; |
| 406 | dma_write(l, LCH_CTRL(lch)); | 355 | p->dma_write(l, LCH_CTRL, lch); |
| 407 | } | 356 | } |
| 408 | } | 357 | } |
| 409 | EXPORT_SYMBOL(omap_set_dma_channel_mode); | 358 | EXPORT_SYMBOL(omap_set_dma_channel_mode); |
| @@ -418,27 +367,21 @@ void omap_set_dma_src_params(int lch, int src_port, int src_amode, | |||
| 418 | if (cpu_class_is_omap1()) { | 367 | if (cpu_class_is_omap1()) { |
| 419 | u16 w; | 368 | u16 w; |
| 420 | 369 | ||
| 421 | w = dma_read(CSDP(lch)); | 370 | w = p->dma_read(CSDP, lch); |
| 422 | w &= ~(0x1f << 2); | 371 | w &= ~(0x1f << 2); |
| 423 | w |= src_port << 2; | 372 | w |= src_port << 2; |
| 424 | dma_write(w, CSDP(lch)); | 373 | p->dma_write(w, CSDP, lch); |
| 425 | } | 374 | } |
| 426 | 375 | ||
| 427 | l = dma_read(CCR(lch)); | 376 | l = p->dma_read(CCR, lch); |
| 428 | l &= ~(0x03 << 12); | 377 | l &= ~(0x03 << 12); |
| 429 | l |= src_amode << 12; | 378 | l |= src_amode << 12; |
| 430 | dma_write(l, CCR(lch)); | 379 | p->dma_write(l, CCR, lch); |
| 431 | |||
| 432 | if (cpu_class_is_omap1()) { | ||
| 433 | dma_write(src_start >> 16, CSSA_U(lch)); | ||
| 434 | dma_write((u16)src_start, CSSA_L(lch)); | ||
| 435 | } | ||
| 436 | 380 | ||
| 437 | if (cpu_class_is_omap2()) | 381 | p->dma_write(src_start, CSSA, lch); |
| 438 | dma_write(src_start, CSSA(lch)); | ||
| 439 | 382 | ||
| 440 | dma_write(src_ei, CSEI(lch)); | 383 | p->dma_write(src_ei, CSEI, lch); |
| 441 | dma_write(src_fi, CSFI(lch)); | 384 | p->dma_write(src_fi, CSFI, lch); |
| 442 | } | 385 | } |
| 443 | EXPORT_SYMBOL(omap_set_dma_src_params); | 386 | EXPORT_SYMBOL(omap_set_dma_src_params); |
| 444 | 387 | ||
| @@ -466,8 +409,8 @@ void omap_set_dma_src_index(int lch, int eidx, int fidx) | |||
| 466 | if (cpu_class_is_omap2()) | 409 | if (cpu_class_is_omap2()) |
| 467 | return; | 410 | return; |
| 468 | 411 | ||
| 469 | dma_write(eidx, CSEI(lch)); | 412 | p->dma_write(eidx, CSEI, lch); |
| 470 | dma_write(fidx, CSFI(lch)); | 413 | p->dma_write(fidx, CSFI, lch); |
| 471 | } | 414 | } |
| 472 | EXPORT_SYMBOL(omap_set_dma_src_index); | 415 | EXPORT_SYMBOL(omap_set_dma_src_index); |
| 473 | 416 | ||
| @@ -475,11 +418,11 @@ void omap_set_dma_src_data_pack(int lch, int enable) | |||
| 475 | { | 418 | { |
| 476 | u32 l; | 419 | u32 l; |
| 477 | 420 | ||
| 478 | l = dma_read(CSDP(lch)); | 421 | l = p->dma_read(CSDP, lch); |
| 479 | l &= ~(1 << 6); | 422 | l &= ~(1 << 6); |
| 480 | if (enable) | 423 | if (enable) |
| 481 | l |= (1 << 6); | 424 | l |= (1 << 6); |
| 482 | dma_write(l, CSDP(lch)); | 425 | p->dma_write(l, CSDP, lch); |
| 483 | } | 426 | } |
| 484 | EXPORT_SYMBOL(omap_set_dma_src_data_pack); | 427 | EXPORT_SYMBOL(omap_set_dma_src_data_pack); |
| 485 | 428 | ||
| @@ -488,7 +431,7 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) | |||
| 488 | unsigned int burst = 0; | 431 | unsigned int burst = 0; |
| 489 | u32 l; | 432 | u32 l; |
| 490 | 433 | ||
| 491 | l = dma_read(CSDP(lch)); | 434 | l = p->dma_read(CSDP, lch); |
| 492 | l &= ~(0x03 << 7); | 435 | l &= ~(0x03 << 7); |
| 493 | 436 | ||
| 494 | switch (burst_mode) { | 437 | switch (burst_mode) { |
| @@ -524,7 +467,7 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) | |||
| 524 | } | 467 | } |
| 525 | 468 | ||
| 526 | l |= (burst << 7); | 469 | l |= (burst << 7); |
| 527 | dma_write(l, CSDP(lch)); | 470 | p->dma_write(l, CSDP, lch); |
| 528 | } | 471 | } |
| 529 | EXPORT_SYMBOL(omap_set_dma_src_burst_mode); | 472 | EXPORT_SYMBOL(omap_set_dma_src_burst_mode); |
| 530 | 473 | ||
| @@ -536,27 +479,21 @@ void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, | |||
| 536 | u32 l; | 479 | u32 l; |
| 537 | 480 | ||
| 538 | if (cpu_class_is_omap1()) { | 481 | if (cpu_class_is_omap1()) { |
| 539 | l = dma_read(CSDP(lch)); | 482 | l = p->dma_read(CSDP, lch); |
| 540 | l &= ~(0x1f << 9); | 483 | l &= ~(0x1f << 9); |
| 541 | l |= dest_port << 9; | 484 | l |= dest_port << 9; |
| 542 | dma_write(l, CSDP(lch)); | 485 | p->dma_write(l, CSDP, lch); |
| 543 | } | 486 | } |
| 544 | 487 | ||
| 545 | l = dma_read(CCR(lch)); | 488 | l = p->dma_read(CCR, lch); |
| 546 | l &= ~(0x03 << 14); | 489 | l &= ~(0x03 << 14); |
| 547 | l |= dest_amode << 14; | 490 | l |= dest_amode << 14; |
| 548 | dma_write(l, CCR(lch)); | 491 | p->dma_write(l, CCR, lch); |
| 549 | |||
| 550 | if (cpu_class_is_omap1()) { | ||
| 551 | dma_write(dest_start >> 16, CDSA_U(lch)); | ||
| 552 | dma_write(dest_start, CDSA_L(lch)); | ||
| 553 | } | ||
| 554 | 492 | ||
| 555 | if (cpu_class_is_omap2()) | 493 | p->dma_write(dest_start, CDSA, lch); |
| 556 | dma_write(dest_start, CDSA(lch)); | ||
| 557 | 494 | ||
| 558 | dma_write(dst_ei, CDEI(lch)); | 495 | p->dma_write(dst_ei, CDEI, lch); |
| 559 | dma_write(dst_fi, CDFI(lch)); | 496 | p->dma_write(dst_fi, CDFI, lch); |
| 560 | } | 497 | } |
| 561 | EXPORT_SYMBOL(omap_set_dma_dest_params); | 498 | EXPORT_SYMBOL(omap_set_dma_dest_params); |
| 562 | 499 | ||
| @@ -565,8 +502,8 @@ void omap_set_dma_dest_index(int lch, int eidx, int fidx) | |||
| 565 | if (cpu_class_is_omap2()) | 502 | if (cpu_class_is_omap2()) |
| 566 | return; | 503 | return; |
| 567 | 504 | ||
| 568 | dma_write(eidx, CDEI(lch)); | 505 | p->dma_write(eidx, CDEI, lch); |
| 569 | dma_write(fidx, CDFI(lch)); | 506 | p->dma_write(fidx, CDFI, lch); |
| 570 | } | 507 | } |
| 571 | EXPORT_SYMBOL(omap_set_dma_dest_index); | 508 | EXPORT_SYMBOL(omap_set_dma_dest_index); |
| 572 | 509 | ||
| @@ -574,11 +511,11 @@ void omap_set_dma_dest_data_pack(int lch, int enable) | |||
| 574 | { | 511 | { |
| 575 | u32 l; | 512 | u32 l; |
| 576 | 513 | ||
| 577 | l = dma_read(CSDP(lch)); | 514 | l = p->dma_read(CSDP, lch); |
| 578 | l &= ~(1 << 13); | 515 | l &= ~(1 << 13); |
| 579 | if (enable) | 516 | if (enable) |
| 580 | l |= 1 << 13; | 517 | l |= 1 << 13; |
| 581 | dma_write(l, CSDP(lch)); | 518 | p->dma_write(l, CSDP, lch); |
| 582 | } | 519 | } |
| 583 | EXPORT_SYMBOL(omap_set_dma_dest_data_pack); | 520 | EXPORT_SYMBOL(omap_set_dma_dest_data_pack); |
| 584 | 521 | ||
| @@ -587,7 +524,7 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) | |||
| 587 | unsigned int burst = 0; | 524 | unsigned int burst = 0; |
| 588 | u32 l; | 525 | u32 l; |
| 589 | 526 | ||
| 590 | l = dma_read(CSDP(lch)); | 527 | l = p->dma_read(CSDP, lch); |
| 591 | l &= ~(0x03 << 14); | 528 | l &= ~(0x03 << 14); |
| 592 | 529 | ||
| 593 | switch (burst_mode) { | 530 | switch (burst_mode) { |
| @@ -620,7 +557,7 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) | |||
| 620 | return; | 557 | return; |
| 621 | } | 558 | } |
| 622 | l |= (burst << 14); | 559 | l |= (burst << 14); |
| 623 | dma_write(l, CSDP(lch)); | 560 | p->dma_write(l, CSDP, lch); |
| 624 | } | 561 | } |
| 625 | EXPORT_SYMBOL(omap_set_dma_dest_burst_mode); | 562 | EXPORT_SYMBOL(omap_set_dma_dest_burst_mode); |
| 626 | 563 | ||
| @@ -630,18 +567,18 @@ static inline void omap_enable_channel_irq(int lch) | |||
| 630 | 567 | ||
| 631 | /* Clear CSR */ | 568 | /* Clear CSR */ |
| 632 | if (cpu_class_is_omap1()) | 569 | if (cpu_class_is_omap1()) |
| 633 | status = dma_read(CSR(lch)); | 570 | status = p->dma_read(CSR, lch); |
| 634 | else if (cpu_class_is_omap2()) | 571 | else if (cpu_class_is_omap2()) |
| 635 | dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch)); | 572 | p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); |
| 636 | 573 | ||
| 637 | /* Enable some nice interrupts. */ | 574 | /* Enable some nice interrupts. */ |
| 638 | dma_write(dma_chan[lch].enabled_irqs, CICR(lch)); | 575 | p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch); |
| 639 | } | 576 | } |
| 640 | 577 | ||
| 641 | static void omap_disable_channel_irq(int lch) | 578 | static void omap_disable_channel_irq(int lch) |
| 642 | { | 579 | { |
| 643 | if (cpu_class_is_omap2()) | 580 | if (cpu_class_is_omap2()) |
| 644 | dma_write(0, CICR(lch)); | 581 | p->dma_write(0, CICR, lch); |
| 645 | } | 582 | } |
| 646 | 583 | ||
| 647 | void omap_enable_dma_irq(int lch, u16 bits) | 584 | void omap_enable_dma_irq(int lch, u16 bits) |
| @@ -660,7 +597,7 @@ static inline void enable_lnk(int lch) | |||
| 660 | { | 597 | { |
| 661 | u32 l; | 598 | u32 l; |
| 662 | 599 | ||
| 663 | l = dma_read(CLNK_CTRL(lch)); | 600 | l = p->dma_read(CLNK_CTRL, lch); |
| 664 | 601 | ||
| 665 | if (cpu_class_is_omap1()) | 602 | if (cpu_class_is_omap1()) |
| 666 | l &= ~(1 << 14); | 603 | l &= ~(1 << 14); |
| @@ -675,18 +612,18 @@ static inline void enable_lnk(int lch) | |||
| 675 | l = dma_chan[lch].next_linked_ch | (1 << 15); | 612 | l = dma_chan[lch].next_linked_ch | (1 << 15); |
| 676 | #endif | 613 | #endif |
| 677 | 614 | ||
| 678 | dma_write(l, CLNK_CTRL(lch)); | 615 | p->dma_write(l, CLNK_CTRL, lch); |
| 679 | } | 616 | } |
| 680 | 617 | ||
| 681 | static inline void disable_lnk(int lch) | 618 | static inline void disable_lnk(int lch) |
| 682 | { | 619 | { |
| 683 | u32 l; | 620 | u32 l; |
| 684 | 621 | ||
| 685 | l = dma_read(CLNK_CTRL(lch)); | 622 | l = p->dma_read(CLNK_CTRL, lch); |
| 686 | 623 | ||
| 687 | /* Disable interrupts */ | 624 | /* Disable interrupts */ |
| 688 | if (cpu_class_is_omap1()) { | 625 | if (cpu_class_is_omap1()) { |
| 689 | dma_write(0, CICR(lch)); | 626 | p->dma_write(0, CICR, lch); |
| 690 | /* Set the STOP_LNK bit */ | 627 | /* Set the STOP_LNK bit */ |
| 691 | l |= 1 << 14; | 628 | l |= 1 << 14; |
| 692 | } | 629 | } |
| @@ -697,7 +634,7 @@ static inline void disable_lnk(int lch) | |||
| 697 | l &= ~(1 << 15); | 634 | l &= ~(1 << 15); |
| 698 | } | 635 | } |
| 699 | 636 | ||
| 700 | dma_write(l, CLNK_CTRL(lch)); | 637 | p->dma_write(l, CLNK_CTRL, lch); |
| 701 | dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; | 638 | dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; |
| 702 | } | 639 | } |
| 703 | 640 | ||
| @@ -710,9 +647,9 @@ static inline void omap2_enable_irq_lch(int lch) | |||
| 710 | return; | 647 | return; |
| 711 | 648 | ||
| 712 | spin_lock_irqsave(&dma_chan_lock, flags); | 649 | spin_lock_irqsave(&dma_chan_lock, flags); |
| 713 | val = dma_read(IRQENABLE_L0); | 650 | val = p->dma_read(IRQENABLE_L0, lch); |
| 714 | val |= 1 << lch; | 651 | val |= 1 << lch; |
| 715 | dma_write(val, IRQENABLE_L0); | 652 | p->dma_write(val, IRQENABLE_L0, lch); |
| 716 | spin_unlock_irqrestore(&dma_chan_lock, flags); | 653 | spin_unlock_irqrestore(&dma_chan_lock, flags); |
| 717 | } | 654 | } |
| 718 | 655 | ||
| @@ -725,9 +662,9 @@ static inline void omap2_disable_irq_lch(int lch) | |||
| 725 | return; | 662 | return; |
| 726 | 663 | ||
| 727 | spin_lock_irqsave(&dma_chan_lock, flags); | 664 | spin_lock_irqsave(&dma_chan_lock, flags); |
| 728 | val = dma_read(IRQENABLE_L0); | 665 | val = p->dma_read(IRQENABLE_L0, lch); |
| 729 | val &= ~(1 << lch); | 666 | val &= ~(1 << lch); |
| 730 | dma_write(val, IRQENABLE_L0); | 667 | p->dma_write(val, IRQENABLE_L0, lch); |
| 731 | spin_unlock_irqrestore(&dma_chan_lock, flags); | 668 | spin_unlock_irqrestore(&dma_chan_lock, flags); |
| 732 | } | 669 | } |
| 733 | 670 | ||
| @@ -754,8 +691,8 @@ int omap_request_dma(int dev_id, const char *dev_name, | |||
| 754 | chan = dma_chan + free_ch; | 691 | chan = dma_chan + free_ch; |
| 755 | chan->dev_id = dev_id; | 692 | chan->dev_id = dev_id; |
| 756 | 693 | ||
| 757 | if (cpu_class_is_omap1()) | 694 | if (p->clear_lch_regs) |
| 758 | clear_lch_regs(free_ch); | 695 | p->clear_lch_regs(free_ch); |
| 759 | 696 | ||
| 760 | if (cpu_class_is_omap2()) | 697 | if (cpu_class_is_omap2()) |
| 761 | omap_clear_dma(free_ch); | 698 | omap_clear_dma(free_ch); |
| @@ -792,17 +729,17 @@ int omap_request_dma(int dev_id, const char *dev_name, | |||
| 792 | * Disable the 1510 compatibility mode and set the sync device | 729 | * Disable the 1510 compatibility mode and set the sync device |
| 793 | * id. | 730 | * id. |
| 794 | */ | 731 | */ |
| 795 | dma_write(dev_id | (1 << 10), CCR(free_ch)); | 732 | p->dma_write(dev_id | (1 << 10), CCR, free_ch); |
| 796 | } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) { | 733 | } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) { |
| 797 | dma_write(dev_id, CCR(free_ch)); | 734 | p->dma_write(dev_id, CCR, free_ch); |
| 798 | } | 735 | } |
| 799 | 736 | ||
| 800 | if (cpu_class_is_omap2()) { | 737 | if (cpu_class_is_omap2()) { |
| 801 | omap2_enable_irq_lch(free_ch); | 738 | omap2_enable_irq_lch(free_ch); |
| 802 | omap_enable_channel_irq(free_ch); | 739 | omap_enable_channel_irq(free_ch); |
| 803 | /* Clear the CSR register and IRQ status register */ | 740 | /* Clear the CSR register and IRQ status register */ |
| 804 | dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch)); | 741 | p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, free_ch); |
| 805 | dma_write(1 << free_ch, IRQSTATUS_L0); | 742 | p->dma_write(1 << free_ch, IRQSTATUS_L0, 0); |
| 806 | } | 743 | } |
| 807 | 744 | ||
| 808 | *dma_ch_out = free_ch; | 745 | *dma_ch_out = free_ch; |
| @@ -823,23 +760,23 @@ void omap_free_dma(int lch) | |||
| 823 | 760 | ||
| 824 | if (cpu_class_is_omap1()) { | 761 | if (cpu_class_is_omap1()) { |
| 825 | /* Disable all DMA interrupts for the channel. */ | 762 | /* Disable all DMA interrupts for the channel. */ |
| 826 | dma_write(0, CICR(lch)); | 763 | p->dma_write(0, CICR, lch); |
| 827 | /* Make sure the DMA transfer is stopped. */ | 764 | /* Make sure the DMA transfer is stopped. */ |
| 828 | dma_write(0, CCR(lch)); | 765 | p->dma_write(0, CCR, lch); |
| 829 | } | 766 | } |
| 830 | 767 | ||
| 831 | if (cpu_class_is_omap2()) { | 768 | if (cpu_class_is_omap2()) { |
| 832 | omap2_disable_irq_lch(lch); | 769 | omap2_disable_irq_lch(lch); |
| 833 | 770 | ||
| 834 | /* Clear the CSR register and IRQ status register */ | 771 | /* Clear the CSR register and IRQ status register */ |
| 835 | dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch)); | 772 | p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); |
| 836 | dma_write(1 << lch, IRQSTATUS_L0); | 773 | p->dma_write(1 << lch, IRQSTATUS_L0, lch); |
| 837 | 774 | ||
| 838 | /* Disable all DMA interrupts for the channel. */ | 775 | /* Disable all DMA interrupts for the channel. */ |
| 839 | dma_write(0, CICR(lch)); | 776 | p->dma_write(0, CICR, lch); |
| 840 | 777 | ||
| 841 | /* Make sure the DMA transfer is stopped. */ | 778 | /* Make sure the DMA transfer is stopped. */ |
| 842 | dma_write(0, CCR(lch)); | 779 | p->dma_write(0, CCR, lch); |
| 843 | omap_clear_dma(lch); | 780 | omap_clear_dma(lch); |
| 844 | } | 781 | } |
| 845 | 782 | ||
| @@ -880,7 +817,7 @@ omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams) | |||
| 880 | reg |= (0x3 & tparams) << 12; | 817 | reg |= (0x3 & tparams) << 12; |
| 881 | reg |= (arb_rate & 0xff) << 16; | 818 | reg |= (arb_rate & 0xff) << 16; |
| 882 | 819 | ||
| 883 | dma_write(reg, GCR); | 820 | p->dma_write(reg, GCR, 0); |
| 884 | } | 821 | } |
| 885 | EXPORT_SYMBOL(omap_dma_set_global_params); | 822 | EXPORT_SYMBOL(omap_dma_set_global_params); |
| 886 | 823 | ||
| @@ -903,14 +840,14 @@ omap_dma_set_prio_lch(int lch, unsigned char read_prio, | |||
| 903 | printk(KERN_ERR "Invalid channel id\n"); | 840 | printk(KERN_ERR "Invalid channel id\n"); |
| 904 | return -EINVAL; | 841 | return -EINVAL; |
| 905 | } | 842 | } |
| 906 | l = dma_read(CCR(lch)); | 843 | l = p->dma_read(CCR, lch); |
| 907 | l &= ~((1 << 6) | (1 << 26)); | 844 | l &= ~((1 << 6) | (1 << 26)); |
| 908 | if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) | 845 | if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) |
| 909 | l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26); | 846 | l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26); |
| 910 | else | 847 | else |
| 911 | l |= ((read_prio & 0x1) << 6); | 848 | l |= ((read_prio & 0x1) << 6); |
| 912 | 849 | ||
| 913 | dma_write(l, CCR(lch)); | 850 | p->dma_write(l, CCR, lch); |
| 914 | 851 | ||
| 915 | return 0; | 852 | return 0; |
| 916 | } | 853 | } |
| @@ -925,25 +862,7 @@ void omap_clear_dma(int lch) | |||
| 925 | unsigned long flags; | 862 | unsigned long flags; |
| 926 | 863 | ||
| 927 | local_irq_save(flags); | 864 | local_irq_save(flags); |
| 928 | 865 | p->clear_dma(lch); | |
| 929 | if (cpu_class_is_omap1()) { | ||
| 930 | u32 l; | ||
| 931 | |||
| 932 | l = dma_read(CCR(lch)); | ||
| 933 | l &= ~OMAP_DMA_CCR_EN; | ||
| 934 | dma_write(l, CCR(lch)); | ||
| 935 | |||
| 936 | /* Clear pending interrupts */ | ||
| 937 | l = dma_read(CSR(lch)); | ||
| 938 | } | ||
| 939 | |||
| 940 | if (cpu_class_is_omap2()) { | ||
| 941 | int i; | ||
| 942 | void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch); | ||
| 943 | for (i = 0; i < 0x44; i += 4) | ||
| 944 | __raw_writel(0, lch_base + i); | ||
| 945 | } | ||
| 946 | |||
| 947 | local_irq_restore(flags); | 866 | local_irq_restore(flags); |
| 948 | } | 867 | } |
| 949 | EXPORT_SYMBOL(omap_clear_dma); | 868 | EXPORT_SYMBOL(omap_clear_dma); |
| @@ -957,13 +876,13 @@ void omap_start_dma(int lch) | |||
| 957 | * before starting dma transfer. | 876 | * before starting dma transfer. |
| 958 | */ | 877 | */ |
| 959 | if (cpu_is_omap15xx()) | 878 | if (cpu_is_omap15xx()) |
| 960 | dma_write(0, CPC(lch)); | 879 | p->dma_write(0, CPC, lch); |
| 961 | else | 880 | else |
| 962 | dma_write(0, CDAC(lch)); | 881 | p->dma_write(0, CDAC, lch); |
| 963 | 882 | ||
| 964 | if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { | 883 | if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { |
| 965 | int next_lch, cur_lch; | 884 | int next_lch, cur_lch; |
| 966 | char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT]; | 885 | char dma_chan_link_map[dma_lch_count]; |
| 967 | 886 | ||
| 968 | dma_chan_link_map[lch] = 1; | 887 | dma_chan_link_map[lch] = 1; |
| 969 | /* Set the link register of the first channel */ | 888 | /* Set the link register of the first channel */ |
| @@ -985,32 +904,18 @@ void omap_start_dma(int lch) | |||
| 985 | 904 | ||
| 986 | cur_lch = next_lch; | 905 | cur_lch = next_lch; |
| 987 | } while (next_lch != -1); | 906 | } while (next_lch != -1); |
| 988 | } else if (cpu_is_omap242x() || | 907 | } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS)) |
| 989 | (cpu_is_omap243x() && omap_type() <= OMAP2430_REV_ES1_0)) { | 908 | p->dma_write(lch, CLNK_CTRL, lch); |
| 990 | |||
| 991 | /* Errata: Need to write lch even if not using chaining */ | ||
| 992 | dma_write(lch, CLNK_CTRL(lch)); | ||
| 993 | } | ||
| 994 | 909 | ||
| 995 | omap_enable_channel_irq(lch); | 910 | omap_enable_channel_irq(lch); |
| 996 | 911 | ||
| 997 | l = dma_read(CCR(lch)); | 912 | l = p->dma_read(CCR, lch); |
| 998 | |||
| 999 | /* | ||
| 1000 | * Errata: Inter Frame DMA buffering issue (All OMAP2420 and | ||
| 1001 | * OMAP2430ES1.0): DMA will wrongly buffer elements if packing and | ||
| 1002 | * bursting is enabled. This might result in data gets stalled in | ||
| 1003 | * FIFO at the end of the block. | ||
| 1004 | * Workaround: DMA channels must have BUFFERING_DISABLED bit set to | ||
| 1005 | * guarantee no data will stay in the DMA FIFO in case inter frame | ||
| 1006 | * buffering occurs. | ||
| 1007 | */ | ||
| 1008 | if (cpu_is_omap2420() || | ||
| 1009 | (cpu_is_omap2430() && (omap_type() == OMAP2430_REV_ES1_0))) | ||
| 1010 | l |= OMAP_DMA_CCR_BUFFERING_DISABLE; | ||
| 1011 | 913 | ||
| 914 | if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING)) | ||
| 915 | l |= OMAP_DMA_CCR_BUFFERING_DISABLE; | ||
| 1012 | l |= OMAP_DMA_CCR_EN; | 916 | l |= OMAP_DMA_CCR_EN; |
| 1013 | dma_write(l, CCR(lch)); | 917 | |
| 918 | p->dma_write(l, CCR, lch); | ||
| 1014 | 919 | ||
| 1015 | dma_chan[lch].flags |= OMAP_DMA_ACTIVE; | 920 | dma_chan[lch].flags |= OMAP_DMA_ACTIVE; |
| 1016 | } | 921 | } |
| @@ -1022,46 +927,46 @@ void omap_stop_dma(int lch) | |||
| 1022 | 927 | ||
| 1023 | /* Disable all interrupts on the channel */ | 928 | /* Disable all interrupts on the channel */ |
| 1024 | if (cpu_class_is_omap1()) | 929 | if (cpu_class_is_omap1()) |
| 1025 | dma_write(0, CICR(lch)); | 930 | p->dma_write(0, CICR, lch); |
| 1026 | 931 | ||
| 1027 | l = dma_read(CCR(lch)); | 932 | l = p->dma_read(CCR, lch); |
| 1028 | /* OMAP3 Errata i541: sDMA FIFO draining does not finish */ | 933 | if (IS_DMA_ERRATA(DMA_ERRATA_i541) && |
| 1029 | if (cpu_is_omap34xx() && (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) { | 934 | (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) { |
| 1030 | int i = 0; | 935 | int i = 0; |
| 1031 | u32 sys_cf; | 936 | u32 sys_cf; |
| 1032 | 937 | ||
| 1033 | /* Configure No-Standby */ | 938 | /* Configure No-Standby */ |
| 1034 | l = dma_read(OCP_SYSCONFIG); | 939 | l = p->dma_read(OCP_SYSCONFIG, lch); |
| 1035 | sys_cf = l; | 940 | sys_cf = l; |
| 1036 | l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK; | 941 | l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK; |
| 1037 | l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE); | 942 | l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE); |
| 1038 | dma_write(l , OCP_SYSCONFIG); | 943 | p->dma_write(l , OCP_SYSCONFIG, 0); |
| 1039 | 944 | ||
| 1040 | l = dma_read(CCR(lch)); | 945 | l = p->dma_read(CCR, lch); |
| 1041 | l &= ~OMAP_DMA_CCR_EN; | 946 | l &= ~OMAP_DMA_CCR_EN; |
| 1042 | dma_write(l, CCR(lch)); | 947 | p->dma_write(l, CCR, lch); |
| 1043 | 948 | ||
| 1044 | /* Wait for sDMA FIFO drain */ | 949 | /* Wait for sDMA FIFO drain */ |
| 1045 | l = dma_read(CCR(lch)); | 950 | l = p->dma_read(CCR, lch); |
| 1046 | while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE | | 951 | while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE | |
| 1047 | OMAP_DMA_CCR_WR_ACTIVE))) { | 952 | OMAP_DMA_CCR_WR_ACTIVE))) { |
| 1048 | udelay(5); | 953 | udelay(5); |
| 1049 | i++; | 954 | i++; |
| 1050 | l = dma_read(CCR(lch)); | 955 | l = p->dma_read(CCR, lch); |
| 1051 | } | 956 | } |
| 1052 | if (i >= 100) | 957 | if (i >= 100) |
| 1053 | printk(KERN_ERR "DMA drain did not complete on " | 958 | printk(KERN_ERR "DMA drain did not complete on " |
| 1054 | "lch %d\n", lch); | 959 | "lch %d\n", lch); |
| 1055 | /* Restore OCP_SYSCONFIG */ | 960 | /* Restore OCP_SYSCONFIG */ |
| 1056 | dma_write(sys_cf, OCP_SYSCONFIG); | 961 | p->dma_write(sys_cf, OCP_SYSCONFIG, lch); |
| 1057 | } else { | 962 | } else { |
| 1058 | l &= ~OMAP_DMA_CCR_EN; | 963 | l &= ~OMAP_DMA_CCR_EN; |
| 1059 | dma_write(l, CCR(lch)); | 964 | p->dma_write(l, CCR, lch); |
| 1060 | } | 965 | } |
| 1061 | 966 | ||
| 1062 | if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { | 967 | if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { |
| 1063 | int next_lch, cur_lch = lch; | 968 | int next_lch, cur_lch = lch; |
| 1064 | char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT]; | 969 | char dma_chan_link_map[dma_lch_count]; |
| 1065 | 970 | ||
| 1066 | memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map)); | 971 | memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map)); |
| 1067 | do { | 972 | do { |
| @@ -1122,19 +1027,15 @@ dma_addr_t omap_get_dma_src_pos(int lch) | |||
| 1122 | dma_addr_t offset = 0; | 1027 | dma_addr_t offset = 0; |
| 1123 | 1028 | ||
| 1124 | if (cpu_is_omap15xx()) | 1029 | if (cpu_is_omap15xx()) |
| 1125 | offset = dma_read(CPC(lch)); | 1030 | offset = p->dma_read(CPC, lch); |
| 1126 | else | 1031 | else |
| 1127 | offset = dma_read(CSAC(lch)); | 1032 | offset = p->dma_read(CSAC, lch); |
| 1128 | 1033 | ||
| 1129 | /* | 1034 | if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0) |
| 1130 | * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is | 1035 | offset = p->dma_read(CSAC, lch); |
| 1131 | * read before the DMA controller finished disabling the channel. | ||
| 1132 | */ | ||
| 1133 | if (!cpu_is_omap15xx() && offset == 0) | ||
| 1134 | offset = dma_read(CSAC(lch)); | ||
| 1135 | 1036 | ||
| 1136 | if (cpu_class_is_omap1()) | 1037 | if (cpu_class_is_omap1()) |
| 1137 | offset |= (dma_read(CSSA_U(lch)) << 16); | 1038 | offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000); |
| 1138 | 1039 | ||
| 1139 | return offset; | 1040 | return offset; |
| 1140 | } | 1041 | } |
| @@ -1153,19 +1054,19 @@ dma_addr_t omap_get_dma_dst_pos(int lch) | |||
| 1153 | dma_addr_t offset = 0; | 1054 | dma_addr_t offset = 0; |
| 1154 | 1055 | ||
| 1155 | if (cpu_is_omap15xx()) | 1056 | if (cpu_is_omap15xx()) |
| 1156 | offset = dma_read(CPC(lch)); | 1057 | offset = p->dma_read(CPC, lch); |
| 1157 | else | 1058 | else |
| 1158 | offset = dma_read(CDAC(lch)); | 1059 | offset = p->dma_read(CDAC, lch); |
| 1159 | 1060 | ||
| 1160 | /* | 1061 | /* |
| 1161 | * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is | 1062 | * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is |
| 1162 | * read before the DMA controller finished disabling the channel. | 1063 | * read before the DMA controller finished disabling the channel. |
| 1163 | */ | 1064 | */ |
| 1164 | if (!cpu_is_omap15xx() && offset == 0) | 1065 | if (!cpu_is_omap15xx() && offset == 0) |
| 1165 | offset = dma_read(CDAC(lch)); | 1066 | offset = p->dma_read(CDAC, lch); |
| 1166 | 1067 | ||
| 1167 | if (cpu_class_is_omap1()) | 1068 | if (cpu_class_is_omap1()) |
| 1168 | offset |= (dma_read(CDSA_U(lch)) << 16); | 1069 | offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000); |
| 1169 | 1070 | ||
| 1170 | return offset; | 1071 | return offset; |
| 1171 | } | 1072 | } |
| @@ -1173,7 +1074,7 @@ EXPORT_SYMBOL(omap_get_dma_dst_pos); | |||
| 1173 | 1074 | ||
| 1174 | int omap_get_dma_active_status(int lch) | 1075 | int omap_get_dma_active_status(int lch) |
| 1175 | { | 1076 | { |
| 1176 | return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0; | 1077 | return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0; |
| 1177 | } | 1078 | } |
| 1178 | EXPORT_SYMBOL(omap_get_dma_active_status); | 1079 | EXPORT_SYMBOL(omap_get_dma_active_status); |
| 1179 | 1080 | ||
| @@ -1186,7 +1087,7 @@ int omap_dma_running(void) | |||
| 1186 | return 1; | 1087 | return 1; |
| 1187 | 1088 | ||
| 1188 | for (lch = 0; lch < dma_chan_count; lch++) | 1089 | for (lch = 0; lch < dma_chan_count; lch++) |
| 1189 | if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) | 1090 | if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) |
| 1190 | return 1; | 1091 | return 1; |
| 1191 | 1092 | ||
| 1192 | return 0; | 1093 | return 0; |
| @@ -1201,8 +1102,8 @@ void omap_dma_link_lch(int lch_head, int lch_queue) | |||
| 1201 | { | 1102 | { |
| 1202 | if (omap_dma_in_1510_mode()) { | 1103 | if (omap_dma_in_1510_mode()) { |
| 1203 | if (lch_head == lch_queue) { | 1104 | if (lch_head == lch_queue) { |
| 1204 | dma_write(dma_read(CCR(lch_head)) | (3 << 8), | 1105 | p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8), |
| 1205 | CCR(lch_head)); | 1106 | CCR, lch_head); |
| 1206 | return; | 1107 | return; |
| 1207 | } | 1108 | } |
| 1208 | printk(KERN_ERR "DMA linking is not supported in 1510 mode\n"); | 1109 | printk(KERN_ERR "DMA linking is not supported in 1510 mode\n"); |
| @@ -1228,8 +1129,8 @@ void omap_dma_unlink_lch(int lch_head, int lch_queue) | |||
| 1228 | { | 1129 | { |
| 1229 | if (omap_dma_in_1510_mode()) { | 1130 | if (omap_dma_in_1510_mode()) { |
| 1230 | if (lch_head == lch_queue) { | 1131 | if (lch_head == lch_queue) { |
| 1231 | dma_write(dma_read(CCR(lch_head)) & ~(3 << 8), | 1132 | p->dma_write(p->dma_read(CCR, lch_head) & ~(3 << 8), |
| 1232 | CCR(lch_head)); | 1133 | CCR, lch_head); |
| 1233 | return; | 1134 | return; |
| 1234 | } | 1135 | } |
| 1235 | printk(KERN_ERR "DMA linking is not supported in 1510 mode\n"); | 1136 | printk(KERN_ERR "DMA linking is not supported in 1510 mode\n"); |
| @@ -1255,8 +1156,6 @@ void omap_dma_unlink_lch(int lch_head, int lch_queue) | |||
| 1255 | } | 1156 | } |
| 1256 | EXPORT_SYMBOL(omap_dma_unlink_lch); | 1157 | EXPORT_SYMBOL(omap_dma_unlink_lch); |
| 1257 | 1158 | ||
| 1258 | /*----------------------------------------------------------------------------*/ | ||
| 1259 | |||
| 1260 | #ifndef CONFIG_ARCH_OMAP1 | 1159 | #ifndef CONFIG_ARCH_OMAP1 |
| 1261 | /* Create chain of DMA channesls */ | 1160 | /* Create chain of DMA channesls */ |
| 1262 | static void create_dma_lch_chain(int lch_head, int lch_queue) | 1161 | static void create_dma_lch_chain(int lch_head, int lch_queue) |
| @@ -1281,15 +1180,15 @@ static void create_dma_lch_chain(int lch_head, int lch_queue) | |||
| 1281 | lch_queue; | 1180 | lch_queue; |
| 1282 | } | 1181 | } |
| 1283 | 1182 | ||
| 1284 | l = dma_read(CLNK_CTRL(lch_head)); | 1183 | l = p->dma_read(CLNK_CTRL, lch_head); |
| 1285 | l &= ~(0x1f); | 1184 | l &= ~(0x1f); |
| 1286 | l |= lch_queue; | 1185 | l |= lch_queue; |
| 1287 | dma_write(l, CLNK_CTRL(lch_head)); | 1186 | p->dma_write(l, CLNK_CTRL, lch_head); |
| 1288 | 1187 | ||
| 1289 | l = dma_read(CLNK_CTRL(lch_queue)); | 1188 | l = p->dma_read(CLNK_CTRL, lch_queue); |
| 1290 | l &= ~(0x1f); | 1189 | l &= ~(0x1f); |
| 1291 | l |= (dma_chan[lch_queue].next_linked_ch); | 1190 | l |= (dma_chan[lch_queue].next_linked_ch); |
| 1292 | dma_write(l, CLNK_CTRL(lch_queue)); | 1191 | p->dma_write(l, CLNK_CTRL, lch_queue); |
| 1293 | } | 1192 | } |
| 1294 | 1193 | ||
| 1295 | /** | 1194 | /** |
| @@ -1565,13 +1464,13 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start, | |||
| 1565 | 1464 | ||
| 1566 | /* Set the params to the free channel */ | 1465 | /* Set the params to the free channel */ |
| 1567 | if (src_start != 0) | 1466 | if (src_start != 0) |
| 1568 | dma_write(src_start, CSSA(lch)); | 1467 | p->dma_write(src_start, CSSA, lch); |
| 1569 | if (dest_start != 0) | 1468 | if (dest_start != 0) |
| 1570 | dma_write(dest_start, CDSA(lch)); | 1469 | p->dma_write(dest_start, CDSA, lch); |
| 1571 | 1470 | ||
| 1572 | /* Write the buffer size */ | 1471 | /* Write the buffer size */ |
| 1573 | dma_write(elem_count, CEN(lch)); | 1472 | p->dma_write(elem_count, CEN, lch); |
| 1574 | dma_write(frame_count, CFN(lch)); | 1473 | p->dma_write(frame_count, CFN, lch); |
| 1575 | 1474 | ||
| 1576 | /* | 1475 | /* |
| 1577 | * If the chain is dynamically linked, | 1476 | * If the chain is dynamically linked, |
| @@ -1604,8 +1503,8 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start, | |||
| 1604 | enable_lnk(dma_chan[lch].prev_linked_ch); | 1503 | enable_lnk(dma_chan[lch].prev_linked_ch); |
| 1605 | dma_chan[lch].state = DMA_CH_QUEUED; | 1504 | dma_chan[lch].state = DMA_CH_QUEUED; |
| 1606 | start_dma = 0; | 1505 | start_dma = 0; |
| 1607 | if (0 == ((1 << 7) & dma_read( | 1506 | if (0 == ((1 << 7) & p->dma_read( |
| 1608 | CCR(dma_chan[lch].prev_linked_ch)))) { | 1507 | CCR, dma_chan[lch].prev_linked_ch))) { |
| 1609 | disable_lnk(dma_chan[lch]. | 1508 | disable_lnk(dma_chan[lch]. |
| 1610 | prev_linked_ch); | 1509 | prev_linked_ch); |
| 1611 | pr_debug("\n prev ch is stopped\n"); | 1510 | pr_debug("\n prev ch is stopped\n"); |
| @@ -1621,7 +1520,7 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start, | |||
| 1621 | } | 1520 | } |
| 1622 | omap_enable_channel_irq(lch); | 1521 | omap_enable_channel_irq(lch); |
| 1623 | 1522 | ||
| 1624 | l = dma_read(CCR(lch)); | 1523 | l = p->dma_read(CCR, lch); |
| 1625 | 1524 | ||
| 1626 | if ((0 == (l & (1 << 24)))) | 1525 | if ((0 == (l & (1 << 24)))) |
| 1627 | l &= ~(1 << 25); | 1526 | l &= ~(1 << 25); |
| @@ -1632,12 +1531,12 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start, | |||
| 1632 | l |= (1 << 7); | 1531 | l |= (1 << 7); |
| 1633 | dma_chan[lch].state = DMA_CH_STARTED; | 1532 | dma_chan[lch].state = DMA_CH_STARTED; |
| 1634 | pr_debug("starting %d\n", lch); | 1533 | pr_debug("starting %d\n", lch); |
| 1635 | dma_write(l, CCR(lch)); | 1534 | p->dma_write(l, CCR, lch); |
| 1636 | } else | 1535 | } else |
| 1637 | start_dma = 0; | 1536 | start_dma = 0; |
| 1638 | } else { | 1537 | } else { |
| 1639 | if (0 == (l & (1 << 7))) | 1538 | if (0 == (l & (1 << 7))) |
| 1640 | dma_write(l, CCR(lch)); | 1539 | p->dma_write(l, CCR, lch); |
| 1641 | } | 1540 | } |
| 1642 | dma_chan[lch].flags |= OMAP_DMA_ACTIVE; | 1541 | dma_chan[lch].flags |= OMAP_DMA_ACTIVE; |
| 1643 | } | 1542 | } |
| @@ -1682,7 +1581,7 @@ int omap_start_dma_chain_transfers(int chain_id) | |||
| 1682 | omap_enable_channel_irq(channels[0]); | 1581 | omap_enable_channel_irq(channels[0]); |
| 1683 | } | 1582 | } |
| 1684 | 1583 | ||
| 1685 | l = dma_read(CCR(channels[0])); | 1584 | l = p->dma_read(CCR, channels[0]); |
| 1686 | l |= (1 << 7); | 1585 | l |= (1 << 7); |
| 1687 | dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED; | 1586 | dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED; |
| 1688 | dma_chan[channels[0]].state = DMA_CH_STARTED; | 1587 | dma_chan[channels[0]].state = DMA_CH_STARTED; |
| @@ -1691,7 +1590,7 @@ int omap_start_dma_chain_transfers(int chain_id) | |||
| 1691 | l &= ~(1 << 25); | 1590 | l &= ~(1 << 25); |
| 1692 | else | 1591 | else |
| 1693 | l |= (1 << 25); | 1592 | l |= (1 << 25); |
| 1694 | dma_write(l, CCR(channels[0])); | 1593 | p->dma_write(l, CCR, channels[0]); |
| 1695 | 1594 | ||
| 1696 | dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE; | 1595 | dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE; |
| 1697 | 1596 | ||
| @@ -1711,7 +1610,7 @@ int omap_stop_dma_chain_transfers(int chain_id) | |||
| 1711 | { | 1610 | { |
| 1712 | int *channels; | 1611 | int *channels; |
| 1713 | u32 l, i; | 1612 | u32 l, i; |
| 1714 | u32 sys_cf; | 1613 | u32 sys_cf = 0; |
| 1715 | 1614 | ||
| 1716 | /* Check for input params */ | 1615 | /* Check for input params */ |
| 1717 | if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { | 1616 | if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { |
| @@ -1726,22 +1625,20 @@ int omap_stop_dma_chain_transfers(int chain_id) | |||
| 1726 | } | 1625 | } |
| 1727 | channels = dma_linked_lch[chain_id].linked_dmach_q; | 1626 | channels = dma_linked_lch[chain_id].linked_dmach_q; |
| 1728 | 1627 | ||
| 1729 | /* | 1628 | if (IS_DMA_ERRATA(DMA_ERRATA_i88)) { |
| 1730 | * DMA Errata: | 1629 | sys_cf = p->dma_read(OCP_SYSCONFIG, 0); |
| 1731 | * Special programming model needed to disable DMA before end of block | 1630 | l = sys_cf; |
| 1732 | */ | 1631 | /* Middle mode reg set no Standby */ |
| 1733 | sys_cf = dma_read(OCP_SYSCONFIG); | 1632 | l &= ~((1 << 12)|(1 << 13)); |
| 1734 | l = sys_cf; | 1633 | p->dma_write(l, OCP_SYSCONFIG, 0); |
| 1735 | /* Middle mode reg set no Standby */ | 1634 | } |
| 1736 | l &= ~((1 << 12)|(1 << 13)); | ||
| 1737 | dma_write(l, OCP_SYSCONFIG); | ||
| 1738 | 1635 | ||
| 1739 | for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) { | 1636 | for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) { |
| 1740 | 1637 | ||
| 1741 | /* Stop the Channel transmission */ | 1638 | /* Stop the Channel transmission */ |
| 1742 | l = dma_read(CCR(channels[i])); | 1639 | l = p->dma_read(CCR, channels[i]); |
| 1743 | l &= ~(1 << 7); | 1640 | l &= ~(1 << 7); |
| 1744 | dma_write(l, CCR(channels[i])); | 1641 | p->dma_write(l, CCR, channels[i]); |
| 1745 | 1642 | ||
| 1746 | /* Disable the link in all the channels */ | 1643 | /* Disable the link in all the channels */ |
| 1747 | disable_lnk(channels[i]); | 1644 | disable_lnk(channels[i]); |
| @@ -1753,8 +1650,8 @@ int omap_stop_dma_chain_transfers(int chain_id) | |||
| 1753 | /* Reset the Queue pointers */ | 1650 | /* Reset the Queue pointers */ |
| 1754 | OMAP_DMA_CHAIN_QINIT(chain_id); | 1651 | OMAP_DMA_CHAIN_QINIT(chain_id); |
| 1755 | 1652 | ||
| 1756 | /* Errata - put in the old value */ | 1653 | if (IS_DMA_ERRATA(DMA_ERRATA_i88)) |
| 1757 | dma_write(sys_cf, OCP_SYSCONFIG); | 1654 | p->dma_write(sys_cf, OCP_SYSCONFIG, 0); |
| 1758 | 1655 | ||
| 1759 | return 0; | 1656 | return 0; |
| 1760 | } | 1657 | } |
| @@ -1796,8 +1693,8 @@ int omap_get_dma_chain_index(int chain_id, int *ei, int *fi) | |||
| 1796 | /* Get the current channel */ | 1693 | /* Get the current channel */ |
| 1797 | lch = channels[dma_linked_lch[chain_id].q_head]; | 1694 | lch = channels[dma_linked_lch[chain_id].q_head]; |
| 1798 | 1695 | ||
| 1799 | *ei = dma_read(CCEN(lch)); | 1696 | *ei = p->dma_read(CCEN, lch); |
| 1800 | *fi = dma_read(CCFN(lch)); | 1697 | *fi = p->dma_read(CCFN, lch); |
| 1801 | 1698 | ||
| 1802 | return 0; | 1699 | return 0; |
| 1803 | } | 1700 | } |
| @@ -1834,7 +1731,7 @@ int omap_get_dma_chain_dst_pos(int chain_id) | |||
| 1834 | /* Get the current channel */ | 1731 | /* Get the current channel */ |
| 1835 | lch = channels[dma_linked_lch[chain_id].q_head]; | 1732 | lch = channels[dma_linked_lch[chain_id].q_head]; |
| 1836 | 1733 | ||
| 1837 | return dma_read(CDAC(lch)); | 1734 | return p->dma_read(CDAC, lch); |
| 1838 | } | 1735 | } |
| 1839 | EXPORT_SYMBOL(omap_get_dma_chain_dst_pos); | 1736 | EXPORT_SYMBOL(omap_get_dma_chain_dst_pos); |
| 1840 | 1737 | ||
| @@ -1868,7 +1765,7 @@ int omap_get_dma_chain_src_pos(int chain_id) | |||
| 1868 | /* Get the current channel */ | 1765 | /* Get the current channel */ |
| 1869 | lch = channels[dma_linked_lch[chain_id].q_head]; | 1766 | lch = channels[dma_linked_lch[chain_id].q_head]; |
| 1870 | 1767 | ||
| 1871 | return dma_read(CSAC(lch)); | 1768 | return p->dma_read(CSAC, lch); |
| 1872 | } | 1769 | } |
| 1873 | EXPORT_SYMBOL(omap_get_dma_chain_src_pos); | 1770 | EXPORT_SYMBOL(omap_get_dma_chain_src_pos); |
| 1874 | #endif /* ifndef CONFIG_ARCH_OMAP1 */ | 1771 | #endif /* ifndef CONFIG_ARCH_OMAP1 */ |
| @@ -1885,7 +1782,7 @@ static int omap1_dma_handle_ch(int ch) | |||
| 1885 | csr = dma_chan[ch].saved_csr; | 1782 | csr = dma_chan[ch].saved_csr; |
| 1886 | dma_chan[ch].saved_csr = 0; | 1783 | dma_chan[ch].saved_csr = 0; |
| 1887 | } else | 1784 | } else |
| 1888 | csr = dma_read(CSR(ch)); | 1785 | csr = p->dma_read(CSR, ch); |
| 1889 | if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) { | 1786 | if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) { |
| 1890 | dma_chan[ch + 6].saved_csr = csr >> 7; | 1787 | dma_chan[ch + 6].saved_csr = csr >> 7; |
| 1891 | csr &= 0x7f; | 1788 | csr &= 0x7f; |
| @@ -1938,13 +1835,13 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id) | |||
| 1938 | 1835 | ||
| 1939 | static int omap2_dma_handle_ch(int ch) | 1836 | static int omap2_dma_handle_ch(int ch) |
| 1940 | { | 1837 | { |
| 1941 | u32 status = dma_read(CSR(ch)); | 1838 | u32 status = p->dma_read(CSR, ch); |
| 1942 | 1839 | ||
| 1943 | if (!status) { | 1840 | if (!status) { |
| 1944 | if (printk_ratelimit()) | 1841 | if (printk_ratelimit()) |
| 1945 | printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n", | 1842 | printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n", |
| 1946 | ch); | 1843 | ch); |
| 1947 | dma_write(1 << ch, IRQSTATUS_L0); | 1844 | p->dma_write(1 << ch, IRQSTATUS_L0, ch); |
| 1948 | return 0; | 1845 | return 0; |
| 1949 | } | 1846 | } |
| 1950 | if (unlikely(dma_chan[ch].dev_id == -1)) { | 1847 | if (unlikely(dma_chan[ch].dev_id == -1)) { |
| @@ -1960,17 +1857,12 @@ static int omap2_dma_handle_ch(int ch) | |||
| 1960 | if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) { | 1857 | if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) { |
| 1961 | printk(KERN_INFO "DMA transaction error with device %d\n", | 1858 | printk(KERN_INFO "DMA transaction error with device %d\n", |
| 1962 | dma_chan[ch].dev_id); | 1859 | dma_chan[ch].dev_id); |
| 1963 | if (cpu_class_is_omap2()) { | 1860 | if (IS_DMA_ERRATA(DMA_ERRATA_i378)) { |
| 1964 | /* | ||
| 1965 | * Errata: sDMA Channel is not disabled | ||
| 1966 | * after a transaction error. So we explicitely | ||
| 1967 | * disable the channel | ||
| 1968 | */ | ||
| 1969 | u32 ccr; | 1861 | u32 ccr; |
| 1970 | 1862 | ||
| 1971 | ccr = dma_read(CCR(ch)); | 1863 | ccr = p->dma_read(CCR, ch); |
| 1972 | ccr &= ~OMAP_DMA_CCR_EN; | 1864 | ccr &= ~OMAP_DMA_CCR_EN; |
| 1973 | dma_write(ccr, CCR(ch)); | 1865 | p->dma_write(ccr, CCR, ch); |
| 1974 | dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; | 1866 | dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; |
| 1975 | } | 1867 | } |
| 1976 | } | 1868 | } |
| @@ -1981,16 +1873,16 @@ static int omap2_dma_handle_ch(int ch) | |||
| 1981 | printk(KERN_INFO "DMA misaligned error with device %d\n", | 1873 | printk(KERN_INFO "DMA misaligned error with device %d\n", |
| 1982 | dma_chan[ch].dev_id); | 1874 | dma_chan[ch].dev_id); |
| 1983 | 1875 | ||
| 1984 | dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch)); | 1876 | p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, ch); |
| 1985 | dma_write(1 << ch, IRQSTATUS_L0); | 1877 | p->dma_write(1 << ch, IRQSTATUS_L0, ch); |
| 1986 | /* read back the register to flush the write */ | 1878 | /* read back the register to flush the write */ |
| 1987 | dma_read(IRQSTATUS_L0); | 1879 | p->dma_read(IRQSTATUS_L0, ch); |
| 1988 | 1880 | ||
| 1989 | /* If the ch is not chained then chain_id will be -1 */ | 1881 | /* If the ch is not chained then chain_id will be -1 */ |
| 1990 | if (dma_chan[ch].chain_id != -1) { | 1882 | if (dma_chan[ch].chain_id != -1) { |
| 1991 | int chain_id = dma_chan[ch].chain_id; | 1883 | int chain_id = dma_chan[ch].chain_id; |
| 1992 | dma_chan[ch].state = DMA_CH_NOTSTARTED; | 1884 | dma_chan[ch].state = DMA_CH_NOTSTARTED; |
| 1993 | if (dma_read(CLNK_CTRL(ch)) & (1 << 15)) | 1885 | if (p->dma_read(CLNK_CTRL, ch) & (1 << 15)) |
| 1994 | dma_chan[dma_chan[ch].next_linked_ch].state = | 1886 | dma_chan[dma_chan[ch].next_linked_ch].state = |
| 1995 | DMA_CH_STARTED; | 1887 | DMA_CH_STARTED; |
| 1996 | if (dma_linked_lch[chain_id].chain_mode == | 1888 | if (dma_linked_lch[chain_id].chain_mode == |
| @@ -2000,10 +1892,10 @@ static int omap2_dma_handle_ch(int ch) | |||
| 2000 | if (!OMAP_DMA_CHAIN_QEMPTY(chain_id)) | 1892 | if (!OMAP_DMA_CHAIN_QEMPTY(chain_id)) |
| 2001 | OMAP_DMA_CHAIN_INCQHEAD(chain_id); | 1893 | OMAP_DMA_CHAIN_INCQHEAD(chain_id); |
| 2002 | 1894 | ||
| 2003 | status = dma_read(CSR(ch)); | 1895 | status = p->dma_read(CSR, ch); |
| 2004 | } | 1896 | } |
| 2005 | 1897 | ||
| 2006 | dma_write(status, CSR(ch)); | 1898 | p->dma_write(status, CSR, ch); |
| 2007 | 1899 | ||
| 2008 | if (likely(dma_chan[ch].callback != NULL)) | 1900 | if (likely(dma_chan[ch].callback != NULL)) |
| 2009 | dma_chan[ch].callback(ch, status, dma_chan[ch].data); | 1901 | dma_chan[ch].callback(ch, status, dma_chan[ch].data); |
| @@ -2017,13 +1909,13 @@ static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id) | |||
| 2017 | u32 val, enable_reg; | 1909 | u32 val, enable_reg; |
| 2018 | int i; | 1910 | int i; |
| 2019 | 1911 | ||
| 2020 | val = dma_read(IRQSTATUS_L0); | 1912 | val = p->dma_read(IRQSTATUS_L0, 0); |
| 2021 | if (val == 0) { | 1913 | if (val == 0) { |
| 2022 | if (printk_ratelimit()) | 1914 | if (printk_ratelimit()) |
| 2023 | printk(KERN_WARNING "Spurious DMA IRQ\n"); | 1915 | printk(KERN_WARNING "Spurious DMA IRQ\n"); |
| 2024 | return IRQ_HANDLED; | 1916 | return IRQ_HANDLED; |
| 2025 | } | 1917 | } |
| 2026 | enable_reg = dma_read(IRQENABLE_L0); | 1918 | enable_reg = p->dma_read(IRQENABLE_L0, 0); |
| 2027 | val &= enable_reg; /* Dispatch only relevant interrupts */ | 1919 | val &= enable_reg; /* Dispatch only relevant interrupts */ |
| 2028 | for (i = 0; i < dma_lch_count && val != 0; i++) { | 1920 | for (i = 0; i < dma_lch_count && val != 0; i++) { |
| 2029 | if (val & 1) | 1921 | if (val & 1) |
| @@ -2049,119 +1941,66 @@ static struct irqaction omap24xx_dma_irq; | |||
| 2049 | void omap_dma_global_context_save(void) | 1941 | void omap_dma_global_context_save(void) |
| 2050 | { | 1942 | { |
| 2051 | omap_dma_global_context.dma_irqenable_l0 = | 1943 | omap_dma_global_context.dma_irqenable_l0 = |
| 2052 | dma_read(IRQENABLE_L0); | 1944 | p->dma_read(IRQENABLE_L0, 0); |
| 2053 | omap_dma_global_context.dma_ocp_sysconfig = | 1945 | omap_dma_global_context.dma_ocp_sysconfig = |
| 2054 | dma_read(OCP_SYSCONFIG); | 1946 | p->dma_read(OCP_SYSCONFIG, 0); |
| 2055 | omap_dma_global_context.dma_gcr = dma_read(GCR); | 1947 | omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0); |
| 2056 | } | 1948 | } |
| 2057 | 1949 | ||
| 2058 | void omap_dma_global_context_restore(void) | 1950 | void omap_dma_global_context_restore(void) |
| 2059 | { | 1951 | { |
| 2060 | int ch; | 1952 | int ch; |
| 2061 | 1953 | ||
| 2062 | dma_write(omap_dma_global_context.dma_gcr, GCR); | 1954 | p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0); |
| 2063 | dma_write(omap_dma_global_context.dma_ocp_sysconfig, | 1955 | p->dma_write(omap_dma_global_context.dma_ocp_sysconfig, |
| 2064 | OCP_SYSCONFIG); | 1956 | OCP_SYSCONFIG, 0); |
| 2065 | dma_write(omap_dma_global_context.dma_irqenable_l0, | 1957 | p->dma_write(omap_dma_global_context.dma_irqenable_l0, |
| 2066 | IRQENABLE_L0); | 1958 | IRQENABLE_L0, 0); |
| 2067 | 1959 | ||
| 2068 | /* | 1960 | if (IS_DMA_ERRATA(DMA_ROMCODE_BUG)) |
| 2069 | * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared | 1961 | p->dma_write(0x3 , IRQSTATUS_L0, 0); |
| 2070 | * after secure sram context save and restore. Hence we need to | ||
| 2071 | * manually clear those IRQs to avoid spurious interrupts. This | ||
| 2072 | * affects only secure devices. | ||
| 2073 | */ | ||
| 2074 | if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) | ||
| 2075 | dma_write(0x3 , IRQSTATUS_L0); | ||
| 2076 | 1962 | ||
| 2077 | for (ch = 0; ch < dma_chan_count; ch++) | 1963 | for (ch = 0; ch < dma_chan_count; ch++) |
| 2078 | if (dma_chan[ch].dev_id != -1) | 1964 | if (dma_chan[ch].dev_id != -1) |
| 2079 | omap_clear_dma(ch); | 1965 | omap_clear_dma(ch); |
| 2080 | } | 1966 | } |
| 2081 | 1967 | ||
| 2082 | /*----------------------------------------------------------------------------*/ | 1968 | static int __devinit omap_system_dma_probe(struct platform_device *pdev) |
| 2083 | |||
| 2084 | static int __init omap_init_dma(void) | ||
| 2085 | { | 1969 | { |
| 2086 | unsigned long base; | 1970 | int ch, ret = 0; |
| 2087 | int ch, r; | 1971 | int dma_irq; |
| 2088 | 1972 | char irq_name[4]; | |
| 2089 | if (cpu_class_is_omap1()) { | 1973 | int irq_rel; |
| 2090 | base = OMAP1_DMA_BASE; | 1974 | |
| 2091 | dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT; | 1975 | p = pdev->dev.platform_data; |
| 2092 | } else if (cpu_is_omap24xx()) { | 1976 | if (!p) { |
| 2093 | base = OMAP24XX_DMA4_BASE; | 1977 | dev_err(&pdev->dev, "%s: System DMA initialized without" |
| 2094 | dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; | 1978 | "platform data\n", __func__); |
| 2095 | } else if (cpu_is_omap34xx()) { | 1979 | return -EINVAL; |
| 2096 | base = OMAP34XX_DMA4_BASE; | ||
| 2097 | dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; | ||
| 2098 | } else if (cpu_is_omap44xx()) { | ||
| 2099 | base = OMAP44XX_DMA4_BASE; | ||
| 2100 | dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; | ||
| 2101 | } else { | ||
| 2102 | pr_err("DMA init failed for unsupported omap\n"); | ||
| 2103 | return -ENODEV; | ||
| 2104 | } | 1980 | } |
| 2105 | 1981 | ||
| 2106 | omap_dma_base = ioremap(base, SZ_4K); | 1982 | d = p->dma_attr; |
| 2107 | BUG_ON(!omap_dma_base); | 1983 | errata = p->errata; |
| 2108 | 1984 | ||
| 2109 | if (cpu_class_is_omap2() && omap_dma_reserve_channels | 1985 | if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels |
| 2110 | && (omap_dma_reserve_channels <= dma_lch_count)) | 1986 | && (omap_dma_reserve_channels <= dma_lch_count)) |
| 2111 | dma_lch_count = omap_dma_reserve_channels; | 1987 | d->lch_count = omap_dma_reserve_channels; |
| 2112 | 1988 | ||
| 2113 | dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count, | 1989 | dma_lch_count = d->lch_count; |
| 2114 | GFP_KERNEL); | 1990 | dma_chan_count = dma_lch_count; |
| 2115 | if (!dma_chan) { | 1991 | dma_chan = d->chan; |
| 2116 | r = -ENOMEM; | 1992 | enable_1510_mode = d->dev_caps & ENABLE_1510_MODE; |
| 2117 | goto out_unmap; | ||
| 2118 | } | ||
| 2119 | 1993 | ||
| 2120 | if (cpu_class_is_omap2()) { | 1994 | if (cpu_class_is_omap2()) { |
| 2121 | dma_linked_lch = kzalloc(sizeof(struct dma_link_info) * | 1995 | dma_linked_lch = kzalloc(sizeof(struct dma_link_info) * |
| 2122 | dma_lch_count, GFP_KERNEL); | 1996 | dma_lch_count, GFP_KERNEL); |
| 2123 | if (!dma_linked_lch) { | 1997 | if (!dma_linked_lch) { |
| 2124 | r = -ENOMEM; | 1998 | ret = -ENOMEM; |
| 2125 | goto out_free; | 1999 | goto exit_dma_lch_fail; |
| 2126 | } | 2000 | } |
| 2127 | } | 2001 | } |
| 2128 | 2002 | ||
| 2129 | if (cpu_is_omap15xx()) { | ||
| 2130 | printk(KERN_INFO "DMA support for OMAP15xx initialized\n"); | ||
| 2131 | dma_chan_count = 9; | ||
| 2132 | enable_1510_mode = 1; | ||
| 2133 | } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) { | ||
| 2134 | printk(KERN_INFO "OMAP DMA hardware version %d\n", | ||
| 2135 | dma_read(HW_ID)); | ||
| 2136 | printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n", | ||
| 2137 | (dma_read(CAPS_0_U) << 16) | | ||
| 2138 | dma_read(CAPS_0_L), | ||
| 2139 | (dma_read(CAPS_1_U) << 16) | | ||
| 2140 | dma_read(CAPS_1_L), | ||
| 2141 | dma_read(CAPS_2), dma_read(CAPS_3), | ||
| 2142 | dma_read(CAPS_4)); | ||
| 2143 | if (!enable_1510_mode) { | ||
| 2144 | u16 w; | ||
| 2145 | |||
| 2146 | /* Disable OMAP 3.0/3.1 compatibility mode. */ | ||
| 2147 | w = dma_read(GSCR); | ||
| 2148 | w |= 1 << 3; | ||
| 2149 | dma_write(w, GSCR); | ||
| 2150 | dma_chan_count = 16; | ||
| 2151 | } else | ||
| 2152 | dma_chan_count = 9; | ||
| 2153 | } else if (cpu_class_is_omap2()) { | ||
| 2154 | u8 revision = dma_read(REVISION) & 0xff; | ||
| 2155 | printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n", | ||
| 2156 | revision >> 4, revision & 0xf); | ||
| 2157 | dma_chan_count = dma_lch_count; | ||
| 2158 | } else { | ||
| 2159 | dma_chan_count = 0; | ||
| 2160 | return 0; | ||
| 2161 | } | ||
| 2162 | |||
| 2163 | spin_lock_init(&dma_chan_lock); | 2003 | spin_lock_init(&dma_chan_lock); |
| 2164 | |||
| 2165 | for (ch = 0; ch < dma_chan_count; ch++) { | 2004 | for (ch = 0; ch < dma_chan_count; ch++) { |
| 2166 | omap_clear_dma(ch); | 2005 | omap_clear_dma(ch); |
| 2167 | if (cpu_class_is_omap2()) | 2006 | if (cpu_class_is_omap2()) |
| @@ -2178,20 +2017,23 @@ static int __init omap_init_dma(void) | |||
| 2178 | * request_irq() doesn't like dev_id (ie. ch) being | 2017 | * request_irq() doesn't like dev_id (ie. ch) being |
| 2179 | * zero, so we have to kludge around this. | 2018 | * zero, so we have to kludge around this. |
| 2180 | */ | 2019 | */ |
| 2181 | r = request_irq(omap1_dma_irq[ch], | 2020 | sprintf(&irq_name[0], "%d", ch); |
| 2021 | dma_irq = platform_get_irq_byname(pdev, irq_name); | ||
| 2022 | |||
| 2023 | if (dma_irq < 0) { | ||
| 2024 | ret = dma_irq; | ||
| 2025 | goto exit_dma_irq_fail; | ||
| 2026 | } | ||
| 2027 | |||
| 2028 | /* INT_DMA_LCD is handled in lcd_dma.c */ | ||
| 2029 | if (dma_irq == INT_DMA_LCD) | ||
| 2030 | continue; | ||
| 2031 | |||
| 2032 | ret = request_irq(dma_irq, | ||
| 2182 | omap1_dma_irq_handler, 0, "DMA", | 2033 | omap1_dma_irq_handler, 0, "DMA", |
| 2183 | (void *) (ch + 1)); | 2034 | (void *) (ch + 1)); |
| 2184 | if (r != 0) { | 2035 | if (ret != 0) |
| 2185 | int i; | 2036 | goto exit_dma_irq_fail; |
| 2186 | |||
| 2187 | printk(KERN_ERR "unable to request IRQ %d " | ||
| 2188 | "for DMA (error %d)\n", | ||
| 2189 | omap1_dma_irq[ch], r); | ||
| 2190 | for (i = 0; i < ch; i++) | ||
| 2191 | free_irq(omap1_dma_irq[i], | ||
| 2192 | (void *) (i + 1)); | ||
| 2193 | goto out_free; | ||
| 2194 | } | ||
| 2195 | } | 2037 | } |
| 2196 | } | 2038 | } |
| 2197 | 2039 | ||
| @@ -2200,46 +2042,91 @@ static int __init omap_init_dma(void) | |||
| 2200 | DMA_DEFAULT_FIFO_DEPTH, 0); | 2042 | DMA_DEFAULT_FIFO_DEPTH, 0); |
| 2201 | 2043 | ||
| 2202 | if (cpu_class_is_omap2()) { | 2044 | if (cpu_class_is_omap2()) { |
| 2203 | int irq; | 2045 | strcpy(irq_name, "0"); |
| 2204 | if (cpu_is_omap44xx()) | 2046 | dma_irq = platform_get_irq_byname(pdev, irq_name); |
| 2205 | irq = OMAP44XX_IRQ_SDMA_0; | 2047 | if (dma_irq < 0) { |
| 2206 | else | 2048 | dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq); |
| 2207 | irq = INT_24XX_SDMA_IRQ0; | 2049 | goto exit_dma_lch_fail; |
| 2208 | setup_irq(irq, &omap24xx_dma_irq); | 2050 | } |
| 2209 | } | 2051 | ret = setup_irq(dma_irq, &omap24xx_dma_irq); |
| 2210 | 2052 | if (ret) { | |
| 2211 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) { | 2053 | dev_err(&pdev->dev, "set_up failed for IRQ %d" |
| 2212 | /* Enable smartidle idlemodes and autoidle */ | 2054 | "for DMA (error %d)\n", dma_irq, ret); |
| 2213 | u32 v = dma_read(OCP_SYSCONFIG); | 2055 | goto exit_dma_lch_fail; |
| 2214 | v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK | | ||
| 2215 | DMA_SYSCONFIG_SIDLEMODE_MASK | | ||
| 2216 | DMA_SYSCONFIG_AUTOIDLE); | ||
| 2217 | v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) | | ||
| 2218 | DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) | | ||
| 2219 | DMA_SYSCONFIG_AUTOIDLE); | ||
| 2220 | dma_write(v , OCP_SYSCONFIG); | ||
| 2221 | /* reserve dma channels 0 and 1 in high security devices */ | ||
| 2222 | if (cpu_is_omap34xx() && | ||
| 2223 | (omap_type() != OMAP2_DEVICE_TYPE_GP)) { | ||
| 2224 | printk(KERN_INFO "Reserving DMA channels 0 and 1 for " | ||
| 2225 | "HS ROM code\n"); | ||
| 2226 | dma_chan[0].dev_id = 0; | ||
| 2227 | dma_chan[1].dev_id = 1; | ||
| 2228 | } | 2056 | } |
| 2229 | } | 2057 | } |
| 2230 | 2058 | ||
| 2059 | /* reserve dma channels 0 and 1 in high security devices */ | ||
| 2060 | if (cpu_is_omap34xx() && | ||
| 2061 | (omap_type() != OMAP2_DEVICE_TYPE_GP)) { | ||
| 2062 | printk(KERN_INFO "Reserving DMA channels 0 and 1 for " | ||
| 2063 | "HS ROM code\n"); | ||
| 2064 | dma_chan[0].dev_id = 0; | ||
| 2065 | dma_chan[1].dev_id = 1; | ||
| 2066 | } | ||
| 2067 | p->show_dma_caps(); | ||
| 2231 | return 0; | 2068 | return 0; |
| 2232 | 2069 | ||
| 2233 | out_free: | 2070 | exit_dma_irq_fail: |
| 2071 | dev_err(&pdev->dev, "unable to request IRQ %d" | ||
| 2072 | "for DMA (error %d)\n", dma_irq, ret); | ||
| 2073 | for (irq_rel = 0; irq_rel < ch; irq_rel++) { | ||
| 2074 | dma_irq = platform_get_irq(pdev, irq_rel); | ||
| 2075 | free_irq(dma_irq, (void *)(irq_rel + 1)); | ||
| 2076 | } | ||
| 2077 | |||
| 2078 | exit_dma_lch_fail: | ||
| 2079 | kfree(p); | ||
| 2080 | kfree(d); | ||
| 2234 | kfree(dma_chan); | 2081 | kfree(dma_chan); |
| 2082 | return ret; | ||
| 2083 | } | ||
| 2235 | 2084 | ||
| 2236 | out_unmap: | 2085 | static int __devexit omap_system_dma_remove(struct platform_device *pdev) |
| 2237 | iounmap(omap_dma_base); | 2086 | { |
| 2087 | int dma_irq; | ||
| 2238 | 2088 | ||
| 2239 | return r; | 2089 | if (cpu_class_is_omap2()) { |
| 2090 | char irq_name[4]; | ||
| 2091 | strcpy(irq_name, "0"); | ||
| 2092 | dma_irq = platform_get_irq_byname(pdev, irq_name); | ||
| 2093 | remove_irq(dma_irq, &omap24xx_dma_irq); | ||
| 2094 | } else { | ||
| 2095 | int irq_rel = 0; | ||
| 2096 | for ( ; irq_rel < dma_chan_count; irq_rel++) { | ||
| 2097 | dma_irq = platform_get_irq(pdev, irq_rel); | ||
| 2098 | free_irq(dma_irq, (void *)(irq_rel + 1)); | ||
| 2099 | } | ||
| 2100 | } | ||
| 2101 | kfree(p); | ||
| 2102 | kfree(d); | ||
| 2103 | kfree(dma_chan); | ||
| 2104 | return 0; | ||
| 2105 | } | ||
| 2106 | |||
| 2107 | static struct platform_driver omap_system_dma_driver = { | ||
| 2108 | .probe = omap_system_dma_probe, | ||
| 2109 | .remove = omap_system_dma_remove, | ||
| 2110 | .driver = { | ||
| 2111 | .name = "omap_dma_system" | ||
| 2112 | }, | ||
| 2113 | }; | ||
| 2114 | |||
| 2115 | static int __init omap_system_dma_init(void) | ||
| 2116 | { | ||
| 2117 | return platform_driver_register(&omap_system_dma_driver); | ||
| 2118 | } | ||
| 2119 | arch_initcall(omap_system_dma_init); | ||
| 2120 | |||
| 2121 | static void __exit omap_system_dma_exit(void) | ||
| 2122 | { | ||
| 2123 | platform_driver_unregister(&omap_system_dma_driver); | ||
| 2240 | } | 2124 | } |
| 2241 | 2125 | ||
| 2242 | arch_initcall(omap_init_dma); | 2126 | MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER"); |
| 2127 | MODULE_LICENSE("GPL"); | ||
| 2128 | MODULE_ALIAS("platform:" DRIVER_NAME); | ||
| 2129 | MODULE_AUTHOR("Texas Instruments Inc"); | ||
| 2243 | 2130 | ||
| 2244 | /* | 2131 | /* |
| 2245 | * Reserve the omap SDMA channels using cmdline bootarg | 2132 | * Reserve the omap SDMA channels using cmdline bootarg |
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index c05c653d1674..1f98e0b94847 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c | |||
| @@ -21,18 +21,18 @@ | |||
| 21 | #include <linux/err.h> | 21 | #include <linux/err.h> |
| 22 | #include <linux/clk.h> | 22 | #include <linux/clk.h> |
| 23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
| 24 | #include <linux/slab.h> | ||
| 25 | #include <linux/pm_runtime.h> | ||
| 24 | 26 | ||
| 25 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
| 26 | #include <asm/irq.h> | 28 | #include <asm/irq.h> |
| 27 | #include <mach/irqs.h> | 29 | #include <mach/irqs.h> |
| 28 | #include <mach/gpio.h> | 30 | #include <mach/gpio.h> |
| 29 | #include <asm/mach/irq.h> | 31 | #include <asm/mach/irq.h> |
| 30 | #include <plat/powerdomain.h> | ||
| 31 | 32 | ||
| 32 | /* | 33 | /* |
| 33 | * OMAP1510 GPIO registers | 34 | * OMAP1510 GPIO registers |
| 34 | */ | 35 | */ |
| 35 | #define OMAP1510_GPIO_BASE 0xfffce000 | ||
| 36 | #define OMAP1510_GPIO_DATA_INPUT 0x00 | 36 | #define OMAP1510_GPIO_DATA_INPUT 0x00 |
| 37 | #define OMAP1510_GPIO_DATA_OUTPUT 0x04 | 37 | #define OMAP1510_GPIO_DATA_OUTPUT 0x04 |
| 38 | #define OMAP1510_GPIO_DIR_CONTROL 0x08 | 38 | #define OMAP1510_GPIO_DIR_CONTROL 0x08 |
| @@ -46,10 +46,6 @@ | |||
| 46 | /* | 46 | /* |
| 47 | * OMAP1610 specific GPIO registers | 47 | * OMAP1610 specific GPIO registers |
| 48 | */ | 48 | */ |
| 49 | #define OMAP1610_GPIO1_BASE 0xfffbe400 | ||
| 50 | #define OMAP1610_GPIO2_BASE 0xfffbec00 | ||
| 51 | #define OMAP1610_GPIO3_BASE 0xfffbb400 | ||
| 52 | #define OMAP1610_GPIO4_BASE 0xfffbbc00 | ||
| 53 | #define OMAP1610_GPIO_REVISION 0x0000 | 49 | #define OMAP1610_GPIO_REVISION 0x0000 |
| 54 | #define OMAP1610_GPIO_SYSCONFIG 0x0010 | 50 | #define OMAP1610_GPIO_SYSCONFIG 0x0010 |
| 55 | #define OMAP1610_GPIO_SYSSTATUS 0x0014 | 51 | #define OMAP1610_GPIO_SYSSTATUS 0x0014 |
| @@ -71,12 +67,6 @@ | |||
| 71 | /* | 67 | /* |
| 72 | * OMAP7XX specific GPIO registers | 68 | * OMAP7XX specific GPIO registers |
| 73 | */ | 69 | */ |
| 74 | #define OMAP7XX_GPIO1_BASE 0xfffbc000 | ||
| 75 | #define OMAP7XX_GPIO2_BASE 0xfffbc800 | ||
| 76 | #define OMAP7XX_GPIO3_BASE 0xfffbd000 | ||
| 77 | #define OMAP7XX_GPIO4_BASE 0xfffbd800 | ||
| 78 | #define OMAP7XX_GPIO5_BASE 0xfffbe000 | ||
| 79 | #define OMAP7XX_GPIO6_BASE 0xfffbe800 | ||
| 80 | #define OMAP7XX_GPIO_DATA_INPUT 0x00 | 70 | #define OMAP7XX_GPIO_DATA_INPUT 0x00 |
| 81 | #define OMAP7XX_GPIO_DATA_OUTPUT 0x04 | 71 | #define OMAP7XX_GPIO_DATA_OUTPUT 0x04 |
| 82 | #define OMAP7XX_GPIO_DIR_CONTROL 0x08 | 72 | #define OMAP7XX_GPIO_DIR_CONTROL 0x08 |
| @@ -84,25 +74,10 @@ | |||
| 84 | #define OMAP7XX_GPIO_INT_MASK 0x10 | 74 | #define OMAP7XX_GPIO_INT_MASK 0x10 |
| 85 | #define OMAP7XX_GPIO_INT_STATUS 0x14 | 75 | #define OMAP7XX_GPIO_INT_STATUS 0x14 |
| 86 | 76 | ||
| 87 | #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE | ||
| 88 | |||
| 89 | /* | 77 | /* |
| 90 | * omap24xx specific GPIO registers | 78 | * omap2+ specific GPIO registers |
| 91 | */ | 79 | */ |
| 92 | #define OMAP242X_GPIO1_BASE 0x48018000 | ||
| 93 | #define OMAP242X_GPIO2_BASE 0x4801a000 | ||
| 94 | #define OMAP242X_GPIO3_BASE 0x4801c000 | ||
| 95 | #define OMAP242X_GPIO4_BASE 0x4801e000 | ||
| 96 | |||
| 97 | #define OMAP243X_GPIO1_BASE 0x4900C000 | ||
| 98 | #define OMAP243X_GPIO2_BASE 0x4900E000 | ||
| 99 | #define OMAP243X_GPIO3_BASE 0x49010000 | ||
| 100 | #define OMAP243X_GPIO4_BASE 0x49012000 | ||
| 101 | #define OMAP243X_GPIO5_BASE 0x480B6000 | ||
| 102 | |||
| 103 | #define OMAP24XX_GPIO_REVISION 0x0000 | 80 | #define OMAP24XX_GPIO_REVISION 0x0000 |
| 104 | #define OMAP24XX_GPIO_SYSCONFIG 0x0010 | ||
| 105 | #define OMAP24XX_GPIO_SYSSTATUS 0x0014 | ||
| 106 | #define OMAP24XX_GPIO_IRQSTATUS1 0x0018 | 81 | #define OMAP24XX_GPIO_IRQSTATUS1 0x0018 |
| 107 | #define OMAP24XX_GPIO_IRQSTATUS2 0x0028 | 82 | #define OMAP24XX_GPIO_IRQSTATUS2 0x0028 |
| 108 | #define OMAP24XX_GPIO_IRQENABLE2 0x002c | 83 | #define OMAP24XX_GPIO_IRQENABLE2 0x002c |
| @@ -126,7 +101,6 @@ | |||
| 126 | #define OMAP24XX_GPIO_SETDATAOUT 0x0094 | 101 | #define OMAP24XX_GPIO_SETDATAOUT 0x0094 |
| 127 | 102 | ||
| 128 | #define OMAP4_GPIO_REVISION 0x0000 | 103 | #define OMAP4_GPIO_REVISION 0x0000 |
| 129 | #define OMAP4_GPIO_SYSCONFIG 0x0010 | ||
| 130 | #define OMAP4_GPIO_EOI 0x0020 | 104 | #define OMAP4_GPIO_EOI 0x0020 |
| 131 | #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024 | 105 | #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024 |
| 132 | #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028 | 106 | #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028 |
| @@ -138,7 +112,6 @@ | |||
| 138 | #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040 | 112 | #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040 |
| 139 | #define OMAP4_GPIO_IRQWAKEN0 0x0044 | 113 | #define OMAP4_GPIO_IRQWAKEN0 0x0044 |
| 140 | #define OMAP4_GPIO_IRQWAKEN1 0x0048 | 114 | #define OMAP4_GPIO_IRQWAKEN1 0x0048 |
| 141 | #define OMAP4_GPIO_SYSSTATUS 0x0114 | ||
| 142 | #define OMAP4_GPIO_IRQENABLE1 0x011c | 115 | #define OMAP4_GPIO_IRQENABLE1 0x011c |
| 143 | #define OMAP4_GPIO_WAKE_EN 0x0120 | 116 | #define OMAP4_GPIO_WAKE_EN 0x0120 |
| 144 | #define OMAP4_GPIO_IRQSTATUS2 0x0128 | 117 | #define OMAP4_GPIO_IRQSTATUS2 0x0128 |
| @@ -159,26 +132,6 @@ | |||
| 159 | #define OMAP4_GPIO_SETWKUENA 0x0184 | 132 | #define OMAP4_GPIO_SETWKUENA 0x0184 |
| 160 | #define OMAP4_GPIO_CLEARDATAOUT 0x0190 | 133 | #define OMAP4_GPIO_CLEARDATAOUT 0x0190 |
| 161 | #define OMAP4_GPIO_SETDATAOUT 0x0194 | 134 | #define OMAP4_GPIO_SETDATAOUT 0x0194 |
| 162 | /* | ||
| 163 | * omap34xx specific GPIO registers | ||
| 164 | */ | ||
| 165 | |||
| 166 | #define OMAP34XX_GPIO1_BASE 0x48310000 | ||
| 167 | #define OMAP34XX_GPIO2_BASE 0x49050000 | ||
| 168 | #define OMAP34XX_GPIO3_BASE 0x49052000 | ||
| 169 | #define OMAP34XX_GPIO4_BASE 0x49054000 | ||
| 170 | #define OMAP34XX_GPIO5_BASE 0x49056000 | ||
| 171 | #define OMAP34XX_GPIO6_BASE 0x49058000 | ||
| 172 | |||
| 173 | /* | ||
| 174 | * OMAP44XX specific GPIO registers | ||
| 175 | */ | ||
| 176 | #define OMAP44XX_GPIO1_BASE 0x4a310000 | ||
| 177 | #define OMAP44XX_GPIO2_BASE 0x48055000 | ||
| 178 | #define OMAP44XX_GPIO3_BASE 0x48057000 | ||
| 179 | #define OMAP44XX_GPIO4_BASE 0x48059000 | ||
| 180 | #define OMAP44XX_GPIO5_BASE 0x4805B000 | ||
| 181 | #define OMAP44XX_GPIO6_BASE 0x4805D000 | ||
| 182 | 135 | ||
| 183 | struct gpio_bank { | 136 | struct gpio_bank { |
| 184 | unsigned long pbase; | 137 | unsigned long pbase; |
| @@ -190,14 +143,12 @@ struct gpio_bank { | |||
| 190 | u32 suspend_wakeup; | 143 | u32 suspend_wakeup; |
| 191 | u32 saved_wakeup; | 144 | u32 saved_wakeup; |
| 192 | #endif | 145 | #endif |
| 193 | #ifdef CONFIG_ARCH_OMAP2PLUS | ||
| 194 | u32 non_wakeup_gpios; | 146 | u32 non_wakeup_gpios; |
| 195 | u32 enabled_non_wakeup_gpios; | 147 | u32 enabled_non_wakeup_gpios; |
| 196 | 148 | ||
| 197 | u32 saved_datain; | 149 | u32 saved_datain; |
| 198 | u32 saved_fallingdetect; | 150 | u32 saved_fallingdetect; |
| 199 | u32 saved_risingdetect; | 151 | u32 saved_risingdetect; |
| 200 | #endif | ||
| 201 | u32 level_mask; | 152 | u32 level_mask; |
| 202 | u32 toggle_mask; | 153 | u32 toggle_mask; |
| 203 | spinlock_t lock; | 154 | spinlock_t lock; |
| @@ -205,104 +156,13 @@ struct gpio_bank { | |||
| 205 | struct clk *dbck; | 156 | struct clk *dbck; |
| 206 | u32 mod_usage; | 157 | u32 mod_usage; |
| 207 | u32 dbck_enable_mask; | 158 | u32 dbck_enable_mask; |
| 159 | struct device *dev; | ||
| 160 | bool dbck_flag; | ||
| 161 | int stride; | ||
| 208 | }; | 162 | }; |
| 209 | 163 | ||
| 210 | #define METHOD_MPUIO 0 | ||
| 211 | #define METHOD_GPIO_1510 1 | ||
| 212 | #define METHOD_GPIO_1610 2 | ||
| 213 | #define METHOD_GPIO_7XX 3 | ||
| 214 | #define METHOD_GPIO_24XX 5 | ||
| 215 | #define METHOD_GPIO_44XX 6 | ||
| 216 | |||
| 217 | #ifdef CONFIG_ARCH_OMAP16XX | ||
| 218 | static struct gpio_bank gpio_bank_1610[5] = { | ||
| 219 | { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE, | ||
| 220 | METHOD_MPUIO }, | ||
| 221 | { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE, | ||
| 222 | METHOD_GPIO_1610 }, | ||
| 223 | { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, | ||
| 224 | METHOD_GPIO_1610 }, | ||
| 225 | { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, | ||
| 226 | METHOD_GPIO_1610 }, | ||
| 227 | { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, | ||
| 228 | METHOD_GPIO_1610 }, | ||
| 229 | }; | ||
| 230 | #endif | ||
| 231 | |||
| 232 | #ifdef CONFIG_ARCH_OMAP15XX | ||
| 233 | static struct gpio_bank gpio_bank_1510[2] = { | ||
| 234 | { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE, | ||
| 235 | METHOD_MPUIO }, | ||
| 236 | { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE, | ||
| 237 | METHOD_GPIO_1510 } | ||
| 238 | }; | ||
| 239 | #endif | ||
| 240 | |||
| 241 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) | ||
| 242 | static struct gpio_bank gpio_bank_7xx[7] = { | ||
| 243 | { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE, | ||
| 244 | METHOD_MPUIO }, | ||
| 245 | { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE, | ||
| 246 | METHOD_GPIO_7XX }, | ||
| 247 | { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32, | ||
| 248 | METHOD_GPIO_7XX }, | ||
| 249 | { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64, | ||
| 250 | METHOD_GPIO_7XX }, | ||
| 251 | { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96, | ||
| 252 | METHOD_GPIO_7XX }, | ||
| 253 | { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128, | ||
| 254 | METHOD_GPIO_7XX }, | ||
| 255 | { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160, | ||
| 256 | METHOD_GPIO_7XX }, | ||
| 257 | }; | ||
| 258 | #endif | ||
| 259 | |||
| 260 | #ifdef CONFIG_ARCH_OMAP2 | ||
| 261 | |||
| 262 | static struct gpio_bank gpio_bank_242x[4] = { | ||
| 263 | { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, | ||
| 264 | METHOD_GPIO_24XX }, | ||
| 265 | { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, | ||
| 266 | METHOD_GPIO_24XX }, | ||
| 267 | { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, | ||
| 268 | METHOD_GPIO_24XX }, | ||
| 269 | { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, | ||
| 270 | METHOD_GPIO_24XX }, | ||
| 271 | }; | ||
| 272 | |||
| 273 | static struct gpio_bank gpio_bank_243x[5] = { | ||
| 274 | { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, | ||
| 275 | METHOD_GPIO_24XX }, | ||
| 276 | { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, | ||
| 277 | METHOD_GPIO_24XX }, | ||
| 278 | { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, | ||
| 279 | METHOD_GPIO_24XX }, | ||
| 280 | { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, | ||
| 281 | METHOD_GPIO_24XX }, | ||
| 282 | { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, | ||
| 283 | METHOD_GPIO_24XX }, | ||
| 284 | }; | ||
| 285 | |||
| 286 | #endif | ||
| 287 | |||
| 288 | #ifdef CONFIG_ARCH_OMAP3 | 164 | #ifdef CONFIG_ARCH_OMAP3 |
| 289 | static struct gpio_bank gpio_bank_34xx[6] = { | ||
| 290 | { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, | ||
| 291 | METHOD_GPIO_24XX }, | ||
| 292 | { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, | ||
| 293 | METHOD_GPIO_24XX }, | ||
| 294 | { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, | ||
| 295 | METHOD_GPIO_24XX }, | ||
| 296 | { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, | ||
| 297 | METHOD_GPIO_24XX }, | ||
| 298 | { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, | ||
| 299 | METHOD_GPIO_24XX }, | ||
| 300 | { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, | ||
| 301 | METHOD_GPIO_24XX }, | ||
| 302 | }; | ||
| 303 | |||
| 304 | struct omap3_gpio_regs { | 165 | struct omap3_gpio_regs { |
| 305 | u32 sysconfig; | ||
| 306 | u32 irqenable1; | 166 | u32 irqenable1; |
| 307 | u32 irqenable2; | 167 | u32 irqenable2; |
| 308 | u32 wake_en; | 168 | u32 wake_en; |
| @@ -318,26 +178,16 @@ struct omap3_gpio_regs { | |||
| 318 | static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS]; | 178 | static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS]; |
| 319 | #endif | 179 | #endif |
| 320 | 180 | ||
| 321 | #ifdef CONFIG_ARCH_OMAP4 | 181 | /* |
| 322 | static struct gpio_bank gpio_bank_44xx[6] = { | 182 | * TODO: Cleanup gpio_bank usage as it is having information |
| 323 | { OMAP44XX_GPIO1_BASE, NULL, OMAP44XX_IRQ_GPIO1, IH_GPIO_BASE, | 183 | * related to all instances of the device |
| 324 | METHOD_GPIO_44XX }, | 184 | */ |
| 325 | { OMAP44XX_GPIO2_BASE, NULL, OMAP44XX_IRQ_GPIO2, IH_GPIO_BASE + 32, | 185 | static struct gpio_bank *gpio_bank; |
| 326 | METHOD_GPIO_44XX }, | ||
| 327 | { OMAP44XX_GPIO3_BASE, NULL, OMAP44XX_IRQ_GPIO3, IH_GPIO_BASE + 64, | ||
| 328 | METHOD_GPIO_44XX }, | ||
| 329 | { OMAP44XX_GPIO4_BASE, NULL, OMAP44XX_IRQ_GPIO4, IH_GPIO_BASE + 96, | ||
| 330 | METHOD_GPIO_44XX }, | ||
| 331 | { OMAP44XX_GPIO5_BASE, NULL, OMAP44XX_IRQ_GPIO5, IH_GPIO_BASE + 128, | ||
| 332 | METHOD_GPIO_44XX }, | ||
| 333 | { OMAP44XX_GPIO6_BASE, NULL, OMAP44XX_IRQ_GPIO6, IH_GPIO_BASE + 160, | ||
| 334 | METHOD_GPIO_44XX }, | ||
| 335 | }; | ||
| 336 | 186 | ||
| 337 | #endif | 187 | static int bank_width; |
| 338 | 188 | ||
| 339 | static struct gpio_bank *gpio_bank; | 189 | /* TODO: Analyze removing gpio_bank_count usage from driver code */ |
| 340 | static int gpio_bank_count; | 190 | int gpio_bank_count; |
| 341 | 191 | ||
| 342 | static inline struct gpio_bank *get_gpio_bank(int gpio) | 192 | static inline struct gpio_bank *get_gpio_bank(int gpio) |
| 343 | { | 193 | { |
| @@ -417,7 +267,7 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) | |||
| 417 | switch (bank->method) { | 267 | switch (bank->method) { |
| 418 | #ifdef CONFIG_ARCH_OMAP1 | 268 | #ifdef CONFIG_ARCH_OMAP1 |
| 419 | case METHOD_MPUIO: | 269 | case METHOD_MPUIO: |
| 420 | reg += OMAP_MPUIO_IO_CNTL; | 270 | reg += OMAP_MPUIO_IO_CNTL / bank->stride; |
| 421 | break; | 271 | break; |
| 422 | #endif | 272 | #endif |
| 423 | #ifdef CONFIG_ARCH_OMAP15XX | 273 | #ifdef CONFIG_ARCH_OMAP15XX |
| @@ -465,7 +315,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) | |||
| 465 | switch (bank->method) { | 315 | switch (bank->method) { |
| 466 | #ifdef CONFIG_ARCH_OMAP1 | 316 | #ifdef CONFIG_ARCH_OMAP1 |
| 467 | case METHOD_MPUIO: | 317 | case METHOD_MPUIO: |
| 468 | reg += OMAP_MPUIO_OUTPUT; | 318 | reg += OMAP_MPUIO_OUTPUT / bank->stride; |
| 469 | l = __raw_readl(reg); | 319 | l = __raw_readl(reg); |
| 470 | if (enable) | 320 | if (enable) |
| 471 | l |= 1 << gpio; | 321 | l |= 1 << gpio; |
| @@ -537,7 +387,7 @@ static int _get_gpio_datain(struct gpio_bank *bank, int gpio) | |||
| 537 | switch (bank->method) { | 387 | switch (bank->method) { |
| 538 | #ifdef CONFIG_ARCH_OMAP1 | 388 | #ifdef CONFIG_ARCH_OMAP1 |
| 539 | case METHOD_MPUIO: | 389 | case METHOD_MPUIO: |
| 540 | reg += OMAP_MPUIO_INPUT_LATCH; | 390 | reg += OMAP_MPUIO_INPUT_LATCH / bank->stride; |
| 541 | break; | 391 | break; |
| 542 | #endif | 392 | #endif |
| 543 | #ifdef CONFIG_ARCH_OMAP15XX | 393 | #ifdef CONFIG_ARCH_OMAP15XX |
| @@ -583,7 +433,7 @@ static int _get_gpio_dataout(struct gpio_bank *bank, int gpio) | |||
| 583 | switch (bank->method) { | 433 | switch (bank->method) { |
| 584 | #ifdef CONFIG_ARCH_OMAP1 | 434 | #ifdef CONFIG_ARCH_OMAP1 |
| 585 | case METHOD_MPUIO: | 435 | case METHOD_MPUIO: |
| 586 | reg += OMAP_MPUIO_OUTPUT; | 436 | reg += OMAP_MPUIO_OUTPUT / bank->stride; |
| 587 | break; | 437 | break; |
| 588 | #endif | 438 | #endif |
| 589 | #ifdef CONFIG_ARCH_OMAP15XX | 439 | #ifdef CONFIG_ARCH_OMAP15XX |
| @@ -642,6 +492,9 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, | |||
| 642 | u32 val; | 492 | u32 val; |
| 643 | u32 l; | 493 | u32 l; |
| 644 | 494 | ||
| 495 | if (!bank->dbck_flag) | ||
| 496 | return; | ||
| 497 | |||
| 645 | if (debounce < 32) | 498 | if (debounce < 32) |
| 646 | debounce = 0x01; | 499 | debounce = 0x01; |
| 647 | else if (debounce > 7936) | 500 | else if (debounce > 7936) |
| @@ -651,7 +504,7 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, | |||
| 651 | 504 | ||
| 652 | l = 1 << get_gpio_index(gpio); | 505 | l = 1 << get_gpio_index(gpio); |
| 653 | 506 | ||
| 654 | if (cpu_is_omap44xx()) | 507 | if (bank->method == METHOD_GPIO_44XX) |
| 655 | reg += OMAP4_GPIO_DEBOUNCINGTIME; | 508 | reg += OMAP4_GPIO_DEBOUNCINGTIME; |
| 656 | else | 509 | else |
| 657 | reg += OMAP24XX_GPIO_DEBOUNCE_VAL; | 510 | reg += OMAP24XX_GPIO_DEBOUNCE_VAL; |
| @@ -659,7 +512,7 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, | |||
| 659 | __raw_writel(debounce, reg); | 512 | __raw_writel(debounce, reg); |
| 660 | 513 | ||
| 661 | reg = bank->base; | 514 | reg = bank->base; |
| 662 | if (cpu_is_omap44xx()) | 515 | if (bank->method == METHOD_GPIO_44XX) |
| 663 | reg += OMAP4_GPIO_DEBOUNCENABLE; | 516 | reg += OMAP4_GPIO_DEBOUNCENABLE; |
| 664 | else | 517 | else |
| 665 | reg += OMAP24XX_GPIO_DEBOUNCE_EN; | 518 | reg += OMAP24XX_GPIO_DEBOUNCE_EN; |
| @@ -668,12 +521,10 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, | |||
| 668 | 521 | ||
| 669 | if (debounce) { | 522 | if (debounce) { |
| 670 | val |= l; | 523 | val |= l; |
| 671 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) | 524 | clk_enable(bank->dbck); |
| 672 | clk_enable(bank->dbck); | ||
| 673 | } else { | 525 | } else { |
| 674 | val &= ~l; | 526 | val &= ~l; |
| 675 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) | 527 | clk_disable(bank->dbck); |
| 676 | clk_disable(bank->dbck); | ||
| 677 | } | 528 | } |
| 678 | bank->dbck_enable_mask = val; | 529 | bank->dbck_enable_mask = val; |
| 679 | 530 | ||
| @@ -769,7 +620,7 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) | |||
| 769 | 620 | ||
| 770 | switch (bank->method) { | 621 | switch (bank->method) { |
| 771 | case METHOD_MPUIO: | 622 | case METHOD_MPUIO: |
| 772 | reg += OMAP_MPUIO_GPIO_INT_EDGE; | 623 | reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride; |
| 773 | break; | 624 | break; |
| 774 | #ifdef CONFIG_ARCH_OMAP15XX | 625 | #ifdef CONFIG_ARCH_OMAP15XX |
| 775 | case METHOD_GPIO_1510: | 626 | case METHOD_GPIO_1510: |
| @@ -803,7 +654,7 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) | |||
| 803 | switch (bank->method) { | 654 | switch (bank->method) { |
| 804 | #ifdef CONFIG_ARCH_OMAP1 | 655 | #ifdef CONFIG_ARCH_OMAP1 |
| 805 | case METHOD_MPUIO: | 656 | case METHOD_MPUIO: |
| 806 | reg += OMAP_MPUIO_GPIO_INT_EDGE; | 657 | reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride; |
| 807 | l = __raw_readl(reg); | 658 | l = __raw_readl(reg); |
| 808 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) | 659 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
| 809 | bank->toggle_mask |= 1 << gpio; | 660 | bank->toggle_mask |= 1 << gpio; |
| @@ -989,7 +840,7 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) | |||
| 989 | switch (bank->method) { | 840 | switch (bank->method) { |
| 990 | #ifdef CONFIG_ARCH_OMAP1 | 841 | #ifdef CONFIG_ARCH_OMAP1 |
| 991 | case METHOD_MPUIO: | 842 | case METHOD_MPUIO: |
| 992 | reg += OMAP_MPUIO_GPIO_MASKIT; | 843 | reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride; |
| 993 | mask = 0xffff; | 844 | mask = 0xffff; |
| 994 | inv = 1; | 845 | inv = 1; |
| 995 | break; | 846 | break; |
| @@ -1046,7 +897,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab | |||
| 1046 | switch (bank->method) { | 897 | switch (bank->method) { |
| 1047 | #ifdef CONFIG_ARCH_OMAP1 | 898 | #ifdef CONFIG_ARCH_OMAP1 |
| 1048 | case METHOD_MPUIO: | 899 | case METHOD_MPUIO: |
| 1049 | reg += OMAP_MPUIO_GPIO_MASKIT; | 900 | reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride; |
| 1050 | l = __raw_readl(reg); | 901 | l = __raw_readl(reg); |
| 1051 | if (enable) | 902 | if (enable) |
| 1052 | l &= ~(gpio_mask); | 903 | l &= ~(gpio_mask); |
| @@ -1296,7 +1147,8 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
| 1296 | bank = get_irq_data(irq); | 1147 | bank = get_irq_data(irq); |
| 1297 | #ifdef CONFIG_ARCH_OMAP1 | 1148 | #ifdef CONFIG_ARCH_OMAP1 |
| 1298 | if (bank->method == METHOD_MPUIO) | 1149 | if (bank->method == METHOD_MPUIO) |
| 1299 | isr_reg = bank->base + OMAP_MPUIO_GPIO_INT; | 1150 | isr_reg = bank->base + |
| 1151 | OMAP_MPUIO_GPIO_INT / bank->stride; | ||
| 1300 | #endif | 1152 | #endif |
| 1301 | #ifdef CONFIG_ARCH_OMAP15XX | 1153 | #ifdef CONFIG_ARCH_OMAP15XX |
| 1302 | if (bank->method == METHOD_GPIO_1510) | 1154 | if (bank->method == METHOD_GPIO_1510) |
| @@ -1318,6 +1170,10 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
| 1318 | if (bank->method == METHOD_GPIO_44XX) | 1170 | if (bank->method == METHOD_GPIO_44XX) |
| 1319 | isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0; | 1171 | isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0; |
| 1320 | #endif | 1172 | #endif |
| 1173 | |||
| 1174 | if (WARN_ON(!isr_reg)) | ||
| 1175 | goto exit; | ||
| 1176 | |||
| 1321 | while(1) { | 1177 | while(1) { |
| 1322 | u32 isr_saved, level_mask = 0; | 1178 | u32 isr_saved, level_mask = 0; |
| 1323 | u32 enabled; | 1179 | u32 enabled; |
| @@ -1377,6 +1233,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
| 1377 | configured, we must unmask the bank interrupt only after | 1233 | configured, we must unmask the bank interrupt only after |
| 1378 | handler(s) are executed in order to avoid spurious bank | 1234 | handler(s) are executed in order to avoid spurious bank |
| 1379 | interrupt */ | 1235 | interrupt */ |
| 1236 | exit: | ||
| 1380 | if (!unmasked) | 1237 | if (!unmasked) |
| 1381 | desc->chip->unmask(irq); | 1238 | desc->chip->unmask(irq); |
| 1382 | 1239 | ||
| @@ -1489,7 +1346,8 @@ static int omap_mpuio_suspend_noirq(struct device *dev) | |||
| 1489 | { | 1346 | { |
| 1490 | struct platform_device *pdev = to_platform_device(dev); | 1347 | struct platform_device *pdev = to_platform_device(dev); |
| 1491 | struct gpio_bank *bank = platform_get_drvdata(pdev); | 1348 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
| 1492 | void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; | 1349 | void __iomem *mask_reg = bank->base + |
| 1350 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | ||
| 1493 | unsigned long flags; | 1351 | unsigned long flags; |
| 1494 | 1352 | ||
| 1495 | spin_lock_irqsave(&bank->lock, flags); | 1353 | spin_lock_irqsave(&bank->lock, flags); |
| @@ -1504,7 +1362,8 @@ static int omap_mpuio_resume_noirq(struct device *dev) | |||
| 1504 | { | 1362 | { |
| 1505 | struct platform_device *pdev = to_platform_device(dev); | 1363 | struct platform_device *pdev = to_platform_device(dev); |
| 1506 | struct gpio_bank *bank = platform_get_drvdata(pdev); | 1364 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
| 1507 | void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; | 1365 | void __iomem *mask_reg = bank->base + |
| 1366 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | ||
| 1508 | unsigned long flags; | 1367 | unsigned long flags; |
| 1509 | 1368 | ||
| 1510 | spin_lock_irqsave(&bank->lock, flags); | 1369 | spin_lock_irqsave(&bank->lock, flags); |
| @@ -1540,7 +1399,8 @@ static struct platform_device omap_mpuio_device = { | |||
| 1540 | 1399 | ||
| 1541 | static inline void mpuio_init(void) | 1400 | static inline void mpuio_init(void) |
| 1542 | { | 1401 | { |
| 1543 | platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]); | 1402 | struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0)); |
| 1403 | platform_set_drvdata(&omap_mpuio_device, bank); | ||
| 1544 | 1404 | ||
| 1545 | if (platform_driver_register(&omap_mpuio_driver) == 0) | 1405 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
| 1546 | (void) platform_device_register(&omap_mpuio_device); | 1406 | (void) platform_device_register(&omap_mpuio_device); |
| @@ -1583,7 +1443,7 @@ static int gpio_is_input(struct gpio_bank *bank, int mask) | |||
| 1583 | 1443 | ||
| 1584 | switch (bank->method) { | 1444 | switch (bank->method) { |
| 1585 | case METHOD_MPUIO: | 1445 | case METHOD_MPUIO: |
| 1586 | reg += OMAP_MPUIO_IO_CNTL; | 1446 | reg += OMAP_MPUIO_IO_CNTL / bank->stride; |
| 1587 | break; | 1447 | break; |
| 1588 | case METHOD_GPIO_1510: | 1448 | case METHOD_GPIO_1510: |
| 1589 | reg += OMAP1510_GPIO_DIR_CONTROL; | 1449 | reg += OMAP1510_GPIO_DIR_CONTROL; |
| @@ -1645,6 +1505,13 @@ static int gpio_debounce(struct gpio_chip *chip, unsigned offset, | |||
| 1645 | unsigned long flags; | 1505 | unsigned long flags; |
| 1646 | 1506 | ||
| 1647 | bank = container_of(chip, struct gpio_bank, chip); | 1507 | bank = container_of(chip, struct gpio_bank, chip); |
| 1508 | |||
| 1509 | if (!bank->dbck) { | ||
| 1510 | bank->dbck = clk_get(bank->dev, "dbclk"); | ||
| 1511 | if (IS_ERR(bank->dbck)) | ||
| 1512 | dev_err(bank->dev, "Could not get gpio dbck\n"); | ||
| 1513 | } | ||
| 1514 | |||
| 1648 | spin_lock_irqsave(&bank->lock, flags); | 1515 | spin_lock_irqsave(&bank->lock, flags); |
| 1649 | _set_gpio_debounce(bank, offset, debounce); | 1516 | _set_gpio_debounce(bank, offset, debounce); |
| 1650 | spin_unlock_irqrestore(&bank->lock, flags); | 1517 | spin_unlock_irqrestore(&bank->lock, flags); |
| @@ -1673,34 +1540,16 @@ static int gpio_2irq(struct gpio_chip *chip, unsigned offset) | |||
| 1673 | 1540 | ||
| 1674 | /*---------------------------------------------------------------------*/ | 1541 | /*---------------------------------------------------------------------*/ |
| 1675 | 1542 | ||
| 1676 | static int initialized; | 1543 | static void __init omap_gpio_show_rev(struct gpio_bank *bank) |
| 1677 | #if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2) | ||
| 1678 | static struct clk * gpio_ick; | ||
| 1679 | #endif | ||
| 1680 | |||
| 1681 | #if defined(CONFIG_ARCH_OMAP2) | ||
| 1682 | static struct clk * gpio_fck; | ||
| 1683 | #endif | ||
| 1684 | |||
| 1685 | #if defined(CONFIG_ARCH_OMAP2430) | ||
| 1686 | static struct clk * gpio5_ick; | ||
| 1687 | static struct clk * gpio5_fck; | ||
| 1688 | #endif | ||
| 1689 | |||
| 1690 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) | ||
| 1691 | static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS]; | ||
| 1692 | #endif | ||
| 1693 | |||
| 1694 | static void __init omap_gpio_show_rev(void) | ||
| 1695 | { | 1544 | { |
| 1696 | u32 rev; | 1545 | u32 rev; |
| 1697 | 1546 | ||
| 1698 | if (cpu_is_omap16xx()) | 1547 | if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO)) |
| 1699 | rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION); | 1548 | rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION); |
| 1700 | else if (cpu_is_omap24xx() || cpu_is_omap34xx()) | 1549 | else if (cpu_is_omap24xx() || cpu_is_omap34xx()) |
| 1701 | rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); | 1550 | rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION); |
| 1702 | else if (cpu_is_omap44xx()) | 1551 | else if (cpu_is_omap44xx()) |
| 1703 | rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION); | 1552 | rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION); |
| 1704 | else | 1553 | else |
| 1705 | return; | 1554 | return; |
| 1706 | 1555 | ||
| @@ -1713,250 +1562,190 @@ static void __init omap_gpio_show_rev(void) | |||
| 1713 | */ | 1562 | */ |
| 1714 | static struct lock_class_key gpio_lock_class; | 1563 | static struct lock_class_key gpio_lock_class; |
| 1715 | 1564 | ||
| 1716 | static int __init _omap_gpio_init(void) | 1565 | static inline int init_gpio_info(struct platform_device *pdev) |
| 1717 | { | 1566 | { |
| 1718 | int i; | 1567 | /* TODO: Analyze removing gpio_bank_count usage from driver code */ |
| 1719 | int gpio = 0; | 1568 | gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank), |
| 1720 | struct gpio_bank *bank; | 1569 | GFP_KERNEL); |
| 1721 | int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */ | 1570 | if (!gpio_bank) { |
| 1722 | char clk_name[11]; | 1571 | dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n"); |
| 1723 | 1572 | return -ENOMEM; | |
| 1724 | initialized = 1; | ||
| 1725 | |||
| 1726 | #if defined(CONFIG_ARCH_OMAP1) | ||
| 1727 | if (cpu_is_omap15xx()) { | ||
| 1728 | gpio_ick = clk_get(NULL, "arm_gpio_ck"); | ||
| 1729 | if (IS_ERR(gpio_ick)) | ||
| 1730 | printk("Could not get arm_gpio_ck\n"); | ||
| 1731 | else | ||
| 1732 | clk_enable(gpio_ick); | ||
| 1733 | } | 1573 | } |
| 1734 | #endif | 1574 | return 0; |
| 1735 | #if defined(CONFIG_ARCH_OMAP2) | 1575 | } |
| 1736 | if (cpu_class_is_omap2()) { | ||
| 1737 | gpio_ick = clk_get(NULL, "gpios_ick"); | ||
| 1738 | if (IS_ERR(gpio_ick)) | ||
| 1739 | printk("Could not get gpios_ick\n"); | ||
| 1740 | else | ||
| 1741 | clk_enable(gpio_ick); | ||
| 1742 | gpio_fck = clk_get(NULL, "gpios_fck"); | ||
| 1743 | if (IS_ERR(gpio_fck)) | ||
| 1744 | printk("Could not get gpios_fck\n"); | ||
| 1745 | else | ||
| 1746 | clk_enable(gpio_fck); | ||
| 1747 | 1576 | ||
| 1748 | /* | 1577 | /* TODO: Cleanup cpu_is_* checks */ |
| 1749 | * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK | 1578 | static void omap_gpio_mod_init(struct gpio_bank *bank, int id) |
| 1750 | */ | 1579 | { |
| 1751 | #if defined(CONFIG_ARCH_OMAP2430) | 1580 | if (cpu_class_is_omap2()) { |
| 1752 | if (cpu_is_omap2430()) { | 1581 | if (cpu_is_omap44xx()) { |
| 1753 | gpio5_ick = clk_get(NULL, "gpio5_ick"); | 1582 | __raw_writel(0xffffffff, bank->base + |
| 1754 | if (IS_ERR(gpio5_ick)) | 1583 | OMAP4_GPIO_IRQSTATUSCLR0); |
| 1755 | printk("Could not get gpio5_ick\n"); | 1584 | __raw_writel(0x00000000, bank->base + |
| 1756 | else | 1585 | OMAP4_GPIO_DEBOUNCENABLE); |
| 1757 | clk_enable(gpio5_ick); | 1586 | /* Initialize interface clk ungated, module enabled */ |
| 1758 | gpio5_fck = clk_get(NULL, "gpio5_fck"); | 1587 | __raw_writel(0, bank->base + OMAP4_GPIO_CTRL); |
| 1759 | if (IS_ERR(gpio5_fck)) | 1588 | } else if (cpu_is_omap34xx()) { |
| 1760 | printk("Could not get gpio5_fck\n"); | 1589 | __raw_writel(0x00000000, bank->base + |
| 1761 | else | 1590 | OMAP24XX_GPIO_IRQENABLE1); |
| 1762 | clk_enable(gpio5_fck); | 1591 | __raw_writel(0xffffffff, bank->base + |
| 1592 | OMAP24XX_GPIO_IRQSTATUS1); | ||
| 1593 | __raw_writel(0x00000000, bank->base + | ||
| 1594 | OMAP24XX_GPIO_DEBOUNCE_EN); | ||
| 1595 | |||
| 1596 | /* Initialize interface clk ungated, module enabled */ | ||
| 1597 | __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL); | ||
| 1598 | } else if (cpu_is_omap24xx()) { | ||
| 1599 | static const u32 non_wakeup_gpios[] = { | ||
| 1600 | 0xe203ffc0, 0x08700040 | ||
| 1601 | }; | ||
| 1602 | if (id < ARRAY_SIZE(non_wakeup_gpios)) | ||
| 1603 | bank->non_wakeup_gpios = non_wakeup_gpios[id]; | ||
| 1763 | } | 1604 | } |
| 1764 | #endif | 1605 | } else if (cpu_class_is_omap1()) { |
| 1765 | } | 1606 | if (bank_is_mpuio(bank)) |
| 1766 | #endif | 1607 | __raw_writew(0xffff, bank->base + |
| 1608 | OMAP_MPUIO_GPIO_MASKIT / bank->stride); | ||
| 1609 | if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { | ||
| 1610 | __raw_writew(0xffff, bank->base | ||
| 1611 | + OMAP1510_GPIO_INT_MASK); | ||
| 1612 | __raw_writew(0x0000, bank->base | ||
| 1613 | + OMAP1510_GPIO_INT_STATUS); | ||
| 1614 | } | ||
| 1615 | if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) { | ||
| 1616 | __raw_writew(0x0000, bank->base | ||
| 1617 | + OMAP1610_GPIO_IRQENABLE1); | ||
| 1618 | __raw_writew(0xffff, bank->base | ||
| 1619 | + OMAP1610_GPIO_IRQSTATUS1); | ||
| 1620 | __raw_writew(0x0014, bank->base | ||
| 1621 | + OMAP1610_GPIO_SYSCONFIG); | ||
| 1767 | 1622 | ||
| 1768 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) | 1623 | /* |
| 1769 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) { | 1624 | * Enable system clock for GPIO module. |
| 1770 | for (i = 0; i < OMAP34XX_NR_GPIOS; i++) { | 1625 | * The CAM_CLK_CTRL *is* really the right place. |
| 1771 | sprintf(clk_name, "gpio%d_ick", i + 1); | 1626 | */ |
| 1772 | gpio_iclks[i] = clk_get(NULL, clk_name); | 1627 | omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, |
| 1773 | if (IS_ERR(gpio_iclks[i])) | 1628 | ULPD_CAM_CLK_CTRL); |
| 1774 | printk(KERN_ERR "Could not get %s\n", clk_name); | 1629 | } |
| 1775 | else | 1630 | if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) { |
| 1776 | clk_enable(gpio_iclks[i]); | 1631 | __raw_writel(0xffffffff, bank->base |
| 1632 | + OMAP7XX_GPIO_INT_MASK); | ||
| 1633 | __raw_writel(0x00000000, bank->base | ||
| 1634 | + OMAP7XX_GPIO_INT_STATUS); | ||
| 1777 | } | 1635 | } |
| 1778 | } | 1636 | } |
| 1779 | #endif | 1637 | } |
| 1780 | 1638 | ||
| 1639 | static void __init omap_gpio_chip_init(struct gpio_bank *bank) | ||
| 1640 | { | ||
| 1641 | int j; | ||
| 1642 | static int gpio; | ||
| 1781 | 1643 | ||
| 1782 | #ifdef CONFIG_ARCH_OMAP15XX | 1644 | bank->mod_usage = 0; |
| 1783 | if (cpu_is_omap15xx()) { | 1645 | /* |
| 1784 | gpio_bank_count = 2; | 1646 | * REVISIT eventually switch from OMAP-specific gpio structs |
| 1785 | gpio_bank = gpio_bank_1510; | 1647 | * over to the generic ones |
| 1786 | bank_size = SZ_2K; | 1648 | */ |
| 1787 | } | 1649 | bank->chip.request = omap_gpio_request; |
| 1788 | #endif | 1650 | bank->chip.free = omap_gpio_free; |
| 1789 | #if defined(CONFIG_ARCH_OMAP16XX) | 1651 | bank->chip.direction_input = gpio_input; |
| 1790 | if (cpu_is_omap16xx()) { | 1652 | bank->chip.get = gpio_get; |
| 1791 | gpio_bank_count = 5; | 1653 | bank->chip.direction_output = gpio_output; |
| 1792 | gpio_bank = gpio_bank_1610; | 1654 | bank->chip.set_debounce = gpio_debounce; |
| 1793 | bank_size = SZ_2K; | 1655 | bank->chip.set = gpio_set; |
| 1794 | } | 1656 | bank->chip.to_irq = gpio_2irq; |
| 1795 | #endif | 1657 | if (bank_is_mpuio(bank)) { |
| 1796 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) | 1658 | bank->chip.label = "mpuio"; |
| 1797 | if (cpu_is_omap7xx()) { | 1659 | #ifdef CONFIG_ARCH_OMAP16XX |
| 1798 | gpio_bank_count = 7; | 1660 | bank->chip.dev = &omap_mpuio_device.dev; |
| 1799 | gpio_bank = gpio_bank_7xx; | ||
| 1800 | bank_size = SZ_2K; | ||
| 1801 | } | ||
| 1802 | #endif | ||
| 1803 | #ifdef CONFIG_ARCH_OMAP2 | ||
| 1804 | if (cpu_is_omap242x()) { | ||
| 1805 | gpio_bank_count = 4; | ||
| 1806 | gpio_bank = gpio_bank_242x; | ||
| 1807 | } | ||
| 1808 | if (cpu_is_omap243x()) { | ||
| 1809 | gpio_bank_count = 5; | ||
| 1810 | gpio_bank = gpio_bank_243x; | ||
| 1811 | } | ||
| 1812 | #endif | 1661 | #endif |
| 1813 | #ifdef CONFIG_ARCH_OMAP3 | 1662 | bank->chip.base = OMAP_MPUIO(0); |
| 1814 | if (cpu_is_omap34xx()) { | 1663 | } else { |
| 1815 | gpio_bank_count = OMAP34XX_NR_GPIOS; | 1664 | bank->chip.label = "gpio"; |
| 1816 | gpio_bank = gpio_bank_34xx; | 1665 | bank->chip.base = gpio; |
| 1666 | gpio += bank_width; | ||
| 1817 | } | 1667 | } |
| 1818 | #endif | 1668 | bank->chip.ngpio = bank_width; |
| 1819 | #ifdef CONFIG_ARCH_OMAP4 | 1669 | |
| 1820 | if (cpu_is_omap44xx()) { | 1670 | gpiochip_add(&bank->chip); |
| 1821 | gpio_bank_count = OMAP34XX_NR_GPIOS; | 1671 | |
| 1822 | gpio_bank = gpio_bank_44xx; | 1672 | for (j = bank->virtual_irq_start; |
| 1673 | j < bank->virtual_irq_start + bank_width; j++) { | ||
| 1674 | lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class); | ||
| 1675 | set_irq_chip_data(j, bank); | ||
| 1676 | if (bank_is_mpuio(bank)) | ||
| 1677 | set_irq_chip(j, &mpuio_irq_chip); | ||
| 1678 | else | ||
| 1679 | set_irq_chip(j, &gpio_irq_chip); | ||
| 1680 | set_irq_handler(j, handle_simple_irq); | ||
| 1681 | set_irq_flags(j, IRQF_VALID); | ||
| 1823 | } | 1682 | } |
| 1824 | #endif | 1683 | set_irq_chained_handler(bank->irq, gpio_irq_handler); |
| 1825 | for (i = 0; i < gpio_bank_count; i++) { | 1684 | set_irq_data(bank->irq, bank); |
| 1826 | int j, gpio_count = 16; | 1685 | } |
| 1686 | |||
| 1687 | static int __devinit omap_gpio_probe(struct platform_device *pdev) | ||
| 1688 | { | ||
| 1689 | static int gpio_init_done; | ||
| 1690 | struct omap_gpio_platform_data *pdata; | ||
| 1691 | struct resource *res; | ||
| 1692 | int id; | ||
| 1693 | struct gpio_bank *bank; | ||
| 1827 | 1694 | ||
| 1828 | bank = &gpio_bank[i]; | 1695 | if (!pdev->dev.platform_data) |
| 1829 | spin_lock_init(&bank->lock); | 1696 | return -EINVAL; |
| 1830 | 1697 | ||
| 1831 | /* Static mapping, never released */ | 1698 | pdata = pdev->dev.platform_data; |
| 1832 | bank->base = ioremap(bank->pbase, bank_size); | ||
| 1833 | if (!bank->base) { | ||
| 1834 | printk(KERN_ERR "Could not ioremap gpio bank%i\n", i); | ||
| 1835 | continue; | ||
| 1836 | } | ||
| 1837 | 1699 | ||
| 1838 | if (bank_is_mpuio(bank)) | 1700 | if (!gpio_init_done) { |
| 1839 | __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT); | 1701 | int ret; |
| 1840 | if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { | ||
| 1841 | __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK); | ||
| 1842 | __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS); | ||
| 1843 | } | ||
| 1844 | if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) { | ||
| 1845 | __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1); | ||
| 1846 | __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); | ||
| 1847 | __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG); | ||
| 1848 | } | ||
| 1849 | if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) { | ||
| 1850 | __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK); | ||
| 1851 | __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS); | ||
| 1852 | 1702 | ||
| 1853 | gpio_count = 32; /* 7xx has 32-bit GPIOs */ | 1703 | ret = init_gpio_info(pdev); |
| 1854 | } | 1704 | if (ret) |
| 1705 | return ret; | ||
| 1706 | } | ||
| 1855 | 1707 | ||
| 1856 | #ifdef CONFIG_ARCH_OMAP2PLUS | 1708 | id = pdev->id; |
| 1857 | if ((bank->method == METHOD_GPIO_24XX) || | 1709 | bank = &gpio_bank[id]; |
| 1858 | (bank->method == METHOD_GPIO_44XX)) { | ||
| 1859 | static const u32 non_wakeup_gpios[] = { | ||
| 1860 | 0xe203ffc0, 0x08700040 | ||
| 1861 | }; | ||
| 1862 | 1710 | ||
| 1863 | if (cpu_is_omap44xx()) { | 1711 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
| 1864 | __raw_writel(0xffffffff, bank->base + | 1712 | if (unlikely(!res)) { |
| 1865 | OMAP4_GPIO_IRQSTATUSCLR0); | 1713 | dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id); |
| 1866 | __raw_writew(0x0015, bank->base + | 1714 | return -ENODEV; |
| 1867 | OMAP4_GPIO_SYSCONFIG); | 1715 | } |
| 1868 | __raw_writel(0x00000000, bank->base + | ||
| 1869 | OMAP4_GPIO_DEBOUNCENABLE); | ||
| 1870 | /* | ||
| 1871 | * Initialize interface clock ungated, | ||
| 1872 | * module enabled | ||
| 1873 | */ | ||
| 1874 | __raw_writel(0, bank->base + OMAP4_GPIO_CTRL); | ||
| 1875 | } else { | ||
| 1876 | __raw_writel(0x00000000, bank->base + | ||
| 1877 | OMAP24XX_GPIO_IRQENABLE1); | ||
| 1878 | __raw_writel(0xffffffff, bank->base + | ||
| 1879 | OMAP24XX_GPIO_IRQSTATUS1); | ||
| 1880 | __raw_writew(0x0015, bank->base + | ||
| 1881 | OMAP24XX_GPIO_SYSCONFIG); | ||
| 1882 | __raw_writel(0x00000000, bank->base + | ||
| 1883 | OMAP24XX_GPIO_DEBOUNCE_EN); | ||
| 1884 | |||
| 1885 | /* | ||
| 1886 | * Initialize interface clock ungated, | ||
| 1887 | * module enabled | ||
| 1888 | */ | ||
| 1889 | __raw_writel(0, bank->base + | ||
| 1890 | OMAP24XX_GPIO_CTRL); | ||
| 1891 | } | ||
| 1892 | if (cpu_is_omap24xx() && | ||
| 1893 | i < ARRAY_SIZE(non_wakeup_gpios)) | ||
| 1894 | bank->non_wakeup_gpios = non_wakeup_gpios[i]; | ||
| 1895 | gpio_count = 32; | ||
| 1896 | } | ||
| 1897 | #endif | ||
| 1898 | 1716 | ||
| 1899 | bank->mod_usage = 0; | 1717 | bank->irq = res->start; |
| 1900 | /* REVISIT eventually switch from OMAP-specific gpio structs | 1718 | bank->virtual_irq_start = pdata->virtual_irq_start; |
| 1901 | * over to the generic ones | 1719 | bank->method = pdata->bank_type; |
| 1902 | */ | 1720 | bank->dev = &pdev->dev; |
| 1903 | bank->chip.request = omap_gpio_request; | 1721 | bank->dbck_flag = pdata->dbck_flag; |
| 1904 | bank->chip.free = omap_gpio_free; | 1722 | bank->stride = pdata->bank_stride; |
| 1905 | bank->chip.direction_input = gpio_input; | 1723 | bank_width = pdata->bank_width; |
| 1906 | bank->chip.get = gpio_get; | ||
| 1907 | bank->chip.direction_output = gpio_output; | ||
| 1908 | bank->chip.set_debounce = gpio_debounce; | ||
| 1909 | bank->chip.set = gpio_set; | ||
| 1910 | bank->chip.to_irq = gpio_2irq; | ||
| 1911 | if (bank_is_mpuio(bank)) { | ||
| 1912 | bank->chip.label = "mpuio"; | ||
| 1913 | #ifdef CONFIG_ARCH_OMAP16XX | ||
| 1914 | bank->chip.dev = &omap_mpuio_device.dev; | ||
| 1915 | #endif | ||
| 1916 | bank->chip.base = OMAP_MPUIO(0); | ||
| 1917 | } else { | ||
| 1918 | bank->chip.label = "gpio"; | ||
| 1919 | bank->chip.base = gpio; | ||
| 1920 | gpio += gpio_count; | ||
| 1921 | } | ||
| 1922 | bank->chip.ngpio = gpio_count; | ||
| 1923 | 1724 | ||
| 1924 | gpiochip_add(&bank->chip); | 1725 | spin_lock_init(&bank->lock); |
| 1925 | 1726 | ||
| 1926 | for (j = bank->virtual_irq_start; | 1727 | /* Static mapping, never released */ |
| 1927 | j < bank->virtual_irq_start + gpio_count; j++) { | 1728 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1928 | lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class); | 1729 | if (unlikely(!res)) { |
| 1929 | set_irq_chip_data(j, bank); | 1730 | dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id); |
| 1930 | if (bank_is_mpuio(bank)) | 1731 | return -ENODEV; |
| 1931 | set_irq_chip(j, &mpuio_irq_chip); | ||
| 1932 | else | ||
| 1933 | set_irq_chip(j, &gpio_irq_chip); | ||
| 1934 | set_irq_handler(j, handle_simple_irq); | ||
| 1935 | set_irq_flags(j, IRQF_VALID); | ||
| 1936 | } | ||
| 1937 | set_irq_chained_handler(bank->irq, gpio_irq_handler); | ||
| 1938 | set_irq_data(bank->irq, bank); | ||
| 1939 | |||
| 1940 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) { | ||
| 1941 | sprintf(clk_name, "gpio%d_dbck", i + 1); | ||
| 1942 | bank->dbck = clk_get(NULL, clk_name); | ||
| 1943 | if (IS_ERR(bank->dbck)) | ||
| 1944 | printk(KERN_ERR "Could not get %s\n", clk_name); | ||
| 1945 | } | ||
| 1946 | } | 1732 | } |
| 1947 | 1733 | ||
| 1948 | /* Enable system clock for GPIO module. | 1734 | bank->base = ioremap(res->start, resource_size(res)); |
| 1949 | * The CAM_CLK_CTRL *is* really the right place. */ | 1735 | if (!bank->base) { |
| 1950 | if (cpu_is_omap16xx()) | 1736 | dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id); |
| 1951 | omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL); | 1737 | return -ENOMEM; |
| 1738 | } | ||
| 1952 | 1739 | ||
| 1953 | /* Enable autoidle for the OCP interface */ | 1740 | pm_runtime_enable(bank->dev); |
| 1954 | if (cpu_is_omap24xx()) | 1741 | pm_runtime_get_sync(bank->dev); |
| 1955 | omap_writel(1 << 0, 0x48019010); | 1742 | |
| 1956 | if (cpu_is_omap34xx()) | 1743 | omap_gpio_mod_init(bank, id); |
| 1957 | omap_writel(1 << 0, 0x48306814); | 1744 | omap_gpio_chip_init(bank); |
| 1745 | omap_gpio_show_rev(bank); | ||
| 1958 | 1746 | ||
| 1959 | omap_gpio_show_rev(); | 1747 | if (!gpio_init_done) |
| 1748 | gpio_init_done = 1; | ||
| 1960 | 1749 | ||
| 1961 | return 0; | 1750 | return 0; |
| 1962 | } | 1751 | } |
| @@ -2074,7 +1863,7 @@ static struct sys_device omap_gpio_device = { | |||
| 2074 | 1863 | ||
| 2075 | static int workaround_enabled; | 1864 | static int workaround_enabled; |
| 2076 | 1865 | ||
| 2077 | void omap2_gpio_prepare_for_idle(int power_state) | 1866 | void omap2_gpio_prepare_for_idle(int off_mode) |
| 2078 | { | 1867 | { |
| 2079 | int i, c = 0; | 1868 | int i, c = 0; |
| 2080 | int min = 0; | 1869 | int min = 0; |
| @@ -2090,7 +1879,7 @@ void omap2_gpio_prepare_for_idle(int power_state) | |||
| 2090 | for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) | 1879 | for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) |
| 2091 | clk_disable(bank->dbck); | 1880 | clk_disable(bank->dbck); |
| 2092 | 1881 | ||
| 2093 | if (power_state > PWRDM_POWER_OFF) | 1882 | if (!off_mode) |
| 2094 | continue; | 1883 | continue; |
| 2095 | 1884 | ||
| 2096 | /* If going to OFF, remove triggering for all | 1885 | /* If going to OFF, remove triggering for all |
| @@ -2251,8 +2040,6 @@ void omap_gpio_save_context(void) | |||
| 2251 | /* saving banks from 2-6 only since GPIO1 is in WKUP */ | 2040 | /* saving banks from 2-6 only since GPIO1 is in WKUP */ |
| 2252 | for (i = 1; i < gpio_bank_count; i++) { | 2041 | for (i = 1; i < gpio_bank_count; i++) { |
| 2253 | struct gpio_bank *bank = &gpio_bank[i]; | 2042 | struct gpio_bank *bank = &gpio_bank[i]; |
| 2254 | gpio_context[i].sysconfig = | ||
| 2255 | __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG); | ||
| 2256 | gpio_context[i].irqenable1 = | 2043 | gpio_context[i].irqenable1 = |
| 2257 | __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1); | 2044 | __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1); |
| 2258 | gpio_context[i].irqenable2 = | 2045 | gpio_context[i].irqenable2 = |
| @@ -2283,8 +2070,6 @@ void omap_gpio_restore_context(void) | |||
| 2283 | 2070 | ||
| 2284 | for (i = 1; i < gpio_bank_count; i++) { | 2071 | for (i = 1; i < gpio_bank_count; i++) { |
| 2285 | struct gpio_bank *bank = &gpio_bank[i]; | 2072 | struct gpio_bank *bank = &gpio_bank[i]; |
| 2286 | __raw_writel(gpio_context[i].sysconfig, | ||
| 2287 | bank->base + OMAP24XX_GPIO_SYSCONFIG); | ||
| 2288 | __raw_writel(gpio_context[i].irqenable1, | 2073 | __raw_writel(gpio_context[i].irqenable1, |
| 2289 | bank->base + OMAP24XX_GPIO_IRQENABLE1); | 2074 | bank->base + OMAP24XX_GPIO_IRQENABLE1); |
| 2290 | __raw_writel(gpio_context[i].irqenable2, | 2075 | __raw_writel(gpio_context[i].irqenable2, |
| @@ -2309,25 +2094,28 @@ void omap_gpio_restore_context(void) | |||
| 2309 | } | 2094 | } |
| 2310 | #endif | 2095 | #endif |
| 2311 | 2096 | ||
| 2097 | static struct platform_driver omap_gpio_driver = { | ||
| 2098 | .probe = omap_gpio_probe, | ||
| 2099 | .driver = { | ||
| 2100 | .name = "omap_gpio", | ||
| 2101 | }, | ||
| 2102 | }; | ||
| 2103 | |||
| 2312 | /* | 2104 | /* |
| 2313 | * This may get called early from board specific init | 2105 | * gpio driver register needs to be done before |
| 2314 | * for boards that have interrupts routed via FPGA. | 2106 | * machine_init functions access gpio APIs. |
| 2107 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | ||
| 2315 | */ | 2108 | */ |
| 2316 | int __init omap_gpio_init(void) | 2109 | static int __init omap_gpio_drv_reg(void) |
| 2317 | { | 2110 | { |
| 2318 | if (!initialized) | 2111 | return platform_driver_register(&omap_gpio_driver); |
| 2319 | return _omap_gpio_init(); | ||
| 2320 | else | ||
| 2321 | return 0; | ||
| 2322 | } | 2112 | } |
| 2113 | postcore_initcall(omap_gpio_drv_reg); | ||
| 2323 | 2114 | ||
| 2324 | static int __init omap_gpio_sysinit(void) | 2115 | static int __init omap_gpio_sysinit(void) |
| 2325 | { | 2116 | { |
| 2326 | int ret = 0; | 2117 | int ret = 0; |
| 2327 | 2118 | ||
| 2328 | if (!initialized) | ||
| 2329 | ret = _omap_gpio_init(); | ||
| 2330 | |||
| 2331 | mpuio_init(); | 2119 | mpuio_init(); |
| 2332 | 2120 | ||
| 2333 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) | 2121 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c index a5ce4f0aad35..a4f8003de664 100644 --- a/arch/arm/plat-omap/i2c.c +++ b/arch/arm/plat-omap/i2c.c | |||
| @@ -27,20 +27,20 @@ | |||
| 27 | #include <linux/platform_device.h> | 27 | #include <linux/platform_device.h> |
| 28 | #include <linux/i2c.h> | 28 | #include <linux/i2c.h> |
| 29 | #include <linux/i2c-omap.h> | 29 | #include <linux/i2c-omap.h> |
| 30 | #include <linux/slab.h> | ||
| 31 | #include <linux/err.h> | ||
| 32 | #include <linux/clk.h> | ||
| 30 | 33 | ||
| 31 | #include <mach/irqs.h> | 34 | #include <mach/irqs.h> |
| 32 | #include <plat/mux.h> | 35 | #include <plat/mux.h> |
| 33 | #include <plat/i2c.h> | 36 | #include <plat/i2c.h> |
| 34 | #include <plat/omap-pm.h> | 37 | #include <plat/omap-pm.h> |
| 38 | #include <plat/omap_device.h> | ||
| 35 | 39 | ||
| 36 | #define OMAP_I2C_SIZE 0x3f | 40 | #define OMAP_I2C_SIZE 0x3f |
| 37 | #define OMAP1_I2C_BASE 0xfffb3800 | 41 | #define OMAP1_I2C_BASE 0xfffb3800 |
| 38 | #define OMAP2_I2C_BASE1 0x48070000 | ||
| 39 | #define OMAP2_I2C_BASE2 0x48072000 | ||
| 40 | #define OMAP2_I2C_BASE3 0x48060000 | ||
| 41 | #define OMAP4_I2C_BASE4 0x48350000 | ||
| 42 | 42 | ||
| 43 | static const char name[] = "i2c_omap"; | 43 | static const char name[] = "omap_i2c"; |
| 44 | 44 | ||
| 45 | #define I2C_RESOURCE_BUILDER(base, irq) \ | 45 | #define I2C_RESOURCE_BUILDER(base, irq) \ |
| 46 | { \ | 46 | { \ |
| @@ -55,15 +55,6 @@ static const char name[] = "i2c_omap"; | |||
| 55 | 55 | ||
| 56 | static struct resource i2c_resources[][2] = { | 56 | static struct resource i2c_resources[][2] = { |
| 57 | { I2C_RESOURCE_BUILDER(0, 0) }, | 57 | { I2C_RESOURCE_BUILDER(0, 0) }, |
| 58 | #if defined(CONFIG_ARCH_OMAP2PLUS) | ||
| 59 | { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE2, 0) }, | ||
| 60 | #endif | ||
| 61 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) | ||
| 62 | { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE3, 0) }, | ||
| 63 | #endif | ||
| 64 | #if defined(CONFIG_ARCH_OMAP4) | ||
| 65 | { I2C_RESOURCE_BUILDER(OMAP4_I2C_BASE4, 0) }, | ||
| 66 | #endif | ||
| 67 | }; | 58 | }; |
| 68 | 59 | ||
| 69 | #define I2C_DEV_BUILDER(bus_id, res, data) \ | 60 | #define I2C_DEV_BUILDER(bus_id, res, data) \ |
| @@ -77,18 +68,11 @@ static struct resource i2c_resources[][2] = { | |||
| 77 | }, \ | 68 | }, \ |
| 78 | } | 69 | } |
| 79 | 70 | ||
| 80 | static struct omap_i2c_bus_platform_data i2c_pdata[ARRAY_SIZE(i2c_resources)]; | 71 | #define MAX_OMAP_I2C_HWMOD_NAME_LEN 16 |
| 72 | #define OMAP_I2C_MAX_CONTROLLERS 4 | ||
| 73 | static struct omap_i2c_bus_platform_data i2c_pdata[OMAP_I2C_MAX_CONTROLLERS]; | ||
| 81 | static struct platform_device omap_i2c_devices[] = { | 74 | static struct platform_device omap_i2c_devices[] = { |
| 82 | I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_pdata[0]), | 75 | I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_pdata[0]), |
| 83 | #if defined(CONFIG_ARCH_OMAP2PLUS) | ||
| 84 | I2C_DEV_BUILDER(2, i2c_resources[1], &i2c_pdata[1]), | ||
| 85 | #endif | ||
| 86 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) | ||
| 87 | I2C_DEV_BUILDER(3, i2c_resources[2], &i2c_pdata[2]), | ||
| 88 | #endif | ||
| 89 | #if defined(CONFIG_ARCH_OMAP4) | ||
| 90 | I2C_DEV_BUILDER(4, i2c_resources[3], &i2c_pdata[3]), | ||
| 91 | #endif | ||
| 92 | }; | 76 | }; |
| 93 | 77 | ||
| 94 | #define OMAP_I2C_CMDLINE_SETUP (BIT(31)) | 78 | #define OMAP_I2C_CMDLINE_SETUP (BIT(31)) |
| @@ -109,35 +93,25 @@ static int __init omap_i2c_nr_ports(void) | |||
| 109 | return ports; | 93 | return ports; |
| 110 | } | 94 | } |
| 111 | 95 | ||
| 112 | /* Shared between omap2 and 3 */ | 96 | static inline int omap1_i2c_add_bus(int bus_id) |
| 113 | static resource_size_t omap2_i2c_irq[3] __initdata = { | ||
| 114 | INT_24XX_I2C1_IRQ, | ||
| 115 | INT_24XX_I2C2_IRQ, | ||
| 116 | INT_34XX_I2C3_IRQ, | ||
| 117 | }; | ||
| 118 | |||
| 119 | static resource_size_t omap4_i2c_irq[4] __initdata = { | ||
| 120 | OMAP44XX_IRQ_I2C1, | ||
| 121 | OMAP44XX_IRQ_I2C2, | ||
| 122 | OMAP44XX_IRQ_I2C3, | ||
| 123 | OMAP44XX_IRQ_I2C4, | ||
| 124 | }; | ||
| 125 | |||
| 126 | static inline int omap1_i2c_add_bus(struct platform_device *pdev, int bus_id) | ||
| 127 | { | 97 | { |
| 128 | struct omap_i2c_bus_platform_data *pd; | 98 | struct platform_device *pdev; |
| 99 | struct omap_i2c_bus_platform_data *pdata; | ||
| 129 | struct resource *res; | 100 | struct resource *res; |
| 130 | 101 | ||
| 131 | pd = pdev->dev.platform_data; | 102 | omap1_i2c_mux_pins(bus_id); |
| 103 | |||
| 104 | pdev = &omap_i2c_devices[bus_id - 1]; | ||
| 132 | res = pdev->resource; | 105 | res = pdev->resource; |
| 133 | res[0].start = OMAP1_I2C_BASE; | 106 | res[0].start = OMAP1_I2C_BASE; |
| 134 | res[0].end = res[0].start + OMAP_I2C_SIZE; | 107 | res[0].end = res[0].start + OMAP_I2C_SIZE; |
| 135 | res[1].start = INT_I2C; | 108 | res[1].start = INT_I2C; |
| 136 | omap1_i2c_mux_pins(bus_id); | 109 | pdata = &i2c_pdata[bus_id - 1]; |
| 137 | 110 | ||
| 138 | return platform_device_register(pdev); | 111 | return platform_device_register(pdev); |
| 139 | } | 112 | } |
| 140 | 113 | ||
| 114 | |||
| 141 | /* | 115 | /* |
| 142 | * XXX This function is a temporary compatibility wrapper - only | 116 | * XXX This function is a temporary compatibility wrapper - only |
| 143 | * needed until the I2C driver can be converted to call | 117 | * needed until the I2C driver can be converted to call |
| @@ -148,52 +122,64 @@ static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t) | |||
| 148 | omap_pm_set_max_mpu_wakeup_lat(dev, t); | 122 | omap_pm_set_max_mpu_wakeup_lat(dev, t); |
| 149 | } | 123 | } |
| 150 | 124 | ||
| 151 | static inline int omap2_i2c_add_bus(struct platform_device *pdev, int bus_id) | 125 | static struct omap_device_pm_latency omap_i2c_latency[] = { |
| 152 | { | 126 | [0] = { |
| 153 | struct resource *res; | 127 | .deactivate_func = omap_device_idle_hwmods, |
| 154 | resource_size_t *irq; | 128 | .activate_func = omap_device_enable_hwmods, |
| 129 | .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, | ||
| 130 | }, | ||
| 131 | }; | ||
| 155 | 132 | ||
| 156 | res = pdev->resource; | 133 | #ifdef CONFIG_ARCH_OMAP2PLUS |
| 134 | static inline int omap2_i2c_add_bus(int bus_id) | ||
| 135 | { | ||
| 136 | int l; | ||
| 137 | struct omap_hwmod *oh; | ||
| 138 | struct omap_device *od; | ||
| 139 | char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN]; | ||
| 140 | struct omap_i2c_bus_platform_data *pdata; | ||
| 157 | 141 | ||
| 158 | if (!cpu_is_omap44xx()) | 142 | omap2_i2c_mux_pins(bus_id); |
| 159 | irq = omap2_i2c_irq; | ||
| 160 | else | ||
| 161 | irq = omap4_i2c_irq; | ||
| 162 | 143 | ||
| 163 | if (bus_id == 1) { | 144 | l = snprintf(oh_name, MAX_OMAP_I2C_HWMOD_NAME_LEN, "i2c%d", bus_id); |
| 164 | res[0].start = OMAP2_I2C_BASE1; | 145 | WARN(l >= MAX_OMAP_I2C_HWMOD_NAME_LEN, |
| 165 | res[0].end = res[0].start + OMAP_I2C_SIZE; | 146 | "String buffer overflow in I2C%d device setup\n", bus_id); |
| 147 | oh = omap_hwmod_lookup(oh_name); | ||
| 148 | if (!oh) { | ||
| 149 | pr_err("Could not look up %s\n", oh_name); | ||
| 150 | return -EEXIST; | ||
| 166 | } | 151 | } |
| 167 | 152 | ||
| 168 | res[1].start = irq[bus_id - 1]; | 153 | pdata = &i2c_pdata[bus_id - 1]; |
| 169 | omap2_i2c_mux_pins(bus_id); | ||
| 170 | |||
| 171 | /* | 154 | /* |
| 172 | * When waiting for completion of a i2c transfer, we need to | 155 | * When waiting for completion of a i2c transfer, we need to |
| 173 | * set a wake up latency constraint for the MPU. This is to | 156 | * set a wake up latency constraint for the MPU. This is to |
| 174 | * ensure quick enough wakeup from idle, when transfer | 157 | * ensure quick enough wakeup from idle, when transfer |
| 175 | * completes. | 158 | * completes. |
| 159 | * Only omap3 has support for constraints | ||
| 176 | */ | 160 | */ |
| 177 | if (cpu_is_omap34xx()) { | 161 | if (cpu_is_omap34xx()) |
| 178 | struct omap_i2c_bus_platform_data *pd; | 162 | pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat; |
| 179 | 163 | od = omap_device_build(name, bus_id, oh, pdata, | |
| 180 | pd = pdev->dev.platform_data; | 164 | sizeof(struct omap_i2c_bus_platform_data), |
| 181 | pd->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat; | 165 | omap_i2c_latency, ARRAY_SIZE(omap_i2c_latency), 0); |
| 182 | } | 166 | WARN(IS_ERR(od), "Could not build omap_device for %s\n", name); |
| 183 | 167 | ||
| 184 | return platform_device_register(pdev); | 168 | return PTR_ERR(od); |
| 185 | } | 169 | } |
| 170 | #else | ||
| 171 | static inline int omap2_i2c_add_bus(int bus_id) | ||
| 172 | { | ||
| 173 | return 0; | ||
| 174 | } | ||
| 175 | #endif | ||
| 186 | 176 | ||
| 187 | static int __init omap_i2c_add_bus(int bus_id) | 177 | static int __init omap_i2c_add_bus(int bus_id) |
| 188 | { | 178 | { |
| 189 | struct platform_device *pdev; | ||
| 190 | |||
| 191 | pdev = &omap_i2c_devices[bus_id - 1]; | ||
| 192 | |||
| 193 | if (cpu_class_is_omap1()) | 179 | if (cpu_class_is_omap1()) |
| 194 | return omap1_i2c_add_bus(pdev, bus_id); | 180 | return omap1_i2c_add_bus(bus_id); |
| 195 | else | 181 | else |
| 196 | return omap2_i2c_add_bus(pdev, bus_id); | 182 | return omap2_i2c_add_bus(bus_id); |
| 197 | } | 183 | } |
| 198 | 184 | ||
| 199 | /** | 185 | /** |
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h index bb937f3fabed..256ab3f1ec8f 100644 --- a/arch/arm/plat-omap/include/plat/clkdev_omap.h +++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h | |||
| @@ -8,7 +8,7 @@ | |||
| 8 | #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H | 8 | #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H |
| 9 | #define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H | 9 | #define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H |
| 10 | 10 | ||
| 11 | #include <asm/clkdev.h> | 11 | #include <linux/clkdev.h> |
| 12 | 12 | ||
| 13 | struct omap_clk { | 13 | struct omap_clk { |
| 14 | u16 cpu; | 14 | u16 cpu; |
| @@ -31,18 +31,18 @@ struct omap_clk { | |||
| 31 | #define CK_1510 (1 << 2) | 31 | #define CK_1510 (1 << 2) |
| 32 | #define CK_16XX (1 << 3) /* 16xx, 17xx, 5912 */ | 32 | #define CK_16XX (1 << 3) /* 16xx, 17xx, 5912 */ |
| 33 | #define CK_242X (1 << 4) | 33 | #define CK_242X (1 << 4) |
| 34 | #define CK_243X (1 << 5) | 34 | #define CK_243X (1 << 5) /* 243x, 253x */ |
| 35 | #define CK_3XXX (1 << 6) /* OMAP3 + AM3 common clocks*/ | 35 | #define CK_3430ES1 (1 << 6) /* 34xxES1 only */ |
| 36 | #define CK_343X (1 << 7) /* OMAP34xx common clocks */ | 36 | #define CK_3430ES2PLUS (1 << 7) /* 34xxES2, ES3, non-Sitara 35xx only */ |
| 37 | #define CK_3430ES1 (1 << 8) /* 34xxES1 only */ | 37 | #define CK_3505 (1 << 8) |
| 38 | #define CK_3430ES2 (1 << 9) /* 34xxES2, ES3, non-Sitara 35xx only */ | 38 | #define CK_3517 (1 << 9) |
| 39 | #define CK_3505 (1 << 10) | 39 | #define CK_36XX (1 << 10) /* 36xx/37xx-specific clocks */ |
| 40 | #define CK_3517 (1 << 11) | 40 | #define CK_443X (1 << 11) |
| 41 | #define CK_36XX (1 << 12) /* OMAP36xx/37xx-specific clocks */ | ||
| 42 | #define CK_443X (1 << 13) | ||
| 43 | 41 | ||
| 44 | #define CK_AM35XX (CK_3505 | CK_3517) /* all Sitara AM35xx */ | ||
| 45 | 42 | ||
| 43 | #define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS) | ||
| 44 | #define CK_AM35XX (CK_3505 | CK_3517) /* all Sitara AM35xx */ | ||
| 45 | #define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX) | ||
| 46 | 46 | ||
| 47 | 47 | ||
| 48 | #endif | 48 | #endif |
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index fef4696dcf67..8eb0adab19ea 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h | |||
| @@ -49,13 +49,18 @@ struct clkops { | |||
| 49 | /* struct clksel_rate.flags possibilities */ | 49 | /* struct clksel_rate.flags possibilities */ |
| 50 | #define RATE_IN_242X (1 << 0) | 50 | #define RATE_IN_242X (1 << 0) |
| 51 | #define RATE_IN_243X (1 << 1) | 51 | #define RATE_IN_243X (1 << 1) |
| 52 | #define RATE_IN_3XXX (1 << 2) /* rates common to all OMAP3 */ | 52 | #define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */ |
| 53 | #define RATE_IN_3430ES2 (1 << 3) /* 3430ES2 rates only */ | 53 | #define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */ |
| 54 | #define RATE_IN_36XX (1 << 4) | 54 | #define RATE_IN_36XX (1 << 4) |
| 55 | #define RATE_IN_4430 (1 << 5) | 55 | #define RATE_IN_4430 (1 << 5) |
| 56 | 56 | ||
| 57 | #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) | 57 | #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) |
| 58 | #define RATE_IN_3430ES2PLUS (RATE_IN_3430ES2 | RATE_IN_36XX) | 58 | #define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS) |
| 59 | #define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX) | ||
| 60 | |||
| 61 | /* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */ | ||
| 62 | #define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX) | ||
| 63 | |||
| 59 | 64 | ||
| 60 | /** | 65 | /** |
| 61 | * struct clksel_rate - register bitfield values corresponding to clk divisors | 66 | * struct clksel_rate - register bitfield values corresponding to clk divisors |
| @@ -119,8 +124,7 @@ struct clksel { | |||
| 119 | * | 124 | * |
| 120 | * Possible values for @flags: | 125 | * Possible values for @flags: |
| 121 | * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs) | 126 | * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs) |
| 122 | * NO_DCO_SEL: don't program DCO (only for some J-type DPLLs) | 127 | * |
| 123 | |||
| 124 | * @freqsel_mask is only used on the OMAP34xx family and AM35xx. | 128 | * @freqsel_mask is only used on the OMAP34xx family and AM35xx. |
| 125 | * | 129 | * |
| 126 | * XXX Some DPLLs have multiple bypass inputs, so it's not technically | 130 | * XXX Some DPLLs have multiple bypass inputs, so it's not technically |
| @@ -156,6 +160,8 @@ struct dpll_data { | |||
| 156 | u32 autoidle_mask; | 160 | u32 autoidle_mask; |
| 157 | u32 freqsel_mask; | 161 | u32 freqsel_mask; |
| 158 | u32 idlest_mask; | 162 | u32 idlest_mask; |
| 163 | u32 dco_mask; | ||
| 164 | u32 sddiv_mask; | ||
| 159 | u8 auto_recal_bit; | 165 | u8 auto_recal_bit; |
| 160 | u8 recal_en_bit; | 166 | u8 recal_en_bit; |
| 161 | u8 recal_st_bit; | 167 | u8 recal_st_bit; |
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h index a9d69a09920d..6b8088ec74af 100644 --- a/arch/arm/plat-omap/include/plat/common.h +++ b/arch/arm/plat-omap/include/plat/common.h | |||
| @@ -27,6 +27,8 @@ | |||
| 27 | #ifndef __ARCH_ARM_MACH_OMAP_COMMON_H | 27 | #ifndef __ARCH_ARM_MACH_OMAP_COMMON_H |
| 28 | #define __ARCH_ARM_MACH_OMAP_COMMON_H | 28 | #define __ARCH_ARM_MACH_OMAP_COMMON_H |
| 29 | 29 | ||
| 30 | #include <linux/delay.h> | ||
| 31 | |||
| 30 | #include <plat/i2c.h> | 32 | #include <plat/i2c.h> |
| 31 | 33 | ||
| 32 | struct sys_timer; | 34 | struct sys_timer; |
diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h index 0cce4ca83aa0..d1c916fcf770 100644 --- a/arch/arm/plat-omap/include/plat/dma.h +++ b/arch/arm/plat-omap/include/plat/dma.h | |||
| @@ -21,141 +21,15 @@ | |||
| 21 | #ifndef __ASM_ARCH_DMA_H | 21 | #ifndef __ASM_ARCH_DMA_H |
| 22 | #define __ASM_ARCH_DMA_H | 22 | #define __ASM_ARCH_DMA_H |
| 23 | 23 | ||
| 24 | /* Move omap4 specific defines to dma-44xx.h */ | 24 | #include <linux/platform_device.h> |
| 25 | #include "dma-44xx.h" | ||
| 26 | 25 | ||
| 27 | /* Hardware registers for omap1 */ | 26 | /* |
| 28 | #define OMAP1_DMA_BASE (0xfffed800) | 27 | * TODO: These dma channel defines should go away once all |
| 29 | 28 | * the omap drivers hwmod adapted. | |
| 30 | #define OMAP1_DMA_GCR 0x400 | 29 | */ |
| 31 | #define OMAP1_DMA_GSCR 0x404 | ||
| 32 | #define OMAP1_DMA_GRST 0x408 | ||
| 33 | #define OMAP1_DMA_HW_ID 0x442 | ||
| 34 | #define OMAP1_DMA_PCH2_ID 0x444 | ||
| 35 | #define OMAP1_DMA_PCH0_ID 0x446 | ||
| 36 | #define OMAP1_DMA_PCH1_ID 0x448 | ||
| 37 | #define OMAP1_DMA_PCHG_ID 0x44a | ||
| 38 | #define OMAP1_DMA_PCHD_ID 0x44c | ||
| 39 | #define OMAP1_DMA_CAPS_0_U 0x44e | ||
| 40 | #define OMAP1_DMA_CAPS_0_L 0x450 | ||
| 41 | #define OMAP1_DMA_CAPS_1_U 0x452 | ||
| 42 | #define OMAP1_DMA_CAPS_1_L 0x454 | ||
| 43 | #define OMAP1_DMA_CAPS_2 0x456 | ||
| 44 | #define OMAP1_DMA_CAPS_3 0x458 | ||
| 45 | #define OMAP1_DMA_CAPS_4 0x45a | ||
| 46 | #define OMAP1_DMA_PCH2_SR 0x460 | ||
| 47 | #define OMAP1_DMA_PCH0_SR 0x480 | ||
| 48 | #define OMAP1_DMA_PCH1_SR 0x482 | ||
| 49 | #define OMAP1_DMA_PCHD_SR 0x4c0 | ||
| 50 | |||
| 51 | /* Hardware registers for omap2 and omap3 */ | ||
| 52 | #define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000) | ||
| 53 | #define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000) | ||
| 54 | #define OMAP44XX_DMA4_BASE (L4_44XX_BASE + 0x56000) | ||
| 55 | |||
| 56 | #define OMAP_DMA4_REVISION 0x00 | ||
| 57 | #define OMAP_DMA4_GCR 0x78 | ||
| 58 | #define OMAP_DMA4_IRQSTATUS_L0 0x08 | ||
| 59 | #define OMAP_DMA4_IRQSTATUS_L1 0x0c | ||
| 60 | #define OMAP_DMA4_IRQSTATUS_L2 0x10 | ||
| 61 | #define OMAP_DMA4_IRQSTATUS_L3 0x14 | ||
| 62 | #define OMAP_DMA4_IRQENABLE_L0 0x18 | ||
| 63 | #define OMAP_DMA4_IRQENABLE_L1 0x1c | ||
| 64 | #define OMAP_DMA4_IRQENABLE_L2 0x20 | ||
| 65 | #define OMAP_DMA4_IRQENABLE_L3 0x24 | ||
| 66 | #define OMAP_DMA4_SYSSTATUS 0x28 | ||
| 67 | #define OMAP_DMA4_OCP_SYSCONFIG 0x2c | ||
| 68 | #define OMAP_DMA4_CAPS_0 0x64 | ||
| 69 | #define OMAP_DMA4_CAPS_2 0x6c | ||
| 70 | #define OMAP_DMA4_CAPS_3 0x70 | ||
| 71 | #define OMAP_DMA4_CAPS_4 0x74 | ||
| 72 | |||
| 73 | #define OMAP1_LOGICAL_DMA_CH_COUNT 17 | ||
| 74 | #define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */ | ||
| 75 | |||
| 76 | /* Common channel specific registers for omap1 */ | ||
| 77 | #define OMAP1_DMA_CH_BASE(n) (0x40 * (n) + 0x00) | ||
| 78 | #define OMAP1_DMA_CSDP(n) (0x40 * (n) + 0x00) | ||
| 79 | #define OMAP1_DMA_CCR(n) (0x40 * (n) + 0x02) | ||
| 80 | #define OMAP1_DMA_CICR(n) (0x40 * (n) + 0x04) | ||
| 81 | #define OMAP1_DMA_CSR(n) (0x40 * (n) + 0x06) | ||
| 82 | #define OMAP1_DMA_CEN(n) (0x40 * (n) + 0x10) | ||
| 83 | #define OMAP1_DMA_CFN(n) (0x40 * (n) + 0x12) | ||
| 84 | #define OMAP1_DMA_CSFI(n) (0x40 * (n) + 0x14) | ||
| 85 | #define OMAP1_DMA_CSEI(n) (0x40 * (n) + 0x16) | ||
| 86 | #define OMAP1_DMA_CPC(n) (0x40 * (n) + 0x18) /* 15xx only */ | ||
| 87 | #define OMAP1_DMA_CSAC(n) (0x40 * (n) + 0x18) | ||
| 88 | #define OMAP1_DMA_CDAC(n) (0x40 * (n) + 0x1a) | ||
| 89 | #define OMAP1_DMA_CDEI(n) (0x40 * (n) + 0x1c) | ||
| 90 | #define OMAP1_DMA_CDFI(n) (0x40 * (n) + 0x1e) | ||
| 91 | #define OMAP1_DMA_CLNK_CTRL(n) (0x40 * (n) + 0x28) | ||
| 92 | |||
| 93 | /* Common channel specific registers for omap2 */ | ||
| 94 | #define OMAP_DMA4_CH_BASE(n) (0x60 * (n) + 0x80) | ||
| 95 | #define OMAP_DMA4_CCR(n) (0x60 * (n) + 0x80) | ||
| 96 | #define OMAP_DMA4_CLNK_CTRL(n) (0x60 * (n) + 0x84) | ||
| 97 | #define OMAP_DMA4_CICR(n) (0x60 * (n) + 0x88) | ||
| 98 | #define OMAP_DMA4_CSR(n) (0x60 * (n) + 0x8c) | ||
| 99 | #define OMAP_DMA4_CSDP(n) (0x60 * (n) + 0x90) | ||
| 100 | #define OMAP_DMA4_CEN(n) (0x60 * (n) + 0x94) | ||
| 101 | #define OMAP_DMA4_CFN(n) (0x60 * (n) + 0x98) | ||
| 102 | #define OMAP_DMA4_CSEI(n) (0x60 * (n) + 0xa4) | ||
| 103 | #define OMAP_DMA4_CSFI(n) (0x60 * (n) + 0xa8) | ||
| 104 | #define OMAP_DMA4_CDEI(n) (0x60 * (n) + 0xac) | ||
| 105 | #define OMAP_DMA4_CDFI(n) (0x60 * (n) + 0xb0) | ||
| 106 | #define OMAP_DMA4_CSAC(n) (0x60 * (n) + 0xb4) | ||
| 107 | #define OMAP_DMA4_CDAC(n) (0x60 * (n) + 0xb8) | ||
| 108 | |||
| 109 | /* Channel specific registers only on omap1 */ | ||
| 110 | #define OMAP1_DMA_CSSA_L(n) (0x40 * (n) + 0x08) | ||
| 111 | #define OMAP1_DMA_CSSA_U(n) (0x40 * (n) + 0x0a) | ||
| 112 | #define OMAP1_DMA_CDSA_L(n) (0x40 * (n) + 0x0c) | ||
| 113 | #define OMAP1_DMA_CDSA_U(n) (0x40 * (n) + 0x0e) | ||
| 114 | #define OMAP1_DMA_COLOR_L(n) (0x40 * (n) + 0x20) | ||
| 115 | #define OMAP1_DMA_COLOR_U(n) (0x40 * (n) + 0x22) | ||
| 116 | #define OMAP1_DMA_CCR2(n) (0x40 * (n) + 0x24) | ||
| 117 | #define OMAP1_DMA_LCH_CTRL(n) (0x40 * (n) + 0x2a) /* not on 15xx */ | ||
| 118 | #define OMAP1_DMA_CCEN(n) 0 | ||
| 119 | #define OMAP1_DMA_CCFN(n) 0 | ||
| 120 | |||
| 121 | /* Channel specific registers only on omap2 */ | ||
| 122 | #define OMAP_DMA4_CSSA(n) (0x60 * (n) + 0x9c) | ||
| 123 | #define OMAP_DMA4_CDSA(n) (0x60 * (n) + 0xa0) | ||
| 124 | #define OMAP_DMA4_CCEN(n) (0x60 * (n) + 0xbc) | ||
| 125 | #define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0) | ||
| 126 | #define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4) | ||
| 127 | |||
| 128 | /* Additional registers available on OMAP4 */ | ||
| 129 | #define OMAP_DMA4_CDP(n) (0x60 * (n) + 0xd0) | ||
| 130 | #define OMAP_DMA4_CNDP(n) (0x60 * (n) + 0xd4) | ||
| 131 | #define OMAP_DMA4_CCDN(n) (0x60 * (n) + 0xd8) | ||
| 132 | |||
| 133 | /* Dummy defines to keep multi-omap compiles happy */ | ||
| 134 | #define OMAP1_DMA_REVISION 0 | ||
| 135 | #define OMAP1_DMA_IRQSTATUS_L0 0 | ||
| 136 | #define OMAP1_DMA_IRQENABLE_L0 0 | ||
| 137 | #define OMAP1_DMA_OCP_SYSCONFIG 0 | ||
| 138 | #define OMAP_DMA4_HW_ID 0 | ||
| 139 | #define OMAP_DMA4_CAPS_0_L 0 | ||
| 140 | #define OMAP_DMA4_CAPS_0_U 0 | ||
| 141 | #define OMAP_DMA4_CAPS_1_L 0 | ||
| 142 | #define OMAP_DMA4_CAPS_1_U 0 | ||
| 143 | #define OMAP_DMA4_GSCR 0 | ||
| 144 | #define OMAP_DMA4_CPC(n) 0 | ||
| 145 | |||
| 146 | #define OMAP_DMA4_LCH_CTRL(n) 0 | ||
| 147 | #define OMAP_DMA4_COLOR_L(n) 0 | ||
| 148 | #define OMAP_DMA4_COLOR_U(n) 0 | ||
| 149 | #define OMAP_DMA4_CCR2(n) 0 | ||
| 150 | #define OMAP1_DMA_CSSA(n) 0 | ||
| 151 | #define OMAP1_DMA_CDSA(n) 0 | ||
| 152 | #define OMAP_DMA4_CSSA_L(n) 0 | ||
| 153 | #define OMAP_DMA4_CSSA_U(n) 0 | ||
| 154 | #define OMAP_DMA4_CDSA_L(n) 0 | ||
| 155 | #define OMAP_DMA4_CDSA_U(n) 0 | ||
| 156 | #define OMAP1_DMA_COLOR(n) 0 | ||
| 157 | 30 | ||
| 158 | /*----------------------------------------------------------------------------*/ | 31 | /* Move omap4 specific defines to dma-44xx.h */ |
| 32 | #include "dma-44xx.h" | ||
| 159 | 33 | ||
| 160 | /* DMA channels for omap1 */ | 34 | /* DMA channels for omap1 */ |
| 161 | #define OMAP_DMA_NO_DEVICE 0 | 35 | #define OMAP_DMA_NO_DEVICE 0 |
| @@ -405,6 +279,63 @@ | |||
| 405 | #define DMA_CH_PRIO_HIGH 0x1 | 279 | #define DMA_CH_PRIO_HIGH 0x1 |
| 406 | #define DMA_CH_PRIO_LOW 0x0 /* Def */ | 280 | #define DMA_CH_PRIO_LOW 0x0 /* Def */ |
| 407 | 281 | ||
| 282 | /* Errata handling */ | ||
| 283 | #define IS_DMA_ERRATA(id) (errata & (id)) | ||
| 284 | #define SET_DMA_ERRATA(id) (errata |= (id)) | ||
| 285 | |||
| 286 | #define DMA_ERRATA_IFRAME_BUFFERING BIT(0x0) | ||
| 287 | #define DMA_ERRATA_PARALLEL_CHANNELS BIT(0x1) | ||
| 288 | #define DMA_ERRATA_i378 BIT(0x2) | ||
| 289 | #define DMA_ERRATA_i541 BIT(0x3) | ||
| 290 | #define DMA_ERRATA_i88 BIT(0x4) | ||
| 291 | #define DMA_ERRATA_3_3 BIT(0x5) | ||
| 292 | #define DMA_ROMCODE_BUG BIT(0x6) | ||
| 293 | |||
| 294 | /* Attributes for OMAP DMA Contrller */ | ||
| 295 | #define DMA_LINKED_LCH BIT(0x0) | ||
| 296 | #define GLOBAL_PRIORITY BIT(0x1) | ||
| 297 | #define RESERVE_CHANNEL BIT(0x2) | ||
| 298 | #define IS_CSSA_32 BIT(0x3) | ||
| 299 | #define IS_CDSA_32 BIT(0x4) | ||
| 300 | #define IS_RW_PRIORITY BIT(0x5) | ||
| 301 | #define ENABLE_1510_MODE BIT(0x6) | ||
| 302 | #define SRC_PORT BIT(0x7) | ||
| 303 | #define DST_PORT BIT(0x8) | ||
| 304 | #define SRC_INDEX BIT(0x9) | ||
| 305 | #define DST_INDEX BIT(0xA) | ||
| 306 | #define IS_BURST_ONLY4 BIT(0xB) | ||
| 307 | #define CLEAR_CSR_ON_READ BIT(0xC) | ||
| 308 | #define IS_WORD_16 BIT(0xD) | ||
| 309 | |||
| 310 | enum omap_reg_offsets { | ||
| 311 | |||
| 312 | GCR, GSCR, GRST1, HW_ID, | ||
| 313 | PCH2_ID, PCH0_ID, PCH1_ID, PCHG_ID, | ||
| 314 | PCHD_ID, CAPS_0, CAPS_1, CAPS_2, | ||
| 315 | CAPS_3, CAPS_4, PCH2_SR, PCH0_SR, | ||
| 316 | PCH1_SR, PCHD_SR, REVISION, IRQSTATUS_L0, | ||
| 317 | IRQSTATUS_L1, IRQSTATUS_L2, IRQSTATUS_L3, IRQENABLE_L0, | ||
| 318 | IRQENABLE_L1, IRQENABLE_L2, IRQENABLE_L3, SYSSTATUS, | ||
| 319 | OCP_SYSCONFIG, | ||
| 320 | |||
| 321 | /* omap1+ specific */ | ||
| 322 | CPC, CCR2, LCH_CTRL, | ||
| 323 | |||
| 324 | /* Common registers for all omap's */ | ||
| 325 | CSDP, CCR, CICR, CSR, | ||
| 326 | CEN, CFN, CSFI, CSEI, | ||
| 327 | CSAC, CDAC, CDEI, | ||
| 328 | CDFI, CLNK_CTRL, | ||
| 329 | |||
| 330 | /* Channel specific registers */ | ||
| 331 | CSSA, CDSA, COLOR, | ||
| 332 | CCEN, CCFN, | ||
| 333 | |||
| 334 | /* omap3630 and omap4 specific */ | ||
| 335 | CDP, CNDP, CCDN, | ||
| 336 | |||
| 337 | }; | ||
| 338 | |||
| 408 | enum omap_dma_burst_mode { | 339 | enum omap_dma_burst_mode { |
| 409 | OMAP_DMA_DATA_BURST_DIS = 0, | 340 | OMAP_DMA_DATA_BURST_DIS = 0, |
| 410 | OMAP_DMA_DATA_BURST_4, | 341 | OMAP_DMA_DATA_BURST_4, |
| @@ -470,6 +401,41 @@ struct omap_dma_channel_params { | |||
| 470 | #endif | 401 | #endif |
| 471 | }; | 402 | }; |
| 472 | 403 | ||
| 404 | struct omap_dma_lch { | ||
| 405 | int next_lch; | ||
| 406 | int dev_id; | ||
| 407 | u16 saved_csr; | ||
| 408 | u16 enabled_irqs; | ||
| 409 | const char *dev_name; | ||
| 410 | void (*callback)(int lch, u16 ch_status, void *data); | ||
| 411 | void *data; | ||
| 412 | long flags; | ||
| 413 | /* required for Dynamic chaining */ | ||
| 414 | int prev_linked_ch; | ||
| 415 | int next_linked_ch; | ||
| 416 | int state; | ||
| 417 | int chain_id; | ||
| 418 | int status; | ||
| 419 | }; | ||
| 420 | |||
| 421 | struct omap_dma_dev_attr { | ||
| 422 | u32 dev_caps; | ||
| 423 | u16 lch_count; | ||
| 424 | u16 chan_count; | ||
| 425 | struct omap_dma_lch *chan; | ||
| 426 | }; | ||
| 427 | |||
| 428 | /* System DMA platform data structure */ | ||
| 429 | struct omap_system_dma_plat_info { | ||
| 430 | struct omap_dma_dev_attr *dma_attr; | ||
| 431 | u32 errata; | ||
| 432 | void (*disable_irq_lch)(int lch); | ||
| 433 | void (*show_dma_caps)(void); | ||
| 434 | void (*clear_lch_regs)(int lch); | ||
| 435 | void (*clear_dma)(int lch); | ||
| 436 | void (*dma_write)(u32 val, int reg, int lch); | ||
| 437 | u32 (*dma_read)(int reg, int lch); | ||
| 438 | }; | ||
| 473 | 439 | ||
| 474 | extern void omap_set_dma_priority(int lch, int dst_port, int priority); | 440 | extern void omap_set_dma_priority(int lch, int dst_port, int priority); |
| 475 | extern int omap_request_dma(int dev_id, const char *dev_name, | 441 | extern int omap_request_dma(int dev_id, const char *dev_name, |
diff --git a/arch/arm/plat-omap/include/plat/fpga.h b/arch/arm/plat-omap/include/plat/fpga.h index f1864a652f7a..ae39bcb3f5ba 100644 --- a/arch/arm/plat-omap/include/plat/fpga.h +++ b/arch/arm/plat-omap/include/plat/fpga.h | |||
| @@ -19,11 +19,7 @@ | |||
| 19 | #ifndef __ASM_ARCH_OMAP_FPGA_H | 19 | #ifndef __ASM_ARCH_OMAP_FPGA_H |
| 20 | #define __ASM_ARCH_OMAP_FPGA_H | 20 | #define __ASM_ARCH_OMAP_FPGA_H |
| 21 | 21 | ||
| 22 | #if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX) | ||
| 23 | extern void omap1510_fpga_init_irq(void); | 22 | extern void omap1510_fpga_init_irq(void); |
| 24 | #else | ||
| 25 | #define omap1510_fpga_init_irq() (0) | ||
| 26 | #endif | ||
| 27 | 23 | ||
| 28 | #define fpga_read(reg) __raw_readb(reg) | 24 | #define fpga_read(reg) __raw_readb(reg) |
| 29 | #define fpga_write(val, reg) __raw_writeb(val, reg) | 25 | #define fpga_write(val, reg) __raw_writeb(val, reg) |
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h index de1c604962eb..d6f9fa0f62af 100644 --- a/arch/arm/plat-omap/include/plat/gpio.h +++ b/arch/arm/plat-omap/include/plat/gpio.h | |||
| @@ -27,26 +27,15 @@ | |||
| 27 | #define __ASM_ARCH_OMAP_GPIO_H | 27 | #define __ASM_ARCH_OMAP_GPIO_H |
| 28 | 28 | ||
| 29 | #include <linux/io.h> | 29 | #include <linux/io.h> |
| 30 | #include <linux/platform_device.h> | ||
| 30 | #include <mach/irqs.h> | 31 | #include <mach/irqs.h> |
| 31 | 32 | ||
| 32 | #define OMAP1_MPUIO_BASE 0xfffb5000 | 33 | #define OMAP1_MPUIO_BASE 0xfffb5000 |
| 33 | 34 | ||
| 34 | #if (defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)) | 35 | /* |
| 35 | 36 | * These are the omap15xx/16xx offsets. The omap7xx offset are | |
| 36 | #define OMAP_MPUIO_INPUT_LATCH 0x00 | 37 | * OMAP_MPUIO_ / 2 offsets below. |
| 37 | #define OMAP_MPUIO_OUTPUT 0x02 | 38 | */ |
| 38 | #define OMAP_MPUIO_IO_CNTL 0x04 | ||
| 39 | #define OMAP_MPUIO_KBR_LATCH 0x08 | ||
| 40 | #define OMAP_MPUIO_KBC 0x0a | ||
| 41 | #define OMAP_MPUIO_GPIO_EVENT_MODE 0x0c | ||
| 42 | #define OMAP_MPUIO_GPIO_INT_EDGE 0x0e | ||
| 43 | #define OMAP_MPUIO_KBD_INT 0x10 | ||
| 44 | #define OMAP_MPUIO_GPIO_INT 0x12 | ||
| 45 | #define OMAP_MPUIO_KBD_MASKIT 0x14 | ||
| 46 | #define OMAP_MPUIO_GPIO_MASKIT 0x16 | ||
| 47 | #define OMAP_MPUIO_GPIO_DEBOUNCING 0x18 | ||
| 48 | #define OMAP_MPUIO_LATCH 0x1a | ||
| 49 | #else | ||
| 50 | #define OMAP_MPUIO_INPUT_LATCH 0x00 | 39 | #define OMAP_MPUIO_INPUT_LATCH 0x00 |
| 51 | #define OMAP_MPUIO_OUTPUT 0x04 | 40 | #define OMAP_MPUIO_OUTPUT 0x04 |
| 52 | #define OMAP_MPUIO_IO_CNTL 0x08 | 41 | #define OMAP_MPUIO_IO_CNTL 0x08 |
| @@ -60,7 +49,6 @@ | |||
| 60 | #define OMAP_MPUIO_GPIO_MASKIT 0x2c | 49 | #define OMAP_MPUIO_GPIO_MASKIT 0x2c |
| 61 | #define OMAP_MPUIO_GPIO_DEBOUNCING 0x30 | 50 | #define OMAP_MPUIO_GPIO_DEBOUNCING 0x30 |
| 62 | #define OMAP_MPUIO_LATCH 0x34 | 51 | #define OMAP_MPUIO_LATCH 0x34 |
| 63 | #endif | ||
| 64 | 52 | ||
| 65 | #define OMAP34XX_NR_GPIOS 6 | 53 | #define OMAP34XX_NR_GPIOS 6 |
| 66 | 54 | ||
| @@ -71,8 +59,30 @@ | |||
| 71 | IH_MPUIO_BASE + ((nr) & 0x0f) : \ | 59 | IH_MPUIO_BASE + ((nr) & 0x0f) : \ |
| 72 | IH_GPIO_BASE + (nr)) | 60 | IH_GPIO_BASE + (nr)) |
| 73 | 61 | ||
| 74 | extern int omap_gpio_init(void); /* Call from board init only */ | 62 | #define METHOD_MPUIO 0 |
| 75 | extern void omap2_gpio_prepare_for_idle(int power_state); | 63 | #define METHOD_GPIO_1510 1 |
| 64 | #define METHOD_GPIO_1610 2 | ||
| 65 | #define METHOD_GPIO_7XX 3 | ||
| 66 | #define METHOD_GPIO_24XX 5 | ||
| 67 | #define METHOD_GPIO_44XX 6 | ||
| 68 | |||
| 69 | struct omap_gpio_dev_attr { | ||
| 70 | int bank_width; /* GPIO bank width */ | ||
| 71 | bool dbck_flag; /* dbck required or not - True for OMAP3&4 */ | ||
| 72 | }; | ||
| 73 | |||
| 74 | struct omap_gpio_platform_data { | ||
| 75 | u16 virtual_irq_start; | ||
| 76 | int bank_type; | ||
| 77 | int bank_width; /* GPIO bank width */ | ||
| 78 | int bank_stride; /* Only needed for omap1 MPUIO */ | ||
| 79 | bool dbck_flag; /* dbck required or not - True for OMAP3&4 */ | ||
| 80 | }; | ||
| 81 | |||
| 82 | /* TODO: Analyze removing gpio_bank_count usage from driver code */ | ||
| 83 | extern int gpio_bank_count; | ||
| 84 | |||
| 85 | extern void omap2_gpio_prepare_for_idle(int off_mode); | ||
| 76 | extern void omap2_gpio_resume_after_idle(void); | 86 | extern void omap2_gpio_resume_after_idle(void); |
| 77 | extern void omap_set_gpio_debounce(int gpio, int enable); | 87 | extern void omap_set_gpio_debounce(int gpio, int enable); |
| 78 | extern void omap_set_gpio_debounce_time(int gpio, int enable); | 88 | extern void omap_set_gpio_debounce_time(int gpio, int enable); |
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h index 9fd99b9e40ab..85ded598853e 100644 --- a/arch/arm/plat-omap/include/plat/gpmc.h +++ b/arch/arm/plat-omap/include/plat/gpmc.h | |||
| @@ -80,12 +80,12 @@ | |||
| 80 | #define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) | 80 | #define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) |
| 81 | 81 | ||
| 82 | /* | 82 | /* |
| 83 | * Note that all values in this struct are in nanoseconds, while | 83 | * Note that all values in this struct are in nanoseconds except sync_clk |
| 84 | * the register values are in gpmc_fck cycles. | 84 | * (which is in picoseconds), while the register values are in gpmc_fck cycles. |
| 85 | */ | 85 | */ |
| 86 | struct gpmc_timings { | 86 | struct gpmc_timings { |
| 87 | /* Minimum clock period for synchronous mode */ | 87 | /* Minimum clock period for synchronous mode (in picoseconds) */ |
| 88 | u16 sync_clk; | 88 | u32 sync_clk; |
| 89 | 89 | ||
| 90 | /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */ | 90 | /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */ |
| 91 | u16 cs_on; /* Assertion time */ | 91 | u16 cs_on; /* Assertion time */ |
| @@ -117,6 +117,7 @@ struct gpmc_timings { | |||
| 117 | }; | 117 | }; |
| 118 | 118 | ||
| 119 | extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns); | 119 | extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns); |
| 120 | extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps); | ||
| 120 | extern unsigned int gpmc_ticks_to_ns(unsigned int ticks); | 121 | extern unsigned int gpmc_ticks_to_ns(unsigned int ticks); |
| 121 | extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns); | 122 | extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns); |
| 122 | extern unsigned long gpmc_get_fclk_period(void); | 123 | extern unsigned long gpmc_get_fclk_period(void); |
diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h index 36a0befd6168..878d632c4092 100644 --- a/arch/arm/plat-omap/include/plat/i2c.h +++ b/arch/arm/plat-omap/include/plat/i2c.h | |||
| @@ -36,6 +36,19 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate, | |||
| 36 | } | 36 | } |
| 37 | #endif | 37 | #endif |
| 38 | 38 | ||
| 39 | /** | ||
| 40 | * i2c_dev_attr - OMAP I2C controller device attributes for omap_hwmod | ||
| 41 | * @fifo_depth: total controller FIFO size (in bytes) | ||
| 42 | * @flags: differences in hardware support capability | ||
| 43 | * | ||
| 44 | * @fifo_depth represents what exists on the hardware, not what is | ||
| 45 | * actually configured at runtime by the device driver. | ||
| 46 | */ | ||
| 47 | struct omap_i2c_dev_attr { | ||
| 48 | u8 fifo_depth; | ||
| 49 | u8 flags; | ||
| 50 | }; | ||
| 51 | |||
| 39 | void __init omap1_i2c_mux_pins(int bus_id); | 52 | void __init omap1_i2c_mux_pins(int bus_id); |
| 40 | void __init omap2_i2c_mux_pins(int bus_id); | 53 | void __init omap2_i2c_mux_pins(int bus_id); |
| 41 | 54 | ||
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h index 128b549c2796..ef4106c13183 100644 --- a/arch/arm/plat-omap/include/plat/io.h +++ b/arch/arm/plat-omap/include/plat/io.h | |||
| @@ -291,11 +291,12 @@ static inline void omap44xx_map_common_io(void) | |||
| 291 | } | 291 | } |
| 292 | #endif | 292 | #endif |
| 293 | 293 | ||
| 294 | extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, | 294 | extern void omap2_init_common_infrastructure(void); |
| 295 | struct omap_sdrc_params *sdrc_cs1); | 295 | extern void omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0, |
| 296 | struct omap_sdrc_params *sdrc_cs1); | ||
| 296 | 297 | ||
| 297 | #define __arch_ioremap(p,s,t) omap_ioremap(p,s,t) | 298 | #define __arch_ioremap omap_ioremap |
| 298 | #define __arch_iounmap(v) omap_iounmap(v) | 299 | #define __arch_iounmap omap_iounmap |
| 299 | 300 | ||
| 300 | void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type); | 301 | void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type); |
| 301 | void omap_iounmap(volatile void __iomem *addr); | 302 | void omap_iounmap(volatile void __iomem *addr); |
diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h index 33c7d41cb6a5..69230d685538 100644 --- a/arch/arm/plat-omap/include/plat/iommu.h +++ b/arch/arm/plat-omap/include/plat/iommu.h | |||
| @@ -50,6 +50,8 @@ struct iommu { | |||
| 50 | int (*isr)(struct iommu *obj); | 50 | int (*isr)(struct iommu *obj); |
| 51 | 51 | ||
| 52 | void *ctx; /* iommu context: registres saved area */ | 52 | void *ctx; /* iommu context: registres saved area */ |
| 53 | u32 da_start; | ||
| 54 | u32 da_end; | ||
| 53 | }; | 55 | }; |
| 54 | 56 | ||
| 55 | struct cr_regs { | 57 | struct cr_regs { |
| @@ -103,6 +105,8 @@ struct iommu_platform_data { | |||
| 103 | const char *name; | 105 | const char *name; |
| 104 | const char *clk_name; | 106 | const char *clk_name; |
| 105 | const int nr_tlb_entries; | 107 | const int nr_tlb_entries; |
| 108 | u32 da_start; | ||
| 109 | u32 da_end; | ||
| 106 | }; | 110 | }; |
| 107 | 111 | ||
| 108 | #if defined(CONFIG_ARCH_OMAP1) | 112 | #if defined(CONFIG_ARCH_OMAP1) |
| @@ -152,6 +156,7 @@ extern void flush_iotlb_all(struct iommu *obj); | |||
| 152 | extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e); | 156 | extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e); |
| 153 | extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova); | 157 | extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova); |
| 154 | 158 | ||
| 159 | extern int iommu_set_da_range(struct iommu *obj, u32 start, u32 end); | ||
| 155 | extern struct iommu *iommu_get(const char *name); | 160 | extern struct iommu *iommu_get(const char *name); |
| 156 | extern void iommu_put(struct iommu *obj); | 161 | extern void iommu_put(struct iommu *obj); |
| 157 | 162 | ||
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h index 65e20a686713..2910de921c52 100644 --- a/arch/arm/plat-omap/include/plat/irqs.h +++ b/arch/arm/plat-omap/include/plat/irqs.h | |||
| @@ -77,7 +77,7 @@ | |||
| 77 | /* | 77 | /* |
| 78 | * OMAP-1610 specific IRQ numbers for interrupt handler 1 | 78 | * OMAP-1610 specific IRQ numbers for interrupt handler 1 |
| 79 | */ | 79 | */ |
| 80 | #define INT_1610_IH2_IRQ 0 | 80 | #define INT_1610_IH2_IRQ INT_1510_IH2_IRQ |
| 81 | #define INT_1610_IH2_FIQ 2 | 81 | #define INT_1610_IH2_FIQ 2 |
| 82 | #define INT_1610_McBSP2_TX 4 | 82 | #define INT_1610_McBSP2_TX 4 |
| 83 | #define INT_1610_McBSP2_RX 5 | 83 | #define INT_1610_McBSP2_RX 5 |
diff --git a/arch/arm/plat-omap/include/plat/keypad.h b/arch/arm/plat-omap/include/plat/keypad.h index 3ae52ccc793c..793ce9d53294 100644 --- a/arch/arm/plat-omap/include/plat/keypad.h +++ b/arch/arm/plat-omap/include/plat/keypad.h | |||
| @@ -10,16 +10,18 @@ | |||
| 10 | #ifndef ASMARM_ARCH_KEYPAD_H | 10 | #ifndef ASMARM_ARCH_KEYPAD_H |
| 11 | #define ASMARM_ARCH_KEYPAD_H | 11 | #define ASMARM_ARCH_KEYPAD_H |
| 12 | 12 | ||
| 13 | #warning: Please update the board to use matrix_keypad.h instead | 13 | #ifndef CONFIG_ARCH_OMAP1 |
| 14 | #warning Please update the board to use matrix-keypad driver | ||
| 15 | #endif | ||
| 16 | #include <linux/input/matrix_keypad.h> | ||
| 14 | 17 | ||
| 15 | struct omap_kp_platform_data { | 18 | struct omap_kp_platform_data { |
| 16 | int rows; | 19 | int rows; |
| 17 | int cols; | 20 | int cols; |
| 18 | int *keymap; | 21 | const struct matrix_keymap_data *keymap_data; |
| 19 | unsigned int keymapsize; | 22 | bool rep; |
| 20 | unsigned int rep:1; | ||
| 21 | unsigned long delay; | 23 | unsigned long delay; |
| 22 | unsigned int dbounce:1; | 24 | bool dbounce; |
| 23 | /* specific to OMAP242x*/ | 25 | /* specific to OMAP242x*/ |
| 24 | unsigned int *row_gpios; | 26 | unsigned int *row_gpios; |
| 25 | unsigned int *col_gpios; | 27 | unsigned int *col_gpios; |
| @@ -28,18 +30,21 @@ struct omap_kp_platform_data { | |||
| 28 | /* Group (0..3) -- when multiple keys are pressed, only the | 30 | /* Group (0..3) -- when multiple keys are pressed, only the |
| 29 | * keys pressed in the same group are considered as pressed. This is | 31 | * keys pressed in the same group are considered as pressed. This is |
| 30 | * in order to workaround certain crappy HW designs that produce ghost | 32 | * in order to workaround certain crappy HW designs that produce ghost |
| 31 | * keypresses. */ | 33 | * keypresses. Two free bits, not used by neither row/col nor keynum, |
| 32 | #define GROUP_0 (0 << 16) | 34 | * must be available for use as group bits. The below GROUP_SHIFT |
| 33 | #define GROUP_1 (1 << 16) | 35 | * macro definition is based on some prior knowledge of the |
| 34 | #define GROUP_2 (2 << 16) | 36 | * matrix_keypad defined KEY() macro internals. |
| 35 | #define GROUP_3 (3 << 16) | 37 | */ |
| 38 | #define GROUP_SHIFT 14 | ||
| 39 | #define GROUP_0 (0 << GROUP_SHIFT) | ||
| 40 | #define GROUP_1 (1 << GROUP_SHIFT) | ||
| 41 | #define GROUP_2 (2 << GROUP_SHIFT) | ||
| 42 | #define GROUP_3 (3 << GROUP_SHIFT) | ||
| 36 | #define GROUP_MASK GROUP_3 | 43 | #define GROUP_MASK GROUP_3 |
| 44 | #if KEY_MAX & GROUP_MASK | ||
| 45 | #error Group bits in conflict with keynum bits | ||
| 46 | #endif | ||
| 37 | 47 | ||
| 38 | #define KEY_PERSISTENT 0x00800000 | ||
| 39 | #define KEYNUM_MASK 0x00EFFFFF | ||
| 40 | #define KEY(col, row, val) (((col) << 28) | ((row) << 24) | (val)) | ||
| 41 | #define PERSISTENT_KEY(col, row) (((col) << 28) | ((row) << 24) | \ | ||
| 42 | KEY_PERSISTENT) | ||
| 43 | 48 | ||
| 44 | #endif | 49 | #endif |
| 45 | 50 | ||
diff --git a/arch/arm/plat-omap/include/plat/l4_3xxx.h b/arch/arm/plat-omap/include/plat/l4_3xxx.h new file mode 100644 index 000000000000..5e1949375422 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/l4_3xxx.h | |||
| @@ -0,0 +1,24 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/l4_3xxx.h - L4 firewall definitions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Nokia Corporation | ||
| 5 | * Paul Walmsley | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_L4_3XXX_H | ||
| 14 | #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_L4_3XXX_H | ||
| 15 | |||
| 16 | /* L4 CORE */ | ||
| 17 | #define OMAP3_L4_CORE_FW_I2C1_REGION 21 | ||
| 18 | #define OMAP3_L4_CORE_FW_I2C1_TA_REGION 22 | ||
| 19 | #define OMAP3_L4_CORE_FW_I2C2_REGION 23 | ||
| 20 | #define OMAP3_L4_CORE_FW_I2C2_TA_REGION 24 | ||
| 21 | #define OMAP3_L4_CORE_FW_I2C3_REGION 73 | ||
| 22 | #define OMAP3_L4_CORE_FW_I2C3_TA_REGION 74 | ||
| 23 | |||
| 24 | #endif | ||
diff --git a/arch/arm/plat-omap/include/plat/mailbox.h b/arch/arm/plat-omap/include/plat/mailbox.h index 997656552109..cc3921e9059c 100644 --- a/arch/arm/plat-omap/include/plat/mailbox.h +++ b/arch/arm/plat-omap/include/plat/mailbox.h | |||
| @@ -46,8 +46,8 @@ struct omap_mbox_queue { | |||
| 46 | struct kfifo fifo; | 46 | struct kfifo fifo; |
| 47 | struct work_struct work; | 47 | struct work_struct work; |
| 48 | struct tasklet_struct tasklet; | 48 | struct tasklet_struct tasklet; |
| 49 | int (*callback)(void *); | ||
| 50 | struct omap_mbox *mbox; | 49 | struct omap_mbox *mbox; |
| 50 | bool full; | ||
| 51 | }; | 51 | }; |
| 52 | 52 | ||
| 53 | struct omap_mbox { | 53 | struct omap_mbox { |
| @@ -57,13 +57,15 @@ struct omap_mbox { | |||
| 57 | struct omap_mbox_ops *ops; | 57 | struct omap_mbox_ops *ops; |
| 58 | struct device *dev; | 58 | struct device *dev; |
| 59 | void *priv; | 59 | void *priv; |
| 60 | int use_count; | ||
| 61 | struct blocking_notifier_head notifier; | ||
| 60 | }; | 62 | }; |
| 61 | 63 | ||
| 62 | int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg); | 64 | int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg); |
| 63 | void omap_mbox_init_seq(struct omap_mbox *); | 65 | void omap_mbox_init_seq(struct omap_mbox *); |
| 64 | 66 | ||
| 65 | struct omap_mbox *omap_mbox_get(const char *); | 67 | struct omap_mbox *omap_mbox_get(const char *, struct notifier_block *nb); |
| 66 | void omap_mbox_put(struct omap_mbox *); | 68 | void omap_mbox_put(struct omap_mbox *mbox, struct notifier_block *nb); |
| 67 | 69 | ||
| 68 | int omap_mbox_register(struct device *parent, struct omap_mbox **); | 70 | int omap_mbox_register(struct device *parent, struct omap_mbox **); |
| 69 | int omap_mbox_unregister(void); | 71 | int omap_mbox_unregister(void); |
diff --git a/arch/arm/plat-omap/include/plat/memory.h b/arch/arm/plat-omap/include/plat/memory.h index d5306bee44b2..f8d922fb5584 100644 --- a/arch/arm/plat-omap/include/plat/memory.h +++ b/arch/arm/plat-omap/include/plat/memory.h | |||
| @@ -61,17 +61,17 @@ | |||
| 61 | #define lbus_to_virt(x) ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET) | 61 | #define lbus_to_virt(x) ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET) |
| 62 | #define is_lbus_device(dev) (cpu_is_omap15xx() && dev && (strncmp(dev_name(dev), "ohci", 4) == 0)) | 62 | #define is_lbus_device(dev) (cpu_is_omap15xx() && dev && (strncmp(dev_name(dev), "ohci", 4) == 0)) |
| 63 | 63 | ||
| 64 | #define __arch_page_to_dma(dev, page) \ | 64 | #define __arch_pfn_to_dma(dev, pfn) \ |
| 65 | ({ dma_addr_t __dma = page_to_phys(page); \ | 65 | ({ dma_addr_t __dma = __pfn_to_phys(pfn); \ |
| 66 | if (is_lbus_device(dev)) \ | 66 | if (is_lbus_device(dev)) \ |
| 67 | __dma = __dma - PHYS_OFFSET + OMAP1510_LB_OFFSET; \ | 67 | __dma = __dma - PHYS_OFFSET + OMAP1510_LB_OFFSET; \ |
| 68 | __dma; }) | 68 | __dma; }) |
| 69 | 69 | ||
| 70 | #define __arch_dma_to_page(dev, addr) \ | 70 | #define __arch_dma_to_pfn(dev, addr) \ |
| 71 | ({ dma_addr_t __dma = addr; \ | 71 | ({ dma_addr_t __dma = addr; \ |
| 72 | if (is_lbus_device(dev)) \ | 72 | if (is_lbus_device(dev)) \ |
| 73 | __dma += PHYS_OFFSET - OMAP1510_LB_OFFSET; \ | 73 | __dma += PHYS_OFFSET - OMAP1510_LB_OFFSET; \ |
| 74 | phys_to_page(__dma); \ | 74 | __phys_to_pfn(__dma); \ |
| 75 | }) | 75 | }) |
| 76 | 76 | ||
| 77 | #define __arch_dma_to_virt(dev, addr) ({ (void *) (is_lbus_device(dev) ? \ | 77 | #define __arch_dma_to_virt(dev, addr) ({ (void *) (is_lbus_device(dev) ? \ |
diff --git a/arch/arm/plat-omap/include/plat/omap-pm.h b/arch/arm/plat-omap/include/plat/omap-pm.h index 728fbb9dd549..c0a752053039 100644 --- a/arch/arm/plat-omap/include/plat/omap-pm.h +++ b/arch/arm/plat-omap/include/plat/omap-pm.h | |||
| @@ -17,26 +17,7 @@ | |||
| 17 | #include <linux/device.h> | 17 | #include <linux/device.h> |
| 18 | #include <linux/cpufreq.h> | 18 | #include <linux/cpufreq.h> |
| 19 | #include <linux/clk.h> | 19 | #include <linux/clk.h> |
| 20 | 20 | #include <linux/opp.h> | |
| 21 | #include "powerdomain.h" | ||
| 22 | |||
| 23 | /** | ||
| 24 | * struct omap_opp - clock frequency-to-OPP ID table for DSP, MPU | ||
| 25 | * @rate: target clock rate | ||
| 26 | * @opp_id: OPP ID | ||
| 27 | * @min_vdd: minimum VDD1 voltage (in millivolts) for this OPP | ||
| 28 | * | ||
| 29 | * Operating performance point data. Can vary by OMAP chip and board. | ||
| 30 | */ | ||
| 31 | struct omap_opp { | ||
| 32 | unsigned long rate; | ||
| 33 | u8 opp_id; | ||
| 34 | u16 min_vdd; | ||
| 35 | }; | ||
| 36 | |||
| 37 | extern struct omap_opp *mpu_opps; | ||
| 38 | extern struct omap_opp *dsp_opps; | ||
| 39 | extern struct omap_opp *l3_opps; | ||
| 40 | 21 | ||
| 41 | /* | 22 | /* |
| 42 | * agent_id values for use with omap_pm_set_min_bus_tput(): | 23 | * agent_id values for use with omap_pm_set_min_bus_tput(): |
| @@ -59,9 +40,11 @@ extern struct omap_opp *l3_opps; | |||
| 59 | * framework starts. The "_if_" is to avoid name collisions with the | 40 | * framework starts. The "_if_" is to avoid name collisions with the |
| 60 | * PM idle-loop code. | 41 | * PM idle-loop code. |
| 61 | */ | 42 | */ |
| 62 | int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table, | 43 | #ifdef CONFIG_OMAP_PM_NONE |
| 63 | struct omap_opp *dsp_opp_table, | 44 | #define omap_pm_if_early_init() 0 |
| 64 | struct omap_opp *l3_opp_table); | 45 | #else |
| 46 | int __init omap_pm_if_early_init(void); | ||
| 47 | #endif | ||
| 65 | 48 | ||
| 66 | /** | 49 | /** |
| 67 | * omap_pm_if_init - OMAP PM init code called after clock fw init | 50 | * omap_pm_if_init - OMAP PM init code called after clock fw init |
| @@ -69,7 +52,11 @@ int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table, | |||
| 69 | * The main initialization code. OPP tables are passed in here. The | 52 | * The main initialization code. OPP tables are passed in here. The |
| 70 | * "_if_" is to avoid name collisions with the PM idle-loop code. | 53 | * "_if_" is to avoid name collisions with the PM idle-loop code. |
| 71 | */ | 54 | */ |
| 55 | #ifdef CONFIG_OMAP_PM_NONE | ||
| 56 | #define omap_pm_if_init() 0 | ||
| 57 | #else | ||
| 72 | int __init omap_pm_if_init(void); | 58 | int __init omap_pm_if_init(void); |
| 59 | #endif | ||
| 73 | 60 | ||
| 74 | /** | 61 | /** |
| 75 | * omap_pm_if_exit - OMAP PM exit code | 62 | * omap_pm_if_exit - OMAP PM exit code |
| @@ -363,9 +350,11 @@ unsigned long omap_pm_cpu_get_freq(void); | |||
| 363 | * driver must restore device context. If the number of context losses | 350 | * driver must restore device context. If the number of context losses |
| 364 | * exceeds the maximum positive integer, the function will wrap to 0 and | 351 | * exceeds the maximum positive integer, the function will wrap to 0 and |
| 365 | * continue counting. Returns the number of context losses for this device, | 352 | * continue counting. Returns the number of context losses for this device, |
| 366 | * or -EINVAL upon error. | 353 | * or zero upon error. |
| 367 | */ | 354 | */ |
| 368 | int omap_pm_get_dev_context_loss_count(struct device *dev); | 355 | u32 omap_pm_get_dev_context_loss_count(struct device *dev); |
| 369 | 356 | ||
| 357 | void omap_pm_enable_off_mode(void); | ||
| 358 | void omap_pm_disable_off_mode(void); | ||
| 370 | 359 | ||
| 371 | #endif | 360 | #endif |
diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h index c8dae02f0704..2682043f5a5b 100644 --- a/arch/arm/plat-omap/include/plat/omap-serial.h +++ b/arch/arm/plat-omap/include/plat/omap-serial.h | |||
| @@ -22,7 +22,7 @@ | |||
| 22 | 22 | ||
| 23 | #include <plat/mux.h> | 23 | #include <plat/mux.h> |
| 24 | 24 | ||
| 25 | #define DRIVER_NAME "omap-hsuart" | 25 | #define DRIVER_NAME "omap_uart" |
| 26 | 26 | ||
| 27 | /* | 27 | /* |
| 28 | * Use tty device name as ttyO, [O -> OMAP] | 28 | * Use tty device name as ttyO, [O -> OMAP] |
| @@ -31,20 +31,8 @@ | |||
| 31 | */ | 31 | */ |
| 32 | #define OMAP_SERIAL_NAME "ttyO" | 32 | #define OMAP_SERIAL_NAME "ttyO" |
| 33 | 33 | ||
| 34 | #define OMAP_MDR1_DISABLE 0x07 | ||
| 35 | #define OMAP_MDR1_MODE13X 0x03 | ||
| 36 | #define OMAP_MDR1_MODE16X 0x00 | ||
| 37 | #define OMAP_MODE13X_SPEED 230400 | 34 | #define OMAP_MODE13X_SPEED 230400 |
| 38 | 35 | ||
| 39 | /* | ||
| 40 | * LCR = 0XBF: Switch to Configuration Mode B. | ||
| 41 | * In configuration mode b allow access | ||
| 42 | * to EFR,DLL,DLH. | ||
| 43 | * Reference OMAP TRM Chapter 17 | ||
| 44 | * Section: 1.4.3 Mode Selection | ||
| 45 | */ | ||
| 46 | #define OMAP_UART_LCR_CONF_MDB 0XBF | ||
| 47 | |||
| 48 | /* WER = 0x7F | 36 | /* WER = 0x7F |
| 49 | * Enable module level wakeup in WER reg | 37 | * Enable module level wakeup in WER reg |
| 50 | */ | 38 | */ |
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h index 8b3f12ff5cbc..ea2b8a6306e7 100644 --- a/arch/arm/plat-omap/include/plat/omap44xx.h +++ b/arch/arm/plat-omap/include/plat/omap44xx.h | |||
| @@ -52,5 +52,10 @@ | |||
| 52 | #define OMAP4_MMU1_BASE 0x55082000 | 52 | #define OMAP4_MMU1_BASE 0x55082000 |
| 53 | #define OMAP4_MMU2_BASE 0x4A066000 | 53 | #define OMAP4_MMU2_BASE 0x4A066000 |
| 54 | 54 | ||
| 55 | #define OMAP44XX_USBTLL_BASE (L4_44XX_BASE + 0x62000) | ||
| 56 | #define OMAP44XX_UHH_CONFIG_BASE (L4_44XX_BASE + 0x64000) | ||
| 57 | #define OMAP44XX_HSUSB_OHCI_BASE (L4_44XX_BASE + 0x64800) | ||
| 58 | #define OMAP44XX_HSUSB_EHCI_BASE (L4_44XX_BASE + 0x64C00) | ||
| 59 | |||
| 55 | #endif /* __ASM_ARCH_OMAP44XX_H */ | 60 | #endif /* __ASM_ARCH_OMAP44XX_H */ |
| 56 | 61 | ||
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h index 28e2d1a78433..e4c349ff9fd8 100644 --- a/arch/arm/plat-omap/include/plat/omap_device.h +++ b/arch/arm/plat-omap/include/plat/omap_device.h | |||
| @@ -107,6 +107,7 @@ void __iomem *omap_device_get_rt_va(struct omap_device *od); | |||
| 107 | int omap_device_align_pm_lat(struct platform_device *pdev, | 107 | int omap_device_align_pm_lat(struct platform_device *pdev, |
| 108 | u32 new_wakeup_lat_limit); | 108 | u32 new_wakeup_lat_limit); |
| 109 | struct powerdomain *omap_device_get_pwrdm(struct omap_device *od); | 109 | struct powerdomain *omap_device_get_pwrdm(struct omap_device *od); |
| 110 | u32 omap_device_get_context_loss_count(struct platform_device *pdev); | ||
| 110 | 111 | ||
| 111 | /* Other */ | 112 | /* Other */ |
| 112 | 113 | ||
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 7eaa8edf3b14..6864a997f2ca 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h | |||
| @@ -23,7 +23,7 @@ | |||
| 23 | * - add pinmuxing | 23 | * - add pinmuxing |
| 24 | * - init_conn_id_bit (CONNID_BIT_VECTOR) | 24 | * - init_conn_id_bit (CONNID_BIT_VECTOR) |
| 25 | * - implement default hwmod SMS/SDRC flags? | 25 | * - implement default hwmod SMS/SDRC flags? |
| 26 | * - remove unused fields | 26 | * - move Linux-specific data ("non-ROM data") out |
| 27 | * | 27 | * |
| 28 | */ | 28 | */ |
| 29 | #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H | 29 | #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H |
| @@ -32,8 +32,9 @@ | |||
| 32 | #include <linux/kernel.h> | 32 | #include <linux/kernel.h> |
| 33 | #include <linux/list.h> | 33 | #include <linux/list.h> |
| 34 | #include <linux/ioport.h> | 34 | #include <linux/ioport.h> |
| 35 | #include <linux/mutex.h> | 35 | #include <linux/spinlock.h> |
| 36 | #include <plat/cpu.h> | 36 | #include <plat/cpu.h> |
| 37 | #include <plat/voltage.h> | ||
| 37 | 38 | ||
| 38 | struct omap_device; | 39 | struct omap_device; |
| 39 | 40 | ||
| @@ -76,6 +77,20 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2; | |||
| 76 | #define HWMOD_IDLEMODE_FORCE (1 << 0) | 77 | #define HWMOD_IDLEMODE_FORCE (1 << 0) |
| 77 | #define HWMOD_IDLEMODE_NO (1 << 1) | 78 | #define HWMOD_IDLEMODE_NO (1 << 1) |
| 78 | #define HWMOD_IDLEMODE_SMART (1 << 2) | 79 | #define HWMOD_IDLEMODE_SMART (1 << 2) |
| 80 | /* Slave idle mode flag only */ | ||
| 81 | #define HWMOD_IDLEMODE_SMART_WKUP (1 << 3) | ||
| 82 | |||
| 83 | /** | ||
| 84 | * struct omap_hwmod_mux_info - hwmod specific mux configuration | ||
| 85 | * @pads: array of omap_device_pad entries | ||
| 86 | * @nr_pads: number of omap_device_pad entries | ||
| 87 | * | ||
| 88 | * Note that this is currently built during init as needed. | ||
| 89 | */ | ||
| 90 | struct omap_hwmod_mux_info { | ||
| 91 | int nr_pads; | ||
| 92 | struct omap_device_pad *pads; | ||
| 93 | }; | ||
| 79 | 94 | ||
| 80 | /** | 95 | /** |
| 81 | * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod | 96 | * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod |
| @@ -159,7 +174,7 @@ struct omap_hwmod_omap2_firewall { | |||
| 159 | * ADDR_MAP_ON_INIT: Map this address space during omap_hwmod init. | 174 | * ADDR_MAP_ON_INIT: Map this address space during omap_hwmod init. |
| 160 | * ADDR_TYPE_RT: Address space contains module register target data. | 175 | * ADDR_TYPE_RT: Address space contains module register target data. |
| 161 | */ | 176 | */ |
| 162 | #define ADDR_MAP_ON_INIT (1 << 0) | 177 | #define ADDR_MAP_ON_INIT (1 << 0) /* XXX does not belong */ |
| 163 | #define ADDR_TYPE_RT (1 << 1) | 178 | #define ADDR_TYPE_RT (1 << 1) |
| 164 | 179 | ||
| 165 | /** | 180 | /** |
| @@ -200,8 +215,6 @@ struct omap_hwmod_addr_space { | |||
| 200 | * @fw: interface firewall data | 215 | * @fw: interface firewall data |
| 201 | * @addr_cnt: ARRAY_SIZE(@addr) | 216 | * @addr_cnt: ARRAY_SIZE(@addr) |
| 202 | * @width: OCP data width | 217 | * @width: OCP data width |
| 203 | * @thread_cnt: number of threads | ||
| 204 | * @max_burst_len: maximum burst length in @width sized words (0 if unlimited) | ||
| 205 | * @user: initiators using this interface (see OCP_USER_* macros above) | 218 | * @user: initiators using this interface (see OCP_USER_* macros above) |
| 206 | * @flags: OCP interface flags (see OCPIF_* macros above) | 219 | * @flags: OCP interface flags (see OCPIF_* macros above) |
| 207 | * | 220 | * |
| @@ -221,8 +234,6 @@ struct omap_hwmod_ocp_if { | |||
| 221 | } fw; | 234 | } fw; |
| 222 | u8 addr_cnt; | 235 | u8 addr_cnt; |
| 223 | u8 width; | 236 | u8 width; |
| 224 | u8 thread_cnt; | ||
| 225 | u8 max_burst_len; | ||
| 226 | u8 user; | 237 | u8 user; |
| 227 | u8 flags; | 238 | u8 flags; |
| 228 | }; | 239 | }; |
| @@ -231,11 +242,12 @@ struct omap_hwmod_ocp_if { | |||
| 231 | /* Macros for use in struct omap_hwmod_sysconfig */ | 242 | /* Macros for use in struct omap_hwmod_sysconfig */ |
| 232 | 243 | ||
| 233 | /* Flags for use in omap_hwmod_sysconfig.idlemodes */ | 244 | /* Flags for use in omap_hwmod_sysconfig.idlemodes */ |
| 234 | #define MASTER_STANDBY_SHIFT 2 | 245 | #define MASTER_STANDBY_SHIFT 4 |
| 235 | #define SLAVE_IDLE_SHIFT 0 | 246 | #define SLAVE_IDLE_SHIFT 0 |
| 236 | #define SIDLE_FORCE (HWMOD_IDLEMODE_FORCE << SLAVE_IDLE_SHIFT) | 247 | #define SIDLE_FORCE (HWMOD_IDLEMODE_FORCE << SLAVE_IDLE_SHIFT) |
| 237 | #define SIDLE_NO (HWMOD_IDLEMODE_NO << SLAVE_IDLE_SHIFT) | 248 | #define SIDLE_NO (HWMOD_IDLEMODE_NO << SLAVE_IDLE_SHIFT) |
| 238 | #define SIDLE_SMART (HWMOD_IDLEMODE_SMART << SLAVE_IDLE_SHIFT) | 249 | #define SIDLE_SMART (HWMOD_IDLEMODE_SMART << SLAVE_IDLE_SHIFT) |
| 250 | #define SIDLE_SMART_WKUP (HWMOD_IDLEMODE_SMART_WKUP << SLAVE_IDLE_SHIFT) | ||
| 239 | #define MSTANDBY_FORCE (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT) | 251 | #define MSTANDBY_FORCE (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT) |
| 240 | #define MSTANDBY_NO (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT) | 252 | #define MSTANDBY_NO (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT) |
| 241 | #define MSTANDBY_SMART (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT) | 253 | #define MSTANDBY_SMART (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT) |
| @@ -357,14 +369,14 @@ struct omap_hwmod_omap4_prcm { | |||
| 357 | * HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out | 369 | * HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out |
| 358 | * of standby, rather than relying on module smart-standby | 370 | * of standby, rather than relying on module smart-standby |
| 359 | * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for | 371 | * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for |
| 360 | * SDRAM controller, etc. | 372 | * SDRAM controller, etc. XXX probably belongs outside the main hwmod file |
| 361 | * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM | 373 | * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM |
| 362 | * controller, etc. | 374 | * controller, etc. XXX probably belongs outside the main hwmod file |
| 363 | * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE) | 375 | * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE) |
| 364 | * when module is enabled, rather than the default, which is to | 376 | * when module is enabled, rather than the default, which is to |
| 365 | * enable autoidle | 377 | * enable autoidle |
| 366 | * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup | 378 | * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup |
| 367 | * HWMOD_NO_IDLEST : this module does not have idle status - this is the case | 379 | * HWMOD_NO_IDLEST: this module does not have idle status - this is the case |
| 368 | * only for few initiator modules on OMAP2 & 3. | 380 | * only for few initiator modules on OMAP2 & 3. |
| 369 | * HWMOD_CONTROL_OPT_CLKS_IN_RESET: Enable all optional clocks during reset. | 381 | * HWMOD_CONTROL_OPT_CLKS_IN_RESET: Enable all optional clocks during reset. |
| 370 | * This is needed for devices like DSS that require optional clocks enabled | 382 | * This is needed for devices like DSS that require optional clocks enabled |
| @@ -415,14 +427,31 @@ struct omap_hwmod_omap4_prcm { | |||
| 415 | * @name: name of the hwmod_class | 427 | * @name: name of the hwmod_class |
| 416 | * @sysc: device SYSCONFIG/SYSSTATUS register data | 428 | * @sysc: device SYSCONFIG/SYSSTATUS register data |
| 417 | * @rev: revision of the IP class | 429 | * @rev: revision of the IP class |
| 430 | * @pre_shutdown: ptr to fn to be executed immediately prior to device shutdown | ||
| 431 | * @reset: ptr to fn to be executed in place of the standard hwmod reset fn | ||
| 418 | * | 432 | * |
| 419 | * Represent the class of a OMAP hardware "modules" (e.g. timer, | 433 | * Represent the class of a OMAP hardware "modules" (e.g. timer, |
| 420 | * smartreflex, gpio, uart...) | 434 | * smartreflex, gpio, uart...) |
| 435 | * | ||
| 436 | * @pre_shutdown is a function that will be run immediately before | ||
| 437 | * hwmod clocks are disabled, etc. It is intended for use for hwmods | ||
| 438 | * like the MPU watchdog, which cannot be disabled with the standard | ||
| 439 | * omap_hwmod_shutdown(). The function should return 0 upon success, | ||
| 440 | * or some negative error upon failure. Returning an error will cause | ||
| 441 | * omap_hwmod_shutdown() to abort the device shutdown and return an | ||
| 442 | * error. | ||
| 443 | * | ||
| 444 | * If @reset is defined, then the function it points to will be | ||
| 445 | * executed in place of the standard hwmod _reset() code in | ||
| 446 | * mach-omap2/omap_hwmod.c. This is needed for IP blocks which have | ||
| 447 | * unusual reset sequences - usually processor IP blocks like the IVA. | ||
| 421 | */ | 448 | */ |
| 422 | struct omap_hwmod_class { | 449 | struct omap_hwmod_class { |
| 423 | const char *name; | 450 | const char *name; |
| 424 | struct omap_hwmod_class_sysconfig *sysc; | 451 | struct omap_hwmod_class_sysconfig *sysc; |
| 425 | u32 rev; | 452 | u32 rev; |
| 453 | int (*pre_shutdown)(struct omap_hwmod *oh); | ||
| 454 | int (*reset)(struct omap_hwmod *oh); | ||
| 426 | }; | 455 | }; |
| 427 | 456 | ||
| 428 | /** | 457 | /** |
| @@ -436,14 +465,14 @@ struct omap_hwmod_class { | |||
| 436 | * @main_clk: main clock: OMAP clock name | 465 | * @main_clk: main clock: OMAP clock name |
| 437 | * @_clk: pointer to the main struct clk (filled in at runtime) | 466 | * @_clk: pointer to the main struct clk (filled in at runtime) |
| 438 | * @opt_clks: other device clocks that drivers can request (0..*) | 467 | * @opt_clks: other device clocks that drivers can request (0..*) |
| 468 | * @vdd_name: voltage domain name | ||
| 469 | * @voltdm: pointer to voltage domain (filled in at runtime) | ||
| 439 | * @masters: ptr to array of OCP ifs that this hwmod can initiate on | 470 | * @masters: ptr to array of OCP ifs that this hwmod can initiate on |
| 440 | * @slaves: ptr to array of OCP ifs that this hwmod can respond on | 471 | * @slaves: ptr to array of OCP ifs that this hwmod can respond on |
| 441 | * @dev_attr: arbitrary device attributes that can be passed to the driver | 472 | * @dev_attr: arbitrary device attributes that can be passed to the driver |
| 442 | * @_sysc_cache: internal-use hwmod flags | 473 | * @_sysc_cache: internal-use hwmod flags |
| 443 | * @_mpu_rt_va: cached register target start address (internal use) | 474 | * @_mpu_rt_va: cached register target start address (internal use) |
| 444 | * @_mpu_port_index: cached MPU register target slave ID (internal use) | 475 | * @_mpu_port_index: cached MPU register target slave ID (internal use) |
| 445 | * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6) | ||
| 446 | * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift | ||
| 447 | * @mpu_irqs_cnt: number of @mpu_irqs | 476 | * @mpu_irqs_cnt: number of @mpu_irqs |
| 448 | * @sdma_reqs_cnt: number of @sdma_reqs | 477 | * @sdma_reqs_cnt: number of @sdma_reqs |
| 449 | * @opt_clks_cnt: number of @opt_clks | 478 | * @opt_clks_cnt: number of @opt_clks |
| @@ -452,9 +481,10 @@ struct omap_hwmod_class { | |||
| 452 | * @response_lat: device OCP response latency (in interface clock cycles) | 481 | * @response_lat: device OCP response latency (in interface clock cycles) |
| 453 | * @_int_flags: internal-use hwmod flags | 482 | * @_int_flags: internal-use hwmod flags |
| 454 | * @_state: internal-use hwmod state | 483 | * @_state: internal-use hwmod state |
| 484 | * @_postsetup_state: internal-use state to leave the hwmod in after _setup() | ||
| 455 | * @flags: hwmod flags (documented below) | 485 | * @flags: hwmod flags (documented below) |
| 456 | * @omap_chip: OMAP chips this hwmod is present on | 486 | * @omap_chip: OMAP chips this hwmod is present on |
| 457 | * @_mutex: mutex serializing operations on this hwmod | 487 | * @_lock: spinlock serializing operations on this hwmod |
| 458 | * @node: list node for hwmod list (internal use) | 488 | * @node: list node for hwmod list (internal use) |
| 459 | * | 489 | * |
| 460 | * @main_clk refers to this module's "main clock," which for our | 490 | * @main_clk refers to this module's "main clock," which for our |
| @@ -469,6 +499,7 @@ struct omap_hwmod { | |||
| 469 | const char *name; | 499 | const char *name; |
| 470 | struct omap_hwmod_class *class; | 500 | struct omap_hwmod_class *class; |
| 471 | struct omap_device *od; | 501 | struct omap_device *od; |
| 502 | struct omap_hwmod_mux_info *mux; | ||
| 472 | struct omap_hwmod_irq_info *mpu_irqs; | 503 | struct omap_hwmod_irq_info *mpu_irqs; |
| 473 | struct omap_hwmod_dma_info *sdma_reqs; | 504 | struct omap_hwmod_dma_info *sdma_reqs; |
| 474 | struct omap_hwmod_rst_info *rst_lines; | 505 | struct omap_hwmod_rst_info *rst_lines; |
| @@ -479,17 +510,17 @@ struct omap_hwmod { | |||
| 479 | const char *main_clk; | 510 | const char *main_clk; |
| 480 | struct clk *_clk; | 511 | struct clk *_clk; |
| 481 | struct omap_hwmod_opt_clk *opt_clks; | 512 | struct omap_hwmod_opt_clk *opt_clks; |
| 513 | char *vdd_name; | ||
| 514 | struct voltagedomain *voltdm; | ||
| 482 | struct omap_hwmod_ocp_if **masters; /* connect to *_IA */ | 515 | struct omap_hwmod_ocp_if **masters; /* connect to *_IA */ |
| 483 | struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */ | 516 | struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */ |
| 484 | void *dev_attr; | 517 | void *dev_attr; |
| 485 | u32 _sysc_cache; | 518 | u32 _sysc_cache; |
| 486 | void __iomem *_mpu_rt_va; | 519 | void __iomem *_mpu_rt_va; |
| 487 | struct mutex _mutex; | 520 | spinlock_t _lock; |
| 488 | struct list_head node; | 521 | struct list_head node; |
| 489 | u16 flags; | 522 | u16 flags; |
| 490 | u8 _mpu_port_index; | 523 | u8 _mpu_port_index; |
| 491 | u8 msuspendmux_reg_id; | ||
| 492 | u8 msuspendmux_shift; | ||
| 493 | u8 response_lat; | 524 | u8 response_lat; |
| 494 | u8 mpu_irqs_cnt; | 525 | u8 mpu_irqs_cnt; |
| 495 | u8 sdma_reqs_cnt; | 526 | u8 sdma_reqs_cnt; |
| @@ -500,16 +531,15 @@ struct omap_hwmod { | |||
| 500 | u8 hwmods_cnt; | 531 | u8 hwmods_cnt; |
| 501 | u8 _int_flags; | 532 | u8 _int_flags; |
| 502 | u8 _state; | 533 | u8 _state; |
| 534 | u8 _postsetup_state; | ||
| 503 | const struct omap_chip_id omap_chip; | 535 | const struct omap_chip_id omap_chip; |
| 504 | }; | 536 | }; |
| 505 | 537 | ||
| 506 | int omap_hwmod_init(struct omap_hwmod **ohs); | 538 | int omap_hwmod_init(struct omap_hwmod **ohs); |
| 507 | int omap_hwmod_register(struct omap_hwmod *oh); | ||
| 508 | int omap_hwmod_unregister(struct omap_hwmod *oh); | ||
| 509 | struct omap_hwmod *omap_hwmod_lookup(const char *name); | 539 | struct omap_hwmod *omap_hwmod_lookup(const char *name); |
| 510 | int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), | 540 | int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), |
| 511 | void *data); | 541 | void *data); |
| 512 | int omap_hwmod_late_init(u8 skip_setup_idle); | 542 | int omap_hwmod_late_init(void); |
| 513 | 543 | ||
| 514 | int omap_hwmod_enable(struct omap_hwmod *oh); | 544 | int omap_hwmod_enable(struct omap_hwmod *oh); |
| 515 | int _omap_hwmod_enable(struct omap_hwmod *oh); | 545 | int _omap_hwmod_enable(struct omap_hwmod *oh); |
| @@ -556,6 +586,9 @@ int omap_hwmod_for_each_by_class(const char *classname, | |||
| 556 | void *user), | 586 | void *user), |
| 557 | void *user); | 587 | void *user); |
| 558 | 588 | ||
| 589 | int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state); | ||
| 590 | u32 omap_hwmod_get_context_loss_count(struct omap_hwmod *oh); | ||
| 591 | |||
| 559 | /* | 592 | /* |
| 560 | * Chip variant-specific hwmod init routines - XXX should be converted | 593 | * Chip variant-specific hwmod init routines - XXX should be converted |
| 561 | * to use initcalls once the initial boot ordering is straightened out | 594 | * to use initcalls once the initial boot ordering is straightened out |
diff --git a/arch/arm/plat-omap/include/plat/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h index ab77442e42ab..2fdf8c80d390 100644 --- a/arch/arm/plat-omap/include/plat/prcm.h +++ b/arch/arm/plat-omap/include/plat/prcm.h | |||
| @@ -18,6 +18,10 @@ | |||
| 18 | * You should have received a copy of the GNU General Public License | 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software | 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | * | ||
| 22 | * XXX This file is deprecated. The PRCM is an OMAP2+-only subsystem, | ||
| 23 | * so this file doesn't belong in plat-omap/include/plat. Please | ||
| 24 | * do not add anything new to this file. | ||
| 21 | */ | 25 | */ |
| 22 | 26 | ||
| 23 | #ifndef __ASM_ARM_ARCH_OMAP_PRCM_H | 27 | #ifndef __ASM_ARM_ARCH_OMAP_PRCM_H |
| @@ -28,22 +32,6 @@ void omap_prcm_arch_reset(char mode, const char *cmd); | |||
| 28 | int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest, | 32 | int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest, |
| 29 | const char *name); | 33 | const char *name); |
| 30 | 34 | ||
| 31 | #define START_PADCONF_SAVE 0x2 | ||
| 32 | #define PADCONF_SAVE_DONE 0x1 | ||
| 33 | |||
| 34 | void omap3_prcm_save_context(void); | ||
| 35 | void omap3_prcm_restore_context(void); | ||
| 36 | |||
| 37 | u32 prm_read_mod_reg(s16 module, u16 idx); | ||
| 38 | void prm_write_mod_reg(u32 val, s16 module, u16 idx); | ||
| 39 | u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); | ||
| 40 | u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask); | ||
| 41 | u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask); | ||
| 42 | u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg); | ||
| 43 | u32 cm_read_mod_reg(s16 module, u16 idx); | ||
| 44 | void cm_write_mod_reg(u32 val, s16 module, u16 idx); | ||
| 45 | u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); | ||
| 46 | |||
| 47 | #endif | 35 | #endif |
| 48 | 36 | ||
| 49 | 37 | ||
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h index 19145f5c32ba..cec5d56db2eb 100644 --- a/arch/arm/plat-omap/include/plat/serial.h +++ b/arch/arm/plat-omap/include/plat/serial.h | |||
| @@ -93,9 +93,12 @@ | |||
| 93 | }) | 93 | }) |
| 94 | 94 | ||
| 95 | #ifndef __ASSEMBLER__ | 95 | #ifndef __ASSEMBLER__ |
| 96 | |||
| 97 | struct omap_board_data; | ||
| 98 | |||
| 96 | extern void __init omap_serial_early_init(void); | 99 | extern void __init omap_serial_early_init(void); |
| 97 | extern void omap_serial_init(void); | 100 | extern void omap_serial_init(void); |
| 98 | extern void omap_serial_init_port(int port); | 101 | extern void omap_serial_init_port(struct omap_board_data *bdata); |
| 99 | extern int omap_uart_can_sleep(void); | 102 | extern int omap_uart_can_sleep(void); |
| 100 | extern void omap_uart_check_wakeup(void); | 103 | extern void omap_uart_check_wakeup(void); |
| 101 | extern void omap_uart_prepare_suspend(void); | 104 | extern void omap_uart_prepare_suspend(void); |
diff --git a/arch/arm/plat-omap/include/plat/smartreflex.h b/arch/arm/plat-omap/include/plat/smartreflex.h new file mode 100644 index 000000000000..6568c885f37a --- /dev/null +++ b/arch/arm/plat-omap/include/plat/smartreflex.h | |||
| @@ -0,0 +1,245 @@ | |||
| 1 | /* | ||
| 2 | * OMAP Smartreflex Defines and Routines | ||
| 3 | * | ||
| 4 | * Author: Thara Gopinath <thara@ti.com> | ||
| 5 | * | ||
| 6 | * Copyright (C) 2010 Texas Instruments, Inc. | ||
| 7 | * Thara Gopinath <thara@ti.com> | ||
| 8 | * | ||
| 9 | * Copyright (C) 2008 Nokia Corporation | ||
| 10 | * Kalle Jokiniemi | ||
| 11 | * | ||
| 12 | * Copyright (C) 2007 Texas Instruments, Inc. | ||
| 13 | * Lesly A M <x0080970@ti.com> | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License version 2 as | ||
| 17 | * published by the Free Software Foundation. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef __ASM_ARM_OMAP_SMARTREFLEX_H | ||
| 21 | #define __ASM_ARM_OMAP_SMARTREFLEX_H | ||
| 22 | |||
| 23 | #include <linux/platform_device.h> | ||
| 24 | #include <plat/voltage.h> | ||
| 25 | |||
| 26 | /* | ||
| 27 | * Different Smartreflex IPs version. The v1 is the 65nm version used in | ||
| 28 | * OMAP3430. The v2 is the update for the 45nm version of the IP | ||
| 29 | * used in OMAP3630 and OMAP4430 | ||
| 30 | */ | ||
| 31 | #define SR_TYPE_V1 1 | ||
| 32 | #define SR_TYPE_V2 2 | ||
| 33 | |||
| 34 | /* SMART REFLEX REG ADDRESS OFFSET */ | ||
| 35 | #define SRCONFIG 0x00 | ||
| 36 | #define SRSTATUS 0x04 | ||
| 37 | #define SENVAL 0x08 | ||
| 38 | #define SENMIN 0x0C | ||
| 39 | #define SENMAX 0x10 | ||
| 40 | #define SENAVG 0x14 | ||
| 41 | #define AVGWEIGHT 0x18 | ||
| 42 | #define NVALUERECIPROCAL 0x1c | ||
| 43 | #define SENERROR_V1 0x20 | ||
| 44 | #define ERRCONFIG_V1 0x24 | ||
| 45 | #define IRQ_EOI 0x20 | ||
| 46 | #define IRQSTATUS_RAW 0x24 | ||
| 47 | #define IRQSTATUS 0x28 | ||
| 48 | #define IRQENABLE_SET 0x2C | ||
| 49 | #define IRQENABLE_CLR 0x30 | ||
| 50 | #define SENERROR_V2 0x34 | ||
| 51 | #define ERRCONFIG_V2 0x38 | ||
| 52 | |||
| 53 | /* Bit/Shift Positions */ | ||
| 54 | |||
| 55 | /* SRCONFIG */ | ||
| 56 | #define SRCONFIG_ACCUMDATA_SHIFT 22 | ||
| 57 | #define SRCONFIG_SRCLKLENGTH_SHIFT 12 | ||
| 58 | #define SRCONFIG_SENNENABLE_V1_SHIFT 5 | ||
| 59 | #define SRCONFIG_SENPENABLE_V1_SHIFT 3 | ||
| 60 | #define SRCONFIG_SENNENABLE_V2_SHIFT 1 | ||
| 61 | #define SRCONFIG_SENPENABLE_V2_SHIFT 0 | ||
| 62 | #define SRCONFIG_CLKCTRL_SHIFT 0 | ||
| 63 | |||
| 64 | #define SRCONFIG_ACCUMDATA_MASK (0x3ff << 22) | ||
| 65 | |||
| 66 | #define SRCONFIG_SRENABLE BIT(11) | ||
| 67 | #define SRCONFIG_SENENABLE BIT(10) | ||
| 68 | #define SRCONFIG_ERRGEN_EN BIT(9) | ||
| 69 | #define SRCONFIG_MINMAXAVG_EN BIT(8) | ||
| 70 | #define SRCONFIG_DELAYCTRL BIT(2) | ||
| 71 | |||
| 72 | /* AVGWEIGHT */ | ||
| 73 | #define AVGWEIGHT_SENPAVGWEIGHT_SHIFT 2 | ||
| 74 | #define AVGWEIGHT_SENNAVGWEIGHT_SHIFT 0 | ||
| 75 | |||
| 76 | /* NVALUERECIPROCAL */ | ||
| 77 | #define NVALUERECIPROCAL_SENPGAIN_SHIFT 20 | ||
| 78 | #define NVALUERECIPROCAL_SENNGAIN_SHIFT 16 | ||
| 79 | #define NVALUERECIPROCAL_RNSENP_SHIFT 8 | ||
| 80 | #define NVALUERECIPROCAL_RNSENN_SHIFT 0 | ||
| 81 | |||
| 82 | /* ERRCONFIG */ | ||
| 83 | #define ERRCONFIG_ERRWEIGHT_SHIFT 16 | ||
| 84 | #define ERRCONFIG_ERRMAXLIMIT_SHIFT 8 | ||
| 85 | #define ERRCONFIG_ERRMINLIMIT_SHIFT 0 | ||
| 86 | |||
| 87 | #define SR_ERRWEIGHT_MASK (0x07 << 16) | ||
| 88 | #define SR_ERRMAXLIMIT_MASK (0xff << 8) | ||
| 89 | #define SR_ERRMINLIMIT_MASK (0xff << 0) | ||
| 90 | |||
| 91 | #define ERRCONFIG_VPBOUNDINTEN_V1 BIT(31) | ||
| 92 | #define ERRCONFIG_VPBOUNDINTST_V1 BIT(30) | ||
| 93 | #define ERRCONFIG_MCUACCUMINTEN BIT(29) | ||
| 94 | #define ERRCONFIG_MCUACCUMINTST BIT(28) | ||
| 95 | #define ERRCONFIG_MCUVALIDINTEN BIT(27) | ||
| 96 | #define ERRCONFIG_MCUVALIDINTST BIT(26) | ||
| 97 | #define ERRCONFIG_MCUBOUNDINTEN BIT(25) | ||
| 98 | #define ERRCONFIG_MCUBOUNDINTST BIT(24) | ||
| 99 | #define ERRCONFIG_MCUDISACKINTEN BIT(23) | ||
| 100 | #define ERRCONFIG_VPBOUNDINTST_V2 BIT(23) | ||
| 101 | #define ERRCONFIG_MCUDISACKINTST BIT(22) | ||
| 102 | #define ERRCONFIG_VPBOUNDINTEN_V2 BIT(22) | ||
| 103 | |||
| 104 | #define ERRCONFIG_STATUS_V1_MASK (ERRCONFIG_VPBOUNDINTST_V1 | \ | ||
| 105 | ERRCONFIG_MCUACCUMINTST | \ | ||
| 106 | ERRCONFIG_MCUVALIDINTST | \ | ||
| 107 | ERRCONFIG_MCUBOUNDINTST | \ | ||
| 108 | ERRCONFIG_MCUDISACKINTST) | ||
| 109 | /* IRQSTATUS */ | ||
| 110 | #define IRQSTATUS_MCUACCUMINT BIT(3) | ||
| 111 | #define IRQSTATUS_MCVALIDINT BIT(2) | ||
| 112 | #define IRQSTATUS_MCBOUNDSINT BIT(1) | ||
| 113 | #define IRQSTATUS_MCUDISABLEACKINT BIT(0) | ||
| 114 | |||
| 115 | /* IRQENABLE_SET and IRQENABLE_CLEAR */ | ||
| 116 | #define IRQENABLE_MCUACCUMINT BIT(3) | ||
| 117 | #define IRQENABLE_MCUVALIDINT BIT(2) | ||
| 118 | #define IRQENABLE_MCUBOUNDSINT BIT(1) | ||
| 119 | #define IRQENABLE_MCUDISABLEACKINT BIT(0) | ||
| 120 | |||
| 121 | /* Common Bit values */ | ||
| 122 | |||
| 123 | #define SRCLKLENGTH_12MHZ_SYSCLK 0x3c | ||
| 124 | #define SRCLKLENGTH_13MHZ_SYSCLK 0x41 | ||
| 125 | #define SRCLKLENGTH_19MHZ_SYSCLK 0x60 | ||
| 126 | #define SRCLKLENGTH_26MHZ_SYSCLK 0x82 | ||
| 127 | #define SRCLKLENGTH_38MHZ_SYSCLK 0xC0 | ||
| 128 | |||
| 129 | /* | ||
| 130 | * 3430 specific values. Maybe these should be passed from board file or | ||
| 131 | * pmic structures. | ||
| 132 | */ | ||
| 133 | #define OMAP3430_SR_ACCUMDATA 0x1f4 | ||
| 134 | |||
| 135 | #define OMAP3430_SR1_SENPAVGWEIGHT 0x03 | ||
| 136 | #define OMAP3430_SR1_SENNAVGWEIGHT 0x03 | ||
| 137 | |||
| 138 | #define OMAP3430_SR2_SENPAVGWEIGHT 0x01 | ||
| 139 | #define OMAP3430_SR2_SENNAVGWEIGHT 0x01 | ||
| 140 | |||
| 141 | #define OMAP3430_SR_ERRWEIGHT 0x04 | ||
| 142 | #define OMAP3430_SR_ERRMAXLIMIT 0x02 | ||
| 143 | |||
| 144 | /** | ||
| 145 | * struct omap_sr_pmic_data - Strucutre to be populated by pmic code to pass | ||
| 146 | * pmic specific info to smartreflex driver | ||
| 147 | * | ||
| 148 | * @sr_pmic_init: API to initialize smartreflex on the PMIC side. | ||
| 149 | */ | ||
| 150 | struct omap_sr_pmic_data { | ||
| 151 | void (*sr_pmic_init) (void); | ||
| 152 | }; | ||
| 153 | |||
| 154 | #ifdef CONFIG_OMAP_SMARTREFLEX | ||
| 155 | /* | ||
| 156 | * The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR. | ||
| 157 | * The smartreflex class driver should pass the class type. | ||
| 158 | * Should be used to populate the class_type field of the | ||
| 159 | * omap_smartreflex_class_data structure. | ||
| 160 | */ | ||
| 161 | #define SR_CLASS1 0x1 | ||
| 162 | #define SR_CLASS2 0x2 | ||
| 163 | #define SR_CLASS3 0x3 | ||
| 164 | |||
| 165 | /** | ||
| 166 | * struct omap_sr_class_data - Smartreflex class driver info | ||
| 167 | * | ||
| 168 | * @enable: API to enable a particular class smaartreflex. | ||
| 169 | * @disable: API to disable a particular class smartreflex. | ||
| 170 | * @configure: API to configure a particular class smartreflex. | ||
| 171 | * @notify: API to notify the class driver about an event in SR. | ||
| 172 | * Not needed for class3. | ||
| 173 | * @notify_flags: specify the events to be notified to the class driver | ||
| 174 | * @class_type: specify which smartreflex class. | ||
| 175 | * Can be used by the SR driver to take any class | ||
| 176 | * based decisions. | ||
| 177 | */ | ||
| 178 | struct omap_sr_class_data { | ||
| 179 | int (*enable)(struct voltagedomain *voltdm); | ||
| 180 | int (*disable)(struct voltagedomain *voltdm, int is_volt_reset); | ||
| 181 | int (*configure)(struct voltagedomain *voltdm); | ||
| 182 | int (*notify)(struct voltagedomain *voltdm, u32 status); | ||
| 183 | u8 notify_flags; | ||
| 184 | u8 class_type; | ||
| 185 | }; | ||
| 186 | |||
| 187 | /** | ||
| 188 | * struct omap_sr_nvalue_table - Smartreflex n-target value info | ||
| 189 | * | ||
| 190 | * @efuse_offs: The offset of the efuse where n-target values are stored. | ||
| 191 | * @nvalue: The n-target value. | ||
| 192 | */ | ||
| 193 | struct omap_sr_nvalue_table { | ||
| 194 | u32 efuse_offs; | ||
| 195 | u32 nvalue; | ||
| 196 | }; | ||
| 197 | |||
| 198 | /** | ||
| 199 | * struct omap_sr_data - Smartreflex platform data. | ||
| 200 | * | ||
| 201 | * @ip_type: Smartreflex IP type. | ||
| 202 | * @senp_mod: SENPENABLE value for the sr | ||
| 203 | * @senn_mod: SENNENABLE value for sr | ||
| 204 | * @nvalue_count: Number of distinct nvalues in the nvalue table | ||
| 205 | * @enable_on_init: whether this sr module needs to enabled at | ||
| 206 | * boot up or not. | ||
| 207 | * @nvalue_table: table containing the efuse offsets and nvalues | ||
| 208 | * corresponding to them. | ||
| 209 | * @voltdm: Pointer to the voltage domain associated with the SR | ||
| 210 | */ | ||
| 211 | struct omap_sr_data { | ||
| 212 | int ip_type; | ||
| 213 | u32 senp_mod; | ||
| 214 | u32 senn_mod; | ||
| 215 | int nvalue_count; | ||
| 216 | bool enable_on_init; | ||
| 217 | struct omap_sr_nvalue_table *nvalue_table; | ||
| 218 | struct voltagedomain *voltdm; | ||
| 219 | }; | ||
| 220 | |||
| 221 | /* Smartreflex module enable/disable interface */ | ||
| 222 | void omap_sr_enable(struct voltagedomain *voltdm); | ||
| 223 | void omap_sr_disable(struct voltagedomain *voltdm); | ||
| 224 | void omap_sr_disable_reset_volt(struct voltagedomain *voltdm); | ||
| 225 | |||
| 226 | /* API to register the pmic specific data with the smartreflex driver. */ | ||
| 227 | void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data); | ||
| 228 | |||
| 229 | /* Smartreflex driver hooks to be called from Smartreflex class driver */ | ||
| 230 | int sr_enable(struct voltagedomain *voltdm, unsigned long volt); | ||
| 231 | void sr_disable(struct voltagedomain *voltdm); | ||
| 232 | int sr_configure_errgen(struct voltagedomain *voltdm); | ||
| 233 | int sr_configure_minmax(struct voltagedomain *voltdm); | ||
| 234 | |||
| 235 | /* API to register the smartreflex class driver with the smartreflex driver */ | ||
| 236 | int sr_register_class(struct omap_sr_class_data *class_data); | ||
| 237 | #else | ||
| 238 | static inline void omap_sr_enable(struct voltagedomain *voltdm) {} | ||
| 239 | static inline void omap_sr_disable(struct voltagedomain *voltdm) {} | ||
| 240 | static inline void omap_sr_disable_reset_volt( | ||
| 241 | struct voltagedomain *voltdm) {} | ||
| 242 | static inline void omap_sr_register_pmic( | ||
| 243 | struct omap_sr_pmic_data *pmic_data) {} | ||
| 244 | #endif | ||
| 245 | #endif | ||
diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h index ecd6a488c497..7a10257909ef 100644 --- a/arch/arm/plat-omap/include/plat/smp.h +++ b/arch/arm/plat-omap/include/plat/smp.h | |||
| @@ -18,7 +18,6 @@ | |||
| 18 | #define OMAP_ARCH_SMP_H | 18 | #define OMAP_ARCH_SMP_H |
| 19 | 19 | ||
| 20 | #include <asm/hardware/gic.h> | 20 | #include <asm/hardware/gic.h> |
| 21 | #include <asm/smp_mpidr.h> | ||
| 22 | 21 | ||
| 23 | /* Needed for secondary core boot */ | 22 | /* Needed for secondary core boot */ |
| 24 | extern void omap_secondary_startup(void); | 23 | extern void omap_secondary_startup(void); |
| @@ -29,9 +28,9 @@ extern u32 omap_read_auxcoreboot0(void); | |||
| 29 | /* | 28 | /* |
| 30 | * We use Soft IRQ1 as the IPI | 29 | * We use Soft IRQ1 as the IPI |
| 31 | */ | 30 | */ |
| 32 | static inline void smp_cross_call(const struct cpumask *mask) | 31 | static inline void smp_cross_call(const struct cpumask *mask, int ipi) |
| 33 | { | 32 | { |
| 34 | gic_raise_softirq(mask, 1); | 33 | gic_raise_softirq(mask, ipi); |
| 35 | } | 34 | } |
| 36 | 35 | ||
| 37 | #endif | 36 | #endif |
diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h index 5905100b29a1..9967d5e855c7 100644 --- a/arch/arm/plat-omap/include/plat/sram.h +++ b/arch/arm/plat-omap/include/plat/sram.h | |||
| @@ -11,6 +11,7 @@ | |||
| 11 | #ifndef __ARCH_ARM_OMAP_SRAM_H | 11 | #ifndef __ARCH_ARM_OMAP_SRAM_H |
| 12 | #define __ARCH_ARM_OMAP_SRAM_H | 12 | #define __ARCH_ARM_OMAP_SRAM_H |
| 13 | 13 | ||
| 14 | #ifndef __ASSEMBLY__ | ||
| 14 | extern void * omap_sram_push(void * start, unsigned long size); | 15 | extern void * omap_sram_push(void * start, unsigned long size); |
| 15 | extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl); | 16 | extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl); |
| 16 | 17 | ||
| @@ -74,4 +75,14 @@ extern void omap_push_sram_idle(void); | |||
| 74 | static inline void omap_push_sram_idle(void) {} | 75 | static inline void omap_push_sram_idle(void) {} |
| 75 | #endif /* CONFIG_PM */ | 76 | #endif /* CONFIG_PM */ |
| 76 | 77 | ||
| 78 | #endif /* __ASSEMBLY__ */ | ||
| 79 | |||
| 80 | /* | ||
| 81 | * OMAP2+: define the SRAM PA addresses. | ||
| 82 | * Used by the SRAM management code and the idle sleep code. | ||
| 83 | */ | ||
| 84 | #define OMAP2_SRAM_PA 0x40200000 | ||
| 85 | #define OMAP3_SRAM_PA 0x40200000 | ||
| 86 | #define OMAP4_SRAM_PA 0x40300000 | ||
| 87 | |||
| 77 | #endif | 88 | #endif |
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h index 9036e374e0ac..ad98b85cae21 100644 --- a/arch/arm/plat-omap/include/plat/uncompress.h +++ b/arch/arm/plat-omap/include/plat/uncompress.h | |||
| @@ -145,8 +145,11 @@ static inline void __arch_decomp_setup(unsigned long arch_id) | |||
| 145 | /* omap3 based boards using UART3 */ | 145 | /* omap3 based boards using UART3 */ |
| 146 | DEBUG_LL_OMAP3(3, cm_t35); | 146 | DEBUG_LL_OMAP3(3, cm_t35); |
| 147 | DEBUG_LL_OMAP3(3, cm_t3517); | 147 | DEBUG_LL_OMAP3(3, cm_t3517); |
| 148 | DEBUG_LL_OMAP3(3, craneboard); | ||
| 149 | DEBUG_LL_OMAP3(3, devkit8000); | ||
| 148 | DEBUG_LL_OMAP3(3, igep0020); | 150 | DEBUG_LL_OMAP3(3, igep0020); |
| 149 | DEBUG_LL_OMAP3(3, igep0030); | 151 | DEBUG_LL_OMAP3(3, igep0030); |
| 152 | DEBUG_LL_OMAP3(3, nokia_rm680); | ||
| 150 | DEBUG_LL_OMAP3(3, nokia_rx51); | 153 | DEBUG_LL_OMAP3(3, nokia_rx51); |
| 151 | DEBUG_LL_OMAP3(3, omap3517evm); | 154 | DEBUG_LL_OMAP3(3, omap3517evm); |
| 152 | DEBUG_LL_OMAP3(3, omap3_beagle); | 155 | DEBUG_LL_OMAP3(3, omap3_beagle); |
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h index 59c7fe731f28..450a332f1009 100644 --- a/arch/arm/plat-omap/include/plat/usb.h +++ b/arch/arm/plat-omap/include/plat/usb.h | |||
| @@ -11,6 +11,7 @@ enum ehci_hcd_omap_mode { | |||
| 11 | EHCI_HCD_OMAP_MODE_UNKNOWN, | 11 | EHCI_HCD_OMAP_MODE_UNKNOWN, |
| 12 | EHCI_HCD_OMAP_MODE_PHY, | 12 | EHCI_HCD_OMAP_MODE_PHY, |
| 13 | EHCI_HCD_OMAP_MODE_TLL, | 13 | EHCI_HCD_OMAP_MODE_TLL, |
| 14 | EHCI_HCD_OMAP_MODE_HSIC, | ||
| 14 | }; | 15 | }; |
| 15 | 16 | ||
| 16 | enum ohci_omap3_port_mode { | 17 | enum ohci_omap3_port_mode { |
| @@ -69,6 +70,10 @@ struct omap_musb_board_data { | |||
| 69 | u8 mode; | 70 | u8 mode; |
| 70 | u16 power; | 71 | u16 power; |
| 71 | unsigned extvbus:1; | 72 | unsigned extvbus:1; |
| 73 | void (*set_phy_power)(u8 on); | ||
| 74 | void (*clear_irq)(void); | ||
| 75 | void (*set_mode)(u8 mode); | ||
| 76 | void (*reset)(void); | ||
| 72 | }; | 77 | }; |
| 73 | 78 | ||
| 74 | enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI}; | 79 | enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI}; |
| @@ -79,6 +84,11 @@ extern void usb_ehci_init(const struct ehci_hcd_omap_platform_data *pdata); | |||
| 79 | 84 | ||
| 80 | extern void usb_ohci_init(const struct ohci_hcd_omap_platform_data *pdata); | 85 | extern void usb_ohci_init(const struct ohci_hcd_omap_platform_data *pdata); |
| 81 | 86 | ||
| 87 | extern int omap4430_phy_power(struct device *dev, int ID, int on); | ||
| 88 | extern int omap4430_phy_set_clk(struct device *dev, int on); | ||
| 89 | extern int omap4430_phy_init(struct device *dev); | ||
| 90 | extern int omap4430_phy_exit(struct device *dev); | ||
| 91 | |||
| 82 | #endif | 92 | #endif |
| 83 | 93 | ||
| 84 | 94 | ||
diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h new file mode 100644 index 000000000000..0ff123399f3b --- /dev/null +++ b/arch/arm/plat-omap/include/plat/voltage.h | |||
| @@ -0,0 +1,146 @@ | |||
| 1 | /* | ||
| 2 | * OMAP Voltage Management Routines | ||
| 3 | * | ||
| 4 | * Author: Thara Gopinath <thara@ti.com> | ||
| 5 | * | ||
| 6 | * Copyright (C) 2009 Texas Instruments, Inc. | ||
| 7 | * Thara Gopinath <thara@ti.com> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ARCH_ARM_MACH_OMAP2_VOLTAGE_H | ||
| 15 | #define __ARCH_ARM_MACH_OMAP2_VOLTAGE_H | ||
| 16 | |||
| 17 | #define VOLTSCALE_VPFORCEUPDATE 1 | ||
| 18 | #define VOLTSCALE_VCBYPASS 2 | ||
| 19 | |||
| 20 | /* | ||
| 21 | * OMAP3 GENERIC setup times. Revisit to see if these needs to be | ||
| 22 | * passed from board or PMIC file | ||
| 23 | */ | ||
| 24 | #define OMAP3_CLKSETUP 0xff | ||
| 25 | #define OMAP3_VOLTOFFSET 0xff | ||
| 26 | #define OMAP3_VOLTSETUP2 0xff | ||
| 27 | |||
| 28 | /* Voltage value defines */ | ||
| 29 | #define OMAP3430_VDD_MPU_OPP1_UV 975000 | ||
| 30 | #define OMAP3430_VDD_MPU_OPP2_UV 1075000 | ||
| 31 | #define OMAP3430_VDD_MPU_OPP3_UV 1200000 | ||
| 32 | #define OMAP3430_VDD_MPU_OPP4_UV 1270000 | ||
| 33 | #define OMAP3430_VDD_MPU_OPP5_UV 1350000 | ||
| 34 | |||
| 35 | #define OMAP3430_VDD_CORE_OPP1_UV 975000 | ||
| 36 | #define OMAP3430_VDD_CORE_OPP2_UV 1050000 | ||
| 37 | #define OMAP3430_VDD_CORE_OPP3_UV 1150000 | ||
| 38 | |||
| 39 | #define OMAP3630_VDD_MPU_OPP50_UV 1012500 | ||
| 40 | #define OMAP3630_VDD_MPU_OPP100_UV 1200000 | ||
| 41 | #define OMAP3630_VDD_MPU_OPP120_UV 1325000 | ||
| 42 | #define OMAP3630_VDD_MPU_OPP1G_UV 1375000 | ||
| 43 | |||
| 44 | #define OMAP3630_VDD_CORE_OPP50_UV 1000000 | ||
| 45 | #define OMAP3630_VDD_CORE_OPP100_UV 1200000 | ||
| 46 | |||
| 47 | #define OMAP4430_VDD_MPU_OPP50_UV 930000 | ||
| 48 | #define OMAP4430_VDD_MPU_OPP100_UV 1100000 | ||
| 49 | #define OMAP4430_VDD_MPU_OPPTURBO_UV 1260000 | ||
| 50 | #define OMAP4430_VDD_MPU_OPPNITRO_UV 1350000 | ||
| 51 | |||
| 52 | #define OMAP4430_VDD_IVA_OPP50_UV 930000 | ||
| 53 | #define OMAP4430_VDD_IVA_OPP100_UV 1100000 | ||
| 54 | #define OMAP4430_VDD_IVA_OPPTURBO_UV 1260000 | ||
| 55 | |||
| 56 | #define OMAP4430_VDD_CORE_OPP50_UV 930000 | ||
| 57 | #define OMAP4430_VDD_CORE_OPP100_UV 1100000 | ||
| 58 | |||
| 59 | /** | ||
| 60 | * struct voltagedomain - omap voltage domain global structure. | ||
| 61 | * @name: Name of the voltage domain which can be used as a unique | ||
| 62 | * identifier. | ||
| 63 | */ | ||
| 64 | struct voltagedomain { | ||
| 65 | char *name; | ||
| 66 | }; | ||
| 67 | |||
| 68 | /* API to get the voltagedomain pointer */ | ||
| 69 | struct voltagedomain *omap_voltage_domain_lookup(char *name); | ||
| 70 | |||
| 71 | /** | ||
| 72 | * struct omap_volt_data - Omap voltage specific data. | ||
| 73 | * @voltage_nominal: The possible voltage value in uV | ||
| 74 | * @sr_efuse_offs: The offset of the efuse register(from system | ||
| 75 | * control module base address) from where to read | ||
| 76 | * the n-target value for the smartreflex module. | ||
| 77 | * @sr_errminlimit: Error min limit value for smartreflex. This value | ||
| 78 | * differs at differnet opp and thus is linked | ||
| 79 | * with voltage. | ||
| 80 | * @vp_errorgain: Error gain value for the voltage processor. This | ||
| 81 | * field also differs according to the voltage/opp. | ||
| 82 | */ | ||
| 83 | struct omap_volt_data { | ||
| 84 | u32 volt_nominal; | ||
| 85 | u32 sr_efuse_offs; | ||
| 86 | u8 sr_errminlimit; | ||
| 87 | u8 vp_errgain; | ||
| 88 | }; | ||
| 89 | |||
| 90 | /** | ||
| 91 | * struct omap_volt_pmic_info - PMIC specific data required by voltage driver. | ||
| 92 | * @slew_rate: PMIC slew rate (in uv/us) | ||
| 93 | * @step_size: PMIC voltage step size (in uv) | ||
| 94 | * @vsel_to_uv: PMIC API to convert vsel value to actual voltage in uV. | ||
| 95 | * @uv_to_vsel: PMIC API to convert voltage in uV to vsel value. | ||
| 96 | */ | ||
| 97 | struct omap_volt_pmic_info { | ||
| 98 | int slew_rate; | ||
| 99 | int step_size; | ||
| 100 | u32 on_volt; | ||
| 101 | u32 onlp_volt; | ||
| 102 | u32 ret_volt; | ||
| 103 | u32 off_volt; | ||
| 104 | u16 volt_setup_time; | ||
| 105 | u8 vp_erroroffset; | ||
| 106 | u8 vp_vstepmin; | ||
| 107 | u8 vp_vstepmax; | ||
| 108 | u8 vp_vddmin; | ||
| 109 | u8 vp_vddmax; | ||
| 110 | u8 vp_timeout_us; | ||
| 111 | u8 i2c_slave_addr; | ||
| 112 | u8 pmic_reg; | ||
| 113 | unsigned long (*vsel_to_uv) (const u8 vsel); | ||
| 114 | u8 (*uv_to_vsel) (unsigned long uV); | ||
| 115 | }; | ||
| 116 | |||
| 117 | unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm); | ||
| 118 | void omap_vp_enable(struct voltagedomain *voltdm); | ||
| 119 | void omap_vp_disable(struct voltagedomain *voltdm); | ||
| 120 | int omap_voltage_scale_vdd(struct voltagedomain *voltdm, | ||
| 121 | unsigned long target_volt); | ||
| 122 | void omap_voltage_reset(struct voltagedomain *voltdm); | ||
| 123 | void omap_voltage_get_volttable(struct voltagedomain *voltdm, | ||
| 124 | struct omap_volt_data **volt_data); | ||
| 125 | struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm, | ||
| 126 | unsigned long volt); | ||
| 127 | unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm); | ||
| 128 | struct dentry *omap_voltage_get_dbgdir(struct voltagedomain *voltdm); | ||
| 129 | #ifdef CONFIG_PM | ||
| 130 | int omap_voltage_register_pmic(struct voltagedomain *voltdm, | ||
| 131 | struct omap_volt_pmic_info *pmic_info); | ||
| 132 | void omap_change_voltscale_method(struct voltagedomain *voltdm, | ||
| 133 | int voltscale_method); | ||
| 134 | int omap_voltage_late_init(void); | ||
| 135 | #else | ||
| 136 | static inline int omap_voltage_register_pmic(struct voltagedomain *voltdm, | ||
| 137 | struct omap_volt_pmic_info *pmic_info) {} | ||
| 138 | static inline void omap_change_voltscale_method(struct voltagedomain *voltdm, | ||
| 139 | int voltscale_method) {} | ||
| 140 | static inline int omap_voltage_late_init(void) | ||
| 141 | { | ||
| 142 | return -EINVAL; | ||
| 143 | } | ||
| 144 | #endif | ||
| 145 | |||
| 146 | #endif | ||
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c index b0078cf96281..f1295fafcd31 100644 --- a/arch/arm/plat-omap/io.c +++ b/arch/arm/plat-omap/io.c | |||
| @@ -136,61 +136,3 @@ void omap_iounmap(volatile void __iomem *addr) | |||
| 136 | __iounmap(addr); | 136 | __iounmap(addr); |
| 137 | } | 137 | } |
| 138 | EXPORT_SYMBOL(omap_iounmap); | 138 | EXPORT_SYMBOL(omap_iounmap); |
| 139 | |||
| 140 | /* | ||
| 141 | * NOTE: Please use ioremap + __raw_read/write where possible instead of these | ||
| 142 | */ | ||
| 143 | |||
| 144 | u8 omap_readb(u32 pa) | ||
| 145 | { | ||
| 146 | if (cpu_class_is_omap1()) | ||
| 147 | return __raw_readb(OMAP1_IO_ADDRESS(pa)); | ||
| 148 | else | ||
| 149 | return __raw_readb(OMAP2_L4_IO_ADDRESS(pa)); | ||
| 150 | } | ||
| 151 | EXPORT_SYMBOL(omap_readb); | ||
| 152 | |||
| 153 | u16 omap_readw(u32 pa) | ||
| 154 | { | ||
| 155 | if (cpu_class_is_omap1()) | ||
| 156 | return __raw_readw(OMAP1_IO_ADDRESS(pa)); | ||
| 157 | else | ||
| 158 | return __raw_readw(OMAP2_L4_IO_ADDRESS(pa)); | ||
| 159 | } | ||
| 160 | EXPORT_SYMBOL(omap_readw); | ||
| 161 | |||
| 162 | u32 omap_readl(u32 pa) | ||
| 163 | { | ||
| 164 | if (cpu_class_is_omap1()) | ||
| 165 | return __raw_readl(OMAP1_IO_ADDRESS(pa)); | ||
| 166 | else | ||
| 167 | return __raw_readl(OMAP2_L4_IO_ADDRESS(pa)); | ||
| 168 | } | ||
| 169 | EXPORT_SYMBOL(omap_readl); | ||
| 170 | |||
| 171 | void omap_writeb(u8 v, u32 pa) | ||
| 172 | { | ||
| 173 | if (cpu_class_is_omap1()) | ||
| 174 | __raw_writeb(v, OMAP1_IO_ADDRESS(pa)); | ||
| 175 | else | ||
| 176 | __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa)); | ||
| 177 | } | ||
| 178 | EXPORT_SYMBOL(omap_writeb); | ||
| 179 | |||
| 180 | void omap_writew(u16 v, u32 pa) | ||
| 181 | { | ||
| 182 | if (cpu_class_is_omap1()) | ||
| 183 | __raw_writew(v, OMAP1_IO_ADDRESS(pa)); | ||
| 184 | else | ||
| 185 | __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa)); | ||
| 186 | } | ||
| 187 | EXPORT_SYMBOL(omap_writew); | ||
| 188 | |||
| 189 | void omap_writel(u32 v, u32 pa) | ||
| 190 | { | ||
| 191 | if (cpu_class_is_omap1()) | ||
| 192 | __raw_writel(v, OMAP1_IO_ADDRESS(pa)); | ||
| 193 | else | ||
| 194 | __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa)); | ||
| 195 | } | ||
| 196 | EXPORT_SYMBOL(omap_writel); | ||
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c index 6cd151b31bc5..b1107c08da56 100644 --- a/arch/arm/plat-omap/iommu.c +++ b/arch/arm/plat-omap/iommu.c | |||
| @@ -830,6 +830,28 @@ static int device_match_by_alias(struct device *dev, void *data) | |||
| 830 | } | 830 | } |
| 831 | 831 | ||
| 832 | /** | 832 | /** |
| 833 | * iommu_set_da_range - Set a valid device address range | ||
| 834 | * @obj: target iommu | ||
| 835 | * @start Start of valid range | ||
| 836 | * @end End of valid range | ||
| 837 | **/ | ||
| 838 | int iommu_set_da_range(struct iommu *obj, u32 start, u32 end) | ||
| 839 | { | ||
| 840 | |||
| 841 | if (!obj) | ||
| 842 | return -EFAULT; | ||
| 843 | |||
| 844 | if (end < start || !PAGE_ALIGN(start | end)) | ||
| 845 | return -EINVAL; | ||
| 846 | |||
| 847 | obj->da_start = start; | ||
| 848 | obj->da_end = end; | ||
| 849 | |||
| 850 | return 0; | ||
| 851 | } | ||
| 852 | EXPORT_SYMBOL_GPL(iommu_set_da_range); | ||
| 853 | |||
| 854 | /** | ||
| 833 | * iommu_get - Get iommu handler | 855 | * iommu_get - Get iommu handler |
| 834 | * @name: target iommu name | 856 | * @name: target iommu name |
| 835 | **/ | 857 | **/ |
| @@ -922,6 +944,8 @@ static int __devinit omap_iommu_probe(struct platform_device *pdev) | |||
| 922 | obj->name = pdata->name; | 944 | obj->name = pdata->name; |
| 923 | obj->dev = &pdev->dev; | 945 | obj->dev = &pdev->dev; |
| 924 | obj->ctx = (void *)obj + sizeof(*obj); | 946 | obj->ctx = (void *)obj + sizeof(*obj); |
| 947 | obj->da_start = pdata->da_start; | ||
| 948 | obj->da_end = pdata->da_end; | ||
| 925 | 949 | ||
| 926 | mutex_init(&obj->iommu_lock); | 950 | mutex_init(&obj->iommu_lock); |
| 927 | mutex_init(&obj->mmap_lock); | 951 | mutex_init(&obj->mmap_lock); |
diff --git a/arch/arm/plat-omap/iovmm.c b/arch/arm/plat-omap/iovmm.c index 8ce0de247c71..6dc1296c8c77 100644 --- a/arch/arm/plat-omap/iovmm.c +++ b/arch/arm/plat-omap/iovmm.c | |||
| @@ -87,35 +87,43 @@ static size_t sgtable_len(const struct sg_table *sgt) | |||
| 87 | } | 87 | } |
| 88 | #define sgtable_ok(x) (!!sgtable_len(x)) | 88 | #define sgtable_ok(x) (!!sgtable_len(x)) |
| 89 | 89 | ||
| 90 | static unsigned max_alignment(u32 addr) | ||
| 91 | { | ||
| 92 | int i; | ||
| 93 | unsigned pagesize[] = { SZ_16M, SZ_1M, SZ_64K, SZ_4K, }; | ||
| 94 | for (i = 0; i < ARRAY_SIZE(pagesize) && addr & (pagesize[i] - 1); i++) | ||
| 95 | ; | ||
| 96 | return (i < ARRAY_SIZE(pagesize)) ? pagesize[i] : 0; | ||
| 97 | } | ||
| 98 | |||
| 90 | /* | 99 | /* |
| 91 | * calculate the optimal number sg elements from total bytes based on | 100 | * calculate the optimal number sg elements from total bytes based on |
| 92 | * iommu superpages | 101 | * iommu superpages |
| 93 | */ | 102 | */ |
| 94 | static unsigned int sgtable_nents(size_t bytes) | 103 | static unsigned sgtable_nents(size_t bytes, u32 da, u32 pa) |
| 95 | { | 104 | { |
| 96 | int i; | 105 | unsigned nr_entries = 0, ent_sz; |
| 97 | unsigned int nr_entries; | ||
| 98 | const unsigned long pagesize[] = { SZ_16M, SZ_1M, SZ_64K, SZ_4K, }; | ||
| 99 | 106 | ||
| 100 | if (!IS_ALIGNED(bytes, PAGE_SIZE)) { | 107 | if (!IS_ALIGNED(bytes, PAGE_SIZE)) { |
| 101 | pr_err("%s: wrong size %08x\n", __func__, bytes); | 108 | pr_err("%s: wrong size %08x\n", __func__, bytes); |
| 102 | return 0; | 109 | return 0; |
| 103 | } | 110 | } |
| 104 | 111 | ||
| 105 | nr_entries = 0; | 112 | while (bytes) { |
| 106 | for (i = 0; i < ARRAY_SIZE(pagesize); i++) { | 113 | ent_sz = max_alignment(da | pa); |
| 107 | if (bytes >= pagesize[i]) { | 114 | ent_sz = min_t(unsigned, ent_sz, iopgsz_max(bytes)); |
| 108 | nr_entries += (bytes / pagesize[i]); | 115 | nr_entries++; |
| 109 | bytes %= pagesize[i]; | 116 | da += ent_sz; |
| 110 | } | 117 | pa += ent_sz; |
| 118 | bytes -= ent_sz; | ||
| 111 | } | 119 | } |
| 112 | BUG_ON(bytes); | ||
| 113 | 120 | ||
| 114 | return nr_entries; | 121 | return nr_entries; |
| 115 | } | 122 | } |
| 116 | 123 | ||
| 117 | /* allocate and initialize sg_table header(a kind of 'superblock') */ | 124 | /* allocate and initialize sg_table header(a kind of 'superblock') */ |
| 118 | static struct sg_table *sgtable_alloc(const size_t bytes, u32 flags) | 125 | static struct sg_table *sgtable_alloc(const size_t bytes, u32 flags, |
| 126 | u32 da, u32 pa) | ||
| 119 | { | 127 | { |
| 120 | unsigned int nr_entries; | 128 | unsigned int nr_entries; |
| 121 | int err; | 129 | int err; |
| @@ -127,9 +135,8 @@ static struct sg_table *sgtable_alloc(const size_t bytes, u32 flags) | |||
| 127 | if (!IS_ALIGNED(bytes, PAGE_SIZE)) | 135 | if (!IS_ALIGNED(bytes, PAGE_SIZE)) |
| 128 | return ERR_PTR(-EINVAL); | 136 | return ERR_PTR(-EINVAL); |
| 129 | 137 | ||
| 130 | /* FIXME: IOVMF_DA_FIXED should support 'superpages' */ | 138 | if (flags & IOVMF_LINEAR) { |
| 131 | if ((flags & IOVMF_LINEAR) && (flags & IOVMF_DA_ANON)) { | 139 | nr_entries = sgtable_nents(bytes, da, pa); |
| 132 | nr_entries = sgtable_nents(bytes); | ||
| 133 | if (!nr_entries) | 140 | if (!nr_entries) |
| 134 | return ERR_PTR(-EINVAL); | 141 | return ERR_PTR(-EINVAL); |
| 135 | } else | 142 | } else |
| @@ -273,13 +280,14 @@ static struct iovm_struct *alloc_iovm_area(struct iommu *obj, u32 da, | |||
| 273 | alignement = PAGE_SIZE; | 280 | alignement = PAGE_SIZE; |
| 274 | 281 | ||
| 275 | if (flags & IOVMF_DA_ANON) { | 282 | if (flags & IOVMF_DA_ANON) { |
| 276 | /* | 283 | start = obj->da_start; |
| 277 | * Reserve the first page for NULL | 284 | |
| 278 | */ | ||
| 279 | start = PAGE_SIZE; | ||
| 280 | if (flags & IOVMF_LINEAR) | 285 | if (flags & IOVMF_LINEAR) |
| 281 | alignement = iopgsz_max(bytes); | 286 | alignement = iopgsz_max(bytes); |
| 282 | start = roundup(start, alignement); | 287 | start = roundup(start, alignement); |
| 288 | } else if (start < obj->da_start || start > obj->da_end || | ||
| 289 | obj->da_end - start < bytes) { | ||
| 290 | return ERR_PTR(-EINVAL); | ||
| 283 | } | 291 | } |
| 284 | 292 | ||
| 285 | tmp = NULL; | 293 | tmp = NULL; |
| @@ -289,19 +297,19 @@ static struct iovm_struct *alloc_iovm_area(struct iommu *obj, u32 da, | |||
| 289 | prev_end = 0; | 297 | prev_end = 0; |
| 290 | list_for_each_entry(tmp, &obj->mmap, list) { | 298 | list_for_each_entry(tmp, &obj->mmap, list) { |
| 291 | 299 | ||
| 292 | if (prev_end >= start) | 300 | if (prev_end > start) |
| 293 | break; | 301 | break; |
| 294 | 302 | ||
| 295 | if (start + bytes < tmp->da_start) | 303 | if (tmp->da_start > start && (tmp->da_start - start) >= bytes) |
| 296 | goto found; | 304 | goto found; |
| 297 | 305 | ||
| 298 | if (flags & IOVMF_DA_ANON) | 306 | if (tmp->da_end >= start && flags & IOVMF_DA_ANON) |
| 299 | start = roundup(tmp->da_end + 1, alignement); | 307 | start = roundup(tmp->da_end + 1, alignement); |
| 300 | 308 | ||
| 301 | prev_end = tmp->da_end; | 309 | prev_end = tmp->da_end; |
| 302 | } | 310 | } |
| 303 | 311 | ||
| 304 | if ((start > prev_end) && (ULONG_MAX - start >= bytes)) | 312 | if ((start >= prev_end) && (obj->da_end - start >= bytes)) |
| 305 | goto found; | 313 | goto found; |
| 306 | 314 | ||
| 307 | dev_dbg(obj->dev, "%s: no space to fit %08x(%x) flags: %08x\n", | 315 | dev_dbg(obj->dev, "%s: no space to fit %08x(%x) flags: %08x\n", |
| @@ -409,7 +417,8 @@ static inline void sgtable_drain_vmalloc(struct sg_table *sgt) | |||
| 409 | BUG_ON(!sgt); | 417 | BUG_ON(!sgt); |
| 410 | } | 418 | } |
| 411 | 419 | ||
| 412 | static void sgtable_fill_kmalloc(struct sg_table *sgt, u32 pa, size_t len) | 420 | static void sgtable_fill_kmalloc(struct sg_table *sgt, u32 pa, u32 da, |
| 421 | size_t len) | ||
| 413 | { | 422 | { |
| 414 | unsigned int i; | 423 | unsigned int i; |
| 415 | struct scatterlist *sg; | 424 | struct scatterlist *sg; |
| @@ -418,9 +427,10 @@ static void sgtable_fill_kmalloc(struct sg_table *sgt, u32 pa, size_t len) | |||
| 418 | va = phys_to_virt(pa); | 427 | va = phys_to_virt(pa); |
| 419 | 428 | ||
| 420 | for_each_sg(sgt->sgl, sg, sgt->nents, i) { | 429 | for_each_sg(sgt->sgl, sg, sgt->nents, i) { |
| 421 | size_t bytes; | 430 | unsigned bytes; |
| 422 | 431 | ||
| 423 | bytes = iopgsz_max(len); | 432 | bytes = max_alignment(da | pa); |
| 433 | bytes = min_t(unsigned, bytes, iopgsz_max(len)); | ||
| 424 | 434 | ||
| 425 | BUG_ON(!iopgsz_ok(bytes)); | 435 | BUG_ON(!iopgsz_ok(bytes)); |
| 426 | 436 | ||
| @@ -429,6 +439,7 @@ static void sgtable_fill_kmalloc(struct sg_table *sgt, u32 pa, size_t len) | |||
| 429 | * 'pa' is cotinuous(linear). | 439 | * 'pa' is cotinuous(linear). |
| 430 | */ | 440 | */ |
| 431 | pa += bytes; | 441 | pa += bytes; |
| 442 | da += bytes; | ||
| 432 | len -= bytes; | 443 | len -= bytes; |
| 433 | } | 444 | } |
| 434 | BUG_ON(len); | 445 | BUG_ON(len); |
| @@ -695,18 +706,18 @@ u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags) | |||
| 695 | if (!va) | 706 | if (!va) |
| 696 | return -ENOMEM; | 707 | return -ENOMEM; |
| 697 | 708 | ||
| 698 | sgt = sgtable_alloc(bytes, flags); | 709 | flags &= IOVMF_HW_MASK; |
| 710 | flags |= IOVMF_DISCONT; | ||
| 711 | flags |= IOVMF_ALLOC; | ||
| 712 | flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON); | ||
| 713 | |||
| 714 | sgt = sgtable_alloc(bytes, flags, da, 0); | ||
| 699 | if (IS_ERR(sgt)) { | 715 | if (IS_ERR(sgt)) { |
| 700 | da = PTR_ERR(sgt); | 716 | da = PTR_ERR(sgt); |
| 701 | goto err_sgt_alloc; | 717 | goto err_sgt_alloc; |
| 702 | } | 718 | } |
| 703 | sgtable_fill_vmalloc(sgt, va); | 719 | sgtable_fill_vmalloc(sgt, va); |
| 704 | 720 | ||
| 705 | flags &= IOVMF_HW_MASK; | ||
| 706 | flags |= IOVMF_DISCONT; | ||
| 707 | flags |= IOVMF_ALLOC; | ||
| 708 | flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON); | ||
| 709 | |||
| 710 | da = __iommu_vmap(obj, da, sgt, va, bytes, flags); | 721 | da = __iommu_vmap(obj, da, sgt, va, bytes, flags); |
| 711 | if (IS_ERR_VALUE(da)) | 722 | if (IS_ERR_VALUE(da)) |
| 712 | goto err_iommu_vmap; | 723 | goto err_iommu_vmap; |
| @@ -746,11 +757,11 @@ static u32 __iommu_kmap(struct iommu *obj, u32 da, u32 pa, void *va, | |||
| 746 | { | 757 | { |
| 747 | struct sg_table *sgt; | 758 | struct sg_table *sgt; |
| 748 | 759 | ||
| 749 | sgt = sgtable_alloc(bytes, flags); | 760 | sgt = sgtable_alloc(bytes, flags, da, pa); |
| 750 | if (IS_ERR(sgt)) | 761 | if (IS_ERR(sgt)) |
| 751 | return PTR_ERR(sgt); | 762 | return PTR_ERR(sgt); |
| 752 | 763 | ||
| 753 | sgtable_fill_kmalloc(sgt, pa, bytes); | 764 | sgtable_fill_kmalloc(sgt, pa, da, bytes); |
| 754 | 765 | ||
| 755 | da = map_iommu_region(obj, da, sgt, va, bytes, flags); | 766 | da = map_iommu_region(obj, da, sgt, va, bytes, flags); |
| 756 | if (IS_ERR_VALUE(da)) { | 767 | if (IS_ERR_VALUE(da)) { |
| @@ -811,7 +822,7 @@ void iommu_kunmap(struct iommu *obj, u32 da) | |||
| 811 | struct sg_table *sgt; | 822 | struct sg_table *sgt; |
| 812 | typedef void (*func_t)(const void *); | 823 | typedef void (*func_t)(const void *); |
| 813 | 824 | ||
| 814 | sgt = unmap_vm_area(obj, da, (func_t)__iounmap, | 825 | sgt = unmap_vm_area(obj, da, (func_t)iounmap, |
| 815 | IOVMF_LINEAR | IOVMF_MMIO); | 826 | IOVMF_LINEAR | IOVMF_MMIO); |
| 816 | if (!sgt) | 827 | if (!sgt) |
| 817 | dev_dbg(obj->dev, "%s: No sgt\n", __func__); | 828 | dev_dbg(obj->dev, "%s: No sgt\n", __func__); |
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c index d2fafb892f7f..459b319a9fad 100644 --- a/arch/arm/plat-omap/mailbox.c +++ b/arch/arm/plat-omap/mailbox.c | |||
| @@ -28,12 +28,12 @@ | |||
| 28 | #include <linux/slab.h> | 28 | #include <linux/slab.h> |
| 29 | #include <linux/kfifo.h> | 29 | #include <linux/kfifo.h> |
| 30 | #include <linux/err.h> | 30 | #include <linux/err.h> |
| 31 | #include <linux/notifier.h> | ||
| 31 | 32 | ||
| 32 | #include <plat/mailbox.h> | 33 | #include <plat/mailbox.h> |
| 33 | 34 | ||
| 34 | static struct workqueue_struct *mboxd; | 35 | static struct workqueue_struct *mboxd; |
| 35 | static struct omap_mbox **mboxes; | 36 | static struct omap_mbox **mboxes; |
| 36 | static bool rq_full; | ||
| 37 | 37 | ||
| 38 | static int mbox_configured; | 38 | static int mbox_configured; |
| 39 | static DEFINE_MUTEX(mbox_configured_lock); | 39 | static DEFINE_MUTEX(mbox_configured_lock); |
| @@ -93,20 +93,25 @@ int omap_mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg) | |||
| 93 | struct omap_mbox_queue *mq = mbox->txq; | 93 | struct omap_mbox_queue *mq = mbox->txq; |
| 94 | int ret = 0, len; | 94 | int ret = 0, len; |
| 95 | 95 | ||
| 96 | spin_lock(&mq->lock); | 96 | spin_lock_bh(&mq->lock); |
| 97 | 97 | ||
| 98 | if (kfifo_avail(&mq->fifo) < sizeof(msg)) { | 98 | if (kfifo_avail(&mq->fifo) < sizeof(msg)) { |
| 99 | ret = -ENOMEM; | 99 | ret = -ENOMEM; |
| 100 | goto out; | 100 | goto out; |
| 101 | } | 101 | } |
| 102 | 102 | ||
| 103 | if (kfifo_is_empty(&mq->fifo) && !__mbox_poll_for_space(mbox)) { | ||
| 104 | mbox_fifo_write(mbox, msg); | ||
| 105 | goto out; | ||
| 106 | } | ||
| 107 | |||
| 103 | len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg)); | 108 | len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg)); |
| 104 | WARN_ON(len != sizeof(msg)); | 109 | WARN_ON(len != sizeof(msg)); |
| 105 | 110 | ||
| 106 | tasklet_schedule(&mbox->txq->tasklet); | 111 | tasklet_schedule(&mbox->txq->tasklet); |
| 107 | 112 | ||
| 108 | out: | 113 | out: |
| 109 | spin_unlock(&mq->lock); | 114 | spin_unlock_bh(&mq->lock); |
| 110 | return ret; | 115 | return ret; |
| 111 | } | 116 | } |
| 112 | EXPORT_SYMBOL(omap_mbox_msg_send); | 117 | EXPORT_SYMBOL(omap_mbox_msg_send); |
| @@ -146,8 +151,14 @@ static void mbox_rx_work(struct work_struct *work) | |||
| 146 | len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg)); | 151 | len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg)); |
| 147 | WARN_ON(len != sizeof(msg)); | 152 | WARN_ON(len != sizeof(msg)); |
| 148 | 153 | ||
| 149 | if (mq->callback) | 154 | blocking_notifier_call_chain(&mq->mbox->notifier, len, |
| 150 | mq->callback((void *)msg); | 155 | (void *)msg); |
| 156 | spin_lock_irq(&mq->lock); | ||
| 157 | if (mq->full) { | ||
| 158 | mq->full = false; | ||
| 159 | omap_mbox_enable_irq(mq->mbox, IRQ_RX); | ||
| 160 | } | ||
| 161 | spin_unlock_irq(&mq->lock); | ||
| 151 | } | 162 | } |
| 152 | } | 163 | } |
| 153 | 164 | ||
| @@ -170,7 +181,7 @@ static void __mbox_rx_interrupt(struct omap_mbox *mbox) | |||
| 170 | while (!mbox_fifo_empty(mbox)) { | 181 | while (!mbox_fifo_empty(mbox)) { |
| 171 | if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) { | 182 | if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) { |
| 172 | omap_mbox_disable_irq(mbox, IRQ_RX); | 183 | omap_mbox_disable_irq(mbox, IRQ_RX); |
| 173 | rq_full = true; | 184 | mq->full = true; |
| 174 | goto nomem; | 185 | goto nomem; |
| 175 | } | 186 | } |
| 176 | 187 | ||
| @@ -239,73 +250,77 @@ static int omap_mbox_startup(struct omap_mbox *mbox) | |||
| 239 | int ret = 0; | 250 | int ret = 0; |
| 240 | struct omap_mbox_queue *mq; | 251 | struct omap_mbox_queue *mq; |
| 241 | 252 | ||
| 242 | if (mbox->ops->startup) { | 253 | mutex_lock(&mbox_configured_lock); |
| 243 | mutex_lock(&mbox_configured_lock); | 254 | if (!mbox_configured++) { |
| 244 | if (!mbox_configured) | 255 | if (likely(mbox->ops->startup)) { |
| 245 | ret = mbox->ops->startup(mbox); | 256 | ret = mbox->ops->startup(mbox); |
| 246 | 257 | if (unlikely(ret)) | |
| 247 | if (ret) { | 258 | goto fail_startup; |
| 248 | mutex_unlock(&mbox_configured_lock); | 259 | } else |
| 249 | return ret; | 260 | goto fail_startup; |
| 250 | } | ||
| 251 | mbox_configured++; | ||
| 252 | mutex_unlock(&mbox_configured_lock); | ||
| 253 | } | ||
| 254 | |||
| 255 | ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED, | ||
| 256 | mbox->name, mbox); | ||
| 257 | if (ret) { | ||
| 258 | printk(KERN_ERR | ||
| 259 | "failed to register mailbox interrupt:%d\n", ret); | ||
| 260 | goto fail_request_irq; | ||
| 261 | } | 261 | } |
| 262 | 262 | ||
| 263 | mq = mbox_queue_alloc(mbox, NULL, mbox_tx_tasklet); | 263 | if (!mbox->use_count++) { |
| 264 | if (!mq) { | 264 | ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED, |
| 265 | ret = -ENOMEM; | 265 | mbox->name, mbox); |
| 266 | goto fail_alloc_txq; | 266 | if (unlikely(ret)) { |
| 267 | } | 267 | pr_err("failed to register mailbox interrupt:%d\n", |
| 268 | mbox->txq = mq; | 268 | ret); |
| 269 | goto fail_request_irq; | ||
| 270 | } | ||
| 271 | mq = mbox_queue_alloc(mbox, NULL, mbox_tx_tasklet); | ||
| 272 | if (!mq) { | ||
| 273 | ret = -ENOMEM; | ||
| 274 | goto fail_alloc_txq; | ||
| 275 | } | ||
| 276 | mbox->txq = mq; | ||
| 269 | 277 | ||
| 270 | mq = mbox_queue_alloc(mbox, mbox_rx_work, NULL); | 278 | mq = mbox_queue_alloc(mbox, mbox_rx_work, NULL); |
| 271 | if (!mq) { | 279 | if (!mq) { |
| 272 | ret = -ENOMEM; | 280 | ret = -ENOMEM; |
| 273 | goto fail_alloc_rxq; | 281 | goto fail_alloc_rxq; |
| 282 | } | ||
| 283 | mbox->rxq = mq; | ||
| 284 | mq->mbox = mbox; | ||
| 274 | } | 285 | } |
| 275 | mbox->rxq = mq; | 286 | mutex_unlock(&mbox_configured_lock); |
| 276 | |||
| 277 | return 0; | 287 | return 0; |
| 278 | 288 | ||
| 279 | fail_alloc_rxq: | 289 | fail_alloc_rxq: |
| 280 | mbox_queue_free(mbox->txq); | 290 | mbox_queue_free(mbox->txq); |
| 281 | fail_alloc_txq: | 291 | fail_alloc_txq: |
| 282 | free_irq(mbox->irq, mbox); | 292 | free_irq(mbox->irq, mbox); |
| 283 | fail_request_irq: | 293 | fail_request_irq: |
| 284 | if (mbox->ops->shutdown) | 294 | if (mbox->ops->shutdown) |
| 285 | mbox->ops->shutdown(mbox); | 295 | mbox->ops->shutdown(mbox); |
| 286 | 296 | mbox->use_count--; | |
| 297 | fail_startup: | ||
| 298 | mbox_configured--; | ||
| 299 | mutex_unlock(&mbox_configured_lock); | ||
| 287 | return ret; | 300 | return ret; |
| 288 | } | 301 | } |
| 289 | 302 | ||
| 290 | static void omap_mbox_fini(struct omap_mbox *mbox) | 303 | static void omap_mbox_fini(struct omap_mbox *mbox) |
| 291 | { | 304 | { |
| 292 | free_irq(mbox->irq, mbox); | 305 | mutex_lock(&mbox_configured_lock); |
| 293 | tasklet_kill(&mbox->txq->tasklet); | 306 | |
| 294 | flush_work(&mbox->rxq->work); | 307 | if (!--mbox->use_count) { |
| 295 | mbox_queue_free(mbox->txq); | 308 | free_irq(mbox->irq, mbox); |
| 296 | mbox_queue_free(mbox->rxq); | 309 | tasklet_kill(&mbox->txq->tasklet); |
| 310 | flush_work(&mbox->rxq->work); | ||
| 311 | mbox_queue_free(mbox->txq); | ||
| 312 | mbox_queue_free(mbox->rxq); | ||
| 313 | } | ||
| 297 | 314 | ||
| 298 | if (mbox->ops->shutdown) { | 315 | if (likely(mbox->ops->shutdown)) { |
| 299 | mutex_lock(&mbox_configured_lock); | 316 | if (!--mbox_configured) |
| 300 | if (mbox_configured > 0) | ||
| 301 | mbox_configured--; | ||
| 302 | if (!mbox_configured) | ||
| 303 | mbox->ops->shutdown(mbox); | 317 | mbox->ops->shutdown(mbox); |
| 304 | mutex_unlock(&mbox_configured_lock); | ||
| 305 | } | 318 | } |
| 319 | |||
| 320 | mutex_unlock(&mbox_configured_lock); | ||
| 306 | } | 321 | } |
| 307 | 322 | ||
| 308 | struct omap_mbox *omap_mbox_get(const char *name) | 323 | struct omap_mbox *omap_mbox_get(const char *name, struct notifier_block *nb) |
| 309 | { | 324 | { |
| 310 | struct omap_mbox *mbox; | 325 | struct omap_mbox *mbox; |
| 311 | int ret; | 326 | int ret; |
| @@ -324,12 +339,16 @@ struct omap_mbox *omap_mbox_get(const char *name) | |||
| 324 | if (ret) | 339 | if (ret) |
| 325 | return ERR_PTR(-ENODEV); | 340 | return ERR_PTR(-ENODEV); |
| 326 | 341 | ||
| 342 | if (nb) | ||
| 343 | blocking_notifier_chain_register(&mbox->notifier, nb); | ||
| 344 | |||
| 327 | return mbox; | 345 | return mbox; |
| 328 | } | 346 | } |
| 329 | EXPORT_SYMBOL(omap_mbox_get); | 347 | EXPORT_SYMBOL(omap_mbox_get); |
| 330 | 348 | ||
| 331 | void omap_mbox_put(struct omap_mbox *mbox) | 349 | void omap_mbox_put(struct omap_mbox *mbox, struct notifier_block *nb) |
| 332 | { | 350 | { |
| 351 | blocking_notifier_chain_unregister(&mbox->notifier, nb); | ||
| 333 | omap_mbox_fini(mbox); | 352 | omap_mbox_fini(mbox); |
| 334 | } | 353 | } |
| 335 | EXPORT_SYMBOL(omap_mbox_put); | 354 | EXPORT_SYMBOL(omap_mbox_put); |
| @@ -353,6 +372,8 @@ int omap_mbox_register(struct device *parent, struct omap_mbox **list) | |||
| 353 | ret = PTR_ERR(mbox->dev); | 372 | ret = PTR_ERR(mbox->dev); |
| 354 | goto err_out; | 373 | goto err_out; |
| 355 | } | 374 | } |
| 375 | |||
| 376 | BLOCKING_INIT_NOTIFIER_HEAD(&mbox->notifier); | ||
| 356 | } | 377 | } |
| 357 | return 0; | 378 | return 0; |
| 358 | 379 | ||
| @@ -391,7 +412,8 @@ static int __init omap_mbox_init(void) | |||
| 391 | 412 | ||
| 392 | /* kfifo size sanity check: alignment and minimal size */ | 413 | /* kfifo size sanity check: alignment and minimal size */ |
| 393 | mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(mbox_msg_t)); | 414 | mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(mbox_msg_t)); |
| 394 | mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size, sizeof(mbox_msg_t)); | 415 | mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size, |
| 416 | sizeof(mbox_msg_t)); | ||
| 395 | 417 | ||
| 396 | return 0; | 418 | return 0; |
| 397 | } | 419 | } |
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index eac4b978e9fd..b5a6e178a7f9 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c | |||
| @@ -28,6 +28,8 @@ | |||
| 28 | #include <plat/dma.h> | 28 | #include <plat/dma.h> |
| 29 | #include <plat/mcbsp.h> | 29 | #include <plat/mcbsp.h> |
| 30 | 30 | ||
| 31 | /* XXX These "sideways" includes are a sign that something is wrong */ | ||
| 32 | #include "../mach-omap2/cm2xxx_3xxx.h" | ||
| 31 | #include "../mach-omap2/cm-regbits-34xx.h" | 33 | #include "../mach-omap2/cm-regbits-34xx.h" |
| 32 | 34 | ||
| 33 | struct omap_mcbsp **mcbsp_ptr; | 35 | struct omap_mcbsp **mcbsp_ptr; |
| @@ -234,9 +236,9 @@ static void omap_st_on(struct omap_mcbsp *mcbsp) | |||
| 234 | * Sidetone uses McBSP ICLK - which must not idle when sidetones | 236 | * Sidetone uses McBSP ICLK - which must not idle when sidetones |
| 235 | * are enabled or sidetones start sounding ugly. | 237 | * are enabled or sidetones start sounding ugly. |
| 236 | */ | 238 | */ |
| 237 | w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); | 239 | w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); |
| 238 | w &= ~(1 << (mcbsp->id - 2)); | 240 | w &= ~(1 << (mcbsp->id - 2)); |
| 239 | cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE); | 241 | omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE); |
| 240 | 242 | ||
| 241 | /* Enable McBSP Sidetone */ | 243 | /* Enable McBSP Sidetone */ |
| 242 | w = MCBSP_READ(mcbsp, SSELCR); | 244 | w = MCBSP_READ(mcbsp, SSELCR); |
| @@ -263,9 +265,9 @@ static void omap_st_off(struct omap_mcbsp *mcbsp) | |||
| 263 | w = MCBSP_READ(mcbsp, SSELCR); | 265 | w = MCBSP_READ(mcbsp, SSELCR); |
| 264 | MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN)); | 266 | MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN)); |
| 265 | 267 | ||
| 266 | w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); | 268 | w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); |
| 267 | w |= 1 << (mcbsp->id - 2); | 269 | w |= 1 << (mcbsp->id - 2); |
| 268 | cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE); | 270 | omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE); |
| 269 | } | 271 | } |
| 270 | 272 | ||
| 271 | static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir) | 273 | static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir) |
| @@ -755,7 +757,7 @@ int omap_mcbsp_request(unsigned int id) | |||
| 755 | goto err_kfree; | 757 | goto err_kfree; |
| 756 | } | 758 | } |
| 757 | 759 | ||
| 758 | mcbsp->free = 0; | 760 | mcbsp->free = false; |
| 759 | mcbsp->reg_cache = reg_cache; | 761 | mcbsp->reg_cache = reg_cache; |
| 760 | spin_unlock(&mcbsp->lock); | 762 | spin_unlock(&mcbsp->lock); |
| 761 | 763 | ||
| @@ -815,7 +817,7 @@ err_clk_disable: | |||
| 815 | clk_disable(mcbsp->iclk); | 817 | clk_disable(mcbsp->iclk); |
| 816 | 818 | ||
| 817 | spin_lock(&mcbsp->lock); | 819 | spin_lock(&mcbsp->lock); |
| 818 | mcbsp->free = 1; | 820 | mcbsp->free = true; |
| 819 | mcbsp->reg_cache = NULL; | 821 | mcbsp->reg_cache = NULL; |
| 820 | err_kfree: | 822 | err_kfree: |
| 821 | spin_unlock(&mcbsp->lock); | 823 | spin_unlock(&mcbsp->lock); |
| @@ -858,7 +860,7 @@ void omap_mcbsp_free(unsigned int id) | |||
| 858 | if (mcbsp->free) | 860 | if (mcbsp->free) |
| 859 | dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id); | 861 | dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id); |
| 860 | else | 862 | else |
| 861 | mcbsp->free = 1; | 863 | mcbsp->free = true; |
| 862 | mcbsp->reg_cache = NULL; | 864 | mcbsp->reg_cache = NULL; |
| 863 | spin_unlock(&mcbsp->lock); | 865 | spin_unlock(&mcbsp->lock); |
| 864 | 866 | ||
| @@ -1771,7 +1773,7 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev) | |||
| 1771 | 1773 | ||
| 1772 | spin_lock_init(&mcbsp->lock); | 1774 | spin_lock_init(&mcbsp->lock); |
| 1773 | mcbsp->id = id + 1; | 1775 | mcbsp->id = id + 1; |
| 1774 | mcbsp->free = 1; | 1776 | mcbsp->free = true; |
| 1775 | mcbsp->dma_tx_lch = -1; | 1777 | mcbsp->dma_tx_lch = -1; |
| 1776 | mcbsp->dma_rx_lch = -1; | 1778 | mcbsp->dma_rx_lch = -1; |
| 1777 | 1779 | ||
| @@ -1836,17 +1838,11 @@ static int __devexit omap_mcbsp_remove(struct platform_device *pdev) | |||
| 1836 | 1838 | ||
| 1837 | omap34xx_device_exit(mcbsp); | 1839 | omap34xx_device_exit(mcbsp); |
| 1838 | 1840 | ||
| 1839 | clk_disable(mcbsp->fclk); | ||
| 1840 | clk_disable(mcbsp->iclk); | ||
| 1841 | clk_put(mcbsp->fclk); | 1841 | clk_put(mcbsp->fclk); |
| 1842 | clk_put(mcbsp->iclk); | 1842 | clk_put(mcbsp->iclk); |
| 1843 | 1843 | ||
| 1844 | iounmap(mcbsp->io_base); | 1844 | iounmap(mcbsp->io_base); |
| 1845 | 1845 | kfree(mcbsp); | |
| 1846 | mcbsp->fclk = NULL; | ||
| 1847 | mcbsp->iclk = NULL; | ||
| 1848 | mcbsp->free = 0; | ||
| 1849 | mcbsp->dev = NULL; | ||
| 1850 | } | 1846 | } |
| 1851 | 1847 | ||
| 1852 | return 0; | 1848 | return 0; |
diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c index e129ce80c53b..b0471bb2d47d 100644 --- a/arch/arm/plat-omap/omap-pm-noop.c +++ b/arch/arm/plat-omap/omap-pm-noop.c | |||
| @@ -20,15 +20,14 @@ | |||
| 20 | #include <linux/init.h> | 20 | #include <linux/init.h> |
| 21 | #include <linux/cpufreq.h> | 21 | #include <linux/cpufreq.h> |
| 22 | #include <linux/device.h> | 22 | #include <linux/device.h> |
| 23 | #include <linux/platform_device.h> | ||
| 23 | 24 | ||
| 24 | /* Interface documentation is in mach/omap-pm.h */ | 25 | /* Interface documentation is in mach/omap-pm.h */ |
| 25 | #include <plat/omap-pm.h> | 26 | #include <plat/omap-pm.h> |
| 27 | #include <plat/omap_device.h> | ||
| 26 | 28 | ||
| 27 | #include <plat/powerdomain.h> | 29 | static bool off_mode_enabled; |
| 28 | 30 | static u32 dummy_context_loss_counter; | |
| 29 | struct omap_opp *dsp_opps; | ||
| 30 | struct omap_opp *mpu_opps; | ||
| 31 | struct omap_opp *l3_opps; | ||
| 32 | 31 | ||
| 33 | /* | 32 | /* |
| 34 | * Device-driver-originated constraints (via board-*.c files) | 33 | * Device-driver-originated constraints (via board-*.c files) |
| @@ -284,37 +283,70 @@ unsigned long omap_pm_cpu_get_freq(void) | |||
| 284 | return 0; | 283 | return 0; |
| 285 | } | 284 | } |
| 286 | 285 | ||
| 286 | /** | ||
| 287 | * omap_pm_enable_off_mode - notify OMAP PM that off-mode is enabled | ||
| 288 | * | ||
| 289 | * Intended for use only by OMAP PM core code to notify this layer | ||
| 290 | * that off mode has been enabled. | ||
| 291 | */ | ||
| 292 | void omap_pm_enable_off_mode(void) | ||
| 293 | { | ||
| 294 | off_mode_enabled = true; | ||
| 295 | } | ||
| 296 | |||
| 297 | /** | ||
| 298 | * omap_pm_disable_off_mode - notify OMAP PM that off-mode is disabled | ||
| 299 | * | ||
| 300 | * Intended for use only by OMAP PM core code to notify this layer | ||
| 301 | * that off mode has been disabled. | ||
| 302 | */ | ||
| 303 | void omap_pm_disable_off_mode(void) | ||
| 304 | { | ||
| 305 | off_mode_enabled = false; | ||
| 306 | } | ||
| 307 | |||
| 287 | /* | 308 | /* |
| 288 | * Device context loss tracking | 309 | * Device context loss tracking |
| 289 | */ | 310 | */ |
| 290 | 311 | ||
| 291 | int omap_pm_get_dev_context_loss_count(struct device *dev) | 312 | #ifdef CONFIG_ARCH_OMAP2PLUS |
| 313 | |||
| 314 | u32 omap_pm_get_dev_context_loss_count(struct device *dev) | ||
| 292 | { | 315 | { |
| 293 | if (!dev) { | 316 | struct platform_device *pdev = to_platform_device(dev); |
| 294 | WARN_ON(1); | 317 | u32 count; |
| 295 | return -EINVAL; | 318 | |
| 296 | }; | 319 | if (WARN_ON(!dev)) |
| 320 | return 0; | ||
| 321 | |||
| 322 | if (dev->parent == &omap_device_parent) { | ||
| 323 | count = omap_device_get_context_loss_count(pdev); | ||
| 324 | } else { | ||
| 325 | WARN_ONCE(off_mode_enabled, "omap_pm: using dummy context loss counter; device %s should be converted to omap_device", | ||
| 326 | dev_name(dev)); | ||
| 327 | if (off_mode_enabled) | ||
| 328 | dummy_context_loss_counter++; | ||
| 329 | count = dummy_context_loss_counter; | ||
| 330 | } | ||
| 297 | 331 | ||
| 298 | pr_debug("OMAP PM: returning context loss count for dev %s\n", | 332 | pr_debug("OMAP PM: context loss count for dev %s = %d\n", |
| 299 | dev_name(dev)); | 333 | dev_name(dev), count); |
| 300 | 334 | ||
| 301 | /* | 335 | return count; |
| 302 | * Map the device to the powerdomain. Return the powerdomain | 336 | } |
| 303 | * off counter. | ||
| 304 | */ | ||
| 305 | 337 | ||
| 306 | return 0; | 338 | #else |
| 339 | |||
| 340 | u32 omap_pm_get_dev_context_loss_count(struct device *dev) | ||
| 341 | { | ||
| 342 | return dummy_context_loss_counter; | ||
| 307 | } | 343 | } |
| 308 | 344 | ||
| 345 | #endif | ||
| 309 | 346 | ||
| 310 | /* Should be called before clk framework init */ | 347 | /* Should be called before clk framework init */ |
| 311 | int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table, | 348 | int __init omap_pm_if_early_init(void) |
| 312 | struct omap_opp *dsp_opp_table, | ||
| 313 | struct omap_opp *l3_opp_table) | ||
| 314 | { | 349 | { |
| 315 | mpu_opps = mpu_opp_table; | ||
| 316 | dsp_opps = dsp_opp_table; | ||
| 317 | l3_opps = l3_opp_table; | ||
| 318 | return 0; | 350 | return 0; |
| 319 | } | 351 | } |
| 320 | 352 | ||
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c index abe933cd8f09..57adb270767b 100644 --- a/arch/arm/plat-omap/omap_device.c +++ b/arch/arm/plat-omap/omap_device.c | |||
| @@ -280,6 +280,34 @@ static void _add_optional_clock_alias(struct omap_device *od, | |||
| 280 | /* Public functions for use by core code */ | 280 | /* Public functions for use by core code */ |
| 281 | 281 | ||
| 282 | /** | 282 | /** |
| 283 | * omap_device_get_context_loss_count - get lost context count | ||
| 284 | * @od: struct omap_device * | ||
| 285 | * | ||
| 286 | * Using the primary hwmod, query the context loss count for this | ||
| 287 | * device. | ||
| 288 | * | ||
| 289 | * Callers should consider context for this device lost any time this | ||
| 290 | * function returns a value different than the value the caller got | ||
| 291 | * the last time it called this function. | ||
| 292 | * | ||
| 293 | * If any hwmods exist for the omap_device assoiated with @pdev, | ||
| 294 | * return the context loss counter for that hwmod, otherwise return | ||
| 295 | * zero. | ||
| 296 | */ | ||
| 297 | u32 omap_device_get_context_loss_count(struct platform_device *pdev) | ||
| 298 | { | ||
| 299 | struct omap_device *od; | ||
| 300 | u32 ret = 0; | ||
| 301 | |||
| 302 | od = _find_by_pdev(pdev); | ||
| 303 | |||
| 304 | if (od->hwmods_cnt) | ||
| 305 | ret = omap_hwmod_get_context_loss_count(od->hwmods[0]); | ||
| 306 | |||
| 307 | return ret; | ||
| 308 | } | ||
| 309 | |||
| 310 | /** | ||
| 283 | * omap_device_count_resources - count number of struct resource entries needed | 311 | * omap_device_count_resources - count number of struct resource entries needed |
| 284 | * @od: struct omap_device * | 312 | * @od: struct omap_device * |
| 285 | * | 313 | * |
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 74dac419d328..e26e50487d60 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c | |||
| @@ -33,23 +33,21 @@ | |||
| 33 | 33 | ||
| 34 | #include "sram.h" | 34 | #include "sram.h" |
| 35 | #include "fb.h" | 35 | #include "fb.h" |
| 36 | |||
| 37 | /* XXX These "sideways" includes are a sign that something is wrong */ | ||
| 36 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) | 38 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
| 37 | # include "../mach-omap2/prm.h" | 39 | # include "../mach-omap2/prm2xxx_3xxx.h" |
| 38 | # include "../mach-omap2/cm.h" | ||
| 39 | # include "../mach-omap2/sdrc.h" | 40 | # include "../mach-omap2/sdrc.h" |
| 40 | #endif | 41 | #endif |
| 41 | 42 | ||
| 42 | #define OMAP1_SRAM_PA 0x20000000 | 43 | #define OMAP1_SRAM_PA 0x20000000 |
| 43 | #define OMAP1_SRAM_VA VMALLOC_END | 44 | #define OMAP1_SRAM_VA VMALLOC_END |
| 44 | #define OMAP2_SRAM_PA 0x40200000 | 45 | #define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800) |
| 45 | #define OMAP2_SRAM_PUB_PA 0x4020f800 | ||
| 46 | #define OMAP2_SRAM_VA 0xfe400000 | 46 | #define OMAP2_SRAM_VA 0xfe400000 |
| 47 | #define OMAP2_SRAM_PUB_VA (OMAP2_SRAM_VA + 0x800) | 47 | #define OMAP2_SRAM_PUB_VA (OMAP2_SRAM_VA + 0x800) |
| 48 | #define OMAP3_SRAM_PA 0x40200000 | ||
| 49 | #define OMAP3_SRAM_VA 0xfe400000 | 48 | #define OMAP3_SRAM_VA 0xfe400000 |
| 50 | #define OMAP3_SRAM_PUB_PA 0x40208000 | 49 | #define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000) |
| 51 | #define OMAP3_SRAM_PUB_VA (OMAP3_SRAM_VA + 0x8000) | 50 | #define OMAP3_SRAM_PUB_VA (OMAP3_SRAM_VA + 0x8000) |
| 52 | #define OMAP4_SRAM_PA 0x40300000 | ||
| 53 | #define OMAP4_SRAM_VA 0xfe400000 | 51 | #define OMAP4_SRAM_VA 0xfe400000 |
| 54 | #define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000) | 52 | #define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000) |
| 55 | #define OMAP4_SRAM_PUB_VA (OMAP4_SRAM_VA + 0x4000) | 53 | #define OMAP4_SRAM_PUB_VA (OMAP4_SRAM_VA + 0x4000) |
| @@ -270,7 +268,7 @@ void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl) | |||
| 270 | _omap_sram_reprogram_clock(dpllctl, ckctl); | 268 | _omap_sram_reprogram_clock(dpllctl, ckctl); |
| 271 | } | 269 | } |
| 272 | 270 | ||
| 273 | int __init omap1_sram_init(void) | 271 | static int __init omap1_sram_init(void) |
| 274 | { | 272 | { |
| 275 | _omap_sram_reprogram_clock = | 273 | _omap_sram_reprogram_clock = |
| 276 | omap_sram_push(omap1_sram_reprogram_clock, | 274 | omap_sram_push(omap1_sram_reprogram_clock, |
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c index 715a30177f28..c3da2478b2aa 100644 --- a/arch/arm/plat-orion/time.c +++ b/arch/arm/plat-orion/time.c | |||
| @@ -13,11 +13,11 @@ | |||
| 13 | 13 | ||
| 14 | #include <linux/kernel.h> | 14 | #include <linux/kernel.h> |
| 15 | #include <linux/sched.h> | 15 | #include <linux/sched.h> |
| 16 | #include <linux/cnt32_to_63.h> | ||
| 17 | #include <linux/timer.h> | 16 | #include <linux/timer.h> |
| 18 | #include <linux/clockchips.h> | 17 | #include <linux/clockchips.h> |
| 19 | #include <linux/interrupt.h> | 18 | #include <linux/interrupt.h> |
| 20 | #include <linux/irq.h> | 19 | #include <linux/irq.h> |
| 20 | #include <asm/sched_clock.h> | ||
| 21 | #include <asm/mach/time.h> | 21 | #include <asm/mach/time.h> |
| 22 | #include <mach/bridge-regs.h> | 22 | #include <mach/bridge-regs.h> |
| 23 | #include <mach/hardware.h> | 23 | #include <mach/hardware.h> |
| @@ -44,52 +44,26 @@ static u32 ticks_per_jiffy; | |||
| 44 | 44 | ||
| 45 | /* | 45 | /* |
| 46 | * Orion's sched_clock implementation. It has a resolution of | 46 | * Orion's sched_clock implementation. It has a resolution of |
| 47 | * at least 7.5ns (133MHz TCLK) and a maximum value of 834 days. | 47 | * at least 7.5ns (133MHz TCLK). |
| 48 | * | ||
| 49 | * Because the hardware timer period is quite short (21 secs if | ||
| 50 | * 200MHz TCLK) and because cnt32_to_63() needs to be called at | ||
| 51 | * least once per half period to work properly, a kernel timer is | ||
| 52 | * set up to ensure this requirement is always met. | ||
| 53 | */ | 48 | */ |
| 54 | #define TCLK2NS_SCALE_FACTOR 8 | 49 | static DEFINE_CLOCK_DATA(cd); |
| 55 | |||
| 56 | static unsigned long tclk2ns_scale; | ||
| 57 | 50 | ||
| 58 | unsigned long long sched_clock(void) | 51 | unsigned long long notrace sched_clock(void) |
| 59 | { | 52 | { |
| 60 | unsigned long long v = cnt32_to_63(0xffffffff - readl(TIMER0_VAL)); | 53 | u32 cyc = 0xffffffff - readl(TIMER0_VAL); |
| 61 | return (v * tclk2ns_scale) >> TCLK2NS_SCALE_FACTOR; | 54 | return cyc_to_sched_clock(&cd, cyc, (u32)~0); |
| 62 | } | 55 | } |
| 63 | 56 | ||
| 64 | static struct timer_list cnt32_to_63_keepwarm_timer; | ||
| 65 | 57 | ||
| 66 | static void cnt32_to_63_keepwarm(unsigned long data) | 58 | static void notrace orion_update_sched_clock(void) |
| 67 | { | 59 | { |
| 68 | mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data)); | 60 | u32 cyc = 0xffffffff - readl(TIMER0_VAL); |
| 69 | (void) sched_clock(); | 61 | update_sched_clock(&cd, cyc, (u32)~0); |
| 70 | } | 62 | } |
| 71 | 63 | ||
| 72 | static void __init setup_sched_clock(unsigned long tclk) | 64 | static void __init setup_sched_clock(unsigned long tclk) |
| 73 | { | 65 | { |
| 74 | unsigned long long v; | 66 | init_sched_clock(&cd, orion_update_sched_clock, 32, tclk); |
| 75 | unsigned long data; | ||
| 76 | |||
| 77 | v = NSEC_PER_SEC; | ||
| 78 | v <<= TCLK2NS_SCALE_FACTOR; | ||
| 79 | v += tclk/2; | ||
| 80 | do_div(v, tclk); | ||
| 81 | /* | ||
| 82 | * We want an even value to automatically clear the top bit | ||
| 83 | * returned by cnt32_to_63() without an additional run time | ||
| 84 | * instruction. So if the LSB is 1 then round it up. | ||
| 85 | */ | ||
| 86 | if (v & 1) | ||
| 87 | v++; | ||
| 88 | tclk2ns_scale = v; | ||
| 89 | |||
| 90 | data = (0xffffffffUL / tclk / 2 - 2) * HZ; | ||
| 91 | setup_timer(&cnt32_to_63_keepwarm_timer, cnt32_to_63_keepwarm, data); | ||
| 92 | mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data)); | ||
| 93 | } | 67 | } |
| 94 | 68 | ||
| 95 | /* | 69 | /* |
| @@ -102,7 +76,6 @@ static cycle_t orion_clksrc_read(struct clocksource *cs) | |||
| 102 | 76 | ||
| 103 | static struct clocksource orion_clksrc = { | 77 | static struct clocksource orion_clksrc = { |
| 104 | .name = "orion_clocksource", | 78 | .name = "orion_clocksource", |
| 105 | .shift = 20, | ||
| 106 | .rating = 300, | 79 | .rating = 300, |
| 107 | .read = orion_clksrc_read, | 80 | .read = orion_clksrc_read, |
| 108 | .mask = CLOCKSOURCE_MASK(32), | 81 | .mask = CLOCKSOURCE_MASK(32), |
| @@ -245,8 +218,7 @@ void __init orion_time_init(unsigned int irq, unsigned int tclk) | |||
| 245 | writel(u & ~BRIDGE_INT_TIMER0, BRIDGE_MASK); | 218 | writel(u & ~BRIDGE_INT_TIMER0, BRIDGE_MASK); |
| 246 | u = readl(TIMER_CTRL); | 219 | u = readl(TIMER_CTRL); |
| 247 | writel(u | TIMER0_EN | TIMER0_RELOAD_EN, TIMER_CTRL); | 220 | writel(u | TIMER0_EN | TIMER0_RELOAD_EN, TIMER_CTRL); |
| 248 | orion_clksrc.mult = clocksource_hz2mult(tclk, orion_clksrc.shift); | 221 | clocksource_register_hz(&orion_clksrc, tclk); |
| 249 | clocksource_register(&orion_clksrc); | ||
| 250 | 222 | ||
| 251 | /* | 223 | /* |
| 252 | * Setup clockevent timer (interrupt-driven.) | 224 | * Setup clockevent timer (interrupt-driven.) |
diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile index 4aacdd12c9cc..3aca5ba0f876 100644 --- a/arch/arm/plat-pxa/Makefile +++ b/arch/arm/plat-pxa/Makefile | |||
| @@ -6,6 +6,7 @@ obj-y := dma.o | |||
| 6 | 6 | ||
| 7 | obj-$(CONFIG_GENERIC_GPIO) += gpio.o | 7 | obj-$(CONFIG_GENERIC_GPIO) += gpio.o |
| 8 | obj-$(CONFIG_PXA3xx) += mfp.o | 8 | obj-$(CONFIG_PXA3xx) += mfp.o |
| 9 | obj-$(CONFIG_PXA95x) += mfp.o | ||
| 9 | obj-$(CONFIG_ARCH_MMP) += mfp.o | 10 | obj-$(CONFIG_ARCH_MMP) += mfp.o |
| 10 | 11 | ||
| 11 | obj-$(CONFIG_HAVE_PWM) += pwm.o | 12 | obj-$(CONFIG_HAVE_PWM) += pwm.o |
diff --git a/arch/arm/plat-pxa/include/plat/mfp.h b/arch/arm/plat-pxa/include/plat/mfp.h index 9e604c80618f..75f656471240 100644 --- a/arch/arm/plat-pxa/include/plat/mfp.h +++ b/arch/arm/plat-pxa/include/plat/mfp.h | |||
| @@ -423,7 +423,7 @@ typedef unsigned long mfp_cfg_t; | |||
| 423 | ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\ | 423 | ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\ |
| 424 | (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm)) | 424 | (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm)) |
| 425 | 425 | ||
| 426 | #if defined(CONFIG_PXA3xx) || defined(CONFIG_ARCH_MMP) | 426 | #if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x) || defined(CONFIG_ARCH_MMP) |
| 427 | /* | 427 | /* |
| 428 | * each MFP pin will have a MFPR register, since the offset of the | 428 | * each MFP pin will have a MFPR register, since the offset of the |
| 429 | * register varies between processors, the processor specific code | 429 | * register varies between processors, the processor specific code |
| @@ -470,6 +470,6 @@ void mfp_write(int mfp, unsigned long mfpr_val); | |||
| 470 | void mfp_config(unsigned long *mfp_cfgs, int num); | 470 | void mfp_config(unsigned long *mfp_cfgs, int num); |
| 471 | void mfp_config_run(void); | 471 | void mfp_config_run(void); |
| 472 | void mfp_config_lpm(void); | 472 | void mfp_config_lpm(void); |
| 473 | #endif /* CONFIG_PXA3xx || CONFIG_ARCH_MMP */ | 473 | #endif /* CONFIG_PXA3xx || CONFIG_PXA95x || CONFIG_ARCH_MMP */ |
| 474 | 474 | ||
| 475 | #endif /* __ASM_PLAT_MFP_H */ | 475 | #endif /* __ASM_PLAT_MFP_H */ |
diff --git a/arch/arm/plat-pxa/include/plat/ssp.h b/arch/arm/plat-pxa/include/plat/ssp.h deleted file mode 100644 index fe43150690ed..000000000000 --- a/arch/arm/plat-pxa/include/plat/ssp.h +++ /dev/null | |||
| @@ -1,186 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * ssp.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 Russell King, All Rights Reserved. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * This driver supports the following PXA CPU/SSP ports:- | ||
| 11 | * | ||
| 12 | * PXA250 SSP | ||
| 13 | * PXA255 SSP, NSSP | ||
| 14 | * PXA26x SSP, NSSP, ASSP | ||
| 15 | * PXA27x SSP1, SSP2, SSP3 | ||
| 16 | * PXA3xx SSP1, SSP2, SSP3, SSP4 | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef __ASM_ARCH_SSP_H | ||
| 20 | #define __ASM_ARCH_SSP_H | ||
| 21 | |||
| 22 | #include <linux/list.h> | ||
| 23 | #include <linux/io.h> | ||
| 24 | |||
| 25 | /* | ||
| 26 | * SSP Serial Port Registers | ||
| 27 | * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different. | ||
| 28 | * PXA255, PXA26x and PXA27x have extra ports, registers and bits. | ||
| 29 | */ | ||
| 30 | |||
| 31 | #define SSCR0 (0x00) /* SSP Control Register 0 */ | ||
| 32 | #define SSCR1 (0x04) /* SSP Control Register 1 */ | ||
| 33 | #define SSSR (0x08) /* SSP Status Register */ | ||
| 34 | #define SSITR (0x0C) /* SSP Interrupt Test Register */ | ||
| 35 | #define SSDR (0x10) /* SSP Data Write/Data Read Register */ | ||
| 36 | |||
| 37 | #define SSTO (0x28) /* SSP Time Out Register */ | ||
| 38 | #define SSPSP (0x2C) /* SSP Programmable Serial Protocol */ | ||
| 39 | #define SSTSA (0x30) /* SSP Tx Timeslot Active */ | ||
| 40 | #define SSRSA (0x34) /* SSP Rx Timeslot Active */ | ||
| 41 | #define SSTSS (0x38) /* SSP Timeslot Status */ | ||
| 42 | #define SSACD (0x3C) /* SSP Audio Clock Divider */ | ||
| 43 | #define SSACDD (0x40) /* SSP Audio Clock Dither Divider */ | ||
| 44 | |||
| 45 | /* Common PXA2xx bits first */ | ||
| 46 | #define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */ | ||
| 47 | #define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */ | ||
| 48 | #define SSCR0_FRF (0x00000030) /* FRame Format (mask) */ | ||
| 49 | #define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */ | ||
| 50 | #define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */ | ||
| 51 | #define SSCR0_National (0x2 << 4) /* National Microwire */ | ||
| 52 | #define SSCR0_ECS (1 << 6) /* External clock select */ | ||
| 53 | #define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */ | ||
| 54 | #define SSCR0_SCR(x) ((x) << 8) /* Serial Clock Rate (mask) */ | ||
| 55 | |||
| 56 | /* PXA27x, PXA3xx */ | ||
| 57 | #define SSCR0_EDSS (1 << 20) /* Extended data size select */ | ||
| 58 | #define SSCR0_NCS (1 << 21) /* Network clock select */ | ||
| 59 | #define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */ | ||
| 60 | #define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */ | ||
| 61 | #define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */ | ||
| 62 | #define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */ | ||
| 63 | #define SSCR0_FPCKE (1 << 29) /* FIFO packing enable */ | ||
| 64 | #define SSCR0_ACS (1 << 30) /* Audio clock select */ | ||
| 65 | #define SSCR0_MOD (1 << 31) /* Mode (normal or network) */ | ||
| 66 | |||
| 67 | |||
| 68 | #define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ | ||
| 69 | #define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ | ||
| 70 | #define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ | ||
| 71 | #define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */ | ||
| 72 | #define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */ | ||
| 73 | #define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */ | ||
| 74 | #define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */ | ||
| 75 | #define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */ | ||
| 76 | #define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */ | ||
| 77 | #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */ | ||
| 78 | |||
| 79 | #define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */ | ||
| 80 | #define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */ | ||
| 81 | #define SSSR_BSY (1 << 4) /* SSP Busy */ | ||
| 82 | #define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */ | ||
| 83 | #define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */ | ||
| 84 | #define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */ | ||
| 85 | |||
| 86 | |||
| 87 | /* extra bits in PXA255, PXA26x and PXA27x SSP ports */ | ||
| 88 | #define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */ | ||
| 89 | #define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */ | ||
| 90 | #define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */ | ||
| 91 | #define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */ | ||
| 92 | #define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */ | ||
| 93 | #define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */ | ||
| 94 | #define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */ | ||
| 95 | #define SSCR1_ECRB (1 << 26) /* Enable Clock request B */ | ||
| 96 | #define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */ | ||
| 97 | #define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */ | ||
| 98 | #define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */ | ||
| 99 | #define SSCR1_TRAIL (1 << 22) /* Trailing Byte */ | ||
| 100 | #define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */ | ||
| 101 | #define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */ | ||
| 102 | #define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */ | ||
| 103 | #define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */ | ||
| 104 | #define SSCR1_IFS (1 << 16) /* Invert Frame Signal */ | ||
| 105 | #define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */ | ||
| 106 | #define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */ | ||
| 107 | |||
| 108 | #define SSSR_BCE (1 << 23) /* Bit Count Error */ | ||
| 109 | #define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */ | ||
| 110 | #define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */ | ||
| 111 | #define SSSR_EOC (1 << 20) /* End Of Chain */ | ||
| 112 | #define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */ | ||
| 113 | #define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */ | ||
| 114 | |||
| 115 | |||
| 116 | #define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */ | ||
| 117 | #define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */ | ||
| 118 | #define SSPSP_ETDS (1 << 3) /* End of Transfer data State */ | ||
| 119 | #define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */ | ||
| 120 | #define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */ | ||
| 121 | #define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */ | ||
| 122 | #define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */ | ||
| 123 | #define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */ | ||
| 124 | #define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */ | ||
| 125 | |||
| 126 | /* PXA3xx */ | ||
| 127 | #define SSPSP_EDMYSTRT(x) ((x) << 26) /* Extended Dummy Start */ | ||
| 128 | #define SSPSP_EDMYSTOP(x) ((x) << 28) /* Extended Dummy Stop */ | ||
| 129 | #define SSPSP_TIMING_MASK (0x7f8001f0) | ||
| 130 | |||
| 131 | #define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */ | ||
| 132 | #define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */ | ||
| 133 | #define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */ | ||
| 134 | #define SSACD_SCDX8 (1 << 7) /* SYSCLK division ratio select */ | ||
| 135 | |||
| 136 | enum pxa_ssp_type { | ||
| 137 | SSP_UNDEFINED = 0, | ||
| 138 | PXA25x_SSP, /* pxa 210, 250, 255, 26x */ | ||
| 139 | PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */ | ||
| 140 | PXA27x_SSP, | ||
| 141 | PXA168_SSP, | ||
| 142 | }; | ||
| 143 | |||
| 144 | struct ssp_device { | ||
| 145 | struct platform_device *pdev; | ||
| 146 | struct list_head node; | ||
| 147 | |||
| 148 | struct clk *clk; | ||
| 149 | void __iomem *mmio_base; | ||
| 150 | unsigned long phys_base; | ||
| 151 | |||
| 152 | const char *label; | ||
| 153 | int port_id; | ||
| 154 | int type; | ||
| 155 | int use_count; | ||
| 156 | int irq; | ||
| 157 | int drcmr_rx; | ||
| 158 | int drcmr_tx; | ||
| 159 | }; | ||
| 160 | |||
| 161 | /** | ||
| 162 | * pxa_ssp_write_reg - Write to a SSP register | ||
| 163 | * | ||
| 164 | * @dev: SSP device to access | ||
| 165 | * @reg: Register to write to | ||
| 166 | * @val: Value to be written. | ||
| 167 | */ | ||
| 168 | static inline void pxa_ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val) | ||
| 169 | { | ||
| 170 | __raw_writel(val, dev->mmio_base + reg); | ||
| 171 | } | ||
| 172 | |||
| 173 | /** | ||
| 174 | * pxa_ssp_read_reg - Read from a SSP register | ||
| 175 | * | ||
| 176 | * @dev: SSP device to access | ||
| 177 | * @reg: Register to read from | ||
| 178 | */ | ||
| 179 | static inline u32 pxa_ssp_read_reg(struct ssp_device *dev, u32 reg) | ||
| 180 | { | ||
| 181 | return __raw_readl(dev->mmio_base + reg); | ||
| 182 | } | ||
| 183 | |||
| 184 | struct ssp_device *pxa_ssp_request(int port, const char *label); | ||
| 185 | void pxa_ssp_free(struct ssp_device *); | ||
| 186 | #endif /* __ASM_ARCH_SSP_H */ | ||
diff --git a/arch/arm/plat-pxa/ssp.c b/arch/arm/plat-pxa/ssp.c index c6357e554aba..58b79809d20c 100644 --- a/arch/arm/plat-pxa/ssp.c +++ b/arch/arm/plat-pxa/ssp.c | |||
| @@ -28,11 +28,11 @@ | |||
| 28 | #include <linux/clk.h> | 28 | #include <linux/clk.h> |
| 29 | #include <linux/err.h> | 29 | #include <linux/err.h> |
| 30 | #include <linux/platform_device.h> | 30 | #include <linux/platform_device.h> |
| 31 | #include <linux/spi/pxa2xx_spi.h> | ||
| 31 | #include <linux/io.h> | 32 | #include <linux/io.h> |
| 32 | 33 | ||
| 33 | #include <asm/irq.h> | 34 | #include <asm/irq.h> |
| 34 | #include <mach/hardware.h> | 35 | #include <mach/hardware.h> |
| 35 | #include <plat/ssp.h> | ||
| 36 | 36 | ||
| 37 | static DEFINE_MUTEX(ssp_lock); | 37 | static DEFINE_MUTEX(ssp_lock); |
| 38 | static LIST_HEAD(ssp_list); | 38 | static LIST_HEAD(ssp_list); |
diff --git a/arch/arm/plat-s3c24xx/cpu-freq.c b/arch/arm/plat-s3c24xx/cpu-freq.c index 1ecc15bfe9d4..25a8fc7f512e 100644 --- a/arch/arm/plat-s3c24xx/cpu-freq.c +++ b/arch/arm/plat-s3c24xx/cpu-freq.c | |||
| @@ -21,7 +21,6 @@ | |||
| 21 | #include <linux/err.h> | 21 | #include <linux/err.h> |
| 22 | #include <linux/io.h> | 22 | #include <linux/io.h> |
| 23 | #include <linux/sysdev.h> | 23 | #include <linux/sysdev.h> |
| 24 | #include <linux/kobject.h> | ||
| 25 | #include <linux/sysfs.h> | 24 | #include <linux/sysfs.h> |
| 26 | #include <linux/slab.h> | 25 | #include <linux/slab.h> |
| 27 | 26 | ||
diff --git a/arch/arm/plat-spear/include/plat/clock.h b/arch/arm/plat-spear/include/plat/clock.h index 298bafc0a52f..2572260f990f 100644 --- a/arch/arm/plat-spear/include/plat/clock.h +++ b/arch/arm/plat-spear/include/plat/clock.h | |||
| @@ -15,7 +15,7 @@ | |||
| 15 | #define __PLAT_CLOCK_H | 15 | #define __PLAT_CLOCK_H |
| 16 | 16 | ||
| 17 | #include <linux/list.h> | 17 | #include <linux/list.h> |
| 18 | #include <asm/clkdev.h> | 18 | #include <linux/clkdev.h> |
| 19 | #include <linux/types.h> | 19 | #include <linux/types.h> |
| 20 | 20 | ||
| 21 | /* clk structure flags */ | 21 | /* clk structure flags */ |
diff --git a/arch/arm/plat-spear/include/plat/keyboard.h b/arch/arm/plat-spear/include/plat/keyboard.h new file mode 100644 index 000000000000..68b5394fc583 --- /dev/null +++ b/arch/arm/plat-spear/include/plat/keyboard.h | |||
| @@ -0,0 +1,141 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 ST Microelectronics | ||
| 3 | * Rajeev Kumar<rajeev-dlh.kumar@st.com> | ||
| 4 | * | ||
| 5 | * This file is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2. This program is licensed "as is" without any | ||
| 7 | * warranty of any kind, whether express or implied. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __PLAT_KEYBOARD_H | ||
| 11 | #define __PLAT_KEYBOARD_H | ||
| 12 | |||
| 13 | #include <linux/bitops.h> | ||
| 14 | #include <linux/input.h> | ||
| 15 | #include <linux/input/matrix_keypad.h> | ||
| 16 | #include <linux/types.h> | ||
| 17 | |||
| 18 | #define DECLARE_KEYMAP(_name) \ | ||
| 19 | int _name[] = { \ | ||
| 20 | KEY(0, 0, KEY_ESC), \ | ||
| 21 | KEY(0, 1, KEY_1), \ | ||
| 22 | KEY(0, 2, KEY_2), \ | ||
| 23 | KEY(0, 3, KEY_3), \ | ||
| 24 | KEY(0, 4, KEY_4), \ | ||
| 25 | KEY(0, 5, KEY_5), \ | ||
| 26 | KEY(0, 6, KEY_6), \ | ||
| 27 | KEY(0, 7, KEY_7), \ | ||
| 28 | KEY(0, 8, KEY_8), \ | ||
| 29 | KEY(1, 0, KEY_9), \ | ||
| 30 | KEY(1, 1, KEY_MINUS), \ | ||
| 31 | KEY(1, 2, KEY_EQUAL), \ | ||
| 32 | KEY(1, 3, KEY_BACKSPACE), \ | ||
| 33 | KEY(1, 4, KEY_TAB), \ | ||
| 34 | KEY(1, 5, KEY_Q), \ | ||
| 35 | KEY(1, 6, KEY_W), \ | ||
| 36 | KEY(1, 7, KEY_E), \ | ||
| 37 | KEY(1, 8, KEY_R), \ | ||
| 38 | KEY(2, 0, KEY_T), \ | ||
| 39 | KEY(2, 1, KEY_Y), \ | ||
| 40 | KEY(2, 2, KEY_U), \ | ||
| 41 | KEY(2, 3, KEY_I), \ | ||
| 42 | KEY(2, 4, KEY_O), \ | ||
| 43 | KEY(2, 5, KEY_P), \ | ||
| 44 | KEY(2, 6, KEY_LEFTBRACE), \ | ||
| 45 | KEY(2, 7, KEY_RIGHTBRACE), \ | ||
| 46 | KEY(2, 8, KEY_ENTER), \ | ||
| 47 | KEY(3, 0, KEY_LEFTCTRL), \ | ||
| 48 | KEY(3, 1, KEY_A), \ | ||
| 49 | KEY(3, 2, KEY_S), \ | ||
| 50 | KEY(3, 3, KEY_D), \ | ||
| 51 | KEY(3, 4, KEY_F), \ | ||
| 52 | KEY(3, 5, KEY_G), \ | ||
| 53 | KEY(3, 6, KEY_H), \ | ||
| 54 | KEY(3, 7, KEY_J), \ | ||
| 55 | KEY(3, 8, KEY_K), \ | ||
| 56 | KEY(4, 0, KEY_L), \ | ||
| 57 | KEY(4, 1, KEY_SEMICOLON), \ | ||
| 58 | KEY(4, 2, KEY_APOSTROPHE), \ | ||
| 59 | KEY(4, 3, KEY_GRAVE), \ | ||
| 60 | KEY(4, 4, KEY_LEFTSHIFT), \ | ||
| 61 | KEY(4, 5, KEY_BACKSLASH), \ | ||
| 62 | KEY(4, 6, KEY_Z), \ | ||
| 63 | KEY(4, 7, KEY_X), \ | ||
| 64 | KEY(4, 8, KEY_C), \ | ||
| 65 | KEY(4, 0, KEY_L), \ | ||
| 66 | KEY(4, 1, KEY_SEMICOLON), \ | ||
| 67 | KEY(4, 2, KEY_APOSTROPHE), \ | ||
| 68 | KEY(4, 3, KEY_GRAVE), \ | ||
| 69 | KEY(4, 4, KEY_LEFTSHIFT), \ | ||
| 70 | KEY(4, 5, KEY_BACKSLASH), \ | ||
| 71 | KEY(4, 6, KEY_Z), \ | ||
| 72 | KEY(4, 7, KEY_X), \ | ||
| 73 | KEY(4, 8, KEY_C), \ | ||
| 74 | KEY(4, 0, KEY_L), \ | ||
| 75 | KEY(4, 1, KEY_SEMICOLON), \ | ||
| 76 | KEY(4, 2, KEY_APOSTROPHE), \ | ||
| 77 | KEY(4, 3, KEY_GRAVE), \ | ||
| 78 | KEY(4, 4, KEY_LEFTSHIFT), \ | ||
| 79 | KEY(4, 5, KEY_BACKSLASH), \ | ||
| 80 | KEY(4, 6, KEY_Z), \ | ||
| 81 | KEY(4, 7, KEY_X), \ | ||
| 82 | KEY(4, 8, KEY_C), \ | ||
| 83 | KEY(5, 0, KEY_V), \ | ||
| 84 | KEY(5, 1, KEY_B), \ | ||
| 85 | KEY(5, 2, KEY_N), \ | ||
| 86 | KEY(5, 3, KEY_M), \ | ||
| 87 | KEY(5, 4, KEY_COMMA), \ | ||
| 88 | KEY(5, 5, KEY_DOT), \ | ||
| 89 | KEY(5, 6, KEY_SLASH), \ | ||
| 90 | KEY(5, 7, KEY_RIGHTSHIFT), \ | ||
| 91 | KEY(5, 8, KEY_KPASTERISK), \ | ||
| 92 | KEY(6, 0, KEY_LEFTALT), \ | ||
| 93 | KEY(6, 1, KEY_SPACE), \ | ||
| 94 | KEY(6, 2, KEY_CAPSLOCK), \ | ||
| 95 | KEY(6, 3, KEY_F1), \ | ||
| 96 | KEY(6, 4, KEY_F2), \ | ||
| 97 | KEY(6, 5, KEY_F3), \ | ||
| 98 | KEY(6, 6, KEY_F4), \ | ||
| 99 | KEY(6, 7, KEY_F5), \ | ||
| 100 | KEY(6, 8, KEY_F6), \ | ||
| 101 | KEY(7, 0, KEY_F7), \ | ||
| 102 | KEY(7, 1, KEY_F8), \ | ||
| 103 | KEY(7, 2, KEY_F9), \ | ||
| 104 | KEY(7, 3, KEY_F10), \ | ||
| 105 | KEY(7, 4, KEY_NUMLOCK), \ | ||
| 106 | KEY(7, 5, KEY_SCROLLLOCK), \ | ||
| 107 | KEY(7, 6, KEY_KP7), \ | ||
| 108 | KEY(7, 7, KEY_KP8), \ | ||
| 109 | KEY(7, 8, KEY_KP9), \ | ||
| 110 | KEY(8, 0, KEY_KPMINUS), \ | ||
| 111 | KEY(8, 1, KEY_KP4), \ | ||
| 112 | KEY(8, 2, KEY_KP5), \ | ||
| 113 | KEY(8, 3, KEY_KP6), \ | ||
| 114 | KEY(8, 4, KEY_KPPLUS), \ | ||
| 115 | KEY(8, 5, KEY_KP1), \ | ||
| 116 | KEY(8, 6, KEY_KP2), \ | ||
| 117 | KEY(8, 7, KEY_KP3), \ | ||
| 118 | KEY(8, 8, KEY_KP0), \ | ||
| 119 | } | ||
| 120 | |||
| 121 | /** | ||
| 122 | * struct kbd_platform_data - spear keyboard platform data | ||
| 123 | * keymap: pointer to keymap data (table and size) | ||
| 124 | * rep: enables key autorepeat | ||
| 125 | * | ||
| 126 | * This structure is supposed to be used by platform code to supply | ||
| 127 | * keymaps to drivers that implement keyboards. | ||
| 128 | */ | ||
| 129 | struct kbd_platform_data { | ||
| 130 | const struct matrix_keymap_data *keymap; | ||
| 131 | bool rep; | ||
| 132 | }; | ||
| 133 | |||
| 134 | /* This function is used to set platform data field of pdev->dev */ | ||
| 135 | static inline void | ||
| 136 | kbd_set_plat_data(struct platform_device *pdev, struct kbd_platform_data *data) | ||
| 137 | { | ||
| 138 | pdev->dev.platform_data = data; | ||
| 139 | } | ||
| 140 | |||
| 141 | #endif /* __PLAT_KEYBOARD_H */ | ||
diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c index ab211652e4ca..839c88df9994 100644 --- a/arch/arm/plat-spear/time.c +++ b/arch/arm/plat-spear/time.c | |||
| @@ -81,8 +81,6 @@ static struct clocksource clksrc = { | |||
| 81 | .rating = 200, /* its a pretty decent clock */ | 81 | .rating = 200, /* its a pretty decent clock */ |
| 82 | .read = clocksource_read_cycles, | 82 | .read = clocksource_read_cycles, |
| 83 | .mask = 0xFFFF, /* 16 bits */ | 83 | .mask = 0xFFFF, /* 16 bits */ |
| 84 | .mult = 0, /* to be computed */ | ||
| 85 | .shift = 0, /* to be computed */ | ||
| 86 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 84 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 87 | }; | 85 | }; |
| 88 | 86 | ||
| @@ -105,10 +103,8 @@ static void spear_clocksource_init(void) | |||
| 105 | val |= CTRL_ENABLE ; | 103 | val |= CTRL_ENABLE ; |
| 106 | writew(val, gpt_base + CR(CLKSRC)); | 104 | writew(val, gpt_base + CR(CLKSRC)); |
| 107 | 105 | ||
| 108 | clocksource_calc_mult_shift(&clksrc, tick_rate, SPEAR_MIN_RANGE); | ||
| 109 | |||
| 110 | /* register the clocksource */ | 106 | /* register the clocksource */ |
| 111 | clocksource_register(&clksrc); | 107 | clocksource_register_hz(&clksrc, tick_rate); |
| 112 | } | 108 | } |
| 113 | 109 | ||
| 114 | static struct clock_event_device clkevt = { | 110 | static struct clock_event_device clkevt = { |
diff --git a/arch/arm/plat-stmp3xxx/clock.c b/arch/arm/plat-stmp3xxx/clock.c index e593a2a801c6..2e712e17ce72 100644 --- a/arch/arm/plat-stmp3xxx/clock.c +++ b/arch/arm/plat-stmp3xxx/clock.c | |||
| @@ -25,9 +25,9 @@ | |||
| 25 | #include <linux/err.h> | 25 | #include <linux/err.h> |
| 26 | #include <linux/delay.h> | 26 | #include <linux/delay.h> |
| 27 | #include <linux/io.h> | 27 | #include <linux/io.h> |
| 28 | #include <linux/clkdev.h> | ||
| 28 | 29 | ||
| 29 | #include <asm/mach-types.h> | 30 | #include <asm/mach-types.h> |
| 30 | #include <asm/clkdev.h> | ||
| 31 | #include <mach/platform.h> | 31 | #include <mach/platform.h> |
| 32 | #include <mach/regs-clkctrl.h> | 32 | #include <mach/regs-clkctrl.h> |
| 33 | 33 | ||
diff --git a/arch/arm/plat-stmp3xxx/timer.c b/arch/arm/plat-stmp3xxx/timer.c index 063c7bc0e740..c395630a6edc 100644 --- a/arch/arm/plat-stmp3xxx/timer.c +++ b/arch/arm/plat-stmp3xxx/timer.c | |||
| @@ -89,7 +89,6 @@ static struct clocksource cksrc_stmp3xxx = { | |||
| 89 | .rating = 250, | 89 | .rating = 250, |
| 90 | .read = stmp3xxx_clock_read, | 90 | .read = stmp3xxx_clock_read, |
| 91 | .mask = CLOCKSOURCE_MASK(16), | 91 | .mask = CLOCKSOURCE_MASK(16), |
| 92 | .shift = 10, | ||
| 93 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 92 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 94 | }; | 93 | }; |
| 95 | 94 | ||
| @@ -106,8 +105,6 @@ static struct irqaction stmp3xxx_timer_irq = { | |||
| 106 | */ | 105 | */ |
| 107 | static void __init stmp3xxx_init_timer(void) | 106 | static void __init stmp3xxx_init_timer(void) |
| 108 | { | 107 | { |
| 109 | cksrc_stmp3xxx.mult = clocksource_hz2mult(CLOCK_TICK_RATE, | ||
| 110 | cksrc_stmp3xxx.shift); | ||
| 111 | ckevt_timrot.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, | 108 | ckevt_timrot.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, |
| 112 | ckevt_timrot.shift); | 109 | ckevt_timrot.shift); |
| 113 | ckevt_timrot.min_delta_ns = clockevent_delta2ns(2, &ckevt_timrot); | 110 | ckevt_timrot.min_delta_ns = clockevent_delta2ns(2, &ckevt_timrot); |
| @@ -140,7 +137,7 @@ static void __init stmp3xxx_init_timer(void) | |||
| 140 | 137 | ||
| 141 | setup_irq(IRQ_TIMER0, &stmp3xxx_timer_irq); | 138 | setup_irq(IRQ_TIMER0, &stmp3xxx_timer_irq); |
| 142 | 139 | ||
| 143 | clocksource_register(&cksrc_stmp3xxx); | 140 | clocksource_register_hz(&cksrc_stmp3xxx, CLOCK_TICK_RATE); |
| 144 | clockevents_register_device(&ckevt_timrot); | 141 | clockevents_register_device(&ckevt_timrot); |
| 145 | } | 142 | } |
| 146 | 143 | ||
diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile index 5cf88e8427b1..16dde0819934 100644 --- a/arch/arm/plat-versatile/Makefile +++ b/arch/arm/plat-versatile/Makefile | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | obj-y := clock.o | 1 | obj-y := clock.o |
| 2 | obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o | 2 | ifneq ($(CONFIG_ARCH_INTEGRATOR),y) |
| 3 | obj-$(CONFIG_ARCH_REALVIEW) += sched-clock.o | 3 | obj-y += sched-clock.o |
| 4 | obj-$(CONFIG_ARCH_VERSATILE) += sched-clock.o | 4 | endif |
| 5 | ifeq ($(CONFIG_LEDS_CLASS),y) | 5 | ifeq ($(CONFIG_LEDS_CLASS),y) |
| 6 | obj-$(CONFIG_ARCH_REALVIEW) += leds.o | 6 | obj-$(CONFIG_ARCH_REALVIEW) += leds.o |
| 7 | obj-$(CONFIG_ARCH_VERSATILE) += leds.o | 7 | obj-$(CONFIG_ARCH_VERSATILE) += leds.o |
diff --git a/arch/arm/plat-versatile/include/plat/sched_clock.h b/arch/arm/plat-versatile/include/plat/sched_clock.h new file mode 100644 index 000000000000..5c3e4fc9fa0c --- /dev/null +++ b/arch/arm/plat-versatile/include/plat/sched_clock.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #ifndef ARM_PLAT_SCHED_CLOCK_H | ||
| 2 | #define ARM_PLAT_SCHED_CLOCK_H | ||
| 3 | |||
| 4 | void versatile_sched_clock_init(void __iomem *, unsigned long); | ||
| 5 | |||
| 6 | #endif | ||
diff --git a/arch/arm/plat-versatile/sched-clock.c b/arch/arm/plat-versatile/sched-clock.c index 9768cf7e83d7..3d6a4c292cab 100644 --- a/arch/arm/plat-versatile/sched-clock.c +++ b/arch/arm/plat-versatile/sched-clock.c | |||
| @@ -18,36 +18,41 @@ | |||
| 18 | * along with this program; if not, write to the Free Software | 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 20 | */ | 20 | */ |
| 21 | #include <linux/cnt32_to_63.h> | ||
| 22 | #include <linux/io.h> | 21 | #include <linux/io.h> |
| 23 | #include <asm/div64.h> | 22 | #include <linux/sched.h> |
| 24 | 23 | ||
| 25 | #include <mach/hardware.h> | 24 | #include <asm/sched_clock.h> |
| 26 | #include <mach/platform.h> | 25 | #include <plat/sched_clock.h> |
| 27 | 26 | ||
| 28 | #ifdef VERSATILE_SYS_BASE | 27 | static DEFINE_CLOCK_DATA(cd); |
| 29 | #define REFCOUNTER (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET) | 28 | static void __iomem *ctr; |
| 30 | #endif | ||
| 31 | |||
| 32 | #ifdef REALVIEW_SYS_BASE | ||
| 33 | #define REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET) | ||
| 34 | #endif | ||
| 35 | 29 | ||
| 36 | /* | 30 | /* |
| 37 | * This is the Realview and Versatile sched_clock implementation. This | 31 | * Constants generated by clocks_calc_mult_shift(m, s, 24MHz, NSEC_PER_SEC, 60). |
| 38 | * has a resolution of 41.7ns, and a maximum value of about 35583 days. | 32 | * This gives a resolution of about 41ns and a wrap period of about 178s. |
| 39 | * | ||
| 40 | * The return value is guaranteed to be monotonic in that range as | ||
| 41 | * long as there is always less than 89 seconds between successive | ||
| 42 | * calls to this function. | ||
| 43 | */ | 33 | */ |
| 44 | unsigned long long sched_clock(void) | 34 | #define SC_MULT 2796202667u |
| 35 | #define SC_SHIFT 26 | ||
| 36 | |||
| 37 | unsigned long long notrace sched_clock(void) | ||
| 45 | { | 38 | { |
| 46 | unsigned long long v = cnt32_to_63(readl(REFCOUNTER)); | 39 | if (ctr) { |
| 40 | u32 cyc = readl(ctr); | ||
| 41 | return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, | ||
| 42 | SC_MULT, SC_SHIFT); | ||
| 43 | } else | ||
| 44 | return 0; | ||
| 45 | } | ||
| 47 | 46 | ||
| 48 | /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */ | 47 | static void notrace versatile_update_sched_clock(void) |
| 49 | v *= 125<<1; | 48 | { |
| 50 | do_div(v, 3<<1); | 49 | u32 cyc = readl(ctr); |
| 50 | update_sched_clock(&cd, cyc, (u32)~0); | ||
| 51 | } | ||
| 51 | 52 | ||
| 52 | return v; | 53 | void __init versatile_sched_clock_init(void __iomem *reg, unsigned long rate) |
| 54 | { | ||
| 55 | ctr = reg; | ||
| 56 | init_fixed_sched_clock(&cd, versatile_update_sched_clock, | ||
| 57 | 32, rate, SC_MULT, SC_SHIFT); | ||
| 53 | } | 58 | } |
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index 8063a322c790..0797cb528b46 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c | |||
| @@ -10,9 +10,12 @@ | |||
| 10 | */ | 10 | */ |
| 11 | #include <linux/module.h> | 11 | #include <linux/module.h> |
| 12 | #include <linux/types.h> | 12 | #include <linux/types.h> |
| 13 | #include <linux/cpu.h> | ||
| 13 | #include <linux/kernel.h> | 14 | #include <linux/kernel.h> |
| 15 | #include <linux/notifier.h> | ||
| 14 | #include <linux/signal.h> | 16 | #include <linux/signal.h> |
| 15 | #include <linux/sched.h> | 17 | #include <linux/sched.h> |
| 18 | #include <linux/smp.h> | ||
| 16 | #include <linux/init.h> | 19 | #include <linux/init.h> |
| 17 | 20 | ||
| 18 | #include <asm/cputype.h> | 21 | #include <asm/cputype.h> |
| @@ -484,7 +487,24 @@ void vfp_flush_hwstate(struct thread_info *thread) | |||
| 484 | put_cpu(); | 487 | put_cpu(); |
| 485 | } | 488 | } |
| 486 | 489 | ||
| 487 | #include <linux/smp.h> | 490 | /* |
| 491 | * VFP hardware can lose all context when a CPU goes offline. | ||
| 492 | * Safely clear our held state when a CPU has been killed, and | ||
| 493 | * re-enable access to VFP when the CPU comes back online. | ||
| 494 | * | ||
| 495 | * Both CPU_DYING and CPU_STARTING are called on the CPU which | ||
| 496 | * is being offlined/onlined. | ||
| 497 | */ | ||
| 498 | static int vfp_hotplug(struct notifier_block *b, unsigned long action, | ||
| 499 | void *hcpu) | ||
| 500 | { | ||
| 501 | if (action == CPU_DYING || action == CPU_DYING_FROZEN) { | ||
| 502 | unsigned int cpu = (long)hcpu; | ||
| 503 | last_VFP_context[cpu] = NULL; | ||
| 504 | } else if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) | ||
| 505 | vfp_enable(NULL); | ||
| 506 | return NOTIFY_OK; | ||
| 507 | } | ||
| 488 | 508 | ||
| 489 | /* | 509 | /* |
| 490 | * VFP support code initialisation. | 510 | * VFP support code initialisation. |
| @@ -514,6 +534,8 @@ static int __init vfp_init(void) | |||
| 514 | else if (vfpsid & FPSID_NODOUBLE) { | 534 | else if (vfpsid & FPSID_NODOUBLE) { |
| 515 | printk("no double precision support\n"); | 535 | printk("no double precision support\n"); |
| 516 | } else { | 536 | } else { |
| 537 | hotcpu_notifier(vfp_hotplug, 0); | ||
| 538 | |||
| 517 | smp_call_function(vfp_enable, NULL, 1); | 539 | smp_call_function(vfp_enable, NULL, 1); |
| 518 | 540 | ||
| 519 | VFP_arch = (vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT; /* Extract the architecture version */ | 541 | VFP_arch = (vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT; /* Extract the architecture version */ |