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-rw-r--r--arch/arm/plat-omap/dma.c7
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index c4b2b478b1a5..85363084cc1a 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -53,7 +53,7 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
53#endif 53#endif
54 54
55#define OMAP_DMA_ACTIVE 0x01 55#define OMAP_DMA_ACTIVE 0x01
56#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe 56#define OMAP2_DMA_CSR_CLEAR_MASK 0xffffffff
57 57
58#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec) 58#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
59 59
@@ -1873,7 +1873,7 @@ static int omap2_dma_handle_ch(int ch)
1873 printk(KERN_INFO "DMA misaligned error with device %d\n", 1873 printk(KERN_INFO "DMA misaligned error with device %d\n",
1874 dma_chan[ch].dev_id); 1874 dma_chan[ch].dev_id);
1875 1875
1876 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, ch); 1876 p->dma_write(status, CSR, ch);
1877 p->dma_write(1 << ch, IRQSTATUS_L0, ch); 1877 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1878 /* read back the register to flush the write */ 1878 /* read back the register to flush the write */
1879 p->dma_read(IRQSTATUS_L0, ch); 1879 p->dma_read(IRQSTATUS_L0, ch);
@@ -1893,10 +1893,9 @@ static int omap2_dma_handle_ch(int ch)
1893 OMAP_DMA_CHAIN_INCQHEAD(chain_id); 1893 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1894 1894
1895 status = p->dma_read(CSR, ch); 1895 status = p->dma_read(CSR, ch);
1896 p->dma_write(status, CSR, ch);
1896 } 1897 }
1897 1898
1898 p->dma_write(status, CSR, ch);
1899
1900 if (likely(dma_chan[ch].callback != NULL)) 1899 if (likely(dma_chan[ch].callback != NULL))
1901 dma_chan[ch].callback(ch, status, dma_chan[ch].data); 1900 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1902 1901