diff options
Diffstat (limited to 'arch/arm')
299 files changed, 6507 insertions, 3249 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8b0b743b4fb1..139212f38ad5 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
| @@ -260,6 +260,7 @@ config ARCH_INTEGRATOR | |||
| 260 | select ICST | 260 | select ICST |
| 261 | select GENERIC_CLOCKEVENTS | 261 | select GENERIC_CLOCKEVENTS |
| 262 | select PLAT_VERSATILE | 262 | select PLAT_VERSATILE |
| 263 | select PLAT_VERSATILE_CLOCK | ||
| 263 | select PLAT_VERSATILE_FPGA_IRQ | 264 | select PLAT_VERSATILE_FPGA_IRQ |
| 264 | select NEED_MACH_IO_H | 265 | select NEED_MACH_IO_H |
| 265 | select NEED_MACH_MEMORY_H | 266 | select NEED_MACH_MEMORY_H |
| @@ -277,6 +278,7 @@ config ARCH_REALVIEW | |||
| 277 | select GENERIC_CLOCKEVENTS | 278 | select GENERIC_CLOCKEVENTS |
| 278 | select ARCH_WANT_OPTIONAL_GPIOLIB | 279 | select ARCH_WANT_OPTIONAL_GPIOLIB |
| 279 | select PLAT_VERSATILE | 280 | select PLAT_VERSATILE |
| 281 | select PLAT_VERSATILE_CLOCK | ||
| 280 | select PLAT_VERSATILE_CLCD | 282 | select PLAT_VERSATILE_CLCD |
| 281 | select ARM_TIMER_SP804 | 283 | select ARM_TIMER_SP804 |
| 282 | select GPIO_PL061 if GPIOLIB | 284 | select GPIO_PL061 if GPIOLIB |
| @@ -295,6 +297,7 @@ config ARCH_VERSATILE | |||
| 295 | select ARCH_WANT_OPTIONAL_GPIOLIB | 297 | select ARCH_WANT_OPTIONAL_GPIOLIB |
| 296 | select NEED_MACH_IO_H if PCI | 298 | select NEED_MACH_IO_H if PCI |
| 297 | select PLAT_VERSATILE | 299 | select PLAT_VERSATILE |
| 300 | select PLAT_VERSATILE_CLOCK | ||
| 298 | select PLAT_VERSATILE_CLCD | 301 | select PLAT_VERSATILE_CLCD |
| 299 | select PLAT_VERSATILE_FPGA_IRQ | 302 | select PLAT_VERSATILE_FPGA_IRQ |
| 300 | select ARM_TIMER_SP804 | 303 | select ARM_TIMER_SP804 |
| @@ -307,7 +310,7 @@ config ARCH_VEXPRESS | |||
| 307 | select ARM_AMBA | 310 | select ARM_AMBA |
| 308 | select ARM_TIMER_SP804 | 311 | select ARM_TIMER_SP804 |
| 309 | select CLKDEV_LOOKUP | 312 | select CLKDEV_LOOKUP |
| 310 | select HAVE_MACH_CLKDEV | 313 | select COMMON_CLK |
| 311 | select GENERIC_CLOCKEVENTS | 314 | select GENERIC_CLOCKEVENTS |
| 312 | select HAVE_CLK | 315 | select HAVE_CLK |
| 313 | select HAVE_PATA_PLATFORM | 316 | select HAVE_PATA_PLATFORM |
| @@ -315,6 +318,7 @@ config ARCH_VEXPRESS | |||
| 315 | select NO_IOPORT | 318 | select NO_IOPORT |
| 316 | select PLAT_VERSATILE | 319 | select PLAT_VERSATILE |
| 317 | select PLAT_VERSATILE_CLCD | 320 | select PLAT_VERSATILE_CLCD |
| 321 | select REGULATOR_FIXED_VOLTAGE if REGULATOR | ||
| 318 | help | 322 | help |
| 319 | This enables support for the ARM Ltd Versatile Express boards. | 323 | This enables support for the ARM Ltd Versatile Express boards. |
| 320 | 324 | ||
| @@ -567,6 +571,7 @@ config ARCH_LPC32XX | |||
| 567 | select CLKDEV_LOOKUP | 571 | select CLKDEV_LOOKUP |
| 568 | select GENERIC_CLOCKEVENTS | 572 | select GENERIC_CLOCKEVENTS |
| 569 | select USE_OF | 573 | select USE_OF |
| 574 | select HAVE_PWM | ||
| 570 | help | 575 | help |
| 571 | Support for the NXP LPC32XX family of processors | 576 | Support for the NXP LPC32XX family of processors |
| 572 | 577 | ||
| @@ -936,6 +941,7 @@ config ARCH_DAVINCI | |||
| 936 | 941 | ||
| 937 | config ARCH_OMAP | 942 | config ARCH_OMAP |
| 938 | bool "TI OMAP" | 943 | bool "TI OMAP" |
| 944 | depends on MMU | ||
| 939 | select HAVE_CLK | 945 | select HAVE_CLK |
| 940 | select ARCH_REQUIRE_GPIOLIB | 946 | select ARCH_REQUIRE_GPIOLIB |
| 941 | select ARCH_HAS_CPUFREQ | 947 | select ARCH_HAS_CPUFREQ |
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 01a134141216..a03b5a7059e2 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug | |||
| @@ -310,6 +310,32 @@ choice | |||
| 310 | The uncompressor code port configuration is now handled | 310 | The uncompressor code port configuration is now handled |
| 311 | by CONFIG_S3C_LOWLEVEL_UART_PORT. | 311 | by CONFIG_S3C_LOWLEVEL_UART_PORT. |
| 312 | 312 | ||
| 313 | config DEBUG_VEXPRESS_UART0_DETECT | ||
| 314 | bool "Autodetect UART0 on Versatile Express Cortex-A core tiles" | ||
| 315 | depends on ARCH_VEXPRESS && CPU_CP15_MMU | ||
| 316 | help | ||
| 317 | This option enables a simple heuristic which tries to determine | ||
| 318 | the motherboard's memory map variant (original or RS1) and then | ||
| 319 | choose the relevant UART0 base address. | ||
| 320 | |||
| 321 | Note that this will only work with standard A-class core tiles, | ||
| 322 | and may fail with non-standard SMM or custom software models. | ||
| 323 | |||
| 324 | config DEBUG_VEXPRESS_UART0_CA9 | ||
| 325 | bool "Use PL011 UART0 at 0x10009000 (V2P-CA9 core tile)" | ||
| 326 | depends on ARCH_VEXPRESS | ||
| 327 | help | ||
| 328 | This option selects UART0 at 0x10009000. Except for custom models, | ||
| 329 | this applies only to the V2P-CA9 tile. | ||
| 330 | |||
| 331 | config DEBUG_VEXPRESS_UART0_RS1 | ||
| 332 | bool "Use PL011 UART0 at 0x1c090000 (RS1 complaint tiles)" | ||
| 333 | depends on ARCH_VEXPRESS | ||
| 334 | help | ||
| 335 | This option selects UART0 at 0x1c090000. This applies to most | ||
| 336 | of the tiles using the RS1 memory map, including all new A-class | ||
| 337 | core tiles, FPGA-based SMMs and software models. | ||
| 338 | |||
| 313 | config DEBUG_LL_UART_NONE | 339 | config DEBUG_LL_UART_NONE |
| 314 | bool "No low-level debugging UART" | 340 | bool "No low-level debugging UART" |
| 315 | help | 341 | help |
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index f449efc9825f..66389c1c6f62 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi | |||
| @@ -52,10 +52,11 @@ | |||
| 52 | ranges; | 52 | ranges; |
| 53 | 53 | ||
| 54 | aic: interrupt-controller@fffff000 { | 54 | aic: interrupt-controller@fffff000 { |
| 55 | #interrupt-cells = <2>; | 55 | #interrupt-cells = <3>; |
| 56 | compatible = "atmel,at91rm9200-aic"; | 56 | compatible = "atmel,at91rm9200-aic"; |
| 57 | interrupt-controller; | 57 | interrupt-controller; |
| 58 | reg = <0xfffff000 0x200>; | 58 | reg = <0xfffff000 0x200>; |
| 59 | atmel,external-irqs = <29 30 31>; | ||
| 59 | }; | 60 | }; |
| 60 | 61 | ||
| 61 | ramc0: ramc@ffffea00 { | 62 | ramc0: ramc@ffffea00 { |
| @@ -81,25 +82,25 @@ | |||
| 81 | pit: timer@fffffd30 { | 82 | pit: timer@fffffd30 { |
| 82 | compatible = "atmel,at91sam9260-pit"; | 83 | compatible = "atmel,at91sam9260-pit"; |
| 83 | reg = <0xfffffd30 0xf>; | 84 | reg = <0xfffffd30 0xf>; |
| 84 | interrupts = <1 4>; | 85 | interrupts = <1 4 7>; |
| 85 | }; | 86 | }; |
| 86 | 87 | ||
| 87 | tcb0: timer@fffa0000 { | 88 | tcb0: timer@fffa0000 { |
| 88 | compatible = "atmel,at91rm9200-tcb"; | 89 | compatible = "atmel,at91rm9200-tcb"; |
| 89 | reg = <0xfffa0000 0x100>; | 90 | reg = <0xfffa0000 0x100>; |
| 90 | interrupts = <17 4 18 4 19 4>; | 91 | interrupts = <17 4 0 18 4 0 19 4 0>; |
| 91 | }; | 92 | }; |
| 92 | 93 | ||
| 93 | tcb1: timer@fffdc000 { | 94 | tcb1: timer@fffdc000 { |
| 94 | compatible = "atmel,at91rm9200-tcb"; | 95 | compatible = "atmel,at91rm9200-tcb"; |
| 95 | reg = <0xfffdc000 0x100>; | 96 | reg = <0xfffdc000 0x100>; |
| 96 | interrupts = <26 4 27 4 28 4>; | 97 | interrupts = <26 4 0 27 4 0 28 4 0>; |
| 97 | }; | 98 | }; |
| 98 | 99 | ||
| 99 | pioA: gpio@fffff400 { | 100 | pioA: gpio@fffff400 { |
| 100 | compatible = "atmel,at91rm9200-gpio"; | 101 | compatible = "atmel,at91rm9200-gpio"; |
| 101 | reg = <0xfffff400 0x100>; | 102 | reg = <0xfffff400 0x100>; |
| 102 | interrupts = <2 4>; | 103 | interrupts = <2 4 1>; |
| 103 | #gpio-cells = <2>; | 104 | #gpio-cells = <2>; |
| 104 | gpio-controller; | 105 | gpio-controller; |
| 105 | interrupt-controller; | 106 | interrupt-controller; |
| @@ -108,7 +109,7 @@ | |||
| 108 | pioB: gpio@fffff600 { | 109 | pioB: gpio@fffff600 { |
| 109 | compatible = "atmel,at91rm9200-gpio"; | 110 | compatible = "atmel,at91rm9200-gpio"; |
| 110 | reg = <0xfffff600 0x100>; | 111 | reg = <0xfffff600 0x100>; |
| 111 | interrupts = <3 4>; | 112 | interrupts = <3 4 1>; |
| 112 | #gpio-cells = <2>; | 113 | #gpio-cells = <2>; |
| 113 | gpio-controller; | 114 | gpio-controller; |
| 114 | interrupt-controller; | 115 | interrupt-controller; |
| @@ -117,7 +118,7 @@ | |||
| 117 | pioC: gpio@fffff800 { | 118 | pioC: gpio@fffff800 { |
| 118 | compatible = "atmel,at91rm9200-gpio"; | 119 | compatible = "atmel,at91rm9200-gpio"; |
| 119 | reg = <0xfffff800 0x100>; | 120 | reg = <0xfffff800 0x100>; |
| 120 | interrupts = <4 4>; | 121 | interrupts = <4 4 1>; |
| 121 | #gpio-cells = <2>; | 122 | #gpio-cells = <2>; |
| 122 | gpio-controller; | 123 | gpio-controller; |
| 123 | interrupt-controller; | 124 | interrupt-controller; |
| @@ -126,14 +127,14 @@ | |||
| 126 | dbgu: serial@fffff200 { | 127 | dbgu: serial@fffff200 { |
| 127 | compatible = "atmel,at91sam9260-usart"; | 128 | compatible = "atmel,at91sam9260-usart"; |
| 128 | reg = <0xfffff200 0x200>; | 129 | reg = <0xfffff200 0x200>; |
| 129 | interrupts = <1 4>; | 130 | interrupts = <1 4 7>; |
| 130 | status = "disabled"; | 131 | status = "disabled"; |
| 131 | }; | 132 | }; |
| 132 | 133 | ||
| 133 | usart0: serial@fffb0000 { | 134 | usart0: serial@fffb0000 { |
| 134 | compatible = "atmel,at91sam9260-usart"; | 135 | compatible = "atmel,at91sam9260-usart"; |
| 135 | reg = <0xfffb0000 0x200>; | 136 | reg = <0xfffb0000 0x200>; |
| 136 | interrupts = <6 4>; | 137 | interrupts = <6 4 5>; |
| 137 | atmel,use-dma-rx; | 138 | atmel,use-dma-rx; |
| 138 | atmel,use-dma-tx; | 139 | atmel,use-dma-tx; |
| 139 | status = "disabled"; | 140 | status = "disabled"; |
| @@ -142,7 +143,7 @@ | |||
| 142 | usart1: serial@fffb4000 { | 143 | usart1: serial@fffb4000 { |
| 143 | compatible = "atmel,at91sam9260-usart"; | 144 | compatible = "atmel,at91sam9260-usart"; |
| 144 | reg = <0xfffb4000 0x200>; | 145 | reg = <0xfffb4000 0x200>; |
| 145 | interrupts = <7 4>; | 146 | interrupts = <7 4 5>; |
| 146 | atmel,use-dma-rx; | 147 | atmel,use-dma-rx; |
| 147 | atmel,use-dma-tx; | 148 | atmel,use-dma-tx; |
| 148 | status = "disabled"; | 149 | status = "disabled"; |
| @@ -151,7 +152,7 @@ | |||
| 151 | usart2: serial@fffb8000 { | 152 | usart2: serial@fffb8000 { |
| 152 | compatible = "atmel,at91sam9260-usart"; | 153 | compatible = "atmel,at91sam9260-usart"; |
| 153 | reg = <0xfffb8000 0x200>; | 154 | reg = <0xfffb8000 0x200>; |
| 154 | interrupts = <8 4>; | 155 | interrupts = <8 4 5>; |
| 155 | atmel,use-dma-rx; | 156 | atmel,use-dma-rx; |
| 156 | atmel,use-dma-tx; | 157 | atmel,use-dma-tx; |
| 157 | status = "disabled"; | 158 | status = "disabled"; |
| @@ -160,7 +161,7 @@ | |||
| 160 | usart3: serial@fffd0000 { | 161 | usart3: serial@fffd0000 { |
| 161 | compatible = "atmel,at91sam9260-usart"; | 162 | compatible = "atmel,at91sam9260-usart"; |
| 162 | reg = <0xfffd0000 0x200>; | 163 | reg = <0xfffd0000 0x200>; |
| 163 | interrupts = <23 4>; | 164 | interrupts = <23 4 5>; |
| 164 | atmel,use-dma-rx; | 165 | atmel,use-dma-rx; |
| 165 | atmel,use-dma-tx; | 166 | atmel,use-dma-tx; |
| 166 | status = "disabled"; | 167 | status = "disabled"; |
| @@ -169,7 +170,7 @@ | |||
| 169 | usart4: serial@fffd4000 { | 170 | usart4: serial@fffd4000 { |
| 170 | compatible = "atmel,at91sam9260-usart"; | 171 | compatible = "atmel,at91sam9260-usart"; |
| 171 | reg = <0xfffd4000 0x200>; | 172 | reg = <0xfffd4000 0x200>; |
| 172 | interrupts = <24 4>; | 173 | interrupts = <24 4 5>; |
| 173 | atmel,use-dma-rx; | 174 | atmel,use-dma-rx; |
| 174 | atmel,use-dma-tx; | 175 | atmel,use-dma-tx; |
| 175 | status = "disabled"; | 176 | status = "disabled"; |
| @@ -178,7 +179,7 @@ | |||
| 178 | usart5: serial@fffd8000 { | 179 | usart5: serial@fffd8000 { |
| 179 | compatible = "atmel,at91sam9260-usart"; | 180 | compatible = "atmel,at91sam9260-usart"; |
| 180 | reg = <0xfffd8000 0x200>; | 181 | reg = <0xfffd8000 0x200>; |
| 181 | interrupts = <25 4>; | 182 | interrupts = <25 4 5>; |
| 182 | atmel,use-dma-rx; | 183 | atmel,use-dma-rx; |
| 183 | atmel,use-dma-tx; | 184 | atmel,use-dma-tx; |
| 184 | status = "disabled"; | 185 | status = "disabled"; |
| @@ -187,21 +188,21 @@ | |||
| 187 | macb0: ethernet@fffc4000 { | 188 | macb0: ethernet@fffc4000 { |
| 188 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | 189 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; |
| 189 | reg = <0xfffc4000 0x100>; | 190 | reg = <0xfffc4000 0x100>; |
| 190 | interrupts = <21 4>; | 191 | interrupts = <21 4 3>; |
| 191 | status = "disabled"; | 192 | status = "disabled"; |
| 192 | }; | 193 | }; |
| 193 | 194 | ||
| 194 | usb1: gadget@fffa4000 { | 195 | usb1: gadget@fffa4000 { |
| 195 | compatible = "atmel,at91rm9200-udc"; | 196 | compatible = "atmel,at91rm9200-udc"; |
| 196 | reg = <0xfffa4000 0x4000>; | 197 | reg = <0xfffa4000 0x4000>; |
| 197 | interrupts = <10 4>; | 198 | interrupts = <10 4 2>; |
| 198 | status = "disabled"; | 199 | status = "disabled"; |
| 199 | }; | 200 | }; |
| 200 | 201 | ||
| 201 | adc0: adc@fffe0000 { | 202 | adc0: adc@fffe0000 { |
| 202 | compatible = "atmel,at91sam9260-adc"; | 203 | compatible = "atmel,at91sam9260-adc"; |
| 203 | reg = <0xfffe0000 0x100>; | 204 | reg = <0xfffe0000 0x100>; |
| 204 | interrupts = <5 4>; | 205 | interrupts = <5 4 0>; |
| 205 | atmel,adc-use-external-triggers; | 206 | atmel,adc-use-external-triggers; |
| 206 | atmel,adc-channels-used = <0xf>; | 207 | atmel,adc-channels-used = <0xf>; |
| 207 | atmel,adc-vref = <3300>; | 208 | atmel,adc-vref = <3300>; |
| @@ -253,7 +254,7 @@ | |||
| 253 | usb0: ohci@00500000 { | 254 | usb0: ohci@00500000 { |
| 254 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | 255 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
| 255 | reg = <0x00500000 0x100000>; | 256 | reg = <0x00500000 0x100000>; |
| 256 | interrupts = <20 4>; | 257 | interrupts = <20 4 2>; |
| 257 | status = "disabled"; | 258 | status = "disabled"; |
| 258 | }; | 259 | }; |
| 259 | }; | 260 | }; |
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index 0209913a65a2..b460d6ce9eb5 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi | |||
| @@ -48,10 +48,11 @@ | |||
| 48 | ranges; | 48 | ranges; |
| 49 | 49 | ||
| 50 | aic: interrupt-controller@fffff000 { | 50 | aic: interrupt-controller@fffff000 { |
| 51 | #interrupt-cells = <2>; | 51 | #interrupt-cells = <3>; |
| 52 | compatible = "atmel,at91rm9200-aic"; | 52 | compatible = "atmel,at91rm9200-aic"; |
| 53 | interrupt-controller; | 53 | interrupt-controller; |
| 54 | reg = <0xfffff000 0x200>; | 54 | reg = <0xfffff000 0x200>; |
| 55 | atmel,external-irqs = <30 31>; | ||
| 55 | }; | 56 | }; |
| 56 | 57 | ||
| 57 | pmc: pmc@fffffc00 { | 58 | pmc: pmc@fffffc00 { |
| @@ -68,13 +69,13 @@ | |||
| 68 | pit: timer@fffffd30 { | 69 | pit: timer@fffffd30 { |
| 69 | compatible = "atmel,at91sam9260-pit"; | 70 | compatible = "atmel,at91sam9260-pit"; |
| 70 | reg = <0xfffffd30 0xf>; | 71 | reg = <0xfffffd30 0xf>; |
| 71 | interrupts = <1 4>; | 72 | interrupts = <1 4 7>; |
| 72 | }; | 73 | }; |
| 73 | 74 | ||
| 74 | tcb0: timer@fff7c000 { | 75 | tcb0: timer@fff7c000 { |
| 75 | compatible = "atmel,at91rm9200-tcb"; | 76 | compatible = "atmel,at91rm9200-tcb"; |
| 76 | reg = <0xfff7c000 0x100>; | 77 | reg = <0xfff7c000 0x100>; |
| 77 | interrupts = <19 4>; | 78 | interrupts = <19 4 0>; |
| 78 | }; | 79 | }; |
| 79 | 80 | ||
| 80 | rstc@fffffd00 { | 81 | rstc@fffffd00 { |
| @@ -90,7 +91,7 @@ | |||
| 90 | pioA: gpio@fffff200 { | 91 | pioA: gpio@fffff200 { |
| 91 | compatible = "atmel,at91rm9200-gpio"; | 92 | compatible = "atmel,at91rm9200-gpio"; |
| 92 | reg = <0xfffff200 0x100>; | 93 | reg = <0xfffff200 0x100>; |
| 93 | interrupts = <2 4>; | 94 | interrupts = <2 4 1>; |
| 94 | #gpio-cells = <2>; | 95 | #gpio-cells = <2>; |
| 95 | gpio-controller; | 96 | gpio-controller; |
| 96 | interrupt-controller; | 97 | interrupt-controller; |
| @@ -99,7 +100,7 @@ | |||
| 99 | pioB: gpio@fffff400 { | 100 | pioB: gpio@fffff400 { |
| 100 | compatible = "atmel,at91rm9200-gpio"; | 101 | compatible = "atmel,at91rm9200-gpio"; |
| 101 | reg = <0xfffff400 0x100>; | 102 | reg = <0xfffff400 0x100>; |
| 102 | interrupts = <3 4>; | 103 | interrupts = <3 4 1>; |
| 103 | #gpio-cells = <2>; | 104 | #gpio-cells = <2>; |
| 104 | gpio-controller; | 105 | gpio-controller; |
| 105 | interrupt-controller; | 106 | interrupt-controller; |
| @@ -108,7 +109,7 @@ | |||
| 108 | pioC: gpio@fffff600 { | 109 | pioC: gpio@fffff600 { |
| 109 | compatible = "atmel,at91rm9200-gpio"; | 110 | compatible = "atmel,at91rm9200-gpio"; |
| 110 | reg = <0xfffff600 0x100>; | 111 | reg = <0xfffff600 0x100>; |
| 111 | interrupts = <4 4>; | 112 | interrupts = <4 4 1>; |
| 112 | #gpio-cells = <2>; | 113 | #gpio-cells = <2>; |
| 113 | gpio-controller; | 114 | gpio-controller; |
| 114 | interrupt-controller; | 115 | interrupt-controller; |
| @@ -117,7 +118,7 @@ | |||
| 117 | pioD: gpio@fffff800 { | 118 | pioD: gpio@fffff800 { |
| 118 | compatible = "atmel,at91rm9200-gpio"; | 119 | compatible = "atmel,at91rm9200-gpio"; |
| 119 | reg = <0xfffff800 0x100>; | 120 | reg = <0xfffff800 0x100>; |
| 120 | interrupts = <4 4>; | 121 | interrupts = <4 4 1>; |
| 121 | #gpio-cells = <2>; | 122 | #gpio-cells = <2>; |
| 122 | gpio-controller; | 123 | gpio-controller; |
| 123 | interrupt-controller; | 124 | interrupt-controller; |
| @@ -126,7 +127,7 @@ | |||
| 126 | pioE: gpio@fffffa00 { | 127 | pioE: gpio@fffffa00 { |
| 127 | compatible = "atmel,at91rm9200-gpio"; | 128 | compatible = "atmel,at91rm9200-gpio"; |
| 128 | reg = <0xfffffa00 0x100>; | 129 | reg = <0xfffffa00 0x100>; |
| 129 | interrupts = <4 4>; | 130 | interrupts = <4 4 1>; |
| 130 | #gpio-cells = <2>; | 131 | #gpio-cells = <2>; |
| 131 | gpio-controller; | 132 | gpio-controller; |
| 132 | interrupt-controller; | 133 | interrupt-controller; |
| @@ -135,14 +136,14 @@ | |||
| 135 | dbgu: serial@ffffee00 { | 136 | dbgu: serial@ffffee00 { |
| 136 | compatible = "atmel,at91sam9260-usart"; | 137 | compatible = "atmel,at91sam9260-usart"; |
| 137 | reg = <0xffffee00 0x200>; | 138 | reg = <0xffffee00 0x200>; |
| 138 | interrupts = <1 4>; | 139 | interrupts = <1 4 7>; |
| 139 | status = "disabled"; | 140 | status = "disabled"; |
| 140 | }; | 141 | }; |
| 141 | 142 | ||
| 142 | usart0: serial@fff8c000 { | 143 | usart0: serial@fff8c000 { |
| 143 | compatible = "atmel,at91sam9260-usart"; | 144 | compatible = "atmel,at91sam9260-usart"; |
| 144 | reg = <0xfff8c000 0x200>; | 145 | reg = <0xfff8c000 0x200>; |
| 145 | interrupts = <7 4>; | 146 | interrupts = <7 4 5>; |
| 146 | atmel,use-dma-rx; | 147 | atmel,use-dma-rx; |
| 147 | atmel,use-dma-tx; | 148 | atmel,use-dma-tx; |
| 148 | status = "disabled"; | 149 | status = "disabled"; |
| @@ -151,7 +152,7 @@ | |||
| 151 | usart1: serial@fff90000 { | 152 | usart1: serial@fff90000 { |
| 152 | compatible = "atmel,at91sam9260-usart"; | 153 | compatible = "atmel,at91sam9260-usart"; |
| 153 | reg = <0xfff90000 0x200>; | 154 | reg = <0xfff90000 0x200>; |
| 154 | interrupts = <8 4>; | 155 | interrupts = <8 4 5>; |
| 155 | atmel,use-dma-rx; | 156 | atmel,use-dma-rx; |
| 156 | atmel,use-dma-tx; | 157 | atmel,use-dma-tx; |
| 157 | status = "disabled"; | 158 | status = "disabled"; |
| @@ -160,7 +161,7 @@ | |||
| 160 | usart2: serial@fff94000 { | 161 | usart2: serial@fff94000 { |
| 161 | compatible = "atmel,at91sam9260-usart"; | 162 | compatible = "atmel,at91sam9260-usart"; |
| 162 | reg = <0xfff94000 0x200>; | 163 | reg = <0xfff94000 0x200>; |
| 163 | interrupts = <9 4>; | 164 | interrupts = <9 4 5>; |
| 164 | atmel,use-dma-rx; | 165 | atmel,use-dma-rx; |
| 165 | atmel,use-dma-tx; | 166 | atmel,use-dma-tx; |
| 166 | status = "disabled"; | 167 | status = "disabled"; |
| @@ -169,14 +170,14 @@ | |||
| 169 | macb0: ethernet@fffbc000 { | 170 | macb0: ethernet@fffbc000 { |
| 170 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | 171 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; |
| 171 | reg = <0xfffbc000 0x100>; | 172 | reg = <0xfffbc000 0x100>; |
| 172 | interrupts = <21 4>; | 173 | interrupts = <21 4 3>; |
| 173 | status = "disabled"; | 174 | status = "disabled"; |
| 174 | }; | 175 | }; |
| 175 | 176 | ||
| 176 | usb1: gadget@fff78000 { | 177 | usb1: gadget@fff78000 { |
| 177 | compatible = "atmel,at91rm9200-udc"; | 178 | compatible = "atmel,at91rm9200-udc"; |
| 178 | reg = <0xfff78000 0x4000>; | 179 | reg = <0xfff78000 0x4000>; |
| 179 | interrupts = <24 4>; | 180 | interrupts = <24 4 2>; |
| 180 | status = "disabled"; | 181 | status = "disabled"; |
| 181 | }; | 182 | }; |
| 182 | }; | 183 | }; |
| @@ -200,7 +201,7 @@ | |||
| 200 | usb0: ohci@00a00000 { | 201 | usb0: ohci@00a00000 { |
| 201 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | 202 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
| 202 | reg = <0x00a00000 0x100000>; | 203 | reg = <0x00a00000 0x100000>; |
| 203 | interrupts = <29 4>; | 204 | interrupts = <29 4 2>; |
| 204 | status = "disabled"; | 205 | status = "disabled"; |
| 205 | }; | 206 | }; |
| 206 | }; | 207 | }; |
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 7dbccaf199f7..bafa8806fc17 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi | |||
| @@ -53,10 +53,11 @@ | |||
| 53 | ranges; | 53 | ranges; |
| 54 | 54 | ||
| 55 | aic: interrupt-controller@fffff000 { | 55 | aic: interrupt-controller@fffff000 { |
| 56 | #interrupt-cells = <2>; | 56 | #interrupt-cells = <3>; |
| 57 | compatible = "atmel,at91rm9200-aic"; | 57 | compatible = "atmel,at91rm9200-aic"; |
| 58 | interrupt-controller; | 58 | interrupt-controller; |
| 59 | reg = <0xfffff000 0x200>; | 59 | reg = <0xfffff000 0x200>; |
| 60 | atmel,external-irqs = <31>; | ||
| 60 | }; | 61 | }; |
| 61 | 62 | ||
| 62 | ramc0: ramc@ffffe400 { | 63 | ramc0: ramc@ffffe400 { |
| @@ -78,7 +79,7 @@ | |||
| 78 | pit: timer@fffffd30 { | 79 | pit: timer@fffffd30 { |
| 79 | compatible = "atmel,at91sam9260-pit"; | 80 | compatible = "atmel,at91sam9260-pit"; |
| 80 | reg = <0xfffffd30 0xf>; | 81 | reg = <0xfffffd30 0xf>; |
| 81 | interrupts = <1 4>; | 82 | interrupts = <1 4 7>; |
| 82 | }; | 83 | }; |
| 83 | 84 | ||
| 84 | 85 | ||
| @@ -90,25 +91,25 @@ | |||
| 90 | tcb0: timer@fff7c000 { | 91 | tcb0: timer@fff7c000 { |
| 91 | compatible = "atmel,at91rm9200-tcb"; | 92 | compatible = "atmel,at91rm9200-tcb"; |
| 92 | reg = <0xfff7c000 0x100>; | 93 | reg = <0xfff7c000 0x100>; |
| 93 | interrupts = <18 4>; | 94 | interrupts = <18 4 0>; |
| 94 | }; | 95 | }; |
| 95 | 96 | ||
| 96 | tcb1: timer@fffd4000 { | 97 | tcb1: timer@fffd4000 { |
| 97 | compatible = "atmel,at91rm9200-tcb"; | 98 | compatible = "atmel,at91rm9200-tcb"; |
| 98 | reg = <0xfffd4000 0x100>; | 99 | reg = <0xfffd4000 0x100>; |
| 99 | interrupts = <18 4>; | 100 | interrupts = <18 4 0>; |
| 100 | }; | 101 | }; |
| 101 | 102 | ||
| 102 | dma: dma-controller@ffffec00 { | 103 | dma: dma-controller@ffffec00 { |
| 103 | compatible = "atmel,at91sam9g45-dma"; | 104 | compatible = "atmel,at91sam9g45-dma"; |
| 104 | reg = <0xffffec00 0x200>; | 105 | reg = <0xffffec00 0x200>; |
| 105 | interrupts = <21 4>; | 106 | interrupts = <21 4 0>; |
| 106 | }; | 107 | }; |
| 107 | 108 | ||
| 108 | pioA: gpio@fffff200 { | 109 | pioA: gpio@fffff200 { |
| 109 | compatible = "atmel,at91rm9200-gpio"; | 110 | compatible = "atmel,at91rm9200-gpio"; |
| 110 | reg = <0xfffff200 0x100>; | 111 | reg = <0xfffff200 0x100>; |
| 111 | interrupts = <2 4>; | 112 | interrupts = <2 4 1>; |
| 112 | #gpio-cells = <2>; | 113 | #gpio-cells = <2>; |
| 113 | gpio-controller; | 114 | gpio-controller; |
| 114 | interrupt-controller; | 115 | interrupt-controller; |
| @@ -117,7 +118,7 @@ | |||
| 117 | pioB: gpio@fffff400 { | 118 | pioB: gpio@fffff400 { |
| 118 | compatible = "atmel,at91rm9200-gpio"; | 119 | compatible = "atmel,at91rm9200-gpio"; |
| 119 | reg = <0xfffff400 0x100>; | 120 | reg = <0xfffff400 0x100>; |
| 120 | interrupts = <3 4>; | 121 | interrupts = <3 4 1>; |
| 121 | #gpio-cells = <2>; | 122 | #gpio-cells = <2>; |
| 122 | gpio-controller; | 123 | gpio-controller; |
| 123 | interrupt-controller; | 124 | interrupt-controller; |
| @@ -126,7 +127,7 @@ | |||
| 126 | pioC: gpio@fffff600 { | 127 | pioC: gpio@fffff600 { |
| 127 | compatible = "atmel,at91rm9200-gpio"; | 128 | compatible = "atmel,at91rm9200-gpio"; |
| 128 | reg = <0xfffff600 0x100>; | 129 | reg = <0xfffff600 0x100>; |
| 129 | interrupts = <4 4>; | 130 | interrupts = <4 4 1>; |
| 130 | #gpio-cells = <2>; | 131 | #gpio-cells = <2>; |
| 131 | gpio-controller; | 132 | gpio-controller; |
| 132 | interrupt-controller; | 133 | interrupt-controller; |
| @@ -135,7 +136,7 @@ | |||
| 135 | pioD: gpio@fffff800 { | 136 | pioD: gpio@fffff800 { |
| 136 | compatible = "atmel,at91rm9200-gpio"; | 137 | compatible = "atmel,at91rm9200-gpio"; |
| 137 | reg = <0xfffff800 0x100>; | 138 | reg = <0xfffff800 0x100>; |
| 138 | interrupts = <5 4>; | 139 | interrupts = <5 4 1>; |
| 139 | #gpio-cells = <2>; | 140 | #gpio-cells = <2>; |
| 140 | gpio-controller; | 141 | gpio-controller; |
| 141 | interrupt-controller; | 142 | interrupt-controller; |
| @@ -144,7 +145,7 @@ | |||
| 144 | pioE: gpio@fffffa00 { | 145 | pioE: gpio@fffffa00 { |
| 145 | compatible = "atmel,at91rm9200-gpio"; | 146 | compatible = "atmel,at91rm9200-gpio"; |
| 146 | reg = <0xfffffa00 0x100>; | 147 | reg = <0xfffffa00 0x100>; |
| 147 | interrupts = <5 4>; | 148 | interrupts = <5 4 1>; |
| 148 | #gpio-cells = <2>; | 149 | #gpio-cells = <2>; |
| 149 | gpio-controller; | 150 | gpio-controller; |
| 150 | interrupt-controller; | 151 | interrupt-controller; |
| @@ -153,14 +154,14 @@ | |||
| 153 | dbgu: serial@ffffee00 { | 154 | dbgu: serial@ffffee00 { |
| 154 | compatible = "atmel,at91sam9260-usart"; | 155 | compatible = "atmel,at91sam9260-usart"; |
| 155 | reg = <0xffffee00 0x200>; | 156 | reg = <0xffffee00 0x200>; |
| 156 | interrupts = <1 4>; | 157 | interrupts = <1 4 7>; |
| 157 | status = "disabled"; | 158 | status = "disabled"; |
| 158 | }; | 159 | }; |
| 159 | 160 | ||
| 160 | usart0: serial@fff8c000 { | 161 | usart0: serial@fff8c000 { |
| 161 | compatible = "atmel,at91sam9260-usart"; | 162 | compatible = "atmel,at91sam9260-usart"; |
| 162 | reg = <0xfff8c000 0x200>; | 163 | reg = <0xfff8c000 0x200>; |
| 163 | interrupts = <7 4>; | 164 | interrupts = <7 4 5>; |
| 164 | atmel,use-dma-rx; | 165 | atmel,use-dma-rx; |
| 165 | atmel,use-dma-tx; | 166 | atmel,use-dma-tx; |
| 166 | status = "disabled"; | 167 | status = "disabled"; |
| @@ -169,7 +170,7 @@ | |||
| 169 | usart1: serial@fff90000 { | 170 | usart1: serial@fff90000 { |
| 170 | compatible = "atmel,at91sam9260-usart"; | 171 | compatible = "atmel,at91sam9260-usart"; |
| 171 | reg = <0xfff90000 0x200>; | 172 | reg = <0xfff90000 0x200>; |
| 172 | interrupts = <8 4>; | 173 | interrupts = <8 4 5>; |
| 173 | atmel,use-dma-rx; | 174 | atmel,use-dma-rx; |
| 174 | atmel,use-dma-tx; | 175 | atmel,use-dma-tx; |
| 175 | status = "disabled"; | 176 | status = "disabled"; |
| @@ -178,7 +179,7 @@ | |||
| 178 | usart2: serial@fff94000 { | 179 | usart2: serial@fff94000 { |
| 179 | compatible = "atmel,at91sam9260-usart"; | 180 | compatible = "atmel,at91sam9260-usart"; |
| 180 | reg = <0xfff94000 0x200>; | 181 | reg = <0xfff94000 0x200>; |
| 181 | interrupts = <9 4>; | 182 | interrupts = <9 4 5>; |
| 182 | atmel,use-dma-rx; | 183 | atmel,use-dma-rx; |
| 183 | atmel,use-dma-tx; | 184 | atmel,use-dma-tx; |
| 184 | status = "disabled"; | 185 | status = "disabled"; |
| @@ -187,7 +188,7 @@ | |||
| 187 | usart3: serial@fff98000 { | 188 | usart3: serial@fff98000 { |
| 188 | compatible = "atmel,at91sam9260-usart"; | 189 | compatible = "atmel,at91sam9260-usart"; |
| 189 | reg = <0xfff98000 0x200>; | 190 | reg = <0xfff98000 0x200>; |
| 190 | interrupts = <10 4>; | 191 | interrupts = <10 4 5>; |
| 191 | atmel,use-dma-rx; | 192 | atmel,use-dma-rx; |
| 192 | atmel,use-dma-tx; | 193 | atmel,use-dma-tx; |
| 193 | status = "disabled"; | 194 | status = "disabled"; |
| @@ -196,14 +197,14 @@ | |||
| 196 | macb0: ethernet@fffbc000 { | 197 | macb0: ethernet@fffbc000 { |
| 197 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | 198 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; |
| 198 | reg = <0xfffbc000 0x100>; | 199 | reg = <0xfffbc000 0x100>; |
| 199 | interrupts = <25 4>; | 200 | interrupts = <25 4 3>; |
| 200 | status = "disabled"; | 201 | status = "disabled"; |
| 201 | }; | 202 | }; |
| 202 | 203 | ||
| 203 | adc0: adc@fffb0000 { | 204 | adc0: adc@fffb0000 { |
| 204 | compatible = "atmel,at91sam9260-adc"; | 205 | compatible = "atmel,at91sam9260-adc"; |
| 205 | reg = <0xfffb0000 0x100>; | 206 | reg = <0xfffb0000 0x100>; |
| 206 | interrupts = <20 4>; | 207 | interrupts = <20 4 0>; |
| 207 | atmel,adc-use-external-triggers; | 208 | atmel,adc-use-external-triggers; |
| 208 | atmel,adc-channels-used = <0xff>; | 209 | atmel,adc-channels-used = <0xff>; |
| 209 | atmel,adc-vref = <3300>; | 210 | atmel,adc-vref = <3300>; |
| @@ -257,14 +258,14 @@ | |||
| 257 | usb0: ohci@00700000 { | 258 | usb0: ohci@00700000 { |
| 258 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | 259 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
| 259 | reg = <0x00700000 0x100000>; | 260 | reg = <0x00700000 0x100000>; |
| 260 | interrupts = <22 4>; | 261 | interrupts = <22 4 2>; |
| 261 | status = "disabled"; | 262 | status = "disabled"; |
| 262 | }; | 263 | }; |
| 263 | 264 | ||
| 264 | usb1: ehci@00800000 { | 265 | usb1: ehci@00800000 { |
| 265 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; | 266 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; |
| 266 | reg = <0x00800000 0x100000>; | 267 | reg = <0x00800000 0x100000>; |
| 267 | interrupts = <22 4>; | 268 | interrupts = <22 4 2>; |
| 268 | status = "disabled"; | 269 | status = "disabled"; |
| 269 | }; | 270 | }; |
| 270 | }; | 271 | }; |
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index cb84de791b5a..bfac0dfc332c 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi | |||
| @@ -50,7 +50,7 @@ | |||
| 50 | ranges; | 50 | ranges; |
| 51 | 51 | ||
| 52 | aic: interrupt-controller@fffff000 { | 52 | aic: interrupt-controller@fffff000 { |
| 53 | #interrupt-cells = <2>; | 53 | #interrupt-cells = <3>; |
| 54 | compatible = "atmel,at91rm9200-aic"; | 54 | compatible = "atmel,at91rm9200-aic"; |
| 55 | interrupt-controller; | 55 | interrupt-controller; |
| 56 | reg = <0xfffff000 0x200>; | 56 | reg = <0xfffff000 0x200>; |
| @@ -74,7 +74,7 @@ | |||
| 74 | pit: timer@fffffe30 { | 74 | pit: timer@fffffe30 { |
| 75 | compatible = "atmel,at91sam9260-pit"; | 75 | compatible = "atmel,at91sam9260-pit"; |
| 76 | reg = <0xfffffe30 0xf>; | 76 | reg = <0xfffffe30 0xf>; |
| 77 | interrupts = <1 4>; | 77 | interrupts = <1 4 7>; |
| 78 | }; | 78 | }; |
| 79 | 79 | ||
| 80 | shdwc@fffffe10 { | 80 | shdwc@fffffe10 { |
| @@ -85,25 +85,25 @@ | |||
| 85 | tcb0: timer@f8008000 { | 85 | tcb0: timer@f8008000 { |
| 86 | compatible = "atmel,at91sam9x5-tcb"; | 86 | compatible = "atmel,at91sam9x5-tcb"; |
| 87 | reg = <0xf8008000 0x100>; | 87 | reg = <0xf8008000 0x100>; |
| 88 | interrupts = <17 4>; | 88 | interrupts = <17 4 0>; |
| 89 | }; | 89 | }; |
| 90 | 90 | ||
| 91 | tcb1: timer@f800c000 { | 91 | tcb1: timer@f800c000 { |
| 92 | compatible = "atmel,at91sam9x5-tcb"; | 92 | compatible = "atmel,at91sam9x5-tcb"; |
| 93 | reg = <0xf800c000 0x100>; | 93 | reg = <0xf800c000 0x100>; |
| 94 | interrupts = <17 4>; | 94 | interrupts = <17 4 0>; |
| 95 | }; | 95 | }; |
| 96 | 96 | ||
| 97 | dma: dma-controller@ffffec00 { | 97 | dma: dma-controller@ffffec00 { |
| 98 | compatible = "atmel,at91sam9g45-dma"; | 98 | compatible = "atmel,at91sam9g45-dma"; |
| 99 | reg = <0xffffec00 0x200>; | 99 | reg = <0xffffec00 0x200>; |
| 100 | interrupts = <20 4>; | 100 | interrupts = <20 4 0>; |
| 101 | }; | 101 | }; |
| 102 | 102 | ||
| 103 | pioA: gpio@fffff400 { | 103 | pioA: gpio@fffff400 { |
| 104 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | 104 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 105 | reg = <0xfffff400 0x100>; | 105 | reg = <0xfffff400 0x100>; |
| 106 | interrupts = <2 4>; | 106 | interrupts = <2 4 1>; |
| 107 | #gpio-cells = <2>; | 107 | #gpio-cells = <2>; |
| 108 | gpio-controller; | 108 | gpio-controller; |
| 109 | interrupt-controller; | 109 | interrupt-controller; |
| @@ -112,7 +112,7 @@ | |||
| 112 | pioB: gpio@fffff600 { | 112 | pioB: gpio@fffff600 { |
| 113 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | 113 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 114 | reg = <0xfffff600 0x100>; | 114 | reg = <0xfffff600 0x100>; |
| 115 | interrupts = <2 4>; | 115 | interrupts = <2 4 1>; |
| 116 | #gpio-cells = <2>; | 116 | #gpio-cells = <2>; |
| 117 | gpio-controller; | 117 | gpio-controller; |
| 118 | interrupt-controller; | 118 | interrupt-controller; |
| @@ -121,7 +121,7 @@ | |||
| 121 | pioC: gpio@fffff800 { | 121 | pioC: gpio@fffff800 { |
| 122 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | 122 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 123 | reg = <0xfffff800 0x100>; | 123 | reg = <0xfffff800 0x100>; |
| 124 | interrupts = <3 4>; | 124 | interrupts = <3 4 1>; |
| 125 | #gpio-cells = <2>; | 125 | #gpio-cells = <2>; |
| 126 | gpio-controller; | 126 | gpio-controller; |
| 127 | interrupt-controller; | 127 | interrupt-controller; |
| @@ -130,7 +130,7 @@ | |||
| 130 | pioD: gpio@fffffa00 { | 130 | pioD: gpio@fffffa00 { |
| 131 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | 131 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 132 | reg = <0xfffffa00 0x100>; | 132 | reg = <0xfffffa00 0x100>; |
| 133 | interrupts = <3 4>; | 133 | interrupts = <3 4 1>; |
| 134 | #gpio-cells = <2>; | 134 | #gpio-cells = <2>; |
| 135 | gpio-controller; | 135 | gpio-controller; |
| 136 | interrupt-controller; | 136 | interrupt-controller; |
| @@ -139,14 +139,14 @@ | |||
| 139 | dbgu: serial@fffff200 { | 139 | dbgu: serial@fffff200 { |
| 140 | compatible = "atmel,at91sam9260-usart"; | 140 | compatible = "atmel,at91sam9260-usart"; |
| 141 | reg = <0xfffff200 0x200>; | 141 | reg = <0xfffff200 0x200>; |
| 142 | interrupts = <1 4>; | 142 | interrupts = <1 4 7>; |
| 143 | status = "disabled"; | 143 | status = "disabled"; |
| 144 | }; | 144 | }; |
| 145 | 145 | ||
| 146 | usart0: serial@f801c000 { | 146 | usart0: serial@f801c000 { |
| 147 | compatible = "atmel,at91sam9260-usart"; | 147 | compatible = "atmel,at91sam9260-usart"; |
| 148 | reg = <0xf801c000 0x4000>; | 148 | reg = <0xf801c000 0x4000>; |
| 149 | interrupts = <5 4>; | 149 | interrupts = <5 4 5>; |
| 150 | atmel,use-dma-rx; | 150 | atmel,use-dma-rx; |
| 151 | atmel,use-dma-tx; | 151 | atmel,use-dma-tx; |
| 152 | status = "disabled"; | 152 | status = "disabled"; |
| @@ -155,7 +155,7 @@ | |||
| 155 | usart1: serial@f8020000 { | 155 | usart1: serial@f8020000 { |
| 156 | compatible = "atmel,at91sam9260-usart"; | 156 | compatible = "atmel,at91sam9260-usart"; |
| 157 | reg = <0xf8020000 0x4000>; | 157 | reg = <0xf8020000 0x4000>; |
| 158 | interrupts = <6 4>; | 158 | interrupts = <6 4 5>; |
| 159 | atmel,use-dma-rx; | 159 | atmel,use-dma-rx; |
| 160 | atmel,use-dma-tx; | 160 | atmel,use-dma-tx; |
| 161 | status = "disabled"; | 161 | status = "disabled"; |
| @@ -164,7 +164,7 @@ | |||
| 164 | usart2: serial@f8024000 { | 164 | usart2: serial@f8024000 { |
| 165 | compatible = "atmel,at91sam9260-usart"; | 165 | compatible = "atmel,at91sam9260-usart"; |
| 166 | reg = <0xf8024000 0x4000>; | 166 | reg = <0xf8024000 0x4000>; |
| 167 | interrupts = <7 4>; | 167 | interrupts = <7 4 5>; |
| 168 | atmel,use-dma-rx; | 168 | atmel,use-dma-rx; |
| 169 | atmel,use-dma-tx; | 169 | atmel,use-dma-tx; |
| 170 | status = "disabled"; | 170 | status = "disabled"; |
| @@ -173,7 +173,7 @@ | |||
| 173 | usart3: serial@f8028000 { | 173 | usart3: serial@f8028000 { |
| 174 | compatible = "atmel,at91sam9260-usart"; | 174 | compatible = "atmel,at91sam9260-usart"; |
| 175 | reg = <0xf8028000 0x4000>; | 175 | reg = <0xf8028000 0x4000>; |
| 176 | interrupts = <8 4>; | 176 | interrupts = <8 4 5>; |
| 177 | atmel,use-dma-rx; | 177 | atmel,use-dma-rx; |
| 178 | atmel,use-dma-tx; | 178 | atmel,use-dma-tx; |
| 179 | status = "disabled"; | 179 | status = "disabled"; |
| @@ -201,7 +201,7 @@ | |||
| 201 | usb0: ohci@00500000 { | 201 | usb0: ohci@00500000 { |
| 202 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | 202 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
| 203 | reg = <0x00500000 0x00100000>; | 203 | reg = <0x00500000 0x00100000>; |
| 204 | interrupts = <22 4>; | 204 | interrupts = <22 4 2>; |
| 205 | status = "disabled"; | 205 | status = "disabled"; |
| 206 | }; | 206 | }; |
| 207 | }; | 207 | }; |
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 6b3ef4339ae7..4a18c393b136 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi | |||
| @@ -51,10 +51,11 @@ | |||
| 51 | ranges; | 51 | ranges; |
| 52 | 52 | ||
| 53 | aic: interrupt-controller@fffff000 { | 53 | aic: interrupt-controller@fffff000 { |
| 54 | #interrupt-cells = <2>; | 54 | #interrupt-cells = <3>; |
| 55 | compatible = "atmel,at91rm9200-aic"; | 55 | compatible = "atmel,at91rm9200-aic"; |
| 56 | interrupt-controller; | 56 | interrupt-controller; |
| 57 | reg = <0xfffff000 0x200>; | 57 | reg = <0xfffff000 0x200>; |
| 58 | atmel,external-irqs = <31>; | ||
| 58 | }; | 59 | }; |
| 59 | 60 | ||
| 60 | ramc0: ramc@ffffe800 { | 61 | ramc0: ramc@ffffe800 { |
| @@ -80,37 +81,37 @@ | |||
| 80 | pit: timer@fffffe30 { | 81 | pit: timer@fffffe30 { |
| 81 | compatible = "atmel,at91sam9260-pit"; | 82 | compatible = "atmel,at91sam9260-pit"; |
| 82 | reg = <0xfffffe30 0xf>; | 83 | reg = <0xfffffe30 0xf>; |
| 83 | interrupts = <1 4>; | 84 | interrupts = <1 4 7>; |
| 84 | }; | 85 | }; |
| 85 | 86 | ||
| 86 | tcb0: timer@f8008000 { | 87 | tcb0: timer@f8008000 { |
| 87 | compatible = "atmel,at91sam9x5-tcb"; | 88 | compatible = "atmel,at91sam9x5-tcb"; |
| 88 | reg = <0xf8008000 0x100>; | 89 | reg = <0xf8008000 0x100>; |
| 89 | interrupts = <17 4>; | 90 | interrupts = <17 4 0>; |
| 90 | }; | 91 | }; |
| 91 | 92 | ||
| 92 | tcb1: timer@f800c000 { | 93 | tcb1: timer@f800c000 { |
| 93 | compatible = "atmel,at91sam9x5-tcb"; | 94 | compatible = "atmel,at91sam9x5-tcb"; |
| 94 | reg = <0xf800c000 0x100>; | 95 | reg = <0xf800c000 0x100>; |
| 95 | interrupts = <17 4>; | 96 | interrupts = <17 4 0>; |
| 96 | }; | 97 | }; |
| 97 | 98 | ||
| 98 | dma0: dma-controller@ffffec00 { | 99 | dma0: dma-controller@ffffec00 { |
| 99 | compatible = "atmel,at91sam9g45-dma"; | 100 | compatible = "atmel,at91sam9g45-dma"; |
| 100 | reg = <0xffffec00 0x200>; | 101 | reg = <0xffffec00 0x200>; |
| 101 | interrupts = <20 4>; | 102 | interrupts = <20 4 0>; |
| 102 | }; | 103 | }; |
| 103 | 104 | ||
| 104 | dma1: dma-controller@ffffee00 { | 105 | dma1: dma-controller@ffffee00 { |
| 105 | compatible = "atmel,at91sam9g45-dma"; | 106 | compatible = "atmel,at91sam9g45-dma"; |
| 106 | reg = <0xffffee00 0x200>; | 107 | reg = <0xffffee00 0x200>; |
| 107 | interrupts = <21 4>; | 108 | interrupts = <21 4 0>; |
| 108 | }; | 109 | }; |
| 109 | 110 | ||
| 110 | pioA: gpio@fffff400 { | 111 | pioA: gpio@fffff400 { |
| 111 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | 112 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 112 | reg = <0xfffff400 0x100>; | 113 | reg = <0xfffff400 0x100>; |
| 113 | interrupts = <2 4>; | 114 | interrupts = <2 4 1>; |
| 114 | #gpio-cells = <2>; | 115 | #gpio-cells = <2>; |
| 115 | gpio-controller; | 116 | gpio-controller; |
| 116 | interrupt-controller; | 117 | interrupt-controller; |
| @@ -119,7 +120,7 @@ | |||
| 119 | pioB: gpio@fffff600 { | 120 | pioB: gpio@fffff600 { |
| 120 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | 121 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 121 | reg = <0xfffff600 0x100>; | 122 | reg = <0xfffff600 0x100>; |
| 122 | interrupts = <2 4>; | 123 | interrupts = <2 4 1>; |
| 123 | #gpio-cells = <2>; | 124 | #gpio-cells = <2>; |
| 124 | gpio-controller; | 125 | gpio-controller; |
| 125 | interrupt-controller; | 126 | interrupt-controller; |
| @@ -128,7 +129,7 @@ | |||
| 128 | pioC: gpio@fffff800 { | 129 | pioC: gpio@fffff800 { |
| 129 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | 130 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 130 | reg = <0xfffff800 0x100>; | 131 | reg = <0xfffff800 0x100>; |
| 131 | interrupts = <3 4>; | 132 | interrupts = <3 4 1>; |
| 132 | #gpio-cells = <2>; | 133 | #gpio-cells = <2>; |
| 133 | gpio-controller; | 134 | gpio-controller; |
| 134 | interrupt-controller; | 135 | interrupt-controller; |
| @@ -137,7 +138,7 @@ | |||
| 137 | pioD: gpio@fffffa00 { | 138 | pioD: gpio@fffffa00 { |
| 138 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | 139 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 139 | reg = <0xfffffa00 0x100>; | 140 | reg = <0xfffffa00 0x100>; |
| 140 | interrupts = <3 4>; | 141 | interrupts = <3 4 1>; |
| 141 | #gpio-cells = <2>; | 142 | #gpio-cells = <2>; |
| 142 | gpio-controller; | 143 | gpio-controller; |
| 143 | interrupt-controller; | 144 | interrupt-controller; |
| @@ -146,14 +147,14 @@ | |||
| 146 | dbgu: serial@fffff200 { | 147 | dbgu: serial@fffff200 { |
| 147 | compatible = "atmel,at91sam9260-usart"; | 148 | compatible = "atmel,at91sam9260-usart"; |
| 148 | reg = <0xfffff200 0x200>; | 149 | reg = <0xfffff200 0x200>; |
| 149 | interrupts = <1 4>; | 150 | interrupts = <1 4 7>; |
| 150 | status = "disabled"; | 151 | status = "disabled"; |
| 151 | }; | 152 | }; |
| 152 | 153 | ||
| 153 | usart0: serial@f801c000 { | 154 | usart0: serial@f801c000 { |
| 154 | compatible = "atmel,at91sam9260-usart"; | 155 | compatible = "atmel,at91sam9260-usart"; |
| 155 | reg = <0xf801c000 0x200>; | 156 | reg = <0xf801c000 0x200>; |
| 156 | interrupts = <5 4>; | 157 | interrupts = <5 4 5>; |
| 157 | atmel,use-dma-rx; | 158 | atmel,use-dma-rx; |
| 158 | atmel,use-dma-tx; | 159 | atmel,use-dma-tx; |
| 159 | status = "disabled"; | 160 | status = "disabled"; |
| @@ -162,7 +163,7 @@ | |||
| 162 | usart1: serial@f8020000 { | 163 | usart1: serial@f8020000 { |
| 163 | compatible = "atmel,at91sam9260-usart"; | 164 | compatible = "atmel,at91sam9260-usart"; |
| 164 | reg = <0xf8020000 0x200>; | 165 | reg = <0xf8020000 0x200>; |
| 165 | interrupts = <6 4>; | 166 | interrupts = <6 4 5>; |
| 166 | atmel,use-dma-rx; | 167 | atmel,use-dma-rx; |
| 167 | atmel,use-dma-tx; | 168 | atmel,use-dma-tx; |
| 168 | status = "disabled"; | 169 | status = "disabled"; |
| @@ -171,7 +172,7 @@ | |||
| 171 | usart2: serial@f8024000 { | 172 | usart2: serial@f8024000 { |
| 172 | compatible = "atmel,at91sam9260-usart"; | 173 | compatible = "atmel,at91sam9260-usart"; |
| 173 | reg = <0xf8024000 0x200>; | 174 | reg = <0xf8024000 0x200>; |
| 174 | interrupts = <7 4>; | 175 | interrupts = <7 4 5>; |
| 175 | atmel,use-dma-rx; | 176 | atmel,use-dma-rx; |
| 176 | atmel,use-dma-tx; | 177 | atmel,use-dma-tx; |
| 177 | status = "disabled"; | 178 | status = "disabled"; |
| @@ -180,21 +181,21 @@ | |||
| 180 | macb0: ethernet@f802c000 { | 181 | macb0: ethernet@f802c000 { |
| 181 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | 182 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; |
| 182 | reg = <0xf802c000 0x100>; | 183 | reg = <0xf802c000 0x100>; |
| 183 | interrupts = <24 4>; | 184 | interrupts = <24 4 3>; |
| 184 | status = "disabled"; | 185 | status = "disabled"; |
| 185 | }; | 186 | }; |
| 186 | 187 | ||
| 187 | macb1: ethernet@f8030000 { | 188 | macb1: ethernet@f8030000 { |
| 188 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | 189 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; |
| 189 | reg = <0xf8030000 0x100>; | 190 | reg = <0xf8030000 0x100>; |
| 190 | interrupts = <27 4>; | 191 | interrupts = <27 4 3>; |
| 191 | status = "disabled"; | 192 | status = "disabled"; |
| 192 | }; | 193 | }; |
| 193 | 194 | ||
| 194 | adc0: adc@f804c000 { | 195 | adc0: adc@f804c000 { |
| 195 | compatible = "atmel,at91sam9260-adc"; | 196 | compatible = "atmel,at91sam9260-adc"; |
| 196 | reg = <0xf804c000 0x100>; | 197 | reg = <0xf804c000 0x100>; |
| 197 | interrupts = <19 4>; | 198 | interrupts = <19 4 0>; |
| 198 | atmel,adc-use-external; | 199 | atmel,adc-use-external; |
| 199 | atmel,adc-channels-used = <0xffff>; | 200 | atmel,adc-channels-used = <0xffff>; |
| 200 | atmel,adc-vref = <3300>; | 201 | atmel,adc-vref = <3300>; |
| @@ -248,14 +249,14 @@ | |||
| 248 | usb0: ohci@00600000 { | 249 | usb0: ohci@00600000 { |
| 249 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | 250 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
| 250 | reg = <0x00600000 0x100000>; | 251 | reg = <0x00600000 0x100000>; |
| 251 | interrupts = <22 4>; | 252 | interrupts = <22 4 2>; |
| 252 | status = "disabled"; | 253 | status = "disabled"; |
| 253 | }; | 254 | }; |
| 254 | 255 | ||
| 255 | usb1: ehci@00700000 { | 256 | usb1: ehci@00700000 { |
| 256 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; | 257 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; |
| 257 | reg = <0x00700000 0x100000>; | 258 | reg = <0x00700000 0x100000>; |
| 258 | interrupts = <22 4>; | 259 | interrupts = <22 4 2>; |
| 259 | status = "disabled"; | 260 | status = "disabled"; |
| 260 | }; | 261 | }; |
| 261 | }; | 262 | }; |
diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi index e9c2e92f75cb..3180a9c588b9 100644 --- a/arch/arm/boot/dts/db8500.dtsi +++ b/arch/arm/boot/dts/db8500.dtsi | |||
| @@ -206,62 +206,74 @@ | |||
| 206 | 206 | ||
| 207 | // DB8500_REGULATOR_VAPE | 207 | // DB8500_REGULATOR_VAPE |
| 208 | db8500_vape_reg: db8500_vape { | 208 | db8500_vape_reg: db8500_vape { |
| 209 | regulator-compatible = "db8500_vape"; | ||
| 209 | regulator-name = "db8500-vape"; | 210 | regulator-name = "db8500-vape"; |
| 210 | regulator-always-on; | 211 | regulator-always-on; |
| 211 | }; | 212 | }; |
| 212 | 213 | ||
| 213 | // DB8500_REGULATOR_VARM | 214 | // DB8500_REGULATOR_VARM |
| 214 | db8500_varm_reg: db8500_varm { | 215 | db8500_varm_reg: db8500_varm { |
| 216 | regulator-compatible = "db8500_varm"; | ||
| 215 | regulator-name = "db8500-varm"; | 217 | regulator-name = "db8500-varm"; |
| 216 | }; | 218 | }; |
| 217 | 219 | ||
| 218 | // DB8500_REGULATOR_VMODEM | 220 | // DB8500_REGULATOR_VMODEM |
| 219 | db8500_vmodem_reg: db8500_vmodem { | 221 | db8500_vmodem_reg: db8500_vmodem { |
| 222 | regulator-compatible = "db8500_vmodem"; | ||
| 220 | regulator-name = "db8500-vmodem"; | 223 | regulator-name = "db8500-vmodem"; |
| 221 | }; | 224 | }; |
| 222 | 225 | ||
| 223 | // DB8500_REGULATOR_VPLL | 226 | // DB8500_REGULATOR_VPLL |
| 224 | db8500_vpll_reg: db8500_vpll { | 227 | db8500_vpll_reg: db8500_vpll { |
| 228 | regulator-compatible = "db8500_vpll"; | ||
| 225 | regulator-name = "db8500-vpll"; | 229 | regulator-name = "db8500-vpll"; |
| 226 | }; | 230 | }; |
| 227 | 231 | ||
| 228 | // DB8500_REGULATOR_VSMPS1 | 232 | // DB8500_REGULATOR_VSMPS1 |
| 229 | db8500_vsmps1_reg: db8500_vsmps1 { | 233 | db8500_vsmps1_reg: db8500_vsmps1 { |
| 234 | regulator-compatible = "db8500_vsmps1"; | ||
| 230 | regulator-name = "db8500-vsmps1"; | 235 | regulator-name = "db8500-vsmps1"; |
| 231 | }; | 236 | }; |
| 232 | 237 | ||
| 233 | // DB8500_REGULATOR_VSMPS2 | 238 | // DB8500_REGULATOR_VSMPS2 |
| 234 | db8500_vsmps2_reg: db8500_vsmps2 { | 239 | db8500_vsmps2_reg: db8500_vsmps2 { |
| 240 | regulator-compatible = "db8500_vsmps2"; | ||
| 235 | regulator-name = "db8500-vsmps2"; | 241 | regulator-name = "db8500-vsmps2"; |
| 236 | }; | 242 | }; |
| 237 | 243 | ||
| 238 | // DB8500_REGULATOR_VSMPS3 | 244 | // DB8500_REGULATOR_VSMPS3 |
| 239 | db8500_vsmps3_reg: db8500_vsmps3 { | 245 | db8500_vsmps3_reg: db8500_vsmps3 { |
| 246 | regulator-compatible = "db8500_vsmps3"; | ||
| 240 | regulator-name = "db8500-vsmps3"; | 247 | regulator-name = "db8500-vsmps3"; |
| 241 | }; | 248 | }; |
| 242 | 249 | ||
| 243 | // DB8500_REGULATOR_VRF1 | 250 | // DB8500_REGULATOR_VRF1 |
| 244 | db8500_vrf1_reg: db8500_vrf1 { | 251 | db8500_vrf1_reg: db8500_vrf1 { |
| 252 | regulator-compatible = "db8500_vrf1"; | ||
| 245 | regulator-name = "db8500-vrf1"; | 253 | regulator-name = "db8500-vrf1"; |
| 246 | }; | 254 | }; |
| 247 | 255 | ||
| 248 | // DB8500_REGULATOR_SWITCH_SVAMMDSP | 256 | // DB8500_REGULATOR_SWITCH_SVAMMDSP |
| 249 | db8500_sva_mmdsp_reg: db8500_sva_mmdsp { | 257 | db8500_sva_mmdsp_reg: db8500_sva_mmdsp { |
| 258 | regulator-compatible = "db8500_sva_mmdsp"; | ||
| 250 | regulator-name = "db8500-sva-mmdsp"; | 259 | regulator-name = "db8500-sva-mmdsp"; |
| 251 | }; | 260 | }; |
| 252 | 261 | ||
| 253 | // DB8500_REGULATOR_SWITCH_SVAMMDSPRET | 262 | // DB8500_REGULATOR_SWITCH_SVAMMDSPRET |
| 254 | db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { | 263 | db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { |
| 264 | regulator-compatible = "db8500_sva_mmdsp_ret"; | ||
| 255 | regulator-name = "db8500-sva-mmdsp-ret"; | 265 | regulator-name = "db8500-sva-mmdsp-ret"; |
| 256 | }; | 266 | }; |
| 257 | 267 | ||
| 258 | // DB8500_REGULATOR_SWITCH_SVAPIPE | 268 | // DB8500_REGULATOR_SWITCH_SVAPIPE |
| 259 | db8500_sva_pipe_reg: db8500_sva_pipe { | 269 | db8500_sva_pipe_reg: db8500_sva_pipe { |
| 270 | regulator-compatible = "db8500_sva_pipe"; | ||
| 260 | regulator-name = "db8500_sva_pipe"; | 271 | regulator-name = "db8500_sva_pipe"; |
| 261 | }; | 272 | }; |
| 262 | 273 | ||
| 263 | // DB8500_REGULATOR_SWITCH_SIAMMDSP | 274 | // DB8500_REGULATOR_SWITCH_SIAMMDSP |
| 264 | db8500_sia_mmdsp_reg: db8500_sia_mmdsp { | 275 | db8500_sia_mmdsp_reg: db8500_sia_mmdsp { |
| 276 | regulator-compatible = "db8500_sia_mmdsp"; | ||
| 265 | regulator-name = "db8500_sia_mmdsp"; | 277 | regulator-name = "db8500_sia_mmdsp"; |
| 266 | }; | 278 | }; |
| 267 | 279 | ||
| @@ -272,38 +284,45 @@ | |||
| 272 | 284 | ||
| 273 | // DB8500_REGULATOR_SWITCH_SIAPIPE | 285 | // DB8500_REGULATOR_SWITCH_SIAPIPE |
| 274 | db8500_sia_pipe_reg: db8500_sia_pipe { | 286 | db8500_sia_pipe_reg: db8500_sia_pipe { |
| 287 | regulator-compatible = "db8500_sia_pipe"; | ||
| 275 | regulator-name = "db8500-sia-pipe"; | 288 | regulator-name = "db8500-sia-pipe"; |
| 276 | }; | 289 | }; |
| 277 | 290 | ||
| 278 | // DB8500_REGULATOR_SWITCH_SGA | 291 | // DB8500_REGULATOR_SWITCH_SGA |
| 279 | db8500_sga_reg: db8500_sga { | 292 | db8500_sga_reg: db8500_sga { |
| 293 | regulator-compatible = "db8500_sga"; | ||
| 280 | regulator-name = "db8500-sga"; | 294 | regulator-name = "db8500-sga"; |
| 281 | vin-supply = <&db8500_vape_reg>; | 295 | vin-supply = <&db8500_vape_reg>; |
| 282 | }; | 296 | }; |
| 283 | 297 | ||
| 284 | // DB8500_REGULATOR_SWITCH_B2R2_MCDE | 298 | // DB8500_REGULATOR_SWITCH_B2R2_MCDE |
| 285 | db8500_b2r2_mcde_reg: db8500_b2r2_mcde { | 299 | db8500_b2r2_mcde_reg: db8500_b2r2_mcde { |
| 300 | regulator-compatible = "db8500_b2r2_mcde"; | ||
| 286 | regulator-name = "db8500-b2r2-mcde"; | 301 | regulator-name = "db8500-b2r2-mcde"; |
| 287 | vin-supply = <&db8500_vape_reg>; | 302 | vin-supply = <&db8500_vape_reg>; |
| 288 | }; | 303 | }; |
| 289 | 304 | ||
| 290 | // DB8500_REGULATOR_SWITCH_ESRAM12 | 305 | // DB8500_REGULATOR_SWITCH_ESRAM12 |
| 291 | db8500_esram12_reg: db8500_esram12 { | 306 | db8500_esram12_reg: db8500_esram12 { |
| 307 | regulator-compatible = "db8500_esram12"; | ||
| 292 | regulator-name = "db8500-esram12"; | 308 | regulator-name = "db8500-esram12"; |
| 293 | }; | 309 | }; |
| 294 | 310 | ||
| 295 | // DB8500_REGULATOR_SWITCH_ESRAM12RET | 311 | // DB8500_REGULATOR_SWITCH_ESRAM12RET |
| 296 | db8500_esram12_ret_reg: db8500_esram12_ret { | 312 | db8500_esram12_ret_reg: db8500_esram12_ret { |
| 313 | regulator-compatible = "db8500_esram12_ret"; | ||
| 297 | regulator-name = "db8500-esram12-ret"; | 314 | regulator-name = "db8500-esram12-ret"; |
| 298 | }; | 315 | }; |
| 299 | 316 | ||
| 300 | // DB8500_REGULATOR_SWITCH_ESRAM34 | 317 | // DB8500_REGULATOR_SWITCH_ESRAM34 |
| 301 | db8500_esram34_reg: db8500_esram34 { | 318 | db8500_esram34_reg: db8500_esram34 { |
| 319 | regulator-compatible = "db8500_esram34"; | ||
| 302 | regulator-name = "db8500-esram34"; | 320 | regulator-name = "db8500-esram34"; |
| 303 | }; | 321 | }; |
| 304 | 322 | ||
| 305 | // DB8500_REGULATOR_SWITCH_ESRAM34RET | 323 | // DB8500_REGULATOR_SWITCH_ESRAM34RET |
| 306 | db8500_esram34_ret_reg: db8500_esram34_ret { | 324 | db8500_esram34_ret_reg: db8500_esram34_ret { |
| 325 | regulator-compatible = "db8500_esram34_ret"; | ||
| 307 | regulator-name = "db8500-esram34-ret"; | 326 | regulator-name = "db8500-esram34-ret"; |
| 308 | }; | 327 | }; |
| 309 | }; | 328 | }; |
| @@ -375,6 +394,7 @@ | |||
| 375 | 394 | ||
| 376 | // supplies to the display/camera | 395 | // supplies to the display/camera |
| 377 | ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { | 396 | ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { |
| 397 | regulator-compatible = "ab8500_ldo_aux1"; | ||
| 378 | regulator-name = "V-DISPLAY"; | 398 | regulator-name = "V-DISPLAY"; |
| 379 | regulator-min-microvolt = <2500000>; | 399 | regulator-min-microvolt = <2500000>; |
| 380 | regulator-max-microvolt = <2900000>; | 400 | regulator-max-microvolt = <2900000>; |
| @@ -385,6 +405,7 @@ | |||
| 385 | 405 | ||
| 386 | // supplies to the on-board eMMC | 406 | // supplies to the on-board eMMC |
| 387 | ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { | 407 | ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { |
| 408 | regulator-compatible = "ab8500_ldo_aux2"; | ||
| 388 | regulator-name = "V-eMMC1"; | 409 | regulator-name = "V-eMMC1"; |
| 389 | regulator-min-microvolt = <1100000>; | 410 | regulator-min-microvolt = <1100000>; |
| 390 | regulator-max-microvolt = <3300000>; | 411 | regulator-max-microvolt = <3300000>; |
| @@ -392,6 +413,7 @@ | |||
| 392 | 413 | ||
| 393 | // supply for VAUX3; SDcard slots | 414 | // supply for VAUX3; SDcard slots |
| 394 | ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { | 415 | ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { |
| 416 | regulator-compatible = "ab8500_ldo_aux3"; | ||
| 395 | regulator-name = "V-MMC-SD"; | 417 | regulator-name = "V-MMC-SD"; |
| 396 | regulator-min-microvolt = <1100000>; | 418 | regulator-min-microvolt = <1100000>; |
| 397 | regulator-max-microvolt = <3300000>; | 419 | regulator-max-microvolt = <3300000>; |
| @@ -399,41 +421,49 @@ | |||
| 399 | 421 | ||
| 400 | // supply for v-intcore12; VINTCORE12 LDO | 422 | // supply for v-intcore12; VINTCORE12 LDO |
| 401 | ab8500_ldo_initcore_reg: ab8500_ldo_initcore { | 423 | ab8500_ldo_initcore_reg: ab8500_ldo_initcore { |
| 424 | regulator-compatible = "ab8500_ldo_initcore"; | ||
| 402 | regulator-name = "V-INTCORE"; | 425 | regulator-name = "V-INTCORE"; |
| 403 | }; | 426 | }; |
| 404 | 427 | ||
| 405 | // supply for tvout; gpadc; TVOUT LDO | 428 | // supply for tvout; gpadc; TVOUT LDO |
| 406 | ab8500_ldo_tvout_reg: ab8500_ldo_tvout { | 429 | ab8500_ldo_tvout_reg: ab8500_ldo_tvout { |
| 430 | regulator-compatible = "ab8500_ldo_tvout"; | ||
| 407 | regulator-name = "V-TVOUT"; | 431 | regulator-name = "V-TVOUT"; |
| 408 | }; | 432 | }; |
| 409 | 433 | ||
| 410 | // supply for ab8500-usb; USB LDO | 434 | // supply for ab8500-usb; USB LDO |
| 411 | ab8500_ldo_usb_reg: ab8500_ldo_usb { | 435 | ab8500_ldo_usb_reg: ab8500_ldo_usb { |
| 436 | regulator-compatible = "ab8500_ldo_usb"; | ||
| 412 | regulator-name = "dummy"; | 437 | regulator-name = "dummy"; |
| 413 | }; | 438 | }; |
| 414 | 439 | ||
| 415 | // supply for ab8500-vaudio; VAUDIO LDO | 440 | // supply for ab8500-vaudio; VAUDIO LDO |
| 416 | ab8500_ldo_audio_reg: ab8500_ldo_audio { | 441 | ab8500_ldo_audio_reg: ab8500_ldo_audio { |
| 442 | regulator-compatible = "ab8500_ldo_audio"; | ||
| 417 | regulator-name = "V-AUD"; | 443 | regulator-name = "V-AUD"; |
| 418 | }; | 444 | }; |
| 419 | 445 | ||
| 420 | // supply for v-anamic1 VAMic1-LDO | 446 | // supply for v-anamic1 VAMic1-LDO |
| 421 | ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { | 447 | ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { |
| 448 | regulator-compatible = "ab8500_ldo_anamic1"; | ||
| 422 | regulator-name = "V-AMIC1"; | 449 | regulator-name = "V-AMIC1"; |
| 423 | }; | 450 | }; |
| 424 | 451 | ||
| 425 | // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1 | 452 | // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1 |
| 426 | ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 { | 453 | ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 { |
| 454 | regulator-compatible = "ab8500_ldo_amamic2"; | ||
| 427 | regulator-name = "V-AMIC2"; | 455 | regulator-name = "V-AMIC2"; |
| 428 | }; | 456 | }; |
| 429 | 457 | ||
| 430 | // supply for v-dmic; VDMIC LDO | 458 | // supply for v-dmic; VDMIC LDO |
| 431 | ab8500_ldo_dmic_reg: ab8500_ldo_dmic { | 459 | ab8500_ldo_dmic_reg: ab8500_ldo_dmic { |
| 460 | regulator-compatible = "ab8500_ldo_dmic"; | ||
| 432 | regulator-name = "V-DMIC"; | 461 | regulator-name = "V-DMIC"; |
| 433 | }; | 462 | }; |
| 434 | 463 | ||
| 435 | // supply for U8500 CSI/DSI; VANA LDO | 464 | // supply for U8500 CSI/DSI; VANA LDO |
| 436 | ab8500_ldo_ana_reg: ab8500_ldo_ana { | 465 | ab8500_ldo_ana_reg: ab8500_ldo_ana { |
| 466 | regulator-compatible = "ab8500_ldo_ana"; | ||
| 437 | regulator-name = "V-CSI/DSI"; | 467 | regulator-name = "V-CSI/DSI"; |
| 438 | }; | 468 | }; |
| 439 | }; | 469 | }; |
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index 5b4506c0a8c4..cdcb98c7e075 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts | |||
| @@ -61,9 +61,9 @@ | |||
| 61 | }; | 61 | }; |
| 62 | 62 | ||
| 63 | &mmc2 { | 63 | &mmc2 { |
| 64 | status = "disable"; | 64 | status = "disabled"; |
| 65 | }; | 65 | }; |
| 66 | 66 | ||
| 67 | &mmc3 { | 67 | &mmc3 { |
| 68 | status = "disable"; | 68 | status = "disabled"; |
| 69 | }; | 69 | }; |
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts index f57f5e8d0035..9880c12877b3 100644 --- a/arch/arm/boot/dts/omap4-panda.dts +++ b/arch/arm/boot/dts/omap4-panda.dts | |||
| @@ -111,15 +111,15 @@ | |||
| 111 | }; | 111 | }; |
| 112 | 112 | ||
| 113 | &mmc2 { | 113 | &mmc2 { |
| 114 | status = "disable"; | 114 | status = "disabled"; |
| 115 | }; | 115 | }; |
| 116 | 116 | ||
| 117 | &mmc3 { | 117 | &mmc3 { |
| 118 | status = "disable"; | 118 | status = "disabled"; |
| 119 | }; | 119 | }; |
| 120 | 120 | ||
| 121 | &mmc4 { | 121 | &mmc4 { |
| 122 | status = "disable"; | 122 | status = "disabled"; |
| 123 | }; | 123 | }; |
| 124 | 124 | ||
| 125 | &mmc5 { | 125 | &mmc5 { |
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index a18cf103e171..72216e932fc0 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts | |||
| @@ -215,11 +215,11 @@ | |||
| 215 | }; | 215 | }; |
| 216 | 216 | ||
| 217 | &mmc3 { | 217 | &mmc3 { |
| 218 | status = "disable"; | 218 | status = "disabled"; |
| 219 | }; | 219 | }; |
| 220 | 220 | ||
| 221 | &mmc4 { | 221 | &mmc4 { |
| 222 | status = "disable"; | 222 | status = "disabled"; |
| 223 | }; | 223 | }; |
| 224 | 224 | ||
| 225 | &mmc5 { | 225 | &mmc5 { |
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi index 10dcec7e7321..f7b84aced654 100644 --- a/arch/arm/boot/dts/spear13xx.dtsi +++ b/arch/arm/boot/dts/spear13xx.dtsi | |||
| @@ -43,8 +43,8 @@ | |||
| 43 | 43 | ||
| 44 | pmu { | 44 | pmu { |
| 45 | compatible = "arm,cortex-a9-pmu"; | 45 | compatible = "arm,cortex-a9-pmu"; |
| 46 | interrupts = <0 8 0x04 | 46 | interrupts = <0 6 0x04 |
| 47 | 0 9 0x04>; | 47 | 0 7 0x04>; |
| 48 | }; | 48 | }; |
| 49 | 49 | ||
| 50 | L2: l2-cache { | 50 | L2: l2-cache { |
| @@ -119,8 +119,8 @@ | |||
| 119 | gmac0: eth@e2000000 { | 119 | gmac0: eth@e2000000 { |
| 120 | compatible = "st,spear600-gmac"; | 120 | compatible = "st,spear600-gmac"; |
| 121 | reg = <0xe2000000 0x8000>; | 121 | reg = <0xe2000000 0x8000>; |
| 122 | interrupts = <0 23 0x4 | 122 | interrupts = <0 33 0x4 |
| 123 | 0 24 0x4>; | 123 | 0 34 0x4>; |
| 124 | interrupt-names = "macirq", "eth_wake_irq"; | 124 | interrupt-names = "macirq", "eth_wake_irq"; |
| 125 | status = "disabled"; | 125 | status = "disabled"; |
| 126 | }; | 126 | }; |
| @@ -202,6 +202,7 @@ | |||
| 202 | kbd@e0300000 { | 202 | kbd@e0300000 { |
| 203 | compatible = "st,spear300-kbd"; | 203 | compatible = "st,spear300-kbd"; |
| 204 | reg = <0xe0300000 0x1000>; | 204 | reg = <0xe0300000 0x1000>; |
| 205 | interrupts = <0 52 0x4>; | ||
| 205 | status = "disabled"; | 206 | status = "disabled"; |
| 206 | }; | 207 | }; |
| 207 | 208 | ||
| @@ -224,7 +225,7 @@ | |||
| 224 | serial@e0000000 { | 225 | serial@e0000000 { |
| 225 | compatible = "arm,pl011", "arm,primecell"; | 226 | compatible = "arm,pl011", "arm,primecell"; |
| 226 | reg = <0xe0000000 0x1000>; | 227 | reg = <0xe0000000 0x1000>; |
| 227 | interrupts = <0 36 0x4>; | 228 | interrupts = <0 35 0x4>; |
| 228 | status = "disabled"; | 229 | status = "disabled"; |
| 229 | }; | 230 | }; |
| 230 | 231 | ||
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts index c13fd1f3b09f..e4e912f95024 100644 --- a/arch/arm/boot/dts/spear320-evb.dts +++ b/arch/arm/boot/dts/spear320-evb.dts | |||
| @@ -15,8 +15,8 @@ | |||
| 15 | /include/ "spear320.dtsi" | 15 | /include/ "spear320.dtsi" |
| 16 | 16 | ||
| 17 | / { | 17 | / { |
| 18 | model = "ST SPEAr300 Evaluation Board"; | 18 | model = "ST SPEAr320 Evaluation Board"; |
| 19 | compatible = "st,spear300-evb", "st,spear300"; | 19 | compatible = "st,spear320-evb", "st,spear320"; |
| 20 | #address-cells = <1>; | 20 | #address-cells = <1>; |
| 21 | #size-cells = <1>; | 21 | #size-cells = <1>; |
| 22 | 22 | ||
| @@ -26,7 +26,7 @@ | |||
| 26 | 26 | ||
| 27 | ahb { | 27 | ahb { |
| 28 | pinmux@b3000000 { | 28 | pinmux@b3000000 { |
| 29 | st,pinmux-mode = <3>; | 29 | st,pinmux-mode = <4>; |
| 30 | pinctrl-names = "default"; | 30 | pinctrl-names = "default"; |
| 31 | pinctrl-0 = <&state_default>; | 31 | pinctrl-0 = <&state_default>; |
| 32 | 32 | ||
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi index 089f0a42c50e..a3c36e47d7ef 100644 --- a/arch/arm/boot/dts/spear600.dtsi +++ b/arch/arm/boot/dts/spear600.dtsi | |||
| @@ -181,6 +181,7 @@ | |||
| 181 | timer@f0000000 { | 181 | timer@f0000000 { |
| 182 | compatible = "st,spear-timer"; | 182 | compatible = "st,spear-timer"; |
| 183 | reg = <0xf0000000 0x400>; | 183 | reg = <0xf0000000 0x400>; |
| 184 | interrupt-parent = <&vic0>; | ||
| 184 | interrupts = <16>; | 185 | interrupts = <16>; |
| 185 | }; | 186 | }; |
| 186 | }; | 187 | }; |
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 59116b852434..9f1921634eb7 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi | |||
| @@ -72,7 +72,7 @@ | |||
| 72 | reg = <0x70002800 0x200>; | 72 | reg = <0x70002800 0x200>; |
| 73 | interrupts = <0 13 0x04>; | 73 | interrupts = <0 13 0x04>; |
| 74 | nvidia,dma-request-selector = <&apbdma 2>; | 74 | nvidia,dma-request-selector = <&apbdma 2>; |
| 75 | status = "disable"; | 75 | status = "disabled"; |
| 76 | }; | 76 | }; |
| 77 | 77 | ||
| 78 | tegra_i2s2: i2s@70002a00 { | 78 | tegra_i2s2: i2s@70002a00 { |
| @@ -80,7 +80,7 @@ | |||
| 80 | reg = <0x70002a00 0x200>; | 80 | reg = <0x70002a00 0x200>; |
| 81 | interrupts = <0 3 0x04>; | 81 | interrupts = <0 3 0x04>; |
| 82 | nvidia,dma-request-selector = <&apbdma 1>; | 82 | nvidia,dma-request-selector = <&apbdma 1>; |
| 83 | status = "disable"; | 83 | status = "disabled"; |
| 84 | }; | 84 | }; |
| 85 | 85 | ||
| 86 | serial@70006000 { | 86 | serial@70006000 { |
| @@ -88,7 +88,7 @@ | |||
| 88 | reg = <0x70006000 0x40>; | 88 | reg = <0x70006000 0x40>; |
| 89 | reg-shift = <2>; | 89 | reg-shift = <2>; |
| 90 | interrupts = <0 36 0x04>; | 90 | interrupts = <0 36 0x04>; |
| 91 | status = "disable"; | 91 | status = "disabled"; |
| 92 | }; | 92 | }; |
| 93 | 93 | ||
| 94 | serial@70006040 { | 94 | serial@70006040 { |
| @@ -96,7 +96,7 @@ | |||
| 96 | reg = <0x70006040 0x40>; | 96 | reg = <0x70006040 0x40>; |
| 97 | reg-shift = <2>; | 97 | reg-shift = <2>; |
| 98 | interrupts = <0 37 0x04>; | 98 | interrupts = <0 37 0x04>; |
| 99 | status = "disable"; | 99 | status = "disabled"; |
| 100 | }; | 100 | }; |
| 101 | 101 | ||
| 102 | serial@70006200 { | 102 | serial@70006200 { |
| @@ -104,7 +104,7 @@ | |||
| 104 | reg = <0x70006200 0x100>; | 104 | reg = <0x70006200 0x100>; |
| 105 | reg-shift = <2>; | 105 | reg-shift = <2>; |
| 106 | interrupts = <0 46 0x04>; | 106 | interrupts = <0 46 0x04>; |
| 107 | status = "disable"; | 107 | status = "disabled"; |
| 108 | }; | 108 | }; |
| 109 | 109 | ||
| 110 | serial@70006300 { | 110 | serial@70006300 { |
| @@ -112,7 +112,7 @@ | |||
| 112 | reg = <0x70006300 0x100>; | 112 | reg = <0x70006300 0x100>; |
| 113 | reg-shift = <2>; | 113 | reg-shift = <2>; |
| 114 | interrupts = <0 90 0x04>; | 114 | interrupts = <0 90 0x04>; |
| 115 | status = "disable"; | 115 | status = "disabled"; |
| 116 | }; | 116 | }; |
| 117 | 117 | ||
| 118 | serial@70006400 { | 118 | serial@70006400 { |
| @@ -120,7 +120,7 @@ | |||
| 120 | reg = <0x70006400 0x100>; | 120 | reg = <0x70006400 0x100>; |
| 121 | reg-shift = <2>; | 121 | reg-shift = <2>; |
| 122 | interrupts = <0 91 0x04>; | 122 | interrupts = <0 91 0x04>; |
| 123 | status = "disable"; | 123 | status = "disabled"; |
| 124 | }; | 124 | }; |
| 125 | 125 | ||
| 126 | i2c@7000c000 { | 126 | i2c@7000c000 { |
| @@ -129,7 +129,7 @@ | |||
| 129 | interrupts = <0 38 0x04>; | 129 | interrupts = <0 38 0x04>; |
| 130 | #address-cells = <1>; | 130 | #address-cells = <1>; |
| 131 | #size-cells = <0>; | 131 | #size-cells = <0>; |
| 132 | status = "disable"; | 132 | status = "disabled"; |
| 133 | }; | 133 | }; |
| 134 | 134 | ||
| 135 | i2c@7000c400 { | 135 | i2c@7000c400 { |
| @@ -138,7 +138,7 @@ | |||
| 138 | interrupts = <0 84 0x04>; | 138 | interrupts = <0 84 0x04>; |
| 139 | #address-cells = <1>; | 139 | #address-cells = <1>; |
| 140 | #size-cells = <0>; | 140 | #size-cells = <0>; |
| 141 | status = "disable"; | 141 | status = "disabled"; |
| 142 | }; | 142 | }; |
| 143 | 143 | ||
| 144 | i2c@7000c500 { | 144 | i2c@7000c500 { |
| @@ -147,7 +147,7 @@ | |||
| 147 | interrupts = <0 92 0x04>; | 147 | interrupts = <0 92 0x04>; |
| 148 | #address-cells = <1>; | 148 | #address-cells = <1>; |
| 149 | #size-cells = <0>; | 149 | #size-cells = <0>; |
| 150 | status = "disable"; | 150 | status = "disabled"; |
| 151 | }; | 151 | }; |
| 152 | 152 | ||
| 153 | i2c@7000d000 { | 153 | i2c@7000d000 { |
| @@ -156,7 +156,7 @@ | |||
| 156 | interrupts = <0 53 0x04>; | 156 | interrupts = <0 53 0x04>; |
| 157 | #address-cells = <1>; | 157 | #address-cells = <1>; |
| 158 | #size-cells = <0>; | 158 | #size-cells = <0>; |
| 159 | status = "disable"; | 159 | status = "disabled"; |
| 160 | }; | 160 | }; |
| 161 | 161 | ||
| 162 | pmc { | 162 | pmc { |
| @@ -190,7 +190,7 @@ | |||
| 190 | interrupts = <0 20 0x04>; | 190 | interrupts = <0 20 0x04>; |
| 191 | phy_type = "utmi"; | 191 | phy_type = "utmi"; |
| 192 | nvidia,has-legacy-mode; | 192 | nvidia,has-legacy-mode; |
| 193 | status = "disable"; | 193 | status = "disabled"; |
| 194 | }; | 194 | }; |
| 195 | 195 | ||
| 196 | usb@c5004000 { | 196 | usb@c5004000 { |
| @@ -198,7 +198,7 @@ | |||
| 198 | reg = <0xc5004000 0x4000>; | 198 | reg = <0xc5004000 0x4000>; |
| 199 | interrupts = <0 21 0x04>; | 199 | interrupts = <0 21 0x04>; |
| 200 | phy_type = "ulpi"; | 200 | phy_type = "ulpi"; |
| 201 | status = "disable"; | 201 | status = "disabled"; |
| 202 | }; | 202 | }; |
| 203 | 203 | ||
| 204 | usb@c5008000 { | 204 | usb@c5008000 { |
| @@ -206,35 +206,35 @@ | |||
| 206 | reg = <0xc5008000 0x4000>; | 206 | reg = <0xc5008000 0x4000>; |
| 207 | interrupts = <0 97 0x04>; | 207 | interrupts = <0 97 0x04>; |
| 208 | phy_type = "utmi"; | 208 | phy_type = "utmi"; |
| 209 | status = "disable"; | 209 | status = "disabled"; |
| 210 | }; | 210 | }; |
| 211 | 211 | ||
| 212 | sdhci@c8000000 { | 212 | sdhci@c8000000 { |
| 213 | compatible = "nvidia,tegra20-sdhci"; | 213 | compatible = "nvidia,tegra20-sdhci"; |
| 214 | reg = <0xc8000000 0x200>; | 214 | reg = <0xc8000000 0x200>; |
| 215 | interrupts = <0 14 0x04>; | 215 | interrupts = <0 14 0x04>; |
| 216 | status = "disable"; | 216 | status = "disabled"; |
| 217 | }; | 217 | }; |
| 218 | 218 | ||
| 219 | sdhci@c8000200 { | 219 | sdhci@c8000200 { |
| 220 | compatible = "nvidia,tegra20-sdhci"; | 220 | compatible = "nvidia,tegra20-sdhci"; |
| 221 | reg = <0xc8000200 0x200>; | 221 | reg = <0xc8000200 0x200>; |
| 222 | interrupts = <0 15 0x04>; | 222 | interrupts = <0 15 0x04>; |
| 223 | status = "disable"; | 223 | status = "disabled"; |
| 224 | }; | 224 | }; |
| 225 | 225 | ||
| 226 | sdhci@c8000400 { | 226 | sdhci@c8000400 { |
| 227 | compatible = "nvidia,tegra20-sdhci"; | 227 | compatible = "nvidia,tegra20-sdhci"; |
| 228 | reg = <0xc8000400 0x200>; | 228 | reg = <0xc8000400 0x200>; |
| 229 | interrupts = <0 19 0x04>; | 229 | interrupts = <0 19 0x04>; |
| 230 | status = "disable"; | 230 | status = "disabled"; |
| 231 | }; | 231 | }; |
| 232 | 232 | ||
| 233 | sdhci@c8000600 { | 233 | sdhci@c8000600 { |
| 234 | compatible = "nvidia,tegra20-sdhci"; | 234 | compatible = "nvidia,tegra20-sdhci"; |
| 235 | reg = <0xc8000600 0x200>; | 235 | reg = <0xc8000600 0x200>; |
| 236 | interrupts = <0 31 0x04>; | 236 | interrupts = <0 31 0x04>; |
| 237 | status = "disable"; | 237 | status = "disabled"; |
| 238 | }; | 238 | }; |
| 239 | 239 | ||
| 240 | pmu { | 240 | pmu { |
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 19479393842e..da740191771f 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi | |||
| @@ -82,7 +82,7 @@ | |||
| 82 | reg = <0x70006000 0x40>; | 82 | reg = <0x70006000 0x40>; |
| 83 | reg-shift = <2>; | 83 | reg-shift = <2>; |
| 84 | interrupts = <0 36 0x04>; | 84 | interrupts = <0 36 0x04>; |
| 85 | status = "disable"; | 85 | status = "disabled"; |
| 86 | }; | 86 | }; |
| 87 | 87 | ||
| 88 | serial@70006040 { | 88 | serial@70006040 { |
| @@ -90,7 +90,7 @@ | |||
| 90 | reg = <0x70006040 0x40>; | 90 | reg = <0x70006040 0x40>; |
| 91 | reg-shift = <2>; | 91 | reg-shift = <2>; |
| 92 | interrupts = <0 37 0x04>; | 92 | interrupts = <0 37 0x04>; |
| 93 | status = "disable"; | 93 | status = "disabled"; |
| 94 | }; | 94 | }; |
| 95 | 95 | ||
| 96 | serial@70006200 { | 96 | serial@70006200 { |
| @@ -98,7 +98,7 @@ | |||
| 98 | reg = <0x70006200 0x100>; | 98 | reg = <0x70006200 0x100>; |
| 99 | reg-shift = <2>; | 99 | reg-shift = <2>; |
| 100 | interrupts = <0 46 0x04>; | 100 | interrupts = <0 46 0x04>; |
| 101 | status = "disable"; | 101 | status = "disabled"; |
| 102 | }; | 102 | }; |
| 103 | 103 | ||
| 104 | serial@70006300 { | 104 | serial@70006300 { |
| @@ -106,7 +106,7 @@ | |||
| 106 | reg = <0x70006300 0x100>; | 106 | reg = <0x70006300 0x100>; |
| 107 | reg-shift = <2>; | 107 | reg-shift = <2>; |
| 108 | interrupts = <0 90 0x04>; | 108 | interrupts = <0 90 0x04>; |
| 109 | status = "disable"; | 109 | status = "disabled"; |
| 110 | }; | 110 | }; |
| 111 | 111 | ||
| 112 | serial@70006400 { | 112 | serial@70006400 { |
| @@ -114,7 +114,7 @@ | |||
| 114 | reg = <0x70006400 0x100>; | 114 | reg = <0x70006400 0x100>; |
| 115 | reg-shift = <2>; | 115 | reg-shift = <2>; |
| 116 | interrupts = <0 91 0x04>; | 116 | interrupts = <0 91 0x04>; |
| 117 | status = "disable"; | 117 | status = "disabled"; |
| 118 | }; | 118 | }; |
| 119 | 119 | ||
| 120 | i2c@7000c000 { | 120 | i2c@7000c000 { |
| @@ -123,7 +123,7 @@ | |||
| 123 | interrupts = <0 38 0x04>; | 123 | interrupts = <0 38 0x04>; |
| 124 | #address-cells = <1>; | 124 | #address-cells = <1>; |
| 125 | #size-cells = <0>; | 125 | #size-cells = <0>; |
| 126 | status = "disable"; | 126 | status = "disabled"; |
| 127 | }; | 127 | }; |
| 128 | 128 | ||
| 129 | i2c@7000c400 { | 129 | i2c@7000c400 { |
| @@ -132,7 +132,7 @@ | |||
| 132 | interrupts = <0 84 0x04>; | 132 | interrupts = <0 84 0x04>; |
| 133 | #address-cells = <1>; | 133 | #address-cells = <1>; |
| 134 | #size-cells = <0>; | 134 | #size-cells = <0>; |
| 135 | status = "disable"; | 135 | status = "disabled"; |
| 136 | }; | 136 | }; |
| 137 | 137 | ||
| 138 | i2c@7000c500 { | 138 | i2c@7000c500 { |
| @@ -141,7 +141,7 @@ | |||
| 141 | interrupts = <0 92 0x04>; | 141 | interrupts = <0 92 0x04>; |
| 142 | #address-cells = <1>; | 142 | #address-cells = <1>; |
| 143 | #size-cells = <0>; | 143 | #size-cells = <0>; |
| 144 | status = "disable"; | 144 | status = "disabled"; |
| 145 | }; | 145 | }; |
| 146 | 146 | ||
| 147 | i2c@7000c700 { | 147 | i2c@7000c700 { |
| @@ -150,7 +150,7 @@ | |||
| 150 | interrupts = <0 120 0x04>; | 150 | interrupts = <0 120 0x04>; |
| 151 | #address-cells = <1>; | 151 | #address-cells = <1>; |
| 152 | #size-cells = <0>; | 152 | #size-cells = <0>; |
| 153 | status = "disable"; | 153 | status = "disabled"; |
| 154 | }; | 154 | }; |
| 155 | 155 | ||
| 156 | i2c@7000d000 { | 156 | i2c@7000d000 { |
| @@ -159,7 +159,7 @@ | |||
| 159 | interrupts = <0 53 0x04>; | 159 | interrupts = <0 53 0x04>; |
| 160 | #address-cells = <1>; | 160 | #address-cells = <1>; |
| 161 | #size-cells = <0>; | 161 | #size-cells = <0>; |
| 162 | status = "disable"; | 162 | status = "disabled"; |
| 163 | }; | 163 | }; |
| 164 | 164 | ||
| 165 | pmc { | 165 | pmc { |
| @@ -201,35 +201,35 @@ | |||
| 201 | compatible = "nvidia,tegra30-i2s"; | 201 | compatible = "nvidia,tegra30-i2s"; |
| 202 | reg = <0x70080300 0x100>; | 202 | reg = <0x70080300 0x100>; |
| 203 | nvidia,ahub-cif-ids = <4 4>; | 203 | nvidia,ahub-cif-ids = <4 4>; |
| 204 | status = "disable"; | 204 | status = "disabled"; |
| 205 | }; | 205 | }; |
| 206 | 206 | ||
| 207 | tegra_i2s1: i2s@70080400 { | 207 | tegra_i2s1: i2s@70080400 { |
| 208 | compatible = "nvidia,tegra30-i2s"; | 208 | compatible = "nvidia,tegra30-i2s"; |
| 209 | reg = <0x70080400 0x100>; | 209 | reg = <0x70080400 0x100>; |
| 210 | nvidia,ahub-cif-ids = <5 5>; | 210 | nvidia,ahub-cif-ids = <5 5>; |
| 211 | status = "disable"; | 211 | status = "disabled"; |
| 212 | }; | 212 | }; |
| 213 | 213 | ||
| 214 | tegra_i2s2: i2s@70080500 { | 214 | tegra_i2s2: i2s@70080500 { |
| 215 | compatible = "nvidia,tegra30-i2s"; | 215 | compatible = "nvidia,tegra30-i2s"; |
| 216 | reg = <0x70080500 0x100>; | 216 | reg = <0x70080500 0x100>; |
| 217 | nvidia,ahub-cif-ids = <6 6>; | 217 | nvidia,ahub-cif-ids = <6 6>; |
| 218 | status = "disable"; | 218 | status = "disabled"; |
| 219 | }; | 219 | }; |
| 220 | 220 | ||
| 221 | tegra_i2s3: i2s@70080600 { | 221 | tegra_i2s3: i2s@70080600 { |
| 222 | compatible = "nvidia,tegra30-i2s"; | 222 | compatible = "nvidia,tegra30-i2s"; |
| 223 | reg = <0x70080600 0x100>; | 223 | reg = <0x70080600 0x100>; |
| 224 | nvidia,ahub-cif-ids = <7 7>; | 224 | nvidia,ahub-cif-ids = <7 7>; |
| 225 | status = "disable"; | 225 | status = "disabled"; |
| 226 | }; | 226 | }; |
| 227 | 227 | ||
| 228 | tegra_i2s4: i2s@70080700 { | 228 | tegra_i2s4: i2s@70080700 { |
| 229 | compatible = "nvidia,tegra30-i2s"; | 229 | compatible = "nvidia,tegra30-i2s"; |
| 230 | reg = <0x70080700 0x100>; | 230 | reg = <0x70080700 0x100>; |
| 231 | nvidia,ahub-cif-ids = <8 8>; | 231 | nvidia,ahub-cif-ids = <8 8>; |
| 232 | status = "disable"; | 232 | status = "disabled"; |
| 233 | }; | 233 | }; |
| 234 | }; | 234 | }; |
| 235 | 235 | ||
| @@ -237,28 +237,28 @@ | |||
| 237 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | 237 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 238 | reg = <0x78000000 0x200>; | 238 | reg = <0x78000000 0x200>; |
| 239 | interrupts = <0 14 0x04>; | 239 | interrupts = <0 14 0x04>; |
| 240 | status = "disable"; | 240 | status = "disabled"; |
| 241 | }; | 241 | }; |
| 242 | 242 | ||
| 243 | sdhci@78000200 { | 243 | sdhci@78000200 { |
| 244 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | 244 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 245 | reg = <0x78000200 0x200>; | 245 | reg = <0x78000200 0x200>; |
| 246 | interrupts = <0 15 0x04>; | 246 | interrupts = <0 15 0x04>; |
| 247 | status = "disable"; | 247 | status = "disabled"; |
| 248 | }; | 248 | }; |
| 249 | 249 | ||
| 250 | sdhci@78000400 { | 250 | sdhci@78000400 { |
| 251 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | 251 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 252 | reg = <0x78000400 0x200>; | 252 | reg = <0x78000400 0x200>; |
| 253 | interrupts = <0 19 0x04>; | 253 | interrupts = <0 19 0x04>; |
| 254 | status = "disable"; | 254 | status = "disabled"; |
| 255 | }; | 255 | }; |
| 256 | 256 | ||
| 257 | sdhci@78000600 { | 257 | sdhci@78000600 { |
| 258 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | 258 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 259 | reg = <0x78000600 0x200>; | 259 | reg = <0x78000600 0x200>; |
| 260 | interrupts = <0 31 0x04>; | 260 | interrupts = <0 31 0x04>; |
| 261 | status = "disable"; | 261 | status = "disabled"; |
| 262 | }; | 262 | }; |
| 263 | 263 | ||
| 264 | pmu { | 264 | pmu { |
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi index 16076e2d0934..d8a827bd2bf3 100644 --- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | |||
| @@ -55,6 +55,8 @@ | |||
| 55 | reg-io-width = <4>; | 55 | reg-io-width = <4>; |
| 56 | smsc,irq-active-high; | 56 | smsc,irq-active-high; |
| 57 | smsc,irq-push-pull; | 57 | smsc,irq-push-pull; |
| 58 | vdd33a-supply = <&v2m_fixed_3v3>; | ||
| 59 | vddvario-supply = <&v2m_fixed_3v3>; | ||
| 58 | }; | 60 | }; |
| 59 | 61 | ||
| 60 | usb@2,03000000 { | 62 | usb@2,03000000 { |
| @@ -157,6 +159,7 @@ | |||
| 157 | v2m_timer23: timer@120000 { | 159 | v2m_timer23: timer@120000 { |
| 158 | compatible = "arm,sp804", "arm,primecell"; | 160 | compatible = "arm,sp804", "arm,primecell"; |
| 159 | reg = <0x120000 0x1000>; | 161 | reg = <0x120000 0x1000>; |
| 162 | interrupts = <3>; | ||
| 160 | }; | 163 | }; |
| 161 | 164 | ||
| 162 | /* DVI I2C bus */ | 165 | /* DVI I2C bus */ |
| @@ -197,5 +200,13 @@ | |||
| 197 | interrupts = <14>; | 200 | interrupts = <14>; |
| 198 | }; | 201 | }; |
| 199 | }; | 202 | }; |
| 203 | |||
| 204 | v2m_fixed_3v3: fixedregulator@0 { | ||
| 205 | compatible = "regulator-fixed"; | ||
| 206 | regulator-name = "3V3"; | ||
| 207 | regulator-min-microvolt = <3300000>; | ||
| 208 | regulator-max-microvolt = <3300000>; | ||
| 209 | regulator-always-on; | ||
| 210 | }; | ||
| 200 | }; | 211 | }; |
| 201 | }; | 212 | }; |
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi index a6c9c7c82d53..dba53fd026bb 100644 --- a/arch/arm/boot/dts/vexpress-v2m.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m.dtsi | |||
| @@ -54,6 +54,8 @@ | |||
| 54 | reg-io-width = <4>; | 54 | reg-io-width = <4>; |
| 55 | smsc,irq-active-high; | 55 | smsc,irq-active-high; |
| 56 | smsc,irq-push-pull; | 56 | smsc,irq-push-pull; |
| 57 | vdd33a-supply = <&v2m_fixed_3v3>; | ||
| 58 | vddvario-supply = <&v2m_fixed_3v3>; | ||
| 57 | }; | 59 | }; |
| 58 | 60 | ||
| 59 | usb@3,03000000 { | 61 | usb@3,03000000 { |
| @@ -156,6 +158,7 @@ | |||
| 156 | v2m_timer23: timer@12000 { | 158 | v2m_timer23: timer@12000 { |
| 157 | compatible = "arm,sp804", "arm,primecell"; | 159 | compatible = "arm,sp804", "arm,primecell"; |
| 158 | reg = <0x12000 0x1000>; | 160 | reg = <0x12000 0x1000>; |
| 161 | interrupts = <3>; | ||
| 159 | }; | 162 | }; |
| 160 | 163 | ||
| 161 | /* DVI I2C bus */ | 164 | /* DVI I2C bus */ |
| @@ -196,5 +199,13 @@ | |||
| 196 | interrupts = <14>; | 199 | interrupts = <14>; |
| 197 | }; | 200 | }; |
| 198 | }; | 201 | }; |
| 202 | |||
| 203 | v2m_fixed_3v3: fixedregulator@0 { | ||
| 204 | compatible = "regulator-fixed"; | ||
| 205 | regulator-name = "3V3"; | ||
| 206 | regulator-min-microvolt = <3300000>; | ||
| 207 | regulator-max-microvolt = <3300000>; | ||
| 208 | regulator-always-on; | ||
| 209 | }; | ||
| 199 | }; | 210 | }; |
| 200 | }; | 211 | }; |
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts index 7e1091d91af8..d12b34ca0568 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts | |||
| @@ -14,8 +14,8 @@ | |||
| 14 | arm,hbi = <0x237>; | 14 | arm,hbi = <0x237>; |
| 15 | compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress"; | 15 | compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress"; |
| 16 | interrupt-parent = <&gic>; | 16 | interrupt-parent = <&gic>; |
| 17 | #address-cells = <1>; | 17 | #address-cells = <2>; |
| 18 | #size-cells = <1>; | 18 | #size-cells = <2>; |
| 19 | 19 | ||
| 20 | chosen { }; | 20 | chosen { }; |
| 21 | 21 | ||
| @@ -47,23 +47,23 @@ | |||
| 47 | 47 | ||
| 48 | memory@80000000 { | 48 | memory@80000000 { |
| 49 | device_type = "memory"; | 49 | device_type = "memory"; |
| 50 | reg = <0x80000000 0x40000000>; | 50 | reg = <0 0x80000000 0 0x40000000>; |
| 51 | }; | 51 | }; |
| 52 | 52 | ||
| 53 | hdlcd@2b000000 { | 53 | hdlcd@2b000000 { |
| 54 | compatible = "arm,hdlcd"; | 54 | compatible = "arm,hdlcd"; |
| 55 | reg = <0x2b000000 0x1000>; | 55 | reg = <0 0x2b000000 0 0x1000>; |
| 56 | interrupts = <0 85 4>; | 56 | interrupts = <0 85 4>; |
| 57 | }; | 57 | }; |
| 58 | 58 | ||
| 59 | memory-controller@2b0a0000 { | 59 | memory-controller@2b0a0000 { |
| 60 | compatible = "arm,pl341", "arm,primecell"; | 60 | compatible = "arm,pl341", "arm,primecell"; |
| 61 | reg = <0x2b0a0000 0x1000>; | 61 | reg = <0 0x2b0a0000 0 0x1000>; |
| 62 | }; | 62 | }; |
| 63 | 63 | ||
| 64 | wdt@2b060000 { | 64 | wdt@2b060000 { |
| 65 | compatible = "arm,sp805", "arm,primecell"; | 65 | compatible = "arm,sp805", "arm,primecell"; |
| 66 | reg = <0x2b060000 0x1000>; | 66 | reg = <0 0x2b060000 0 0x1000>; |
| 67 | interrupts = <98>; | 67 | interrupts = <98>; |
| 68 | }; | 68 | }; |
| 69 | 69 | ||
| @@ -72,23 +72,23 @@ | |||
| 72 | #interrupt-cells = <3>; | 72 | #interrupt-cells = <3>; |
| 73 | #address-cells = <0>; | 73 | #address-cells = <0>; |
| 74 | interrupt-controller; | 74 | interrupt-controller; |
| 75 | reg = <0x2c001000 0x1000>, | 75 | reg = <0 0x2c001000 0 0x1000>, |
| 76 | <0x2c002000 0x1000>, | 76 | <0 0x2c002000 0 0x1000>, |
| 77 | <0x2c004000 0x2000>, | 77 | <0 0x2c004000 0 0x2000>, |
| 78 | <0x2c006000 0x2000>; | 78 | <0 0x2c006000 0 0x2000>; |
| 79 | interrupts = <1 9 0xf04>; | 79 | interrupts = <1 9 0xf04>; |
| 80 | }; | 80 | }; |
| 81 | 81 | ||
| 82 | memory-controller@7ffd0000 { | 82 | memory-controller@7ffd0000 { |
| 83 | compatible = "arm,pl354", "arm,primecell"; | 83 | compatible = "arm,pl354", "arm,primecell"; |
| 84 | reg = <0x7ffd0000 0x1000>; | 84 | reg = <0 0x7ffd0000 0 0x1000>; |
| 85 | interrupts = <0 86 4>, | 85 | interrupts = <0 86 4>, |
| 86 | <0 87 4>; | 86 | <0 87 4>; |
| 87 | }; | 87 | }; |
| 88 | 88 | ||
| 89 | dma@7ffb0000 { | 89 | dma@7ffb0000 { |
| 90 | compatible = "arm,pl330", "arm,primecell"; | 90 | compatible = "arm,pl330", "arm,primecell"; |
| 91 | reg = <0x7ffb0000 0x1000>; | 91 | reg = <0 0x7ffb0000 0 0x1000>; |
| 92 | interrupts = <0 92 4>, | 92 | interrupts = <0 92 4>, |
| 93 | <0 88 4>, | 93 | <0 88 4>, |
| 94 | <0 89 4>, | 94 | <0 89 4>, |
| @@ -111,12 +111,12 @@ | |||
| 111 | }; | 111 | }; |
| 112 | 112 | ||
| 113 | motherboard { | 113 | motherboard { |
| 114 | ranges = <0 0 0x08000000 0x04000000>, | 114 | ranges = <0 0 0 0x08000000 0x04000000>, |
| 115 | <1 0 0x14000000 0x04000000>, | 115 | <1 0 0 0x14000000 0x04000000>, |
| 116 | <2 0 0x18000000 0x04000000>, | 116 | <2 0 0 0x18000000 0x04000000>, |
| 117 | <3 0 0x1c000000 0x04000000>, | 117 | <3 0 0 0x1c000000 0x04000000>, |
| 118 | <4 0 0x0c000000 0x04000000>, | 118 | <4 0 0 0x0c000000 0x04000000>, |
| 119 | <5 0 0x10000000 0x04000000>; | 119 | <5 0 0 0x10000000 0x04000000>; |
| 120 | 120 | ||
| 121 | interrupt-map-mask = <0 0 63>; | 121 | interrupt-map-mask = <0 0 63>; |
| 122 | interrupt-map = <0 0 0 &gic 0 0 4>, | 122 | interrupt-map = <0 0 0 &gic 0 0 4>, |
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts new file mode 100644 index 000000000000..4890a81c5467 --- /dev/null +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | |||
| @@ -0,0 +1,188 @@ | |||
| 1 | /* | ||
| 2 | * ARM Ltd. Versatile Express | ||
| 3 | * | ||
| 4 | * CoreTile Express A15x2 A7x3 | ||
| 5 | * Cortex-A15_A7 MPCore (V2P-CA15_A7) | ||
| 6 | * | ||
| 7 | * HBI-0249A | ||
| 8 | */ | ||
| 9 | |||
| 10 | /dts-v1/; | ||
| 11 | |||
| 12 | / { | ||
| 13 | model = "V2P-CA15_CA7"; | ||
| 14 | arm,hbi = <0x249>; | ||
| 15 | compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress"; | ||
| 16 | interrupt-parent = <&gic>; | ||
| 17 | #address-cells = <2>; | ||
| 18 | #size-cells = <2>; | ||
| 19 | |||
| 20 | chosen { }; | ||
| 21 | |||
| 22 | aliases { | ||
| 23 | serial0 = &v2m_serial0; | ||
| 24 | serial1 = &v2m_serial1; | ||
| 25 | serial2 = &v2m_serial2; | ||
| 26 | serial3 = &v2m_serial3; | ||
| 27 | i2c0 = &v2m_i2c_dvi; | ||
| 28 | i2c1 = &v2m_i2c_pcie; | ||
| 29 | }; | ||
| 30 | |||
| 31 | cpus { | ||
| 32 | #address-cells = <1>; | ||
| 33 | #size-cells = <0>; | ||
| 34 | |||
| 35 | cpu0: cpu@0 { | ||
| 36 | device_type = "cpu"; | ||
| 37 | compatible = "arm,cortex-a15"; | ||
| 38 | reg = <0>; | ||
| 39 | }; | ||
| 40 | |||
| 41 | cpu1: cpu@1 { | ||
| 42 | device_type = "cpu"; | ||
| 43 | compatible = "arm,cortex-a15"; | ||
| 44 | reg = <1>; | ||
| 45 | }; | ||
| 46 | |||
| 47 | /* A7s disabled till big.LITTLE patches are available... | ||
| 48 | cpu2: cpu@2 { | ||
| 49 | device_type = "cpu"; | ||
| 50 | compatible = "arm,cortex-a7"; | ||
| 51 | reg = <0x100>; | ||
| 52 | }; | ||
| 53 | |||
| 54 | cpu3: cpu@3 { | ||
| 55 | device_type = "cpu"; | ||
| 56 | compatible = "arm,cortex-a7"; | ||
| 57 | reg = <0x101>; | ||
| 58 | }; | ||
| 59 | |||
| 60 | cpu4: cpu@4 { | ||
| 61 | device_type = "cpu"; | ||
| 62 | compatible = "arm,cortex-a7"; | ||
| 63 | reg = <0x102>; | ||
| 64 | }; | ||
| 65 | */ | ||
| 66 | }; | ||
| 67 | |||
| 68 | memory@80000000 { | ||
| 69 | device_type = "memory"; | ||
| 70 | reg = <0 0x80000000 0 0x40000000>; | ||
| 71 | }; | ||
| 72 | |||
| 73 | wdt@2a490000 { | ||
| 74 | compatible = "arm,sp805", "arm,primecell"; | ||
| 75 | reg = <0 0x2a490000 0 0x1000>; | ||
| 76 | interrupts = <98>; | ||
| 77 | }; | ||
| 78 | |||
| 79 | hdlcd@2b000000 { | ||
| 80 | compatible = "arm,hdlcd"; | ||
| 81 | reg = <0 0x2b000000 0 0x1000>; | ||
| 82 | interrupts = <0 85 4>; | ||
| 83 | }; | ||
| 84 | |||
| 85 | memory-controller@2b0a0000 { | ||
| 86 | compatible = "arm,pl341", "arm,primecell"; | ||
| 87 | reg = <0 0x2b0a0000 0 0x1000>; | ||
| 88 | }; | ||
| 89 | |||
| 90 | gic: interrupt-controller@2c001000 { | ||
| 91 | compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; | ||
| 92 | #interrupt-cells = <3>; | ||
| 93 | #address-cells = <0>; | ||
| 94 | interrupt-controller; | ||
| 95 | reg = <0 0x2c001000 0 0x1000>, | ||
| 96 | <0 0x2c002000 0 0x1000>, | ||
| 97 | <0 0x2c004000 0 0x2000>, | ||
| 98 | <0 0x2c006000 0 0x2000>; | ||
| 99 | interrupts = <1 9 0xf04>; | ||
| 100 | }; | ||
| 101 | |||
| 102 | memory-controller@7ffd0000 { | ||
| 103 | compatible = "arm,pl354", "arm,primecell"; | ||
| 104 | reg = <0 0x7ffd0000 0 0x1000>; | ||
| 105 | interrupts = <0 86 4>, | ||
| 106 | <0 87 4>; | ||
| 107 | }; | ||
| 108 | |||
| 109 | dma@7ff00000 { | ||
| 110 | compatible = "arm,pl330", "arm,primecell"; | ||
| 111 | reg = <0 0x7ff00000 0 0x1000>; | ||
| 112 | interrupts = <0 92 4>, | ||
| 113 | <0 88 4>, | ||
| 114 | <0 89 4>, | ||
| 115 | <0 90 4>, | ||
| 116 | <0 91 4>; | ||
| 117 | }; | ||
| 118 | |||
| 119 | timer { | ||
| 120 | compatible = "arm,armv7-timer"; | ||
| 121 | interrupts = <1 13 0xf08>, | ||
| 122 | <1 14 0xf08>, | ||
| 123 | <1 11 0xf08>, | ||
| 124 | <1 10 0xf08>; | ||
| 125 | }; | ||
| 126 | |||
| 127 | pmu { | ||
| 128 | compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu"; | ||
| 129 | interrupts = <0 68 4>, | ||
| 130 | <0 69 4>; | ||
| 131 | }; | ||
| 132 | |||
| 133 | motherboard { | ||
| 134 | ranges = <0 0 0 0x08000000 0x04000000>, | ||
| 135 | <1 0 0 0x14000000 0x04000000>, | ||
| 136 | <2 0 0 0x18000000 0x04000000>, | ||
| 137 | <3 0 0 0x1c000000 0x04000000>, | ||
| 138 | <4 0 0 0x0c000000 0x04000000>, | ||
| 139 | <5 0 0 0x10000000 0x04000000>; | ||
| 140 | |||
| 141 | interrupt-map-mask = <0 0 63>; | ||
| 142 | interrupt-map = <0 0 0 &gic 0 0 4>, | ||
| 143 | <0 0 1 &gic 0 1 4>, | ||
| 144 | <0 0 2 &gic 0 2 4>, | ||
| 145 | <0 0 3 &gic 0 3 4>, | ||
| 146 | <0 0 4 &gic 0 4 4>, | ||
| 147 | <0 0 5 &gic 0 5 4>, | ||
| 148 | <0 0 6 &gic 0 6 4>, | ||
| 149 | <0 0 7 &gic 0 7 4>, | ||
| 150 | <0 0 8 &gic 0 8 4>, | ||
| 151 | <0 0 9 &gic 0 9 4>, | ||
| 152 | <0 0 10 &gic 0 10 4>, | ||
| 153 | <0 0 11 &gic 0 11 4>, | ||
| 154 | <0 0 12 &gic 0 12 4>, | ||
| 155 | <0 0 13 &gic 0 13 4>, | ||
| 156 | <0 0 14 &gic 0 14 4>, | ||
| 157 | <0 0 15 &gic 0 15 4>, | ||
| 158 | <0 0 16 &gic 0 16 4>, | ||
| 159 | <0 0 17 &gic 0 17 4>, | ||
| 160 | <0 0 18 &gic 0 18 4>, | ||
| 161 | <0 0 19 &gic 0 19 4>, | ||
| 162 | <0 0 20 &gic 0 20 4>, | ||
| 163 | <0 0 21 &gic 0 21 4>, | ||
| 164 | <0 0 22 &gic 0 22 4>, | ||
| 165 | <0 0 23 &gic 0 23 4>, | ||
| 166 | <0 0 24 &gic 0 24 4>, | ||
| 167 | <0 0 25 &gic 0 25 4>, | ||
| 168 | <0 0 26 &gic 0 26 4>, | ||
| 169 | <0 0 27 &gic 0 27 4>, | ||
| 170 | <0 0 28 &gic 0 28 4>, | ||
| 171 | <0 0 29 &gic 0 29 4>, | ||
| 172 | <0 0 30 &gic 0 30 4>, | ||
| 173 | <0 0 31 &gic 0 31 4>, | ||
| 174 | <0 0 32 &gic 0 32 4>, | ||
| 175 | <0 0 33 &gic 0 33 4>, | ||
| 176 | <0 0 34 &gic 0 34 4>, | ||
| 177 | <0 0 35 &gic 0 35 4>, | ||
| 178 | <0 0 36 &gic 0 36 4>, | ||
| 179 | <0 0 37 &gic 0 37 4>, | ||
| 180 | <0 0 38 &gic 0 38 4>, | ||
| 181 | <0 0 39 &gic 0 39 4>, | ||
| 182 | <0 0 40 &gic 0 40 4>, | ||
| 183 | <0 0 41 &gic 0 41 4>, | ||
| 184 | <0 0 42 &gic 0 42 4>; | ||
| 185 | }; | ||
| 186 | }; | ||
| 187 | |||
| 188 | /include/ "vexpress-v2m-rs1.dtsi" | ||
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 9854ff4279e0..d3c29b377af9 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig | |||
| @@ -176,7 +176,6 @@ CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | |||
| 176 | CONFIG_USB_DEVICEFS=y | 176 | CONFIG_USB_DEVICEFS=y |
| 177 | CONFIG_USB_SUSPEND=y | 177 | CONFIG_USB_SUSPEND=y |
| 178 | CONFIG_USB_MON=y | 178 | CONFIG_USB_MON=y |
| 179 | CONFIG_USB_EHCI_HCD=y | ||
| 180 | CONFIG_USB_WDM=y | 179 | CONFIG_USB_WDM=y |
| 181 | CONFIG_USB_STORAGE=y | 180 | CONFIG_USB_STORAGE=y |
| 182 | CONFIG_USB_LIBUSUAL=y | 181 | CONFIG_USB_LIBUSUAL=y |
| @@ -197,6 +196,7 @@ CONFIG_RTC_DRV_TWL4030=y | |||
| 197 | CONFIG_EXT2_FS=y | 196 | CONFIG_EXT2_FS=y |
| 198 | CONFIG_EXT3_FS=y | 197 | CONFIG_EXT3_FS=y |
| 199 | # CONFIG_EXT3_FS_XATTR is not set | 198 | # CONFIG_EXT3_FS_XATTR is not set |
| 199 | CONFIG_EXT4_FS=y | ||
| 200 | CONFIG_QUOTA=y | 200 | CONFIG_QUOTA=y |
| 201 | CONFIG_QFMT_V2=y | 201 | CONFIG_QFMT_V2=y |
| 202 | CONFIG_MSDOS_FS=y | 202 | CONFIG_MSDOS_FS=y |
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 8349d4e97e2b..16cedb42c0c3 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c | |||
| @@ -40,13 +40,6 @@ | |||
| 40 | #include <asm/mach/irq.h> | 40 | #include <asm/mach/irq.h> |
| 41 | #include <asm/mach/time.h> | 41 | #include <asm/mach/time.h> |
| 42 | 42 | ||
| 43 | /* | ||
| 44 | * No architecture-specific irq_finish function defined in arm/arch/irqs.h. | ||
| 45 | */ | ||
| 46 | #ifndef irq_finish | ||
| 47 | #define irq_finish(irq) do { } while (0) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | unsigned long irq_err_count; | 43 | unsigned long irq_err_count; |
| 51 | 44 | ||
| 52 | int arch_show_interrupts(struct seq_file *p, int prec) | 45 | int arch_show_interrupts(struct seq_file *p, int prec) |
| @@ -85,9 +78,6 @@ void handle_IRQ(unsigned int irq, struct pt_regs *regs) | |||
| 85 | generic_handle_irq(irq); | 78 | generic_handle_irq(irq); |
| 86 | } | 79 | } |
| 87 | 80 | ||
| 88 | /* AT91 specific workaround */ | ||
| 89 | irq_finish(irq); | ||
| 90 | |||
| 91 | irq_exit(); | 81 | irq_exit(); |
| 92 | set_irq_regs(old_regs); | 82 | set_irq_regs(old_regs); |
| 93 | } | 83 | } |
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 19505c0a3f01..c8050b14e615 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig | |||
| @@ -29,12 +29,16 @@ comment "Atmel AT91 Processor" | |||
| 29 | config SOC_AT91SAM9 | 29 | config SOC_AT91SAM9 |
| 30 | bool | 30 | bool |
| 31 | select CPU_ARM926T | 31 | select CPU_ARM926T |
| 32 | select MULTI_IRQ_HANDLER | ||
| 33 | select SPARSE_IRQ | ||
| 32 | select AT91_SAM9_TIME | 34 | select AT91_SAM9_TIME |
| 33 | select AT91_SAM9_SMC | 35 | select AT91_SAM9_SMC |
| 34 | 36 | ||
| 35 | config SOC_AT91RM9200 | 37 | config SOC_AT91RM9200 |
| 36 | bool "AT91RM9200" | 38 | bool "AT91RM9200" |
| 37 | select CPU_ARM920T | 39 | select CPU_ARM920T |
| 40 | select MULTI_IRQ_HANDLER | ||
| 41 | select SPARSE_IRQ | ||
| 38 | select GENERIC_CLOCKEVENTS | 42 | select GENERIC_CLOCKEVENTS |
| 39 | select HAVE_AT91_DBGU0 | 43 | select HAVE_AT91_DBGU0 |
| 40 | 44 | ||
| @@ -140,6 +144,8 @@ config ARCH_AT91SAM9G45 | |||
| 140 | config ARCH_AT91X40 | 144 | config ARCH_AT91X40 |
| 141 | bool "AT91x40" | 145 | bool "AT91x40" |
| 142 | depends on !MMU | 146 | depends on !MMU |
| 147 | select MULTI_IRQ_HANDLER | ||
| 148 | select SPARSE_IRQ | ||
| 143 | select ARCH_USES_GETTIMEOFFSET | 149 | select ARCH_USES_GETTIMEOFFSET |
| 144 | 150 | ||
| 145 | endchoice | 151 | endchoice |
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c index 26917687fc30..6f50c6722276 100644 --- a/arch/arm/mach-at91/at91rm9200.c +++ b/arch/arm/mach-at91/at91rm9200.c | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | #include <asm/mach/map.h> | 17 | #include <asm/mach/map.h> |
| 18 | #include <asm/system_misc.h> | 18 | #include <asm/system_misc.h> |
| 19 | #include <mach/at91rm9200.h> | 19 | #include <mach/at91rm9200.h> |
| 20 | #include <mach/at91_aic.h> | ||
| 20 | #include <mach/at91_pmc.h> | 21 | #include <mach/at91_pmc.h> |
| 21 | #include <mach/at91_st.h> | 22 | #include <mach/at91_st.h> |
| 22 | #include <mach/cpu.h> | 23 | #include <mach/cpu.h> |
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c index e6b7d0533dd7..01fb7325fecc 100644 --- a/arch/arm/mach-at91/at91rm9200_devices.c +++ b/arch/arm/mach-at91/at91rm9200_devices.c | |||
| @@ -41,8 +41,8 @@ static struct resource usbh_resources[] = { | |||
| 41 | .flags = IORESOURCE_MEM, | 41 | .flags = IORESOURCE_MEM, |
| 42 | }, | 42 | }, |
| 43 | [1] = { | 43 | [1] = { |
| 44 | .start = AT91RM9200_ID_UHP, | 44 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_UHP, |
| 45 | .end = AT91RM9200_ID_UHP, | 45 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_UHP, |
| 46 | .flags = IORESOURCE_IRQ, | 46 | .flags = IORESOURCE_IRQ, |
| 47 | }, | 47 | }, |
| 48 | }; | 48 | }; |
| @@ -94,8 +94,8 @@ static struct resource udc_resources[] = { | |||
| 94 | .flags = IORESOURCE_MEM, | 94 | .flags = IORESOURCE_MEM, |
| 95 | }, | 95 | }, |
| 96 | [1] = { | 96 | [1] = { |
| 97 | .start = AT91RM9200_ID_UDP, | 97 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_UDP, |
| 98 | .end = AT91RM9200_ID_UDP, | 98 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_UDP, |
| 99 | .flags = IORESOURCE_IRQ, | 99 | .flags = IORESOURCE_IRQ, |
| 100 | }, | 100 | }, |
| 101 | }; | 101 | }; |
| @@ -145,8 +145,8 @@ static struct resource eth_resources[] = { | |||
| 145 | .flags = IORESOURCE_MEM, | 145 | .flags = IORESOURCE_MEM, |
| 146 | }, | 146 | }, |
| 147 | [1] = { | 147 | [1] = { |
| 148 | .start = AT91RM9200_ID_EMAC, | 148 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_EMAC, |
| 149 | .end = AT91RM9200_ID_EMAC, | 149 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_EMAC, |
| 150 | .flags = IORESOURCE_IRQ, | 150 | .flags = IORESOURCE_IRQ, |
| 151 | }, | 151 | }, |
| 152 | }; | 152 | }; |
| @@ -305,8 +305,8 @@ static struct resource mmc_resources[] = { | |||
| 305 | .flags = IORESOURCE_MEM, | 305 | .flags = IORESOURCE_MEM, |
| 306 | }, | 306 | }, |
| 307 | [1] = { | 307 | [1] = { |
| 308 | .start = AT91RM9200_ID_MCI, | 308 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_MCI, |
| 309 | .end = AT91RM9200_ID_MCI, | 309 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_MCI, |
| 310 | .flags = IORESOURCE_IRQ, | 310 | .flags = IORESOURCE_IRQ, |
| 311 | }, | 311 | }, |
| 312 | }; | 312 | }; |
| @@ -488,8 +488,8 @@ static struct resource twi_resources[] = { | |||
| 488 | .flags = IORESOURCE_MEM, | 488 | .flags = IORESOURCE_MEM, |
| 489 | }, | 489 | }, |
| 490 | [1] = { | 490 | [1] = { |
| 491 | .start = AT91RM9200_ID_TWI, | 491 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_TWI, |
| 492 | .end = AT91RM9200_ID_TWI, | 492 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_TWI, |
| 493 | .flags = IORESOURCE_IRQ, | 493 | .flags = IORESOURCE_IRQ, |
| 494 | }, | 494 | }, |
| 495 | }; | 495 | }; |
| @@ -532,8 +532,8 @@ static struct resource spi_resources[] = { | |||
| 532 | .flags = IORESOURCE_MEM, | 532 | .flags = IORESOURCE_MEM, |
| 533 | }, | 533 | }, |
| 534 | [1] = { | 534 | [1] = { |
| 535 | .start = AT91RM9200_ID_SPI, | 535 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_SPI, |
| 536 | .end = AT91RM9200_ID_SPI, | 536 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_SPI, |
| 537 | .flags = IORESOURCE_IRQ, | 537 | .flags = IORESOURCE_IRQ, |
| 538 | }, | 538 | }, |
| 539 | }; | 539 | }; |
| @@ -598,18 +598,18 @@ static struct resource tcb0_resources[] = { | |||
| 598 | .flags = IORESOURCE_MEM, | 598 | .flags = IORESOURCE_MEM, |
| 599 | }, | 599 | }, |
| 600 | [1] = { | 600 | [1] = { |
| 601 | .start = AT91RM9200_ID_TC0, | 601 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC0, |
| 602 | .end = AT91RM9200_ID_TC0, | 602 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC0, |
| 603 | .flags = IORESOURCE_IRQ, | 603 | .flags = IORESOURCE_IRQ, |
| 604 | }, | 604 | }, |
| 605 | [2] = { | 605 | [2] = { |
| 606 | .start = AT91RM9200_ID_TC1, | 606 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC1, |
| 607 | .end = AT91RM9200_ID_TC1, | 607 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC1, |
| 608 | .flags = IORESOURCE_IRQ, | 608 | .flags = IORESOURCE_IRQ, |
| 609 | }, | 609 | }, |
| 610 | [3] = { | 610 | [3] = { |
| 611 | .start = AT91RM9200_ID_TC2, | 611 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC2, |
| 612 | .end = AT91RM9200_ID_TC2, | 612 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC2, |
| 613 | .flags = IORESOURCE_IRQ, | 613 | .flags = IORESOURCE_IRQ, |
| 614 | }, | 614 | }, |
| 615 | }; | 615 | }; |
| @@ -628,18 +628,18 @@ static struct resource tcb1_resources[] = { | |||
| 628 | .flags = IORESOURCE_MEM, | 628 | .flags = IORESOURCE_MEM, |
| 629 | }, | 629 | }, |
| 630 | [1] = { | 630 | [1] = { |
| 631 | .start = AT91RM9200_ID_TC3, | 631 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC3, |
| 632 | .end = AT91RM9200_ID_TC3, | 632 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC3, |
| 633 | .flags = IORESOURCE_IRQ, | 633 | .flags = IORESOURCE_IRQ, |
| 634 | }, | 634 | }, |
| 635 | [2] = { | 635 | [2] = { |
| 636 | .start = AT91RM9200_ID_TC4, | 636 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC4, |
| 637 | .end = AT91RM9200_ID_TC4, | 637 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC4, |
| 638 | .flags = IORESOURCE_IRQ, | 638 | .flags = IORESOURCE_IRQ, |
| 639 | }, | 639 | }, |
| 640 | [3] = { | 640 | [3] = { |
| 641 | .start = AT91RM9200_ID_TC5, | 641 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC5, |
| 642 | .end = AT91RM9200_ID_TC5, | 642 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC5, |
| 643 | .flags = IORESOURCE_IRQ, | 643 | .flags = IORESOURCE_IRQ, |
| 644 | }, | 644 | }, |
| 645 | }; | 645 | }; |
| @@ -673,8 +673,8 @@ static struct resource rtc_resources[] = { | |||
| 673 | .flags = IORESOURCE_MEM, | 673 | .flags = IORESOURCE_MEM, |
| 674 | }, | 674 | }, |
| 675 | [1] = { | 675 | [1] = { |
| 676 | .start = AT91_ID_SYS, | 676 | .start = NR_IRQS_LEGACY + AT91_ID_SYS, |
| 677 | .end = AT91_ID_SYS, | 677 | .end = NR_IRQS_LEGACY + AT91_ID_SYS, |
| 678 | .flags = IORESOURCE_IRQ, | 678 | .flags = IORESOURCE_IRQ, |
| 679 | }, | 679 | }, |
| 680 | }; | 680 | }; |
| @@ -729,8 +729,8 @@ static struct resource ssc0_resources[] = { | |||
| 729 | .flags = IORESOURCE_MEM, | 729 | .flags = IORESOURCE_MEM, |
| 730 | }, | 730 | }, |
| 731 | [1] = { | 731 | [1] = { |
| 732 | .start = AT91RM9200_ID_SSC0, | 732 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_SSC0, |
| 733 | .end = AT91RM9200_ID_SSC0, | 733 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_SSC0, |
| 734 | .flags = IORESOURCE_IRQ, | 734 | .flags = IORESOURCE_IRQ, |
| 735 | }, | 735 | }, |
| 736 | }; | 736 | }; |
| @@ -771,8 +771,8 @@ static struct resource ssc1_resources[] = { | |||
| 771 | .flags = IORESOURCE_MEM, | 771 | .flags = IORESOURCE_MEM, |
| 772 | }, | 772 | }, |
| 773 | [1] = { | 773 | [1] = { |
| 774 | .start = AT91RM9200_ID_SSC1, | 774 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_SSC1, |
| 775 | .end = AT91RM9200_ID_SSC1, | 775 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_SSC1, |
| 776 | .flags = IORESOURCE_IRQ, | 776 | .flags = IORESOURCE_IRQ, |
| 777 | }, | 777 | }, |
| 778 | }; | 778 | }; |
| @@ -813,8 +813,8 @@ static struct resource ssc2_resources[] = { | |||
| 813 | .flags = IORESOURCE_MEM, | 813 | .flags = IORESOURCE_MEM, |
| 814 | }, | 814 | }, |
| 815 | [1] = { | 815 | [1] = { |
| 816 | .start = AT91RM9200_ID_SSC2, | 816 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_SSC2, |
| 817 | .end = AT91RM9200_ID_SSC2, | 817 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_SSC2, |
| 818 | .flags = IORESOURCE_IRQ, | 818 | .flags = IORESOURCE_IRQ, |
| 819 | }, | 819 | }, |
| 820 | }; | 820 | }; |
| @@ -897,8 +897,8 @@ static struct resource dbgu_resources[] = { | |||
| 897 | .flags = IORESOURCE_MEM, | 897 | .flags = IORESOURCE_MEM, |
| 898 | }, | 898 | }, |
| 899 | [1] = { | 899 | [1] = { |
| 900 | .start = AT91_ID_SYS, | 900 | .start = NR_IRQS_LEGACY + AT91_ID_SYS, |
| 901 | .end = AT91_ID_SYS, | 901 | .end = NR_IRQS_LEGACY + AT91_ID_SYS, |
| 902 | .flags = IORESOURCE_IRQ, | 902 | .flags = IORESOURCE_IRQ, |
| 903 | }, | 903 | }, |
| 904 | }; | 904 | }; |
| @@ -935,8 +935,8 @@ static struct resource uart0_resources[] = { | |||
| 935 | .flags = IORESOURCE_MEM, | 935 | .flags = IORESOURCE_MEM, |
| 936 | }, | 936 | }, |
| 937 | [1] = { | 937 | [1] = { |
| 938 | .start = AT91RM9200_ID_US0, | 938 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_US0, |
| 939 | .end = AT91RM9200_ID_US0, | 939 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_US0, |
| 940 | .flags = IORESOURCE_IRQ, | 940 | .flags = IORESOURCE_IRQ, |
| 941 | }, | 941 | }, |
| 942 | }; | 942 | }; |
| @@ -984,8 +984,8 @@ static struct resource uart1_resources[] = { | |||
| 984 | .flags = IORESOURCE_MEM, | 984 | .flags = IORESOURCE_MEM, |
| 985 | }, | 985 | }, |
| 986 | [1] = { | 986 | [1] = { |
| 987 | .start = AT91RM9200_ID_US1, | 987 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_US1, |
| 988 | .end = AT91RM9200_ID_US1, | 988 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_US1, |
| 989 | .flags = IORESOURCE_IRQ, | 989 | .flags = IORESOURCE_IRQ, |
| 990 | }, | 990 | }, |
| 991 | }; | 991 | }; |
| @@ -1035,8 +1035,8 @@ static struct resource uart2_resources[] = { | |||
| 1035 | .flags = IORESOURCE_MEM, | 1035 | .flags = IORESOURCE_MEM, |
| 1036 | }, | 1036 | }, |
| 1037 | [1] = { | 1037 | [1] = { |
| 1038 | .start = AT91RM9200_ID_US2, | 1038 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_US2, |
| 1039 | .end = AT91RM9200_ID_US2, | 1039 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_US2, |
| 1040 | .flags = IORESOURCE_IRQ, | 1040 | .flags = IORESOURCE_IRQ, |
| 1041 | }, | 1041 | }, |
| 1042 | }; | 1042 | }; |
| @@ -1078,8 +1078,8 @@ static struct resource uart3_resources[] = { | |||
| 1078 | .flags = IORESOURCE_MEM, | 1078 | .flags = IORESOURCE_MEM, |
| 1079 | }, | 1079 | }, |
| 1080 | [1] = { | 1080 | [1] = { |
| 1081 | .start = AT91RM9200_ID_US3, | 1081 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_US3, |
| 1082 | .end = AT91RM9200_ID_US3, | 1082 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_US3, |
| 1083 | .flags = IORESOURCE_IRQ, | 1083 | .flags = IORESOURCE_IRQ, |
| 1084 | }, | 1084 | }, |
| 1085 | }; | 1085 | }; |
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c index 2b1e438ed878..30c7f26a4668 100644 --- a/arch/arm/mach-at91/at91sam9260.c +++ b/arch/arm/mach-at91/at91sam9260.c | |||
| @@ -20,6 +20,7 @@ | |||
| 20 | #include <mach/cpu.h> | 20 | #include <mach/cpu.h> |
| 21 | #include <mach/at91_dbgu.h> | 21 | #include <mach/at91_dbgu.h> |
| 22 | #include <mach/at91sam9260.h> | 22 | #include <mach/at91sam9260.h> |
| 23 | #include <mach/at91_aic.h> | ||
| 23 | #include <mach/at91_pmc.h> | 24 | #include <mach/at91_pmc.h> |
| 24 | #include <mach/at91_rstc.h> | 25 | #include <mach/at91_rstc.h> |
| 25 | 26 | ||
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c index 0ded951f785a..7b9c2ba396ed 100644 --- a/arch/arm/mach-at91/at91sam9260_devices.c +++ b/arch/arm/mach-at91/at91sam9260_devices.c | |||
| @@ -45,8 +45,8 @@ static struct resource usbh_resources[] = { | |||
| 45 | .flags = IORESOURCE_MEM, | 45 | .flags = IORESOURCE_MEM, |
| 46 | }, | 46 | }, |
| 47 | [1] = { | 47 | [1] = { |
| 48 | .start = AT91SAM9260_ID_UHP, | 48 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_UHP, |
| 49 | .end = AT91SAM9260_ID_UHP, | 49 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_UHP, |
| 50 | .flags = IORESOURCE_IRQ, | 50 | .flags = IORESOURCE_IRQ, |
| 51 | }, | 51 | }, |
| 52 | }; | 52 | }; |
| @@ -98,8 +98,8 @@ static struct resource udc_resources[] = { | |||
| 98 | .flags = IORESOURCE_MEM, | 98 | .flags = IORESOURCE_MEM, |
| 99 | }, | 99 | }, |
| 100 | [1] = { | 100 | [1] = { |
| 101 | .start = AT91SAM9260_ID_UDP, | 101 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_UDP, |
| 102 | .end = AT91SAM9260_ID_UDP, | 102 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_UDP, |
| 103 | .flags = IORESOURCE_IRQ, | 103 | .flags = IORESOURCE_IRQ, |
| 104 | }, | 104 | }, |
| 105 | }; | 105 | }; |
| @@ -149,8 +149,8 @@ static struct resource eth_resources[] = { | |||
| 149 | .flags = IORESOURCE_MEM, | 149 | .flags = IORESOURCE_MEM, |
| 150 | }, | 150 | }, |
| 151 | [1] = { | 151 | [1] = { |
| 152 | .start = AT91SAM9260_ID_EMAC, | 152 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_EMAC, |
| 153 | .end = AT91SAM9260_ID_EMAC, | 153 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_EMAC, |
| 154 | .flags = IORESOURCE_IRQ, | 154 | .flags = IORESOURCE_IRQ, |
| 155 | }, | 155 | }, |
| 156 | }; | 156 | }; |
| @@ -223,8 +223,8 @@ static struct resource mmc_resources[] = { | |||
| 223 | .flags = IORESOURCE_MEM, | 223 | .flags = IORESOURCE_MEM, |
| 224 | }, | 224 | }, |
| 225 | [1] = { | 225 | [1] = { |
| 226 | .start = AT91SAM9260_ID_MCI, | 226 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI, |
| 227 | .end = AT91SAM9260_ID_MCI, | 227 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI, |
| 228 | .flags = IORESOURCE_IRQ, | 228 | .flags = IORESOURCE_IRQ, |
| 229 | }, | 229 | }, |
| 230 | }; | 230 | }; |
| @@ -305,8 +305,8 @@ static struct resource mmc_resources[] = { | |||
| 305 | .flags = IORESOURCE_MEM, | 305 | .flags = IORESOURCE_MEM, |
| 306 | }, | 306 | }, |
| 307 | [1] = { | 307 | [1] = { |
| 308 | .start = AT91SAM9260_ID_MCI, | 308 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI, |
| 309 | .end = AT91SAM9260_ID_MCI, | 309 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI, |
| 310 | .flags = IORESOURCE_IRQ, | 310 | .flags = IORESOURCE_IRQ, |
| 311 | }, | 311 | }, |
| 312 | }; | 312 | }; |
| @@ -496,8 +496,8 @@ static struct resource twi_resources[] = { | |||
| 496 | .flags = IORESOURCE_MEM, | 496 | .flags = IORESOURCE_MEM, |
| 497 | }, | 497 | }, |
| 498 | [1] = { | 498 | [1] = { |
| 499 | .start = AT91SAM9260_ID_TWI, | 499 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TWI, |
| 500 | .end = AT91SAM9260_ID_TWI, | 500 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TWI, |
| 501 | .flags = IORESOURCE_IRQ, | 501 | .flags = IORESOURCE_IRQ, |
| 502 | }, | 502 | }, |
| 503 | }; | 503 | }; |
| @@ -540,8 +540,8 @@ static struct resource spi0_resources[] = { | |||
| 540 | .flags = IORESOURCE_MEM, | 540 | .flags = IORESOURCE_MEM, |
| 541 | }, | 541 | }, |
| 542 | [1] = { | 542 | [1] = { |
| 543 | .start = AT91SAM9260_ID_SPI0, | 543 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI0, |
| 544 | .end = AT91SAM9260_ID_SPI0, | 544 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI0, |
| 545 | .flags = IORESOURCE_IRQ, | 545 | .flags = IORESOURCE_IRQ, |
| 546 | }, | 546 | }, |
| 547 | }; | 547 | }; |
| @@ -566,8 +566,8 @@ static struct resource spi1_resources[] = { | |||
| 566 | .flags = IORESOURCE_MEM, | 566 | .flags = IORESOURCE_MEM, |
| 567 | }, | 567 | }, |
| 568 | [1] = { | 568 | [1] = { |
| 569 | .start = AT91SAM9260_ID_SPI1, | 569 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI1, |
| 570 | .end = AT91SAM9260_ID_SPI1, | 570 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI1, |
| 571 | .flags = IORESOURCE_IRQ, | 571 | .flags = IORESOURCE_IRQ, |
| 572 | }, | 572 | }, |
| 573 | }; | 573 | }; |
| @@ -652,18 +652,18 @@ static struct resource tcb0_resources[] = { | |||
| 652 | .flags = IORESOURCE_MEM, | 652 | .flags = IORESOURCE_MEM, |
| 653 | }, | 653 | }, |
| 654 | [1] = { | 654 | [1] = { |
| 655 | .start = AT91SAM9260_ID_TC0, | 655 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC0, |
| 656 | .end = AT91SAM9260_ID_TC0, | 656 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC0, |
| 657 | .flags = IORESOURCE_IRQ, | 657 | .flags = IORESOURCE_IRQ, |
| 658 | }, | 658 | }, |
| 659 | [2] = { | 659 | [2] = { |
| 660 | .start = AT91SAM9260_ID_TC1, | 660 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC1, |
| 661 | .end = AT91SAM9260_ID_TC1, | 661 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC1, |
| 662 | .flags = IORESOURCE_IRQ, | 662 | .flags = IORESOURCE_IRQ, |
| 663 | }, | 663 | }, |
| 664 | [3] = { | 664 | [3] = { |
| 665 | .start = AT91SAM9260_ID_TC2, | 665 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC2, |
| 666 | .end = AT91SAM9260_ID_TC2, | 666 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC2, |
| 667 | .flags = IORESOURCE_IRQ, | 667 | .flags = IORESOURCE_IRQ, |
| 668 | }, | 668 | }, |
| 669 | }; | 669 | }; |
| @@ -682,18 +682,18 @@ static struct resource tcb1_resources[] = { | |||
| 682 | .flags = IORESOURCE_MEM, | 682 | .flags = IORESOURCE_MEM, |
| 683 | }, | 683 | }, |
| 684 | [1] = { | 684 | [1] = { |
| 685 | .start = AT91SAM9260_ID_TC3, | 685 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC3, |
| 686 | .end = AT91SAM9260_ID_TC3, | 686 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC3, |
| 687 | .flags = IORESOURCE_IRQ, | 687 | .flags = IORESOURCE_IRQ, |
| 688 | }, | 688 | }, |
| 689 | [2] = { | 689 | [2] = { |
| 690 | .start = AT91SAM9260_ID_TC4, | 690 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC4, |
| 691 | .end = AT91SAM9260_ID_TC4, | 691 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC4, |
| 692 | .flags = IORESOURCE_IRQ, | 692 | .flags = IORESOURCE_IRQ, |
| 693 | }, | 693 | }, |
| 694 | [3] = { | 694 | [3] = { |
| 695 | .start = AT91SAM9260_ID_TC5, | 695 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC5, |
| 696 | .end = AT91SAM9260_ID_TC5, | 696 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC5, |
| 697 | .flags = IORESOURCE_IRQ, | 697 | .flags = IORESOURCE_IRQ, |
| 698 | }, | 698 | }, |
| 699 | }; | 699 | }; |
| @@ -807,8 +807,8 @@ static struct resource ssc_resources[] = { | |||
| 807 | .flags = IORESOURCE_MEM, | 807 | .flags = IORESOURCE_MEM, |
| 808 | }, | 808 | }, |
| 809 | [1] = { | 809 | [1] = { |
| 810 | .start = AT91SAM9260_ID_SSC, | 810 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_SSC, |
| 811 | .end = AT91SAM9260_ID_SSC, | 811 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_SSC, |
| 812 | .flags = IORESOURCE_IRQ, | 812 | .flags = IORESOURCE_IRQ, |
| 813 | }, | 813 | }, |
| 814 | }; | 814 | }; |
| @@ -882,8 +882,8 @@ static struct resource dbgu_resources[] = { | |||
| 882 | .flags = IORESOURCE_MEM, | 882 | .flags = IORESOURCE_MEM, |
| 883 | }, | 883 | }, |
| 884 | [1] = { | 884 | [1] = { |
| 885 | .start = AT91_ID_SYS, | 885 | .start = NR_IRQS_LEGACY + AT91_ID_SYS, |
| 886 | .end = AT91_ID_SYS, | 886 | .end = NR_IRQS_LEGACY + AT91_ID_SYS, |
| 887 | .flags = IORESOURCE_IRQ, | 887 | .flags = IORESOURCE_IRQ, |
| 888 | }, | 888 | }, |
| 889 | }; | 889 | }; |
| @@ -920,8 +920,8 @@ static struct resource uart0_resources[] = { | |||
| 920 | .flags = IORESOURCE_MEM, | 920 | .flags = IORESOURCE_MEM, |
| 921 | }, | 921 | }, |
| 922 | [1] = { | 922 | [1] = { |
| 923 | .start = AT91SAM9260_ID_US0, | 923 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US0, |
| 924 | .end = AT91SAM9260_ID_US0, | 924 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US0, |
| 925 | .flags = IORESOURCE_IRQ, | 925 | .flags = IORESOURCE_IRQ, |
| 926 | }, | 926 | }, |
| 927 | }; | 927 | }; |
| @@ -971,8 +971,8 @@ static struct resource uart1_resources[] = { | |||
| 971 | .flags = IORESOURCE_MEM, | 971 | .flags = IORESOURCE_MEM, |
| 972 | }, | 972 | }, |
| 973 | [1] = { | 973 | [1] = { |
| 974 | .start = AT91SAM9260_ID_US1, | 974 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US1, |
| 975 | .end = AT91SAM9260_ID_US1, | 975 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US1, |
| 976 | .flags = IORESOURCE_IRQ, | 976 | .flags = IORESOURCE_IRQ, |
| 977 | }, | 977 | }, |
| 978 | }; | 978 | }; |
| @@ -1014,8 +1014,8 @@ static struct resource uart2_resources[] = { | |||
| 1014 | .flags = IORESOURCE_MEM, | 1014 | .flags = IORESOURCE_MEM, |
| 1015 | }, | 1015 | }, |
| 1016 | [1] = { | 1016 | [1] = { |
| 1017 | .start = AT91SAM9260_ID_US2, | 1017 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US2, |
| 1018 | .end = AT91SAM9260_ID_US2, | 1018 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US2, |
| 1019 | .flags = IORESOURCE_IRQ, | 1019 | .flags = IORESOURCE_IRQ, |
| 1020 | }, | 1020 | }, |
| 1021 | }; | 1021 | }; |
| @@ -1057,8 +1057,8 @@ static struct resource uart3_resources[] = { | |||
| 1057 | .flags = IORESOURCE_MEM, | 1057 | .flags = IORESOURCE_MEM, |
| 1058 | }, | 1058 | }, |
| 1059 | [1] = { | 1059 | [1] = { |
| 1060 | .start = AT91SAM9260_ID_US3, | 1060 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US3, |
| 1061 | .end = AT91SAM9260_ID_US3, | 1061 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US3, |
| 1062 | .flags = IORESOURCE_IRQ, | 1062 | .flags = IORESOURCE_IRQ, |
| 1063 | }, | 1063 | }, |
| 1064 | }; | 1064 | }; |
| @@ -1100,8 +1100,8 @@ static struct resource uart4_resources[] = { | |||
| 1100 | .flags = IORESOURCE_MEM, | 1100 | .flags = IORESOURCE_MEM, |
| 1101 | }, | 1101 | }, |
| 1102 | [1] = { | 1102 | [1] = { |
| 1103 | .start = AT91SAM9260_ID_US4, | 1103 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US4, |
| 1104 | .end = AT91SAM9260_ID_US4, | 1104 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US4, |
| 1105 | .flags = IORESOURCE_IRQ, | 1105 | .flags = IORESOURCE_IRQ, |
| 1106 | }, | 1106 | }, |
| 1107 | }; | 1107 | }; |
| @@ -1138,8 +1138,8 @@ static struct resource uart5_resources[] = { | |||
| 1138 | .flags = IORESOURCE_MEM, | 1138 | .flags = IORESOURCE_MEM, |
| 1139 | }, | 1139 | }, |
| 1140 | [1] = { | 1140 | [1] = { |
| 1141 | .start = AT91SAM9260_ID_US5, | 1141 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US5, |
| 1142 | .end = AT91SAM9260_ID_US5, | 1142 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US5, |
| 1143 | .flags = IORESOURCE_IRQ, | 1143 | .flags = IORESOURCE_IRQ, |
| 1144 | }, | 1144 | }, |
| 1145 | }; | 1145 | }; |
| @@ -1357,8 +1357,8 @@ static struct resource adc_resources[] = { | |||
| 1357 | .flags = IORESOURCE_MEM, | 1357 | .flags = IORESOURCE_MEM, |
| 1358 | }, | 1358 | }, |
| 1359 | [1] = { | 1359 | [1] = { |
| 1360 | .start = AT91SAM9260_ID_ADC, | 1360 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_ADC, |
| 1361 | .end = AT91SAM9260_ID_ADC, | 1361 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_ADC, |
| 1362 | .flags = IORESOURCE_IRQ, | 1362 | .flags = IORESOURCE_IRQ, |
| 1363 | }, | 1363 | }, |
| 1364 | }; | 1364 | }; |
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c index c77d503d09d1..f40762c5fede 100644 --- a/arch/arm/mach-at91/at91sam9261.c +++ b/arch/arm/mach-at91/at91sam9261.c | |||
| @@ -19,6 +19,7 @@ | |||
| 19 | #include <asm/system_misc.h> | 19 | #include <asm/system_misc.h> |
| 20 | #include <mach/cpu.h> | 20 | #include <mach/cpu.h> |
| 21 | #include <mach/at91sam9261.h> | 21 | #include <mach/at91sam9261.h> |
| 22 | #include <mach/at91_aic.h> | ||
| 22 | #include <mach/at91_pmc.h> | 23 | #include <mach/at91_pmc.h> |
| 23 | #include <mach/at91_rstc.h> | 24 | #include <mach/at91_rstc.h> |
| 24 | 25 | ||
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c index 9295e90b08ff..8df5c1bdff92 100644 --- a/arch/arm/mach-at91/at91sam9261_devices.c +++ b/arch/arm/mach-at91/at91sam9261_devices.c | |||
| @@ -45,8 +45,8 @@ static struct resource usbh_resources[] = { | |||
| 45 | .flags = IORESOURCE_MEM, | 45 | .flags = IORESOURCE_MEM, |
| 46 | }, | 46 | }, |
| 47 | [1] = { | 47 | [1] = { |
| 48 | .start = AT91SAM9261_ID_UHP, | 48 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_UHP, |
| 49 | .end = AT91SAM9261_ID_UHP, | 49 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_UHP, |
| 50 | .flags = IORESOURCE_IRQ, | 50 | .flags = IORESOURCE_IRQ, |
| 51 | }, | 51 | }, |
| 52 | }; | 52 | }; |
| @@ -98,8 +98,8 @@ static struct resource udc_resources[] = { | |||
| 98 | .flags = IORESOURCE_MEM, | 98 | .flags = IORESOURCE_MEM, |
| 99 | }, | 99 | }, |
| 100 | [1] = { | 100 | [1] = { |
| 101 | .start = AT91SAM9261_ID_UDP, | 101 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_UDP, |
| 102 | .end = AT91SAM9261_ID_UDP, | 102 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_UDP, |
| 103 | .flags = IORESOURCE_IRQ, | 103 | .flags = IORESOURCE_IRQ, |
| 104 | }, | 104 | }, |
| 105 | }; | 105 | }; |
| @@ -148,8 +148,8 @@ static struct resource mmc_resources[] = { | |||
| 148 | .flags = IORESOURCE_MEM, | 148 | .flags = IORESOURCE_MEM, |
| 149 | }, | 149 | }, |
| 150 | [1] = { | 150 | [1] = { |
| 151 | .start = AT91SAM9261_ID_MCI, | 151 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_MCI, |
| 152 | .end = AT91SAM9261_ID_MCI, | 152 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_MCI, |
| 153 | .flags = IORESOURCE_IRQ, | 153 | .flags = IORESOURCE_IRQ, |
| 154 | }, | 154 | }, |
| 155 | }; | 155 | }; |
| @@ -310,8 +310,8 @@ static struct resource twi_resources[] = { | |||
| 310 | .flags = IORESOURCE_MEM, | 310 | .flags = IORESOURCE_MEM, |
| 311 | }, | 311 | }, |
| 312 | [1] = { | 312 | [1] = { |
| 313 | .start = AT91SAM9261_ID_TWI, | 313 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TWI, |
| 314 | .end = AT91SAM9261_ID_TWI, | 314 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TWI, |
| 315 | .flags = IORESOURCE_IRQ, | 315 | .flags = IORESOURCE_IRQ, |
| 316 | }, | 316 | }, |
| 317 | }; | 317 | }; |
| @@ -354,8 +354,8 @@ static struct resource spi0_resources[] = { | |||
| 354 | .flags = IORESOURCE_MEM, | 354 | .flags = IORESOURCE_MEM, |
| 355 | }, | 355 | }, |
| 356 | [1] = { | 356 | [1] = { |
| 357 | .start = AT91SAM9261_ID_SPI0, | 357 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI0, |
| 358 | .end = AT91SAM9261_ID_SPI0, | 358 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI0, |
| 359 | .flags = IORESOURCE_IRQ, | 359 | .flags = IORESOURCE_IRQ, |
| 360 | }, | 360 | }, |
| 361 | }; | 361 | }; |
| @@ -380,8 +380,8 @@ static struct resource spi1_resources[] = { | |||
| 380 | .flags = IORESOURCE_MEM, | 380 | .flags = IORESOURCE_MEM, |
| 381 | }, | 381 | }, |
| 382 | [1] = { | 382 | [1] = { |
| 383 | .start = AT91SAM9261_ID_SPI1, | 383 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI1, |
| 384 | .end = AT91SAM9261_ID_SPI1, | 384 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI1, |
| 385 | .flags = IORESOURCE_IRQ, | 385 | .flags = IORESOURCE_IRQ, |
| 386 | }, | 386 | }, |
| 387 | }; | 387 | }; |
| @@ -468,8 +468,8 @@ static struct resource lcdc_resources[] = { | |||
| 468 | .flags = IORESOURCE_MEM, | 468 | .flags = IORESOURCE_MEM, |
| 469 | }, | 469 | }, |
| 470 | [1] = { | 470 | [1] = { |
| 471 | .start = AT91SAM9261_ID_LCDC, | 471 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_LCDC, |
| 472 | .end = AT91SAM9261_ID_LCDC, | 472 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_LCDC, |
| 473 | .flags = IORESOURCE_IRQ, | 473 | .flags = IORESOURCE_IRQ, |
| 474 | }, | 474 | }, |
| 475 | #if defined(CONFIG_FB_INTSRAM) | 475 | #if defined(CONFIG_FB_INTSRAM) |
| @@ -566,18 +566,18 @@ static struct resource tcb_resources[] = { | |||
| 566 | .flags = IORESOURCE_MEM, | 566 | .flags = IORESOURCE_MEM, |
| 567 | }, | 567 | }, |
| 568 | [1] = { | 568 | [1] = { |
| 569 | .start = AT91SAM9261_ID_TC0, | 569 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TC0, |
| 570 | .end = AT91SAM9261_ID_TC0, | 570 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TC0, |
| 571 | .flags = IORESOURCE_IRQ, | 571 | .flags = IORESOURCE_IRQ, |
| 572 | }, | 572 | }, |
| 573 | [2] = { | 573 | [2] = { |
| 574 | .start = AT91SAM9261_ID_TC1, | 574 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TC1, |
| 575 | .end = AT91SAM9261_ID_TC1, | 575 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TC1, |
| 576 | .flags = IORESOURCE_IRQ, | 576 | .flags = IORESOURCE_IRQ, |
| 577 | }, | 577 | }, |
| 578 | [3] = { | 578 | [3] = { |
| 579 | .start = AT91SAM9261_ID_TC2, | 579 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TC2, |
| 580 | .end = AT91SAM9261_ID_TC2, | 580 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TC2, |
| 581 | .flags = IORESOURCE_IRQ, | 581 | .flags = IORESOURCE_IRQ, |
| 582 | }, | 582 | }, |
| 583 | }; | 583 | }; |
| @@ -689,8 +689,8 @@ static struct resource ssc0_resources[] = { | |||
| 689 | .flags = IORESOURCE_MEM, | 689 | .flags = IORESOURCE_MEM, |
| 690 | }, | 690 | }, |
| 691 | [1] = { | 691 | [1] = { |
| 692 | .start = AT91SAM9261_ID_SSC0, | 692 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC0, |
| 693 | .end = AT91SAM9261_ID_SSC0, | 693 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC0, |
| 694 | .flags = IORESOURCE_IRQ, | 694 | .flags = IORESOURCE_IRQ, |
| 695 | }, | 695 | }, |
| 696 | }; | 696 | }; |
| @@ -731,8 +731,8 @@ static struct resource ssc1_resources[] = { | |||
| 731 | .flags = IORESOURCE_MEM, | 731 | .flags = IORESOURCE_MEM, |
| 732 | }, | 732 | }, |
| 733 | [1] = { | 733 | [1] = { |
| 734 | .start = AT91SAM9261_ID_SSC1, | 734 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC1, |
| 735 | .end = AT91SAM9261_ID_SSC1, | 735 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC1, |
| 736 | .flags = IORESOURCE_IRQ, | 736 | .flags = IORESOURCE_IRQ, |
| 737 | }, | 737 | }, |
| 738 | }; | 738 | }; |
| @@ -773,8 +773,8 @@ static struct resource ssc2_resources[] = { | |||
| 773 | .flags = IORESOURCE_MEM, | 773 | .flags = IORESOURCE_MEM, |
| 774 | }, | 774 | }, |
| 775 | [1] = { | 775 | [1] = { |
| 776 | .start = AT91SAM9261_ID_SSC2, | 776 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC2, |
| 777 | .end = AT91SAM9261_ID_SSC2, | 777 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC2, |
| 778 | .flags = IORESOURCE_IRQ, | 778 | .flags = IORESOURCE_IRQ, |
| 779 | }, | 779 | }, |
| 780 | }; | 780 | }; |
| @@ -857,8 +857,8 @@ static struct resource dbgu_resources[] = { | |||
| 857 | .flags = IORESOURCE_MEM, | 857 | .flags = IORESOURCE_MEM, |
| 858 | }, | 858 | }, |
| 859 | [1] = { | 859 | [1] = { |
| 860 | .start = AT91_ID_SYS, | 860 | .start = NR_IRQS_LEGACY + AT91_ID_SYS, |
| 861 | .end = AT91_ID_SYS, | 861 | .end = NR_IRQS_LEGACY + AT91_ID_SYS, |
| 862 | .flags = IORESOURCE_IRQ, | 862 | .flags = IORESOURCE_IRQ, |
| 863 | }, | 863 | }, |
| 864 | }; | 864 | }; |
| @@ -895,8 +895,8 @@ static struct resource uart0_resources[] = { | |||
| 895 | .flags = IORESOURCE_MEM, | 895 | .flags = IORESOURCE_MEM, |
| 896 | }, | 896 | }, |
| 897 | [1] = { | 897 | [1] = { |
| 898 | .start = AT91SAM9261_ID_US0, | 898 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_US0, |
| 899 | .end = AT91SAM9261_ID_US0, | 899 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_US0, |
| 900 | .flags = IORESOURCE_IRQ, | 900 | .flags = IORESOURCE_IRQ, |
| 901 | }, | 901 | }, |
| 902 | }; | 902 | }; |
| @@ -938,8 +938,8 @@ static struct resource uart1_resources[] = { | |||
| 938 | .flags = IORESOURCE_MEM, | 938 | .flags = IORESOURCE_MEM, |
| 939 | }, | 939 | }, |
| 940 | [1] = { | 940 | [1] = { |
| 941 | .start = AT91SAM9261_ID_US1, | 941 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_US1, |
| 942 | .end = AT91SAM9261_ID_US1, | 942 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_US1, |
| 943 | .flags = IORESOURCE_IRQ, | 943 | .flags = IORESOURCE_IRQ, |
| 944 | }, | 944 | }, |
| 945 | }; | 945 | }; |
| @@ -981,8 +981,8 @@ static struct resource uart2_resources[] = { | |||
| 981 | .flags = IORESOURCE_MEM, | 981 | .flags = IORESOURCE_MEM, |
| 982 | }, | 982 | }, |
| 983 | [1] = { | 983 | [1] = { |
| 984 | .start = AT91SAM9261_ID_US2, | 984 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_US2, |
| 985 | .end = AT91SAM9261_ID_US2, | 985 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_US2, |
| 986 | .flags = IORESOURCE_IRQ, | 986 | .flags = IORESOURCE_IRQ, |
| 987 | }, | 987 | }, |
| 988 | }; | 988 | }; |
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c index ed91c7e9f7c2..84b38105231e 100644 --- a/arch/arm/mach-at91/at91sam9263.c +++ b/arch/arm/mach-at91/at91sam9263.c | |||
| @@ -18,6 +18,7 @@ | |||
| 18 | #include <asm/mach/map.h> | 18 | #include <asm/mach/map.h> |
| 19 | #include <asm/system_misc.h> | 19 | #include <asm/system_misc.h> |
| 20 | #include <mach/at91sam9263.h> | 20 | #include <mach/at91sam9263.h> |
| 21 | #include <mach/at91_aic.h> | ||
| 21 | #include <mach/at91_pmc.h> | 22 | #include <mach/at91_pmc.h> |
| 22 | #include <mach/at91_rstc.h> | 23 | #include <mach/at91_rstc.h> |
| 23 | 24 | ||
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c index 175e0009eaa9..eb6bbf86fb9f 100644 --- a/arch/arm/mach-at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/at91sam9263_devices.c | |||
| @@ -44,8 +44,8 @@ static struct resource usbh_resources[] = { | |||
| 44 | .flags = IORESOURCE_MEM, | 44 | .flags = IORESOURCE_MEM, |
| 45 | }, | 45 | }, |
| 46 | [1] = { | 46 | [1] = { |
| 47 | .start = AT91SAM9263_ID_UHP, | 47 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_UHP, |
| 48 | .end = AT91SAM9263_ID_UHP, | 48 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_UHP, |
| 49 | .flags = IORESOURCE_IRQ, | 49 | .flags = IORESOURCE_IRQ, |
| 50 | }, | 50 | }, |
| 51 | }; | 51 | }; |
| @@ -104,8 +104,8 @@ static struct resource udc_resources[] = { | |||
| 104 | .flags = IORESOURCE_MEM, | 104 | .flags = IORESOURCE_MEM, |
| 105 | }, | 105 | }, |
| 106 | [1] = { | 106 | [1] = { |
| 107 | .start = AT91SAM9263_ID_UDP, | 107 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_UDP, |
| 108 | .end = AT91SAM9263_ID_UDP, | 108 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_UDP, |
| 109 | .flags = IORESOURCE_IRQ, | 109 | .flags = IORESOURCE_IRQ, |
| 110 | }, | 110 | }, |
| 111 | }; | 111 | }; |
| @@ -155,8 +155,8 @@ static struct resource eth_resources[] = { | |||
| 155 | .flags = IORESOURCE_MEM, | 155 | .flags = IORESOURCE_MEM, |
| 156 | }, | 156 | }, |
| 157 | [1] = { | 157 | [1] = { |
| 158 | .start = AT91SAM9263_ID_EMAC, | 158 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_EMAC, |
| 159 | .end = AT91SAM9263_ID_EMAC, | 159 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_EMAC, |
| 160 | .flags = IORESOURCE_IRQ, | 160 | .flags = IORESOURCE_IRQ, |
| 161 | }, | 161 | }, |
| 162 | }; | 162 | }; |
| @@ -229,8 +229,8 @@ static struct resource mmc0_resources[] = { | |||
| 229 | .flags = IORESOURCE_MEM, | 229 | .flags = IORESOURCE_MEM, |
| 230 | }, | 230 | }, |
| 231 | [1] = { | 231 | [1] = { |
| 232 | .start = AT91SAM9263_ID_MCI0, | 232 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI0, |
| 233 | .end = AT91SAM9263_ID_MCI0, | 233 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI0, |
| 234 | .flags = IORESOURCE_IRQ, | 234 | .flags = IORESOURCE_IRQ, |
| 235 | }, | 235 | }, |
| 236 | }; | 236 | }; |
| @@ -254,8 +254,8 @@ static struct resource mmc1_resources[] = { | |||
| 254 | .flags = IORESOURCE_MEM, | 254 | .flags = IORESOURCE_MEM, |
| 255 | }, | 255 | }, |
| 256 | [1] = { | 256 | [1] = { |
| 257 | .start = AT91SAM9263_ID_MCI1, | 257 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI1, |
| 258 | .end = AT91SAM9263_ID_MCI1, | 258 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI1, |
| 259 | .flags = IORESOURCE_IRQ, | 259 | .flags = IORESOURCE_IRQ, |
| 260 | }, | 260 | }, |
| 261 | }; | 261 | }; |
| @@ -567,8 +567,8 @@ static struct resource twi_resources[] = { | |||
| 567 | .flags = IORESOURCE_MEM, | 567 | .flags = IORESOURCE_MEM, |
| 568 | }, | 568 | }, |
| 569 | [1] = { | 569 | [1] = { |
| 570 | .start = AT91SAM9263_ID_TWI, | 570 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_TWI, |
| 571 | .end = AT91SAM9263_ID_TWI, | 571 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_TWI, |
| 572 | .flags = IORESOURCE_IRQ, | 572 | .flags = IORESOURCE_IRQ, |
| 573 | }, | 573 | }, |
| 574 | }; | 574 | }; |
| @@ -611,8 +611,8 @@ static struct resource spi0_resources[] = { | |||
| 611 | .flags = IORESOURCE_MEM, | 611 | .flags = IORESOURCE_MEM, |
| 612 | }, | 612 | }, |
| 613 | [1] = { | 613 | [1] = { |
| 614 | .start = AT91SAM9263_ID_SPI0, | 614 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI0, |
| 615 | .end = AT91SAM9263_ID_SPI0, | 615 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI0, |
| 616 | .flags = IORESOURCE_IRQ, | 616 | .flags = IORESOURCE_IRQ, |
| 617 | }, | 617 | }, |
| 618 | }; | 618 | }; |
| @@ -637,8 +637,8 @@ static struct resource spi1_resources[] = { | |||
| 637 | .flags = IORESOURCE_MEM, | 637 | .flags = IORESOURCE_MEM, |
| 638 | }, | 638 | }, |
| 639 | [1] = { | 639 | [1] = { |
| 640 | .start = AT91SAM9263_ID_SPI1, | 640 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI1, |
| 641 | .end = AT91SAM9263_ID_SPI1, | 641 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI1, |
| 642 | .flags = IORESOURCE_IRQ, | 642 | .flags = IORESOURCE_IRQ, |
| 643 | }, | 643 | }, |
| 644 | }; | 644 | }; |
| @@ -725,8 +725,8 @@ static struct resource ac97_resources[] = { | |||
| 725 | .flags = IORESOURCE_MEM, | 725 | .flags = IORESOURCE_MEM, |
| 726 | }, | 726 | }, |
| 727 | [1] = { | 727 | [1] = { |
| 728 | .start = AT91SAM9263_ID_AC97C, | 728 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_AC97C, |
| 729 | .end = AT91SAM9263_ID_AC97C, | 729 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_AC97C, |
| 730 | .flags = IORESOURCE_IRQ, | 730 | .flags = IORESOURCE_IRQ, |
| 731 | }, | 731 | }, |
| 732 | }; | 732 | }; |
| @@ -776,8 +776,8 @@ static struct resource can_resources[] = { | |||
| 776 | .flags = IORESOURCE_MEM, | 776 | .flags = IORESOURCE_MEM, |
| 777 | }, | 777 | }, |
| 778 | [1] = { | 778 | [1] = { |
| 779 | .start = AT91SAM9263_ID_CAN, | 779 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_CAN, |
| 780 | .end = AT91SAM9263_ID_CAN, | 780 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_CAN, |
| 781 | .flags = IORESOURCE_IRQ, | 781 | .flags = IORESOURCE_IRQ, |
| 782 | }, | 782 | }, |
| 783 | }; | 783 | }; |
| @@ -816,8 +816,8 @@ static struct resource lcdc_resources[] = { | |||
| 816 | .flags = IORESOURCE_MEM, | 816 | .flags = IORESOURCE_MEM, |
| 817 | }, | 817 | }, |
| 818 | [1] = { | 818 | [1] = { |
| 819 | .start = AT91SAM9263_ID_LCDC, | 819 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_LCDC, |
| 820 | .end = AT91SAM9263_ID_LCDC, | 820 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_LCDC, |
| 821 | .flags = IORESOURCE_IRQ, | 821 | .flags = IORESOURCE_IRQ, |
| 822 | }, | 822 | }, |
| 823 | }; | 823 | }; |
| @@ -883,8 +883,8 @@ struct resource isi_resources[] = { | |||
| 883 | .flags = IORESOURCE_MEM, | 883 | .flags = IORESOURCE_MEM, |
| 884 | }, | 884 | }, |
| 885 | [1] = { | 885 | [1] = { |
| 886 | .start = AT91SAM9263_ID_ISI, | 886 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_ISI, |
| 887 | .end = AT91SAM9263_ID_ISI, | 887 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_ISI, |
| 888 | .flags = IORESOURCE_IRQ, | 888 | .flags = IORESOURCE_IRQ, |
| 889 | }, | 889 | }, |
| 890 | }; | 890 | }; |
| @@ -940,8 +940,8 @@ static struct resource tcb_resources[] = { | |||
| 940 | .flags = IORESOURCE_MEM, | 940 | .flags = IORESOURCE_MEM, |
| 941 | }, | 941 | }, |
| 942 | [1] = { | 942 | [1] = { |
| 943 | .start = AT91SAM9263_ID_TCB, | 943 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_TCB, |
| 944 | .end = AT91SAM9263_ID_TCB, | 944 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_TCB, |
| 945 | .flags = IORESOURCE_IRQ, | 945 | .flags = IORESOURCE_IRQ, |
| 946 | }, | 946 | }, |
| 947 | }; | 947 | }; |
| @@ -1108,8 +1108,8 @@ static struct resource pwm_resources[] = { | |||
| 1108 | .flags = IORESOURCE_MEM, | 1108 | .flags = IORESOURCE_MEM, |
| 1109 | }, | 1109 | }, |
| 1110 | [1] = { | 1110 | [1] = { |
| 1111 | .start = AT91SAM9263_ID_PWMC, | 1111 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_PWMC, |
| 1112 | .end = AT91SAM9263_ID_PWMC, | 1112 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_PWMC, |
| 1113 | .flags = IORESOURCE_IRQ, | 1113 | .flags = IORESOURCE_IRQ, |
| 1114 | }, | 1114 | }, |
| 1115 | }; | 1115 | }; |
| @@ -1161,8 +1161,8 @@ static struct resource ssc0_resources[] = { | |||
| 1161 | .flags = IORESOURCE_MEM, | 1161 | .flags = IORESOURCE_MEM, |
| 1162 | }, | 1162 | }, |
| 1163 | [1] = { | 1163 | [1] = { |
| 1164 | .start = AT91SAM9263_ID_SSC0, | 1164 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC0, |
| 1165 | .end = AT91SAM9263_ID_SSC0, | 1165 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC0, |
| 1166 | .flags = IORESOURCE_IRQ, | 1166 | .flags = IORESOURCE_IRQ, |
| 1167 | }, | 1167 | }, |
| 1168 | }; | 1168 | }; |
| @@ -1203,8 +1203,8 @@ static struct resource ssc1_resources[] = { | |||
| 1203 | .flags = IORESOURCE_MEM, | 1203 | .flags = IORESOURCE_MEM, |
| 1204 | }, | 1204 | }, |
| 1205 | [1] = { | 1205 | [1] = { |
| 1206 | .start = AT91SAM9263_ID_SSC1, | 1206 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC1, |
| 1207 | .end = AT91SAM9263_ID_SSC1, | 1207 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC1, |
| 1208 | .flags = IORESOURCE_IRQ, | 1208 | .flags = IORESOURCE_IRQ, |
| 1209 | }, | 1209 | }, |
| 1210 | }; | 1210 | }; |
| @@ -1284,8 +1284,8 @@ static struct resource dbgu_resources[] = { | |||
| 1284 | .flags = IORESOURCE_MEM, | 1284 | .flags = IORESOURCE_MEM, |
| 1285 | }, | 1285 | }, |
| 1286 | [1] = { | 1286 | [1] = { |
| 1287 | .start = AT91_ID_SYS, | 1287 | .start = NR_IRQS_LEGACY + AT91_ID_SYS, |
| 1288 | .end = AT91_ID_SYS, | 1288 | .end = NR_IRQS_LEGACY + AT91_ID_SYS, |
| 1289 | .flags = IORESOURCE_IRQ, | 1289 | .flags = IORESOURCE_IRQ, |
| 1290 | }, | 1290 | }, |
| 1291 | }; | 1291 | }; |
| @@ -1322,8 +1322,8 @@ static struct resource uart0_resources[] = { | |||
| 1322 | .flags = IORESOURCE_MEM, | 1322 | .flags = IORESOURCE_MEM, |
| 1323 | }, | 1323 | }, |
| 1324 | [1] = { | 1324 | [1] = { |
| 1325 | .start = AT91SAM9263_ID_US0, | 1325 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_US0, |
| 1326 | .end = AT91SAM9263_ID_US0, | 1326 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_US0, |
| 1327 | .flags = IORESOURCE_IRQ, | 1327 | .flags = IORESOURCE_IRQ, |
| 1328 | }, | 1328 | }, |
| 1329 | }; | 1329 | }; |
| @@ -1365,8 +1365,8 @@ static struct resource uart1_resources[] = { | |||
| 1365 | .flags = IORESOURCE_MEM, | 1365 | .flags = IORESOURCE_MEM, |
| 1366 | }, | 1366 | }, |
| 1367 | [1] = { | 1367 | [1] = { |
| 1368 | .start = AT91SAM9263_ID_US1, | 1368 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_US1, |
| 1369 | .end = AT91SAM9263_ID_US1, | 1369 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_US1, |
| 1370 | .flags = IORESOURCE_IRQ, | 1370 | .flags = IORESOURCE_IRQ, |
| 1371 | }, | 1371 | }, |
| 1372 | }; | 1372 | }; |
| @@ -1408,8 +1408,8 @@ static struct resource uart2_resources[] = { | |||
| 1408 | .flags = IORESOURCE_MEM, | 1408 | .flags = IORESOURCE_MEM, |
| 1409 | }, | 1409 | }, |
| 1410 | [1] = { | 1410 | [1] = { |
| 1411 | .start = AT91SAM9263_ID_US2, | 1411 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_US2, |
| 1412 | .end = AT91SAM9263_ID_US2, | 1412 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_US2, |
| 1413 | .flags = IORESOURCE_IRQ, | 1413 | .flags = IORESOURCE_IRQ, |
| 1414 | }, | 1414 | }, |
| 1415 | }; | 1415 | }; |
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c index a94758b42737..ffc0957d7623 100644 --- a/arch/arm/mach-at91/at91sam926x_time.c +++ b/arch/arm/mach-at91/at91sam926x_time.c | |||
| @@ -137,7 +137,7 @@ static struct irqaction at91sam926x_pit_irq = { | |||
| 137 | .name = "at91_tick", | 137 | .name = "at91_tick", |
| 138 | .flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | 138 | .flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
| 139 | .handler = at91sam926x_pit_interrupt, | 139 | .handler = at91sam926x_pit_interrupt, |
| 140 | .irq = AT91_ID_SYS, | 140 | .irq = NR_IRQS_LEGACY + AT91_ID_SYS, |
| 141 | }; | 141 | }; |
| 142 | 142 | ||
| 143 | static void at91sam926x_pit_reset(void) | 143 | static void at91sam926x_pit_reset(void) |
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index 4792682d52b9..977127368a7d 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c | |||
| @@ -18,6 +18,7 @@ | |||
| 18 | #include <asm/mach/map.h> | 18 | #include <asm/mach/map.h> |
| 19 | #include <asm/system_misc.h> | 19 | #include <asm/system_misc.h> |
| 20 | #include <mach/at91sam9g45.h> | 20 | #include <mach/at91sam9g45.h> |
| 21 | #include <mach/at91_aic.h> | ||
| 21 | #include <mach/at91_pmc.h> | 22 | #include <mach/at91_pmc.h> |
| 22 | #include <mach/cpu.h> | 23 | #include <mach/cpu.h> |
| 23 | 24 | ||
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c index 933fc9afe7d0..40fb79df2de0 100644 --- a/arch/arm/mach-at91/at91sam9g45_devices.c +++ b/arch/arm/mach-at91/at91sam9g45_devices.c | |||
| @@ -53,8 +53,8 @@ static struct resource hdmac_resources[] = { | |||
| 53 | .flags = IORESOURCE_MEM, | 53 | .flags = IORESOURCE_MEM, |
| 54 | }, | 54 | }, |
| 55 | [1] = { | 55 | [1] = { |
| 56 | .start = AT91SAM9G45_ID_DMA, | 56 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_DMA, |
| 57 | .end = AT91SAM9G45_ID_DMA, | 57 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_DMA, |
| 58 | .flags = IORESOURCE_IRQ, | 58 | .flags = IORESOURCE_IRQ, |
| 59 | }, | 59 | }, |
| 60 | }; | 60 | }; |
| @@ -94,8 +94,8 @@ static struct resource usbh_ohci_resources[] = { | |||
| 94 | .flags = IORESOURCE_MEM, | 94 | .flags = IORESOURCE_MEM, |
| 95 | }, | 95 | }, |
| 96 | [1] = { | 96 | [1] = { |
| 97 | .start = AT91SAM9G45_ID_UHPHS, | 97 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS, |
| 98 | .end = AT91SAM9G45_ID_UHPHS, | 98 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS, |
| 99 | .flags = IORESOURCE_IRQ, | 99 | .flags = IORESOURCE_IRQ, |
| 100 | }, | 100 | }, |
| 101 | }; | 101 | }; |
| @@ -156,8 +156,8 @@ static struct resource usbh_ehci_resources[] = { | |||
| 156 | .flags = IORESOURCE_MEM, | 156 | .flags = IORESOURCE_MEM, |
| 157 | }, | 157 | }, |
| 158 | [1] = { | 158 | [1] = { |
| 159 | .start = AT91SAM9G45_ID_UHPHS, | 159 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS, |
| 160 | .end = AT91SAM9G45_ID_UHPHS, | 160 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS, |
| 161 | .flags = IORESOURCE_IRQ, | 161 | .flags = IORESOURCE_IRQ, |
| 162 | }, | 162 | }, |
| 163 | }; | 163 | }; |
| @@ -213,8 +213,8 @@ static struct resource usba_udc_resources[] = { | |||
| 213 | .flags = IORESOURCE_MEM, | 213 | .flags = IORESOURCE_MEM, |
| 214 | }, | 214 | }, |
| 215 | [2] = { | 215 | [2] = { |
| 216 | .start = AT91SAM9G45_ID_UDPHS, | 216 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UDPHS, |
| 217 | .end = AT91SAM9G45_ID_UDPHS, | 217 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UDPHS, |
| 218 | .flags = IORESOURCE_IRQ, | 218 | .flags = IORESOURCE_IRQ, |
| 219 | }, | 219 | }, |
| 220 | }; | 220 | }; |
| @@ -296,8 +296,8 @@ static struct resource eth_resources[] = { | |||
| 296 | .flags = IORESOURCE_MEM, | 296 | .flags = IORESOURCE_MEM, |
| 297 | }, | 297 | }, |
| 298 | [1] = { | 298 | [1] = { |
| 299 | .start = AT91SAM9G45_ID_EMAC, | 299 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_EMAC, |
| 300 | .end = AT91SAM9G45_ID_EMAC, | 300 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_EMAC, |
| 301 | .flags = IORESOURCE_IRQ, | 301 | .flags = IORESOURCE_IRQ, |
| 302 | }, | 302 | }, |
| 303 | }; | 303 | }; |
| @@ -370,8 +370,8 @@ static struct resource mmc0_resources[] = { | |||
| 370 | .flags = IORESOURCE_MEM, | 370 | .flags = IORESOURCE_MEM, |
| 371 | }, | 371 | }, |
| 372 | [1] = { | 372 | [1] = { |
| 373 | .start = AT91SAM9G45_ID_MCI0, | 373 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI0, |
| 374 | .end = AT91SAM9G45_ID_MCI0, | 374 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI0, |
| 375 | .flags = IORESOURCE_IRQ, | 375 | .flags = IORESOURCE_IRQ, |
| 376 | }, | 376 | }, |
| 377 | }; | 377 | }; |
| @@ -395,8 +395,8 @@ static struct resource mmc1_resources[] = { | |||
| 395 | .flags = IORESOURCE_MEM, | 395 | .flags = IORESOURCE_MEM, |
| 396 | }, | 396 | }, |
| 397 | [1] = { | 397 | [1] = { |
| 398 | .start = AT91SAM9G45_ID_MCI1, | 398 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI1, |
| 399 | .end = AT91SAM9G45_ID_MCI1, | 399 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI1, |
| 400 | .flags = IORESOURCE_IRQ, | 400 | .flags = IORESOURCE_IRQ, |
| 401 | }, | 401 | }, |
| 402 | }; | 402 | }; |
| @@ -645,8 +645,8 @@ static struct resource twi0_resources[] = { | |||
| 645 | .flags = IORESOURCE_MEM, | 645 | .flags = IORESOURCE_MEM, |
| 646 | }, | 646 | }, |
| 647 | [1] = { | 647 | [1] = { |
| 648 | .start = AT91SAM9G45_ID_TWI0, | 648 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI0, |
| 649 | .end = AT91SAM9G45_ID_TWI0, | 649 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI0, |
| 650 | .flags = IORESOURCE_IRQ, | 650 | .flags = IORESOURCE_IRQ, |
| 651 | }, | 651 | }, |
| 652 | }; | 652 | }; |
| @@ -665,8 +665,8 @@ static struct resource twi1_resources[] = { | |||
| 665 | .flags = IORESOURCE_MEM, | 665 | .flags = IORESOURCE_MEM, |
| 666 | }, | 666 | }, |
| 667 | [1] = { | 667 | [1] = { |
| 668 | .start = AT91SAM9G45_ID_TWI1, | 668 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI1, |
| 669 | .end = AT91SAM9G45_ID_TWI1, | 669 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI1, |
| 670 | .flags = IORESOURCE_IRQ, | 670 | .flags = IORESOURCE_IRQ, |
| 671 | }, | 671 | }, |
| 672 | }; | 672 | }; |
| @@ -720,8 +720,8 @@ static struct resource spi0_resources[] = { | |||
| 720 | .flags = IORESOURCE_MEM, | 720 | .flags = IORESOURCE_MEM, |
| 721 | }, | 721 | }, |
| 722 | [1] = { | 722 | [1] = { |
| 723 | .start = AT91SAM9G45_ID_SPI0, | 723 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI0, |
| 724 | .end = AT91SAM9G45_ID_SPI0, | 724 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI0, |
| 725 | .flags = IORESOURCE_IRQ, | 725 | .flags = IORESOURCE_IRQ, |
| 726 | }, | 726 | }, |
| 727 | }; | 727 | }; |
| @@ -746,8 +746,8 @@ static struct resource spi1_resources[] = { | |||
| 746 | .flags = IORESOURCE_MEM, | 746 | .flags = IORESOURCE_MEM, |
| 747 | }, | 747 | }, |
| 748 | [1] = { | 748 | [1] = { |
| 749 | .start = AT91SAM9G45_ID_SPI1, | 749 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI1, |
| 750 | .end = AT91SAM9G45_ID_SPI1, | 750 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI1, |
| 751 | .flags = IORESOURCE_IRQ, | 751 | .flags = IORESOURCE_IRQ, |
| 752 | }, | 752 | }, |
| 753 | }; | 753 | }; |
| @@ -834,8 +834,8 @@ static struct resource ac97_resources[] = { | |||
| 834 | .flags = IORESOURCE_MEM, | 834 | .flags = IORESOURCE_MEM, |
| 835 | }, | 835 | }, |
| 836 | [1] = { | 836 | [1] = { |
| 837 | .start = AT91SAM9G45_ID_AC97C, | 837 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AC97C, |
| 838 | .end = AT91SAM9G45_ID_AC97C, | 838 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AC97C, |
| 839 | .flags = IORESOURCE_IRQ, | 839 | .flags = IORESOURCE_IRQ, |
| 840 | }, | 840 | }, |
| 841 | }; | 841 | }; |
| @@ -887,8 +887,8 @@ struct resource isi_resources[] = { | |||
| 887 | .flags = IORESOURCE_MEM, | 887 | .flags = IORESOURCE_MEM, |
| 888 | }, | 888 | }, |
| 889 | [1] = { | 889 | [1] = { |
| 890 | .start = AT91SAM9G45_ID_ISI, | 890 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_ISI, |
| 891 | .end = AT91SAM9G45_ID_ISI, | 891 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_ISI, |
| 892 | .flags = IORESOURCE_IRQ, | 892 | .flags = IORESOURCE_IRQ, |
| 893 | }, | 893 | }, |
| 894 | }; | 894 | }; |
| @@ -979,8 +979,8 @@ static struct resource lcdc_resources[] = { | |||
| 979 | .flags = IORESOURCE_MEM, | 979 | .flags = IORESOURCE_MEM, |
| 980 | }, | 980 | }, |
| 981 | [1] = { | 981 | [1] = { |
| 982 | .start = AT91SAM9G45_ID_LCDC, | 982 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_LCDC, |
| 983 | .end = AT91SAM9G45_ID_LCDC, | 983 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_LCDC, |
| 984 | .flags = IORESOURCE_IRQ, | 984 | .flags = IORESOURCE_IRQ, |
| 985 | }, | 985 | }, |
| 986 | }; | 986 | }; |
| @@ -1054,8 +1054,8 @@ static struct resource tcb0_resources[] = { | |||
| 1054 | .flags = IORESOURCE_MEM, | 1054 | .flags = IORESOURCE_MEM, |
| 1055 | }, | 1055 | }, |
| 1056 | [1] = { | 1056 | [1] = { |
| 1057 | .start = AT91SAM9G45_ID_TCB, | 1057 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB, |
| 1058 | .end = AT91SAM9G45_ID_TCB, | 1058 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB, |
| 1059 | .flags = IORESOURCE_IRQ, | 1059 | .flags = IORESOURCE_IRQ, |
| 1060 | }, | 1060 | }, |
| 1061 | }; | 1061 | }; |
| @@ -1075,8 +1075,8 @@ static struct resource tcb1_resources[] = { | |||
| 1075 | .flags = IORESOURCE_MEM, | 1075 | .flags = IORESOURCE_MEM, |
| 1076 | }, | 1076 | }, |
| 1077 | [1] = { | 1077 | [1] = { |
| 1078 | .start = AT91SAM9G45_ID_TCB, | 1078 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB, |
| 1079 | .end = AT91SAM9G45_ID_TCB, | 1079 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB, |
| 1080 | .flags = IORESOURCE_IRQ, | 1080 | .flags = IORESOURCE_IRQ, |
| 1081 | }, | 1081 | }, |
| 1082 | }; | 1082 | }; |
| @@ -1110,8 +1110,8 @@ static struct resource rtc_resources[] = { | |||
| 1110 | .flags = IORESOURCE_MEM, | 1110 | .flags = IORESOURCE_MEM, |
| 1111 | }, | 1111 | }, |
| 1112 | [1] = { | 1112 | [1] = { |
| 1113 | .start = AT91_ID_SYS, | 1113 | .start = NR_IRQS_LEGACY + AT91_ID_SYS, |
| 1114 | .end = AT91_ID_SYS, | 1114 | .end = NR_IRQS_LEGACY + AT91_ID_SYS, |
| 1115 | .flags = IORESOURCE_IRQ, | 1115 | .flags = IORESOURCE_IRQ, |
| 1116 | }, | 1116 | }, |
| 1117 | }; | 1117 | }; |
| @@ -1147,8 +1147,8 @@ static struct resource tsadcc_resources[] = { | |||
| 1147 | .flags = IORESOURCE_MEM, | 1147 | .flags = IORESOURCE_MEM, |
| 1148 | }, | 1148 | }, |
| 1149 | [1] = { | 1149 | [1] = { |
| 1150 | .start = AT91SAM9G45_ID_TSC, | 1150 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC, |
| 1151 | .end = AT91SAM9G45_ID_TSC, | 1151 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC, |
| 1152 | .flags = IORESOURCE_IRQ, | 1152 | .flags = IORESOURCE_IRQ, |
| 1153 | } | 1153 | } |
| 1154 | }; | 1154 | }; |
| @@ -1197,8 +1197,8 @@ static struct resource adc_resources[] = { | |||
| 1197 | .flags = IORESOURCE_MEM, | 1197 | .flags = IORESOURCE_MEM, |
| 1198 | }, | 1198 | }, |
| 1199 | [1] = { | 1199 | [1] = { |
| 1200 | .start = AT91SAM9G45_ID_TSC, | 1200 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC, |
| 1201 | .end = AT91SAM9G45_ID_TSC, | 1201 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC, |
| 1202 | .flags = IORESOURCE_IRQ, | 1202 | .flags = IORESOURCE_IRQ, |
| 1203 | } | 1203 | } |
| 1204 | }; | 1204 | }; |
| @@ -1400,8 +1400,8 @@ static struct resource pwm_resources[] = { | |||
| 1400 | .flags = IORESOURCE_MEM, | 1400 | .flags = IORESOURCE_MEM, |
| 1401 | }, | 1401 | }, |
| 1402 | [1] = { | 1402 | [1] = { |
| 1403 | .start = AT91SAM9G45_ID_PWMC, | 1403 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_PWMC, |
| 1404 | .end = AT91SAM9G45_ID_PWMC, | 1404 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_PWMC, |
| 1405 | .flags = IORESOURCE_IRQ, | 1405 | .flags = IORESOURCE_IRQ, |
| 1406 | }, | 1406 | }, |
| 1407 | }; | 1407 | }; |
| @@ -1453,8 +1453,8 @@ static struct resource ssc0_resources[] = { | |||
| 1453 | .flags = IORESOURCE_MEM, | 1453 | .flags = IORESOURCE_MEM, |
| 1454 | }, | 1454 | }, |
| 1455 | [1] = { | 1455 | [1] = { |
| 1456 | .start = AT91SAM9G45_ID_SSC0, | 1456 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC0, |
| 1457 | .end = AT91SAM9G45_ID_SSC0, | 1457 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC0, |
| 1458 | .flags = IORESOURCE_IRQ, | 1458 | .flags = IORESOURCE_IRQ, |
| 1459 | }, | 1459 | }, |
| 1460 | }; | 1460 | }; |
| @@ -1495,8 +1495,8 @@ static struct resource ssc1_resources[] = { | |||
| 1495 | .flags = IORESOURCE_MEM, | 1495 | .flags = IORESOURCE_MEM, |
| 1496 | }, | 1496 | }, |
| 1497 | [1] = { | 1497 | [1] = { |
| 1498 | .start = AT91SAM9G45_ID_SSC1, | 1498 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC1, |
| 1499 | .end = AT91SAM9G45_ID_SSC1, | 1499 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC1, |
| 1500 | .flags = IORESOURCE_IRQ, | 1500 | .flags = IORESOURCE_IRQ, |
| 1501 | }, | 1501 | }, |
| 1502 | }; | 1502 | }; |
| @@ -1575,8 +1575,8 @@ static struct resource dbgu_resources[] = { | |||
| 1575 | .flags = IORESOURCE_MEM, | 1575 | .flags = IORESOURCE_MEM, |
| 1576 | }, | 1576 | }, |
| 1577 | [1] = { | 1577 | [1] = { |
| 1578 | .start = AT91_ID_SYS, | 1578 | .start = NR_IRQS_LEGACY + AT91_ID_SYS, |
| 1579 | .end = AT91_ID_SYS, | 1579 | .end = NR_IRQS_LEGACY + AT91_ID_SYS, |
| 1580 | .flags = IORESOURCE_IRQ, | 1580 | .flags = IORESOURCE_IRQ, |
| 1581 | }, | 1581 | }, |
| 1582 | }; | 1582 | }; |
| @@ -1613,8 +1613,8 @@ static struct resource uart0_resources[] = { | |||
| 1613 | .flags = IORESOURCE_MEM, | 1613 | .flags = IORESOURCE_MEM, |
| 1614 | }, | 1614 | }, |
| 1615 | [1] = { | 1615 | [1] = { |
| 1616 | .start = AT91SAM9G45_ID_US0, | 1616 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0, |
| 1617 | .end = AT91SAM9G45_ID_US0, | 1617 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0, |
| 1618 | .flags = IORESOURCE_IRQ, | 1618 | .flags = IORESOURCE_IRQ, |
| 1619 | }, | 1619 | }, |
| 1620 | }; | 1620 | }; |
| @@ -1656,8 +1656,8 @@ static struct resource uart1_resources[] = { | |||
| 1656 | .flags = IORESOURCE_MEM, | 1656 | .flags = IORESOURCE_MEM, |
| 1657 | }, | 1657 | }, |
| 1658 | [1] = { | 1658 | [1] = { |
| 1659 | .start = AT91SAM9G45_ID_US1, | 1659 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US1, |
| 1660 | .end = AT91SAM9G45_ID_US1, | 1660 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US1, |
| 1661 | .flags = IORESOURCE_IRQ, | 1661 | .flags = IORESOURCE_IRQ, |
| 1662 | }, | 1662 | }, |
| 1663 | }; | 1663 | }; |
| @@ -1699,8 +1699,8 @@ static struct resource uart2_resources[] = { | |||
| 1699 | .flags = IORESOURCE_MEM, | 1699 | .flags = IORESOURCE_MEM, |
| 1700 | }, | 1700 | }, |
| 1701 | [1] = { | 1701 | [1] = { |
| 1702 | .start = AT91SAM9G45_ID_US2, | 1702 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US2, |
| 1703 | .end = AT91SAM9G45_ID_US2, | 1703 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US2, |
| 1704 | .flags = IORESOURCE_IRQ, | 1704 | .flags = IORESOURCE_IRQ, |
| 1705 | }, | 1705 | }, |
| 1706 | }; | 1706 | }; |
| @@ -1742,8 +1742,8 @@ static struct resource uart3_resources[] = { | |||
| 1742 | .flags = IORESOURCE_MEM, | 1742 | .flags = IORESOURCE_MEM, |
| 1743 | }, | 1743 | }, |
| 1744 | [1] = { | 1744 | [1] = { |
| 1745 | .start = AT91SAM9G45_ID_US3, | 1745 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US3, |
| 1746 | .end = AT91SAM9G45_ID_US3, | 1746 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US3, |
| 1747 | .flags = IORESOURCE_IRQ, | 1747 | .flags = IORESOURCE_IRQ, |
| 1748 | }, | 1748 | }, |
| 1749 | }; | 1749 | }; |
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c index e420085a57ef..72ce50a50de5 100644 --- a/arch/arm/mach-at91/at91sam9rl.c +++ b/arch/arm/mach-at91/at91sam9rl.c | |||
| @@ -19,6 +19,7 @@ | |||
| 19 | #include <mach/cpu.h> | 19 | #include <mach/cpu.h> |
| 20 | #include <mach/at91_dbgu.h> | 20 | #include <mach/at91_dbgu.h> |
| 21 | #include <mach/at91sam9rl.h> | 21 | #include <mach/at91sam9rl.h> |
| 22 | #include <mach/at91_aic.h> | ||
| 22 | #include <mach/at91_pmc.h> | 23 | #include <mach/at91_pmc.h> |
| 23 | #include <mach/at91_rstc.h> | 24 | #include <mach/at91_rstc.h> |
| 24 | 25 | ||
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c index 9c0b1481a9a7..f09fff932172 100644 --- a/arch/arm/mach-at91/at91sam9rl_devices.c +++ b/arch/arm/mach-at91/at91sam9rl_devices.c | |||
| @@ -41,8 +41,8 @@ static struct resource hdmac_resources[] = { | |||
| 41 | .flags = IORESOURCE_MEM, | 41 | .flags = IORESOURCE_MEM, |
| 42 | }, | 42 | }, |
| 43 | [2] = { | 43 | [2] = { |
| 44 | .start = AT91SAM9RL_ID_DMA, | 44 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_DMA, |
| 45 | .end = AT91SAM9RL_ID_DMA, | 45 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_DMA, |
| 46 | .flags = IORESOURCE_IRQ, | 46 | .flags = IORESOURCE_IRQ, |
| 47 | }, | 47 | }, |
| 48 | }; | 48 | }; |
| @@ -84,8 +84,8 @@ static struct resource usba_udc_resources[] = { | |||
| 84 | .flags = IORESOURCE_MEM, | 84 | .flags = IORESOURCE_MEM, |
| 85 | }, | 85 | }, |
| 86 | [2] = { | 86 | [2] = { |
| 87 | .start = AT91SAM9RL_ID_UDPHS, | 87 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_UDPHS, |
| 88 | .end = AT91SAM9RL_ID_UDPHS, | 88 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_UDPHS, |
| 89 | .flags = IORESOURCE_IRQ, | 89 | .flags = IORESOURCE_IRQ, |
| 90 | }, | 90 | }, |
| 91 | }; | 91 | }; |
| @@ -172,8 +172,8 @@ static struct resource mmc_resources[] = { | |||
| 172 | .flags = IORESOURCE_MEM, | 172 | .flags = IORESOURCE_MEM, |
| 173 | }, | 173 | }, |
| 174 | [1] = { | 174 | [1] = { |
| 175 | .start = AT91SAM9RL_ID_MCI, | 175 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_MCI, |
| 176 | .end = AT91SAM9RL_ID_MCI, | 176 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_MCI, |
| 177 | .flags = IORESOURCE_IRQ, | 177 | .flags = IORESOURCE_IRQ, |
| 178 | }, | 178 | }, |
| 179 | }; | 179 | }; |
| @@ -339,8 +339,8 @@ static struct resource twi_resources[] = { | |||
| 339 | .flags = IORESOURCE_MEM, | 339 | .flags = IORESOURCE_MEM, |
| 340 | }, | 340 | }, |
| 341 | [1] = { | 341 | [1] = { |
| 342 | .start = AT91SAM9RL_ID_TWI0, | 342 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TWI0, |
| 343 | .end = AT91SAM9RL_ID_TWI0, | 343 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TWI0, |
| 344 | .flags = IORESOURCE_IRQ, | 344 | .flags = IORESOURCE_IRQ, |
| 345 | }, | 345 | }, |
| 346 | }; | 346 | }; |
| @@ -383,8 +383,8 @@ static struct resource spi_resources[] = { | |||
| 383 | .flags = IORESOURCE_MEM, | 383 | .flags = IORESOURCE_MEM, |
| 384 | }, | 384 | }, |
| 385 | [1] = { | 385 | [1] = { |
| 386 | .start = AT91SAM9RL_ID_SPI, | 386 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_SPI, |
| 387 | .end = AT91SAM9RL_ID_SPI, | 387 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_SPI, |
| 388 | .flags = IORESOURCE_IRQ, | 388 | .flags = IORESOURCE_IRQ, |
| 389 | }, | 389 | }, |
| 390 | }; | 390 | }; |
| @@ -452,8 +452,8 @@ static struct resource ac97_resources[] = { | |||
| 452 | .flags = IORESOURCE_MEM, | 452 | .flags = IORESOURCE_MEM, |
| 453 | }, | 453 | }, |
| 454 | [1] = { | 454 | [1] = { |
| 455 | .start = AT91SAM9RL_ID_AC97C, | 455 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_AC97C, |
| 456 | .end = AT91SAM9RL_ID_AC97C, | 456 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_AC97C, |
| 457 | .flags = IORESOURCE_IRQ, | 457 | .flags = IORESOURCE_IRQ, |
| 458 | }, | 458 | }, |
| 459 | }; | 459 | }; |
| @@ -507,8 +507,8 @@ static struct resource lcdc_resources[] = { | |||
| 507 | .flags = IORESOURCE_MEM, | 507 | .flags = IORESOURCE_MEM, |
| 508 | }, | 508 | }, |
| 509 | [1] = { | 509 | [1] = { |
| 510 | .start = AT91SAM9RL_ID_LCDC, | 510 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_LCDC, |
| 511 | .end = AT91SAM9RL_ID_LCDC, | 511 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_LCDC, |
| 512 | .flags = IORESOURCE_IRQ, | 512 | .flags = IORESOURCE_IRQ, |
| 513 | }, | 513 | }, |
| 514 | }; | 514 | }; |
| @@ -574,18 +574,18 @@ static struct resource tcb_resources[] = { | |||
| 574 | .flags = IORESOURCE_MEM, | 574 | .flags = IORESOURCE_MEM, |
| 575 | }, | 575 | }, |
| 576 | [1] = { | 576 | [1] = { |
| 577 | .start = AT91SAM9RL_ID_TC0, | 577 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC0, |
| 578 | .end = AT91SAM9RL_ID_TC0, | 578 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC0, |
| 579 | .flags = IORESOURCE_IRQ, | 579 | .flags = IORESOURCE_IRQ, |
| 580 | }, | 580 | }, |
| 581 | [2] = { | 581 | [2] = { |
| 582 | .start = AT91SAM9RL_ID_TC1, | 582 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC1, |
| 583 | .end = AT91SAM9RL_ID_TC1, | 583 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC1, |
| 584 | .flags = IORESOURCE_IRQ, | 584 | .flags = IORESOURCE_IRQ, |
| 585 | }, | 585 | }, |
| 586 | [3] = { | 586 | [3] = { |
| 587 | .start = AT91SAM9RL_ID_TC2, | 587 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC2, |
| 588 | .end = AT91SAM9RL_ID_TC2, | 588 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC2, |
| 589 | .flags = IORESOURCE_IRQ, | 589 | .flags = IORESOURCE_IRQ, |
| 590 | }, | 590 | }, |
| 591 | }; | 591 | }; |
| @@ -621,8 +621,8 @@ static struct resource tsadcc_resources[] = { | |||
| 621 | .flags = IORESOURCE_MEM, | 621 | .flags = IORESOURCE_MEM, |
| 622 | }, | 622 | }, |
| 623 | [1] = { | 623 | [1] = { |
| 624 | .start = AT91SAM9RL_ID_TSC, | 624 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TSC, |
| 625 | .end = AT91SAM9RL_ID_TSC, | 625 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TSC, |
| 626 | .flags = IORESOURCE_IRQ, | 626 | .flags = IORESOURCE_IRQ, |
| 627 | } | 627 | } |
| 628 | }; | 628 | }; |
| @@ -768,8 +768,8 @@ static struct resource pwm_resources[] = { | |||
| 768 | .flags = IORESOURCE_MEM, | 768 | .flags = IORESOURCE_MEM, |
| 769 | }, | 769 | }, |
| 770 | [1] = { | 770 | [1] = { |
| 771 | .start = AT91SAM9RL_ID_PWMC, | 771 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_PWMC, |
| 772 | .end = AT91SAM9RL_ID_PWMC, | 772 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_PWMC, |
| 773 | .flags = IORESOURCE_IRQ, | 773 | .flags = IORESOURCE_IRQ, |
| 774 | }, | 774 | }, |
| 775 | }; | 775 | }; |
| @@ -821,8 +821,8 @@ static struct resource ssc0_resources[] = { | |||
| 821 | .flags = IORESOURCE_MEM, | 821 | .flags = IORESOURCE_MEM, |
| 822 | }, | 822 | }, |
| 823 | [1] = { | 823 | [1] = { |
| 824 | .start = AT91SAM9RL_ID_SSC0, | 824 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC0, |
| 825 | .end = AT91SAM9RL_ID_SSC0, | 825 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC0, |
| 826 | .flags = IORESOURCE_IRQ, | 826 | .flags = IORESOURCE_IRQ, |
| 827 | }, | 827 | }, |
| 828 | }; | 828 | }; |
| @@ -863,8 +863,8 @@ static struct resource ssc1_resources[] = { | |||
| 863 | .flags = IORESOURCE_MEM, | 863 | .flags = IORESOURCE_MEM, |
| 864 | }, | 864 | }, |
| 865 | [1] = { | 865 | [1] = { |
| 866 | .start = AT91SAM9RL_ID_SSC1, | 866 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC1, |
| 867 | .end = AT91SAM9RL_ID_SSC1, | 867 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC1, |
| 868 | .flags = IORESOURCE_IRQ, | 868 | .flags = IORESOURCE_IRQ, |
| 869 | }, | 869 | }, |
| 870 | }; | 870 | }; |
| @@ -943,8 +943,8 @@ static struct resource dbgu_resources[] = { | |||
| 943 | .flags = IORESOURCE_MEM, | 943 | .flags = IORESOURCE_MEM, |
| 944 | }, | 944 | }, |
| 945 | [1] = { | 945 | [1] = { |
| 946 | .start = AT91_ID_SYS, | 946 | .start = NR_IRQS_LEGACY + AT91_ID_SYS, |
| 947 | .end = AT91_ID_SYS, | 947 | .end = NR_IRQS_LEGACY + AT91_ID_SYS, |
| 948 | .flags = IORESOURCE_IRQ, | 948 | .flags = IORESOURCE_IRQ, |
| 949 | }, | 949 | }, |
| 950 | }; | 950 | }; |
| @@ -981,8 +981,8 @@ static struct resource uart0_resources[] = { | |||
| 981 | .flags = IORESOURCE_MEM, | 981 | .flags = IORESOURCE_MEM, |
| 982 | }, | 982 | }, |
| 983 | [1] = { | 983 | [1] = { |
| 984 | .start = AT91SAM9RL_ID_US0, | 984 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_US0, |
| 985 | .end = AT91SAM9RL_ID_US0, | 985 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_US0, |
| 986 | .flags = IORESOURCE_IRQ, | 986 | .flags = IORESOURCE_IRQ, |
| 987 | }, | 987 | }, |
| 988 | }; | 988 | }; |
| @@ -1032,8 +1032,8 @@ static struct resource uart1_resources[] = { | |||
| 1032 | .flags = IORESOURCE_MEM, | 1032 | .flags = IORESOURCE_MEM, |
| 1033 | }, | 1033 | }, |
| 1034 | [1] = { | 1034 | [1] = { |
| 1035 | .start = AT91SAM9RL_ID_US1, | 1035 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_US1, |
| 1036 | .end = AT91SAM9RL_ID_US1, | 1036 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_US1, |
| 1037 | .flags = IORESOURCE_IRQ, | 1037 | .flags = IORESOURCE_IRQ, |
| 1038 | }, | 1038 | }, |
| 1039 | }; | 1039 | }; |
| @@ -1075,8 +1075,8 @@ static struct resource uart2_resources[] = { | |||
| 1075 | .flags = IORESOURCE_MEM, | 1075 | .flags = IORESOURCE_MEM, |
| 1076 | }, | 1076 | }, |
| 1077 | [1] = { | 1077 | [1] = { |
| 1078 | .start = AT91SAM9RL_ID_US2, | 1078 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_US2, |
| 1079 | .end = AT91SAM9RL_ID_US2, | 1079 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_US2, |
| 1080 | .flags = IORESOURCE_IRQ, | 1080 | .flags = IORESOURCE_IRQ, |
| 1081 | }, | 1081 | }, |
| 1082 | }; | 1082 | }; |
| @@ -1118,8 +1118,8 @@ static struct resource uart3_resources[] = { | |||
| 1118 | .flags = IORESOURCE_MEM, | 1118 | .flags = IORESOURCE_MEM, |
| 1119 | }, | 1119 | }, |
| 1120 | [1] = { | 1120 | [1] = { |
| 1121 | .start = AT91SAM9RL_ID_US3, | 1121 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_US3, |
| 1122 | .end = AT91SAM9RL_ID_US3, | 1122 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_US3, |
| 1123 | .flags = IORESOURCE_IRQ, | 1123 | .flags = IORESOURCE_IRQ, |
| 1124 | }, | 1124 | }, |
| 1125 | }; | 1125 | }; |
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c index 1b144b4d3ce1..477cf9d06672 100644 --- a/arch/arm/mach-at91/at91sam9x5.c +++ b/arch/arm/mach-at91/at91sam9x5.c | |||
| @@ -312,8 +312,6 @@ static void __init at91sam9x5_map_io(void) | |||
| 312 | 312 | ||
| 313 | void __init at91sam9x5_initialize(void) | 313 | void __init at91sam9x5_initialize(void) |
| 314 | { | 314 | { |
| 315 | at91_extern_irq = (1 << AT91SAM9X5_ID_IRQ0); | ||
| 316 | |||
| 317 | /* Register GPIO subsystem (using DT) */ | 315 | /* Register GPIO subsystem (using DT) */ |
| 318 | at91_gpio_init(NULL, 0); | 316 | at91_gpio_init(NULL, 0); |
| 319 | } | 317 | } |
| @@ -321,47 +319,9 @@ void __init at91sam9x5_initialize(void) | |||
| 321 | /* -------------------------------------------------------------------- | 319 | /* -------------------------------------------------------------------- |
| 322 | * Interrupt initialization | 320 | * Interrupt initialization |
| 323 | * -------------------------------------------------------------------- */ | 321 | * -------------------------------------------------------------------- */ |
| 324 | /* | ||
| 325 | * The default interrupt priority levels (0 = lowest, 7 = highest). | ||
| 326 | */ | ||
| 327 | static unsigned int at91sam9x5_default_irq_priority[NR_AIC_IRQS] __initdata = { | ||
| 328 | 7, /* Advanced Interrupt Controller (FIQ) */ | ||
| 329 | 7, /* System Peripherals */ | ||
| 330 | 1, /* Parallel IO Controller A and B */ | ||
| 331 | 1, /* Parallel IO Controller C and D */ | ||
| 332 | 4, /* Soft Modem */ | ||
| 333 | 5, /* USART 0 */ | ||
| 334 | 5, /* USART 1 */ | ||
| 335 | 5, /* USART 2 */ | ||
| 336 | 5, /* USART 3 */ | ||
| 337 | 6, /* Two-Wire Interface 0 */ | ||
| 338 | 6, /* Two-Wire Interface 1 */ | ||
| 339 | 6, /* Two-Wire Interface 2 */ | ||
| 340 | 0, /* Multimedia Card Interface 0 */ | ||
| 341 | 5, /* Serial Peripheral Interface 0 */ | ||
| 342 | 5, /* Serial Peripheral Interface 1 */ | ||
| 343 | 5, /* UART 0 */ | ||
| 344 | 5, /* UART 1 */ | ||
| 345 | 0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */ | ||
| 346 | 0, /* Pulse Width Modulation Controller */ | ||
| 347 | 0, /* ADC Controller */ | ||
| 348 | 0, /* DMA Controller 0 */ | ||
| 349 | 0, /* DMA Controller 1 */ | ||
| 350 | 2, /* USB Host High Speed port */ | ||
| 351 | 2, /* USB Device High speed port */ | ||
| 352 | 3, /* Ethernet MAC 0 */ | ||
| 353 | 3, /* LDC Controller or Image Sensor Interface */ | ||
| 354 | 0, /* Multimedia Card Interface 1 */ | ||
| 355 | 3, /* Ethernet MAC 1 */ | ||
| 356 | 4, /* Synchronous Serial Interface */ | ||
| 357 | 4, /* CAN Controller 0 */ | ||
| 358 | 4, /* CAN Controller 1 */ | ||
| 359 | 0, /* Advanced Interrupt Controller (IRQ0) */ | ||
| 360 | }; | ||
| 361 | 322 | ||
| 362 | struct at91_init_soc __initdata at91sam9x5_soc = { | 323 | struct at91_init_soc __initdata at91sam9x5_soc = { |
| 363 | .map_io = at91sam9x5_map_io, | 324 | .map_io = at91sam9x5_map_io, |
| 364 | .default_irq_priority = at91sam9x5_default_irq_priority, | ||
| 365 | .register_clocks = at91sam9x5_register_clocks, | 325 | .register_clocks = at91sam9x5_register_clocks, |
| 366 | .init = at91sam9x5_initialize, | 326 | .init = at91sam9x5_initialize, |
| 367 | }; | 327 | }; |
diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c index d62fe090d814..46090e642d8e 100644 --- a/arch/arm/mach-at91/at91x40.c +++ b/arch/arm/mach-at91/at91x40.c | |||
| @@ -13,10 +13,12 @@ | |||
| 13 | #include <linux/kernel.h> | 13 | #include <linux/kernel.h> |
| 14 | #include <linux/init.h> | 14 | #include <linux/init.h> |
| 15 | #include <linux/irq.h> | 15 | #include <linux/irq.h> |
| 16 | #include <linux/io.h> | ||
| 16 | #include <asm/proc-fns.h> | 17 | #include <asm/proc-fns.h> |
| 17 | #include <asm/system_misc.h> | 18 | #include <asm/system_misc.h> |
| 18 | #include <asm/mach/arch.h> | 19 | #include <asm/mach/arch.h> |
| 19 | #include <mach/at91x40.h> | 20 | #include <mach/at91x40.h> |
| 21 | #include <mach/at91_aic.h> | ||
| 20 | #include <mach/at91_st.h> | 22 | #include <mach/at91_st.h> |
| 21 | #include <mach/timex.h> | 23 | #include <mach/timex.h> |
| 22 | #include "generic.h" | 24 | #include "generic.h" |
diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c index 271f994314a4..22d8856094f1 100644 --- a/arch/arm/mach-at91/board-1arm.c +++ b/arch/arm/mach-at91/board-1arm.c | |||
| @@ -36,6 +36,7 @@ | |||
| 36 | 36 | ||
| 37 | #include <mach/board.h> | 37 | #include <mach/board.h> |
| 38 | #include <mach/cpu.h> | 38 | #include <mach/cpu.h> |
| 39 | #include <mach/at91_aic.h> | ||
| 39 | 40 | ||
| 40 | #include "generic.h" | 41 | #include "generic.h" |
| 41 | 42 | ||
| @@ -91,6 +92,7 @@ MACHINE_START(ONEARM, "Ajeco 1ARM single board computer") | |||
| 91 | /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ | 92 | /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ |
| 92 | .timer = &at91rm9200_timer, | 93 | .timer = &at91rm9200_timer, |
| 93 | .map_io = at91_map_io, | 94 | .map_io = at91_map_io, |
| 95 | .handle_irq = at91_aic_handle_irq, | ||
| 94 | .init_early = onearm_init_early, | 96 | .init_early = onearm_init_early, |
| 95 | .init_irq = at91_init_irq_default, | 97 | .init_irq = at91_init_irq_default, |
| 96 | .init_machine = onearm_board_init, | 98 | .init_machine = onearm_board_init, |
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c index b7d8aa7b81e6..de7be1931817 100644 --- a/arch/arm/mach-at91/board-afeb-9260v1.c +++ b/arch/arm/mach-at91/board-afeb-9260v1.c | |||
| @@ -44,6 +44,7 @@ | |||
| 44 | #include <asm/mach/irq.h> | 44 | #include <asm/mach/irq.h> |
| 45 | 45 | ||
| 46 | #include <mach/board.h> | 46 | #include <mach/board.h> |
| 47 | #include <mach/at91_aic.h> | ||
| 47 | 48 | ||
| 48 | #include "generic.h" | 49 | #include "generic.h" |
| 49 | 50 | ||
| @@ -212,6 +213,7 @@ MACHINE_START(AFEB9260, "Custom afeb9260 board") | |||
| 212 | /* Maintainer: Sergey Lapin <slapin@ossfans.org> */ | 213 | /* Maintainer: Sergey Lapin <slapin@ossfans.org> */ |
| 213 | .timer = &at91sam926x_timer, | 214 | .timer = &at91sam926x_timer, |
| 214 | .map_io = at91_map_io, | 215 | .map_io = at91_map_io, |
| 216 | .handle_irq = at91_aic_handle_irq, | ||
| 215 | .init_early = afeb9260_init_early, | 217 | .init_early = afeb9260_init_early, |
| 216 | .init_irq = at91_init_irq_default, | 218 | .init_irq = at91_init_irq_default, |
| 217 | .init_machine = afeb9260_board_init, | 219 | .init_machine = afeb9260_board_init, |
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c index 29d3ef0a50fb..477e708497bc 100644 --- a/arch/arm/mach-at91/board-cam60.c +++ b/arch/arm/mach-at91/board-cam60.c | |||
| @@ -39,6 +39,7 @@ | |||
| 39 | #include <asm/mach/irq.h> | 39 | #include <asm/mach/irq.h> |
| 40 | 40 | ||
| 41 | #include <mach/board.h> | 41 | #include <mach/board.h> |
| 42 | #include <mach/at91_aic.h> | ||
| 42 | #include <mach/at91sam9_smc.h> | 43 | #include <mach/at91sam9_smc.h> |
| 43 | 44 | ||
| 44 | #include "sam9_smc.h" | 45 | #include "sam9_smc.h" |
| @@ -188,6 +189,7 @@ MACHINE_START(CAM60, "KwikByte CAM60") | |||
| 188 | /* Maintainer: KwikByte */ | 189 | /* Maintainer: KwikByte */ |
| 189 | .timer = &at91sam926x_timer, | 190 | .timer = &at91sam926x_timer, |
| 190 | .map_io = at91_map_io, | 191 | .map_io = at91_map_io, |
| 192 | .handle_irq = at91_aic_handle_irq, | ||
| 191 | .init_early = cam60_init_early, | 193 | .init_early = cam60_init_early, |
| 192 | .init_irq = at91_init_irq_default, | 194 | .init_irq = at91_init_irq_default, |
| 193 | .init_machine = cam60_board_init, | 195 | .init_machine = cam60_board_init, |
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c index 44328a6d4609..a5b002f32a61 100644 --- a/arch/arm/mach-at91/board-carmeva.c +++ b/arch/arm/mach-at91/board-carmeva.c | |||
| @@ -36,6 +36,7 @@ | |||
| 36 | 36 | ||
| 37 | #include <mach/hardware.h> | 37 | #include <mach/hardware.h> |
| 38 | #include <mach/board.h> | 38 | #include <mach/board.h> |
| 39 | #include <mach/at91_aic.h> | ||
| 39 | 40 | ||
| 40 | #include "generic.h" | 41 | #include "generic.h" |
| 41 | 42 | ||
| @@ -158,6 +159,7 @@ MACHINE_START(CARMEVA, "Carmeva") | |||
| 158 | /* Maintainer: Conitec Datasystems */ | 159 | /* Maintainer: Conitec Datasystems */ |
| 159 | .timer = &at91rm9200_timer, | 160 | .timer = &at91rm9200_timer, |
| 160 | .map_io = at91_map_io, | 161 | .map_io = at91_map_io, |
| 162 | .handle_irq = at91_aic_handle_irq, | ||
| 161 | .init_early = carmeva_init_early, | 163 | .init_early = carmeva_init_early, |
| 162 | .init_irq = at91_init_irq_default, | 164 | .init_irq = at91_init_irq_default, |
| 163 | .init_machine = carmeva_board_init, | 165 | .init_machine = carmeva_board_init, |
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c index 69951ec7dbf3..ecbc13b594de 100644 --- a/arch/arm/mach-at91/board-cpu9krea.c +++ b/arch/arm/mach-at91/board-cpu9krea.c | |||
| @@ -41,6 +41,7 @@ | |||
| 41 | 41 | ||
| 42 | #include <mach/hardware.h> | 42 | #include <mach/hardware.h> |
| 43 | #include <mach/board.h> | 43 | #include <mach/board.h> |
| 44 | #include <mach/at91_aic.h> | ||
| 44 | #include <mach/at91sam9_smc.h> | 45 | #include <mach/at91sam9_smc.h> |
| 45 | #include <mach/at91sam9260_matrix.h> | 46 | #include <mach/at91sam9260_matrix.h> |
| 46 | #include <mach/at91_matrix.h> | 47 | #include <mach/at91_matrix.h> |
| @@ -376,6 +377,7 @@ MACHINE_START(CPUAT9G20, "Eukrea CPU9G20") | |||
| 376 | /* Maintainer: Eric Benard - EUKREA Electromatique */ | 377 | /* Maintainer: Eric Benard - EUKREA Electromatique */ |
| 377 | .timer = &at91sam926x_timer, | 378 | .timer = &at91sam926x_timer, |
| 378 | .map_io = at91_map_io, | 379 | .map_io = at91_map_io, |
| 380 | .handle_irq = at91_aic_handle_irq, | ||
| 379 | .init_early = cpu9krea_init_early, | 381 | .init_early = cpu9krea_init_early, |
| 380 | .init_irq = at91_init_irq_default, | 382 | .init_irq = at91_init_irq_default, |
| 381 | .init_machine = cpu9krea_board_init, | 383 | .init_machine = cpu9krea_board_init, |
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c index 895cf2dba612..2e6d043c82f2 100644 --- a/arch/arm/mach-at91/board-cpuat91.c +++ b/arch/arm/mach-at91/board-cpuat91.c | |||
| @@ -37,6 +37,7 @@ | |||
| 37 | #include <asm/mach/irq.h> | 37 | #include <asm/mach/irq.h> |
| 38 | 38 | ||
| 39 | #include <mach/board.h> | 39 | #include <mach/board.h> |
| 40 | #include <mach/at91_aic.h> | ||
| 40 | #include <mach/at91rm9200_mc.h> | 41 | #include <mach/at91rm9200_mc.h> |
| 41 | #include <mach/at91_ramc.h> | 42 | #include <mach/at91_ramc.h> |
| 42 | #include <mach/cpu.h> | 43 | #include <mach/cpu.h> |
| @@ -178,6 +179,7 @@ MACHINE_START(CPUAT91, "Eukrea") | |||
| 178 | /* Maintainer: Eric Benard - EUKREA Electromatique */ | 179 | /* Maintainer: Eric Benard - EUKREA Electromatique */ |
| 179 | .timer = &at91rm9200_timer, | 180 | .timer = &at91rm9200_timer, |
| 180 | .map_io = at91_map_io, | 181 | .map_io = at91_map_io, |
| 182 | .handle_irq = at91_aic_handle_irq, | ||
| 181 | .init_early = cpuat91_init_early, | 183 | .init_early = cpuat91_init_early, |
| 182 | .init_irq = at91_init_irq_default, | 184 | .init_irq = at91_init_irq_default, |
| 183 | .init_machine = cpuat91_board_init, | 185 | .init_machine = cpuat91_board_init, |
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c index cd813361cd26..462bc319cbc5 100644 --- a/arch/arm/mach-at91/board-csb337.c +++ b/arch/arm/mach-at91/board-csb337.c | |||
| @@ -39,6 +39,7 @@ | |||
| 39 | 39 | ||
| 40 | #include <mach/hardware.h> | 40 | #include <mach/hardware.h> |
| 41 | #include <mach/board.h> | 41 | #include <mach/board.h> |
| 42 | #include <mach/at91_aic.h> | ||
| 42 | 43 | ||
| 43 | #include "generic.h" | 44 | #include "generic.h" |
| 44 | 45 | ||
| @@ -252,6 +253,7 @@ MACHINE_START(CSB337, "Cogent CSB337") | |||
| 252 | /* Maintainer: Bill Gatliff */ | 253 | /* Maintainer: Bill Gatliff */ |
| 253 | .timer = &at91rm9200_timer, | 254 | .timer = &at91rm9200_timer, |
| 254 | .map_io = at91_map_io, | 255 | .map_io = at91_map_io, |
| 256 | .handle_irq = at91_aic_handle_irq, | ||
| 255 | .init_early = csb337_init_early, | 257 | .init_early = csb337_init_early, |
| 256 | .init_irq = at91_init_irq_default, | 258 | .init_irq = at91_init_irq_default, |
| 257 | .init_machine = csb337_board_init, | 259 | .init_machine = csb337_board_init, |
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c index 7c8b05a57d7f..872871ab1160 100644 --- a/arch/arm/mach-at91/board-csb637.c +++ b/arch/arm/mach-at91/board-csb637.c | |||
| @@ -36,6 +36,7 @@ | |||
| 36 | 36 | ||
| 37 | #include <mach/hardware.h> | 37 | #include <mach/hardware.h> |
| 38 | #include <mach/board.h> | 38 | #include <mach/board.h> |
| 39 | #include <mach/at91_aic.h> | ||
| 39 | 40 | ||
| 40 | #include "generic.h" | 41 | #include "generic.h" |
| 41 | 42 | ||
| @@ -133,6 +134,7 @@ MACHINE_START(CSB637, "Cogent CSB637") | |||
| 133 | /* Maintainer: Bill Gatliff */ | 134 | /* Maintainer: Bill Gatliff */ |
| 134 | .timer = &at91rm9200_timer, | 135 | .timer = &at91rm9200_timer, |
| 135 | .map_io = at91_map_io, | 136 | .map_io = at91_map_io, |
| 137 | .handle_irq = at91_aic_handle_irq, | ||
| 136 | .init_early = csb637_init_early, | 138 | .init_early = csb637_init_early, |
| 137 | .init_irq = at91_init_irq_default, | 139 | .init_irq = at91_init_irq_default, |
| 138 | .init_machine = csb637_board_init, | 140 | .init_machine = csb637_board_init, |
diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c index a1fce05aa7a5..e8f45c4e0ea8 100644 --- a/arch/arm/mach-at91/board-dt.c +++ b/arch/arm/mach-at91/board-dt.c | |||
| @@ -16,6 +16,7 @@ | |||
| 16 | #include <linux/of_platform.h> | 16 | #include <linux/of_platform.h> |
| 17 | 17 | ||
| 18 | #include <mach/board.h> | 18 | #include <mach/board.h> |
| 19 | #include <mach/at91_aic.h> | ||
| 19 | 20 | ||
| 20 | #include <asm/setup.h> | 21 | #include <asm/setup.h> |
| 21 | #include <asm/irq.h> | 22 | #include <asm/irq.h> |
| @@ -53,6 +54,7 @@ DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)") | |||
| 53 | /* Maintainer: Atmel */ | 54 | /* Maintainer: Atmel */ |
| 54 | .timer = &at91sam926x_timer, | 55 | .timer = &at91sam926x_timer, |
| 55 | .map_io = at91_map_io, | 56 | .map_io = at91_map_io, |
| 57 | .handle_irq = at91_aic_handle_irq, | ||
| 56 | .init_early = at91_dt_initialize, | 58 | .init_early = at91_dt_initialize, |
| 57 | .init_irq = at91_dt_init_irq, | 59 | .init_irq = at91_dt_init_irq, |
| 58 | .init_machine = at91_dt_device_init, | 60 | .init_machine = at91_dt_device_init, |
diff --git a/arch/arm/mach-at91/board-eb01.c b/arch/arm/mach-at91/board-eb01.c index d2023f27c652..01f66e99ece7 100644 --- a/arch/arm/mach-at91/board-eb01.c +++ b/arch/arm/mach-at91/board-eb01.c | |||
| @@ -28,6 +28,7 @@ | |||
| 28 | #include <asm/mach/arch.h> | 28 | #include <asm/mach/arch.h> |
| 29 | #include <asm/mach/map.h> | 29 | #include <asm/mach/map.h> |
| 30 | #include <mach/board.h> | 30 | #include <mach/board.h> |
| 31 | #include <mach/at91_aic.h> | ||
| 31 | #include "generic.h" | 32 | #include "generic.h" |
| 32 | 33 | ||
| 33 | static void __init at91eb01_init_irq(void) | 34 | static void __init at91eb01_init_irq(void) |
| @@ -43,6 +44,7 @@ static void __init at91eb01_init_early(void) | |||
| 43 | MACHINE_START(AT91EB01, "Atmel AT91 EB01") | 44 | MACHINE_START(AT91EB01, "Atmel AT91 EB01") |
| 44 | /* Maintainer: Greg Ungerer <gerg@snapgear.com> */ | 45 | /* Maintainer: Greg Ungerer <gerg@snapgear.com> */ |
| 45 | .timer = &at91x40_timer, | 46 | .timer = &at91x40_timer, |
| 47 | .handle_irq = at91_aic_handle_irq, | ||
| 46 | .init_early = at91eb01_init_early, | 48 | .init_early = at91eb01_init_early, |
| 47 | .init_irq = at91eb01_init_irq, | 49 | .init_irq = at91eb01_init_irq, |
| 48 | MACHINE_END | 50 | MACHINE_END |
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c index bd1017297989..d1e1f3fc0a47 100644 --- a/arch/arm/mach-at91/board-eb9200.c +++ b/arch/arm/mach-at91/board-eb9200.c | |||
| @@ -36,6 +36,7 @@ | |||
| 36 | #include <asm/mach/irq.h> | 36 | #include <asm/mach/irq.h> |
| 37 | 37 | ||
| 38 | #include <mach/board.h> | 38 | #include <mach/board.h> |
| 39 | #include <mach/at91_aic.h> | ||
| 39 | 40 | ||
| 40 | #include "generic.h" | 41 | #include "generic.h" |
| 41 | 42 | ||
| @@ -118,6 +119,7 @@ static void __init eb9200_board_init(void) | |||
| 118 | MACHINE_START(ATEB9200, "Embest ATEB9200") | 119 | MACHINE_START(ATEB9200, "Embest ATEB9200") |
| 119 | .timer = &at91rm9200_timer, | 120 | .timer = &at91rm9200_timer, |
| 120 | .map_io = at91_map_io, | 121 | .map_io = at91_map_io, |
| 122 | .handle_irq = at91_aic_handle_irq, | ||
| 121 | .init_early = eb9200_init_early, | 123 | .init_early = eb9200_init_early, |
| 122 | .init_irq = at91_init_irq_default, | 124 | .init_irq = at91_init_irq_default, |
| 123 | .init_machine = eb9200_board_init, | 125 | .init_machine = eb9200_board_init, |
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c index 89cc3726a9ce..9c24cb25707c 100644 --- a/arch/arm/mach-at91/board-ecbat91.c +++ b/arch/arm/mach-at91/board-ecbat91.c | |||
| @@ -39,6 +39,7 @@ | |||
| 39 | 39 | ||
| 40 | #include <mach/board.h> | 40 | #include <mach/board.h> |
| 41 | #include <mach/cpu.h> | 41 | #include <mach/cpu.h> |
| 42 | #include <mach/at91_aic.h> | ||
| 42 | 43 | ||
| 43 | #include "generic.h" | 44 | #include "generic.h" |
| 44 | 45 | ||
| @@ -170,6 +171,7 @@ MACHINE_START(ECBAT91, "emQbit's ECB_AT91") | |||
| 170 | /* Maintainer: emQbit.com */ | 171 | /* Maintainer: emQbit.com */ |
| 171 | .timer = &at91rm9200_timer, | 172 | .timer = &at91rm9200_timer, |
| 172 | .map_io = at91_map_io, | 173 | .map_io = at91_map_io, |
| 174 | .handle_irq = at91_aic_handle_irq, | ||
| 173 | .init_early = ecb_at91init_early, | 175 | .init_early = ecb_at91init_early, |
| 174 | .init_irq = at91_init_irq_default, | 176 | .init_irq = at91_init_irq_default, |
| 175 | .init_machine = ecb_at91board_init, | 177 | .init_machine = ecb_at91board_init, |
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c index 558546cf63f4..82bdfde3405f 100644 --- a/arch/arm/mach-at91/board-eco920.c +++ b/arch/arm/mach-at91/board-eco920.c | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | #include <asm/mach/map.h> | 25 | #include <asm/mach/map.h> |
| 26 | 26 | ||
| 27 | #include <mach/board.h> | 27 | #include <mach/board.h> |
| 28 | #include <mach/at91_aic.h> | ||
| 28 | #include <mach/at91rm9200_mc.h> | 29 | #include <mach/at91rm9200_mc.h> |
| 29 | #include <mach/at91_ramc.h> | 30 | #include <mach/at91_ramc.h> |
| 30 | #include <mach/cpu.h> | 31 | #include <mach/cpu.h> |
| @@ -132,6 +133,7 @@ MACHINE_START(ECO920, "eco920") | |||
| 132 | /* Maintainer: Sascha Hauer */ | 133 | /* Maintainer: Sascha Hauer */ |
| 133 | .timer = &at91rm9200_timer, | 134 | .timer = &at91rm9200_timer, |
| 134 | .map_io = at91_map_io, | 135 | .map_io = at91_map_io, |
| 136 | .handle_irq = at91_aic_handle_irq, | ||
| 135 | .init_early = eco920_init_early, | 137 | .init_early = eco920_init_early, |
| 136 | .init_irq = at91_init_irq_default, | 138 | .init_irq = at91_init_irq_default, |
| 137 | .init_machine = eco920_board_init, | 139 | .init_machine = eco920_board_init, |
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c index 47658f78105d..6cc83a87d77c 100644 --- a/arch/arm/mach-at91/board-flexibity.c +++ b/arch/arm/mach-at91/board-flexibity.c | |||
| @@ -34,6 +34,7 @@ | |||
| 34 | 34 | ||
| 35 | #include <mach/hardware.h> | 35 | #include <mach/hardware.h> |
| 36 | #include <mach/board.h> | 36 | #include <mach/board.h> |
| 37 | #include <mach/at91_aic.h> | ||
| 37 | 38 | ||
| 38 | #include "generic.h" | 39 | #include "generic.h" |
| 39 | 40 | ||
| @@ -160,6 +161,7 @@ MACHINE_START(FLEXIBITY, "Flexibity Connect") | |||
| 160 | /* Maintainer: Maxim Osipov */ | 161 | /* Maintainer: Maxim Osipov */ |
| 161 | .timer = &at91sam926x_timer, | 162 | .timer = &at91sam926x_timer, |
| 162 | .map_io = at91_map_io, | 163 | .map_io = at91_map_io, |
| 164 | .handle_irq = at91_aic_handle_irq, | ||
| 163 | .init_early = flexibity_init_early, | 165 | .init_early = flexibity_init_early, |
| 164 | .init_irq = at91_init_irq_default, | 166 | .init_irq = at91_init_irq_default, |
| 165 | .init_machine = flexibity_board_init, | 167 | .init_machine = flexibity_board_init, |
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c index 33411e6ecb1f..69ab1247ef81 100644 --- a/arch/arm/mach-at91/board-foxg20.c +++ b/arch/arm/mach-at91/board-foxg20.c | |||
| @@ -42,6 +42,7 @@ | |||
| 42 | #include <asm/mach/irq.h> | 42 | #include <asm/mach/irq.h> |
| 43 | 43 | ||
| 44 | #include <mach/board.h> | 44 | #include <mach/board.h> |
| 45 | #include <mach/at91_aic.h> | ||
| 45 | #include <mach/at91sam9_smc.h> | 46 | #include <mach/at91sam9_smc.h> |
| 46 | 47 | ||
| 47 | #include "sam9_smc.h" | 48 | #include "sam9_smc.h" |
| @@ -262,6 +263,7 @@ MACHINE_START(ACMENETUSFOXG20, "Acme Systems srl FOX Board G20") | |||
| 262 | /* Maintainer: Sergio Tanzilli */ | 263 | /* Maintainer: Sergio Tanzilli */ |
| 263 | .timer = &at91sam926x_timer, | 264 | .timer = &at91sam926x_timer, |
| 264 | .map_io = at91_map_io, | 265 | .map_io = at91_map_io, |
| 266 | .handle_irq = at91_aic_handle_irq, | ||
| 265 | .init_early = foxg20_init_early, | 267 | .init_early = foxg20_init_early, |
| 266 | .init_irq = at91_init_irq_default, | 268 | .init_irq = at91_init_irq_default, |
| 267 | .init_machine = foxg20_board_init, | 269 | .init_machine = foxg20_board_init, |
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c index 3e0dfa643a86..a9d5e78118c5 100644 --- a/arch/arm/mach-at91/board-gsia18s.c +++ b/arch/arm/mach-at91/board-gsia18s.c | |||
| @@ -31,6 +31,7 @@ | |||
| 31 | #include <asm/mach/arch.h> | 31 | #include <asm/mach/arch.h> |
| 32 | 32 | ||
| 33 | #include <mach/board.h> | 33 | #include <mach/board.h> |
| 34 | #include <mach/at91_aic.h> | ||
| 34 | #include <mach/at91sam9_smc.h> | 35 | #include <mach/at91sam9_smc.h> |
| 35 | #include <mach/gsia18s.h> | 36 | #include <mach/gsia18s.h> |
| 36 | #include <mach/stamp9g20.h> | 37 | #include <mach/stamp9g20.h> |
| @@ -575,6 +576,7 @@ static void __init gsia18s_board_init(void) | |||
| 575 | MACHINE_START(GSIA18S, "GS_IA18_S") | 576 | MACHINE_START(GSIA18S, "GS_IA18_S") |
| 576 | .timer = &at91sam926x_timer, | 577 | .timer = &at91sam926x_timer, |
| 577 | .map_io = at91_map_io, | 578 | .map_io = at91_map_io, |
| 579 | .handle_irq = at91_aic_handle_irq, | ||
| 578 | .init_early = gsia18s_init_early, | 580 | .init_early = gsia18s_init_early, |
| 579 | .init_irq = at91_init_irq_default, | 581 | .init_irq = at91_init_irq_default, |
| 580 | .init_machine = gsia18s_board_init, | 582 | .init_machine = gsia18s_board_init, |
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c index f260657f32bc..64c1dbf88a07 100644 --- a/arch/arm/mach-at91/board-kafa.c +++ b/arch/arm/mach-at91/board-kafa.c | |||
| @@ -35,6 +35,7 @@ | |||
| 35 | #include <asm/mach/irq.h> | 35 | #include <asm/mach/irq.h> |
| 36 | 36 | ||
| 37 | #include <mach/board.h> | 37 | #include <mach/board.h> |
| 38 | #include <mach/at91_aic.h> | ||
| 38 | #include <mach/cpu.h> | 39 | #include <mach/cpu.h> |
| 39 | 40 | ||
| 40 | #include "generic.h" | 41 | #include "generic.h" |
| @@ -93,6 +94,7 @@ MACHINE_START(KAFA, "Sperry-Sun KAFA") | |||
| 93 | /* Maintainer: Sergei Sharonov */ | 94 | /* Maintainer: Sergei Sharonov */ |
| 94 | .timer = &at91rm9200_timer, | 95 | .timer = &at91rm9200_timer, |
| 95 | .map_io = at91_map_io, | 96 | .map_io = at91_map_io, |
| 97 | .handle_irq = at91_aic_handle_irq, | ||
| 96 | .init_early = kafa_init_early, | 98 | .init_early = kafa_init_early, |
| 97 | .init_irq = at91_init_irq_default, | 99 | .init_irq = at91_init_irq_default, |
| 98 | .init_machine = kafa_board_init, | 100 | .init_machine = kafa_board_init, |
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c index ba39db5482b9..5d96cb85175f 100644 --- a/arch/arm/mach-at91/board-kb9202.c +++ b/arch/arm/mach-at91/board-kb9202.c | |||
| @@ -37,6 +37,7 @@ | |||
| 37 | 37 | ||
| 38 | #include <mach/board.h> | 38 | #include <mach/board.h> |
| 39 | #include <mach/cpu.h> | 39 | #include <mach/cpu.h> |
| 40 | #include <mach/at91_aic.h> | ||
| 40 | #include <mach/at91rm9200_mc.h> | 41 | #include <mach/at91rm9200_mc.h> |
| 41 | #include <mach/at91_ramc.h> | 42 | #include <mach/at91_ramc.h> |
| 42 | 43 | ||
| @@ -133,6 +134,7 @@ MACHINE_START(KB9200, "KB920x") | |||
| 133 | /* Maintainer: KwikByte, Inc. */ | 134 | /* Maintainer: KwikByte, Inc. */ |
| 134 | .timer = &at91rm9200_timer, | 135 | .timer = &at91rm9200_timer, |
| 135 | .map_io = at91_map_io, | 136 | .map_io = at91_map_io, |
| 137 | .handle_irq = at91_aic_handle_irq, | ||
| 136 | .init_early = kb9202_init_early, | 138 | .init_early = kb9202_init_early, |
| 137 | .init_irq = at91_init_irq_default, | 139 | .init_irq = at91_init_irq_default, |
| 138 | .init_machine = kb9202_board_init, | 140 | .init_machine = kb9202_board_init, |
diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c index d2f4cc161766..18103c5d993c 100644 --- a/arch/arm/mach-at91/board-neocore926.c +++ b/arch/arm/mach-at91/board-neocore926.c | |||
| @@ -45,6 +45,7 @@ | |||
| 45 | 45 | ||
| 46 | #include <mach/hardware.h> | 46 | #include <mach/hardware.h> |
| 47 | #include <mach/board.h> | 47 | #include <mach/board.h> |
| 48 | #include <mach/at91_aic.h> | ||
| 48 | #include <mach/at91sam9_smc.h> | 49 | #include <mach/at91sam9_smc.h> |
| 49 | 50 | ||
| 50 | #include "sam9_smc.h" | 51 | #include "sam9_smc.h" |
| @@ -378,6 +379,7 @@ MACHINE_START(NEOCORE926, "ADENEO NEOCORE 926") | |||
| 378 | /* Maintainer: ADENEO */ | 379 | /* Maintainer: ADENEO */ |
| 379 | .timer = &at91sam926x_timer, | 380 | .timer = &at91sam926x_timer, |
| 380 | .map_io = at91_map_io, | 381 | .map_io = at91_map_io, |
| 382 | .handle_irq = at91_aic_handle_irq, | ||
| 381 | .init_early = neocore926_init_early, | 383 | .init_early = neocore926_init_early, |
| 382 | .init_irq = at91_init_irq_default, | 384 | .init_irq = at91_init_irq_default, |
| 383 | .init_machine = neocore926_board_init, | 385 | .init_machine = neocore926_board_init, |
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c index 7fe638342421..9ca3e32c54cb 100644 --- a/arch/arm/mach-at91/board-pcontrol-g20.c +++ b/arch/arm/mach-at91/board-pcontrol-g20.c | |||
| @@ -30,6 +30,7 @@ | |||
| 30 | #include <asm/mach/arch.h> | 30 | #include <asm/mach/arch.h> |
| 31 | 31 | ||
| 32 | #include <mach/board.h> | 32 | #include <mach/board.h> |
| 33 | #include <mach/at91_aic.h> | ||
| 33 | #include <mach/at91sam9_smc.h> | 34 | #include <mach/at91sam9_smc.h> |
| 34 | #include <mach/stamp9g20.h> | 35 | #include <mach/stamp9g20.h> |
| 35 | 36 | ||
| @@ -218,6 +219,7 @@ MACHINE_START(PCONTROL_G20, "PControl G20") | |||
| 218 | /* Maintainer: pgsellmann@portner-elektronik.at */ | 219 | /* Maintainer: pgsellmann@portner-elektronik.at */ |
| 219 | .timer = &at91sam926x_timer, | 220 | .timer = &at91sam926x_timer, |
| 220 | .map_io = at91_map_io, | 221 | .map_io = at91_map_io, |
| 222 | .handle_irq = at91_aic_handle_irq, | ||
| 221 | .init_early = pcontrol_g20_init_early, | 223 | .init_early = pcontrol_g20_init_early, |
| 222 | .init_irq = at91_init_irq_default, | 224 | .init_irq = at91_init_irq_default, |
| 223 | .init_machine = pcontrol_g20_board_init, | 225 | .init_machine = pcontrol_g20_board_init, |
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c index b45c0a5d5ca7..127065504508 100644 --- a/arch/arm/mach-at91/board-picotux200.c +++ b/arch/arm/mach-at91/board-picotux200.c | |||
| @@ -38,6 +38,7 @@ | |||
| 38 | #include <asm/mach/irq.h> | 38 | #include <asm/mach/irq.h> |
| 39 | 39 | ||
| 40 | #include <mach/board.h> | 40 | #include <mach/board.h> |
| 41 | #include <mach/at91_aic.h> | ||
| 41 | #include <mach/at91rm9200_mc.h> | 42 | #include <mach/at91rm9200_mc.h> |
| 42 | #include <mach/at91_ramc.h> | 43 | #include <mach/at91_ramc.h> |
| 43 | 44 | ||
| @@ -120,6 +121,7 @@ MACHINE_START(PICOTUX2XX, "picotux 200") | |||
| 120 | /* Maintainer: Kleinhenz Elektronik GmbH */ | 121 | /* Maintainer: Kleinhenz Elektronik GmbH */ |
| 121 | .timer = &at91rm9200_timer, | 122 | .timer = &at91rm9200_timer, |
| 122 | .map_io = at91_map_io, | 123 | .map_io = at91_map_io, |
| 124 | .handle_irq = at91_aic_handle_irq, | ||
| 123 | .init_early = picotux200_init_early, | 125 | .init_early = picotux200_init_early, |
| 124 | .init_irq = at91_init_irq_default, | 126 | .init_irq = at91_init_irq_default, |
| 125 | .init_machine = picotux200_board_init, | 127 | .init_machine = picotux200_board_init, |
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c index 0c61bf0d272c..bf351e285422 100644 --- a/arch/arm/mach-at91/board-qil-a9260.c +++ b/arch/arm/mach-at91/board-qil-a9260.c | |||
| @@ -41,6 +41,7 @@ | |||
| 41 | 41 | ||
| 42 | #include <mach/hardware.h> | 42 | #include <mach/hardware.h> |
| 43 | #include <mach/board.h> | 43 | #include <mach/board.h> |
| 44 | #include <mach/at91_aic.h> | ||
| 44 | #include <mach/at91sam9_smc.h> | 45 | #include <mach/at91sam9_smc.h> |
| 45 | #include <mach/at91_shdwc.h> | 46 | #include <mach/at91_shdwc.h> |
| 46 | 47 | ||
| @@ -258,6 +259,7 @@ MACHINE_START(QIL_A9260, "CALAO QIL_A9260") | |||
| 258 | /* Maintainer: calao-systems */ | 259 | /* Maintainer: calao-systems */ |
| 259 | .timer = &at91sam926x_timer, | 260 | .timer = &at91sam926x_timer, |
| 260 | .map_io = at91_map_io, | 261 | .map_io = at91_map_io, |
| 262 | .handle_irq = at91_aic_handle_irq, | ||
| 261 | .init_early = ek_init_early, | 263 | .init_early = ek_init_early, |
| 262 | .init_irq = at91_init_irq_default, | 264 | .init_irq = at91_init_irq_default, |
| 263 | .init_machine = ek_board_init, | 265 | .init_machine = ek_board_init, |
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c index afd7a4713766..cc2bf9796073 100644 --- a/arch/arm/mach-at91/board-rm9200dk.c +++ b/arch/arm/mach-at91/board-rm9200dk.c | |||
| @@ -40,6 +40,7 @@ | |||
| 40 | 40 | ||
| 41 | #include <mach/hardware.h> | 41 | #include <mach/hardware.h> |
| 42 | #include <mach/board.h> | 42 | #include <mach/board.h> |
| 43 | #include <mach/at91_aic.h> | ||
| 43 | #include <mach/at91rm9200_mc.h> | 44 | #include <mach/at91rm9200_mc.h> |
| 44 | #include <mach/at91_ramc.h> | 45 | #include <mach/at91_ramc.h> |
| 45 | 46 | ||
| @@ -223,6 +224,7 @@ MACHINE_START(AT91RM9200DK, "Atmel AT91RM9200-DK") | |||
| 223 | /* Maintainer: SAN People/Atmel */ | 224 | /* Maintainer: SAN People/Atmel */ |
| 224 | .timer = &at91rm9200_timer, | 225 | .timer = &at91rm9200_timer, |
| 225 | .map_io = at91_map_io, | 226 | .map_io = at91_map_io, |
| 227 | .handle_irq = at91_aic_handle_irq, | ||
| 226 | .init_early = dk_init_early, | 228 | .init_early = dk_init_early, |
| 227 | .init_irq = at91_init_irq_default, | 229 | .init_irq = at91_init_irq_default, |
| 228 | .init_machine = dk_board_init, | 230 | .init_machine = dk_board_init, |
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c index 2b15b8adec4c..62e19e64c9d3 100644 --- a/arch/arm/mach-at91/board-rm9200ek.c +++ b/arch/arm/mach-at91/board-rm9200ek.c | |||
| @@ -40,6 +40,7 @@ | |||
| 40 | 40 | ||
| 41 | #include <mach/hardware.h> | 41 | #include <mach/hardware.h> |
| 42 | #include <mach/board.h> | 42 | #include <mach/board.h> |
| 43 | #include <mach/at91_aic.h> | ||
| 43 | #include <mach/at91rm9200_mc.h> | 44 | #include <mach/at91rm9200_mc.h> |
| 44 | #include <mach/at91_ramc.h> | 45 | #include <mach/at91_ramc.h> |
| 45 | 46 | ||
| @@ -190,6 +191,7 @@ MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK") | |||
| 190 | /* Maintainer: SAN People/Atmel */ | 191 | /* Maintainer: SAN People/Atmel */ |
| 191 | .timer = &at91rm9200_timer, | 192 | .timer = &at91rm9200_timer, |
| 192 | .map_io = at91_map_io, | 193 | .map_io = at91_map_io, |
| 194 | .handle_irq = at91_aic_handle_irq, | ||
| 193 | .init_early = ek_init_early, | 195 | .init_early = ek_init_early, |
| 194 | .init_irq = at91_init_irq_default, | 196 | .init_irq = at91_init_irq_default, |
| 195 | .init_machine = ek_board_init, | 197 | .init_machine = ek_board_init, |
diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c index 24ab9be7510f..c3b43aefdb75 100644 --- a/arch/arm/mach-at91/board-rsi-ews.c +++ b/arch/arm/mach-at91/board-rsi-ews.c | |||
| @@ -26,6 +26,7 @@ | |||
| 26 | 26 | ||
| 27 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
| 28 | #include <mach/board.h> | 28 | #include <mach/board.h> |
| 29 | #include <mach/at91_aic.h> | ||
| 29 | 30 | ||
| 30 | #include <linux/gpio.h> | 31 | #include <linux/gpio.h> |
| 31 | 32 | ||
| @@ -225,6 +226,7 @@ MACHINE_START(RSI_EWS, "RSI EWS") | |||
| 225 | /* Maintainer: Josef Holzmayr <holzmayr@rsi-elektrotechnik.de> */ | 226 | /* Maintainer: Josef Holzmayr <holzmayr@rsi-elektrotechnik.de> */ |
| 226 | .timer = &at91rm9200_timer, | 227 | .timer = &at91rm9200_timer, |
| 227 | .map_io = at91_map_io, | 228 | .map_io = at91_map_io, |
| 229 | .handle_irq = at91_aic_handle_irq, | ||
| 228 | .init_early = rsi_ews_init_early, | 230 | .init_early = rsi_ews_init_early, |
| 229 | .init_irq = at91_init_irq_default, | 231 | .init_irq = at91_init_irq_default, |
| 230 | .init_machine = rsi_ews_board_init, | 232 | .init_machine = rsi_ews_board_init, |
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c index cdd21f2595d2..7bf6da70d7d5 100644 --- a/arch/arm/mach-at91/board-sam9-l9260.c +++ b/arch/arm/mach-at91/board-sam9-l9260.c | |||
| @@ -38,6 +38,7 @@ | |||
| 38 | #include <asm/mach/irq.h> | 38 | #include <asm/mach/irq.h> |
| 39 | 39 | ||
| 40 | #include <mach/board.h> | 40 | #include <mach/board.h> |
| 41 | #include <mach/at91_aic.h> | ||
| 41 | #include <mach/at91sam9_smc.h> | 42 | #include <mach/at91sam9_smc.h> |
| 42 | 43 | ||
| 43 | #include "sam9_smc.h" | 44 | #include "sam9_smc.h" |
| @@ -202,6 +203,7 @@ MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260") | |||
| 202 | /* Maintainer: Olimex */ | 203 | /* Maintainer: Olimex */ |
| 203 | .timer = &at91sam926x_timer, | 204 | .timer = &at91sam926x_timer, |
| 204 | .map_io = at91_map_io, | 205 | .map_io = at91_map_io, |
| 206 | .handle_irq = at91_aic_handle_irq, | ||
| 205 | .init_early = ek_init_early, | 207 | .init_early = ek_init_early, |
| 206 | .init_irq = at91_init_irq_default, | 208 | .init_irq = at91_init_irq_default, |
| 207 | .init_machine = ek_board_init, | 209 | .init_machine = ek_board_init, |
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c index 7b3c3913551a..889c1bf71eb5 100644 --- a/arch/arm/mach-at91/board-sam9260ek.c +++ b/arch/arm/mach-at91/board-sam9260ek.c | |||
| @@ -42,6 +42,7 @@ | |||
| 42 | 42 | ||
| 43 | #include <mach/hardware.h> | 43 | #include <mach/hardware.h> |
| 44 | #include <mach/board.h> | 44 | #include <mach/board.h> |
| 45 | #include <mach/at91_aic.h> | ||
| 45 | #include <mach/at91sam9_smc.h> | 46 | #include <mach/at91sam9_smc.h> |
| 46 | #include <mach/at91_shdwc.h> | 47 | #include <mach/at91_shdwc.h> |
| 47 | #include <mach/system_rev.h> | 48 | #include <mach/system_rev.h> |
| @@ -344,6 +345,7 @@ MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK") | |||
| 344 | /* Maintainer: Atmel */ | 345 | /* Maintainer: Atmel */ |
| 345 | .timer = &at91sam926x_timer, | 346 | .timer = &at91sam926x_timer, |
| 346 | .map_io = at91_map_io, | 347 | .map_io = at91_map_io, |
| 348 | .handle_irq = at91_aic_handle_irq, | ||
| 347 | .init_early = ek_init_early, | 349 | .init_early = ek_init_early, |
| 348 | .init_irq = at91_init_irq_default, | 350 | .init_irq = at91_init_irq_default, |
| 349 | .init_machine = ek_board_init, | 351 | .init_machine = ek_board_init, |
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c index 2736453821b0..2269be5fa384 100644 --- a/arch/arm/mach-at91/board-sam9261ek.c +++ b/arch/arm/mach-at91/board-sam9261ek.c | |||
| @@ -46,6 +46,7 @@ | |||
| 46 | 46 | ||
| 47 | #include <mach/hardware.h> | 47 | #include <mach/hardware.h> |
| 48 | #include <mach/board.h> | 48 | #include <mach/board.h> |
| 49 | #include <mach/at91_aic.h> | ||
| 49 | #include <mach/at91sam9_smc.h> | 50 | #include <mach/at91sam9_smc.h> |
| 50 | #include <mach/at91_shdwc.h> | 51 | #include <mach/at91_shdwc.h> |
| 51 | #include <mach/system_rev.h> | 52 | #include <mach/system_rev.h> |
| @@ -615,6 +616,7 @@ MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK") | |||
| 615 | /* Maintainer: Atmel */ | 616 | /* Maintainer: Atmel */ |
| 616 | .timer = &at91sam926x_timer, | 617 | .timer = &at91sam926x_timer, |
| 617 | .map_io = at91_map_io, | 618 | .map_io = at91_map_io, |
| 619 | .handle_irq = at91_aic_handle_irq, | ||
| 618 | .init_early = ek_init_early, | 620 | .init_early = ek_init_early, |
| 619 | .init_irq = at91_init_irq_default, | 621 | .init_irq = at91_init_irq_default, |
| 620 | .init_machine = ek_board_init, | 622 | .init_machine = ek_board_init, |
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c index 983cb98d2465..82adf581afc2 100644 --- a/arch/arm/mach-at91/board-sam9263ek.c +++ b/arch/arm/mach-at91/board-sam9263ek.c | |||
| @@ -45,6 +45,7 @@ | |||
| 45 | 45 | ||
| 46 | #include <mach/hardware.h> | 46 | #include <mach/hardware.h> |
| 47 | #include <mach/board.h> | 47 | #include <mach/board.h> |
| 48 | #include <mach/at91_aic.h> | ||
| 48 | #include <mach/at91sam9_smc.h> | 49 | #include <mach/at91sam9_smc.h> |
| 49 | #include <mach/at91_shdwc.h> | 50 | #include <mach/at91_shdwc.h> |
| 50 | #include <mach/system_rev.h> | 51 | #include <mach/system_rev.h> |
| @@ -443,6 +444,7 @@ MACHINE_START(AT91SAM9263EK, "Atmel AT91SAM9263-EK") | |||
| 443 | /* Maintainer: Atmel */ | 444 | /* Maintainer: Atmel */ |
| 444 | .timer = &at91sam926x_timer, | 445 | .timer = &at91sam926x_timer, |
| 445 | .map_io = at91_map_io, | 446 | .map_io = at91_map_io, |
| 447 | .handle_irq = at91_aic_handle_irq, | ||
| 446 | .init_early = ek_init_early, | 448 | .init_early = ek_init_early, |
| 447 | .init_irq = at91_init_irq_default, | 449 | .init_irq = at91_init_irq_default, |
| 448 | .init_machine = ek_board_init, | 450 | .init_machine = ek_board_init, |
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c index 6860d3451100..4ea4ee00364b 100644 --- a/arch/arm/mach-at91/board-sam9g20ek.c +++ b/arch/arm/mach-at91/board-sam9g20ek.c | |||
| @@ -44,6 +44,7 @@ | |||
| 44 | #include <asm/mach/irq.h> | 44 | #include <asm/mach/irq.h> |
| 45 | 45 | ||
| 46 | #include <mach/board.h> | 46 | #include <mach/board.h> |
| 47 | #include <mach/at91_aic.h> | ||
| 47 | #include <mach/at91sam9_smc.h> | 48 | #include <mach/at91sam9_smc.h> |
| 48 | #include <mach/system_rev.h> | 49 | #include <mach/system_rev.h> |
| 49 | 50 | ||
| @@ -413,6 +414,7 @@ MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK") | |||
| 413 | /* Maintainer: Atmel */ | 414 | /* Maintainer: Atmel */ |
| 414 | .timer = &at91sam926x_timer, | 415 | .timer = &at91sam926x_timer, |
| 415 | .map_io = at91_map_io, | 416 | .map_io = at91_map_io, |
| 417 | .handle_irq = at91_aic_handle_irq, | ||
| 416 | .init_early = ek_init_early, | 418 | .init_early = ek_init_early, |
| 417 | .init_irq = at91_init_irq_default, | 419 | .init_irq = at91_init_irq_default, |
| 418 | .init_machine = ek_board_init, | 420 | .init_machine = ek_board_init, |
| @@ -422,6 +424,7 @@ MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod") | |||
| 422 | /* Maintainer: Atmel */ | 424 | /* Maintainer: Atmel */ |
| 423 | .timer = &at91sam926x_timer, | 425 | .timer = &at91sam926x_timer, |
| 424 | .map_io = at91_map_io, | 426 | .map_io = at91_map_io, |
| 427 | .handle_irq = at91_aic_handle_irq, | ||
| 425 | .init_early = ek_init_early, | 428 | .init_early = ek_init_early, |
| 426 | .init_irq = at91_init_irq_default, | 429 | .init_irq = at91_init_irq_default, |
| 427 | .init_machine = ek_board_init, | 430 | .init_machine = ek_board_init, |
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c index 63163dc7df46..3d48ec154685 100644 --- a/arch/arm/mach-at91/board-sam9m10g45ek.c +++ b/arch/arm/mach-at91/board-sam9m10g45ek.c | |||
| @@ -43,6 +43,7 @@ | |||
| 43 | #include <asm/mach/irq.h> | 43 | #include <asm/mach/irq.h> |
| 44 | 44 | ||
| 45 | #include <mach/board.h> | 45 | #include <mach/board.h> |
| 46 | #include <mach/at91_aic.h> | ||
| 46 | #include <mach/at91sam9_smc.h> | 47 | #include <mach/at91sam9_smc.h> |
| 47 | #include <mach/at91_shdwc.h> | 48 | #include <mach/at91_shdwc.h> |
| 48 | #include <mach/system_rev.h> | 49 | #include <mach/system_rev.h> |
| @@ -503,6 +504,7 @@ MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK") | |||
| 503 | /* Maintainer: Atmel */ | 504 | /* Maintainer: Atmel */ |
| 504 | .timer = &at91sam926x_timer, | 505 | .timer = &at91sam926x_timer, |
| 505 | .map_io = at91_map_io, | 506 | .map_io = at91_map_io, |
| 507 | .handle_irq = at91_aic_handle_irq, | ||
| 506 | .init_early = ek_init_early, | 508 | .init_early = ek_init_early, |
| 507 | .init_irq = at91_init_irq_default, | 509 | .init_irq = at91_init_irq_default, |
| 508 | .init_machine = ek_board_init, | 510 | .init_machine = ek_board_init, |
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c index be3239f13daa..e7dc3ead7045 100644 --- a/arch/arm/mach-at91/board-sam9rlek.c +++ b/arch/arm/mach-at91/board-sam9rlek.c | |||
| @@ -31,6 +31,7 @@ | |||
| 31 | 31 | ||
| 32 | #include <mach/hardware.h> | 32 | #include <mach/hardware.h> |
| 33 | #include <mach/board.h> | 33 | #include <mach/board.h> |
| 34 | #include <mach/at91_aic.h> | ||
| 34 | #include <mach/at91sam9_smc.h> | 35 | #include <mach/at91sam9_smc.h> |
| 35 | #include <mach/at91_shdwc.h> | 36 | #include <mach/at91_shdwc.h> |
| 36 | 37 | ||
| @@ -319,6 +320,7 @@ MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK") | |||
| 319 | /* Maintainer: Atmel */ | 320 | /* Maintainer: Atmel */ |
| 320 | .timer = &at91sam926x_timer, | 321 | .timer = &at91sam926x_timer, |
| 321 | .map_io = at91_map_io, | 322 | .map_io = at91_map_io, |
| 323 | .handle_irq = at91_aic_handle_irq, | ||
| 322 | .init_early = ek_init_early, | 324 | .init_early = ek_init_early, |
| 323 | .init_irq = at91_init_irq_default, | 325 | .init_irq = at91_init_irq_default, |
| 324 | .init_machine = ek_board_init, | 326 | .init_machine = ek_board_init, |
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c index 9d446f1bb45f..a4e031a039fd 100644 --- a/arch/arm/mach-at91/board-snapper9260.c +++ b/arch/arm/mach-at91/board-snapper9260.c | |||
| @@ -33,6 +33,7 @@ | |||
| 33 | 33 | ||
| 34 | #include <mach/hardware.h> | 34 | #include <mach/hardware.h> |
| 35 | #include <mach/board.h> | 35 | #include <mach/board.h> |
| 36 | #include <mach/at91_aic.h> | ||
| 36 | #include <mach/at91sam9_smc.h> | 37 | #include <mach/at91sam9_smc.h> |
| 37 | 38 | ||
| 38 | #include "sam9_smc.h" | 39 | #include "sam9_smc.h" |
| @@ -178,6 +179,7 @@ static void __init snapper9260_board_init(void) | |||
| 178 | MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module") | 179 | MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module") |
| 179 | .timer = &at91sam926x_timer, | 180 | .timer = &at91sam926x_timer, |
| 180 | .map_io = at91_map_io, | 181 | .map_io = at91_map_io, |
| 182 | .handle_irq = at91_aic_handle_irq, | ||
| 181 | .init_early = snapper9260_init_early, | 183 | .init_early = snapper9260_init_early, |
| 182 | .init_irq = at91_init_irq_default, | 184 | .init_irq = at91_init_irq_default, |
| 183 | .init_machine = snapper9260_board_init, | 185 | .init_machine = snapper9260_board_init, |
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c index ee86f9d7ee72..29eae1626bf7 100644 --- a/arch/arm/mach-at91/board-stamp9g20.c +++ b/arch/arm/mach-at91/board-stamp9g20.c | |||
| @@ -26,6 +26,7 @@ | |||
| 26 | #include <asm/mach/arch.h> | 26 | #include <asm/mach/arch.h> |
| 27 | 27 | ||
| 28 | #include <mach/board.h> | 28 | #include <mach/board.h> |
| 29 | #include <mach/at91_aic.h> | ||
| 29 | #include <mach/at91sam9_smc.h> | 30 | #include <mach/at91sam9_smc.h> |
| 30 | 31 | ||
| 31 | #include "sam9_smc.h" | 32 | #include "sam9_smc.h" |
| @@ -287,6 +288,7 @@ MACHINE_START(PORTUXG20, "taskit PortuxG20") | |||
| 287 | /* Maintainer: taskit GmbH */ | 288 | /* Maintainer: taskit GmbH */ |
| 288 | .timer = &at91sam926x_timer, | 289 | .timer = &at91sam926x_timer, |
| 289 | .map_io = at91_map_io, | 290 | .map_io = at91_map_io, |
| 291 | .handle_irq = at91_aic_handle_irq, | ||
| 290 | .init_early = stamp9g20_init_early, | 292 | .init_early = stamp9g20_init_early, |
| 291 | .init_irq = at91_init_irq_default, | 293 | .init_irq = at91_init_irq_default, |
| 292 | .init_machine = portuxg20_board_init, | 294 | .init_machine = portuxg20_board_init, |
| @@ -296,6 +298,7 @@ MACHINE_START(STAMP9G20, "taskit Stamp9G20") | |||
| 296 | /* Maintainer: taskit GmbH */ | 298 | /* Maintainer: taskit GmbH */ |
| 297 | .timer = &at91sam926x_timer, | 299 | .timer = &at91sam926x_timer, |
| 298 | .map_io = at91_map_io, | 300 | .map_io = at91_map_io, |
| 301 | .handle_irq = at91_aic_handle_irq, | ||
| 299 | .init_early = stamp9g20_init_early, | 302 | .init_early = stamp9g20_init_early, |
| 300 | .init_irq = at91_init_irq_default, | 303 | .init_irq = at91_init_irq_default, |
| 301 | .init_machine = stamp9g20evb_board_init, | 304 | .init_machine = stamp9g20evb_board_init, |
diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c index 95393fcaf199..c1476b9fe7b9 100644 --- a/arch/arm/mach-at91/board-usb-a926x.c +++ b/arch/arm/mach-at91/board-usb-a926x.c | |||
| @@ -42,6 +42,7 @@ | |||
| 42 | 42 | ||
| 43 | #include <mach/hardware.h> | 43 | #include <mach/hardware.h> |
| 44 | #include <mach/board.h> | 44 | #include <mach/board.h> |
| 45 | #include <mach/at91_aic.h> | ||
| 45 | #include <mach/at91sam9_smc.h> | 46 | #include <mach/at91sam9_smc.h> |
| 46 | #include <mach/at91_shdwc.h> | 47 | #include <mach/at91_shdwc.h> |
| 47 | 48 | ||
| @@ -358,6 +359,7 @@ MACHINE_START(USB_A9263, "CALAO USB_A9263") | |||
| 358 | /* Maintainer: calao-systems */ | 359 | /* Maintainer: calao-systems */ |
| 359 | .timer = &at91sam926x_timer, | 360 | .timer = &at91sam926x_timer, |
| 360 | .map_io = at91_map_io, | 361 | .map_io = at91_map_io, |
| 362 | .handle_irq = at91_aic_handle_irq, | ||
| 361 | .init_early = ek_init_early, | 363 | .init_early = ek_init_early, |
| 362 | .init_irq = at91_init_irq_default, | 364 | .init_irq = at91_init_irq_default, |
| 363 | .init_machine = ek_board_init, | 365 | .init_machine = ek_board_init, |
| @@ -367,6 +369,7 @@ MACHINE_START(USB_A9260, "CALAO USB_A9260") | |||
| 367 | /* Maintainer: calao-systems */ | 369 | /* Maintainer: calao-systems */ |
| 368 | .timer = &at91sam926x_timer, | 370 | .timer = &at91sam926x_timer, |
| 369 | .map_io = at91_map_io, | 371 | .map_io = at91_map_io, |
| 372 | .handle_irq = at91_aic_handle_irq, | ||
| 370 | .init_early = ek_init_early, | 373 | .init_early = ek_init_early, |
| 371 | .init_irq = at91_init_irq_default, | 374 | .init_irq = at91_init_irq_default, |
| 372 | .init_machine = ek_board_init, | 375 | .init_machine = ek_board_init, |
| @@ -376,6 +379,7 @@ MACHINE_START(USB_A9G20, "CALAO USB_A92G0") | |||
| 376 | /* Maintainer: Jean-Christophe PLAGNIOL-VILLARD */ | 379 | /* Maintainer: Jean-Christophe PLAGNIOL-VILLARD */ |
| 377 | .timer = &at91sam926x_timer, | 380 | .timer = &at91sam926x_timer, |
| 378 | .map_io = at91_map_io, | 381 | .map_io = at91_map_io, |
| 382 | .handle_irq = at91_aic_handle_irq, | ||
| 379 | .init_early = ek_init_early, | 383 | .init_early = ek_init_early, |
| 380 | .init_irq = at91_init_irq_default, | 384 | .init_irq = at91_init_irq_default, |
| 381 | .init_machine = ek_board_init, | 385 | .init_machine = ek_board_init, |
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c index d56665ea4b55..516d340549d8 100644 --- a/arch/arm/mach-at91/board-yl-9200.c +++ b/arch/arm/mach-at91/board-yl-9200.c | |||
| @@ -44,6 +44,7 @@ | |||
| 44 | 44 | ||
| 45 | #include <mach/hardware.h> | 45 | #include <mach/hardware.h> |
| 46 | #include <mach/board.h> | 46 | #include <mach/board.h> |
| 47 | #include <mach/at91_aic.h> | ||
| 47 | #include <mach/at91rm9200_mc.h> | 48 | #include <mach/at91rm9200_mc.h> |
| 48 | #include <mach/at91_ramc.h> | 49 | #include <mach/at91_ramc.h> |
| 49 | #include <mach/cpu.h> | 50 | #include <mach/cpu.h> |
| @@ -590,6 +591,7 @@ MACHINE_START(YL9200, "uCdragon YL-9200") | |||
| 590 | /* Maintainer: S.Birtles */ | 591 | /* Maintainer: S.Birtles */ |
| 591 | .timer = &at91rm9200_timer, | 592 | .timer = &at91rm9200_timer, |
| 592 | .map_io = at91_map_io, | 593 | .map_io = at91_map_io, |
| 594 | .handle_irq = at91_aic_handle_irq, | ||
| 593 | .init_early = yl9200_init_early, | 595 | .init_early = yl9200_init_early, |
| 594 | .init_irq = at91_init_irq_default, | 596 | .init_irq = at91_init_irq_default, |
| 595 | .init_machine = yl9200_board_init, | 597 | .init_machine = yl9200_board_init, |
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index 0a60bf837037..f49650677653 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h | |||
| @@ -29,6 +29,8 @@ extern void __init at91x40_init_interrupts(unsigned int priority[]); | |||
| 29 | extern void __init at91_aic_init(unsigned int priority[]); | 29 | extern void __init at91_aic_init(unsigned int priority[]); |
| 30 | extern int __init at91_aic_of_init(struct device_node *node, | 30 | extern int __init at91_aic_of_init(struct device_node *node, |
| 31 | struct device_node *parent); | 31 | struct device_node *parent); |
| 32 | extern int __init at91_aic5_of_init(struct device_node *node, | ||
| 33 | struct device_node *parent); | ||
| 32 | 34 | ||
| 33 | 35 | ||
| 34 | /* Timer */ | 36 | /* Timer */ |
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c index 325837a264c9..be42cf0e74bd 100644 --- a/arch/arm/mach-at91/gpio.c +++ b/arch/arm/mach-at91/gpio.c | |||
| @@ -26,6 +26,8 @@ | |||
| 26 | #include <linux/of_irq.h> | 26 | #include <linux/of_irq.h> |
| 27 | #include <linux/of_gpio.h> | 27 | #include <linux/of_gpio.h> |
| 28 | 28 | ||
| 29 | #include <asm/mach/irq.h> | ||
| 30 | |||
| 29 | #include <mach/hardware.h> | 31 | #include <mach/hardware.h> |
| 30 | #include <mach/at91_pio.h> | 32 | #include <mach/at91_pio.h> |
| 31 | 33 | ||
| @@ -585,15 +587,14 @@ static struct irq_chip gpio_irqchip = { | |||
| 585 | 587 | ||
| 586 | static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) | 588 | static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) |
| 587 | { | 589 | { |
| 590 | struct irq_chip *chip = irq_desc_get_chip(desc); | ||
| 588 | struct irq_data *idata = irq_desc_get_irq_data(desc); | 591 | struct irq_data *idata = irq_desc_get_irq_data(desc); |
| 589 | struct irq_chip *chip = irq_data_get_irq_chip(idata); | ||
| 590 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata); | 592 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata); |
| 591 | void __iomem *pio = at91_gpio->regbase; | 593 | void __iomem *pio = at91_gpio->regbase; |
| 592 | unsigned long isr; | 594 | unsigned long isr; |
| 593 | int n; | 595 | int n; |
| 594 | 596 | ||
| 595 | /* temporarily mask (level sensitive) parent IRQ */ | 597 | chained_irq_enter(chip, desc); |
| 596 | chip->irq_ack(idata); | ||
| 597 | for (;;) { | 598 | for (;;) { |
| 598 | /* Reading ISR acks pending (edge triggered) GPIO interrupts. | 599 | /* Reading ISR acks pending (edge triggered) GPIO interrupts. |
| 599 | * When there none are pending, we're finished unless we need | 600 | * When there none are pending, we're finished unless we need |
| @@ -614,7 +615,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |||
| 614 | n = find_next_bit(&isr, BITS_PER_LONG, n + 1); | 615 | n = find_next_bit(&isr, BITS_PER_LONG, n + 1); |
| 615 | } | 616 | } |
| 616 | } | 617 | } |
| 617 | chip->irq_unmask(idata); | 618 | chained_irq_exit(chip, desc); |
| 618 | /* now it may re-trigger */ | 619 | /* now it may re-trigger */ |
| 619 | } | 620 | } |
| 620 | 621 | ||
diff --git a/arch/arm/mach-at91/include/mach/at91_aic.h b/arch/arm/mach-at91/include/mach/at91_aic.h index 3045781c473f..eaea66197fa1 100644 --- a/arch/arm/mach-at91/include/mach/at91_aic.h +++ b/arch/arm/mach-at91/include/mach/at91_aic.h | |||
| @@ -23,12 +23,23 @@ extern void __iomem *at91_aic_base; | |||
| 23 | __raw_readl(at91_aic_base + field) | 23 | __raw_readl(at91_aic_base + field) |
| 24 | 24 | ||
| 25 | #define at91_aic_write(field, value) \ | 25 | #define at91_aic_write(field, value) \ |
| 26 | __raw_writel(value, at91_aic_base + field); | 26 | __raw_writel(value, at91_aic_base + field) |
| 27 | #else | 27 | #else |
| 28 | .extern at91_aic_base | 28 | .extern at91_aic_base |
| 29 | #endif | 29 | #endif |
| 30 | 30 | ||
| 31 | /* Number of irq lines managed by AIC */ | ||
| 32 | #define NR_AIC_IRQS 32 | ||
| 33 | #define NR_AIC5_IRQS 128 | ||
| 34 | |||
| 35 | #define AT91_AIC5_SSR 0x0 /* Source Select Register [AIC5] */ | ||
| 36 | #define AT91_AIC5_INTSEL_MSK (0x7f << 0) /* Interrupt Line Selection Mask */ | ||
| 37 | |||
| 38 | #define AT91_AIC_IRQ_MIN_PRIORITY 0 | ||
| 39 | #define AT91_AIC_IRQ_MAX_PRIORITY 7 | ||
| 40 | |||
| 31 | #define AT91_AIC_SMR(n) ((n) * 4) /* Source Mode Registers 0-31 */ | 41 | #define AT91_AIC_SMR(n) ((n) * 4) /* Source Mode Registers 0-31 */ |
| 42 | #define AT91_AIC5_SMR 0x4 /* Source Mode Register [AIC5] */ | ||
| 32 | #define AT91_AIC_PRIOR (7 << 0) /* Priority Level */ | 43 | #define AT91_AIC_PRIOR (7 << 0) /* Priority Level */ |
| 33 | #define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */ | 44 | #define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */ |
| 34 | #define AT91_AIC_SRCTYPE_LOW (0 << 5) | 45 | #define AT91_AIC_SRCTYPE_LOW (0 << 5) |
| @@ -37,29 +48,52 @@ extern void __iomem *at91_aic_base; | |||
| 37 | #define AT91_AIC_SRCTYPE_RISING (3 << 5) | 48 | #define AT91_AIC_SRCTYPE_RISING (3 << 5) |
| 38 | 49 | ||
| 39 | #define AT91_AIC_SVR(n) (0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */ | 50 | #define AT91_AIC_SVR(n) (0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */ |
| 51 | #define AT91_AIC5_SVR 0x8 /* Source Vector Register [AIC5] */ | ||
| 40 | #define AT91_AIC_IVR 0x100 /* Interrupt Vector Register */ | 52 | #define AT91_AIC_IVR 0x100 /* Interrupt Vector Register */ |
| 53 | #define AT91_AIC5_IVR 0x10 /* Interrupt Vector Register [AIC5] */ | ||
| 41 | #define AT91_AIC_FVR 0x104 /* Fast Interrupt Vector Register */ | 54 | #define AT91_AIC_FVR 0x104 /* Fast Interrupt Vector Register */ |
| 55 | #define AT91_AIC5_FVR 0x14 /* Fast Interrupt Vector Register [AIC5] */ | ||
| 42 | #define AT91_AIC_ISR 0x108 /* Interrupt Status Register */ | 56 | #define AT91_AIC_ISR 0x108 /* Interrupt Status Register */ |
| 57 | #define AT91_AIC5_ISR 0x18 /* Interrupt Status Register [AIC5] */ | ||
| 43 | #define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */ | 58 | #define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */ |
| 44 | 59 | ||
| 45 | #define AT91_AIC_IPR 0x10c /* Interrupt Pending Register */ | 60 | #define AT91_AIC_IPR 0x10c /* Interrupt Pending Register */ |
| 61 | #define AT91_AIC5_IPR0 0x20 /* Interrupt Pending Register 0 [AIC5] */ | ||
| 62 | #define AT91_AIC5_IPR1 0x24 /* Interrupt Pending Register 1 [AIC5] */ | ||
| 63 | #define AT91_AIC5_IPR2 0x28 /* Interrupt Pending Register 2 [AIC5] */ | ||
| 64 | #define AT91_AIC5_IPR3 0x2c /* Interrupt Pending Register 3 [AIC5] */ | ||
| 46 | #define AT91_AIC_IMR 0x110 /* Interrupt Mask Register */ | 65 | #define AT91_AIC_IMR 0x110 /* Interrupt Mask Register */ |
| 66 | #define AT91_AIC5_IMR 0x30 /* Interrupt Mask Register [AIC5] */ | ||
| 47 | #define AT91_AIC_CISR 0x114 /* Core Interrupt Status Register */ | 67 | #define AT91_AIC_CISR 0x114 /* Core Interrupt Status Register */ |
| 68 | #define AT91_AIC5_CISR 0x34 /* Core Interrupt Status Register [AIC5] */ | ||
| 48 | #define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */ | 69 | #define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */ |
| 49 | #define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */ | 70 | #define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */ |
| 50 | 71 | ||
| 51 | #define AT91_AIC_IECR 0x120 /* Interrupt Enable Command Register */ | 72 | #define AT91_AIC_IECR 0x120 /* Interrupt Enable Command Register */ |
| 73 | #define AT91_AIC5_IECR 0x40 /* Interrupt Enable Command Register [AIC5] */ | ||
| 52 | #define AT91_AIC_IDCR 0x124 /* Interrupt Disable Command Register */ | 74 | #define AT91_AIC_IDCR 0x124 /* Interrupt Disable Command Register */ |
| 75 | #define AT91_AIC5_IDCR 0x44 /* Interrupt Disable Command Register [AIC5] */ | ||
| 53 | #define AT91_AIC_ICCR 0x128 /* Interrupt Clear Command Register */ | 76 | #define AT91_AIC_ICCR 0x128 /* Interrupt Clear Command Register */ |
| 77 | #define AT91_AIC5_ICCR 0x48 /* Interrupt Clear Command Register [AIC5] */ | ||
| 54 | #define AT91_AIC_ISCR 0x12c /* Interrupt Set Command Register */ | 78 | #define AT91_AIC_ISCR 0x12c /* Interrupt Set Command Register */ |
| 79 | #define AT91_AIC5_ISCR 0x4c /* Interrupt Set Command Register [AIC5] */ | ||
| 55 | #define AT91_AIC_EOICR 0x130 /* End of Interrupt Command Register */ | 80 | #define AT91_AIC_EOICR 0x130 /* End of Interrupt Command Register */ |
| 81 | #define AT91_AIC5_EOICR 0x38 /* End of Interrupt Command Register [AIC5] */ | ||
| 56 | #define AT91_AIC_SPU 0x134 /* Spurious Interrupt Vector Register */ | 82 | #define AT91_AIC_SPU 0x134 /* Spurious Interrupt Vector Register */ |
| 83 | #define AT91_AIC5_SPU 0x3c /* Spurious Interrupt Vector Register [AIC5] */ | ||
| 57 | #define AT91_AIC_DCR 0x138 /* Debug Control Register */ | 84 | #define AT91_AIC_DCR 0x138 /* Debug Control Register */ |
| 85 | #define AT91_AIC5_DCR 0x6c /* Debug Control Register [AIC5] */ | ||
| 58 | #define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */ | 86 | #define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */ |
| 59 | #define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */ | 87 | #define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */ |
| 60 | 88 | ||
| 61 | #define AT91_AIC_FFER 0x140 /* Fast Forcing Enable Register [SAM9 only] */ | 89 | #define AT91_AIC_FFER 0x140 /* Fast Forcing Enable Register [SAM9 only] */ |
| 90 | #define AT91_AIC5_FFER 0x50 /* Fast Forcing Enable Register [AIC5] */ | ||
| 62 | #define AT91_AIC_FFDR 0x144 /* Fast Forcing Disable Register [SAM9 only] */ | 91 | #define AT91_AIC_FFDR 0x144 /* Fast Forcing Disable Register [SAM9 only] */ |
| 92 | #define AT91_AIC5_FFDR 0x54 /* Fast Forcing Disable Register [AIC5] */ | ||
| 63 | #define AT91_AIC_FFSR 0x148 /* Fast Forcing Status Register [SAM9 only] */ | 93 | #define AT91_AIC_FFSR 0x148 /* Fast Forcing Status Register [SAM9 only] */ |
| 94 | #define AT91_AIC5_FFSR 0x58 /* Fast Forcing Status Register [AIC5] */ | ||
| 95 | |||
| 96 | void at91_aic_handle_irq(struct pt_regs *regs); | ||
| 97 | void at91_aic5_handle_irq(struct pt_regs *regs); | ||
| 64 | 98 | ||
| 65 | #endif | 99 | #endif |
diff --git a/arch/arm/mach-at91/include/mach/at91_spi.h b/arch/arm/mach-at91/include/mach/at91_spi.h deleted file mode 100644 index 2f6ba0c5636e..000000000000 --- a/arch/arm/mach-at91/include/mach/at91_spi.h +++ /dev/null | |||
| @@ -1,81 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91_spi.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Serial Peripheral Interface (SPI) registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_SPI_H | ||
| 17 | #define AT91_SPI_H | ||
| 18 | |||
| 19 | #define AT91_SPI_CR 0x00 /* Control Register */ | ||
| 20 | #define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */ | ||
| 21 | #define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */ | ||
| 22 | #define AT91_SPI_SWRST (1 << 7) /* SPI Software Reset */ | ||
| 23 | #define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */ | ||
| 24 | |||
| 25 | #define AT91_SPI_MR 0x04 /* Mode Register */ | ||
| 26 | #define AT91_SPI_MSTR (1 << 0) /* Master/Slave Mode */ | ||
| 27 | #define AT91_SPI_PS (1 << 1) /* Peripheral Select */ | ||
| 28 | #define AT91_SPI_PS_FIXED (0 << 1) | ||
| 29 | #define AT91_SPI_PS_VARIABLE (1 << 1) | ||
| 30 | #define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */ | ||
| 31 | #define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */ | ||
| 32 | #define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */ | ||
| 33 | #define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */ | ||
| 34 | #define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ | ||
| 35 | #define AT91_SPI_DLYBCS (0xff << 24) /* Delay Between Chip Selects */ | ||
| 36 | |||
| 37 | #define AT91_SPI_RDR 0x08 /* Receive Data Register */ | ||
| 38 | #define AT91_SPI_RD (0xffff << 0) /* Receive Data */ | ||
| 39 | #define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ | ||
| 40 | |||
| 41 | #define AT91_SPI_TDR 0x0c /* Transmit Data Register */ | ||
| 42 | #define AT91_SPI_TD (0xffff << 0) /* Transmit Data */ | ||
| 43 | #define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ | ||
| 44 | #define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */ | ||
| 45 | |||
| 46 | #define AT91_SPI_SR 0x10 /* Status Register */ | ||
| 47 | #define AT91_SPI_RDRF (1 << 0) /* Receive Data Register Full */ | ||
| 48 | #define AT91_SPI_TDRE (1 << 1) /* Transmit Data Register Full */ | ||
| 49 | #define AT91_SPI_MODF (1 << 2) /* Mode Fault Error */ | ||
| 50 | #define AT91_SPI_OVRES (1 << 3) /* Overrun Error Status */ | ||
| 51 | #define AT91_SPI_ENDRX (1 << 4) /* End of RX buffer */ | ||
| 52 | #define AT91_SPI_ENDTX (1 << 5) /* End of TX buffer */ | ||
| 53 | #define AT91_SPI_RXBUFF (1 << 6) /* RX Buffer Full */ | ||
| 54 | #define AT91_SPI_TXBUFE (1 << 7) /* TX Buffer Empty */ | ||
| 55 | #define AT91_SPI_NSSR (1 << 8) /* NSS Rising [SAM9261 only] */ | ||
| 56 | #define AT91_SPI_TXEMPTY (1 << 9) /* Transmission Register Empty [SAM9261 only] */ | ||
| 57 | #define AT91_SPI_SPIENS (1 << 16) /* SPI Enable Status */ | ||
| 58 | |||
| 59 | #define AT91_SPI_IER 0x14 /* Interrupt Enable Register */ | ||
| 60 | #define AT91_SPI_IDR 0x18 /* Interrupt Disable Register */ | ||
| 61 | #define AT91_SPI_IMR 0x1c /* Interrupt Mask Register */ | ||
| 62 | |||
| 63 | #define AT91_SPI_CSR(n) (0x30 + ((n) * 4)) /* Chip Select Registers 0-3 */ | ||
| 64 | #define AT91_SPI_CPOL (1 << 0) /* Clock Polarity */ | ||
| 65 | #define AT91_SPI_NCPHA (1 << 1) /* Clock Phase */ | ||
| 66 | #define AT91_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */ | ||
| 67 | #define AT91_SPI_BITS (0xf << 4) /* Bits Per Transfer */ | ||
| 68 | #define AT91_SPI_BITS_8 (0 << 4) | ||
| 69 | #define AT91_SPI_BITS_9 (1 << 4) | ||
| 70 | #define AT91_SPI_BITS_10 (2 << 4) | ||
| 71 | #define AT91_SPI_BITS_11 (3 << 4) | ||
| 72 | #define AT91_SPI_BITS_12 (4 << 4) | ||
| 73 | #define AT91_SPI_BITS_13 (5 << 4) | ||
| 74 | #define AT91_SPI_BITS_14 (6 << 4) | ||
| 75 | #define AT91_SPI_BITS_15 (7 << 4) | ||
| 76 | #define AT91_SPI_BITS_16 (8 << 4) | ||
| 77 | #define AT91_SPI_SCBR (0xff << 8) /* Serial Clock Baud Rate */ | ||
| 78 | #define AT91_SPI_DLYBS (0xff << 16) /* Delay before SPCK */ | ||
| 79 | #define AT91_SPI_DLYBCT (0xff << 24) /* Delay between Consecutive Transfers */ | ||
| 80 | |||
| 81 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91_ssc.h b/arch/arm/mach-at91/include/mach/at91_ssc.h deleted file mode 100644 index a81114c11c74..000000000000 --- a/arch/arm/mach-at91/include/mach/at91_ssc.h +++ /dev/null | |||
| @@ -1,106 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91_ssc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) SAN People | ||
| 5 | * | ||
| 6 | * Serial Synchronous Controller (SSC) registers. | ||
| 7 | * Based on AT91RM9200 datasheet revision E. | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef AT91_SSC_H | ||
| 16 | #define AT91_SSC_H | ||
| 17 | |||
| 18 | #define AT91_SSC_CR 0x00 /* Control Register */ | ||
| 19 | #define AT91_SSC_RXEN (1 << 0) /* Receive Enable */ | ||
| 20 | #define AT91_SSC_RXDIS (1 << 1) /* Receive Disable */ | ||
| 21 | #define AT91_SSC_TXEN (1 << 8) /* Transmit Enable */ | ||
| 22 | #define AT91_SSC_TXDIS (1 << 9) /* Transmit Disable */ | ||
| 23 | #define AT91_SSC_SWRST (1 << 15) /* Software Reset */ | ||
| 24 | |||
| 25 | #define AT91_SSC_CMR 0x04 /* Clock Mode Register */ | ||
| 26 | #define AT91_SSC_CMR_DIV (0xfff << 0) /* Clock Divider */ | ||
| 27 | |||
| 28 | #define AT91_SSC_RCMR 0x10 /* Receive Clock Mode Register */ | ||
| 29 | #define AT91_SSC_CKS (3 << 0) /* Clock Selection */ | ||
| 30 | #define AT91_SSC_CKS_DIV (0 << 0) | ||
| 31 | #define AT91_SSC_CKS_CLOCK (1 << 0) | ||
| 32 | #define AT91_SSC_CKS_PIN (2 << 0) | ||
| 33 | #define AT91_SSC_CKO (7 << 2) /* Clock Output Mode Selection */ | ||
| 34 | #define AT91_SSC_CKO_NONE (0 << 2) | ||
| 35 | #define AT91_SSC_CKO_CONTINUOUS (1 << 2) | ||
| 36 | #define AT91_SSC_CKI (1 << 5) /* Clock Inversion */ | ||
| 37 | #define AT91_SSC_CKI_FALLING (0 << 5) | ||
| 38 | #define AT91_SSC_CK_RISING (1 << 5) | ||
| 39 | #define AT91_SSC_CKG (1 << 6) /* Receive Clock Gating Selection [AT91SAM9261 only] */ | ||
| 40 | #define AT91_SSC_CKG_NONE (0 << 6) | ||
| 41 | #define AT91_SSC_CKG_RFLOW (1 << 6) | ||
| 42 | #define AT91_SSC_CKG_RFHIGH (2 << 6) | ||
| 43 | #define AT91_SSC_START (0xf << 8) /* Start Selection */ | ||
| 44 | #define AT91_SSC_START_CONTINUOUS (0 << 8) | ||
| 45 | #define AT91_SSC_START_TX_RX (1 << 8) | ||
| 46 | #define AT91_SSC_START_LOW_RF (2 << 8) | ||
| 47 | #define AT91_SSC_START_HIGH_RF (3 << 8) | ||
| 48 | #define AT91_SSC_START_FALLING_RF (4 << 8) | ||
| 49 | #define AT91_SSC_START_RISING_RF (5 << 8) | ||
| 50 | #define AT91_SSC_START_LEVEL_RF (6 << 8) | ||
| 51 | #define AT91_SSC_START_EDGE_RF (7 << 8) | ||
| 52 | #define AT91_SSC_STOP (1 << 12) /* Receive Stop Selection [AT91SAM9261 only] */ | ||
| 53 | #define AT91_SSC_STTDLY (0xff << 16) /* Start Delay */ | ||
| 54 | #define AT91_SSC_PERIOD (0xff << 24) /* Period Divider Selection */ | ||
| 55 | |||
| 56 | #define AT91_SSC_RFMR 0x14 /* Receive Frame Mode Register */ | ||
| 57 | #define AT91_SSC_DATALEN (0x1f << 0) /* Data Length */ | ||
| 58 | #define AT91_SSC_LOOP (1 << 5) /* Loop Mode */ | ||
| 59 | #define AT91_SSC_MSBF (1 << 7) /* Most Significant Bit First */ | ||
| 60 | #define AT91_SSC_DATNB (0xf << 8) /* Data Number per Frame */ | ||
| 61 | #define AT91_SSC_FSLEN (0xf << 16) /* Frame Sync Length */ | ||
| 62 | #define AT91_SSC_FSOS (7 << 20) /* Frame Sync Output Selection */ | ||
| 63 | #define AT91_SSC_FSOS_NONE (0 << 20) | ||
| 64 | #define AT91_SSC_FSOS_NEGATIVE (1 << 20) | ||
| 65 | #define AT91_SSC_FSOS_POSITIVE (2 << 20) | ||
| 66 | #define AT91_SSC_FSOS_LOW (3 << 20) | ||
| 67 | #define AT91_SSC_FSOS_HIGH (4 << 20) | ||
| 68 | #define AT91_SSC_FSOS_TOGGLE (5 << 20) | ||
| 69 | #define AT91_SSC_FSEDGE (1 << 24) /* Frame Sync Edge Detection */ | ||
| 70 | #define AT91_SSC_FSEDGE_POSITIVE (0 << 24) | ||
| 71 | #define AT91_SSC_FSEDGE_NEGATIVE (1 << 24) | ||
| 72 | |||
| 73 | #define AT91_SSC_TCMR 0x18 /* Transmit Clock Mode Register */ | ||
| 74 | #define AT91_SSC_TFMR 0x1c /* Transmit Fram Mode Register */ | ||
| 75 | #define AT91_SSC_DATDEF (1 << 5) /* Data Default Value */ | ||
| 76 | #define AT91_SSC_FSDEN (1 << 23) /* Frame Sync Data Enable */ | ||
| 77 | |||
| 78 | #define AT91_SSC_RHR 0x20 /* Receive Holding Register */ | ||
| 79 | #define AT91_SSC_THR 0x24 /* Transmit Holding Register */ | ||
| 80 | #define AT91_SSC_RSHR 0x30 /* Receive Sync Holding Register */ | ||
| 81 | #define AT91_SSC_TSHR 0x34 /* Transmit Sync Holding Register */ | ||
| 82 | |||
| 83 | #define AT91_SSC_RC0R 0x38 /* Receive Compare 0 Register [AT91SAM9261 only] */ | ||
| 84 | #define AT91_SSC_RC1R 0x3c /* Receive Compare 1 Register [AT91SAM9261 only] */ | ||
| 85 | |||
| 86 | #define AT91_SSC_SR 0x40 /* Status Register */ | ||
| 87 | #define AT91_SSC_TXRDY (1 << 0) /* Transmit Ready */ | ||
| 88 | #define AT91_SSC_TXEMPTY (1 << 1) /* Transmit Empty */ | ||
| 89 | #define AT91_SSC_ENDTX (1 << 2) /* End of Transmission */ | ||
| 90 | #define AT91_SSC_TXBUFE (1 << 3) /* Transmit Buffer Empty */ | ||
| 91 | #define AT91_SSC_RXRDY (1 << 4) /* Receive Ready */ | ||
| 92 | #define AT91_SSC_OVRUN (1 << 5) /* Receive Overrun */ | ||
| 93 | #define AT91_SSC_ENDRX (1 << 6) /* End of Reception */ | ||
| 94 | #define AT91_SSC_RXBUFF (1 << 7) /* Receive Buffer Full */ | ||
| 95 | #define AT91_SSC_CP0 (1 << 8) /* Compare 0 [AT91SAM9261 only] */ | ||
| 96 | #define AT91_SSC_CP1 (1 << 9) /* Compare 1 [AT91SAM9261 only] */ | ||
| 97 | #define AT91_SSC_TXSYN (1 << 10) /* Transmit Sync */ | ||
| 98 | #define AT91_SSC_RXSYN (1 << 11) /* Receive Sync */ | ||
| 99 | #define AT91_SSC_TXENA (1 << 16) /* Transmit Enable */ | ||
| 100 | #define AT91_SSC_RXENA (1 << 17) /* Receive Enable */ | ||
| 101 | |||
| 102 | #define AT91_SSC_IER 0x44 /* Interrupt Enable Register */ | ||
| 103 | #define AT91_SSC_IDR 0x48 /* Interrupt Disable Register */ | ||
| 104 | #define AT91_SSC_IMR 0x4c /* Interrupt Mask Register */ | ||
| 105 | |||
| 106 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/entry-macro.S b/arch/arm/mach-at91/include/mach/entry-macro.S deleted file mode 100644 index 903bf205a333..000000000000 --- a/arch/arm/mach-at91/include/mach/entry-macro.S +++ /dev/null | |||
| @@ -1,27 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/entry-macro.S | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003-2005 SAN People | ||
| 5 | * | ||
| 6 | * Low-level IRQ helper macros for AT91RM9200 platforms | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <mach/hardware.h> | ||
| 14 | #include <mach/at91_aic.h> | ||
| 15 | |||
| 16 | .macro get_irqnr_preamble, base, tmp | ||
| 17 | ldr \base, =at91_aic_base @ base virtual address of AIC peripheral | ||
| 18 | ldr \base, [\base] | ||
| 19 | .endm | ||
| 20 | |||
| 21 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 22 | ldr \irqnr, [\base, #AT91_AIC_IVR] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt) | ||
| 23 | ldr \irqstat, [\base, #AT91_AIC_ISR] @ read interrupt source number | ||
| 24 | teq \irqstat, #0 @ ISR is 0 when no current interrupt, or spurious interrupt | ||
| 25 | streq \tmp, [\base, #AT91_AIC_EOICR] @ not going to be handled further, then ACK it now. | ||
| 26 | .endm | ||
| 27 | |||
diff --git a/arch/arm/mach-at91/include/mach/irqs.h b/arch/arm/mach-at91/include/mach/irqs.h deleted file mode 100644 index ac8b7dfc85ef..000000000000 --- a/arch/arm/mach-at91/include/mach/irqs.h +++ /dev/null | |||
| @@ -1,48 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/irqs.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2004 SAN People | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_IRQS_H | ||
| 22 | #define __ASM_ARCH_IRQS_H | ||
| 23 | |||
| 24 | #include <linux/io.h> | ||
| 25 | #include <mach/at91_aic.h> | ||
| 26 | |||
| 27 | #define NR_AIC_IRQS 32 | ||
| 28 | |||
| 29 | |||
| 30 | /* | ||
| 31 | * Acknowledge interrupt with AIC after interrupt has been handled. | ||
| 32 | * (by kernel/irq.c) | ||
| 33 | */ | ||
| 34 | #define irq_finish(irq) do { at91_aic_write(AT91_AIC_EOICR, 0); } while (0) | ||
| 35 | |||
| 36 | |||
| 37 | /* | ||
| 38 | * IRQ interrupt symbols are the AT91xxx_ID_* symbols | ||
| 39 | * for IRQs handled directly through the AIC, or else the AT91_PIN_* | ||
| 40 | * symbols in gpio.h for ones handled indirectly as GPIOs. | ||
| 41 | * We make provision for 5 banks of GPIO. | ||
| 42 | */ | ||
| 43 | #define NR_IRQS (NR_AIC_IRQS + (5 * 32)) | ||
| 44 | |||
| 45 | /* FIQ is AIC source 0. */ | ||
| 46 | #define FIQ_START AT91_ID_FIQ | ||
| 47 | |||
| 48 | #endif | ||
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c index cfcfcbe36269..1e02c0e49dcc 100644 --- a/arch/arm/mach-at91/irq.c +++ b/arch/arm/mach-at91/irq.c | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | #include <linux/init.h> | 23 | #include <linux/init.h> |
| 24 | #include <linux/module.h> | 24 | #include <linux/module.h> |
| 25 | #include <linux/mm.h> | 25 | #include <linux/mm.h> |
| 26 | #include <linux/bitmap.h> | ||
| 26 | #include <linux/types.h> | 27 | #include <linux/types.h> |
| 27 | #include <linux/irq.h> | 28 | #include <linux/irq.h> |
| 28 | #include <linux/of.h> | 29 | #include <linux/of.h> |
| @@ -30,38 +31,218 @@ | |||
| 30 | #include <linux/of_irq.h> | 31 | #include <linux/of_irq.h> |
| 31 | #include <linux/irqdomain.h> | 32 | #include <linux/irqdomain.h> |
| 32 | #include <linux/err.h> | 33 | #include <linux/err.h> |
| 34 | #include <linux/slab.h> | ||
| 33 | 35 | ||
| 34 | #include <mach/hardware.h> | 36 | #include <mach/hardware.h> |
| 35 | #include <asm/irq.h> | 37 | #include <asm/irq.h> |
| 36 | #include <asm/setup.h> | 38 | #include <asm/setup.h> |
| 37 | 39 | ||
| 40 | #include <asm/exception.h> | ||
| 38 | #include <asm/mach/arch.h> | 41 | #include <asm/mach/arch.h> |
| 39 | #include <asm/mach/irq.h> | 42 | #include <asm/mach/irq.h> |
| 40 | #include <asm/mach/map.h> | 43 | #include <asm/mach/map.h> |
| 41 | 44 | ||
| 45 | #include <mach/at91_aic.h> | ||
| 46 | |||
| 42 | void __iomem *at91_aic_base; | 47 | void __iomem *at91_aic_base; |
| 43 | static struct irq_domain *at91_aic_domain; | 48 | static struct irq_domain *at91_aic_domain; |
| 44 | static struct device_node *at91_aic_np; | 49 | static struct device_node *at91_aic_np; |
| 50 | static unsigned int n_irqs = NR_AIC_IRQS; | ||
| 51 | static unsigned long at91_aic_caps = 0; | ||
| 52 | |||
| 53 | /* AIC5 introduces a Source Select Register */ | ||
| 54 | #define AT91_AIC_CAP_AIC5 (1 << 0) | ||
| 55 | #define has_aic5() (at91_aic_caps & AT91_AIC_CAP_AIC5) | ||
| 56 | |||
| 57 | #ifdef CONFIG_PM | ||
| 58 | |||
| 59 | static unsigned long *wakeups; | ||
| 60 | static unsigned long *backups; | ||
| 61 | |||
| 62 | #define set_backup(bit) set_bit(bit, backups) | ||
| 63 | #define clear_backup(bit) clear_bit(bit, backups) | ||
| 64 | |||
| 65 | static int at91_aic_pm_init(void) | ||
| 66 | { | ||
| 67 | backups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL); | ||
| 68 | if (!backups) | ||
| 69 | return -ENOMEM; | ||
| 70 | |||
| 71 | wakeups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL); | ||
| 72 | if (!wakeups) { | ||
| 73 | kfree(backups); | ||
| 74 | return -ENOMEM; | ||
| 75 | } | ||
| 76 | |||
| 77 | return 0; | ||
| 78 | } | ||
| 79 | |||
| 80 | static int at91_aic_set_wake(struct irq_data *d, unsigned value) | ||
| 81 | { | ||
| 82 | if (unlikely(d->hwirq >= n_irqs)) | ||
| 83 | return -EINVAL; | ||
| 84 | |||
| 85 | if (value) | ||
| 86 | set_bit(d->hwirq, wakeups); | ||
| 87 | else | ||
| 88 | clear_bit(d->hwirq, wakeups); | ||
| 89 | |||
| 90 | return 0; | ||
| 91 | } | ||
| 92 | |||
| 93 | void at91_irq_suspend(void) | ||
| 94 | { | ||
| 95 | int i = 0, bit; | ||
| 96 | |||
| 97 | if (has_aic5()) { | ||
| 98 | /* disable enabled irqs */ | ||
| 99 | while ((bit = find_next_bit(backups, n_irqs, i)) < n_irqs) { | ||
| 100 | at91_aic_write(AT91_AIC5_SSR, | ||
| 101 | bit & AT91_AIC5_INTSEL_MSK); | ||
| 102 | at91_aic_write(AT91_AIC5_IDCR, 1); | ||
| 103 | i = bit; | ||
| 104 | } | ||
| 105 | /* enable wakeup irqs */ | ||
| 106 | i = 0; | ||
| 107 | while ((bit = find_next_bit(wakeups, n_irqs, i)) < n_irqs) { | ||
| 108 | at91_aic_write(AT91_AIC5_SSR, | ||
| 109 | bit & AT91_AIC5_INTSEL_MSK); | ||
| 110 | at91_aic_write(AT91_AIC5_IECR, 1); | ||
| 111 | i = bit; | ||
| 112 | } | ||
| 113 | } else { | ||
| 114 | at91_aic_write(AT91_AIC_IDCR, *backups); | ||
| 115 | at91_aic_write(AT91_AIC_IECR, *wakeups); | ||
| 116 | } | ||
| 117 | } | ||
| 118 | |||
| 119 | void at91_irq_resume(void) | ||
| 120 | { | ||
| 121 | int i = 0, bit; | ||
| 122 | |||
| 123 | if (has_aic5()) { | ||
| 124 | /* disable wakeup irqs */ | ||
| 125 | while ((bit = find_next_bit(wakeups, n_irqs, i)) < n_irqs) { | ||
| 126 | at91_aic_write(AT91_AIC5_SSR, | ||
| 127 | bit & AT91_AIC5_INTSEL_MSK); | ||
| 128 | at91_aic_write(AT91_AIC5_IDCR, 1); | ||
| 129 | i = bit; | ||
| 130 | } | ||
| 131 | /* enable irqs disabled for suspend */ | ||
| 132 | i = 0; | ||
| 133 | while ((bit = find_next_bit(backups, n_irqs, i)) < n_irqs) { | ||
| 134 | at91_aic_write(AT91_AIC5_SSR, | ||
| 135 | bit & AT91_AIC5_INTSEL_MSK); | ||
| 136 | at91_aic_write(AT91_AIC5_IECR, 1); | ||
| 137 | i = bit; | ||
| 138 | } | ||
| 139 | } else { | ||
| 140 | at91_aic_write(AT91_AIC_IDCR, *wakeups); | ||
| 141 | at91_aic_write(AT91_AIC_IECR, *backups); | ||
| 142 | } | ||
| 143 | } | ||
| 144 | |||
| 145 | #else | ||
| 146 | static inline int at91_aic_pm_init(void) | ||
| 147 | { | ||
| 148 | return 0; | ||
| 149 | } | ||
| 150 | |||
| 151 | #define set_backup(bit) | ||
| 152 | #define clear_backup(bit) | ||
| 153 | #define at91_aic_set_wake NULL | ||
| 154 | |||
| 155 | #endif /* CONFIG_PM */ | ||
| 156 | |||
| 157 | asmlinkage void __exception_irq_entry | ||
| 158 | at91_aic_handle_irq(struct pt_regs *regs) | ||
| 159 | { | ||
| 160 | u32 irqnr; | ||
| 161 | u32 irqstat; | ||
| 162 | |||
| 163 | irqnr = at91_aic_read(AT91_AIC_IVR); | ||
| 164 | irqstat = at91_aic_read(AT91_AIC_ISR); | ||
| 165 | |||
| 166 | /* | ||
| 167 | * ISR value is 0 when there is no current interrupt or when there is | ||
| 168 | * a spurious interrupt | ||
| 169 | */ | ||
| 170 | if (!irqstat) | ||
| 171 | at91_aic_write(AT91_AIC_EOICR, 0); | ||
| 172 | else | ||
| 173 | handle_IRQ(irqnr, regs); | ||
| 174 | } | ||
| 175 | |||
| 176 | asmlinkage void __exception_irq_entry | ||
| 177 | at91_aic5_handle_irq(struct pt_regs *regs) | ||
| 178 | { | ||
| 179 | u32 irqnr; | ||
| 180 | u32 irqstat; | ||
| 181 | |||
| 182 | irqnr = at91_aic_read(AT91_AIC5_IVR); | ||
| 183 | irqstat = at91_aic_read(AT91_AIC5_ISR); | ||
| 184 | |||
| 185 | if (!irqstat) | ||
| 186 | at91_aic_write(AT91_AIC5_EOICR, 0); | ||
| 187 | else | ||
| 188 | handle_IRQ(irqnr, regs); | ||
| 189 | } | ||
| 45 | 190 | ||
| 46 | static void at91_aic_mask_irq(struct irq_data *d) | 191 | static void at91_aic_mask_irq(struct irq_data *d) |
| 47 | { | 192 | { |
| 48 | /* Disable interrupt on AIC */ | 193 | /* Disable interrupt on AIC */ |
| 49 | at91_aic_write(AT91_AIC_IDCR, 1 << d->hwirq); | 194 | at91_aic_write(AT91_AIC_IDCR, 1 << d->hwirq); |
| 195 | /* Update ISR cache */ | ||
| 196 | clear_backup(d->hwirq); | ||
| 197 | } | ||
| 198 | |||
| 199 | static void __maybe_unused at91_aic5_mask_irq(struct irq_data *d) | ||
| 200 | { | ||
| 201 | /* Disable interrupt on AIC5 */ | ||
| 202 | at91_aic_write(AT91_AIC5_SSR, d->hwirq & AT91_AIC5_INTSEL_MSK); | ||
| 203 | at91_aic_write(AT91_AIC5_IDCR, 1); | ||
| 204 | /* Update ISR cache */ | ||
| 205 | clear_backup(d->hwirq); | ||
| 50 | } | 206 | } |
| 51 | 207 | ||
| 52 | static void at91_aic_unmask_irq(struct irq_data *d) | 208 | static void at91_aic_unmask_irq(struct irq_data *d) |
| 53 | { | 209 | { |
| 54 | /* Enable interrupt on AIC */ | 210 | /* Enable interrupt on AIC */ |
| 55 | at91_aic_write(AT91_AIC_IECR, 1 << d->hwirq); | 211 | at91_aic_write(AT91_AIC_IECR, 1 << d->hwirq); |
| 212 | /* Update ISR cache */ | ||
| 213 | set_backup(d->hwirq); | ||
| 214 | } | ||
| 215 | |||
| 216 | static void __maybe_unused at91_aic5_unmask_irq(struct irq_data *d) | ||
| 217 | { | ||
| 218 | /* Enable interrupt on AIC5 */ | ||
| 219 | at91_aic_write(AT91_AIC5_SSR, d->hwirq & AT91_AIC5_INTSEL_MSK); | ||
| 220 | at91_aic_write(AT91_AIC5_IECR, 1); | ||
| 221 | /* Update ISR cache */ | ||
| 222 | set_backup(d->hwirq); | ||
| 56 | } | 223 | } |
| 57 | 224 | ||
| 58 | unsigned int at91_extern_irq; | 225 | static void at91_aic_eoi(struct irq_data *d) |
| 226 | { | ||
| 227 | /* | ||
| 228 | * Mark end-of-interrupt on AIC, the controller doesn't care about | ||
| 229 | * the value written. Moreover it's a write-only register. | ||
| 230 | */ | ||
| 231 | at91_aic_write(AT91_AIC_EOICR, 0); | ||
| 232 | } | ||
| 233 | |||
| 234 | static void __maybe_unused at91_aic5_eoi(struct irq_data *d) | ||
| 235 | { | ||
| 236 | at91_aic_write(AT91_AIC5_EOICR, 0); | ||
| 237 | } | ||
| 59 | 238 | ||
| 60 | #define is_extern_irq(hwirq) ((1 << (hwirq)) & at91_extern_irq) | 239 | unsigned long *at91_extern_irq; |
| 61 | 240 | ||
| 62 | static int at91_aic_set_type(struct irq_data *d, unsigned type) | 241 | #define is_extern_irq(hwirq) test_bit(hwirq, at91_extern_irq) |
| 242 | |||
| 243 | static int at91_aic_compute_srctype(struct irq_data *d, unsigned type) | ||
| 63 | { | 244 | { |
| 64 | unsigned int smr, srctype; | 245 | int srctype; |
| 65 | 246 | ||
| 66 | switch (type) { | 247 | switch (type) { |
| 67 | case IRQ_TYPE_LEVEL_HIGH: | 248 | case IRQ_TYPE_LEVEL_HIGH: |
| @@ -74,65 +255,51 @@ static int at91_aic_set_type(struct irq_data *d, unsigned type) | |||
| 74 | if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */ | 255 | if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */ |
| 75 | srctype = AT91_AIC_SRCTYPE_LOW; | 256 | srctype = AT91_AIC_SRCTYPE_LOW; |
| 76 | else | 257 | else |
| 77 | return -EINVAL; | 258 | srctype = -EINVAL; |
| 78 | break; | 259 | break; |
| 79 | case IRQ_TYPE_EDGE_FALLING: | 260 | case IRQ_TYPE_EDGE_FALLING: |
| 80 | if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */ | 261 | if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */ |
| 81 | srctype = AT91_AIC_SRCTYPE_FALLING; | 262 | srctype = AT91_AIC_SRCTYPE_FALLING; |
| 82 | else | 263 | else |
| 83 | return -EINVAL; | 264 | srctype = -EINVAL; |
| 84 | break; | 265 | break; |
| 85 | default: | 266 | default: |
| 86 | return -EINVAL; | 267 | srctype = -EINVAL; |
| 87 | } | 268 | } |
| 88 | 269 | ||
| 89 | smr = at91_aic_read(AT91_AIC_SMR(d->hwirq)) & ~AT91_AIC_SRCTYPE; | 270 | return srctype; |
| 90 | at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype); | ||
| 91 | return 0; | ||
| 92 | } | 271 | } |
| 93 | 272 | ||
| 94 | #ifdef CONFIG_PM | 273 | static int at91_aic_set_type(struct irq_data *d, unsigned type) |
| 95 | |||
| 96 | static u32 wakeups; | ||
| 97 | static u32 backups; | ||
| 98 | |||
| 99 | static int at91_aic_set_wake(struct irq_data *d, unsigned value) | ||
| 100 | { | 274 | { |
| 101 | if (unlikely(d->hwirq >= NR_AIC_IRQS)) | 275 | unsigned int smr; |
| 102 | return -EINVAL; | 276 | int srctype; |
| 103 | 277 | ||
| 104 | if (value) | 278 | srctype = at91_aic_compute_srctype(d, type); |
| 105 | wakeups |= (1 << d->hwirq); | 279 | if (srctype < 0) |
| 106 | else | 280 | return srctype; |
| 107 | wakeups &= ~(1 << d->hwirq); | 281 | |
| 282 | if (has_aic5()) { | ||
| 283 | at91_aic_write(AT91_AIC5_SSR, | ||
| 284 | d->hwirq & AT91_AIC5_INTSEL_MSK); | ||
| 285 | smr = at91_aic_read(AT91_AIC5_SMR) & ~AT91_AIC_SRCTYPE; | ||
| 286 | at91_aic_write(AT91_AIC5_SMR, smr | srctype); | ||
| 287 | } else { | ||
| 288 | smr = at91_aic_read(AT91_AIC_SMR(d->hwirq)) | ||
| 289 | & ~AT91_AIC_SRCTYPE; | ||
| 290 | at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype); | ||
| 291 | } | ||
| 108 | 292 | ||
| 109 | return 0; | 293 | return 0; |
| 110 | } | 294 | } |
| 111 | 295 | ||
| 112 | void at91_irq_suspend(void) | ||
| 113 | { | ||
| 114 | backups = at91_aic_read(AT91_AIC_IMR); | ||
| 115 | at91_aic_write(AT91_AIC_IDCR, backups); | ||
| 116 | at91_aic_write(AT91_AIC_IECR, wakeups); | ||
| 117 | } | ||
| 118 | |||
| 119 | void at91_irq_resume(void) | ||
| 120 | { | ||
| 121 | at91_aic_write(AT91_AIC_IDCR, wakeups); | ||
| 122 | at91_aic_write(AT91_AIC_IECR, backups); | ||
| 123 | } | ||
| 124 | |||
| 125 | #else | ||
| 126 | #define at91_aic_set_wake NULL | ||
| 127 | #endif | ||
| 128 | |||
| 129 | static struct irq_chip at91_aic_chip = { | 296 | static struct irq_chip at91_aic_chip = { |
| 130 | .name = "AIC", | 297 | .name = "AIC", |
| 131 | .irq_ack = at91_aic_mask_irq, | ||
| 132 | .irq_mask = at91_aic_mask_irq, | 298 | .irq_mask = at91_aic_mask_irq, |
| 133 | .irq_unmask = at91_aic_unmask_irq, | 299 | .irq_unmask = at91_aic_unmask_irq, |
| 134 | .irq_set_type = at91_aic_set_type, | 300 | .irq_set_type = at91_aic_set_type, |
| 135 | .irq_set_wake = at91_aic_set_wake, | 301 | .irq_set_wake = at91_aic_set_wake, |
| 302 | .irq_eoi = at91_aic_eoi, | ||
| 136 | }; | 303 | }; |
| 137 | 304 | ||
| 138 | static void __init at91_aic_hw_init(unsigned int spu_vector) | 305 | static void __init at91_aic_hw_init(unsigned int spu_vector) |
| @@ -161,41 +328,172 @@ static void __init at91_aic_hw_init(unsigned int spu_vector) | |||
| 161 | at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF); | 328 | at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF); |
| 162 | } | 329 | } |
| 163 | 330 | ||
| 331 | static void __init __maybe_unused at91_aic5_hw_init(unsigned int spu_vector) | ||
| 332 | { | ||
| 333 | int i; | ||
| 334 | |||
| 335 | /* | ||
| 336 | * Perform 8 End Of Interrupt Command to make sure AIC | ||
| 337 | * will not Lock out nIRQ | ||
| 338 | */ | ||
| 339 | for (i = 0; i < 8; i++) | ||
| 340 | at91_aic_write(AT91_AIC5_EOICR, 0); | ||
| 341 | |||
| 342 | /* | ||
| 343 | * Spurious Interrupt ID in Spurious Vector Register. | ||
| 344 | * When there is no current interrupt, the IRQ Vector Register | ||
| 345 | * reads the value stored in AIC_SPU | ||
| 346 | */ | ||
| 347 | at91_aic_write(AT91_AIC5_SPU, spu_vector); | ||
| 348 | |||
| 349 | /* No debugging in AIC: Debug (Protect) Control Register */ | ||
| 350 | at91_aic_write(AT91_AIC5_DCR, 0); | ||
| 351 | |||
| 352 | /* Disable and clear all interrupts initially */ | ||
| 353 | for (i = 0; i < n_irqs; i++) { | ||
| 354 | at91_aic_write(AT91_AIC5_SSR, i & AT91_AIC5_INTSEL_MSK); | ||
| 355 | at91_aic_write(AT91_AIC5_IDCR, 1); | ||
| 356 | at91_aic_write(AT91_AIC5_ICCR, 1); | ||
| 357 | } | ||
| 358 | } | ||
| 359 | |||
| 164 | #if defined(CONFIG_OF) | 360 | #if defined(CONFIG_OF) |
| 361 | static unsigned int *at91_aic_irq_priorities; | ||
| 362 | |||
| 165 | static int at91_aic_irq_map(struct irq_domain *h, unsigned int virq, | 363 | static int at91_aic_irq_map(struct irq_domain *h, unsigned int virq, |
| 166 | irq_hw_number_t hw) | 364 | irq_hw_number_t hw) |
| 167 | { | 365 | { |
| 168 | /* Put virq number in Source Vector Register */ | 366 | /* Put virq number in Source Vector Register */ |
| 169 | at91_aic_write(AT91_AIC_SVR(hw), virq); | 367 | at91_aic_write(AT91_AIC_SVR(hw), virq); |
| 170 | 368 | ||
| 171 | /* Active Low interrupt, without priority */ | 369 | /* Active Low interrupt, with priority */ |
| 172 | at91_aic_write(AT91_AIC_SMR(hw), AT91_AIC_SRCTYPE_LOW); | 370 | at91_aic_write(AT91_AIC_SMR(hw), |
| 371 | AT91_AIC_SRCTYPE_LOW | at91_aic_irq_priorities[hw]); | ||
| 173 | 372 | ||
| 174 | irq_set_chip_and_handler(virq, &at91_aic_chip, handle_level_irq); | 373 | irq_set_chip_and_handler(virq, &at91_aic_chip, handle_fasteoi_irq); |
| 175 | set_irq_flags(virq, IRQF_VALID | IRQF_PROBE); | 374 | set_irq_flags(virq, IRQF_VALID | IRQF_PROBE); |
| 176 | 375 | ||
| 177 | return 0; | 376 | return 0; |
| 178 | } | 377 | } |
| 179 | 378 | ||
| 379 | static int at91_aic5_irq_map(struct irq_domain *h, unsigned int virq, | ||
| 380 | irq_hw_number_t hw) | ||
| 381 | { | ||
| 382 | at91_aic_write(AT91_AIC5_SSR, hw & AT91_AIC5_INTSEL_MSK); | ||
| 383 | |||
| 384 | /* Put virq number in Source Vector Register */ | ||
| 385 | at91_aic_write(AT91_AIC5_SVR, virq); | ||
| 386 | |||
| 387 | /* Active Low interrupt, with priority */ | ||
| 388 | at91_aic_write(AT91_AIC5_SMR, | ||
| 389 | AT91_AIC_SRCTYPE_LOW | at91_aic_irq_priorities[hw]); | ||
| 390 | |||
| 391 | irq_set_chip_and_handler(virq, &at91_aic_chip, handle_fasteoi_irq); | ||
| 392 | set_irq_flags(virq, IRQF_VALID | IRQF_PROBE); | ||
| 393 | |||
| 394 | return 0; | ||
| 395 | } | ||
| 396 | |||
| 397 | static int at91_aic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, | ||
| 398 | const u32 *intspec, unsigned int intsize, | ||
| 399 | irq_hw_number_t *out_hwirq, unsigned int *out_type) | ||
| 400 | { | ||
| 401 | if (WARN_ON(intsize < 3)) | ||
| 402 | return -EINVAL; | ||
| 403 | if (WARN_ON(intspec[0] >= n_irqs)) | ||
| 404 | return -EINVAL; | ||
| 405 | if (WARN_ON((intspec[2] < AT91_AIC_IRQ_MIN_PRIORITY) | ||
| 406 | || (intspec[2] > AT91_AIC_IRQ_MAX_PRIORITY))) | ||
| 407 | return -EINVAL; | ||
| 408 | |||
| 409 | *out_hwirq = intspec[0]; | ||
| 410 | *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK; | ||
| 411 | at91_aic_irq_priorities[*out_hwirq] = intspec[2]; | ||
| 412 | |||
| 413 | return 0; | ||
| 414 | } | ||
| 415 | |||
| 180 | static struct irq_domain_ops at91_aic_irq_ops = { | 416 | static struct irq_domain_ops at91_aic_irq_ops = { |
| 181 | .map = at91_aic_irq_map, | 417 | .map = at91_aic_irq_map, |
| 182 | .xlate = irq_domain_xlate_twocell, | 418 | .xlate = at91_aic_irq_domain_xlate, |
| 183 | }; | 419 | }; |
| 184 | 420 | ||
| 185 | int __init at91_aic_of_init(struct device_node *node, | 421 | int __init at91_aic_of_common_init(struct device_node *node, |
| 186 | struct device_node *parent) | 422 | struct device_node *parent) |
| 187 | { | 423 | { |
| 424 | struct property *prop; | ||
| 425 | const __be32 *p; | ||
| 426 | u32 val; | ||
| 427 | |||
| 428 | at91_extern_irq = kzalloc(BITS_TO_LONGS(n_irqs) | ||
| 429 | * sizeof(*at91_extern_irq), GFP_KERNEL); | ||
| 430 | if (!at91_extern_irq) | ||
| 431 | return -ENOMEM; | ||
| 432 | |||
| 433 | if (at91_aic_pm_init()) { | ||
| 434 | kfree(at91_extern_irq); | ||
| 435 | return -ENOMEM; | ||
| 436 | } | ||
| 437 | |||
| 438 | at91_aic_irq_priorities = kzalloc(n_irqs | ||
| 439 | * sizeof(*at91_aic_irq_priorities), | ||
| 440 | GFP_KERNEL); | ||
| 441 | if (!at91_aic_irq_priorities) | ||
| 442 | return -ENOMEM; | ||
| 443 | |||
| 188 | at91_aic_base = of_iomap(node, 0); | 444 | at91_aic_base = of_iomap(node, 0); |
| 189 | at91_aic_np = node; | 445 | at91_aic_np = node; |
| 190 | 446 | ||
| 191 | at91_aic_domain = irq_domain_add_linear(at91_aic_np, NR_AIC_IRQS, | 447 | at91_aic_domain = irq_domain_add_linear(at91_aic_np, n_irqs, |
| 192 | &at91_aic_irq_ops, NULL); | 448 | &at91_aic_irq_ops, NULL); |
| 193 | if (!at91_aic_domain) | 449 | if (!at91_aic_domain) |
| 194 | panic("Unable to add AIC irq domain (DT)\n"); | 450 | panic("Unable to add AIC irq domain (DT)\n"); |
| 195 | 451 | ||
| 452 | of_property_for_each_u32(node, "atmel,external-irqs", prop, p, val) { | ||
| 453 | if (val >= n_irqs) | ||
| 454 | pr_warn("AIC: external irq %d >= %d skip it\n", | ||
| 455 | val, n_irqs); | ||
| 456 | else | ||
| 457 | set_bit(val, at91_extern_irq); | ||
| 458 | } | ||
| 459 | |||
| 196 | irq_set_default_host(at91_aic_domain); | 460 | irq_set_default_host(at91_aic_domain); |
| 197 | 461 | ||
| 198 | at91_aic_hw_init(NR_AIC_IRQS); | 462 | return 0; |
| 463 | } | ||
| 464 | |||
| 465 | int __init at91_aic_of_init(struct device_node *node, | ||
| 466 | struct device_node *parent) | ||
| 467 | { | ||
| 468 | int err; | ||
| 469 | |||
| 470 | err = at91_aic_of_common_init(node, parent); | ||
| 471 | if (err) | ||
| 472 | return err; | ||
| 473 | |||
| 474 | at91_aic_hw_init(n_irqs); | ||
| 475 | |||
| 476 | return 0; | ||
| 477 | } | ||
| 478 | |||
| 479 | int __init at91_aic5_of_init(struct device_node *node, | ||
| 480 | struct device_node *parent) | ||
| 481 | { | ||
| 482 | int err; | ||
| 483 | |||
| 484 | at91_aic_caps |= AT91_AIC_CAP_AIC5; | ||
| 485 | n_irqs = NR_AIC5_IRQS; | ||
| 486 | at91_aic_chip.irq_ack = at91_aic5_mask_irq; | ||
| 487 | at91_aic_chip.irq_mask = at91_aic5_mask_irq; | ||
| 488 | at91_aic_chip.irq_unmask = at91_aic5_unmask_irq; | ||
| 489 | at91_aic_chip.irq_eoi = at91_aic5_eoi; | ||
| 490 | at91_aic_irq_ops.map = at91_aic5_irq_map; | ||
| 491 | |||
| 492 | err = at91_aic_of_common_init(node, parent); | ||
| 493 | if (err) | ||
| 494 | return err; | ||
| 495 | |||
| 496 | at91_aic5_hw_init(n_irqs); | ||
| 199 | 497 | ||
| 200 | return 0; | 498 | return 0; |
| 201 | } | 499 | } |
| @@ -204,22 +502,25 @@ int __init at91_aic_of_init(struct device_node *node, | |||
| 204 | /* | 502 | /* |
| 205 | * Initialize the AIC interrupt controller. | 503 | * Initialize the AIC interrupt controller. |
| 206 | */ | 504 | */ |
| 207 | void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS]) | 505 | void __init at91_aic_init(unsigned int *priority) |
| 208 | { | 506 | { |
| 209 | unsigned int i; | 507 | unsigned int i; |
| 210 | int irq_base; | 508 | int irq_base; |
| 211 | 509 | ||
| 510 | if (at91_aic_pm_init()) | ||
| 511 | panic("Unable to allocate bit maps\n"); | ||
| 512 | |||
| 212 | at91_aic_base = ioremap(AT91_AIC, 512); | 513 | at91_aic_base = ioremap(AT91_AIC, 512); |
| 213 | if (!at91_aic_base) | 514 | if (!at91_aic_base) |
| 214 | panic("Unable to ioremap AIC registers\n"); | 515 | panic("Unable to ioremap AIC registers\n"); |
| 215 | 516 | ||
| 216 | /* Add irq domain for AIC */ | 517 | /* Add irq domain for AIC */ |
| 217 | irq_base = irq_alloc_descs(-1, 0, NR_AIC_IRQS, 0); | 518 | irq_base = irq_alloc_descs(-1, 0, n_irqs, 0); |
| 218 | if (irq_base < 0) { | 519 | if (irq_base < 0) { |
| 219 | WARN(1, "Cannot allocate irq_descs, assuming pre-allocated\n"); | 520 | WARN(1, "Cannot allocate irq_descs, assuming pre-allocated\n"); |
| 220 | irq_base = 0; | 521 | irq_base = 0; |
| 221 | } | 522 | } |
| 222 | at91_aic_domain = irq_domain_add_legacy(at91_aic_np, NR_AIC_IRQS, | 523 | at91_aic_domain = irq_domain_add_legacy(at91_aic_np, n_irqs, |
| 223 | irq_base, 0, | 524 | irq_base, 0, |
| 224 | &irq_domain_simple_ops, NULL); | 525 | &irq_domain_simple_ops, NULL); |
| 225 | 526 | ||
| @@ -232,15 +533,14 @@ void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS]) | |||
| 232 | * The IVR is used by macro get_irqnr_and_base to read and verify. | 533 | * The IVR is used by macro get_irqnr_and_base to read and verify. |
| 233 | * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred. | 534 | * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred. |
| 234 | */ | 535 | */ |
| 235 | for (i = 0; i < NR_AIC_IRQS; i++) { | 536 | for (i = 0; i < n_irqs; i++) { |
| 236 | /* Put hardware irq number in Source Vector Register: */ | 537 | /* Put hardware irq number in Source Vector Register: */ |
| 237 | at91_aic_write(AT91_AIC_SVR(i), i); | 538 | at91_aic_write(AT91_AIC_SVR(i), NR_IRQS_LEGACY + i); |
| 238 | /* Active Low interrupt, with the specified priority */ | 539 | /* Active Low interrupt, with the specified priority */ |
| 239 | at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); | 540 | at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); |
| 240 | 541 | irq_set_chip_and_handler(NR_IRQS_LEGACY + i, &at91_aic_chip, handle_fasteoi_irq); | |
| 241 | irq_set_chip_and_handler(i, &at91_aic_chip, handle_level_irq); | ||
| 242 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 542 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
| 243 | } | 543 | } |
| 244 | 544 | ||
| 245 | at91_aic_hw_init(NR_AIC_IRQS); | 545 | at91_aic_hw_init(n_irqs); |
| 246 | } | 546 | } |
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 1bfaad628731..2c2d86505a54 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | #include <asm/mach/time.h> | 25 | #include <asm/mach/time.h> |
| 26 | #include <asm/mach/irq.h> | 26 | #include <asm/mach/irq.h> |
| 27 | 27 | ||
| 28 | #include <mach/at91_aic.h> | ||
| 28 | #include <mach/at91_pmc.h> | 29 | #include <mach/at91_pmc.h> |
| 29 | #include <mach/cpu.h> | 30 | #include <mach/cpu.h> |
| 30 | 31 | ||
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c index c965fd8eb31a..f15293bd7974 100644 --- a/arch/arm/mach-clps711x/common.c +++ b/arch/arm/mach-clps711x/common.c | |||
| @@ -26,7 +26,6 @@ | |||
| 26 | #include <linux/io.h> | 26 | #include <linux/io.h> |
| 27 | #include <linux/irq.h> | 27 | #include <linux/irq.h> |
| 28 | #include <linux/sched.h> | 28 | #include <linux/sched.h> |
| 29 | #include <linux/timex.h> | ||
| 30 | 29 | ||
| 31 | #include <asm/sizes.h> | 30 | #include <asm/sizes.h> |
| 32 | #include <mach/hardware.h> | 31 | #include <mach/hardware.h> |
| @@ -188,7 +187,6 @@ static struct irqaction clps711x_timer_irq = { | |||
| 188 | 187 | ||
| 189 | static void __init clps711x_timer_init(void) | 188 | static void __init clps711x_timer_init(void) |
| 190 | { | 189 | { |
| 191 | struct timespec tv; | ||
| 192 | unsigned int syscon; | 190 | unsigned int syscon; |
| 193 | 191 | ||
| 194 | syscon = clps_readl(SYSCON1); | 192 | syscon = clps_readl(SYSCON1); |
| @@ -198,10 +196,6 @@ static void __init clps711x_timer_init(void) | |||
| 198 | clps_writel(LATCH-1, TC2D); /* 512kHz / 100Hz - 1 */ | 196 | clps_writel(LATCH-1, TC2D); /* 512kHz / 100Hz - 1 */ |
| 199 | 197 | ||
| 200 | setup_irq(IRQ_TC2OI, &clps711x_timer_irq); | 198 | setup_irq(IRQ_TC2OI, &clps711x_timer_irq); |
| 201 | |||
| 202 | tv.tv_nsec = 0; | ||
| 203 | tv.tv_sec = clps_readl(RTCDR); | ||
| 204 | do_settimeofday(&tv); | ||
| 205 | } | 199 | } |
| 206 | 200 | ||
| 207 | struct sys_timer clps711x_timer = { | 201 | struct sys_timer clps711x_timer = { |
diff --git a/arch/arm/mach-clps711x/include/mach/memory.h b/arch/arm/mach-clps711x/include/mach/memory.h index 3a032a67725c..fc0e028d9405 100644 --- a/arch/arm/mach-clps711x/include/mach/memory.h +++ b/arch/arm/mach-clps711x/include/mach/memory.h | |||
| @@ -25,26 +25,6 @@ | |||
| 25 | */ | 25 | */ |
| 26 | #define PLAT_PHYS_OFFSET UL(0xc0000000) | 26 | #define PLAT_PHYS_OFFSET UL(0xc0000000) |
| 27 | 27 | ||
| 28 | #if !defined(CONFIG_ARCH_CDB89712) && !defined (CONFIG_ARCH_AUTCPU12) | ||
| 29 | |||
| 30 | #define __virt_to_bus(x) ((x) - PAGE_OFFSET) | ||
| 31 | #define __bus_to_virt(x) ((x) + PAGE_OFFSET) | ||
| 32 | #define __pfn_to_bus(x) (__pfn_to_phys(x) - PHYS_OFFSET) | ||
| 33 | #define __bus_to_pfn(x) __phys_to_pfn((x) + PHYS_OFFSET) | ||
| 34 | |||
| 35 | #endif | ||
| 36 | |||
| 37 | |||
| 38 | /* | ||
| 39 | * Like the SA1100, the EDB7211 has a large gap between physical RAM | ||
| 40 | * banks. In 2.2, the Psion (CL-PS7110) port added custom support for | ||
| 41 | * discontiguous physical memory. In 2.4, we can use the standard | ||
| 42 | * Linux NUMA support. | ||
| 43 | * | ||
| 44 | * This is not necessary for EP7211 implementations with only one used | ||
| 45 | * memory bank. For those systems, simply undefine CONFIG_DISCONTIGMEM. | ||
| 46 | */ | ||
| 47 | |||
| 48 | /* | 28 | /* |
| 49 | * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211 | 29 | * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211 |
| 50 | * uses only one of the two banks (bank #1). However, even within | 30 | * uses only one of the two banks (bank #1). However, even within |
| @@ -54,23 +34,6 @@ | |||
| 54 | * them, so we use 24 for the node max shift to get 16MB node sizes. | 34 | * them, so we use 24 for the node max shift to get 16MB node sizes. |
| 55 | */ | 35 | */ |
| 56 | 36 | ||
| 57 | /* | ||
| 58 | * Because of the wide memory address space between physical RAM banks on the | ||
| 59 | * SA1100, it's much more convenient to use Linux's NUMA support to implement | ||
| 60 | * our memory map representation. Assuming all memory nodes have equal access | ||
| 61 | * characteristics, we then have generic discontiguous memory support. | ||
| 62 | * | ||
| 63 | * Of course, all this isn't mandatory for SA1100 implementations with only | ||
| 64 | * one used memory bank. For those, simply undefine CONFIG_DISCONTIGMEM. | ||
| 65 | * | ||
| 66 | * The nodes are matched with the physical memory bank addresses which are | ||
| 67 | * incidentally the same as virtual addresses. | ||
| 68 | * | ||
| 69 | * node 0: 0xc0000000 - 0xc7ffffff | ||
| 70 | * node 1: 0xc8000000 - 0xcfffffff | ||
| 71 | * node 2: 0xd0000000 - 0xd7ffffff | ||
| 72 | * node 3: 0xd8000000 - 0xdfffffff | ||
| 73 | */ | ||
| 74 | #define SECTION_SIZE_BITS 24 | 37 | #define SECTION_SIZE_BITS 24 |
| 75 | #define MAX_PHYSMEM_BITS 32 | 38 | #define MAX_PHYSMEM_BITS 32 |
| 76 | 39 | ||
diff --git a/arch/arm/mach-clps711x/p720t.c b/arch/arm/mach-clps711x/p720t.c index 42ee8f33eafb..f266d90b9efc 100644 --- a/arch/arm/mach-clps711x/p720t.c +++ b/arch/arm/mach-clps711x/p720t.c | |||
| @@ -86,17 +86,7 @@ static void __init p720t_map_io(void) | |||
| 86 | iotable_init(p720t_io_desc, ARRAY_SIZE(p720t_io_desc)); | 86 | iotable_init(p720t_io_desc, ARRAY_SIZE(p720t_io_desc)); |
| 87 | } | 87 | } |
| 88 | 88 | ||
| 89 | MACHINE_START(P720T, "ARM-Prospector720T") | 89 | static void __init p720t_init_early(void) |
| 90 | /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ | ||
| 91 | .atag_offset = 0x100, | ||
| 92 | .fixup = fixup_p720t, | ||
| 93 | .map_io = p720t_map_io, | ||
| 94 | .init_irq = clps711x_init_irq, | ||
| 95 | .timer = &clps711x_timer, | ||
| 96 | .restart = clps711x_restart, | ||
| 97 | MACHINE_END | ||
| 98 | |||
| 99 | static int p720t_hw_init(void) | ||
| 100 | { | 90 | { |
| 101 | /* | 91 | /* |
| 102 | * Power down as much as possible in case we don't | 92 | * Power down as much as possible in case we don't |
| @@ -111,13 +101,19 @@ static int p720t_hw_init(void) | |||
| 111 | PLD_CODEC = 0; | 101 | PLD_CODEC = 0; |
| 112 | PLD_TCH = 0; | 102 | PLD_TCH = 0; |
| 113 | PLD_SPI = 0; | 103 | PLD_SPI = 0; |
| 114 | #ifndef CONFIG_DEBUG_LL | 104 | if (!IS_ENABLED(CONFIG_DEBUG_LL)) { |
| 115 | PLD_COM2 = 0; | 105 | PLD_COM2 = 0; |
| 116 | PLD_COM1 = 0; | 106 | PLD_COM1 = 0; |
| 117 | #endif | 107 | } |
| 118 | |||
| 119 | return 0; | ||
| 120 | } | 108 | } |
| 121 | 109 | ||
| 122 | __initcall(p720t_hw_init); | 110 | MACHINE_START(P720T, "ARM-Prospector720T") |
| 123 | 111 | /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ | |
| 112 | .atag_offset = 0x100, | ||
| 113 | .fixup = fixup_p720t, | ||
| 114 | .init_early = p720t_init_early, | ||
| 115 | .map_io = p720t_map_io, | ||
| 116 | .init_irq = clps711x_init_irq, | ||
| 117 | .timer = &clps711x_timer, | ||
| 118 | .restart = clps711x_restart, | ||
| 119 | MACHINE_END | ||
diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h deleted file mode 100644 index b9bf3d6a4423..000000000000 --- a/arch/arm/mach-davinci/include/mach/dm365.h +++ /dev/null | |||
| @@ -1 +0,0 @@ | |||
| 1 | /* empty, remove once unused */ | ||
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h deleted file mode 100644 index b9bf3d6a4423..000000000000 --- a/arch/arm/mach-davinci/include/mach/dm646x.h +++ /dev/null | |||
| @@ -1 +0,0 @@ | |||
| 1 | /* empty, remove once unused */ | ||
diff --git a/arch/arm/mach-davinci/include/mach/entry-macro.S b/arch/arm/mach-davinci/include/mach/entry-macro.S index 768b3c060214..cf5f573eb5fd 100644 --- a/arch/arm/mach-davinci/include/mach/entry-macro.S +++ b/arch/arm/mach-davinci/include/mach/entry-macro.S | |||
| @@ -30,12 +30,10 @@ | |||
| 30 | #endif | 30 | #endif |
| 31 | #if defined(CONFIG_CP_INTC) | 31 | #if defined(CONFIG_CP_INTC) |
| 32 | 1001: ldr \irqnr, [\base, #0x80] /* get irq number */ | 32 | 1001: ldr \irqnr, [\base, #0x80] /* get irq number */ |
| 33 | mov \tmp, \irqnr, lsr #31 | ||
| 33 | and \irqnr, \irqnr, #0xff /* irq is in bits 0-9 */ | 34 | and \irqnr, \irqnr, #0xff /* irq is in bits 0-9 */ |
| 34 | mov \tmp, \irqnr, lsr #3 | 35 | and \tmp, \tmp, #0x1 |
| 35 | and \tmp, \tmp, #0xfc | 36 | cmp \tmp, #0x1 |
| 36 | add \tmp, \tmp, #0x280 /* get the register offset */ | ||
| 37 | ldr \irqstat, [\base, \tmp] /* get the intc status */ | ||
| 38 | cmp \irqstat, #0x0 | ||
| 39 | #endif | 37 | #endif |
| 40 | 1002: | 38 | 1002: |
| 41 | .endm | 39 | .endm |
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index 4dd07a0e3604..4afe52aaaff3 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c | |||
| @@ -797,6 +797,102 @@ static struct platform_device ep93xx_wdt_device = { | |||
| 797 | .resource = ep93xx_wdt_resources, | 797 | .resource = ep93xx_wdt_resources, |
| 798 | }; | 798 | }; |
| 799 | 799 | ||
| 800 | /************************************************************************* | ||
| 801 | * EP93xx IDE | ||
| 802 | *************************************************************************/ | ||
| 803 | static struct resource ep93xx_ide_resources[] = { | ||
| 804 | DEFINE_RES_MEM(EP93XX_IDE_PHYS_BASE, 0x38), | ||
| 805 | DEFINE_RES_IRQ(IRQ_EP93XX_EXT3), | ||
| 806 | }; | ||
| 807 | |||
| 808 | static struct platform_device ep93xx_ide_device = { | ||
| 809 | .name = "ep93xx-ide", | ||
| 810 | .id = -1, | ||
| 811 | .dev = { | ||
| 812 | .dma_mask = &ep93xx_ide_device.dev.coherent_dma_mask, | ||
| 813 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 814 | }, | ||
| 815 | .num_resources = ARRAY_SIZE(ep93xx_ide_resources), | ||
| 816 | .resource = ep93xx_ide_resources, | ||
| 817 | }; | ||
| 818 | |||
| 819 | void __init ep93xx_register_ide(void) | ||
| 820 | { | ||
| 821 | platform_device_register(&ep93xx_ide_device); | ||
| 822 | } | ||
| 823 | |||
| 824 | int ep93xx_ide_acquire_gpio(struct platform_device *pdev) | ||
| 825 | { | ||
| 826 | int err; | ||
| 827 | int i; | ||
| 828 | |||
| 829 | err = gpio_request(EP93XX_GPIO_LINE_EGPIO2, dev_name(&pdev->dev)); | ||
| 830 | if (err) | ||
| 831 | return err; | ||
| 832 | err = gpio_request(EP93XX_GPIO_LINE_EGPIO15, dev_name(&pdev->dev)); | ||
| 833 | if (err) | ||
| 834 | goto fail_egpio15; | ||
| 835 | for (i = 2; i < 8; i++) { | ||
| 836 | err = gpio_request(EP93XX_GPIO_LINE_E(i), dev_name(&pdev->dev)); | ||
| 837 | if (err) | ||
| 838 | goto fail_gpio_e; | ||
| 839 | } | ||
| 840 | for (i = 4; i < 8; i++) { | ||
| 841 | err = gpio_request(EP93XX_GPIO_LINE_G(i), dev_name(&pdev->dev)); | ||
| 842 | if (err) | ||
| 843 | goto fail_gpio_g; | ||
| 844 | } | ||
| 845 | for (i = 0; i < 8; i++) { | ||
| 846 | err = gpio_request(EP93XX_GPIO_LINE_H(i), dev_name(&pdev->dev)); | ||
| 847 | if (err) | ||
| 848 | goto fail_gpio_h; | ||
| 849 | } | ||
| 850 | |||
| 851 | /* GPIO ports E[7:2], G[7:4] and H used by IDE */ | ||
| 852 | ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_EONIDE | | ||
| 853 | EP93XX_SYSCON_DEVCFG_GONIDE | | ||
| 854 | EP93XX_SYSCON_DEVCFG_HONIDE); | ||
| 855 | return 0; | ||
| 856 | |||
| 857 | fail_gpio_h: | ||
| 858 | for (--i; i >= 0; --i) | ||
| 859 | gpio_free(EP93XX_GPIO_LINE_H(i)); | ||
| 860 | i = 8; | ||
| 861 | fail_gpio_g: | ||
| 862 | for (--i; i >= 4; --i) | ||
| 863 | gpio_free(EP93XX_GPIO_LINE_G(i)); | ||
| 864 | i = 8; | ||
| 865 | fail_gpio_e: | ||
| 866 | for (--i; i >= 2; --i) | ||
| 867 | gpio_free(EP93XX_GPIO_LINE_E(i)); | ||
| 868 | gpio_free(EP93XX_GPIO_LINE_EGPIO15); | ||
| 869 | fail_egpio15: | ||
| 870 | gpio_free(EP93XX_GPIO_LINE_EGPIO2); | ||
| 871 | return err; | ||
| 872 | } | ||
| 873 | EXPORT_SYMBOL(ep93xx_ide_acquire_gpio); | ||
| 874 | |||
| 875 | void ep93xx_ide_release_gpio(struct platform_device *pdev) | ||
| 876 | { | ||
| 877 | int i; | ||
| 878 | |||
| 879 | for (i = 2; i < 8; i++) | ||
| 880 | gpio_free(EP93XX_GPIO_LINE_E(i)); | ||
| 881 | for (i = 4; i < 8; i++) | ||
| 882 | gpio_free(EP93XX_GPIO_LINE_G(i)); | ||
| 883 | for (i = 0; i < 8; i++) | ||
| 884 | gpio_free(EP93XX_GPIO_LINE_H(i)); | ||
| 885 | gpio_free(EP93XX_GPIO_LINE_EGPIO15); | ||
| 886 | gpio_free(EP93XX_GPIO_LINE_EGPIO2); | ||
| 887 | |||
| 888 | |||
| 889 | /* GPIO ports E[7:2], G[7:4] and H used by GPIO */ | ||
| 890 | ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_EONIDE | | ||
| 891 | EP93XX_SYSCON_DEVCFG_GONIDE | | ||
| 892 | EP93XX_SYSCON_DEVCFG_HONIDE); | ||
| 893 | } | ||
| 894 | EXPORT_SYMBOL(ep93xx_ide_release_gpio); | ||
| 895 | |||
| 800 | void __init ep93xx_init_devices(void) | 896 | void __init ep93xx_init_devices(void) |
| 801 | { | 897 | { |
| 802 | /* Disallow access to MaverickCrunch initially */ | 898 | /* Disallow access to MaverickCrunch initially */ |
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c index d74c5cddb98b..337ab7cf4c16 100644 --- a/arch/arm/mach-ep93xx/edb93xx.c +++ b/arch/arm/mach-ep93xx/edb93xx.c | |||
| @@ -91,8 +91,8 @@ static void __init edb93xx_register_i2c(void) | |||
| 91 | ep93xx_register_i2c(&edb93xx_i2c_gpio_data, | 91 | ep93xx_register_i2c(&edb93xx_i2c_gpio_data, |
| 92 | edb93xxa_i2c_board_info, | 92 | edb93xxa_i2c_board_info, |
| 93 | ARRAY_SIZE(edb93xxa_i2c_board_info)); | 93 | ARRAY_SIZE(edb93xxa_i2c_board_info)); |
| 94 | } else if (machine_is_edb9307() || machine_is_edb9312() || | 94 | } else if (machine_is_edb9302() || machine_is_edb9307() |
| 95 | machine_is_edb9315()) { | 95 | || machine_is_edb9312() || machine_is_edb9315()) { |
| 96 | ep93xx_register_i2c(&edb93xx_i2c_gpio_data, | 96 | ep93xx_register_i2c(&edb93xx_i2c_gpio_data, |
| 97 | edb93xx_i2c_board_info, | 97 | edb93xx_i2c_board_info, |
| 98 | ARRAY_SIZE(edb93xx_i2c_board_info)); | 98 | ARRAY_SIZE(edb93xx_i2c_board_info)); |
| @@ -233,6 +233,29 @@ static void __init edb93xx_register_fb(void) | |||
| 233 | } | 233 | } |
| 234 | 234 | ||
| 235 | 235 | ||
| 236 | /************************************************************************* | ||
| 237 | * EDB93xx IDE | ||
| 238 | *************************************************************************/ | ||
| 239 | static int __init edb93xx_has_ide(void) | ||
| 240 | { | ||
| 241 | /* | ||
| 242 | * Although EDB9312 and EDB9315 do have IDE capability, they have | ||
| 243 | * INTRQ line wired as pull-up, which makes using IDE interface | ||
| 244 | * problematic. | ||
| 245 | */ | ||
| 246 | return machine_is_edb9312() || machine_is_edb9315() || | ||
| 247 | machine_is_edb9315a(); | ||
| 248 | } | ||
| 249 | |||
| 250 | static void __init edb93xx_register_ide(void) | ||
| 251 | { | ||
| 252 | if (!edb93xx_has_ide()) | ||
| 253 | return; | ||
| 254 | |||
| 255 | ep93xx_register_ide(); | ||
| 256 | } | ||
| 257 | |||
| 258 | |||
| 236 | static void __init edb93xx_init_machine(void) | 259 | static void __init edb93xx_init_machine(void) |
| 237 | { | 260 | { |
| 238 | ep93xx_init_devices(); | 261 | ep93xx_init_devices(); |
| @@ -243,6 +266,7 @@ static void __init edb93xx_init_machine(void) | |||
| 243 | edb93xx_register_i2s(); | 266 | edb93xx_register_i2s(); |
| 244 | edb93xx_register_pwm(); | 267 | edb93xx_register_pwm(); |
| 245 | edb93xx_register_fb(); | 268 | edb93xx_register_fb(); |
| 269 | edb93xx_register_ide(); | ||
| 246 | } | 270 | } |
| 247 | 271 | ||
| 248 | 272 | ||
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h index 1ecb040d98bf..33a5122c6dc8 100644 --- a/arch/arm/mach-ep93xx/include/mach/platform.h +++ b/arch/arm/mach-ep93xx/include/mach/platform.h | |||
| @@ -48,6 +48,9 @@ void ep93xx_register_i2s(void); | |||
| 48 | int ep93xx_i2s_acquire(void); | 48 | int ep93xx_i2s_acquire(void); |
| 49 | void ep93xx_i2s_release(void); | 49 | void ep93xx_i2s_release(void); |
| 50 | void ep93xx_register_ac97(void); | 50 | void ep93xx_register_ac97(void); |
| 51 | void ep93xx_register_ide(void); | ||
| 52 | int ep93xx_ide_acquire_gpio(struct platform_device *pdev); | ||
| 53 | void ep93xx_ide_release_gpio(struct platform_device *pdev); | ||
| 51 | 54 | ||
| 52 | void ep93xx_init_devices(void); | 55 | void ep93xx_init_devices(void); |
| 53 | extern struct sys_timer ep93xx_timer; | 56 | extern struct sys_timer ep93xx_timer; |
diff --git a/arch/arm/mach-ep93xx/soc.h b/arch/arm/mach-ep93xx/soc.h index 979fba722926..7bf7ff8beae7 100644 --- a/arch/arm/mach-ep93xx/soc.h +++ b/arch/arm/mach-ep93xx/soc.h | |||
| @@ -69,6 +69,7 @@ | |||
| 69 | 69 | ||
| 70 | #define EP93XX_BOOT_ROM_BASE EP93XX_AHB_IOMEM(0x00090000) | 70 | #define EP93XX_BOOT_ROM_BASE EP93XX_AHB_IOMEM(0x00090000) |
| 71 | 71 | ||
| 72 | #define EP93XX_IDE_PHYS_BASE EP93XX_AHB_PHYS(0x000a0000) | ||
| 72 | #define EP93XX_IDE_BASE EP93XX_AHB_IOMEM(0x000a0000) | 73 | #define EP93XX_IDE_BASE EP93XX_AHB_IOMEM(0x000a0000) |
| 73 | 74 | ||
| 74 | #define EP93XX_VIC1_BASE EP93XX_AHB_IOMEM(0x000b0000) | 75 | #define EP93XX_VIC1_BASE EP93XX_AHB_IOMEM(0x000b0000) |
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 742edd3bbec3..4eb39cdf75ea 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c | |||
| @@ -540,7 +540,8 @@ static struct irq_domain_ops combiner_irq_domain_ops = { | |||
| 540 | .map = combiner_irq_domain_map, | 540 | .map = combiner_irq_domain_map, |
| 541 | }; | 541 | }; |
| 542 | 542 | ||
| 543 | void __init combiner_init(void __iomem *combiner_base, struct device_node *np) | 543 | static void __init combiner_init(void __iomem *combiner_base, |
| 544 | struct device_node *np) | ||
| 544 | { | 545 | { |
| 545 | int i, irq, irq_base; | 546 | int i, irq, irq_base; |
| 546 | unsigned int max_nr, nr_irq; | 547 | unsigned int max_nr, nr_irq; |
| @@ -712,31 +713,6 @@ static int __init exynos4_l2x0_cache_init(void) | |||
| 712 | early_initcall(exynos4_l2x0_cache_init); | 713 | early_initcall(exynos4_l2x0_cache_init); |
| 713 | #endif | 714 | #endif |
| 714 | 715 | ||
| 715 | static int __init exynos5_l2_cache_init(void) | ||
| 716 | { | ||
| 717 | unsigned int val; | ||
| 718 | |||
| 719 | if (!soc_is_exynos5250()) | ||
| 720 | return 0; | ||
| 721 | |||
| 722 | asm volatile("mrc p15, 0, %0, c1, c0, 0\n" | ||
| 723 | "bic %0, %0, #(1 << 2)\n" /* cache disable */ | ||
| 724 | "mcr p15, 0, %0, c1, c0, 0\n" | ||
| 725 | "mrc p15, 1, %0, c9, c0, 2\n" | ||
| 726 | : "=r"(val)); | ||
| 727 | |||
| 728 | val |= (1 << 9) | (1 << 5) | (2 << 6) | (2 << 0); | ||
| 729 | |||
| 730 | asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val)); | ||
| 731 | asm volatile("mrc p15, 0, %0, c1, c0, 0\n" | ||
| 732 | "orr %0, %0, #(1 << 2)\n" /* cache enable */ | ||
| 733 | "mcr p15, 0, %0, c1, c0, 0\n" | ||
| 734 | : : "r"(val)); | ||
| 735 | |||
| 736 | return 0; | ||
| 737 | } | ||
| 738 | early_initcall(exynos5_l2_cache_init); | ||
| 739 | |||
| 740 | static int __init exynos_init(void) | 716 | static int __init exynos_init(void) |
| 741 | { | 717 | { |
| 742 | printk(KERN_INFO "EXYNOS: Initializing architecture\n"); | 718 | printk(KERN_INFO "EXYNOS: Initializing architecture\n"); |
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h index 43a99e6f56ab..d4e392b811a3 100644 --- a/arch/arm/mach-exynos/include/mach/regs-pmu.h +++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h | |||
| @@ -232,6 +232,11 @@ | |||
| 232 | 232 | ||
| 233 | #define EXYNOS5_USB_CFG S5P_PMUREG(0x0230) | 233 | #define EXYNOS5_USB_CFG S5P_PMUREG(0x0230) |
| 234 | 234 | ||
| 235 | #define EXYNOS5_AUTO_WDTRESET_DISABLE S5P_PMUREG(0x0408) | ||
| 236 | #define EXYNOS5_MASK_WDTRESET_REQUEST S5P_PMUREG(0x040C) | ||
| 237 | |||
| 238 | #define EXYNOS5_SYS_WDTRESET (1 << 20) | ||
| 239 | |||
| 235 | #define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000) | 240 | #define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000) |
| 236 | #define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004) | 241 | #define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004) |
| 237 | #define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008) | 242 | #define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008) |
diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h index c337cf3a71bf..07277735252e 100644 --- a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h +++ b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h | |||
| @@ -35,11 +35,21 @@ | |||
| 35 | #define PHY1_COMMON_ON_N (1 << 7) | 35 | #define PHY1_COMMON_ON_N (1 << 7) |
| 36 | #define PHY0_COMMON_ON_N (1 << 4) | 36 | #define PHY0_COMMON_ON_N (1 << 4) |
| 37 | #define PHY0_ID_PULLUP (1 << 2) | 37 | #define PHY0_ID_PULLUP (1 << 2) |
| 38 | #define CLKSEL_MASK (0x3 << 0) | 38 | |
| 39 | #define CLKSEL_SHIFT (0) | 39 | #define EXYNOS4_CLKSEL_SHIFT (0) |
| 40 | #define CLKSEL_48M (0x0 << 0) | 40 | |
| 41 | #define CLKSEL_12M (0x2 << 0) | 41 | #define EXYNOS4210_CLKSEL_MASK (0x3 << 0) |
| 42 | #define CLKSEL_24M (0x3 << 0) | 42 | #define EXYNOS4210_CLKSEL_48M (0x0 << 0) |
| 43 | #define EXYNOS4210_CLKSEL_12M (0x2 << 0) | ||
| 44 | #define EXYNOS4210_CLKSEL_24M (0x3 << 0) | ||
| 45 | |||
| 46 | #define EXYNOS4X12_CLKSEL_MASK (0x7 << 0) | ||
| 47 | #define EXYNOS4X12_CLKSEL_9600K (0x0 << 0) | ||
| 48 | #define EXYNOS4X12_CLKSEL_10M (0x1 << 0) | ||
| 49 | #define EXYNOS4X12_CLKSEL_12M (0x2 << 0) | ||
| 50 | #define EXYNOS4X12_CLKSEL_19200K (0x3 << 0) | ||
| 51 | #define EXYNOS4X12_CLKSEL_20M (0x4 << 0) | ||
| 52 | #define EXYNOS4X12_CLKSEL_24M (0x5 << 0) | ||
| 43 | 53 | ||
| 44 | #define EXYNOS4_RSTCON EXYNOS4_HSOTG_PHYREG(0x08) | 54 | #define EXYNOS4_RSTCON EXYNOS4_HSOTG_PHYREG(0x08) |
| 45 | #define HOST_LINK_PORT_SWRST_MASK (0xf << 6) | 55 | #define HOST_LINK_PORT_SWRST_MASK (0xf << 6) |
diff --git a/arch/arm/mach-exynos/include/mach/spi-clocks.h b/arch/arm/mach-exynos/include/mach/spi-clocks.h deleted file mode 100644 index c71a5fba6a84..000000000000 --- a/arch/arm/mach-exynos/include/mach/spi-clocks.h +++ /dev/null | |||
| @@ -1,16 +0,0 @@ | |||
| 1 | /* linux/arch/arm/mach-exynos4/include/mach/spi-clocks.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2011 Samsung Electronics Co. Ltd. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License version 2 as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __ASM_ARCH_SPI_CLKS_H | ||
| 11 | #define __ASM_ARCH_SPI_CLKS_H __FILE__ | ||
| 12 | |||
| 13 | /* Must source from SCLK_SPI */ | ||
| 14 | #define EXYNOS_SPI_SRCCLK_SCLK 0 | ||
| 15 | |||
| 16 | #endif /* __ASM_ARCH_SPI_CLKS_H */ | ||
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c index 656f8fc9addd..f3b328d0aff6 100644 --- a/arch/arm/mach-exynos/mach-nuri.c +++ b/arch/arm/mach-exynos/mach-nuri.c | |||
| @@ -50,7 +50,6 @@ | |||
| 50 | #include <plat/gpio-cfg.h> | 50 | #include <plat/gpio-cfg.h> |
| 51 | #include <plat/iic.h> | 51 | #include <plat/iic.h> |
| 52 | #include <plat/mfc.h> | 52 | #include <plat/mfc.h> |
| 53 | #include <plat/pd.h> | ||
| 54 | #include <plat/fimc-core.h> | 53 | #include <plat/fimc-core.h> |
| 55 | #include <plat/camport.h> | 54 | #include <plat/camport.h> |
| 56 | #include <plat/mipi_csis.h> | 55 | #include <plat/mipi_csis.h> |
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c index f5572be9d7bf..873c708fd340 100644 --- a/arch/arm/mach-exynos/mach-origen.c +++ b/arch/arm/mach-exynos/mach-origen.c | |||
| @@ -38,7 +38,6 @@ | |||
| 38 | #include <plat/clock.h> | 38 | #include <plat/clock.h> |
| 39 | #include <plat/gpio-cfg.h> | 39 | #include <plat/gpio-cfg.h> |
| 40 | #include <plat/backlight.h> | 40 | #include <plat/backlight.h> |
| 41 | #include <plat/pd.h> | ||
| 42 | #include <plat/fb.h> | 41 | #include <plat/fb.h> |
| 43 | #include <plat/mfc.h> | 42 | #include <plat/mfc.h> |
| 44 | 43 | ||
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c index 262e9e446a96..5fb209c4a594 100644 --- a/arch/arm/mach-exynos/mach-smdkv310.c +++ b/arch/arm/mach-exynos/mach-smdkv310.c | |||
| @@ -34,7 +34,6 @@ | |||
| 34 | #include <plat/keypad.h> | 34 | #include <plat/keypad.h> |
| 35 | #include <plat/sdhci.h> | 35 | #include <plat/sdhci.h> |
| 36 | #include <plat/iic.h> | 36 | #include <plat/iic.h> |
| 37 | #include <plat/pd.h> | ||
| 38 | #include <plat/gpio-cfg.h> | 37 | #include <plat/gpio-cfg.h> |
| 39 | #include <plat/backlight.h> | 38 | #include <plat/backlight.h> |
| 40 | #include <plat/mfc.h> | 39 | #include <plat/mfc.h> |
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c index cd92fa86ba41..68719f57dcea 100644 --- a/arch/arm/mach-exynos/mach-universal_c210.c +++ b/arch/arm/mach-exynos/mach-universal_c210.c | |||
| @@ -39,7 +39,6 @@ | |||
| 39 | #include <plat/fb.h> | 39 | #include <plat/fb.h> |
| 40 | #include <plat/mfc.h> | 40 | #include <plat/mfc.h> |
| 41 | #include <plat/sdhci.h> | 41 | #include <plat/sdhci.h> |
| 42 | #include <plat/pd.h> | ||
| 43 | #include <plat/regs-fb-v4.h> | 42 | #include <plat/regs-fb-v4.h> |
| 44 | #include <plat/fimc-core.h> | 43 | #include <plat/fimc-core.h> |
| 45 | #include <plat/s5p-time.h> | 44 | #include <plat/s5p-time.h> |
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c index e9fafcf163de..373c3c00d24c 100644 --- a/arch/arm/mach-exynos/pm_domains.c +++ b/arch/arm/mach-exynos/pm_domains.c | |||
| @@ -119,7 +119,9 @@ static __init void exynos_pm_add_dev_to_genpd(struct platform_device *pdev, | |||
| 119 | struct exynos_pm_domain *pd) | 119 | struct exynos_pm_domain *pd) |
| 120 | { | 120 | { |
| 121 | if (pdev->dev.bus) { | 121 | if (pdev->dev.bus) { |
| 122 | if (pm_genpd_add_device(&pd->pd, &pdev->dev)) | 122 | if (!pm_genpd_add_device(&pd->pd, &pdev->dev)) |
| 123 | pm_genpd_dev_need_restore(&pdev->dev, true); | ||
| 124 | else | ||
| 123 | pr_info("%s: error in adding %s device to %s power" | 125 | pr_info("%s: error in adding %s device to %s power" |
| 124 | "domain\n", __func__, dev_name(&pdev->dev), | 126 | "domain\n", __func__, dev_name(&pdev->dev), |
| 125 | pd->name); | 127 | pd->name); |
| @@ -151,9 +153,12 @@ static __init int exynos4_pm_init_power_domain(void) | |||
| 151 | if (of_have_populated_dt()) | 153 | if (of_have_populated_dt()) |
| 152 | return exynos_pm_dt_parse_domains(); | 154 | return exynos_pm_dt_parse_domains(); |
| 153 | 155 | ||
| 154 | for (idx = 0; idx < ARRAY_SIZE(exynos4_pm_domains); idx++) | 156 | for (idx = 0; idx < ARRAY_SIZE(exynos4_pm_domains); idx++) { |
| 155 | pm_genpd_init(&exynos4_pm_domains[idx]->pd, NULL, | 157 | struct exynos_pm_domain *pd = exynos4_pm_domains[idx]; |
| 156 | exynos4_pm_domains[idx]->is_off); | 158 | int on = __raw_readl(pd->base + 0x4) & S5P_INT_LOCAL_PWR_EN; |
| 159 | |||
| 160 | pm_genpd_init(&pd->pd, NULL, !on); | ||
| 161 | } | ||
| 157 | 162 | ||
| 158 | #ifdef CONFIG_S5P_DEV_FIMD0 | 163 | #ifdef CONFIG_S5P_DEV_FIMD0 |
| 159 | exynos_pm_add_dev_to_genpd(&s5p_device_fimd0, &exynos4_pd_lcd0); | 164 | exynos_pm_add_dev_to_genpd(&s5p_device_fimd0, &exynos4_pd_lcd0); |
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c index 4aacb66f7161..3a48c852be6c 100644 --- a/arch/arm/mach-exynos/pmu.c +++ b/arch/arm/mach-exynos/pmu.c | |||
| @@ -315,7 +315,7 @@ static struct exynos_pmu_conf exynos5250_pmu_config[] = { | |||
| 315 | { PMU_TABLE_END,}, | 315 | { PMU_TABLE_END,}, |
| 316 | }; | 316 | }; |
| 317 | 317 | ||
| 318 | void __iomem *exynos5_list_both_cnt_feed[] = { | 318 | static void __iomem *exynos5_list_both_cnt_feed[] = { |
| 319 | EXYNOS5_ARM_CORE0_OPTION, | 319 | EXYNOS5_ARM_CORE0_OPTION, |
| 320 | EXYNOS5_ARM_CORE1_OPTION, | 320 | EXYNOS5_ARM_CORE1_OPTION, |
| 321 | EXYNOS5_ARM_COMMON_OPTION, | 321 | EXYNOS5_ARM_COMMON_OPTION, |
| @@ -329,7 +329,7 @@ void __iomem *exynos5_list_both_cnt_feed[] = { | |||
| 329 | EXYNOS5_TOP_PWR_SYSMEM_OPTION, | 329 | EXYNOS5_TOP_PWR_SYSMEM_OPTION, |
| 330 | }; | 330 | }; |
| 331 | 331 | ||
| 332 | void __iomem *exynos5_list_diable_wfi_wfe[] = { | 332 | static void __iomem *exynos5_list_diable_wfi_wfe[] = { |
| 333 | EXYNOS5_ARM_CORE1_OPTION, | 333 | EXYNOS5_ARM_CORE1_OPTION, |
| 334 | EXYNOS5_FSYS_ARM_OPTION, | 334 | EXYNOS5_FSYS_ARM_OPTION, |
| 335 | EXYNOS5_ISP_ARM_OPTION, | 335 | EXYNOS5_ISP_ARM_OPTION, |
| @@ -390,6 +390,8 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode) | |||
| 390 | 390 | ||
| 391 | static int __init exynos_pmu_init(void) | 391 | static int __init exynos_pmu_init(void) |
| 392 | { | 392 | { |
| 393 | unsigned int value; | ||
| 394 | |||
| 393 | exynos_pmu_config = exynos4210_pmu_config; | 395 | exynos_pmu_config = exynos4210_pmu_config; |
| 394 | 396 | ||
| 395 | if (soc_is_exynos4210()) { | 397 | if (soc_is_exynos4210()) { |
| @@ -399,6 +401,18 @@ static int __init exynos_pmu_init(void) | |||
| 399 | exynos_pmu_config = exynos4x12_pmu_config; | 401 | exynos_pmu_config = exynos4x12_pmu_config; |
| 400 | pr_info("EXYNOS4x12 PMU Initialize\n"); | 402 | pr_info("EXYNOS4x12 PMU Initialize\n"); |
| 401 | } else if (soc_is_exynos5250()) { | 403 | } else if (soc_is_exynos5250()) { |
| 404 | /* | ||
| 405 | * When SYS_WDTRESET is set, watchdog timer reset request | ||
| 406 | * is ignored by power management unit. | ||
| 407 | */ | ||
| 408 | value = __raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE); | ||
| 409 | value &= ~EXYNOS5_SYS_WDTRESET; | ||
| 410 | __raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE); | ||
| 411 | |||
| 412 | value = __raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST); | ||
| 413 | value &= ~EXYNOS5_SYS_WDTRESET; | ||
| 414 | __raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST); | ||
| 415 | |||
| 402 | exynos_pmu_config = exynos5250_pmu_config; | 416 | exynos_pmu_config = exynos5250_pmu_config; |
| 403 | pr_info("EXYNOS5250 PMU Initialize\n"); | 417 | pr_info("EXYNOS5250 PMU Initialize\n"); |
| 404 | } else { | 418 | } else { |
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c index 1af0a7f44e00..b81cc569a8dd 100644 --- a/arch/arm/mach-exynos/setup-usb-phy.c +++ b/arch/arm/mach-exynos/setup-usb-phy.c | |||
| @@ -31,27 +31,55 @@ static void exynos4210_usb_phy_clkset(struct platform_device *pdev) | |||
| 31 | struct clk *xusbxti_clk; | 31 | struct clk *xusbxti_clk; |
| 32 | u32 phyclk; | 32 | u32 phyclk; |
| 33 | 33 | ||
| 34 | /* set clock frequency for PLL */ | ||
| 35 | phyclk = readl(EXYNOS4_PHYCLK) & ~CLKSEL_MASK; | ||
| 36 | |||
| 37 | xusbxti_clk = clk_get(&pdev->dev, "xusbxti"); | 34 | xusbxti_clk = clk_get(&pdev->dev, "xusbxti"); |
| 38 | if (xusbxti_clk && !IS_ERR(xusbxti_clk)) { | 35 | if (xusbxti_clk && !IS_ERR(xusbxti_clk)) { |
| 39 | switch (clk_get_rate(xusbxti_clk)) { | 36 | if (soc_is_exynos4210()) { |
| 40 | case 12 * MHZ: | 37 | /* set clock frequency for PLL */ |
| 41 | phyclk |= CLKSEL_12M; | 38 | phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4210_CLKSEL_MASK; |
| 42 | break; | 39 | |
| 43 | case 24 * MHZ: | 40 | switch (clk_get_rate(xusbxti_clk)) { |
| 44 | phyclk |= CLKSEL_24M; | 41 | case 12 * MHZ: |
| 45 | break; | 42 | phyclk |= EXYNOS4210_CLKSEL_12M; |
| 46 | default: | 43 | break; |
| 47 | case 48 * MHZ: | 44 | case 48 * MHZ: |
| 48 | /* default reference clock */ | 45 | phyclk |= EXYNOS4210_CLKSEL_48M; |
| 49 | break; | 46 | break; |
| 47 | default: | ||
| 48 | case 24 * MHZ: | ||
| 49 | phyclk |= EXYNOS4210_CLKSEL_24M; | ||
| 50 | break; | ||
| 51 | } | ||
| 52 | writel(phyclk, EXYNOS4_PHYCLK); | ||
| 53 | } else if (soc_is_exynos4212() || soc_is_exynos4412()) { | ||
| 54 | /* set clock frequency for PLL */ | ||
| 55 | phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4X12_CLKSEL_MASK; | ||
| 56 | |||
| 57 | switch (clk_get_rate(xusbxti_clk)) { | ||
| 58 | case 9600 * KHZ: | ||
| 59 | phyclk |= EXYNOS4X12_CLKSEL_9600K; | ||
| 60 | break; | ||
| 61 | case 10 * MHZ: | ||
| 62 | phyclk |= EXYNOS4X12_CLKSEL_10M; | ||
| 63 | break; | ||
| 64 | case 12 * MHZ: | ||
| 65 | phyclk |= EXYNOS4X12_CLKSEL_12M; | ||
| 66 | break; | ||
| 67 | case 19200 * KHZ: | ||
| 68 | phyclk |= EXYNOS4X12_CLKSEL_19200K; | ||
| 69 | break; | ||
| 70 | case 20 * MHZ: | ||
| 71 | phyclk |= EXYNOS4X12_CLKSEL_20M; | ||
| 72 | break; | ||
| 73 | default: | ||
| 74 | case 24 * MHZ: | ||
| 75 | /* default reference clock */ | ||
| 76 | phyclk |= EXYNOS4X12_CLKSEL_24M; | ||
| 77 | break; | ||
| 78 | } | ||
| 79 | writel(phyclk, EXYNOS4_PHYCLK); | ||
| 50 | } | 80 | } |
| 51 | clk_put(xusbxti_clk); | 81 | clk_put(xusbxti_clk); |
| 52 | } | 82 | } |
| 53 | |||
| 54 | writel(phyclk, EXYNOS4_PHYCLK); | ||
| 55 | } | 83 | } |
| 56 | 84 | ||
| 57 | static int exynos4210_usb_phy0_init(struct platform_device *pdev) | 85 | static int exynos4210_usb_phy0_init(struct platform_device *pdev) |
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 5f87f2e2ddae..7616101a35f0 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig | |||
| @@ -74,7 +74,7 @@ config SOC_IMX31 | |||
| 74 | 74 | ||
| 75 | config SOC_IMX35 | 75 | config SOC_IMX35 |
| 76 | bool | 76 | bool |
| 77 | select CPU_V6 | 77 | select CPU_V6K |
| 78 | select ARCH_MXC_IOMUX_V3 | 78 | select ARCH_MXC_IOMUX_V3 |
| 79 | select COMMON_CLK | 79 | select COMMON_CLK |
| 80 | select HAVE_EPIT | 80 | select HAVE_EPIT |
| @@ -161,7 +161,6 @@ config MACH_MX25_3DS | |||
| 161 | select IMX_HAVE_PLATFORM_IMX2_WDT | 161 | select IMX_HAVE_PLATFORM_IMX2_WDT |
| 162 | select IMX_HAVE_PLATFORM_IMXDI_RTC | 162 | select IMX_HAVE_PLATFORM_IMXDI_RTC |
| 163 | select IMX_HAVE_PLATFORM_IMX_I2C | 163 | select IMX_HAVE_PLATFORM_IMX_I2C |
| 164 | select IMX_HAVE_PLATFORM_IMX_SSI | ||
| 165 | select IMX_HAVE_PLATFORM_IMX_FB | 164 | select IMX_HAVE_PLATFORM_IMX_FB |
| 166 | select IMX_HAVE_PLATFORM_IMX_KEYPAD | 165 | select IMX_HAVE_PLATFORM_IMX_KEYPAD |
| 167 | select IMX_HAVE_PLATFORM_IMX_UART | 166 | select IMX_HAVE_PLATFORM_IMX_UART |
| @@ -600,6 +599,7 @@ config MACH_MX35_3DS | |||
| 600 | select IMX_HAVE_PLATFORM_IPU_CORE | 599 | select IMX_HAVE_PLATFORM_IPU_CORE |
| 601 | select IMX_HAVE_PLATFORM_MXC_EHCI | 600 | select IMX_HAVE_PLATFORM_MXC_EHCI |
| 602 | select IMX_HAVE_PLATFORM_MXC_NAND | 601 | select IMX_HAVE_PLATFORM_MXC_NAND |
| 602 | select IMX_HAVE_PLATFORM_MXC_RTC | ||
| 603 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | 603 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX |
| 604 | help | 604 | help |
| 605 | Include support for MX35PDK platform. This includes specific | 605 | Include support for MX35PDK platform. This includes specific |
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index d5e88c0d5e6c..ea89520b6e22 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c | |||
| @@ -392,12 +392,9 @@ int __init mx6q_clocks_init(void) | |||
| 392 | pr_err("i.MX6q clk %d: register failed with %ld\n", | 392 | pr_err("i.MX6q clk %d: register failed with %ld\n", |
| 393 | i, PTR_ERR(clk[i])); | 393 | i, PTR_ERR(clk[i])); |
| 394 | 394 | ||
| 395 | clk_register_clkdev(clk[mmdc_ch0_axi], NULL, "mmdc_ch0_axi"); | ||
| 396 | clk_register_clkdev(clk[mmdc_ch1_axi], NULL, "mmdc_ch1_axi"); | ||
| 397 | clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0"); | 395 | clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0"); |
| 398 | clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); | 396 | clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); |
| 399 | clk_register_clkdev(clk[twd], NULL, "smp_twd"); | 397 | clk_register_clkdev(clk[twd], NULL, "smp_twd"); |
| 400 | clk_register_clkdev(clk[usboh3], NULL, "usboh3"); | ||
| 401 | clk_register_clkdev(clk[apbh_dma], NULL, "110000.dma-apbh"); | 398 | clk_register_clkdev(clk[apbh_dma], NULL, "110000.dma-apbh"); |
| 402 | clk_register_clkdev(clk[per1_bch], "per1_bch", "112000.gpmi-nand"); | 399 | clk_register_clkdev(clk[per1_bch], "per1_bch", "112000.gpmi-nand"); |
| 403 | clk_register_clkdev(clk[gpmi_bch_apb], "gpmi_bch_apb", "112000.gpmi-nand"); | 400 | clk_register_clkdev(clk[gpmi_bch_apb], "gpmi_bch_apb", "112000.gpmi-nand"); |
diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h index 2628e0c474dc..93ece55f75df 100644 --- a/arch/arm/mach-imx/devices-imx21.h +++ b/arch/arm/mach-imx/devices-imx21.h | |||
| @@ -14,7 +14,7 @@ extern const struct imx_imx21_hcd_data imx21_imx21_hcd_data; | |||
| 14 | imx_add_imx21_hcd(&imx21_imx21_hcd_data, pdata) | 14 | imx_add_imx21_hcd(&imx21_imx21_hcd_data, pdata) |
| 15 | 15 | ||
| 16 | extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data; | 16 | extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data; |
| 17 | #define imx21_add_imx2_wdt(pdata) \ | 17 | #define imx21_add_imx2_wdt() \ |
| 18 | imx_add_imx2_wdt(&imx21_imx2_wdt_data) | 18 | imx_add_imx2_wdt(&imx21_imx2_wdt_data) |
| 19 | 19 | ||
| 20 | extern const struct imx_imx_fb_data imx21_imx_fb_data; | 20 | extern const struct imx_imx_fb_data imx21_imx_fb_data; |
| @@ -50,7 +50,7 @@ extern const struct imx_mxc_nand_data imx21_mxc_nand_data; | |||
| 50 | imx_add_mxc_nand(&imx21_mxc_nand_data, pdata) | 50 | imx_add_mxc_nand(&imx21_mxc_nand_data, pdata) |
| 51 | 51 | ||
| 52 | extern const struct imx_mxc_w1_data imx21_mxc_w1_data; | 52 | extern const struct imx_mxc_w1_data imx21_mxc_w1_data; |
| 53 | #define imx21_add_mxc_w1(pdata) \ | 53 | #define imx21_add_mxc_w1() \ |
| 54 | imx_add_mxc_w1(&imx21_mxc_w1_data) | 54 | imx_add_mxc_w1(&imx21_mxc_w1_data) |
| 55 | 55 | ||
| 56 | extern const struct imx_spi_imx_data imx21_cspi_data[]; | 56 | extern const struct imx_spi_imx_data imx21_cspi_data[]; |
diff --git a/arch/arm/mach-imx/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h index efa0761c508d..f8e03dd1f116 100644 --- a/arch/arm/mach-imx/devices-imx25.h +++ b/arch/arm/mach-imx/devices-imx25.h | |||
| @@ -24,11 +24,11 @@ extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data; | |||
| 24 | imx_add_fsl_usb2_udc(&imx25_fsl_usb2_udc_data, pdata) | 24 | imx_add_fsl_usb2_udc(&imx25_fsl_usb2_udc_data, pdata) |
| 25 | 25 | ||
| 26 | extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data; | 26 | extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data; |
| 27 | #define imx25_add_imxdi_rtc(pdata) \ | 27 | #define imx25_add_imxdi_rtc() \ |
| 28 | imx_add_imxdi_rtc(&imx25_imxdi_rtc_data) | 28 | imx_add_imxdi_rtc(&imx25_imxdi_rtc_data) |
| 29 | 29 | ||
| 30 | extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data; | 30 | extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data; |
| 31 | #define imx25_add_imx2_wdt(pdata) \ | 31 | #define imx25_add_imx2_wdt() \ |
| 32 | imx_add_imx2_wdt(&imx25_imx2_wdt_data) | 32 | imx_add_imx2_wdt(&imx25_imx2_wdt_data) |
| 33 | 33 | ||
| 34 | extern const struct imx_imx_fb_data imx25_imx_fb_data; | 34 | extern const struct imx_imx_fb_data imx25_imx_fb_data; |
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h index 28537a5d9048..436c5720fe6a 100644 --- a/arch/arm/mach-imx/devices-imx27.h +++ b/arch/arm/mach-imx/devices-imx27.h | |||
| @@ -18,7 +18,7 @@ extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data; | |||
| 18 | imx_add_fsl_usb2_udc(&imx27_fsl_usb2_udc_data, pdata) | 18 | imx_add_fsl_usb2_udc(&imx27_fsl_usb2_udc_data, pdata) |
| 19 | 19 | ||
| 20 | extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data; | 20 | extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data; |
| 21 | #define imx27_add_imx2_wdt(pdata) \ | 21 | #define imx27_add_imx2_wdt() \ |
| 22 | imx_add_imx2_wdt(&imx27_imx2_wdt_data) | 22 | imx_add_imx2_wdt(&imx27_imx2_wdt_data) |
| 23 | 23 | ||
| 24 | extern const struct imx_imx_fb_data imx27_imx_fb_data; | 24 | extern const struct imx_imx_fb_data imx27_imx_fb_data; |
| @@ -50,7 +50,7 @@ extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[]; | |||
| 50 | extern const struct imx_mx2_camera_data imx27_mx2_camera_data; | 50 | extern const struct imx_mx2_camera_data imx27_mx2_camera_data; |
| 51 | #define imx27_add_mx2_camera(pdata) \ | 51 | #define imx27_add_mx2_camera(pdata) \ |
| 52 | imx_add_mx2_camera(&imx27_mx2_camera_data, pdata) | 52 | imx_add_mx2_camera(&imx27_mx2_camera_data, pdata) |
| 53 | #define imx27_add_mx2_emmaprp(pdata) \ | 53 | #define imx27_add_mx2_emmaprp() \ |
| 54 | imx_add_mx2_emmaprp(&imx27_mx2_camera_data) | 54 | imx_add_mx2_emmaprp(&imx27_mx2_camera_data) |
| 55 | 55 | ||
| 56 | extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data; | 56 | extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data; |
| @@ -69,7 +69,7 @@ extern const struct imx_mxc_nand_data imx27_mxc_nand_data; | |||
| 69 | imx_add_mxc_nand(&imx27_mxc_nand_data, pdata) | 69 | imx_add_mxc_nand(&imx27_mxc_nand_data, pdata) |
| 70 | 70 | ||
| 71 | extern const struct imx_mxc_w1_data imx27_mxc_w1_data; | 71 | extern const struct imx_mxc_w1_data imx27_mxc_w1_data; |
| 72 | #define imx27_add_mxc_w1(pdata) \ | 72 | #define imx27_add_mxc_w1() \ |
| 73 | imx_add_mxc_w1(&imx27_mxc_w1_data) | 73 | imx_add_mxc_w1(&imx27_mxc_w1_data) |
| 74 | 74 | ||
| 75 | extern const struct imx_spi_imx_data imx27_cspi_data[]; | 75 | extern const struct imx_spi_imx_data imx27_cspi_data[]; |
diff --git a/arch/arm/mach-imx/devices-imx31.h b/arch/arm/mach-imx/devices-imx31.h index 488e241a6db6..13f533d0aa5c 100644 --- a/arch/arm/mach-imx/devices-imx31.h +++ b/arch/arm/mach-imx/devices-imx31.h | |||
| @@ -14,7 +14,7 @@ extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data; | |||
| 14 | imx_add_fsl_usb2_udc(&imx31_fsl_usb2_udc_data, pdata) | 14 | imx_add_fsl_usb2_udc(&imx31_fsl_usb2_udc_data, pdata) |
| 15 | 15 | ||
| 16 | extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data; | 16 | extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data; |
| 17 | #define imx31_add_imx2_wdt(pdata) \ | 17 | #define imx31_add_imx2_wdt() \ |
| 18 | imx_add_imx2_wdt(&imx31_imx2_wdt_data) | 18 | imx_add_imx2_wdt(&imx31_imx2_wdt_data) |
| 19 | 19 | ||
| 20 | extern const struct imx_imx_i2c_data imx31_imx_i2c_data[]; | 20 | extern const struct imx_imx_i2c_data imx31_imx_i2c_data[]; |
| @@ -65,11 +65,11 @@ extern const struct imx_mxc_nand_data imx31_mxc_nand_data; | |||
| 65 | imx_add_mxc_nand(&imx31_mxc_nand_data, pdata) | 65 | imx_add_mxc_nand(&imx31_mxc_nand_data, pdata) |
| 66 | 66 | ||
| 67 | extern const struct imx_mxc_rtc_data imx31_mxc_rtc_data; | 67 | extern const struct imx_mxc_rtc_data imx31_mxc_rtc_data; |
| 68 | #define imx31_add_mxc_rtc(pdata) \ | 68 | #define imx31_add_mxc_rtc() \ |
| 69 | imx_add_mxc_rtc(&imx31_mxc_rtc_data) | 69 | imx_add_mxc_rtc(&imx31_mxc_rtc_data) |
| 70 | 70 | ||
| 71 | extern const struct imx_mxc_w1_data imx31_mxc_w1_data; | 71 | extern const struct imx_mxc_w1_data imx31_mxc_w1_data; |
| 72 | #define imx31_add_mxc_w1(pdata) \ | 72 | #define imx31_add_mxc_w1() \ |
| 73 | imx_add_mxc_w1(&imx31_mxc_w1_data) | 73 | imx_add_mxc_w1(&imx31_mxc_w1_data) |
| 74 | 74 | ||
| 75 | extern const struct imx_spi_imx_data imx31_cspi_data[]; | 75 | extern const struct imx_spi_imx_data imx31_cspi_data[]; |
diff --git a/arch/arm/mach-imx/devices-imx35.h b/arch/arm/mach-imx/devices-imx35.h index 7b99ef0bb501..4815be1ee675 100644 --- a/arch/arm/mach-imx/devices-imx35.h +++ b/arch/arm/mach-imx/devices-imx35.h | |||
| @@ -24,7 +24,7 @@ extern const struct imx_flexcan_data imx35_flexcan_data[]; | |||
| 24 | #define imx35_add_flexcan1(pdata) imx35_add_flexcan(1, pdata) | 24 | #define imx35_add_flexcan1(pdata) imx35_add_flexcan(1, pdata) |
| 25 | 25 | ||
| 26 | extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data; | 26 | extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data; |
| 27 | #define imx35_add_imx2_wdt(pdata) \ | 27 | #define imx35_add_imx2_wdt() \ |
| 28 | imx_add_imx2_wdt(&imx35_imx2_wdt_data) | 28 | imx_add_imx2_wdt(&imx35_imx2_wdt_data) |
| 29 | 29 | ||
| 30 | extern const struct imx_imx_i2c_data imx35_imx_i2c_data[]; | 30 | extern const struct imx_imx_i2c_data imx35_imx_i2c_data[]; |
| @@ -68,8 +68,12 @@ extern const struct imx_mxc_nand_data imx35_mxc_nand_data; | |||
| 68 | #define imx35_add_mxc_nand(pdata) \ | 68 | #define imx35_add_mxc_nand(pdata) \ |
| 69 | imx_add_mxc_nand(&imx35_mxc_nand_data, pdata) | 69 | imx_add_mxc_nand(&imx35_mxc_nand_data, pdata) |
| 70 | 70 | ||
| 71 | extern const struct imx_mxc_rtc_data imx35_mxc_rtc_data; | ||
| 72 | #define imx35_add_mxc_rtc() \ | ||
| 73 | imx_add_mxc_rtc(&imx35_mxc_rtc_data) | ||
| 74 | |||
| 71 | extern const struct imx_mxc_w1_data imx35_mxc_w1_data; | 75 | extern const struct imx_mxc_w1_data imx35_mxc_w1_data; |
| 72 | #define imx35_add_mxc_w1(pdata) \ | 76 | #define imx35_add_mxc_w1() \ |
| 73 | imx_add_mxc_w1(&imx35_mxc_w1_data) | 77 | imx_add_mxc_w1(&imx35_mxc_w1_data) |
| 74 | 78 | ||
| 75 | extern const struct imx_sdhci_esdhc_imx_data imx35_sdhci_esdhc_imx_data[]; | 79 | extern const struct imx_sdhci_esdhc_imx_data imx35_sdhci_esdhc_imx_data[]; |
diff --git a/arch/arm/mach-imx/devices-imx51.h b/arch/arm/mach-imx/devices-imx51.h index af488bc0e225..9f1718725195 100644 --- a/arch/arm/mach-imx/devices-imx51.h +++ b/arch/arm/mach-imx/devices-imx51.h | |||
| @@ -55,7 +55,7 @@ extern const struct imx_spi_imx_data imx51_ecspi_data[]; | |||
| 55 | imx_add_spi_imx(&imx51_ecspi_data[id], pdata) | 55 | imx_add_spi_imx(&imx51_ecspi_data[id], pdata) |
| 56 | 56 | ||
| 57 | extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[]; | 57 | extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[]; |
| 58 | #define imx51_add_imx2_wdt(id, pdata) \ | 58 | #define imx51_add_imx2_wdt(id) \ |
| 59 | imx_add_imx2_wdt(&imx51_imx2_wdt_data[id]) | 59 | imx_add_imx2_wdt(&imx51_imx2_wdt_data[id]) |
| 60 | 60 | ||
| 61 | extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[]; | 61 | extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[]; |
diff --git a/arch/arm/mach-imx/devices-imx53.h b/arch/arm/mach-imx/devices-imx53.h index 6e1e5d1f8c3a..77e0db96c448 100644 --- a/arch/arm/mach-imx/devices-imx53.h +++ b/arch/arm/mach-imx/devices-imx53.h | |||
| @@ -30,7 +30,7 @@ extern const struct imx_spi_imx_data imx53_ecspi_data[]; | |||
| 30 | imx_add_spi_imx(&imx53_ecspi_data[id], pdata) | 30 | imx_add_spi_imx(&imx53_ecspi_data[id], pdata) |
| 31 | 31 | ||
| 32 | extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[]; | 32 | extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[]; |
| 33 | #define imx53_add_imx2_wdt(id, pdata) \ | 33 | #define imx53_add_imx2_wdt(id) \ |
| 34 | imx_add_imx2_wdt(&imx53_imx2_wdt_data[id]) | 34 | imx_add_imx2_wdt(&imx53_imx2_wdt_data[id]) |
| 35 | 35 | ||
| 36 | extern const struct imx_imx_ssi_data imx53_imx_ssi_data[]; | 36 | extern const struct imx_imx_ssi_data imx53_imx_ssi_data[]; |
diff --git a/arch/arm/mach-imx/ehci-imx25.c b/arch/arm/mach-imx/ehci-imx25.c index 865daf0b09e9..05bb41d99728 100644 --- a/arch/arm/mach-imx/ehci-imx25.c +++ b/arch/arm/mach-imx/ehci-imx25.c | |||
| @@ -24,14 +24,18 @@ | |||
| 24 | #define MX25_OTG_SIC_SHIFT 29 | 24 | #define MX25_OTG_SIC_SHIFT 29 |
| 25 | #define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT) | 25 | #define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT) |
| 26 | #define MX25_OTG_PM_BIT (1 << 24) | 26 | #define MX25_OTG_PM_BIT (1 << 24) |
| 27 | #define MX25_OTG_PP_BIT (1 << 11) | ||
| 28 | #define MX25_OTG_OCPOL_BIT (1 << 3) | ||
| 27 | 29 | ||
| 28 | #define MX25_H1_SIC_SHIFT 21 | 30 | #define MX25_H1_SIC_SHIFT 21 |
| 29 | #define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT) | 31 | #define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT) |
| 32 | #define MX25_H1_PP_BIT (1 << 18) | ||
| 30 | #define MX25_H1_PM_BIT (1 << 8) | 33 | #define MX25_H1_PM_BIT (1 << 8) |
| 31 | #define MX25_H1_IPPUE_UP_BIT (1 << 7) | 34 | #define MX25_H1_IPPUE_UP_BIT (1 << 7) |
| 32 | #define MX25_H1_IPPUE_DOWN_BIT (1 << 6) | 35 | #define MX25_H1_IPPUE_DOWN_BIT (1 << 6) |
| 33 | #define MX25_H1_TLL_BIT (1 << 5) | 36 | #define MX25_H1_TLL_BIT (1 << 5) |
| 34 | #define MX25_H1_USBTE_BIT (1 << 4) | 37 | #define MX25_H1_USBTE_BIT (1 << 4) |
| 38 | #define MX25_H1_OCPOL_BIT (1 << 2) | ||
| 35 | 39 | ||
| 36 | int mx25_initialize_usb_hw(int port, unsigned int flags) | 40 | int mx25_initialize_usb_hw(int port, unsigned int flags) |
| 37 | { | 41 | { |
| @@ -41,21 +45,35 @@ int mx25_initialize_usb_hw(int port, unsigned int flags) | |||
| 41 | 45 | ||
| 42 | switch (port) { | 46 | switch (port) { |
| 43 | case 0: /* OTG port */ | 47 | case 0: /* OTG port */ |
| 44 | v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT); | 48 | v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT | |
| 49 | MX25_OTG_OCPOL_BIT); | ||
| 45 | v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT; | 50 | v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT; |
| 46 | 51 | ||
| 47 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) | 52 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) |
| 48 | v |= MX25_OTG_PM_BIT; | 53 | v |= MX25_OTG_PM_BIT; |
| 49 | 54 | ||
| 55 | if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) | ||
| 56 | v |= MX25_OTG_PP_BIT; | ||
| 57 | |||
| 58 | if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) | ||
| 59 | v |= MX25_OTG_OCPOL_BIT; | ||
| 60 | |||
| 50 | break; | 61 | break; |
| 51 | case 1: /* H1 port */ | 62 | case 1: /* H1 port */ |
| 52 | v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_TLL_BIT | | 63 | v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT | |
| 53 | MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT); | 64 | MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | MX25_H1_USBTE_BIT | |
| 65 | MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT); | ||
| 54 | v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT; | 66 | v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT; |
| 55 | 67 | ||
| 56 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) | 68 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) |
| 57 | v |= MX25_H1_PM_BIT; | 69 | v |= MX25_H1_PM_BIT; |
| 58 | 70 | ||
| 71 | if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) | ||
| 72 | v |= MX25_H1_PP_BIT; | ||
| 73 | |||
| 74 | if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) | ||
| 75 | v |= MX25_H1_OCPOL_BIT; | ||
| 76 | |||
| 59 | if (!(flags & MXC_EHCI_TTL_ENABLED)) | 77 | if (!(flags & MXC_EHCI_TTL_ENABLED)) |
| 60 | v |= MX25_H1_TLL_BIT; | 78 | v |= MX25_H1_TLL_BIT; |
| 61 | 79 | ||
diff --git a/arch/arm/mach-imx/ehci-imx35.c b/arch/arm/mach-imx/ehci-imx35.c index 001ec3971f5d..73574c30cf50 100644 --- a/arch/arm/mach-imx/ehci-imx35.c +++ b/arch/arm/mach-imx/ehci-imx35.c | |||
| @@ -24,14 +24,18 @@ | |||
| 24 | #define MX35_OTG_SIC_SHIFT 29 | 24 | #define MX35_OTG_SIC_SHIFT 29 |
| 25 | #define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT) | 25 | #define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT) |
| 26 | #define MX35_OTG_PM_BIT (1 << 24) | 26 | #define MX35_OTG_PM_BIT (1 << 24) |
| 27 | #define MX35_OTG_PP_BIT (1 << 11) | ||
| 28 | #define MX35_OTG_OCPOL_BIT (1 << 3) | ||
| 27 | 29 | ||
| 28 | #define MX35_H1_SIC_SHIFT 21 | 30 | #define MX35_H1_SIC_SHIFT 21 |
| 29 | #define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT) | 31 | #define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT) |
| 32 | #define MX35_H1_PP_BIT (1 << 18) | ||
| 30 | #define MX35_H1_PM_BIT (1 << 8) | 33 | #define MX35_H1_PM_BIT (1 << 8) |
| 31 | #define MX35_H1_IPPUE_UP_BIT (1 << 7) | 34 | #define MX35_H1_IPPUE_UP_BIT (1 << 7) |
| 32 | #define MX35_H1_IPPUE_DOWN_BIT (1 << 6) | 35 | #define MX35_H1_IPPUE_DOWN_BIT (1 << 6) |
| 33 | #define MX35_H1_TLL_BIT (1 << 5) | 36 | #define MX35_H1_TLL_BIT (1 << 5) |
| 34 | #define MX35_H1_USBTE_BIT (1 << 4) | 37 | #define MX35_H1_USBTE_BIT (1 << 4) |
| 38 | #define MX35_H1_OCPOL_BIT (1 << 2) | ||
| 35 | 39 | ||
| 36 | int mx35_initialize_usb_hw(int port, unsigned int flags) | 40 | int mx35_initialize_usb_hw(int port, unsigned int flags) |
| 37 | { | 41 | { |
| @@ -41,21 +45,35 @@ int mx35_initialize_usb_hw(int port, unsigned int flags) | |||
| 41 | 45 | ||
| 42 | switch (port) { | 46 | switch (port) { |
| 43 | case 0: /* OTG port */ | 47 | case 0: /* OTG port */ |
| 44 | v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT); | 48 | v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT | |
| 49 | MX35_OTG_OCPOL_BIT); | ||
| 45 | v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT; | 50 | v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT; |
| 46 | 51 | ||
| 47 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) | 52 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) |
| 48 | v |= MX35_OTG_PM_BIT; | 53 | v |= MX35_OTG_PM_BIT; |
| 49 | 54 | ||
| 55 | if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) | ||
| 56 | v |= MX35_OTG_PP_BIT; | ||
| 57 | |||
| 58 | if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) | ||
| 59 | v |= MX35_OTG_OCPOL_BIT; | ||
| 60 | |||
| 50 | break; | 61 | break; |
| 51 | case 1: /* H1 port */ | 62 | case 1: /* H1 port */ |
| 52 | v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT | | 63 | v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT | |
| 53 | MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT); | 64 | MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT | MX35_H1_USBTE_BIT | |
| 65 | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT); | ||
| 54 | v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT; | 66 | v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT; |
| 55 | 67 | ||
| 56 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) | 68 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) |
| 57 | v |= MX35_H1_PM_BIT; | 69 | v |= MX35_H1_PM_BIT; |
| 58 | 70 | ||
| 71 | if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) | ||
| 72 | v |= MX35_H1_PP_BIT; | ||
| 73 | |||
| 74 | if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) | ||
| 75 | v |= MX35_H1_OCPOL_BIT; | ||
| 76 | |||
| 59 | if (!(flags & MXC_EHCI_TTL_ENABLED)) | 77 | if (!(flags & MXC_EHCI_TTL_ENABLED)) |
| 60 | v |= MX35_H1_TLL_BIT; | 78 | v |= MX35_H1_TLL_BIT; |
| 61 | 79 | ||
diff --git a/arch/arm/mach-imx/ehci-imx5.c b/arch/arm/mach-imx/ehci-imx5.c index c17fa131728b..a6a4afb0ad62 100644 --- a/arch/arm/mach-imx/ehci-imx5.c +++ b/arch/arm/mach-imx/ehci-imx5.c | |||
| @@ -28,11 +28,14 @@ | |||
| 28 | #define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */ | 28 | #define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */ |
| 29 | #define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */ | 29 | #define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */ |
| 30 | #define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */ | 30 | #define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */ |
| 31 | #define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */ | 31 | #define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */ |
| 32 | 32 | ||
| 33 | /* USB_PHY_CTRL_FUNC */ | 33 | /* USB_PHY_CTRL_FUNC */ |
| 34 | #define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9) /* OTG Polarity of Overcurrent */ | ||
| 34 | #define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */ | 35 | #define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */ |
| 36 | #define MXC_H1_OC_POL_BIT (1 << 6) /* UH1 Polarity of Overcurrent */ | ||
| 35 | #define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */ | 37 | #define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */ |
| 38 | #define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3) /* OTG Power Pin Polarity */ | ||
| 36 | 39 | ||
| 37 | /* USBH2CTRL */ | 40 | /* USBH2CTRL */ |
| 38 | #define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) | 41 | #define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) |
| @@ -80,13 +83,21 @@ int mx51_initialize_usb_hw(int port, unsigned int flags) | |||
| 80 | if (flags & MXC_EHCI_INTERNAL_PHY) { | 83 | if (flags & MXC_EHCI_INTERNAL_PHY) { |
| 81 | v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); | 84 | v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); |
| 82 | 85 | ||
| 86 | if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) | ||
| 87 | v |= MXC_OTG_PHYCTRL_OC_POL_BIT; | ||
| 88 | else | ||
| 89 | v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT; | ||
| 83 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) { | 90 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) { |
| 84 | /* OC/USBPWR is not used */ | ||
| 85 | v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; | ||
| 86 | } else { | ||
| 87 | /* OC/USBPWR is used */ | 91 | /* OC/USBPWR is used */ |
| 88 | v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT; | 92 | v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT; |
| 93 | } else { | ||
| 94 | /* OC/USBPWR is not used */ | ||
| 95 | v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; | ||
| 89 | } | 96 | } |
| 97 | if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) | ||
| 98 | v |= MXC_OTG_PHYCTRL_PWR_POL_BIT; | ||
| 99 | else | ||
| 100 | v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT; | ||
| 90 | __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); | 101 | __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); |
| 91 | 102 | ||
| 92 | v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); | 103 | v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); |
| @@ -95,9 +106,9 @@ int mx51_initialize_usb_hw(int port, unsigned int flags) | |||
| 95 | else | 106 | else |
| 96 | v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */ | 107 | v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */ |
| 97 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) | 108 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) |
| 98 | v |= MXC_OTG_UCTRL_OPM_BIT; | ||
| 99 | else | ||
| 100 | v &= ~MXC_OTG_UCTRL_OPM_BIT; | 109 | v &= ~MXC_OTG_UCTRL_OPM_BIT; |
| 110 | else | ||
| 111 | v |= MXC_OTG_UCTRL_OPM_BIT; | ||
| 101 | __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); | 112 | __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); |
| 102 | } | 113 | } |
| 103 | break; | 114 | break; |
| @@ -113,12 +124,16 @@ int mx51_initialize_usb_hw(int port, unsigned int flags) | |||
| 113 | } | 124 | } |
| 114 | 125 | ||
| 115 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) | 126 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) |
| 116 | v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ | 127 | v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused*/ |
| 117 | else | 128 | else |
| 118 | v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ | 129 | v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ |
| 119 | __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); | 130 | __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); |
| 120 | 131 | ||
| 121 | v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); | 132 | v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); |
| 133 | if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) | ||
| 134 | v |= MXC_H1_OC_POL_BIT; | ||
| 135 | else | ||
| 136 | v &= ~MXC_H1_OC_POL_BIT; | ||
| 122 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) | 137 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) |
| 123 | v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */ | 138 | v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */ |
| 124 | else | 139 | else |
| @@ -142,7 +157,7 @@ int mx51_initialize_usb_hw(int port, unsigned int flags) | |||
| 142 | } | 157 | } |
| 143 | 158 | ||
| 144 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) | 159 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) |
| 145 | v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/ | 160 | v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused*/ |
| 146 | else | 161 | else |
| 147 | v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/ | 162 | v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/ |
| 148 | __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); | 163 | __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); |
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c index eee0cc8d92a4..52efe4d5149b 100644 --- a/arch/arm/mach-imx/imx27-dt.c +++ b/arch/arm/mach-imx/imx27-dt.c | |||
| @@ -75,7 +75,7 @@ static struct sys_timer imx27_timer = { | |||
| 75 | .init = imx27_timer_init, | 75 | .init = imx27_timer_init, |
| 76 | }; | 76 | }; |
| 77 | 77 | ||
| 78 | static const char *imx27_dt_board_compat[] __initdata = { | 78 | static const char * const imx27_dt_board_compat[] __initconst = { |
| 79 | "fsl,imx27", | 79 | "fsl,imx27", |
| 80 | NULL | 80 | NULL |
| 81 | }; | 81 | }; |
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c index d085aea08709..9a3b06e688c5 100644 --- a/arch/arm/mach-imx/mach-cpuimx27.c +++ b/arch/arm/mach-imx/mach-cpuimx27.c | |||
| @@ -233,18 +233,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { | |||
| 233 | .phy_mode = FSL_USB2_PHY_ULPI, | 233 | .phy_mode = FSL_USB2_PHY_ULPI, |
| 234 | }; | 234 | }; |
| 235 | 235 | ||
| 236 | static int otg_mode_host; | 236 | static bool otg_mode_host __initdata; |
| 237 | 237 | ||
| 238 | static int __init eukrea_cpuimx27_otg_mode(char *options) | 238 | static int __init eukrea_cpuimx27_otg_mode(char *options) |
| 239 | { | 239 | { |
| 240 | if (!strcmp(options, "host")) | 240 | if (!strcmp(options, "host")) |
| 241 | otg_mode_host = 1; | 241 | otg_mode_host = true; |
| 242 | else if (!strcmp(options, "device")) | 242 | else if (!strcmp(options, "device")) |
| 243 | otg_mode_host = 0; | 243 | otg_mode_host = false; |
| 244 | else | 244 | else |
| 245 | pr_info("otg_mode neither \"host\" nor \"device\". " | 245 | pr_info("otg_mode neither \"host\" nor \"device\". " |
| 246 | "Defaulting to device\n"); | 246 | "Defaulting to device\n"); |
| 247 | return 0; | 247 | return 1; |
| 248 | } | 248 | } |
| 249 | __setup("otg_mode=", eukrea_cpuimx27_otg_mode); | 249 | __setup("otg_mode=", eukrea_cpuimx27_otg_mode); |
| 250 | 250 | ||
| @@ -266,8 +266,8 @@ static void __init eukrea_cpuimx27_init(void) | |||
| 266 | 266 | ||
| 267 | imx27_add_fec(NULL); | 267 | imx27_add_fec(NULL); |
| 268 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); | 268 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); |
| 269 | imx27_add_imx2_wdt(NULL); | 269 | imx27_add_imx2_wdt(); |
| 270 | imx27_add_mxc_w1(NULL); | 270 | imx27_add_mxc_w1(); |
| 271 | 271 | ||
| 272 | #if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2) | 272 | #if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2) |
| 273 | /* SDHC2 can be used for Wifi */ | 273 | /* SDHC2 can be used for Wifi */ |
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c index 6450303f1a7a..1634e54ffed5 100644 --- a/arch/arm/mach-imx/mach-cpuimx35.c +++ b/arch/arm/mach-imx/mach-cpuimx35.c | |||
| @@ -141,18 +141,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { | |||
| 141 | .workaround = FLS_USB2_WORKAROUND_ENGCM09152, | 141 | .workaround = FLS_USB2_WORKAROUND_ENGCM09152, |
| 142 | }; | 142 | }; |
| 143 | 143 | ||
| 144 | static int otg_mode_host; | 144 | static bool otg_mode_host __initdata; |
| 145 | 145 | ||
| 146 | static int __init eukrea_cpuimx35_otg_mode(char *options) | 146 | static int __init eukrea_cpuimx35_otg_mode(char *options) |
| 147 | { | 147 | { |
| 148 | if (!strcmp(options, "host")) | 148 | if (!strcmp(options, "host")) |
| 149 | otg_mode_host = 1; | 149 | otg_mode_host = true; |
| 150 | else if (!strcmp(options, "device")) | 150 | else if (!strcmp(options, "device")) |
| 151 | otg_mode_host = 0; | 151 | otg_mode_host = false; |
| 152 | else | 152 | else |
| 153 | pr_info("otg_mode neither \"host\" nor \"device\". " | 153 | pr_info("otg_mode neither \"host\" nor \"device\". " |
| 154 | "Defaulting to device\n"); | 154 | "Defaulting to device\n"); |
| 155 | return 0; | 155 | return 1; |
| 156 | } | 156 | } |
| 157 | __setup("otg_mode=", eukrea_cpuimx35_otg_mode); | 157 | __setup("otg_mode=", eukrea_cpuimx35_otg_mode); |
| 158 | 158 | ||
| @@ -167,7 +167,7 @@ static void __init eukrea_cpuimx35_init(void) | |||
| 167 | ARRAY_SIZE(eukrea_cpuimx35_pads)); | 167 | ARRAY_SIZE(eukrea_cpuimx35_pads)); |
| 168 | 168 | ||
| 169 | imx35_add_fec(NULL); | 169 | imx35_add_fec(NULL); |
| 170 | imx35_add_imx2_wdt(NULL); | 170 | imx35_add_imx2_wdt(); |
| 171 | 171 | ||
| 172 | imx35_add_imx_uart0(&uart_pdata); | 172 | imx35_add_imx_uart0(&uart_pdata); |
| 173 | imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info); | 173 | imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info); |
diff --git a/arch/arm/mach-imx/mach-cpuimx51sd.c b/arch/arm/mach-imx/mach-cpuimx51sd.c index 1e09de50cbcd..e78b40b41462 100644 --- a/arch/arm/mach-imx/mach-cpuimx51sd.c +++ b/arch/arm/mach-imx/mach-cpuimx51sd.c | |||
| @@ -217,18 +217,18 @@ static const struct mxc_usbh_platform_data usbh1_config __initconst = { | |||
| 217 | .portsc = MXC_EHCI_MODE_ULPI, | 217 | .portsc = MXC_EHCI_MODE_ULPI, |
| 218 | }; | 218 | }; |
| 219 | 219 | ||
| 220 | static int otg_mode_host; | 220 | static bool otg_mode_host __initdata; |
| 221 | 221 | ||
| 222 | static int __init eukrea_cpuimx51sd_otg_mode(char *options) | 222 | static int __init eukrea_cpuimx51sd_otg_mode(char *options) |
| 223 | { | 223 | { |
| 224 | if (!strcmp(options, "host")) | 224 | if (!strcmp(options, "host")) |
| 225 | otg_mode_host = 1; | 225 | otg_mode_host = true; |
| 226 | else if (!strcmp(options, "device")) | 226 | else if (!strcmp(options, "device")) |
| 227 | otg_mode_host = 0; | 227 | otg_mode_host = false; |
| 228 | else | 228 | else |
| 229 | pr_info("otg_mode neither \"host\" nor \"device\". " | 229 | pr_info("otg_mode neither \"host\" nor \"device\". " |
| 230 | "Defaulting to device\n"); | 230 | "Defaulting to device\n"); |
| 231 | return 0; | 231 | return 1; |
| 232 | } | 232 | } |
| 233 | __setup("otg_mode=", eukrea_cpuimx51sd_otg_mode); | 233 | __setup("otg_mode=", eukrea_cpuimx51sd_otg_mode); |
| 234 | 234 | ||
| @@ -292,7 +292,7 @@ static void __init eukrea_cpuimx51sd_init(void) | |||
| 292 | 292 | ||
| 293 | imx51_add_imx_uart(0, &uart_pdata); | 293 | imx51_add_imx_uart(0, &uart_pdata); |
| 294 | imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info); | 294 | imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info); |
| 295 | imx51_add_imx2_wdt(0, NULL); | 295 | imx51_add_imx2_wdt(0); |
| 296 | 296 | ||
| 297 | gpio_request(ETH_RST, "eth_rst"); | 297 | gpio_request(ETH_RST, "eth_rst"); |
| 298 | gpio_set_value(ETH_RST, 1); | 298 | gpio_set_value(ETH_RST, 1); |
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c index d1e04e676e33..017bbb70ea41 100644 --- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c +++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c | |||
| @@ -109,18 +109,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { | |||
| 109 | .workaround = FLS_USB2_WORKAROUND_ENGCM09152, | 109 | .workaround = FLS_USB2_WORKAROUND_ENGCM09152, |
| 110 | }; | 110 | }; |
| 111 | 111 | ||
| 112 | static int otg_mode_host; | 112 | static bool otg_mode_host __initdata; |
| 113 | 113 | ||
| 114 | static int __init eukrea_cpuimx25_otg_mode(char *options) | 114 | static int __init eukrea_cpuimx25_otg_mode(char *options) |
| 115 | { | 115 | { |
| 116 | if (!strcmp(options, "host")) | 116 | if (!strcmp(options, "host")) |
| 117 | otg_mode_host = 1; | 117 | otg_mode_host = true; |
| 118 | else if (!strcmp(options, "device")) | 118 | else if (!strcmp(options, "device")) |
| 119 | otg_mode_host = 0; | 119 | otg_mode_host = false; |
| 120 | else | 120 | else |
| 121 | pr_info("otg_mode neither \"host\" nor \"device\". " | 121 | pr_info("otg_mode neither \"host\" nor \"device\". " |
| 122 | "Defaulting to device\n"); | 122 | "Defaulting to device\n"); |
| 123 | return 0; | 123 | return 1; |
| 124 | } | 124 | } |
| 125 | __setup("otg_mode=", eukrea_cpuimx25_otg_mode); | 125 | __setup("otg_mode=", eukrea_cpuimx25_otg_mode); |
| 126 | 126 | ||
| @@ -134,9 +134,9 @@ static void __init eukrea_cpuimx25_init(void) | |||
| 134 | 134 | ||
| 135 | imx25_add_imx_uart0(&uart_pdata); | 135 | imx25_add_imx_uart0(&uart_pdata); |
| 136 | imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info); | 136 | imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info); |
| 137 | imx25_add_imxdi_rtc(NULL); | 137 | imx25_add_imxdi_rtc(); |
| 138 | imx25_add_fec(&mx25_fec_pdata); | 138 | imx25_add_fec(&mx25_fec_pdata); |
| 139 | imx25_add_imx2_wdt(NULL); | 139 | imx25_add_imx2_wdt(); |
| 140 | 140 | ||
| 141 | i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices, | 141 | i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices, |
| 142 | ARRAY_SIZE(eukrea_cpuimx25_i2c_devices)); | 142 | ARRAY_SIZE(eukrea_cpuimx25_i2c_devices)); |
diff --git a/arch/arm/mach-imx/mach-imx27ipcam.c b/arch/arm/mach-imx/mach-imx27ipcam.c index c9d350c5dcc8..7381387a8905 100644 --- a/arch/arm/mach-imx/mach-imx27ipcam.c +++ b/arch/arm/mach-imx/mach-imx27ipcam.c | |||
| @@ -57,7 +57,7 @@ static void __init mx27ipcam_init(void) | |||
| 57 | 57 | ||
| 58 | imx27_add_imx_uart0(NULL); | 58 | imx27_add_imx_uart0(NULL); |
| 59 | imx27_add_fec(NULL); | 59 | imx27_add_fec(NULL); |
| 60 | imx27_add_imx2_wdt(NULL); | 60 | imx27_add_imx2_wdt(); |
| 61 | } | 61 | } |
| 62 | 62 | ||
| 63 | static void __init mx27ipcam_timer_init(void) | 63 | static void __init mx27ipcam_timer_init(void) |
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c index f26734298aa6..ce247fd1269a 100644 --- a/arch/arm/mach-imx/mach-mx25_3ds.c +++ b/arch/arm/mach-imx/mach-mx25_3ds.c | |||
| @@ -237,9 +237,9 @@ static void __init mx25pdk_init(void) | |||
| 237 | imx25_add_fsl_usb2_udc(&otg_device_pdata); | 237 | imx25_add_fsl_usb2_udc(&otg_device_pdata); |
| 238 | imx25_add_mxc_ehci_hs(&usbh2_pdata); | 238 | imx25_add_mxc_ehci_hs(&usbh2_pdata); |
| 239 | imx25_add_mxc_nand(&mx25pdk_nand_board_info); | 239 | imx25_add_mxc_nand(&mx25pdk_nand_board_info); |
| 240 | imx25_add_imxdi_rtc(NULL); | 240 | imx25_add_imxdi_rtc(); |
| 241 | imx25_add_imx_fb(&mx25pdk_fb_pdata); | 241 | imx25_add_imx_fb(&mx25pdk_fb_pdata); |
| 242 | imx25_add_imx2_wdt(NULL); | 242 | imx25_add_imx2_wdt(); |
| 243 | 243 | ||
| 244 | mx25pdk_fec_reset(); | 244 | mx25pdk_fec_reset(); |
| 245 | imx25_add_fec(&mx25_fec_pdata); | 245 | imx25_add_fec(&mx25_fec_pdata); |
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c index c6d385c52257..ce9a5c26290c 100644 --- a/arch/arm/mach-imx/mach-mx27_3ds.c +++ b/arch/arm/mach-imx/mach-mx27_3ds.c | |||
| @@ -241,18 +241,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { | |||
| 241 | .phy_mode = FSL_USB2_PHY_ULPI, | 241 | .phy_mode = FSL_USB2_PHY_ULPI, |
| 242 | }; | 242 | }; |
| 243 | 243 | ||
| 244 | static int otg_mode_host; | 244 | static bool otg_mode_host __initdata; |
| 245 | 245 | ||
| 246 | static int __init mx27_3ds_otg_mode(char *options) | 246 | static int __init mx27_3ds_otg_mode(char *options) |
| 247 | { | 247 | { |
| 248 | if (!strcmp(options, "host")) | 248 | if (!strcmp(options, "host")) |
| 249 | otg_mode_host = 1; | 249 | otg_mode_host = true; |
| 250 | else if (!strcmp(options, "device")) | 250 | else if (!strcmp(options, "device")) |
| 251 | otg_mode_host = 0; | 251 | otg_mode_host = false; |
| 252 | else | 252 | else |
| 253 | pr_info("otg_mode neither \"host\" nor \"device\". " | 253 | pr_info("otg_mode neither \"host\" nor \"device\". " |
| 254 | "Defaulting to device\n"); | 254 | "Defaulting to device\n"); |
| 255 | return 0; | 255 | return 1; |
| 256 | } | 256 | } |
| 257 | __setup("otg_mode=", mx27_3ds_otg_mode); | 257 | __setup("otg_mode=", mx27_3ds_otg_mode); |
| 258 | 258 | ||
| @@ -480,7 +480,7 @@ static void __init mx27pdk_init(void) | |||
| 480 | imx27_add_fec(NULL); | 480 | imx27_add_fec(NULL); |
| 481 | imx27_add_imx_keypad(&mx27_3ds_keymap_data); | 481 | imx27_add_imx_keypad(&mx27_3ds_keymap_data); |
| 482 | imx27_add_mxc_mmc(0, &sdhc1_pdata); | 482 | imx27_add_mxc_mmc(0, &sdhc1_pdata); |
| 483 | imx27_add_imx2_wdt(NULL); | 483 | imx27_add_imx2_wdt(); |
| 484 | otg_phy_init(); | 484 | otg_phy_init(); |
| 485 | 485 | ||
| 486 | if (otg_mode_host) { | 486 | if (otg_mode_host) { |
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c index 0228d2e07fe0..7936bb32264d 100644 --- a/arch/arm/mach-imx/mach-mx27ads.c +++ b/arch/arm/mach-imx/mach-mx27ads.c | |||
| @@ -310,7 +310,7 @@ static void __init mx27ads_board_init(void) | |||
| 310 | 310 | ||
| 311 | imx27_add_fec(NULL); | 311 | imx27_add_fec(NULL); |
| 312 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); | 312 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); |
| 313 | imx27_add_mxc_w1(NULL); | 313 | imx27_add_mxc_w1(); |
| 314 | } | 314 | } |
| 315 | 315 | ||
| 316 | static void __init mx27ads_timer_init(void) | 316 | static void __init mx27ads_timer_init(void) |
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c index 4eafdf275ea2..928e1dcbc6a7 100644 --- a/arch/arm/mach-imx/mach-mx31_3ds.c +++ b/arch/arm/mach-imx/mach-mx31_3ds.c | |||
| @@ -671,18 +671,18 @@ static const struct fsl_usb2_platform_data usbotg_pdata __initconst = { | |||
| 671 | .phy_mode = FSL_USB2_PHY_ULPI, | 671 | .phy_mode = FSL_USB2_PHY_ULPI, |
| 672 | }; | 672 | }; |
| 673 | 673 | ||
| 674 | static int otg_mode_host; | 674 | static bool otg_mode_host __initdata; |
| 675 | 675 | ||
| 676 | static int __init mx31_3ds_otg_mode(char *options) | 676 | static int __init mx31_3ds_otg_mode(char *options) |
| 677 | { | 677 | { |
| 678 | if (!strcmp(options, "host")) | 678 | if (!strcmp(options, "host")) |
| 679 | otg_mode_host = 1; | 679 | otg_mode_host = true; |
| 680 | else if (!strcmp(options, "device")) | 680 | else if (!strcmp(options, "device")) |
| 681 | otg_mode_host = 0; | 681 | otg_mode_host = false; |
| 682 | else | 682 | else |
| 683 | pr_info("otg_mode neither \"host\" nor \"device\". " | 683 | pr_info("otg_mode neither \"host\" nor \"device\". " |
| 684 | "Defaulting to device\n"); | 684 | "Defaulting to device\n"); |
| 685 | return 0; | 685 | return 1; |
| 686 | } | 686 | } |
| 687 | __setup("otg_mode=", mx31_3ds_otg_mode); | 687 | __setup("otg_mode=", mx31_3ds_otg_mode); |
| 688 | 688 | ||
| @@ -739,7 +739,7 @@ static void __init mx31_3ds_init(void) | |||
| 739 | if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT)) | 739 | if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT)) |
| 740 | printk(KERN_WARNING "Init of the debug board failed, all " | 740 | printk(KERN_WARNING "Init of the debug board failed, all " |
| 741 | "devices on the debug board are unusable.\n"); | 741 | "devices on the debug board are unusable.\n"); |
| 742 | imx31_add_imx2_wdt(NULL); | 742 | imx31_add_imx2_wdt(); |
| 743 | imx31_add_imx_i2c0(&mx31_3ds_i2c0_data); | 743 | imx31_add_imx_i2c0(&mx31_3ds_i2c0_data); |
| 744 | imx31_add_mxc_mmc(0, &sdhc1_pdata); | 744 | imx31_add_mxc_mmc(0, &sdhc1_pdata); |
| 745 | 745 | ||
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c index 016791f038b0..63e84e67b990 100644 --- a/arch/arm/mach-imx/mach-mx31moboard.c +++ b/arch/arm/mach-imx/mach-mx31moboard.c | |||
| @@ -544,7 +544,7 @@ static void __init mx31moboard_init(void) | |||
| 544 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 544 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 545 | gpio_led_register_device(-1, &mx31moboard_led_pdata); | 545 | gpio_led_register_device(-1, &mx31moboard_led_pdata); |
| 546 | 546 | ||
| 547 | imx31_add_imx2_wdt(NULL); | 547 | imx31_add_imx2_wdt(); |
| 548 | 548 | ||
| 549 | imx31_add_imx_uart0(&uart0_pdata); | 549 | imx31_add_imx_uart0(&uart0_pdata); |
| 550 | imx31_add_imx_uart4(&uart4_pdata); | 550 | imx31_add_imx_uart4(&uart4_pdata); |
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c index 28aa19476de7..69018e5c52de 100644 --- a/arch/arm/mach-imx/mach-mx35_3ds.c +++ b/arch/arm/mach-imx/mach-mx35_3ds.c | |||
| @@ -540,18 +540,18 @@ static const struct mxc_usbh_platform_data usb_host_pdata __initconst = { | |||
| 540 | .portsc = MXC_EHCI_MODE_SERIAL, | 540 | .portsc = MXC_EHCI_MODE_SERIAL, |
| 541 | }; | 541 | }; |
| 542 | 542 | ||
| 543 | static int otg_mode_host; | 543 | static bool otg_mode_host __initdata; |
| 544 | 544 | ||
| 545 | static int __init mx35_3ds_otg_mode(char *options) | 545 | static int __init mx35_3ds_otg_mode(char *options) |
| 546 | { | 546 | { |
| 547 | if (!strcmp(options, "host")) | 547 | if (!strcmp(options, "host")) |
| 548 | otg_mode_host = 1; | 548 | otg_mode_host = true; |
| 549 | else if (!strcmp(options, "device")) | 549 | else if (!strcmp(options, "device")) |
| 550 | otg_mode_host = 0; | 550 | otg_mode_host = false; |
| 551 | else | 551 | else |
| 552 | pr_info("otg_mode neither \"host\" nor \"device\". " | 552 | pr_info("otg_mode neither \"host\" nor \"device\". " |
| 553 | "Defaulting to device\n"); | 553 | "Defaulting to device\n"); |
| 554 | return 0; | 554 | return 1; |
| 555 | } | 555 | } |
| 556 | __setup("otg_mode=", mx35_3ds_otg_mode); | 556 | __setup("otg_mode=", mx35_3ds_otg_mode); |
| 557 | 557 | ||
| @@ -571,7 +571,8 @@ static void __init mx35_3ds_init(void) | |||
| 571 | mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads)); | 571 | mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads)); |
| 572 | 572 | ||
| 573 | imx35_add_fec(NULL); | 573 | imx35_add_fec(NULL); |
| 574 | imx35_add_imx2_wdt(NULL); | 574 | imx35_add_imx2_wdt(); |
| 575 | imx35_add_mxc_rtc(); | ||
| 575 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 576 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 576 | 577 | ||
| 577 | imx35_add_imx_uart0(&uart_pdata); | 578 | imx35_add_imx_uart0(&uart_pdata); |
diff --git a/arch/arm/mach-imx/mach-mx51_3ds.c b/arch/arm/mach-imx/mach-mx51_3ds.c index 3c5b163923f6..2edb563b968d 100644 --- a/arch/arm/mach-imx/mach-mx51_3ds.c +++ b/arch/arm/mach-imx/mach-mx51_3ds.c | |||
| @@ -154,7 +154,7 @@ static void __init mx51_3ds_init(void) | |||
| 154 | 154 | ||
| 155 | imx51_add_sdhci_esdhc_imx(0, NULL); | 155 | imx51_add_sdhci_esdhc_imx(0, NULL); |
| 156 | imx51_add_imx_keypad(&mx51_3ds_map_data); | 156 | imx51_add_imx_keypad(&mx51_3ds_map_data); |
| 157 | imx51_add_imx2_wdt(0, NULL); | 157 | imx51_add_imx2_wdt(0); |
| 158 | } | 158 | } |
| 159 | 159 | ||
| 160 | static void __init mx51_3ds_timer_init(void) | 160 | static void __init mx51_3ds_timer_init(void) |
diff --git a/arch/arm/mach-imx/mach-mx51_babbage.c b/arch/arm/mach-imx/mach-mx51_babbage.c index dde397014d4b..7b31cbde8775 100644 --- a/arch/arm/mach-imx/mach-mx51_babbage.c +++ b/arch/arm/mach-imx/mach-mx51_babbage.c | |||
| @@ -307,18 +307,18 @@ static const struct mxc_usbh_platform_data usbh1_config __initconst = { | |||
| 307 | .portsc = MXC_EHCI_MODE_ULPI, | 307 | .portsc = MXC_EHCI_MODE_ULPI, |
| 308 | }; | 308 | }; |
| 309 | 309 | ||
| 310 | static int otg_mode_host; | 310 | static bool otg_mode_host __initdata; |
| 311 | 311 | ||
| 312 | static int __init babbage_otg_mode(char *options) | 312 | static int __init babbage_otg_mode(char *options) |
| 313 | { | 313 | { |
| 314 | if (!strcmp(options, "host")) | 314 | if (!strcmp(options, "host")) |
| 315 | otg_mode_host = 1; | 315 | otg_mode_host = true; |
| 316 | else if (!strcmp(options, "device")) | 316 | else if (!strcmp(options, "device")) |
| 317 | otg_mode_host = 0; | 317 | otg_mode_host = false; |
| 318 | else | 318 | else |
| 319 | pr_info("otg_mode neither \"host\" nor \"device\". " | 319 | pr_info("otg_mode neither \"host\" nor \"device\". " |
| 320 | "Defaulting to device\n"); | 320 | "Defaulting to device\n"); |
| 321 | return 0; | 321 | return 1; |
| 322 | } | 322 | } |
| 323 | __setup("otg_mode=", babbage_otg_mode); | 323 | __setup("otg_mode=", babbage_otg_mode); |
| 324 | 324 | ||
| @@ -411,7 +411,7 @@ static void __init mx51_babbage_init(void) | |||
| 411 | spi_register_board_info(mx51_babbage_spi_board_info, | 411 | spi_register_board_info(mx51_babbage_spi_board_info, |
| 412 | ARRAY_SIZE(mx51_babbage_spi_board_info)); | 412 | ARRAY_SIZE(mx51_babbage_spi_board_info)); |
| 413 | imx51_add_ecspi(0, &mx51_babbage_spi_pdata); | 413 | imx51_add_ecspi(0, &mx51_babbage_spi_pdata); |
| 414 | imx51_add_imx2_wdt(0, NULL); | 414 | imx51_add_imx2_wdt(0); |
| 415 | } | 415 | } |
| 416 | 416 | ||
| 417 | static void __init mx51_babbage_timer_init(void) | 417 | static void __init mx51_babbage_timer_init(void) |
diff --git a/arch/arm/mach-imx/mach-mx53_ard.c b/arch/arm/mach-imx/mach-mx53_ard.c index 05641980dc5e..4a7593a953e2 100644 --- a/arch/arm/mach-imx/mach-mx53_ard.c +++ b/arch/arm/mach-imx/mach-mx53_ard.c | |||
| @@ -243,7 +243,7 @@ static void __init mx53_ard_board_init(void) | |||
| 243 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 243 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 244 | 244 | ||
| 245 | imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data); | 245 | imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data); |
| 246 | imx53_add_imx2_wdt(0, NULL); | 246 | imx53_add_imx2_wdt(0); |
| 247 | imx53_add_imx_i2c(1, &mx53_ard_i2c2_data); | 247 | imx53_add_imx_i2c(1, &mx53_ard_i2c2_data); |
| 248 | imx53_add_imx_i2c(2, &mx53_ard_i2c3_data); | 248 | imx53_add_imx_i2c(2, &mx53_ard_i2c3_data); |
| 249 | imx_add_gpio_keys(&ard_button_data); | 249 | imx_add_gpio_keys(&ard_button_data); |
diff --git a/arch/arm/mach-imx/mach-mx53_evk.c b/arch/arm/mach-imx/mach-mx53_evk.c index 5a72188b9cdb..a1060b26fb23 100644 --- a/arch/arm/mach-imx/mach-mx53_evk.c +++ b/arch/arm/mach-imx/mach-mx53_evk.c | |||
| @@ -154,7 +154,7 @@ static void __init mx53_evk_board_init(void) | |||
| 154 | spi_register_board_info(mx53_evk_spi_board_info, | 154 | spi_register_board_info(mx53_evk_spi_board_info, |
| 155 | ARRAY_SIZE(mx53_evk_spi_board_info)); | 155 | ARRAY_SIZE(mx53_evk_spi_board_info)); |
| 156 | imx53_add_ecspi(0, &mx53_evk_spi_data); | 156 | imx53_add_ecspi(0, &mx53_evk_spi_data); |
| 157 | imx53_add_imx2_wdt(0, NULL); | 157 | imx53_add_imx2_wdt(0); |
| 158 | gpio_led_register_device(-1, &mx53evk_leds_data); | 158 | gpio_led_register_device(-1, &mx53evk_leds_data); |
| 159 | } | 159 | } |
| 160 | 160 | ||
diff --git a/arch/arm/mach-imx/mach-mx53_loco.c b/arch/arm/mach-imx/mach-mx53_loco.c index 37f67cac15a4..388c415d6b62 100644 --- a/arch/arm/mach-imx/mach-mx53_loco.c +++ b/arch/arm/mach-imx/mach-mx53_loco.c | |||
| @@ -283,7 +283,7 @@ static void __init mx53_loco_board_init(void) | |||
| 283 | imx53_add_imx_uart(0, NULL); | 283 | imx53_add_imx_uart(0, NULL); |
| 284 | mx53_loco_fec_reset(); | 284 | mx53_loco_fec_reset(); |
| 285 | imx53_add_fec(&mx53_loco_fec_data); | 285 | imx53_add_fec(&mx53_loco_fec_data); |
| 286 | imx53_add_imx2_wdt(0, NULL); | 286 | imx53_add_imx2_wdt(0); |
| 287 | 287 | ||
| 288 | ret = gpio_request_one(LOCO_ACCEL_EN, GPIOF_OUT_INIT_HIGH, "accel_en"); | 288 | ret = gpio_request_one(LOCO_ACCEL_EN, GPIOF_OUT_INIT_HIGH, "accel_en"); |
| 289 | if (ret) | 289 | if (ret) |
diff --git a/arch/arm/mach-imx/mach-mx53_smd.c b/arch/arm/mach-imx/mach-mx53_smd.c index 8e972c5c3e13..f297df7ccb39 100644 --- a/arch/arm/mach-imx/mach-mx53_smd.c +++ b/arch/arm/mach-imx/mach-mx53_smd.c | |||
| @@ -138,7 +138,7 @@ static void __init mx53_smd_board_init(void) | |||
| 138 | mx53_smd_init_uart(); | 138 | mx53_smd_init_uart(); |
| 139 | mx53_smd_fec_reset(); | 139 | mx53_smd_fec_reset(); |
| 140 | imx53_add_fec(&mx53_smd_fec_data); | 140 | imx53_add_fec(&mx53_smd_fec_data); |
| 141 | imx53_add_imx2_wdt(0, NULL); | 141 | imx53_add_imx2_wdt(0); |
| 142 | imx53_add_imx_i2c(0, &mx53_smd_i2c_data); | 142 | imx53_add_imx_i2c(0, &mx53_smd_i2c_data); |
| 143 | imx53_add_sdhci_esdhc_imx(0, NULL); | 143 | imx53_add_sdhci_esdhc_imx(0, NULL); |
| 144 | imx53_add_sdhci_esdhc_imx(1, NULL); | 144 | imx53_add_sdhci_esdhc_imx(1, NULL); |
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c index 541152e450c4..d37ed25003b2 100644 --- a/arch/arm/mach-imx/mach-pca100.c +++ b/arch/arm/mach-imx/mach-pca100.c | |||
| @@ -298,18 +298,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { | |||
| 298 | .phy_mode = FSL_USB2_PHY_ULPI, | 298 | .phy_mode = FSL_USB2_PHY_ULPI, |
| 299 | }; | 299 | }; |
| 300 | 300 | ||
| 301 | static int otg_mode_host; | 301 | static bool otg_mode_host __initdata; |
| 302 | 302 | ||
| 303 | static int __init pca100_otg_mode(char *options) | 303 | static int __init pca100_otg_mode(char *options) |
| 304 | { | 304 | { |
| 305 | if (!strcmp(options, "host")) | 305 | if (!strcmp(options, "host")) |
| 306 | otg_mode_host = 1; | 306 | otg_mode_host = true; |
| 307 | else if (!strcmp(options, "device")) | 307 | else if (!strcmp(options, "device")) |
| 308 | otg_mode_host = 0; | 308 | otg_mode_host = false; |
| 309 | else | 309 | else |
| 310 | pr_info("otg_mode neither \"host\" nor \"device\". " | 310 | pr_info("otg_mode neither \"host\" nor \"device\". " |
| 311 | "Defaulting to device\n"); | 311 | "Defaulting to device\n"); |
| 312 | return 0; | 312 | return 1; |
| 313 | } | 313 | } |
| 314 | __setup("otg_mode=", pca100_otg_mode); | 314 | __setup("otg_mode=", pca100_otg_mode); |
| 315 | 315 | ||
| @@ -408,8 +408,8 @@ static void __init pca100_init(void) | |||
| 408 | imx27_add_imx_fb(&pca100_fb_data); | 408 | imx27_add_imx_fb(&pca100_fb_data); |
| 409 | 409 | ||
| 410 | imx27_add_fec(NULL); | 410 | imx27_add_fec(NULL); |
| 411 | imx27_add_imx2_wdt(NULL); | 411 | imx27_add_imx2_wdt(); |
| 412 | imx27_add_mxc_w1(NULL); | 412 | imx27_add_mxc_w1(); |
| 413 | } | 413 | } |
| 414 | 414 | ||
| 415 | static void __init pca100_timer_init(void) | 415 | static void __init pca100_timer_init(void) |
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c index 0a40004154f2..cd48712a6f50 100644 --- a/arch/arm/mach-imx/mach-pcm037.c +++ b/arch/arm/mach-imx/mach-pcm037.c | |||
| @@ -557,18 +557,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { | |||
| 557 | .phy_mode = FSL_USB2_PHY_ULPI, | 557 | .phy_mode = FSL_USB2_PHY_ULPI, |
| 558 | }; | 558 | }; |
| 559 | 559 | ||
| 560 | static int otg_mode_host; | 560 | static bool otg_mode_host __initdata; |
| 561 | 561 | ||
| 562 | static int __init pcm037_otg_mode(char *options) | 562 | static int __init pcm037_otg_mode(char *options) |
| 563 | { | 563 | { |
| 564 | if (!strcmp(options, "host")) | 564 | if (!strcmp(options, "host")) |
| 565 | otg_mode_host = 1; | 565 | otg_mode_host = true; |
| 566 | else if (!strcmp(options, "device")) | 566 | else if (!strcmp(options, "device")) |
| 567 | otg_mode_host = 0; | 567 | otg_mode_host = false; |
| 568 | else | 568 | else |
| 569 | pr_info("otg_mode neither \"host\" nor \"device\". " | 569 | pr_info("otg_mode neither \"host\" nor \"device\". " |
| 570 | "Defaulting to device\n"); | 570 | "Defaulting to device\n"); |
| 571 | return 0; | 571 | return 1; |
| 572 | } | 572 | } |
| 573 | __setup("otg_mode=", pcm037_otg_mode); | 573 | __setup("otg_mode=", pcm037_otg_mode); |
| 574 | 574 | ||
| @@ -619,13 +619,13 @@ static void __init pcm037_init(void) | |||
| 619 | 619 | ||
| 620 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 620 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 621 | 621 | ||
| 622 | imx31_add_imx2_wdt(NULL); | 622 | imx31_add_imx2_wdt(); |
| 623 | imx31_add_imx_uart0(&uart_pdata); | 623 | imx31_add_imx_uart0(&uart_pdata); |
| 624 | /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */ | 624 | /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */ |
| 625 | imx31_add_imx_uart1(&uart_pdata); | 625 | imx31_add_imx_uart1(&uart_pdata); |
| 626 | imx31_add_imx_uart2(&uart_pdata); | 626 | imx31_add_imx_uart2(&uart_pdata); |
| 627 | 627 | ||
| 628 | imx31_add_mxc_w1(NULL); | 628 | imx31_add_mxc_w1(); |
| 629 | 629 | ||
| 630 | /* LAN9217 IRQ pin */ | 630 | /* LAN9217 IRQ pin */ |
| 631 | ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq"); | 631 | ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq"); |
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c index 2f3debe2a113..3fbb89d74fcc 100644 --- a/arch/arm/mach-imx/mach-pcm038.c +++ b/arch/arm/mach-imx/mach-pcm038.c | |||
| @@ -332,8 +332,8 @@ static void __init pcm038_init(void) | |||
| 332 | 332 | ||
| 333 | imx27_add_fec(NULL); | 333 | imx27_add_fec(NULL); |
| 334 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); | 334 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); |
| 335 | imx27_add_imx2_wdt(NULL); | 335 | imx27_add_imx2_wdt(); |
| 336 | imx27_add_mxc_w1(NULL); | 336 | imx27_add_mxc_w1(); |
| 337 | 337 | ||
| 338 | #ifdef CONFIG_MACH_PCM970_BASEBOARD | 338 | #ifdef CONFIG_MACH_PCM970_BASEBOARD |
| 339 | pcm970_baseboard_init(); | 339 | pcm970_baseboard_init(); |
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c index 73585f55cca0..1f20f222375e 100644 --- a/arch/arm/mach-imx/mach-pcm043.c +++ b/arch/arm/mach-imx/mach-pcm043.c | |||
| @@ -330,18 +330,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { | |||
| 330 | .phy_mode = FSL_USB2_PHY_UTMI, | 330 | .phy_mode = FSL_USB2_PHY_UTMI, |
| 331 | }; | 331 | }; |
| 332 | 332 | ||
| 333 | static int otg_mode_host; | 333 | static bool otg_mode_host __initdata; |
| 334 | 334 | ||
| 335 | static int __init pcm043_otg_mode(char *options) | 335 | static int __init pcm043_otg_mode(char *options) |
| 336 | { | 336 | { |
| 337 | if (!strcmp(options, "host")) | 337 | if (!strcmp(options, "host")) |
| 338 | otg_mode_host = 1; | 338 | otg_mode_host = true; |
| 339 | else if (!strcmp(options, "device")) | 339 | else if (!strcmp(options, "device")) |
| 340 | otg_mode_host = 0; | 340 | otg_mode_host = false; |
| 341 | else | 341 | else |
| 342 | pr_info("otg_mode neither \"host\" nor \"device\". " | 342 | pr_info("otg_mode neither \"host\" nor \"device\". " |
| 343 | "Defaulting to device\n"); | 343 | "Defaulting to device\n"); |
| 344 | return 0; | 344 | return 1; |
| 345 | } | 345 | } |
| 346 | __setup("otg_mode=", pcm043_otg_mode); | 346 | __setup("otg_mode=", pcm043_otg_mode); |
| 347 | 347 | ||
| @@ -363,7 +363,7 @@ static void __init pcm043_init(void) | |||
| 363 | 363 | ||
| 364 | imx35_add_fec(NULL); | 364 | imx35_add_fec(NULL); |
| 365 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 365 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 366 | imx35_add_imx2_wdt(NULL); | 366 | imx35_add_imx2_wdt(); |
| 367 | 367 | ||
| 368 | imx35_add_imx_uart0(&uart_pdata); | 368 | imx35_add_imx_uart0(&uart_pdata); |
| 369 | imx35_add_mxc_nand(&pcm037_nand_board_info); | 369 | imx35_add_mxc_nand(&pcm037_nand_board_info); |
diff --git a/arch/arm/mach-imx/mach-qong.c b/arch/arm/mach-imx/mach-qong.c index 260621055b6b..a13087b11a6e 100644 --- a/arch/arm/mach-imx/mach-qong.c +++ b/arch/arm/mach-imx/mach-qong.c | |||
| @@ -252,7 +252,7 @@ static void __init qong_init(void) | |||
| 252 | mxc_init_imx_uart(); | 252 | mxc_init_imx_uart(); |
| 253 | qong_init_nor_mtd(); | 253 | qong_init_nor_mtd(); |
| 254 | qong_init_fpga(); | 254 | qong_init_fpga(); |
| 255 | imx31_add_imx2_wdt(NULL); | 255 | imx31_add_imx2_wdt(); |
| 256 | } | 256 | } |
| 257 | 257 | ||
| 258 | static void __init qong_timer_init(void) | 258 | static void __init qong_timer_init(void) |
diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c index add8c69c6c1a..b26209d4bcef 100644 --- a/arch/arm/mach-imx/mach-vpr200.c +++ b/arch/arm/mach-imx/mach-vpr200.c | |||
| @@ -272,7 +272,7 @@ static void __init vpr200_board_init(void) | |||
| 272 | mxc_iomux_v3_setup_multiple_pads(vpr200_pads, ARRAY_SIZE(vpr200_pads)); | 272 | mxc_iomux_v3_setup_multiple_pads(vpr200_pads, ARRAY_SIZE(vpr200_pads)); |
| 273 | 273 | ||
| 274 | imx35_add_fec(NULL); | 274 | imx35_add_fec(NULL); |
| 275 | imx35_add_imx2_wdt(NULL); | 275 | imx35_add_imx2_wdt(); |
| 276 | imx_add_gpio_keys(&vpr200_gpio_keys_data); | 276 | imx_add_gpio_keys(&vpr200_gpio_keys_data); |
| 277 | 277 | ||
| 278 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 278 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
diff --git a/arch/arm/mach-imx/mx31lite-db.c b/arch/arm/mach-imx/mx31lite-db.c index bf0fb87946ba..fa60ef6ac7ff 100644 --- a/arch/arm/mach-imx/mx31lite-db.c +++ b/arch/arm/mach-imx/mx31lite-db.c | |||
| @@ -191,6 +191,6 @@ void __init mx31lite_db_init(void) | |||
| 191 | imx31_add_mxc_mmc(0, &mmc_pdata); | 191 | imx31_add_mxc_mmc(0, &mmc_pdata); |
| 192 | imx31_add_spi_imx0(&spi0_pdata); | 192 | imx31_add_spi_imx0(&spi0_pdata); |
| 193 | gpio_led_register_device(-1, &litekit_led_platform_data); | 193 | gpio_led_register_device(-1, &litekit_led_platform_data); |
| 194 | imx31_add_imx2_wdt(NULL); | 194 | imx31_add_imx2_wdt(); |
| 195 | imx31_add_mxc_rtc(NULL); | 195 | imx31_add_mxc_rtc(); |
| 196 | } | 196 | } |
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c index e8d315e6db09..f48c2e961b84 100644 --- a/arch/arm/mach-lpc32xx/clock.c +++ b/arch/arm/mach-lpc32xx/clock.c | |||
| @@ -607,6 +607,19 @@ static struct clk clk_dma = { | |||
| 607 | .get_rate = local_return_parent_rate, | 607 | .get_rate = local_return_parent_rate, |
| 608 | }; | 608 | }; |
| 609 | 609 | ||
| 610 | static struct clk clk_pwm = { | ||
| 611 | .parent = &clk_pclk, | ||
| 612 | .enable = local_onoff_enable, | ||
| 613 | .enable_reg = LPC32XX_CLKPWR_PWM_CLK_CTRL, | ||
| 614 | .enable_mask = LPC32XX_CLKPWR_PWMCLK_PWM1CLK_EN | | ||
| 615 | LPC32XX_CLKPWR_PWMCLK_PWM1SEL_PCLK | | ||
| 616 | LPC32XX_CLKPWR_PWMCLK_PWM1_DIV(1) | | ||
| 617 | LPC32XX_CLKPWR_PWMCLK_PWM2CLK_EN | | ||
| 618 | LPC32XX_CLKPWR_PWMCLK_PWM2SEL_PCLK | | ||
| 619 | LPC32XX_CLKPWR_PWMCLK_PWM2_DIV(1), | ||
| 620 | .get_rate = local_return_parent_rate, | ||
| 621 | }; | ||
| 622 | |||
| 610 | static struct clk clk_uart3 = { | 623 | static struct clk clk_uart3 = { |
| 611 | .parent = &clk_pclk, | 624 | .parent = &clk_pclk, |
| 612 | .enable = local_onoff_enable, | 625 | .enable = local_onoff_enable, |
| @@ -739,14 +752,77 @@ static struct clk clk_rtc = { | |||
| 739 | .get_rate = local_return_parent_rate, | 752 | .get_rate = local_return_parent_rate, |
| 740 | }; | 753 | }; |
| 741 | 754 | ||
| 755 | static int local_usb_enable(struct clk *clk, int enable) | ||
| 756 | { | ||
| 757 | u32 tmp; | ||
| 758 | |||
| 759 | if (enable) { | ||
| 760 | /* Set up I2C pull levels */ | ||
| 761 | tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL); | ||
| 762 | tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE; | ||
| 763 | __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL); | ||
| 764 | } | ||
| 765 | |||
| 766 | return local_onoff_enable(clk, enable); | ||
| 767 | } | ||
| 768 | |||
| 742 | static struct clk clk_usbd = { | 769 | static struct clk clk_usbd = { |
| 743 | .parent = &clk_usbpll, | 770 | .parent = &clk_usbpll, |
| 744 | .enable = local_onoff_enable, | 771 | .enable = local_usb_enable, |
| 745 | .enable_reg = LPC32XX_CLKPWR_USB_CTRL, | 772 | .enable_reg = LPC32XX_CLKPWR_USB_CTRL, |
| 746 | .enable_mask = LPC32XX_CLKPWR_USBCTRL_HCLK_EN, | 773 | .enable_mask = LPC32XX_CLKPWR_USBCTRL_HCLK_EN, |
| 747 | .get_rate = local_return_parent_rate, | 774 | .get_rate = local_return_parent_rate, |
| 748 | }; | 775 | }; |
| 749 | 776 | ||
| 777 | #define OTG_ALWAYS_MASK (LPC32XX_USB_OTG_OTG_CLOCK_ON | \ | ||
| 778 | LPC32XX_USB_OTG_I2C_CLOCK_ON) | ||
| 779 | |||
| 780 | static int local_usb_otg_enable(struct clk *clk, int enable) | ||
| 781 | { | ||
| 782 | int to = 1000; | ||
| 783 | |||
| 784 | if (enable) { | ||
| 785 | __raw_writel(clk->enable_mask, clk->enable_reg); | ||
| 786 | |||
| 787 | while (((__raw_readl(LPC32XX_USB_OTG_CLK_STAT) & | ||
| 788 | clk->enable_mask) != clk->enable_mask) && (to > 0)) | ||
| 789 | to--; | ||
| 790 | } else { | ||
| 791 | __raw_writel(OTG_ALWAYS_MASK, clk->enable_reg); | ||
| 792 | |||
| 793 | while (((__raw_readl(LPC32XX_USB_OTG_CLK_STAT) & | ||
| 794 | OTG_ALWAYS_MASK) != OTG_ALWAYS_MASK) && (to > 0)) | ||
| 795 | to--; | ||
| 796 | } | ||
| 797 | |||
| 798 | if (to) | ||
| 799 | return 0; | ||
| 800 | else | ||
| 801 | return -1; | ||
| 802 | } | ||
| 803 | |||
| 804 | static struct clk clk_usb_otg_dev = { | ||
| 805 | .parent = &clk_usbpll, | ||
| 806 | .enable = local_usb_otg_enable, | ||
| 807 | .enable_reg = LPC32XX_USB_OTG_CLK_CTRL, | ||
| 808 | .enable_mask = LPC32XX_USB_OTG_AHB_M_CLOCK_ON | | ||
| 809 | LPC32XX_USB_OTG_OTG_CLOCK_ON | | ||
| 810 | LPC32XX_USB_OTG_DEV_CLOCK_ON | | ||
| 811 | LPC32XX_USB_OTG_I2C_CLOCK_ON, | ||
| 812 | .get_rate = local_return_parent_rate, | ||
| 813 | }; | ||
| 814 | |||
| 815 | static struct clk clk_usb_otg_host = { | ||
| 816 | .parent = &clk_usbpll, | ||
| 817 | .enable = local_usb_otg_enable, | ||
| 818 | .enable_reg = LPC32XX_USB_OTG_CLK_CTRL, | ||
| 819 | .enable_mask = LPC32XX_USB_OTG_AHB_M_CLOCK_ON | | ||
| 820 | LPC32XX_USB_OTG_OTG_CLOCK_ON | | ||
| 821 | LPC32XX_USB_OTG_HOST_CLOCK_ON | | ||
| 822 | LPC32XX_USB_OTG_I2C_CLOCK_ON, | ||
| 823 | .get_rate = local_return_parent_rate, | ||
| 824 | }; | ||
| 825 | |||
| 750 | static int tsc_onoff_enable(struct clk *clk, int enable) | 826 | static int tsc_onoff_enable(struct clk *clk, int enable) |
| 751 | { | 827 | { |
| 752 | u32 tmp; | 828 | u32 tmp; |
| @@ -812,11 +888,17 @@ static int mmc_onoff_enable(struct clk *clk, int enable) | |||
| 812 | u32 tmp; | 888 | u32 tmp; |
| 813 | 889 | ||
| 814 | tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) & | 890 | tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) & |
| 815 | ~LPC32XX_CLKPWR_MSCARD_SDCARD_EN; | 891 | ~(LPC32XX_CLKPWR_MSCARD_SDCARD_EN | |
| 892 | LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN | | ||
| 893 | LPC32XX_CLKPWR_MSCARD_MSDIO_PIN_DIS | | ||
| 894 | LPC32XX_CLKPWR_MSCARD_MSDIO0_DIS | | ||
| 895 | LPC32XX_CLKPWR_MSCARD_MSDIO1_DIS | | ||
| 896 | LPC32XX_CLKPWR_MSCARD_MSDIO23_DIS); | ||
| 816 | 897 | ||
| 817 | /* If rate is 0, disable clock */ | 898 | /* If rate is 0, disable clock */ |
| 818 | if (enable != 0) | 899 | if (enable != 0) |
| 819 | tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN; | 900 | tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN | |
| 901 | LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN; | ||
| 820 | 902 | ||
| 821 | __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL); | 903 | __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL); |
| 822 | 904 | ||
| @@ -865,7 +947,7 @@ static unsigned long mmc_round_rate(struct clk *clk, unsigned long rate) | |||
| 865 | 947 | ||
| 866 | static int mmc_set_rate(struct clk *clk, unsigned long rate) | 948 | static int mmc_set_rate(struct clk *clk, unsigned long rate) |
| 867 | { | 949 | { |
| 868 | u32 oldclk, tmp; | 950 | u32 tmp; |
| 869 | unsigned long prate, div, crate = mmc_round_rate(clk, rate); | 951 | unsigned long prate, div, crate = mmc_round_rate(clk, rate); |
| 870 | 952 | ||
| 871 | prate = clk->parent->get_rate(clk->parent); | 953 | prate = clk->parent->get_rate(clk->parent); |
| @@ -873,16 +955,12 @@ static int mmc_set_rate(struct clk *clk, unsigned long rate) | |||
| 873 | div = prate / crate; | 955 | div = prate / crate; |
| 874 | 956 | ||
| 875 | /* The MMC clock must be on when accessing an MMC register */ | 957 | /* The MMC clock must be on when accessing an MMC register */ |
| 876 | oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL); | ||
| 877 | __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN, | ||
| 878 | LPC32XX_CLKPWR_MS_CTRL); | ||
| 879 | tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) & | 958 | tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) & |
| 880 | ~LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf); | 959 | ~LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf); |
| 881 | tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div); | 960 | tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div) | |
| 961 | LPC32XX_CLKPWR_MSCARD_SDCARD_EN; | ||
| 882 | __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL); | 962 | __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL); |
| 883 | 963 | ||
| 884 | __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL); | ||
| 885 | |||
| 886 | return 0; | 964 | return 0; |
| 887 | } | 965 | } |
| 888 | 966 | ||
| @@ -1123,6 +1201,7 @@ static struct clk_lookup lookups[] = { | |||
| 1123 | CLKDEV_INIT(NULL, "vfp9_ck", &clk_vfp9), | 1201 | CLKDEV_INIT(NULL, "vfp9_ck", &clk_vfp9), |
| 1124 | CLKDEV_INIT("pl08xdmac", NULL, &clk_dma), | 1202 | CLKDEV_INIT("pl08xdmac", NULL, &clk_dma), |
| 1125 | CLKDEV_INIT("4003c000.watchdog", NULL, &clk_wdt), | 1203 | CLKDEV_INIT("4003c000.watchdog", NULL, &clk_wdt), |
| 1204 | CLKDEV_INIT("4005c000.pwm", NULL, &clk_pwm), | ||
| 1126 | CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3), | 1205 | CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3), |
| 1127 | CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4), | 1206 | CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4), |
| 1128 | CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5), | 1207 | CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5), |
| @@ -1143,6 +1222,9 @@ static struct clk_lookup lookups[] = { | |||
| 1143 | CLKDEV_INIT("31060000.ethernet", NULL, &clk_net), | 1222 | CLKDEV_INIT("31060000.ethernet", NULL, &clk_net), |
| 1144 | CLKDEV_INIT("dev:clcd", NULL, &clk_lcd), | 1223 | CLKDEV_INIT("dev:clcd", NULL, &clk_lcd), |
| 1145 | CLKDEV_INIT("31020000.usbd", "ck_usbd", &clk_usbd), | 1224 | CLKDEV_INIT("31020000.usbd", "ck_usbd", &clk_usbd), |
| 1225 | CLKDEV_INIT("31020000.ohci", "ck_usbd", &clk_usbd), | ||
| 1226 | CLKDEV_INIT("31020000.usbd", "ck_usb_otg", &clk_usb_otg_dev), | ||
| 1227 | CLKDEV_INIT("31020000.ohci", "ck_usb_otg", &clk_usb_otg_host), | ||
| 1146 | CLKDEV_INIT("lpc32xx_rtc", NULL, &clk_rtc), | 1228 | CLKDEV_INIT("lpc32xx_rtc", NULL, &clk_rtc), |
| 1147 | }; | 1229 | }; |
| 1148 | 1230 | ||
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c index 5c96057b6d78..a48dc2dec485 100644 --- a/arch/arm/mach-lpc32xx/common.c +++ b/arch/arm/mach-lpc32xx/common.c | |||
| @@ -26,6 +26,7 @@ | |||
| 26 | #include <linux/io.h> | 26 | #include <linux/io.h> |
| 27 | 27 | ||
| 28 | #include <asm/mach/map.h> | 28 | #include <asm/mach/map.h> |
| 29 | #include <asm/system_info.h> | ||
| 29 | 30 | ||
| 30 | #include <mach/hardware.h> | 31 | #include <mach/hardware.h> |
| 31 | #include <mach/platform.h> | 32 | #include <mach/platform.h> |
| @@ -224,7 +225,7 @@ void lpc23xx_restart(char mode, const char *cmd) | |||
| 224 | ; | 225 | ; |
| 225 | } | 226 | } |
| 226 | 227 | ||
| 227 | static int __init lpc32xx_display_uid(void) | 228 | static int __init lpc32xx_check_uid(void) |
| 228 | { | 229 | { |
| 229 | u32 uid[4]; | 230 | u32 uid[4]; |
| 230 | 231 | ||
| @@ -233,6 +234,11 @@ static int __init lpc32xx_display_uid(void) | |||
| 233 | printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n", | 234 | printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n", |
| 234 | uid[3], uid[2], uid[1], uid[0]); | 235 | uid[3], uid[2], uid[1], uid[0]); |
| 235 | 236 | ||
| 237 | if (!system_serial_low && !system_serial_high) { | ||
| 238 | system_serial_low = uid[0]; | ||
| 239 | system_serial_high = uid[1]; | ||
| 240 | } | ||
| 241 | |||
| 236 | return 1; | 242 | return 1; |
| 237 | } | 243 | } |
| 238 | arch_initcall(lpc32xx_display_uid); | 244 | arch_initcall(lpc32xx_check_uid); |
diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h index c584f5bb164f..acc4aabf1c7b 100644 --- a/arch/arm/mach-lpc32xx/include/mach/platform.h +++ b/arch/arm/mach-lpc32xx/include/mach/platform.h | |||
| @@ -694,4 +694,18 @@ | |||
| 694 | #define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C) | 694 | #define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C) |
| 695 | #define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030) | 695 | #define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030) |
| 696 | 696 | ||
| 697 | /* | ||
| 698 | * USB Otg Registers | ||
| 699 | */ | ||
| 700 | #define _OTGREG(x) io_p2v(LPC32XX_USB_OTG_BASE + (x)) | ||
| 701 | #define LPC32XX_USB_OTG_CLK_CTRL _OTGREG(0xFF4) | ||
| 702 | #define LPC32XX_USB_OTG_CLK_STAT _OTGREG(0xFF8) | ||
| 703 | |||
| 704 | /* USB OTG CLK CTRL bit defines */ | ||
| 705 | #define LPC32XX_USB_OTG_AHB_M_CLOCK_ON _BIT(4) | ||
| 706 | #define LPC32XX_USB_OTG_OTG_CLOCK_ON _BIT(3) | ||
| 707 | #define LPC32XX_USB_OTG_I2C_CLOCK_ON _BIT(2) | ||
| 708 | #define LPC32XX_USB_OTG_DEV_CLOCK_ON _BIT(1) | ||
| 709 | #define LPC32XX_USB_OTG_HOST_CLOCK_ON _BIT(0) | ||
| 710 | |||
| 697 | #endif | 711 | #endif |
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index c1aabfcbde49..b07dcc90829d 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c | |||
| @@ -51,12 +51,9 @@ | |||
| 51 | /* | 51 | /* |
| 52 | * Mapped GPIOLIB GPIOs | 52 | * Mapped GPIOLIB GPIOs |
| 53 | */ | 53 | */ |
| 54 | #define SPI0_CS_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5) | ||
| 55 | #define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0) | 54 | #define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0) |
| 56 | #define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4) | 55 | #define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4) |
| 57 | #define MMC_PWR_ENABLE_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5) | 56 | #define MMC_PWR_ENABLE_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5) |
| 58 | #define MMC_CD_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 1) | ||
| 59 | #define MMC_WP_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 0) | ||
| 60 | 57 | ||
| 61 | /* | 58 | /* |
| 62 | * AMBA LCD controller | 59 | * AMBA LCD controller |
| @@ -189,13 +186,12 @@ static struct pl08x_channel_data pl08x_slave_channels[] = { | |||
| 189 | }, | 186 | }, |
| 190 | }; | 187 | }; |
| 191 | 188 | ||
| 192 | /* NOTE: These will change, according to RMK */ | 189 | static int pl08x_get_signal(const struct pl08x_channel_data *cd) |
| 193 | static int pl08x_get_signal(struct pl08x_dma_chan *ch) | ||
| 194 | { | 190 | { |
| 195 | return ch->cd->min_signal; | 191 | return cd->min_signal; |
| 196 | } | 192 | } |
| 197 | 193 | ||
| 198 | static void pl08x_put_signal(struct pl08x_dma_chan *ch) | 194 | static void pl08x_put_signal(const struct pl08x_channel_data *cd, int ch) |
| 199 | { | 195 | { |
| 200 | } | 196 | } |
| 201 | 197 | ||
| @@ -248,25 +244,8 @@ static void __init lpc3250_machine_init(void) | |||
| 248 | tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16; | 244 | tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16; |
| 249 | __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL); | 245 | __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL); |
| 250 | 246 | ||
| 251 | /* Set up USB power */ | ||
| 252 | tmp = __raw_readl(LPC32XX_CLKPWR_USB_CTRL); | ||
| 253 | tmp |= LPC32XX_CLKPWR_USBCTRL_HCLK_EN | | ||
| 254 | LPC32XX_CLKPWR_USBCTRL_USBI2C_EN; | ||
| 255 | __raw_writel(tmp, LPC32XX_CLKPWR_USB_CTRL); | ||
| 256 | |||
| 257 | /* Set up I2C pull levels */ | ||
| 258 | tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL); | ||
| 259 | tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE | | ||
| 260 | LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE; | ||
| 261 | __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL); | ||
| 262 | |||
| 263 | lpc32xx_serial_init(); | 247 | lpc32xx_serial_init(); |
| 264 | 248 | ||
| 265 | tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL); | ||
| 266 | tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN | | ||
| 267 | LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN; | ||
| 268 | __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL); | ||
| 269 | |||
| 270 | /* Test clock needed for UDA1380 initial init */ | 249 | /* Test clock needed for UDA1380 initial init */ |
| 271 | __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC | | 250 | __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC | |
| 272 | LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN, | 251 | LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN, |
diff --git a/arch/arm/mach-mxs/module-tx28.c b/arch/arm/mach-mxs/module-tx28.c index 9a7b08b2a925..0f71f82101cc 100644 --- a/arch/arm/mach-mxs/module-tx28.c +++ b/arch/arm/mach-mxs/module-tx28.c | |||
| @@ -11,7 +11,7 @@ | |||
| 11 | #include <linux/gpio.h> | 11 | #include <linux/gpio.h> |
| 12 | 12 | ||
| 13 | #include <mach/iomux-mx28.h> | 13 | #include <mach/iomux-mx28.h> |
| 14 | #include "../devices-mx28.h" | 14 | #include "devices-mx28.h" |
| 15 | 15 | ||
| 16 | #include "module-tx28.h" | 16 | #include "module-tx28.h" |
| 17 | 17 | ||
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index f2f8a5847018..c53469802c03 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c | |||
| @@ -37,12 +37,12 @@ | |||
| 37 | #include <plat/board-ams-delta.h> | 37 | #include <plat/board-ams-delta.h> |
| 38 | #include <plat/keypad.h> | 38 | #include <plat/keypad.h> |
| 39 | #include <plat/mux.h> | 39 | #include <plat/mux.h> |
| 40 | #include <plat/usb.h> | ||
| 41 | #include <plat/board.h> | 40 | #include <plat/board.h> |
| 42 | 41 | ||
| 43 | #include <mach/hardware.h> | 42 | #include <mach/hardware.h> |
| 44 | #include <mach/ams-delta-fiq.h> | 43 | #include <mach/ams-delta-fiq.h> |
| 45 | #include <mach/camera.h> | 44 | #include <mach/camera.h> |
| 45 | #include <mach/usb.h> | ||
| 46 | 46 | ||
| 47 | #include "iomap.h" | 47 | #include "iomap.h" |
| 48 | #include "common.h" | 48 | #include "common.h" |
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c index e75e2d55a2d7..6ec385e2b98e 100644 --- a/arch/arm/mach-omap1/board-generic.c +++ b/arch/arm/mach-omap1/board-generic.c | |||
| @@ -23,8 +23,10 @@ | |||
| 23 | #include <asm/mach/map.h> | 23 | #include <asm/mach/map.h> |
| 24 | 24 | ||
| 25 | #include <plat/mux.h> | 25 | #include <plat/mux.h> |
| 26 | #include <plat/usb.h> | ||
| 27 | #include <plat/board.h> | 26 | #include <plat/board.h> |
| 27 | |||
| 28 | #include <mach/usb.h> | ||
| 29 | |||
| 28 | #include "common.h" | 30 | #include "common.h" |
| 29 | 31 | ||
| 30 | /* assume no Mini-AB port */ | 32 | /* assume no Mini-AB port */ |
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index a28e989a63f4..44a4ab195fbc 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c | |||
| @@ -40,11 +40,11 @@ | |||
| 40 | #include <plat/dma.h> | 40 | #include <plat/dma.h> |
| 41 | #include <plat/tc.h> | 41 | #include <plat/tc.h> |
| 42 | #include <plat/irda.h> | 42 | #include <plat/irda.h> |
| 43 | #include <plat/usb.h> | ||
| 44 | #include <plat/keypad.h> | 43 | #include <plat/keypad.h> |
| 45 | #include <plat/flash.h> | 44 | #include <plat/flash.h> |
| 46 | 45 | ||
| 47 | #include <mach/hardware.h> | 46 | #include <mach/hardware.h> |
| 47 | #include <mach/usb.h> | ||
| 48 | 48 | ||
| 49 | #include "common.h" | 49 | #include "common.h" |
| 50 | #include "board-h2.h" | 50 | #include "board-h2.h" |
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index 108a8640fc6f..86cb5a04a404 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c | |||
| @@ -40,13 +40,13 @@ | |||
| 40 | 40 | ||
| 41 | #include <plat/mux.h> | 41 | #include <plat/mux.h> |
| 42 | #include <plat/tc.h> | 42 | #include <plat/tc.h> |
| 43 | #include <plat/usb.h> | ||
| 44 | #include <plat/keypad.h> | 43 | #include <plat/keypad.h> |
| 45 | #include <plat/dma.h> | 44 | #include <plat/dma.h> |
| 46 | #include <plat/flash.h> | 45 | #include <plat/flash.h> |
| 47 | 46 | ||
| 48 | #include <mach/hardware.h> | 47 | #include <mach/hardware.h> |
| 49 | #include <mach/irqs.h> | 48 | #include <mach/irqs.h> |
| 49 | #include <mach/usb.h> | ||
| 50 | 50 | ||
| 51 | #include "common.h" | 51 | #include "common.h" |
| 52 | #include "board-h3.h" | 52 | #include "board-h3.h" |
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c index 118a9d4a4c54..b3f6e943e661 100644 --- a/arch/arm/mach-omap1/board-htcherald.c +++ b/arch/arm/mach-omap1/board-htcherald.c | |||
| @@ -44,10 +44,10 @@ | |||
| 44 | #include <plat/omap7xx.h> | 44 | #include <plat/omap7xx.h> |
| 45 | #include <plat/board.h> | 45 | #include <plat/board.h> |
| 46 | #include <plat/keypad.h> | 46 | #include <plat/keypad.h> |
| 47 | #include <plat/usb.h> | ||
| 48 | #include <plat/mmc.h> | 47 | #include <plat/mmc.h> |
| 49 | 48 | ||
| 50 | #include <mach/irqs.h> | 49 | #include <mach/irqs.h> |
| 50 | #include <mach/usb.h> | ||
| 51 | 51 | ||
| 52 | #include "common.h" | 52 | #include "common.h" |
| 53 | 53 | ||
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c index 7970223a559d..f21c2966daad 100644 --- a/arch/arm/mach-omap1/board-innovator.c +++ b/arch/arm/mach-omap1/board-innovator.c | |||
| @@ -35,11 +35,11 @@ | |||
| 35 | #include <plat/flash.h> | 35 | #include <plat/flash.h> |
| 36 | #include <plat/fpga.h> | 36 | #include <plat/fpga.h> |
| 37 | #include <plat/tc.h> | 37 | #include <plat/tc.h> |
| 38 | #include <plat/usb.h> | ||
| 39 | #include <plat/keypad.h> | 38 | #include <plat/keypad.h> |
| 40 | #include <plat/mmc.h> | 39 | #include <plat/mmc.h> |
| 41 | 40 | ||
| 42 | #include <mach/hardware.h> | 41 | #include <mach/hardware.h> |
| 42 | #include <mach/usb.h> | ||
| 43 | 43 | ||
| 44 | #include "iomap.h" | 44 | #include "iomap.h" |
| 45 | #include "common.h" | 45 | #include "common.h" |
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index 7212ae97f44a..4007a372481b 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c | |||
| @@ -26,7 +26,6 @@ | |||
| 26 | #include <asm/mach/map.h> | 26 | #include <asm/mach/map.h> |
| 27 | 27 | ||
| 28 | #include <plat/mux.h> | 28 | #include <plat/mux.h> |
| 29 | #include <plat/usb.h> | ||
| 30 | #include <plat/board.h> | 29 | #include <plat/board.h> |
| 31 | #include <plat/keypad.h> | 30 | #include <plat/keypad.h> |
| 32 | #include <plat/lcd_mipid.h> | 31 | #include <plat/lcd_mipid.h> |
| @@ -34,6 +33,7 @@ | |||
| 34 | #include <plat/clock.h> | 33 | #include <plat/clock.h> |
| 35 | 34 | ||
| 36 | #include <mach/hardware.h> | 35 | #include <mach/hardware.h> |
| 36 | #include <mach/usb.h> | ||
| 37 | 37 | ||
| 38 | #include "common.h" | 38 | #include "common.h" |
| 39 | 39 | ||
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index da8d872d3d1c..8784705edb60 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c | |||
| @@ -45,11 +45,11 @@ | |||
| 45 | #include <asm/mach/map.h> | 45 | #include <asm/mach/map.h> |
| 46 | 46 | ||
| 47 | #include <plat/flash.h> | 47 | #include <plat/flash.h> |
| 48 | #include <plat/usb.h> | ||
| 49 | #include <plat/mux.h> | 48 | #include <plat/mux.h> |
| 50 | #include <plat/tc.h> | 49 | #include <plat/tc.h> |
| 51 | 50 | ||
| 52 | #include <mach/hardware.h> | 51 | #include <mach/hardware.h> |
| 52 | #include <mach/usb.h> | ||
| 53 | 53 | ||
| 54 | #include "common.h" | 54 | #include "common.h" |
| 55 | 55 | ||
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c index 949b62a73693..26bcb9defcdc 100644 --- a/arch/arm/mach-omap1/board-palmte.c +++ b/arch/arm/mach-omap1/board-palmte.c | |||
| @@ -35,7 +35,6 @@ | |||
| 35 | 35 | ||
| 36 | #include <plat/flash.h> | 36 | #include <plat/flash.h> |
| 37 | #include <plat/mux.h> | 37 | #include <plat/mux.h> |
| 38 | #include <plat/usb.h> | ||
| 39 | #include <plat/tc.h> | 38 | #include <plat/tc.h> |
| 40 | #include <plat/dma.h> | 39 | #include <plat/dma.h> |
| 41 | #include <plat/board.h> | 40 | #include <plat/board.h> |
| @@ -43,6 +42,7 @@ | |||
| 43 | #include <plat/keypad.h> | 42 | #include <plat/keypad.h> |
| 44 | 43 | ||
| 45 | #include <mach/hardware.h> | 44 | #include <mach/hardware.h> |
| 45 | #include <mach/usb.h> | ||
| 46 | 46 | ||
| 47 | #include "common.h" | 47 | #include "common.h" |
| 48 | 48 | ||
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c index 7f1e1cf2bf46..4d099446dfa8 100644 --- a/arch/arm/mach-omap1/board-palmtt.c +++ b/arch/arm/mach-omap1/board-palmtt.c | |||
| @@ -35,7 +35,6 @@ | |||
| 35 | #include <plat/led.h> | 35 | #include <plat/led.h> |
| 36 | #include <plat/flash.h> | 36 | #include <plat/flash.h> |
| 37 | #include <plat/mux.h> | 37 | #include <plat/mux.h> |
| 38 | #include <plat/usb.h> | ||
| 39 | #include <plat/dma.h> | 38 | #include <plat/dma.h> |
| 40 | #include <plat/tc.h> | 39 | #include <plat/tc.h> |
| 41 | #include <plat/board.h> | 40 | #include <plat/board.h> |
| @@ -43,6 +42,7 @@ | |||
| 43 | #include <plat/keypad.h> | 42 | #include <plat/keypad.h> |
| 44 | 43 | ||
| 45 | #include <mach/hardware.h> | 44 | #include <mach/hardware.h> |
| 45 | #include <mach/usb.h> | ||
| 46 | 46 | ||
| 47 | #include "common.h" | 47 | #include "common.h" |
| 48 | 48 | ||
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index 3c71c6bace2c..cc71a26723ef 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c | |||
| @@ -37,7 +37,6 @@ | |||
| 37 | 37 | ||
| 38 | #include <plat/flash.h> | 38 | #include <plat/flash.h> |
| 39 | #include <plat/mux.h> | 39 | #include <plat/mux.h> |
| 40 | #include <plat/usb.h> | ||
| 41 | #include <plat/dma.h> | 40 | #include <plat/dma.h> |
| 42 | #include <plat/tc.h> | 41 | #include <plat/tc.h> |
| 43 | #include <plat/board.h> | 42 | #include <plat/board.h> |
| @@ -45,6 +44,7 @@ | |||
| 45 | #include <plat/keypad.h> | 44 | #include <plat/keypad.h> |
| 46 | 45 | ||
| 47 | #include <mach/hardware.h> | 46 | #include <mach/hardware.h> |
| 47 | #include <mach/usb.h> | ||
| 48 | 48 | ||
| 49 | #include "common.h" | 49 | #include "common.h" |
| 50 | 50 | ||
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c index 3b7b82b13684..8c665bd16ac2 100644 --- a/arch/arm/mach-omap1/board-sx1.c +++ b/arch/arm/mach-omap1/board-sx1.c | |||
| @@ -37,13 +37,13 @@ | |||
| 37 | #include <plat/mux.h> | 37 | #include <plat/mux.h> |
| 38 | #include <plat/dma.h> | 38 | #include <plat/dma.h> |
| 39 | #include <plat/irda.h> | 39 | #include <plat/irda.h> |
| 40 | #include <plat/usb.h> | ||
| 41 | #include <plat/tc.h> | 40 | #include <plat/tc.h> |
| 42 | #include <plat/board.h> | 41 | #include <plat/board.h> |
| 43 | #include <plat/keypad.h> | 42 | #include <plat/keypad.h> |
| 44 | #include <plat/board-sx1.h> | 43 | #include <plat/board-sx1.h> |
| 45 | 44 | ||
| 46 | #include <mach/hardware.h> | 45 | #include <mach/hardware.h> |
| 46 | #include <mach/usb.h> | ||
| 47 | 47 | ||
| 48 | #include "common.h" | 48 | #include "common.h" |
| 49 | 49 | ||
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index afd67f0ec495..3497769eb353 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c | |||
| @@ -35,9 +35,10 @@ | |||
| 35 | #include <plat/flash.h> | 35 | #include <plat/flash.h> |
| 36 | #include <plat/mux.h> | 36 | #include <plat/mux.h> |
| 37 | #include <plat/tc.h> | 37 | #include <plat/tc.h> |
| 38 | #include <plat/usb.h> | 38 | #include <plat/board.h> |
| 39 | 39 | ||
| 40 | #include <mach/hardware.h> | 40 | #include <mach/hardware.h> |
| 41 | #include <mach/usb.h> | ||
| 41 | 42 | ||
| 42 | #include "common.h" | 43 | #include "common.h" |
| 43 | 44 | ||
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index c6ce93f71d08..c007d80dfb62 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c | |||
| @@ -25,10 +25,11 @@ | |||
| 25 | #include <plat/clock.h> | 25 | #include <plat/clock.h> |
| 26 | #include <plat/cpu.h> | 26 | #include <plat/cpu.h> |
| 27 | #include <plat/clkdev_omap.h> | 27 | #include <plat/clkdev_omap.h> |
| 28 | #include <plat/board.h> | ||
| 28 | #include <plat/sram.h> /* for omap_sram_reprogram_clock() */ | 29 | #include <plat/sram.h> /* for omap_sram_reprogram_clock() */ |
| 29 | #include <plat/usb.h> /* for OTG_BASE */ | ||
| 30 | 30 | ||
| 31 | #include <mach/hardware.h> | 31 | #include <mach/hardware.h> |
| 32 | #include <mach/usb.h> /* for OTG_BASE */ | ||
| 32 | 33 | ||
| 33 | #include "iomap.h" | 34 | #include "iomap.h" |
| 34 | #include "clock.h" | 35 | #include "clock.h" |
diff --git a/arch/arm/mach-omap1/include/mach/usb.h b/arch/arm/mach-omap1/include/mach/usb.h new file mode 100644 index 000000000000..753cd5ce6949 --- /dev/null +++ b/arch/arm/mach-omap1/include/mach/usb.h | |||
| @@ -0,0 +1,165 @@ | |||
| 1 | /* | ||
| 2 | * FIXME correct answer depends on hmc_mode, | ||
| 3 | * as does (on omap1) any nonzero value for config->otg port number | ||
| 4 | */ | ||
| 5 | #ifdef CONFIG_USB_GADGET_OMAP | ||
| 6 | #define is_usb0_device(config) 1 | ||
| 7 | #else | ||
| 8 | #define is_usb0_device(config) 0 | ||
| 9 | #endif | ||
| 10 | |||
| 11 | struct omap_usb_config { | ||
| 12 | /* Configure drivers according to the connectors on your board: | ||
| 13 | * - "A" connector (rectagular) | ||
| 14 | * ... for host/OHCI use, set "register_host". | ||
| 15 | * - "B" connector (squarish) or "Mini-B" | ||
| 16 | * ... for device/gadget use, set "register_dev". | ||
| 17 | * - "Mini-AB" connector (very similar to Mini-B) | ||
| 18 | * ... for OTG use as device OR host, initialize "otg" | ||
| 19 | */ | ||
| 20 | unsigned register_host:1; | ||
| 21 | unsigned register_dev:1; | ||
| 22 | u8 otg; /* port number, 1-based: usb1 == 2 */ | ||
| 23 | |||
| 24 | u8 hmc_mode; | ||
| 25 | |||
| 26 | /* implicitly true if otg: host supports remote wakeup? */ | ||
| 27 | u8 rwc; | ||
| 28 | |||
| 29 | /* signaling pins used to talk to transceiver on usbN: | ||
| 30 | * 0 == usbN unused | ||
| 31 | * 2 == usb0-only, using internal transceiver | ||
| 32 | * 3 == 3 wire bidirectional | ||
| 33 | * 4 == 4 wire bidirectional | ||
| 34 | * 6 == 6 wire unidirectional (or TLL) | ||
| 35 | */ | ||
| 36 | u8 pins[3]; | ||
| 37 | |||
| 38 | struct platform_device *udc_device; | ||
| 39 | struct platform_device *ohci_device; | ||
| 40 | struct platform_device *otg_device; | ||
| 41 | |||
| 42 | u32 (*usb0_init)(unsigned nwires, unsigned is_device); | ||
| 43 | u32 (*usb1_init)(unsigned nwires); | ||
| 44 | u32 (*usb2_init)(unsigned nwires, unsigned alt_pingroup); | ||
| 45 | |||
| 46 | int (*ocpi_enable)(void); | ||
| 47 | }; | ||
| 48 | |||
| 49 | void omap_otg_init(struct omap_usb_config *config); | ||
| 50 | |||
| 51 | #if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE) | ||
| 52 | void omap1_usb_init(struct omap_usb_config *pdata); | ||
| 53 | #else | ||
| 54 | static inline void omap1_usb_init(struct omap_usb_config *pdata) | ||
| 55 | { | ||
| 56 | } | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #define OMAP1_OTG_BASE 0xfffb0400 | ||
| 60 | #define OMAP1_UDC_BASE 0xfffb4000 | ||
| 61 | #define OMAP1_OHCI_BASE 0xfffba000 | ||
| 62 | |||
| 63 | #define OMAP2_OHCI_BASE 0x4805e000 | ||
| 64 | #define OMAP2_UDC_BASE 0x4805e200 | ||
| 65 | #define OMAP2_OTG_BASE 0x4805e300 | ||
| 66 | #define OTG_BASE OMAP1_OTG_BASE | ||
| 67 | #define UDC_BASE OMAP1_UDC_BASE | ||
| 68 | #define OMAP_OHCI_BASE OMAP1_OHCI_BASE | ||
| 69 | |||
| 70 | /* | ||
| 71 | * OTG and transceiver registers, for OMAPs starting with ARM926 | ||
| 72 | */ | ||
| 73 | #define OTG_REV (OTG_BASE + 0x00) | ||
| 74 | #define OTG_SYSCON_1 (OTG_BASE + 0x04) | ||
| 75 | # define USB2_TRX_MODE(w) (((w)>>24)&0x07) | ||
| 76 | # define USB1_TRX_MODE(w) (((w)>>20)&0x07) | ||
| 77 | # define USB0_TRX_MODE(w) (((w)>>16)&0x07) | ||
| 78 | # define OTG_IDLE_EN (1 << 15) | ||
| 79 | # define HST_IDLE_EN (1 << 14) | ||
| 80 | # define DEV_IDLE_EN (1 << 13) | ||
| 81 | # define OTG_RESET_DONE (1 << 2) | ||
| 82 | # define OTG_SOFT_RESET (1 << 1) | ||
| 83 | #define OTG_SYSCON_2 (OTG_BASE + 0x08) | ||
| 84 | # define OTG_EN (1 << 31) | ||
| 85 | # define USBX_SYNCHRO (1 << 30) | ||
| 86 | # define OTG_MST16 (1 << 29) | ||
| 87 | # define SRP_GPDATA (1 << 28) | ||
| 88 | # define SRP_GPDVBUS (1 << 27) | ||
| 89 | # define SRP_GPUVBUS(w) (((w)>>24)&0x07) | ||
| 90 | # define A_WAIT_VRISE(w) (((w)>>20)&0x07) | ||
| 91 | # define B_ASE_BRST(w) (((w)>>16)&0x07) | ||
| 92 | # define SRP_DPW (1 << 14) | ||
| 93 | # define SRP_DATA (1 << 13) | ||
| 94 | # define SRP_VBUS (1 << 12) | ||
| 95 | # define OTG_PADEN (1 << 10) | ||
| 96 | # define HMC_PADEN (1 << 9) | ||
| 97 | # define UHOST_EN (1 << 8) | ||
| 98 | # define HMC_TLLSPEED (1 << 7) | ||
| 99 | # define HMC_TLLATTACH (1 << 6) | ||
| 100 | # define OTG_HMC(w) (((w)>>0)&0x3f) | ||
| 101 | #define OTG_CTRL (OTG_BASE + 0x0c) | ||
| 102 | # define OTG_USB2_EN (1 << 29) | ||
| 103 | # define OTG_USB2_DP (1 << 28) | ||
| 104 | # define OTG_USB2_DM (1 << 27) | ||
| 105 | # define OTG_USB1_EN (1 << 26) | ||
| 106 | # define OTG_USB1_DP (1 << 25) | ||
| 107 | # define OTG_USB1_DM (1 << 24) | ||
| 108 | # define OTG_USB0_EN (1 << 23) | ||
| 109 | # define OTG_USB0_DP (1 << 22) | ||
| 110 | # define OTG_USB0_DM (1 << 21) | ||
| 111 | # define OTG_ASESSVLD (1 << 20) | ||
| 112 | # define OTG_BSESSEND (1 << 19) | ||
| 113 | # define OTG_BSESSVLD (1 << 18) | ||
| 114 | # define OTG_VBUSVLD (1 << 17) | ||
| 115 | # define OTG_ID (1 << 16) | ||
| 116 | # define OTG_DRIVER_SEL (1 << 15) | ||
| 117 | # define OTG_A_SETB_HNPEN (1 << 12) | ||
| 118 | # define OTG_A_BUSREQ (1 << 11) | ||
| 119 | # define OTG_B_HNPEN (1 << 9) | ||
| 120 | # define OTG_B_BUSREQ (1 << 8) | ||
| 121 | # define OTG_BUSDROP (1 << 7) | ||
| 122 | # define OTG_PULLDOWN (1 << 5) | ||
| 123 | # define OTG_PULLUP (1 << 4) | ||
| 124 | # define OTG_DRV_VBUS (1 << 3) | ||
| 125 | # define OTG_PD_VBUS (1 << 2) | ||
| 126 | # define OTG_PU_VBUS (1 << 1) | ||
| 127 | # define OTG_PU_ID (1 << 0) | ||
| 128 | #define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */ | ||
| 129 | # define DRIVER_SWITCH (1 << 15) | ||
| 130 | # define A_VBUS_ERR (1 << 13) | ||
| 131 | # define A_REQ_TMROUT (1 << 12) | ||
| 132 | # define A_SRP_DETECT (1 << 11) | ||
| 133 | # define B_HNP_FAIL (1 << 10) | ||
| 134 | # define B_SRP_TMROUT (1 << 9) | ||
| 135 | # define B_SRP_DONE (1 << 8) | ||
| 136 | # define B_SRP_STARTED (1 << 7) | ||
| 137 | # define OPRT_CHG (1 << 0) | ||
| 138 | #define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */ | ||
| 139 | // same bits as in IRQ_EN | ||
| 140 | #define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */ | ||
| 141 | # define OTGVPD (1 << 14) | ||
| 142 | # define OTGVPU (1 << 13) | ||
| 143 | # define OTGPUID (1 << 12) | ||
| 144 | # define USB2VDR (1 << 10) | ||
| 145 | # define USB2PDEN (1 << 9) | ||
| 146 | # define USB2PUEN (1 << 8) | ||
| 147 | # define USB1VDR (1 << 6) | ||
| 148 | # define USB1PDEN (1 << 5) | ||
| 149 | # define USB1PUEN (1 << 4) | ||
| 150 | # define USB0VDR (1 << 2) | ||
| 151 | # define USB0PDEN (1 << 1) | ||
| 152 | # define USB0PUEN (1 << 0) | ||
| 153 | #define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */ | ||
| 154 | #define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */ | ||
| 155 | |||
| 156 | /*-------------------------------------------------------------------------*/ | ||
| 157 | |||
| 158 | /* OMAP1 */ | ||
| 159 | #define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064) | ||
| 160 | # define CONF_USB2_UNI_R (1 << 8) | ||
| 161 | # define CONF_USB1_UNI_R (1 << 7) | ||
| 162 | # define CONF_USB_PORT0_R(x) (((x)>>4)&0x7) | ||
| 163 | # define CONF_USB0_ISOLATE_R (1 << 3) | ||
| 164 | # define CONF_USB_PWRDN_DM_R (1 << 2) | ||
| 165 | # define CONF_USB_PWRDN_DP_R (1 << 1) | ||
diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c index e61afd922766..65f88176fba8 100644 --- a/arch/arm/mach-omap1/usb.c +++ b/arch/arm/mach-omap1/usb.c | |||
| @@ -27,7 +27,8 @@ | |||
| 27 | #include <asm/irq.h> | 27 | #include <asm/irq.h> |
| 28 | 28 | ||
| 29 | #include <plat/mux.h> | 29 | #include <plat/mux.h> |
| 30 | #include <plat/usb.h> | 30 | |
| 31 | #include <mach/usb.h> | ||
| 31 | 32 | ||
| 32 | #include "common.h" | 33 | #include "common.h" |
| 33 | 34 | ||
| @@ -55,6 +56,119 @@ | |||
| 55 | #define INT_USB_IRQ_HGEN INT_USB_HHC_1 | 56 | #define INT_USB_IRQ_HGEN INT_USB_HHC_1 |
| 56 | #define INT_USB_IRQ_OTG IH2_BASE + 8 | 57 | #define INT_USB_IRQ_OTG IH2_BASE + 8 |
| 57 | 58 | ||
| 59 | #ifdef CONFIG_ARCH_OMAP_OTG | ||
| 60 | |||
| 61 | void __init | ||
| 62 | omap_otg_init(struct omap_usb_config *config) | ||
| 63 | { | ||
| 64 | u32 syscon; | ||
| 65 | int alt_pingroup = 0; | ||
| 66 | |||
| 67 | /* NOTE: no bus or clock setup (yet?) */ | ||
| 68 | |||
| 69 | syscon = omap_readl(OTG_SYSCON_1) & 0xffff; | ||
| 70 | if (!(syscon & OTG_RESET_DONE)) | ||
| 71 | pr_debug("USB resets not complete?\n"); | ||
| 72 | |||
| 73 | //omap_writew(0, OTG_IRQ_EN); | ||
| 74 | |||
| 75 | /* pin muxing and transceiver pinouts */ | ||
| 76 | if (config->pins[0] > 2) /* alt pingroup 2 */ | ||
| 77 | alt_pingroup = 1; | ||
| 78 | syscon |= config->usb0_init(config->pins[0], is_usb0_device(config)); | ||
| 79 | syscon |= config->usb1_init(config->pins[1]); | ||
| 80 | syscon |= config->usb2_init(config->pins[2], alt_pingroup); | ||
| 81 | pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1)); | ||
| 82 | omap_writel(syscon, OTG_SYSCON_1); | ||
| 83 | |||
| 84 | syscon = config->hmc_mode; | ||
| 85 | syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */; | ||
| 86 | #ifdef CONFIG_USB_OTG | ||
| 87 | if (config->otg) | ||
| 88 | syscon |= OTG_EN; | ||
| 89 | #endif | ||
| 90 | if (cpu_class_is_omap1()) | ||
| 91 | pr_debug("USB_TRANSCEIVER_CTRL = %03x\n", | ||
| 92 | omap_readl(USB_TRANSCEIVER_CTRL)); | ||
| 93 | pr_debug("OTG_SYSCON_2 = %08x\n", omap_readl(OTG_SYSCON_2)); | ||
| 94 | omap_writel(syscon, OTG_SYSCON_2); | ||
| 95 | |||
| 96 | printk("USB: hmc %d", config->hmc_mode); | ||
| 97 | if (!alt_pingroup) | ||
| 98 | printk(", usb2 alt %d wires", config->pins[2]); | ||
| 99 | else if (config->pins[0]) | ||
| 100 | printk(", usb0 %d wires%s", config->pins[0], | ||
| 101 | is_usb0_device(config) ? " (dev)" : ""); | ||
| 102 | if (config->pins[1]) | ||
| 103 | printk(", usb1 %d wires", config->pins[1]); | ||
| 104 | if (!alt_pingroup && config->pins[2]) | ||
| 105 | printk(", usb2 %d wires", config->pins[2]); | ||
| 106 | if (config->otg) | ||
| 107 | printk(", Mini-AB on usb%d", config->otg - 1); | ||
| 108 | printk("\n"); | ||
| 109 | |||
| 110 | if (cpu_class_is_omap1()) { | ||
| 111 | u16 w; | ||
| 112 | |||
| 113 | /* leave USB clocks/controllers off until needed */ | ||
| 114 | w = omap_readw(ULPD_SOFT_REQ); | ||
| 115 | w &= ~SOFT_USB_CLK_REQ; | ||
| 116 | omap_writew(w, ULPD_SOFT_REQ); | ||
| 117 | |||
| 118 | w = omap_readw(ULPD_CLOCK_CTRL); | ||
| 119 | w &= ~USB_MCLK_EN; | ||
| 120 | w |= DIS_USB_PVCI_CLK; | ||
| 121 | omap_writew(w, ULPD_CLOCK_CTRL); | ||
| 122 | } | ||
| 123 | syscon = omap_readl(OTG_SYSCON_1); | ||
| 124 | syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN; | ||
| 125 | |||
| 126 | #ifdef CONFIG_USB_GADGET_OMAP | ||
| 127 | if (config->otg || config->register_dev) { | ||
| 128 | struct platform_device *udc_device = config->udc_device; | ||
| 129 | int status; | ||
| 130 | |||
| 131 | syscon &= ~DEV_IDLE_EN; | ||
| 132 | udc_device->dev.platform_data = config; | ||
| 133 | status = platform_device_register(udc_device); | ||
| 134 | if (status) | ||
| 135 | pr_debug("can't register UDC device, %d\n", status); | ||
| 136 | } | ||
| 137 | #endif | ||
| 138 | |||
| 139 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | ||
| 140 | if (config->otg || config->register_host) { | ||
| 141 | struct platform_device *ohci_device = config->ohci_device; | ||
| 142 | int status; | ||
| 143 | |||
| 144 | syscon &= ~HST_IDLE_EN; | ||
| 145 | ohci_device->dev.platform_data = config; | ||
| 146 | status = platform_device_register(ohci_device); | ||
| 147 | if (status) | ||
| 148 | pr_debug("can't register OHCI device, %d\n", status); | ||
| 149 | } | ||
| 150 | #endif | ||
| 151 | |||
| 152 | #ifdef CONFIG_USB_OTG | ||
| 153 | if (config->otg) { | ||
| 154 | struct platform_device *otg_device = config->otg_device; | ||
| 155 | int status; | ||
| 156 | |||
| 157 | syscon &= ~OTG_IDLE_EN; | ||
| 158 | otg_device->dev.platform_data = config; | ||
| 159 | status = platform_device_register(otg_device); | ||
| 160 | if (status) | ||
| 161 | pr_debug("can't register OTG device, %d\n", status); | ||
| 162 | } | ||
| 163 | #endif | ||
| 164 | pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1)); | ||
| 165 | omap_writel(syscon, OTG_SYSCON_1); | ||
| 166 | } | ||
| 167 | |||
| 168 | #else | ||
| 169 | void omap_otg_init(struct omap_usb_config *config) {} | ||
| 170 | #endif | ||
| 171 | |||
| 58 | #ifdef CONFIG_USB_GADGET_OMAP | 172 | #ifdef CONFIG_USB_GADGET_OMAP |
| 59 | 173 | ||
| 60 | static struct resource udc_resources[] = { | 174 | static struct resource udc_resources[] = { |
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 4cf5142f22cc..184469517f15 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig | |||
| @@ -35,6 +35,7 @@ config ARCH_OMAP3 | |||
| 35 | select CPU_V7 | 35 | select CPU_V7 |
| 36 | select USB_ARCH_HAS_EHCI if USB_SUPPORT | 36 | select USB_ARCH_HAS_EHCI if USB_SUPPORT |
| 37 | select ARCH_HAS_OPP | 37 | select ARCH_HAS_OPP |
| 38 | select PM_RUNTIME if CPU_IDLE | ||
| 38 | select PM_OPP if PM | 39 | select PM_OPP if PM |
| 39 | select ARM_CPU_SUSPEND if PM | 40 | select ARM_CPU_SUSPEND if PM |
| 40 | select MULTI_IRQ_HANDLER | 41 | select MULTI_IRQ_HANDLER |
| @@ -52,6 +53,7 @@ config ARCH_OMAP4 | |||
| 52 | select PL310_ERRATA_727915 | 53 | select PL310_ERRATA_727915 |
| 53 | select ARM_ERRATA_720789 | 54 | select ARM_ERRATA_720789 |
| 54 | select ARCH_HAS_OPP | 55 | select ARCH_HAS_OPP |
| 56 | select PM_RUNTIME if CPU_IDLE | ||
| 55 | select PM_OPP if PM | 57 | select PM_OPP if PM |
| 56 | select USB_ARCH_HAS_EHCI if USB_SUPPORT | 58 | select USB_ARCH_HAS_EHCI if USB_SUPPORT |
| 57 | select ARM_CPU_SUSPEND if PM | 59 | select ARM_CPU_SUSPEND if PM |
| @@ -64,19 +66,16 @@ config SOC_OMAP2420 | |||
| 64 | depends on ARCH_OMAP2 | 66 | depends on ARCH_OMAP2 |
| 65 | default y | 67 | default y |
| 66 | select OMAP_DM_TIMER | 68 | select OMAP_DM_TIMER |
| 67 | select ARCH_OMAP_OTG | ||
| 68 | 69 | ||
| 69 | config SOC_OMAP2430 | 70 | config SOC_OMAP2430 |
| 70 | bool "OMAP2430 support" | 71 | bool "OMAP2430 support" |
| 71 | depends on ARCH_OMAP2 | 72 | depends on ARCH_OMAP2 |
| 72 | default y | 73 | default y |
| 73 | select ARCH_OMAP_OTG | ||
| 74 | 74 | ||
| 75 | config SOC_OMAP3430 | 75 | config SOC_OMAP3430 |
| 76 | bool "OMAP3430 support" | 76 | bool "OMAP3430 support" |
| 77 | depends on ARCH_OMAP3 | 77 | depends on ARCH_OMAP3 |
| 78 | default y | 78 | default y |
| 79 | select ARCH_OMAP_OTG | ||
| 80 | 79 | ||
| 81 | config SOC_TI81XX | 80 | config SOC_TI81XX |
| 82 | bool "TI81XX support" | 81 | bool "TI81XX support" |
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index fa742f3c2629..821794fd03d6 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile | |||
| @@ -66,9 +66,7 @@ ifeq ($(CONFIG_PM),y) | |||
| 66 | obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o | 66 | obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o |
| 67 | obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o | 67 | obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o |
| 68 | obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o | 68 | obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o |
| 69 | obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o | ||
| 70 | obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o | 69 | obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o |
| 71 | obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o | ||
| 72 | obj-$(CONFIG_PM_DEBUG) += pm-debug.o | 70 | obj-$(CONFIG_PM_DEBUG) += pm-debug.o |
| 73 | obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o | 71 | obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o |
| 74 | obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3) += smartreflex-class3.o | 72 | obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3) += smartreflex-class3.o |
| @@ -82,6 +80,11 @@ endif | |||
| 82 | 80 | ||
| 83 | endif | 81 | endif |
| 84 | 82 | ||
| 83 | ifeq ($(CONFIG_CPU_IDLE),y) | ||
| 84 | obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o | ||
| 85 | obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o | ||
| 86 | endif | ||
| 87 | |||
| 85 | # PRCM | 88 | # PRCM |
| 86 | obj-y += prm_common.o | 89 | obj-y += prm_common.o |
| 87 | obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o | 90 | obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o |
| @@ -90,6 +93,7 @@ obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o | |||
| 90 | obj-$(CONFIG_ARCH_OMAP4) += prcm.o cminst44xx.o cm44xx.o | 93 | obj-$(CONFIG_ARCH_OMAP4) += prcm.o cminst44xx.o cm44xx.o |
| 91 | obj-$(CONFIG_ARCH_OMAP4) += prcm_mpu44xx.o prminst44xx.o | 94 | obj-$(CONFIG_ARCH_OMAP4) += prcm_mpu44xx.o prminst44xx.o |
| 92 | obj-$(CONFIG_ARCH_OMAP4) += vc44xx_data.o vp44xx_data.o prm44xx.o | 95 | obj-$(CONFIG_ARCH_OMAP4) += vc44xx_data.o vp44xx_data.o prm44xx.o |
| 96 | obj-$(CONFIG_SOC_AM33XX) += prcm.o prm33xx.o cm33xx.o | ||
| 93 | 97 | ||
| 94 | # OMAP voltage domains | 98 | # OMAP voltage domains |
| 95 | voltagedomain-common := voltage.o vc.o vp.o | 99 | voltagedomain-common := voltage.o vc.o vp.o |
| @@ -99,6 +103,7 @@ obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common) | |||
| 99 | obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o | 103 | obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o |
| 100 | obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) | 104 | obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) |
| 101 | obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o | 105 | obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o |
| 106 | obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o | ||
| 102 | 107 | ||
| 103 | # OMAP powerdomain framework | 108 | # OMAP powerdomain framework |
| 104 | powerdomain-common += powerdomain.o powerdomain-common.o | 109 | powerdomain-common += powerdomain.o powerdomain-common.o |
| @@ -113,10 +118,11 @@ obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o | |||
| 113 | obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) | 118 | obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) |
| 114 | obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o | 119 | obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o |
| 115 | obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o | 120 | obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o |
| 121 | obj-$(CONFIG_SOC_AM33XX) += powerdomain33xx.o | ||
| 122 | obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o | ||
| 116 | 123 | ||
| 117 | # PRCM clockdomain control | 124 | # PRCM clockdomain control |
| 118 | clockdomain-common += clockdomain.o | 125 | clockdomain-common += clockdomain.o |
| 119 | clockdomain-common += clockdomains_common_data.o | ||
| 120 | obj-$(CONFIG_ARCH_OMAP2) += $(clockdomain-common) | 126 | obj-$(CONFIG_ARCH_OMAP2) += $(clockdomain-common) |
| 121 | obj-$(CONFIG_ARCH_OMAP2) += clockdomain2xxx_3xxx.o | 127 | obj-$(CONFIG_ARCH_OMAP2) += clockdomain2xxx_3xxx.o |
| 122 | obj-$(CONFIG_ARCH_OMAP2) += clockdomains2xxx_3xxx_data.o | 128 | obj-$(CONFIG_ARCH_OMAP2) += clockdomains2xxx_3xxx_data.o |
| @@ -129,6 +135,8 @@ obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o | |||
| 129 | obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common) | 135 | obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common) |
| 130 | obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o | 136 | obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o |
| 131 | obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o | 137 | obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o |
| 138 | obj-$(CONFIG_SOC_AM33XX) += clockdomain33xx.o | ||
| 139 | obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o | ||
| 132 | 140 | ||
| 133 | # Clock framework | 141 | # Clock framework |
| 134 | obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o | 142 | obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o |
| @@ -244,9 +252,6 @@ obj-y += $(omap-flash-y) $(omap-flash-m) | |||
| 244 | omap-hsmmc-$(CONFIG_MMC_OMAP_HS) := hsmmc.o | 252 | omap-hsmmc-$(CONFIG_MMC_OMAP_HS) := hsmmc.o |
| 245 | obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y) | 253 | obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y) |
| 246 | 254 | ||
| 247 | |||
| 248 | usbfs-$(CONFIG_ARCH_OMAP_OTG) := usb-fs.o | ||
| 249 | obj-y += $(usbfs-m) $(usbfs-y) | ||
| 250 | obj-y += usb-musb.o | 255 | obj-y += usb-musb.o |
| 251 | obj-y += omap_phy_internal.o | 256 | obj-y += omap_phy_internal.o |
| 252 | 257 | ||
diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c index 447682c4e11c..2c90ac686686 100644 --- a/arch/arm/mach-omap2/am35xx-emac.c +++ b/arch/arm/mach-omap2/am35xx-emac.c | |||
| @@ -15,27 +15,13 @@ | |||
| 15 | * General Public License for more details. | 15 | * General Public License for more details. |
| 16 | */ | 16 | */ |
| 17 | 17 | ||
| 18 | #include <linux/clk.h> | 18 | #include <linux/err.h> |
| 19 | #include <linux/davinci_emac.h> | 19 | #include <linux/davinci_emac.h> |
| 20 | #include <linux/platform_device.h> | 20 | #include <asm/system.h> |
| 21 | #include <plat/irqs.h> | 21 | #include <plat/omap_device.h> |
| 22 | #include <mach/am35xx.h> | 22 | #include <mach/am35xx.h> |
| 23 | |||
| 24 | #include "control.h" | 23 | #include "control.h" |
| 25 | 24 | #include "am35xx-emac.h" | |
| 26 | static struct mdio_platform_data am35xx_emac_mdio_pdata; | ||
| 27 | |||
| 28 | static struct resource am35xx_emac_mdio_resources[] = { | ||
| 29 | DEFINE_RES_MEM(AM35XX_IPSS_EMAC_BASE + AM35XX_EMAC_MDIO_OFFSET, SZ_4K), | ||
| 30 | }; | ||
| 31 | |||
| 32 | static struct platform_device am35xx_emac_mdio_device = { | ||
| 33 | .name = "davinci_mdio", | ||
| 34 | .id = 0, | ||
| 35 | .num_resources = ARRAY_SIZE(am35xx_emac_mdio_resources), | ||
| 36 | .resource = am35xx_emac_mdio_resources, | ||
| 37 | .dev.platform_data = &am35xx_emac_mdio_pdata, | ||
| 38 | }; | ||
| 39 | 25 | ||
| 40 | static void am35xx_enable_emac_int(void) | 26 | static void am35xx_enable_emac_int(void) |
| 41 | { | 27 | { |
| @@ -69,41 +55,57 @@ static struct emac_platform_data am35xx_emac_pdata = { | |||
| 69 | .interrupt_disable = am35xx_disable_emac_int, | 55 | .interrupt_disable = am35xx_disable_emac_int, |
| 70 | }; | 56 | }; |
| 71 | 57 | ||
| 72 | static struct resource am35xx_emac_resources[] = { | 58 | static struct mdio_platform_data am35xx_mdio_pdata; |
| 73 | DEFINE_RES_MEM(AM35XX_IPSS_EMAC_BASE, 0x30000), | ||
| 74 | DEFINE_RES_IRQ(INT_35XX_EMAC_C0_RXTHRESH_IRQ), | ||
| 75 | DEFINE_RES_IRQ(INT_35XX_EMAC_C0_RX_PULSE_IRQ), | ||
| 76 | DEFINE_RES_IRQ(INT_35XX_EMAC_C0_TX_PULSE_IRQ), | ||
| 77 | DEFINE_RES_IRQ(INT_35XX_EMAC_C0_MISC_PULSE_IRQ), | ||
| 78 | }; | ||
| 79 | 59 | ||
| 80 | static struct platform_device am35xx_emac_device = { | 60 | static int __init omap_davinci_emac_dev_init(struct omap_hwmod *oh, |
| 81 | .name = "davinci_emac", | 61 | void *pdata, int pdata_len) |
| 82 | .id = -1, | 62 | { |
| 83 | .num_resources = ARRAY_SIZE(am35xx_emac_resources), | 63 | struct platform_device *pdev; |
| 84 | .resource = am35xx_emac_resources, | 64 | |
| 85 | .dev = { | 65 | pdev = omap_device_build(oh->class->name, 0, oh, pdata, pdata_len, |
| 86 | .platform_data = &am35xx_emac_pdata, | 66 | NULL, 0, false); |
| 87 | }, | 67 | if (IS_ERR(pdev)) { |
| 88 | }; | 68 | WARN(1, "Can't build omap_device for %s:%s.\n", |
| 69 | oh->class->name, oh->name); | ||
| 70 | return PTR_ERR(pdev); | ||
| 71 | } | ||
| 72 | |||
| 73 | return 0; | ||
| 74 | } | ||
| 89 | 75 | ||
| 90 | void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en) | 76 | void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en) |
| 91 | { | 77 | { |
| 78 | struct omap_hwmod *oh; | ||
| 92 | u32 v; | 79 | u32 v; |
| 93 | int err; | 80 | int ret; |
| 94 | 81 | ||
| 95 | am35xx_emac_pdata.rmii_en = rmii_en; | 82 | oh = omap_hwmod_lookup("davinci_mdio"); |
| 96 | am35xx_emac_mdio_pdata.bus_freq = mdio_bus_freq; | 83 | if (!oh) { |
| 97 | err = platform_device_register(&am35xx_emac_device); | 84 | pr_err("Could not find davinci_mdio hwmod\n"); |
| 98 | if (err) { | 85 | return; |
| 99 | pr_err("AM35x: failed registering EMAC device: %d\n", err); | 86 | } |
| 87 | |||
| 88 | am35xx_mdio_pdata.bus_freq = mdio_bus_freq; | ||
| 89 | |||
| 90 | ret = omap_davinci_emac_dev_init(oh, &am35xx_mdio_pdata, | ||
| 91 | sizeof(am35xx_mdio_pdata)); | ||
| 92 | if (ret) { | ||
| 93 | pr_err("Could not build davinci_mdio hwmod device\n"); | ||
| 100 | return; | 94 | return; |
| 101 | } | 95 | } |
| 102 | 96 | ||
| 103 | err = platform_device_register(&am35xx_emac_mdio_device); | 97 | oh = omap_hwmod_lookup("davinci_emac"); |
| 104 | if (err) { | 98 | if (!oh) { |
| 105 | pr_err("AM35x: failed registering EMAC MDIO device: %d\n", err); | 99 | pr_err("Could not find davinci_emac hwmod\n"); |
| 106 | platform_device_unregister(&am35xx_emac_device); | 100 | return; |
| 101 | } | ||
| 102 | |||
| 103 | am35xx_emac_pdata.rmii_en = rmii_en; | ||
| 104 | |||
| 105 | ret = omap_davinci_emac_dev_init(oh, &am35xx_emac_pdata, | ||
| 106 | sizeof(am35xx_emac_pdata)); | ||
| 107 | if (ret) { | ||
| 108 | pr_err("Could not build davinci_emac hwmod device\n"); | ||
| 107 | return; | 109 | return; |
| 108 | } | 110 | } |
| 109 | 111 | ||
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index 99ca6bad5c30..9511584fdc4f 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c | |||
| @@ -218,9 +218,6 @@ static struct twl4030_gpio_platform_data sdp2430_gpio_data = { | |||
| 218 | }; | 218 | }; |
| 219 | 219 | ||
| 220 | static struct twl4030_platform_data sdp2430_twldata = { | 220 | static struct twl4030_platform_data sdp2430_twldata = { |
| 221 | .irq_base = TWL4030_IRQ_BASE, | ||
| 222 | .irq_end = TWL4030_IRQ_END, | ||
| 223 | |||
| 224 | /* platform_data for children goes here */ | 221 | /* platform_data for children goes here */ |
| 225 | .gpio = &sdp2430_gpio_data, | 222 | .gpio = &sdp2430_gpio_data, |
| 226 | .vmmc1 = &sdp2430_vmmc1, | 223 | .vmmc1 = &sdp2430_vmmc1, |
| @@ -254,16 +251,6 @@ static struct omap2_hsmmc_info mmc[] __initdata = { | |||
| 254 | {} /* Terminator */ | 251 | {} /* Terminator */ |
| 255 | }; | 252 | }; |
| 256 | 253 | ||
| 257 | static struct omap_usb_config sdp2430_usb_config __initdata = { | ||
| 258 | .otg = 1, | ||
| 259 | #ifdef CONFIG_USB_GADGET_OMAP | ||
| 260 | .hmc_mode = 0x0, | ||
| 261 | #elif defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | ||
| 262 | .hmc_mode = 0x1, | ||
| 263 | #endif | ||
| 264 | .pins[0] = 3, | ||
| 265 | }; | ||
| 266 | |||
| 267 | #ifdef CONFIG_OMAP_MUX | 254 | #ifdef CONFIG_OMAP_MUX |
| 268 | static struct omap_board_mux board_mux[] __initdata = { | 255 | static struct omap_board_mux board_mux[] __initdata = { |
| 269 | { .reg_offset = OMAP_MUX_TERMINATOR }, | 256 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
| @@ -280,7 +267,6 @@ static void __init omap_2430sdp_init(void) | |||
| 280 | omap_serial_init(); | 267 | omap_serial_init(); |
| 281 | omap_sdrc_init(NULL, NULL); | 268 | omap_sdrc_init(NULL, NULL); |
| 282 | omap_hsmmc_init(mmc); | 269 | omap_hsmmc_init(mmc); |
| 283 | omap2_usbfs_init(&sdp2430_usb_config); | ||
| 284 | 270 | ||
| 285 | omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP); | 271 | omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP); |
| 286 | usb_musb_init(NULL); | 272 | usb_musb_init(NULL); |
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index 502c31e123be..519bcd3079e8 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c | |||
| @@ -35,7 +35,6 @@ | |||
| 35 | #include <asm/mach/flash.h> | 35 | #include <asm/mach/flash.h> |
| 36 | 36 | ||
| 37 | #include <plat/led.h> | 37 | #include <plat/led.h> |
| 38 | #include <plat/usb.h> | ||
| 39 | #include <plat/board.h> | 38 | #include <plat/board.h> |
| 40 | #include "common.h" | 39 | #include "common.h" |
| 41 | #include <plat/gpmc.h> | 40 | #include <plat/gpmc.h> |
| @@ -253,13 +252,6 @@ out: | |||
| 253 | clk_put(gpmc_fck); | 252 | clk_put(gpmc_fck); |
| 254 | } | 253 | } |
| 255 | 254 | ||
| 256 | static struct omap_usb_config apollon_usb_config __initdata = { | ||
| 257 | .register_dev = 1, | ||
| 258 | .hmc_mode = 0x14, /* 0:dev 1:host1 2:disable */ | ||
| 259 | |||
| 260 | .pins[0] = 6, | ||
| 261 | }; | ||
| 262 | |||
| 263 | static struct panel_generic_dpi_data apollon_panel_data = { | 255 | static struct panel_generic_dpi_data apollon_panel_data = { |
| 264 | .name = "apollon", | 256 | .name = "apollon", |
| 265 | }; | 257 | }; |
| @@ -297,15 +289,6 @@ static void __init apollon_led_init(void) | |||
| 297 | gpio_request_array(apollon_gpio_leds, ARRAY_SIZE(apollon_gpio_leds)); | 289 | gpio_request_array(apollon_gpio_leds, ARRAY_SIZE(apollon_gpio_leds)); |
| 298 | } | 290 | } |
| 299 | 291 | ||
| 300 | static void __init apollon_usb_init(void) | ||
| 301 | { | ||
| 302 | /* USB device */ | ||
| 303 | /* DEVICE_SUSPEND */ | ||
| 304 | omap_mux_init_signal("mcbsp2_clkx.gpio_12", 0); | ||
| 305 | gpio_request_one(12, GPIOF_OUT_INIT_LOW, "USB suspend"); | ||
| 306 | omap2_usbfs_init(&apollon_usb_config); | ||
| 307 | } | ||
| 308 | |||
| 309 | #ifdef CONFIG_OMAP_MUX | 292 | #ifdef CONFIG_OMAP_MUX |
| 310 | static struct omap_board_mux board_mux[] __initdata = { | 293 | static struct omap_board_mux board_mux[] __initdata = { |
| 311 | { .reg_offset = OMAP_MUX_TERMINATOR }, | 294 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
| @@ -321,7 +304,6 @@ static void __init omap_apollon_init(void) | |||
| 321 | apollon_init_smc91x(); | 304 | apollon_init_smc91x(); |
| 322 | apollon_led_init(); | 305 | apollon_led_init(); |
| 323 | apollon_flash_init(); | 306 | apollon_flash_init(); |
| 324 | apollon_usb_init(); | ||
| 325 | 307 | ||
| 326 | /* REVISIT: where's the correct place */ | 308 | /* REVISIT: where's the correct place */ |
| 327 | omap_mux_init_signal("sys_nirq", OMAP_PULL_ENA | OMAP_PULL_UP); | 309 | omap_mux_init_signal("sys_nirq", OMAP_PULL_ENA | OMAP_PULL_UP); |
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 202934657867..2f2abfb82d84 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c | |||
| @@ -112,6 +112,24 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)") | |||
| 112 | MACHINE_END | 112 | MACHINE_END |
| 113 | #endif | 113 | #endif |
| 114 | 114 | ||
| 115 | #ifdef CONFIG_SOC_AM33XX | ||
| 116 | static const char *am33xx_boards_compat[] __initdata = { | ||
| 117 | "ti,am33xx", | ||
| 118 | NULL, | ||
| 119 | }; | ||
| 120 | |||
| 121 | DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)") | ||
| 122 | .reserve = omap_reserve, | ||
| 123 | .map_io = am33xx_map_io, | ||
| 124 | .init_early = am33xx_init_early, | ||
| 125 | .init_irq = omap_init_irq, | ||
| 126 | .handle_irq = omap3_intc_handle_irq, | ||
| 127 | .init_machine = omap_generic_init, | ||
| 128 | .timer = &omap3_am33xx_timer, | ||
| 129 | .dt_compat = am33xx_boards_compat, | ||
| 130 | MACHINE_END | ||
| 131 | #endif | ||
| 132 | |||
| 115 | #ifdef CONFIG_ARCH_OMAP4 | 133 | #ifdef CONFIG_ARCH_OMAP4 |
| 116 | static const char *omap4_boards_compat[] __initdata = { | 134 | static const char *omap4_boards_compat[] __initdata = { |
| 117 | "ti,omap4", | 135 | "ti,omap4", |
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index 876becf8205a..ace20482e3e1 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c | |||
| @@ -32,7 +32,6 @@ | |||
| 32 | #include <asm/mach/arch.h> | 32 | #include <asm/mach/arch.h> |
| 33 | #include <asm/mach/map.h> | 33 | #include <asm/mach/map.h> |
| 34 | 34 | ||
| 35 | #include <plat/usb.h> | ||
| 36 | #include <plat/board.h> | 35 | #include <plat/board.h> |
| 37 | #include "common.h" | 36 | #include "common.h" |
| 38 | #include <plat/menelaus.h> | 37 | #include <plat/menelaus.h> |
| @@ -329,17 +328,6 @@ static void __init h4_init_flash(void) | |||
| 329 | h4_flash_resource.end = base + SZ_64M - 1; | 328 | h4_flash_resource.end = base + SZ_64M - 1; |
| 330 | } | 329 | } |
| 331 | 330 | ||
| 332 | static struct omap_usb_config h4_usb_config __initdata = { | ||
| 333 | /* S1.10 OFF -- usb "download port" | ||
| 334 | * usb0 switched to Mini-B port and isp1105 transceiver; | ||
| 335 | * S2.POS3 = ON, S2.POS4 = OFF ... to enable battery charging | ||
| 336 | */ | ||
| 337 | .register_dev = 1, | ||
| 338 | .pins[0] = 3, | ||
| 339 | /* .hmc_mode = 0x14,*/ /* 0:dev 1:host 2:disable */ | ||
| 340 | .hmc_mode = 0x00, /* 0:dev|otg 1:disable 2:disable */ | ||
| 341 | }; | ||
| 342 | |||
| 343 | static struct at24_platform_data m24c01 = { | 331 | static struct at24_platform_data m24c01 = { |
| 344 | .byte_len = SZ_1K / 8, | 332 | .byte_len = SZ_1K / 8, |
| 345 | .page_size = 16, | 333 | .page_size = 16, |
| @@ -381,7 +369,6 @@ static void __init omap_h4_init(void) | |||
| 381 | ARRAY_SIZE(h4_i2c_board_info)); | 369 | ARRAY_SIZE(h4_i2c_board_info)); |
| 382 | 370 | ||
| 383 | platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices)); | 371 | platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices)); |
| 384 | omap2_usbfs_init(&h4_usb_config); | ||
| 385 | omap_serial_init(); | 372 | omap_serial_init(); |
| 386 | omap_sdrc_init(NULL, NULL); | 373 | omap_sdrc_init(NULL, NULL); |
| 387 | h4_init_flash(); | 374 | h4_init_flash(); |
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 580fd17208da..6202fc76e490 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c | |||
| @@ -433,7 +433,7 @@ static struct platform_device *omap3_beagle_devices[] __initdata = { | |||
| 433 | 433 | ||
| 434 | static const struct usbhs_omap_board_data usbhs_bdata __initconst = { | 434 | static const struct usbhs_omap_board_data usbhs_bdata __initconst = { |
| 435 | 435 | ||
| 436 | .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, | 436 | .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, |
| 437 | .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, | 437 | .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, |
| 438 | .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, | 438 | .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, |
| 439 | 439 | ||
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c index 932e1778aff9..fca93d1afd43 100644 --- a/arch/arm/mach-omap2/board-omap3logic.c +++ b/arch/arm/mach-omap2/board-omap3logic.c | |||
| @@ -93,9 +93,6 @@ static struct twl4030_usb_data omap3logic_usb_data = { | |||
| 93 | 93 | ||
| 94 | 94 | ||
| 95 | static struct twl4030_platform_data omap3logic_twldata = { | 95 | static struct twl4030_platform_data omap3logic_twldata = { |
| 96 | .irq_base = TWL4030_IRQ_BASE, | ||
| 97 | .irq_end = TWL4030_IRQ_END, | ||
| 98 | |||
| 99 | /* platform_data for children goes here */ | 96 | /* platform_data for children goes here */ |
| 100 | .gpio = &omap3logic_gpio_data, | 97 | .gpio = &omap3logic_gpio_data, |
| 101 | .vmmc1 = &omap3logic_vmmc1, | 98 | .vmmc1 = &omap3logic_vmmc1, |
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index bace9308a4db..7e39015357b1 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c | |||
| @@ -1774,8 +1774,6 @@ static struct omap_clk omap2420_clks[] = { | |||
| 1774 | CLK(NULL, "osc_ck", &osc_ck, CK_242X), | 1774 | CLK(NULL, "osc_ck", &osc_ck, CK_242X), |
| 1775 | CLK(NULL, "sys_ck", &sys_ck, CK_242X), | 1775 | CLK(NULL, "sys_ck", &sys_ck, CK_242X), |
| 1776 | CLK(NULL, "alt_ck", &alt_ck, CK_242X), | 1776 | CLK(NULL, "alt_ck", &alt_ck, CK_242X), |
| 1777 | CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_242X), | ||
| 1778 | CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_242X), | ||
| 1779 | CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X), | 1777 | CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X), |
| 1780 | /* internal analog sources */ | 1778 | /* internal analog sources */ |
| 1781 | CLK(NULL, "dpll_ck", &dpll_ck, CK_242X), | 1779 | CLK(NULL, "dpll_ck", &dpll_ck, CK_242X), |
| @@ -1784,8 +1782,6 @@ static struct omap_clk omap2420_clks[] = { | |||
| 1784 | /* internal prcm root sources */ | 1782 | /* internal prcm root sources */ |
| 1785 | CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X), | 1783 | CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X), |
| 1786 | CLK(NULL, "core_ck", &core_ck, CK_242X), | 1784 | CLK(NULL, "core_ck", &core_ck, CK_242X), |
| 1787 | CLK("omap-mcbsp.1", "prcm_fck", &func_96m_ck, CK_242X), | ||
| 1788 | CLK("omap-mcbsp.2", "prcm_fck", &func_96m_ck, CK_242X), | ||
| 1789 | CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X), | 1785 | CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X), |
| 1790 | CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X), | 1786 | CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X), |
| 1791 | CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X), | 1787 | CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X), |
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index 3b4d09a50399..90a08c3b12ac 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c | |||
| @@ -1858,11 +1858,6 @@ static struct omap_clk omap2430_clks[] = { | |||
| 1858 | CLK(NULL, "osc_ck", &osc_ck, CK_243X), | 1858 | CLK(NULL, "osc_ck", &osc_ck, CK_243X), |
| 1859 | CLK(NULL, "sys_ck", &sys_ck, CK_243X), | 1859 | CLK(NULL, "sys_ck", &sys_ck, CK_243X), |
| 1860 | CLK(NULL, "alt_ck", &alt_ck, CK_243X), | 1860 | CLK(NULL, "alt_ck", &alt_ck, CK_243X), |
| 1861 | CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_243X), | ||
| 1862 | CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_243X), | ||
| 1863 | CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks, CK_243X), | ||
| 1864 | CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks, CK_243X), | ||
| 1865 | CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks, CK_243X), | ||
| 1866 | CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X), | 1861 | CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X), |
| 1867 | /* internal analog sources */ | 1862 | /* internal analog sources */ |
| 1868 | CLK(NULL, "dpll_ck", &dpll_ck, CK_243X), | 1863 | CLK(NULL, "dpll_ck", &dpll_ck, CK_243X), |
| @@ -1871,11 +1866,6 @@ static struct omap_clk omap2430_clks[] = { | |||
| 1871 | /* internal prcm root sources */ | 1866 | /* internal prcm root sources */ |
| 1872 | CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X), | 1867 | CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X), |
| 1873 | CLK(NULL, "core_ck", &core_ck, CK_243X), | 1868 | CLK(NULL, "core_ck", &core_ck, CK_243X), |
| 1874 | CLK("omap-mcbsp.1", "prcm_fck", &func_96m_ck, CK_243X), | ||
| 1875 | CLK("omap-mcbsp.2", "prcm_fck", &func_96m_ck, CK_243X), | ||
| 1876 | CLK("omap-mcbsp.3", "prcm_fck", &func_96m_ck, CK_243X), | ||
| 1877 | CLK("omap-mcbsp.4", "prcm_fck", &func_96m_ck, CK_243X), | ||
| 1878 | CLK("omap-mcbsp.5", "prcm_fck", &func_96m_ck, CK_243X), | ||
| 1879 | CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X), | 1869 | CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X), |
| 1880 | CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X), | 1870 | CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X), |
| 1881 | CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X), | 1871 | CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X), |
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 1efdec236ae8..049061778a85 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c | |||
| @@ -2490,13 +2490,13 @@ static struct clk uart4_fck = { | |||
| 2490 | }; | 2490 | }; |
| 2491 | 2491 | ||
| 2492 | static struct clk uart4_fck_am35xx = { | 2492 | static struct clk uart4_fck_am35xx = { |
| 2493 | .name = "uart4_fck", | 2493 | .name = "uart4_fck", |
| 2494 | .ops = &clkops_omap2_dflt_wait, | 2494 | .ops = &clkops_omap2_dflt_wait, |
| 2495 | .parent = &per_48m_fck, | 2495 | .parent = &core_48m_fck, |
| 2496 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2496 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2497 | .enable_bit = OMAP3430_EN_UART4_SHIFT, | 2497 | .enable_bit = AM35XX_EN_UART4_SHIFT, |
| 2498 | .clkdm_name = "core_l4_clkdm", | 2498 | .clkdm_name = "core_l4_clkdm", |
| 2499 | .recalc = &followparent_recalc, | 2499 | .recalc = &followparent_recalc, |
| 2500 | }; | 2500 | }; |
| 2501 | 2501 | ||
| 2502 | static struct clk gpt2_fck = { | 2502 | static struct clk gpt2_fck = { |
| @@ -3201,8 +3201,12 @@ static struct clk vpfe_fck = { | |||
| 3201 | }; | 3201 | }; |
| 3202 | 3202 | ||
| 3203 | /* | 3203 | /* |
| 3204 | * The UART1/2 functional clock acts as the functional | 3204 | * The UART1/2 functional clock acts as the functional clock for |
| 3205 | * clock for UART4. No separate fclk control available. | 3205 | * UART4. No separate fclk control available. XXX Well now we have a |
| 3206 | * uart4_fck that is apparently used as the UART4 functional clock, | ||
| 3207 | * but it also seems that uart1_fck or uart2_fck are still needed, at | ||
| 3208 | * least for UART4 softresets to complete. This really needs | ||
| 3209 | * clarification. | ||
| 3206 | */ | 3210 | */ |
| 3207 | static struct clk uart4_ick_am35xx = { | 3211 | static struct clk uart4_ick_am35xx = { |
| 3208 | .name = "uart4_ick", | 3212 | .name = "uart4_ick", |
| @@ -3236,11 +3240,6 @@ static struct omap_clk omap3xxx_clks[] = { | |||
| 3236 | CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX), | 3240 | CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX), |
| 3237 | CLK(NULL, "sys_ck", &sys_ck, CK_3XXX), | 3241 | CLK(NULL, "sys_ck", &sys_ck, CK_3XXX), |
| 3238 | CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX), | 3242 | CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX), |
| 3239 | CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_3XXX), | ||
| 3240 | CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_3XXX), | ||
| 3241 | CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks, CK_3XXX), | ||
| 3242 | CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks, CK_3XXX), | ||
| 3243 | CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks, CK_3XXX), | ||
| 3244 | CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX), | 3243 | CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX), |
| 3245 | CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX), | 3244 | CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX), |
| 3246 | CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX), | 3245 | CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX), |
| @@ -3307,8 +3306,6 @@ static struct omap_clk omap3xxx_clks[] = { | |||
| 3307 | CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | 3306 | CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
| 3308 | CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | 3307 | CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
| 3309 | CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | 3308 | CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
| 3310 | CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX), | ||
| 3311 | CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX), | ||
| 3312 | CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), | 3309 | CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), |
| 3313 | CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | 3310 | CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
| 3314 | CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX), | 3311 | CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX), |
| @@ -3413,9 +3410,6 @@ static struct omap_clk omap3xxx_clks[] = { | |||
| 3413 | CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX), | 3410 | CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX), |
| 3414 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX), | 3411 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX), |
| 3415 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX), | 3412 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX), |
| 3416 | CLK("omap-mcbsp.2", "prcm_fck", &per_96m_fck, CK_3XXX), | ||
| 3417 | CLK("omap-mcbsp.3", "prcm_fck", &per_96m_fck, CK_3XXX), | ||
| 3418 | CLK("omap-mcbsp.4", "prcm_fck", &per_96m_fck, CK_3XXX), | ||
| 3419 | CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX), | 3413 | CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX), |
| 3420 | CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX), | 3414 | CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX), |
| 3421 | CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX), | 3415 | CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX), |
| @@ -3474,12 +3468,12 @@ static struct omap_clk omap3xxx_clks[] = { | |||
| 3474 | CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX), | 3468 | CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX), |
| 3475 | CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX), | 3469 | CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX), |
| 3476 | CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX), | 3470 | CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX), |
| 3477 | CLK("davinci_emac", NULL, &emac_ick, CK_AM35XX), | 3471 | CLK("davinci_emac.0", NULL, &emac_ick, CK_AM35XX), |
| 3478 | CLK("davinci_mdio.0", NULL, &emac_fck, CK_AM35XX), | 3472 | CLK("davinci_mdio.0", NULL, &emac_fck, CK_AM35XX), |
| 3479 | CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX), | 3473 | CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX), |
| 3480 | CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX), | 3474 | CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX), |
| 3481 | CLK("musb-am35x", "ick", &hsotgusb_ick_am35xx, CK_AM35XX), | 3475 | CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx, CK_AM35XX), |
| 3482 | CLK("musb-am35x", "fck", &hsotgusb_fck_am35xx, CK_AM35XX), | 3476 | CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx, CK_AM35XX), |
| 3483 | CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX), | 3477 | CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX), |
| 3484 | CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX), | 3478 | CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX), |
| 3485 | CLK("omap_timer.1", "32k_ck", &omap_32k_fck, CK_3XXX), | 3479 | CLK("omap_timer.1", "32k_ck", &omap_32k_fck, CK_3XXX), |
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index f7b58609bad8..5601dc13785e 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h | |||
| @@ -31,12 +31,16 @@ | |||
| 31 | * | 31 | * |
| 32 | * CLKDM_NO_AUTODEPS: Prevent "autodeps" from being added/removed from this | 32 | * CLKDM_NO_AUTODEPS: Prevent "autodeps" from being added/removed from this |
| 33 | * clockdomain. (Currently, this applies to OMAP3 clockdomains only.) | 33 | * clockdomain. (Currently, this applies to OMAP3 clockdomains only.) |
| 34 | * CLKDM_ACTIVE_WITH_MPU: The PRCM guarantees that this clockdomain is | ||
| 35 | * active whenever the MPU is active. True for interconnects and | ||
| 36 | * the WKUP clockdomains. | ||
| 34 | */ | 37 | */ |
| 35 | #define CLKDM_CAN_FORCE_SLEEP (1 << 0) | 38 | #define CLKDM_CAN_FORCE_SLEEP (1 << 0) |
| 36 | #define CLKDM_CAN_FORCE_WAKEUP (1 << 1) | 39 | #define CLKDM_CAN_FORCE_WAKEUP (1 << 1) |
| 37 | #define CLKDM_CAN_ENABLE_AUTO (1 << 2) | 40 | #define CLKDM_CAN_ENABLE_AUTO (1 << 2) |
| 38 | #define CLKDM_CAN_DISABLE_AUTO (1 << 3) | 41 | #define CLKDM_CAN_DISABLE_AUTO (1 << 3) |
| 39 | #define CLKDM_NO_AUTODEPS (1 << 4) | 42 | #define CLKDM_NO_AUTODEPS (1 << 4) |
| 43 | #define CLKDM_ACTIVE_WITH_MPU (1 << 5) | ||
| 40 | 44 | ||
| 41 | #define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO) | 45 | #define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO) |
| 42 | #define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP) | 46 | #define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP) |
| @@ -195,6 +199,7 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh); | |||
| 195 | extern void __init omap242x_clockdomains_init(void); | 199 | extern void __init omap242x_clockdomains_init(void); |
| 196 | extern void __init omap243x_clockdomains_init(void); | 200 | extern void __init omap243x_clockdomains_init(void); |
| 197 | extern void __init omap3xxx_clockdomains_init(void); | 201 | extern void __init omap3xxx_clockdomains_init(void); |
| 202 | extern void __init am33xx_clockdomains_init(void); | ||
| 198 | extern void __init omap44xx_clockdomains_init(void); | 203 | extern void __init omap44xx_clockdomains_init(void); |
| 199 | extern void _clkdm_add_autodeps(struct clockdomain *clkdm); | 204 | extern void _clkdm_add_autodeps(struct clockdomain *clkdm); |
| 200 | extern void _clkdm_del_autodeps(struct clockdomain *clkdm); | 205 | extern void _clkdm_del_autodeps(struct clockdomain *clkdm); |
| @@ -202,11 +207,10 @@ extern void _clkdm_del_autodeps(struct clockdomain *clkdm); | |||
| 202 | extern struct clkdm_ops omap2_clkdm_operations; | 207 | extern struct clkdm_ops omap2_clkdm_operations; |
| 203 | extern struct clkdm_ops omap3_clkdm_operations; | 208 | extern struct clkdm_ops omap3_clkdm_operations; |
| 204 | extern struct clkdm_ops omap4_clkdm_operations; | 209 | extern struct clkdm_ops omap4_clkdm_operations; |
| 210 | extern struct clkdm_ops am33xx_clkdm_operations; | ||
| 205 | 211 | ||
| 206 | extern struct clkdm_dep gfx_24xx_wkdeps[]; | 212 | extern struct clkdm_dep gfx_24xx_wkdeps[]; |
| 207 | extern struct clkdm_dep dsp_24xx_wkdeps[]; | 213 | extern struct clkdm_dep dsp_24xx_wkdeps[]; |
| 208 | extern struct clockdomain wkup_common_clkdm; | 214 | extern struct clockdomain wkup_common_clkdm; |
| 209 | extern struct clockdomain prm_common_clkdm; | ||
| 210 | extern struct clockdomain cm_common_clkdm; | ||
| 211 | 215 | ||
| 212 | #endif | 216 | #endif |
diff --git a/arch/arm/mach-omap2/clockdomain33xx.c b/arch/arm/mach-omap2/clockdomain33xx.c new file mode 100644 index 000000000000..aca6388fad76 --- /dev/null +++ b/arch/arm/mach-omap2/clockdomain33xx.c | |||
| @@ -0,0 +1,74 @@ | |||
| 1 | /* | ||
| 2 | * AM33XX clockdomain control | ||
| 3 | * | ||
| 4 | * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 5 | * Vaibhav Hiremath <hvaibhav@ti.com> | ||
| 6 | * | ||
| 7 | * Derived from mach-omap2/clockdomain44xx.c written by Rajendra Nayak | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or | ||
| 10 | * modify it under the terms of the GNU General Public License as | ||
| 11 | * published by the Free Software Foundation version 2. | ||
| 12 | * | ||
| 13 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
| 14 | * kind, whether express or implied; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/kernel.h> | ||
| 20 | |||
| 21 | #include "clockdomain.h" | ||
| 22 | #include "cm33xx.h" | ||
| 23 | |||
| 24 | |||
| 25 | static int am33xx_clkdm_sleep(struct clockdomain *clkdm) | ||
| 26 | { | ||
| 27 | am33xx_cm_clkdm_force_sleep(clkdm->cm_inst, clkdm->clkdm_offs); | ||
| 28 | return 0; | ||
| 29 | } | ||
| 30 | |||
| 31 | static int am33xx_clkdm_wakeup(struct clockdomain *clkdm) | ||
| 32 | { | ||
| 33 | am33xx_cm_clkdm_force_wakeup(clkdm->cm_inst, clkdm->clkdm_offs); | ||
| 34 | return 0; | ||
| 35 | } | ||
| 36 | |||
| 37 | static void am33xx_clkdm_allow_idle(struct clockdomain *clkdm) | ||
| 38 | { | ||
| 39 | am33xx_cm_clkdm_enable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs); | ||
| 40 | } | ||
| 41 | |||
| 42 | static void am33xx_clkdm_deny_idle(struct clockdomain *clkdm) | ||
| 43 | { | ||
| 44 | am33xx_cm_clkdm_disable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs); | ||
| 45 | } | ||
| 46 | |||
| 47 | static int am33xx_clkdm_clk_enable(struct clockdomain *clkdm) | ||
| 48 | { | ||
| 49 | if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) | ||
| 50 | return am33xx_clkdm_wakeup(clkdm); | ||
| 51 | |||
| 52 | return 0; | ||
| 53 | } | ||
| 54 | |||
| 55 | static int am33xx_clkdm_clk_disable(struct clockdomain *clkdm) | ||
| 56 | { | ||
| 57 | bool hwsup = false; | ||
| 58 | |||
| 59 | hwsup = am33xx_cm_is_clkdm_in_hwsup(clkdm->cm_inst, clkdm->clkdm_offs); | ||
| 60 | |||
| 61 | if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) | ||
| 62 | am33xx_clkdm_sleep(clkdm); | ||
| 63 | |||
| 64 | return 0; | ||
| 65 | } | ||
| 66 | |||
| 67 | struct clkdm_ops am33xx_clkdm_operations = { | ||
| 68 | .clkdm_sleep = am33xx_clkdm_sleep, | ||
| 69 | .clkdm_wakeup = am33xx_clkdm_wakeup, | ||
| 70 | .clkdm_allow_idle = am33xx_clkdm_allow_idle, | ||
| 71 | .clkdm_deny_idle = am33xx_clkdm_deny_idle, | ||
| 72 | .clkdm_clk_enable = am33xx_clkdm_clk_enable, | ||
| 73 | .clkdm_clk_disable = am33xx_clkdm_clk_disable, | ||
| 74 | }; | ||
diff --git a/arch/arm/mach-omap2/clockdomains2420_data.c b/arch/arm/mach-omap2/clockdomains2420_data.c index 0ab8e46d5b2b..5c741852fac0 100644 --- a/arch/arm/mach-omap2/clockdomains2420_data.c +++ b/arch/arm/mach-omap2/clockdomains2420_data.c | |||
| @@ -131,8 +131,6 @@ static struct clockdomain dss_2420_clkdm = { | |||
| 131 | 131 | ||
| 132 | static struct clockdomain *clockdomains_omap242x[] __initdata = { | 132 | static struct clockdomain *clockdomains_omap242x[] __initdata = { |
| 133 | &wkup_common_clkdm, | 133 | &wkup_common_clkdm, |
| 134 | &cm_common_clkdm, | ||
| 135 | &prm_common_clkdm, | ||
| 136 | &mpu_2420_clkdm, | 134 | &mpu_2420_clkdm, |
| 137 | &iva1_2420_clkdm, | 135 | &iva1_2420_clkdm, |
| 138 | &dsp_2420_clkdm, | 136 | &dsp_2420_clkdm, |
diff --git a/arch/arm/mach-omap2/clockdomains2430_data.c b/arch/arm/mach-omap2/clockdomains2430_data.c index 3645ed044890..f09617555e15 100644 --- a/arch/arm/mach-omap2/clockdomains2430_data.c +++ b/arch/arm/mach-omap2/clockdomains2430_data.c | |||
| @@ -157,8 +157,6 @@ static struct clockdomain dss_2430_clkdm = { | |||
| 157 | 157 | ||
| 158 | static struct clockdomain *clockdomains_omap243x[] __initdata = { | 158 | static struct clockdomain *clockdomains_omap243x[] __initdata = { |
| 159 | &wkup_common_clkdm, | 159 | &wkup_common_clkdm, |
| 160 | &cm_common_clkdm, | ||
| 161 | &prm_common_clkdm, | ||
| 162 | &mpu_2430_clkdm, | 160 | &mpu_2430_clkdm, |
| 163 | &mdm_clkdm, | 161 | &mdm_clkdm, |
| 164 | &dsp_2430_clkdm, | 162 | &dsp_2430_clkdm, |
diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c index 839145e1cfbe..4972219653ce 100644 --- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c +++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c | |||
| @@ -88,4 +88,5 @@ struct clockdomain wkup_common_clkdm = { | |||
| 88 | .name = "wkup_clkdm", | 88 | .name = "wkup_clkdm", |
| 89 | .pwrdm = { .name = "wkup_pwrdm" }, | 89 | .pwrdm = { .name = "wkup_pwrdm" }, |
| 90 | .dep_bit = OMAP_EN_WKUP_SHIFT, | 90 | .dep_bit = OMAP_EN_WKUP_SHIFT, |
| 91 | .flags = CLKDM_ACTIVE_WITH_MPU, | ||
| 91 | }; | 92 | }; |
diff --git a/arch/arm/mach-omap2/clockdomains33xx_data.c b/arch/arm/mach-omap2/clockdomains33xx_data.c new file mode 100644 index 000000000000..32c90fd9eba2 --- /dev/null +++ b/arch/arm/mach-omap2/clockdomains33xx_data.c | |||
| @@ -0,0 +1,196 @@ | |||
| 1 | /* | ||
| 2 | * AM33XX Clock Domain data. | ||
| 3 | * | ||
| 4 | * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 5 | * Vaibhav Hiremath <hvaibhav@ti.com> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or | ||
| 8 | * modify it under the terms of the GNU General Public License as | ||
| 9 | * published by the Free Software Foundation version 2. | ||
| 10 | * | ||
| 11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
| 12 | * kind, whether express or implied; without even the implied warranty | ||
| 13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include <linux/kernel.h> | ||
| 18 | #include <linux/io.h> | ||
| 19 | |||
| 20 | #include "clockdomain.h" | ||
| 21 | #include "cm.h" | ||
| 22 | #include "cm33xx.h" | ||
| 23 | #include "cm-regbits-33xx.h" | ||
| 24 | |||
| 25 | static struct clockdomain l4ls_am33xx_clkdm = { | ||
| 26 | .name = "l4ls_clkdm", | ||
| 27 | .pwrdm = { .name = "per_pwrdm" }, | ||
| 28 | .cm_inst = AM33XX_CM_PER_MOD, | ||
| 29 | .clkdm_offs = AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET, | ||
| 30 | .flags = CLKDM_CAN_SWSUP, | ||
| 31 | }; | ||
| 32 | |||
| 33 | static struct clockdomain l3s_am33xx_clkdm = { | ||
| 34 | .name = "l3s_clkdm", | ||
| 35 | .pwrdm = { .name = "per_pwrdm" }, | ||
| 36 | .cm_inst = AM33XX_CM_PER_MOD, | ||
| 37 | .clkdm_offs = AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET, | ||
| 38 | .flags = CLKDM_CAN_SWSUP, | ||
| 39 | }; | ||
| 40 | |||
| 41 | static struct clockdomain l4fw_am33xx_clkdm = { | ||
| 42 | .name = "l4fw_clkdm", | ||
| 43 | .pwrdm = { .name = "per_pwrdm" }, | ||
| 44 | .cm_inst = AM33XX_CM_PER_MOD, | ||
| 45 | .clkdm_offs = AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET, | ||
| 46 | .flags = CLKDM_CAN_SWSUP, | ||
| 47 | }; | ||
| 48 | |||
| 49 | static struct clockdomain l3_am33xx_clkdm = { | ||
| 50 | .name = "l3_clkdm", | ||
| 51 | .pwrdm = { .name = "per_pwrdm" }, | ||
| 52 | .cm_inst = AM33XX_CM_PER_MOD, | ||
| 53 | .clkdm_offs = AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET, | ||
| 54 | .flags = CLKDM_CAN_SWSUP, | ||
| 55 | }; | ||
| 56 | |||
| 57 | static struct clockdomain l4hs_am33xx_clkdm = { | ||
| 58 | .name = "l4hs_clkdm", | ||
| 59 | .pwrdm = { .name = "per_pwrdm" }, | ||
| 60 | .cm_inst = AM33XX_CM_PER_MOD, | ||
| 61 | .clkdm_offs = AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET, | ||
| 62 | .flags = CLKDM_CAN_SWSUP, | ||
| 63 | }; | ||
| 64 | |||
| 65 | static struct clockdomain ocpwp_l3_am33xx_clkdm = { | ||
| 66 | .name = "ocpwp_l3_clkdm", | ||
| 67 | .pwrdm = { .name = "per_pwrdm" }, | ||
| 68 | .cm_inst = AM33XX_CM_PER_MOD, | ||
| 69 | .clkdm_offs = AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET, | ||
| 70 | .flags = CLKDM_CAN_SWSUP, | ||
| 71 | }; | ||
| 72 | |||
| 73 | static struct clockdomain pruss_ocp_am33xx_clkdm = { | ||
| 74 | .name = "pruss_ocp_clkdm", | ||
| 75 | .pwrdm = { .name = "per_pwrdm" }, | ||
| 76 | .cm_inst = AM33XX_CM_PER_MOD, | ||
| 77 | .clkdm_offs = AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET, | ||
| 78 | .flags = CLKDM_CAN_SWSUP, | ||
| 79 | }; | ||
| 80 | |||
| 81 | static struct clockdomain cpsw_125mhz_am33xx_clkdm = { | ||
| 82 | .name = "cpsw_125mhz_clkdm", | ||
| 83 | .pwrdm = { .name = "per_pwrdm" }, | ||
| 84 | .cm_inst = AM33XX_CM_PER_MOD, | ||
| 85 | .clkdm_offs = AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET, | ||
| 86 | .flags = CLKDM_CAN_SWSUP, | ||
| 87 | }; | ||
| 88 | |||
| 89 | static struct clockdomain lcdc_am33xx_clkdm = { | ||
| 90 | .name = "lcdc_clkdm", | ||
| 91 | .pwrdm = { .name = "per_pwrdm" }, | ||
| 92 | .cm_inst = AM33XX_CM_PER_MOD, | ||
| 93 | .clkdm_offs = AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET, | ||
| 94 | .flags = CLKDM_CAN_SWSUP, | ||
| 95 | }; | ||
| 96 | |||
| 97 | static struct clockdomain clk_24mhz_am33xx_clkdm = { | ||
| 98 | .name = "clk_24mhz_clkdm", | ||
| 99 | .pwrdm = { .name = "per_pwrdm" }, | ||
| 100 | .cm_inst = AM33XX_CM_PER_MOD, | ||
| 101 | .clkdm_offs = AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET, | ||
| 102 | .flags = CLKDM_CAN_SWSUP, | ||
| 103 | }; | ||
| 104 | |||
| 105 | static struct clockdomain l4_wkup_am33xx_clkdm = { | ||
| 106 | .name = "l4_wkup_clkdm", | ||
| 107 | .pwrdm = { .name = "wkup_pwrdm" }, | ||
| 108 | .cm_inst = AM33XX_CM_WKUP_MOD, | ||
| 109 | .clkdm_offs = AM33XX_CM_WKUP_CLKSTCTRL_OFFSET, | ||
| 110 | .flags = CLKDM_CAN_SWSUP, | ||
| 111 | }; | ||
| 112 | |||
| 113 | static struct clockdomain l3_aon_am33xx_clkdm = { | ||
| 114 | .name = "l3_aon_clkdm", | ||
| 115 | .pwrdm = { .name = "wkup_pwrdm" }, | ||
| 116 | .cm_inst = AM33XX_CM_WKUP_MOD, | ||
| 117 | .clkdm_offs = AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET, | ||
| 118 | .flags = CLKDM_CAN_SWSUP, | ||
| 119 | }; | ||
| 120 | |||
| 121 | static struct clockdomain l4_wkup_aon_am33xx_clkdm = { | ||
| 122 | .name = "l4_wkup_aon_clkdm", | ||
| 123 | .pwrdm = { .name = "wkup_pwrdm" }, | ||
| 124 | .cm_inst = AM33XX_CM_WKUP_MOD, | ||
| 125 | .clkdm_offs = AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET, | ||
| 126 | .flags = CLKDM_CAN_SWSUP, | ||
| 127 | }; | ||
| 128 | |||
| 129 | static struct clockdomain mpu_am33xx_clkdm = { | ||
| 130 | .name = "mpu_clkdm", | ||
| 131 | .pwrdm = { .name = "mpu_pwrdm" }, | ||
| 132 | .cm_inst = AM33XX_CM_MPU_MOD, | ||
| 133 | .clkdm_offs = AM33XX_CM_MPU_CLKSTCTRL_OFFSET, | ||
| 134 | .flags = CLKDM_CAN_SWSUP, | ||
| 135 | }; | ||
| 136 | |||
| 137 | static struct clockdomain l4_rtc_am33xx_clkdm = { | ||
| 138 | .name = "l4_rtc_clkdm", | ||
| 139 | .pwrdm = { .name = "rtc_pwrdm" }, | ||
| 140 | .cm_inst = AM33XX_CM_RTC_MOD, | ||
| 141 | .clkdm_offs = AM33XX_CM_RTC_CLKSTCTRL_OFFSET, | ||
| 142 | .flags = CLKDM_CAN_SWSUP, | ||
| 143 | }; | ||
| 144 | |||
| 145 | static struct clockdomain gfx_l3_am33xx_clkdm = { | ||
| 146 | .name = "gfx_l3_clkdm", | ||
| 147 | .pwrdm = { .name = "gfx_pwrdm" }, | ||
| 148 | .cm_inst = AM33XX_CM_GFX_MOD, | ||
| 149 | .clkdm_offs = AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET, | ||
| 150 | .flags = CLKDM_CAN_SWSUP, | ||
| 151 | }; | ||
| 152 | |||
| 153 | static struct clockdomain gfx_l4ls_gfx_am33xx_clkdm = { | ||
| 154 | .name = "gfx_l4ls_gfx_clkdm", | ||
| 155 | .pwrdm = { .name = "gfx_pwrdm" }, | ||
| 156 | .cm_inst = AM33XX_CM_GFX_MOD, | ||
| 157 | .clkdm_offs = AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET, | ||
| 158 | .flags = CLKDM_CAN_SWSUP, | ||
| 159 | }; | ||
| 160 | |||
| 161 | static struct clockdomain l4_cefuse_am33xx_clkdm = { | ||
| 162 | .name = "l4_cefuse_clkdm", | ||
| 163 | .pwrdm = { .name = "cefuse_pwrdm" }, | ||
| 164 | .cm_inst = AM33XX_CM_CEFUSE_MOD, | ||
| 165 | .clkdm_offs = AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET, | ||
| 166 | .flags = CLKDM_CAN_SWSUP, | ||
| 167 | }; | ||
| 168 | |||
| 169 | static struct clockdomain *clockdomains_am33xx[] __initdata = { | ||
| 170 | &l4ls_am33xx_clkdm, | ||
| 171 | &l3s_am33xx_clkdm, | ||
| 172 | &l4fw_am33xx_clkdm, | ||
| 173 | &l3_am33xx_clkdm, | ||
| 174 | &l4hs_am33xx_clkdm, | ||
| 175 | &ocpwp_l3_am33xx_clkdm, | ||
| 176 | &pruss_ocp_am33xx_clkdm, | ||
| 177 | &cpsw_125mhz_am33xx_clkdm, | ||
| 178 | &lcdc_am33xx_clkdm, | ||
| 179 | &clk_24mhz_am33xx_clkdm, | ||
| 180 | &l4_wkup_am33xx_clkdm, | ||
| 181 | &l3_aon_am33xx_clkdm, | ||
| 182 | &l4_wkup_aon_am33xx_clkdm, | ||
| 183 | &mpu_am33xx_clkdm, | ||
| 184 | &l4_rtc_am33xx_clkdm, | ||
| 185 | &gfx_l3_am33xx_clkdm, | ||
| 186 | &gfx_l4ls_gfx_am33xx_clkdm, | ||
| 187 | &l4_cefuse_am33xx_clkdm, | ||
| 188 | NULL, | ||
| 189 | }; | ||
| 190 | |||
| 191 | void __init am33xx_clockdomains_init(void) | ||
| 192 | { | ||
| 193 | clkdm_register_platform_funcs(&am33xx_clkdm_operations); | ||
| 194 | clkdm_register_clkdms(clockdomains_am33xx); | ||
| 195 | clkdm_complete_init(); | ||
| 196 | } | ||
diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c index 6038adb97710..56089c49142a 100644 --- a/arch/arm/mach-omap2/clockdomains3xxx_data.c +++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c | |||
| @@ -59,6 +59,12 @@ static struct clkdm_dep gfx_sgx_3xxx_wkdeps[] = { | |||
| 59 | { NULL }, | 59 | { NULL }, |
| 60 | }; | 60 | }; |
| 61 | 61 | ||
| 62 | static struct clkdm_dep gfx_sgx_am35x_wkdeps[] = { | ||
| 63 | { .clkdm_name = "mpu_clkdm" }, | ||
| 64 | { .clkdm_name = "wkup_clkdm" }, | ||
| 65 | { NULL }, | ||
| 66 | }; | ||
| 67 | |||
| 62 | /* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */ | 68 | /* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */ |
| 63 | static struct clkdm_dep per_wkdeps[] = { | 69 | static struct clkdm_dep per_wkdeps[] = { |
| 64 | { .clkdm_name = "core_l3_clkdm" }, | 70 | { .clkdm_name = "core_l3_clkdm" }, |
| @@ -69,6 +75,14 @@ static struct clkdm_dep per_wkdeps[] = { | |||
| 69 | { NULL }, | 75 | { NULL }, |
| 70 | }; | 76 | }; |
| 71 | 77 | ||
| 78 | static struct clkdm_dep per_am35x_wkdeps[] = { | ||
| 79 | { .clkdm_name = "core_l3_clkdm" }, | ||
| 80 | { .clkdm_name = "core_l4_clkdm" }, | ||
| 81 | { .clkdm_name = "mpu_clkdm" }, | ||
| 82 | { .clkdm_name = "wkup_clkdm" }, | ||
| 83 | { NULL }, | ||
| 84 | }; | ||
| 85 | |||
| 72 | /* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */ | 86 | /* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */ |
| 73 | static struct clkdm_dep usbhost_wkdeps[] = { | 87 | static struct clkdm_dep usbhost_wkdeps[] = { |
| 74 | { .clkdm_name = "core_l3_clkdm" }, | 88 | { .clkdm_name = "core_l3_clkdm" }, |
| @@ -79,6 +93,14 @@ static struct clkdm_dep usbhost_wkdeps[] = { | |||
| 79 | { NULL }, | 93 | { NULL }, |
| 80 | }; | 94 | }; |
| 81 | 95 | ||
| 96 | static struct clkdm_dep usbhost_am35x_wkdeps[] = { | ||
| 97 | { .clkdm_name = "core_l3_clkdm" }, | ||
| 98 | { .clkdm_name = "core_l4_clkdm" }, | ||
| 99 | { .clkdm_name = "mpu_clkdm" }, | ||
| 100 | { .clkdm_name = "wkup_clkdm" }, | ||
| 101 | { NULL }, | ||
| 102 | }; | ||
| 103 | |||
| 82 | /* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */ | 104 | /* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */ |
| 83 | static struct clkdm_dep mpu_3xxx_wkdeps[] = { | 105 | static struct clkdm_dep mpu_3xxx_wkdeps[] = { |
| 84 | { .clkdm_name = "core_l3_clkdm" }, | 106 | { .clkdm_name = "core_l3_clkdm" }, |
| @@ -89,6 +111,14 @@ static struct clkdm_dep mpu_3xxx_wkdeps[] = { | |||
| 89 | { NULL }, | 111 | { NULL }, |
| 90 | }; | 112 | }; |
| 91 | 113 | ||
| 114 | static struct clkdm_dep mpu_am35x_wkdeps[] = { | ||
| 115 | { .clkdm_name = "core_l3_clkdm" }, | ||
| 116 | { .clkdm_name = "core_l4_clkdm" }, | ||
| 117 | { .clkdm_name = "dss_clkdm" }, | ||
| 118 | { .clkdm_name = "per_clkdm" }, | ||
| 119 | { NULL }, | ||
| 120 | }; | ||
| 121 | |||
| 92 | /* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */ | 122 | /* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */ |
| 93 | static struct clkdm_dep iva2_wkdeps[] = { | 123 | static struct clkdm_dep iva2_wkdeps[] = { |
| 94 | { .clkdm_name = "core_l3_clkdm" }, | 124 | { .clkdm_name = "core_l3_clkdm" }, |
| @@ -116,6 +146,12 @@ static struct clkdm_dep dss_wkdeps[] = { | |||
| 116 | { NULL }, | 146 | { NULL }, |
| 117 | }; | 147 | }; |
| 118 | 148 | ||
| 149 | static struct clkdm_dep dss_am35x_wkdeps[] = { | ||
| 150 | { .clkdm_name = "mpu_clkdm" }, | ||
| 151 | { .clkdm_name = "wkup_clkdm" }, | ||
| 152 | { NULL }, | ||
| 153 | }; | ||
| 154 | |||
| 119 | /* 3430: PM_WKDEP_NEON: MPU */ | 155 | /* 3430: PM_WKDEP_NEON: MPU */ |
| 120 | static struct clkdm_dep neon_wkdeps[] = { | 156 | static struct clkdm_dep neon_wkdeps[] = { |
| 121 | { .clkdm_name = "mpu_clkdm" }, | 157 | { .clkdm_name = "mpu_clkdm" }, |
| @@ -131,6 +167,11 @@ static struct clkdm_dep dss_sleepdeps[] = { | |||
| 131 | { NULL }, | 167 | { NULL }, |
| 132 | }; | 168 | }; |
| 133 | 169 | ||
| 170 | static struct clkdm_dep dss_am35x_sleepdeps[] = { | ||
| 171 | { .clkdm_name = "mpu_clkdm" }, | ||
| 172 | { NULL }, | ||
| 173 | }; | ||
| 174 | |||
| 134 | /* 3430: CM_SLEEPDEP_PER: MPU, IVA */ | 175 | /* 3430: CM_SLEEPDEP_PER: MPU, IVA */ |
| 135 | static struct clkdm_dep per_sleepdeps[] = { | 176 | static struct clkdm_dep per_sleepdeps[] = { |
| 136 | { .clkdm_name = "mpu_clkdm" }, | 177 | { .clkdm_name = "mpu_clkdm" }, |
| @@ -138,6 +179,11 @@ static struct clkdm_dep per_sleepdeps[] = { | |||
| 138 | { NULL }, | 179 | { NULL }, |
| 139 | }; | 180 | }; |
| 140 | 181 | ||
| 182 | static struct clkdm_dep per_am35x_sleepdeps[] = { | ||
| 183 | { .clkdm_name = "mpu_clkdm" }, | ||
| 184 | { NULL }, | ||
| 185 | }; | ||
| 186 | |||
| 141 | /* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */ | 187 | /* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */ |
| 142 | static struct clkdm_dep usbhost_sleepdeps[] = { | 188 | static struct clkdm_dep usbhost_sleepdeps[] = { |
| 143 | { .clkdm_name = "mpu_clkdm" }, | 189 | { .clkdm_name = "mpu_clkdm" }, |
| @@ -145,6 +191,11 @@ static struct clkdm_dep usbhost_sleepdeps[] = { | |||
| 145 | { NULL }, | 191 | { NULL }, |
| 146 | }; | 192 | }; |
| 147 | 193 | ||
| 194 | static struct clkdm_dep usbhost_am35x_sleepdeps[] = { | ||
| 195 | { .clkdm_name = "mpu_clkdm" }, | ||
| 196 | { NULL }, | ||
| 197 | }; | ||
| 198 | |||
| 148 | /* 3430: CM_SLEEPDEP_CAM: MPU */ | 199 | /* 3430: CM_SLEEPDEP_CAM: MPU */ |
| 149 | static struct clkdm_dep cam_sleepdeps[] = { | 200 | static struct clkdm_dep cam_sleepdeps[] = { |
| 150 | { .clkdm_name = "mpu_clkdm" }, | 201 | { .clkdm_name = "mpu_clkdm" }, |
| @@ -175,6 +226,15 @@ static struct clockdomain mpu_3xxx_clkdm = { | |||
| 175 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK, | 226 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK, |
| 176 | }; | 227 | }; |
| 177 | 228 | ||
| 229 | static struct clockdomain mpu_am35x_clkdm = { | ||
| 230 | .name = "mpu_clkdm", | ||
| 231 | .pwrdm = { .name = "mpu_pwrdm" }, | ||
| 232 | .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP, | ||
| 233 | .dep_bit = OMAP3430_EN_MPU_SHIFT, | ||
| 234 | .wkdep_srcs = mpu_am35x_wkdeps, | ||
| 235 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK, | ||
| 236 | }; | ||
| 237 | |||
| 178 | static struct clockdomain neon_clkdm = { | 238 | static struct clockdomain neon_clkdm = { |
| 179 | .name = "neon_clkdm", | 239 | .name = "neon_clkdm", |
| 180 | .pwrdm = { .name = "neon_pwrdm" }, | 240 | .pwrdm = { .name = "neon_pwrdm" }, |
| @@ -210,6 +270,15 @@ static struct clockdomain sgx_clkdm = { | |||
| 210 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK, | 270 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK, |
| 211 | }; | 271 | }; |
| 212 | 272 | ||
| 273 | static struct clockdomain sgx_am35x_clkdm = { | ||
| 274 | .name = "sgx_clkdm", | ||
| 275 | .pwrdm = { .name = "sgx_pwrdm" }, | ||
| 276 | .flags = CLKDM_CAN_HWSUP_SWSUP, | ||
| 277 | .wkdep_srcs = gfx_sgx_am35x_wkdeps, | ||
| 278 | .sleepdep_srcs = gfx_sgx_sleepdeps, | ||
| 279 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK, | ||
| 280 | }; | ||
| 281 | |||
| 213 | /* | 282 | /* |
| 214 | * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but | 283 | * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but |
| 215 | * then that information was removed from the 34xx ES2+ TRM. It is | 284 | * then that information was removed from the 34xx ES2+ TRM. It is |
| @@ -261,6 +330,16 @@ static struct clockdomain dss_3xxx_clkdm = { | |||
| 261 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK, | 330 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK, |
| 262 | }; | 331 | }; |
| 263 | 332 | ||
| 333 | static struct clockdomain dss_am35x_clkdm = { | ||
| 334 | .name = "dss_clkdm", | ||
| 335 | .pwrdm = { .name = "dss_pwrdm" }, | ||
| 336 | .flags = CLKDM_CAN_HWSUP_SWSUP, | ||
| 337 | .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT, | ||
| 338 | .wkdep_srcs = dss_am35x_wkdeps, | ||
| 339 | .sleepdep_srcs = dss_am35x_sleepdeps, | ||
| 340 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK, | ||
| 341 | }; | ||
| 342 | |||
| 264 | static struct clockdomain cam_clkdm = { | 343 | static struct clockdomain cam_clkdm = { |
| 265 | .name = "cam_clkdm", | 344 | .name = "cam_clkdm", |
| 266 | .pwrdm = { .name = "cam_pwrdm" }, | 345 | .pwrdm = { .name = "cam_pwrdm" }, |
| @@ -279,6 +358,15 @@ static struct clockdomain usbhost_clkdm = { | |||
| 279 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK, | 358 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK, |
| 280 | }; | 359 | }; |
| 281 | 360 | ||
| 361 | static struct clockdomain usbhost_am35x_clkdm = { | ||
| 362 | .name = "usbhost_clkdm", | ||
| 363 | .pwrdm = { .name = "core_pwrdm" }, | ||
| 364 | .flags = CLKDM_CAN_HWSUP_SWSUP, | ||
| 365 | .wkdep_srcs = usbhost_am35x_wkdeps, | ||
| 366 | .sleepdep_srcs = usbhost_am35x_sleepdeps, | ||
| 367 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK, | ||
| 368 | }; | ||
| 369 | |||
| 282 | static struct clockdomain per_clkdm = { | 370 | static struct clockdomain per_clkdm = { |
| 283 | .name = "per_clkdm", | 371 | .name = "per_clkdm", |
| 284 | .pwrdm = { .name = "per_pwrdm" }, | 372 | .pwrdm = { .name = "per_pwrdm" }, |
| @@ -289,6 +377,16 @@ static struct clockdomain per_clkdm = { | |||
| 289 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK, | 377 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK, |
| 290 | }; | 378 | }; |
| 291 | 379 | ||
| 380 | static struct clockdomain per_am35x_clkdm = { | ||
| 381 | .name = "per_clkdm", | ||
| 382 | .pwrdm = { .name = "per_pwrdm" }, | ||
| 383 | .flags = CLKDM_CAN_HWSUP_SWSUP, | ||
| 384 | .dep_bit = OMAP3430_EN_PER_SHIFT, | ||
| 385 | .wkdep_srcs = per_am35x_wkdeps, | ||
| 386 | .sleepdep_srcs = per_am35x_sleepdeps, | ||
| 387 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK, | ||
| 388 | }; | ||
| 389 | |||
| 292 | /* | 390 | /* |
| 293 | * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is | 391 | * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is |
| 294 | * switched of even if sdti is in use | 392 | * switched of even if sdti is in use |
| @@ -341,31 +439,42 @@ static struct clkdm_autodep clkdm_autodeps[] = { | |||
| 341 | } | 439 | } |
| 342 | }; | 440 | }; |
| 343 | 441 | ||
| 442 | static struct clkdm_autodep clkdm_am35x_autodeps[] = { | ||
| 443 | { | ||
| 444 | .clkdm = { .name = "mpu_clkdm" }, | ||
| 445 | }, | ||
| 446 | { | ||
| 447 | .clkdm = { .name = NULL }, | ||
| 448 | } | ||
| 449 | }; | ||
| 450 | |||
| 344 | /* | 451 | /* |
| 345 | * | 452 | * |
| 346 | */ | 453 | */ |
| 347 | 454 | ||
| 348 | static struct clockdomain *clockdomains_omap3430_common[] __initdata = { | 455 | static struct clockdomain *clockdomains_common[] __initdata = { |
| 349 | &wkup_common_clkdm, | 456 | &wkup_common_clkdm, |
| 350 | &cm_common_clkdm, | ||
| 351 | &prm_common_clkdm, | ||
| 352 | &mpu_3xxx_clkdm, | ||
| 353 | &neon_clkdm, | 457 | &neon_clkdm, |
| 354 | &iva2_clkdm, | ||
| 355 | &d2d_clkdm, | ||
| 356 | &core_l3_3xxx_clkdm, | 458 | &core_l3_3xxx_clkdm, |
| 357 | &core_l4_3xxx_clkdm, | 459 | &core_l4_3xxx_clkdm, |
| 358 | &dss_3xxx_clkdm, | ||
| 359 | &cam_clkdm, | ||
| 360 | &per_clkdm, | ||
| 361 | &emu_clkdm, | 460 | &emu_clkdm, |
| 362 | &dpll1_clkdm, | 461 | &dpll1_clkdm, |
| 363 | &dpll2_clkdm, | ||
| 364 | &dpll3_clkdm, | 462 | &dpll3_clkdm, |
| 365 | &dpll4_clkdm, | 463 | &dpll4_clkdm, |
| 366 | NULL | 464 | NULL |
| 367 | }; | 465 | }; |
| 368 | 466 | ||
| 467 | static struct clockdomain *clockdomains_omap3430[] __initdata = { | ||
| 468 | &mpu_3xxx_clkdm, | ||
| 469 | &iva2_clkdm, | ||
| 470 | &d2d_clkdm, | ||
| 471 | &dss_3xxx_clkdm, | ||
| 472 | &cam_clkdm, | ||
| 473 | &per_clkdm, | ||
| 474 | &dpll2_clkdm, | ||
| 475 | NULL | ||
| 476 | }; | ||
| 477 | |||
| 369 | static struct clockdomain *clockdomains_omap3430es1[] __initdata = { | 478 | static struct clockdomain *clockdomains_omap3430es1[] __initdata = { |
| 370 | &gfx_3430es1_clkdm, | 479 | &gfx_3430es1_clkdm, |
| 371 | NULL, | 480 | NULL, |
| @@ -378,21 +487,41 @@ static struct clockdomain *clockdomains_omap3430es2plus[] __initdata = { | |||
| 378 | NULL, | 487 | NULL, |
| 379 | }; | 488 | }; |
| 380 | 489 | ||
| 490 | static struct clockdomain *clockdomains_am35x[] __initdata = { | ||
| 491 | &mpu_am35x_clkdm, | ||
| 492 | &sgx_am35x_clkdm, | ||
| 493 | &dss_am35x_clkdm, | ||
| 494 | &per_am35x_clkdm, | ||
| 495 | &usbhost_am35x_clkdm, | ||
| 496 | &dpll5_clkdm, | ||
| 497 | NULL | ||
| 498 | }; | ||
| 499 | |||
| 381 | void __init omap3xxx_clockdomains_init(void) | 500 | void __init omap3xxx_clockdomains_init(void) |
| 382 | { | 501 | { |
| 383 | struct clockdomain **sc; | 502 | struct clockdomain **sc; |
| 503 | unsigned int rev; | ||
| 384 | 504 | ||
| 385 | if (!cpu_is_omap34xx()) | 505 | if (!cpu_is_omap34xx()) |
| 386 | return; | 506 | return; |
| 387 | 507 | ||
| 388 | clkdm_register_platform_funcs(&omap3_clkdm_operations); | 508 | clkdm_register_platform_funcs(&omap3_clkdm_operations); |
| 389 | clkdm_register_clkdms(clockdomains_omap3430_common); | 509 | clkdm_register_clkdms(clockdomains_common); |
| 390 | 510 | ||
| 391 | sc = (omap_rev() == OMAP3430_REV_ES1_0) ? clockdomains_omap3430es1 : | 511 | rev = omap_rev(); |
| 392 | clockdomains_omap3430es2plus; | ||
| 393 | 512 | ||
| 394 | clkdm_register_clkdms(sc); | 513 | if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) { |
| 514 | clkdm_register_clkdms(clockdomains_am35x); | ||
| 515 | clkdm_register_autodeps(clkdm_am35x_autodeps); | ||
| 516 | } else { | ||
| 517 | clkdm_register_clkdms(clockdomains_omap3430); | ||
| 518 | |||
| 519 | sc = (rev == OMAP3430_REV_ES1_0) ? | ||
| 520 | clockdomains_omap3430es1 : clockdomains_omap3430es2plus; | ||
| 521 | |||
| 522 | clkdm_register_clkdms(sc); | ||
| 523 | clkdm_register_autodeps(clkdm_autodeps); | ||
| 524 | } | ||
| 395 | 525 | ||
| 396 | clkdm_register_autodeps(clkdm_autodeps); | ||
| 397 | clkdm_complete_init(); | 526 | clkdm_complete_init(); |
| 398 | } | 527 | } |
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c index c53425847493..63d60a773d3b 100644 --- a/arch/arm/mach-omap2/clockdomains44xx_data.c +++ b/arch/arm/mach-omap2/clockdomains44xx_data.c | |||
| @@ -381,7 +381,7 @@ static struct clockdomain l4_wkup_44xx_clkdm = { | |||
| 381 | .cm_inst = OMAP4430_PRM_WKUP_CM_INST, | 381 | .cm_inst = OMAP4430_PRM_WKUP_CM_INST, |
| 382 | .clkdm_offs = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS, | 382 | .clkdm_offs = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS, |
| 383 | .dep_bit = OMAP4430_L4WKUP_STATDEP_SHIFT, | 383 | .dep_bit = OMAP4430_L4WKUP_STATDEP_SHIFT, |
| 384 | .flags = CLKDM_CAN_HWSUP, | 384 | .flags = CLKDM_CAN_HWSUP | CLKDM_ACTIVE_WITH_MPU, |
| 385 | }; | 385 | }; |
| 386 | 386 | ||
| 387 | static struct clockdomain emu_sys_44xx_clkdm = { | 387 | static struct clockdomain emu_sys_44xx_clkdm = { |
| @@ -430,8 +430,6 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = { | |||
| 430 | &l4_wkup_44xx_clkdm, | 430 | &l4_wkup_44xx_clkdm, |
| 431 | &emu_sys_44xx_clkdm, | 431 | &emu_sys_44xx_clkdm, |
| 432 | &l3_dma_44xx_clkdm, | 432 | &l3_dma_44xx_clkdm, |
| 433 | &prm_common_clkdm, | ||
| 434 | &cm_common_clkdm, | ||
| 435 | NULL | 433 | NULL |
| 436 | }; | 434 | }; |
| 437 | 435 | ||
diff --git a/arch/arm/mach-omap2/clockdomains_common_data.c b/arch/arm/mach-omap2/clockdomains_common_data.c deleted file mode 100644 index 615b1f04967d..000000000000 --- a/arch/arm/mach-omap2/clockdomains_common_data.c +++ /dev/null | |||
| @@ -1,24 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * OMAP2+-common clockdomain data | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008-2012 Texas Instruments, Inc. | ||
| 5 | * Copyright (C) 2008-2010 Nokia Corporation | ||
| 6 | * | ||
| 7 | * Paul Walmsley, Jouni Högander | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include <linux/kernel.h> | ||
| 11 | #include <linux/io.h> | ||
| 12 | |||
| 13 | #include "clockdomain.h" | ||
| 14 | |||
| 15 | /* These are implicit clockdomains - they are never defined as such in TRM */ | ||
| 16 | struct clockdomain prm_common_clkdm = { | ||
| 17 | .name = "prm_clkdm", | ||
| 18 | .pwrdm = { .name = "wkup_pwrdm" }, | ||
| 19 | }; | ||
| 20 | |||
| 21 | struct clockdomain cm_common_clkdm = { | ||
| 22 | .name = "cm_clkdm", | ||
| 23 | .pwrdm = { .name = "core_pwrdm" }, | ||
| 24 | }; | ||
diff --git a/arch/arm/mach-omap2/cm-regbits-33xx.h b/arch/arm/mach-omap2/cm-regbits-33xx.h new file mode 100644 index 000000000000..532027ee3d8d --- /dev/null +++ b/arch/arm/mach-omap2/cm-regbits-33xx.h | |||
| @@ -0,0 +1,687 @@ | |||
| 1 | /* | ||
| 2 | * AM33XX Power Management register bits | ||
| 3 | * | ||
| 4 | * This file is automatically generated from the AM33XX hardware databases. | ||
| 5 | * Vaibhav Hiremath <hvaibhav@ti.com> | ||
| 6 | * | ||
| 7 | * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or | ||
| 10 | * modify it under the terms of the GNU General Public License as | ||
| 11 | * published by the Free Software Foundation version 2. | ||
| 12 | * | ||
| 13 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
| 14 | * kind, whether express or implied; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | */ | ||
| 18 | |||
| 19 | |||
| 20 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H | ||
| 21 | #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H | ||
| 22 | |||
| 23 | /* | ||
| 24 | * Used by CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_DDR, CM_AUTOIDLE_DPLL_DISP, | ||
| 25 | * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER | ||
| 26 | */ | ||
| 27 | #define AM33XX_AUTO_DPLL_MODE_SHIFT 0 | ||
| 28 | #define AM33XX_AUTO_DPLL_MODE_MASK (0x7 << 0) | ||
| 29 | |||
| 30 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
| 31 | #define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT 14 | ||
| 32 | #define AM33XX_CLKACTIVITY_ADC_FCLK_MASK (1 << 16) | ||
| 33 | |||
| 34 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 35 | #define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT 11 | ||
| 36 | #define AM33XX_CLKACTIVITY_CAN_CLK_MASK (1 << 11) | ||
| 37 | |||
| 38 | /* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */ | ||
| 39 | #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT 4 | ||
| 40 | #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK (1 << 4) | ||
| 41 | |||
| 42 | /* Used by CM_PER_CPSW_CLKSTCTRL */ | ||
| 43 | #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT 4 | ||
| 44 | #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK (1 << 4) | ||
| 45 | |||
| 46 | /* Used by CM_PER_L4HS_CLKSTCTRL */ | ||
| 47 | #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT 4 | ||
| 48 | #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK (1 << 4) | ||
| 49 | |||
| 50 | /* Used by CM_PER_L4HS_CLKSTCTRL */ | ||
| 51 | #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT 5 | ||
| 52 | #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK (1 << 5) | ||
| 53 | |||
| 54 | /* Used by CM_PER_L4HS_CLKSTCTRL */ | ||
| 55 | #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT 6 | ||
| 56 | #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK (1 << 6) | ||
| 57 | |||
| 58 | /* Used by CM_PER_L3_CLKSTCTRL */ | ||
| 59 | #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT 6 | ||
| 60 | #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK (1 << 6) | ||
| 61 | |||
| 62 | /* Used by CM_CEFUSE_CLKSTCTRL */ | ||
| 63 | #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 | ||
| 64 | #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) | ||
| 65 | |||
| 66 | /* Used by CM_L3_AON_CLKSTCTRL */ | ||
| 67 | #define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT 2 | ||
| 68 | #define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK (1 << 2) | ||
| 69 | |||
| 70 | /* Used by CM_L3_AON_CLKSTCTRL */ | ||
| 71 | #define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT 4 | ||
| 72 | #define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK (1 << 4) | ||
| 73 | |||
| 74 | /* Used by CM_PER_L3_CLKSTCTRL */ | ||
| 75 | #define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT 2 | ||
| 76 | #define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK (1 << 2) | ||
| 77 | |||
| 78 | /* Used by CM_GFX_L3_CLKSTCTRL */ | ||
| 79 | #define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT 9 | ||
| 80 | #define AM33XX_CLKACTIVITY_GFX_FCLK_MASK (1 << 9) | ||
| 81 | |||
| 82 | /* Used by CM_GFX_L3_CLKSTCTRL */ | ||
| 83 | #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT 8 | ||
| 84 | #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK (1 << 8) | ||
| 85 | |||
| 86 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
| 87 | #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT 8 | ||
| 88 | #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK (1 << 8) | ||
| 89 | |||
| 90 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 91 | #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT 19 | ||
| 92 | #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK (1 << 19) | ||
| 93 | |||
| 94 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 95 | #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT 20 | ||
| 96 | #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK (1 << 20) | ||
| 97 | |||
| 98 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 99 | #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT 21 | ||
| 100 | #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK (1 << 21) | ||
| 101 | |||
| 102 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 103 | #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT 22 | ||
| 104 | #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK (1 << 22) | ||
| 105 | |||
| 106 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 107 | #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT 26 | ||
| 108 | #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK (1 << 26) | ||
| 109 | |||
| 110 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 111 | #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT 18 | ||
| 112 | #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK (1 << 18) | ||
| 113 | |||
| 114 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
| 115 | #define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT 11 | ||
| 116 | #define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK (1 << 11) | ||
| 117 | |||
| 118 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 119 | #define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT 24 | ||
| 120 | #define AM33XX_CLKACTIVITY_I2C_FCLK_MASK (1 << 24) | ||
| 121 | |||
| 122 | /* Used by CM_PER_PRUSS_CLKSTCTRL */ | ||
| 123 | #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT 5 | ||
| 124 | #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK (1 << 5) | ||
| 125 | |||
| 126 | /* Used by CM_PER_PRUSS_CLKSTCTRL */ | ||
| 127 | #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT 4 | ||
| 128 | #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK (1 << 4) | ||
| 129 | |||
| 130 | /* Used by CM_PER_PRUSS_CLKSTCTRL */ | ||
| 131 | #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT 6 | ||
| 132 | #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK (1 << 6) | ||
| 133 | |||
| 134 | /* Used by CM_PER_L3S_CLKSTCTRL */ | ||
| 135 | #define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT 3 | ||
| 136 | #define AM33XX_CLKACTIVITY_L3S_GCLK_MASK (1 << 3) | ||
| 137 | |||
| 138 | /* Used by CM_L3_AON_CLKSTCTRL */ | ||
| 139 | #define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT 3 | ||
| 140 | #define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK (1 << 3) | ||
| 141 | |||
| 142 | /* Used by CM_PER_L3_CLKSTCTRL */ | ||
| 143 | #define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT 4 | ||
| 144 | #define AM33XX_CLKACTIVITY_L3_GCLK_MASK (1 << 4) | ||
| 145 | |||
| 146 | /* Used by CM_PER_L4FW_CLKSTCTRL */ | ||
| 147 | #define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT 8 | ||
| 148 | #define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK (1 << 8) | ||
| 149 | |||
| 150 | /* Used by CM_PER_L4HS_CLKSTCTRL */ | ||
| 151 | #define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT 3 | ||
| 152 | #define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK (1 << 3) | ||
| 153 | |||
| 154 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 155 | #define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT 8 | ||
| 156 | #define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK (1 << 8) | ||
| 157 | |||
| 158 | /* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */ | ||
| 159 | #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT 8 | ||
| 160 | #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK (1 << 8) | ||
| 161 | |||
| 162 | /* Used by CM_CEFUSE_CLKSTCTRL */ | ||
| 163 | #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 | ||
| 164 | #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) | ||
| 165 | |||
| 166 | /* Used by CM_RTC_CLKSTCTRL */ | ||
| 167 | #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT 8 | ||
| 168 | #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK (1 << 8) | ||
| 169 | |||
| 170 | /* Used by CM_L4_WKUP_AON_CLKSTCTRL */ | ||
| 171 | #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT 2 | ||
| 172 | #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK (1 << 2) | ||
| 173 | |||
| 174 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
| 175 | #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT 2 | ||
| 176 | #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK (1 << 2) | ||
| 177 | |||
| 178 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 179 | #define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT 17 | ||
| 180 | #define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK (1 << 17) | ||
| 181 | |||
| 182 | /* Used by CM_PER_LCDC_CLKSTCTRL */ | ||
| 183 | #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT 4 | ||
| 184 | #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK (1 << 4) | ||
| 185 | |||
| 186 | /* Used by CM_PER_LCDC_CLKSTCTRL */ | ||
| 187 | #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT 5 | ||
| 188 | #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK (1 << 5) | ||
| 189 | |||
| 190 | /* Used by CM_PER_L3_CLKSTCTRL */ | ||
| 191 | #define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT 7 | ||
| 192 | #define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK (1 << 7) | ||
| 193 | |||
| 194 | /* Used by CM_PER_L3_CLKSTCTRL */ | ||
| 195 | #define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT 3 | ||
| 196 | #define AM33XX_CLKACTIVITY_MMC_FCLK_MASK (1 << 3) | ||
| 197 | |||
| 198 | /* Used by CM_MPU_CLKSTCTRL */ | ||
| 199 | #define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT 2 | ||
| 200 | #define AM33XX_CLKACTIVITY_MPU_CLK_MASK (1 << 2) | ||
| 201 | |||
| 202 | /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */ | ||
| 203 | #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT 4 | ||
| 204 | #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK (1 << 4) | ||
| 205 | |||
| 206 | /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */ | ||
| 207 | #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT 5 | ||
| 208 | #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK (1 << 5) | ||
| 209 | |||
| 210 | /* Used by CM_RTC_CLKSTCTRL */ | ||
| 211 | #define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT 9 | ||
| 212 | #define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK (1 << 9) | ||
| 213 | |||
| 214 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 215 | #define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT 25 | ||
| 216 | #define AM33XX_CLKACTIVITY_SPI_GCLK_MASK (1 << 25) | ||
| 217 | |||
| 218 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
| 219 | #define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT 3 | ||
| 220 | #define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK (1 << 3) | ||
| 221 | |||
| 222 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
| 223 | #define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT 10 | ||
| 224 | #define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK (1 << 10) | ||
| 225 | |||
| 226 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
| 227 | #define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT 13 | ||
| 228 | #define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK (1 << 13) | ||
| 229 | |||
| 230 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 231 | #define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT 14 | ||
| 232 | #define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK (1 << 14) | ||
| 233 | |||
| 234 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 235 | #define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT 15 | ||
| 236 | #define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK (1 << 15) | ||
| 237 | |||
| 238 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 239 | #define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT 16 | ||
| 240 | #define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK (1 << 16) | ||
| 241 | |||
| 242 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 243 | #define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT 27 | ||
| 244 | #define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK (1 << 27) | ||
| 245 | |||
| 246 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 247 | #define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT 28 | ||
| 248 | #define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK (1 << 28) | ||
| 249 | |||
| 250 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 251 | #define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT 13 | ||
| 252 | #define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK (1 << 13) | ||
| 253 | |||
| 254 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
| 255 | #define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT 12 | ||
| 256 | #define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK (1 << 12) | ||
| 257 | |||
| 258 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 259 | #define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT 10 | ||
| 260 | #define AM33XX_CLKACTIVITY_UART_GFCLK_MASK (1 << 10) | ||
| 261 | |||
| 262 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
| 263 | #define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT 9 | ||
| 264 | #define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK (1 << 9) | ||
| 265 | |||
| 266 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
| 267 | #define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT 4 | ||
| 268 | #define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK (1 << 4) | ||
| 269 | |||
| 270 | /* Used by CLKSEL_GFX_FCLK */ | ||
| 271 | #define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT 0 | ||
| 272 | #define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK (1 << 0) | ||
| 273 | |||
| 274 | /* Used by CM_CLKOUT_CTRL */ | ||
| 275 | #define AM33XX_CLKOUT2DIV_SHIFT 3 | ||
| 276 | #define AM33XX_CLKOUT2DIV_MASK (0x05 << 3) | ||
| 277 | |||
| 278 | /* Used by CM_CLKOUT_CTRL */ | ||
| 279 | #define AM33XX_CLKOUT2EN_SHIFT 7 | ||
| 280 | #define AM33XX_CLKOUT2EN_MASK (1 << 7) | ||
| 281 | |||
| 282 | /* Used by CM_CLKOUT_CTRL */ | ||
| 283 | #define AM33XX_CLKOUT2SOURCE_SHIFT 0 | ||
| 284 | #define AM33XX_CLKOUT2SOURCE_MASK (0x02 << 0) | ||
| 285 | |||
| 286 | /* | ||
| 287 | * Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK, | ||
| 288 | * CLKSEL_TIMER3_CLK, CLKSEL_TIMER4_CLK, CLKSEL_TIMER5_CLK, CLKSEL_TIMER6_CLK, | ||
| 289 | * CLKSEL_TIMER7_CLK | ||
| 290 | */ | ||
| 291 | #define AM33XX_CLKSEL_SHIFT 0 | ||
| 292 | #define AM33XX_CLKSEL_MASK (0x01 << 0) | ||
| 293 | |||
| 294 | /* | ||
| 295 | * Renamed from CLKSEL Used by CLKSEL_PRUSS_OCP_CLK, CLKSEL_WDT1_CLK, | ||
| 296 | * CM_CPTS_RFT_CLKSEL | ||
| 297 | */ | ||
| 298 | #define AM33XX_CLKSEL_0_0_SHIFT 0 | ||
| 299 | #define AM33XX_CLKSEL_0_0_MASK (1 << 0) | ||
| 300 | |||
| 301 | #define AM33XX_CLKSEL_0_1_SHIFT 0 | ||
| 302 | #define AM33XX_CLKSEL_0_1_MASK (3 << 0) | ||
| 303 | |||
| 304 | /* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */ | ||
| 305 | #define AM33XX_CLKSEL_0_2_SHIFT 0 | ||
| 306 | #define AM33XX_CLKSEL_0_2_MASK (7 << 0) | ||
| 307 | |||
| 308 | /* Used by CLKSEL_GFX_FCLK */ | ||
| 309 | #define AM33XX_CLKSEL_GFX_FCLK_SHIFT 1 | ||
| 310 | #define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1) | ||
| 311 | |||
| 312 | /* | ||
| 313 | * Used by CM_MPU_CLKSTCTRL, CM_RTC_CLKSTCTRL, CM_PER_CLK_24MHZ_CLKSTCTRL, | ||
| 314 | * CM_PER_CPSW_CLKSTCTRL, CM_PER_PRUSS_CLKSTCTRL, CM_PER_L3S_CLKSTCTRL, | ||
| 315 | * CM_PER_L3_CLKSTCTRL, CM_PER_L4FW_CLKSTCTRL, CM_PER_L4HS_CLKSTCTRL, | ||
| 316 | * CM_PER_L4LS_CLKSTCTRL, CM_PER_LCDC_CLKSTCTRL, CM_PER_OCPWP_L3_CLKSTCTRL, | ||
| 317 | * CM_L3_AON_CLKSTCTRL, CM_L4_WKUP_AON_CLKSTCTRL, CM_WKUP_CLKSTCTRL, | ||
| 318 | * CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL | ||
| 319 | */ | ||
| 320 | #define AM33XX_CLKTRCTRL_SHIFT 0 | ||
| 321 | #define AM33XX_CLKTRCTRL_MASK (0x3 << 0) | ||
| 322 | |||
| 323 | /* | ||
| 324 | * Used by CM_SSC_DELTAMSTEP_DPLL_CORE, CM_SSC_DELTAMSTEP_DPLL_DDR, | ||
| 325 | * CM_SSC_DELTAMSTEP_DPLL_DISP, CM_SSC_DELTAMSTEP_DPLL_MPU, | ||
| 326 | * CM_SSC_DELTAMSTEP_DPLL_PER | ||
| 327 | */ | ||
| 328 | #define AM33XX_DELTAMSTEP_SHIFT 0 | ||
| 329 | #define AM33XX_DELTAMSTEP_MASK (0x19 << 0) | ||
| 330 | |||
| 331 | /* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */ | ||
| 332 | #define AM33XX_DPLL_BYP_CLKSEL_SHIFT 23 | ||
| 333 | #define AM33XX_DPLL_BYP_CLKSEL_MASK (1 << 23) | ||
| 334 | |||
| 335 | /* Used by CM_CLKDCOLDO_DPLL_PER */ | ||
| 336 | #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 | ||
| 337 | #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) | ||
| 338 | |||
| 339 | /* Used by CM_CLKDCOLDO_DPLL_PER */ | ||
| 340 | #define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT 12 | ||
| 341 | #define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK (1 << 12) | ||
| 342 | |||
| 343 | /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */ | ||
| 344 | #define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0 | ||
| 345 | #define AM33XX_DPLL_CLKOUT_DIV_MASK (0x1f << 0) | ||
| 346 | |||
| 347 | /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */ | ||
| 348 | #define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT 0 | ||
| 349 | #define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x06 << 0) | ||
| 350 | |||
| 351 | /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */ | ||
| 352 | #define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT 5 | ||
| 353 | #define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) | ||
| 354 | |||
| 355 | /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */ | ||
| 356 | #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT 7 | ||
| 357 | #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK (1 << 7) | ||
| 358 | |||
| 359 | /* | ||
| 360 | * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU, | ||
| 361 | * CM_DIV_M2_DPLL_PER | ||
| 362 | */ | ||
| 363 | #define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 | ||
| 364 | #define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) | ||
| 365 | |||
| 366 | /* | ||
| 367 | * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, | ||
| 368 | * CM_CLKSEL_DPLL_MPU | ||
| 369 | */ | ||
| 370 | #define AM33XX_DPLL_DIV_SHIFT 0 | ||
| 371 | #define AM33XX_DPLL_DIV_MASK (0x7f << 0) | ||
| 372 | |||
| 373 | #define AM33XX_DPLL_PER_DIV_MASK (0xff << 0) | ||
| 374 | |||
| 375 | /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */ | ||
| 376 | #define AM33XX_DPLL_DIV_0_7_SHIFT 0 | ||
| 377 | #define AM33XX_DPLL_DIV_0_7_MASK (0x07 << 0) | ||
| 378 | |||
| 379 | /* | ||
| 380 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, | ||
| 381 | * CM_CLKMODE_DPLL_MPU | ||
| 382 | */ | ||
| 383 | #define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT 8 | ||
| 384 | #define AM33XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8) | ||
| 385 | |||
| 386 | /* | ||
| 387 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, | ||
| 388 | * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER | ||
| 389 | */ | ||
| 390 | #define AM33XX_DPLL_EN_SHIFT 0 | ||
| 391 | #define AM33XX_DPLL_EN_MASK (0x7 << 0) | ||
| 392 | |||
| 393 | /* | ||
| 394 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, | ||
| 395 | * CM_CLKMODE_DPLL_MPU | ||
| 396 | */ | ||
| 397 | #define AM33XX_DPLL_LPMODE_EN_SHIFT 10 | ||
| 398 | #define AM33XX_DPLL_LPMODE_EN_MASK (1 << 10) | ||
| 399 | |||
| 400 | /* | ||
| 401 | * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, | ||
| 402 | * CM_CLKSEL_DPLL_MPU | ||
| 403 | */ | ||
| 404 | #define AM33XX_DPLL_MULT_SHIFT 8 | ||
| 405 | #define AM33XX_DPLL_MULT_MASK (0x7ff << 8) | ||
| 406 | |||
| 407 | /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */ | ||
| 408 | #define AM33XX_DPLL_MULT_PERIPH_SHIFT 8 | ||
| 409 | #define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8) | ||
| 410 | |||
| 411 | /* | ||
| 412 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, | ||
| 413 | * CM_CLKMODE_DPLL_MPU | ||
| 414 | */ | ||
| 415 | #define AM33XX_DPLL_REGM4XEN_SHIFT 11 | ||
| 416 | #define AM33XX_DPLL_REGM4XEN_MASK (1 << 11) | ||
| 417 | |||
| 418 | /* Used by CM_CLKSEL_DPLL_PERIPH */ | ||
| 419 | #define AM33XX_DPLL_SD_DIV_SHIFT 24 | ||
| 420 | #define AM33XX_DPLL_SD_DIV_MASK (24, 31) | ||
| 421 | |||
| 422 | /* | ||
| 423 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, | ||
| 424 | * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER | ||
| 425 | */ | ||
| 426 | #define AM33XX_DPLL_SSC_ACK_SHIFT 13 | ||
| 427 | #define AM33XX_DPLL_SSC_ACK_MASK (1 << 13) | ||
| 428 | |||
| 429 | /* | ||
| 430 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, | ||
| 431 | * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER | ||
| 432 | */ | ||
| 433 | #define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT 14 | ||
| 434 | #define AM33XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) | ||
| 435 | |||
| 436 | /* | ||
| 437 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, | ||
| 438 | * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER | ||
| 439 | */ | ||
| 440 | #define AM33XX_DPLL_SSC_EN_SHIFT 12 | ||
| 441 | #define AM33XX_DPLL_SSC_EN_MASK (1 << 12) | ||
| 442 | |||
| 443 | /* Used by CM_DIV_M4_DPLL_CORE */ | ||
| 444 | #define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 | ||
| 445 | #define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) | ||
| 446 | |||
| 447 | /* Used by CM_DIV_M4_DPLL_CORE */ | ||
| 448 | #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 | ||
| 449 | #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) | ||
| 450 | |||
| 451 | /* Used by CM_DIV_M4_DPLL_CORE */ | ||
| 452 | #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 | ||
| 453 | #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) | ||
| 454 | |||
| 455 | /* Used by CM_DIV_M4_DPLL_CORE */ | ||
| 456 | #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 | ||
| 457 | #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) | ||
| 458 | |||
| 459 | /* Used by CM_DIV_M5_DPLL_CORE */ | ||
| 460 | #define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 | ||
| 461 | #define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) | ||
| 462 | |||
| 463 | /* Used by CM_DIV_M5_DPLL_CORE */ | ||
| 464 | #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 | ||
| 465 | #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) | ||
| 466 | |||
| 467 | /* Used by CM_DIV_M5_DPLL_CORE */ | ||
| 468 | #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 | ||
| 469 | #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) | ||
| 470 | |||
| 471 | /* Used by CM_DIV_M5_DPLL_CORE */ | ||
| 472 | #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 | ||
| 473 | #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) | ||
| 474 | |||
| 475 | /* Used by CM_DIV_M6_DPLL_CORE */ | ||
| 476 | #define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 | ||
| 477 | #define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x04 << 0) | ||
| 478 | |||
| 479 | /* Used by CM_DIV_M6_DPLL_CORE */ | ||
| 480 | #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 | ||
| 481 | #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) | ||
| 482 | |||
| 483 | /* Used by CM_DIV_M6_DPLL_CORE */ | ||
| 484 | #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 | ||
| 485 | #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) | ||
| 486 | |||
| 487 | /* Used by CM_DIV_M6_DPLL_CORE */ | ||
| 488 | #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 | ||
| 489 | #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) | ||
| 490 | |||
| 491 | /* | ||
| 492 | * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL, | ||
| 493 | * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, | ||
| 494 | * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL, | ||
| 495 | * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL, | ||
| 496 | * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL, | ||
| 497 | * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL, | ||
| 498 | * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL, | ||
| 499 | * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL, | ||
| 500 | * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL, | ||
| 501 | * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL, | ||
| 502 | * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL, | ||
| 503 | * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL, | ||
| 504 | * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL, | ||
| 505 | * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL, | ||
| 506 | * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL, | ||
| 507 | * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL, | ||
| 508 | * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL, | ||
| 509 | * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL, | ||
| 510 | * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL, | ||
| 511 | * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL, | ||
| 512 | * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL, | ||
| 513 | * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL, | ||
| 514 | * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL, | ||
| 515 | * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL, | ||
| 516 | * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL, | ||
| 517 | * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL, | ||
| 518 | * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL, | ||
| 519 | * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL, | ||
| 520 | * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL, | ||
| 521 | * CM_WKUP_WDT1_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL, | ||
| 522 | * CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL | ||
| 523 | */ | ||
| 524 | #define AM33XX_IDLEST_SHIFT 16 | ||
| 525 | #define AM33XX_IDLEST_MASK (0x3 << 16) | ||
| 526 | #define AM33XX_IDLEST_VAL 0x3 | ||
| 527 | |||
| 528 | /* Used by CM_MAC_CLKSEL */ | ||
| 529 | #define AM33XX_MII_CLK_SEL_SHIFT 2 | ||
| 530 | #define AM33XX_MII_CLK_SEL_MASK (1 << 2) | ||
| 531 | |||
| 532 | /* | ||
| 533 | * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR, | ||
| 534 | * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU, | ||
| 535 | * CM_SSC_MODFREQDIV_DPLL_PER | ||
| 536 | */ | ||
| 537 | #define AM33XX_MODFREQDIV_EXPONENT_SHIFT 8 | ||
| 538 | #define AM33XX_MODFREQDIV_EXPONENT_MASK (0x10 << 8) | ||
| 539 | |||
| 540 | /* | ||
| 541 | * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR, | ||
| 542 | * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU, | ||
| 543 | * CM_SSC_MODFREQDIV_DPLL_PER | ||
| 544 | */ | ||
| 545 | #define AM33XX_MODFREQDIV_MANTISSA_SHIFT 0 | ||
| 546 | #define AM33XX_MODFREQDIV_MANTISSA_MASK (0x06 << 0) | ||
| 547 | |||
| 548 | /* | ||
| 549 | * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL, | ||
| 550 | * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, | ||
| 551 | * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL, | ||
| 552 | * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL, | ||
| 553 | * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL, | ||
| 554 | * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL, | ||
| 555 | * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL, | ||
| 556 | * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL, | ||
| 557 | * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL, | ||
| 558 | * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL, | ||
| 559 | * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL, | ||
| 560 | * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL, | ||
| 561 | * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL, | ||
| 562 | * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL, | ||
| 563 | * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL, | ||
| 564 | * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL, | ||
| 565 | * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL, | ||
| 566 | * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL, | ||
| 567 | * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL, | ||
| 568 | * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL, | ||
| 569 | * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL, | ||
| 570 | * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL, | ||
| 571 | * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL, | ||
| 572 | * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL, | ||
| 573 | * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL, | ||
| 574 | * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL, | ||
| 575 | * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL, | ||
| 576 | * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL, | ||
| 577 | * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL, | ||
| 578 | * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, | ||
| 579 | * CM_GFX_GFX_CLKCTRL, CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, | ||
| 580 | * CM_CEFUSE_CEFUSE_CLKCTRL | ||
| 581 | */ | ||
| 582 | #define AM33XX_MODULEMODE_SHIFT 0 | ||
| 583 | #define AM33XX_MODULEMODE_MASK (0x3 << 0) | ||
| 584 | |||
| 585 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ | ||
| 586 | #define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30 | ||
| 587 | #define AM33XX_OPTCLK_DEBUG_CLKA_MASK (1 << 30) | ||
| 588 | |||
| 589 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ | ||
| 590 | #define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19 | ||
| 591 | #define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK (1 << 19) | ||
| 592 | |||
| 593 | /* Used by CM_WKUP_GPIO0_CLKCTRL */ | ||
| 594 | #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18 | ||
| 595 | #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK (1 << 18) | ||
| 596 | |||
| 597 | /* Used by CM_PER_GPIO1_CLKCTRL */ | ||
| 598 | #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18 | ||
| 599 | #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK (1 << 18) | ||
| 600 | |||
| 601 | /* Used by CM_PER_GPIO2_CLKCTRL */ | ||
| 602 | #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18 | ||
| 603 | #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK (1 << 18) | ||
| 604 | |||
| 605 | /* Used by CM_PER_GPIO3_CLKCTRL */ | ||
| 606 | #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18 | ||
| 607 | #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK (1 << 18) | ||
| 608 | |||
| 609 | /* Used by CM_PER_GPIO4_CLKCTRL */ | ||
| 610 | #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT 18 | ||
| 611 | #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK (1 << 18) | ||
| 612 | |||
| 613 | /* Used by CM_PER_GPIO5_CLKCTRL */ | ||
| 614 | #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT 18 | ||
| 615 | #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK (1 << 18) | ||
| 616 | |||
| 617 | /* Used by CM_PER_GPIO6_CLKCTRL */ | ||
| 618 | #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT 18 | ||
| 619 | #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK (1 << 18) | ||
| 620 | |||
| 621 | /* | ||
| 622 | * Used by CM_MPU_MPU_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, CM_PER_PRUSS_CLKCTRL, | ||
| 623 | * CM_PER_IEEE5000_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MLB_CLKCTRL, | ||
| 624 | * CM_PER_MSTR_EXPS_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL, | ||
| 625 | * CM_PER_SPARE_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL, | ||
| 626 | * CM_PER_TPTC2_CLKCTRL, CM_PER_USB0_CLKCTRL, CM_WKUP_DEBUGSS_CLKCTRL, | ||
| 627 | * CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL | ||
| 628 | */ | ||
| 629 | #define AM33XX_STBYST_SHIFT 18 | ||
| 630 | #define AM33XX_STBYST_MASK (1 << 18) | ||
| 631 | |||
| 632 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ | ||
| 633 | #define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27 | ||
| 634 | #define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x29 << 27) | ||
| 635 | |||
| 636 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ | ||
| 637 | #define AM33XX_STM_PMD_CLKSEL_SHIFT 22 | ||
| 638 | #define AM33XX_STM_PMD_CLKSEL_MASK (0x23 << 22) | ||
| 639 | |||
| 640 | /* | ||
| 641 | * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP, | ||
| 642 | * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER | ||
| 643 | */ | ||
| 644 | #define AM33XX_ST_DPLL_CLK_SHIFT 0 | ||
| 645 | #define AM33XX_ST_DPLL_CLK_MASK (1 << 0) | ||
| 646 | |||
| 647 | /* Used by CM_CLKDCOLDO_DPLL_PER */ | ||
| 648 | #define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8 | ||
| 649 | #define AM33XX_ST_DPLL_CLKDCOLDO_MASK (1 << 8) | ||
| 650 | |||
| 651 | /* | ||
| 652 | * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU, | ||
| 653 | * CM_DIV_M2_DPLL_PER | ||
| 654 | */ | ||
| 655 | #define AM33XX_ST_DPLL_CLKOUT_SHIFT 9 | ||
| 656 | #define AM33XX_ST_DPLL_CLKOUT_MASK (1 << 9) | ||
| 657 | |||
| 658 | /* Used by CM_DIV_M4_DPLL_CORE */ | ||
| 659 | #define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT 9 | ||
| 660 | #define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) | ||
| 661 | |||
| 662 | /* Used by CM_DIV_M5_DPLL_CORE */ | ||
| 663 | #define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT 9 | ||
| 664 | #define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) | ||
| 665 | |||
| 666 | /* Used by CM_DIV_M6_DPLL_CORE */ | ||
| 667 | #define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT 9 | ||
| 668 | #define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) | ||
| 669 | |||
| 670 | /* | ||
| 671 | * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP, | ||
| 672 | * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER | ||
| 673 | */ | ||
| 674 | #define AM33XX_ST_MN_BYPASS_SHIFT 8 | ||
| 675 | #define AM33XX_ST_MN_BYPASS_MASK (1 << 8) | ||
| 676 | |||
| 677 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ | ||
| 678 | #define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24 | ||
| 679 | #define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x26 << 24) | ||
| 680 | |||
| 681 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ | ||
| 682 | #define AM33XX_TRC_PMD_CLKSEL_SHIFT 20 | ||
| 683 | #define AM33XX_TRC_PMD_CLKSEL_MASK (0x21 << 20) | ||
| 684 | |||
| 685 | /* Used by CONTROL_SEC_CLK_CTRL */ | ||
| 686 | #define AM33XX_TIMER0_CLKSEL_MASK (0x3 << 4) | ||
| 687 | #endif | ||
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index 8083a8cdc55f..766338fe4d34 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h | |||
| @@ -169,8 +169,6 @@ | |||
| 169 | /* AM35XX specific CM_ICLKEN1_CORE bits */ | 169 | /* AM35XX specific CM_ICLKEN1_CORE bits */ |
| 170 | #define AM35XX_EN_IPSS_MASK (1 << 4) | 170 | #define AM35XX_EN_IPSS_MASK (1 << 4) |
| 171 | #define AM35XX_EN_IPSS_SHIFT 4 | 171 | #define AM35XX_EN_IPSS_SHIFT 4 |
| 172 | #define AM35XX_EN_UART4_MASK (1 << 23) | ||
| 173 | #define AM35XX_EN_UART4_SHIFT 23 | ||
| 174 | 172 | ||
| 175 | /* CM_ICLKEN2_CORE */ | 173 | /* CM_ICLKEN2_CORE */ |
| 176 | #define OMAP3430_EN_PKA_MASK (1 << 4) | 174 | #define OMAP3430_EN_PKA_MASK (1 << 4) |
| @@ -207,6 +205,8 @@ | |||
| 207 | #define OMAP3430_ST_DES2_MASK (1 << 26) | 205 | #define OMAP3430_ST_DES2_MASK (1 << 26) |
| 208 | #define OMAP3430_ST_MSPRO_SHIFT 23 | 206 | #define OMAP3430_ST_MSPRO_SHIFT 23 |
| 209 | #define OMAP3430_ST_MSPRO_MASK (1 << 23) | 207 | #define OMAP3430_ST_MSPRO_MASK (1 << 23) |
| 208 | #define AM35XX_ST_UART4_SHIFT 23 | ||
| 209 | #define AM35XX_ST_UART4_MASK (1 << 23) | ||
| 210 | #define OMAP3430_ST_HDQ_SHIFT 22 | 210 | #define OMAP3430_ST_HDQ_SHIFT 22 |
| 211 | #define OMAP3430_ST_HDQ_MASK (1 << 22) | 211 | #define OMAP3430_ST_HDQ_MASK (1 << 22) |
| 212 | #define OMAP3430ES1_ST_FAC_SHIFT 8 | 212 | #define OMAP3430ES1_ST_FAC_SHIFT 8 |
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c new file mode 100644 index 000000000000..13f56eafef03 --- /dev/null +++ b/arch/arm/mach-omap2/cm33xx.c | |||
| @@ -0,0 +1,313 @@ | |||
| 1 | /* | ||
| 2 | * AM33XX CM functions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 5 | * Vaibhav Hiremath <hvaibhav@ti.com> | ||
| 6 | * | ||
| 7 | * Reference taken from from OMAP4 cminst44xx.c | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or | ||
| 10 | * modify it under the terms of the GNU General Public License as | ||
| 11 | * published by the Free Software Foundation version 2. | ||
| 12 | * | ||
| 13 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
| 14 | * kind, whether express or implied; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/kernel.h> | ||
| 20 | #include <linux/types.h> | ||
| 21 | #include <linux/errno.h> | ||
| 22 | #include <linux/err.h> | ||
| 23 | #include <linux/io.h> | ||
| 24 | |||
| 25 | #include <plat/common.h> | ||
| 26 | |||
| 27 | #include "cm.h" | ||
| 28 | #include "cm33xx.h" | ||
| 29 | #include "cm-regbits-34xx.h" | ||
| 30 | #include "cm-regbits-33xx.h" | ||
| 31 | #include "prm33xx.h" | ||
| 32 | |||
| 33 | /* | ||
| 34 | * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield: | ||
| 35 | * | ||
| 36 | * 0x0 func: Module is fully functional, including OCP | ||
| 37 | * 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep | ||
| 38 | * abortion | ||
| 39 | * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if | ||
| 40 | * using separate functional clock | ||
| 41 | * 0x3 disabled: Module is disabled and cannot be accessed | ||
| 42 | * | ||
| 43 | */ | ||
| 44 | #define CLKCTRL_IDLEST_FUNCTIONAL 0x0 | ||
| 45 | #define CLKCTRL_IDLEST_INTRANSITION 0x1 | ||
| 46 | #define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2 | ||
| 47 | #define CLKCTRL_IDLEST_DISABLED 0x3 | ||
| 48 | |||
| 49 | /* Private functions */ | ||
| 50 | |||
| 51 | /* Read a register in a CM instance */ | ||
| 52 | static inline u32 am33xx_cm_read_reg(s16 inst, u16 idx) | ||
| 53 | { | ||
| 54 | return __raw_readl(cm_base + inst + idx); | ||
| 55 | } | ||
| 56 | |||
| 57 | /* Write into a register in a CM */ | ||
| 58 | static inline void am33xx_cm_write_reg(u32 val, s16 inst, u16 idx) | ||
| 59 | { | ||
| 60 | __raw_writel(val, cm_base + inst + idx); | ||
| 61 | } | ||
| 62 | |||
| 63 | /* Read-modify-write a register in CM */ | ||
| 64 | static inline u32 am33xx_cm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx) | ||
| 65 | { | ||
| 66 | u32 v; | ||
| 67 | |||
| 68 | v = am33xx_cm_read_reg(inst, idx); | ||
| 69 | v &= ~mask; | ||
| 70 | v |= bits; | ||
| 71 | am33xx_cm_write_reg(v, inst, idx); | ||
| 72 | |||
| 73 | return v; | ||
| 74 | } | ||
| 75 | |||
| 76 | static inline u32 am33xx_cm_set_reg_bits(u32 bits, s16 inst, s16 idx) | ||
| 77 | { | ||
| 78 | return am33xx_cm_rmw_reg_bits(bits, bits, inst, idx); | ||
| 79 | } | ||
| 80 | |||
| 81 | static inline u32 am33xx_cm_clear_reg_bits(u32 bits, s16 inst, s16 idx) | ||
| 82 | { | ||
| 83 | return am33xx_cm_rmw_reg_bits(bits, 0x0, inst, idx); | ||
| 84 | } | ||
| 85 | |||
| 86 | static inline u32 am33xx_cm_read_reg_bits(u16 inst, s16 idx, u32 mask) | ||
| 87 | { | ||
| 88 | u32 v; | ||
| 89 | |||
| 90 | v = am33xx_cm_read_reg(inst, idx); | ||
| 91 | v &= mask; | ||
| 92 | v >>= __ffs(mask); | ||
| 93 | |||
| 94 | return v; | ||
| 95 | } | ||
| 96 | |||
| 97 | /** | ||
| 98 | * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield | ||
| 99 | * @inst: CM instance register offset (*_INST macro) | ||
| 100 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
| 101 | * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) | ||
| 102 | * | ||
| 103 | * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to | ||
| 104 | * bit 0. | ||
| 105 | */ | ||
| 106 | static u32 _clkctrl_idlest(u16 inst, s16 cdoffs, u16 clkctrl_offs) | ||
| 107 | { | ||
| 108 | u32 v = am33xx_cm_read_reg(inst, clkctrl_offs); | ||
| 109 | v &= AM33XX_IDLEST_MASK; | ||
| 110 | v >>= AM33XX_IDLEST_SHIFT; | ||
| 111 | return v; | ||
| 112 | } | ||
| 113 | |||
| 114 | /** | ||
| 115 | * _is_module_ready - can module registers be accessed without causing an abort? | ||
| 116 | * @inst: CM instance register offset (*_INST macro) | ||
| 117 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
| 118 | * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) | ||
| 119 | * | ||
| 120 | * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either | ||
| 121 | * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise. | ||
| 122 | */ | ||
| 123 | static bool _is_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs) | ||
| 124 | { | ||
| 125 | u32 v; | ||
| 126 | |||
| 127 | v = _clkctrl_idlest(inst, cdoffs, clkctrl_offs); | ||
| 128 | |||
| 129 | return (v == CLKCTRL_IDLEST_FUNCTIONAL || | ||
| 130 | v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false; | ||
| 131 | } | ||
| 132 | |||
| 133 | /** | ||
| 134 | * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield | ||
| 135 | * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted) | ||
| 136 | * @inst: CM instance register offset (*_INST macro) | ||
| 137 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
| 138 | * | ||
| 139 | * @c must be the unshifted value for CLKTRCTRL - i.e., this function | ||
| 140 | * will handle the shift itself. | ||
| 141 | */ | ||
| 142 | static void _clktrctrl_write(u8 c, s16 inst, u16 cdoffs) | ||
| 143 | { | ||
| 144 | u32 v; | ||
| 145 | |||
| 146 | v = am33xx_cm_read_reg(inst, cdoffs); | ||
| 147 | v &= ~AM33XX_CLKTRCTRL_MASK; | ||
| 148 | v |= c << AM33XX_CLKTRCTRL_SHIFT; | ||
| 149 | am33xx_cm_write_reg(v, inst, cdoffs); | ||
| 150 | } | ||
| 151 | |||
| 152 | /* Public functions */ | ||
| 153 | |||
| 154 | /** | ||
| 155 | * am33xx_cm_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode? | ||
| 156 | * @inst: CM instance register offset (*_INST macro) | ||
| 157 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
| 158 | * | ||
| 159 | * Returns true if the clockdomain referred to by (@inst, @cdoffs) | ||
| 160 | * is in hardware-supervised idle mode, or 0 otherwise. | ||
| 161 | */ | ||
| 162 | bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs) | ||
| 163 | { | ||
| 164 | u32 v; | ||
| 165 | |||
| 166 | v = am33xx_cm_read_reg(inst, cdoffs); | ||
| 167 | v &= AM33XX_CLKTRCTRL_MASK; | ||
| 168 | v >>= AM33XX_CLKTRCTRL_SHIFT; | ||
| 169 | |||
| 170 | return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false; | ||
| 171 | } | ||
| 172 | |||
| 173 | /** | ||
| 174 | * am33xx_cm_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode | ||
| 175 | * @inst: CM instance register offset (*_INST macro) | ||
| 176 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
| 177 | * | ||
| 178 | * Put a clockdomain referred to by (@inst, @cdoffs) into | ||
| 179 | * hardware-supervised idle mode. No return value. | ||
| 180 | */ | ||
| 181 | void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs) | ||
| 182 | { | ||
| 183 | _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs); | ||
| 184 | } | ||
| 185 | |||
| 186 | /** | ||
| 187 | * am33xx_cm_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode | ||
| 188 | * @inst: CM instance register offset (*_INST macro) | ||
| 189 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
| 190 | * | ||
| 191 | * Put a clockdomain referred to by (@inst, @cdoffs) into | ||
| 192 | * software-supervised idle mode, i.e., controlled manually by the | ||
| 193 | * Linux OMAP clockdomain code. No return value. | ||
| 194 | */ | ||
| 195 | void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs) | ||
| 196 | { | ||
| 197 | _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs); | ||
| 198 | } | ||
| 199 | |||
| 200 | /** | ||
| 201 | * am33xx_cm_clkdm_force_sleep - try to put a clockdomain into idle | ||
| 202 | * @inst: CM instance register offset (*_INST macro) | ||
| 203 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
| 204 | * | ||
| 205 | * Put a clockdomain referred to by (@inst, @cdoffs) into idle | ||
| 206 | * No return value. | ||
| 207 | */ | ||
| 208 | void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs) | ||
| 209 | { | ||
| 210 | _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs); | ||
| 211 | } | ||
| 212 | |||
| 213 | /** | ||
| 214 | * am33xx_cm_clkdm_force_wakeup - try to take a clockdomain out of idle | ||
| 215 | * @inst: CM instance register offset (*_INST macro) | ||
| 216 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
| 217 | * | ||
| 218 | * Take a clockdomain referred to by (@inst, @cdoffs) out of idle, | ||
| 219 | * waking it up. No return value. | ||
| 220 | */ | ||
| 221 | void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs) | ||
| 222 | { | ||
| 223 | _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs); | ||
| 224 | } | ||
| 225 | |||
| 226 | /* | ||
| 227 | * | ||
| 228 | */ | ||
| 229 | |||
| 230 | /** | ||
| 231 | * am33xx_cm_wait_module_ready - wait for a module to be in 'func' state | ||
| 232 | * @inst: CM instance register offset (*_INST macro) | ||
| 233 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
| 234 | * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) | ||
| 235 | * | ||
| 236 | * Wait for the module IDLEST to be functional. If the idle state is in any | ||
| 237 | * the non functional state (trans, idle or disabled), module and thus the | ||
| 238 | * sysconfig cannot be accessed and will probably lead to an "imprecise | ||
| 239 | * external abort" | ||
| 240 | */ | ||
| 241 | int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs) | ||
| 242 | { | ||
| 243 | int i = 0; | ||
| 244 | |||
| 245 | if (!clkctrl_offs) | ||
| 246 | return 0; | ||
| 247 | |||
| 248 | omap_test_timeout(_is_module_ready(inst, cdoffs, clkctrl_offs), | ||
| 249 | MAX_MODULE_READY_TIME, i); | ||
| 250 | |||
| 251 | return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; | ||
| 252 | } | ||
| 253 | |||
| 254 | /** | ||
| 255 | * am33xx_cm_wait_module_idle - wait for a module to be in 'disabled' | ||
| 256 | * state | ||
| 257 | * @inst: CM instance register offset (*_INST macro) | ||
| 258 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
| 259 | * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) | ||
| 260 | * | ||
| 261 | * Wait for the module IDLEST to be disabled. Some PRCM transition, | ||
| 262 | * like reset assertion or parent clock de-activation must wait the | ||
| 263 | * module to be fully disabled. | ||
| 264 | */ | ||
| 265 | int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, u16 clkctrl_offs) | ||
| 266 | { | ||
| 267 | int i = 0; | ||
| 268 | |||
| 269 | if (!clkctrl_offs) | ||
| 270 | return 0; | ||
| 271 | |||
| 272 | omap_test_timeout((_clkctrl_idlest(inst, cdoffs, clkctrl_offs) == | ||
| 273 | CLKCTRL_IDLEST_DISABLED), | ||
| 274 | MAX_MODULE_READY_TIME, i); | ||
| 275 | |||
| 276 | return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; | ||
| 277 | } | ||
| 278 | |||
| 279 | /** | ||
| 280 | * am33xx_cm_module_enable - Enable the modulemode inside CLKCTRL | ||
| 281 | * @mode: Module mode (SW or HW) | ||
| 282 | * @inst: CM instance register offset (*_INST macro) | ||
| 283 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
| 284 | * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) | ||
| 285 | * | ||
| 286 | * No return value. | ||
| 287 | */ | ||
| 288 | void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, u16 clkctrl_offs) | ||
| 289 | { | ||
| 290 | u32 v; | ||
| 291 | |||
| 292 | v = am33xx_cm_read_reg(inst, clkctrl_offs); | ||
| 293 | v &= ~AM33XX_MODULEMODE_MASK; | ||
| 294 | v |= mode << AM33XX_MODULEMODE_SHIFT; | ||
| 295 | am33xx_cm_write_reg(v, inst, clkctrl_offs); | ||
| 296 | } | ||
| 297 | |||
| 298 | /** | ||
| 299 | * am33xx_cm_module_disable - Disable the module inside CLKCTRL | ||
| 300 | * @inst: CM instance register offset (*_INST macro) | ||
| 301 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
| 302 | * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) | ||
| 303 | * | ||
| 304 | * No return value. | ||
| 305 | */ | ||
| 306 | void am33xx_cm_module_disable(u16 inst, s16 cdoffs, u16 clkctrl_offs) | ||
| 307 | { | ||
| 308 | u32 v; | ||
| 309 | |||
| 310 | v = am33xx_cm_read_reg(inst, clkctrl_offs); | ||
| 311 | v &= ~AM33XX_MODULEMODE_MASK; | ||
| 312 | am33xx_cm_write_reg(v, inst, clkctrl_offs); | ||
| 313 | } | ||
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h new file mode 100644 index 000000000000..5fa0b62e1a79 --- /dev/null +++ b/arch/arm/mach-omap2/cm33xx.h | |||
| @@ -0,0 +1,420 @@ | |||
| 1 | /* | ||
| 2 | * AM33XX CM offset macros | ||
| 3 | * | ||
| 4 | * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 5 | * Vaibhav Hiremath <hvaibhav@ti.com> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or | ||
| 8 | * modify it under the terms of the GNU General Public License as | ||
| 9 | * published by the Free Software Foundation version 2. | ||
| 10 | * | ||
| 11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
| 12 | * kind, whether express or implied; without even the implied warranty | ||
| 13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H | ||
| 18 | #define __ARCH_ARM_MACH_OMAP2_CM_33XX_H | ||
| 19 | |||
| 20 | #include <linux/delay.h> | ||
| 21 | #include <linux/errno.h> | ||
| 22 | #include <linux/err.h> | ||
| 23 | #include <linux/io.h> | ||
| 24 | |||
| 25 | #include "common.h" | ||
| 26 | |||
| 27 | #include "cm.h" | ||
| 28 | #include "cm-regbits-33xx.h" | ||
| 29 | #include "cm33xx.h" | ||
| 30 | |||
| 31 | /* CM base address */ | ||
| 32 | #define AM33XX_CM_BASE 0x44e00000 | ||
| 33 | |||
| 34 | #define AM33XX_CM_REGADDR(inst, reg) \ | ||
| 35 | AM33XX_L4_WK_IO_ADDRESS(AM33XX_CM_BASE + (inst) + (reg)) | ||
| 36 | |||
| 37 | /* CM instances */ | ||
| 38 | #define AM33XX_CM_PER_MOD 0x0000 | ||
| 39 | #define AM33XX_CM_WKUP_MOD 0x0400 | ||
| 40 | #define AM33XX_CM_DPLL_MOD 0x0500 | ||
| 41 | #define AM33XX_CM_MPU_MOD 0x0600 | ||
| 42 | #define AM33XX_CM_DEVICE_MOD 0x0700 | ||
| 43 | #define AM33XX_CM_RTC_MOD 0x0800 | ||
| 44 | #define AM33XX_CM_GFX_MOD 0x0900 | ||
| 45 | #define AM33XX_CM_CEFUSE_MOD 0x0A00 | ||
| 46 | |||
| 47 | /* CM */ | ||
| 48 | |||
| 49 | /* CM.PER_CM register offsets */ | ||
| 50 | #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000 | ||
| 51 | #define AM33XX_CM_PER_L4LS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0000) | ||
| 52 | #define AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET 0x0004 | ||
| 53 | #define AM33XX_CM_PER_L3S_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0004) | ||
| 54 | #define AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET 0x0008 | ||
| 55 | #define AM33XX_CM_PER_L4FW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0008) | ||
| 56 | #define AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET 0x000c | ||
| 57 | #define AM33XX_CM_PER_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x000c) | ||
| 58 | #define AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET 0x0014 | ||
| 59 | #define AM33XX_CM_PER_CPGMAC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0014) | ||
| 60 | #define AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET 0x0018 | ||
| 61 | #define AM33XX_CM_PER_LCDC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0018) | ||
| 62 | #define AM33XX_CM_PER_USB0_CLKCTRL_OFFSET 0x001c | ||
| 63 | #define AM33XX_CM_PER_USB0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x001c) | ||
| 64 | #define AM33XX_CM_PER_MLB_CLKCTRL_OFFSET 0x0020 | ||
| 65 | #define AM33XX_CM_PER_MLB_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0020) | ||
| 66 | #define AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET 0x0024 | ||
| 67 | #define AM33XX_CM_PER_TPTC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0024) | ||
| 68 | #define AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET 0x0028 | ||
| 69 | #define AM33XX_CM_PER_EMIF_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0028) | ||
| 70 | #define AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET 0x002c | ||
| 71 | #define AM33XX_CM_PER_OCMCRAM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x002c) | ||
| 72 | #define AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET 0x0030 | ||
| 73 | #define AM33XX_CM_PER_GPMC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0030) | ||
| 74 | #define AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET 0x0034 | ||
| 75 | #define AM33XX_CM_PER_MCASP0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0034) | ||
| 76 | #define AM33XX_CM_PER_UART5_CLKCTRL_OFFSET 0x0038 | ||
| 77 | #define AM33XX_CM_PER_UART5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0038) | ||
| 78 | #define AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET 0x003c | ||
| 79 | #define AM33XX_CM_PER_MMC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x003c) | ||
| 80 | #define AM33XX_CM_PER_ELM_CLKCTRL_OFFSET 0x0040 | ||
| 81 | #define AM33XX_CM_PER_ELM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0040) | ||
| 82 | #define AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET 0x0044 | ||
| 83 | #define AM33XX_CM_PER_I2C2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0044) | ||
| 84 | #define AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET 0x0048 | ||
| 85 | #define AM33XX_CM_PER_I2C1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0048) | ||
| 86 | #define AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET 0x004c | ||
| 87 | #define AM33XX_CM_PER_SPI0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x004c) | ||
| 88 | #define AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET 0x0050 | ||
| 89 | #define AM33XX_CM_PER_SPI1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0050) | ||
| 90 | #define AM33XX_CM_PER_SPI2_CLKCTRL_OFFSET 0x0054 | ||
| 91 | #define AM33XX_CM_PER_SPI2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0054) | ||
| 92 | #define AM33XX_CM_PER_SPI3_CLKCTRL_OFFSET 0x0058 | ||
| 93 | #define AM33XX_CM_PER_SPI3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0058) | ||
| 94 | #define AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET 0x0060 | ||
| 95 | #define AM33XX_CM_PER_L4LS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0060) | ||
| 96 | #define AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET 0x0064 | ||
| 97 | #define AM33XX_CM_PER_L4FW_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0064) | ||
| 98 | #define AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET 0x0068 | ||
| 99 | #define AM33XX_CM_PER_MCASP1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0068) | ||
| 100 | #define AM33XX_CM_PER_UART1_CLKCTRL_OFFSET 0x006c | ||
| 101 | #define AM33XX_CM_PER_UART1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x006c) | ||
| 102 | #define AM33XX_CM_PER_UART2_CLKCTRL_OFFSET 0x0070 | ||
| 103 | #define AM33XX_CM_PER_UART2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0070) | ||
| 104 | #define AM33XX_CM_PER_UART3_CLKCTRL_OFFSET 0x0074 | ||
| 105 | #define AM33XX_CM_PER_UART3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0074) | ||
| 106 | #define AM33XX_CM_PER_UART4_CLKCTRL_OFFSET 0x0078 | ||
| 107 | #define AM33XX_CM_PER_UART4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0078) | ||
| 108 | #define AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET 0x007c | ||
| 109 | #define AM33XX_CM_PER_TIMER7_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x007c) | ||
| 110 | #define AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET 0x0080 | ||
| 111 | #define AM33XX_CM_PER_TIMER2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0080) | ||
| 112 | #define AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET 0x0084 | ||
| 113 | #define AM33XX_CM_PER_TIMER3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0084) | ||
| 114 | #define AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET 0x0088 | ||
| 115 | #define AM33XX_CM_PER_TIMER4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0088) | ||
| 116 | #define AM33XX_CM_PER_MCASP2_CLKCTRL_OFFSET 0x008c | ||
| 117 | #define AM33XX_CM_PER_MCASP2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x008c) | ||
| 118 | #define AM33XX_CM_PER_RNG_CLKCTRL_OFFSET 0x0090 | ||
| 119 | #define AM33XX_CM_PER_RNG_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0090) | ||
| 120 | #define AM33XX_CM_PER_AES0_CLKCTRL_OFFSET 0x0094 | ||
| 121 | #define AM33XX_CM_PER_AES0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0094) | ||
| 122 | #define AM33XX_CM_PER_AES1_CLKCTRL_OFFSET 0x0098 | ||
| 123 | #define AM33XX_CM_PER_AES1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0098) | ||
| 124 | #define AM33XX_CM_PER_DES_CLKCTRL_OFFSET 0x009c | ||
| 125 | #define AM33XX_CM_PER_DES_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x009c) | ||
| 126 | #define AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET 0x00a0 | ||
| 127 | #define AM33XX_CM_PER_SHA0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a0) | ||
| 128 | #define AM33XX_CM_PER_PKA_CLKCTRL_OFFSET 0x00a4 | ||
| 129 | #define AM33XX_CM_PER_PKA_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a4) | ||
| 130 | #define AM33XX_CM_PER_GPIO6_CLKCTRL_OFFSET 0x00a8 | ||
| 131 | #define AM33XX_CM_PER_GPIO6_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a8) | ||
| 132 | #define AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET 0x00ac | ||
| 133 | #define AM33XX_CM_PER_GPIO1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ac) | ||
| 134 | #define AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET 0x00b0 | ||
| 135 | #define AM33XX_CM_PER_GPIO2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b0) | ||
| 136 | #define AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET 0x00b4 | ||
| 137 | #define AM33XX_CM_PER_GPIO3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b4) | ||
| 138 | #define AM33XX_CM_PER_GPIO4_CLKCTRL_OFFSET 0x00b8 | ||
| 139 | #define AM33XX_CM_PER_GPIO4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b8) | ||
| 140 | #define AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET 0x00bc | ||
| 141 | #define AM33XX_CM_PER_TPCC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00bc) | ||
| 142 | #define AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET 0x00c0 | ||
| 143 | #define AM33XX_CM_PER_DCAN0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c0) | ||
| 144 | #define AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET 0x00c4 | ||
| 145 | #define AM33XX_CM_PER_DCAN1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c4) | ||
| 146 | #define AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET 0x00cc | ||
| 147 | #define AM33XX_CM_PER_EPWMSS1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00cc) | ||
| 148 | #define AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET 0x00d0 | ||
| 149 | #define AM33XX_CM_PER_EMIF_FW_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d0) | ||
| 150 | #define AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET 0x00d4 | ||
| 151 | #define AM33XX_CM_PER_EPWMSS0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d4) | ||
| 152 | #define AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET 0x00d8 | ||
| 153 | #define AM33XX_CM_PER_EPWMSS2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d8) | ||
| 154 | #define AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET 0x00dc | ||
| 155 | #define AM33XX_CM_PER_L3_INSTR_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00dc) | ||
| 156 | #define AM33XX_CM_PER_L3_CLKCTRL_OFFSET 0x00e0 | ||
| 157 | #define AM33XX_CM_PER_L3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e0) | ||
| 158 | #define AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET 0x00e4 | ||
| 159 | #define AM33XX_CM_PER_IEEE5000_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e4) | ||
| 160 | #define AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET 0x00e8 | ||
| 161 | #define AM33XX_CM_PER_PRUSS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e8) | ||
| 162 | #define AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET 0x00ec | ||
| 163 | #define AM33XX_CM_PER_TIMER5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ec) | ||
| 164 | #define AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET 0x00f0 | ||
| 165 | #define AM33XX_CM_PER_TIMER6_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f0) | ||
| 166 | #define AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET 0x00f4 | ||
| 167 | #define AM33XX_CM_PER_MMC1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f4) | ||
| 168 | #define AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET 0x00f8 | ||
| 169 | #define AM33XX_CM_PER_MMC2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f8) | ||
| 170 | #define AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET 0x00fc | ||
| 171 | #define AM33XX_CM_PER_TPTC1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00fc) | ||
| 172 | #define AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET 0x0100 | ||
| 173 | #define AM33XX_CM_PER_TPTC2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0100) | ||
| 174 | #define AM33XX_CM_PER_GPIO5_CLKCTRL_OFFSET 0x0104 | ||
| 175 | #define AM33XX_CM_PER_GPIO5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0104) | ||
| 176 | #define AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET 0x010c | ||
| 177 | #define AM33XX_CM_PER_SPINLOCK_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x010c) | ||
| 178 | #define AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET 0x0110 | ||
| 179 | #define AM33XX_CM_PER_MAILBOX0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0110) | ||
| 180 | #define AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET 0x011c | ||
| 181 | #define AM33XX_CM_PER_L4HS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x011c) | ||
| 182 | #define AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET 0x0120 | ||
| 183 | #define AM33XX_CM_PER_L4HS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0120) | ||
| 184 | #define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL_OFFSET 0x0124 | ||
| 185 | #define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0124) | ||
| 186 | #define AM33XX_CM_PER_SLV_EXPS_CLKCTRL_OFFSET 0x0128 | ||
| 187 | #define AM33XX_CM_PER_SLV_EXPS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0128) | ||
| 188 | #define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET 0x012c | ||
| 189 | #define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x012c) | ||
| 190 | #define AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET 0x0130 | ||
| 191 | #define AM33XX_CM_PER_OCPWP_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0130) | ||
| 192 | #define AM33XX_CM_PER_MAILBOX1_CLKCTRL_OFFSET 0x0134 | ||
| 193 | #define AM33XX_CM_PER_MAILBOX1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0134) | ||
| 194 | #define AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET 0x0140 | ||
| 195 | #define AM33XX_CM_PER_PRUSS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0140) | ||
| 196 | #define AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET 0x0144 | ||
| 197 | #define AM33XX_CM_PER_CPSW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0144) | ||
| 198 | #define AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET 0x0148 | ||
| 199 | #define AM33XX_CM_PER_LCDC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0148) | ||
| 200 | #define AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET 0x014c | ||
| 201 | #define AM33XX_CM_PER_CLKDIV32K_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x014c) | ||
| 202 | #define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET 0x0150 | ||
| 203 | #define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0150) | ||
| 204 | |||
| 205 | /* CM.WKUP_CM register offsets */ | ||
| 206 | #define AM33XX_CM_WKUP_CLKSTCTRL_OFFSET 0x0000 | ||
| 207 | #define AM33XX_CM_WKUP_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0000) | ||
| 208 | #define AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET 0x0004 | ||
| 209 | #define AM33XX_CM_WKUP_CONTROL_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0004) | ||
| 210 | #define AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET 0x0008 | ||
| 211 | #define AM33XX_CM_WKUP_GPIO0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0008) | ||
| 212 | #define AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x000c | ||
| 213 | #define AM33XX_CM_WKUP_L4WKUP_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x000c) | ||
| 214 | #define AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET 0x0010 | ||
| 215 | #define AM33XX_CM_WKUP_TIMER0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0010) | ||
| 216 | #define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET 0x0014 | ||
| 217 | #define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0014) | ||
| 218 | #define AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET 0x0018 | ||
| 219 | #define AM33XX_CM_L3_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0018) | ||
| 220 | #define AM33XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x001c | ||
| 221 | #define AM33XX_CM_AUTOIDLE_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x001c) | ||
| 222 | #define AM33XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0020 | ||
| 223 | #define AM33XX_CM_IDLEST_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0020) | ||
| 224 | #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0024 | ||
| 225 | #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0024) | ||
| 226 | #define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x0028 | ||
| 227 | #define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0028) | ||
| 228 | #define AM33XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x002c | ||
| 229 | #define AM33XX_CM_CLKSEL_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x002c) | ||
| 230 | #define AM33XX_CM_AUTOIDLE_DPLL_DDR_OFFSET 0x0030 | ||
| 231 | #define AM33XX_CM_AUTOIDLE_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0030) | ||
| 232 | #define AM33XX_CM_IDLEST_DPLL_DDR_OFFSET 0x0034 | ||
| 233 | #define AM33XX_CM_IDLEST_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0034) | ||
| 234 | #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET 0x0038 | ||
| 235 | #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0038) | ||
| 236 | #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET 0x003c | ||
| 237 | #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x003c) | ||
| 238 | #define AM33XX_CM_CLKSEL_DPLL_DDR_OFFSET 0x0040 | ||
| 239 | #define AM33XX_CM_CLKSEL_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0040) | ||
| 240 | #define AM33XX_CM_AUTOIDLE_DPLL_DISP_OFFSET 0x0044 | ||
| 241 | #define AM33XX_CM_AUTOIDLE_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0044) | ||
| 242 | #define AM33XX_CM_IDLEST_DPLL_DISP_OFFSET 0x0048 | ||
| 243 | #define AM33XX_CM_IDLEST_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0048) | ||
| 244 | #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP_OFFSET 0x004c | ||
| 245 | #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x004c) | ||
| 246 | #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP_OFFSET 0x0050 | ||
| 247 | #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0050) | ||
| 248 | #define AM33XX_CM_CLKSEL_DPLL_DISP_OFFSET 0x0054 | ||
| 249 | #define AM33XX_CM_CLKSEL_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0054) | ||
| 250 | #define AM33XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0058 | ||
| 251 | #define AM33XX_CM_AUTOIDLE_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0058) | ||
| 252 | #define AM33XX_CM_IDLEST_DPLL_CORE_OFFSET 0x005c | ||
| 253 | #define AM33XX_CM_IDLEST_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x005c) | ||
| 254 | #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0060 | ||
| 255 | #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0060) | ||
| 256 | #define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x0064 | ||
| 257 | #define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0064) | ||
| 258 | #define AM33XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x0068 | ||
| 259 | #define AM33XX_CM_CLKSEL_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0068) | ||
| 260 | #define AM33XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x006c | ||
| 261 | #define AM33XX_CM_AUTOIDLE_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x006c) | ||
| 262 | #define AM33XX_CM_IDLEST_DPLL_PER_OFFSET 0x0070 | ||
| 263 | #define AM33XX_CM_IDLEST_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0070) | ||
| 264 | #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0074 | ||
| 265 | #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0074) | ||
| 266 | #define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x0078 | ||
| 267 | #define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0078) | ||
| 268 | #define AM33XX_CM_CLKDCOLDO_DPLL_PER_OFFSET 0x007c | ||
| 269 | #define AM33XX_CM_CLKDCOLDO_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x007c) | ||
| 270 | #define AM33XX_CM_DIV_M4_DPLL_CORE_OFFSET 0x0080 | ||
| 271 | #define AM33XX_CM_DIV_M4_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0080) | ||
| 272 | #define AM33XX_CM_DIV_M5_DPLL_CORE_OFFSET 0x0084 | ||
| 273 | #define AM33XX_CM_DIV_M5_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0084) | ||
| 274 | #define AM33XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0088 | ||
| 275 | #define AM33XX_CM_CLKMODE_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0088) | ||
| 276 | #define AM33XX_CM_CLKMODE_DPLL_PER_OFFSET 0x008c | ||
| 277 | #define AM33XX_CM_CLKMODE_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x008c) | ||
| 278 | #define AM33XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0090 | ||
| 279 | #define AM33XX_CM_CLKMODE_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0090) | ||
| 280 | #define AM33XX_CM_CLKMODE_DPLL_DDR_OFFSET 0x0094 | ||
| 281 | #define AM33XX_CM_CLKMODE_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0094) | ||
| 282 | #define AM33XX_CM_CLKMODE_DPLL_DISP_OFFSET 0x0098 | ||
| 283 | #define AM33XX_CM_CLKMODE_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0098) | ||
| 284 | #define AM33XX_CM_CLKSEL_DPLL_PERIPH_OFFSET 0x009c | ||
| 285 | #define AM33XX_CM_CLKSEL_DPLL_PERIPH AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x009c) | ||
| 286 | #define AM33XX_CM_DIV_M2_DPLL_DDR_OFFSET 0x00a0 | ||
| 287 | #define AM33XX_CM_DIV_M2_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a0) | ||
| 288 | #define AM33XX_CM_DIV_M2_DPLL_DISP_OFFSET 0x00a4 | ||
| 289 | #define AM33XX_CM_DIV_M2_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a4) | ||
| 290 | #define AM33XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x00a8 | ||
| 291 | #define AM33XX_CM_DIV_M2_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a8) | ||
| 292 | #define AM33XX_CM_DIV_M2_DPLL_PER_OFFSET 0x00ac | ||
| 293 | #define AM33XX_CM_DIV_M2_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00ac) | ||
| 294 | #define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET 0x00b0 | ||
| 295 | #define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b0) | ||
| 296 | #define AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET 0x00b4 | ||
| 297 | #define AM33XX_CM_WKUP_UART0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b4) | ||
| 298 | #define AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET 0x00b8 | ||
| 299 | #define AM33XX_CM_WKUP_I2C0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b8) | ||
| 300 | #define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET 0x00bc | ||
| 301 | #define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00bc) | ||
| 302 | #define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET 0x00c0 | ||
| 303 | #define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c0) | ||
| 304 | #define AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x00c4 | ||
| 305 | #define AM33XX_CM_WKUP_TIMER1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c4) | ||
| 306 | #define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET 0x00c8 | ||
| 307 | #define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c8) | ||
| 308 | #define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET 0x00cc | ||
| 309 | #define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00cc) | ||
| 310 | #define AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET 0x00d0 | ||
| 311 | #define AM33XX_CM_WKUP_WDT0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d0) | ||
| 312 | #define AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x00d4 | ||
| 313 | #define AM33XX_CM_WKUP_WDT1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d4) | ||
| 314 | #define AM33XX_CM_DIV_M6_DPLL_CORE_OFFSET 0x00d8 | ||
| 315 | #define AM33XX_CM_DIV_M6_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d8) | ||
| 316 | |||
| 317 | /* CM.DPLL_CM register offsets */ | ||
| 318 | #define AM33XX_CLKSEL_TIMER7_CLK_OFFSET 0x0004 | ||
| 319 | #define AM33XX_CLKSEL_TIMER7_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0004) | ||
| 320 | #define AM33XX_CLKSEL_TIMER2_CLK_OFFSET 0x0008 | ||
| 321 | #define AM33XX_CLKSEL_TIMER2_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0008) | ||
| 322 | #define AM33XX_CLKSEL_TIMER3_CLK_OFFSET 0x000c | ||
| 323 | #define AM33XX_CLKSEL_TIMER3_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x000c) | ||
| 324 | #define AM33XX_CLKSEL_TIMER4_CLK_OFFSET 0x0010 | ||
| 325 | #define AM33XX_CLKSEL_TIMER4_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0010) | ||
| 326 | #define AM33XX_CM_MAC_CLKSEL_OFFSET 0x0014 | ||
| 327 | #define AM33XX_CM_MAC_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0014) | ||
| 328 | #define AM33XX_CLKSEL_TIMER5_CLK_OFFSET 0x0018 | ||
| 329 | #define AM33XX_CLKSEL_TIMER5_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0018) | ||
| 330 | #define AM33XX_CLKSEL_TIMER6_CLK_OFFSET 0x001c | ||
| 331 | #define AM33XX_CLKSEL_TIMER6_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x001c) | ||
| 332 | #define AM33XX_CM_CPTS_RFT_CLKSEL_OFFSET 0x0020 | ||
| 333 | #define AM33XX_CM_CPTS_RFT_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0020) | ||
| 334 | #define AM33XX_CLKSEL_TIMER1MS_CLK_OFFSET 0x0028 | ||
| 335 | #define AM33XX_CLKSEL_TIMER1MS_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0028) | ||
| 336 | #define AM33XX_CLKSEL_GFX_FCLK_OFFSET 0x002c | ||
| 337 | #define AM33XX_CLKSEL_GFX_FCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x002c) | ||
| 338 | #define AM33XX_CLKSEL_PRUSS_OCP_CLK_OFFSET 0x0030 | ||
| 339 | #define AM33XX_CLKSEL_PRUSS_OCP_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0030) | ||
| 340 | #define AM33XX_CLKSEL_LCDC_PIXEL_CLK_OFFSET 0x0034 | ||
| 341 | #define AM33XX_CLKSEL_LCDC_PIXEL_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0034) | ||
| 342 | #define AM33XX_CLKSEL_WDT1_CLK_OFFSET 0x0038 | ||
| 343 | #define AM33XX_CLKSEL_WDT1_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0038) | ||
| 344 | #define AM33XX_CLKSEL_GPIO0_DBCLK_OFFSET 0x003c | ||
| 345 | #define AM33XX_CLKSEL_GPIO0_DBCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x003c) | ||
| 346 | |||
| 347 | /* CM.MPU_CM register offsets */ | ||
| 348 | #define AM33XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000 | ||
| 349 | #define AM33XX_CM_MPU_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0000) | ||
| 350 | #define AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0004 | ||
| 351 | #define AM33XX_CM_MPU_MPU_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0004) | ||
| 352 | |||
| 353 | /* CM.DEVICE_CM register offsets */ | ||
| 354 | #define AM33XX_CM_CLKOUT_CTRL_OFFSET 0x0000 | ||
| 355 | #define AM33XX_CM_CLKOUT_CTRL AM33XX_CM_REGADDR(AM33XX_CM_DEVICE_MOD, 0x0000) | ||
| 356 | |||
| 357 | /* CM.RTC_CM register offsets */ | ||
| 358 | #define AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET 0x0000 | ||
| 359 | #define AM33XX_CM_RTC_RTC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0000) | ||
| 360 | #define AM33XX_CM_RTC_CLKSTCTRL_OFFSET 0x0004 | ||
| 361 | #define AM33XX_CM_RTC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0004) | ||
| 362 | |||
| 363 | /* CM.GFX_CM register offsets */ | ||
| 364 | #define AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET 0x0000 | ||
| 365 | #define AM33XX_CM_GFX_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0000) | ||
| 366 | #define AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET 0x0004 | ||
| 367 | #define AM33XX_CM_GFX_GFX_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0004) | ||
| 368 | #define AM33XX_CM_GFX_BITBLT_CLKCTRL_OFFSET 0x0008 | ||
| 369 | #define AM33XX_CM_GFX_BITBLT_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0008) | ||
| 370 | #define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET 0x000c | ||
| 371 | #define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1 AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x000c) | ||
| 372 | #define AM33XX_CM_GFX_MMUCFG_CLKCTRL_OFFSET 0x0010 | ||
| 373 | #define AM33XX_CM_GFX_MMUCFG_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0010) | ||
| 374 | #define AM33XX_CM_GFX_MMUDATA_CLKCTRL_OFFSET 0x0014 | ||
| 375 | #define AM33XX_CM_GFX_MMUDATA_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0014) | ||
| 376 | |||
| 377 | /* CM.CEFUSE_CM register offsets */ | ||
| 378 | #define AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000 | ||
| 379 | #define AM33XX_CM_CEFUSE_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0000) | ||
| 380 | #define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 | ||
| 381 | #define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020) | ||
| 382 | |||
| 383 | |||
| 384 | extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs); | ||
| 385 | extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs); | ||
| 386 | extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs); | ||
| 387 | extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs); | ||
| 388 | extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs); | ||
| 389 | |||
| 390 | #ifdef CONFIG_SOC_AM33XX | ||
| 391 | extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, | ||
| 392 | u16 clkctrl_offs); | ||
| 393 | extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, | ||
| 394 | u16 clkctrl_offs); | ||
| 395 | extern void am33xx_cm_module_disable(u16 inst, s16 cdoffs, | ||
| 396 | u16 clkctrl_offs); | ||
| 397 | extern int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, | ||
| 398 | u16 clkctrl_offs); | ||
| 399 | #else | ||
| 400 | static inline int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, | ||
| 401 | u16 clkctrl_offs) | ||
| 402 | { | ||
| 403 | return 0; | ||
| 404 | } | ||
| 405 | static inline void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, | ||
| 406 | u16 clkctrl_offs) | ||
| 407 | { | ||
| 408 | } | ||
| 409 | static inline void am33xx_cm_module_disable(u16 inst, s16 cdoffs, | ||
| 410 | u16 clkctrl_offs) | ||
| 411 | { | ||
| 412 | } | ||
| 413 | static inline int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, | ||
| 414 | u16 clkctrl_offs) | ||
| 415 | { | ||
| 416 | return 0; | ||
| 417 | } | ||
| 418 | #endif | ||
| 419 | |||
| 420 | #endif | ||
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c index 1706ebcec08d..c1875862679f 100644 --- a/arch/arm/mach-omap2/common-board-devices.c +++ b/arch/arm/mach-omap2/common-board-devices.c | |||
| @@ -63,28 +63,30 @@ void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce, | |||
| 63 | struct spi_board_info *spi_bi = &ads7846_spi_board_info; | 63 | struct spi_board_info *spi_bi = &ads7846_spi_board_info; |
| 64 | int err; | 64 | int err; |
| 65 | 65 | ||
| 66 | if (board_pdata && board_pdata->get_pendown_state) { | 66 | err = gpio_request_one(gpio_pendown, GPIOF_IN, "TSPenDown"); |
| 67 | err = gpio_request_one(gpio_pendown, GPIOF_IN, "TSPenDown"); | 67 | if (err) { |
| 68 | if (err) { | 68 | pr_err("Couldn't obtain gpio for TSPenDown: %d\n", err); |
| 69 | pr_err("Couldn't obtain gpio for TSPenDown: %d\n", err); | 69 | return; |
| 70 | return; | ||
| 71 | } | ||
| 72 | gpio_export(gpio_pendown, 0); | ||
| 73 | |||
| 74 | if (gpio_debounce) | ||
| 75 | gpio_set_debounce(gpio_pendown, gpio_debounce); | ||
| 76 | } | 70 | } |
| 77 | 71 | ||
| 72 | if (gpio_debounce) | ||
| 73 | gpio_set_debounce(gpio_pendown, gpio_debounce); | ||
| 74 | |||
| 78 | spi_bi->bus_num = bus_num; | 75 | spi_bi->bus_num = bus_num; |
| 79 | spi_bi->irq = gpio_to_irq(gpio_pendown); | 76 | spi_bi->irq = gpio_to_irq(gpio_pendown); |
| 80 | 77 | ||
| 81 | if (board_pdata) { | 78 | if (board_pdata) { |
| 82 | board_pdata->gpio_pendown = gpio_pendown; | 79 | board_pdata->gpio_pendown = gpio_pendown; |
| 83 | spi_bi->platform_data = board_pdata; | 80 | spi_bi->platform_data = board_pdata; |
| 81 | if (board_pdata->get_pendown_state) | ||
| 82 | gpio_export(gpio_pendown, 0); | ||
| 84 | } else { | 83 | } else { |
| 85 | ads7846_config.gpio_pendown = gpio_pendown; | 84 | ads7846_config.gpio_pendown = gpio_pendown; |
| 86 | } | 85 | } |
| 87 | 86 | ||
| 87 | if (!board_pdata || (board_pdata && !board_pdata->get_pendown_state)) | ||
| 88 | gpio_free(gpio_pendown); | ||
| 89 | |||
| 88 | spi_register_board_info(&ads7846_spi_board_info, 1); | 90 | spi_register_board_info(&ads7846_spi_board_info, 1); |
| 89 | } | 91 | } |
| 90 | #else | 92 | #else |
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index be9dfd1abe60..5d99c1b2cb48 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h | |||
| @@ -120,6 +120,7 @@ extern void omap2_init_common_infrastructure(void); | |||
| 120 | extern struct sys_timer omap2_timer; | 120 | extern struct sys_timer omap2_timer; |
| 121 | extern struct sys_timer omap3_timer; | 121 | extern struct sys_timer omap3_timer; |
| 122 | extern struct sys_timer omap3_secure_timer; | 122 | extern struct sys_timer omap3_secure_timer; |
| 123 | extern struct sys_timer omap3_am33xx_timer; | ||
| 123 | extern struct sys_timer omap4_timer; | 124 | extern struct sys_timer omap4_timer; |
| 124 | 125 | ||
| 125 | void omap2420_init_early(void); | 126 | void omap2420_init_early(void); |
| @@ -128,8 +129,10 @@ void omap3430_init_early(void); | |||
| 128 | void omap35xx_init_early(void); | 129 | void omap35xx_init_early(void); |
| 129 | void omap3630_init_early(void); | 130 | void omap3630_init_early(void); |
| 130 | void omap3_init_early(void); /* Do not use this one */ | 131 | void omap3_init_early(void); /* Do not use this one */ |
| 132 | void am33xx_init_early(void); | ||
| 131 | void am35xx_init_early(void); | 133 | void am35xx_init_early(void); |
| 132 | void ti81xx_init_early(void); | 134 | void ti81xx_init_early(void); |
| 135 | void am33xx_init_early(void); | ||
| 133 | void omap4430_init_early(void); | 136 | void omap4430_init_early(void); |
| 134 | void omap3_init_late(void); /* Do not use this one */ | 137 | void omap3_init_late(void); /* Do not use this one */ |
| 135 | void omap4430_init_late(void); | 138 | void omap4430_init_late(void); |
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 08e674bb0417..3223b81e7532 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c | |||
| @@ -241,6 +241,49 @@ void omap3_ctrl_write_boot_mode(u8 bootmode) | |||
| 241 | 241 | ||
| 242 | #endif | 242 | #endif |
| 243 | 243 | ||
| 244 | /** | ||
| 245 | * omap_ctrl_write_dsp_boot_addr - set boot address for a remote processor | ||
| 246 | * @bootaddr: physical address of the boot loader | ||
| 247 | * | ||
| 248 | * Set boot address for the boot loader of a supported processor | ||
| 249 | * when a power ON sequence occurs. | ||
| 250 | */ | ||
| 251 | void omap_ctrl_write_dsp_boot_addr(u32 bootaddr) | ||
| 252 | { | ||
| 253 | u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR : | ||
| 254 | cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR : | ||
| 255 | cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR : | ||
| 256 | 0; | ||
| 257 | |||
| 258 | if (!offset) { | ||
| 259 | pr_err("%s: unsupported omap type\n", __func__); | ||
| 260 | return; | ||
| 261 | } | ||
| 262 | |||
| 263 | omap_ctrl_writel(bootaddr, offset); | ||
| 264 | } | ||
| 265 | |||
| 266 | /** | ||
| 267 | * omap_ctrl_write_dsp_boot_mode - set boot mode for a remote processor | ||
| 268 | * @bootmode: 8-bit value to pass to some boot code | ||
| 269 | * | ||
| 270 | * Sets boot mode for the boot loader of a supported processor | ||
| 271 | * when a power ON sequence occurs. | ||
| 272 | */ | ||
| 273 | void omap_ctrl_write_dsp_boot_mode(u8 bootmode) | ||
| 274 | { | ||
| 275 | u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTMOD : | ||
| 276 | cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTMOD : | ||
| 277 | 0; | ||
| 278 | |||
| 279 | if (!offset) { | ||
| 280 | pr_err("%s: unsupported omap type\n", __func__); | ||
| 281 | return; | ||
| 282 | } | ||
| 283 | |||
| 284 | omap_ctrl_writel(bootmode, offset); | ||
| 285 | } | ||
| 286 | |||
| 244 | #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) | 287 | #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) |
| 245 | /* | 288 | /* |
| 246 | * Clears the scratchpad contents in case of cold boot- | 289 | * Clears the scratchpad contents in case of cold boot- |
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index a406fd045ce1..5baf305386e9 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h | |||
| @@ -21,6 +21,8 @@ | |||
| 21 | #include <mach/ctrl_module_pad_core_44xx.h> | 21 | #include <mach/ctrl_module_pad_core_44xx.h> |
| 22 | #include <mach/ctrl_module_pad_wkup_44xx.h> | 22 | #include <mach/ctrl_module_pad_wkup_44xx.h> |
| 23 | 23 | ||
| 24 | #include <plat/am33xx.h> | ||
| 25 | |||
| 24 | #ifndef __ASSEMBLY__ | 26 | #ifndef __ASSEMBLY__ |
| 25 | #define OMAP242X_CTRL_REGADDR(reg) \ | 27 | #define OMAP242X_CTRL_REGADDR(reg) \ |
| 26 | OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) | 28 | OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) |
| @@ -28,6 +30,8 @@ | |||
| 28 | OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) | 30 | OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) |
| 29 | #define OMAP343X_CTRL_REGADDR(reg) \ | 31 | #define OMAP343X_CTRL_REGADDR(reg) \ |
| 30 | OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) | 32 | OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) |
| 33 | #define AM33XX_CTRL_REGADDR(reg) \ | ||
| 34 | AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg)) | ||
| 31 | #else | 35 | #else |
| 32 | #define OMAP242X_CTRL_REGADDR(reg) \ | 36 | #define OMAP242X_CTRL_REGADDR(reg) \ |
| 33 | OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) | 37 | OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) |
| @@ -35,6 +39,8 @@ | |||
| 35 | OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) | 39 | OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) |
| 36 | #define OMAP343X_CTRL_REGADDR(reg) \ | 40 | #define OMAP343X_CTRL_REGADDR(reg) \ |
| 37 | OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) | 41 | OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) |
| 42 | #define AM33XX_CTRL_REGADDR(reg) \ | ||
| 43 | AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg)) | ||
| 38 | #endif /* __ASSEMBLY__ */ | 44 | #endif /* __ASSEMBLY__ */ |
| 39 | 45 | ||
| 40 | /* | 46 | /* |
| @@ -312,15 +318,15 @@ | |||
| 312 | OMAP343X_SCRATCHPAD + reg) | 318 | OMAP343X_SCRATCHPAD + reg) |
| 313 | 319 | ||
| 314 | /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */ | 320 | /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */ |
| 315 | #define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0 | 321 | #define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0 |
| 316 | #define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1 | 322 | #define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1 |
| 317 | #define AM35XX_VPFE_VBUSP_CLK_SHIFT 2 | 323 | #define AM35XX_VPFE_VBUSP_CLK_SHIFT 2 |
| 318 | #define AM35XX_HECC_VBUSP_CLK_SHIFT 3 | 324 | #define AM35XX_HECC_VBUSP_CLK_SHIFT 3 |
| 319 | #define AM35XX_USBOTG_FCLK_SHIFT 8 | 325 | #define AM35XX_USBOTG_FCLK_SHIFT 8 |
| 320 | #define AM35XX_CPGMAC_FCLK_SHIFT 9 | 326 | #define AM35XX_CPGMAC_FCLK_SHIFT 9 |
| 321 | #define AM35XX_VPFE_FCLK_SHIFT 10 | 327 | #define AM35XX_VPFE_FCLK_SHIFT 10 |
| 322 | 328 | ||
| 323 | /*AM35XX CONTROL_LVL_INTR_CLEAR bits*/ | 329 | /* AM35XX CONTROL_LVL_INTR_CLEAR bits */ |
| 324 | #define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0) | 330 | #define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0) |
| 325 | #define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1) | 331 | #define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1) |
| 326 | #define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2) | 332 | #define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2) |
| @@ -330,21 +336,22 @@ | |||
| 330 | #define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6) | 336 | #define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6) |
| 331 | #define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7) | 337 | #define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7) |
| 332 | 338 | ||
| 333 | /*AM35XX CONTROL_IP_SW_RESET bits*/ | 339 | /* AM35XX CONTROL_IP_SW_RESET bits */ |
| 334 | #define AM35XX_USBOTGSS_SW_RST BIT(0) | 340 | #define AM35XX_USBOTGSS_SW_RST BIT(0) |
| 335 | #define AM35XX_CPGMACSS_SW_RST BIT(1) | 341 | #define AM35XX_CPGMACSS_SW_RST BIT(1) |
| 336 | #define AM35XX_VPFE_VBUSP_SW_RST BIT(2) | 342 | #define AM35XX_VPFE_VBUSP_SW_RST BIT(2) |
| 337 | #define AM35XX_HECC_SW_RST BIT(3) | 343 | #define AM35XX_HECC_SW_RST BIT(3) |
| 338 | #define AM35XX_VPFE_PCLK_SW_RST BIT(4) | 344 | #define AM35XX_VPFE_PCLK_SW_RST BIT(4) |
| 339 | 345 | ||
| 340 | /* | 346 | /* AM33XX CONTROL_STATUS register */ |
| 341 | * CONTROL AM33XX STATUS register | ||
| 342 | */ | ||
| 343 | #define AM33XX_CONTROL_STATUS 0x040 | 347 | #define AM33XX_CONTROL_STATUS 0x040 |
| 348 | #define AM33XX_CONTROL_SEC_CLK_CTRL 0x1bc | ||
| 344 | 349 | ||
| 345 | /* | 350 | /* AM33XX CONTROL_STATUS bitfields (partial) */ |
| 346 | * CONTROL OMAP STATUS register to identify OMAP3 features | 351 | #define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT 22 |
| 347 | */ | 352 | #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22) |
| 353 | |||
| 354 | /* CONTROL OMAP STATUS register to identify OMAP3 features */ | ||
| 348 | #define OMAP3_CONTROL_OMAP_STATUS 0x044c | 355 | #define OMAP3_CONTROL_OMAP_STATUS 0x044c |
| 349 | 356 | ||
| 350 | #define OMAP3_SGX_SHIFT 13 | 357 | #define OMAP3_SGX_SHIFT 13 |
| @@ -397,6 +404,8 @@ extern u32 omap3_arm_context[128]; | |||
| 397 | extern void omap3_control_save_context(void); | 404 | extern void omap3_control_save_context(void); |
| 398 | extern void omap3_control_restore_context(void); | 405 | extern void omap3_control_restore_context(void); |
| 399 | extern void omap3_ctrl_write_boot_mode(u8 bootmode); | 406 | extern void omap3_ctrl_write_boot_mode(u8 bootmode); |
| 407 | extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr); | ||
| 408 | extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode); | ||
| 400 | extern void omap3630_ctrl_disable_rta(void); | 409 | extern void omap3630_ctrl_disable_rta(void); |
| 401 | extern int omap3_ctrl_save_padconf(void); | 410 | extern int omap3_ctrl_save_padconf(void); |
| 402 | #else | 411 | #else |
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index 207bc1c7759f..31344528eb54 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c | |||
| @@ -36,8 +36,6 @@ | |||
| 36 | #include "control.h" | 36 | #include "control.h" |
| 37 | #include "common.h" | 37 | #include "common.h" |
| 38 | 38 | ||
| 39 | #ifdef CONFIG_CPU_IDLE | ||
| 40 | |||
| 41 | /* Mach specific information to be recorded in the C-state driver_data */ | 39 | /* Mach specific information to be recorded in the C-state driver_data */ |
| 42 | struct omap3_idle_statedata { | 40 | struct omap3_idle_statedata { |
| 43 | u32 mpu_state; | 41 | u32 mpu_state; |
| @@ -379,9 +377,3 @@ int __init omap3_idle_init(void) | |||
| 379 | 377 | ||
| 380 | return 0; | 378 | return 0; |
| 381 | } | 379 | } |
| 382 | #else | ||
| 383 | int __init omap3_idle_init(void) | ||
| 384 | { | ||
| 385 | return 0; | ||
| 386 | } | ||
| 387 | #endif /* CONFIG_CPU_IDLE */ | ||
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c index be1617ca84bd..02d15bbd4e35 100644 --- a/arch/arm/mach-omap2/cpuidle44xx.c +++ b/arch/arm/mach-omap2/cpuidle44xx.c | |||
| @@ -22,8 +22,6 @@ | |||
| 22 | #include "pm.h" | 22 | #include "pm.h" |
| 23 | #include "prm.h" | 23 | #include "prm.h" |
| 24 | 24 | ||
| 25 | #ifdef CONFIG_CPU_IDLE | ||
| 26 | |||
| 27 | /* Machine specific information */ | 25 | /* Machine specific information */ |
| 28 | struct omap4_idle_statedata { | 26 | struct omap4_idle_statedata { |
| 29 | u32 cpu_state; | 27 | u32 cpu_state; |
| @@ -199,9 +197,3 @@ int __init omap4_idle_init(void) | |||
| 199 | 197 | ||
| 200 | return 0; | 198 | return 0; |
| 201 | } | 199 | } |
| 202 | #else | ||
| 203 | int __init omap4_idle_init(void) | ||
| 204 | { | ||
| 205 | return 0; | ||
| 206 | } | ||
| 207 | #endif /* CONFIG_CPU_IDLE */ | ||
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c index 88ffa1e645cd..a636ebc16b39 100644 --- a/arch/arm/mach-omap2/dsp.c +++ b/arch/arm/mach-omap2/dsp.c | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | 23 | ||
| 24 | #include <asm/memblock.h> | 24 | #include <asm/memblock.h> |
| 25 | 25 | ||
| 26 | #include "control.h" | ||
| 26 | #include "cm2xxx_3xxx.h" | 27 | #include "cm2xxx_3xxx.h" |
| 27 | #include "prm2xxx_3xxx.h" | 28 | #include "prm2xxx_3xxx.h" |
| 28 | #ifdef CONFIG_BRIDGE_DVFS | 29 | #ifdef CONFIG_BRIDGE_DVFS |
| @@ -46,6 +47,9 @@ static struct omap_dsp_platform_data omap_dsp_pdata __initdata = { | |||
| 46 | .dsp_cm_read = omap2_cm_read_mod_reg, | 47 | .dsp_cm_read = omap2_cm_read_mod_reg, |
| 47 | .dsp_cm_write = omap2_cm_write_mod_reg, | 48 | .dsp_cm_write = omap2_cm_write_mod_reg, |
| 48 | .dsp_cm_rmw_bits = omap2_cm_rmw_mod_reg_bits, | 49 | .dsp_cm_rmw_bits = omap2_cm_rmw_mod_reg_bits, |
| 50 | |||
| 51 | .set_bootaddr = omap_ctrl_write_dsp_boot_addr, | ||
| 52 | .set_bootmode = omap_ctrl_write_dsp_boot_mode, | ||
| 49 | }; | 53 | }; |
| 50 | 54 | ||
| 51 | static phys_addr_t omap_dsp_phys_mempool_base; | 55 | static phys_addr_t omap_dsp_phys_mempool_base; |
diff --git a/arch/arm/mach-omap2/include/mach/am35xx.h b/arch/arm/mach-omap2/include/mach/am35xx.h index f1e13d1ca5e7..95594495fcf6 100644 --- a/arch/arm/mach-omap2/include/mach/am35xx.h +++ b/arch/arm/mach-omap2/include/mach/am35xx.h | |||
| @@ -36,6 +36,8 @@ | |||
| 36 | #define AM35XX_EMAC_CNTRL_MOD_OFFSET (0x0) | 36 | #define AM35XX_EMAC_CNTRL_MOD_OFFSET (0x0) |
| 37 | #define AM35XX_EMAC_CNTRL_RAM_OFFSET (0x20000) | 37 | #define AM35XX_EMAC_CNTRL_RAM_OFFSET (0x20000) |
| 38 | #define AM35XX_EMAC_MDIO_OFFSET (0x30000) | 38 | #define AM35XX_EMAC_MDIO_OFFSET (0x30000) |
| 39 | #define AM35XX_IPSS_MDIO_BASE (AM35XX_IPSS_EMAC_BASE + \ | ||
| 40 | AM35XX_EMAC_MDIO_OFFSET) | ||
| 39 | #define AM35XX_EMAC_CNTRL_RAM_SIZE (0x2000) | 41 | #define AM35XX_EMAC_CNTRL_RAM_SIZE (0x2000) |
| 40 | #define AM35XX_EMAC_RAM_ADDR (AM3517_EMAC_BASE + \ | 42 | #define AM35XX_EMAC_RAM_ADDR (AM3517_EMAC_BASE + \ |
| 41 | AM3517_EMAC_CNTRL_RAM_OFFSET) | 43 | AM3517_EMAC_CNTRL_RAM_OFFSET) |
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h index 2f7ac70a20d8..01970824e0e5 100644 --- a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h +++ b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h | |||
| @@ -42,6 +42,7 @@ | |||
| 42 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268 | 42 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268 |
| 43 | #define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4 | 43 | #define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4 |
| 44 | #define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300 | 44 | #define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300 |
| 45 | #define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR 0x0304 | ||
| 45 | #define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314 | 46 | #define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314 |
| 46 | #define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318 | 47 | #define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318 |
| 47 | #define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320 | 48 | #define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320 |
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S index cdfc2a1f0e75..d7f844a99a7b 100644 --- a/arch/arm/mach-omap2/include/mach/debug-macro.S +++ b/arch/arm/mach-omap2/include/mach/debug-macro.S | |||
| @@ -72,6 +72,8 @@ omap_uart_lsr: .word 0 | |||
| 72 | beq 82f @ configure UART2 | 72 | beq 82f @ configure UART2 |
| 73 | cmp \rp, #TI81XXUART3 @ ti81Xx UART offsets different | 73 | cmp \rp, #TI81XXUART3 @ ti81Xx UART offsets different |
| 74 | beq 83f @ configure UART3 | 74 | beq 83f @ configure UART3 |
| 75 | cmp \rp, #AM33XXUART1 @ AM33XX UART offsets different | ||
| 76 | beq 84f @ configure UART1 | ||
| 75 | cmp \rp, #ZOOM_UART @ only on zoom2/3 | 77 | cmp \rp, #ZOOM_UART @ only on zoom2/3 |
| 76 | beq 95f @ configure ZOOM_UART | 78 | beq 95f @ configure ZOOM_UART |
| 77 | 79 | ||
| @@ -100,7 +102,9 @@ omap_uart_lsr: .word 0 | |||
| 100 | b 98f | 102 | b 98f |
| 101 | 83: mov \rp, #UART_OFFSET(TI81XX_UART3_BASE) | 103 | 83: mov \rp, #UART_OFFSET(TI81XX_UART3_BASE) |
| 102 | b 98f | 104 | b 98f |
| 103 | 105 | 84: ldr \rp, =AM33XX_UART1_BASE | |
| 106 | and \rp, \rp, #0x00ffffff | ||
| 107 | b 97f | ||
| 104 | 95: ldr \rp, =ZOOM_UART_BASE | 108 | 95: ldr \rp, =ZOOM_UART_BASE |
| 105 | str \rp, [\tmp, #0] @ omap_uart_phys | 109 | str \rp, [\tmp, #0] @ omap_uart_phys |
| 106 | ldr \rp, =ZOOM_UART_VIRT | 110 | ldr \rp, =ZOOM_UART_VIRT |
| @@ -109,6 +113,17 @@ omap_uart_lsr: .word 0 | |||
| 109 | str \rp, [\tmp, #8] @ omap_uart_lsr | 113 | str \rp, [\tmp, #8] @ omap_uart_lsr |
| 110 | b 10b | 114 | b 10b |
| 111 | 115 | ||
| 116 | /* AM33XX: Store both phys and virt address for the uart */ | ||
| 117 | 97: add \rp, \rp, #0x44000000 @ phys base | ||
| 118 | str \rp, [\tmp, #0] @ omap_uart_phys | ||
| 119 | sub \rp, \rp, #0x44000000 @ phys base | ||
| 120 | add \rp, \rp, #0xf9000000 @ virt base | ||
| 121 | str \rp, [\tmp, #4] @ omap_uart_virt | ||
| 122 | mov \rp, #(UART_LSR << OMAP_PORT_SHIFT) | ||
| 123 | str \rp, [\tmp, #8] @ omap_uart_lsr | ||
| 124 | |||
| 125 | b 10b | ||
| 126 | |||
| 112 | /* Store both phys and virt address for the uart */ | 127 | /* Store both phys and virt address for the uart */ |
| 113 | 98: add \rp, \rp, #0x48000000 @ phys base | 128 | 98: add \rp, \rp, #0x48000000 @ phys base |
| 114 | str \rp, [\tmp, #0] @ omap_uart_phys | 129 | str \rp, [\tmp, #0] @ omap_uart_phys |
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 8d014ba04abc..cb6c11cd8df9 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c | |||
| @@ -477,6 +477,19 @@ void __init ti81xx_init_late(void) | |||
| 477 | } | 477 | } |
| 478 | #endif | 478 | #endif |
| 479 | 479 | ||
| 480 | #ifdef CONFIG_SOC_AM33XX | ||
| 481 | void __init am33xx_init_early(void) | ||
| 482 | { | ||
| 483 | omap2_set_globals_am33xx(); | ||
| 484 | omap3xxx_check_revision(); | ||
| 485 | ti81xx_check_features(); | ||
| 486 | omap_common_init_early(); | ||
| 487 | am33xx_voltagedomains_init(); | ||
| 488 | am33xx_powerdomains_init(); | ||
| 489 | am33xx_clockdomains_init(); | ||
| 490 | } | ||
| 491 | #endif | ||
| 492 | |||
| 480 | #ifdef CONFIG_ARCH_OMAP4 | 493 | #ifdef CONFIG_ARCH_OMAP4 |
| 481 | void __init omap4430_init_early(void) | 494 | void __init omap4430_init_early(void) |
| 482 | { | 495 | { |
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index 6038a8c84b74..a9c26b12cad2 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c | |||
| @@ -262,7 +262,7 @@ int __init omap_intc_of_init(struct device_node *node, | |||
| 262 | struct device_node *parent) | 262 | struct device_node *parent) |
| 263 | { | 263 | { |
| 264 | struct resource res; | 264 | struct resource res; |
| 265 | u32 nr_irqs = 96; | 265 | u32 nr_irq = 96; |
| 266 | 266 | ||
| 267 | if (WARN_ON(!node)) | 267 | if (WARN_ON(!node)) |
| 268 | return -ENODEV; | 268 | return -ENODEV; |
| @@ -272,15 +272,15 @@ int __init omap_intc_of_init(struct device_node *node, | |||
| 272 | return -EINVAL; | 272 | return -EINVAL; |
| 273 | } | 273 | } |
| 274 | 274 | ||
| 275 | if (of_property_read_u32(node, "ti,intc-size", &nr_irqs)) | 275 | if (of_property_read_u32(node, "ti,intc-size", &nr_irq)) |
| 276 | pr_warn("unable to get intc-size, default to %d\n", nr_irqs); | 276 | pr_warn("unable to get intc-size, default to %d\n", nr_irq); |
| 277 | 277 | ||
| 278 | omap_init_irq(res.start, nr_irqs, of_node_get(node)); | 278 | omap_init_irq(res.start, nr_irq, of_node_get(node)); |
| 279 | 279 | ||
| 280 | return 0; | 280 | return 0; |
| 281 | } | 281 | } |
| 282 | 282 | ||
| 283 | #ifdef CONFIG_ARCH_OMAP3 | 283 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) |
| 284 | static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)]; | 284 | static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)]; |
| 285 | 285 | ||
| 286 | void omap_intc_save_context(void) | 286 | void omap_intc_save_context(void) |
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c index 19b8b6774862..6875be837d9f 100644 --- a/arch/arm/mach-omap2/mailbox.c +++ b/arch/arm/mach-omap2/mailbox.c | |||
| @@ -83,8 +83,6 @@ static int omap2_mbox_startup(struct omap_mbox *mbox) | |||
| 83 | l = mbox_read_reg(MAILBOX_REVISION); | 83 | l = mbox_read_reg(MAILBOX_REVISION); |
| 84 | pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f)); | 84 | pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f)); |
| 85 | 85 | ||
| 86 | omap2_mbox_enable_irq(mbox, IRQ_RX); | ||
| 87 | |||
| 88 | return 0; | 86 | return 0; |
| 89 | } | 87 | } |
| 90 | 88 | ||
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c index ac49384d0285..1be8bcb52e93 100644 --- a/arch/arm/mach-omap2/omap-iommu.c +++ b/arch/arm/mach-omap2/omap-iommu.c | |||
| @@ -73,19 +73,17 @@ static struct iommu_device omap4_devices[] = { | |||
| 73 | .da_end = 0xFFFFF000, | 73 | .da_end = 0xFFFFF000, |
| 74 | }, | 74 | }, |
| 75 | }, | 75 | }, |
| 76 | #if defined(CONFIG_MPU_TESLA_IOMMU) | ||
| 77 | { | 76 | { |
| 78 | .base = OMAP4_MMU2_BASE, | 77 | .base = OMAP4_MMU2_BASE, |
| 79 | .irq = INT_44XX_DSP_MMU, | 78 | .irq = OMAP44XX_IRQ_TESLA_MMU, |
| 80 | .pdata = { | 79 | .pdata = { |
| 81 | .name = "tesla", | 80 | .name = "tesla", |
| 82 | .nr_tlb_entries = 32, | 81 | .nr_tlb_entries = 32, |
| 83 | .clk_name = "tesla_ick", | 82 | .clk_name = "dsp_fck", |
| 84 | .da_start = 0x0, | 83 | .da_start = 0x0, |
| 85 | .da_end = 0xFFFFF000, | 84 | .da_end = 0xFFFFF000, |
| 86 | }, | 85 | }, |
| 87 | }, | 86 | }, |
| 88 | #endif | ||
| 89 | }; | 87 | }; |
| 90 | #define NR_OMAP4_IOMMU_DEVICES ARRAY_SIZE(omap4_devices) | 88 | #define NR_OMAP4_IOMMU_DEVICES ARRAY_SIZE(omap4_devices) |
| 91 | static struct platform_device *omap4_iommu_pdev[NR_OMAP4_IOMMU_DEVICES]; | 89 | static struct platform_device *omap4_iommu_pdev[NR_OMAP4_IOMMU_DEVICES]; |
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 773193670ea2..bdc1ec2edb4d 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c | |||
| @@ -166,6 +166,31 @@ | |||
| 166 | */ | 166 | */ |
| 167 | #define LINKS_PER_OCP_IF 2 | 167 | #define LINKS_PER_OCP_IF 2 |
| 168 | 168 | ||
| 169 | /** | ||
| 170 | * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations | ||
| 171 | * @enable_module: function to enable a module (via MODULEMODE) | ||
| 172 | * @disable_module: function to disable a module (via MODULEMODE) | ||
| 173 | * | ||
| 174 | * XXX Eventually this functionality will be hidden inside the PRM/CM | ||
| 175 | * device drivers. Until then, this should avoid huge blocks of cpu_is_*() | ||
| 176 | * conditionals in this code. | ||
| 177 | */ | ||
| 178 | struct omap_hwmod_soc_ops { | ||
| 179 | void (*enable_module)(struct omap_hwmod *oh); | ||
| 180 | int (*disable_module)(struct omap_hwmod *oh); | ||
| 181 | int (*wait_target_ready)(struct omap_hwmod *oh); | ||
| 182 | int (*assert_hardreset)(struct omap_hwmod *oh, | ||
| 183 | struct omap_hwmod_rst_info *ohri); | ||
| 184 | int (*deassert_hardreset)(struct omap_hwmod *oh, | ||
| 185 | struct omap_hwmod_rst_info *ohri); | ||
| 186 | int (*is_hardreset_asserted)(struct omap_hwmod *oh, | ||
| 187 | struct omap_hwmod_rst_info *ohri); | ||
| 188 | int (*init_clkdm)(struct omap_hwmod *oh); | ||
| 189 | }; | ||
| 190 | |||
| 191 | /* soc_ops: adapts the omap_hwmod code to the currently-booted SoC */ | ||
| 192 | static struct omap_hwmod_soc_ops soc_ops; | ||
| 193 | |||
| 169 | /* omap_hwmod_list contains all registered struct omap_hwmods */ | 194 | /* omap_hwmod_list contains all registered struct omap_hwmods */ |
| 170 | static LIST_HEAD(omap_hwmod_list); | 195 | static LIST_HEAD(omap_hwmod_list); |
| 171 | 196 | ||
| @@ -186,6 +211,9 @@ static struct omap_hwmod_link *linkspace; | |||
| 186 | */ | 211 | */ |
| 187 | static unsigned short free_ls, max_ls, ls_supp; | 212 | static unsigned short free_ls, max_ls, ls_supp; |
| 188 | 213 | ||
| 214 | /* inited: set to true once the hwmod code is initialized */ | ||
| 215 | static bool inited; | ||
| 216 | |||
| 189 | /* Private functions */ | 217 | /* Private functions */ |
| 190 | 218 | ||
| 191 | /** | 219 | /** |
| @@ -771,23 +799,19 @@ static void _disable_optional_clocks(struct omap_hwmod *oh) | |||
| 771 | } | 799 | } |
| 772 | 800 | ||
| 773 | /** | 801 | /** |
| 774 | * _enable_module - enable CLKCTRL modulemode on OMAP4 | 802 | * _omap4_enable_module - enable CLKCTRL modulemode on OMAP4 |
| 775 | * @oh: struct omap_hwmod * | 803 | * @oh: struct omap_hwmod * |
| 776 | * | 804 | * |
| 777 | * Enables the PRCM module mode related to the hwmod @oh. | 805 | * Enables the PRCM module mode related to the hwmod @oh. |
| 778 | * No return value. | 806 | * No return value. |
| 779 | */ | 807 | */ |
| 780 | static void _enable_module(struct omap_hwmod *oh) | 808 | static void _omap4_enable_module(struct omap_hwmod *oh) |
| 781 | { | 809 | { |
| 782 | /* The module mode does not exist prior OMAP4 */ | ||
| 783 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | ||
| 784 | return; | ||
| 785 | |||
| 786 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) | 810 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) |
| 787 | return; | 811 | return; |
| 788 | 812 | ||
| 789 | pr_debug("omap_hwmod: %s: _enable_module: %d\n", | 813 | pr_debug("omap_hwmod: %s: %s: %d\n", |
| 790 | oh->name, oh->prcm.omap4.modulemode); | 814 | oh->name, __func__, oh->prcm.omap4.modulemode); |
| 791 | 815 | ||
| 792 | omap4_cminst_module_enable(oh->prcm.omap4.modulemode, | 816 | omap4_cminst_module_enable(oh->prcm.omap4.modulemode, |
| 793 | oh->clkdm->prcm_partition, | 817 | oh->clkdm->prcm_partition, |
| @@ -807,10 +831,7 @@ static void _enable_module(struct omap_hwmod *oh) | |||
| 807 | */ | 831 | */ |
| 808 | static int _omap4_wait_target_disable(struct omap_hwmod *oh) | 832 | static int _omap4_wait_target_disable(struct omap_hwmod *oh) |
| 809 | { | 833 | { |
| 810 | if (!cpu_is_omap44xx()) | 834 | if (!oh || !oh->clkdm) |
| 811 | return 0; | ||
| 812 | |||
| 813 | if (!oh) | ||
| 814 | return -EINVAL; | 835 | return -EINVAL; |
| 815 | 836 | ||
| 816 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | 837 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) |
| @@ -1124,15 +1145,18 @@ static struct omap_hwmod_addr_space * __init _find_mpu_rt_addr_space(struct omap | |||
| 1124 | * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG | 1145 | * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG |
| 1125 | * @oh: struct omap_hwmod * | 1146 | * @oh: struct omap_hwmod * |
| 1126 | * | 1147 | * |
| 1127 | * If module is marked as SWSUP_SIDLE, force the module out of slave | 1148 | * Ensure that the OCP_SYSCONFIG register for the IP block represented |
| 1128 | * idle; otherwise, configure it for smart-idle. If module is marked | 1149 | * by @oh is set to indicate to the PRCM that the IP block is active. |
| 1129 | * as SWSUP_MSUSPEND, force the module out of master standby; | 1150 | * Usually this means placing the module into smart-idle mode and |
| 1130 | * otherwise, configure it for smart-standby. No return value. | 1151 | * smart-standby, but if there is a bug in the automatic idle handling |
| 1152 | * for the IP block, it may need to be placed into the force-idle or | ||
| 1153 | * no-idle variants of these modes. No return value. | ||
| 1131 | */ | 1154 | */ |
| 1132 | static void _enable_sysc(struct omap_hwmod *oh) | 1155 | static void _enable_sysc(struct omap_hwmod *oh) |
| 1133 | { | 1156 | { |
| 1134 | u8 idlemode, sf; | 1157 | u8 idlemode, sf; |
| 1135 | u32 v; | 1158 | u32 v; |
| 1159 | bool clkdm_act; | ||
| 1136 | 1160 | ||
| 1137 | if (!oh->class->sysc) | 1161 | if (!oh->class->sysc) |
| 1138 | return; | 1162 | return; |
| @@ -1141,8 +1165,16 @@ static void _enable_sysc(struct omap_hwmod *oh) | |||
| 1141 | sf = oh->class->sysc->sysc_flags; | 1165 | sf = oh->class->sysc->sysc_flags; |
| 1142 | 1166 | ||
| 1143 | if (sf & SYSC_HAS_SIDLEMODE) { | 1167 | if (sf & SYSC_HAS_SIDLEMODE) { |
| 1144 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? | 1168 | clkdm_act = ((oh->clkdm && |
| 1145 | HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; | 1169 | oh->clkdm->flags & CLKDM_ACTIVE_WITH_MPU) || |
| 1170 | (oh->_clk && oh->_clk->clkdm && | ||
| 1171 | oh->_clk->clkdm->flags & CLKDM_ACTIVE_WITH_MPU)); | ||
| 1172 | if (clkdm_act && !(oh->class->sysc->idlemodes & | ||
| 1173 | (SIDLE_SMART | SIDLE_SMART_WKUP))) | ||
| 1174 | idlemode = HWMOD_IDLEMODE_FORCE; | ||
| 1175 | else | ||
| 1176 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? | ||
| 1177 | HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; | ||
| 1146 | _set_slave_idlemode(oh, idlemode, &v); | 1178 | _set_slave_idlemode(oh, idlemode, &v); |
| 1147 | } | 1179 | } |
| 1148 | 1180 | ||
| @@ -1208,8 +1240,13 @@ static void _idle_sysc(struct omap_hwmod *oh) | |||
| 1208 | sf = oh->class->sysc->sysc_flags; | 1240 | sf = oh->class->sysc->sysc_flags; |
| 1209 | 1241 | ||
| 1210 | if (sf & SYSC_HAS_SIDLEMODE) { | 1242 | if (sf & SYSC_HAS_SIDLEMODE) { |
| 1211 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? | 1243 | /* XXX What about HWMOD_IDLEMODE_SMART_WKUP? */ |
| 1212 | HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART; | 1244 | if (oh->flags & HWMOD_SWSUP_SIDLE || |
| 1245 | !(oh->class->sysc->idlemodes & | ||
| 1246 | (SIDLE_SMART | SIDLE_SMART_WKUP))) | ||
| 1247 | idlemode = HWMOD_IDLEMODE_FORCE; | ||
| 1248 | else | ||
| 1249 | idlemode = HWMOD_IDLEMODE_SMART; | ||
| 1213 | _set_slave_idlemode(oh, idlemode, &v); | 1250 | _set_slave_idlemode(oh, idlemode, &v); |
| 1214 | } | 1251 | } |
| 1215 | 1252 | ||
| @@ -1285,24 +1322,20 @@ static struct omap_hwmod *_lookup(const char *name) | |||
| 1285 | 1322 | ||
| 1286 | return oh; | 1323 | return oh; |
| 1287 | } | 1324 | } |
| 1325 | |||
| 1288 | /** | 1326 | /** |
| 1289 | * _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod | 1327 | * _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod |
| 1290 | * @oh: struct omap_hwmod * | 1328 | * @oh: struct omap_hwmod * |
| 1291 | * | 1329 | * |
| 1292 | * Convert a clockdomain name stored in a struct omap_hwmod into a | 1330 | * Convert a clockdomain name stored in a struct omap_hwmod into a |
| 1293 | * clockdomain pointer, and save it into the struct omap_hwmod. | 1331 | * clockdomain pointer, and save it into the struct omap_hwmod. |
| 1294 | * return -EINVAL if clkdm_name does not exist or if the lookup failed. | 1332 | * Return -EINVAL if the clkdm_name lookup failed. |
| 1295 | */ | 1333 | */ |
| 1296 | static int _init_clkdm(struct omap_hwmod *oh) | 1334 | static int _init_clkdm(struct omap_hwmod *oh) |
| 1297 | { | 1335 | { |
| 1298 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | 1336 | if (!oh->clkdm_name) |
| 1299 | return 0; | 1337 | return 0; |
| 1300 | 1338 | ||
| 1301 | if (!oh->clkdm_name) { | ||
| 1302 | pr_warning("omap_hwmod: %s: no clkdm_name\n", oh->name); | ||
| 1303 | return -EINVAL; | ||
| 1304 | } | ||
| 1305 | |||
| 1306 | oh->clkdm = clkdm_lookup(oh->clkdm_name); | 1339 | oh->clkdm = clkdm_lookup(oh->clkdm_name); |
| 1307 | if (!oh->clkdm) { | 1340 | if (!oh->clkdm) { |
| 1308 | pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n", | 1341 | pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n", |
| @@ -1338,7 +1371,8 @@ static int _init_clocks(struct omap_hwmod *oh, void *data) | |||
| 1338 | ret |= _init_main_clk(oh); | 1371 | ret |= _init_main_clk(oh); |
| 1339 | ret |= _init_interface_clks(oh); | 1372 | ret |= _init_interface_clks(oh); |
| 1340 | ret |= _init_opt_clks(oh); | 1373 | ret |= _init_opt_clks(oh); |
| 1341 | ret |= _init_clkdm(oh); | 1374 | if (soc_ops.init_clkdm) |
| 1375 | ret |= soc_ops.init_clkdm(oh); | ||
| 1342 | 1376 | ||
| 1343 | if (!ret) | 1377 | if (!ret) |
| 1344 | oh->_state = _HWMOD_STATE_CLKS_INITED; | 1378 | oh->_state = _HWMOD_STATE_CLKS_INITED; |
| @@ -1349,53 +1383,6 @@ static int _init_clocks(struct omap_hwmod *oh, void *data) | |||
| 1349 | } | 1383 | } |
| 1350 | 1384 | ||
| 1351 | /** | 1385 | /** |
| 1352 | * _wait_target_ready - wait for a module to leave slave idle | ||
| 1353 | * @oh: struct omap_hwmod * | ||
| 1354 | * | ||
| 1355 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | ||
| 1356 | * does not have an IDLEST bit or if the module successfully leaves | ||
| 1357 | * slave idle; otherwise, pass along the return value of the | ||
| 1358 | * appropriate *_cm*_wait_module_ready() function. | ||
| 1359 | */ | ||
| 1360 | static int _wait_target_ready(struct omap_hwmod *oh) | ||
| 1361 | { | ||
| 1362 | struct omap_hwmod_ocp_if *os; | ||
| 1363 | int ret; | ||
| 1364 | |||
| 1365 | if (!oh) | ||
| 1366 | return -EINVAL; | ||
| 1367 | |||
| 1368 | if (oh->flags & HWMOD_NO_IDLEST) | ||
| 1369 | return 0; | ||
| 1370 | |||
| 1371 | os = _find_mpu_rt_port(oh); | ||
| 1372 | if (!os) | ||
| 1373 | return 0; | ||
| 1374 | |||
| 1375 | /* XXX check module SIDLEMODE */ | ||
| 1376 | |||
| 1377 | /* XXX check clock enable states */ | ||
| 1378 | |||
| 1379 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | ||
| 1380 | ret = omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs, | ||
| 1381 | oh->prcm.omap2.idlest_reg_id, | ||
| 1382 | oh->prcm.omap2.idlest_idle_bit); | ||
| 1383 | } else if (cpu_is_omap44xx()) { | ||
| 1384 | if (!oh->clkdm) | ||
| 1385 | return -EINVAL; | ||
| 1386 | |||
| 1387 | ret = omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition, | ||
| 1388 | oh->clkdm->cm_inst, | ||
| 1389 | oh->clkdm->clkdm_offs, | ||
| 1390 | oh->prcm.omap4.clkctrl_offs); | ||
| 1391 | } else { | ||
| 1392 | BUG(); | ||
| 1393 | }; | ||
| 1394 | |||
| 1395 | return ret; | ||
| 1396 | } | ||
| 1397 | |||
| 1398 | /** | ||
| 1399 | * _lookup_hardreset - fill register bit info for this hwmod/reset line | 1386 | * _lookup_hardreset - fill register bit info for this hwmod/reset line |
| 1400 | * @oh: struct omap_hwmod * | 1387 | * @oh: struct omap_hwmod * |
| 1401 | * @name: name of the reset line in the context of this hwmod | 1388 | * @name: name of the reset line in the context of this hwmod |
| @@ -1431,32 +1418,31 @@ static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name, | |||
| 1431 | * @oh: struct omap_hwmod * | 1418 | * @oh: struct omap_hwmod * |
| 1432 | * @name: name of the reset line to lookup and assert | 1419 | * @name: name of the reset line to lookup and assert |
| 1433 | * | 1420 | * |
| 1434 | * Some IP like dsp, ipu or iva contain processor that require | 1421 | * Some IP like dsp, ipu or iva contain processor that require an HW |
| 1435 | * an HW reset line to be assert / deassert in order to enable fully | 1422 | * reset line to be assert / deassert in order to enable fully the IP. |
| 1436 | * the IP. | 1423 | * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of |
| 1424 | * asserting the hardreset line on the currently-booted SoC, or passes | ||
| 1425 | * along the return value from _lookup_hardreset() or the SoC's | ||
| 1426 | * assert_hardreset code. | ||
| 1437 | */ | 1427 | */ |
| 1438 | static int _assert_hardreset(struct omap_hwmod *oh, const char *name) | 1428 | static int _assert_hardreset(struct omap_hwmod *oh, const char *name) |
| 1439 | { | 1429 | { |
| 1440 | struct omap_hwmod_rst_info ohri; | 1430 | struct omap_hwmod_rst_info ohri; |
| 1441 | u8 ret; | 1431 | u8 ret = -EINVAL; |
| 1442 | 1432 | ||
| 1443 | if (!oh) | 1433 | if (!oh) |
| 1444 | return -EINVAL; | 1434 | return -EINVAL; |
| 1445 | 1435 | ||
| 1436 | if (!soc_ops.assert_hardreset) | ||
| 1437 | return -ENOSYS; | ||
| 1438 | |||
| 1446 | ret = _lookup_hardreset(oh, name, &ohri); | 1439 | ret = _lookup_hardreset(oh, name, &ohri); |
| 1447 | if (IS_ERR_VALUE(ret)) | 1440 | if (IS_ERR_VALUE(ret)) |
| 1448 | return ret; | 1441 | return ret; |
| 1449 | 1442 | ||
| 1450 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | 1443 | ret = soc_ops.assert_hardreset(oh, &ohri); |
| 1451 | return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs, | 1444 | |
| 1452 | ohri.rst_shift); | 1445 | return ret; |
| 1453 | else if (cpu_is_omap44xx()) | ||
| 1454 | return omap4_prminst_assert_hardreset(ohri.rst_shift, | ||
| 1455 | oh->clkdm->pwrdm.ptr->prcm_partition, | ||
| 1456 | oh->clkdm->pwrdm.ptr->prcm_offs, | ||
| 1457 | oh->prcm.omap4.rstctrl_offs); | ||
| 1458 | else | ||
| 1459 | return -EINVAL; | ||
| 1460 | } | 1446 | } |
| 1461 | 1447 | ||
| 1462 | /** | 1448 | /** |
| @@ -1465,38 +1451,29 @@ static int _assert_hardreset(struct omap_hwmod *oh, const char *name) | |||
| 1465 | * @oh: struct omap_hwmod * | 1451 | * @oh: struct omap_hwmod * |
| 1466 | * @name: name of the reset line to look up and deassert | 1452 | * @name: name of the reset line to look up and deassert |
| 1467 | * | 1453 | * |
| 1468 | * Some IP like dsp, ipu or iva contain processor that require | 1454 | * Some IP like dsp, ipu or iva contain processor that require an HW |
| 1469 | * an HW reset line to be assert / deassert in order to enable fully | 1455 | * reset line to be assert / deassert in order to enable fully the IP. |
| 1470 | * the IP. | 1456 | * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of |
| 1457 | * deasserting the hardreset line on the currently-booted SoC, or passes | ||
| 1458 | * along the return value from _lookup_hardreset() or the SoC's | ||
| 1459 | * deassert_hardreset code. | ||
| 1471 | */ | 1460 | */ |
| 1472 | static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) | 1461 | static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) |
| 1473 | { | 1462 | { |
| 1474 | struct omap_hwmod_rst_info ohri; | 1463 | struct omap_hwmod_rst_info ohri; |
| 1475 | int ret; | 1464 | int ret = -EINVAL; |
| 1476 | 1465 | ||
| 1477 | if (!oh) | 1466 | if (!oh) |
| 1478 | return -EINVAL; | 1467 | return -EINVAL; |
| 1479 | 1468 | ||
| 1469 | if (!soc_ops.deassert_hardreset) | ||
| 1470 | return -ENOSYS; | ||
| 1471 | |||
| 1480 | ret = _lookup_hardreset(oh, name, &ohri); | 1472 | ret = _lookup_hardreset(oh, name, &ohri); |
| 1481 | if (IS_ERR_VALUE(ret)) | 1473 | if (IS_ERR_VALUE(ret)) |
| 1482 | return ret; | 1474 | return ret; |
| 1483 | 1475 | ||
| 1484 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | 1476 | ret = soc_ops.deassert_hardreset(oh, &ohri); |
| 1485 | ret = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs, | ||
| 1486 | ohri.rst_shift, | ||
| 1487 | ohri.st_shift); | ||
| 1488 | } else if (cpu_is_omap44xx()) { | ||
| 1489 | if (ohri.st_shift) | ||
| 1490 | pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", | ||
| 1491 | oh->name, name); | ||
| 1492 | ret = omap4_prminst_deassert_hardreset(ohri.rst_shift, | ||
| 1493 | oh->clkdm->pwrdm.ptr->prcm_partition, | ||
| 1494 | oh->clkdm->pwrdm.ptr->prcm_offs, | ||
| 1495 | oh->prcm.omap4.rstctrl_offs); | ||
| 1496 | } else { | ||
| 1497 | return -EINVAL; | ||
| 1498 | } | ||
| 1499 | |||
| 1500 | if (ret == -EBUSY) | 1477 | if (ret == -EBUSY) |
| 1501 | pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name); | 1478 | pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name); |
| 1502 | 1479 | ||
| @@ -1509,31 +1486,28 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) | |||
| 1509 | * @oh: struct omap_hwmod * | 1486 | * @oh: struct omap_hwmod * |
| 1510 | * @name: name of the reset line to look up and read | 1487 | * @name: name of the reset line to look up and read |
| 1511 | * | 1488 | * |
| 1512 | * Return the state of the reset line. | 1489 | * Return the state of the reset line. Returns -EINVAL if @oh is |
| 1490 | * null, -ENOSYS if we have no way of reading the hardreset line | ||
| 1491 | * status on the currently-booted SoC, or passes along the return | ||
| 1492 | * value from _lookup_hardreset() or the SoC's is_hardreset_asserted | ||
| 1493 | * code. | ||
| 1513 | */ | 1494 | */ |
| 1514 | static int _read_hardreset(struct omap_hwmod *oh, const char *name) | 1495 | static int _read_hardreset(struct omap_hwmod *oh, const char *name) |
| 1515 | { | 1496 | { |
| 1516 | struct omap_hwmod_rst_info ohri; | 1497 | struct omap_hwmod_rst_info ohri; |
| 1517 | u8 ret; | 1498 | u8 ret = -EINVAL; |
| 1518 | 1499 | ||
| 1519 | if (!oh) | 1500 | if (!oh) |
| 1520 | return -EINVAL; | 1501 | return -EINVAL; |
| 1521 | 1502 | ||
| 1503 | if (!soc_ops.is_hardreset_asserted) | ||
| 1504 | return -ENOSYS; | ||
| 1505 | |||
| 1522 | ret = _lookup_hardreset(oh, name, &ohri); | 1506 | ret = _lookup_hardreset(oh, name, &ohri); |
| 1523 | if (IS_ERR_VALUE(ret)) | 1507 | if (IS_ERR_VALUE(ret)) |
| 1524 | return ret; | 1508 | return ret; |
| 1525 | 1509 | ||
| 1526 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | 1510 | return soc_ops.is_hardreset_asserted(oh, &ohri); |
| 1527 | return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs, | ||
| 1528 | ohri.st_shift); | ||
| 1529 | } else if (cpu_is_omap44xx()) { | ||
| 1530 | return omap4_prminst_is_hardreset_asserted(ohri.rst_shift, | ||
| 1531 | oh->clkdm->pwrdm.ptr->prcm_partition, | ||
| 1532 | oh->clkdm->pwrdm.ptr->prcm_offs, | ||
| 1533 | oh->prcm.omap4.rstctrl_offs); | ||
| 1534 | } else { | ||
| 1535 | return -EINVAL; | ||
| 1536 | } | ||
| 1537 | } | 1511 | } |
| 1538 | 1512 | ||
| 1539 | /** | 1513 | /** |
| @@ -1571,10 +1545,6 @@ static int _omap4_disable_module(struct omap_hwmod *oh) | |||
| 1571 | { | 1545 | { |
| 1572 | int v; | 1546 | int v; |
| 1573 | 1547 | ||
| 1574 | /* The module mode does not exist prior OMAP4 */ | ||
| 1575 | if (!cpu_is_omap44xx()) | ||
| 1576 | return -EINVAL; | ||
| 1577 | |||
| 1578 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) | 1548 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) |
| 1579 | return -EINVAL; | 1549 | return -EINVAL; |
| 1580 | 1550 | ||
| @@ -1814,9 +1784,11 @@ static int _enable(struct omap_hwmod *oh) | |||
| 1814 | } | 1784 | } |
| 1815 | 1785 | ||
| 1816 | _enable_clocks(oh); | 1786 | _enable_clocks(oh); |
| 1817 | _enable_module(oh); | 1787 | if (soc_ops.enable_module) |
| 1788 | soc_ops.enable_module(oh); | ||
| 1818 | 1789 | ||
| 1819 | r = _wait_target_ready(oh); | 1790 | r = (soc_ops.wait_target_ready) ? soc_ops.wait_target_ready(oh) : |
| 1791 | -EINVAL; | ||
| 1820 | if (!r) { | 1792 | if (!r) { |
| 1821 | /* | 1793 | /* |
| 1822 | * Set the clockdomain to HW_AUTO only if the target is ready, | 1794 | * Set the clockdomain to HW_AUTO only if the target is ready, |
| @@ -1870,7 +1842,8 @@ static int _idle(struct omap_hwmod *oh) | |||
| 1870 | _idle_sysc(oh); | 1842 | _idle_sysc(oh); |
| 1871 | _del_initiator_dep(oh, mpu_oh); | 1843 | _del_initiator_dep(oh, mpu_oh); |
| 1872 | 1844 | ||
| 1873 | _omap4_disable_module(oh); | 1845 | if (soc_ops.disable_module) |
| 1846 | soc_ops.disable_module(oh); | ||
| 1874 | 1847 | ||
| 1875 | /* | 1848 | /* |
| 1876 | * The module must be in idle mode before disabling any parents | 1849 | * The module must be in idle mode before disabling any parents |
| @@ -1975,7 +1948,8 @@ static int _shutdown(struct omap_hwmod *oh) | |||
| 1975 | if (oh->_state == _HWMOD_STATE_ENABLED) { | 1948 | if (oh->_state == _HWMOD_STATE_ENABLED) { |
| 1976 | _del_initiator_dep(oh, mpu_oh); | 1949 | _del_initiator_dep(oh, mpu_oh); |
| 1977 | /* XXX what about the other system initiators here? dma, dsp */ | 1950 | /* XXX what about the other system initiators here? dma, dsp */ |
| 1978 | _omap4_disable_module(oh); | 1951 | if (soc_ops.disable_module) |
| 1952 | soc_ops.disable_module(oh); | ||
| 1979 | _disable_clocks(oh); | 1953 | _disable_clocks(oh); |
| 1980 | if (oh->clkdm) | 1954 | if (oh->clkdm) |
| 1981 | clkdm_hwmod_disable(oh->clkdm, oh); | 1955 | clkdm_hwmod_disable(oh->clkdm, oh); |
| @@ -2431,6 +2405,194 @@ static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois) | |||
| 2431 | return 0; | 2405 | return 0; |
| 2432 | } | 2406 | } |
| 2433 | 2407 | ||
| 2408 | /* Static functions intended only for use in soc_ops field function pointers */ | ||
| 2409 | |||
| 2410 | /** | ||
| 2411 | * _omap2_wait_target_ready - wait for a module to leave slave idle | ||
| 2412 | * @oh: struct omap_hwmod * | ||
| 2413 | * | ||
| 2414 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | ||
| 2415 | * does not have an IDLEST bit or if the module successfully leaves | ||
| 2416 | * slave idle; otherwise, pass along the return value of the | ||
| 2417 | * appropriate *_cm*_wait_module_ready() function. | ||
| 2418 | */ | ||
| 2419 | static int _omap2_wait_target_ready(struct omap_hwmod *oh) | ||
| 2420 | { | ||
| 2421 | if (!oh) | ||
| 2422 | return -EINVAL; | ||
| 2423 | |||
| 2424 | if (oh->flags & HWMOD_NO_IDLEST) | ||
| 2425 | return 0; | ||
| 2426 | |||
| 2427 | if (!_find_mpu_rt_port(oh)) | ||
| 2428 | return 0; | ||
| 2429 | |||
| 2430 | /* XXX check module SIDLEMODE, hardreset status, enabled clocks */ | ||
| 2431 | |||
| 2432 | return omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs, | ||
| 2433 | oh->prcm.omap2.idlest_reg_id, | ||
| 2434 | oh->prcm.omap2.idlest_idle_bit); | ||
| 2435 | } | ||
| 2436 | |||
| 2437 | /** | ||
| 2438 | * _omap4_wait_target_ready - wait for a module to leave slave idle | ||
| 2439 | * @oh: struct omap_hwmod * | ||
| 2440 | * | ||
| 2441 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | ||
| 2442 | * does not have an IDLEST bit or if the module successfully leaves | ||
| 2443 | * slave idle; otherwise, pass along the return value of the | ||
| 2444 | * appropriate *_cm*_wait_module_ready() function. | ||
| 2445 | */ | ||
| 2446 | static int _omap4_wait_target_ready(struct omap_hwmod *oh) | ||
| 2447 | { | ||
| 2448 | if (!oh || !oh->clkdm) | ||
| 2449 | return -EINVAL; | ||
| 2450 | |||
| 2451 | if (oh->flags & HWMOD_NO_IDLEST) | ||
| 2452 | return 0; | ||
| 2453 | |||
| 2454 | if (!_find_mpu_rt_port(oh)) | ||
| 2455 | return 0; | ||
| 2456 | |||
| 2457 | /* XXX check module SIDLEMODE, hardreset status */ | ||
| 2458 | |||
| 2459 | return omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition, | ||
| 2460 | oh->clkdm->cm_inst, | ||
| 2461 | oh->clkdm->clkdm_offs, | ||
| 2462 | oh->prcm.omap4.clkctrl_offs); | ||
| 2463 | } | ||
| 2464 | |||
| 2465 | /** | ||
| 2466 | * _omap2_assert_hardreset - call OMAP2 PRM hardreset fn with hwmod args | ||
| 2467 | * @oh: struct omap_hwmod * to assert hardreset | ||
| 2468 | * @ohri: hardreset line data | ||
| 2469 | * | ||
| 2470 | * Call omap2_prm_assert_hardreset() with parameters extracted from | ||
| 2471 | * the hwmod @oh and the hardreset line data @ohri. Only intended for | ||
| 2472 | * use as an soc_ops function pointer. Passes along the return value | ||
| 2473 | * from omap2_prm_assert_hardreset(). XXX This function is scheduled | ||
| 2474 | * for removal when the PRM code is moved into drivers/. | ||
| 2475 | */ | ||
| 2476 | static int _omap2_assert_hardreset(struct omap_hwmod *oh, | ||
| 2477 | struct omap_hwmod_rst_info *ohri) | ||
| 2478 | { | ||
| 2479 | return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs, | ||
| 2480 | ohri->rst_shift); | ||
| 2481 | } | ||
| 2482 | |||
| 2483 | /** | ||
| 2484 | * _omap2_deassert_hardreset - call OMAP2 PRM hardreset fn with hwmod args | ||
| 2485 | * @oh: struct omap_hwmod * to deassert hardreset | ||
| 2486 | * @ohri: hardreset line data | ||
| 2487 | * | ||
| 2488 | * Call omap2_prm_deassert_hardreset() with parameters extracted from | ||
| 2489 | * the hwmod @oh and the hardreset line data @ohri. Only intended for | ||
| 2490 | * use as an soc_ops function pointer. Passes along the return value | ||
| 2491 | * from omap2_prm_deassert_hardreset(). XXX This function is | ||
| 2492 | * scheduled for removal when the PRM code is moved into drivers/. | ||
| 2493 | */ | ||
| 2494 | static int _omap2_deassert_hardreset(struct omap_hwmod *oh, | ||
| 2495 | struct omap_hwmod_rst_info *ohri) | ||
| 2496 | { | ||
| 2497 | return omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs, | ||
| 2498 | ohri->rst_shift, | ||
| 2499 | ohri->st_shift); | ||
| 2500 | } | ||
| 2501 | |||
| 2502 | /** | ||
| 2503 | * _omap2_is_hardreset_asserted - call OMAP2 PRM hardreset fn with hwmod args | ||
| 2504 | * @oh: struct omap_hwmod * to test hardreset | ||
| 2505 | * @ohri: hardreset line data | ||
| 2506 | * | ||
| 2507 | * Call omap2_prm_is_hardreset_asserted() with parameters extracted | ||
| 2508 | * from the hwmod @oh and the hardreset line data @ohri. Only | ||
| 2509 | * intended for use as an soc_ops function pointer. Passes along the | ||
| 2510 | * return value from omap2_prm_is_hardreset_asserted(). XXX This | ||
| 2511 | * function is scheduled for removal when the PRM code is moved into | ||
| 2512 | * drivers/. | ||
| 2513 | */ | ||
| 2514 | static int _omap2_is_hardreset_asserted(struct omap_hwmod *oh, | ||
| 2515 | struct omap_hwmod_rst_info *ohri) | ||
| 2516 | { | ||
| 2517 | return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs, | ||
| 2518 | ohri->st_shift); | ||
| 2519 | } | ||
| 2520 | |||
| 2521 | /** | ||
| 2522 | * _omap4_assert_hardreset - call OMAP4 PRM hardreset fn with hwmod args | ||
| 2523 | * @oh: struct omap_hwmod * to assert hardreset | ||
| 2524 | * @ohri: hardreset line data | ||
| 2525 | * | ||
| 2526 | * Call omap4_prminst_assert_hardreset() with parameters extracted | ||
| 2527 | * from the hwmod @oh and the hardreset line data @ohri. Only | ||
| 2528 | * intended for use as an soc_ops function pointer. Passes along the | ||
| 2529 | * return value from omap4_prminst_assert_hardreset(). XXX This | ||
| 2530 | * function is scheduled for removal when the PRM code is moved into | ||
| 2531 | * drivers/. | ||
| 2532 | */ | ||
| 2533 | static int _omap4_assert_hardreset(struct omap_hwmod *oh, | ||
| 2534 | struct omap_hwmod_rst_info *ohri) | ||
| 2535 | { | ||
| 2536 | if (!oh->clkdm) | ||
| 2537 | return -EINVAL; | ||
| 2538 | |||
| 2539 | return omap4_prminst_assert_hardreset(ohri->rst_shift, | ||
| 2540 | oh->clkdm->pwrdm.ptr->prcm_partition, | ||
| 2541 | oh->clkdm->pwrdm.ptr->prcm_offs, | ||
| 2542 | oh->prcm.omap4.rstctrl_offs); | ||
| 2543 | } | ||
| 2544 | |||
| 2545 | /** | ||
| 2546 | * _omap4_deassert_hardreset - call OMAP4 PRM hardreset fn with hwmod args | ||
| 2547 | * @oh: struct omap_hwmod * to deassert hardreset | ||
| 2548 | * @ohri: hardreset line data | ||
| 2549 | * | ||
| 2550 | * Call omap4_prminst_deassert_hardreset() with parameters extracted | ||
| 2551 | * from the hwmod @oh and the hardreset line data @ohri. Only | ||
| 2552 | * intended for use as an soc_ops function pointer. Passes along the | ||
| 2553 | * return value from omap4_prminst_deassert_hardreset(). XXX This | ||
| 2554 | * function is scheduled for removal when the PRM code is moved into | ||
| 2555 | * drivers/. | ||
| 2556 | */ | ||
| 2557 | static int _omap4_deassert_hardreset(struct omap_hwmod *oh, | ||
| 2558 | struct omap_hwmod_rst_info *ohri) | ||
| 2559 | { | ||
| 2560 | if (!oh->clkdm) | ||
| 2561 | return -EINVAL; | ||
| 2562 | |||
| 2563 | if (ohri->st_shift) | ||
| 2564 | pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", | ||
| 2565 | oh->name, ohri->name); | ||
| 2566 | return omap4_prminst_deassert_hardreset(ohri->rst_shift, | ||
| 2567 | oh->clkdm->pwrdm.ptr->prcm_partition, | ||
| 2568 | oh->clkdm->pwrdm.ptr->prcm_offs, | ||
| 2569 | oh->prcm.omap4.rstctrl_offs); | ||
| 2570 | } | ||
| 2571 | |||
| 2572 | /** | ||
| 2573 | * _omap4_is_hardreset_asserted - call OMAP4 PRM hardreset fn with hwmod args | ||
| 2574 | * @oh: struct omap_hwmod * to test hardreset | ||
| 2575 | * @ohri: hardreset line data | ||
| 2576 | * | ||
| 2577 | * Call omap4_prminst_is_hardreset_asserted() with parameters | ||
| 2578 | * extracted from the hwmod @oh and the hardreset line data @ohri. | ||
| 2579 | * Only intended for use as an soc_ops function pointer. Passes along | ||
| 2580 | * the return value from omap4_prminst_is_hardreset_asserted(). XXX | ||
| 2581 | * This function is scheduled for removal when the PRM code is moved | ||
| 2582 | * into drivers/. | ||
| 2583 | */ | ||
| 2584 | static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh, | ||
| 2585 | struct omap_hwmod_rst_info *ohri) | ||
| 2586 | { | ||
| 2587 | if (!oh->clkdm) | ||
| 2588 | return -EINVAL; | ||
| 2589 | |||
| 2590 | return omap4_prminst_is_hardreset_asserted(ohri->rst_shift, | ||
| 2591 | oh->clkdm->pwrdm.ptr->prcm_partition, | ||
| 2592 | oh->clkdm->pwrdm.ptr->prcm_offs, | ||
| 2593 | oh->prcm.omap4.rstctrl_offs); | ||
| 2594 | } | ||
| 2595 | |||
| 2434 | /* Public functions */ | 2596 | /* Public functions */ |
| 2435 | 2597 | ||
| 2436 | u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) | 2598 | u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) |
| @@ -2563,12 +2725,18 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), | |||
| 2563 | * | 2725 | * |
| 2564 | * Intended to be called early in boot before the clock framework is | 2726 | * Intended to be called early in boot before the clock framework is |
| 2565 | * initialized. If @ois is not null, will register all omap_hwmods | 2727 | * initialized. If @ois is not null, will register all omap_hwmods |
| 2566 | * listed in @ois that are valid for this chip. Returns 0. | 2728 | * listed in @ois that are valid for this chip. Returns -EINVAL if |
| 2729 | * omap_hwmod_init() hasn't been called before calling this function, | ||
| 2730 | * -ENOMEM if the link memory area can't be allocated, or 0 upon | ||
| 2731 | * success. | ||
| 2567 | */ | 2732 | */ |
| 2568 | int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois) | 2733 | int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois) |
| 2569 | { | 2734 | { |
| 2570 | int r, i; | 2735 | int r, i; |
| 2571 | 2736 | ||
| 2737 | if (!inited) | ||
| 2738 | return -EINVAL; | ||
| 2739 | |||
| 2572 | if (!ois) | 2740 | if (!ois) |
| 2573 | return 0; | 2741 | return 0; |
| 2574 | 2742 | ||
| @@ -3401,3 +3569,32 @@ int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx) | |||
| 3401 | 3569 | ||
| 3402 | return 0; | 3570 | return 0; |
| 3403 | } | 3571 | } |
| 3572 | |||
| 3573 | /** | ||
| 3574 | * omap_hwmod_init - initialize the hwmod code | ||
| 3575 | * | ||
| 3576 | * Sets up some function pointers needed by the hwmod code to operate on the | ||
| 3577 | * currently-booted SoC. Intended to be called once during kernel init | ||
| 3578 | * before any hwmods are registered. No return value. | ||
| 3579 | */ | ||
| 3580 | void __init omap_hwmod_init(void) | ||
| 3581 | { | ||
| 3582 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | ||
| 3583 | soc_ops.wait_target_ready = _omap2_wait_target_ready; | ||
| 3584 | soc_ops.assert_hardreset = _omap2_assert_hardreset; | ||
| 3585 | soc_ops.deassert_hardreset = _omap2_deassert_hardreset; | ||
| 3586 | soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; | ||
| 3587 | } else if (cpu_is_omap44xx()) { | ||
| 3588 | soc_ops.enable_module = _omap4_enable_module; | ||
| 3589 | soc_ops.disable_module = _omap4_disable_module; | ||
| 3590 | soc_ops.wait_target_ready = _omap4_wait_target_ready; | ||
| 3591 | soc_ops.assert_hardreset = _omap4_assert_hardreset; | ||
| 3592 | soc_ops.deassert_hardreset = _omap4_deassert_hardreset; | ||
| 3593 | soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted; | ||
| 3594 | soc_ops.init_clkdm = _init_clkdm; | ||
| 3595 | } else { | ||
| 3596 | WARN(1, "omap_hwmod: unknown SoC type\n"); | ||
| 3597 | } | ||
| 3598 | |||
| 3599 | inited = true; | ||
| 3600 | } | ||
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index a7640d1b215e..50cfab61b0e2 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c | |||
| @@ -192,6 +192,11 @@ static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = { | |||
| 192 | .name = "mcbsp", | 192 | .name = "mcbsp", |
| 193 | }; | 193 | }; |
| 194 | 194 | ||
| 195 | static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = { | ||
| 196 | { .role = "pad_fck", .clk = "mcbsp_clks" }, | ||
| 197 | { .role = "prcm_fck", .clk = "func_96m_ck" }, | ||
| 198 | }; | ||
| 199 | |||
| 195 | /* mcbsp1 */ | 200 | /* mcbsp1 */ |
| 196 | static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { | 201 | static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { |
| 197 | { .name = "tx", .irq = 59 }, | 202 | { .name = "tx", .irq = 59 }, |
| @@ -214,6 +219,8 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = { | |||
| 214 | .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, | 219 | .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, |
| 215 | }, | 220 | }, |
| 216 | }, | 221 | }, |
| 222 | .opt_clks = mcbsp_opt_clks, | ||
| 223 | .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), | ||
| 217 | }; | 224 | }; |
| 218 | 225 | ||
| 219 | /* mcbsp2 */ | 226 | /* mcbsp2 */ |
| @@ -238,6 +245,8 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = { | |||
| 238 | .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, | 245 | .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, |
| 239 | }, | 246 | }, |
| 240 | }, | 247 | }, |
| 248 | .opt_clks = mcbsp_opt_clks, | ||
| 249 | .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), | ||
| 241 | }; | 250 | }; |
| 242 | 251 | ||
| 243 | static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = { | 252 | static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = { |
| @@ -585,5 +594,6 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { | |||
| 585 | 594 | ||
| 586 | int __init omap2420_hwmod_init(void) | 595 | int __init omap2420_hwmod_init(void) |
| 587 | { | 596 | { |
| 597 | omap_hwmod_init(); | ||
| 588 | return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs); | 598 | return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs); |
| 589 | } | 599 | } |
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 4d7264981230..58b5bc196d32 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c | |||
| @@ -296,6 +296,11 @@ static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = { | |||
| 296 | .rev = MCBSP_CONFIG_TYPE2, | 296 | .rev = MCBSP_CONFIG_TYPE2, |
| 297 | }; | 297 | }; |
| 298 | 298 | ||
| 299 | static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = { | ||
| 300 | { .role = "pad_fck", .clk = "mcbsp_clks" }, | ||
| 301 | { .role = "prcm_fck", .clk = "func_96m_ck" }, | ||
| 302 | }; | ||
| 303 | |||
| 299 | /* mcbsp1 */ | 304 | /* mcbsp1 */ |
| 300 | static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = { | 305 | static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = { |
| 301 | { .name = "tx", .irq = 59 }, | 306 | { .name = "tx", .irq = 59 }, |
| @@ -320,6 +325,8 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = { | |||
| 320 | .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, | 325 | .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, |
| 321 | }, | 326 | }, |
| 322 | }, | 327 | }, |
| 328 | .opt_clks = mcbsp_opt_clks, | ||
| 329 | .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), | ||
| 323 | }; | 330 | }; |
| 324 | 331 | ||
| 325 | /* mcbsp2 */ | 332 | /* mcbsp2 */ |
| @@ -345,6 +352,8 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = { | |||
| 345 | .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, | 352 | .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, |
| 346 | }, | 353 | }, |
| 347 | }, | 354 | }, |
| 355 | .opt_clks = mcbsp_opt_clks, | ||
| 356 | .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), | ||
| 348 | }; | 357 | }; |
| 349 | 358 | ||
| 350 | /* mcbsp3 */ | 359 | /* mcbsp3 */ |
| @@ -370,6 +379,8 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = { | |||
| 370 | .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT, | 379 | .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT, |
| 371 | }, | 380 | }, |
| 372 | }, | 381 | }, |
| 382 | .opt_clks = mcbsp_opt_clks, | ||
| 383 | .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), | ||
| 373 | }; | 384 | }; |
| 374 | 385 | ||
| 375 | /* mcbsp4 */ | 386 | /* mcbsp4 */ |
| @@ -401,6 +412,8 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = { | |||
| 401 | .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT, | 412 | .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT, |
| 402 | }, | 413 | }, |
| 403 | }, | 414 | }, |
| 415 | .opt_clks = mcbsp_opt_clks, | ||
| 416 | .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), | ||
| 404 | }; | 417 | }; |
| 405 | 418 | ||
| 406 | /* mcbsp5 */ | 419 | /* mcbsp5 */ |
| @@ -432,6 +445,8 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = { | |||
| 432 | .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT, | 445 | .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT, |
| 433 | }, | 446 | }, |
| 434 | }, | 447 | }, |
| 448 | .opt_clks = mcbsp_opt_clks, | ||
| 449 | .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), | ||
| 435 | }; | 450 | }; |
| 436 | 451 | ||
| 437 | /* MMC/SD/SDIO common */ | 452 | /* MMC/SD/SDIO common */ |
| @@ -938,5 +953,6 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { | |||
| 938 | 953 | ||
| 939 | int __init omap2430_hwmod_init(void) | 954 | int __init omap2430_hwmod_init(void) |
| 940 | { | 955 | { |
| 956 | omap_hwmod_init(); | ||
| 941 | return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs); | 957 | return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs); |
| 942 | } | 958 | } |
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index b26d3c9bca16..892c7c740976 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | |||
| @@ -527,11 +527,27 @@ static struct omap_hwmod omap36xx_uart4_hwmod = { | |||
| 527 | 527 | ||
| 528 | static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = { | 528 | static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = { |
| 529 | { .irq = INT_35XX_UART4_IRQ, }, | 529 | { .irq = INT_35XX_UART4_IRQ, }, |
| 530 | { .irq = -1 } | ||
| 530 | }; | 531 | }; |
| 531 | 532 | ||
| 532 | static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { | 533 | static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { |
| 533 | { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, }, | 534 | { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, }, |
| 534 | { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, }, | 535 | { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, }, |
| 536 | { .dma_req = -1 } | ||
| 537 | }; | ||
| 538 | |||
| 539 | /* | ||
| 540 | * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or | ||
| 541 | * uart2_fck being enabled. So we add uart1_fck as an optional clock, | ||
| 542 | * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really | ||
| 543 | * should not be needed. The functional clock structure of the AM35xx | ||
| 544 | * UART4 is extremely unclear and opaque; it is unclear what the role | ||
| 545 | * of uart1/2_fck is for the UART4. Any clarification from either | ||
| 546 | * empirical testing or the AM3505/3517 hardware designers would be | ||
| 547 | * most welcome. | ||
| 548 | */ | ||
| 549 | static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = { | ||
| 550 | { .role = "softreset_uart1_fck", .clk = "uart1_fck" }, | ||
| 535 | }; | 551 | }; |
| 536 | 552 | ||
| 537 | static struct omap_hwmod am35xx_uart4_hwmod = { | 553 | static struct omap_hwmod am35xx_uart4_hwmod = { |
| @@ -543,11 +559,14 @@ static struct omap_hwmod am35xx_uart4_hwmod = { | |||
| 543 | .omap2 = { | 559 | .omap2 = { |
| 544 | .module_offs = CORE_MOD, | 560 | .module_offs = CORE_MOD, |
| 545 | .prcm_reg_id = 1, | 561 | .prcm_reg_id = 1, |
| 546 | .module_bit = OMAP3430_EN_UART4_SHIFT, | 562 | .module_bit = AM35XX_EN_UART4_SHIFT, |
| 547 | .idlest_reg_id = 1, | 563 | .idlest_reg_id = 1, |
| 548 | .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT, | 564 | .idlest_idle_bit = AM35XX_ST_UART4_SHIFT, |
| 549 | }, | 565 | }, |
| 550 | }, | 566 | }, |
| 567 | .opt_clks = am35xx_uart4_opt_clks, | ||
| 568 | .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks), | ||
| 569 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | ||
| 551 | .class = &omap2_uart_class, | 570 | .class = &omap2_uart_class, |
| 552 | }; | 571 | }; |
| 553 | 572 | ||
| @@ -1074,6 +1093,17 @@ static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { | |||
| 1074 | .rev = MCBSP_CONFIG_TYPE3, | 1093 | .rev = MCBSP_CONFIG_TYPE3, |
| 1075 | }; | 1094 | }; |
| 1076 | 1095 | ||
| 1096 | /* McBSP functional clock mapping */ | ||
| 1097 | static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = { | ||
| 1098 | { .role = "pad_fck", .clk = "mcbsp_clks" }, | ||
| 1099 | { .role = "prcm_fck", .clk = "core_96m_fck" }, | ||
| 1100 | }; | ||
| 1101 | |||
| 1102 | static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = { | ||
| 1103 | { .role = "pad_fck", .clk = "mcbsp_clks" }, | ||
| 1104 | { .role = "prcm_fck", .clk = "per_96m_fck" }, | ||
| 1105 | }; | ||
| 1106 | |||
| 1077 | /* mcbsp1 */ | 1107 | /* mcbsp1 */ |
| 1078 | static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { | 1108 | static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { |
| 1079 | { .name = "common", .irq = 16 }, | 1109 | { .name = "common", .irq = 16 }, |
| @@ -1097,6 +1127,8 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { | |||
| 1097 | .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, | 1127 | .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, |
| 1098 | }, | 1128 | }, |
| 1099 | }, | 1129 | }, |
| 1130 | .opt_clks = mcbsp15_opt_clks, | ||
| 1131 | .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks), | ||
| 1100 | }; | 1132 | }; |
| 1101 | 1133 | ||
| 1102 | /* mcbsp2 */ | 1134 | /* mcbsp2 */ |
| @@ -1126,6 +1158,8 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { | |||
| 1126 | .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, | 1158 | .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, |
| 1127 | }, | 1159 | }, |
| 1128 | }, | 1160 | }, |
| 1161 | .opt_clks = mcbsp234_opt_clks, | ||
| 1162 | .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), | ||
| 1129 | .dev_attr = &omap34xx_mcbsp2_dev_attr, | 1163 | .dev_attr = &omap34xx_mcbsp2_dev_attr, |
| 1130 | }; | 1164 | }; |
| 1131 | 1165 | ||
| @@ -1156,6 +1190,8 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { | |||
| 1156 | .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, | 1190 | .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, |
| 1157 | }, | 1191 | }, |
| 1158 | }, | 1192 | }, |
| 1193 | .opt_clks = mcbsp234_opt_clks, | ||
| 1194 | .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), | ||
| 1159 | .dev_attr = &omap34xx_mcbsp3_dev_attr, | 1195 | .dev_attr = &omap34xx_mcbsp3_dev_attr, |
| 1160 | }; | 1196 | }; |
| 1161 | 1197 | ||
| @@ -1188,6 +1224,8 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { | |||
| 1188 | .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, | 1224 | .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, |
| 1189 | }, | 1225 | }, |
| 1190 | }, | 1226 | }, |
| 1227 | .opt_clks = mcbsp234_opt_clks, | ||
| 1228 | .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), | ||
| 1191 | }; | 1229 | }; |
| 1192 | 1230 | ||
| 1193 | /* mcbsp5 */ | 1231 | /* mcbsp5 */ |
| @@ -1219,6 +1257,8 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { | |||
| 1219 | .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, | 1257 | .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, |
| 1220 | }, | 1258 | }, |
| 1221 | }, | 1259 | }, |
| 1260 | .opt_clks = mcbsp15_opt_clks, | ||
| 1261 | .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks), | ||
| 1222 | }; | 1262 | }; |
| 1223 | 1263 | ||
| 1224 | /* 'mcbsp sidetone' class */ | 1264 | /* 'mcbsp sidetone' class */ |
| @@ -1638,25 +1678,20 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { | |||
| 1638 | 1678 | ||
| 1639 | /* usb_otg_hs */ | 1679 | /* usb_otg_hs */ |
| 1640 | static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { | 1680 | static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { |
| 1641 | |||
| 1642 | { .name = "mc", .irq = 71 }, | 1681 | { .name = "mc", .irq = 71 }, |
| 1643 | { .irq = -1 } | 1682 | { .irq = -1 } |
| 1644 | }; | 1683 | }; |
| 1645 | 1684 | ||
| 1646 | static struct omap_hwmod_class am35xx_usbotg_class = { | 1685 | static struct omap_hwmod_class am35xx_usbotg_class = { |
| 1647 | .name = "am35xx_usbotg", | 1686 | .name = "am35xx_usbotg", |
| 1648 | .sysc = NULL, | ||
| 1649 | }; | 1687 | }; |
| 1650 | 1688 | ||
| 1651 | static struct omap_hwmod am35xx_usbhsotg_hwmod = { | 1689 | static struct omap_hwmod am35xx_usbhsotg_hwmod = { |
| 1652 | .name = "am35x_otg_hs", | 1690 | .name = "am35x_otg_hs", |
| 1653 | .mpu_irqs = am35xx_usbhsotg_mpu_irqs, | 1691 | .mpu_irqs = am35xx_usbhsotg_mpu_irqs, |
| 1654 | .main_clk = NULL, | 1692 | .main_clk = "hsotgusb_fck", |
| 1655 | .prcm = { | ||
| 1656 | .omap2 = { | ||
| 1657 | }, | ||
| 1658 | }, | ||
| 1659 | .class = &am35xx_usbotg_class, | 1693 | .class = &am35xx_usbotg_class, |
| 1694 | .flags = HWMOD_NO_IDLEST, | ||
| 1660 | }; | 1695 | }; |
| 1661 | 1696 | ||
| 1662 | /* MMC/SD/SDIO common */ | 1697 | /* MMC/SD/SDIO common */ |
| @@ -2097,9 +2132,10 @@ static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { | |||
| 2097 | static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { | 2132 | static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { |
| 2098 | .master = &am35xx_usbhsotg_hwmod, | 2133 | .master = &am35xx_usbhsotg_hwmod, |
| 2099 | .slave = &omap3xxx_l3_main_hwmod, | 2134 | .slave = &omap3xxx_l3_main_hwmod, |
| 2100 | .clk = "core_l3_ick", | 2135 | .clk = "hsotgusb_ick", |
| 2101 | .user = OCP_USER_MPU, | 2136 | .user = OCP_USER_MPU, |
| 2102 | }; | 2137 | }; |
| 2138 | |||
| 2103 | /* L4_CORE -> L4_WKUP interface */ | 2139 | /* L4_CORE -> L4_WKUP interface */ |
| 2104 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { | 2140 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { |
| 2105 | .master = &omap3xxx_l4_core_hwmod, | 2141 | .master = &omap3xxx_l4_core_hwmod, |
| @@ -2243,6 +2279,7 @@ static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = { | |||
| 2243 | .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1, | 2279 | .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1, |
| 2244 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | 2280 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, |
| 2245 | }, | 2281 | }, |
| 2282 | { } | ||
| 2246 | }; | 2283 | }; |
| 2247 | 2284 | ||
| 2248 | static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { | 2285 | static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { |
| @@ -2393,7 +2430,7 @@ static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = { | |||
| 2393 | static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { | 2430 | static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { |
| 2394 | .master = &omap3xxx_l4_core_hwmod, | 2431 | .master = &omap3xxx_l4_core_hwmod, |
| 2395 | .slave = &am35xx_usbhsotg_hwmod, | 2432 | .slave = &am35xx_usbhsotg_hwmod, |
| 2396 | .clk = "l4_ick", | 2433 | .clk = "hsotgusb_ick", |
| 2397 | .addr = am35xx_usbhsotg_addrs, | 2434 | .addr = am35xx_usbhsotg_addrs, |
| 2398 | .user = OCP_USER_MPU, | 2435 | .user = OCP_USER_MPU, |
| 2399 | }; | 2436 | }; |
| @@ -3138,6 +3175,107 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = { | |||
| 3138 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 3175 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3139 | }; | 3176 | }; |
| 3140 | 3177 | ||
| 3178 | /* am35xx has Davinci MDIO & EMAC */ | ||
| 3179 | static struct omap_hwmod_class am35xx_mdio_class = { | ||
| 3180 | .name = "davinci_mdio", | ||
| 3181 | }; | ||
| 3182 | |||
| 3183 | static struct omap_hwmod am35xx_mdio_hwmod = { | ||
| 3184 | .name = "davinci_mdio", | ||
| 3185 | .class = &am35xx_mdio_class, | ||
| 3186 | .flags = HWMOD_NO_IDLEST, | ||
| 3187 | }; | ||
| 3188 | |||
| 3189 | /* | ||
| 3190 | * XXX Should be connected to an IPSS hwmod, not the L3 directly; | ||
| 3191 | * but this will probably require some additional hwmod core support, | ||
| 3192 | * so is left as a future to-do item. | ||
| 3193 | */ | ||
| 3194 | static struct omap_hwmod_ocp_if am35xx_mdio__l3 = { | ||
| 3195 | .master = &am35xx_mdio_hwmod, | ||
| 3196 | .slave = &omap3xxx_l3_main_hwmod, | ||
| 3197 | .clk = "emac_fck", | ||
| 3198 | .user = OCP_USER_MPU, | ||
| 3199 | }; | ||
| 3200 | |||
| 3201 | static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = { | ||
| 3202 | { | ||
| 3203 | .pa_start = AM35XX_IPSS_MDIO_BASE, | ||
| 3204 | .pa_end = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1, | ||
| 3205 | .flags = ADDR_TYPE_RT, | ||
| 3206 | }, | ||
| 3207 | { } | ||
| 3208 | }; | ||
| 3209 | |||
| 3210 | /* l4_core -> davinci mdio */ | ||
| 3211 | /* | ||
| 3212 | * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; | ||
| 3213 | * but this will probably require some additional hwmod core support, | ||
| 3214 | * so is left as a future to-do item. | ||
| 3215 | */ | ||
| 3216 | static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = { | ||
| 3217 | .master = &omap3xxx_l4_core_hwmod, | ||
| 3218 | .slave = &am35xx_mdio_hwmod, | ||
| 3219 | .clk = "emac_fck", | ||
| 3220 | .addr = am35xx_mdio_addrs, | ||
| 3221 | .user = OCP_USER_MPU, | ||
| 3222 | }; | ||
| 3223 | |||
| 3224 | static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = { | ||
| 3225 | { .name = "rxthresh", .irq = INT_35XX_EMAC_C0_RXTHRESH_IRQ }, | ||
| 3226 | { .name = "rx_pulse", .irq = INT_35XX_EMAC_C0_RX_PULSE_IRQ }, | ||
| 3227 | { .name = "tx_pulse", .irq = INT_35XX_EMAC_C0_TX_PULSE_IRQ }, | ||
| 3228 | { .name = "misc_pulse", .irq = INT_35XX_EMAC_C0_MISC_PULSE_IRQ }, | ||
| 3229 | { .irq = -1 } | ||
| 3230 | }; | ||
| 3231 | |||
| 3232 | static struct omap_hwmod_class am35xx_emac_class = { | ||
| 3233 | .name = "davinci_emac", | ||
| 3234 | }; | ||
| 3235 | |||
| 3236 | static struct omap_hwmod am35xx_emac_hwmod = { | ||
| 3237 | .name = "davinci_emac", | ||
| 3238 | .mpu_irqs = am35xx_emac_mpu_irqs, | ||
| 3239 | .class = &am35xx_emac_class, | ||
| 3240 | .flags = HWMOD_NO_IDLEST, | ||
| 3241 | }; | ||
| 3242 | |||
| 3243 | /* l3_core -> davinci emac interface */ | ||
| 3244 | /* | ||
| 3245 | * XXX Should be connected to an IPSS hwmod, not the L3 directly; | ||
| 3246 | * but this will probably require some additional hwmod core support, | ||
| 3247 | * so is left as a future to-do item. | ||
| 3248 | */ | ||
| 3249 | static struct omap_hwmod_ocp_if am35xx_emac__l3 = { | ||
| 3250 | .master = &am35xx_emac_hwmod, | ||
| 3251 | .slave = &omap3xxx_l3_main_hwmod, | ||
| 3252 | .clk = "emac_ick", | ||
| 3253 | .user = OCP_USER_MPU, | ||
| 3254 | }; | ||
| 3255 | |||
| 3256 | static struct omap_hwmod_addr_space am35xx_emac_addrs[] = { | ||
| 3257 | { | ||
| 3258 | .pa_start = AM35XX_IPSS_EMAC_BASE, | ||
| 3259 | .pa_end = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1, | ||
| 3260 | .flags = ADDR_TYPE_RT, | ||
| 3261 | }, | ||
| 3262 | { } | ||
| 3263 | }; | ||
| 3264 | |||
| 3265 | /* l4_core -> davinci emac */ | ||
| 3266 | /* | ||
| 3267 | * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; | ||
| 3268 | * but this will probably require some additional hwmod core support, | ||
| 3269 | * so is left as a future to-do item. | ||
| 3270 | */ | ||
| 3271 | static struct omap_hwmod_ocp_if am35xx_l4_core__emac = { | ||
| 3272 | .master = &omap3xxx_l4_core_hwmod, | ||
| 3273 | .slave = &am35xx_emac_hwmod, | ||
| 3274 | .clk = "emac_ick", | ||
| 3275 | .addr = am35xx_emac_addrs, | ||
| 3276 | .user = OCP_USER_MPU, | ||
| 3277 | }; | ||
| 3278 | |||
| 3141 | static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { | 3279 | static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { |
| 3142 | &omap3xxx_l3_main__l4_core, | 3280 | &omap3xxx_l3_main__l4_core, |
| 3143 | &omap3xxx_l3_main__l4_per, | 3281 | &omap3xxx_l3_main__l4_per, |
| @@ -3266,6 +3404,10 @@ static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = { | |||
| 3266 | &omap3xxx_l4_core__usb_tll_hs, | 3404 | &omap3xxx_l4_core__usb_tll_hs, |
| 3267 | &omap3xxx_l4_core__es3plus_mmc1, | 3405 | &omap3xxx_l4_core__es3plus_mmc1, |
| 3268 | &omap3xxx_l4_core__es3plus_mmc2, | 3406 | &omap3xxx_l4_core__es3plus_mmc2, |
| 3407 | &am35xx_mdio__l3, | ||
| 3408 | &am35xx_l4_core__mdio, | ||
| 3409 | &am35xx_emac__l3, | ||
| 3410 | &am35xx_l4_core__emac, | ||
| 3269 | NULL | 3411 | NULL |
| 3270 | }; | 3412 | }; |
| 3271 | 3413 | ||
| @@ -3283,6 +3425,8 @@ int __init omap3xxx_hwmod_init(void) | |||
| 3283 | struct omap_hwmod_ocp_if **h = NULL; | 3425 | struct omap_hwmod_ocp_if **h = NULL; |
| 3284 | unsigned int rev; | 3426 | unsigned int rev; |
| 3285 | 3427 | ||
| 3428 | omap_hwmod_init(); | ||
| 3429 | |||
| 3286 | /* Register hwmod links common to all OMAP3 */ | 3430 | /* Register hwmod links common to all OMAP3 */ |
| 3287 | r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs); | 3431 | r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs); |
| 3288 | if (r < 0) | 3432 | if (r < 0) |
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index b7bcba5221ba..4cab6318d33e 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c | |||
| @@ -2544,14 +2544,12 @@ static struct omap_hwmod omap44xx_prcm_mpu_hwmod = { | |||
| 2544 | static struct omap_hwmod omap44xx_cm_core_aon_hwmod = { | 2544 | static struct omap_hwmod omap44xx_cm_core_aon_hwmod = { |
| 2545 | .name = "cm_core_aon", | 2545 | .name = "cm_core_aon", |
| 2546 | .class = &omap44xx_prcm_hwmod_class, | 2546 | .class = &omap44xx_prcm_hwmod_class, |
| 2547 | .clkdm_name = "cm_clkdm", | ||
| 2548 | }; | 2547 | }; |
| 2549 | 2548 | ||
| 2550 | /* cm_core */ | 2549 | /* cm_core */ |
| 2551 | static struct omap_hwmod omap44xx_cm_core_hwmod = { | 2550 | static struct omap_hwmod omap44xx_cm_core_hwmod = { |
| 2552 | .name = "cm_core", | 2551 | .name = "cm_core", |
| 2553 | .class = &omap44xx_prcm_hwmod_class, | 2552 | .class = &omap44xx_prcm_hwmod_class, |
| 2554 | .clkdm_name = "cm_clkdm", | ||
| 2555 | }; | 2553 | }; |
| 2556 | 2554 | ||
| 2557 | /* prm */ | 2555 | /* prm */ |
| @@ -2568,7 +2566,6 @@ static struct omap_hwmod_rst_info omap44xx_prm_resets[] = { | |||
| 2568 | static struct omap_hwmod omap44xx_prm_hwmod = { | 2566 | static struct omap_hwmod omap44xx_prm_hwmod = { |
| 2569 | .name = "prm", | 2567 | .name = "prm", |
| 2570 | .class = &omap44xx_prcm_hwmod_class, | 2568 | .class = &omap44xx_prcm_hwmod_class, |
| 2571 | .clkdm_name = "prm_clkdm", | ||
| 2572 | .mpu_irqs = omap44xx_prm_irqs, | 2569 | .mpu_irqs = omap44xx_prm_irqs, |
| 2573 | .rst_lines = omap44xx_prm_resets, | 2570 | .rst_lines = omap44xx_prm_resets, |
| 2574 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets), | 2571 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets), |
| @@ -6148,6 +6145,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { | |||
| 6148 | 6145 | ||
| 6149 | int __init omap44xx_hwmod_init(void) | 6146 | int __init omap44xx_hwmod_init(void) |
| 6150 | { | 6147 | { |
| 6148 | omap_hwmod_init(); | ||
| 6151 | return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs); | 6149 | return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs); |
| 6152 | } | 6150 | } |
| 6153 | 6151 | ||
diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c index de6d46451746..d8f6dbf45d16 100644 --- a/arch/arm/mach-omap2/opp.c +++ b/arch/arm/mach-omap2/opp.c | |||
| @@ -53,7 +53,7 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def, | |||
| 53 | omap_table_init = 1; | 53 | omap_table_init = 1; |
| 54 | 54 | ||
| 55 | /* Lets now register with OPP library */ | 55 | /* Lets now register with OPP library */ |
| 56 | for (i = 0; i < opp_def_size; i++) { | 56 | for (i = 0; i < opp_def_size; i++, opp_def++) { |
| 57 | struct omap_hwmod *oh; | 57 | struct omap_hwmod *oh; |
| 58 | struct device *dev; | 58 | struct device *dev; |
| 59 | 59 | ||
| @@ -86,7 +86,6 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def, | |||
| 86 | __func__, opp_def->freq, | 86 | __func__, opp_def->freq, |
| 87 | opp_def->hwmod_name, i, r); | 87 | opp_def->hwmod_name, i, r); |
| 88 | } | 88 | } |
| 89 | opp_def++; | ||
| 90 | } | 89 | } |
| 91 | 90 | ||
| 92 | return 0; | 91 | return 0; |
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 78564895e914..ab04d3bba2e7 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h | |||
| @@ -15,12 +15,25 @@ | |||
| 15 | 15 | ||
| 16 | #include "powerdomain.h" | 16 | #include "powerdomain.h" |
| 17 | 17 | ||
| 18 | #ifdef CONFIG_CPU_IDLE | ||
| 19 | extern int __init omap3_idle_init(void); | ||
| 20 | extern int __init omap4_idle_init(void); | ||
| 21 | #else | ||
| 22 | static inline int omap3_idle_init(void) | ||
| 23 | { | ||
| 24 | return 0; | ||
| 25 | } | ||
| 26 | |||
| 27 | static inline int omap4_idle_init(void) | ||
| 28 | { | ||
| 29 | return 0; | ||
| 30 | } | ||
| 31 | #endif | ||
| 32 | |||
| 18 | extern void *omap3_secure_ram_storage; | 33 | extern void *omap3_secure_ram_storage; |
| 19 | extern void omap3_pm_off_mode_enable(int); | 34 | extern void omap3_pm_off_mode_enable(int); |
| 20 | extern void omap_sram_idle(void); | 35 | extern void omap_sram_idle(void); |
| 21 | extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state); | 36 | extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state); |
| 22 | extern int omap3_idle_init(void); | ||
| 23 | extern int omap4_idle_init(void); | ||
| 24 | extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused); | 37 | extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused); |
| 25 | extern int (*omap_pm_suspend)(void); | 38 | extern int (*omap_pm_suspend)(void); |
| 26 | 39 | ||
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 3a595e899724..9b463c987508 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c | |||
| @@ -581,10 +581,13 @@ static void __init prcm_setup_regs(void) | |||
| 581 | OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); | 581 | OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); |
| 582 | 582 | ||
| 583 | /* Don't attach IVA interrupts */ | 583 | /* Don't attach IVA interrupts */ |
| 584 | omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); | 584 | if (omap3_has_iva()) { |
| 585 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); | 585 | omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); |
| 586 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); | 586 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); |
| 587 | omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); | 587 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); |
| 588 | omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, | ||
| 589 | OMAP3430_PM_IVAGRPSEL); | ||
| 590 | } | ||
| 588 | 591 | ||
| 589 | /* Clear any pending 'reset' flags */ | 592 | /* Clear any pending 'reset' flags */ |
| 590 | omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); | 593 | omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); |
| @@ -598,7 +601,9 @@ static void __init prcm_setup_regs(void) | |||
| 598 | /* Clear any pending PRCM interrupts */ | 601 | /* Clear any pending PRCM interrupts */ |
| 599 | omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); | 602 | omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
| 600 | 603 | ||
| 601 | omap3_iva_idle(); | 604 | if (omap3_has_iva()) |
| 605 | omap3_iva_idle(); | ||
| 606 | |||
| 602 | omap3_d2d_idle(); | 607 | omap3_d2d_idle(); |
| 603 | } | 608 | } |
| 604 | 609 | ||
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h index 8f88d65c46ea..a8a95184243d 100644 --- a/arch/arm/mach-omap2/powerdomain.h +++ b/arch/arm/mach-omap2/powerdomain.h | |||
| @@ -67,9 +67,9 @@ | |||
| 67 | 67 | ||
| 68 | /* | 68 | /* |
| 69 | * Maximum number of clockdomains that can be associated with a powerdomain. | 69 | * Maximum number of clockdomains that can be associated with a powerdomain. |
| 70 | * CORE powerdomain on OMAP4 is the worst case | 70 | * PER powerdomain on AM33XX is the worst case |
| 71 | */ | 71 | */ |
| 72 | #define PWRDM_MAX_CLKDMS 9 | 72 | #define PWRDM_MAX_CLKDMS 11 |
| 73 | 73 | ||
| 74 | /* XXX A completely arbitrary number. What is reasonable here? */ | 74 | /* XXX A completely arbitrary number. What is reasonable here? */ |
| 75 | #define PWRDM_TRANSITION_BAILOUT 100000 | 75 | #define PWRDM_TRANSITION_BAILOUT 100000 |
| @@ -92,6 +92,15 @@ struct powerdomain; | |||
| 92 | * @pwrdm_clkdms: Clockdomains in this powerdomain | 92 | * @pwrdm_clkdms: Clockdomains in this powerdomain |
| 93 | * @node: list_head linking all powerdomains | 93 | * @node: list_head linking all powerdomains |
| 94 | * @voltdm_node: list_head linking all powerdomains in a voltagedomain | 94 | * @voltdm_node: list_head linking all powerdomains in a voltagedomain |
| 95 | * @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs | ||
| 96 | * @pwrstst_offs: (AM33XX only) XXX_PWRSTST reg offset from prcm_offs | ||
| 97 | * @logicretstate_mask: (AM33XX only) mask for logic retention bitfield | ||
| 98 | * in @pwrstctrl_offs | ||
| 99 | * @mem_on_mask: (AM33XX only) mask for mem on bitfield in @pwrstctrl_offs | ||
| 100 | * @mem_ret_mask: (AM33XX only) mask for mem ret bitfield in @pwrstctrl_offs | ||
| 101 | * @mem_pwrst_mask: (AM33XX only) mask for mem state bitfield in @pwrstst_offs | ||
| 102 | * @mem_retst_mask: (AM33XX only) mask for mem retention state bitfield | ||
| 103 | * in @pwrstctrl_offs | ||
| 95 | * @state: | 104 | * @state: |
| 96 | * @state_counter: | 105 | * @state_counter: |
| 97 | * @timer: | 106 | * @timer: |
| @@ -121,6 +130,14 @@ struct powerdomain { | |||
| 121 | unsigned ret_logic_off_counter; | 130 | unsigned ret_logic_off_counter; |
| 122 | unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS]; | 131 | unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS]; |
| 123 | 132 | ||
| 133 | const u8 pwrstctrl_offs; | ||
| 134 | const u8 pwrstst_offs; | ||
| 135 | const u32 logicretstate_mask; | ||
| 136 | const u32 mem_on_mask[PWRDM_MAX_MEM_BANKS]; | ||
| 137 | const u32 mem_ret_mask[PWRDM_MAX_MEM_BANKS]; | ||
| 138 | const u32 mem_pwrst_mask[PWRDM_MAX_MEM_BANKS]; | ||
| 139 | const u32 mem_retst_mask[PWRDM_MAX_MEM_BANKS]; | ||
| 140 | |||
| 124 | #ifdef CONFIG_PM_DEBUG | 141 | #ifdef CONFIG_PM_DEBUG |
| 125 | s64 timer; | 142 | s64 timer; |
| 126 | s64 state_timer[PWRDM_MAX_PWRSTS]; | 143 | s64 state_timer[PWRDM_MAX_PWRSTS]; |
| @@ -222,10 +239,12 @@ bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm); | |||
| 222 | extern void omap242x_powerdomains_init(void); | 239 | extern void omap242x_powerdomains_init(void); |
| 223 | extern void omap243x_powerdomains_init(void); | 240 | extern void omap243x_powerdomains_init(void); |
| 224 | extern void omap3xxx_powerdomains_init(void); | 241 | extern void omap3xxx_powerdomains_init(void); |
| 242 | extern void am33xx_powerdomains_init(void); | ||
| 225 | extern void omap44xx_powerdomains_init(void); | 243 | extern void omap44xx_powerdomains_init(void); |
| 226 | 244 | ||
| 227 | extern struct pwrdm_ops omap2_pwrdm_operations; | 245 | extern struct pwrdm_ops omap2_pwrdm_operations; |
| 228 | extern struct pwrdm_ops omap3_pwrdm_operations; | 246 | extern struct pwrdm_ops omap3_pwrdm_operations; |
| 247 | extern struct pwrdm_ops am33xx_pwrdm_operations; | ||
| 229 | extern struct pwrdm_ops omap4_pwrdm_operations; | 248 | extern struct pwrdm_ops omap4_pwrdm_operations; |
| 230 | 249 | ||
| 231 | /* Common Internal functions used across OMAP rev's */ | 250 | /* Common Internal functions used across OMAP rev's */ |
diff --git a/arch/arm/mach-omap2/powerdomain33xx.c b/arch/arm/mach-omap2/powerdomain33xx.c new file mode 100644 index 000000000000..67c5663899b6 --- /dev/null +++ b/arch/arm/mach-omap2/powerdomain33xx.c | |||
| @@ -0,0 +1,229 @@ | |||
| 1 | /* | ||
| 2 | * AM33XX Powerdomain control | ||
| 3 | * | ||
| 4 | * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 5 | * | ||
| 6 | * Derived from mach-omap2/powerdomain44xx.c written by Rajendra Nayak | ||
| 7 | * <rnayak@ti.com> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or | ||
| 10 | * modify it under the terms of the GNU General Public License as | ||
| 11 | * published by the Free Software Foundation version 2. | ||
| 12 | * | ||
| 13 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
| 14 | * kind, whether express or implied; without even the implied warranty | ||
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/io.h> | ||
| 20 | #include <linux/errno.h> | ||
| 21 | #include <linux/delay.h> | ||
| 22 | |||
| 23 | #include <plat/prcm.h> | ||
| 24 | |||
| 25 | #include "powerdomain.h" | ||
| 26 | #include "prm33xx.h" | ||
| 27 | #include "prm-regbits-33xx.h" | ||
| 28 | |||
| 29 | |||
| 30 | static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) | ||
| 31 | { | ||
| 32 | am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK, | ||
| 33 | (pwrst << OMAP_POWERSTATE_SHIFT), | ||
| 34 | pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); | ||
| 35 | return 0; | ||
| 36 | } | ||
| 37 | |||
| 38 | static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) | ||
| 39 | { | ||
| 40 | u32 v; | ||
| 41 | |||
| 42 | v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); | ||
| 43 | v &= OMAP_POWERSTATE_MASK; | ||
| 44 | v >>= OMAP_POWERSTATE_SHIFT; | ||
| 45 | |||
| 46 | return v; | ||
| 47 | } | ||
| 48 | |||
| 49 | static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm) | ||
| 50 | { | ||
| 51 | u32 v; | ||
| 52 | |||
| 53 | v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); | ||
| 54 | v &= OMAP_POWERSTATEST_MASK; | ||
| 55 | v >>= OMAP_POWERSTATEST_SHIFT; | ||
| 56 | |||
| 57 | return v; | ||
| 58 | } | ||
| 59 | |||
| 60 | static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) | ||
| 61 | { | ||
| 62 | u32 v; | ||
| 63 | |||
| 64 | v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); | ||
| 65 | v &= AM33XX_LASTPOWERSTATEENTERED_MASK; | ||
| 66 | v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT; | ||
| 67 | |||
| 68 | return v; | ||
| 69 | } | ||
| 70 | |||
| 71 | static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) | ||
| 72 | { | ||
| 73 | am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK, | ||
| 74 | (1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT), | ||
| 75 | pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); | ||
| 76 | return 0; | ||
| 77 | } | ||
| 78 | |||
| 79 | static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) | ||
| 80 | { | ||
| 81 | am33xx_prm_rmw_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK, | ||
| 82 | AM33XX_LASTPOWERSTATEENTERED_MASK, | ||
| 83 | pwrdm->prcm_offs, pwrdm->pwrstst_offs); | ||
| 84 | return 0; | ||
| 85 | } | ||
| 86 | |||
| 87 | static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) | ||
| 88 | { | ||
| 89 | u32 m; | ||
| 90 | |||
| 91 | m = pwrdm->logicretstate_mask; | ||
| 92 | if (!m) | ||
| 93 | return -EINVAL; | ||
| 94 | |||
| 95 | am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), | ||
| 96 | pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); | ||
| 97 | |||
| 98 | return 0; | ||
| 99 | } | ||
| 100 | |||
| 101 | static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) | ||
| 102 | { | ||
| 103 | u32 v; | ||
| 104 | |||
| 105 | v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); | ||
| 106 | v &= AM33XX_LOGICSTATEST_MASK; | ||
| 107 | v >>= AM33XX_LOGICSTATEST_SHIFT; | ||
| 108 | |||
| 109 | return v; | ||
| 110 | } | ||
| 111 | |||
| 112 | static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm) | ||
| 113 | { | ||
| 114 | u32 v, m; | ||
| 115 | |||
| 116 | m = pwrdm->logicretstate_mask; | ||
| 117 | if (!m) | ||
| 118 | return -EINVAL; | ||
| 119 | |||
| 120 | v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); | ||
| 121 | v &= m; | ||
| 122 | v >>= __ffs(m); | ||
| 123 | |||
| 124 | return v; | ||
| 125 | } | ||
| 126 | |||
| 127 | static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, | ||
| 128 | u8 pwrst) | ||
| 129 | { | ||
| 130 | u32 m; | ||
| 131 | |||
| 132 | m = pwrdm->mem_on_mask[bank]; | ||
| 133 | if (!m) | ||
| 134 | return -EINVAL; | ||
| 135 | |||
| 136 | am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), | ||
| 137 | pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); | ||
| 138 | |||
| 139 | return 0; | ||
| 140 | } | ||
| 141 | |||
| 142 | static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, | ||
| 143 | u8 pwrst) | ||
| 144 | { | ||
| 145 | u32 m; | ||
| 146 | |||
| 147 | m = pwrdm->mem_ret_mask[bank]; | ||
| 148 | if (!m) | ||
| 149 | return -EINVAL; | ||
| 150 | |||
| 151 | am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), | ||
| 152 | pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); | ||
| 153 | |||
| 154 | return 0; | ||
| 155 | } | ||
| 156 | |||
| 157 | static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) | ||
| 158 | { | ||
| 159 | u32 m, v; | ||
| 160 | |||
| 161 | m = pwrdm->mem_pwrst_mask[bank]; | ||
| 162 | if (!m) | ||
| 163 | return -EINVAL; | ||
| 164 | |||
| 165 | v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); | ||
| 166 | v &= m; | ||
| 167 | v >>= __ffs(m); | ||
| 168 | |||
| 169 | return v; | ||
| 170 | } | ||
| 171 | |||
| 172 | static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) | ||
| 173 | { | ||
| 174 | u32 m, v; | ||
| 175 | |||
| 176 | m = pwrdm->mem_retst_mask[bank]; | ||
| 177 | if (!m) | ||
| 178 | return -EINVAL; | ||
| 179 | |||
| 180 | v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); | ||
| 181 | v &= m; | ||
| 182 | v >>= __ffs(m); | ||
| 183 | |||
| 184 | return v; | ||
| 185 | } | ||
| 186 | |||
| 187 | static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm) | ||
| 188 | { | ||
| 189 | u32 c = 0; | ||
| 190 | |||
| 191 | /* | ||
| 192 | * REVISIT: pwrdm_wait_transition() may be better implemented | ||
| 193 | * via a callback and a periodic timer check -- how long do we expect | ||
| 194 | * powerdomain transitions to take? | ||
| 195 | */ | ||
| 196 | |||
| 197 | /* XXX Is this udelay() value meaningful? */ | ||
| 198 | while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs) | ||
| 199 | & OMAP_INTRANSITION_MASK) && | ||
| 200 | (c++ < PWRDM_TRANSITION_BAILOUT)) | ||
| 201 | udelay(1); | ||
| 202 | |||
| 203 | if (c > PWRDM_TRANSITION_BAILOUT) { | ||
| 204 | pr_err("powerdomain: %s: waited too long to complete transition\n", | ||
| 205 | pwrdm->name); | ||
| 206 | return -EAGAIN; | ||
| 207 | } | ||
| 208 | |||
| 209 | pr_debug("powerdomain: completed transition in %d loops\n", c); | ||
| 210 | |||
| 211 | return 0; | ||
| 212 | } | ||
| 213 | |||
| 214 | struct pwrdm_ops am33xx_pwrdm_operations = { | ||
| 215 | .pwrdm_set_next_pwrst = am33xx_pwrdm_set_next_pwrst, | ||
| 216 | .pwrdm_read_next_pwrst = am33xx_pwrdm_read_next_pwrst, | ||
| 217 | .pwrdm_read_pwrst = am33xx_pwrdm_read_pwrst, | ||
| 218 | .pwrdm_read_prev_pwrst = am33xx_pwrdm_read_prev_pwrst, | ||
| 219 | .pwrdm_set_logic_retst = am33xx_pwrdm_set_logic_retst, | ||
| 220 | .pwrdm_read_logic_pwrst = am33xx_pwrdm_read_logic_pwrst, | ||
| 221 | .pwrdm_read_logic_retst = am33xx_pwrdm_read_logic_retst, | ||
| 222 | .pwrdm_clear_all_prev_pwrst = am33xx_pwrdm_clear_all_prev_pwrst, | ||
| 223 | .pwrdm_set_lowpwrstchange = am33xx_pwrdm_set_lowpwrstchange, | ||
| 224 | .pwrdm_read_mem_pwrst = am33xx_pwrdm_read_mem_pwrst, | ||
| 225 | .pwrdm_read_mem_retst = am33xx_pwrdm_read_mem_retst, | ||
| 226 | .pwrdm_set_mem_onst = am33xx_pwrdm_set_mem_onst, | ||
| 227 | .pwrdm_set_mem_retst = am33xx_pwrdm_set_mem_retst, | ||
| 228 | .pwrdm_wait_transition = am33xx_pwrdm_wait_transition, | ||
| 229 | }; | ||
diff --git a/arch/arm/mach-omap2/powerdomains33xx_data.c b/arch/arm/mach-omap2/powerdomains33xx_data.c new file mode 100644 index 000000000000..869adb82569e --- /dev/null +++ b/arch/arm/mach-omap2/powerdomains33xx_data.c | |||
| @@ -0,0 +1,185 @@ | |||
| 1 | /* | ||
| 2 | * AM33XX Power domain data | ||
| 3 | * | ||
| 4 | * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License as | ||
| 8 | * published by the Free Software Foundation version 2. | ||
| 9 | * | ||
| 10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
| 11 | * kind, whether express or implied; without even the implied warranty | ||
| 12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include <linux/kernel.h> | ||
| 17 | #include <linux/init.h> | ||
| 18 | |||
| 19 | #include "powerdomain.h" | ||
| 20 | #include "prcm-common.h" | ||
| 21 | #include "prm-regbits-33xx.h" | ||
| 22 | #include "prm33xx.h" | ||
| 23 | |||
| 24 | static struct powerdomain gfx_33xx_pwrdm = { | ||
| 25 | .name = "gfx_pwrdm", | ||
| 26 | .voltdm = { .name = "core" }, | ||
| 27 | .prcm_offs = AM33XX_PRM_GFX_MOD, | ||
| 28 | .pwrstctrl_offs = AM33XX_PM_GFX_PWRSTCTRL_OFFSET, | ||
| 29 | .pwrstst_offs = AM33XX_PM_GFX_PWRSTST_OFFSET, | ||
| 30 | .pwrsts = PWRSTS_OFF_RET_ON, | ||
| 31 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | ||
| 32 | .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, | ||
| 33 | .banks = 1, | ||
| 34 | .logicretstate_mask = AM33XX_LOGICRETSTATE_MASK, | ||
| 35 | .mem_on_mask = { | ||
| 36 | [0] = AM33XX_GFX_MEM_ONSTATE_MASK, /* gfx_mem */ | ||
| 37 | }, | ||
| 38 | .mem_ret_mask = { | ||
| 39 | [0] = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */ | ||
| 40 | }, | ||
| 41 | .mem_pwrst_mask = { | ||
| 42 | [0] = AM33XX_GFX_MEM_STATEST_MASK, /* gfx_mem */ | ||
| 43 | }, | ||
| 44 | .mem_retst_mask = { | ||
| 45 | [0] = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */ | ||
| 46 | }, | ||
| 47 | .pwrsts_mem_ret = { | ||
| 48 | [0] = PWRSTS_OFF_RET, /* gfx_mem */ | ||
| 49 | }, | ||
| 50 | .pwrsts_mem_on = { | ||
| 51 | [0] = PWRSTS_ON, /* gfx_mem */ | ||
| 52 | }, | ||
| 53 | }; | ||
| 54 | |||
| 55 | static struct powerdomain rtc_33xx_pwrdm = { | ||
| 56 | .name = "rtc_pwrdm", | ||
| 57 | .voltdm = { .name = "rtc" }, | ||
| 58 | .prcm_offs = AM33XX_PRM_RTC_MOD, | ||
| 59 | .pwrstctrl_offs = AM33XX_PM_RTC_PWRSTCTRL_OFFSET, | ||
| 60 | .pwrstst_offs = AM33XX_PM_RTC_PWRSTST_OFFSET, | ||
| 61 | .pwrsts = PWRSTS_ON, | ||
| 62 | .logicretstate_mask = AM33XX_LOGICRETSTATE_MASK, | ||
| 63 | }; | ||
| 64 | |||
| 65 | static struct powerdomain wkup_33xx_pwrdm = { | ||
| 66 | .name = "wkup_pwrdm", | ||
| 67 | .voltdm = { .name = "core" }, | ||
| 68 | .prcm_offs = AM33XX_PRM_WKUP_MOD, | ||
| 69 | .pwrstctrl_offs = AM33XX_PM_WKUP_PWRSTCTRL_OFFSET, | ||
| 70 | .pwrstst_offs = AM33XX_PM_WKUP_PWRSTST_OFFSET, | ||
| 71 | .pwrsts = PWRSTS_ON, | ||
| 72 | .logicretstate_mask = AM33XX_LOGICRETSTATE_3_3_MASK, | ||
| 73 | }; | ||
| 74 | |||
| 75 | static struct powerdomain per_33xx_pwrdm = { | ||
| 76 | .name = "per_pwrdm", | ||
| 77 | .voltdm = { .name = "core" }, | ||
| 78 | .prcm_offs = AM33XX_PRM_PER_MOD, | ||
| 79 | .pwrstctrl_offs = AM33XX_PM_PER_PWRSTCTRL_OFFSET, | ||
| 80 | .pwrstst_offs = AM33XX_PM_PER_PWRSTST_OFFSET, | ||
| 81 | .pwrsts = PWRSTS_OFF_RET_ON, | ||
| 82 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | ||
| 83 | .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, | ||
| 84 | .banks = 3, | ||
| 85 | .logicretstate_mask = AM33XX_LOGICRETSTATE_3_3_MASK, | ||
| 86 | .mem_on_mask = { | ||
| 87 | [0] = AM33XX_PRUSS_MEM_ONSTATE_MASK, /* pruss_mem */ | ||
| 88 | [1] = AM33XX_PER_MEM_ONSTATE_MASK, /* per_mem */ | ||
| 89 | [2] = AM33XX_RAM_MEM_ONSTATE_MASK, /* ram_mem */ | ||
| 90 | }, | ||
| 91 | .mem_ret_mask = { | ||
| 92 | [0] = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */ | ||
| 93 | [1] = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */ | ||
| 94 | [2] = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */ | ||
| 95 | }, | ||
| 96 | .mem_pwrst_mask = { | ||
| 97 | [0] = AM33XX_PRUSS_MEM_STATEST_MASK, /* pruss_mem */ | ||
| 98 | [1] = AM33XX_PER_MEM_STATEST_MASK, /* per_mem */ | ||
| 99 | [2] = AM33XX_RAM_MEM_STATEST_MASK, /* ram_mem */ | ||
| 100 | }, | ||
| 101 | .mem_retst_mask = { | ||
| 102 | [0] = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */ | ||
| 103 | [1] = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */ | ||
| 104 | [2] = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */ | ||
| 105 | }, | ||
| 106 | .pwrsts_mem_ret = { | ||
| 107 | [0] = PWRSTS_OFF_RET, /* pruss_mem */ | ||
| 108 | [1] = PWRSTS_OFF_RET, /* per_mem */ | ||
| 109 | [2] = PWRSTS_OFF_RET, /* ram_mem */ | ||
| 110 | }, | ||
| 111 | .pwrsts_mem_on = { | ||
| 112 | [0] = PWRSTS_ON, /* pruss_mem */ | ||
| 113 | [1] = PWRSTS_ON, /* per_mem */ | ||
| 114 | [2] = PWRSTS_ON, /* ram_mem */ | ||
| 115 | }, | ||
| 116 | }; | ||
| 117 | |||
| 118 | static struct powerdomain mpu_33xx_pwrdm = { | ||
| 119 | .name = "mpu_pwrdm", | ||
| 120 | .voltdm = { .name = "mpu" }, | ||
| 121 | .prcm_offs = AM33XX_PRM_MPU_MOD, | ||
| 122 | .pwrstctrl_offs = AM33XX_PM_MPU_PWRSTCTRL_OFFSET, | ||
| 123 | .pwrstst_offs = AM33XX_PM_MPU_PWRSTST_OFFSET, | ||
| 124 | .pwrsts = PWRSTS_OFF_RET_ON, | ||
| 125 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | ||
| 126 | .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, | ||
| 127 | .banks = 3, | ||
| 128 | .logicretstate_mask = AM33XX_LOGICRETSTATE_MASK, | ||
| 129 | .mem_on_mask = { | ||
| 130 | [0] = AM33XX_MPU_L1_ONSTATE_MASK, /* mpu_l1 */ | ||
| 131 | [1] = AM33XX_MPU_L2_ONSTATE_MASK, /* mpu_l2 */ | ||
| 132 | [2] = AM33XX_MPU_RAM_ONSTATE_MASK, /* mpu_ram */ | ||
| 133 | }, | ||
| 134 | .mem_ret_mask = { | ||
| 135 | [0] = AM33XX_MPU_L1_RETSTATE_MASK, /* mpu_l1 */ | ||
| 136 | [1] = AM33XX_MPU_L2_RETSTATE_MASK, /* mpu_l2 */ | ||
| 137 | [2] = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */ | ||
| 138 | }, | ||
| 139 | .mem_pwrst_mask = { | ||
| 140 | [0] = AM33XX_MPU_L1_STATEST_MASK, /* mpu_l1 */ | ||
| 141 | [1] = AM33XX_MPU_L2_STATEST_MASK, /* mpu_l2 */ | ||
| 142 | [2] = AM33XX_MPU_RAM_STATEST_MASK, /* mpu_ram */ | ||
| 143 | }, | ||
| 144 | .mem_retst_mask = { | ||
| 145 | [0] = AM33XX_MPU_L1_RETSTATE_MASK, /* mpu_l1 */ | ||
| 146 | [1] = AM33XX_MPU_L2_RETSTATE_MASK, /* mpu_l2 */ | ||
| 147 | [2] = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */ | ||
| 148 | }, | ||
| 149 | .pwrsts_mem_ret = { | ||
| 150 | [0] = PWRSTS_OFF_RET, /* mpu_l1 */ | ||
| 151 | [1] = PWRSTS_OFF_RET, /* mpu_l2 */ | ||
| 152 | [2] = PWRSTS_OFF_RET, /* mpu_ram */ | ||
| 153 | }, | ||
| 154 | .pwrsts_mem_on = { | ||
| 155 | [0] = PWRSTS_ON, /* mpu_l1 */ | ||
| 156 | [1] = PWRSTS_ON, /* mpu_l2 */ | ||
| 157 | [2] = PWRSTS_ON, /* mpu_ram */ | ||
| 158 | }, | ||
| 159 | }; | ||
| 160 | |||
| 161 | static struct powerdomain cefuse_33xx_pwrdm = { | ||
| 162 | .name = "cefuse_pwrdm", | ||
| 163 | .voltdm = { .name = "core" }, | ||
| 164 | .prcm_offs = AM33XX_PRM_CEFUSE_MOD, | ||
| 165 | .pwrstctrl_offs = AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET, | ||
| 166 | .pwrstst_offs = AM33XX_PM_CEFUSE_PWRSTST_OFFSET, | ||
| 167 | .pwrsts = PWRSTS_OFF_ON, | ||
| 168 | }; | ||
| 169 | |||
| 170 | static struct powerdomain *powerdomains_am33xx[] __initdata = { | ||
| 171 | &gfx_33xx_pwrdm, | ||
| 172 | &rtc_33xx_pwrdm, | ||
| 173 | &wkup_33xx_pwrdm, | ||
| 174 | &per_33xx_pwrdm, | ||
| 175 | &mpu_33xx_pwrdm, | ||
| 176 | &cefuse_33xx_pwrdm, | ||
| 177 | NULL, | ||
| 178 | }; | ||
| 179 | |||
| 180 | void __init am33xx_powerdomains_init(void) | ||
| 181 | { | ||
| 182 | pwrdm_register_platform_funcs(&am33xx_pwrdm_operations); | ||
| 183 | pwrdm_register_pwrdms(powerdomains_am33xx); | ||
| 184 | pwrdm_complete_init(); | ||
| 185 | } | ||
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c index fb0a0a6869d1..bb883e463078 100644 --- a/arch/arm/mach-omap2/powerdomains3xxx_data.c +++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c | |||
| @@ -71,6 +71,22 @@ static struct powerdomain mpu_3xxx_pwrdm = { | |||
| 71 | .voltdm = { .name = "mpu_iva" }, | 71 | .voltdm = { .name = "mpu_iva" }, |
| 72 | }; | 72 | }; |
| 73 | 73 | ||
| 74 | static struct powerdomain mpu_am35x_pwrdm = { | ||
| 75 | .name = "mpu_pwrdm", | ||
| 76 | .prcm_offs = MPU_MOD, | ||
| 77 | .pwrsts = PWRSTS_ON, | ||
| 78 | .pwrsts_logic_ret = PWRSTS_ON, | ||
| 79 | .flags = PWRDM_HAS_MPU_QUIRK, | ||
| 80 | .banks = 1, | ||
| 81 | .pwrsts_mem_ret = { | ||
| 82 | [0] = PWRSTS_ON, | ||
| 83 | }, | ||
| 84 | .pwrsts_mem_on = { | ||
| 85 | [0] = PWRSTS_ON, | ||
| 86 | }, | ||
| 87 | .voltdm = { .name = "mpu_iva" }, | ||
| 88 | }; | ||
| 89 | |||
| 74 | /* | 90 | /* |
| 75 | * The USBTLL Save-and-Restore mechanism is broken on | 91 | * The USBTLL Save-and-Restore mechanism is broken on |
| 76 | * 3430s up to ES3.0 and 3630ES1.0. Hence this feature | 92 | * 3430s up to ES3.0 and 3630ES1.0. Hence this feature |
| @@ -120,6 +136,23 @@ static struct powerdomain core_3xxx_es3_1_pwrdm = { | |||
| 120 | .voltdm = { .name = "core" }, | 136 | .voltdm = { .name = "core" }, |
| 121 | }; | 137 | }; |
| 122 | 138 | ||
| 139 | static struct powerdomain core_am35x_pwrdm = { | ||
| 140 | .name = "core_pwrdm", | ||
| 141 | .prcm_offs = CORE_MOD, | ||
| 142 | .pwrsts = PWRSTS_ON, | ||
| 143 | .pwrsts_logic_ret = PWRSTS_ON, | ||
| 144 | .banks = 2, | ||
| 145 | .pwrsts_mem_ret = { | ||
| 146 | [0] = PWRSTS_ON, /* MEM1RETSTATE */ | ||
| 147 | [1] = PWRSTS_ON, /* MEM2RETSTATE */ | ||
| 148 | }, | ||
| 149 | .pwrsts_mem_on = { | ||
| 150 | [0] = PWRSTS_ON, /* MEM1ONSTATE */ | ||
| 151 | [1] = PWRSTS_ON, /* MEM2ONSTATE */ | ||
| 152 | }, | ||
| 153 | .voltdm = { .name = "core" }, | ||
| 154 | }; | ||
| 155 | |||
| 123 | static struct powerdomain dss_pwrdm = { | 156 | static struct powerdomain dss_pwrdm = { |
| 124 | .name = "dss_pwrdm", | 157 | .name = "dss_pwrdm", |
| 125 | .prcm_offs = OMAP3430_DSS_MOD, | 158 | .prcm_offs = OMAP3430_DSS_MOD, |
| @@ -135,6 +168,21 @@ static struct powerdomain dss_pwrdm = { | |||
| 135 | .voltdm = { .name = "core" }, | 168 | .voltdm = { .name = "core" }, |
| 136 | }; | 169 | }; |
| 137 | 170 | ||
| 171 | static struct powerdomain dss_am35x_pwrdm = { | ||
| 172 | .name = "dss_pwrdm", | ||
| 173 | .prcm_offs = OMAP3430_DSS_MOD, | ||
| 174 | .pwrsts = PWRSTS_ON, | ||
| 175 | .pwrsts_logic_ret = PWRSTS_ON, | ||
| 176 | .banks = 1, | ||
| 177 | .pwrsts_mem_ret = { | ||
| 178 | [0] = PWRSTS_ON, /* MEMRETSTATE */ | ||
| 179 | }, | ||
| 180 | .pwrsts_mem_on = { | ||
| 181 | [0] = PWRSTS_ON, /* MEMONSTATE */ | ||
| 182 | }, | ||
| 183 | .voltdm = { .name = "core" }, | ||
| 184 | }; | ||
| 185 | |||
| 138 | /* | 186 | /* |
| 139 | * Although the 34XX TRM Rev K Table 4-371 notes that retention is a | 187 | * Although the 34XX TRM Rev K Table 4-371 notes that retention is a |
| 140 | * possible SGX powerstate, the SGX device itself does not support | 188 | * possible SGX powerstate, the SGX device itself does not support |
| @@ -156,6 +204,21 @@ static struct powerdomain sgx_pwrdm = { | |||
| 156 | .voltdm = { .name = "core" }, | 204 | .voltdm = { .name = "core" }, |
| 157 | }; | 205 | }; |
| 158 | 206 | ||
| 207 | static struct powerdomain sgx_am35x_pwrdm = { | ||
| 208 | .name = "sgx_pwrdm", | ||
| 209 | .prcm_offs = OMAP3430ES2_SGX_MOD, | ||
| 210 | .pwrsts = PWRSTS_ON, | ||
| 211 | .pwrsts_logic_ret = PWRSTS_ON, | ||
| 212 | .banks = 1, | ||
| 213 | .pwrsts_mem_ret = { | ||
| 214 | [0] = PWRSTS_ON, /* MEMRETSTATE */ | ||
| 215 | }, | ||
| 216 | .pwrsts_mem_on = { | ||
| 217 | [0] = PWRSTS_ON, /* MEMONSTATE */ | ||
| 218 | }, | ||
| 219 | .voltdm = { .name = "core" }, | ||
| 220 | }; | ||
| 221 | |||
| 159 | static struct powerdomain cam_pwrdm = { | 222 | static struct powerdomain cam_pwrdm = { |
| 160 | .name = "cam_pwrdm", | 223 | .name = "cam_pwrdm", |
| 161 | .prcm_offs = OMAP3430_CAM_MOD, | 224 | .prcm_offs = OMAP3430_CAM_MOD, |
| @@ -186,6 +249,21 @@ static struct powerdomain per_pwrdm = { | |||
| 186 | .voltdm = { .name = "core" }, | 249 | .voltdm = { .name = "core" }, |
| 187 | }; | 250 | }; |
| 188 | 251 | ||
| 252 | static struct powerdomain per_am35x_pwrdm = { | ||
| 253 | .name = "per_pwrdm", | ||
| 254 | .prcm_offs = OMAP3430_PER_MOD, | ||
| 255 | .pwrsts = PWRSTS_ON, | ||
| 256 | .pwrsts_logic_ret = PWRSTS_ON, | ||
| 257 | .banks = 1, | ||
| 258 | .pwrsts_mem_ret = { | ||
| 259 | [0] = PWRSTS_ON, /* MEMRETSTATE */ | ||
| 260 | }, | ||
| 261 | .pwrsts_mem_on = { | ||
| 262 | [0] = PWRSTS_ON, /* MEMONSTATE */ | ||
| 263 | }, | ||
| 264 | .voltdm = { .name = "core" }, | ||
| 265 | }; | ||
| 266 | |||
| 189 | static struct powerdomain emu_pwrdm = { | 267 | static struct powerdomain emu_pwrdm = { |
| 190 | .name = "emu_pwrdm", | 268 | .name = "emu_pwrdm", |
| 191 | .prcm_offs = OMAP3430_EMU_MOD, | 269 | .prcm_offs = OMAP3430_EMU_MOD, |
| @@ -200,6 +278,14 @@ static struct powerdomain neon_pwrdm = { | |||
| 200 | .voltdm = { .name = "mpu_iva" }, | 278 | .voltdm = { .name = "mpu_iva" }, |
| 201 | }; | 279 | }; |
| 202 | 280 | ||
| 281 | static struct powerdomain neon_am35x_pwrdm = { | ||
| 282 | .name = "neon_pwrdm", | ||
| 283 | .prcm_offs = OMAP3430_NEON_MOD, | ||
| 284 | .pwrsts = PWRSTS_ON, | ||
| 285 | .pwrsts_logic_ret = PWRSTS_ON, | ||
| 286 | .voltdm = { .name = "mpu_iva" }, | ||
| 287 | }; | ||
| 288 | |||
| 203 | static struct powerdomain usbhost_pwrdm = { | 289 | static struct powerdomain usbhost_pwrdm = { |
| 204 | .name = "usbhost_pwrdm", | 290 | .name = "usbhost_pwrdm", |
| 205 | .prcm_offs = OMAP3430ES2_USBHOST_MOD, | 291 | .prcm_offs = OMAP3430ES2_USBHOST_MOD, |
| @@ -293,6 +379,22 @@ static struct powerdomain *powerdomains_omap3430es3_1plus[] __initdata = { | |||
| 293 | NULL | 379 | NULL |
| 294 | }; | 380 | }; |
| 295 | 381 | ||
| 382 | static struct powerdomain *powerdomains_am35x[] __initdata = { | ||
| 383 | &wkup_omap2_pwrdm, | ||
| 384 | &mpu_am35x_pwrdm, | ||
| 385 | &neon_am35x_pwrdm, | ||
| 386 | &core_am35x_pwrdm, | ||
| 387 | &sgx_am35x_pwrdm, | ||
| 388 | &dss_am35x_pwrdm, | ||
| 389 | &per_am35x_pwrdm, | ||
| 390 | &emu_pwrdm, | ||
| 391 | &dpll1_pwrdm, | ||
| 392 | &dpll3_pwrdm, | ||
| 393 | &dpll4_pwrdm, | ||
| 394 | &dpll5_pwrdm, | ||
| 395 | NULL | ||
| 396 | }; | ||
| 397 | |||
| 296 | void __init omap3xxx_powerdomains_init(void) | 398 | void __init omap3xxx_powerdomains_init(void) |
| 297 | { | 399 | { |
| 298 | unsigned int rev; | 400 | unsigned int rev; |
| @@ -301,21 +403,34 @@ void __init omap3xxx_powerdomains_init(void) | |||
| 301 | return; | 403 | return; |
| 302 | 404 | ||
| 303 | pwrdm_register_platform_funcs(&omap3_pwrdm_operations); | 405 | pwrdm_register_platform_funcs(&omap3_pwrdm_operations); |
| 304 | pwrdm_register_pwrdms(powerdomains_omap3430_common); | ||
| 305 | 406 | ||
| 306 | rev = omap_rev(); | 407 | rev = omap_rev(); |
| 307 | 408 | ||
| 308 | if (rev == OMAP3430_REV_ES1_0) | 409 | if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) { |
| 309 | pwrdm_register_pwrdms(powerdomains_omap3430es1); | 410 | pwrdm_register_pwrdms(powerdomains_am35x); |
| 310 | else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || | 411 | } else { |
| 311 | rev == OMAP3430_REV_ES3_0 || rev == OMAP3630_REV_ES1_0) | 412 | pwrdm_register_pwrdms(powerdomains_omap3430_common); |
| 312 | pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0); | 413 | |
| 313 | else if (rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2 || | 414 | switch (rev) { |
| 314 | rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1 || | 415 | case OMAP3430_REV_ES1_0: |
| 315 | rev == OMAP3630_REV_ES1_1 || rev == OMAP3630_REV_ES1_2) | 416 | pwrdm_register_pwrdms(powerdomains_omap3430es1); |
| 316 | pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus); | 417 | break; |
| 317 | else | 418 | case OMAP3430_REV_ES2_0: |
| 318 | WARN(1, "OMAP3 powerdomain init: unknown chip type\n"); | 419 | case OMAP3430_REV_ES2_1: |
| 420 | case OMAP3430_REV_ES3_0: | ||
| 421 | case OMAP3630_REV_ES1_0: | ||
| 422 | pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0); | ||
| 423 | break; | ||
| 424 | case OMAP3430_REV_ES3_1: | ||
| 425 | case OMAP3430_REV_ES3_1_2: | ||
| 426 | case OMAP3630_REV_ES1_1: | ||
| 427 | case OMAP3630_REV_ES1_2: | ||
| 428 | pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus); | ||
| 429 | break; | ||
| 430 | default: | ||
| 431 | WARN(1, "OMAP3 powerdomain init: unknown chip type\n"); | ||
| 432 | } | ||
| 433 | } | ||
| 319 | 434 | ||
| 320 | pwrdm_complete_init(); | 435 | pwrdm_complete_init(); |
| 321 | } | 436 | } |
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index 6da3ba483ad1..cc1398e8b469 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h | |||
| @@ -203,8 +203,8 @@ | |||
| 203 | #define OMAP3430_EN_MMC2_SHIFT 25 | 203 | #define OMAP3430_EN_MMC2_SHIFT 25 |
| 204 | #define OMAP3430_EN_MMC1_MASK (1 << 24) | 204 | #define OMAP3430_EN_MMC1_MASK (1 << 24) |
| 205 | #define OMAP3430_EN_MMC1_SHIFT 24 | 205 | #define OMAP3430_EN_MMC1_SHIFT 24 |
| 206 | #define OMAP3430_EN_UART4_MASK (1 << 23) | 206 | #define AM35XX_EN_UART4_MASK (1 << 23) |
| 207 | #define OMAP3430_EN_UART4_SHIFT 23 | 207 | #define AM35XX_EN_UART4_SHIFT 23 |
| 208 | #define OMAP3430_EN_MCSPI4_MASK (1 << 21) | 208 | #define OMAP3430_EN_MCSPI4_MASK (1 << 21) |
| 209 | #define OMAP3430_EN_MCSPI4_SHIFT 21 | 209 | #define OMAP3430_EN_MCSPI4_SHIFT 21 |
| 210 | #define OMAP3430_EN_MCSPI3_MASK (1 << 20) | 210 | #define OMAP3430_EN_MCSPI3_MASK (1 << 20) |
diff --git a/arch/arm/mach-omap2/prm-regbits-33xx.h b/arch/arm/mach-omap2/prm-regbits-33xx.h new file mode 100644 index 000000000000..0221b5c20e87 --- /dev/null +++ b/arch/arm/mach-omap2/prm-regbits-33xx.h | |||
| @@ -0,0 +1,357 @@ | |||
| 1 | /* | ||
| 2 | * AM33XX PRM_XXX register bits | ||
| 3 | * | ||
| 4 | * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License as | ||
| 8 | * published by the Free Software Foundation version 2. | ||
| 9 | * | ||
| 10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
| 11 | * kind, whether express or implied; without even the implied warranty | ||
| 12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H | ||
| 17 | #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H | ||
| 18 | |||
| 19 | #include "prm.h" | ||
| 20 | |||
| 21 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
| 22 | #define AM33XX_ABBOFF_ACT_EXPORT_SHIFT 1 | ||
| 23 | #define AM33XX_ABBOFF_ACT_EXPORT_MASK (1 << 1) | ||
| 24 | |||
| 25 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
| 26 | #define AM33XX_ABBOFF_SLEEP_EXPORT_SHIFT 2 | ||
| 27 | #define AM33XX_ABBOFF_SLEEP_EXPORT_MASK (1 << 2) | ||
| 28 | |||
| 29 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
| 30 | #define AM33XX_AIPOFF_SHIFT 8 | ||
| 31 | #define AM33XX_AIPOFF_MASK (1 << 8) | ||
| 32 | |||
| 33 | /* Used by PM_WKUP_PWRSTST */ | ||
| 34 | #define AM33XX_DEBUGSS_MEM_STATEST_SHIFT 17 | ||
| 35 | #define AM33XX_DEBUGSS_MEM_STATEST_MASK (0x3 << 17) | ||
| 36 | |||
| 37 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
| 38 | #define AM33XX_DISABLE_RTA_EXPORT_SHIFT 0 | ||
| 39 | #define AM33XX_DISABLE_RTA_EXPORT_MASK (1 << 0) | ||
| 40 | |||
| 41 | /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ | ||
| 42 | #define AM33XX_DPLL_CORE_RECAL_EN_SHIFT 12 | ||
| 43 | #define AM33XX_DPLL_CORE_RECAL_EN_MASK (1 << 12) | ||
| 44 | |||
| 45 | /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ | ||
| 46 | #define AM33XX_DPLL_CORE_RECAL_ST_SHIFT 12 | ||
| 47 | #define AM33XX_DPLL_CORE_RECAL_ST_MASK (1 << 12) | ||
| 48 | |||
| 49 | /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ | ||
| 50 | #define AM33XX_DPLL_DDR_RECAL_EN_SHIFT 14 | ||
| 51 | #define AM33XX_DPLL_DDR_RECAL_EN_MASK (1 << 14) | ||
| 52 | |||
| 53 | /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ | ||
| 54 | #define AM33XX_DPLL_DDR_RECAL_ST_SHIFT 14 | ||
| 55 | #define AM33XX_DPLL_DDR_RECAL_ST_MASK (1 << 14) | ||
| 56 | |||
| 57 | /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ | ||
| 58 | #define AM33XX_DPLL_DISP_RECAL_EN_SHIFT 15 | ||
| 59 | #define AM33XX_DPLL_DISP_RECAL_EN_MASK (1 << 15) | ||
| 60 | |||
| 61 | /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ | ||
| 62 | #define AM33XX_DPLL_DISP_RECAL_ST_SHIFT 13 | ||
| 63 | #define AM33XX_DPLL_DISP_RECAL_ST_MASK (1 << 13) | ||
| 64 | |||
| 65 | /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ | ||
| 66 | #define AM33XX_DPLL_MPU_RECAL_EN_SHIFT 11 | ||
| 67 | #define AM33XX_DPLL_MPU_RECAL_EN_MASK (1 << 11) | ||
| 68 | |||
| 69 | /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ | ||
| 70 | #define AM33XX_DPLL_MPU_RECAL_ST_SHIFT 11 | ||
| 71 | #define AM33XX_DPLL_MPU_RECAL_ST_MASK (1 << 11) | ||
| 72 | |||
| 73 | /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ | ||
| 74 | #define AM33XX_DPLL_PER_RECAL_EN_SHIFT 13 | ||
| 75 | #define AM33XX_DPLL_PER_RECAL_EN_MASK (1 << 13) | ||
| 76 | |||
| 77 | /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ | ||
| 78 | #define AM33XX_DPLL_PER_RECAL_ST_SHIFT 15 | ||
| 79 | #define AM33XX_DPLL_PER_RECAL_ST_MASK (1 << 15) | ||
| 80 | |||
| 81 | /* Used by RM_WKUP_RSTST */ | ||
| 82 | #define AM33XX_EMULATION_M3_RST_SHIFT 6 | ||
| 83 | #define AM33XX_EMULATION_M3_RST_MASK (1 << 6) | ||
| 84 | |||
| 85 | /* Used by RM_MPU_RSTST */ | ||
| 86 | #define AM33XX_EMULATION_MPU_RST_SHIFT 5 | ||
| 87 | #define AM33XX_EMULATION_MPU_RST_MASK (1 << 5) | ||
| 88 | |||
| 89 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
| 90 | #define AM33XX_ENFUNC1_EXPORT_SHIFT 3 | ||
| 91 | #define AM33XX_ENFUNC1_EXPORT_MASK (1 << 3) | ||
| 92 | |||
| 93 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
| 94 | #define AM33XX_ENFUNC3_EXPORT_SHIFT 5 | ||
| 95 | #define AM33XX_ENFUNC3_EXPORT_MASK (1 << 5) | ||
| 96 | |||
| 97 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
| 98 | #define AM33XX_ENFUNC4_SHIFT 6 | ||
| 99 | #define AM33XX_ENFUNC4_MASK (1 << 6) | ||
| 100 | |||
| 101 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
| 102 | #define AM33XX_ENFUNC5_SHIFT 7 | ||
| 103 | #define AM33XX_ENFUNC5_MASK (1 << 7) | ||
| 104 | |||
| 105 | /* Used by PRM_RSTST */ | ||
| 106 | #define AM33XX_EXTERNAL_WARM_RST_SHIFT 5 | ||
| 107 | #define AM33XX_EXTERNAL_WARM_RST_MASK (1 << 5) | ||
| 108 | |||
| 109 | /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ | ||
| 110 | #define AM33XX_FORCEWKUP_EN_SHIFT 10 | ||
| 111 | #define AM33XX_FORCEWKUP_EN_MASK (1 << 10) | ||
| 112 | |||
| 113 | /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ | ||
| 114 | #define AM33XX_FORCEWKUP_ST_SHIFT 10 | ||
| 115 | #define AM33XX_FORCEWKUP_ST_MASK (1 << 10) | ||
| 116 | |||
| 117 | /* Used by PM_GFX_PWRSTCTRL */ | ||
| 118 | #define AM33XX_GFX_MEM_ONSTATE_SHIFT 17 | ||
| 119 | #define AM33XX_GFX_MEM_ONSTATE_MASK (0x3 << 17) | ||
| 120 | |||
| 121 | /* Used by PM_GFX_PWRSTCTRL */ | ||
| 122 | #define AM33XX_GFX_MEM_RETSTATE_SHIFT 6 | ||
| 123 | #define AM33XX_GFX_MEM_RETSTATE_MASK (1 << 6) | ||
| 124 | |||
| 125 | /* Used by PM_GFX_PWRSTST */ | ||
| 126 | #define AM33XX_GFX_MEM_STATEST_SHIFT 4 | ||
| 127 | #define AM33XX_GFX_MEM_STATEST_MASK (0x3 << 4) | ||
| 128 | |||
| 129 | /* Used by RM_GFX_RSTCTRL, RM_GFX_RSTST */ | ||
| 130 | #define AM33XX_GFX_RST_SHIFT 0 | ||
| 131 | #define AM33XX_GFX_RST_MASK (1 << 0) | ||
| 132 | |||
| 133 | /* Used by PRM_RSTST */ | ||
| 134 | #define AM33XX_GLOBAL_COLD_RST_SHIFT 0 | ||
| 135 | #define AM33XX_GLOBAL_COLD_RST_MASK (1 << 0) | ||
| 136 | |||
| 137 | /* Used by PRM_RSTST */ | ||
| 138 | #define AM33XX_GLOBAL_WARM_SW_RST_SHIFT 1 | ||
| 139 | #define AM33XX_GLOBAL_WARM_SW_RST_MASK (1 << 1) | ||
| 140 | |||
| 141 | /* Used by RM_WKUP_RSTST */ | ||
| 142 | #define AM33XX_ICECRUSHER_M3_RST_SHIFT 7 | ||
| 143 | #define AM33XX_ICECRUSHER_M3_RST_MASK (1 << 7) | ||
| 144 | |||
| 145 | /* Used by RM_MPU_RSTST */ | ||
| 146 | #define AM33XX_ICECRUSHER_MPU_RST_SHIFT 6 | ||
| 147 | #define AM33XX_ICECRUSHER_MPU_RST_MASK (1 << 6) | ||
| 148 | |||
| 149 | /* Used by PRM_RSTST */ | ||
| 150 | #define AM33XX_ICEPICK_RST_SHIFT 9 | ||
| 151 | #define AM33XX_ICEPICK_RST_MASK (1 << 9) | ||
| 152 | |||
| 153 | /* Used by RM_PER_RSTCTRL */ | ||
| 154 | #define AM33XX_PRUSS_LRST_SHIFT 1 | ||
| 155 | #define AM33XX_PRUSS_LRST_MASK (1 << 1) | ||
| 156 | |||
| 157 | /* Used by PM_PER_PWRSTCTRL */ | ||
| 158 | #define AM33XX_PRUSS_MEM_ONSTATE_SHIFT 5 | ||
| 159 | #define AM33XX_PRUSS_MEM_ONSTATE_MASK (0x3 << 5) | ||
| 160 | |||
| 161 | /* Used by PM_PER_PWRSTCTRL */ | ||
| 162 | #define AM33XX_PRUSS_MEM_RETSTATE_SHIFT 7 | ||
| 163 | #define AM33XX_PRUSS_MEM_RETSTATE_MASK (1 << 7) | ||
| 164 | |||
| 165 | /* Used by PM_PER_PWRSTST */ | ||
| 166 | #define AM33XX_PRUSS_MEM_STATEST_SHIFT 23 | ||
| 167 | #define AM33XX_PRUSS_MEM_STATEST_MASK (0x3 << 23) | ||
| 168 | |||
| 169 | /* | ||
| 170 | * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST, | ||
| 171 | * PM_WKUP_PWRSTST, PM_RTC_PWRSTST | ||
| 172 | */ | ||
| 173 | #define AM33XX_INTRANSITION_SHIFT 20 | ||
| 174 | #define AM33XX_INTRANSITION_MASK (1 << 20) | ||
| 175 | |||
| 176 | /* Used by PM_CEFUSE_PWRSTST */ | ||
| 177 | #define AM33XX_LASTPOWERSTATEENTERED_SHIFT 24 | ||
| 178 | #define AM33XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24) | ||
| 179 | |||
| 180 | /* Used by PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_RTC_PWRSTCTRL */ | ||
| 181 | #define AM33XX_LOGICRETSTATE_SHIFT 2 | ||
| 182 | #define AM33XX_LOGICRETSTATE_MASK (1 << 2) | ||
| 183 | |||
| 184 | /* Renamed from LOGICRETSTATE Used by PM_PER_PWRSTCTRL, PM_WKUP_PWRSTCTRL */ | ||
| 185 | #define AM33XX_LOGICRETSTATE_3_3_SHIFT 3 | ||
| 186 | #define AM33XX_LOGICRETSTATE_3_3_MASK (1 << 3) | ||
| 187 | |||
| 188 | /* | ||
| 189 | * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST, | ||
| 190 | * PM_WKUP_PWRSTST, PM_RTC_PWRSTST | ||
| 191 | */ | ||
| 192 | #define AM33XX_LOGICSTATEST_SHIFT 2 | ||
| 193 | #define AM33XX_LOGICSTATEST_MASK (1 << 2) | ||
| 194 | |||
| 195 | /* | ||
| 196 | * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL, | ||
| 197 | * PM_MPU_PWRSTCTRL, PM_WKUP_PWRSTCTRL, PM_RTC_PWRSTCTRL | ||
| 198 | */ | ||
| 199 | #define AM33XX_LOWPOWERSTATECHANGE_SHIFT 4 | ||
| 200 | #define AM33XX_LOWPOWERSTATECHANGE_MASK (1 << 4) | ||
| 201 | |||
| 202 | /* Used by PM_MPU_PWRSTCTRL */ | ||
| 203 | #define AM33XX_MPU_L1_ONSTATE_SHIFT 18 | ||
| 204 | #define AM33XX_MPU_L1_ONSTATE_MASK (0x3 << 18) | ||
| 205 | |||
| 206 | /* Used by PM_MPU_PWRSTCTRL */ | ||
| 207 | #define AM33XX_MPU_L1_RETSTATE_SHIFT 22 | ||
| 208 | #define AM33XX_MPU_L1_RETSTATE_MASK (1 << 22) | ||
| 209 | |||
| 210 | /* Used by PM_MPU_PWRSTST */ | ||
| 211 | #define AM33XX_MPU_L1_STATEST_SHIFT 6 | ||
| 212 | #define AM33XX_MPU_L1_STATEST_MASK (0x3 << 6) | ||
| 213 | |||
| 214 | /* Used by PM_MPU_PWRSTCTRL */ | ||
| 215 | #define AM33XX_MPU_L2_ONSTATE_SHIFT 20 | ||
| 216 | #define AM33XX_MPU_L2_ONSTATE_MASK (0x3 << 20) | ||
| 217 | |||
| 218 | /* Used by PM_MPU_PWRSTCTRL */ | ||
| 219 | #define AM33XX_MPU_L2_RETSTATE_SHIFT 23 | ||
| 220 | #define AM33XX_MPU_L2_RETSTATE_MASK (1 << 23) | ||
| 221 | |||
| 222 | /* Used by PM_MPU_PWRSTST */ | ||
| 223 | #define AM33XX_MPU_L2_STATEST_SHIFT 8 | ||
| 224 | #define AM33XX_MPU_L2_STATEST_MASK (0x3 << 8) | ||
| 225 | |||
| 226 | /* Used by PM_MPU_PWRSTCTRL */ | ||
| 227 | #define AM33XX_MPU_RAM_ONSTATE_SHIFT 16 | ||
| 228 | #define AM33XX_MPU_RAM_ONSTATE_MASK (0x3 << 16) | ||
| 229 | |||
| 230 | /* Used by PM_MPU_PWRSTCTRL */ | ||
| 231 | #define AM33XX_MPU_RAM_RETSTATE_SHIFT 24 | ||
| 232 | #define AM33XX_MPU_RAM_RETSTATE_MASK (1 << 24) | ||
| 233 | |||
| 234 | /* Used by PM_MPU_PWRSTST */ | ||
| 235 | #define AM33XX_MPU_RAM_STATEST_SHIFT 4 | ||
| 236 | #define AM33XX_MPU_RAM_STATEST_MASK (0x3 << 4) | ||
| 237 | |||
| 238 | /* Used by PRM_RSTST */ | ||
| 239 | #define AM33XX_MPU_SECURITY_VIOL_RST_SHIFT 2 | ||
| 240 | #define AM33XX_MPU_SECURITY_VIOL_RST_MASK (1 << 2) | ||
| 241 | |||
| 242 | /* Used by PRM_SRAM_COUNT */ | ||
| 243 | #define AM33XX_PCHARGECNT_VALUE_SHIFT 0 | ||
| 244 | #define AM33XX_PCHARGECNT_VALUE_MASK (0x3f << 0) | ||
| 245 | |||
| 246 | /* Used by RM_PER_RSTCTRL */ | ||
| 247 | #define AM33XX_PCI_LRST_SHIFT 0 | ||
| 248 | #define AM33XX_PCI_LRST_MASK (1 << 0) | ||
| 249 | |||
| 250 | /* Renamed from PCI_LRST Used by RM_PER_RSTST */ | ||
| 251 | #define AM33XX_PCI_LRST_5_5_SHIFT 5 | ||
| 252 | #define AM33XX_PCI_LRST_5_5_MASK (1 << 5) | ||
| 253 | |||
| 254 | /* Used by PM_PER_PWRSTCTRL */ | ||
| 255 | #define AM33XX_PER_MEM_ONSTATE_SHIFT 25 | ||
| 256 | #define AM33XX_PER_MEM_ONSTATE_MASK (0x3 << 25) | ||
| 257 | |||
| 258 | /* Used by PM_PER_PWRSTCTRL */ | ||
| 259 | #define AM33XX_PER_MEM_RETSTATE_SHIFT 29 | ||
| 260 | #define AM33XX_PER_MEM_RETSTATE_MASK (1 << 29) | ||
| 261 | |||
| 262 | /* Used by PM_PER_PWRSTST */ | ||
| 263 | #define AM33XX_PER_MEM_STATEST_SHIFT 17 | ||
| 264 | #define AM33XX_PER_MEM_STATEST_MASK (0x3 << 17) | ||
| 265 | |||
| 266 | /* | ||
| 267 | * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL, | ||
| 268 | * PM_MPU_PWRSTCTRL | ||
| 269 | */ | ||
| 270 | #define AM33XX_POWERSTATE_SHIFT 0 | ||
| 271 | #define AM33XX_POWERSTATE_MASK (0x3 << 0) | ||
| 272 | |||
| 273 | /* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST */ | ||
| 274 | #define AM33XX_POWERSTATEST_SHIFT 0 | ||
| 275 | #define AM33XX_POWERSTATEST_MASK (0x3 << 0) | ||
| 276 | |||
| 277 | /* Used by PM_PER_PWRSTCTRL */ | ||
| 278 | #define AM33XX_RAM_MEM_ONSTATE_SHIFT 30 | ||
| 279 | #define AM33XX_RAM_MEM_ONSTATE_MASK (0x3 << 30) | ||
| 280 | |||
| 281 | /* Used by PM_PER_PWRSTCTRL */ | ||
| 282 | #define AM33XX_RAM_MEM_RETSTATE_SHIFT 27 | ||
| 283 | #define AM33XX_RAM_MEM_RETSTATE_MASK (1 << 27) | ||
| 284 | |||
| 285 | /* Used by PM_PER_PWRSTST */ | ||
| 286 | #define AM33XX_RAM_MEM_STATEST_SHIFT 21 | ||
| 287 | #define AM33XX_RAM_MEM_STATEST_MASK (0x3 << 21) | ||
| 288 | |||
| 289 | /* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */ | ||
| 290 | #define AM33XX_RETMODE_ENABLE_SHIFT 0 | ||
| 291 | #define AM33XX_RETMODE_ENABLE_MASK (1 << 0) | ||
| 292 | |||
| 293 | /* Used by REVISION_PRM */ | ||
| 294 | #define AM33XX_REV_SHIFT 0 | ||
| 295 | #define AM33XX_REV_MASK (0xff << 0) | ||
| 296 | |||
| 297 | /* Used by PRM_RSTTIME */ | ||
| 298 | #define AM33XX_RSTTIME1_SHIFT 0 | ||
| 299 | #define AM33XX_RSTTIME1_MASK (0xff << 0) | ||
| 300 | |||
| 301 | /* Used by PRM_RSTTIME */ | ||
| 302 | #define AM33XX_RSTTIME2_SHIFT 8 | ||
| 303 | #define AM33XX_RSTTIME2_MASK (0x1f << 8) | ||
| 304 | |||
| 305 | /* Used by PRM_RSTCTRL */ | ||
| 306 | #define AM33XX_RST_GLOBAL_COLD_SW_SHIFT 1 | ||
| 307 | #define AM33XX_RST_GLOBAL_COLD_SW_MASK (1 << 1) | ||
| 308 | |||
| 309 | /* Used by PRM_RSTCTRL */ | ||
| 310 | #define AM33XX_RST_GLOBAL_WARM_SW_SHIFT 0 | ||
| 311 | #define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0) | ||
| 312 | |||
| 313 | /* Used by PRM_SRAM_COUNT */ | ||
| 314 | #define AM33XX_SLPCNT_VALUE_SHIFT 16 | ||
| 315 | #define AM33XX_SLPCNT_VALUE_MASK (0xff << 16) | ||
| 316 | |||
| 317 | /* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */ | ||
| 318 | #define AM33XX_SRAMLDO_STATUS_SHIFT 8 | ||
| 319 | #define AM33XX_SRAMLDO_STATUS_MASK (1 << 8) | ||
| 320 | |||
| 321 | /* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */ | ||
| 322 | #define AM33XX_SRAM_IN_TRANSITION_SHIFT 9 | ||
| 323 | #define AM33XX_SRAM_IN_TRANSITION_MASK (1 << 9) | ||
| 324 | |||
| 325 | /* Used by PRM_SRAM_COUNT */ | ||
| 326 | #define AM33XX_STARTUP_COUNT_SHIFT 24 | ||
| 327 | #define AM33XX_STARTUP_COUNT_MASK (0xff << 24) | ||
| 328 | |||
| 329 | /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ | ||
| 330 | #define AM33XX_TRANSITION_EN_SHIFT 8 | ||
| 331 | #define AM33XX_TRANSITION_EN_MASK (1 << 8) | ||
| 332 | |||
| 333 | /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ | ||
| 334 | #define AM33XX_TRANSITION_ST_SHIFT 8 | ||
| 335 | #define AM33XX_TRANSITION_ST_MASK (1 << 8) | ||
| 336 | |||
| 337 | /* Used by PRM_SRAM_COUNT */ | ||
| 338 | #define AM33XX_VSETUPCNT_VALUE_SHIFT 8 | ||
| 339 | #define AM33XX_VSETUPCNT_VALUE_MASK (0xff << 8) | ||
| 340 | |||
| 341 | /* Used by PRM_RSTST */ | ||
| 342 | #define AM33XX_WDT0_RST_SHIFT 3 | ||
| 343 | #define AM33XX_WDT0_RST_MASK (1 << 3) | ||
| 344 | |||
| 345 | /* Used by PRM_RSTST */ | ||
| 346 | #define AM33XX_WDT1_RST_SHIFT 4 | ||
| 347 | #define AM33XX_WDT1_RST_MASK (1 << 4) | ||
| 348 | |||
| 349 | /* Used by RM_WKUP_RSTCTRL */ | ||
| 350 | #define AM33XX_WKUP_M3_LRST_SHIFT 3 | ||
| 351 | #define AM33XX_WKUP_M3_LRST_MASK (1 << 3) | ||
| 352 | |||
| 353 | /* Renamed from WKUP_M3_LRST Used by RM_WKUP_RSTST */ | ||
| 354 | #define AM33XX_WKUP_M3_LRST_5_5_SHIFT 5 | ||
| 355 | #define AM33XX_WKUP_M3_LRST_5_5_MASK (1 << 5) | ||
| 356 | |||
| 357 | #endif | ||
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c new file mode 100644 index 000000000000..e7dbb6cf1255 --- /dev/null +++ b/arch/arm/mach-omap2/prm33xx.c | |||
| @@ -0,0 +1,135 @@ | |||
| 1 | /* | ||
| 2 | * AM33XX PRM functions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License as | ||
| 8 | * published by the Free Software Foundation version 2. | ||
| 9 | * | ||
| 10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
| 11 | * kind, whether express or implied; without even the implied warranty | ||
| 12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include <linux/kernel.h> | ||
| 17 | #include <linux/types.h> | ||
| 18 | #include <linux/errno.h> | ||
| 19 | #include <linux/err.h> | ||
| 20 | #include <linux/io.h> | ||
| 21 | |||
| 22 | #include <plat/common.h> | ||
| 23 | |||
| 24 | #include "common.h" | ||
| 25 | #include "prm33xx.h" | ||
| 26 | #include "prm-regbits-33xx.h" | ||
| 27 | |||
| 28 | /* Read a register in a PRM instance */ | ||
| 29 | u32 am33xx_prm_read_reg(s16 inst, u16 idx) | ||
| 30 | { | ||
| 31 | return __raw_readl(prm_base + inst + idx); | ||
| 32 | } | ||
| 33 | |||
| 34 | /* Write into a register in a PRM instance */ | ||
| 35 | void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx) | ||
| 36 | { | ||
| 37 | __raw_writel(val, prm_base + inst + idx); | ||
| 38 | } | ||
| 39 | |||
| 40 | /* Read-modify-write a register in PRM. Caller must lock */ | ||
| 41 | u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx) | ||
| 42 | { | ||
| 43 | u32 v; | ||
| 44 | |||
| 45 | v = am33xx_prm_read_reg(inst, idx); | ||
| 46 | v &= ~mask; | ||
| 47 | v |= bits; | ||
| 48 | am33xx_prm_write_reg(v, inst, idx); | ||
| 49 | |||
| 50 | return v; | ||
| 51 | } | ||
| 52 | |||
| 53 | /** | ||
| 54 | * am33xx_prm_is_hardreset_asserted - read the HW reset line state of | ||
| 55 | * submodules contained in the hwmod module | ||
| 56 | * @shift: register bit shift corresponding to the reset line to check | ||
| 57 | * @inst: CM instance register offset (*_INST macro) | ||
| 58 | * @rstctrl_offs: RM_RSTCTRL register address offset for this module | ||
| 59 | * | ||
| 60 | * Returns 1 if the (sub)module hardreset line is currently asserted, | ||
| 61 | * 0 if the (sub)module hardreset line is not currently asserted, or | ||
| 62 | * -EINVAL upon parameter error. | ||
| 63 | */ | ||
| 64 | int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst, u16 rstctrl_offs) | ||
| 65 | { | ||
| 66 | u32 v; | ||
| 67 | |||
| 68 | v = am33xx_prm_read_reg(inst, rstctrl_offs); | ||
| 69 | v &= 1 << shift; | ||
| 70 | v >>= shift; | ||
| 71 | |||
| 72 | return v; | ||
| 73 | } | ||
| 74 | |||
| 75 | /** | ||
| 76 | * am33xx_prm_assert_hardreset - assert the HW reset line of a submodule | ||
| 77 | * @shift: register bit shift corresponding to the reset line to assert | ||
| 78 | * @inst: CM instance register offset (*_INST macro) | ||
| 79 | * @rstctrl_reg: RM_RSTCTRL register address for this module | ||
| 80 | * | ||
| 81 | * Some IPs like dsp, ipu or iva contain processors that require an HW | ||
| 82 | * reset line to be asserted / deasserted in order to fully enable the | ||
| 83 | * IP. These modules may have multiple hard-reset lines that reset | ||
| 84 | * different 'submodules' inside the IP block. This function will | ||
| 85 | * place the submodule into reset. Returns 0 upon success or -EINVAL | ||
| 86 | * upon an argument error. | ||
| 87 | */ | ||
| 88 | int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs) | ||
| 89 | { | ||
| 90 | u32 mask = 1 << shift; | ||
| 91 | |||
| 92 | am33xx_prm_rmw_reg_bits(mask, mask, inst, rstctrl_offs); | ||
| 93 | |||
| 94 | return 0; | ||
| 95 | } | ||
| 96 | |||
| 97 | /** | ||
| 98 | * am33xx_prm_deassert_hardreset - deassert a submodule hardreset line and | ||
| 99 | * wait | ||
| 100 | * @shift: register bit shift corresponding to the reset line to deassert | ||
| 101 | * @inst: CM instance register offset (*_INST macro) | ||
| 102 | * @rstctrl_reg: RM_RSTCTRL register address for this module | ||
| 103 | * @rstst_reg: RM_RSTST register address for this module | ||
| 104 | * | ||
| 105 | * Some IPs like dsp, ipu or iva contain processors that require an HW | ||
| 106 | * reset line to be asserted / deasserted in order to fully enable the | ||
| 107 | * IP. These modules may have multiple hard-reset lines that reset | ||
| 108 | * different 'submodules' inside the IP block. This function will | ||
| 109 | * take the submodule out of reset and wait until the PRCM indicates | ||
| 110 | * that the reset has completed before returning. Returns 0 upon success or | ||
| 111 | * -EINVAL upon an argument error, -EEXIST if the submodule was already out | ||
| 112 | * of reset, or -EBUSY if the submodule did not exit reset promptly. | ||
| 113 | */ | ||
| 114 | int am33xx_prm_deassert_hardreset(u8 shift, s16 inst, | ||
| 115 | u16 rstctrl_offs, u16 rstst_offs) | ||
| 116 | { | ||
| 117 | int c; | ||
| 118 | u32 mask = 1 << shift; | ||
| 119 | |||
| 120 | /* Check the current status to avoid de-asserting the line twice */ | ||
| 121 | if (am33xx_prm_is_hardreset_asserted(shift, inst, rstctrl_offs) == 0) | ||
| 122 | return -EEXIST; | ||
| 123 | |||
| 124 | /* Clear the reset status by writing 1 to the status bit */ | ||
| 125 | am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs); | ||
| 126 | /* de-assert the reset control line */ | ||
| 127 | am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs); | ||
| 128 | /* wait the status to be set */ | ||
| 129 | |||
| 130 | omap_test_timeout(am33xx_prm_is_hardreset_asserted(shift, inst, | ||
| 131 | rstst_offs), | ||
| 132 | MAX_MODULE_HARDRESET_WAIT, c); | ||
| 133 | |||
| 134 | return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; | ||
| 135 | } | ||
diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h new file mode 100644 index 000000000000..3f25c563a821 --- /dev/null +++ b/arch/arm/mach-omap2/prm33xx.h | |||
| @@ -0,0 +1,129 @@ | |||
| 1 | /* | ||
| 2 | * AM33XX PRM instance offset macros | ||
| 3 | * | ||
| 4 | * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License as | ||
| 8 | * published by the Free Software Foundation version 2. | ||
| 9 | * | ||
| 10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
| 11 | * kind, whether express or implied; without even the implied warranty | ||
| 12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM33XX_H | ||
| 17 | #define __ARCH_ARM_MACH_OMAP2_PRM33XX_H | ||
| 18 | |||
| 19 | #include "prcm-common.h" | ||
| 20 | #include "prm.h" | ||
| 21 | |||
| 22 | #define AM33XX_PRM_BASE 0x44E00000 | ||
| 23 | |||
| 24 | #define AM33XX_PRM_REGADDR(inst, reg) \ | ||
| 25 | AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRM_BASE + (inst) + (reg)) | ||
| 26 | |||
| 27 | |||
| 28 | /* PRM instances */ | ||
| 29 | #define AM33XX_PRM_OCP_SOCKET_MOD 0x0B00 | ||
| 30 | #define AM33XX_PRM_PER_MOD 0x0C00 | ||
| 31 | #define AM33XX_PRM_WKUP_MOD 0x0D00 | ||
| 32 | #define AM33XX_PRM_MPU_MOD 0x0E00 | ||
| 33 | #define AM33XX_PRM_DEVICE_MOD 0x0F00 | ||
| 34 | #define AM33XX_PRM_RTC_MOD 0x1000 | ||
| 35 | #define AM33XX_PRM_GFX_MOD 0x1100 | ||
| 36 | #define AM33XX_PRM_CEFUSE_MOD 0x1200 | ||
| 37 | |||
| 38 | /* PRM */ | ||
| 39 | |||
| 40 | /* PRM.OCP_SOCKET_PRM register offsets */ | ||
| 41 | #define AM33XX_REVISION_PRM_OFFSET 0x0000 | ||
| 42 | #define AM33XX_REVISION_PRM AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0000) | ||
| 43 | #define AM33XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004 | ||
| 44 | #define AM33XX_PRM_IRQSTATUS_MPU AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0004) | ||
| 45 | #define AM33XX_PRM_IRQENABLE_MPU_OFFSET 0x0008 | ||
| 46 | #define AM33XX_PRM_IRQENABLE_MPU AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0008) | ||
| 47 | #define AM33XX_PRM_IRQSTATUS_M3_OFFSET 0x000c | ||
| 48 | #define AM33XX_PRM_IRQSTATUS_M3 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x000c) | ||
| 49 | #define AM33XX_PRM_IRQENABLE_M3_OFFSET 0x0010 | ||
| 50 | #define AM33XX_PRM_IRQENABLE_M3 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0010) | ||
| 51 | |||
| 52 | /* PRM.PER_PRM register offsets */ | ||
| 53 | #define AM33XX_RM_PER_RSTCTRL_OFFSET 0x0000 | ||
| 54 | #define AM33XX_RM_PER_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0000) | ||
| 55 | #define AM33XX_RM_PER_RSTST_OFFSET 0x0004 | ||
| 56 | #define AM33XX_RM_PER_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0004) | ||
| 57 | #define AM33XX_PM_PER_PWRSTST_OFFSET 0x0008 | ||
| 58 | #define AM33XX_PM_PER_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0008) | ||
| 59 | #define AM33XX_PM_PER_PWRSTCTRL_OFFSET 0x000c | ||
| 60 | #define AM33XX_PM_PER_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x000c) | ||
| 61 | |||
| 62 | /* PRM.WKUP_PRM register offsets */ | ||
| 63 | #define AM33XX_RM_WKUP_RSTCTRL_OFFSET 0x0000 | ||
| 64 | #define AM33XX_RM_WKUP_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0000) | ||
| 65 | #define AM33XX_PM_WKUP_PWRSTCTRL_OFFSET 0x0004 | ||
| 66 | #define AM33XX_PM_WKUP_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0004) | ||
| 67 | #define AM33XX_PM_WKUP_PWRSTST_OFFSET 0x0008 | ||
| 68 | #define AM33XX_PM_WKUP_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0008) | ||
| 69 | #define AM33XX_RM_WKUP_RSTST_OFFSET 0x000c | ||
| 70 | #define AM33XX_RM_WKUP_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x000c) | ||
| 71 | |||
| 72 | /* PRM.MPU_PRM register offsets */ | ||
| 73 | #define AM33XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000 | ||
| 74 | #define AM33XX_PM_MPU_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0000) | ||
| 75 | #define AM33XX_PM_MPU_PWRSTST_OFFSET 0x0004 | ||
| 76 | #define AM33XX_PM_MPU_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0004) | ||
| 77 | #define AM33XX_RM_MPU_RSTST_OFFSET 0x0008 | ||
| 78 | #define AM33XX_RM_MPU_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0008) | ||
| 79 | |||
| 80 | /* PRM.DEVICE_PRM register offsets */ | ||
| 81 | #define AM33XX_PRM_RSTCTRL_OFFSET 0x0000 | ||
| 82 | #define AM33XX_PRM_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0000) | ||
| 83 | #define AM33XX_PRM_RSTTIME_OFFSET 0x0004 | ||
| 84 | #define AM33XX_PRM_RSTTIME AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0004) | ||
| 85 | #define AM33XX_PRM_RSTST_OFFSET 0x0008 | ||
| 86 | #define AM33XX_PRM_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0008) | ||
| 87 | #define AM33XX_PRM_SRAM_COUNT_OFFSET 0x000c | ||
| 88 | #define AM33XX_PRM_SRAM_COUNT AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x000c) | ||
| 89 | #define AM33XX_PRM_LDO_SRAM_CORE_SETUP_OFFSET 0x0010 | ||
| 90 | #define AM33XX_PRM_LDO_SRAM_CORE_SETUP AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0010) | ||
| 91 | #define AM33XX_PRM_LDO_SRAM_CORE_CTRL_OFFSET 0x0014 | ||
| 92 | #define AM33XX_PRM_LDO_SRAM_CORE_CTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0014) | ||
| 93 | #define AM33XX_PRM_LDO_SRAM_MPU_SETUP_OFFSET 0x0018 | ||
| 94 | #define AM33XX_PRM_LDO_SRAM_MPU_SETUP AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0018) | ||
| 95 | #define AM33XX_PRM_LDO_SRAM_MPU_CTRL_OFFSET 0x001c | ||
| 96 | #define AM33XX_PRM_LDO_SRAM_MPU_CTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x001c) | ||
| 97 | |||
| 98 | /* PRM.RTC_PRM register offsets */ | ||
| 99 | #define AM33XX_PM_RTC_PWRSTCTRL_OFFSET 0x0000 | ||
| 100 | #define AM33XX_PM_RTC_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0000) | ||
| 101 | #define AM33XX_PM_RTC_PWRSTST_OFFSET 0x0004 | ||
| 102 | #define AM33XX_PM_RTC_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0004) | ||
| 103 | |||
| 104 | /* PRM.GFX_PRM register offsets */ | ||
| 105 | #define AM33XX_PM_GFX_PWRSTCTRL_OFFSET 0x0000 | ||
| 106 | #define AM33XX_PM_GFX_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0000) | ||
| 107 | #define AM33XX_RM_GFX_RSTCTRL_OFFSET 0x0004 | ||
| 108 | #define AM33XX_RM_GFX_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0004) | ||
| 109 | #define AM33XX_PM_GFX_PWRSTST_OFFSET 0x0010 | ||
| 110 | #define AM33XX_PM_GFX_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0010) | ||
| 111 | #define AM33XX_RM_GFX_RSTST_OFFSET 0x0014 | ||
| 112 | #define AM33XX_RM_GFX_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0014) | ||
| 113 | |||
| 114 | /* PRM.CEFUSE_PRM register offsets */ | ||
| 115 | #define AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET 0x0000 | ||
| 116 | #define AM33XX_PM_CEFUSE_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0000) | ||
| 117 | #define AM33XX_PM_CEFUSE_PWRSTST_OFFSET 0x0004 | ||
| 118 | #define AM33XX_PM_CEFUSE_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004) | ||
| 119 | |||
| 120 | extern u32 am33xx_prm_read_reg(s16 inst, u16 idx); | ||
| 121 | extern void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx); | ||
| 122 | extern u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); | ||
| 123 | extern void am33xx_prm_global_warm_sw_reset(void); | ||
| 124 | extern int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst, | ||
| 125 | u16 rstctrl_offs); | ||
| 126 | extern int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs); | ||
| 127 | extern int am33xx_prm_deassert_hardreset(u8 shift, s16 inst, | ||
| 128 | u16 rstctrl_offs, u16 rstst_offs); | ||
| 129 | #endif | ||
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index dfe00ddb5c60..534d732caa1e 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c | |||
| @@ -85,7 +85,7 @@ static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
| 85 | unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG]; | 85 | unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG]; |
| 86 | struct irq_chip *chip = irq_desc_get_chip(desc); | 86 | struct irq_chip *chip = irq_desc_get_chip(desc); |
| 87 | unsigned int virtirq; | 87 | unsigned int virtirq; |
| 88 | int nr_irqs = prcm_irq_setup->nr_regs * 32; | 88 | int nr_irq = prcm_irq_setup->nr_regs * 32; |
| 89 | 89 | ||
| 90 | /* | 90 | /* |
| 91 | * If we are suspended, mask all interrupts from PRCM level, | 91 | * If we are suspended, mask all interrupts from PRCM level, |
| @@ -110,7 +110,7 @@ static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
| 110 | prcm_irq_setup->read_pending_irqs(pending); | 110 | prcm_irq_setup->read_pending_irqs(pending); |
| 111 | 111 | ||
| 112 | /* No bit set, then all IRQs are handled */ | 112 | /* No bit set, then all IRQs are handled */ |
| 113 | if (find_first_bit(pending, nr_irqs) >= nr_irqs) | 113 | if (find_first_bit(pending, nr_irq) >= nr_irq) |
| 114 | break; | 114 | break; |
| 115 | 115 | ||
| 116 | omap_prcm_events_filter_priority(pending, priority_pending); | 116 | omap_prcm_events_filter_priority(pending, priority_pending); |
| @@ -121,11 +121,11 @@ static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
| 121 | */ | 121 | */ |
| 122 | 122 | ||
| 123 | /* Serve priority events first */ | 123 | /* Serve priority events first */ |
| 124 | for_each_set_bit(virtirq, priority_pending, nr_irqs) | 124 | for_each_set_bit(virtirq, priority_pending, nr_irq) |
| 125 | generic_handle_irq(prcm_irq_setup->base_irq + virtirq); | 125 | generic_handle_irq(prcm_irq_setup->base_irq + virtirq); |
| 126 | 126 | ||
| 127 | /* Serve normal events next */ | 127 | /* Serve normal events next */ |
| 128 | for_each_set_bit(virtirq, pending, nr_irqs) | 128 | for_each_set_bit(virtirq, pending, nr_irq) |
| 129 | generic_handle_irq(prcm_irq_setup->base_irq + virtirq); | 129 | generic_handle_irq(prcm_irq_setup->base_irq + virtirq); |
| 130 | } | 130 | } |
| 131 | if (chip->irq_ack) | 131 | if (chip->irq_ack) |
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 840929bd9dae..ea6a0eb13f05 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c | |||
| @@ -368,6 +368,11 @@ OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE, | |||
| 368 | OMAP_SYS_TIMER(3_secure) | 368 | OMAP_SYS_TIMER(3_secure) |
| 369 | #endif | 369 | #endif |
| 370 | 370 | ||
| 371 | #ifdef CONFIG_SOC_AM33XX | ||
| 372 | OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE) | ||
| 373 | OMAP_SYS_TIMER(3_am33xx) | ||
| 374 | #endif | ||
| 375 | |||
| 371 | #ifdef CONFIG_ARCH_OMAP4 | 376 | #ifdef CONFIG_ARCH_OMAP4 |
| 372 | #ifdef CONFIG_LOCAL_TIMERS | 377 | #ifdef CONFIG_LOCAL_TIMERS |
| 373 | static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, | 378 | static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, |
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c index 43a979075338..3882f3c7608c 100644 --- a/arch/arm/mach-omap2/twl-common.c +++ b/arch/arm/mach-omap2/twl-common.c | |||
| @@ -49,6 +49,7 @@ static struct i2c_board_info __initdata omap4_i2c1_board_info[] = { | |||
| 49 | }, | 49 | }, |
| 50 | }; | 50 | }; |
| 51 | 51 | ||
| 52 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) | ||
| 52 | static int twl_set_voltage(void *data, int target_uV) | 53 | static int twl_set_voltage(void *data, int target_uV) |
| 53 | { | 54 | { |
| 54 | struct voltagedomain *voltdm = (struct voltagedomain *)data; | 55 | struct voltagedomain *voltdm = (struct voltagedomain *)data; |
| @@ -60,6 +61,7 @@ static int twl_get_voltage(void *data) | |||
| 60 | struct voltagedomain *voltdm = (struct voltagedomain *)data; | 61 | struct voltagedomain *voltdm = (struct voltagedomain *)data; |
| 61 | return voltdm_get_voltage(voltdm); | 62 | return voltdm_get_voltage(voltdm); |
| 62 | } | 63 | } |
| 64 | #endif | ||
| 63 | 65 | ||
| 64 | void __init omap_pmic_init(int bus, u32 clkrate, | 66 | void __init omap_pmic_init(int bus, u32 clkrate, |
| 65 | const char *pmic_type, int pmic_irq, | 67 | const char *pmic_type, int pmic_irq, |
| @@ -213,10 +215,6 @@ static struct twl_regulator_driver_data omap3_vdd2_drvdata = { | |||
| 213 | void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data, | 215 | void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data, |
| 214 | u32 pdata_flags, u32 regulators_flags) | 216 | u32 pdata_flags, u32 regulators_flags) |
| 215 | { | 217 | { |
| 216 | if (!pmic_data->irq_base) | ||
| 217 | pmic_data->irq_base = TWL4030_IRQ_BASE; | ||
| 218 | if (!pmic_data->irq_end) | ||
| 219 | pmic_data->irq_end = TWL4030_IRQ_END; | ||
| 220 | if (!pmic_data->vdd1) { | 218 | if (!pmic_data->vdd1) { |
| 221 | omap3_vdd1.driver_data = &omap3_vdd1_drvdata; | 219 | omap3_vdd1.driver_data = &omap3_vdd1_drvdata; |
| 222 | omap3_vdd1_drvdata.data = voltdm_lookup("mpu_iva"); | 220 | omap3_vdd1_drvdata.data = voltdm_lookup("mpu_iva"); |
| @@ -481,11 +479,6 @@ static struct regulator_init_data omap4_v2v1_idata = { | |||
| 481 | void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data, | 479 | void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data, |
| 482 | u32 pdata_flags, u32 regulators_flags) | 480 | u32 pdata_flags, u32 regulators_flags) |
| 483 | { | 481 | { |
| 484 | if (!pmic_data->irq_base) | ||
| 485 | pmic_data->irq_base = TWL6030_IRQ_BASE; | ||
| 486 | if (!pmic_data->irq_end) | ||
| 487 | pmic_data->irq_end = TWL6030_IRQ_END; | ||
| 488 | |||
| 489 | if (!pmic_data->vdd1) { | 482 | if (!pmic_data->vdd1) { |
| 490 | omap4_vdd1.driver_data = &omap4_vdd1_drvdata; | 483 | omap4_vdd1.driver_data = &omap4_vdd1_drvdata; |
| 491 | omap4_vdd1_drvdata.data = voltdm_lookup("mpu"); | 484 | omap4_vdd1_drvdata.data = voltdm_lookup("mpu"); |
diff --git a/arch/arm/mach-omap2/usb-fs.c b/arch/arm/mach-omap2/usb-fs.c deleted file mode 100644 index 1481078763b8..000000000000 --- a/arch/arm/mach-omap2/usb-fs.c +++ /dev/null | |||
| @@ -1,359 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Platform level USB initialization for FS USB OTG controller on omap1 and 24xx | ||
| 3 | * | ||
| 4 | * Copyright (C) 2004 Texas Instruments, Inc. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include <linux/module.h> | ||
| 22 | #include <linux/kernel.h> | ||
| 23 | #include <linux/types.h> | ||
| 24 | #include <linux/errno.h> | ||
| 25 | #include <linux/init.h> | ||
| 26 | #include <linux/platform_device.h> | ||
| 27 | #include <linux/clk.h> | ||
| 28 | #include <linux/err.h> | ||
| 29 | |||
| 30 | #include <asm/irq.h> | ||
| 31 | |||
| 32 | #include <plat/usb.h> | ||
| 33 | #include <plat/board.h> | ||
| 34 | |||
| 35 | #include "control.h" | ||
| 36 | #include "mux.h" | ||
| 37 | |||
| 38 | #define INT_USB_IRQ_GEN INT_24XX_USB_IRQ_GEN | ||
| 39 | #define INT_USB_IRQ_NISO INT_24XX_USB_IRQ_NISO | ||
| 40 | #define INT_USB_IRQ_ISO INT_24XX_USB_IRQ_ISO | ||
| 41 | #define INT_USB_IRQ_HGEN INT_24XX_USB_IRQ_HGEN | ||
| 42 | #define INT_USB_IRQ_OTG INT_24XX_USB_IRQ_OTG | ||
| 43 | |||
| 44 | #if defined(CONFIG_ARCH_OMAP2) | ||
| 45 | |||
| 46 | #ifdef CONFIG_USB_GADGET_OMAP | ||
| 47 | |||
| 48 | static struct resource udc_resources[] = { | ||
| 49 | /* order is significant! */ | ||
| 50 | { /* registers */ | ||
| 51 | .start = UDC_BASE, | ||
| 52 | .end = UDC_BASE + 0xff, | ||
| 53 | .flags = IORESOURCE_MEM, | ||
| 54 | }, { /* general IRQ */ | ||
| 55 | .start = INT_USB_IRQ_GEN, | ||
| 56 | .flags = IORESOURCE_IRQ, | ||
| 57 | }, { /* PIO IRQ */ | ||
| 58 | .start = INT_USB_IRQ_NISO, | ||
| 59 | .flags = IORESOURCE_IRQ, | ||
| 60 | }, { /* SOF IRQ */ | ||
| 61 | .start = INT_USB_IRQ_ISO, | ||
| 62 | .flags = IORESOURCE_IRQ, | ||
| 63 | }, | ||
| 64 | }; | ||
| 65 | |||
| 66 | static u64 udc_dmamask = ~(u32)0; | ||
| 67 | |||
| 68 | static struct platform_device udc_device = { | ||
| 69 | .name = "omap_udc", | ||
| 70 | .id = -1, | ||
| 71 | .dev = { | ||
| 72 | .dma_mask = &udc_dmamask, | ||
| 73 | .coherent_dma_mask = 0xffffffff, | ||
| 74 | }, | ||
| 75 | .num_resources = ARRAY_SIZE(udc_resources), | ||
| 76 | .resource = udc_resources, | ||
| 77 | }; | ||
| 78 | |||
| 79 | static inline void udc_device_init(struct omap_usb_config *pdata) | ||
| 80 | { | ||
| 81 | pdata->udc_device = &udc_device; | ||
| 82 | } | ||
| 83 | |||
| 84 | #else | ||
| 85 | |||
| 86 | static inline void udc_device_init(struct omap_usb_config *pdata) | ||
| 87 | { | ||
| 88 | } | ||
| 89 | |||
| 90 | #endif | ||
| 91 | |||
| 92 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | ||
| 93 | |||
| 94 | /* The dmamask must be set for OHCI to work */ | ||
| 95 | static u64 ohci_dmamask = ~(u32)0; | ||
| 96 | |||
| 97 | static struct resource ohci_resources[] = { | ||
| 98 | { | ||
| 99 | .start = OMAP_OHCI_BASE, | ||
| 100 | .end = OMAP_OHCI_BASE + 0xff, | ||
| 101 | .flags = IORESOURCE_MEM, | ||
| 102 | }, | ||
| 103 | { | ||
| 104 | .start = INT_USB_IRQ_HGEN, | ||
| 105 | .flags = IORESOURCE_IRQ, | ||
| 106 | }, | ||
| 107 | }; | ||
| 108 | |||
| 109 | static struct platform_device ohci_device = { | ||
| 110 | .name = "ohci", | ||
| 111 | .id = -1, | ||
| 112 | .dev = { | ||
| 113 | .dma_mask = &ohci_dmamask, | ||
| 114 | .coherent_dma_mask = 0xffffffff, | ||
| 115 | }, | ||
| 116 | .num_resources = ARRAY_SIZE(ohci_resources), | ||
| 117 | .resource = ohci_resources, | ||
| 118 | }; | ||
| 119 | |||
| 120 | static inline void ohci_device_init(struct omap_usb_config *pdata) | ||
| 121 | { | ||
| 122 | pdata->ohci_device = &ohci_device; | ||
| 123 | } | ||
| 124 | |||
| 125 | #else | ||
| 126 | |||
| 127 | static inline void ohci_device_init(struct omap_usb_config *pdata) | ||
| 128 | { | ||
| 129 | } | ||
| 130 | |||
| 131 | #endif | ||
| 132 | |||
| 133 | #if defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG) | ||
| 134 | |||
| 135 | static struct resource otg_resources[] = { | ||
| 136 | /* order is significant! */ | ||
| 137 | { | ||
| 138 | .start = OTG_BASE, | ||
| 139 | .end = OTG_BASE + 0xff, | ||
| 140 | .flags = IORESOURCE_MEM, | ||
| 141 | }, { | ||
| 142 | .start = INT_USB_IRQ_OTG, | ||
| 143 | .flags = IORESOURCE_IRQ, | ||
| 144 | }, | ||
| 145 | }; | ||
| 146 | |||
| 147 | static struct platform_device otg_device = { | ||
| 148 | .name = "omap_otg", | ||
| 149 | .id = -1, | ||
| 150 | .num_resources = ARRAY_SIZE(otg_resources), | ||
| 151 | .resource = otg_resources, | ||
| 152 | }; | ||
| 153 | |||
| 154 | static inline void otg_device_init(struct omap_usb_config *pdata) | ||
| 155 | { | ||
| 156 | pdata->otg_device = &otg_device; | ||
| 157 | } | ||
| 158 | |||
| 159 | #else | ||
| 160 | |||
| 161 | static inline void otg_device_init(struct omap_usb_config *pdata) | ||
| 162 | { | ||
| 163 | } | ||
| 164 | |||
| 165 | #endif | ||
| 166 | |||
| 167 | static void omap2_usb_devconf_clear(u8 port, u32 mask) | ||
| 168 | { | ||
| 169 | u32 r; | ||
| 170 | |||
| 171 | r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | ||
| 172 | r &= ~USBTXWRMODEI(port, mask); | ||
| 173 | omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); | ||
| 174 | } | ||
| 175 | |||
| 176 | static void omap2_usb_devconf_set(u8 port, u32 mask) | ||
| 177 | { | ||
| 178 | u32 r; | ||
| 179 | |||
| 180 | r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | ||
| 181 | r |= USBTXWRMODEI(port, mask); | ||
| 182 | omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); | ||
| 183 | } | ||
| 184 | |||
| 185 | static void omap2_usb2_disable_5pinbitll(void) | ||
| 186 | { | ||
| 187 | u32 r; | ||
| 188 | |||
| 189 | r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | ||
| 190 | r &= ~(USBTXWRMODEI(2, USB_BIDIR_TLL) | USBT2TLL5PI); | ||
| 191 | omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); | ||
| 192 | } | ||
| 193 | |||
| 194 | static void omap2_usb2_enable_5pinunitll(void) | ||
| 195 | { | ||
| 196 | u32 r; | ||
| 197 | |||
| 198 | r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | ||
| 199 | r |= USBTXWRMODEI(2, USB_UNIDIR_TLL) | USBT2TLL5PI; | ||
| 200 | omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); | ||
| 201 | } | ||
| 202 | |||
| 203 | static u32 __init omap2_usb0_init(unsigned nwires, unsigned is_device) | ||
| 204 | { | ||
| 205 | u32 syscon1 = 0; | ||
| 206 | |||
| 207 | omap2_usb_devconf_clear(0, USB_BIDIR_TLL); | ||
| 208 | |||
| 209 | if (nwires == 0) | ||
| 210 | return 0; | ||
| 211 | |||
| 212 | if (is_device) | ||
| 213 | omap_mux_init_signal("usb0_puen", 0); | ||
| 214 | |||
| 215 | omap_mux_init_signal("usb0_dat", 0); | ||
| 216 | omap_mux_init_signal("usb0_txen", 0); | ||
| 217 | omap_mux_init_signal("usb0_se0", 0); | ||
| 218 | if (nwires != 3) | ||
| 219 | omap_mux_init_signal("usb0_rcv", 0); | ||
| 220 | |||
| 221 | switch (nwires) { | ||
| 222 | case 3: | ||
| 223 | syscon1 = 2; | ||
| 224 | omap2_usb_devconf_set(0, USB_BIDIR); | ||
| 225 | break; | ||
| 226 | case 4: | ||
| 227 | syscon1 = 1; | ||
| 228 | omap2_usb_devconf_set(0, USB_BIDIR); | ||
| 229 | break; | ||
| 230 | case 6: | ||
| 231 | syscon1 = 3; | ||
| 232 | omap_mux_init_signal("usb0_vp", 0); | ||
| 233 | omap_mux_init_signal("usb0_vm", 0); | ||
| 234 | omap2_usb_devconf_set(0, USB_UNIDIR); | ||
| 235 | break; | ||
| 236 | default: | ||
| 237 | printk(KERN_ERR "illegal usb%d %d-wire transceiver\n", | ||
| 238 | 0, nwires); | ||
| 239 | } | ||
| 240 | |||
| 241 | return syscon1 << 16; | ||
| 242 | } | ||
| 243 | |||
| 244 | static u32 __init omap2_usb1_init(unsigned nwires) | ||
| 245 | { | ||
| 246 | u32 syscon1 = 0; | ||
| 247 | |||
| 248 | omap2_usb_devconf_clear(1, USB_BIDIR_TLL); | ||
| 249 | |||
| 250 | if (nwires == 0) | ||
| 251 | return 0; | ||
| 252 | |||
| 253 | /* NOTE: board-specific code must set up pin muxing for usb1, | ||
| 254 | * since each signal could come out on either of two balls. | ||
| 255 | */ | ||
| 256 | |||
| 257 | switch (nwires) { | ||
| 258 | case 2: | ||
| 259 | /* NOTE: board-specific code must override this setting if | ||
| 260 | * this TLL link is not using DP/DM | ||
| 261 | */ | ||
| 262 | syscon1 = 1; | ||
| 263 | omap2_usb_devconf_set(1, USB_BIDIR_TLL); | ||
| 264 | break; | ||
| 265 | case 3: | ||
| 266 | syscon1 = 2; | ||
| 267 | omap2_usb_devconf_set(1, USB_BIDIR); | ||
| 268 | break; | ||
| 269 | case 4: | ||
| 270 | syscon1 = 1; | ||
| 271 | omap2_usb_devconf_set(1, USB_BIDIR); | ||
| 272 | break; | ||
| 273 | case 6: | ||
| 274 | default: | ||
| 275 | printk(KERN_ERR "illegal usb%d %d-wire transceiver\n", | ||
| 276 | 1, nwires); | ||
| 277 | } | ||
| 278 | |||
| 279 | return syscon1 << 20; | ||
| 280 | } | ||
| 281 | |||
| 282 | static u32 __init omap2_usb2_init(unsigned nwires, unsigned alt_pingroup) | ||
| 283 | { | ||
| 284 | u32 syscon1 = 0; | ||
| 285 | |||
| 286 | omap2_usb2_disable_5pinbitll(); | ||
| 287 | alt_pingroup = 0; | ||
| 288 | |||
| 289 | /* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */ | ||
| 290 | if (alt_pingroup || nwires == 0) | ||
| 291 | return 0; | ||
| 292 | |||
| 293 | omap_mux_init_signal("usb2_dat", 0); | ||
| 294 | omap_mux_init_signal("usb2_se0", 0); | ||
| 295 | if (nwires > 2) | ||
| 296 | omap_mux_init_signal("usb2_txen", 0); | ||
| 297 | if (nwires > 3) | ||
| 298 | omap_mux_init_signal("usb2_rcv", 0); | ||
| 299 | |||
| 300 | switch (nwires) { | ||
| 301 | case 2: | ||
| 302 | /* NOTE: board-specific code must override this setting if | ||
| 303 | * this TLL link is not using DP/DM | ||
| 304 | */ | ||
| 305 | syscon1 = 1; | ||
| 306 | omap2_usb_devconf_set(2, USB_BIDIR_TLL); | ||
| 307 | break; | ||
| 308 | case 3: | ||
| 309 | syscon1 = 2; | ||
| 310 | omap2_usb_devconf_set(2, USB_BIDIR); | ||
| 311 | break; | ||
| 312 | case 4: | ||
| 313 | syscon1 = 1; | ||
| 314 | omap2_usb_devconf_set(2, USB_BIDIR); | ||
| 315 | break; | ||
| 316 | case 5: | ||
| 317 | /* NOTE: board-specific code must mux this setting depending | ||
| 318 | * on TLL link using DP/DM. Something must also | ||
| 319 | * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED} | ||
| 320 | * 2420: hdq_sio.usb2_tllse0 or vlynq_rx0.usb2_tllse0 | ||
| 321 | * 2430: hdq_sio.usb2_tllse0 or sdmmc2_dat0.usb2_tllse0 | ||
| 322 | */ | ||
| 323 | |||
| 324 | syscon1 = 3; | ||
| 325 | omap2_usb2_enable_5pinunitll(); | ||
| 326 | break; | ||
| 327 | case 6: | ||
| 328 | default: | ||
| 329 | printk(KERN_ERR "illegal usb%d %d-wire transceiver\n", | ||
| 330 | 2, nwires); | ||
| 331 | } | ||
| 332 | |||
| 333 | return syscon1 << 24; | ||
| 334 | } | ||
| 335 | |||
| 336 | void __init omap2_usbfs_init(struct omap_usb_config *pdata) | ||
| 337 | { | ||
| 338 | struct clk *ick; | ||
| 339 | |||
| 340 | if (!cpu_is_omap24xx()) | ||
| 341 | return; | ||
| 342 | |||
| 343 | ick = clk_get(NULL, "usb_l4_ick"); | ||
| 344 | if (IS_ERR(ick)) | ||
| 345 | return; | ||
| 346 | |||
| 347 | clk_enable(ick); | ||
| 348 | pdata->usb0_init = omap2_usb0_init; | ||
| 349 | pdata->usb1_init = omap2_usb1_init; | ||
| 350 | pdata->usb2_init = omap2_usb2_init; | ||
| 351 | udc_device_init(pdata); | ||
| 352 | ohci_device_init(pdata); | ||
| 353 | otg_device_init(pdata); | ||
| 354 | omap_otg_init(pdata); | ||
| 355 | clk_disable(ick); | ||
| 356 | clk_put(ick); | ||
| 357 | } | ||
| 358 | |||
| 359 | #endif | ||
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h index 16a1b092cf36..a7c43c1042be 100644 --- a/arch/arm/mach-omap2/voltage.h +++ b/arch/arm/mach-omap2/voltage.h | |||
| @@ -156,6 +156,7 @@ int omap_voltage_late_init(void); | |||
| 156 | 156 | ||
| 157 | extern void omap2xxx_voltagedomains_init(void); | 157 | extern void omap2xxx_voltagedomains_init(void); |
| 158 | extern void omap3xxx_voltagedomains_init(void); | 158 | extern void omap3xxx_voltagedomains_init(void); |
| 159 | extern void am33xx_voltagedomains_init(void); | ||
| 159 | extern void omap44xx_voltagedomains_init(void); | 160 | extern void omap44xx_voltagedomains_init(void); |
| 160 | 161 | ||
| 161 | struct voltagedomain *voltdm_lookup(const char *name); | 162 | struct voltagedomain *voltdm_lookup(const char *name); |
diff --git a/arch/arm/mach-omap2/voltagedomains33xx_data.c b/arch/arm/mach-omap2/voltagedomains33xx_data.c new file mode 100644 index 000000000000..965458dc0cb9 --- /dev/null +++ b/arch/arm/mach-omap2/voltagedomains33xx_data.c | |||
| @@ -0,0 +1,43 @@ | |||
| 1 | /* | ||
| 2 | * AM33XX voltage domain data | ||
| 3 | * | ||
| 4 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License as | ||
| 8 | * published by the Free Software Foundation version 2. | ||
| 9 | * | ||
| 10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
| 11 | * kind, whether express or implied; without even the implied warranty | ||
| 12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include <linux/kernel.h> | ||
| 17 | #include <linux/init.h> | ||
| 18 | |||
| 19 | #include "voltage.h" | ||
| 20 | |||
| 21 | static struct voltagedomain am33xx_voltdm_mpu = { | ||
| 22 | .name = "mpu", | ||
| 23 | }; | ||
| 24 | |||
| 25 | static struct voltagedomain am33xx_voltdm_core = { | ||
| 26 | .name = "core", | ||
| 27 | }; | ||
| 28 | |||
| 29 | static struct voltagedomain am33xx_voltdm_rtc = { | ||
| 30 | .name = "rtc", | ||
| 31 | }; | ||
| 32 | |||
| 33 | static struct voltagedomain *voltagedomains_am33xx[] __initdata = { | ||
| 34 | &am33xx_voltdm_mpu, | ||
| 35 | &am33xx_voltdm_core, | ||
| 36 | &am33xx_voltdm_rtc, | ||
| 37 | NULL, | ||
| 38 | }; | ||
| 39 | |||
| 40 | void __init am33xx_voltagedomains_init(void) | ||
| 41 | { | ||
| 42 | voltdm_init(voltagedomains_am33xx); | ||
| 43 | } | ||
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2440.c b/arch/arm/mach-s3c24xx/clock-s3c2440.c index 414364eb426c..cb2883d553b5 100644 --- a/arch/arm/mach-s3c24xx/clock-s3c2440.c +++ b/arch/arm/mach-s3c24xx/clock-s3c2440.c | |||
| @@ -106,7 +106,7 @@ static struct clk s3c2440_clk_cam_upll = { | |||
| 106 | static struct clk s3c2440_clk_ac97 = { | 106 | static struct clk s3c2440_clk_ac97 = { |
| 107 | .name = "ac97", | 107 | .name = "ac97", |
| 108 | .enable = s3c2410_clkcon_enable, | 108 | .enable = s3c2410_clkcon_enable, |
| 109 | .ctrlbit = S3C2440_CLKCON_CAMERA, | 109 | .ctrlbit = S3C2440_CLKCON_AC97, |
| 110 | }; | 110 | }; |
| 111 | 111 | ||
| 112 | static unsigned long s3c2440_fclk_n_getrate(struct clk *clk) | 112 | static unsigned long s3c2440_fclk_n_getrate(struct clk *clk) |
diff --git a/arch/arm/mach-s3c24xx/common-smdk.c b/arch/arm/mach-s3c24xx/common-smdk.c index 084604be6ad1..87e75a250d5e 100644 --- a/arch/arm/mach-s3c24xx/common-smdk.c +++ b/arch/arm/mach-s3c24xx/common-smdk.c | |||
| @@ -182,19 +182,21 @@ static struct platform_device __initdata *smdk_devs[] = { | |||
| 182 | &smdk_led7, | 182 | &smdk_led7, |
| 183 | }; | 183 | }; |
| 184 | 184 | ||
| 185 | static const struct gpio smdk_led_gpios[] = { | ||
| 186 | { S3C2410_GPF(4), GPIOF_OUT_INIT_HIGH, NULL }, | ||
| 187 | { S3C2410_GPF(5), GPIOF_OUT_INIT_HIGH, NULL }, | ||
| 188 | { S3C2410_GPF(6), GPIOF_OUT_INIT_HIGH, NULL }, | ||
| 189 | { S3C2410_GPF(7), GPIOF_OUT_INIT_HIGH, NULL }, | ||
| 190 | }; | ||
| 191 | |||
| 185 | void __init smdk_machine_init(void) | 192 | void __init smdk_machine_init(void) |
| 186 | { | 193 | { |
| 187 | /* Configure the LEDs (even if we have no LED support)*/ | 194 | /* Configure the LEDs (even if we have no LED support)*/ |
| 188 | 195 | ||
| 189 | s3c_gpio_cfgpin(S3C2410_GPF(4), S3C2410_GPIO_OUTPUT); | 196 | int ret = gpio_request_array(smdk_led_gpios, |
| 190 | s3c_gpio_cfgpin(S3C2410_GPF(5), S3C2410_GPIO_OUTPUT); | 197 | ARRAY_SIZE(smdk_led_gpios)); |
| 191 | s3c_gpio_cfgpin(S3C2410_GPF(6), S3C2410_GPIO_OUTPUT); | 198 | if (!WARN_ON(ret < 0)) |
| 192 | s3c_gpio_cfgpin(S3C2410_GPF(7), S3C2410_GPIO_OUTPUT); | 199 | gpio_free_array(smdk_led_gpios, ARRAY_SIZE(smdk_led_gpios)); |
| 193 | |||
| 194 | s3c2410_gpio_setpin(S3C2410_GPF(4), 1); | ||
| 195 | s3c2410_gpio_setpin(S3C2410_GPF(5), 1); | ||
| 196 | s3c2410_gpio_setpin(S3C2410_GPF(6), 1); | ||
| 197 | s3c2410_gpio_setpin(S3C2410_GPF(7), 1); | ||
| 198 | 200 | ||
| 199 | if (machine_is_smdk2443()) | 201 | if (machine_is_smdk2443()) |
| 200 | smdk_nand_info.twrph0 = 50; | 202 | smdk_nand_info.twrph0 = 50; |
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c index 56cdd34cce41..0c9e9a785ef6 100644 --- a/arch/arm/mach-s3c24xx/common.c +++ b/arch/arm/mach-s3c24xx/common.c | |||
| @@ -41,7 +41,6 @@ | |||
| 41 | #include <asm/mach/arch.h> | 41 | #include <asm/mach/arch.h> |
| 42 | #include <asm/mach/map.h> | 42 | #include <asm/mach/map.h> |
| 43 | 43 | ||
| 44 | #include <mach/regs-clock.h> | ||
| 45 | #include <mach/regs-gpio.h> | 44 | #include <mach/regs-gpio.h> |
| 46 | #include <plat/regs-serial.h> | 45 | #include <plat/regs-serial.h> |
| 47 | 46 | ||
diff --git a/arch/arm/mach-s3c24xx/include/mach/bast-pmu.h b/arch/arm/mach-s3c24xx/include/mach/bast-pmu.h deleted file mode 100644 index 4c38b39b741d..000000000000 --- a/arch/arm/mach-s3c24xx/include/mach/bast-pmu.h +++ /dev/null | |||
| @@ -1,40 +0,0 @@ | |||
| 1 | /* arch/arm/mach-s3c2410/include/mach/bast-pmu.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2003-2004 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * Vincent Sanders <vince@simtec.co.uk> | ||
| 6 | * | ||
| 7 | * Machine BAST - Power Management chip | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_BASTPMU_H | ||
| 15 | #define __ASM_ARCH_BASTPMU_H "08_OCT_2004" | ||
| 16 | |||
| 17 | #define BASTPMU_REG_IDENT (0x00) | ||
| 18 | #define BASTPMU_REG_VERSION (0x01) | ||
| 19 | #define BASTPMU_REG_DDCCTRL (0x02) | ||
| 20 | #define BASTPMU_REG_POWER (0x03) | ||
| 21 | #define BASTPMU_REG_RESET (0x04) | ||
| 22 | #define BASTPMU_REG_GWO (0x05) | ||
| 23 | #define BASTPMU_REG_WOL (0x06) | ||
| 24 | #define BASTPMU_REG_WOR (0x07) | ||
| 25 | #define BASTPMU_REG_UID (0x09) | ||
| 26 | |||
| 27 | #define BASTPMU_EEPROM (0xC0) | ||
| 28 | |||
| 29 | #define BASTPMU_EEP_UID (BASTPMU_EEPROM + 0) | ||
| 30 | #define BASTPMU_EEP_WOL (BASTPMU_EEPROM + 8) | ||
| 31 | #define BASTPMU_EEP_WOR (BASTPMU_EEPROM + 9) | ||
| 32 | |||
| 33 | #define BASTPMU_IDENT_0 0x53 | ||
| 34 | #define BASTPMU_IDENT_1 0x42 | ||
| 35 | #define BASTPMU_IDENT_2 0x50 | ||
| 36 | #define BASTPMU_IDENT_3 0x4d | ||
| 37 | |||
| 38 | #define BASTPMU_RESET_GUARD (0x55) | ||
| 39 | |||
| 40 | #endif /* __ASM_ARCH_BASTPMU_H */ | ||
diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h b/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h index 019ea86057f6..3890a05948fb 100644 --- a/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h +++ b/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h | |||
| @@ -93,26 +93,5 @@ enum s3c_gpio_number { | |||
| 93 | #define S3C2410_GPL(_nr) (S3C2410_GPIO_L_START + (_nr)) | 93 | #define S3C2410_GPL(_nr) (S3C2410_GPIO_L_START + (_nr)) |
| 94 | #define S3C2410_GPM(_nr) (S3C2410_GPIO_M_START + (_nr)) | 94 | #define S3C2410_GPM(_nr) (S3C2410_GPIO_M_START + (_nr)) |
| 95 | 95 | ||
| 96 | /* compatibility until drivers can be modified */ | ||
| 97 | |||
| 98 | #define S3C2410_GPA0 S3C2410_GPA(0) | ||
| 99 | #define S3C2410_GPA1 S3C2410_GPA(1) | ||
| 100 | #define S3C2410_GPA3 S3C2410_GPA(3) | ||
| 101 | #define S3C2410_GPA7 S3C2410_GPA(7) | ||
| 102 | |||
| 103 | #define S3C2410_GPE0 S3C2410_GPE(0) | ||
| 104 | #define S3C2410_GPE1 S3C2410_GPE(1) | ||
| 105 | #define S3C2410_GPE2 S3C2410_GPE(2) | ||
| 106 | #define S3C2410_GPE3 S3C2410_GPE(3) | ||
| 107 | #define S3C2410_GPE4 S3C2410_GPE(4) | ||
| 108 | #define S3C2410_GPE5 S3C2410_GPE(5) | ||
| 109 | #define S3C2410_GPE6 S3C2410_GPE(6) | ||
| 110 | #define S3C2410_GPE7 S3C2410_GPE(7) | ||
| 111 | #define S3C2410_GPE8 S3C2410_GPE(8) | ||
| 112 | #define S3C2410_GPE9 S3C2410_GPE(9) | ||
| 113 | #define S3C2410_GPE10 S3C2410_GPE(10) | ||
| 114 | |||
| 115 | #define S3C2410_GPH10 S3C2410_GPH(10) | ||
| 116 | |||
| 117 | #endif /* __MACH_GPIONRS_H */ | 96 | #endif /* __MACH_GPIONRS_H */ |
| 118 | 97 | ||
diff --git a/arch/arm/mach-s3c24xx/include/mach/gta02.h b/arch/arm/mach-s3c24xx/include/mach/gta02.h index 3a56a229cac6..217393482153 100644 --- a/arch/arm/mach-s3c24xx/include/mach/gta02.h +++ b/arch/arm/mach-s3c24xx/include/mach/gta02.h | |||
| @@ -3,82 +3,13 @@ | |||
| 3 | 3 | ||
| 4 | #include <mach/regs-gpio.h> | 4 | #include <mach/regs-gpio.h> |
| 5 | 5 | ||
| 6 | /* Different hardware revisions, passed in ATAG_REVISION by u-boot */ | ||
| 7 | #define GTA02v1_SYSTEM_REV 0x00000310 | ||
| 8 | #define GTA02v2_SYSTEM_REV 0x00000320 | ||
| 9 | #define GTA02v3_SYSTEM_REV 0x00000330 | ||
| 10 | #define GTA02v4_SYSTEM_REV 0x00000340 | ||
| 11 | #define GTA02v5_SYSTEM_REV 0x00000350 | ||
| 12 | /* since A7 is basically same as A6, we use A6 PCB ID */ | ||
| 13 | #define GTA02v6_SYSTEM_REV 0x00000360 | ||
| 14 | |||
| 15 | #define GTA02_GPIO_n3DL_GSM S3C2410_GPA(13) /* v1 + v2 + v3 only */ | ||
| 16 | |||
| 17 | #define GTA02_GPIO_PWR_LED1 S3C2410_GPB(0) | ||
| 18 | #define GTA02_GPIO_PWR_LED2 S3C2410_GPB(1) | ||
| 19 | #define GTA02_GPIO_AUX_LED S3C2410_GPB(2) | 6 | #define GTA02_GPIO_AUX_LED S3C2410_GPB(2) |
| 20 | #define GTA02_GPIO_VIBRATOR_ON S3C2410_GPB(3) | ||
| 21 | #define GTA02_GPIO_MODEM_RST S3C2410_GPB(5) | ||
| 22 | #define GTA02_GPIO_BT_EN S3C2410_GPB(6) | ||
| 23 | #define GTA02_GPIO_MODEM_ON S3C2410_GPB(7) | ||
| 24 | #define GTA02_GPIO_EXTINT8 S3C2410_GPB(8) | ||
| 25 | #define GTA02_GPIO_USB_PULLUP S3C2410_GPB(9) | 7 | #define GTA02_GPIO_USB_PULLUP S3C2410_GPB(9) |
| 26 | |||
| 27 | #define GTA02_GPIO_PIO5 S3C2410_GPC(5) /* v3 + v4 only */ | ||
| 28 | |||
| 29 | #define GTA02v3_GPIO_nG1_CS S3C2410_GPD(12) /* v3 + v4 only */ | ||
| 30 | #define GTA02v3_GPIO_nG2_CS S3C2410_GPD(13) /* v3 + v4 only */ | ||
| 31 | #define GTA02v5_GPIO_HDQ S3C2410_GPD(14) /* v5 + */ | ||
| 32 | |||
| 33 | #define GTA02_GPIO_nG1_INT S3C2410_GPF(0) | ||
| 34 | #define GTA02_GPIO_IO1 S3C2410_GPF(1) | ||
| 35 | #define GTA02_GPIO_PIO_2 S3C2410_GPF(2) /* v2 + v3 + v4 only */ | ||
| 36 | #define GTA02_GPIO_JACK_INSERT S3C2410_GPF(4) | ||
| 37 | #define GTA02_GPIO_WLAN_GPIO1 S3C2410_GPF(5) /* v2 + v3 + v4 only */ | ||
| 38 | #define GTA02_GPIO_AUX_KEY S3C2410_GPF(6) | 8 | #define GTA02_GPIO_AUX_KEY S3C2410_GPF(6) |
| 39 | #define GTA02_GPIO_HOLD_KEY S3C2410_GPF(7) | 9 | #define GTA02_GPIO_HOLD_KEY S3C2410_GPF(7) |
| 40 | |||
| 41 | #define GTA02_GPIO_3D_IRQ S3C2410_GPG(4) | ||
| 42 | #define GTA02v2_GPIO_nG2_INT S3C2410_GPG(8) /* v2 + v3 + v4 only */ | ||
| 43 | #define GTA02v3_GPIO_nUSB_OC S3C2410_GPG(9) /* v3 + v4 only */ | ||
| 44 | #define GTA02v3_GPIO_nUSB_FLT S3C2410_GPG(10) /* v3 + v4 only */ | ||
| 45 | #define GTA02v3_GPIO_nGSM_OC S3C2410_GPG(11) /* v3 + v4 only */ | ||
| 46 | |||
| 47 | #define GTA02_GPIO_AMP_SHUT S3C2410_GPJ(1) /* v2 + v3 + v4 only */ | 10 | #define GTA02_GPIO_AMP_SHUT S3C2410_GPJ(1) /* v2 + v3 + v4 only */ |
| 48 | #define GTA02v1_GPIO_WLAN_GPIO10 S3C2410_GPJ(2) | ||
| 49 | #define GTA02_GPIO_HP_IN S3C2410_GPJ(2) /* v2 + v3 + v4 only */ | 11 | #define GTA02_GPIO_HP_IN S3C2410_GPJ(2) /* v2 + v3 + v4 only */ |
| 50 | #define GTA02_GPIO_INT0 S3C2410_GPJ(3) /* v2 + v3 + v4 only */ | ||
| 51 | #define GTA02_GPIO_nGSM_EN S3C2410_GPJ(4) | ||
| 52 | #define GTA02_GPIO_3D_RESET S3C2410_GPJ(5) | ||
| 53 | #define GTA02_GPIO_nDL_GSM S3C2410_GPJ(6) /* v4 + v5 only */ | ||
| 54 | #define GTA02_GPIO_WLAN_GPIO0 S3C2410_GPJ(7) | ||
| 55 | #define GTA02v1_GPIO_BAT_ID S3C2410_GPJ(8) | ||
| 56 | #define GTA02_GPIO_KEEPACT S3C2410_GPJ(8) | ||
| 57 | #define GTA02v1_GPIO_HP_IN S3C2410_GPJ(10) | ||
| 58 | #define GTA02_CHIP_PWD S3C2410_GPJ(11) /* v2 + v3 + v4 only */ | ||
| 59 | #define GTA02_GPIO_nWLAN_RESET S3C2410_GPJ(12) /* v2 + v3 + v4 only */ | ||
| 60 | 12 | ||
| 61 | #define GTA02_IRQ_GSENSOR_1 IRQ_EINT0 | ||
| 62 | #define GTA02_IRQ_MODEM IRQ_EINT1 | ||
| 63 | #define GTA02_IRQ_PIO_2 IRQ_EINT2 /* v2 + v3 + v4 only */ | ||
| 64 | #define GTA02_IRQ_nJACK_INSERT IRQ_EINT4 | ||
| 65 | #define GTA02_IRQ_WLAN_GPIO1 IRQ_EINT5 | ||
| 66 | #define GTA02_IRQ_AUX IRQ_EINT6 | ||
| 67 | #define GTA02_IRQ_nHOLD IRQ_EINT7 | ||
| 68 | #define GTA02_IRQ_PCF50633 IRQ_EINT9 | 13 | #define GTA02_IRQ_PCF50633 IRQ_EINT9 |
| 69 | #define GTA02_IRQ_3D IRQ_EINT12 | ||
| 70 | #define GTA02_IRQ_GSENSOR_2 IRQ_EINT16 /* v2 + v3 + v4 only */ | ||
| 71 | #define GTA02v3_IRQ_nUSB_OC IRQ_EINT17 /* v3 + v4 only */ | ||
| 72 | #define GTA02v3_IRQ_nUSB_FLT IRQ_EINT18 /* v3 + v4 only */ | ||
| 73 | #define GTA02v3_IRQ_nGSM_OC IRQ_EINT19 /* v3 + v4 only */ | ||
| 74 | |||
| 75 | /* returns 00 000 on GTA02 A5 and earlier, A6 returns 01 001 */ | ||
| 76 | #define GTA02_PCB_ID1_0 S3C2410_GPC(13) | ||
| 77 | #define GTA02_PCB_ID1_1 S3C2410_GPC(15) | ||
| 78 | #define GTA02_PCB_ID1_2 S3C2410_GPD(0) | ||
| 79 | #define GTA02_PCB_ID2_0 S3C2410_GPD(3) | ||
| 80 | #define GTA02_PCB_ID2_1 S3C2410_GPD(4) | ||
| 81 | |||
| 82 | int gta02_get_pcb_revision(void); | ||
| 83 | 14 | ||
| 84 | #endif /* _GTA02_H */ | 15 | #endif /* _GTA02_H */ |
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h index cac1ad6b582c..a11a638bd599 100644 --- a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h +++ b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h | |||
| @@ -302,7 +302,7 @@ | |||
| 302 | /* S3C2410: | 302 | /* S3C2410: |
| 303 | * Port G consists of 8 GPIO/IRQ/Special function | 303 | * Port G consists of 8 GPIO/IRQ/Special function |
| 304 | * | 304 | * |
| 305 | * GPGCON has 2 bits for each of the input pins on port F | 305 | * GPGCON has 2 bits for each of the input pins on port G |
| 306 | * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func | 306 | * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func |
| 307 | * | 307 | * |
| 308 | * pull up works like all other ports. | 308 | * pull up works like all other ports. |
| @@ -366,7 +366,7 @@ | |||
| 366 | 366 | ||
| 367 | /* Port H consists of11 GPIO/serial/Misc pins | 367 | /* Port H consists of11 GPIO/serial/Misc pins |
| 368 | * | 368 | * |
| 369 | * GPGCON has 2 bits for each of the input pins on port F | 369 | * GPHCON has 2 bits for each of the input pins on port H |
| 370 | * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func | 370 | * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func |
| 371 | * | 371 | * |
| 372 | * pull up works like all other ports. | 372 | * pull up works like all other ports. |
| @@ -427,6 +427,19 @@ | |||
| 427 | * for the 2412/2413 from the 2410/2440/2442 | 427 | * for the 2412/2413 from the 2410/2440/2442 |
| 428 | */ | 428 | */ |
| 429 | 429 | ||
| 430 | /* | ||
| 431 | * Port J consists of 13 GPIO/Camera pins. GPJCON has 2 bits | ||
| 432 | * for each of the pins on port J. | ||
| 433 | * 00 - input, 01 output, 10 - camera | ||
| 434 | * | ||
| 435 | * Pull up works like all other ports. | ||
| 436 | */ | ||
| 437 | |||
| 438 | #define S3C2413_GPJCON S3C2410_GPIOREG(0x80) | ||
| 439 | #define S3C2413_GPJDAT S3C2410_GPIOREG(0x84) | ||
| 440 | #define S3C2413_GPJUP S3C2410_GPIOREG(0x88) | ||
| 441 | #define S3C2413_GPJSLPCON S3C2410_GPIOREG(0x8C) | ||
| 442 | |||
| 430 | /* S3C2443 and above */ | 443 | /* S3C2443 and above */ |
| 431 | #define S3C2440_GPJCON S3C2410_GPIOREG(0xD0) | 444 | #define S3C2440_GPJCON S3C2410_GPIOREG(0xD0) |
| 432 | #define S3C2440_GPJDAT S3C2410_GPIOREG(0xD4) | 445 | #define S3C2440_GPJDAT S3C2410_GPIOREG(0xD4) |
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-gpioj.h b/arch/arm/mach-s3c24xx/include/mach/regs-gpioj.h deleted file mode 100644 index 19575e061114..000000000000 --- a/arch/arm/mach-s3c24xx/include/mach/regs-gpioj.h +++ /dev/null | |||
| @@ -1,70 +0,0 @@ | |||
| 1 | /* arch/arm/mach-s3c2410/include/mach/regs-gpioj.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> | ||
| 4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * S3C2440 GPIO J register definitions | ||
| 11 | */ | ||
| 12 | |||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_REGS_GPIOJ_H | ||
| 15 | #define __ASM_ARCH_REGS_GPIOJ_H "gpioj" | ||
| 16 | |||
| 17 | /* Port J consists of 13 GPIO/Camera pins | ||
| 18 | * | ||
| 19 | * GPJCON has 2 bits for each of the input pins on port F | ||
| 20 | * 00 = 0 input, 1 output, 2 Camera | ||
| 21 | * | ||
| 22 | * pull up works like all other ports. | ||
| 23 | */ | ||
| 24 | |||
| 25 | #define S3C2413_GPJCON S3C2410_GPIOREG(0x80) | ||
| 26 | #define S3C2413_GPJDAT S3C2410_GPIOREG(0x84) | ||
| 27 | #define S3C2413_GPJUP S3C2410_GPIOREG(0x88) | ||
| 28 | #define S3C2413_GPJSLPCON S3C2410_GPIOREG(0x8C) | ||
| 29 | |||
| 30 | #define S3C2440_GPJ0_OUTP (0x01 << 0) | ||
| 31 | #define S3C2440_GPJ0_CAMDATA0 (0x02 << 0) | ||
| 32 | |||
| 33 | #define S3C2440_GPJ1_OUTP (0x01 << 2) | ||
| 34 | #define S3C2440_GPJ1_CAMDATA1 (0x02 << 2) | ||
| 35 | |||
| 36 | #define S3C2440_GPJ2_OUTP (0x01 << 4) | ||
| 37 | #define S3C2440_GPJ2_CAMDATA2 (0x02 << 4) | ||
| 38 | |||
| 39 | #define S3C2440_GPJ3_OUTP (0x01 << 6) | ||
| 40 | #define S3C2440_GPJ3_CAMDATA3 (0x02 << 6) | ||
| 41 | |||
| 42 | #define S3C2440_GPJ4_OUTP (0x01 << 8) | ||
| 43 | #define S3C2440_GPJ4_CAMDATA4 (0x02 << 8) | ||
| 44 | |||
| 45 | #define S3C2440_GPJ5_OUTP (0x01 << 10) | ||
| 46 | #define S3C2440_GPJ5_CAMDATA5 (0x02 << 10) | ||
| 47 | |||
| 48 | #define S3C2440_GPJ6_OUTP (0x01 << 12) | ||
| 49 | #define S3C2440_GPJ6_CAMDATA6 (0x02 << 12) | ||
| 50 | |||
| 51 | #define S3C2440_GPJ7_OUTP (0x01 << 14) | ||
| 52 | #define S3C2440_GPJ7_CAMDATA7 (0x02 << 14) | ||
| 53 | |||
| 54 | #define S3C2440_GPJ8_OUTP (0x01 << 16) | ||
| 55 | #define S3C2440_GPJ8_CAMPCLK (0x02 << 16) | ||
| 56 | |||
| 57 | #define S3C2440_GPJ9_OUTP (0x01 << 18) | ||
| 58 | #define S3C2440_GPJ9_CAMVSYNC (0x02 << 18) | ||
| 59 | |||
| 60 | #define S3C2440_GPJ10_OUTP (0x01 << 20) | ||
| 61 | #define S3C2440_GPJ10_CAMHREF (0x02 << 20) | ||
| 62 | |||
| 63 | #define S3C2440_GPJ11_OUTP (0x01 << 22) | ||
| 64 | #define S3C2440_GPJ11_CAMCLKOUT (0x02 << 22) | ||
| 65 | |||
| 66 | #define S3C2440_GPJ12_OUTP (0x01 << 24) | ||
| 67 | #define S3C2440_GPJ12_CAMRESET (0x02 << 24) | ||
| 68 | |||
| 69 | #endif /* __ASM_ARCH_REGS_GPIOJ_H */ | ||
| 70 | |||
diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c index 0f29f64a3eeb..92e1f93a6bca 100644 --- a/arch/arm/mach-s3c24xx/mach-gta02.c +++ b/arch/arm/mach-s3c24xx/mach-gta02.c | |||
| @@ -71,7 +71,6 @@ | |||
| 71 | 71 | ||
| 72 | #include <mach/regs-irq.h> | 72 | #include <mach/regs-irq.h> |
| 73 | #include <mach/regs-gpio.h> | 73 | #include <mach/regs-gpio.h> |
| 74 | #include <mach/regs-gpioj.h> | ||
| 75 | #include <mach/fb.h> | 74 | #include <mach/fb.h> |
| 76 | 75 | ||
| 77 | #include <plat/usb-control.h> | 76 | #include <plat/usb-control.h> |
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c index f092b188ab70..bd6d2525debe 100644 --- a/arch/arm/mach-s3c24xx/mach-mini2440.c +++ b/arch/arm/mach-s3c24xx/mach-mini2440.c | |||
| @@ -634,8 +634,8 @@ static void __init mini2440_init(void) | |||
| 634 | s3c_gpio_cfgpin(S3C2410_GPC(0), S3C2410_GPC0_LEND); | 634 | s3c_gpio_cfgpin(S3C2410_GPC(0), S3C2410_GPC0_LEND); |
| 635 | 635 | ||
| 636 | /* Turn the backlight early on */ | 636 | /* Turn the backlight early on */ |
| 637 | WARN_ON(gpio_request(S3C2410_GPG(4), "backlight")); | 637 | WARN_ON(gpio_request_one(S3C2410_GPG(4), GPIOF_OUT_INIT_HIGH, NULL)); |
| 638 | gpio_direction_output(S3C2410_GPG(4), 1); | 638 | gpio_free(S3C2410_GPG(4)); |
| 639 | 639 | ||
| 640 | /* remove pullup on optional PWM backlight -- unused on 3.5 and 7"s */ | 640 | /* remove pullup on optional PWM backlight -- unused on 3.5 and 7"s */ |
| 641 | s3c_gpio_setpull(S3C2410_GPB(1), S3C_GPIO_PULL_UP); | 641 | s3c_gpio_setpull(S3C2410_GPB(1), S3C_GPIO_PULL_UP); |
diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c index b868dddcb836..678bbca2b5e5 100644 --- a/arch/arm/mach-s3c24xx/mach-qt2410.c +++ b/arch/arm/mach-s3c24xx/mach-qt2410.c | |||
| @@ -47,7 +47,6 @@ | |||
| 47 | #include <asm/irq.h> | 47 | #include <asm/irq.h> |
| 48 | #include <asm/mach-types.h> | 48 | #include <asm/mach-types.h> |
| 49 | 49 | ||
| 50 | #include <mach/regs-gpio.h> | ||
| 51 | #include <mach/leds-gpio.h> | 50 | #include <mach/leds-gpio.h> |
| 52 | #include <mach/regs-lcd.h> | 51 | #include <mach/regs-lcd.h> |
| 53 | #include <plat/regs-serial.h> | 52 | #include <plat/regs-serial.h> |
| @@ -325,8 +324,9 @@ static void __init qt2410_machine_init(void) | |||
| 325 | } | 324 | } |
| 326 | s3c24xx_fb_set_platdata(&qt2410_fb_info); | 325 | s3c24xx_fb_set_platdata(&qt2410_fb_info); |
| 327 | 326 | ||
| 328 | s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPIO_OUTPUT); | 327 | /* set initial state of the LED GPIO */ |
| 329 | s3c2410_gpio_setpin(S3C2410_GPB(0), 1); | 328 | WARN_ON(gpio_request_one(S3C2410_GPB(0), GPIOF_OUT_INIT_HIGH, NULL)); |
| 329 | gpio_free(S3C2410_GPB(0)); | ||
| 330 | 330 | ||
| 331 | s3c24xx_udc_set_platdata(&qt2410_udc_cfg); | 331 | s3c24xx_udc_set_platdata(&qt2410_udc_cfg); |
| 332 | s3c_i2c0_set_platdata(NULL); | 332 | s3c_i2c0_set_platdata(NULL); |
diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c index a6762aae4727..7ee73f27f207 100644 --- a/arch/arm/mach-s3c24xx/mach-rx1950.c +++ b/arch/arm/mach-s3c24xx/mach-rx1950.c | |||
| @@ -42,7 +42,6 @@ | |||
| 42 | #include <asm/mach-types.h> | 42 | #include <asm/mach-types.h> |
| 43 | 43 | ||
| 44 | #include <mach/regs-gpio.h> | 44 | #include <mach/regs-gpio.h> |
| 45 | #include <mach/regs-gpioj.h> | ||
| 46 | #include <mach/regs-lcd.h> | 45 | #include <mach/regs-lcd.h> |
| 47 | #include <mach/h1940.h> | 46 | #include <mach/h1940.h> |
| 48 | #include <mach/fb.h> | 47 | #include <mach/fb.h> |
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2410.c b/arch/arm/mach-s3c24xx/pm-s3c2410.c index 03f706dd6009..949ae05e07c5 100644 --- a/arch/arm/mach-s3c24xx/pm-s3c2410.c +++ b/arch/arm/mach-s3c24xx/pm-s3c2410.c | |||
| @@ -77,8 +77,10 @@ static void s3c2410_pm_prepare(void) | |||
| 77 | __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM)); | 77 | __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM)); |
| 78 | } | 78 | } |
| 79 | 79 | ||
| 80 | if ( machine_is_aml_m5900() ) | 80 | if (machine_is_aml_m5900()) { |
| 81 | s3c2410_gpio_setpin(S3C2410_GPF(2), 1); | 81 | gpio_request_one(S3C2410_GPF(2), GPIOF_OUT_INIT_HIGH, NULL); |
| 82 | gpio_free(S3C2410_GPF(2)); | ||
| 83 | } | ||
| 82 | 84 | ||
| 83 | if (machine_is_rx1950()) { | 85 | if (machine_is_rx1950()) { |
| 84 | /* According to S3C2442 user's manual, page 7-17, | 86 | /* According to S3C2442 user's manual, page 7-17, |
| @@ -103,8 +105,10 @@ static void s3c2410_pm_resume(void) | |||
| 103 | tmp &= S3C2410_GSTATUS2_OFFRESET; | 105 | tmp &= S3C2410_GSTATUS2_OFFRESET; |
| 104 | __raw_writel(tmp, S3C2410_GSTATUS2); | 106 | __raw_writel(tmp, S3C2410_GSTATUS2); |
| 105 | 107 | ||
| 106 | if ( machine_is_aml_m5900() ) | 108 | if (machine_is_aml_m5900()) { |
| 107 | s3c2410_gpio_setpin(S3C2410_GPF(2), 0); | 109 | gpio_request_one(S3C2410_GPF(2), GPIOF_OUT_INIT_LOW, NULL); |
| 110 | gpio_free(S3C2410_GPF(2)); | ||
| 111 | } | ||
| 108 | } | 112 | } |
| 109 | 113 | ||
| 110 | struct syscore_ops s3c2410_pm_syscore_ops = { | 114 | struct syscore_ops s3c2410_pm_syscore_ops = { |
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2412.c b/arch/arm/mach-s3c24xx/pm-s3c2412.c index d04588506ec4..c60f67a75aff 100644 --- a/arch/arm/mach-s3c24xx/pm-s3c2412.c +++ b/arch/arm/mach-s3c24xx/pm-s3c2412.c | |||
| @@ -26,7 +26,6 @@ | |||
| 26 | #include <asm/irq.h> | 26 | #include <asm/irq.h> |
| 27 | 27 | ||
| 28 | #include <mach/regs-power.h> | 28 | #include <mach/regs-power.h> |
| 29 | #include <mach/regs-gpioj.h> | ||
| 30 | #include <mach/regs-gpio.h> | 29 | #include <mach/regs-gpio.h> |
| 31 | #include <mach/regs-dsc.h> | 30 | #include <mach/regs-dsc.h> |
| 32 | 31 | ||
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c index d4bc7f960bbb..6c5f4031ff0c 100644 --- a/arch/arm/mach-s3c24xx/s3c2412.c +++ b/arch/arm/mach-s3c24xx/s3c2412.c | |||
| @@ -39,7 +39,6 @@ | |||
| 39 | #include <plat/regs-serial.h> | 39 | #include <plat/regs-serial.h> |
| 40 | #include <mach/regs-power.h> | 40 | #include <mach/regs-power.h> |
| 41 | #include <mach/regs-gpio.h> | 41 | #include <mach/regs-gpio.h> |
| 42 | #include <mach/regs-gpioj.h> | ||
| 43 | #include <mach/regs-dsc.h> | 42 | #include <mach/regs-dsc.h> |
| 44 | #include <plat/regs-spi.h> | 43 | #include <plat/regs-spi.h> |
| 45 | #include <mach/regs-s3c2412.h> | 44 | #include <mach/regs-s3c2412.h> |
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c index 6f74118f60c6..b0b60a1154d6 100644 --- a/arch/arm/mach-s3c24xx/s3c244x.c +++ b/arch/arm/mach-s3c24xx/s3c244x.c | |||
| @@ -36,7 +36,6 @@ | |||
| 36 | #include <mach/regs-clock.h> | 36 | #include <mach/regs-clock.h> |
| 37 | #include <plat/regs-serial.h> | 37 | #include <plat/regs-serial.h> |
| 38 | #include <mach/regs-gpio.h> | 38 | #include <mach/regs-gpio.h> |
| 39 | #include <mach/regs-gpioj.h> | ||
| 40 | #include <mach/regs-dsc.h> | 39 | #include <mach/regs-dsc.h> |
| 41 | 40 | ||
| 42 | #include <plat/s3c2410.h> | 41 | #include <plat/s3c2410.h> |
diff --git a/arch/arm/mach-s3c24xx/setup-ts.c b/arch/arm/mach-s3c24xx/setup-ts.c index ed2638663675..4e11affce3a8 100644 --- a/arch/arm/mach-s3c24xx/setup-ts.c +++ b/arch/arm/mach-s3c24xx/setup-ts.c | |||
| @@ -16,7 +16,6 @@ | |||
| 16 | struct platform_device; /* don't need the contents */ | 16 | struct platform_device; /* don't need the contents */ |
| 17 | 17 | ||
| 18 | #include <mach/hardware.h> | 18 | #include <mach/hardware.h> |
| 19 | #include <mach/regs-gpio.h> | ||
| 20 | 19 | ||
| 21 | /** | 20 | /** |
| 22 | * s3c24xx_ts_cfg_gpio - configure gpio for s3c2410 systems | 21 | * s3c24xx_ts_cfg_gpio - configure gpio for s3c2410 systems |
| @@ -27,8 +26,5 @@ struct platform_device; /* don't need the contents */ | |||
| 27 | */ | 26 | */ |
| 28 | void s3c24xx_ts_cfg_gpio(struct platform_device *dev) | 27 | void s3c24xx_ts_cfg_gpio(struct platform_device *dev) |
| 29 | { | 28 | { |
| 30 | s3c2410_gpio_cfgpin(S3C2410_GPG(12), S3C2410_GPG12_XMON); | 29 | s3c_gpio_cfgpin_range(S3C2410_GPG(12), 4, S3C_GPIO_SFN(3)); |
| 31 | s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPG13_nXPON); | ||
| 32 | s3c2410_gpio_cfgpin(S3C2410_GPG(14), S3C2410_GPG14_YMON); | ||
| 33 | s3c2410_gpio_cfgpin(S3C2410_GPG(15), S3C2410_GPG15_nYPON); | ||
| 34 | } | 30 | } |
diff --git a/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h b/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h deleted file mode 100644 index 9d0c43b4b687..000000000000 --- a/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h +++ /dev/null | |||
| @@ -1,18 +0,0 @@ | |||
| 1 | /* linux/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2009 Samsung Electronics Ltd. | ||
| 4 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __S3C64XX_PLAT_SPI_CLKS_H | ||
| 12 | #define __S3C64XX_PLAT_SPI_CLKS_H __FILE__ | ||
| 13 | |||
| 14 | #define S3C64XX_SPI_SRCCLK_PCLK 0 | ||
| 15 | #define S3C64XX_SPI_SRCCLK_SPIBUS 1 | ||
| 16 | #define S3C64XX_SPI_SRCCLK_48M 2 | ||
| 17 | |||
| 18 | #endif /* __S3C64XX_PLAT_SPI_CLKS_H */ | ||
diff --git a/arch/arm/mach-s5p64x0/dma.c b/arch/arm/mach-s5p64x0/dma.c index 2ee5dc069b37..9c4ce085f585 100644 --- a/arch/arm/mach-s5p64x0/dma.c +++ b/arch/arm/mach-s5p64x0/dma.c | |||
| @@ -36,8 +36,6 @@ | |||
| 36 | #include <plat/devs.h> | 36 | #include <plat/devs.h> |
| 37 | #include <plat/irqs.h> | 37 | #include <plat/irqs.h> |
| 38 | 38 | ||
| 39 | static u64 dma_dmamask = DMA_BIT_MASK(32); | ||
| 40 | |||
| 41 | static u8 s5p6440_pdma_peri[] = { | 39 | static u8 s5p6440_pdma_peri[] = { |
| 42 | DMACH_UART0_RX, | 40 | DMACH_UART0_RX, |
| 43 | DMACH_UART0_TX, | 41 | DMACH_UART0_TX, |
diff --git a/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h b/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h deleted file mode 100644 index 170a20a9643a..000000000000 --- a/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h +++ /dev/null | |||
| @@ -1,20 +0,0 @@ | |||
| 1 | /* linux/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com | ||
| 5 | * | ||
| 6 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
| 7 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_SPI_CLKS_H | ||
| 15 | #define __ASM_ARCH_SPI_CLKS_H __FILE__ | ||
| 16 | |||
| 17 | #define S5P64X0_SPI_SRCCLK_PCLK 0 | ||
| 18 | #define S5P64X0_SPI_SRCCLK_SCLK 1 | ||
| 19 | |||
| 20 | #endif /* __ASM_ARCH_SPI_CLKS_H */ | ||
diff --git a/arch/arm/mach-s5pc100/dma.c b/arch/arm/mach-s5pc100/dma.c index afd8db2d5991..b1418409709e 100644 --- a/arch/arm/mach-s5pc100/dma.c +++ b/arch/arm/mach-s5pc100/dma.c | |||
| @@ -33,8 +33,6 @@ | |||
| 33 | #include <mach/irqs.h> | 33 | #include <mach/irqs.h> |
| 34 | #include <mach/dma.h> | 34 | #include <mach/dma.h> |
| 35 | 35 | ||
| 36 | static u64 dma_dmamask = DMA_BIT_MASK(32); | ||
| 37 | |||
| 38 | static u8 pdma0_peri[] = { | 36 | static u8 pdma0_peri[] = { |
| 39 | DMACH_UART0_RX, | 37 | DMACH_UART0_RX, |
| 40 | DMACH_UART0_TX, | 38 | DMACH_UART0_TX, |
diff --git a/arch/arm/mach-s5pc100/include/mach/spi-clocks.h b/arch/arm/mach-s5pc100/include/mach/spi-clocks.h deleted file mode 100644 index 65e426370bb2..000000000000 --- a/arch/arm/mach-s5pc100/include/mach/spi-clocks.h +++ /dev/null | |||
| @@ -1,18 +0,0 @@ | |||
| 1 | /* linux/arch/arm/mach-s5pc100/include/mach/spi-clocks.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
| 4 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __S5PC100_PLAT_SPI_CLKS_H | ||
| 12 | #define __S5PC100_PLAT_SPI_CLKS_H __FILE__ | ||
| 13 | |||
| 14 | #define S5PC100_SPI_SRCCLK_PCLK 0 | ||
| 15 | #define S5PC100_SPI_SRCCLK_48M 1 | ||
| 16 | #define S5PC100_SPI_SRCCLK_SPIBUS 2 | ||
| 17 | |||
| 18 | #endif /* __S5PC100_PLAT_SPI_CLKS_H */ | ||
diff --git a/arch/arm/mach-s5pv210/include/mach/spi-clocks.h b/arch/arm/mach-s5pv210/include/mach/spi-clocks.h deleted file mode 100644 index 02acded5f73d..000000000000 --- a/arch/arm/mach-s5pv210/include/mach/spi-clocks.h +++ /dev/null | |||
| @@ -1,17 +0,0 @@ | |||
| 1 | /* linux/arch/arm/mach-s5pv210/include/mach/spi-clocks.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
| 4 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __S5PV210_PLAT_SPI_CLKS_H | ||
| 12 | #define __S5PV210_PLAT_SPI_CLKS_H __FILE__ | ||
| 13 | |||
| 14 | #define S5PV210_SPI_SRCCLK_PCLK 0 | ||
| 15 | #define S5PV210_SPI_SRCCLK_SCLK 1 | ||
| 16 | |||
| 17 | #endif /* __S5PV210_PLAT_SPI_CLKS_H */ | ||
diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c index e859fcdb3d58..fde0d23121dc 100644 --- a/arch/arm/mach-shmobile/platsmp.c +++ b/arch/arm/mach-shmobile/platsmp.c | |||
| @@ -22,8 +22,13 @@ | |||
| 22 | #include <mach/common.h> | 22 | #include <mach/common.h> |
| 23 | #include <mach/emev2.h> | 23 | #include <mach/emev2.h> |
| 24 | 24 | ||
| 25 | #ifdef CONFIG_ARCH_SH73A0 | ||
| 25 | #define is_sh73a0() (machine_is_ag5evm() || machine_is_kota2() || \ | 26 | #define is_sh73a0() (machine_is_ag5evm() || machine_is_kota2() || \ |
| 26 | of_machine_is_compatible("renesas,sh73a0")) | 27 | of_machine_is_compatible("renesas,sh73a0")) |
| 28 | #else | ||
| 29 | #define is_sh73a0() (0) | ||
| 30 | #endif | ||
| 31 | |||
| 27 | #define is_r8a7779() machine_is_marzen() | 32 | #define is_r8a7779() machine_is_marzen() |
| 28 | 33 | ||
| 29 | #ifdef CONFIG_ARCH_EMEV2 | 34 | #ifdef CONFIG_ARCH_EMEV2 |
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c index 0f41bd1c47c3..66db5f13af84 100644 --- a/arch/arm/mach-spear3xx/spear3xx.c +++ b/arch/arm/mach-spear3xx/spear3xx.c | |||
| @@ -87,7 +87,7 @@ void __init spear3xx_map_io(void) | |||
| 87 | 87 | ||
| 88 | static void __init spear3xx_timer_init(void) | 88 | static void __init spear3xx_timer_init(void) |
| 89 | { | 89 | { |
| 90 | char pclk_name[] = "pll3_48m_clk"; | 90 | char pclk_name[] = "pll3_clk"; |
| 91 | struct clk *gpt_clk, *pclk; | 91 | struct clk *gpt_clk, *pclk; |
| 92 | 92 | ||
| 93 | spear3xx_clk_init(); | 93 | spear3xx_clk_init(); |
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c index 2e2e3596583e..9af67d003c62 100644 --- a/arch/arm/mach-spear6xx/spear6xx.c +++ b/arch/arm/mach-spear6xx/spear6xx.c | |||
| @@ -423,7 +423,7 @@ void __init spear6xx_map_io(void) | |||
| 423 | 423 | ||
| 424 | static void __init spear6xx_timer_init(void) | 424 | static void __init spear6xx_timer_init(void) |
| 425 | { | 425 | { |
| 426 | char pclk_name[] = "pll3_48m_clk"; | 426 | char pclk_name[] = "pll3_clk"; |
| 427 | struct clk *gpt_clk, *pclk; | 427 | struct clk *gpt_clk, *pclk; |
| 428 | 428 | ||
| 429 | spear6xx_clk_init(); | 429 | spear6xx_clk_init(); |
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 2eb4445ddb14..90aae34245cd 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile | |||
| @@ -8,9 +8,10 @@ obj-y += timer.o | |||
| 8 | obj-y += fuse.o | 8 | obj-y += fuse.o |
| 9 | obj-y += pmc.o | 9 | obj-y += pmc.o |
| 10 | obj-y += flowctrl.o | 10 | obj-y += flowctrl.o |
| 11 | obj-y += powergate.o | ||
| 12 | obj-y += apbio.o | ||
| 11 | obj-$(CONFIG_CPU_IDLE) += cpuidle.o | 13 | obj-$(CONFIG_CPU_IDLE) += cpuidle.o |
| 12 | obj-$(CONFIG_CPU_IDLE) += sleep.o | 14 | obj-$(CONFIG_CPU_IDLE) += sleep.o |
| 13 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o | ||
| 14 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o | 15 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o |
| 15 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o | 16 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o |
| 16 | obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o | 17 | obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o |
| @@ -18,7 +19,7 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o | |||
| 18 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o | 19 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o |
| 19 | obj-$(CONFIG_SMP) += reset.o | 20 | obj-$(CONFIG_SMP) += reset.o |
| 20 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o | 21 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o |
| 21 | obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o apbio.o | 22 | obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o |
| 22 | obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o | 23 | obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o |
| 23 | obj-$(CONFIG_TEGRA_PCI) += pcie.o | 24 | obj-$(CONFIG_TEGRA_PCI) += pcie.o |
| 24 | obj-$(CONFIG_USB_SUPPORT) += usb_phy.o | 25 | obj-$(CONFIG_USB_SUPPORT) += usb_phy.o |
diff --git a/arch/arm/mach-tegra/apbio.c b/arch/arm/mach-tegra/apbio.c index e75451e517bd..dc0fe389be56 100644 --- a/arch/arm/mach-tegra/apbio.c +++ b/arch/arm/mach-tegra/apbio.c | |||
| @@ -15,6 +15,9 @@ | |||
| 15 | 15 | ||
| 16 | #include <linux/kernel.h> | 16 | #include <linux/kernel.h> |
| 17 | #include <linux/io.h> | 17 | #include <linux/io.h> |
| 18 | #include <mach/iomap.h> | ||
| 19 | #include <linux/of.h> | ||
| 20 | #include <linux/dmaengine.h> | ||
| 18 | #include <linux/dma-mapping.h> | 21 | #include <linux/dma-mapping.h> |
| 19 | #include <linux/spinlock.h> | 22 | #include <linux/spinlock.h> |
| 20 | #include <linux/completion.h> | 23 | #include <linux/completion.h> |
| @@ -22,17 +25,21 @@ | |||
| 22 | #include <linux/mutex.h> | 25 | #include <linux/mutex.h> |
| 23 | 26 | ||
| 24 | #include <mach/dma.h> | 27 | #include <mach/dma.h> |
| 25 | #include <mach/iomap.h> | ||
| 26 | 28 | ||
| 27 | #include "apbio.h" | 29 | #include "apbio.h" |
| 28 | 30 | ||
| 31 | #if defined(CONFIG_TEGRA_SYSTEM_DMA) || defined(CONFIG_TEGRA20_APB_DMA) | ||
| 29 | static DEFINE_MUTEX(tegra_apb_dma_lock); | 32 | static DEFINE_MUTEX(tegra_apb_dma_lock); |
| 30 | |||
| 31 | static struct tegra_dma_channel *tegra_apb_dma; | ||
| 32 | static u32 *tegra_apb_bb; | 33 | static u32 *tegra_apb_bb; |
| 33 | static dma_addr_t tegra_apb_bb_phys; | 34 | static dma_addr_t tegra_apb_bb_phys; |
| 34 | static DECLARE_COMPLETION(tegra_apb_wait); | 35 | static DECLARE_COMPLETION(tegra_apb_wait); |
| 35 | 36 | ||
| 37 | static u32 tegra_apb_readl_direct(unsigned long offset); | ||
| 38 | static void tegra_apb_writel_direct(u32 value, unsigned long offset); | ||
| 39 | |||
| 40 | #if defined(CONFIG_TEGRA_SYSTEM_DMA) | ||
| 41 | static struct tegra_dma_channel *tegra_apb_dma; | ||
| 42 | |||
| 36 | bool tegra_apb_init(void) | 43 | bool tegra_apb_init(void) |
| 37 | { | 44 | { |
| 38 | struct tegra_dma_channel *ch; | 45 | struct tegra_dma_channel *ch; |
| @@ -72,13 +79,13 @@ static void apb_dma_complete(struct tegra_dma_req *req) | |||
| 72 | complete(&tegra_apb_wait); | 79 | complete(&tegra_apb_wait); |
| 73 | } | 80 | } |
| 74 | 81 | ||
| 75 | u32 tegra_apb_readl(unsigned long offset) | 82 | static u32 tegra_apb_readl_using_dma(unsigned long offset) |
| 76 | { | 83 | { |
| 77 | struct tegra_dma_req req; | 84 | struct tegra_dma_req req; |
| 78 | int ret; | 85 | int ret; |
| 79 | 86 | ||
| 80 | if (!tegra_apb_dma && !tegra_apb_init()) | 87 | if (!tegra_apb_dma && !tegra_apb_init()) |
| 81 | return readl(IO_TO_VIRT(offset)); | 88 | return tegra_apb_readl_direct(offset); |
| 82 | 89 | ||
| 83 | mutex_lock(&tegra_apb_dma_lock); | 90 | mutex_lock(&tegra_apb_dma_lock); |
| 84 | req.complete = apb_dma_complete; | 91 | req.complete = apb_dma_complete; |
| @@ -108,13 +115,13 @@ u32 tegra_apb_readl(unsigned long offset) | |||
| 108 | return *((u32 *)tegra_apb_bb); | 115 | return *((u32 *)tegra_apb_bb); |
| 109 | } | 116 | } |
| 110 | 117 | ||
| 111 | void tegra_apb_writel(u32 value, unsigned long offset) | 118 | static void tegra_apb_writel_using_dma(u32 value, unsigned long offset) |
| 112 | { | 119 | { |
| 113 | struct tegra_dma_req req; | 120 | struct tegra_dma_req req; |
| 114 | int ret; | 121 | int ret; |
| 115 | 122 | ||
| 116 | if (!tegra_apb_dma && !tegra_apb_init()) { | 123 | if (!tegra_apb_dma && !tegra_apb_init()) { |
| 117 | writel(value, IO_TO_VIRT(offset)); | 124 | tegra_apb_writel_direct(value, offset); |
| 118 | return; | 125 | return; |
| 119 | } | 126 | } |
| 120 | 127 | ||
| @@ -143,3 +150,176 @@ void tegra_apb_writel(u32 value, unsigned long offset) | |||
| 143 | 150 | ||
| 144 | mutex_unlock(&tegra_apb_dma_lock); | 151 | mutex_unlock(&tegra_apb_dma_lock); |
| 145 | } | 152 | } |
| 153 | |||
| 154 | #else | ||
| 155 | static struct dma_chan *tegra_apb_dma_chan; | ||
| 156 | static struct dma_slave_config dma_sconfig; | ||
| 157 | |||
| 158 | bool tegra_apb_dma_init(void) | ||
| 159 | { | ||
| 160 | dma_cap_mask_t mask; | ||
| 161 | |||
| 162 | mutex_lock(&tegra_apb_dma_lock); | ||
| 163 | |||
| 164 | /* Check to see if we raced to setup */ | ||
| 165 | if (tegra_apb_dma_chan) | ||
| 166 | goto skip_init; | ||
| 167 | |||
| 168 | dma_cap_zero(mask); | ||
| 169 | dma_cap_set(DMA_SLAVE, mask); | ||
| 170 | tegra_apb_dma_chan = dma_request_channel(mask, NULL, NULL); | ||
| 171 | if (!tegra_apb_dma_chan) { | ||
| 172 | /* | ||
| 173 | * This is common until the device is probed, so don't | ||
| 174 | * shout about it. | ||
| 175 | */ | ||
| 176 | pr_debug("%s: can not allocate dma channel\n", __func__); | ||
| 177 | goto err_dma_alloc; | ||
| 178 | } | ||
| 179 | |||
| 180 | tegra_apb_bb = dma_alloc_coherent(NULL, sizeof(u32), | ||
| 181 | &tegra_apb_bb_phys, GFP_KERNEL); | ||
| 182 | if (!tegra_apb_bb) { | ||
| 183 | pr_err("%s: can not allocate bounce buffer\n", __func__); | ||
| 184 | goto err_buff_alloc; | ||
| 185 | } | ||
| 186 | |||
| 187 | dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
| 188 | dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
| 189 | dma_sconfig.slave_id = TEGRA_DMA_REQ_SEL_CNTR; | ||
| 190 | dma_sconfig.src_maxburst = 1; | ||
| 191 | dma_sconfig.dst_maxburst = 1; | ||
| 192 | |||
| 193 | skip_init: | ||
| 194 | mutex_unlock(&tegra_apb_dma_lock); | ||
| 195 | return true; | ||
| 196 | |||
| 197 | err_buff_alloc: | ||
| 198 | dma_release_channel(tegra_apb_dma_chan); | ||
| 199 | tegra_apb_dma_chan = NULL; | ||
| 200 | |||
| 201 | err_dma_alloc: | ||
| 202 | mutex_unlock(&tegra_apb_dma_lock); | ||
| 203 | return false; | ||
| 204 | } | ||
| 205 | |||
| 206 | static void apb_dma_complete(void *args) | ||
| 207 | { | ||
| 208 | complete(&tegra_apb_wait); | ||
| 209 | } | ||
| 210 | |||
| 211 | static int do_dma_transfer(unsigned long apb_add, | ||
| 212 | enum dma_transfer_direction dir) | ||
| 213 | { | ||
| 214 | struct dma_async_tx_descriptor *dma_desc; | ||
| 215 | int ret; | ||
| 216 | |||
| 217 | if (dir == DMA_DEV_TO_MEM) | ||
| 218 | dma_sconfig.src_addr = apb_add; | ||
| 219 | else | ||
| 220 | dma_sconfig.dst_addr = apb_add; | ||
| 221 | |||
| 222 | ret = dmaengine_slave_config(tegra_apb_dma_chan, &dma_sconfig); | ||
| 223 | if (ret) | ||
| 224 | return ret; | ||
| 225 | |||
| 226 | dma_desc = dmaengine_prep_slave_single(tegra_apb_dma_chan, | ||
| 227 | tegra_apb_bb_phys, sizeof(u32), dir, | ||
| 228 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | ||
| 229 | if (!dma_desc) | ||
| 230 | return -EINVAL; | ||
| 231 | |||
| 232 | dma_desc->callback = apb_dma_complete; | ||
| 233 | dma_desc->callback_param = NULL; | ||
| 234 | |||
| 235 | INIT_COMPLETION(tegra_apb_wait); | ||
| 236 | |||
| 237 | dmaengine_submit(dma_desc); | ||
| 238 | dma_async_issue_pending(tegra_apb_dma_chan); | ||
| 239 | ret = wait_for_completion_timeout(&tegra_apb_wait, | ||
| 240 | msecs_to_jiffies(50)); | ||
| 241 | |||
| 242 | if (WARN(ret == 0, "apb read dma timed out")) { | ||
| 243 | dmaengine_terminate_all(tegra_apb_dma_chan); | ||
| 244 | return -EFAULT; | ||
| 245 | } | ||
| 246 | return 0; | ||
| 247 | } | ||
| 248 | |||
| 249 | static u32 tegra_apb_readl_using_dma(unsigned long offset) | ||
| 250 | { | ||
| 251 | int ret; | ||
| 252 | |||
| 253 | if (!tegra_apb_dma_chan && !tegra_apb_dma_init()) | ||
| 254 | return tegra_apb_readl_direct(offset); | ||
| 255 | |||
| 256 | mutex_lock(&tegra_apb_dma_lock); | ||
| 257 | ret = do_dma_transfer(offset, DMA_DEV_TO_MEM); | ||
| 258 | if (ret < 0) { | ||
| 259 | pr_err("error in reading offset 0x%08lx using dma\n", offset); | ||
| 260 | *(u32 *)tegra_apb_bb = 0; | ||
| 261 | } | ||
| 262 | mutex_unlock(&tegra_apb_dma_lock); | ||
| 263 | return *((u32 *)tegra_apb_bb); | ||
| 264 | } | ||
| 265 | |||
| 266 | static void tegra_apb_writel_using_dma(u32 value, unsigned long offset) | ||
| 267 | { | ||
| 268 | int ret; | ||
| 269 | |||
| 270 | if (!tegra_apb_dma_chan && !tegra_apb_dma_init()) { | ||
| 271 | tegra_apb_writel_direct(value, offset); | ||
| 272 | return; | ||
| 273 | } | ||
| 274 | |||
| 275 | mutex_lock(&tegra_apb_dma_lock); | ||
| 276 | *((u32 *)tegra_apb_bb) = value; | ||
| 277 | ret = do_dma_transfer(offset, DMA_MEM_TO_DEV); | ||
| 278 | if (ret < 0) | ||
| 279 | pr_err("error in writing offset 0x%08lx using dma\n", offset); | ||
| 280 | mutex_unlock(&tegra_apb_dma_lock); | ||
| 281 | } | ||
| 282 | #endif | ||
| 283 | #else | ||
| 284 | #define tegra_apb_readl_using_dma tegra_apb_readl_direct | ||
| 285 | #define tegra_apb_writel_using_dma tegra_apb_writel_direct | ||
| 286 | #endif | ||
| 287 | |||
| 288 | typedef u32 (*apbio_read_fptr)(unsigned long offset); | ||
| 289 | typedef void (*apbio_write_fptr)(u32 value, unsigned long offset); | ||
| 290 | |||
| 291 | static apbio_read_fptr apbio_read; | ||
| 292 | static apbio_write_fptr apbio_write; | ||
| 293 | |||
| 294 | static u32 tegra_apb_readl_direct(unsigned long offset) | ||
| 295 | { | ||
| 296 | return readl(IO_TO_VIRT(offset)); | ||
| 297 | } | ||
| 298 | |||
| 299 | static void tegra_apb_writel_direct(u32 value, unsigned long offset) | ||
| 300 | { | ||
| 301 | writel(value, IO_TO_VIRT(offset)); | ||
| 302 | } | ||
| 303 | |||
| 304 | void tegra_apb_io_init(void) | ||
| 305 | { | ||
| 306 | /* Need to use dma only when it is Tegra20 based platform */ | ||
| 307 | if (of_machine_is_compatible("nvidia,tegra20") || | ||
| 308 | !of_have_populated_dt()) { | ||
| 309 | apbio_read = tegra_apb_readl_using_dma; | ||
| 310 | apbio_write = tegra_apb_writel_using_dma; | ||
| 311 | } else { | ||
| 312 | apbio_read = tegra_apb_readl_direct; | ||
| 313 | apbio_write = tegra_apb_writel_direct; | ||
| 314 | } | ||
| 315 | } | ||
| 316 | |||
| 317 | u32 tegra_apb_readl(unsigned long offset) | ||
| 318 | { | ||
| 319 | return apbio_read(offset); | ||
| 320 | } | ||
| 321 | |||
| 322 | void tegra_apb_writel(u32 value, unsigned long offset) | ||
| 323 | { | ||
| 324 | apbio_write(value, offset); | ||
| 325 | } | ||
diff --git a/arch/arm/mach-tegra/apbio.h b/arch/arm/mach-tegra/apbio.h index 8b49e8c89a64..f05d71c303c7 100644 --- a/arch/arm/mach-tegra/apbio.h +++ b/arch/arm/mach-tegra/apbio.h | |||
| @@ -16,24 +16,7 @@ | |||
| 16 | #ifndef __MACH_TEGRA_APBIO_H | 16 | #ifndef __MACH_TEGRA_APBIO_H |
| 17 | #define __MACH_TEGRA_APBIO_H | 17 | #define __MACH_TEGRA_APBIO_H |
| 18 | 18 | ||
| 19 | #ifdef CONFIG_TEGRA_SYSTEM_DMA | 19 | void tegra_apb_io_init(void); |
| 20 | |||
| 21 | u32 tegra_apb_readl(unsigned long offset); | 20 | u32 tegra_apb_readl(unsigned long offset); |
| 22 | void tegra_apb_writel(u32 value, unsigned long offset); | 21 | void tegra_apb_writel(u32 value, unsigned long offset); |
| 23 | |||
| 24 | #else | ||
| 25 | #include <asm/io.h> | ||
| 26 | #include <mach/io.h> | ||
| 27 | |||
| 28 | static inline u32 tegra_apb_readl(unsigned long offset) | ||
| 29 | { | ||
| 30 | return readl(IO_TO_VIRT(offset)); | ||
| 31 | } | ||
| 32 | |||
| 33 | static inline void tegra_apb_writel(u32 value, unsigned long offset) | ||
| 34 | { | ||
| 35 | writel(value, IO_TO_VIRT(offset)); | ||
| 36 | } | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #endif | 22 | #endif |
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 204a5c8b0b57..96fef6bcc651 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c | |||
| @@ -33,6 +33,7 @@ | |||
| 33 | #include "clock.h" | 33 | #include "clock.h" |
| 34 | #include "fuse.h" | 34 | #include "fuse.h" |
| 35 | #include "pmc.h" | 35 | #include "pmc.h" |
| 36 | #include "apbio.h" | ||
| 36 | 37 | ||
| 37 | /* | 38 | /* |
| 38 | * Storage for debug-macro.S's state. | 39 | * Storage for debug-macro.S's state. |
| @@ -127,6 +128,7 @@ static void __init tegra_init_cache(u32 tag_latency, u32 data_latency) | |||
| 127 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC | 128 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC |
| 128 | void __init tegra20_init_early(void) | 129 | void __init tegra20_init_early(void) |
| 129 | { | 130 | { |
| 131 | tegra_apb_io_init(); | ||
| 130 | tegra_init_fuse(); | 132 | tegra_init_fuse(); |
| 131 | tegra2_init_clocks(); | 133 | tegra2_init_clocks(); |
| 132 | tegra_clk_init_from_table(tegra20_clk_init_table); | 134 | tegra_clk_init_from_table(tegra20_clk_init_table); |
| @@ -138,6 +140,7 @@ void __init tegra20_init_early(void) | |||
| 138 | #ifdef CONFIG_ARCH_TEGRA_3x_SOC | 140 | #ifdef CONFIG_ARCH_TEGRA_3x_SOC |
| 139 | void __init tegra30_init_early(void) | 141 | void __init tegra30_init_early(void) |
| 140 | { | 142 | { |
| 143 | tegra_apb_io_init(); | ||
| 141 | tegra_init_fuse(); | 144 | tegra_init_fuse(); |
| 142 | tegra30_init_clocks(); | 145 | tegra30_init_clocks(); |
| 143 | tegra_clk_init_from_table(tegra30_clk_init_table); | 146 | tegra_clk_init_from_table(tegra30_clk_init_table); |
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig index cf8730d35e70..fc3730f01650 100644 --- a/arch/arm/mach-vexpress/Kconfig +++ b/arch/arm/mach-vexpress/Kconfig | |||
| @@ -2,7 +2,8 @@ menu "Versatile Express platform type" | |||
| 2 | depends on ARCH_VEXPRESS | 2 | depends on ARCH_VEXPRESS |
| 3 | 3 | ||
| 4 | config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA | 4 | config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA |
| 5 | bool | 5 | bool "Enable A5 and A9 only errata work-arounds" |
| 6 | default y | ||
| 6 | select ARM_ERRATA_720789 | 7 | select ARM_ERRATA_720789 |
| 7 | select ARM_ERRATA_751472 | 8 | select ARM_ERRATA_751472 |
| 8 | select PL310_ERRATA_753970 if CACHE_PL310 | 9 | select PL310_ERRATA_753970 if CACHE_PL310 |
| @@ -14,7 +15,6 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA | |||
| 14 | 15 | ||
| 15 | config ARCH_VEXPRESS_CA9X4 | 16 | config ARCH_VEXPRESS_CA9X4 |
| 16 | bool "Versatile Express Cortex-A9x4 tile" | 17 | bool "Versatile Express Cortex-A9x4 tile" |
| 17 | select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA | ||
| 18 | select ARM_GIC | 18 | select ARM_GIC |
| 19 | select CPU_V7 | 19 | select CPU_V7 |
| 20 | select HAVE_SMP | 20 | select HAVE_SMP |
| @@ -22,7 +22,6 @@ config ARCH_VEXPRESS_CA9X4 | |||
| 22 | 22 | ||
| 23 | config ARCH_VEXPRESS_DT | 23 | config ARCH_VEXPRESS_DT |
| 24 | bool "Device Tree support for Versatile Express platforms" | 24 | bool "Device Tree support for Versatile Express platforms" |
| 25 | select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA | ||
| 26 | select ARM_GIC | 25 | select ARM_GIC |
| 27 | select ARM_PATCH_PHYS_VIRT | 26 | select ARM_PATCH_PHYS_VIRT |
| 28 | select AUTO_ZRELADDR | 27 | select AUTO_ZRELADDR |
diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot index 909f85ebf5f4..318d308dfb93 100644 --- a/arch/arm/mach-vexpress/Makefile.boot +++ b/arch/arm/mach-vexpress/Makefile.boot | |||
| @@ -6,4 +6,5 @@ initrd_phys-y := 0x60800000 | |||
| 6 | 6 | ||
| 7 | dtb-$(CONFIG_ARCH_VEXPRESS_DT) += vexpress-v2p-ca5s.dtb \ | 7 | dtb-$(CONFIG_ARCH_VEXPRESS_DT) += vexpress-v2p-ca5s.dtb \ |
| 8 | vexpress-v2p-ca9.dtb \ | 8 | vexpress-v2p-ca9.dtb \ |
| 9 | vexpress-v2p-ca15-tc1.dtb | 9 | vexpress-v2p-ca15-tc1.dtb \ |
| 10 | vexpress-v2p-ca15_a7.dtb | ||
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c index c65cc3b462a5..61c492403b05 100644 --- a/arch/arm/mach-vexpress/ct-ca9x4.c +++ b/arch/arm/mach-vexpress/ct-ca9x4.c | |||
| @@ -66,8 +66,15 @@ static void __init ct_ca9x4_init_irq(void) | |||
| 66 | 66 | ||
| 67 | static void ct_ca9x4_clcd_enable(struct clcd_fb *fb) | 67 | static void ct_ca9x4_clcd_enable(struct clcd_fb *fb) |
| 68 | { | 68 | { |
| 69 | v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0); | 69 | u32 site = v2m_get_master_site(); |
| 70 | v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE_DB1, 2); | 70 | |
| 71 | /* | ||
| 72 | * Old firmware was using the "site" component of the command | ||
| 73 | * to control the DVI muxer (while it should be always 0 ie. MB). | ||
| 74 | * Newer firmware uses the data register. Keep both for compatibility. | ||
| 75 | */ | ||
| 76 | v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE(site), site); | ||
| 77 | v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE(SYS_CFG_SITE_MB), 2); | ||
| 71 | } | 78 | } |
| 72 | 79 | ||
| 73 | static int ct_ca9x4_clcd_setup(struct clcd_fb *fb) | 80 | static int ct_ca9x4_clcd_setup(struct clcd_fb *fb) |
| @@ -105,43 +112,11 @@ static struct amba_device *ct_ca9x4_amba_devs[] __initdata = { | |||
| 105 | }; | 112 | }; |
| 106 | 113 | ||
| 107 | 114 | ||
| 108 | static long ct_round(struct clk *clk, unsigned long rate) | 115 | static struct v2m_osc ct_osc1 = { |
| 109 | { | 116 | .osc = 1, |
| 110 | return rate; | 117 | .rate_min = 10000000, |
| 111 | } | 118 | .rate_max = 80000000, |
| 112 | 119 | .rate_default = 23750000, | |
| 113 | static int ct_set(struct clk *clk, unsigned long rate) | ||
| 114 | { | ||
| 115 | return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_DB1 | 1, rate); | ||
| 116 | } | ||
| 117 | |||
| 118 | static const struct clk_ops osc1_clk_ops = { | ||
| 119 | .round = ct_round, | ||
| 120 | .set = ct_set, | ||
| 121 | }; | ||
| 122 | |||
| 123 | static struct clk osc1_clk = { | ||
| 124 | .ops = &osc1_clk_ops, | ||
| 125 | .rate = 24000000, | ||
| 126 | }; | ||
| 127 | |||
| 128 | static struct clk ct_sp804_clk = { | ||
| 129 | .rate = 1000000, | ||
| 130 | }; | ||
| 131 | |||
| 132 | static struct clk_lookup lookups[] = { | ||
| 133 | { /* CLCD */ | ||
| 134 | .dev_id = "ct:clcd", | ||
| 135 | .clk = &osc1_clk, | ||
| 136 | }, { /* SP804 timers */ | ||
| 137 | .dev_id = "sp804", | ||
| 138 | .con_id = "ct-timer0", | ||
| 139 | .clk = &ct_sp804_clk, | ||
| 140 | }, { /* SP804 timers */ | ||
| 141 | .dev_id = "sp804", | ||
| 142 | .con_id = "ct-timer1", | ||
| 143 | .clk = &ct_sp804_clk, | ||
| 144 | }, | ||
| 145 | }; | 120 | }; |
| 146 | 121 | ||
| 147 | static struct resource pmu_resources[] = { | 122 | static struct resource pmu_resources[] = { |
| @@ -174,14 +149,10 @@ static struct platform_device pmu_device = { | |||
| 174 | .resource = pmu_resources, | 149 | .resource = pmu_resources, |
| 175 | }; | 150 | }; |
| 176 | 151 | ||
| 177 | static void __init ct_ca9x4_init_early(void) | ||
| 178 | { | ||
| 179 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); | ||
| 180 | } | ||
| 181 | |||
| 182 | static void __init ct_ca9x4_init(void) | 152 | static void __init ct_ca9x4_init(void) |
| 183 | { | 153 | { |
| 184 | int i; | 154 | int i; |
| 155 | struct clk *clk; | ||
| 185 | 156 | ||
| 186 | #ifdef CONFIG_CACHE_L2X0 | 157 | #ifdef CONFIG_CACHE_L2X0 |
| 187 | void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K); | 158 | void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K); |
| @@ -193,6 +164,10 @@ static void __init ct_ca9x4_init(void) | |||
| 193 | l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff); | 164 | l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff); |
| 194 | #endif | 165 | #endif |
| 195 | 166 | ||
| 167 | ct_osc1.site = v2m_get_master_site(); | ||
| 168 | clk = v2m_osc_register("ct:osc1", &ct_osc1); | ||
| 169 | clk_register_clkdev(clk, NULL, "ct:clcd"); | ||
| 170 | |||
| 196 | for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++) | 171 | for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++) |
| 197 | amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource); | 172 | amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource); |
| 198 | 173 | ||
| @@ -234,7 +209,6 @@ struct ct_desc ct_ca9x4_desc __initdata = { | |||
| 234 | .id = V2M_CT_ID_CA9, | 209 | .id = V2M_CT_ID_CA9, |
| 235 | .name = "CA9x4", | 210 | .name = "CA9x4", |
| 236 | .map_io = ct_ca9x4_map_io, | 211 | .map_io = ct_ca9x4_map_io, |
| 237 | .init_early = ct_ca9x4_init_early, | ||
| 238 | .init_irq = ct_ca9x4_init_irq, | 212 | .init_irq = ct_ca9x4_init_irq, |
| 239 | .init_tile = ct_ca9x4_init, | 213 | .init_tile = ct_ca9x4_init, |
| 240 | #ifdef CONFIG_SMP | 214 | #ifdef CONFIG_SMP |
diff --git a/arch/arm/mach-vexpress/include/mach/clkdev.h b/arch/arm/mach-vexpress/include/mach/clkdev.h deleted file mode 100644 index 3f8307d73cad..000000000000 --- a/arch/arm/mach-vexpress/include/mach/clkdev.h +++ /dev/null | |||
| @@ -1,15 +0,0 @@ | |||
| 1 | #ifndef __ASM_MACH_CLKDEV_H | ||
| 2 | #define __ASM_MACH_CLKDEV_H | ||
| 3 | |||
| 4 | #include <plat/clock.h> | ||
| 5 | |||
| 6 | struct clk { | ||
| 7 | const struct clk_ops *ops; | ||
| 8 | unsigned long rate; | ||
| 9 | const struct icst_params *params; | ||
| 10 | }; | ||
| 11 | |||
| 12 | #define __clk_get(clk) ({ 1; }) | ||
| 13 | #define __clk_put(clk) do { } while (0) | ||
| 14 | |||
| 15 | #endif | ||
diff --git a/arch/arm/mach-vexpress/include/mach/debug-macro.S b/arch/arm/mach-vexpress/include/mach/debug-macro.S index fa8224794e0b..9f509f55d078 100644 --- a/arch/arm/mach-vexpress/include/mach/debug-macro.S +++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S | |||
| @@ -18,6 +18,8 @@ | |||
| 18 | 18 | ||
| 19 | #define DEBUG_LL_VIRT_BASE 0xf8000000 | 19 | #define DEBUG_LL_VIRT_BASE 0xf8000000 |
| 20 | 20 | ||
| 21 | #if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT) | ||
| 22 | |||
| 21 | .macro addruart,rp,rv,tmp | 23 | .macro addruart,rp,rv,tmp |
| 22 | 24 | ||
| 23 | @ Make an educated guess regarding the memory map: | 25 | @ Make an educated guess regarding the memory map: |
| @@ -41,3 +43,42 @@ | |||
| 41 | .endm | 43 | .endm |
| 42 | 44 | ||
| 43 | #include <asm/hardware/debug-pl01x.S> | 45 | #include <asm/hardware/debug-pl01x.S> |
| 46 | |||
| 47 | #elif defined(CONFIG_DEBUG_VEXPRESS_UART0_CA9) | ||
| 48 | |||
| 49 | .macro addruart,rp,rv,tmp | ||
| 50 | mov \rp, #DEBUG_LL_UART_OFFSET | ||
| 51 | orr \rv, \rp, #DEBUG_LL_VIRT_BASE | ||
| 52 | orr \rp, \rp, #DEBUG_LL_PHYS_BASE | ||
| 53 | .endm | ||
| 54 | |||
| 55 | #include <asm/hardware/debug-pl01x.S> | ||
| 56 | |||
| 57 | #elif defined(CONFIG_DEBUG_VEXPRESS_UART0_RS1) | ||
| 58 | |||
| 59 | .macro addruart,rp,rv,tmp | ||
| 60 | mov \rp, #DEBUG_LL_UART_OFFSET_RS1 | ||
| 61 | orr \rv, \rp, #DEBUG_LL_VIRT_BASE | ||
| 62 | orr \rp, \rp, #DEBUG_LL_PHYS_BASE_RS1 | ||
| 63 | .endm | ||
| 64 | |||
| 65 | #include <asm/hardware/debug-pl01x.S> | ||
| 66 | |||
| 67 | #else /* CONFIG_DEBUG_LL_UART_NONE */ | ||
| 68 | |||
| 69 | .macro addruart, rp, rv, tmp | ||
| 70 | /* Safe dummy values */ | ||
| 71 | mov \rp, #0 | ||
| 72 | mov \rv, #DEBUG_LL_VIRT_BASE | ||
| 73 | .endm | ||
| 74 | |||
| 75 | .macro senduart,rd,rx | ||
| 76 | .endm | ||
| 77 | |||
| 78 | .macro waituart,rd,rx | ||
| 79 | .endm | ||
| 80 | |||
| 81 | .macro busyuart,rd,rx | ||
| 82 | .endm | ||
| 83 | |||
| 84 | #endif | ||
diff --git a/arch/arm/mach-vexpress/include/mach/motherboard.h b/arch/arm/mach-vexpress/include/mach/motherboard.h index 31a92890893d..1e388c7bf4d7 100644 --- a/arch/arm/mach-vexpress/include/mach/motherboard.h +++ b/arch/arm/mach-vexpress/include/mach/motherboard.h | |||
| @@ -1,6 +1,8 @@ | |||
| 1 | #ifndef __MACH_MOTHERBOARD_H | 1 | #ifndef __MACH_MOTHERBOARD_H |
| 2 | #define __MACH_MOTHERBOARD_H | 2 | #define __MACH_MOTHERBOARD_H |
| 3 | 3 | ||
| 4 | #include <linux/clk-provider.h> | ||
| 5 | |||
| 4 | /* | 6 | /* |
| 5 | * Physical addresses, offset from V2M_PA_CS0-3 | 7 | * Physical addresses, offset from V2M_PA_CS0-3 |
| 6 | */ | 8 | */ |
| @@ -104,9 +106,10 @@ | |||
| 104 | #define SYS_CFG_REBOOT (9 << 20) | 106 | #define SYS_CFG_REBOOT (9 << 20) |
| 105 | #define SYS_CFG_DVIMODE (11 << 20) | 107 | #define SYS_CFG_DVIMODE (11 << 20) |
| 106 | #define SYS_CFG_POWER (12 << 20) | 108 | #define SYS_CFG_POWER (12 << 20) |
| 107 | #define SYS_CFG_SITE_MB (0 << 16) | 109 | #define SYS_CFG_SITE(n) ((n) << 16) |
| 108 | #define SYS_CFG_SITE_DB1 (1 << 16) | 110 | #define SYS_CFG_SITE_MB 0 |
| 109 | #define SYS_CFG_SITE_DB2 (2 << 16) | 111 | #define SYS_CFG_SITE_DB1 1 |
| 112 | #define SYS_CFG_SITE_DB2 2 | ||
| 110 | #define SYS_CFG_STACK(n) ((n) << 12) | 113 | #define SYS_CFG_STACK(n) ((n) << 12) |
| 111 | 114 | ||
| 112 | #define SYS_CFG_ERR (1 << 1) | 115 | #define SYS_CFG_ERR (1 << 1) |
| @@ -122,6 +125,8 @@ void v2m_flags_set(u32 data); | |||
| 122 | #define SYS_MISC_MASTERSITE (1 << 14) | 125 | #define SYS_MISC_MASTERSITE (1 << 14) |
| 123 | #define SYS_PROCIDx_HBI_MASK 0xfff | 126 | #define SYS_PROCIDx_HBI_MASK 0xfff |
| 124 | 127 | ||
| 128 | int v2m_get_master_site(void); | ||
| 129 | |||
| 125 | /* | 130 | /* |
| 126 | * Core tile IDs | 131 | * Core tile IDs |
| 127 | */ | 132 | */ |
| @@ -144,4 +149,21 @@ struct ct_desc { | |||
| 144 | 149 | ||
| 145 | extern struct ct_desc *ct_desc; | 150 | extern struct ct_desc *ct_desc; |
| 146 | 151 | ||
| 152 | /* | ||
| 153 | * OSC clock provider | ||
| 154 | */ | ||
| 155 | struct v2m_osc { | ||
| 156 | struct clk_hw hw; | ||
| 157 | u8 site; /* 0 = motherboard, 1 = site 1, 2 = site 2 */ | ||
| 158 | u8 stack; /* board stack position */ | ||
| 159 | u16 osc; | ||
| 160 | unsigned long rate_min; | ||
| 161 | unsigned long rate_max; | ||
| 162 | unsigned long rate_default; | ||
| 163 | }; | ||
| 164 | |||
| 165 | #define to_v2m_osc(osc) container_of(osc, struct v2m_osc, hw) | ||
| 166 | |||
| 167 | struct clk *v2m_osc_register(const char *name, struct v2m_osc *osc); | ||
| 168 | |||
| 147 | #endif | 169 | #endif |
diff --git a/arch/arm/mach-vexpress/include/mach/uncompress.h b/arch/arm/mach-vexpress/include/mach/uncompress.h index 7dab5596b868..1e472eb0bbdc 100644 --- a/arch/arm/mach-vexpress/include/mach/uncompress.h +++ b/arch/arm/mach-vexpress/include/mach/uncompress.h | |||
| @@ -27,6 +27,7 @@ | |||
| 27 | 27 | ||
| 28 | static unsigned long get_uart_base(void) | 28 | static unsigned long get_uart_base(void) |
| 29 | { | 29 | { |
| 30 | #if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT) | ||
| 30 | unsigned long mpcore_periph; | 31 | unsigned long mpcore_periph; |
| 31 | 32 | ||
| 32 | /* | 33 | /* |
| @@ -42,6 +43,13 @@ static unsigned long get_uart_base(void) | |||
| 42 | return UART_BASE; | 43 | return UART_BASE; |
| 43 | else | 44 | else |
| 44 | return UART_BASE_RS1; | 45 | return UART_BASE_RS1; |
| 46 | #elif defined(CONFIG_DEBUG_VEXPRESS_UART0_CA9) | ||
| 47 | return UART_BASE; | ||
| 48 | #elif defined(CONFIG_DEBUG_VEXPRESS_UART0_RS1) | ||
| 49 | return UART_BASE_RS1; | ||
| 50 | #else | ||
| 51 | return 0; | ||
| 52 | #endif | ||
| 45 | } | 53 | } |
| 46 | 54 | ||
| 47 | /* | 55 | /* |
| @@ -51,6 +59,9 @@ static inline void putc(int c) | |||
| 51 | { | 59 | { |
| 52 | unsigned long base = get_uart_base(); | 60 | unsigned long base = get_uart_base(); |
| 53 | 61 | ||
| 62 | if (!base) | ||
| 63 | return; | ||
| 64 | |||
| 54 | while (AMBA_UART_FR(base) & (1 << 5)) | 65 | while (AMBA_UART_FR(base) & (1 << 5)) |
| 55 | barrier(); | 66 | barrier(); |
| 56 | 67 | ||
| @@ -61,6 +72,9 @@ static inline void flush(void) | |||
| 61 | { | 72 | { |
| 62 | unsigned long base = get_uart_base(); | 73 | unsigned long base = get_uart_base(); |
| 63 | 74 | ||
| 75 | if (!base) | ||
| 76 | return; | ||
| 77 | |||
| 64 | while (AMBA_UART_FR(base) & (1 << 3)) | 78 | while (AMBA_UART_FR(base) & (1 << 3)) |
| 65 | barrier(); | 79 | barrier(); |
| 66 | } | 80 | } |
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c index fde26adaef32..37608f22ee31 100644 --- a/arch/arm/mach-vexpress/v2m.c +++ b/arch/arm/mach-vexpress/v2m.c | |||
| @@ -16,7 +16,10 @@ | |||
| 16 | #include <linux/spinlock.h> | 16 | #include <linux/spinlock.h> |
| 17 | #include <linux/usb/isp1760.h> | 17 | #include <linux/usb/isp1760.h> |
| 18 | #include <linux/clkdev.h> | 18 | #include <linux/clkdev.h> |
| 19 | #include <linux/clk-provider.h> | ||
| 19 | #include <linux/mtd/physmap.h> | 20 | #include <linux/mtd/physmap.h> |
| 21 | #include <linux/regulator/fixed.h> | ||
| 22 | #include <linux/regulator/machine.h> | ||
| 20 | 23 | ||
| 21 | #include <asm/arch_timer.h> | 24 | #include <asm/arch_timer.h> |
| 22 | #include <asm/mach-types.h> | 25 | #include <asm/mach-types.h> |
| @@ -81,16 +84,6 @@ static void __init v2m_sp804_init(void __iomem *base, unsigned int irq) | |||
| 81 | sp804_clockevents_init(base + TIMER_1_BASE, irq, "v2m-timer0"); | 84 | sp804_clockevents_init(base + TIMER_1_BASE, irq, "v2m-timer0"); |
| 82 | } | 85 | } |
| 83 | 86 | ||
| 84 | static void __init v2m_timer_init(void) | ||
| 85 | { | ||
| 86 | v2m_sysctl_init(ioremap(V2M_SYSCTL, SZ_4K)); | ||
| 87 | v2m_sp804_init(ioremap(V2M_TIMER01, SZ_4K), IRQ_V2M_TIMER0); | ||
| 88 | } | ||
| 89 | |||
| 90 | static struct sys_timer v2m_timer = { | ||
| 91 | .init = v2m_timer_init, | ||
| 92 | }; | ||
| 93 | |||
| 94 | 87 | ||
| 95 | static DEFINE_SPINLOCK(v2m_cfg_lock); | 88 | static DEFINE_SPINLOCK(v2m_cfg_lock); |
| 96 | 89 | ||
| @@ -147,6 +140,13 @@ void __init v2m_flags_set(u32 data) | |||
| 147 | writel(data, v2m_sysreg_base + V2M_SYS_FLAGSSET); | 140 | writel(data, v2m_sysreg_base + V2M_SYS_FLAGSSET); |
| 148 | } | 141 | } |
| 149 | 142 | ||
| 143 | int v2m_get_master_site(void) | ||
| 144 | { | ||
| 145 | u32 misc = readl(v2m_sysreg_base + V2M_SYS_MISC); | ||
| 146 | |||
| 147 | return misc & SYS_MISC_MASTERSITE ? SYS_CFG_SITE_DB2 : SYS_CFG_SITE_DB1; | ||
| 148 | } | ||
| 149 | |||
| 150 | 150 | ||
| 151 | static struct resource v2m_pcie_i2c_resource = { | 151 | static struct resource v2m_pcie_i2c_resource = { |
| 152 | .start = V2M_SERIAL_BUS_PCI, | 152 | .start = V2M_SERIAL_BUS_PCI, |
| @@ -201,6 +201,11 @@ static struct platform_device v2m_eth_device = { | |||
| 201 | .dev.platform_data = &v2m_eth_config, | 201 | .dev.platform_data = &v2m_eth_config, |
| 202 | }; | 202 | }; |
| 203 | 203 | ||
| 204 | static struct regulator_consumer_supply v2m_eth_supplies[] = { | ||
| 205 | REGULATOR_SUPPLY("vddvario", "smsc911x"), | ||
| 206 | REGULATOR_SUPPLY("vdd33a", "smsc911x"), | ||
| 207 | }; | ||
| 208 | |||
| 204 | static struct resource v2m_usb_resources[] = { | 209 | static struct resource v2m_usb_resources[] = { |
| 205 | { | 210 | { |
| 206 | .start = V2M_ISP1761, | 211 | .start = V2M_ISP1761, |
| @@ -319,98 +324,145 @@ static struct amba_device *v2m_amba_devs[] __initdata = { | |||
| 319 | }; | 324 | }; |
| 320 | 325 | ||
| 321 | 326 | ||
| 322 | static long v2m_osc_round(struct clk *clk, unsigned long rate) | 327 | static unsigned long v2m_osc_recalc_rate(struct clk_hw *hw, |
| 328 | unsigned long parent_rate) | ||
| 329 | { | ||
| 330 | struct v2m_osc *osc = to_v2m_osc(hw); | ||
| 331 | |||
| 332 | return !parent_rate ? osc->rate_default : parent_rate; | ||
| 333 | } | ||
| 334 | |||
| 335 | static long v2m_osc_round_rate(struct clk_hw *hw, unsigned long rate, | ||
| 336 | unsigned long *parent_rate) | ||
| 323 | { | 337 | { |
| 338 | struct v2m_osc *osc = to_v2m_osc(hw); | ||
| 339 | |||
| 340 | if (WARN_ON(rate < osc->rate_min)) | ||
| 341 | rate = osc->rate_min; | ||
| 342 | |||
| 343 | if (WARN_ON(rate > osc->rate_max)) | ||
| 344 | rate = osc->rate_max; | ||
| 345 | |||
| 324 | return rate; | 346 | return rate; |
| 325 | } | 347 | } |
| 326 | 348 | ||
| 327 | static int v2m_osc1_set(struct clk *clk, unsigned long rate) | 349 | static int v2m_osc_set_rate(struct clk_hw *hw, unsigned long rate, |
| 350 | unsigned long parent_rate) | ||
| 328 | { | 351 | { |
| 329 | return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_MB | 1, rate); | 352 | struct v2m_osc *osc = to_v2m_osc(hw); |
| 353 | |||
| 354 | v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE(osc->site) | | ||
| 355 | SYS_CFG_STACK(osc->stack) | osc->osc, rate); | ||
| 356 | |||
| 357 | return 0; | ||
| 330 | } | 358 | } |
| 331 | 359 | ||
| 332 | static const struct clk_ops osc1_clk_ops = { | 360 | static struct clk_ops v2m_osc_ops = { |
| 333 | .round = v2m_osc_round, | 361 | .recalc_rate = v2m_osc_recalc_rate, |
| 334 | .set = v2m_osc1_set, | 362 | .round_rate = v2m_osc_round_rate, |
| 335 | }; | 363 | .set_rate = v2m_osc_set_rate, |
| 336 | 364 | }; | |
| 337 | static struct clk osc1_clk = { | 365 | |
| 338 | .ops = &osc1_clk_ops, | 366 | struct clk * __init v2m_osc_register(const char *name, struct v2m_osc *osc) |
| 339 | .rate = 24000000, | 367 | { |
| 340 | }; | 368 | struct clk_init_data init; |
| 341 | 369 | ||
| 342 | static struct clk osc2_clk = { | 370 | WARN_ON(osc->site > 2); |
| 343 | .rate = 24000000, | 371 | WARN_ON(osc->stack > 15); |
| 344 | }; | 372 | WARN_ON(osc->osc > 4095); |
| 345 | 373 | ||
| 346 | static struct clk v2m_sp804_clk = { | 374 | init.name = name; |
| 347 | .rate = 1000000, | 375 | init.ops = &v2m_osc_ops; |
| 348 | }; | 376 | init.flags = CLK_IS_ROOT; |
| 349 | 377 | init.num_parents = 0; | |
| 350 | static struct clk v2m_ref_clk = { | 378 | |
| 351 | .rate = 32768, | 379 | osc->hw.init = &init; |
| 352 | }; | 380 | |
| 353 | 381 | return clk_register(NULL, &osc->hw); | |
| 354 | static struct clk dummy_apb_pclk; | 382 | } |
| 355 | 383 | ||
| 356 | static struct clk_lookup v2m_lookups[] = { | 384 | static struct v2m_osc v2m_mb_osc1 = { |
| 357 | { /* AMBA bus clock */ | 385 | .site = SYS_CFG_SITE_MB, |
| 358 | .con_id = "apb_pclk", | 386 | .osc = 1, |
| 359 | .clk = &dummy_apb_pclk, | 387 | .rate_min = 23750000, |
| 360 | }, { /* UART0 */ | 388 | .rate_max = 63500000, |
| 361 | .dev_id = "mb:uart0", | 389 | .rate_default = 23750000, |
| 362 | .clk = &osc2_clk, | 390 | }; |
| 363 | }, { /* UART1 */ | 391 | |
| 364 | .dev_id = "mb:uart1", | 392 | static const char *v2m_ref_clk_periphs[] __initconst = { |
| 365 | .clk = &osc2_clk, | 393 | "mb:wdt", "1000f000.wdt", "1c0f0000.wdt", /* SP805 WDT */ |
| 366 | }, { /* UART2 */ | 394 | }; |
| 367 | .dev_id = "mb:uart2", | 395 | |
| 368 | .clk = &osc2_clk, | 396 | static const char *v2m_osc1_periphs[] __initconst = { |
| 369 | }, { /* UART3 */ | 397 | "mb:clcd", "1001f000.clcd", "1c1f0000.clcd", /* PL111 CLCD */ |
| 370 | .dev_id = "mb:uart3", | 398 | }; |
| 371 | .clk = &osc2_clk, | 399 | |
| 372 | }, { /* KMI0 */ | 400 | static const char *v2m_osc2_periphs[] __initconst = { |
| 373 | .dev_id = "mb:kmi0", | 401 | "mb:mmci", "10005000.mmci", "1c050000.mmci", /* PL180 MMCI */ |
| 374 | .clk = &osc2_clk, | 402 | "mb:kmi0", "10006000.kmi", "1c060000.kmi", /* PL050 KMI0 */ |
| 375 | }, { /* KMI1 */ | 403 | "mb:kmi1", "10007000.kmi", "1c070000.kmi", /* PL050 KMI1 */ |
| 376 | .dev_id = "mb:kmi1", | 404 | "mb:uart0", "10009000.uart", "1c090000.uart", /* PL011 UART0 */ |
| 377 | .clk = &osc2_clk, | 405 | "mb:uart1", "1000a000.uart", "1c0a0000.uart", /* PL011 UART1 */ |
| 378 | }, { /* MMC0 */ | 406 | "mb:uart2", "1000b000.uart", "1c0b0000.uart", /* PL011 UART2 */ |
| 379 | .dev_id = "mb:mmci", | 407 | "mb:uart3", "1000c000.uart", "1c0c0000.uart", /* PL011 UART3 */ |
| 380 | .clk = &osc2_clk, | 408 | }; |
| 381 | }, { /* CLCD */ | 409 | |
| 382 | .dev_id = "mb:clcd", | 410 | static void __init v2m_clk_init(void) |
| 383 | .clk = &osc1_clk, | 411 | { |
| 384 | }, { /* SP805 WDT */ | 412 | struct clk *clk; |
| 385 | .dev_id = "mb:wdt", | 413 | int i; |
| 386 | .clk = &v2m_ref_clk, | 414 | |
| 387 | }, { /* SP804 timers */ | 415 | clk = clk_register_fixed_rate(NULL, "dummy_apb_pclk", NULL, |
| 388 | .dev_id = "sp804", | 416 | CLK_IS_ROOT, 0); |
| 389 | .con_id = "v2m-timer0", | 417 | WARN_ON(clk_register_clkdev(clk, "apb_pclk", NULL)); |
| 390 | .clk = &v2m_sp804_clk, | 418 | |
| 391 | }, { /* SP804 timers */ | 419 | clk = clk_register_fixed_rate(NULL, "mb:ref_clk", NULL, |
| 392 | .dev_id = "sp804", | 420 | CLK_IS_ROOT, 32768); |
| 393 | .con_id = "v2m-timer1", | 421 | for (i = 0; i < ARRAY_SIZE(v2m_ref_clk_periphs); i++) |
| 394 | .clk = &v2m_sp804_clk, | 422 | WARN_ON(clk_register_clkdev(clk, NULL, v2m_ref_clk_periphs[i])); |
| 395 | }, | 423 | |
| 424 | clk = clk_register_fixed_rate(NULL, "mb:sp804_clk", NULL, | ||
| 425 | CLK_IS_ROOT, 1000000); | ||
| 426 | WARN_ON(clk_register_clkdev(clk, "v2m-timer0", "sp804")); | ||
| 427 | WARN_ON(clk_register_clkdev(clk, "v2m-timer1", "sp804")); | ||
| 428 | |||
| 429 | clk = v2m_osc_register("mb:osc1", &v2m_mb_osc1); | ||
| 430 | for (i = 0; i < ARRAY_SIZE(v2m_osc1_periphs); i++) | ||
| 431 | WARN_ON(clk_register_clkdev(clk, NULL, v2m_osc1_periphs[i])); | ||
| 432 | |||
| 433 | clk = clk_register_fixed_rate(NULL, "mb:osc2", NULL, | ||
| 434 | CLK_IS_ROOT, 24000000); | ||
| 435 | for (i = 0; i < ARRAY_SIZE(v2m_osc2_periphs); i++) | ||
| 436 | WARN_ON(clk_register_clkdev(clk, NULL, v2m_osc2_periphs[i])); | ||
| 437 | } | ||
| 438 | |||
| 439 | static void __init v2m_timer_init(void) | ||
| 440 | { | ||
| 441 | v2m_sysctl_init(ioremap(V2M_SYSCTL, SZ_4K)); | ||
| 442 | v2m_clk_init(); | ||
| 443 | v2m_sp804_init(ioremap(V2M_TIMER01, SZ_4K), IRQ_V2M_TIMER0); | ||
| 444 | } | ||
| 445 | |||
| 446 | static struct sys_timer v2m_timer = { | ||
| 447 | .init = v2m_timer_init, | ||
| 396 | }; | 448 | }; |
| 397 | 449 | ||
| 398 | static void __init v2m_init_early(void) | 450 | static void __init v2m_init_early(void) |
| 399 | { | 451 | { |
| 400 | ct_desc->init_early(); | 452 | if (ct_desc->init_early) |
| 401 | clkdev_add_table(v2m_lookups, ARRAY_SIZE(v2m_lookups)); | 453 | ct_desc->init_early(); |
| 402 | versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000); | 454 | versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000); |
| 403 | } | 455 | } |
| 404 | 456 | ||
| 405 | static void v2m_power_off(void) | 457 | static void v2m_power_off(void) |
| 406 | { | 458 | { |
| 407 | if (v2m_cfg_write(SYS_CFG_SHUTDOWN | SYS_CFG_SITE_MB, 0)) | 459 | if (v2m_cfg_write(SYS_CFG_SHUTDOWN | SYS_CFG_SITE(SYS_CFG_SITE_MB), 0)) |
| 408 | printk(KERN_EMERG "Unable to shutdown\n"); | 460 | printk(KERN_EMERG "Unable to shutdown\n"); |
| 409 | } | 461 | } |
| 410 | 462 | ||
| 411 | static void v2m_restart(char str, const char *cmd) | 463 | static void v2m_restart(char str, const char *cmd) |
| 412 | { | 464 | { |
| 413 | if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0)) | 465 | if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE(SYS_CFG_SITE_MB), 0)) |
| 414 | printk(KERN_EMERG "Unable to reboot\n"); | 466 | printk(KERN_EMERG "Unable to reboot\n"); |
| 415 | } | 467 | } |
| 416 | 468 | ||
| @@ -458,6 +510,9 @@ static void __init v2m_init(void) | |||
| 458 | { | 510 | { |
| 459 | int i; | 511 | int i; |
| 460 | 512 | ||
| 513 | regulator_register_fixed(0, v2m_eth_supplies, | ||
| 514 | ARRAY_SIZE(v2m_eth_supplies)); | ||
| 515 | |||
| 461 | platform_device_register(&v2m_pcie_i2c_device); | 516 | platform_device_register(&v2m_pcie_i2c_device); |
| 462 | platform_device_register(&v2m_ddc_i2c_device); | 517 | platform_device_register(&v2m_ddc_i2c_device); |
| 463 | platform_device_register(&v2m_flash_device); | 518 | platform_device_register(&v2m_flash_device); |
| @@ -522,77 +577,6 @@ void __init v2m_dt_map_io(void) | |||
| 522 | #endif | 577 | #endif |
| 523 | } | 578 | } |
| 524 | 579 | ||
| 525 | static struct clk_lookup v2m_dt_lookups[] = { | ||
| 526 | { /* AMBA bus clock */ | ||
| 527 | .con_id = "apb_pclk", | ||
| 528 | .clk = &dummy_apb_pclk, | ||
| 529 | }, { /* SP804 timers */ | ||
| 530 | .dev_id = "sp804", | ||
| 531 | .con_id = "v2m-timer0", | ||
| 532 | .clk = &v2m_sp804_clk, | ||
| 533 | }, { /* SP804 timers */ | ||
| 534 | .dev_id = "sp804", | ||
| 535 | .con_id = "v2m-timer1", | ||
| 536 | .clk = &v2m_sp804_clk, | ||
| 537 | }, { /* PL180 MMCI */ | ||
| 538 | .dev_id = "mb:mmci", /* 10005000.mmci */ | ||
| 539 | .clk = &osc2_clk, | ||
| 540 | }, { /* PL050 KMI0 */ | ||
| 541 | .dev_id = "10006000.kmi", | ||
| 542 | .clk = &osc2_clk, | ||
| 543 | }, { /* PL050 KMI1 */ | ||
| 544 | .dev_id = "10007000.kmi", | ||
| 545 | .clk = &osc2_clk, | ||
| 546 | }, { /* PL011 UART0 */ | ||
| 547 | .dev_id = "10009000.uart", | ||
| 548 | .clk = &osc2_clk, | ||
| 549 | }, { /* PL011 UART1 */ | ||
| 550 | .dev_id = "1000a000.uart", | ||
| 551 | .clk = &osc2_clk, | ||
| 552 | }, { /* PL011 UART2 */ | ||
| 553 | .dev_id = "1000b000.uart", | ||
| 554 | .clk = &osc2_clk, | ||
| 555 | }, { /* PL011 UART3 */ | ||
| 556 | .dev_id = "1000c000.uart", | ||
| 557 | .clk = &osc2_clk, | ||
| 558 | }, { /* SP805 WDT */ | ||
| 559 | .dev_id = "1000f000.wdt", | ||
| 560 | .clk = &v2m_ref_clk, | ||
| 561 | }, { /* PL111 CLCD */ | ||
| 562 | .dev_id = "1001f000.clcd", | ||
| 563 | .clk = &osc1_clk, | ||
| 564 | }, | ||
| 565 | /* RS1 memory map */ | ||
| 566 | { /* PL180 MMCI */ | ||
| 567 | .dev_id = "mb:mmci", /* 1c050000.mmci */ | ||
| 568 | .clk = &osc2_clk, | ||
| 569 | }, { /* PL050 KMI0 */ | ||
| 570 | .dev_id = "1c060000.kmi", | ||
| 571 | .clk = &osc2_clk, | ||
| 572 | }, { /* PL050 KMI1 */ | ||
| 573 | .dev_id = "1c070000.kmi", | ||
| 574 | .clk = &osc2_clk, | ||
| 575 | }, { /* PL011 UART0 */ | ||
| 576 | .dev_id = "1c090000.uart", | ||
| 577 | .clk = &osc2_clk, | ||
| 578 | }, { /* PL011 UART1 */ | ||
| 579 | .dev_id = "1c0a0000.uart", | ||
| 580 | .clk = &osc2_clk, | ||
| 581 | }, { /* PL011 UART2 */ | ||
| 582 | .dev_id = "1c0b0000.uart", | ||
| 583 | .clk = &osc2_clk, | ||
| 584 | }, { /* PL011 UART3 */ | ||
| 585 | .dev_id = "1c0c0000.uart", | ||
| 586 | .clk = &osc2_clk, | ||
| 587 | }, { /* SP805 WDT */ | ||
| 588 | .dev_id = "1c0f0000.wdt", | ||
| 589 | .clk = &v2m_ref_clk, | ||
| 590 | }, { /* PL111 CLCD */ | ||
| 591 | .dev_id = "1c1f0000.clcd", | ||
| 592 | .clk = &osc1_clk, | ||
| 593 | }, | ||
| 594 | }; | ||
| 595 | |||
| 596 | void __init v2m_dt_init_early(void) | 580 | void __init v2m_dt_init_early(void) |
| 597 | { | 581 | { |
| 598 | struct device_node *node; | 582 | struct device_node *node; |
| @@ -605,8 +589,8 @@ void __init v2m_dt_init_early(void) | |||
| 605 | 589 | ||
| 606 | /* Confirm board type against DT property, if available */ | 590 | /* Confirm board type against DT property, if available */ |
| 607 | if (of_property_read_u32(allnodes, "arm,hbi", &dt_hbi) == 0) { | 591 | if (of_property_read_u32(allnodes, "arm,hbi", &dt_hbi) == 0) { |
| 608 | u32 misc = readl(v2m_sysreg_base + V2M_SYS_MISC); | 592 | int site = v2m_get_master_site(); |
| 609 | u32 id = readl(v2m_sysreg_base + (misc & SYS_MISC_MASTERSITE ? | 593 | u32 id = readl(v2m_sysreg_base + (site == SYS_CFG_SITE_DB2 ? |
| 610 | V2M_SYS_PROCID1 : V2M_SYS_PROCID0)); | 594 | V2M_SYS_PROCID1 : V2M_SYS_PROCID0)); |
| 611 | u32 hbi = id & SYS_PROCIDx_HBI_MASK; | 595 | u32 hbi = id & SYS_PROCIDx_HBI_MASK; |
| 612 | 596 | ||
| @@ -614,8 +598,6 @@ void __init v2m_dt_init_early(void) | |||
| 614 | pr_warning("vexpress: DT HBI (%x) is not matching " | 598 | pr_warning("vexpress: DT HBI (%x) is not matching " |
| 615 | "hardware (%x)!\n", dt_hbi, hbi); | 599 | "hardware (%x)!\n", dt_hbi, hbi); |
| 616 | } | 600 | } |
| 617 | |||
| 618 | clkdev_add_table(v2m_dt_lookups, ARRAY_SIZE(v2m_dt_lookups)); | ||
| 619 | } | 601 | } |
| 620 | 602 | ||
| 621 | static struct of_device_id vexpress_irq_match[] __initdata = { | 603 | static struct of_device_id vexpress_irq_match[] __initdata = { |
| @@ -637,6 +619,8 @@ static void __init v2m_dt_timer_init(void) | |||
| 637 | node = of_find_compatible_node(NULL, NULL, "arm,sp810"); | 619 | node = of_find_compatible_node(NULL, NULL, "arm,sp810"); |
| 638 | v2m_sysctl_init(of_iomap(node, 0)); | 620 | v2m_sysctl_init(of_iomap(node, 0)); |
| 639 | 621 | ||
| 622 | v2m_clk_init(); | ||
| 623 | |||
| 640 | err = of_property_read_string(of_aliases, "arm,v2m_timer", &path); | 624 | err = of_property_read_string(of_aliases, "arm,v2m_timer", &path); |
| 641 | if (WARN_ON(err)) | 625 | if (WARN_ON(err)) |
| 642 | return; | 626 | return; |
diff --git a/arch/arm/mach-vt8500/Makefile b/arch/arm/mach-vt8500/Makefile index 81aedb7c893c..54e69973f39b 100644 --- a/arch/arm/mach-vt8500/Makefile +++ b/arch/arm/mach-vt8500/Makefile | |||
| @@ -1,4 +1,4 @@ | |||
| 1 | obj-y += devices.o gpio.o irq.o timer.o | 1 | obj-y += devices.o gpio.o irq.o timer.o restart.o |
| 2 | 2 | ||
| 3 | obj-$(CONFIG_VTWM_VERSION_VT8500) += devices-vt8500.o | 3 | obj-$(CONFIG_VTWM_VERSION_VT8500) += devices-vt8500.o |
| 4 | obj-$(CONFIG_VTWM_VERSION_WM8505) += devices-wm8505.o | 4 | obj-$(CONFIG_VTWM_VERSION_WM8505) += devices-wm8505.o |
diff --git a/arch/arm/mach-vt8500/bv07.c b/arch/arm/mach-vt8500/bv07.c index a464c7584411..f9fbeb2d10e9 100644 --- a/arch/arm/mach-vt8500/bv07.c +++ b/arch/arm/mach-vt8500/bv07.c | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | 23 | ||
| 24 | #include <asm/mach-types.h> | 24 | #include <asm/mach-types.h> |
| 25 | #include <asm/mach/arch.h> | 25 | #include <asm/mach/arch.h> |
| 26 | #include <mach/restart.h> | ||
| 26 | 27 | ||
| 27 | #include "devices.h" | 28 | #include "devices.h" |
| 28 | 29 | ||
| @@ -62,6 +63,7 @@ void __init bv07_init(void) | |||
| 62 | else | 63 | else |
| 63 | printk(KERN_ERR "PMC Hibernation register could not be remapped, not enabling power off!\n"); | 64 | printk(KERN_ERR "PMC Hibernation register could not be remapped, not enabling power off!\n"); |
| 64 | 65 | ||
| 66 | wmt_setup_restart(); | ||
| 65 | vt8500_set_resources(); | 67 | vt8500_set_resources(); |
| 66 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 68 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 67 | vt8500_gpio_init(); | 69 | vt8500_gpio_init(); |
| @@ -69,6 +71,7 @@ void __init bv07_init(void) | |||
| 69 | 71 | ||
| 70 | MACHINE_START(BV07, "Benign BV07 Mini Netbook") | 72 | MACHINE_START(BV07, "Benign BV07 Mini Netbook") |
| 71 | .atag_offset = 0x100, | 73 | .atag_offset = 0x100, |
| 74 | .restart = wmt_restart, | ||
| 72 | .reserve = vt8500_reserve_mem, | 75 | .reserve = vt8500_reserve_mem, |
| 73 | .map_io = vt8500_map_io, | 76 | .map_io = vt8500_map_io, |
| 74 | .init_irq = vt8500_init_irq, | 77 | .init_irq = vt8500_init_irq, |
diff --git a/arch/arm/mach-vt8500/include/mach/restart.h b/arch/arm/mach-vt8500/include/mach/restart.h new file mode 100644 index 000000000000..89f9b787d2a0 --- /dev/null +++ b/arch/arm/mach-vt8500/include/mach/restart.h | |||
| @@ -0,0 +1,17 @@ | |||
| 1 | /* linux/arch/arm/mach-vt8500/restart.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> | ||
| 4 | * | ||
| 5 | * This software is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2, as published by the Free Software Foundation, and | ||
| 7 | * may be copied, distributed, and modified under those terms. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | */ | ||
| 15 | |||
| 16 | void wmt_setup_restart(void); | ||
| 17 | void wmt_restart(char mode, const char *cmd); | ||
diff --git a/arch/arm/mach-vt8500/include/mach/system.h b/arch/arm/mach-vt8500/include/mach/system.h deleted file mode 100644 index 58fa8010ee61..000000000000 --- a/arch/arm/mach-vt8500/include/mach/system.h +++ /dev/null | |||
| @@ -1,13 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-vt8500/include/mach/system.h | ||
| 3 | * | ||
| 4 | */ | ||
| 5 | #include <asm/io.h> | ||
| 6 | |||
| 7 | /* PM Software Reset request register */ | ||
| 8 | #define VT8500_PMSR_VIRT 0xf8130060 | ||
| 9 | |||
| 10 | static inline void arch_reset(char mode, const char *cmd) | ||
| 11 | { | ||
| 12 | writel(1, VT8500_PMSR_VIRT); | ||
| 13 | } | ||
diff --git a/arch/arm/mach-vt8500/restart.c b/arch/arm/mach-vt8500/restart.c new file mode 100644 index 000000000000..497e89a5e130 --- /dev/null +++ b/arch/arm/mach-vt8500/restart.c | |||
| @@ -0,0 +1,54 @@ | |||
| 1 | /* linux/arch/arm/mach-vt8500/restart.c | ||
| 2 | * | ||
| 3 | * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> | ||
| 4 | * | ||
| 5 | * This software is licensed under the terms of the GNU General Public | ||
| 6 | * License version 2, as published by the Free Software Foundation, and | ||
| 7 | * may be copied, distributed, and modified under those terms. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | */ | ||
| 15 | #include <asm/io.h> | ||
| 16 | #include <linux/of.h> | ||
| 17 | #include <linux/of_address.h> | ||
| 18 | |||
| 19 | #define LEGACY_PMC_BASE 0xD8130000 | ||
| 20 | #define WMT_PRIZM_PMSR_REG 0x60 | ||
| 21 | |||
| 22 | static void __iomem *pmc_base; | ||
| 23 | |||
| 24 | void wmt_setup_restart(void) | ||
| 25 | { | ||
| 26 | struct device_node *np; | ||
| 27 | |||
| 28 | /* | ||
| 29 | * Check if Power Mgmt Controller node is present in device tree. If no | ||
| 30 | * device tree node, use the legacy PMSR value (valid for all current | ||
| 31 | * SoCs). | ||
| 32 | */ | ||
| 33 | np = of_find_compatible_node(NULL, NULL, "wmt,prizm-pmc"); | ||
| 34 | if (np) { | ||
| 35 | pmc_base = of_iomap(np, 0); | ||
| 36 | |||
| 37 | if (!pmc_base) | ||
| 38 | pr_err("%s:of_iomap(pmc) failed\n", __func__); | ||
| 39 | |||
| 40 | of_node_put(np); | ||
| 41 | } else { | ||
| 42 | pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000); | ||
| 43 | if (!pmc_base) { | ||
| 44 | pr_err("%s:ioremap(rstc) failed\n", __func__); | ||
| 45 | return; | ||
| 46 | } | ||
| 47 | } | ||
| 48 | } | ||
| 49 | |||
| 50 | void wmt_restart(char mode, const char *cmd) | ||
| 51 | { | ||
| 52 | if (pmc_base) | ||
| 53 | writel(1, pmc_base + WMT_PRIZM_PMSR_REG); | ||
| 54 | } | ||
diff --git a/arch/arm/mach-vt8500/wm8505_7in.c b/arch/arm/mach-vt8500/wm8505_7in.c index cf910a956080..db19886caf7c 100644 --- a/arch/arm/mach-vt8500/wm8505_7in.c +++ b/arch/arm/mach-vt8500/wm8505_7in.c | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | 23 | ||
| 24 | #include <asm/mach-types.h> | 24 | #include <asm/mach-types.h> |
| 25 | #include <asm/mach/arch.h> | 25 | #include <asm/mach/arch.h> |
| 26 | #include <mach/restart.h> | ||
| 26 | 27 | ||
| 27 | #include "devices.h" | 28 | #include "devices.h" |
| 28 | 29 | ||
| @@ -61,7 +62,7 @@ void __init wm8505_7in_init(void) | |||
| 61 | pm_power_off = &vt8500_power_off; | 62 | pm_power_off = &vt8500_power_off; |
| 62 | else | 63 | else |
| 63 | printk(KERN_ERR "PMC Hibernation register could not be remapped, not enabling power off!\n"); | 64 | printk(KERN_ERR "PMC Hibernation register could not be remapped, not enabling power off!\n"); |
| 64 | 65 | wmt_setup_restart(); | |
| 65 | wm8505_set_resources(); | 66 | wm8505_set_resources(); |
| 66 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 67 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 67 | vt8500_gpio_init(); | 68 | vt8500_gpio_init(); |
| @@ -69,6 +70,7 @@ void __init wm8505_7in_init(void) | |||
| 69 | 70 | ||
| 70 | MACHINE_START(WM8505_7IN_NETBOOK, "WM8505 7-inch generic netbook") | 71 | MACHINE_START(WM8505_7IN_NETBOOK, "WM8505 7-inch generic netbook") |
| 71 | .atag_offset = 0x100, | 72 | .atag_offset = 0x100, |
| 73 | .restart = wmt_restart, | ||
| 72 | .reserve = wm8505_reserve_mem, | 74 | .reserve = wm8505_reserve_mem, |
| 73 | .map_io = wm8505_map_io, | 75 | .map_io = wm8505_map_io, |
| 74 | .init_irq = wm8505_init_irq, | 76 | .init_irq = wm8505_init_irq, |
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 4044abcf6f9d..655878bcc96d 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c | |||
| @@ -1091,7 +1091,7 @@ error: | |||
| 1091 | while (--i) | 1091 | while (--i) |
| 1092 | if (pages[i]) | 1092 | if (pages[i]) |
| 1093 | __free_pages(pages[i], 0); | 1093 | __free_pages(pages[i], 0); |
| 1094 | if (array_size < PAGE_SIZE) | 1094 | if (array_size <= PAGE_SIZE) |
| 1095 | kfree(pages); | 1095 | kfree(pages); |
| 1096 | else | 1096 | else |
| 1097 | vfree(pages); | 1097 | vfree(pages); |
| @@ -1106,7 +1106,7 @@ static int __iommu_free_buffer(struct device *dev, struct page **pages, size_t s | |||
| 1106 | for (i = 0; i < count; i++) | 1106 | for (i = 0; i < count; i++) |
| 1107 | if (pages[i]) | 1107 | if (pages[i]) |
| 1108 | __free_pages(pages[i], 0); | 1108 | __free_pages(pages[i], 0); |
| 1109 | if (array_size < PAGE_SIZE) | 1109 | if (array_size <= PAGE_SIZE) |
| 1110 | kfree(pages); | 1110 | kfree(pages); |
| 1111 | else | 1111 | else |
| 1112 | vfree(pages); | 1112 | vfree(pages); |
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_rtc.c b/arch/arm/plat-mxc/devices/platform-mxc_rtc.c index 16d0ec4df5f6..a5c9ad5721c2 100644 --- a/arch/arm/plat-mxc/devices/platform-mxc_rtc.c +++ b/arch/arm/plat-mxc/devices/platform-mxc_rtc.c | |||
| @@ -20,6 +20,11 @@ const struct imx_mxc_rtc_data imx31_mxc_rtc_data __initconst = | |||
| 20 | imx_mxc_rtc_data_entry_single(MX31); | 20 | imx_mxc_rtc_data_entry_single(MX31); |
| 21 | #endif /* ifdef CONFIG_SOC_IMX31 */ | 21 | #endif /* ifdef CONFIG_SOC_IMX31 */ |
| 22 | 22 | ||
| 23 | #ifdef CONFIG_SOC_IMX35 | ||
| 24 | const struct imx_mxc_rtc_data imx35_mxc_rtc_data __initconst = | ||
| 25 | imx_mxc_rtc_data_entry_single(MX35); | ||
| 26 | #endif /* ifdef CONFIG_SOC_IMX35 */ | ||
| 27 | |||
| 23 | struct platform_device *__init imx_add_mxc_rtc( | 28 | struct platform_device *__init imx_add_mxc_rtc( |
| 24 | const struct imx_mxc_rtc_data *data) | 29 | const struct imx_mxc_rtc_data *data) |
| 25 | { | 30 | { |
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h index 36c8989d9de6..2623e7a2e190 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h | |||
| @@ -107,11 +107,13 @@ | |||
| 107 | #define MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL) | 107 | #define MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL) |
| 108 | #define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL) | 108 | #define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL) |
| 109 | #define MX51_PAD_EIM_D25__USBOTG_DATA1 IOMUX_PAD(0x414, 0x080, 2, __NA_, 0, NO_PAD_CTRL) | 109 | #define MX51_PAD_EIM_D25__USBOTG_DATA1 IOMUX_PAD(0x414, 0x080, 2, __NA_, 0, NO_PAD_CTRL) |
| 110 | #define MX51_PAD_EIM_D25__GPT_CMPOUT1 IOMUX_PAD(0x414, 0x080, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 110 | #define MX51_PAD_EIM_D26__EIM_D26 IOMUX_PAD(0x418, 0x084, 0, __NA_, 0, NO_PAD_CTRL) | 111 | #define MX51_PAD_EIM_D26__EIM_D26 IOMUX_PAD(0x418, 0x084, 0, __NA_, 0, NO_PAD_CTRL) |
| 111 | #define MX51_PAD_EIM_D26__KEY_COL7 IOMUX_PAD(0x418, 0x084, 1, 0x9cc, 0, NO_PAD_CTRL) | 112 | #define MX51_PAD_EIM_D26__KEY_COL7 IOMUX_PAD(0x418, 0x084, 1, 0x9cc, 0, NO_PAD_CTRL) |
| 112 | #define MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL) | 113 | #define MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL) |
| 113 | #define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL) | 114 | #define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL) |
| 114 | #define MX51_PAD_EIM_D26__USBOTG_DATA2 IOMUX_PAD(0x418, 0x084, 2, __NA_, 0, NO_PAD_CTRL) | 115 | #define MX51_PAD_EIM_D26__USBOTG_DATA2 IOMUX_PAD(0x418, 0x084, 2, __NA_, 0, NO_PAD_CTRL) |
| 116 | #define MX51_PAD_EIM_D26__GPT_CMPOUT2 IOMUX_PAD(0x418, 0x084, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 115 | #define MX51_PAD_EIM_D27__AUD6_RXC IOMUX_PAD(0x41c, 0x088, 5, 0x8f4, 0, NO_PAD_CTRL) | 117 | #define MX51_PAD_EIM_D27__AUD6_RXC IOMUX_PAD(0x41c, 0x088, 5, 0x8f4, 0, NO_PAD_CTRL) |
| 116 | #define MX51_PAD_EIM_D27__EIM_D27 IOMUX_PAD(0x41c, 0x088, 0, __NA_, 0, NO_PAD_CTRL) | 118 | #define MX51_PAD_EIM_D27__EIM_D27 IOMUX_PAD(0x41c, 0x088, 0, __NA_, 0, NO_PAD_CTRL) |
| 117 | #define MX51_PAD_EIM_D27__GPIO2_9 IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | 119 | #define MX51_PAD_EIM_D27__GPIO2_9 IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| @@ -228,6 +230,7 @@ | |||
| 228 | #define MX51_PAD_EIM_CRE__EIM_CRE IOMUX_PAD(0x4a0, 0x100, 0, __NA_, 0, NO_PAD_CTRL) | 230 | #define MX51_PAD_EIM_CRE__EIM_CRE IOMUX_PAD(0x4a0, 0x100, 0, __NA_, 0, NO_PAD_CTRL) |
| 229 | #define MX51_PAD_EIM_CRE__GPIO3_2 IOMUX_PAD(0x4a0, 0x100, 1, 0x97c, 0, MX51_GPIO_PAD_CTRL) | 231 | #define MX51_PAD_EIM_CRE__GPIO3_2 IOMUX_PAD(0x4a0, 0x100, 1, 0x97c, 0, MX51_GPIO_PAD_CTRL) |
| 230 | #define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL) | 232 | #define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL) |
| 233 | #define MX51_PAD_DRAM_CS1__CCM_CLKO IOMUX_PAD(0x4d0, 0x104, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 231 | #define MX51_PAD_NANDF_WE_B__GPIO3_3 IOMUX_PAD(0x4e4, 0x108, 3, 0x980, 0, MX51_GPIO_PAD_CTRL) | 234 | #define MX51_PAD_NANDF_WE_B__GPIO3_3 IOMUX_PAD(0x4e4, 0x108, 3, 0x980, 0, MX51_GPIO_PAD_CTRL) |
| 232 | #define MX51_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL) | 235 | #define MX51_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL) |
| 233 | #define MX51_PAD_NANDF_WE_B__PATA_DIOW IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL) | 236 | #define MX51_PAD_NANDF_WE_B__PATA_DIOW IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL) |
| @@ -256,12 +259,14 @@ | |||
| 256 | #define MX51_PAD_NANDF_RB1__GPIO3_9 IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | 259 | #define MX51_PAD_NANDF_RB1__GPIO3_9 IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 257 | #define MX51_PAD_NANDF_RB1__NANDF_RB1 IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL) | 260 | #define MX51_PAD_NANDF_RB1__NANDF_RB1 IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL) |
| 258 | #define MX51_PAD_NANDF_RB1__PATA_IORDY IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL) | 261 | #define MX51_PAD_NANDF_RB1__PATA_IORDY IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL) |
| 262 | #define MX51_PAD_NANDF_RB1__GPT_CMPOUT2 IOMUX_PAD(0x4fc, 0x120, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 259 | #define MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL) | 263 | #define MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL) |
| 260 | #define MX51_PAD_NANDF_RB2__DISP2_WAIT IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL) | 264 | #define MX51_PAD_NANDF_RB2__DISP2_WAIT IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL) |
| 261 | #define MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) | 265 | #define MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) |
| 262 | #define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2) | 266 | #define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2) |
| 263 | #define MX51_PAD_NANDF_RB2__GPIO3_10 IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | 267 | #define MX51_PAD_NANDF_RB2__GPIO3_10 IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 264 | #define MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL) | 268 | #define MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL) |
| 269 | #define MX51_PAD_NANDF_RB2__GPT_CMPOUT3 IOMUX_PAD(0x500, 0x124, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 265 | #define MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 0x17, __NA_, 0, NO_PAD_CTRL) | 270 | #define MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 0x17, __NA_, 0, NO_PAD_CTRL) |
| 266 | #define MX51_PAD_NANDF_RB2__USBH3_NXT IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL) | 271 | #define MX51_PAD_NANDF_RB2__USBH3_NXT IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL) |
| 267 | #define MX51_PAD_NANDF_RB3__DISP1_WAIT IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL) | 272 | #define MX51_PAD_NANDF_RB3__DISP1_WAIT IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL) |
| @@ -637,7 +642,9 @@ | |||
| 637 | #define MX51_PAD_DISP1_DAT23__DISP2_DAT17 IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL) | 642 | #define MX51_PAD_DISP1_DAT23__DISP2_DAT17 IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL) |
| 638 | #define MX51_PAD_DISP1_DAT23__DISP2_SER_CS IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL) | 643 | #define MX51_PAD_DISP1_DAT23__DISP2_SER_CS IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL) |
| 639 | #define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL) | 644 | #define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL) |
| 645 | #define MX51_PAD_DI1_DISP_CLK__DI1_DISP_CLK IOMUX_PAD(0x730, __NA_, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 640 | #define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL) | 646 | #define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL) |
| 647 | #define MX51_PAD_DI1_PIN15__DI1_PIN15 IOMUX_PAD(0x738, __NA_, 0, __NA_, 0, NO_PAD_CTRL) | ||
| 641 | #define MX51_PAD_DI_GP2__DISP1_SER_CLK IOMUX_PAD(0x740, 0x338, 0, __NA_, 0, NO_PAD_CTRL) | 648 | #define MX51_PAD_DI_GP2__DISP1_SER_CLK IOMUX_PAD(0x740, 0x338, 0, __NA_, 0, NO_PAD_CTRL) |
| 642 | #define MX51_PAD_DI_GP2__DISP2_WAIT IOMUX_PAD(0x740, 0x338, 2, 0x9a8, 1, NO_PAD_CTRL) | 649 | #define MX51_PAD_DI_GP2__DISP2_WAIT IOMUX_PAD(0x740, 0x338, 2, 0x9a8, 1, NO_PAD_CTRL) |
| 643 | #define MX51_PAD_DI_GP3__CSI1_DATA_EN IOMUX_PAD(0x744, 0x33c, 3, 0x9a0, 1, NO_PAD_CTRL) | 650 | #define MX51_PAD_DI_GP3__CSI1_DATA_EN IOMUX_PAD(0x744, 0x33c, 3, 0x9a0, 1, NO_PAD_CTRL) |
| @@ -780,6 +787,8 @@ | |||
| 780 | #define MX51_PAD_GPIO1_2__PWM1_PWMO IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL) | 787 | #define MX51_PAD_GPIO1_2__PWM1_PWMO IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL) |
| 781 | #define MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) | 788 | #define MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 782 | #define MX51_PAD_GPIO1_3__I2C2_SDA IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL) | 789 | #define MX51_PAD_GPIO1_3__I2C2_SDA IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL) |
| 790 | #define MX51_PAD_GPIO1_3__CCM_CLKO2 IOMUX_PAD(0x7d8, 0x3d0, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 791 | #define MX51_PAD_GPIO1_3__GPT_CLKIN IOMUX_PAD(0x7d8, 0x3d0, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 783 | #define MX51_PAD_GPIO1_3__PLL2_BYP IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL) | 792 | #define MX51_PAD_GPIO1_3__PLL2_BYP IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL) |
| 784 | #define MX51_PAD_GPIO1_3__PWM2_PWMO IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL) | 793 | #define MX51_PAD_GPIO1_3__PWM2_PWMO IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL) |
| 785 | #define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7fc, 0x3d4, 0, __NA_, 0, NO_PAD_CTRL) | 794 | #define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7fc, 0x3d4, 0, __NA_, 0, NO_PAD_CTRL) |
| @@ -788,13 +797,16 @@ | |||
| 788 | #define MX51_PAD_GPIO1_4__EIM_RDY IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL) | 797 | #define MX51_PAD_GPIO1_4__EIM_RDY IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL) |
| 789 | #define MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) | 798 | #define MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 790 | #define MX51_PAD_GPIO1_4__WDOG1_WDOG_B IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL) | 799 | #define MX51_PAD_GPIO1_4__WDOG1_WDOG_B IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL) |
| 800 | #define MX51_PAD_GPIO1_4__GPT_CAPIN1 IOMUX_PAD(0x804, 0x3d8, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 791 | #define MX51_PAD_GPIO1_5__CSI2_MCLK IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL) | 801 | #define MX51_PAD_GPIO1_5__CSI2_MCLK IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL) |
| 792 | #define MX51_PAD_GPIO1_5__DISP2_PIN16 IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL) | 802 | #define MX51_PAD_GPIO1_5__DISP2_PIN16 IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL) |
| 793 | #define MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) | 803 | #define MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 794 | #define MX51_PAD_GPIO1_5__WDOG2_WDOG_B IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL) | 804 | #define MX51_PAD_GPIO1_5__WDOG2_WDOG_B IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL) |
| 805 | #define MX51_PAD_GPIO1_5__CCM_CLKO IOMUX_PAD(0x808, 0x3dc, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 795 | #define MX51_PAD_GPIO1_6__DISP2_PIN17 IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL) | 806 | #define MX51_PAD_GPIO1_6__DISP2_PIN17 IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL) |
| 796 | #define MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) | 807 | #define MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 797 | #define MX51_PAD_GPIO1_6__REF_EN_B IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL) | 808 | #define MX51_PAD_GPIO1_6__REF_EN_B IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL) |
| 809 | #define MX51_PAD_GPIO1_6__GPT_CAPIN2 IOMUX_PAD(0x80c, 0x3e0, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 798 | #define MX51_PAD_GPIO1_7__CCM_OUT_0 IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL) | 810 | #define MX51_PAD_GPIO1_7__CCM_OUT_0 IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL) |
| 799 | #define MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) | 811 | #define MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 800 | #define MX51_PAD_GPIO1_7__SD2_WP IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) | 812 | #define MX51_PAD_GPIO1_7__SD2_WP IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) |
| @@ -803,11 +815,13 @@ | |||
| 803 | #define MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) | 815 | #define MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 804 | #define MX51_PAD_GPIO1_8__SD2_CD IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) | 816 | #define MX51_PAD_GPIO1_8__SD2_CD IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) |
| 805 | #define MX51_PAD_GPIO1_8__USBH3_PWR IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL) | 817 | #define MX51_PAD_GPIO1_8__USBH3_PWR IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL) |
| 818 | #define MX51_PAD_GPIO1_8__CCM_CLKO2 IOMUX_PAD(0x814, 0x3e8, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 806 | #define MX51_PAD_GPIO1_9__CCM_OUT_1 IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL) | 819 | #define MX51_PAD_GPIO1_9__CCM_OUT_1 IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL) |
| 807 | #define MX51_PAD_GPIO1_9__DISP2_D1_CS IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL) | 820 | #define MX51_PAD_GPIO1_9__DISP2_D1_CS IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL) |
| 808 | #define MX51_PAD_GPIO1_9__DISP2_SER_CS IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL) | 821 | #define MX51_PAD_GPIO1_9__DISP2_SER_CS IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL) |
| 809 | #define MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) | 822 | #define MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 810 | #define MX51_PAD_GPIO1_9__SD2_LCTL IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL) | 823 | #define MX51_PAD_GPIO1_9__SD2_LCTL IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL) |
| 811 | #define MX51_PAD_GPIO1_9__USBH3_OC IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL) | 824 | #define MX51_PAD_GPIO1_9__USBH3_OC IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL) |
| 825 | #define MX51_PAD_GPIO1_9__CCM_CLKO IOMUX_PAD(0x818, 0x3ec, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 812 | 826 | ||
| 813 | #endif /* __MACH_IOMUX_MX51_H__ */ | 827 | #endif /* __MACH_IOMUX_MX51_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h index 9ffd1bbe615f..7eb9d1329671 100644 --- a/arch/arm/plat-mxc/include/mach/mxc_ehci.h +++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h | |||
| @@ -20,13 +20,15 @@ | |||
| 20 | #define MXC_EHCI_INTERFACE_MASK (0xf) | 20 | #define MXC_EHCI_INTERFACE_MASK (0xf) |
| 21 | 21 | ||
| 22 | #define MXC_EHCI_POWER_PINS_ENABLED (1 << 5) | 22 | #define MXC_EHCI_POWER_PINS_ENABLED (1 << 5) |
| 23 | #define MXC_EHCI_TTL_ENABLED (1 << 6) | 23 | #define MXC_EHCI_PWR_PIN_ACTIVE_HIGH (1 << 6) |
| 24 | 24 | #define MXC_EHCI_OC_PIN_ACTIVE_LOW (1 << 7) | |
| 25 | #define MXC_EHCI_INTERNAL_PHY (1 << 7) | 25 | #define MXC_EHCI_TTL_ENABLED (1 << 8) |
| 26 | #define MXC_EHCI_IPPUE_DOWN (1 << 8) | 26 | |
| 27 | #define MXC_EHCI_IPPUE_UP (1 << 9) | 27 | #define MXC_EHCI_INTERNAL_PHY (1 << 9) |
| 28 | #define MXC_EHCI_WAKEUP_ENABLED (1 << 10) | 28 | #define MXC_EHCI_IPPUE_DOWN (1 << 10) |
| 29 | #define MXC_EHCI_ITC_NO_THRESHOLD (1 << 11) | 29 | #define MXC_EHCI_IPPUE_UP (1 << 11) |
| 30 | #define MXC_EHCI_WAKEUP_ENABLED (1 << 12) | ||
| 31 | #define MXC_EHCI_ITC_NO_THRESHOLD (1 << 13) | ||
| 30 | 32 | ||
| 31 | #define MXC_USBCTRL_OFFSET 0 | 33 | #define MXC_USBCTRL_OFFSET 0 |
| 32 | #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 | 34 | #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 |
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index ed8605f01155..6d87532871cd 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile | |||
| @@ -4,7 +4,7 @@ | |||
| 4 | 4 | ||
| 5 | # Common support | 5 | # Common support |
| 6 | obj-y := common.o sram.o clock.o devices.o dma.o mux.o \ | 6 | obj-y := common.o sram.o clock.o devices.o dma.o mux.o \ |
| 7 | usb.o fb.o counter_32k.o | 7 | fb.o counter_32k.o |
| 8 | obj-m := | 8 | obj-m := |
| 9 | obj-n := | 9 | obj-n := |
| 10 | obj- := | 10 | obj- := |
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index cb16ade437cb..7fe626761e53 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c | |||
| @@ -573,22 +573,25 @@ EXPORT_SYMBOL(omap_set_dma_dest_burst_mode); | |||
| 573 | 573 | ||
| 574 | static inline void omap_enable_channel_irq(int lch) | 574 | static inline void omap_enable_channel_irq(int lch) |
| 575 | { | 575 | { |
| 576 | u32 status; | ||
| 577 | |||
| 578 | /* Clear CSR */ | 576 | /* Clear CSR */ |
| 579 | if (cpu_class_is_omap1()) | 577 | if (cpu_class_is_omap1()) |
| 580 | status = p->dma_read(CSR, lch); | 578 | p->dma_read(CSR, lch); |
| 581 | else if (cpu_class_is_omap2()) | 579 | else |
| 582 | p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); | 580 | p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); |
| 583 | 581 | ||
| 584 | /* Enable some nice interrupts. */ | 582 | /* Enable some nice interrupts. */ |
| 585 | p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch); | 583 | p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch); |
| 586 | } | 584 | } |
| 587 | 585 | ||
| 588 | static void omap_disable_channel_irq(int lch) | 586 | static inline void omap_disable_channel_irq(int lch) |
| 589 | { | 587 | { |
| 590 | if (cpu_class_is_omap2()) | 588 | /* disable channel interrupts */ |
| 591 | p->dma_write(0, CICR, lch); | 589 | p->dma_write(0, CICR, lch); |
| 590 | /* Clear CSR */ | ||
| 591 | if (cpu_class_is_omap1()) | ||
| 592 | p->dma_read(CSR, lch); | ||
| 593 | else | ||
| 594 | p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); | ||
| 592 | } | 595 | } |
| 593 | 596 | ||
| 594 | void omap_enable_dma_irq(int lch, u16 bits) | 597 | void omap_enable_dma_irq(int lch, u16 bits) |
| @@ -632,14 +635,14 @@ static inline void disable_lnk(int lch) | |||
| 632 | l = p->dma_read(CLNK_CTRL, lch); | 635 | l = p->dma_read(CLNK_CTRL, lch); |
| 633 | 636 | ||
| 634 | /* Disable interrupts */ | 637 | /* Disable interrupts */ |
| 638 | omap_disable_channel_irq(lch); | ||
| 639 | |||
| 635 | if (cpu_class_is_omap1()) { | 640 | if (cpu_class_is_omap1()) { |
| 636 | p->dma_write(0, CICR, lch); | ||
| 637 | /* Set the STOP_LNK bit */ | 641 | /* Set the STOP_LNK bit */ |
| 638 | l |= 1 << 14; | 642 | l |= 1 << 14; |
| 639 | } | 643 | } |
| 640 | 644 | ||
| 641 | if (cpu_class_is_omap2()) { | 645 | if (cpu_class_is_omap2()) { |
| 642 | omap_disable_channel_irq(lch); | ||
| 643 | /* Clear the ENABLE_LNK bit */ | 646 | /* Clear the ENABLE_LNK bit */ |
| 644 | l &= ~(1 << 15); | 647 | l &= ~(1 << 15); |
| 645 | } | 648 | } |
| @@ -657,6 +660,9 @@ static inline void omap2_enable_irq_lch(int lch) | |||
| 657 | return; | 660 | return; |
| 658 | 661 | ||
| 659 | spin_lock_irqsave(&dma_chan_lock, flags); | 662 | spin_lock_irqsave(&dma_chan_lock, flags); |
| 663 | /* clear IRQ STATUS */ | ||
| 664 | p->dma_write(1 << lch, IRQSTATUS_L0, lch); | ||
| 665 | /* Enable interrupt */ | ||
| 660 | val = p->dma_read(IRQENABLE_L0, lch); | 666 | val = p->dma_read(IRQENABLE_L0, lch); |
| 661 | val |= 1 << lch; | 667 | val |= 1 << lch; |
| 662 | p->dma_write(val, IRQENABLE_L0, lch); | 668 | p->dma_write(val, IRQENABLE_L0, lch); |
| @@ -672,9 +678,12 @@ static inline void omap2_disable_irq_lch(int lch) | |||
| 672 | return; | 678 | return; |
| 673 | 679 | ||
| 674 | spin_lock_irqsave(&dma_chan_lock, flags); | 680 | spin_lock_irqsave(&dma_chan_lock, flags); |
| 681 | /* Disable interrupt */ | ||
| 675 | val = p->dma_read(IRQENABLE_L0, lch); | 682 | val = p->dma_read(IRQENABLE_L0, lch); |
| 676 | val &= ~(1 << lch); | 683 | val &= ~(1 << lch); |
| 677 | p->dma_write(val, IRQENABLE_L0, lch); | 684 | p->dma_write(val, IRQENABLE_L0, lch); |
| 685 | /* clear IRQ STATUS */ | ||
| 686 | p->dma_write(1 << lch, IRQSTATUS_L0, lch); | ||
| 678 | spin_unlock_irqrestore(&dma_chan_lock, flags); | 687 | spin_unlock_irqrestore(&dma_chan_lock, flags); |
| 679 | } | 688 | } |
| 680 | 689 | ||
| @@ -745,11 +754,8 @@ int omap_request_dma(int dev_id, const char *dev_name, | |||
| 745 | } | 754 | } |
| 746 | 755 | ||
| 747 | if (cpu_class_is_omap2()) { | 756 | if (cpu_class_is_omap2()) { |
| 748 | omap2_enable_irq_lch(free_ch); | ||
| 749 | omap_enable_channel_irq(free_ch); | 757 | omap_enable_channel_irq(free_ch); |
| 750 | /* Clear the CSR register and IRQ status register */ | 758 | omap2_enable_irq_lch(free_ch); |
| 751 | p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, free_ch); | ||
| 752 | p->dma_write(1 << free_ch, IRQSTATUS_L0, 0); | ||
| 753 | } | 759 | } |
| 754 | 760 | ||
| 755 | *dma_ch_out = free_ch; | 761 | *dma_ch_out = free_ch; |
| @@ -768,27 +774,19 @@ void omap_free_dma(int lch) | |||
| 768 | return; | 774 | return; |
| 769 | } | 775 | } |
| 770 | 776 | ||
| 771 | if (cpu_class_is_omap1()) { | 777 | /* Disable interrupt for logical channel */ |
| 772 | /* Disable all DMA interrupts for the channel. */ | 778 | if (cpu_class_is_omap2()) |
| 773 | p->dma_write(0, CICR, lch); | ||
| 774 | /* Make sure the DMA transfer is stopped. */ | ||
| 775 | p->dma_write(0, CCR, lch); | ||
| 776 | } | ||
| 777 | |||
| 778 | if (cpu_class_is_omap2()) { | ||
| 779 | omap2_disable_irq_lch(lch); | 779 | omap2_disable_irq_lch(lch); |
| 780 | 780 | ||
| 781 | /* Clear the CSR register and IRQ status register */ | 781 | /* Disable all DMA interrupts for the channel. */ |
| 782 | p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); | 782 | omap_disable_channel_irq(lch); |
| 783 | p->dma_write(1 << lch, IRQSTATUS_L0, lch); | ||
| 784 | 783 | ||
| 785 | /* Disable all DMA interrupts for the channel. */ | 784 | /* Make sure the DMA transfer is stopped. */ |
| 786 | p->dma_write(0, CICR, lch); | 785 | p->dma_write(0, CCR, lch); |
| 787 | 786 | ||
| 788 | /* Make sure the DMA transfer is stopped. */ | 787 | /* Clear registers */ |
| 789 | p->dma_write(0, CCR, lch); | 788 | if (cpu_class_is_omap2()) |
| 790 | omap_clear_dma(lch); | 789 | omap_clear_dma(lch); |
| 791 | } | ||
| 792 | 790 | ||
| 793 | spin_lock_irqsave(&dma_chan_lock, flags); | 791 | spin_lock_irqsave(&dma_chan_lock, flags); |
| 794 | dma_chan[lch].dev_id = -1; | 792 | dma_chan[lch].dev_id = -1; |
| @@ -943,8 +941,7 @@ void omap_stop_dma(int lch) | |||
| 943 | u32 l; | 941 | u32 l; |
| 944 | 942 | ||
| 945 | /* Disable all interrupts on the channel */ | 943 | /* Disable all interrupts on the channel */ |
| 946 | if (cpu_class_is_omap1()) | 944 | omap_disable_channel_irq(lch); |
| 947 | p->dma_write(0, CICR, lch); | ||
| 948 | 945 | ||
| 949 | l = p->dma_read(CCR, lch); | 946 | l = p->dma_read(CCR, lch); |
| 950 | if (IS_DMA_ERRATA(DMA_ERRATA_i541) && | 947 | if (IS_DMA_ERRATA(DMA_ERRATA_i541) && |
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h index 4814c5b65306..e62f20a5c0af 100644 --- a/arch/arm/plat-omap/include/plat/board.h +++ b/arch/arm/plat-omap/include/plat/board.h | |||
| @@ -57,44 +57,6 @@ struct omap_camera_sensor_config { | |||
| 57 | int (*power_off)(void * data); | 57 | int (*power_off)(void * data); |
| 58 | }; | 58 | }; |
| 59 | 59 | ||
| 60 | struct omap_usb_config { | ||
| 61 | /* Configure drivers according to the connectors on your board: | ||
| 62 | * - "A" connector (rectagular) | ||
| 63 | * ... for host/OHCI use, set "register_host". | ||
| 64 | * - "B" connector (squarish) or "Mini-B" | ||
| 65 | * ... for device/gadget use, set "register_dev". | ||
| 66 | * - "Mini-AB" connector (very similar to Mini-B) | ||
| 67 | * ... for OTG use as device OR host, initialize "otg" | ||
| 68 | */ | ||
| 69 | unsigned register_host:1; | ||
| 70 | unsigned register_dev:1; | ||
| 71 | u8 otg; /* port number, 1-based: usb1 == 2 */ | ||
| 72 | |||
| 73 | u8 hmc_mode; | ||
| 74 | |||
| 75 | /* implicitly true if otg: host supports remote wakeup? */ | ||
| 76 | u8 rwc; | ||
| 77 | |||
| 78 | /* signaling pins used to talk to transceiver on usbN: | ||
| 79 | * 0 == usbN unused | ||
| 80 | * 2 == usb0-only, using internal transceiver | ||
| 81 | * 3 == 3 wire bidirectional | ||
| 82 | * 4 == 4 wire bidirectional | ||
| 83 | * 6 == 6 wire unidirectional (or TLL) | ||
| 84 | */ | ||
| 85 | u8 pins[3]; | ||
| 86 | |||
| 87 | struct platform_device *udc_device; | ||
| 88 | struct platform_device *ohci_device; | ||
| 89 | struct platform_device *otg_device; | ||
| 90 | |||
| 91 | u32 (*usb0_init)(unsigned nwires, unsigned is_device); | ||
| 92 | u32 (*usb1_init)(unsigned nwires); | ||
| 93 | u32 (*usb2_init)(unsigned nwires, unsigned alt_pingroup); | ||
| 94 | |||
| 95 | int (*ocpi_enable)(void); | ||
| 96 | }; | ||
| 97 | |||
| 98 | struct omap_lcd_config { | 60 | struct omap_lcd_config { |
| 99 | char panel_name[16]; | 61 | char panel_name[16]; |
| 100 | char ctrl_name[16]; | 62 | char ctrl_name[16]; |
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index d0ef57c1d71b..656b9862279e 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h | |||
| @@ -156,7 +156,6 @@ struct dpll_data { | |||
| 156 | u8 min_divider; | 156 | u8 min_divider; |
| 157 | u16 max_divider; | 157 | u16 max_divider; |
| 158 | u8 modes; | 158 | u8 modes; |
| 159 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) | ||
| 160 | void __iomem *autoidle_reg; | 159 | void __iomem *autoidle_reg; |
| 161 | void __iomem *idlest_reg; | 160 | void __iomem *idlest_reg; |
| 162 | u32 autoidle_mask; | 161 | u32 autoidle_mask; |
| @@ -167,7 +166,6 @@ struct dpll_data { | |||
| 167 | u8 auto_recal_bit; | 166 | u8 auto_recal_bit; |
| 168 | u8 recal_en_bit; | 167 | u8 recal_en_bit; |
| 169 | u8 recal_st_bit; | 168 | u8 recal_st_bit; |
| 170 | # endif | ||
| 171 | u8 flags; | 169 | u8 flags; |
| 172 | }; | 170 | }; |
| 173 | 171 | ||
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index de6c0a08f461..430081ac0c47 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h | |||
| @@ -238,9 +238,7 @@ IS_AM_SUBCLASS(335x, 0x335) | |||
| 238 | /* | 238 | /* |
| 239 | * Macros to detect individual cpu types. | 239 | * Macros to detect individual cpu types. |
| 240 | * These are only rarely needed. | 240 | * These are only rarely needed. |
| 241 | * cpu_is_omap330(): True for OMAP330 | 241 | * cpu_is_omap310(): True for OMAP310 |
| 242 | * cpu_is_omap730(): True for OMAP730 | ||
| 243 | * cpu_is_omap850(): True for OMAP850 | ||
| 244 | * cpu_is_omap1510(): True for OMAP1510 | 242 | * cpu_is_omap1510(): True for OMAP1510 |
| 245 | * cpu_is_omap1610(): True for OMAP1610 | 243 | * cpu_is_omap1610(): True for OMAP1610 |
| 246 | * cpu_is_omap1611(): True for OMAP1611 | 244 | * cpu_is_omap1611(): True for OMAP1611 |
| @@ -262,8 +260,6 @@ static inline int is_omap ##type (void) \ | |||
| 262 | } | 260 | } |
| 263 | 261 | ||
| 264 | IS_OMAP_TYPE(310, 0x0310) | 262 | IS_OMAP_TYPE(310, 0x0310) |
| 265 | IS_OMAP_TYPE(730, 0x0730) | ||
| 266 | IS_OMAP_TYPE(850, 0x0850) | ||
| 267 | IS_OMAP_TYPE(1510, 0x1510) | 263 | IS_OMAP_TYPE(1510, 0x1510) |
| 268 | IS_OMAP_TYPE(1610, 0x1610) | 264 | IS_OMAP_TYPE(1610, 0x1610) |
| 269 | IS_OMAP_TYPE(1611, 0x1611) | 265 | IS_OMAP_TYPE(1611, 0x1611) |
| @@ -277,8 +273,6 @@ IS_OMAP_TYPE(2430, 0x2430) | |||
| 277 | IS_OMAP_TYPE(3430, 0x3430) | 273 | IS_OMAP_TYPE(3430, 0x3430) |
| 278 | 274 | ||
| 279 | #define cpu_is_omap310() 0 | 275 | #define cpu_is_omap310() 0 |
| 280 | #define cpu_is_omap730() 0 | ||
| 281 | #define cpu_is_omap850() 0 | ||
| 282 | #define cpu_is_omap1510() 0 | 276 | #define cpu_is_omap1510() 0 |
| 283 | #define cpu_is_omap1610() 0 | 277 | #define cpu_is_omap1610() 0 |
| 284 | #define cpu_is_omap5912() 0 | 278 | #define cpu_is_omap5912() 0 |
| @@ -294,19 +288,9 @@ IS_OMAP_TYPE(3430, 0x3430) | |||
| 294 | 288 | ||
| 295 | /* | 289 | /* |
| 296 | * Whether we have MULTI_OMAP1 or not, we still need to distinguish | 290 | * Whether we have MULTI_OMAP1 or not, we still need to distinguish |
| 297 | * between 730 vs 850, 330 vs. 1510 and 1611B/5912 vs. 1710. | 291 | * between 310 vs. 1510 and 1611B/5912 vs. 1710. |
| 298 | */ | 292 | */ |
| 299 | 293 | ||
| 300 | #if defined(CONFIG_ARCH_OMAP730) | ||
| 301 | # undef cpu_is_omap730 | ||
| 302 | # define cpu_is_omap730() is_omap730() | ||
| 303 | #endif | ||
| 304 | |||
| 305 | #if defined(CONFIG_ARCH_OMAP850) | ||
| 306 | # undef cpu_is_omap850 | ||
| 307 | # define cpu_is_omap850() is_omap850() | ||
| 308 | #endif | ||
| 309 | |||
| 310 | #if defined(CONFIG_ARCH_OMAP15XX) | 294 | #if defined(CONFIG_ARCH_OMAP15XX) |
| 311 | # undef cpu_is_omap310 | 295 | # undef cpu_is_omap310 |
| 312 | # undef cpu_is_omap1510 | 296 | # undef cpu_is_omap1510 |
diff --git a/arch/arm/plat-omap/include/plat/dsp.h b/arch/arm/plat-omap/include/plat/dsp.h index 9c604b390f9f..5927709b1908 100644 --- a/arch/arm/plat-omap/include/plat/dsp.h +++ b/arch/arm/plat-omap/include/plat/dsp.h | |||
| @@ -18,6 +18,9 @@ struct omap_dsp_platform_data { | |||
| 18 | u32 (*dsp_cm_read)(s16 , u16); | 18 | u32 (*dsp_cm_read)(s16 , u16); |
| 19 | u32 (*dsp_cm_rmw_bits)(u32, u32, s16, s16); | 19 | u32 (*dsp_cm_rmw_bits)(u32, u32, s16, s16); |
| 20 | 20 | ||
| 21 | void (*set_bootaddr)(u32); | ||
| 22 | void (*set_bootmode)(u8); | ||
| 23 | |||
| 21 | phys_addr_t phys_mempool_base; | 24 | phys_addr_t phys_mempool_base; |
| 22 | phys_addr_t phys_mempool_size; | 25 | phys_addr_t phys_mempool_size; |
| 23 | }; | 26 | }; |
diff --git a/arch/arm/plat-omap/include/plat/mux.h b/arch/arm/plat-omap/include/plat/mux.h index aeba71796ad9..323948959200 100644 --- a/arch/arm/plat-omap/include/plat/mux.h +++ b/arch/arm/plat-omap/include/plat/mux.h | |||
| @@ -99,7 +99,7 @@ | |||
| 99 | 99 | ||
| 100 | /* | 100 | /* |
| 101 | * OMAP730/850 has a slightly different config for the pin mux. | 101 | * OMAP730/850 has a slightly different config for the pin mux. |
| 102 | * - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and | 102 | * - config regs are the OMAP7XX_IO_CONF_x regs (see omap7xx.h) regs and |
| 103 | * not the FUNC_MUX_CTRL_x regs from hardware.h | 103 | * not the FUNC_MUX_CTRL_x regs from hardware.h |
| 104 | * - for pull-up/down, only has one enable bit which is is in the same register | 104 | * - for pull-up/down, only has one enable bit which is is in the same register |
| 105 | * as mux config | 105 | * as mux config |
diff --git a/arch/arm/plat-omap/include/plat/omap730.h b/arch/arm/plat-omap/include/plat/omap730.h deleted file mode 100644 index 14272bc1a6fd..000000000000 --- a/arch/arm/plat-omap/include/plat/omap730.h +++ /dev/null | |||
| @@ -1,102 +0,0 @@ | |||
| 1 | /* arch/arm/plat-omap/include/mach/omap730.h | ||
| 2 | * | ||
| 3 | * Hardware definitions for TI OMAP730 processor. | ||
| 4 | * | ||
| 5 | * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License as published by the | ||
| 9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 10 | * option) any later version. | ||
| 11 | * | ||
| 12 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 13 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 14 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 15 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 16 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 17 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 18 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 19 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 20 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 21 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 22 | * | ||
| 23 | * You should have received a copy of the GNU General Public License along | ||
| 24 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 25 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 26 | */ | ||
| 27 | |||
| 28 | #ifndef __ASM_ARCH_OMAP730_H | ||
| 29 | #define __ASM_ARCH_OMAP730_H | ||
| 30 | |||
| 31 | /* | ||
| 32 | * ---------------------------------------------------------------------------- | ||
| 33 | * Base addresses | ||
| 34 | * ---------------------------------------------------------------------------- | ||
| 35 | */ | ||
| 36 | |||
| 37 | /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ | ||
| 38 | |||
| 39 | #define OMAP730_DSP_BASE 0xE0000000 | ||
| 40 | #define OMAP730_DSP_SIZE 0x50000 | ||
| 41 | #define OMAP730_DSP_START 0xE0000000 | ||
| 42 | |||
| 43 | #define OMAP730_DSPREG_BASE 0xE1000000 | ||
| 44 | #define OMAP730_DSPREG_SIZE SZ_128K | ||
| 45 | #define OMAP730_DSPREG_START 0xE1000000 | ||
| 46 | |||
| 47 | /* | ||
| 48 | * ---------------------------------------------------------------------------- | ||
| 49 | * OMAP730 specific configuration registers | ||
| 50 | * ---------------------------------------------------------------------------- | ||
| 51 | */ | ||
| 52 | #define OMAP730_CONFIG_BASE 0xfffe1000 | ||
| 53 | #define OMAP730_IO_CONF_0 0xfffe1070 | ||
| 54 | #define OMAP730_IO_CONF_1 0xfffe1074 | ||
| 55 | #define OMAP730_IO_CONF_2 0xfffe1078 | ||
| 56 | #define OMAP730_IO_CONF_3 0xfffe107c | ||
| 57 | #define OMAP730_IO_CONF_4 0xfffe1080 | ||
| 58 | #define OMAP730_IO_CONF_5 0xfffe1084 | ||
| 59 | #define OMAP730_IO_CONF_6 0xfffe1088 | ||
| 60 | #define OMAP730_IO_CONF_7 0xfffe108c | ||
| 61 | #define OMAP730_IO_CONF_8 0xfffe1090 | ||
| 62 | #define OMAP730_IO_CONF_9 0xfffe1094 | ||
| 63 | #define OMAP730_IO_CONF_10 0xfffe1098 | ||
| 64 | #define OMAP730_IO_CONF_11 0xfffe109c | ||
| 65 | #define OMAP730_IO_CONF_12 0xfffe10a0 | ||
| 66 | #define OMAP730_IO_CONF_13 0xfffe10a4 | ||
| 67 | |||
| 68 | #define OMAP730_MODE_1 0xfffe1010 | ||
| 69 | #define OMAP730_MODE_2 0xfffe1014 | ||
| 70 | |||
| 71 | /* CSMI specials: in terms of base + offset */ | ||
| 72 | #define OMAP730_MODE2_OFFSET 0x14 | ||
| 73 | |||
| 74 | /* | ||
| 75 | * ---------------------------------------------------------------------------- | ||
| 76 | * OMAP730 traffic controller configuration registers | ||
| 77 | * ---------------------------------------------------------------------------- | ||
| 78 | */ | ||
| 79 | #define OMAP730_FLASH_CFG_0 0xfffecc10 | ||
| 80 | #define OMAP730_FLASH_ACFG_0 0xfffecc50 | ||
| 81 | #define OMAP730_FLASH_CFG_1 0xfffecc14 | ||
| 82 | #define OMAP730_FLASH_ACFG_1 0xfffecc54 | ||
| 83 | |||
| 84 | /* | ||
| 85 | * ---------------------------------------------------------------------------- | ||
| 86 | * OMAP730 DSP control registers | ||
| 87 | * ---------------------------------------------------------------------------- | ||
| 88 | */ | ||
| 89 | #define OMAP730_ICR_BASE 0xfffbb800 | ||
| 90 | #define OMAP730_DSP_M_CTL 0xfffbb804 | ||
| 91 | #define OMAP730_DSP_MMU_BASE 0xfffed200 | ||
| 92 | |||
| 93 | /* | ||
| 94 | * ---------------------------------------------------------------------------- | ||
| 95 | * OMAP730 PCC_UPLD configuration registers | ||
| 96 | * ---------------------------------------------------------------------------- | ||
| 97 | */ | ||
| 98 | #define OMAP730_PCC_UPLD_CTRL_BASE (0xfffe0900) | ||
| 99 | #define OMAP730_PCC_UPLD_CTRL (OMAP730_PCC_UPLD_CTRL_BASE + 0x00) | ||
| 100 | |||
| 101 | #endif /* __ASM_ARCH_OMAP730_H */ | ||
| 102 | |||
diff --git a/arch/arm/plat-omap/include/plat/omap850.h b/arch/arm/plat-omap/include/plat/omap850.h deleted file mode 100644 index c33f67981712..000000000000 --- a/arch/arm/plat-omap/include/plat/omap850.h +++ /dev/null | |||
| @@ -1,102 +0,0 @@ | |||
| 1 | /* arch/arm/plat-omap/include/mach/omap850.h | ||
| 2 | * | ||
| 3 | * Hardware definitions for TI OMAP850 processor. | ||
| 4 | * | ||
| 5 | * Derived from omap730.h by Zebediah C. McClure <zmc@lurian.net> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License as published by the | ||
| 9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 10 | * option) any later version. | ||
| 11 | * | ||
| 12 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 13 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 14 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 15 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 16 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 17 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 18 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 19 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 20 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 21 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 22 | * | ||
| 23 | * You should have received a copy of the GNU General Public License along | ||
| 24 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 25 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 26 | */ | ||
| 27 | |||
| 28 | #ifndef __ASM_ARCH_OMAP850_H | ||
| 29 | #define __ASM_ARCH_OMAP850_H | ||
| 30 | |||
| 31 | /* | ||
| 32 | * ---------------------------------------------------------------------------- | ||
| 33 | * Base addresses | ||
| 34 | * ---------------------------------------------------------------------------- | ||
| 35 | */ | ||
| 36 | |||
| 37 | /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ | ||
| 38 | |||
| 39 | #define OMAP850_DSP_BASE 0xE0000000 | ||
| 40 | #define OMAP850_DSP_SIZE 0x50000 | ||
| 41 | #define OMAP850_DSP_START 0xE0000000 | ||
| 42 | |||
| 43 | #define OMAP850_DSPREG_BASE 0xE1000000 | ||
| 44 | #define OMAP850_DSPREG_SIZE SZ_128K | ||
| 45 | #define OMAP850_DSPREG_START 0xE1000000 | ||
| 46 | |||
| 47 | /* | ||
| 48 | * ---------------------------------------------------------------------------- | ||
| 49 | * OMAP850 specific configuration registers | ||
| 50 | * ---------------------------------------------------------------------------- | ||
| 51 | */ | ||
| 52 | #define OMAP850_CONFIG_BASE 0xfffe1000 | ||
| 53 | #define OMAP850_IO_CONF_0 0xfffe1070 | ||
| 54 | #define OMAP850_IO_CONF_1 0xfffe1074 | ||
| 55 | #define OMAP850_IO_CONF_2 0xfffe1078 | ||
| 56 | #define OMAP850_IO_CONF_3 0xfffe107c | ||
| 57 | #define OMAP850_IO_CONF_4 0xfffe1080 | ||
| 58 | #define OMAP850_IO_CONF_5 0xfffe1084 | ||
| 59 | #define OMAP850_IO_CONF_6 0xfffe1088 | ||
| 60 | #define OMAP850_IO_CONF_7 0xfffe108c | ||
| 61 | #define OMAP850_IO_CONF_8 0xfffe1090 | ||
| 62 | #define OMAP850_IO_CONF_9 0xfffe1094 | ||
| 63 | #define OMAP850_IO_CONF_10 0xfffe1098 | ||
| 64 | #define OMAP850_IO_CONF_11 0xfffe109c | ||
| 65 | #define OMAP850_IO_CONF_12 0xfffe10a0 | ||
| 66 | #define OMAP850_IO_CONF_13 0xfffe10a4 | ||
| 67 | |||
| 68 | #define OMAP850_MODE_1 0xfffe1010 | ||
| 69 | #define OMAP850_MODE_2 0xfffe1014 | ||
| 70 | |||
| 71 | /* CSMI specials: in terms of base + offset */ | ||
| 72 | #define OMAP850_MODE2_OFFSET 0x14 | ||
| 73 | |||
| 74 | /* | ||
| 75 | * ---------------------------------------------------------------------------- | ||
| 76 | * OMAP850 traffic controller configuration registers | ||
| 77 | * ---------------------------------------------------------------------------- | ||
| 78 | */ | ||
| 79 | #define OMAP850_FLASH_CFG_0 0xfffecc10 | ||
| 80 | #define OMAP850_FLASH_ACFG_0 0xfffecc50 | ||
| 81 | #define OMAP850_FLASH_CFG_1 0xfffecc14 | ||
| 82 | #define OMAP850_FLASH_ACFG_1 0xfffecc54 | ||
| 83 | |||
| 84 | /* | ||
| 85 | * ---------------------------------------------------------------------------- | ||
| 86 | * OMAP850 DSP control registers | ||
| 87 | * ---------------------------------------------------------------------------- | ||
| 88 | */ | ||
| 89 | #define OMAP850_ICR_BASE 0xfffbb800 | ||
| 90 | #define OMAP850_DSP_M_CTL 0xfffbb804 | ||
| 91 | #define OMAP850_DSP_MMU_BASE 0xfffed200 | ||
| 92 | |||
| 93 | /* | ||
| 94 | * ---------------------------------------------------------------------------- | ||
| 95 | * OMAP850 PCC_UPLD configuration registers | ||
| 96 | * ---------------------------------------------------------------------------- | ||
| 97 | */ | ||
| 98 | #define OMAP850_PCC_UPLD_CTRL_BASE (0xfffe0900) | ||
| 99 | #define OMAP850_PCC_UPLD_CTRL (OMAP850_PCC_UPLD_CTRL_BASE + 0x00) | ||
| 100 | |||
| 101 | #endif /* __ASM_ARCH_OMAP850_H */ | ||
| 102 | |||
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index c835b7194ff5..a8ecc53b3670 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h | |||
| @@ -629,6 +629,8 @@ int omap_hwmod_no_setup_reset(struct omap_hwmod *oh); | |||
| 629 | 629 | ||
| 630 | int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx); | 630 | int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx); |
| 631 | 631 | ||
| 632 | extern void __init omap_hwmod_init(void); | ||
| 633 | |||
| 632 | /* | 634 | /* |
| 633 | * Chip variant-specific hwmod init routines - XXX should be converted | 635 | * Chip variant-specific hwmod init routines - XXX should be converted |
| 634 | * to use initcalls once the initial boot ordering is straightened out | 636 | * to use initcalls once the initial boot ordering is straightened out |
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h index b073e5f2b190..28e2d250c2fd 100644 --- a/arch/arm/plat-omap/include/plat/serial.h +++ b/arch/arm/plat-omap/include/plat/serial.h | |||
| @@ -60,6 +60,9 @@ | |||
| 60 | /* AM3505/3517 UART4 */ | 60 | /* AM3505/3517 UART4 */ |
| 61 | #define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */ | 61 | #define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */ |
| 62 | 62 | ||
| 63 | /* AM33XX serial port */ | ||
| 64 | #define AM33XX_UART1_BASE 0x44E09000 | ||
| 65 | |||
| 63 | /* External port on Zoom2/3 */ | 66 | /* External port on Zoom2/3 */ |
| 64 | #define ZOOM_UART_BASE 0x10000000 | 67 | #define ZOOM_UART_BASE 0x10000000 |
| 65 | #define ZOOM_UART_VIRT 0xfa400000 | 68 | #define ZOOM_UART_VIRT 0xfa400000 |
| @@ -93,6 +96,7 @@ | |||
| 93 | #define TI81XXUART1 81 | 96 | #define TI81XXUART1 81 |
| 94 | #define TI81XXUART2 82 | 97 | #define TI81XXUART2 82 |
| 95 | #define TI81XXUART3 83 | 98 | #define TI81XXUART3 83 |
| 99 | #define AM33XXUART1 84 | ||
| 96 | #define ZOOM_UART 95 /* Only on zoom2/3 */ | 100 | #define ZOOM_UART 95 /* Only on zoom2/3 */ |
| 97 | 101 | ||
| 98 | /* This is only used by 8250.c for omap1510 */ | 102 | /* This is only used by 8250.c for omap1510 */ |
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h index cc3f11ba7a99..ac4323390213 100644 --- a/arch/arm/plat-omap/include/plat/uncompress.h +++ b/arch/arm/plat-omap/include/plat/uncompress.h | |||
| @@ -103,6 +103,10 @@ static inline void flush(void) | |||
| 103 | _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT, \ | 103 | _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT, \ |
| 104 | TI81XXUART##p) | 104 | TI81XXUART##p) |
| 105 | 105 | ||
| 106 | #define DEBUG_LL_AM33XX(p, mach) \ | ||
| 107 | _DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT, \ | ||
| 108 | AM33XXUART##p) | ||
| 109 | |||
| 106 | static inline void __arch_decomp_setup(unsigned long arch_id) | 110 | static inline void __arch_decomp_setup(unsigned long arch_id) |
| 107 | { | 111 | { |
| 108 | int port = 0; | 112 | int port = 0; |
| @@ -183,6 +187,8 @@ static inline void __arch_decomp_setup(unsigned long arch_id) | |||
| 183 | /* TI8148 base boards using UART1 */ | 187 | /* TI8148 base boards using UART1 */ |
| 184 | DEBUG_LL_TI81XX(1, ti8148evm); | 188 | DEBUG_LL_TI81XX(1, ti8148evm); |
| 185 | 189 | ||
| 190 | /* AM33XX base boards using UART1 */ | ||
| 191 | DEBUG_LL_AM33XX(1, am335xevm); | ||
| 186 | } while (0); | 192 | } while (0); |
| 187 | } | 193 | } |
| 188 | 194 | ||
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h index 762eeb0626c1..548a4c8d63df 100644 --- a/arch/arm/plat-omap/include/plat/usb.h +++ b/arch/arm/plat-omap/include/plat/usb.h | |||
| @@ -44,6 +44,8 @@ struct usbhs_omap_board_data { | |||
| 44 | struct regulator *regulator[OMAP3_HS_USB_PORTS]; | 44 | struct regulator *regulator[OMAP3_HS_USB_PORTS]; |
| 45 | }; | 45 | }; |
| 46 | 46 | ||
| 47 | #ifdef CONFIG_ARCH_OMAP2PLUS | ||
| 48 | |||
| 47 | struct ehci_hcd_omap_platform_data { | 49 | struct ehci_hcd_omap_platform_data { |
| 48 | enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS]; | 50 | enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS]; |
| 49 | int reset_gpio_port[OMAP3_HS_USB_PORTS]; | 51 | int reset_gpio_port[OMAP3_HS_USB_PORTS]; |
| @@ -64,26 +66,6 @@ struct usbhs_omap_platform_data { | |||
| 64 | }; | 66 | }; |
| 65 | /*-------------------------------------------------------------------------*/ | 67 | /*-------------------------------------------------------------------------*/ |
| 66 | 68 | ||
| 67 | #define OMAP1_OTG_BASE 0xfffb0400 | ||
| 68 | #define OMAP1_UDC_BASE 0xfffb4000 | ||
| 69 | #define OMAP1_OHCI_BASE 0xfffba000 | ||
| 70 | |||
| 71 | #define OMAP2_OHCI_BASE 0x4805e000 | ||
| 72 | #define OMAP2_UDC_BASE 0x4805e200 | ||
| 73 | #define OMAP2_OTG_BASE 0x4805e300 | ||
| 74 | |||
| 75 | #ifdef CONFIG_ARCH_OMAP1 | ||
| 76 | |||
| 77 | #define OTG_BASE OMAP1_OTG_BASE | ||
| 78 | #define UDC_BASE OMAP1_UDC_BASE | ||
| 79 | #define OMAP_OHCI_BASE OMAP1_OHCI_BASE | ||
| 80 | |||
| 81 | #else | ||
| 82 | |||
| 83 | #define OTG_BASE OMAP2_OTG_BASE | ||
| 84 | #define UDC_BASE OMAP2_UDC_BASE | ||
| 85 | #define OMAP_OHCI_BASE OMAP2_OHCI_BASE | ||
| 86 | |||
| 87 | struct omap_musb_board_data { | 69 | struct omap_musb_board_data { |
| 88 | u8 interface_type; | 70 | u8 interface_type; |
| 89 | u8 mode; | 71 | u8 mode; |
| @@ -107,44 +89,6 @@ extern int omap4430_phy_init(struct device *dev); | |||
| 107 | extern int omap4430_phy_exit(struct device *dev); | 89 | extern int omap4430_phy_exit(struct device *dev); |
| 108 | extern int omap4430_phy_suspend(struct device *dev, int suspend); | 90 | extern int omap4430_phy_suspend(struct device *dev, int suspend); |
| 109 | 91 | ||
| 110 | /* | ||
| 111 | * NOTE: Please update omap USB drivers to use ioremap + read/write | ||
| 112 | */ | ||
| 113 | |||
| 114 | #define OMAP2_L4_IO_OFFSET 0xb2000000 | ||
| 115 | #define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) | ||
| 116 | |||
| 117 | static inline u8 omap_readb(u32 pa) | ||
| 118 | { | ||
| 119 | return __raw_readb(OMAP2_L4_IO_ADDRESS(pa)); | ||
| 120 | } | ||
| 121 | |||
| 122 | static inline u16 omap_readw(u32 pa) | ||
| 123 | { | ||
| 124 | return __raw_readw(OMAP2_L4_IO_ADDRESS(pa)); | ||
| 125 | } | ||
| 126 | |||
| 127 | static inline u32 omap_readl(u32 pa) | ||
| 128 | { | ||
| 129 | return __raw_readl(OMAP2_L4_IO_ADDRESS(pa)); | ||
| 130 | } | ||
| 131 | |||
| 132 | static inline void omap_writeb(u8 v, u32 pa) | ||
| 133 | { | ||
| 134 | __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa)); | ||
| 135 | } | ||
| 136 | |||
| 137 | |||
| 138 | static inline void omap_writew(u16 v, u32 pa) | ||
| 139 | { | ||
| 140 | __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa)); | ||
| 141 | } | ||
| 142 | |||
| 143 | static inline void omap_writel(u32 v, u32 pa) | ||
| 144 | { | ||
| 145 | __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa)); | ||
| 146 | } | ||
| 147 | |||
| 148 | #endif | 92 | #endif |
| 149 | 93 | ||
| 150 | extern void am35x_musb_reset(void); | 94 | extern void am35x_musb_reset(void); |
| @@ -153,142 +97,6 @@ extern void am35x_musb_clear_irq(void); | |||
| 153 | extern void am35x_set_mode(u8 musb_mode); | 97 | extern void am35x_set_mode(u8 musb_mode); |
| 154 | extern void ti81xx_musb_phy_power(u8 on); | 98 | extern void ti81xx_musb_phy_power(u8 on); |
| 155 | 99 | ||
| 156 | /* | ||
| 157 | * FIXME correct answer depends on hmc_mode, | ||
| 158 | * as does (on omap1) any nonzero value for config->otg port number | ||
| 159 | */ | ||
| 160 | #ifdef CONFIG_USB_GADGET_OMAP | ||
| 161 | #define is_usb0_device(config) 1 | ||
| 162 | #else | ||
| 163 | #define is_usb0_device(config) 0 | ||
| 164 | #endif | ||
| 165 | |||
| 166 | void omap_otg_init(struct omap_usb_config *config); | ||
| 167 | |||
| 168 | #if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE) | ||
| 169 | void omap1_usb_init(struct omap_usb_config *pdata); | ||
| 170 | #else | ||
| 171 | static inline void omap1_usb_init(struct omap_usb_config *pdata) | ||
| 172 | { | ||
| 173 | } | ||
| 174 | #endif | ||
| 175 | |||
| 176 | #if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE) | ||
| 177 | void omap2_usbfs_init(struct omap_usb_config *pdata); | ||
| 178 | #else | ||
| 179 | static inline void omap2_usbfs_init(struct omap_usb_config *pdata) | ||
| 180 | { | ||
| 181 | } | ||
| 182 | #endif | ||
| 183 | |||
| 184 | /*-------------------------------------------------------------------------*/ | ||
| 185 | |||
| 186 | /* | ||
| 187 | * OTG and transceiver registers, for OMAPs starting with ARM926 | ||
| 188 | */ | ||
| 189 | #define OTG_REV (OTG_BASE + 0x00) | ||
| 190 | #define OTG_SYSCON_1 (OTG_BASE + 0x04) | ||
| 191 | # define USB2_TRX_MODE(w) (((w)>>24)&0x07) | ||
| 192 | # define USB1_TRX_MODE(w) (((w)>>20)&0x07) | ||
| 193 | # define USB0_TRX_MODE(w) (((w)>>16)&0x07) | ||
| 194 | # define OTG_IDLE_EN (1 << 15) | ||
| 195 | # define HST_IDLE_EN (1 << 14) | ||
| 196 | # define DEV_IDLE_EN (1 << 13) | ||
| 197 | # define OTG_RESET_DONE (1 << 2) | ||
| 198 | # define OTG_SOFT_RESET (1 << 1) | ||
| 199 | #define OTG_SYSCON_2 (OTG_BASE + 0x08) | ||
| 200 | # define OTG_EN (1 << 31) | ||
| 201 | # define USBX_SYNCHRO (1 << 30) | ||
| 202 | # define OTG_MST16 (1 << 29) | ||
| 203 | # define SRP_GPDATA (1 << 28) | ||
| 204 | # define SRP_GPDVBUS (1 << 27) | ||
| 205 | # define SRP_GPUVBUS(w) (((w)>>24)&0x07) | ||
| 206 | # define A_WAIT_VRISE(w) (((w)>>20)&0x07) | ||
| 207 | # define B_ASE_BRST(w) (((w)>>16)&0x07) | ||
| 208 | # define SRP_DPW (1 << 14) | ||
| 209 | # define SRP_DATA (1 << 13) | ||
| 210 | # define SRP_VBUS (1 << 12) | ||
| 211 | # define OTG_PADEN (1 << 10) | ||
| 212 | # define HMC_PADEN (1 << 9) | ||
| 213 | # define UHOST_EN (1 << 8) | ||
| 214 | # define HMC_TLLSPEED (1 << 7) | ||
| 215 | # define HMC_TLLATTACH (1 << 6) | ||
| 216 | # define OTG_HMC(w) (((w)>>0)&0x3f) | ||
| 217 | #define OTG_CTRL (OTG_BASE + 0x0c) | ||
| 218 | # define OTG_USB2_EN (1 << 29) | ||
| 219 | # define OTG_USB2_DP (1 << 28) | ||
| 220 | # define OTG_USB2_DM (1 << 27) | ||
| 221 | # define OTG_USB1_EN (1 << 26) | ||
| 222 | # define OTG_USB1_DP (1 << 25) | ||
| 223 | # define OTG_USB1_DM (1 << 24) | ||
| 224 | # define OTG_USB0_EN (1 << 23) | ||
| 225 | # define OTG_USB0_DP (1 << 22) | ||
| 226 | # define OTG_USB0_DM (1 << 21) | ||
| 227 | # define OTG_ASESSVLD (1 << 20) | ||
| 228 | # define OTG_BSESSEND (1 << 19) | ||
| 229 | # define OTG_BSESSVLD (1 << 18) | ||
| 230 | # define OTG_VBUSVLD (1 << 17) | ||
| 231 | # define OTG_ID (1 << 16) | ||
| 232 | # define OTG_DRIVER_SEL (1 << 15) | ||
| 233 | # define OTG_A_SETB_HNPEN (1 << 12) | ||
| 234 | # define OTG_A_BUSREQ (1 << 11) | ||
| 235 | # define OTG_B_HNPEN (1 << 9) | ||
| 236 | # define OTG_B_BUSREQ (1 << 8) | ||
| 237 | # define OTG_BUSDROP (1 << 7) | ||
| 238 | # define OTG_PULLDOWN (1 << 5) | ||
| 239 | # define OTG_PULLUP (1 << 4) | ||
| 240 | # define OTG_DRV_VBUS (1 << 3) | ||
| 241 | # define OTG_PD_VBUS (1 << 2) | ||
| 242 | # define OTG_PU_VBUS (1 << 1) | ||
| 243 | # define OTG_PU_ID (1 << 0) | ||
| 244 | #define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */ | ||
| 245 | # define DRIVER_SWITCH (1 << 15) | ||
| 246 | # define A_VBUS_ERR (1 << 13) | ||
| 247 | # define A_REQ_TMROUT (1 << 12) | ||
| 248 | # define A_SRP_DETECT (1 << 11) | ||
| 249 | # define B_HNP_FAIL (1 << 10) | ||
| 250 | # define B_SRP_TMROUT (1 << 9) | ||
| 251 | # define B_SRP_DONE (1 << 8) | ||
| 252 | # define B_SRP_STARTED (1 << 7) | ||
| 253 | # define OPRT_CHG (1 << 0) | ||
| 254 | #define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */ | ||
| 255 | // same bits as in IRQ_EN | ||
| 256 | #define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */ | ||
| 257 | # define OTGVPD (1 << 14) | ||
| 258 | # define OTGVPU (1 << 13) | ||
| 259 | # define OTGPUID (1 << 12) | ||
| 260 | # define USB2VDR (1 << 10) | ||
| 261 | # define USB2PDEN (1 << 9) | ||
| 262 | # define USB2PUEN (1 << 8) | ||
| 263 | # define USB1VDR (1 << 6) | ||
| 264 | # define USB1PDEN (1 << 5) | ||
| 265 | # define USB1PUEN (1 << 4) | ||
| 266 | # define USB0VDR (1 << 2) | ||
| 267 | # define USB0PDEN (1 << 1) | ||
| 268 | # define USB0PUEN (1 << 0) | ||
| 269 | #define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */ | ||
| 270 | #define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */ | ||
| 271 | |||
| 272 | /*-------------------------------------------------------------------------*/ | ||
| 273 | |||
| 274 | /* OMAP1 */ | ||
| 275 | #define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064) | ||
| 276 | # define CONF_USB2_UNI_R (1 << 8) | ||
| 277 | # define CONF_USB1_UNI_R (1 << 7) | ||
| 278 | # define CONF_USB_PORT0_R(x) (((x)>>4)&0x7) | ||
| 279 | # define CONF_USB0_ISOLATE_R (1 << 3) | ||
| 280 | # define CONF_USB_PWRDN_DM_R (1 << 2) | ||
| 281 | # define CONF_USB_PWRDN_DP_R (1 << 1) | ||
| 282 | |||
| 283 | /* OMAP2 */ | ||
| 284 | # define USB_UNIDIR 0x0 | ||
| 285 | # define USB_UNIDIR_TLL 0x1 | ||
| 286 | # define USB_BIDIR 0x2 | ||
| 287 | # define USB_BIDIR_TLL 0x3 | ||
| 288 | # define USBTXWRMODEI(port, x) ((x) << (22 - (port * 2))) | ||
| 289 | # define USBT2TLL5PI (1 << 17) | ||
| 290 | # define USB0PUENACTLOI (1 << 16) | ||
| 291 | # define USBSTANDBYCTRL (1 << 15) | ||
| 292 | /* AM35x */ | 100 | /* AM35x */ |
| 293 | /* USB 2.0 PHY Control */ | 101 | /* USB 2.0 PHY Control */ |
| 294 | #define CONF2_PHY_GPIOMODE (1 << 23) | 102 | #define CONF2_PHY_GPIOMODE (1 << 23) |
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c index ad32621aa52e..5e13c3884aa4 100644 --- a/arch/arm/plat-omap/mailbox.c +++ b/arch/arm/plat-omap/mailbox.c | |||
| @@ -282,6 +282,8 @@ static int omap_mbox_startup(struct omap_mbox *mbox) | |||
| 282 | } | 282 | } |
| 283 | mbox->rxq = mq; | 283 | mbox->rxq = mq; |
| 284 | mq->mbox = mbox; | 284 | mq->mbox = mbox; |
| 285 | |||
| 286 | omap_mbox_enable_irq(mbox, IRQ_RX); | ||
| 285 | } | 287 | } |
| 286 | mutex_unlock(&mbox_configured_lock); | 288 | mutex_unlock(&mbox_configured_lock); |
| 287 | return 0; | 289 | return 0; |
| @@ -305,6 +307,7 @@ static void omap_mbox_fini(struct omap_mbox *mbox) | |||
| 305 | mutex_lock(&mbox_configured_lock); | 307 | mutex_lock(&mbox_configured_lock); |
| 306 | 308 | ||
| 307 | if (!--mbox->use_count) { | 309 | if (!--mbox->use_count) { |
| 310 | omap_mbox_disable_irq(mbox, IRQ_RX); | ||
| 308 | free_irq(mbox->irq, mbox); | 311 | free_irq(mbox->irq, mbox); |
| 309 | tasklet_kill(&mbox->txq->tasklet); | 312 | tasklet_kill(&mbox->txq->tasklet); |
| 310 | flush_work_sync(&mbox->rxq->work); | 313 | flush_work_sync(&mbox->rxq->work); |
| @@ -338,13 +341,15 @@ struct omap_mbox *omap_mbox_get(const char *name, struct notifier_block *nb) | |||
| 338 | if (!mbox) | 341 | if (!mbox) |
| 339 | return ERR_PTR(-ENOENT); | 342 | return ERR_PTR(-ENOENT); |
| 340 | 343 | ||
| 341 | ret = omap_mbox_startup(mbox); | ||
| 342 | if (ret) | ||
| 343 | return ERR_PTR(-ENODEV); | ||
| 344 | |||
| 345 | if (nb) | 344 | if (nb) |
| 346 | blocking_notifier_chain_register(&mbox->notifier, nb); | 345 | blocking_notifier_chain_register(&mbox->notifier, nb); |
| 347 | 346 | ||
| 347 | ret = omap_mbox_startup(mbox); | ||
| 348 | if (ret) { | ||
| 349 | blocking_notifier_chain_unregister(&mbox->notifier, nb); | ||
| 350 | return ERR_PTR(-ENODEV); | ||
| 351 | } | ||
| 352 | |||
| 348 | return mbox; | 353 | return mbox; |
| 349 | } | 354 | } |
| 350 | EXPORT_SYMBOL(omap_mbox_get); | 355 | EXPORT_SYMBOL(omap_mbox_get); |
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c deleted file mode 100644 index daa0327381b5..000000000000 --- a/arch/arm/plat-omap/usb.c +++ /dev/null | |||
| @@ -1,145 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/usb.c -- platform level USB initialization | ||
| 3 | * | ||
| 4 | * Copyright (C) 2004 Texas Instruments, Inc. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #undef DEBUG | ||
| 22 | |||
| 23 | #include <linux/module.h> | ||
| 24 | #include <linux/kernel.h> | ||
| 25 | #include <linux/init.h> | ||
| 26 | #include <linux/platform_device.h> | ||
| 27 | #include <linux/io.h> | ||
| 28 | |||
| 29 | #include <plat/usb.h> | ||
| 30 | #include <plat/board.h> | ||
| 31 | |||
| 32 | #include <mach/hardware.h> | ||
| 33 | |||
| 34 | #ifdef CONFIG_ARCH_OMAP_OTG | ||
| 35 | |||
| 36 | void __init | ||
| 37 | omap_otg_init(struct omap_usb_config *config) | ||
| 38 | { | ||
| 39 | u32 syscon; | ||
| 40 | int alt_pingroup = 0; | ||
| 41 | |||
| 42 | /* NOTE: no bus or clock setup (yet?) */ | ||
| 43 | |||
| 44 | syscon = omap_readl(OTG_SYSCON_1) & 0xffff; | ||
| 45 | if (!(syscon & OTG_RESET_DONE)) | ||
| 46 | pr_debug("USB resets not complete?\n"); | ||
| 47 | |||
| 48 | //omap_writew(0, OTG_IRQ_EN); | ||
| 49 | |||
| 50 | /* pin muxing and transceiver pinouts */ | ||
| 51 | if (config->pins[0] > 2) /* alt pingroup 2 */ | ||
| 52 | alt_pingroup = 1; | ||
| 53 | syscon |= config->usb0_init(config->pins[0], is_usb0_device(config)); | ||
| 54 | syscon |= config->usb1_init(config->pins[1]); | ||
| 55 | syscon |= config->usb2_init(config->pins[2], alt_pingroup); | ||
| 56 | pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1)); | ||
| 57 | omap_writel(syscon, OTG_SYSCON_1); | ||
| 58 | |||
| 59 | syscon = config->hmc_mode; | ||
| 60 | syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */; | ||
| 61 | #ifdef CONFIG_USB_OTG | ||
| 62 | if (config->otg) | ||
| 63 | syscon |= OTG_EN; | ||
| 64 | #endif | ||
| 65 | if (cpu_class_is_omap1()) | ||
| 66 | pr_debug("USB_TRANSCEIVER_CTRL = %03x\n", | ||
| 67 | omap_readl(USB_TRANSCEIVER_CTRL)); | ||
| 68 | pr_debug("OTG_SYSCON_2 = %08x\n", omap_readl(OTG_SYSCON_2)); | ||
| 69 | omap_writel(syscon, OTG_SYSCON_2); | ||
| 70 | |||
| 71 | printk("USB: hmc %d", config->hmc_mode); | ||
| 72 | if (!alt_pingroup) | ||
| 73 | printk(", usb2 alt %d wires", config->pins[2]); | ||
| 74 | else if (config->pins[0]) | ||
| 75 | printk(", usb0 %d wires%s", config->pins[0], | ||
| 76 | is_usb0_device(config) ? " (dev)" : ""); | ||
| 77 | if (config->pins[1]) | ||
| 78 | printk(", usb1 %d wires", config->pins[1]); | ||
| 79 | if (!alt_pingroup && config->pins[2]) | ||
| 80 | printk(", usb2 %d wires", config->pins[2]); | ||
| 81 | if (config->otg) | ||
| 82 | printk(", Mini-AB on usb%d", config->otg - 1); | ||
| 83 | printk("\n"); | ||
| 84 | |||
| 85 | if (cpu_class_is_omap1()) { | ||
| 86 | u16 w; | ||
| 87 | |||
| 88 | /* leave USB clocks/controllers off until needed */ | ||
| 89 | w = omap_readw(ULPD_SOFT_REQ); | ||
| 90 | w &= ~SOFT_USB_CLK_REQ; | ||
| 91 | omap_writew(w, ULPD_SOFT_REQ); | ||
| 92 | |||
| 93 | w = omap_readw(ULPD_CLOCK_CTRL); | ||
| 94 | w &= ~USB_MCLK_EN; | ||
| 95 | w |= DIS_USB_PVCI_CLK; | ||
| 96 | omap_writew(w, ULPD_CLOCK_CTRL); | ||
| 97 | } | ||
| 98 | syscon = omap_readl(OTG_SYSCON_1); | ||
| 99 | syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN; | ||
| 100 | |||
| 101 | #ifdef CONFIG_USB_GADGET_OMAP | ||
| 102 | if (config->otg || config->register_dev) { | ||
| 103 | struct platform_device *udc_device = config->udc_device; | ||
| 104 | int status; | ||
| 105 | |||
| 106 | syscon &= ~DEV_IDLE_EN; | ||
| 107 | udc_device->dev.platform_data = config; | ||
| 108 | status = platform_device_register(udc_device); | ||
| 109 | if (status) | ||
| 110 | pr_debug("can't register UDC device, %d\n", status); | ||
| 111 | } | ||
| 112 | #endif | ||
| 113 | |||
| 114 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | ||
| 115 | if (config->otg || config->register_host) { | ||
| 116 | struct platform_device *ohci_device = config->ohci_device; | ||
| 117 | int status; | ||
| 118 | |||
| 119 | syscon &= ~HST_IDLE_EN; | ||
| 120 | ohci_device->dev.platform_data = config; | ||
| 121 | status = platform_device_register(ohci_device); | ||
| 122 | if (status) | ||
| 123 | pr_debug("can't register OHCI device, %d\n", status); | ||
| 124 | } | ||
| 125 | #endif | ||
| 126 | |||
| 127 | #ifdef CONFIG_USB_OTG | ||
| 128 | if (config->otg) { | ||
| 129 | struct platform_device *otg_device = config->otg_device; | ||
| 130 | int status; | ||
| 131 | |||
| 132 | syscon &= ~OTG_IDLE_EN; | ||
| 133 | otg_device->dev.platform_data = config; | ||
| 134 | status = platform_device_register(otg_device); | ||
| 135 | if (status) | ||
| 136 | pr_debug("can't register OTG device, %d\n", status); | ||
| 137 | } | ||
| 138 | #endif | ||
| 139 | pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1)); | ||
| 140 | omap_writel(syscon, OTG_SYSCON_1); | ||
| 141 | } | ||
| 142 | |||
| 143 | #else | ||
| 144 | void omap_otg_init(struct omap_usb_config *config) {} | ||
| 145 | #endif | ||
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index a2fae4ea0936..7aca31c1df1f 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig | |||
| @@ -78,6 +78,10 @@ config S5P_HRT | |||
| 78 | 78 | ||
| 79 | # clock options | 79 | # clock options |
| 80 | 80 | ||
| 81 | config SAMSUNG_CLOCK | ||
| 82 | bool | ||
| 83 | default y if !COMMON_CLK | ||
| 84 | |||
| 81 | config SAMSUNG_CLKSRC | 85 | config SAMSUNG_CLKSRC |
| 82 | bool | 86 | bool |
| 83 | help | 87 | help |
| @@ -491,14 +495,6 @@ config S5P_SLEEP | |||
| 491 | Internal config node to apply common S5P sleep management code. | 495 | Internal config node to apply common S5P sleep management code. |
| 492 | Can be selected by S5P and newer SoCs with similar sleep procedure. | 496 | Can be selected by S5P and newer SoCs with similar sleep procedure. |
| 493 | 497 | ||
| 494 | comment "Power Domain" | ||
| 495 | |||
| 496 | config SAMSUNG_PD | ||
| 497 | bool "Samsung Power Domain" | ||
| 498 | depends on PM_RUNTIME | ||
| 499 | help | ||
| 500 | Say Y here if you want to control Power Domain by Runtime PM. | ||
| 501 | |||
| 502 | config DEBUG_S3C_UART | 498 | config DEBUG_S3C_UART |
| 503 | depends on PLAT_SAMSUNG | 499 | depends on PLAT_SAMSUNG |
| 504 | int | 500 | int |
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 860b2db4db15..b78717496677 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile | |||
| @@ -15,8 +15,8 @@ obj-y += init.o cpu.o | |||
| 15 | obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET) += time.o | 15 | obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET) += time.o |
| 16 | obj-$(CONFIG_S5P_HRT) += s5p-time.o | 16 | obj-$(CONFIG_S5P_HRT) += s5p-time.o |
| 17 | 17 | ||
| 18 | obj-y += clock.o | 18 | obj-$(CONFIG_SAMSUNG_CLOCK) += clock.o |
| 19 | obj-y += pwm-clock.o | 19 | obj-$(CONFIG_SAMSUNG_CLOCK) += pwm-clock.o |
| 20 | 20 | ||
| 21 | obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o | 21 | obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o |
| 22 | obj-$(CONFIG_S5P_CLOCK) += s5p-clock.o | 22 | obj-$(CONFIG_S5P_CLOCK) += s5p-clock.o |
| @@ -60,10 +60,6 @@ obj-$(CONFIG_SAMSUNG_WAKEMASK) += wakeup-mask.o | |||
| 60 | obj-$(CONFIG_S5P_PM) += s5p-pm.o s5p-irq-pm.o | 60 | obj-$(CONFIG_S5P_PM) += s5p-pm.o s5p-irq-pm.o |
| 61 | obj-$(CONFIG_S5P_SLEEP) += s5p-sleep.o | 61 | obj-$(CONFIG_S5P_SLEEP) += s5p-sleep.o |
| 62 | 62 | ||
| 63 | # PD support | ||
| 64 | |||
| 65 | obj-$(CONFIG_SAMSUNG_PD) += pd.o | ||
| 66 | |||
| 67 | # PWM support | 63 | # PWM support |
| 68 | 64 | ||
| 69 | obj-$(CONFIG_HAVE_PWM) += pwm.o | 65 | obj-$(CONFIG_HAVE_PWM) += pwm.o |
diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c index 33ecd0c9f0c3..b1e05ccff3ac 100644 --- a/arch/arm/plat-samsung/adc.c +++ b/arch/arm/plat-samsung/adc.c | |||
| @@ -157,11 +157,13 @@ int s3c_adc_start(struct s3c_adc_client *client, | |||
| 157 | return -EINVAL; | 157 | return -EINVAL; |
| 158 | } | 158 | } |
| 159 | 159 | ||
| 160 | if (client->is_ts && adc->ts_pend) | ||
| 161 | return -EAGAIN; | ||
| 162 | |||
| 163 | spin_lock_irqsave(&adc->lock, flags); | 160 | spin_lock_irqsave(&adc->lock, flags); |
| 164 | 161 | ||
| 162 | if (client->is_ts && adc->ts_pend) { | ||
| 163 | spin_unlock_irqrestore(&adc->lock, flags); | ||
| 164 | return -EAGAIN; | ||
| 165 | } | ||
| 166 | |||
| 165 | client->channel = channel; | 167 | client->channel = channel; |
| 166 | client->nr_samples = nr_samples; | 168 | client->nr_samples = nr_samples; |
| 167 | 169 | ||
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index 86d075870a52..74e31ce35538 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c | |||
| @@ -126,7 +126,8 @@ struct platform_device s3c_device_adc = { | |||
| 126 | #ifdef CONFIG_CPU_S3C2440 | 126 | #ifdef CONFIG_CPU_S3C2440 |
| 127 | static struct resource s3c_camif_resource[] = { | 127 | static struct resource s3c_camif_resource[] = { |
| 128 | [0] = DEFINE_RES_MEM(S3C2440_PA_CAMIF, S3C2440_SZ_CAMIF), | 128 | [0] = DEFINE_RES_MEM(S3C2440_PA_CAMIF, S3C2440_SZ_CAMIF), |
| 129 | [1] = DEFINE_RES_IRQ(IRQ_CAM), | 129 | [1] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_C), |
| 130 | [2] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_P), | ||
| 130 | }; | 131 | }; |
| 131 | 132 | ||
| 132 | struct platform_device s3c_device_camif = { | 133 | struct platform_device s3c_device_camif = { |
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index 0721293fad63..ace4451b7651 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h | |||
| @@ -132,6 +132,10 @@ IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) | |||
| 132 | 132 | ||
| 133 | #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } | 133 | #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } |
| 134 | 134 | ||
| 135 | #ifndef KHZ | ||
| 136 | #define KHZ (1000) | ||
| 137 | #endif | ||
| 138 | |||
| 135 | #ifndef MHZ | 139 | #ifndef MHZ |
| 136 | #define MHZ (1000*1000) | 140 | #define MHZ (1000*1000) |
| 137 | #endif | 141 | #endif |
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index 61ca2f356c52..5da4b4f38f40 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h | |||
| @@ -131,7 +131,6 @@ extern struct platform_device exynos4_device_ohci; | |||
| 131 | extern struct platform_device exynos4_device_pcm0; | 131 | extern struct platform_device exynos4_device_pcm0; |
| 132 | extern struct platform_device exynos4_device_pcm1; | 132 | extern struct platform_device exynos4_device_pcm1; |
| 133 | extern struct platform_device exynos4_device_pcm2; | 133 | extern struct platform_device exynos4_device_pcm2; |
| 134 | extern struct platform_device exynos4_device_pd[]; | ||
| 135 | extern struct platform_device exynos4_device_spdif; | 134 | extern struct platform_device exynos4_device_spdif; |
| 136 | 135 | ||
| 137 | extern struct platform_device exynos_device_drm; | 136 | extern struct platform_device exynos_device_drm; |
diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h index 536002ff2ab8..b885322717a1 100644 --- a/arch/arm/plat-samsung/include/plat/fb.h +++ b/arch/arm/plat-samsung/include/plat/fb.h | |||
| @@ -43,7 +43,6 @@ struct s3c_fb_pd_win { | |||
| 43 | * @setup_gpio: Setup the external GPIO pins to the right state to transfer | 43 | * @setup_gpio: Setup the external GPIO pins to the right state to transfer |
| 44 | * the data from the display system to the connected display | 44 | * the data from the display system to the connected display |
| 45 | * device. | 45 | * device. |
| 46 | * @default_win: default window layer number to be used for UI layer. | ||
| 47 | * @vidcon0: The base vidcon0 values to control the panel data format. | 46 | * @vidcon0: The base vidcon0 values to control the panel data format. |
| 48 | * @vidcon1: The base vidcon1 values to control the panel data output. | 47 | * @vidcon1: The base vidcon1 values to control the panel data output. |
| 49 | * @vtiming: Video timing when connected to a RGB type panel. | 48 | * @vtiming: Video timing when connected to a RGB type panel. |
diff --git a/arch/arm/plat-samsung/include/plat/pd.h b/arch/arm/plat-samsung/include/plat/pd.h deleted file mode 100644 index abb4bc32716a..000000000000 --- a/arch/arm/plat-samsung/include/plat/pd.h +++ /dev/null | |||
| @@ -1,30 +0,0 @@ | |||
| 1 | /* linux/arch/arm/plat-samsung/include/plat/pd.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_PLAT_SAMSUNG_PD_H | ||
| 12 | #define __ASM_PLAT_SAMSUNG_PD_H __FILE__ | ||
| 13 | |||
| 14 | struct samsung_pd_info { | ||
| 15 | int (*enable)(struct device *dev); | ||
| 16 | int (*disable)(struct device *dev); | ||
| 17 | void __iomem *base; | ||
| 18 | }; | ||
| 19 | |||
| 20 | enum exynos4_pd_block { | ||
| 21 | PD_MFC, | ||
| 22 | PD_G3D, | ||
| 23 | PD_LCD0, | ||
| 24 | PD_LCD1, | ||
| 25 | PD_TV, | ||
| 26 | PD_CAM, | ||
| 27 | PD_GPS | ||
| 28 | }; | ||
| 29 | |||
| 30 | #endif /* __ASM_PLAT_SAMSUNG_PD_H */ | ||
diff --git a/arch/arm/plat-samsung/pd.c b/arch/arm/plat-samsung/pd.c deleted file mode 100644 index 312b510d86b7..000000000000 --- a/arch/arm/plat-samsung/pd.c +++ /dev/null | |||
| @@ -1,95 +0,0 @@ | |||
| 1 | /* linux/arch/arm/plat-samsung/pd.c | ||
| 2 | * | ||
| 3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com | ||
| 5 | * | ||
| 6 | * Samsung Power domain support | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/init.h> | ||
| 14 | #include <linux/export.h> | ||
| 15 | #include <linux/platform_device.h> | ||
| 16 | #include <linux/err.h> | ||
| 17 | #include <linux/pm_runtime.h> | ||
| 18 | |||
| 19 | #include <plat/pd.h> | ||
| 20 | |||
| 21 | static int samsung_pd_probe(struct platform_device *pdev) | ||
| 22 | { | ||
| 23 | struct samsung_pd_info *pdata = pdev->dev.platform_data; | ||
| 24 | struct device *dev = &pdev->dev; | ||
| 25 | |||
| 26 | if (!pdata) { | ||
| 27 | dev_err(dev, "no device data specified\n"); | ||
| 28 | return -ENOENT; | ||
| 29 | } | ||
| 30 | |||
| 31 | pm_runtime_set_active(dev); | ||
| 32 | pm_runtime_enable(dev); | ||
| 33 | |||
| 34 | dev_info(dev, "power domain registered\n"); | ||
| 35 | return 0; | ||
| 36 | } | ||
| 37 | |||
| 38 | static int __devexit samsung_pd_remove(struct platform_device *pdev) | ||
| 39 | { | ||
| 40 | struct device *dev = &pdev->dev; | ||
| 41 | |||
| 42 | pm_runtime_disable(dev); | ||
| 43 | return 0; | ||
| 44 | } | ||
| 45 | |||
| 46 | static int samsung_pd_runtime_suspend(struct device *dev) | ||
| 47 | { | ||
| 48 | struct samsung_pd_info *pdata = dev->platform_data; | ||
| 49 | int ret = 0; | ||
| 50 | |||
| 51 | if (pdata->disable) | ||
| 52 | ret = pdata->disable(dev); | ||
| 53 | |||
| 54 | dev_dbg(dev, "suspended\n"); | ||
| 55 | return ret; | ||
| 56 | } | ||
| 57 | |||
| 58 | static int samsung_pd_runtime_resume(struct device *dev) | ||
| 59 | { | ||
| 60 | struct samsung_pd_info *pdata = dev->platform_data; | ||
| 61 | int ret = 0; | ||
| 62 | |||
| 63 | if (pdata->enable) | ||
| 64 | ret = pdata->enable(dev); | ||
| 65 | |||
| 66 | dev_dbg(dev, "resumed\n"); | ||
| 67 | return ret; | ||
| 68 | } | ||
| 69 | |||
| 70 | static const struct dev_pm_ops samsung_pd_pm_ops = { | ||
| 71 | .runtime_suspend = samsung_pd_runtime_suspend, | ||
| 72 | .runtime_resume = samsung_pd_runtime_resume, | ||
| 73 | }; | ||
| 74 | |||
| 75 | static struct platform_driver samsung_pd_driver = { | ||
| 76 | .driver = { | ||
| 77 | .name = "samsung-pd", | ||
| 78 | .owner = THIS_MODULE, | ||
| 79 | .pm = &samsung_pd_pm_ops, | ||
| 80 | }, | ||
| 81 | .probe = samsung_pd_probe, | ||
| 82 | .remove = __devexit_p(samsung_pd_remove), | ||
| 83 | }; | ||
| 84 | |||
| 85 | static int __init samsung_pd_init(void) | ||
| 86 | { | ||
| 87 | int ret; | ||
| 88 | |||
| 89 | ret = platform_driver_register(&samsung_pd_driver); | ||
| 90 | if (ret) | ||
| 91 | printk(KERN_ERR "%s: failed to add PD driver\n", __func__); | ||
| 92 | |||
| 93 | return ret; | ||
| 94 | } | ||
| 95 | arch_initcall(samsung_pd_init); | ||
diff --git a/arch/arm/plat-samsung/pwm.c b/arch/arm/plat-samsung/pwm.c index c559d8438c70..d3583050fb05 100644 --- a/arch/arm/plat-samsung/pwm.c +++ b/arch/arm/plat-samsung/pwm.c | |||
| @@ -36,7 +36,6 @@ struct pwm_device { | |||
| 36 | unsigned int duty_ns; | 36 | unsigned int duty_ns; |
| 37 | 37 | ||
| 38 | unsigned char tcon_base; | 38 | unsigned char tcon_base; |
| 39 | unsigned char running; | ||
| 40 | unsigned char use_count; | 39 | unsigned char use_count; |
| 41 | unsigned char pwm_id; | 40 | unsigned char pwm_id; |
| 42 | }; | 41 | }; |
| @@ -116,7 +115,6 @@ int pwm_enable(struct pwm_device *pwm) | |||
| 116 | 115 | ||
| 117 | local_irq_restore(flags); | 116 | local_irq_restore(flags); |
| 118 | 117 | ||
| 119 | pwm->running = 1; | ||
| 120 | return 0; | 118 | return 0; |
| 121 | } | 119 | } |
| 122 | 120 | ||
| @@ -134,8 +132,6 @@ void pwm_disable(struct pwm_device *pwm) | |||
| 134 | __raw_writel(tcon, S3C2410_TCON); | 132 | __raw_writel(tcon, S3C2410_TCON); |
| 135 | 133 | ||
| 136 | local_irq_restore(flags); | 134 | local_irq_restore(flags); |
| 137 | |||
| 138 | pwm->running = 0; | ||
| 139 | } | 135 | } |
| 140 | 136 | ||
| 141 | EXPORT_SYMBOL(pwm_disable); | 137 | EXPORT_SYMBOL(pwm_disable); |
diff --git a/arch/arm/plat-samsung/s5p-clock.c b/arch/arm/plat-samsung/s5p-clock.c index 031a61899bef..48a159911037 100644 --- a/arch/arm/plat-samsung/s5p-clock.c +++ b/arch/arm/plat-samsung/s5p-clock.c | |||
| @@ -37,6 +37,7 @@ struct clk clk_ext_xtal_mux = { | |||
| 37 | struct clk clk_xusbxti = { | 37 | struct clk clk_xusbxti = { |
| 38 | .name = "xusbxti", | 38 | .name = "xusbxti", |
| 39 | .id = -1, | 39 | .id = -1, |
| 40 | .rate = 24000000, | ||
| 40 | }; | 41 | }; |
| 41 | 42 | ||
| 42 | struct clk s5p_clk_27m = { | 43 | struct clk s5p_clk_27m = { |
diff --git a/arch/arm/plat-versatile/Kconfig b/arch/arm/plat-versatile/Kconfig index 81ee7cc34457..8d5c10a5084d 100644 --- a/arch/arm/plat-versatile/Kconfig +++ b/arch/arm/plat-versatile/Kconfig | |||
| @@ -1,5 +1,8 @@ | |||
| 1 | if PLAT_VERSATILE | 1 | if PLAT_VERSATILE |
| 2 | 2 | ||
| 3 | config PLAT_VERSATILE_CLOCK | ||
| 4 | bool | ||
| 5 | |||
| 3 | config PLAT_VERSATILE_CLCD | 6 | config PLAT_VERSATILE_CLCD |
| 4 | bool | 7 | bool |
| 5 | 8 | ||
diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile index a5cb1945bdcc..272769a8a7d6 100644 --- a/arch/arm/plat-versatile/Makefile +++ b/arch/arm/plat-versatile/Makefile | |||
| @@ -1,4 +1,4 @@ | |||
| 1 | obj-y := clock.o | 1 | obj-$(CONFIG_PLAT_VERSATILE_CLOCK) += clock.o |
| 2 | obj-$(CONFIG_PLAT_VERSATILE_CLCD) += clcd.o | 2 | obj-$(CONFIG_PLAT_VERSATILE_CLCD) += clcd.o |
| 3 | obj-$(CONFIG_PLAT_VERSATILE_FPGA_IRQ) += fpga-irq.o | 3 | obj-$(CONFIG_PLAT_VERSATILE_FPGA_IRQ) += fpga-irq.o |
| 4 | obj-$(CONFIG_PLAT_VERSATILE_LEDS) += leds.o | 4 | obj-$(CONFIG_PLAT_VERSATILE_LEDS) += leds.o |