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-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi1
-rw-r--r--arch/arm/boot/dts/tegra-paz00.dts6
-rw-r--r--arch/arm/common/it8152.c7
-rw-r--r--arch/arm/common/pl330.c3
-rw-r--r--arch/arm/include/asm/assembler.h5
-rw-r--r--arch/arm/include/asm/hardware/pl330.h2
-rw-r--r--arch/arm/include/asm/processor.h1
-rw-r--r--arch/arm/kernel/ptrace.c9
-rw-r--r--arch/arm/kernel/smp_twd.c2
-rw-r--r--arch/arm/kernel/traps.c5
-rw-r--r--arch/arm/kernel/vmlinux.lds.S1
-rw-r--r--arch/arm/mach-at91/at91rm9200_devices.c2
-rw-r--r--arch/arm/mach-at91/at91sam9260_devices.c9
-rw-r--r--arch/arm/mach-at91/at91sam9261_devices.c2
-rw-r--r--arch/arm/mach-at91/at91sam9263_devices.c8
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_smc.h29
-rw-r--r--arch/arm/mach-at91/sam9_smc.c76
-rw-r--r--arch/arm/mach-at91/sam9_smc.h23
-rw-r--r--arch/arm/mach-dove/common.c3
-rw-r--r--arch/arm/mach-ep93xx/vision_ep9307.c4
-rw-r--r--arch/arm/mach-exynos/clock-exynos4210.c2
-rw-r--r--arch/arm/mach-exynos/clock-exynos4212.c2
-rw-r--r--arch/arm/mach-exynos/clock.c2
-rw-r--r--arch/arm/mach-exynos/mach-exynos4-dt.c8
-rw-r--r--arch/arm/mach-exynos/mach-nuri.c8
-rw-r--r--arch/arm/mach-exynos/mach-universal_c210.c2
-rw-r--r--arch/arm/mach-exynos/pm.c4
-rw-r--r--arch/arm/mach-kirkwood/common.c3
-rw-r--r--arch/arm/mach-kirkwood/mpp.h320
-rw-r--r--arch/arm/mach-mv78xx0/common.c3
-rw-r--r--arch/arm/mach-mv78xx0/mpp.h226
-rw-r--r--arch/arm/mach-omap2/Makefile4
-rw-r--r--arch/arm/mach-omap2/board-4430sdp.c17
-rw-r--r--arch/arm/mach-omap2/board-cm-t35.c2
-rw-r--r--arch/arm/mach-omap2/board-generic.c4
-rw-r--r--arch/arm/mach-omap2/board-omap3evm.c23
-rw-r--r--arch/arm/mach-omap2/board-omap4panda.c6
-rw-r--r--arch/arm/mach-omap2/board-zoom-peripherals.c6
-rw-r--r--arch/arm/mach-omap2/hsmmc.c8
-rw-r--r--arch/arm/mach-omap2/mux.c22
-rw-r--r--arch/arm/mach-omap2/omap-headsmp.S1
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c16
-rw-r--r--arch/arm/mach-omap2/pm24xx.c8
-rw-r--r--arch/arm/mach-omap2/prm44xx.c1
-rw-r--r--arch/arm/mach-omap2/serial.c8
-rw-r--r--arch/arm/mach-omap2/vc.c10
-rw-r--r--arch/arm/mach-omap2/voltagedomains3xxx_data.c2
-rw-r--r--arch/arm/mach-omap2/voltagedomains44xx_data.c2
-rw-r--r--arch/arm/mach-omap2/vp.c5
-rw-r--r--arch/arm/mach-orion5x/common.c4
-rw-r--r--arch/arm/mach-s3c2410/cpu-freq.c8
-rw-r--r--arch/arm/mach-s3c2410/dma.c5
-rw-r--r--arch/arm/mach-s3c2410/pll.c2
-rw-r--r--arch/arm/mach-s3c2410/pm.c2
-rw-r--r--arch/arm/mach-s3c2412/cpu-freq.c3
-rw-r--r--arch/arm/mach-s3c2412/dma.c3
-rw-r--r--arch/arm/mach-s3c2412/irq.c2
-rw-r--r--arch/arm/mach-s3c2412/pm.c2
-rw-r--r--arch/arm/mach-s3c2416/irq.c3
-rw-r--r--arch/arm/mach-s3c2416/pm.c2
-rw-r--r--arch/arm/mach-s3c2440/clock.c2
-rw-r--r--arch/arm/mach-s3c2440/dma.c3
-rw-r--r--arch/arm/mach-s3c2440/irq.c2
-rw-r--r--arch/arm/mach-s3c2440/s3c2440-cpufreq.c3
-rw-r--r--arch/arm/mach-s3c2440/s3c2440-pll-12000000.c2
-rw-r--r--arch/arm/mach-s3c2440/s3c2440-pll-16934400.c3
-rw-r--r--arch/arm/mach-s3c2440/s3c2442.c2
-rw-r--r--arch/arm/mach-s3c2440/s3c244x-clock.c2
-rw-r--r--arch/arm/mach-s3c2440/s3c244x-irq.c2
-rw-r--r--arch/arm/mach-s3c2443/dma.c3
-rw-r--r--arch/arm/mach-s3c2443/irq.c3
-rw-r--r--arch/arm/mach-s3c64xx/clock.c5
-rw-r--r--arch/arm/mach-s3c64xx/common.c2
-rw-r--r--arch/arm/mach-s5p64x0/pm.c2
-rw-r--r--arch/arm/mach-s5pv210/clock.c4
-rw-r--r--arch/arm/mach-s5pv210/pm.c2
-rw-r--r--arch/arm/mach-shmobile/board-ag5evm.c29
-rw-r--r--arch/arm/mach-shmobile/board-ap4evb.c12
-rw-r--r--arch/arm/mach-shmobile/board-kota2.c3
-rw-r--r--arch/arm/mach-shmobile/board-mackerel.c95
-rw-r--r--arch/arm/mach-shmobile/clock-sh73a0.c113
-rw-r--r--arch/arm/mach-shmobile/include/mach/sh73a0.h6
-rw-r--r--arch/arm/mach-shmobile/intc-sh73a0.c2
-rw-r--r--arch/arm/mach-shmobile/pfc-r8a7779.c2
-rw-r--r--arch/arm/mach-shmobile/pfc-sh7372.c41
-rw-r--r--arch/arm/mach-shmobile/smp-sh73a0.c2
-rw-r--r--arch/arm/mach-tegra/board-paz00.c8
-rw-r--r--arch/arm/mach-tegra/board-paz00.h2
-rw-r--r--arch/arm/mach-tegra/include/mach/dma.h10
-rw-r--r--arch/arm/mm/Kconfig3
-rw-r--r--arch/arm/mm/cache-v7.S6
-rw-r--r--arch/arm/plat-omap/include/plat/omap-secure.h2
-rw-r--r--arch/arm/plat-orion/common.c9
-rw-r--r--arch/arm/plat-orion/include/plat/common.h3
-rw-r--r--arch/arm/plat-orion/mpp.c3
-rw-r--r--arch/arm/plat-samsung/devs.c4
96 files changed, 800 insertions, 556 deletions
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 63d7578856c1..a1dd2ee83753 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -29,6 +29,7 @@
29 compatible = "arm,cortex-a9-gic"; 29 compatible = "arm,cortex-a9-gic";
30 #interrupt-cells = <3>; 30 #interrupt-cells = <3>;
31 interrupt-controller; 31 interrupt-controller;
32 cpu-offset = <0x8000>;
32 reg = <0x10490000 0x1000>, <0x10480000 0x100>; 33 reg = <0x10490000 0x1000>, <0x10480000 0x100>;
33 }; 34 };
34 35
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts
index 1a1d7023b69b..825d2957da0b 100644
--- a/arch/arm/boot/dts/tegra-paz00.dts
+++ b/arch/arm/boot/dts/tegra-paz00.dts
@@ -46,11 +46,11 @@
46 }; 46 };
47 47
48 serial@70006200 { 48 serial@70006200 {
49 status = "disable"; 49 clock-frequency = <216000000>;
50 }; 50 };
51 51
52 serial@70006300 { 52 serial@70006300 {
53 clock-frequency = <216000000>; 53 status = "disable";
54 }; 54 };
55 55
56 serial@70006400 { 56 serial@70006400 {
@@ -60,7 +60,7 @@
60 sdhci@c8000000 { 60 sdhci@c8000000 {
61 cd-gpios = <&gpio 173 0>; /* gpio PV5 */ 61 cd-gpios = <&gpio 173 0>; /* gpio PV5 */
62 wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 62 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
63 power-gpios = <&gpio 155 0>; /* gpio PT3 */ 63 power-gpios = <&gpio 169 0>; /* gpio PV1 */
64 }; 64 };
65 65
66 sdhci@c8000200 { 66 sdhci@c8000200 {
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index d1bcd7b13ebc..fb1f1cfce60c 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -320,13 +320,6 @@ err0:
320 return -EBUSY; 320 return -EBUSY;
321} 321}
322 322
323/*
324 * If we set up a device for bus mastering, we need to check the latency
325 * timer as we don't have even crappy BIOSes to set it properly.
326 * The implementation is from arch/i386/pci/i386.c
327 */
328unsigned int pcibios_max_latency = 255;
329
330/* ITE bridge requires setting latency timer to avoid early bus access 323/* ITE bridge requires setting latency timer to avoid early bus access
331 termination by PCI bus master devices 324 termination by PCI bus master devices
332*/ 325*/
diff --git a/arch/arm/common/pl330.c b/arch/arm/common/pl330.c
index d8e44a43047c..ff3ad2244824 100644
--- a/arch/arm/common/pl330.c
+++ b/arch/arm/common/pl330.c
@@ -1502,12 +1502,13 @@ int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op)
1502 struct pl330_thread *thrd = ch_id; 1502 struct pl330_thread *thrd = ch_id;
1503 struct pl330_dmac *pl330; 1503 struct pl330_dmac *pl330;
1504 unsigned long flags; 1504 unsigned long flags;
1505 int ret = 0, active = thrd->req_running; 1505 int ret = 0, active;
1506 1506
1507 if (!thrd || thrd->free || thrd->dmac->state == DYING) 1507 if (!thrd || thrd->free || thrd->dmac->state == DYING)
1508 return -EINVAL; 1508 return -EINVAL;
1509 1509
1510 pl330 = thrd->dmac; 1510 pl330 = thrd->dmac;
1511 active = thrd->req_running;
1511 1512
1512 spin_lock_irqsave(&pl330->lock, flags); 1513 spin_lock_irqsave(&pl330->lock, flags);
1513 1514
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 62f8095d46de..23371b17b23e 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -137,6 +137,11 @@
137 disable_irq 137 disable_irq
138 .endm 138 .endm
139 139
140 .macro save_and_disable_irqs_notrace, oldcpsr
141 mrs \oldcpsr, cpsr
142 disable_irq_notrace
143 .endm
144
140/* 145/*
141 * Restore interrupt state previously stored in a register. We don't 146 * Restore interrupt state previously stored in a register. We don't
142 * guarantee that this will preserve the flags. 147 * guarantee that this will preserve the flags.
diff --git a/arch/arm/include/asm/hardware/pl330.h b/arch/arm/include/asm/hardware/pl330.h
index 575fa8186ca0..c1821385abfa 100644
--- a/arch/arm/include/asm/hardware/pl330.h
+++ b/arch/arm/include/asm/hardware/pl330.h
@@ -41,7 +41,7 @@ enum pl330_dstcachectrl {
41 DCCTRL1, /* Bufferable only */ 41 DCCTRL1, /* Bufferable only */
42 DCCTRL2, /* Cacheable, but do not allocate */ 42 DCCTRL2, /* Cacheable, but do not allocate */
43 DCCTRL3, /* Cacheable and bufferable, but do not allocate */ 43 DCCTRL3, /* Cacheable and bufferable, but do not allocate */
44 DINVALID1 = 8, 44 DINVALID1, /* AWCACHE = 0x1000 */
45 DINVALID2, 45 DINVALID2,
46 DCCTRL6, /* Cacheable write-through, allocate on writes only */ 46 DCCTRL6, /* Cacheable write-through, allocate on writes only */
47 DCCTRL7, /* Cacheable write-back, allocate on writes only */ 47 DCCTRL7, /* Cacheable write-back, allocate on writes only */
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index ce280b8d613c..cb8d638924fd 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -22,6 +22,7 @@
22#include <asm/hw_breakpoint.h> 22#include <asm/hw_breakpoint.h>
23#include <asm/ptrace.h> 23#include <asm/ptrace.h>
24#include <asm/types.h> 24#include <asm/types.h>
25#include <asm/system.h>
25 26
26#ifdef __KERNEL__ 27#ifdef __KERNEL__
27#define STACK_TOP ((current->personality & ADDR_LIMIT_32BIT) ? \ 28#define STACK_TOP ((current->personality & ADDR_LIMIT_32BIT) ? \
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index e33870ff0ac0..ede6443c34d9 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -23,6 +23,7 @@
23#include <linux/perf_event.h> 23#include <linux/perf_event.h>
24#include <linux/hw_breakpoint.h> 24#include <linux/hw_breakpoint.h>
25#include <linux/regset.h> 25#include <linux/regset.h>
26#include <linux/audit.h>
26 27
27#include <asm/pgtable.h> 28#include <asm/pgtable.h>
28#include <asm/system.h> 29#include <asm/system.h>
@@ -904,6 +905,12 @@ long arch_ptrace(struct task_struct *child, long request,
904 return ret; 905 return ret;
905} 906}
906 907
908#ifdef __ARMEB__
909#define AUDIT_ARCH_NR AUDIT_ARCH_ARMEB
910#else
911#define AUDIT_ARCH_NR AUDIT_ARCH_ARM
912#endif
913
907asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno) 914asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
908{ 915{
909 unsigned long ip; 916 unsigned long ip;
@@ -918,7 +925,7 @@ asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
918 if (!ip) 925 if (!ip)
919 audit_syscall_exit(regs); 926 audit_syscall_exit(regs);
920 else 927 else
921 audit_syscall_entry(AUDIT_ARCH_ARMEB, scno, regs->ARM_r0, 928 audit_syscall_entry(AUDIT_ARCH_NR, scno, regs->ARM_r0,
922 regs->ARM_r1, regs->ARM_r2, regs->ARM_r3); 929 regs->ARM_r1, regs->ARM_r2, regs->ARM_r3);
923 930
924 if (!test_thread_flag(TIF_SYSCALL_TRACE)) 931 if (!test_thread_flag(TIF_SYSCALL_TRACE))
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 4285daa077b0..7a79b24597b2 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -129,7 +129,7 @@ static struct notifier_block twd_cpufreq_nb = {
129 129
130static int twd_cpufreq_init(void) 130static int twd_cpufreq_init(void)
131{ 131{
132 if (!IS_ERR(twd_clk)) 132 if (twd_evt && *__this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk))
133 return cpufreq_register_notifier(&twd_cpufreq_nb, 133 return cpufreq_register_notifier(&twd_cpufreq_nb,
134 CPUFREQ_TRANSITION_NOTIFIER); 134 CPUFREQ_TRANSITION_NOTIFIER);
135 135
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 99a572702509..f84dfe67724f 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -266,6 +266,7 @@ void die(const char *str, struct pt_regs *regs, int err)
266{ 266{
267 struct thread_info *thread = current_thread_info(); 267 struct thread_info *thread = current_thread_info();
268 int ret; 268 int ret;
269 enum bug_trap_type bug_type = BUG_TRAP_TYPE_NONE;
269 270
270 oops_enter(); 271 oops_enter();
271 272
@@ -273,7 +274,9 @@ void die(const char *str, struct pt_regs *regs, int err)
273 console_verbose(); 274 console_verbose();
274 bust_spinlocks(1); 275 bust_spinlocks(1);
275 if (!user_mode(regs)) 276 if (!user_mode(regs))
276 report_bug(regs->ARM_pc, regs); 277 bug_type = report_bug(regs->ARM_pc, regs);
278 if (bug_type != BUG_TRAP_TYPE_NONE)
279 str = "Oops - BUG";
277 ret = __die(str, err, thread, regs); 280 ret = __die(str, err, thread, regs);
278 281
279 if (regs && kexec_should_crash(thread->task)) 282 if (regs && kexec_should_crash(thread->task))
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index 1e19691e0406..43a31fb06318 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -10,6 +10,7 @@
10#include <asm/page.h> 10#include <asm/page.h>
11 11
12#define PROC_INFO \ 12#define PROC_INFO \
13 . = ALIGN(4); \
13 VMLINUX_SYMBOL(__proc_info_begin) = .; \ 14 VMLINUX_SYMBOL(__proc_info_begin) = .; \
14 *(.proc.info.init) \ 15 *(.proc.info.init) \
15 VMLINUX_SYMBOL(__proc_info_end) = .; 16 VMLINUX_SYMBOL(__proc_info_end) = .;
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 18bacec2b094..97676bdae998 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -83,7 +83,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
83 * USB Device (Gadget) 83 * USB Device (Gadget)
84 * -------------------------------------------------------------------- */ 84 * -------------------------------------------------------------------- */
85 85
86#ifdef CONFIG_USB_AT91 86#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
87static struct at91_udc_data udc_data; 87static struct at91_udc_data udc_data;
88 88
89static struct resource udc_resources[] = { 89static struct resource udc_resources[] = {
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 642ccb6d26b2..5a24f0b4554d 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -84,7 +84,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
84 * USB Device (Gadget) 84 * USB Device (Gadget)
85 * -------------------------------------------------------------------- */ 85 * -------------------------------------------------------------------- */
86 86
87#ifdef CONFIG_USB_AT91 87#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
88static struct at91_udc_data udc_data; 88static struct at91_udc_data udc_data;
89 89
90static struct resource udc_resources[] = { 90static struct resource udc_resources[] = {
@@ -1215,8 +1215,7 @@ void __init at91_add_device_serial(void) {}
1215 * CF/IDE 1215 * CF/IDE
1216 * -------------------------------------------------------------------- */ 1216 * -------------------------------------------------------------------- */
1217 1217
1218#if defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE) || \ 1218#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \
1219 defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \
1220 defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) 1219 defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
1221 1220
1222static struct at91_cf_data cf0_data; 1221static struct at91_cf_data cf0_data;
@@ -1313,10 +1312,8 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
1313 if (data->flags & AT91_CF_TRUE_IDE) 1312 if (data->flags & AT91_CF_TRUE_IDE)
1314#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) 1313#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE)
1315 pdev->name = "pata_at91"; 1314 pdev->name = "pata_at91";
1316#elif defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE)
1317 pdev->name = "at91_ide";
1318#else 1315#else
1319#warning "board requires AT91_CF_TRUE_IDE: enable either at91_ide or pata_at91" 1316#warning "board requires AT91_CF_TRUE_IDE: enable pata_at91"
1320#endif 1317#endif
1321 else 1318 else
1322 pdev->name = "at91_cf"; 1319 pdev->name = "at91_cf";
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index fc59cbdb0e3c..1e28bed8f425 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -87,7 +87,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
87 * USB Device (Gadget) 87 * USB Device (Gadget)
88 * -------------------------------------------------------------------- */ 88 * -------------------------------------------------------------------- */
89 89
90#ifdef CONFIG_USB_AT91 90#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
91static struct at91_udc_data udc_data; 91static struct at91_udc_data udc_data;
92 92
93static struct resource udc_resources[] = { 93static struct resource udc_resources[] = {
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 7b46b2787022..366a7765635b 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -92,7 +92,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
92 * USB Device (Gadget) 92 * USB Device (Gadget)
93 * -------------------------------------------------------------------- */ 93 * -------------------------------------------------------------------- */
94 94
95#ifdef CONFIG_USB_AT91 95#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
96static struct at91_udc_data udc_data; 96static struct at91_udc_data udc_data;
97 97
98static struct resource udc_resources[] = { 98static struct resource udc_resources[] = {
@@ -355,8 +355,8 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
355 * Compact Flash (PCMCIA or IDE) 355 * Compact Flash (PCMCIA or IDE)
356 * -------------------------------------------------------------------- */ 356 * -------------------------------------------------------------------- */
357 357
358#if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) || \ 358#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \
359 defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE) 359 defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
360 360
361static struct at91_cf_data cf0_data; 361static struct at91_cf_data cf0_data;
362 362
@@ -450,7 +450,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
450 at91_set_A_periph(AT91_PIN_PD9, 0); /* CFCE2 */ 450 at91_set_A_periph(AT91_PIN_PD9, 0); /* CFCE2 */
451 at91_set_A_periph(AT91_PIN_PD14, 0); /* CFNRW */ 451 at91_set_A_periph(AT91_PIN_PD14, 0); /* CFNRW */
452 452
453 pdev->name = (data->flags & AT91_CF_TRUE_IDE) ? "at91_ide" : "at91_cf"; 453 pdev->name = (data->flags & AT91_CF_TRUE_IDE) ? "pata_at91" : "at91_cf";
454 platform_device_register(pdev); 454 platform_device_register(pdev);
455} 455}
456#else 456#else
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
index eb18a70fa647..175e1fdd9fe8 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
@@ -18,6 +18,35 @@
18 18
19#include <mach/cpu.h> 19#include <mach/cpu.h>
20 20
21#ifndef __ASSEMBLY__
22struct sam9_smc_config {
23 /* Setup register */
24 u8 ncs_read_setup;
25 u8 nrd_setup;
26 u8 ncs_write_setup;
27 u8 nwe_setup;
28
29 /* Pulse register */
30 u8 ncs_read_pulse;
31 u8 nrd_pulse;
32 u8 ncs_write_pulse;
33 u8 nwe_pulse;
34
35 /* Cycle register */
36 u16 read_cycle;
37 u16 write_cycle;
38
39 /* Mode register */
40 u32 mode;
41 u8 tdf_cycles:4;
42};
43
44extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config);
45extern void sam9_smc_read(int id, int cs, struct sam9_smc_config *config);
46extern void sam9_smc_read_mode(int id, int cs, struct sam9_smc_config *config);
47extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config);
48#endif
49
21#define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */ 50#define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */
22#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ 51#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
23#define AT91_SMC_NWESETUP_(x) ((x) << 0) 52#define AT91_SMC_NWESETUP_(x) ((x) << 0)
diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c
index 8294783b679d..99a0a1d2b7dc 100644
--- a/arch/arm/mach-at91/sam9_smc.c
+++ b/arch/arm/mach-at91/sam9_smc.c
@@ -2,6 +2,7 @@
2 * linux/arch/arm/mach-at91/sam9_smc.c 2 * linux/arch/arm/mach-at91/sam9_smc.c
3 * 3 *
4 * Copyright (C) 2008 Andrew Victor 4 * Copyright (C) 2008 Andrew Victor
5 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
@@ -22,7 +23,22 @@
22 23
23static void __iomem *smc_base_addr[2]; 24static void __iomem *smc_base_addr[2];
24 25
25static void __init sam9_smc_cs_configure(void __iomem *base, struct sam9_smc_config* config) 26static void sam9_smc_cs_write_mode(void __iomem *base,
27 struct sam9_smc_config *config)
28{
29 __raw_writel(config->mode
30 | AT91_SMC_TDF_(config->tdf_cycles),
31 base + AT91_SMC_MODE);
32}
33
34void sam9_smc_write_mode(int id, int cs,
35 struct sam9_smc_config *config)
36{
37 sam9_smc_cs_write_mode(AT91_SMC_CS(id, cs), config);
38}
39
40static void sam9_smc_cs_configure(void __iomem *base,
41 struct sam9_smc_config *config)
26{ 42{
27 43
28 /* Setup register */ 44 /* Setup register */
@@ -45,16 +61,66 @@ static void __init sam9_smc_cs_configure(void __iomem *base, struct sam9_smc_con
45 base + AT91_SMC_CYCLE); 61 base + AT91_SMC_CYCLE);
46 62
47 /* Mode register */ 63 /* Mode register */
48 __raw_writel(config->mode 64 sam9_smc_cs_write_mode(base, config);
49 | AT91_SMC_TDF_(config->tdf_cycles),
50 base + AT91_SMC_MODE);
51} 65}
52 66
53void __init sam9_smc_configure(int id, int cs, struct sam9_smc_config* config) 67void sam9_smc_configure(int id, int cs,
68 struct sam9_smc_config *config)
54{ 69{
55 sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config); 70 sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config);
56} 71}
57 72
73static void sam9_smc_cs_read_mode(void __iomem *base,
74 struct sam9_smc_config *config)
75{
76 u32 val = __raw_readl(base + AT91_SMC_MODE);
77
78 config->mode = (val & ~AT91_SMC_NWECYCLE);
79 config->tdf_cycles = (val & AT91_SMC_NWECYCLE) >> 16 ;
80}
81
82void sam9_smc_read_mode(int id, int cs,
83 struct sam9_smc_config *config)
84{
85 sam9_smc_cs_read_mode(AT91_SMC_CS(id, cs), config);
86}
87
88static void sam9_smc_cs_read(void __iomem *base,
89 struct sam9_smc_config *config)
90{
91 u32 val;
92
93 /* Setup register */
94 val = __raw_readl(base + AT91_SMC_SETUP);
95
96 config->nwe_setup = val & AT91_SMC_NWESETUP;
97 config->ncs_write_setup = (val & AT91_SMC_NCS_WRSETUP) >> 8;
98 config->nrd_setup = (val & AT91_SMC_NRDSETUP) >> 16;
99 config->ncs_read_setup = (val & AT91_SMC_NCS_RDSETUP) >> 24;
100
101 /* Pulse register */
102 val = __raw_readl(base + AT91_SMC_PULSE);
103
104 config->nwe_setup = val & AT91_SMC_NWEPULSE;
105 config->ncs_write_pulse = (val & AT91_SMC_NCS_WRPULSE) >> 8;
106 config->nrd_pulse = (val & AT91_SMC_NRDPULSE) >> 16;
107 config->ncs_read_pulse = (val & AT91_SMC_NCS_RDPULSE) >> 24;
108
109 /* Cycle register */
110 val = __raw_readl(base + AT91_SMC_CYCLE);
111
112 config->write_cycle = val & AT91_SMC_NWECYCLE;
113 config->read_cycle = (val & AT91_SMC_NRDCYCLE) >> 16;
114
115 /* Mode register */
116 sam9_smc_cs_read_mode(base, config);
117}
118
119void sam9_smc_read(int id, int cs, struct sam9_smc_config *config)
120{
121 sam9_smc_cs_read(AT91_SMC_CS(id, cs), config);
122}
123
58void __init at91sam9_ioremap_smc(int id, u32 addr) 124void __init at91sam9_ioremap_smc(int id, u32 addr)
59{ 125{
60 if (id > 1) { 126 if (id > 1) {
diff --git a/arch/arm/mach-at91/sam9_smc.h b/arch/arm/mach-at91/sam9_smc.h
index 039c5ce17aec..3e52dcd4a59f 100644
--- a/arch/arm/mach-at91/sam9_smc.h
+++ b/arch/arm/mach-at91/sam9_smc.h
@@ -8,27 +8,4 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11struct sam9_smc_config {
12 /* Setup register */
13 u8 ncs_read_setup;
14 u8 nrd_setup;
15 u8 ncs_write_setup;
16 u8 nwe_setup;
17
18 /* Pulse register */
19 u8 ncs_read_pulse;
20 u8 nrd_pulse;
21 u8 ncs_write_pulse;
22 u8 nwe_pulse;
23
24 /* Cycle register */
25 u16 read_cycle;
26 u16 write_cycle;
27
28 /* Mode register */
29 u32 mode;
30 u8 tdf_cycles:4;
31};
32
33extern void __init sam9_smc_configure(int id, int cs, struct sam9_smc_config* config);
34extern void __init at91sam9_ioremap_smc(int id, u32 addr); 11extern void __init at91sam9_ioremap_smc(int id, u32 addr);
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index dd1429ae6405..bda7aca04ca0 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -28,6 +28,7 @@
28#include <asm/mach/arch.h> 28#include <asm/mach/arch.h>
29#include <linux/irq.h> 29#include <linux/irq.h>
30#include <plat/time.h> 30#include <plat/time.h>
31#include <plat/ehci-orion.h>
31#include <plat/common.h> 32#include <plat/common.h>
32#include <plat/addr-map.h> 33#include <plat/addr-map.h>
33#include "common.h" 34#include "common.h"
@@ -71,7 +72,7 @@ void __init dove_map_io(void)
71 ****************************************************************************/ 72 ****************************************************************************/
72void __init dove_ehci0_init(void) 73void __init dove_ehci0_init(void)
73{ 74{
74 orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0); 75 orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA);
75} 76}
76 77
77/***************************************************************************** 78/*****************************************************************************
diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vision_ep9307.c
index 03dd4012043e..d5fb44f16d31 100644
--- a/arch/arm/mach-ep93xx/vision_ep9307.c
+++ b/arch/arm/mach-ep93xx/vision_ep9307.c
@@ -32,6 +32,7 @@
32#include <mach/hardware.h> 32#include <mach/hardware.h>
33#include <mach/fb.h> 33#include <mach/fb.h>
34#include <mach/ep93xx_spi.h> 34#include <mach/ep93xx_spi.h>
35#include <mach/gpio-ep93xx.h>
35 36
36#include <asm/mach-types.h> 37#include <asm/mach-types.h>
37#include <asm/mach/map.h> 38#include <asm/mach/map.h>
@@ -153,7 +154,6 @@ static struct i2c_board_info vision_i2c_info[] __initdata = {
153 }, { 154 }, {
154 I2C_BOARD_INFO("pca9539", 0x74), 155 I2C_BOARD_INFO("pca9539", 0x74),
155 .platform_data = &pca953x_74_gpio_data, 156 .platform_data = &pca953x_74_gpio_data,
156 .irq = gpio_to_irq(EP93XX_GPIO_LINE_F(7)),
157 }, { 157 }, {
158 I2C_BOARD_INFO("pca9539", 0x75), 158 I2C_BOARD_INFO("pca9539", 0x75),
159 .platform_data = &pca953x_75_gpio_data, 159 .platform_data = &pca953x_75_gpio_data,
@@ -348,6 +348,8 @@ static void __init vision_init_machine(void)
348 "pca9539:74")) 348 "pca9539:74"))
349 pr_warn("cannot request interrupt gpio for pca9539:74\n"); 349 pr_warn("cannot request interrupt gpio for pca9539:74\n");
350 350
351 vision_i2c_info[1].irq = gpio_to_irq(EP93XX_GPIO_LINE_F(7));
352
351 ep93xx_register_i2c(&vision_i2c_gpio_data, vision_i2c_info, 353 ep93xx_register_i2c(&vision_i2c_gpio_data, vision_i2c_info,
352 ARRAY_SIZE(vision_i2c_info)); 354 ARRAY_SIZE(vision_i2c_info));
353 ep93xx_register_spi(&vision_spi_master, vision_spi_board_info, 355 ep93xx_register_spi(&vision_spi_master, vision_spi_board_info,
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
index a5823a7f249e..13312ccb2d93 100644
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ b/arch/arm/mach-exynos/clock-exynos4210.c
@@ -32,6 +32,7 @@
32 32
33#include "common.h" 33#include "common.h"
34 34
35#ifdef CONFIG_PM_SLEEP
35static struct sleep_save exynos4210_clock_save[] = { 36static struct sleep_save exynos4210_clock_save[] = {
36 SAVE_ITEM(S5P_CLKSRC_IMAGE), 37 SAVE_ITEM(S5P_CLKSRC_IMAGE),
37 SAVE_ITEM(S5P_CLKSRC_LCD1), 38 SAVE_ITEM(S5P_CLKSRC_LCD1),
@@ -42,6 +43,7 @@ static struct sleep_save exynos4210_clock_save[] = {
42 SAVE_ITEM(S5P_CLKGATE_IP_LCD1), 43 SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
43 SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210), 44 SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
44}; 45};
46#endif
45 47
46static struct clksrc_clk *sysclks[] = { 48static struct clksrc_clk *sysclks[] = {
47 /* nothing here yet */ 49 /* nothing here yet */
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index 26a668b0d101..48af28566fa1 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -32,12 +32,14 @@
32 32
33#include "common.h" 33#include "common.h"
34 34
35#ifdef CONFIG_PM_SLEEP
35static struct sleep_save exynos4212_clock_save[] = { 36static struct sleep_save exynos4212_clock_save[] = {
36 SAVE_ITEM(S5P_CLKSRC_IMAGE), 37 SAVE_ITEM(S5P_CLKSRC_IMAGE),
37 SAVE_ITEM(S5P_CLKDIV_IMAGE), 38 SAVE_ITEM(S5P_CLKDIV_IMAGE),
38 SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212), 39 SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
39 SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212), 40 SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
40}; 41};
42#endif
41 43
42static struct clk *clk_src_mpll_user_list[] = { 44static struct clk *clk_src_mpll_user_list[] = {
43 [0] = &clk_fin_mpll, 45 [0] = &clk_fin_mpll,
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
index 5a8c42e90005..187287aa57ab 100644
--- a/arch/arm/mach-exynos/clock.c
+++ b/arch/arm/mach-exynos/clock.c
@@ -30,6 +30,7 @@
30 30
31#include "common.h" 31#include "common.h"
32 32
33#ifdef CONFIG_PM_SLEEP
33static struct sleep_save exynos4_clock_save[] = { 34static struct sleep_save exynos4_clock_save[] = {
34 SAVE_ITEM(S5P_CLKDIV_LEFTBUS), 35 SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
35 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS), 36 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
@@ -93,6 +94,7 @@ static struct sleep_save exynos4_clock_save[] = {
93 SAVE_ITEM(S5P_CLKGATE_SCLKCPU), 94 SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
94 SAVE_ITEM(S5P_CLKGATE_IP_CPU), 95 SAVE_ITEM(S5P_CLKGATE_IP_CPU),
95}; 96};
97#endif
96 98
97struct clk clk_sclk_hdmi27m = { 99struct clk clk_sclk_hdmi27m = {
98 .name = "sclk_hdmi27m", 100 .name = "sclk_hdmi27m",
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index 85fa02767d67..e6b02fdf1b09 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -15,11 +15,13 @@
15#include <linux/serial_core.h> 15#include <linux/serial_core.h>
16 16
17#include <asm/mach/arch.h> 17#include <asm/mach/arch.h>
18#include <asm/hardware/gic.h>
18#include <mach/map.h> 19#include <mach/map.h>
19 20
20#include <plat/cpu.h> 21#include <plat/cpu.h>
21#include <plat/regs-serial.h> 22#include <plat/regs-serial.h>
22#include <plat/exynos4.h> 23
24#include "common.h"
23 25
24/* 26/*
25 * The following lookup table is used to override device names when devices 27 * The following lookup table is used to override device names when devices
@@ -60,7 +62,7 @@ static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
60 62
61static void __init exynos4210_dt_map_io(void) 63static void __init exynos4210_dt_map_io(void)
62{ 64{
63 s5p_init_io(NULL, 0, S5P_VA_CHIPID); 65 exynos_init_io(NULL, 0);
64 s3c24xx_init_clocks(24000000); 66 s3c24xx_init_clocks(24000000);
65} 67}
66 68
@@ -79,7 +81,9 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
79 /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */ 81 /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
80 .init_irq = exynos4_init_irq, 82 .init_irq = exynos4_init_irq,
81 .map_io = exynos4210_dt_map_io, 83 .map_io = exynos4210_dt_map_io,
84 .handle_irq = gic_handle_irq,
82 .init_machine = exynos4210_dt_machine_init, 85 .init_machine = exynos4210_dt_machine_init,
83 .timer = &exynos4_timer, 86 .timer = &exynos4_timer,
84 .dt_compat = exynos4210_dt_compat, 87 .dt_compat = exynos4210_dt_compat,
88 .restart = exynos4_restart,
85MACHINE_END 89MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index b895ec031105..435261f83f46 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -220,14 +220,14 @@ static struct s3c_fb_pd_win nuri_fb_win0 = {
220 .lower_margin = 1, 220 .lower_margin = 1,
221 .hsync_len = 48, 221 .hsync_len = 48,
222 .vsync_len = 3, 222 .vsync_len = 3,
223 .xres = 1280, 223 .xres = 1024,
224 .yres = 800, 224 .yres = 600,
225 .refresh = 60, 225 .refresh = 60,
226 }, 226 },
227 .max_bpp = 24, 227 .max_bpp = 24,
228 .default_bpp = 16, 228 .default_bpp = 16,
229 .virtual_x = 1280, 229 .virtual_x = 1024,
230 .virtual_y = 800, 230 .virtual_y = 2 * 600,
231}; 231};
232 232
233static struct s3c_fb_platdata nuri_fb_pdata __initdata = { 233static struct s3c_fb_platdata nuri_fb_pdata __initdata = {
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 37ac93e8d6d9..0fc65ffde8ff 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -910,7 +910,7 @@ static struct s5p_fimc_isp_info universal_camera_sensors[] = {
910 .bus_type = FIMC_MIPI_CSI2, 910 .bus_type = FIMC_MIPI_CSI2,
911 .board_info = &m5mols_board_info, 911 .board_info = &m5mols_board_info,
912 .i2c_bus_num = 0, 912 .i2c_bus_num = 0,
913 .clk_frequency = 21600000UL, 913 .clk_frequency = 24000000UL,
914 .csi_data_align = 32, 914 .csi_data_align = 32,
915 }, 915 },
916}; 916};
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index a4f61a43c7ba..e19013051772 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -206,7 +206,7 @@ static void exynos4_pm_prepare(void)
206 206
207} 207}
208 208
209static int exynos4_pm_add(struct device *dev) 209static int exynos4_pm_add(struct device *dev, struct subsys_interface *sif)
210{ 210{
211 pm_cpu_prep = exynos4_pm_prepare; 211 pm_cpu_prep = exynos4_pm_prepare;
212 pm_cpu_sleep = exynos4_cpu_suspend; 212 pm_cpu_sleep = exynos4_cpu_suspend;
@@ -384,7 +384,9 @@ static void exynos4_pm_resume(void)
384 384
385 exynos4_restore_pll(); 385 exynos4_restore_pll();
386 386
387#ifdef CONFIG_SMP
387 scu_enable(S5P_VA_SCU); 388 scu_enable(S5P_VA_SCU);
389#endif
388 390
389#ifdef CONFIG_CACHE_L2X0 391#ifdef CONFIG_CACHE_L2X0
390 s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); 392 s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index cc15426787b1..77d4852e19f2 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -27,6 +27,7 @@
27#include <plat/cache-feroceon-l2.h> 27#include <plat/cache-feroceon-l2.h>
28#include <plat/mvsdio.h> 28#include <plat/mvsdio.h>
29#include <plat/orion_nand.h> 29#include <plat/orion_nand.h>
30#include <plat/ehci-orion.h>
30#include <plat/common.h> 31#include <plat/common.h>
31#include <plat/time.h> 32#include <plat/time.h>
32#include <plat/addr-map.h> 33#include <plat/addr-map.h>
@@ -73,7 +74,7 @@ unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED;
73void __init kirkwood_ehci_init(void) 74void __init kirkwood_ehci_init(void)
74{ 75{
75 kirkwood_clk_ctrl |= CGC_USB0; 76 kirkwood_clk_ctrl |= CGC_USB0;
76 orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB); 77 orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB, EHCI_PHY_NA);
77} 78}
78 79
79 80
diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h
index e8fda45c0736..d5a0d1da2e0e 100644
--- a/arch/arm/mach-kirkwood/mpp.h
+++ b/arch/arm/mach-kirkwood/mpp.h
@@ -31,314 +31,314 @@
31#define MPP_F6282_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 0, 1 ) 31#define MPP_F6282_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 0, 1 )
32 32
33#define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 33#define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1, 1 )
34#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 34#define MPP0_NF_IO2 MPP( 0, 0x1, 0, 0, 1, 1, 1, 1, 1 )
35#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 35#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 0, 1, 1, 1, 1, 1 )
36 36
37#define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 37#define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1, 1 )
38#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 38#define MPP1_NF_IO3 MPP( 1, 0x1, 0, 0, 1, 1, 1, 1, 1 )
39#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 39#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 0, 1, 1, 1, 1, 1 )
40 40
41#define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 41#define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1, 1 )
42#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 42#define MPP2_NF_IO4 MPP( 2, 0x1, 0, 0, 1, 1, 1, 1, 1 )
43#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 43#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 0, 1, 1, 1, 1, 1 )
44 44
45#define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 45#define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1, 1 )
46#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 46#define MPP3_NF_IO5 MPP( 3, 0x1, 0, 0, 1, 1, 1, 1, 1 )
47#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1, 1 ) 47#define MPP3_SPI_MISO MPP( 3, 0x2, 0, 0, 1, 1, 1, 1, 1 )
48 48
49#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 49#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1, 1 )
50#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 50#define MPP4_NF_IO6 MPP( 4, 0x1, 0, 0, 1, 1, 1, 1, 1 )
51#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1, 1 ) 51#define MPP4_UART0_RXD MPP( 4, 0x2, 0, 0, 1, 1, 1, 1, 1 )
52#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1, 1 ) 52#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 0, 0, 0, 1, 1, 1 )
53#define MPP4_LCD_VGA_HSYNC MPP( 4, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 53#define MPP4_LCD_VGA_HSYNC MPP( 4, 0xb, 0, 0, 0, 0, 0, 0, 1 )
54#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1, 0 ) 54#define MPP4_PTP_CLK MPP( 4, 0xd, 0, 0, 1, 1, 1, 1, 0 )
55 55
56#define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 56#define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1, 1 )
57#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 57#define MPP5_NF_IO7 MPP( 5, 0x1, 0, 0, 1, 1, 1, 1, 1 )
58#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 58#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 0, 1, 1, 1, 1, 1 )
59#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1, 0 ) 59#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 0, 1, 1, 1, 1, 0 )
60#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1, 1 ) 60#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 0, 0, 1, 1, 1, 1 )
61#define MPP5_LCD_VGA_VSYNC MPP( 5, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 61#define MPP5_LCD_VGA_VSYNC MPP( 5, 0xb, 0, 0, 0, 0, 0, 0, 1 )
62 62
63#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1, 1 ) 63#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 0, 1, 1, 1, 1, 1 )
64#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 64#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 0, 1, 1, 1, 1, 1 )
65#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1, 0 ) 65#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 0, 1, 1, 1, 1, 0 )
66 66
67#define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 67#define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1, 1 )
68#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1, 0 ) 68#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 0, 1, 1, 1, 1, 0 )
69#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 69#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 0, 1, 1, 1, 1, 1 )
70#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1, 0 ) 70#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 0, 1, 1, 1, 1, 0 )
71#define MPP7_LCD_PWM MPP( 7, 0xb, 0, 1, 0, 0, 0, 0, 1 ) 71#define MPP7_LCD_PWM MPP( 7, 0xb, 0, 0, 0, 0, 0, 0, 1 )
72 72
73#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 73#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1, 1 )
74#define MPP8_TW0_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 74#define MPP8_TW0_SDA MPP( 8, 0x1, 0, 0, 1, 1, 1, 1, 1 )
75#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 75#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 0, 1, 1, 1, 1, 1 )
76#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1, 1 ) 76#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 0, 1, 1, 1, 1, 1 )
77#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1, 1 ) 77#define MPP8_MII0_RXERR MPP( 8, 0x4, 0, 0, 0, 1, 1, 1, 1 )
78#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1, 1 ) 78#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 0, 0, 0, 1, 1, 1 )
79#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1, 0 ) 79#define MPP8_PTP_CLK MPP( 8, 0xc, 0, 0, 1, 1, 1, 1, 0 )
80#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1, 1 ) 80#define MPP8_MII0_COL MPP( 8, 0xd, 0, 0, 1, 1, 1, 1, 1 )
81 81
82#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 82#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1, 1 )
83#define MPP9_TW0_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 83#define MPP9_TW0_SCK MPP( 9, 0x1, 0, 0, 1, 1, 1, 1, 1 )
84#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1, 1 ) 84#define MPP9_UART0_CTS MPP( 9, 0x2, 0, 0, 1, 1, 1, 1, 1 )
85#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1, 1 ) 85#define MPP9_UART1_CTS MPP( 9, 0x3, 0, 0, 1, 1, 1, 1, 1 )
86#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1, 1 ) 86#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 0, 0, 1, 1, 1, 1 )
87#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1, 0 ) 87#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 0, 0, 1, 1, 1, 1, 0 )
88#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1, 1 ) 88#define MPP9_MII0_CRS MPP( 9, 0xd, 0, 0, 1, 1, 1, 1, 1 )
89 89
90#define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 90#define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1, 1 )
91#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 91#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 0, 1, 1, 1, 1, 1 )
92#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1, 1 ) 92#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 0, 1, 1, 1, 1, 1 )
93#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1, 1 ) 93#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 0, 0, 0, 1, 1, 1 )
94#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1, 0 ) 94#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 0, 1, 1, 1, 1, 0 )
95 95
96#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 96#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1, 1 )
97#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1, 1 ) 97#define MPP11_SPI_MISO MPP( 11, 0x2, 0, 0, 1, 1, 1, 1, 1 )
98#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1, 1 ) 98#define MPP11_UART0_RXD MPP( 11, 0x3, 0, 0, 1, 1, 1, 1, 1 )
99#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1, 0 ) 99#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 0, 0, 1, 1, 1, 1, 0 )
100#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1, 0 ) 100#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 0, 1, 1, 1, 1, 0 )
101#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1, 0 ) 101#define MPP11_PTP_CLK MPP( 11, 0xd, 0, 0, 1, 1, 1, 1, 0 )
102#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1, 1 ) 102#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 0, 0, 1, 1, 1, 1 )
103 103
104#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 104#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1, 1 )
105#define MPP12_GPIO MPP( 12, 0x0, 1, 1, 0, 0, 0, 1, 0 ) 105#define MPP12_GPIO MPP( 12, 0x0, 1, 1, 0, 0, 0, 1, 0 )
106#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1, 1 ) 106#define MPP12_SD_CLK MPP( 12, 0x1, 0, 0, 1, 1, 1, 1, 1 )
107#define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 1, 0, 0, 0, 0, 1 ) 107#define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 0, 0, 0, 0, 0, 1 )
108#define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 1, 0, 0, 0, 0, 1 ) 108#define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 0, 0, 0, 0, 0, 1 )
109#define MPP12_TW1_SDA MPP( 12, 0xd, 1, 0, 0, 0, 0, 0, 1 ) 109#define MPP12_TW1_SDA MPP( 12, 0xd, 0, 0, 0, 0, 0, 0, 1 )
110 110
111#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 111#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1, 1 )
112#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 112#define MPP13_SD_CMD MPP( 13, 0x1, 0, 0, 1, 1, 1, 1, 1 )
113#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1, 1 ) 113#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 0, 1, 1, 1, 1, 1 )
114#define MPP13_AU_SPDIFRMCLK MPP( 13, 0xa, 0, 1, 0, 0, 0, 0, 1 ) 114#define MPP13_AU_SPDIFRMCLK MPP( 13, 0xa, 0, 0, 0, 0, 0, 0, 1 )
115#define MPP13_LCDPWM MPP( 13, 0xb, 0, 1, 0, 0, 0, 0, 1 ) 115#define MPP13_LCDPWM MPP( 13, 0xb, 0, 0, 0, 0, 0, 0, 1 )
116 116
117#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 117#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1, 1 )
118#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 118#define MPP14_SD_D0 MPP( 14, 0x1, 0, 0, 1, 1, 1, 1, 1 )
119#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1, 1 ) 119#define MPP14_UART1_RXD MPP( 14, 0x3, 0, 0, 1, 1, 1, 1, 1 )
120#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 120#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 0, 0, 0, 1, 1, 1 )
121#define MPP14_AU_SPDIFI MPP( 14, 0xa, 1, 0, 0, 0, 0, 0, 1 ) 121#define MPP14_AU_SPDIFI MPP( 14, 0xa, 0, 0, 0, 0, 0, 0, 1 )
122#define MPP14_AU_I2SDI MPP( 14, 0xb, 1, 0, 0, 0, 0, 0, 1 ) 122#define MPP14_AU_I2SDI MPP( 14, 0xb, 0, 0, 0, 0, 0, 0, 1 )
123#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1, 1 ) 123#define MPP14_MII0_COL MPP( 14, 0xd, 0, 0, 1, 1, 1, 1, 1 )
124 124
125#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 125#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1, 1 )
126#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 126#define MPP15_SD_D1 MPP( 15, 0x1, 0, 0, 1, 1, 1, 1, 1 )
127#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1, 1 ) 127#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 0, 1, 1, 1, 1, 1 )
128#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1, 1 ) 128#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 0, 1, 1, 1, 1, 1 )
129#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1, 1 ) 129#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 0, 0, 1, 1, 1, 1 )
130#define MPP15_SPI_CSn MPP( 15, 0xb, 0, 1, 0, 0, 0, 0, 1 ) 130#define MPP15_SPI_CSn MPP( 15, 0xb, 0, 0, 0, 0, 0, 0, 1 )
131 131
132#define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 132#define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1, 1 )
133#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 133#define MPP16_SD_D2 MPP( 16, 0x1, 0, 0, 1, 1, 1, 1, 1 )
134#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1, 1 ) 134#define MPP16_UART0_CTS MPP( 16, 0x2, 0, 0, 1, 1, 1, 1, 1 )
135#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1, 1 ) 135#define MPP16_UART1_RXD MPP( 16, 0x3, 0, 0, 1, 1, 1, 1, 1 )
136#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 136#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 0, 0, 0, 1, 1, 1 )
137#define MPP16_LCD_EXT_REF_CLK MPP( 16, 0xb, 1, 0, 0, 0, 0, 0, 1 ) 137#define MPP16_LCD_EXT_REF_CLK MPP( 16, 0xb, 0, 0, 0, 0, 0, 0, 1 )
138#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1, 1 ) 138#define MPP16_MII0_CRS MPP( 16, 0xd, 0, 0, 1, 1, 1, 1, 1 )
139 139
140#define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 140#define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1, 1 )
141#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 141#define MPP17_SD_D3 MPP( 17, 0x1, 0, 0, 1, 1, 1, 1, 1 )
142#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1, 1 ) 142#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 0, 0, 1, 1, 1, 1 )
143#define MPP17_SATA1_ACTn MPP( 17, 0xa, 0, 1, 0, 0, 0, 0, 1 ) 143#define MPP17_SATA1_ACTn MPP( 17, 0xa, 0, 0, 0, 0, 0, 0, 1 )
144#define MPP17_TW1_SCK MPP( 17, 0xd, 1, 1, 0, 0, 0, 0, 1 ) 144#define MPP17_TW1_SCK MPP( 17, 0xd, 0, 0, 0, 0, 0, 0, 1 )
145 145
146#define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 146#define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1, 1 )
147#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 147#define MPP18_NF_IO0 MPP( 18, 0x1, 0, 0, 1, 1, 1, 1, 1 )
148#define MPP18_PEX0_CLKREQ MPP( 18, 0x2, 0, 1, 0, 0, 0, 0, 1 ) 148#define MPP18_PEX0_CLKREQ MPP( 18, 0x2, 0, 0, 0, 0, 0, 0, 1 )
149 149
150#define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1, 1 ) 150#define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1, 1 )
151#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1, 1 ) 151#define MPP19_NF_IO1 MPP( 19, 0x1, 0, 0, 1, 1, 1, 1, 1 )
152 152
153#define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 153#define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1, 1 )
154#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 154#define MPP20_TSMP0 MPP( 20, 0x1, 0, 0, 0, 0, 1, 1, 1 )
155#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 155#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 0, 0, 0, 1, 1, 1 )
156#define MPP20_GE1_TXD0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 156#define MPP20_GE1_TXD0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1, 1 )
157#define MPP20_AU_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1, 1 ) 157#define MPP20_AU_SPDIFI MPP( 20, 0x4, 0, 0, 0, 0, 1, 1, 1 )
158#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1, 1 ) 158#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 0, 0, 0, 1, 1, 1 )
159#define MPP20_LCD_D0 MPP( 20, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 159#define MPP20_LCD_D0 MPP( 20, 0xb, 0, 0, 0, 0, 0, 0, 1 )
160 160
161#define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 161#define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1, 1 )
162#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 162#define MPP21_TSMP1 MPP( 21, 0x1, 0, 0, 0, 0, 1, 1, 1 )
163#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 163#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 0, 0, 0, 1, 1, 1 )
164#define MPP21_GE1_TXD1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 164#define MPP21_GE1_TXD1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1, 1 )
165#define MPP21_AU_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 165#define MPP21_AU_SPDIFO MPP( 21, 0x4, 0, 0, 0, 0, 1, 1, 1 )
166#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1, 1 ) 166#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 0, 0, 1, 1, 1, 1 )
167#define MPP21_LCD_D1 MPP( 21, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 167#define MPP21_LCD_D1 MPP( 21, 0xb, 0, 0, 0, 0, 0, 0, 1 )
168 168
169#define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 169#define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1, 1 )
170#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 170#define MPP22_TSMP2 MPP( 22, 0x1, 0, 0, 0, 0, 1, 1, 1 )
171#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 171#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 0, 0, 0, 1, 1, 1 )
172#define MPP22_GE1_TXD2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 172#define MPP22_GE1_TXD2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1, 1 )
173#define MPP22_AU_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 173#define MPP22_AU_SPDIFRMKCLK MPP( 22, 0x4, 0, 0, 0, 0, 1, 1, 1 )
174#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1, 1 ) 174#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 0, 0, 0, 1, 1, 1 )
175#define MPP22_LCD_D2 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 175#define MPP22_LCD_D2 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
176 176
177#define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 177#define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1, 1 )
178#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 178#define MPP23_TSMP3 MPP( 23, 0x1, 0, 0, 0, 0, 1, 1, 1 )
179#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1, 1 ) 179#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 0, 0, 0, 0, 1, 1, 1 )
180#define MPP23_GE1_TXD3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 180#define MPP23_GE1_TXD3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1, 1 )
181#define MPP23_AU_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 181#define MPP23_AU_I2SBCLK MPP( 23, 0x4, 0, 0, 0, 0, 1, 1, 1 )
182#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1, 1 ) 182#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 0, 0, 1, 1, 1, 1 )
183#define MPP23_LCD_D3 MPP( 23, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 183#define MPP23_LCD_D3 MPP( 23, 0xb, 0, 0, 0, 0, 0, 0, 1 )
184 184
185#define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 185#define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1, 1 )
186#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 186#define MPP24_TSMP4 MPP( 24, 0x1, 0, 0, 0, 0, 1, 1, 1 )
187#define MPP24_TDM_SPI_CS0 MPP( 24, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 187#define MPP24_TDM_SPI_CS0 MPP( 24, 0x2, 0, 0, 0, 0, 1, 1, 1 )
188#define MPP24_GE1_RXD0 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 188#define MPP24_GE1_RXD0 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1, 1 )
189#define MPP24_AU_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 189#define MPP24_AU_I2SDO MPP( 24, 0x4, 0, 0, 0, 0, 1, 1, 1 )
190#define MPP24_LCD_D4 MPP( 24, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 190#define MPP24_LCD_D4 MPP( 24, 0xb, 0, 0, 0, 0, 0, 0, 1 )
191 191
192#define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 192#define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1, 1 )
193#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 193#define MPP25_TSMP5 MPP( 25, 0x1, 0, 0, 0, 0, 1, 1, 1 )
194#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 194#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 0, 0, 0, 1, 1, 1 )
195#define MPP25_GE1_RXD1 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 195#define MPP25_GE1_RXD1 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1, 1 )
196#define MPP25_AU_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 196#define MPP25_AU_I2SLRCLK MPP( 25, 0x4, 0, 0, 0, 0, 1, 1, 1 )
197#define MPP25_LCD_D5 MPP( 25, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 197#define MPP25_LCD_D5 MPP( 25, 0xb, 0, 0, 0, 0, 0, 0, 1 )
198 198
199#define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 199#define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1, 1 )
200#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 200#define MPP26_TSMP6 MPP( 26, 0x1, 0, 0, 0, 0, 1, 1, 1 )
201#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1, 1 ) 201#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 0, 0, 0, 0, 1, 1, 1 )
202#define MPP26_GE1_RXD2 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 202#define MPP26_GE1_RXD2 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1, 1 )
203#define MPP26_AU_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1, 1 ) 203#define MPP26_AU_I2SMCLK MPP( 26, 0x4, 0, 0, 0, 0, 1, 1, 1 )
204#define MPP26_LCD_D6 MPP( 26, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 204#define MPP26_LCD_D6 MPP( 26, 0xb, 0, 0, 0, 0, 0, 0, 1 )
205 205
206#define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 206#define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1, 1 )
207#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 207#define MPP27_TSMP7 MPP( 27, 0x1, 0, 0, 0, 0, 1, 1, 1 )
208#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 208#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 0, 0, 0, 1, 1, 1 )
209#define MPP27_GE1_RXD3 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 209#define MPP27_GE1_RXD3 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1, 1 )
210#define MPP27_AU_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1, 1 ) 210#define MPP27_AU_I2SDI MPP( 27, 0x4, 0, 0, 0, 0, 1, 1, 1 )
211#define MPP27_LCD_D7 MPP( 27, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 211#define MPP27_LCD_D7 MPP( 27, 0xb, 0, 0, 0, 0, 0, 0, 1 )
212 212
213#define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 213#define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1, 1 )
214#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 214#define MPP28_TSMP8 MPP( 28, 0x1, 0, 0, 0, 0, 1, 1, 1 )
215#define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1, 1 ) 215#define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1, 1 )
216#define MPP28_GE1_COL MPP( 28, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 216#define MPP28_GE1_COL MPP( 28, 0x3, 0, 0, 0, 1, 1, 1, 1 )
217#define MPP28_AU_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1, 1 ) 217#define MPP28_AU_EXTCLK MPP( 28, 0x4, 0, 0, 0, 0, 1, 1, 1 )
218#define MPP28_LCD_D8 MPP( 28, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 218#define MPP28_LCD_D8 MPP( 28, 0xb, 0, 0, 0, 0, 0, 0, 1 )
219 219
220#define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 220#define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1, 1 )
221#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 221#define MPP29_TSMP9 MPP( 29, 0x1, 0, 0, 0, 0, 1, 1, 1 )
222#define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1, 1 ) 222#define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1, 1 )
223#define MPP29_GE1_TCLK MPP( 29, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 223#define MPP29_GE1_TCLK MPP( 29, 0x3, 0, 0, 0, 1, 1, 1, 1 )
224#define MPP29_LCD_D9 MPP( 29, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 224#define MPP29_LCD_D9 MPP( 29, 0xb, 0, 0, 0, 0, 0, 0, 1 )
225 225
226#define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 226#define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1, 1 )
227#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 227#define MPP30_TSMP10 MPP( 30, 0x1, 0, 0, 0, 0, 1, 1, 1 )
228#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1, 1 ) 228#define MPP30_TDM_PCLK MPP( 30, 0x2, 0, 0, 0, 0, 1, 1, 1 )
229#define MPP30_GE1_RXCTL MPP( 30, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 229#define MPP30_GE1_RXCTL MPP( 30, 0x3, 0, 0, 0, 1, 1, 1, 1 )
230#define MPP30_LCD_D10 MPP( 30, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 230#define MPP30_LCD_D10 MPP( 30, 0xb, 0, 0, 0, 0, 0, 0, 1 )
231 231
232#define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 232#define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1, 1 )
233#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 233#define MPP31_TSMP11 MPP( 31, 0x1, 0, 0, 0, 0, 1, 1, 1 )
234#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1, 1 ) 234#define MPP31_TDM_FS MPP( 31, 0x2, 0, 0, 0, 0, 1, 1, 1 )
235#define MPP31_GE1_RXCLK MPP( 31, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 235#define MPP31_GE1_RXCLK MPP( 31, 0x3, 0, 0, 0, 1, 1, 1, 1 )
236#define MPP31_LCD_D11 MPP( 31, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 236#define MPP31_LCD_D11 MPP( 31, 0xb, 0, 0, 0, 0, 0, 0, 1 )
237 237
238#define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 238#define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1, 1 )
239#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1, 1 ) 239#define MPP32_TSMP12 MPP( 32, 0x1, 0, 0, 0, 0, 1, 1, 1 )
240#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1, 1 ) 240#define MPP32_TDM_DRX MPP( 32, 0x2, 0, 0, 0, 0, 1, 1, 1 )
241#define MPP32_GE1_TCLKOUT MPP( 32, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 241#define MPP32_GE1_TCLKOUT MPP( 32, 0x3, 0, 0, 0, 1, 1, 1, 1 )
242#define MPP32_LCD_D12 MPP( 32, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 242#define MPP32_LCD_D12 MPP( 32, 0xb, 0, 0, 0, 0, 0, 0, 1 )
243 243
244#define MPP33_GPO MPP( 33, 0x0, 0, 1, 0, 1, 1, 1, 1 ) 244#define MPP33_GPO MPP( 33, 0x0, 0, 1, 0, 1, 1, 1, 1 )
245#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 245#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 0, 0, 0, 1, 1, 1 )
246#define MPP33_GE1_TXCTL MPP( 33, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 246#define MPP33_GE1_TXCTL MPP( 33, 0x3, 0, 0, 0, 1, 1, 1, 1 )
247#define MPP33_LCD_D13 MPP( 33, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 247#define MPP33_LCD_D13 MPP( 33, 0xb, 0, 0, 0, 0, 0, 0, 1 )
248 248
249#define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1, 1 ) 249#define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1, 1 )
250#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 250#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 0, 0, 0, 1, 1, 1 )
251#define MPP34_GE1_TXEN MPP( 34, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 251#define MPP34_GE1_TXEN MPP( 34, 0x3, 0, 0, 0, 1, 1, 1, 1 )
252#define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 1, 0, 0, 0, 1, 1 ) 252#define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 0, 0, 0, 0, 1, 1 )
253#define MPP34_LCD_D14 MPP( 34, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 253#define MPP34_LCD_D14 MPP( 34, 0xb, 0, 0, 0, 0, 0, 0, 1 )
254 254
255#define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1, 1 ) 255#define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1, 1 )
256#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1, 1 ) 256#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 0, 0, 0, 1, 1, 1 )
257#define MPP35_GE1_RXERR MPP( 35, 0x3, 0, 0, 0, 1, 1, 1, 1 ) 257#define MPP35_GE1_RXERR MPP( 35, 0x3, 0, 0, 0, 1, 1, 1, 1 )
258#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1, 1 ) 258#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 0, 0, 1, 1, 1, 1 )
259#define MPP35_LCD_D15 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 259#define MPP35_LCD_D15 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
260#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1, 1 ) 260#define MPP35_MII0_RXERR MPP( 35, 0xc, 0, 0, 1, 1, 1, 1, 1 )
261 261
262#define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 262#define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1, 1 )
263#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 263#define MPP36_TSMP0 MPP( 36, 0x1, 0, 0, 0, 0, 0, 1, 1 )
264#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 264#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 0, 0, 0, 0, 1, 1 )
265#define MPP36_AU_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1, 1 ) 265#define MPP36_AU_SPDIFI MPP( 36, 0x4, 0, 0, 1, 0, 0, 1, 1 )
266#define MPP36_TW1_SDA MPP( 36, 0xb, 1, 1, 0, 0, 0, 0, 1 ) 266#define MPP36_TW1_SDA MPP( 36, 0xb, 0, 0, 0, 0, 0, 0, 1 )
267 267
268#define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 268#define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1, 1 )
269#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 269#define MPP37_TSMP1 MPP( 37, 0x1, 0, 0, 0, 0, 0, 1, 1 )
270#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 270#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 0, 0, 0, 0, 1, 1 )
271#define MPP37_AU_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1, 1 ) 271#define MPP37_AU_SPDIFO MPP( 37, 0x4, 0, 0, 1, 0, 0, 1, 1 )
272#define MPP37_TW1_SCK MPP( 37, 0xb, 1, 1, 0, 0, 0, 0, 1 ) 272#define MPP37_TW1_SCK MPP( 37, 0xb, 0, 0, 0, 0, 0, 0, 1 )
273 273
274#define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 274#define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1, 1 )
275#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 275#define MPP38_TSMP2 MPP( 38, 0x1, 0, 0, 0, 0, 0, 1, 1 )
276#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 276#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 0, 0, 0, 0, 1, 1 )
277#define MPP38_AU_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1, 1 ) 277#define MPP38_AU_SPDIFRMLCLK MPP( 38, 0x4, 0, 0, 1, 0, 0, 1, 1 )
278#define MPP38_LCD_D18 MPP( 38, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 278#define MPP38_LCD_D18 MPP( 38, 0xb, 0, 0, 0, 0, 0, 0, 1 )
279 279
280#define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 280#define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1, 1 )
281#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 281#define MPP39_TSMP3 MPP( 39, 0x1, 0, 0, 0, 0, 0, 1, 1 )
282#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 282#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 0, 0, 0, 0, 1, 1 )
283#define MPP39_AU_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1, 1 ) 283#define MPP39_AU_I2SBCLK MPP( 39, 0x4, 0, 0, 1, 0, 0, 1, 1 )
284#define MPP39_LCD_D19 MPP( 39, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 284#define MPP39_LCD_D19 MPP( 39, 0xb, 0, 0, 0, 0, 0, 0, 1 )
285 285
286#define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 286#define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1, 1 )
287#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 287#define MPP40_TSMP4 MPP( 40, 0x1, 0, 0, 0, 0, 0, 1, 1 )
288#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 288#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 0, 0, 0, 0, 1, 1 )
289#define MPP40_AU_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1, 1 ) 289#define MPP40_AU_I2SDO MPP( 40, 0x4, 0, 0, 1, 0, 0, 1, 1 )
290#define MPP40_LCD_D20 MPP( 40, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 290#define MPP40_LCD_D20 MPP( 40, 0xb, 0, 0, 0, 0, 0, 0, 1 )
291 291
292#define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 292#define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1, 1 )
293#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 293#define MPP41_TSMP5 MPP( 41, 0x1, 0, 0, 0, 0, 0, 1, 1 )
294#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1, 1 ) 294#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 0, 0, 0, 0, 0, 1, 1 )
295#define MPP41_AU_I2SLRCLK MPP( 41, 0x4, 0, 1, 1, 0, 0, 1, 1 ) 295#define MPP41_AU_I2SLRCLK MPP( 41, 0x4, 0, 0, 1, 0, 0, 1, 1 )
296#define MPP41_LCD_D21 MPP( 41, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 296#define MPP41_LCD_D21 MPP( 41, 0xb, 0, 0, 0, 0, 0, 0, 1 )
297 297
298#define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 298#define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1, 1 )
299#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 299#define MPP42_TSMP6 MPP( 42, 0x1, 0, 0, 0, 0, 0, 1, 1 )
300#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 300#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 0, 0, 0, 0, 1, 1 )
301#define MPP42_AU_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1, 1 ) 301#define MPP42_AU_I2SMCLK MPP( 42, 0x4, 0, 0, 1, 0, 0, 1, 1 )
302#define MPP42_LCD_D22 MPP( 42, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 302#define MPP42_LCD_D22 MPP( 42, 0xb, 0, 0, 0, 0, 0, 0, 1 )
303 303
304#define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 304#define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1, 1 )
305#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 305#define MPP43_TSMP7 MPP( 43, 0x1, 0, 0, 0, 0, 0, 1, 1 )
306#define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1, 1 ) 306#define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1, 1 )
307#define MPP43_AU_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1, 1 ) 307#define MPP43_AU_I2SDI MPP( 43, 0x4, 0, 0, 1, 0, 0, 1, 1 )
308#define MPP43_LCD_D23 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 308#define MPP43_LCD_D23 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
309 309
310#define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1, 1 ) 310#define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1, 1 )
311#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 311#define MPP44_TSMP8 MPP( 44, 0x1, 0, 0, 0, 0, 0, 1, 1 )
312#define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1, 1 ) 312#define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1, 1 )
313#define MPP44_AU_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1, 1 ) 313#define MPP44_AU_EXTCLK MPP( 44, 0x4, 0, 0, 1, 0, 0, 1, 1 )
314#define MPP44_LCD_CLK MPP( 44, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 314#define MPP44_LCD_CLK MPP( 44, 0xb, 0, 0, 0, 0, 0, 0, 1 )
315 315
316#define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1, 1 ) 316#define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1, 1 )
317#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 317#define MPP45_TSMP9 MPP( 45, 0x1, 0, 0, 0, 0, 0, 1, 1 )
318#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1, 1 ) 318#define MPP45_TDM_PCLK MPP( 45, 0x2, 0, 0, 0, 0, 0, 1, 1 )
319#define MPP245_LCD_E MPP( 45, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 319#define MPP245_LCD_E MPP( 45, 0xb, 0, 0, 0, 0, 0, 0, 1 )
320 320
321#define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1, 1 ) 321#define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1, 1 )
322#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 322#define MPP46_TSMP10 MPP( 46, 0x1, 0, 0, 0, 0, 0, 1, 1 )
323#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1, 1 ) 323#define MPP46_TDM_FS MPP( 46, 0x2, 0, 0, 0, 0, 0, 1, 1 )
324#define MPP46_LCD_HSYNC MPP( 46, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 324#define MPP46_LCD_HSYNC MPP( 46, 0xb, 0, 0, 0, 0, 0, 0, 1 )
325 325
326#define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1, 1 ) 326#define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1, 1 )
327#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 327#define MPP47_TSMP11 MPP( 47, 0x1, 0, 0, 0, 0, 0, 1, 1 )
328#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1, 1 ) 328#define MPP47_TDM_DRX MPP( 47, 0x2, 0, 0, 0, 0, 0, 1, 1 )
329#define MPP47_LCD_VSYNC MPP( 47, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 329#define MPP47_LCD_VSYNC MPP( 47, 0xb, 0, 0, 0, 0, 0, 0, 1 )
330 330
331#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1, 1 ) 331#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1, 1 )
332#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1, 1 ) 332#define MPP48_TSMP12 MPP( 48, 0x1, 0, 0, 0, 0, 0, 1, 1 )
333#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 333#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 0, 0, 0, 0, 1, 1 )
334#define MPP48_LCD_D16 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 334#define MPP48_LCD_D16 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
335 335
336#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1, 0 ) 336#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1, 0 )
337#define MPP49_GPO MPP( 49, 0x0, 0, 1, 0, 0, 0, 0, 1 ) 337#define MPP49_GPO MPP( 49, 0x0, 0, 1, 0, 0, 0, 0, 1 )
338#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1, 0 ) 338#define MPP49_TSMP9 MPP( 49, 0x1, 0, 0, 0, 0, 0, 1, 0 )
339#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1, 1 ) 339#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 0, 0, 0, 0, 1, 1 )
340#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1, 0 ) 340#define MPP49_PTP_CLK MPP( 49, 0x5, 0, 0, 0, 0, 0, 1, 0 )
341#define MPP49_PEX0_CLKREQ MPP( 49, 0xa, 0, 1, 0, 0, 0, 0, 1 ) 341#define MPP49_PEX0_CLKREQ MPP( 49, 0xa, 0, 0, 0, 0, 0, 0, 1 )
342#define MPP49_LCD_D17 MPP( 49, 0xb, 0, 0, 0, 0, 0, 0, 1 ) 342#define MPP49_LCD_D17 MPP( 49, 0xb, 0, 0, 0, 0, 0, 0, 1 )
343 343
344#define MPP_MAX 49 344#define MPP_MAX 49
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 0cdd41004ad0..a5dcf766a3f9 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -19,6 +19,7 @@
19#include <mach/mv78xx0.h> 19#include <mach/mv78xx0.h>
20#include <mach/bridge-regs.h> 20#include <mach/bridge-regs.h>
21#include <plat/cache-feroceon-l2.h> 21#include <plat/cache-feroceon-l2.h>
22#include <plat/ehci-orion.h>
22#include <plat/orion_nand.h> 23#include <plat/orion_nand.h>
23#include <plat/time.h> 24#include <plat/time.h>
24#include <plat/common.h> 25#include <plat/common.h>
@@ -169,7 +170,7 @@ void __init mv78xx0_map_io(void)
169 ****************************************************************************/ 170 ****************************************************************************/
170void __init mv78xx0_ehci0_init(void) 171void __init mv78xx0_ehci0_init(void)
171{ 172{
172 orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0); 173 orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA);
173} 174}
174 175
175 176
diff --git a/arch/arm/mach-mv78xx0/mpp.h b/arch/arm/mach-mv78xx0/mpp.h
index b61b50927123..3752302ae2ee 100644
--- a/arch/arm/mach-mv78xx0/mpp.h
+++ b/arch/arm/mach-mv78xx0/mpp.h
@@ -24,296 +24,296 @@
24#define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1) 24#define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1)
25 25
26#define MPP0_GPIO MPP(0, 0x0, 1, 1, 1) 26#define MPP0_GPIO MPP(0, 0x0, 1, 1, 1)
27#define MPP0_GE0_COL MPP(0, 0x1, 1, 0, 1) 27#define MPP0_GE0_COL MPP(0, 0x1, 0, 0, 1)
28#define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 1, 1) 28#define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 0, 1)
29#define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1) 29#define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1)
30 30
31#define MPP1_GPIO MPP(1, 0x0, 1, 1, 1) 31#define MPP1_GPIO MPP(1, 0x0, 1, 1, 1)
32#define MPP1_GE0_RXERR MPP(1, 0x1, 1, 0, 1) 32#define MPP1_GE0_RXERR MPP(1, 0x1, 0, 0, 1)
33#define MPP1_GE1_TXCTL MPP(1, 0x2, 0, 1, 1) 33#define MPP1_GE1_TXCTL MPP(1, 0x2, 0, 0, 1)
34#define MPP1_UNUSED MPP(1, 0x3, 0, 0, 1) 34#define MPP1_UNUSED MPP(1, 0x3, 0, 0, 1)
35 35
36#define MPP2_GPIO MPP(2, 0x0, 1, 1, 1) 36#define MPP2_GPIO MPP(2, 0x0, 1, 1, 1)
37#define MPP2_GE0_CRS MPP(2, 0x1, 1, 0, 1) 37#define MPP2_GE0_CRS MPP(2, 0x1, 0, 0, 1)
38#define MPP2_GE1_RXCTL MPP(2, 0x2, 1, 0, 1) 38#define MPP2_GE1_RXCTL MPP(2, 0x2, 0, 0, 1)
39#define MPP2_UNUSED MPP(2, 0x3, 0, 0, 1) 39#define MPP2_UNUSED MPP(2, 0x3, 0, 0, 1)
40 40
41#define MPP3_GPIO MPP(3, 0x0, 1, 1, 1) 41#define MPP3_GPIO MPP(3, 0x0, 1, 1, 1)
42#define MPP3_GE0_TXERR MPP(3, 0x1, 0, 1, 1) 42#define MPP3_GE0_TXERR MPP(3, 0x1, 0, 0, 1)
43#define MPP3_GE1_RXCLK MPP(3, 0x2, 1, 0, 1) 43#define MPP3_GE1_RXCLK MPP(3, 0x2, 0, 0, 1)
44#define MPP3_UNUSED MPP(3, 0x3, 0, 0, 1) 44#define MPP3_UNUSED MPP(3, 0x3, 0, 0, 1)
45 45
46#define MPP4_GPIO MPP(4, 0x0, 1, 1, 1) 46#define MPP4_GPIO MPP(4, 0x0, 1, 1, 1)
47#define MPP4_GE0_TXD4 MPP(4, 0x1, 0, 1, 1) 47#define MPP4_GE0_TXD4 MPP(4, 0x1, 0, 0, 1)
48#define MPP4_GE1_TXD0 MPP(4, 0x2, 0, 1, 1) 48#define MPP4_GE1_TXD0 MPP(4, 0x2, 0, 0, 1)
49#define MPP4_UNUSED MPP(4, 0x3, 0, 0, 1) 49#define MPP4_UNUSED MPP(4, 0x3, 0, 0, 1)
50 50
51#define MPP5_GPIO MPP(5, 0x0, 1, 1, 1) 51#define MPP5_GPIO MPP(5, 0x0, 1, 1, 1)
52#define MPP5_GE0_TXD5 MPP(5, 0x1, 0, 1, 1) 52#define MPP5_GE0_TXD5 MPP(5, 0x1, 0, 0, 1)
53#define MPP5_GE1_TXD1 MPP(5, 0x2, 0, 1, 1) 53#define MPP5_GE1_TXD1 MPP(5, 0x2, 0, 0, 1)
54#define MPP5_UNUSED MPP(5, 0x3, 0, 0, 1) 54#define MPP5_UNUSED MPP(5, 0x3, 0, 0, 1)
55 55
56#define MPP6_GPIO MPP(6, 0x0, 1, 1, 1) 56#define MPP6_GPIO MPP(6, 0x0, 1, 1, 1)
57#define MPP6_GE0_TXD6 MPP(6, 0x1, 0, 1, 1) 57#define MPP6_GE0_TXD6 MPP(6, 0x1, 0, 0, 1)
58#define MPP6_GE1_TXD2 MPP(6, 0x2, 0, 1, 1) 58#define MPP6_GE1_TXD2 MPP(6, 0x2, 0, 0, 1)
59#define MPP6_UNUSED MPP(6, 0x3, 0, 0, 1) 59#define MPP6_UNUSED MPP(6, 0x3, 0, 0, 1)
60 60
61#define MPP7_GPIO MPP(7, 0x0, 1, 1, 1) 61#define MPP7_GPIO MPP(7, 0x0, 1, 1, 1)
62#define MPP7_GE0_TXD7 MPP(7, 0x1, 0, 1, 1) 62#define MPP7_GE0_TXD7 MPP(7, 0x1, 0, 0, 1)
63#define MPP7_GE1_TXD3 MPP(7, 0x2, 0, 1, 1) 63#define MPP7_GE1_TXD3 MPP(7, 0x2, 0, 0, 1)
64#define MPP7_UNUSED MPP(7, 0x3, 0, 0, 1) 64#define MPP7_UNUSED MPP(7, 0x3, 0, 0, 1)
65 65
66#define MPP8_GPIO MPP(8, 0x0, 1, 1, 1) 66#define MPP8_GPIO MPP(8, 0x0, 1, 1, 1)
67#define MPP8_GE0_RXD4 MPP(8, 0x1, 1, 0, 1) 67#define MPP8_GE0_RXD4 MPP(8, 0x1, 0, 0, 1)
68#define MPP8_GE1_RXD0 MPP(8, 0x2, 1, 0, 1) 68#define MPP8_GE1_RXD0 MPP(8, 0x2, 0, 0, 1)
69#define MPP8_UNUSED MPP(8, 0x3, 0, 0, 1) 69#define MPP8_UNUSED MPP(8, 0x3, 0, 0, 1)
70 70
71#define MPP9_GPIO MPP(9, 0x0, 1, 1, 1) 71#define MPP9_GPIO MPP(9, 0x0, 1, 1, 1)
72#define MPP9_GE0_RXD5 MPP(9, 0x1, 1, 0, 1) 72#define MPP9_GE0_RXD5 MPP(9, 0x1, 0, 0, 1)
73#define MPP9_GE1_RXD1 MPP(9, 0x2, 1, 0, 1) 73#define MPP9_GE1_RXD1 MPP(9, 0x2, 0, 0, 1)
74#define MPP9_UNUSED MPP(9, 0x3, 0, 0, 1) 74#define MPP9_UNUSED MPP(9, 0x3, 0, 0, 1)
75 75
76#define MPP10_GPIO MPP(10, 0x0, 1, 1, 1) 76#define MPP10_GPIO MPP(10, 0x0, 1, 1, 1)
77#define MPP10_GE0_RXD6 MPP(10, 0x1, 1, 0, 1) 77#define MPP10_GE0_RXD6 MPP(10, 0x1, 0, 0, 1)
78#define MPP10_GE1_RXD2 MPP(10, 0x2, 1, 0, 1) 78#define MPP10_GE1_RXD2 MPP(10, 0x2, 0, 0, 1)
79#define MPP10_UNUSED MPP(10, 0x3, 0, 0, 1) 79#define MPP10_UNUSED MPP(10, 0x3, 0, 0, 1)
80 80
81#define MPP11_GPIO MPP(11, 0x0, 1, 1, 1) 81#define MPP11_GPIO MPP(11, 0x0, 1, 1, 1)
82#define MPP11_GE0_RXD7 MPP(11, 0x1, 1, 0, 1) 82#define MPP11_GE0_RXD7 MPP(11, 0x1, 0, 0, 1)
83#define MPP11_GE1_RXD3 MPP(11, 0x2, 1, 0, 1) 83#define MPP11_GE1_RXD3 MPP(11, 0x2, 0, 0, 1)
84#define MPP11_UNUSED MPP(11, 0x3, 0, 0, 1) 84#define MPP11_UNUSED MPP(11, 0x3, 0, 0, 1)
85 85
86#define MPP12_GPIO MPP(12, 0x0, 1, 1, 1) 86#define MPP12_GPIO MPP(12, 0x0, 1, 1, 1)
87#define MPP12_M_BB MPP(12, 0x3, 1, 0, 1) 87#define MPP12_M_BB MPP(12, 0x3, 0, 0, 1)
88#define MPP12_UA0_CTSn MPP(12, 0x4, 1, 0, 1) 88#define MPP12_UA0_CTSn MPP(12, 0x4, 0, 0, 1)
89#define MPP12_NAND_FLASH_REn0 MPP(12, 0x5, 0, 1, 1) 89#define MPP12_NAND_FLASH_REn0 MPP(12, 0x5, 0, 0, 1)
90#define MPP12_TDM0_SCSn MPP(12, 0X6, 0, 1, 1) 90#define MPP12_TDM0_SCSn MPP(12, 0X6, 0, 0, 1)
91#define MPP12_UNUSED MPP(12, 0x1, 0, 0, 1) 91#define MPP12_UNUSED MPP(12, 0x1, 0, 0, 1)
92 92
93#define MPP13_GPIO MPP(13, 0x0, 1, 1, 1) 93#define MPP13_GPIO MPP(13, 0x0, 1, 1, 1)
94#define MPP13_SYSRST_OUTn MPP(13, 0x3, 0, 1, 1) 94#define MPP13_SYSRST_OUTn MPP(13, 0x3, 0, 0, 1)
95#define MPP13_UA0_RTSn MPP(13, 0x4, 0, 1, 1) 95#define MPP13_UA0_RTSn MPP(13, 0x4, 0, 0, 1)
96#define MPP13_NAN_FLASH_WEn0 MPP(13, 0x5, 0, 1, 1) 96#define MPP13_NAN_FLASH_WEn0 MPP(13, 0x5, 0, 0, 1)
97#define MPP13_TDM_SCLK MPP(13, 0x6, 0, 1, 1) 97#define MPP13_TDM_SCLK MPP(13, 0x6, 0, 0, 1)
98#define MPP13_UNUSED MPP(13, 0x1, 0, 0, 1) 98#define MPP13_UNUSED MPP(13, 0x1, 0, 0, 1)
99 99
100#define MPP14_GPIO MPP(14, 0x0, 1, 1, 1) 100#define MPP14_GPIO MPP(14, 0x0, 1, 1, 1)
101#define MPP14_SATA1_ACTn MPP(14, 0x3, 0, 1, 1) 101#define MPP14_SATA1_ACTn MPP(14, 0x3, 0, 0, 1)
102#define MPP14_UA1_CTSn MPP(14, 0x4, 1, 0, 1) 102#define MPP14_UA1_CTSn MPP(14, 0x4, 0, 0, 1)
103#define MPP14_NAND_FLASH_REn1 MPP(14, 0x5, 0, 1, 1) 103#define MPP14_NAND_FLASH_REn1 MPP(14, 0x5, 0, 0, 1)
104#define MPP14_TDM_SMOSI MPP(14, 0x6, 0, 1, 1) 104#define MPP14_TDM_SMOSI MPP(14, 0x6, 0, 0, 1)
105#define MPP14_UNUSED MPP(14, 0x1, 0, 0, 1) 105#define MPP14_UNUSED MPP(14, 0x1, 0, 0, 1)
106 106
107#define MPP15_GPIO MPP(15, 0x0, 1, 1, 1) 107#define MPP15_GPIO MPP(15, 0x0, 1, 1, 1)
108#define MPP15_SATA0_ACTn MPP(15, 0x3, 0, 1, 1) 108#define MPP15_SATA0_ACTn MPP(15, 0x3, 0, 0, 1)
109#define MPP15_UA1_RTSn MPP(15, 0x4, 0, 1, 1) 109#define MPP15_UA1_RTSn MPP(15, 0x4, 0, 0, 1)
110#define MPP15_NAND_FLASH_WEn1 MPP(15, 0x5, 0, 1, 1) 110#define MPP15_NAND_FLASH_WEn1 MPP(15, 0x5, 0, 0, 1)
111#define MPP15_TDM_SMISO MPP(15, 0x6, 1, 0, 1) 111#define MPP15_TDM_SMISO MPP(15, 0x6, 0, 0, 1)
112#define MPP15_UNUSED MPP(15, 0x1, 0, 0, 1) 112#define MPP15_UNUSED MPP(15, 0x1, 0, 0, 1)
113 113
114#define MPP16_GPIO MPP(16, 0x0, 1, 1, 1) 114#define MPP16_GPIO MPP(16, 0x0, 1, 1, 1)
115#define MPP16_SATA1_PRESENTn MPP(16, 0x3, 0, 1, 1) 115#define MPP16_SATA1_PRESENTn MPP(16, 0x3, 0, 0, 1)
116#define MPP16_UA2_TXD MPP(16, 0x4, 0, 1, 1) 116#define MPP16_UA2_TXD MPP(16, 0x4, 0, 0, 1)
117#define MPP16_NAND_FLASH_REn3 MPP(16, 0x5, 0, 1, 1) 117#define MPP16_NAND_FLASH_REn3 MPP(16, 0x5, 0, 0, 1)
118#define MPP16_TDM_INTn MPP(16, 0x6, 1, 0, 1) 118#define MPP16_TDM_INTn MPP(16, 0x6, 0, 0, 1)
119#define MPP16_UNUSED MPP(16, 0x1, 0, 0, 1) 119#define MPP16_UNUSED MPP(16, 0x1, 0, 0, 1)
120 120
121 121
122#define MPP17_GPIO MPP(17, 0x0, 1, 1, 1) 122#define MPP17_GPIO MPP(17, 0x0, 1, 1, 1)
123#define MPP17_SATA0_PRESENTn MPP(17, 0x3, 0, 1, 1) 123#define MPP17_SATA0_PRESENTn MPP(17, 0x3, 0, 0, 1)
124#define MPP17_UA2_RXD MPP(17, 0x4, 1, 0, 1) 124#define MPP17_UA2_RXD MPP(17, 0x4, 0, 0, 1)
125#define MPP17_NAND_FLASH_WEn3 MPP(17, 0x5, 0, 1, 1) 125#define MPP17_NAND_FLASH_WEn3 MPP(17, 0x5, 0, 0, 1)
126#define MPP17_TDM_RSTn MPP(17, 0x6, 0, 1, 1) 126#define MPP17_TDM_RSTn MPP(17, 0x6, 0, 0, 1)
127#define MPP17_UNUSED MPP(17, 0x1, 0, 0, 1) 127#define MPP17_UNUSED MPP(17, 0x1, 0, 0, 1)
128 128
129 129
130#define MPP18_GPIO MPP(18, 0x0, 1, 1, 1) 130#define MPP18_GPIO MPP(18, 0x0, 1, 1, 1)
131#define MPP18_UA0_CTSn MPP(18, 0x4, 1, 0, 1) 131#define MPP18_UA0_CTSn MPP(18, 0x4, 0, 0, 1)
132#define MPP18_BOOT_FLASH_REn MPP(18, 0x5, 0, 1, 1) 132#define MPP18_BOOT_FLASH_REn MPP(18, 0x5, 0, 0, 1)
133#define MPP18_UNUSED MPP(18, 0x1, 0, 0, 1) 133#define MPP18_UNUSED MPP(18, 0x1, 0, 0, 1)
134 134
135 135
136 136
137#define MPP19_GPIO MPP(19, 0x0, 1, 1, 1) 137#define MPP19_GPIO MPP(19, 0x0, 1, 1, 1)
138#define MPP19_UA0_CTSn MPP(19, 0x4, 0, 1, 1) 138#define MPP19_UA0_CTSn MPP(19, 0x4, 0, 0, 1)
139#define MPP19_BOOT_FLASH_WEn MPP(19, 0x5, 0, 1, 1) 139#define MPP19_BOOT_FLASH_WEn MPP(19, 0x5, 0, 0, 1)
140#define MPP19_UNUSED MPP(19, 0x1, 0, 0, 1) 140#define MPP19_UNUSED MPP(19, 0x1, 0, 0, 1)
141 141
142 142
143#define MPP20_GPIO MPP(20, 0x0, 1, 1, 1) 143#define MPP20_GPIO MPP(20, 0x0, 1, 1, 1)
144#define MPP20_UA1_CTSs MPP(20, 0x4, 1, 0, 1) 144#define MPP20_UA1_CTSs MPP(20, 0x4, 0, 0, 1)
145#define MPP20_TDM_PCLK MPP(20, 0x6, 1, 1, 0) 145#define MPP20_TDM_PCLK MPP(20, 0x6, 0, 0, 0)
146#define MPP20_UNUSED MPP(20, 0x1, 0, 0, 1) 146#define MPP20_UNUSED MPP(20, 0x1, 0, 0, 1)
147 147
148 148
149 149
150#define MPP21_GPIO MPP(21, 0x0, 1, 1, 1) 150#define MPP21_GPIO MPP(21, 0x0, 1, 1, 1)
151#define MPP21_UA1_CTSs MPP(21, 0x4, 0, 1, 1) 151#define MPP21_UA1_CTSs MPP(21, 0x4, 0, 0, 1)
152#define MPP21_TDM_FSYNC MPP(21, 0x6, 1, 1, 0) 152#define MPP21_TDM_FSYNC MPP(21, 0x6, 0, 0, 0)
153#define MPP21_UNUSED MPP(21, 0x1, 0, 0, 1) 153#define MPP21_UNUSED MPP(21, 0x1, 0, 0, 1)
154 154
155 155
156 156
157#define MPP22_GPIO MPP(22, 0x0, 1, 1, 1) 157#define MPP22_GPIO MPP(22, 0x0, 1, 1, 1)
158#define MPP22_UA3_TDX MPP(22, 0x4, 0, 1, 1) 158#define MPP22_UA3_TDX MPP(22, 0x4, 0, 0, 1)
159#define MPP22_NAND_FLASH_REn2 MPP(22, 0x5, 0, 1, 1) 159#define MPP22_NAND_FLASH_REn2 MPP(22, 0x5, 0, 0, 1)
160#define MPP22_TDM_DRX MPP(22, 0x6, 1, 0, 1) 160#define MPP22_TDM_DRX MPP(22, 0x6, 0, 0, 1)
161#define MPP22_UNUSED MPP(22, 0x1, 0, 0, 1) 161#define MPP22_UNUSED MPP(22, 0x1, 0, 0, 1)
162 162
163 163
164 164
165#define MPP23_GPIO MPP(23, 0x0, 1, 1, 1) 165#define MPP23_GPIO MPP(23, 0x0, 1, 1, 1)
166#define MPP23_UA3_RDX MPP(23, 0x4, 1, 0, 1) 166#define MPP23_UA3_RDX MPP(23, 0x4, 0, 0, 1)
167#define MPP23_NAND_FLASH_WEn2 MPP(23, 0x5, 0, 1, 1) 167#define MPP23_NAND_FLASH_WEn2 MPP(23, 0x5, 0, 0, 1)
168#define MPP23_TDM_DTX MPP(23, 0x6, 0, 1, 1) 168#define MPP23_TDM_DTX MPP(23, 0x6, 0, 0, 1)
169#define MPP23_UNUSED MPP(23, 0x1, 0, 0, 1) 169#define MPP23_UNUSED MPP(23, 0x1, 0, 0, 1)
170 170
171 171
172#define MPP24_GPIO MPP(24, 0x0, 1, 1, 1) 172#define MPP24_GPIO MPP(24, 0x0, 1, 1, 1)
173#define MPP24_UA2_TXD MPP(24, 0x4, 0, 1, 1) 173#define MPP24_UA2_TXD MPP(24, 0x4, 0, 0, 1)
174#define MPP24_TDM_INTn MPP(24, 0x6, 1, 0, 1) 174#define MPP24_TDM_INTn MPP(24, 0x6, 0, 0, 1)
175#define MPP24_UNUSED MPP(24, 0x1, 0, 0, 1) 175#define MPP24_UNUSED MPP(24, 0x1, 0, 0, 1)
176 176
177 177
178#define MPP25_GPIO MPP(25, 0x0, 1, 1, 1) 178#define MPP25_GPIO MPP(25, 0x0, 1, 1, 1)
179#define MPP25_UA2_RXD MPP(25, 0x4, 1, 0, 1) 179#define MPP25_UA2_RXD MPP(25, 0x4, 0, 0, 1)
180#define MPP25_TDM_RSTn MPP(25, 0x6, 0, 1, 1) 180#define MPP25_TDM_RSTn MPP(25, 0x6, 0, 0, 1)
181#define MPP25_UNUSED MPP(25, 0x1, 0, 0, 1) 181#define MPP25_UNUSED MPP(25, 0x1, 0, 0, 1)
182 182
183 183
184#define MPP26_GPIO MPP(26, 0x0, 1, 1, 1) 184#define MPP26_GPIO MPP(26, 0x0, 1, 1, 1)
185#define MPP26_UA2_CTSn MPP(26, 0x4, 1, 0, 1) 185#define MPP26_UA2_CTSn MPP(26, 0x4, 0, 0, 1)
186#define MPP26_TDM_PCLK MPP(26, 0x6, 1, 1, 1) 186#define MPP26_TDM_PCLK MPP(26, 0x6, 0, 0, 1)
187#define MPP26_UNUSED MPP(26, 0x1, 0, 0, 1) 187#define MPP26_UNUSED MPP(26, 0x1, 0, 0, 1)
188 188
189 189
190#define MPP27_GPIO MPP(27, 0x0, 1, 1, 1) 190#define MPP27_GPIO MPP(27, 0x0, 1, 1, 1)
191#define MPP27_UA2_RTSn MPP(27, 0x4, 0, 1, 1) 191#define MPP27_UA2_RTSn MPP(27, 0x4, 0, 0, 1)
192#define MPP27_TDM_FSYNC MPP(27, 0x6, 1, 1, 1) 192#define MPP27_TDM_FSYNC MPP(27, 0x6, 0, 0, 1)
193#define MPP27_UNUSED MPP(27, 0x1, 0, 0, 1) 193#define MPP27_UNUSED MPP(27, 0x1, 0, 0, 1)
194 194
195 195
196#define MPP28_GPIO MPP(28, 0x0, 1, 1, 1) 196#define MPP28_GPIO MPP(28, 0x0, 1, 1, 1)
197#define MPP28_UA3_TXD MPP(28, 0x4, 0, 1, 1) 197#define MPP28_UA3_TXD MPP(28, 0x4, 0, 0, 1)
198#define MPP28_TDM_DRX MPP(28, 0x6, 1, 0, 1) 198#define MPP28_TDM_DRX MPP(28, 0x6, 0, 0, 1)
199#define MPP28_UNUSED MPP(28, 0x1, 0, 0, 1) 199#define MPP28_UNUSED MPP(28, 0x1, 0, 0, 1)
200 200
201#define MPP29_GPIO MPP(29, 0x0, 1, 1, 1) 201#define MPP29_GPIO MPP(29, 0x0, 1, 1, 1)
202#define MPP29_UA3_RXD MPP(29, 0x4, 1, 0, 1) 202#define MPP29_UA3_RXD MPP(29, 0x4, 0, 0, 1)
203#define MPP29_SYSRST_OUTn MPP(29, 0x5, 0, 1, 1) 203#define MPP29_SYSRST_OUTn MPP(29, 0x5, 0, 0, 1)
204#define MPP29_TDM_DTX MPP(29, 0x6, 0, 1, 1) 204#define MPP29_TDM_DTX MPP(29, 0x6, 0, 0, 1)
205#define MPP29_UNUSED MPP(29, 0x1, 0, 0, 1) 205#define MPP29_UNUSED MPP(29, 0x1, 0, 0, 1)
206 206
207#define MPP30_GPIO MPP(30, 0x0, 1, 1, 1) 207#define MPP30_GPIO MPP(30, 0x0, 1, 1, 1)
208#define MPP30_UA3_CTSn MPP(30, 0x4, 1, 0, 1) 208#define MPP30_UA3_CTSn MPP(30, 0x4, 0, 0, 1)
209#define MPP30_UNUSED MPP(30, 0x1, 0, 0, 1) 209#define MPP30_UNUSED MPP(30, 0x1, 0, 0, 1)
210 210
211#define MPP31_GPIO MPP(31, 0x0, 1, 1, 1) 211#define MPP31_GPIO MPP(31, 0x0, 1, 1, 1)
212#define MPP31_UA3_RTSn MPP(31, 0x4, 0, 1, 1) 212#define MPP31_UA3_RTSn MPP(31, 0x4, 0, 0, 1)
213#define MPP31_TDM1_SCSn MPP(31, 0x6, 0, 1, 1) 213#define MPP31_TDM1_SCSn MPP(31, 0x6, 0, 0, 1)
214#define MPP31_UNUSED MPP(31, 0x1, 0, 0, 1) 214#define MPP31_UNUSED MPP(31, 0x1, 0, 0, 1)
215 215
216 216
217#define MPP32_GPIO MPP(32, 0x1, 1, 1, 1) 217#define MPP32_GPIO MPP(32, 0x1, 1, 1, 1)
218#define MPP32_UA3_TDX MPP(32, 0x4, 0, 1, 1) 218#define MPP32_UA3_TDX MPP(32, 0x4, 0, 0, 1)
219#define MPP32_SYSRST_OUTn MPP(32, 0x5, 0, 1, 1) 219#define MPP32_SYSRST_OUTn MPP(32, 0x5, 0, 0, 1)
220#define MPP32_TDM0_RXQ MPP(32, 0x6, 0, 1, 1) 220#define MPP32_TDM0_RXQ MPP(32, 0x6, 0, 0, 1)
221#define MPP32_UNUSED MPP(32, 0x3, 0, 0, 1) 221#define MPP32_UNUSED MPP(32, 0x3, 0, 0, 1)
222 222
223 223
224#define MPP33_GPIO MPP(33, 0x1, 1, 1, 1) 224#define MPP33_GPIO MPP(33, 0x1, 1, 1, 1)
225#define MPP33_UA3_RDX MPP(33, 0x4, 1, 0, 1) 225#define MPP33_UA3_RDX MPP(33, 0x4, 0, 0, 1)
226#define MPP33_TDM0_TXQ MPP(33, 0x6, 0, 1, 1) 226#define MPP33_TDM0_TXQ MPP(33, 0x6, 0, 0, 1)
227#define MPP33_UNUSED MPP(33, 0x3, 0, 0, 1) 227#define MPP33_UNUSED MPP(33, 0x3, 0, 0, 1)
228 228
229 229
230 230
231#define MPP34_GPIO MPP(34, 0x1, 1, 1, 1) 231#define MPP34_GPIO MPP(34, 0x1, 1, 1, 1)
232#define MPP34_UA2_TDX MPP(34, 0x4, 0, 1, 1) 232#define MPP34_UA2_TDX MPP(34, 0x4, 0, 0, 1)
233#define MPP34_TDM1_RXQ MPP(34, 0x6, 0, 1, 1) 233#define MPP34_TDM1_RXQ MPP(34, 0x6, 0, 0, 1)
234#define MPP34_UNUSED MPP(34, 0x3, 0, 0, 1) 234#define MPP34_UNUSED MPP(34, 0x3, 0, 0, 1)
235 235
236 236
237 237
238#define MPP35_GPIO MPP(35, 0x1, 1, 1, 1) 238#define MPP35_GPIO MPP(35, 0x1, 1, 1, 1)
239#define MPP35_UA2_RDX MPP(35, 0x4, 1, 0, 1) 239#define MPP35_UA2_RDX MPP(35, 0x4, 0, 0, 1)
240#define MPP35_TDM1_TXQ MPP(35, 0x6, 0, 1, 1) 240#define MPP35_TDM1_TXQ MPP(35, 0x6, 0, 0, 1)
241#define MPP35_UNUSED MPP(35, 0x3, 0, 0, 1) 241#define MPP35_UNUSED MPP(35, 0x3, 0, 0, 1)
242 242
243#define MPP36_GPIO MPP(36, 0x1, 1, 1, 1) 243#define MPP36_GPIO MPP(36, 0x1, 1, 1, 1)
244#define MPP36_UA0_CTSn MPP(36, 0x2, 1, 0, 1) 244#define MPP36_UA0_CTSn MPP(36, 0x2, 0, 0, 1)
245#define MPP36_UA2_TDX MPP(36, 0x4, 0, 1, 1) 245#define MPP36_UA2_TDX MPP(36, 0x4, 0, 0, 1)
246#define MPP36_TDM0_SCSn MPP(36, 0x6, 0, 1, 1) 246#define MPP36_TDM0_SCSn MPP(36, 0x6, 0, 0, 1)
247#define MPP36_UNUSED MPP(36, 0x3, 0, 0, 1) 247#define MPP36_UNUSED MPP(36, 0x3, 0, 0, 1)
248 248
249 249
250#define MPP37_GPIO MPP(37, 0x1, 1, 1, 1) 250#define MPP37_GPIO MPP(37, 0x1, 1, 1, 1)
251#define MPP37_UA0_RTSn MPP(37, 0x2, 0, 1, 1) 251#define MPP37_UA0_RTSn MPP(37, 0x2, 0, 0, 1)
252#define MPP37_UA2_RXD MPP(37, 0x4, 1, 0, 1) 252#define MPP37_UA2_RXD MPP(37, 0x4, 0, 0, 1)
253#define MPP37_SYSRST_OUTn MPP(37, 0x5, 0, 1, 1) 253#define MPP37_SYSRST_OUTn MPP(37, 0x5, 0, 0, 1)
254#define MPP37_TDM_SCLK MPP(37, 0x6, 0, 1, 1) 254#define MPP37_TDM_SCLK MPP(37, 0x6, 0, 0, 1)
255#define MPP37_UNUSED MPP(37, 0x3, 0, 0, 1) 255#define MPP37_UNUSED MPP(37, 0x3, 0, 0, 1)
256 256
257 257
258 258
259 259
260#define MPP38_GPIO MPP(38, 0x1, 1, 1, 1) 260#define MPP38_GPIO MPP(38, 0x1, 1, 1, 1)
261#define MPP38_UA1_CTSn MPP(38, 0x2, 1, 0, 1) 261#define MPP38_UA1_CTSn MPP(38, 0x2, 0, 0, 1)
262#define MPP38_UA3_TXD MPP(38, 0x4, 0, 1, 1) 262#define MPP38_UA3_TXD MPP(38, 0x4, 0, 0, 1)
263#define MPP38_SYSRST_OUTn MPP(38, 0x5, 0, 1, 1) 263#define MPP38_SYSRST_OUTn MPP(38, 0x5, 0, 0, 1)
264#define MPP38_TDM_SMOSI MPP(38, 0x6, 0, 1, 1) 264#define MPP38_TDM_SMOSI MPP(38, 0x6, 0, 0, 1)
265#define MPP38_UNUSED MPP(38, 0x3, 0, 0, 1) 265#define MPP38_UNUSED MPP(38, 0x3, 0, 0, 1)
266 266
267 267
268 268
269 269
270#define MPP39_GPIO MPP(39, 0x1, 1, 1, 1) 270#define MPP39_GPIO MPP(39, 0x1, 1, 1, 1)
271#define MPP39_UA1_RTSn MPP(39, 0x2, 0, 1, 1) 271#define MPP39_UA1_RTSn MPP(39, 0x2, 0, 0, 1)
272#define MPP39_UA3_RXD MPP(39, 0x4, 1, 0, 1) 272#define MPP39_UA3_RXD MPP(39, 0x4, 0, 0, 1)
273#define MPP39_SYSRST_OUTn MPP(39, 0x5, 0, 1, 1) 273#define MPP39_SYSRST_OUTn MPP(39, 0x5, 0, 0, 1)
274#define MPP39_TDM_SMISO MPP(39, 0x6, 1, 0, 1) 274#define MPP39_TDM_SMISO MPP(39, 0x6, 0, 0, 1)
275#define MPP39_UNUSED MPP(39, 0x3, 0, 0, 1) 275#define MPP39_UNUSED MPP(39, 0x3, 0, 0, 1)
276 276
277 277
278 278
279#define MPP40_GPIO MPP(40, 0x1, 1, 1, 1) 279#define MPP40_GPIO MPP(40, 0x1, 1, 1, 1)
280#define MPP40_TDM_INTn MPP(40, 0x6, 1, 0, 1) 280#define MPP40_TDM_INTn MPP(40, 0x6, 0, 0, 1)
281#define MPP40_UNUSED MPP(40, 0x0, 0, 0, 1) 281#define MPP40_UNUSED MPP(40, 0x0, 0, 0, 1)
282 282
283 283
284 284
285#define MPP41_GPIO MPP(41, 0x1, 1, 1, 1) 285#define MPP41_GPIO MPP(41, 0x1, 1, 1, 1)
286#define MPP41_TDM_RSTn MPP(41, 0x6, 0, 1, 1) 286#define MPP41_TDM_RSTn MPP(41, 0x6, 0, 0, 1)
287#define MPP41_UNUSED MPP(41, 0x0, 0, 0, 1) 287#define MPP41_UNUSED MPP(41, 0x0, 0, 0, 1)
288 288
289 289
290 290
291#define MPP42_GPIO MPP(42, 0x1, 1, 1, 1) 291#define MPP42_GPIO MPP(42, 0x1, 1, 1, 1)
292#define MPP42_TDM_PCLK MPP(42, 0x6, 1, 1, 1) 292#define MPP42_TDM_PCLK MPP(42, 0x6, 0, 0, 1)
293#define MPP42_UNUSED MPP(42, 0x0, 0, 0, 1) 293#define MPP42_UNUSED MPP(42, 0x0, 0, 0, 1)
294 294
295 295
296 296
297#define MPP43_GPIO MPP(43, 0x1, 1, 1, 1) 297#define MPP43_GPIO MPP(43, 0x1, 1, 1, 1)
298#define MPP43_TDM_FSYNC MPP(43, 0x6, 1, 1, 1) 298#define MPP43_TDM_FSYNC MPP(43, 0x6, 0, 0, 1)
299#define MPP43_UNUSED MPP(43, 0x0, 0, 0, 1) 299#define MPP43_UNUSED MPP(43, 0x0, 0, 0, 1)
300 300
301 301
302 302
303#define MPP44_GPIO MPP(44, 0x1, 1, 1, 1) 303#define MPP44_GPIO MPP(44, 0x1, 1, 1, 1)
304#define MPP44_TDM_DRX MPP(44, 0x6, 1, 0, 1) 304#define MPP44_TDM_DRX MPP(44, 0x6, 0, 0, 1)
305#define MPP44_UNUSED MPP(44, 0x0, 0, 0, 1) 305#define MPP44_UNUSED MPP(44, 0x0, 0, 0, 1)
306 306
307 307
308 308
309#define MPP45_GPIO MPP(45, 0x1, 1, 1, 1) 309#define MPP45_GPIO MPP(45, 0x1, 1, 1, 1)
310#define MPP45_SATA0_ACTn MPP(45, 0x3, 0, 1, 1) 310#define MPP45_SATA0_ACTn MPP(45, 0x3, 0, 0, 1)
311#define MPP45_TDM_DRX MPP(45, 0x6, 0, 1, 1) 311#define MPP45_TDM_DRX MPP(45, 0x6, 0, 0, 1)
312#define MPP45_UNUSED MPP(45, 0x0, 0, 0, 1) 312#define MPP45_UNUSED MPP(45, 0x0, 0, 0, 1)
313 313
314 314
315#define MPP46_GPIO MPP(46, 0x1, 1, 1, 1) 315#define MPP46_GPIO MPP(46, 0x1, 1, 1, 1)
316#define MPP46_TDM_SCSn MPP(46, 0x6, 0, 1, 1) 316#define MPP46_TDM_SCSn MPP(46, 0x6, 0, 0, 1)
317#define MPP46_UNUSED MPP(46, 0x0, 0, 0, 1) 317#define MPP46_UNUSED MPP(46, 0x0, 0, 0, 1)
318 318
319 319
@@ -323,14 +323,14 @@
323 323
324 324
325#define MPP48_GPIO MPP(48, 0x1, 1, 1, 1) 325#define MPP48_GPIO MPP(48, 0x1, 1, 1, 1)
326#define MPP48_SATA1_ACTn MPP(48, 0x3, 0, 1, 1) 326#define MPP48_SATA1_ACTn MPP(48, 0x3, 0, 0, 1)
327#define MPP48_UNUSED MPP(48, 0x2, 0, 0, 1) 327#define MPP48_UNUSED MPP(48, 0x2, 0, 0, 1)
328 328
329 329
330 330
331#define MPP49_GPIO MPP(49, 0x1, 1, 1, 1) 331#define MPP49_GPIO MPP(49, 0x1, 1, 1, 1)
332#define MPP49_SATA0_ACTn MPP(49, 0x3, 0, 1, 1) 332#define MPP49_SATA0_ACTn MPP(49, 0x3, 0, 0, 1)
333#define MPP49_M_BB MPP(49, 0x4, 1, 0, 1) 333#define MPP49_M_BB MPP(49, 0x4, 0, 0, 1)
334#define MPP49_UNUSED MPP(49, 0x2, 0, 0, 1) 334#define MPP49_UNUSED MPP(49, 0x2, 0, 0, 1)
335 335
336 336
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index fc9b238cbc19..bd76394ccaf8 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -11,9 +11,9 @@ hwmod-common = omap_hwmod.o \
11 omap_hwmod_common_data.o 11 omap_hwmod_common_data.o
12clock-common = clock.o clock_common_data.o \ 12clock-common = clock.o clock_common_data.o \
13 clkt_dpll.o clkt_clksel.o 13 clkt_dpll.o clkt_clksel.o
14secure-common = omap-smc.o omap-secure.o 14secure-common = omap-smc.o omap-secure.o
15 15
16obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) $(secure-common) 16obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
17obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) 17obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
18obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common) 18obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
19 19
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 21fc87648660..4e9071589bfb 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -814,7 +814,7 @@ static struct omap_dss_board_info sdp4430_dss_data = {
814 .default_device = &sdp4430_lcd_device, 814 .default_device = &sdp4430_lcd_device,
815}; 815};
816 816
817static void omap_4430sdp_display_init(void) 817static void __init omap_4430sdp_display_init(void)
818{ 818{
819 int r; 819 int r;
820 820
@@ -851,7 +851,7 @@ static struct omap_board_mux board_mux[] __initdata = {
851#define board_mux NULL 851#define board_mux NULL
852 #endif 852 #endif
853 853
854static void omap4_sdp4430_wifi_mux_init(void) 854static void __init omap4_sdp4430_wifi_mux_init(void)
855{ 855{
856 omap_mux_init_gpio(GPIO_WIFI_IRQ, OMAP_PIN_INPUT | 856 omap_mux_init_gpio(GPIO_WIFI_IRQ, OMAP_PIN_INPUT |
857 OMAP_PIN_OFF_WAKEUPENABLE); 857 OMAP_PIN_OFF_WAKEUPENABLE);
@@ -878,12 +878,17 @@ static struct wl12xx_platform_data omap4_sdp4430_wlan_data __initdata = {
878 .board_tcxo_clock = WL12XX_TCXOCLOCK_26, 878 .board_tcxo_clock = WL12XX_TCXOCLOCK_26,
879}; 879};
880 880
881static void omap4_sdp4430_wifi_init(void) 881static void __init omap4_sdp4430_wifi_init(void)
882{ 882{
883 int ret;
884
883 omap4_sdp4430_wifi_mux_init(); 885 omap4_sdp4430_wifi_mux_init();
884 if (wl12xx_set_platform_data(&omap4_sdp4430_wlan_data)) 886 ret = wl12xx_set_platform_data(&omap4_sdp4430_wlan_data);
885 pr_err("Error setting wl12xx data\n"); 887 if (ret)
886 platform_device_register(&omap_vwlan_device); 888 pr_err("Error setting wl12xx data: %d\n", ret);
889 ret = platform_device_register(&omap_vwlan_device);
890 if (ret)
891 pr_err("Error registering wl12xx device: %d\n", ret);
887} 892}
888 893
889static void __init omap_4430sdp_init(void) 894static void __init omap_4430sdp_init(void)
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index e921e3be24a4..d73316ed4207 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -437,7 +437,7 @@ static struct usbhs_omap_board_data usbhs_bdata __initdata = {
437 .reset_gpio_port[2] = -EINVAL 437 .reset_gpio_port[2] = -EINVAL
438}; 438};
439 439
440static void cm_t35_init_usbh(void) 440static void __init cm_t35_init_usbh(void)
441{ 441{
442 int err; 442 int err;
443 443
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index d58756060483..ad497620539b 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -17,6 +17,7 @@
17#include <linux/i2c/twl.h> 17#include <linux/i2c/twl.h>
18 18
19#include <mach/hardware.h> 19#include <mach/hardware.h>
20#include <asm/hardware/gic.h>
20#include <asm/mach/arch.h> 21#include <asm/mach/arch.h>
21 22
22#include <plat/board.h> 23#include <plat/board.h>
@@ -102,6 +103,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
102 .map_io = omap242x_map_io, 103 .map_io = omap242x_map_io,
103 .init_early = omap2420_init_early, 104 .init_early = omap2420_init_early,
104 .init_irq = omap2_init_irq, 105 .init_irq = omap2_init_irq,
106 .handle_irq = omap2_intc_handle_irq,
105 .init_machine = omap_generic_init, 107 .init_machine = omap_generic_init,
106 .timer = &omap2_timer, 108 .timer = &omap2_timer,
107 .dt_compat = omap242x_boards_compat, 109 .dt_compat = omap242x_boards_compat,
@@ -141,6 +143,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
141 .map_io = omap3_map_io, 143 .map_io = omap3_map_io,
142 .init_early = omap3430_init_early, 144 .init_early = omap3430_init_early,
143 .init_irq = omap3_init_irq, 145 .init_irq = omap3_init_irq,
146 .handle_irq = omap3_intc_handle_irq,
144 .init_machine = omap3_init, 147 .init_machine = omap3_init,
145 .timer = &omap3_timer, 148 .timer = &omap3_timer,
146 .dt_compat = omap3_boards_compat, 149 .dt_compat = omap3_boards_compat,
@@ -160,6 +163,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
160 .map_io = omap4_map_io, 163 .map_io = omap4_map_io,
161 .init_early = omap4430_init_early, 164 .init_early = omap4430_init_early,
162 .init_irq = gic_init_irq, 165 .init_irq = gic_init_irq,
166 .handle_irq = gic_handle_irq,
163 .init_machine = omap4_init, 167 .init_machine = omap4_init,
164 .timer = &omap4_timer, 168 .timer = &omap4_timer,
165 .dt_compat = omap4_boards_compat, 169 .dt_compat = omap4_boards_compat,
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 003fe34c9343..c775bead1497 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -617,6 +617,21 @@ static struct gpio omap3_evm_ehci_gpios[] __initdata = {
617 { OMAP3_EVM_EHCI_SELECT, GPIOF_OUT_INIT_LOW, "select EHCI port" }, 617 { OMAP3_EVM_EHCI_SELECT, GPIOF_OUT_INIT_LOW, "select EHCI port" },
618}; 618};
619 619
620static void __init omap3_evm_wl12xx_init(void)
621{
622#ifdef CONFIG_WL12XX_PLATFORM_DATA
623 int ret;
624
625 /* WL12xx WLAN Init */
626 ret = wl12xx_set_platform_data(&omap3evm_wlan_data);
627 if (ret)
628 pr_err("error setting wl12xx data: %d\n", ret);
629 ret = platform_device_register(&omap3evm_wlan_regulator);
630 if (ret)
631 pr_err("error registering wl12xx device: %d\n", ret);
632#endif
633}
634
620static void __init omap3_evm_init(void) 635static void __init omap3_evm_init(void)
621{ 636{
622 omap3_evm_get_revision(); 637 omap3_evm_get_revision();
@@ -665,13 +680,7 @@ static void __init omap3_evm_init(void)
665 omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL); 680 omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL);
666 omap3evm_init_smsc911x(); 681 omap3evm_init_smsc911x();
667 omap3_evm_display_init(); 682 omap3_evm_display_init();
668 683 omap3_evm_wl12xx_init();
669#ifdef CONFIG_WL12XX_PLATFORM_DATA
670 /* WL12xx WLAN Init */
671 if (wl12xx_set_platform_data(&omap3evm_wlan_data))
672 pr_err("error setting wl12xx data\n");
673 platform_device_register(&omap3evm_wlan_regulator);
674#endif
675} 684}
676 685
677MACHINE_START(OMAP3EVM, "OMAP3 EVM") 686MACHINE_START(OMAP3EVM, "OMAP3 EVM")
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index b7779c206a90..28fc271f7031 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -488,13 +488,15 @@ void omap4_panda_display_init(void)
488static void __init omap4_panda_init(void) 488static void __init omap4_panda_init(void)
489{ 489{
490 int package = OMAP_PACKAGE_CBS; 490 int package = OMAP_PACKAGE_CBS;
491 int ret;
491 492
492 if (omap_rev() == OMAP4430_REV_ES1_0) 493 if (omap_rev() == OMAP4430_REV_ES1_0)
493 package = OMAP_PACKAGE_CBL; 494 package = OMAP_PACKAGE_CBL;
494 omap4_mux_init(board_mux, NULL, package); 495 omap4_mux_init(board_mux, NULL, package);
495 496
496 if (wl12xx_set_platform_data(&omap_panda_wlan_data)) 497 ret = wl12xx_set_platform_data(&omap_panda_wlan_data);
497 pr_err("error setting wl12xx data\n"); 498 if (ret)
499 pr_err("error setting wl12xx data: %d\n", ret);
498 500
499 omap4_panda_i2c_init(); 501 omap4_panda_i2c_init();
500 platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices)); 502 platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index 8d7ce11cfeaf..c126461836ac 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -296,8 +296,10 @@ static void enable_board_wakeup_source(void)
296 296
297void __init zoom_peripherals_init(void) 297void __init zoom_peripherals_init(void)
298{ 298{
299 if (wl12xx_set_platform_data(&omap_zoom_wlan_data)) 299 int ret = wl12xx_set_platform_data(&omap_zoom_wlan_data);
300 pr_err("error setting wl12xx data\n"); 300
301 if (ret)
302 pr_err("error setting wl12xx data: %d\n", ret);
301 303
302 omap_i2c_init(); 304 omap_i2c_init();
303 platform_device_register(&omap_vwlan_device); 305 platform_device_register(&omap_vwlan_device);
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index ad0adb5a1e0e..b40c28895298 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -293,8 +293,8 @@ static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
293 } 293 }
294} 294}
295 295
296static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, 296static int omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
297 struct omap_mmc_platform_data *mmc) 297 struct omap_mmc_platform_data *mmc)
298{ 298{
299 char *hc_name; 299 char *hc_name;
300 300
@@ -430,7 +430,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
430 430
431#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16 431#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16
432 432
433void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr) 433void omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
434{ 434{
435 struct omap_hwmod *oh; 435 struct omap_hwmod *oh;
436 struct platform_device *pdev; 436 struct platform_device *pdev;
@@ -487,7 +487,7 @@ done:
487 kfree(mmc_data); 487 kfree(mmc_data);
488} 488}
489 489
490void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) 490void omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
491{ 491{
492 u32 reg; 492 u32 reg;
493 493
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index e1cc75d1a57a..fb8bc9fa43b1 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -100,8 +100,8 @@ void omap_mux_write_array(struct omap_mux_partition *partition,
100 100
101static char *omap_mux_options; 101static char *omap_mux_options;
102 102
103static int __init _omap_mux_init_gpio(struct omap_mux_partition *partition, 103static int _omap_mux_init_gpio(struct omap_mux_partition *partition,
104 int gpio, int val) 104 int gpio, int val)
105{ 105{
106 struct omap_mux_entry *e; 106 struct omap_mux_entry *e;
107 struct omap_mux *gpio_mux = NULL; 107 struct omap_mux *gpio_mux = NULL;
@@ -145,7 +145,7 @@ static int __init _omap_mux_init_gpio(struct omap_mux_partition *partition,
145 return 0; 145 return 0;
146} 146}
147 147
148int __init omap_mux_init_gpio(int gpio, int val) 148int omap_mux_init_gpio(int gpio, int val)
149{ 149{
150 struct omap_mux_partition *partition; 150 struct omap_mux_partition *partition;
151 int ret; 151 int ret;
@@ -159,9 +159,9 @@ int __init omap_mux_init_gpio(int gpio, int val)
159 return -ENODEV; 159 return -ENODEV;
160} 160}
161 161
162static int __init _omap_mux_get_by_name(struct omap_mux_partition *partition, 162static int _omap_mux_get_by_name(struct omap_mux_partition *partition,
163 const char *muxname, 163 const char *muxname,
164 struct omap_mux **found_mux) 164 struct omap_mux **found_mux)
165{ 165{
166 struct omap_mux *mux = NULL; 166 struct omap_mux *mux = NULL;
167 struct omap_mux_entry *e; 167 struct omap_mux_entry *e;
@@ -240,7 +240,7 @@ omap_mux_get_by_name(const char *muxname,
240 return -ENODEV; 240 return -ENODEV;
241} 241}
242 242
243int __init omap_mux_init_signal(const char *muxname, int val) 243int omap_mux_init_signal(const char *muxname, int val)
244{ 244{
245 struct omap_mux_partition *partition = NULL; 245 struct omap_mux_partition *partition = NULL;
246 struct omap_mux *mux = NULL; 246 struct omap_mux *mux = NULL;
@@ -1094,8 +1094,8 @@ static void omap_mux_init_package(struct omap_mux *superset,
1094 omap_mux_package_init_balls(package_balls, superset); 1094 omap_mux_package_init_balls(package_balls, superset);
1095} 1095}
1096 1096
1097static void omap_mux_init_signals(struct omap_mux_partition *partition, 1097static void __init omap_mux_init_signals(struct omap_mux_partition *partition,
1098 struct omap_board_mux *board_mux) 1098 struct omap_board_mux *board_mux)
1099{ 1099{
1100 omap_mux_set_cmdline_signals(); 1100 omap_mux_set_cmdline_signals();
1101 omap_mux_write_array(partition, board_mux); 1101 omap_mux_write_array(partition, board_mux);
@@ -1109,8 +1109,8 @@ static void omap_mux_init_package(struct omap_mux *superset,
1109{ 1109{
1110} 1110}
1111 1111
1112static void omap_mux_init_signals(struct omap_mux_partition *partition, 1112static void __init omap_mux_init_signals(struct omap_mux_partition *partition,
1113 struct omap_board_mux *board_mux) 1113 struct omap_board_mux *board_mux)
1114{ 1114{
1115} 1115}
1116 1116
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index b13ef7ef5ef4..503ac777a2ba 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -18,6 +18,7 @@
18#include <linux/linkage.h> 18#include <linux/linkage.h>
19#include <linux/init.h> 19#include <linux/init.h>
20 20
21 __CPUINIT
21/* 22/*
22 * OMAP4 specific entry point for secondary CPU to jump from ROM 23 * OMAP4 specific entry point for secondary CPU to jump from ROM
23 * code. This routine also provides a holding flag into which 24 * code. This routine also provides a holding flag into which
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 5192cabb40ed..eba6cd3816f5 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1517,8 +1517,8 @@ static int _enable(struct omap_hwmod *oh)
1517 if (oh->_state != _HWMOD_STATE_INITIALIZED && 1517 if (oh->_state != _HWMOD_STATE_INITIALIZED &&
1518 oh->_state != _HWMOD_STATE_IDLE && 1518 oh->_state != _HWMOD_STATE_IDLE &&
1519 oh->_state != _HWMOD_STATE_DISABLED) { 1519 oh->_state != _HWMOD_STATE_DISABLED) {
1520 WARN(1, "omap_hwmod: %s: enabled state can only be entered " 1520 WARN(1, "omap_hwmod: %s: enabled state can only be entered from initialized, idle, or disabled state\n",
1521 "from initialized, idle, or disabled state\n", oh->name); 1521 oh->name);
1522 return -EINVAL; 1522 return -EINVAL;
1523 } 1523 }
1524 1524
@@ -1600,8 +1600,8 @@ static int _idle(struct omap_hwmod *oh)
1600 pr_debug("omap_hwmod: %s: idling\n", oh->name); 1600 pr_debug("omap_hwmod: %s: idling\n", oh->name);
1601 1601
1602 if (oh->_state != _HWMOD_STATE_ENABLED) { 1602 if (oh->_state != _HWMOD_STATE_ENABLED) {
1603 WARN(1, "omap_hwmod: %s: idle state can only be entered from " 1603 WARN(1, "omap_hwmod: %s: idle state can only be entered from enabled state\n",
1604 "enabled state\n", oh->name); 1604 oh->name);
1605 return -EINVAL; 1605 return -EINVAL;
1606 } 1606 }
1607 1607
@@ -1682,8 +1682,8 @@ static int _shutdown(struct omap_hwmod *oh)
1682 1682
1683 if (oh->_state != _HWMOD_STATE_IDLE && 1683 if (oh->_state != _HWMOD_STATE_IDLE &&
1684 oh->_state != _HWMOD_STATE_ENABLED) { 1684 oh->_state != _HWMOD_STATE_ENABLED) {
1685 WARN(1, "omap_hwmod: %s: disabled state can only be entered " 1685 WARN(1, "omap_hwmod: %s: disabled state can only be entered from idle, or enabled state\n",
1686 "from idle, or enabled state\n", oh->name); 1686 oh->name);
1687 return -EINVAL; 1687 return -EINVAL;
1688 } 1688 }
1689 1689
@@ -2240,8 +2240,8 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh)
2240 BUG_ON(!oh); 2240 BUG_ON(!oh);
2241 2241
2242 if (!oh->class->sysc || !oh->class->sysc->sysc_flags) { 2242 if (!oh->class->sysc || !oh->class->sysc->sysc_flags) {
2243 WARN(1, "omap_device: %s: OCP barrier impossible due to " 2243 WARN(1, "omap_device: %s: OCP barrier impossible due to device configuration\n",
2244 "device configuration\n", oh->name); 2244 oh->name);
2245 return; 2245 return;
2246 } 2246 }
2247 2247
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 1f736222a629..a4eb5c280435 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -82,13 +82,7 @@ static int omap2_fclks_active(void)
82 f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); 82 f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
83 f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); 83 f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
84 84
85 /* Ignore UART clocks. These are handled by UART core (serial.c) */ 85 return (f1 | f2) ? 1 : 0;
86 f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK);
87 f2 &= ~OMAP24XX_EN_UART3_MASK;
88
89 if (f1 | f2)
90 return 1;
91 return 0;
92} 86}
93 87
94static void omap2_enter_full_retention(void) 88static void omap2_enter_full_retention(void)
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 33dd655e6aab..a1d6154dc120 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -19,6 +19,7 @@
19 19
20#include "common.h" 20#include "common.h"
21#include <plat/cpu.h> 21#include <plat/cpu.h>
22#include <plat/irqs.h>
22#include <plat/prcm.h> 23#include <plat/prcm.h>
23 24
24#include "vp.h" 25#include "vp.h"
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 247d89478f24..f590afc1f673 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -107,18 +107,18 @@ static void omap_uart_set_noidle(struct platform_device *pdev)
107 omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO); 107 omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO);
108} 108}
109 109
110static void omap_uart_set_forceidle(struct platform_device *pdev) 110static void omap_uart_set_smartidle(struct platform_device *pdev)
111{ 111{
112 struct omap_device *od = to_omap_device(pdev); 112 struct omap_device *od = to_omap_device(pdev);
113 113
114 omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_FORCE); 114 omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_SMART);
115} 115}
116 116
117#else 117#else
118static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable) 118static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
119{} 119{}
120static void omap_uart_set_noidle(struct platform_device *pdev) {} 120static void omap_uart_set_noidle(struct platform_device *pdev) {}
121static void omap_uart_set_forceidle(struct platform_device *pdev) {} 121static void omap_uart_set_smartidle(struct platform_device *pdev) {}
122#endif /* CONFIG_PM */ 122#endif /* CONFIG_PM */
123 123
124#ifdef CONFIG_OMAP_MUX 124#ifdef CONFIG_OMAP_MUX
@@ -349,7 +349,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata,
349 omap_up.uartclk = OMAP24XX_BASE_BAUD * 16; 349 omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
350 omap_up.flags = UPF_BOOT_AUTOCONF; 350 omap_up.flags = UPF_BOOT_AUTOCONF;
351 omap_up.get_context_loss_count = omap_pm_get_dev_context_loss_count; 351 omap_up.get_context_loss_count = omap_pm_get_dev_context_loss_count;
352 omap_up.set_forceidle = omap_uart_set_forceidle; 352 omap_up.set_forceidle = omap_uart_set_smartidle;
353 omap_up.set_noidle = omap_uart_set_noidle; 353 omap_up.set_noidle = omap_uart_set_noidle;
354 omap_up.enable_wakeup = omap_uart_enable_wakeup; 354 omap_up.enable_wakeup = omap_uart_enable_wakeup;
355 omap_up.dma_rx_buf_size = info->dma_rx_buf_size; 355 omap_up.dma_rx_buf_size = info->dma_rx_buf_size;
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
index 031d116fbf10..175b7d86d86a 100644
--- a/arch/arm/mach-omap2/vc.c
+++ b/arch/arm/mach-omap2/vc.c
@@ -247,7 +247,7 @@ static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
247 * omap_vc_i2c_init - initialize I2C interface to PMIC 247 * omap_vc_i2c_init - initialize I2C interface to PMIC
248 * @voltdm: voltage domain containing VC data 248 * @voltdm: voltage domain containing VC data
249 * 249 *
250 * Use PMIC supplied seetings for I2C high-speed mode and 250 * Use PMIC supplied settings for I2C high-speed mode and
251 * master code (if set) and program the VC I2C configuration 251 * master code (if set) and program the VC I2C configuration
252 * register. 252 * register.
253 * 253 *
@@ -265,8 +265,8 @@ static void __init omap_vc_i2c_init(struct voltagedomain *voltdm)
265 265
266 if (initialized) { 266 if (initialized) {
267 if (voltdm->pmic->i2c_high_speed != i2c_high_speed) 267 if (voltdm->pmic->i2c_high_speed != i2c_high_speed)
268 pr_warn("%s: I2C config for all channels must match.", 268 pr_warn("%s: I2C config for vdd_%s does not match other channels (%u).",
269 __func__); 269 __func__, voltdm->name, i2c_high_speed);
270 return; 270 return;
271 } 271 }
272 272
@@ -292,9 +292,7 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)
292 u32 val; 292 u32 val;
293 293
294 if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) { 294 if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) {
295 pr_err("%s: PMIC info requried to configure vc for" 295 pr_err("%s: No PMIC info for vdd_%s\n", __func__, voltdm->name);
296 "vdd_%s not populated.Hence cannot initialize vc\n",
297 __func__, voltdm->name);
298 return; 296 return;
299 } 297 }
300 298
diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
index c005e2f5e383..57db2038b23c 100644
--- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
@@ -108,6 +108,7 @@ void __init omap3xxx_voltagedomains_init(void)
108 * XXX Will depend on the process, validation, and binning 108 * XXX Will depend on the process, validation, and binning
109 * for the currently-running IC 109 * for the currently-running IC
110 */ 110 */
111#ifdef CONFIG_PM_OPP
111 if (cpu_is_omap3630()) { 112 if (cpu_is_omap3630()) {
112 omap3_voltdm_mpu.volt_data = omap36xx_vddmpu_volt_data; 113 omap3_voltdm_mpu.volt_data = omap36xx_vddmpu_volt_data;
113 omap3_voltdm_core.volt_data = omap36xx_vddcore_volt_data; 114 omap3_voltdm_core.volt_data = omap36xx_vddcore_volt_data;
@@ -115,6 +116,7 @@ void __init omap3xxx_voltagedomains_init(void)
115 omap3_voltdm_mpu.volt_data = omap34xx_vddmpu_volt_data; 116 omap3_voltdm_mpu.volt_data = omap34xx_vddmpu_volt_data;
116 omap3_voltdm_core.volt_data = omap34xx_vddcore_volt_data; 117 omap3_voltdm_core.volt_data = omap34xx_vddcore_volt_data;
117 } 118 }
119#endif
118 120
119 if (cpu_is_omap3517() || cpu_is_omap3505()) 121 if (cpu_is_omap3517() || cpu_is_omap3505())
120 voltdms = voltagedomains_am35xx; 122 voltdms = voltagedomains_am35xx;
diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c
index 4e11d022595d..c3115f6853d4 100644
--- a/arch/arm/mach-omap2/voltagedomains44xx_data.c
+++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c
@@ -100,9 +100,11 @@ void __init omap44xx_voltagedomains_init(void)
100 * XXX Will depend on the process, validation, and binning 100 * XXX Will depend on the process, validation, and binning
101 * for the currently-running IC 101 * for the currently-running IC
102 */ 102 */
103#ifdef CONFIG_PM_OPP
103 omap4_voltdm_mpu.volt_data = omap44xx_vdd_mpu_volt_data; 104 omap4_voltdm_mpu.volt_data = omap44xx_vdd_mpu_volt_data;
104 omap4_voltdm_iva.volt_data = omap44xx_vdd_iva_volt_data; 105 omap4_voltdm_iva.volt_data = omap44xx_vdd_iva_volt_data;
105 omap4_voltdm_core.volt_data = omap44xx_vdd_core_volt_data; 106 omap4_voltdm_core.volt_data = omap44xx_vdd_core_volt_data;
107#endif
106 108
107 for (i = 0; voltdm = voltagedomains_omap4[i], voltdm; i++) 109 for (i = 0; voltdm = voltagedomains_omap4[i], voltdm; i++)
108 voltdm->sys_clk.name = sys_clk_name; 110 voltdm->sys_clk.name = sys_clk_name;
diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
index 807391d84a9d..0df88820978d 100644
--- a/arch/arm/mach-omap2/vp.c
+++ b/arch/arm/mach-omap2/vp.c
@@ -41,6 +41,11 @@ void __init omap_vp_init(struct voltagedomain *voltdm)
41 u32 val, sys_clk_rate, timeout, waittime; 41 u32 val, sys_clk_rate, timeout, waittime;
42 u32 vddmin, vddmax, vstepmin, vstepmax; 42 u32 vddmin, vddmax, vstepmin, vstepmax;
43 43
44 if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) {
45 pr_err("%s: No PMIC info for vdd_%s\n", __func__, voltdm->name);
46 return;
47 }
48
44 if (!voltdm->read || !voltdm->write) { 49 if (!voltdm->read || !voltdm->write) {
45 pr_err("%s: No read/write API for accessing vdd_%s regs\n", 50 pr_err("%s: No read/write API for accessing vdd_%s regs\n",
46 __func__, voltdm->name); 51 __func__, voltdm->name);
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 0e28bae20bd4..5dad38ec00ea 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -29,6 +29,7 @@
29#include <mach/hardware.h> 29#include <mach/hardware.h>
30#include <mach/orion5x.h> 30#include <mach/orion5x.h>
31#include <plat/orion_nand.h> 31#include <plat/orion_nand.h>
32#include <plat/ehci-orion.h>
32#include <plat/time.h> 33#include <plat/time.h>
33#include <plat/common.h> 34#include <plat/common.h>
34#include <plat/addr-map.h> 35#include <plat/addr-map.h>
@@ -72,7 +73,8 @@ void __init orion5x_map_io(void)
72 ****************************************************************************/ 73 ****************************************************************************/
73void __init orion5x_ehci0_init(void) 74void __init orion5x_ehci0_init(void)
74{ 75{
75 orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL); 76 orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL,
77 EHCI_PHY_ORION);
76} 78}
77 79
78 80
diff --git a/arch/arm/mach-s3c2410/cpu-freq.c b/arch/arm/mach-s3c2410/cpu-freq.c
index 7dc6c46b5e2b..5404535da1a5 100644
--- a/arch/arm/mach-s3c2410/cpu-freq.c
+++ b/arch/arm/mach-s3c2410/cpu-freq.c
@@ -115,7 +115,8 @@ static struct s3c_cpufreq_info s3c2410_cpufreq_info = {
115 .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs), 115 .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
116}; 116};
117 117
118static int s3c2410_cpufreq_add(struct device *dev) 118static int s3c2410_cpufreq_add(struct device *dev,
119 struct subsys_interface *sif)
119{ 120{
120 return s3c_cpufreq_register(&s3c2410_cpufreq_info); 121 return s3c_cpufreq_register(&s3c2410_cpufreq_info);
121} 122}
@@ -133,7 +134,8 @@ static int __init s3c2410_cpufreq_init(void)
133 134
134arch_initcall(s3c2410_cpufreq_init); 135arch_initcall(s3c2410_cpufreq_init);
135 136
136static int s3c2410a_cpufreq_add(struct device *dev) 137static int s3c2410a_cpufreq_add(struct device *dev,
138 struct subsys_interface *sif)
137{ 139{
138 /* alter the maximum freq settings for S3C2410A. If a board knows 140 /* alter the maximum freq settings for S3C2410A. If a board knows
139 * it only has a maximum of 200, then it should register its own 141 * it only has a maximum of 200, then it should register its own
@@ -144,7 +146,7 @@ static int s3c2410a_cpufreq_add(struct device *dev)
144 s3c2410_cpufreq_info.max.pclk = 66500000; 146 s3c2410_cpufreq_info.max.pclk = 66500000;
145 s3c2410_cpufreq_info.name = "s3c2410a"; 147 s3c2410_cpufreq_info.name = "s3c2410a";
146 148
147 return s3c2410_cpufreq_add(dev); 149 return s3c2410_cpufreq_add(dev, sif);
148} 150}
149 151
150static struct subsys_interface s3c2410a_cpufreq_interface = { 152static struct subsys_interface s3c2410a_cpufreq_interface = {
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
index 2afd00014a77..4803338cf56e 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -132,7 +132,8 @@ static struct s3c24xx_dma_order __initdata s3c2410_dma_order = {
132 }, 132 },
133}; 133};
134 134
135static int __init s3c2410_dma_add(struct device *dev) 135static int __init s3c2410_dma_add(struct device *dev,
136 struct subsys_interface *sif)
136{ 137{
137 s3c2410_dma_init(); 138 s3c2410_dma_init();
138 s3c24xx_dma_order_set(&s3c2410_dma_order); 139 s3c24xx_dma_order_set(&s3c2410_dma_order);
@@ -148,7 +149,7 @@ static struct subsys_interface s3c2410_dma_interface = {
148 149
149static int __init s3c2410_dma_drvinit(void) 150static int __init s3c2410_dma_drvinit(void)
150{ 151{
151 return subsys_interface_register(&s3c2410_interface); 152 return subsys_interface_register(&s3c2410_dma_interface);
152} 153}
153 154
154arch_initcall(s3c2410_dma_drvinit); 155arch_initcall(s3c2410_dma_drvinit);
diff --git a/arch/arm/mach-s3c2410/pll.c b/arch/arm/mach-s3c2410/pll.c
index c07438bfc99f..e0b3b347da82 100644
--- a/arch/arm/mach-s3c2410/pll.c
+++ b/arch/arm/mach-s3c2410/pll.c
@@ -66,7 +66,7 @@ static struct cpufreq_frequency_table pll_vals_12MHz[] = {
66 { .frequency = 270000000, .index = PLLVAL(127, 1, 1), }, 66 { .frequency = 270000000, .index = PLLVAL(127, 1, 1), },
67}; 67};
68 68
69static int s3c2410_plls_add(struct device *dev) 69static int s3c2410_plls_add(struct device *dev, struct subsys_interface *sif)
70{ 70{
71 return s3c_plltab_register(pll_vals_12MHz, ARRAY_SIZE(pll_vals_12MHz)); 71 return s3c_plltab_register(pll_vals_12MHz, ARRAY_SIZE(pll_vals_12MHz));
72} 72}
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c
index fda5385deff6..03f706dd6009 100644
--- a/arch/arm/mach-s3c2410/pm.c
+++ b/arch/arm/mach-s3c2410/pm.c
@@ -111,7 +111,7 @@ struct syscore_ops s3c2410_pm_syscore_ops = {
111 .resume = s3c2410_pm_resume, 111 .resume = s3c2410_pm_resume,
112}; 112};
113 113
114static int s3c2410_pm_add(struct device *dev) 114static int s3c2410_pm_add(struct device *dev, struct subsys_interface *sif)
115{ 115{
116 pm_cpu_prep = s3c2410_pm_prepare; 116 pm_cpu_prep = s3c2410_pm_prepare;
117 pm_cpu_sleep = s3c2410_cpu_suspend; 117 pm_cpu_sleep = s3c2410_cpu_suspend;
diff --git a/arch/arm/mach-s3c2412/cpu-freq.c b/arch/arm/mach-s3c2412/cpu-freq.c
index d8664b7652ce..125be7d5fa60 100644
--- a/arch/arm/mach-s3c2412/cpu-freq.c
+++ b/arch/arm/mach-s3c2412/cpu-freq.c
@@ -194,7 +194,8 @@ static struct s3c_cpufreq_info s3c2412_cpufreq_info = {
194 .debug_io_show = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs), 194 .debug_io_show = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs),
195}; 195};
196 196
197static int s3c2412_cpufreq_add(struct device *dev) 197static int s3c2412_cpufreq_add(struct device *dev,
198 struct subsys_interface *sif)
198{ 199{
199 unsigned long fclk_rate; 200 unsigned long fclk_rate;
200 201
diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c
index 142acd3b5e15..38472ac920ff 100644
--- a/arch/arm/mach-s3c2412/dma.c
+++ b/arch/arm/mach-s3c2412/dma.c
@@ -159,7 +159,8 @@ static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = {
159 .map_size = ARRAY_SIZE(s3c2412_dma_mappings), 159 .map_size = ARRAY_SIZE(s3c2412_dma_mappings),
160}; 160};
161 161
162static int __init s3c2412_dma_add(struct device *dev) 162static int __init s3c2412_dma_add(struct device *dev,
163 struct subsys_interface *sif)
163{ 164{
164 s3c2410_dma_init(); 165 s3c2410_dma_init();
165 return s3c24xx_dma_init_map(&s3c2412_dma_sel); 166 return s3c24xx_dma_init_map(&s3c2412_dma_sel);
diff --git a/arch/arm/mach-s3c2412/irq.c b/arch/arm/mach-s3c2412/irq.c
index a8a46c1644f4..e65619ddbccc 100644
--- a/arch/arm/mach-s3c2412/irq.c
+++ b/arch/arm/mach-s3c2412/irq.c
@@ -170,7 +170,7 @@ static int s3c2412_irq_rtc_wake(struct irq_data *data, unsigned int state)
170 170
171static struct irq_chip s3c2412_irq_rtc_chip; 171static struct irq_chip s3c2412_irq_rtc_chip;
172 172
173static int s3c2412_irq_add(struct device *dev) 173static int s3c2412_irq_add(struct device *dev, struct subsys_interface *sif)
174{ 174{
175 unsigned int irqno; 175 unsigned int irqno;
176 176
diff --git a/arch/arm/mach-s3c2412/pm.c b/arch/arm/mach-s3c2412/pm.c
index d1adfa65f66d..d04588506ec4 100644
--- a/arch/arm/mach-s3c2412/pm.c
+++ b/arch/arm/mach-s3c2412/pm.c
@@ -56,7 +56,7 @@ static void s3c2412_pm_prepare(void)
56{ 56{
57} 57}
58 58
59static int s3c2412_pm_add(struct device *dev) 59static int s3c2412_pm_add(struct device *dev, struct subsys_interface *sif)
60{ 60{
61 pm_cpu_prep = s3c2412_pm_prepare; 61 pm_cpu_prep = s3c2412_pm_prepare;
62 pm_cpu_sleep = s3c2412_cpu_suspend; 62 pm_cpu_sleep = s3c2412_cpu_suspend;
diff --git a/arch/arm/mach-s3c2416/irq.c b/arch/arm/mach-s3c2416/irq.c
index 36df761061de..fd49f35e448e 100644
--- a/arch/arm/mach-s3c2416/irq.c
+++ b/arch/arm/mach-s3c2416/irq.c
@@ -213,7 +213,8 @@ static int __init s3c2416_add_sub(unsigned int base,
213 return 0; 213 return 0;
214} 214}
215 215
216static int __init s3c2416_irq_add(struct device *dev) 216static int __init s3c2416_irq_add(struct device *dev,
217 struct subsys_interface *sif)
217{ 218{
218 printk(KERN_INFO "S3C2416: IRQ Support\n"); 219 printk(KERN_INFO "S3C2416: IRQ Support\n");
219 220
diff --git a/arch/arm/mach-s3c2416/pm.c b/arch/arm/mach-s3c2416/pm.c
index 3bdb15a0d419..1bd4817b8eb8 100644
--- a/arch/arm/mach-s3c2416/pm.c
+++ b/arch/arm/mach-s3c2416/pm.c
@@ -48,7 +48,7 @@ static void s3c2416_pm_prepare(void)
48 __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1); 48 __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
49} 49}
50 50
51static int s3c2416_pm_add(struct device *dev) 51static int s3c2416_pm_add(struct device *dev, struct subsys_interface *sif)
52{ 52{
53 pm_cpu_prep = s3c2416_pm_prepare; 53 pm_cpu_prep = s3c2416_pm_prepare;
54 pm_cpu_sleep = s3c2416_cpu_suspend; 54 pm_cpu_sleep = s3c2416_cpu_suspend;
diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c
index bedbc87a3426..414364eb426c 100644
--- a/arch/arm/mach-s3c2440/clock.c
+++ b/arch/arm/mach-s3c2440/clock.c
@@ -149,7 +149,7 @@ static struct clk_lookup s3c2440_clk_lookup[] = {
149 CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n), 149 CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n),
150}; 150};
151 151
152static int s3c2440_clk_add(struct device *dev) 152static int s3c2440_clk_add(struct device *dev, struct subsys_interface *sif)
153{ 153{
154 struct clk *clock_upll; 154 struct clk *clock_upll;
155 struct clk *clock_h; 155 struct clk *clock_h;
diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c
index 15b1ddf8f626..5f0a0c8ef84f 100644
--- a/arch/arm/mach-s3c2440/dma.c
+++ b/arch/arm/mach-s3c2440/dma.c
@@ -174,7 +174,8 @@ static struct s3c24xx_dma_order __initdata s3c2440_dma_order = {
174 }, 174 },
175}; 175};
176 176
177static int __init s3c2440_dma_add(struct device *dev) 177static int __init s3c2440_dma_add(struct device *dev,
178 struct subsys_interface *sif)
178{ 179{
179 s3c2410_dma_init(); 180 s3c2410_dma_init();
180 s3c24xx_dma_order_set(&s3c2440_dma_order); 181 s3c24xx_dma_order_set(&s3c2440_dma_order);
diff --git a/arch/arm/mach-s3c2440/irq.c b/arch/arm/mach-s3c2440/irq.c
index 4fee9bc6bcb5..4a18cde439cc 100644
--- a/arch/arm/mach-s3c2440/irq.c
+++ b/arch/arm/mach-s3c2440/irq.c
@@ -92,7 +92,7 @@ static struct irq_chip s3c_irq_wdtac97 = {
92 .irq_ack = s3c_irq_wdtac97_ack, 92 .irq_ack = s3c_irq_wdtac97_ack,
93}; 93};
94 94
95static int s3c2440_irq_add(struct device *dev) 95static int s3c2440_irq_add(struct device *dev, struct subsys_interface *sif)
96{ 96{
97 unsigned int irqno; 97 unsigned int irqno;
98 98
diff --git a/arch/arm/mach-s3c2440/s3c2440-cpufreq.c b/arch/arm/mach-s3c2440/s3c2440-cpufreq.c
index cf7596694efe..61776764d9f4 100644
--- a/arch/arm/mach-s3c2440/s3c2440-cpufreq.c
+++ b/arch/arm/mach-s3c2440/s3c2440-cpufreq.c
@@ -270,7 +270,8 @@ struct s3c_cpufreq_info s3c2440_cpufreq_info = {
270 .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs), 270 .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
271}; 271};
272 272
273static int s3c2440_cpufreq_add(struct device *dev) 273static int s3c2440_cpufreq_add(struct device *dev,
274 struct subsys_interface *sif)
274{ 275{
275 xtal = s3c_cpufreq_clk_get(NULL, "xtal"); 276 xtal = s3c_cpufreq_clk_get(NULL, "xtal");
276 hclk = s3c_cpufreq_clk_get(NULL, "hclk"); 277 hclk = s3c_cpufreq_clk_get(NULL, "hclk");
diff --git a/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c b/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c
index b5368ae8d7fe..551fb433be87 100644
--- a/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c
+++ b/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c
@@ -51,7 +51,7 @@ static struct cpufreq_frequency_table s3c2440_plls_12[] __initdata = {
51 { .frequency = 400000000, .index = PLLVAL(0x5c, 1, 1), }, /* FVco 800.000000 */ 51 { .frequency = 400000000, .index = PLLVAL(0x5c, 1, 1), }, /* FVco 800.000000 */
52}; 52};
53 53
54static int s3c2440_plls12_add(struct device *dev) 54static int s3c2440_plls12_add(struct device *dev, struct subsys_interface *sif)
55{ 55{
56 struct clk *xtal_clk; 56 struct clk *xtal_clk;
57 unsigned long xtal; 57 unsigned long xtal;
diff --git a/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c b/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c
index 42f2b5cd2399..3f15bcf64290 100644
--- a/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c
+++ b/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c
@@ -79,7 +79,8 @@ static struct cpufreq_frequency_table s3c2440_plls_169344[] __initdata = {
79 { .frequency = 402192000, .index = PLLVAL(87, 2, 1), }, /* FVco 804.384000 */ 79 { .frequency = 402192000, .index = PLLVAL(87, 2, 1), }, /* FVco 804.384000 */
80}; 80};
81 81
82static int s3c2440_plls169344_add(struct device *dev) 82static int s3c2440_plls169344_add(struct device *dev,
83 struct subsys_interface *sif)
83{ 84{
84 struct clk *xtal_clk; 85 struct clk *xtal_clk;
85 unsigned long xtal; 86 unsigned long xtal;
diff --git a/arch/arm/mach-s3c2440/s3c2442.c b/arch/arm/mach-s3c2440/s3c2442.c
index 8004e0497bf4..22cb7c94a8c8 100644
--- a/arch/arm/mach-s3c2440/s3c2442.c
+++ b/arch/arm/mach-s3c2440/s3c2442.c
@@ -122,7 +122,7 @@ static struct clk s3c2442_clk_cam_upll = {
122 }, 122 },
123}; 123};
124 124
125static int s3c2442_clk_add(struct device *dev) 125static int s3c2442_clk_add(struct device *dev, struct subsys_interface *sif)
126{ 126{
127 struct clk *clock_upll; 127 struct clk *clock_upll;
128 struct clk *clock_h; 128 struct clk *clock_h;
diff --git a/arch/arm/mach-s3c2440/s3c244x-clock.c b/arch/arm/mach-s3c2440/s3c244x-clock.c
index b3fdbdda3d5f..6d9b688c442b 100644
--- a/arch/arm/mach-s3c2440/s3c244x-clock.c
+++ b/arch/arm/mach-s3c2440/s3c244x-clock.c
@@ -72,7 +72,7 @@ static struct clk clk_arm = {
72 }, 72 },
73}; 73};
74 74
75static int s3c244x_clk_add(struct device *dev) 75static int s3c244x_clk_add(struct device *dev, struct subsys_interface *sif)
76{ 76{
77 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); 77 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
78 unsigned long clkdivn; 78 unsigned long clkdivn;
diff --git a/arch/arm/mach-s3c2440/s3c244x-irq.c b/arch/arm/mach-s3c2440/s3c244x-irq.c
index 74d3dcf46a48..5fe8e58d3afd 100644
--- a/arch/arm/mach-s3c2440/s3c244x-irq.c
+++ b/arch/arm/mach-s3c2440/s3c244x-irq.c
@@ -91,7 +91,7 @@ static struct irq_chip s3c_irq_cam = {
91 .irq_ack = s3c_irq_cam_ack, 91 .irq_ack = s3c_irq_cam_ack,
92}; 92};
93 93
94static int s3c244x_irq_add(struct device *dev) 94static int s3c244x_irq_add(struct device *dev, struct subsys_interface *sif)
95{ 95{
96 unsigned int irqno; 96 unsigned int irqno;
97 97
diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c
index de6b4a23c9ed..14224517e621 100644
--- a/arch/arm/mach-s3c2443/dma.c
+++ b/arch/arm/mach-s3c2443/dma.c
@@ -135,7 +135,8 @@ static struct s3c24xx_dma_selection __initdata s3c2443_dma_sel = {
135 .map_size = ARRAY_SIZE(s3c2443_dma_mappings), 135 .map_size = ARRAY_SIZE(s3c2443_dma_mappings),
136}; 136};
137 137
138static int __init s3c2443_dma_add(struct device *dev) 138static int __init s3c2443_dma_add(struct device *dev,
139 struct subsys_interface *sif)
139{ 140{
140 s3c24xx_dma_init(6, IRQ_S3C2443_DMA0, 0x100); 141 s3c24xx_dma_init(6, IRQ_S3C2443_DMA0, 0x100);
141 return s3c24xx_dma_init_map(&s3c2443_dma_sel); 142 return s3c24xx_dma_init_map(&s3c2443_dma_sel);
diff --git a/arch/arm/mach-s3c2443/irq.c b/arch/arm/mach-s3c2443/irq.c
index 35e4ff24fb43..ac2829f56d12 100644
--- a/arch/arm/mach-s3c2443/irq.c
+++ b/arch/arm/mach-s3c2443/irq.c
@@ -241,7 +241,8 @@ static int __init s3c2443_add_sub(unsigned int base,
241 return 0; 241 return 0;
242} 242}
243 243
244static int __init s3c2443_irq_add(struct device *dev) 244static int __init s3c2443_irq_add(struct device *dev,
245 struct subsys_interface *sif)
245{ 246{
246 printk("S3C2443: IRQ Support\n"); 247 printk("S3C2443: IRQ Support\n");
247 248
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 31bb27dc4aeb..aebbcc291b4e 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -138,6 +138,11 @@ static struct clk init_clocks_off[] = {
138 .ctrlbit = S3C_CLKCON_PCLK_TSADC, 138 .ctrlbit = S3C_CLKCON_PCLK_TSADC,
139 }, { 139 }, {
140 .name = "i2c", 140 .name = "i2c",
141#ifdef CONFIG_S3C_DEV_I2C1
142 .devname = "s3c2440-i2c.0",
143#else
144 .devname = "s3c2440-i2c",
145#endif
141 .parent = &clk_p, 146 .parent = &clk_p,
142 .enable = s3c64xx_pclk_ctrl, 147 .enable = s3c64xx_pclk_ctrl,
143 .ctrlbit = S3C_CLKCON_PCLK_IIC, 148 .ctrlbit = S3C_CLKCON_PCLK_IIC,
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
index 4a7394d4bd9e..bee7dcd4df7c 100644
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c64xx/common.c
@@ -49,7 +49,7 @@
49 49
50/* uart registration process */ 50/* uart registration process */
51 51
52void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) 52static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
53{ 53{
54 s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no); 54 s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
55} 55}
diff --git a/arch/arm/mach-s5p64x0/pm.c b/arch/arm/mach-s5p64x0/pm.c
index 23f9b22439c9..9cba18bfe47b 100644
--- a/arch/arm/mach-s5p64x0/pm.c
+++ b/arch/arm/mach-s5p64x0/pm.c
@@ -160,7 +160,7 @@ static void s5p64x0_pm_prepare(void)
160 160
161} 161}
162 162
163static int s5p64x0_pm_add(struct device *dev) 163static int s5p64x0_pm_add(struct device *dev, struct subsys_interface *sif)
164{ 164{
165 pm_cpu_prep = s5p64x0_pm_prepare; 165 pm_cpu_prep = s5p64x0_pm_prepare;
166 pm_cpu_sleep = s5p64x0_cpu_suspend; 166 pm_cpu_sleep = s5p64x0_cpu_suspend;
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index c78dfddd77fd..b9ec0c35379f 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -175,7 +175,7 @@ static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
175 return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable); 175 return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
176} 176}
177 177
178static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable) 178static int s5pv210_clk_hdmiphy_ctrl(struct clk *clk, int enable)
179{ 179{
180 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable); 180 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
181} 181}
@@ -372,7 +372,7 @@ static struct clk init_clocks_off[] = {
372 }, { 372 }, {
373 .name = "hdmiphy", 373 .name = "hdmiphy",
374 .devname = "s5pv210-hdmi", 374 .devname = "s5pv210-hdmi",
375 .enable = exynos4_clk_hdmiphy_ctrl, 375 .enable = s5pv210_clk_hdmiphy_ctrl,
376 .ctrlbit = (1 << 0), 376 .ctrlbit = (1 << 0),
377 }, { 377 }, {
378 .name = "dacphy", 378 .name = "dacphy",
diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
index 677c71c41e50..736bfb103cbc 100644
--- a/arch/arm/mach-s5pv210/pm.c
+++ b/arch/arm/mach-s5pv210/pm.c
@@ -133,7 +133,7 @@ static void s5pv210_pm_prepare(void)
133 s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save)); 133 s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save));
134} 134}
135 135
136static int s5pv210_pm_add(struct device *dev) 136static int s5pv210_pm_add(struct device *dev, struct subsys_interface *sif)
137{ 137{
138 pm_cpu_prep = s5pv210_pm_prepare; 138 pm_cpu_prep = s5pv210_pm_prepare;
139 pm_cpu_sleep = s5pv210_cpu_suspend; 139 pm_cpu_sleep = s5pv210_cpu_suspend;
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index eff8a96c75ee..068b754bc348 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -30,6 +30,7 @@
30#include <linux/serial_sci.h> 30#include <linux/serial_sci.h>
31#include <linux/smsc911x.h> 31#include <linux/smsc911x.h>
32#include <linux/gpio.h> 32#include <linux/gpio.h>
33#include <linux/videodev2.h>
33#include <linux/input.h> 34#include <linux/input.h>
34#include <linux/input/sh_keysc.h> 35#include <linux/input/sh_keysc.h>
35#include <linux/mmc/host.h> 36#include <linux/mmc/host.h>
@@ -37,7 +38,6 @@
37#include <linux/mmc/sh_mobile_sdhi.h> 38#include <linux/mmc/sh_mobile_sdhi.h>
38#include <linux/mfd/tmio.h> 39#include <linux/mfd/tmio.h>
39#include <linux/sh_clk.h> 40#include <linux/sh_clk.h>
40#include <linux/dma-mapping.h>
41#include <video/sh_mobile_lcdc.h> 41#include <video/sh_mobile_lcdc.h>
42#include <video/sh_mipi_dsi.h> 42#include <video/sh_mipi_dsi.h>
43#include <sound/sh_fsi.h> 43#include <sound/sh_fsi.h>
@@ -159,19 +159,12 @@ static struct resource sh_mmcif_resources[] = {
159 }, 159 },
160}; 160};
161 161
162static struct sh_mmcif_dma sh_mmcif_dma = {
163 .chan_priv_rx = {
164 .slave_id = SHDMA_SLAVE_MMCIF_RX,
165 },
166 .chan_priv_tx = {
167 .slave_id = SHDMA_SLAVE_MMCIF_TX,
168 },
169};
170static struct sh_mmcif_plat_data sh_mmcif_platdata = { 162static struct sh_mmcif_plat_data sh_mmcif_platdata = {
171 .sup_pclk = 0, 163 .sup_pclk = 0,
172 .ocr = MMC_VDD_165_195, 164 .ocr = MMC_VDD_165_195,
173 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE, 165 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
174 .dma = &sh_mmcif_dma, 166 .slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
167 .slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
175}; 168};
176 169
177static struct platform_device mmc_device = { 170static struct platform_device mmc_device = {
@@ -321,12 +314,11 @@ static struct resource mipidsi0_resources[] = {
321 }, 314 },
322}; 315};
323 316
324#define DSI0PHYCR 0xe615006c
325static int sh_mipi_set_dot_clock(struct platform_device *pdev, 317static int sh_mipi_set_dot_clock(struct platform_device *pdev,
326 void __iomem *base, 318 void __iomem *base,
327 int enable) 319 int enable)
328{ 320{
329 struct clk *pck; 321 struct clk *pck, *phy;
330 int ret; 322 int ret;
331 323
332 pck = clk_get(&pdev->dev, "dsip_clk"); 324 pck = clk_get(&pdev->dev, "dsip_clk");
@@ -335,18 +327,27 @@ static int sh_mipi_set_dot_clock(struct platform_device *pdev,
335 goto sh_mipi_set_dot_clock_pck_err; 327 goto sh_mipi_set_dot_clock_pck_err;
336 } 328 }
337 329
330 phy = clk_get(&pdev->dev, "dsiphy_clk");
331 if (IS_ERR(phy)) {
332 ret = PTR_ERR(phy);
333 goto sh_mipi_set_dot_clock_phy_err;
334 }
335
338 if (enable) { 336 if (enable) {
339 clk_set_rate(pck, clk_round_rate(pck, 24000000)); 337 clk_set_rate(pck, clk_round_rate(pck, 24000000));
340 __raw_writel(0x2a809010, DSI0PHYCR); 338 clk_set_rate(phy, clk_round_rate(pck, 510000000));
341 clk_enable(pck); 339 clk_enable(pck);
340 clk_enable(phy);
342 } else { 341 } else {
343 clk_disable(pck); 342 clk_disable(pck);
343 clk_disable(phy);
344 } 344 }
345 345
346 ret = 0; 346 ret = 0;
347 347
348 clk_put(phy);
349sh_mipi_set_dot_clock_phy_err:
348 clk_put(pck); 350 clk_put(pck);
349
350sh_mipi_set_dot_clock_pck_err: 351sh_mipi_set_dot_clock_pck_err:
351 return ret; 352 return ret;
352} 353}
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index aab0a349f759..eeb4d9664584 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -295,15 +295,6 @@ static struct resource sh_mmcif_resources[] = {
295 }, 295 },
296}; 296};
297 297
298static struct sh_mmcif_dma sh_mmcif_dma = {
299 .chan_priv_rx = {
300 .slave_id = SHDMA_SLAVE_MMCIF_RX,
301 },
302 .chan_priv_tx = {
303 .slave_id = SHDMA_SLAVE_MMCIF_TX,
304 },
305};
306
307static struct sh_mmcif_plat_data sh_mmcif_plat = { 298static struct sh_mmcif_plat_data sh_mmcif_plat = {
308 .sup_pclk = 0, 299 .sup_pclk = 0,
309 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, 300 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
@@ -311,7 +302,8 @@ static struct sh_mmcif_plat_data sh_mmcif_plat = {
311 MMC_CAP_8_BIT_DATA | 302 MMC_CAP_8_BIT_DATA |
312 MMC_CAP_NEEDS_POLL, 303 MMC_CAP_NEEDS_POLL,
313 .get_cd = slot_cn7_get_cd, 304 .get_cd = slot_cn7_get_cd,
314 .dma = &sh_mmcif_dma, 305 .slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
306 .slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
315}; 307};
316 308
317static struct platform_device sh_mmcif_device = { 309static struct platform_device sh_mmcif_device = {
diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c
index 857ceeec1bb0..c8e7ca23fc06 100644
--- a/arch/arm/mach-shmobile/board-kota2.c
+++ b/arch/arm/mach-shmobile/board-kota2.c
@@ -143,11 +143,10 @@ static struct gpio_keys_button gpio_buttons[] = {
143static struct gpio_keys_platform_data gpio_key_info = { 143static struct gpio_keys_platform_data gpio_key_info = {
144 .buttons = gpio_buttons, 144 .buttons = gpio_buttons,
145 .nbuttons = ARRAY_SIZE(gpio_buttons), 145 .nbuttons = ARRAY_SIZE(gpio_buttons),
146 .poll_interval = 250, /* polled for now */
147}; 146};
148 147
149static struct platform_device gpio_keys_device = { 148static struct platform_device gpio_keys_device = {
150 .name = "gpio-keys-polled", /* polled for now */ 149 .name = "gpio-keys",
151 .id = -1, 150 .id = -1,
152 .dev = { 151 .dev = {
153 .platform_data = &gpio_key_info, 152 .platform_data = &gpio_key_info,
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 9b42fbd10f8e..a2813247b455 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -43,7 +43,6 @@
43#include <linux/smsc911x.h> 43#include <linux/smsc911x.h>
44#include <linux/sh_intc.h> 44#include <linux/sh_intc.h>
45#include <linux/tca6416_keypad.h> 45#include <linux/tca6416_keypad.h>
46#include <linux/usb/r8a66597.h>
47#include <linux/usb/renesas_usbhs.h> 46#include <linux/usb/renesas_usbhs.h>
48#include <linux/dma-mapping.h> 47#include <linux/dma-mapping.h>
49 48
@@ -145,11 +144,6 @@
145 * 1-2 short | VBUS 5V | Host 144 * 1-2 short | VBUS 5V | Host
146 * open | external VBUS | Function 145 * open | external VBUS | Function
147 * 146 *
148 * *1
149 * CN31 is used as
150 * CONFIG_USB_R8A66597_HCD Host
151 * CONFIG_USB_RENESAS_USBHS Function
152 *
153 * CAUTION 147 * CAUTION
154 * 148 *
155 * renesas_usbhs driver can use external interrupt mode 149 * renesas_usbhs driver can use external interrupt mode
@@ -161,15 +155,6 @@
161 * mackerel can not use external interrupt (IRQ7-PORT167) mode on "USB0", 155 * mackerel can not use external interrupt (IRQ7-PORT167) mode on "USB0",
162 * because Touchscreen is using IRQ7-PORT40. 156 * because Touchscreen is using IRQ7-PORT40.
163 * It is impossible to use IRQ7 demux on this board. 157 * It is impossible to use IRQ7 demux on this board.
164 *
165 * We can use external interrupt mode USB-Function on "USB1".
166 * USB1 can become Host by r8a66597, and become Function by renesas_usbhs.
167 * But don't select both drivers in same time.
168 * These uses same IRQ number for request_irq(), and aren't supporting
169 * IRQF_SHARED / IORESOURCE_IRQ_SHAREABLE.
170 *
171 * Actually these are old/new version of USB driver.
172 * This mean its register will be broken if it supports shared IRQ,
173 */ 158 */
174 159
175/* 160/*
@@ -208,6 +193,16 @@
208 */ 193 */
209 194
210/* 195/*
196 * FSI - AK4642
197 *
198 * it needs amixer settings for playing
199 *
200 * amixer set "Headphone" on
201 * amixer set "HPOUTL Mixer DACH" on
202 * amixer set "HPOUTR Mixer DACH" on
203 */
204
205/*
211 * FIXME !! 206 * FIXME !!
212 * 207 *
213 * gpio_no_direction 208 * gpio_no_direction
@@ -676,51 +671,16 @@ static struct platform_device usbhs0_device = {
676 * Use J30 to select between Host and Function. This setting 671 * Use J30 to select between Host and Function. This setting
677 * can however not be detected by software. Hotplug of USBHS1 672 * can however not be detected by software. Hotplug of USBHS1
678 * is provided via IRQ8. 673 * is provided via IRQ8.
674 *
675 * Current USB1 works as "USB Host".
676 * - set J30 "short"
677 *
678 * If you want to use it as "USB gadget",
679 * - J30 "open"
680 * - modify usbhs1_get_id() USBHS_HOST -> USBHS_GADGET
681 * - add .get_vbus = usbhs_get_vbus in usbhs1_private
679 */ 682 */
680#define IRQ8 evt2irq(0x0300) 683#define IRQ8 evt2irq(0x0300)
681
682/* USBHS1 USB Host support via r8a66597_hcd */
683static void usb1_host_port_power(int port, int power)
684{
685 if (!power) /* only power-on is supported for now */
686 return;
687
688 /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */
689 __raw_writew(__raw_readw(0xE68B0008) | 0x600, 0xE68B0008);
690}
691
692static struct r8a66597_platdata usb1_host_data = {
693 .on_chip = 1,
694 .port_power = usb1_host_port_power,
695};
696
697static struct resource usb1_host_resources[] = {
698 [0] = {
699 .name = "USBHS1",
700 .start = 0xe68b0000,
701 .end = 0xe68b00e6 - 1,
702 .flags = IORESOURCE_MEM,
703 },
704 [1] = {
705 .start = evt2irq(0x1ce0) /* USB1_USB1I0 */,
706 .flags = IORESOURCE_IRQ,
707 },
708};
709
710static struct platform_device usb1_host_device = {
711 .name = "r8a66597_hcd",
712 .id = 1,
713 .dev = {
714 .dma_mask = NULL, /* not use dma */
715 .coherent_dma_mask = 0xffffffff,
716 .platform_data = &usb1_host_data,
717 },
718 .num_resources = ARRAY_SIZE(usb1_host_resources),
719 .resource = usb1_host_resources,
720};
721
722/* USBHS1 USB Function support via renesas_usbhs */
723
724#define USB_PHY_MODE (1 << 4) 684#define USB_PHY_MODE (1 << 4)
725#define USB_PHY_INT_EN ((1 << 3) | (1 << 2)) 685#define USB_PHY_INT_EN ((1 << 3) | (1 << 2))
726#define USB_PHY_ON (1 << 1) 686#define USB_PHY_ON (1 << 1)
@@ -776,7 +736,7 @@ static void usbhs1_hardware_exit(struct platform_device *pdev)
776 736
777static int usbhs1_get_id(struct platform_device *pdev) 737static int usbhs1_get_id(struct platform_device *pdev)
778{ 738{
779 return USBHS_GADGET; 739 return USBHS_HOST;
780} 740}
781 741
782static u32 usbhs1_pipe_cfg[] = { 742static u32 usbhs1_pipe_cfg[] = {
@@ -807,7 +767,6 @@ static struct usbhs_private usbhs1_private = {
807 .hardware_exit = usbhs1_hardware_exit, 767 .hardware_exit = usbhs1_hardware_exit,
808 .get_id = usbhs1_get_id, 768 .get_id = usbhs1_get_id,
809 .phy_reset = usbhs_phy_reset, 769 .phy_reset = usbhs_phy_reset,
810 .get_vbus = usbhs_get_vbus,
811 }, 770 },
812 .driver_param = { 771 .driver_param = {
813 .buswait_bwait = 4, 772 .buswait_bwait = 4,
@@ -1184,15 +1143,6 @@ static struct resource sh_mmcif_resources[] = {
1184 }, 1143 },
1185}; 1144};
1186 1145
1187static struct sh_mmcif_dma sh_mmcif_dma = {
1188 .chan_priv_rx = {
1189 .slave_id = SHDMA_SLAVE_MMCIF_RX,
1190 },
1191 .chan_priv_tx = {
1192 .slave_id = SHDMA_SLAVE_MMCIF_TX,
1193 },
1194};
1195
1196static struct sh_mmcif_plat_data sh_mmcif_plat = { 1146static struct sh_mmcif_plat_data sh_mmcif_plat = {
1197 .sup_pclk = 0, 1147 .sup_pclk = 0,
1198 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, 1148 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
@@ -1200,7 +1150,8 @@ static struct sh_mmcif_plat_data sh_mmcif_plat = {
1200 MMC_CAP_8_BIT_DATA | 1150 MMC_CAP_8_BIT_DATA |
1201 MMC_CAP_NEEDS_POLL, 1151 MMC_CAP_NEEDS_POLL,
1202 .get_cd = slot_cn7_get_cd, 1152 .get_cd = slot_cn7_get_cd,
1203 .dma = &sh_mmcif_dma, 1153 .slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
1154 .slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
1204}; 1155};
1205 1156
1206static struct platform_device sh_mmcif_device = { 1157static struct platform_device sh_mmcif_device = {
@@ -1311,7 +1262,6 @@ static struct platform_device *mackerel_devices[] __initdata = {
1311 &nor_flash_device, 1262 &nor_flash_device,
1312 &smc911x_device, 1263 &smc911x_device,
1313 &lcdc_device, 1264 &lcdc_device,
1314 &usb1_host_device,
1315 &usbhs1_device, 1265 &usbhs1_device,
1316 &usbhs0_device, 1266 &usbhs0_device,
1317 &leds_device, 1267 &leds_device,
@@ -1473,9 +1423,6 @@ static void __init mackerel_init(void)
1473 gpio_pull_down(GPIO_PORT167CR); /* VBUS0_1 pull down */ 1423 gpio_pull_down(GPIO_PORT167CR); /* VBUS0_1 pull down */
1474 gpio_request(GPIO_FN_IDIN_1_113, NULL); 1424 gpio_request(GPIO_FN_IDIN_1_113, NULL);
1475 1425
1476 /* USB phy tweak to make the r8a66597_hcd host driver work */
1477 __raw_writew(0x8a0a, 0xe6058130); /* USBCR4 */
1478
1479 /* enable FSI2 port A (ak4643) */ 1426 /* enable FSI2 port A (ak4643) */
1480 gpio_request(GPIO_FN_FSIAIBT, NULL); 1427 gpio_request(GPIO_FN_FSIAIBT, NULL);
1481 gpio_request(GPIO_FN_FSIAILR, NULL); 1428 gpio_request(GPIO_FN_FSIAILR, NULL);
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index afbead6a6e17..7727cca6136c 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -365,6 +365,114 @@ static struct clk div6_clks[DIV6_NR] = {
365 dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3), 365 dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3),
366}; 366};
367 367
368/* DSI DIV */
369static unsigned long dsiphy_recalc(struct clk *clk)
370{
371 u32 value;
372
373 value = __raw_readl(clk->mapping->base);
374
375 /* FIXME */
376 if (!(value & 0x000B8000))
377 return clk->parent->rate;
378
379 value &= 0x3f;
380 value += 1;
381
382 if ((value < 12) ||
383 (value > 33)) {
384 pr_err("DSIPHY has wrong value (%d)", value);
385 return 0;
386 }
387
388 return clk->parent->rate / value;
389}
390
391static long dsiphy_round_rate(struct clk *clk, unsigned long rate)
392{
393 return clk_rate_mult_range_round(clk, 12, 33, rate);
394}
395
396static void dsiphy_disable(struct clk *clk)
397{
398 u32 value;
399
400 value = __raw_readl(clk->mapping->base);
401 value &= ~0x000B8000;
402
403 __raw_writel(value , clk->mapping->base);
404}
405
406static int dsiphy_enable(struct clk *clk)
407{
408 u32 value;
409 int multi;
410
411 value = __raw_readl(clk->mapping->base);
412 multi = (value & 0x3f) + 1;
413
414 if ((multi < 12) || (multi > 33))
415 return -EIO;
416
417 __raw_writel(value | 0x000B8000, clk->mapping->base);
418
419 return 0;
420}
421
422static int dsiphy_set_rate(struct clk *clk, unsigned long rate)
423{
424 u32 value;
425 int idx;
426
427 idx = rate / clk->parent->rate;
428 if ((idx < 12) || (idx > 33))
429 return -EINVAL;
430
431 idx += -1;
432
433 value = __raw_readl(clk->mapping->base);
434 value = (value & ~0x3f) + idx;
435
436 __raw_writel(value, clk->mapping->base);
437
438 return 0;
439}
440
441static struct clk_ops dsiphy_clk_ops = {
442 .recalc = dsiphy_recalc,
443 .round_rate = dsiphy_round_rate,
444 .set_rate = dsiphy_set_rate,
445 .enable = dsiphy_enable,
446 .disable = dsiphy_disable,
447};
448
449static struct clk_mapping dsi0phy_clk_mapping = {
450 .phys = DSI0PHYCR,
451 .len = 4,
452};
453
454static struct clk_mapping dsi1phy_clk_mapping = {
455 .phys = DSI1PHYCR,
456 .len = 4,
457};
458
459static struct clk dsi0phy_clk = {
460 .ops = &dsiphy_clk_ops,
461 .parent = &div6_clks[DIV6_DSI0P], /* late install */
462 .mapping = &dsi0phy_clk_mapping,
463};
464
465static struct clk dsi1phy_clk = {
466 .ops = &dsiphy_clk_ops,
467 .parent = &div6_clks[DIV6_DSI1P], /* late install */
468 .mapping = &dsi1phy_clk_mapping,
469};
470
471static struct clk *late_main_clks[] = {
472 &dsi0phy_clk,
473 &dsi1phy_clk,
474};
475
368enum { MSTP001, 476enum { MSTP001,
369 MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100, 477 MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100,
370 MSTP219, 478 MSTP219,
@@ -429,6 +537,8 @@ static struct clk_lookup lookups[] = {
429 CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]), 537 CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
430 CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]), 538 CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
431 CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]), 539 CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
540 CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.0", &dsi0phy_clk),
541 CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.1", &dsi1phy_clk),
432 542
433 /* MSTP32 clocks */ 543 /* MSTP32 clocks */
434 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */ 544 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */
@@ -504,6 +614,9 @@ void __init sh73a0_clock_init(void)
504 if (!ret) 614 if (!ret)
505 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); 615 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
506 616
617 for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
618 ret = clk_register(late_main_clks[k]);
619
507 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 620 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
508 621
509 if (!ret) 622 if (!ret)
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index 881d515a9686..cad57578ceed 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -515,8 +515,8 @@ enum {
515 SHDMA_SLAVE_MMCIF_RX, 515 SHDMA_SLAVE_MMCIF_RX,
516}; 516};
517 517
518/* PINT interrupts are located at Linux IRQ 768 and up */ 518/* PINT interrupts are located at Linux IRQ 800 and up */
519#define SH73A0_PINT0_IRQ(irq) ((irq) + 768) 519#define SH73A0_PINT0_IRQ(irq) ((irq) + 800)
520#define SH73A0_PINT1_IRQ(irq) ((irq) + 800) 520#define SH73A0_PINT1_IRQ(irq) ((irq) + 832)
521 521
522#endif /* __ASM_SH73A0_H__ */ 522#endif /* __ASM_SH73A0_H__ */
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c
index 1eda6b0b69e3..9857595eaa79 100644
--- a/arch/arm/mach-shmobile/intc-sh73a0.c
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -19,6 +19,7 @@
19#include <linux/kernel.h> 19#include <linux/kernel.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/interrupt.h> 21#include <linux/interrupt.h>
22#include <linux/module.h>
22#include <linux/irq.h> 23#include <linux/irq.h>
23#include <linux/io.h> 24#include <linux/io.h>
24#include <linux/sh_intc.h> 25#include <linux/sh_intc.h>
@@ -445,6 +446,7 @@ void __init sh73a0_init_irq(void)
445 setup_irq(gic_spi(1 + k), &sh73a0_irq_pin_cascade[k]); 446 setup_irq(gic_spi(1 + k), &sh73a0_irq_pin_cascade[k]);
446 447
447 n = intcs_evt2irq(to_intc_vect(gic_spi(1 + k))); 448 n = intcs_evt2irq(to_intc_vect(gic_spi(1 + k)));
449 WARN_ON(irq_alloc_desc_at(n, numa_node_id()) != n);
448 irq_set_chip_and_handler_name(n, &intca_gic_irq_chip, 450 irq_set_chip_and_handler_name(n, &intca_gic_irq_chip,
449 handle_level_irq, "level"); 451 handle_level_irq, "level");
450 set_irq_flags(n, IRQF_VALID); /* yuck */ 452 set_irq_flags(n, IRQF_VALID); /* yuck */
diff --git a/arch/arm/mach-shmobile/pfc-r8a7779.c b/arch/arm/mach-shmobile/pfc-r8a7779.c
index 963532f2b2c4..d14c9b048077 100644
--- a/arch/arm/mach-shmobile/pfc-r8a7779.c
+++ b/arch/arm/mach-shmobile/pfc-r8a7779.c
@@ -2120,7 +2120,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
2120 FN_AUDATA3, 0, 0, 0 } 2120 FN_AUDATA3, 0, 0, 0 }
2121 }, 2121 },
2122 { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32, 2122 { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
2123 3, 1, 1, 1, 1, 1, 1, 3, 3, 1, 2123 3, 1, 1, 1, 1, 1, 1, 3, 3,
2124 1, 1, 1, 1, 1, 1, 3, 3, 3, 2) { 2124 1, 1, 1, 1, 1, 1, 3, 3, 3, 2) {
2125 /* IP4_31_29 [3] */ 2125 /* IP4_31_29 [3] */
2126 FN_DU1_DB0, FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0, 2126 FN_DU1_DB0, FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0,
diff --git a/arch/arm/mach-shmobile/pfc-sh7372.c b/arch/arm/mach-shmobile/pfc-sh7372.c
index 1bd6585a6acf..336093f9210a 100644
--- a/arch/arm/mach-shmobile/pfc-sh7372.c
+++ b/arch/arm/mach-shmobile/pfc-sh7372.c
@@ -23,6 +23,7 @@
23#include <linux/init.h> 23#include <linux/init.h>
24#include <linux/kernel.h> 24#include <linux/kernel.h>
25#include <linux/gpio.h> 25#include <linux/gpio.h>
26#include <mach/irqs.h>
26#include <mach/sh7372.h> 27#include <mach/sh7372.h>
27 28
28#define CPU_ALL_PORT(fn, pfx, sfx) \ 29#define CPU_ALL_PORT(fn, pfx, sfx) \
@@ -1594,6 +1595,43 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
1594 { }, 1595 { },
1595}; 1596};
1596 1597
1598#define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5))
1599#define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5))
1600static struct pinmux_irq pinmux_irqs[] = {
1601 PINMUX_IRQ(EXT_IRQ16L(0), PORT6_FN0, PORT162_FN0),
1602 PINMUX_IRQ(EXT_IRQ16L(1), PORT12_FN0),
1603 PINMUX_IRQ(EXT_IRQ16L(2), PORT4_FN0, PORT5_FN0),
1604 PINMUX_IRQ(EXT_IRQ16L(3), PORT8_FN0, PORT16_FN0),
1605 PINMUX_IRQ(EXT_IRQ16L(4), PORT17_FN0, PORT163_FN0),
1606 PINMUX_IRQ(EXT_IRQ16L(5), PORT18_FN0),
1607 PINMUX_IRQ(EXT_IRQ16L(6), PORT39_FN0, PORT164_FN0),
1608 PINMUX_IRQ(EXT_IRQ16L(7), PORT40_FN0, PORT167_FN0),
1609 PINMUX_IRQ(EXT_IRQ16L(8), PORT41_FN0, PORT168_FN0),
1610 PINMUX_IRQ(EXT_IRQ16L(9), PORT42_FN0, PORT169_FN0),
1611 PINMUX_IRQ(EXT_IRQ16L(10), PORT65_FN0),
1612 PINMUX_IRQ(EXT_IRQ16L(11), PORT67_FN0),
1613 PINMUX_IRQ(EXT_IRQ16L(12), PORT80_FN0, PORT137_FN0),
1614 PINMUX_IRQ(EXT_IRQ16L(13), PORT81_FN0, PORT145_FN0),
1615 PINMUX_IRQ(EXT_IRQ16L(14), PORT82_FN0, PORT146_FN0),
1616 PINMUX_IRQ(EXT_IRQ16L(15), PORT83_FN0, PORT147_FN0),
1617 PINMUX_IRQ(EXT_IRQ16H(16), PORT84_FN0, PORT170_FN0),
1618 PINMUX_IRQ(EXT_IRQ16H(17), PORT85_FN0),
1619 PINMUX_IRQ(EXT_IRQ16H(18), PORT86_FN0),
1620 PINMUX_IRQ(EXT_IRQ16H(19), PORT87_FN0),
1621 PINMUX_IRQ(EXT_IRQ16H(20), PORT92_FN0),
1622 PINMUX_IRQ(EXT_IRQ16H(21), PORT93_FN0),
1623 PINMUX_IRQ(EXT_IRQ16H(22), PORT94_FN0),
1624 PINMUX_IRQ(EXT_IRQ16H(23), PORT95_FN0),
1625 PINMUX_IRQ(EXT_IRQ16H(24), PORT112_FN0),
1626 PINMUX_IRQ(EXT_IRQ16H(25), PORT119_FN0),
1627 PINMUX_IRQ(EXT_IRQ16H(26), PORT121_FN0, PORT172_FN0),
1628 PINMUX_IRQ(EXT_IRQ16H(27), PORT122_FN0, PORT180_FN0),
1629 PINMUX_IRQ(EXT_IRQ16H(28), PORT123_FN0, PORT181_FN0),
1630 PINMUX_IRQ(EXT_IRQ16H(29), PORT129_FN0, PORT182_FN0),
1631 PINMUX_IRQ(EXT_IRQ16H(30), PORT130_FN0, PORT183_FN0),
1632 PINMUX_IRQ(EXT_IRQ16H(31), PORT138_FN0, PORT184_FN0),
1633};
1634
1597static struct pinmux_info sh7372_pinmux_info = { 1635static struct pinmux_info sh7372_pinmux_info = {
1598 .name = "sh7372_pfc", 1636 .name = "sh7372_pfc",
1599 .reserved_id = PINMUX_RESERVED, 1637 .reserved_id = PINMUX_RESERVED,
@@ -1614,6 +1652,9 @@ static struct pinmux_info sh7372_pinmux_info = {
1614 1652
1615 .gpio_data = pinmux_data, 1653 .gpio_data = pinmux_data,
1616 .gpio_data_size = ARRAY_SIZE(pinmux_data), 1654 .gpio_data_size = ARRAY_SIZE(pinmux_data),
1655
1656 .gpio_irq = pinmux_irqs,
1657 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
1617}; 1658};
1618 1659
1619void sh7372_pinmux_init(void) 1660void sh7372_pinmux_init(void)
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index 0d159d64a345..2d0d4212be41 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -80,7 +80,7 @@ int __cpuinit sh73a0_boot_secondary(unsigned int cpu)
80 /* enable cache coherency */ 80 /* enable cache coherency */
81 modify_scu_cpu_psr(0, 3 << (cpu * 8)); 81 modify_scu_cpu_psr(0, 3 << (cpu * 8));
82 82
83 if (((__raw_readw(__io(PSTR)) >> (4 * cpu)) & 3) == 3) 83 if (((__raw_readl(__io(PSTR)) >> (4 * cpu)) & 3) == 3)
84 __raw_writel(1 << cpu, __io(WUPCR)); /* wake up */ 84 __raw_writel(1 << cpu, __io(WUPCR)); /* wake up */
85 else 85 else
86 __raw_writel(1 << cpu, __io(SRESCR)); /* reset */ 86 __raw_writel(1 << cpu, __io(SRESCR)); /* reset */
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index fcf4f377b1dc..330afdfa2475 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -60,9 +60,9 @@ static struct plat_serial8250_port debug_uart_platform_data[] = {
60 .uartclk = 216000000, 60 .uartclk = 216000000,
61 }, { 61 }, {
62 /* serial port on mini-pcie */ 62 /* serial port on mini-pcie */
63 .membase = IO_ADDRESS(TEGRA_UARTD_BASE), 63 .membase = IO_ADDRESS(TEGRA_UARTC_BASE),
64 .mapbase = TEGRA_UARTD_BASE, 64 .mapbase = TEGRA_UARTC_BASE,
65 .irq = INT_UARTD, 65 .irq = INT_UARTC,
66 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE, 66 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
67 .type = PORT_TEGRA, 67 .type = PORT_TEGRA,
68 .iotype = UPIO_MEM, 68 .iotype = UPIO_MEM,
@@ -174,7 +174,7 @@ static void __init tegra_paz00_fixup(struct tag *tags, char **cmdline,
174static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = { 174static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = {
175 /* name parent rate enabled */ 175 /* name parent rate enabled */
176 { "uarta", "pll_p", 216000000, true }, 176 { "uarta", "pll_p", 216000000, true },
177 { "uartd", "pll_p", 216000000, true }, 177 { "uartc", "pll_p", 216000000, true },
178 178
179 { "pll_p_out4", "pll_p", 24000000, true }, 179 { "pll_p_out4", "pll_p", 24000000, true },
180 { "usbd", "clk_m", 12000000, false }, 180 { "usbd", "clk_m", 12000000, false },
diff --git a/arch/arm/mach-tegra/board-paz00.h b/arch/arm/mach-tegra/board-paz00.h
index ffa83f580db6..3c9f8da37ea3 100644
--- a/arch/arm/mach-tegra/board-paz00.h
+++ b/arch/arm/mach-tegra/board-paz00.h
@@ -22,7 +22,7 @@
22/* SDCARD */ 22/* SDCARD */
23#define TEGRA_GPIO_SD1_CD TEGRA_GPIO_PV5 23#define TEGRA_GPIO_SD1_CD TEGRA_GPIO_PV5
24#define TEGRA_GPIO_SD1_WP TEGRA_GPIO_PH1 24#define TEGRA_GPIO_SD1_WP TEGRA_GPIO_PH1
25#define TEGRA_GPIO_SD1_POWER TEGRA_GPIO_PT3 25#define TEGRA_GPIO_SD1_POWER TEGRA_GPIO_PV1
26 26
27/* ULPI */ 27/* ULPI */
28#define TEGRA_ULPI_RST TEGRA_GPIO_PV0 28#define TEGRA_ULPI_RST TEGRA_GPIO_PV0
diff --git a/arch/arm/mach-tegra/include/mach/dma.h b/arch/arm/mach-tegra/include/mach/dma.h
index d0132e8031a1..3c9339058bec 100644
--- a/arch/arm/mach-tegra/include/mach/dma.h
+++ b/arch/arm/mach-tegra/include/mach/dma.h
@@ -23,11 +23,6 @@
23 23
24#include <linux/list.h> 24#include <linux/list.h>
25 25
26#if defined(CONFIG_TEGRA_SYSTEM_DMA)
27
28struct tegra_dma_req;
29struct tegra_dma_channel;
30
31#define TEGRA_DMA_REQ_SEL_CNTR 0 26#define TEGRA_DMA_REQ_SEL_CNTR 0
32#define TEGRA_DMA_REQ_SEL_I2S_2 1 27#define TEGRA_DMA_REQ_SEL_I2S_2 1
33#define TEGRA_DMA_REQ_SEL_I2S_1 2 28#define TEGRA_DMA_REQ_SEL_I2S_1 2
@@ -56,6 +51,11 @@ struct tegra_dma_channel;
56#define TEGRA_DMA_REQ_SEL_OWR 25 51#define TEGRA_DMA_REQ_SEL_OWR 25
57#define TEGRA_DMA_REQ_SEL_INVALID 31 52#define TEGRA_DMA_REQ_SEL_INVALID 31
58 53
54#if defined(CONFIG_TEGRA_SYSTEM_DMA)
55
56struct tegra_dma_req;
57struct tegra_dma_channel;
58
59enum tegra_dma_mode { 59enum tegra_dma_mode {
60 TEGRA_DMA_SHARED = 1, 60 TEGRA_DMA_SHARED = 1,
61 TEGRA_DMA_MODE_CONTINOUS = 2, 61 TEGRA_DMA_MODE_CONTINOUS = 2,
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 1a3ca2488164..7edef9121632 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -631,7 +631,8 @@ comment "Processor Features"
631 631
632config ARM_LPAE 632config ARM_LPAE
633 bool "Support for the Large Physical Address Extension" 633 bool "Support for the Large Physical Address Extension"
634 depends on MMU && CPU_V7 634 depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
635 !CPU_32v4 && !CPU_32v3
635 help 636 help
636 Say Y if you have an ARMv7 processor supporting the LPAE page 637 Say Y if you have an ARMv7 processor supporting the LPAE page
637 table format and you would like to access memory beyond the 638 table format and you would like to access memory beyond the
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 07c4bc8ea0a4..a655d3da386d 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -54,9 +54,15 @@ loop1:
54 and r1, r1, #7 @ mask of the bits for current cache only 54 and r1, r1, #7 @ mask of the bits for current cache only
55 cmp r1, #2 @ see what cache we have at this level 55 cmp r1, #2 @ see what cache we have at this level
56 blt skip @ skip if no cache, or just i-cache 56 blt skip @ skip if no cache, or just i-cache
57#ifdef CONFIG_PREEMPT
58 save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic
59#endif
57 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 60 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
58 isb @ isb to sych the new cssr&csidr 61 isb @ isb to sych the new cssr&csidr
59 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr 62 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
63#ifdef CONFIG_PREEMPT
64 restore_irqs_notrace r9
65#endif
60 and r2, r1, #7 @ extract the length of the cache lines 66 and r2, r1, #7 @ extract the length of the cache lines
61 add r2, r2, #4 @ add 4 (line length offset) 67 add r2, r2, #4 @ add 4 (line length offset)
62 ldr r4, =0x3ff 68 ldr r4, =0x3ff
diff --git a/arch/arm/plat-omap/include/plat/omap-secure.h b/arch/arm/plat-omap/include/plat/omap-secure.h
index 64f9d1c7f1bb..3047ff923a63 100644
--- a/arch/arm/plat-omap/include/plat/omap-secure.h
+++ b/arch/arm/plat-omap/include/plat/omap-secure.h
@@ -3,7 +3,7 @@
3 3
4#include <linux/types.h> 4#include <linux/types.h>
5 5
6#ifdef CONFIG_ARCH_OMAP2PLUS 6#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
7extern int omap_secure_ram_reserve_memblock(void); 7extern int omap_secure_ram_reserve_memblock(void);
8#else 8#else
9static inline void omap_secure_ram_reserve_memblock(void) 9static inline void omap_secure_ram_reserve_memblock(void)
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index e5a2fde29b19..089899a7db72 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -789,10 +789,7 @@ void __init orion_xor1_init(unsigned long mapbase_low,
789/***************************************************************************** 789/*****************************************************************************
790 * EHCI 790 * EHCI
791 ****************************************************************************/ 791 ****************************************************************************/
792static struct orion_ehci_data orion_ehci_data = { 792static struct orion_ehci_data orion_ehci_data;
793 .phy_version = EHCI_PHY_NA,
794};
795
796static u64 ehci_dmamask = DMA_BIT_MASK(32); 793static u64 ehci_dmamask = DMA_BIT_MASK(32);
797 794
798 795
@@ -812,8 +809,10 @@ static struct platform_device orion_ehci = {
812}; 809};
813 810
814void __init orion_ehci_init(unsigned long mapbase, 811void __init orion_ehci_init(unsigned long mapbase,
815 unsigned long irq) 812 unsigned long irq,
813 enum orion_ehci_phy_ver phy_version)
816{ 814{
815 orion_ehci_data.phy_version = phy_version;
817 fill_resources(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1, 816 fill_resources(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1,
818 irq); 817 irq);
819 818
diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h
index 0fe08d77e835..a7fa005a5a0e 100644
--- a/arch/arm/plat-orion/include/plat/common.h
+++ b/arch/arm/plat-orion/include/plat/common.h
@@ -89,7 +89,8 @@ void __init orion_xor1_init(unsigned long mapbase_low,
89 unsigned long irq_1); 89 unsigned long irq_1);
90 90
91void __init orion_ehci_init(unsigned long mapbase, 91void __init orion_ehci_init(unsigned long mapbase,
92 unsigned long irq); 92 unsigned long irq,
93 enum orion_ehci_phy_ver phy_version);
93 94
94void __init orion_ehci_1_init(unsigned long mapbase, 95void __init orion_ehci_1_init(unsigned long mapbase,
95 unsigned long irq); 96 unsigned long irq);
diff --git a/arch/arm/plat-orion/mpp.c b/arch/arm/plat-orion/mpp.c
index 91553432711d..3b1e17bd3d17 100644
--- a/arch/arm/plat-orion/mpp.c
+++ b/arch/arm/plat-orion/mpp.c
@@ -64,8 +64,7 @@ void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
64 gpio_mode |= GPIO_INPUT_OK; 64 gpio_mode |= GPIO_INPUT_OK;
65 if (*mpp_list & MPP_OUTPUT_MASK) 65 if (*mpp_list & MPP_OUTPUT_MASK)
66 gpio_mode |= GPIO_OUTPUT_OK; 66 gpio_mode |= GPIO_OUTPUT_OK;
67 if (sel != 0) 67
68 gpio_mode = 0;
69 orion_gpio_set_valid(num, gpio_mode); 68 orion_gpio_set_valid(num, gpio_mode);
70 } 69 }
71 70
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 32a6e394db24..f10768e988d4 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -468,8 +468,10 @@ void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
468{ 468{
469 struct s3c2410_platform_i2c *npd; 469 struct s3c2410_platform_i2c *npd;
470 470
471 if (!pd) 471 if (!pd) {
472 pd = &default_i2c_data; 472 pd = &default_i2c_data;
473 pd->bus_num = 0;
474 }
473 475
474 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), 476 npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
475 &s3c_device_i2c0); 477 &s3c_device_i2c0);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-19 02:42:44 -0500