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-rw-r--r--arch/arm/kernel/entry-armv.S6
-rw-r--r--arch/arm/mm/abort-ev4.S8
-rw-r--r--arch/arm/mm/abort-ev4t.S8
-rw-r--r--arch/arm/mm/abort-ev5t.S8
-rw-r--r--arch/arm/mm/abort-ev5tj.S12
-rw-r--r--arch/arm/mm/abort-ev6.S12
-rw-r--r--arch/arm/mm/abort-ev7.S4
-rw-r--r--arch/arm/mm/abort-lv4t.S12
-rw-r--r--arch/arm/mm/abort-nommu.S4
-rw-r--r--arch/arm/mm/proc-arm6_7.S10
10 files changed, 38 insertions, 46 deletions
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index af2fba7a4cae..85298c093256 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -56,14 +56,12 @@
56 .endm 56 .endm
57 57
58 .macro dabt_helper 58 .macro dabt_helper
59 mov r2, r4
60 mov r3, r5
61 59
62 @ 60 @
63 @ Call the processor-specific abort handler: 61 @ Call the processor-specific abort handler:
64 @ 62 @
65 @ r2 - aborted context pc 63 @ r4 - aborted context pc
66 @ r3 - aborted context cpsr 64 @ r5 - aborted context psr
67 @ 65 @
68 @ The abort handler must return the aborted address in r0, and 66 @ The abort handler must return the aborted address in r0, and
69 @ the fault status register in r1. r9 must be preserved. 67 @ the fault status register in r1. r9 must be preserved.
diff --git a/arch/arm/mm/abort-ev4.S b/arch/arm/mm/abort-ev4.S
index 4f18f9e87bae..beb112bdc049 100644
--- a/arch/arm/mm/abort-ev4.S
+++ b/arch/arm/mm/abort-ev4.S
@@ -3,8 +3,8 @@
3/* 3/*
4 * Function: v4_early_abort 4 * Function: v4_early_abort
5 * 5 *
6 * Params : r2 = address of aborted instruction 6 * Params : r4 = aborted context pc
7 * : r3 = saved SPSR 7 * : r5 = aborted context psr
8 * 8 *
9 * Returns : r0 = address of abort 9 * Returns : r0 = address of abort
10 * : r1 = FSR, bit 11 = write 10 * : r1 = FSR, bit 11 = write
@@ -21,10 +21,8 @@
21ENTRY(v4_early_abort) 21ENTRY(v4_early_abort)
22 mrc p15, 0, r1, c5, c0, 0 @ get FSR 22 mrc p15, 0, r1, c5, c0, 0 @ get FSR
23 mrc p15, 0, r0, c6, c0, 0 @ get FAR 23 mrc p15, 0, r0, c6, c0, 0 @ get FAR
24 ldr r3, [r2] @ read aborted ARM instruction 24 ldr r3, [r4] @ read aborted ARM instruction
25 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR 25 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
26 tst r3, #1 << 20 @ L = 1 -> write? 26 tst r3, #1 << 20 @ L = 1 -> write?
27 orreq r1, r1, #1 << 11 @ yes. 27 orreq r1, r1, #1 << 11 @ yes.
28 mov pc, lr 28 mov pc, lr
29
30
diff --git a/arch/arm/mm/abort-ev4t.S b/arch/arm/mm/abort-ev4t.S
index 9910123079ce..eaa4ac023959 100644
--- a/arch/arm/mm/abort-ev4t.S
+++ b/arch/arm/mm/abort-ev4t.S
@@ -4,8 +4,8 @@
4/* 4/*
5 * Function: v4t_early_abort 5 * Function: v4t_early_abort
6 * 6 *
7 * Params : r2 = address of aborted instruction 7 * Params : r4 = aborted context pc
8 * : r3 = saved SPSR 8 * : r5 = aborted context psr
9 * 9 *
10 * Returns : r0 = address of abort 10 * Returns : r0 = address of abort
11 * : r1 = FSR, bit 11 = write 11 * : r1 = FSR, bit 11 = write
@@ -22,8 +22,8 @@
22ENTRY(v4t_early_abort) 22ENTRY(v4t_early_abort)
23 mrc p15, 0, r1, c5, c0, 0 @ get FSR 23 mrc p15, 0, r1, c5, c0, 0 @ get FSR
24 mrc p15, 0, r0, c6, c0, 0 @ get FAR 24 mrc p15, 0, r0, c6, c0, 0 @ get FAR
25 do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3 25 do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
26 ldreq r3, [r2] @ read aborted ARM instruction 26 ldreq r3, [r4] @ read aborted ARM instruction
27 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR 27 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
28 tst r3, #1 << 20 @ check write 28 tst r3, #1 << 20 @ check write
29 orreq r1, r1, #1 << 11 29 orreq r1, r1, #1 << 11
diff --git a/arch/arm/mm/abort-ev5t.S b/arch/arm/mm/abort-ev5t.S
index 800e8d42d39e..97eee7c48019 100644
--- a/arch/arm/mm/abort-ev5t.S
+++ b/arch/arm/mm/abort-ev5t.S
@@ -4,8 +4,8 @@
4/* 4/*
5 * Function: v5t_early_abort 5 * Function: v5t_early_abort
6 * 6 *
7 * Params : r2 = address of aborted instruction 7 * Params : r4 = aborted context pc
8 * : r3 = saved SPSR 8 * : r5 = aborted context psr
9 * 9 *
10 * Returns : r0 = address of abort 10 * Returns : r0 = address of abort
11 * : r1 = FSR, bit 11 = write 11 * : r1 = FSR, bit 11 = write
@@ -22,8 +22,8 @@
22ENTRY(v5t_early_abort) 22ENTRY(v5t_early_abort)
23 mrc p15, 0, r1, c5, c0, 0 @ get FSR 23 mrc p15, 0, r1, c5, c0, 0 @ get FSR
24 mrc p15, 0, r0, c6, c0, 0 @ get FAR 24 mrc p15, 0, r0, c6, c0, 0 @ get FAR
25 do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3 25 do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
26 ldreq r3, [r2] @ read aborted ARM instruction 26 ldreq r3, [r4] @ read aborted ARM instruction
27 bic r1, r1, #1 << 11 @ clear bits 11 of FSR 27 bic r1, r1, #1 << 11 @ clear bits 11 of FSR
28 do_ldrd_abort tmp=r2, insn=r3 28 do_ldrd_abort tmp=r2, insn=r3
29 tst r3, #1 << 20 @ check write 29 tst r3, #1 << 20 @ check write
diff --git a/arch/arm/mm/abort-ev5tj.S b/arch/arm/mm/abort-ev5tj.S
index bcb58d2fc11a..9a365cf1936f 100644
--- a/arch/arm/mm/abort-ev5tj.S
+++ b/arch/arm/mm/abort-ev5tj.S
@@ -4,8 +4,8 @@
4/* 4/*
5 * Function: v5tj_early_abort 5 * Function: v5tj_early_abort
6 * 6 *
7 * Params : r2 = address of aborted instruction 7 * Params : r4 = aborted context pc
8 * : r3 = saved SPSR 8 * : r5 = aborted context psr
9 * 9 *
10 * Returns : r0 = address of abort 10 * Returns : r0 = address of abort
11 * : r1 = FSR, bit 11 = write 11 * : r1 = FSR, bit 11 = write
@@ -23,13 +23,11 @@ ENTRY(v5tj_early_abort)
23 mrc p15, 0, r1, c5, c0, 0 @ get FSR 23 mrc p15, 0, r1, c5, c0, 0 @ get FSR
24 mrc p15, 0, r0, c6, c0, 0 @ get FAR 24 mrc p15, 0, r0, c6, c0, 0 @ get FAR
25 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR 25 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
26 tst r3, #PSR_J_BIT @ Java? 26 tst r5, #PSR_J_BIT @ Java?
27 movne pc, lr 27 movne pc, lr
28 do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3 28 do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
29 ldreq r3, [r2] @ read aborted ARM instruction 29 ldreq r3, [r4] @ read aborted ARM instruction
30 do_ldrd_abort tmp=r2, insn=r3 30 do_ldrd_abort tmp=r2, insn=r3
31 tst r3, #1 << 20 @ L = 0 -> write 31 tst r3, #1 << 20 @ L = 0 -> write
32 orreq r1, r1, #1 << 11 @ yes. 32 orreq r1, r1, #1 << 11 @ yes.
33 mov pc, lr 33 mov pc, lr
34
35
diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
index ef526e702a5c..52db4a3fc5f2 100644
--- a/arch/arm/mm/abort-ev6.S
+++ b/arch/arm/mm/abort-ev6.S
@@ -4,8 +4,8 @@
4/* 4/*
5 * Function: v6_early_abort 5 * Function: v6_early_abort
6 * 6 *
7 * Params : r2 = address of aborted instruction 7 * Params : r4 = aborted context pc
8 * : r3 = saved SPSR 8 * : r5 = aborted context psr
9 * 9 *
10 * Returns : r0 = address of abort 10 * Returns : r0 = address of abort
11 * : r1 = FSR, bit 11 = write 11 * : r1 = FSR, bit 11 = write
@@ -33,10 +33,10 @@ ENTRY(v6_early_abort)
33 * The test below covers all the write situations, including Java bytecodes 33 * The test below covers all the write situations, including Java bytecodes
34 */ 34 */
35 bic r1, r1, #1 << 11 @ clear bit 11 of FSR 35 bic r1, r1, #1 << 11 @ clear bit 11 of FSR
36 tst r3, #PSR_J_BIT @ Java? 36 tst r5, #PSR_J_BIT @ Java?
37 movne pc, lr 37 movne pc, lr
38 do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3 38 do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
39 ldreq r3, [r2] @ read aborted ARM instruction 39 ldreq r3, [r4] @ read aborted ARM instruction
40#ifdef CONFIG_CPU_ENDIAN_BE8 40#ifdef CONFIG_CPU_ENDIAN_BE8
41 reveq r3, r3 41 reveq r3, r3
42#endif 42#endif
@@ -44,5 +44,3 @@ ENTRY(v6_early_abort)
44 tst r3, #1 << 20 @ L = 0 -> write 44 tst r3, #1 << 20 @ L = 0 -> write
45 orreq r1, r1, #1 << 11 @ yes. 45 orreq r1, r1, #1 << 11 @ yes.
46 mov pc, lr 46 mov pc, lr
47
48
diff --git a/arch/arm/mm/abort-ev7.S b/arch/arm/mm/abort-ev7.S
index ec88b157d3bb..6cb51431a859 100644
--- a/arch/arm/mm/abort-ev7.S
+++ b/arch/arm/mm/abort-ev7.S
@@ -3,8 +3,8 @@
3/* 3/*
4 * Function: v7_early_abort 4 * Function: v7_early_abort
5 * 5 *
6 * Params : r2 = address of aborted instruction 6 * Params : r4 = aborted context pc
7 * : r3 = saved SPSR 7 * : r5 = aborted context psr
8 * 8 *
9 * Returns : r0 = address of abort 9 * Returns : r0 = address of abort
10 * : r1 = FSR, bit 11 = write 10 * : r1 = FSR, bit 11 = write
diff --git a/arch/arm/mm/abort-lv4t.S b/arch/arm/mm/abort-lv4t.S
index 9fb7b0e25ea1..fea7514225a6 100644
--- a/arch/arm/mm/abort-lv4t.S
+++ b/arch/arm/mm/abort-lv4t.S
@@ -3,8 +3,8 @@
3/* 3/*
4 * Function: v4t_late_abort 4 * Function: v4t_late_abort
5 * 5 *
6 * Params : r2 = address of aborted instruction 6 * Params : r4 = aborted context pc
7 * : r3 = saved SPSR 7 * : r5 = aborted context psr
8 * 8 *
9 * Returns : r0 = address of abort 9 * Returns : r0 = address of abort
10 * : r1 = FSR, bit 11 = write 10 * : r1 = FSR, bit 11 = write
@@ -18,7 +18,7 @@
18 * picture. Unfortunately, this does happen. We live with it. 18 * picture. Unfortunately, this does happen. We live with it.
19 */ 19 */
20ENTRY(v4t_late_abort) 20ENTRY(v4t_late_abort)
21 tst r3, #PSR_T_BIT @ check for thumb mode 21 tst r5, #PSR_T_BIT @ check for thumb mode
22#ifdef CONFIG_CPU_CP15_MMU 22#ifdef CONFIG_CPU_CP15_MMU
23 mrc p15, 0, r1, c5, c0, 0 @ get FSR 23 mrc p15, 0, r1, c5, c0, 0 @ get FSR
24 mrc p15, 0, r0, c6, c0, 0 @ get FAR 24 mrc p15, 0, r0, c6, c0, 0 @ get FAR
@@ -28,7 +28,7 @@ ENTRY(v4t_late_abort)
28 mov r1, #0 28 mov r1, #0
29#endif 29#endif
30 bne .data_thumb_abort 30 bne .data_thumb_abort
31 ldr r8, [r2] @ read arm instruction 31 ldr r8, [r4] @ read arm instruction
32 tst r8, #1 << 20 @ L = 1 -> write? 32 tst r8, #1 << 20 @ L = 1 -> write?
33 orreq r1, r1, #1 << 11 @ yes. 33 orreq r1, r1, #1 << 11 @ yes.
34 and r7, r8, #15 << 24 34 and r7, r8, #15 << 24
@@ -52,7 +52,7 @@ ENTRY(v4t_late_abort)
52/* e */ b .data_unknown 52/* e */ b .data_unknown
53/* f */ 53/* f */
54.data_unknown: @ Part of jumptable 54.data_unknown: @ Part of jumptable
55 mov r0, r2 55 mov r0, r4
56 mov r1, r8 56 mov r1, r8
57 mov r2, sp 57 mov r2, sp
58 bl baddataabort 58 bl baddataabort
@@ -159,7 +159,7 @@ ENTRY(v4t_late_abort)
159 b .data_unknown @ F: MUL? 159 b .data_unknown @ F: MUL?
160 160
161.data_thumb_abort: 161.data_thumb_abort:
162 ldrh r8, [r2] @ read instruction 162 ldrh r8, [r4] @ read instruction
163 tst r8, #1 << 11 @ L = 1 -> write? 163 tst r8, #1 << 11 @ L = 1 -> write?
164 orreq r1, r1, #1 << 8 @ yes 164 orreq r1, r1, #1 << 8 @ yes
165 and r7, r8, #15 << 12 165 and r7, r8, #15 << 12
diff --git a/arch/arm/mm/abort-nommu.S b/arch/arm/mm/abort-nommu.S
index 625e580945b5..9eaef6f846c3 100644
--- a/arch/arm/mm/abort-nommu.S
+++ b/arch/arm/mm/abort-nommu.S
@@ -3,8 +3,8 @@
3/* 3/*
4 * Function: nommu_early_abort 4 * Function: nommu_early_abort
5 * 5 *
6 * Params : r2 = address of aborted instruction 6 * Params : r4 = aborted context pc
7 * : r3 = saved SPSR 7 * : r5 = aborted context psr
8 * 8 *
9 * Returns : r0 = 0 (abort address) 9 * Returns : r0 = 0 (abort address)
10 * : r1 = 0 (FSR) 10 * : r1 = 0 (FSR)
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 5f79dc4ce3fb..e7be700db08c 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -29,8 +29,8 @@ ENTRY(cpu_arm7_dcache_clean_area)
29/* 29/*
30 * Function: arm6_7_data_abort () 30 * Function: arm6_7_data_abort ()
31 * 31 *
32 * Params : r2 = address of aborted instruction 32 * Params : r4 = aborted context pc
33 * : sp = pointer to registers 33 * : r5 = aborted context psr
34 * 34 *
35 * Purpose : obtain information about current aborted instruction 35 * Purpose : obtain information about current aborted instruction
36 * 36 *
@@ -41,7 +41,7 @@ ENTRY(cpu_arm7_dcache_clean_area)
41ENTRY(cpu_arm7_data_abort) 41ENTRY(cpu_arm7_data_abort)
42 mrc p15, 0, r1, c5, c0, 0 @ get FSR 42 mrc p15, 0, r1, c5, c0, 0 @ get FSR
43 mrc p15, 0, r0, c6, c0, 0 @ get FAR 43 mrc p15, 0, r0, c6, c0, 0 @ get FAR
44 ldr r8, [r2] @ read arm instruction 44 ldr r8, [r4] @ read arm instruction
45 tst r8, #1 << 20 @ L = 0 -> write? 45 tst r8, #1 << 20 @ L = 0 -> write?
46 orreq r1, r1, #1 << 11 @ yes. 46 orreq r1, r1, #1 << 11 @ yes.
47 and r7, r8, #15 << 24 47 and r7, r8, #15 << 24
@@ -65,7 +65,7 @@ ENTRY(cpu_arm7_data_abort)
65/* e */ b .data_unknown 65/* e */ b .data_unknown
66/* f */ 66/* f */
67.data_unknown: @ Part of jumptable 67.data_unknown: @ Part of jumptable
68 mov r0, r2 68 mov r0, r4
69 mov r1, r8 69 mov r1, r8
70 mov r2, sp 70 mov r2, sp
71 bl baddataabort 71 bl baddataabort
@@ -74,7 +74,7 @@ ENTRY(cpu_arm7_data_abort)
74ENTRY(cpu_arm6_data_abort) 74ENTRY(cpu_arm6_data_abort)
75 mrc p15, 0, r1, c5, c0, 0 @ get FSR 75 mrc p15, 0, r1, c5, c0, 0 @ get FSR
76 mrc p15, 0, r0, c6, c0, 0 @ get FAR 76 mrc p15, 0, r0, c6, c0, 0 @ get FAR
77 ldr r8, [r2] @ read arm instruction 77 ldr r8, [r4] @ read arm instruction
78 tst r8, #1 << 20 @ L = 0 -> write? 78 tst r8, #1 << 20 @ L = 0 -> write?
79 orreq r1, r1, #1 << 11 @ yes. 79 orreq r1, r1, #1 << 11 @ yes.
80 and r7, r8, #14 << 24 80 and r7, r8, #14 << 24
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-07 17:36:29 -0500