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-rw-r--r--arch/arm/mach-sunxi/common.h19
-rw-r--r--arch/arm/mach-sunxi/platsmp.c2
-rw-r--r--arch/arm/mach-sunxi/sunxi.c3
3 files changed, 0 insertions, 24 deletions
diff --git a/arch/arm/mach-sunxi/common.h b/arch/arm/mach-sunxi/common.h
deleted file mode 100644
index 9e5ac4756cbb..000000000000
--- a/arch/arm/mach-sunxi/common.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * Core functions for Allwinner SoCs
3 *
4 * Copyright (C) 2013 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#ifndef __ARCH_SUNXI_COMMON_H_
14#define __ARCH_SUNXI_COMMON_H_
15
16void sun6i_secondary_startup(void);
17extern struct smp_operations sun6i_smp_ops;
18
19#endif /* __ARCH_SUNXI_COMMON_H_ */
diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
index 828f21126973..c53077bb8c3f 100644
--- a/arch/arm/mach-sunxi/platsmp.c
+++ b/arch/arm/mach-sunxi/platsmp.c
@@ -21,8 +21,6 @@
21#include <linux/of_address.h> 21#include <linux/of_address.h>
22#include <linux/smp.h> 22#include <linux/smp.h>
23 23
24#include "common.h"
25
26#define CPUCFG_CPU_PWR_CLAMP_STATUS_REG(cpu) ((cpu) * 0x40 + 0x64) 24#define CPUCFG_CPU_PWR_CLAMP_STATUS_REG(cpu) ((cpu) * 0x40 + 0x64)
27#define CPUCFG_CPU_RST_CTRL_REG(cpu) (((cpu) + 1) * 0x40) 25#define CPUCFG_CPU_RST_CTRL_REG(cpu) (((cpu) + 1) * 0x40)
28#define CPUCFG_CPU_CTRL_REG(cpu) (((cpu) + 1) * 0x40 + 0x04) 26#define CPUCFG_CPU_CTRL_REG(cpu) (((cpu) + 1) * 0x40 + 0x04)
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 460b5a4962ef..df906e3a8f91 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -25,8 +25,6 @@
25#include <asm/mach/map.h> 25#include <asm/mach/map.h>
26#include <asm/system_misc.h> 26#include <asm/system_misc.h>
27 27
28#include "common.h"
29
30#define SUN4I_WATCHDOG_CTRL_REG 0x00 28#define SUN4I_WATCHDOG_CTRL_REG 0x00
31#define SUN4I_WATCHDOG_CTRL_RESTART BIT(0) 29#define SUN4I_WATCHDOG_CTRL_RESTART BIT(0)
32#define SUN4I_WATCHDOG_MODE_REG 0x04 30#define SUN4I_WATCHDOG_MODE_REG 0x04
@@ -149,7 +147,6 @@ DT_MACHINE_START(SUN6I_DT, "Allwinner sun6i (A31) Family")
149 .init_time = sun6i_timer_init, 147 .init_time = sun6i_timer_init,
150 .dt_compat = sun6i_board_dt_compat, 148 .dt_compat = sun6i_board_dt_compat,
151 .restart = sun6i_restart, 149 .restart = sun6i_restart,
152 .smp = smp_ops(sun6i_smp_ops),
153MACHINE_END 150MACHINE_END
154 151
155static const char * const sun7i_board_dt_compat[] = { 152static const char * const sun7i_board_dt_compat[] = {