diff options
Diffstat (limited to 'arch/arm')
154 files changed, 3755 insertions, 5282 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 52f1027d9cb1..bd220b85c550 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
| @@ -397,6 +397,7 @@ config ARCH_MXC | |||
| 397 | select CLKSRC_MMIO | 397 | select CLKSRC_MMIO |
| 398 | select GENERIC_IRQ_CHIP | 398 | select GENERIC_IRQ_CHIP |
| 399 | select HAVE_SCHED_CLOCK | 399 | select HAVE_SCHED_CLOCK |
| 400 | select MULTI_IRQ_HANDLER | ||
| 400 | help | 401 | help |
| 401 | Support for Freescale MXC/iMX-based family of processors | 402 | Support for Freescale MXC/iMX-based family of processors |
| 402 | 403 | ||
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 70c424eaf7b0..9260c293405c 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile | |||
| @@ -154,9 +154,7 @@ machine-$(CONFIG_ARCH_LPC32XX) := lpc32xx | |||
| 154 | machine-$(CONFIG_ARCH_MMP) := mmp | 154 | machine-$(CONFIG_ARCH_MMP) := mmp |
| 155 | machine-$(CONFIG_ARCH_MSM) := msm | 155 | machine-$(CONFIG_ARCH_MSM) := msm |
| 156 | machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 | 156 | machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 |
| 157 | machine-$(CONFIG_ARCH_MX1) := imx | 157 | machine-$(CONFIG_ARCH_IMX_V4_V5) := imx |
| 158 | machine-$(CONFIG_ARCH_MX2) := imx | ||
| 159 | machine-$(CONFIG_ARCH_MX25) := imx | ||
| 160 | machine-$(CONFIG_ARCH_MX3) := imx | 158 | machine-$(CONFIG_ARCH_MX3) := imx |
| 161 | machine-$(CONFIG_ARCH_MX5) := mx5 | 159 | machine-$(CONFIG_ARCH_MX5) := mx5 |
| 162 | machine-$(CONFIG_ARCH_MXS) := mxs | 160 | machine-$(CONFIG_ARCH_MXS) := mxs |
diff --git a/arch/arm/boot/dts/prima2-cb.dts b/arch/arm/boot/dts/prima2-cb.dts index 6fecc88065b2..17b6737c4ee5 100644 --- a/arch/arm/boot/dts/prima2-cb.dts +++ b/arch/arm/boot/dts/prima2-cb.dts | |||
| @@ -67,6 +67,11 @@ | |||
| 67 | compatible = "sirf,prima2-rstc"; | 67 | compatible = "sirf,prima2-rstc"; |
| 68 | reg = <0x88010000 0x1000>; | 68 | reg = <0x88010000 0x1000>; |
| 69 | }; | 69 | }; |
| 70 | |||
| 71 | rsc-controller@88020000 { | ||
| 72 | compatible = "sirf,prima2-rsc"; | ||
| 73 | reg = <0x88020000 0x1000>; | ||
| 74 | }; | ||
| 70 | }; | 75 | }; |
| 71 | 76 | ||
| 72 | mem-iobg { | 77 | mem-iobg { |
| @@ -274,7 +279,7 @@ | |||
| 274 | gpio: gpio-controller@b0120000 { | 279 | gpio: gpio-controller@b0120000 { |
| 275 | #gpio-cells = <2>; | 280 | #gpio-cells = <2>; |
| 276 | #interrupt-cells = <2>; | 281 | #interrupt-cells = <2>; |
| 277 | compatible = "sirf,prima2-gpio"; | 282 | compatible = "sirf,prima2-gpio-pinmux"; |
| 278 | reg = <0xb0120000 0x10000>; | 283 | reg = <0xb0120000 0x10000>; |
| 279 | gpio-controller; | 284 | gpio-controller; |
| 280 | interrupt-controller; | 285 | interrupt-controller; |
| @@ -358,7 +363,7 @@ | |||
| 358 | }; | 363 | }; |
| 359 | 364 | ||
| 360 | rtc-iobg { | 365 | rtc-iobg { |
| 361 | compatible = "sirf,prima2-rtciobg", "simple-bus"; | 366 | compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus"; |
| 362 | #address-cells = <1>; | 367 | #address-cells = <1>; |
| 363 | #size-cells = <1>; | 368 | #size-cells = <1>; |
| 364 | reg = <0x80030000 0x10000>; | 369 | reg = <0x80030000 0x10000>; |
diff --git a/arch/arm/configs/mx27_defconfig b/arch/arm/configs/imx_v4_v5_defconfig index 9ad4c656c9bd..11a4192197c8 100644 --- a/arch/arm/configs/mx27_defconfig +++ b/arch/arm/configs/imx_v4_v5_defconfig | |||
| @@ -3,9 +3,7 @@ CONFIG_EXPERIMENTAL=y | |||
| 3 | CONFIG_SYSVIPC=y | 3 | CONFIG_SYSVIPC=y |
| 4 | CONFIG_POSIX_MQUEUE=y | 4 | CONFIG_POSIX_MQUEUE=y |
| 5 | CONFIG_LOG_BUF_SHIFT=14 | 5 | CONFIG_LOG_BUF_SHIFT=14 |
| 6 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | ||
| 7 | CONFIG_EXPERT=y | 6 | CONFIG_EXPERT=y |
| 8 | CONFIG_KALLSYMS_EXTRA_PASS=y | ||
| 9 | # CONFIG_COMPAT_BRK is not set | 7 | # CONFIG_COMPAT_BRK is not set |
| 10 | CONFIG_SLAB=y | 8 | CONFIG_SLAB=y |
| 11 | CONFIG_PROFILING=y | 9 | CONFIG_PROFILING=y |
| @@ -17,8 +15,12 @@ CONFIG_MODULE_UNLOAD=y | |||
| 17 | # CONFIG_IOSCHED_DEADLINE is not set | 15 | # CONFIG_IOSCHED_DEADLINE is not set |
| 18 | # CONFIG_IOSCHED_CFQ is not set | 16 | # CONFIG_IOSCHED_CFQ is not set |
| 19 | CONFIG_ARCH_MXC=y | 17 | CONFIG_ARCH_MXC=y |
| 20 | CONFIG_ARCH_MX2=y | 18 | CONFIG_ARCH_IMX_V4_V5=y |
| 21 | CONFIG_MACH_MX27=y | 19 | CONFIG_ARCH_MX1ADS=y |
| 20 | CONFIG_MACH_SCB9328=y | ||
| 21 | CONFIG_MACH_MX21ADS=y | ||
| 22 | CONFIG_MACH_MX25_3DS=y | ||
| 23 | CONFIG_MACH_EUKREA_CPUIMX25=y | ||
| 22 | CONFIG_MACH_MX27ADS=y | 24 | CONFIG_MACH_MX27ADS=y |
| 23 | CONFIG_MACH_PCM038=y | 25 | CONFIG_MACH_PCM038=y |
| 24 | CONFIG_MACH_CPUIMX27=y | 26 | CONFIG_MACH_CPUIMX27=y |
| @@ -29,6 +31,7 @@ CONFIG_MACH_IMX27_VISSTRIM_M10=y | |||
| 29 | CONFIG_MACH_IMX27LITE=y | 31 | CONFIG_MACH_IMX27LITE=y |
| 30 | CONFIG_MACH_PCA100=y | 32 | CONFIG_MACH_PCA100=y |
| 31 | CONFIG_MACH_MXT_TD60=y | 33 | CONFIG_MACH_MXT_TD60=y |
| 34 | CONFIG_MACH_IMX27IPCAM=y | ||
| 32 | CONFIG_MXC_IRQ_PRIOR=y | 35 | CONFIG_MXC_IRQ_PRIOR=y |
| 33 | CONFIG_MXC_PWM=y | 36 | CONFIG_MXC_PWM=y |
| 34 | CONFIG_NO_HZ=y | 37 | CONFIG_NO_HZ=y |
| @@ -39,7 +42,6 @@ CONFIG_ZBOOT_ROM_TEXT=0x0 | |||
| 39 | CONFIG_ZBOOT_ROM_BSS=0x0 | 42 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| 40 | CONFIG_FPE_NWFPE=y | 43 | CONFIG_FPE_NWFPE=y |
| 41 | CONFIG_FPE_NWFPE_XP=y | 44 | CONFIG_FPE_NWFPE_XP=y |
| 42 | CONFIG_PM=y | ||
| 43 | CONFIG_PM_DEBUG=y | 45 | CONFIG_PM_DEBUG=y |
| 44 | CONFIG_NET=y | 46 | CONFIG_NET=y |
| 45 | CONFIG_PACKET=y | 47 | CONFIG_PACKET=y |
| @@ -55,8 +57,9 @@ CONFIG_IP_PNP_DHCP=y | |||
| 55 | # CONFIG_INET_DIAG is not set | 57 | # CONFIG_INET_DIAG is not set |
| 56 | # CONFIG_IPV6 is not set | 58 | # CONFIG_IPV6 is not set |
| 57 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 59 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 60 | CONFIG_DEVTMPFS=y | ||
| 61 | CONFIG_DEVTMPFS_MOUNT=y | ||
| 58 | CONFIG_MTD=y | 62 | CONFIG_MTD=y |
| 59 | CONFIG_MTD_PARTITIONS=y | ||
| 60 | CONFIG_MTD_CMDLINE_PARTS=y | 63 | CONFIG_MTD_CMDLINE_PARTS=y |
| 61 | CONFIG_MTD_CHAR=y | 64 | CONFIG_MTD_CHAR=y |
| 62 | CONFIG_MTD_BLOCK=y | 65 | CONFIG_MTD_BLOCK=y |
| @@ -69,12 +72,15 @@ CONFIG_MTD_CFI_GEOMETRY=y | |||
| 69 | CONFIG_MTD_CFI_INTELEXT=y | 72 | CONFIG_MTD_CFI_INTELEXT=y |
| 70 | CONFIG_MTD_PHYSMAP=y | 73 | CONFIG_MTD_PHYSMAP=y |
| 71 | CONFIG_MTD_NAND=y | 74 | CONFIG_MTD_NAND=y |
| 72 | CONFIG_MTD_NAND_MXC=y | ||
| 73 | CONFIG_MTD_UBI=y | 75 | CONFIG_MTD_UBI=y |
| 76 | CONFIG_MISC_DEVICES=y | ||
| 74 | CONFIG_EEPROM_AT24=y | 77 | CONFIG_EEPROM_AT24=y |
| 78 | CONFIG_EEPROM_AT25=y | ||
| 75 | CONFIG_NETDEVICES=y | 79 | CONFIG_NETDEVICES=y |
| 76 | CONFIG_NET_ETHERNET=y | 80 | CONFIG_NET_ETHERNET=y |
| 77 | CONFIG_FEC=y | 81 | CONFIG_SMC91X=y |
| 82 | CONFIG_DM9000=y | ||
| 83 | CONFIG_SMC911X=y | ||
| 78 | # CONFIG_NETDEV_1000 is not set | 84 | # CONFIG_NETDEV_1000 is not set |
| 79 | # CONFIG_NETDEV_10000 is not set | 85 | # CONFIG_NETDEV_10000 is not set |
| 80 | # CONFIG_INPUT_MOUSEDEV is not set | 86 | # CONFIG_INPUT_MOUSEDEV is not set |
| @@ -84,10 +90,10 @@ CONFIG_INPUT_EVDEV=y | |||
| 84 | CONFIG_INPUT_TOUCHSCREEN=y | 90 | CONFIG_INPUT_TOUCHSCREEN=y |
| 85 | CONFIG_TOUCHSCREEN_ADS7846=m | 91 | CONFIG_TOUCHSCREEN_ADS7846=m |
| 86 | # CONFIG_SERIO is not set | 92 | # CONFIG_SERIO is not set |
| 93 | # CONFIG_LEGACY_PTYS is not set | ||
| 87 | CONFIG_SERIAL_8250=m | 94 | CONFIG_SERIAL_8250=m |
| 88 | CONFIG_SERIAL_IMX=y | 95 | CONFIG_SERIAL_IMX=y |
| 89 | CONFIG_SERIAL_IMX_CONSOLE=y | 96 | CONFIG_SERIAL_IMX_CONSOLE=y |
| 90 | # CONFIG_LEGACY_PTYS is not set | ||
| 91 | # CONFIG_HW_RANDOM is not set | 97 | # CONFIG_HW_RANDOM is not set |
| 92 | CONFIG_I2C=y | 98 | CONFIG_I2C=y |
| 93 | CONFIG_I2C_CHARDEV=y | 99 | CONFIG_I2C_CHARDEV=y |
| @@ -98,19 +104,56 @@ CONFIG_W1=y | |||
| 98 | CONFIG_W1_MASTER_MXC=y | 104 | CONFIG_W1_MASTER_MXC=y |
| 99 | CONFIG_W1_SLAVE_THERM=y | 105 | CONFIG_W1_SLAVE_THERM=y |
| 100 | # CONFIG_HWMON is not set | 106 | # CONFIG_HWMON is not set |
| 107 | CONFIG_WATCHDOG=y | ||
| 108 | CONFIG_IMX2_WDT=y | ||
| 109 | CONFIG_MFD_MC13XXX=y | ||
| 110 | CONFIG_REGULATOR=y | ||
| 111 | CONFIG_REGULATOR_MC13783=y | ||
| 112 | CONFIG_REGULATOR_MC13892=y | ||
| 101 | CONFIG_FB=y | 113 | CONFIG_FB=y |
| 102 | CONFIG_FB_IMX=y | 114 | CONFIG_FB_IMX=y |
| 115 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | ||
| 116 | CONFIG_LCD_CLASS_DEVICE=y | ||
| 117 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | ||
| 118 | CONFIG_BACKLIGHT_PWM=y | ||
| 103 | CONFIG_FRAMEBUFFER_CONSOLE=y | 119 | CONFIG_FRAMEBUFFER_CONSOLE=y |
| 104 | CONFIG_FONTS=y | 120 | CONFIG_FONTS=y |
| 105 | CONFIG_FONT_8x8=y | 121 | CONFIG_FONT_8x8=y |
| 106 | # CONFIG_HID_SUPPORT is not set | 122 | CONFIG_LOGO=y |
| 107 | CONFIG_USB=m | 123 | CONFIG_SOUND=y |
| 124 | CONFIG_SND=y | ||
| 125 | # CONFIG_SND_ARM is not set | ||
| 126 | # CONFIG_SND_SPI is not set | ||
| 127 | CONFIG_SND_SOC=y | ||
| 128 | CONFIG_SND_IMX_SOC=y | ||
| 129 | CONFIG_SND_SOC_MX27VIS_AIC32X4=y | ||
| 130 | CONFIG_SND_SOC_PHYCORE_AC97=y | ||
| 131 | CONFIG_SND_SOC_EUKREA_TLV320=y | ||
| 132 | CONFIG_USB_HID=m | ||
| 133 | CONFIG_USB=y | ||
| 108 | # CONFIG_USB_DEVICE_CLASS is not set | 134 | # CONFIG_USB_DEVICE_CLASS is not set |
| 135 | CONFIG_USB_EHCI_HCD=y | ||
| 136 | CONFIG_USB_EHCI_MXC=y | ||
| 109 | CONFIG_USB_ULPI=y | 137 | CONFIG_USB_ULPI=y |
| 110 | CONFIG_MMC=y | 138 | CONFIG_MMC=y |
| 111 | CONFIG_MMC_MXC=y | 139 | CONFIG_MMC_MXC=y |
| 140 | CONFIG_NEW_LEDS=y | ||
| 141 | CONFIG_LEDS_CLASS=y | ||
| 142 | CONFIG_LEDS_MC13783=y | ||
| 143 | CONFIG_LEDS_TRIGGERS=y | ||
| 144 | CONFIG_LEDS_TRIGGER_TIMER=y | ||
| 145 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
| 146 | CONFIG_LEDS_TRIGGER_BACKLIGHT=y | ||
| 147 | CONFIG_LEDS_TRIGGER_GPIO=y | ||
| 148 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=y | ||
| 112 | CONFIG_RTC_CLASS=y | 149 | CONFIG_RTC_CLASS=y |
| 113 | CONFIG_RTC_DRV_PCF8563=y | 150 | CONFIG_RTC_DRV_PCF8563=y |
| 151 | CONFIG_RTC_DRV_IMXDI=y | ||
| 152 | CONFIG_RTC_MXC=y | ||
| 153 | CONFIG_DMADEVICES=y | ||
| 154 | CONFIG_IMX_SDMA=y | ||
| 155 | CONFIG_IMX_DMA=y | ||
| 156 | # CONFIG_IOMMU_SUPPORT is not set | ||
| 114 | # CONFIG_DNOTIFY is not set | 157 | # CONFIG_DNOTIFY is not set |
| 115 | # CONFIG_PROC_PAGE_MONITOR is not set | 158 | # CONFIG_PROC_PAGE_MONITOR is not set |
| 116 | CONFIG_TMPFS=y | 159 | CONFIG_TMPFS=y |
| @@ -119,12 +162,9 @@ CONFIG_UBIFS_FS=y | |||
| 119 | CONFIG_NFS_FS=y | 162 | CONFIG_NFS_FS=y |
| 120 | CONFIG_NFS_V3=y | 163 | CONFIG_NFS_V3=y |
| 121 | CONFIG_ROOT_NFS=y | 164 | CONFIG_ROOT_NFS=y |
| 122 | CONFIG_NLS=y | ||
| 123 | CONFIG_NLS_CODEPAGE_437=m | 165 | CONFIG_NLS_CODEPAGE_437=m |
| 124 | CONFIG_NLS_CODEPAGE_850=m | 166 | CONFIG_NLS_CODEPAGE_850=m |
| 125 | CONFIG_NLS_ISO8859_1=y | 167 | CONFIG_NLS_ISO8859_1=y |
| 126 | CONFIG_NLS_ISO8859_15=m | 168 | CONFIG_NLS_ISO8859_15=m |
| 127 | CONFIG_DEBUG_FS=y | ||
| 128 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 129 | CONFIG_SYSCTL_SYSCALL_CHECK=y | 169 | CONFIG_SYSCTL_SYSCALL_CHECK=y |
| 130 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | 170 | # CONFIG_CRYPTO_ANSI_CPRNG is not set |
diff --git a/arch/arm/configs/mx1_defconfig b/arch/arm/configs/mx1_defconfig deleted file mode 100644 index c9436d0bf593..000000000000 --- a/arch/arm/configs/mx1_defconfig +++ /dev/null | |||
| @@ -1,91 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | CONFIG_SYSVIPC=y | ||
| 3 | CONFIG_IKCONFIG=y | ||
| 4 | CONFIG_IKCONFIG_PROC=y | ||
| 5 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 6 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 7 | CONFIG_EXPERT=y | ||
| 8 | CONFIG_SLAB=y | ||
| 9 | CONFIG_MODULES=y | ||
| 10 | CONFIG_MODULE_UNLOAD=y | ||
| 11 | CONFIG_MODULE_FORCE_UNLOAD=y | ||
| 12 | CONFIG_MODVERSIONS=y | ||
| 13 | # CONFIG_BLK_DEV_BSG is not set | ||
| 14 | CONFIG_ARCH_MXC=y | ||
| 15 | CONFIG_ARCH_MX1=y | ||
| 16 | CONFIG_ARCH_MX1ADS=y | ||
| 17 | CONFIG_MACH_SCB9328=y | ||
| 18 | CONFIG_MACH_APF9328=y | ||
| 19 | CONFIG_MXC_IRQ_PRIOR=y | ||
| 20 | CONFIG_NO_HZ=y | ||
| 21 | CONFIG_HIGH_RES_TIMERS=y | ||
| 22 | CONFIG_PREEMPT=y | ||
| 23 | CONFIG_AEABI=y | ||
| 24 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 25 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 26 | CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw ip=off" | ||
| 27 | CONFIG_PM=y | ||
| 28 | CONFIG_PM_DEBUG=y | ||
| 29 | CONFIG_NET=y | ||
| 30 | CONFIG_PACKET=y | ||
| 31 | CONFIG_UNIX=y | ||
| 32 | CONFIG_INET=y | ||
| 33 | CONFIG_IP_PNP=y | ||
| 34 | CONFIG_IP_PNP_DHCP=y | ||
| 35 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | ||
| 36 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | ||
| 37 | # CONFIG_INET_XFRM_MODE_BEET is not set | ||
| 38 | # CONFIG_INET_LRO is not set | ||
| 39 | # CONFIG_INET_DIAG is not set | ||
| 40 | # CONFIG_IPV6 is not set | ||
| 41 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 42 | CONFIG_FW_LOADER=m | ||
| 43 | CONFIG_MTD=y | ||
| 44 | CONFIG_MTD_PARTITIONS=y | ||
| 45 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 46 | CONFIG_MTD_CHAR=y | ||
| 47 | CONFIG_MTD_BLOCK=y | ||
| 48 | CONFIG_MTD_CFI=y | ||
| 49 | CONFIG_MTD_PHYSMAP=y | ||
| 50 | # CONFIG_BLK_DEV is not set | ||
| 51 | # CONFIG_MISC_DEVICES is not set | ||
| 52 | CONFIG_NETDEVICES=y | ||
| 53 | CONFIG_PHYLIB=y | ||
| 54 | CONFIG_SMSC_PHY=y | ||
| 55 | CONFIG_NET_ETHERNET=y | ||
| 56 | CONFIG_DM9000=y | ||
| 57 | # CONFIG_NETDEV_1000 is not set | ||
| 58 | # CONFIG_NETDEV_10000 is not set | ||
| 59 | # CONFIG_INPUT is not set | ||
| 60 | # CONFIG_SERIO is not set | ||
| 61 | # CONFIG_VT is not set | ||
| 62 | CONFIG_SERIAL_IMX=y | ||
| 63 | CONFIG_SERIAL_IMX_CONSOLE=y | ||
| 64 | # CONFIG_LEGACY_PTYS is not set | ||
| 65 | # CONFIG_HW_RANDOM is not set | ||
| 66 | CONFIG_I2C=y | ||
| 67 | CONFIG_I2C_CHARDEV=y | ||
| 68 | CONFIG_I2C_IMX=y | ||
| 69 | CONFIG_W1=y | ||
| 70 | CONFIG_W1_MASTER_MXC=y | ||
| 71 | CONFIG_W1_SLAVE_THERM=y | ||
| 72 | # CONFIG_HWMON is not set | ||
| 73 | CONFIG_FB=y | ||
| 74 | CONFIG_USB_GADGET=y | ||
| 75 | CONFIG_USB_GADGET_IMX=y | ||
| 76 | CONFIG_USB_ETH=m | ||
| 77 | CONFIG_MMC=y | ||
| 78 | CONFIG_MMC_MXC=y | ||
| 79 | # CONFIG_DNOTIFY is not set | ||
| 80 | CONFIG_INOTIFY=y | ||
| 81 | CONFIG_TMPFS=y | ||
| 82 | CONFIG_JFFS2_FS=y | ||
| 83 | CONFIG_NFS_FS=y | ||
| 84 | CONFIG_NFS_V3=y | ||
| 85 | CONFIG_NFS_V4=y | ||
| 86 | CONFIG_ROOT_NFS=y | ||
| 87 | # CONFIG_ENABLE_WARN_DEPRECATED is not set | ||
| 88 | # CONFIG_ENABLE_MUST_CHECK is not set | ||
| 89 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 90 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
| 91 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
diff --git a/arch/arm/configs/mx21_defconfig b/arch/arm/configs/mx21_defconfig deleted file mode 100644 index 411f88dd4402..000000000000 --- a/arch/arm/configs/mx21_defconfig +++ /dev/null | |||
| @@ -1,97 +0,0 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | ||
| 2 | # CONFIG_SWAP is not set | ||
| 3 | CONFIG_SYSVIPC=y | ||
| 4 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 5 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 6 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | ||
| 7 | CONFIG_EXPERT=y | ||
| 8 | CONFIG_KALLSYMS_EXTRA_PASS=y | ||
| 9 | CONFIG_SLAB=y | ||
| 10 | CONFIG_MODULES=y | ||
| 11 | CONFIG_MODULE_UNLOAD=y | ||
| 12 | # CONFIG_BLK_DEV_BSG is not set | ||
| 13 | # CONFIG_IOSCHED_DEADLINE is not set | ||
| 14 | # CONFIG_IOSCHED_CFQ is not set | ||
| 15 | CONFIG_ARCH_MXC=y | ||
| 16 | CONFIG_ARCH_MX2=y | ||
| 17 | CONFIG_MACH_MX21ADS=y | ||
| 18 | CONFIG_MXC_PWM=y | ||
| 19 | CONFIG_NO_HZ=y | ||
| 20 | CONFIG_HIGH_RES_TIMERS=y | ||
| 21 | CONFIG_PREEMPT=y | ||
| 22 | CONFIG_AEABI=y | ||
| 23 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 24 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 25 | CONFIG_NET=y | ||
| 26 | CONFIG_INET=y | ||
| 27 | CONFIG_IP_PNP=y | ||
| 28 | CONFIG_IP_PNP_DHCP=y | ||
| 29 | CONFIG_IP_PNP_BOOTP=y | ||
| 30 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | ||
| 31 | # CONFIG_INET_XFRM_MODE_BEET is not set | ||
| 32 | # CONFIG_INET_LRO is not set | ||
| 33 | # CONFIG_INET_DIAG is not set | ||
| 34 | # CONFIG_IPV6 is not set | ||
| 35 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 36 | # CONFIG_FW_LOADER is not set | ||
| 37 | CONFIG_MTD=y | ||
| 38 | CONFIG_MTD_DEBUG=y | ||
| 39 | CONFIG_MTD_DEBUG_VERBOSE=3 | ||
| 40 | CONFIG_MTD_PARTITIONS=y | ||
| 41 | CONFIG_MTD_REDBOOT_PARTS=y | ||
| 42 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 43 | CONFIG_MTD_CHAR=y | ||
| 44 | CONFIG_MTD_BLOCK=y | ||
| 45 | CONFIG_MTD_CFI=y | ||
| 46 | CONFIG_MTD_CFI_ADV_OPTIONS=y | ||
| 47 | CONFIG_MTD_CFI_GEOMETRY=y | ||
| 48 | # CONFIG_MTD_MAP_BANK_WIDTH_1 is not set | ||
| 49 | CONFIG_MTD_CFI_AMDSTD=y | ||
| 50 | CONFIG_MTD_PHYSMAP=y | ||
| 51 | CONFIG_MTD_NAND=y | ||
| 52 | CONFIG_MTD_NAND_MXC=y | ||
| 53 | CONFIG_NETDEVICES=y | ||
| 54 | CONFIG_NET_ETHERNET=y | ||
| 55 | CONFIG_MII=y | ||
| 56 | # CONFIG_NETDEV_1000 is not set | ||
| 57 | # CONFIG_NETDEV_10000 is not set | ||
| 58 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 59 | CONFIG_INPUT_EVDEV=y | ||
| 60 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 61 | # CONFIG_INPUT_MOUSE is not set | ||
| 62 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 63 | # CONFIG_SERIO is not set | ||
| 64 | # CONFIG_CONSOLE_TRANSLATIONS is not set | ||
| 65 | CONFIG_SERIAL_8250=y | ||
| 66 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 67 | CONFIG_SERIAL_8250_NR_UARTS=1 | ||
| 68 | CONFIG_SERIAL_IMX=y | ||
| 69 | CONFIG_SERIAL_IMX_CONSOLE=y | ||
| 70 | # CONFIG_LEGACY_PTYS is not set | ||
| 71 | # CONFIG_HW_RANDOM is not set | ||
| 72 | CONFIG_I2C=y | ||
| 73 | CONFIG_I2C_CHARDEV=y | ||
| 74 | CONFIG_I2C_IMX=y | ||
| 75 | CONFIG_SPI=y | ||
| 76 | # CONFIG_HWMON is not set | ||
| 77 | CONFIG_FB=y | ||
| 78 | CONFIG_FB_IMX=y | ||
| 79 | # CONFIG_VGA_CONSOLE is not set | ||
| 80 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 81 | CONFIG_FONTS=y | ||
| 82 | CONFIG_FONT_8x8=y | ||
| 83 | CONFIG_LOGO=y | ||
| 84 | # CONFIG_HID_SUPPORT is not set | ||
| 85 | # CONFIG_USB_SUPPORT is not set | ||
| 86 | CONFIG_MMC=y | ||
| 87 | CONFIG_MMC_MXC=y | ||
| 88 | # CONFIG_DNOTIFY is not set | ||
| 89 | CONFIG_MSDOS_FS=y | ||
| 90 | CONFIG_TMPFS=y | ||
| 91 | CONFIG_JFFS2_FS=y | ||
| 92 | CONFIG_NFS_FS=y | ||
| 93 | CONFIG_NFS_V3=y | ||
| 94 | CONFIG_ROOT_NFS=y | ||
| 95 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 96 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
| 97 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
diff --git a/arch/arm/configs/mx51_defconfig b/arch/arm/configs/mx5_defconfig index 88c5802a2351..d0d8dfece37e 100644 --- a/arch/arm/configs/mx51_defconfig +++ b/arch/arm/configs/mx5_defconfig | |||
| @@ -1,5 +1,6 @@ | |||
| 1 | CONFIG_EXPERIMENTAL=y | 1 | CONFIG_EXPERIMENTAL=y |
| 2 | # CONFIG_LOCALVERSION_AUTO is not set | 2 | # CONFIG_LOCALVERSION_AUTO is not set |
| 3 | CONFIG_KERNEL_LZO=y | ||
| 3 | CONFIG_SYSVIPC=y | 4 | CONFIG_SYSVIPC=y |
| 4 | CONFIG_LOG_BUF_SHIFT=18 | 5 | CONFIG_LOG_BUF_SHIFT=18 |
| 5 | CONFIG_RELAY=y | 6 | CONFIG_RELAY=y |
| @@ -13,21 +14,29 @@ CONFIG_MODULE_SRCVERSION_ALL=y | |||
| 13 | # CONFIG_LBDAF is not set | 14 | # CONFIG_LBDAF is not set |
| 14 | # CONFIG_BLK_DEV_BSG is not set | 15 | # CONFIG_BLK_DEV_BSG is not set |
| 15 | CONFIG_ARCH_MXC=y | 16 | CONFIG_ARCH_MXC=y |
| 16 | CONFIG_ARCH_MX51=y | 17 | CONFIG_ARCH_MX5=y |
| 17 | CONFIG_MACH_MX51_BABBAGE=y | 18 | CONFIG_MACH_MX51_BABBAGE=y |
| 18 | CONFIG_MACH_MX51_3DS=y | 19 | CONFIG_MACH_MX51_3DS=y |
| 19 | CONFIG_MACH_EUKREA_CPUIMX51=y | 20 | CONFIG_MACH_EUKREA_CPUIMX51=y |
| 21 | CONFIG_MACH_EUKREA_CPUIMX51SD=y | ||
| 22 | CONFIG_MACH_MX51_EFIKAMX=y | ||
| 23 | CONFIG_MACH_MX51_EFIKASB=y | ||
| 24 | CONFIG_MACH_MX53_EVK=y | ||
| 25 | CONFIG_MACH_MX53_SMD=y | ||
| 26 | CONFIG_MACH_MX53_LOCO=y | ||
| 27 | CONFIG_MACH_MX53_ARD=y | ||
| 28 | CONFIG_MXC_PWM=y | ||
| 20 | CONFIG_NO_HZ=y | 29 | CONFIG_NO_HZ=y |
| 21 | CONFIG_HIGH_RES_TIMERS=y | 30 | CONFIG_HIGH_RES_TIMERS=y |
| 31 | CONFIG_VMSPLIT_2G=y | ||
| 22 | CONFIG_PREEMPT_VOLUNTARY=y | 32 | CONFIG_PREEMPT_VOLUNTARY=y |
| 23 | CONFIG_AEABI=y | 33 | CONFIG_AEABI=y |
| 24 | # CONFIG_OABI_COMPAT is not set | 34 | # CONFIG_OABI_COMPAT is not set |
| 25 | CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 | 35 | CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 |
| 26 | CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/nfs nfsroot=192.168.0.101:/shared/nfs ip=dhcp" | 36 | CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" |
| 27 | CONFIG_VFP=y | 37 | CONFIG_VFP=y |
| 28 | CONFIG_NEON=y | 38 | CONFIG_NEON=y |
| 29 | CONFIG_BINFMT_MISC=m | 39 | CONFIG_BINFMT_MISC=m |
| 30 | CONFIG_PM=y | ||
| 31 | CONFIG_PM_DEBUG=y | 40 | CONFIG_PM_DEBUG=y |
| 32 | CONFIG_PM_TEST_SUSPEND=y | 41 | CONFIG_PM_TEST_SUSPEND=y |
| 33 | CONFIG_NET=y | 42 | CONFIG_NET=y |
| @@ -42,13 +51,13 @@ CONFIG_IP_PNP_DHCP=y | |||
| 42 | # CONFIG_INET_LRO is not set | 51 | # CONFIG_INET_LRO is not set |
| 43 | # CONFIG_IPV6 is not set | 52 | # CONFIG_IPV6 is not set |
| 44 | # CONFIG_WIRELESS is not set | 53 | # CONFIG_WIRELESS is not set |
| 54 | CONFIG_DEVTMPFS=y | ||
| 55 | CONFIG_DEVTMPFS_MOUNT=y | ||
| 45 | # CONFIG_STANDALONE is not set | 56 | # CONFIG_STANDALONE is not set |
| 46 | CONFIG_CONNECTOR=y | 57 | CONFIG_CONNECTOR=y |
| 47 | CONFIG_BLK_DEV_LOOP=y | 58 | CONFIG_BLK_DEV_LOOP=y |
| 48 | CONFIG_BLK_DEV_RAM=y | 59 | CONFIG_BLK_DEV_RAM=y |
| 49 | CONFIG_BLK_DEV_RAM_SIZE=65536 | 60 | CONFIG_BLK_DEV_RAM_SIZE=65536 |
| 50 | # CONFIG_MISC_DEVICES is not set | ||
| 51 | CONFIG_SCSI=y | ||
| 52 | # CONFIG_SCSI_PROC_FS is not set | 61 | # CONFIG_SCSI_PROC_FS is not set |
| 53 | CONFIG_BLK_DEV_SD=y | 62 | CONFIG_BLK_DEV_SD=y |
| 54 | CONFIG_SCSI_MULTI_LUN=y | 63 | CONFIG_SCSI_MULTI_LUN=y |
| @@ -56,8 +65,10 @@ CONFIG_SCSI_CONSTANTS=y | |||
| 56 | CONFIG_SCSI_LOGGING=y | 65 | CONFIG_SCSI_LOGGING=y |
| 57 | CONFIG_SCSI_SCAN_ASYNC=y | 66 | CONFIG_SCSI_SCAN_ASYNC=y |
| 58 | # CONFIG_SCSI_LOWLEVEL is not set | 67 | # CONFIG_SCSI_LOWLEVEL is not set |
| 59 | CONFIG_ATA=m | 68 | CONFIG_ATA=y |
| 69 | CONFIG_PATA_IMX=y | ||
| 60 | CONFIG_NETDEVICES=y | 70 | CONFIG_NETDEVICES=y |
| 71 | CONFIG_MII=m | ||
| 61 | CONFIG_MARVELL_PHY=y | 72 | CONFIG_MARVELL_PHY=y |
| 62 | CONFIG_DAVICOM_PHY=y | 73 | CONFIG_DAVICOM_PHY=y |
| 63 | CONFIG_QSEMI_PHY=y | 74 | CONFIG_QSEMI_PHY=y |
| @@ -71,49 +82,57 @@ CONFIG_REALTEK_PHY=y | |||
| 71 | CONFIG_NATIONAL_PHY=y | 82 | CONFIG_NATIONAL_PHY=y |
| 72 | CONFIG_STE10XP=y | 83 | CONFIG_STE10XP=y |
| 73 | CONFIG_LSI_ET1011C_PHY=y | 84 | CONFIG_LSI_ET1011C_PHY=y |
| 74 | CONFIG_MDIO_BITBANG=y | 85 | CONFIG_MICREL_PHY=y |
| 75 | CONFIG_MDIO_GPIO=y | ||
| 76 | CONFIG_NET_ETHERNET=y | 86 | CONFIG_NET_ETHERNET=y |
| 77 | CONFIG_MII=m | ||
| 78 | CONFIG_FEC=y | ||
| 79 | # CONFIG_NETDEV_1000 is not set | 87 | # CONFIG_NETDEV_1000 is not set |
| 80 | # CONFIG_NETDEV_10000 is not set | 88 | # CONFIG_NETDEV_10000 is not set |
| 81 | # CONFIG_WLAN is not set | 89 | # CONFIG_WLAN is not set |
| 82 | CONFIG_INPUT_FF_MEMLESS=m | ||
| 83 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | 90 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set |
| 84 | CONFIG_INPUT_EVDEV=y | 91 | CONFIG_INPUT_EVDEV=y |
| 85 | CONFIG_KEYBOARD_GPIO=y | ||
| 86 | CONFIG_INPUT_EVBUG=m | 92 | CONFIG_INPUT_EVBUG=m |
| 93 | CONFIG_KEYBOARD_GPIO=y | ||
| 87 | CONFIG_MOUSE_PS2=m | 94 | CONFIG_MOUSE_PS2=m |
| 88 | CONFIG_MOUSE_PS2_ELANTECH=y | 95 | CONFIG_MOUSE_PS2_ELANTECH=y |
| 96 | CONFIG_INPUT_MISC=y | ||
| 97 | CONFIG_INPUT_MMA8450=y | ||
| 89 | CONFIG_SERIO_SERPORT=m | 98 | CONFIG_SERIO_SERPORT=m |
| 90 | CONFIG_VT_HW_CONSOLE_BINDING=y | 99 | CONFIG_VT_HW_CONSOLE_BINDING=y |
| 100 | # CONFIG_LEGACY_PTYS is not set | ||
| 91 | # CONFIG_DEVKMEM is not set | 101 | # CONFIG_DEVKMEM is not set |
| 92 | CONFIG_SERIAL_IMX=y | 102 | CONFIG_SERIAL_IMX=y |
| 93 | CONFIG_SERIAL_IMX_CONSOLE=y | 103 | CONFIG_SERIAL_IMX_CONSOLE=y |
| 94 | # CONFIG_LEGACY_PTYS is not set | ||
| 95 | CONFIG_HW_RANDOM=y | 104 | CONFIG_HW_RANDOM=y |
| 96 | CONFIG_I2C=y | 105 | CONFIG_I2C=y |
| 97 | # CONFIG_I2C_COMPAT is not set | 106 | # CONFIG_I2C_COMPAT is not set |
| 98 | CONFIG_I2C_CHARDEV=m | 107 | CONFIG_I2C_CHARDEV=y |
| 99 | # CONFIG_I2C_HELPER_AUTO is not set | 108 | # CONFIG_I2C_HELPER_AUTO is not set |
| 100 | CONFIG_I2C_ALGOBIT=m | 109 | CONFIG_I2C_ALGOBIT=m |
| 101 | CONFIG_I2C_ALGOPCF=m | 110 | CONFIG_I2C_ALGOPCF=m |
| 102 | CONFIG_I2C_ALGOPCA=m | 111 | CONFIG_I2C_ALGOPCA=m |
| 112 | CONFIG_I2C_IMX=y | ||
| 113 | CONFIG_SPI=y | ||
| 114 | CONFIG_SPI_IMX=y | ||
| 103 | CONFIG_GPIO_SYSFS=y | 115 | CONFIG_GPIO_SYSFS=y |
| 104 | # CONFIG_HWMON is not set | 116 | # CONFIG_HWMON is not set |
| 105 | # CONFIG_HID_SUPPORT is not set | 117 | CONFIG_WATCHDOG=y |
| 118 | CONFIG_IMX2_WDT=y | ||
| 119 | CONFIG_MFD_MC13XXX=y | ||
| 120 | CONFIG_REGULATOR=y | ||
| 121 | CONFIG_REGULATOR_MC13892=y | ||
| 106 | CONFIG_USB=y | 122 | CONFIG_USB=y |
| 107 | CONFIG_USB_EHCI_HCD=y | 123 | CONFIG_USB_EHCI_HCD=y |
| 108 | CONFIG_USB_EHCI_MXC=y | 124 | CONFIG_USB_EHCI_MXC=y |
| 109 | CONFIG_USB_STORAGE=y | 125 | CONFIG_USB_STORAGE=y |
| 110 | CONFIG_MMC=y | 126 | CONFIG_MMC=y |
| 111 | CONFIG_MMC_BLOCK=m | 127 | CONFIG_MMC_BLOCK=m |
| 112 | CONFIG_MMC_SDHCI=m | 128 | CONFIG_MMC_SDHCI=y |
| 129 | CONFIG_MMC_SDHCI_PLTFM=y | ||
| 130 | CONFIG_MMC_SDHCI_ESDHC_IMX=y | ||
| 113 | CONFIG_NEW_LEDS=y | 131 | CONFIG_NEW_LEDS=y |
| 114 | CONFIG_LEDS_CLASS=y | 132 | CONFIG_LEDS_CLASS=y |
| 115 | CONFIG_RTC_CLASS=y | 133 | CONFIG_RTC_CLASS=y |
| 116 | CONFIG_RTC_INTF_DEV_UIE_EMUL=y | 134 | CONFIG_RTC_INTF_DEV_UIE_EMUL=y |
| 135 | CONFIG_RTC_MXC=y | ||
| 117 | CONFIG_EXT2_FS=y | 136 | CONFIG_EXT2_FS=y |
| 118 | CONFIG_EXT2_FS_XATTR=y | 137 | CONFIG_EXT2_FS_XATTR=y |
| 119 | CONFIG_EXT2_FS_POSIX_ACL=y | 138 | CONFIG_EXT2_FS_POSIX_ACL=y |
| @@ -127,7 +146,6 @@ CONFIG_EXT4_FS_SECURITY=y | |||
| 127 | CONFIG_QUOTA=y | 146 | CONFIG_QUOTA=y |
| 128 | CONFIG_QUOTA_NETLINK_INTERFACE=y | 147 | CONFIG_QUOTA_NETLINK_INTERFACE=y |
| 129 | # CONFIG_PRINT_QUOTA_WARNING is not set | 148 | # CONFIG_PRINT_QUOTA_WARNING is not set |
| 130 | CONFIG_AUTOFS_FS=y | ||
| 131 | CONFIG_AUTOFS4_FS=y | 149 | CONFIG_AUTOFS4_FS=y |
| 132 | CONFIG_FUSE_FS=y | 150 | CONFIG_FUSE_FS=y |
| 133 | CONFIG_ISO9660_FS=m | 151 | CONFIG_ISO9660_FS=m |
| @@ -151,17 +169,13 @@ CONFIG_NLS_ISO8859_15=m | |||
| 151 | CONFIG_NLS_UTF8=y | 169 | CONFIG_NLS_UTF8=y |
| 152 | CONFIG_MAGIC_SYSRQ=y | 170 | CONFIG_MAGIC_SYSRQ=y |
| 153 | CONFIG_DEBUG_FS=y | 171 | CONFIG_DEBUG_FS=y |
| 154 | CONFIG_DEBUG_KERNEL=y | ||
| 155 | # CONFIG_SCHED_DEBUG is not set | 172 | # CONFIG_SCHED_DEBUG is not set |
| 156 | # CONFIG_DEBUG_BUGVERBOSE is not set | 173 | # CONFIG_DEBUG_BUGVERBOSE is not set |
| 157 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 158 | # CONFIG_FTRACE is not set | 174 | # CONFIG_FTRACE is not set |
| 159 | # CONFIG_ARM_UNWIND is not set | 175 | # CONFIG_ARM_UNWIND is not set |
| 160 | CONFIG_DEBUG_LL=y | ||
| 161 | CONFIG_EARLY_PRINTK=y | ||
| 162 | CONFIG_SECURITYFS=y | 176 | CONFIG_SECURITYFS=y |
| 163 | CONFIG_CRYPTO_DEFLATE=y | 177 | CONFIG_CRYPTO_DEFLATE=m |
| 164 | CONFIG_CRYPTO_LZO=y | 178 | CONFIG_CRYPTO_LZO=m |
| 165 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | 179 | # CONFIG_CRYPTO_ANSI_CPRNG is not set |
| 166 | # CONFIG_CRYPTO_HW is not set | 180 | # CONFIG_CRYPTO_HW is not set |
| 167 | CONFIG_CRC_CCITT=m | 181 | CONFIG_CRC_CCITT=m |
diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c index bfc684441ef8..ecdd54dd68c6 100644 --- a/arch/arm/mach-at91/at91cap9.c +++ b/arch/arm/mach-at91/at91cap9.c | |||
| @@ -219,6 +219,8 @@ static struct clk_lookup periph_clocks_lookups[] = { | |||
| 219 | CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk), | 219 | CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk), |
| 220 | CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), | 220 | CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), |
| 221 | CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), | 221 | CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), |
| 222 | /* fake hclk clock */ | ||
| 223 | CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk), | ||
| 222 | }; | 224 | }; |
| 223 | 225 | ||
| 224 | static struct clk_lookup usart_clocks_lookups[] = { | 226 | static struct clk_lookup usart_clocks_lookups[] = { |
diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c index dba0d8d8a4bd..b46615a59355 100644 --- a/arch/arm/mach-at91/at91cap9_devices.c +++ b/arch/arm/mach-at91/at91cap9_devices.c | |||
| @@ -80,6 +80,12 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) | |||
| 80 | at91_set_gpio_output(data->vbus_pin[i], 0); | 80 | at91_set_gpio_output(data->vbus_pin[i], 0); |
| 81 | } | 81 | } |
| 82 | 82 | ||
| 83 | /* Enable overcurrent notification */ | ||
| 84 | for (i = 0; i < data->ports; i++) { | ||
| 85 | if (data->overcurrent_pin[i]) | ||
| 86 | at91_set_gpio_input(data->overcurrent_pin[i], 1); | ||
| 87 | } | ||
| 88 | |||
| 83 | usbh_data = *data; | 89 | usbh_data = *data; |
| 84 | platform_device_register(&at91_usbh_device); | 90 | platform_device_register(&at91_usbh_device); |
| 85 | } | 91 | } |
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c index f73302dbc6a5..713d3bdbd284 100644 --- a/arch/arm/mach-at91/at91rm9200.c +++ b/arch/arm/mach-at91/at91rm9200.c | |||
| @@ -193,6 +193,8 @@ static struct clk_lookup periph_clocks_lookups[] = { | |||
| 193 | CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), | 193 | CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), |
| 194 | CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), | 194 | CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), |
| 195 | CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk), | 195 | CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk), |
| 196 | /* fake hclk clock */ | ||
| 197 | CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk), | ||
| 196 | }; | 198 | }; |
| 197 | 199 | ||
| 198 | static struct clk_lookup usart_clocks_lookups[] = { | 200 | static struct clk_lookup usart_clocks_lookups[] = { |
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c index 7227755ffec6..3f2711391a69 100644 --- a/arch/arm/mach-at91/at91rm9200_devices.c +++ b/arch/arm/mach-at91/at91rm9200_devices.c | |||
| @@ -60,9 +60,17 @@ static struct platform_device at91rm9200_usbh_device = { | |||
| 60 | 60 | ||
| 61 | void __init at91_add_device_usbh(struct at91_usbh_data *data) | 61 | void __init at91_add_device_usbh(struct at91_usbh_data *data) |
| 62 | { | 62 | { |
| 63 | int i; | ||
| 64 | |||
| 63 | if (!data) | 65 | if (!data) |
| 64 | return; | 66 | return; |
| 65 | 67 | ||
| 68 | /* Enable overcurrent notification */ | ||
| 69 | for (i = 0; i < data->ports; i++) { | ||
| 70 | if (data->overcurrent_pin[i]) | ||
| 71 | at91_set_gpio_input(data->overcurrent_pin[i], 1); | ||
| 72 | } | ||
| 73 | |||
| 66 | usbh_data = *data; | 74 | usbh_data = *data; |
| 67 | platform_device_register(&at91rm9200_usbh_device); | 75 | platform_device_register(&at91rm9200_usbh_device); |
| 68 | } | 76 | } |
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c index cb397be14448..a9be75825e34 100644 --- a/arch/arm/mach-at91/at91sam9260.c +++ b/arch/arm/mach-at91/at91sam9260.c | |||
| @@ -199,6 +199,8 @@ static struct clk_lookup periph_clocks_lookups[] = { | |||
| 199 | CLKDEV_CON_DEV_ID("t4_clk", "atmel_tcb.1", &tc4_clk), | 199 | CLKDEV_CON_DEV_ID("t4_clk", "atmel_tcb.1", &tc4_clk), |
| 200 | CLKDEV_CON_DEV_ID("t5_clk", "atmel_tcb.1", &tc5_clk), | 200 | CLKDEV_CON_DEV_ID("t5_clk", "atmel_tcb.1", &tc5_clk), |
| 201 | CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk), | 201 | CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk), |
| 202 | /* fake hclk clock */ | ||
| 203 | CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk), | ||
| 202 | }; | 204 | }; |
| 203 | 205 | ||
| 204 | static struct clk_lookup usart_clocks_lookups[] = { | 206 | static struct clk_lookup usart_clocks_lookups[] = { |
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c index 39f81f47b4ba..344075fbb39e 100644 --- a/arch/arm/mach-at91/at91sam9260_devices.c +++ b/arch/arm/mach-at91/at91sam9260_devices.c | |||
| @@ -61,9 +61,17 @@ static struct platform_device at91_usbh_device = { | |||
| 61 | 61 | ||
| 62 | void __init at91_add_device_usbh(struct at91_usbh_data *data) | 62 | void __init at91_add_device_usbh(struct at91_usbh_data *data) |
| 63 | { | 63 | { |
| 64 | int i; | ||
| 65 | |||
| 64 | if (!data) | 66 | if (!data) |
| 65 | return; | 67 | return; |
| 66 | 68 | ||
| 69 | /* Enable overcurrent notification */ | ||
| 70 | for (i = 0; i < data->ports; i++) { | ||
| 71 | if (data->overcurrent_pin[i]) | ||
| 72 | at91_set_gpio_input(data->overcurrent_pin[i], 1); | ||
| 73 | } | ||
| 74 | |||
| 67 | usbh_data = *data; | 75 | usbh_data = *data; |
| 68 | platform_device_register(&at91_usbh_device); | 76 | platform_device_register(&at91_usbh_device); |
| 69 | } | 77 | } |
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c index 6c8e3b5f669f..658a5185abfd 100644 --- a/arch/arm/mach-at91/at91sam9261.c +++ b/arch/arm/mach-at91/at91sam9261.c | |||
| @@ -129,6 +129,20 @@ static struct clk lcdc_clk = { | |||
| 129 | .type = CLK_TYPE_PERIPHERAL, | 129 | .type = CLK_TYPE_PERIPHERAL, |
| 130 | }; | 130 | }; |
| 131 | 131 | ||
| 132 | /* HClocks */ | ||
| 133 | static struct clk hck0 = { | ||
| 134 | .name = "hck0", | ||
| 135 | .pmc_mask = AT91_PMC_HCK0, | ||
| 136 | .type = CLK_TYPE_SYSTEM, | ||
| 137 | .id = 0, | ||
| 138 | }; | ||
| 139 | static struct clk hck1 = { | ||
| 140 | .name = "hck1", | ||
| 141 | .pmc_mask = AT91_PMC_HCK1, | ||
| 142 | .type = CLK_TYPE_SYSTEM, | ||
| 143 | .id = 1, | ||
| 144 | }; | ||
| 145 | |||
| 132 | static struct clk *periph_clocks[] __initdata = { | 146 | static struct clk *periph_clocks[] __initdata = { |
| 133 | &pioA_clk, | 147 | &pioA_clk, |
| 134 | &pioB_clk, | 148 | &pioB_clk, |
| @@ -161,6 +175,7 @@ static struct clk_lookup periph_clocks_lookups[] = { | |||
| 161 | CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), | 175 | CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), |
| 162 | CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), | 176 | CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), |
| 163 | CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk), | 177 | CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk), |
| 178 | CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0), | ||
| 164 | }; | 179 | }; |
| 165 | 180 | ||
| 166 | static struct clk_lookup usart_clocks_lookups[] = { | 181 | static struct clk_lookup usart_clocks_lookups[] = { |
| @@ -199,20 +214,6 @@ static struct clk pck3 = { | |||
| 199 | .id = 3, | 214 | .id = 3, |
| 200 | }; | 215 | }; |
| 201 | 216 | ||
| 202 | /* HClocks */ | ||
| 203 | static struct clk hck0 = { | ||
| 204 | .name = "hck0", | ||
| 205 | .pmc_mask = AT91_PMC_HCK0, | ||
| 206 | .type = CLK_TYPE_SYSTEM, | ||
| 207 | .id = 0, | ||
| 208 | }; | ||
| 209 | static struct clk hck1 = { | ||
| 210 | .name = "hck1", | ||
| 211 | .pmc_mask = AT91_PMC_HCK1, | ||
| 212 | .type = CLK_TYPE_SYSTEM, | ||
| 213 | .id = 1, | ||
| 214 | }; | ||
| 215 | |||
| 216 | static void __init at91sam9261_register_clocks(void) | 217 | static void __init at91sam9261_register_clocks(void) |
| 217 | { | 218 | { |
| 218 | int i; | 219 | int i; |
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c index 0f917928eeb7..3b8fb79d6b10 100644 --- a/arch/arm/mach-at91/at91sam9261_devices.c +++ b/arch/arm/mach-at91/at91sam9261_devices.c | |||
| @@ -64,9 +64,17 @@ static struct platform_device at91sam9261_usbh_device = { | |||
| 64 | 64 | ||
| 65 | void __init at91_add_device_usbh(struct at91_usbh_data *data) | 65 | void __init at91_add_device_usbh(struct at91_usbh_data *data) |
| 66 | { | 66 | { |
| 67 | int i; | ||
| 68 | |||
| 67 | if (!data) | 69 | if (!data) |
| 68 | return; | 70 | return; |
| 69 | 71 | ||
| 72 | /* Enable overcurrent notification */ | ||
| 73 | for (i = 0; i < data->ports; i++) { | ||
| 74 | if (data->overcurrent_pin[i]) | ||
| 75 | at91_set_gpio_input(data->overcurrent_pin[i], 1); | ||
| 76 | } | ||
| 77 | |||
| 70 | usbh_data = *data; | 78 | usbh_data = *data; |
| 71 | platform_device_register(&at91sam9261_usbh_device); | 79 | platform_device_register(&at91sam9261_usbh_device); |
| 72 | } | 80 | } |
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c index 044f3c927e64..f83fbb0ee0c5 100644 --- a/arch/arm/mach-at91/at91sam9263.c +++ b/arch/arm/mach-at91/at91sam9263.c | |||
| @@ -189,6 +189,8 @@ static struct clk_lookup periph_clocks_lookups[] = { | |||
| 189 | CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk), | 189 | CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk), |
| 190 | CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), | 190 | CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), |
| 191 | CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk), | 191 | CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk), |
| 192 | /* fake hclk clock */ | ||
| 193 | CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk), | ||
| 192 | }; | 194 | }; |
| 193 | 195 | ||
| 194 | static struct clk_lookup usart_clocks_lookups[] = { | 196 | static struct clk_lookup usart_clocks_lookups[] = { |
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c index a050f41fc860..d4aef76a092d 100644 --- a/arch/arm/mach-at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/at91sam9263_devices.c | |||
| @@ -74,6 +74,12 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) | |||
| 74 | at91_set_gpio_output(data->vbus_pin[i], 0); | 74 | at91_set_gpio_output(data->vbus_pin[i], 0); |
| 75 | } | 75 | } |
| 76 | 76 | ||
| 77 | /* Enable overcurrent notification */ | ||
| 78 | for (i = 0; i < data->ports; i++) { | ||
| 79 | if (data->overcurrent_pin[i]) | ||
| 80 | at91_set_gpio_input(data->overcurrent_pin[i], 1); | ||
| 81 | } | ||
| 82 | |||
| 77 | usbh_data = *data; | 83 | usbh_data = *data; |
| 78 | platform_device_register(&at91_usbh_device); | 84 | platform_device_register(&at91_usbh_device); |
| 79 | } | 85 | } |
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index e04c5fb6f1ee..8f5db7b9e6ea 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c | |||
| @@ -215,6 +215,8 @@ static struct clk_lookup periph_clocks_lookups[] = { | |||
| 215 | CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk), | 215 | CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk), |
| 216 | CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), | 216 | CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), |
| 217 | CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), | 217 | CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), |
| 218 | /* fake hclk clock */ | ||
| 219 | CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk), | ||
| 218 | }; | 220 | }; |
| 219 | 221 | ||
| 220 | static struct clk_lookup usart_clocks_lookups[] = { | 222 | static struct clk_lookup usart_clocks_lookups[] = { |
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c index 600bffb01edb..e4a98574893d 100644 --- a/arch/arm/mach-at91/at91sam9g45_devices.c +++ b/arch/arm/mach-at91/at91sam9g45_devices.c | |||
| @@ -124,6 +124,12 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) | |||
| 124 | at91_set_gpio_output(data->vbus_pin[i], 0); | 124 | at91_set_gpio_output(data->vbus_pin[i], 0); |
| 125 | } | 125 | } |
| 126 | 126 | ||
| 127 | /* Enable overcurrent notification */ | ||
| 128 | for (i = 0; i < data->ports; i++) { | ||
| 129 | if (data->overcurrent_pin[i]) | ||
| 130 | at91_set_gpio_input(data->overcurrent_pin[i], 1); | ||
| 131 | } | ||
| 132 | |||
| 127 | usbh_ohci_data = *data; | 133 | usbh_ohci_data = *data; |
| 128 | platform_device_register(&at91_usbh_ohci_device); | 134 | platform_device_register(&at91_usbh_ohci_device); |
| 129 | } | 135 | } |
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h index ed544a0d5a1d..d07767f4052e 100644 --- a/arch/arm/mach-at91/include/mach/board.h +++ b/arch/arm/mach-at91/include/mach/board.h | |||
| @@ -98,6 +98,11 @@ extern void __init at91_add_device_eth(struct at91_eth_data *data); | |||
| 98 | struct at91_usbh_data { | 98 | struct at91_usbh_data { |
| 99 | u8 ports; /* number of ports on root hub */ | 99 | u8 ports; /* number of ports on root hub */ |
| 100 | u8 vbus_pin[2]; /* port power-control pin */ | 100 | u8 vbus_pin[2]; /* port power-control pin */ |
| 101 | u8 vbus_pin_inverted; | ||
| 102 | u8 overcurrent_supported; | ||
| 103 | u8 overcurrent_pin[2]; | ||
| 104 | u8 overcurrent_status[2]; | ||
| 105 | u8 overcurrent_changed[2]; | ||
| 101 | }; | 106 | }; |
| 102 | extern void __init at91_add_device_usbh(struct at91_usbh_data *data); | 107 | extern void __init at91_add_device_usbh(struct at91_usbh_data *data); |
| 103 | extern void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data); | 108 | extern void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data); |
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index c0deacae778d..32d837d8eab9 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig | |||
| @@ -192,6 +192,16 @@ config DA850_UI_RMII | |||
| 192 | 192 | ||
| 193 | endchoice | 193 | endchoice |
| 194 | 194 | ||
| 195 | config DA850_WL12XX | ||
| 196 | bool "AM18x wl1271 daughter board" | ||
| 197 | depends on MACH_DAVINCI_DA850_EVM | ||
| 198 | help | ||
| 199 | The wl1271 daughter card for AM18x EVMs is a combo wireless | ||
| 200 | connectivity add-on card, based on the LS Research TiWi module with | ||
| 201 | Texas Instruments' wl1271 solution. | ||
| 202 | Say Y if you want to use a wl1271 expansion card connected to the | ||
| 203 | AM18x EVM. | ||
| 204 | |||
| 195 | config GPIO_PCA953X | 205 | config GPIO_PCA953X |
| 196 | default MACH_DAVINCI_DA850_EVM | 206 | default MACH_DAVINCI_DA850_EVM |
| 197 | 207 | ||
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 008d51407cd7..cb7a1f0b299f 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c | |||
| @@ -31,6 +31,8 @@ | |||
| 31 | #include <linux/input/tps6507x-ts.h> | 31 | #include <linux/input/tps6507x-ts.h> |
| 32 | #include <linux/spi/spi.h> | 32 | #include <linux/spi/spi.h> |
| 33 | #include <linux/spi/flash.h> | 33 | #include <linux/spi/flash.h> |
| 34 | #include <linux/delay.h> | ||
| 35 | #include <linux/wl12xx.h> | ||
| 34 | 36 | ||
| 35 | #include <asm/mach-types.h> | 37 | #include <asm/mach-types.h> |
| 36 | #include <asm/mach/arch.h> | 38 | #include <asm/mach/arch.h> |
| @@ -49,6 +51,9 @@ | |||
| 49 | #define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0) | 51 | #define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0) |
| 50 | #define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1) | 52 | #define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1) |
| 51 | 53 | ||
| 54 | #define DA850_WLAN_EN GPIO_TO_PIN(6, 9) | ||
| 55 | #define DA850_WLAN_IRQ GPIO_TO_PIN(6, 10) | ||
| 56 | |||
| 52 | #define DA850_MII_MDIO_CLKEN_PIN GPIO_TO_PIN(2, 6) | 57 | #define DA850_MII_MDIO_CLKEN_PIN GPIO_TO_PIN(2, 6) |
| 53 | 58 | ||
| 54 | static struct mtd_partition da850evm_spiflash_part[] = { | 59 | static struct mtd_partition da850evm_spiflash_part[] = { |
| @@ -1143,6 +1148,110 @@ static __init int da850_evm_init_cpufreq(void) | |||
| 1143 | static __init int da850_evm_init_cpufreq(void) { return 0; } | 1148 | static __init int da850_evm_init_cpufreq(void) { return 0; } |
| 1144 | #endif | 1149 | #endif |
| 1145 | 1150 | ||
| 1151 | #ifdef CONFIG_DA850_WL12XX | ||
| 1152 | |||
| 1153 | static void wl12xx_set_power(int index, bool power_on) | ||
| 1154 | { | ||
| 1155 | static bool power_state; | ||
| 1156 | |||
| 1157 | pr_debug("Powering %s wl12xx", power_on ? "on" : "off"); | ||
| 1158 | |||
| 1159 | if (power_on == power_state) | ||
| 1160 | return; | ||
| 1161 | power_state = power_on; | ||
| 1162 | |||
| 1163 | if (power_on) { | ||
| 1164 | /* Power up sequence required for wl127x devices */ | ||
| 1165 | gpio_set_value(DA850_WLAN_EN, 1); | ||
| 1166 | usleep_range(15000, 15000); | ||
| 1167 | gpio_set_value(DA850_WLAN_EN, 0); | ||
| 1168 | usleep_range(1000, 1000); | ||
| 1169 | gpio_set_value(DA850_WLAN_EN, 1); | ||
| 1170 | msleep(70); | ||
| 1171 | } else { | ||
| 1172 | gpio_set_value(DA850_WLAN_EN, 0); | ||
| 1173 | } | ||
| 1174 | } | ||
| 1175 | |||
| 1176 | static struct davinci_mmc_config da850_wl12xx_mmc_config = { | ||
| 1177 | .set_power = wl12xx_set_power, | ||
| 1178 | .wires = 4, | ||
| 1179 | .max_freq = 25000000, | ||
| 1180 | .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_NONREMOVABLE | | ||
| 1181 | MMC_CAP_POWER_OFF_CARD, | ||
| 1182 | .version = MMC_CTLR_VERSION_2, | ||
| 1183 | }; | ||
| 1184 | |||
| 1185 | static const short da850_wl12xx_pins[] __initconst = { | ||
| 1186 | DA850_MMCSD1_DAT_0, DA850_MMCSD1_DAT_1, DA850_MMCSD1_DAT_2, | ||
| 1187 | DA850_MMCSD1_DAT_3, DA850_MMCSD1_CLK, DA850_MMCSD1_CMD, | ||
| 1188 | DA850_GPIO6_9, DA850_GPIO6_10, | ||
| 1189 | -1 | ||
| 1190 | }; | ||
| 1191 | |||
| 1192 | static struct wl12xx_platform_data da850_wl12xx_wlan_data __initdata = { | ||
| 1193 | .irq = -1, | ||
| 1194 | .board_ref_clock = WL12XX_REFCLOCK_38, | ||
| 1195 | .platform_quirks = WL12XX_PLATFORM_QUIRK_EDGE_IRQ, | ||
| 1196 | }; | ||
| 1197 | |||
| 1198 | static __init int da850_wl12xx_init(void) | ||
| 1199 | { | ||
| 1200 | int ret; | ||
| 1201 | |||
| 1202 | ret = davinci_cfg_reg_list(da850_wl12xx_pins); | ||
| 1203 | if (ret) { | ||
| 1204 | pr_err("wl12xx/mmc mux setup failed: %d\n", ret); | ||
| 1205 | goto exit; | ||
| 1206 | } | ||
| 1207 | |||
| 1208 | ret = da850_register_mmcsd1(&da850_wl12xx_mmc_config); | ||
| 1209 | if (ret) { | ||
| 1210 | pr_err("wl12xx/mmc registration failed: %d\n", ret); | ||
| 1211 | goto exit; | ||
| 1212 | } | ||
| 1213 | |||
| 1214 | ret = gpio_request_one(DA850_WLAN_EN, GPIOF_OUT_INIT_LOW, "wl12xx_en"); | ||
| 1215 | if (ret) { | ||
| 1216 | pr_err("Could not request wl12xx enable gpio: %d\n", ret); | ||
| 1217 | goto exit; | ||
| 1218 | } | ||
| 1219 | |||
| 1220 | ret = gpio_request_one(DA850_WLAN_IRQ, GPIOF_IN, "wl12xx_irq"); | ||
| 1221 | if (ret) { | ||
| 1222 | pr_err("Could not request wl12xx irq gpio: %d\n", ret); | ||
| 1223 | goto free_wlan_en; | ||
| 1224 | } | ||
| 1225 | |||
| 1226 | da850_wl12xx_wlan_data.irq = gpio_to_irq(DA850_WLAN_IRQ); | ||
| 1227 | |||
| 1228 | ret = wl12xx_set_platform_data(&da850_wl12xx_wlan_data); | ||
| 1229 | if (ret) { | ||
| 1230 | pr_err("Could not set wl12xx data: %d\n", ret); | ||
| 1231 | goto free_wlan_irq; | ||
| 1232 | } | ||
| 1233 | |||
| 1234 | return 0; | ||
| 1235 | |||
| 1236 | free_wlan_irq: | ||
| 1237 | gpio_free(DA850_WLAN_IRQ); | ||
| 1238 | |||
| 1239 | free_wlan_en: | ||
| 1240 | gpio_free(DA850_WLAN_EN); | ||
| 1241 | |||
| 1242 | exit: | ||
| 1243 | return ret; | ||
| 1244 | } | ||
| 1245 | |||
| 1246 | #else /* CONFIG_DA850_WL12XX */ | ||
| 1247 | |||
| 1248 | static __init int da850_wl12xx_init(void) | ||
| 1249 | { | ||
| 1250 | return 0; | ||
| 1251 | } | ||
| 1252 | |||
| 1253 | #endif /* CONFIG_DA850_WL12XX */ | ||
| 1254 | |||
| 1146 | #define DA850EVM_SATA_REFCLKPN_RATE (100 * 1000 * 1000) | 1255 | #define DA850EVM_SATA_REFCLKPN_RATE (100 * 1000 * 1000) |
| 1147 | 1256 | ||
| 1148 | static __init void da850_evm_init(void) | 1257 | static __init void da850_evm_init(void) |
| @@ -1197,6 +1306,11 @@ static __init void da850_evm_init(void) | |||
| 1197 | if (ret) | 1306 | if (ret) |
| 1198 | pr_warning("da850_evm_init: mmcsd0 registration failed:" | 1307 | pr_warning("da850_evm_init: mmcsd0 registration failed:" |
| 1199 | " %d\n", ret); | 1308 | " %d\n", ret); |
| 1309 | |||
| 1310 | ret = da850_wl12xx_init(); | ||
| 1311 | if (ret) | ||
| 1312 | pr_warning("da850_evm_init: wl12xx initialization" | ||
| 1313 | " failed: %d\n", ret); | ||
| 1200 | } | 1314 | } |
| 1201 | 1315 | ||
| 1202 | davinci_serial_init(&da850_evm_uart_config); | 1316 | davinci_serial_init(&da850_evm_uart_config); |
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 935dbed5c541..0cf0d8845422 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c | |||
| @@ -535,6 +535,13 @@ static const struct mux_config da850_pins[] = { | |||
| 535 | MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false) | 535 | MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false) |
| 536 | MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false) | 536 | MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false) |
| 537 | MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false) | 537 | MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false) |
| 538 | /* MMC/SD1 function */ | ||
| 539 | MUX_CFG(DA850, MMCSD1_DAT_0, 18, 8, 15, 2, false) | ||
| 540 | MUX_CFG(DA850, MMCSD1_DAT_1, 19, 16, 15, 2, false) | ||
| 541 | MUX_CFG(DA850, MMCSD1_DAT_2, 19, 12, 15, 2, false) | ||
| 542 | MUX_CFG(DA850, MMCSD1_DAT_3, 19, 8, 15, 2, false) | ||
| 543 | MUX_CFG(DA850, MMCSD1_CLK, 18, 12, 15, 2, false) | ||
| 544 | MUX_CFG(DA850, MMCSD1_CMD, 18, 16, 15, 2, false) | ||
| 538 | /* EMIF2.5/EMIFA function */ | 545 | /* EMIF2.5/EMIFA function */ |
| 539 | MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false) | 546 | MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false) |
| 540 | MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false) | 547 | MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false) |
| @@ -593,6 +600,8 @@ static const struct mux_config da850_pins[] = { | |||
| 593 | MUX_CFG(DA850, GPIO3_13, 7, 8, 15, 8, false) | 600 | MUX_CFG(DA850, GPIO3_13, 7, 8, 15, 8, false) |
| 594 | MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false) | 601 | MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false) |
| 595 | MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false) | 602 | MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false) |
| 603 | MUX_CFG(DA850, GPIO6_9, 13, 24, 15, 8, false) | ||
| 604 | MUX_CFG(DA850, GPIO6_10, 13, 20, 15, 8, false) | ||
| 596 | MUX_CFG(DA850, GPIO6_13, 13, 8, 15, 8, false) | 605 | MUX_CFG(DA850, GPIO6_13, 13, 8, 15, 8, false) |
| 597 | MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false) | 606 | MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false) |
| 598 | #endif | 607 | #endif |
diff --git a/arch/arm/mach-davinci/include/mach/mmc.h b/arch/arm/mach-davinci/include/mach/mmc.h index d4f1e9675069..5ba6b22ce338 100644 --- a/arch/arm/mach-davinci/include/mach/mmc.h +++ b/arch/arm/mach-davinci/include/mach/mmc.h | |||
| @@ -12,6 +12,9 @@ struct davinci_mmc_config { | |||
| 12 | /* get_cd()/get_wp() may sleep */ | 12 | /* get_cd()/get_wp() may sleep */ |
| 13 | int (*get_cd)(int module); | 13 | int (*get_cd)(int module); |
| 14 | int (*get_ro)(int module); | 14 | int (*get_ro)(int module); |
| 15 | |||
| 16 | void (*set_power)(int module, bool on); | ||
| 17 | |||
| 15 | /* wires == 0 is equivalent to wires == 4 (4-bit parallel) */ | 18 | /* wires == 0 is equivalent to wires == 4 (4-bit parallel) */ |
| 16 | u8 wires; | 19 | u8 wires; |
| 17 | 20 | ||
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h index 5d4e0fed828a..a7e92fca32e6 100644 --- a/arch/arm/mach-davinci/include/mach/mux.h +++ b/arch/arm/mach-davinci/include/mach/mux.h | |||
| @@ -857,6 +857,14 @@ enum davinci_da850_index { | |||
| 857 | DA850_MMCSD0_CLK, | 857 | DA850_MMCSD0_CLK, |
| 858 | DA850_MMCSD0_CMD, | 858 | DA850_MMCSD0_CMD, |
| 859 | 859 | ||
| 860 | /* MMC/SD1 function */ | ||
| 861 | DA850_MMCSD1_DAT_0, | ||
| 862 | DA850_MMCSD1_DAT_1, | ||
| 863 | DA850_MMCSD1_DAT_2, | ||
| 864 | DA850_MMCSD1_DAT_3, | ||
| 865 | DA850_MMCSD1_CLK, | ||
| 866 | DA850_MMCSD1_CMD, | ||
| 867 | |||
| 860 | /* EMIF2.5/EMIFA function */ | 868 | /* EMIF2.5/EMIFA function */ |
| 861 | DA850_EMA_D_7, | 869 | DA850_EMA_D_7, |
| 862 | DA850_EMA_D_6, | 870 | DA850_EMA_D_6, |
| @@ -916,6 +924,8 @@ enum davinci_da850_index { | |||
| 916 | DA850_GPIO3_13, | 924 | DA850_GPIO3_13, |
| 917 | DA850_GPIO4_0, | 925 | DA850_GPIO4_0, |
| 918 | DA850_GPIO4_1, | 926 | DA850_GPIO4_1, |
| 927 | DA850_GPIO6_9, | ||
| 928 | DA850_GPIO6_10, | ||
| 919 | DA850_GPIO6_13, | 929 | DA850_GPIO6_13, |
| 920 | DA850_RTC_ALARM, | 930 | DA850_RTC_ALARM, |
| 921 | }; | 931 | }; |
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 0519dd7f034b..b4e1bf8757c7 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig | |||
| @@ -5,6 +5,18 @@ config IMX_HAVE_DMA_V1 | |||
| 5 | # Some usages assume that having one of them implies not having (e.g.) ARCH_MX2. | 5 | # Some usages assume that having one of them implies not having (e.g.) ARCH_MX2. |
| 6 | # To easily distinguish good and reviewed from unreviewed usages new (and IMHO | 6 | # To easily distinguish good and reviewed from unreviewed usages new (and IMHO |
| 7 | # more sensible) names are used: SOC_IMX31 and SOC_IMX35 | 7 | # more sensible) names are used: SOC_IMX31 and SOC_IMX35 |
| 8 | config ARCH_MX1 | ||
| 9 | bool | ||
| 10 | |||
| 11 | config MACH_MX21 | ||
| 12 | bool | ||
| 13 | |||
| 14 | config ARCH_MX25 | ||
| 15 | bool | ||
| 16 | |||
| 17 | config MACH_MX27 | ||
| 18 | bool | ||
| 19 | |||
| 8 | config ARCH_MX31 | 20 | config ARCH_MX31 |
| 9 | bool | 21 | bool |
| 10 | 22 | ||
| @@ -13,6 +25,7 @@ config ARCH_MX35 | |||
| 13 | 25 | ||
| 14 | config SOC_IMX1 | 26 | config SOC_IMX1 |
| 15 | bool | 27 | bool |
| 28 | select ARCH_MX1 | ||
| 16 | select CPU_ARM920T | 29 | select CPU_ARM920T |
| 17 | select IMX_HAVE_DMA_V1 | 30 | select IMX_HAVE_DMA_V1 |
| 18 | select IMX_HAVE_IOMUX_V1 | 31 | select IMX_HAVE_IOMUX_V1 |
| @@ -20,6 +33,7 @@ config SOC_IMX1 | |||
| 20 | 33 | ||
| 21 | config SOC_IMX21 | 34 | config SOC_IMX21 |
| 22 | bool | 35 | bool |
| 36 | select MACH_MX21 | ||
| 23 | select CPU_ARM926T | 37 | select CPU_ARM926T |
| 24 | select ARCH_MXC_AUDMUX_V1 | 38 | select ARCH_MXC_AUDMUX_V1 |
| 25 | select IMX_HAVE_DMA_V1 | 39 | select IMX_HAVE_DMA_V1 |
| @@ -28,6 +42,7 @@ config SOC_IMX21 | |||
| 28 | 42 | ||
| 29 | config SOC_IMX25 | 43 | config SOC_IMX25 |
| 30 | bool | 44 | bool |
| 45 | select ARCH_MX25 | ||
| 31 | select CPU_ARM926T | 46 | select CPU_ARM926T |
| 32 | select ARCH_MXC_AUDMUX_V2 | 47 | select ARCH_MXC_AUDMUX_V2 |
| 33 | select ARCH_MXC_IOMUX_V3 | 48 | select ARCH_MXC_IOMUX_V3 |
| @@ -35,6 +50,7 @@ config SOC_IMX25 | |||
| 35 | 50 | ||
| 36 | config SOC_IMX27 | 51 | config SOC_IMX27 |
| 37 | bool | 52 | bool |
| 53 | select MACH_MX27 | ||
| 38 | select CPU_ARM926T | 54 | select CPU_ARM926T |
| 39 | select ARCH_MXC_AUDMUX_V1 | 55 | select ARCH_MXC_AUDMUX_V1 |
| 40 | select IMX_HAVE_DMA_V1 | 56 | select IMX_HAVE_DMA_V1 |
| @@ -59,7 +75,7 @@ config SOC_IMX35 | |||
| 59 | select MXC_AVIC | 75 | select MXC_AVIC |
| 60 | 76 | ||
| 61 | 77 | ||
| 62 | if ARCH_MX1 | 78 | if ARCH_IMX_V4_V5 |
| 63 | 79 | ||
| 64 | comment "MX1 platforms:" | 80 | comment "MX1 platforms:" |
| 65 | config MACH_MXLADS | 81 | config MACH_MXLADS |
| @@ -87,30 +103,6 @@ config MACH_APF9328 | |||
| 87 | help | 103 | help |
| 88 | Say Yes here if you are using the Armadeus APF9328 development board | 104 | Say Yes here if you are using the Armadeus APF9328 development board |
| 89 | 105 | ||
| 90 | endif | ||
| 91 | |||
| 92 | if ARCH_MX2 | ||
| 93 | |||
| 94 | choice | ||
| 95 | prompt "CPUs:" | ||
| 96 | default MACH_MX21 | ||
| 97 | |||
| 98 | config MACH_MX21 | ||
| 99 | bool "i.MX21 support" | ||
| 100 | help | ||
| 101 | This enables support for Freescale's MX2 based i.MX21 processor. | ||
| 102 | |||
| 103 | config MACH_MX27 | ||
| 104 | bool "i.MX27 support" | ||
| 105 | help | ||
| 106 | This enables support for Freescale's MX2 based i.MX27 processor. | ||
| 107 | |||
| 108 | endchoice | ||
| 109 | |||
| 110 | endif | ||
| 111 | |||
| 112 | if MACH_MX21 | ||
| 113 | |||
| 114 | comment "MX21 platforms:" | 106 | comment "MX21 platforms:" |
| 115 | 107 | ||
| 116 | config MACH_MX21ADS | 108 | config MACH_MX21ADS |
| @@ -124,15 +116,12 @@ config MACH_MX21ADS | |||
| 124 | Include support for MX21ADS platform. This includes specific | 116 | Include support for MX21ADS platform. This includes specific |
| 125 | configurations for the board and its peripherals. | 117 | configurations for the board and its peripherals. |
| 126 | 118 | ||
| 127 | endif | ||
| 128 | |||
| 129 | if ARCH_MX25 | ||
| 130 | |||
| 131 | comment "MX25 platforms:" | 119 | comment "MX25 platforms:" |
| 132 | 120 | ||
| 133 | config MACH_MX25_3DS | 121 | config MACH_MX25_3DS |
| 134 | bool "Support MX25PDK (3DS) Platform" | 122 | bool "Support MX25PDK (3DS) Platform" |
| 135 | select SOC_IMX25 | 123 | select SOC_IMX25 |
| 124 | select IMX_HAVE_PLATFORM_FLEXCAN | ||
| 136 | select IMX_HAVE_PLATFORM_FSL_USB2_UDC | 125 | select IMX_HAVE_PLATFORM_FSL_USB2_UDC |
| 137 | select IMX_HAVE_PLATFORM_IMX2_WDT | 126 | select IMX_HAVE_PLATFORM_IMX2_WDT |
| 138 | select IMX_HAVE_PLATFORM_IMXDI_RTC | 127 | select IMX_HAVE_PLATFORM_IMXDI_RTC |
| @@ -174,10 +163,6 @@ config MACH_EUKREA_MBIMXSD25_BASEBOARD | |||
| 174 | 163 | ||
| 175 | endchoice | 164 | endchoice |
| 176 | 165 | ||
| 177 | endif | ||
| 178 | |||
| 179 | if MACH_MX27 | ||
| 180 | |||
| 181 | comment "MX27 platforms:" | 166 | comment "MX27 platforms:" |
| 182 | 167 | ||
| 183 | config MACH_MX27ADS | 168 | config MACH_MX27ADS |
| @@ -485,6 +470,7 @@ config MACH_QONG | |||
| 485 | bool "Support Dave/DENX QongEVB-LITE platform" | 470 | bool "Support Dave/DENX QongEVB-LITE platform" |
| 486 | select SOC_IMX31 | 471 | select SOC_IMX31 |
| 487 | select IMX_HAVE_PLATFORM_IMX_UART | 472 | select IMX_HAVE_PLATFORM_IMX_UART |
| 473 | select IMX_HAVE_PLATFORM_IMX2_WDT | ||
| 488 | help | 474 | help |
| 489 | Include support for Dave/DENX QongEVB-LITE platform. This includes | 475 | Include support for Dave/DENX QongEVB-LITE platform. This includes |
| 490 | specific configurations for the board and its peripherals. | 476 | specific configurations for the board and its peripherals. |
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index e9eb36dad888..116d4b2d2817 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile | |||
| @@ -1,16 +1,15 @@ | |||
| 1 | obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o | 1 | obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o |
| 2 | 2 | ||
| 3 | obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o | 3 | obj-$(CONFIG_SOC_IMX1) += clock-imx1.o mm-imx1.o |
| 4 | obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o | 4 | obj-$(CONFIG_SOC_IMX21) += clock-imx21.o mm-imx21.o |
| 5 | 5 | ||
| 6 | obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o ehci-imx25.o | 6 | obj-$(CONFIG_SOC_IMX25) += clock-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o |
| 7 | 7 | ||
| 8 | obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o | 8 | obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o |
| 9 | obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o ehci-imx27.o | 9 | obj-$(CONFIG_SOC_IMX27) += clock-imx27.o mm-imx27.o ehci-imx27.o |
| 10 | 10 | ||
| 11 | obj-$(CONFIG_SOC_IMX31) += mm-imx31.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o | 11 | obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o |
| 12 | obj-$(CONFIG_SOC_IMX35) += mm-imx35.o cpu-imx35.o clock-imx35.o ehci-imx35.o | 12 | obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o |
| 13 | obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o | ||
| 14 | 13 | ||
| 15 | # Support for CMOS sensor interface | 14 | # Support for CMOS sensor interface |
| 16 | obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o | 15 | obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o |
diff --git a/arch/arm/mach-imx/cache-l2x0.c b/arch/arm/mach-imx/cache-l2x0.c deleted file mode 100644 index 69d1322add3c..000000000000 --- a/arch/arm/mach-imx/cache-l2x0.c +++ /dev/null | |||
| @@ -1,56 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009-2010 Pengutronix | ||
| 3 | * Sascha Hauer <s.hauer@pengutronix.de> | ||
| 4 | * Juergen Beisert <j.beisert@pengutronix.de> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify it under | ||
| 7 | * the terms of the GNU General Public License version 2 as published by the | ||
| 8 | * Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/init.h> | ||
| 12 | #include <linux/err.h> | ||
| 13 | #include <linux/kernel.h> | ||
| 14 | |||
| 15 | #include <asm/hardware/cache-l2x0.h> | ||
| 16 | |||
| 17 | #include <mach/hardware.h> | ||
| 18 | |||
| 19 | static int mxc_init_l2x0(void) | ||
| 20 | { | ||
| 21 | void __iomem *l2x0_base; | ||
| 22 | void __iomem *clkctl_base; | ||
| 23 | |||
| 24 | if (!cpu_is_mx31() && !cpu_is_mx35()) | ||
| 25 | return 0; | ||
| 26 | |||
| 27 | /* | ||
| 28 | * First of all, we must repair broken chip settings. There are some | ||
| 29 | * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These | ||
| 30 | * misconfigured CPUs will run amok immediately when the L2 cache gets enabled. | ||
| 31 | * Workaraound is to setup the correct register setting prior enabling the | ||
| 32 | * L2 cache. This should not hurt already working CPUs, as they are using the | ||
| 33 | * same value. | ||
| 34 | */ | ||
| 35 | #define L2_MEM_VAL 0x10 | ||
| 36 | |||
| 37 | clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096); | ||
| 38 | if (clkctl_base != NULL) { | ||
| 39 | writel(0x00000515, clkctl_base + L2_MEM_VAL); | ||
| 40 | iounmap(clkctl_base); | ||
| 41 | } else { | ||
| 42 | pr_err("L2 cache: Cannot fix timing. Trying to continue without\n"); | ||
| 43 | } | ||
| 44 | |||
| 45 | l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096); | ||
| 46 | if (IS_ERR(l2x0_base)) { | ||
| 47 | printk(KERN_ERR "remapping L2 cache area failed with %ld\n", | ||
| 48 | PTR_ERR(l2x0_base)); | ||
| 49 | return 0; | ||
| 50 | } | ||
| 51 | |||
| 52 | l2x0_init(l2x0_base, 0x00030024, 0x00000000); | ||
| 53 | |||
| 54 | return 0; | ||
| 55 | } | ||
| 56 | arch_initcall(mxc_init_l2x0); | ||
diff --git a/arch/arm/mach-imx/clock-imx25.c b/arch/arm/mach-imx/clock-imx25.c index e63e23504fe5..b0fec74c8c91 100644 --- a/arch/arm/mach-imx/clock-imx25.c +++ b/arch/arm/mach-imx/clock-imx25.c | |||
| @@ -263,6 +263,7 @@ DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL); | |||
| 263 | DEFINE_CLOCK(csi_clk, 0, CCM_CGCR1, 4, get_rate_csi, NULL, &csi_per_clk); | 263 | DEFINE_CLOCK(csi_clk, 0, CCM_CGCR1, 4, get_rate_csi, NULL, &csi_per_clk); |
| 264 | DEFINE_CLOCK(can1_clk, 0, CCM_CGCR1, 2, get_rate_ipg, NULL, NULL); | 264 | DEFINE_CLOCK(can1_clk, 0, CCM_CGCR1, 2, get_rate_ipg, NULL, NULL); |
| 265 | DEFINE_CLOCK(can2_clk, 1, CCM_CGCR1, 3, get_rate_ipg, NULL, NULL); | 265 | DEFINE_CLOCK(can2_clk, 1, CCM_CGCR1, 3, get_rate_ipg, NULL, NULL); |
| 266 | DEFINE_CLOCK(iim_clk, 0, CCM_CGCR1, 26, NULL, NULL, NULL); | ||
| 266 | 267 | ||
| 267 | #define _REGISTER_CLOCK(d, n, c) \ | 268 | #define _REGISTER_CLOCK(d, n, c) \ |
| 268 | { \ | 269 | { \ |
| @@ -310,6 +311,7 @@ static struct clk_lookup lookups[] = { | |||
| 310 | _REGISTER_CLOCK("flexcan.1", NULL, can2_clk) | 311 | _REGISTER_CLOCK("flexcan.1", NULL, can2_clk) |
| 311 | /* i.mx25 has the i.mx35 type sdma */ | 312 | /* i.mx25 has the i.mx35 type sdma */ |
| 312 | _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk) | 313 | _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk) |
| 314 | _REGISTER_CLOCK(NULL, "iim", iim_clk) | ||
| 313 | }; | 315 | }; |
| 314 | 316 | ||
| 315 | int __init mx25_clocks_init(void) | 317 | int __init mx25_clocks_init(void) |
| @@ -334,6 +336,10 @@ int __init mx25_clocks_init(void) | |||
| 334 | /* Clock source for gpt is ahb_div */ | 336 | /* Clock source for gpt is ahb_div */ |
| 335 | __raw_writel(__raw_readl(CRM_BASE+0x64) & ~(1 << 5), CRM_BASE + 0x64); | 337 | __raw_writel(__raw_readl(CRM_BASE+0x64) & ~(1 << 5), CRM_BASE + 0x64); |
| 336 | 338 | ||
| 339 | clk_enable(&iim_clk); | ||
| 340 | imx_print_silicon_rev("i.MX25", mx25_revision()); | ||
| 341 | clk_disable(&iim_clk); | ||
| 342 | |||
| 337 | mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54); | 343 | mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54); |
| 338 | 344 | ||
| 339 | return 0; | 345 | return 0; |
diff --git a/arch/arm/mach-imx/clock-imx27.c b/arch/arm/mach-imx/clock-imx27.c index 6912b821b37b..88fe00a146e3 100644 --- a/arch/arm/mach-imx/clock-imx27.c +++ b/arch/arm/mach-imx/clock-imx27.c | |||
| @@ -583,7 +583,7 @@ DEFINE_CLOCK(emi_clk, 0, PCCR1, 19, NULL, NULL, &ahb_clk); | |||
| 583 | DEFINE_CLOCK(dma_clk1, 0, PCCR1, 20, NULL, NULL, &ahb_clk); | 583 | DEFINE_CLOCK(dma_clk1, 0, PCCR1, 20, NULL, NULL, &ahb_clk); |
| 584 | DEFINE_CLOCK(csi_clk1, 0, PCCR1, 21, NULL, NULL, &ahb_clk); | 584 | DEFINE_CLOCK(csi_clk1, 0, PCCR1, 21, NULL, NULL, &ahb_clk); |
| 585 | DEFINE_CLOCK(brom_clk, 0, PCCR1, 22, NULL, NULL, &ahb_clk); | 585 | DEFINE_CLOCK(brom_clk, 0, PCCR1, 22, NULL, NULL, &ahb_clk); |
| 586 | DEFINE_CLOCK(ata_clk, 0, PCCR1, 23, NULL, NULL, &ahb_clk); | 586 | DEFINE_CLOCK(pata_clk, 0, PCCR1, 23, NULL, NULL, &ahb_clk); |
| 587 | DEFINE_CLOCK(wdog_clk, 0, PCCR1, 24, NULL, NULL, &ipg_clk); | 587 | DEFINE_CLOCK(wdog_clk, 0, PCCR1, 24, NULL, NULL, &ipg_clk); |
| 588 | DEFINE_CLOCK(usb_clk, 0, PCCR1, 25, get_rate_usb, &usb_clk1, &spll_clk); | 588 | DEFINE_CLOCK(usb_clk, 0, PCCR1, 25, get_rate_usb, &usb_clk1, &spll_clk); |
| 589 | DEFINE_CLOCK(uart6_clk1, 0, PCCR1, 26, NULL, NULL, &ipg_clk); | 589 | DEFINE_CLOCK(uart6_clk1, 0, PCCR1, 26, NULL, NULL, &ipg_clk); |
| @@ -666,7 +666,7 @@ static struct clk_lookup lookups[] = { | |||
| 666 | _REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk) | 666 | _REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk) |
| 667 | _REGISTER_CLOCK(NULL, "emi", emi_clk) | 667 | _REGISTER_CLOCK(NULL, "emi", emi_clk) |
| 668 | _REGISTER_CLOCK(NULL, "sahara2", sahara2_clk) | 668 | _REGISTER_CLOCK(NULL, "sahara2", sahara2_clk) |
| 669 | _REGISTER_CLOCK(NULL, "ata", ata_clk) | 669 | _REGISTER_CLOCK("pata_imx", NULL, pata_clk) |
| 670 | _REGISTER_CLOCK(NULL, "mstick", mstick_clk) | 670 | _REGISTER_CLOCK(NULL, "mstick", mstick_clk) |
| 671 | _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk) | 671 | _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk) |
| 672 | _REGISTER_CLOCK(NULL, "gpio", gpio_clk) | 672 | _REGISTER_CLOCK(NULL, "gpio", gpio_clk) |
| @@ -751,6 +751,8 @@ int __init mx27_clocks_init(unsigned long fref) | |||
| 751 | clk_enable(&gpio_clk); | 751 | clk_enable(&gpio_clk); |
| 752 | clk_enable(&emi_clk); | 752 | clk_enable(&emi_clk); |
| 753 | clk_enable(&iim_clk); | 753 | clk_enable(&iim_clk); |
| 754 | imx_print_silicon_rev("i.MX27", mx27_revision()); | ||
| 755 | clk_disable(&iim_clk); | ||
| 754 | 756 | ||
| 755 | #if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC) | 757 | #if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC) |
| 756 | clk_enable(&uart1_clk); | 758 | clk_enable(&uart1_clk); |
diff --git a/arch/arm/mach-imx/clock-imx31.c b/arch/arm/mach-imx/clock-imx31.c index d973770b1f96..988a28178d4c 100644 --- a/arch/arm/mach-imx/clock-imx31.c +++ b/arch/arm/mach-imx/clock-imx31.c | |||
| @@ -476,7 +476,7 @@ DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CGR0, 4, NULL, NULL, &perclk_clk); | |||
| 476 | DEFINE_CLOCK(epit1_clk, 0, MXC_CCM_CGR0, 6, NULL, NULL, &perclk_clk); | 476 | DEFINE_CLOCK(epit1_clk, 0, MXC_CCM_CGR0, 6, NULL, NULL, &perclk_clk); |
| 477 | DEFINE_CLOCK(epit2_clk, 1, MXC_CCM_CGR0, 8, NULL, NULL, &perclk_clk); | 477 | DEFINE_CLOCK(epit2_clk, 1, MXC_CCM_CGR0, 8, NULL, NULL, &perclk_clk); |
| 478 | DEFINE_CLOCK(iim_clk, 0, MXC_CCM_CGR0, 10, NULL, NULL, &ipg_clk); | 478 | DEFINE_CLOCK(iim_clk, 0, MXC_CCM_CGR0, 10, NULL, NULL, &ipg_clk); |
| 479 | DEFINE_CLOCK(ata_clk, 0, MXC_CCM_CGR0, 12, NULL, NULL, &ipg_clk); | 479 | DEFINE_CLOCK(pata_clk, 0, MXC_CCM_CGR0, 12, NULL, NULL, &ipg_clk); |
| 480 | DEFINE_CLOCK(sdma_clk1, 0, MXC_CCM_CGR0, 14, NULL, NULL, &ahb_clk); | 480 | DEFINE_CLOCK(sdma_clk1, 0, MXC_CCM_CGR0, 14, NULL, NULL, &ahb_clk); |
| 481 | DEFINE_CLOCK(cspi3_clk, 2, MXC_CCM_CGR0, 16, NULL, NULL, &ipg_clk); | 481 | DEFINE_CLOCK(cspi3_clk, 2, MXC_CCM_CGR0, 16, NULL, NULL, &ipg_clk); |
| 482 | DEFINE_CLOCK(rng_clk, 0, MXC_CCM_CGR0, 18, NULL, NULL, &ipg_clk); | 482 | DEFINE_CLOCK(rng_clk, 0, MXC_CCM_CGR0, 18, NULL, NULL, &ipg_clk); |
| @@ -562,7 +562,7 @@ static struct clk_lookup lookups[] = { | |||
| 562 | _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) | 562 | _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) |
| 563 | _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) | 563 | _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) |
| 564 | _REGISTER_CLOCK(NULL, "firi", firi_clk) | 564 | _REGISTER_CLOCK(NULL, "firi", firi_clk) |
| 565 | _REGISTER_CLOCK(NULL, "ata", ata_clk) | 565 | _REGISTER_CLOCK("pata_imx", NULL, pata_clk) |
| 566 | _REGISTER_CLOCK(NULL, "rtic", rtic_clk) | 566 | _REGISTER_CLOCK(NULL, "rtic", rtic_clk) |
| 567 | _REGISTER_CLOCK(NULL, "rng", rng_clk) | 567 | _REGISTER_CLOCK(NULL, "rng", rng_clk) |
| 568 | _REGISTER_CLOCK("imx31-sdma", NULL, sdma_clk1) | 568 | _REGISTER_CLOCK("imx31-sdma", NULL, sdma_clk1) |
| @@ -611,11 +611,11 @@ int __init mx31_clocks_init(unsigned long fref) | |||
| 611 | clk_enable(&gpt_clk); | 611 | clk_enable(&gpt_clk); |
| 612 | clk_enable(&emi_clk); | 612 | clk_enable(&emi_clk); |
| 613 | clk_enable(&iim_clk); | 613 | clk_enable(&iim_clk); |
| 614 | mx31_revision(); | ||
| 615 | clk_disable(&iim_clk); | ||
| 614 | 616 | ||
| 615 | clk_enable(&serial_pll_clk); | 617 | clk_enable(&serial_pll_clk); |
| 616 | 618 | ||
| 617 | mx31_read_cpu_rev(); | ||
| 618 | |||
| 619 | if (mx31_revision() >= IMX_CHIP_REVISION_2_0) { | 619 | if (mx31_revision() >= IMX_CHIP_REVISION_2_0) { |
| 620 | reg = __raw_readl(MXC_CCM_PMCR1); | 620 | reg = __raw_readl(MXC_CCM_PMCR1); |
| 621 | /* No PLL restart on DVFS switch; enable auto EMI handshake */ | 621 | /* No PLL restart on DVFS switch; enable auto EMI handshake */ |
diff --git a/arch/arm/mach-imx/clock-imx35.c b/arch/arm/mach-imx/clock-imx35.c index 88b62a071aea..8116f119517d 100644 --- a/arch/arm/mach-imx/clock-imx35.c +++ b/arch/arm/mach-imx/clock-imx35.c | |||
| @@ -354,7 +354,7 @@ static void clk_cgr_disable(struct clk *clk) | |||
| 354 | } | 354 | } |
| 355 | 355 | ||
| 356 | DEFINE_CLOCK(asrc_clk, 0, CCM_CGR0, 0, NULL, NULL); | 356 | DEFINE_CLOCK(asrc_clk, 0, CCM_CGR0, 0, NULL, NULL); |
| 357 | DEFINE_CLOCK(ata_clk, 0, CCM_CGR0, 2, get_rate_ipg, NULL); | 357 | DEFINE_CLOCK(pata_clk, 0, CCM_CGR0, 2, get_rate_ipg, NULL); |
| 358 | /* DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0, 4, NULL, NULL); */ | 358 | /* DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0, 4, NULL, NULL); */ |
| 359 | DEFINE_CLOCK(can1_clk, 0, CCM_CGR0, 6, get_rate_ipg, NULL); | 359 | DEFINE_CLOCK(can1_clk, 0, CCM_CGR0, 6, get_rate_ipg, NULL); |
| 360 | DEFINE_CLOCK(can2_clk, 1, CCM_CGR0, 8, get_rate_ipg, NULL); | 360 | DEFINE_CLOCK(can2_clk, 1, CCM_CGR0, 8, get_rate_ipg, NULL); |
| @@ -447,7 +447,7 @@ static struct clk nfc_clk = { | |||
| 447 | 447 | ||
| 448 | static struct clk_lookup lookups[] = { | 448 | static struct clk_lookup lookups[] = { |
| 449 | _REGISTER_CLOCK(NULL, "asrc", asrc_clk) | 449 | _REGISTER_CLOCK(NULL, "asrc", asrc_clk) |
| 450 | _REGISTER_CLOCK(NULL, "ata", ata_clk) | 450 | _REGISTER_CLOCK("pata_imx", NULL, pata_clk) |
| 451 | _REGISTER_CLOCK("flexcan.0", NULL, can1_clk) | 451 | _REGISTER_CLOCK("flexcan.0", NULL, can1_clk) |
| 452 | _REGISTER_CLOCK("flexcan.1", NULL, can2_clk) | 452 | _REGISTER_CLOCK("flexcan.1", NULL, can2_clk) |
| 453 | _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi1_clk) | 453 | _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi1_clk) |
| @@ -537,7 +537,8 @@ int __init mx35_clocks_init() | |||
| 537 | __raw_writel(cgr3, CCM_BASE + CCM_CGR3); | 537 | __raw_writel(cgr3, CCM_BASE + CCM_CGR3); |
| 538 | 538 | ||
| 539 | clk_enable(&iim_clk); | 539 | clk_enable(&iim_clk); |
| 540 | mx35_read_cpu_rev(); | 540 | imx_print_silicon_rev("i.MX35", mx35_revision()); |
| 541 | clk_disable(&iim_clk); | ||
| 541 | 542 | ||
| 542 | #ifdef CONFIG_MXC_USE_EPIT | 543 | #ifdef CONFIG_MXC_USE_EPIT |
| 543 | epit_timer_init(&epit1_clk, | 544 | epit_timer_init(&epit1_clk, |
diff --git a/arch/arm/mach-imx/cpu-imx25.c b/arch/arm/mach-imx/cpu-imx25.c new file mode 100644 index 000000000000..6914bcbf84e4 --- /dev/null +++ b/arch/arm/mach-imx/cpu-imx25.c | |||
| @@ -0,0 +1,41 @@ | |||
| 1 | /* | ||
| 2 | * MX25 CPU type detection | ||
| 3 | * | ||
| 4 | * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> | ||
| 5 | * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | #include <linux/module.h> | ||
| 13 | #include <linux/io.h> | ||
| 14 | #include <mach/hardware.h> | ||
| 15 | #include <mach/iim.h> | ||
| 16 | |||
| 17 | static int mx25_cpu_rev = -1; | ||
| 18 | |||
| 19 | static int mx25_read_cpu_rev(void) | ||
| 20 | { | ||
| 21 | u32 rev; | ||
| 22 | |||
| 23 | rev = __raw_readl(MX25_IO_ADDRESS(MX25_IIM_BASE_ADDR + MXC_IIMSREV)); | ||
| 24 | switch (rev) { | ||
| 25 | case 0x00: | ||
| 26 | return IMX_CHIP_REVISION_1_0; | ||
| 27 | case 0x01: | ||
| 28 | return IMX_CHIP_REVISION_1_1; | ||
| 29 | default: | ||
| 30 | return IMX_CHIP_REVISION_UNKNOWN; | ||
| 31 | } | ||
| 32 | } | ||
| 33 | |||
| 34 | int mx25_revision(void) | ||
| 35 | { | ||
| 36 | if (mx25_cpu_rev == -1) | ||
| 37 | mx25_cpu_rev = mx25_read_cpu_rev(); | ||
| 38 | |||
| 39 | return mx25_cpu_rev; | ||
| 40 | } | ||
| 41 | EXPORT_SYMBOL(mx25_revision); | ||
diff --git a/arch/arm/mach-imx/cpu-imx27.c b/arch/arm/mach-imx/cpu-imx27.c index 3b117be37bd2..ff38e1505f67 100644 --- a/arch/arm/mach-imx/cpu-imx27.c +++ b/arch/arm/mach-imx/cpu-imx27.c | |||
| @@ -26,12 +26,12 @@ | |||
| 26 | 26 | ||
| 27 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
| 28 | 28 | ||
| 29 | static int cpu_silicon_rev = -1; | 29 | static int mx27_cpu_rev = -1; |
| 30 | static int cpu_partnumber; | 30 | static int mx27_cpu_partnumber; |
| 31 | 31 | ||
| 32 | #define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */ | 32 | #define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */ |
| 33 | 33 | ||
| 34 | static void query_silicon_parameter(void) | 34 | static int mx27_read_cpu_rev(void) |
| 35 | { | 35 | { |
| 36 | u32 val; | 36 | u32 val; |
| 37 | /* | 37 | /* |
| @@ -42,20 +42,18 @@ static void query_silicon_parameter(void) | |||
| 42 | val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR | 42 | val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR |
| 43 | + SYS_CHIP_ID)); | 43 | + SYS_CHIP_ID)); |
| 44 | 44 | ||
| 45 | mx27_cpu_partnumber = (int)((val >> 12) & 0xFFFF); | ||
| 46 | |||
| 45 | switch (val >> 28) { | 47 | switch (val >> 28) { |
| 46 | case 0: | 48 | case 0: |
| 47 | cpu_silicon_rev = IMX_CHIP_REVISION_1_0; | 49 | return IMX_CHIP_REVISION_1_0; |
| 48 | break; | ||
| 49 | case 1: | 50 | case 1: |
| 50 | cpu_silicon_rev = IMX_CHIP_REVISION_2_0; | 51 | return IMX_CHIP_REVISION_2_0; |
| 51 | break; | ||
| 52 | case 2: | 52 | case 2: |
| 53 | cpu_silicon_rev = IMX_CHIP_REVISION_2_1; | 53 | return IMX_CHIP_REVISION_2_1; |
| 54 | break; | ||
| 55 | default: | 54 | default: |
| 56 | cpu_silicon_rev = IMX_CHIP_REVISION_UNKNOWN; | 55 | return IMX_CHIP_REVISION_UNKNOWN; |
| 57 | } | 56 | } |
| 58 | cpu_partnumber = (int)((val >> 12) & 0xFFFF); | ||
| 59 | } | 57 | } |
| 60 | 58 | ||
| 61 | /* | 59 | /* |
| @@ -65,12 +63,12 @@ static void query_silicon_parameter(void) | |||
| 65 | */ | 63 | */ |
| 66 | int mx27_revision(void) | 64 | int mx27_revision(void) |
| 67 | { | 65 | { |
| 68 | if (cpu_silicon_rev == -1) | 66 | if (mx27_cpu_rev == -1) |
| 69 | query_silicon_parameter(); | 67 | mx27_cpu_rev = mx27_read_cpu_rev(); |
| 70 | 68 | ||
| 71 | if (cpu_partnumber != 0x8821) | 69 | if (mx27_cpu_partnumber != 0x8821) |
| 72 | return -EINVAL; | 70 | return -EINVAL; |
| 73 | 71 | ||
| 74 | return cpu_silicon_rev; | 72 | return mx27_cpu_rev; |
| 75 | } | 73 | } |
| 76 | EXPORT_SYMBOL(mx27_revision); | 74 | EXPORT_SYMBOL(mx27_revision); |
diff --git a/arch/arm/mach-imx/cpu-imx31.c b/arch/arm/mach-imx/cpu-imx31.c index a3780700a882..3f2345f0cdaf 100644 --- a/arch/arm/mach-imx/cpu-imx31.c +++ b/arch/arm/mach-imx/cpu-imx31.c | |||
| @@ -13,45 +13,50 @@ | |||
| 13 | #include <linux/io.h> | 13 | #include <linux/io.h> |
| 14 | #include <mach/hardware.h> | 14 | #include <mach/hardware.h> |
| 15 | #include <mach/iim.h> | 15 | #include <mach/iim.h> |
| 16 | #include <mach/common.h> | ||
| 16 | 17 | ||
| 17 | unsigned int mx31_cpu_rev; | 18 | static int mx31_cpu_rev = -1; |
| 18 | EXPORT_SYMBOL(mx31_cpu_rev); | ||
| 19 | 19 | ||
| 20 | static struct { | 20 | static struct { |
| 21 | u8 srev; | 21 | u8 srev; |
| 22 | const char *name; | 22 | const char *name; |
| 23 | const char *v; | ||
| 24 | unsigned int rev; | 23 | unsigned int rev; |
| 25 | } mx31_cpu_type[] __initdata = { | 24 | } mx31_cpu_type[] = { |
| 26 | { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = IMX_CHIP_REVISION_1_0 }, | 25 | { .srev = 0x00, .name = "i.MX31(L)", .rev = IMX_CHIP_REVISION_1_0 }, |
| 27 | { .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 }, | 26 | { .srev = 0x10, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_1 }, |
| 28 | { .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 }, | 27 | { .srev = 0x11, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_1 }, |
| 29 | { .srev = 0x12, .name = "i.MX31", .v = "1.15", .rev = IMX_CHIP_REVISION_1_1 }, | 28 | { .srev = 0x12, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_1 }, |
| 30 | { .srev = 0x13, .name = "i.MX31L", .v = "1.15", .rev = IMX_CHIP_REVISION_1_1 }, | 29 | { .srev = 0x13, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_1 }, |
| 31 | { .srev = 0x14, .name = "i.MX31", .v = "1.2", .rev = IMX_CHIP_REVISION_1_2 }, | 30 | { .srev = 0x14, .name = "i.MX31", .rev = IMX_CHIP_REVISION_1_2 }, |
| 32 | { .srev = 0x15, .name = "i.MX31L", .v = "1.2", .rev = IMX_CHIP_REVISION_1_2 }, | 31 | { .srev = 0x15, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_2 }, |
| 33 | { .srev = 0x28, .name = "i.MX31", .v = "2.0", .rev = IMX_CHIP_REVISION_2_0 }, | 32 | { .srev = 0x28, .name = "i.MX31", .rev = IMX_CHIP_REVISION_2_0 }, |
| 34 | { .srev = 0x29, .name = "i.MX31L", .v = "2.0", .rev = IMX_CHIP_REVISION_2_0 }, | 33 | { .srev = 0x29, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_2_0 }, |
| 35 | }; | 34 | }; |
| 36 | 35 | ||
| 37 | void __init mx31_read_cpu_rev(void) | 36 | static int mx31_read_cpu_rev(void) |
| 38 | { | 37 | { |
| 39 | u32 i, srev; | 38 | u32 i, srev; |
| 40 | 39 | ||
| 41 | /* read SREV register from IIM module */ | 40 | /* read SREV register from IIM module */ |
| 42 | srev = __raw_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV)); | 41 | srev = __raw_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV)); |
| 42 | srev &= 0xff; | ||
| 43 | 43 | ||
| 44 | for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++) | 44 | for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++) |
| 45 | if (srev == mx31_cpu_type[i].srev) { | 45 | if (srev == mx31_cpu_type[i].srev) { |
| 46 | printk(KERN_INFO | 46 | imx_print_silicon_rev(mx31_cpu_type[i].name, |
| 47 | "CPU identified as %s, silicon rev %s\n", | 47 | mx31_cpu_type[i].rev); |
| 48 | mx31_cpu_type[i].name, mx31_cpu_type[i].v); | 48 | return mx31_cpu_type[i].rev; |
| 49 | |||
| 50 | mx31_cpu_rev = mx31_cpu_type[i].rev; | ||
| 51 | return; | ||
| 52 | } | 49 | } |
| 53 | 50 | ||
| 54 | mx31_cpu_rev = IMX_CHIP_REVISION_UNKNOWN; | 51 | imx_print_silicon_rev("i.MX31", IMX_CHIP_REVISION_UNKNOWN); |
| 52 | return IMX_CHIP_REVISION_UNKNOWN; | ||
| 53 | } | ||
| 54 | |||
| 55 | int mx31_revision(void) | ||
| 56 | { | ||
| 57 | if (mx31_cpu_rev == -1) | ||
| 58 | mx31_cpu_rev = mx31_read_cpu_rev(); | ||
| 55 | 59 | ||
| 56 | printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev); | 60 | return mx31_cpu_rev; |
| 57 | } | 61 | } |
| 62 | EXPORT_SYMBOL(mx31_revision); | ||
diff --git a/arch/arm/mach-imx/cpu-imx35.c b/arch/arm/mach-imx/cpu-imx35.c index 6637cd819ecb..846e46eb8cbf 100644 --- a/arch/arm/mach-imx/cpu-imx35.c +++ b/arch/arm/mach-imx/cpu-imx35.c | |||
| @@ -13,32 +13,30 @@ | |||
| 13 | #include <mach/hardware.h> | 13 | #include <mach/hardware.h> |
| 14 | #include <mach/iim.h> | 14 | #include <mach/iim.h> |
| 15 | 15 | ||
| 16 | unsigned int mx35_cpu_rev; | 16 | static int mx35_cpu_rev = -1; |
| 17 | EXPORT_SYMBOL(mx35_cpu_rev); | ||
| 18 | 17 | ||
| 19 | void __init mx35_read_cpu_rev(void) | 18 | static int mx35_read_cpu_rev(void) |
| 20 | { | 19 | { |
| 21 | u32 rev; | 20 | u32 rev; |
| 22 | char *srev; | ||
| 23 | 21 | ||
| 24 | rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV)); | 22 | rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV)); |
| 25 | switch (rev) { | 23 | switch (rev) { |
| 26 | case 0x00: | 24 | case 0x00: |
| 27 | mx35_cpu_rev = IMX_CHIP_REVISION_1_0; | 25 | return IMX_CHIP_REVISION_1_0; |
| 28 | srev = "1.0"; | ||
| 29 | break; | ||
| 30 | case 0x10: | 26 | case 0x10: |
| 31 | mx35_cpu_rev = IMX_CHIP_REVISION_2_0; | 27 | return IMX_CHIP_REVISION_2_0; |
| 32 | srev = "2.0"; | ||
| 33 | break; | ||
| 34 | case 0x11: | 28 | case 0x11: |
| 35 | mx35_cpu_rev = IMX_CHIP_REVISION_2_1; | 29 | return IMX_CHIP_REVISION_2_1; |
| 36 | srev = "2.1"; | ||
| 37 | break; | ||
| 38 | default: | 30 | default: |
| 39 | mx35_cpu_rev = IMX_CHIP_REVISION_UNKNOWN; | 31 | return IMX_CHIP_REVISION_UNKNOWN; |
| 40 | srev = "unknown"; | ||
| 41 | } | 32 | } |
| 33 | } | ||
| 34 | |||
| 35 | int mx35_revision(void) | ||
| 36 | { | ||
| 37 | if (mx35_cpu_rev == -1) | ||
| 38 | mx35_cpu_rev = mx35_read_cpu_rev(); | ||
| 42 | 39 | ||
| 43 | printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev); | 40 | return mx35_cpu_rev; |
| 44 | } | 41 | } |
| 42 | EXPORT_SYMBOL(mx35_revision); | ||
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h index 7f97a3cdd41d..2f727d7c380c 100644 --- a/arch/arm/mach-imx/devices-imx27.h +++ b/arch/arm/mach-imx/devices-imx27.h | |||
| @@ -76,3 +76,7 @@ extern const struct imx_spi_imx_data imx27_cspi_data[]; | |||
| 76 | #define imx27_add_spi_imx0(pdata) imx27_add_cspi(0, pdata) | 76 | #define imx27_add_spi_imx0(pdata) imx27_add_cspi(0, pdata) |
| 77 | #define imx27_add_spi_imx1(pdata) imx27_add_cspi(1, pdata) | 77 | #define imx27_add_spi_imx1(pdata) imx27_add_cspi(1, pdata) |
| 78 | #define imx27_add_spi_imx2(pdata) imx27_add_cspi(2, pdata) | 78 | #define imx27_add_spi_imx2(pdata) imx27_add_cspi(2, pdata) |
| 79 | |||
| 80 | extern const struct imx_pata_imx_data imx27_pata_imx_data; | ||
| 81 | #define imx27_add_pata_imx() \ | ||
| 82 | imx_add_pata_imx(&imx27_pata_imx_data) | ||
diff --git a/arch/arm/mach-imx/devices-imx31.h b/arch/arm/mach-imx/devices-imx31.h index dbe940d9c53a..488e241a6db6 100644 --- a/arch/arm/mach-imx/devices-imx31.h +++ b/arch/arm/mach-imx/devices-imx31.h | |||
| @@ -78,3 +78,7 @@ extern const struct imx_spi_imx_data imx31_cspi_data[]; | |||
| 78 | #define imx31_add_spi_imx0(pdata) imx31_add_cspi(0, pdata) | 78 | #define imx31_add_spi_imx0(pdata) imx31_add_cspi(0, pdata) |
| 79 | #define imx31_add_spi_imx1(pdata) imx31_add_cspi(1, pdata) | 79 | #define imx31_add_spi_imx1(pdata) imx31_add_cspi(1, pdata) |
| 80 | #define imx31_add_spi_imx2(pdata) imx31_add_cspi(2, pdata) | 80 | #define imx31_add_spi_imx2(pdata) imx31_add_cspi(2, pdata) |
| 81 | |||
| 82 | extern const struct imx_pata_imx_data imx31_pata_imx_data; | ||
| 83 | #define imx31_add_pata_imx() \ | ||
| 84 | imx_add_pata_imx(&imx31_pata_imx_data) | ||
diff --git a/arch/arm/mach-imx/devices-imx35.h b/arch/arm/mach-imx/devices-imx35.h index 234cbd3c18af..7b99ef0bb501 100644 --- a/arch/arm/mach-imx/devices-imx35.h +++ b/arch/arm/mach-imx/devices-imx35.h | |||
| @@ -81,3 +81,7 @@ extern const struct imx_spi_imx_data imx35_cspi_data[]; | |||
| 81 | imx_add_spi_imx(&imx35_cspi_data[id], pdata) | 81 | imx_add_spi_imx(&imx35_cspi_data[id], pdata) |
| 82 | #define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata) | 82 | #define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata) |
| 83 | #define imx35_add_spi_imx1(pdata) imx35_add_cspi(1, pdata) | 83 | #define imx35_add_spi_imx1(pdata) imx35_add_cspi(1, pdata) |
| 84 | |||
| 85 | extern const struct imx_pata_imx_data imx35_pata_imx_data; | ||
| 86 | #define imx35_add_pata_imx() \ | ||
| 87 | imx_add_pata_imx(&imx35_pata_imx_data) | ||
diff --git a/arch/arm/mach-imx/mach-apf9328.c b/arch/arm/mach-imx/mach-apf9328.c index a404c89485ca..1e486e67dabb 100644 --- a/arch/arm/mach-imx/mach-apf9328.c +++ b/arch/arm/mach-imx/mach-apf9328.c | |||
| @@ -136,6 +136,7 @@ MACHINE_START(APF9328, "Armadeus APF9328") | |||
| 136 | .map_io = mx1_map_io, | 136 | .map_io = mx1_map_io, |
| 137 | .init_early = imx1_init_early, | 137 | .init_early = imx1_init_early, |
| 138 | .init_irq = mx1_init_irq, | 138 | .init_irq = mx1_init_irq, |
| 139 | .handle_irq = imx1_handle_irq, | ||
| 139 | .timer = &apf9328_timer, | 140 | .timer = &apf9328_timer, |
| 140 | .init_machine = apf9328_init, | 141 | .init_machine = apf9328_init, |
| 141 | MACHINE_END | 142 | MACHINE_END |
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c index ede2710f8b76..e008554e48bf 100644 --- a/arch/arm/mach-imx/mach-armadillo5x0.c +++ b/arch/arm/mach-imx/mach-armadillo5x0.c | |||
| @@ -314,25 +314,19 @@ static struct mtd_partition armadillo5x0_nor_flash_partitions[] = { | |||
| 314 | }, | 314 | }, |
| 315 | }; | 315 | }; |
| 316 | 316 | ||
| 317 | static struct physmap_flash_data armadillo5x0_nor_flash_pdata = { | 317 | static const struct physmap_flash_data |
| 318 | armadillo5x0_nor_flash_pdata __initconst = { | ||
| 318 | .width = 2, | 319 | .width = 2, |
| 319 | .parts = armadillo5x0_nor_flash_partitions, | 320 | .parts = armadillo5x0_nor_flash_partitions, |
| 320 | .nr_parts = ARRAY_SIZE(armadillo5x0_nor_flash_partitions), | 321 | .nr_parts = ARRAY_SIZE(armadillo5x0_nor_flash_partitions), |
| 321 | }; | 322 | }; |
| 322 | 323 | ||
| 323 | static struct resource armadillo5x0_nor_flash_resource = { | 324 | static const struct resource armadillo5x0_nor_flash_resource __initconst = { |
| 324 | .flags = IORESOURCE_MEM, | 325 | .flags = IORESOURCE_MEM, |
| 325 | .start = MX31_CS0_BASE_ADDR, | 326 | .start = MX31_CS0_BASE_ADDR, |
| 326 | .end = MX31_CS0_BASE_ADDR + SZ_64M - 1, | 327 | .end = MX31_CS0_BASE_ADDR + SZ_64M - 1, |
| 327 | }; | 328 | }; |
| 328 | 329 | ||
| 329 | static struct platform_device armadillo5x0_nor_flash = { | ||
| 330 | .name = "physmap-flash", | ||
| 331 | .id = -1, | ||
| 332 | .num_resources = 1, | ||
| 333 | .resource = &armadillo5x0_nor_flash_resource, | ||
| 334 | }; | ||
| 335 | |||
| 336 | /* | 330 | /* |
| 337 | * FB support | 331 | * FB support |
| 338 | */ | 332 | */ |
| @@ -514,8 +508,10 @@ static void __init armadillo5x0_init(void) | |||
| 514 | imx31_add_mx3_sdc_fb(&mx3fb_pdata); | 508 | imx31_add_mx3_sdc_fb(&mx3fb_pdata); |
| 515 | 509 | ||
| 516 | /* Register NOR Flash */ | 510 | /* Register NOR Flash */ |
| 517 | mxc_register_device(&armadillo5x0_nor_flash, | 511 | platform_device_register_resndata(NULL, "physmap-flash", -1, |
| 518 | &armadillo5x0_nor_flash_pdata); | 512 | &armadillo5x0_nor_flash_resource, 1, |
| 513 | &armadillo5x0_nor_flash_pdata, | ||
| 514 | sizeof(armadillo5x0_nor_flash_pdata)); | ||
| 519 | 515 | ||
| 520 | /* Register NAND Flash */ | 516 | /* Register NAND Flash */ |
| 521 | imx31_add_mxc_nand(&armadillo5x0_nand_board_info); | 517 | imx31_add_mxc_nand(&armadillo5x0_nand_board_info); |
| @@ -562,6 +558,7 @@ MACHINE_START(ARMADILLO5X0, "Armadillo-500") | |||
| 562 | .map_io = mx31_map_io, | 558 | .map_io = mx31_map_io, |
| 563 | .init_early = imx31_init_early, | 559 | .init_early = imx31_init_early, |
| 564 | .init_irq = mx31_init_irq, | 560 | .init_irq = mx31_init_irq, |
| 561 | .handle_irq = imx31_handle_irq, | ||
| 565 | .timer = &armadillo5x0_timer, | 562 | .timer = &armadillo5x0_timer, |
| 566 | .init_machine = armadillo5x0_init, | 563 | .init_machine = armadillo5x0_init, |
| 567 | MACHINE_END | 564 | MACHINE_END |
diff --git a/arch/arm/mach-imx/mach-bug.c b/arch/arm/mach-imx/mach-bug.c index f49470553bdf..313f62ddc1ef 100644 --- a/arch/arm/mach-imx/mach-bug.c +++ b/arch/arm/mach-imx/mach-bug.c | |||
| @@ -62,6 +62,7 @@ MACHINE_START(BUG, "BugLabs BUGBase") | |||
| 62 | .map_io = mx31_map_io, | 62 | .map_io = mx31_map_io, |
| 63 | .init_early = imx31_init_early, | 63 | .init_early = imx31_init_early, |
| 64 | .init_irq = mx31_init_irq, | 64 | .init_irq = mx31_init_irq, |
| 65 | .handle_irq = imx31_handle_irq, | ||
| 65 | .timer = &bug_timer, | 66 | .timer = &bug_timer, |
| 66 | .init_machine = bug_board_init, | 67 | .init_machine = bug_board_init, |
| 67 | MACHINE_END | 68 | MACHINE_END |
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c index f851fe903687..a8364cc52b4d 100644 --- a/arch/arm/mach-imx/mach-cpuimx27.c +++ b/arch/arm/mach-imx/mach-cpuimx27.c | |||
| @@ -315,6 +315,7 @@ MACHINE_START(EUKREA_CPUIMX27, "EUKREA CPUIMX27") | |||
| 315 | .map_io = mx27_map_io, | 315 | .map_io = mx27_map_io, |
| 316 | .init_early = imx27_init_early, | 316 | .init_early = imx27_init_early, |
| 317 | .init_irq = mx27_init_irq, | 317 | .init_irq = mx27_init_irq, |
| 318 | .handle_irq = imx27_handle_irq, | ||
| 318 | .timer = &eukrea_cpuimx27_timer, | 319 | .timer = &eukrea_cpuimx27_timer, |
| 319 | .init_machine = eukrea_cpuimx27_init, | 320 | .init_machine = eukrea_cpuimx27_init, |
| 320 | MACHINE_END | 321 | MACHINE_END |
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c index 4bd083ba9af2..fc4fea1d3fc7 100644 --- a/arch/arm/mach-imx/mach-cpuimx35.c +++ b/arch/arm/mach-imx/mach-cpuimx35.c | |||
| @@ -66,7 +66,7 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = { | |||
| 66 | I2C_BOARD_INFO("tsc2007", 0x48), | 66 | I2C_BOARD_INFO("tsc2007", 0x48), |
| 67 | .type = "tsc2007", | 67 | .type = "tsc2007", |
| 68 | .platform_data = &tsc2007_info, | 68 | .platform_data = &tsc2007_info, |
| 69 | .irq = gpio_to_irq(TSC2007_IRQGPIO), | 69 | .irq = IMX_GPIO_TO_IRQ(TSC2007_IRQGPIO), |
| 70 | }, | 70 | }, |
| 71 | }; | 71 | }; |
| 72 | 72 | ||
| @@ -198,6 +198,7 @@ MACHINE_START(EUKREA_CPUIMX35SD, "Eukrea CPUIMX35") | |||
| 198 | .map_io = mx35_map_io, | 198 | .map_io = mx35_map_io, |
| 199 | .init_early = imx35_init_early, | 199 | .init_early = imx35_init_early, |
| 200 | .init_irq = mx35_init_irq, | 200 | .init_irq = mx35_init_irq, |
| 201 | .handle_irq = imx35_handle_irq, | ||
| 201 | .timer = &eukrea_cpuimx35_timer, | 202 | .timer = &eukrea_cpuimx35_timer, |
| 202 | .init_machine = eukrea_cpuimx35_init, | 203 | .init_machine = eukrea_cpuimx35_init, |
| 203 | MACHINE_END | 204 | MACHINE_END |
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c index 2442d5da883d..b05de09b1a6e 100644 --- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c +++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c | |||
| @@ -167,6 +167,7 @@ MACHINE_START(EUKREA_CPUIMX25SD, "Eukrea CPUIMX25") | |||
| 167 | .map_io = mx25_map_io, | 167 | .map_io = mx25_map_io, |
| 168 | .init_early = imx25_init_early, | 168 | .init_early = imx25_init_early, |
| 169 | .init_irq = mx25_init_irq, | 169 | .init_irq = mx25_init_irq, |
| 170 | .handle_irq = imx25_handle_irq, | ||
| 170 | .timer = &eukrea_cpuimx25_timer, | 171 | .timer = &eukrea_cpuimx25_timer, |
| 171 | .init_machine = eukrea_cpuimx25_init, | 172 | .init_machine = eukrea_cpuimx25_init, |
| 172 | MACHINE_END | 173 | MACHINE_END |
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c index 6778f8193bc6..678cf831bc31 100644 --- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c +++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c | |||
| @@ -279,6 +279,7 @@ MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10") | |||
| 279 | .map_io = mx27_map_io, | 279 | .map_io = mx27_map_io, |
| 280 | .init_early = imx27_init_early, | 280 | .init_early = imx27_init_early, |
| 281 | .init_irq = mx27_init_irq, | 281 | .init_irq = mx27_init_irq, |
| 282 | .handle_irq = imx27_handle_irq, | ||
| 282 | .timer = &visstrim_m10_timer, | 283 | .timer = &visstrim_m10_timer, |
| 283 | .init_machine = visstrim_m10_board_init, | 284 | .init_machine = visstrim_m10_board_init, |
| 284 | MACHINE_END | 285 | MACHINE_END |
diff --git a/arch/arm/mach-imx/mach-imx27ipcam.c b/arch/arm/mach-imx/mach-imx27ipcam.c index 272f793e9247..f572ce943947 100644 --- a/arch/arm/mach-imx/mach-imx27ipcam.c +++ b/arch/arm/mach-imx/mach-imx27ipcam.c | |||
| @@ -75,6 +75,7 @@ MACHINE_START(IMX27IPCAM, "Freescale IMX27IPCAM") | |||
| 75 | .map_io = mx27_map_io, | 75 | .map_io = mx27_map_io, |
| 76 | .init_early = imx27_init_early, | 76 | .init_early = imx27_init_early, |
| 77 | .init_irq = mx27_init_irq, | 77 | .init_irq = mx27_init_irq, |
| 78 | .handle_irq = imx27_handle_irq, | ||
| 78 | .timer = &mx27ipcam_timer, | 79 | .timer = &mx27ipcam_timer, |
| 79 | .init_machine = mx27ipcam_init, | 80 | .init_machine = mx27ipcam_init, |
| 80 | MACHINE_END | 81 | MACHINE_END |
diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c index d81a769fe895..e7fc4f044946 100644 --- a/arch/arm/mach-imx/mach-imx27lite.c +++ b/arch/arm/mach-imx/mach-imx27lite.c | |||
| @@ -81,6 +81,7 @@ MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE") | |||
| 81 | .map_io = mx27_map_io, | 81 | .map_io = mx27_map_io, |
| 82 | .init_early = imx27_init_early, | 82 | .init_early = imx27_init_early, |
| 83 | .init_irq = mx27_init_irq, | 83 | .init_irq = mx27_init_irq, |
| 84 | .handle_irq = imx27_handle_irq, | ||
| 84 | .timer = &mx27lite_timer, | 85 | .timer = &mx27lite_timer, |
| 85 | .init_machine = mx27lite_init, | 86 | .init_machine = mx27lite_init, |
| 86 | MACHINE_END | 87 | MACHINE_END |
diff --git a/arch/arm/mach-imx/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c index e472a1d88058..a65d91048348 100644 --- a/arch/arm/mach-imx/mach-kzm_arm11_01.c +++ b/arch/arm/mach-imx/mach-kzm_arm11_01.c | |||
| @@ -275,6 +275,7 @@ MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01") | |||
| 275 | .map_io = kzm_map_io, | 275 | .map_io = kzm_map_io, |
| 276 | .init_early = imx31_init_early, | 276 | .init_early = imx31_init_early, |
| 277 | .init_irq = mx31_init_irq, | 277 | .init_irq = mx31_init_irq, |
| 278 | .handle_irq = imx31_handle_irq, | ||
| 278 | .timer = &kzm_timer, | 279 | .timer = &kzm_timer, |
| 279 | .init_machine = kzm_board_init, | 280 | .init_machine = kzm_board_init, |
| 280 | MACHINE_END | 281 | MACHINE_END |
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c index 5cd8bee46960..ebe9a29e30a6 100644 --- a/arch/arm/mach-imx/mach-mx1ads.c +++ b/arch/arm/mach-imx/mach-mx1ads.c | |||
| @@ -68,23 +68,16 @@ static const struct imxuart_platform_data uart1_pdata __initconst = { | |||
| 68 | * Physmap flash | 68 | * Physmap flash |
| 69 | */ | 69 | */ |
| 70 | 70 | ||
| 71 | static struct physmap_flash_data mx1ads_flash_data = { | 71 | static const struct physmap_flash_data mx1ads_flash_data __initconst = { |
| 72 | .width = 4, /* bankwidth in bytes */ | 72 | .width = 4, /* bankwidth in bytes */ |
| 73 | }; | 73 | }; |
| 74 | 74 | ||
| 75 | static struct resource flash_resource = { | 75 | static const struct resource flash_resource __initconst = { |
| 76 | .start = MX1_CS0_PHYS, | 76 | .start = MX1_CS0_PHYS, |
| 77 | .end = MX1_CS0_PHYS + SZ_32M - 1, | 77 | .end = MX1_CS0_PHYS + SZ_32M - 1, |
| 78 | .flags = IORESOURCE_MEM, | 78 | .flags = IORESOURCE_MEM, |
| 79 | }; | 79 | }; |
| 80 | 80 | ||
| 81 | static struct platform_device flash_device = { | ||
| 82 | .name = "physmap-flash", | ||
| 83 | .id = 0, | ||
| 84 | .resource = &flash_resource, | ||
| 85 | .num_resources = 1, | ||
| 86 | }; | ||
| 87 | |||
| 88 | /* | 81 | /* |
| 89 | * I2C | 82 | * I2C |
| 90 | */ | 83 | */ |
| @@ -125,7 +118,9 @@ static void __init mx1ads_init(void) | |||
| 125 | imx1_add_imx_uart1(&uart1_pdata); | 118 | imx1_add_imx_uart1(&uart1_pdata); |
| 126 | 119 | ||
| 127 | /* Physmap flash */ | 120 | /* Physmap flash */ |
| 128 | mxc_register_device(&flash_device, &mx1ads_flash_data); | 121 | platform_device_register_resndata(NULL, "physmap-flash", 0, |
| 122 | &flash_resource, 1, | ||
| 123 | &mx1ads_flash_data, sizeof(mx1ads_flash_data)); | ||
| 129 | 124 | ||
| 130 | /* I2C */ | 125 | /* I2C */ |
| 131 | i2c_register_board_info(0, mx1ads_i2c_devices, | 126 | i2c_register_board_info(0, mx1ads_i2c_devices, |
| @@ -149,6 +144,7 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS") | |||
| 149 | .map_io = mx1_map_io, | 144 | .map_io = mx1_map_io, |
| 150 | .init_early = imx1_init_early, | 145 | .init_early = imx1_init_early, |
| 151 | .init_irq = mx1_init_irq, | 146 | .init_irq = mx1_init_irq, |
| 147 | .handle_irq = imx1_handle_irq, | ||
| 152 | .timer = &mx1ads_timer, | 148 | .timer = &mx1ads_timer, |
| 153 | .init_machine = mx1ads_init, | 149 | .init_machine = mx1ads_init, |
| 154 | MACHINE_END | 150 | MACHINE_END |
| @@ -158,6 +154,7 @@ MACHINE_START(MXLADS, "Freescale MXLADS") | |||
| 158 | .map_io = mx1_map_io, | 154 | .map_io = mx1_map_io, |
| 159 | .init_early = imx1_init_early, | 155 | .init_early = imx1_init_early, |
| 160 | .init_irq = mx1_init_irq, | 156 | .init_irq = mx1_init_irq, |
| 157 | .handle_irq = imx1_handle_irq, | ||
| 161 | .timer = &mx1ads_timer, | 158 | .timer = &mx1ads_timer, |
| 162 | .init_machine = mx1ads_init, | 159 | .init_machine = mx1ads_init, |
| 163 | MACHINE_END | 160 | MACHINE_END |
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c index d389ecf9b5a8..43dd22b768e0 100644 --- a/arch/arm/mach-imx/mach-mx21ads.c +++ b/arch/arm/mach-imx/mach-mx21ads.c | |||
| @@ -309,6 +309,7 @@ MACHINE_START(MX21ADS, "Freescale i.MX21ADS") | |||
| 309 | .map_io = mx21ads_map_io, | 309 | .map_io = mx21ads_map_io, |
| 310 | .init_early = imx21_init_early, | 310 | .init_early = imx21_init_early, |
| 311 | .init_irq = mx21_init_irq, | 311 | .init_irq = mx21_init_irq, |
| 312 | .handle_irq = imx21_handle_irq, | ||
| 312 | .timer = &mx21ads_timer, | 313 | .timer = &mx21ads_timer, |
| 313 | .init_machine = mx21ads_board_init, | 314 | .init_machine = mx21ads_board_init, |
| 314 | MACHINE_END | 315 | MACHINE_END |
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c index 7f66a91df361..bd735ad6675e 100644 --- a/arch/arm/mach-imx/mach-mx25_3ds.c +++ b/arch/arm/mach-imx/mach-mx25_3ds.c | |||
| @@ -43,6 +43,8 @@ | |||
| 43 | 43 | ||
| 44 | #include "devices-imx25.h" | 44 | #include "devices-imx25.h" |
| 45 | 45 | ||
| 46 | #define MX25PDK_CAN_PWDN IMX_GPIO_NR(4, 6) | ||
| 47 | |||
| 46 | static const struct imxuart_platform_data uart_pdata __initconst = { | 48 | static const struct imxuart_platform_data uart_pdata __initconst = { |
| 47 | .flags = IMXUART_HAVE_RTSCTS, | 49 | .flags = IMXUART_HAVE_RTSCTS, |
| 48 | }; | 50 | }; |
| @@ -108,6 +110,11 @@ static iomux_v3_cfg_t mx25pdk_pads[] = { | |||
| 108 | /* I2C1 */ | 110 | /* I2C1 */ |
| 109 | MX25_PAD_I2C1_CLK__I2C1_CLK, | 111 | MX25_PAD_I2C1_CLK__I2C1_CLK, |
| 110 | MX25_PAD_I2C1_DAT__I2C1_DAT, | 112 | MX25_PAD_I2C1_DAT__I2C1_DAT, |
| 113 | |||
| 114 | /* CAN1 */ | ||
| 115 | MX25_PAD_GPIO_A__CAN1_TX, | ||
| 116 | MX25_PAD_GPIO_B__CAN1_RX, | ||
| 117 | MX25_PAD_D14__GPIO_4_6, /* CAN_PWDN */ | ||
| 111 | }; | 118 | }; |
| 112 | 119 | ||
| 113 | static const struct fec_platform_data mx25_fec_pdata __initconst = { | 120 | static const struct fec_platform_data mx25_fec_pdata __initconst = { |
| @@ -240,6 +247,9 @@ static void __init mx25pdk_init(void) | |||
| 240 | 247 | ||
| 241 | imx25_add_sdhci_esdhc_imx(0, &mx25pdk_esdhc_pdata); | 248 | imx25_add_sdhci_esdhc_imx(0, &mx25pdk_esdhc_pdata); |
| 242 | imx25_add_imx_i2c0(&mx25_3ds_i2c0_data); | 249 | imx25_add_imx_i2c0(&mx25_3ds_i2c0_data); |
| 250 | |||
| 251 | gpio_request_one(MX25PDK_CAN_PWDN, GPIOF_OUT_INIT_LOW, "can-pwdn"); | ||
| 252 | imx25_add_flexcan0(NULL); | ||
| 243 | } | 253 | } |
| 244 | 254 | ||
| 245 | static void __init mx25pdk_timer_init(void) | 255 | static void __init mx25pdk_timer_init(void) |
| @@ -257,6 +267,7 @@ MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)") | |||
| 257 | .map_io = mx25_map_io, | 267 | .map_io = mx25_map_io, |
| 258 | .init_early = imx25_init_early, | 268 | .init_early = imx25_init_early, |
| 259 | .init_irq = mx25_init_irq, | 269 | .init_irq = mx25_init_irq, |
| 270 | .handle_irq = imx25_handle_irq, | ||
| 260 | .timer = &mx25pdk_timer, | 271 | .timer = &mx25pdk_timer, |
| 261 | .init_machine = mx25pdk_init, | 272 | .init_machine = mx25pdk_init, |
| 262 | MACHINE_END | 273 | MACHINE_END |
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c index 6fa6934ab150..b2bc10bdf443 100644 --- a/arch/arm/mach-imx/mach-mx27_3ds.c +++ b/arch/arm/mach-imx/mach-mx27_3ds.c | |||
| @@ -359,7 +359,7 @@ static struct spi_board_info mx27_3ds_spi_devs[] __initdata = { | |||
| 359 | .bus_num = 1, | 359 | .bus_num = 1, |
| 360 | .chip_select = 0, /* SS0 */ | 360 | .chip_select = 0, /* SS0 */ |
| 361 | .platform_data = &mc13783_pdata, | 361 | .platform_data = &mc13783_pdata, |
| 362 | .irq = gpio_to_irq(PMIC_INT), | 362 | .irq = IMX_GPIO_TO_IRQ(PMIC_INT), |
| 363 | .mode = SPI_CS_HIGH, | 363 | .mode = SPI_CS_HIGH, |
| 364 | }, { | 364 | }, { |
| 365 | .modalias = "l4f00242t03", | 365 | .modalias = "l4f00242t03", |
| @@ -425,6 +425,7 @@ MACHINE_START(MX27_3DS, "Freescale MX27PDK") | |||
| 425 | .map_io = mx27_map_io, | 425 | .map_io = mx27_map_io, |
| 426 | .init_early = imx27_init_early, | 426 | .init_early = imx27_init_early, |
| 427 | .init_irq = mx27_init_irq, | 427 | .init_irq = mx27_init_irq, |
| 428 | .handle_irq = imx27_handle_irq, | ||
| 428 | .timer = &mx27pdk_timer, | 429 | .timer = &mx27pdk_timer, |
| 429 | .init_machine = mx27pdk_init, | 430 | .init_machine = mx27pdk_init, |
| 430 | MACHINE_END | 431 | MACHINE_END |
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c index fc26ed71b9ed..e6d132108b2b 100644 --- a/arch/arm/mach-imx/mach-mx27ads.c +++ b/arch/arm/mach-imx/mach-mx27ads.c | |||
| @@ -349,6 +349,7 @@ MACHINE_START(MX27ADS, "Freescale i.MX27ADS") | |||
| 349 | .map_io = mx27ads_map_io, | 349 | .map_io = mx27ads_map_io, |
| 350 | .init_early = imx27_init_early, | 350 | .init_early = imx27_init_early, |
| 351 | .init_irq = mx27_init_irq, | 351 | .init_irq = mx27_init_irq, |
| 352 | .handle_irq = imx27_handle_irq, | ||
| 352 | .timer = &mx27ads_timer, | 353 | .timer = &mx27ads_timer, |
| 353 | .init_machine = mx27ads_board_init, | 354 | .init_machine = mx27ads_board_init, |
| 354 | MACHINE_END | 355 | MACHINE_END |
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c index c20be7530927..b4aa9c35bb45 100644 --- a/arch/arm/mach-imx/mach-mx31_3ds.c +++ b/arch/arm/mach-imx/mach-mx31_3ds.c | |||
| @@ -768,6 +768,7 @@ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") | |||
| 768 | .map_io = mx31_map_io, | 768 | .map_io = mx31_map_io, |
| 769 | .init_early = imx31_init_early, | 769 | .init_early = imx31_init_early, |
| 770 | .init_irq = mx31_init_irq, | 770 | .init_irq = mx31_init_irq, |
| 771 | .handle_irq = imx31_handle_irq, | ||
| 771 | .timer = &mx31_3ds_timer, | 772 | .timer = &mx31_3ds_timer, |
| 772 | .init_machine = mx31_3ds_init, | 773 | .init_machine = mx31_3ds_init, |
| 773 | .reserve = mx31_3ds_reserve, | 774 | .reserve = mx31_3ds_reserve, |
diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c index 29ca8907a780..13e7347e14d4 100644 --- a/arch/arm/mach-imx/mach-mx31ads.c +++ b/arch/arm/mach-imx/mach-mx31ads.c | |||
| @@ -539,6 +539,7 @@ MACHINE_START(MX31ADS, "Freescale MX31ADS") | |||
| 539 | .map_io = mx31ads_map_io, | 539 | .map_io = mx31ads_map_io, |
| 540 | .init_early = imx31_init_early, | 540 | .init_early = imx31_init_early, |
| 541 | .init_irq = mx31ads_init_irq, | 541 | .init_irq = mx31ads_init_irq, |
| 542 | .handle_irq = imx31_handle_irq, | ||
| 542 | .timer = &mx31ads_timer, | 543 | .timer = &mx31ads_timer, |
| 543 | .init_machine = mx31ads_init, | 544 | .init_machine = mx31ads_init, |
| 544 | MACHINE_END | 545 | MACHINE_END |
diff --git a/arch/arm/mach-imx/mach-mx31lilly.c b/arch/arm/mach-imx/mach-mx31lilly.c index 126913ad106a..070a8d1f40cc 100644 --- a/arch/arm/mach-imx/mach-mx31lilly.c +++ b/arch/arm/mach-imx/mach-mx31lilly.c | |||
| @@ -299,6 +299,7 @@ MACHINE_START(LILLY1131, "INCO startec LILLY-1131") | |||
| 299 | .map_io = mx31_map_io, | 299 | .map_io = mx31_map_io, |
| 300 | .init_early = imx31_init_early, | 300 | .init_early = imx31_init_early, |
| 301 | .init_irq = mx31_init_irq, | 301 | .init_irq = mx31_init_irq, |
| 302 | .handle_irq = imx31_handle_irq, | ||
| 302 | .timer = &mx31lilly_timer, | 303 | .timer = &mx31lilly_timer, |
| 303 | .init_machine = mx31lilly_board_init, | 304 | .init_machine = mx31lilly_board_init, |
| 304 | MACHINE_END | 305 | MACHINE_END |
diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c index 4b47fd9fdd89..4f66ea440742 100644 --- a/arch/arm/mach-imx/mach-mx31lite.c +++ b/arch/arm/mach-imx/mach-mx31lite.c | |||
| @@ -284,6 +284,7 @@ MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM") | |||
| 284 | .map_io = mx31lite_map_io, | 284 | .map_io = mx31lite_map_io, |
| 285 | .init_early = imx31_init_early, | 285 | .init_early = imx31_init_early, |
| 286 | .init_irq = mx31_init_irq, | 286 | .init_irq = mx31_init_irq, |
| 287 | .handle_irq = imx31_handle_irq, | ||
| 287 | .timer = &mx31lite_timer, | 288 | .timer = &mx31lite_timer, |
| 288 | .init_machine = mx31lite_init, | 289 | .init_machine = mx31lite_init, |
| 289 | MACHINE_END | 290 | MACHINE_END |
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c index b358383120e7..cd07ebe9b9d8 100644 --- a/arch/arm/mach-imx/mach-mx31moboard.c +++ b/arch/arm/mach-imx/mach-mx31moboard.c | |||
| @@ -28,6 +28,9 @@ | |||
| 28 | #include <linux/spi/spi.h> | 28 | #include <linux/spi/spi.h> |
| 29 | #include <linux/types.h> | 29 | #include <linux/types.h> |
| 30 | #include <linux/memblock.h> | 30 | #include <linux/memblock.h> |
| 31 | #include <linux/clk.h> | ||
| 32 | #include <linux/io.h> | ||
| 33 | #include <linux/err.h> | ||
| 31 | 34 | ||
| 32 | #include <linux/usb/otg.h> | 35 | #include <linux/usb/otg.h> |
| 33 | #include <linux/usb/ulpi.h> | 36 | #include <linux/usb/ulpi.h> |
| @@ -490,6 +493,18 @@ err: | |||
| 490 | 493 | ||
| 491 | } | 494 | } |
| 492 | 495 | ||
| 496 | static void mx31moboard_poweroff(void) | ||
| 497 | { | ||
| 498 | struct clk *clk = clk_get_sys("imx2-wdt.0", NULL); | ||
| 499 | |||
| 500 | if (!IS_ERR(clk)) | ||
| 501 | clk_enable(clk); | ||
| 502 | |||
| 503 | mxc_iomux_mode(MX31_PIN_WATCHDOG_RST__WATCHDOG_RST); | ||
| 504 | |||
| 505 | __raw_writew(1 << 6 | 1 << 2, MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); | ||
| 506 | } | ||
| 507 | |||
| 493 | static int mx31moboard_baseboard; | 508 | static int mx31moboard_baseboard; |
| 494 | core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444); | 509 | core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444); |
| 495 | 510 | ||
| @@ -528,6 +543,8 @@ static void __init mx31moboard_init(void) | |||
| 528 | 543 | ||
| 529 | moboard_usbh2_init(); | 544 | moboard_usbh2_init(); |
| 530 | 545 | ||
| 546 | pm_power_off = mx31moboard_poweroff; | ||
| 547 | |||
| 531 | switch (mx31moboard_baseboard) { | 548 | switch (mx31moboard_baseboard) { |
| 532 | case MX31NOBOARD: | 549 | case MX31NOBOARD: |
| 533 | break; | 550 | break; |
| @@ -572,6 +589,7 @@ MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard") | |||
| 572 | .map_io = mx31_map_io, | 589 | .map_io = mx31_map_io, |
| 573 | .init_early = imx31_init_early, | 590 | .init_early = imx31_init_early, |
| 574 | .init_irq = mx31_init_irq, | 591 | .init_irq = mx31_init_irq, |
| 592 | .handle_irq = imx31_handle_irq, | ||
| 575 | .timer = &mx31moboard_timer, | 593 | .timer = &mx31moboard_timer, |
| 576 | .init_machine = mx31moboard_init, | 594 | .init_machine = mx31moboard_init, |
| 577 | MACHINE_END | 595 | MACHINE_END |
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c index b3b9bd8ac2a3..5a5eb3e0f737 100644 --- a/arch/arm/mach-imx/mach-mx35_3ds.c +++ b/arch/arm/mach-imx/mach-mx35_3ds.c | |||
| @@ -221,6 +221,7 @@ MACHINE_START(MX35_3DS, "Freescale MX35PDK") | |||
| 221 | .map_io = mx35_map_io, | 221 | .map_io = mx35_map_io, |
| 222 | .init_early = imx35_init_early, | 222 | .init_early = imx35_init_early, |
| 223 | .init_irq = mx35_init_irq, | 223 | .init_irq = mx35_init_irq, |
| 224 | .handle_irq = imx35_handle_irq, | ||
| 224 | .timer = &mx35pdk_timer, | 225 | .timer = &mx35pdk_timer, |
| 225 | .init_machine = mx35_3ds_init, | 226 | .init_machine = mx35_3ds_init, |
| 226 | MACHINE_END | 227 | MACHINE_END |
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c index c85876fed663..d01a92f71006 100644 --- a/arch/arm/mach-imx/mach-mxt_td60.c +++ b/arch/arm/mach-imx/mach-mxt_td60.c | |||
| @@ -271,6 +271,7 @@ MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60") | |||
| 271 | .map_io = mx27_map_io, | 271 | .map_io = mx27_map_io, |
| 272 | .init_early = imx27_init_early, | 272 | .init_early = imx27_init_early, |
| 273 | .init_irq = mx27_init_irq, | 273 | .init_irq = mx27_init_irq, |
| 274 | .handle_irq = imx27_handle_irq, | ||
| 274 | .timer = &mxt_td60_timer, | 275 | .timer = &mxt_td60_timer, |
| 275 | .init_machine = mxt_td60_board_init, | 276 | .init_machine = mxt_td60_board_init, |
| 276 | MACHINE_END | 277 | MACHINE_END |
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c index 71083aa16038..100babc71875 100644 --- a/arch/arm/mach-imx/mach-pca100.c +++ b/arch/arm/mach-imx/mach-pca100.c | |||
| @@ -439,6 +439,7 @@ MACHINE_START(PCA100, "phyCARD-i.MX27") | |||
| 439 | .map_io = mx27_map_io, | 439 | .map_io = mx27_map_io, |
| 440 | .init_early = imx27_init_early, | 440 | .init_early = imx27_init_early, |
| 441 | .init_irq = mx27_init_irq, | 441 | .init_irq = mx27_init_irq, |
| 442 | .handle_irq = imx27_handle_irq, | ||
| 442 | .init_machine = pca100_init, | 443 | .init_machine = pca100_init, |
| 443 | .timer = &pca100_timer, | 444 | .timer = &pca100_timer, |
| 444 | MACHINE_END | 445 | MACHINE_END |
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c index f45b7cd72c8a..3fb5eaa8248a 100644 --- a/arch/arm/mach-imx/mach-pcm037.c +++ b/arch/arm/mach-imx/mach-pcm037.c | |||
| @@ -693,6 +693,7 @@ MACHINE_START(PCM037, "Phytec Phycore pcm037") | |||
| 693 | .map_io = mx31_map_io, | 693 | .map_io = mx31_map_io, |
| 694 | .init_early = imx31_init_early, | 694 | .init_early = imx31_init_early, |
| 695 | .init_irq = mx31_init_irq, | 695 | .init_irq = mx31_init_irq, |
| 696 | .handle_irq = imx31_handle_irq, | ||
| 696 | .timer = &pcm037_timer, | 697 | .timer = &pcm037_timer, |
| 697 | .init_machine = pcm037_init, | 698 | .init_machine = pcm037_init, |
| 698 | MACHINE_END | 699 | MACHINE_END |
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c index 2d6a64bbac44..dac2b790df06 100644 --- a/arch/arm/mach-imx/mach-pcm038.c +++ b/arch/arm/mach-imx/mach-pcm038.c | |||
| @@ -353,6 +353,7 @@ MACHINE_START(PCM038, "phyCORE-i.MX27") | |||
| 353 | .map_io = mx27_map_io, | 353 | .map_io = mx27_map_io, |
| 354 | .init_early = imx27_init_early, | 354 | .init_early = imx27_init_early, |
| 355 | .init_irq = mx27_init_irq, | 355 | .init_irq = mx27_init_irq, |
| 356 | .handle_irq = imx27_handle_irq, | ||
| 356 | .timer = &pcm038_timer, | 357 | .timer = &pcm038_timer, |
| 357 | .init_machine = pcm038_init, | 358 | .init_machine = pcm038_init, |
| 358 | MACHINE_END | 359 | MACHINE_END |
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c index 660ec3e80cf8..a27baa493ced 100644 --- a/arch/arm/mach-imx/mach-pcm043.c +++ b/arch/arm/mach-imx/mach-pcm043.c | |||
| @@ -422,6 +422,7 @@ MACHINE_START(PCM043, "Phytec Phycore pcm043") | |||
| 422 | .map_io = mx35_map_io, | 422 | .map_io = mx35_map_io, |
| 423 | .init_early = imx35_init_early, | 423 | .init_early = imx35_init_early, |
| 424 | .init_irq = mx35_init_irq, | 424 | .init_irq = mx35_init_irq, |
| 425 | .handle_irq = imx35_handle_irq, | ||
| 425 | .timer = &pcm043_timer, | 426 | .timer = &pcm043_timer, |
| 426 | .init_machine = pcm043_init, | 427 | .init_machine = pcm043_init, |
| 427 | MACHINE_END | 428 | MACHINE_END |
diff --git a/arch/arm/mach-imx/mach-qong.c b/arch/arm/mach-imx/mach-qong.c index 3626f486498a..4243d1f548c2 100644 --- a/arch/arm/mach-imx/mach-qong.c +++ b/arch/arm/mach-imx/mach-qong.c | |||
| @@ -249,6 +249,7 @@ static void __init qong_init(void) | |||
| 249 | mxc_init_imx_uart(); | 249 | mxc_init_imx_uart(); |
| 250 | qong_init_nor_mtd(); | 250 | qong_init_nor_mtd(); |
| 251 | qong_init_fpga(); | 251 | qong_init_fpga(); |
| 252 | imx31_add_imx2_wdt(NULL); | ||
| 252 | } | 253 | } |
| 253 | 254 | ||
| 254 | static void __init qong_timer_init(void) | 255 | static void __init qong_timer_init(void) |
| @@ -266,6 +267,7 @@ MACHINE_START(QONG, "Dave/DENX QongEVB-LITE") | |||
| 266 | .map_io = mx31_map_io, | 267 | .map_io = mx31_map_io, |
| 267 | .init_early = imx31_init_early, | 268 | .init_early = imx31_init_early, |
| 268 | .init_irq = mx31_init_irq, | 269 | .init_irq = mx31_init_irq, |
| 270 | .handle_irq = imx31_handle_irq, | ||
| 269 | .timer = &qong_timer, | 271 | .timer = &qong_timer, |
| 270 | .init_machine = qong_init, | 272 | .init_machine = qong_init, |
| 271 | MACHINE_END | 273 | MACHINE_END |
diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c index db2d60470e15..17f15fb57e1c 100644 --- a/arch/arm/mach-imx/mach-scb9328.c +++ b/arch/arm/mach-imx/mach-scb9328.c | |||
| @@ -141,6 +141,7 @@ MACHINE_START(SCB9328, "Synertronixx scb9328") | |||
| 141 | .map_io = mx1_map_io, | 141 | .map_io = mx1_map_io, |
| 142 | .init_early = imx1_init_early, | 142 | .init_early = imx1_init_early, |
| 143 | .init_irq = mx1_init_irq, | 143 | .init_irq = mx1_init_irq, |
| 144 | .handle_irq = imx1_handle_irq, | ||
| 144 | .timer = &scb9328_timer, | 145 | .timer = &scb9328_timer, |
| 145 | .init_machine = scb9328_init, | 146 | .init_machine = scb9328_init, |
| 146 | MACHINE_END | 147 | MACHINE_END |
diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c index 7d8e012a6335..69092458f2d9 100644 --- a/arch/arm/mach-imx/mach-vpr200.c +++ b/arch/arm/mach-imx/mach-vpr200.c | |||
| @@ -162,7 +162,7 @@ static struct i2c_board_info vpr200_i2c_devices[] = { | |||
| 162 | }, { | 162 | }, { |
| 163 | I2C_BOARD_INFO("mc13892", 0x08), | 163 | I2C_BOARD_INFO("mc13892", 0x08), |
| 164 | .platform_data = &vpr200_pmic, | 164 | .platform_data = &vpr200_pmic, |
| 165 | .irq = gpio_to_irq(GPIO_PMIC_INT), | 165 | .irq = IMX_GPIO_TO_IRQ(GPIO_PMIC_INT), |
| 166 | } | 166 | } |
| 167 | }; | 167 | }; |
| 168 | 168 | ||
| @@ -319,6 +319,7 @@ MACHINE_START(VPR200, "VPR200") | |||
| 319 | .map_io = mx35_map_io, | 319 | .map_io = mx35_map_io, |
| 320 | .init_early = imx35_init_early, | 320 | .init_early = imx35_init_early, |
| 321 | .init_irq = mx35_init_irq, | 321 | .init_irq = mx35_init_irq, |
| 322 | .handle_irq = imx35_handle_irq, | ||
| 322 | .timer = &vpr200_timer, | 323 | .timer = &vpr200_timer, |
| 323 | .init_machine = vpr200_board_init, | 324 | .init_machine = vpr200_board_init, |
| 324 | MACHINE_END | 325 | MACHINE_END |
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c new file mode 100644 index 000000000000..9f0e82ec3398 --- /dev/null +++ b/arch/arm/mach-imx/mm-imx3.c | |||
| @@ -0,0 +1,256 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 1999,2000 Arm Limited | ||
| 3 | * Copyright (C) 2000 Deep Blue Solutions Ltd | ||
| 4 | * Copyright (C) 2002 Shane Nay (shane@minirl.com) | ||
| 5 | * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 6 | * - add MX31 specific definitions | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/mm.h> | ||
| 20 | #include <linux/init.h> | ||
| 21 | #include <linux/err.h> | ||
| 22 | |||
| 23 | #include <asm/pgtable.h> | ||
| 24 | #include <asm/hardware/cache-l2x0.h> | ||
| 25 | #include <asm/mach/map.h> | ||
| 26 | |||
| 27 | #include <mach/common.h> | ||
| 28 | #include <mach/devices-common.h> | ||
| 29 | #include <mach/hardware.h> | ||
| 30 | #include <mach/iomux-v3.h> | ||
| 31 | #include <mach/irqs.h> | ||
| 32 | |||
| 33 | static void imx3_idle(void) | ||
| 34 | { | ||
| 35 | unsigned long reg = 0; | ||
| 36 | __asm__ __volatile__( | ||
| 37 | /* disable I and D cache */ | ||
| 38 | "mrc p15, 0, %0, c1, c0, 0\n" | ||
| 39 | "bic %0, %0, #0x00001000\n" | ||
| 40 | "bic %0, %0, #0x00000004\n" | ||
| 41 | "mcr p15, 0, %0, c1, c0, 0\n" | ||
| 42 | /* invalidate I cache */ | ||
| 43 | "mov %0, #0\n" | ||
| 44 | "mcr p15, 0, %0, c7, c5, 0\n" | ||
| 45 | /* clear and invalidate D cache */ | ||
| 46 | "mov %0, #0\n" | ||
| 47 | "mcr p15, 0, %0, c7, c14, 0\n" | ||
| 48 | /* WFI */ | ||
| 49 | "mov %0, #0\n" | ||
| 50 | "mcr p15, 0, %0, c7, c0, 4\n" | ||
| 51 | "nop\n" "nop\n" "nop\n" "nop\n" | ||
| 52 | "nop\n" "nop\n" "nop\n" | ||
| 53 | /* enable I and D cache */ | ||
| 54 | "mrc p15, 0, %0, c1, c0, 0\n" | ||
| 55 | "orr %0, %0, #0x00001000\n" | ||
| 56 | "orr %0, %0, #0x00000004\n" | ||
| 57 | "mcr p15, 0, %0, c1, c0, 0\n" | ||
| 58 | : "=r" (reg)); | ||
| 59 | } | ||
| 60 | |||
| 61 | static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size, | ||
| 62 | unsigned int mtype) | ||
| 63 | { | ||
| 64 | if (mtype == MT_DEVICE) { | ||
| 65 | /* | ||
| 66 | * Access all peripherals below 0x80000000 as nonshared device | ||
| 67 | * on mx3, but leave l2cc alone. Otherwise cache corruptions | ||
| 68 | * can occur. | ||
| 69 | */ | ||
| 70 | if (phys_addr < 0x80000000 && | ||
| 71 | !addr_in_module(phys_addr, MX3x_L2CC)) | ||
| 72 | mtype = MT_DEVICE_NONSHARED; | ||
| 73 | } | ||
| 74 | |||
| 75 | return __arm_ioremap(phys_addr, size, mtype); | ||
| 76 | } | ||
| 77 | |||
| 78 | void imx3_init_l2x0(void) | ||
| 79 | { | ||
| 80 | void __iomem *l2x0_base; | ||
| 81 | void __iomem *clkctl_base; | ||
| 82 | |||
| 83 | /* | ||
| 84 | * First of all, we must repair broken chip settings. There are some | ||
| 85 | * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These | ||
| 86 | * misconfigured CPUs will run amok immediately when the L2 cache gets enabled. | ||
| 87 | * Workaraound is to setup the correct register setting prior enabling the | ||
| 88 | * L2 cache. This should not hurt already working CPUs, as they are using the | ||
| 89 | * same value. | ||
| 90 | */ | ||
| 91 | #define L2_MEM_VAL 0x10 | ||
| 92 | |||
| 93 | clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096); | ||
| 94 | if (clkctl_base != NULL) { | ||
| 95 | writel(0x00000515, clkctl_base + L2_MEM_VAL); | ||
| 96 | iounmap(clkctl_base); | ||
| 97 | } else { | ||
| 98 | pr_err("L2 cache: Cannot fix timing. Trying to continue without\n"); | ||
| 99 | } | ||
| 100 | |||
| 101 | l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096); | ||
| 102 | if (IS_ERR(l2x0_base)) { | ||
| 103 | printk(KERN_ERR "remapping L2 cache area failed with %ld\n", | ||
| 104 | PTR_ERR(l2x0_base)); | ||
| 105 | return; | ||
| 106 | } | ||
| 107 | |||
| 108 | l2x0_init(l2x0_base, 0x00030024, 0x00000000); | ||
| 109 | } | ||
| 110 | |||
| 111 | static struct map_desc mx31_io_desc[] __initdata = { | ||
| 112 | imx_map_entry(MX31, X_MEMC, MT_DEVICE), | ||
| 113 | imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED), | ||
| 114 | imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED), | ||
| 115 | imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED), | ||
| 116 | imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED), | ||
| 117 | }; | ||
| 118 | |||
| 119 | /* | ||
| 120 | * This function initializes the memory map. It is called during the | ||
| 121 | * system startup to create static physical to virtual memory mappings | ||
| 122 | * for the IO modules. | ||
| 123 | */ | ||
| 124 | void __init mx31_map_io(void) | ||
| 125 | { | ||
| 126 | iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc)); | ||
| 127 | } | ||
| 128 | |||
| 129 | static struct map_desc mx35_io_desc[] __initdata = { | ||
| 130 | imx_map_entry(MX35, X_MEMC, MT_DEVICE), | ||
| 131 | imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED), | ||
| 132 | imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED), | ||
| 133 | imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED), | ||
| 134 | imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED), | ||
| 135 | }; | ||
| 136 | |||
| 137 | void __init mx35_map_io(void) | ||
| 138 | { | ||
| 139 | iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc)); | ||
| 140 | } | ||
| 141 | |||
| 142 | void __init imx31_init_early(void) | ||
| 143 | { | ||
| 144 | mxc_set_cpu_type(MXC_CPU_MX31); | ||
| 145 | mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); | ||
| 146 | imx_idle = imx3_idle; | ||
| 147 | imx_ioremap = imx3_ioremap; | ||
| 148 | } | ||
| 149 | |||
| 150 | void __init imx35_init_early(void) | ||
| 151 | { | ||
| 152 | mxc_set_cpu_type(MXC_CPU_MX35); | ||
| 153 | mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR)); | ||
| 154 | mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR)); | ||
| 155 | imx_idle = imx3_idle; | ||
| 156 | imx_ioremap = imx3_ioremap; | ||
| 157 | } | ||
| 158 | |||
| 159 | void __init mx31_init_irq(void) | ||
| 160 | { | ||
| 161 | mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR)); | ||
| 162 | } | ||
| 163 | |||
| 164 | void __init mx35_init_irq(void) | ||
| 165 | { | ||
| 166 | mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR)); | ||
| 167 | } | ||
| 168 | |||
| 169 | static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = { | ||
| 170 | .per_2_per_addr = 1677, | ||
| 171 | }; | ||
| 172 | |||
| 173 | static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = { | ||
| 174 | .ap_2_ap_addr = 423, | ||
| 175 | .ap_2_bp_addr = 829, | ||
| 176 | .bp_2_ap_addr = 1029, | ||
| 177 | }; | ||
| 178 | |||
| 179 | static struct sdma_platform_data imx31_sdma_pdata __initdata = { | ||
| 180 | .fw_name = "sdma-imx31-to2.bin", | ||
| 181 | .script_addrs = &imx31_to2_sdma_script, | ||
| 182 | }; | ||
| 183 | |||
| 184 | void __init imx31_soc_init(void) | ||
| 185 | { | ||
| 186 | int to_version = mx31_revision() >> 4; | ||
| 187 | |||
| 188 | imx3_init_l2x0(); | ||
| 189 | |||
| 190 | mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0); | ||
| 191 | mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0); | ||
| 192 | mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0); | ||
| 193 | |||
| 194 | if (to_version == 1) { | ||
| 195 | strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin", | ||
| 196 | strlen(imx31_sdma_pdata.fw_name)); | ||
| 197 | imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script; | ||
| 198 | } | ||
| 199 | |||
| 200 | imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata); | ||
| 201 | } | ||
| 202 | |||
| 203 | static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = { | ||
| 204 | .ap_2_ap_addr = 642, | ||
| 205 | .uart_2_mcu_addr = 817, | ||
| 206 | .mcu_2_app_addr = 747, | ||
| 207 | .uartsh_2_mcu_addr = 1183, | ||
| 208 | .per_2_shp_addr = 1033, | ||
| 209 | .mcu_2_shp_addr = 961, | ||
| 210 | .ata_2_mcu_addr = 1333, | ||
| 211 | .mcu_2_ata_addr = 1252, | ||
| 212 | .app_2_mcu_addr = 683, | ||
| 213 | .shp_2_per_addr = 1111, | ||
| 214 | .shp_2_mcu_addr = 892, | ||
| 215 | }; | ||
| 216 | |||
| 217 | static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = { | ||
| 218 | .ap_2_ap_addr = 729, | ||
| 219 | .uart_2_mcu_addr = 904, | ||
| 220 | .per_2_app_addr = 1597, | ||
| 221 | .mcu_2_app_addr = 834, | ||
| 222 | .uartsh_2_mcu_addr = 1270, | ||
| 223 | .per_2_shp_addr = 1120, | ||
| 224 | .mcu_2_shp_addr = 1048, | ||
| 225 | .ata_2_mcu_addr = 1429, | ||
| 226 | .mcu_2_ata_addr = 1339, | ||
| 227 | .app_2_per_addr = 1531, | ||
| 228 | .app_2_mcu_addr = 770, | ||
| 229 | .shp_2_per_addr = 1198, | ||
| 230 | .shp_2_mcu_addr = 979, | ||
| 231 | }; | ||
| 232 | |||
| 233 | static struct sdma_platform_data imx35_sdma_pdata __initdata = { | ||
| 234 | .fw_name = "sdma-imx35-to2.bin", | ||
| 235 | .script_addrs = &imx35_to2_sdma_script, | ||
| 236 | }; | ||
| 237 | |||
| 238 | void __init imx35_soc_init(void) | ||
| 239 | { | ||
| 240 | int to_version = mx35_revision() >> 4; | ||
| 241 | |||
| 242 | imx3_init_l2x0(); | ||
| 243 | |||
| 244 | /* i.mx35 has the i.mx31 type gpio */ | ||
| 245 | mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0); | ||
| 246 | mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0); | ||
| 247 | mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0); | ||
| 248 | |||
| 249 | if (to_version == 1) { | ||
| 250 | strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin", | ||
| 251 | strlen(imx35_sdma_pdata.fw_name)); | ||
| 252 | imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script; | ||
| 253 | } | ||
| 254 | |||
| 255 | imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata); | ||
| 256 | } | ||
diff --git a/arch/arm/mach-imx/mm-imx31.c b/arch/arm/mach-imx/mm-imx31.c deleted file mode 100644 index b7c55e7db000..000000000000 --- a/arch/arm/mach-imx/mm-imx31.c +++ /dev/null | |||
| @@ -1,91 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 1999,2000 Arm Limited | ||
| 3 | * Copyright (C) 2000 Deep Blue Solutions Ltd | ||
| 4 | * Copyright (C) 2002 Shane Nay (shane@minirl.com) | ||
| 5 | * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 6 | * - add MX31 specific definitions | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/mm.h> | ||
| 20 | #include <linux/init.h> | ||
| 21 | #include <linux/err.h> | ||
| 22 | |||
| 23 | #include <asm/pgtable.h> | ||
| 24 | #include <asm/mach/map.h> | ||
| 25 | |||
| 26 | #include <mach/common.h> | ||
| 27 | #include <mach/devices-common.h> | ||
| 28 | #include <mach/hardware.h> | ||
| 29 | #include <mach/iomux-v3.h> | ||
| 30 | #include <mach/irqs.h> | ||
| 31 | |||
| 32 | static struct map_desc mx31_io_desc[] __initdata = { | ||
| 33 | imx_map_entry(MX31, X_MEMC, MT_DEVICE), | ||
| 34 | imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED), | ||
| 35 | imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED), | ||
| 36 | imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED), | ||
| 37 | imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED), | ||
| 38 | }; | ||
| 39 | |||
| 40 | /* | ||
| 41 | * This function initializes the memory map. It is called during the | ||
| 42 | * system startup to create static physical to virtual memory mappings | ||
| 43 | * for the IO modules. | ||
| 44 | */ | ||
| 45 | void __init mx31_map_io(void) | ||
| 46 | { | ||
| 47 | iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc)); | ||
| 48 | } | ||
| 49 | |||
| 50 | void __init imx31_init_early(void) | ||
| 51 | { | ||
| 52 | mxc_set_cpu_type(MXC_CPU_MX31); | ||
| 53 | mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); | ||
| 54 | } | ||
| 55 | |||
| 56 | void __init mx31_init_irq(void) | ||
| 57 | { | ||
| 58 | mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR)); | ||
| 59 | } | ||
| 60 | |||
| 61 | static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = { | ||
| 62 | .per_2_per_addr = 1677, | ||
| 63 | }; | ||
| 64 | |||
| 65 | static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = { | ||
| 66 | .ap_2_ap_addr = 423, | ||
| 67 | .ap_2_bp_addr = 829, | ||
| 68 | .bp_2_ap_addr = 1029, | ||
| 69 | }; | ||
| 70 | |||
| 71 | static struct sdma_platform_data imx31_sdma_pdata __initdata = { | ||
| 72 | .fw_name = "sdma-imx31-to2.bin", | ||
| 73 | .script_addrs = &imx31_to2_sdma_script, | ||
| 74 | }; | ||
| 75 | |||
| 76 | void __init imx31_soc_init(void) | ||
| 77 | { | ||
| 78 | int to_version = mx31_revision() >> 4; | ||
| 79 | |||
| 80 | mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0); | ||
| 81 | mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0); | ||
| 82 | mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0); | ||
| 83 | |||
| 84 | if (to_version == 1) { | ||
| 85 | strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin", | ||
| 86 | strlen(imx31_sdma_pdata.fw_name)); | ||
| 87 | imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script; | ||
| 88 | } | ||
| 89 | |||
| 90 | imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata); | ||
| 91 | } | ||
diff --git a/arch/arm/mach-imx/mm-imx35.c b/arch/arm/mach-imx/mm-imx35.c deleted file mode 100644 index f49bac7a1ede..000000000000 --- a/arch/arm/mach-imx/mm-imx35.c +++ /dev/null | |||
| @@ -1,109 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 1999,2000 Arm Limited | ||
| 3 | * Copyright (C) 2000 Deep Blue Solutions Ltd | ||
| 4 | * Copyright (C) 2002 Shane Nay (shane@minirl.com) | ||
| 5 | * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 6 | * - add MX31 specific definitions | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/mm.h> | ||
| 20 | #include <linux/init.h> | ||
| 21 | #include <linux/err.h> | ||
| 22 | |||
| 23 | #include <asm/pgtable.h> | ||
| 24 | #include <asm/mach/map.h> | ||
| 25 | #include <asm/hardware/cache-l2x0.h> | ||
| 26 | |||
| 27 | #include <mach/common.h> | ||
| 28 | #include <mach/devices-common.h> | ||
| 29 | #include <mach/hardware.h> | ||
| 30 | #include <mach/iomux-v3.h> | ||
| 31 | #include <mach/irqs.h> | ||
| 32 | |||
| 33 | static struct map_desc mx35_io_desc[] __initdata = { | ||
| 34 | imx_map_entry(MX35, X_MEMC, MT_DEVICE), | ||
| 35 | imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED), | ||
| 36 | imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED), | ||
| 37 | imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED), | ||
| 38 | imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED), | ||
| 39 | }; | ||
| 40 | |||
| 41 | void __init mx35_map_io(void) | ||
| 42 | { | ||
| 43 | iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc)); | ||
| 44 | } | ||
| 45 | |||
| 46 | void __init imx35_init_early(void) | ||
| 47 | { | ||
| 48 | mxc_set_cpu_type(MXC_CPU_MX35); | ||
| 49 | mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR)); | ||
| 50 | mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR)); | ||
| 51 | } | ||
| 52 | |||
| 53 | void __init mx35_init_irq(void) | ||
| 54 | { | ||
| 55 | mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR)); | ||
| 56 | } | ||
| 57 | |||
| 58 | static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = { | ||
| 59 | .ap_2_ap_addr = 642, | ||
| 60 | .uart_2_mcu_addr = 817, | ||
| 61 | .mcu_2_app_addr = 747, | ||
| 62 | .uartsh_2_mcu_addr = 1183, | ||
| 63 | .per_2_shp_addr = 1033, | ||
| 64 | .mcu_2_shp_addr = 961, | ||
| 65 | .ata_2_mcu_addr = 1333, | ||
| 66 | .mcu_2_ata_addr = 1252, | ||
| 67 | .app_2_mcu_addr = 683, | ||
| 68 | .shp_2_per_addr = 1111, | ||
| 69 | .shp_2_mcu_addr = 892, | ||
| 70 | }; | ||
| 71 | |||
| 72 | static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = { | ||
| 73 | .ap_2_ap_addr = 729, | ||
| 74 | .uart_2_mcu_addr = 904, | ||
| 75 | .per_2_app_addr = 1597, | ||
| 76 | .mcu_2_app_addr = 834, | ||
| 77 | .uartsh_2_mcu_addr = 1270, | ||
| 78 | .per_2_shp_addr = 1120, | ||
| 79 | .mcu_2_shp_addr = 1048, | ||
| 80 | .ata_2_mcu_addr = 1429, | ||
| 81 | .mcu_2_ata_addr = 1339, | ||
| 82 | .app_2_per_addr = 1531, | ||
| 83 | .app_2_mcu_addr = 770, | ||
| 84 | .shp_2_per_addr = 1198, | ||
| 85 | .shp_2_mcu_addr = 979, | ||
| 86 | }; | ||
| 87 | |||
| 88 | static struct sdma_platform_data imx35_sdma_pdata __initdata = { | ||
| 89 | .fw_name = "sdma-imx35-to2.bin", | ||
| 90 | .script_addrs = &imx35_to2_sdma_script, | ||
| 91 | }; | ||
| 92 | |||
| 93 | void __init imx35_soc_init(void) | ||
| 94 | { | ||
| 95 | int to_version = mx35_revision() >> 4; | ||
| 96 | |||
| 97 | /* i.mx35 has the i.mx31 type gpio */ | ||
| 98 | mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0); | ||
| 99 | mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0); | ||
| 100 | mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0); | ||
| 101 | |||
| 102 | if (to_version == 1) { | ||
| 103 | strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin", | ||
| 104 | strlen(imx35_sdma_pdata.fw_name)); | ||
| 105 | imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script; | ||
| 106 | } | ||
| 107 | |||
| 108 | imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata); | ||
| 109 | } | ||
diff --git a/arch/arm/mach-imx/pm-imx27.c b/arch/arm/mach-imx/pm-imx27.c index acf17691d2cc..e455d2f855bf 100644 --- a/arch/arm/mach-imx/pm-imx27.c +++ b/arch/arm/mach-imx/pm-imx27.c | |||
| @@ -11,7 +11,7 @@ | |||
| 11 | #include <linux/suspend.h> | 11 | #include <linux/suspend.h> |
| 12 | #include <linux/io.h> | 12 | #include <linux/io.h> |
| 13 | #include <mach/system.h> | 13 | #include <mach/system.h> |
| 14 | #include <mach/mx27.h> | 14 | #include <mach/hardware.h> |
| 15 | 15 | ||
| 16 | static int mx27_suspend_enter(suspend_state_t state) | 16 | static int mx27_suspend_enter(suspend_state_t state) |
| 17 | { | 17 | { |
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index b4e7c58bbb38..3d4c31306ca7 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig | |||
| @@ -1,8 +1,9 @@ | |||
| 1 | if ARCH_MX503 || ARCH_MX51 | 1 | if ARCH_MX5 |
| 2 | |||
| 2 | # ARCH_MX5/50/53 are left to mark places where prevent multi-soc in single | 3 | # ARCH_MX5/50/53 are left to mark places where prevent multi-soc in single |
| 3 | # image. So for most time, SOC_IMX50/51/53 should be used. | 4 | # image. So for most time, SOC_IMX50/51/53 should be used. |
| 4 | 5 | ||
| 5 | config ARCH_MX5 | 6 | config ARCH_MX51 |
| 6 | bool | 7 | bool |
| 7 | 8 | ||
| 8 | config ARCH_MX50 | 9 | config ARCH_MX50 |
| @@ -19,7 +20,6 @@ config SOC_IMX50 | |||
| 19 | select ARCH_MXC_IOMUX_V3 | 20 | select ARCH_MXC_IOMUX_V3 |
| 20 | select ARCH_MXC_AUDMUX_V2 | 21 | select ARCH_MXC_AUDMUX_V2 |
| 21 | select ARCH_HAS_CPUFREQ | 22 | select ARCH_HAS_CPUFREQ |
| 22 | select ARCH_MX5 | ||
| 23 | select ARCH_MX50 | 23 | select ARCH_MX50 |
| 24 | 24 | ||
| 25 | config SOC_IMX51 | 25 | config SOC_IMX51 |
| @@ -30,7 +30,7 @@ config SOC_IMX51 | |||
| 30 | select ARCH_MXC_IOMUX_V3 | 30 | select ARCH_MXC_IOMUX_V3 |
| 31 | select ARCH_MXC_AUDMUX_V2 | 31 | select ARCH_MXC_AUDMUX_V2 |
| 32 | select ARCH_HAS_CPUFREQ | 32 | select ARCH_HAS_CPUFREQ |
| 33 | select ARCH_MX5 | 33 | select ARCH_MX51 |
| 34 | 34 | ||
| 35 | config SOC_IMX53 | 35 | config SOC_IMX53 |
| 36 | bool | 36 | bool |
| @@ -38,10 +38,8 @@ config SOC_IMX53 | |||
| 38 | select ARM_L1_CACHE_SHIFT_6 | 38 | select ARM_L1_CACHE_SHIFT_6 |
| 39 | select MXC_TZIC | 39 | select MXC_TZIC |
| 40 | select ARCH_MXC_IOMUX_V3 | 40 | select ARCH_MXC_IOMUX_V3 |
| 41 | select ARCH_MX5 | ||
| 42 | select ARCH_MX53 | 41 | select ARCH_MX53 |
| 43 | 42 | ||
| 44 | if ARCH_MX50_SUPPORTED | ||
| 45 | #comment "i.MX50 machines:" | 43 | #comment "i.MX50 machines:" |
| 46 | 44 | ||
| 47 | config MACH_MX50_RDP | 45 | config MACH_MX50_RDP |
| @@ -52,22 +50,20 @@ config MACH_MX50_RDP | |||
| 52 | select IMX_HAVE_PLATFORM_IMX_UART | 50 | select IMX_HAVE_PLATFORM_IMX_UART |
| 53 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | 51 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX |
| 54 | select IMX_HAVE_PLATFORM_SPI_IMX | 52 | select IMX_HAVE_PLATFORM_SPI_IMX |
| 55 | select IMX_HAVE_PLATFORM_FEC | ||
| 56 | help | 53 | help |
| 57 | Include support for MX50 reference design platform (RDP) board. This | 54 | Include support for MX50 reference design platform (RDP) board. This |
| 58 | includes specific configurations for the board and its peripherals. | 55 | includes specific configurations for the board and its peripherals. |
| 59 | 56 | ||
| 60 | endif # ARCH_MX50_SUPPORTED | ||
| 61 | |||
| 62 | if ARCH_MX51 | ||
| 63 | comment "i.MX51 machines:" | 57 | comment "i.MX51 machines:" |
| 64 | 58 | ||
| 65 | config MACH_MX51_BABBAGE | 59 | config MACH_MX51_BABBAGE |
| 66 | bool "Support MX51 BABBAGE platforms" | 60 | bool "Support MX51 BABBAGE platforms" |
| 67 | select SOC_IMX51 | 61 | select SOC_IMX51 |
| 62 | select IMX_HAVE_PLATFORM_FSL_USB2_UDC | ||
| 68 | select IMX_HAVE_PLATFORM_IMX2_WDT | 63 | select IMX_HAVE_PLATFORM_IMX2_WDT |
| 69 | select IMX_HAVE_PLATFORM_IMX_I2C | 64 | select IMX_HAVE_PLATFORM_IMX_I2C |
| 70 | select IMX_HAVE_PLATFORM_IMX_UART | 65 | select IMX_HAVE_PLATFORM_IMX_UART |
| 66 | select IMX_HAVE_PLATFORM_MXC_EHCI | ||
| 71 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | 67 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX |
| 72 | select IMX_HAVE_PLATFORM_SPI_IMX | 68 | select IMX_HAVE_PLATFORM_SPI_IMX |
| 73 | help | 69 | help |
| @@ -91,8 +87,10 @@ config MACH_MX51_3DS | |||
| 91 | config MACH_EUKREA_CPUIMX51 | 87 | config MACH_EUKREA_CPUIMX51 |
| 92 | bool "Support Eukrea CPUIMX51 module" | 88 | bool "Support Eukrea CPUIMX51 module" |
| 93 | select SOC_IMX51 | 89 | select SOC_IMX51 |
| 90 | select IMX_HAVE_PLATFORM_FSL_USB2_UDC | ||
| 94 | select IMX_HAVE_PLATFORM_IMX_I2C | 91 | select IMX_HAVE_PLATFORM_IMX_I2C |
| 95 | select IMX_HAVE_PLATFORM_IMX_UART | 92 | select IMX_HAVE_PLATFORM_IMX_UART |
| 93 | select IMX_HAVE_PLATFORM_MXC_EHCI | ||
| 96 | select IMX_HAVE_PLATFORM_MXC_NAND | 94 | select IMX_HAVE_PLATFORM_MXC_NAND |
| 97 | select IMX_HAVE_PLATFORM_SPI_IMX | 95 | select IMX_HAVE_PLATFORM_SPI_IMX |
| 98 | help | 96 | help |
| @@ -119,10 +117,12 @@ endchoice | |||
| 119 | config MACH_EUKREA_CPUIMX51SD | 117 | config MACH_EUKREA_CPUIMX51SD |
| 120 | bool "Support Eukrea CPUIMX51SD module" | 118 | bool "Support Eukrea CPUIMX51SD module" |
| 121 | select SOC_IMX51 | 119 | select SOC_IMX51 |
| 120 | select IMX_HAVE_PLATFORM_FSL_USB2_UDC | ||
| 122 | select IMX_HAVE_PLATFORM_IMX_I2C | 121 | select IMX_HAVE_PLATFORM_IMX_I2C |
| 123 | select IMX_HAVE_PLATFORM_SPI_IMX | ||
| 124 | select IMX_HAVE_PLATFORM_IMX_UART | 122 | select IMX_HAVE_PLATFORM_IMX_UART |
| 123 | select IMX_HAVE_PLATFORM_MXC_EHCI | ||
| 125 | select IMX_HAVE_PLATFORM_MXC_NAND | 124 | select IMX_HAVE_PLATFORM_MXC_NAND |
| 125 | select IMX_HAVE_PLATFORM_SPI_IMX | ||
| 126 | help | 126 | help |
| 127 | Include support for Eukrea CPUIMX51SD platform. This includes | 127 | Include support for Eukrea CPUIMX51SD platform. This includes |
| 128 | specific configurations for the module and its peripherals. | 128 | specific configurations for the module and its peripherals. |
| @@ -147,6 +147,8 @@ config MX51_EFIKA_COMMON | |||
| 147 | bool | 147 | bool |
| 148 | select SOC_IMX51 | 148 | select SOC_IMX51 |
| 149 | select IMX_HAVE_PLATFORM_IMX_UART | 149 | select IMX_HAVE_PLATFORM_IMX_UART |
| 150 | select IMX_HAVE_PLATFORM_MXC_EHCI | ||
| 151 | select IMX_HAVE_PLATFORM_PATA_IMX | ||
| 150 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | 152 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX |
| 151 | select IMX_HAVE_PLATFORM_SPI_IMX | 153 | select IMX_HAVE_PLATFORM_SPI_IMX |
| 152 | select MXC_ULPI if USB_ULPI | 154 | select MXC_ULPI if USB_ULPI |
| @@ -167,9 +169,6 @@ config MACH_MX51_EFIKASB | |||
| 167 | Include support for Genesi Efika Smartbook. This includes specific | 169 | Include support for Genesi Efika Smartbook. This includes specific |
| 168 | configurations for the board and its peripherals. | 170 | configurations for the board and its peripherals. |
| 169 | 171 | ||
| 170 | endif # ARCH_MX51 | ||
| 171 | |||
| 172 | if ARCH_MX53_SUPPORTED | ||
| 173 | comment "i.MX53 machines:" | 172 | comment "i.MX53 machines:" |
| 174 | 173 | ||
| 175 | config MACH_MX53_EVK | 174 | config MACH_MX53_EVK |
| @@ -221,6 +220,4 @@ config MACH_MX53_ARD | |||
| 221 | Include support for MX53 ARD platform. This includes specific | 220 | Include support for MX53 ARD platform. This includes specific |
| 222 | configurations for the board and its peripherals. | 221 | configurations for the board and its peripherals. |
| 223 | 222 | ||
| 224 | endif # ARCH_MX53_SUPPORTED | ||
| 225 | |||
| 226 | endif | 223 | endif |
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile index 383e7cd3fbcb..9565304b7282 100644 --- a/arch/arm/mach-mx5/Makefile +++ b/arch/arm/mach-mx5/Makefile | |||
| @@ -3,8 +3,7 @@ | |||
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | # Object file lists. | 5 | # Object file lists. |
| 6 | obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o ehci.o system.o | 6 | obj-y := cpu.o mm.o clock-mx51-mx53.o ehci.o system.o |
| 7 | obj-$(CONFIG_SOC_IMX50) += mm-mx50.o | ||
| 8 | 7 | ||
| 9 | obj-$(CONFIG_PM) += pm-imx5.o | 8 | obj-$(CONFIG_PM) += pm-imx5.o |
| 10 | obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o | 9 | obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o |
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c index 68934ea8725a..e28d0e165e5c 100644 --- a/arch/arm/mach-mx5/board-cpuimx51.c +++ b/arch/arm/mach-mx5/board-cpuimx51.c | |||
| @@ -22,21 +22,18 @@ | |||
| 22 | #include <linux/delay.h> | 22 | #include <linux/delay.h> |
| 23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
| 24 | #include <linux/interrupt.h> | 24 | #include <linux/interrupt.h> |
| 25 | #include <linux/irq.h> | ||
| 26 | 25 | ||
| 27 | #include <mach/eukrea-baseboards.h> | 26 | #include <mach/eukrea-baseboards.h> |
| 28 | #include <mach/common.h> | 27 | #include <mach/common.h> |
| 29 | #include <mach/hardware.h> | 28 | #include <mach/hardware.h> |
| 30 | #include <mach/iomux-mx51.h> | 29 | #include <mach/iomux-mx51.h> |
| 31 | 30 | ||
| 32 | #include <asm/irq.h> | ||
| 33 | #include <asm/setup.h> | 31 | #include <asm/setup.h> |
| 34 | #include <asm/mach-types.h> | 32 | #include <asm/mach-types.h> |
| 35 | #include <asm/mach/arch.h> | 33 | #include <asm/mach/arch.h> |
| 36 | #include <asm/mach/time.h> | 34 | #include <asm/mach/time.h> |
| 37 | 35 | ||
| 38 | #include "devices-imx51.h" | 36 | #include "devices-imx51.h" |
| 39 | #include "devices.h" | ||
| 40 | 37 | ||
| 41 | #define CPUIMX51_USBH1_STP IMX_GPIO_NR(1, 27) | 38 | #define CPUIMX51_USBH1_STP IMX_GPIO_NR(1, 27) |
| 42 | #define CPUIMX51_QUARTA_GPIO IMX_GPIO_NR(3, 28) | 39 | #define CPUIMX51_QUARTA_GPIO IMX_GPIO_NR(3, 28) |
| @@ -57,7 +54,7 @@ | |||
| 57 | static struct plat_serial8250_port serial_platform_data[] = { | 54 | static struct plat_serial8250_port serial_platform_data[] = { |
| 58 | { | 55 | { |
| 59 | .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000), | 56 | .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000), |
| 60 | .irq = gpio_to_irq(CPUIMX51_QUARTA_GPIO), | 57 | .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTA_GPIO), |
| 61 | .irqflags = IRQF_TRIGGER_HIGH, | 58 | .irqflags = IRQF_TRIGGER_HIGH, |
| 62 | .uartclk = CPUIMX51_QUART_XTAL, | 59 | .uartclk = CPUIMX51_QUART_XTAL, |
| 63 | .regshift = CPUIMX51_QUART_REGSHIFT, | 60 | .regshift = CPUIMX51_QUART_REGSHIFT, |
| @@ -65,7 +62,7 @@ static struct plat_serial8250_port serial_platform_data[] = { | |||
| 65 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, | 62 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, |
| 66 | }, { | 63 | }, { |
| 67 | .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000), | 64 | .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000), |
| 68 | .irq = gpio_to_irq(CPUIMX51_QUARTB_GPIO), | 65 | .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTB_GPIO), |
| 69 | .irqflags = IRQF_TRIGGER_HIGH, | 66 | .irqflags = IRQF_TRIGGER_HIGH, |
| 70 | .uartclk = CPUIMX51_QUART_XTAL, | 67 | .uartclk = CPUIMX51_QUART_XTAL, |
| 71 | .regshift = CPUIMX51_QUART_REGSHIFT, | 68 | .regshift = CPUIMX51_QUART_REGSHIFT, |
| @@ -73,7 +70,7 @@ static struct plat_serial8250_port serial_platform_data[] = { | |||
| 73 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, | 70 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, |
| 74 | }, { | 71 | }, { |
| 75 | .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000), | 72 | .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000), |
| 76 | .irq = gpio_to_irq(CPUIMX51_QUARTC_GPIO), | 73 | .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTC_GPIO), |
| 77 | .irqflags = IRQF_TRIGGER_HIGH, | 74 | .irqflags = IRQF_TRIGGER_HIGH, |
| 78 | .uartclk = CPUIMX51_QUART_XTAL, | 75 | .uartclk = CPUIMX51_QUART_XTAL, |
| 79 | .regshift = CPUIMX51_QUART_REGSHIFT, | 76 | .regshift = CPUIMX51_QUART_REGSHIFT, |
| @@ -81,7 +78,7 @@ static struct plat_serial8250_port serial_platform_data[] = { | |||
| 81 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, | 78 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, |
| 82 | }, { | 79 | }, { |
| 83 | .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000), | 80 | .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000), |
| 84 | .irq = gpio_to_irq(CPUIMX51_QUARTD_GPIO), | 81 | .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTD_GPIO), |
| 85 | .irqflags = IRQF_TRIGGER_HIGH, | 82 | .irqflags = IRQF_TRIGGER_HIGH, |
| 86 | .uartclk = CPUIMX51_QUART_XTAL, | 83 | .uartclk = CPUIMX51_QUART_XTAL, |
| 87 | .regshift = CPUIMX51_QUART_REGSHIFT, | 84 | .regshift = CPUIMX51_QUART_REGSHIFT, |
| @@ -167,7 +164,7 @@ static int initialize_otg_port(struct platform_device *pdev) | |||
| 167 | void __iomem *usb_base; | 164 | void __iomem *usb_base; |
| 168 | void __iomem *usbother_base; | 165 | void __iomem *usbother_base; |
| 169 | 166 | ||
| 170 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); | 167 | usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); |
| 171 | if (!usb_base) | 168 | if (!usb_base) |
| 172 | return -ENOMEM; | 169 | return -ENOMEM; |
| 173 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; | 170 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; |
| @@ -190,7 +187,7 @@ static int initialize_usbh1_port(struct platform_device *pdev) | |||
| 190 | void __iomem *usb_base; | 187 | void __iomem *usb_base; |
| 191 | void __iomem *usbother_base; | 188 | void __iomem *usbother_base; |
| 192 | 189 | ||
| 193 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); | 190 | usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); |
| 194 | if (!usb_base) | 191 | if (!usb_base) |
| 195 | return -ENOMEM; | 192 | return -ENOMEM; |
| 196 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; | 193 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; |
| @@ -206,17 +203,17 @@ static int initialize_usbh1_port(struct platform_device *pdev) | |||
| 206 | MXC_EHCI_ITC_NO_THRESHOLD); | 203 | MXC_EHCI_ITC_NO_THRESHOLD); |
| 207 | } | 204 | } |
| 208 | 205 | ||
| 209 | static struct mxc_usbh_platform_data dr_utmi_config = { | 206 | static const struct mxc_usbh_platform_data dr_utmi_config __initconst = { |
| 210 | .init = initialize_otg_port, | 207 | .init = initialize_otg_port, |
| 211 | .portsc = MXC_EHCI_UTMI_16BIT, | 208 | .portsc = MXC_EHCI_UTMI_16BIT, |
| 212 | }; | 209 | }; |
| 213 | 210 | ||
| 214 | static struct fsl_usb2_platform_data usb_pdata = { | 211 | static const struct fsl_usb2_platform_data usb_pdata __initconst = { |
| 215 | .operating_mode = FSL_USB2_DR_DEVICE, | 212 | .operating_mode = FSL_USB2_DR_DEVICE, |
| 216 | .phy_mode = FSL_USB2_PHY_UTMI_WIDE, | 213 | .phy_mode = FSL_USB2_PHY_UTMI_WIDE, |
| 217 | }; | 214 | }; |
| 218 | 215 | ||
| 219 | static struct mxc_usbh_platform_data usbh1_config = { | 216 | static const struct mxc_usbh_platform_data usbh1_config __initconst = { |
| 220 | .init = initialize_usbh1_port, | 217 | .init = initialize_usbh1_port, |
| 221 | .portsc = MXC_EHCI_MODE_ULPI, | 218 | .portsc = MXC_EHCI_MODE_ULPI, |
| 222 | }; | 219 | }; |
| @@ -270,12 +267,12 @@ static void __init eukrea_cpuimx51_init(void) | |||
| 270 | ARRAY_SIZE(eukrea_cpuimx51_i2c_devices)); | 267 | ARRAY_SIZE(eukrea_cpuimx51_i2c_devices)); |
| 271 | 268 | ||
| 272 | if (otg_mode_host) | 269 | if (otg_mode_host) |
| 273 | mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); | 270 | imx51_add_mxc_ehci_otg(&dr_utmi_config); |
| 274 | else { | 271 | else { |
| 275 | initialize_otg_port(NULL); | 272 | initialize_otg_port(NULL); |
| 276 | mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata); | 273 | imx51_add_fsl_usb2_udc(&usb_pdata); |
| 277 | } | 274 | } |
| 278 | mxc_register_device(&mxc_usbh1_device, &usbh1_config); | 275 | imx51_add_mxc_ehci_hs(1, &usbh1_config); |
| 279 | 276 | ||
| 280 | #ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD | 277 | #ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD |
| 281 | eukrea_mbimx51_baseboard_init(); | 278 | eukrea_mbimx51_baseboard_init(); |
| @@ -297,6 +294,7 @@ MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module") | |||
| 297 | .map_io = mx51_map_io, | 294 | .map_io = mx51_map_io, |
| 298 | .init_early = imx51_init_early, | 295 | .init_early = imx51_init_early, |
| 299 | .init_irq = mx51_init_irq, | 296 | .init_irq = mx51_init_irq, |
| 297 | .handle_irq = imx51_handle_irq, | ||
| 300 | .timer = &mxc_timer, | 298 | .timer = &mxc_timer, |
| 301 | .init_machine = eukrea_cpuimx51_init, | 299 | .init_machine = eukrea_cpuimx51_init, |
| 302 | MACHINE_END | 300 | MACHINE_END |
diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c index ff096d587299..5276660041ad 100644 --- a/arch/arm/mach-mx5/board-cpuimx51sd.c +++ b/arch/arm/mach-mx5/board-cpuimx51sd.c | |||
| @@ -22,7 +22,6 @@ | |||
| 22 | #include <linux/delay.h> | 22 | #include <linux/delay.h> |
| 23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
| 24 | #include <linux/interrupt.h> | 24 | #include <linux/interrupt.h> |
| 25 | #include <linux/irq.h> | ||
| 26 | #include <linux/i2c-gpio.h> | 25 | #include <linux/i2c-gpio.h> |
| 27 | #include <linux/spi/spi.h> | 26 | #include <linux/spi/spi.h> |
| 28 | #include <linux/can/platform/mcp251x.h> | 27 | #include <linux/can/platform/mcp251x.h> |
| @@ -32,14 +31,12 @@ | |||
| 32 | #include <mach/hardware.h> | 31 | #include <mach/hardware.h> |
| 33 | #include <mach/iomux-mx51.h> | 32 | #include <mach/iomux-mx51.h> |
| 34 | 33 | ||
| 35 | #include <asm/irq.h> | ||
| 36 | #include <asm/setup.h> | 34 | #include <asm/setup.h> |
| 37 | #include <asm/mach-types.h> | 35 | #include <asm/mach-types.h> |
| 38 | #include <asm/mach/arch.h> | 36 | #include <asm/mach/arch.h> |
| 39 | #include <asm/mach/time.h> | 37 | #include <asm/mach/time.h> |
| 40 | 38 | ||
| 41 | #include "devices-imx51.h" | 39 | #include "devices-imx51.h" |
| 42 | #include "devices.h" | ||
| 43 | #include "cpu_op-mx51.h" | 40 | #include "cpu_op-mx51.h" |
| 44 | 41 | ||
| 45 | #define USBH1_RST IMX_GPIO_NR(2, 28) | 42 | #define USBH1_RST IMX_GPIO_NR(2, 28) |
| @@ -108,7 +105,7 @@ static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = { | |||
| 108 | 105 | ||
| 109 | /* Touchscreen */ | 106 | /* Touchscreen */ |
| 110 | /* IRQ */ | 107 | /* IRQ */ |
| 111 | _MX51_PAD_GPIO_NAND__GPIO_NAND | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | | 108 | NEW_PAD_CTRL(MX51_PAD_GPIO_NAND__GPIO_NAND, PAD_CTL_PUS_22K_UP | |
| 112 | PAD_CTL_PKE | PAD_CTL_SRE_FAST | | 109 | PAD_CTL_PKE | PAD_CTL_SRE_FAST | |
| 113 | PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS), | 110 | PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS), |
| 114 | }; | 111 | }; |
| @@ -129,7 +126,7 @@ static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = { | |||
| 129 | I2C_BOARD_INFO("tsc2007", 0x49), | 126 | I2C_BOARD_INFO("tsc2007", 0x49), |
| 130 | .type = "tsc2007", | 127 | .type = "tsc2007", |
| 131 | .platform_data = &tsc2007_info, | 128 | .platform_data = &tsc2007_info, |
| 132 | .irq = gpio_to_irq(TSC2007_IRQGPIO), | 129 | .irq = IMX_GPIO_TO_IRQ(TSC2007_IRQGPIO), |
| 133 | }, | 130 | }, |
| 134 | }; | 131 | }; |
| 135 | 132 | ||
| @@ -149,7 +146,7 @@ static int initialize_otg_port(struct platform_device *pdev) | |||
| 149 | void __iomem *usb_base; | 146 | void __iomem *usb_base; |
| 150 | void __iomem *usbother_base; | 147 | void __iomem *usbother_base; |
| 151 | 148 | ||
| 152 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); | 149 | usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); |
| 153 | if (!usb_base) | 150 | if (!usb_base) |
| 154 | return -ENOMEM; | 151 | return -ENOMEM; |
| 155 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; | 152 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; |
| @@ -172,7 +169,7 @@ static int initialize_usbh1_port(struct platform_device *pdev) | |||
| 172 | void __iomem *usb_base; | 169 | void __iomem *usb_base; |
| 173 | void __iomem *usbother_base; | 170 | void __iomem *usbother_base; |
| 174 | 171 | ||
| 175 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); | 172 | usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); |
| 176 | if (!usb_base) | 173 | if (!usb_base) |
| 177 | return -ENOMEM; | 174 | return -ENOMEM; |
| 178 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; | 175 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; |
| @@ -189,17 +186,17 @@ static int initialize_usbh1_port(struct platform_device *pdev) | |||
| 189 | MXC_EHCI_ITC_NO_THRESHOLD); | 186 | MXC_EHCI_ITC_NO_THRESHOLD); |
| 190 | } | 187 | } |
| 191 | 188 | ||
| 192 | static struct mxc_usbh_platform_data dr_utmi_config = { | 189 | static const struct mxc_usbh_platform_data dr_utmi_config __initconst = { |
| 193 | .init = initialize_otg_port, | 190 | .init = initialize_otg_port, |
| 194 | .portsc = MXC_EHCI_UTMI_16BIT, | 191 | .portsc = MXC_EHCI_UTMI_16BIT, |
| 195 | }; | 192 | }; |
| 196 | 193 | ||
| 197 | static struct fsl_usb2_platform_data usb_pdata = { | 194 | static const struct fsl_usb2_platform_data usb_pdata __initconst = { |
| 198 | .operating_mode = FSL_USB2_DR_DEVICE, | 195 | .operating_mode = FSL_USB2_DR_DEVICE, |
| 199 | .phy_mode = FSL_USB2_PHY_UTMI_WIDE, | 196 | .phy_mode = FSL_USB2_PHY_UTMI_WIDE, |
| 200 | }; | 197 | }; |
| 201 | 198 | ||
| 202 | static struct mxc_usbh_platform_data usbh1_config = { | 199 | static const struct mxc_usbh_platform_data usbh1_config __initconst = { |
| 203 | .init = initialize_usbh1_port, | 200 | .init = initialize_usbh1_port, |
| 204 | .portsc = MXC_EHCI_MODE_ULPI, | 201 | .portsc = MXC_EHCI_MODE_ULPI, |
| 205 | }; | 202 | }; |
| @@ -245,7 +242,7 @@ static struct spi_board_info cpuimx51sd_spi_device[] = { | |||
| 245 | .mode = SPI_MODE_0, | 242 | .mode = SPI_MODE_0, |
| 246 | .chip_select = 0, | 243 | .chip_select = 0, |
| 247 | .platform_data = &mcp251x_info, | 244 | .platform_data = &mcp251x_info, |
| 248 | .irq = gpio_to_irq(CAN_IRQGPIO) | 245 | .irq = IMX_GPIO_TO_IRQ(CAN_IRQGPIO) |
| 249 | }, | 246 | }, |
| 250 | }; | 247 | }; |
| 251 | 248 | ||
| @@ -303,17 +300,17 @@ static void __init eukrea_cpuimx51sd_init(void) | |||
| 303 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); | 300 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); |
| 304 | 301 | ||
| 305 | if (otg_mode_host) | 302 | if (otg_mode_host) |
| 306 | mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); | 303 | imx51_add_mxc_ehci_otg(&dr_utmi_config); |
| 307 | else { | 304 | else { |
| 308 | initialize_otg_port(NULL); | 305 | initialize_otg_port(NULL); |
| 309 | mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata); | 306 | imx51_add_fsl_usb2_udc(&usb_pdata); |
| 310 | } | 307 | } |
| 311 | 308 | ||
| 312 | gpio_request(USBH1_RST, "usb_rst"); | 309 | gpio_request(USBH1_RST, "usb_rst"); |
| 313 | gpio_direction_output(USBH1_RST, 0); | 310 | gpio_direction_output(USBH1_RST, 0); |
| 314 | msleep(20); | 311 | msleep(20); |
| 315 | gpio_set_value(USBH1_RST, 1); | 312 | gpio_set_value(USBH1_RST, 1); |
| 316 | mxc_register_device(&mxc_usbh1_device, &usbh1_config); | 313 | imx51_add_mxc_ehci_hs(1, &usbh1_config); |
| 317 | 314 | ||
| 318 | #ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD | 315 | #ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD |
| 319 | eukrea_mbimxsd51_baseboard_init(); | 316 | eukrea_mbimxsd51_baseboard_init(); |
| @@ -335,6 +332,7 @@ MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD") | |||
| 335 | .map_io = mx51_map_io, | 332 | .map_io = mx51_map_io, |
| 336 | .init_early = imx51_init_early, | 333 | .init_early = imx51_init_early, |
| 337 | .init_irq = mx51_init_irq, | 334 | .init_irq = mx51_init_irq, |
| 335 | .handle_irq = imx51_handle_irq, | ||
| 338 | .timer = &mxc_timer, | 336 | .timer = &mxc_timer, |
| 339 | .init_machine = eukrea_cpuimx51sd_init, | 337 | .init_machine = eukrea_cpuimx51sd_init, |
| 340 | MACHINE_END | 338 | MACHINE_END |
diff --git a/arch/arm/mach-mx5/board-mx50_rdp.c b/arch/arm/mach-mx5/board-mx50_rdp.c index 7de25c6712eb..fc3621d90bde 100644 --- a/arch/arm/mach-mx5/board-mx50_rdp.c +++ b/arch/arm/mach-mx5/board-mx50_rdp.c | |||
| @@ -219,6 +219,7 @@ MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform") | |||
| 219 | .map_io = mx50_map_io, | 219 | .map_io = mx50_map_io, |
| 220 | .init_early = imx50_init_early, | 220 | .init_early = imx50_init_early, |
| 221 | .init_irq = mx50_init_irq, | 221 | .init_irq = mx50_init_irq, |
| 222 | .handle_irq = imx50_handle_irq, | ||
| 222 | .timer = &mx50_rdp_timer, | 223 | .timer = &mx50_rdp_timer, |
| 223 | .init_machine = mx50_rdp_board_init, | 224 | .init_machine = mx50_rdp_board_init, |
| 224 | MACHINE_END | 225 | MACHINE_END |
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c index 07a38154da21..067d8c4eb656 100644 --- a/arch/arm/mach-mx5/board-mx51_3ds.c +++ b/arch/arm/mach-mx5/board-mx51_3ds.c | |||
| @@ -25,7 +25,6 @@ | |||
| 25 | #include <mach/3ds_debugboard.h> | 25 | #include <mach/3ds_debugboard.h> |
| 26 | 26 | ||
| 27 | #include "devices-imx51.h" | 27 | #include "devices-imx51.h" |
| 28 | #include "devices.h" | ||
| 29 | 28 | ||
| 30 | #define EXPIO_PARENT_INT gpio_to_irq(IMX_GPIO_NR(1, 6)) | 29 | #define EXPIO_PARENT_INT gpio_to_irq(IMX_GPIO_NR(1, 6)) |
| 31 | #define MX51_3DS_ECSPI2_CS (GPIO_PORTC + 28) | 30 | #define MX51_3DS_ECSPI2_CS (GPIO_PORTC + 28) |
| @@ -173,6 +172,7 @@ MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board") | |||
| 173 | .map_io = mx51_map_io, | 172 | .map_io = mx51_map_io, |
| 174 | .init_early = imx51_init_early, | 173 | .init_early = imx51_init_early, |
| 175 | .init_irq = mx51_init_irq, | 174 | .init_irq = mx51_init_irq, |
| 175 | .handle_irq = imx51_handle_irq, | ||
| 176 | .timer = &mx51_3ds_timer, | 176 | .timer = &mx51_3ds_timer, |
| 177 | .init_machine = mx51_3ds_init, | 177 | .init_machine = mx51_3ds_init, |
| 178 | MACHINE_END | 178 | MACHINE_END |
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c index 11b0ff67f89d..4231d984579c 100644 --- a/arch/arm/mach-mx5/board-mx51_babbage.c +++ b/arch/arm/mach-mx5/board-mx51_babbage.c | |||
| @@ -24,14 +24,12 @@ | |||
| 24 | #include <mach/hardware.h> | 24 | #include <mach/hardware.h> |
| 25 | #include <mach/iomux-mx51.h> | 25 | #include <mach/iomux-mx51.h> |
| 26 | 26 | ||
| 27 | #include <asm/irq.h> | ||
| 28 | #include <asm/setup.h> | 27 | #include <asm/setup.h> |
| 29 | #include <asm/mach-types.h> | 28 | #include <asm/mach-types.h> |
| 30 | #include <asm/mach/arch.h> | 29 | #include <asm/mach/arch.h> |
| 31 | #include <asm/mach/time.h> | 30 | #include <asm/mach/time.h> |
| 32 | 31 | ||
| 33 | #include "devices-imx51.h" | 32 | #include "devices-imx51.h" |
| 34 | #include "devices.h" | ||
| 35 | #include "cpu_op-mx51.h" | 33 | #include "cpu_op-mx51.h" |
| 36 | 34 | ||
| 37 | #define BABBAGE_USB_HUB_RESET IMX_GPIO_NR(1, 7) | 35 | #define BABBAGE_USB_HUB_RESET IMX_GPIO_NR(1, 7) |
| @@ -176,7 +174,7 @@ static const struct imxi2c_platform_data babbage_i2c_data __initconst = { | |||
| 176 | .bitrate = 100000, | 174 | .bitrate = 100000, |
| 177 | }; | 175 | }; |
| 178 | 176 | ||
| 179 | static struct imxi2c_platform_data babbage_hsi2c_data = { | 177 | static const struct imxi2c_platform_data babbage_hsi2c_data __initconst = { |
| 180 | .bitrate = 400000, | 178 | .bitrate = 400000, |
| 181 | }; | 179 | }; |
| 182 | 180 | ||
| @@ -249,7 +247,7 @@ static int initialize_otg_port(struct platform_device *pdev) | |||
| 249 | void __iomem *usb_base; | 247 | void __iomem *usb_base; |
| 250 | void __iomem *usbother_base; | 248 | void __iomem *usbother_base; |
| 251 | 249 | ||
| 252 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); | 250 | usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); |
| 253 | if (!usb_base) | 251 | if (!usb_base) |
| 254 | return -ENOMEM; | 252 | return -ENOMEM; |
| 255 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; | 253 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; |
| @@ -272,7 +270,7 @@ static int initialize_usbh1_port(struct platform_device *pdev) | |||
| 272 | void __iomem *usb_base; | 270 | void __iomem *usb_base; |
| 273 | void __iomem *usbother_base; | 271 | void __iomem *usbother_base; |
| 274 | 272 | ||
| 275 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); | 273 | usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); |
| 276 | if (!usb_base) | 274 | if (!usb_base) |
| 277 | return -ENOMEM; | 275 | return -ENOMEM; |
| 278 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; | 276 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; |
| @@ -288,17 +286,17 @@ static int initialize_usbh1_port(struct platform_device *pdev) | |||
| 288 | MXC_EHCI_ITC_NO_THRESHOLD); | 286 | MXC_EHCI_ITC_NO_THRESHOLD); |
| 289 | } | 287 | } |
| 290 | 288 | ||
| 291 | static struct mxc_usbh_platform_data dr_utmi_config = { | 289 | static const struct mxc_usbh_platform_data dr_utmi_config __initconst = { |
| 292 | .init = initialize_otg_port, | 290 | .init = initialize_otg_port, |
| 293 | .portsc = MXC_EHCI_UTMI_16BIT, | 291 | .portsc = MXC_EHCI_UTMI_16BIT, |
| 294 | }; | 292 | }; |
| 295 | 293 | ||
| 296 | static struct fsl_usb2_platform_data usb_pdata = { | 294 | static const struct fsl_usb2_platform_data usb_pdata __initconst = { |
| 297 | .operating_mode = FSL_USB2_DR_DEVICE, | 295 | .operating_mode = FSL_USB2_DR_DEVICE, |
| 298 | .phy_mode = FSL_USB2_PHY_UTMI_WIDE, | 296 | .phy_mode = FSL_USB2_PHY_UTMI_WIDE, |
| 299 | }; | 297 | }; |
| 300 | 298 | ||
| 301 | static struct mxc_usbh_platform_data usbh1_config = { | 299 | static const struct mxc_usbh_platform_data usbh1_config __initconst = { |
| 302 | .init = initialize_usbh1_port, | 300 | .init = initialize_usbh1_port, |
| 303 | .portsc = MXC_EHCI_MODE_ULPI, | 301 | .portsc = MXC_EHCI_MODE_ULPI, |
| 304 | }; | 302 | }; |
| @@ -357,8 +355,8 @@ static const struct esdhc_platform_data mx51_babbage_sd2_data __initconst = { | |||
| 357 | static void __init mx51_babbage_init(void) | 355 | static void __init mx51_babbage_init(void) |
| 358 | { | 356 | { |
| 359 | iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP; | 357 | iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP; |
| 360 | iomux_v3_cfg_t power_key = _MX51_PAD_EIM_A27__GPIO2_21 | | 358 | iomux_v3_cfg_t power_key = NEW_PAD_CTRL(MX51_PAD_EIM_A27__GPIO2_21, |
| 361 | MUX_PAD_CTRL(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP); | 359 | PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP); |
| 362 | 360 | ||
| 363 | imx51_soc_init(); | 361 | imx51_soc_init(); |
| 364 | 362 | ||
| @@ -381,17 +379,17 @@ static void __init mx51_babbage_init(void) | |||
| 381 | 379 | ||
| 382 | imx51_add_imx_i2c(0, &babbage_i2c_data); | 380 | imx51_add_imx_i2c(0, &babbage_i2c_data); |
| 383 | imx51_add_imx_i2c(1, &babbage_i2c_data); | 381 | imx51_add_imx_i2c(1, &babbage_i2c_data); |
| 384 | mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data); | 382 | imx51_add_hsi2c(&babbage_hsi2c_data); |
| 385 | 383 | ||
| 386 | if (otg_mode_host) | 384 | if (otg_mode_host) |
| 387 | mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); | 385 | imx51_add_mxc_ehci_otg(&dr_utmi_config); |
| 388 | else { | 386 | else { |
| 389 | initialize_otg_port(NULL); | 387 | initialize_otg_port(NULL); |
| 390 | mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata); | 388 | imx51_add_fsl_usb2_udc(&usb_pdata); |
| 391 | } | 389 | } |
| 392 | 390 | ||
| 393 | gpio_usbh1_active(); | 391 | gpio_usbh1_active(); |
| 394 | mxc_register_device(&mxc_usbh1_device, &usbh1_config); | 392 | imx51_add_mxc_ehci_hs(1, &usbh1_config); |
| 395 | /* setback USBH1_STP to be function */ | 393 | /* setback USBH1_STP to be function */ |
| 396 | mxc_iomux_v3_setup_pad(usbh1stp); | 394 | mxc_iomux_v3_setup_pad(usbh1stp); |
| 397 | babbage_usbhub_reset(); | 395 | babbage_usbhub_reset(); |
| @@ -420,6 +418,7 @@ MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board") | |||
| 420 | .map_io = mx51_map_io, | 418 | .map_io = mx51_map_io, |
| 421 | .init_early = imx51_init_early, | 419 | .init_early = imx51_init_early, |
| 422 | .init_irq = mx51_init_irq, | 420 | .init_irq = mx51_init_irq, |
| 421 | .handle_irq = imx51_handle_irq, | ||
| 423 | .timer = &mx51_babbage_timer, | 422 | .timer = &mx51_babbage_timer, |
| 424 | .init_machine = mx51_babbage_init, | 423 | .init_machine = mx51_babbage_init, |
| 425 | MACHINE_END | 424 | MACHINE_END |
diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c index 551daf85ff8c..90ae903aaee7 100644 --- a/arch/arm/mach-mx5/board-mx51_efikamx.c +++ b/arch/arm/mach-mx5/board-mx51_efikamx.c | |||
| @@ -32,14 +32,12 @@ | |||
| 32 | #include <mach/hardware.h> | 32 | #include <mach/hardware.h> |
| 33 | #include <mach/iomux-mx51.h> | 33 | #include <mach/iomux-mx51.h> |
| 34 | 34 | ||
| 35 | #include <asm/irq.h> | ||
| 36 | #include <asm/setup.h> | 35 | #include <asm/setup.h> |
| 37 | #include <asm/mach-types.h> | 36 | #include <asm/mach-types.h> |
| 38 | #include <asm/mach/arch.h> | 37 | #include <asm/mach/arch.h> |
| 39 | #include <asm/mach/time.h> | 38 | #include <asm/mach/time.h> |
| 40 | 39 | ||
| 41 | #include "devices-imx51.h" | 40 | #include "devices-imx51.h" |
| 42 | #include "devices.h" | ||
| 43 | #include "efika.h" | 41 | #include "efika.h" |
| 44 | 42 | ||
| 45 | #define EFIKAMX_PCBID0 IMX_GPIO_NR(3, 16) | 43 | #define EFIKAMX_PCBID0 IMX_GPIO_NR(3, 16) |
| @@ -163,6 +161,11 @@ static const struct gpio_led_platform_data | |||
| 163 | .num_leds = ARRAY_SIZE(mx51_efikamx_leds), | 161 | .num_leds = ARRAY_SIZE(mx51_efikamx_leds), |
| 164 | }; | 162 | }; |
| 165 | 163 | ||
| 164 | static struct esdhc_platform_data sd_pdata = { | ||
| 165 | .cd_type = ESDHC_CD_CONTROLLER, | ||
| 166 | .wp_type = ESDHC_WP_CONTROLLER, | ||
| 167 | }; | ||
| 168 | |||
| 166 | static struct gpio_keys_button mx51_efikamx_powerkey[] = { | 169 | static struct gpio_keys_button mx51_efikamx_powerkey[] = { |
| 167 | { | 170 | { |
| 168 | .code = KEY_POWER, | 171 | .code = KEY_POWER, |
| @@ -239,9 +242,11 @@ static void __init mx51_efikamx_init(void) | |||
| 239 | 242 | ||
| 240 | /* on < 1.2 boards both SD controllers are used */ | 243 | /* on < 1.2 boards both SD controllers are used */ |
| 241 | if (system_rev < 0x12) { | 244 | if (system_rev < 0x12) { |
| 242 | imx51_add_sdhci_esdhc_imx(1, NULL); | 245 | imx51_add_sdhci_esdhc_imx(0, NULL); |
| 246 | imx51_add_sdhci_esdhc_imx(1, &sd_pdata); | ||
| 243 | mx51_efikamx_leds[2].default_trigger = "mmc1"; | 247 | mx51_efikamx_leds[2].default_trigger = "mmc1"; |
| 244 | } | 248 | } else |
| 249 | imx51_add_sdhci_esdhc_imx(0, &sd_pdata); | ||
| 245 | 250 | ||
| 246 | gpio_led_register_device(-1, &mx51_efikamx_leds_data); | 251 | gpio_led_register_device(-1, &mx51_efikamx_leds_data); |
| 247 | imx_add_gpio_keys(&mx51_efikamx_powerkey_data); | 252 | imx_add_gpio_keys(&mx51_efikamx_powerkey_data); |
| @@ -284,6 +289,7 @@ MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop") | |||
| 284 | .map_io = mx51_map_io, | 289 | .map_io = mx51_map_io, |
| 285 | .init_early = imx51_init_early, | 290 | .init_early = imx51_init_early, |
| 286 | .init_irq = mx51_init_irq, | 291 | .init_irq = mx51_init_irq, |
| 292 | .handle_irq = imx51_handle_irq, | ||
| 287 | .timer = &mx51_efikamx_timer, | 293 | .timer = &mx51_efikamx_timer, |
| 288 | .init_machine = mx51_efikamx_init, | 294 | .init_machine = mx51_efikamx_init, |
| 289 | MACHINE_END | 295 | MACHINE_END |
diff --git a/arch/arm/mach-mx5/board-mx51_efikasb.c b/arch/arm/mach-mx5/board-mx51_efikasb.c index 8a9bca22beb5..c26508a6708e 100644 --- a/arch/arm/mach-mx5/board-mx51_efikasb.c +++ b/arch/arm/mach-mx5/board-mx51_efikasb.c | |||
| @@ -35,14 +35,12 @@ | |||
| 35 | #include <mach/hardware.h> | 35 | #include <mach/hardware.h> |
| 36 | #include <mach/iomux-mx51.h> | 36 | #include <mach/iomux-mx51.h> |
| 37 | 37 | ||
| 38 | #include <asm/irq.h> | ||
| 39 | #include <asm/setup.h> | 38 | #include <asm/setup.h> |
| 40 | #include <asm/mach-types.h> | 39 | #include <asm/mach-types.h> |
| 41 | #include <asm/mach/arch.h> | 40 | #include <asm/mach/arch.h> |
| 42 | #include <asm/mach/time.h> | 41 | #include <asm/mach/time.h> |
| 43 | 42 | ||
| 44 | #include "devices-imx51.h" | 43 | #include "devices-imx51.h" |
| 45 | #include "devices.h" | ||
| 46 | #include "efika.h" | 44 | #include "efika.h" |
| 47 | 45 | ||
| 48 | #define EFIKASB_USBH2_STP IMX_GPIO_NR(2, 20) | 46 | #define EFIKASB_USBH2_STP IMX_GPIO_NR(2, 20) |
| @@ -56,6 +54,7 @@ | |||
| 56 | #define EFIKASB_RFKILL IMX_GPIO_NR(3, 1) | 54 | #define EFIKASB_RFKILL IMX_GPIO_NR(3, 1) |
| 57 | 55 | ||
| 58 | #define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE) | 56 | #define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE) |
| 57 | #define MX51_PAD_SD1_CD IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_ESDHC_PAD_CTRL) | ||
| 59 | 58 | ||
| 60 | static iomux_v3_cfg_t mx51efikasb_pads[] = { | 59 | static iomux_v3_cfg_t mx51efikasb_pads[] = { |
| 61 | /* USB HOST2 */ | 60 | /* USB HOST2 */ |
| @@ -97,6 +96,8 @@ static iomux_v3_cfg_t mx51efikasb_pads[] = { | |||
| 97 | 96 | ||
| 98 | /* BT */ | 97 | /* BT */ |
| 99 | MX51_PAD_EIM_A17__GPIO2_11, | 98 | MX51_PAD_EIM_A17__GPIO2_11, |
| 99 | |||
| 100 | MX51_PAD_SD1_CD, | ||
| 100 | }; | 101 | }; |
| 101 | 102 | ||
| 102 | static int initialize_usbh2_port(struct platform_device *pdev) | 103 | static int initialize_usbh2_port(struct platform_device *pdev) |
| @@ -119,7 +120,7 @@ static int initialize_usbh2_port(struct platform_device *pdev) | |||
| 119 | return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD); | 120 | return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD); |
| 120 | } | 121 | } |
| 121 | 122 | ||
| 122 | static struct mxc_usbh_platform_data usbh2_config = { | 123 | static struct mxc_usbh_platform_data usbh2_config __initdata = { |
| 123 | .init = initialize_usbh2_port, | 124 | .init = initialize_usbh2_port, |
| 124 | .portsc = MXC_EHCI_MODE_ULPI, | 125 | .portsc = MXC_EHCI_MODE_ULPI, |
| 125 | }; | 126 | }; |
| @@ -129,7 +130,7 @@ static void __init mx51_efikasb_usb(void) | |||
| 129 | usbh2_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | | 130 | usbh2_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | |
| 130 | ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND); | 131 | ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND); |
| 131 | if (usbh2_config.otg) | 132 | if (usbh2_config.otg) |
| 132 | mxc_register_device(&mxc_usbh2_device, &usbh2_config); | 133 | imx51_add_mxc_ehci_hs(2, &usbh2_config); |
| 133 | } | 134 | } |
| 134 | 135 | ||
| 135 | static const struct gpio_led mx51_efikasb_leds[] __initconst = { | 136 | static const struct gpio_led mx51_efikasb_leds[] __initconst = { |
| @@ -182,6 +183,18 @@ static const struct gpio_keys_platform_data mx51_efikasb_keys_data __initconst = | |||
| 182 | .nbuttons = ARRAY_SIZE(mx51_efikasb_keys), | 183 | .nbuttons = ARRAY_SIZE(mx51_efikasb_keys), |
| 183 | }; | 184 | }; |
| 184 | 185 | ||
| 186 | static struct esdhc_platform_data sd0_pdata = { | ||
| 187 | #define EFIKASB_SD1_CD IMX_GPIO_NR(2, 27) | ||
| 188 | .cd_gpio = EFIKASB_SD1_CD, | ||
| 189 | .cd_type = ESDHC_CD_GPIO, | ||
| 190 | .wp_type = ESDHC_WP_CONTROLLER, | ||
| 191 | }; | ||
| 192 | |||
| 193 | static struct esdhc_platform_data sd1_pdata = { | ||
| 194 | .cd_type = ESDHC_CD_CONTROLLER, | ||
| 195 | .wp_type = ESDHC_WP_CONTROLLER, | ||
| 196 | }; | ||
| 197 | |||
| 185 | static struct regulator *pwgt1, *pwgt2; | 198 | static struct regulator *pwgt1, *pwgt2; |
| 186 | 199 | ||
| 187 | static void mx51_efikasb_power_off(void) | 200 | static void mx51_efikasb_power_off(void) |
| @@ -250,7 +263,8 @@ static void __init efikasb_board_init(void) | |||
| 250 | 263 | ||
| 251 | mx51_efikasb_board_id(); | 264 | mx51_efikasb_board_id(); |
| 252 | mx51_efikasb_usb(); | 265 | mx51_efikasb_usb(); |
| 253 | imx51_add_sdhci_esdhc_imx(1, NULL); | 266 | imx51_add_sdhci_esdhc_imx(0, &sd0_pdata); |
| 267 | imx51_add_sdhci_esdhc_imx(1, &sd1_pdata); | ||
| 254 | 268 | ||
| 255 | gpio_led_register_device(-1, &mx51_efikasb_leds_data); | 269 | gpio_led_register_device(-1, &mx51_efikasb_leds_data); |
| 256 | imx_add_gpio_keys(&mx51_efikasb_keys_data); | 270 | imx_add_gpio_keys(&mx51_efikasb_keys_data); |
| @@ -270,6 +284,7 @@ MACHINE_START(MX51_EFIKASB, "Genesi Efika Smartbook") | |||
| 270 | .map_io = mx51_map_io, | 284 | .map_io = mx51_map_io, |
| 271 | .init_early = imx51_init_early, | 285 | .init_early = imx51_init_early, |
| 272 | .init_irq = mx51_init_irq, | 286 | .init_irq = mx51_init_irq, |
| 287 | .handle_irq = imx51_handle_irq, | ||
| 273 | .init_machine = efikasb_board_init, | 288 | .init_machine = efikasb_board_init, |
| 274 | .timer = &mx51_efikasb_timer, | 289 | .timer = &mx51_efikasb_timer, |
| 275 | MACHINE_END | 290 | MACHINE_END |
diff --git a/arch/arm/mach-mx5/board-mx53_ard.c b/arch/arm/mach-mx5/board-mx53_ard.c index 76a67c4a2a0b..cb4d753c6c95 100644 --- a/arch/arm/mach-mx5/board-mx53_ard.c +++ b/arch/arm/mach-mx5/board-mx53_ard.c | |||
| @@ -134,8 +134,8 @@ static struct resource ard_smsc911x_resources[] = { | |||
| 134 | .flags = IORESOURCE_MEM, | 134 | .flags = IORESOURCE_MEM, |
| 135 | }, | 135 | }, |
| 136 | { | 136 | { |
| 137 | .start = gpio_to_irq(ARD_ETHERNET_INT_B), | 137 | .start = IMX_GPIO_TO_IRQ(ARD_ETHERNET_INT_B), |
| 138 | .end = gpio_to_irq(ARD_ETHERNET_INT_B), | 138 | .end = IMX_GPIO_TO_IRQ(ARD_ETHERNET_INT_B), |
| 139 | .flags = IORESOURCE_IRQ, | 139 | .flags = IORESOURCE_IRQ, |
| 140 | }, | 140 | }, |
| 141 | }; | 141 | }; |
| @@ -249,6 +249,7 @@ MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board") | |||
| 249 | .map_io = mx53_map_io, | 249 | .map_io = mx53_map_io, |
| 250 | .init_early = imx53_init_early, | 250 | .init_early = imx53_init_early, |
| 251 | .init_irq = mx53_init_irq, | 251 | .init_irq = mx53_init_irq, |
| 252 | .handle_irq = imx53_handle_irq, | ||
| 252 | .timer = &mx53_ard_timer, | 253 | .timer = &mx53_ard_timer, |
| 253 | .init_machine = mx53_ard_board_init, | 254 | .init_machine = mx53_ard_board_init, |
| 254 | MACHINE_END | 255 | MACHINE_END |
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c index 1b417b06b736..6a3e6168e322 100644 --- a/arch/arm/mach-mx5/board-mx53_evk.c +++ b/arch/arm/mach-mx5/board-mx53_evk.c | |||
| @@ -167,6 +167,7 @@ MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board") | |||
| 167 | .map_io = mx53_map_io, | 167 | .map_io = mx53_map_io, |
| 168 | .init_early = imx53_init_early, | 168 | .init_early = imx53_init_early, |
| 169 | .init_irq = mx53_init_irq, | 169 | .init_irq = mx53_init_irq, |
| 170 | .handle_irq = imx53_handle_irq, | ||
| 170 | .timer = &mx53_evk_timer, | 171 | .timer = &mx53_evk_timer, |
| 171 | .init_machine = mx53_evk_board_init, | 172 | .init_machine = mx53_evk_board_init, |
| 172 | MACHINE_END | 173 | MACHINE_END |
diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c index 4e1d51d252dc..7149416d1519 100644 --- a/arch/arm/mach-mx5/board-mx53_loco.c +++ b/arch/arm/mach-mx5/board-mx53_loco.c | |||
| @@ -22,6 +22,7 @@ | |||
| 22 | #include <linux/clk.h> | 22 | #include <linux/clk.h> |
| 23 | #include <linux/delay.h> | 23 | #include <linux/delay.h> |
| 24 | #include <linux/gpio.h> | 24 | #include <linux/gpio.h> |
| 25 | #include <linux/i2c.h> | ||
| 25 | 26 | ||
| 26 | #include <mach/common.h> | 27 | #include <mach/common.h> |
| 27 | #include <mach/hardware.h> | 28 | #include <mach/hardware.h> |
| @@ -42,6 +43,7 @@ | |||
| 42 | #define LOCO_SD3_CD IMX_GPIO_NR(3, 11) | 43 | #define LOCO_SD3_CD IMX_GPIO_NR(3, 11) |
| 43 | #define LOCO_SD3_WP IMX_GPIO_NR(3, 12) | 44 | #define LOCO_SD3_WP IMX_GPIO_NR(3, 12) |
| 44 | #define LOCO_SD1_CD IMX_GPIO_NR(3, 13) | 45 | #define LOCO_SD1_CD IMX_GPIO_NR(3, 13) |
| 46 | #define LOCO_ACCEL_EN IMX_GPIO_NR(6, 14) | ||
| 45 | 47 | ||
| 46 | static iomux_v3_cfg_t mx53_loco_pads[] = { | 48 | static iomux_v3_cfg_t mx53_loco_pads[] = { |
| 47 | /* FEC */ | 49 | /* FEC */ |
| @@ -64,6 +66,10 @@ static iomux_v3_cfg_t mx53_loco_pads[] = { | |||
| 64 | MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD, | 66 | MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD, |
| 65 | MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS, | 67 | MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS, |
| 66 | MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD, | 68 | MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD, |
| 69 | /* I2C1 */ | ||
| 70 | MX53_PAD_CSI0_DAT8__I2C1_SDA, | ||
| 71 | MX53_PAD_CSI0_DAT9__I2C1_SCL, | ||
| 72 | MX53_PAD_NANDF_CS1__GPIO6_14, /* Accelerometer Enable */ | ||
| 67 | /* I2C2 */ | 73 | /* I2C2 */ |
| 68 | MX53_PAD_KEY_COL3__I2C2_SCL, | 74 | MX53_PAD_KEY_COL3__I2C2_SCL, |
| 69 | MX53_PAD_KEY_ROW3__I2C2_SDA, | 75 | MX53_PAD_KEY_ROW3__I2C2_SDA, |
| @@ -257,8 +263,15 @@ static const struct gpio_led_platform_data mx53loco_leds_data __initconst = { | |||
| 257 | .num_leds = ARRAY_SIZE(mx53loco_leds), | 263 | .num_leds = ARRAY_SIZE(mx53loco_leds), |
| 258 | }; | 264 | }; |
| 259 | 265 | ||
| 266 | static struct i2c_board_info mx53loco_i2c_devices[] = { | ||
| 267 | { | ||
| 268 | I2C_BOARD_INFO("mma8450", 0x1C), | ||
| 269 | }, | ||
| 270 | }; | ||
| 271 | |||
| 260 | static void __init mx53_loco_board_init(void) | 272 | static void __init mx53_loco_board_init(void) |
| 261 | { | 273 | { |
| 274 | int ret; | ||
| 262 | imx53_soc_init(); | 275 | imx53_soc_init(); |
| 263 | 276 | ||
| 264 | mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads, | 277 | mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads, |
| @@ -267,6 +280,13 @@ static void __init mx53_loco_board_init(void) | |||
| 267 | mx53_loco_fec_reset(); | 280 | mx53_loco_fec_reset(); |
| 268 | imx53_add_fec(&mx53_loco_fec_data); | 281 | imx53_add_fec(&mx53_loco_fec_data); |
| 269 | imx53_add_imx2_wdt(0, NULL); | 282 | imx53_add_imx2_wdt(0, NULL); |
| 283 | |||
| 284 | ret = gpio_request_one(LOCO_ACCEL_EN, GPIOF_OUT_INIT_HIGH, "accel_en"); | ||
| 285 | if (ret) | ||
| 286 | pr_err("Cannot request ACCEL_EN pin: %d\n", ret); | ||
| 287 | |||
| 288 | i2c_register_board_info(0, mx53loco_i2c_devices, | ||
| 289 | ARRAY_SIZE(mx53loco_i2c_devices)); | ||
| 270 | imx53_add_imx_i2c(0, &mx53_loco_i2c_data); | 290 | imx53_add_imx_i2c(0, &mx53_loco_i2c_data); |
| 271 | imx53_add_imx_i2c(1, &mx53_loco_i2c_data); | 291 | imx53_add_imx_i2c(1, &mx53_loco_i2c_data); |
| 272 | imx53_add_sdhci_esdhc_imx(0, &mx53_loco_sd1_data); | 292 | imx53_add_sdhci_esdhc_imx(0, &mx53_loco_sd1_data); |
| @@ -288,6 +308,7 @@ MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board") | |||
| 288 | .map_io = mx53_map_io, | 308 | .map_io = mx53_map_io, |
| 289 | .init_early = imx53_init_early, | 309 | .init_early = imx53_init_early, |
| 290 | .init_irq = mx53_init_irq, | 310 | .init_irq = mx53_init_irq, |
| 311 | .handle_irq = imx53_handle_irq, | ||
| 291 | .timer = &mx53_loco_timer, | 312 | .timer = &mx53_loco_timer, |
| 292 | .init_machine = mx53_loco_board_init, | 313 | .init_machine = mx53_loco_board_init, |
| 293 | MACHINE_END | 314 | MACHINE_END |
diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c index bc02894eafef..e64fd2c088eb 100644 --- a/arch/arm/mach-mx5/board-mx53_smd.c +++ b/arch/arm/mach-mx5/board-mx53_smd.c | |||
| @@ -140,6 +140,7 @@ MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board") | |||
| 140 | .map_io = mx53_map_io, | 140 | .map_io = mx53_map_io, |
| 141 | .init_early = imx53_init_early, | 141 | .init_early = imx53_init_early, |
| 142 | .init_irq = mx53_init_irq, | 142 | .init_irq = mx53_init_irq, |
| 143 | .handle_irq = imx53_handle_irq, | ||
| 143 | .timer = &mx53_smd_timer, | 144 | .timer = &mx53_smd_timer, |
| 144 | .init_machine = mx53_smd_board_init, | 145 | .init_machine = mx53_smd_board_init, |
| 145 | MACHINE_END | 146 | MACHINE_END |
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c index f7bf996f463b..2b9bd1fabaf9 100644 --- a/arch/arm/mach-mx5/clock-mx51-mx53.c +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c | |||
| @@ -1418,6 +1418,10 @@ DEFINE_CLOCK(ipu_di0_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG5_OFFSET, | |||
| 1418 | DEFINE_CLOCK(ipu_di1_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG6_OFFSET, | 1418 | DEFINE_CLOCK(ipu_di1_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG6_OFFSET, |
| 1419 | NULL, NULL, &pll3_sw_clk, NULL); | 1419 | NULL, NULL, &pll3_sw_clk, NULL); |
| 1420 | 1420 | ||
| 1421 | /* PATA */ | ||
| 1422 | DEFINE_CLOCK(pata_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG0_OFFSET, | ||
| 1423 | NULL, NULL, &ipg_clk, &spba_clk); | ||
| 1424 | |||
| 1421 | #define _REGISTER_CLOCK(d, n, c) \ | 1425 | #define _REGISTER_CLOCK(d, n, c) \ |
| 1422 | { \ | 1426 | { \ |
| 1423 | .dev_id = d, \ | 1427 | .dev_id = d, \ |
| @@ -1474,6 +1478,7 @@ static struct clk_lookup mx51_lookups[] = { | |||
| 1474 | _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk) | 1478 | _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk) |
| 1475 | _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk) | 1479 | _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk) |
| 1476 | _REGISTER_CLOCK(NULL, "gpc_dvfs", gpc_dvfs_clk) | 1480 | _REGISTER_CLOCK(NULL, "gpc_dvfs", gpc_dvfs_clk) |
| 1481 | _REGISTER_CLOCK("pata_imx", NULL, pata_clk) | ||
| 1477 | }; | 1482 | }; |
| 1478 | 1483 | ||
| 1479 | static struct clk_lookup mx53_lookups[] = { | 1484 | static struct clk_lookup mx53_lookups[] = { |
| @@ -1507,6 +1512,7 @@ static struct clk_lookup mx53_lookups[] = { | |||
| 1507 | _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) | 1512 | _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) |
| 1508 | _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk) | 1513 | _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk) |
| 1509 | _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk) | 1514 | _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk) |
| 1515 | _REGISTER_CLOCK("pata_imx", NULL, pata_clk) | ||
| 1510 | }; | 1516 | }; |
| 1511 | 1517 | ||
| 1512 | static void clk_tree_init(void) | 1518 | static void clk_tree_init(void) |
| @@ -1548,9 +1554,8 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, | |||
| 1548 | clk_enable(&main_bus_clk); | 1554 | clk_enable(&main_bus_clk); |
| 1549 | 1555 | ||
| 1550 | clk_enable(&iim_clk); | 1556 | clk_enable(&iim_clk); |
| 1551 | mx51_revision(); | 1557 | imx_print_silicon_rev("i.MX51", mx51_revision()); |
| 1552 | clk_disable(&iim_clk); | 1558 | clk_disable(&iim_clk); |
| 1553 | mx51_display_revision(); | ||
| 1554 | 1559 | ||
| 1555 | /* move usb_phy_clk to 24MHz */ | 1560 | /* move usb_phy_clk to 24MHz */ |
| 1556 | clk_set_parent(&usb_phy1_clk, &osc_clk); | 1561 | clk_set_parent(&usb_phy1_clk, &osc_clk); |
| @@ -1568,7 +1573,7 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, | |||
| 1568 | 1573 | ||
| 1569 | /* System timer */ | 1574 | /* System timer */ |
| 1570 | mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), | 1575 | mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), |
| 1571 | MX51_MXC_INT_GPT); | 1576 | MX51_INT_GPT); |
| 1572 | return 0; | 1577 | return 0; |
| 1573 | } | 1578 | } |
| 1574 | 1579 | ||
| @@ -1592,9 +1597,8 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, | |||
| 1592 | clk_enable(&main_bus_clk); | 1597 | clk_enable(&main_bus_clk); |
| 1593 | 1598 | ||
| 1594 | clk_enable(&iim_clk); | 1599 | clk_enable(&iim_clk); |
| 1595 | mx53_revision(); | 1600 | imx_print_silicon_rev("i.MX53", mx53_revision()); |
| 1596 | clk_disable(&iim_clk); | 1601 | clk_disable(&iim_clk); |
| 1597 | mx53_display_revision(); | ||
| 1598 | 1602 | ||
| 1599 | /* Set SDHC parents to be PLL2 */ | 1603 | /* Set SDHC parents to be PLL2 */ |
| 1600 | clk_set_parent(&esdhc1_clk, &pll2_sw_clk); | 1604 | clk_set_parent(&esdhc1_clk, &pll2_sw_clk); |
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c index 86f87da59c64..5c5328257dca 100644 --- a/arch/arm/mach-mx5/cpu.c +++ b/arch/arm/mach-mx5/cpu.c | |||
| @@ -18,7 +18,7 @@ | |||
| 18 | #include <mach/hardware.h> | 18 | #include <mach/hardware.h> |
| 19 | #include <asm/io.h> | 19 | #include <asm/io.h> |
| 20 | 20 | ||
| 21 | static int cpu_silicon_rev = -1; | 21 | static int mx5_cpu_rev = -1; |
| 22 | 22 | ||
| 23 | #define IIM_SREV 0x24 | 23 | #define IIM_SREV 0x24 |
| 24 | #define MX50_HW_ADADIG_DIGPROG 0xB0 | 24 | #define MX50_HW_ADADIG_DIGPROG 0xB0 |
| @@ -28,11 +28,14 @@ static int get_mx51_srev(void) | |||
| 28 | void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR); | 28 | void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR); |
| 29 | u32 rev = readl(iim_base + IIM_SREV) & 0xff; | 29 | u32 rev = readl(iim_base + IIM_SREV) & 0xff; |
| 30 | 30 | ||
| 31 | if (rev == 0x0) | 31 | switch (rev) { |
| 32 | case 0x0: | ||
| 32 | return IMX_CHIP_REVISION_2_0; | 33 | return IMX_CHIP_REVISION_2_0; |
| 33 | else if (rev == 0x10) | 34 | case 0x10: |
| 34 | return IMX_CHIP_REVISION_3_0; | 35 | return IMX_CHIP_REVISION_3_0; |
| 35 | return 0; | 36 | default: |
| 37 | return IMX_CHIP_REVISION_UNKNOWN; | ||
| 38 | } | ||
| 36 | } | 39 | } |
| 37 | 40 | ||
| 38 | /* | 41 | /* |
| @@ -45,33 +48,13 @@ int mx51_revision(void) | |||
| 45 | if (!cpu_is_mx51()) | 48 | if (!cpu_is_mx51()) |
| 46 | return -EINVAL; | 49 | return -EINVAL; |
| 47 | 50 | ||
| 48 | if (cpu_silicon_rev == -1) | 51 | if (mx5_cpu_rev == -1) |
| 49 | cpu_silicon_rev = get_mx51_srev(); | 52 | mx5_cpu_rev = get_mx51_srev(); |
| 50 | 53 | ||
| 51 | return cpu_silicon_rev; | 54 | return mx5_cpu_rev; |
| 52 | } | 55 | } |
| 53 | EXPORT_SYMBOL(mx51_revision); | 56 | EXPORT_SYMBOL(mx51_revision); |
| 54 | 57 | ||
| 55 | void mx51_display_revision(void) | ||
| 56 | { | ||
| 57 | int rev; | ||
| 58 | char *srev; | ||
| 59 | rev = mx51_revision(); | ||
| 60 | |||
| 61 | switch (rev) { | ||
| 62 | case IMX_CHIP_REVISION_2_0: | ||
| 63 | srev = IMX_CHIP_REVISION_2_0_STRING; | ||
| 64 | break; | ||
| 65 | case IMX_CHIP_REVISION_3_0: | ||
| 66 | srev = IMX_CHIP_REVISION_3_0_STRING; | ||
| 67 | break; | ||
| 68 | default: | ||
| 69 | srev = IMX_CHIP_REVISION_UNKNOWN_STRING; | ||
| 70 | } | ||
| 71 | printk(KERN_INFO "CPU identified as i.MX51, silicon rev %s\n", srev); | ||
| 72 | } | ||
| 73 | EXPORT_SYMBOL(mx51_display_revision); | ||
| 74 | |||
| 75 | #ifdef CONFIG_NEON | 58 | #ifdef CONFIG_NEON |
| 76 | 59 | ||
| 77 | /* | 60 | /* |
| @@ -121,10 +104,10 @@ int mx53_revision(void) | |||
| 121 | if (!cpu_is_mx53()) | 104 | if (!cpu_is_mx53()) |
| 122 | return -EINVAL; | 105 | return -EINVAL; |
| 123 | 106 | ||
| 124 | if (cpu_silicon_rev == -1) | 107 | if (mx5_cpu_rev == -1) |
| 125 | cpu_silicon_rev = get_mx53_srev(); | 108 | mx5_cpu_rev = get_mx53_srev(); |
| 126 | 109 | ||
| 127 | return cpu_silicon_rev; | 110 | return mx5_cpu_rev; |
| 128 | } | 111 | } |
| 129 | EXPORT_SYMBOL(mx53_revision); | 112 | EXPORT_SYMBOL(mx53_revision); |
| 130 | 113 | ||
| @@ -134,7 +117,7 @@ static int get_mx50_srev(void) | |||
| 134 | u32 rev; | 117 | u32 rev; |
| 135 | 118 | ||
| 136 | if (!anatop) { | 119 | if (!anatop) { |
| 137 | cpu_silicon_rev = -EINVAL; | 120 | mx5_cpu_rev = -EINVAL; |
| 138 | return 0; | 121 | return 0; |
| 139 | } | 122 | } |
| 140 | 123 | ||
| @@ -159,36 +142,13 @@ int mx50_revision(void) | |||
| 159 | if (!cpu_is_mx50()) | 142 | if (!cpu_is_mx50()) |
| 160 | return -EINVAL; | 143 | return -EINVAL; |
| 161 | 144 | ||
| 162 | if (cpu_silicon_rev == -1) | 145 | if (mx5_cpu_rev == -1) |
| 163 | cpu_silicon_rev = get_mx50_srev(); | 146 | mx5_cpu_rev = get_mx50_srev(); |
| 164 | 147 | ||
| 165 | return cpu_silicon_rev; | 148 | return mx5_cpu_rev; |
| 166 | } | 149 | } |
| 167 | EXPORT_SYMBOL(mx50_revision); | 150 | EXPORT_SYMBOL(mx50_revision); |
| 168 | 151 | ||
| 169 | void mx53_display_revision(void) | ||
| 170 | { | ||
| 171 | int rev; | ||
| 172 | char *srev; | ||
| 173 | rev = mx53_revision(); | ||
| 174 | |||
| 175 | switch (rev) { | ||
| 176 | case IMX_CHIP_REVISION_1_0: | ||
| 177 | srev = IMX_CHIP_REVISION_1_0_STRING; | ||
| 178 | break; | ||
| 179 | case IMX_CHIP_REVISION_2_0: | ||
| 180 | srev = IMX_CHIP_REVISION_2_0_STRING; | ||
| 181 | break; | ||
| 182 | case IMX_CHIP_REVISION_2_1: | ||
| 183 | srev = IMX_CHIP_REVISION_2_1_STRING; | ||
| 184 | break; | ||
| 185 | default: | ||
| 186 | srev = IMX_CHIP_REVISION_UNKNOWN_STRING; | ||
| 187 | } | ||
| 188 | printk(KERN_INFO "CPU identified as i.MX53, silicon rev %s\n", srev); | ||
| 189 | } | ||
| 190 | EXPORT_SYMBOL(mx53_display_revision); | ||
| 191 | |||
| 192 | static int __init post_cpu_init(void) | 152 | static int __init post_cpu_init(void) |
| 193 | { | 153 | { |
| 194 | unsigned int reg; | 154 | unsigned int reg; |
diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h index e11bc0e0ec49..af488bc0e225 100644 --- a/arch/arm/mach-mx5/devices-imx51.h +++ b/arch/arm/mach-mx5/devices-imx51.h | |||
| @@ -13,9 +13,15 @@ extern const struct imx_fec_data imx51_fec_data; | |||
| 13 | #define imx51_add_fec(pdata) \ | 13 | #define imx51_add_fec(pdata) \ |
| 14 | imx_add_fec(&imx51_fec_data, pdata) | 14 | imx_add_fec(&imx51_fec_data, pdata) |
| 15 | 15 | ||
| 16 | extern const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data; | ||
| 17 | #define imx51_add_fsl_usb2_udc(pdata) \ | ||
| 18 | imx_add_fsl_usb2_udc(&imx51_fsl_usb2_udc_data, pdata) | ||
| 19 | |||
| 16 | extern const struct imx_imx_i2c_data imx51_imx_i2c_data[]; | 20 | extern const struct imx_imx_i2c_data imx51_imx_i2c_data[]; |
| 17 | #define imx51_add_imx_i2c(id, pdata) \ | 21 | #define imx51_add_imx_i2c(id, pdata) \ |
| 18 | imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata) | 22 | imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata) |
| 23 | #define imx51_add_hsi2c(pdata) \ | ||
| 24 | imx51_add_imx_i2c(2, pdata) | ||
| 19 | 25 | ||
| 20 | extern const struct imx_imx_ssi_data imx51_imx_ssi_data[]; | 26 | extern const struct imx_imx_ssi_data imx51_imx_ssi_data[]; |
| 21 | #define imx51_add_imx_ssi(id, pdata) \ | 27 | #define imx51_add_imx_ssi(id, pdata) \ |
| @@ -25,6 +31,13 @@ extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[]; | |||
| 25 | #define imx51_add_imx_uart(id, pdata) \ | 31 | #define imx51_add_imx_uart(id, pdata) \ |
| 26 | imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata) | 32 | imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata) |
| 27 | 33 | ||
| 34 | extern const struct imx_mxc_ehci_data imx51_mxc_ehci_otg_data; | ||
| 35 | #define imx51_add_mxc_ehci_otg(pdata) \ | ||
| 36 | imx_add_mxc_ehci(&imx51_mxc_ehci_otg_data, pdata) | ||
| 37 | extern const struct imx_mxc_ehci_data imx51_mxc_ehci_hs_data[]; | ||
| 38 | #define imx51_add_mxc_ehci_hs(id, pdata) \ | ||
| 39 | imx_add_mxc_ehci(&imx51_mxc_ehci_hs_data[id - 1], pdata) | ||
| 40 | |||
| 28 | extern const struct imx_mxc_nand_data imx51_mxc_nand_data; | 41 | extern const struct imx_mxc_nand_data imx51_mxc_nand_data; |
| 29 | #define imx51_add_mxc_nand(pdata) \ | 42 | #define imx51_add_mxc_nand(pdata) \ |
| 30 | imx_add_mxc_nand(&imx51_mxc_nand_data, pdata) | 43 | imx_add_mxc_nand(&imx51_mxc_nand_data, pdata) |
| @@ -52,3 +65,7 @@ extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[]; | |||
| 52 | extern const struct imx_imx_keypad_data imx51_imx_keypad_data; | 65 | extern const struct imx_imx_keypad_data imx51_imx_keypad_data; |
| 53 | #define imx51_add_imx_keypad(pdata) \ | 66 | #define imx51_add_imx_keypad(pdata) \ |
| 54 | imx_add_imx_keypad(&imx51_imx_keypad_data, pdata) | 67 | imx_add_imx_keypad(&imx51_imx_keypad_data, pdata) |
| 68 | |||
| 69 | extern const struct imx_pata_imx_data imx51_pata_imx_data; | ||
| 70 | #define imx51_add_pata_imx() \ | ||
| 71 | imx_add_pata_imx(&imx51_pata_imx_data) | ||
diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h index c27fe8bb4762..7ca5d0c76f8b 100644 --- a/arch/arm/mach-mx5/devices-imx53.h +++ b/arch/arm/mach-mx5/devices-imx53.h | |||
| @@ -40,3 +40,7 @@ extern const struct imx_imx_ssi_data imx53_imx_ssi_data[]; | |||
| 40 | extern const struct imx_imx_keypad_data imx53_imx_keypad_data; | 40 | extern const struct imx_imx_keypad_data imx53_imx_keypad_data; |
| 41 | #define imx53_add_imx_keypad(pdata) \ | 41 | #define imx53_add_imx_keypad(pdata) \ |
| 42 | imx_add_imx_keypad(&imx53_imx_keypad_data, pdata) | 42 | imx_add_imx_keypad(&imx53_imx_keypad_data, pdata) |
| 43 | |||
| 44 | extern const struct imx_pata_imx_data imx53_pata_imx_data; | ||
| 45 | #define imx53_add_pata_imx() \ | ||
| 46 | imx_add_pata_imx(&imx53_pata_imx_data) | ||
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c deleted file mode 100644 index 371ca8c8414c..000000000000 --- a/arch/arm/mach-mx5/devices.c +++ /dev/null | |||
| @@ -1,120 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2009 Amit Kucheria <amit.kucheria@canonical.com> | ||
| 3 | * Copyright (C) 2010 Freescale Semiconductor, Inc. | ||
| 4 | * | ||
| 5 | * The code contained herein is licensed under the GNU General Public | ||
| 6 | * License. You may obtain a copy of the GNU General Public License | ||
| 7 | * Version 2 or later at the following locations: | ||
| 8 | * | ||
| 9 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 10 | * http://www.gnu.org/copyleft/gpl.html | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/platform_device.h> | ||
| 14 | #include <linux/dma-mapping.h> | ||
| 15 | #include <mach/hardware.h> | ||
| 16 | #include <mach/imx-uart.h> | ||
| 17 | #include <mach/irqs.h> | ||
| 18 | |||
| 19 | static struct resource mxc_hsi2c_resources[] = { | ||
| 20 | { | ||
| 21 | .start = MX51_HSI2C_DMA_BASE_ADDR, | ||
| 22 | .end = MX51_HSI2C_DMA_BASE_ADDR + SZ_16K - 1, | ||
| 23 | .flags = IORESOURCE_MEM, | ||
| 24 | }, | ||
| 25 | { | ||
| 26 | .start = MX51_MXC_INT_HS_I2C, | ||
| 27 | .end = MX51_MXC_INT_HS_I2C, | ||
| 28 | .flags = IORESOURCE_IRQ, | ||
| 29 | }, | ||
| 30 | }; | ||
| 31 | |||
| 32 | struct platform_device mxc_hsi2c_device = { | ||
| 33 | .name = "imx-i2c", | ||
| 34 | .id = 2, | ||
| 35 | .num_resources = ARRAY_SIZE(mxc_hsi2c_resources), | ||
| 36 | .resource = mxc_hsi2c_resources | ||
| 37 | }; | ||
| 38 | |||
| 39 | static u64 usb_dma_mask = DMA_BIT_MASK(32); | ||
| 40 | |||
| 41 | static struct resource usbotg_resources[] = { | ||
| 42 | { | ||
| 43 | .start = MX51_OTG_BASE_ADDR, | ||
| 44 | .end = MX51_OTG_BASE_ADDR + 0x1ff, | ||
| 45 | .flags = IORESOURCE_MEM, | ||
| 46 | }, | ||
| 47 | { | ||
| 48 | .start = MX51_MXC_INT_USB_OTG, | ||
| 49 | .flags = IORESOURCE_IRQ, | ||
| 50 | }, | ||
| 51 | }; | ||
| 52 | |||
| 53 | /* OTG gadget device */ | ||
| 54 | struct platform_device mxc_usbdr_udc_device = { | ||
| 55 | .name = "fsl-usb2-udc", | ||
| 56 | .id = -1, | ||
| 57 | .num_resources = ARRAY_SIZE(usbotg_resources), | ||
| 58 | .resource = usbotg_resources, | ||
| 59 | .dev = { | ||
| 60 | .dma_mask = &usb_dma_mask, | ||
| 61 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 62 | }, | ||
| 63 | }; | ||
| 64 | |||
| 65 | struct platform_device mxc_usbdr_host_device = { | ||
| 66 | .name = "mxc-ehci", | ||
| 67 | .id = 0, | ||
| 68 | .num_resources = ARRAY_SIZE(usbotg_resources), | ||
| 69 | .resource = usbotg_resources, | ||
| 70 | .dev = { | ||
| 71 | .dma_mask = &usb_dma_mask, | ||
| 72 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 73 | }, | ||
| 74 | }; | ||
| 75 | |||
| 76 | static struct resource usbh1_resources[] = { | ||
| 77 | { | ||
| 78 | .start = MX51_OTG_BASE_ADDR + 0x200, | ||
| 79 | .end = MX51_OTG_BASE_ADDR + 0x200 + 0x1ff, | ||
| 80 | .flags = IORESOURCE_MEM, | ||
| 81 | }, | ||
| 82 | { | ||
| 83 | .start = MX51_MXC_INT_USB_H1, | ||
| 84 | .flags = IORESOURCE_IRQ, | ||
| 85 | }, | ||
| 86 | }; | ||
| 87 | |||
| 88 | struct platform_device mxc_usbh1_device = { | ||
| 89 | .name = "mxc-ehci", | ||
| 90 | .id = 1, | ||
| 91 | .num_resources = ARRAY_SIZE(usbh1_resources), | ||
| 92 | .resource = usbh1_resources, | ||
| 93 | .dev = { | ||
| 94 | .dma_mask = &usb_dma_mask, | ||
| 95 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 96 | }, | ||
| 97 | }; | ||
| 98 | |||
| 99 | static struct resource usbh2_resources[] = { | ||
| 100 | { | ||
| 101 | .start = MX51_OTG_BASE_ADDR + 0x400, | ||
| 102 | .end = MX51_OTG_BASE_ADDR + 0x400 + 0x1ff, | ||
| 103 | .flags = IORESOURCE_MEM, | ||
| 104 | }, | ||
| 105 | { | ||
| 106 | .start = MX51_MXC_INT_USB_H2, | ||
| 107 | .flags = IORESOURCE_IRQ, | ||
| 108 | }, | ||
| 109 | }; | ||
| 110 | |||
| 111 | struct platform_device mxc_usbh2_device = { | ||
| 112 | .name = "mxc-ehci", | ||
| 113 | .id = 2, | ||
| 114 | .num_resources = ARRAY_SIZE(usbh2_resources), | ||
| 115 | .resource = usbh2_resources, | ||
| 116 | .dev = { | ||
| 117 | .dma_mask = &usb_dma_mask, | ||
| 118 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 119 | }, | ||
| 120 | }; | ||
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h deleted file mode 100644 index 55a5129bc29f..000000000000 --- a/arch/arm/mach-mx5/devices.h +++ /dev/null | |||
| @@ -1,5 +0,0 @@ | |||
| 1 | extern struct platform_device mxc_usbdr_host_device; | ||
| 2 | extern struct platform_device mxc_usbh1_device; | ||
| 3 | extern struct platform_device mxc_usbh2_device; | ||
| 4 | extern struct platform_device mxc_usbdr_udc_device; | ||
| 5 | extern struct platform_device mxc_hsi2c_device; | ||
diff --git a/arch/arm/mach-mx5/ehci.c b/arch/arm/mach-mx5/ehci.c index 7ce12c804a32..c17fa131728b 100644 --- a/arch/arm/mach-mx5/ehci.c +++ b/arch/arm/mach-mx5/ehci.c | |||
| @@ -52,7 +52,7 @@ int mx51_initialize_usb_hw(int port, unsigned int flags) | |||
| 52 | void __iomem *usbother_base; | 52 | void __iomem *usbother_base; |
| 53 | int ret = 0; | 53 | int ret = 0; |
| 54 | 54 | ||
| 55 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); | 55 | usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); |
| 56 | if (!usb_base) { | 56 | if (!usb_base) { |
| 57 | printk(KERN_ERR "%s(): ioremap failed\n", __func__); | 57 | printk(KERN_ERR "%s(): ioremap failed\n", __func__); |
| 58 | return -ENOMEM; | 58 | return -ENOMEM; |
diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c index bbf4564bd050..a6a3ab8f1b1c 100644 --- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c +++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c | |||
| @@ -28,7 +28,6 @@ | |||
| 28 | #include <asm/mach/arch.h> | 28 | #include <asm/mach/arch.h> |
| 29 | 29 | ||
| 30 | #include "devices-imx51.h" | 30 | #include "devices-imx51.h" |
| 31 | #include "devices.h" | ||
| 32 | 31 | ||
| 33 | #define MBIMX51_TSC2007_GPIO IMX_GPIO_NR(3, 30) | 32 | #define MBIMX51_TSC2007_GPIO IMX_GPIO_NR(3, 30) |
| 34 | #define MBIMX51_LED0 IMX_GPIO_NR(3, 5) | 33 | #define MBIMX51_LED0 IMX_GPIO_NR(3, 5) |
| @@ -160,7 +159,7 @@ struct tsc2007_platform_data tsc2007_data = { | |||
| 160 | static struct i2c_board_info mbimx51_i2c_devices[] = { | 159 | static struct i2c_board_info mbimx51_i2c_devices[] = { |
| 161 | { | 160 | { |
| 162 | I2C_BOARD_INFO("tsc2007", 0x49), | 161 | I2C_BOARD_INFO("tsc2007", 0x49), |
| 163 | .irq = gpio_to_irq(MBIMX51_TSC2007_GPIO), | 162 | .irq = IMX_GPIO_TO_IRQ(MBIMX51_TSC2007_GPIO), |
| 164 | .platform_data = &tsc2007_data, | 163 | .platform_data = &tsc2007_data, |
| 165 | }, { | 164 | }, { |
| 166 | I2C_BOARD_INFO("tlv320aic23", 0x1a), | 165 | I2C_BOARD_INFO("tlv320aic23", 0x1a), |
diff --git a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c index 261923997643..d817fc80b986 100644 --- a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c +++ b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c | |||
| @@ -24,7 +24,6 @@ | |||
| 24 | 24 | ||
| 25 | #include <linux/gpio.h> | 25 | #include <linux/gpio.h> |
| 26 | #include <linux/interrupt.h> | 26 | #include <linux/interrupt.h> |
| 27 | #include <linux/irq.h> | ||
| 28 | #include <linux/leds.h> | 27 | #include <linux/leds.h> |
| 29 | #include <linux/platform_device.h> | 28 | #include <linux/platform_device.h> |
| 30 | #include <linux/input.h> | 29 | #include <linux/input.h> |
| @@ -41,13 +40,12 @@ | |||
| 41 | #include <mach/audmux.h> | 40 | #include <mach/audmux.h> |
| 42 | 41 | ||
| 43 | #include "devices-imx51.h" | 42 | #include "devices-imx51.h" |
| 44 | #include "devices.h" | ||
| 45 | 43 | ||
| 46 | static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = { | 44 | static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = { |
| 47 | /* LED */ | 45 | /* LED */ |
| 48 | MX51_PAD_NANDF_D10__GPIO3_30, | 46 | MX51_PAD_NANDF_D10__GPIO3_30, |
| 49 | /* SWITCH */ | 47 | /* SWITCH */ |
| 50 | _MX51_PAD_NANDF_D9__GPIO3_31 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | | 48 | NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, PAD_CTL_PUS_22K_UP | |
| 51 | PAD_CTL_PKE | PAD_CTL_SRE_FAST | | 49 | PAD_CTL_PKE | PAD_CTL_SRE_FAST | |
| 52 | PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS), | 50 | PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS), |
| 53 | /* UART2 */ | 51 | /* UART2 */ |
| @@ -66,7 +64,7 @@ static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = { | |||
| 66 | MX51_PAD_SD1_DATA2__SD1_DATA2, | 64 | MX51_PAD_SD1_DATA2__SD1_DATA2, |
| 67 | MX51_PAD_SD1_DATA3__SD1_DATA3, | 65 | MX51_PAD_SD1_DATA3__SD1_DATA3, |
| 68 | /* SD1 CD */ | 66 | /* SD1 CD */ |
| 69 | _MX51_PAD_GPIO1_0__SD1_CD | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | | 67 | NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_PUS_22K_UP | |
| 70 | PAD_CTL_PKE | PAD_CTL_SRE_FAST | | 68 | PAD_CTL_PKE | PAD_CTL_SRE_FAST | |
| 71 | PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS), | 69 | PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS), |
| 72 | }; | 70 | }; |
diff --git a/arch/arm/mach-mx5/mm-mx50.c b/arch/arm/mach-mx5/mm-mx50.c deleted file mode 100644 index 77e374c726fa..000000000000 --- a/arch/arm/mach-mx5/mm-mx50.c +++ /dev/null | |||
| @@ -1,72 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | |||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | |||
| 14 | * You should have received a copy of the GNU General Public License along | ||
| 15 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
| 17 | * | ||
| 18 | * Create static mapping between physical to virtual memory. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include <linux/mm.h> | ||
| 22 | #include <linux/init.h> | ||
| 23 | |||
| 24 | #include <asm/mach/map.h> | ||
| 25 | |||
| 26 | #include <mach/hardware.h> | ||
| 27 | #include <mach/common.h> | ||
| 28 | #include <mach/iomux-v3.h> | ||
| 29 | #include <mach/irqs.h> | ||
| 30 | |||
| 31 | /* | ||
| 32 | * Define the MX50 memory map. | ||
| 33 | */ | ||
| 34 | static struct map_desc mx50_io_desc[] __initdata = { | ||
| 35 | imx_map_entry(MX50, TZIC, MT_DEVICE), | ||
| 36 | imx_map_entry(MX50, SPBA0, MT_DEVICE), | ||
| 37 | imx_map_entry(MX50, AIPS1, MT_DEVICE), | ||
| 38 | imx_map_entry(MX50, AIPS2, MT_DEVICE), | ||
| 39 | }; | ||
| 40 | |||
| 41 | /* | ||
| 42 | * This function initializes the memory map. It is called during the | ||
| 43 | * system startup to create static physical to virtual memory mappings | ||
| 44 | * for the IO modules. | ||
| 45 | */ | ||
| 46 | void __init mx50_map_io(void) | ||
| 47 | { | ||
| 48 | iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc)); | ||
| 49 | } | ||
| 50 | |||
| 51 | void __init imx50_init_early(void) | ||
| 52 | { | ||
| 53 | mxc_set_cpu_type(MXC_CPU_MX50); | ||
| 54 | mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR)); | ||
| 55 | mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR)); | ||
| 56 | } | ||
| 57 | |||
| 58 | void __init mx50_init_irq(void) | ||
| 59 | { | ||
| 60 | tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR)); | ||
| 61 | } | ||
| 62 | |||
| 63 | void __init imx50_soc_init(void) | ||
| 64 | { | ||
| 65 | /* i.mx50 has the i.mx31 type gpio */ | ||
| 66 | mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH); | ||
| 67 | mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH); | ||
| 68 | mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH); | ||
| 69 | mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH); | ||
| 70 | mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH); | ||
| 71 | mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH); | ||
| 72 | } | ||
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c index baea6e5cddd9..26eacc9d0d90 100644 --- a/arch/arm/mach-mx5/mm.c +++ b/arch/arm/mach-mx5/mm.c | |||
| @@ -21,12 +21,27 @@ | |||
| 21 | #include <mach/devices-common.h> | 21 | #include <mach/devices-common.h> |
| 22 | #include <mach/iomux-v3.h> | 22 | #include <mach/iomux-v3.h> |
| 23 | 23 | ||
| 24 | static void imx5_idle(void) | ||
| 25 | { | ||
| 26 | mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); | ||
| 27 | } | ||
| 28 | |||
| 29 | /* | ||
| 30 | * Define the MX50 memory map. | ||
| 31 | */ | ||
| 32 | static struct map_desc mx50_io_desc[] __initdata = { | ||
| 33 | imx_map_entry(MX50, TZIC, MT_DEVICE), | ||
| 34 | imx_map_entry(MX50, SPBA0, MT_DEVICE), | ||
| 35 | imx_map_entry(MX50, AIPS1, MT_DEVICE), | ||
| 36 | imx_map_entry(MX50, AIPS2, MT_DEVICE), | ||
| 37 | }; | ||
| 38 | |||
| 24 | /* | 39 | /* |
| 25 | * Define the MX51 memory map. | 40 | * Define the MX51 memory map. |
| 26 | */ | 41 | */ |
| 27 | static struct map_desc mx51_io_desc[] __initdata = { | 42 | static struct map_desc mx51_io_desc[] __initdata = { |
| 43 | imx_map_entry(MX51, TZIC, MT_DEVICE), | ||
| 28 | imx_map_entry(MX51, IRAM, MT_DEVICE), | 44 | imx_map_entry(MX51, IRAM, MT_DEVICE), |
| 29 | imx_map_entry(MX51, DEBUG, MT_DEVICE), | ||
| 30 | imx_map_entry(MX51, AIPS1, MT_DEVICE), | 45 | imx_map_entry(MX51, AIPS1, MT_DEVICE), |
| 31 | imx_map_entry(MX51, SPBA0, MT_DEVICE), | 46 | imx_map_entry(MX51, SPBA0, MT_DEVICE), |
| 32 | imx_map_entry(MX51, AIPS2, MT_DEVICE), | 47 | imx_map_entry(MX51, AIPS2, MT_DEVICE), |
| @@ -36,6 +51,7 @@ static struct map_desc mx51_io_desc[] __initdata = { | |||
| 36 | * Define the MX53 memory map. | 51 | * Define the MX53 memory map. |
| 37 | */ | 52 | */ |
| 38 | static struct map_desc mx53_io_desc[] __initdata = { | 53 | static struct map_desc mx53_io_desc[] __initdata = { |
| 54 | imx_map_entry(MX53, TZIC, MT_DEVICE), | ||
| 39 | imx_map_entry(MX53, AIPS1, MT_DEVICE), | 55 | imx_map_entry(MX53, AIPS1, MT_DEVICE), |
| 40 | imx_map_entry(MX53, SPBA0, MT_DEVICE), | 56 | imx_map_entry(MX53, SPBA0, MT_DEVICE), |
| 41 | imx_map_entry(MX53, AIPS2, MT_DEVICE), | 57 | imx_map_entry(MX53, AIPS2, MT_DEVICE), |
| @@ -46,21 +62,34 @@ static struct map_desc mx53_io_desc[] __initdata = { | |||
| 46 | * system startup to create static physical to virtual memory mappings | 62 | * system startup to create static physical to virtual memory mappings |
| 47 | * for the IO modules. | 63 | * for the IO modules. |
| 48 | */ | 64 | */ |
| 65 | void __init mx50_map_io(void) | ||
| 66 | { | ||
| 67 | iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc)); | ||
| 68 | } | ||
| 69 | |||
| 49 | void __init mx51_map_io(void) | 70 | void __init mx51_map_io(void) |
| 50 | { | 71 | { |
| 51 | iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc)); | 72 | iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc)); |
| 52 | } | 73 | } |
| 53 | 74 | ||
| 75 | void __init mx53_map_io(void) | ||
| 76 | { | ||
| 77 | iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc)); | ||
| 78 | } | ||
| 79 | |||
| 80 | void __init imx50_init_early(void) | ||
| 81 | { | ||
| 82 | mxc_set_cpu_type(MXC_CPU_MX50); | ||
| 83 | mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR)); | ||
| 84 | mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR)); | ||
| 85 | } | ||
| 86 | |||
| 54 | void __init imx51_init_early(void) | 87 | void __init imx51_init_early(void) |
| 55 | { | 88 | { |
| 56 | mxc_set_cpu_type(MXC_CPU_MX51); | 89 | mxc_set_cpu_type(MXC_CPU_MX51); |
| 57 | mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); | 90 | mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); |
| 58 | mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR)); | 91 | mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR)); |
| 59 | } | 92 | imx_idle = imx5_idle; |
| 60 | |||
| 61 | void __init mx53_map_io(void) | ||
| 62 | { | ||
| 63 | iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc)); | ||
| 64 | } | 93 | } |
| 65 | 94 | ||
| 66 | void __init imx53_init_early(void) | 95 | void __init imx53_init_early(void) |
| @@ -70,35 +99,19 @@ void __init imx53_init_early(void) | |||
| 70 | mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR)); | 99 | mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR)); |
| 71 | } | 100 | } |
| 72 | 101 | ||
| 73 | void __init mx51_init_irq(void) | 102 | void __init mx50_init_irq(void) |
| 74 | { | 103 | { |
| 75 | unsigned long tzic_addr; | 104 | tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR)); |
| 76 | void __iomem *tzic_virt; | 105 | } |
| 77 | |||
| 78 | if (mx51_revision() < IMX_CHIP_REVISION_2_0) | ||
| 79 | tzic_addr = MX51_TZIC_BASE_ADDR_TO1; | ||
| 80 | else | ||
| 81 | tzic_addr = MX51_TZIC_BASE_ADDR; | ||
| 82 | |||
| 83 | tzic_virt = ioremap(tzic_addr, SZ_16K); | ||
| 84 | if (!tzic_virt) | ||
| 85 | panic("unable to map TZIC interrupt controller\n"); | ||
| 86 | 106 | ||
| 87 | tzic_init_irq(tzic_virt); | 107 | void __init mx51_init_irq(void) |
| 108 | { | ||
| 109 | tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR)); | ||
| 88 | } | 110 | } |
| 89 | 111 | ||
| 90 | void __init mx53_init_irq(void) | 112 | void __init mx53_init_irq(void) |
| 91 | { | 113 | { |
| 92 | unsigned long tzic_addr; | 114 | tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR)); |
| 93 | void __iomem *tzic_virt; | ||
| 94 | |||
| 95 | tzic_addr = MX53_TZIC_BASE_ADDR; | ||
| 96 | |||
| 97 | tzic_virt = ioremap(tzic_addr, SZ_16K); | ||
| 98 | if (!tzic_virt) | ||
| 99 | panic("unable to map TZIC interrupt controller\n"); | ||
| 100 | |||
| 101 | tzic_init_irq(tzic_virt); | ||
| 102 | } | 115 | } |
| 103 | 116 | ||
| 104 | static struct sdma_script_start_addrs imx51_sdma_script __initdata = { | 117 | static struct sdma_script_start_addrs imx51_sdma_script __initdata = { |
| @@ -138,13 +151,24 @@ static struct sdma_platform_data imx53_sdma_pdata __initdata = { | |||
| 138 | .script_addrs = &imx53_sdma_script, | 151 | .script_addrs = &imx53_sdma_script, |
| 139 | }; | 152 | }; |
| 140 | 153 | ||
| 154 | void __init imx50_soc_init(void) | ||
| 155 | { | ||
| 156 | /* i.mx50 has the i.mx31 type gpio */ | ||
| 157 | mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH); | ||
| 158 | mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH); | ||
| 159 | mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH); | ||
| 160 | mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH); | ||
| 161 | mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH); | ||
| 162 | mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH); | ||
| 163 | } | ||
| 164 | |||
| 141 | void __init imx51_soc_init(void) | 165 | void __init imx51_soc_init(void) |
| 142 | { | 166 | { |
| 143 | /* i.mx51 has the i.mx31 type gpio */ | 167 | /* i.mx51 has the i.mx31 type gpio */ |
| 144 | mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO1_LOW, MX51_MXC_INT_GPIO1_HIGH); | 168 | mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH); |
| 145 | mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO2_LOW, MX51_MXC_INT_GPIO2_HIGH); | 169 | mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH); |
| 146 | mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO3_LOW, MX51_MXC_INT_GPIO3_HIGH); | 170 | mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH); |
| 147 | mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO4_LOW, MX51_MXC_INT_GPIO4_HIGH); | 171 | mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH); |
| 148 | 172 | ||
| 149 | /* i.mx51 has the i.mx35 type sdma */ | 173 | /* i.mx51 has the i.mx35 type sdma */ |
| 150 | imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata); | 174 | imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata); |
diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-mx5/mx51_efika.c index c9209454807a..b004e178417d 100644 --- a/arch/arm/mach-mx5/mx51_efika.c +++ b/arch/arm/mach-mx5/mx51_efika.c | |||
| @@ -34,14 +34,12 @@ | |||
| 34 | #include <linux/usb/ulpi.h> | 34 | #include <linux/usb/ulpi.h> |
| 35 | #include <mach/ulpi.h> | 35 | #include <mach/ulpi.h> |
| 36 | 36 | ||
| 37 | #include <asm/irq.h> | ||
| 38 | #include <asm/setup.h> | 37 | #include <asm/setup.h> |
| 39 | #include <asm/mach-types.h> | 38 | #include <asm/mach-types.h> |
| 40 | #include <asm/mach/arch.h> | 39 | #include <asm/mach/arch.h> |
| 41 | #include <asm/mach/time.h> | 40 | #include <asm/mach/time.h> |
| 42 | 41 | ||
| 43 | #include "devices-imx51.h" | 42 | #include "devices-imx51.h" |
| 44 | #include "devices.h" | ||
| 45 | #include "efika.h" | 43 | #include "efika.h" |
| 46 | #include "cpu_op-mx51.h" | 44 | #include "cpu_op-mx51.h" |
| 47 | 45 | ||
| @@ -133,7 +131,7 @@ static int initialize_otg_port(struct platform_device *pdev) | |||
| 133 | u32 v; | 131 | u32 v; |
| 134 | void __iomem *usb_base; | 132 | void __iomem *usb_base; |
| 135 | void __iomem *usbother_base; | 133 | void __iomem *usbother_base; |
| 136 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); | 134 | usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); |
| 137 | if (!usb_base) | 135 | if (!usb_base) |
| 138 | return -ENOMEM; | 136 | return -ENOMEM; |
| 139 | usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET); | 137 | usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET); |
| @@ -150,7 +148,7 @@ static int initialize_otg_port(struct platform_device *pdev) | |||
| 150 | return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY); | 148 | return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY); |
| 151 | } | 149 | } |
| 152 | 150 | ||
| 153 | static struct mxc_usbh_platform_data dr_utmi_config = { | 151 | static const struct mxc_usbh_platform_data dr_utmi_config __initconst = { |
| 154 | .init = initialize_otg_port, | 152 | .init = initialize_otg_port, |
| 155 | .portsc = MXC_EHCI_UTMI_16BIT, | 153 | .portsc = MXC_EHCI_UTMI_16BIT, |
| 156 | }; | 154 | }; |
| @@ -170,7 +168,7 @@ static int initialize_usbh1_port(struct platform_device *pdev) | |||
| 170 | gpio_set_value(EFIKAMX_USBH1_STP, 1); | 168 | gpio_set_value(EFIKAMX_USBH1_STP, 1); |
| 171 | msleep(1); | 169 | msleep(1); |
| 172 | 170 | ||
| 173 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); | 171 | usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); |
| 174 | socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET); | 172 | socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET); |
| 175 | 173 | ||
| 176 | /* The clock for the USBH1 ULPI port will come externally */ | 174 | /* The clock for the USBH1 ULPI port will come externally */ |
| @@ -189,7 +187,7 @@ static int initialize_usbh1_port(struct platform_device *pdev) | |||
| 189 | return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD); | 187 | return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD); |
| 190 | } | 188 | } |
| 191 | 189 | ||
| 192 | static struct mxc_usbh_platform_data usbh1_config = { | 190 | static struct mxc_usbh_platform_data usbh1_config __initdata = { |
| 193 | .init = initialize_usbh1_port, | 191 | .init = initialize_usbh1_port, |
| 194 | .portsc = MXC_EHCI_MODE_ULPI, | 192 | .portsc = MXC_EHCI_MODE_ULPI, |
| 195 | }; | 193 | }; |
| @@ -217,9 +215,9 @@ static void __init mx51_efika_usb(void) | |||
| 217 | usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | | 215 | usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | |
| 218 | ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND); | 216 | ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND); |
| 219 | 217 | ||
| 220 | mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); | 218 | imx51_add_mxc_ehci_otg(&dr_utmi_config); |
| 221 | if (usbh1_config.otg) | 219 | if (usbh1_config.otg) |
| 222 | mxc_register_device(&mxc_usbh1_device, &usbh1_config); | 220 | imx51_add_mxc_ehci_hs(1, &usbh1_config); |
| 223 | } | 221 | } |
| 224 | 222 | ||
| 225 | static struct mtd_partition mx51_efika_spi_nor_partitions[] = { | 223 | static struct mtd_partition mx51_efika_spi_nor_partitions[] = { |
| @@ -589,7 +587,7 @@ static struct spi_board_info mx51_efika_spi_board_info[] __initdata = { | |||
| 589 | .bus_num = 0, | 587 | .bus_num = 0, |
| 590 | .chip_select = 0, | 588 | .chip_select = 0, |
| 591 | .platform_data = &mx51_efika_mc13892_data, | 589 | .platform_data = &mx51_efika_mc13892_data, |
| 592 | .irq = gpio_to_irq(EFIKAMX_PMIC), | 590 | .irq = IMX_GPIO_TO_IRQ(EFIKAMX_PMIC), |
| 593 | }, | 591 | }, |
| 594 | }; | 592 | }; |
| 595 | 593 | ||
| @@ -609,7 +607,6 @@ void __init efika_board_common_init(void) | |||
| 609 | ARRAY_SIZE(mx51efika_pads)); | 607 | ARRAY_SIZE(mx51efika_pads)); |
| 610 | imx51_add_imx_uart(0, &uart_pdata); | 608 | imx51_add_imx_uart(0, &uart_pdata); |
| 611 | mx51_efika_usb(); | 609 | mx51_efika_usb(); |
| 612 | imx51_add_sdhci_esdhc_imx(0, NULL); | ||
| 613 | 610 | ||
| 614 | /* FIXME: comes from original code. check this. */ | 611 | /* FIXME: comes from original code. check this. */ |
| 615 | if (mx51_revision() < IMX_CHIP_REVISION_2_0) | 612 | if (mx51_revision() < IMX_CHIP_REVISION_2_0) |
| @@ -627,8 +624,9 @@ void __init efika_board_common_init(void) | |||
| 627 | ARRAY_SIZE(mx51_efika_spi_board_info)); | 624 | ARRAY_SIZE(mx51_efika_spi_board_info)); |
| 628 | imx51_add_ecspi(0, &mx51_efika_spi_pdata); | 625 | imx51_add_ecspi(0, &mx51_efika_spi_pdata); |
| 629 | 626 | ||
| 627 | imx51_add_pata_imx(); | ||
| 628 | |||
| 630 | #if defined(CONFIG_CPU_FREQ_IMX) | 629 | #if defined(CONFIG_CPU_FREQ_IMX) |
| 631 | get_cpu_op = mx51_get_cpu_op; | 630 | get_cpu_op = mx51_get_cpu_op; |
| 632 | #endif | 631 | #endif |
| 633 | } | 632 | } |
| 634 | |||
diff --git a/arch/arm/mach-mx5/pm-imx5.c b/arch/arm/mach-mx5/pm-imx5.c index e4529af0da72..0624fb8edffb 100644 --- a/arch/arm/mach-mx5/pm-imx5.c +++ b/arch/arm/mach-mx5/pm-imx5.c | |||
| @@ -14,7 +14,8 @@ | |||
| 14 | #include <linux/err.h> | 14 | #include <linux/err.h> |
| 15 | #include <asm/cacheflush.h> | 15 | #include <asm/cacheflush.h> |
| 16 | #include <asm/tlbflush.h> | 16 | #include <asm/tlbflush.h> |
| 17 | #include <mach/system.h> | 17 | #include <mach/common.h> |
| 18 | #include <mach/hardware.h> | ||
| 18 | #include "crm_regs.h" | 19 | #include "crm_regs.h" |
| 19 | 20 | ||
| 20 | static struct clk *gpc_dvfs_clk; | 21 | static struct clk *gpc_dvfs_clk; |
diff --git a/arch/arm/mach-mx5/system.c b/arch/arm/mach-mx5/system.c index 76ae8dc33e00..144ebebc4a61 100644 --- a/arch/arm/mach-mx5/system.c +++ b/arch/arm/mach-mx5/system.c | |||
| @@ -13,6 +13,7 @@ | |||
| 13 | #include <linux/platform_device.h> | 13 | #include <linux/platform_device.h> |
| 14 | #include <linux/io.h> | 14 | #include <linux/io.h> |
| 15 | #include <mach/hardware.h> | 15 | #include <mach/hardware.h> |
| 16 | #include <mach/common.h> | ||
| 16 | #include "crm_regs.h" | 17 | #include "crm_regs.h" |
| 17 | 18 | ||
| 18 | /* set cpu low power mode before WFI instruction. This function is called | 19 | /* set cpu low power mode before WFI instruction. This function is called |
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index 4cd0231ee539..fdf104f083b7 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig | |||
| @@ -23,6 +23,7 @@ config MACH_STMP378X_DEVB | |||
| 23 | select MXS_HAVE_AMBA_DUART | 23 | select MXS_HAVE_AMBA_DUART |
| 24 | select MXS_HAVE_PLATFORM_AUART | 24 | select MXS_HAVE_PLATFORM_AUART |
| 25 | select MXS_HAVE_PLATFORM_MXS_MMC | 25 | select MXS_HAVE_PLATFORM_MXS_MMC |
| 26 | select MXS_HAVE_PLATFORM_RTC_STMP3XXX | ||
| 26 | help | 27 | help |
| 27 | Include support for STMP378x-devb platform. This includes specific | 28 | Include support for STMP378x-devb platform. This includes specific |
| 28 | configurations for the board and its peripherals. | 29 | configurations for the board and its peripherals. |
| @@ -34,6 +35,7 @@ config MACH_MX23EVK | |||
| 34 | select MXS_HAVE_PLATFORM_AUART | 35 | select MXS_HAVE_PLATFORM_AUART |
| 35 | select MXS_HAVE_PLATFORM_MXS_MMC | 36 | select MXS_HAVE_PLATFORM_MXS_MMC |
| 36 | select MXS_HAVE_PLATFORM_MXSFB | 37 | select MXS_HAVE_PLATFORM_MXSFB |
| 38 | select MXS_HAVE_PLATFORM_RTC_STMP3XXX | ||
| 37 | help | 39 | help |
| 38 | Include support for MX23EVK platform. This includes specific | 40 | Include support for MX23EVK platform. This includes specific |
| 39 | configurations for the board and its peripherals. | 41 | configurations for the board and its peripherals. |
| @@ -48,6 +50,9 @@ config MACH_MX28EVK | |||
| 48 | select MXS_HAVE_PLATFORM_FLEXCAN | 50 | select MXS_HAVE_PLATFORM_FLEXCAN |
| 49 | select MXS_HAVE_PLATFORM_MXS_MMC | 51 | select MXS_HAVE_PLATFORM_MXS_MMC |
| 50 | select MXS_HAVE_PLATFORM_MXSFB | 52 | select MXS_HAVE_PLATFORM_MXSFB |
| 53 | select MXS_HAVE_PLATFORM_MXS_SAIF | ||
| 54 | select MXS_HAVE_PLATFORM_MXS_I2C | ||
| 55 | select MXS_HAVE_PLATFORM_RTC_STMP3XXX | ||
| 51 | select MXS_OCOTP | 56 | select MXS_OCOTP |
| 52 | help | 57 | help |
| 53 | Include support for MX28EVK platform. This includes specific | 58 | Include support for MX28EVK platform. This includes specific |
| @@ -63,6 +68,7 @@ config MODULE_TX28 | |||
| 63 | select MXS_HAVE_PLATFORM_MXS_I2C | 68 | select MXS_HAVE_PLATFORM_MXS_I2C |
| 64 | select MXS_HAVE_PLATFORM_MXS_MMC | 69 | select MXS_HAVE_PLATFORM_MXS_MMC |
| 65 | select MXS_HAVE_PLATFORM_MXS_PWM | 70 | select MXS_HAVE_PLATFORM_MXS_PWM |
| 71 | select MXS_HAVE_PLATFORM_RTC_STMP3XXX | ||
| 66 | 72 | ||
| 67 | config MACH_TX28 | 73 | config MACH_TX28 |
| 68 | bool "Ka-Ro TX28 module" | 74 | bool "Ka-Ro TX28 module" |
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile index 6c38262a3aaa..ea8dcb7742bc 100644 --- a/arch/arm/mach-mxs/Makefile +++ b/arch/arm/mach-mxs/Makefile | |||
| @@ -1,11 +1,11 @@ | |||
| 1 | # Common support | 1 | # Common support |
| 2 | obj-y := clock.o devices.o icoll.o iomux.o system.o timer.o | 2 | obj-y := clock.o devices.o icoll.o iomux.o system.o timer.o mm.o |
| 3 | 3 | ||
| 4 | obj-$(CONFIG_MXS_OCOTP) += ocotp.o | 4 | obj-$(CONFIG_MXS_OCOTP) += ocotp.o |
| 5 | obj-$(CONFIG_PM) += pm.o | 5 | obj-$(CONFIG_PM) += pm.o |
| 6 | 6 | ||
| 7 | obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o | 7 | obj-$(CONFIG_SOC_IMX23) += clock-mx23.o |
| 8 | obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o | 8 | obj-$(CONFIG_SOC_IMX28) += clock-mx28.o |
| 9 | 9 | ||
| 10 | obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o | 10 | obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o |
| 11 | obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o | 11 | obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o |
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c index 5dcc59d5b9ec..7954013bd32f 100644 --- a/arch/arm/mach-mxs/clock-mx28.c +++ b/arch/arm/mach-mxs/clock-mx28.c | |||
| @@ -640,6 +640,8 @@ static struct clk_lookup lookups[] = { | |||
| 640 | _REGISTER_CLOCK(NULL, "lradc", lradc_clk) | 640 | _REGISTER_CLOCK(NULL, "lradc", lradc_clk) |
| 641 | _REGISTER_CLOCK(NULL, "spdif", spdif_clk) | 641 | _REGISTER_CLOCK(NULL, "spdif", spdif_clk) |
| 642 | _REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk) | 642 | _REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk) |
| 643 | _REGISTER_CLOCK("mxs-saif.0", NULL, saif0_clk) | ||
| 644 | _REGISTER_CLOCK("mxs-saif.1", NULL, saif1_clk) | ||
| 643 | }; | 645 | }; |
| 644 | 646 | ||
| 645 | static int clk_misc_init(void) | 647 | static int clk_misc_init(void) |
| @@ -708,11 +710,11 @@ static int clk_misc_init(void) | |||
| 708 | 710 | ||
| 709 | /* SAIF has to use frac div for functional operation */ | 711 | /* SAIF has to use frac div for functional operation */ |
| 710 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0); | 712 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0); |
| 711 | reg &= ~BM_CLKCTRL_SAIF0_DIV_FRAC_EN; | 713 | reg |= BM_CLKCTRL_SAIF0_DIV_FRAC_EN; |
| 712 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0); | 714 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0); |
| 713 | 715 | ||
| 714 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1); | 716 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1); |
| 715 | reg &= ~BM_CLKCTRL_SAIF1_DIV_FRAC_EN; | 717 | reg |= BM_CLKCTRL_SAIF1_DIV_FRAC_EN; |
| 716 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1); | 718 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1); |
| 717 | 719 | ||
| 718 | /* | 720 | /* |
| @@ -774,6 +776,8 @@ int __init mx28_clocks_init(void) | |||
| 774 | clk_enable(&uart_clk); | 776 | clk_enable(&uart_clk); |
| 775 | 777 | ||
| 776 | clk_set_parent(&lcdif_clk, &ref_pix_clk); | 778 | clk_set_parent(&lcdif_clk, &ref_pix_clk); |
| 779 | clk_set_parent(&saif0_clk, &pll0_clk); | ||
| 780 | clk_set_parent(&saif1_clk, &pll0_clk); | ||
| 777 | 781 | ||
| 778 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); | 782 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); |
| 779 | 783 | ||
diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h index c6f345febd39..3fa651d2c994 100644 --- a/arch/arm/mach-mxs/devices-mx23.h +++ b/arch/arm/mach-mxs/devices-mx23.h | |||
| @@ -29,3 +29,5 @@ extern const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst; | |||
| 29 | 29 | ||
| 30 | struct platform_device *__init mx23_add_mxsfb( | 30 | struct platform_device *__init mx23_add_mxsfb( |
| 31 | const struct mxsfb_platform_data *pdata); | 31 | const struct mxsfb_platform_data *pdata); |
| 32 | |||
| 33 | struct platform_device *__init mx23_add_rtc_stmp3xxx(void); | ||
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h index 79b94523954a..c8887103f0e3 100644 --- a/arch/arm/mach-mxs/devices-mx28.h +++ b/arch/arm/mach-mxs/devices-mx28.h | |||
| @@ -45,3 +45,8 @@ extern const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst; | |||
| 45 | 45 | ||
| 46 | struct platform_device *__init mx28_add_mxsfb( | 46 | struct platform_device *__init mx28_add_mxsfb( |
| 47 | const struct mxsfb_platform_data *pdata); | 47 | const struct mxsfb_platform_data *pdata); |
| 48 | |||
| 49 | extern const struct mxs_saif_data mx28_saif_data[] __initconst; | ||
| 50 | #define mx28_add_saif(id) mxs_add_saif(&mx28_saif_data[id]) | ||
| 51 | |||
| 52 | struct platform_device *__init mx28_add_rtc_stmp3xxx(void); | ||
diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig index acf9eea124c0..18b6bf526a27 100644 --- a/arch/arm/mach-mxs/devices/Kconfig +++ b/arch/arm/mach-mxs/devices/Kconfig | |||
| @@ -23,3 +23,9 @@ config MXS_HAVE_PLATFORM_MXS_PWM | |||
| 23 | 23 | ||
| 24 | config MXS_HAVE_PLATFORM_MXSFB | 24 | config MXS_HAVE_PLATFORM_MXSFB |
| 25 | bool | 25 | bool |
| 26 | |||
| 27 | config MXS_HAVE_PLATFORM_MXS_SAIF | ||
| 28 | bool | ||
| 29 | |||
| 30 | config MXS_HAVE_PLATFORM_RTC_STMP3XXX | ||
| 31 | bool | ||
diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile index 351915c683ff..f52e3e53baec 100644 --- a/arch/arm/mach-mxs/devices/Makefile +++ b/arch/arm/mach-mxs/devices/Makefile | |||
| @@ -8,3 +8,5 @@ obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_MMC) += platform-mxs-mmc.o | |||
| 8 | obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o | 8 | obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o |
| 9 | obj-y += platform-gpio-mxs.o | 9 | obj-y += platform-gpio-mxs.o |
| 10 | obj-$(CONFIG_MXS_HAVE_PLATFORM_MXSFB) += platform-mxsfb.o | 10 | obj-$(CONFIG_MXS_HAVE_PLATFORM_MXSFB) += platform-mxsfb.o |
| 11 | obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_SAIF) += platform-mxs-saif.o | ||
| 12 | obj-$(CONFIG_MXS_HAVE_PLATFORM_RTC_STMP3XXX) += platform-rtc-stmp3xxx.o | ||
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-saif.c b/arch/arm/mach-mxs/devices/platform-mxs-saif.c new file mode 100644 index 000000000000..1ec965e9fe92 --- /dev/null +++ b/arch/arm/mach-mxs/devices/platform-mxs-saif.c | |||
| @@ -0,0 +1,60 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it under | ||
| 5 | * the terms of the GNU General Public License version 2 as published by the | ||
| 6 | * Free Software Foundation. | ||
| 7 | */ | ||
| 8 | #include <linux/compiler.h> | ||
| 9 | #include <linux/err.h> | ||
| 10 | #include <linux/init.h> | ||
| 11 | |||
| 12 | #include <mach/mx23.h> | ||
| 13 | #include <mach/mx28.h> | ||
| 14 | #include <mach/devices-common.h> | ||
| 15 | |||
| 16 | #define mxs_saif_data_entry_single(soc, _id) \ | ||
| 17 | { \ | ||
| 18 | .id = _id, \ | ||
| 19 | .iobase = soc ## _SAIF ## _id ## _BASE_ADDR, \ | ||
| 20 | .irq = soc ## _INT_SAIF ## _id, \ | ||
| 21 | .dma = soc ## _DMA_SAIF ## _id, \ | ||
| 22 | .dmairq = soc ## _INT_SAIF ## _id ##_DMA, \ | ||
| 23 | } | ||
| 24 | |||
| 25 | #define mxs_saif_data_entry(soc, _id) \ | ||
| 26 | [_id] = mxs_saif_data_entry_single(soc, _id) | ||
| 27 | |||
| 28 | #ifdef CONFIG_SOC_IMX28 | ||
| 29 | const struct mxs_saif_data mx28_saif_data[] __initconst = { | ||
| 30 | mxs_saif_data_entry(MX28, 0), | ||
| 31 | mxs_saif_data_entry(MX28, 1), | ||
| 32 | }; | ||
| 33 | #endif | ||
| 34 | |||
| 35 | struct platform_device *__init mxs_add_saif(const struct mxs_saif_data *data) | ||
| 36 | { | ||
| 37 | struct resource res[] = { | ||
| 38 | { | ||
| 39 | .start = data->iobase, | ||
| 40 | .end = data->iobase + SZ_4K - 1, | ||
| 41 | .flags = IORESOURCE_MEM, | ||
| 42 | }, { | ||
| 43 | .start = data->irq, | ||
| 44 | .end = data->irq, | ||
| 45 | .flags = IORESOURCE_IRQ, | ||
| 46 | }, { | ||
| 47 | .start = data->dma, | ||
| 48 | .end = data->dma, | ||
| 49 | .flags = IORESOURCE_DMA, | ||
| 50 | }, { | ||
| 51 | .start = data->dmairq, | ||
| 52 | .end = data->dmairq, | ||
| 53 | .flags = IORESOURCE_IRQ, | ||
| 54 | }, | ||
| 55 | |||
| 56 | }; | ||
| 57 | |||
| 58 | return mxs_add_platform_device("mxs-saif", data->id, res, | ||
| 59 | ARRAY_SIZE(res), NULL, 0); | ||
| 60 | } | ||
diff --git a/arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c b/arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c new file mode 100644 index 000000000000..639eaee15553 --- /dev/null +++ b/arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c | |||
| @@ -0,0 +1,51 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2011 Pengutronix, Wolfram Sang <w.sang@pengutronix.de> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it under | ||
| 5 | * the terms of the GNU General Public License version 2 as published by the | ||
| 6 | * Free Software Foundation. | ||
| 7 | */ | ||
| 8 | #include <asm/sizes.h> | ||
| 9 | #include <mach/mx23.h> | ||
| 10 | #include <mach/mx28.h> | ||
| 11 | #include <mach/devices-common.h> | ||
| 12 | |||
| 13 | #ifdef CONFIG_SOC_IMX23 | ||
| 14 | struct platform_device *__init mx23_add_rtc_stmp3xxx(void) | ||
| 15 | { | ||
| 16 | struct resource res[] = { | ||
| 17 | { | ||
| 18 | .start = MX23_RTC_BASE_ADDR, | ||
| 19 | .end = MX23_RTC_BASE_ADDR + SZ_8K - 1, | ||
| 20 | .flags = IORESOURCE_MEM, | ||
| 21 | }, { | ||
| 22 | .start = MX23_INT_RTC_ALARM, | ||
| 23 | .end = MX23_INT_RTC_ALARM, | ||
| 24 | .flags = IORESOURCE_IRQ, | ||
| 25 | }, | ||
| 26 | }; | ||
| 27 | |||
| 28 | return mxs_add_platform_device("stmp3xxx-rtc", 0, res, ARRAY_SIZE(res), | ||
| 29 | NULL, 0); | ||
| 30 | } | ||
| 31 | #endif /* CONFIG_SOC_IMX23 */ | ||
| 32 | |||
| 33 | #ifdef CONFIG_SOC_IMX28 | ||
| 34 | struct platform_device *__init mx28_add_rtc_stmp3xxx(void) | ||
| 35 | { | ||
| 36 | struct resource res[] = { | ||
| 37 | { | ||
| 38 | .start = MX28_RTC_BASE_ADDR, | ||
| 39 | .end = MX28_RTC_BASE_ADDR + SZ_8K - 1, | ||
| 40 | .flags = IORESOURCE_MEM, | ||
| 41 | }, { | ||
| 42 | .start = MX28_INT_RTC_ALARM, | ||
| 43 | .end = MX28_INT_RTC_ALARM, | ||
| 44 | .flags = IORESOURCE_IRQ, | ||
| 45 | }, | ||
| 46 | }; | ||
| 47 | |||
| 48 | return mxs_add_platform_device("stmp3xxx-rtc", 0, res, ARRAY_SIZE(res), | ||
| 49 | NULL, 0); | ||
| 50 | } | ||
| 51 | #endif /* CONFIG_SOC_IMX28 */ | ||
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h index 812d7a813a78..a8080f44c03d 100644 --- a/arch/arm/mach-mxs/include/mach/devices-common.h +++ b/arch/arm/mach-mxs/include/mach/devices-common.h | |||
| @@ -92,3 +92,15 @@ struct platform_device *__init mxs_add_mxs_mmc( | |||
| 92 | /* pwm */ | 92 | /* pwm */ |
| 93 | struct platform_device *__init mxs_add_mxs_pwm( | 93 | struct platform_device *__init mxs_add_mxs_pwm( |
| 94 | resource_size_t iobase, int id); | 94 | resource_size_t iobase, int id); |
| 95 | |||
| 96 | /* saif */ | ||
| 97 | struct mxs_saif_data { | ||
| 98 | int id; | ||
| 99 | resource_size_t iobase; | ||
| 100 | resource_size_t irq; | ||
| 101 | resource_size_t dma; | ||
| 102 | resource_size_t dmairq; | ||
| 103 | }; | ||
| 104 | |||
| 105 | struct platform_device *__init mxs_add_saif( | ||
| 106 | const struct mxs_saif_data *data); | ||
diff --git a/arch/arm/mach-mxs/include/mach/gpio.h b/arch/arm/mach-mxs/include/mach/gpio.h index 828ccccb6aad..56025aa0a639 100644 --- a/arch/arm/mach-mxs/include/mach/gpio.h +++ b/arch/arm/mach-mxs/include/mach/gpio.h | |||
| @@ -22,14 +22,10 @@ | |||
| 22 | 22 | ||
| 23 | #include <asm-generic/gpio.h> | 23 | #include <asm-generic/gpio.h> |
| 24 | 24 | ||
| 25 | #define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr)) | ||
| 26 | |||
| 27 | /* use gpiolib dispatchers */ | 25 | /* use gpiolib dispatchers */ |
| 28 | #define gpio_get_value __gpio_get_value | 26 | #define gpio_get_value __gpio_get_value |
| 29 | #define gpio_set_value __gpio_set_value | 27 | #define gpio_set_value __gpio_set_value |
| 30 | #define gpio_cansleep __gpio_cansleep | 28 | #define gpio_cansleep __gpio_cansleep |
| 31 | #define gpio_to_irq __gpio_to_irq | 29 | #define gpio_to_irq __gpio_to_irq |
| 32 | 30 | ||
| 33 | #define irq_to_gpio(irq) ((irq) - MXS_GPIO_IRQ_START) | ||
| 34 | |||
| 35 | #endif /* __MACH_MXS_GPIO_H__ */ | 31 | #endif /* __MACH_MXS_GPIO_H__ */ |
diff --git a/arch/arm/mach-mxs/include/mach/mxs.h b/arch/arm/mach-mxs/include/mach/mxs.h index 35a89dd27242..5aa5f754c846 100644 --- a/arch/arm/mach-mxs/include/mach/mxs.h +++ b/arch/arm/mach-mxs/include/mach/mxs.h | |||
| @@ -86,6 +86,8 @@ | |||
| 86 | .type = _type, \ | 86 | .type = _type, \ |
| 87 | } | 87 | } |
| 88 | 88 | ||
| 89 | #define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr)) | ||
| 90 | |||
| 89 | #define MXS_SET_ADDR 0x4 | 91 | #define MXS_SET_ADDR 0x4 |
| 90 | #define MXS_CLR_ADDR 0x8 | 92 | #define MXS_CLR_ADDR 0x8 |
| 91 | #define MXS_TOG_ADDR 0xc | 93 | #define MXS_TOG_ADDR 0xc |
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c index 3c2de33803ab..a1d132dce5c3 100644 --- a/arch/arm/mach-mxs/mach-mx23evk.c +++ b/arch/arm/mach-mxs/mach-mx23evk.c | |||
| @@ -15,7 +15,6 @@ | |||
| 15 | #include <linux/delay.h> | 15 | #include <linux/delay.h> |
| 16 | #include <linux/platform_device.h> | 16 | #include <linux/platform_device.h> |
| 17 | #include <linux/gpio.h> | 17 | #include <linux/gpio.h> |
| 18 | #include <linux/irq.h> | ||
| 19 | 18 | ||
| 20 | #include <asm/mach-types.h> | 19 | #include <asm/mach-types.h> |
| 21 | #include <asm/mach/arch.h> | 20 | #include <asm/mach/arch.h> |
| @@ -167,6 +166,7 @@ static void __init mx23evk_init(void) | |||
| 167 | gpio_set_value(MX23EVK_BL_ENABLE, 1); | 166 | gpio_set_value(MX23EVK_BL_ENABLE, 1); |
| 168 | 167 | ||
| 169 | mx23_add_mxsfb(&mx23evk_mxsfb_pdata); | 168 | mx23_add_mxsfb(&mx23evk_mxsfb_pdata); |
| 169 | mx23_add_rtc_stmp3xxx(); | ||
| 170 | } | 170 | } |
| 171 | 171 | ||
| 172 | static void __init mx23evk_timer_init(void) | 172 | static void __init mx23evk_timer_init(void) |
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c index eaaf6ff28990..e7bff1e2cd2b 100644 --- a/arch/arm/mach-mxs/mach-mx28evk.c +++ b/arch/arm/mach-mxs/mach-mx28evk.c | |||
| @@ -16,8 +16,10 @@ | |||
| 16 | #include <linux/platform_device.h> | 16 | #include <linux/platform_device.h> |
| 17 | #include <linux/gpio.h> | 17 | #include <linux/gpio.h> |
| 18 | #include <linux/leds.h> | 18 | #include <linux/leds.h> |
| 19 | #include <linux/irq.h> | ||
| 20 | #include <linux/clk.h> | 19 | #include <linux/clk.h> |
| 20 | #include <linux/i2c.h> | ||
| 21 | #include <linux/regulator/machine.h> | ||
| 22 | #include <linux/regulator/fixed.h> | ||
| 21 | 23 | ||
| 22 | #include <asm/mach-types.h> | 24 | #include <asm/mach-types.h> |
| 23 | #include <asm/mach/arch.h> | 25 | #include <asm/mach/arch.h> |
| @@ -183,6 +185,24 @@ static const iomux_cfg_t mx28evk_pads[] __initconst = { | |||
| 183 | 185 | ||
| 184 | /* led */ | 186 | /* led */ |
| 185 | MX28_PAD_AUART1_TX__GPIO_3_5 | MXS_PAD_CTRL, | 187 | MX28_PAD_AUART1_TX__GPIO_3_5 | MXS_PAD_CTRL, |
| 188 | |||
| 189 | /* I2C */ | ||
| 190 | MX28_PAD_I2C0_SCL__I2C0_SCL | | ||
| 191 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 192 | MX28_PAD_I2C0_SDA__I2C0_SDA | | ||
| 193 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 194 | |||
| 195 | /* saif0 & saif1 */ | ||
| 196 | MX28_PAD_SAIF0_MCLK__SAIF0_MCLK | | ||
| 197 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 198 | MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK | | ||
| 199 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 200 | MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK | | ||
| 201 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 202 | MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 | | ||
| 203 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 204 | MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 | | ||
| 205 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
| 186 | }; | 206 | }; |
| 187 | 207 | ||
| 188 | /* led */ | 208 | /* led */ |
| @@ -352,6 +372,55 @@ static struct mxs_mmc_platform_data mx28evk_mmc_pdata[] __initdata = { | |||
| 352 | }, | 372 | }, |
| 353 | }; | 373 | }; |
| 354 | 374 | ||
| 375 | static struct i2c_board_info mxs_i2c0_board_info[] __initdata = { | ||
| 376 | { | ||
| 377 | I2C_BOARD_INFO("sgtl5000", 0x0a), | ||
| 378 | }, | ||
| 379 | }; | ||
| 380 | |||
| 381 | #if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE) | ||
| 382 | static struct regulator_consumer_supply mx28evk_audio_consumer_supplies[] = { | ||
| 383 | REGULATOR_SUPPLY("VDDA", "0-000a"), | ||
| 384 | REGULATOR_SUPPLY("VDDIO", "0-000a"), | ||
| 385 | }; | ||
| 386 | |||
| 387 | static struct regulator_init_data mx28evk_vdd_reg_init_data = { | ||
| 388 | .constraints = { | ||
| 389 | .name = "3V3", | ||
| 390 | .always_on = 1, | ||
| 391 | }, | ||
| 392 | .consumer_supplies = mx28evk_audio_consumer_supplies, | ||
| 393 | .num_consumer_supplies = ARRAY_SIZE(mx28evk_audio_consumer_supplies), | ||
| 394 | }; | ||
| 395 | |||
| 396 | static struct fixed_voltage_config mx28evk_vdd_pdata = { | ||
| 397 | .supply_name = "board-3V3", | ||
| 398 | .microvolts = 3300000, | ||
| 399 | .gpio = -EINVAL, | ||
| 400 | .enabled_at_boot = 1, | ||
| 401 | .init_data = &mx28evk_vdd_reg_init_data, | ||
| 402 | }; | ||
| 403 | static struct platform_device mx28evk_voltage_regulator = { | ||
| 404 | .name = "reg-fixed-voltage", | ||
| 405 | .id = -1, | ||
| 406 | .num_resources = 0, | ||
| 407 | .dev = { | ||
| 408 | .platform_data = &mx28evk_vdd_pdata, | ||
| 409 | }, | ||
| 410 | }; | ||
| 411 | static void __init mx28evk_add_regulators(void) | ||
| 412 | { | ||
| 413 | platform_device_register(&mx28evk_voltage_regulator); | ||
| 414 | } | ||
| 415 | #else | ||
| 416 | static void __init mx28evk_add_regulators(void) {} | ||
| 417 | #endif | ||
| 418 | |||
| 419 | static struct gpio mx28evk_lcd_gpios[] = { | ||
| 420 | { MX28EVK_LCD_ENABLE, GPIOF_OUT_INIT_HIGH, "lcd-enable" }, | ||
| 421 | { MX28EVK_BL_ENABLE, GPIOF_OUT_INIT_HIGH, "bl-enable" }, | ||
| 422 | }; | ||
| 423 | |||
| 355 | static void __init mx28evk_init(void) | 424 | static void __init mx28evk_init(void) |
| 356 | { | 425 | { |
| 357 | int ret; | 426 | int ret; |
| @@ -378,19 +447,24 @@ static void __init mx28evk_init(void) | |||
| 378 | mx28_add_flexcan(1, &mx28evk_flexcan_pdata[1]); | 447 | mx28_add_flexcan(1, &mx28evk_flexcan_pdata[1]); |
| 379 | } | 448 | } |
| 380 | 449 | ||
| 381 | ret = gpio_request_one(MX28EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable"); | 450 | ret = gpio_request_array(mx28evk_lcd_gpios, |
| 451 | ARRAY_SIZE(mx28evk_lcd_gpios)); | ||
| 382 | if (ret) | 452 | if (ret) |
| 383 | pr_warn("failed to request gpio lcd-enable: %d\n", ret); | 453 | pr_warn("failed to request gpio pins for lcd: %d\n", ret); |
| 384 | else | 454 | else |
| 385 | gpio_set_value(MX28EVK_LCD_ENABLE, 1); | 455 | mx28_add_mxsfb(&mx28evk_mxsfb_pdata); |
| 386 | 456 | ||
| 387 | ret = gpio_request_one(MX28EVK_BL_ENABLE, GPIOF_DIR_OUT, "bl-enable"); | 457 | mx28_add_saif(0); |
| 388 | if (ret) | 458 | mx28_add_saif(1); |
| 389 | pr_warn("failed to request gpio bl-enable: %d\n", ret); | 459 | |
| 390 | else | 460 | mx28_add_mxs_i2c(0); |
| 391 | gpio_set_value(MX28EVK_BL_ENABLE, 1); | 461 | i2c_register_board_info(0, mxs_i2c0_board_info, |
| 462 | ARRAY_SIZE(mxs_i2c0_board_info)); | ||
| 392 | 463 | ||
| 393 | mx28_add_mxsfb(&mx28evk_mxsfb_pdata); | 464 | mx28evk_add_regulators(); |
| 465 | |||
| 466 | mxs_add_platform_device("mxs-sgtl5000", 0, NULL, 0, | ||
| 467 | NULL, 0); | ||
| 394 | 468 | ||
| 395 | /* power on mmc slot by writing 0 to the gpio */ | 469 | /* power on mmc slot by writing 0 to the gpio */ |
| 396 | ret = gpio_request_one(MX28EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW, | 470 | ret = gpio_request_one(MX28EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW, |
| @@ -403,7 +477,11 @@ static void __init mx28evk_init(void) | |||
| 403 | "mmc1-slot-power"); | 477 | "mmc1-slot-power"); |
| 404 | if (ret) | 478 | if (ret) |
| 405 | pr_warn("failed to request gpio mmc1-slot-power: %d\n", ret); | 479 | pr_warn("failed to request gpio mmc1-slot-power: %d\n", ret); |
| 480 | else | ||
| 481 | mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]); | ||
| 482 | |||
| 406 | mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]); | 483 | mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]); |
| 484 | mx28_add_rtc_stmp3xxx(); | ||
| 407 | 485 | ||
| 408 | gpio_led_register_device(0, &mx28evk_led_data); | 486 | gpio_led_register_device(0, &mx28evk_led_data); |
| 409 | } | 487 | } |
diff --git a/arch/arm/mach-mxs/mach-stmp378x_devb.c b/arch/arm/mach-mxs/mach-stmp378x_devb.c index 7f38d82b69af..177e53123a02 100644 --- a/arch/arm/mach-mxs/mach-stmp378x_devb.c +++ b/arch/arm/mach-mxs/mach-stmp378x_devb.c | |||
| @@ -19,7 +19,6 @@ | |||
| 19 | 19 | ||
| 20 | #include <linux/platform_device.h> | 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/gpio.h> | 21 | #include <linux/gpio.h> |
| 22 | #include <linux/irq.h> | ||
| 23 | #include <linux/spi/spi.h> | 22 | #include <linux/spi/spi.h> |
| 24 | 23 | ||
| 25 | #include <asm/mach-types.h> | 24 | #include <asm/mach-types.h> |
| @@ -91,6 +90,7 @@ static void __init stmp378x_dvb_init(void) | |||
| 91 | 90 | ||
| 92 | mx23_add_duart(); | 91 | mx23_add_duart(); |
| 93 | mx23_add_auart0(); | 92 | mx23_add_auart0(); |
| 93 | mx23_add_rtc_stmp3xxx(); | ||
| 94 | 94 | ||
| 95 | /* power on mmc slot */ | 95 | /* power on mmc slot */ |
| 96 | ret = gpio_request_one(STMP378X_DEVB_MMC0_SLOT_POWER, | 96 | ret = gpio_request_one(STMP378X_DEVB_MMC0_SLOT_POWER, |
diff --git a/arch/arm/mach-mxs/mach-tx28.c b/arch/arm/mach-mxs/mach-tx28.c index 515a423f82cd..ce5d5632e62f 100644 --- a/arch/arm/mach-mxs/mach-tx28.c +++ b/arch/arm/mach-mxs/mach-tx28.c | |||
| @@ -161,6 +161,7 @@ static void __init tx28_stk5v3_init(void) | |||
| 161 | i2c_register_board_info(0, tx28_stk5v3_i2c_boardinfo, | 161 | i2c_register_board_info(0, tx28_stk5v3_i2c_boardinfo, |
| 162 | ARRAY_SIZE(tx28_stk5v3_i2c_boardinfo)); | 162 | ARRAY_SIZE(tx28_stk5v3_i2c_boardinfo)); |
| 163 | mx28_add_mxs_mmc(0, &tx28_mmc0_pdata); | 163 | mx28_add_mxs_mmc(0, &tx28_mmc0_pdata); |
| 164 | mx28_add_rtc_stmp3xxx(); | ||
| 164 | } | 165 | } |
| 165 | 166 | ||
| 166 | static void __init tx28_timer_init(void) | 167 | static void __init tx28_timer_init(void) |
diff --git a/arch/arm/mach-mxs/mm-mx28.c b/arch/arm/mach-mxs/mm-mx28.c deleted file mode 100644 index b6e18ddb92c0..000000000000 --- a/arch/arm/mach-mxs/mm-mx28.c +++ /dev/null | |||
| @@ -1,44 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * | ||
| 4 | * The code contained herein is licensed under the GNU General Public | ||
| 5 | * License. You may obtain a copy of the GNU General Public License | ||
| 6 | * Version 2 or later at the following locations: | ||
| 7 | * | ||
| 8 | * http://www.opensource.org/licenses/gpl-license.html | ||
| 9 | * http://www.gnu.org/copyleft/gpl.html | ||
| 10 | * | ||
| 11 | * Create static mapping between physical to virtual memory. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/mm.h> | ||
| 15 | #include <linux/init.h> | ||
| 16 | |||
| 17 | #include <asm/mach/map.h> | ||
| 18 | |||
| 19 | #include <mach/mx28.h> | ||
| 20 | #include <mach/common.h> | ||
| 21 | #include <mach/iomux.h> | ||
| 22 | |||
| 23 | /* | ||
| 24 | * Define the MX28 memory map. | ||
| 25 | */ | ||
| 26 | static struct map_desc mx28_io_desc[] __initdata = { | ||
| 27 | mxs_map_entry(MX28, OCRAM, MT_DEVICE), | ||
| 28 | mxs_map_entry(MX28, IO, MT_DEVICE), | ||
| 29 | }; | ||
| 30 | |||
| 31 | /* | ||
| 32 | * This function initializes the memory map. It is called during the | ||
| 33 | * system startup to create static physical to virtual memory mappings | ||
| 34 | * for the IO modules. | ||
| 35 | */ | ||
| 36 | void __init mx28_map_io(void) | ||
| 37 | { | ||
| 38 | iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc)); | ||
| 39 | } | ||
| 40 | |||
| 41 | void __init mx28_init_irq(void) | ||
| 42 | { | ||
| 43 | icoll_init_irq(); | ||
| 44 | } | ||
diff --git a/arch/arm/mach-mxs/mm-mx23.c b/arch/arm/mach-mxs/mm.c index 1b2345ac1a87..50af5ceebf6d 100644 --- a/arch/arm/mach-mxs/mm-mx23.c +++ b/arch/arm/mach-mxs/mm.c | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | #include <asm/mach/map.h> | 17 | #include <asm/mach/map.h> |
| 18 | 18 | ||
| 19 | #include <mach/mx23.h> | 19 | #include <mach/mx23.h> |
| 20 | #include <mach/mx28.h> | ||
| 20 | #include <mach/common.h> | 21 | #include <mach/common.h> |
| 21 | #include <mach/iomux.h> | 22 | #include <mach/iomux.h> |
| 22 | 23 | ||
| @@ -29,6 +30,14 @@ static struct map_desc mx23_io_desc[] __initdata = { | |||
| 29 | }; | 30 | }; |
| 30 | 31 | ||
| 31 | /* | 32 | /* |
| 33 | * Define the MX28 memory map. | ||
| 34 | */ | ||
| 35 | static struct map_desc mx28_io_desc[] __initdata = { | ||
| 36 | mxs_map_entry(MX28, OCRAM, MT_DEVICE), | ||
| 37 | mxs_map_entry(MX28, IO, MT_DEVICE), | ||
| 38 | }; | ||
| 39 | |||
| 40 | /* | ||
| 32 | * This function initializes the memory map. It is called during the | 41 | * This function initializes the memory map. It is called during the |
| 33 | * system startup to create static physical to virtual memory mappings | 42 | * system startup to create static physical to virtual memory mappings |
| 34 | * for the IO modules. | 43 | * for the IO modules. |
| @@ -42,3 +51,13 @@ void __init mx23_init_irq(void) | |||
| 42 | { | 51 | { |
| 43 | icoll_init_irq(); | 52 | icoll_init_irq(); |
| 44 | } | 53 | } |
| 54 | |||
| 55 | void __init mx28_map_io(void) | ||
| 56 | { | ||
| 57 | iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc)); | ||
| 58 | } | ||
| 59 | |||
| 60 | void __init mx28_init_irq(void) | ||
| 61 | { | ||
| 62 | icoll_init_irq(); | ||
| 63 | } | ||
diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile index 7af7fc05d565..f49d70b86854 100644 --- a/arch/arm/mach-prima2/Makefile +++ b/arch/arm/mach-prima2/Makefile | |||
| @@ -3,5 +3,6 @@ obj-y += irq.o | |||
| 3 | obj-y += clock.o | 3 | obj-y += clock.o |
| 4 | obj-y += rstc.o | 4 | obj-y += rstc.o |
| 5 | obj-y += prima2.o | 5 | obj-y += prima2.o |
| 6 | obj-y += rtciobrg.o | ||
| 6 | obj-$(CONFIG_DEBUG_LL) += lluart.o | 7 | obj-$(CONFIG_DEBUG_LL) += lluart.o |
| 7 | obj-$(CONFIG_CACHE_L2X0) += l2x0.o | 8 | obj-$(CONFIG_CACHE_L2X0) += l2x0.o |
diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c index 7af254d046ba..cf80a72c0a09 100644 --- a/arch/arm/mach-prima2/irq.c +++ b/arch/arm/mach-prima2/irq.c | |||
| @@ -13,6 +13,7 @@ | |||
| 13 | #include <asm/mach/irq.h> | 13 | #include <asm/mach/irq.h> |
| 14 | #include <linux/of.h> | 14 | #include <linux/of.h> |
| 15 | #include <linux/of_address.h> | 15 | #include <linux/of_address.h> |
| 16 | #include <linux/irqdomain.h> | ||
| 16 | 17 | ||
| 17 | #define SIRFSOC_INT_RISC_MASK0 0x0018 | 18 | #define SIRFSOC_INT_RISC_MASK0 0x0018 |
| 18 | #define SIRFSOC_INT_RISC_MASK1 0x001C | 19 | #define SIRFSOC_INT_RISC_MASK1 0x001C |
| @@ -66,6 +67,8 @@ void __init sirfsoc_of_irq_init(void) | |||
| 66 | if (!sirfsoc_intc_base) | 67 | if (!sirfsoc_intc_base) |
| 67 | panic("unable to map intc cpu registers\n"); | 68 | panic("unable to map intc cpu registers\n"); |
| 68 | 69 | ||
| 70 | irq_domain_add_simple(np, 0); | ||
| 71 | |||
| 69 | of_node_put(np); | 72 | of_node_put(np); |
| 70 | 73 | ||
| 71 | sirfsoc_irq_init(); | 74 | sirfsoc_irq_init(); |
diff --git a/arch/arm/mach-prima2/rtciobrg.c b/arch/arm/mach-prima2/rtciobrg.c new file mode 100644 index 000000000000..9d80f1e20a98 --- /dev/null +++ b/arch/arm/mach-prima2/rtciobrg.c | |||
| @@ -0,0 +1,139 @@ | |||
| 1 | /* | ||
| 2 | * RTC I/O Bridge interfaces for CSR SiRFprimaII | ||
| 3 | * ARM access the registers of SYSRTC, GPSRTC and PWRC through this module | ||
| 4 | * | ||
| 5 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. | ||
| 6 | * | ||
| 7 | * Licensed under GPLv2 or later. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include <linux/kernel.h> | ||
| 11 | #include <linux/module.h> | ||
| 12 | #include <linux/io.h> | ||
| 13 | #include <linux/of.h> | ||
| 14 | #include <linux/of_address.h> | ||
| 15 | #include <linux/of_device.h> | ||
| 16 | #include <linux/of_platform.h> | ||
| 17 | |||
| 18 | #define SIRFSOC_CPUIOBRG_CTRL 0x00 | ||
| 19 | #define SIRFSOC_CPUIOBRG_WRBE 0x04 | ||
| 20 | #define SIRFSOC_CPUIOBRG_ADDR 0x08 | ||
| 21 | #define SIRFSOC_CPUIOBRG_DATA 0x0c | ||
| 22 | |||
| 23 | /* | ||
| 24 | * suspend asm codes will access this address to make system deepsleep | ||
| 25 | * after DRAM becomes self-refresh | ||
| 26 | */ | ||
| 27 | void __iomem *sirfsoc_rtciobrg_base; | ||
| 28 | static DEFINE_SPINLOCK(rtciobrg_lock); | ||
| 29 | |||
| 30 | /* | ||
| 31 | * symbols without lock are only used by suspend asm codes | ||
| 32 | * and these symbols are not exported too | ||
| 33 | */ | ||
| 34 | void sirfsoc_rtc_iobrg_wait_sync(void) | ||
| 35 | { | ||
| 36 | while (readl_relaxed(sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_CTRL)) | ||
| 37 | cpu_relax(); | ||
| 38 | } | ||
| 39 | |||
| 40 | void sirfsoc_rtc_iobrg_besyncing(void) | ||
| 41 | { | ||
| 42 | unsigned long flags; | ||
| 43 | |||
| 44 | spin_lock_irqsave(&rtciobrg_lock, flags); | ||
| 45 | |||
| 46 | sirfsoc_rtc_iobrg_wait_sync(); | ||
| 47 | |||
| 48 | spin_unlock_irqrestore(&rtciobrg_lock, flags); | ||
| 49 | } | ||
| 50 | EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_besyncing); | ||
| 51 | |||
| 52 | u32 __sirfsoc_rtc_iobrg_readl(u32 addr) | ||
| 53 | { | ||
| 54 | sirfsoc_rtc_iobrg_wait_sync(); | ||
| 55 | |||
| 56 | writel_relaxed(0x00, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_WRBE); | ||
| 57 | writel_relaxed(addr, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_ADDR); | ||
| 58 | writel_relaxed(0x01, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_CTRL); | ||
| 59 | |||
| 60 | sirfsoc_rtc_iobrg_wait_sync(); | ||
| 61 | |||
| 62 | return readl_relaxed(sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_DATA); | ||
| 63 | } | ||
| 64 | |||
| 65 | u32 sirfsoc_rtc_iobrg_readl(u32 addr) | ||
| 66 | { | ||
| 67 | unsigned long flags, val; | ||
| 68 | |||
| 69 | spin_lock_irqsave(&rtciobrg_lock, flags); | ||
| 70 | |||
| 71 | val = __sirfsoc_rtc_iobrg_readl(addr); | ||
| 72 | |||
| 73 | spin_unlock_irqrestore(&rtciobrg_lock, flags); | ||
| 74 | |||
| 75 | return val; | ||
| 76 | } | ||
| 77 | EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_readl); | ||
| 78 | |||
| 79 | void sirfsoc_rtc_iobrg_pre_writel(u32 val, u32 addr) | ||
| 80 | { | ||
| 81 | sirfsoc_rtc_iobrg_wait_sync(); | ||
| 82 | |||
| 83 | writel_relaxed(0xf1, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_WRBE); | ||
| 84 | writel_relaxed(addr, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_ADDR); | ||
| 85 | |||
| 86 | writel_relaxed(val, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_DATA); | ||
| 87 | } | ||
| 88 | |||
| 89 | void sirfsoc_rtc_iobrg_writel(u32 val, u32 addr) | ||
| 90 | { | ||
| 91 | unsigned long flags; | ||
| 92 | |||
| 93 | spin_lock_irqsave(&rtciobrg_lock, flags); | ||
| 94 | |||
| 95 | sirfsoc_rtc_iobrg_pre_writel(val, addr); | ||
| 96 | |||
| 97 | writel_relaxed(0x01, sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_CTRL); | ||
| 98 | |||
| 99 | sirfsoc_rtc_iobrg_wait_sync(); | ||
| 100 | |||
| 101 | spin_unlock_irqrestore(&rtciobrg_lock, flags); | ||
| 102 | } | ||
| 103 | EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_writel); | ||
| 104 | |||
| 105 | static const struct of_device_id rtciobrg_ids[] = { | ||
| 106 | { .compatible = "sirf,prima2-rtciobg" }, | ||
| 107 | {} | ||
| 108 | }; | ||
| 109 | |||
| 110 | static int __devinit sirfsoc_rtciobrg_probe(struct platform_device *op) | ||
| 111 | { | ||
| 112 | struct device_node *np = op->dev.of_node; | ||
| 113 | |||
| 114 | sirfsoc_rtciobrg_base = of_iomap(np, 0); | ||
| 115 | if (!sirfsoc_rtciobrg_base) | ||
| 116 | panic("unable to map rtc iobrg registers\n"); | ||
| 117 | |||
| 118 | return 0; | ||
| 119 | } | ||
| 120 | |||
| 121 | static struct platform_driver sirfsoc_rtciobrg_driver = { | ||
| 122 | .probe = sirfsoc_rtciobrg_probe, | ||
| 123 | .driver = { | ||
| 124 | .name = "sirfsoc-rtciobrg", | ||
| 125 | .owner = THIS_MODULE, | ||
| 126 | .of_match_table = rtciobrg_ids, | ||
| 127 | }, | ||
| 128 | }; | ||
| 129 | |||
| 130 | static int __init sirfsoc_rtciobrg_init(void) | ||
| 131 | { | ||
| 132 | return platform_driver_register(&sirfsoc_rtciobrg_driver); | ||
| 133 | } | ||
| 134 | postcore_initcall(sirfsoc_rtciobrg_init); | ||
| 135 | |||
| 136 | MODULE_AUTHOR("Zhiwu Song <zhiwu.song@csr.com>, " | ||
| 137 | "Barry Song <baohua.song@csr.com>"); | ||
| 138 | MODULE_DESCRIPTION("CSR SiRFprimaII rtc io bridge"); | ||
| 139 | MODULE_LICENSE("GPL"); | ||
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index a5353fc0793f..502e45f03178 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig | |||
| @@ -4,50 +4,31 @@ source "arch/arm/plat-mxc/devices/Kconfig" | |||
| 4 | 4 | ||
| 5 | menu "Freescale MXC Implementations" | 5 | menu "Freescale MXC Implementations" |
| 6 | 6 | ||
| 7 | config ARCH_MX50_SUPPORTED | ||
| 8 | bool | ||
| 9 | |||
| 10 | config ARCH_MX53_SUPPORTED | ||
| 11 | bool | ||
| 12 | |||
| 13 | choice | 7 | choice |
| 14 | prompt "Freescale CPU family:" | 8 | prompt "Freescale CPU family:" |
| 15 | default ARCH_MX3 | 9 | default ARCH_MX3 |
| 16 | 10 | ||
| 17 | config ARCH_MX1 | 11 | config ARCH_IMX_V4_V5 |
| 18 | bool "MX1-based" | 12 | bool "i.MX1, i.MX21, i.MX25, i.MX27" |
| 19 | help | 13 | select AUTO_ZRELADDR |
| 20 | This enables support for systems based on the Freescale i.MX1 family | 14 | select ARM_PATCH_PHYS_VIRT |
| 21 | |||
| 22 | config ARCH_MX2 | ||
| 23 | bool "MX2-based" | ||
| 24 | help | ||
| 25 | This enables support for systems based on the Freescale i.MX2 family | ||
| 26 | |||
| 27 | config ARCH_MX25 | ||
| 28 | bool "MX25-based" | ||
| 29 | help | 15 | help |
| 30 | This enables support for systems based on the Freescale i.MX25 family | 16 | This enables support for systems based on the Freescale i.MX ARMv4 |
| 17 | and ARMv5 SoCs | ||
| 31 | 18 | ||
| 32 | config ARCH_MX3 | 19 | config ARCH_MX3 |
| 33 | bool "MX3-based" | 20 | bool "MX3-based" |
| 34 | help | 21 | help |
| 35 | This enables support for systems based on the Freescale i.MX3 family | 22 | This enables support for systems based on the Freescale i.MX3 family |
| 36 | 23 | ||
| 37 | config ARCH_MX503 | 24 | config ARCH_MX5 |
| 38 | bool "i.MX50 + i.MX53" | 25 | bool "i.MX50, i.MX51, i.MX53" |
| 39 | select ARCH_MX50_SUPPORTED | 26 | select AUTO_ZRELADDR |
| 40 | select ARCH_MX53_SUPPORTED | 27 | select ARM_PATCH_PHYS_VIRT |
| 41 | help | 28 | help |
| 42 | This enables support for machines using Freescale's i.MX50 and i.MX51 | 29 | This enables support for machines using Freescale's i.MX50 and i.MX51 |
| 43 | processors. | 30 | processors. |
| 44 | 31 | ||
| 45 | config ARCH_MX51 | ||
| 46 | bool "i.MX51" | ||
| 47 | select ARCH_MX51_SUPPORTED | ||
| 48 | help | ||
| 49 | This enables support for systems based on the Freescale i.MX51 family | ||
| 50 | |||
| 51 | endchoice | 32 | endchoice |
| 52 | 33 | ||
| 53 | source "arch/arm/mach-imx/Kconfig" | 34 | source "arch/arm/mach-imx/Kconfig" |
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c index 175e3647bb27..8cced35009bd 100644 --- a/arch/arm/plat-mxc/audmux-v2.c +++ b/arch/arm/plat-mxc/audmux-v2.c | |||
| @@ -187,18 +187,11 @@ EXPORT_SYMBOL_GPL(mxc_audmux_v2_configure_port); | |||
| 187 | static int mxc_audmux_v2_init(void) | 187 | static int mxc_audmux_v2_init(void) |
| 188 | { | 188 | { |
| 189 | int ret; | 189 | int ret; |
| 190 | #if defined(CONFIG_ARCH_MX5) | ||
| 191 | if (cpu_is_mx51()) { | 190 | if (cpu_is_mx51()) { |
| 192 | audmux_base = MX51_IO_ADDRESS(MX51_AUDMUX_BASE_ADDR); | 191 | audmux_base = MX51_IO_ADDRESS(MX51_AUDMUX_BASE_ADDR); |
| 193 | ret = 0; | 192 | } else if (cpu_is_mx31()) { |
| 194 | return ret; | ||
| 195 | } | ||
| 196 | #endif | ||
| 197 | #if defined(CONFIG_ARCH_MX3) | ||
| 198 | if (cpu_is_mx31()) | ||
| 199 | audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR); | 193 | audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR); |
| 200 | 194 | } else if (cpu_is_mx35()) { | |
| 201 | else if (cpu_is_mx35()) { | ||
| 202 | audmux_clk = clk_get(NULL, "audmux"); | 195 | audmux_clk = clk_get(NULL, "audmux"); |
| 203 | if (IS_ERR(audmux_clk)) { | 196 | if (IS_ERR(audmux_clk)) { |
| 204 | ret = PTR_ERR(audmux_clk); | 197 | ret = PTR_ERR(audmux_clk); |
| @@ -207,10 +200,7 @@ static int mxc_audmux_v2_init(void) | |||
| 207 | return ret; | 200 | return ret; |
| 208 | } | 201 | } |
| 209 | audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR); | 202 | audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR); |
| 210 | } | 203 | } else if (cpu_is_mx25()) { |
| 211 | #endif | ||
| 212 | #if defined(CONFIG_SOC_IMX25) | ||
| 213 | if (cpu_is_mx25()) { | ||
| 214 | audmux_clk = clk_get(NULL, "audmux"); | 204 | audmux_clk = clk_get(NULL, "audmux"); |
| 215 | if (IS_ERR(audmux_clk)) { | 205 | if (IS_ERR(audmux_clk)) { |
| 216 | ret = PTR_ERR(audmux_clk); | 206 | ret = PTR_ERR(audmux_clk); |
| @@ -220,7 +210,7 @@ static int mxc_audmux_v2_init(void) | |||
| 220 | } | 210 | } |
| 221 | audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR); | 211 | audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR); |
| 222 | } | 212 | } |
| 223 | #endif /* if defined(CONFIG_SOC_IMX25) */ | 213 | |
| 224 | audmux_debugfs_init(); | 214 | audmux_debugfs_init(); |
| 225 | 215 | ||
| 226 | return 0; | 216 | return 0; |
diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c index 55d2534ec727..8875fb415f68 100644 --- a/arch/arm/plat-mxc/avic.c +++ b/arch/arm/plat-mxc/avic.c | |||
| @@ -50,6 +50,8 @@ | |||
| 50 | 50 | ||
| 51 | void __iomem *avic_base; | 51 | void __iomem *avic_base; |
| 52 | 52 | ||
| 53 | static u32 avic_saved_mask_reg[2]; | ||
| 54 | |||
| 53 | #ifdef CONFIG_MXC_IRQ_PRIOR | 55 | #ifdef CONFIG_MXC_IRQ_PRIOR |
| 54 | static int avic_irq_set_priority(unsigned char irq, unsigned char prio) | 56 | static int avic_irq_set_priority(unsigned char irq, unsigned char prio) |
| 55 | { | 57 | { |
| @@ -90,24 +92,8 @@ static int avic_set_irq_fiq(unsigned int irq, unsigned int type) | |||
| 90 | } | 92 | } |
| 91 | #endif /* CONFIG_FIQ */ | 93 | #endif /* CONFIG_FIQ */ |
| 92 | 94 | ||
| 93 | /* Disable interrupt number "irq" in the AVIC */ | ||
| 94 | static void mxc_mask_irq(struct irq_data *d) | ||
| 95 | { | ||
| 96 | __raw_writel(d->irq, avic_base + AVIC_INTDISNUM); | ||
| 97 | } | ||
| 98 | 95 | ||
| 99 | /* Enable interrupt number "irq" in the AVIC */ | 96 | static struct mxc_extra_irq avic_extra_irq = { |
| 100 | static void mxc_unmask_irq(struct irq_data *d) | ||
| 101 | { | ||
| 102 | __raw_writel(d->irq, avic_base + AVIC_INTENNUM); | ||
| 103 | } | ||
| 104 | |||
| 105 | static struct mxc_irq_chip mxc_avic_chip = { | ||
| 106 | .base = { | ||
| 107 | .irq_ack = mxc_mask_irq, | ||
| 108 | .irq_mask = mxc_mask_irq, | ||
| 109 | .irq_unmask = mxc_unmask_irq, | ||
| 110 | }, | ||
| 111 | #ifdef CONFIG_MXC_IRQ_PRIOR | 97 | #ifdef CONFIG_MXC_IRQ_PRIOR |
| 112 | .set_priority = avic_irq_set_priority, | 98 | .set_priority = avic_irq_set_priority, |
| 113 | #endif | 99 | #endif |
| @@ -116,6 +102,68 @@ static struct mxc_irq_chip mxc_avic_chip = { | |||
| 116 | #endif | 102 | #endif |
| 117 | }; | 103 | }; |
| 118 | 104 | ||
| 105 | #ifdef CONFIG_PM | ||
| 106 | static void avic_irq_suspend(struct irq_data *d) | ||
| 107 | { | ||
| 108 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | ||
| 109 | struct irq_chip_type *ct = gc->chip_types; | ||
| 110 | int idx = gc->irq_base >> 5; | ||
| 111 | |||
| 112 | avic_saved_mask_reg[idx] = __raw_readl(avic_base + ct->regs.mask); | ||
| 113 | __raw_writel(gc->wake_active, avic_base + ct->regs.mask); | ||
| 114 | } | ||
| 115 | |||
| 116 | static void avic_irq_resume(struct irq_data *d) | ||
| 117 | { | ||
| 118 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | ||
| 119 | struct irq_chip_type *ct = gc->chip_types; | ||
| 120 | int idx = gc->irq_base >> 5; | ||
| 121 | |||
| 122 | __raw_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask); | ||
| 123 | } | ||
| 124 | |||
| 125 | #else | ||
| 126 | #define avic_irq_suspend NULL | ||
| 127 | #define avic_irq_resume NULL | ||
| 128 | #endif | ||
| 129 | |||
| 130 | static __init void avic_init_gc(unsigned int irq_start) | ||
| 131 | { | ||
| 132 | struct irq_chip_generic *gc; | ||
| 133 | struct irq_chip_type *ct; | ||
| 134 | int idx = irq_start >> 5; | ||
| 135 | |||
| 136 | gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base, | ||
| 137 | handle_level_irq); | ||
| 138 | gc->private = &avic_extra_irq; | ||
| 139 | gc->wake_enabled = IRQ_MSK(32); | ||
| 140 | |||
| 141 | ct = gc->chip_types; | ||
| 142 | ct->chip.irq_mask = irq_gc_mask_clr_bit; | ||
| 143 | ct->chip.irq_unmask = irq_gc_mask_set_bit; | ||
| 144 | ct->chip.irq_ack = irq_gc_mask_clr_bit; | ||
| 145 | ct->chip.irq_set_wake = irq_gc_set_wake; | ||
| 146 | ct->chip.irq_suspend = avic_irq_suspend; | ||
| 147 | ct->chip.irq_resume = avic_irq_resume; | ||
| 148 | ct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH; | ||
| 149 | ct->regs.ack = ct->regs.mask; | ||
| 150 | |||
| 151 | irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0); | ||
| 152 | } | ||
| 153 | |||
| 154 | asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs) | ||
| 155 | { | ||
| 156 | u32 nivector; | ||
| 157 | |||
| 158 | do { | ||
| 159 | nivector = __raw_readl(avic_base + AVIC_NIVECSR) >> 16; | ||
| 160 | if (nivector == 0xffff) | ||
| 161 | break; | ||
| 162 | |||
| 163 | handle_IRQ(nivector, regs); | ||
| 164 | } while (1); | ||
| 165 | } | ||
| 166 | |||
| 119 | /* | 167 | /* |
| 120 | * This function initializes the AVIC hardware and disables all the | 168 | * This function initializes the AVIC hardware and disables all the |
| 121 | * interrupts. It registers the interrupt enable and disable functions | 169 | * interrupts. It registers the interrupt enable and disable functions |
| @@ -140,11 +188,9 @@ void __init mxc_init_irq(void __iomem *irqbase) | |||
| 140 | /* all IRQ no FIQ */ | 188 | /* all IRQ no FIQ */ |
| 141 | __raw_writel(0, avic_base + AVIC_INTTYPEH); | 189 | __raw_writel(0, avic_base + AVIC_INTTYPEH); |
| 142 | __raw_writel(0, avic_base + AVIC_INTTYPEL); | 190 | __raw_writel(0, avic_base + AVIC_INTTYPEL); |
| 143 | for (i = 0; i < AVIC_NUM_IRQS; i++) { | 191 | |
| 144 | irq_set_chip_and_handler(i, &mxc_avic_chip.base, | 192 | for (i = 0; i < AVIC_NUM_IRQS; i += 32) |
| 145 | handle_level_irq); | 193 | avic_init_gc(i); |
| 146 | set_irq_flags(i, IRQF_VALID); | ||
| 147 | } | ||
| 148 | 194 | ||
| 149 | /* Set default priority value (0) for all IRQ's */ | 195 | /* Set default priority value (0) for all IRQ's */ |
| 150 | for (i = 0; i < 8; i++) | 196 | for (i = 0; i < 8; i++) |
| @@ -157,4 +203,3 @@ void __init mxc_init_irq(void __iomem *irqbase) | |||
| 157 | 203 | ||
| 158 | printk(KERN_INFO "MXC IRQ initialized\n"); | 204 | printk(KERN_INFO "MXC IRQ initialized\n"); |
| 159 | } | 205 | } |
| 160 | |||
diff --git a/arch/arm/plat-mxc/cpu.c b/arch/arm/plat-mxc/cpu.c index 386e0d52cf58..f5b7e0fa237f 100644 --- a/arch/arm/plat-mxc/cpu.c +++ b/arch/arm/plat-mxc/cpu.c | |||
| @@ -1,5 +1,6 @@ | |||
| 1 | 1 | ||
| 2 | #include <linux/module.h> | 2 | #include <linux/module.h> |
| 3 | #include <mach/hardware.h> | ||
| 3 | 4 | ||
| 4 | unsigned int __mxc_cpu_type; | 5 | unsigned int __mxc_cpu_type; |
| 5 | EXPORT_SYMBOL(__mxc_cpu_type); | 6 | EXPORT_SYMBOL(__mxc_cpu_type); |
| @@ -9,3 +10,11 @@ void mxc_set_cpu_type(unsigned int type) | |||
| 9 | __mxc_cpu_type = type; | 10 | __mxc_cpu_type = type; |
| 10 | } | 11 | } |
| 11 | 12 | ||
| 13 | void imx_print_silicon_rev(const char *cpu, int srev) | ||
| 14 | { | ||
| 15 | if (srev == IMX_CHIP_REVISION_UNKNOWN) | ||
| 16 | pr_info("CPU identified as %s, unknown revision\n", cpu); | ||
| 17 | else | ||
| 18 | pr_info("CPU identified as %s, silicon rev %d.%d\n", | ||
| 19 | cpu, (srev >> 4) & 0xf, srev & 0xf); | ||
| 20 | } | ||
diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c index 0d6ed31bdbf2..5aaa8c5f3420 100644 --- a/arch/arm/plat-mxc/devices.c +++ b/arch/arm/plat-mxc/devices.c | |||
| @@ -23,20 +23,6 @@ | |||
| 23 | #include <linux/platform_device.h> | 23 | #include <linux/platform_device.h> |
| 24 | #include <mach/common.h> | 24 | #include <mach/common.h> |
| 25 | 25 | ||
| 26 | int __init mxc_register_device(struct platform_device *pdev, void *data) | ||
| 27 | { | ||
| 28 | int ret; | ||
| 29 | |||
| 30 | pdev->dev.platform_data = data; | ||
| 31 | |||
| 32 | ret = platform_device_register(pdev); | ||
| 33 | if (ret) | ||
| 34 | pr_debug("Unable to register platform device '%s': %d\n", | ||
| 35 | pdev->name, ret); | ||
| 36 | |||
| 37 | return ret; | ||
| 38 | } | ||
| 39 | |||
| 40 | struct platform_device *__init imx_add_platform_device_dmamask( | 26 | struct platform_device *__init imx_add_platform_device_dmamask( |
| 41 | const char *name, int id, | 27 | const char *name, int id, |
| 42 | const struct resource *res, unsigned int num_resources, | 28 | const struct resource *res, unsigned int num_resources, |
diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index bd294add932c..b0f74f70b25c 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | config IMX_HAVE_PLATFORM_FEC | 1 | config IMX_HAVE_PLATFORM_FEC |
| 2 | bool | 2 | bool |
| 3 | default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX51 || SOC_IMX53 | 3 | default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX50 || SOC_IMX51 || SOC_IMX53 |
| 4 | 4 | ||
| 5 | config IMX_HAVE_PLATFORM_FLEXCAN | 5 | config IMX_HAVE_PLATFORM_FLEXCAN |
| 6 | select HAVE_CAN_FLEXCAN if CAN | 6 | select HAVE_CAN_FLEXCAN if CAN |
| @@ -31,6 +31,9 @@ config IMX_HAVE_PLATFORM_IMX_I2C | |||
| 31 | config IMX_HAVE_PLATFORM_IMX_KEYPAD | 31 | config IMX_HAVE_PLATFORM_IMX_KEYPAD |
| 32 | bool | 32 | bool |
| 33 | 33 | ||
| 34 | config IMX_HAVE_PLATFORM_PATA_IMX | ||
| 35 | bool | ||
| 36 | |||
| 34 | config IMX_HAVE_PLATFORM_IMX_SSI | 37 | config IMX_HAVE_PLATFORM_IMX_SSI |
| 35 | bool | 38 | bool |
| 36 | 39 | ||
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index b41bf972b54b..a093b454541d 100644 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile | |||
| @@ -10,6 +10,7 @@ obj-y += platform-imx-dma.o | |||
| 10 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o | 10 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o |
| 11 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o | 11 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o |
| 12 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD) += platform-imx-keypad.o | 12 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD) += platform-imx-keypad.o |
| 13 | obj-$(CONFIG_IMX_HAVE_PLATFORM_PATA_IMX) += platform-pata_imx.o | ||
| 13 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o | 14 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o |
| 14 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o | 15 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o |
| 15 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o | 16 | obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o |
diff --git a/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c index 23ce08e6ffd2..848038f301fd 100644 --- a/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c +++ b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c | |||
| @@ -36,6 +36,11 @@ const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst = | |||
| 36 | imx_fsl_usb2_udc_data_entry_single(MX35); | 36 | imx_fsl_usb2_udc_data_entry_single(MX35); |
| 37 | #endif /* ifdef CONFIG_SOC_IMX35 */ | 37 | #endif /* ifdef CONFIG_SOC_IMX35 */ |
| 38 | 38 | ||
| 39 | #ifdef CONFIG_SOC_IMX51 | ||
| 40 | const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data __initconst = | ||
| 41 | imx_fsl_usb2_udc_data_entry_single(MX51); | ||
| 42 | #endif | ||
| 43 | |||
| 39 | struct platform_device *__init imx_add_fsl_usb2_udc( | 44 | struct platform_device *__init imx_add_fsl_usb2_udc( |
| 40 | const struct imx_fsl_usb2_udc_data *data, | 45 | const struct imx_fsl_usb2_udc_data *data, |
| 41 | const struct fsl_usb2_platform_data *pdata) | 46 | const struct fsl_usb2_platform_data *pdata) |
diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c index afe60f7244a8..19ad580c0be3 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c +++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c | |||
| @@ -85,6 +85,12 @@ const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = { | |||
| 85 | imx_imx_i2c_data_entry(MX51, _id, _hwid, SZ_4K) | 85 | imx_imx_i2c_data_entry(MX51, _id, _hwid, SZ_4K) |
| 86 | imx51_imx_i2c_data_entry(0, 1), | 86 | imx51_imx_i2c_data_entry(0, 1), |
| 87 | imx51_imx_i2c_data_entry(1, 2), | 87 | imx51_imx_i2c_data_entry(1, 2), |
| 88 | { | ||
| 89 | .id = 2, | ||
| 90 | .iobase = MX51_HSI2C_DMA_BASE_ADDR, | ||
| 91 | .iosize = SZ_16K, | ||
| 92 | .irq = MX51_INT_HS_I2C, | ||
| 93 | }, | ||
| 88 | }; | 94 | }; |
| 89 | #endif /* ifdef CONFIG_SOC_IMX51 */ | 95 | #endif /* ifdef CONFIG_SOC_IMX51 */ |
| 90 | 96 | ||
diff --git a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c index e1763e03e7cb..35851d889aca 100644 --- a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c +++ b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c | |||
| @@ -49,6 +49,15 @@ const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst = | |||
| 49 | imx_mxc_ehci_data_entry_single(MX35, 1, HS); | 49 | imx_mxc_ehci_data_entry_single(MX35, 1, HS); |
| 50 | #endif /* ifdef CONFIG_SOC_IMX35 */ | 50 | #endif /* ifdef CONFIG_SOC_IMX35 */ |
| 51 | 51 | ||
| 52 | #ifdef CONFIG_SOC_IMX51 | ||
| 53 | const struct imx_mxc_ehci_data imx51_mxc_ehci_otg_data __initconst = | ||
| 54 | imx_mxc_ehci_data_entry_single(MX51, 0, OTG); | ||
| 55 | const struct imx_mxc_ehci_data imx51_mxc_ehci_hs_data[] __initconst = { | ||
| 56 | imx_mxc_ehci_data_entry_single(MX51, 1, HS1), | ||
| 57 | imx_mxc_ehci_data_entry_single(MX51, 2, HS2), | ||
| 58 | }; | ||
| 59 | #endif /* ifdef CONFIG_SOC_IMX51 */ | ||
| 60 | |||
| 52 | struct platform_device *__init imx_add_mxc_ehci( | 61 | struct platform_device *__init imx_add_mxc_ehci( |
| 53 | const struct imx_mxc_ehci_data *data, | 62 | const struct imx_mxc_ehci_data *data, |
| 54 | const struct mxc_usbh_platform_data *pdata) | 63 | const struct mxc_usbh_platform_data *pdata) |
diff --git a/arch/arm/plat-mxc/devices/platform-pata_imx.c b/arch/arm/plat-mxc/devices/platform-pata_imx.c new file mode 100644 index 000000000000..70e2f2a44714 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-pata_imx.c | |||
| @@ -0,0 +1,59 @@ | |||
| 1 | /* | ||
| 2 | * This program is free software; you can redistribute it and/or modify it under | ||
| 3 | * the terms of the GNU General Public License version 2 as published by the | ||
| 4 | * Free Software Foundation. | ||
| 5 | */ | ||
| 6 | #include <mach/hardware.h> | ||
| 7 | #include <mach/devices-common.h> | ||
| 8 | |||
| 9 | #define imx_pata_imx_data_entry_single(soc, _size) \ | ||
| 10 | { \ | ||
| 11 | .iobase = soc ## _ATA_BASE_ADDR, \ | ||
| 12 | .iosize = _size, \ | ||
| 13 | .irq = soc ## _INT_ATA, \ | ||
| 14 | } | ||
| 15 | |||
| 16 | #ifdef CONFIG_SOC_IMX27 | ||
| 17 | const struct imx_pata_imx_data imx27_pata_imx_data __initconst = | ||
| 18 | imx_pata_imx_data_entry_single(MX27, SZ_4K); | ||
| 19 | #endif /* ifdef CONFIG_SOC_IMX27 */ | ||
| 20 | |||
| 21 | #ifdef CONFIG_SOC_IMX31 | ||
| 22 | const struct imx_pata_imx_data imx31_pata_imx_data __initconst = | ||
| 23 | imx_pata_imx_data_entry_single(MX31, SZ_16K); | ||
| 24 | #endif /* ifdef CONFIG_SOC_IMX31 */ | ||
| 25 | |||
| 26 | #ifdef CONFIG_SOC_IMX35 | ||
| 27 | const struct imx_pata_imx_data imx35_pata_imx_data __initconst = | ||
| 28 | imx_pata_imx_data_entry_single(MX35, SZ_16K); | ||
| 29 | #endif /* ifdef CONFIG_SOC_IMX35 */ | ||
| 30 | |||
| 31 | #ifdef CONFIG_SOC_IMX51 | ||
| 32 | const struct imx_pata_imx_data imx51_pata_imx_data __initconst = | ||
| 33 | imx_pata_imx_data_entry_single(MX51, SZ_16K); | ||
| 34 | #endif /* ifdef CONFIG_SOC_IMX51 */ | ||
| 35 | |||
| 36 | #ifdef CONFIG_SOC_IMX53 | ||
| 37 | const struct imx_pata_imx_data imx53_pata_imx_data __initconst = | ||
| 38 | imx_pata_imx_data_entry_single(MX53, SZ_16K); | ||
| 39 | #endif /* ifdef CONFIG_SOC_IMX53 */ | ||
| 40 | |||
| 41 | struct platform_device *__init imx_add_pata_imx( | ||
| 42 | const struct imx_pata_imx_data *data) | ||
| 43 | { | ||
| 44 | struct resource res[] = { | ||
| 45 | { | ||
| 46 | .start = data->iobase, | ||
| 47 | .end = data->iobase + data->iosize - 1, | ||
| 48 | .flags = IORESOURCE_MEM, | ||
| 49 | }, | ||
| 50 | { | ||
| 51 | .start = data->irq, | ||
| 52 | .end = data->irq, | ||
| 53 | .flags = IORESOURCE_IRQ, | ||
| 54 | }, | ||
| 55 | }; | ||
| 56 | return imx_add_platform_device("pata_imx", -1, | ||
| 57 | res, ARRAY_SIZE(res), NULL, 0); | ||
| 58 | } | ||
| 59 | |||
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 4e3d97890d69..ace4bb550edc 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h | |||
| @@ -66,10 +66,35 @@ extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, | |||
| 66 | unsigned long ckih1, unsigned long ckih2); | 66 | unsigned long ckih1, unsigned long ckih2); |
| 67 | extern struct platform_device *mxc_register_gpio(char *name, int id, | 67 | extern struct platform_device *mxc_register_gpio(char *name, int id, |
| 68 | resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); | 68 | resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); |
| 69 | extern int mxc_register_device(struct platform_device *pdev, void *data); | ||
| 70 | extern void mxc_set_cpu_type(unsigned int type); | 69 | extern void mxc_set_cpu_type(unsigned int type); |
| 71 | extern void mxc_arch_reset_init(void __iomem *); | 70 | extern void mxc_arch_reset_init(void __iomem *); |
| 72 | extern void mx51_efikamx_reset(void); | 71 | extern void mx51_efikamx_reset(void); |
| 73 | extern int mx53_revision(void); | 72 | extern int mx53_revision(void); |
| 74 | extern int mx53_display_revision(void); | 73 | extern int mx53_display_revision(void); |
| 74 | |||
| 75 | enum mxc_cpu_pwr_mode { | ||
| 76 | WAIT_CLOCKED, /* wfi only */ | ||
| 77 | WAIT_UNCLOCKED, /* WAIT */ | ||
| 78 | WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */ | ||
| 79 | STOP_POWER_ON, /* just STOP */ | ||
| 80 | STOP_POWER_OFF, /* STOP + SRPG */ | ||
| 81 | }; | ||
| 82 | |||
| 83 | extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode); | ||
| 84 | extern void (*imx_idle)(void); | ||
| 85 | extern void imx_print_silicon_rev(const char *cpu, int srev); | ||
| 86 | |||
| 87 | void avic_handle_irq(struct pt_regs *); | ||
| 88 | void tzic_handle_irq(struct pt_regs *); | ||
| 89 | |||
| 90 | #define imx1_handle_irq avic_handle_irq | ||
| 91 | #define imx21_handle_irq avic_handle_irq | ||
| 92 | #define imx25_handle_irq avic_handle_irq | ||
| 93 | #define imx27_handle_irq avic_handle_irq | ||
| 94 | #define imx31_handle_irq avic_handle_irq | ||
| 95 | #define imx35_handle_irq avic_handle_irq | ||
| 96 | #define imx50_handle_irq tzic_handle_irq | ||
| 97 | #define imx51_handle_irq tzic_handle_irq | ||
| 98 | #define imx53_handle_irq tzic_handle_irq | ||
| 99 | |||
| 75 | #endif | 100 | #endif |
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 524538aabc4b..4cbad45edc15 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h | |||
| @@ -251,6 +251,14 @@ struct platform_device *__init imx_add_mxc_nand( | |||
| 251 | const struct imx_mxc_nand_data *data, | 251 | const struct imx_mxc_nand_data *data, |
| 252 | const struct mxc_nand_platform_data *pdata); | 252 | const struct mxc_nand_platform_data *pdata); |
| 253 | 253 | ||
| 254 | struct imx_pata_imx_data { | ||
| 255 | resource_size_t iobase; | ||
| 256 | resource_size_t iosize; | ||
| 257 | resource_size_t irq; | ||
| 258 | }; | ||
| 259 | struct platform_device *__init imx_add_pata_imx( | ||
| 260 | const struct imx_pata_imx_data *data); | ||
| 261 | |||
| 254 | struct imx_mxc_pwm_data { | 262 | struct imx_mxc_pwm_data { |
| 255 | int id; | 263 | int id; |
| 256 | resource_size_t iobase; | 264 | resource_size_t iobase; |
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S index 066d464d322d..842fbcb0d6cc 100644 --- a/arch/arm/plat-mxc/include/mach/entry-macro.S +++ b/arch/arm/plat-mxc/include/mach/entry-macro.S | |||
| @@ -9,72 +9,16 @@ | |||
| 9 | * published by the Free Software Foundation. | 9 | * published by the Free Software Foundation. |
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | #include <mach/hardware.h> | 12 | /* Unused, we use CONFIG_MULTI_IRQ_HANDLER */ |
| 13 | 13 | ||
| 14 | #define AVIC_NIMASK 0x04 | ||
| 15 | |||
| 16 | @ this macro disables fast irq (not implemented) | ||
| 17 | .macro disable_fiq | 14 | .macro disable_fiq |
| 18 | .endm | 15 | .endm |
| 19 | 16 | ||
| 20 | .macro get_irqnr_preamble, base, tmp | 17 | .macro get_irqnr_preamble, base, tmp |
| 21 | #ifndef CONFIG_MXC_TZIC | ||
| 22 | ldr \base, =avic_base | ||
| 23 | ldr \base, [\base] | ||
| 24 | #ifdef CONFIG_MXC_IRQ_PRIOR | ||
| 25 | ldr r4, [\base, #AVIC_NIMASK] | ||
| 26 | #endif | ||
| 27 | #elif defined CONFIG_MXC_TZIC | ||
| 28 | ldr \base, =tzic_base | ||
| 29 | ldr \base, [\base] | ||
| 30 | #endif /* CONFIG_MXC_TZIC */ | ||
| 31 | .endm | 18 | .endm |
| 32 | 19 | ||
| 33 | .macro arch_ret_to_user, tmp1, tmp2 | 20 | .macro arch_ret_to_user, tmp1, tmp2 |
| 34 | .endm | 21 | .endm |
| 35 | 22 | ||
| 36 | @ this macro checks which interrupt occurred | ||
| 37 | @ and returns its number in irqnr | ||
| 38 | @ and returns if an interrupt occurred in irqstat | ||
| 39 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | 23 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp |
| 40 | #ifndef CONFIG_MXC_TZIC | ||
| 41 | @ Load offset & priority of the highest priority | ||
| 42 | @ interrupt pending from AVIC_NIVECSR | ||
| 43 | ldr \irqstat, [\base, #0x40] | ||
| 44 | @ Shift to get the decoded IRQ number, using ASR so | ||
| 45 | @ 'no interrupt pending' becomes 0xffffffff | ||
| 46 | mov \irqnr, \irqstat, asr #16 | ||
| 47 | @ set zero flag if IRQ + 1 == 0 | ||
| 48 | adds \tmp, \irqnr, #1 | ||
| 49 | #ifdef CONFIG_MXC_IRQ_PRIOR | ||
| 50 | bicne \tmp, \irqstat, #0xFFFFFFE0 | ||
| 51 | strne \tmp, [\base, #AVIC_NIMASK] | ||
| 52 | streq r4, [\base, #AVIC_NIMASK] | ||
| 53 | #endif | ||
| 54 | #elif defined CONFIG_MXC_TZIC | ||
| 55 | @ Load offset & priority of the highest priority | ||
| 56 | @ interrupt pending. | ||
| 57 | @ 0x080 is INTSEC0 register | ||
| 58 | @ 0xD80 is HIPND0 register | ||
| 59 | mov \irqnr, #0 | ||
| 60 | 1000: add \irqstat, \base, \irqnr, lsr #3 | ||
| 61 | ldr \tmp, [\irqstat, #0xd80] | ||
| 62 | ldr \irqstat, [\irqstat, #0x080] | ||
| 63 | ands \tmp, \tmp, \irqstat | ||
| 64 | bne 1001f | ||
| 65 | add \irqnr, \irqnr, #32 | ||
| 66 | cmp \irqnr, #128 | ||
| 67 | blo 1000b | ||
| 68 | b 2001f | ||
| 69 | 1001: mov \irqstat, #1 | ||
| 70 | 1002: tst \tmp, \irqstat | ||
| 71 | bne 2002f | ||
| 72 | movs \tmp, \tmp, lsr #1 | ||
| 73 | addne \irqnr, \irqnr, #1 | ||
| 74 | bne 1002b | ||
| 75 | 2001: | ||
| 76 | mov \irqnr, #0 | ||
| 77 | 2002: | ||
| 78 | movs \irqnr, \irqnr | ||
| 79 | #endif | ||
| 80 | .endm | 24 | .endm |
diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h index 31c820c1b796..44af0064ba1a 100644 --- a/arch/arm/plat-mxc/include/mach/gpio.h +++ b/arch/arm/plat-mxc/include/mach/gpio.h | |||
| @@ -23,17 +23,10 @@ | |||
| 23 | #include <mach/hardware.h> | 23 | #include <mach/hardware.h> |
| 24 | #include <asm-generic/gpio.h> | 24 | #include <asm-generic/gpio.h> |
| 25 | 25 | ||
| 26 | |||
| 27 | /* There's a off-by-one betweem the gpio bank number and the gpiochip */ | ||
| 28 | /* range e.g. GPIO_1_5 is gpio 5 under linux */ | ||
| 29 | #define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr)) | ||
| 30 | |||
| 31 | /* use gpiolib dispatchers */ | 26 | /* use gpiolib dispatchers */ |
| 32 | #define gpio_get_value __gpio_get_value | 27 | #define gpio_get_value __gpio_get_value |
| 33 | #define gpio_set_value __gpio_set_value | 28 | #define gpio_set_value __gpio_set_value |
| 34 | #define gpio_cansleep __gpio_cansleep | 29 | #define gpio_cansleep __gpio_cansleep |
| 35 | 30 | #define gpio_to_irq __gpio_to_irq | |
| 36 | #define gpio_to_irq(gpio) (MXC_GPIO_IRQ_START + (gpio)) | ||
| 37 | #define irq_to_gpio(irq) ((irq) - MXC_GPIO_IRQ_START) | ||
| 38 | 31 | ||
| 39 | #endif | 32 | #endif |
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index a8bfd565dcad..eba3118adfbb 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h | |||
| @@ -81,11 +81,16 @@ | |||
| 81 | * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000 | 81 | * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000 |
| 82 | * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000 | 82 | * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000 |
| 83 | * mx51: | 83 | * mx51: |
| 84 | * TZIC 0xe0000000+0x004000 -> 0xf5000000+0x004000 | ||
| 84 | * IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000 | 85 | * IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000 |
| 85 | * DEBUG 0x60000000+0x100000 -> 0xf5000000+0x100000 | ||
| 86 | * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000 | 86 | * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000 |
| 87 | * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000 | 87 | * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000 |
| 88 | * AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000 | 88 | * AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000 |
| 89 | * mx53: | ||
| 90 | * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000 | ||
| 91 | * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000 | ||
| 92 | * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000 | ||
| 93 | * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000 | ||
| 89 | */ | 94 | */ |
| 90 | #define IMX_IO_P2V(x) ( \ | 95 | #define IMX_IO_P2V(x) ( \ |
| 91 | 0xf4000000 + \ | 96 | 0xf4000000 + \ |
| @@ -116,4 +121,10 @@ | |||
| 116 | .type = _type, \ | 121 | .type = _type, \ |
| 117 | } | 122 | } |
| 118 | 123 | ||
| 124 | /* There's a off-by-one betweem the gpio bank number and the gpiochip */ | ||
| 125 | /* range e.g. GPIO_1_5 is gpio 5 under linux */ | ||
| 126 | #define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr)) | ||
| 127 | |||
| 128 | #define IMX_GPIO_TO_IRQ(gpio) (MXC_GPIO_IRQ_START + (gpio)) | ||
| 129 | |||
| 119 | #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ | 130 | #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/io.h b/arch/arm/plat-mxc/include/mach/io.h index 4347a87d2bb0..338300b18b00 100644 --- a/arch/arm/plat-mxc/include/mach/io.h +++ b/arch/arm/plat-mxc/include/mach/io.h | |||
| @@ -14,32 +14,22 @@ | |||
| 14 | /* Allow IO space to be anywhere in the memory */ | 14 | /* Allow IO space to be anywhere in the memory */ |
| 15 | #define IO_SPACE_LIMIT 0xffffffff | 15 | #define IO_SPACE_LIMIT 0xffffffff |
| 16 | 16 | ||
| 17 | #if defined(CONFIG_SOC_IMX31) || defined(CONFIG_SOC_IMX35) | ||
| 18 | #include <mach/hardware.h> | ||
| 19 | |||
| 20 | #define __arch_ioremap __imx_ioremap | 17 | #define __arch_ioremap __imx_ioremap |
| 21 | #define __arch_iounmap __iounmap | 18 | #define __arch_iounmap __iounmap |
| 22 | 19 | ||
| 23 | #define addr_in_module(addr, mod) \ | 20 | #define addr_in_module(addr, mod) \ |
| 24 | ((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE) | 21 | ((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE) |
| 25 | 22 | ||
| 23 | extern void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int); | ||
| 24 | |||
| 26 | static inline void __iomem * | 25 | static inline void __iomem * |
| 27 | __imx_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) | 26 | __imx_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) |
| 28 | { | 27 | { |
| 29 | if (mtype == MT_DEVICE && (cpu_is_mx31() || cpu_is_mx35())) { | 28 | if (imx_ioremap != NULL) |
| 30 | /* | 29 | return imx_ioremap(phys_addr, size, mtype); |
| 31 | * Access all peripherals below 0x80000000 as nonshared device | 30 | else |
| 32 | * on mx3, but leave l2cc alone. Otherwise cache corruptions | 31 | return __arm_ioremap(phys_addr, size, mtype); |
| 33 | * can occur. | ||
| 34 | */ | ||
| 35 | if (phys_addr < 0x80000000 && | ||
| 36 | !addr_in_module(phys_addr, MX3x_L2CC)) | ||
| 37 | mtype = MT_DEVICE_NONSHARED; | ||
| 38 | } | ||
| 39 | |||
| 40 | return __arm_ioremap(phys_addr, size, mtype); | ||
| 41 | } | 32 | } |
| 42 | #endif | ||
| 43 | 33 | ||
| 44 | /* io address mapping macro */ | 34 | /* io address mapping macro */ |
| 45 | #define __io(a) __typesafe_io(a) | 35 | #define __io(a) __typesafe_io(a) |
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h index c92f0b1f216f..63f22a009a65 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h | |||
| @@ -735,6 +735,7 @@ enum iomux_pins { | |||
| 735 | #define MX31_PIN_KEY_COL5_KEY_COL5 IOMUX_MODE(MX31_PIN_KEY_COL5, IOMUX_CONFIG_FUNC) | 735 | #define MX31_PIN_KEY_COL5_KEY_COL5 IOMUX_MODE(MX31_PIN_KEY_COL5, IOMUX_CONFIG_FUNC) |
| 736 | #define MX31_PIN_KEY_COL6_KEY_COL6 IOMUX_MODE(MX31_PIN_KEY_COL6, IOMUX_CONFIG_FUNC) | 736 | #define MX31_PIN_KEY_COL6_KEY_COL6 IOMUX_MODE(MX31_PIN_KEY_COL6, IOMUX_CONFIG_FUNC) |
| 737 | #define MX31_PIN_KEY_COL7_KEY_COL7 IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_FUNC) | 737 | #define MX31_PIN_KEY_COL7_KEY_COL7 IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_FUNC) |
| 738 | #define MX31_PIN_WATCHDOG_RST__WATCHDOG_RST IOMUX_MODE(MX31_PIN_WATCHDOG_RST, IOMUX_CONFIG_FUNC) | ||
| 738 | 739 | ||
| 739 | 740 | ||
| 740 | /* | 741 | /* |
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h index df6acc066fb1..c7f5169a6a54 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h | |||
| @@ -14,6 +14,8 @@ | |||
| 14 | #define __MACH_IOMUX_MX51_H__ | 14 | #define __MACH_IOMUX_MX51_H__ |
| 15 | 15 | ||
| 16 | #include <mach/iomux-v3.h> | 16 | #include <mach/iomux-v3.h> |
| 17 | #define __NA_ 0x000 | ||
| 18 | |||
| 17 | 19 | ||
| 18 | /* Pad control groupings */ | 20 | /* Pad control groupings */ |
| 19 | #define MX51_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \ | 21 | #define MX51_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \ |
| @@ -47,1521 +49,765 @@ | |||
| 47 | 49 | ||
| 48 | /* Raw pin modes without pad control */ | 50 | /* Raw pin modes without pad control */ |
| 49 | /* PAD MUX ALT INPSE PATH PADCTRL */ | 51 | /* PAD MUX ALT INPSE PATH PADCTRL */ |
| 50 | #define _MX51_PAD_EIM_D16__AUD4_RXFS IOMUX_PAD(0x3f0, 0x5c, 5, 0x0000, 0, 0) | ||
| 51 | #define _MX51_PAD_EIM_D16__AUD5_TXD IOMUX_PAD(0x3f0, 0x5c, 7, 0x08d8, 0, 0) | ||
| 52 | #define _MX51_PAD_EIM_D16__EIM_D16 IOMUX_PAD(0x3f0, 0x5c, 0, 0x0000, 0, 0) | ||
| 53 | #define _MX51_PAD_EIM_D16__GPIO2_0 IOMUX_PAD(0x3f0, 0x5c, 1, 0x0000, 0, 0) | ||
| 54 | #define _MX51_PAD_EIM_D16__I2C1_SDA IOMUX_PAD(0x3f0, 0x5c, 0x14, 0x09b4, 0, 0) | ||
| 55 | #define _MX51_PAD_EIM_D16__UART2_CTS IOMUX_PAD(0x3f0, 0x5c, 3, 0x0000, 0, 0) | ||
| 56 | #define _MX51_PAD_EIM_D16__USBH2_DATA0 IOMUX_PAD(0x3f0, 0x5c, 2, 0x0000, 0, 0) | ||
| 57 | #define _MX51_PAD_EIM_D17__AUD5_RXD IOMUX_PAD(0x3f4, 0x60, 7, 0x08d4, 0, 0) | ||
| 58 | #define _MX51_PAD_EIM_D17__EIM_D17 IOMUX_PAD(0x3f4, 0x60, 0, 0x0000, 0, 0) | ||
| 59 | #define _MX51_PAD_EIM_D17__GPIO2_1 IOMUX_PAD(0x3f4, 0x60, 1, 0x0000, 0, 0) | ||
| 60 | #define _MX51_PAD_EIM_D17__UART2_RXD IOMUX_PAD(0x3f4, 0x60, 3, 0x09ec, 0, 0) | ||
| 61 | #define _MX51_PAD_EIM_D17__UART3_CTS IOMUX_PAD(0x3f4, 0x60, 4, 0x0000, 0, 0) | ||
| 62 | #define _MX51_PAD_EIM_D17__USBH2_DATA1 IOMUX_PAD(0x3f4, 0x60, 2, 0x0000, 0, 0) | ||
| 63 | #define _MX51_PAD_EIM_D18__AUD5_TXC IOMUX_PAD(0x3f8, 0x64, 7, 0x08e4, 0, 0) | ||
| 64 | #define _MX51_PAD_EIM_D18__EIM_D18 IOMUX_PAD(0x3f8, 0x64, 0, 0x0000, 0, 0) | ||
| 65 | #define _MX51_PAD_EIM_D18__GPIO2_2 IOMUX_PAD(0x3f8, 0x64, 1, 0x0000, 0, 0) | ||
| 66 | #define _MX51_PAD_EIM_D18__UART2_TXD IOMUX_PAD(0x3f8, 0x64, 3, 0x0000, 0, 0) | ||
| 67 | #define _MX51_PAD_EIM_D18__UART3_RTS IOMUX_PAD(0x3f8, 0x64, 4, 0x09f0, 1, 0) | ||
| 68 | #define _MX51_PAD_EIM_D18__USBH2_DATA2 IOMUX_PAD(0x3f8, 0x64, 2, 0x0000, 0, 0) | ||
| 69 | #define _MX51_PAD_EIM_D19__AUD4_RXC IOMUX_PAD(0x3fc, 0x68, 5, 0x0000, 0, 0) | ||
| 70 | #define _MX51_PAD_EIM_D19__AUD5_TXFS IOMUX_PAD(0x3fc, 0x68, 7, 0x08e8, 0, 0) | ||
| 71 | #define _MX51_PAD_EIM_D19__EIM_D19 IOMUX_PAD(0x3fc, 0x68, 0, 0x0000, 0, 0) | ||
| 72 | #define _MX51_PAD_EIM_D19__GPIO2_3 IOMUX_PAD(0x3fc, 0x68, 1, 0x0000, 0, 0) | ||
| 73 | #define _MX51_PAD_EIM_D19__I2C1_SCL IOMUX_PAD(0x3fc, 0x68, 0x14, 0x09b0, 0, 0) | ||
| 74 | #define _MX51_PAD_EIM_D19__UART2_RTS IOMUX_PAD(0x3fc, 0x68, 3, 0x09e8, 1, 0) | ||
| 75 | #define _MX51_PAD_EIM_D19__USBH2_DATA3 IOMUX_PAD(0x3fc, 0x68, 2, 0x0000, 0, 0) | ||
| 76 | #define _MX51_PAD_EIM_D20__AUD4_TXD IOMUX_PAD(0x400, 0x6c, 5, 0x08c8, 0, 0) | ||
| 77 | #define _MX51_PAD_EIM_D20__EIM_D20 IOMUX_PAD(0x400, 0x6c, 0, 0x0000, 0, 0) | ||
| 78 | #define _MX51_PAD_EIM_D20__GPIO2_4 IOMUX_PAD(0x400, 0x6c, 1, 0x0000, 0, 0) | ||
| 79 | #define _MX51_PAD_EIM_D20__SRTC_ALARM_DEB IOMUX_PAD(0x400, 0x6c, 4, 0x0000, 0, 0) | ||
| 80 | #define _MX51_PAD_EIM_D20__USBH2_DATA4 IOMUX_PAD(0x400, 0x6c, 2, 0x0000, 0, 0) | ||
| 81 | #define _MX51_PAD_EIM_D21__AUD4_RXD IOMUX_PAD(0x404, 0x70, 5, 0x08c4, 0, 0) | ||
| 82 | #define _MX51_PAD_EIM_D21__EIM_D21 IOMUX_PAD(0x404, 0x70, 0, 0x0000, 0, 0) | ||
| 83 | #define _MX51_PAD_EIM_D21__GPIO2_5 IOMUX_PAD(0x404, 0x70, 1, 0x0000, 0, 0) | ||
| 84 | #define _MX51_PAD_EIM_D21__SRTC_ALARM_DEB IOMUX_PAD(0x404, 0x70, 3, 0x0000, 0, 0) | ||
| 85 | #define _MX51_PAD_EIM_D21__USBH2_DATA5 IOMUX_PAD(0x404, 0x70, 2, 0x0000, 0, 0) | ||
| 86 | #define _MX51_PAD_EIM_D22__AUD4_TXC IOMUX_PAD(0x408, 0x74, 5, 0x08cc, 0, 0) | ||
| 87 | #define _MX51_PAD_EIM_D22__EIM_D22 IOMUX_PAD(0x408, 0x74, 0, 0x0000, 0, 0) | ||
| 88 | #define _MX51_PAD_EIM_D22__GPIO2_6 IOMUX_PAD(0x408, 0x74, 1, 0x0000, 0, 0) | ||
| 89 | #define _MX51_PAD_EIM_D22__USBH2_DATA6 IOMUX_PAD(0x408, 0x74, 2, 0x0000, 0, 0) | ||
| 90 | #define _MX51_PAD_EIM_D23__AUD4_TXFS IOMUX_PAD(0x40c, 0x78, 5, 0x08d0, 0, 0) | ||
| 91 | #define _MX51_PAD_EIM_D23__EIM_D23 IOMUX_PAD(0x40c, 0x78, 0, 0x0000, 0, 0) | ||
| 92 | #define _MX51_PAD_EIM_D23__GPIO2_7 IOMUX_PAD(0x40c, 0x78, 1, 0x0000, 0, 0) | ||
| 93 | #define _MX51_PAD_EIM_D23__SPDIF_OUT1 IOMUX_PAD(0x40c, 0x78, 4, 0x0000, 0, 0) | ||
| 94 | #define _MX51_PAD_EIM_D23__USBH2_DATA7 IOMUX_PAD(0x40c, 0x78, 2, 0x0000, 0, 0) | ||
| 95 | #define _MX51_PAD_EIM_D24__AUD6_RXFS IOMUX_PAD(0x410, 0x7c, 5, 0x08f8, 0, 0) | ||
| 96 | #define _MX51_PAD_EIM_D24__EIM_D24 IOMUX_PAD(0x410, 0x7c, 0, 0x0000, 0, 0) | ||
| 97 | #define _MX51_PAD_EIM_D24__GPIO2_8 IOMUX_PAD(0x410, 0x7c, 1, 0x0000, 0, 0) | ||
| 98 | #define _MX51_PAD_EIM_D24__I2C2_SDA IOMUX_PAD(0x410, 0x7c, 0x14, 0x09bc, 0, 0) | ||
| 99 | #define _MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x7c, 3, 0x0000, 0, 0) | ||
| 100 | #define _MX51_PAD_EIM_D24__USBOTG_DATA0 IOMUX_PAD(0x410, 0x7c, 2, 0x0000, 0, 0) | ||
| 101 | #define _MX51_PAD_EIM_D25__EIM_D25 IOMUX_PAD(0x414, 0x80, 0, 0x0000, 0, 0) | ||
| 102 | #define _MX51_PAD_EIM_D25__KEY_COL6 IOMUX_PAD(0x414, 0x80, 1, 0x09c8, 0, 0) | ||
| 103 | #define _MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x80, 4, 0x0000, 0, 0) | ||
| 104 | #define _MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x80, 3, 0x09f4, 0, 0) | ||
| 105 | #define _MX51_PAD_EIM_D25__USBOTG_DATA1 IOMUX_PAD(0x414, 0x80, 2, 0x0000, 0, 0) | ||
| 106 | #define _MX51_PAD_EIM_D26__EIM_D26 IOMUX_PAD(0x418, 0x84, 0, 0x0000, 0, 0) | ||
| 107 | #define _MX51_PAD_EIM_D26__KEY_COL7 IOMUX_PAD(0x418, 0x84, 1, 0x09cc, 0, 0) | ||
| 108 | #define _MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x84, 4, 0x09e8, 3, 0) | ||
| 109 | #define _MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x84, 3, 0x0000, 0, 0) | ||
| 110 | #define _MX51_PAD_EIM_D26__USBOTG_DATA2 IOMUX_PAD(0x418, 0x84, 2, 0x0000, 0, 0) | ||
| 111 | #define _MX51_PAD_EIM_D27__AUD6_RXC IOMUX_PAD(0x41c, 0x88, 5, 0x08f4, 0, 0) | ||
| 112 | #define _MX51_PAD_EIM_D27__EIM_D27 IOMUX_PAD(0x41c, 0x88, 0, 0x0000, 0, 0) | ||
| 113 | #define _MX51_PAD_EIM_D27__GPIO2_9 IOMUX_PAD(0x41c, 0x88, 1, 0x0000, 0, 0) | ||
| 114 | #define _MX51_PAD_EIM_D27__I2C2_SCL IOMUX_PAD(0x41c, 0x88, 0x14, 0x09b8, 0, 0) | ||
| 115 | #define _MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x88, 3, 0x09f0, 3, 0) | ||
| 116 | #define _MX51_PAD_EIM_D27__USBOTG_DATA3 IOMUX_PAD(0x41c, 0x88, 2, 0x0000, 0, 0) | ||
| 117 | #define _MX51_PAD_EIM_D28__AUD6_TXD IOMUX_PAD(0x420, 0x8c, 5, 0x08f0, 0, 0) | ||
| 118 | #define _MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x8c, 0, 0x0000, 0, 0) | ||
| 119 | #define _MX51_PAD_EIM_D28__KEY_ROW4 IOMUX_PAD(0x420, 0x8c, 1, 0x09d0, 0, 0) | ||
| 120 | #define _MX51_PAD_EIM_D28__USBOTG_DATA4 IOMUX_PAD(0x420, 0x8c, 2, 0x0000, 0, 0) | ||
| 121 | #define _MX51_PAD_EIM_D29__AUD6_RXD IOMUX_PAD(0x424, 0x90, 5, 0x08ec, 0, 0) | ||
| 122 | #define _MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x90, 0, 0x0000, 0, 0) | ||
| 123 | #define _MX51_PAD_EIM_D29__KEY_ROW5 IOMUX_PAD(0x424, 0x90, 1, 0x09d4, 0, 0) | ||
| 124 | #define _MX51_PAD_EIM_D29__USBOTG_DATA5 IOMUX_PAD(0x424, 0x90, 2, 0x0000, 0, 0) | ||
| 125 | #define _MX51_PAD_EIM_D30__AUD6_TXC IOMUX_PAD(0x428, 0x94, 5, 0x08fc, 0, 0) | ||
| 126 | #define _MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x94, 0, 0x0000, 0, 0) | ||
| 127 | #define _MX51_PAD_EIM_D30__KEY_ROW6 IOMUX_PAD(0x428, 0x94, 1, 0x09d8, 0, 0) | ||
| 128 | #define _MX51_PAD_EIM_D30__USBOTG_DATA6 IOMUX_PAD(0x428, 0x94, 2, 0x0000, 0, 0) | ||
| 129 | #define _MX51_PAD_EIM_D31__AUD6_TXFS IOMUX_PAD(0x42c, 0x98, 5, 0x0900, 0, 0) | ||
| 130 | #define _MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x98, 0, 0x0000, 0, 0) | ||
| 131 | #define _MX51_PAD_EIM_D31__KEY_ROW7 IOMUX_PAD(0x42c, 0x98, 1, 0x09dc, 0, 0) | ||
| 132 | #define _MX51_PAD_EIM_D31__USBOTG_DATA7 IOMUX_PAD(0x42c, 0x98, 2, 0x0000, 0, 0) | ||
| 133 | #define _MX51_PAD_EIM_A16__EIM_A16 IOMUX_PAD(0x430, 0x9c, 0, 0x0000, 0, 0) | ||
| 134 | #define _MX51_PAD_EIM_A16__GPIO2_10 IOMUX_PAD(0x430, 0x9c, 1, 0x0000, 0, 0) | ||
| 135 | #define _MX51_PAD_EIM_A16__OSC_FREQ_SEL0 IOMUX_PAD(0x430, 0x9c, 7, 0x0000, 0, 0) | ||
| 136 | #define _MX51_PAD_EIM_A17__EIM_A17 IOMUX_PAD(0x434, 0xa0, 0, 0x0000, 0, 0) | ||
| 137 | #define _MX51_PAD_EIM_A17__GPIO2_11 IOMUX_PAD(0x434, 0xa0, 1, 0x0000, 0, 0) | ||
| 138 | #define _MX51_PAD_EIM_A17__OSC_FREQ_SEL1 IOMUX_PAD(0x434, 0xa0, 7, 0x0000, 0, 0) | ||
| 139 | #define _MX51_PAD_EIM_A18__BOOT_LPB0 IOMUX_PAD(0x438, 0xa4, 7, 0x0000, 0, 0) | ||
| 140 | #define _MX51_PAD_EIM_A18__EIM_A18 IOMUX_PAD(0x438, 0xa4, 0, 0x0000, 0, 0) | ||
| 141 | #define _MX51_PAD_EIM_A18__GPIO2_12 IOMUX_PAD(0x438, 0xa4, 1, 0x0000, 0, 0) | ||
| 142 | #define _MX51_PAD_EIM_A19__BOOT_LPB1 IOMUX_PAD(0x43c, 0xa8, 7, 0x0000, 0, 0) | ||
| 143 | #define _MX51_PAD_EIM_A19__EIM_A19 IOMUX_PAD(0x43c, 0xa8, 0, 0x0000, 0, 0) | ||
| 144 | #define _MX51_PAD_EIM_A19__GPIO2_13 IOMUX_PAD(0x43c, 0xa8, 1, 0x0000, 0, 0) | ||
| 145 | #define _MX51_PAD_EIM_A20__BOOT_UART_SRC0 IOMUX_PAD(0x440, 0xac, 7, 0x0000, 0, 0) | ||
| 146 | #define _MX51_PAD_EIM_A20__EIM_A20 IOMUX_PAD(0x440, 0xac, 0, 0x0000, 0, 0) | ||
| 147 | #define _MX51_PAD_EIM_A20__GPIO2_14 IOMUX_PAD(0x440, 0xac, 1, 0x0000, 0, 0) | ||
| 148 | #define _MX51_PAD_EIM_A21__BOOT_UART_SRC1 IOMUX_PAD(0x444, 0xb0, 7, 0x0000, 0, 0) | ||
| 149 | #define _MX51_PAD_EIM_A21__EIM_A21 IOMUX_PAD(0x444, 0xb0, 0, 0x0000, 0, 0) | ||
| 150 | #define _MX51_PAD_EIM_A21__GPIO2_15 IOMUX_PAD(0x444, 0xb0, 1, 0x0000, 0, 0) | ||
| 151 | #define _MX51_PAD_EIM_A22__EIM_A22 IOMUX_PAD(0x448, 0xb4, 0, 0x0000, 0, 0) | ||
| 152 | #define _MX51_PAD_EIM_A22__GPIO2_16 IOMUX_PAD(0x448, 0xb4, 1, 0x0000, 0, 0) | ||
| 153 | #define _MX51_PAD_EIM_A23__BOOT_HPN_EN IOMUX_PAD(0x44c, 0xb8, 7, 0x0000, 0, 0) | ||
| 154 | #define _MX51_PAD_EIM_A23__EIM_A23 IOMUX_PAD(0x44c, 0xb8, 0, 0x0000, 0, 0) | ||
| 155 | #define _MX51_PAD_EIM_A23__GPIO2_17 IOMUX_PAD(0x44c, 0xb8, 1, 0x0000, 0, 0) | ||
| 156 | #define _MX51_PAD_EIM_A24__EIM_A24 IOMUX_PAD(0x450, 0xbc, 0, 0x0000, 0, 0) | ||
| 157 | #define _MX51_PAD_EIM_A24__GPIO2_18 IOMUX_PAD(0x450, 0xbc, 1, 0x0000, 0, 0) | ||
| 158 | #define _MX51_PAD_EIM_A24__USBH2_CLK IOMUX_PAD(0x450, 0xbc, 2, 0x0000, 0, 0) | ||
| 159 | #define _MX51_PAD_EIM_A25__DISP1_PIN4 IOMUX_PAD(0x454, 0xc0, 6, 0x0000, 0, 0) | ||
| 160 | #define _MX51_PAD_EIM_A25__EIM_A25 IOMUX_PAD(0x454, 0xc0, 0, 0x0000, 0, 0) | ||
| 161 | #define _MX51_PAD_EIM_A25__GPIO2_19 IOMUX_PAD(0x454, 0xc0, 1, 0x0000, 0, 0) | ||
| 162 | #define _MX51_PAD_EIM_A25__USBH2_DIR IOMUX_PAD(0x454, 0xc0, 2, 0x0000, 0, 0) | ||
| 163 | #define _MX51_PAD_EIM_A26__CSI1_DATA_EN IOMUX_PAD(0x458, 0xc4, 5, 0x09a0, 0, 0) | ||
| 164 | #define _MX51_PAD_EIM_A26__DISP2_EXT_CLK IOMUX_PAD(0x458, 0xc4, 6, 0x0908, 0, 0) | ||
| 165 | #define _MX51_PAD_EIM_A26__EIM_A26 IOMUX_PAD(0x458, 0xc4, 0, 0x0000, 0, 0) | ||
| 166 | #define _MX51_PAD_EIM_A26__GPIO2_20 IOMUX_PAD(0x458, 0xc4, 1, 0x0000, 0, 0) | ||
| 167 | #define _MX51_PAD_EIM_A26__USBH2_STP IOMUX_PAD(0x458, 0xc4, 2, 0x0000, 0, 0) | ||
| 168 | #define _MX51_PAD_EIM_A27__CSI2_DATA_EN IOMUX_PAD(0x45c, 0xc8, 5, 0x099c, 0, 0) | ||
| 169 | #define _MX51_PAD_EIM_A27__DISP1_PIN1 IOMUX_PAD(0x45c, 0xc8, 6, 0x09a4, 0, 0) | ||
| 170 | #define _MX51_PAD_EIM_A27__EIM_A27 IOMUX_PAD(0x45c, 0xc8, 0, 0x0000, 0, 0) | ||
| 171 | #define _MX51_PAD_EIM_A27__GPIO2_21 IOMUX_PAD(0x45c, 0xc8, 1, 0x0000, 0, 0) | ||
| 172 | #define _MX51_PAD_EIM_A27__USBH2_NXT IOMUX_PAD(0x45c, 0xc8, 2, 0x0000, 0, 0) | ||
| 173 | #define _MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0xcc, 0, 0x0000, 0, 0) | ||
| 174 | #define _MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0xd0, 0, 0x0000, 0, 0) | ||
| 175 | #define _MX51_PAD_EIM_EB2__AUD5_RXFS IOMUX_PAD(0x468, 0xd4, 6, 0x08e0, 0, 0) | ||
| 176 | #define _MX51_PAD_EIM_EB2__CSI1_D2 IOMUX_PAD(0x468, 0xd4, 5, 0x0000, 0, 0) | ||
| 177 | #define _MX51_PAD_EIM_EB2__EIM_EB2 IOMUX_PAD(0x468, 0xd4, 0, 0x0000, 0, 0) | ||
| 178 | #define _MX51_PAD_EIM_EB2__FEC_MDIO IOMUX_PAD(0x468, 0xd4, 3, 0x0954, 0, 0) | ||
| 179 | #define _MX51_PAD_EIM_EB2__GPIO2_22 IOMUX_PAD(0x468, 0xd4, 1, 0x0000, 0, 0) | ||
| 180 | #define _MX51_PAD_EIM_EB2__GPT_CMPOUT1 IOMUX_PAD(0x468, 0xd4, 7, 0x0000, 0, 0) | ||
| 181 | #define _MX51_PAD_EIM_EB3__AUD5_RXC IOMUX_PAD(0x46c, 0xd8, 6, 0x08dc, 0, 0) | ||
| 182 | #define _MX51_PAD_EIM_EB3__CSI1_D3 IOMUX_PAD(0x46c, 0xd8, 5, 0x0000, 0, 0) | ||
| 183 | #define _MX51_PAD_EIM_EB3__EIM_EB3 IOMUX_PAD(0x46c, 0xd8, 0, 0x0000, 0, 0) | ||
| 184 | #define _MX51_PAD_EIM_EB3__FEC_RDATA1 IOMUX_PAD(0x46c, 0xd8, 3, 0x095c, 0, 0) | ||
| 185 | #define _MX51_PAD_EIM_EB3__GPIO2_23 IOMUX_PAD(0x46c, 0xd8, 1, 0x0000, 0, 0) | ||
| 186 | #define _MX51_PAD_EIM_EB3__GPT_CMPOUT2 IOMUX_PAD(0x46c, 0xd8, 7, 0x0000, 0, 0) | ||
| 187 | #define _MX51_PAD_EIM_OE__EIM_OE IOMUX_PAD(0x470, 0xdc, 0, 0x0000, 0, 0) | ||
| 188 | #define _MX51_PAD_EIM_OE__GPIO2_24 IOMUX_PAD(0x470, 0xdc, 1, 0x0000, 0, 0) | ||
| 189 | #define _MX51_PAD_EIM_CS0__EIM_CS0 IOMUX_PAD(0x474, 0xe0, 0, 0x0000, 0, 0) | ||
| 190 | #define _MX51_PAD_EIM_CS0__GPIO2_25 IOMUX_PAD(0x474, 0xe0, 1, 0x0000, 0, 0) | ||
| 191 | #define _MX51_PAD_EIM_CS1__EIM_CS1 IOMUX_PAD(0x478, 0xe4, 0, 0x0000, 0, 0) | ||
| 192 | #define _MX51_PAD_EIM_CS1__GPIO2_26 IOMUX_PAD(0x478, 0xe4, 1, 0x0000, 0, 0) | ||
| 193 | #define _MX51_PAD_EIM_CS2__AUD5_TXD IOMUX_PAD(0x47c, 0xe8, 6, 0x08d8, 1, 0) | ||
| 194 | #define _MX51_PAD_EIM_CS2__CSI1_D4 IOMUX_PAD(0x47c, 0xe8, 5, 0x0000, 0, 0) | ||
| 195 | #define _MX51_PAD_EIM_CS2__EIM_CS2 IOMUX_PAD(0x47c, 0xe8, 0, 0x0000, 0, 0) | ||
| 196 | #define _MX51_PAD_EIM_CS2__FEC_RDATA2 IOMUX_PAD(0x47c, 0xe8, 3, 0x0960, 0, 0) | ||
| 197 | #define _MX51_PAD_EIM_CS2__GPIO2_27 IOMUX_PAD(0x47c, 0xe8, 1, 0x0000, 0, 0) | ||
| 198 | #define _MX51_PAD_EIM_CS2__USBOTG_STP IOMUX_PAD(0x47c, 0xe8, 2, 0x0000, 0, 0) | ||
| 199 | #define _MX51_PAD_EIM_CS3__AUD5_RXD IOMUX_PAD(0x480, 0xec, 6, 0x08d4, 1, 0) | ||
| 200 | #define _MX51_PAD_EIM_CS3__CSI1_D5 IOMUX_PAD(0x480, 0xec, 5, 0x0000, 0, 0) | ||
| 201 | #define _MX51_PAD_EIM_CS3__EIM_CS3 IOMUX_PAD(0x480, 0xec, 0, 0x0000, 0, 0) | ||
| 202 | #define _MX51_PAD_EIM_CS3__FEC_RDATA3 IOMUX_PAD(0x480, 0xec, 3, 0x0964, 0, 0) | ||
| 203 | #define _MX51_PAD_EIM_CS3__GPIO2_28 IOMUX_PAD(0x480, 0xec, 1, 0x0000, 0, 0) | ||
| 204 | #define _MX51_PAD_EIM_CS3__USBOTG_NXT IOMUX_PAD(0x480, 0xec, 2, 0x0000, 0, 0) | ||
| 205 | #define _MX51_PAD_EIM_CS4__AUD5_TXC IOMUX_PAD(0x484, 0xf0, 6, 0x08e4, 1, 0) | ||
| 206 | #define _MX51_PAD_EIM_CS4__CSI1_D6 IOMUX_PAD(0x484, 0xf0, 5, 0x0000, 0, 0) | ||
| 207 | #define _MX51_PAD_EIM_CS4__EIM_CS4 IOMUX_PAD(0x484, 0xf0, 0, 0x0000, 0, 0) | ||
| 208 | #define _MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0xf0, 3, 0x0970, 0, 0) | ||
| 209 | #define _MX51_PAD_EIM_CS4__GPIO2_29 IOMUX_PAD(0x484, 0xf0, 1, 0x0000, 0, 0) | ||
| 210 | #define _MX51_PAD_EIM_CS4__USBOTG_CLK IOMUX_PAD(0x484, 0xf0, 2, 0x0000, 0, 0) | ||
| 211 | #define _MX51_PAD_EIM_CS5__AUD5_TXFS IOMUX_PAD(0x488, 0xf4, 6, 0x08e8, 1, 0) | ||
| 212 | #define _MX51_PAD_EIM_CS5__CSI1_D7 IOMUX_PAD(0x488, 0xf4, 5, 0x0000, 0, 0) | ||
| 213 | #define _MX51_PAD_EIM_CS5__DISP1_EXT_CLK IOMUX_PAD(0x488, 0xf4, 4, 0x0904, 0, 0) | ||
| 214 | #define _MX51_PAD_EIM_CS5__EIM_CS5 IOMUX_PAD(0x488, 0xf4, 0, 0x0000, 0, 0) | ||
| 215 | #define _MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x488, 0xf4, 3, 0x0950, 0, 0) | ||
| 216 | #define _MX51_PAD_EIM_CS5__GPIO2_30 IOMUX_PAD(0x488, 0xf4, 1, 0x0000, 0, 0) | ||
| 217 | #define _MX51_PAD_EIM_CS5__USBOTG_DIR IOMUX_PAD(0x488, 0xf4, 2, 0x0000, 0, 0) | ||
| 218 | #define _MX51_PAD_EIM_DTACK__EIM_DTACK IOMUX_PAD(0x48c, 0xf8, 0, 0x0000, 0, 0) | ||
| 219 | #define _MX51_PAD_EIM_DTACK__GPIO2_31 IOMUX_PAD(0x48c, 0xf8, 1, 0x0000, 0, 0) | ||
| 220 | #define _MX51_PAD_EIM_LBA__EIM_LBA IOMUX_PAD(0x494, 0xfc, 0, 0x0000, 0, 0) | ||
| 221 | #define _MX51_PAD_EIM_LBA__GPIO3_1 IOMUX_PAD(0x494, 0xfc, 1, 0x0978, 0, 0) | ||
| 222 | #define _MX51_PAD_EIM_CRE__EIM_CRE IOMUX_PAD(0x4a0, 0x100, 0, 0x0000, 0, 0) | ||
| 223 | #define _MX51_PAD_EIM_CRE__GPIO3_2 IOMUX_PAD(0x4a0, 0x100, 1, 0x097c, 0, 0) | ||
| 224 | #define _MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4d0, 0x104, 0, 0x0000, 0, 0) | ||
| 225 | #define _MX51_PAD_NANDF_WE_B__GPIO3_3 IOMUX_PAD(0x4e4, 0x108, 3, 0x0980, 0, 0) | ||
| 226 | #define _MX51_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x4e4, 0x108, 0, 0x0000, 0, 0) | ||
| 227 | #define _MX51_PAD_NANDF_WE_B__PATA_DIOW IOMUX_PAD(0x4e4, 0x108, 1, 0x0000, 0, 0) | ||
| 228 | #define _MX51_PAD_NANDF_WE_B__SD3_DATA0 IOMUX_PAD(0x4e4, 0x108, 2, 0x093c, 0, 0) | ||
| 229 | #define _MX51_PAD_NANDF_RE_B__GPIO3_4 IOMUX_PAD(0x4e8, 0x10c, 3, 0x0984, 0, 0) | ||
| 230 | #define _MX51_PAD_NANDF_RE_B__NANDF_RE_B IOMUX_PAD(0x4e8, 0x10c, 0, 0x0000, 0, 0) | ||
| 231 | #define _MX51_PAD_NANDF_RE_B__PATA_DIOR IOMUX_PAD(0x4e8, 0x10c, 1, 0x0000, 0, 0) | ||
| 232 | #define _MX51_PAD_NANDF_RE_B__SD3_DATA1 IOMUX_PAD(0x4e8, 0x10c, 2, 0x0940, 0, 0) | ||
| 233 | #define _MX51_PAD_NANDF_ALE__GPIO3_5 IOMUX_PAD(0x4ec, 0x110, 3, 0x0988, 0, 0) | ||
| 234 | #define _MX51_PAD_NANDF_ALE__NANDF_ALE IOMUX_PAD(0x4ec, 0x110, 0, 0x0000, 0, 0) | ||
| 235 | #define _MX51_PAD_NANDF_ALE__PATA_BUFFER_EN IOMUX_PAD(0x4ec, 0x110, 1, 0x0000, 0, 0) | ||
| 236 | #define _MX51_PAD_NANDF_CLE__GPIO3_6 IOMUX_PAD(0x4f0, 0x114, 3, 0x098c, 0, 0) | ||
| 237 | #define _MX51_PAD_NANDF_CLE__NANDF_CLE IOMUX_PAD(0x4f0, 0x114, 0, 0x0000, 0, 0) | ||
| 238 | #define _MX51_PAD_NANDF_CLE__PATA_RESET_B IOMUX_PAD(0x4f0, 0x114, 1, 0x0000, 0, 0) | ||
| 239 | #define _MX51_PAD_NANDF_WP_B__GPIO3_7 IOMUX_PAD(0x4f4, 0x118, 3, 0x0990, 0, 0) | ||
| 240 | #define _MX51_PAD_NANDF_WP_B__NANDF_WP_B IOMUX_PAD(0x4f4, 0x118, 0, 0x0000, 0, 0) | ||
| 241 | #define _MX51_PAD_NANDF_WP_B__PATA_DMACK IOMUX_PAD(0x4f4, 0x118, 1, 0x0000, 0, 0) | ||
| 242 | #define _MX51_PAD_NANDF_WP_B__SD3_DATA2 IOMUX_PAD(0x4f4, 0x118, 2, 0x0944, 0, 0) | ||
| 243 | #define _MX51_PAD_NANDF_RB0__ECSPI2_SS1 IOMUX_PAD(0x4f8, 0x11c, 5, 0x0930, 0, 0) | ||
| 244 | #define _MX51_PAD_NANDF_RB0__GPIO3_8 IOMUX_PAD(0x4f8, 0x11c, 3, 0x0994, 0, 0) | ||
| 245 | #define _MX51_PAD_NANDF_RB0__NANDF_RB0 IOMUX_PAD(0x4f8, 0x11c, 0, 0x0000, 0, 0) | ||
| 246 | #define _MX51_PAD_NANDF_RB0__PATA_DMARQ IOMUX_PAD(0x4f8, 0x11c, 1, 0x0000, 0, 0) | ||
| 247 | #define _MX51_PAD_NANDF_RB0__SD3_DATA3 IOMUX_PAD(0x4f8, 0x11c, 2, 0x0948, 0, 0) | ||
| 248 | #define _MX51_PAD_NANDF_RB1__CSPI_MOSI IOMUX_PAD(0x4fc, 0x120, 6, 0x091c, 0, 0) | ||
| 249 | #define _MX51_PAD_NANDF_RB1__ECSPI2_RDY IOMUX_PAD(0x4fc, 0x120, 2, 0x0000, 0, 0) | ||
| 250 | #define _MX51_PAD_NANDF_RB1__GPIO3_9 IOMUX_PAD(0x4fc, 0x120, 3, 0x0000, 0, 0) | ||
| 251 | #define _MX51_PAD_NANDF_RB1__NANDF_RB1 IOMUX_PAD(0x4fc, 0x120, 0, 0x0000, 0, 0) | ||
| 252 | #define _MX51_PAD_NANDF_RB1__PATA_IORDY IOMUX_PAD(0x4fc, 0x120, 1, 0x0000, 0, 0) | ||
| 253 | #define _MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 5, 0x0000, 0, 0) | ||
| 254 | #define _MX51_PAD_NANDF_RB2__DISP2_WAIT IOMUX_PAD(0x500, 0x124, 5, 0x09a8, 0, 0) | ||
| 255 | #define _MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, 0x0000, 0, 0) | ||
| 256 | #define _MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x094c, 0, 0) | ||
| 257 | #define _MX51_PAD_NANDF_RB2__GPIO3_10 IOMUX_PAD(0x500, 0x124, 3, 0x0000, 0, 0) | ||
| 258 | #define _MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, 0x0000, 0, 0) | ||
| 259 | #define _MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 7, 0x0000, 0, 0) | ||
| 260 | #define _MX51_PAD_NANDF_RB2__USBH3_NXT IOMUX_PAD(0x500, 0x124, 6, 0x0a20, 0, 0) | ||
| 261 | #define _MX51_PAD_NANDF_RB3__DISP1_WAIT IOMUX_PAD(0x504, 0x128, 5, 0x0000, 0, 0) | ||
| 262 | #define _MX51_PAD_NANDF_RB3__ECSPI2_MISO IOMUX_PAD(0x504, 0x128, 2, 0x0000, 0, 0) | ||
| 263 | #define _MX51_PAD_NANDF_RB3__FEC_RX_CLK IOMUX_PAD(0x504, 0x128, 1, 0x0968, 0, 0) | ||
| 264 | #define _MX51_PAD_NANDF_RB3__GPIO3_11 IOMUX_PAD(0x504, 0x128, 3, 0x0000, 0, 0) | ||
| 265 | #define _MX51_PAD_NANDF_RB3__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 0, 0x0000, 0, 0) | ||
| 266 | #define _MX51_PAD_NANDF_RB3__USBH3_CLK IOMUX_PAD(0x504, 0x128, 6, 0x09f8, 0, 0) | ||
| 267 | #define _MX51_PAD_NANDF_RB3__USBH3_H3_DM IOMUX_PAD(0x504, 0x128, 7, 0x0000, 0, 0) | ||
| 268 | #define _MX51_PAD_GPIO_NAND__GPIO_NAND IOMUX_PAD(0x514, 0x12c, 0, 0x0998, 0, 0) | ||
| 269 | #define _MX51_PAD_GPIO_NAND__PATA_INTRQ IOMUX_PAD(0x514, 0x12c, 1, 0x0000, 0, 0) | ||
| 270 | #define _MX51_PAD_NANDF_CS0__GPIO3_16 IOMUX_PAD(0x518, 0x130, 3, 0x0000, 0, 0) | ||
| 271 | #define _MX51_PAD_NANDF_CS0__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 0, 0x0000, 0, 0) | ||
| 272 | #define _MX51_PAD_NANDF_CS1__GPIO3_17 IOMUX_PAD(0x51c, 0x134, 3, 0x0000, 0, 0) | ||
| 273 | #define _MX51_PAD_NANDF_CS1__NANDF_CS1 IOMUX_PAD(0x51c, 0x134, 0, 0x0000, 0, 0) | ||
| 274 | #define _MX51_PAD_NANDF_CS2__CSPI_SCLK IOMUX_PAD(0x520, 0x138, 6, 0x0914, 0, 0) | ||
| 275 | #define _MX51_PAD_NANDF_CS2__FEC_TX_ER IOMUX_PAD(0x520, 0x138, 2, 0x0000, 0, 0) | ||
| 276 | #define _MX51_PAD_NANDF_CS2__GPIO3_18 IOMUX_PAD(0x520, 0x138, 3, 0x0000, 0, 0) | ||
| 277 | #define _MX51_PAD_NANDF_CS2__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 0, 0x0000, 0, 0) | ||
| 278 | #define _MX51_PAD_NANDF_CS2__PATA_CS_0 IOMUX_PAD(0x520, 0x138, 1, 0x0000, 0, 0) | ||
| 279 | #define _MX51_PAD_NANDF_CS2__SD4_CLK IOMUX_PAD(0x520, 0x138, 5, 0x0000, 0, 0) | ||
| 280 | #define _MX51_PAD_NANDF_CS2__USBH3_H1_DP IOMUX_PAD(0x520, 0x138, 7, 0x0000, 0, 0) | ||
| 281 | #define _MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13c, 2, 0x0000, 0, 0) | ||
| 282 | #define _MX51_PAD_NANDF_CS3__GPIO3_19 IOMUX_PAD(0x524, 0x13c, 3, 0x0000, 0, 0) | ||
| 283 | #define _MX51_PAD_NANDF_CS3__NANDF_CS3 IOMUX_PAD(0x524, 0x13c, 0, 0x0000, 0, 0) | ||
| 284 | #define _MX51_PAD_NANDF_CS3__PATA_CS_1 IOMUX_PAD(0x524, 0x13c, 1, 0x0000, 0, 0) | ||
| 285 | #define _MX51_PAD_NANDF_CS3__SD4_DAT0 IOMUX_PAD(0x524, 0x13c, 5, 0x0000, 0, 0) | ||
| 286 | #define _MX51_PAD_NANDF_CS3__USBH3_H1_DM IOMUX_PAD(0x524, 0x13c, 7, 0x0000, 0, 0) | ||
| 287 | #define _MX51_PAD_NANDF_CS4__FEC_TDATA1 IOMUX_PAD(0x528, 0x140, 2, 0x0000, 0, 0) | ||
| 288 | #define _MX51_PAD_NANDF_CS4__GPIO3_20 IOMUX_PAD(0x528, 0x140, 3, 0x0000, 0, 0) | ||
| 289 | #define _MX51_PAD_NANDF_CS4__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 0, 0x0000, 0, 0) | ||
| 290 | #define _MX51_PAD_NANDF_CS4__PATA_DA_0 IOMUX_PAD(0x528, 0x140, 1, 0x0000, 0, 0) | ||
| 291 | #define _MX51_PAD_NANDF_CS4__SD4_DAT1 IOMUX_PAD(0x528, 0x140, 5, 0x0000, 0, 0) | ||
| 292 | #define _MX51_PAD_NANDF_CS4__USBH3_STP IOMUX_PAD(0x528, 0x140, 7, 0x0a24, 0, 0) | ||
| 293 | #define _MX51_PAD_NANDF_CS5__FEC_TDATA2 IOMUX_PAD(0x52c, 0x144, 2, 0x0000, 0, 0) | ||
| 294 | #define _MX51_PAD_NANDF_CS5__GPIO3_21 IOMUX_PAD(0x52c, 0x144, 3, 0x0000, 0, 0) | ||
| 295 | #define _MX51_PAD_NANDF_CS5__NANDF_CS5 IOMUX_PAD(0x52c, 0x144, 0, 0x0000, 0, 0) | ||
| 296 | #define _MX51_PAD_NANDF_CS5__PATA_DA_1 IOMUX_PAD(0x52c, 0x144, 1, 0x0000, 0, 0) | ||
| 297 | #define _MX51_PAD_NANDF_CS5__SD4_DAT2 IOMUX_PAD(0x52c, 0x144, 5, 0x0000, 0, 0) | ||
| 298 | #define _MX51_PAD_NANDF_CS5__USBH3_DIR IOMUX_PAD(0x52c, 0x144, 7, 0x0a1c, 0, 0) | ||
| 299 | #define _MX51_PAD_NANDF_CS6__CSPI_SS3 IOMUX_PAD(0x530, 0x148, 7, 0x0928, 0, 0) | ||
| 300 | #define _MX51_PAD_NANDF_CS6__FEC_TDATA3 IOMUX_PAD(0x530, 0x148, 2, 0x0000, 0, 0) | ||
| 301 | #define _MX51_PAD_NANDF_CS6__GPIO3_22 IOMUX_PAD(0x530, 0x148, 3, 0x0000, 0, 0) | ||
| 302 | #define _MX51_PAD_NANDF_CS6__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 0, 0x0000, 0, 0) | ||
| 303 | #define _MX51_PAD_NANDF_CS6__PATA_DA_2 IOMUX_PAD(0x530, 0x148, 1, 0x0000, 0, 0) | ||
| 304 | #define _MX51_PAD_NANDF_CS6__SD4_DAT3 IOMUX_PAD(0x530, 0x148, 5, 0x0000, 0, 0) | ||
| 305 | #define _MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14c, 1, 0x0000, 0, 0) | ||
| 306 | #define _MX51_PAD_NANDF_CS7__GPIO3_23 IOMUX_PAD(0x534, 0x14c, 3, 0x0000, 0, 0) | ||
| 307 | #define _MX51_PAD_NANDF_CS7__NANDF_CS7 IOMUX_PAD(0x534, 0x14c, 0, 0x0000, 0, 0) | ||
| 308 | #define _MX51_PAD_NANDF_CS7__SD3_CLK IOMUX_PAD(0x534, 0x14c, 5, 0x0000, 0, 0) | ||
| 309 | #define _MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 IOMUX_PAD(0x538, 0x150, 2, 0x0000, 0, 0) | ||
| 310 | #define _MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x0974, 0, 0) | ||
| 311 | #define _MX51_PAD_NANDF_RDY_INT__GPIO3_24 IOMUX_PAD(0x538, 0x150, 3, 0x0000, 0, 0) | ||
| 312 | #define _MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 0, 0x0938, 0, 0) | ||
| 313 | #define _MX51_PAD_NANDF_RDY_INT__SD3_CMD IOMUX_PAD(0x538, 0x150, 5, 0x0000, 0, 0) | ||
| 314 | #define _MX51_PAD_NANDF_D15__ECSPI2_MOSI IOMUX_PAD(0x53c, 0x154, 2, 0x0000, 0, 0) | ||
| 315 | #define _MX51_PAD_NANDF_D15__GPIO3_25 IOMUX_PAD(0x53c, 0x154, 3, 0x0000, 0, 0) | ||
| 316 | #define _MX51_PAD_NANDF_D15__NANDF_D15 IOMUX_PAD(0x53c, 0x154, 0, 0x0000, 0, 0) | ||
| 317 | #define _MX51_PAD_NANDF_D15__PATA_DATA15 IOMUX_PAD(0x53c, 0x154, 1, 0x0000, 0, 0) | ||
| 318 | #define _MX51_PAD_NANDF_D15__SD3_DAT7 IOMUX_PAD(0x53c, 0x154, 5, 0x0000, 0, 0) | ||
| 319 | #define _MX51_PAD_NANDF_D14__ECSPI2_SS3 IOMUX_PAD(0x540, 0x158, 2, 0x0934, 0, 0) | ||
| 320 | #define _MX51_PAD_NANDF_D14__GPIO3_26 IOMUX_PAD(0x540, 0x158, 3, 0x0000, 0, 0) | ||
| 321 | #define _MX51_PAD_NANDF_D14__NANDF_D14 IOMUX_PAD(0x540, 0x158, 0, 0x0000, 0, 0) | ||
| 322 | #define _MX51_PAD_NANDF_D14__PATA_DATA14 IOMUX_PAD(0x540, 0x158, 1, 0x0000, 0, 0) | ||
| 323 | #define _MX51_PAD_NANDF_D14__SD3_DAT6 IOMUX_PAD(0x540, 0x158, 5, 0x0000, 0, 0) | ||
| 324 | #define _MX51_PAD_NANDF_D13__ECSPI2_SS2 IOMUX_PAD(0x544, 0x15c, 2, 0x0000, 0, 0) | ||
| 325 | #define _MX51_PAD_NANDF_D13__GPIO3_27 IOMUX_PAD(0x544, 0x15c, 3, 0x0000, 0, 0) | ||
| 326 | #define _MX51_PAD_NANDF_D13__NANDF_D13 IOMUX_PAD(0x544, 0x15c, 0, 0x0000, 0, 0) | ||
| 327 | #define _MX51_PAD_NANDF_D13__PATA_DATA13 IOMUX_PAD(0x544, 0x15c, 1, 0x0000, 0, 0) | ||
| 328 | #define _MX51_PAD_NANDF_D13__SD3_DAT5 IOMUX_PAD(0x544, 0x15c, 5, 0x0000, 0, 0) | ||
| 329 | #define _MX51_PAD_NANDF_D12__ECSPI2_SS1 IOMUX_PAD(0x548, 0x160, 2, 0x0930, 1, 0) | ||
| 330 | #define _MX51_PAD_NANDF_D12__GPIO3_28 IOMUX_PAD(0x548, 0x160, 3, 0x0000, 0, 0) | ||
| 331 | #define _MX51_PAD_NANDF_D12__NANDF_D12 IOMUX_PAD(0x548, 0x160, 0, 0x0000, 0, 0) | ||
| 332 | #define _MX51_PAD_NANDF_D12__PATA_DATA12 IOMUX_PAD(0x548, 0x160, 1, 0x0000, 0, 0) | ||
| 333 | #define _MX51_PAD_NANDF_D12__SD3_DAT4 IOMUX_PAD(0x548, 0x160, 5, 0x0000, 0, 0) | ||
| 334 | #define _MX51_PAD_NANDF_D11__FEC_RX_DV IOMUX_PAD(0x54c, 0x164, 2, 0x096c, 0, 0) | ||
| 335 | #define _MX51_PAD_NANDF_D11__GPIO3_29 IOMUX_PAD(0x54c, 0x164, 3, 0x0000, 0, 0) | ||
| 336 | #define _MX51_PAD_NANDF_D11__NANDF_D11 IOMUX_PAD(0x54c, 0x164, 0, 0x0000, 0, 0) | ||
| 337 | #define _MX51_PAD_NANDF_D11__PATA_DATA11 IOMUX_PAD(0x54c, 0x164, 1, 0x0000, 0, 0) | ||
| 338 | #define _MX51_PAD_NANDF_D11__SD3_DATA3 IOMUX_PAD(0x54c, 0x164, 5, 0x0948, 1, 0) | ||
| 339 | #define _MX51_PAD_NANDF_D10__GPIO3_30 IOMUX_PAD(0x550, 0x168, 3, 0x0000, 0, 0) | ||
| 340 | #define _MX51_PAD_NANDF_D10__NANDF_D10 IOMUX_PAD(0x550, 0x168, 0, 0x0000, 0, 0) | ||
| 341 | #define _MX51_PAD_NANDF_D10__PATA_DATA10 IOMUX_PAD(0x550, 0x168, 1, 0x0000, 0, 0) | ||
| 342 | #define _MX51_PAD_NANDF_D10__SD3_DATA2 IOMUX_PAD(0x550, 0x168, 5, 0x0944, 1, 0) | ||
| 343 | #define _MX51_PAD_NANDF_D9__FEC_RDATA0 IOMUX_PAD(0x554, 0x16c, 0x12, 0x0958, 0, 0) | ||
| 344 | #define _MX51_PAD_NANDF_D9__GPIO3_31 IOMUX_PAD(0x554, 0x16c, 3, 0x0000, 0, 0) | ||
| 345 | #define _MX51_PAD_NANDF_D9__NANDF_D9 IOMUX_PAD(0x554, 0x16c, 0, 0x0000, 0, 0) | ||
| 346 | #define _MX51_PAD_NANDF_D9__PATA_DATA9 IOMUX_PAD(0x554, 0x16c, 1, 0x0000, 0, 0) | ||
| 347 | #define _MX51_PAD_NANDF_D9__SD3_DATA1 IOMUX_PAD(0x554, 0x16c, 5, 0x0940, 1, 0) | ||
| 348 | #define _MX51_PAD_NANDF_D8__FEC_TDATA0 IOMUX_PAD(0x558, 0x170, 2, 0x0000, 0, 0) | ||
| 349 | #define _MX51_PAD_NANDF_D8__GPIO4_0 IOMUX_PAD(0x558, 0x170, 3, 0x0000, 0, 0) | ||
| 350 | #define _MX51_PAD_NANDF_D8__NANDF_D8 IOMUX_PAD(0x558, 0x170, 0, 0x0000, 0, 0) | ||
| 351 | #define _MX51_PAD_NANDF_D8__PATA_DATA8 IOMUX_PAD(0x558, 0x170, 1, 0x0000, 0, 0) | ||
| 352 | #define _MX51_PAD_NANDF_D8__SD3_DATA0 IOMUX_PAD(0x558, 0x170, 5, 0x093c, 1, 0) | ||
| 353 | #define _MX51_PAD_NANDF_D7__GPIO4_1 IOMUX_PAD(0x55c, 0x174, 3, 0x0000, 0, 0) | ||
| 354 | #define _MX51_PAD_NANDF_D7__NANDF_D7 IOMUX_PAD(0x55c, 0x174, 0, 0x0000, 0, 0) | ||
| 355 | #define _MX51_PAD_NANDF_D7__PATA_DATA7 IOMUX_PAD(0x55c, 0x174, 1, 0x0000, 0, 0) | ||
| 356 | #define _MX51_PAD_NANDF_D7__USBH3_DATA0 IOMUX_PAD(0x55c, 0x174, 5, 0x09fc, 0, 0) | ||
| 357 | #define _MX51_PAD_NANDF_D6__GPIO4_2 IOMUX_PAD(0x560, 0x178, 3, 0x0000, 0, 0) | ||
| 358 | #define _MX51_PAD_NANDF_D6__NANDF_D6 IOMUX_PAD(0x560, 0x178, 0, 0x0000, 0, 0) | ||
| 359 | #define _MX51_PAD_NANDF_D6__PATA_DATA6 IOMUX_PAD(0x560, 0x178, 1, 0x0000, 0, 0) | ||
| 360 | #define _MX51_PAD_NANDF_D6__SD4_LCTL IOMUX_PAD(0x560, 0x178, 2, 0x0000, 0, 0) | ||
| 361 | #define _MX51_PAD_NANDF_D6__USBH3_DATA1 IOMUX_PAD(0x560, 0x178, 5, 0x0a00, 0, 0) | ||
| 362 | #define _MX51_PAD_NANDF_D5__GPIO4_3 IOMUX_PAD(0x564, 0x17c, 3, 0x0000, 0, 0) | ||
| 363 | #define _MX51_PAD_NANDF_D5__NANDF_D5 IOMUX_PAD(0x564, 0x17c, 0, 0x0000, 0, 0) | ||
| 364 | #define _MX51_PAD_NANDF_D5__PATA_DATA5 IOMUX_PAD(0x564, 0x17c, 1, 0x0000, 0, 0) | ||
| 365 | #define _MX51_PAD_NANDF_D5__SD4_WP IOMUX_PAD(0x564, 0x17c, 2, 0x0000, 0, 0) | ||
| 366 | #define _MX51_PAD_NANDF_D5__USBH3_DATA2 IOMUX_PAD(0x564, 0x17c, 5, 0x0a04, 0, 0) | ||
| 367 | #define _MX51_PAD_NANDF_D4__GPIO4_4 IOMUX_PAD(0x568, 0x180, 3, 0x0000, 0, 0) | ||
| 368 | #define _MX51_PAD_NANDF_D4__NANDF_D4 IOMUX_PAD(0x568, 0x180, 0, 0x0000, 0, 0) | ||
| 369 | #define _MX51_PAD_NANDF_D4__PATA_DATA4 IOMUX_PAD(0x568, 0x180, 1, 0x0000, 0, 0) | ||
| 370 | #define _MX51_PAD_NANDF_D4__SD4_CD IOMUX_PAD(0x568, 0x180, 2, 0x0000, 0, 0) | ||
| 371 | #define _MX51_PAD_NANDF_D4__USBH3_DATA3 IOMUX_PAD(0x568, 0x180, 5, 0x0a08, 0, 0) | ||
| 372 | #define _MX51_PAD_NANDF_D3__GPIO4_5 IOMUX_PAD(0x56c, 0x184, 3, 0x0000, 0, 0) | ||
| 373 | #define _MX51_PAD_NANDF_D3__NANDF_D3 IOMUX_PAD(0x56c, 0x184, 0, 0x0000, 0, 0) | ||
| 374 | #define _MX51_PAD_NANDF_D3__PATA_DATA3 IOMUX_PAD(0x56c, 0x184, 1, 0x0000, 0, 0) | ||
| 375 | #define _MX51_PAD_NANDF_D3__SD4_DAT4 IOMUX_PAD(0x56c, 0x184, 2, 0x0000, 0, 0) | ||
| 376 | #define _MX51_PAD_NANDF_D3__USBH3_DATA4 IOMUX_PAD(0x56c, 0x184, 5, 0x0a0c, 0, 0) | ||
| 377 | #define _MX51_PAD_NANDF_D2__GPIO4_6 IOMUX_PAD(0x570, 0x188, 3, 0x0000, 0, 0) | ||
| 378 | #define _MX51_PAD_NANDF_D2__NANDF_D2 IOMUX_PAD(0x570, 0x188, 0, 0x0000, 0, 0) | ||
| 379 | #define _MX51_PAD_NANDF_D2__PATA_DATA2 IOMUX_PAD(0x570, 0x188, 1, 0x0000, 0, 0) | ||
| 380 | #define _MX51_PAD_NANDF_D2__SD4_DAT5 IOMUX_PAD(0x570, 0x188, 2, 0x0000, 0, 0) | ||
| 381 | #define _MX51_PAD_NANDF_D2__USBH3_DATA5 IOMUX_PAD(0x570, 0x188, 5, 0x0a10, 0, 0) | ||
| 382 | #define _MX51_PAD_NANDF_D1__GPIO4_7 IOMUX_PAD(0x574, 0x18c, 3, 0x0000, 0, 0) | ||
| 383 | #define _MX51_PAD_NANDF_D1__NANDF_D1 IOMUX_PAD(0x574, 0x18c, 0, 0x0000, 0, 0) | ||
| 384 | #define _MX51_PAD_NANDF_D1__PATA_DATA1 IOMUX_PAD(0x574, 0x18c, 1, 0x0000, 0, 0) | ||
| 385 | #define _MX51_PAD_NANDF_D1__SD4_DAT6 IOMUX_PAD(0x574, 0x18c, 2, 0x0000, 0, 0) | ||
| 386 | #define _MX51_PAD_NANDF_D1__USBH3_DATA6 IOMUX_PAD(0x574, 0x18c, 5, 0x0a14, 0, 0) | ||
| 387 | #define _MX51_PAD_NANDF_D0__GPIO4_8 IOMUX_PAD(0x578, 0x190, 3, 0x0000, 0, 0) | ||
| 388 | #define _MX51_PAD_NANDF_D0__NANDF_D0 IOMUX_PAD(0x578, 0x190, 0, 0x0000, 0, 0) | ||
| 389 | #define _MX51_PAD_NANDF_D0__PATA_DATA0 IOMUX_PAD(0x578, 0x190, 1, 0x0000, 0, 0) | ||
| 390 | #define _MX51_PAD_NANDF_D0__SD4_DAT7 IOMUX_PAD(0x578, 0x190, 2, 0x0000, 0, 0) | ||
| 391 | #define _MX51_PAD_NANDF_D0__USBH3_DATA7 IOMUX_PAD(0x578, 0x190, 5, 0x0a18, 0, 0) | ||
| 392 | #define _MX51_PAD_CSI1_D8__CSI1_D8 IOMUX_PAD(0x57c, 0x194, 0, 0x0000, 0, 0) | ||
| 393 | #define _MX51_PAD_CSI1_D8__GPIO3_12 IOMUX_PAD(0x57c, 0x194, 3, 0x0998, 1, 0) | ||
| 394 | #define _MX51_PAD_CSI1_D9__CSI1_D9 IOMUX_PAD(0x580, 0x198, 0, 0x0000, 0, 0) | ||
| 395 | #define _MX51_PAD_CSI1_D9__GPIO3_13 IOMUX_PAD(0x580, 0x198, 3, 0x0000, 0, 0) | ||
| 396 | #define _MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19c, 0, 0x0000, 0, 0) | ||
| 397 | #define _MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1a0, 0, 0x0000, 0, 0) | ||
| 398 | #define _MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58c, 0x1a4, 0, 0x0000, 0, 0) | ||
| 399 | #define _MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1a8, 0, 0x0000, 0, 0) | ||
| 400 | #define _MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1ac, 0, 0x0000, 0, 0) | ||
| 401 | #define _MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1b0, 0, 0x0000, 0, 0) | ||
| 402 | #define _MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59c, 0x1b4, 0, 0x0000, 0, 0) | ||
| 403 | #define _MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5a0, 0x1b8, 0, 0x0000, 0, 0) | ||
| 404 | #define _MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5a4, 0x1bc, 0, 0x0000, 0, 0) | ||
| 405 | #define _MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5a8, 0x1c0, 0, 0x0000, 0, 0) | ||
| 406 | #define _MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5ac, 0x1c4, 0, 0x0000, 0, 0) | ||
| 407 | #define _MX51_PAD_CSI1_VSYNC__GPIO3_14 IOMUX_PAD(0x5ac, 0x1c4, 3, 0x0000, 0, 0) | ||
| 408 | #define _MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5b0, 0x1c8, 0, 0x0000, 0, 0) | ||
| 409 | #define _MX51_PAD_CSI1_HSYNC__GPIO3_15 IOMUX_PAD(0x5b0, 0x1c8, 3, 0x0000, 0, 0) | ||
| 410 | #define _MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5b4, 0x000, 0, 0x0000, 0, 0) | ||
| 411 | #define _MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5b8, 0x000, 0, 0x0000, 0, 0) | ||
| 412 | #define _MX51_PAD_CSI2_D12__CSI2_D12 IOMUX_PAD(0x5bc, 0x1cc, 0, 0x0000, 0, 0) | ||
| 413 | #define _MX51_PAD_CSI2_D12__GPIO4_9 IOMUX_PAD(0x5bc, 0x1cc, 3, 0x0000, 0, 0) | ||
| 414 | #define _MX51_PAD_CSI2_D13__CSI2_D13 IOMUX_PAD(0x5c0, 0x1d0, 0, 0x0000, 0, 0) | ||
| 415 | #define _MX51_PAD_CSI2_D13__GPIO4_10 IOMUX_PAD(0x5c0, 0x1d0, 3, 0x0000, 0, 0) | ||
| 416 | #define _MX51_PAD_CSI2_D14__CSI2_D14 IOMUX_PAD(0x5c4, 0x1d4, 0, 0x0000, 0, 0) | ||
| 417 | #define _MX51_PAD_CSI2_D15__CSI2_D15 IOMUX_PAD(0x5c8, 0x1d8, 0, 0x0000, 0, 0) | ||
| 418 | #define _MX51_PAD_CSI2_D16__CSI2_D16 IOMUX_PAD(0x5cc, 0x1dc, 0, 0x0000, 0, 0) | ||
| 419 | #define _MX51_PAD_CSI2_D17__CSI2_D17 IOMUX_PAD(0x5d0, 0x1e0, 0, 0x0000, 0, 0) | ||
| 420 | #define _MX51_PAD_CSI2_D18__CSI2_D18 IOMUX_PAD(0x5d4, 0x1e4, 0, 0x0000, 0, 0) | ||
| 421 | #define _MX51_PAD_CSI2_D18__GPIO4_11 IOMUX_PAD(0x5d4, 0x1e4, 3, 0x0000, 0, 0) | ||
| 422 | #define _MX51_PAD_CSI2_D19__CSI2_D19 IOMUX_PAD(0x5d8, 0x1e8, 0, 0x0000, 0, 0) | ||
| 423 | #define _MX51_PAD_CSI2_D19__GPIO4_12 IOMUX_PAD(0x5d8, 0x1e8, 3, 0x0000, 0, 0) | ||
| 424 | #define _MX51_PAD_CSI2_VSYNC__CSI2_VSYNC IOMUX_PAD(0x5dc, 0x1ec, 0, 0x0000, 0, 0) | ||
| 425 | #define _MX51_PAD_CSI2_VSYNC__GPIO4_13 IOMUX_PAD(0x5dc, 0x1ec, 3, 0x0000, 0, 0) | ||
| 426 | #define _MX51_PAD_CSI2_HSYNC__CSI2_HSYNC IOMUX_PAD(0x5e0, 0x1f0, 0, 0x0000, 0, 0) | ||
| 427 | #define _MX51_PAD_CSI2_HSYNC__GPIO4_14 IOMUX_PAD(0x5e0, 0x1f0, 3, 0x0000, 0, 0) | ||
| 428 | #define _MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK IOMUX_PAD(0x5e4, 0x1f4, 0, 0x0000, 0, 0) | ||
| 429 | #define _MX51_PAD_CSI2_PIXCLK__GPIO4_15 IOMUX_PAD(0x5e4, 0x1f4, 3, 0x0000, 0, 0) | ||
| 430 | #define _MX51_PAD_I2C1_CLK__GPIO4_16 IOMUX_PAD(0x5e8, 0x1f8, 3, 0x0000, 0, 0) | ||
| 431 | #define _MX51_PAD_I2C1_CLK__I2C1_CLK IOMUX_PAD(0x5e8, 0x1f8, 0x10, 0x0000, 0, 0) | ||
| 432 | #define _MX51_PAD_I2C1_DAT__GPIO4_17 IOMUX_PAD(0x5ec, 0x1fc, 3, 0x0000, 0, 0) | ||
| 433 | #define _MX51_PAD_I2C1_DAT__I2C1_DAT IOMUX_PAD(0x5ec, 0x1fc, 0x10, 0x0000, 0, 0) | ||
| 434 | #define _MX51_PAD_AUD3_BB_TXD__AUD3_TXD IOMUX_PAD(0x5f0, 0x200, 0, 0x0000, 0, 0) | ||
| 435 | #define _MX51_PAD_AUD3_BB_TXD__GPIO4_18 IOMUX_PAD(0x5f0, 0x200, 3, 0x0000, 0, 0) | ||
| 436 | #define _MX51_PAD_AUD3_BB_RXD__AUD3_RXD IOMUX_PAD(0x5f4, 0x204, 0, 0x0000, 0, 0) | ||
| 437 | #define _MX51_PAD_AUD3_BB_RXD__GPIO4_19 IOMUX_PAD(0x5f4, 0x204, 3, 0x0000, 0, 0) | ||
| 438 | #define _MX51_PAD_AUD3_BB_RXD__UART3_RXD IOMUX_PAD(0x5f4, 0x204, 1, 0x09f4, 2, 0) | ||
| 439 | #define _MX51_PAD_AUD3_BB_CK__AUD3_TXC IOMUX_PAD(0x5f8, 0x208, 0, 0x0000, 0, 0) | ||
| 440 | #define _MX51_PAD_AUD3_BB_CK__GPIO4_20 IOMUX_PAD(0x5f8, 0x208, 3, 0x0000, 0, 0) | ||
| 441 | #define _MX51_PAD_AUD3_BB_FS__AUD3_TXFS IOMUX_PAD(0x5fc, 0x20c, 0, 0x0000, 0, 0) | ||
| 442 | #define _MX51_PAD_AUD3_BB_FS__GPIO4_21 IOMUX_PAD(0x5fc, 0x20c, 3, 0x0000, 0, 0) | ||
| 443 | #define _MX51_PAD_AUD3_BB_FS__UART3_TXD IOMUX_PAD(0x5fc, 0x20c, 1, 0x0000, 0, 0) | ||
| 444 | #define _MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x600, 0x210, 0, 0x0000, 0, 0) | ||
| 445 | #define _MX51_PAD_CSPI1_MOSI__GPIO4_22 IOMUX_PAD(0x600, 0x210, 3, 0x0000, 0, 0) | ||
| 446 | #define _MX51_PAD_CSPI1_MOSI__I2C1_SDA IOMUX_PAD(0x600, 0x210, 0x11, 0x09b4, 1, 0) | ||
| 447 | #define _MX51_PAD_CSPI1_MISO__AUD4_RXD IOMUX_PAD(0x604, 0x214, 1, 0x08c4, 1, 0) | ||
| 448 | #define _MX51_PAD_CSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x604, 0x214, 0, 0x0000, 0, 0) | ||
| 449 | #define _MX51_PAD_CSPI1_MISO__GPIO4_23 IOMUX_PAD(0x604, 0x214, 3, 0x0000, 0, 0) | ||
| 450 | #define _MX51_PAD_CSPI1_SS0__AUD4_TXC IOMUX_PAD(0x608, 0x218, 1, 0x08cc, 1, 0) | ||
| 451 | #define _MX51_PAD_CSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, 0x0000, 0, 0) | ||
| 452 | #define _MX51_PAD_CSPI1_SS0__GPIO4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0000, 0, 0) | ||
| 453 | #define _MX51_PAD_CSPI1_SS1__AUD4_TXD IOMUX_PAD(0x60c, 0x21c, 1, 0x08c8, 1, 0) | ||
| 454 | #define _MX51_PAD_CSPI1_SS1__ECSPI1_SS1 IOMUX_PAD(0x60c, 0x21c, 0, 0x0000, 0, 0) | ||
| 455 | #define _MX51_PAD_CSPI1_SS1__GPIO4_25 IOMUX_PAD(0x60c, 0x21c, 3, 0x0000, 0, 0) | ||
| 456 | #define _MX51_PAD_CSPI1_RDY__AUD4_TXFS IOMUX_PAD(0x610, 0x220, 1, 0x08d0, 1, 0) | ||
| 457 | #define _MX51_PAD_CSPI1_RDY__ECSPI1_RDY IOMUX_PAD(0x610, 0x220, 0, 0x0000, 0, 0) | ||
| 458 | #define _MX51_PAD_CSPI1_RDY__GPIO4_26 IOMUX_PAD(0x610, 0x220, 3, 0x0000, 0, 0) | ||
| 459 | #define _MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x614, 0x224, 0, 0x0000, 0, 0) | ||
| 460 | #define _MX51_PAD_CSPI1_SCLK__GPIO4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0000, 0, 0) | ||
| 461 | #define _MX51_PAD_CSPI1_SCLK__I2C1_SCL IOMUX_PAD(0x614, 0x224, 0x11, 0x09b0, 1, 0) | ||
| 462 | #define _MX51_PAD_UART1_RXD__GPIO4_28 IOMUX_PAD(0x618, 0x228, 3, 0x0000, 0, 0) | ||
| 463 | #define _MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x09e4, 0, 0) | ||
| 464 | #define _MX51_PAD_UART1_TXD__GPIO4_29 IOMUX_PAD(0x61c, 0x22c, 3, 0x0000, 0, 0) | ||
| 465 | #define _MX51_PAD_UART1_TXD__PWM2_PWMO IOMUX_PAD(0x61c, 0x22c, 1, 0x0000, 0, 0) | ||
| 466 | #define _MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61c, 0x22c, 0, 0x0000, 0, 0) | ||
| 467 | #define _MX51_PAD_UART1_RTS__GPIO4_30 IOMUX_PAD(0x620, 0x230, 3, 0x0000, 0, 0) | ||
| 468 | #define _MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, 0, 0x09e0, 0, 0) | ||
| 469 | #define _MX51_PAD_UART1_CTS__GPIO4_31 IOMUX_PAD(0x624, 0x234, 3, 0x0000, 0, 0) | ||
| 470 | #define _MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, 0, 0x0000, 0, 0) | ||
| 471 | #define _MX51_PAD_UART2_RXD__FIRI_TXD IOMUX_PAD(0x628, 0x238, 1, 0x0000, 0, 0) | ||
| 472 | #define _MX51_PAD_UART2_RXD__GPIO1_20 IOMUX_PAD(0x628, 0x238, 3, 0x0000, 0, 0) | ||
| 473 | #define _MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x09ec, 2, 0) | ||
| 474 | #define _MX51_PAD_UART2_TXD__FIRI_RXD IOMUX_PAD(0x62c, 0x23c, 1, 0x0000, 0, 0) | ||
| 475 | #define _MX51_PAD_UART2_TXD__GPIO1_21 IOMUX_PAD(0x62c, 0x23c, 3, 0x0000, 0, 0) | ||
| 476 | #define _MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62c, 0x23c, 0, 0x0000, 0, 0) | ||
| 477 | #define _MX51_PAD_UART3_RXD__CSI1_D0 IOMUX_PAD(0x630, 0x240, 2, 0x0000, 0, 0) | ||
| 478 | #define _MX51_PAD_UART3_RXD__GPIO1_22 IOMUX_PAD(0x630, 0x240, 3, 0x0000, 0, 0) | ||
| 479 | #define _MX51_PAD_UART3_RXD__UART1_DTR IOMUX_PAD(0x630, 0x240, 0, 0x0000, 0, 0) | ||
| 480 | #define _MX51_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x630, 0x240, 1, 0x09f4, 4, 0) | ||
| 481 | #define _MX51_PAD_UART3_TXD__CSI1_D1 IOMUX_PAD(0x634, 0x244, 2, 0x0000, 0, 0) | ||
| 482 | #define _MX51_PAD_UART3_TXD__GPIO1_23 IOMUX_PAD(0x634, 0x244, 3, 0x0000, 0, 0) | ||
| 483 | #define _MX51_PAD_UART3_TXD__UART1_DSR IOMUX_PAD(0x634, 0x244, 0, 0x0000, 0, 0) | ||
| 484 | #define _MX51_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x634, 0x244, 1, 0x0000, 0, 0) | ||
| 485 | #define _MX51_PAD_OWIRE_LINE__GPIO1_24 IOMUX_PAD(0x638, 0x248, 3, 0x0000, 0, 0) | ||
| 486 | #define _MX51_PAD_OWIRE_LINE__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 0, 0x0000, 0, 0) | ||
| 487 | #define _MX51_PAD_OWIRE_LINE__SPDIF_OUT IOMUX_PAD(0x638, 0x248, 6, 0x0000, 0, 0) | ||
| 488 | #define _MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63c, 0x24c, 0, 0x0000, 0, 0) | ||
| 489 | #define _MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0000, 0, 0) | ||
| 490 | #define _MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0000, 0, 0) | ||
| 491 | #define _MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0000, 0, 0) | ||
| 492 | #define _MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64c, 0x25c, 0, 0x0000, 0, 0) | ||
| 493 | #define _MX51_PAD_KEY_COL0__PLL1_BYP IOMUX_PAD(0x64c, 0x25c, 7, 0x090c, 0, 0) | ||
| 494 | #define _MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0000, 0, 0) | ||
| 495 | #define _MX51_PAD_KEY_COL1__PLL2_BYP IOMUX_PAD(0x650, 0x260, 7, 0x0910, 0, 0) | ||
| 496 | #define _MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0000, 0, 0) | ||
| 497 | #define _MX51_PAD_KEY_COL2__PLL3_BYP IOMUX_PAD(0x654, 0x264, 7, 0x0000, 0, 0) | ||
| 498 | #define _MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0000, 0, 0) | ||
| 499 | #define _MX51_PAD_KEY_COL4__I2C2_SCL IOMUX_PAD(0x65c, 0x26c, 0x13, 0x09b8, 1, 0) | ||
| 500 | #define _MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65c, 0x26c, 0, 0x0000, 0, 0) | ||
| 501 | #define _MX51_PAD_KEY_COL4__SPDIF_OUT1 IOMUX_PAD(0x65c, 0x26c, 6, 0x0000, 0, 0) | ||
| 502 | #define _MX51_PAD_KEY_COL4__UART1_RI IOMUX_PAD(0x65c, 0x26c, 1, 0x0000, 0, 0) | ||
| 503 | #define _MX51_PAD_KEY_COL4__UART3_RTS IOMUX_PAD(0x65c, 0x26c, 2, 0x09f0, 4, 0) | ||
| 504 | #define _MX51_PAD_KEY_COL5__I2C2_SDA IOMUX_PAD(0x660, 0x270, 0x13, 0x09bc, 1, 0) | ||
| 505 | #define _MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0000, 0, 0) | ||
| 506 | #define _MX51_PAD_KEY_COL5__UART1_DCD IOMUX_PAD(0x660, 0x270, 1, 0x0000, 0, 0) | ||
| 507 | #define _MX51_PAD_KEY_COL5__UART3_CTS IOMUX_PAD(0x660, 0x270, 2, 0x0000, 0, 0) | ||
| 508 | #define _MX51_PAD_USBH1_CLK__CSPI_SCLK IOMUX_PAD(0x678, 0x278, 1, 0x0914, 1, 0) | ||
| 509 | #define _MX51_PAD_USBH1_CLK__GPIO1_25 IOMUX_PAD(0x678, 0x278, 2, 0x0000, 0, 0) | ||
| 510 | #define _MX51_PAD_USBH1_CLK__I2C2_SCL IOMUX_PAD(0x678, 0x278, 0x15, 0x09b8, 2, 0) | ||
| 511 | #define _MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, 0, 0x0000, 0, 0) | ||
| 512 | #define _MX51_PAD_USBH1_DIR__CSPI_MOSI IOMUX_PAD(0x67c, 0x27c, 1, 0x091c, 1, 0) | ||
| 513 | #define _MX51_PAD_USBH1_DIR__GPIO1_26 IOMUX_PAD(0x67c, 0x27c, 2, 0x0000, 0, 0) | ||
| 514 | #define _MX51_PAD_USBH1_DIR__I2C2_SDA IOMUX_PAD(0x67c, 0x27c, 0x15, 0x09bc, 2, 0) | ||
| 515 | #define _MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67c, 0x27c, 0, 0x0000, 0, 0) | ||
| 516 | #define _MX51_PAD_USBH1_STP__CSPI_RDY IOMUX_PAD(0x680, 0x280, 1, 0x0000, 0, 0) | ||
| 517 | #define _MX51_PAD_USBH1_STP__GPIO1_27 IOMUX_PAD(0x680, 0x280, 2, 0x0000, 0, 0) | ||
| 518 | #define _MX51_PAD_USBH1_STP__UART3_RXD IOMUX_PAD(0x680, 0x280, 5, 0x09f4, 6, 0) | ||
| 519 | #define _MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, 0, 0x0000, 0, 0) | ||
| 520 | #define _MX51_PAD_USBH1_NXT__CSPI_MISO IOMUX_PAD(0x684, 0x284, 1, 0x0918, 0, 0) | ||
| 521 | #define _MX51_PAD_USBH1_NXT__GPIO1_28 IOMUX_PAD(0x684, 0x284, 2, 0x0000, 0, 0) | ||
| 522 | #define _MX51_PAD_USBH1_NXT__UART3_TXD IOMUX_PAD(0x684, 0x284, 5, 0x0000, 0, 0) | ||
| 523 | #define _MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, 0, 0x0000, 0, 0) | ||
| 524 | #define _MX51_PAD_USBH1_DATA0__GPIO1_11 IOMUX_PAD(0x688, 0x288, 2, 0x0000, 0, 0) | ||
| 525 | #define _MX51_PAD_USBH1_DATA0__UART2_CTS IOMUX_PAD(0x688, 0x288, 1, 0x0000, 0, 0) | ||
| 526 | #define _MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 0, 0x0000, 0, 0) | ||
| 527 | #define _MX51_PAD_USBH1_DATA1__GPIO1_12 IOMUX_PAD(0x68c, 0x28c, 2, 0x0000, 0, 0) | ||
| 528 | #define _MX51_PAD_USBH1_DATA1__UART2_RXD IOMUX_PAD(0x68c, 0x28c, 1, 0x09ec, 4, 0) | ||
| 529 | #define _MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68c, 0x28c, 0, 0x0000, 0, 0) | ||
| 530 | #define _MX51_PAD_USBH1_DATA2__GPIO1_13 IOMUX_PAD(0x690, 0x290, 2, 0x0000, 0, 0) | ||
| 531 | #define _MX51_PAD_USBH1_DATA2__UART2_TXD IOMUX_PAD(0x690, 0x290, 1, 0x0000, 0, 0) | ||
| 532 | #define _MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, 0x0000, 0, 0) | ||
| 533 | #define _MX51_PAD_USBH1_DATA3__GPIO1_14 IOMUX_PAD(0x694, 0x294, 2, 0x0000, 0, 0) | ||
| 534 | #define _MX51_PAD_USBH1_DATA3__UART2_RTS IOMUX_PAD(0x694, 0x294, 1, 0x09e8, 5, 0) | ||
| 535 | #define _MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 0, 0x0000, 0, 0) | ||
| 536 | #define _MX51_PAD_USBH1_DATA4__CSPI_SS0 IOMUX_PAD(0x698, 0x298, 1, 0x0000, 0, 0) | ||
| 537 | #define _MX51_PAD_USBH1_DATA4__GPIO1_15 IOMUX_PAD(0x698, 0x298, 2, 0x0000, 0, 0) | ||
| 538 | #define _MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 0, 0x0000, 0, 0) | ||
| 539 | #define _MX51_PAD_USBH1_DATA5__CSPI_SS1 IOMUX_PAD(0x69c, 0x29c, 1, 0x0920, 0, 0) | ||
| 540 | #define _MX51_PAD_USBH1_DATA5__GPIO1_16 IOMUX_PAD(0x69c, 0x29c, 2, 0x0000, 0, 0) | ||
| 541 | #define _MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69c, 0x29c, 0, 0x0000, 0, 0) | ||
| 542 | #define _MX51_PAD_USBH1_DATA6__CSPI_SS3 IOMUX_PAD(0x6a0, 0x2a0, 1, 0x0928, 1, 0) | ||
| 543 | #define _MX51_PAD_USBH1_DATA6__GPIO1_17 IOMUX_PAD(0x6a0, 0x2a0, 2, 0x0000, 0, 0) | ||
| 544 | #define _MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6a0, 0x2a0, 0, 0x0000, 0, 0) | ||
| 545 | #define _MX51_PAD_USBH1_DATA7__ECSPI1_SS3 IOMUX_PAD(0x6a4, 0x2a4, 1, 0x0000, 0, 0) | ||
| 546 | #define _MX51_PAD_USBH1_DATA7__ECSPI2_SS3 IOMUX_PAD(0x6a4, 0x2a4, 5, 0x0934, 1, 0) | ||
| 547 | #define _MX51_PAD_USBH1_DATA7__GPIO1_18 IOMUX_PAD(0x6a4, 0x2a4, 2, 0x0000, 0, 0) | ||
| 548 | #define _MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6a4, 0x2a4, 0, 0x0000, 0, 0) | ||
| 549 | #define _MX51_PAD_DI1_PIN11__DI1_PIN11 IOMUX_PAD(0x6a8, 0x2a8, 0, 0x0000, 0, 0) | ||
| 550 | #define _MX51_PAD_DI1_PIN11__ECSPI1_SS2 IOMUX_PAD(0x6a8, 0x2a8, 7, 0x0000, 0, 0) | ||
| 551 | #define _MX51_PAD_DI1_PIN11__GPIO3_0 IOMUX_PAD(0x6a8, 0x2a8, 4, 0x0000, 0, 0) | ||
| 552 | #define _MX51_PAD_DI1_PIN12__DI1_PIN12 IOMUX_PAD(0x6ac, 0x2ac, 0, 0x0000, 0, 0) | ||
| 553 | #define _MX51_PAD_DI1_PIN12__GPIO3_1 IOMUX_PAD(0x6ac, 0x2ac, 4, 0x0978, 1, 0) | ||
| 554 | #define _MX51_PAD_DI1_PIN13__DI1_PIN13 IOMUX_PAD(0x6b0, 0x2b0, 0, 0x0000, 0, 0) | ||
| 555 | #define _MX51_PAD_DI1_PIN13__GPIO3_2 IOMUX_PAD(0x6b0, 0x2b0, 4, 0x097c, 1, 0) | ||
| 556 | #define _MX51_PAD_DI1_D0_CS__DI1_D0_CS IOMUX_PAD(0x6b4, 0x2b4, 0, 0x0000, 0, 0) | ||
| 557 | #define _MX51_PAD_DI1_D0_CS__GPIO3_3 IOMUX_PAD(0x6b4, 0x2b4, 4, 0x0980, 1, 0) | ||
| 558 | #define _MX51_PAD_DI1_D1_CS__DI1_D1_CS IOMUX_PAD(0x6b8, 0x2b8, 0, 0x0000, 0, 0) | ||
| 559 | #define _MX51_PAD_DI1_D1_CS__DISP1_PIN14 IOMUX_PAD(0x6b8, 0x2b8, 2, 0x0000, 0, 0) | ||
| 560 | #define _MX51_PAD_DI1_D1_CS__DISP1_PIN5 IOMUX_PAD(0x6b8, 0x2b8, 3, 0x0000, 0, 0) | ||
| 561 | #define _MX51_PAD_DI1_D1_CS__GPIO3_4 IOMUX_PAD(0x6b8, 0x2b8, 4, 0x0984, 1, 0) | ||
| 562 | #define _MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 IOMUX_PAD(0x6bc, 0x2bc, 2, 0x09a4, 1, 0) | ||
| 563 | #define _MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN IOMUX_PAD(0x6bc, 0x2bc, 0, 0x09c4, 0, 0) | ||
| 564 | #define _MX51_PAD_DISPB2_SER_DIN__GPIO3_5 IOMUX_PAD(0x6bc, 0x2bc, 4, 0x0988, 1, 0) | ||
| 565 | #define _MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 IOMUX_PAD(0x6c0, 0x2c0, 3, 0x0000, 0, 0) | ||
| 566 | #define _MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO IOMUX_PAD(0x6c0, 0x2c0, 0, 0x09c4, 1, 0) | ||
| 567 | #define _MX51_PAD_DISPB2_SER_DIO__GPIO3_6 IOMUX_PAD(0x6c0, 0x2c0, 4, 0x098c, 1, 0) | ||
| 568 | #define _MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 IOMUX_PAD(0x6c4, 0x2c4, 2, 0x0000, 0, 0) | ||
| 569 | #define _MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 IOMUX_PAD(0x6c4, 0x2c4, 3, 0x0000, 0, 0) | ||
| 570 | #define _MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK IOMUX_PAD(0x6c4, 0x2c4, 0, 0x0000, 0, 0) | ||
| 571 | #define _MX51_PAD_DISPB2_SER_CLK__GPIO3_7 IOMUX_PAD(0x6c4, 0x2c4, 4, 0x0990, 1, 0) | ||
| 572 | #define _MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK IOMUX_PAD(0x6c8, 0x2c8, 2, 0x0000, 0, 0) | ||
| 573 | #define _MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 IOMUX_PAD(0x6c8, 0x2c8, 2, 0x0000, 0, 0) | ||
| 574 | #define _MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 IOMUX_PAD(0x6c8, 0x2c8, 3, 0x0000, 0, 0) | ||
| 575 | #define _MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, 0x0000, 0, 0) | ||
| 576 | #define _MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, 0x0000, 0, 0) | ||
| 577 | #define _MX51_PAD_DISPB2_SER_RS__GPIO3_8 IOMUX_PAD(0x6c8, 0x2c8, 4, 0x0994, 1, 0) | ||
| 578 | #define _MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6cc, 0x2cc, 0, 0x0000, 0, 0) | ||
| 579 | #define _MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6d0, 0x2d0, 0, 0x0000, 0, 0) | ||
| 580 | #define _MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6d4, 0x2d4, 0, 0x0000, 0, 0) | ||
| 581 | #define _MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6d8, 0x2d8, 0, 0x0000, 0, 0) | ||
| 582 | #define _MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6dc, 0x2dc, 0, 0x0000, 0, 0) | ||
| 583 | #define _MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6e0, 0x2e0, 0, 0x0000, 0, 0) | ||
| 584 | #define _MX51_PAD_DISP1_DAT6__BOOT_USB_SRC IOMUX_PAD(0x6e4, 0x2e4, 7, 0x0000, 0, 0) | ||
| 585 | #define _MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6e4, 0x2e4, 0, 0x0000, 0, 0) | ||
| 586 | #define _MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG IOMUX_PAD(0x6e8, 0x2e8, 7, 0x0000, 0, 0) | ||
| 587 | #define _MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6e8, 0x2e8, 0, 0x0000, 0, 0) | ||
| 588 | #define _MX51_PAD_DISP1_DAT8__BOOT_SRC0 IOMUX_PAD(0x6ec, 0x2ec, 7, 0x0000, 0, 0) | ||
| 589 | #define _MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6ec, 0x2ec, 0, 0x0000, 0, 0) | ||
| 590 | #define _MX51_PAD_DISP1_DAT9__BOOT_SRC1 IOMUX_PAD(0x6f0, 0x2f0, 7, 0x0000, 0, 0) | ||
| 591 | #define _MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6f0, 0x2f0, 0, 0x0000, 0, 0) | ||
| 592 | #define _MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE IOMUX_PAD(0x6f4, 0x2f4, 7, 0x0000, 0, 0) | ||
| 593 | #define _MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6f4, 0x2f4, 0, 0x0000, 0, 0) | ||
| 594 | #define _MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 IOMUX_PAD(0x6f8, 0x2f8, 7, 0x0000, 0, 0) | ||
| 595 | #define _MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6f8, 0x2f8, 0, 0x0000, 0, 0) | ||
| 596 | #define _MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL IOMUX_PAD(0x6fc, 0x2fc, 7, 0x0000, 0, 0) | ||
| 597 | #define _MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6fc, 0x2fc, 0, 0x0000, 0, 0) | ||
| 598 | #define _MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 IOMUX_PAD(0x700, 0x300, 7, 0x0000, 0, 0) | ||
| 599 | #define _MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, 0x0000, 0, 0) | ||
| 600 | #define _MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 IOMUX_PAD(0x704, 0x304, 7, 0x0000, 0, 0) | ||
| 601 | #define _MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, 0x0000, 0, 0) | ||
| 602 | #define _MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH IOMUX_PAD(0x708, 0x308, 7, 0x0000, 0, 0) | ||
| 603 | #define _MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, 0x0000, 0, 0) | ||
| 604 | #define _MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 IOMUX_PAD(0x70c, 0x30c, 7, 0x0000, 0, 0) | ||
| 605 | #define _MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70c, 0x30c, 0, 0x0000, 0, 0) | ||
| 606 | #define _MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 IOMUX_PAD(0x710, 0x310, 7, 0x0000, 0, 0) | ||
| 607 | #define _MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, 0x0000, 0, 0) | ||
| 608 | #define _MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 IOMUX_PAD(0x714, 0x314, 7, 0x0000, 0, 0) | ||
| 609 | #define _MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, 0x0000, 0, 0) | ||
| 610 | #define _MX51_PAD_DISP1_DAT18__DISP2_PIN11 IOMUX_PAD(0x714, 0x314, 5, 0x0000, 0, 0) | ||
| 611 | #define _MX51_PAD_DISP1_DAT18__DISP2_PIN5 IOMUX_PAD(0x714, 0x314, 4, 0x0000, 0, 0) | ||
| 612 | #define _MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 IOMUX_PAD(0x718, 0x318, 7, 0x0000, 0, 0) | ||
| 613 | #define _MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0000, 0, 0) | ||
| 614 | #define _MX51_PAD_DISP1_DAT19__DISP2_PIN12 IOMUX_PAD(0x718, 0x318, 5, 0x0000, 0, 0) | ||
| 615 | #define _MX51_PAD_DISP1_DAT19__DISP2_PIN6 IOMUX_PAD(0x718, 0x318, 4, 0x0000, 0, 0) | ||
| 616 | #define _MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 IOMUX_PAD(0x71c, 0x31c, 7, 0x0000, 0, 0) | ||
| 617 | #define _MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71c, 0x31c, 0, 0x0000, 0, 0) | ||
| 618 | #define _MX51_PAD_DISP1_DAT20__DISP2_PIN13 IOMUX_PAD(0x71c, 0x31c, 5, 0x0000, 0, 0) | ||
| 619 | #define _MX51_PAD_DISP1_DAT20__DISP2_PIN7 IOMUX_PAD(0x71c, 0x31c, 4, 0x0000, 0, 0) | ||
| 620 | #define _MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 IOMUX_PAD(0x720, 0x320, 7, 0x0000, 0, 0) | ||
| 621 | #define _MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0000, 0, 0) | ||
| 622 | #define _MX51_PAD_DISP1_DAT21__DISP2_PIN14 IOMUX_PAD(0x720, 0x320, 5, 0x0000, 0, 0) | ||
| 623 | #define _MX51_PAD_DISP1_DAT21__DISP2_PIN8 IOMUX_PAD(0x720, 0x320, 4, 0x0000, 0, 0) | ||
| 624 | #define _MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 IOMUX_PAD(0x724, 0x324, 7, 0x0000, 0, 0) | ||
| 625 | #define _MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0000, 0, 0) | ||
| 626 | #define _MX51_PAD_DISP1_DAT22__DISP2_D0_CS IOMUX_PAD(0x724, 0x324, 6, 0x0000, 0, 0) | ||
| 627 | #define _MX51_PAD_DISP1_DAT22__DISP2_DAT16 IOMUX_PAD(0x724, 0x324, 5, 0x0000, 0, 0) | ||
| 628 | #define _MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 IOMUX_PAD(0x728, 0x328, 7, 0x0000, 0, 0) | ||
| 629 | #define _MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0000, 0, 0) | ||
| 630 | #define _MX51_PAD_DISP1_DAT23__DISP2_D1_CS IOMUX_PAD(0x728, 0x328, 6, 0x0000, 0, 0) | ||
| 631 | #define _MX51_PAD_DISP1_DAT23__DISP2_DAT17 IOMUX_PAD(0x728, 0x328, 5, 0x0000, 0, 0) | ||
| 632 | #define _MX51_PAD_DISP1_DAT23__DISP2_SER_CS IOMUX_PAD(0x728, 0x328, 4, 0x0000, 0, 0) | ||
| 633 | #define _MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72c, 0x32c, 0, 0x0000, 0, 0) | ||
| 634 | #define _MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0000, 0, 0) | ||
| 635 | #define _MX51_PAD_DI_GP2__DISP1_SER_CLK IOMUX_PAD(0x740, 0x338, 0, 0x0000, 0, 0) | ||
| 636 | #define _MX51_PAD_DI_GP2__DISP2_WAIT IOMUX_PAD(0x740, 0x338, 2, 0x09a8, 1, 0) | ||
| 637 | #define _MX51_PAD_DI_GP3__CSI1_DATA_EN IOMUX_PAD(0x744, 0x33c, 3, 0x09a0, 1, 0) | ||
| 638 | #define _MX51_PAD_DI_GP3__DISP1_SER_DIO IOMUX_PAD(0x744, 0x33c, 0, 0x09c0, 0, 0) | ||
| 639 | #define _MX51_PAD_DI_GP3__FEC_TX_ER IOMUX_PAD(0x744, 0x33c, 2, 0x0000, 0, 0) | ||
| 640 | #define _MX51_PAD_DI2_PIN4__CSI2_DATA_EN IOMUX_PAD(0x748, 0x340, 3, 0x099c, 1, 0) | ||
| 641 | #define _MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0000, 0, 0) | ||
| 642 | #define _MX51_PAD_DI2_PIN4__FEC_CRS IOMUX_PAD(0x748, 0x340, 2, 0x0950, 1, 0) | ||
| 643 | #define _MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74c, 0x344, 0, 0x0000, 0, 0) | ||
| 644 | #define _MX51_PAD_DI2_PIN2__FEC_MDC IOMUX_PAD(0x74c, 0x344, 2, 0x0000, 0, 0) | ||
| 645 | #define _MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0000, 0, 0) | ||
| 646 | #define _MX51_PAD_DI2_PIN3__FEC_MDIO IOMUX_PAD(0x750, 0x348, 2, 0x0954, 1, 0) | ||
| 647 | #define _MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34c, 0, 0x0000, 0, 0) | ||
| 648 | #define _MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 IOMUX_PAD(0x754, 0x34c, 2, 0x095c, 1, 0) | ||
| 649 | #define _MX51_PAD_DI_GP4__DI2_PIN15 IOMUX_PAD(0x758, 0x350, 4, 0x0000, 0, 0) | ||
| 650 | #define _MX51_PAD_DI_GP4__DISP1_SER_DIN IOMUX_PAD(0x758, 0x350, 0, 0x09c0, 1, 0) | ||
| 651 | #define _MX51_PAD_DI_GP4__DISP2_PIN1 IOMUX_PAD(0x758, 0x350, 3, 0x0000, 0, 0) | ||
| 652 | #define _MX51_PAD_DI_GP4__FEC_RDATA2 IOMUX_PAD(0x758, 0x350, 2, 0x0960, 1, 0) | ||
| 653 | #define _MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75c, 0x354, 0, 0x0000, 0, 0) | ||
| 654 | #define _MX51_PAD_DISP2_DAT0__FEC_RDATA3 IOMUX_PAD(0x75c, 0x354, 2, 0x0964, 1, 0) | ||
| 655 | #define _MX51_PAD_DISP2_DAT0__KEY_COL6 IOMUX_PAD(0x75c, 0x354, 4, 0x09c8, 1, 0) | ||
| 656 | #define _MX51_PAD_DISP2_DAT0__UART3_RXD IOMUX_PAD(0x75c, 0x354, 5, 0x09f4, 8, 0) | ||
| 657 | #define _MX51_PAD_DISP2_DAT0__USBH3_CLK IOMUX_PAD(0x75c, 0x354, 3, 0x09f8, 1, 0) | ||
| 658 | #define _MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0000, 0, 0) | ||
| 659 | #define _MX51_PAD_DISP2_DAT1__FEC_RX_ER IOMUX_PAD(0x760, 0x358, 2, 0x0970, 1, 0) | ||
| 660 | #define _MX51_PAD_DISP2_DAT1__KEY_COL7 IOMUX_PAD(0x760, 0x358, 4, 0x09cc, 1, 0) | ||
| 661 | #define _MX51_PAD_DISP2_DAT1__UART3_TXD IOMUX_PAD(0x760, 0x358, 5, 0x0000, 0, 0) | ||
| 662 | #define _MX51_PAD_DISP2_DAT1__USBH3_DIR IOMUX_PAD(0x760, 0x358, 3, 0x0a1c, 1, 0) | ||
| 663 | #define _MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35c, 0, 0x0000, 0, 0) | ||
| 664 | #define _MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0000, 0, 0) | ||
| 665 | #define _MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76c, 0x364, 0, 0x0000, 0, 0) | ||
| 666 | #define _MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0000, 0, 0) | ||
| 667 | #define _MX51_PAD_DISP2_DAT6__DISP2_DAT6 IOMUX_PAD(0x774, 0x36c, 0, 0x0000, 0, 0) | ||
| 668 | #define _MX51_PAD_DISP2_DAT6__FEC_TDATA1 IOMUX_PAD(0x774, 0x36c, 2, 0x0000, 0, 0) | ||
| 669 | #define _MX51_PAD_DISP2_DAT6__GPIO1_19 IOMUX_PAD(0x774, 0x36c, 5, 0x0000, 0, 0) | ||
| 670 | #define _MX51_PAD_DISP2_DAT6__KEY_ROW4 IOMUX_PAD(0x774, 0x36c, 4, 0x09d0, 1, 0) | ||
| 671 | #define _MX51_PAD_DISP2_DAT6__USBH3_STP IOMUX_PAD(0x774, 0x36c, 3, 0x0a24, 1, 0) | ||
| 672 | #define _MX51_PAD_DISP2_DAT7__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 0, 0x0000, 0, 0) | ||
| 673 | #define _MX51_PAD_DISP2_DAT7__FEC_TDATA2 IOMUX_PAD(0x778, 0x370, 2, 0x0000, 0, 0) | ||
| 674 | #define _MX51_PAD_DISP2_DAT7__GPIO1_29 IOMUX_PAD(0x778, 0x370, 5, 0x0000, 0, 0) | ||
| 675 | #define _MX51_PAD_DISP2_DAT7__KEY_ROW5 IOMUX_PAD(0x778, 0x370, 4, 0x09d4, 1, 0) | ||
| 676 | #define _MX51_PAD_DISP2_DAT7__USBH3_NXT IOMUX_PAD(0x778, 0x370, 3, 0x0a20, 1, 0) | ||
| 677 | #define _MX51_PAD_DISP2_DAT8__DISP2_DAT8 IOMUX_PAD(0x77c, 0x374, 0, 0x0000, 0, 0) | ||
| 678 | #define _MX51_PAD_DISP2_DAT8__FEC_TDATA3 IOMUX_PAD(0x77c, 0x374, 2, 0x0000, 0, 0) | ||
| 679 | #define _MX51_PAD_DISP2_DAT8__GPIO1_30 IOMUX_PAD(0x77c, 0x374, 5, 0x0000, 0, 0) | ||
| 680 | #define _MX51_PAD_DISP2_DAT8__KEY_ROW6 IOMUX_PAD(0x77c, 0x374, 4, 0x09d8, 1, 0) | ||
| 681 | #define _MX51_PAD_DISP2_DAT8__USBH3_DATA0 IOMUX_PAD(0x77c, 0x374, 3, 0x09fc, 1, 0) | ||
| 682 | #define _MX51_PAD_DISP2_DAT9__AUD6_RXC IOMUX_PAD(0x780, 0x378, 4, 0x08f4, 1, 0) | ||
| 683 | #define _MX51_PAD_DISP2_DAT9__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 0, 0x0000, 0, 0) | ||
| 684 | #define _MX51_PAD_DISP2_DAT9__FEC_TX_EN IOMUX_PAD(0x780, 0x378, 2, 0x0000, 0, 0) | ||
| 685 | #define _MX51_PAD_DISP2_DAT9__GPIO1_31 IOMUX_PAD(0x780, 0x378, 5, 0x0000, 0, 0) | ||
| 686 | #define _MX51_PAD_DISP2_DAT9__USBH3_DATA1 IOMUX_PAD(0x780, 0x378, 3, 0x0a00, 1, 0) | ||
| 687 | #define _MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37c, 0, 0x0000, 0, 0) | ||
| 688 | #define _MX51_PAD_DISP2_DAT10__DISP2_SER_CS IOMUX_PAD(0x784, 0x37c, 5, 0x0000, 0, 0) | ||
| 689 | #define _MX51_PAD_DISP2_DAT10__FEC_COL IOMUX_PAD(0x784, 0x37c, 2, 0x094c, 1, 0) | ||
| 690 | #define _MX51_PAD_DISP2_DAT10__KEY_ROW7 IOMUX_PAD(0x784, 0x37c, 4, 0x09dc, 1, 0) | ||
| 691 | #define _MX51_PAD_DISP2_DAT10__USBH3_DATA2 IOMUX_PAD(0x784, 0x37c, 3, 0x0a04, 1, 0) | ||
| 692 | #define _MX51_PAD_DISP2_DAT11__AUD6_TXD IOMUX_PAD(0x788, 0x380, 4, 0x08f0, 1, 0) | ||
| 693 | #define _MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0000, 0, 0) | ||
| 694 | #define _MX51_PAD_DISP2_DAT11__FEC_RX_CLK IOMUX_PAD(0x788, 0x380, 2, 0x0968, 1, 0) | ||
| 695 | #define _MX51_PAD_DISP2_DAT11__GPIO1_10 IOMUX_PAD(0x788, 0x380, 7, 0x0000, 0, 0) | ||
| 696 | #define _MX51_PAD_DISP2_DAT11__USBH3_DATA3 IOMUX_PAD(0x788, 0x380, 3, 0x0a08, 1, 0) | ||
| 697 | #define _MX51_PAD_DISP2_DAT12__AUD6_RXD IOMUX_PAD(0x78c, 0x384, 4, 0x08ec, 1, 0) | ||
| 698 | #define _MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78c, 0x384, 0, 0x0000, 0, 0) | ||
| 699 | #define _MX51_PAD_DISP2_DAT12__FEC_RX_DV IOMUX_PAD(0x78c, 0x384, 2, 0x096c, 1, 0) | ||
| 700 | #define _MX51_PAD_DISP2_DAT12__USBH3_DATA4 IOMUX_PAD(0x78c, 0x384, 3, 0x0a0c, 1, 0) | ||
| 701 | #define _MX51_PAD_DISP2_DAT13__AUD6_TXC IOMUX_PAD(0x790, 0x388, 4, 0x08fc, 1, 0) | ||
| 702 | #define _MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0000, 0, 0) | ||
| 703 | #define _MX51_PAD_DISP2_DAT13__FEC_TX_CLK IOMUX_PAD(0x790, 0x388, 2, 0x0974, 1, 0) | ||
| 704 | #define _MX51_PAD_DISP2_DAT13__USBH3_DATA5 IOMUX_PAD(0x790, 0x388, 3, 0x0a10, 1, 0) | ||
| 705 | #define _MX51_PAD_DISP2_DAT14__AUD6_TXFS IOMUX_PAD(0x794, 0x38c, 4, 0x0900, 1, 0) | ||
| 706 | #define _MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38c, 0, 0x0000, 0, 0) | ||
| 707 | #define _MX51_PAD_DISP2_DAT14__FEC_RDATA0 IOMUX_PAD(0x794, 0x38c, 2, 0x0958, 1, 0) | ||
| 708 | #define _MX51_PAD_DISP2_DAT14__USBH3_DATA6 IOMUX_PAD(0x794, 0x38c, 3, 0x0a14, 1, 0) | ||
| 709 | #define _MX51_PAD_DISP2_DAT15__AUD6_RXFS IOMUX_PAD(0x798, 0x390, 4, 0x08f8, 1, 0) | ||
| 710 | #define _MX51_PAD_DISP2_DAT15__DISP1_SER_CS IOMUX_PAD(0x798, 0x390, 5, 0x0000, 0, 0) | ||
| 711 | #define _MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0000, 0, 0) | ||
| 712 | #define _MX51_PAD_DISP2_DAT15__FEC_TDATA0 IOMUX_PAD(0x798, 0x390, 2, 0x0000, 0, 0) | ||
| 713 | #define _MX51_PAD_DISP2_DAT15__USBH3_DATA7 IOMUX_PAD(0x798, 0x390, 3, 0x0a18, 1, 0) | ||
| 714 | #define _MX51_PAD_SD1_CMD__AUD5_RXFS IOMUX_PAD(0x79c, 0x394, 1, 0x08e0, 1, 0) | ||
| 715 | #define _MX51_PAD_SD1_CMD__CSPI_MOSI IOMUX_PAD(0x79c, 0x394, 2, 0x091c, 2, 0) | ||
| 716 | #define _MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79c, 0x394, 0x10, 0x0000, 0, 0) | ||
| 717 | #define _MX51_PAD_SD1_CLK__AUD5_RXC IOMUX_PAD(0x7a0, 0x398, 1, 0x08dc, 1, 0) | ||
| 718 | #define _MX51_PAD_SD1_CLK__CSPI_SCLK IOMUX_PAD(0x7a0, 0x398, 2, 0x0914, 2, 0) | ||
| 719 | #define _MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7a0, 0x398, 0x10, 0x0000, 0, 0) | ||
| 720 | #define _MX51_PAD_SD1_DATA0__AUD5_TXD IOMUX_PAD(0x7a4, 0x39c, 1, 0x08d8, 2, 0) | ||
| 721 | #define _MX51_PAD_SD1_DATA0__CSPI_MISO IOMUX_PAD(0x7a4, 0x39c, 2, 0x0918, 1, 0) | ||
| 722 | #define _MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7a4, 0x39c, 0x10, 0x0000, 0, 0) | ||
| 723 | #define _MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x000, 0x01c, 0, 0x0000, 0, 0) | ||
| 724 | #define _MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x000, 0x020, 0, 0x0000, 0, 0) | ||
| 725 | #define _MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x000, 0x024, 0, 0x0000, 0, 0) | ||
| 726 | #define _MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x000, 0x028, 0, 0x0000, 0, 0) | ||
| 727 | #define _MX51_PAD_SD1_DATA1__AUD5_RXD IOMUX_PAD(0x7a8, 0x3a0, 1, 0x08d4, 2, 0) | ||
| 728 | #define _MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7a8, 0x3a0, 0x10, 0x0000, 0, 0) | ||
| 729 | #define _MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x000, 0x02c, 0, 0x0000, 0, 0) | ||
| 730 | #define _MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x000, 0x030, 0, 0x0000, 0, 0) | ||
| 731 | #define _MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x000, 0x034, 0, 0x0000, 0, 0) | ||
| 732 | #define _MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x000, 0x038, 0, 0x0000, 0, 0) | ||
| 733 | #define _MX51_PAD_SD1_DATA2__AUD5_TXC IOMUX_PAD(0x7ac, 0x3a4, 1, 0x08e4, 2, 0) | ||
| 734 | #define _MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7ac, 0x3a4, 0x10, 0x0000, 0, 0) | ||
| 735 | #define _MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x000, 0x044, 0, 0x0000, 0, 0) | ||
| 736 | #define _MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x000, 0x048, 0, 0x0000, 0, 0) | ||
| 737 | #define _MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x000, 0x03c, 0, 0x0000, 0, 0) | ||
| 738 | #define _MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x000, 0x040, 0, 0x0000, 0, 0) | ||
| 739 | #define _MX51_PAD_SD1_DATA3__AUD5_TXFS IOMUX_PAD(0x7b0, 0x3a8, 1, 0x08e8, 2, 0) | ||
| 740 | #define _MX51_PAD_SD1_DATA3__CSPI_SS1 IOMUX_PAD(0x7b0, 0x3a8, 2, 0x0920, 1, 0) | ||
| 741 | #define _MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7b0, 0x3a8, 0x10, 0x0000, 0, 0) | ||
| 742 | #define _MX51_PAD_GPIO1_0__CSPI_SS2 IOMUX_PAD(0x7b4, 0x3ac, 2, 0x0924, 0, 0) | ||
| 743 | #define _MX51_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x7b4, 0x3ac, 1, 0x0000, 0, 0) | ||
| 744 | #define _MX51_PAD_GPIO1_0__SD1_CD IOMUX_PAD(0x7b4, 0x3ac, 0, 0x0000, 0, 0) | ||
| 745 | #define _MX51_PAD_GPIO1_1__CSPI_MISO IOMUX_PAD(0x7b8, 0x3b0, 2, 0x0918, 2, 0) | ||
| 746 | #define _MX51_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x7b8, 0x3b0, 1, 0x0000, 0, 0) | ||
| 747 | #define _MX51_PAD_GPIO1_1__SD1_WP IOMUX_PAD(0x7b8, 0x3b0, 0, 0x0000, 0, 0) | ||
| 748 | #define _MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x000, 0x04c, 0, 0x0000, 0, 0) | ||
| 749 | #define _MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x000, 0x050, 0, 0x0000, 0, 0) | ||
| 750 | #define _MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x000, 0x054, 0, 0x0000, 0, 0) | ||
| 751 | #define _MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x000, 0x058, 0, 0x0000, 0, 0) | ||
| 752 | #define _MX51_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(0x000, 0x3b4, 2, 0x091c, 3, 0) | ||
| 753 | #define _MX51_PAD_SD2_CMD__I2C1_SCL IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x09b0, 2, 0) | ||
| 754 | #define _MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7bc, 0x3b4, 0x10, 0x0000, 0, 0) | ||
| 755 | #define _MX51_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x7c0, 0x3b8, 2, 0x0914, 3, 0) | ||
| 756 | #define _MX51_PAD_SD2_CLK__I2C1_SDA IOMUX_PAD(0x7c0, 0x3b8, 0x11, 0x09b4, 2, 0) | ||
| 757 | #define _MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7c0, 0x3b8, 0x10, 0x0000, 0, 0) | ||
| 758 | #define _MX51_PAD_SD2_DATA0__CSPI_MISO IOMUX_PAD(0x7c4, 0x3bc, 2, 0x0918, 3, 0) | ||
| 759 | #define _MX51_PAD_SD2_DATA0__SD1_DAT4 IOMUX_PAD(0x7c4, 0x3bc, 1, 0x0000, 0, 0) | ||
| 760 | #define _MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7c4, 0x3bc, 0x10, 0x0000, 0, 0) | ||
| 761 | #define _MX51_PAD_SD2_DATA1__SD1_DAT5 IOMUX_PAD(0x7c8, 0x3c0, 1, 0x0000, 0, 0) | ||
| 762 | #define _MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7c8, 0x3c0, 0x10, 0x0000, 0, 0) | ||
| 763 | #define _MX51_PAD_SD2_DATA1__USBH3_H2_DP IOMUX_PAD(0x7c8, 0x3c0, 2, 0x0000, 0, 0) | ||
| 764 | #define _MX51_PAD_SD2_DATA2__SD1_DAT6 IOMUX_PAD(0x7cc, 0x3c4, 1, 0x0000, 0, 0) | ||
| 765 | #define _MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7cc, 0x3c4, 0x10, 0x0000, 0, 0) | ||
| 766 | #define _MX51_PAD_SD2_DATA2__USBH3_H2_DM IOMUX_PAD(0x7cc, 0x3c4, 2, 0x0000, 0, 0) | ||
| 767 | #define _MX51_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x7d0, 0x3c8, 2, 0x0924, 1, 0) | ||
| 768 | #define _MX51_PAD_SD2_DATA3__SD1_DAT7 IOMUX_PAD(0x7d0, 0x3c8, 1, 0x0000, 0, 0) | ||
| 769 | #define _MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7d0, 0x3c8, 0x10, 0x0000, 0, 0) | ||
| 770 | #define _MX51_PAD_GPIO1_2__CCM_OUT_2 IOMUX_PAD(0x7d4, 0x3cc, 5, 0x0000, 0, 0) | ||
| 771 | #define _MX51_PAD_GPIO1_2__GPIO1_2 IOMUX_PAD(0x7d4, 0x3cc, 0, 0x0000, 0, 0) | ||
| 772 | #define _MX51_PAD_GPIO1_2__I2C2_SCL IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x09b8, 3, 0) | ||
| 773 | #define _MX51_PAD_GPIO1_2__PLL1_BYP IOMUX_PAD(0x7d4, 0x3cc, 7, 0x090c, 1, 0) | ||
| 774 | #define _MX51_PAD_GPIO1_2__PWM1_PWMO IOMUX_PAD(0x7d4, 0x3cc, 1, 0x0000, 0, 0) | ||
| 775 | #define _MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, 0x0000, 0, 0) | ||
| 776 | #define _MX51_PAD_GPIO1_3__I2C2_SDA IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x09bc, 3, 0) | ||
| 777 | #define _MX51_PAD_GPIO1_3__PLL2_BYP IOMUX_PAD(0x7d8, 0x3d0, 7, 0x0910, 1, 0) | ||
| 778 | #define _MX51_PAD_GPIO1_3__PWM2_PWMO IOMUX_PAD(0x7d8, 0x3d0, 1, 0x0000, 0, 0) | ||
| 779 | #define _MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7fc, 0x3d4, 0, 0x0000, 0, 0) | ||
| 780 | #define _MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B IOMUX_PAD(0x7fc, 0x3d4, 1, 0x0000, 0, 0) | ||
| 781 | #define _MX51_PAD_GPIO1_4__DISP2_EXT_CLK IOMUX_PAD(0x804, 0x3d8, 4, 0x0908, 1, 0) | ||
| 782 | #define _MX51_PAD_GPIO1_4__EIM_RDY IOMUX_PAD(0x804, 0x3d8, 3, 0x0938, 1, 0) | ||
| 783 | #define _MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, 0x0000, 0, 0) | ||
| 784 | #define _MX51_PAD_GPIO1_4__WDOG1_WDOG_B IOMUX_PAD(0x804, 0x3d8, 2, 0x0000, 0, 0) | ||
| 785 | #define _MX51_PAD_GPIO1_5__CSI2_MCLK IOMUX_PAD(0x808, 0x3dc, 6, 0x0000, 0, 0) | ||
| 786 | #define _MX51_PAD_GPIO1_5__DISP2_PIN16 IOMUX_PAD(0x808, 0x3dc, 3, 0x0000, 0, 0) | ||
| 787 | #define _MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, 0x0000, 0, 0) | ||
| 788 | #define _MX51_PAD_GPIO1_5__WDOG2_WDOG_B IOMUX_PAD(0x808, 0x3dc, 2, 0x0000, 0, 0) | ||
| 789 | #define _MX51_PAD_GPIO1_6__DISP2_PIN17 IOMUX_PAD(0x80c, 0x3e0, 4, 0x0000, 0, 0) | ||
| 790 | #define _MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, 0x0000, 0, 0) | ||
| 791 | #define _MX51_PAD_GPIO1_6__REF_EN_B IOMUX_PAD(0x80c, 0x3e0, 3, 0x0000, 0, 0) | ||
| 792 | #define _MX51_PAD_GPIO1_7__CCM_OUT_0 IOMUX_PAD(0x810, 0x3e4, 3, 0x0000, 0, 0) | ||
| 793 | #define _MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, 0x0000, 0, 0) | ||
| 794 | #define _MX51_PAD_GPIO1_7__SD2_WP IOMUX_PAD(0x810, 0x3e4, 6, 0x0000, 0, 0) | ||
| 795 | #define _MX51_PAD_GPIO1_7__SPDIF_OUT1 IOMUX_PAD(0x810, 0x3e4, 2, 0x0000, 0, 0) | ||
| 796 | #define _MX51_PAD_GPIO1_8__CSI2_DATA_EN IOMUX_PAD(0x814, 0x3e8, 2, 0x099c, 2, 0) | ||
| 797 | #define _MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, 0x0000, 0, 0) | ||
| 798 | #define _MX51_PAD_GPIO1_8__SD2_CD IOMUX_PAD(0x814, 0x3e8, 6, 0x0000, 0, 0) | ||
| 799 | #define _MX51_PAD_GPIO1_8__USBH3_PWR IOMUX_PAD(0x814, 0x3e8, 1, 0x0000, 0, 0) | ||
| 800 | #define _MX51_PAD_GPIO1_9__CCM_OUT_1 IOMUX_PAD(0x818, 0x3ec, 3, 0x0000, 0, 0) | ||
| 801 | #define _MX51_PAD_GPIO1_9__DISP2_D1_CS IOMUX_PAD(0x818, 0x3ec, 2, 0x0000, 0, 0) | ||
| 802 | #define _MX51_PAD_GPIO1_9__DISP2_SER_CS IOMUX_PAD(0x818, 0x3ec, 7, 0x0000, 0, 0) | ||
| 803 | #define _MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, 0x0000, 0, 0) | ||
| 804 | #define _MX51_PAD_GPIO1_9__SD2_LCTL IOMUX_PAD(0x818, 0x3ec, 6, 0x0000, 0, 0) | ||
| 805 | #define _MX51_PAD_GPIO1_9__USBH3_OC IOMUX_PAD(0x818, 0x3ec, 1, 0x0000, 0, 0) | ||
| 806 | 52 | ||
| 807 | /* The same pins as above but with the default pad control values applied */ | 53 | /* The same pins as above but with the default pad control values applied */ |
| 808 | #define MX51_PAD_EIM_D16__AUD4_RXFS (_MX51_PAD_EIM_D16__AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 54 | #define MX51_PAD_EIM_D16__AUD4_RXFS IOMUX_PAD(0x3f0, 0x05c, 5, __NA_, 0, NO_PAD_CTRL) |
| 809 | #define MX51_PAD_EIM_D16__AUD5_TXD (_MX51_PAD_EIM_D16__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 55 | #define MX51_PAD_EIM_D16__AUD5_TXD IOMUX_PAD(0x3f0, 0x05c, 7, 0x8d8, 0, NO_PAD_CTRL) |
| 810 | #define MX51_PAD_EIM_D16__EIM_D16 (_MX51_PAD_EIM_D16__EIM_D16 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 56 | #define MX51_PAD_EIM_D16__EIM_D16 IOMUX_PAD(0x3f0, 0x05c, 0, __NA_, 0, NO_PAD_CTRL) |
| 811 | #define MX51_PAD_EIM_D16__GPIO2_0 (_MX51_PAD_EIM_D16__GPIO2_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 57 | #define MX51_PAD_EIM_D16__GPIO2_0 IOMUX_PAD(0x3f0, 0x05c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 812 | #define MX51_PAD_EIM_D16__I2C1_SDA (_MX51_PAD_EIM_D16__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | 58 | #define MX51_PAD_EIM_D16__I2C1_SDA IOMUX_PAD(0x3f0, 0x05c, 0x14, 0x9b4, 0, MX51_I2C_PAD_CTRL) |
| 813 | #define MX51_PAD_EIM_D16__UART2_CTS (_MX51_PAD_EIM_D16__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 59 | #define MX51_PAD_EIM_D16__UART2_CTS IOMUX_PAD(0x3f0, 0x05c, 3, __NA_, 0, MX51_UART_PAD_CTRL) |
| 814 | #define MX51_PAD_EIM_D16__USBH2_DATA0 (_MX51_PAD_EIM_D16__USBH2_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 60 | #define MX51_PAD_EIM_D16__USBH2_DATA0 IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, NO_PAD_CTRL) |
| 815 | #define MX51_PAD_EIM_D17__AUD5_RXD (_MX51_PAD_EIM_D17__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 61 | #define MX51_PAD_EIM_D17__AUD5_RXD IOMUX_PAD(0x3f4, 0x060, 7, 0x8d4, 0, NO_PAD_CTRL) |
| 816 | #define MX51_PAD_EIM_D17__EIM_D17 (_MX51_PAD_EIM_D17__EIM_D17 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 62 | #define MX51_PAD_EIM_D17__EIM_D17 IOMUX_PAD(0x3f4, 0x060, 0, __NA_, 0, NO_PAD_CTRL) |
| 817 | #define MX51_PAD_EIM_D17__GPIO2_1 (_MX51_PAD_EIM_D17__GPIO2_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 63 | #define MX51_PAD_EIM_D17__GPIO2_1 IOMUX_PAD(0x3f4, 0x060, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 818 | #define MX51_PAD_EIM_D17__UART2_RXD (_MX51_PAD_EIM_D17__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 64 | #define MX51_PAD_EIM_D17__UART2_RXD IOMUX_PAD(0x3f4, 0x060, 3, 0x9ec, 0, MX51_UART_PAD_CTRL) |
| 819 | #define MX51_PAD_EIM_D17__UART3_CTS (_MX51_PAD_EIM_D17__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 65 | #define MX51_PAD_EIM_D17__UART3_CTS IOMUX_PAD(0x3f4, 0x060, 4, __NA_, 0, MX51_UART_PAD_CTRL) |
| 820 | #define MX51_PAD_EIM_D17__USBH2_DATA1 (_MX51_PAD_EIM_D17__USBH2_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 66 | #define MX51_PAD_EIM_D17__USBH2_DATA1 IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, NO_PAD_CTRL) |
| 821 | #define MX51_PAD_EIM_D18__AUD5_TXC (_MX51_PAD_EIM_D18__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 67 | #define MX51_PAD_EIM_D18__AUD5_TXC IOMUX_PAD(0x3f8, 0x064, 7, 0x8e4, 0, NO_PAD_CTRL) |
| 822 | #define MX51_PAD_EIM_D18__EIM_D18 (_MX51_PAD_EIM_D18__EIM_D18 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 68 | #define MX51_PAD_EIM_D18__EIM_D18 IOMUX_PAD(0x3f8, 0x064, 0, __NA_, 0, NO_PAD_CTRL) |
| 823 | #define MX51_PAD_EIM_D18__GPIO2_2 (_MX51_PAD_EIM_D18__GPIO2_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 69 | #define MX51_PAD_EIM_D18__GPIO2_2 IOMUX_PAD(0x3f8, 0x064, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 824 | #define MX51_PAD_EIM_D18__UART2_TXD (_MX51_PAD_EIM_D18__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 70 | #define MX51_PAD_EIM_D18__UART2_TXD IOMUX_PAD(0x3f8, 0x064, 3, __NA_, 0, MX51_UART_PAD_CTRL) |
| 825 | #define MX51_PAD_EIM_D18__UART3_RTS (_MX51_PAD_EIM_D18__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 71 | #define MX51_PAD_EIM_D18__UART3_RTS IOMUX_PAD(0x3f8, 0x064, 4, 0x9f0, 1, MX51_UART_PAD_CTRL) |
| 826 | #define MX51_PAD_EIM_D18__USBH2_DATA2 (_MX51_PAD_EIM_D18__USBH2_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 72 | #define MX51_PAD_EIM_D18__USBH2_DATA2 IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, NO_PAD_CTRL) |
| 827 | #define MX51_PAD_EIM_D19__AUD4_RXC (_MX51_PAD_EIM_D19__AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 73 | #define MX51_PAD_EIM_D19__AUD4_RXC IOMUX_PAD(0x3fc, 0x068, 5, __NA_, 0, NO_PAD_CTRL) |
| 828 | #define MX51_PAD_EIM_D19__AUD5_TXFS (_MX51_PAD_EIM_D19__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 74 | #define MX51_PAD_EIM_D19__AUD5_TXFS IOMUX_PAD(0x3fc, 0x068, 7, 0x8e8, 0, NO_PAD_CTRL) |
| 829 | #define MX51_PAD_EIM_D19__EIM_D19 (_MX51_PAD_EIM_D19__EIM_D19 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 75 | #define MX51_PAD_EIM_D19__EIM_D19 IOMUX_PAD(0x3fc, 0x068, 0, __NA_, 0, NO_PAD_CTRL) |
| 830 | #define MX51_PAD_EIM_D19__GPIO2_3 (_MX51_PAD_EIM_D19__GPIO2_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 76 | #define MX51_PAD_EIM_D19__GPIO2_3 IOMUX_PAD(0x3fc, 0x068, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 831 | #define MX51_PAD_EIM_D19__I2C1_SCL (_MX51_PAD_EIM_D19__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | 77 | #define MX51_PAD_EIM_D19__I2C1_SCL IOMUX_PAD(0x3fc, 0x068, 0x14, 0x9b0, 0, MX51_I2C_PAD_CTRL) |
| 832 | #define MX51_PAD_EIM_D19__UART2_RTS (_MX51_PAD_EIM_D19__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 78 | #define MX51_PAD_EIM_D19__UART2_RTS IOMUX_PAD(0x3fc, 0x068, 3, 0x9e8, 1, MX51_UART_PAD_CTRL) |
| 833 | #define MX51_PAD_EIM_D19__USBH2_DATA3 (_MX51_PAD_EIM_D19__USBH2_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 79 | #define MX51_PAD_EIM_D19__USBH2_DATA3 IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, NO_PAD_CTRL) |
| 834 | #define MX51_PAD_EIM_D20__AUD4_TXD (_MX51_PAD_EIM_D20__AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 80 | #define MX51_PAD_EIM_D20__AUD4_TXD IOMUX_PAD(0x400, 0x06c, 5, 0x8c8, 0, NO_PAD_CTRL) |
| 835 | #define MX51_PAD_EIM_D20__EIM_D20 (_MX51_PAD_EIM_D20__EIM_D20 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 81 | #define MX51_PAD_EIM_D20__EIM_D20 IOMUX_PAD(0x400, 0x06c, 0, __NA_, 0, NO_PAD_CTRL) |
| 836 | #define MX51_PAD_EIM_D20__GPIO2_4 (_MX51_PAD_EIM_D20__GPIO2_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 82 | #define MX51_PAD_EIM_D20__GPIO2_4 IOMUX_PAD(0x400, 0x06c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 837 | #define MX51_PAD_EIM_D20__SRTC_ALARM_DEB (_MX51_PAD_EIM_D20__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) | 83 | #define MX51_PAD_EIM_D20__SRTC_ALARM_DEB IOMUX_PAD(0x400, 0x06c, 4, __NA_, 0, NO_PAD_CTRL) |
| 838 | #define MX51_PAD_EIM_D20__USBH2_DATA4 (_MX51_PAD_EIM_D20__USBH2_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 84 | #define MX51_PAD_EIM_D20__USBH2_DATA4 IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, NO_PAD_CTRL) |
| 839 | #define MX51_PAD_EIM_D21__AUD4_RXD (_MX51_PAD_EIM_D21__AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 85 | #define MX51_PAD_EIM_D21__AUD4_RXD IOMUX_PAD(0x404, 0x070, 5, 0x8c4, 0, NO_PAD_CTRL) |
| 840 | #define MX51_PAD_EIM_D21__EIM_D21 (_MX51_PAD_EIM_D21__EIM_D21 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 86 | #define MX51_PAD_EIM_D21__EIM_D21 IOMUX_PAD(0x404, 0x070, 0, __NA_, 0, NO_PAD_CTRL) |
| 841 | #define MX51_PAD_EIM_D21__GPIO2_5 (_MX51_PAD_EIM_D21__GPIO2_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 87 | #define MX51_PAD_EIM_D21__GPIO2_5 IOMUX_PAD(0x404, 0x070, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 842 | #define MX51_PAD_EIM_D21__SRTC_ALARM_DEB (_MX51_PAD_EIM_D21__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) | 88 | #define MX51_PAD_EIM_D21__SRTC_ALARM_DEB IOMUX_PAD(0x404, 0x070, 3, __NA_, 0, NO_PAD_CTRL) |
| 843 | #define MX51_PAD_EIM_D21__USBH2_DATA5 (_MX51_PAD_EIM_D21__USBH2_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 89 | #define MX51_PAD_EIM_D21__USBH2_DATA5 IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, NO_PAD_CTRL) |
| 844 | #define MX51_PAD_EIM_D22__AUD4_TXC (_MX51_PAD_EIM_D22__AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 90 | #define MX51_PAD_EIM_D22__AUD4_TXC IOMUX_PAD(0x408, 0x074, 5, 0x8cc, 0, NO_PAD_CTRL) |
| 845 | #define MX51_PAD_EIM_D22__EIM_D22 (_MX51_PAD_EIM_D22__EIM_D22 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 91 | #define MX51_PAD_EIM_D22__EIM_D22 IOMUX_PAD(0x408, 0x074, 0, __NA_, 0, NO_PAD_CTRL) |
| 846 | #define MX51_PAD_EIM_D22__GPIO2_6 (_MX51_PAD_EIM_D22__GPIO2_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 92 | #define MX51_PAD_EIM_D22__GPIO2_6 IOMUX_PAD(0x408, 0x074, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 847 | #define MX51_PAD_EIM_D22__USBH2_DATA6 (_MX51_PAD_EIM_D22__USBH2_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 93 | #define MX51_PAD_EIM_D22__USBH2_DATA6 IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, NO_PAD_CTRL) |
| 848 | #define MX51_PAD_EIM_D23__AUD4_TXFS (_MX51_PAD_EIM_D23__AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 94 | #define MX51_PAD_EIM_D23__AUD4_TXFS IOMUX_PAD(0x40c, 0x078, 5, 0x8d0, 0, NO_PAD_CTRL) |
| 849 | #define MX51_PAD_EIM_D23__EIM_D23 (_MX51_PAD_EIM_D23__EIM_D23 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 95 | #define MX51_PAD_EIM_D23__EIM_D23 IOMUX_PAD(0x40c, 0x078, 0, __NA_, 0, NO_PAD_CTRL) |
| 850 | #define MX51_PAD_EIM_D23__GPIO2_7 (_MX51_PAD_EIM_D23__GPIO2_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 96 | #define MX51_PAD_EIM_D23__GPIO2_7 IOMUX_PAD(0x40c, 0x078, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 851 | #define MX51_PAD_EIM_D23__SPDIF_OUT1 (_MX51_PAD_EIM_D23__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 97 | #define MX51_PAD_EIM_D23__SPDIF_OUT1 IOMUX_PAD(0x40c, 0x078, 4, __NA_, 0, NO_PAD_CTRL) |
| 852 | #define MX51_PAD_EIM_D23__USBH2_DATA7 (_MX51_PAD_EIM_D23__USBH2_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 98 | #define MX51_PAD_EIM_D23__USBH2_DATA7 IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, NO_PAD_CTRL) |
| 853 | #define MX51_PAD_EIM_D24__AUD6_RXFS (_MX51_PAD_EIM_D24__AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 99 | #define MX51_PAD_EIM_D24__AUD6_RXFS IOMUX_PAD(0x410, 0x07c, 5, 0x8f8, 0, NO_PAD_CTRL) |
| 854 | #define MX51_PAD_EIM_D24__EIM_D24 (_MX51_PAD_EIM_D24__EIM_D24 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 100 | #define MX51_PAD_EIM_D24__EIM_D24 IOMUX_PAD(0x410, 0x07c, 0, __NA_, 0, NO_PAD_CTRL) |
| 855 | #define MX51_PAD_EIM_D24__GPIO2_8 (_MX51_PAD_EIM_D24__GPIO2_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 101 | #define MX51_PAD_EIM_D24__GPIO2_8 IOMUX_PAD(0x410, 0x07c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 856 | #define MX51_PAD_EIM_D24__I2C2_SDA (_MX51_PAD_EIM_D24__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | 102 | #define MX51_PAD_EIM_D24__I2C2_SDA IOMUX_PAD(0x410, 0x07c, 0x14, 0x9bc, 0, MX51_I2C_PAD_CTRL) |
| 857 | #define MX51_PAD_EIM_D24__UART3_CTS (_MX51_PAD_EIM_D24__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 103 | #define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, 3, __NA_, 0, MX51_UART_PAD_CTRL) |
| 858 | #define MX51_PAD_EIM_D24__USBOTG_DATA0 (_MX51_PAD_EIM_D24__USBOTG_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 104 | #define MX51_PAD_EIM_D24__USBOTG_DATA0 IOMUX_PAD(0x410, 0x07c, 2, __NA_, 0, NO_PAD_CTRL) |
| 859 | #define MX51_PAD_EIM_D25__EIM_D25 (_MX51_PAD_EIM_D25__EIM_D25 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 105 | #define MX51_PAD_EIM_D25__EIM_D25 IOMUX_PAD(0x414, 0x080, 0, __NA_, 0, NO_PAD_CTRL) |
| 860 | #define MX51_PAD_EIM_D25__KEY_COL6 (_MX51_PAD_EIM_D25__KEY_COL6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 106 | #define MX51_PAD_EIM_D25__KEY_COL6 IOMUX_PAD(0x414, 0x080, 1, 0x9c8, 0, NO_PAD_CTRL) |
| 861 | #define MX51_PAD_EIM_D25__UART2_CTS (_MX51_PAD_EIM_D25__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 107 | #define MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL) |
| 862 | #define MX51_PAD_EIM_D25__UART3_RXD (_MX51_PAD_EIM_D25__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 108 | #define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL) |
| 863 | #define MX51_PAD_EIM_D25__USBOTG_DATA1 (_MX51_PAD_EIM_D25__USBOTG_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 109 | #define MX51_PAD_EIM_D25__USBOTG_DATA1 IOMUX_PAD(0x414, 0x080, 2, __NA_, 0, NO_PAD_CTRL) |
| 864 | #define MX51_PAD_EIM_D26__EIM_D26 (_MX51_PAD_EIM_D26__EIM_D26 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 110 | #define MX51_PAD_EIM_D26__EIM_D26 IOMUX_PAD(0x418, 0x084, 0, __NA_, 0, NO_PAD_CTRL) |
| 865 | #define MX51_PAD_EIM_D26__KEY_COL7 (_MX51_PAD_EIM_D26__KEY_COL7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 111 | #define MX51_PAD_EIM_D26__KEY_COL7 IOMUX_PAD(0x418, 0x084, 1, 0x9cc, 0, NO_PAD_CTRL) |
| 866 | #define MX51_PAD_EIM_D26__UART2_RTS (_MX51_PAD_EIM_D26__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 112 | #define MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL) |
| 867 | #define MX51_PAD_EIM_D26__UART3_TXD (_MX51_PAD_EIM_D26__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 113 | #define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL) |
| 868 | #define MX51_PAD_EIM_D26__USBOTG_DATA2 (_MX51_PAD_EIM_D26__USBOTG_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 114 | #define MX51_PAD_EIM_D26__USBOTG_DATA2 IOMUX_PAD(0x418, 0x084, 2, __NA_, 0, NO_PAD_CTRL) |
| 869 | #define MX51_PAD_EIM_D27__AUD6_RXC (_MX51_PAD_EIM_D27__AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 115 | #define MX51_PAD_EIM_D27__AUD6_RXC IOMUX_PAD(0x41c, 0x088, 5, 0x8f4, 0, NO_PAD_CTRL) |
| 870 | #define MX51_PAD_EIM_D27__EIM_D27 (_MX51_PAD_EIM_D27__EIM_D27 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 116 | #define MX51_PAD_EIM_D27__EIM_D27 IOMUX_PAD(0x41c, 0x088, 0, __NA_, 0, NO_PAD_CTRL) |
| 871 | #define MX51_PAD_EIM_D27__GPIO2_9 (_MX51_PAD_EIM_D27__GPIO2_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 117 | #define MX51_PAD_EIM_D27__GPIO2_9 IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 872 | #define MX51_PAD_EIM_D27__I2C2_SCL (_MX51_PAD_EIM_D27__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | 118 | #define MX51_PAD_EIM_D27__I2C2_SCL IOMUX_PAD(0x41c, 0x088, 0x14, 0x9b8, 0, MX51_I2C_PAD_CTRL) |
| 873 | #define MX51_PAD_EIM_D27__UART3_RTS (_MX51_PAD_EIM_D27__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 119 | #define MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART_PAD_CTRL) |
| 874 | #define MX51_PAD_EIM_D27__USBOTG_DATA3 (_MX51_PAD_EIM_D27__USBOTG_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 120 | #define MX51_PAD_EIM_D27__USBOTG_DATA3 IOMUX_PAD(0x41c, 0x088, 2, __NA_, 0, NO_PAD_CTRL) |
| 875 | #define MX51_PAD_EIM_D28__AUD6_TXD (_MX51_PAD_EIM_D28__AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 121 | #define MX51_PAD_EIM_D28__AUD6_TXD IOMUX_PAD(0x420, 0x08c, 5, 0x8f0, 0, NO_PAD_CTRL) |
| 876 | #define MX51_PAD_EIM_D28__EIM_D28 (_MX51_PAD_EIM_D28__EIM_D28 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 122 | #define MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x08c, 0, __NA_, 0, NO_PAD_CTRL) |
| 877 | #define MX51_PAD_EIM_D28__KEY_ROW4 (_MX51_PAD_EIM_D28__KEY_ROW4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 123 | #define MX51_PAD_EIM_D28__KEY_ROW4 IOMUX_PAD(0x420, 0x08c, 1, 0x9d0, 0, NO_PAD_CTRL) |
| 878 | #define MX51_PAD_EIM_D28__USBOTG_DATA4 (_MX51_PAD_EIM_D28__USBOTG_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 124 | #define MX51_PAD_EIM_D28__USBOTG_DATA4 IOMUX_PAD(0x420, 0x08c, 2, __NA_, 0, NO_PAD_CTRL) |
| 879 | #define MX51_PAD_EIM_D29__AUD6_RXD (_MX51_PAD_EIM_D29__AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 125 | #define MX51_PAD_EIM_D29__AUD6_RXD IOMUX_PAD(0x424, 0x090, 5, 0x8ec, 0, NO_PAD_CTRL) |
| 880 | #define MX51_PAD_EIM_D29__EIM_D29 (_MX51_PAD_EIM_D29__EIM_D29 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 126 | #define MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x090, 0, __NA_, 0, NO_PAD_CTRL) |
| 881 | #define MX51_PAD_EIM_D29__KEY_ROW5 (_MX51_PAD_EIM_D29__KEY_ROW5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 127 | #define MX51_PAD_EIM_D29__KEY_ROW5 IOMUX_PAD(0x424, 0x090, 1, 0x9d4, 0, NO_PAD_CTRL) |
| 882 | #define MX51_PAD_EIM_D29__USBOTG_DATA5 (_MX51_PAD_EIM_D29__USBOTG_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 128 | #define MX51_PAD_EIM_D29__USBOTG_DATA5 IOMUX_PAD(0x424, 0x090, 2, __NA_, 0, NO_PAD_CTRL) |
| 883 | #define MX51_PAD_EIM_D30__AUD6_TXC (_MX51_PAD_EIM_D30__AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 129 | #define MX51_PAD_EIM_D30__AUD6_TXC IOMUX_PAD(0x428, 0x094, 5, 0x8fc, 0, NO_PAD_CTRL) |
| 884 | #define MX51_PAD_EIM_D30__EIM_D30 (_MX51_PAD_EIM_D30__EIM_D30 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 130 | #define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x094, 0, __NA_, 0, NO_PAD_CTRL) |
| 885 | #define MX51_PAD_EIM_D30__KEY_ROW6 (_MX51_PAD_EIM_D30__KEY_ROW6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 131 | #define MX51_PAD_EIM_D30__KEY_ROW6 IOMUX_PAD(0x428, 0x094, 1, 0x9d8, 0, NO_PAD_CTRL) |
| 886 | #define MX51_PAD_EIM_D30__USBOTG_DATA6 (_MX51_PAD_EIM_D30__USBOTG_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 132 | #define MX51_PAD_EIM_D30__USBOTG_DATA6 IOMUX_PAD(0x428, 0x094, 2, __NA_, 0, NO_PAD_CTRL) |
| 887 | #define MX51_PAD_EIM_D31__AUD6_TXFS (_MX51_PAD_EIM_D31__AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 133 | #define MX51_PAD_EIM_D31__AUD6_TXFS IOMUX_PAD(0x42c, 0x098, 5, 0x900, 0, NO_PAD_CTRL) |
| 888 | #define MX51_PAD_EIM_D31__EIM_D31 (_MX51_PAD_EIM_D31__EIM_D31 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 134 | #define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x098, 0, __NA_, 0, NO_PAD_CTRL) |
| 889 | #define MX51_PAD_EIM_D31__KEY_ROW7 (_MX51_PAD_EIM_D31__KEY_ROW7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 135 | #define MX51_PAD_EIM_D31__KEY_ROW7 IOMUX_PAD(0x42c, 0x098, 1, 0x9dc, 0, NO_PAD_CTRL) |
| 890 | #define MX51_PAD_EIM_D31__USBOTG_DATA7 (_MX51_PAD_EIM_D31__USBOTG_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 136 | #define MX51_PAD_EIM_D31__USBOTG_DATA7 IOMUX_PAD(0x42c, 0x098, 2, __NA_, 0, NO_PAD_CTRL) |
| 891 | #define MX51_PAD_EIM_A16__EIM_A16 (_MX51_PAD_EIM_A16__EIM_A16 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 137 | #define MX51_PAD_EIM_A16__EIM_A16 IOMUX_PAD(0x430, 0x09c, 0, __NA_, 0, NO_PAD_CTRL) |
| 892 | #define MX51_PAD_EIM_A16__GPIO2_10 (_MX51_PAD_EIM_A16__GPIO2_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 138 | #define MX51_PAD_EIM_A16__GPIO2_10 IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 893 | #define MX51_PAD_EIM_A16__OSC_FREQ_SEL0 (_MX51_PAD_EIM_A16__OSC_FREQ_SEL0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 139 | #define MX51_PAD_EIM_A16__OSC_FREQ_SEL0 IOMUX_PAD(0x430, 0x09c, 7, __NA_, 0, NO_PAD_CTRL) |
| 894 | #define MX51_PAD_EIM_A17__EIM_A17 (_MX51_PAD_EIM_A17__EIM_A17 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 140 | #define MX51_PAD_EIM_A17__EIM_A17 IOMUX_PAD(0x434, 0x0a0, 0, __NA_, 0, NO_PAD_CTRL) |
| 895 | #define MX51_PAD_EIM_A17__GPIO2_11 (_MX51_PAD_EIM_A17__GPIO2_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 141 | #define MX51_PAD_EIM_A17__GPIO2_11 IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 896 | #define MX51_PAD_EIM_A17__OSC_FREQ_SEL1 (_MX51_PAD_EIM_A17__OSC_FREQ_SEL1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 142 | #define MX51_PAD_EIM_A17__OSC_FREQ_SEL1 IOMUX_PAD(0x434, 0x0a0, 7, __NA_, 0, NO_PAD_CTRL) |
| 897 | #define MX51_PAD_EIM_A18__BOOT_LPB0 (_MX51_PAD_EIM_A18__BOOT_LPB0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 143 | #define MX51_PAD_EIM_A18__BOOT_LPB0 IOMUX_PAD(0x438, 0x0a4, 7, __NA_, 0, NO_PAD_CTRL) |
| 898 | #define MX51_PAD_EIM_A18__EIM_A18 (_MX51_PAD_EIM_A18__EIM_A18 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 144 | #define MX51_PAD_EIM_A18__EIM_A18 IOMUX_PAD(0x438, 0x0a4, 0, __NA_, 0, NO_PAD_CTRL) |
| 899 | #define MX51_PAD_EIM_A18__GPIO2_12 (_MX51_PAD_EIM_A18__GPIO2_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 145 | #define MX51_PAD_EIM_A18__GPIO2_12 IOMUX_PAD(0x438, 0x0a4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 900 | #define MX51_PAD_EIM_A19__BOOT_LPB1 (_MX51_PAD_EIM_A19__BOOT_LPB1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 146 | #define MX51_PAD_EIM_A19__BOOT_LPB1 IOMUX_PAD(0x43c, 0x0a8, 7, __NA_, 0, NO_PAD_CTRL) |
| 901 | #define MX51_PAD_EIM_A19__EIM_A19 (_MX51_PAD_EIM_A19__EIM_A19 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 147 | #define MX51_PAD_EIM_A19__EIM_A19 IOMUX_PAD(0x43c, 0x0a8, 0, __NA_, 0, NO_PAD_CTRL) |
| 902 | #define MX51_PAD_EIM_A19__GPIO2_13 (_MX51_PAD_EIM_A19__GPIO2_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 148 | #define MX51_PAD_EIM_A19__GPIO2_13 IOMUX_PAD(0x43c, 0x0a8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 903 | #define MX51_PAD_EIM_A20__BOOT_UART_SRC0 (_MX51_PAD_EIM_A20__BOOT_UART_SRC0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 149 | #define MX51_PAD_EIM_A20__BOOT_UART_SRC0 IOMUX_PAD(0x440, 0x0ac, 7, __NA_, 0, NO_PAD_CTRL) |
| 904 | #define MX51_PAD_EIM_A20__EIM_A20 (_MX51_PAD_EIM_A20__EIM_A20 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 150 | #define MX51_PAD_EIM_A20__EIM_A20 IOMUX_PAD(0x440, 0x0ac, 0, __NA_, 0, NO_PAD_CTRL) |
| 905 | #define MX51_PAD_EIM_A20__GPIO2_14 (_MX51_PAD_EIM_A20__GPIO2_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 151 | #define MX51_PAD_EIM_A20__GPIO2_14 IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 906 | #define MX51_PAD_EIM_A21__BOOT_UART_SRC1 (_MX51_PAD_EIM_A21__BOOT_UART_SRC1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 152 | #define MX51_PAD_EIM_A21__BOOT_UART_SRC1 IOMUX_PAD(0x444, 0x0b0, 7, __NA_, 0, NO_PAD_CTRL) |
| 907 | #define MX51_PAD_EIM_A21__EIM_A21 (_MX51_PAD_EIM_A21__EIM_A21 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 153 | #define MX51_PAD_EIM_A21__EIM_A21 IOMUX_PAD(0x444, 0x0b0, 0, __NA_, 0, NO_PAD_CTRL) |
| 908 | #define MX51_PAD_EIM_A21__GPIO2_15 (_MX51_PAD_EIM_A21__GPIO2_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 154 | #define MX51_PAD_EIM_A21__GPIO2_15 IOMUX_PAD(0x444, 0x0b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 909 | #define MX51_PAD_EIM_A22__EIM_A22 (_MX51_PAD_EIM_A22__EIM_A22 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 155 | #define MX51_PAD_EIM_A22__EIM_A22 IOMUX_PAD(0x448, 0x0b4, 0, __NA_, 0, NO_PAD_CTRL) |
| 910 | #define MX51_PAD_EIM_A22__GPIO2_16 (_MX51_PAD_EIM_A22__GPIO2_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 156 | #define MX51_PAD_EIM_A22__GPIO2_16 IOMUX_PAD(0x448, 0x0b4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 911 | #define MX51_PAD_EIM_A23__BOOT_HPN_EN (_MX51_PAD_EIM_A23__BOOT_HPN_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) | 157 | #define MX51_PAD_EIM_A23__BOOT_HPN_EN IOMUX_PAD(0x44c, 0x0b8, 7, __NA_, 0, NO_PAD_CTRL) |
| 912 | #define MX51_PAD_EIM_A23__EIM_A23 (_MX51_PAD_EIM_A23__EIM_A23 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 158 | #define MX51_PAD_EIM_A23__EIM_A23 IOMUX_PAD(0x44c, 0x0b8, 0, __NA_, 0, NO_PAD_CTRL) |
| 913 | #define MX51_PAD_EIM_A23__GPIO2_17 (_MX51_PAD_EIM_A23__GPIO2_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 159 | #define MX51_PAD_EIM_A23__GPIO2_17 IOMUX_PAD(0x44c, 0x0b8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 914 | #define MX51_PAD_EIM_A24__EIM_A24 (_MX51_PAD_EIM_A24__EIM_A24 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 160 | #define MX51_PAD_EIM_A24__EIM_A24 IOMUX_PAD(0x450, 0x0bc, 0, __NA_, 0, NO_PAD_CTRL) |
| 915 | #define MX51_PAD_EIM_A24__GPIO2_18 (_MX51_PAD_EIM_A24__GPIO2_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 161 | #define MX51_PAD_EIM_A24__GPIO2_18 IOMUX_PAD(0x450, 0x0bc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 916 | #define MX51_PAD_EIM_A24__USBH2_CLK (_MX51_PAD_EIM_A24__USBH2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 162 | #define MX51_PAD_EIM_A24__USBH2_CLK IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, NO_PAD_CTRL) |
| 917 | #define MX51_PAD_EIM_A25__DISP1_PIN4 (_MX51_PAD_EIM_A25__DISP1_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 163 | #define MX51_PAD_EIM_A25__DISP1_PIN4 IOMUX_PAD(0x454, 0x0c0, 6, __NA_, 0, NO_PAD_CTRL) |
| 918 | #define MX51_PAD_EIM_A25__EIM_A25 (_MX51_PAD_EIM_A25__EIM_A25 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 164 | #define MX51_PAD_EIM_A25__EIM_A25 IOMUX_PAD(0x454, 0x0c0, 0, __NA_, 0, NO_PAD_CTRL) |
| 919 | #define MX51_PAD_EIM_A25__GPIO2_19 (_MX51_PAD_EIM_A25__GPIO2_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 165 | #define MX51_PAD_EIM_A25__GPIO2_19 IOMUX_PAD(0x454, 0x0c0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 920 | #define MX51_PAD_EIM_A25__USBH2_DIR (_MX51_PAD_EIM_A25__USBH2_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) | 166 | #define MX51_PAD_EIM_A25__USBH2_DIR IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, NO_PAD_CTRL) |
| 921 | #define MX51_PAD_EIM_A26__CSI1_DATA_EN (_MX51_PAD_EIM_A26__CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) | 167 | #define MX51_PAD_EIM_A26__CSI1_DATA_EN IOMUX_PAD(0x458, 0x0c4, 5, 0x9a0, 0, NO_PAD_CTRL) |
| 922 | #define MX51_PAD_EIM_A26__DISP2_EXT_CLK (_MX51_PAD_EIM_A26__DISP2_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 168 | #define MX51_PAD_EIM_A26__DISP2_EXT_CLK IOMUX_PAD(0x458, 0x0c4, 6, 0x908, 0, NO_PAD_CTRL) |
| 923 | #define MX51_PAD_EIM_A26__EIM_A26 (_MX51_PAD_EIM_A26__EIM_A26 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 169 | #define MX51_PAD_EIM_A26__EIM_A26 IOMUX_PAD(0x458, 0x0c4, 0, __NA_, 0, NO_PAD_CTRL) |
| 924 | #define MX51_PAD_EIM_A26__GPIO2_20 (_MX51_PAD_EIM_A26__GPIO2_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 170 | #define MX51_PAD_EIM_A26__GPIO2_20 IOMUX_PAD(0x458, 0x0c4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 925 | #define MX51_PAD_EIM_A26__USBH2_STP (_MX51_PAD_EIM_A26__USBH2_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) | 171 | #define MX51_PAD_EIM_A26__USBH2_STP IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, NO_PAD_CTRL) |
| 926 | #define MX51_PAD_EIM_A27__CSI2_DATA_EN (_MX51_PAD_EIM_A27__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) | 172 | #define MX51_PAD_EIM_A27__CSI2_DATA_EN IOMUX_PAD(0x45c, 0x0c8, 5, 0x99c, 0, NO_PAD_CTRL) |
| 927 | #define MX51_PAD_EIM_A27__DISP1_PIN1 (_MX51_PAD_EIM_A27__DISP1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 173 | #define MX51_PAD_EIM_A27__DISP1_PIN1 IOMUX_PAD(0x45c, 0x0c8, 6, 0x9a4, 0, NO_PAD_CTRL) |
| 928 | #define MX51_PAD_EIM_A27__EIM_A27 (_MX51_PAD_EIM_A27__EIM_A27 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 174 | #define MX51_PAD_EIM_A27__EIM_A27 IOMUX_PAD(0x45c, 0x0c8, 0, __NA_, 0, NO_PAD_CTRL) |
| 929 | #define MX51_PAD_EIM_A27__GPIO2_21 (_MX51_PAD_EIM_A27__GPIO2_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 175 | #define MX51_PAD_EIM_A27__GPIO2_21 IOMUX_PAD(0x45c, 0x0c8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 930 | #define MX51_PAD_EIM_A27__USBH2_NXT (_MX51_PAD_EIM_A27__USBH2_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) | 176 | #define MX51_PAD_EIM_A27__USBH2_NXT IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, NO_PAD_CTRL) |
| 931 | #define MX51_PAD_EIM_EB0__EIM_EB0 (_MX51_PAD_EIM_EB0__EIM_EB0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 177 | #define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, __NA_, 0, NO_PAD_CTRL) |
| 932 | #define MX51_PAD_EIM_EB1__EIM_EB1 (_MX51_PAD_EIM_EB1__EIM_EB1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 178 | #define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, __NA_, 0, NO_PAD_CTRL) |
| 933 | #define MX51_PAD_EIM_EB2__AUD5_RXFS (_MX51_PAD_EIM_EB2__AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 179 | #define MX51_PAD_EIM_EB2__AUD5_RXFS IOMUX_PAD(0x468, 0x0d4, 6, 0x8e0, 0, NO_PAD_CTRL) |
| 934 | #define MX51_PAD_EIM_EB2__CSI1_D2 (_MX51_PAD_EIM_EB2__CSI1_D2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 180 | #define MX51_PAD_EIM_EB2__CSI1_D2 IOMUX_PAD(0x468, 0x0d4, 5, __NA_, 0, NO_PAD_CTRL) |
| 935 | #define MX51_PAD_EIM_EB2__EIM_EB2 (_MX51_PAD_EIM_EB2__EIM_EB2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 181 | #define MX51_PAD_EIM_EB2__EIM_EB2 IOMUX_PAD(0x468, 0x0d4, 0, __NA_, 0, NO_PAD_CTRL) |
| 936 | #define MX51_PAD_EIM_EB2__FEC_MDIO (_MX51_PAD_EIM_EB2__FEC_MDIO | \ | 182 | #define MX51_PAD_EIM_EB2__FEC_MDIO (IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, 0) | \ |
| 937 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | PAD_CTL_PKE | PAD_CTL_SRE_FAST | \ | 183 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | PAD_CTL_PKE | PAD_CTL_SRE_FAST | \ |
| 938 | PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS)) | 184 | PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS)) |
| 939 | #define MX51_PAD_EIM_EB2__GPIO2_22 (_MX51_PAD_EIM_EB2__GPIO2_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 185 | #define MX51_PAD_EIM_EB2__GPIO2_22 IOMUX_PAD(0x468, 0x0d4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 940 | #define MX51_PAD_EIM_EB2__GPT_CMPOUT1 (_MX51_PAD_EIM_EB2__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 186 | #define MX51_PAD_EIM_EB2__GPT_CMPOUT1 IOMUX_PAD(0x468, 0x0d4, 7, __NA_, 0, NO_PAD_CTRL) |
| 941 | #define MX51_PAD_EIM_EB3__AUD5_RXC (_MX51_PAD_EIM_EB3__AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 187 | #define MX51_PAD_EIM_EB3__AUD5_RXC IOMUX_PAD(0x46c, 0x0d8, 6, 0x8dc, 0, NO_PAD_CTRL) |
| 942 | #define MX51_PAD_EIM_EB3__CSI1_D3 (_MX51_PAD_EIM_EB3__CSI1_D3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 188 | #define MX51_PAD_EIM_EB3__CSI1_D3 IOMUX_PAD(0x46c, 0x0d8, 5, __NA_, 0, NO_PAD_CTRL) |
| 943 | #define MX51_PAD_EIM_EB3__EIM_EB3 (_MX51_PAD_EIM_EB3__EIM_EB3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 189 | #define MX51_PAD_EIM_EB3__EIM_EB3 IOMUX_PAD(0x46c, 0x0d8, 0, __NA_, 0, NO_PAD_CTRL) |
| 944 | #define MX51_PAD_EIM_EB3__FEC_RDATA1 (_MX51_PAD_EIM_EB3__FEC_RDATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 190 | #define MX51_PAD_EIM_EB3__FEC_RDATA1 IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL) |
| 945 | #define MX51_PAD_EIM_EB3__GPIO2_23 (_MX51_PAD_EIM_EB3__GPIO2_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 191 | #define MX51_PAD_EIM_EB3__GPIO2_23 IOMUX_PAD(0x46c, 0x0d8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 946 | #define MX51_PAD_EIM_EB3__GPT_CMPOUT2 (_MX51_PAD_EIM_EB3__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 192 | #define MX51_PAD_EIM_EB3__GPT_CMPOUT2 IOMUX_PAD(0x46c, 0x0d8, 7, __NA_, 0, NO_PAD_CTRL) |
| 947 | #define MX51_PAD_EIM_OE__EIM_OE (_MX51_PAD_EIM_OE__EIM_OE | MUX_PAD_CTRL(NO_PAD_CTRL)) | 193 | #define MX51_PAD_EIM_OE__EIM_OE IOMUX_PAD(0x470, 0x0dc, 0, __NA_, 0, NO_PAD_CTRL) |
| 948 | #define MX51_PAD_EIM_OE__GPIO2_24 (_MX51_PAD_EIM_OE__GPIO2_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 194 | #define MX51_PAD_EIM_OE__GPIO2_24 IOMUX_PAD(0x470, 0x0dc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 949 | #define MX51_PAD_EIM_CS0__EIM_CS0 (_MX51_PAD_EIM_CS0__EIM_CS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 195 | #define MX51_PAD_EIM_CS0__EIM_CS0 IOMUX_PAD(0x474, 0x0e0, 0, __NA_, 0, NO_PAD_CTRL) |
| 950 | #define MX51_PAD_EIM_CS0__GPIO2_25 (_MX51_PAD_EIM_CS0__GPIO2_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 196 | #define MX51_PAD_EIM_CS0__GPIO2_25 IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 951 | #define MX51_PAD_EIM_CS1__EIM_CS1 (_MX51_PAD_EIM_CS1__EIM_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 197 | #define MX51_PAD_EIM_CS1__EIM_CS1 IOMUX_PAD(0x478, 0x0e4, 0, __NA_, 0, NO_PAD_CTRL) |
| 952 | #define MX51_PAD_EIM_CS1__GPIO2_26 (_MX51_PAD_EIM_CS1__GPIO2_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 198 | #define MX51_PAD_EIM_CS1__GPIO2_26 IOMUX_PAD(0x478, 0x0e4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 953 | #define MX51_PAD_EIM_CS2__AUD5_TXD (_MX51_PAD_EIM_CS2__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 199 | #define MX51_PAD_EIM_CS2__AUD5_TXD IOMUX_PAD(0x47c, 0x0e8, 6, 0x8d8, 1, NO_PAD_CTRL) |
| 954 | #define MX51_PAD_EIM_CS2__CSI1_D4 (_MX51_PAD_EIM_CS2__CSI1_D4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 200 | #define MX51_PAD_EIM_CS2__CSI1_D4 IOMUX_PAD(0x47c, 0x0e8, 5, __NA_, 0, NO_PAD_CTRL) |
| 955 | #define MX51_PAD_EIM_CS2__EIM_CS2 (_MX51_PAD_EIM_CS2__EIM_CS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 201 | #define MX51_PAD_EIM_CS2__EIM_CS2 IOMUX_PAD(0x47c, 0x0e8, 0, __NA_, 0, NO_PAD_CTRL) |
| 956 | #define MX51_PAD_EIM_CS2__FEC_RDATA2 (_MX51_PAD_EIM_CS2__FEC_RDATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 202 | #define MX51_PAD_EIM_CS2__FEC_RDATA2 IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL) |
| 957 | #define MX51_PAD_EIM_CS2__GPIO2_27 (_MX51_PAD_EIM_CS2__GPIO2_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 203 | #define MX51_PAD_EIM_CS2__GPIO2_27 IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 958 | #define MX51_PAD_EIM_CS2__USBOTG_STP (_MX51_PAD_EIM_CS2__USBOTG_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) | 204 | #define MX51_PAD_EIM_CS2__USBOTG_STP IOMUX_PAD(0x47c, 0x0e8, 2, __NA_, 0, NO_PAD_CTRL) |
| 959 | #define MX51_PAD_EIM_CS3__AUD5_RXD (_MX51_PAD_EIM_CS3__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 205 | #define MX51_PAD_EIM_CS3__AUD5_RXD IOMUX_PAD(0x480, 0x0ec, 6, 0x8d4, 1, NO_PAD_CTRL) |
| 960 | #define MX51_PAD_EIM_CS3__CSI1_D5 (_MX51_PAD_EIM_CS3__CSI1_D5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 206 | #define MX51_PAD_EIM_CS3__CSI1_D5 IOMUX_PAD(0x480, 0x0ec, 5, __NA_, 0, NO_PAD_CTRL) |
| 961 | #define MX51_PAD_EIM_CS3__EIM_CS3 (_MX51_PAD_EIM_CS3__EIM_CS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 207 | #define MX51_PAD_EIM_CS3__EIM_CS3 IOMUX_PAD(0x480, 0x0ec, 0, __NA_, 0, NO_PAD_CTRL) |
| 962 | #define MX51_PAD_EIM_CS3__FEC_RDATA3 (_MX51_PAD_EIM_CS3__FEC_RDATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 208 | #define MX51_PAD_EIM_CS3__FEC_RDATA3 IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL) |
| 963 | #define MX51_PAD_EIM_CS3__GPIO2_28 (_MX51_PAD_EIM_CS3__GPIO2_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 209 | #define MX51_PAD_EIM_CS3__GPIO2_28 IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 964 | #define MX51_PAD_EIM_CS3__USBOTG_NXT (_MX51_PAD_EIM_CS3__USBOTG_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) | 210 | #define MX51_PAD_EIM_CS3__USBOTG_NXT IOMUX_PAD(0x480, 0x0ec, 2, __NA_, 0, NO_PAD_CTRL) |
| 965 | #define MX51_PAD_EIM_CS4__AUD5_TXC (_MX51_PAD_EIM_CS4__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 211 | #define MX51_PAD_EIM_CS4__AUD5_TXC IOMUX_PAD(0x484, 0x0f0, 6, 0x8e4, 1, NO_PAD_CTRL) |
| 966 | #define MX51_PAD_EIM_CS4__CSI1_D6 (_MX51_PAD_EIM_CS4__CSI1_D6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 212 | #define MX51_PAD_EIM_CS4__CSI1_D6 IOMUX_PAD(0x484, 0x0f0, 5, __NA_, 0, NO_PAD_CTRL) |
| 967 | #define MX51_PAD_EIM_CS4__EIM_CS4 (_MX51_PAD_EIM_CS4__EIM_CS4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 213 | #define MX51_PAD_EIM_CS4__EIM_CS4 IOMUX_PAD(0x484, 0x0f0, 0, __NA_, 0, NO_PAD_CTRL) |
| 968 | #define MX51_PAD_EIM_CS4__FEC_RX_ER (_MX51_PAD_EIM_CS4__FEC_RX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_2)) | 214 | #define MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2) |
| 969 | #define MX51_PAD_EIM_CS4__GPIO2_29 (_MX51_PAD_EIM_CS4__GPIO2_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 215 | #define MX51_PAD_EIM_CS4__GPIO2_29 IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 970 | #define MX51_PAD_EIM_CS4__USBOTG_CLK (_MX51_PAD_EIM_CS4__USBOTG_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 216 | #define MX51_PAD_EIM_CS4__USBOTG_CLK IOMUX_PAD(0x484, 0x0f0, 2, __NA_, 0, NO_PAD_CTRL) |
| 971 | #define MX51_PAD_EIM_CS5__AUD5_TXFS (_MX51_PAD_EIM_CS5__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 217 | #define MX51_PAD_EIM_CS5__AUD5_TXFS IOMUX_PAD(0x488, 0x0f4, 6, 0x8e8, 1, NO_PAD_CTRL) |
| 972 | #define MX51_PAD_EIM_CS5__CSI1_D7 (_MX51_PAD_EIM_CS5__CSI1_D7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 218 | #define MX51_PAD_EIM_CS5__CSI1_D7 IOMUX_PAD(0x488, 0x0f4, 5, __NA_, 0, NO_PAD_CTRL) |
| 973 | #define MX51_PAD_EIM_CS5__DISP1_EXT_CLK (_MX51_PAD_EIM_CS5__DISP1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 219 | #define MX51_PAD_EIM_CS5__DISP1_EXT_CLK IOMUX_PAD(0x488, 0x0f4, 4, 0x904, 0, NO_PAD_CTRL) |
| 974 | #define MX51_PAD_EIM_CS5__EIM_CS5 (_MX51_PAD_EIM_CS5__EIM_CS5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 220 | #define MX51_PAD_EIM_CS5__EIM_CS5 IOMUX_PAD(0x488, 0x0f4, 0, __NA_, 0, NO_PAD_CTRL) |
| 975 | #define MX51_PAD_EIM_CS5__FEC_CRS (_MX51_PAD_EIM_CS5__FEC_CRS | MUX_PAD_CTRL(MX51_PAD_CTRL_2)) | 221 | #define MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2) |
| 976 | #define MX51_PAD_EIM_CS5__GPIO2_30 (_MX51_PAD_EIM_CS5__GPIO2_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 222 | #define MX51_PAD_EIM_CS5__GPIO2_30 IOMUX_PAD(0x488, 0x0f4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 977 | #define MX51_PAD_EIM_CS5__USBOTG_DIR (_MX51_PAD_EIM_CS5__USBOTG_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) | 223 | #define MX51_PAD_EIM_CS5__USBOTG_DIR IOMUX_PAD(0x488, 0x0f4, 2, __NA_, 0, NO_PAD_CTRL) |
| 978 | #define MX51_PAD_EIM_DTACK__EIM_DTACK (_MX51_PAD_EIM_DTACK__EIM_DTACK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 224 | #define MX51_PAD_EIM_DTACK__EIM_DTACK IOMUX_PAD(0x48c, 0x0f8, 0, __NA_, 0, NO_PAD_CTRL) |
| 979 | #define MX51_PAD_EIM_DTACK__GPIO2_31 (_MX51_PAD_EIM_DTACK__GPIO2_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 225 | #define MX51_PAD_EIM_DTACK__GPIO2_31 IOMUX_PAD(0x48c, 0x0f8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 980 | #define MX51_PAD_EIM_LBA__EIM_LBA (_MX51_PAD_EIM_LBA__EIM_LBA | MUX_PAD_CTRL(NO_PAD_CTRL)) | 226 | #define MX51_PAD_EIM_LBA__EIM_LBA IOMUX_PAD(0x494, 0x0fc, 0, __NA_, 0, NO_PAD_CTRL) |
| 981 | #define MX51_PAD_EIM_LBA__GPIO3_1 (_MX51_PAD_EIM_LBA__GPIO3_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 227 | #define MX51_PAD_EIM_LBA__GPIO3_1 IOMUX_PAD(0x494, 0x0fc, 1, 0x978, 0, MX51_GPIO_PAD_CTRL) |
| 982 | #define MX51_PAD_EIM_CRE__EIM_CRE (_MX51_PAD_EIM_CRE__EIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL)) | 228 | #define MX51_PAD_EIM_CRE__EIM_CRE IOMUX_PAD(0x4a0, 0x100, 0, __NA_, 0, NO_PAD_CTRL) |
| 983 | #define MX51_PAD_EIM_CRE__GPIO3_2 (_MX51_PAD_EIM_CRE__GPIO3_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 229 | #define MX51_PAD_EIM_CRE__GPIO3_2 IOMUX_PAD(0x4a0, 0x100, 1, 0x97c, 0, MX51_GPIO_PAD_CTRL) |
| 984 | #define MX51_PAD_DRAM_CS1__DRAM_CS1 (_MX51_PAD_DRAM_CS1__DRAM_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 230 | #define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL) |
| 985 | #define MX51_PAD_NANDF_WE_B__GPIO3_3 (_MX51_PAD_NANDF_WE_B__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 231 | #define MX51_PAD_NANDF_WE_B__GPIO3_3 IOMUX_PAD(0x4e4, 0x108, 3, 0x980, 0, MX51_GPIO_PAD_CTRL) |
| 986 | #define MX51_PAD_NANDF_WE_B__NANDF_WE_B (_MX51_PAD_NANDF_WE_B__NANDF_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) | 232 | #define MX51_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL) |
| 987 | #define MX51_PAD_NANDF_WE_B__PATA_DIOW (_MX51_PAD_NANDF_WE_B__PATA_DIOW | MUX_PAD_CTRL(NO_PAD_CTRL)) | 233 | #define MX51_PAD_NANDF_WE_B__PATA_DIOW IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL) |
| 988 | #define MX51_PAD_NANDF_WE_B__SD3_DATA0 (_MX51_PAD_NANDF_WE_B__SD3_DATA0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) | 234 | #define MX51_PAD_NANDF_WE_B__SD3_DATA0 IOMUX_PAD(0x4e4, 0x108, 2, 0x93c, 0, MX51_SDHCI_PAD_CTRL) |
| 989 | #define MX51_PAD_NANDF_RE_B__GPIO3_4 (_MX51_PAD_NANDF_RE_B__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 235 | #define MX51_PAD_NANDF_RE_B__GPIO3_4 IOMUX_PAD(0x4e8, 0x10c, 3, 0x984, 0, MX51_GPIO_PAD_CTRL) |
| 990 | #define MX51_PAD_NANDF_RE_B__NANDF_RE_B (_MX51_PAD_NANDF_RE_B__NANDF_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) | 236 | #define MX51_PAD_NANDF_RE_B__NANDF_RE_B IOMUX_PAD(0x4e8, 0x10c, 0, __NA_, 0, NO_PAD_CTRL) |
| 991 | #define MX51_PAD_NANDF_RE_B__PATA_DIOR (_MX51_PAD_NANDF_RE_B__PATA_DIOR | MUX_PAD_CTRL(NO_PAD_CTRL)) | 237 | #define MX51_PAD_NANDF_RE_B__PATA_DIOR IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL) |
| 992 | #define MX51_PAD_NANDF_RE_B__SD3_DATA1 (_MX51_PAD_NANDF_RE_B__SD3_DATA1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) | 238 | #define MX51_PAD_NANDF_RE_B__SD3_DATA1 IOMUX_PAD(0x4e8, 0x10c, 2, 0x940, 0, MX51_SDHCI_PAD_CTRL) |
| 993 | #define MX51_PAD_NANDF_ALE__GPIO3_5 (_MX51_PAD_NANDF_ALE__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 239 | #define MX51_PAD_NANDF_ALE__GPIO3_5 IOMUX_PAD(0x4ec, 0x110, 3, 0x988, 0, MX51_GPIO_PAD_CTRL) |
| 994 | #define MX51_PAD_NANDF_ALE__NANDF_ALE (_MX51_PAD_NANDF_ALE__NANDF_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)) | 240 | #define MX51_PAD_NANDF_ALE__NANDF_ALE IOMUX_PAD(0x4ec, 0x110, 0, __NA_, 0, NO_PAD_CTRL) |
| 995 | #define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN (_MX51_PAD_NANDF_ALE__PATA_BUFFER_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) | 241 | #define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL) |
| 996 | #define MX51_PAD_NANDF_CLE__GPIO3_6 (_MX51_PAD_NANDF_CLE__GPIO3_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 242 | #define MX51_PAD_NANDF_CLE__GPIO3_6 IOMUX_PAD(0x4f0, 0x114, 3, 0x98c, 0, MX51_GPIO_PAD_CTRL) |
| 997 | #define MX51_PAD_NANDF_CLE__NANDF_CLE (_MX51_PAD_NANDF_CLE__NANDF_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)) | 243 | #define MX51_PAD_NANDF_CLE__NANDF_CLE IOMUX_PAD(0x4f0, 0x114, 0, __NA_, 0, NO_PAD_CTRL) |
| 998 | #define MX51_PAD_NANDF_CLE__PATA_RESET_B (_MX51_PAD_NANDF_CLE__PATA_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL)) | 244 | #define MX51_PAD_NANDF_CLE__PATA_RESET_B IOMUX_PAD(0x4f0, 0x114, 1, __NA_, 0, NO_PAD_CTRL) |
| 999 | #define MX51_PAD_NANDF_WP_B__GPIO3_7 (_MX51_PAD_NANDF_WP_B__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 245 | #define MX51_PAD_NANDF_WP_B__GPIO3_7 IOMUX_PAD(0x4f4, 0x118, 3, 0x990, 0, MX51_GPIO_PAD_CTRL) |
| 1000 | #define MX51_PAD_NANDF_WP_B__NANDF_WP_B (_MX51_PAD_NANDF_WP_B__NANDF_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)) | 246 | #define MX51_PAD_NANDF_WP_B__NANDF_WP_B IOMUX_PAD(0x4f4, 0x118, 0, __NA_, 0, NO_PAD_CTRL) |
| 1001 | #define MX51_PAD_NANDF_WP_B__PATA_DMACK (_MX51_PAD_NANDF_WP_B__PATA_DMACK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 247 | #define MX51_PAD_NANDF_WP_B__PATA_DMACK IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL) |
| 1002 | #define MX51_PAD_NANDF_WP_B__SD3_DATA2 (_MX51_PAD_NANDF_WP_B__SD3_DATA2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) | 248 | #define MX51_PAD_NANDF_WP_B__SD3_DATA2 IOMUX_PAD(0x4f4, 0x118, 2, 0x944, 0, MX51_SDHCI_PAD_CTRL) |
| 1003 | #define MX51_PAD_NANDF_RB0__ECSPI2_SS1 (_MX51_PAD_NANDF_RB0__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 249 | #define MX51_PAD_NANDF_RB0__ECSPI2_SS1 IOMUX_PAD(0x4f8, 0x11c, 5, 0x930, 0, MX51_ECSPI_PAD_CTRL) |
| 1004 | #define MX51_PAD_NANDF_RB0__GPIO3_8 (_MX51_PAD_NANDF_RB0__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 250 | #define MX51_PAD_NANDF_RB0__GPIO3_8 IOMUX_PAD(0x4f8, 0x11c, 3, 0x994, 0, MX51_GPIO_PAD_CTRL) |
| 1005 | #define MX51_PAD_NANDF_RB0__NANDF_RB0 (_MX51_PAD_NANDF_RB0__NANDF_RB0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 251 | #define MX51_PAD_NANDF_RB0__NANDF_RB0 IOMUX_PAD(0x4f8, 0x11c, 0, __NA_, 0, NO_PAD_CTRL) |
| 1006 | #define MX51_PAD_NANDF_RB0__PATA_DMARQ (_MX51_PAD_NANDF_RB0__PATA_DMARQ | MUX_PAD_CTRL(NO_PAD_CTRL)) | 252 | #define MX51_PAD_NANDF_RB0__PATA_DMARQ IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL) |
| 1007 | #define MX51_PAD_NANDF_RB0__SD3_DATA3 (_MX51_PAD_NANDF_RB0__SD3_DATA3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) | 253 | #define MX51_PAD_NANDF_RB0__SD3_DATA3 IOMUX_PAD(0x4f8, 0x11c, 2, 0x948, 0, MX51_SDHCI_PAD_CTRL) |
| 1008 | #define MX51_PAD_NANDF_RB1__CSPI_MOSI (_MX51_PAD_NANDF_RB1__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 254 | #define MX51_PAD_NANDF_RB1__CSPI_MOSI IOMUX_PAD(0x4fc, 0x120, 6, 0x91c, 0, MX51_ECSPI_PAD_CTRL) |
| 1009 | #define MX51_PAD_NANDF_RB1__ECSPI2_RDY (_MX51_PAD_NANDF_RB1__ECSPI2_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 255 | #define MX51_PAD_NANDF_RB1__ECSPI2_RDY IOMUX_PAD(0x4fc, 0x120, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) |
| 1010 | #define MX51_PAD_NANDF_RB1__GPIO3_9 (_MX51_PAD_NANDF_RB1__GPIO3_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 256 | #define MX51_PAD_NANDF_RB1__GPIO3_9 IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1011 | #define MX51_PAD_NANDF_RB1__NANDF_RB1 (_MX51_PAD_NANDF_RB1__NANDF_RB1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 257 | #define MX51_PAD_NANDF_RB1__NANDF_RB1 IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL) |
| 1012 | #define MX51_PAD_NANDF_RB1__PATA_IORDY (_MX51_PAD_NANDF_RB1__PATA_IORDY | MUX_PAD_CTRL(NO_PAD_CTRL)) | 258 | #define MX51_PAD_NANDF_RB1__PATA_IORDY IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL) |
| 1013 | #define MX51_PAD_NANDF_RB1__SD4_CMD (_MX51_PAD_NANDF_RB1__SD4_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) | 259 | #define MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) |
| 1014 | #define MX51_PAD_NANDF_RB2__DISP2_WAIT (_MX51_PAD_NANDF_RB2__DISP2_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL)) | 260 | #define MX51_PAD_NANDF_RB2__DISP2_WAIT IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL) |
| 1015 | #define MX51_PAD_NANDF_RB2__ECSPI2_SCLK (_MX51_PAD_NANDF_RB2__ECSPI2_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 261 | #define MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) |
| 1016 | #define MX51_PAD_NANDF_RB2__FEC_COL (_MX51_PAD_NANDF_RB2__FEC_COL | MUX_PAD_CTRL(MX51_PAD_CTRL_2)) | 262 | #define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2) |
| 1017 | #define MX51_PAD_NANDF_RB2__GPIO3_10 (_MX51_PAD_NANDF_RB2__GPIO3_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 263 | #define MX51_PAD_NANDF_RB2__GPIO3_10 IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1018 | #define MX51_PAD_NANDF_RB2__NANDF_RB2 (_MX51_PAD_NANDF_RB2__NANDF_RB2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 264 | #define MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL) |
| 1019 | #define MX51_PAD_NANDF_RB2__USBH3_H3_DP (_MX51_PAD_NANDF_RB2__USBH3_H3_DP | MUX_PAD_CTRL(NO_PAD_CTRL)) | 265 | #define MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 7, __NA_, 0, NO_PAD_CTRL) |
| 1020 | #define MX51_PAD_NANDF_RB2__USBH3_NXT (_MX51_PAD_NANDF_RB2__USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) | 266 | #define MX51_PAD_NANDF_RB2__USBH3_NXT IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL) |
| 1021 | #define MX51_PAD_NANDF_RB3__DISP1_WAIT (_MX51_PAD_NANDF_RB3__DISP1_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL)) | 267 | #define MX51_PAD_NANDF_RB3__DISP1_WAIT IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL) |
| 1022 | #define MX51_PAD_NANDF_RB3__ECSPI2_MISO (_MX51_PAD_NANDF_RB3__ECSPI2_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 268 | #define MX51_PAD_NANDF_RB3__ECSPI2_MISO IOMUX_PAD(0x504, 0x128, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) |
| 1023 | #define MX51_PAD_NANDF_RB3__FEC_RX_CLK (_MX51_PAD_NANDF_RB3__FEC_RX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_2)) | 269 | #define MX51_PAD_NANDF_RB3__FEC_RX_CLK IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2) |
| 1024 | #define MX51_PAD_NANDF_RB3__GPIO3_11 (_MX51_PAD_NANDF_RB3__GPIO3_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 270 | #define MX51_PAD_NANDF_RB3__GPIO3_11 IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1025 | #define MX51_PAD_NANDF_RB3__NANDF_RB3 (_MX51_PAD_NANDF_RB3__NANDF_RB3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 271 | #define MX51_PAD_NANDF_RB3__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 0, __NA_, 0, NO_PAD_CTRL) |
| 1026 | #define MX51_PAD_NANDF_RB3__USBH3_CLK (_MX51_PAD_NANDF_RB3__USBH3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 272 | #define MX51_PAD_NANDF_RB3__USBH3_CLK IOMUX_PAD(0x504, 0x128, 6, 0x9f8, 0, NO_PAD_CTRL) |
| 1027 | #define MX51_PAD_NANDF_RB3__USBH3_H3_DM (_MX51_PAD_NANDF_RB3__USBH3_H3_DM | MUX_PAD_CTRL(NO_PAD_CTRL)) | 273 | #define MX51_PAD_NANDF_RB3__USBH3_H3_DM IOMUX_PAD(0x504, 0x128, 7, __NA_, 0, NO_PAD_CTRL) |
| 1028 | #define MX51_PAD_GPIO_NAND__GPIO_NAND (_MX51_PAD_GPIO_NAND__GPIO_NAND | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 274 | #define MX51_PAD_GPIO_NAND__GPIO_NAND IOMUX_PAD(0x514, 0x12c, 0, 0x998, 0, MX51_GPIO_PAD_CTRL) |
| 1029 | #define MX51_PAD_GPIO_NAND__PATA_INTRQ (_MX51_PAD_GPIO_NAND__PATA_INTRQ | MUX_PAD_CTRL(NO_PAD_CTRL)) | 275 | #define MX51_PAD_GPIO_NAND__PATA_INTRQ IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL) |
| 1030 | #define MX51_PAD_NANDF_CS0__GPIO3_16 (_MX51_PAD_NANDF_CS0__GPIO3_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 276 | #define MX51_PAD_NANDF_CS0__GPIO3_16 IOMUX_PAD(0x518, 0x130, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1031 | #define MX51_PAD_NANDF_CS0__NANDF_CS0 (_MX51_PAD_NANDF_CS0__NANDF_CS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 277 | #define MX51_PAD_NANDF_CS0__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 0, __NA_, 0, NO_PAD_CTRL) |
| 1032 | #define MX51_PAD_NANDF_CS1__GPIO3_17 (_MX51_PAD_NANDF_CS1__GPIO3_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 278 | #define MX51_PAD_NANDF_CS1__GPIO3_17 IOMUX_PAD(0x51c, 0x134, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1033 | #define MX51_PAD_NANDF_CS1__NANDF_CS1 (_MX51_PAD_NANDF_CS1__NANDF_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 279 | #define MX51_PAD_NANDF_CS1__NANDF_CS1 IOMUX_PAD(0x51c, 0x134, 0, __NA_, 0, NO_PAD_CTRL) |
| 1034 | #define MX51_PAD_NANDF_CS2__CSPI_SCLK (_MX51_PAD_NANDF_CS2__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 280 | #define MX51_PAD_NANDF_CS2__CSPI_SCLK IOMUX_PAD(0x520, 0x138, 6, 0x914, 0, MX51_ECSPI_PAD_CTRL) |
| 1035 | #define MX51_PAD_NANDF_CS2__FEC_TX_ER (_MX51_PAD_NANDF_CS2__FEC_TX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) | 281 | #define MX51_PAD_NANDF_CS2__FEC_TX_ER IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5) |
| 1036 | #define MX51_PAD_NANDF_CS2__GPIO3_18 (_MX51_PAD_NANDF_CS2__GPIO3_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 282 | #define MX51_PAD_NANDF_CS2__GPIO3_18 IOMUX_PAD(0x520, 0x138, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1037 | #define MX51_PAD_NANDF_CS2__NANDF_CS2 (_MX51_PAD_NANDF_CS2__NANDF_CS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 283 | #define MX51_PAD_NANDF_CS2__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 0, __NA_, 0, NO_PAD_CTRL) |
| 1038 | #define MX51_PAD_NANDF_CS2__PATA_CS_0 (_MX51_PAD_NANDF_CS2__PATA_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 284 | #define MX51_PAD_NANDF_CS2__PATA_CS_0 IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL) |
| 1039 | #define MX51_PAD_NANDF_CS2__SD4_CLK (_MX51_PAD_NANDF_CS2__SD4_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)) | 285 | #define MX51_PAD_NANDF_CS2__SD4_CLK IOMUX_PAD(0x520, 0x138, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) |
| 1040 | #define MX51_PAD_NANDF_CS2__USBH3_H1_DP (_MX51_PAD_NANDF_CS2__USBH3_H1_DP | MUX_PAD_CTRL(NO_PAD_CTRL)) | 286 | #define MX51_PAD_NANDF_CS2__USBH3_H1_DP IOMUX_PAD(0x520, 0x138, 7, __NA_, 0, NO_PAD_CTRL) |
| 1041 | #define MX51_PAD_NANDF_CS3__FEC_MDC (_MX51_PAD_NANDF_CS3__FEC_MDC | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) | 287 | #define MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5) |
| 1042 | #define MX51_PAD_NANDF_CS3__GPIO3_19 (_MX51_PAD_NANDF_CS3__GPIO3_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 288 | #define MX51_PAD_NANDF_CS3__GPIO3_19 IOMUX_PAD(0x524, 0x13c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1043 | #define MX51_PAD_NANDF_CS3__NANDF_CS3 (_MX51_PAD_NANDF_CS3__NANDF_CS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 289 | #define MX51_PAD_NANDF_CS3__NANDF_CS3 IOMUX_PAD(0x524, 0x13c, 0, __NA_, 0, NO_PAD_CTRL) |
| 1044 | #define MX51_PAD_NANDF_CS3__PATA_CS_1 (_MX51_PAD_NANDF_CS3__PATA_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 290 | #define MX51_PAD_NANDF_CS3__PATA_CS_1 IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL) |
| 1045 | #define MX51_PAD_NANDF_CS3__SD4_DAT0 (_MX51_PAD_NANDF_CS3__SD4_DAT0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) | 291 | #define MX51_PAD_NANDF_CS3__SD4_DAT0 IOMUX_PAD(0x524, 0x13c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) |
| 1046 | #define MX51_PAD_NANDF_CS3__USBH3_H1_DM (_MX51_PAD_NANDF_CS3__USBH3_H1_DM | MUX_PAD_CTRL(NO_PAD_CTRL)) | 292 | #define MX51_PAD_NANDF_CS3__USBH3_H1_DM IOMUX_PAD(0x524, 0x13c, 7, __NA_, 0, NO_PAD_CTRL) |
| 1047 | #define MX51_PAD_NANDF_CS4__FEC_TDATA1 (_MX51_PAD_NANDF_CS4__FEC_TDATA1 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) | 293 | #define MX51_PAD_NANDF_CS4__FEC_TDATA1 IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5) |
| 1048 | #define MX51_PAD_NANDF_CS4__GPIO3_20 (_MX51_PAD_NANDF_CS4__GPIO3_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 294 | #define MX51_PAD_NANDF_CS4__GPIO3_20 IOMUX_PAD(0x528, 0x140, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1049 | #define MX51_PAD_NANDF_CS4__NANDF_CS4 (_MX51_PAD_NANDF_CS4__NANDF_CS4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 295 | #define MX51_PAD_NANDF_CS4__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 0, __NA_, 0, NO_PAD_CTRL) |
| 1050 | #define MX51_PAD_NANDF_CS4__PATA_DA_0 (_MX51_PAD_NANDF_CS4__PATA_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 296 | #define MX51_PAD_NANDF_CS4__PATA_DA_0 IOMUX_PAD(0x528, 0x140, 1, __NA_, 0, NO_PAD_CTRL) |
| 1051 | #define MX51_PAD_NANDF_CS4__SD4_DAT1 (_MX51_PAD_NANDF_CS4__SD4_DAT1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) | 297 | #define MX51_PAD_NANDF_CS4__SD4_DAT1 IOMUX_PAD(0x528, 0x140, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) |
| 1052 | #define MX51_PAD_NANDF_CS4__USBH3_STP (_MX51_PAD_NANDF_CS4__USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) | 298 | #define MX51_PAD_NANDF_CS4__USBH3_STP IOMUX_PAD(0x528, 0x140, 7, 0xa24, 0, NO_PAD_CTRL) |
| 1053 | #define MX51_PAD_NANDF_CS5__FEC_TDATA2 (_MX51_PAD_NANDF_CS5__FEC_TDATA2 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) | 299 | #define MX51_PAD_NANDF_CS5__FEC_TDATA2 IOMUX_PAD(0x52c, 0x144, 2, __NA_, 0, MX51_PAD_CTRL_5) |
| 1054 | #define MX51_PAD_NANDF_CS5__GPIO3_21 (_MX51_PAD_NANDF_CS5__GPIO3_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 300 | #define MX51_PAD_NANDF_CS5__GPIO3_21 IOMUX_PAD(0x52c, 0x144, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1055 | #define MX51_PAD_NANDF_CS5__NANDF_CS5 (_MX51_PAD_NANDF_CS5__NANDF_CS5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 301 | #define MX51_PAD_NANDF_CS5__NANDF_CS5 IOMUX_PAD(0x52c, 0x144, 0, __NA_, 0, NO_PAD_CTRL) |
| 1056 | #define MX51_PAD_NANDF_CS5__PATA_DA_1 (_MX51_PAD_NANDF_CS5__PATA_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 302 | #define MX51_PAD_NANDF_CS5__PATA_DA_1 IOMUX_PAD(0x52c, 0x144, 1, __NA_, 0, NO_PAD_CTRL) |
| 1057 | #define MX51_PAD_NANDF_CS5__SD4_DAT2 (_MX51_PAD_NANDF_CS5__SD4_DAT2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) | 303 | #define MX51_PAD_NANDF_CS5__SD4_DAT2 IOMUX_PAD(0x52c, 0x144, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) |
| 1058 | #define MX51_PAD_NANDF_CS5__USBH3_DIR (_MX51_PAD_NANDF_CS5__USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) | 304 | #define MX51_PAD_NANDF_CS5__USBH3_DIR IOMUX_PAD(0x52c, 0x144, 7, 0xa1c, 0, NO_PAD_CTRL) |
| 1059 | #define MX51_PAD_NANDF_CS6__CSPI_SS3 (_MX51_PAD_NANDF_CS6__CSPI_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 305 | #define MX51_PAD_NANDF_CS6__CSPI_SS3 IOMUX_PAD(0x530, 0x148, 7, 0x928, 0, MX51_ECSPI_PAD_CTRL) |
| 1060 | #define MX51_PAD_NANDF_CS6__FEC_TDATA3 (_MX51_PAD_NANDF_CS6__FEC_TDATA3 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) | 306 | #define MX51_PAD_NANDF_CS6__FEC_TDATA3 IOMUX_PAD(0x530, 0x148, 2, __NA_, 0, MX51_PAD_CTRL_5) |
| 1061 | #define MX51_PAD_NANDF_CS6__GPIO3_22 (_MX51_PAD_NANDF_CS6__GPIO3_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 307 | #define MX51_PAD_NANDF_CS6__GPIO3_22 IOMUX_PAD(0x530, 0x148, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1062 | #define MX51_PAD_NANDF_CS6__NANDF_CS6 (_MX51_PAD_NANDF_CS6__NANDF_CS6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 308 | #define MX51_PAD_NANDF_CS6__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 0, __NA_, 0, NO_PAD_CTRL) |
| 1063 | #define MX51_PAD_NANDF_CS6__PATA_DA_2 (_MX51_PAD_NANDF_CS6__PATA_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 309 | #define MX51_PAD_NANDF_CS6__PATA_DA_2 IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL) |
| 1064 | #define MX51_PAD_NANDF_CS6__SD4_DAT3 (_MX51_PAD_NANDF_CS6__SD4_DAT3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) | 310 | #define MX51_PAD_NANDF_CS6__SD4_DAT3 IOMUX_PAD(0x530, 0x148, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) |
| 1065 | #define MX51_PAD_NANDF_CS7__FEC_TX_EN (_MX51_PAD_NANDF_CS7__FEC_TX_EN | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) | 311 | #define MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14c, 1, __NA_, 0, MX51_PAD_CTRL_5) |
| 1066 | #define MX51_PAD_NANDF_CS7__GPIO3_23 (_MX51_PAD_NANDF_CS7__GPIO3_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 312 | #define MX51_PAD_NANDF_CS7__GPIO3_23 IOMUX_PAD(0x534, 0x14c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1067 | #define MX51_PAD_NANDF_CS7__NANDF_CS7 (_MX51_PAD_NANDF_CS7__NANDF_CS7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 313 | #define MX51_PAD_NANDF_CS7__NANDF_CS7 IOMUX_PAD(0x534, 0x14c, 0, __NA_, 0, NO_PAD_CTRL) |
| 1068 | #define MX51_PAD_NANDF_CS7__SD3_CLK (_MX51_PAD_NANDF_CS7__SD3_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)) | 314 | #define MX51_PAD_NANDF_CS7__SD3_CLK IOMUX_PAD(0x534, 0x14c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) |
| 1069 | #define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 (_MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 315 | #define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 IOMUX_PAD(0x538, 0x150, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) |
| 1070 | #define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK (_MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_4)) | 316 | #define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4) |
| 1071 | #define MX51_PAD_NANDF_RDY_INT__GPIO3_24 (_MX51_PAD_NANDF_RDY_INT__GPIO3_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 317 | #define MX51_PAD_NANDF_RDY_INT__GPIO3_24 IOMUX_PAD(0x538, 0x150, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1072 | #define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT (_MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT | MUX_PAD_CTRL(NO_PAD_CTRL)) | 318 | #define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 0, 0x938, 0, NO_PAD_CTRL) |
| 1073 | #define MX51_PAD_NANDF_RDY_INT__SD3_CMD (_MX51_PAD_NANDF_RDY_INT__SD3_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) | 319 | #define MX51_PAD_NANDF_RDY_INT__SD3_CMD IOMUX_PAD(0x538, 0x150, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) |
| 1074 | #define MX51_PAD_NANDF_D15__ECSPI2_MOSI (_MX51_PAD_NANDF_D15__ECSPI2_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 320 | #define MX51_PAD_NANDF_D15__ECSPI2_MOSI IOMUX_PAD(0x53c, 0x154, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) |
| 1075 | #define MX51_PAD_NANDF_D15__GPIO3_25 (_MX51_PAD_NANDF_D15__GPIO3_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 321 | #define MX51_PAD_NANDF_D15__GPIO3_25 IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1076 | #define MX51_PAD_NANDF_D15__NANDF_D15 (_MX51_PAD_NANDF_D15__NANDF_D15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 322 | #define MX51_PAD_NANDF_D15__NANDF_D15 IOMUX_PAD(0x53c, 0x154, 0, __NA_, 0, NO_PAD_CTRL) |
| 1077 | #define MX51_PAD_NANDF_D15__PATA_DATA15 (_MX51_PAD_NANDF_D15__PATA_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 323 | #define MX51_PAD_NANDF_D15__PATA_DATA15 IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL) |
| 1078 | #define MX51_PAD_NANDF_D15__SD3_DAT7 (_MX51_PAD_NANDF_D15__SD3_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 324 | #define MX51_PAD_NANDF_D15__SD3_DAT7 IOMUX_PAD(0x53c, 0x154, 5, __NA_, 0, NO_PAD_CTRL) |
| 1079 | #define MX51_PAD_NANDF_D14__ECSPI2_SS3 (_MX51_PAD_NANDF_D14__ECSPI2_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 325 | #define MX51_PAD_NANDF_D14__ECSPI2_SS3 IOMUX_PAD(0x540, 0x158, 2, 0x934, 0, MX51_ECSPI_PAD_CTRL) |
| 1080 | #define MX51_PAD_NANDF_D14__GPIO3_26 (_MX51_PAD_NANDF_D14__GPIO3_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 326 | #define MX51_PAD_NANDF_D14__GPIO3_26 IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1081 | #define MX51_PAD_NANDF_D14__NANDF_D14 (_MX51_PAD_NANDF_D14__NANDF_D14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 327 | #define MX51_PAD_NANDF_D14__NANDF_D14 IOMUX_PAD(0x540, 0x158, 0, __NA_, 0, NO_PAD_CTRL) |
| 1082 | #define MX51_PAD_NANDF_D14__PATA_DATA14 (_MX51_PAD_NANDF_D14__PATA_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 328 | #define MX51_PAD_NANDF_D14__PATA_DATA14 IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL) |
| 1083 | #define MX51_PAD_NANDF_D14__SD3_DAT6 (_MX51_PAD_NANDF_D14__SD3_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 329 | #define MX51_PAD_NANDF_D14__SD3_DAT6 IOMUX_PAD(0x540, 0x158, 5, __NA_, 0, NO_PAD_CTRL) |
| 1084 | #define MX51_PAD_NANDF_D13__ECSPI2_SS2 (_MX51_PAD_NANDF_D13__ECSPI2_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 330 | #define MX51_PAD_NANDF_D13__ECSPI2_SS2 IOMUX_PAD(0x544, 0x15c, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) |
| 1085 | #define MX51_PAD_NANDF_D13__GPIO3_27 (_MX51_PAD_NANDF_D13__GPIO3_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 331 | #define MX51_PAD_NANDF_D13__GPIO3_27 IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1086 | #define MX51_PAD_NANDF_D13__NANDF_D13 (_MX51_PAD_NANDF_D13__NANDF_D13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 332 | #define MX51_PAD_NANDF_D13__NANDF_D13 IOMUX_PAD(0x544, 0x15c, 0, __NA_, 0, NO_PAD_CTRL) |
| 1087 | #define MX51_PAD_NANDF_D13__PATA_DATA13 (_MX51_PAD_NANDF_D13__PATA_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 333 | #define MX51_PAD_NANDF_D13__PATA_DATA13 IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL) |
| 1088 | #define MX51_PAD_NANDF_D13__SD3_DAT5 (_MX51_PAD_NANDF_D13__SD3_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 334 | #define MX51_PAD_NANDF_D13__SD3_DAT5 IOMUX_PAD(0x544, 0x15c, 5, __NA_, 0, NO_PAD_CTRL) |
| 1089 | #define MX51_PAD_NANDF_D12__ECSPI2_SS1 (_MX51_PAD_NANDF_D12__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 335 | #define MX51_PAD_NANDF_D12__ECSPI2_SS1 IOMUX_PAD(0x548, 0x160, 2, 0x930, 1, MX51_ECSPI_PAD_CTRL) |
| 1090 | #define MX51_PAD_NANDF_D12__GPIO3_28 (_MX51_PAD_NANDF_D12__GPIO3_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 336 | #define MX51_PAD_NANDF_D12__GPIO3_28 IOMUX_PAD(0x548, 0x160, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1091 | #define MX51_PAD_NANDF_D12__NANDF_D12 (_MX51_PAD_NANDF_D12__NANDF_D12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 337 | #define MX51_PAD_NANDF_D12__NANDF_D12 IOMUX_PAD(0x548, 0x160, 0, __NA_, 0, NO_PAD_CTRL) |
| 1092 | #define MX51_PAD_NANDF_D12__PATA_DATA12 (_MX51_PAD_NANDF_D12__PATA_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 338 | #define MX51_PAD_NANDF_D12__PATA_DATA12 IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL) |
| 1093 | #define MX51_PAD_NANDF_D12__SD3_DAT4 (_MX51_PAD_NANDF_D12__SD3_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 339 | #define MX51_PAD_NANDF_D12__SD3_DAT4 IOMUX_PAD(0x548, 0x160, 5, __NA_, 0, NO_PAD_CTRL) |
| 1094 | #define MX51_PAD_NANDF_D11__FEC_RX_DV (_MX51_PAD_NANDF_D11__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL)) | 340 | #define MX51_PAD_NANDF_D11__FEC_RX_DV IOMUX_PAD(0x54c, 0x164, 2, 0x96c, 0, NO_PAD_CTRL) |
| 1095 | #define MX51_PAD_NANDF_D11__GPIO3_29 (_MX51_PAD_NANDF_D11__GPIO3_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 341 | #define MX51_PAD_NANDF_D11__GPIO3_29 IOMUX_PAD(0x54c, 0x164, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1096 | #define MX51_PAD_NANDF_D11__NANDF_D11 (_MX51_PAD_NANDF_D11__NANDF_D11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 342 | #define MX51_PAD_NANDF_D11__NANDF_D11 IOMUX_PAD(0x54c, 0x164, 0, __NA_, 0, NO_PAD_CTRL) |
| 1097 | #define MX51_PAD_NANDF_D11__PATA_DATA11 (_MX51_PAD_NANDF_D11__PATA_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 343 | #define MX51_PAD_NANDF_D11__PATA_DATA11 IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL) |
| 1098 | #define MX51_PAD_NANDF_D11__SD3_DATA3 (_MX51_PAD_NANDF_D11__SD3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 344 | #define MX51_PAD_NANDF_D11__SD3_DATA3 IOMUX_PAD(0x54c, 0x164, 5, 0x948, 1, NO_PAD_CTRL) |
| 1099 | #define MX51_PAD_NANDF_D10__GPIO3_30 (_MX51_PAD_NANDF_D10__GPIO3_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 345 | #define MX51_PAD_NANDF_D10__GPIO3_30 IOMUX_PAD(0x550, 0x168, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1100 | #define MX51_PAD_NANDF_D10__NANDF_D10 (_MX51_PAD_NANDF_D10__NANDF_D10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 346 | #define MX51_PAD_NANDF_D10__NANDF_D10 IOMUX_PAD(0x550, 0x168, 0, __NA_, 0, NO_PAD_CTRL) |
| 1101 | #define MX51_PAD_NANDF_D10__PATA_DATA10 (_MX51_PAD_NANDF_D10__PATA_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 347 | #define MX51_PAD_NANDF_D10__PATA_DATA10 IOMUX_PAD(0x550, 0x168, 1, __NA_, 0, NO_PAD_CTRL) |
| 1102 | #define MX51_PAD_NANDF_D10__SD3_DATA2 (_MX51_PAD_NANDF_D10__SD3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 348 | #define MX51_PAD_NANDF_D10__SD3_DATA2 IOMUX_PAD(0x550, 0x168, 5, 0x944, 1, NO_PAD_CTRL) |
| 1103 | #define MX51_PAD_NANDF_D9__FEC_RDATA0 (_MX51_PAD_NANDF_D9__FEC_RDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_4)) | 349 | #define MX51_PAD_NANDF_D9__FEC_RDATA0 IOMUX_PAD(0x554, 0x16c, 0x12, 0x958, 0, MX51_PAD_CTRL_4) |
| 1104 | #define MX51_PAD_NANDF_D9__GPIO3_31 (_MX51_PAD_NANDF_D9__GPIO3_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 350 | #define MX51_PAD_NANDF_D9__GPIO3_31 IOMUX_PAD(0x554, 0x16c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1105 | #define MX51_PAD_NANDF_D9__NANDF_D9 (_MX51_PAD_NANDF_D9__NANDF_D9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 351 | #define MX51_PAD_NANDF_D9__NANDF_D9 IOMUX_PAD(0x554, 0x16c, 0, __NA_, 0, NO_PAD_CTRL) |
| 1106 | #define MX51_PAD_NANDF_D9__PATA_DATA9 (_MX51_PAD_NANDF_D9__PATA_DATA9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 352 | #define MX51_PAD_NANDF_D9__PATA_DATA9 IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL) |
| 1107 | #define MX51_PAD_NANDF_D9__SD3_DATA1 (_MX51_PAD_NANDF_D9__SD3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 353 | #define MX51_PAD_NANDF_D9__SD3_DATA1 IOMUX_PAD(0x554, 0x16c, 5, 0x940, 1, NO_PAD_CTRL) |
| 1108 | #define MX51_PAD_NANDF_D8__FEC_TDATA0 (_MX51_PAD_NANDF_D8__FEC_TDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) | 354 | #define MX51_PAD_NANDF_D8__FEC_TDATA0 IOMUX_PAD(0x558, 0x170, 2, __NA_, 0, MX51_PAD_CTRL_5) |
| 1109 | #define MX51_PAD_NANDF_D8__GPIO4_0 (_MX51_PAD_NANDF_D8__GPIO4_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 355 | #define MX51_PAD_NANDF_D8__GPIO4_0 IOMUX_PAD(0x558, 0x170, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1110 | #define MX51_PAD_NANDF_D8__NANDF_D8 (_MX51_PAD_NANDF_D8__NANDF_D8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 356 | #define MX51_PAD_NANDF_D8__NANDF_D8 IOMUX_PAD(0x558, 0x170, 0, __NA_, 0, NO_PAD_CTRL) |
| 1111 | #define MX51_PAD_NANDF_D8__PATA_DATA8 (_MX51_PAD_NANDF_D8__PATA_DATA8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 357 | #define MX51_PAD_NANDF_D8__PATA_DATA8 IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL) |
| 1112 | #define MX51_PAD_NANDF_D8__SD3_DATA0 (_MX51_PAD_NANDF_D8__SD3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 358 | #define MX51_PAD_NANDF_D8__SD3_DATA0 IOMUX_PAD(0x558, 0x170, 5, 0x93c, 1, NO_PAD_CTRL) |
| 1113 | #define MX51_PAD_NANDF_D7__GPIO4_1 (_MX51_PAD_NANDF_D7__GPIO4_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 359 | #define MX51_PAD_NANDF_D7__GPIO4_1 IOMUX_PAD(0x55c, 0x174, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1114 | #define MX51_PAD_NANDF_D7__NANDF_D7 (_MX51_PAD_NANDF_D7__NANDF_D7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 360 | #define MX51_PAD_NANDF_D7__NANDF_D7 IOMUX_PAD(0x55c, 0x174, 0, __NA_, 0, NO_PAD_CTRL) |
| 1115 | #define MX51_PAD_NANDF_D7__PATA_DATA7 (_MX51_PAD_NANDF_D7__PATA_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 361 | #define MX51_PAD_NANDF_D7__PATA_DATA7 IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL) |
| 1116 | #define MX51_PAD_NANDF_D7__USBH3_DATA0 (_MX51_PAD_NANDF_D7__USBH3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 362 | #define MX51_PAD_NANDF_D7__USBH3_DATA0 IOMUX_PAD(0x55c, 0x174, 5, 0x9fc, 0, NO_PAD_CTRL) |
| 1117 | #define MX51_PAD_NANDF_D6__GPIO4_2 (_MX51_PAD_NANDF_D6__GPIO4_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 363 | #define MX51_PAD_NANDF_D6__GPIO4_2 IOMUX_PAD(0x560, 0x178, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1118 | #define MX51_PAD_NANDF_D6__NANDF_D6 (_MX51_PAD_NANDF_D6__NANDF_D6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 364 | #define MX51_PAD_NANDF_D6__NANDF_D6 IOMUX_PAD(0x560, 0x178, 0, __NA_, 0, NO_PAD_CTRL) |
| 1119 | #define MX51_PAD_NANDF_D6__PATA_DATA6 (_MX51_PAD_NANDF_D6__PATA_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 365 | #define MX51_PAD_NANDF_D6__PATA_DATA6 IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL) |
| 1120 | #define MX51_PAD_NANDF_D6__SD4_LCTL (_MX51_PAD_NANDF_D6__SD4_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL)) | 366 | #define MX51_PAD_NANDF_D6__SD4_LCTL IOMUX_PAD(0x560, 0x178, 2, __NA_, 0, NO_PAD_CTRL) |
| 1121 | #define MX51_PAD_NANDF_D6__USBH3_DATA1 (_MX51_PAD_NANDF_D6__USBH3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 367 | #define MX51_PAD_NANDF_D6__USBH3_DATA1 IOMUX_PAD(0x560, 0x178, 5, 0xa00, 0, NO_PAD_CTRL) |
| 1122 | #define MX51_PAD_NANDF_D5__GPIO4_3 (_MX51_PAD_NANDF_D5__GPIO4_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 368 | #define MX51_PAD_NANDF_D5__GPIO4_3 IOMUX_PAD(0x564, 0x17c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1123 | #define MX51_PAD_NANDF_D5__NANDF_D5 (_MX51_PAD_NANDF_D5__NANDF_D5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 369 | #define MX51_PAD_NANDF_D5__NANDF_D5 IOMUX_PAD(0x564, 0x17c, 0, __NA_, 0, NO_PAD_CTRL) |
| 1124 | #define MX51_PAD_NANDF_D5__PATA_DATA5 (_MX51_PAD_NANDF_D5__PATA_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 370 | #define MX51_PAD_NANDF_D5__PATA_DATA5 IOMUX_PAD(0x564, 0x17c, 1, __NA_, 0, NO_PAD_CTRL) |
| 1125 | #define MX51_PAD_NANDF_D5__SD4_WP (_MX51_PAD_NANDF_D5__SD4_WP | MUX_PAD_CTRL(NO_PAD_CTRL)) | 371 | #define MX51_PAD_NANDF_D5__SD4_WP IOMUX_PAD(0x564, 0x17c, 2, __NA_, 0, NO_PAD_CTRL) |
| 1126 | #define MX51_PAD_NANDF_D5__USBH3_DATA2 (_MX51_PAD_NANDF_D5__USBH3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 372 | #define MX51_PAD_NANDF_D5__USBH3_DATA2 IOMUX_PAD(0x564, 0x17c, 5, 0xa04, 0, NO_PAD_CTRL) |
| 1127 | #define MX51_PAD_NANDF_D4__GPIO4_4 (_MX51_PAD_NANDF_D4__GPIO4_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 373 | #define MX51_PAD_NANDF_D4__GPIO4_4 IOMUX_PAD(0x568, 0x180, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1128 | #define MX51_PAD_NANDF_D4__NANDF_D4 (_MX51_PAD_NANDF_D4__NANDF_D4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 374 | #define MX51_PAD_NANDF_D4__NANDF_D4 IOMUX_PAD(0x568, 0x180, 0, __NA_, 0, NO_PAD_CTRL) |
| 1129 | #define MX51_PAD_NANDF_D4__PATA_DATA4 (_MX51_PAD_NANDF_D4__PATA_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 375 | #define MX51_PAD_NANDF_D4__PATA_DATA4 IOMUX_PAD(0x568, 0x180, 1, __NA_, 0, NO_PAD_CTRL) |
| 1130 | #define MX51_PAD_NANDF_D4__SD4_CD (_MX51_PAD_NANDF_D4__SD4_CD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 376 | #define MX51_PAD_NANDF_D4__SD4_CD IOMUX_PAD(0x568, 0x180, 2, __NA_, 0, NO_PAD_CTRL) |
| 1131 | #define MX51_PAD_NANDF_D4__USBH3_DATA3 (_MX51_PAD_NANDF_D4__USBH3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 377 | #define MX51_PAD_NANDF_D4__USBH3_DATA3 IOMUX_PAD(0x568, 0x180, 5, 0xa08, 0, NO_PAD_CTRL) |
| 1132 | #define MX51_PAD_NANDF_D3__GPIO4_5 (_MX51_PAD_NANDF_D3__GPIO4_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 378 | #define MX51_PAD_NANDF_D3__GPIO4_5 IOMUX_PAD(0x56c, 0x184, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1133 | #define MX51_PAD_NANDF_D3__NANDF_D3 (_MX51_PAD_NANDF_D3__NANDF_D3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 379 | #define MX51_PAD_NANDF_D3__NANDF_D3 IOMUX_PAD(0x56c, 0x184, 0, __NA_, 0, NO_PAD_CTRL) |
| 1134 | #define MX51_PAD_NANDF_D3__PATA_DATA3 (_MX51_PAD_NANDF_D3__PATA_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 380 | #define MX51_PAD_NANDF_D3__PATA_DATA3 IOMUX_PAD(0x56c, 0x184, 1, __NA_, 0, NO_PAD_CTRL) |
| 1135 | #define MX51_PAD_NANDF_D3__SD4_DAT4 (_MX51_PAD_NANDF_D3__SD4_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 381 | #define MX51_PAD_NANDF_D3__SD4_DAT4 IOMUX_PAD(0x56c, 0x184, 2, __NA_, 0, NO_PAD_CTRL) |
| 1136 | #define MX51_PAD_NANDF_D3__USBH3_DATA4 (_MX51_PAD_NANDF_D3__USBH3_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 382 | #define MX51_PAD_NANDF_D3__USBH3_DATA4 IOMUX_PAD(0x56c, 0x184, 5, 0xa0c, 0, NO_PAD_CTRL) |
| 1137 | #define MX51_PAD_NANDF_D2__GPIO4_6 (_MX51_PAD_NANDF_D2__GPIO4_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 383 | #define MX51_PAD_NANDF_D2__GPIO4_6 IOMUX_PAD(0x570, 0x188, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1138 | #define MX51_PAD_NANDF_D2__NANDF_D2 (_MX51_PAD_NANDF_D2__NANDF_D2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 384 | #define MX51_PAD_NANDF_D2__NANDF_D2 IOMUX_PAD(0x570, 0x188, 0, __NA_, 0, NO_PAD_CTRL) |
| 1139 | #define MX51_PAD_NANDF_D2__PATA_DATA2 (_MX51_PAD_NANDF_D2__PATA_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 385 | #define MX51_PAD_NANDF_D2__PATA_DATA2 IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL) |
| 1140 | #define MX51_PAD_NANDF_D2__SD4_DAT5 (_MX51_PAD_NANDF_D2__SD4_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 386 | #define MX51_PAD_NANDF_D2__SD4_DAT5 IOMUX_PAD(0x570, 0x188, 2, __NA_, 0, NO_PAD_CTRL) |
| 1141 | #define MX51_PAD_NANDF_D2__USBH3_DATA5 (_MX51_PAD_NANDF_D2__USBH3_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 387 | #define MX51_PAD_NANDF_D2__USBH3_DATA5 IOMUX_PAD(0x570, 0x188, 5, 0xa10, 0, NO_PAD_CTRL) |
| 1142 | #define MX51_PAD_NANDF_D1__GPIO4_7 (_MX51_PAD_NANDF_D1__GPIO4_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 388 | #define MX51_PAD_NANDF_D1__GPIO4_7 IOMUX_PAD(0x574, 0x18c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1143 | #define MX51_PAD_NANDF_D1__NANDF_D1 (_MX51_PAD_NANDF_D1__NANDF_D1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 389 | #define MX51_PAD_NANDF_D1__NANDF_D1 IOMUX_PAD(0x574, 0x18c, 0, __NA_, 0, NO_PAD_CTRL) |
| 1144 | #define MX51_PAD_NANDF_D1__PATA_DATA1 (_MX51_PAD_NANDF_D1__PATA_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 390 | #define MX51_PAD_NANDF_D1__PATA_DATA1 IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL) |
| 1145 | #define MX51_PAD_NANDF_D1__SD4_DAT6 (_MX51_PAD_NANDF_D1__SD4_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 391 | #define MX51_PAD_NANDF_D1__SD4_DAT6 IOMUX_PAD(0x574, 0x18c, 2, __NA_, 0, NO_PAD_CTRL) |
| 1146 | #define MX51_PAD_NANDF_D1__USBH3_DATA6 (_MX51_PAD_NANDF_D1__USBH3_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 392 | #define MX51_PAD_NANDF_D1__USBH3_DATA6 IOMUX_PAD(0x574, 0x18c, 5, 0xa14, 0, NO_PAD_CTRL) |
| 1147 | #define MX51_PAD_NANDF_D0__GPIO4_8 (_MX51_PAD_NANDF_D0__GPIO4_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 393 | #define MX51_PAD_NANDF_D0__GPIO4_8 IOMUX_PAD(0x578, 0x190, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1148 | #define MX51_PAD_NANDF_D0__NANDF_D0 (_MX51_PAD_NANDF_D0__NANDF_D0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 394 | #define MX51_PAD_NANDF_D0__NANDF_D0 IOMUX_PAD(0x578, 0x190, 0, __NA_, 0, NO_PAD_CTRL) |
| 1149 | #define MX51_PAD_NANDF_D0__PATA_DATA0 (_MX51_PAD_NANDF_D0__PATA_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 395 | #define MX51_PAD_NANDF_D0__PATA_DATA0 IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL) |
| 1150 | #define MX51_PAD_NANDF_D0__SD4_DAT7 (_MX51_PAD_NANDF_D0__SD4_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 396 | #define MX51_PAD_NANDF_D0__SD4_DAT7 IOMUX_PAD(0x578, 0x190, 2, __NA_, 0, NO_PAD_CTRL) |
| 1151 | #define MX51_PAD_NANDF_D0__USBH3_DATA7 (_MX51_PAD_NANDF_D0__USBH3_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 397 | #define MX51_PAD_NANDF_D0__USBH3_DATA7 IOMUX_PAD(0x578, 0x190, 5, 0xa18, 0, NO_PAD_CTRL) |
| 1152 | #define MX51_PAD_CSI1_D8__CSI1_D8 (_MX51_PAD_CSI1_D8__CSI1_D8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 398 | #define MX51_PAD_CSI1_D8__CSI1_D8 IOMUX_PAD(0x57c, 0x194, 0, __NA_, 0, NO_PAD_CTRL) |
| 1153 | #define MX51_PAD_CSI1_D8__GPIO3_12 (_MX51_PAD_CSI1_D8__GPIO3_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 399 | #define MX51_PAD_CSI1_D8__GPIO3_12 IOMUX_PAD(0x57c, 0x194, 3, 0x998, 1, MX51_GPIO_PAD_CTRL) |
| 1154 | #define MX51_PAD_CSI1_D9__CSI1_D9 (_MX51_PAD_CSI1_D9__CSI1_D9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 400 | #define MX51_PAD_CSI1_D9__CSI1_D9 IOMUX_PAD(0x580, 0x198, 0, __NA_, 0, NO_PAD_CTRL) |
| 1155 | #define MX51_PAD_CSI1_D9__GPIO3_13 (_MX51_PAD_CSI1_D9__GPIO3_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 401 | #define MX51_PAD_CSI1_D9__GPIO3_13 IOMUX_PAD(0x580, 0x198, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1156 | #define MX51_PAD_CSI1_D10__CSI1_D10 (_MX51_PAD_CSI1_D10__CSI1_D10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 402 | #define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19c, 0, __NA_, 0, NO_PAD_CTRL) |
| 1157 | #define MX51_PAD_CSI1_D11__CSI1_D11 (_MX51_PAD_CSI1_D11__CSI1_D11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 403 | #define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1a0, 0, __NA_, 0, NO_PAD_CTRL) |
| 1158 | #define MX51_PAD_CSI1_D12__CSI1_D12 (_MX51_PAD_CSI1_D12__CSI1_D12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 404 | #define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58c, 0x1a4, 0, __NA_, 0, NO_PAD_CTRL) |
| 1159 | #define MX51_PAD_CSI1_D13__CSI1_D13 (_MX51_PAD_CSI1_D13__CSI1_D13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 405 | #define MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1a8, 0, __NA_, 0, NO_PAD_CTRL) |
| 1160 | #define MX51_PAD_CSI1_D14__CSI1_D14 (_MX51_PAD_CSI1_D14__CSI1_D14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 406 | #define MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1ac, 0, __NA_, 0, NO_PAD_CTRL) |
| 1161 | #define MX51_PAD_CSI1_D15__CSI1_D15 (_MX51_PAD_CSI1_D15__CSI1_D15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 407 | #define MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1b0, 0, __NA_, 0, NO_PAD_CTRL) |
| 1162 | #define MX51_PAD_CSI1_D16__CSI1_D16 (_MX51_PAD_CSI1_D16__CSI1_D16 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 408 | #define MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59c, 0x1b4, 0, __NA_, 0, NO_PAD_CTRL) |
| 1163 | #define MX51_PAD_CSI1_D17__CSI1_D17 (_MX51_PAD_CSI1_D17__CSI1_D17 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 409 | #define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5a0, 0x1b8, 0, __NA_, 0, NO_PAD_CTRL) |
| 1164 | #define MX51_PAD_CSI1_D18__CSI1_D18 (_MX51_PAD_CSI1_D18__CSI1_D18 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 410 | #define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5a4, 0x1bc, 0, __NA_, 0, NO_PAD_CTRL) |
| 1165 | #define MX51_PAD_CSI1_D19__CSI1_D19 (_MX51_PAD_CSI1_D19__CSI1_D19 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 411 | #define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5a8, 0x1c0, 0, __NA_, 0, NO_PAD_CTRL) |
| 1166 | #define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC (_MX51_PAD_CSI1_VSYNC__CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 412 | #define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5ac, 0x1c4, 0, __NA_, 0, NO_PAD_CTRL) |
| 1167 | #define MX51_PAD_CSI1_VSYNC__GPIO3_14 (_MX51_PAD_CSI1_VSYNC__GPIO3_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 413 | #define MX51_PAD_CSI1_VSYNC__GPIO3_14 IOMUX_PAD(0x5ac, 0x1c4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1168 | #define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC (_MX51_PAD_CSI1_HSYNC__CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 414 | #define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5b0, 0x1c8, 0, __NA_, 0, NO_PAD_CTRL) |
| 1169 | #define MX51_PAD_CSI1_HSYNC__GPIO3_15 (_MX51_PAD_CSI1_HSYNC__GPIO3_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 415 | #define MX51_PAD_CSI1_HSYNC__GPIO3_15 IOMUX_PAD(0x5b0, 0x1c8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1170 | #define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK (_MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 416 | #define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5b4, __NA_, 0, 0x000, 0, NO_PAD_CTRL) |
| 1171 | #define MX51_PAD_CSI1_MCLK__CSI1_MCLK (_MX51_PAD_CSI1_MCLK__CSI1_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 417 | #define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5b8, __NA_, 0, 0x000, 0, NO_PAD_CTRL) |
| 1172 | #define MX51_PAD_CSI2_D12__CSI2_D12 (_MX51_PAD_CSI2_D12__CSI2_D12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 418 | #define MX51_PAD_CSI2_D12__CSI2_D12 IOMUX_PAD(0x5bc, 0x1cc, 0, __NA_, 0, NO_PAD_CTRL) |
| 1173 | #define MX51_PAD_CSI2_D12__GPIO4_9 (_MX51_PAD_CSI2_D12__GPIO4_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 419 | #define MX51_PAD_CSI2_D12__GPIO4_9 IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1174 | #define MX51_PAD_CSI2_D13__CSI2_D13 (_MX51_PAD_CSI2_D13__CSI2_D13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 420 | #define MX51_PAD_CSI2_D13__CSI2_D13 IOMUX_PAD(0x5c0, 0x1d0, 0, __NA_, 0, NO_PAD_CTRL) |
| 1175 | #define MX51_PAD_CSI2_D13__GPIO4_10 (_MX51_PAD_CSI2_D13__GPIO4_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 421 | #define MX51_PAD_CSI2_D13__GPIO4_10 IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1176 | #define MX51_PAD_CSI2_D14__CSI2_D14 (_MX51_PAD_CSI2_D14__CSI2_D14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 422 | #define MX51_PAD_CSI2_D14__CSI2_D14 IOMUX_PAD(0x5c4, 0x1d4, 0, __NA_, 0, NO_PAD_CTRL) |
| 1177 | #define MX51_PAD_CSI2_D15__CSI2_D15 (_MX51_PAD_CSI2_D15__CSI2_D15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 423 | #define MX51_PAD_CSI2_D15__CSI2_D15 IOMUX_PAD(0x5c8, 0x1d8, 0, __NA_, 0, NO_PAD_CTRL) |
| 1178 | #define MX51_PAD_CSI2_D16__CSI2_D16 (_MX51_PAD_CSI2_D16__CSI2_D16 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 424 | #define MX51_PAD_CSI2_D16__CSI2_D16 IOMUX_PAD(0x5cc, 0x1dc, 0, __NA_, 0, NO_PAD_CTRL) |
| 1179 | #define MX51_PAD_CSI2_D17__CSI2_D17 (_MX51_PAD_CSI2_D17__CSI2_D17 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 425 | #define MX51_PAD_CSI2_D17__CSI2_D17 IOMUX_PAD(0x5d0, 0x1e0, 0, __NA_, 0, NO_PAD_CTRL) |
| 1180 | #define MX51_PAD_CSI2_D18__CSI2_D18 (_MX51_PAD_CSI2_D18__CSI2_D18 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 426 | #define MX51_PAD_CSI2_D18__CSI2_D18 IOMUX_PAD(0x5d4, 0x1e4, 0, __NA_, 0, NO_PAD_CTRL) |
| 1181 | #define MX51_PAD_CSI2_D18__GPIO4_11 (_MX51_PAD_CSI2_D18__GPIO4_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 427 | #define MX51_PAD_CSI2_D18__GPIO4_11 IOMUX_PAD(0x5d4, 0x1e4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1182 | #define MX51_PAD_CSI2_D19__CSI2_D19 (_MX51_PAD_CSI2_D19__CSI2_D19 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 428 | #define MX51_PAD_CSI2_D19__CSI2_D19 IOMUX_PAD(0x5d8, 0x1e8, 0, __NA_, 0, NO_PAD_CTRL) |
| 1183 | #define MX51_PAD_CSI2_D19__GPIO4_12 (_MX51_PAD_CSI2_D19__GPIO4_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 429 | #define MX51_PAD_CSI2_D19__GPIO4_12 IOMUX_PAD(0x5d8, 0x1e8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1184 | #define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC (_MX51_PAD_CSI2_VSYNC__CSI2_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 430 | #define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC IOMUX_PAD(0x5dc, 0x1ec, 0, __NA_, 0, NO_PAD_CTRL) |
| 1185 | #define MX51_PAD_CSI2_VSYNC__GPIO4_13 (_MX51_PAD_CSI2_VSYNC__GPIO4_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 431 | #define MX51_PAD_CSI2_VSYNC__GPIO4_13 IOMUX_PAD(0x5dc, 0x1ec, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1186 | #define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC (_MX51_PAD_CSI2_HSYNC__CSI2_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 432 | #define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC IOMUX_PAD(0x5e0, 0x1f0, 0, __NA_, 0, NO_PAD_CTRL) |
| 1187 | #define MX51_PAD_CSI2_HSYNC__GPIO4_14 (_MX51_PAD_CSI2_HSYNC__GPIO4_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 433 | #define MX51_PAD_CSI2_HSYNC__GPIO4_14 IOMUX_PAD(0x5e0, 0x1f0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1188 | #define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK (_MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 434 | #define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK IOMUX_PAD(0x5e4, 0x1f4, 0, __NA_, 0, NO_PAD_CTRL) |
| 1189 | #define MX51_PAD_CSI2_PIXCLK__GPIO4_15 (_MX51_PAD_CSI2_PIXCLK__GPIO4_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 435 | #define MX51_PAD_CSI2_PIXCLK__GPIO4_15 IOMUX_PAD(0x5e4, 0x1f4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1190 | #define MX51_PAD_I2C1_CLK__GPIO4_16 (_MX51_PAD_I2C1_CLK__GPIO4_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 436 | #define MX51_PAD_I2C1_CLK__GPIO4_16 IOMUX_PAD(0x5e8, 0x1f8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1191 | #define MX51_PAD_I2C1_CLK__I2C1_CLK (_MX51_PAD_I2C1_CLK__I2C1_CLK | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | 437 | #define MX51_PAD_I2C1_CLK__I2C1_CLK IOMUX_PAD(0x5e8, 0x1f8, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL) |
| 1192 | #define MX51_PAD_I2C1_DAT__GPIO4_17 (_MX51_PAD_I2C1_DAT__GPIO4_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 438 | #define MX51_PAD_I2C1_DAT__GPIO4_17 IOMUX_PAD(0x5ec, 0x1fc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1193 | #define MX51_PAD_I2C1_DAT__I2C1_DAT (_MX51_PAD_I2C1_DAT__I2C1_DAT | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | 439 | #define MX51_PAD_I2C1_DAT__I2C1_DAT IOMUX_PAD(0x5ec, 0x1fc, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL) |
| 1194 | #define MX51_PAD_AUD3_BB_TXD__AUD3_TXD (_MX51_PAD_AUD3_BB_TXD__AUD3_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 440 | #define MX51_PAD_AUD3_BB_TXD__AUD3_TXD IOMUX_PAD(0x5f0, 0x200, 0, __NA_, 0, NO_PAD_CTRL) |
| 1195 | #define MX51_PAD_AUD3_BB_TXD__GPIO4_18 (_MX51_PAD_AUD3_BB_TXD__GPIO4_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 441 | #define MX51_PAD_AUD3_BB_TXD__GPIO4_18 IOMUX_PAD(0x5f0, 0x200, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1196 | #define MX51_PAD_AUD3_BB_RXD__AUD3_RXD (_MX51_PAD_AUD3_BB_RXD__AUD3_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 442 | #define MX51_PAD_AUD3_BB_RXD__AUD3_RXD IOMUX_PAD(0x5f4, 0x204, 0, __NA_, 0, NO_PAD_CTRL) |
| 1197 | #define MX51_PAD_AUD3_BB_RXD__GPIO4_19 (_MX51_PAD_AUD3_BB_RXD__GPIO4_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 443 | #define MX51_PAD_AUD3_BB_RXD__GPIO4_19 IOMUX_PAD(0x5f4, 0x204, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1198 | #define MX51_PAD_AUD3_BB_RXD__UART3_RXD (_MX51_PAD_AUD3_BB_RXD__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 444 | #define MX51_PAD_AUD3_BB_RXD__UART3_RXD IOMUX_PAD(0x5f4, 0x204, 1, 0x9f4, 2, MX51_UART_PAD_CTRL) |
| 1199 | #define MX51_PAD_AUD3_BB_CK__AUD3_TXC (_MX51_PAD_AUD3_BB_CK__AUD3_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 445 | #define MX51_PAD_AUD3_BB_CK__AUD3_TXC IOMUX_PAD(0x5f8, 0x208, 0, __NA_, 0, NO_PAD_CTRL) |
| 1200 | #define MX51_PAD_AUD3_BB_CK__GPIO4_20 (_MX51_PAD_AUD3_BB_CK__GPIO4_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 446 | #define MX51_PAD_AUD3_BB_CK__GPIO4_20 IOMUX_PAD(0x5f8, 0x208, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1201 | #define MX51_PAD_AUD3_BB_FS__AUD3_TXFS (_MX51_PAD_AUD3_BB_FS__AUD3_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 447 | #define MX51_PAD_AUD3_BB_FS__AUD3_TXFS IOMUX_PAD(0x5fc, 0x20c, 0, __NA_, 0, NO_PAD_CTRL) |
| 1202 | #define MX51_PAD_AUD3_BB_FS__GPIO4_21 (_MX51_PAD_AUD3_BB_FS__GPIO4_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 448 | #define MX51_PAD_AUD3_BB_FS__GPIO4_21 IOMUX_PAD(0x5fc, 0x20c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1203 | #define MX51_PAD_AUD3_BB_FS__UART3_TXD (_MX51_PAD_AUD3_BB_FS__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 449 | #define MX51_PAD_AUD3_BB_FS__UART3_TXD IOMUX_PAD(0x5fc, 0x20c, 1, __NA_, 0, MX51_UART_PAD_CTRL) |
| 1204 | #define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI (_MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 450 | #define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) |
| 1205 | #define MX51_PAD_CSPI1_MOSI__GPIO4_22 (_MX51_PAD_CSPI1_MOSI__GPIO4_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 451 | #define MX51_PAD_CSPI1_MOSI__GPIO4_22 IOMUX_PAD(0x600, 0x210, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1206 | #define MX51_PAD_CSPI1_MOSI__I2C1_SDA (_MX51_PAD_CSPI1_MOSI__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | 452 | #define MX51_PAD_CSPI1_MOSI__I2C1_SDA IOMUX_PAD(0x600, 0x210, 0x11, 0x9b4, 1, MX51_I2C_PAD_CTRL) |
| 1207 | #define MX51_PAD_CSPI1_MISO__AUD4_RXD (_MX51_PAD_CSPI1_MISO__AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 453 | #define MX51_PAD_CSPI1_MISO__AUD4_RXD IOMUX_PAD(0x604, 0x214, 1, 0x8c4, 1, NO_PAD_CTRL) |
| 1208 | #define MX51_PAD_CSPI1_MISO__ECSPI1_MISO (_MX51_PAD_CSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 454 | #define MX51_PAD_CSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) |
| 1209 | #define MX51_PAD_CSPI1_MISO__GPIO4_23 (_MX51_PAD_CSPI1_MISO__GPIO4_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 455 | #define MX51_PAD_CSPI1_MISO__GPIO4_23 IOMUX_PAD(0x604, 0x214, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1210 | #define MX51_PAD_CSPI1_SS0__AUD4_TXC (_MX51_PAD_CSPI1_SS0__AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 456 | #define MX51_PAD_CSPI1_SS0__AUD4_TXC IOMUX_PAD(0x608, 0x218, 1, 0x8cc, 1, NO_PAD_CTRL) |
| 1211 | #define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 (_MX51_PAD_CSPI1_SS0__ECSPI1_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 457 | #define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) |
| 1212 | #define MX51_PAD_CSPI1_SS0__GPIO4_24 (_MX51_PAD_CSPI1_SS0__GPIO4_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 458 | #define MX51_PAD_CSPI1_SS0__GPIO4_24 IOMUX_PAD(0x608, 0x218, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1213 | #define MX51_PAD_CSPI1_SS1__AUD4_TXD (_MX51_PAD_CSPI1_SS1__AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 459 | #define MX51_PAD_CSPI1_SS1__AUD4_TXD IOMUX_PAD(0x60c, 0x21c, 1, 0x8c8, 1, NO_PAD_CTRL) |
| 1214 | #define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 (_MX51_PAD_CSPI1_SS1__ECSPI1_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 460 | #define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 IOMUX_PAD(0x60c, 0x21c, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) |
| 1215 | #define MX51_PAD_CSPI1_SS1__GPIO4_25 (_MX51_PAD_CSPI1_SS1__GPIO4_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 461 | #define MX51_PAD_CSPI1_SS1__GPIO4_25 IOMUX_PAD(0x60c, 0x21c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1216 | #define MX51_PAD_CSPI1_RDY__AUD4_TXFS (_MX51_PAD_CSPI1_RDY__AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 462 | #define MX51_PAD_CSPI1_RDY__AUD4_TXFS IOMUX_PAD(0x610, 0x220, 1, 0x8d0, 1, NO_PAD_CTRL) |
| 1217 | #define MX51_PAD_CSPI1_RDY__ECSPI1_RDY (_MX51_PAD_CSPI1_RDY__ECSPI1_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 463 | #define MX51_PAD_CSPI1_RDY__ECSPI1_RDY IOMUX_PAD(0x610, 0x220, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) |
| 1218 | #define MX51_PAD_CSPI1_RDY__GPIO4_26 (_MX51_PAD_CSPI1_RDY__GPIO4_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 464 | #define MX51_PAD_CSPI1_RDY__GPIO4_26 IOMUX_PAD(0x610, 0x220, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1219 | #define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK (_MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 465 | #define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x614, 0x224, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) |
| 1220 | #define MX51_PAD_CSPI1_SCLK__GPIO4_27 (_MX51_PAD_CSPI1_SCLK__GPIO4_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 466 | #define MX51_PAD_CSPI1_SCLK__GPIO4_27 IOMUX_PAD(0x614, 0x224, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1221 | #define MX51_PAD_CSPI1_SCLK__I2C1_SCL (_MX51_PAD_CSPI1_SCLK__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | 467 | #define MX51_PAD_CSPI1_SCLK__I2C1_SCL IOMUX_PAD(0x614, 0x224, 0x11, 0x9b0, 1, MX51_I2C_PAD_CTRL) |
| 1222 | #define MX51_PAD_UART1_RXD__GPIO4_28 (_MX51_PAD_UART1_RXD__GPIO4_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 468 | #define MX51_PAD_UART1_RXD__GPIO4_28 IOMUX_PAD(0x618, 0x228, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1223 | #define MX51_PAD_UART1_RXD__UART1_RXD (_MX51_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 469 | #define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART_PAD_CTRL) |
| 1224 | #define MX51_PAD_UART1_TXD__GPIO4_29 (_MX51_PAD_UART1_TXD__GPIO4_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 470 | #define MX51_PAD_UART1_TXD__GPIO4_29 IOMUX_PAD(0x61c, 0x22c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1225 | #define MX51_PAD_UART1_TXD__PWM2_PWMO (_MX51_PAD_UART1_TXD__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 471 | #define MX51_PAD_UART1_TXD__PWM2_PWMO IOMUX_PAD(0x61c, 0x22c, 1, __NA_, 0, NO_PAD_CTRL) |
| 1226 | #define MX51_PAD_UART1_TXD__UART1_TXD (_MX51_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 472 | #define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL) |
| 1227 | #define MX51_PAD_UART1_RTS__GPIO4_30 (_MX51_PAD_UART1_RTS__GPIO4_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 473 | #define MX51_PAD_UART1_RTS__GPIO4_30 IOMUX_PAD(0x620, 0x230, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1228 | #define MX51_PAD_UART1_RTS__UART1_RTS (_MX51_PAD_UART1_RTS__UART1_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 474 | #define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL) |
| 1229 | #define MX51_PAD_UART1_CTS__GPIO4_31 (_MX51_PAD_UART1_CTS__GPIO4_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 475 | #define MX51_PAD_UART1_CTS__GPIO4_31 IOMUX_PAD(0x624, 0x234, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1230 | #define MX51_PAD_UART1_CTS__UART1_CTS (_MX51_PAD_UART1_CTS__UART1_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 476 | #define MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL) |
| 1231 | #define MX51_PAD_UART2_RXD__FIRI_TXD (_MX51_PAD_UART2_RXD__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 477 | #define MX51_PAD_UART2_RXD__FIRI_TXD IOMUX_PAD(0x628, 0x238, 1, __NA_, 0, NO_PAD_CTRL) |
| 1232 | #define MX51_PAD_UART2_RXD__GPIO1_20 (_MX51_PAD_UART2_RXD__GPIO1_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 478 | #define MX51_PAD_UART2_RXD__GPIO1_20 IOMUX_PAD(0x628, 0x238, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1233 | #define MX51_PAD_UART2_RXD__UART2_RXD (_MX51_PAD_UART2_RXD__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 479 | #define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART_PAD_CTRL) |
| 1234 | #define MX51_PAD_UART2_TXD__FIRI_RXD (_MX51_PAD_UART2_TXD__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 480 | #define MX51_PAD_UART2_TXD__FIRI_RXD IOMUX_PAD(0x62c, 0x23c, 1, __NA_, 0, NO_PAD_CTRL) |
| 1235 | #define MX51_PAD_UART2_TXD__GPIO1_21 (_MX51_PAD_UART2_TXD__GPIO1_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 481 | #define MX51_PAD_UART2_TXD__GPIO1_21 IOMUX_PAD(0x62c, 0x23c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1236 | #define MX51_PAD_UART2_TXD__UART2_TXD (_MX51_PAD_UART2_TXD__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 482 | #define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62c, 0x23c, 0, __NA_, 0, MX51_UART_PAD_CTRL) |
| 1237 | #define MX51_PAD_UART3_RXD__CSI1_D0 (_MX51_PAD_UART3_RXD__CSI1_D0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 483 | #define MX51_PAD_UART3_RXD__CSI1_D0 IOMUX_PAD(0x630, 0x240, 2, __NA_, 0, NO_PAD_CTRL) |
| 1238 | #define MX51_PAD_UART3_RXD__GPIO1_22 (_MX51_PAD_UART3_RXD__GPIO1_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 484 | #define MX51_PAD_UART3_RXD__GPIO1_22 IOMUX_PAD(0x630, 0x240, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1239 | #define MX51_PAD_UART3_RXD__UART1_DTR (_MX51_PAD_UART3_RXD__UART1_DTR | MUX_PAD_CTRL(NO_PAD_CTRL)) | 485 | #define MX51_PAD_UART3_RXD__UART1_DTR IOMUX_PAD(0x630, 0x240, 0, __NA_, 0, NO_PAD_CTRL) |
| 1240 | #define MX51_PAD_UART3_RXD__UART3_RXD (_MX51_PAD_UART3_RXD__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 486 | #define MX51_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART_PAD_CTRL) |
| 1241 | #define MX51_PAD_UART3_TXD__CSI1_D1 (_MX51_PAD_UART3_TXD__CSI1_D1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 487 | #define MX51_PAD_UART3_TXD__CSI1_D1 IOMUX_PAD(0x634, 0x244, 2, __NA_, 0, NO_PAD_CTRL) |
| 1242 | #define MX51_PAD_UART3_TXD__GPIO1_23 (_MX51_PAD_UART3_TXD__GPIO1_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 488 | #define MX51_PAD_UART3_TXD__GPIO1_23 IOMUX_PAD(0x634, 0x244, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1243 | #define MX51_PAD_UART3_TXD__UART1_DSR (_MX51_PAD_UART3_TXD__UART1_DSR | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 489 | #define MX51_PAD_UART3_TXD__UART1_DSR IOMUX_PAD(0x634, 0x244, 0, __NA_, 0, MX51_UART_PAD_CTRL) |
| 1244 | #define MX51_PAD_UART3_TXD__UART3_TXD (_MX51_PAD_UART3_TXD__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 490 | #define MX51_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x634, 0x244, 1, __NA_, 0, MX51_UART_PAD_CTRL) |
| 1245 | #define MX51_PAD_OWIRE_LINE__GPIO1_24 (_MX51_PAD_OWIRE_LINE__GPIO1_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 491 | #define MX51_PAD_OWIRE_LINE__GPIO1_24 IOMUX_PAD(0x638, 0x248, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1246 | #define MX51_PAD_OWIRE_LINE__OWIRE_LINE (_MX51_PAD_OWIRE_LINE__OWIRE_LINE | MUX_PAD_CTRL(NO_PAD_CTRL)) | 492 | #define MX51_PAD_OWIRE_LINE__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 0, __NA_, 0, NO_PAD_CTRL) |
| 1247 | #define MX51_PAD_OWIRE_LINE__SPDIF_OUT (_MX51_PAD_OWIRE_LINE__SPDIF_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) | 493 | #define MX51_PAD_OWIRE_LINE__SPDIF_OUT IOMUX_PAD(0x638, 0x248, 6, __NA_, 0, NO_PAD_CTRL) |
| 1248 | #define MX51_PAD_KEY_ROW0__KEY_ROW0 (_MX51_PAD_KEY_ROW0__KEY_ROW0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 494 | #define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63c, 0x24c, 0, __NA_, 0, NO_PAD_CTRL) |
| 1249 | #define MX51_PAD_KEY_ROW1__KEY_ROW1 (_MX51_PAD_KEY_ROW1__KEY_ROW1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 495 | #define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, __NA_, 0, NO_PAD_CTRL) |
| 1250 | #define MX51_PAD_KEY_ROW2__KEY_ROW2 (_MX51_PAD_KEY_ROW2__KEY_ROW2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 496 | #define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, __NA_, 0, NO_PAD_CTRL) |
| 1251 | #define MX51_PAD_KEY_ROW3__KEY_ROW3 (_MX51_PAD_KEY_ROW3__KEY_ROW3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 497 | #define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, __NA_, 0, NO_PAD_CTRL) |
| 1252 | #define MX51_PAD_KEY_COL0__KEY_COL0 (_MX51_PAD_KEY_COL0__KEY_COL0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 498 | #define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64c, 0x25c, 0, __NA_, 0, NO_PAD_CTRL) |
| 1253 | #define MX51_PAD_KEY_COL0__PLL1_BYP (_MX51_PAD_KEY_COL0__PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) | 499 | #define MX51_PAD_KEY_COL0__PLL1_BYP IOMUX_PAD(0x64c, 0x25c, 7, 0x90c, 0, NO_PAD_CTRL) |
| 1254 | #define MX51_PAD_KEY_COL1__KEY_COL1 (_MX51_PAD_KEY_COL1__KEY_COL1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 500 | #define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, __NA_, 0, NO_PAD_CTRL) |
| 1255 | #define MX51_PAD_KEY_COL1__PLL2_BYP (_MX51_PAD_KEY_COL1__PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) | 501 | #define MX51_PAD_KEY_COL1__PLL2_BYP IOMUX_PAD(0x650, 0x260, 7, 0x910, 0, NO_PAD_CTRL) |
| 1256 | #define MX51_PAD_KEY_COL2__KEY_COL2 (_MX51_PAD_KEY_COL2__KEY_COL2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 502 | #define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, __NA_, 0, NO_PAD_CTRL) |
| 1257 | #define MX51_PAD_KEY_COL2__PLL3_BYP (_MX51_PAD_KEY_COL2__PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) | 503 | #define MX51_PAD_KEY_COL2__PLL3_BYP IOMUX_PAD(0x654, 0x264, 7, __NA_, 0, NO_PAD_CTRL) |
| 1258 | #define MX51_PAD_KEY_COL3__KEY_COL3 (_MX51_PAD_KEY_COL3__KEY_COL3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 504 | #define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, __NA_, 0, NO_PAD_CTRL) |
| 1259 | #define MX51_PAD_KEY_COL4__I2C2_SCL (_MX51_PAD_KEY_COL4__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | 505 | #define MX51_PAD_KEY_COL4__I2C2_SCL IOMUX_PAD(0x65c, 0x26c, 0x13, 0x9b8, 1, MX51_I2C_PAD_CTRL) |
| 1260 | #define MX51_PAD_KEY_COL4__KEY_COL4 (_MX51_PAD_KEY_COL4__KEY_COL4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 506 | #define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65c, 0x26c, 0, __NA_, 0, NO_PAD_CTRL) |
| 1261 | #define MX51_PAD_KEY_COL4__SPDIF_OUT1 (_MX51_PAD_KEY_COL4__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 507 | #define MX51_PAD_KEY_COL4__SPDIF_OUT1 IOMUX_PAD(0x65c, 0x26c, 6, __NA_, 0, NO_PAD_CTRL) |
| 1262 | #define MX51_PAD_KEY_COL4__UART1_RI (_MX51_PAD_KEY_COL4__UART1_RI | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 508 | #define MX51_PAD_KEY_COL4__UART1_RI IOMUX_PAD(0x65c, 0x26c, 1, __NA_, 0, MX51_UART_PAD_CTRL) |
| 1263 | #define MX51_PAD_KEY_COL4__UART3_RTS (_MX51_PAD_KEY_COL4__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 509 | #define MX51_PAD_KEY_COL4__UART3_RTS IOMUX_PAD(0x65c, 0x26c, 2, 0x9f0, 4, MX51_UART_PAD_CTRL) |
| 1264 | #define MX51_PAD_KEY_COL5__I2C2_SDA (_MX51_PAD_KEY_COL5__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | 510 | #define MX51_PAD_KEY_COL5__I2C2_SDA IOMUX_PAD(0x660, 0x270, 0x13, 0x9bc, 1, MX51_I2C_PAD_CTRL) |
| 1265 | #define MX51_PAD_KEY_COL5__KEY_COL5 (_MX51_PAD_KEY_COL5__KEY_COL5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 511 | #define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, __NA_, 0, NO_PAD_CTRL) |
| 1266 | #define MX51_PAD_KEY_COL5__UART1_DCD (_MX51_PAD_KEY_COL5__UART1_DCD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 512 | #define MX51_PAD_KEY_COL5__UART1_DCD IOMUX_PAD(0x660, 0x270, 1, __NA_, 0, MX51_UART_PAD_CTRL) |
| 1267 | #define MX51_PAD_KEY_COL5__UART3_CTS (_MX51_PAD_KEY_COL5__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 513 | #define MX51_PAD_KEY_COL5__UART3_CTS IOMUX_PAD(0x660, 0x270, 2, __NA_, 0, MX51_UART_PAD_CTRL) |
| 1268 | #define MX51_PAD_USBH1_CLK__CSPI_SCLK (_MX51_PAD_USBH1_CLK__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 514 | #define MX51_PAD_USBH1_CLK__CSPI_SCLK IOMUX_PAD(0x678, 0x278, 1, 0x914, 1, MX51_ECSPI_PAD_CTRL) |
| 1269 | #define MX51_PAD_USBH1_CLK__GPIO1_25 (_MX51_PAD_USBH1_CLK__GPIO1_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 515 | #define MX51_PAD_USBH1_CLK__GPIO1_25 IOMUX_PAD(0x678, 0x278, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1270 | #define MX51_PAD_USBH1_CLK__I2C2_SCL (_MX51_PAD_USBH1_CLK__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | 516 | #define MX51_PAD_USBH1_CLK__I2C2_SCL IOMUX_PAD(0x678, 0x278, 0x15, 0x9b8, 2, MX51_I2C_PAD_CTRL) |
| 1271 | #define MX51_PAD_USBH1_CLK__USBH1_CLK (_MX51_PAD_USBH1_CLK__USBH1_CLK | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) | 517 | #define MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) |
| 1272 | #define MX51_PAD_USBH1_DIR__CSPI_MOSI (_MX51_PAD_USBH1_DIR__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 518 | #define MX51_PAD_USBH1_DIR__CSPI_MOSI IOMUX_PAD(0x67c, 0x27c, 1, 0x91c, 1, MX51_ECSPI_PAD_CTRL) |
| 1273 | #define MX51_PAD_USBH1_DIR__GPIO1_26 (_MX51_PAD_USBH1_DIR__GPIO1_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 519 | #define MX51_PAD_USBH1_DIR__GPIO1_26 IOMUX_PAD(0x67c, 0x27c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1274 | #define MX51_PAD_USBH1_DIR__I2C2_SDA (_MX51_PAD_USBH1_DIR__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | 520 | #define MX51_PAD_USBH1_DIR__I2C2_SDA IOMUX_PAD(0x67c, 0x27c, 0x15, 0x9bc, 2, MX51_I2C_PAD_CTRL) |
| 1275 | #define MX51_PAD_USBH1_DIR__USBH1_DIR (_MX51_PAD_USBH1_DIR__USBH1_DIR | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) | 521 | #define MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) |
| 1276 | #define MX51_PAD_USBH1_STP__CSPI_RDY (_MX51_PAD_USBH1_STP__CSPI_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 522 | #define MX51_PAD_USBH1_STP__CSPI_RDY IOMUX_PAD(0x680, 0x280, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL) |
| 1277 | #define MX51_PAD_USBH1_STP__GPIO1_27 (_MX51_PAD_USBH1_STP__GPIO1_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 523 | #define MX51_PAD_USBH1_STP__GPIO1_27 IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1278 | #define MX51_PAD_USBH1_STP__UART3_RXD (_MX51_PAD_USBH1_STP__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 524 | #define MX51_PAD_USBH1_STP__UART3_RXD IOMUX_PAD(0x680, 0x280, 5, 0x9f4, 6, MX51_UART_PAD_CTRL) |
| 1279 | #define MX51_PAD_USBH1_STP__USBH1_STP (_MX51_PAD_USBH1_STP__USBH1_STP | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) | 525 | #define MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) |
| 1280 | #define MX51_PAD_USBH1_NXT__CSPI_MISO (_MX51_PAD_USBH1_NXT__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 526 | #define MX51_PAD_USBH1_NXT__CSPI_MISO IOMUX_PAD(0x684, 0x284, 1, 0x918, 0, MX51_ECSPI_PAD_CTRL) |
| 1281 | #define MX51_PAD_USBH1_NXT__GPIO1_28 (_MX51_PAD_USBH1_NXT__GPIO1_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 527 | #define MX51_PAD_USBH1_NXT__GPIO1_28 IOMUX_PAD(0x684, 0x284, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1282 | #define MX51_PAD_USBH1_NXT__UART3_TXD (_MX51_PAD_USBH1_NXT__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 528 | #define MX51_PAD_USBH1_NXT__UART3_TXD IOMUX_PAD(0x684, 0x284, 5, __NA_, 0, MX51_UART_PAD_CTRL) |
| 1283 | #define MX51_PAD_USBH1_NXT__USBH1_NXT (_MX51_PAD_USBH1_NXT__USBH1_NXT | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) | 529 | #define MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) |
| 1284 | #define MX51_PAD_USBH1_DATA0__GPIO1_11 (_MX51_PAD_USBH1_DATA0__GPIO1_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 530 | #define MX51_PAD_USBH1_DATA0__GPIO1_11 IOMUX_PAD(0x688, 0x288, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1285 | #define MX51_PAD_USBH1_DATA0__UART2_CTS (_MX51_PAD_USBH1_DATA0__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 531 | #define MX51_PAD_USBH1_DATA0__UART2_CTS IOMUX_PAD(0x688, 0x288, 1, __NA_, 0, MX51_UART_PAD_CTRL) |
| 1286 | #define MX51_PAD_USBH1_DATA0__USBH1_DATA0 (_MX51_PAD_USBH1_DATA0__USBH1_DATA0 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) | 532 | #define MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) |
| 1287 | #define MX51_PAD_USBH1_DATA1__GPIO1_12 (_MX51_PAD_USBH1_DATA1__GPIO1_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 533 | #define MX51_PAD_USBH1_DATA1__GPIO1_12 IOMUX_PAD(0x68c, 0x28c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1288 | #define MX51_PAD_USBH1_DATA1__UART2_RXD (_MX51_PAD_USBH1_DATA1__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 534 | #define MX51_PAD_USBH1_DATA1__UART2_RXD IOMUX_PAD(0x68c, 0x28c, 1, 0x9ec, 4, MX51_UART_PAD_CTRL) |
| 1289 | #define MX51_PAD_USBH1_DATA1__USBH1_DATA1 (_MX51_PAD_USBH1_DATA1__USBH1_DATA1 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) | 535 | #define MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) |
| 1290 | #define MX51_PAD_USBH1_DATA2__GPIO1_13 (_MX51_PAD_USBH1_DATA2__GPIO1_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 536 | #define MX51_PAD_USBH1_DATA2__GPIO1_13 IOMUX_PAD(0x690, 0x290, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1291 | #define MX51_PAD_USBH1_DATA2__UART2_TXD (_MX51_PAD_USBH1_DATA2__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 537 | #define MX51_PAD_USBH1_DATA2__UART2_TXD IOMUX_PAD(0x690, 0x290, 1, __NA_, 0, MX51_UART_PAD_CTRL) |
| 1292 | #define MX51_PAD_USBH1_DATA2__USBH1_DATA2 (_MX51_PAD_USBH1_DATA2__USBH1_DATA2 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) | 538 | #define MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) |
| 1293 | #define MX51_PAD_USBH1_DATA3__GPIO1_14 (_MX51_PAD_USBH1_DATA3__GPIO1_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 539 | #define MX51_PAD_USBH1_DATA3__GPIO1_14 IOMUX_PAD(0x694, 0x294, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1294 | #define MX51_PAD_USBH1_DATA3__UART2_RTS (_MX51_PAD_USBH1_DATA3__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 540 | #define MX51_PAD_USBH1_DATA3__UART2_RTS IOMUX_PAD(0x694, 0x294, 1, 0x9e8, 5, MX51_UART_PAD_CTRL) |
| 1295 | #define MX51_PAD_USBH1_DATA3__USBH1_DATA3 (_MX51_PAD_USBH1_DATA3__USBH1_DATA3 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) | 541 | #define MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) |
| 1296 | #define MX51_PAD_USBH1_DATA4__CSPI_SS0 (_MX51_PAD_USBH1_DATA4__CSPI_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 542 | #define MX51_PAD_USBH1_DATA4__CSPI_SS0 IOMUX_PAD(0x698, 0x298, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL) |
| 1297 | #define MX51_PAD_USBH1_DATA4__GPIO1_15 (_MX51_PAD_USBH1_DATA4__GPIO1_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 543 | #define MX51_PAD_USBH1_DATA4__GPIO1_15 IOMUX_PAD(0x698, 0x298, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1298 | #define MX51_PAD_USBH1_DATA4__USBH1_DATA4 (_MX51_PAD_USBH1_DATA4__USBH1_DATA4 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) | 544 | #define MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) |
| 1299 | #define MX51_PAD_USBH1_DATA5__CSPI_SS1 (_MX51_PAD_USBH1_DATA5__CSPI_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 545 | #define MX51_PAD_USBH1_DATA5__CSPI_SS1 IOMUX_PAD(0x69c, 0x29c, 1, 0x920, 0, MX51_ECSPI_PAD_CTRL) |
| 1300 | #define MX51_PAD_USBH1_DATA5__GPIO1_16 (_MX51_PAD_USBH1_DATA5__GPIO1_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 546 | #define MX51_PAD_USBH1_DATA5__GPIO1_16 IOMUX_PAD(0x69c, 0x29c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1301 | #define MX51_PAD_USBH1_DATA5__USBH1_DATA5 (_MX51_PAD_USBH1_DATA5__USBH1_DATA5 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) | 547 | #define MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) |
| 1302 | #define MX51_PAD_USBH1_DATA6__CSPI_SS3 (_MX51_PAD_USBH1_DATA6__CSPI_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 548 | #define MX51_PAD_USBH1_DATA6__CSPI_SS3 IOMUX_PAD(0x6a0, 0x2a0, 1, 0x928, 1, MX51_ECSPI_PAD_CTRL) |
| 1303 | #define MX51_PAD_USBH1_DATA6__GPIO1_17 (_MX51_PAD_USBH1_DATA6__GPIO1_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 549 | #define MX51_PAD_USBH1_DATA6__GPIO1_17 IOMUX_PAD(0x6a0, 0x2a0, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1304 | #define MX51_PAD_USBH1_DATA6__USBH1_DATA6 (_MX51_PAD_USBH1_DATA6__USBH1_DATA6 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) | 550 | #define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) |
| 1305 | #define MX51_PAD_USBH1_DATA7__ECSPI1_SS3 (_MX51_PAD_USBH1_DATA7__ECSPI1_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 551 | #define MX51_PAD_USBH1_DATA7__ECSPI1_SS3 IOMUX_PAD(0x6a4, 0x2a4, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL) |
| 1306 | #define MX51_PAD_USBH1_DATA7__ECSPI2_SS3 (_MX51_PAD_USBH1_DATA7__ECSPI2_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 552 | #define MX51_PAD_USBH1_DATA7__ECSPI2_SS3 IOMUX_PAD(0x6a4, 0x2a4, 5, 0x934, 1, MX51_ECSPI_PAD_CTRL) |
| 1307 | #define MX51_PAD_USBH1_DATA7__GPIO1_18 (_MX51_PAD_USBH1_DATA7__GPIO1_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 553 | #define MX51_PAD_USBH1_DATA7__GPIO1_18 IOMUX_PAD(0x6a4, 0x2a4, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1308 | #define MX51_PAD_USBH1_DATA7__USBH1_DATA7 (_MX51_PAD_USBH1_DATA7__USBH1_DATA7 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL)) | 554 | #define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) |
| 1309 | #define MX51_PAD_DI1_PIN11__DI1_PIN11 (_MX51_PAD_DI1_PIN11__DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 555 | #define MX51_PAD_DI1_PIN11__DI1_PIN11 IOMUX_PAD(0x6a8, 0x2a8, 0, __NA_, 0, NO_PAD_CTRL) |
| 1310 | #define MX51_PAD_DI1_PIN11__ECSPI1_SS2 (_MX51_PAD_DI1_PIN11__ECSPI1_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 556 | #define MX51_PAD_DI1_PIN11__ECSPI1_SS2 IOMUX_PAD(0x6a8, 0x2a8, 7, __NA_, 0, MX51_ECSPI_PAD_CTRL) |
| 1311 | #define MX51_PAD_DI1_PIN11__GPIO3_0 (_MX51_PAD_DI1_PIN11__GPIO3_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 557 | #define MX51_PAD_DI1_PIN11__GPIO3_0 IOMUX_PAD(0x6a8, 0x2a8, 4, __NA_, 0, MX51_GPIO_PAD_CTRL) |
| 1312 | #define MX51_PAD_DI1_PIN12__DI1_PIN12 (_MX51_PAD_DI1_PIN12__DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 558 | #define MX51_PAD_DI1_PIN12__DI1_PIN12 IOMUX_PAD(0x6ac, 0x2ac, 0, __NA_, 0, NO_PAD_CTRL) |
| 1313 | #define MX51_PAD_DI1_PIN12__GPIO3_1 (_MX51_PAD_DI1_PIN12__GPIO3_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 559 | #define MX51_PAD_DI1_PIN12__GPIO3_1 IOMUX_PAD(0x6ac, 0x2ac, 4, 0x978, 1, MX51_GPIO_PAD_CTRL) |
| 1314 | #define MX51_PAD_DI1_PIN13__DI1_PIN13 (_MX51_PAD_DI1_PIN13__DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 560 | #define MX51_PAD_DI1_PIN13__DI1_PIN13 IOMUX_PAD(0x6b0, 0x2b0, 0, __NA_, 0, NO_PAD_CTRL) |
| 1315 | #define MX51_PAD_DI1_PIN13__GPIO3_2 (_MX51_PAD_DI1_PIN13__GPIO3_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 561 | #define MX51_PAD_DI1_PIN13__GPIO3_2 IOMUX_PAD(0x6b0, 0x2b0, 4, 0x97c, 1, MX51_GPIO_PAD_CTRL) |
| 1316 | #define MX51_PAD_DI1_D0_CS__DI1_D0_CS (_MX51_PAD_DI1_D0_CS__DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 562 | #define MX51_PAD_DI1_D0_CS__DI1_D0_CS IOMUX_PAD(0x6b4, 0x2b4, 0, __NA_, 0, NO_PAD_CTRL) |
| 1317 | #define MX51_PAD_DI1_D0_CS__GPIO3_3 (_MX51_PAD_DI1_D0_CS__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 563 | #define MX51_PAD_DI1_D0_CS__GPIO3_3 IOMUX_PAD(0x6b4, 0x2b4, 4, 0x980, 1, MX51_GPIO_PAD_CTRL) |
| 1318 | #define MX51_PAD_DI1_D1_CS__DI1_D1_CS (_MX51_PAD_DI1_D1_CS__DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 564 | #define MX51_PAD_DI1_D1_CS__DI1_D1_CS IOMUX_PAD(0x6b8, 0x2b8, 0, __NA_, 0, NO_PAD_CTRL) |
| 1319 | #define MX51_PAD_DI1_D1_CS__DISP1_PIN14 (_MX51_PAD_DI1_D1_CS__DISP1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 565 | #define MX51_PAD_DI1_D1_CS__DISP1_PIN14 IOMUX_PAD(0x6b8, 0x2b8, 2, __NA_, 0, NO_PAD_CTRL) |
| 1320 | #define MX51_PAD_DI1_D1_CS__DISP1_PIN5 (_MX51_PAD_DI1_D1_CS__DISP1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 566 | #define MX51_PAD_DI1_D1_CS__DISP1_PIN5 IOMUX_PAD(0x6b8, 0x2b8, 3, __NA_, 0, NO_PAD_CTRL) |
| 1321 | #define MX51_PAD_DI1_D1_CS__GPIO3_4 (_MX51_PAD_DI1_D1_CS__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 567 | #define MX51_PAD_DI1_D1_CS__GPIO3_4 IOMUX_PAD(0x6b8, 0x2b8, 4, 0x984, 1, MX51_GPIO_PAD_CTRL) |
| 1322 | #define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 (_MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 568 | #define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 IOMUX_PAD(0x6bc, 0x2bc, 2, 0x9a4, 1, NO_PAD_CTRL) |
| 1323 | #define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN (_MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL)) | 569 | #define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN IOMUX_PAD(0x6bc, 0x2bc, 0, 0x9c4, 0, NO_PAD_CTRL) |
| 1324 | #define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 (_MX51_PAD_DISPB2_SER_DIN__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 570 | #define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 IOMUX_PAD(0x6bc, 0x2bc, 4, 0x988, 1, MX51_GPIO_PAD_CTRL) |
| 1325 | #define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 (_MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 571 | #define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 IOMUX_PAD(0x6c0, 0x2c0, 3, __NA_, 0, NO_PAD_CTRL) |
| 1326 | #define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO (_MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 572 | #define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO IOMUX_PAD(0x6c0, 0x2c0, 0, 0x9c4, 1, NO_PAD_CTRL) |
| 1327 | #define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 (_MX51_PAD_DISPB2_SER_DIO__GPIO3_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 573 | #define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL) |
| 1328 | #define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 (_MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 574 | #define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 IOMUX_PAD(0x6c4, 0x2c4, 2, __NA_, 0, NO_PAD_CTRL) |
| 1329 | #define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 (_MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 575 | #define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 IOMUX_PAD(0x6c4, 0x2c4, 3, __NA_, 0, NO_PAD_CTRL) |
| 1330 | #define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK (_MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 576 | #define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK IOMUX_PAD(0x6c4, 0x2c4, 0, __NA_, 0, NO_PAD_CTRL) |
| 1331 | #define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 (_MX51_PAD_DISPB2_SER_CLK__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 577 | #define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 IOMUX_PAD(0x6c4, 0x2c4, 4, 0x990, 1, MX51_GPIO_PAD_CTRL) |
| 1332 | #define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK (_MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 578 | #define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL) |
| 1333 | #define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 (_MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 579 | #define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL) |
| 1334 | #define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 (_MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 580 | #define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 IOMUX_PAD(0x6c8, 0x2c8, 3, __NA_, 0, NO_PAD_CTRL) |
| 1335 | #define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS (_MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 581 | #define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL) |
| 1336 | #define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS (_MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 582 | #define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL) |
| 1337 | #define MX51_PAD_DISPB2_SER_RS__GPIO3_8 (_MX51_PAD_DISPB2_SER_RS__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) | 583 | #define MX51_PAD_DISPB2_SER_RS__GPIO3_8 IOMUX_PAD(0x6c8, 0x2c8, 4, 0x994, 1, MX51_GPIO_PAD_CTRL) |
| 1338 | #define MX51_PAD_DISP1_DAT0__DISP1_DAT0 (_MX51_PAD_DISP1_DAT0__DISP1_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 584 | #define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6cc, 0x2cc, 0, __NA_, 0, NO_PAD_CTRL) |
| 1339 | #define MX51_PAD_DISP1_DAT1__DISP1_DAT1 (_MX51_PAD_DISP1_DAT1__DISP1_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 585 | #define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6d0, 0x2d0, 0, __NA_, 0, NO_PAD_CTRL) |
| 1340 | #define MX51_PAD_DISP1_DAT2__DISP1_DAT2 (_MX51_PAD_DISP1_DAT2__DISP1_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 586 | #define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6d4, 0x2d4, 0, __NA_, 0, NO_PAD_CTRL) |
| 1341 | #define MX51_PAD_DISP1_DAT3__DISP1_DAT3 (_MX51_PAD_DISP1_DAT3__DISP1_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 587 | #define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6d8, 0x2d8, 0, __NA_, 0, NO_PAD_CTRL) |
| 1342 | #define MX51_PAD_DISP1_DAT4__DISP1_DAT4 (_MX51_PAD_DISP1_DAT4__DISP1_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 588 | #define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6dc, 0x2dc, 0, __NA_, 0, NO_PAD_CTRL) |
| 1343 | #define MX51_PAD_DISP1_DAT5__DISP1_DAT5 (_MX51_PAD_DISP1_DAT5__DISP1_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 589 | #define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6e0, 0x2e0, 0, __NA_, 0, NO_PAD_CTRL) |
| 1344 | #define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC (_MX51_PAD_DISP1_DAT6__BOOT_USB_SRC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 590 | #define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC IOMUX_PAD(0x6e4, 0x2e4, 7, __NA_, 0, NO_PAD_CTRL) |
| 1345 | #define MX51_PAD_DISP1_DAT6__DISP1_DAT6 (_MX51_PAD_DISP1_DAT6__DISP1_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 591 | #define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6e4, 0x2e4, 0, __NA_, 0, NO_PAD_CTRL) |
| 1346 | #define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG (_MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG | MUX_PAD_CTRL(NO_PAD_CTRL)) | 592 | #define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG IOMUX_PAD(0x6e8, 0x2e8, 7, __NA_, 0, NO_PAD_CTRL) |
| 1347 | #define MX51_PAD_DISP1_DAT7__DISP1_DAT7 (_MX51_PAD_DISP1_DAT7__DISP1_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 593 | #define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6e8, 0x2e8, 0, __NA_, 0, NO_PAD_CTRL) |
| 1348 | #define MX51_PAD_DISP1_DAT8__BOOT_SRC0 (_MX51_PAD_DISP1_DAT8__BOOT_SRC0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 594 | #define MX51_PAD_DISP1_DAT8__BOOT_SRC0 IOMUX_PAD(0x6ec, 0x2ec, 7, __NA_, 0, NO_PAD_CTRL) |
| 1349 | #define MX51_PAD_DISP1_DAT8__DISP1_DAT8 (_MX51_PAD_DISP1_DAT8__DISP1_DAT8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 595 | #define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6ec, 0x2ec, 0, __NA_, 0, NO_PAD_CTRL) |
| 1350 | #define MX51_PAD_DISP1_DAT9__BOOT_SRC1 (_MX51_PAD_DISP1_DAT9__BOOT_SRC1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 596 | #define MX51_PAD_DISP1_DAT9__BOOT_SRC1 IOMUX_PAD(0x6f0, 0x2f0, 7, __NA_, 0, NO_PAD_CTRL) |
| 1351 | #define MX51_PAD_DISP1_DAT9__DISP1_DAT9 (_MX51_PAD_DISP1_DAT9__DISP1_DAT9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 597 | #define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6f0, 0x2f0, 0, __NA_, 0, NO_PAD_CTRL) |
| 1352 | #define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE (_MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE | MUX_PAD_CTRL(NO_PAD_CTRL)) | 598 | #define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE IOMUX_PAD(0x6f4, 0x2f4, 7, __NA_, 0, NO_PAD_CTRL) |
| 1353 | #define MX51_PAD_DISP1_DAT10__DISP1_DAT10 (_MX51_PAD_DISP1_DAT10__DISP1_DAT10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 599 | #define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6f4, 0x2f4, 0, __NA_, 0, NO_PAD_CTRL) |
| 1354 | #define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 (_MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 600 | #define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 IOMUX_PAD(0x6f8, 0x2f8, 7, __NA_, 0, NO_PAD_CTRL) |
| 1355 | #define MX51_PAD_DISP1_DAT11__DISP1_DAT11 (_MX51_PAD_DISP1_DAT11__DISP1_DAT11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 601 | #define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6f8, 0x2f8, 0, __NA_, 0, NO_PAD_CTRL) |
| 1356 | #define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL (_MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL | MUX_PAD_CTRL(NO_PAD_CTRL)) | 602 | #define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL IOMUX_PAD(0x6fc, 0x2fc, 7, __NA_, 0, NO_PAD_CTRL) |
| 1357 | #define MX51_PAD_DISP1_DAT12__DISP1_DAT12 (_MX51_PAD_DISP1_DAT12__DISP1_DAT12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 603 | #define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6fc, 0x2fc, 0, __NA_, 0, NO_PAD_CTRL) |
| 1358 | #define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 (_MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 604 | #define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 IOMUX_PAD(0x700, 0x300, 7, __NA_, 0, NO_PAD_CTRL) |
| 1359 | #define MX51_PAD_DISP1_DAT13__DISP1_DAT13 (_MX51_PAD_DISP1_DAT13__DISP1_DAT13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 605 | #define MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, __NA_, 0, NO_PAD_CTRL) |
| 1360 | #define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 (_MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 606 | #define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 IOMUX_PAD(0x704, 0x304, 7, __NA_, 0, NO_PAD_CTRL) |
| 1361 | #define MX51_PAD_DISP1_DAT14__DISP1_DAT14 (_MX51_PAD_DISP1_DAT14__DISP1_DAT14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 607 | #define MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, __NA_, 0, NO_PAD_CTRL) |
| 1362 | #define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH (_MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH | MUX_PAD_CTRL(NO_PAD_CTRL)) | 608 | #define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH IOMUX_PAD(0x708, 0x308, 7, __NA_, 0, NO_PAD_CTRL) |
| 1363 | #define MX51_PAD_DISP1_DAT15__DISP1_DAT15 (_MX51_PAD_DISP1_DAT15__DISP1_DAT15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 609 | #define MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, __NA_, 0, NO_PAD_CTRL) |
| 1364 | #define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 (_MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 610 | #define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 IOMUX_PAD(0x70c, 0x30c, 7, __NA_, 0, NO_PAD_CTRL) |
| 1365 | #define MX51_PAD_DISP1_DAT16__DISP1_DAT16 (_MX51_PAD_DISP1_DAT16__DISP1_DAT16 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 611 | #define MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70c, 0x30c, 0, __NA_, 0, NO_PAD_CTRL) |
| 1366 | #define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 (_MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 612 | #define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 IOMUX_PAD(0x710, 0x310, 7, __NA_, 0, NO_PAD_CTRL) |
| 1367 | #define MX51_PAD_DISP1_DAT17__DISP1_DAT17 (_MX51_PAD_DISP1_DAT17__DISP1_DAT17 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 613 | #define MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, __NA_, 0, NO_PAD_CTRL) |
| 1368 | #define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 (_MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 614 | #define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 IOMUX_PAD(0x714, 0x314, 7, __NA_, 0, NO_PAD_CTRL) |
| 1369 | #define MX51_PAD_DISP1_DAT18__DISP1_DAT18 (_MX51_PAD_DISP1_DAT18__DISP1_DAT18 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 615 | #define MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, __NA_, 0, NO_PAD_CTRL) |
| 1370 | #define MX51_PAD_DISP1_DAT18__DISP2_PIN11 (_MX51_PAD_DISP1_DAT18__DISP2_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 616 | #define MX51_PAD_DISP1_DAT18__DISP2_PIN11 IOMUX_PAD(0x714, 0x314, 5, __NA_, 0, NO_PAD_CTRL) |
| 1371 | #define MX51_PAD_DISP1_DAT18__DISP2_PIN5 (_MX51_PAD_DISP1_DAT18__DISP2_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 617 | #define MX51_PAD_DISP1_DAT18__DISP2_PIN5 IOMUX_PAD(0x714, 0x314, 4, __NA_, 0, NO_PAD_CTRL) |
| 1372 | #define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 (_MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 618 | #define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 IOMUX_PAD(0x718, 0x318, 7, __NA_, 0, NO_PAD_CTRL) |
| 1373 | #define MX51_PAD_DISP1_DAT19__DISP1_DAT19 (_MX51_PAD_DISP1_DAT19__DISP1_DAT19 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 619 | #define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, __NA_, 0, NO_PAD_CTRL) |
| 1374 | #define MX51_PAD_DISP1_DAT19__DISP2_PIN12 (_MX51_PAD_DISP1_DAT19__DISP2_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 620 | #define MX51_PAD_DISP1_DAT19__DISP2_PIN12 IOMUX_PAD(0x718, 0x318, 5, __NA_, 0, NO_PAD_CTRL) |
| 1375 | #define MX51_PAD_DISP1_DAT19__DISP2_PIN6 (_MX51_PAD_DISP1_DAT19__DISP2_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 621 | #define MX51_PAD_DISP1_DAT19__DISP2_PIN6 IOMUX_PAD(0x718, 0x318, 4, __NA_, 0, NO_PAD_CTRL) |
| 1376 | #define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 (_MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 622 | #define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 IOMUX_PAD(0x71c, 0x31c, 7, __NA_, 0, NO_PAD_CTRL) |
| 1377 | #define MX51_PAD_DISP1_DAT20__DISP1_DAT20 (_MX51_PAD_DISP1_DAT20__DISP1_DAT20 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 623 | #define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71c, 0x31c, 0, __NA_, 0, NO_PAD_CTRL) |
| 1378 | #define MX51_PAD_DISP1_DAT20__DISP2_PIN13 (_MX51_PAD_DISP1_DAT20__DISP2_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 624 | #define MX51_PAD_DISP1_DAT20__DISP2_PIN13 IOMUX_PAD(0x71c, 0x31c, 5, __NA_, 0, NO_PAD_CTRL) |
| 1379 | #define MX51_PAD_DISP1_DAT20__DISP2_PIN7 (_MX51_PAD_DISP1_DAT20__DISP2_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 625 | #define MX51_PAD_DISP1_DAT20__DISP2_PIN7 IOMUX_PAD(0x71c, 0x31c, 4, __NA_, 0, NO_PAD_CTRL) |
| 1380 | #define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 (_MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 626 | #define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 IOMUX_PAD(0x720, 0x320, 7, __NA_, 0, NO_PAD_CTRL) |
| 1381 | #define MX51_PAD_DISP1_DAT21__DISP1_DAT21 (_MX51_PAD_DISP1_DAT21__DISP1_DAT21 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 627 | #define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, __NA_, 0, NO_PAD_CTRL) |
| 1382 | #define MX51_PAD_DISP1_DAT21__DISP2_PIN14 (_MX51_PAD_DISP1_DAT21__DISP2_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 628 | #define MX51_PAD_DISP1_DAT21__DISP2_PIN14 IOMUX_PAD(0x720, 0x320, 5, __NA_, 0, NO_PAD_CTRL) |
| 1383 | #define MX51_PAD_DISP1_DAT21__DISP2_PIN8 (_MX51_PAD_DISP1_DAT21__DISP2_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 629 | #define MX51_PAD_DISP1_DAT21__DISP2_PIN8 IOMUX_PAD(0x720, 0x320, 4, __NA_, 0, NO_PAD_CTRL) |
| 1384 | #define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 (_MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 630 | #define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 IOMUX_PAD(0x724, 0x324, 7, __NA_, 0, NO_PAD_CTRL) |
| 1385 | #define MX51_PAD_DISP1_DAT22__DISP1_DAT22 (_MX51_PAD_DISP1_DAT22__DISP1_DAT22 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 631 | #define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, __NA_, 0, NO_PAD_CTRL) |
| 1386 | #define MX51_PAD_DISP1_DAT22__DISP2_D0_CS (_MX51_PAD_DISP1_DAT22__DISP2_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 632 | #define MX51_PAD_DISP1_DAT22__DISP2_D0_CS IOMUX_PAD(0x724, 0x324, 6, __NA_, 0, NO_PAD_CTRL) |
| 1387 | #define MX51_PAD_DISP1_DAT22__DISP2_DAT16 (_MX51_PAD_DISP1_DAT22__DISP2_DAT16 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 633 | #define MX51_PAD_DISP1_DAT22__DISP2_DAT16 IOMUX_PAD(0x724, 0x324, 5, __NA_, 0, NO_PAD_CTRL) |
| 1388 | #define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 (_MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 634 | #define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 IOMUX_PAD(0x728, 0x328, 7, __NA_, 0, NO_PAD_CTRL) |
| 1389 | #define MX51_PAD_DISP1_DAT23__DISP1_DAT23 (_MX51_PAD_DISP1_DAT23__DISP1_DAT23 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 635 | #define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, __NA_, 0, NO_PAD_CTRL) |
| 1390 | #define MX51_PAD_DISP1_DAT23__DISP2_D1_CS (_MX51_PAD_DISP1_DAT23__DISP2_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 636 | #define MX51_PAD_DISP1_DAT23__DISP2_D1_CS IOMUX_PAD(0x728, 0x328, 6, __NA_, 0, NO_PAD_CTRL) |
| 1391 | #define MX51_PAD_DISP1_DAT23__DISP2_DAT17 (_MX51_PAD_DISP1_DAT23__DISP2_DAT17 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 637 | #define MX51_PAD_DISP1_DAT23__DISP2_DAT17 IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL) |
| 1392 | #define MX51_PAD_DISP1_DAT23__DISP2_SER_CS (_MX51_PAD_DISP1_DAT23__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 638 | #define MX51_PAD_DISP1_DAT23__DISP2_SER_CS IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL) |
| 1393 | #define MX51_PAD_DI1_PIN3__DI1_PIN3 (_MX51_PAD_DI1_PIN3__DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 639 | #define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL) |
| 1394 | #define MX51_PAD_DI1_PIN2__DI1_PIN2 (_MX51_PAD_DI1_PIN2__DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 640 | #define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL) |
| 1395 | #define MX51_PAD_DI_GP2__DISP1_SER_CLK (_MX51_PAD_DI_GP2__DISP1_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 641 | #define MX51_PAD_DI_GP2__DISP1_SER_CLK IOMUX_PAD(0x740, 0x338, 0, __NA_, 0, NO_PAD_CTRL) |
| 1396 | #define MX51_PAD_DI_GP2__DISP2_WAIT (_MX51_PAD_DI_GP2__DISP2_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL)) | 642 | #define MX51_PAD_DI_GP2__DISP2_WAIT IOMUX_PAD(0x740, 0x338, 2, 0x9a8, 1, NO_PAD_CTRL) |
| 1397 | #define MX51_PAD_DI_GP3__CSI1_DATA_EN (_MX51_PAD_DI_GP3__CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) | 643 | #define MX51_PAD_DI_GP3__CSI1_DATA_EN IOMUX_PAD(0x744, 0x33c, 3, 0x9a0, 1, NO_PAD_CTRL) |
| 1398 | #define MX51_PAD_DI_GP3__DISP1_SER_DIO (_MX51_PAD_DI_GP3__DISP1_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 644 | #define MX51_PAD_DI_GP3__DISP1_SER_DIO IOMUX_PAD(0x744, 0x33c, 0, 0x9c0, 0, NO_PAD_CTRL) |
| 1399 | #define MX51_PAD_DI_GP3__FEC_TX_ER (_MX51_PAD_DI_GP3__FEC_TX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) | 645 | #define MX51_PAD_DI_GP3__FEC_TX_ER IOMUX_PAD(0x744, 0x33c, 2, __NA_, 0, MX51_PAD_CTRL_5) |
| 1400 | #define MX51_PAD_DI2_PIN4__CSI2_DATA_EN (_MX51_PAD_DI2_PIN4__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) | 646 | #define MX51_PAD_DI2_PIN4__CSI2_DATA_EN IOMUX_PAD(0x748, 0x340, 3, 0x99c, 1, NO_PAD_CTRL) |
| 1401 | #define MX51_PAD_DI2_PIN4__DI2_PIN4 (_MX51_PAD_DI2_PIN4__DI2_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 647 | #define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, __NA_, 0, NO_PAD_CTRL) |
| 1402 | #define MX51_PAD_DI2_PIN4__FEC_CRS (_MX51_PAD_DI2_PIN4__FEC_CRS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 648 | #define MX51_PAD_DI2_PIN4__FEC_CRS IOMUX_PAD(0x748, 0x340, 2, 0x950, 1, NO_PAD_CTRL) |
| 1403 | #define MX51_PAD_DI2_PIN2__DI2_PIN2 (_MX51_PAD_DI2_PIN2__DI2_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 649 | #define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74c, 0x344, 0, __NA_, 0, NO_PAD_CTRL) |
| 1404 | #define MX51_PAD_DI2_PIN2__FEC_MDC (_MX51_PAD_DI2_PIN2__FEC_MDC | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) | 650 | #define MX51_PAD_DI2_PIN2__FEC_MDC IOMUX_PAD(0x74c, 0x344, 2, __NA_, 0, MX51_PAD_CTRL_5) |
| 1405 | #define MX51_PAD_DI2_PIN3__DI2_PIN3 (_MX51_PAD_DI2_PIN3__DI2_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 651 | #define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, __NA_, 0, NO_PAD_CTRL) |
| 1406 | #define MX51_PAD_DI2_PIN3__FEC_MDIO (_MX51_PAD_DI2_PIN3__FEC_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 652 | #define MX51_PAD_DI2_PIN3__FEC_MDIO IOMUX_PAD(0x750, 0x348, 2, 0x954, 1, NO_PAD_CTRL) |
| 1407 | #define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK (_MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 653 | #define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL) |
| 1408 | #define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 (_MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 654 | #define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 IOMUX_PAD(0x754, 0x34c, 2, 0x95c, 1, NO_PAD_CTRL) |
| 1409 | #define MX51_PAD_DI_GP4__DI2_PIN15 (_MX51_PAD_DI_GP4__DI2_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 655 | #define MX51_PAD_DI_GP4__DI2_PIN15 IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL) |
| 1410 | #define MX51_PAD_DI_GP4__DISP1_SER_DIN (_MX51_PAD_DI_GP4__DISP1_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL)) | 656 | #define MX51_PAD_DI_GP4__DISP1_SER_DIN IOMUX_PAD(0x758, 0x350, 0, 0x9c0, 1, NO_PAD_CTRL) |
| 1411 | #define MX51_PAD_DI_GP4__DISP2_PIN1 (_MX51_PAD_DI_GP4__DISP2_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 657 | #define MX51_PAD_DI_GP4__DISP2_PIN1 IOMUX_PAD(0x758, 0x350, 3, __NA_, 0, NO_PAD_CTRL) |
| 1412 | #define MX51_PAD_DI_GP4__FEC_RDATA2 (_MX51_PAD_DI_GP4__FEC_RDATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 658 | #define MX51_PAD_DI_GP4__FEC_RDATA2 IOMUX_PAD(0x758, 0x350, 2, 0x960, 1, NO_PAD_CTRL) |
| 1413 | #define MX51_PAD_DISP2_DAT0__DISP2_DAT0 (_MX51_PAD_DISP2_DAT0__DISP2_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 659 | #define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75c, 0x354, 0, __NA_, 0, NO_PAD_CTRL) |
| 1414 | #define MX51_PAD_DISP2_DAT0__FEC_RDATA3 (_MX51_PAD_DISP2_DAT0__FEC_RDATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 660 | #define MX51_PAD_DISP2_DAT0__FEC_RDATA3 IOMUX_PAD(0x75c, 0x354, 2, 0x964, 1, NO_PAD_CTRL) |
| 1415 | #define MX51_PAD_DISP2_DAT0__KEY_COL6 (_MX51_PAD_DISP2_DAT0__KEY_COL6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 661 | #define MX51_PAD_DISP2_DAT0__KEY_COL6 IOMUX_PAD(0x75c, 0x354, 4, 0x9c8, 1, NO_PAD_CTRL) |
| 1416 | #define MX51_PAD_DISP2_DAT0__UART3_RXD (_MX51_PAD_DISP2_DAT0__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 662 | #define MX51_PAD_DISP2_DAT0__UART3_RXD IOMUX_PAD(0x75c, 0x354, 5, 0x9f4, 8, MX51_UART_PAD_CTRL) |
| 1417 | #define MX51_PAD_DISP2_DAT0__USBH3_CLK (_MX51_PAD_DISP2_DAT0__USBH3_CLK | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 663 | #define MX51_PAD_DISP2_DAT0__USBH3_CLK IOMUX_PAD(0x75c, 0x354, 3, 0x9f8, 1, MX51_UART_PAD_CTRL) |
| 1418 | #define MX51_PAD_DISP2_DAT1__DISP2_DAT1 (_MX51_PAD_DISP2_DAT1__DISP2_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 664 | #define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, __NA_, 0, NO_PAD_CTRL) |
| 1419 | #define MX51_PAD_DISP2_DAT1__FEC_RX_ER (_MX51_PAD_DISP2_DAT1__FEC_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL)) | 665 | #define MX51_PAD_DISP2_DAT1__FEC_RX_ER IOMUX_PAD(0x760, 0x358, 2, 0x970, 1, NO_PAD_CTRL) |
| 1420 | #define MX51_PAD_DISP2_DAT1__KEY_COL7 (_MX51_PAD_DISP2_DAT1__KEY_COL7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 666 | #define MX51_PAD_DISP2_DAT1__KEY_COL7 IOMUX_PAD(0x760, 0x358, 4, 0x9cc, 1, NO_PAD_CTRL) |
| 1421 | #define MX51_PAD_DISP2_DAT1__UART3_TXD (_MX51_PAD_DISP2_DAT1__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL)) | 667 | #define MX51_PAD_DISP2_DAT1__UART3_TXD IOMUX_PAD(0x760, 0x358, 5, __NA_, 0, MX51_UART_PAD_CTRL) |
| 1422 | #define MX51_PAD_DISP2_DAT1__USBH3_DIR (_MX51_PAD_DISP2_DAT1__USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) | 668 | #define MX51_PAD_DISP2_DAT1__USBH3_DIR IOMUX_PAD(0x760, 0x358, 3, 0xa1c, 1, NO_PAD_CTRL) |
| 1423 | #define MX51_PAD_DISP2_DAT2__DISP2_DAT2 (_MX51_PAD_DISP2_DAT2__DISP2_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 669 | #define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35c, 0, __NA_, 0, NO_PAD_CTRL) |
| 1424 | #define MX51_PAD_DISP2_DAT3__DISP2_DAT3 (_MX51_PAD_DISP2_DAT3__DISP2_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 670 | #define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, __NA_, 0, NO_PAD_CTRL) |
| 1425 | #define MX51_PAD_DISP2_DAT4__DISP2_DAT4 (_MX51_PAD_DISP2_DAT4__DISP2_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 671 | #define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76c, 0x364, 0, __NA_, 0, NO_PAD_CTRL) |
| 1426 | #define MX51_PAD_DISP2_DAT5__DISP2_DAT5 (_MX51_PAD_DISP2_DAT5__DISP2_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 672 | #define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, __NA_, 0, NO_PAD_CTRL) |
| 1427 | #define MX51_PAD_DISP2_DAT6__DISP2_DAT6 (_MX51_PAD_DISP2_DAT6__DISP2_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 673 | #define MX51_PAD_DISP2_DAT6__DISP2_DAT6 IOMUX_PAD(0x774, 0x36c, 0, __NA_, 0, NO_PAD_CTRL) |
| 1428 | #define MX51_PAD_DISP2_DAT6__FEC_TDATA1 (_MX51_PAD_DISP2_DAT6__FEC_TDATA1 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) | 674 | #define MX51_PAD_DISP2_DAT6__FEC_TDATA1 IOMUX_PAD(0x774, 0x36c, 2, __NA_, 0, MX51_PAD_CTRL_5) |
| 1429 | #define MX51_PAD_DISP2_DAT6__GPIO1_19 (_MX51_PAD_DISP2_DAT6__GPIO1_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 675 | #define MX51_PAD_DISP2_DAT6__GPIO1_19 IOMUX_PAD(0x774, 0x36c, 5, __NA_, 0, NO_PAD_CTRL) |
| 1430 | #define MX51_PAD_DISP2_DAT6__KEY_ROW4 (_MX51_PAD_DISP2_DAT6__KEY_ROW4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 676 | #define MX51_PAD_DISP2_DAT6__KEY_ROW4 IOMUX_PAD(0x774, 0x36c, 4, 0x9d0, 1, NO_PAD_CTRL) |
| 1431 | #define MX51_PAD_DISP2_DAT6__USBH3_STP (_MX51_PAD_DISP2_DAT6__USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) | 677 | #define MX51_PAD_DISP2_DAT6__USBH3_STP IOMUX_PAD(0x774, 0x36c, 3, 0xa24, 1, NO_PAD_CTRL) |
| 1432 | #define MX51_PAD_DISP2_DAT7__DISP2_DAT7 (_MX51_PAD_DISP2_DAT7__DISP2_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 678 | #define MX51_PAD_DISP2_DAT7__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 0, __NA_, 0, NO_PAD_CTRL) |
| 1433 | #define MX51_PAD_DISP2_DAT7__FEC_TDATA2 (_MX51_PAD_DISP2_DAT7__FEC_TDATA2 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) | 679 | #define MX51_PAD_DISP2_DAT7__FEC_TDATA2 IOMUX_PAD(0x778, 0x370, 2, __NA_, 0, MX51_PAD_CTRL_5) |
| 1434 | #define MX51_PAD_DISP2_DAT7__GPIO1_29 (_MX51_PAD_DISP2_DAT7__GPIO1_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 680 | #define MX51_PAD_DISP2_DAT7__GPIO1_29 IOMUX_PAD(0x778, 0x370, 5, __NA_, 0, NO_PAD_CTRL) |
| 1435 | #define MX51_PAD_DISP2_DAT7__KEY_ROW5 (_MX51_PAD_DISP2_DAT7__KEY_ROW5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 681 | #define MX51_PAD_DISP2_DAT7__KEY_ROW5 IOMUX_PAD(0x778, 0x370, 4, 0x9d4, 1, NO_PAD_CTRL) |
| 1436 | #define MX51_PAD_DISP2_DAT7__USBH3_NXT (_MX51_PAD_DISP2_DAT7__USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) | 682 | #define MX51_PAD_DISP2_DAT7__USBH3_NXT IOMUX_PAD(0x778, 0x370, 3, 0xa20, 1, NO_PAD_CTRL) |
| 1437 | #define MX51_PAD_DISP2_DAT8__DISP2_DAT8 (_MX51_PAD_DISP2_DAT8__DISP2_DAT8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 683 | #define MX51_PAD_DISP2_DAT8__DISP2_DAT8 IOMUX_PAD(0x77c, 0x374, 0, __NA_, 0, NO_PAD_CTRL) |
| 1438 | #define MX51_PAD_DISP2_DAT8__FEC_TDATA3 (_MX51_PAD_DISP2_DAT8__FEC_TDATA3 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) | 684 | #define MX51_PAD_DISP2_DAT8__FEC_TDATA3 IOMUX_PAD(0x77c, 0x374, 2, __NA_, 0, MX51_PAD_CTRL_5) |
| 1439 | #define MX51_PAD_DISP2_DAT8__GPIO1_30 (_MX51_PAD_DISP2_DAT8__GPIO1_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 685 | #define MX51_PAD_DISP2_DAT8__GPIO1_30 IOMUX_PAD(0x77c, 0x374, 5, __NA_, 0, NO_PAD_CTRL) |
| 1440 | #define MX51_PAD_DISP2_DAT8__KEY_ROW6 (_MX51_PAD_DISP2_DAT8__KEY_ROW6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 686 | #define MX51_PAD_DISP2_DAT8__KEY_ROW6 IOMUX_PAD(0x77c, 0x374, 4, 0x9d8, 1, NO_PAD_CTRL) |
| 1441 | #define MX51_PAD_DISP2_DAT8__USBH3_DATA0 (_MX51_PAD_DISP2_DAT8__USBH3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 687 | #define MX51_PAD_DISP2_DAT8__USBH3_DATA0 IOMUX_PAD(0x77c, 0x374, 3, 0x9fc, 1, NO_PAD_CTRL) |
| 1442 | #define MX51_PAD_DISP2_DAT9__AUD6_RXC (_MX51_PAD_DISP2_DAT9__AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 688 | #define MX51_PAD_DISP2_DAT9__AUD6_RXC IOMUX_PAD(0x780, 0x378, 4, 0x8f4, 1, NO_PAD_CTRL) |
| 1443 | #define MX51_PAD_DISP2_DAT9__DISP2_DAT9 (_MX51_PAD_DISP2_DAT9__DISP2_DAT9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 689 | #define MX51_PAD_DISP2_DAT9__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 0, __NA_, 0, NO_PAD_CTRL) |
| 1444 | #define MX51_PAD_DISP2_DAT9__FEC_TX_EN (_MX51_PAD_DISP2_DAT9__FEC_TX_EN | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) | 690 | #define MX51_PAD_DISP2_DAT9__FEC_TX_EN IOMUX_PAD(0x780, 0x378, 2, __NA_, 0, MX51_PAD_CTRL_5) |
| 1445 | #define MX51_PAD_DISP2_DAT9__GPIO1_31 (_MX51_PAD_DISP2_DAT9__GPIO1_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 691 | #define MX51_PAD_DISP2_DAT9__GPIO1_31 IOMUX_PAD(0x780, 0x378, 5, __NA_, 0, NO_PAD_CTRL) |
| 1446 | #define MX51_PAD_DISP2_DAT9__USBH3_DATA1 (_MX51_PAD_DISP2_DAT9__USBH3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 692 | #define MX51_PAD_DISP2_DAT9__USBH3_DATA1 IOMUX_PAD(0x780, 0x378, 3, 0xa00, 1, NO_PAD_CTRL) |
| 1447 | #define MX51_PAD_DISP2_DAT10__DISP2_DAT10 (_MX51_PAD_DISP2_DAT10__DISP2_DAT10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 693 | #define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37c, 0, __NA_, 0, NO_PAD_CTRL) |
| 1448 | #define MX51_PAD_DISP2_DAT10__DISP2_SER_CS (_MX51_PAD_DISP2_DAT10__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 694 | #define MX51_PAD_DISP2_DAT10__DISP2_SER_CS IOMUX_PAD(0x784, 0x37c, 5, __NA_, 0, NO_PAD_CTRL) |
| 1449 | #define MX51_PAD_DISP2_DAT10__FEC_COL (_MX51_PAD_DISP2_DAT10__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL)) | 695 | #define MX51_PAD_DISP2_DAT10__FEC_COL IOMUX_PAD(0x784, 0x37c, 2, 0x94c, 1, NO_PAD_CTRL) |
| 1450 | #define MX51_PAD_DISP2_DAT10__KEY_ROW7 (_MX51_PAD_DISP2_DAT10__KEY_ROW7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 696 | #define MX51_PAD_DISP2_DAT10__KEY_ROW7 IOMUX_PAD(0x784, 0x37c, 4, 0x9dc, 1, NO_PAD_CTRL) |
| 1451 | #define MX51_PAD_DISP2_DAT10__USBH3_DATA2 (_MX51_PAD_DISP2_DAT10__USBH3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 697 | #define MX51_PAD_DISP2_DAT10__USBH3_DATA2 IOMUX_PAD(0x784, 0x37c, 3, 0xa04, 1, NO_PAD_CTRL) |
| 1452 | #define MX51_PAD_DISP2_DAT11__AUD6_TXD (_MX51_PAD_DISP2_DAT11__AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 698 | #define MX51_PAD_DISP2_DAT11__AUD6_TXD IOMUX_PAD(0x788, 0x380, 4, 0x8f0, 1, NO_PAD_CTRL) |
| 1453 | #define MX51_PAD_DISP2_DAT11__DISP2_DAT11 (_MX51_PAD_DISP2_DAT11__DISP2_DAT11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 699 | #define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, __NA_, 0, NO_PAD_CTRL) |
| 1454 | #define MX51_PAD_DISP2_DAT11__FEC_RX_CLK (_MX51_PAD_DISP2_DAT11__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 700 | #define MX51_PAD_DISP2_DAT11__FEC_RX_CLK IOMUX_PAD(0x788, 0x380, 2, 0x968, 1, NO_PAD_CTRL) |
| 1455 | #define MX51_PAD_DISP2_DAT11__GPIO1_10 (_MX51_PAD_DISP2_DAT11__GPIO1_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 701 | #define MX51_PAD_DISP2_DAT11__GPIO1_10 IOMUX_PAD(0x788, 0x380, 7, __NA_, 0, NO_PAD_CTRL) |
| 1456 | #define MX51_PAD_DISP2_DAT11__USBH3_DATA3 (_MX51_PAD_DISP2_DAT11__USBH3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 702 | #define MX51_PAD_DISP2_DAT11__USBH3_DATA3 IOMUX_PAD(0x788, 0x380, 3, 0xa08, 1, NO_PAD_CTRL) |
| 1457 | #define MX51_PAD_DISP2_DAT12__AUD6_RXD (_MX51_PAD_DISP2_DAT12__AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 703 | #define MX51_PAD_DISP2_DAT12__AUD6_RXD IOMUX_PAD(0x78c, 0x384, 4, 0x8ec, 1, NO_PAD_CTRL) |
| 1458 | #define MX51_PAD_DISP2_DAT12__DISP2_DAT12 (_MX51_PAD_DISP2_DAT12__DISP2_DAT12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 704 | #define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78c, 0x384, 0, __NA_, 0, NO_PAD_CTRL) |
| 1459 | #define MX51_PAD_DISP2_DAT12__FEC_RX_DV (_MX51_PAD_DISP2_DAT12__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL)) | 705 | #define MX51_PAD_DISP2_DAT12__FEC_RX_DV IOMUX_PAD(0x78c, 0x384, 2, 0x96c, 1, NO_PAD_CTRL) |
| 1460 | #define MX51_PAD_DISP2_DAT12__USBH3_DATA4 (_MX51_PAD_DISP2_DAT12__USBH3_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 706 | #define MX51_PAD_DISP2_DAT12__USBH3_DATA4 IOMUX_PAD(0x78c, 0x384, 3, 0xa0c, 1, NO_PAD_CTRL) |
| 1461 | #define MX51_PAD_DISP2_DAT13__AUD6_TXC (_MX51_PAD_DISP2_DAT13__AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 707 | #define MX51_PAD_DISP2_DAT13__AUD6_TXC IOMUX_PAD(0x790, 0x388, 4, 0x8fc, 1, NO_PAD_CTRL) |
| 1462 | #define MX51_PAD_DISP2_DAT13__DISP2_DAT13 (_MX51_PAD_DISP2_DAT13__DISP2_DAT13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 708 | #define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, __NA_, 0, NO_PAD_CTRL) |
| 1463 | #define MX51_PAD_DISP2_DAT13__FEC_TX_CLK (_MX51_PAD_DISP2_DAT13__FEC_TX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_4)) | 709 | #define MX51_PAD_DISP2_DAT13__FEC_TX_CLK IOMUX_PAD(0x790, 0x388, 2, 0x974, 1, MX51_PAD_CTRL_4) |
| 1464 | #define MX51_PAD_DISP2_DAT13__USBH3_DATA5 (_MX51_PAD_DISP2_DAT13__USBH3_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 710 | #define MX51_PAD_DISP2_DAT13__USBH3_DATA5 IOMUX_PAD(0x790, 0x388, 3, 0xa10, 1, NO_PAD_CTRL) |
| 1465 | #define MX51_PAD_DISP2_DAT14__AUD6_TXFS (_MX51_PAD_DISP2_DAT14__AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 711 | #define MX51_PAD_DISP2_DAT14__AUD6_TXFS IOMUX_PAD(0x794, 0x38c, 4, 0x900, 1, NO_PAD_CTRL) |
| 1466 | #define MX51_PAD_DISP2_DAT14__DISP2_DAT14 (_MX51_PAD_DISP2_DAT14__DISP2_DAT14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 712 | #define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38c, 0, __NA_, 0, NO_PAD_CTRL) |
| 1467 | #define MX51_PAD_DISP2_DAT14__FEC_RDATA0 (_MX51_PAD_DISP2_DAT14__FEC_RDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_4)) | 713 | #define MX51_PAD_DISP2_DAT14__FEC_RDATA0 IOMUX_PAD(0x794, 0x38c, 2, 0x958, 1, MX51_PAD_CTRL_4) |
| 1468 | #define MX51_PAD_DISP2_DAT14__USBH3_DATA6 (_MX51_PAD_DISP2_DAT14__USBH3_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 714 | #define MX51_PAD_DISP2_DAT14__USBH3_DATA6 IOMUX_PAD(0x794, 0x38c, 3, 0xa14, 1, NO_PAD_CTRL) |
| 1469 | #define MX51_PAD_DISP2_DAT15__AUD6_RXFS (_MX51_PAD_DISP2_DAT15__AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 715 | #define MX51_PAD_DISP2_DAT15__AUD6_RXFS IOMUX_PAD(0x798, 0x390, 4, 0x8f8, 1, NO_PAD_CTRL) |
| 1470 | #define MX51_PAD_DISP2_DAT15__DISP1_SER_CS (_MX51_PAD_DISP2_DAT15__DISP1_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 716 | #define MX51_PAD_DISP2_DAT15__DISP1_SER_CS IOMUX_PAD(0x798, 0x390, 5, __NA_, 0, NO_PAD_CTRL) |
| 1471 | #define MX51_PAD_DISP2_DAT15__DISP2_DAT15 (_MX51_PAD_DISP2_DAT15__DISP2_DAT15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 717 | #define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, __NA_, 0, NO_PAD_CTRL) |
| 1472 | #define MX51_PAD_DISP2_DAT15__FEC_TDATA0 (_MX51_PAD_DISP2_DAT15__FEC_TDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) | 718 | #define MX51_PAD_DISP2_DAT15__FEC_TDATA0 IOMUX_PAD(0x798, 0x390, 2, __NA_, 0, MX51_PAD_CTRL_5) |
| 1473 | #define MX51_PAD_DISP2_DAT15__USBH3_DATA7 (_MX51_PAD_DISP2_DAT15__USBH3_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 719 | #define MX51_PAD_DISP2_DAT15__USBH3_DATA7 IOMUX_PAD(0x798, 0x390, 3, 0xa18, 1, NO_PAD_CTRL) |
| 1474 | #define MX51_PAD_SD1_CMD__AUD5_RXFS (_MX51_PAD_SD1_CMD__AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 720 | #define MX51_PAD_SD1_CMD__AUD5_RXFS IOMUX_PAD(0x79c, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL) |
| 1475 | #define MX51_PAD_SD1_CMD__CSPI_MOSI (_MX51_PAD_SD1_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) | 721 | #define MX51_PAD_SD1_CMD__CSPI_MOSI IOMUX_PAD(0x79c, 0x394, 2, 0x91c, 2, NO_PAD_CTRL) |
| 1476 | #define MX51_PAD_SD1_CMD__SD1_CMD (_MX51_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) | 722 | #define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) |
| 1477 | #define MX51_PAD_SD1_CLK__AUD5_RXC (_MX51_PAD_SD1_CLK__AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 723 | #define MX51_PAD_SD1_CLK__AUD5_RXC IOMUX_PAD(0x7a0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL) |
| 1478 | #define MX51_PAD_SD1_CLK__CSPI_SCLK (_MX51_PAD_SD1_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 724 | #define MX51_PAD_SD1_CLK__CSPI_SCLK IOMUX_PAD(0x7a0, 0x398, 2, 0x914, 2, NO_PAD_CTRL) |
| 1479 | #define MX51_PAD_SD1_CLK__SD1_CLK (_MX51_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)) | 725 | #define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) |
| 1480 | #define MX51_PAD_SD1_DATA0__AUD5_TXD (_MX51_PAD_SD1_DATA0__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 726 | #define MX51_PAD_SD1_DATA0__AUD5_TXD IOMUX_PAD(0x7a4, 0x39c, 1, 0x8d8, 2, NO_PAD_CTRL) |
| 1481 | #define MX51_PAD_SD1_DATA0__CSPI_MISO (_MX51_PAD_SD1_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 727 | #define MX51_PAD_SD1_DATA0__CSPI_MISO IOMUX_PAD(0x7a4, 0x39c, 2, 0x918, 1, MX51_ECSPI_PAD_CTRL) |
| 1482 | #define MX51_PAD_SD1_DATA0__SD1_DATA0 (_MX51_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) | 728 | #define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) |
| 1483 | #define MX51_PAD_EIM_DA0__EIM_DA0 (_MX51_PAD_EIM_DA0__EIM_DA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 729 | #define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(__NA_, 0x01c, 0, 0x000, 0, NO_PAD_CTRL) |
| 1484 | #define MX51_PAD_EIM_DA1__EIM_DA1 (_MX51_PAD_EIM_DA1__EIM_DA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 730 | #define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(__NA_, 0x020, 0, 0x000, 0, NO_PAD_CTRL) |
| 1485 | #define MX51_PAD_EIM_DA2__EIM_DA2 (_MX51_PAD_EIM_DA2__EIM_DA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 731 | #define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(__NA_, 0x024, 0, 0x000, 0, NO_PAD_CTRL) |
| 1486 | #define MX51_PAD_EIM_DA3__EIM_DA3 (_MX51_PAD_EIM_DA3__EIM_DA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 732 | #define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(__NA_, 0x028, 0, 0x000, 0, NO_PAD_CTRL) |
| 1487 | #define MX51_PAD_SD1_DATA1__AUD5_RXD (_MX51_PAD_SD1_DATA1__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 733 | #define MX51_PAD_SD1_DATA1__AUD5_RXD IOMUX_PAD(0x7a8, 0x3a0, 1, 0x8d4, 2, NO_PAD_CTRL) |
| 1488 | #define MX51_PAD_SD1_DATA1__SD1_DATA1 (_MX51_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) | 734 | #define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7a8, 0x3a0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) |
| 1489 | #define MX51_PAD_EIM_DA4__EIM_DA4 (_MX51_PAD_EIM_DA4__EIM_DA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 735 | #define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(__NA_, 0x02c, 0, 0x000, 0, NO_PAD_CTRL) |
| 1490 | #define MX51_PAD_EIM_DA5__EIM_DA5 (_MX51_PAD_EIM_DA5__EIM_DA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 736 | #define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(__NA_, 0x030, 0, 0x000, 0, NO_PAD_CTRL) |
| 1491 | #define MX51_PAD_EIM_DA6__EIM_DA6 (_MX51_PAD_EIM_DA6__EIM_DA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 737 | #define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(__NA_, 0x034, 0, 0x000, 0, NO_PAD_CTRL) |
| 1492 | #define MX51_PAD_EIM_DA7__EIM_DA7 (_MX51_PAD_EIM_DA7__EIM_DA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 738 | #define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(__NA_, 0x038, 0, 0x000, 0, NO_PAD_CTRL) |
| 1493 | #define MX51_PAD_SD1_DATA2__AUD5_TXC (_MX51_PAD_SD1_DATA2__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 739 | #define MX51_PAD_SD1_DATA2__AUD5_TXC IOMUX_PAD(0x7ac, 0x3a4, 1, 0x8e4, 2, NO_PAD_CTRL) |
| 1494 | #define MX51_PAD_SD1_DATA2__SD1_DATA2 (_MX51_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) | 740 | #define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7ac, 0x3a4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) |
| 1495 | #define MX51_PAD_EIM_DA10__EIM_DA10 (_MX51_PAD_EIM_DA10__EIM_DA10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 741 | #define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(__NA_, 0x044, 0, 0x000, 0, NO_PAD_CTRL) |
| 1496 | #define MX51_PAD_EIM_DA11__EIM_DA11 (_MX51_PAD_EIM_DA11__EIM_DA11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 742 | #define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(__NA_, 0x048, 0, 0x000, 0, NO_PAD_CTRL) |
| 1497 | #define MX51_PAD_EIM_DA8__EIM_DA8 (_MX51_PAD_EIM_DA8__EIM_DA8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 743 | #define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(__NA_, 0x03c, 0, 0x000, 0, NO_PAD_CTRL) |
| 1498 | #define MX51_PAD_EIM_DA9__EIM_DA9 (_MX51_PAD_EIM_DA9__EIM_DA9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 744 | #define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(__NA_, 0x040, 0, 0x000, 0, NO_PAD_CTRL) |
| 1499 | #define MX51_PAD_SD1_DATA3__AUD5_TXFS (_MX51_PAD_SD1_DATA3__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 745 | #define MX51_PAD_SD1_DATA3__AUD5_TXFS IOMUX_PAD(0x7b0, 0x3a8, 1, 0x8e8, 2, NO_PAD_CTRL) |
| 1500 | #define MX51_PAD_SD1_DATA3__CSPI_SS1 (_MX51_PAD_SD1_DATA3__CSPI_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 746 | #define MX51_PAD_SD1_DATA3__CSPI_SS1 IOMUX_PAD(0x7b0, 0x3a8, 2, 0x920, 1, MX51_ECSPI_PAD_CTRL) |
| 1501 | #define MX51_PAD_SD1_DATA3__SD1_DATA3 (_MX51_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) | 747 | #define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) |
| 1502 | #define MX51_PAD_GPIO1_0__CSPI_SS2 (_MX51_PAD_GPIO1_0__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 748 | #define MX51_PAD_GPIO1_0__CSPI_SS2 IOMUX_PAD(0x7b4, 0x3ac, 2, 0x924, 0, MX51_ECSPI_PAD_CTRL) |
| 1503 | #define MX51_PAD_GPIO1_0__GPIO1_0 (_MX51_PAD_GPIO1_0__GPIO1_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 749 | #define MX51_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, NO_PAD_CTRL) |
| 1504 | #define MX51_PAD_GPIO1_0__SD1_CD (_MX51_PAD_GPIO1_0__SD1_CD | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL)) | 750 | #define MX51_PAD_GPIO1_0__SD1_CD IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL) |
| 1505 | #define MX51_PAD_GPIO1_1__CSPI_MISO (_MX51_PAD_GPIO1_1__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 751 | #define MX51_PAD_GPIO1_1__CSPI_MISO IOMUX_PAD(0x7b8, 0x3b0, 2, 0x918, 2, MX51_ECSPI_PAD_CTRL) |
| 1506 | #define MX51_PAD_GPIO1_1__GPIO1_1 (_MX51_PAD_GPIO1_1__GPIO1_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 752 | #define MX51_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x7b8, 0x3b0, 1, __NA_, 0, NO_PAD_CTRL) |
| 1507 | #define MX51_PAD_GPIO1_1__SD1_WP (_MX51_PAD_GPIO1_1__SD1_WP | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL)) | 753 | #define MX51_PAD_GPIO1_1__SD1_WP IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL) |
| 1508 | #define MX51_PAD_EIM_DA12__EIM_DA12 (_MX51_PAD_EIM_DA12__EIM_DA12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 754 | #define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(__NA_, 0x04c, 0, 0x000, 0, NO_PAD_CTRL) |
| 1509 | #define MX51_PAD_EIM_DA13__EIM_DA13 (_MX51_PAD_EIM_DA13__EIM_DA13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 755 | #define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(__NA_, 0x050, 0, 0x000, 0, NO_PAD_CTRL) |
| 1510 | #define MX51_PAD_EIM_DA14__EIM_DA14 (_MX51_PAD_EIM_DA14__EIM_DA14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 756 | #define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(__NA_, 0x054, 0, 0x000, 0, NO_PAD_CTRL) |
| 1511 | #define MX51_PAD_EIM_DA15__EIM_DA15 (_MX51_PAD_EIM_DA15__EIM_DA15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 757 | #define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(__NA_, 0x058, 0, 0x000, 0, NO_PAD_CTRL) |
| 1512 | #define MX51_PAD_SD2_CMD__CSPI_MOSI (_MX51_PAD_SD2_CMD__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 758 | #define MX51_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(__NA_, 0x3b4, 2, 0x91c, 3, MX51_ECSPI_PAD_CTRL) |
| 1513 | #define MX51_PAD_SD2_CMD__I2C1_SCL (_MX51_PAD_SD2_CMD__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | 759 | #define MX51_PAD_SD2_CMD__I2C1_SCL IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x9b0, 2, MX51_I2C_PAD_CTRL) |
| 1514 | #define MX51_PAD_SD2_CMD__SD2_CMD (_MX51_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) | 760 | #define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) |
| 1515 | #define MX51_PAD_SD2_CLK__CSPI_SCLK (_MX51_PAD_SD2_CLK__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 761 | #define MX51_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x7c0, 0x3b8, 2, 0x914, 3, MX51_ECSPI_PAD_CTRL) |
| 1516 | #define MX51_PAD_SD2_CLK__I2C1_SDA (_MX51_PAD_SD2_CLK__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | 762 | #define MX51_PAD_SD2_CLK__I2C1_SDA IOMUX_PAD(0x7c0, 0x3b8, 0x11, 0x9b4, 2, MX51_I2C_PAD_CTRL) |
| 1517 | #define MX51_PAD_SD2_CLK__SD2_CLK (_MX51_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)) | 763 | #define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7c0, 0x3b8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) |
| 1518 | #define MX51_PAD_SD2_DATA0__CSPI_MISO (_MX51_PAD_SD2_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 764 | #define MX51_PAD_SD2_DATA0__CSPI_MISO IOMUX_PAD(0x7c4, 0x3bc, 2, 0x918, 3, MX51_ECSPI_PAD_CTRL) |
| 1519 | #define MX51_PAD_SD2_DATA0__SD1_DAT4 (_MX51_PAD_SD2_DATA0__SD1_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 765 | #define MX51_PAD_SD2_DATA0__SD1_DAT4 IOMUX_PAD(0x7c4, 0x3bc, 1, __NA_, 0, NO_PAD_CTRL) |
| 1520 | #define MX51_PAD_SD2_DATA0__SD2_DATA0 (_MX51_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) | 766 | #define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) |
| 1521 | #define MX51_PAD_SD2_DATA1__SD1_DAT5 (_MX51_PAD_SD2_DATA1__SD1_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 767 | #define MX51_PAD_SD2_DATA1__SD1_DAT5 IOMUX_PAD(0x7c8, 0x3c0, 1, __NA_, 0, NO_PAD_CTRL) |
| 1522 | #define MX51_PAD_SD2_DATA1__SD2_DATA1 (_MX51_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) | 768 | #define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) |
| 1523 | #define MX51_PAD_SD2_DATA1__USBH3_H2_DP (_MX51_PAD_SD2_DATA1__USBH3_H2_DP | MUX_PAD_CTRL(NO_PAD_CTRL)) | 769 | #define MX51_PAD_SD2_DATA1__USBH3_H2_DP IOMUX_PAD(0x7c8, 0x3c0, 2, __NA_, 0, NO_PAD_CTRL) |
| 1524 | #define MX51_PAD_SD2_DATA2__SD1_DAT6 (_MX51_PAD_SD2_DATA2__SD1_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 770 | #define MX51_PAD_SD2_DATA2__SD1_DAT6 IOMUX_PAD(0x7cc, 0x3c4, 1, __NA_, 0, NO_PAD_CTRL) |
| 1525 | #define MX51_PAD_SD2_DATA2__SD2_DATA2 (_MX51_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) | 771 | #define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) |
| 1526 | #define MX51_PAD_SD2_DATA2__USBH3_H2_DM (_MX51_PAD_SD2_DATA2__USBH3_H2_DM | MUX_PAD_CTRL(NO_PAD_CTRL)) | 772 | #define MX51_PAD_SD2_DATA2__USBH3_H2_DM IOMUX_PAD(0x7cc, 0x3c4, 2, __NA_, 0, NO_PAD_CTRL) |
| 1527 | #define MX51_PAD_SD2_DATA3__CSPI_SS2 (_MX51_PAD_SD2_DATA3__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) | 773 | #define MX51_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x7d0, 0x3c8, 2, 0x924, 1, MX51_ECSPI_PAD_CTRL) |
| 1528 | #define MX51_PAD_SD2_DATA3__SD1_DAT7 (_MX51_PAD_SD2_DATA3__SD1_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 774 | #define MX51_PAD_SD2_DATA3__SD1_DAT7 IOMUX_PAD(0x7d0, 0x3c8, 1, __NA_, 0, NO_PAD_CTRL) |
| 1529 | #define MX51_PAD_SD2_DATA3__SD2_DATA3 (_MX51_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL)) | 775 | #define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) |
| 1530 | #define MX51_PAD_GPIO1_2__CCM_OUT_2 (_MX51_PAD_GPIO1_2__CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 776 | #define MX51_PAD_GPIO1_2__CCM_OUT_2 IOMUX_PAD(0x7d4, 0x3cc, 5, __NA_, 0, NO_PAD_CTRL) |
| 1531 | #define MX51_PAD_GPIO1_2__GPIO1_2 (_MX51_PAD_GPIO1_2__GPIO1_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 777 | #define MX51_PAD_GPIO1_2__GPIO1_2 IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, NO_PAD_CTRL) |
| 1532 | #define MX51_PAD_GPIO1_2__I2C2_SCL (_MX51_PAD_GPIO1_2__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | 778 | #define MX51_PAD_GPIO1_2__I2C2_SCL IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x9b8, 3, MX51_I2C_PAD_CTRL) |
| 1533 | #define MX51_PAD_GPIO1_2__PLL1_BYP (_MX51_PAD_GPIO1_2__PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) | 779 | #define MX51_PAD_GPIO1_2__PLL1_BYP IOMUX_PAD(0x7d4, 0x3cc, 7, 0x90c, 1, NO_PAD_CTRL) |
| 1534 | #define MX51_PAD_GPIO1_2__PWM1_PWMO (_MX51_PAD_GPIO1_2__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 780 | #define MX51_PAD_GPIO1_2__PWM1_PWMO IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL) |
| 1535 | #define MX51_PAD_GPIO1_3__GPIO1_3 (_MX51_PAD_GPIO1_3__GPIO1_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 781 | #define MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, NO_PAD_CTRL) |
| 1536 | #define MX51_PAD_GPIO1_3__I2C2_SDA (_MX51_PAD_GPIO1_3__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) | 782 | #define MX51_PAD_GPIO1_3__I2C2_SDA IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL) |
| 1537 | #define MX51_PAD_GPIO1_3__PLL2_BYP (_MX51_PAD_GPIO1_3__PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) | 783 | #define MX51_PAD_GPIO1_3__PLL2_BYP IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL) |
| 1538 | #define MX51_PAD_GPIO1_3__PWM2_PWMO (_MX51_PAD_GPIO1_3__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 784 | #define MX51_PAD_GPIO1_3__PWM2_PWMO IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL) |
| 1539 | #define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ (_MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ | MUX_PAD_CTRL(NO_PAD_CTRL)) | 785 | #define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7fc, 0x3d4, 0, __NA_, 0, NO_PAD_CTRL) |
| 1540 | #define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B (_MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B | MUX_PAD_CTRL(NO_PAD_CTRL)) | 786 | #define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B IOMUX_PAD(0x7fc, 0x3d4, 1, __NA_, 0, NO_PAD_CTRL) |
| 1541 | #define MX51_PAD_GPIO1_4__DISP2_EXT_CLK (_MX51_PAD_GPIO1_4__DISP2_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 787 | #define MX51_PAD_GPIO1_4__DISP2_EXT_CLK IOMUX_PAD(0x804, 0x3d8, 4, 0x908, 1, NO_PAD_CTRL) |
| 1542 | #define MX51_PAD_GPIO1_4__EIM_RDY (_MX51_PAD_GPIO1_4__EIM_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) | 788 | #define MX51_PAD_GPIO1_4__EIM_RDY IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL) |
| 1543 | #define MX51_PAD_GPIO1_4__GPIO1_4 (_MX51_PAD_GPIO1_4__GPIO1_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 789 | #define MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, NO_PAD_CTRL) |
| 1544 | #define MX51_PAD_GPIO1_4__WDOG1_WDOG_B (_MX51_PAD_GPIO1_4__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) | 790 | #define MX51_PAD_GPIO1_4__WDOG1_WDOG_B IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL) |
| 1545 | #define MX51_PAD_GPIO1_5__CSI2_MCLK (_MX51_PAD_GPIO1_5__CSI2_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 791 | #define MX51_PAD_GPIO1_5__CSI2_MCLK IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL) |
| 1546 | #define MX51_PAD_GPIO1_5__DISP2_PIN16 (_MX51_PAD_GPIO1_5__DISP2_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 792 | #define MX51_PAD_GPIO1_5__DISP2_PIN16 IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL) |
| 1547 | #define MX51_PAD_GPIO1_5__GPIO1_5 (_MX51_PAD_GPIO1_5__GPIO1_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 793 | #define MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, NO_PAD_CTRL) |
| 1548 | #define MX51_PAD_GPIO1_5__WDOG2_WDOG_B (_MX51_PAD_GPIO1_5__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) | 794 | #define MX51_PAD_GPIO1_5__WDOG2_WDOG_B IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL) |
| 1549 | #define MX51_PAD_GPIO1_6__DISP2_PIN17 (_MX51_PAD_GPIO1_6__DISP2_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 795 | #define MX51_PAD_GPIO1_6__DISP2_PIN17 IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL) |
| 1550 | #define MX51_PAD_GPIO1_6__GPIO1_6 (_MX51_PAD_GPIO1_6__GPIO1_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 796 | #define MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, NO_PAD_CTRL) |
| 1551 | #define MX51_PAD_GPIO1_6__REF_EN_B (_MX51_PAD_GPIO1_6__REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL)) | 797 | #define MX51_PAD_GPIO1_6__REF_EN_B IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL) |
| 1552 | #define MX51_PAD_GPIO1_7__CCM_OUT_0 (_MX51_PAD_GPIO1_7__CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 798 | #define MX51_PAD_GPIO1_7__CCM_OUT_0 IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL) |
| 1553 | #define MX51_PAD_GPIO1_7__GPIO1_7 (_MX51_PAD_GPIO1_7__GPIO1_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 799 | #define MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, NO_PAD_CTRL) |
| 1554 | #define MX51_PAD_GPIO1_7__SD2_WP (_MX51_PAD_GPIO1_7__SD2_WP | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL)) | 800 | #define MX51_PAD_GPIO1_7__SD2_WP IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) |
| 1555 | #define MX51_PAD_GPIO1_7__SPDIF_OUT1 (_MX51_PAD_GPIO1_7__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 801 | #define MX51_PAD_GPIO1_7__SPDIF_OUT1 IOMUX_PAD(0x810, 0x3e4, 2, __NA_, 0, NO_PAD_CTRL) |
| 1556 | #define MX51_PAD_GPIO1_8__CSI2_DATA_EN (_MX51_PAD_GPIO1_8__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) | 802 | #define MX51_PAD_GPIO1_8__CSI2_DATA_EN IOMUX_PAD(0x814, 0x3e8, 2, 0x99c, 2, NO_PAD_CTRL) |
| 1557 | #define MX51_PAD_GPIO1_8__GPIO1_8 (_MX51_PAD_GPIO1_8__GPIO1_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 803 | #define MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, NO_PAD_CTRL) |
| 1558 | #define MX51_PAD_GPIO1_8__SD2_CD (_MX51_PAD_GPIO1_8__SD2_CD | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL)) | 804 | #define MX51_PAD_GPIO1_8__SD2_CD IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) |
| 1559 | #define MX51_PAD_GPIO1_8__USBH3_PWR (_MX51_PAD_GPIO1_8__USBH3_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) | 805 | #define MX51_PAD_GPIO1_8__USBH3_PWR IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL) |
| 1560 | #define MX51_PAD_GPIO1_9__CCM_OUT_1 (_MX51_PAD_GPIO1_9__CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 806 | #define MX51_PAD_GPIO1_9__CCM_OUT_1 IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL) |
| 1561 | #define MX51_PAD_GPIO1_9__DISP2_D1_CS (_MX51_PAD_GPIO1_9__DISP2_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 807 | #define MX51_PAD_GPIO1_9__DISP2_D1_CS IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL) |
| 1562 | #define MX51_PAD_GPIO1_9__DISP2_SER_CS (_MX51_PAD_GPIO1_9__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 808 | #define MX51_PAD_GPIO1_9__DISP2_SER_CS IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL) |
| 1563 | #define MX51_PAD_GPIO1_9__GPIO1_9 (_MX51_PAD_GPIO1_9__GPIO1_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 809 | #define MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, NO_PAD_CTRL) |
| 1564 | #define MX51_PAD_GPIO1_9__SD2_LCTL (_MX51_PAD_GPIO1_9__SD2_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL)) | 810 | #define MX51_PAD_GPIO1_9__SD2_LCTL IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL) |
| 1565 | #define MX51_PAD_GPIO1_9__USBH3_OC (_MX51_PAD_GPIO1_9__USBH3_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 811 | #define MX51_PAD_GPIO1_9__USBH3_OC IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL) |
| 1566 | 812 | ||
| 1567 | #endif /* __MACH_IOMUX_MX51_H__ */ | 813 | #endif /* __MACH_IOMUX_MX51_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h index 5408fd1fc736..527f8fe3e31b 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx53.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h | |||
| @@ -23,2359 +23,1197 @@ | |||
| 23 | 23 | ||
| 24 | /* These 2 defines are for pins that may not have a mux register, but could | 24 | /* These 2 defines are for pins that may not have a mux register, but could |
| 25 | * have a pad setting register, and vice-versa. */ | 25 | * have a pad setting register, and vice-versa. */ |
| 26 | #define NON_PAD_I 0x00 | 26 | #define __NA_ 0x00 |
| 27 | 27 | ||
| 28 | #define MX53_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ | 28 | #define MX53_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| 29 | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS) | 29 | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| 30 | #define MX53_SDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ | 30 | #define MX53_SDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ |
| 31 | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \ | 31 | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \ |
| 32 | PAD_CTL_SRE_FAST) | 32 | PAD_CTL_SRE_FAST) |
| 33 | #define PAD_CTRL_I2C (PAD_CTL_SRE_FAST | PAD_CTL_ODE | PAD_CTL_PKE | \ | ||
| 34 | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP \ | ||
| 35 | | PAD_CTL_HYS) | ||
| 36 | 33 | ||
| 37 | #define _MX53_PAD_GPIO_19__KPP_COL_5 IOMUX_PAD(0x348, 0x20, 0, 0x840, 0, 0) | ||
| 38 | #define _MX53_PAD_GPIO_19__GPIO4_5 IOMUX_PAD(0x348, 0x20, 1, 0x0, 0, 0) | ||
| 39 | #define _MX53_PAD_GPIO_19__CCM_CLKO IOMUX_PAD(0x348, 0x20, 2, 0x0, 0, 0) | ||
| 40 | #define _MX53_PAD_GPIO_19__SPDIF_OUT1 IOMUX_PAD(0x348, 0x20, 3, 0x0, 0, 0) | ||
| 41 | #define _MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 IOMUX_PAD(0x348, 0x20, 4, 0x0, 0, 0) | ||
| 42 | #define _MX53_PAD_GPIO_19__ECSPI1_RDY IOMUX_PAD(0x348, 0x20, 5, 0x0, 0, 0) | ||
| 43 | #define _MX53_PAD_GPIO_19__FEC_TDATA_3 IOMUX_PAD(0x348, 0x20, 6, 0x0, 0, 0) | ||
| 44 | #define _MX53_PAD_GPIO_19__SRC_INT_BOOT IOMUX_PAD(0x348, 0x20,7, 0x0, 0, 0) | ||
| 45 | #define _MX53_PAD_KEY_COL0__KPP_COL_0 IOMUX_PAD(0x34C, 0x24, 0, 0x0, 0, 0) | ||
| 46 | #define _MX53_PAD_KEY_COL0__GPIO4_6 IOMUX_PAD(0x34C, 0x24, 1, 0x0, 0, 0) | ||
| 47 | #define _MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC IOMUX_PAD(0x34C, 0x24, 2, 0x758, 0, 0) | ||
| 48 | #define _MX53_PAD_KEY_COL0__UART4_TXD_MUX IOMUX_PAD(0x34C, 0x24, 4, 0x0, 0, 0) | ||
| 49 | #define _MX53_PAD_KEY_COL0__ECSPI1_SCLK IOMUX_PAD(0x34C, 0x24, 5, 0x79C, 0, 0) | ||
| 50 | #define _MX53_PAD_KEY_COL0__FEC_RDATA_3 IOMUX_PAD(0x34C, 0x24, 6, 0x0, 0, 0) | ||
| 51 | #define _MX53_PAD_KEY_COL0__SRC_ANY_PU_RST IOMUX_PAD(0x34C, 0x24, 7, 0x0, 0, 0) | ||
| 52 | #define _MX53_PAD_KEY_ROW0__KPP_ROW_0 IOMUX_PAD(0x350, 0x28, 0, 0x0, 0, 0) | ||
| 53 | #define _MX53_PAD_KEY_ROW0__GPIO4_7 IOMUX_PAD(0x350, 0x28, 1, 0x0, 0, 0) | ||
| 54 | #define _MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD IOMUX_PAD(0x350, 0x28, 2, 0x74C, 0, 0) | ||
| 55 | #define _MX53_PAD_KEY_ROW0__UART4_RXD_MUX IOMUX_PAD(0x350, 0x28, 4, 0x890, 1, 0) | ||
| 56 | #define _MX53_PAD_KEY_ROW0__ECSPI1_MOSI IOMUX_PAD(0x350, 0x28, 5, 0x7A4, 0, 0) | ||
| 57 | #define _MX53_PAD_KEY_ROW0__FEC_TX_ER IOMUX_PAD(0x350, 0x28, 6, 0x0, 0, 0) | ||
| 58 | #define _MX53_PAD_KEY_COL1__KPP_COL_1 IOMUX_PAD(0x354, 0x2C, 0, 0x0, 0, 0) | ||
| 59 | #define _MX53_PAD_KEY_COL1__GPIO4_8 IOMUX_PAD(0x354, 0x2C, 1, 0x0, 0, 0) | ||
| 60 | #define _MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS IOMUX_PAD(0x354, 0x2C, 2, 0x75C, 0, 0) | ||
| 61 | #define _MX53_PAD_KEY_COL1__UART5_TXD_MUX IOMUX_PAD(0x354, 0x2C, 4, 0x0, 0, 0) | ||
| 62 | #define _MX53_PAD_KEY_COL1__ECSPI1_MISO IOMUX_PAD(0x354, 0x2C, 5, 0x7A0, 0, 0) | ||
| 63 | #define _MX53_PAD_KEY_COL1__FEC_RX_CLK IOMUX_PAD(0x354, 0x2C, 6, 0x808, 0, 0) | ||
| 64 | #define _MX53_PAD_KEY_COL1__USBPHY1_TXREADY IOMUX_PAD(0x354, 0x2C, 7, 0x0, 0, 0) | ||
| 65 | #define _MX53_PAD_KEY_ROW1__KPP_ROW_1 IOMUX_PAD(0x358, 0x30, 0, 0x0, 0, 0) | ||
| 66 | #define _MX53_PAD_KEY_ROW1__GPIO4_9 IOMUX_PAD(0x358, 0x30, 1, 0x0, 0, 0) | ||
| 67 | #define _MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD IOMUX_PAD(0x358, 0x30, 2, 0x748, 0, 0) | ||
| 68 | #define _MX53_PAD_KEY_ROW1__UART5_RXD_MUX IOMUX_PAD(0x358, 0x30, 4, 0x898, 1, 0) | ||
| 69 | #define _MX53_PAD_KEY_ROW1__ECSPI1_SS0 IOMUX_PAD(0x358, 0x30, 5, 0x7A8, 0, 0) | ||
| 70 | #define _MX53_PAD_KEY_ROW1__FEC_COL IOMUX_PAD(0x358, 0x30, 6, 0x800, 0, 0) | ||
| 71 | #define _MX53_PAD_KEY_ROW1__USBPHY1_RXVALID IOMUX_PAD(0x358, 0x30, 7, 0x0, 0, 0) | ||
| 72 | #define _MX53_PAD_KEY_COL2__KPP_COL_2 IOMUX_PAD(0x35C, 0x34, 0, 0x0, 0, 0) | ||
| 73 | #define _MX53_PAD_KEY_COL2__GPIO4_10 IOMUX_PAD(0x35C, 0x34, 1, 0x0, 0, 0) | ||
| 74 | #define _MX53_PAD_KEY_COL2__CAN1_TXCAN IOMUX_PAD(0x35C, 0x34, 2, 0x0, 0, 0) | ||
| 75 | #define _MX53_PAD_KEY_COL2__FEC_MDIO IOMUX_PAD(0x35C, 0x34, 4, 0x804, 0, 0) | ||
| 76 | #define _MX53_PAD_KEY_COL2__ECSPI1_SS1 IOMUX_PAD(0x35C, 0x34, 5, 0x7AC, 0, 0) | ||
| 77 | #define _MX53_PAD_KEY_COL2__FEC_RDATA_2 IOMUX_PAD(0x35C, 0x34, 6, 0x0, 0, 0) | ||
| 78 | #define _MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE IOMUX_PAD(0x35C, 0x34, 7, 0x0, 0, 0) | ||
| 79 | #define _MX53_PAD_KEY_ROW2__KPP_ROW_2 IOMUX_PAD(0x360, 0x38, 0, 0x0, 0, 0) | ||
| 80 | #define _MX53_PAD_KEY_ROW2__GPIO4_11 IOMUX_PAD(0x360, 0x38, 1, 0x0, 0, 0) | ||
| 81 | #define _MX53_PAD_KEY_ROW2__CAN1_RXCAN IOMUX_PAD(0x360, 0x38, 2, 0x760, 0, 0) | ||
| 82 | #define _MX53_PAD_KEY_ROW2__FEC_MDC IOMUX_PAD(0x360, 0x38, 4, 0x0, 0, 0) | ||
| 83 | #define _MX53_PAD_KEY_ROW2__ECSPI1_SS2 IOMUX_PAD(0x360, 0x38, 5, 0x7B0, 0, 0) | ||
| 84 | #define _MX53_PAD_KEY_ROW2__FEC_TDATA_2 IOMUX_PAD(0x360, 0x38, 6, 0x0, 0, 0) | ||
| 85 | #define _MX53_PAD_KEY_ROW2__USBPHY1_RXERROR IOMUX_PAD(0x360, 0x38, 7, 0x0, 0, 0) | ||
| 86 | #define _MX53_PAD_KEY_COL3__KPP_COL_3 IOMUX_PAD(0x364, 0x3C, 0, 0x0, 0, 0) | ||
| 87 | #define _MX53_PAD_KEY_COL3__GPIO4_12 IOMUX_PAD(0x364, 0x3C, 1, 0x0, 0, 0) | ||
| 88 | #define _MX53_PAD_KEY_COL3__USBOH3_H2_DP IOMUX_PAD(0x364, 0x3C, 2, 0x0, 0, 0) | ||
| 89 | #define _MX53_PAD_KEY_COL3__SPDIF_IN1 IOMUX_PAD(0x364, 0x3C, 3, 0x870, 0, 0) | ||
| 90 | #define _MX53_PAD_KEY_COL3__I2C2_SCL IOMUX_PAD(0x364, 0x3C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, 0) | ||
| 91 | #define _MX53_PAD_KEY_COL3__ECSPI1_SS3 IOMUX_PAD(0x364, 0x3C, 5, 0x7B4, 0, 0) | ||
| 92 | #define _MX53_PAD_KEY_COL3__FEC_CRS IOMUX_PAD(0x364, 0x3C, 6, 0x0, 0, 0) | ||
| 93 | #define _MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK IOMUX_PAD(0x364, 0x3C, 7, 0x0, 0, 0) | ||
| 94 | #define _MX53_PAD_KEY_ROW3__KPP_ROW_3 IOMUX_PAD(0x368, 0x40, 0, 0x0, 0, 0) | ||
| 95 | #define _MX53_PAD_KEY_ROW3__GPIO4_13 IOMUX_PAD(0x368, 0x40, 1, 0x0, 0, 0) | ||
| 96 | #define _MX53_PAD_KEY_ROW3__USBOH3_H2_DM IOMUX_PAD(0x368, 0x40, 2, 0x0, 0, 0) | ||
| 97 | #define _MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK IOMUX_PAD(0x368, 0x40, 3, 0x768, 0, 0) | ||
| 98 | #define _MX53_PAD_KEY_ROW3__I2C2_SDA IOMUX_PAD(0x368, 0x40, 4 | IOMUX_CONFIG_SION, 0x820, 0, 0) | ||
| 99 | #define _MX53_PAD_KEY_ROW3__OSC32K_32K_OUT IOMUX_PAD(0x368, 0x40, 5, 0x0, 0, 0) | ||
| 100 | #define _MX53_PAD_KEY_ROW3__CCM_PLL4_BYP IOMUX_PAD(0x368, 0x40, 6, 0x77C, 0, 0) | ||
| 101 | #define _MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 IOMUX_PAD(0x368, 0x40, 7, 0x0, 0, 0) | ||
| 102 | #define _MX53_PAD_KEY_COL4__KPP_COL_4 IOMUX_PAD(0x36C, 0x44, 0, 0x0, 0, 0) | ||
| 103 | #define _MX53_PAD_KEY_COL4__GPIO4_14 IOMUX_PAD(0x36C, 0x44, 1, 0x0, 0, 0) | ||
| 104 | #define _MX53_PAD_KEY_COL4__CAN2_TXCAN IOMUX_PAD(0x36C, 0x44, 2, 0x0, 0, 0) | ||
| 105 | #define _MX53_PAD_KEY_COL4__IPU_SISG_4 IOMUX_PAD(0x36C, 0x44, 3, 0x0, 0, 0) | ||
| 106 | #define _MX53_PAD_KEY_COL4__UART5_RTS IOMUX_PAD(0x36C, 0x44, 4, 0x894, 0, 0) | ||
| 107 | #define _MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC IOMUX_PAD(0x36C, 0x44, 5, 0x89C, 0, 0) | ||
| 108 | #define _MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 IOMUX_PAD(0x36C, 0x44, 7, 0x0, 0, 0) | ||
| 109 | #define _MX53_PAD_KEY_ROW4__KPP_ROW_4 IOMUX_PAD(0x370, 0x48, 0, 0x0, 0, 0) | ||
| 110 | #define _MX53_PAD_KEY_ROW4__GPIO4_15 IOMUX_PAD(0x370, 0x48, 1, 0x0, 0, 0) | ||
| 111 | #define _MX53_PAD_KEY_ROW4__CAN2_RXCAN IOMUX_PAD(0x370, 0x48, 2, 0x764, 0, 0) | ||
| 112 | #define _MX53_PAD_KEY_ROW4__IPU_SISG_5 IOMUX_PAD(0x370, 0x48, 3, 0x0, 0, 0) | ||
| 113 | #define _MX53_PAD_KEY_ROW4__UART5_CTS IOMUX_PAD(0x370, 0x48, 4, 0x0, 0, 0) | ||
| 114 | #define _MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR IOMUX_PAD(0x370, 0x48, 5, 0x0, 0, 0) | ||
| 115 | #define _MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID IOMUX_PAD(0x370, 0x48, 7, 0x0, 0, 0) | ||
| 116 | #define _MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK IOMUX_PAD(0x378, 0x4C, 0, 0x0, 0, 0) | ||
| 117 | #define _MX53_PAD_DI0_DISP_CLK__GPIO4_16 IOMUX_PAD(0x378, 0x4C, 1, 0x0, 0, 0) | ||
| 118 | #define _MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR IOMUX_PAD(0x378, 0x4C, 2, 0x0, 0, 0) | ||
| 119 | #define _MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 IOMUX_PAD(0x378, 0x4C, 5, 0x0, 0, 0) | ||
| 120 | #define _MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 IOMUX_PAD(0x378, 0x4C, 6, 0x0, 0, 0) | ||
| 121 | #define _MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID IOMUX_PAD(0x378, 0x4C, 7, 0x0, 0, 0) | ||
| 122 | #define _MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 IOMUX_PAD(0x37C, 0x50, 0, 0x0, 0, 0) | ||
| 123 | #define _MX53_PAD_DI0_PIN15__GPIO4_17 IOMUX_PAD(0x37C, 0x50, 1, 0x0, 0, 0) | ||
| 124 | #define _MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC IOMUX_PAD(0x37C, 0x50, 2, 0x0, 0, 0) | ||
| 125 | #define _MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 IOMUX_PAD(0x37C, 0x50, 5, 0x0, 0, 0) | ||
| 126 | #define _MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 IOMUX_PAD(0x37C, 0x50, 6, 0x0, 0, 0) | ||
| 127 | #define _MX53_PAD_DI0_PIN15__USBPHY1_BVALID IOMUX_PAD(0x37C, 0x50, 7, 0x0, 0, 0) | ||
| 128 | #define _MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 IOMUX_PAD(0x380, 0x54, 0, 0x0, 0, 0) | ||
| 129 | #define _MX53_PAD_DI0_PIN2__GPIO4_18 IOMUX_PAD(0x380, 0x54, 1, 0x0, 0, 0) | ||
| 130 | #define _MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD IOMUX_PAD(0x380, 0x54, 2, 0x0, 0, 0) | ||
| 131 | #define _MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 IOMUX_PAD(0x380, 0x54, 5, 0x0, 0, 0) | ||
| 132 | #define _MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 IOMUX_PAD(0x380, 0x54, 6, 0x0, 0, 0) | ||
| 133 | #define _MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION IOMUX_PAD(0x380, 0x54, 7, 0x0, 0, 0) | ||
| 134 | #define _MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 IOMUX_PAD(0x384, 0x58, 0, 0x0, 0, 0) | ||
| 135 | #define _MX53_PAD_DI0_PIN3__GPIO4_19 IOMUX_PAD(0x384, 0x58, 1, 0x0, 0, 0) | ||
| 136 | #define _MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS IOMUX_PAD(0x384, 0x58, 2, 0x0, 0, 0) | ||
| 137 | #define _MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 IOMUX_PAD(0x384, 0x58, 5, 0x0, 0, 0) | ||
| 138 | #define _MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 IOMUX_PAD(0x384, 0x58, 6, 0x0, 0, 0) | ||
| 139 | #define _MX53_PAD_DI0_PIN3__USBPHY1_IDDIG IOMUX_PAD(0x384, 0x58, 7, 0x0, 0, 0) | ||
| 140 | #define _MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 IOMUX_PAD(0x388, 0x5C, 0, 0x0, 0, 0) | ||
| 141 | #define _MX53_PAD_DI0_PIN4__GPIO4_20 IOMUX_PAD(0x388, 0x5C, 1, 0x0, 0, 0) | ||
| 142 | #define _MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD IOMUX_PAD(0x388, 0x5C, 2, 0x0, 0, 0) | ||
| 143 | #define _MX53_PAD_DI0_PIN4__ESDHC1_WP IOMUX_PAD(0x388, 0x5C, 3, 0x7FC, 0, 0) | ||
| 144 | #define _MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD IOMUX_PAD(0x388, 0x5C, 5, 0x0, 0, 0) | ||
| 145 | #define _MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 IOMUX_PAD(0x388, 0x5C, 6, 0x0, 0, 0) | ||
| 146 | #define _MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT IOMUX_PAD(0x388, 0x5C, 7, 0x0, 0, 0) | ||
| 147 | #define _MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 IOMUX_PAD(0x38C, 0x60, 0, 0x0, 0, 0) | ||
| 148 | #define _MX53_PAD_DISP0_DAT0__GPIO4_21 IOMUX_PAD(0x38C, 0x60, 1, 0x0, 0, 0) | ||
| 149 | #define _MX53_PAD_DISP0_DAT0__CSPI_SCLK IOMUX_PAD(0x38C, 0x60, 2, 0x780, 0, 0) | ||
| 150 | #define _MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 IOMUX_PAD(0x38C, 0x60, 3, 0x0, 0, 0) | ||
| 151 | #define _MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN IOMUX_PAD(0x38C, 0x60, 5, 0x0, 0, 0) | ||
| 152 | #define _MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 IOMUX_PAD(0x38C, 0x60, 6, 0x0, 0, 0) | ||
| 153 | #define _MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY IOMUX_PAD(0x38C, 0x60, 7, 0x0, 0, 0) | ||
| 154 | #define _MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 IOMUX_PAD(0x390, 0x64, 0, 0x0, 0, 0) | ||
| 155 | #define _MX53_PAD_DISP0_DAT1__GPIO4_22 IOMUX_PAD(0x390, 0x64, 1, 0x0, 0, 0) | ||
| 156 | #define _MX53_PAD_DISP0_DAT1__CSPI_MOSI IOMUX_PAD(0x390, 0x64, 2, 0x788, 0, 0) | ||
| 157 | #define _MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 IOMUX_PAD(0x390, 0x64, 3, 0x0, 0, 0) | ||
| 158 | #define _MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL IOMUX_PAD(0x390, 0x64, 5, 0x0, 0, 0) | ||
| 159 | #define _MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 IOMUX_PAD(0x390, 0x64, 6, 0x0, 0, 0) | ||
| 160 | #define _MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID IOMUX_PAD(0x390, 0x64, 7, 0x0, 0, 0) | ||
| 161 | #define _MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 IOMUX_PAD(0x394, 0x68, 0, 0x0, 0, 0) | ||
| 162 | #define _MX53_PAD_DISP0_DAT2__GPIO4_23 IOMUX_PAD(0x394, 0x68, 1, 0x0, 0, 0) | ||
| 163 | #define _MX53_PAD_DISP0_DAT2__CSPI_MISO IOMUX_PAD(0x394, 0x68, 2, 0x784, 0, 0) | ||
| 164 | #define _MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 IOMUX_PAD(0x394, 0x68, 3, 0x0, 0, 0) | ||
| 165 | #define _MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE IOMUX_PAD(0x394, 0x68, 5, 0x0, 0, 0) | ||
| 166 | #define _MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 IOMUX_PAD(0x394, 0x68, 6, 0x0, 0, 0) | ||
| 167 | #define _MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE IOMUX_PAD(0x394, 0x68, 7, 0x0, 0, 0) | ||
| 168 | #define _MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 IOMUX_PAD(0x398, 0x6C, 0, 0x0, 0, 0) | ||
| 169 | #define _MX53_PAD_DISP0_DAT3__GPIO4_24 IOMUX_PAD(0x398, 0x6C, 1, 0x0, 0, 0) | ||
| 170 | #define _MX53_PAD_DISP0_DAT3__CSPI_SS0 IOMUX_PAD(0x398, 0x6C, 2, 0x78C, 0, 0) | ||
| 171 | #define _MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 IOMUX_PAD(0x398, 0x6C, 3, 0x0, 0, 0) | ||
| 172 | #define _MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR IOMUX_PAD(0x398, 0x6C, 5, 0x0, 0, 0) | ||
| 173 | #define _MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 IOMUX_PAD(0x398, 0x6C, 6, 0x0, 0, 0) | ||
| 174 | #define _MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR IOMUX_PAD(0x398, 0x6C, 7, 0x0, 0, 0) | ||
| 175 | #define _MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 IOMUX_PAD(0x39C, 0x70, 0, 0x0, 0, 0) | ||
| 176 | #define _MX53_PAD_DISP0_DAT4__GPIO4_25 IOMUX_PAD(0x39C, 0x70, 1, 0x0, 0, 0) | ||
| 177 | #define _MX53_PAD_DISP0_DAT4__CSPI_SS1 IOMUX_PAD(0x39C, 0x70, 2, 0x790, 0, 0) | ||
| 178 | #define _MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 IOMUX_PAD(0x39C, 0x70, 3, 0x0, 0, 0) | ||
| 179 | #define _MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB IOMUX_PAD(0x39C, 0x70, 5, 0x0, 0, 0) | ||
| 180 | #define _MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 IOMUX_PAD(0x39C, 0x70, 6, 0x0, 0, 0) | ||
| 181 | #define _MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK IOMUX_PAD(0x39C, 0x70, 7, 0x0, 0, 0) | ||
| 182 | #define _MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 IOMUX_PAD(0x3A0, 0x74, 0, 0x0, 0, 0) | ||
| 183 | #define _MX53_PAD_DISP0_DAT5__GPIO4_26 IOMUX_PAD(0x3A0, 0x74, 1, 0x0, 0, 0) | ||
| 184 | #define _MX53_PAD_DISP0_DAT5__CSPI_SS2 IOMUX_PAD(0x3A0, 0x74, 2, 0x794, 0, 0) | ||
| 185 | #define _MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 IOMUX_PAD(0x3A0, 0x74, 3, 0x0, 0, 0) | ||
| 186 | #define _MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS IOMUX_PAD(0x3A0, 0x74, 5, 0x0, 0, 0) | ||
| 187 | #define _MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 IOMUX_PAD(0x3A0, 0x74, 6, 0x0, 0, 0) | ||
| 188 | #define _MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 IOMUX_PAD(0x3A0, 0x74, 7, 0x0, 0, 0) | ||
| 189 | #define _MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 IOMUX_PAD(0x3A4, 0x78, 0, 0x0, 0, 0) | ||
| 190 | #define _MX53_PAD_DISP0_DAT6__GPIO4_27 IOMUX_PAD(0x3A4, 0x78, 1, 0x0, 0, 0) | ||
| 191 | #define _MX53_PAD_DISP0_DAT6__CSPI_SS3 IOMUX_PAD(0x3A4, 0x78, 2, 0x798, 0, 0) | ||
| 192 | #define _MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 IOMUX_PAD(0x3A4, 0x78, 3, 0x0, 0, 0) | ||
| 193 | #define _MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x3A4, 0x78, 5, 0x0, 0, 0) | ||
| 194 | #define _MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 IOMUX_PAD(0x3A4, 0x78, 6, 0x0, 0, 0) | ||
| 195 | #define _MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 IOMUX_PAD(0x3A4, 0x78, 7, 0x0, 0, 0) | ||
| 196 | #define _MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 IOMUX_PAD(0x3A8, 0x7C, 0, 0x0, 0, 0) | ||
| 197 | #define _MX53_PAD_DISP0_DAT7__GPIO4_28 IOMUX_PAD(0x3A8, 0x7C, 1, 0x0, 0, 0) | ||
| 198 | #define _MX53_PAD_DISP0_DAT7__CSPI_RDY IOMUX_PAD(0x3A8, 0x7C, 2, 0x0, 0, 0) | ||
| 199 | #define _MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 IOMUX_PAD(0x3A8, 0x7C, 3, 0x0, 0, 0) | ||
| 200 | #define _MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x3A8, 0x7C, 5, 0x0, 0, 0) | ||
| 201 | #define _MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 IOMUX_PAD(0x3A8, 0x7C, 6, 0x0, 0, 0) | ||
| 202 | #define _MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID IOMUX_PAD(0x3A8, 0x7C, 7, 0x0, 0, 0) | ||
| 203 | #define _MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 IOMUX_PAD(0x3AC, 0x80, 0, 0x0, 0, 0) | ||
| 204 | #define _MX53_PAD_DISP0_DAT8__GPIO4_29 IOMUX_PAD(0x3AC, 0x80, 1, 0x0, 0, 0) | ||
| 205 | #define _MX53_PAD_DISP0_DAT8__PWM1_PWMO IOMUX_PAD(0x3AC, 0x80, 2, 0x0, 0, 0) | ||
| 206 | #define _MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B IOMUX_PAD(0x3AC, 0x80, 3, 0x0, 0, 0) | ||
| 207 | #define _MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x3AC, 0x80, 5, 0x0, 0, 0) | ||
| 208 | #define _MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 IOMUX_PAD(0x3AC, 0x80, 6, 0x0, 0, 0) | ||
| 209 | #define _MX53_PAD_DISP0_DAT8__USBPHY2_AVALID IOMUX_PAD(0x3AC, 0x80, 7, 0x0, 0, 0) | ||
| 210 | #define _MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 IOMUX_PAD(0x3B0, 0x84, 0, 0x0, 0, 0) | ||
| 211 | #define _MX53_PAD_DISP0_DAT9__GPIO4_30 IOMUX_PAD(0x3B0, 0x84, 1, 0x0, 0, 0) | ||
| 212 | #define _MX53_PAD_DISP0_DAT9__PWM2_PWMO IOMUX_PAD(0x3B0, 0x84, 2, 0x0, 0, 0) | ||
| 213 | #define _MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B IOMUX_PAD(0x3B0, 0x84, 3, 0x0, 0, 0) | ||
| 214 | #define _MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x3B0, 0x84, 5, 0x0, 0, 0) | ||
| 215 | #define _MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 IOMUX_PAD(0x3B0, 0x84, 6, 0x0, 0, 0) | ||
| 216 | #define _MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 IOMUX_PAD(0x3B0, 0x84, 7, 0x0, 0, 0) | ||
| 217 | #define _MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 IOMUX_PAD(0x3B4, 0x88, 0, 0x0, 0, 0) | ||
| 218 | #define _MX53_PAD_DISP0_DAT10__GPIO4_31 IOMUX_PAD(0x3B4, 0x88, 1, 0x0, 0, 0) | ||
| 219 | #define _MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP IOMUX_PAD(0x3B4, 0x88, 2, 0x0, 0, 0) | ||
| 220 | #define _MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 IOMUX_PAD(0x3B4, 0x88, 5, 0x0, 0, 0) | ||
| 221 | #define _MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 IOMUX_PAD(0x3B4, 0x88, 6, 0x0, 0, 0) | ||
| 222 | #define _MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 IOMUX_PAD(0x3B4, 0x88, 7, 0x0, 0, 0) | ||
| 223 | #define _MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 IOMUX_PAD(0x3B8, 0x8C, 0, 0x0, 0, 0) | ||
| 224 | #define _MX53_PAD_DISP0_DAT11__GPIO5_5 IOMUX_PAD(0x3B8, 0x8C, 1, 0x0, 0, 0) | ||
| 225 | #define _MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT IOMUX_PAD(0x3B8, 0x8C, 2, 0x0, 0, 0) | ||
| 226 | #define _MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 IOMUX_PAD(0x3B8, 0x8C, 5, 0x0, 0, 0) | ||
| 227 | #define _MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 IOMUX_PAD(0x3B8, 0x8C, 6, 0x0, 0, 0) | ||
| 228 | #define _MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 IOMUX_PAD(0x3B8, 0x8C, 7, 0x0, 0, 0) | ||
| 229 | #define _MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 IOMUX_PAD(0x3BC, 0x90, 0, 0x0, 0, 0) | ||
| 230 | #define _MX53_PAD_DISP0_DAT12__GPIO5_6 IOMUX_PAD(0x3BC, 0x90, 1, 0x0, 0, 0) | ||
| 231 | #define _MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK IOMUX_PAD(0x3BC, 0x90, 2, 0x0, 0, 0) | ||
| 232 | #define _MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 IOMUX_PAD(0x3BC, 0x90, 5, 0x0, 0, 0) | ||
| 233 | #define _MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 IOMUX_PAD(0x3BC, 0x90, 6, 0x0, 0, 0) | ||
| 234 | #define _MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 IOMUX_PAD(0x3BC, 0x90, 7, 0x0, 0, 0) | ||
| 235 | #define _MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 IOMUX_PAD(0x3C0, 0x94, 0, 0x0, 0, 0) | ||
| 236 | #define _MX53_PAD_DISP0_DAT13__GPIO5_7 IOMUX_PAD(0x3C0, 0x94, 1, 0x0, 0, 0) | ||
| 237 | #define _MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS IOMUX_PAD(0x3C0, 0x94, 3, 0x754, 0, 0) | ||
| 238 | #define _MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 IOMUX_PAD(0x3C0, 0x94, 5, 0x0, 0, 0) | ||
| 239 | #define _MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 IOMUX_PAD(0x3C0, 0x94, 6, 0x0, 0, 0) | ||
| 240 | #define _MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 IOMUX_PAD(0x3C0, 0x94, 7, 0x0, 0, 0) | ||
| 241 | #define _MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 IOMUX_PAD(0x3C4, 0x98, 0, 0x0, 0, 0) | ||
| 242 | #define _MX53_PAD_DISP0_DAT14__GPIO5_8 IOMUX_PAD(0x3C4, 0x98, 1, 0x0, 0, 0) | ||
| 243 | #define _MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC IOMUX_PAD(0x3C4, 0x98, 3, 0x750, 0, 0) | ||
| 244 | #define _MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 IOMUX_PAD(0x3C4, 0x98, 5, 0x0, 0, 0) | ||
| 245 | #define _MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 IOMUX_PAD(0x3C4, 0x98, 6, 0x0, 0, 0) | ||
| 246 | #define _MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 IOMUX_PAD(0x3C4, 0x98, 7, 0x0, 0, 0) | ||
| 247 | #define _MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 IOMUX_PAD(0x3C8, 0x9C, 0, 0x0, 0, 0) | ||
| 248 | #define _MX53_PAD_DISP0_DAT15__GPIO5_9 IOMUX_PAD(0x3C8, 0x9C, 1, 0x0, 0, 0) | ||
| 249 | #define _MX53_PAD_DISP0_DAT15__ECSPI1_SS1 IOMUX_PAD(0x3C8, 0x9C, 2, 0x7AC, 1, 0) | ||
| 250 | #define _MX53_PAD_DISP0_DAT15__ECSPI2_SS1 IOMUX_PAD(0x3C8, 0x9C, 3, 0x7C8, 0, 0) | ||
| 251 | #define _MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 IOMUX_PAD(0x3C8, 0x9C, 5, 0x0, 0, 0) | ||
| 252 | #define _MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 IOMUX_PAD(0x3C8, 0x9C, 6, 0x0, 0, 0) | ||
| 253 | #define _MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 IOMUX_PAD(0x3C8, 0x9C, 7, 0x0, 0, 0) | ||
| 254 | #define _MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 IOMUX_PAD(0x3CC, 0xA0, 0, 0x0, 0, 0) | ||
| 255 | #define _MX53_PAD_DISP0_DAT16__GPIO5_10 IOMUX_PAD(0x3CC, 0xA0, 1, 0x0, 0, 0) | ||
| 256 | #define _MX53_PAD_DISP0_DAT16__ECSPI2_MOSI IOMUX_PAD(0x3CC, 0xA0, 2, 0x7C0, 0, 0) | ||
| 257 | #define _MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC IOMUX_PAD(0x3CC, 0xA0, 3, 0x758, 1, 0) | ||
| 258 | #define _MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 IOMUX_PAD(0x3CC, 0xA0, 4, 0x868, 0, 0) | ||
| 259 | #define _MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 IOMUX_PAD(0x3CC, 0xA0, 5, 0x0, 0, 0) | ||
| 260 | #define _MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 IOMUX_PAD(0x3CC, 0xA0, 6, 0x0, 0, 0) | ||
| 261 | #define _MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 IOMUX_PAD(0x3CC, 0xA0, 7, 0x0, 0, 0) | ||
| 262 | #define _MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 IOMUX_PAD(0x3D0, 0xA4, 0, 0x0, 0, 0) | ||
| 263 | #define _MX53_PAD_DISP0_DAT17__GPIO5_11 IOMUX_PAD(0x3D0, 0xA4, 1, 0x0, 0, 0) | ||
| 264 | #define _MX53_PAD_DISP0_DAT17__ECSPI2_MISO IOMUX_PAD(0x3D0, 0xA4, 2, 0x7BC, 0, 0) | ||
| 265 | #define _MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD IOMUX_PAD(0x3D0, 0xA4, 3, 0x74C, 1, 0) | ||
| 266 | #define _MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 IOMUX_PAD(0x3D0, 0xA4, 4, 0x86C, 0, 0) | ||
| 267 | #define _MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 IOMUX_PAD(0x3D0, 0xA4, 5, 0x0, 0, 0) | ||
| 268 | #define _MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 IOMUX_PAD(0x3D0, 0xA4, 6, 0x0, 0, 0) | ||
| 269 | #define _MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 IOMUX_PAD(0x3D4, 0xA8, 0, 0x0, 0, 0) | ||
| 270 | #define _MX53_PAD_DISP0_DAT18__GPIO5_12 IOMUX_PAD(0x3D4, 0xA8, 1, 0x0, 0, 0) | ||
| 271 | #define _MX53_PAD_DISP0_DAT18__ECSPI2_SS0 IOMUX_PAD(0x3D4, 0xA8, 2, 0x7C4, 0, 0) | ||
| 272 | #define _MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS IOMUX_PAD(0x3D4, 0xA8, 3, 0x75C, 1, 0) | ||
| 273 | #define _MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS IOMUX_PAD(0x3D4, 0xA8, 4, 0x73C, 0, 0) | ||
| 274 | #define _MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 IOMUX_PAD(0x3D4, 0xA8, 5, 0x0, 0, 0) | ||
| 275 | #define _MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 IOMUX_PAD(0x3D4, 0xA8, 6, 0x0, 0, 0) | ||
| 276 | #define _MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 IOMUX_PAD(0x3D4, 0xA8, 7, 0x0, 0, 0) | ||
| 277 | #define _MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 IOMUX_PAD(0x3D8, 0xAC, 0, 0x0, 0, 0) | ||
| 278 | #define _MX53_PAD_DISP0_DAT19__GPIO5_13 IOMUX_PAD(0x3D8, 0xAC, 1, 0x0, 0, 0) | ||
| 279 | #define _MX53_PAD_DISP0_DAT19__ECSPI2_SCLK IOMUX_PAD(0x3D8, 0xAC, 2, 0x7B8, 0, 0) | ||
| 280 | #define _MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD IOMUX_PAD(0x3D8, 0xAC, 3, 0x748, 1, 0) | ||
| 281 | #define _MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC IOMUX_PAD(0x3D8, 0xAC, 4, 0x738, 0, 0) | ||
| 282 | #define _MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 IOMUX_PAD(0x3D8, 0xAC, 5, 0x0, 0, 0) | ||
| 283 | #define _MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 IOMUX_PAD(0x3D8, 0xAC, 6, 0x0, 0, 0) | ||
| 284 | #define _MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 IOMUX_PAD(0x3D8, 0xAC, 7, 0x0, 0, 0) | ||
| 285 | #define _MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 IOMUX_PAD(0x3DC, 0xB0, 0, 0x0, 0, 0) | ||
| 286 | #define _MX53_PAD_DISP0_DAT20__GPIO5_14 IOMUX_PAD(0x3DC, 0xB0, 1, 0x0, 0, 0) | ||
| 287 | #define _MX53_PAD_DISP0_DAT20__ECSPI1_SCLK IOMUX_PAD(0x3DC, 0xB0, 2, 0x79C, 1, 0) | ||
| 288 | #define _MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC IOMUX_PAD(0x3DC, 0xB0, 3, 0x740, 0, 0) | ||
| 289 | #define _MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 IOMUX_PAD(0x3DC, 0xB0, 5, 0x0, 0, 0) | ||
| 290 | #define _MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 IOMUX_PAD(0x3DC, 0xB0, 6, 0x0, 0, 0) | ||
| 291 | #define _MX53_PAD_DISP0_DAT20__SATA_PHY_TDI IOMUX_PAD(0x3DC, 0xB0, 7, 0x0, 0, 0) | ||
| 292 | #define _MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 IOMUX_PAD(0x3E0, 0xB4, 0, 0x0, 0, 0) | ||
| 293 | #define _MX53_PAD_DISP0_DAT21__GPIO5_15 IOMUX_PAD(0x3E0, 0xB4, 1, 0x0, 0, 0) | ||
| 294 | #define _MX53_PAD_DISP0_DAT21__ECSPI1_MOSI IOMUX_PAD(0x3E0, 0xB4, 2, 0x7A4, 1, 0) | ||
| 295 | #define _MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD IOMUX_PAD(0x3E0, 0xB4, 3, 0x734, 0, 0) | ||
| 296 | #define _MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 IOMUX_PAD(0x3E0, 0xB4, 5, 0x0, 0, 0) | ||
| 297 | #define _MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 IOMUX_PAD(0x3E0, 0xB4, 6, 0x0, 0, 0) | ||
| 298 | #define _MX53_PAD_DISP0_DAT21__SATA_PHY_TDO IOMUX_PAD(0x3E0, 0xB4, 7, 0x0, 0, 0) | ||
| 299 | #define _MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 IOMUX_PAD(0x3E4, 0xB8, 0, 0x0, 0, 0) | ||
| 300 | #define _MX53_PAD_DISP0_DAT22__GPIO5_16 IOMUX_PAD(0x3E4, 0xB8, 1, 0x0, 0, 0) | ||
| 301 | #define _MX53_PAD_DISP0_DAT22__ECSPI1_MISO IOMUX_PAD(0x3E4, 0xB8, 2, 0x7A0, 1, 0) | ||
| 302 | #define _MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS IOMUX_PAD(0x3E4, 0xB8, 3, 0x744, 0, 0) | ||
| 303 | #define _MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 IOMUX_PAD(0x3E4, 0xB8, 5, 0x0, 0, 0) | ||
| 304 | #define _MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 IOMUX_PAD(0x3E4, 0xB8, 6, 0x0, 0, 0) | ||
| 305 | #define _MX53_PAD_DISP0_DAT22__SATA_PHY_TCK IOMUX_PAD(0x3E4, 0xB8, 7, 0x0, 0, 0) | ||
| 306 | #define _MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 IOMUX_PAD(0x3E8, 0xBC, 0, 0x0, 0, 0) | ||
| 307 | #define _MX53_PAD_DISP0_DAT23__GPIO5_17 IOMUX_PAD(0x3E8, 0xBC, 1, 0x0, 0, 0) | ||
| 308 | #define _MX53_PAD_DISP0_DAT23__ECSPI1_SS0 IOMUX_PAD(0x3E8, 0xBC, 2, 0x7A8, 1, 0) | ||
| 309 | #define _MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD IOMUX_PAD(0x3E8, 0xBC, 3, 0x730, 0, 0) | ||
| 310 | #define _MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 IOMUX_PAD(0x3E8, 0xBC, 5, 0x0, 0, 0) | ||
| 311 | #define _MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 IOMUX_PAD(0x3E8, 0xBC, 6, 0x0, 0, 0) | ||
| 312 | #define _MX53_PAD_DISP0_DAT23__SATA_PHY_TMS IOMUX_PAD(0x3E8, 0xBC, 7, 0x0, 0, 0) | ||
| 313 | #define _MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK IOMUX_PAD(0x3EC, 0xC0, 0, 0x0, 0, 0) | ||
| 314 | #define _MX53_PAD_CSI0_PIXCLK__GPIO5_18 IOMUX_PAD(0x3EC, 0xC0, 1, 0x0, 0, 0) | ||
| 315 | #define _MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 IOMUX_PAD(0x3EC, 0xC0, 5, 0x0, 0, 0) | ||
| 316 | #define _MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 IOMUX_PAD(0x3EC, 0xC0, 6, 0x0, 0, 0) | ||
| 317 | #define _MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC IOMUX_PAD(0x3F0, 0xC4, 0, 0x0, 0, 0) | ||
| 318 | #define _MX53_PAD_CSI0_MCLK__GPIO5_19 IOMUX_PAD(0x3F0, 0xC4, 1, 0x0, 0, 0) | ||
| 319 | #define _MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK IOMUX_PAD(0x3F0, 0xC4, 2, 0x0, 0, 0) | ||
| 320 | #define _MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 IOMUX_PAD(0x3F0, 0xC4, 5, 0x0, 0, 0) | ||
| 321 | #define _MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 IOMUX_PAD(0x3F0, 0xC4, 6, 0x0, 0, 0) | ||
| 322 | #define _MX53_PAD_CSI0_MCLK__TPIU_TRCTL IOMUX_PAD(0x3F0, 0xC4, 7, 0x0, 0, 0) | ||
| 323 | #define _MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN IOMUX_PAD(0x3F4, 0xC8, 0, 0x0, 0, 0) | ||
| 324 | #define _MX53_PAD_CSI0_DATA_EN__GPIO5_20 IOMUX_PAD(0x3F4, 0xC8, 1, 0x0, 0, 0) | ||
| 325 | #define _MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 IOMUX_PAD(0x3F4, 0xC8, 5, 0x0, 0, 0) | ||
| 326 | #define _MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 IOMUX_PAD(0x3F4, 0xC8, 6, 0x0, 0, 0) | ||
| 327 | #define _MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK IOMUX_PAD(0x3F4, 0xC8, 7, 0x0, 0, 0) | ||
| 328 | #define _MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC IOMUX_PAD(0x3F8, 0xCC, 0, 0x0, 0, 0) | ||
| 329 | #define _MX53_PAD_CSI0_VSYNC__GPIO5_21 IOMUX_PAD(0x3F8, 0xCC, 1, 0x0, 0, 0) | ||
| 330 | #define _MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 IOMUX_PAD(0x3F8, 0xCC, 5, 0x0, 0, 0) | ||
| 331 | #define _MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 IOMUX_PAD(0x3F8, 0xCC, 6, 0x0, 0, 0) | ||
| 332 | #define _MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 IOMUX_PAD(0x3F8, 0xCC, 7, 0x0, 0, 0) | ||
| 333 | #define _MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 IOMUX_PAD(0x3FC, 0xD0, 0, 0x0, 0, 0) | ||
| 334 | #define _MX53_PAD_CSI0_DAT4__GPIO5_22 IOMUX_PAD(0x3FC, 0xD0, 1, 0x0, 0, 0) | ||
| 335 | #define _MX53_PAD_CSI0_DAT4__KPP_COL_5 IOMUX_PAD(0x3FC, 0xD0, 2, 0x840, 1, 0) | ||
| 336 | #define _MX53_PAD_CSI0_DAT4__ECSPI1_SCLK IOMUX_PAD(0x3FC, 0xD0, 3, 0x79C, 2, 0) | ||
| 337 | #define _MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP IOMUX_PAD(0x3FC, 0xD0, 4, 0x0, 0, 0) | ||
| 338 | #define _MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC IOMUX_PAD(0x3FC, 0xD0, 5, 0x0, 0, 0) | ||
| 339 | #define _MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 IOMUX_PAD(0x3FC, 0xD0, 6, 0x0, 0, 0) | ||
| 340 | #define _MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 IOMUX_PAD(0x3FC, 0xD0, 7, 0x0, 0, 0) | ||
| 341 | #define _MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 IOMUX_PAD(0x400, 0xD4, 0, 0x0, 0, 0) | ||
| 342 | #define _MX53_PAD_CSI0_DAT5__GPIO5_23 IOMUX_PAD(0x400, 0xD4, 1, 0x0, 0, 0) | ||
| 343 | #define _MX53_PAD_CSI0_DAT5__KPP_ROW_5 IOMUX_PAD(0x400, 0xD4, 2, 0x84C, 0, 0) | ||
| 344 | #define _MX53_PAD_CSI0_DAT5__ECSPI1_MOSI IOMUX_PAD(0x400, 0xD4, 3, 0x7A4, 2, 0) | ||
| 345 | #define _MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT IOMUX_PAD(0x400, 0xD4, 4, 0x0, 0, 0) | ||
| 346 | #define _MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD IOMUX_PAD(0x400, 0xD4, 5, 0x0, 0, 0) | ||
| 347 | #define _MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 IOMUX_PAD(0x400, 0xD4, 6, 0x0, 0, 0) | ||
| 348 | #define _MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 IOMUX_PAD(0x400, 0xD4, 7, 0x0, 0, 0) | ||
| 349 | #define _MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 IOMUX_PAD(0x404, 0xD8, 0, 0x0, 0, 0) | ||
| 350 | #define _MX53_PAD_CSI0_DAT6__GPIO5_24 IOMUX_PAD(0x404, 0xD8, 1, 0x0, 0, 0) | ||
| 351 | #define _MX53_PAD_CSI0_DAT6__KPP_COL_6 IOMUX_PAD(0x404, 0xD8, 2, 0x844, 0, 0) | ||
| 352 | #define _MX53_PAD_CSI0_DAT6__ECSPI1_MISO IOMUX_PAD(0x404, 0xD8, 3, 0x7A0, 2, 0) | ||
| 353 | #define _MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK IOMUX_PAD(0x404, 0xD8, 4, 0x0, 0, 0) | ||
| 354 | #define _MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS IOMUX_PAD(0x404, 0xD8, 5, 0x0, 0, 0) | ||
| 355 | #define _MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 IOMUX_PAD(0x404, 0xD8, 6, 0x0, 0, 0) | ||
| 356 | #define _MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 IOMUX_PAD(0x404, 0xD8, 7, 0x0, 0, 0) | ||
| 357 | #define _MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 IOMUX_PAD(0x408, 0xDC, 0, 0x0, 0, 0) | ||
| 358 | #define _MX53_PAD_CSI0_DAT7__GPIO5_25 IOMUX_PAD(0x408, 0xDC, 1, 0x0, 0, 0) | ||
| 359 | #define _MX53_PAD_CSI0_DAT7__KPP_ROW_6 IOMUX_PAD(0x408, 0xDC, 2, 0x850, 0, 0) | ||
| 360 | #define _MX53_PAD_CSI0_DAT7__ECSPI1_SS0 IOMUX_PAD(0x408, 0xDC, 3, 0x7A8, 2, 0) | ||
| 361 | #define _MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR IOMUX_PAD(0x408, 0xDC, 4, 0x0, 0, 0) | ||
| 362 | #define _MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD IOMUX_PAD(0x408, 0xDC, 5, 0x0, 0, 0) | ||
| 363 | #define _MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 IOMUX_PAD(0x408, 0xDC, 6, 0x0, 0, 0) | ||
| 364 | #define _MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 IOMUX_PAD(0x408, 0xDC, 7, 0x0, 0, 0) | ||
| 365 | #define _MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 IOMUX_PAD(0x40C, 0xE0, 0, 0x0, 0, 0) | ||
| 366 | #define _MX53_PAD_CSI0_DAT8__GPIO5_26 IOMUX_PAD(0x40C, 0xE0, 1, 0x0, 0, 0) | ||
| 367 | #define _MX53_PAD_CSI0_DAT8__KPP_COL_7 IOMUX_PAD(0x40C, 0xE0, 2, 0x848, 0, 0) | ||
| 368 | #define _MX53_PAD_CSI0_DAT8__ECSPI2_SCLK IOMUX_PAD(0x40C, 0xE0, 3, 0x7B8, 1, 0) | ||
| 369 | #define _MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC IOMUX_PAD(0x40C, 0xE0, 4, 0x0, 0, 0) | ||
| 370 | #define _MX53_PAD_CSI0_DAT8__I2C1_SDA IOMUX_PAD(0x40C, 0xE0, 5 | IOMUX_CONFIG_SION, 0x818, 0, 0) | ||
| 371 | #define _MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 IOMUX_PAD(0x40C, 0xE0, 6, 0x0, 0, 0) | ||
| 372 | #define _MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 IOMUX_PAD(0x40C, 0xE0, 7, 0x0, 0, 0) | ||
| 373 | #define _MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 IOMUX_PAD(0x410, 0xE4, 0, 0x0, 0, 0) | ||
| 374 | #define _MX53_PAD_CSI0_DAT9__GPIO5_27 IOMUX_PAD(0x410, 0xE4, 1, 0x0, 0, 0) | ||
| 375 | #define _MX53_PAD_CSI0_DAT9__KPP_ROW_7 IOMUX_PAD(0x410, 0xE4, 2, 0x854, 0, 0) | ||
| 376 | #define _MX53_PAD_CSI0_DAT9__ECSPI2_MOSI IOMUX_PAD(0x410, 0xE4, 3, 0x7C0, 1, 0) | ||
| 377 | #define _MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR IOMUX_PAD(0x410, 0xE4, 4, 0x0, 0, 0) | ||
| 378 | #define _MX53_PAD_CSI0_DAT9__I2C1_SCL IOMUX_PAD(0x410, 0xE4, 5 | IOMUX_CONFIG_SION, 0x814, 0, 0) | ||
| 379 | #define _MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 IOMUX_PAD(0x410, 0xE4, 6, 0x0, 0, 0) | ||
| 380 | #define _MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 IOMUX_PAD(0x410, 0xE4, 7, 0x0, 0, 0) | ||
| 381 | #define _MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 IOMUX_PAD(0x414, 0xE8, 0, 0x0, 0, 0) | ||
| 382 | #define _MX53_PAD_CSI0_DAT10__GPIO5_28 IOMUX_PAD(0x414, 0xE8, 1, 0x0, 0, 0) | ||
| 383 | #define _MX53_PAD_CSI0_DAT10__UART1_TXD_MUX IOMUX_PAD(0x414, 0xE8, 2, 0x0, 0, 0) | ||
| 384 | #define _MX53_PAD_CSI0_DAT10__ECSPI2_MISO IOMUX_PAD(0x414, 0xE8, 3, 0x7BC, 1, 0) | ||
| 385 | #define _MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC IOMUX_PAD(0x414, 0xE8, 4, 0x0, 0, 0) | ||
| 386 | #define _MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 IOMUX_PAD(0x414, 0xE8, 5, 0x0, 0, 0) | ||
| 387 | #define _MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 IOMUX_PAD(0x414, 0xE8, 6, 0x0, 0, 0) | ||
| 388 | #define _MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 IOMUX_PAD(0x414, 0xE8, 7, 0x0, 0, 0) | ||
| 389 | #define _MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 IOMUX_PAD(0x418, 0xEC, 0, 0x0, 0, 0) | ||
| 390 | #define _MX53_PAD_CSI0_DAT11__GPIO5_29 IOMUX_PAD(0x418, 0xEC, 1, 0x0, 0, 0) | ||
| 391 | #define _MX53_PAD_CSI0_DAT11__UART1_RXD_MUX IOMUX_PAD(0x418, 0xEC, 2, 0x878, 1, 0) | ||
| 392 | #define _MX53_PAD_CSI0_DAT11__ECSPI2_SS0 IOMUX_PAD(0x418, 0xEC, 3, 0x7C4, 1, 0) | ||
| 393 | #define _MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS IOMUX_PAD(0x418, 0xEC, 4, 0x0, 0, 0) | ||
| 394 | #define _MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 IOMUX_PAD(0x418, 0xEC, 5, 0x0, 0, 0) | ||
| 395 | #define _MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 IOMUX_PAD(0x418, 0xEC, 6, 0x0, 0, 0) | ||
| 396 | #define _MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 IOMUX_PAD(0x418, 0xEC, 7, 0x0, 0, 0) | ||
| 397 | #define _MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 IOMUX_PAD(0x41C, 0xF0, 0, 0x0, 0, 0) | ||
| 398 | #define _MX53_PAD_CSI0_DAT12__GPIO5_30 IOMUX_PAD(0x41C, 0xF0, 1, 0x0, 0, 0) | ||
| 399 | #define _MX53_PAD_CSI0_DAT12__UART4_TXD_MUX IOMUX_PAD(0x41C, 0xF0, 2, 0x0, 0, 0) | ||
| 400 | #define _MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 IOMUX_PAD(0x41C, 0xF0, 4, 0x0, 0, 0) | ||
| 401 | #define _MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 IOMUX_PAD(0x41C, 0xF0, 5, 0x0, 0, 0) | ||
| 402 | #define _MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 IOMUX_PAD(0x41C, 0xF0, 6, 0x0, 0, 0) | ||
| 403 | #define _MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 IOMUX_PAD(0x41C, 0xF0, 7, 0x0, 0, 0) | ||
| 404 | #define _MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 IOMUX_PAD(0x420, 0xF4, 0, 0x0, 0, 0) | ||
| 405 | #define _MX53_PAD_CSI0_DAT13__GPIO5_31 IOMUX_PAD(0x420, 0xF4, 1, 0x0, 0, 0) | ||
| 406 | #define _MX53_PAD_CSI0_DAT13__UART4_RXD_MUX IOMUX_PAD(0x420, 0xF4, 2, 0x890, 3, 0) | ||
| 407 | #define _MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 IOMUX_PAD(0x420, 0xF4, 4, 0x0, 0, 0) | ||
| 408 | #define _MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 IOMUX_PAD(0x420, 0xF4, 5, 0x0, 0, 0) | ||
| 409 | #define _MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 IOMUX_PAD(0x420, 0xF4, 6, 0x0, 0, 0) | ||
| 410 | #define _MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 IOMUX_PAD(0x420, 0xF4, 7, 0x0, 0, 0) | ||
| 411 | #define _MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 IOMUX_PAD(0x424, 0xF8, 0, 0x0, 0, 0) | ||
| 412 | #define _MX53_PAD_CSI0_DAT14__GPIO6_0 IOMUX_PAD(0x424, 0xF8, 1, 0x0, 0, 0) | ||
| 413 | #define _MX53_PAD_CSI0_DAT14__UART5_TXD_MUX IOMUX_PAD(0x424, 0xF8, 2, 0x0, 0, 0) | ||
| 414 | #define _MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 IOMUX_PAD(0x424, 0xF8, 4, 0x0, 0, 0) | ||
| 415 | #define _MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 IOMUX_PAD(0x424, 0xF8, 5, 0x0, 0, 0) | ||
| 416 | #define _MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 IOMUX_PAD(0x424, 0xF8, 6, 0x0, 0, 0) | ||
| 417 | #define _MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 IOMUX_PAD(0x424, 0xF8, 7, 0x0, 0, 0) | ||
| 418 | #define _MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 IOMUX_PAD(0x428, 0xFC, 0, 0x0, 0, 0) | ||
| 419 | #define _MX53_PAD_CSI0_DAT15__GPIO6_1 IOMUX_PAD(0x428, 0xFC, 1, 0x0, 0, 0) | ||
| 420 | #define _MX53_PAD_CSI0_DAT15__UART5_RXD_MUX IOMUX_PAD(0x428, 0xFC, 2, 0x898, 3, 0) | ||
| 421 | #define _MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 IOMUX_PAD(0x428, 0xFC, 4, 0x0, 0, 0) | ||
| 422 | #define _MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 IOMUX_PAD(0x428, 0xFC, 5, 0x0, 0, 0) | ||
| 423 | #define _MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 IOMUX_PAD(0x428, 0xFC, 6, 0x0, 0, 0) | ||
| 424 | #define _MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 IOMUX_PAD(0x428, 0xFC, 7, 0x0, 0, 0) | ||
| 425 | #define _MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 IOMUX_PAD(0x42C, 0x100, 0, 0x0, 0, 0) | ||
| 426 | #define _MX53_PAD_CSI0_DAT16__GPIO6_2 IOMUX_PAD(0x42C, 0x100, 1, 0x0, 0, 0) | ||
| 427 | #define _MX53_PAD_CSI0_DAT16__UART4_RTS IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, 0) | ||
| 428 | #define _MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 IOMUX_PAD(0x42C, 0x100, 4, 0x0, 0, 0) | ||
| 429 | #define _MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 IOMUX_PAD(0x42C, 0x100, 5, 0x0, 0, 0) | ||
| 430 | #define _MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 IOMUX_PAD(0x42C, 0x100, 6, 0x0, 0, 0) | ||
| 431 | #define _MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 IOMUX_PAD(0x42C, 0x100, 7, 0x0, 0, 0) | ||
| 432 | #define _MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 IOMUX_PAD(0x430, 0x104, 0, 0x0, 0, 0) | ||
| 433 | #define _MX53_PAD_CSI0_DAT17__GPIO6_3 IOMUX_PAD(0x430, 0x104, 1, 0x0, 0, 0) | ||
| 434 | #define _MX53_PAD_CSI0_DAT17__UART4_CTS IOMUX_PAD(0x430, 0x104, 2, 0x0, 0, 0) | ||
| 435 | #define _MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 IOMUX_PAD(0x430, 0x104, 4, 0x0, 0, 0) | ||
| 436 | #define _MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 IOMUX_PAD(0x430, 0x104, 5, 0x0, 0, 0) | ||
| 437 | #define _MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 IOMUX_PAD(0x430, 0x104, 6, 0x0, 0, 0) | ||
| 438 | #define _MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 IOMUX_PAD(0x430, 0x104, 7, 0x0, 0, 0) | ||
| 439 | #define _MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 IOMUX_PAD(0x434, 0x108, 0, 0x0, 0, 0) | ||
| 440 | #define _MX53_PAD_CSI0_DAT18__GPIO6_4 IOMUX_PAD(0x434, 0x108, 1, 0x0, 0, 0) | ||
| 441 | #define _MX53_PAD_CSI0_DAT18__UART5_RTS IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, 0) | ||
| 442 | #define _MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 IOMUX_PAD(0x434, 0x108, 4, 0x0, 0, 0) | ||
| 443 | #define _MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 IOMUX_PAD(0x434, 0x108, 5, 0x0, 0, 0) | ||
| 444 | #define _MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 IOMUX_PAD(0x434, 0x108, 6, 0x0, 0, 0) | ||
| 445 | #define _MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 IOMUX_PAD(0x434, 0x108, 7, 0x0, 0, 0) | ||
| 446 | #define _MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 IOMUX_PAD(0x438, 0x10C, 0, 0x0, 0, 0) | ||
| 447 | #define _MX53_PAD_CSI0_DAT19__GPIO6_5 IOMUX_PAD(0x438, 0x10C, 1, 0x0, 0, 0) | ||
| 448 | #define _MX53_PAD_CSI0_DAT19__UART5_CTS IOMUX_PAD(0x438, 0x10C, 2, 0x0, 0, 0) | ||
| 449 | #define _MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 IOMUX_PAD(0x438, 0x10C, 4, 0x0, 0, 0) | ||
| 450 | #define _MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 IOMUX_PAD(0x438, 0x10C, 5, 0x0, 0, 0) | ||
| 451 | #define _MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 IOMUX_PAD(0x438, 0x10C, 6, 0x0, 0, 0) | ||
| 452 | #define _MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK IOMUX_PAD(0x438, 0x10C, 7, 0x0, 0, 0) | ||
| 453 | #define _MX53_PAD_EIM_A25__EMI_WEIM_A_25 IOMUX_PAD(0x458, 0x110, 0, 0x0, 0, 0) | ||
| 454 | #define _MX53_PAD_EIM_A25__GPIO5_2 IOMUX_PAD(0x458, 0x110, 1, 0x0, 0, 0) | ||
| 455 | #define _MX53_PAD_EIM_A25__ECSPI2_RDY IOMUX_PAD(0x458, 0x110, 2, 0x0, 0, 0) | ||
| 456 | #define _MX53_PAD_EIM_A25__IPU_DI1_PIN12 IOMUX_PAD(0x458, 0x110, 3, 0x0, 0, 0) | ||
| 457 | #define _MX53_PAD_EIM_A25__CSPI_SS1 IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, 0) | ||
| 458 | #define _MX53_PAD_EIM_A25__IPU_DI0_D1_CS IOMUX_PAD(0x458, 0x110, 6, 0x0, 0, 0) | ||
| 459 | #define _MX53_PAD_EIM_A25__USBPHY1_BISTOK IOMUX_PAD(0x458, 0x110, 7, 0x0, 0, 0) | ||
| 460 | #define _MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 IOMUX_PAD(0x45C, 0x114, 0, 0x0, 0, 0) | ||
| 461 | #define _MX53_PAD_EIM_EB2__GPIO2_30 IOMUX_PAD(0x45C, 0x114, 1, 0x0, 0, 0) | ||
| 462 | #define _MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, 0) | ||
| 463 | #define _MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS IOMUX_PAD(0x45C, 0x114, 3, 0x0, 0, 0) | ||
| 464 | #define _MX53_PAD_EIM_EB2__ECSPI1_SS0 IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, 0) | ||
| 465 | #define _MX53_PAD_EIM_EB2__I2C2_SCL IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, 0) | ||
| 466 | #define _MX53_PAD_EIM_D16__EMI_WEIM_D_16 IOMUX_PAD(0x460, 0x118, 0, 0x0, 0, 0) | ||
| 467 | #define _MX53_PAD_EIM_D16__GPIO3_16 IOMUX_PAD(0x460, 0x118, 1, 0x0, 0, 0) | ||
| 468 | #define _MX53_PAD_EIM_D16__IPU_DI0_PIN5 IOMUX_PAD(0x460, 0x118, 2, 0x0, 0, 0) | ||
| 469 | #define _MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK IOMUX_PAD(0x460, 0x118, 3, 0x0, 0, 0) | ||
| 470 | #define _MX53_PAD_EIM_D16__ECSPI1_SCLK IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, 0) | ||
| 471 | #define _MX53_PAD_EIM_D16__I2C2_SDA IOMUX_PAD(0x460, 0x118, 5 | IOMUX_CONFIG_SION, 0x820, 1, 0) | ||
| 472 | #define _MX53_PAD_EIM_D17__EMI_WEIM_D_17 IOMUX_PAD(0x464, 0x11C, 0, 0x0, 0, 0) | ||
| 473 | #define _MX53_PAD_EIM_D17__GPIO3_17 IOMUX_PAD(0x464, 0x11C, 1, 0x0, 0, 0) | ||
| 474 | #define _MX53_PAD_EIM_D17__IPU_DI0_PIN6 IOMUX_PAD(0x464, 0x11C, 2, 0x0, 0, 0) | ||
| 475 | #define _MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, 0) | ||
| 476 | #define _MX53_PAD_EIM_D17__ECSPI1_MISO IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, 0) | ||
| 477 | #define _MX53_PAD_EIM_D17__I2C3_SCL IOMUX_PAD(0x464, 0x11C, 5 | IOMUX_CONFIG_SION, 0x824, 0, 0) | ||
| 478 | #define _MX53_PAD_EIM_D18__EMI_WEIM_D_18 IOMUX_PAD(0x468, 0x120, 0, 0x0, 0, 0) | ||
| 479 | #define _MX53_PAD_EIM_D18__GPIO3_18 IOMUX_PAD(0x468, 0x120, 1, 0x0, 0, 0) | ||
| 480 | #define _MX53_PAD_EIM_D18__IPU_DI0_PIN7 IOMUX_PAD(0x468, 0x120, 2, 0x0, 0, 0) | ||
| 481 | #define _MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, 0) | ||
| 482 | #define _MX53_PAD_EIM_D18__ECSPI1_MOSI IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, 0) | ||
| 483 | #define _MX53_PAD_EIM_D18__I2C3_SDA IOMUX_PAD(0x468, 0x120, 5 | IOMUX_CONFIG_SION, 0x828, 0, 0) | ||
| 484 | #define _MX53_PAD_EIM_D18__IPU_DI1_D0_CS IOMUX_PAD(0x468, 0x120, 6, 0x0, 0, 0) | ||
| 485 | #define _MX53_PAD_EIM_D19__EMI_WEIM_D_19 IOMUX_PAD(0x46C, 0x124, 0, 0x0, 0, 0) | ||
| 486 | #define _MX53_PAD_EIM_D19__GPIO3_19 IOMUX_PAD(0x46C, 0x124, 1, 0x0, 0, 0) | ||
| 487 | #define _MX53_PAD_EIM_D19__IPU_DI0_PIN8 IOMUX_PAD(0x46C, 0x124, 2, 0x0, 0, 0) | ||
| 488 | #define _MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS IOMUX_PAD(0x46C, 0x124, 3, 0x0, 0, 0) | ||
| 489 | #define _MX53_PAD_EIM_D19__ECSPI1_SS1 IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, 0) | ||
| 490 | #define _MX53_PAD_EIM_D19__EPIT1_EPITO IOMUX_PAD(0x46C, 0x124, 5, 0x0, 0, 0) | ||
| 491 | #define _MX53_PAD_EIM_D19__UART1_CTS IOMUX_PAD(0x46C, 0x124, 6, 0x0, 0, 0) | ||
| 492 | #define _MX53_PAD_EIM_D19__USBOH3_USBH2_OC IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, 0) | ||
| 493 | #define _MX53_PAD_EIM_D20__EMI_WEIM_D_20 IOMUX_PAD(0x470, 0x128, 0, 0x0, 0, 0) | ||
| 494 | #define _MX53_PAD_EIM_D20__GPIO3_20 IOMUX_PAD(0x470, 0x128, 1, 0x0, 0, 0) | ||
| 495 | #define _MX53_PAD_EIM_D20__IPU_DI0_PIN16 IOMUX_PAD(0x470, 0x128, 2, 0x0, 0, 0) | ||
| 496 | #define _MX53_PAD_EIM_D20__IPU_SER_DISP0_CS IOMUX_PAD(0x470, 0x128, 3, 0x0, 0, 0) | ||
| 497 | #define _MX53_PAD_EIM_D20__CSPI_SS0 IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, 0) | ||
| 498 | #define _MX53_PAD_EIM_D20__EPIT2_EPITO IOMUX_PAD(0x470, 0x128, 5, 0x0, 0, 0) | ||
| 499 | #define _MX53_PAD_EIM_D20__UART1_RTS IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, 0) | ||
| 500 | #define _MX53_PAD_EIM_D20__USBOH3_USBH2_PWR IOMUX_PAD(0x470, 0x128, 7, 0x0, 0, 0) | ||
| 501 | #define _MX53_PAD_EIM_D21__EMI_WEIM_D_21 IOMUX_PAD(0x474, 0x12C, 0, 0x0, 0, 0) | ||
| 502 | #define _MX53_PAD_EIM_D21__GPIO3_21 IOMUX_PAD(0x474, 0x12C, 1, 0x0, 0, 0) | ||
| 503 | #define _MX53_PAD_EIM_D21__IPU_DI0_PIN17 IOMUX_PAD(0x474, 0x12C, 2, 0x0, 0, 0) | ||
| 504 | #define _MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK IOMUX_PAD(0x474, 0x12C, 3, 0x0, 0, 0) | ||
| 505 | #define _MX53_PAD_EIM_D21__CSPI_SCLK IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, 0) | ||
| 506 | #define _MX53_PAD_EIM_D21__I2C1_SCL IOMUX_PAD(0x474, 0x12C, 5 | IOMUX_CONFIG_SION, 0x814, 1, 0) | ||
| 507 | #define _MX53_PAD_EIM_D21__USBOH3_USBOTG_OC IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, 0) | ||
| 508 | #define _MX53_PAD_EIM_D22__EMI_WEIM_D_22 IOMUX_PAD(0x478, 0x130, 0, 0x0, 0, 0) | ||
| 509 | #define _MX53_PAD_EIM_D22__GPIO3_22 IOMUX_PAD(0x478, 0x130, 1, 0x0, 0, 0) | ||
| 510 | #define _MX53_PAD_EIM_D22__IPU_DI0_PIN1 IOMUX_PAD(0x478, 0x130, 2, 0x0, 0, 0) | ||
| 511 | #define _MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, 0) | ||
| 512 | #define _MX53_PAD_EIM_D22__CSPI_MISO IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, 0) | ||
| 513 | #define _MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR IOMUX_PAD(0x478, 0x130, 6, 0x0, 0, 0) | ||
| 514 | #define _MX53_PAD_EIM_D23__EMI_WEIM_D_23 IOMUX_PAD(0x47C, 0x134, 0, 0x0, 0, 0) | ||
| 515 | #define _MX53_PAD_EIM_D23__GPIO3_23 IOMUX_PAD(0x47C, 0x134, 1, 0x0, 0, 0) | ||
| 516 | #define _MX53_PAD_EIM_D23__UART3_CTS IOMUX_PAD(0x47C, 0x134, 2, 0x0, 0, 0) | ||
| 517 | #define _MX53_PAD_EIM_D23__UART1_DCD IOMUX_PAD(0x47C, 0x134, 3, 0x0, 0, 0) | ||
| 518 | #define _MX53_PAD_EIM_D23__IPU_DI0_D0_CS IOMUX_PAD(0x47C, 0x134, 4, 0x0, 0, 0) | ||
| 519 | #define _MX53_PAD_EIM_D23__IPU_DI1_PIN2 IOMUX_PAD(0x47C, 0x134, 5, 0x0, 0, 0) | ||
| 520 | #define _MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, 0) | ||
| 521 | #define _MX53_PAD_EIM_D23__IPU_DI1_PIN14 IOMUX_PAD(0x47C, 0x134, 7, 0x0, 0, 0) | ||
| 522 | #define _MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 IOMUX_PAD(0x480, 0x138, 0, 0x0, 0, 0) | ||
| 523 | #define _MX53_PAD_EIM_EB3__GPIO2_31 IOMUX_PAD(0x480, 0x138, 1, 0x0, 0, 0) | ||
| 524 | #define _MX53_PAD_EIM_EB3__UART3_RTS IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, 0) | ||
| 525 | #define _MX53_PAD_EIM_EB3__UART1_RI IOMUX_PAD(0x480, 0x138, 3, 0x0, 0, 0) | ||
| 526 | #define _MX53_PAD_EIM_EB3__IPU_DI1_PIN3 IOMUX_PAD(0x480, 0x138, 5, 0x0, 0, 0) | ||
| 527 | #define _MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, 0) | ||
| 528 | #define _MX53_PAD_EIM_EB3__IPU_DI1_PIN16 IOMUX_PAD(0x480, 0x138, 7, 0x0, 0, 0) | ||
| 529 | #define _MX53_PAD_EIM_D24__EMI_WEIM_D_24 IOMUX_PAD(0x484, 0x13C, 0, 0x0, 0, 0) | ||
| 530 | #define _MX53_PAD_EIM_D24__GPIO3_24 IOMUX_PAD(0x484, 0x13C, 1, 0x0, 0, 0) | ||
| 531 | #define _MX53_PAD_EIM_D24__UART3_TXD_MUX IOMUX_PAD(0x484, 0x13C, 2, 0x0, 0, 0) | ||
| 532 | #define _MX53_PAD_EIM_D24__ECSPI1_SS2 IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, 0) | ||
| 533 | #define _MX53_PAD_EIM_D24__CSPI_SS2 IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, 0) | ||
| 534 | #define _MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, 0) | ||
| 535 | #define _MX53_PAD_EIM_D24__ECSPI2_SS2 IOMUX_PAD(0x484, 0x13C, 6, 0x0, 0, 0) | ||
| 536 | #define _MX53_PAD_EIM_D24__UART1_DTR IOMUX_PAD(0x484, 0x13C, 7, 0x0, 0, 0) | ||
| 537 | #define _MX53_PAD_EIM_D25__EMI_WEIM_D_25 IOMUX_PAD(0x488, 0x140, 0, 0x0, 0, 0) | ||
| 538 | #define _MX53_PAD_EIM_D25__GPIO3_25 IOMUX_PAD(0x488, 0x140, 1, 0x0, 0, 0) | ||
| 539 | #define _MX53_PAD_EIM_D25__UART3_RXD_MUX IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, 0) | ||
| 540 | #define _MX53_PAD_EIM_D25__ECSPI1_SS3 IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, 0) | ||
| 541 | #define _MX53_PAD_EIM_D25__CSPI_SS3 IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, 0) | ||
| 542 | #define _MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, 0) | ||
| 543 | #define _MX53_PAD_EIM_D25__ECSPI2_SS3 IOMUX_PAD(0x488, 0x140, 6, 0x0, 0, 0) | ||
| 544 | #define _MX53_PAD_EIM_D25__UART1_DSR IOMUX_PAD(0x488, 0x140, 7, 0x0, 0, 0) | ||
| 545 | #define _MX53_PAD_EIM_D26__EMI_WEIM_D_26 IOMUX_PAD(0x48C, 0x144, 0, 0x0, 0, 0) | ||
| 546 | #define _MX53_PAD_EIM_D26__GPIO3_26 IOMUX_PAD(0x48C, 0x144, 1, 0x0, 0, 0) | ||
| 547 | #define _MX53_PAD_EIM_D26__UART2_TXD_MUX IOMUX_PAD(0x48C, 0x144, 2, 0x0, 0, 0) | ||
| 548 | #define _MX53_PAD_EIM_D26__FIRI_RXD IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, 0) | ||
| 549 | #define _MX53_PAD_EIM_D26__IPU_CSI0_D_1 IOMUX_PAD(0x48C, 0x144, 4, 0x0, 0, 0) | ||
| 550 | #define _MX53_PAD_EIM_D26__IPU_DI1_PIN11 IOMUX_PAD(0x48C, 0x144, 5, 0x0, 0, 0) | ||
| 551 | #define _MX53_PAD_EIM_D26__IPU_SISG_2 IOMUX_PAD(0x48C, 0x144, 6, 0x0, 0, 0) | ||
| 552 | #define _MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 IOMUX_PAD(0x48C, 0x144, 7, 0x0, 0, 0) | ||
| 553 | #define _MX53_PAD_EIM_D27__EMI_WEIM_D_27 IOMUX_PAD(0x490, 0x148, 0, 0x0, 0, 0) | ||
| 554 | #define _MX53_PAD_EIM_D27__GPIO3_27 IOMUX_PAD(0x490, 0x148, 1, 0x0, 0, 0) | ||
| 555 | #define _MX53_PAD_EIM_D27__UART2_RXD_MUX IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, 0) | ||
| 556 | #define _MX53_PAD_EIM_D27__FIRI_TXD IOMUX_PAD(0x490, 0x148, 3, 0x0, 0, 0) | ||
| 557 | #define _MX53_PAD_EIM_D27__IPU_CSI0_D_0 IOMUX_PAD(0x490, 0x148, 4, 0x0, 0, 0) | ||
| 558 | #define _MX53_PAD_EIM_D27__IPU_DI1_PIN13 IOMUX_PAD(0x490, 0x148, 5, 0x0, 0, 0) | ||
| 559 | #define _MX53_PAD_EIM_D27__IPU_SISG_3 IOMUX_PAD(0x490, 0x148, 6, 0x0, 0, 0) | ||
| 560 | #define _MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 IOMUX_PAD(0x490, 0x148, 7, 0x0, 0, 0) | ||
| 561 | #define _MX53_PAD_EIM_D28__EMI_WEIM_D_28 IOMUX_PAD(0x494, 0x14C, 0, 0x0, 0, 0) | ||
| 562 | #define _MX53_PAD_EIM_D28__GPIO3_28 IOMUX_PAD(0x494, 0x14C, 1, 0x0, 0, 0) | ||
| 563 | #define _MX53_PAD_EIM_D28__UART2_CTS IOMUX_PAD(0x494, 0x14C, 2, 0x0, 0, 0) | ||
| 564 | #define _MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, 0) | ||
| 565 | #define _MX53_PAD_EIM_D28__CSPI_MOSI IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, 0) | ||
| 566 | #define _MX53_PAD_EIM_D28__I2C1_SDA IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, 0) | ||
| 567 | #define _MX53_PAD_EIM_D28__IPU_EXT_TRIG IOMUX_PAD(0x494, 0x14C, 6, 0x0, 0, 0) | ||
| 568 | #define _MX53_PAD_EIM_D28__IPU_DI0_PIN13 IOMUX_PAD(0x494, 0x14C, 7, 0x0, 0, 0) | ||
| 569 | #define _MX53_PAD_EIM_D29__EMI_WEIM_D_29 IOMUX_PAD(0x498, 0x150, 0, 0x0, 0, 0) | ||
| 570 | #define _MX53_PAD_EIM_D29__GPIO3_29 IOMUX_PAD(0x498, 0x150, 1, 0x0, 0, 0) | ||
| 571 | #define _MX53_PAD_EIM_D29__UART2_RTS IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, 0) | ||
| 572 | #define _MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS IOMUX_PAD(0x498, 0x150, 3, 0x0, 0, 0) | ||
| 573 | #define _MX53_PAD_EIM_D29__CSPI_SS0 IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, 0) | ||
| 574 | #define _MX53_PAD_EIM_D29__IPU_DI1_PIN15 IOMUX_PAD(0x498, 0x150, 5, 0x0, 0, 0) | ||
| 575 | #define _MX53_PAD_EIM_D29__IPU_CSI1_VSYNC IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, 0) | ||
| 576 | #define _MX53_PAD_EIM_D29__IPU_DI0_PIN14 IOMUX_PAD(0x498, 0x150, 7, 0x0, 0, 0) | ||
| 577 | #define _MX53_PAD_EIM_D30__EMI_WEIM_D_30 IOMUX_PAD(0x49C, 0x154, 0, 0x0, 0, 0) | ||
| 578 | #define _MX53_PAD_EIM_D30__GPIO3_30 IOMUX_PAD(0x49C, 0x154, 1, 0x0, 0, 0) | ||
| 579 | #define _MX53_PAD_EIM_D30__UART3_CTS IOMUX_PAD(0x49C, 0x154, 2, 0x0, 0, 0) | ||
| 580 | #define _MX53_PAD_EIM_D30__IPU_CSI0_D_3 IOMUX_PAD(0x49C, 0x154, 3, 0x0, 0, 0) | ||
| 581 | #define _MX53_PAD_EIM_D30__IPU_DI0_PIN11 IOMUX_PAD(0x49C, 0x154, 4, 0x0, 0, 0) | ||
| 582 | #define _MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 IOMUX_PAD(0x49C, 0x154, 5, 0x0, 0, 0) | ||
| 583 | #define _MX53_PAD_EIM_D30__USBOH3_USBH1_OC IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, 0) | ||
| 584 | #define _MX53_PAD_EIM_D30__USBOH3_USBH2_OC IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, 0) | ||
| 585 | #define _MX53_PAD_EIM_D31__EMI_WEIM_D_31 IOMUX_PAD(0x4A0, 0x158, 0, 0x0, 0, 0) | ||
| 586 | #define _MX53_PAD_EIM_D31__GPIO3_31 IOMUX_PAD(0x4A0, 0x158, 1, 0x0, 0, 0) | ||
| 587 | #define _MX53_PAD_EIM_D31__UART3_RTS IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, 0) | ||
| 588 | #define _MX53_PAD_EIM_D31__IPU_CSI0_D_2 IOMUX_PAD(0x4A0, 0x158, 3, 0x0, 0, 0) | ||
| 589 | #define _MX53_PAD_EIM_D31__IPU_DI0_PIN12 IOMUX_PAD(0x4A0, 0x158, 4, 0x0, 0, 0) | ||
| 590 | #define _MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 IOMUX_PAD(0x4A0, 0x158, 5, 0x0, 0, 0) | ||
| 591 | #define _MX53_PAD_EIM_D31__USBOH3_USBH1_PWR IOMUX_PAD(0x4A0, 0x158, 6, 0x0, 0, 0) | ||
| 592 | #define _MX53_PAD_EIM_D31__USBOH3_USBH2_PWR IOMUX_PAD(0x4A0, 0x158, 7, 0x0, 0, 0) | ||
| 593 | #define _MX53_PAD_EIM_A24__EMI_WEIM_A_24 IOMUX_PAD(0x4A8, 0x15C, 0, 0x0, 0, 0) | ||
| 594 | #define _MX53_PAD_EIM_A24__GPIO5_4 IOMUX_PAD(0x4A8, 0x15C, 1, 0x0, 0, 0) | ||
| 595 | #define _MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 IOMUX_PAD(0x4A8, 0x15C, 2, 0x0, 0, 0) | ||
| 596 | #define _MX53_PAD_EIM_A24__IPU_CSI1_D_19 IOMUX_PAD(0x4A8, 0x15C, 3, 0x0, 0, 0) | ||
| 597 | #define _MX53_PAD_EIM_A24__IPU_SISG_2 IOMUX_PAD(0x4A8, 0x15C, 6, 0x0, 0, 0) | ||
| 598 | #define _MX53_PAD_EIM_A24__USBPHY2_BVALID IOMUX_PAD(0x4A8, 0x15C, 7, 0x0, 0, 0) | ||
| 599 | #define _MX53_PAD_EIM_A23__EMI_WEIM_A_23 IOMUX_PAD(0x4AC, 0x160, 0, 0x0, 0, 0) | ||
| 600 | #define _MX53_PAD_EIM_A23__GPIO6_6 IOMUX_PAD(0x4AC, 0x160, 1, 0x0, 0, 0) | ||
| 601 | #define _MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 IOMUX_PAD(0x4AC, 0x160, 2, 0x0, 0, 0) | ||
| 602 | #define _MX53_PAD_EIM_A23__IPU_CSI1_D_18 IOMUX_PAD(0x4AC, 0x160, 3, 0x0, 0, 0) | ||
| 603 | #define _MX53_PAD_EIM_A23__IPU_SISG_3 IOMUX_PAD(0x4AC, 0x160, 6, 0x0, 0, 0) | ||
| 604 | #define _MX53_PAD_EIM_A23__USBPHY2_ENDSESSION IOMUX_PAD(0x4AC, 0x160, 7, 0x0, 0, 0) | ||
| 605 | #define _MX53_PAD_EIM_A22__EMI_WEIM_A_22 IOMUX_PAD(0x4B0, 0x164, 0, 0x0, 0, 0) | ||
| 606 | #define _MX53_PAD_EIM_A22__GPIO2_16 IOMUX_PAD(0x4B0, 0x164, 1, 0x0, 0, 0) | ||
| 607 | #define _MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 IOMUX_PAD(0x4B0, 0x164, 2, 0x0, 0, 0) | ||
| 608 | #define _MX53_PAD_EIM_A22__IPU_CSI1_D_17 IOMUX_PAD(0x4B0, 0x164, 3, 0x0, 0, 0) | ||
| 609 | #define _MX53_PAD_EIM_A22__SRC_BT_CFG1_7 IOMUX_PAD(0x4B0, 0x164, 7, 0x0, 0, 0) | ||
| 610 | #define _MX53_PAD_EIM_A21__EMI_WEIM_A_21 IOMUX_PAD(0x4B4, 0x168, 0, 0x0, 0, 0) | ||
| 611 | #define _MX53_PAD_EIM_A21__GPIO2_17 IOMUX_PAD(0x4B4, 0x168, 1, 0x0, 0, 0) | ||
| 612 | #define _MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 IOMUX_PAD(0x4B4, 0x168, 2, 0x0, 0, 0) | ||
| 613 | #define _MX53_PAD_EIM_A21__IPU_CSI1_D_16 IOMUX_PAD(0x4B4, 0x168, 3, 0x0, 0, 0) | ||
| 614 | #define _MX53_PAD_EIM_A21__SRC_BT_CFG1_6 IOMUX_PAD(0x4B4, 0x168, 7, 0x0, 0, 0) | ||
| 615 | #define _MX53_PAD_EIM_A20__EMI_WEIM_A_20 IOMUX_PAD(0x4B8, 0x16C, 0, 0x0, 0, 0) | ||
| 616 | #define _MX53_PAD_EIM_A20__GPIO2_18 IOMUX_PAD(0x4B8, 0x16C, 1, 0x0, 0, 0) | ||
| 617 | #define _MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 IOMUX_PAD(0x4B8, 0x16C, 2, 0x0, 0, 0) | ||
| 618 | #define _MX53_PAD_EIM_A20__IPU_CSI1_D_15 IOMUX_PAD(0x4B8, 0x16C, 3, 0x0, 0, 0) | ||
| 619 | #define _MX53_PAD_EIM_A20__SRC_BT_CFG1_5 IOMUX_PAD(0x4B8, 0x16C, 7, 0x0, 0, 0) | ||
| 620 | #define _MX53_PAD_EIM_A19__EMI_WEIM_A_19 IOMUX_PAD(0x4BC, 0x170, 0, 0x0, 0, 0) | ||
| 621 | #define _MX53_PAD_EIM_A19__GPIO2_19 IOMUX_PAD(0x4BC, 0x170, 1, 0x0, 0, 0) | ||
| 622 | #define _MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 IOMUX_PAD(0x4BC, 0x170, 2, 0x0, 0, 0) | ||
| 623 | #define _MX53_PAD_EIM_A19__IPU_CSI1_D_14 IOMUX_PAD(0x4BC, 0x170, 3, 0x0, 0, 0) | ||
| 624 | #define _MX53_PAD_EIM_A19__SRC_BT_CFG1_4 IOMUX_PAD(0x4BC, 0x170, 7, 0x0, 0, 0) | ||
| 625 | #define _MX53_PAD_EIM_A18__EMI_WEIM_A_18 IOMUX_PAD(0x4C0, 0x174, 0, 0x0, 0, 0) | ||
| 626 | #define _MX53_PAD_EIM_A18__GPIO2_20 IOMUX_PAD(0x4C0, 0x174, 1, 0x0, 0, 0) | ||
| 627 | #define _MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 IOMUX_PAD(0x4C0, 0x174, 2, 0x0, 0, 0) | ||
| 628 | #define _MX53_PAD_EIM_A18__IPU_CSI1_D_13 IOMUX_PAD(0x4C0, 0x174, 3, 0x0, 0, 0) | ||
| 629 | #define _MX53_PAD_EIM_A18__SRC_BT_CFG1_3 IOMUX_PAD(0x4C0, 0x174, 7, 0x0, 0, 0) | ||
| 630 | #define _MX53_PAD_EIM_A17__EMI_WEIM_A_17 IOMUX_PAD(0x4C4, 0x178, 0, 0x0, 0, 0) | ||
| 631 | #define _MX53_PAD_EIM_A17__GPIO2_21 IOMUX_PAD(0x4C4, 0x178, 1, 0x0, 0, 0) | ||
| 632 | #define _MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 IOMUX_PAD(0x4C4, 0x178, 2, 0x0, 0, 0) | ||
| 633 | #define _MX53_PAD_EIM_A17__IPU_CSI1_D_12 IOMUX_PAD(0x4C4, 0x178, 3, 0x0, 0, 0) | ||
| 634 | #define _MX53_PAD_EIM_A17__SRC_BT_CFG1_2 IOMUX_PAD(0x4C4, 0x178, 7, 0x0, 0, 0) | ||
| 635 | #define _MX53_PAD_EIM_A16__EMI_WEIM_A_16 IOMUX_PAD(0x4C8, 0x17C, 0, 0x0, 0, 0) | ||
| 636 | #define _MX53_PAD_EIM_A16__GPIO2_22 IOMUX_PAD(0x4C8, 0x17C, 1, 0x0, 0, 0) | ||
| 637 | #define _MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK IOMUX_PAD(0x4C8, 0x17C, 2, 0x0, 0, 0) | ||
| 638 | #define _MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK IOMUX_PAD(0x4C8, 0x17C, 3, 0x0, 0, 0) | ||
| 639 | #define _MX53_PAD_EIM_A16__SRC_BT_CFG1_1 IOMUX_PAD(0x4C8, 0x17C, 7, 0x0, 0, 0) | ||
| 640 | #define _MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 IOMUX_PAD(0x4CC, 0x180, 0, 0x0, 0, 0) | ||
| 641 | #define _MX53_PAD_EIM_CS0__GPIO2_23 IOMUX_PAD(0x4CC, 0x180, 1, 0x0, 0, 0) | ||
| 642 | #define _MX53_PAD_EIM_CS0__ECSPI2_SCLK IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, 0) | ||
| 643 | #define _MX53_PAD_EIM_CS0__IPU_DI1_PIN5 IOMUX_PAD(0x4CC, 0x180, 3, 0x0, 0, 0) | ||
| 644 | #define _MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 IOMUX_PAD(0x4D0, 0x184, 0, 0x0, 0, 0) | ||
| 645 | #define _MX53_PAD_EIM_CS1__GPIO2_24 IOMUX_PAD(0x4D0, 0x184, 1, 0x0, 0, 0) | ||
| 646 | #define _MX53_PAD_EIM_CS1__ECSPI2_MOSI IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, 0) | ||
| 647 | #define _MX53_PAD_EIM_CS1__IPU_DI1_PIN6 IOMUX_PAD(0x4D0, 0x184, 3, 0x0, 0, 0) | ||
| 648 | #define _MX53_PAD_EIM_OE__EMI_WEIM_OE IOMUX_PAD(0x4D4, 0x188, 0, 0x0, 0, 0) | ||
| 649 | #define _MX53_PAD_EIM_OE__GPIO2_25 IOMUX_PAD(0x4D4, 0x188, 1, 0x0, 0, 0) | ||
| 650 | #define _MX53_PAD_EIM_OE__ECSPI2_MISO IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, 0) | ||
| 651 | #define _MX53_PAD_EIM_OE__IPU_DI1_PIN7 IOMUX_PAD(0x4D4, 0x188, 3, 0x0, 0, 0) | ||
| 652 | #define _MX53_PAD_EIM_OE__USBPHY2_IDDIG IOMUX_PAD(0x4D4, 0x188, 7, 0x0, 0, 0) | ||
| 653 | #define _MX53_PAD_EIM_RW__EMI_WEIM_RW IOMUX_PAD(0x4D8, 0x18C, 0, 0x0, 0, 0) | ||
| 654 | #define _MX53_PAD_EIM_RW__GPIO2_26 IOMUX_PAD(0x4D8, 0x18C, 1, 0x0, 0, 0) | ||
| 655 | #define _MX53_PAD_EIM_RW__ECSPI2_SS0 IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, 0) | ||
| 656 | #define _MX53_PAD_EIM_RW__IPU_DI1_PIN8 IOMUX_PAD(0x4D8, 0x18C, 3, 0x0, 0, 0) | ||
| 657 | #define _MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT IOMUX_PAD(0x4D8, 0x18C, 7, 0x0, 0, 0) | ||
| 658 | #define _MX53_PAD_EIM_LBA__EMI_WEIM_LBA IOMUX_PAD(0x4DC, 0x190, 0, 0x0, 0, 0) | ||
| 659 | #define _MX53_PAD_EIM_LBA__GPIO2_27 IOMUX_PAD(0x4DC, 0x190, 1, 0x0, 0, 0) | ||
| 660 | #define _MX53_PAD_EIM_LBA__ECSPI2_SS1 IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, 0) | ||
| 661 | #define _MX53_PAD_EIM_LBA__IPU_DI1_PIN17 IOMUX_PAD(0x4DC, 0x190, 3, 0x0, 0, 0) | ||
| 662 | #define _MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 IOMUX_PAD(0x4DC, 0x190, 7, 0x0, 0, 0) | ||
| 663 | #define _MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 IOMUX_PAD(0x4E4, 0x194, 0, 0x0, 0, 0) | ||
| 664 | #define _MX53_PAD_EIM_EB0__GPIO2_28 IOMUX_PAD(0x4E4, 0x194, 1, 0x0, 0, 0) | ||
| 665 | #define _MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 IOMUX_PAD(0x4E4, 0x194, 3, 0x0, 0, 0) | ||
| 666 | #define _MX53_PAD_EIM_EB0__IPU_CSI1_D_11 IOMUX_PAD(0x4E4, 0x194, 4, 0x0, 0, 0) | ||
| 667 | #define _MX53_PAD_EIM_EB0__GPC_PMIC_RDY IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, 0) | ||
| 668 | #define _MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 IOMUX_PAD(0x4E4, 0x194, 7, 0x0, 0, 0) | ||
| 669 | #define _MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 IOMUX_PAD(0x4E8, 0x198, 0, 0x0, 0, 0) | ||
| 670 | #define _MX53_PAD_EIM_EB1__GPIO2_29 IOMUX_PAD(0x4E8, 0x198, 1, 0x0, 0, 0) | ||
| 671 | #define _MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 IOMUX_PAD(0x4E8, 0x198, 3, 0x0, 0, 0) | ||
| 672 | #define _MX53_PAD_EIM_EB1__IPU_CSI1_D_10 IOMUX_PAD(0x4E8, 0x198, 4, 0x0, 0, 0) | ||
| 673 | #define _MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 IOMUX_PAD(0x4E8, 0x198, 7, 0x0, 0, 0) | ||
| 674 | #define _MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 IOMUX_PAD(0x4EC, 0x19C, 0, 0x0, 0, 0) | ||
| 675 | #define _MX53_PAD_EIM_DA0__GPIO3_0 IOMUX_PAD(0x4EC, 0x19C, 1, 0x0, 0, 0) | ||
| 676 | #define _MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 IOMUX_PAD(0x4EC, 0x19C, 3, 0x0, 0, 0) | ||
| 677 | #define _MX53_PAD_EIM_DA0__IPU_CSI1_D_9 IOMUX_PAD(0x4EC, 0x19C, 4, 0x0, 0, 0) | ||
| 678 | #define _MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 IOMUX_PAD(0x4EC, 0x19C, 7, 0x0, 0, 0) | ||
| 679 | #define _MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 IOMUX_PAD(0x4F0, 0x1A0, 0, 0x0, 0, 0) | ||
| 680 | #define _MX53_PAD_EIM_DA1__GPIO3_1 IOMUX_PAD(0x4F0, 0x1A0, 1, 0x0, 0, 0) | ||
| 681 | #define _MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 IOMUX_PAD(0x4F0, 0x1A0, 3, 0x0, 0, 0) | ||
| 682 | #define _MX53_PAD_EIM_DA1__IPU_CSI1_D_8 IOMUX_PAD(0x4F0, 0x1A0, 4, 0x0, 0, 0) | ||
| 683 | #define _MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 IOMUX_PAD(0x4F0, 0x1A0, 7, 0x0, 0, 0) | ||
| 684 | #define _MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 IOMUX_PAD(0x4F4, 0x1A4, 0, 0x0, 0, 0) | ||
| 685 | #define _MX53_PAD_EIM_DA2__GPIO3_2 IOMUX_PAD(0x4F4, 0x1A4, 1, 0x0, 0, 0) | ||
| 686 | #define _MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 IOMUX_PAD(0x4F4, 0x1A4, 3, 0x0, 0, 0) | ||
| 687 | #define _MX53_PAD_EIM_DA2__IPU_CSI1_D_7 IOMUX_PAD(0x4F4, 0x1A4, 4, 0x0, 0, 0) | ||
| 688 | #define _MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 IOMUX_PAD(0x4F4, 0x1A4, 7, 0x0, 0, 0) | ||
| 689 | #define _MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 IOMUX_PAD(0x4F8, 0x1A8, 0, 0x0, 0, 0) | ||
| 690 | #define _MX53_PAD_EIM_DA3__GPIO3_3 IOMUX_PAD(0x4F8, 0x1A8, 1, 0x0, 0, 0) | ||
| 691 | #define _MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 IOMUX_PAD(0x4F8, 0x1A8, 3, 0x0, 0, 0) | ||
| 692 | #define _MX53_PAD_EIM_DA3__IPU_CSI1_D_6 IOMUX_PAD(0x4F8, 0x1A8, 4, 0x0, 0, 0) | ||
| 693 | #define _MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 IOMUX_PAD(0x4F8, 0x1A8, 7, 0x0, 0, 0) | ||
| 694 | #define _MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 IOMUX_PAD(0x4FC, 0x1AC, 0, 0x0, 0, 0) | ||
| 695 | #define _MX53_PAD_EIM_DA4__GPIO3_4 IOMUX_PAD(0x4FC, 0x1AC, 1, 0x0, 0, 0) | ||
| 696 | #define _MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 IOMUX_PAD(0x4FC, 0x1AC, 3, 0x0, 0, 0) | ||
| 697 | #define _MX53_PAD_EIM_DA4__IPU_CSI1_D_5 IOMUX_PAD(0x4FC, 0x1AC, 4, 0x0, 0, 0) | ||
| 698 | #define _MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 IOMUX_PAD(0x4FC, 0x1AC, 7, 0x0, 0, 0) | ||
| 699 | #define _MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 IOMUX_PAD(0x500, 0x1B0, 0, 0x0, 0, 0) | ||
| 700 | #define _MX53_PAD_EIM_DA5__GPIO3_5 IOMUX_PAD(0x500, 0x1B0, 1, 0x0, 0, 0) | ||
| 701 | #define _MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 IOMUX_PAD(0x500, 0x1B0, 3, 0x0, 0, 0) | ||
| 702 | #define _MX53_PAD_EIM_DA5__IPU_CSI1_D_4 IOMUX_PAD(0x500, 0x1B0, 4, 0x0, 0, 0) | ||
| 703 | #define _MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 IOMUX_PAD(0x500, 0x1B0, 7 | IOMUX_CONFIG_SION, 0x0, 0, 0) | ||
| 704 | #define _MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 IOMUX_PAD(0x504, 0x1B4, 0, 0x0, 0, 0) | ||
| 705 | #define _MX53_PAD_EIM_DA6__GPIO3_6 IOMUX_PAD(0x504, 0x1B4, 1, 0x0, 0, 0) | ||
| 706 | #define _MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 IOMUX_PAD(0x504, 0x1B4, 3, 0x0, 0, 0) | ||
| 707 | #define _MX53_PAD_EIM_DA6__IPU_CSI1_D_3 IOMUX_PAD(0x504, 0x1B4, 4, 0x0, 0, 0) | ||
| 708 | #define _MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 IOMUX_PAD(0x504, 0x1B4, 7, 0x0, 0, 0) | ||
| 709 | #define _MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 IOMUX_PAD(0x508, 0x1B8, 0, 0x0, 0, 0) | ||
| 710 | #define _MX53_PAD_EIM_DA7__GPIO3_7 IOMUX_PAD(0x508, 0x1B8, 1, 0x0, 0, 0) | ||
| 711 | #define _MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 IOMUX_PAD(0x508, 0x1B8, 3, 0x0, 0, 0) | ||
| 712 | #define _MX53_PAD_EIM_DA7__IPU_CSI1_D_2 IOMUX_PAD(0x508, 0x1B8, 4, 0x0, 0, 0) | ||
| 713 | #define _MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 IOMUX_PAD(0x508, 0x1B8, 7, 0x0, 0, 0) | ||
| 714 | #define _MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 IOMUX_PAD(0x50C, 0x1BC, 0, 0x0, 0, 0) | ||
| 715 | #define _MX53_PAD_EIM_DA8__GPIO3_8 IOMUX_PAD(0x50C, 0x1BC, 1, 0x0, 0, 0) | ||
| 716 | #define _MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 IOMUX_PAD(0x50C, 0x1BC, 3, 0x0, 0, 0) | ||
| 717 | #define _MX53_PAD_EIM_DA8__IPU_CSI1_D_1 IOMUX_PAD(0x50C, 0x1BC, 4, 0x0, 0, 0) | ||
| 718 | #define _MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 IOMUX_PAD(0x50C, 0x1BC, 7, 0x0, 0, 0) | ||
| 719 | #define _MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 IOMUX_PAD(0x510, 0x1C0, 0, 0x0, 0, 0) | ||
| 720 | #define _MX53_PAD_EIM_DA9__GPIO3_9 IOMUX_PAD(0x510, 0x1C0, 1, 0x0, 0, 0) | ||
| 721 | #define _MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 IOMUX_PAD(0x510, 0x1C0, 3, 0x0, 0, 0) | ||
| 722 | #define _MX53_PAD_EIM_DA9__IPU_CSI1_D_0 IOMUX_PAD(0x510, 0x1C0, 4, 0x0, 0, 0) | ||
| 723 | #define _MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 IOMUX_PAD(0x510, 0x1C0, 7, 0x0, 0, 0) | ||
| 724 | #define _MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 IOMUX_PAD(0x514, 0x1C4, 0, 0x0, 0, 0) | ||
| 725 | #define _MX53_PAD_EIM_DA10__GPIO3_10 IOMUX_PAD(0x514, 0x1C4, 1, 0x0, 0, 0) | ||
| 726 | #define _MX53_PAD_EIM_DA10__IPU_DI1_PIN15 IOMUX_PAD(0x514, 0x1C4, 3, 0x0, 0, 0) | ||
| 727 | #define _MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, 0) | ||
| 728 | #define _MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 IOMUX_PAD(0x514, 0x1C4, 7, 0x0, 0, 0) | ||
| 729 | #define _MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 IOMUX_PAD(0x518, 0x1C8, 0, 0x0, 0, 0) | ||
| 730 | #define _MX53_PAD_EIM_DA11__GPIO3_11 IOMUX_PAD(0x518, 0x1C8, 1, 0x0, 0, 0) | ||
| 731 | #define _MX53_PAD_EIM_DA11__IPU_DI1_PIN2 IOMUX_PAD(0x518, 0x1C8, 3, 0x0, 0, 0) | ||
| 732 | #define _MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, 0) | ||
| 733 | #define _MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 IOMUX_PAD(0x51C, 0x1CC, 0, 0x0, 0, 0) | ||
| 734 | #define _MX53_PAD_EIM_DA12__GPIO3_12 IOMUX_PAD(0x51C, 0x1CC, 1, 0x0, 0, 0) | ||
| 735 | #define _MX53_PAD_EIM_DA12__IPU_DI1_PIN3 IOMUX_PAD(0x51C, 0x1CC, 3, 0x0, 0, 0) | ||
| 736 | #define _MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, 0) | ||
| 737 | #define _MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 IOMUX_PAD(0x520, 0x1D0, 0, 0x0, 0, 0) | ||
| 738 | #define _MX53_PAD_EIM_DA13__GPIO3_13 IOMUX_PAD(0x520, 0x1D0, 1, 0x0, 0, 0) | ||
| 739 | #define _MX53_PAD_EIM_DA13__IPU_DI1_D0_CS IOMUX_PAD(0x520, 0x1D0, 3, 0x0, 0, 0) | ||
| 740 | #define _MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, 0) | ||
| 741 | #define _MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 IOMUX_PAD(0x524, 0x1D4, 0, 0x0, 0, 0) | ||
| 742 | #define _MX53_PAD_EIM_DA14__GPIO3_14 IOMUX_PAD(0x524, 0x1D4, 1, 0x0, 0, 0) | ||
| 743 | #define _MX53_PAD_EIM_DA14__IPU_DI1_D1_CS IOMUX_PAD(0x524, 0x1D4, 3, 0x0, 0, 0) | ||
| 744 | #define _MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK IOMUX_PAD(0x524, 0x1D4, 4, 0x0, 0, 0) | ||
| 745 | #define _MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 IOMUX_PAD(0x528, 0x1D8, 0, 0x0, 0, 0) | ||
| 746 | #define _MX53_PAD_EIM_DA15__GPIO3_15 IOMUX_PAD(0x528, 0x1D8, 1, 0x0, 0, 0) | ||
| 747 | #define _MX53_PAD_EIM_DA15__IPU_DI1_PIN1 IOMUX_PAD(0x528, 0x1D8, 3, 0x0, 0, 0) | ||
| 748 | #define _MX53_PAD_EIM_DA15__IPU_DI1_PIN4 IOMUX_PAD(0x528, 0x1D8, 4, 0x0, 0, 0) | ||
| 749 | #define _MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B IOMUX_PAD(0x52C, 0x1DC, 0, 0x0, 0, 0) | ||
| 750 | #define _MX53_PAD_NANDF_WE_B__GPIO6_12 IOMUX_PAD(0x52C, 0x1DC, 1, 0x0, 0, 0) | ||
| 751 | #define _MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B IOMUX_PAD(0x530, 0x1E0, 0, 0x0, 0, 0) | ||
| 752 | #define _MX53_PAD_NANDF_RE_B__GPIO6_13 IOMUX_PAD(0x530, 0x1E0, 1, 0x0, 0, 0) | ||
| 753 | #define _MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT IOMUX_PAD(0x534, 0x1E4, 0, 0x0, 0, 0) | ||
| 754 | #define _MX53_PAD_EIM_WAIT__GPIO5_0 IOMUX_PAD(0x534, 0x1E4, 1, 0x0, 0, 0) | ||
| 755 | #define _MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B IOMUX_PAD(0x534, 0x1E4, 2, 0x0, 0, 0) | ||
| 756 | #define _MX53_PAD_LVDS1_TX3_P__GPIO6_22 IOMUX_PAD(NON_PAD_I, 0x1EC, 0, 0x0, 0, 0) | ||
| 757 | #define _MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 IOMUX_PAD(NON_PAD_I, 0x1EC, 1, 0x0, 0, 0) | ||
| 758 | #define _MX53_PAD_LVDS1_TX2_P__GPIO6_24 IOMUX_PAD(NON_PAD_I, 0x1F0, 0, 0x0, 0, 0) | ||
| 759 | #define _MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 IOMUX_PAD(NON_PAD_I, 0x1F0, 1, 0x0, 0, 0) | ||
| 760 | #define _MX53_PAD_LVDS1_CLK_P__GPIO6_26 IOMUX_PAD(NON_PAD_I, 0x1F4, 0, 0x0, 0, 0) | ||
| 761 | #define _MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK IOMUX_PAD(NON_PAD_I, 0x1F4, 1, 0x0, 0, 0) | ||
| 762 | #define _MX53_PAD_LVDS1_TX1_P__GPIO6_28 IOMUX_PAD(NON_PAD_I, 0x1F8, 0, 0x0, 0, 0) | ||
| 763 | #define _MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 IOMUX_PAD(NON_PAD_I, 0x1F8, 1, 0x0, 0, 0) | ||
| 764 | #define _MX53_PAD_LVDS1_TX0_P__GPIO6_30 IOMUX_PAD(NON_PAD_I, 0x1FC, 0, 0x0, 0, 0) | ||
| 765 | #define _MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 IOMUX_PAD(NON_PAD_I, 0x1FC, 1, 0x0, 0, 0) | ||
| 766 | #define _MX53_PAD_LVDS0_TX3_P__GPIO7_22 IOMUX_PAD(NON_PAD_I, 0x200, 0, 0x0, 0, 0) | ||
| 767 | #define _MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 IOMUX_PAD(NON_PAD_I, 0x200, 1, 0x0, 0, 0) | ||
| 768 | #define _MX53_PAD_LVDS0_CLK_P__GPIO7_24 IOMUX_PAD(NON_PAD_I, 0x204, 0, 0x0, 0, 0) | ||
| 769 | #define _MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK IOMUX_PAD(NON_PAD_I, 0x204, 1, 0x0, 0, 0) | ||
| 770 | #define _MX53_PAD_LVDS0_TX2_P__GPIO7_26 IOMUX_PAD(NON_PAD_I, 0x208, 0, 0x0, 0, 0) | ||
| 771 | #define _MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 IOMUX_PAD(NON_PAD_I, 0x208, 1, 0x0, 0, 0) | ||
| 772 | #define _MX53_PAD_LVDS0_TX1_P__GPIO7_28 IOMUX_PAD(NON_PAD_I, 0x20C, 0, 0x0, 0, 0) | ||
| 773 | #define _MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 IOMUX_PAD(NON_PAD_I, 0x20C, 1, 0x0, 0, 0) | ||
| 774 | #define _MX53_PAD_LVDS0_TX0_P__GPIO7_30 IOMUX_PAD(NON_PAD_I, 0x210, 0, 0x0, 0, 0) | ||
| 775 | #define _MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 IOMUX_PAD(NON_PAD_I, 0x210, 1, 0x0, 0, 0) | ||
| 776 | #define _MX53_PAD_GPIO_10__GPIO4_0 IOMUX_PAD(0x540, 0x214, 0, 0x0, 0, 0) | ||
| 777 | #define _MX53_PAD_GPIO_10__OSC32k_32K_OUT IOMUX_PAD(0x540, 0x214, 1, 0x0, 0, 0) | ||
| 778 | #define _MX53_PAD_GPIO_11__GPIO4_1 IOMUX_PAD(0x544, 0x218, 0, 0x0, 0, 0) | ||
| 779 | #define _MX53_PAD_GPIO_12__GPIO4_2 IOMUX_PAD(0x548, 0x21C, 0, 0x0, 0, 0) | ||
| 780 | #define _MX53_PAD_GPIO_13__GPIO4_3 IOMUX_PAD(0x54C, 0x220, 0, 0x0, 0, 0) | ||
| 781 | #define _MX53_PAD_GPIO_14__GPIO4_4 IOMUX_PAD(0x550, 0x224, 0, 0x0, 0, 0) | ||
| 782 | #define _MX53_PAD_NANDF_CLE__EMI_NANDF_CLE IOMUX_PAD(0x5A0, 0x228, 0, 0x0, 0, 0) | ||
| 783 | #define _MX53_PAD_NANDF_CLE__GPIO6_7 IOMUX_PAD(0x5A0, 0x228, 1, 0x0, 0, 0) | ||
| 784 | #define _MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 IOMUX_PAD(0x5A0, 0x228, 7, 0x0, 0, 0) | ||
| 785 | #define _MX53_PAD_NANDF_ALE__EMI_NANDF_ALE IOMUX_PAD(0x5A4, 0x22C, 0, 0x0, 0, 0) | ||
| 786 | #define _MX53_PAD_NANDF_ALE__GPIO6_8 IOMUX_PAD(0x5A4, 0x22C, 1, 0x0, 0, 0) | ||
| 787 | #define _MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 IOMUX_PAD(0x5A4, 0x22C, 7, 0x0, 0, 0) | ||
| 788 | #define _MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B IOMUX_PAD(0x5A8, 0x230, 0, 0x0, 0, 0) | ||
| 789 | #define _MX53_PAD_NANDF_WP_B__GPIO6_9 IOMUX_PAD(0x5A8, 0x230, 1, 0x0, 0, 0) | ||
| 790 | #define _MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 IOMUX_PAD(0x5A8, 0x230, 7, 0x0, 0, 0) | ||
| 791 | #define _MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 IOMUX_PAD(0x5AC, 0x234, 0, 0x0, 0, 0) | ||
| 792 | #define _MX53_PAD_NANDF_RB0__GPIO6_10 IOMUX_PAD(0x5AC, 0x234, 1, 0x0, 0, 0) | ||
| 793 | #define _MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 IOMUX_PAD(0x5AC, 0x234, 7, 0x0, 0, 0) | ||
| 794 | #define _MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 IOMUX_PAD(0x5B0, 0x238, 0, 0x0, 0, 0) | ||
| 795 | #define _MX53_PAD_NANDF_CS0__GPIO6_11 IOMUX_PAD(0x5B0, 0x238, 1, 0x0, 0, 0) | ||
| 796 | #define _MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 IOMUX_PAD(0x5B0, 0x238, 7, 0x0, 0, 0) | ||
| 797 | #define _MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 IOMUX_PAD(0x5B4, 0x23C, 0, 0x0, 0, 0) | ||
| 798 | #define _MX53_PAD_NANDF_CS1__GPIO6_14 IOMUX_PAD(0x5B4, 0x23C, 1, 0x0, 0, 0) | ||
| 799 | #define _MX53_PAD_NANDF_CS1__MLB_MLBCLK IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, 0) | ||
| 800 | #define _MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 IOMUX_PAD(0x5B4, 0x23C, 7, 0x0, 0, 0) | ||
| 801 | #define _MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 IOMUX_PAD(0x5B8, 0x240, 0, 0x0, 0, 0) | ||
| 802 | #define _MX53_PAD_NANDF_CS2__GPIO6_15 IOMUX_PAD(0x5B8, 0x240, 1, 0x0, 0, 0) | ||
| 803 | #define _MX53_PAD_NANDF_CS2__IPU_SISG_0 IOMUX_PAD(0x5B8, 0x240, 2, 0x0, 0, 0) | ||
| 804 | #define _MX53_PAD_NANDF_CS2__ESAI1_TX0 IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, 0) | ||
| 805 | #define _MX53_PAD_NANDF_CS2__EMI_WEIM_CRE IOMUX_PAD(0x5B8, 0x240, 4, 0x0, 0, 0) | ||
| 806 | #define _MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK IOMUX_PAD(0x5B8, 0x240, 5, 0x0, 0, 0) | ||
| 807 | #define _MX53_PAD_NANDF_CS2__MLB_MLBSIG IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, 0) | ||
| 808 | #define _MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 IOMUX_PAD(0x5B8, 0x240, 7, 0x0, 0, 0) | ||
| 809 | #define _MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 IOMUX_PAD(0x5BC, 0x244, 0, 0x0, 0, 0) | ||
| 810 | #define _MX53_PAD_NANDF_CS3__GPIO6_16 IOMUX_PAD(0x5BC, 0x244, 1, 0x0, 0, 0) | ||
| 811 | #define _MX53_PAD_NANDF_CS3__IPU_SISG_1 IOMUX_PAD(0x5BC, 0x244, 2, 0x0, 0, 0) | ||
| 812 | #define _MX53_PAD_NANDF_CS3__ESAI1_TX1 IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, 0) | ||
| 813 | #define _MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 IOMUX_PAD(0x5BC, 0x244, 4, 0x0, 0, 0) | ||
| 814 | #define _MX53_PAD_NANDF_CS3__MLB_MLBDAT IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, 0) | ||
| 815 | #define _MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 IOMUX_PAD(0x5BC, 0x244, 7, 0x0, 0, 0) | ||
| 816 | #define _MX53_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, 0) | ||
| 817 | #define _MX53_PAD_FEC_MDIO__GPIO1_22 IOMUX_PAD(0x5C4, 0x248, 1, 0x0, 0, 0) | ||
| 818 | #define _MX53_PAD_FEC_MDIO__ESAI1_SCKR IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, 0) | ||
| 819 | #define _MX53_PAD_FEC_MDIO__FEC_COL IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, 0) | ||
| 820 | #define _MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 IOMUX_PAD(0x5C4, 0x248, 4, 0x0, 0, 0) | ||
| 821 | #define _MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 IOMUX_PAD(0x5C4, 0x248, 5, 0x0, 0, 0) | ||
| 822 | #define _MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 IOMUX_PAD(0x5C4, 0x248, 6, 0x0, 0, 0) | ||
| 823 | #define _MX53_PAD_FEC_REF_CLK__FEC_TX_CLK IOMUX_PAD(0x5C8, 0x24C, 0, 0x0, 0, 0) | ||
| 824 | #define _MX53_PAD_FEC_REF_CLK__GPIO1_23 IOMUX_PAD(0x5C8, 0x24C, 1, 0x0, 0, 0) | ||
| 825 | #define _MX53_PAD_FEC_REF_CLK__ESAI1_FSR IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, 0) | ||
| 826 | #define _MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 IOMUX_PAD(0x5C8, 0x24C, 5, 0x0, 0, 0) | ||
| 827 | #define _MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 IOMUX_PAD(0x5C8, 0x24C, 6, 0x0, 0, 0) | ||
| 828 | #define _MX53_PAD_FEC_RX_ER__FEC_RX_ER IOMUX_PAD(0x5CC, 0x250, 0, 0x0, 0, 0) | ||
| 829 | #define _MX53_PAD_FEC_RX_ER__GPIO1_24 IOMUX_PAD(0x5CC, 0x250, 1, 0x0, 0, 0) | ||
| 830 | #define _MX53_PAD_FEC_RX_ER__ESAI1_HCKR IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, 0) | ||
| 831 | #define _MX53_PAD_FEC_RX_ER__FEC_RX_CLK IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, 0) | ||
| 832 | #define _MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 IOMUX_PAD(0x5CC, 0x250, 4, 0x0, 0, 0) | ||
| 833 | #define _MX53_PAD_FEC_CRS_DV__FEC_RX_DV IOMUX_PAD(0x5D0, 0x254, 0, 0x0, 0, 0) | ||
| 834 | #define _MX53_PAD_FEC_CRS_DV__GPIO1_25 IOMUX_PAD(0x5D0, 0x254, 1, 0x0, 0, 0) | ||
| 835 | #define _MX53_PAD_FEC_CRS_DV__ESAI1_SCKT IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, 0) | ||
| 836 | #define _MX53_PAD_FEC_RXD1__FEC_RDATA_1 IOMUX_PAD(0x5D4, 0x258, 0, 0x0, 0, 0) | ||
| 837 | #define _MX53_PAD_FEC_RXD1__GPIO1_26 IOMUX_PAD(0x5D4, 0x258, 1, 0x0, 0, 0) | ||
| 838 | #define _MX53_PAD_FEC_RXD1__ESAI1_FST IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, 0) | ||
| 839 | #define _MX53_PAD_FEC_RXD1__MLB_MLBSIG IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, 0) | ||
| 840 | #define _MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 IOMUX_PAD(0x5D4, 0x258, 4, 0x0, 0, 0) | ||
| 841 | #define _MX53_PAD_FEC_RXD0__FEC_RDATA_0 IOMUX_PAD(0x5D8, 0x25C, 0, 0x0, 0, 0) | ||
| 842 | #define _MX53_PAD_FEC_RXD0__GPIO1_27 IOMUX_PAD(0x5D8, 0x25C, 1, 0x0, 0, 0) | ||
| 843 | #define _MX53_PAD_FEC_RXD0__ESAI1_HCKT IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, 0) | ||
| 844 | #define _MX53_PAD_FEC_RXD0__OSC32k_32K_OUT IOMUX_PAD(0x5D8, 0x25C, 3, 0x0, 0, 0) | ||
| 845 | #define _MX53_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x5DC, 0x260, 0, 0x0, 0, 0) | ||
| 846 | #define _MX53_PAD_FEC_TX_EN__GPIO1_28 IOMUX_PAD(0x5DC, 0x260, 1, 0x0, 0, 0) | ||
| 847 | #define _MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, 0) | ||
| 848 | #define _MX53_PAD_FEC_TXD1__FEC_TDATA_1 IOMUX_PAD(0x5E0, 0x264, 0, 0x0, 0, 0) | ||
| 849 | #define _MX53_PAD_FEC_TXD1__GPIO1_29 IOMUX_PAD(0x5E0, 0x264, 1, 0x0, 0, 0) | ||
| 850 | #define _MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, 0) | ||
| 851 | #define _MX53_PAD_FEC_TXD1__MLB_MLBCLK IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, 0) | ||
| 852 | #define _MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK IOMUX_PAD(0x5E0, 0x264, 4, 0x0, 0, 0) | ||
| 853 | #define _MX53_PAD_FEC_TXD0__FEC_TDATA_0 IOMUX_PAD(0x5E4, 0x268, 0, 0x0, 0, 0) | ||
| 854 | #define _MX53_PAD_FEC_TXD0__GPIO1_30 IOMUX_PAD(0x5E4, 0x268, 1, 0x0, 0, 0) | ||
| 855 | #define _MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, 0) | ||
| 856 | #define _MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 IOMUX_PAD(0x5E4, 0x268, 7, 0x0, 0, 0) | ||
| 857 | #define _MX53_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x5E8, 0x26C, 0, 0x0, 0, 0) | ||
| 858 | #define _MX53_PAD_FEC_MDC__GPIO1_31 IOMUX_PAD(0x5E8, 0x26C, 1, 0x0, 0, 0) | ||
| 859 | #define _MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, 0) | ||
| 860 | #define _MX53_PAD_FEC_MDC__MLB_MLBDAT IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, 0) | ||
| 861 | #define _MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG IOMUX_PAD(0x5E8, 0x26C, 4, 0x0, 0, 0) | ||
| 862 | #define _MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 IOMUX_PAD(0x5E8, 0x26C, 7, 0x0, 0, 0) | ||
| 863 | #define _MX53_PAD_PATA_DIOW__PATA_DIOW IOMUX_PAD(0x5F0, 0x270, 0, 0x0, 0, 0) | ||
| 864 | #define _MX53_PAD_PATA_DIOW__GPIO6_17 IOMUX_PAD(0x5F0, 0x270, 1, 0x0, 0, 0) | ||
| 865 | #define _MX53_PAD_PATA_DIOW__UART1_TXD_MUX IOMUX_PAD(0x5F0, 0x270, 3, 0x0, 0, 0) | ||
| 866 | #define _MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 IOMUX_PAD(0x5F0, 0x270, 7, 0x0, 0, 0) | ||
| 867 | #define _MX53_PAD_PATA_DMACK__PATA_DMACK IOMUX_PAD(0x5F4, 0x274, 0, 0x0, 0, 0) | ||
| 868 | #define _MX53_PAD_PATA_DMACK__GPIO6_18 IOMUX_PAD(0x5F4, 0x274, 1, 0x0, 0, 0) | ||
| 869 | #define _MX53_PAD_PATA_DMACK__UART1_RXD_MUX IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, 0) | ||
| 870 | #define _MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 IOMUX_PAD(0x5F4, 0x274, 7, 0x0, 0, 0) | ||
| 871 | #define _MX53_PAD_PATA_DMARQ__PATA_DMARQ IOMUX_PAD(0x5F8, 0x278, 0, 0x0, 0, 0) | ||
| 872 | #define _MX53_PAD_PATA_DMARQ__GPIO7_0 IOMUX_PAD(0x5F8, 0x278, 1, 0x0, 0, 0) | ||
| 873 | #define _MX53_PAD_PATA_DMARQ__UART2_TXD_MUX IOMUX_PAD(0x5F8, 0x278, 3, 0x0, 0, 0) | ||
| 874 | #define _MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 IOMUX_PAD(0x5F8, 0x278, 5, 0x0, 0, 0) | ||
| 875 | #define _MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 IOMUX_PAD(0x5F8, 0x278, 7, 0x0, 0, 0) | ||
| 876 | #define _MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN IOMUX_PAD(0x5FC, 0x27C, 0, 0x0, 0, 0) | ||
| 877 | #define _MX53_PAD_PATA_BUFFER_EN__GPIO7_1 IOMUX_PAD(0x5FC, 0x27C, 1, 0x0, 0, 0) | ||
| 878 | #define _MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, 0) | ||
| 879 | #define _MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 IOMUX_PAD(0x5FC, 0x27C, 5, 0x0, 0, 0) | ||
| 880 | #define _MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 IOMUX_PAD(0x5FC, 0x27C, 7, 0x0, 0, 0) | ||
| 881 | #define _MX53_PAD_PATA_INTRQ__PATA_INTRQ IOMUX_PAD(0x600, 0x280, 0, 0x0, 0, 0) | ||
| 882 | #define _MX53_PAD_PATA_INTRQ__GPIO7_2 IOMUX_PAD(0x600, 0x280, 1, 0x0, 0, 0) | ||
| 883 | #define _MX53_PAD_PATA_INTRQ__UART2_CTS IOMUX_PAD(0x600, 0x280, 3, 0x0, 0, 0) | ||
| 884 | #define _MX53_PAD_PATA_INTRQ__CAN1_TXCAN IOMUX_PAD(0x600, 0x280, 4, 0x0, 0, 0) | ||
| 885 | #define _MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 IOMUX_PAD(0x600, 0x280, 5, 0x0, 0, 0) | ||
| 886 | #define _MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 IOMUX_PAD(0x600, 0x280, 7, 0x0, 0, 0) | ||
| 887 | #define _MX53_PAD_PATA_DIOR__PATA_DIOR IOMUX_PAD(0x604, 0x284, 0, 0x0, 0, 0) | ||
| 888 | #define _MX53_PAD_PATA_DIOR__GPIO7_3 IOMUX_PAD(0x604, 0x284, 1, 0x0, 0, 0) | ||
| 889 | #define _MX53_PAD_PATA_DIOR__UART2_RTS IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, 0) | ||
| 890 | #define _MX53_PAD_PATA_DIOR__CAN1_RXCAN IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, 0) | ||
| 891 | #define _MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 IOMUX_PAD(0x604, 0x284, 7, 0x0, 0, 0) | ||
| 892 | #define _MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B IOMUX_PAD(0x608, 0x288, 0, 0x0, 0, 0) | ||
| 893 | #define _MX53_PAD_PATA_RESET_B__GPIO7_4 IOMUX_PAD(0x608, 0x288, 1, 0x0, 0, 0) | ||
| 894 | #define _MX53_PAD_PATA_RESET_B__ESDHC3_CMD IOMUX_PAD(0x608, 0x288, 2, 0x0, 0, 0) | ||
| 895 | #define _MX53_PAD_PATA_RESET_B__UART1_CTS IOMUX_PAD(0x608, 0x288, 3, 0x0, 0, 0) | ||
| 896 | #define _MX53_PAD_PATA_RESET_B__CAN2_TXCAN IOMUX_PAD(0x608, 0x288, 4, 0x0, 0, 0) | ||
| 897 | #define _MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 IOMUX_PAD(0x608, 0x288, 7, 0x0, 0, 0) | ||
| 898 | #define _MX53_PAD_PATA_IORDY__PATA_IORDY IOMUX_PAD(0x60C, 0x28C, 0, 0x0, 0, 0) | ||
| 899 | #define _MX53_PAD_PATA_IORDY__GPIO7_5 IOMUX_PAD(0x60C, 0x28C, 1, 0x0, 0, 0) | ||
| 900 | #define _MX53_PAD_PATA_IORDY__ESDHC3_CLK IOMUX_PAD(0x60C, 0x28C, 2, 0x0, 0, 0) | ||
| 901 | #define _MX53_PAD_PATA_IORDY__UART1_RTS IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, 0) | ||
| 902 | #define _MX53_PAD_PATA_IORDY__CAN2_RXCAN IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, 0) | ||
| 903 | #define _MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 IOMUX_PAD(0x60C, 0x28C, 7, 0x0, 0, 0) | ||
| 904 | #define _MX53_PAD_PATA_DA_0__PATA_DA_0 IOMUX_PAD(0x610, 0x290, 0, 0x0, 0, 0) | ||
| 905 | #define _MX53_PAD_PATA_DA_0__GPIO7_6 IOMUX_PAD(0x610, 0x290, 1, 0x0, 0, 0) | ||
| 906 | #define _MX53_PAD_PATA_DA_0__ESDHC3_RST IOMUX_PAD(0x610, 0x290, 2, 0x0, 0, 0) | ||
| 907 | #define _MX53_PAD_PATA_DA_0__OWIRE_LINE IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, 0) | ||
| 908 | #define _MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 IOMUX_PAD(0x610, 0x290, 7, 0x0, 0, 0) | ||
| 909 | #define _MX53_PAD_PATA_DA_1__PATA_DA_1 IOMUX_PAD(0x614, 0x294, 0, 0x0, 0, 0) | ||
| 910 | #define _MX53_PAD_PATA_DA_1__GPIO7_7 IOMUX_PAD(0x614, 0x294, 1, 0x0, 0, 0) | ||
| 911 | #define _MX53_PAD_PATA_DA_1__ESDHC4_CMD IOMUX_PAD(0x614, 0x294, 2, 0x0, 0, 0) | ||
| 912 | #define _MX53_PAD_PATA_DA_1__UART3_CTS IOMUX_PAD(0x614, 0x294, 4, 0x0, 0, 0) | ||
| 913 | #define _MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 IOMUX_PAD(0x614, 0x294, 7, 0x0, 0, 0) | ||
| 914 | #define _MX53_PAD_PATA_DA_2__PATA_DA_2 IOMUX_PAD(0x618, 0x298, 0, 0x0, 0, 0) | ||
| 915 | #define _MX53_PAD_PATA_DA_2__GPIO7_8 IOMUX_PAD(0x618, 0x298, 1, 0x0, 0, 0) | ||
| 916 | #define _MX53_PAD_PATA_DA_2__ESDHC4_CLK IOMUX_PAD(0x618, 0x298, 2, 0x0, 0, 0) | ||
| 917 | #define _MX53_PAD_PATA_DA_2__UART3_RTS IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, 0) | ||
| 918 | #define _MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 IOMUX_PAD(0x618, 0x298, 7, 0x0, 0, 0) | ||
| 919 | #define _MX53_PAD_PATA_CS_0__PATA_CS_0 IOMUX_PAD(0x61C, 0x29C, 0, 0x0, 0, 0) | ||
| 920 | #define _MX53_PAD_PATA_CS_0__GPIO7_9 IOMUX_PAD(0x61C, 0x29C, 1, 0x0, 0, 0) | ||
| 921 | #define _MX53_PAD_PATA_CS_0__UART3_TXD_MUX IOMUX_PAD(0x61C, 0x29C, 4, 0x0, 0, 0) | ||
| 922 | #define _MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 IOMUX_PAD(0x61C, 0x29C, 7, 0x0, 0, 0) | ||
| 923 | #define _MX53_PAD_PATA_CS_1__PATA_CS_1 IOMUX_PAD(0x620, 0x2A0, 0, 0x0, 0, 0) | ||
| 924 | #define _MX53_PAD_PATA_CS_1__GPIO7_10 IOMUX_PAD(0x620, 0x2A0, 1, 0x0, 0, 0) | ||
| 925 | #define _MX53_PAD_PATA_CS_1__UART3_RXD_MUX IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, 0) | ||
| 926 | #define _MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 IOMUX_PAD(0x620, 0x2A0, 7, 0x0, 0, 0) | ||
| 927 | #define _MX53_PAD_PATA_DATA0__PATA_DATA_0 IOMUX_PAD(0x628, 0x2A4, 0, 0x0, 0, 0) | ||
| 928 | #define _MX53_PAD_PATA_DATA0__GPIO2_0 IOMUX_PAD(0x628, 0x2A4, 1, 0x0, 0, 0) | ||
| 929 | #define _MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 IOMUX_PAD(0x628, 0x2A4, 3, 0x0, 0, 0) | ||
| 930 | #define _MX53_PAD_PATA_DATA0__ESDHC3_DAT4 IOMUX_PAD(0x628, 0x2A4, 4, 0x0, 0, 0) | ||
| 931 | #define _MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 IOMUX_PAD(0x628, 0x2A4, 5, 0x0, 0, 0) | ||
| 932 | #define _MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 IOMUX_PAD(0x628, 0x2A4, 6, 0x0, 0, 0) | ||
| 933 | #define _MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 IOMUX_PAD(0x628, 0x2A4, 7, 0x0, 0, 0) | ||
| 934 | #define _MX53_PAD_PATA_DATA1__PATA_DATA_1 IOMUX_PAD(0x62C, 0x2A8, 0, 0x0, 0, 0) | ||
| 935 | #define _MX53_PAD_PATA_DATA1__GPIO2_1 IOMUX_PAD(0x62C, 0x2A8, 1, 0x0, 0, 0) | ||
| 936 | #define _MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 IOMUX_PAD(0x62C, 0x2A8, 3, 0x0, 0, 0) | ||
| 937 | #define _MX53_PAD_PATA_DATA1__ESDHC3_DAT5 IOMUX_PAD(0x62C, 0x2A8, 4, 0x0, 0, 0) | ||
| 938 | #define _MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 IOMUX_PAD(0x62C, 0x2A8, 5, 0x0, 0, 0) | ||
| 939 | #define _MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 IOMUX_PAD(0x62C, 0x2A8, 6, 0x0, 0, 0) | ||
| 940 | #define _MX53_PAD_PATA_DATA2__PATA_DATA_2 IOMUX_PAD(0x630, 0x2AC, 0, 0x0, 0, 0) | ||
| 941 | #define _MX53_PAD_PATA_DATA2__GPIO2_2 IOMUX_PAD(0x630, 0x2AC, 1, 0x0, 0, 0) | ||
| 942 | #define _MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 IOMUX_PAD(0x630, 0x2AC, 3, 0x0, 0, 0) | ||
| 943 | #define _MX53_PAD_PATA_DATA2__ESDHC3_DAT6 IOMUX_PAD(0x630, 0x2AC, 4, 0x0, 0, 0) | ||
| 944 | #define _MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 IOMUX_PAD(0x630, 0x2AC, 5, 0x0, 0, 0) | ||
| 945 | #define _MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 IOMUX_PAD(0x630, 0x2AC, 6, 0x0, 0, 0) | ||
| 946 | #define _MX53_PAD_PATA_DATA3__PATA_DATA_3 IOMUX_PAD(0x634, 0x2B0, 0, 0x0, 0, 0) | ||
| 947 | #define _MX53_PAD_PATA_DATA3__GPIO2_3 IOMUX_PAD(0x634, 0x2B0, 1, 0x0, 0, 0) | ||
| 948 | #define _MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 IOMUX_PAD(0x634, 0x2B0, 3, 0x0, 0, 0) | ||
| 949 | #define _MX53_PAD_PATA_DATA3__ESDHC3_DAT7 IOMUX_PAD(0x634, 0x2B0, 4, 0x0, 0, 0) | ||
| 950 | #define _MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 IOMUX_PAD(0x634, 0x2B0, 5, 0x0, 0, 0) | ||
| 951 | #define _MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 IOMUX_PAD(0x634, 0x2B0, 6, 0x0, 0, 0) | ||
| 952 | #define _MX53_PAD_PATA_DATA4__PATA_DATA_4 IOMUX_PAD(0x638, 0x2B4, 0, 0x0, 0, 0) | ||
| 953 | #define _MX53_PAD_PATA_DATA4__GPIO2_4 IOMUX_PAD(0x638, 0x2B4, 1, 0x0, 0, 0) | ||
| 954 | #define _MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 IOMUX_PAD(0x638, 0x2B4, 3, 0x0, 0, 0) | ||
| 955 | #define _MX53_PAD_PATA_DATA4__ESDHC4_DAT4 IOMUX_PAD(0x638, 0x2B4, 4, 0x0, 0, 0) | ||
| 956 | #define _MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 IOMUX_PAD(0x638, 0x2B4, 5, 0x0, 0, 0) | ||
| 957 | #define _MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 IOMUX_PAD(0x638, 0x2B4, 6, 0x0, 0, 0) | ||
| 958 | #define _MX53_PAD_PATA_DATA5__PATA_DATA_5 IOMUX_PAD(0x63C, 0x2B8, 0, 0x0, 0, 0) | ||
| 959 | #define _MX53_PAD_PATA_DATA5__GPIO2_5 IOMUX_PAD(0x63C, 0x2B8, 1, 0x0, 0, 0) | ||
| 960 | #define _MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 IOMUX_PAD(0x63C, 0x2B8, 3, 0x0, 0, 0) | ||
| 961 | #define _MX53_PAD_PATA_DATA5__ESDHC4_DAT5 IOMUX_PAD(0x63C, 0x2B8, 4, 0x0, 0, 0) | ||
| 962 | #define _MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 IOMUX_PAD(0x63C, 0x2B8, 5, 0x0, 0, 0) | ||
| 963 | #define _MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 IOMUX_PAD(0x63C, 0x2B8, 6, 0x0, 0, 0) | ||
| 964 | #define _MX53_PAD_PATA_DATA6__PATA_DATA_6 IOMUX_PAD(0x640, 0x2BC, 0, 0x0, 0, 0) | ||
| 965 | #define _MX53_PAD_PATA_DATA6__GPIO2_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0) | ||
| 966 | #define _MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 IOMUX_PAD(0x640, 0x2BC, 3, 0x0, 0, 0) | ||
| 967 | #define _MX53_PAD_PATA_DATA6__ESDHC4_DAT6 IOMUX_PAD(0x640, 0x2BC, 4, 0x0, 0, 0) | ||
| 968 | #define _MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 IOMUX_PAD(0x640, 0x2BC, 5, 0x0, 0, 0) | ||
| 969 | #define _MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 IOMUX_PAD(0x640, 0x2BC, 6, 0x0, 0, 0) | ||
| 970 | #define _MX53_PAD_PATA_DATA7__PATA_DATA_7 IOMUX_PAD(0x644, 0x2C0, 0, 0x0, 0, 0) | ||
| 971 | #define _MX53_PAD_PATA_DATA7__GPIO2_7 IOMUX_PAD(0x644, 0x2C0, 1, 0x0, 0, 0) | ||
| 972 | #define _MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 IOMUX_PAD(0x644, 0x2C0, 3, 0x0, 0, 0) | ||
| 973 | #define _MX53_PAD_PATA_DATA7__ESDHC4_DAT7 IOMUX_PAD(0x644, 0x2C0, 4, 0x0, 0, 0) | ||
| 974 | #define _MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 IOMUX_PAD(0x644, 0x2C0, 5, 0x0, 0, 0) | ||
| 975 | #define _MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 IOMUX_PAD(0x644, 0x2C0, 6, 0x0, 0, 0) | ||
| 976 | #define _MX53_PAD_PATA_DATA8__PATA_DATA_8 IOMUX_PAD(0x648, 0x2C4, 0, 0x0, 0, 0) | ||
| 977 | #define _MX53_PAD_PATA_DATA8__GPIO2_8 IOMUX_PAD(0x648, 0x2C4, 1, 0x0, 0, 0) | ||
| 978 | #define _MX53_PAD_PATA_DATA8__ESDHC1_DAT4 IOMUX_PAD(0x648, 0x2C4, 2, 0x0, 0, 0) | ||
| 979 | #define _MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 IOMUX_PAD(0x648, 0x2C4, 3, 0x0, 0, 0) | ||
| 980 | #define _MX53_PAD_PATA_DATA8__ESDHC3_DAT0 IOMUX_PAD(0x648, 0x2C4, 4, 0x0, 0, 0) | ||
| 981 | #define _MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 IOMUX_PAD(0x648, 0x2C4, 5, 0x0, 0, 0) | ||
| 982 | #define _MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 IOMUX_PAD(0x648, 0x2C4, 6, 0x0, 0, 0) | ||
| 983 | #define _MX53_PAD_PATA_DATA9__PATA_DATA_9 IOMUX_PAD(0x64C, 0x2C8, 0, 0x0, 0, 0) | ||
| 984 | #define _MX53_PAD_PATA_DATA9__GPIO2_9 IOMUX_PAD(0x64C, 0x2C8, 1, 0x0, 0, 0) | ||
| 985 | #define _MX53_PAD_PATA_DATA9__ESDHC1_DAT5 IOMUX_PAD(0x64C, 0x2C8, 2, 0x0, 0, 0) | ||
| 986 | #define _MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 IOMUX_PAD(0x64C, 0x2C8, 3, 0x0, 0, 0) | ||
| 987 | #define _MX53_PAD_PATA_DATA9__ESDHC3_DAT1 IOMUX_PAD(0x64C, 0x2C8, 4, 0x0, 0, 0) | ||
| 988 | #define _MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 IOMUX_PAD(0x64C, 0x2C8, 5, 0x0, 0, 0) | ||
| 989 | #define _MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 IOMUX_PAD(0x64C, 0x2C8, 6, 0x0, 0, 0) | ||
| 990 | #define _MX53_PAD_PATA_DATA10__PATA_DATA_10 IOMUX_PAD(0x650, 0x2CC, 0, 0x0, 0, 0) | ||
| 991 | #define _MX53_PAD_PATA_DATA10__GPIO2_10 IOMUX_PAD(0x650, 0x2CC, 1, 0x0, 0, 0) | ||
| 992 | #define _MX53_PAD_PATA_DATA10__ESDHC1_DAT6 IOMUX_PAD(0x650, 0x2CC, 2, 0x0, 0, 0) | ||
| 993 | #define _MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 IOMUX_PAD(0x650, 0x2CC, 3, 0x0, 0, 0) | ||
| 994 | #define _MX53_PAD_PATA_DATA10__ESDHC3_DAT2 IOMUX_PAD(0x650, 0x2CC, 4, 0x0, 0, 0) | ||
| 995 | #define _MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 IOMUX_PAD(0x650, 0x2CC, 5, 0x0, 0, 0) | ||
| 996 | #define _MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 IOMUX_PAD(0x650, 0x2CC, 6, 0x0, 0, 0) | ||
| 997 | #define _MX53_PAD_PATA_DATA11__PATA_DATA_11 IOMUX_PAD(0x654, 0x2D0, 0, 0x0, 0, 0) | ||
| 998 | #define _MX53_PAD_PATA_DATA11__GPIO2_11 IOMUX_PAD(0x654, 0x2D0, 1, 0x0, 0, 0) | ||
| 999 | #define _MX53_PAD_PATA_DATA11__ESDHC1_DAT7 IOMUX_PAD(0x654, 0x2D0, 2, 0x0, 0, 0) | ||
| 1000 | #define _MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 IOMUX_PAD(0x654, 0x2D0, 3, 0x0, 0, 0) | ||
| 1001 | #define _MX53_PAD_PATA_DATA11__ESDHC3_DAT3 IOMUX_PAD(0x654, 0x2D0, 4, 0x0, 0, 0) | ||
| 1002 | #define _MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 IOMUX_PAD(0x654, 0x2D0, 5, 0x0, 0, 0) | ||
| 1003 | #define _MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 IOMUX_PAD(0x654, 0x2D0, 6, 0x0, 0, 0) | ||
| 1004 | #define _MX53_PAD_PATA_DATA12__PATA_DATA_12 IOMUX_PAD(0x658, 0x2D4, 0, 0x0, 0, 0) | ||
| 1005 | #define _MX53_PAD_PATA_DATA12__GPIO2_12 IOMUX_PAD(0x658, 0x2D4, 1, 0x0, 0, 0) | ||
| 1006 | #define _MX53_PAD_PATA_DATA12__ESDHC2_DAT4 IOMUX_PAD(0x658, 0x2D4, 2, 0x0, 0, 0) | ||
| 1007 | #define _MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 IOMUX_PAD(0x658, 0x2D4, 3, 0x0, 0, 0) | ||
| 1008 | #define _MX53_PAD_PATA_DATA12__ESDHC4_DAT0 IOMUX_PAD(0x658, 0x2D4, 4, 0x0, 0, 0) | ||
| 1009 | #define _MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 IOMUX_PAD(0x658, 0x2D4, 5, 0x0, 0, 0) | ||
| 1010 | #define _MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 IOMUX_PAD(0x658, 0x2D4, 6, 0x0, 0, 0) | ||
| 1011 | #define _MX53_PAD_PATA_DATA13__PATA_DATA_13 IOMUX_PAD(0x65C, 0x2D8, 0, 0x0, 0, 0) | ||
| 1012 | #define _MX53_PAD_PATA_DATA13__GPIO2_13 IOMUX_PAD(0x65C, 0x2D8, 1, 0x0, 0, 0) | ||
| 1013 | #define _MX53_PAD_PATA_DATA13__ESDHC2_DAT5 IOMUX_PAD(0x65C, 0x2D8, 2, 0x0, 0, 0) | ||
| 1014 | #define _MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 IOMUX_PAD(0x65C, 0x2D8, 3, 0x0, 0, 0) | ||
| 1015 | #define _MX53_PAD_PATA_DATA13__ESDHC4_DAT1 IOMUX_PAD(0x65C, 0x2D8, 4, 0x0, 0, 0) | ||
| 1016 | #define _MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 IOMUX_PAD(0x65C, 0x2D8, 5, 0x0, 0, 0) | ||
| 1017 | #define _MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 IOMUX_PAD(0x65C, 0x2D8, 6, 0x0, 0, 0) | ||
| 1018 | #define _MX53_PAD_PATA_DATA14__PATA_DATA_14 IOMUX_PAD(0x660, 0x2DC, 0, 0x0, 0, 0) | ||
| 1019 | #define _MX53_PAD_PATA_DATA14__GPIO2_14 IOMUX_PAD(0x660, 0x2DC, 1, 0x0, 0, 0) | ||
| 1020 | #define _MX53_PAD_PATA_DATA14__ESDHC2_DAT6 IOMUX_PAD(0x660, 0x2DC, 2, 0x0, 0, 0) | ||
| 1021 | #define _MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 IOMUX_PAD(0x660, 0x2DC, 3, 0x0, 0, 0) | ||
| 1022 | #define _MX53_PAD_PATA_DATA14__ESDHC4_DAT2 IOMUX_PAD(0x660, 0x2DC, 4, 0x0, 0, 0) | ||
| 1023 | #define _MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 IOMUX_PAD(0x660, 0x2DC, 5, 0x0, 0, 0) | ||
| 1024 | #define _MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 IOMUX_PAD(0x660, 0x2DC, 6, 0x0, 0, 0) | ||
| 1025 | #define _MX53_PAD_PATA_DATA15__PATA_DATA_15 IOMUX_PAD(0x664, 0x2E0, 0, 0x0, 0, 0) | ||
| 1026 | #define _MX53_PAD_PATA_DATA15__GPIO2_15 IOMUX_PAD(0x664, 0x2E0, 1, 0x0, 0, 0) | ||
| 1027 | #define _MX53_PAD_PATA_DATA15__ESDHC2_DAT7 IOMUX_PAD(0x664, 0x2E0, 2, 0x0, 0, 0) | ||
| 1028 | #define _MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 IOMUX_PAD(0x664, 0x2E0, 3, 0x0, 0, 0) | ||
| 1029 | #define _MX53_PAD_PATA_DATA15__ESDHC4_DAT3 IOMUX_PAD(0x664, 0x2E0, 4, 0x0, 0, 0) | ||
| 1030 | #define _MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 IOMUX_PAD(0x664, 0x2E0, 5, 0x0, 0, 0) | ||
| 1031 | #define _MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 IOMUX_PAD(0x664, 0x2E0, 6, 0x0, 0, 0) | ||
| 1032 | #define _MX53_PAD_SD1_DATA0__ESDHC1_DAT0 IOMUX_PAD(0x66C, 0x2E4, 0, 0x0, 0, 0) | ||
| 1033 | #define _MX53_PAD_SD1_DATA0__GPIO1_16 IOMUX_PAD(0x66C, 0x2E4, 1, 0x0, 0, 0) | ||
| 1034 | #define _MX53_PAD_SD1_DATA0__GPT_CAPIN1 IOMUX_PAD(0x66C, 0x2E4, 3, 0x0, 0, 0) | ||
| 1035 | #define _MX53_PAD_SD1_DATA0__CSPI_MISO IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, 0) | ||
| 1036 | #define _MX53_PAD_SD1_DATA0__CCM_PLL3_BYP IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, 0) | ||
| 1037 | #define _MX53_PAD_SD1_DATA1__ESDHC1_DAT1 IOMUX_PAD(0x670, 0x2E8, 0, 0x0, 0, 0) | ||
| 1038 | #define _MX53_PAD_SD1_DATA1__GPIO1_17 IOMUX_PAD(0x670, 0x2E8, 1, 0x0, 0, 0) | ||
| 1039 | #define _MX53_PAD_SD1_DATA1__GPT_CAPIN2 IOMUX_PAD(0x670, 0x2E8, 3, 0x0, 0, 0) | ||
| 1040 | #define _MX53_PAD_SD1_DATA1__CSPI_SS0 IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, 0) | ||
| 1041 | #define _MX53_PAD_SD1_DATA1__CCM_PLL4_BYP IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, 0) | ||
| 1042 | #define _MX53_PAD_SD1_CMD__ESDHC1_CMD IOMUX_PAD(0x674, 0x2EC, IOMUX_CONFIG_SION, 0x0, 0, 0) | ||
| 1043 | #define _MX53_PAD_SD1_CMD__GPIO1_18 IOMUX_PAD(0x674, 0x2EC, 1, 0x0, 0, 0) | ||
| 1044 | #define _MX53_PAD_SD1_CMD__GPT_CMPOUT1 IOMUX_PAD(0x674, 0x2EC, 3, 0x0, 0, 0) | ||
| 1045 | #define _MX53_PAD_SD1_CMD__CSPI_MOSI IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, 0) | ||
| 1046 | #define _MX53_PAD_SD1_CMD__CCM_PLL1_BYP IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, 0) | ||
| 1047 | #define _MX53_PAD_SD1_DATA2__ESDHC1_DAT2 IOMUX_PAD(0x678, 0x2F0, 0, 0x0, 0, 0) | ||
| 1048 | #define _MX53_PAD_SD1_DATA2__GPIO1_19 IOMUX_PAD(0x678, 0x2F0, 1, 0x0, 0, 0) | ||
| 1049 | #define _MX53_PAD_SD1_DATA2__GPT_CMPOUT2 IOMUX_PAD(0x678, 0x2F0, 2, 0x0, 0, 0) | ||
| 1050 | #define _MX53_PAD_SD1_DATA2__PWM2_PWMO IOMUX_PAD(0x678, 0x2F0, 3, 0x0, 0, 0) | ||
| 1051 | #define _MX53_PAD_SD1_DATA2__WDOG1_WDOG_B IOMUX_PAD(0x678, 0x2F0, 4, 0x0, 0, 0) | ||
| 1052 | #define _MX53_PAD_SD1_DATA2__CSPI_SS1 IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, 0) | ||
| 1053 | #define _MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB IOMUX_PAD(0x678, 0x2F0, 6, 0x0, 0, 0) | ||
| 1054 | #define _MX53_PAD_SD1_DATA2__CCM_PLL2_BYP IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, 0) | ||
| 1055 | #define _MX53_PAD_SD1_CLK__ESDHC1_CLK IOMUX_PAD(0x67C, 0x2F4, 0, 0x0, 0, 0) | ||
| 1056 | #define _MX53_PAD_SD1_CLK__GPIO1_20 IOMUX_PAD(0x67C, 0x2F4, 1, 0x0, 0, 0) | ||
| 1057 | #define _MX53_PAD_SD1_CLK__OSC32k_32K_OUT IOMUX_PAD(0x67C, 0x2F4, 2, 0x0, 0, 0) | ||
| 1058 | #define _MX53_PAD_SD1_CLK__GPT_CLKIN IOMUX_PAD(0x67C, 0x2F4, 3, 0x0, 0, 0) | ||
| 1059 | #define _MX53_PAD_SD1_CLK__CSPI_SCLK IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, 0) | ||
| 1060 | #define _MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 IOMUX_PAD(0x67C, 0x2F4, 7, 0x0, 0, 0) | ||
| 1061 | #define _MX53_PAD_SD1_DATA3__ESDHC1_DAT3 IOMUX_PAD(0x680, 0x2F8, 0, 0x0, 0, 0) | ||
| 1062 | #define _MX53_PAD_SD1_DATA3__GPIO1_21 IOMUX_PAD(0x680, 0x2F8, 1, 0x0, 0, 0) | ||
| 1063 | #define _MX53_PAD_SD1_DATA3__GPT_CMPOUT3 IOMUX_PAD(0x680, 0x2F8, 2, 0x0, 0, 0) | ||
| 1064 | #define _MX53_PAD_SD1_DATA3__PWM1_PWMO IOMUX_PAD(0x680, 0x2F8, 3, 0x0, 0, 0) | ||
| 1065 | #define _MX53_PAD_SD1_DATA3__WDOG2_WDOG_B IOMUX_PAD(0x680, 0x2F8, 4, 0x0, 0, 0) | ||
| 1066 | #define _MX53_PAD_SD1_DATA3__CSPI_SS2 IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, 0) | ||
| 1067 | #define _MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB IOMUX_PAD(0x680, 0x2F8, 6, 0x0, 0, 0) | ||
| 1068 | #define _MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 IOMUX_PAD(0x680, 0x2F8, 7, 0x0, 0, 0) | ||
| 1069 | #define _MX53_PAD_SD2_CLK__ESDHC2_CLK IOMUX_PAD(0x688, 0x2FC, 0, 0x0, 0, 0) | ||
| 1070 | #define _MX53_PAD_SD2_CLK__GPIO1_10 IOMUX_PAD(0x688, 0x2FC, 1, 0x0, 0, 0) | ||
| 1071 | #define _MX53_PAD_SD2_CLK__KPP_COL_5 IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, 0) | ||
| 1072 | #define _MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, 0) | ||
| 1073 | #define _MX53_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, 0) | ||
| 1074 | #define _MX53_PAD_SD2_CLK__SCC_RANDOM_V IOMUX_PAD(0x688, 0x2FC, 7, 0x0, 0, 0) | ||
| 1075 | #define _MX53_PAD_SD2_CMD__ESDHC2_CMD IOMUX_PAD(0x68C, 0x300, 0, 0x0, 0, 0) | ||
| 1076 | #define _MX53_PAD_SD2_CMD__GPIO1_11 IOMUX_PAD(0x68C, 0x300, 1, 0x0, 0, 0) | ||
| 1077 | #define _MX53_PAD_SD2_CMD__KPP_ROW_5 IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, 0) | ||
| 1078 | #define _MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, 0) | ||
| 1079 | #define _MX53_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, 0) | ||
| 1080 | #define _MX53_PAD_SD2_CMD__SCC_RANDOM IOMUX_PAD(0x68C, 0x300, 7, 0x0, 0, 0) | ||
| 1081 | #define _MX53_PAD_SD2_DATA3__ESDHC2_DAT3 IOMUX_PAD(0x690, 0x304, 0, 0x0, 0, 0) | ||
| 1082 | #define _MX53_PAD_SD2_DATA3__GPIO1_12 IOMUX_PAD(0x690, 0x304, 1, 0x0, 0, 0) | ||
| 1083 | #define _MX53_PAD_SD2_DATA3__KPP_COL_6 IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, 0) | ||
| 1084 | #define _MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, 0) | ||
| 1085 | #define _MX53_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, 0) | ||
| 1086 | #define _MX53_PAD_SD2_DATA3__SJC_DONE IOMUX_PAD(0x690, 0x304, 7, 0x0, 0, 0) | ||
| 1087 | #define _MX53_PAD_SD2_DATA2__ESDHC2_DAT2 IOMUX_PAD(0x694, 0x308, 0, 0x0, 0, 0) | ||
| 1088 | #define _MX53_PAD_SD2_DATA2__GPIO1_13 IOMUX_PAD(0x694, 0x308, 1, 0x0, 0, 0) | ||
| 1089 | #define _MX53_PAD_SD2_DATA2__KPP_ROW_6 IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, 0) | ||
| 1090 | #define _MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, 0) | ||
| 1091 | #define _MX53_PAD_SD2_DATA2__CSPI_SS1 IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, 0) | ||
| 1092 | #define _MX53_PAD_SD2_DATA2__SJC_FAIL IOMUX_PAD(0x694, 0x308, 7, 0x0, 0, 0) | ||
| 1093 | #define _MX53_PAD_SD2_DATA1__ESDHC2_DAT1 IOMUX_PAD(0x698, 0x30C, 0, 0x0, 0, 0) | ||
| 1094 | #define _MX53_PAD_SD2_DATA1__GPIO1_14 IOMUX_PAD(0x698, 0x30C, 1, 0x0, 0, 0) | ||
| 1095 | #define _MX53_PAD_SD2_DATA1__KPP_COL_7 IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, 0) | ||
| 1096 | #define _MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, 0) | ||
| 1097 | #define _MX53_PAD_SD2_DATA1__CSPI_SS0 IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, 0) | ||
| 1098 | #define _MX53_PAD_SD2_DATA1__RTIC_SEC_VIO IOMUX_PAD(0x698, 0x30C, 7, 0x0, 0, 0) | ||
| 1099 | #define _MX53_PAD_SD2_DATA0__ESDHC2_DAT0 IOMUX_PAD(0x69C, 0x310, 0, 0x0, 0, 0) | ||
| 1100 | #define _MX53_PAD_SD2_DATA0__GPIO1_15 IOMUX_PAD(0x69C, 0x310, 1, 0x0, 0, 0) | ||
| 1101 | #define _MX53_PAD_SD2_DATA0__KPP_ROW_7 IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, 0) | ||
| 1102 | #define _MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, 0) | ||
| 1103 | #define _MX53_PAD_SD2_DATA0__CSPI_MISO IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, 0) | ||
| 1104 | #define _MX53_PAD_SD2_DATA0__RTIC_DONE_INT IOMUX_PAD(0x69C, 0x310, 7, 0x0, 0, 0) | ||
| 1105 | #define _MX53_PAD_GPIO_0__CCM_CLKO IOMUX_PAD(0x6A4, 0x314, 0, 0x0, 0, 0) | ||
| 1106 | #define _MX53_PAD_GPIO_0__GPIO1_0 IOMUX_PAD(0x6A4, 0x314, 1, 0x0, 0, 0) | ||
| 1107 | #define _MX53_PAD_GPIO_0__KPP_COL_5 IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, 0) | ||
| 1108 | #define _MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK IOMUX_PAD(0x6A4, 0x314, 3, 0x0, 0, 0) | ||
| 1109 | #define _MX53_PAD_GPIO_0__EPIT1_EPITO IOMUX_PAD(0x6A4, 0x314, 4, 0x0, 0, 0) | ||
| 1110 | #define _MX53_PAD_GPIO_0__SRTC_ALARM_DEB IOMUX_PAD(0x6A4, 0x314, 5, 0x0, 0, 0) | ||
| 1111 | #define _MX53_PAD_GPIO_0__USBOH3_USBH1_PWR IOMUX_PAD(0x6A4, 0x314, 6, 0x0, 0, 0) | ||
| 1112 | #define _MX53_PAD_GPIO_0__CSU_TD IOMUX_PAD(0x6A4, 0x314, 7, 0x0, 0, 0) | ||
| 1113 | #define _MX53_PAD_GPIO_1__ESAI1_SCKR IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, 0) | ||
| 1114 | #define _MX53_PAD_GPIO_1__GPIO1_1 IOMUX_PAD(0x6A8, 0x318, 1, 0x0, 0, 0) | ||
| 1115 | #define _MX53_PAD_GPIO_1__KPP_ROW_5 IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, 0) | ||
| 1116 | #define _MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK IOMUX_PAD(0x6A8, 0x318, 3, 0x0, 0, 0) | ||
| 1117 | #define _MX53_PAD_GPIO_1__PWM2_PWMO IOMUX_PAD(0x6A8, 0x318, 4, 0x0, 0, 0) | ||
| 1118 | #define _MX53_PAD_GPIO_1__WDOG2_WDOG_B IOMUX_PAD(0x6A8, 0x318, 5, 0x0, 0, 0) | ||
| 1119 | #define _MX53_PAD_GPIO_1__ESDHC1_CD IOMUX_PAD(0x6A8, 0x318, 6, 0x0, 0, 0) | ||
| 1120 | #define _MX53_PAD_GPIO_1__SRC_TESTER_ACK IOMUX_PAD(0x6A8, 0x318, 7, 0x0, 0, 0) | ||
| 1121 | #define _MX53_PAD_GPIO_9__ESAI1_FSR IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, 0) | ||
| 1122 | #define _MX53_PAD_GPIO_9__GPIO1_9 IOMUX_PAD(0x6AC, 0x31C, 1, 0x0, 0, 0) | ||
| 1123 | #define _MX53_PAD_GPIO_9__KPP_COL_6 IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, 0) | ||
| 1124 | #define _MX53_PAD_GPIO_9__CCM_REF_EN_B IOMUX_PAD(0x6AC, 0x31C, 3, 0x0, 0, 0) | ||
| 1125 | #define _MX53_PAD_GPIO_9__PWM1_PWMO IOMUX_PAD(0x6AC, 0x31C, 4, 0x0, 0, 0) | ||
| 1126 | #define _MX53_PAD_GPIO_9__WDOG1_WDOG_B IOMUX_PAD(0x6AC, 0x31C, 5, 0x0, 0, 0) | ||
| 1127 | #define _MX53_PAD_GPIO_9__ESDHC1_WP IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, 0) | ||
| 1128 | #define _MX53_PAD_GPIO_9__SCC_FAIL_STATE IOMUX_PAD(0x6AC, 0x31C, 7, 0x0, 0, 0) | ||
| 1129 | #define _MX53_PAD_GPIO_3__ESAI1_HCKR IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, 0) | ||
| 1130 | #define _MX53_PAD_GPIO_3__GPIO1_3 IOMUX_PAD(0x6B0, 0x320, 1, 0x0, 0, 0) | ||
| 1131 | #define _MX53_PAD_GPIO_3__I2C3_SCL IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, 0) | ||
| 1132 | #define _MX53_PAD_GPIO_3__DPLLIP1_TOG_EN IOMUX_PAD(0x6B0, 0x320, 3, 0x0, 0, 0) | ||
| 1133 | #define _MX53_PAD_GPIO_3__CCM_CLKO2 IOMUX_PAD(0x6B0, 0x320, 4, 0x0, 0, 0) | ||
| 1134 | #define _MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 IOMUX_PAD(0x6B0, 0x320, 5, 0x0, 0, 0) | ||
| 1135 | #define _MX53_PAD_GPIO_3__USBOH3_USBH1_OC IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, 0) | ||
| 1136 | #define _MX53_PAD_GPIO_3__MLB_MLBCLK IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, 0) | ||
| 1137 | #define _MX53_PAD_GPIO_6__ESAI1_SCKT IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, 0) | ||
| 1138 | #define _MX53_PAD_GPIO_6__GPIO1_6 IOMUX_PAD(0x6B4, 0x324, 1, 0x0, 0, 0) | ||
| 1139 | #define _MX53_PAD_GPIO_6__I2C3_SDA IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, 0) | ||
| 1140 | #define _MX53_PAD_GPIO_6__CCM_CCM_OUT_0 IOMUX_PAD(0x6B4, 0x324, 3, 0x0, 0, 0) | ||
| 1141 | #define _MX53_PAD_GPIO_6__CSU_CSU_INT_DEB IOMUX_PAD(0x6B4, 0x324, 4, 0x0, 0, 0) | ||
| 1142 | #define _MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 IOMUX_PAD(0x6B4, 0x324, 5, 0x0, 0, 0) | ||
| 1143 | #define _MX53_PAD_GPIO_6__ESDHC2_LCTL IOMUX_PAD(0x6B4, 0x324, 6, 0x0, 0, 0) | ||
| 1144 | #define _MX53_PAD_GPIO_6__MLB_MLBSIG IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, 0) | ||
| 1145 | #define _MX53_PAD_GPIO_2__ESAI1_FST IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, 0) | ||
| 1146 | #define _MX53_PAD_GPIO_2__GPIO1_2 IOMUX_PAD(0x6B8, 0x328, 1, 0x0, 0, 0) | ||
| 1147 | #define _MX53_PAD_GPIO_2__KPP_ROW_6 IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, 0) | ||
| 1148 | #define _MX53_PAD_GPIO_2__CCM_CCM_OUT_1 IOMUX_PAD(0x6B8, 0x328, 3, 0x0, 0, 0) | ||
| 1149 | #define _MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 IOMUX_PAD(0x6B8, 0x328, 4, 0x0, 0, 0) | ||
| 1150 | #define _MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 IOMUX_PAD(0x6B8, 0x328, 5, 0x0, 0, 0) | ||
| 1151 | #define _MX53_PAD_GPIO_2__ESDHC2_WP IOMUX_PAD(0x6B8, 0x328, 6, 0x0, 0, 0) | ||
| 1152 | #define _MX53_PAD_GPIO_2__MLB_MLBDAT IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, 0) | ||
| 1153 | #define _MX53_PAD_GPIO_4__ESAI1_HCKT IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, 0) | ||
| 1154 | #define _MX53_PAD_GPIO_4__GPIO1_4 IOMUX_PAD(0x6BC, 0x32C, 1, 0x0, 0, 0) | ||
| 1155 | #define _MX53_PAD_GPIO_4__KPP_COL_7 IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, 0) | ||
| 1156 | #define _MX53_PAD_GPIO_4__CCM_CCM_OUT_2 IOMUX_PAD(0x6BC, 0x32C, 3, 0x0, 0, 0) | ||
| 1157 | #define _MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 IOMUX_PAD(0x6BC, 0x32C, 4, 0x0, 0, 0) | ||
| 1158 | #define _MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 IOMUX_PAD(0x6BC, 0x32C, 5, 0x0, 0, 0) | ||
| 1159 | #define _MX53_PAD_GPIO_4__ESDHC2_CD IOMUX_PAD(0x6BC, 0x32C, 6, 0x0, 0, 0) | ||
| 1160 | #define _MX53_PAD_GPIO_4__SCC_SEC_STATE IOMUX_PAD(0x6BC, 0x32C, 7, 0x0, 0, 0) | ||
| 1161 | #define _MX53_PAD_GPIO_5__ESAI1_TX2_RX3 IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, 0) | ||
| 1162 | #define _MX53_PAD_GPIO_5__GPIO1_5 IOMUX_PAD(0x6C0, 0x330, 1, 0x0, 0, 0) | ||
| 1163 | #define _MX53_PAD_GPIO_5__KPP_ROW_7 IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, 0) | ||
| 1164 | #define _MX53_PAD_GPIO_5__CCM_CLKO IOMUX_PAD(0x6C0, 0x330, 3, 0x0, 0, 0) | ||
| 1165 | #define _MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 IOMUX_PAD(0x6C0, 0x330, 4, 0x0, 0, 0) | ||
| 1166 | #define _MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 IOMUX_PAD(0x6C0, 0x330, 5, 0x0, 0, 0) | ||
| 1167 | #define _MX53_PAD_GPIO_5__I2C3_SCL IOMUX_PAD(0x6C0, 0x330, 6 | IOMUX_CONFIG_SION, 0x824, 2, 0) | ||
| 1168 | #define _MX53_PAD_GPIO_5__CCM_PLL1_BYP IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, 0) | ||
| 1169 | #define _MX53_PAD_GPIO_7__ESAI1_TX4_RX1 IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, 0) | ||
| 1170 | #define _MX53_PAD_GPIO_7__GPIO1_7 IOMUX_PAD(0x6C4, 0x334, 1, 0x0, 0, 0) | ||
| 1171 | #define _MX53_PAD_GPIO_7__EPIT1_EPITO IOMUX_PAD(0x6C4, 0x334, 2, 0x0, 0, 0) | ||
| 1172 | #define _MX53_PAD_GPIO_7__CAN1_TXCAN IOMUX_PAD(0x6C4, 0x334, 3, 0x0, 0, 0) | ||
| 1173 | #define _MX53_PAD_GPIO_7__UART2_TXD_MUX IOMUX_PAD(0x6C4, 0x334, 4, 0x0, 0, 0) | ||
| 1174 | #define _MX53_PAD_GPIO_7__FIRI_RXD IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, 0) | ||
| 1175 | #define _MX53_PAD_GPIO_7__SPDIF_PLOCK IOMUX_PAD(0x6C4, 0x334, 6, 0x0, 0, 0) | ||
| 1176 | #define _MX53_PAD_GPIO_7__CCM_PLL2_BYP IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, 0) | ||
| 1177 | #define _MX53_PAD_GPIO_8__ESAI1_TX5_RX0 IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, 0) | ||
| 1178 | #define _MX53_PAD_GPIO_8__GPIO1_8 IOMUX_PAD(0x6C8, 0x338, 1, 0x0, 0, 0) | ||
| 1179 | #define _MX53_PAD_GPIO_8__EPIT2_EPITO IOMUX_PAD(0x6C8, 0x338, 2, 0x0, 0, 0) | ||
| 1180 | #define _MX53_PAD_GPIO_8__CAN1_RXCAN IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 3, 0) | ||
| 1181 | #define _MX53_PAD_GPIO_8__UART2_RXD_MUX IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, 0) | ||
| 1182 | #define _MX53_PAD_GPIO_8__FIRI_TXD IOMUX_PAD(0x6C8, 0x338, 5, 0x0, 0, 0) | ||
| 1183 | #define _MX53_PAD_GPIO_8__SPDIF_SRCLK IOMUX_PAD(0x6C8, 0x338, 6, 0x0, 0, 0) | ||
| 1184 | #define _MX53_PAD_GPIO_8__CCM_PLL3_BYP IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, 0) | ||
| 1185 | #define _MX53_PAD_GPIO_16__ESAI1_TX3_RX2 IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, 0) | ||
| 1186 | #define _MX53_PAD_GPIO_16__GPIO7_11 IOMUX_PAD(0x6CC, 0x33C, 1, 0x0, 0, 0) | ||
| 1187 | #define _MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT IOMUX_PAD(0x6CC, 0x33C, 2, 0x0, 0, 0) | ||
| 1188 | #define _MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 IOMUX_PAD(0x6CC, 0x33C, 4, 0x0, 0, 0) | ||
| 1189 | #define _MX53_PAD_GPIO_16__SPDIF_IN1 IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, 0) | ||
| 1190 | #define _MX53_PAD_GPIO_16__I2C3_SDA IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, 0) | ||
| 1191 | #define _MX53_PAD_GPIO_16__SJC_DE_B IOMUX_PAD(0x6CC, 0x33C, 7, 0x0, 0, 0) | ||
| 1192 | #define _MX53_PAD_GPIO_17__ESAI1_TX0 IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, 0) | ||
| 1193 | #define _MX53_PAD_GPIO_17__GPIO7_12 IOMUX_PAD(0x6D0, 0x340, 1, 0x0, 0, 0) | ||
| 1194 | #define _MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, 0) | ||
| 1195 | #define _MX53_PAD_GPIO_17__GPC_PMIC_RDY IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, 0) | ||
| 1196 | #define _MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG IOMUX_PAD(0x6D0, 0x340, 4, 0x0, 0, 0) | ||
| 1197 | #define _MX53_PAD_GPIO_17__SPDIF_OUT1 IOMUX_PAD(0x6D0, 0x340, 5, 0x0, 0, 0) | ||
| 1198 | #define _MX53_PAD_GPIO_17__IPU_SNOOP2 IOMUX_PAD(0x6D0, 0x340, 6, 0x0, 0, 0) | ||
| 1199 | #define _MX53_PAD_GPIO_17__SJC_JTAG_ACT IOMUX_PAD(0x6D0, 0x340, 7, 0x0, 0, 0) | ||
| 1200 | #define _MX53_PAD_GPIO_18__ESAI1_TX1 IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, 0) | ||
| 1201 | #define _MX53_PAD_GPIO_18__GPIO7_13 IOMUX_PAD(0x6D4, 0x344, 1, 0x0, 0, 0) | ||
| 1202 | #define _MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, 0) | ||
| 1203 | #define _MX53_PAD_GPIO_18__OWIRE_LINE IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, 0) | ||
| 1204 | #define _MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG IOMUX_PAD(0x6D4, 0x344, 4, 0x0, 0, 0) | ||
| 1205 | #define _MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, 0) | ||
| 1206 | #define _MX53_PAD_GPIO_18__ESDHC1_LCTL IOMUX_PAD(0x6D4, 0x344, 6, 0x0, 0, 0) | ||
| 1207 | #define _MX53_PAD_GPIO_18__SRC_SYSTEM_RST IOMUX_PAD(0x6D4, 0x344, 7, 0x0, 0, 0) | ||
| 1208 | 34 | ||
| 1209 | #define MX53_PAD_GPIO_19__KPP_COL_5 (_MX53_PAD_GPIO_19__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 35 | #define MX53_PAD_GPIO_19__KPP_COL_5 IOMUX_PAD(0x348, 0x020, 0, 0x840, 0, NO_PAD_CTRL) |
| 1210 | #define MX53_PAD_GPIO_19__GPIO4_5 (_MX53_PAD_GPIO_19__GPIO4_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 36 | #define MX53_PAD_GPIO_19__GPIO4_5 IOMUX_PAD(0x348, 0x020, 1, __NA_, 0, NO_PAD_CTRL) |
| 1211 | #define MX53_PAD_GPIO_19__CCM_CLKO (_MX53_PAD_GPIO_19__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 37 | #define MX53_PAD_GPIO_19__CCM_CLKO IOMUX_PAD(0x348, 0x020, 2, __NA_, 0, NO_PAD_CTRL) |
| 1212 | #define MX53_PAD_GPIO_19__SPDIF_OUT1 (_MX53_PAD_GPIO_19__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 38 | #define MX53_PAD_GPIO_19__SPDIF_OUT1 IOMUX_PAD(0x348, 0x020, 3, __NA_, 0, NO_PAD_CTRL) |
| 1213 | #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 (_MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 39 | #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 IOMUX_PAD(0x348, 0x020, 4, __NA_, 0, NO_PAD_CTRL) |
| 1214 | #define MX53_PAD_GPIO_19__ECSPI1_RDY (_MX53_PAD_GPIO_19__ECSPI1_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) | 40 | #define MX53_PAD_GPIO_19__ECSPI1_RDY IOMUX_PAD(0x348, 0x020, 5, __NA_, 0, NO_PAD_CTRL) |
| 1215 | #define MX53_PAD_GPIO_19__FEC_TDATA_3 (_MX53_PAD_GPIO_19__FEC_TDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 41 | #define MX53_PAD_GPIO_19__FEC_TDATA_3 IOMUX_PAD(0x348, 0x020, 6, __NA_, 0, NO_PAD_CTRL) |
| 1216 | #define MX53_PAD_GPIO_19__SRC_INT_BOOT (_MX53_PAD_GPIO_19__SRC_INT_BOOT | MUX_PAD_CTRL(NO_PAD_CTRL)) | 42 | #define MX53_PAD_GPIO_19__SRC_INT_BOOT IOMUX_PAD(0x348, 0x020, 7, __NA_, 0, NO_PAD_CTRL) |
| 1217 | #define MX53_PAD_KEY_COL0__KPP_COL_0 (_MX53_PAD_KEY_COL0__KPP_COL_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 43 | #define MX53_PAD_KEY_COL0__KPP_COL_0 IOMUX_PAD(0x34C, 0x024, 0, __NA_, 0, NO_PAD_CTRL) |
| 1218 | #define MX53_PAD_KEY_COL0__GPIO4_6 (_MX53_PAD_KEY_COL0__GPIO4_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 44 | #define MX53_PAD_KEY_COL0__GPIO4_6 IOMUX_PAD(0x34C, 0x024, 1, __NA_, 0, NO_PAD_CTRL) |
| 1219 | #define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC (_MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 45 | #define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC IOMUX_PAD(0x34C, 0x024, 2, 0x758, 0, NO_PAD_CTRL) |
| 1220 | #define MX53_PAD_KEY_COL0__UART4_TXD_MUX (_MX53_PAD_KEY_COL0__UART4_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 46 | #define MX53_PAD_KEY_COL0__UART4_TXD_MUX IOMUX_PAD(0x34C, 0x024, 4, __NA_, 0, MX53_UART_PAD_CTRL) |
| 1221 | #define MX53_PAD_KEY_COL0__ECSPI1_SCLK (_MX53_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 47 | #define MX53_PAD_KEY_COL0__ECSPI1_SCLK IOMUX_PAD(0x34C, 0x024, 5, 0x79C, 0, NO_PAD_CTRL) |
| 1222 | #define MX53_PAD_KEY_COL0__FEC_RDATA_3 (_MX53_PAD_KEY_COL0__FEC_RDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 48 | #define MX53_PAD_KEY_COL0__FEC_RDATA_3 IOMUX_PAD(0x34C, 0x024, 6, __NA_, 0, NO_PAD_CTRL) |
| 1223 | #define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST (_MX53_PAD_KEY_COL0__SRC_ANY_PU_RST | MUX_PAD_CTRL(NO_PAD_CTRL)) | 49 | #define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST IOMUX_PAD(0x34C, 0x024, 7, __NA_, 0, NO_PAD_CTRL) |
| 1224 | #define MX53_PAD_KEY_ROW0__KPP_ROW_0 (_MX53_PAD_KEY_ROW0__KPP_ROW_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 50 | #define MX53_PAD_KEY_ROW0__KPP_ROW_0 IOMUX_PAD(0x350, 0x028, 0, __NA_, 0, NO_PAD_CTRL) |
| 1225 | #define MX53_PAD_KEY_ROW0__GPIO4_7 (_MX53_PAD_KEY_ROW0__GPIO4_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 51 | #define MX53_PAD_KEY_ROW0__GPIO4_7 IOMUX_PAD(0x350, 0x028, 1, __NA_, 0, NO_PAD_CTRL) |
| 1226 | #define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD (_MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 52 | #define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD IOMUX_PAD(0x350, 0x028, 2, 0x74C, 0, NO_PAD_CTRL) |
| 1227 | #define MX53_PAD_KEY_ROW0__UART4_RXD_MUX (_MX53_PAD_KEY_ROW0__UART4_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 53 | #define MX53_PAD_KEY_ROW0__UART4_RXD_MUX IOMUX_PAD(0x350, 0x028, 4, 0x890, 1, MX53_UART_PAD_CTRL) |
| 1228 | #define MX53_PAD_KEY_ROW0__ECSPI1_MOSI (_MX53_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) | 54 | #define MX53_PAD_KEY_ROW0__ECSPI1_MOSI IOMUX_PAD(0x350, 0x028, 5, 0x7A4, 0, NO_PAD_CTRL) |
| 1229 | #define MX53_PAD_KEY_ROW0__FEC_TX_ER (_MX53_PAD_KEY_ROW0__FEC_TX_ER | MUX_PAD_CTRL(NO_PAD_CTRL)) | 55 | #define MX53_PAD_KEY_ROW0__FEC_TX_ER IOMUX_PAD(0x350, 0x028, 6, __NA_, 0, NO_PAD_CTRL) |
| 1230 | #define MX53_PAD_KEY_COL1__KPP_COL_1 (_MX53_PAD_KEY_COL1__KPP_COL_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 56 | #define MX53_PAD_KEY_COL1__KPP_COL_1 IOMUX_PAD(0x354, 0x02C, 0, __NA_, 0, NO_PAD_CTRL) |
| 1231 | #define MX53_PAD_KEY_COL1__GPIO4_8 (_MX53_PAD_KEY_COL1__GPIO4_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 57 | #define MX53_PAD_KEY_COL1__GPIO4_8 IOMUX_PAD(0x354, 0x02C, 1, __NA_, 0, NO_PAD_CTRL) |
| 1232 | #define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS (_MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 58 | #define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS IOMUX_PAD(0x354, 0x02C, 2, 0x75C, 0, NO_PAD_CTRL) |
| 1233 | #define MX53_PAD_KEY_COL1__UART5_TXD_MUX (_MX53_PAD_KEY_COL1__UART5_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 59 | #define MX53_PAD_KEY_COL1__UART5_TXD_MUX IOMUX_PAD(0x354, 0x02C, 4, __NA_, 0, MX53_UART_PAD_CTRL) |
| 1234 | #define MX53_PAD_KEY_COL1__ECSPI1_MISO (_MX53_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 60 | #define MX53_PAD_KEY_COL1__ECSPI1_MISO IOMUX_PAD(0x354, 0x02C, 5, 0x7A0, 0, NO_PAD_CTRL) |
| 1235 | #define MX53_PAD_KEY_COL1__FEC_RX_CLK (_MX53_PAD_KEY_COL1__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 61 | #define MX53_PAD_KEY_COL1__FEC_RX_CLK IOMUX_PAD(0x354, 0x02C, 6, 0x808, 0, NO_PAD_CTRL) |
| 1236 | #define MX53_PAD_KEY_COL1__USBPHY1_TXREADY (_MX53_PAD_KEY_COL1__USBPHY1_TXREADY | MUX_PAD_CTRL(NO_PAD_CTRL)) | 62 | #define MX53_PAD_KEY_COL1__USBPHY1_TXREADY IOMUX_PAD(0x354, 0x02C, 7, __NA_, 0, NO_PAD_CTRL) |
| 1237 | #define MX53_PAD_KEY_ROW1__KPP_ROW_1 (_MX53_PAD_KEY_ROW1__KPP_ROW_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 63 | #define MX53_PAD_KEY_ROW1__KPP_ROW_1 IOMUX_PAD(0x358, 0x030, 0, __NA_, 0, NO_PAD_CTRL) |
| 1238 | #define MX53_PAD_KEY_ROW1__GPIO4_9 (_MX53_PAD_KEY_ROW1__GPIO4_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 64 | #define MX53_PAD_KEY_ROW1__GPIO4_9 IOMUX_PAD(0x358, 0x030, 1, __NA_, 0, NO_PAD_CTRL) |
| 1239 | #define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD (_MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 65 | #define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD IOMUX_PAD(0x358, 0x030, 2, 0x748, 0, NO_PAD_CTRL) |
| 1240 | #define MX53_PAD_KEY_ROW1__UART5_RXD_MUX (_MX53_PAD_KEY_ROW1__UART5_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 66 | #define MX53_PAD_KEY_ROW1__UART5_RXD_MUX IOMUX_PAD(0x358, 0x030, 4, 0x898, 1, MX53_UART_PAD_CTRL) |
| 1241 | #define MX53_PAD_KEY_ROW1__ECSPI1_SS0 (_MX53_PAD_KEY_ROW1__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 67 | #define MX53_PAD_KEY_ROW1__ECSPI1_SS0 IOMUX_PAD(0x358, 0x030, 5, 0x7A8, 0, NO_PAD_CTRL) |
| 1242 | #define MX53_PAD_KEY_ROW1__FEC_COL (_MX53_PAD_KEY_ROW1__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL)) | 68 | #define MX53_PAD_KEY_ROW1__FEC_COL IOMUX_PAD(0x358, 0x030, 6, 0x800, 0, NO_PAD_CTRL) |
| 1243 | #define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID (_MX53_PAD_KEY_ROW1__USBPHY1_RXVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) | 69 | #define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID IOMUX_PAD(0x358, 0x030, 7, __NA_, 0, NO_PAD_CTRL) |
| 1244 | #define MX53_PAD_KEY_COL2__KPP_COL_2 (_MX53_PAD_KEY_COL2__KPP_COL_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 70 | #define MX53_PAD_KEY_COL2__KPP_COL_2 IOMUX_PAD(0x35C, 0x034, 0, __NA_, 0, NO_PAD_CTRL) |
| 1245 | #define MX53_PAD_KEY_COL2__GPIO4_10 (_MX53_PAD_KEY_COL2__GPIO4_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 71 | #define MX53_PAD_KEY_COL2__GPIO4_10 IOMUX_PAD(0x35C, 0x034, 1, __NA_, 0, NO_PAD_CTRL) |
| 1246 | #define MX53_PAD_KEY_COL2__CAN1_TXCAN (_MX53_PAD_KEY_COL2__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) | 72 | #define MX53_PAD_KEY_COL2__CAN1_TXCAN IOMUX_PAD(0x35C, 0x034, 2, __NA_, 0, NO_PAD_CTRL) |
| 1247 | #define MX53_PAD_KEY_COL2__FEC_MDIO (_MX53_PAD_KEY_COL2__FEC_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 73 | #define MX53_PAD_KEY_COL2__FEC_MDIO IOMUX_PAD(0x35C, 0x034, 4, 0x804, 0, NO_PAD_CTRL) |
| 1248 | #define MX53_PAD_KEY_COL2__ECSPI1_SS1 (_MX53_PAD_KEY_COL2__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 74 | #define MX53_PAD_KEY_COL2__ECSPI1_SS1 IOMUX_PAD(0x35C, 0x034, 5, 0x7AC, 0, NO_PAD_CTRL) |
| 1249 | #define MX53_PAD_KEY_COL2__FEC_RDATA_2 (_MX53_PAD_KEY_COL2__FEC_RDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 75 | #define MX53_PAD_KEY_COL2__FEC_RDATA_2 IOMUX_PAD(0x35C, 0x034, 6, __NA_, 0, NO_PAD_CTRL) |
| 1250 | #define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE (_MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE | MUX_PAD_CTRL(NO_PAD_CTRL)) | 76 | #define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE IOMUX_PAD(0x35C, 0x034, 7, __NA_, 0, NO_PAD_CTRL) |
| 1251 | #define MX53_PAD_KEY_ROW2__KPP_ROW_2 (_MX53_PAD_KEY_ROW2__KPP_ROW_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 77 | #define MX53_PAD_KEY_ROW2__KPP_ROW_2 IOMUX_PAD(0x360, 0x038, 0, __NA_, 0, NO_PAD_CTRL) |
| 1252 | #define MX53_PAD_KEY_ROW2__GPIO4_11 (_MX53_PAD_KEY_ROW2__GPIO4_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 78 | #define MX53_PAD_KEY_ROW2__GPIO4_11 IOMUX_PAD(0x360, 0x038, 1, __NA_, 0, NO_PAD_CTRL) |
| 1253 | #define MX53_PAD_KEY_ROW2__CAN1_RXCAN (_MX53_PAD_KEY_ROW2__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) | 79 | #define MX53_PAD_KEY_ROW2__CAN1_RXCAN IOMUX_PAD(0x360, 0x038, 2, 0x760, 0, NO_PAD_CTRL) |
| 1254 | #define MX53_PAD_KEY_ROW2__FEC_MDC (_MX53_PAD_KEY_ROW2__FEC_MDC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 80 | #define MX53_PAD_KEY_ROW2__FEC_MDC IOMUX_PAD(0x360, 0x038, 4, __NA_, 0, NO_PAD_CTRL) |
| 1255 | #define MX53_PAD_KEY_ROW2__ECSPI1_SS2 (_MX53_PAD_KEY_ROW2__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 81 | #define MX53_PAD_KEY_ROW2__ECSPI1_SS2 IOMUX_PAD(0x360, 0x038, 5, 0x7B0, 0, NO_PAD_CTRL) |
| 1256 | #define MX53_PAD_KEY_ROW2__FEC_TDATA_2 (_MX53_PAD_KEY_ROW2__FEC_TDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 82 | #define MX53_PAD_KEY_ROW2__FEC_TDATA_2 IOMUX_PAD(0x360, 0x038, 6, __NA_, 0, NO_PAD_CTRL) |
| 1257 | #define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR (_MX53_PAD_KEY_ROW2__USBPHY1_RXERROR | MUX_PAD_CTRL(NO_PAD_CTRL)) | 83 | #define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR IOMUX_PAD(0x360, 0x038, 7, __NA_, 0, NO_PAD_CTRL) |
| 1258 | #define MX53_PAD_KEY_COL3__KPP_COL_3 (_MX53_PAD_KEY_COL3__KPP_COL_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 84 | #define MX53_PAD_KEY_COL3__KPP_COL_3 IOMUX_PAD(0x364, 0x03C, 0, __NA_, 0, NO_PAD_CTRL) |
| 1259 | #define MX53_PAD_KEY_COL3__GPIO4_12 (_MX53_PAD_KEY_COL3__GPIO4_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 85 | #define MX53_PAD_KEY_COL3__GPIO4_12 IOMUX_PAD(0x364, 0x03C, 1, __NA_, 0, NO_PAD_CTRL) |
| 1260 | #define MX53_PAD_KEY_COL3__USBOH3_H2_DP (_MX53_PAD_KEY_COL3__USBOH3_H2_DP | MUX_PAD_CTRL(NO_PAD_CTRL)) | 86 | #define MX53_PAD_KEY_COL3__USBOH3_H2_DP IOMUX_PAD(0x364, 0x03C, 2, __NA_, 0, NO_PAD_CTRL) |
| 1261 | #define MX53_PAD_KEY_COL3__SPDIF_IN1 (_MX53_PAD_KEY_COL3__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 87 | #define MX53_PAD_KEY_COL3__SPDIF_IN1 IOMUX_PAD(0x364, 0x03C, 3, 0x870, 0, NO_PAD_CTRL) |
| 1262 | #define MX53_PAD_KEY_COL3__I2C2_SCL (_MX53_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C)) | 88 | #define MX53_PAD_KEY_COL3__I2C2_SCL IOMUX_PAD(0x364, 0x03C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, NO_PAD_CTRL) |
| 1263 | #define MX53_PAD_KEY_COL3__ECSPI1_SS3 (_MX53_PAD_KEY_COL3__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 89 | #define MX53_PAD_KEY_COL3__ECSPI1_SS3 IOMUX_PAD(0x364, 0x03C, 5, 0x7B4, 0, NO_PAD_CTRL) |
| 1264 | #define MX53_PAD_KEY_COL3__FEC_CRS (_MX53_PAD_KEY_COL3__FEC_CRS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 90 | #define MX53_PAD_KEY_COL3__FEC_CRS IOMUX_PAD(0x364, 0x03C, 6, __NA_, 0, NO_PAD_CTRL) |
| 1265 | #define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK (_MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 91 | #define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK IOMUX_PAD(0x364, 0x03C, 7, __NA_, 0, NO_PAD_CTRL) |
| 1266 | #define MX53_PAD_KEY_ROW3__KPP_ROW_3 (_MX53_PAD_KEY_ROW3__KPP_ROW_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 92 | #define MX53_PAD_KEY_ROW3__KPP_ROW_3 IOMUX_PAD(0x368, 0x040, 0, __NA_, 0, NO_PAD_CTRL) |
| 1267 | #define MX53_PAD_KEY_ROW3__GPIO4_13 (_MX53_PAD_KEY_ROW3__GPIO4_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 93 | #define MX53_PAD_KEY_ROW3__GPIO4_13 IOMUX_PAD(0x368, 0x040, 1, __NA_, 0, NO_PAD_CTRL) |
| 1268 | #define MX53_PAD_KEY_ROW3__USBOH3_H2_DM (_MX53_PAD_KEY_ROW3__USBOH3_H2_DM | MUX_PAD_CTRL(NO_PAD_CTRL)) | 94 | #define MX53_PAD_KEY_ROW3__USBOH3_H2_DM IOMUX_PAD(0x368, 0x040, 2, __NA_, 0, NO_PAD_CTRL) |
| 1269 | #define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK (_MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 95 | #define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK IOMUX_PAD(0x368, 0x040, 3, 0x768, 0, NO_PAD_CTRL) |
| 1270 | #define MX53_PAD_KEY_ROW3__I2C2_SDA (_MX53_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C)) | 96 | #define MX53_PAD_KEY_ROW3__I2C2_SDA IOMUX_PAD(0x368, 0x040, 4 | IOMUX_CONFIG_SION, 0x820, 0, NO_PAD_CTRL) |
| 1271 | #define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT (_MX53_PAD_KEY_ROW3__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) | 97 | #define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT IOMUX_PAD(0x368, 0x040, 5, __NA_, 0, NO_PAD_CTRL) |
| 1272 | #define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP (_MX53_PAD_KEY_ROW3__CCM_PLL4_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) | 98 | #define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP IOMUX_PAD(0x368, 0x040, 6, 0x77C, 0, NO_PAD_CTRL) |
| 1273 | #define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 (_MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 99 | #define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 IOMUX_PAD(0x368, 0x040, 7, __NA_, 0, NO_PAD_CTRL) |
| 1274 | #define MX53_PAD_KEY_COL4__KPP_COL_4 (_MX53_PAD_KEY_COL4__KPP_COL_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 100 | #define MX53_PAD_KEY_COL4__KPP_COL_4 IOMUX_PAD(0x36C, 0x044, 0, __NA_, 0, NO_PAD_CTRL) |
| 1275 | #define MX53_PAD_KEY_COL4__GPIO4_14 (_MX53_PAD_KEY_COL4__GPIO4_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 101 | #define MX53_PAD_KEY_COL4__GPIO4_14 IOMUX_PAD(0x36C, 0x044, 1, __NA_, 0, NO_PAD_CTRL) |
| 1276 | #define MX53_PAD_KEY_COL4__CAN2_TXCAN (_MX53_PAD_KEY_COL4__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) | 102 | #define MX53_PAD_KEY_COL4__CAN2_TXCAN IOMUX_PAD(0x36C, 0x044, 2, __NA_, 0, NO_PAD_CTRL) |
| 1277 | #define MX53_PAD_KEY_COL4__IPU_SISG_4 (_MX53_PAD_KEY_COL4__IPU_SISG_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 103 | #define MX53_PAD_KEY_COL4__IPU_SISG_4 IOMUX_PAD(0x36C, 0x044, 3, __NA_, 0, NO_PAD_CTRL) |
| 1278 | #define MX53_PAD_KEY_COL4__UART5_RTS (_MX53_PAD_KEY_COL4__UART5_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 104 | #define MX53_PAD_KEY_COL4__UART5_RTS IOMUX_PAD(0x36C, 0x044, 4, 0x894, 0, MX53_UART_PAD_CTRL) |
| 1279 | #define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC (_MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 105 | #define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC IOMUX_PAD(0x36C, 0x044, 5, 0x89C, 0, NO_PAD_CTRL) |
| 1280 | #define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 (_MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 106 | #define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 IOMUX_PAD(0x36C, 0x044, 7, __NA_, 0, NO_PAD_CTRL) |
| 1281 | #define MX53_PAD_KEY_ROW4__KPP_ROW_4 (_MX53_PAD_KEY_ROW4__KPP_ROW_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 107 | #define MX53_PAD_KEY_ROW4__KPP_ROW_4 IOMUX_PAD(0x370, 0x048, 0, __NA_, 0, NO_PAD_CTRL) |
| 1282 | #define MX53_PAD_KEY_ROW4__GPIO4_15 (_MX53_PAD_KEY_ROW4__GPIO4_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 108 | #define MX53_PAD_KEY_ROW4__GPIO4_15 IOMUX_PAD(0x370, 0x048, 1, __NA_, 0, NO_PAD_CTRL) |
| 1283 | #define MX53_PAD_KEY_ROW4__CAN2_RXCAN (_MX53_PAD_KEY_ROW4__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) | 109 | #define MX53_PAD_KEY_ROW4__CAN2_RXCAN IOMUX_PAD(0x370, 0x048, 2, 0x764, 0, NO_PAD_CTRL) |
| 1284 | #define MX53_PAD_KEY_ROW4__IPU_SISG_5 (_MX53_PAD_KEY_ROW4__IPU_SISG_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 110 | #define MX53_PAD_KEY_ROW4__IPU_SISG_5 IOMUX_PAD(0x370, 0x048, 3, __NA_, 0, NO_PAD_CTRL) |
| 1285 | #define MX53_PAD_KEY_ROW4__UART5_CTS (_MX53_PAD_KEY_ROW4__UART5_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 111 | #define MX53_PAD_KEY_ROW4__UART5_CTS IOMUX_PAD(0x370, 0x048, 4, __NA_, 0, MX53_UART_PAD_CTRL) |
| 1286 | #define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR (_MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) | 112 | #define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR IOMUX_PAD(0x370, 0x048, 5, __NA_, 0, NO_PAD_CTRL) |
| 1287 | #define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID (_MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) | 113 | #define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID IOMUX_PAD(0x370, 0x048, 7, __NA_, 0, NO_PAD_CTRL) |
| 1288 | #define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK (_MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 114 | #define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK IOMUX_PAD(0x378, 0x04C, 0, __NA_, 0, NO_PAD_CTRL) |
| 1289 | #define MX53_PAD_DI0_DISP_CLK__GPIO4_16 (_MX53_PAD_DI0_DISP_CLK__GPIO4_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 115 | #define MX53_PAD_DI0_DISP_CLK__GPIO4_16 IOMUX_PAD(0x378, 0x04C, 1, __NA_, 0, NO_PAD_CTRL) |
| 1290 | #define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR (_MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) | 116 | #define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR IOMUX_PAD(0x378, 0x04C, 2, __NA_, 0, NO_PAD_CTRL) |
| 1291 | #define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 (_MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 117 | #define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 IOMUX_PAD(0x378, 0x04C, 5, __NA_, 0, NO_PAD_CTRL) |
| 1292 | #define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 (_MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 118 | #define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 IOMUX_PAD(0x378, 0x04C, 6, __NA_, 0, NO_PAD_CTRL) |
| 1293 | #define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID (_MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) | 119 | #define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID IOMUX_PAD(0x378, 0x04C, 7, __NA_, 0, NO_PAD_CTRL) |
| 1294 | #define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 (_MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 120 | #define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 IOMUX_PAD(0x37C, 0x050, 0, __NA_, 0, NO_PAD_CTRL) |
| 1295 | #define MX53_PAD_DI0_PIN15__GPIO4_17 (_MX53_PAD_DI0_PIN15__GPIO4_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 121 | #define MX53_PAD_DI0_PIN15__GPIO4_17 IOMUX_PAD(0x37C, 0x050, 1, __NA_, 0, NO_PAD_CTRL) |
| 1296 | #define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC (_MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 122 | #define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC IOMUX_PAD(0x37C, 0x050, 2, __NA_, 0, NO_PAD_CTRL) |
| 1297 | #define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 (_MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 123 | #define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 IOMUX_PAD(0x37C, 0x050, 5, __NA_, 0, NO_PAD_CTRL) |
| 1298 | #define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 (_MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 124 | #define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 IOMUX_PAD(0x37C, 0x050, 6, __NA_, 0, NO_PAD_CTRL) |
| 1299 | #define MX53_PAD_DI0_PIN15__USBPHY1_BVALID (_MX53_PAD_DI0_PIN15__USBPHY1_BVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) | 125 | #define MX53_PAD_DI0_PIN15__USBPHY1_BVALID IOMUX_PAD(0x37C, 0x050, 7, __NA_, 0, NO_PAD_CTRL) |
| 1300 | #define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 (_MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 126 | #define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 IOMUX_PAD(0x380, 0x054, 0, __NA_, 0, NO_PAD_CTRL) |
| 1301 | #define MX53_PAD_DI0_PIN2__GPIO4_18 (_MX53_PAD_DI0_PIN2__GPIO4_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 127 | #define MX53_PAD_DI0_PIN2__GPIO4_18 IOMUX_PAD(0x380, 0x054, 1, __NA_, 0, NO_PAD_CTRL) |
| 1302 | #define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD (_MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 128 | #define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD IOMUX_PAD(0x380, 0x054, 2, __NA_, 0, NO_PAD_CTRL) |
| 1303 | #define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 (_MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 129 | #define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 IOMUX_PAD(0x380, 0x054, 5, __NA_, 0, NO_PAD_CTRL) |
| 1304 | #define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 (_MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 130 | #define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 IOMUX_PAD(0x380, 0x054, 6, __NA_, 0, NO_PAD_CTRL) |
| 1305 | #define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION (_MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION | MUX_PAD_CTRL(NO_PAD_CTRL)) | 131 | #define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION IOMUX_PAD(0x380, 0x054, 7, __NA_, 0, NO_PAD_CTRL) |
| 1306 | #define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 (_MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 132 | #define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 IOMUX_PAD(0x384, 0x058, 0, __NA_, 0, NO_PAD_CTRL) |
| 1307 | #define MX53_PAD_DI0_PIN3__GPIO4_19 (_MX53_PAD_DI0_PIN3__GPIO4_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 133 | #define MX53_PAD_DI0_PIN3__GPIO4_19 IOMUX_PAD(0x384, 0x058, 1, __NA_, 0, NO_PAD_CTRL) |
| 1308 | #define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS (_MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 134 | #define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS IOMUX_PAD(0x384, 0x058, 2, __NA_, 0, NO_PAD_CTRL) |
| 1309 | #define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 (_MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 135 | #define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 IOMUX_PAD(0x384, 0x058, 5, __NA_, 0, NO_PAD_CTRL) |
| 1310 | #define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 (_MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 136 | #define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 IOMUX_PAD(0x384, 0x058, 6, __NA_, 0, NO_PAD_CTRL) |
| 1311 | #define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG (_MX53_PAD_DI0_PIN3__USBPHY1_IDDIG | MUX_PAD_CTRL(NO_PAD_CTRL)) | 137 | #define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG IOMUX_PAD(0x384, 0x058, 7, __NA_, 0, NO_PAD_CTRL) |
| 1312 | #define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 (_MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 138 | #define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 IOMUX_PAD(0x388, 0x05C, 0, __NA_, 0, NO_PAD_CTRL) |
| 1313 | #define MX53_PAD_DI0_PIN4__GPIO4_20 (_MX53_PAD_DI0_PIN4__GPIO4_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 139 | #define MX53_PAD_DI0_PIN4__GPIO4_20 IOMUX_PAD(0x388, 0x05C, 1, __NA_, 0, NO_PAD_CTRL) |
| 1314 | #define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD (_MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 140 | #define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD IOMUX_PAD(0x388, 0x05C, 2, __NA_, 0, NO_PAD_CTRL) |
| 1315 | #define MX53_PAD_DI0_PIN4__ESDHC1_WP (_MX53_PAD_DI0_PIN4__ESDHC1_WP | MUX_PAD_CTRL(NO_PAD_CTRL)) | 141 | #define MX53_PAD_DI0_PIN4__ESDHC1_WP IOMUX_PAD(0x388, 0x05C, 3, 0x7FC, 0, NO_PAD_CTRL) |
| 1316 | #define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD (_MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 142 | #define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD IOMUX_PAD(0x388, 0x05C, 5, __NA_, 0, NO_PAD_CTRL) |
| 1317 | #define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 (_MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 143 | #define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 IOMUX_PAD(0x388, 0x05C, 6, __NA_, 0, NO_PAD_CTRL) |
| 1318 | #define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT (_MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT | MUX_PAD_CTRL(NO_PAD_CTRL)) | 144 | #define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT IOMUX_PAD(0x388, 0x05C, 7, __NA_, 0, NO_PAD_CTRL) |
| 1319 | #define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 (_MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 145 | #define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 IOMUX_PAD(0x38C, 0x060, 0, __NA_, 0, NO_PAD_CTRL) |
| 1320 | #define MX53_PAD_DISP0_DAT0__GPIO4_21 (_MX53_PAD_DISP0_DAT0__GPIO4_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 146 | #define MX53_PAD_DISP0_DAT0__GPIO4_21 IOMUX_PAD(0x38C, 0x060, 1, __NA_, 0, NO_PAD_CTRL) |
| 1321 | #define MX53_PAD_DISP0_DAT0__CSPI_SCLK (_MX53_PAD_DISP0_DAT0__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 147 | #define MX53_PAD_DISP0_DAT0__CSPI_SCLK IOMUX_PAD(0x38C, 0x060, 2, 0x780, 0, NO_PAD_CTRL) |
| 1322 | #define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 (_MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 148 | #define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 IOMUX_PAD(0x38C, 0x060, 3, __NA_, 0, NO_PAD_CTRL) |
| 1323 | #define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN (_MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN | MUX_PAD_CTRL(NO_PAD_CTRL)) | 149 | #define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN IOMUX_PAD(0x38C, 0x060, 5, __NA_, 0, NO_PAD_CTRL) |
| 1324 | #define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 (_MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 150 | #define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 IOMUX_PAD(0x38C, 0x060, 6, __NA_, 0, NO_PAD_CTRL) |
| 1325 | #define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY (_MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY | MUX_PAD_CTRL(NO_PAD_CTRL)) | 151 | #define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY IOMUX_PAD(0x38C, 0x060, 7, __NA_, 0, NO_PAD_CTRL) |
| 1326 | #define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 (_MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 152 | #define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 IOMUX_PAD(0x390, 0x064, 0, __NA_, 0, NO_PAD_CTRL) |
| 1327 | #define MX53_PAD_DISP0_DAT1__GPIO4_22 (_MX53_PAD_DISP0_DAT1__GPIO4_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 153 | #define MX53_PAD_DISP0_DAT1__GPIO4_22 IOMUX_PAD(0x390, 0x064, 1, __NA_, 0, NO_PAD_CTRL) |
| 1328 | #define MX53_PAD_DISP0_DAT1__CSPI_MOSI (_MX53_PAD_DISP0_DAT1__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) | 154 | #define MX53_PAD_DISP0_DAT1__CSPI_MOSI IOMUX_PAD(0x390, 0x064, 2, 0x788, 0, NO_PAD_CTRL) |
| 1329 | #define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 (_MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 155 | #define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 IOMUX_PAD(0x390, 0x064, 3, __NA_, 0, NO_PAD_CTRL) |
| 1330 | #define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL (_MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL | MUX_PAD_CTRL(NO_PAD_CTRL)) | 156 | #define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL \ |
| 1331 | #define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 (_MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 157 | IOMUX_PAD(0x390, 0x064, 5, __NA_, 0, NO_PAD_CTRL) |
| 1332 | #define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID (_MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) | 158 | #define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 IOMUX_PAD(0x390, 0x064, 6, __NA_, 0, NO_PAD_CTRL) |
| 1333 | #define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 (_MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 159 | #define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID IOMUX_PAD(0x390, 0x064, 7, __NA_, 0, NO_PAD_CTRL) |
| 1334 | #define MX53_PAD_DISP0_DAT2__GPIO4_23 (_MX53_PAD_DISP0_DAT2__GPIO4_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 160 | #define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 IOMUX_PAD(0x394, 0x068, 0, __NA_, 0, NO_PAD_CTRL) |
| 1335 | #define MX53_PAD_DISP0_DAT2__CSPI_MISO (_MX53_PAD_DISP0_DAT2__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 161 | #define MX53_PAD_DISP0_DAT2__GPIO4_23 IOMUX_PAD(0x394, 0x068, 1, __NA_, 0, NO_PAD_CTRL) |
| 1336 | #define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 (_MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 162 | #define MX53_PAD_DISP0_DAT2__CSPI_MISO IOMUX_PAD(0x394, 0x068, 2, 0x784, 0, NO_PAD_CTRL) |
| 1337 | #define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE (_MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE | MUX_PAD_CTRL(NO_PAD_CTRL)) | 163 | #define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 IOMUX_PAD(0x394, 0x068, 3, __NA_, 0, NO_PAD_CTRL) |
| 1338 | #define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 (_MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 164 | #define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE IOMUX_PAD(0x394, 0x068, 5, __NA_, 0, NO_PAD_CTRL) |
| 1339 | #define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE (_MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE | MUX_PAD_CTRL(NO_PAD_CTRL)) | 165 | #define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 IOMUX_PAD(0x394, 0x068, 6, __NA_, 0, NO_PAD_CTRL) |
| 1340 | #define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 (_MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 166 | #define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE IOMUX_PAD(0x394, 0x068, 7, __NA_, 0, NO_PAD_CTRL) |
| 1341 | #define MX53_PAD_DISP0_DAT3__GPIO4_24 (_MX53_PAD_DISP0_DAT3__GPIO4_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 167 | #define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 IOMUX_PAD(0x398, 0x06C, 0, __NA_, 0, NO_PAD_CTRL) |
| 1342 | #define MX53_PAD_DISP0_DAT3__CSPI_SS0 (_MX53_PAD_DISP0_DAT3__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 168 | #define MX53_PAD_DISP0_DAT3__GPIO4_24 IOMUX_PAD(0x398, 0x06C, 1, __NA_, 0, NO_PAD_CTRL) |
| 1343 | #define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 (_MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 169 | #define MX53_PAD_DISP0_DAT3__CSPI_SS0 IOMUX_PAD(0x398, 0x06C, 2, 0x78C, 0, NO_PAD_CTRL) |
| 1344 | #define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR (_MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR | MUX_PAD_CTRL(NO_PAD_CTRL)) | 170 | #define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 IOMUX_PAD(0x398, 0x06C, 3, __NA_, 0, NO_PAD_CTRL) |
| 1345 | #define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 (_MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 171 | #define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR IOMUX_PAD(0x398, 0x06C, 5, __NA_, 0, NO_PAD_CTRL) |
| 1346 | #define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR (_MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR | MUX_PAD_CTRL(NO_PAD_CTRL)) | 172 | #define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 IOMUX_PAD(0x398, 0x06C, 6, __NA_, 0, NO_PAD_CTRL) |
| 1347 | #define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 (_MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 173 | #define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR IOMUX_PAD(0x398, 0x06C, 7, __NA_, 0, NO_PAD_CTRL) |
| 1348 | #define MX53_PAD_DISP0_DAT4__GPIO4_25 (_MX53_PAD_DISP0_DAT4__GPIO4_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 174 | #define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 IOMUX_PAD(0x39C, 0x070, 0, __NA_, 0, NO_PAD_CTRL) |
| 1349 | #define MX53_PAD_DISP0_DAT4__CSPI_SS1 (_MX53_PAD_DISP0_DAT4__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 175 | #define MX53_PAD_DISP0_DAT4__GPIO4_25 IOMUX_PAD(0x39C, 0x070, 1, __NA_, 0, NO_PAD_CTRL) |
| 1350 | #define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 (_MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 176 | #define MX53_PAD_DISP0_DAT4__CSPI_SS1 IOMUX_PAD(0x39C, 0x070, 2, 0x790, 0, NO_PAD_CTRL) |
| 1351 | #define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB (_MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB | MUX_PAD_CTRL(NO_PAD_CTRL)) | 177 | #define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 IOMUX_PAD(0x39C, 0x070, 3, __NA_, 0, NO_PAD_CTRL) |
| 1352 | #define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 (_MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 178 | #define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB IOMUX_PAD(0x39C, 0x070, 5, __NA_, 0, NO_PAD_CTRL) |
| 1353 | #define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK (_MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 179 | #define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 IOMUX_PAD(0x39C, 0x070, 6, __NA_, 0, NO_PAD_CTRL) |
| 1354 | #define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 (_MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 180 | #define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK IOMUX_PAD(0x39C, 0x070, 7, __NA_, 0, NO_PAD_CTRL) |
| 1355 | #define MX53_PAD_DISP0_DAT5__GPIO4_26 (_MX53_PAD_DISP0_DAT5__GPIO4_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 181 | #define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 IOMUX_PAD(0x3A0, 0x074, 0, __NA_, 0, NO_PAD_CTRL) |
| 1356 | #define MX53_PAD_DISP0_DAT5__CSPI_SS2 (_MX53_PAD_DISP0_DAT5__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 182 | #define MX53_PAD_DISP0_DAT5__GPIO4_26 IOMUX_PAD(0x3A0, 0x074, 1, __NA_, 0, NO_PAD_CTRL) |
| 1357 | #define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 (_MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 183 | #define MX53_PAD_DISP0_DAT5__CSPI_SS2 IOMUX_PAD(0x3A0, 0x074, 2, 0x794, 0, NO_PAD_CTRL) |
| 1358 | #define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS (_MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 184 | #define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 IOMUX_PAD(0x3A0, 0x074, 3, __NA_, 0, NO_PAD_CTRL) |
| 1359 | #define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 (_MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 185 | #define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS IOMUX_PAD(0x3A0, 0x074, 5, __NA_, 0, NO_PAD_CTRL) |
| 1360 | #define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 (_MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 186 | #define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 IOMUX_PAD(0x3A0, 0x074, 6, __NA_, 0, NO_PAD_CTRL) |
| 1361 | #define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 (_MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 187 | #define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 IOMUX_PAD(0x3A0, 0x074, 7, __NA_, 0, NO_PAD_CTRL) |
| 1362 | #define MX53_PAD_DISP0_DAT6__GPIO4_27 (_MX53_PAD_DISP0_DAT6__GPIO4_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 188 | #define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 IOMUX_PAD(0x3A4, 0x078, 0, __NA_, 0, NO_PAD_CTRL) |
| 1363 | #define MX53_PAD_DISP0_DAT6__CSPI_SS3 (_MX53_PAD_DISP0_DAT6__CSPI_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 189 | #define MX53_PAD_DISP0_DAT6__GPIO4_27 IOMUX_PAD(0x3A4, 0x078, 1, __NA_, 0, NO_PAD_CTRL) |
| 1364 | #define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 (_MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 190 | #define MX53_PAD_DISP0_DAT6__CSPI_SS3 IOMUX_PAD(0x3A4, 0x078, 2, 0x798, 0, NO_PAD_CTRL) |
| 1365 | #define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE (_MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE | MUX_PAD_CTRL(NO_PAD_CTRL)) | 191 | #define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 IOMUX_PAD(0x3A4, 0x078, 3, __NA_, 0, NO_PAD_CTRL) |
| 1366 | #define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 (_MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 192 | #define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x3A4, 0x078, 5, __NA_, 0, NO_PAD_CTRL) |
| 1367 | #define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 (_MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 193 | #define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 IOMUX_PAD(0x3A4, 0x078, 6, __NA_, 0, NO_PAD_CTRL) |
| 1368 | #define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 (_MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 194 | #define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 IOMUX_PAD(0x3A4, 0x078, 7, __NA_, 0, NO_PAD_CTRL) |
| 1369 | #define MX53_PAD_DISP0_DAT7__GPIO4_28 (_MX53_PAD_DISP0_DAT7__GPIO4_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 195 | #define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 IOMUX_PAD(0x3A8, 0x07C, 0, __NA_, 0, NO_PAD_CTRL) |
| 1370 | #define MX53_PAD_DISP0_DAT7__CSPI_RDY (_MX53_PAD_DISP0_DAT7__CSPI_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) | 196 | #define MX53_PAD_DISP0_DAT7__GPIO4_28 IOMUX_PAD(0x3A8, 0x07C, 1, __NA_, 0, NO_PAD_CTRL) |
| 1371 | #define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 (_MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 197 | #define MX53_PAD_DISP0_DAT7__CSPI_RDY IOMUX_PAD(0x3A8, 0x07C, 2, __NA_, 0, NO_PAD_CTRL) |
| 1372 | #define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 (_MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 198 | #define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 IOMUX_PAD(0x3A8, 0x07C, 3, __NA_, 0, NO_PAD_CTRL) |
| 1373 | #define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 (_MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 199 | #define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x3A8, 0x07C, 5, __NA_, 0, NO_PAD_CTRL) |
| 1374 | #define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID (_MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) | 200 | #define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 IOMUX_PAD(0x3A8, 0x07C, 6, __NA_, 0, NO_PAD_CTRL) |
| 1375 | #define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 (_MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 201 | #define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID IOMUX_PAD(0x3A8, 0x07C, 7, __NA_, 0, NO_PAD_CTRL) |
| 1376 | #define MX53_PAD_DISP0_DAT8__GPIO4_29 (_MX53_PAD_DISP0_DAT8__GPIO4_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 202 | #define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 IOMUX_PAD(0x3AC, 0x080, 0, __NA_, 0, NO_PAD_CTRL) |
| 1377 | #define MX53_PAD_DISP0_DAT8__PWM1_PWMO (_MX53_PAD_DISP0_DAT8__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 203 | #define MX53_PAD_DISP0_DAT8__GPIO4_29 IOMUX_PAD(0x3AC, 0x080, 1, __NA_, 0, NO_PAD_CTRL) |
| 1378 | #define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B (_MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) | 204 | #define MX53_PAD_DISP0_DAT8__PWM1_PWMO IOMUX_PAD(0x3AC, 0x080, 2, __NA_, 0, NO_PAD_CTRL) |
| 1379 | #define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 (_MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 205 | #define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B IOMUX_PAD(0x3AC, 0x080, 3, __NA_, 0, NO_PAD_CTRL) |
| 1380 | #define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 (_MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 206 | #define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x3AC, 0x080, 5, __NA_, 0, NO_PAD_CTRL) |
| 1381 | #define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID (_MX53_PAD_DISP0_DAT8__USBPHY2_AVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) | 207 | #define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 IOMUX_PAD(0x3AC, 0x080, 6, __NA_, 0, NO_PAD_CTRL) |
| 1382 | #define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 (_MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 208 | #define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID IOMUX_PAD(0x3AC, 0x080, 7, __NA_, 0, NO_PAD_CTRL) |
| 1383 | #define MX53_PAD_DISP0_DAT9__GPIO4_30 (_MX53_PAD_DISP0_DAT9__GPIO4_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 209 | #define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 IOMUX_PAD(0x3B0, 0x084, 0, __NA_, 0, NO_PAD_CTRL) |
| 1384 | #define MX53_PAD_DISP0_DAT9__PWM2_PWMO (_MX53_PAD_DISP0_DAT9__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 210 | #define MX53_PAD_DISP0_DAT9__GPIO4_30 IOMUX_PAD(0x3B0, 0x084, 1, __NA_, 0, NO_PAD_CTRL) |
| 1385 | #define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B (_MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) | 211 | #define MX53_PAD_DISP0_DAT9__PWM2_PWMO IOMUX_PAD(0x3B0, 0x084, 2, __NA_, 0, NO_PAD_CTRL) |
| 1386 | #define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 (_MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 212 | #define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B IOMUX_PAD(0x3B0, 0x084, 3, __NA_, 0, NO_PAD_CTRL) |
| 1387 | #define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 (_MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 213 | #define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x3B0, 0x084, 5, __NA_, 0, NO_PAD_CTRL) |
| 1388 | #define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 (_MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 214 | #define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 IOMUX_PAD(0x3B0, 0x084, 6, __NA_, 0, NO_PAD_CTRL) |
| 1389 | #define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 (_MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 215 | #define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 IOMUX_PAD(0x3B0, 0x084, 7, __NA_, 0, NO_PAD_CTRL) |
| 1390 | #define MX53_PAD_DISP0_DAT10__GPIO4_31 (_MX53_PAD_DISP0_DAT10__GPIO4_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 216 | #define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 IOMUX_PAD(0x3B4, 0x088, 0, __NA_, 0, NO_PAD_CTRL) |
| 1391 | #define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP (_MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) | 217 | #define MX53_PAD_DISP0_DAT10__GPIO4_31 IOMUX_PAD(0x3B4, 0x088, 1, __NA_, 0, NO_PAD_CTRL) |
| 1392 | #define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 (_MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 218 | #define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP IOMUX_PAD(0x3B4, 0x088, 2, __NA_, 0, NO_PAD_CTRL) |
| 1393 | #define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 (_MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 219 | #define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 \ |
| 1394 | #define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 (_MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 220 | IOMUX_PAD(0x3B4, 0x088, 5, __NA_, 0, NO_PAD_CTRL) |
| 1395 | #define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 (_MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 221 | #define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 IOMUX_PAD(0x3B4, 0x088, 6, __NA_, 0, NO_PAD_CTRL) |
| 1396 | #define MX53_PAD_DISP0_DAT11__GPIO5_5 (_MX53_PAD_DISP0_DAT11__GPIO5_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 222 | #define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 IOMUX_PAD(0x3B4, 0x088, 7, __NA_, 0, NO_PAD_CTRL) |
| 1397 | #define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT (_MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) | 223 | #define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 IOMUX_PAD(0x3B8, 0x08C, 0, __NA_, 0, NO_PAD_CTRL) |
| 1398 | #define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 (_MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 224 | #define MX53_PAD_DISP0_DAT11__GPIO5_5 IOMUX_PAD(0x3B8, 0x08C, 1, __NA_, 0, NO_PAD_CTRL) |
| 1399 | #define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 (_MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 225 | #define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT IOMUX_PAD(0x3B8, 0x08C, 2, __NA_, 0, NO_PAD_CTRL) |
| 1400 | #define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 (_MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 226 | #define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 \ |
| 1401 | #define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 (_MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 227 | IOMUX_PAD(0x3B8, 0x08C, 5, __NA_, 0, NO_PAD_CTRL) |
| 1402 | #define MX53_PAD_DISP0_DAT12__GPIO5_6 (_MX53_PAD_DISP0_DAT12__GPIO5_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 228 | #define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 IOMUX_PAD(0x3B8, 0x08C, 6, __NA_, 0, NO_PAD_CTRL) |
| 1403 | #define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK (_MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 229 | #define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 IOMUX_PAD(0x3B8, 0x08C, 7, __NA_, 0, NO_PAD_CTRL) |
| 1404 | #define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 (_MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 230 | #define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 IOMUX_PAD(0x3BC, 0x090, 0, __NA_, 0, NO_PAD_CTRL) |
| 1405 | #define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 (_MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 231 | #define MX53_PAD_DISP0_DAT12__GPIO5_6 IOMUX_PAD(0x3BC, 0x090, 1, __NA_, 0, NO_PAD_CTRL) |
| 1406 | #define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 (_MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 232 | #define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK IOMUX_PAD(0x3BC, 0x090, 2, __NA_, 0, NO_PAD_CTRL) |
| 1407 | #define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 (_MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 233 | #define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 \ |
| 1408 | #define MX53_PAD_DISP0_DAT13__GPIO5_7 (_MX53_PAD_DISP0_DAT13__GPIO5_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 234 | IOMUX_PAD(0x3BC, 0x090, 5, __NA_, 0, NO_PAD_CTRL) |
| 1409 | #define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS (_MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 235 | #define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 IOMUX_PAD(0x3BC, 0x090, 6, __NA_, 0, NO_PAD_CTRL) |
| 1410 | #define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 (_MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 236 | #define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 IOMUX_PAD(0x3BC, 0x090, 7, __NA_, 0, NO_PAD_CTRL) |
| 1411 | #define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 (_MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 237 | #define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 IOMUX_PAD(0x3C0, 0x094, 0, __NA_, 0, NO_PAD_CTRL) |
| 1412 | #define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 (_MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 238 | #define MX53_PAD_DISP0_DAT13__GPIO5_7 IOMUX_PAD(0x3C0, 0x094, 1, __NA_, 0, NO_PAD_CTRL) |
| 1413 | #define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 (_MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 239 | #define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS IOMUX_PAD(0x3C0, 0x094, 3, 0x754, 0, NO_PAD_CTRL) |
| 1414 | #define MX53_PAD_DISP0_DAT14__GPIO5_8 (_MX53_PAD_DISP0_DAT14__GPIO5_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 240 | #define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 \ |
| 1415 | #define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC (_MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 241 | IOMUX_PAD(0x3C0, 0x094, 5, __NA_, 0, NO_PAD_CTRL) |
| 1416 | #define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 (_MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 242 | #define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 IOMUX_PAD(0x3C0, 0x094, 6, __NA_, 0, NO_PAD_CTRL) |
| 1417 | #define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 (_MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 243 | #define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 IOMUX_PAD(0x3C0, 0x094, 7, __NA_, 0, NO_PAD_CTRL) |
| 1418 | #define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 (_MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 244 | #define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 IOMUX_PAD(0x3C4, 0x098, 0, __NA_, 0, NO_PAD_CTRL) |
| 1419 | #define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 (_MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 245 | #define MX53_PAD_DISP0_DAT14__GPIO5_8 IOMUX_PAD(0x3C4, 0x098, 1, __NA_, 0, NO_PAD_CTRL) |
| 1420 | #define MX53_PAD_DISP0_DAT15__GPIO5_9 (_MX53_PAD_DISP0_DAT15__GPIO5_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 246 | #define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC IOMUX_PAD(0x3C4, 0x098, 3, 0x750, 0, NO_PAD_CTRL) |
| 1421 | #define MX53_PAD_DISP0_DAT15__ECSPI1_SS1 (_MX53_PAD_DISP0_DAT15__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 247 | #define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 \ |
| 1422 | #define MX53_PAD_DISP0_DAT15__ECSPI2_SS1 (_MX53_PAD_DISP0_DAT15__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 248 | IOMUX_PAD(0x3C4, 0x098, 5, __NA_, 0, NO_PAD_CTRL) |
| 1423 | #define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 (_MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 249 | #define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 IOMUX_PAD(0x3C4, 0x098, 6, __NA_, 0, NO_PAD_CTRL) |
| 1424 | #define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 (_MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 250 | #define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 IOMUX_PAD(0x3C4, 0x098, 7, __NA_, 0, NO_PAD_CTRL) |
| 1425 | #define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 (_MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 251 | #define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 IOMUX_PAD(0x3C8, 0x09C, 0, __NA_, 0, NO_PAD_CTRL) |
| 1426 | #define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 (_MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 252 | #define MX53_PAD_DISP0_DAT15__GPIO5_9 IOMUX_PAD(0x3C8, 0x09C, 1, __NA_, 0, NO_PAD_CTRL) |
| 1427 | #define MX53_PAD_DISP0_DAT16__GPIO5_10 (_MX53_PAD_DISP0_DAT16__GPIO5_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 253 | #define MX53_PAD_DISP0_DAT15__ECSPI1_SS1 IOMUX_PAD(0x3C8, 0x09C, 2, 0x7AC, 1, NO_PAD_CTRL) |
| 1428 | #define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI (_MX53_PAD_DISP0_DAT16__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) | 254 | #define MX53_PAD_DISP0_DAT15__ECSPI2_SS1 IOMUX_PAD(0x3C8, 0x09C, 3, 0x7C8, 0, NO_PAD_CTRL) |
| 1429 | #define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC (_MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 255 | #define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 \ |
| 1430 | #define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 (_MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 256 | IOMUX_PAD(0x3C8, 0x09C, 5, __NA_, 0, NO_PAD_CTRL) |
| 1431 | #define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 (_MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 257 | #define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 IOMUX_PAD(0x3C8, 0x09C, 6, __NA_, 0, NO_PAD_CTRL) |
| 1432 | #define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 (_MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 258 | #define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 IOMUX_PAD(0x3C8, 0x09C, 7, __NA_, 0, NO_PAD_CTRL) |
| 1433 | #define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 (_MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 259 | #define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 IOMUX_PAD(0x3CC, 0x0A0, 0, __NA_, 0, NO_PAD_CTRL) |
| 1434 | #define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 (_MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 260 | #define MX53_PAD_DISP0_DAT16__GPIO5_10 IOMUX_PAD(0x3CC, 0x0A0, 1, __NA_, 0, NO_PAD_CTRL) |
| 1435 | #define MX53_PAD_DISP0_DAT17__GPIO5_11 (_MX53_PAD_DISP0_DAT17__GPIO5_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 261 | #define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI IOMUX_PAD(0x3CC, 0x0A0, 2, 0x7C0, 0, NO_PAD_CTRL) |
| 1436 | #define MX53_PAD_DISP0_DAT17__ECSPI2_MISO (_MX53_PAD_DISP0_DAT17__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 262 | #define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC IOMUX_PAD(0x3CC, 0x0A0, 3, 0x758, 1, NO_PAD_CTRL) |
| 1437 | #define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD (_MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 263 | #define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 IOMUX_PAD(0x3CC, 0x0A0, 4, 0x868, 0, NO_PAD_CTRL) |
| 1438 | #define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 (_MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 264 | #define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 \ |
| 1439 | #define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 (_MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 265 | IOMUX_PAD(0x3CC, 0x0A0, 5, __NA_, 0, NO_PAD_CTRL) |
| 1440 | #define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 (_MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 266 | #define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 IOMUX_PAD(0x3CC, 0x0A0, 6, __NA_, 0, NO_PAD_CTRL) |
| 1441 | #define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 (_MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 267 | #define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 IOMUX_PAD(0x3CC, 0x0A0, 7, __NA_, 0, NO_PAD_CTRL) |
| 1442 | #define MX53_PAD_DISP0_DAT18__GPIO5_12 (_MX53_PAD_DISP0_DAT18__GPIO5_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 268 | #define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 IOMUX_PAD(0x3D0, 0x0A4, 0, __NA_, 0, NO_PAD_CTRL) |
| 1443 | #define MX53_PAD_DISP0_DAT18__ECSPI2_SS0 (_MX53_PAD_DISP0_DAT18__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 269 | #define MX53_PAD_DISP0_DAT17__GPIO5_11 IOMUX_PAD(0x3D0, 0x0A4, 1, __NA_, 0, NO_PAD_CTRL) |
| 1444 | #define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS (_MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 270 | #define MX53_PAD_DISP0_DAT17__ECSPI2_MISO IOMUX_PAD(0x3D0, 0x0A4, 2, 0x7BC, 0, NO_PAD_CTRL) |
| 1445 | #define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS (_MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 271 | #define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD IOMUX_PAD(0x3D0, 0x0A4, 3, 0x74C, 1, NO_PAD_CTRL) |
| 1446 | #define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 (_MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 272 | #define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 IOMUX_PAD(0x3D0, 0x0A4, 4, 0x86C, 0, NO_PAD_CTRL) |
| 1447 | #define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 (_MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 273 | #define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 \ |
| 1448 | #define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 (_MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 274 | IOMUX_PAD(0x3D0, 0x0A4, 5, __NA_, 0, NO_PAD_CTRL) |
| 1449 | #define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 (_MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 275 | #define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 IOMUX_PAD(0x3D0, 0x0A4, 6, __NA_, 0, NO_PAD_CTRL) |
| 1450 | #define MX53_PAD_DISP0_DAT19__GPIO5_13 (_MX53_PAD_DISP0_DAT19__GPIO5_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 276 | #define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 IOMUX_PAD(0x3D4, 0x0A8, 0, __NA_, 0, NO_PAD_CTRL) |
| 1451 | #define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK (_MX53_PAD_DISP0_DAT19__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 277 | #define MX53_PAD_DISP0_DAT18__GPIO5_12 IOMUX_PAD(0x3D4, 0x0A8, 1, __NA_, 0, NO_PAD_CTRL) |
| 1452 | #define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD (_MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 278 | #define MX53_PAD_DISP0_DAT18__ECSPI2_SS0 IOMUX_PAD(0x3D4, 0x0A8, 2, 0x7C4, 0, NO_PAD_CTRL) |
| 1453 | #define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC (_MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 279 | #define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS IOMUX_PAD(0x3D4, 0x0A8, 3, 0x75C, 1, NO_PAD_CTRL) |
| 1454 | #define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 (_MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 280 | #define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS IOMUX_PAD(0x3D4, 0x0A8, 4, 0x73C, 0, NO_PAD_CTRL) |
| 1455 | #define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 (_MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 281 | #define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 \ |
| 1456 | #define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 (_MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 282 | IOMUX_PAD(0x3D4, 0x0A8, 5, __NA_, 0, NO_PAD_CTRL) |
| 1457 | #define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 (_MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 283 | #define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 IOMUX_PAD(0x3D4, 0x0A8, 6, __NA_, 0, NO_PAD_CTRL) |
| 1458 | #define MX53_PAD_DISP0_DAT20__GPIO5_14 (_MX53_PAD_DISP0_DAT20__GPIO5_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 284 | #define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 IOMUX_PAD(0x3D4, 0x0A8, 7, __NA_, 0, NO_PAD_CTRL) |
| 1459 | #define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK (_MX53_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 285 | #define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 IOMUX_PAD(0x3D8, 0x0AC, 0, __NA_, 0, NO_PAD_CTRL) |
| 1460 | #define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC (_MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 286 | #define MX53_PAD_DISP0_DAT19__GPIO5_13 IOMUX_PAD(0x3D8, 0x0AC, 1, __NA_, 0, NO_PAD_CTRL) |
| 1461 | #define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 (_MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 287 | #define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK IOMUX_PAD(0x3D8, 0x0AC, 2, 0x7B8, 0, NO_PAD_CTRL) |
| 1462 | #define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 (_MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 288 | #define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD IOMUX_PAD(0x3D8, 0x0AC, 3, 0x748, 1, NO_PAD_CTRL) |
| 1463 | #define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI (_MX53_PAD_DISP0_DAT20__SATA_PHY_TDI | MUX_PAD_CTRL(NO_PAD_CTRL)) | 289 | #define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC IOMUX_PAD(0x3D8, 0x0AC, 4, 0x738, 0, NO_PAD_CTRL) |
| 1464 | #define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 (_MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 290 | #define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 \ |
| 1465 | #define MX53_PAD_DISP0_DAT21__GPIO5_15 (_MX53_PAD_DISP0_DAT21__GPIO5_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 291 | IOMUX_PAD(0x3D8, 0x0AC, 5, __NA_, 0, NO_PAD_CTRL) |
| 1466 | #define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI (_MX53_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) | 292 | #define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 IOMUX_PAD(0x3D8, 0x0AC, 6, __NA_, 0, NO_PAD_CTRL) |
| 1467 | #define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD (_MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 293 | #define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 IOMUX_PAD(0x3D8, 0x0AC, 7, __NA_, 0, NO_PAD_CTRL) |
| 1468 | #define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 (_MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 294 | #define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 IOMUX_PAD(0x3DC, 0x0B0, 0, __NA_, 0, NO_PAD_CTRL) |
| 1469 | #define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 (_MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 295 | #define MX53_PAD_DISP0_DAT20__GPIO5_14 IOMUX_PAD(0x3DC, 0x0B0, 1, __NA_, 0, NO_PAD_CTRL) |
| 1470 | #define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO (_MX53_PAD_DISP0_DAT21__SATA_PHY_TDO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 296 | #define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK IOMUX_PAD(0x3DC, 0x0B0, 2, 0x79C, 1, NO_PAD_CTRL) |
| 1471 | #define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 (_MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 297 | #define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC IOMUX_PAD(0x3DC, 0x0B0, 3, 0x740, 0, NO_PAD_CTRL) |
| 1472 | #define MX53_PAD_DISP0_DAT22__GPIO5_16 (_MX53_PAD_DISP0_DAT22__GPIO5_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 298 | #define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 \ |
| 1473 | #define MX53_PAD_DISP0_DAT22__ECSPI1_MISO (_MX53_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 299 | IOMUX_PAD(0x3DC, 0x0B0, 5, __NA_, 0, NO_PAD_CTRL) |
| 1474 | #define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS (_MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 300 | #define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 IOMUX_PAD(0x3DC, 0x0B0, 6, __NA_, 0, NO_PAD_CTRL) |
| 1475 | #define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 (_MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 301 | #define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI IOMUX_PAD(0x3DC, 0x0B0, 7, __NA_, 0, NO_PAD_CTRL) |
| 1476 | #define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 (_MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 302 | #define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 IOMUX_PAD(0x3E0, 0x0B4, 0, __NA_, 0, NO_PAD_CTRL) |
| 1477 | #define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK (_MX53_PAD_DISP0_DAT22__SATA_PHY_TCK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 303 | #define MX53_PAD_DISP0_DAT21__GPIO5_15 IOMUX_PAD(0x3E0, 0x0B4, 1, __NA_, 0, NO_PAD_CTRL) |
| 1478 | #define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 (_MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 304 | #define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI IOMUX_PAD(0x3E0, 0x0B4, 2, 0x7A4, 1, NO_PAD_CTRL) |
| 1479 | #define MX53_PAD_DISP0_DAT23__GPIO5_17 (_MX53_PAD_DISP0_DAT23__GPIO5_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 305 | #define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD IOMUX_PAD(0x3E0, 0x0B4, 3, 0x734, 0, NO_PAD_CTRL) |
| 1480 | #define MX53_PAD_DISP0_DAT23__ECSPI1_SS0 (_MX53_PAD_DISP0_DAT23__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 306 | #define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 IOMUX_PAD(0x3E0, 0x0B4, 5, __NA_, 0, NO_PAD_CTRL) |
| 1481 | #define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD (_MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 307 | #define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 IOMUX_PAD(0x3E0, 0x0B4, 6, __NA_, 0, NO_PAD_CTRL) |
| 1482 | #define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 (_MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 308 | #define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO IOMUX_PAD(0x3E0, 0x0B4, 7, __NA_, 0, NO_PAD_CTRL) |
| 1483 | #define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 (_MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 309 | #define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 IOMUX_PAD(0x3E4, 0x0B8, 0, __NA_, 0, NO_PAD_CTRL) |
| 1484 | #define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS (_MX53_PAD_DISP0_DAT23__SATA_PHY_TMS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 310 | #define MX53_PAD_DISP0_DAT22__GPIO5_16 IOMUX_PAD(0x3E4, 0x0B8, 1, __NA_, 0, NO_PAD_CTRL) |
| 1485 | #define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK (_MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 311 | #define MX53_PAD_DISP0_DAT22__ECSPI1_MISO IOMUX_PAD(0x3E4, 0x0B8, 2, 0x7A0, 1, NO_PAD_CTRL) |
| 1486 | #define MX53_PAD_CSI0_PIXCLK__GPIO5_18 (_MX53_PAD_CSI0_PIXCLK__GPIO5_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 312 | #define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS IOMUX_PAD(0x3E4, 0x0B8, 3, 0x744, 0, NO_PAD_CTRL) |
| 1487 | #define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 (_MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 313 | #define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 IOMUX_PAD(0x3E4, 0x0B8, 5, __NA_, 0, NO_PAD_CTRL) |
| 1488 | #define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 (_MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 314 | #define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 IOMUX_PAD(0x3E4, 0x0B8, 6, __NA_, 0, NO_PAD_CTRL) |
| 1489 | #define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC (_MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 315 | #define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK IOMUX_PAD(0x3E4, 0x0B8, 7, __NA_, 0, NO_PAD_CTRL) |
| 1490 | #define MX53_PAD_CSI0_MCLK__GPIO5_19 (_MX53_PAD_CSI0_MCLK__GPIO5_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 316 | #define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 IOMUX_PAD(0x3E8, 0x0BC, 0, __NA_, 0, NO_PAD_CTRL) |
| 1491 | #define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK (_MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 317 | #define MX53_PAD_DISP0_DAT23__GPIO5_17 IOMUX_PAD(0x3E8, 0x0BC, 1, __NA_, 0, NO_PAD_CTRL) |
| 1492 | #define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 (_MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 318 | #define MX53_PAD_DISP0_DAT23__ECSPI1_SS0 IOMUX_PAD(0x3E8, 0x0BC, 2, 0x7A8, 1, NO_PAD_CTRL) |
| 1493 | #define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 (_MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 319 | #define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD IOMUX_PAD(0x3E8, 0x0BC, 3, 0x730, 0, NO_PAD_CTRL) |
| 1494 | #define MX53_PAD_CSI0_MCLK__TPIU_TRCTL (_MX53_PAD_CSI0_MCLK__TPIU_TRCTL | MUX_PAD_CTRL(NO_PAD_CTRL)) | 320 | #define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 IOMUX_PAD(0x3E8, 0x0BC, 5, __NA_, 0, NO_PAD_CTRL) |
| 1495 | #define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN (_MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) | 321 | #define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 IOMUX_PAD(0x3E8, 0x0BC, 6, __NA_, 0, NO_PAD_CTRL) |
| 1496 | #define MX53_PAD_CSI0_DATA_EN__GPIO5_20 (_MX53_PAD_CSI0_DATA_EN__GPIO5_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 322 | #define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS IOMUX_PAD(0x3E8, 0x0BC, 7, __NA_, 0, NO_PAD_CTRL) |
| 1497 | #define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 (_MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 323 | #define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK IOMUX_PAD(0x3EC, 0x0C0, 0, __NA_, 0, NO_PAD_CTRL) |
| 1498 | #define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 (_MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 324 | #define MX53_PAD_CSI0_PIXCLK__GPIO5_18 IOMUX_PAD(0x3EC, 0x0C0, 1, __NA_, 0, NO_PAD_CTRL) |
| 1499 | #define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK (_MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 325 | #define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 IOMUX_PAD(0x3EC, 0x0C0, 5, __NA_, 0, NO_PAD_CTRL) |
| 1500 | #define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC (_MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 326 | #define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 IOMUX_PAD(0x3EC, 0x0C0, 6, __NA_, 0, NO_PAD_CTRL) |
| 1501 | #define MX53_PAD_CSI0_VSYNC__GPIO5_21 (_MX53_PAD_CSI0_VSYNC__GPIO5_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 327 | #define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC IOMUX_PAD(0x3F0, 0x0C4, 0, __NA_, 0, NO_PAD_CTRL) |
| 1502 | #define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 (_MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 328 | #define MX53_PAD_CSI0_MCLK__GPIO5_19 IOMUX_PAD(0x3F0, 0x0C4, 1, __NA_, 0, NO_PAD_CTRL) |
| 1503 | #define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 (_MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 329 | #define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK IOMUX_PAD(0x3F0, 0x0C4, 2, __NA_, 0, NO_PAD_CTRL) |
| 1504 | #define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 (_MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 330 | #define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 IOMUX_PAD(0x3F0, 0x0C4, 5, __NA_, 0, NO_PAD_CTRL) |
| 1505 | #define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 (_MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 331 | #define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 IOMUX_PAD(0x3F0, 0x0C4, 6, __NA_, 0, NO_PAD_CTRL) |
| 1506 | #define MX53_PAD_CSI0_DAT4__GPIO5_22 (_MX53_PAD_CSI0_DAT4__GPIO5_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 332 | #define MX53_PAD_CSI0_MCLK__TPIU_TRCTL IOMUX_PAD(0x3F0, 0x0C4, 7, __NA_, 0, NO_PAD_CTRL) |
| 1507 | #define MX53_PAD_CSI0_DAT4__KPP_COL_5 (_MX53_PAD_CSI0_DAT4__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 333 | #define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN IOMUX_PAD(0x3F4, 0x0C8, 0, __NA_, 0, NO_PAD_CTRL) |
| 1508 | #define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK (_MX53_PAD_CSI0_DAT4__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 334 | #define MX53_PAD_CSI0_DATA_EN__GPIO5_20 IOMUX_PAD(0x3F4, 0x0C8, 1, __NA_, 0, NO_PAD_CTRL) |
| 1509 | #define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP (_MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) | 335 | #define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 IOMUX_PAD(0x3F4, 0x0C8, 5, __NA_, 0, NO_PAD_CTRL) |
| 1510 | #define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC (_MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 336 | #define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 IOMUX_PAD(0x3F4, 0x0C8, 6, __NA_, 0, NO_PAD_CTRL) |
| 1511 | #define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 (_MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 337 | #define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK IOMUX_PAD(0x3F4, 0x0C8, 7, __NA_, 0, NO_PAD_CTRL) |
| 1512 | #define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 (_MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 338 | #define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC IOMUX_PAD(0x3F8, 0x0CC, 0, __NA_, 0, NO_PAD_CTRL) |
| 1513 | #define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 (_MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 339 | #define MX53_PAD_CSI0_VSYNC__GPIO5_21 IOMUX_PAD(0x3F8, 0x0CC, 1, __NA_, 0, NO_PAD_CTRL) |
| 1514 | #define MX53_PAD_CSI0_DAT5__GPIO5_23 (_MX53_PAD_CSI0_DAT5__GPIO5_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 340 | #define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 IOMUX_PAD(0x3F8, 0x0CC, 5, __NA_, 0, NO_PAD_CTRL) |
| 1515 | #define MX53_PAD_CSI0_DAT5__KPP_ROW_5 (_MX53_PAD_CSI0_DAT5__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 341 | #define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 IOMUX_PAD(0x3F8, 0x0CC, 6, __NA_, 0, NO_PAD_CTRL) |
| 1516 | #define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI (_MX53_PAD_CSI0_DAT5__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) | 342 | #define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 IOMUX_PAD(0x3F8, 0x0CC, 7, __NA_, 0, NO_PAD_CTRL) |
| 1517 | #define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT (_MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL)) | 343 | #define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 IOMUX_PAD(0x3FC, 0x0D0, 0, __NA_, 0, NO_PAD_CTRL) |
| 1518 | #define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD (_MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 344 | #define MX53_PAD_CSI0_DAT4__GPIO5_22 IOMUX_PAD(0x3FC, 0x0D0, 1, __NA_, 0, NO_PAD_CTRL) |
| 1519 | #define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 (_MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 345 | #define MX53_PAD_CSI0_DAT4__KPP_COL_5 IOMUX_PAD(0x3FC, 0x0D0, 2, 0x840, 1, NO_PAD_CTRL) |
| 1520 | #define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 (_MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 346 | #define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK IOMUX_PAD(0x3FC, 0x0D0, 3, 0x79C, 2, NO_PAD_CTRL) |
| 1521 | #define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 (_MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 347 | #define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP IOMUX_PAD(0x3FC, 0x0D0, 4, __NA_, 0, NO_PAD_CTRL) |
| 1522 | #define MX53_PAD_CSI0_DAT6__GPIO5_24 (_MX53_PAD_CSI0_DAT6__GPIO5_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 348 | #define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC IOMUX_PAD(0x3FC, 0x0D0, 5, __NA_, 0, NO_PAD_CTRL) |
| 1523 | #define MX53_PAD_CSI0_DAT6__KPP_COL_6 (_MX53_PAD_CSI0_DAT6__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 349 | #define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 IOMUX_PAD(0x3FC, 0x0D0, 6, __NA_, 0, NO_PAD_CTRL) |
| 1524 | #define MX53_PAD_CSI0_DAT6__ECSPI1_MISO (_MX53_PAD_CSI0_DAT6__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 350 | #define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 IOMUX_PAD(0x3FC, 0x0D0, 7, __NA_, 0, NO_PAD_CTRL) |
| 1525 | #define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK (_MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 351 | #define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 IOMUX_PAD(0x400, 0x0D4, 0, __NA_, 0, NO_PAD_CTRL) |
| 1526 | #define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS (_MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 352 | #define MX53_PAD_CSI0_DAT5__GPIO5_23 IOMUX_PAD(0x400, 0x0D4, 1, __NA_, 0, NO_PAD_CTRL) |
| 1527 | #define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 (_MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 353 | #define MX53_PAD_CSI0_DAT5__KPP_ROW_5 IOMUX_PAD(0x400, 0x0D4, 2, 0x84C, 0, NO_PAD_CTRL) |
| 1528 | #define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 (_MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 354 | #define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI IOMUX_PAD(0x400, 0x0D4, 3, 0x7A4, 2, NO_PAD_CTRL) |
| 1529 | #define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 (_MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 355 | #define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT IOMUX_PAD(0x400, 0x0D4, 4, __NA_, 0, NO_PAD_CTRL) |
| 1530 | #define MX53_PAD_CSI0_DAT7__GPIO5_25 (_MX53_PAD_CSI0_DAT7__GPIO5_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 356 | #define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD IOMUX_PAD(0x400, 0x0D4, 5, __NA_, 0, NO_PAD_CTRL) |
| 1531 | #define MX53_PAD_CSI0_DAT7__KPP_ROW_6 (_MX53_PAD_CSI0_DAT7__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 357 | #define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 IOMUX_PAD(0x400, 0x0D4, 6, __NA_, 0, NO_PAD_CTRL) |
| 1532 | #define MX53_PAD_CSI0_DAT7__ECSPI1_SS0 (_MX53_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 358 | #define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 IOMUX_PAD(0x400, 0x0D4, 7, __NA_, 0, NO_PAD_CTRL) |
| 1533 | #define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR (_MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) | 359 | #define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 IOMUX_PAD(0x404, 0x0D8, 0, __NA_, 0, NO_PAD_CTRL) |
| 1534 | #define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD (_MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 360 | #define MX53_PAD_CSI0_DAT6__GPIO5_24 IOMUX_PAD(0x404, 0x0D8, 1, __NA_, 0, NO_PAD_CTRL) |
| 1535 | #define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 (_MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 361 | #define MX53_PAD_CSI0_DAT6__KPP_COL_6 IOMUX_PAD(0x404, 0x0D8, 2, 0x844, 0, NO_PAD_CTRL) |
| 1536 | #define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 (_MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 362 | #define MX53_PAD_CSI0_DAT6__ECSPI1_MISO IOMUX_PAD(0x404, 0x0D8, 3, 0x7A0, 2, NO_PAD_CTRL) |
| 1537 | #define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 (_MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 363 | #define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK IOMUX_PAD(0x404, 0x0D8, 4, __NA_, 0, NO_PAD_CTRL) |
| 1538 | #define MX53_PAD_CSI0_DAT8__GPIO5_26 (_MX53_PAD_CSI0_DAT8__GPIO5_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 364 | #define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS IOMUX_PAD(0x404, 0x0D8, 5, __NA_, 0, NO_PAD_CTRL) |
| 1539 | #define MX53_PAD_CSI0_DAT8__KPP_COL_7 (_MX53_PAD_CSI0_DAT8__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 365 | #define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 IOMUX_PAD(0x404, 0x0D8, 6, __NA_, 0, NO_PAD_CTRL) |
| 1540 | #define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK (_MX53_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 366 | #define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 IOMUX_PAD(0x404, 0x0D8, 7, __NA_, 0, NO_PAD_CTRL) |
| 1541 | #define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC (_MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 367 | #define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 IOMUX_PAD(0x408, 0x0DC, 0, __NA_, 0, NO_PAD_CTRL) |
| 1542 | #define MX53_PAD_CSI0_DAT8__I2C1_SDA (_MX53_PAD_CSI0_DAT8__I2C1_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C)) | 368 | #define MX53_PAD_CSI0_DAT7__GPIO5_25 IOMUX_PAD(0x408, 0x0DC, 1, __NA_, 0, NO_PAD_CTRL) |
| 1543 | #define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 (_MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 369 | #define MX53_PAD_CSI0_DAT7__KPP_ROW_6 IOMUX_PAD(0x408, 0x0DC, 2, 0x850, 0, NO_PAD_CTRL) |
| 1544 | #define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 (_MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 370 | #define MX53_PAD_CSI0_DAT7__ECSPI1_SS0 IOMUX_PAD(0x408, 0x0DC, 3, 0x7A8, 2, NO_PAD_CTRL) |
| 1545 | #define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 (_MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 371 | #define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR IOMUX_PAD(0x408, 0x0DC, 4, __NA_, 0, NO_PAD_CTRL) |
| 1546 | #define MX53_PAD_CSI0_DAT9__GPIO5_27 (_MX53_PAD_CSI0_DAT9__GPIO5_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 372 | #define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD IOMUX_PAD(0x408, 0x0DC, 5, __NA_, 0, NO_PAD_CTRL) |
| 1547 | #define MX53_PAD_CSI0_DAT9__KPP_ROW_7 (_MX53_PAD_CSI0_DAT9__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 373 | #define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 IOMUX_PAD(0x408, 0x0DC, 6, __NA_, 0, NO_PAD_CTRL) |
| 1548 | #define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI (_MX53_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) | 374 | #define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 IOMUX_PAD(0x408, 0x0DC, 7, __NA_, 0, NO_PAD_CTRL) |
| 1549 | #define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR (_MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) | 375 | #define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 IOMUX_PAD(0x40C, 0x0E0, 0, __NA_, 0, NO_PAD_CTRL) |
| 1550 | #define MX53_PAD_CSI0_DAT9__I2C1_SCL (_MX53_PAD_CSI0_DAT9__I2C1_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C)) | 376 | #define MX53_PAD_CSI0_DAT8__GPIO5_26 IOMUX_PAD(0x40C, 0x0E0, 1, __NA_, 0, NO_PAD_CTRL) |
| 1551 | #define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 (_MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 377 | #define MX53_PAD_CSI0_DAT8__KPP_COL_7 IOMUX_PAD(0x40C, 0x0E0, 2, 0x848, 0, NO_PAD_CTRL) |
| 1552 | #define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 (_MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 378 | #define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK IOMUX_PAD(0x40C, 0x0E0, 3, 0x7B8, 1, NO_PAD_CTRL) |
| 1553 | #define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 (_MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 379 | #define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC IOMUX_PAD(0x40C, 0x0E0, 4, __NA_, 0, NO_PAD_CTRL) |
| 1554 | #define MX53_PAD_CSI0_DAT10__GPIO5_28 (_MX53_PAD_CSI0_DAT10__GPIO5_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 380 | #define MX53_PAD_CSI0_DAT8__I2C1_SDA IOMUX_PAD(0x40C, 0x0E0, 5 | IOMUX_CONFIG_SION, 0x818, 0, NO_PAD_CTRL) |
| 1555 | #define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX (_MX53_PAD_CSI0_DAT10__UART1_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 381 | #define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 IOMUX_PAD(0x40C, 0x0E0, 6, __NA_, 0, NO_PAD_CTRL) |
| 1556 | #define MX53_PAD_CSI0_DAT10__ECSPI2_MISO (_MX53_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 382 | #define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 IOMUX_PAD(0x40C, 0x0E0, 7, __NA_, 0, NO_PAD_CTRL) |
| 1557 | #define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC (_MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 383 | #define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 IOMUX_PAD(0x410, 0x0E4, 0, __NA_, 0, NO_PAD_CTRL) |
| 1558 | #define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 (_MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 384 | #define MX53_PAD_CSI0_DAT9__GPIO5_27 IOMUX_PAD(0x410, 0x0E4, 1, __NA_, 0, NO_PAD_CTRL) |
| 1559 | #define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 (_MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 385 | #define MX53_PAD_CSI0_DAT9__KPP_ROW_7 IOMUX_PAD(0x410, 0x0E4, 2, 0x854, 0, NO_PAD_CTRL) |
| 1560 | #define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 (_MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 386 | #define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI IOMUX_PAD(0x410, 0x0E4, 3, 0x7C0, 1, NO_PAD_CTRL) |
| 1561 | #define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 (_MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 387 | #define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR IOMUX_PAD(0x410, 0x0E4, 4, __NA_, 0, NO_PAD_CTRL) |
| 1562 | #define MX53_PAD_CSI0_DAT11__GPIO5_29 (_MX53_PAD_CSI0_DAT11__GPIO5_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 388 | #define MX53_PAD_CSI0_DAT9__I2C1_SCL IOMUX_PAD(0x410, 0x0E4, 5 | IOMUX_CONFIG_SION, 0x814, 0, NO_PAD_CTRL) |
| 1563 | #define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX (_MX53_PAD_CSI0_DAT11__UART1_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 389 | #define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 IOMUX_PAD(0x410, 0x0E4, 6, __NA_, 0, NO_PAD_CTRL) |
| 1564 | #define MX53_PAD_CSI0_DAT11__ECSPI2_SS0 (_MX53_PAD_CSI0_DAT11__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 390 | #define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 IOMUX_PAD(0x410, 0x0E4, 7, __NA_, 0, NO_PAD_CTRL) |
| 1565 | #define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS (_MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 391 | #define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 IOMUX_PAD(0x414, 0x0E8, 0, __NA_, 0, NO_PAD_CTRL) |
| 1566 | #define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 (_MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 392 | #define MX53_PAD_CSI0_DAT10__GPIO5_28 IOMUX_PAD(0x414, 0x0E8, 1, __NA_, 0, NO_PAD_CTRL) |
| 1567 | #define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 (_MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 393 | #define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX IOMUX_PAD(0x414, 0x0E8, 2, __NA_, 0, MX53_UART_PAD_CTRL) |
| 1568 | #define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 (_MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 394 | #define MX53_PAD_CSI0_DAT10__ECSPI2_MISO IOMUX_PAD(0x414, 0x0E8, 3, 0x7BC, 1, NO_PAD_CTRL) |
| 1569 | #define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 (_MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 395 | #define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC IOMUX_PAD(0x414, 0x0E8, 4, __NA_, 0, NO_PAD_CTRL) |
| 1570 | #define MX53_PAD_CSI0_DAT12__GPIO5_30 (_MX53_PAD_CSI0_DAT12__GPIO5_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 396 | #define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 IOMUX_PAD(0x414, 0x0E8, 5, __NA_, 0, NO_PAD_CTRL) |
| 1571 | #define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX (_MX53_PAD_CSI0_DAT12__UART4_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 397 | #define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 IOMUX_PAD(0x414, 0x0E8, 6, __NA_, 0, NO_PAD_CTRL) |
| 1572 | #define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 (_MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 398 | #define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 IOMUX_PAD(0x414, 0x0E8, 7, __NA_, 0, NO_PAD_CTRL) |
| 1573 | #define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 (_MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 399 | #define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 IOMUX_PAD(0x418, 0x0EC, 0, __NA_, 0, NO_PAD_CTRL) |
| 1574 | #define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 (_MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 400 | #define MX53_PAD_CSI0_DAT11__GPIO5_29 IOMUX_PAD(0x418, 0x0EC, 1, __NA_, 0, NO_PAD_CTRL) |
| 1575 | #define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 (_MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 401 | #define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX IOMUX_PAD(0x418, 0x0EC, 2, 0x878, 1, MX53_UART_PAD_CTRL) |
| 1576 | #define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 (_MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 402 | #define MX53_PAD_CSI0_DAT11__ECSPI2_SS0 IOMUX_PAD(0x418, 0x0EC, 3, 0x7C4, 1, NO_PAD_CTRL) |
| 1577 | #define MX53_PAD_CSI0_DAT13__GPIO5_31 (_MX53_PAD_CSI0_DAT13__GPIO5_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 403 | #define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS IOMUX_PAD(0x418, 0x0EC, 4, __NA_, 0, NO_PAD_CTRL) |
| 1578 | #define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX (_MX53_PAD_CSI0_DAT13__UART4_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 404 | #define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 IOMUX_PAD(0x418, 0x0EC, 5, __NA_, 0, NO_PAD_CTRL) |
| 1579 | #define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 (_MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 405 | #define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 IOMUX_PAD(0x418, 0x0EC, 6, __NA_, 0, NO_PAD_CTRL) |
| 1580 | #define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 (_MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 406 | #define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 IOMUX_PAD(0x418, 0x0EC, 7, __NA_, 0, NO_PAD_CTRL) |
| 1581 | #define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 (_MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 407 | #define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 IOMUX_PAD(0x41C, 0x0F0, 0, __NA_, 0, NO_PAD_CTRL) |
| 1582 | #define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 (_MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 408 | #define MX53_PAD_CSI0_DAT12__GPIO5_30 IOMUX_PAD(0x41C, 0x0F0, 1, __NA_, 0, NO_PAD_CTRL) |
| 1583 | #define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 (_MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 409 | #define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX IOMUX_PAD(0x41C, 0x0F0, 2, __NA_, 0, MX53_UART_PAD_CTRL) |
| 1584 | #define MX53_PAD_CSI0_DAT14__GPIO6_0 (_MX53_PAD_CSI0_DAT14__GPIO6_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 410 | #define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 IOMUX_PAD(0x41C, 0x0F0, 4, __NA_, 0, NO_PAD_CTRL) |
| 1585 | #define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX (_MX53_PAD_CSI0_DAT14__UART5_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 411 | #define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 IOMUX_PAD(0x41C, 0x0F0, 5, __NA_, 0, NO_PAD_CTRL) |
| 1586 | #define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 (_MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 412 | #define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 IOMUX_PAD(0x41C, 0x0F0, 6, __NA_, 0, NO_PAD_CTRL) |
| 1587 | #define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 (_MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 413 | #define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 IOMUX_PAD(0x41C, 0x0F0, 7, __NA_, 0, NO_PAD_CTRL) |
| 1588 | #define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 (_MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 414 | #define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 IOMUX_PAD(0x420, 0x0F4, 0, __NA_, 0, NO_PAD_CTRL) |
| 1589 | #define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 (_MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 415 | #define MX53_PAD_CSI0_DAT13__GPIO5_31 IOMUX_PAD(0x420, 0x0F4, 1, __NA_, 0, NO_PAD_CTRL) |
| 1590 | #define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 (_MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 416 | #define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX IOMUX_PAD(0x420, 0x0F4, 2, 0x890, 3, MX53_UART_PAD_CTRL) |
| 1591 | #define MX53_PAD_CSI0_DAT15__GPIO6_1 (_MX53_PAD_CSI0_DAT15__GPIO6_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 417 | #define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 IOMUX_PAD(0x420, 0x0F4, 4, __NA_, 0, NO_PAD_CTRL) |
| 1592 | #define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX (_MX53_PAD_CSI0_DAT15__UART5_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 418 | #define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 IOMUX_PAD(0x420, 0x0F4, 5, __NA_, 0, NO_PAD_CTRL) |
| 1593 | #define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 (_MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 419 | #define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 IOMUX_PAD(0x420, 0x0F4, 6, __NA_, 0, NO_PAD_CTRL) |
| 1594 | #define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 (_MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 420 | #define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 IOMUX_PAD(0x420, 0x0F4, 7, __NA_, 0, NO_PAD_CTRL) |
| 1595 | #define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 (_MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 421 | #define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 IOMUX_PAD(0x424, 0x0F8, 0, __NA_, 0, NO_PAD_CTRL) |
| 1596 | #define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 (_MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 422 | #define MX53_PAD_CSI0_DAT14__GPIO6_0 IOMUX_PAD(0x424, 0x0F8, 1, __NA_, 0, NO_PAD_CTRL) |
| 1597 | #define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 (_MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 423 | #define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX IOMUX_PAD(0x424, 0x0F8, 2, __NA_, 0, MX53_UART_PAD_CTRL) |
| 1598 | #define MX53_PAD_CSI0_DAT16__GPIO6_2 (_MX53_PAD_CSI0_DAT16__GPIO6_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 424 | #define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 IOMUX_PAD(0x424, 0x0F8, 4, __NA_, 0, NO_PAD_CTRL) |
| 1599 | #define MX53_PAD_CSI0_DAT16__UART4_RTS (_MX53_PAD_CSI0_DAT16__UART4_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 425 | #define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 IOMUX_PAD(0x424, 0x0F8, 5, __NA_, 0, NO_PAD_CTRL) |
| 1600 | #define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 (_MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 426 | #define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 IOMUX_PAD(0x424, 0x0F8, 6, __NA_, 0, NO_PAD_CTRL) |
| 1601 | #define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 (_MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 427 | #define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 IOMUX_PAD(0x424, 0x0F8, 7, __NA_, 0, NO_PAD_CTRL) |
| 1602 | #define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 (_MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 428 | #define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 IOMUX_PAD(0x428, 0x0FC, 0, __NA_, 0, NO_PAD_CTRL) |
| 1603 | #define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 (_MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 429 | #define MX53_PAD_CSI0_DAT15__GPIO6_1 IOMUX_PAD(0x428, 0x0FC, 1, __NA_, 0, NO_PAD_CTRL) |
| 1604 | #define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 (_MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 430 | #define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX IOMUX_PAD(0x428, 0x0FC, 2, 0x898, 3, MX53_UART_PAD_CTRL) |
| 1605 | #define MX53_PAD_CSI0_DAT17__GPIO6_3 (_MX53_PAD_CSI0_DAT17__GPIO6_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 431 | #define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 IOMUX_PAD(0x428, 0x0FC, 4, __NA_, 0, NO_PAD_CTRL) |
| 1606 | #define MX53_PAD_CSI0_DAT17__UART4_CTS (_MX53_PAD_CSI0_DAT17__UART4_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 432 | #define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 IOMUX_PAD(0x428, 0x0FC, 5, __NA_, 0, NO_PAD_CTRL) |
| 1607 | #define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 (_MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 433 | #define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 IOMUX_PAD(0x428, 0x0FC, 6, __NA_, 0, NO_PAD_CTRL) |
| 1608 | #define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 (_MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 434 | #define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 IOMUX_PAD(0x428, 0x0FC, 7, __NA_, 0, NO_PAD_CTRL) |
| 1609 | #define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 (_MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 435 | #define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 IOMUX_PAD(0x42C, 0x100, 0, __NA_, 0, NO_PAD_CTRL) |
| 1610 | #define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 (_MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 436 | #define MX53_PAD_CSI0_DAT16__GPIO6_2 IOMUX_PAD(0x42C, 0x100, 1, __NA_, 0, NO_PAD_CTRL) |
| 1611 | #define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 (_MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 437 | #define MX53_PAD_CSI0_DAT16__UART4_RTS IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, MX53_UART_PAD_CTRL) |
| 1612 | #define MX53_PAD_CSI0_DAT18__GPIO6_4 (_MX53_PAD_CSI0_DAT18__GPIO6_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 438 | #define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 IOMUX_PAD(0x42C, 0x100, 4, __NA_, 0, NO_PAD_CTRL) |
| 1613 | #define MX53_PAD_CSI0_DAT18__UART5_RTS (_MX53_PAD_CSI0_DAT18__UART5_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 439 | #define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 IOMUX_PAD(0x42C, 0x100, 5, __NA_, 0, NO_PAD_CTRL) |
| 1614 | #define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 (_MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 440 | #define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 IOMUX_PAD(0x42C, 0x100, 6, __NA_, 0, NO_PAD_CTRL) |
| 1615 | #define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 (_MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 441 | #define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 IOMUX_PAD(0x42C, 0x100, 7, __NA_, 0, NO_PAD_CTRL) |
| 1616 | #define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 (_MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 442 | #define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 IOMUX_PAD(0x430, 0x104, 0, __NA_, 0, NO_PAD_CTRL) |
| 1617 | #define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 (_MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 443 | #define MX53_PAD_CSI0_DAT17__GPIO6_3 IOMUX_PAD(0x430, 0x104, 1, __NA_, 0, NO_PAD_CTRL) |
| 1618 | #define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 (_MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 444 | #define MX53_PAD_CSI0_DAT17__UART4_CTS IOMUX_PAD(0x430, 0x104, 2, __NA_, 0, MX53_UART_PAD_CTRL) |
| 1619 | #define MX53_PAD_CSI0_DAT19__GPIO6_5 (_MX53_PAD_CSI0_DAT19__GPIO6_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 445 | #define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 IOMUX_PAD(0x430, 0x104, 4, __NA_, 0, NO_PAD_CTRL) |
| 1620 | #define MX53_PAD_CSI0_DAT19__UART5_CTS (_MX53_PAD_CSI0_DAT19__UART5_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 446 | #define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 IOMUX_PAD(0x430, 0x104, 5, __NA_, 0, NO_PAD_CTRL) |
| 1621 | #define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 (_MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 447 | #define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 IOMUX_PAD(0x430, 0x104, 6, __NA_, 0, NO_PAD_CTRL) |
| 1622 | #define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 (_MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 448 | #define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 IOMUX_PAD(0x430, 0x104, 7, __NA_, 0, NO_PAD_CTRL) |
| 1623 | #define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 (_MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 449 | #define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 IOMUX_PAD(0x434, 0x108, 0, __NA_, 0, NO_PAD_CTRL) |
| 1624 | #define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK (_MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 450 | #define MX53_PAD_CSI0_DAT18__GPIO6_4 IOMUX_PAD(0x434, 0x108, 1, __NA_, 0, NO_PAD_CTRL) |
| 1625 | #define MX53_PAD_EIM_A25__EMI_WEIM_A_25 (_MX53_PAD_EIM_A25__EMI_WEIM_A_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 451 | #define MX53_PAD_CSI0_DAT18__UART5_RTS IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, MX53_UART_PAD_CTRL) |
| 1626 | #define MX53_PAD_EIM_A25__GPIO5_2 (_MX53_PAD_EIM_A25__GPIO5_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 452 | #define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 IOMUX_PAD(0x434, 0x108, 4, __NA_, 0, NO_PAD_CTRL) |
| 1627 | #define MX53_PAD_EIM_A25__ECSPI2_RDY (_MX53_PAD_EIM_A25__ECSPI2_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) | 453 | #define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 IOMUX_PAD(0x434, 0x108, 5, __NA_, 0, NO_PAD_CTRL) |
| 1628 | #define MX53_PAD_EIM_A25__IPU_DI1_PIN12 (_MX53_PAD_EIM_A25__IPU_DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 454 | #define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 IOMUX_PAD(0x434, 0x108, 6, __NA_, 0, NO_PAD_CTRL) |
| 1629 | #define MX53_PAD_EIM_A25__CSPI_SS1 (_MX53_PAD_EIM_A25__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 455 | #define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 IOMUX_PAD(0x434, 0x108, 7, __NA_, 0, NO_PAD_CTRL) |
| 1630 | #define MX53_PAD_EIM_A25__IPU_DI0_D1_CS (_MX53_PAD_EIM_A25__IPU_DI0_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 456 | #define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 IOMUX_PAD(0x438, 0x10C, 0, __NA_, 0, NO_PAD_CTRL) |
| 1631 | #define MX53_PAD_EIM_A25__USBPHY1_BISTOK (_MX53_PAD_EIM_A25__USBPHY1_BISTOK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 457 | #define MX53_PAD_CSI0_DAT19__GPIO6_5 IOMUX_PAD(0x438, 0x10C, 1, __NA_, 0, NO_PAD_CTRL) |
| 1632 | #define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 (_MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 458 | #define MX53_PAD_CSI0_DAT19__UART5_CTS IOMUX_PAD(0x438, 0x10C, 2, __NA_, 0, MX53_UART_PAD_CTRL) |
| 1633 | #define MX53_PAD_EIM_EB2__GPIO2_30 (_MX53_PAD_EIM_EB2__GPIO2_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 459 | #define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 IOMUX_PAD(0x438, 0x10C, 4, __NA_, 0, NO_PAD_CTRL) |
| 1634 | #define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK (_MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 460 | #define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 IOMUX_PAD(0x438, 0x10C, 5, __NA_, 0, NO_PAD_CTRL) |
| 1635 | #define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS (_MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 461 | #define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 IOMUX_PAD(0x438, 0x10C, 6, __NA_, 0, NO_PAD_CTRL) |
| 1636 | #define MX53_PAD_EIM_EB2__ECSPI1_SS0 (_MX53_PAD_EIM_EB2__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 462 | #define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK IOMUX_PAD(0x438, 0x10C, 7, __NA_, 0, NO_PAD_CTRL) |
| 1637 | #define MX53_PAD_EIM_EB2__I2C2_SCL (_MX53_PAD_EIM_EB2__I2C2_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C)) | 463 | #define MX53_PAD_EIM_A25__EMI_WEIM_A_25 IOMUX_PAD(0x458, 0x110, 0, __NA_, 0, NO_PAD_CTRL) |
| 1638 | #define MX53_PAD_EIM_D16__EMI_WEIM_D_16 (_MX53_PAD_EIM_D16__EMI_WEIM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 464 | #define MX53_PAD_EIM_A25__GPIO5_2 IOMUX_PAD(0x458, 0x110, 1, __NA_, 0, NO_PAD_CTRL) |
| 1639 | #define MX53_PAD_EIM_D16__GPIO3_16 (_MX53_PAD_EIM_D16__GPIO3_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 465 | #define MX53_PAD_EIM_A25__ECSPI2_RDY IOMUX_PAD(0x458, 0x110, 2, __NA_, 0, NO_PAD_CTRL) |
| 1640 | #define MX53_PAD_EIM_D16__IPU_DI0_PIN5 (_MX53_PAD_EIM_D16__IPU_DI0_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 466 | #define MX53_PAD_EIM_A25__IPU_DI1_PIN12 IOMUX_PAD(0x458, 0x110, 3, __NA_, 0, NO_PAD_CTRL) |
| 1641 | #define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK (_MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 467 | #define MX53_PAD_EIM_A25__CSPI_SS1 IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, NO_PAD_CTRL) |
| 1642 | #define MX53_PAD_EIM_D16__ECSPI1_SCLK (_MX53_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 468 | #define MX53_PAD_EIM_A25__IPU_DI0_D1_CS IOMUX_PAD(0x458, 0x110, 6, __NA_, 0, NO_PAD_CTRL) |
| 1643 | #define MX53_PAD_EIM_D16__I2C2_SDA (_MX53_PAD_EIM_D16__I2C2_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C)) | 469 | #define MX53_PAD_EIM_A25__USBPHY1_BISTOK IOMUX_PAD(0x458, 0x110, 7, __NA_, 0, NO_PAD_CTRL) |
| 1644 | #define MX53_PAD_EIM_D17__EMI_WEIM_D_17 (_MX53_PAD_EIM_D17__EMI_WEIM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 470 | #define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 IOMUX_PAD(0x45C, 0x114, 0, __NA_, 0, NO_PAD_CTRL) |
| 1645 | #define MX53_PAD_EIM_D17__GPIO3_17 (_MX53_PAD_EIM_D17__GPIO3_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 471 | #define MX53_PAD_EIM_EB2__GPIO2_30 IOMUX_PAD(0x45C, 0x114, 1, __NA_, 0, NO_PAD_CTRL) |
| 1646 | #define MX53_PAD_EIM_D17__IPU_DI0_PIN6 (_MX53_PAD_EIM_D17__IPU_DI0_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 472 | #define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, NO_PAD_CTRL) |
| 1647 | #define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN (_MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL)) | 473 | #define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS IOMUX_PAD(0x45C, 0x114, 3, __NA_, 0, NO_PAD_CTRL) |
| 1648 | #define MX53_PAD_EIM_D17__ECSPI1_MISO (_MX53_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 474 | #define MX53_PAD_EIM_EB2__ECSPI1_SS0 IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, NO_PAD_CTRL) |
| 1649 | #define MX53_PAD_EIM_D17__I2C3_SCL (_MX53_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C)) | 475 | #define MX53_PAD_EIM_EB2__I2C2_SCL IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, NO_PAD_CTRL) |
| 1650 | #define MX53_PAD_EIM_D18__EMI_WEIM_D_18 (_MX53_PAD_EIM_D18__EMI_WEIM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 476 | #define MX53_PAD_EIM_D16__EMI_WEIM_D_16 IOMUX_PAD(0x460, 0x118, 0, __NA_, 0, NO_PAD_CTRL) |
| 1651 | #define MX53_PAD_EIM_D18__GPIO3_18 (_MX53_PAD_EIM_D18__GPIO3_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 477 | #define MX53_PAD_EIM_D16__GPIO3_16 IOMUX_PAD(0x460, 0x118, 1, __NA_, 0, NO_PAD_CTRL) |
| 1652 | #define MX53_PAD_EIM_D18__IPU_DI0_PIN7 (_MX53_PAD_EIM_D18__IPU_DI0_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 478 | #define MX53_PAD_EIM_D16__IPU_DI0_PIN5 IOMUX_PAD(0x460, 0x118, 2, __NA_, 0, NO_PAD_CTRL) |
| 1653 | #define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO (_MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 479 | #define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK IOMUX_PAD(0x460, 0x118, 3, __NA_, 0, NO_PAD_CTRL) |
| 1654 | #define MX53_PAD_EIM_D18__ECSPI1_MOSI (_MX53_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) | 480 | #define MX53_PAD_EIM_D16__ECSPI1_SCLK IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, NO_PAD_CTRL) |
| 1655 | #define MX53_PAD_EIM_D18__I2C3_SDA (_MX53_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C)) | 481 | #define MX53_PAD_EIM_D16__I2C2_SDA IOMUX_PAD(0x460, 0x118, 5 | IOMUX_CONFIG_SION, 0x820, 1, NO_PAD_CTRL) |
| 1656 | #define MX53_PAD_EIM_D18__IPU_DI1_D0_CS (_MX53_PAD_EIM_D18__IPU_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 482 | #define MX53_PAD_EIM_D17__EMI_WEIM_D_17 IOMUX_PAD(0x464, 0x11C, 0, __NA_, 0, NO_PAD_CTRL) |
| 1657 | #define MX53_PAD_EIM_D19__EMI_WEIM_D_19 (_MX53_PAD_EIM_D19__EMI_WEIM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 483 | #define MX53_PAD_EIM_D17__GPIO3_17 IOMUX_PAD(0x464, 0x11C, 1, __NA_, 0, NO_PAD_CTRL) |
| 1658 | #define MX53_PAD_EIM_D19__GPIO3_19 (_MX53_PAD_EIM_D19__GPIO3_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 484 | #define MX53_PAD_EIM_D17__IPU_DI0_PIN6 IOMUX_PAD(0x464, 0x11C, 2, __NA_, 0, NO_PAD_CTRL) |
| 1659 | #define MX53_PAD_EIM_D19__IPU_DI0_PIN8 (_MX53_PAD_EIM_D19__IPU_DI0_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 485 | #define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, NO_PAD_CTRL) |
| 1660 | #define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS (_MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 486 | #define MX53_PAD_EIM_D17__ECSPI1_MISO IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, NO_PAD_CTRL) |
| 1661 | #define MX53_PAD_EIM_D19__ECSPI1_SS1 (_MX53_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 487 | #define MX53_PAD_EIM_D17__I2C3_SCL IOMUX_PAD(0x464, 0x11C, 5 | IOMUX_CONFIG_SION, 0x824, 0, NO_PAD_CTRL) |
| 1662 | #define MX53_PAD_EIM_D19__EPIT1_EPITO (_MX53_PAD_EIM_D19__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 488 | #define MX53_PAD_EIM_D18__EMI_WEIM_D_18 IOMUX_PAD(0x468, 0x120, 0, __NA_, 0, NO_PAD_CTRL) |
| 1663 | #define MX53_PAD_EIM_D19__UART1_CTS (_MX53_PAD_EIM_D19__UART1_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 489 | #define MX53_PAD_EIM_D18__GPIO3_18 IOMUX_PAD(0x468, 0x120, 1, __NA_, 0, NO_PAD_CTRL) |
| 1664 | #define MX53_PAD_EIM_D19__USBOH3_USBH2_OC (_MX53_PAD_EIM_D19__USBOH3_USBH2_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 490 | #define MX53_PAD_EIM_D18__IPU_DI0_PIN7 IOMUX_PAD(0x468, 0x120, 2, __NA_, 0, NO_PAD_CTRL) |
| 1665 | #define MX53_PAD_EIM_D20__EMI_WEIM_D_20 (_MX53_PAD_EIM_D20__EMI_WEIM_D_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 491 | #define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, NO_PAD_CTRL) |
| 1666 | #define MX53_PAD_EIM_D20__GPIO3_20 (_MX53_PAD_EIM_D20__GPIO3_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 492 | #define MX53_PAD_EIM_D18__ECSPI1_MOSI IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, NO_PAD_CTRL) |
| 1667 | #define MX53_PAD_EIM_D20__IPU_DI0_PIN16 (_MX53_PAD_EIM_D20__IPU_DI0_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 493 | #define MX53_PAD_EIM_D18__I2C3_SDA IOMUX_PAD(0x468, 0x120, 5 | IOMUX_CONFIG_SION, 0x828, 0, NO_PAD_CTRL) |
| 1668 | #define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS (_MX53_PAD_EIM_D20__IPU_SER_DISP0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 494 | #define MX53_PAD_EIM_D18__IPU_DI1_D0_CS IOMUX_PAD(0x468, 0x120, 6, __NA_, 0, NO_PAD_CTRL) |
| 1669 | #define MX53_PAD_EIM_D20__CSPI_SS0 (_MX53_PAD_EIM_D20__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 495 | #define MX53_PAD_EIM_D19__EMI_WEIM_D_19 IOMUX_PAD(0x46C, 0x124, 0, __NA_, 0, NO_PAD_CTRL) |
| 1670 | #define MX53_PAD_EIM_D20__EPIT2_EPITO (_MX53_PAD_EIM_D20__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 496 | #define MX53_PAD_EIM_D19__GPIO3_19 IOMUX_PAD(0x46C, 0x124, 1, __NA_, 0, NO_PAD_CTRL) |
| 1671 | #define MX53_PAD_EIM_D20__UART1_RTS (_MX53_PAD_EIM_D20__UART1_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 497 | #define MX53_PAD_EIM_D19__IPU_DI0_PIN8 IOMUX_PAD(0x46C, 0x124, 2, __NA_, 0, NO_PAD_CTRL) |
| 1672 | #define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR (_MX53_PAD_EIM_D20__USBOH3_USBH2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) | 498 | #define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS IOMUX_PAD(0x46C, 0x124, 3, __NA_, 0, NO_PAD_CTRL) |
| 1673 | #define MX53_PAD_EIM_D21__EMI_WEIM_D_21 (_MX53_PAD_EIM_D21__EMI_WEIM_D_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 499 | #define MX53_PAD_EIM_D19__ECSPI1_SS1 IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, NO_PAD_CTRL) |
| 1674 | #define MX53_PAD_EIM_D21__GPIO3_21 (_MX53_PAD_EIM_D21__GPIO3_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 500 | #define MX53_PAD_EIM_D19__EPIT1_EPITO IOMUX_PAD(0x46C, 0x124, 5, __NA_, 0, NO_PAD_CTRL) |
| 1675 | #define MX53_PAD_EIM_D21__IPU_DI0_PIN17 (_MX53_PAD_EIM_D21__IPU_DI0_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 501 | #define MX53_PAD_EIM_D19__UART1_CTS IOMUX_PAD(0x46C, 0x124, 6, __NA_, 0, MX53_UART_PAD_CTRL) |
| 1676 | #define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK (_MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 502 | #define MX53_PAD_EIM_D19__USBOH3_USBH2_OC IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, NO_PAD_CTRL) |
| 1677 | #define MX53_PAD_EIM_D21__CSPI_SCLK (_MX53_PAD_EIM_D21__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 503 | #define MX53_PAD_EIM_D20__EMI_WEIM_D_20 IOMUX_PAD(0x470, 0x128, 0, __NA_, 0, NO_PAD_CTRL) |
| 1678 | #define MX53_PAD_EIM_D21__I2C1_SCL (_MX53_PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C)) | 504 | #define MX53_PAD_EIM_D20__GPIO3_20 IOMUX_PAD(0x470, 0x128, 1, __NA_, 0, NO_PAD_CTRL) |
| 1679 | #define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC (_MX53_PAD_EIM_D21__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 505 | #define MX53_PAD_EIM_D20__IPU_DI0_PIN16 IOMUX_PAD(0x470, 0x128, 2, __NA_, 0, NO_PAD_CTRL) |
| 1680 | #define MX53_PAD_EIM_D22__EMI_WEIM_D_22 (_MX53_PAD_EIM_D22__EMI_WEIM_D_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 506 | #define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS IOMUX_PAD(0x470, 0x128, 3, __NA_, 0, NO_PAD_CTRL) |
| 1681 | #define MX53_PAD_EIM_D22__GPIO3_22 (_MX53_PAD_EIM_D22__GPIO3_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 507 | #define MX53_PAD_EIM_D20__CSPI_SS0 IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, NO_PAD_CTRL) |
| 1682 | #define MX53_PAD_EIM_D22__IPU_DI0_PIN1 (_MX53_PAD_EIM_D22__IPU_DI0_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 508 | #define MX53_PAD_EIM_D20__EPIT2_EPITO IOMUX_PAD(0x470, 0x128, 5, __NA_, 0, NO_PAD_CTRL) |
| 1683 | #define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN (_MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL)) | 509 | #define MX53_PAD_EIM_D20__UART1_RTS IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, MX53_UART_PAD_CTRL) |
| 1684 | #define MX53_PAD_EIM_D22__CSPI_MISO (_MX53_PAD_EIM_D22__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 510 | #define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR IOMUX_PAD(0x470, 0x128, 7, __NA_, 0, NO_PAD_CTRL) |
| 1685 | #define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR (_MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) | 511 | #define MX53_PAD_EIM_D21__EMI_WEIM_D_21 IOMUX_PAD(0x474, 0x12C, 0, __NA_, 0, NO_PAD_CTRL) |
| 1686 | #define MX53_PAD_EIM_D23__EMI_WEIM_D_23 (_MX53_PAD_EIM_D23__EMI_WEIM_D_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 512 | #define MX53_PAD_EIM_D21__GPIO3_21 IOMUX_PAD(0x474, 0x12C, 1, __NA_, 0, NO_PAD_CTRL) |
| 1687 | #define MX53_PAD_EIM_D23__GPIO3_23 (_MX53_PAD_EIM_D23__GPIO3_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 513 | #define MX53_PAD_EIM_D21__IPU_DI0_PIN17 IOMUX_PAD(0x474, 0x12C, 2, __NA_, 0, NO_PAD_CTRL) |
| 1688 | #define MX53_PAD_EIM_D23__UART3_CTS (_MX53_PAD_EIM_D23__UART3_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 514 | #define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK IOMUX_PAD(0x474, 0x12C, 3, __NA_, 0, NO_PAD_CTRL) |
| 1689 | #define MX53_PAD_EIM_D23__UART1_DCD (_MX53_PAD_EIM_D23__UART1_DCD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 515 | #define MX53_PAD_EIM_D21__CSPI_SCLK IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, NO_PAD_CTRL) |
| 1690 | #define MX53_PAD_EIM_D23__IPU_DI0_D0_CS (_MX53_PAD_EIM_D23__IPU_DI0_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 516 | #define MX53_PAD_EIM_D21__I2C1_SCL IOMUX_PAD(0x474, 0x12C, 5 | IOMUX_CONFIG_SION, 0x814, 1, NO_PAD_CTRL) |
| 1691 | #define MX53_PAD_EIM_D23__IPU_DI1_PIN2 (_MX53_PAD_EIM_D23__IPU_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 517 | #define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, NO_PAD_CTRL) |
| 1692 | #define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN (_MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) | 518 | #define MX53_PAD_EIM_D22__EMI_WEIM_D_22 IOMUX_PAD(0x478, 0x130, 0, __NA_, 0, NO_PAD_CTRL) |
| 1693 | #define MX53_PAD_EIM_D23__IPU_DI1_PIN14 (_MX53_PAD_EIM_D23__IPU_DI1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 519 | #define MX53_PAD_EIM_D22__GPIO3_22 IOMUX_PAD(0x478, 0x130, 1, __NA_, 0, NO_PAD_CTRL) |
| 1694 | #define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 (_MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 520 | #define MX53_PAD_EIM_D22__IPU_DI0_PIN1 IOMUX_PAD(0x478, 0x130, 2, __NA_, 0, NO_PAD_CTRL) |
| 1695 | #define MX53_PAD_EIM_EB3__GPIO2_31 (_MX53_PAD_EIM_EB3__GPIO2_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 521 | #define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, NO_PAD_CTRL) |
| 1696 | #define MX53_PAD_EIM_EB3__UART3_RTS (_MX53_PAD_EIM_EB3__UART3_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 522 | #define MX53_PAD_EIM_D22__CSPI_MISO IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, NO_PAD_CTRL) |
| 1697 | #define MX53_PAD_EIM_EB3__UART1_RI (_MX53_PAD_EIM_EB3__UART1_RI | MUX_PAD_CTRL(NO_PAD_CTRL)) | 523 | #define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR IOMUX_PAD(0x478, 0x130, 6, __NA_, 0, NO_PAD_CTRL) |
| 1698 | #define MX53_PAD_EIM_EB3__IPU_DI1_PIN3 (_MX53_PAD_EIM_EB3__IPU_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 524 | #define MX53_PAD_EIM_D23__EMI_WEIM_D_23 IOMUX_PAD(0x47C, 0x134, 0, __NA_, 0, NO_PAD_CTRL) |
| 1699 | #define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC (_MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 525 | #define MX53_PAD_EIM_D23__GPIO3_23 IOMUX_PAD(0x47C, 0x134, 1, __NA_, 0, NO_PAD_CTRL) |
| 1700 | #define MX53_PAD_EIM_EB3__IPU_DI1_PIN16 (_MX53_PAD_EIM_EB3__IPU_DI1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 526 | #define MX53_PAD_EIM_D23__UART3_CTS IOMUX_PAD(0x47C, 0x134, 2, __NA_, 0, MX53_UART_PAD_CTRL) |
| 1701 | #define MX53_PAD_EIM_D24__EMI_WEIM_D_24 (_MX53_PAD_EIM_D24__EMI_WEIM_D_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 527 | #define MX53_PAD_EIM_D23__UART1_DCD IOMUX_PAD(0x47C, 0x134, 3, __NA_, 0, NO_PAD_CTRL) |
| 1702 | #define MX53_PAD_EIM_D24__GPIO3_24 (_MX53_PAD_EIM_D24__GPIO3_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 528 | #define MX53_PAD_EIM_D23__IPU_DI0_D0_CS IOMUX_PAD(0x47C, 0x134, 4, __NA_, 0, NO_PAD_CTRL) |
| 1703 | #define MX53_PAD_EIM_D24__UART3_TXD_MUX (_MX53_PAD_EIM_D24__UART3_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 529 | #define MX53_PAD_EIM_D23__IPU_DI1_PIN2 IOMUX_PAD(0x47C, 0x134, 5, __NA_, 0, NO_PAD_CTRL) |
| 1704 | #define MX53_PAD_EIM_D24__ECSPI1_SS2 (_MX53_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 530 | #define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, NO_PAD_CTRL) |
| 1705 | #define MX53_PAD_EIM_D24__CSPI_SS2 (_MX53_PAD_EIM_D24__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 531 | #define MX53_PAD_EIM_D23__IPU_DI1_PIN14 IOMUX_PAD(0x47C, 0x134, 7, __NA_, 0, NO_PAD_CTRL) |
| 1706 | #define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS (_MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 532 | #define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 IOMUX_PAD(0x480, 0x138, 0, __NA_, 0, NO_PAD_CTRL) |
| 1707 | #define MX53_PAD_EIM_D24__ECSPI2_SS2 (_MX53_PAD_EIM_D24__ECSPI2_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 533 | #define MX53_PAD_EIM_EB3__GPIO2_31 IOMUX_PAD(0x480, 0x138, 1, __NA_, 0, NO_PAD_CTRL) |
| 1708 | #define MX53_PAD_EIM_D24__UART1_DTR (_MX53_PAD_EIM_D24__UART1_DTR | MUX_PAD_CTRL(NO_PAD_CTRL)) | 534 | #define MX53_PAD_EIM_EB3__UART3_RTS IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, MX53_UART_PAD_CTRL) |
| 1709 | #define MX53_PAD_EIM_D25__EMI_WEIM_D_25 (_MX53_PAD_EIM_D25__EMI_WEIM_D_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 535 | #define MX53_PAD_EIM_EB3__UART1_RI IOMUX_PAD(0x480, 0x138, 3, __NA_, 0, NO_PAD_CTRL) |
| 1710 | #define MX53_PAD_EIM_D25__GPIO3_25 (_MX53_PAD_EIM_D25__GPIO3_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 536 | #define MX53_PAD_EIM_EB3__IPU_DI1_PIN3 IOMUX_PAD(0x480, 0x138, 5, __NA_, 0, NO_PAD_CTRL) |
| 1711 | #define MX53_PAD_EIM_D25__UART3_RXD_MUX (_MX53_PAD_EIM_D25__UART3_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 537 | #define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, NO_PAD_CTRL) |
| 1712 | #define MX53_PAD_EIM_D25__ECSPI1_SS3 (_MX53_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 538 | #define MX53_PAD_EIM_EB3__IPU_DI1_PIN16 IOMUX_PAD(0x480, 0x138, 7, __NA_, 0, NO_PAD_CTRL) |
| 1713 | #define MX53_PAD_EIM_D25__CSPI_SS3 (_MX53_PAD_EIM_D25__CSPI_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 539 | #define MX53_PAD_EIM_D24__EMI_WEIM_D_24 IOMUX_PAD(0x484, 0x13C, 0, __NA_, 0, NO_PAD_CTRL) |
| 1714 | #define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC (_MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 540 | #define MX53_PAD_EIM_D24__GPIO3_24 IOMUX_PAD(0x484, 0x13C, 1, __NA_, 0, NO_PAD_CTRL) |
| 1715 | #define MX53_PAD_EIM_D25__ECSPI2_SS3 (_MX53_PAD_EIM_D25__ECSPI2_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 541 | #define MX53_PAD_EIM_D24__UART3_TXD_MUX IOMUX_PAD(0x484, 0x13C, 2, __NA_, 0, MX53_UART_PAD_CTRL) |
| 1716 | #define MX53_PAD_EIM_D25__UART1_DSR (_MX53_PAD_EIM_D25__UART1_DSR | MUX_PAD_CTRL(NO_PAD_CTRL)) | 542 | #define MX53_PAD_EIM_D24__ECSPI1_SS2 IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, NO_PAD_CTRL) |
| 1717 | #define MX53_PAD_EIM_D26__EMI_WEIM_D_26 (_MX53_PAD_EIM_D26__EMI_WEIM_D_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 543 | #define MX53_PAD_EIM_D24__CSPI_SS2 IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, NO_PAD_CTRL) |
| 1718 | #define MX53_PAD_EIM_D26__GPIO3_26 (_MX53_PAD_EIM_D26__GPIO3_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 544 | #define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, NO_PAD_CTRL) |
| 1719 | #define MX53_PAD_EIM_D26__UART2_TXD_MUX (_MX53_PAD_EIM_D26__UART2_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 545 | #define MX53_PAD_EIM_D24__ECSPI2_SS2 IOMUX_PAD(0x484, 0x13C, 6, __NA_, 0, NO_PAD_CTRL) |
| 1720 | #define MX53_PAD_EIM_D26__FIRI_RXD (_MX53_PAD_EIM_D26__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 546 | #define MX53_PAD_EIM_D24__UART1_DTR IOMUX_PAD(0x484, 0x13C, 7, __NA_, 0, NO_PAD_CTRL) |
| 1721 | #define MX53_PAD_EIM_D26__IPU_CSI0_D_1 (_MX53_PAD_EIM_D26__IPU_CSI0_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 547 | #define MX53_PAD_EIM_D25__EMI_WEIM_D_25 IOMUX_PAD(0x488, 0x140, 0, __NA_, 0, NO_PAD_CTRL) |
| 1722 | #define MX53_PAD_EIM_D26__IPU_DI1_PIN11 (_MX53_PAD_EIM_D26__IPU_DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 548 | #define MX53_PAD_EIM_D25__GPIO3_25 IOMUX_PAD(0x488, 0x140, 1, __NA_, 0, NO_PAD_CTRL) |
| 1723 | #define MX53_PAD_EIM_D26__IPU_SISG_2 (_MX53_PAD_EIM_D26__IPU_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 549 | #define MX53_PAD_EIM_D25__UART3_RXD_MUX IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, MX53_UART_PAD_CTRL) |
| 1724 | #define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 (_MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 550 | #define MX53_PAD_EIM_D25__ECSPI1_SS3 IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, NO_PAD_CTRL) |
| 1725 | #define MX53_PAD_EIM_D27__EMI_WEIM_D_27 (_MX53_PAD_EIM_D27__EMI_WEIM_D_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 551 | #define MX53_PAD_EIM_D25__CSPI_SS3 IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, NO_PAD_CTRL) |
| 1726 | #define MX53_PAD_EIM_D27__GPIO3_27 (_MX53_PAD_EIM_D27__GPIO3_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 552 | #define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, NO_PAD_CTRL) |
| 1727 | #define MX53_PAD_EIM_D27__UART2_RXD_MUX (_MX53_PAD_EIM_D27__UART2_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 553 | #define MX53_PAD_EIM_D25__ECSPI2_SS3 IOMUX_PAD(0x488, 0x140, 6, __NA_, 0, NO_PAD_CTRL) |
| 1728 | #define MX53_PAD_EIM_D27__FIRI_TXD (_MX53_PAD_EIM_D27__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 554 | #define MX53_PAD_EIM_D25__UART1_DSR IOMUX_PAD(0x488, 0x140, 7, __NA_, 0, NO_PAD_CTRL) |
| 1729 | #define MX53_PAD_EIM_D27__IPU_CSI0_D_0 (_MX53_PAD_EIM_D27__IPU_CSI0_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 555 | #define MX53_PAD_EIM_D26__EMI_WEIM_D_26 IOMUX_PAD(0x48C, 0x144, 0, __NA_, 0, NO_PAD_CTRL) |
| 1730 | #define MX53_PAD_EIM_D27__IPU_DI1_PIN13 (_MX53_PAD_EIM_D27__IPU_DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 556 | #define MX53_PAD_EIM_D26__GPIO3_26 IOMUX_PAD(0x48C, 0x144, 1, __NA_, 0, NO_PAD_CTRL) |
| 1731 | #define MX53_PAD_EIM_D27__IPU_SISG_3 (_MX53_PAD_EIM_D27__IPU_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 557 | #define MX53_PAD_EIM_D26__UART2_TXD_MUX IOMUX_PAD(0x48C, 0x144, 2, __NA_, 0, MX53_UART_PAD_CTRL) |
| 1732 | #define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 (_MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 558 | #define MX53_PAD_EIM_D26__FIRI_RXD IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, NO_PAD_CTRL) |
| 1733 | #define MX53_PAD_EIM_D28__EMI_WEIM_D_28 (_MX53_PAD_EIM_D28__EMI_WEIM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 559 | #define MX53_PAD_EIM_D26__IPU_CSI0_D_1 IOMUX_PAD(0x48C, 0x144, 4, __NA_, 0, NO_PAD_CTRL) |
| 1734 | #define MX53_PAD_EIM_D28__GPIO3_28 (_MX53_PAD_EIM_D28__GPIO3_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 560 | #define MX53_PAD_EIM_D26__IPU_DI1_PIN11 IOMUX_PAD(0x48C, 0x144, 5, __NA_, 0, NO_PAD_CTRL) |
| 1735 | #define MX53_PAD_EIM_D28__UART2_CTS (_MX53_PAD_EIM_D28__UART2_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 561 | #define MX53_PAD_EIM_D26__IPU_SISG_2 IOMUX_PAD(0x48C, 0x144, 6, __NA_, 0, NO_PAD_CTRL) |
| 1736 | #define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO (_MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 562 | #define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 IOMUX_PAD(0x48C, 0x144, 7, __NA_, 0, NO_PAD_CTRL) |
| 1737 | #define MX53_PAD_EIM_D28__CSPI_MOSI (_MX53_PAD_EIM_D28__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) | 563 | #define MX53_PAD_EIM_D27__EMI_WEIM_D_27 IOMUX_PAD(0x490, 0x148, 0, __NA_, 0, NO_PAD_CTRL) |
| 1738 | #define MX53_PAD_EIM_D28__I2C1_SDA (_MX53_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C)) | 564 | #define MX53_PAD_EIM_D27__GPIO3_27 IOMUX_PAD(0x490, 0x148, 1, __NA_, 0, NO_PAD_CTRL) |
| 1739 | #define MX53_PAD_EIM_D28__IPU_EXT_TRIG (_MX53_PAD_EIM_D28__IPU_EXT_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL)) | 565 | #define MX53_PAD_EIM_D27__UART2_RXD_MUX IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, MX53_UART_PAD_CTRL) |
| 1740 | #define MX53_PAD_EIM_D28__IPU_DI0_PIN13 (_MX53_PAD_EIM_D28__IPU_DI0_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 566 | #define MX53_PAD_EIM_D27__FIRI_TXD IOMUX_PAD(0x490, 0x148, 3, __NA_, 0, NO_PAD_CTRL) |
| 1741 | #define MX53_PAD_EIM_D29__EMI_WEIM_D_29 (_MX53_PAD_EIM_D29__EMI_WEIM_D_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 567 | #define MX53_PAD_EIM_D27__IPU_CSI0_D_0 IOMUX_PAD(0x490, 0x148, 4, __NA_, 0, NO_PAD_CTRL) |
| 1742 | #define MX53_PAD_EIM_D29__GPIO3_29 (_MX53_PAD_EIM_D29__GPIO3_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 568 | #define MX53_PAD_EIM_D27__IPU_DI1_PIN13 IOMUX_PAD(0x490, 0x148, 5, __NA_, 0, NO_PAD_CTRL) |
| 1743 | #define MX53_PAD_EIM_D29__UART2_RTS (_MX53_PAD_EIM_D29__UART2_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 569 | #define MX53_PAD_EIM_D27__IPU_SISG_3 IOMUX_PAD(0x490, 0x148, 6, __NA_, 0, NO_PAD_CTRL) |
| 1744 | #define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS (_MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 570 | #define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 IOMUX_PAD(0x490, 0x148, 7, __NA_, 0, NO_PAD_CTRL) |
| 1745 | #define MX53_PAD_EIM_D29__CSPI_SS0 (_MX53_PAD_EIM_D29__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 571 | #define MX53_PAD_EIM_D28__EMI_WEIM_D_28 IOMUX_PAD(0x494, 0x14C, 0, __NA_, 0, NO_PAD_CTRL) |
| 1746 | #define MX53_PAD_EIM_D29__IPU_DI1_PIN15 (_MX53_PAD_EIM_D29__IPU_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 572 | #define MX53_PAD_EIM_D28__GPIO3_28 IOMUX_PAD(0x494, 0x14C, 1, __NA_, 0, NO_PAD_CTRL) |
| 1747 | #define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC (_MX53_PAD_EIM_D29__IPU_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 573 | #define MX53_PAD_EIM_D28__UART2_CTS IOMUX_PAD(0x494, 0x14C, 2, __NA_, 0, MX53_UART_PAD_CTRL) |
| 1748 | #define MX53_PAD_EIM_D29__IPU_DI0_PIN14 (_MX53_PAD_EIM_D29__IPU_DI0_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 574 | #define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, NO_PAD_CTRL) |
| 1749 | #define MX53_PAD_EIM_D30__EMI_WEIM_D_30 (_MX53_PAD_EIM_D30__EMI_WEIM_D_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 575 | #define MX53_PAD_EIM_D28__CSPI_MOSI IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, NO_PAD_CTRL) |
| 1750 | #define MX53_PAD_EIM_D30__GPIO3_30 (_MX53_PAD_EIM_D30__GPIO3_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 576 | #define MX53_PAD_EIM_D28__I2C1_SDA IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, PAD_CTRL_I2C) |
| 1751 | #define MX53_PAD_EIM_D30__UART3_CTS (_MX53_PAD_EIM_D30__UART3_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 577 | #define MX53_PAD_EIM_D28__IPU_EXT_TRIG IOMUX_PAD(0x494, 0x14C, 6, __NA_, 0, NO_PAD_CTRL) |
| 1752 | #define MX53_PAD_EIM_D30__IPU_CSI0_D_3 (_MX53_PAD_EIM_D30__IPU_CSI0_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 578 | #define MX53_PAD_EIM_D28__IPU_DI0_PIN13 IOMUX_PAD(0x494, 0x14C, 7, __NA_, 0, NO_PAD_CTRL) |
| 1753 | #define MX53_PAD_EIM_D30__IPU_DI0_PIN11 (_MX53_PAD_EIM_D30__IPU_DI0_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 579 | #define MX53_PAD_EIM_D29__EMI_WEIM_D_29 IOMUX_PAD(0x498, 0x150, 0, __NA_, 0, NO_PAD_CTRL) |
| 1754 | #define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 (_MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 580 | #define MX53_PAD_EIM_D29__GPIO3_29 IOMUX_PAD(0x498, 0x150, 1, __NA_, 0, NO_PAD_CTRL) |
| 1755 | #define MX53_PAD_EIM_D30__USBOH3_USBH1_OC (_MX53_PAD_EIM_D30__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 581 | #define MX53_PAD_EIM_D29__UART2_RTS IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, MX53_UART_PAD_CTRL) |
| 1756 | #define MX53_PAD_EIM_D30__USBOH3_USBH2_OC (_MX53_PAD_EIM_D30__USBOH3_USBH2_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 582 | #define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS IOMUX_PAD(0x498, 0x150, 3, __NA_, 0, NO_PAD_CTRL) |
| 1757 | #define MX53_PAD_EIM_D31__EMI_WEIM_D_31 (_MX53_PAD_EIM_D31__EMI_WEIM_D_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 583 | #define MX53_PAD_EIM_D29__CSPI_SS0 IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, NO_PAD_CTRL) |
| 1758 | #define MX53_PAD_EIM_D31__GPIO3_31 (_MX53_PAD_EIM_D31__GPIO3_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 584 | #define MX53_PAD_EIM_D29__IPU_DI1_PIN15 IOMUX_PAD(0x498, 0x150, 5, __NA_, 0, NO_PAD_CTRL) |
| 1759 | #define MX53_PAD_EIM_D31__UART3_RTS (_MX53_PAD_EIM_D31__UART3_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 585 | #define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, NO_PAD_CTRL) |
| 1760 | #define MX53_PAD_EIM_D31__IPU_CSI0_D_2 (_MX53_PAD_EIM_D31__IPU_CSI0_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 586 | #define MX53_PAD_EIM_D29__IPU_DI0_PIN14 IOMUX_PAD(0x498, 0x150, 7, __NA_, 0, NO_PAD_CTRL) |
| 1761 | #define MX53_PAD_EIM_D31__IPU_DI0_PIN12 (_MX53_PAD_EIM_D31__IPU_DI0_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 587 | #define MX53_PAD_EIM_D30__EMI_WEIM_D_30 IOMUX_PAD(0x49C, 0x154, 0, __NA_, 0, NO_PAD_CTRL) |
| 1762 | #define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 (_MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 588 | #define MX53_PAD_EIM_D30__GPIO3_30 IOMUX_PAD(0x49C, 0x154, 1, __NA_, 0, NO_PAD_CTRL) |
| 1763 | #define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR (_MX53_PAD_EIM_D31__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) | 589 | #define MX53_PAD_EIM_D30__UART3_CTS IOMUX_PAD(0x49C, 0x154, 2, __NA_, 0, MX53_UART_PAD_CTRL) |
| 1764 | #define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR (_MX53_PAD_EIM_D31__USBOH3_USBH2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) | 590 | #define MX53_PAD_EIM_D30__IPU_CSI0_D_3 IOMUX_PAD(0x49C, 0x154, 3, __NA_, 0, NO_PAD_CTRL) |
| 1765 | #define MX53_PAD_EIM_A24__EMI_WEIM_A_24 (_MX53_PAD_EIM_A24__EMI_WEIM_A_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 591 | #define MX53_PAD_EIM_D30__IPU_DI0_PIN11 IOMUX_PAD(0x49C, 0x154, 4, __NA_, 0, NO_PAD_CTRL) |
| 1766 | #define MX53_PAD_EIM_A24__GPIO5_4 (_MX53_PAD_EIM_A24__GPIO5_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 592 | #define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 IOMUX_PAD(0x49C, 0x154, 5, __NA_, 0, NO_PAD_CTRL) |
| 1767 | #define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 (_MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 593 | #define MX53_PAD_EIM_D30__USBOH3_USBH1_OC IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, NO_PAD_CTRL) |
| 1768 | #define MX53_PAD_EIM_A24__IPU_CSI1_D_19 (_MX53_PAD_EIM_A24__IPU_CSI1_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 594 | #define MX53_PAD_EIM_D30__USBOH3_USBH2_OC IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, NO_PAD_CTRL) |
| 1769 | #define MX53_PAD_EIM_A24__IPU_SISG_2 (_MX53_PAD_EIM_A24__IPU_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 595 | #define MX53_PAD_EIM_D31__EMI_WEIM_D_31 IOMUX_PAD(0x4A0, 0x158, 0, __NA_, 0, NO_PAD_CTRL) |
| 1770 | #define MX53_PAD_EIM_A24__USBPHY2_BVALID (_MX53_PAD_EIM_A24__USBPHY2_BVALID | MUX_PAD_CTRL(NO_PAD_CTRL)) | 596 | #define MX53_PAD_EIM_D31__GPIO3_31 IOMUX_PAD(0x4A0, 0x158, 1, __NA_, 0, NO_PAD_CTRL) |
| 1771 | #define MX53_PAD_EIM_A23__EMI_WEIM_A_23 (_MX53_PAD_EIM_A23__EMI_WEIM_A_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 597 | #define MX53_PAD_EIM_D31__UART3_RTS IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, MX53_UART_PAD_CTRL) |
| 1772 | #define MX53_PAD_EIM_A23__GPIO6_6 (_MX53_PAD_EIM_A23__GPIO6_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 598 | #define MX53_PAD_EIM_D31__IPU_CSI0_D_2 IOMUX_PAD(0x4A0, 0x158, 3, __NA_, 0, NO_PAD_CTRL) |
| 1773 | #define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 (_MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 599 | #define MX53_PAD_EIM_D31__IPU_DI0_PIN12 IOMUX_PAD(0x4A0, 0x158, 4, __NA_, 0, NO_PAD_CTRL) |
| 1774 | #define MX53_PAD_EIM_A23__IPU_CSI1_D_18 (_MX53_PAD_EIM_A23__IPU_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 600 | #define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 IOMUX_PAD(0x4A0, 0x158, 5, __NA_, 0, NO_PAD_CTRL) |
| 1775 | #define MX53_PAD_EIM_A23__IPU_SISG_3 (_MX53_PAD_EIM_A23__IPU_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 601 | #define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR IOMUX_PAD(0x4A0, 0x158, 6, __NA_, 0, NO_PAD_CTRL) |
| 1776 | #define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION (_MX53_PAD_EIM_A23__USBPHY2_ENDSESSION | MUX_PAD_CTRL(NO_PAD_CTRL)) | 602 | #define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR IOMUX_PAD(0x4A0, 0x158, 7, __NA_, 0, NO_PAD_CTRL) |
| 1777 | #define MX53_PAD_EIM_A22__EMI_WEIM_A_22 (_MX53_PAD_EIM_A22__EMI_WEIM_A_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 603 | #define MX53_PAD_EIM_A24__EMI_WEIM_A_24 IOMUX_PAD(0x4A8, 0x15C, 0, __NA_, 0, NO_PAD_CTRL) |
| 1778 | #define MX53_PAD_EIM_A22__GPIO2_16 (_MX53_PAD_EIM_A22__GPIO2_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 604 | #define MX53_PAD_EIM_A24__GPIO5_4 IOMUX_PAD(0x4A8, 0x15C, 1, __NA_, 0, NO_PAD_CTRL) |
| 1779 | #define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 (_MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 605 | #define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 IOMUX_PAD(0x4A8, 0x15C, 2, __NA_, 0, NO_PAD_CTRL) |
| 1780 | #define MX53_PAD_EIM_A22__IPU_CSI1_D_17 (_MX53_PAD_EIM_A22__IPU_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 606 | #define MX53_PAD_EIM_A24__IPU_CSI1_D_19 IOMUX_PAD(0x4A8, 0x15C, 3, __NA_, 0, NO_PAD_CTRL) |
| 1781 | #define MX53_PAD_EIM_A22__SRC_BT_CFG1_7 (_MX53_PAD_EIM_A22__SRC_BT_CFG1_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 607 | #define MX53_PAD_EIM_A24__IPU_SISG_2 IOMUX_PAD(0x4A8, 0x15C, 6, __NA_, 0, NO_PAD_CTRL) |
| 1782 | #define MX53_PAD_EIM_A21__EMI_WEIM_A_21 (_MX53_PAD_EIM_A21__EMI_WEIM_A_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 608 | #define MX53_PAD_EIM_A24__USBPHY2_BVALID IOMUX_PAD(0x4A8, 0x15C, 7, __NA_, 0, NO_PAD_CTRL) |
| 1783 | #define MX53_PAD_EIM_A21__GPIO2_17 (_MX53_PAD_EIM_A21__GPIO2_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 609 | #define MX53_PAD_EIM_A23__EMI_WEIM_A_23 IOMUX_PAD(0x4AC, 0x160, 0, __NA_, 0, NO_PAD_CTRL) |
| 1784 | #define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 (_MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 610 | #define MX53_PAD_EIM_A23__GPIO6_6 IOMUX_PAD(0x4AC, 0x160, 1, __NA_, 0, NO_PAD_CTRL) |
| 1785 | #define MX53_PAD_EIM_A21__IPU_CSI1_D_16 (_MX53_PAD_EIM_A21__IPU_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 611 | #define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 IOMUX_PAD(0x4AC, 0x160, 2, __NA_, 0, NO_PAD_CTRL) |
| 1786 | #define MX53_PAD_EIM_A21__SRC_BT_CFG1_6 (_MX53_PAD_EIM_A21__SRC_BT_CFG1_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 612 | #define MX53_PAD_EIM_A23__IPU_CSI1_D_18 IOMUX_PAD(0x4AC, 0x160, 3, __NA_, 0, NO_PAD_CTRL) |
| 1787 | #define MX53_PAD_EIM_A20__EMI_WEIM_A_20 (_MX53_PAD_EIM_A20__EMI_WEIM_A_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 613 | #define MX53_PAD_EIM_A23__IPU_SISG_3 IOMUX_PAD(0x4AC, 0x160, 6, __NA_, 0, NO_PAD_CTRL) |
| 1788 | #define MX53_PAD_EIM_A20__GPIO2_18 (_MX53_PAD_EIM_A20__GPIO2_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 614 | #define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION IOMUX_PAD(0x4AC, 0x160, 7, __NA_, 0, NO_PAD_CTRL) |
| 1789 | #define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 (_MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 615 | #define MX53_PAD_EIM_A22__EMI_WEIM_A_22 IOMUX_PAD(0x4B0, 0x164, 0, __NA_, 0, NO_PAD_CTRL) |
| 1790 | #define MX53_PAD_EIM_A20__IPU_CSI1_D_15 (_MX53_PAD_EIM_A20__IPU_CSI1_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 616 | #define MX53_PAD_EIM_A22__GPIO2_16 IOMUX_PAD(0x4B0, 0x164, 1, __NA_, 0, NO_PAD_CTRL) |
| 1791 | #define MX53_PAD_EIM_A20__SRC_BT_CFG1_5 (_MX53_PAD_EIM_A20__SRC_BT_CFG1_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 617 | #define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 IOMUX_PAD(0x4B0, 0x164, 2, __NA_, 0, NO_PAD_CTRL) |
| 1792 | #define MX53_PAD_EIM_A19__EMI_WEIM_A_19 (_MX53_PAD_EIM_A19__EMI_WEIM_A_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 618 | #define MX53_PAD_EIM_A22__IPU_CSI1_D_17 IOMUX_PAD(0x4B0, 0x164, 3, __NA_, 0, NO_PAD_CTRL) |
| 1793 | #define MX53_PAD_EIM_A19__GPIO2_19 (_MX53_PAD_EIM_A19__GPIO2_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 619 | #define MX53_PAD_EIM_A22__SRC_BT_CFG1_7 IOMUX_PAD(0x4B0, 0x164, 7, __NA_, 0, NO_PAD_CTRL) |
| 1794 | #define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 (_MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 620 | #define MX53_PAD_EIM_A21__EMI_WEIM_A_21 IOMUX_PAD(0x4B4, 0x168, 0, __NA_, 0, NO_PAD_CTRL) |
| 1795 | #define MX53_PAD_EIM_A19__IPU_CSI1_D_14 (_MX53_PAD_EIM_A19__IPU_CSI1_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 621 | #define MX53_PAD_EIM_A21__GPIO2_17 IOMUX_PAD(0x4B4, 0x168, 1, __NA_, 0, NO_PAD_CTRL) |
| 1796 | #define MX53_PAD_EIM_A19__SRC_BT_CFG1_4 (_MX53_PAD_EIM_A19__SRC_BT_CFG1_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 622 | #define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 IOMUX_PAD(0x4B4, 0x168, 2, __NA_, 0, NO_PAD_CTRL) |
| 1797 | #define MX53_PAD_EIM_A18__EMI_WEIM_A_18 (_MX53_PAD_EIM_A18__EMI_WEIM_A_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 623 | #define MX53_PAD_EIM_A21__IPU_CSI1_D_16 IOMUX_PAD(0x4B4, 0x168, 3, __NA_, 0, NO_PAD_CTRL) |
| 1798 | #define MX53_PAD_EIM_A18__GPIO2_20 (_MX53_PAD_EIM_A18__GPIO2_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 624 | #define MX53_PAD_EIM_A21__SRC_BT_CFG1_6 IOMUX_PAD(0x4B4, 0x168, 7, __NA_, 0, NO_PAD_CTRL) |
| 1799 | #define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 (_MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 625 | #define MX53_PAD_EIM_A20__EMI_WEIM_A_20 IOMUX_PAD(0x4B8, 0x16C, 0, __NA_, 0, NO_PAD_CTRL) |
| 1800 | #define MX53_PAD_EIM_A18__IPU_CSI1_D_13 (_MX53_PAD_EIM_A18__IPU_CSI1_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 626 | #define MX53_PAD_EIM_A20__GPIO2_18 IOMUX_PAD(0x4B8, 0x16C, 1, __NA_, 0, NO_PAD_CTRL) |
| 1801 | #define MX53_PAD_EIM_A18__SRC_BT_CFG1_3 (_MX53_PAD_EIM_A18__SRC_BT_CFG1_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 627 | #define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 IOMUX_PAD(0x4B8, 0x16C, 2, __NA_, 0, NO_PAD_CTRL) |
| 1802 | #define MX53_PAD_EIM_A17__EMI_WEIM_A_17 (_MX53_PAD_EIM_A17__EMI_WEIM_A_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 628 | #define MX53_PAD_EIM_A20__IPU_CSI1_D_15 IOMUX_PAD(0x4B8, 0x16C, 3, __NA_, 0, NO_PAD_CTRL) |
| 1803 | #define MX53_PAD_EIM_A17__GPIO2_21 (_MX53_PAD_EIM_A17__GPIO2_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 629 | #define MX53_PAD_EIM_A20__SRC_BT_CFG1_5 IOMUX_PAD(0x4B8, 0x16C, 7, __NA_, 0, NO_PAD_CTRL) |
| 1804 | #define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 (_MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 630 | #define MX53_PAD_EIM_A19__EMI_WEIM_A_19 IOMUX_PAD(0x4BC, 0x170, 0, __NA_, 0, NO_PAD_CTRL) |
| 1805 | #define MX53_PAD_EIM_A17__IPU_CSI1_D_12 (_MX53_PAD_EIM_A17__IPU_CSI1_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 631 | #define MX53_PAD_EIM_A19__GPIO2_19 IOMUX_PAD(0x4BC, 0x170, 1, __NA_, 0, NO_PAD_CTRL) |
| 1806 | #define MX53_PAD_EIM_A17__SRC_BT_CFG1_2 (_MX53_PAD_EIM_A17__SRC_BT_CFG1_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 632 | #define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 IOMUX_PAD(0x4BC, 0x170, 2, __NA_, 0, NO_PAD_CTRL) |
| 1807 | #define MX53_PAD_EIM_A16__EMI_WEIM_A_16 (_MX53_PAD_EIM_A16__EMI_WEIM_A_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 633 | #define MX53_PAD_EIM_A19__IPU_CSI1_D_14 IOMUX_PAD(0x4BC, 0x170, 3, __NA_, 0, NO_PAD_CTRL) |
| 1808 | #define MX53_PAD_EIM_A16__GPIO2_22 (_MX53_PAD_EIM_A16__GPIO2_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 634 | #define MX53_PAD_EIM_A19__SRC_BT_CFG1_4 IOMUX_PAD(0x4BC, 0x170, 7, __NA_, 0, NO_PAD_CTRL) |
| 1809 | #define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK (_MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 635 | #define MX53_PAD_EIM_A18__EMI_WEIM_A_18 IOMUX_PAD(0x4C0, 0x174, 0, __NA_, 0, NO_PAD_CTRL) |
| 1810 | #define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK (_MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 636 | #define MX53_PAD_EIM_A18__GPIO2_20 IOMUX_PAD(0x4C0, 0x174, 1, __NA_, 0, NO_PAD_CTRL) |
| 1811 | #define MX53_PAD_EIM_A16__SRC_BT_CFG1_1 (_MX53_PAD_EIM_A16__SRC_BT_CFG1_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 637 | #define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 IOMUX_PAD(0x4C0, 0x174, 2, __NA_, 0, NO_PAD_CTRL) |
| 1812 | #define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 (_MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 638 | #define MX53_PAD_EIM_A18__IPU_CSI1_D_13 IOMUX_PAD(0x4C0, 0x174, 3, __NA_, 0, NO_PAD_CTRL) |
| 1813 | #define MX53_PAD_EIM_CS0__GPIO2_23 (_MX53_PAD_EIM_CS0__GPIO2_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 639 | #define MX53_PAD_EIM_A18__SRC_BT_CFG1_3 IOMUX_PAD(0x4C0, 0x174, 7, __NA_, 0, NO_PAD_CTRL) |
| 1814 | #define MX53_PAD_EIM_CS0__ECSPI2_SCLK (_MX53_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 640 | #define MX53_PAD_EIM_A17__EMI_WEIM_A_17 IOMUX_PAD(0x4C4, 0x178, 0, __NA_, 0, NO_PAD_CTRL) |
| 1815 | #define MX53_PAD_EIM_CS0__IPU_DI1_PIN5 (_MX53_PAD_EIM_CS0__IPU_DI1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 641 | #define MX53_PAD_EIM_A17__GPIO2_21 IOMUX_PAD(0x4C4, 0x178, 1, __NA_, 0, NO_PAD_CTRL) |
| 1816 | #define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 (_MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 642 | #define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 IOMUX_PAD(0x4C4, 0x178, 2, __NA_, 0, NO_PAD_CTRL) |
| 1817 | #define MX53_PAD_EIM_CS1__GPIO2_24 (_MX53_PAD_EIM_CS1__GPIO2_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 643 | #define MX53_PAD_EIM_A17__IPU_CSI1_D_12 IOMUX_PAD(0x4C4, 0x178, 3, __NA_, 0, NO_PAD_CTRL) |
| 1818 | #define MX53_PAD_EIM_CS1__ECSPI2_MOSI (_MX53_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) | 644 | #define MX53_PAD_EIM_A17__SRC_BT_CFG1_2 IOMUX_PAD(0x4C4, 0x178, 7, __NA_, 0, NO_PAD_CTRL) |
| 1819 | #define MX53_PAD_EIM_CS1__IPU_DI1_PIN6 (_MX53_PAD_EIM_CS1__IPU_DI1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 645 | #define MX53_PAD_EIM_A16__EMI_WEIM_A_16 IOMUX_PAD(0x4C8, 0x17C, 0, __NA_, 0, NO_PAD_CTRL) |
| 1820 | #define MX53_PAD_EIM_OE__EMI_WEIM_OE (_MX53_PAD_EIM_OE__EMI_WEIM_OE | MUX_PAD_CTRL(NO_PAD_CTRL)) | 646 | #define MX53_PAD_EIM_A16__GPIO2_22 IOMUX_PAD(0x4C8, 0x17C, 1, __NA_, 0, NO_PAD_CTRL) |
| 1821 | #define MX53_PAD_EIM_OE__GPIO2_25 (_MX53_PAD_EIM_OE__GPIO2_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 647 | #define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK IOMUX_PAD(0x4C8, 0x17C, 2, __NA_, 0, NO_PAD_CTRL) |
| 1822 | #define MX53_PAD_EIM_OE__ECSPI2_MISO (_MX53_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 648 | #define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK IOMUX_PAD(0x4C8, 0x17C, 3, __NA_, 0, NO_PAD_CTRL) |
| 1823 | #define MX53_PAD_EIM_OE__IPU_DI1_PIN7 (_MX53_PAD_EIM_OE__IPU_DI1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 649 | #define MX53_PAD_EIM_A16__SRC_BT_CFG1_1 IOMUX_PAD(0x4C8, 0x17C, 7, __NA_, 0, NO_PAD_CTRL) |
| 1824 | #define MX53_PAD_EIM_OE__USBPHY2_IDDIG (_MX53_PAD_EIM_OE__USBPHY2_IDDIG | MUX_PAD_CTRL(NO_PAD_CTRL)) | 650 | #define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 IOMUX_PAD(0x4CC, 0x180, 0, __NA_, 0, NO_PAD_CTRL) |
| 1825 | #define MX53_PAD_EIM_RW__EMI_WEIM_RW (_MX53_PAD_EIM_RW__EMI_WEIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL)) | 651 | #define MX53_PAD_EIM_CS0__GPIO2_23 IOMUX_PAD(0x4CC, 0x180, 1, __NA_, 0, NO_PAD_CTRL) |
| 1826 | #define MX53_PAD_EIM_RW__GPIO2_26 (_MX53_PAD_EIM_RW__GPIO2_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 652 | #define MX53_PAD_EIM_CS0__ECSPI2_SCLK IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, NO_PAD_CTRL) |
| 1827 | #define MX53_PAD_EIM_RW__ECSPI2_SS0 (_MX53_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 653 | #define MX53_PAD_EIM_CS0__IPU_DI1_PIN5 IOMUX_PAD(0x4CC, 0x180, 3, __NA_, 0, NO_PAD_CTRL) |
| 1828 | #define MX53_PAD_EIM_RW__IPU_DI1_PIN8 (_MX53_PAD_EIM_RW__IPU_DI1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 654 | #define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 IOMUX_PAD(0x4D0, 0x184, 0, __NA_, 0, NO_PAD_CTRL) |
| 1829 | #define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT (_MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT | MUX_PAD_CTRL(NO_PAD_CTRL)) | 655 | #define MX53_PAD_EIM_CS1__GPIO2_24 IOMUX_PAD(0x4D0, 0x184, 1, __NA_, 0, NO_PAD_CTRL) |
| 1830 | #define MX53_PAD_EIM_LBA__EMI_WEIM_LBA (_MX53_PAD_EIM_LBA__EMI_WEIM_LBA | MUX_PAD_CTRL(NO_PAD_CTRL)) | 656 | #define MX53_PAD_EIM_CS1__ECSPI2_MOSI IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, NO_PAD_CTRL) |
| 1831 | #define MX53_PAD_EIM_LBA__GPIO2_27 (_MX53_PAD_EIM_LBA__GPIO2_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 657 | #define MX53_PAD_EIM_CS1__IPU_DI1_PIN6 IOMUX_PAD(0x4D0, 0x184, 3, __NA_, 0, NO_PAD_CTRL) |
| 1832 | #define MX53_PAD_EIM_LBA__ECSPI2_SS1 (_MX53_PAD_EIM_LBA__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 658 | #define MX53_PAD_EIM_OE__EMI_WEIM_OE IOMUX_PAD(0x4D4, 0x188, 0, __NA_, 0, NO_PAD_CTRL) |
| 1833 | #define MX53_PAD_EIM_LBA__IPU_DI1_PIN17 (_MX53_PAD_EIM_LBA__IPU_DI1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 659 | #define MX53_PAD_EIM_OE__GPIO2_25 IOMUX_PAD(0x4D4, 0x188, 1, __NA_, 0, NO_PAD_CTRL) |
| 1834 | #define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 (_MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 660 | #define MX53_PAD_EIM_OE__ECSPI2_MISO IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, NO_PAD_CTRL) |
| 1835 | #define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 (_MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 661 | #define MX53_PAD_EIM_OE__IPU_DI1_PIN7 IOMUX_PAD(0x4D4, 0x188, 3, __NA_, 0, NO_PAD_CTRL) |
| 1836 | #define MX53_PAD_EIM_EB0__GPIO2_28 (_MX53_PAD_EIM_EB0__GPIO2_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 662 | #define MX53_PAD_EIM_OE__USBPHY2_IDDIG IOMUX_PAD(0x4D4, 0x188, 7, __NA_, 0, NO_PAD_CTRL) |
| 1837 | #define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 (_MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 663 | #define MX53_PAD_EIM_RW__EMI_WEIM_RW IOMUX_PAD(0x4D8, 0x18C, 0, __NA_, 0, NO_PAD_CTRL) |
| 1838 | #define MX53_PAD_EIM_EB0__IPU_CSI1_D_11 (_MX53_PAD_EIM_EB0__IPU_CSI1_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 664 | #define MX53_PAD_EIM_RW__GPIO2_26 IOMUX_PAD(0x4D8, 0x18C, 1, __NA_, 0, NO_PAD_CTRL) |
| 1839 | #define MX53_PAD_EIM_EB0__GPC_PMIC_RDY (_MX53_PAD_EIM_EB0__GPC_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) | 665 | #define MX53_PAD_EIM_RW__ECSPI2_SS0 IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, NO_PAD_CTRL) |
| 1840 | #define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 (_MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 666 | #define MX53_PAD_EIM_RW__IPU_DI1_PIN8 IOMUX_PAD(0x4D8, 0x18C, 3, __NA_, 0, NO_PAD_CTRL) |
| 1841 | #define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 (_MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 667 | #define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT IOMUX_PAD(0x4D8, 0x18C, 7, __NA_, 0, NO_PAD_CTRL) |
| 1842 | #define MX53_PAD_EIM_EB1__GPIO2_29 (_MX53_PAD_EIM_EB1__GPIO2_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 668 | #define MX53_PAD_EIM_LBA__EMI_WEIM_LBA IOMUX_PAD(0x4DC, 0x190, 0, __NA_, 0, NO_PAD_CTRL) |
| 1843 | #define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 (_MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 669 | #define MX53_PAD_EIM_LBA__GPIO2_27 IOMUX_PAD(0x4DC, 0x190, 1, __NA_, 0, NO_PAD_CTRL) |
| 1844 | #define MX53_PAD_EIM_EB1__IPU_CSI1_D_10 (_MX53_PAD_EIM_EB1__IPU_CSI1_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 670 | #define MX53_PAD_EIM_LBA__ECSPI2_SS1 IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, NO_PAD_CTRL) |
| 1845 | #define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 (_MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 671 | #define MX53_PAD_EIM_LBA__IPU_DI1_PIN17 IOMUX_PAD(0x4DC, 0x190, 3, __NA_, 0, NO_PAD_CTRL) |
| 1846 | #define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 (_MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 672 | #define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 IOMUX_PAD(0x4DC, 0x190, 7, __NA_, 0, NO_PAD_CTRL) |
| 1847 | #define MX53_PAD_EIM_DA0__GPIO3_0 (_MX53_PAD_EIM_DA0__GPIO3_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 673 | #define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 IOMUX_PAD(0x4E4, 0x194, 0, __NA_, 0, NO_PAD_CTRL) |
| 1848 | #define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 (_MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 674 | #define MX53_PAD_EIM_EB0__GPIO2_28 IOMUX_PAD(0x4E4, 0x194, 1, __NA_, 0, NO_PAD_CTRL) |
| 1849 | #define MX53_PAD_EIM_DA0__IPU_CSI1_D_9 (_MX53_PAD_EIM_DA0__IPU_CSI1_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 675 | #define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 IOMUX_PAD(0x4E4, 0x194, 3, __NA_, 0, NO_PAD_CTRL) |
| 1850 | #define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 (_MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 676 | #define MX53_PAD_EIM_EB0__IPU_CSI1_D_11 IOMUX_PAD(0x4E4, 0x194, 4, __NA_, 0, NO_PAD_CTRL) |
| 1851 | #define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 (_MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 677 | #define MX53_PAD_EIM_EB0__GPC_PMIC_RDY IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, NO_PAD_CTRL) |
| 1852 | #define MX53_PAD_EIM_DA1__GPIO3_1 (_MX53_PAD_EIM_DA1__GPIO3_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 678 | #define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 IOMUX_PAD(0x4E4, 0x194, 7, __NA_, 0, NO_PAD_CTRL) |
| 1853 | #define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 (_MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 679 | #define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 IOMUX_PAD(0x4E8, 0x198, 0, __NA_, 0, NO_PAD_CTRL) |
| 1854 | #define MX53_PAD_EIM_DA1__IPU_CSI1_D_8 (_MX53_PAD_EIM_DA1__IPU_CSI1_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 680 | #define MX53_PAD_EIM_EB1__GPIO2_29 IOMUX_PAD(0x4E8, 0x198, 1, __NA_, 0, NO_PAD_CTRL) |
| 1855 | #define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 (_MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 681 | #define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 IOMUX_PAD(0x4E8, 0x198, 3, __NA_, 0, NO_PAD_CTRL) |
| 1856 | #define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 (_MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 682 | #define MX53_PAD_EIM_EB1__IPU_CSI1_D_10 IOMUX_PAD(0x4E8, 0x198, 4, __NA_, 0, NO_PAD_CTRL) |
| 1857 | #define MX53_PAD_EIM_DA2__GPIO3_2 (_MX53_PAD_EIM_DA2__GPIO3_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 683 | #define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 IOMUX_PAD(0x4E8, 0x198, 7, __NA_, 0, NO_PAD_CTRL) |
| 1858 | #define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 (_MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 684 | #define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 IOMUX_PAD(0x4EC, 0x19C, 0, __NA_, 0, NO_PAD_CTRL) |
| 1859 | #define MX53_PAD_EIM_DA2__IPU_CSI1_D_7 (_MX53_PAD_EIM_DA2__IPU_CSI1_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 685 | #define MX53_PAD_EIM_DA0__GPIO3_0 IOMUX_PAD(0x4EC, 0x19C, 1, __NA_, 0, NO_PAD_CTRL) |
| 1860 | #define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 (_MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 686 | #define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 IOMUX_PAD(0x4EC, 0x19C, 3, __NA_, 0, NO_PAD_CTRL) |
| 1861 | #define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 (_MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 687 | #define MX53_PAD_EIM_DA0__IPU_CSI1_D_9 IOMUX_PAD(0x4EC, 0x19C, 4, __NA_, 0, NO_PAD_CTRL) |
| 1862 | #define MX53_PAD_EIM_DA3__GPIO3_3 (_MX53_PAD_EIM_DA3__GPIO3_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 688 | #define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 IOMUX_PAD(0x4EC, 0x19C, 7, __NA_, 0, NO_PAD_CTRL) |
| 1863 | #define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 (_MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 689 | #define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 IOMUX_PAD(0x4F0, 0x1A0, 0, __NA_, 0, NO_PAD_CTRL) |
| 1864 | #define MX53_PAD_EIM_DA3__IPU_CSI1_D_6 (_MX53_PAD_EIM_DA3__IPU_CSI1_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 690 | #define MX53_PAD_EIM_DA1__GPIO3_1 IOMUX_PAD(0x4F0, 0x1A0, 1, __NA_, 0, NO_PAD_CTRL) |
| 1865 | #define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 (_MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 691 | #define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 IOMUX_PAD(0x4F0, 0x1A0, 3, __NA_, 0, NO_PAD_CTRL) |
| 1866 | #define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 (_MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 692 | #define MX53_PAD_EIM_DA1__IPU_CSI1_D_8 IOMUX_PAD(0x4F0, 0x1A0, 4, __NA_, 0, NO_PAD_CTRL) |
| 1867 | #define MX53_PAD_EIM_DA4__GPIO3_4 (_MX53_PAD_EIM_DA4__GPIO3_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 693 | #define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 IOMUX_PAD(0x4F0, 0x1A0, 7, __NA_, 0, NO_PAD_CTRL) |
| 1868 | #define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 (_MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 694 | #define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 IOMUX_PAD(0x4F4, 0x1A4, 0, __NA_, 0, NO_PAD_CTRL) |
| 1869 | #define MX53_PAD_EIM_DA4__IPU_CSI1_D_5 (_MX53_PAD_EIM_DA4__IPU_CSI1_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 695 | #define MX53_PAD_EIM_DA2__GPIO3_2 IOMUX_PAD(0x4F4, 0x1A4, 1, __NA_, 0, NO_PAD_CTRL) |
| 1870 | #define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 (_MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 696 | #define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 IOMUX_PAD(0x4F4, 0x1A4, 3, __NA_, 0, NO_PAD_CTRL) |
| 1871 | #define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 (_MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 697 | #define MX53_PAD_EIM_DA2__IPU_CSI1_D_7 IOMUX_PAD(0x4F4, 0x1A4, 4, __NA_, 0, NO_PAD_CTRL) |
| 1872 | #define MX53_PAD_EIM_DA5__GPIO3_5 (_MX53_PAD_EIM_DA5__GPIO3_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 698 | #define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 IOMUX_PAD(0x4F4, 0x1A4, 7, __NA_, 0, NO_PAD_CTRL) |
| 1873 | #define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 (_MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 699 | #define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 IOMUX_PAD(0x4F8, 0x1A8, 0, __NA_, 0, NO_PAD_CTRL) |
| 1874 | #define MX53_PAD_EIM_DA5__IPU_CSI1_D_4 (_MX53_PAD_EIM_DA5__IPU_CSI1_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 700 | #define MX53_PAD_EIM_DA3__GPIO3_3 IOMUX_PAD(0x4F8, 0x1A8, 1, __NA_, 0, NO_PAD_CTRL) |
| 1875 | #define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 (_MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 701 | #define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 IOMUX_PAD(0x4F8, 0x1A8, 3, __NA_, 0, NO_PAD_CTRL) |
| 1876 | #define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 (_MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 702 | #define MX53_PAD_EIM_DA3__IPU_CSI1_D_6 IOMUX_PAD(0x4F8, 0x1A8, 4, __NA_, 0, NO_PAD_CTRL) |
| 1877 | #define MX53_PAD_EIM_DA6__GPIO3_6 (_MX53_PAD_EIM_DA6__GPIO3_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 703 | #define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 IOMUX_PAD(0x4F8, 0x1A8, 7, __NA_, 0, NO_PAD_CTRL) |
| 1878 | #define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 (_MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 704 | #define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 IOMUX_PAD(0x4FC, 0x1AC, 0, __NA_, 0, NO_PAD_CTRL) |
| 1879 | #define MX53_PAD_EIM_DA6__IPU_CSI1_D_3 (_MX53_PAD_EIM_DA6__IPU_CSI1_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 705 | #define MX53_PAD_EIM_DA4__GPIO3_4 IOMUX_PAD(0x4FC, 0x1AC, 1, __NA_, 0, NO_PAD_CTRL) |
| 1880 | #define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 (_MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 706 | #define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 IOMUX_PAD(0x4FC, 0x1AC, 3, __NA_, 0, NO_PAD_CTRL) |
| 1881 | #define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 (_MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 707 | #define MX53_PAD_EIM_DA4__IPU_CSI1_D_5 IOMUX_PAD(0x4FC, 0x1AC, 4, __NA_, 0, NO_PAD_CTRL) |
| 1882 | #define MX53_PAD_EIM_DA7__GPIO3_7 (_MX53_PAD_EIM_DA7__GPIO3_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 708 | #define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 IOMUX_PAD(0x4FC, 0x1AC, 7, __NA_, 0, NO_PAD_CTRL) |
| 1883 | #define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 (_MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 709 | #define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 IOMUX_PAD(0x500, 0x1B0, 0, __NA_, 0, NO_PAD_CTRL) |
| 1884 | #define MX53_PAD_EIM_DA7__IPU_CSI1_D_2 (_MX53_PAD_EIM_DA7__IPU_CSI1_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 710 | #define MX53_PAD_EIM_DA5__GPIO3_5 IOMUX_PAD(0x500, 0x1B0, 1, __NA_, 0, NO_PAD_CTRL) |
| 1885 | #define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 (_MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 711 | #define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 IOMUX_PAD(0x500, 0x1B0, 3, __NA_, 0, NO_PAD_CTRL) |
| 1886 | #define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 (_MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 712 | #define MX53_PAD_EIM_DA5__IPU_CSI1_D_4 IOMUX_PAD(0x500, 0x1B0, 4, __NA_, 0, NO_PAD_CTRL) |
| 1887 | #define MX53_PAD_EIM_DA8__GPIO3_8 (_MX53_PAD_EIM_DA8__GPIO3_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 713 | #define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 IOMUX_PAD(0x500, 0x1B0, 7 | IOMUX_CONFIG_SION, __NA_, 0, NO_PAD_CTRL) |
| 1888 | #define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 (_MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 714 | #define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 IOMUX_PAD(0x504, 0x1B4, 0, __NA_, 0, NO_PAD_CTRL) |
| 1889 | #define MX53_PAD_EIM_DA8__IPU_CSI1_D_1 (_MX53_PAD_EIM_DA8__IPU_CSI1_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 715 | #define MX53_PAD_EIM_DA6__GPIO3_6 IOMUX_PAD(0x504, 0x1B4, 1, __NA_, 0, NO_PAD_CTRL) |
| 1890 | #define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 (_MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 716 | #define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 IOMUX_PAD(0x504, 0x1B4, 3, __NA_, 0, NO_PAD_CTRL) |
| 1891 | #define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 (_MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 717 | #define MX53_PAD_EIM_DA6__IPU_CSI1_D_3 IOMUX_PAD(0x504, 0x1B4, 4, __NA_, 0, NO_PAD_CTRL) |
| 1892 | #define MX53_PAD_EIM_DA9__GPIO3_9 (_MX53_PAD_EIM_DA9__GPIO3_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 718 | #define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 IOMUX_PAD(0x504, 0x1B4, 7, __NA_, 0, NO_PAD_CTRL) |
| 1893 | #define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 (_MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 719 | #define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 IOMUX_PAD(0x508, 0x1B8, 0, __NA_, 0, NO_PAD_CTRL) |
| 1894 | #define MX53_PAD_EIM_DA9__IPU_CSI1_D_0 (_MX53_PAD_EIM_DA9__IPU_CSI1_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 720 | #define MX53_PAD_EIM_DA7__GPIO3_7 IOMUX_PAD(0x508, 0x1B8, 1, __NA_, 0, NO_PAD_CTRL) |
| 1895 | #define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 (_MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 721 | #define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 IOMUX_PAD(0x508, 0x1B8, 3, __NA_, 0, NO_PAD_CTRL) |
| 1896 | #define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 (_MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 722 | #define MX53_PAD_EIM_DA7__IPU_CSI1_D_2 IOMUX_PAD(0x508, 0x1B8, 4, __NA_, 0, NO_PAD_CTRL) |
| 1897 | #define MX53_PAD_EIM_DA10__GPIO3_10 (_MX53_PAD_EIM_DA10__GPIO3_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 723 | #define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 IOMUX_PAD(0x508, 0x1B8, 7, __NA_, 0, NO_PAD_CTRL) |
| 1898 | #define MX53_PAD_EIM_DA10__IPU_DI1_PIN15 (_MX53_PAD_EIM_DA10__IPU_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 724 | #define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 IOMUX_PAD(0x50C, 0x1BC, 0, __NA_, 0, NO_PAD_CTRL) |
| 1899 | #define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN (_MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) | 725 | #define MX53_PAD_EIM_DA8__GPIO3_8 IOMUX_PAD(0x50C, 0x1BC, 1, __NA_, 0, NO_PAD_CTRL) |
| 1900 | #define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 (_MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 726 | #define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 IOMUX_PAD(0x50C, 0x1BC, 3, __NA_, 0, NO_PAD_CTRL) |
| 1901 | #define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 (_MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 727 | #define MX53_PAD_EIM_DA8__IPU_CSI1_D_1 IOMUX_PAD(0x50C, 0x1BC, 4, __NA_, 0, NO_PAD_CTRL) |
| 1902 | #define MX53_PAD_EIM_DA11__GPIO3_11 (_MX53_PAD_EIM_DA11__GPIO3_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 728 | #define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 IOMUX_PAD(0x50C, 0x1BC, 7, __NA_, 0, NO_PAD_CTRL) |
| 1903 | #define MX53_PAD_EIM_DA11__IPU_DI1_PIN2 (_MX53_PAD_EIM_DA11__IPU_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 729 | #define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 IOMUX_PAD(0x510, 0x1C0, 0, __NA_, 0, NO_PAD_CTRL) |
| 1904 | #define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC (_MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 730 | #define MX53_PAD_EIM_DA9__GPIO3_9 IOMUX_PAD(0x510, 0x1C0, 1, __NA_, 0, NO_PAD_CTRL) |
| 1905 | #define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 (_MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 731 | #define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 IOMUX_PAD(0x510, 0x1C0, 3, __NA_, 0, NO_PAD_CTRL) |
| 1906 | #define MX53_PAD_EIM_DA12__GPIO3_12 (_MX53_PAD_EIM_DA12__GPIO3_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 732 | #define MX53_PAD_EIM_DA9__IPU_CSI1_D_0 IOMUX_PAD(0x510, 0x1C0, 4, __NA_, 0, NO_PAD_CTRL) |
| 1907 | #define MX53_PAD_EIM_DA12__IPU_DI1_PIN3 (_MX53_PAD_EIM_DA12__IPU_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 733 | #define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 IOMUX_PAD(0x510, 0x1C0, 7, __NA_, 0, NO_PAD_CTRL) |
| 1908 | #define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC (_MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 734 | #define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 IOMUX_PAD(0x514, 0x1C4, 0, __NA_, 0, NO_PAD_CTRL) |
| 1909 | #define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 (_MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 735 | #define MX53_PAD_EIM_DA10__GPIO3_10 IOMUX_PAD(0x514, 0x1C4, 1, __NA_, 0, NO_PAD_CTRL) |
| 1910 | #define MX53_PAD_EIM_DA13__GPIO3_13 (_MX53_PAD_EIM_DA13__GPIO3_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 736 | #define MX53_PAD_EIM_DA10__IPU_DI1_PIN15 IOMUX_PAD(0x514, 0x1C4, 3, __NA_, 0, NO_PAD_CTRL) |
| 1911 | #define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS (_MX53_PAD_EIM_DA13__IPU_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 737 | #define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, NO_PAD_CTRL) |
| 1912 | #define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK (_MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 738 | #define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 IOMUX_PAD(0x514, 0x1C4, 7, __NA_, 0, NO_PAD_CTRL) |
| 1913 | #define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 (_MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 739 | #define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 IOMUX_PAD(0x518, 0x1C8, 0, __NA_, 0, NO_PAD_CTRL) |
| 1914 | #define MX53_PAD_EIM_DA14__GPIO3_14 (_MX53_PAD_EIM_DA14__GPIO3_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 740 | #define MX53_PAD_EIM_DA11__GPIO3_11 IOMUX_PAD(0x518, 0x1C8, 1, __NA_, 0, NO_PAD_CTRL) |
| 1915 | #define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS (_MX53_PAD_EIM_DA14__IPU_DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 741 | #define MX53_PAD_EIM_DA11__IPU_DI1_PIN2 IOMUX_PAD(0x518, 0x1C8, 3, __NA_, 0, NO_PAD_CTRL) |
| 1916 | #define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK (_MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 742 | #define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, NO_PAD_CTRL) |
| 1917 | #define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 (_MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 743 | #define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 IOMUX_PAD(0x51C, 0x1CC, 0, __NA_, 0, NO_PAD_CTRL) |
| 1918 | #define MX53_PAD_EIM_DA15__GPIO3_15 (_MX53_PAD_EIM_DA15__GPIO3_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 744 | #define MX53_PAD_EIM_DA12__GPIO3_12 IOMUX_PAD(0x51C, 0x1CC, 1, __NA_, 0, NO_PAD_CTRL) |
| 1919 | #define MX53_PAD_EIM_DA15__IPU_DI1_PIN1 (_MX53_PAD_EIM_DA15__IPU_DI1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 745 | #define MX53_PAD_EIM_DA12__IPU_DI1_PIN3 IOMUX_PAD(0x51C, 0x1CC, 3, __NA_, 0, NO_PAD_CTRL) |
| 1920 | #define MX53_PAD_EIM_DA15__IPU_DI1_PIN4 (_MX53_PAD_EIM_DA15__IPU_DI1_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 746 | #define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, NO_PAD_CTRL) |
| 1921 | #define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B (_MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) | 747 | #define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 IOMUX_PAD(0x520, 0x1D0, 0, __NA_, 0, NO_PAD_CTRL) |
| 1922 | #define MX53_PAD_NANDF_WE_B__GPIO6_12 (_MX53_PAD_NANDF_WE_B__GPIO6_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 748 | #define MX53_PAD_EIM_DA13__GPIO3_13 IOMUX_PAD(0x520, 0x1D0, 1, __NA_, 0, NO_PAD_CTRL) |
| 1923 | #define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B (_MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) | 749 | #define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS IOMUX_PAD(0x520, 0x1D0, 3, __NA_, 0, NO_PAD_CTRL) |
| 1924 | #define MX53_PAD_NANDF_RE_B__GPIO6_13 (_MX53_PAD_NANDF_RE_B__GPIO6_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 750 | #define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, NO_PAD_CTRL) |
| 1925 | #define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT (_MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL)) | 751 | #define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 IOMUX_PAD(0x524, 0x1D4, 0, __NA_, 0, NO_PAD_CTRL) |
| 1926 | #define MX53_PAD_EIM_WAIT__GPIO5_0 (_MX53_PAD_EIM_WAIT__GPIO5_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 752 | #define MX53_PAD_EIM_DA14__GPIO3_14 IOMUX_PAD(0x524, 0x1D4, 1, __NA_, 0, NO_PAD_CTRL) |
| 1927 | #define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B (_MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B | MUX_PAD_CTRL(NO_PAD_CTRL)) | 753 | #define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS IOMUX_PAD(0x524, 0x1D4, 3, __NA_, 0, NO_PAD_CTRL) |
| 1928 | #define MX53_PAD_LVDS1_TX3_P__GPIO6_22 (_MX53_PAD_LVDS1_TX3_P__GPIO6_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 754 | #define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK IOMUX_PAD(0x524, 0x1D4, 4, __NA_, 0, NO_PAD_CTRL) |
| 1929 | #define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 (_MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 755 | #define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 IOMUX_PAD(0x528, 0x1D8, 0, __NA_, 0, NO_PAD_CTRL) |
| 1930 | #define MX53_PAD_LVDS1_TX2_P__GPIO6_24 (_MX53_PAD_LVDS1_TX2_P__GPIO6_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 756 | #define MX53_PAD_EIM_DA15__GPIO3_15 IOMUX_PAD(0x528, 0x1D8, 1, __NA_, 0, NO_PAD_CTRL) |
| 1931 | #define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 (_MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 757 | #define MX53_PAD_EIM_DA15__IPU_DI1_PIN1 IOMUX_PAD(0x528, 0x1D8, 3, __NA_, 0, NO_PAD_CTRL) |
| 1932 | #define MX53_PAD_LVDS1_CLK_P__GPIO6_26 (_MX53_PAD_LVDS1_CLK_P__GPIO6_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 758 | #define MX53_PAD_EIM_DA15__IPU_DI1_PIN4 IOMUX_PAD(0x528, 0x1D8, 4, __NA_, 0, NO_PAD_CTRL) |
| 1933 | #define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK (_MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 759 | #define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B IOMUX_PAD(0x52C, 0x1DC, 0, __NA_, 0, NO_PAD_CTRL) |
| 1934 | #define MX53_PAD_LVDS1_TX1_P__GPIO6_28 (_MX53_PAD_LVDS1_TX1_P__GPIO6_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 760 | #define MX53_PAD_NANDF_WE_B__GPIO6_12 IOMUX_PAD(0x52C, 0x1DC, 1, __NA_, 0, NO_PAD_CTRL) |
| 1935 | #define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 (_MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 761 | #define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B IOMUX_PAD(0x530, 0x1E0, 0, __NA_, 0, NO_PAD_CTRL) |
| 1936 | #define MX53_PAD_LVDS1_TX0_P__GPIO6_30 (_MX53_PAD_LVDS1_TX0_P__GPIO6_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 762 | #define MX53_PAD_NANDF_RE_B__GPIO6_13 IOMUX_PAD(0x530, 0x1E0, 1, __NA_, 0, NO_PAD_CTRL) |
| 1937 | #define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 (_MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 763 | #define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT IOMUX_PAD(0x534, 0x1E4, 0, __NA_, 0, NO_PAD_CTRL) |
| 1938 | #define MX53_PAD_LVDS0_TX3_P__GPIO7_22 (_MX53_PAD_LVDS0_TX3_P__GPIO7_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 764 | #define MX53_PAD_EIM_WAIT__GPIO5_0 IOMUX_PAD(0x534, 0x1E4, 1, __NA_, 0, NO_PAD_CTRL) |
| 1939 | #define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 (_MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 765 | #define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B IOMUX_PAD(0x534, 0x1E4, 2, __NA_, 0, NO_PAD_CTRL) |
| 1940 | #define MX53_PAD_LVDS0_CLK_P__GPIO7_24 (_MX53_PAD_LVDS0_CLK_P__GPIO7_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 766 | #define MX53_PAD_LVDS1_TX3_P__GPIO6_22 IOMUX_PAD(__NA_, 0x1EC, 0, __NA_, 0, NO_PAD_CTRL) |
| 1941 | #define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK (_MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 767 | #define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 IOMUX_PAD(__NA_, 0x1EC, 1, __NA_, 0, NO_PAD_CTRL) |
| 1942 | #define MX53_PAD_LVDS0_TX2_P__GPIO7_26 (_MX53_PAD_LVDS0_TX2_P__GPIO7_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 768 | #define MX53_PAD_LVDS1_TX2_P__GPIO6_24 IOMUX_PAD(__NA_, 0x1F0, 0, __NA_, 0, NO_PAD_CTRL) |
| 1943 | #define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 (_MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 769 | #define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 IOMUX_PAD(__NA_, 0x1F0, 1, __NA_, 0, NO_PAD_CTRL) |
| 1944 | #define MX53_PAD_LVDS0_TX1_P__GPIO7_28 (_MX53_PAD_LVDS0_TX1_P__GPIO7_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 770 | #define MX53_PAD_LVDS1_CLK_P__GPIO6_26 IOMUX_PAD(__NA_, 0x1F4, 0, __NA_, 0, NO_PAD_CTRL) |
| 1945 | #define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 (_MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 771 | #define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK IOMUX_PAD(__NA_, 0x1F4, 1, __NA_, 0, NO_PAD_CTRL) |
| 1946 | #define MX53_PAD_LVDS0_TX0_P__GPIO7_30 (_MX53_PAD_LVDS0_TX0_P__GPIO7_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 772 | #define MX53_PAD_LVDS1_TX1_P__GPIO6_28 IOMUX_PAD(__NA_, 0x1F8, 0, __NA_, 0, NO_PAD_CTRL) |
| 1947 | #define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 (_MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 773 | #define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 IOMUX_PAD(__NA_, 0x1F8, 1, __NA_, 0, NO_PAD_CTRL) |
| 1948 | #define MX53_PAD_GPIO_10__GPIO4_0 (_MX53_PAD_GPIO_10__GPIO4_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 774 | #define MX53_PAD_LVDS1_TX0_P__GPIO6_30 IOMUX_PAD(__NA_, 0x1FC, 0, __NA_, 0, NO_PAD_CTRL) |
| 1949 | #define MX53_PAD_GPIO_10__OSC32k_32K_OUT (_MX53_PAD_GPIO_10__OSC32k_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) | 775 | #define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 IOMUX_PAD(__NA_, 0x1FC, 1, __NA_, 0, NO_PAD_CTRL) |
| 1950 | #define MX53_PAD_GPIO_11__GPIO4_1 (_MX53_PAD_GPIO_11__GPIO4_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 776 | #define MX53_PAD_LVDS0_TX3_P__GPIO7_22 IOMUX_PAD(__NA_, 0x200, 0, __NA_, 0, NO_PAD_CTRL) |
| 1951 | #define MX53_PAD_GPIO_12__GPIO4_2 (_MX53_PAD_GPIO_12__GPIO4_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 777 | #define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 IOMUX_PAD(__NA_, 0x200, 1, __NA_, 0, NO_PAD_CTRL) |
| 1952 | #define MX53_PAD_GPIO_13__GPIO4_3 (_MX53_PAD_GPIO_13__GPIO4_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 778 | #define MX53_PAD_LVDS0_CLK_P__GPIO7_24 IOMUX_PAD(__NA_, 0x204, 0, __NA_, 0, NO_PAD_CTRL) |
| 1953 | #define MX53_PAD_GPIO_14__GPIO4_4 (_MX53_PAD_GPIO_14__GPIO4_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 779 | #define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK IOMUX_PAD(__NA_, 0x204, 1, __NA_, 0, NO_PAD_CTRL) |
| 1954 | #define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE (_MX53_PAD_NANDF_CLE__EMI_NANDF_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)) | 780 | #define MX53_PAD_LVDS0_TX2_P__GPIO7_26 IOMUX_PAD(__NA_, 0x208, 0, __NA_, 0, NO_PAD_CTRL) |
| 1955 | #define MX53_PAD_NANDF_CLE__GPIO6_7 (_MX53_PAD_NANDF_CLE__GPIO6_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 781 | #define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 IOMUX_PAD(__NA_, 0x208, 1, __NA_, 0, NO_PAD_CTRL) |
| 1956 | #define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 (_MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 782 | #define MX53_PAD_LVDS0_TX1_P__GPIO7_28 IOMUX_PAD(__NA_, 0x20C, 0, __NA_, 0, NO_PAD_CTRL) |
| 1957 | #define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE (_MX53_PAD_NANDF_ALE__EMI_NANDF_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)) | 783 | #define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 IOMUX_PAD(__NA_, 0x20C, 1, __NA_, 0, NO_PAD_CTRL) |
| 1958 | #define MX53_PAD_NANDF_ALE__GPIO6_8 (_MX53_PAD_NANDF_ALE__GPIO6_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 784 | #define MX53_PAD_LVDS0_TX0_P__GPIO7_30 IOMUX_PAD(__NA_, 0x210, 0, __NA_, 0, NO_PAD_CTRL) |
| 1959 | #define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 (_MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 785 | #define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 IOMUX_PAD(__NA_, 0x210, 1, __NA_, 0, NO_PAD_CTRL) |
| 1960 | #define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B (_MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)) | 786 | #define MX53_PAD_GPIO_10__GPIO4_0 IOMUX_PAD(0x540, 0x214, 0, __NA_, 0, NO_PAD_CTRL) |
| 1961 | #define MX53_PAD_NANDF_WP_B__GPIO6_9 (_MX53_PAD_NANDF_WP_B__GPIO6_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 787 | #define MX53_PAD_GPIO_10__OSC32k_32K_OUT IOMUX_PAD(0x540, 0x214, 1, __NA_, 0, NO_PAD_CTRL) |
| 1962 | #define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 (_MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 788 | #define MX53_PAD_GPIO_11__GPIO4_1 IOMUX_PAD(0x544, 0x218, 0, __NA_, 0, NO_PAD_CTRL) |
| 1963 | #define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 (_MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 789 | #define MX53_PAD_GPIO_12__GPIO4_2 IOMUX_PAD(0x548, 0x21C, 0, __NA_, 0, NO_PAD_CTRL) |
| 1964 | #define MX53_PAD_NANDF_RB0__GPIO6_10 (_MX53_PAD_NANDF_RB0__GPIO6_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 790 | #define MX53_PAD_GPIO_13__GPIO4_3 IOMUX_PAD(0x54C, 0x220, 0, __NA_, 0, NO_PAD_CTRL) |
| 1965 | #define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 (_MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 791 | #define MX53_PAD_GPIO_14__GPIO4_4 IOMUX_PAD(0x550, 0x224, 0, __NA_, 0, NO_PAD_CTRL) |
| 1966 | #define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 (_MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 792 | #define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE IOMUX_PAD(0x5A0, 0x228, 0, __NA_, 0, NO_PAD_CTRL) |
| 1967 | #define MX53_PAD_NANDF_CS0__GPIO6_11 (_MX53_PAD_NANDF_CS0__GPIO6_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 793 | #define MX53_PAD_NANDF_CLE__GPIO6_7 IOMUX_PAD(0x5A0, 0x228, 1, __NA_, 0, NO_PAD_CTRL) |
| 1968 | #define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 (_MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 794 | #define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 IOMUX_PAD(0x5A0, 0x228, 7, __NA_, 0, NO_PAD_CTRL) |
| 1969 | #define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 (_MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 795 | #define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE IOMUX_PAD(0x5A4, 0x22C, 0, __NA_, 0, NO_PAD_CTRL) |
| 1970 | #define MX53_PAD_NANDF_CS1__GPIO6_14 (_MX53_PAD_NANDF_CS1__GPIO6_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 796 | #define MX53_PAD_NANDF_ALE__GPIO6_8 IOMUX_PAD(0x5A4, 0x22C, 1, __NA_, 0, NO_PAD_CTRL) |
| 1971 | #define MX53_PAD_NANDF_CS1__MLB_MLBCLK (_MX53_PAD_NANDF_CS1__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 797 | #define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 IOMUX_PAD(0x5A4, 0x22C, 7, __NA_, 0, NO_PAD_CTRL) |
| 1972 | #define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 (_MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 798 | #define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B IOMUX_PAD(0x5A8, 0x230, 0, __NA_, 0, NO_PAD_CTRL) |
| 1973 | #define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 (_MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 799 | #define MX53_PAD_NANDF_WP_B__GPIO6_9 IOMUX_PAD(0x5A8, 0x230, 1, __NA_, 0, NO_PAD_CTRL) |
| 1974 | #define MX53_PAD_NANDF_CS2__GPIO6_15 (_MX53_PAD_NANDF_CS2__GPIO6_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 800 | #define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 IOMUX_PAD(0x5A8, 0x230, 7, __NA_, 0, NO_PAD_CTRL) |
| 1975 | #define MX53_PAD_NANDF_CS2__IPU_SISG_0 (_MX53_PAD_NANDF_CS2__IPU_SISG_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 801 | #define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 IOMUX_PAD(0x5AC, 0x234, 0, __NA_, 0, NO_PAD_CTRL) |
| 1976 | #define MX53_PAD_NANDF_CS2__ESAI1_TX0 (_MX53_PAD_NANDF_CS2__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 802 | #define MX53_PAD_NANDF_RB0__GPIO6_10 IOMUX_PAD(0x5AC, 0x234, 1, __NA_, 0, NO_PAD_CTRL) |
| 1977 | #define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE (_MX53_PAD_NANDF_CS2__EMI_WEIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL)) | 803 | #define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 IOMUX_PAD(0x5AC, 0x234, 7, __NA_, 0, NO_PAD_CTRL) |
| 1978 | #define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK (_MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 804 | #define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 IOMUX_PAD(0x5B0, 0x238, 0, __NA_, 0, NO_PAD_CTRL) |
| 1979 | #define MX53_PAD_NANDF_CS2__MLB_MLBSIG (_MX53_PAD_NANDF_CS2__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL)) | 805 | #define MX53_PAD_NANDF_CS0__GPIO6_11 IOMUX_PAD(0x5B0, 0x238, 1, __NA_, 0, NO_PAD_CTRL) |
| 1980 | #define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 (_MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 806 | #define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 IOMUX_PAD(0x5B0, 0x238, 7, __NA_, 0, NO_PAD_CTRL) |
| 1981 | #define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 (_MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 807 | #define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 IOMUX_PAD(0x5B4, 0x23C, 0, __NA_, 0, NO_PAD_CTRL) |
| 1982 | #define MX53_PAD_NANDF_CS3__GPIO6_16 (_MX53_PAD_NANDF_CS3__GPIO6_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 808 | #define MX53_PAD_NANDF_CS1__GPIO6_14 IOMUX_PAD(0x5B4, 0x23C, 1, __NA_, 0, NO_PAD_CTRL) |
| 1983 | #define MX53_PAD_NANDF_CS3__IPU_SISG_1 (_MX53_PAD_NANDF_CS3__IPU_SISG_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 809 | #define MX53_PAD_NANDF_CS1__MLB_MLBCLK IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, NO_PAD_CTRL) |
| 1984 | #define MX53_PAD_NANDF_CS3__ESAI1_TX1 (_MX53_PAD_NANDF_CS3__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 810 | #define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 IOMUX_PAD(0x5B4, 0x23C, 7, __NA_, 0, NO_PAD_CTRL) |
| 1985 | #define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 (_MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 811 | #define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 IOMUX_PAD(0x5B8, 0x240, 0, __NA_, 0, NO_PAD_CTRL) |
| 1986 | #define MX53_PAD_NANDF_CS3__MLB_MLBDAT (_MX53_PAD_NANDF_CS3__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL)) | 812 | #define MX53_PAD_NANDF_CS2__GPIO6_15 IOMUX_PAD(0x5B8, 0x240, 1, __NA_, 0, NO_PAD_CTRL) |
| 1987 | #define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 (_MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 813 | #define MX53_PAD_NANDF_CS2__IPU_SISG_0 IOMUX_PAD(0x5B8, 0x240, 2, __NA_, 0, NO_PAD_CTRL) |
| 1988 | #define MX53_PAD_FEC_MDIO__FEC_MDIO (_MX53_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 814 | #define MX53_PAD_NANDF_CS2__ESAI1_TX0 IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, NO_PAD_CTRL) |
| 1989 | #define MX53_PAD_FEC_MDIO__GPIO1_22 (_MX53_PAD_FEC_MDIO__GPIO1_22 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 815 | #define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE IOMUX_PAD(0x5B8, 0x240, 4, __NA_, 0, NO_PAD_CTRL) |
| 1990 | #define MX53_PAD_FEC_MDIO__ESAI1_SCKR (_MX53_PAD_FEC_MDIO__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL)) | 816 | #define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK IOMUX_PAD(0x5B8, 0x240, 5, __NA_, 0, NO_PAD_CTRL) |
| 1991 | #define MX53_PAD_FEC_MDIO__FEC_COL (_MX53_PAD_FEC_MDIO__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL)) | 817 | #define MX53_PAD_NANDF_CS2__MLB_MLBSIG IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, NO_PAD_CTRL) |
| 1992 | #define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 (_MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 818 | #define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 IOMUX_PAD(0x5B8, 0x240, 7, __NA_, 0, NO_PAD_CTRL) |
| 1993 | #define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 (_MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 819 | #define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 IOMUX_PAD(0x5BC, 0x244, 0, __NA_, 0, NO_PAD_CTRL) |
| 1994 | #define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 (_MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 820 | #define MX53_PAD_NANDF_CS3__GPIO6_16 IOMUX_PAD(0x5BC, 0x244, 1, __NA_, 0, NO_PAD_CTRL) |
| 1995 | #define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK (_MX53_PAD_FEC_REF_CLK__FEC_TX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 821 | #define MX53_PAD_NANDF_CS3__IPU_SISG_1 IOMUX_PAD(0x5BC, 0x244, 2, __NA_, 0, NO_PAD_CTRL) |
| 1996 | #define MX53_PAD_FEC_REF_CLK__GPIO1_23 (_MX53_PAD_FEC_REF_CLK__GPIO1_23 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 822 | #define MX53_PAD_NANDF_CS3__ESAI1_TX1 IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, NO_PAD_CTRL) |
| 1997 | #define MX53_PAD_FEC_REF_CLK__ESAI1_FSR (_MX53_PAD_FEC_REF_CLK__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL)) | 823 | #define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 IOMUX_PAD(0x5BC, 0x244, 4, __NA_, 0, NO_PAD_CTRL) |
| 1998 | #define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 (_MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 824 | #define MX53_PAD_NANDF_CS3__MLB_MLBDAT IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, NO_PAD_CTRL) |
| 1999 | #define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 (_MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 825 | #define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 IOMUX_PAD(0x5BC, 0x244, 7, __NA_, 0, NO_PAD_CTRL) |
| 2000 | #define MX53_PAD_FEC_RX_ER__FEC_RX_ER (_MX53_PAD_FEC_RX_ER__FEC_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL)) | 826 | #define MX53_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, NO_PAD_CTRL) |
| 2001 | #define MX53_PAD_FEC_RX_ER__GPIO1_24 (_MX53_PAD_FEC_RX_ER__GPIO1_24 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 827 | #define MX53_PAD_FEC_MDIO__GPIO1_22 IOMUX_PAD(0x5C4, 0x248, 1, __NA_, 0, NO_PAD_CTRL) |
| 2002 | #define MX53_PAD_FEC_RX_ER__ESAI1_HCKR (_MX53_PAD_FEC_RX_ER__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL)) | 828 | #define MX53_PAD_FEC_MDIO__ESAI1_SCKR IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, NO_PAD_CTRL) |
| 2003 | #define MX53_PAD_FEC_RX_ER__FEC_RX_CLK (_MX53_PAD_FEC_RX_ER__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 829 | #define MX53_PAD_FEC_MDIO__FEC_COL IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, NO_PAD_CTRL) |
| 2004 | #define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 (_MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 830 | #define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 IOMUX_PAD(0x5C4, 0x248, 4, __NA_, 0, NO_PAD_CTRL) |
| 2005 | #define MX53_PAD_FEC_CRS_DV__FEC_RX_DV (_MX53_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL)) | 831 | #define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 IOMUX_PAD(0x5C4, 0x248, 5, __NA_, 0, NO_PAD_CTRL) |
| 2006 | #define MX53_PAD_FEC_CRS_DV__GPIO1_25 (_MX53_PAD_FEC_CRS_DV__GPIO1_25 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 832 | #define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 IOMUX_PAD(0x5C4, 0x248, 6, __NA_, 0, NO_PAD_CTRL) |
| 2007 | #define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT (_MX53_PAD_FEC_CRS_DV__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL)) | 833 | #define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK IOMUX_PAD(0x5C8, 0x24C, 0, __NA_, 0, NO_PAD_CTRL) |
| 2008 | #define MX53_PAD_FEC_RXD1__FEC_RDATA_1 (_MX53_PAD_FEC_RXD1__FEC_RDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 834 | #define MX53_PAD_FEC_REF_CLK__GPIO1_23 IOMUX_PAD(0x5C8, 0x24C, 1, __NA_, 0, NO_PAD_CTRL) |
| 2009 | #define MX53_PAD_FEC_RXD1__GPIO1_26 (_MX53_PAD_FEC_RXD1__GPIO1_26 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 835 | #define MX53_PAD_FEC_REF_CLK__ESAI1_FSR IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, NO_PAD_CTRL) |
| 2010 | #define MX53_PAD_FEC_RXD1__ESAI1_FST (_MX53_PAD_FEC_RXD1__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL)) | 836 | #define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 IOMUX_PAD(0x5C8, 0x24C, 5, __NA_, 0, NO_PAD_CTRL) |
| 2011 | #define MX53_PAD_FEC_RXD1__MLB_MLBSIG (_MX53_PAD_FEC_RXD1__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL)) | 837 | #define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 IOMUX_PAD(0x5C8, 0x24C, 6, __NA_, 0, NO_PAD_CTRL) |
| 2012 | #define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 (_MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 838 | #define MX53_PAD_FEC_RX_ER__FEC_RX_ER IOMUX_PAD(0x5CC, 0x250, 0, __NA_, 0, NO_PAD_CTRL) |
| 2013 | #define MX53_PAD_FEC_RXD0__FEC_RDATA_0 (_MX53_PAD_FEC_RXD0__FEC_RDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 839 | #define MX53_PAD_FEC_RX_ER__GPIO1_24 IOMUX_PAD(0x5CC, 0x250, 1, __NA_, 0, NO_PAD_CTRL) |
| 2014 | #define MX53_PAD_FEC_RXD0__GPIO1_27 (_MX53_PAD_FEC_RXD0__GPIO1_27 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 840 | #define MX53_PAD_FEC_RX_ER__ESAI1_HCKR IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, NO_PAD_CTRL) |
| 2015 | #define MX53_PAD_FEC_RXD0__ESAI1_HCKT (_MX53_PAD_FEC_RXD0__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL)) | 841 | #define MX53_PAD_FEC_RX_ER__FEC_RX_CLK IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, NO_PAD_CTRL) |
| 2016 | #define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT (_MX53_PAD_FEC_RXD0__OSC32k_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) | 842 | #define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 IOMUX_PAD(0x5CC, 0x250, 4, __NA_, 0, NO_PAD_CTRL) |
| 2017 | #define MX53_PAD_FEC_TX_EN__FEC_TX_EN (_MX53_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) | 843 | #define MX53_PAD_FEC_CRS_DV__FEC_RX_DV IOMUX_PAD(0x5D0, 0x254, 0, __NA_, 0, NO_PAD_CTRL) |
| 2018 | #define MX53_PAD_FEC_TX_EN__GPIO1_28 (_MX53_PAD_FEC_TX_EN__GPIO1_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 844 | #define MX53_PAD_FEC_CRS_DV__GPIO1_25 IOMUX_PAD(0x5D0, 0x254, 1, __NA_, 0, NO_PAD_CTRL) |
| 2019 | #define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 (_MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 845 | #define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, NO_PAD_CTRL) |
| 2020 | #define MX53_PAD_FEC_TXD1__FEC_TDATA_1 (_MX53_PAD_FEC_TXD1__FEC_TDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 846 | #define MX53_PAD_FEC_RXD1__FEC_RDATA_1 IOMUX_PAD(0x5D4, 0x258, 0, __NA_, 0, NO_PAD_CTRL) |
| 2021 | #define MX53_PAD_FEC_TXD1__GPIO1_29 (_MX53_PAD_FEC_TXD1__GPIO1_29 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 847 | #define MX53_PAD_FEC_RXD1__GPIO1_26 IOMUX_PAD(0x5D4, 0x258, 1, __NA_, 0, NO_PAD_CTRL) |
| 2022 | #define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 (_MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 848 | #define MX53_PAD_FEC_RXD1__ESAI1_FST IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, NO_PAD_CTRL) |
| 2023 | #define MX53_PAD_FEC_TXD1__MLB_MLBCLK (_MX53_PAD_FEC_TXD1__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 849 | #define MX53_PAD_FEC_RXD1__MLB_MLBSIG IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, NO_PAD_CTRL) |
| 2024 | #define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK (_MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 850 | #define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 IOMUX_PAD(0x5D4, 0x258, 4, __NA_, 0, NO_PAD_CTRL) |
| 2025 | #define MX53_PAD_FEC_TXD0__FEC_TDATA_0 (_MX53_PAD_FEC_TXD0__FEC_TDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 851 | #define MX53_PAD_FEC_RXD0__FEC_RDATA_0 IOMUX_PAD(0x5D8, 0x25C, 0, __NA_, 0, NO_PAD_CTRL) |
| 2026 | #define MX53_PAD_FEC_TXD0__GPIO1_30 (_MX53_PAD_FEC_TXD0__GPIO1_30 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 852 | #define MX53_PAD_FEC_RXD0__GPIO1_27 IOMUX_PAD(0x5D8, 0x25C, 1, __NA_, 0, NO_PAD_CTRL) |
| 2027 | #define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 (_MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 853 | #define MX53_PAD_FEC_RXD0__ESAI1_HCKT IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, NO_PAD_CTRL) |
| 2028 | #define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 (_MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 854 | #define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT IOMUX_PAD(0x5D8, 0x25C, 3, __NA_, 0, NO_PAD_CTRL) |
| 2029 | #define MX53_PAD_FEC_MDC__FEC_MDC (_MX53_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 855 | #define MX53_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x5DC, 0x260, 0, __NA_, 0, NO_PAD_CTRL) |
| 2030 | #define MX53_PAD_FEC_MDC__GPIO1_31 (_MX53_PAD_FEC_MDC__GPIO1_31 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 856 | #define MX53_PAD_FEC_TX_EN__GPIO1_28 IOMUX_PAD(0x5DC, 0x260, 1, __NA_, 0, NO_PAD_CTRL) |
| 2031 | #define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 (_MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 857 | #define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, NO_PAD_CTRL) |
| 2032 | #define MX53_PAD_FEC_MDC__MLB_MLBDAT (_MX53_PAD_FEC_MDC__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL)) | 858 | #define MX53_PAD_FEC_TXD1__FEC_TDATA_1 IOMUX_PAD(0x5E0, 0x264, 0, __NA_, 0, NO_PAD_CTRL) |
| 2033 | #define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG (_MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL)) | 859 | #define MX53_PAD_FEC_TXD1__GPIO1_29 IOMUX_PAD(0x5E0, 0x264, 1, __NA_, 0, NO_PAD_CTRL) |
| 2034 | #define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 (_MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 860 | #define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, NO_PAD_CTRL) |
| 2035 | #define MX53_PAD_PATA_DIOW__PATA_DIOW (_MX53_PAD_PATA_DIOW__PATA_DIOW | MUX_PAD_CTRL(NO_PAD_CTRL)) | 861 | #define MX53_PAD_FEC_TXD1__MLB_MLBCLK IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, NO_PAD_CTRL) |
| 2036 | #define MX53_PAD_PATA_DIOW__GPIO6_17 (_MX53_PAD_PATA_DIOW__GPIO6_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 862 | #define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK IOMUX_PAD(0x5E0, 0x264, 4, __NA_, 0, NO_PAD_CTRL) |
| 2037 | #define MX53_PAD_PATA_DIOW__UART1_TXD_MUX (_MX53_PAD_PATA_DIOW__UART1_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 863 | #define MX53_PAD_FEC_TXD0__FEC_TDATA_0 IOMUX_PAD(0x5E4, 0x268, 0, __NA_, 0, NO_PAD_CTRL) |
| 2038 | #define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 (_MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 864 | #define MX53_PAD_FEC_TXD0__GPIO1_30 IOMUX_PAD(0x5E4, 0x268, 1, __NA_, 0, NO_PAD_CTRL) |
| 2039 | #define MX53_PAD_PATA_DMACK__PATA_DMACK (_MX53_PAD_PATA_DMACK__PATA_DMACK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 865 | #define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, NO_PAD_CTRL) |
| 2040 | #define MX53_PAD_PATA_DMACK__GPIO6_18 (_MX53_PAD_PATA_DMACK__GPIO6_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 866 | #define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 IOMUX_PAD(0x5E4, 0x268, 7, __NA_, 0, NO_PAD_CTRL) |
| 2041 | #define MX53_PAD_PATA_DMACK__UART1_RXD_MUX (_MX53_PAD_PATA_DMACK__UART1_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 867 | #define MX53_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x5E8, 0x26C, 0, __NA_, 0, NO_PAD_CTRL) |
| 2042 | #define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 (_MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 868 | #define MX53_PAD_FEC_MDC__GPIO1_31 IOMUX_PAD(0x5E8, 0x26C, 1, __NA_, 0, NO_PAD_CTRL) |
| 2043 | #define MX53_PAD_PATA_DMARQ__PATA_DMARQ (_MX53_PAD_PATA_DMARQ__PATA_DMARQ | MUX_PAD_CTRL(NO_PAD_CTRL)) | 869 | #define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, NO_PAD_CTRL) |
| 2044 | #define MX53_PAD_PATA_DMARQ__GPIO7_0 (_MX53_PAD_PATA_DMARQ__GPIO7_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 870 | #define MX53_PAD_FEC_MDC__MLB_MLBDAT IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, NO_PAD_CTRL) |
| 2045 | #define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX (_MX53_PAD_PATA_DMARQ__UART2_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 871 | #define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG IOMUX_PAD(0x5E8, 0x26C, 4, __NA_, 0, NO_PAD_CTRL) |
| 2046 | #define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 (_MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 872 | #define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 IOMUX_PAD(0x5E8, 0x26C, 7, __NA_, 0, NO_PAD_CTRL) |
| 2047 | #define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 (_MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 873 | #define MX53_PAD_PATA_DIOW__PATA_DIOW IOMUX_PAD(0x5F0, 0x270, 0, __NA_, 0, NO_PAD_CTRL) |
| 2048 | #define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN (_MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) | 874 | #define MX53_PAD_PATA_DIOW__GPIO6_17 IOMUX_PAD(0x5F0, 0x270, 1, __NA_, 0, NO_PAD_CTRL) |
| 2049 | #define MX53_PAD_PATA_BUFFER_EN__GPIO7_1 (_MX53_PAD_PATA_BUFFER_EN__GPIO7_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 875 | #define MX53_PAD_PATA_DIOW__UART1_TXD_MUX IOMUX_PAD(0x5F0, 0x270, 3, __NA_, 0, MX53_UART_PAD_CTRL) |
| 2050 | #define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX (_MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 876 | #define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 IOMUX_PAD(0x5F0, 0x270, 7, __NA_, 0, NO_PAD_CTRL) |
| 2051 | #define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 (_MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 877 | #define MX53_PAD_PATA_DMACK__PATA_DMACK IOMUX_PAD(0x5F4, 0x274, 0, __NA_, 0, NO_PAD_CTRL) |
| 2052 | #define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 (_MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 878 | #define MX53_PAD_PATA_DMACK__GPIO6_18 IOMUX_PAD(0x5F4, 0x274, 1, __NA_, 0, NO_PAD_CTRL) |
| 2053 | #define MX53_PAD_PATA_INTRQ__PATA_INTRQ (_MX53_PAD_PATA_INTRQ__PATA_INTRQ | MUX_PAD_CTRL(NO_PAD_CTRL)) | 879 | #define MX53_PAD_PATA_DMACK__UART1_RXD_MUX IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, MX53_UART_PAD_CTRL) |
| 2054 | #define MX53_PAD_PATA_INTRQ__GPIO7_2 (_MX53_PAD_PATA_INTRQ__GPIO7_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 880 | #define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 IOMUX_PAD(0x5F4, 0x274, 7, __NA_, 0, NO_PAD_CTRL) |
| 2055 | #define MX53_PAD_PATA_INTRQ__UART2_CTS (_MX53_PAD_PATA_INTRQ__UART2_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 881 | #define MX53_PAD_PATA_DMARQ__PATA_DMARQ IOMUX_PAD(0x5F8, 0x278, 0, __NA_, 0, NO_PAD_CTRL) |
| 2056 | #define MX53_PAD_PATA_INTRQ__CAN1_TXCAN (_MX53_PAD_PATA_INTRQ__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) | 882 | #define MX53_PAD_PATA_DMARQ__GPIO7_0 IOMUX_PAD(0x5F8, 0x278, 1, __NA_, 0, NO_PAD_CTRL) |
| 2057 | #define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 (_MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 883 | #define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX IOMUX_PAD(0x5F8, 0x278, 3, __NA_, 0, MX53_UART_PAD_CTRL) |
| 2058 | #define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 (_MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 884 | #define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 IOMUX_PAD(0x5F8, 0x278, 5, __NA_, 0, NO_PAD_CTRL) |
| 2059 | #define MX53_PAD_PATA_DIOR__PATA_DIOR (_MX53_PAD_PATA_DIOR__PATA_DIOR | MUX_PAD_CTRL(NO_PAD_CTRL)) | 885 | #define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 IOMUX_PAD(0x5F8, 0x278, 7, __NA_, 0, NO_PAD_CTRL) |
| 2060 | #define MX53_PAD_PATA_DIOR__GPIO7_3 (_MX53_PAD_PATA_DIOR__GPIO7_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 886 | #define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN IOMUX_PAD(0x5FC, 0x27C, 0, __NA_, 0, NO_PAD_CTRL) |
| 2061 | #define MX53_PAD_PATA_DIOR__UART2_RTS (_MX53_PAD_PATA_DIOR__UART2_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 887 | #define MX53_PAD_PATA_BUFFER_EN__GPIO7_1 IOMUX_PAD(0x5FC, 0x27C, 1, __NA_, 0, NO_PAD_CTRL) |
| 2062 | #define MX53_PAD_PATA_DIOR__CAN1_RXCAN (_MX53_PAD_PATA_DIOR__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) | 888 | #define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL) |
| 2063 | #define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 (_MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 889 | #define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 IOMUX_PAD(0x5FC, 0x27C, 5, __NA_, 0, NO_PAD_CTRL) |
| 2064 | #define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B (_MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL)) | 890 | #define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 IOMUX_PAD(0x5FC, 0x27C, 7, __NA_, 0, NO_PAD_CTRL) |
| 2065 | #define MX53_PAD_PATA_RESET_B__GPIO7_4 (_MX53_PAD_PATA_RESET_B__GPIO7_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 891 | #define MX53_PAD_PATA_INTRQ__PATA_INTRQ IOMUX_PAD(0x600, 0x280, 0, __NA_, 0, NO_PAD_CTRL) |
| 2066 | #define MX53_PAD_PATA_RESET_B__ESDHC3_CMD (_MX53_PAD_PATA_RESET_B__ESDHC3_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 892 | #define MX53_PAD_PATA_INTRQ__GPIO7_2 IOMUX_PAD(0x600, 0x280, 1, __NA_, 0, NO_PAD_CTRL) |
| 2067 | #define MX53_PAD_PATA_RESET_B__UART1_CTS (_MX53_PAD_PATA_RESET_B__UART1_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 893 | #define MX53_PAD_PATA_INTRQ__UART2_CTS IOMUX_PAD(0x600, 0x280, 3, __NA_, 0, MX53_UART_PAD_CTRL) |
| 2068 | #define MX53_PAD_PATA_RESET_B__CAN2_TXCAN (_MX53_PAD_PATA_RESET_B__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) | 894 | #define MX53_PAD_PATA_INTRQ__CAN1_TXCAN IOMUX_PAD(0x600, 0x280, 4, __NA_, 0, NO_PAD_CTRL) |
| 2069 | #define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 (_MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 895 | #define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 IOMUX_PAD(0x600, 0x280, 5, __NA_, 0, NO_PAD_CTRL) |
| 2070 | #define MX53_PAD_PATA_IORDY__PATA_IORDY (_MX53_PAD_PATA_IORDY__PATA_IORDY | MUX_PAD_CTRL(NO_PAD_CTRL)) | 896 | #define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 IOMUX_PAD(0x600, 0x280, 7, __NA_, 0, NO_PAD_CTRL) |
| 2071 | #define MX53_PAD_PATA_IORDY__GPIO7_5 (_MX53_PAD_PATA_IORDY__GPIO7_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 897 | #define MX53_PAD_PATA_DIOR__PATA_DIOR IOMUX_PAD(0x604, 0x284, 0, __NA_, 0, NO_PAD_CTRL) |
| 2072 | #define MX53_PAD_PATA_IORDY__ESDHC3_CLK (_MX53_PAD_PATA_IORDY__ESDHC3_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 898 | #define MX53_PAD_PATA_DIOR__GPIO7_3 IOMUX_PAD(0x604, 0x284, 1, __NA_, 0, NO_PAD_CTRL) |
| 2073 | #define MX53_PAD_PATA_IORDY__UART1_RTS (_MX53_PAD_PATA_IORDY__UART1_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 899 | #define MX53_PAD_PATA_DIOR__UART2_RTS IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL) |
| 2074 | #define MX53_PAD_PATA_IORDY__CAN2_RXCAN (_MX53_PAD_PATA_IORDY__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) | 900 | #define MX53_PAD_PATA_DIOR__CAN1_RXCAN IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, NO_PAD_CTRL) |
| 2075 | #define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 (_MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 901 | #define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 IOMUX_PAD(0x604, 0x284, 7, __NA_, 0, NO_PAD_CTRL) |
| 2076 | #define MX53_PAD_PATA_DA_0__PATA_DA_0 (_MX53_PAD_PATA_DA_0__PATA_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 902 | #define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B IOMUX_PAD(0x608, 0x288, 0, __NA_, 0, NO_PAD_CTRL) |
| 2077 | #define MX53_PAD_PATA_DA_0__GPIO7_6 (_MX53_PAD_PATA_DA_0__GPIO7_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 903 | #define MX53_PAD_PATA_RESET_B__GPIO7_4 IOMUX_PAD(0x608, 0x288, 1, __NA_, 0, NO_PAD_CTRL) |
| 2078 | #define MX53_PAD_PATA_DA_0__ESDHC3_RST (_MX53_PAD_PATA_DA_0__ESDHC3_RST | MUX_PAD_CTRL(NO_PAD_CTRL)) | 904 | #define MX53_PAD_PATA_RESET_B__ESDHC3_CMD IOMUX_PAD(0x608, 0x288, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2079 | #define MX53_PAD_PATA_DA_0__OWIRE_LINE (_MX53_PAD_PATA_DA_0__OWIRE_LINE | MUX_PAD_CTRL(NO_PAD_CTRL)) | 905 | #define MX53_PAD_PATA_RESET_B__UART1_CTS IOMUX_PAD(0x608, 0x288, 3, __NA_, 0, MX53_UART_PAD_CTRL) |
| 2080 | #define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 (_MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 906 | #define MX53_PAD_PATA_RESET_B__CAN2_TXCAN IOMUX_PAD(0x608, 0x288, 4, __NA_, 0, NO_PAD_CTRL) |
| 2081 | #define MX53_PAD_PATA_DA_1__PATA_DA_1 (_MX53_PAD_PATA_DA_1__PATA_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 907 | #define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 IOMUX_PAD(0x608, 0x288, 7, __NA_, 0, NO_PAD_CTRL) |
| 2082 | #define MX53_PAD_PATA_DA_1__GPIO7_7 (_MX53_PAD_PATA_DA_1__GPIO7_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 908 | #define MX53_PAD_PATA_IORDY__PATA_IORDY IOMUX_PAD(0x60C, 0x28C, 0, __NA_, 0, NO_PAD_CTRL) |
| 2083 | #define MX53_PAD_PATA_DA_1__ESDHC4_CMD (_MX53_PAD_PATA_DA_1__ESDHC4_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 909 | #define MX53_PAD_PATA_IORDY__GPIO7_5 IOMUX_PAD(0x60C, 0x28C, 1, __NA_, 0, NO_PAD_CTRL) |
| 2084 | #define MX53_PAD_PATA_DA_1__UART3_CTS (_MX53_PAD_PATA_DA_1__UART3_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 910 | #define MX53_PAD_PATA_IORDY__ESDHC3_CLK IOMUX_PAD(0x60C, 0x28C, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2085 | #define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 (_MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 911 | #define MX53_PAD_PATA_IORDY__UART1_RTS IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, MX53_UART_PAD_CTRL) |
| 2086 | #define MX53_PAD_PATA_DA_2__PATA_DA_2 (_MX53_PAD_PATA_DA_2__PATA_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 912 | #define MX53_PAD_PATA_IORDY__CAN2_RXCAN IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, NO_PAD_CTRL) |
| 2087 | #define MX53_PAD_PATA_DA_2__GPIO7_8 (_MX53_PAD_PATA_DA_2__GPIO7_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 913 | #define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 IOMUX_PAD(0x60C, 0x28C, 7, __NA_, 0, NO_PAD_CTRL) |
| 2088 | #define MX53_PAD_PATA_DA_2__ESDHC4_CLK (_MX53_PAD_PATA_DA_2__ESDHC4_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 914 | #define MX53_PAD_PATA_DA_0__PATA_DA_0 IOMUX_PAD(0x610, 0x290, 0, __NA_, 0, NO_PAD_CTRL) |
| 2089 | #define MX53_PAD_PATA_DA_2__UART3_RTS (_MX53_PAD_PATA_DA_2__UART3_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 915 | #define MX53_PAD_PATA_DA_0__GPIO7_6 IOMUX_PAD(0x610, 0x290, 1, __NA_, 0, NO_PAD_CTRL) |
| 2090 | #define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 (_MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 916 | #define MX53_PAD_PATA_DA_0__ESDHC3_RST IOMUX_PAD(0x610, 0x290, 2, __NA_, 0, NO_PAD_CTRL) |
| 2091 | #define MX53_PAD_PATA_CS_0__PATA_CS_0 (_MX53_PAD_PATA_CS_0__PATA_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 917 | #define MX53_PAD_PATA_DA_0__OWIRE_LINE IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, NO_PAD_CTRL) |
| 2092 | #define MX53_PAD_PATA_CS_0__GPIO7_9 (_MX53_PAD_PATA_CS_0__GPIO7_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 918 | #define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 IOMUX_PAD(0x610, 0x290, 7, __NA_, 0, NO_PAD_CTRL) |
| 2093 | #define MX53_PAD_PATA_CS_0__UART3_TXD_MUX (_MX53_PAD_PATA_CS_0__UART3_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 919 | #define MX53_PAD_PATA_DA_1__PATA_DA_1 IOMUX_PAD(0x614, 0x294, 0, __NA_, 0, NO_PAD_CTRL) |
| 2094 | #define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 (_MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 920 | #define MX53_PAD_PATA_DA_1__GPIO7_7 IOMUX_PAD(0x614, 0x294, 1, __NA_, 0, NO_PAD_CTRL) |
| 2095 | #define MX53_PAD_PATA_CS_1__PATA_CS_1 (_MX53_PAD_PATA_CS_1__PATA_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 921 | #define MX53_PAD_PATA_DA_1__ESDHC4_CMD IOMUX_PAD(0x614, 0x294, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2096 | #define MX53_PAD_PATA_CS_1__GPIO7_10 (_MX53_PAD_PATA_CS_1__GPIO7_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 922 | #define MX53_PAD_PATA_DA_1__UART3_CTS IOMUX_PAD(0x614, 0x294, 4, __NA_, 0, MX53_UART_PAD_CTRL) |
| 2097 | #define MX53_PAD_PATA_CS_1__UART3_RXD_MUX (_MX53_PAD_PATA_CS_1__UART3_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 923 | #define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 IOMUX_PAD(0x614, 0x294, 7, __NA_, 0, NO_PAD_CTRL) |
| 2098 | #define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 (_MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 924 | #define MX53_PAD_PATA_DA_2__PATA_DA_2 IOMUX_PAD(0x618, 0x298, 0, __NA_, 0, NO_PAD_CTRL) |
| 2099 | #define MX53_PAD_PATA_DATA0__PATA_DATA_0 (_MX53_PAD_PATA_DATA0__PATA_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 925 | #define MX53_PAD_PATA_DA_2__GPIO7_8 IOMUX_PAD(0x618, 0x298, 1, __NA_, 0, NO_PAD_CTRL) |
| 2100 | #define MX53_PAD_PATA_DATA0__GPIO2_0 (_MX53_PAD_PATA_DATA0__GPIO2_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 926 | #define MX53_PAD_PATA_DA_2__ESDHC4_CLK IOMUX_PAD(0x618, 0x298, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2101 | #define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 (_MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 927 | #define MX53_PAD_PATA_DA_2__UART3_RTS IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL) |
| 2102 | #define MX53_PAD_PATA_DATA0__ESDHC3_DAT4 (_MX53_PAD_PATA_DATA0__ESDHC3_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 928 | #define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 IOMUX_PAD(0x618, 0x298, 7, __NA_, 0, NO_PAD_CTRL) |
| 2103 | #define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 (_MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 929 | #define MX53_PAD_PATA_CS_0__PATA_CS_0 IOMUX_PAD(0x61C, 0x29C, 0, __NA_, 0, NO_PAD_CTRL) |
| 2104 | #define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 (_MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 930 | #define MX53_PAD_PATA_CS_0__GPIO7_9 IOMUX_PAD(0x61C, 0x29C, 1, __NA_, 0, NO_PAD_CTRL) |
| 2105 | #define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 (_MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 931 | #define MX53_PAD_PATA_CS_0__UART3_TXD_MUX IOMUX_PAD(0x61C, 0x29C, 4, __NA_, 0, MX53_UART_PAD_CTRL) |
| 2106 | #define MX53_PAD_PATA_DATA1__PATA_DATA_1 (_MX53_PAD_PATA_DATA1__PATA_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 932 | #define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 IOMUX_PAD(0x61C, 0x29C, 7, __NA_, 0, NO_PAD_CTRL) |
| 2107 | #define MX53_PAD_PATA_DATA1__GPIO2_1 (_MX53_PAD_PATA_DATA1__GPIO2_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 933 | #define MX53_PAD_PATA_CS_1__PATA_CS_1 IOMUX_PAD(0x620, 0x2A0, 0, __NA_, 0, NO_PAD_CTRL) |
| 2108 | #define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 (_MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 934 | #define MX53_PAD_PATA_CS_1__GPIO7_10 IOMUX_PAD(0x620, 0x2A0, 1, __NA_, 0, NO_PAD_CTRL) |
| 2109 | #define MX53_PAD_PATA_DATA1__ESDHC3_DAT5 (_MX53_PAD_PATA_DATA1__ESDHC3_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 935 | #define MX53_PAD_PATA_CS_1__UART3_RXD_MUX IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL) |
| 2110 | #define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 (_MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 936 | #define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 IOMUX_PAD(0x620, 0x2A0, 7, __NA_, 0, NO_PAD_CTRL) |
| 2111 | #define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 (_MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 937 | #define MX53_PAD_PATA_DATA0__PATA_DATA_0 IOMUX_PAD(0x628, 0x2A4, 0, __NA_, 0, NO_PAD_CTRL) |
| 2112 | #define MX53_PAD_PATA_DATA2__PATA_DATA_2 (_MX53_PAD_PATA_DATA2__PATA_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 938 | #define MX53_PAD_PATA_DATA0__GPIO2_0 IOMUX_PAD(0x628, 0x2A4, 1, __NA_, 0, NO_PAD_CTRL) |
| 2113 | #define MX53_PAD_PATA_DATA2__GPIO2_2 (_MX53_PAD_PATA_DATA2__GPIO2_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 939 | #define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 IOMUX_PAD(0x628, 0x2A4, 3, __NA_, 0, NO_PAD_CTRL) |
| 2114 | #define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 (_MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 940 | #define MX53_PAD_PATA_DATA0__ESDHC3_DAT4 IOMUX_PAD(0x628, 0x2A4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2115 | #define MX53_PAD_PATA_DATA2__ESDHC3_DAT6 (_MX53_PAD_PATA_DATA2__ESDHC3_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 941 | #define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 IOMUX_PAD(0x628, 0x2A4, 5, __NA_, 0, NO_PAD_CTRL) |
| 2116 | #define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 (_MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 942 | #define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 IOMUX_PAD(0x628, 0x2A4, 6, __NA_, 0, NO_PAD_CTRL) |
| 2117 | #define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 (_MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 943 | #define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 IOMUX_PAD(0x628, 0x2A4, 7, __NA_, 0, NO_PAD_CTRL) |
| 2118 | #define MX53_PAD_PATA_DATA3__PATA_DATA_3 (_MX53_PAD_PATA_DATA3__PATA_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 944 | #define MX53_PAD_PATA_DATA1__PATA_DATA_1 IOMUX_PAD(0x62C, 0x2A8, 0, __NA_, 0, NO_PAD_CTRL) |
| 2119 | #define MX53_PAD_PATA_DATA3__GPIO2_3 (_MX53_PAD_PATA_DATA3__GPIO2_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 945 | #define MX53_PAD_PATA_DATA1__GPIO2_1 IOMUX_PAD(0x62C, 0x2A8, 1, __NA_, 0, NO_PAD_CTRL) |
| 2120 | #define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 (_MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 946 | #define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 IOMUX_PAD(0x62C, 0x2A8, 3, __NA_, 0, NO_PAD_CTRL) |
| 2121 | #define MX53_PAD_PATA_DATA3__ESDHC3_DAT7 (_MX53_PAD_PATA_DATA3__ESDHC3_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 947 | #define MX53_PAD_PATA_DATA1__ESDHC3_DAT5 IOMUX_PAD(0x62C, 0x2A8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2122 | #define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 (_MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 948 | #define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 IOMUX_PAD(0x62C, 0x2A8, 5, __NA_, 0, NO_PAD_CTRL) |
| 2123 | #define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 (_MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 949 | #define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 IOMUX_PAD(0x62C, 0x2A8, 6, __NA_, 0, NO_PAD_CTRL) |
| 2124 | #define MX53_PAD_PATA_DATA4__PATA_DATA_4 (_MX53_PAD_PATA_DATA4__PATA_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 950 | #define MX53_PAD_PATA_DATA2__PATA_DATA_2 IOMUX_PAD(0x630, 0x2AC, 0, __NA_, 0, NO_PAD_CTRL) |
| 2125 | #define MX53_PAD_PATA_DATA4__GPIO2_4 (_MX53_PAD_PATA_DATA4__GPIO2_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 951 | #define MX53_PAD_PATA_DATA2__GPIO2_2 IOMUX_PAD(0x630, 0x2AC, 1, __NA_, 0, NO_PAD_CTRL) |
| 2126 | #define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 (_MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 952 | #define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 IOMUX_PAD(0x630, 0x2AC, 3, __NA_, 0, NO_PAD_CTRL) |
| 2127 | #define MX53_PAD_PATA_DATA4__ESDHC4_DAT4 (_MX53_PAD_PATA_DATA4__ESDHC4_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 953 | #define MX53_PAD_PATA_DATA2__ESDHC3_DAT6 IOMUX_PAD(0x630, 0x2AC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2128 | #define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 (_MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 954 | #define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 IOMUX_PAD(0x630, 0x2AC, 5, __NA_, 0, NO_PAD_CTRL) |
| 2129 | #define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 (_MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 955 | #define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 IOMUX_PAD(0x630, 0x2AC, 6, __NA_, 0, NO_PAD_CTRL) |
| 2130 | #define MX53_PAD_PATA_DATA5__PATA_DATA_5 (_MX53_PAD_PATA_DATA5__PATA_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 956 | #define MX53_PAD_PATA_DATA3__PATA_DATA_3 IOMUX_PAD(0x634, 0x2B0, 0, __NA_, 0, NO_PAD_CTRL) |
| 2131 | #define MX53_PAD_PATA_DATA5__GPIO2_5 (_MX53_PAD_PATA_DATA5__GPIO2_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 957 | #define MX53_PAD_PATA_DATA3__GPIO2_3 IOMUX_PAD(0x634, 0x2B0, 1, __NA_, 0, NO_PAD_CTRL) |
| 2132 | #define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 (_MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 958 | #define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 IOMUX_PAD(0x634, 0x2B0, 3, __NA_, 0, NO_PAD_CTRL) |
| 2133 | #define MX53_PAD_PATA_DATA5__ESDHC4_DAT5 (_MX53_PAD_PATA_DATA5__ESDHC4_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 959 | #define MX53_PAD_PATA_DATA3__ESDHC3_DAT7 IOMUX_PAD(0x634, 0x2B0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2134 | #define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 (_MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 960 | #define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 IOMUX_PAD(0x634, 0x2B0, 5, __NA_, 0, NO_PAD_CTRL) |
| 2135 | #define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 (_MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 961 | #define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 IOMUX_PAD(0x634, 0x2B0, 6, __NA_, 0, NO_PAD_CTRL) |
| 2136 | #define MX53_PAD_PATA_DATA6__PATA_DATA_6 (_MX53_PAD_PATA_DATA6__PATA_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 962 | #define MX53_PAD_PATA_DATA4__PATA_DATA_4 IOMUX_PAD(0x638, 0x2B4, 0, __NA_, 0, NO_PAD_CTRL) |
| 2137 | #define MX53_PAD_PATA_DATA6__GPIO2_6 (_MX53_PAD_PATA_DATA6__GPIO2_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 963 | #define MX53_PAD_PATA_DATA4__GPIO2_4 IOMUX_PAD(0x638, 0x2B4, 1, __NA_, 0, NO_PAD_CTRL) |
| 2138 | #define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 (_MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 964 | #define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 IOMUX_PAD(0x638, 0x2B4, 3, __NA_, 0, NO_PAD_CTRL) |
| 2139 | #define MX53_PAD_PATA_DATA6__ESDHC4_DAT6 (_MX53_PAD_PATA_DATA6__ESDHC4_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 965 | #define MX53_PAD_PATA_DATA4__ESDHC4_DAT4 IOMUX_PAD(0x638, 0x2B4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2140 | #define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 (_MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 966 | #define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 IOMUX_PAD(0x638, 0x2B4, 5, __NA_, 0, NO_PAD_CTRL) |
| 2141 | #define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 (_MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 967 | #define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 IOMUX_PAD(0x638, 0x2B4, 6, __NA_, 0, NO_PAD_CTRL) |
| 2142 | #define MX53_PAD_PATA_DATA7__PATA_DATA_7 (_MX53_PAD_PATA_DATA7__PATA_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 968 | #define MX53_PAD_PATA_DATA5__PATA_DATA_5 IOMUX_PAD(0x63C, 0x2B8, 0, __NA_, 0, NO_PAD_CTRL) |
| 2143 | #define MX53_PAD_PATA_DATA7__GPIO2_7 (_MX53_PAD_PATA_DATA7__GPIO2_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 969 | #define MX53_PAD_PATA_DATA5__GPIO2_5 IOMUX_PAD(0x63C, 0x2B8, 1, __NA_, 0, NO_PAD_CTRL) |
| 2144 | #define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 (_MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 970 | #define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 IOMUX_PAD(0x63C, 0x2B8, 3, __NA_, 0, NO_PAD_CTRL) |
| 2145 | #define MX53_PAD_PATA_DATA7__ESDHC4_DAT7 (_MX53_PAD_PATA_DATA7__ESDHC4_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 971 | #define MX53_PAD_PATA_DATA5__ESDHC4_DAT5 IOMUX_PAD(0x63C, 0x2B8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2146 | #define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 (_MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 972 | #define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 IOMUX_PAD(0x63C, 0x2B8, 5, __NA_, 0, NO_PAD_CTRL) |
| 2147 | #define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 (_MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 973 | #define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 IOMUX_PAD(0x63C, 0x2B8, 6, __NA_, 0, NO_PAD_CTRL) |
| 2148 | #define MX53_PAD_PATA_DATA8__PATA_DATA_8 (_MX53_PAD_PATA_DATA8__PATA_DATA_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 974 | #define MX53_PAD_PATA_DATA6__PATA_DATA_6 IOMUX_PAD(0x640, 0x2BC, 0, __NA_, 0, NO_PAD_CTRL) |
| 2149 | #define MX53_PAD_PATA_DATA8__GPIO2_8 (_MX53_PAD_PATA_DATA8__GPIO2_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 975 | #define MX53_PAD_PATA_DATA6__GPIO2_6 IOMUX_PAD(0x640, 0x2BC, 1, __NA_, 0, NO_PAD_CTRL) |
| 2150 | #define MX53_PAD_PATA_DATA8__ESDHC1_DAT4 (_MX53_PAD_PATA_DATA8__ESDHC1_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 976 | #define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 IOMUX_PAD(0x640, 0x2BC, 3, __NA_, 0, NO_PAD_CTRL) |
| 2151 | #define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 (_MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 977 | #define MX53_PAD_PATA_DATA6__ESDHC4_DAT6 IOMUX_PAD(0x640, 0x2BC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2152 | #define MX53_PAD_PATA_DATA8__ESDHC3_DAT0 (_MX53_PAD_PATA_DATA8__ESDHC3_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 978 | #define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 IOMUX_PAD(0x640, 0x2BC, 5, __NA_, 0, NO_PAD_CTRL) |
| 2153 | #define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 (_MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 979 | #define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 IOMUX_PAD(0x640, 0x2BC, 6, __NA_, 0, NO_PAD_CTRL) |
| 2154 | #define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 (_MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 980 | #define MX53_PAD_PATA_DATA7__PATA_DATA_7 IOMUX_PAD(0x644, 0x2C0, 0, __NA_, 0, NO_PAD_CTRL) |
| 2155 | #define MX53_PAD_PATA_DATA9__PATA_DATA_9 (_MX53_PAD_PATA_DATA9__PATA_DATA_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 981 | #define MX53_PAD_PATA_DATA7__GPIO2_7 IOMUX_PAD(0x644, 0x2C0, 1, __NA_, 0, NO_PAD_CTRL) |
| 2156 | #define MX53_PAD_PATA_DATA9__GPIO2_9 (_MX53_PAD_PATA_DATA9__GPIO2_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 982 | #define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 IOMUX_PAD(0x644, 0x2C0, 3, __NA_, 0, NO_PAD_CTRL) |
| 2157 | #define MX53_PAD_PATA_DATA9__ESDHC1_DAT5 (_MX53_PAD_PATA_DATA9__ESDHC1_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 983 | #define MX53_PAD_PATA_DATA7__ESDHC4_DAT7 IOMUX_PAD(0x644, 0x2C0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2158 | #define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 (_MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 984 | #define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 IOMUX_PAD(0x644, 0x2C0, 5, __NA_, 0, NO_PAD_CTRL) |
| 2159 | #define MX53_PAD_PATA_DATA9__ESDHC3_DAT1 (_MX53_PAD_PATA_DATA9__ESDHC3_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 985 | #define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 IOMUX_PAD(0x644, 0x2C0, 6, __NA_, 0, NO_PAD_CTRL) |
| 2160 | #define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 (_MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 986 | #define MX53_PAD_PATA_DATA8__PATA_DATA_8 IOMUX_PAD(0x648, 0x2C4, 0, __NA_, 0, NO_PAD_CTRL) |
| 2161 | #define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 (_MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 987 | #define MX53_PAD_PATA_DATA8__GPIO2_8 IOMUX_PAD(0x648, 0x2C4, 1, __NA_, 0, NO_PAD_CTRL) |
| 2162 | #define MX53_PAD_PATA_DATA10__PATA_DATA_10 (_MX53_PAD_PATA_DATA10__PATA_DATA_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 988 | #define MX53_PAD_PATA_DATA8__ESDHC1_DAT4 IOMUX_PAD(0x648, 0x2C4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2163 | #define MX53_PAD_PATA_DATA10__GPIO2_10 (_MX53_PAD_PATA_DATA10__GPIO2_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 989 | #define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 IOMUX_PAD(0x648, 0x2C4, 3, __NA_, 0, NO_PAD_CTRL) |
| 2164 | #define MX53_PAD_PATA_DATA10__ESDHC1_DAT6 (_MX53_PAD_PATA_DATA10__ESDHC1_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 990 | #define MX53_PAD_PATA_DATA8__ESDHC3_DAT0 IOMUX_PAD(0x648, 0x2C4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2165 | #define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 (_MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 991 | #define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 IOMUX_PAD(0x648, 0x2C4, 5, __NA_, 0, NO_PAD_CTRL) |
| 2166 | #define MX53_PAD_PATA_DATA10__ESDHC3_DAT2 (_MX53_PAD_PATA_DATA10__ESDHC3_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 992 | #define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 IOMUX_PAD(0x648, 0x2C4, 6, __NA_, 0, NO_PAD_CTRL) |
| 2167 | #define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 (_MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 993 | #define MX53_PAD_PATA_DATA9__PATA_DATA_9 IOMUX_PAD(0x64C, 0x2C8, 0, __NA_, 0, NO_PAD_CTRL) |
| 2168 | #define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 (_MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 994 | #define MX53_PAD_PATA_DATA9__GPIO2_9 IOMUX_PAD(0x64C, 0x2C8, 1, __NA_, 0, NO_PAD_CTRL) |
| 2169 | #define MX53_PAD_PATA_DATA11__PATA_DATA_11 (_MX53_PAD_PATA_DATA11__PATA_DATA_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 995 | #define MX53_PAD_PATA_DATA9__ESDHC1_DAT5 IOMUX_PAD(0x64C, 0x2C8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2170 | #define MX53_PAD_PATA_DATA11__GPIO2_11 (_MX53_PAD_PATA_DATA11__GPIO2_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 996 | #define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 IOMUX_PAD(0x64C, 0x2C8, 3, __NA_, 0, NO_PAD_CTRL) |
| 2171 | #define MX53_PAD_PATA_DATA11__ESDHC1_DAT7 (_MX53_PAD_PATA_DATA11__ESDHC1_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 997 | #define MX53_PAD_PATA_DATA9__ESDHC3_DAT1 IOMUX_PAD(0x64C, 0x2C8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2172 | #define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 (_MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 998 | #define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 IOMUX_PAD(0x64C, 0x2C8, 5, __NA_, 0, NO_PAD_CTRL) |
| 2173 | #define MX53_PAD_PATA_DATA11__ESDHC3_DAT3 (_MX53_PAD_PATA_DATA11__ESDHC3_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 999 | #define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 IOMUX_PAD(0x64C, 0x2C8, 6, __NA_, 0, NO_PAD_CTRL) |
| 2174 | #define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 (_MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1000 | #define MX53_PAD_PATA_DATA10__PATA_DATA_10 IOMUX_PAD(0x650, 0x2CC, 0, __NA_, 0, NO_PAD_CTRL) |
| 2175 | #define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 (_MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1001 | #define MX53_PAD_PATA_DATA10__GPIO2_10 IOMUX_PAD(0x650, 0x2CC, 1, __NA_, 0, NO_PAD_CTRL) |
| 2176 | #define MX53_PAD_PATA_DATA12__PATA_DATA_12 (_MX53_PAD_PATA_DATA12__PATA_DATA_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1002 | #define MX53_PAD_PATA_DATA10__ESDHC1_DAT6 IOMUX_PAD(0x650, 0x2CC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2177 | #define MX53_PAD_PATA_DATA12__GPIO2_12 (_MX53_PAD_PATA_DATA12__GPIO2_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1003 | #define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 IOMUX_PAD(0x650, 0x2CC, 3, __NA_, 0, NO_PAD_CTRL) |
| 2178 | #define MX53_PAD_PATA_DATA12__ESDHC2_DAT4 (_MX53_PAD_PATA_DATA12__ESDHC2_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 1004 | #define MX53_PAD_PATA_DATA10__ESDHC3_DAT2 IOMUX_PAD(0x650, 0x2CC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2179 | #define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 (_MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1005 | #define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 IOMUX_PAD(0x650, 0x2CC, 5, __NA_, 0, NO_PAD_CTRL) |
| 2180 | #define MX53_PAD_PATA_DATA12__ESDHC4_DAT0 (_MX53_PAD_PATA_DATA12__ESDHC4_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 1006 | #define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 IOMUX_PAD(0x650, 0x2CC, 6, __NA_, 0, NO_PAD_CTRL) |
| 2181 | #define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 (_MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1007 | #define MX53_PAD_PATA_DATA11__PATA_DATA_11 IOMUX_PAD(0x654, 0x2D0, 0, __NA_, 0, NO_PAD_CTRL) |
| 2182 | #define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 (_MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1008 | #define MX53_PAD_PATA_DATA11__GPIO2_11 IOMUX_PAD(0x654, 0x2D0, 1, __NA_, 0, NO_PAD_CTRL) |
| 2183 | #define MX53_PAD_PATA_DATA13__PATA_DATA_13 (_MX53_PAD_PATA_DATA13__PATA_DATA_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1009 | #define MX53_PAD_PATA_DATA11__ESDHC1_DAT7 IOMUX_PAD(0x654, 0x2D0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2184 | #define MX53_PAD_PATA_DATA13__GPIO2_13 (_MX53_PAD_PATA_DATA13__GPIO2_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1010 | #define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 IOMUX_PAD(0x654, 0x2D0, 3, __NA_, 0, NO_PAD_CTRL) |
| 2185 | #define MX53_PAD_PATA_DATA13__ESDHC2_DAT5 (_MX53_PAD_PATA_DATA13__ESDHC2_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 1011 | #define MX53_PAD_PATA_DATA11__ESDHC3_DAT3 IOMUX_PAD(0x654, 0x2D0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2186 | #define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 (_MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1012 | #define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 IOMUX_PAD(0x654, 0x2D0, 5, __NA_, 0, NO_PAD_CTRL) |
| 2187 | #define MX53_PAD_PATA_DATA13__ESDHC4_DAT1 (_MX53_PAD_PATA_DATA13__ESDHC4_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 1013 | #define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 IOMUX_PAD(0x654, 0x2D0, 6, __NA_, 0, NO_PAD_CTRL) |
| 2188 | #define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 (_MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1014 | #define MX53_PAD_PATA_DATA12__PATA_DATA_12 IOMUX_PAD(0x658, 0x2D4, 0, __NA_, 0, NO_PAD_CTRL) |
| 2189 | #define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 (_MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1015 | #define MX53_PAD_PATA_DATA12__GPIO2_12 IOMUX_PAD(0x658, 0x2D4, 1, __NA_, 0, NO_PAD_CTRL) |
| 2190 | #define MX53_PAD_PATA_DATA14__PATA_DATA_14 (_MX53_PAD_PATA_DATA14__PATA_DATA_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1016 | #define MX53_PAD_PATA_DATA12__ESDHC2_DAT4 IOMUX_PAD(0x658, 0x2D4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2191 | #define MX53_PAD_PATA_DATA14__GPIO2_14 (_MX53_PAD_PATA_DATA14__GPIO2_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1017 | #define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 IOMUX_PAD(0x658, 0x2D4, 3, __NA_, 0, NO_PAD_CTRL) |
| 2192 | #define MX53_PAD_PATA_DATA14__ESDHC2_DAT6 (_MX53_PAD_PATA_DATA14__ESDHC2_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 1018 | #define MX53_PAD_PATA_DATA12__ESDHC4_DAT0 IOMUX_PAD(0x658, 0x2D4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2193 | #define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 (_MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1019 | #define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 IOMUX_PAD(0x658, 0x2D4, 5, __NA_, 0, NO_PAD_CTRL) |
| 2194 | #define MX53_PAD_PATA_DATA14__ESDHC4_DAT2 (_MX53_PAD_PATA_DATA14__ESDHC4_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 1020 | #define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 IOMUX_PAD(0x658, 0x2D4, 6, __NA_, 0, NO_PAD_CTRL) |
| 2195 | #define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 (_MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1021 | #define MX53_PAD_PATA_DATA13__PATA_DATA_13 IOMUX_PAD(0x65C, 0x2D8, 0, __NA_, 0, NO_PAD_CTRL) |
| 2196 | #define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 (_MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1022 | #define MX53_PAD_PATA_DATA13__GPIO2_13 IOMUX_PAD(0x65C, 0x2D8, 1, __NA_, 0, NO_PAD_CTRL) |
| 2197 | #define MX53_PAD_PATA_DATA15__PATA_DATA_15 (_MX53_PAD_PATA_DATA15__PATA_DATA_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1023 | #define MX53_PAD_PATA_DATA13__ESDHC2_DAT5 IOMUX_PAD(0x65C, 0x2D8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2198 | #define MX53_PAD_PATA_DATA15__GPIO2_15 (_MX53_PAD_PATA_DATA15__GPIO2_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1024 | #define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 IOMUX_PAD(0x65C, 0x2D8, 3, __NA_, 0, NO_PAD_CTRL) |
| 2199 | #define MX53_PAD_PATA_DATA15__ESDHC2_DAT7 (_MX53_PAD_PATA_DATA15__ESDHC2_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 1025 | #define MX53_PAD_PATA_DATA13__ESDHC4_DAT1 IOMUX_PAD(0x65C, 0x2D8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2200 | #define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 (_MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1026 | #define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 IOMUX_PAD(0x65C, 0x2D8, 5, __NA_, 0, NO_PAD_CTRL) |
| 2201 | #define MX53_PAD_PATA_DATA15__ESDHC4_DAT3 (_MX53_PAD_PATA_DATA15__ESDHC4_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 1027 | #define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 IOMUX_PAD(0x65C, 0x2D8, 6, __NA_, 0, NO_PAD_CTRL) |
| 2202 | #define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 (_MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1028 | #define MX53_PAD_PATA_DATA14__PATA_DATA_14 IOMUX_PAD(0x660, 0x2DC, 0, __NA_, 0, NO_PAD_CTRL) |
| 2203 | #define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 (_MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1029 | #define MX53_PAD_PATA_DATA14__GPIO2_14 IOMUX_PAD(0x660, 0x2DC, 1, __NA_, 0, NO_PAD_CTRL) |
| 2204 | #define MX53_PAD_SD1_DATA0__ESDHC1_DAT0 (_MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 1030 | #define MX53_PAD_PATA_DATA14__ESDHC2_DAT6 IOMUX_PAD(0x660, 0x2DC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2205 | #define MX53_PAD_SD1_DATA0__GPIO1_16 (_MX53_PAD_SD1_DATA0__GPIO1_16 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1031 | #define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 IOMUX_PAD(0x660, 0x2DC, 3, __NA_, 0, NO_PAD_CTRL) |
| 2206 | #define MX53_PAD_SD1_DATA0__GPT_CAPIN1 (_MX53_PAD_SD1_DATA0__GPT_CAPIN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1032 | #define MX53_PAD_PATA_DATA14__ESDHC4_DAT2 IOMUX_PAD(0x660, 0x2DC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2207 | #define MX53_PAD_SD1_DATA0__CSPI_MISO (_MX53_PAD_SD1_DATA0__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1033 | #define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 IOMUX_PAD(0x660, 0x2DC, 5, __NA_, 0, NO_PAD_CTRL) |
| 2208 | #define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP (_MX53_PAD_SD1_DATA0__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1034 | #define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 IOMUX_PAD(0x660, 0x2DC, 6, __NA_, 0, NO_PAD_CTRL) |
| 2209 | #define MX53_PAD_SD1_DATA1__ESDHC1_DAT1 (_MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 1035 | #define MX53_PAD_PATA_DATA15__PATA_DATA_15 IOMUX_PAD(0x664, 0x2E0, 0, __NA_, 0, NO_PAD_CTRL) |
| 2210 | #define MX53_PAD_SD1_DATA1__GPIO1_17 (_MX53_PAD_SD1_DATA1__GPIO1_17 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1036 | #define MX53_PAD_PATA_DATA15__GPIO2_15 IOMUX_PAD(0x664, 0x2E0, 1, __NA_, 0, NO_PAD_CTRL) |
| 2211 | #define MX53_PAD_SD1_DATA1__GPT_CAPIN2 (_MX53_PAD_SD1_DATA1__GPT_CAPIN2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1037 | #define MX53_PAD_PATA_DATA15__ESDHC2_DAT7 IOMUX_PAD(0x664, 0x2E0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2212 | #define MX53_PAD_SD1_DATA1__CSPI_SS0 (_MX53_PAD_SD1_DATA1__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1038 | #define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 IOMUX_PAD(0x664, 0x2E0, 3, __NA_, 0, NO_PAD_CTRL) |
| 2213 | #define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP (_MX53_PAD_SD1_DATA1__CCM_PLL4_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1039 | #define MX53_PAD_PATA_DATA15__ESDHC4_DAT3 IOMUX_PAD(0x664, 0x2E0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2214 | #define MX53_PAD_SD1_CMD__ESDHC1_CMD (_MX53_PAD_SD1_CMD__ESDHC1_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 1040 | #define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 IOMUX_PAD(0x664, 0x2E0, 5, __NA_, 0, NO_PAD_CTRL) |
| 2215 | #define MX53_PAD_SD1_CMD__GPIO1_18 (_MX53_PAD_SD1_CMD__GPIO1_18 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1041 | #define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 IOMUX_PAD(0x664, 0x2E0, 6, __NA_, 0, NO_PAD_CTRL) |
| 2216 | #define MX53_PAD_SD1_CMD__GPT_CMPOUT1 (_MX53_PAD_SD1_CMD__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1042 | #define MX53_PAD_SD1_DATA0__ESDHC1_DAT0 IOMUX_PAD(0x66C, 0x2E4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2217 | #define MX53_PAD_SD1_CMD__CSPI_MOSI (_MX53_PAD_SD1_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1043 | #define MX53_PAD_SD1_DATA0__GPIO1_16 IOMUX_PAD(0x66C, 0x2E4, 1, __NA_, 0, NO_PAD_CTRL) |
| 2218 | #define MX53_PAD_SD1_CMD__CCM_PLL1_BYP (_MX53_PAD_SD1_CMD__CCM_PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1044 | #define MX53_PAD_SD1_DATA0__GPT_CAPIN1 IOMUX_PAD(0x66C, 0x2E4, 3, __NA_, 0, NO_PAD_CTRL) |
| 2219 | #define MX53_PAD_SD1_DATA2__ESDHC1_DAT2 (_MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 1045 | #define MX53_PAD_SD1_DATA0__CSPI_MISO IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, NO_PAD_CTRL) |
| 2220 | #define MX53_PAD_SD1_DATA2__GPIO1_19 (_MX53_PAD_SD1_DATA2__GPIO1_19 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1046 | #define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, NO_PAD_CTRL) |
| 2221 | #define MX53_PAD_SD1_DATA2__GPT_CMPOUT2 (_MX53_PAD_SD1_DATA2__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1047 | #define MX53_PAD_SD1_DATA1__ESDHC1_DAT1 IOMUX_PAD(0x670, 0x2E8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2222 | #define MX53_PAD_SD1_DATA2__PWM2_PWMO (_MX53_PAD_SD1_DATA2__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1048 | #define MX53_PAD_SD1_DATA1__GPIO1_17 IOMUX_PAD(0x670, 0x2E8, 1, __NA_, 0, NO_PAD_CTRL) |
| 2223 | #define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B (_MX53_PAD_SD1_DATA2__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1049 | #define MX53_PAD_SD1_DATA1__GPT_CAPIN2 IOMUX_PAD(0x670, 0x2E8, 3, __NA_, 0, NO_PAD_CTRL) |
| 2224 | #define MX53_PAD_SD1_DATA2__CSPI_SS1 (_MX53_PAD_SD1_DATA2__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1050 | #define MX53_PAD_SD1_DATA1__CSPI_SS0 IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, NO_PAD_CTRL) |
| 2225 | #define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB (_MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1051 | #define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, NO_PAD_CTRL) |
| 2226 | #define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP (_MX53_PAD_SD1_DATA2__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1052 | #define MX53_PAD_SD1_CMD__ESDHC1_CMD IOMUX_PAD(0x674, 0x2EC, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2227 | #define MX53_PAD_SD1_CLK__ESDHC1_CLK (_MX53_PAD_SD1_CLK__ESDHC1_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 1053 | #define MX53_PAD_SD1_CMD__GPIO1_18 IOMUX_PAD(0x674, 0x2EC, 1, __NA_, 0, NO_PAD_CTRL) |
| 2228 | #define MX53_PAD_SD1_CLK__GPIO1_20 (_MX53_PAD_SD1_CLK__GPIO1_20 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1054 | #define MX53_PAD_SD1_CMD__GPT_CMPOUT1 IOMUX_PAD(0x674, 0x2EC, 3, __NA_, 0, NO_PAD_CTRL) |
| 2229 | #define MX53_PAD_SD1_CLK__OSC32k_32K_OUT (_MX53_PAD_SD1_CLK__OSC32k_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1055 | #define MX53_PAD_SD1_CMD__CSPI_MOSI IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, NO_PAD_CTRL) |
| 2230 | #define MX53_PAD_SD1_CLK__GPT_CLKIN (_MX53_PAD_SD1_CLK__GPT_CLKIN | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1056 | #define MX53_PAD_SD1_CMD__CCM_PLL1_BYP IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, NO_PAD_CTRL) |
| 2231 | #define MX53_PAD_SD1_CLK__CSPI_SCLK (_MX53_PAD_SD1_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1057 | #define MX53_PAD_SD1_DATA2__ESDHC1_DAT2 IOMUX_PAD(0x678, 0x2F0, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2232 | #define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 (_MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1058 | #define MX53_PAD_SD1_DATA2__GPIO1_19 IOMUX_PAD(0x678, 0x2F0, 1, __NA_, 0, NO_PAD_CTRL) |
| 2233 | #define MX53_PAD_SD1_DATA3__ESDHC1_DAT3 (_MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 1059 | #define MX53_PAD_SD1_DATA2__GPT_CMPOUT2 IOMUX_PAD(0x678, 0x2F0, 2, __NA_, 0, NO_PAD_CTRL) |
| 2234 | #define MX53_PAD_SD1_DATA3__GPIO1_21 (_MX53_PAD_SD1_DATA3__GPIO1_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1060 | #define MX53_PAD_SD1_DATA2__PWM2_PWMO IOMUX_PAD(0x678, 0x2F0, 3, __NA_, 0, NO_PAD_CTRL) |
| 2235 | #define MX53_PAD_SD1_DATA3__GPT_CMPOUT3 (_MX53_PAD_SD1_DATA3__GPT_CMPOUT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1061 | #define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B IOMUX_PAD(0x678, 0x2F0, 4, __NA_, 0, NO_PAD_CTRL) |
| 2236 | #define MX53_PAD_SD1_DATA3__PWM1_PWMO (_MX53_PAD_SD1_DATA3__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1062 | #define MX53_PAD_SD1_DATA2__CSPI_SS1 IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, NO_PAD_CTRL) |
| 2237 | #define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B (_MX53_PAD_SD1_DATA3__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1063 | #define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB IOMUX_PAD(0x678, 0x2F0, 6, __NA_, 0, NO_PAD_CTRL) |
| 2238 | #define MX53_PAD_SD1_DATA3__CSPI_SS2 (_MX53_PAD_SD1_DATA3__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1064 | #define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, NO_PAD_CTRL) |
| 2239 | #define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB (_MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1065 | #define MX53_PAD_SD1_CLK__ESDHC1_CLK IOMUX_PAD(0x67C, 0x2F4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2240 | #define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 (_MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1066 | #define MX53_PAD_SD1_CLK__GPIO1_20 IOMUX_PAD(0x67C, 0x2F4, 1, __NA_, 0, NO_PAD_CTRL) |
| 2241 | #define MX53_PAD_SD2_CLK__ESDHC2_CLK (_MX53_PAD_SD2_CLK__ESDHC2_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 1067 | #define MX53_PAD_SD1_CLK__OSC32k_32K_OUT IOMUX_PAD(0x67C, 0x2F4, 2, __NA_, 0, NO_PAD_CTRL) |
| 2242 | #define MX53_PAD_SD2_CLK__GPIO1_10 (_MX53_PAD_SD2_CLK__GPIO1_10 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1068 | #define MX53_PAD_SD1_CLK__GPT_CLKIN IOMUX_PAD(0x67C, 0x2F4, 3, __NA_, 0, NO_PAD_CTRL) |
| 2243 | #define MX53_PAD_SD2_CLK__KPP_COL_5 (_MX53_PAD_SD2_CLK__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1069 | #define MX53_PAD_SD1_CLK__CSPI_SCLK IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, NO_PAD_CTRL) |
| 2244 | #define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS (_MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1070 | #define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 IOMUX_PAD(0x67C, 0x2F4, 7, __NA_, 0, NO_PAD_CTRL) |
| 2245 | #define MX53_PAD_SD2_CLK__CSPI_SCLK (_MX53_PAD_SD2_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1071 | #define MX53_PAD_SD1_DATA3__ESDHC1_DAT3 IOMUX_PAD(0x680, 0x2F8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2246 | #define MX53_PAD_SD2_CLK__SCC_RANDOM_V (_MX53_PAD_SD2_CLK__SCC_RANDOM_V | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1072 | #define MX53_PAD_SD1_DATA3__GPIO1_21 IOMUX_PAD(0x680, 0x2F8, 1, __NA_, 0, NO_PAD_CTRL) |
| 2247 | #define MX53_PAD_SD2_CMD__ESDHC2_CMD (_MX53_PAD_SD2_CMD__ESDHC2_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 1073 | #define MX53_PAD_SD1_DATA3__GPT_CMPOUT3 IOMUX_PAD(0x680, 0x2F8, 2, __NA_, 0, NO_PAD_CTRL) |
| 2248 | #define MX53_PAD_SD2_CMD__GPIO1_11 (_MX53_PAD_SD2_CMD__GPIO1_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1074 | #define MX53_PAD_SD1_DATA3__PWM1_PWMO IOMUX_PAD(0x680, 0x2F8, 3, __NA_, 0, NO_PAD_CTRL) |
| 2249 | #define MX53_PAD_SD2_CMD__KPP_ROW_5 (_MX53_PAD_SD2_CMD__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1075 | #define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B IOMUX_PAD(0x680, 0x2F8, 4, __NA_, 0, NO_PAD_CTRL) |
| 2250 | #define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC (_MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1076 | #define MX53_PAD_SD1_DATA3__CSPI_SS2 IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, NO_PAD_CTRL) |
| 2251 | #define MX53_PAD_SD2_CMD__CSPI_MOSI (_MX53_PAD_SD2_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1077 | #define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB IOMUX_PAD(0x680, 0x2F8, 6, __NA_, 0, NO_PAD_CTRL) |
| 2252 | #define MX53_PAD_SD2_CMD__SCC_RANDOM (_MX53_PAD_SD2_CMD__SCC_RANDOM | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1078 | #define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 IOMUX_PAD(0x680, 0x2F8, 7, __NA_, 0, NO_PAD_CTRL) |
| 2253 | #define MX53_PAD_SD2_DATA3__ESDHC2_DAT3 (_MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 1079 | #define MX53_PAD_SD2_CLK__ESDHC2_CLK IOMUX_PAD(0x688, 0x2FC, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2254 | #define MX53_PAD_SD2_DATA3__GPIO1_12 (_MX53_PAD_SD2_DATA3__GPIO1_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1080 | #define MX53_PAD_SD2_CLK__GPIO1_10 IOMUX_PAD(0x688, 0x2FC, 1, __NA_, 0, NO_PAD_CTRL) |
| 2255 | #define MX53_PAD_SD2_DATA3__KPP_COL_6 (_MX53_PAD_SD2_DATA3__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1081 | #define MX53_PAD_SD2_CLK__KPP_COL_5 IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, NO_PAD_CTRL) |
| 2256 | #define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC (_MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1082 | #define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, NO_PAD_CTRL) |
| 2257 | #define MX53_PAD_SD2_DATA3__CSPI_SS2 (_MX53_PAD_SD2_DATA3__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1083 | #define MX53_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, NO_PAD_CTRL) |
| 2258 | #define MX53_PAD_SD2_DATA3__SJC_DONE (_MX53_PAD_SD2_DATA3__SJC_DONE | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1084 | #define MX53_PAD_SD2_CLK__SCC_RANDOM_V IOMUX_PAD(0x688, 0x2FC, 7, __NA_, 0, NO_PAD_CTRL) |
| 2259 | #define MX53_PAD_SD2_DATA2__ESDHC2_DAT2 (_MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 1085 | #define MX53_PAD_SD2_CMD__ESDHC2_CMD IOMUX_PAD(0x68C, 0x300, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2260 | #define MX53_PAD_SD2_DATA2__GPIO1_13 (_MX53_PAD_SD2_DATA2__GPIO1_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1086 | #define MX53_PAD_SD2_CMD__GPIO1_11 IOMUX_PAD(0x68C, 0x300, 1, __NA_, 0, NO_PAD_CTRL) |
| 2261 | #define MX53_PAD_SD2_DATA2__KPP_ROW_6 (_MX53_PAD_SD2_DATA2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1087 | #define MX53_PAD_SD2_CMD__KPP_ROW_5 IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, NO_PAD_CTRL) |
| 2262 | #define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD (_MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1088 | #define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, NO_PAD_CTRL) |
| 2263 | #define MX53_PAD_SD2_DATA2__CSPI_SS1 (_MX53_PAD_SD2_DATA2__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1089 | #define MX53_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, NO_PAD_CTRL) |
| 2264 | #define MX53_PAD_SD2_DATA2__SJC_FAIL (_MX53_PAD_SD2_DATA2__SJC_FAIL | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1090 | #define MX53_PAD_SD2_CMD__SCC_RANDOM IOMUX_PAD(0x68C, 0x300, 7, __NA_, 0, NO_PAD_CTRL) |
| 2265 | #define MX53_PAD_SD2_DATA1__ESDHC2_DAT1 (_MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 1091 | #define MX53_PAD_SD2_DATA3__ESDHC2_DAT3 IOMUX_PAD(0x690, 0x304, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2266 | #define MX53_PAD_SD2_DATA1__GPIO1_14 (_MX53_PAD_SD2_DATA1__GPIO1_14 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1092 | #define MX53_PAD_SD2_DATA3__GPIO1_12 IOMUX_PAD(0x690, 0x304, 1, __NA_, 0, NO_PAD_CTRL) |
| 2267 | #define MX53_PAD_SD2_DATA1__KPP_COL_7 (_MX53_PAD_SD2_DATA1__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1093 | #define MX53_PAD_SD2_DATA3__KPP_COL_6 IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, NO_PAD_CTRL) |
| 2268 | #define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS (_MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1094 | #define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, NO_PAD_CTRL) |
| 2269 | #define MX53_PAD_SD2_DATA1__CSPI_SS0 (_MX53_PAD_SD2_DATA1__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1095 | #define MX53_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, NO_PAD_CTRL) |
| 2270 | #define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO (_MX53_PAD_SD2_DATA1__RTIC_SEC_VIO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1096 | #define MX53_PAD_SD2_DATA3__SJC_DONE IOMUX_PAD(0x690, 0x304, 7, __NA_, 0, NO_PAD_CTRL) |
| 2271 | #define MX53_PAD_SD2_DATA0__ESDHC2_DAT0 (_MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL)) | 1097 | #define MX53_PAD_SD2_DATA2__ESDHC2_DAT2 IOMUX_PAD(0x694, 0x308, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2272 | #define MX53_PAD_SD2_DATA0__GPIO1_15 (_MX53_PAD_SD2_DATA0__GPIO1_15 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1098 | #define MX53_PAD_SD2_DATA2__GPIO1_13 IOMUX_PAD(0x694, 0x308, 1, __NA_, 0, NO_PAD_CTRL) |
| 2273 | #define MX53_PAD_SD2_DATA0__KPP_ROW_7 (_MX53_PAD_SD2_DATA0__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1099 | #define MX53_PAD_SD2_DATA2__KPP_ROW_6 IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, NO_PAD_CTRL) |
| 2274 | #define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD (_MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1100 | #define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, NO_PAD_CTRL) |
| 2275 | #define MX53_PAD_SD2_DATA0__CSPI_MISO (_MX53_PAD_SD2_DATA0__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1101 | #define MX53_PAD_SD2_DATA2__CSPI_SS1 IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, NO_PAD_CTRL) |
| 2276 | #define MX53_PAD_SD2_DATA0__RTIC_DONE_INT (_MX53_PAD_SD2_DATA0__RTIC_DONE_INT | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1102 | #define MX53_PAD_SD2_DATA2__SJC_FAIL IOMUX_PAD(0x694, 0x308, 7, __NA_, 0, NO_PAD_CTRL) |
| 2277 | #define MX53_PAD_GPIO_0__CCM_CLKO (_MX53_PAD_GPIO_0__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1103 | #define MX53_PAD_SD2_DATA1__ESDHC2_DAT1 IOMUX_PAD(0x698, 0x30C, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2278 | #define MX53_PAD_GPIO_0__GPIO1_0 (_MX53_PAD_GPIO_0__GPIO1_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1104 | #define MX53_PAD_SD2_DATA1__GPIO1_14 IOMUX_PAD(0x698, 0x30C, 1, __NA_, 0, NO_PAD_CTRL) |
| 2279 | #define MX53_PAD_GPIO_0__KPP_COL_5 (_MX53_PAD_GPIO_0__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1105 | #define MX53_PAD_SD2_DATA1__KPP_COL_7 IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, NO_PAD_CTRL) |
| 2280 | #define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK (_MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1106 | #define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, NO_PAD_CTRL) |
| 2281 | #define MX53_PAD_GPIO_0__EPIT1_EPITO (_MX53_PAD_GPIO_0__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1107 | #define MX53_PAD_SD2_DATA1__CSPI_SS0 IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, NO_PAD_CTRL) |
| 2282 | #define MX53_PAD_GPIO_0__SRTC_ALARM_DEB (_MX53_PAD_GPIO_0__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1108 | #define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO IOMUX_PAD(0x698, 0x30C, 7, __NA_, 0, NO_PAD_CTRL) |
| 2283 | #define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR (_MX53_PAD_GPIO_0__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1109 | #define MX53_PAD_SD2_DATA0__ESDHC2_DAT0 IOMUX_PAD(0x69C, 0x310, 0, __NA_, 0, MX53_SDHC_PAD_CTRL) |
| 2284 | #define MX53_PAD_GPIO_0__CSU_TD (_MX53_PAD_GPIO_0__CSU_TD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1110 | #define MX53_PAD_SD2_DATA0__GPIO1_15 IOMUX_PAD(0x69C, 0x310, 1, __NA_, 0, NO_PAD_CTRL) |
| 2285 | #define MX53_PAD_GPIO_1__ESAI1_SCKR (_MX53_PAD_GPIO_1__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1111 | #define MX53_PAD_SD2_DATA0__KPP_ROW_7 IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, NO_PAD_CTRL) |
| 2286 | #define MX53_PAD_GPIO_1__GPIO1_1 (_MX53_PAD_GPIO_1__GPIO1_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1112 | #define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, NO_PAD_CTRL) |
| 2287 | #define MX53_PAD_GPIO_1__KPP_ROW_5 (_MX53_PAD_GPIO_1__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1113 | #define MX53_PAD_SD2_DATA0__CSPI_MISO IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, NO_PAD_CTRL) |
| 2288 | #define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK (_MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1114 | #define MX53_PAD_SD2_DATA0__RTIC_DONE_INT IOMUX_PAD(0x69C, 0x310, 7, __NA_, 0, NO_PAD_CTRL) |
| 2289 | #define MX53_PAD_GPIO_1__PWM2_PWMO (_MX53_PAD_GPIO_1__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1115 | #define MX53_PAD_GPIO_0__CCM_CLKO IOMUX_PAD(0x6A4, 0x314, 0, __NA_, 0, NO_PAD_CTRL) |
| 2290 | #define MX53_PAD_GPIO_1__WDOG2_WDOG_B (_MX53_PAD_GPIO_1__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1116 | #define MX53_PAD_GPIO_0__GPIO1_0 IOMUX_PAD(0x6A4, 0x314, 1, __NA_, 0, NO_PAD_CTRL) |
| 2291 | #define MX53_PAD_GPIO_1__ESDHC1_CD (_MX53_PAD_GPIO_1__ESDHC1_CD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1117 | #define MX53_PAD_GPIO_0__KPP_COL_5 IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, NO_PAD_CTRL) |
| 2292 | #define MX53_PAD_GPIO_1__SRC_TESTER_ACK (_MX53_PAD_GPIO_1__SRC_TESTER_ACK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1118 | #define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK IOMUX_PAD(0x6A4, 0x314, 3, __NA_, 0, NO_PAD_CTRL) |
| 2293 | #define MX53_PAD_GPIO_9__ESAI1_FSR (_MX53_PAD_GPIO_9__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1119 | #define MX53_PAD_GPIO_0__EPIT1_EPITO IOMUX_PAD(0x6A4, 0x314, 4, __NA_, 0, NO_PAD_CTRL) |
| 2294 | #define MX53_PAD_GPIO_9__GPIO1_9 (_MX53_PAD_GPIO_9__GPIO1_9 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1120 | #define MX53_PAD_GPIO_0__SRTC_ALARM_DEB IOMUX_PAD(0x6A4, 0x314, 5, __NA_, 0, NO_PAD_CTRL) |
| 2295 | #define MX53_PAD_GPIO_9__KPP_COL_6 (_MX53_PAD_GPIO_9__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1121 | #define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR IOMUX_PAD(0x6A4, 0x314, 6, __NA_, 0, NO_PAD_CTRL) |
| 2296 | #define MX53_PAD_GPIO_9__CCM_REF_EN_B (_MX53_PAD_GPIO_9__CCM_REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1122 | #define MX53_PAD_GPIO_0__CSU_TD IOMUX_PAD(0x6A4, 0x314, 7, __NA_, 0, NO_PAD_CTRL) |
| 2297 | #define MX53_PAD_GPIO_9__PWM1_PWMO (_MX53_PAD_GPIO_9__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1123 | #define MX53_PAD_GPIO_1__ESAI1_SCKR IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, NO_PAD_CTRL) |
| 2298 | #define MX53_PAD_GPIO_9__WDOG1_WDOG_B (_MX53_PAD_GPIO_9__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1124 | #define MX53_PAD_GPIO_1__GPIO1_1 IOMUX_PAD(0x6A8, 0x318, 1, __NA_, 0, NO_PAD_CTRL) |
| 2299 | #define MX53_PAD_GPIO_9__ESDHC1_WP (_MX53_PAD_GPIO_9__ESDHC1_WP | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1125 | #define MX53_PAD_GPIO_1__KPP_ROW_5 IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, NO_PAD_CTRL) |
| 2300 | #define MX53_PAD_GPIO_9__SCC_FAIL_STATE (_MX53_PAD_GPIO_9__SCC_FAIL_STATE | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1126 | #define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK IOMUX_PAD(0x6A8, 0x318, 3, __NA_, 0, NO_PAD_CTRL) |
| 2301 | #define MX53_PAD_GPIO_3__ESAI1_HCKR (_MX53_PAD_GPIO_3__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1127 | #define MX53_PAD_GPIO_1__PWM2_PWMO IOMUX_PAD(0x6A8, 0x318, 4, __NA_, 0, NO_PAD_CTRL) |
| 2302 | #define MX53_PAD_GPIO_3__GPIO1_3 (_MX53_PAD_GPIO_3__GPIO1_3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1128 | #define MX53_PAD_GPIO_1__WDOG2_WDOG_B IOMUX_PAD(0x6A8, 0x318, 5, __NA_, 0, NO_PAD_CTRL) |
| 2303 | #define MX53_PAD_GPIO_3__I2C3_SCL (_MX53_PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C)) | 1129 | #define MX53_PAD_GPIO_1__ESDHC1_CD IOMUX_PAD(0x6A8, 0x318, 6, __NA_, 0, NO_PAD_CTRL) |
| 2304 | #define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN (_MX53_PAD_GPIO_3__DPLLIP1_TOG_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1130 | #define MX53_PAD_GPIO_1__SRC_TESTER_ACK IOMUX_PAD(0x6A8, 0x318, 7, __NA_, 0, NO_PAD_CTRL) |
| 2305 | #define MX53_PAD_GPIO_3__CCM_CLKO2 (_MX53_PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1131 | #define MX53_PAD_GPIO_9__ESAI1_FSR IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, NO_PAD_CTRL) |
| 2306 | #define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 (_MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1132 | #define MX53_PAD_GPIO_9__GPIO1_9 IOMUX_PAD(0x6AC, 0x31C, 1, __NA_, 0, NO_PAD_CTRL) |
| 2307 | #define MX53_PAD_GPIO_3__USBOH3_USBH1_OC (_MX53_PAD_GPIO_3__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1133 | #define MX53_PAD_GPIO_9__KPP_COL_6 IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, NO_PAD_CTRL) |
| 2308 | #define MX53_PAD_GPIO_3__MLB_MLBCLK (_MX53_PAD_GPIO_3__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1134 | #define MX53_PAD_GPIO_9__CCM_REF_EN_B IOMUX_PAD(0x6AC, 0x31C, 3, __NA_, 0, NO_PAD_CTRL) |
| 2309 | #define MX53_PAD_GPIO_6__ESAI1_SCKT (_MX53_PAD_GPIO_6__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1135 | #define MX53_PAD_GPIO_9__PWM1_PWMO IOMUX_PAD(0x6AC, 0x31C, 4, __NA_, 0, NO_PAD_CTRL) |
| 2310 | #define MX53_PAD_GPIO_6__GPIO1_6 (_MX53_PAD_GPIO_6__GPIO1_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1136 | #define MX53_PAD_GPIO_9__WDOG1_WDOG_B IOMUX_PAD(0x6AC, 0x31C, 5, __NA_, 0, NO_PAD_CTRL) |
| 2311 | #define MX53_PAD_GPIO_6__I2C3_SDA (_MX53_PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C)) | 1137 | #define MX53_PAD_GPIO_9__ESDHC1_WP IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, NO_PAD_CTRL) |
| 2312 | #define MX53_PAD_GPIO_6__CCM_CCM_OUT_0 (_MX53_PAD_GPIO_6__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1138 | #define MX53_PAD_GPIO_9__SCC_FAIL_STATE IOMUX_PAD(0x6AC, 0x31C, 7, __NA_, 0, NO_PAD_CTRL) |
| 2313 | #define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB (_MX53_PAD_GPIO_6__CSU_CSU_INT_DEB | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1139 | #define MX53_PAD_GPIO_3__ESAI1_HCKR IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, NO_PAD_CTRL) |
| 2314 | #define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 (_MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1140 | #define MX53_PAD_GPIO_3__GPIO1_3 IOMUX_PAD(0x6B0, 0x320, 1, __NA_, 0, NO_PAD_CTRL) |
| 2315 | #define MX53_PAD_GPIO_6__ESDHC2_LCTL (_MX53_PAD_GPIO_6__ESDHC2_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1141 | #define MX53_PAD_GPIO_3__I2C3_SCL IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, NO_PAD_CTRL) |
| 2316 | #define MX53_PAD_GPIO_6__MLB_MLBSIG (_MX53_PAD_GPIO_6__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1142 | #define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN IOMUX_PAD(0x6B0, 0x320, 3, __NA_, 0, NO_PAD_CTRL) |
| 2317 | #define MX53_PAD_GPIO_2__ESAI1_FST (_MX53_PAD_GPIO_2__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1143 | #define MX53_PAD_GPIO_3__CCM_CLKO2 IOMUX_PAD(0x6B0, 0x320, 4, __NA_, 0, NO_PAD_CTRL) |
| 2318 | #define MX53_PAD_GPIO_2__GPIO1_2 (_MX53_PAD_GPIO_2__GPIO1_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1144 | #define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 IOMUX_PAD(0x6B0, 0x320, 5, __NA_, 0, NO_PAD_CTRL) |
| 2319 | #define MX53_PAD_GPIO_2__KPP_ROW_6 (_MX53_PAD_GPIO_2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1145 | #define MX53_PAD_GPIO_3__USBOH3_USBH1_OC IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, NO_PAD_CTRL) |
| 2320 | #define MX53_PAD_GPIO_2__CCM_CCM_OUT_1 (_MX53_PAD_GPIO_2__CCM_CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1146 | #define MX53_PAD_GPIO_3__MLB_MLBCLK IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, NO_PAD_CTRL) |
| 2321 | #define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 (_MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1147 | #define MX53_PAD_GPIO_6__ESAI1_SCKT IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, NO_PAD_CTRL) |
| 2322 | #define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 (_MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1148 | #define MX53_PAD_GPIO_6__GPIO1_6 IOMUX_PAD(0x6B4, 0x324, 1, __NA_, 0, NO_PAD_CTRL) |
| 2323 | #define MX53_PAD_GPIO_2__ESDHC2_WP (_MX53_PAD_GPIO_2__ESDHC2_WP | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1149 | #define MX53_PAD_GPIO_6__I2C3_SDA IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, NO_PAD_CTRL) |
| 2324 | #define MX53_PAD_GPIO_2__MLB_MLBDAT (_MX53_PAD_GPIO_2__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1150 | #define MX53_PAD_GPIO_6__CCM_CCM_OUT_0 IOMUX_PAD(0x6B4, 0x324, 3, __NA_, 0, NO_PAD_CTRL) |
| 2325 | #define MX53_PAD_GPIO_4__ESAI1_HCKT (_MX53_PAD_GPIO_4__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1151 | #define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB IOMUX_PAD(0x6B4, 0x324, 4, __NA_, 0, NO_PAD_CTRL) |
| 2326 | #define MX53_PAD_GPIO_4__GPIO1_4 (_MX53_PAD_GPIO_4__GPIO1_4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1152 | #define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 IOMUX_PAD(0x6B4, 0x324, 5, __NA_, 0, NO_PAD_CTRL) |
| 2327 | #define MX53_PAD_GPIO_4__KPP_COL_7 (_MX53_PAD_GPIO_4__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1153 | #define MX53_PAD_GPIO_6__ESDHC2_LCTL IOMUX_PAD(0x6B4, 0x324, 6, __NA_, 0, NO_PAD_CTRL) |
| 2328 | #define MX53_PAD_GPIO_4__CCM_CCM_OUT_2 (_MX53_PAD_GPIO_4__CCM_CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1154 | #define MX53_PAD_GPIO_6__MLB_MLBSIG IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, NO_PAD_CTRL) |
| 2329 | #define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 (_MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1155 | #define MX53_PAD_GPIO_2__ESAI1_FST IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, NO_PAD_CTRL) |
| 2330 | #define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 (_MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1156 | #define MX53_PAD_GPIO_2__GPIO1_2 IOMUX_PAD(0x6B8, 0x328, 1, __NA_, 0, NO_PAD_CTRL) |
| 2331 | #define MX53_PAD_GPIO_4__ESDHC2_CD (_MX53_PAD_GPIO_4__ESDHC2_CD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1157 | #define MX53_PAD_GPIO_2__KPP_ROW_6 IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, NO_PAD_CTRL) |
| 2332 | #define MX53_PAD_GPIO_4__SCC_SEC_STATE (_MX53_PAD_GPIO_4__SCC_SEC_STATE | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1158 | #define MX53_PAD_GPIO_2__CCM_CCM_OUT_1 IOMUX_PAD(0x6B8, 0x328, 3, __NA_, 0, NO_PAD_CTRL) |
| 2333 | #define MX53_PAD_GPIO_5__ESAI1_TX2_RX3 (_MX53_PAD_GPIO_5__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1159 | #define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 IOMUX_PAD(0x6B8, 0x328, 4, __NA_, 0, NO_PAD_CTRL) |
| 2334 | #define MX53_PAD_GPIO_5__GPIO1_5 (_MX53_PAD_GPIO_5__GPIO1_5 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1160 | #define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 IOMUX_PAD(0x6B8, 0x328, 5, __NA_, 0, NO_PAD_CTRL) |
| 2335 | #define MX53_PAD_GPIO_5__KPP_ROW_7 (_MX53_PAD_GPIO_5__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1161 | #define MX53_PAD_GPIO_2__ESDHC2_WP IOMUX_PAD(0x6B8, 0x328, 6, __NA_, 0, NO_PAD_CTRL) |
| 2336 | #define MX53_PAD_GPIO_5__CCM_CLKO (_MX53_PAD_GPIO_5__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1162 | #define MX53_PAD_GPIO_2__MLB_MLBDAT IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, NO_PAD_CTRL) |
| 2337 | #define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 (_MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1163 | #define MX53_PAD_GPIO_4__ESAI1_HCKT IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, NO_PAD_CTRL) |
| 2338 | #define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 (_MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1164 | #define MX53_PAD_GPIO_4__GPIO1_4 IOMUX_PAD(0x6BC, 0x32C, 1, __NA_, 0, NO_PAD_CTRL) |
| 2339 | #define MX53_PAD_GPIO_5__I2C3_SCL (_MX53_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C)) | 1165 | #define MX53_PAD_GPIO_4__KPP_COL_7 IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, NO_PAD_CTRL) |
| 2340 | #define MX53_PAD_GPIO_5__CCM_PLL1_BYP (_MX53_PAD_GPIO_5__CCM_PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1166 | #define MX53_PAD_GPIO_4__CCM_CCM_OUT_2 IOMUX_PAD(0x6BC, 0x32C, 3, __NA_, 0, NO_PAD_CTRL) |
| 2341 | #define MX53_PAD_GPIO_7__ESAI1_TX4_RX1 (_MX53_PAD_GPIO_7__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1167 | #define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 IOMUX_PAD(0x6BC, 0x32C, 4, __NA_, 0, NO_PAD_CTRL) |
| 2342 | #define MX53_PAD_GPIO_7__GPIO1_7 (_MX53_PAD_GPIO_7__GPIO1_7 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1168 | #define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 IOMUX_PAD(0x6BC, 0x32C, 5, __NA_, 0, NO_PAD_CTRL) |
| 2343 | #define MX53_PAD_GPIO_7__EPIT1_EPITO (_MX53_PAD_GPIO_7__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1169 | #define MX53_PAD_GPIO_4__ESDHC2_CD IOMUX_PAD(0x6BC, 0x32C, 6, __NA_, 0, NO_PAD_CTRL) |
| 2344 | #define MX53_PAD_GPIO_7__CAN1_TXCAN (_MX53_PAD_GPIO_7__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1170 | #define MX53_PAD_GPIO_4__SCC_SEC_STATE IOMUX_PAD(0x6BC, 0x32C, 7, __NA_, 0, NO_PAD_CTRL) |
| 2345 | #define MX53_PAD_GPIO_7__UART2_TXD_MUX (_MX53_PAD_GPIO_7__UART2_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 1171 | #define MX53_PAD_GPIO_5__ESAI1_TX2_RX3 IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, NO_PAD_CTRL) |
| 2346 | #define MX53_PAD_GPIO_7__FIRI_RXD (_MX53_PAD_GPIO_7__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1172 | #define MX53_PAD_GPIO_5__GPIO1_5 IOMUX_PAD(0x6C0, 0x330, 1, __NA_, 0, NO_PAD_CTRL) |
| 2347 | #define MX53_PAD_GPIO_7__SPDIF_PLOCK (_MX53_PAD_GPIO_7__SPDIF_PLOCK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1173 | #define MX53_PAD_GPIO_5__KPP_ROW_7 IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, NO_PAD_CTRL) |
| 2348 | #define MX53_PAD_GPIO_7__CCM_PLL2_BYP (_MX53_PAD_GPIO_7__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1174 | #define MX53_PAD_GPIO_5__CCM_CLKO IOMUX_PAD(0x6C0, 0x330, 3, __NA_, 0, NO_PAD_CTRL) |
| 2349 | #define MX53_PAD_GPIO_8__ESAI1_TX5_RX0 (_MX53_PAD_GPIO_8__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1175 | #define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 IOMUX_PAD(0x6C0, 0x330, 4, __NA_, 0, NO_PAD_CTRL) |
| 2350 | #define MX53_PAD_GPIO_8__GPIO1_8 (_MX53_PAD_GPIO_8__GPIO1_8 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1176 | #define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 IOMUX_PAD(0x6C0, 0x330, 5, __NA_, 0, NO_PAD_CTRL) |
| 2351 | #define MX53_PAD_GPIO_8__EPIT2_EPITO (_MX53_PAD_GPIO_8__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1177 | #define MX53_PAD_GPIO_5__I2C3_SCL IOMUX_PAD(0x6C0, 0x330, 6 | IOMUX_CONFIG_SION, 0x824, 2, NO_PAD_CTRL) |
| 2352 | #define MX53_PAD_GPIO_8__CAN1_RXCAN (_MX53_PAD_GPIO_8__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1178 | #define MX53_PAD_GPIO_5__CCM_PLL1_BYP IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, NO_PAD_CTRL) |
| 2353 | #define MX53_PAD_GPIO_8__UART2_RXD_MUX (_MX53_PAD_GPIO_8__UART2_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL)) | 1179 | #define MX53_PAD_GPIO_7__ESAI1_TX4_RX1 IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, NO_PAD_CTRL) |
| 2354 | #define MX53_PAD_GPIO_8__FIRI_TXD (_MX53_PAD_GPIO_8__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1180 | #define MX53_PAD_GPIO_7__GPIO1_7 IOMUX_PAD(0x6C4, 0x334, 1, __NA_, 0, NO_PAD_CTRL) |
| 2355 | #define MX53_PAD_GPIO_8__SPDIF_SRCLK (_MX53_PAD_GPIO_8__SPDIF_SRCLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1181 | #define MX53_PAD_GPIO_7__EPIT1_EPITO IOMUX_PAD(0x6C4, 0x334, 2, __NA_, 0, NO_PAD_CTRL) |
| 2356 | #define MX53_PAD_GPIO_8__CCM_PLL3_BYP (_MX53_PAD_GPIO_8__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1182 | #define MX53_PAD_GPIO_7__CAN1_TXCAN IOMUX_PAD(0x6C4, 0x334, 3, __NA_, 0, NO_PAD_CTRL) |
| 2357 | #define MX53_PAD_GPIO_16__ESAI1_TX3_RX2 (_MX53_PAD_GPIO_16__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1183 | #define MX53_PAD_GPIO_7__UART2_TXD_MUX IOMUX_PAD(0x6C4, 0x334, 4, __NA_, 0, MX53_UART_PAD_CTRL) |
| 2358 | #define MX53_PAD_GPIO_16__GPIO7_11 (_MX53_PAD_GPIO_16__GPIO7_11 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1184 | #define MX53_PAD_GPIO_7__FIRI_RXD IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, NO_PAD_CTRL) |
| 2359 | #define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT (_MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1185 | #define MX53_PAD_GPIO_7__SPDIF_PLOCK IOMUX_PAD(0x6C4, 0x334, 6, __NA_, 0, NO_PAD_CTRL) |
| 2360 | #define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 (_MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1186 | #define MX53_PAD_GPIO_7__CCM_PLL2_BYP IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, NO_PAD_CTRL) |
| 2361 | #define MX53_PAD_GPIO_16__SPDIF_IN1 (_MX53_PAD_GPIO_16__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1187 | #define MX53_PAD_GPIO_8__ESAI1_TX5_RX0 IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, NO_PAD_CTRL) |
| 2362 | #define MX53_PAD_GPIO_16__I2C3_SDA (_MX53_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C)) | 1188 | #define MX53_PAD_GPIO_8__GPIO1_8 IOMUX_PAD(0x6C8, 0x338, 1, __NA_, 0, NO_PAD_CTRL) |
| 2363 | #define MX53_PAD_GPIO_16__SJC_DE_B (_MX53_PAD_GPIO_16__SJC_DE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1189 | #define MX53_PAD_GPIO_8__EPIT2_EPITO IOMUX_PAD(0x6C8, 0x338, 2, __NA_, 0, NO_PAD_CTRL) |
| 2364 | #define MX53_PAD_GPIO_17__ESAI1_TX0 (_MX53_PAD_GPIO_17__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1190 | #define MX53_PAD_GPIO_8__CAN1_RXCAN IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 3, NO_PAD_CTRL) |
| 2365 | #define MX53_PAD_GPIO_17__GPIO7_12 (_MX53_PAD_GPIO_17__GPIO7_12 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1191 | #define MX53_PAD_GPIO_8__UART2_RXD_MUX IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, MX53_UART_PAD_CTRL) |
| 2366 | #define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 (_MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1192 | #define MX53_PAD_GPIO_8__FIRI_TXD IOMUX_PAD(0x6C8, 0x338, 5, __NA_, 0, NO_PAD_CTRL) |
| 2367 | #define MX53_PAD_GPIO_17__GPC_PMIC_RDY (_MX53_PAD_GPIO_17__GPC_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1193 | #define MX53_PAD_GPIO_8__SPDIF_SRCLK IOMUX_PAD(0x6C8, 0x338, 6, __NA_, 0, NO_PAD_CTRL) |
| 2368 | #define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG (_MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1194 | #define MX53_PAD_GPIO_8__CCM_PLL3_BYP IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, NO_PAD_CTRL) |
| 2369 | #define MX53_PAD_GPIO_17__SPDIF_OUT1 (_MX53_PAD_GPIO_17__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1195 | #define MX53_PAD_GPIO_16__ESAI1_TX3_RX2 IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, NO_PAD_CTRL) |
| 2370 | #define MX53_PAD_GPIO_17__IPU_SNOOP2 (_MX53_PAD_GPIO_17__IPU_SNOOP2 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1196 | #define MX53_PAD_GPIO_16__GPIO7_11 IOMUX_PAD(0x6CC, 0x33C, 1, __NA_, 0, NO_PAD_CTRL) |
| 2371 | #define MX53_PAD_GPIO_17__SJC_JTAG_ACT (_MX53_PAD_GPIO_17__SJC_JTAG_ACT | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1197 | #define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT IOMUX_PAD(0x6CC, 0x33C, 2, __NA_, 0, NO_PAD_CTRL) |
| 2372 | #define MX53_PAD_GPIO_18__ESAI1_TX1 (_MX53_PAD_GPIO_18__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1198 | #define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 IOMUX_PAD(0x6CC, 0x33C, 4, __NA_, 0, NO_PAD_CTRL) |
| 2373 | #define MX53_PAD_GPIO_18__GPIO7_13 (_MX53_PAD_GPIO_18__GPIO7_13 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1199 | #define MX53_PAD_GPIO_16__SPDIF_IN1 IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, NO_PAD_CTRL) |
| 2374 | #define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 (_MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1200 | #define MX53_PAD_GPIO_16__I2C3_SDA IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, NO_PAD_CTRL) |
| 2375 | #define MX53_PAD_GPIO_18__OWIRE_LINE (_MX53_PAD_GPIO_18__OWIRE_LINE | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1201 | #define MX53_PAD_GPIO_16__SJC_DE_B IOMUX_PAD(0x6CC, 0x33C, 7, __NA_, 0, NO_PAD_CTRL) |
| 2376 | #define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG (_MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1202 | #define MX53_PAD_GPIO_17__ESAI1_TX0 IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, NO_PAD_CTRL) |
| 2377 | #define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK (_MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1203 | #define MX53_PAD_GPIO_17__GPIO7_12 IOMUX_PAD(0x6D0, 0x340, 1, __NA_, 0, NO_PAD_CTRL) |
| 2378 | #define MX53_PAD_GPIO_18__ESDHC1_LCTL (_MX53_PAD_GPIO_18__ESDHC1_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1204 | #define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, NO_PAD_CTRL) |
| 2379 | #define MX53_PAD_GPIO_18__SRC_SYSTEM_RST (_MX53_PAD_GPIO_18__SRC_SYSTEM_RST | MUX_PAD_CTRL(NO_PAD_CTRL)) | 1205 | #define MX53_PAD_GPIO_17__GPC_PMIC_RDY IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, NO_PAD_CTRL) |
| 1206 | #define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG IOMUX_PAD(0x6D0, 0x340, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 1207 | #define MX53_PAD_GPIO_17__SPDIF_OUT1 IOMUX_PAD(0x6D0, 0x340, 5, __NA_, 0, NO_PAD_CTRL) | ||
| 1208 | #define MX53_PAD_GPIO_17__IPU_SNOOP2 IOMUX_PAD(0x6D0, 0x340, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1209 | #define MX53_PAD_GPIO_17__SJC_JTAG_ACT IOMUX_PAD(0x6D0, 0x340, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 1210 | #define MX53_PAD_GPIO_18__ESAI1_TX1 IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, NO_PAD_CTRL) | ||
| 1211 | #define MX53_PAD_GPIO_18__GPIO7_13 IOMUX_PAD(0x6D4, 0x344, 1, __NA_, 0, NO_PAD_CTRL) | ||
| 1212 | #define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, NO_PAD_CTRL) | ||
| 1213 | #define MX53_PAD_GPIO_18__OWIRE_LINE IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, NO_PAD_CTRL) | ||
| 1214 | #define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG IOMUX_PAD(0x6D4, 0x344, 4, __NA_, 0, NO_PAD_CTRL) | ||
| 1215 | #define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, NO_PAD_CTRL) | ||
| 1216 | #define MX53_PAD_GPIO_18__ESDHC1_LCTL IOMUX_PAD(0x6D4, 0x344, 6, __NA_, 0, NO_PAD_CTRL) | ||
| 1217 | #define MX53_PAD_GPIO_18__SRC_SYSTEM_RST IOMUX_PAD(0x6D4, 0x344, 7, __NA_, 0, NO_PAD_CTRL) | ||
| 2380 | 1218 | ||
| 2381 | #endif /* __MACH_IOMUX_MX53_H__ */ | 1219 | #endif /* __MACH_IOMUX_MX53_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h index ebbce33097a7..35e0df224caa 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-v3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h | |||
| @@ -80,6 +80,7 @@ typedef u64 iomux_v3_cfg_t; | |||
| 80 | ((iomux_v3_cfg_t)(_sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT) | \ | 80 | ((iomux_v3_cfg_t)(_sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT) | \ |
| 81 | ((iomux_v3_cfg_t)(_sel_input) << MUX_SEL_INPUT_SHIFT)) | 81 | ((iomux_v3_cfg_t)(_sel_input) << MUX_SEL_INPUT_SHIFT)) |
| 82 | 82 | ||
| 83 | #define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(pad)) | ||
| 83 | /* | 84 | /* |
| 84 | * Use to set PAD control | 85 | * Use to set PAD control |
| 85 | */ | 86 | */ |
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index 11be5cdbdd1a..35e6c7f4ffd1 100644 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h | |||
| @@ -21,22 +21,8 @@ | |||
| 21 | #define MX53_PHYS_OFFSET UL(0x70000000) | 21 | #define MX53_PHYS_OFFSET UL(0x70000000) |
| 22 | 22 | ||
| 23 | #if !defined(CONFIG_RUNTIME_PHYS_OFFSET) | 23 | #if !defined(CONFIG_RUNTIME_PHYS_OFFSET) |
| 24 | # if defined CONFIG_ARCH_MX1 | 24 | # if defined CONFIG_ARCH_MX3 |
| 25 | # define PLAT_PHYS_OFFSET MX1_PHYS_OFFSET | ||
| 26 | # elif defined CONFIG_MACH_MX21 | ||
| 27 | # define PLAT_PHYS_OFFSET MX21_PHYS_OFFSET | ||
| 28 | # elif defined CONFIG_ARCH_MX25 | ||
| 29 | # define PLAT_PHYS_OFFSET MX25_PHYS_OFFSET | ||
| 30 | # elif defined CONFIG_MACH_MX27 | ||
| 31 | # define PLAT_PHYS_OFFSET MX27_PHYS_OFFSET | ||
| 32 | # elif defined CONFIG_ARCH_MX3 | ||
| 33 | # define PLAT_PHYS_OFFSET MX3x_PHYS_OFFSET | 25 | # define PLAT_PHYS_OFFSET MX3x_PHYS_OFFSET |
| 34 | # elif defined CONFIG_ARCH_MX50 | ||
| 35 | # define PLAT_PHYS_OFFSET MX50_PHYS_OFFSET | ||
| 36 | # elif defined CONFIG_ARCH_MX51 | ||
| 37 | # define PLAT_PHYS_OFFSET MX51_PHYS_OFFSET | ||
| 38 | # elif defined CONFIG_ARCH_MX53 | ||
| 39 | # define PLAT_PHYS_OFFSET MX53_PHYS_OFFSET | ||
| 40 | # endif | 26 | # endif |
| 41 | #endif | 27 | #endif |
| 42 | 28 | ||
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index 087cd7ac8d52..ccebf5ba12f0 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h | |||
| @@ -41,6 +41,7 @@ | |||
| 41 | #define MX25_SSI2_BASE_ADDR 0x50014000 | 41 | #define MX25_SSI2_BASE_ADDR 0x50014000 |
| 42 | #define MX25_SSI1_BASE_ADDR 0x50034000 | 42 | #define MX25_SSI1_BASE_ADDR 0x50034000 |
| 43 | #define MX25_NFC_BASE_ADDR 0xbb000000 | 43 | #define MX25_NFC_BASE_ADDR 0xbb000000 |
| 44 | #define MX25_IIM_BASE_ADDR 0x53ff0000 | ||
| 44 | #define MX25_DRYICE_BASE_ADDR 0x53ffc000 | 45 | #define MX25_DRYICE_BASE_ADDR 0x53ffc000 |
| 45 | #define MX25_ESDHC1_BASE_ADDR 0x53fb4000 | 46 | #define MX25_ESDHC1_BASE_ADDR 0x53fb4000 |
| 46 | #define MX25_ESDHC2_BASE_ADDR 0x53fb8000 | 47 | #define MX25_ESDHC2_BASE_ADDR 0x53fb8000 |
| @@ -104,4 +105,8 @@ | |||
| 104 | #define MX25_DMA_REQ_SSI1_RX0 28 | 105 | #define MX25_DMA_REQ_SSI1_RX0 28 |
| 105 | #define MX25_DMA_REQ_SSI1_TX0 29 | 106 | #define MX25_DMA_REQ_SSI1_TX0 29 |
| 106 | 107 | ||
| 108 | #ifndef __ASSEMBLY__ | ||
| 109 | extern int mx25_revision(void); | ||
| 110 | #endif | ||
| 111 | |||
| 107 | #endif /* ifndef __MACH_MX25_H__ */ | 112 | #endif /* ifndef __MACH_MX25_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h index d13dbfeef08a..80965a99aa55 100644 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ b/arch/arm/plat-mxc/include/mach/mx35.h | |||
| @@ -36,7 +36,7 @@ | |||
| 36 | #define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000) | 36 | #define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000) |
| 37 | #define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000) | 37 | #define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000) |
| 38 | #define MX35_SSI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x14000) | 38 | #define MX35_SSI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x14000) |
| 39 | #define MX35_ATA_DMA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000) | 39 | #define MX35_ATA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000) |
| 40 | #define MX35_MSHC1_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x24000) | 40 | #define MX35_MSHC1_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x24000) |
| 41 | #define MX35_FEC_BASE_ADDR 0x50038000 | 41 | #define MX35_FEC_BASE_ADDR 0x50038000 |
| 42 | #define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000) | 42 | #define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000) |
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h index 388a407d72d6..30dbf424583e 100644 --- a/arch/arm/plat-mxc/include/mach/mx3x.h +++ b/arch/arm/plat-mxc/include/mach/mx3x.h | |||
| @@ -187,22 +187,8 @@ | |||
| 187 | /* Mandatory defines used globally */ | 187 | /* Mandatory defines used globally */ |
| 188 | 188 | ||
| 189 | #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) | 189 | #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) |
| 190 | 190 | extern int mx35_revision(void); | |
| 191 | extern unsigned int mx31_cpu_rev; | 191 | extern int mx31_revision(void); |
| 192 | extern void mx31_read_cpu_rev(void); | ||
| 193 | |||
| 194 | static inline int mx31_revision(void) | ||
| 195 | { | ||
| 196 | return mx31_cpu_rev; | ||
| 197 | } | ||
| 198 | |||
| 199 | extern unsigned int mx35_cpu_rev; | ||
| 200 | extern void mx35_read_cpu_rev(void); | ||
| 201 | |||
| 202 | static inline int mx35_revision(void) | ||
| 203 | { | ||
| 204 | return mx35_cpu_rev; | ||
| 205 | } | ||
| 206 | #endif | 192 | #endif |
| 207 | 193 | ||
| 208 | #endif /* ifndef __MACH_MX3x_H__ */ | 194 | #endif /* ifndef __MACH_MX3x_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index dede19a766ff..cdf07c65ec1e 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h | |||
| @@ -18,18 +18,6 @@ | |||
| 18 | #define MX51_GPU_CTRL_BASE_ADDR 0x30000000 | 18 | #define MX51_GPU_CTRL_BASE_ADDR 0x30000000 |
| 19 | #define MX51_IPU_CTRL_BASE_ADDR 0x40000000 | 19 | #define MX51_IPU_CTRL_BASE_ADDR 0x40000000 |
| 20 | 20 | ||
| 21 | #define MX51_DEBUG_BASE_ADDR 0x60000000 | ||
| 22 | #define MX51_DEBUG_SIZE SZ_1M | ||
| 23 | |||
| 24 | #define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x01000) | ||
| 25 | #define MX51_ETM_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x02000) | ||
| 26 | #define MX51_TPIU_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x03000) | ||
| 27 | #define MX51_CTI0_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x04000) | ||
| 28 | #define MX51_CTI1_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x05000) | ||
| 29 | #define MX51_CTI2_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x06000) | ||
| 30 | #define MX51_CTI3_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x07000) | ||
| 31 | #define MX51_CORTEX_DBG_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x08000) | ||
| 32 | |||
| 33 | /* | 21 | /* |
| 34 | * SPBA global module enabled #0 | 22 | * SPBA global module enabled #0 |
| 35 | */ | 23 | */ |
| @@ -55,7 +43,10 @@ | |||
| 55 | #define MX51_AIPS1_BASE_ADDR 0x73f00000 | 43 | #define MX51_AIPS1_BASE_ADDR 0x73f00000 |
| 56 | #define MX51_AIPS1_SIZE SZ_1M | 44 | #define MX51_AIPS1_SIZE SZ_1M |
| 57 | 45 | ||
| 58 | #define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000) | 46 | #define MX51_USB_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000) |
| 47 | #define MX51_USB_OTG_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0000) | ||
| 48 | #define MX51_USB_HS1_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0200) | ||
| 49 | #define MX51_USB_HS2_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0400) | ||
| 59 | #define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x84000) | 50 | #define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x84000) |
| 60 | #define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x88000) | 51 | #define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x88000) |
| 61 | #define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x8c000) | 52 | #define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x8c000) |
| @@ -132,6 +123,7 @@ | |||
| 132 | 123 | ||
| 133 | #define MX51_GPU2D_BASE_ADDR 0xd0000000 | 124 | #define MX51_GPU2D_BASE_ADDR 0xd0000000 |
| 134 | #define MX51_TZIC_BASE_ADDR 0xe0000000 | 125 | #define MX51_TZIC_BASE_ADDR 0xe0000000 |
| 126 | #define MX51_TZIC_SIZE SZ_16K | ||
| 135 | 127 | ||
| 136 | #define MX51_IO_P2V(x) IMX_IO_P2V(x) | 128 | #define MX51_IO_P2V(x) IMX_IO_P2V(x) |
| 137 | #define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x)) | 129 | #define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x)) |
| @@ -240,117 +232,114 @@ | |||
| 240 | /* | 232 | /* |
| 241 | * Interrupt numbers | 233 | * Interrupt numbers |
| 242 | */ | 234 | */ |
| 243 | #define MX51_MXC_INT_BASE 0 | 235 | #define MX51_INT_BASE 0 |
| 244 | #define MX51_MXC_INT_RESV0 0 | 236 | #define MX51_INT_RESV0 0 |
| 245 | #define MX51_INT_ESDHC1 1 | 237 | #define MX51_INT_ESDHC1 1 |
| 246 | #define MX51_INT_ESDHC2 2 | 238 | #define MX51_INT_ESDHC2 2 |
| 247 | #define MX51_INT_ESDHC3 3 | 239 | #define MX51_INT_ESDHC3 3 |
| 248 | #define MX51_INT_ESDHC4 4 | 240 | #define MX51_INT_ESDHC4 4 |
| 249 | #define MX51_MXC_INT_RESV5 5 | 241 | #define MX51_INT_RESV5 5 |
| 250 | #define MX51_INT_SDMA 6 | 242 | #define MX51_INT_SDMA 6 |
| 251 | #define MX51_MXC_INT_IOMUX 7 | 243 | #define MX51_INT_IOMUX 7 |
| 252 | #define MX51_INT_NFC 8 | 244 | #define MX51_INT_NFC 8 |
| 253 | #define MX51_MXC_INT_VPU 9 | 245 | #define MX51_INT_VPU 9 |
| 254 | #define MX51_INT_IPU_ERR 10 | 246 | #define MX51_INT_IPU_ERR 10 |
| 255 | #define MX51_INT_IPU_SYN 11 | 247 | #define MX51_INT_IPU_SYN 11 |
| 256 | #define MX51_MXC_INT_GPU 12 | 248 | #define MX51_INT_GPU 12 |
| 257 | #define MX51_MXC_INT_RESV13 13 | 249 | #define MX51_INT_RESV13 13 |
| 258 | #define MX51_MXC_INT_USB_H1 14 | 250 | #define MX51_INT_USB_HS1 14 |
| 259 | #define MX51_MXC_INT_EMI 15 | 251 | #define MX51_INT_EMI 15 |
| 260 | #define MX51_MXC_INT_USB_H2 16 | 252 | #define MX51_INT_USB_HS2 16 |
| 261 | #define MX51_MXC_INT_USB_H3 17 | 253 | #define MX51_INT_USB_HS3 17 |
| 262 | #define MX51_MXC_INT_USB_OTG 18 | 254 | #define MX51_INT_USB_OTG 18 |
| 263 | #define MX51_MXC_INT_SAHARA_H0 19 | 255 | #define MX51_INT_SAHARA_H0 19 |
| 264 | #define MX51_MXC_INT_SAHARA_H1 20 | 256 | #define MX51_INT_SAHARA_H1 20 |
| 265 | #define MX51_MXC_INT_SCC_SMN 21 | 257 | #define MX51_INT_SCC_SMN 21 |
| 266 | #define MX51_MXC_INT_SCC_STZ 22 | 258 | #define MX51_INT_SCC_STZ 22 |
| 267 | #define MX51_MXC_INT_SCC_SCM 23 | 259 | #define MX51_INT_SCC_SCM 23 |
| 268 | #define MX51_MXC_INT_SRTC_NTZ 24 | 260 | #define MX51_INT_SRTC_NTZ 24 |
| 269 | #define MX51_MXC_INT_SRTC_TZ 25 | 261 | #define MX51_INT_SRTC_TZ 25 |
| 270 | #define MX51_MXC_INT_RTIC 26 | 262 | #define MX51_INT_RTIC 26 |
| 271 | #define MX51_MXC_INT_CSU 27 | 263 | #define MX51_INT_CSU 27 |
| 272 | #define MX51_MXC_INT_SLIM_B 28 | 264 | #define MX51_INT_SLIM_B 28 |
| 273 | #define MX51_INT_SSI1 29 | 265 | #define MX51_INT_SSI1 29 |
| 274 | #define MX51_INT_SSI2 30 | 266 | #define MX51_INT_SSI2 30 |
| 275 | #define MX51_INT_UART1 31 | 267 | #define MX51_INT_UART1 31 |
| 276 | #define MX51_INT_UART2 32 | 268 | #define MX51_INT_UART2 32 |
| 277 | #define MX51_INT_UART3 33 | 269 | #define MX51_INT_UART3 33 |
| 278 | #define MX51_MXC_INT_RESV34 34 | 270 | #define MX51_INT_RESV34 34 |
| 279 | #define MX51_MXC_INT_RESV35 35 | 271 | #define MX51_INT_RESV35 35 |
| 280 | #define MX51_INT_ECSPI1 36 | 272 | #define MX51_INT_ECSPI1 36 |
| 281 | #define MX51_INT_ECSPI2 37 | 273 | #define MX51_INT_ECSPI2 37 |
| 282 | #define MX51_INT_CSPI 38 | 274 | #define MX51_INT_CSPI 38 |
| 283 | #define MX51_MXC_INT_GPT 39 | 275 | #define MX51_INT_GPT 39 |
| 284 | #define MX51_MXC_INT_EPIT1 40 | 276 | #define MX51_INT_EPIT1 40 |
| 285 | #define MX51_MXC_INT_EPIT2 41 | 277 | #define MX51_INT_EPIT2 41 |
| 286 | #define MX51_MXC_INT_GPIO1_INT7 42 | 278 | #define MX51_INT_GPIO1_INT7 42 |
| 287 | #define MX51_MXC_INT_GPIO1_INT6 43 | 279 | #define MX51_INT_GPIO1_INT6 43 |
| 288 | #define MX51_MXC_INT_GPIO1_INT5 44 | 280 | #define MX51_INT_GPIO1_INT5 44 |
| 289 | #define MX51_MXC_INT_GPIO1_INT4 45 | 281 | #define MX51_INT_GPIO1_INT4 45 |
| 290 | #define MX51_MXC_INT_GPIO1_INT3 46 | 282 | #define MX51_INT_GPIO1_INT3 46 |
| 291 | #define MX51_MXC_INT_GPIO1_INT2 47 | 283 | #define MX51_INT_GPIO1_INT2 47 |
| 292 | #define MX51_MXC_INT_GPIO1_INT1 48 | 284 | #define MX51_INT_GPIO1_INT1 48 |
| 293 | #define MX51_MXC_INT_GPIO1_INT0 49 | 285 | #define MX51_INT_GPIO1_INT0 49 |
| 294 | #define MX51_MXC_INT_GPIO1_LOW 50 | 286 | #define MX51_INT_GPIO1_LOW 50 |
| 295 | #define MX51_MXC_INT_GPIO1_HIGH 51 | 287 | #define MX51_INT_GPIO1_HIGH 51 |
| 296 | #define MX51_MXC_INT_GPIO2_LOW 52 | 288 | #define MX51_INT_GPIO2_LOW 52 |
| 297 | #define MX51_MXC_INT_GPIO2_HIGH 53 | 289 | #define MX51_INT_GPIO2_HIGH 53 |
| 298 | #define MX51_MXC_INT_GPIO3_LOW 54 | 290 | #define MX51_INT_GPIO3_LOW 54 |
| 299 | #define MX51_MXC_INT_GPIO3_HIGH 55 | 291 | #define MX51_INT_GPIO3_HIGH 55 |
| 300 | #define MX51_MXC_INT_GPIO4_LOW 56 | 292 | #define MX51_INT_GPIO4_LOW 56 |
| 301 | #define MX51_MXC_INT_GPIO4_HIGH 57 | 293 | #define MX51_INT_GPIO4_HIGH 57 |
| 302 | #define MX51_MXC_INT_WDOG1 58 | 294 | #define MX51_INT_WDOG1 58 |
| 303 | #define MX51_MXC_INT_WDOG2 59 | 295 | #define MX51_INT_WDOG2 59 |
| 304 | #define MX51_INT_KPP 60 | 296 | #define MX51_INT_KPP 60 |
| 305 | #define MX51_INT_PWM1 61 | 297 | #define MX51_INT_PWM1 61 |
| 306 | #define MX51_INT_I2C1 62 | 298 | #define MX51_INT_I2C1 62 |
| 307 | #define MX51_INT_I2C2 63 | 299 | #define MX51_INT_I2C2 63 |
| 308 | #define MX51_MXC_INT_HS_I2C 64 | 300 | #define MX51_INT_HS_I2C 64 |
| 309 | #define MX51_MXC_INT_RESV65 65 | 301 | #define MX51_INT_RESV65 65 |
| 310 | #define MX51_MXC_INT_RESV66 66 | 302 | #define MX51_INT_RESV66 66 |
| 311 | #define MX51_MXC_INT_SIM_IPB 67 | 303 | #define MX51_INT_SIM_IPB 67 |
| 312 | #define MX51_MXC_INT_SIM_DAT 68 | 304 | #define MX51_INT_SIM_DAT 68 |
| 313 | #define MX51_MXC_INT_IIM 69 | 305 | #define MX51_INT_IIM 69 |
| 314 | #define MX51_MXC_INT_ATA 70 | 306 | #define MX51_INT_ATA 70 |
| 315 | #define MX51_MXC_INT_CCM1 71 | 307 | #define MX51_INT_CCM1 71 |
| 316 | #define MX51_MXC_INT_CCM2 72 | 308 | #define MX51_INT_CCM2 72 |
| 317 | #define MX51_MXC_INT_GPC1 73 | 309 | #define MX51_INT_GPC1 73 |
| 318 | #define MX51_MXC_INT_GPC2 74 | 310 | #define MX51_INT_GPC2 74 |
| 319 | #define MX51_MXC_INT_SRC 75 | 311 | #define MX51_INT_SRC 75 |
| 320 | #define MX51_MXC_INT_NM 76 | 312 | #define MX51_INT_NM 76 |
| 321 | #define MX51_MXC_INT_PMU 77 | 313 | #define MX51_INT_PMU 77 |
| 322 | #define MX51_MXC_INT_CTI_IRQ 78 | 314 | #define MX51_INT_CTI_IRQ 78 |
| 323 | #define MX51_MXC_INT_CTI1_TG0 79 | 315 | #define MX51_INT_CTI1_TG0 79 |
| 324 | #define MX51_MXC_INT_CTI1_TG1 80 | 316 | #define MX51_INT_CTI1_TG1 80 |
| 325 | #define MX51_MXC_INT_MCG_ERR 81 | 317 | #define MX51_INT_MCG_ERR 81 |
| 326 | #define MX51_MXC_INT_MCG_TMR 82 | 318 | #define MX51_INT_MCG_TMR 82 |
| 327 | #define MX51_MXC_INT_MCG_FUNC 83 | 319 | #define MX51_INT_MCG_FUNC 83 |
| 328 | #define MX51_MXC_INT_GPU2_IRQ 84 | 320 | #define MX51_INT_GPU2_IRQ 84 |
| 329 | #define MX51_MXC_INT_GPU2_BUSY 85 | 321 | #define MX51_INT_GPU2_BUSY 85 |
| 330 | #define MX51_MXC_INT_RESV86 86 | 322 | #define MX51_INT_RESV86 86 |
| 331 | #define MX51_INT_FEC 87 | 323 | #define MX51_INT_FEC 87 |
| 332 | #define MX51_MXC_INT_OWIRE 88 | 324 | #define MX51_INT_OWIRE 88 |
| 333 | #define MX51_MXC_INT_CTI1_TG2 89 | 325 | #define MX51_INT_CTI1_TG2 89 |
| 334 | #define MX51_MXC_INT_SJC 90 | 326 | #define MX51_INT_SJC 90 |
| 335 | #define MX51_MXC_INT_SPDIF 91 | 327 | #define MX51_INT_SPDIF 91 |
| 336 | #define MX51_MXC_INT_TVE 92 | 328 | #define MX51_INT_TVE 92 |
| 337 | #define MX51_MXC_INT_FIRI 93 | 329 | #define MX51_INT_FIRI 93 |
| 338 | #define MX51_INT_PWM2 94 | 330 | #define MX51_INT_PWM2 94 |
| 339 | #define MX51_MXC_INT_SLIM_EXP 95 | 331 | #define MX51_INT_SLIM_EXP 95 |
| 340 | #define MX51_INT_SSI3 96 | 332 | #define MX51_INT_SSI3 96 |
| 341 | #define MX51_MXC_INT_EMI_BOOT 97 | 333 | #define MX51_INT_EMI_BOOT 97 |
| 342 | #define MX51_MXC_INT_CTI1_TG3 98 | 334 | #define MX51_INT_CTI1_TG3 98 |
| 343 | #define MX51_MXC_INT_SMC_RX 99 | 335 | #define MX51_INT_SMC_RX 99 |
| 344 | #define MX51_MXC_INT_VPU_IDLE 100 | 336 | #define MX51_INT_VPU_IDLE 100 |
| 345 | #define MX51_MXC_INT_EMI_NFC 101 | 337 | #define MX51_INT_EMI_NFC 101 |
| 346 | #define MX51_MXC_INT_GPU_IDLE 102 | 338 | #define MX51_INT_GPU_IDLE 102 |
| 347 | 339 | ||
| 348 | #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) | 340 | #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) |
| 349 | extern int mx51_revision(void); | 341 | extern int mx51_revision(void); |
| 350 | extern void mx51_display_revision(void); | 342 | extern void mx51_display_revision(void); |
| 351 | #endif | 343 | #endif |
| 352 | 344 | ||
| 353 | /* tape-out 1 defines */ | ||
| 354 | #define MX51_TZIC_BASE_ADDR_TO1 0x8fffc000 | ||
| 355 | |||
| 356 | #endif /* ifndef __MACH_MX51_H__ */ | 345 | #endif /* ifndef __MACH_MX51_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h index 5e3c3236ebf3..a37e8c353994 100644 --- a/arch/arm/plat-mxc/include/mach/mx53.h +++ b/arch/arm/plat-mxc/include/mach/mx53.h | |||
| @@ -9,6 +9,7 @@ | |||
| 9 | 9 | ||
| 10 | /* TZIC */ | 10 | /* TZIC */ |
| 11 | #define MX53_TZIC_BASE_ADDR 0x0FFFC000 | 11 | #define MX53_TZIC_BASE_ADDR 0x0FFFC000 |
| 12 | #define MX53_TZIC_SIZE SZ_16K | ||
| 12 | 13 | ||
| 13 | /* | 14 | /* |
| 14 | * AHCI SATA | 15 | * AHCI SATA |
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index 09879235a9f5..00a78193c681 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h | |||
| @@ -183,13 +183,6 @@ struct cpu_op { | |||
| 183 | }; | 183 | }; |
| 184 | 184 | ||
| 185 | int tzic_enable_wake(int is_idle); | 185 | int tzic_enable_wake(int is_idle); |
| 186 | enum mxc_cpu_pwr_mode { | ||
| 187 | WAIT_CLOCKED, /* wfi only */ | ||
| 188 | WAIT_UNCLOCKED, /* WAIT */ | ||
| 189 | WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */ | ||
| 190 | STOP_POWER_ON, /* just STOP */ | ||
| 191 | STOP_POWER_OFF, /* STOP + SRPG */ | ||
| 192 | }; | ||
| 193 | 186 | ||
| 194 | extern struct cpu_op *(*get_cpu_op)(int *op); | 187 | extern struct cpu_op *(*get_cpu_op)(int *op); |
| 195 | #endif | 188 | #endif |
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h index 51f02a9d41a3..cf88b3593fba 100644 --- a/arch/arm/plat-mxc/include/mach/system.h +++ b/arch/arm/plat-mxc/include/mach/system.h | |||
| @@ -17,41 +17,12 @@ | |||
| 17 | #ifndef __ASM_ARCH_MXC_SYSTEM_H__ | 17 | #ifndef __ASM_ARCH_MXC_SYSTEM_H__ |
| 18 | #define __ASM_ARCH_MXC_SYSTEM_H__ | 18 | #define __ASM_ARCH_MXC_SYSTEM_H__ |
| 19 | 19 | ||
| 20 | #include <mach/hardware.h> | 20 | extern void (*imx_idle)(void); |
| 21 | #include <mach/common.h> | ||
| 22 | |||
| 23 | extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode); | ||
| 24 | 21 | ||
| 25 | static inline void arch_idle(void) | 22 | static inline void arch_idle(void) |
| 26 | { | 23 | { |
| 27 | /* fix i.MX31 errata TLSbo65953 and i.MX35 errata ENGcm09472 */ | 24 | if (imx_idle != NULL) |
| 28 | if (cpu_is_mx31() || cpu_is_mx35()) { | 25 | (imx_idle)(); |
| 29 | unsigned long reg = 0; | ||
| 30 | __asm__ __volatile__( | ||
| 31 | /* disable I and D cache */ | ||
| 32 | "mrc p15, 0, %0, c1, c0, 0\n" | ||
| 33 | "bic %0, %0, #0x00001000\n" | ||
| 34 | "bic %0, %0, #0x00000004\n" | ||
| 35 | "mcr p15, 0, %0, c1, c0, 0\n" | ||
| 36 | /* invalidate I cache */ | ||
| 37 | "mov %0, #0\n" | ||
| 38 | "mcr p15, 0, %0, c7, c5, 0\n" | ||
| 39 | /* clear and invalidate D cache */ | ||
| 40 | "mov %0, #0\n" | ||
| 41 | "mcr p15, 0, %0, c7, c14, 0\n" | ||
| 42 | /* WFI */ | ||
| 43 | "mov %0, #0\n" | ||
| 44 | "mcr p15, 0, %0, c7, c0, 4\n" | ||
| 45 | "nop\n" "nop\n" "nop\n" "nop\n" | ||
| 46 | "nop\n" "nop\n" "nop\n" | ||
| 47 | /* enable I and D cache */ | ||
| 48 | "mrc p15, 0, %0, c1, c0, 0\n" | ||
| 49 | "orr %0, %0, #0x00001000\n" | ||
| 50 | "orr %0, %0, #0x00000004\n" | ||
| 51 | "mcr p15, 0, %0, c1, c0, 0\n" | ||
| 52 | : "=r" (reg)); | ||
| 53 | } else if (cpu_is_mx51()) | ||
| 54 | mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); | ||
| 55 | else | 26 | else |
| 56 | cpu_do_idle(); | 27 | cpu_do_idle(); |
| 57 | } | 28 | } |
diff --git a/arch/arm/plat-mxc/irq-common.c b/arch/arm/plat-mxc/irq-common.c index 96953e2e4f11..b6e11458e5ae 100644 --- a/arch/arm/plat-mxc/irq-common.c +++ b/arch/arm/plat-mxc/irq-common.c | |||
| @@ -23,17 +23,17 @@ | |||
| 23 | 23 | ||
| 24 | int imx_irq_set_priority(unsigned char irq, unsigned char prio) | 24 | int imx_irq_set_priority(unsigned char irq, unsigned char prio) |
| 25 | { | 25 | { |
| 26 | struct mxc_irq_chip *chip; | 26 | struct irq_chip_generic *gc; |
| 27 | struct irq_chip *base; | 27 | struct mxc_extra_irq *exirq; |
| 28 | int ret; | 28 | int ret; |
| 29 | 29 | ||
| 30 | ret = -ENOSYS; | 30 | ret = -ENOSYS; |
| 31 | 31 | ||
| 32 | base = irq_get_chip(irq); | 32 | gc = irq_get_chip_data(irq); |
| 33 | if (base) { | 33 | if (gc && gc->private) { |
| 34 | chip = container_of(base, struct mxc_irq_chip, base); | 34 | exirq = gc->private; |
| 35 | if (chip->set_priority) | 35 | if (exirq->set_priority) |
| 36 | ret = chip->set_priority(irq, prio); | 36 | ret = exirq->set_priority(irq, prio); |
| 37 | } | 37 | } |
| 38 | 38 | ||
| 39 | return ret; | 39 | return ret; |
| @@ -43,15 +43,16 @@ EXPORT_SYMBOL(imx_irq_set_priority); | |||
| 43 | int mxc_set_irq_fiq(unsigned int irq, unsigned int type) | 43 | int mxc_set_irq_fiq(unsigned int irq, unsigned int type) |
| 44 | { | 44 | { |
| 45 | struct irq_chip_generic *gc; | 45 | struct irq_chip_generic *gc; |
| 46 | int (*set_irq_fiq)(unsigned int, unsigned int); | 46 | struct mxc_extra_irq *exirq; |
| 47 | int ret; | 47 | int ret; |
| 48 | 48 | ||
| 49 | ret = -ENOSYS; | 49 | ret = -ENOSYS; |
| 50 | 50 | ||
| 51 | gc = irq_get_chip_data(irq); | 51 | gc = irq_get_chip_data(irq); |
| 52 | if (gc && gc->private) { | 52 | if (gc && gc->private) { |
| 53 | set_irq_fiq = gc->private; | 53 | exirq = gc->private; |
| 54 | ret = set_irq_fiq(irq, type); | 54 | if (exirq->set_irq_fiq) |
| 55 | ret = exirq->set_irq_fiq(irq, type); | ||
| 55 | } | 56 | } |
| 56 | 57 | ||
| 57 | return ret; | 58 | return ret; |
diff --git a/arch/arm/plat-mxc/irq-common.h b/arch/arm/plat-mxc/irq-common.h index 7203543fb1b3..6ccb3a14c693 100644 --- a/arch/arm/plat-mxc/irq-common.h +++ b/arch/arm/plat-mxc/irq-common.h | |||
| @@ -19,9 +19,8 @@ | |||
| 19 | #ifndef __PLAT_MXC_IRQ_COMMON_H__ | 19 | #ifndef __PLAT_MXC_IRQ_COMMON_H__ |
| 20 | #define __PLAT_MXC_IRQ_COMMON_H__ | 20 | #define __PLAT_MXC_IRQ_COMMON_H__ |
| 21 | 21 | ||
| 22 | struct mxc_irq_chip | 22 | struct mxc_extra_irq |
| 23 | { | 23 | { |
| 24 | struct irq_chip base; | ||
| 25 | int (*set_priority)(unsigned char irq, unsigned char prio); | 24 | int (*set_priority)(unsigned char irq, unsigned char prio); |
| 26 | int (*set_irq_fiq)(unsigned int irq, unsigned int type); | 25 | int (*set_irq_fiq)(unsigned int irq, unsigned int type); |
| 27 | }; | 26 | }; |
diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c index 761c3c940a68..42d74ea59084 100644 --- a/arch/arm/plat-mxc/pwm.c +++ b/arch/arm/plat-mxc/pwm.c | |||
| @@ -57,7 +57,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) | |||
| 57 | if (pwm == NULL || period_ns == 0 || duty_ns > period_ns) | 57 | if (pwm == NULL || period_ns == 0 || duty_ns > period_ns) |
| 58 | return -EINVAL; | 58 | return -EINVAL; |
| 59 | 59 | ||
| 60 | if (cpu_is_mx27() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) { | 60 | if (!(cpu_is_mx1() || cpu_is_mx21())) { |
| 61 | unsigned long long c; | 61 | unsigned long long c; |
| 62 | unsigned long period_cycles, duty_cycles, prescale; | 62 | unsigned long period_cycles, duty_cycles, prescale; |
| 63 | u32 cr; | 63 | u32 cr; |
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c index 8024f2ac177c..9dad8dcc2ea9 100644 --- a/arch/arm/plat-mxc/system.c +++ b/arch/arm/plat-mxc/system.c | |||
| @@ -28,6 +28,9 @@ | |||
| 28 | #include <asm/system.h> | 28 | #include <asm/system.h> |
| 29 | #include <asm/mach-types.h> | 29 | #include <asm/mach-types.h> |
| 30 | 30 | ||
| 31 | void (*imx_idle)(void) = NULL; | ||
| 32 | void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int) = NULL; | ||
| 33 | |||
| 31 | static void __iomem *wdog_base; | 34 | static void __iomem *wdog_base; |
| 32 | 35 | ||
| 33 | /* | 36 | /* |
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c index f257fccdc394..e993a184189a 100644 --- a/arch/arm/plat-mxc/tzic.c +++ b/arch/arm/plat-mxc/tzic.c | |||
| @@ -42,7 +42,7 @@ | |||
| 42 | #define TZIC_SRCCLAR0 0x0280 /* Source Clear Register 0 */ | 42 | #define TZIC_SRCCLAR0 0x0280 /* Source Clear Register 0 */ |
| 43 | #define TZIC_PRIORITY0 0x0400 /* Priority Register 0 */ | 43 | #define TZIC_PRIORITY0 0x0400 /* Priority Register 0 */ |
| 44 | #define TZIC_PND0 0x0D00 /* Pending Register 0 */ | 44 | #define TZIC_PND0 0x0D00 /* Pending Register 0 */ |
| 45 | #define TZIC_HIPND0 0x0D80 /* High Priority Pending Register */ | 45 | #define TZIC_HIPND(i) (0x0D80+ ((i) << 2)) /* High Priority Pending Register */ |
| 46 | #define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2)) /* Wakeup Config Register */ | 46 | #define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2)) /* Wakeup Config Register */ |
| 47 | #define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */ | 47 | #define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */ |
| 48 | #define TZIC_ID0 0x0FD0 /* Indentification Register 0 */ | 48 | #define TZIC_ID0 0x0FD0 /* Indentification Register 0 */ |
| @@ -74,6 +74,12 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type) | |||
| 74 | 74 | ||
| 75 | static unsigned int *wakeup_intr[4]; | 75 | static unsigned int *wakeup_intr[4]; |
| 76 | 76 | ||
| 77 | static struct mxc_extra_irq tzic_extra_irq = { | ||
| 78 | #ifdef CONFIG_FIQ | ||
| 79 | .set_irq_fiq = tzic_set_irq_fiq, | ||
| 80 | #endif | ||
| 81 | }; | ||
| 82 | |||
| 77 | static __init void tzic_init_gc(unsigned int irq_start) | 83 | static __init void tzic_init_gc(unsigned int irq_start) |
| 78 | { | 84 | { |
| 79 | struct irq_chip_generic *gc; | 85 | struct irq_chip_generic *gc; |
| @@ -82,7 +88,7 @@ static __init void tzic_init_gc(unsigned int irq_start) | |||
| 82 | 88 | ||
| 83 | gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base, | 89 | gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base, |
| 84 | handle_level_irq); | 90 | handle_level_irq); |
| 85 | gc->private = tzic_set_irq_fiq; | 91 | gc->private = &tzic_extra_irq; |
| 86 | gc->wake_enabled = IRQ_MSK(32); | 92 | gc->wake_enabled = IRQ_MSK(32); |
| 87 | wakeup_intr[idx] = &gc->wake_active; | 93 | wakeup_intr[idx] = &gc->wake_active; |
| 88 | 94 | ||
| @@ -96,6 +102,28 @@ static __init void tzic_init_gc(unsigned int irq_start) | |||
| 96 | irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0); | 102 | irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0); |
| 97 | } | 103 | } |
| 98 | 104 | ||
| 105 | asmlinkage void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs) | ||
| 106 | { | ||
| 107 | u32 stat; | ||
| 108 | int i, irqofs, handled; | ||
| 109 | |||
| 110 | do { | ||
| 111 | handled = 0; | ||
| 112 | |||
| 113 | for (i = 0; i < 4; i++) { | ||
| 114 | stat = __raw_readl(tzic_base + TZIC_HIPND(i)) & | ||
| 115 | __raw_readl(tzic_base + TZIC_INTSEC0(i)); | ||
| 116 | |||
| 117 | while (stat) { | ||
| 118 | handled = 1; | ||
| 119 | irqofs = fls(stat) - 1; | ||
| 120 | handle_IRQ(irqofs + i * 32, regs); | ||
| 121 | stat &= ~(1 << irqofs); | ||
| 122 | } | ||
| 123 | } | ||
| 124 | } while (handled); | ||
| 125 | } | ||
| 126 | |||
| 99 | /* | 127 | /* |
| 100 | * This function initializes the TZIC hardware and disables all the | 128 | * This function initializes the TZIC hardware and disables all the |
| 101 | * interrupts. It registers the interrupt enable and disable functions | 129 | * interrupts. It registers the interrupt enable and disable functions |