Merge branch 'samsung/devel' of git+ssh://git.linaro.org/home/arndbergmann/public_git/arm-soc into next/devel2

246 files changed, 6955 insertions, 6243 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3c47745c7f7b..bd220b85c550 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -725,9 +725,6 @@ config ARCH_S3C64XX
         select SAMSUNG_IRQ_VIC_TIMER
         select SAMSUNG_IRQ_UART
         select S3C_GPIO_TRACK
-        select S3C_GPIO_PULL_UPDOWN
-        select S3C_GPIO_CFG_S3C24XX
-        select S3C_GPIO_CFG_S3C64XX
         select S3C_DEV_NAND
         select USB_ARCH_HAS_OHCI
         select SAMSUNG_GPIOLIB_4BIT
@@ -1284,6 +1281,20 @@ config ARM_ERRATA_364296
           processor into full low interrupt latency mode. ARM11MPCore
           is not affected.
 
+config ARM_ERRATA_764369
+        bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
+        depends on CPU_V7 && SMP
+        help
+          This option enables the workaround for erratum 764369
+          affecting Cortex-A9 MPCore with two or more processors (all
+          current revisions). Under certain timing circumstances, a data
+          cache line maintenance operation by MVA targeting an Inner
+          Shareable memory region may fail to proceed up to either the
+          Point of Coherency or to the Point of Unification of the
+          system. This workaround adds a DSB instruction before the
+          relevant cache maintenance functions and sets a specific bit
+          in the diagnostic control register of the SCU.
+
 endmenu
 
 source "arch/arm/common/Kconfig"
@@ -2083,7 +2094,7 @@ menu "Power management options"
 source "kernel/power/Kconfig"
 
 config ARCH_SUSPEND_POSSIBLE
-        depends on !ARCH_S5P64X0 && !ARCH_S5PC100
+        depends on !ARCH_S5PC100
         depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
         def_bool y
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts
index 4c053340ce33..e5818668d091 100644
--- a/arch/arm/boot/dts/tegra-harmony.dts
+++ b/arch/arm/boot/dts/tegra-harmony.dts
@@ -57,14 +57,14 @@
         };
 
         sdhci@c8000200 {
-                gpios = <&gpio 69 0>, /* cd, gpio PI5 */
-                        <&gpio 57 0>, /* wp, gpio PH1 */
-                        <&gpio 155 0>; /* power, gpio PT3 */
+                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+                wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+                power-gpios = <&gpio 155 0>; /* gpio PT3 */
         };
 
         sdhci@c8000600 {
-                gpios = <&gpio 58 0>, /* cd, gpio PH2 */
-                        <&gpio 59 0>, /* wp, gpio PH3 */
-                        <&gpio 70 0>; /* power, gpio PI6 */
+                cd-gpios = <&gpio 58 0>; /* gpio PH2 */
+                wp-gpios = <&gpio 59 0>; /* gpio PH3 */
+                power-gpios = <&gpio 70 0>; /* gpio PI6 */
         };
 };
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
index 1940cae00748..64cedca6fc79 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -21,8 +21,8 @@
         };
 
         sdhci@c8000400 {
-                gpios = <&gpio 69 0>, /* cd, gpio PI5 */
-                        <&gpio 57 0>, /* wp, gpio PH1 */
-                        <&gpio 70 0>; /* power, gpio PI6 */
+                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+                wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+                power-gpios = <&gpio 70 0>; /* gpio PI6 */
         };
 };
diff --git a/arch/arm/configs/exynos4_defconfig b/arch/arm/configs/exynos4_defconfig
index da53ff3b4d70..cd40bb56e568 100644
--- a/arch/arm/configs/exynos4_defconfig
+++ b/arch/arm/configs/exynos4_defconfig
@@ -11,6 +11,7 @@ CONFIG_MACH_SMDKV310=y
 CONFIG_MACH_ARMLEX4210=y
 CONFIG_MACH_UNIVERSAL_C210=y
 CONFIG_MACH_NURI=y
+CONFIG_MACH_ORIGEN=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_SMP=y
diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h
index 8c73900da9ed..253cc86318bf 100644
--- a/arch/arm/include/asm/futex.h
+++ b/arch/arm/include/asm/futex.h
@@ -25,17 +25,17 @@
 
 #ifdef CONFIG_SMP
 
-#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg)      \
+#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
         smp_mb();                                               \
         __asm__ __volatile__(                                   \
-        "1:     ldrex   %1, [%2]\n"                             \
+        "1:     ldrex   %1, [%3]\n"                             \
         "       " insn "\n"                                     \
-        "2:     strex   %1, %0, [%2]\n"                         \
-        "       teq     %1, #0\n"                               \
+        "2:     strex   %2, %0, [%3]\n"                         \
+        "       teq     %2, #0\n"                               \
         "       bne     1b\n"                                   \
         "       mov     %0, #0\n"                               \
-        __futex_atomic_ex_table("%4")                           \
-        : "=&r" (ret), "=&r" (oldval)                           \
+        __futex_atomic_ex_table("%5")                           \
+        : "=&r" (ret), "=&r" (oldval), "=&r" (tmp)              \
         : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT)              \
         : "cc", "memory")
 
@@ -73,14 +73,14 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
 #include <linux/preempt.h>
 #include <asm/domain.h>
 
-#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg)      \
+#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
         __asm__ __volatile__(                                   \
-        "1:     " T(ldr) "      %1, [%2]\n"                     \
+        "1:     " T(ldr) "      %1, [%3]\n"                     \
         "       " insn "\n"                                     \
-        "2:     " T(str) "      %0, [%2]\n"                     \
+        "2:     " T(str) "      %0, [%3]\n"                     \
         "       mov     %0, #0\n"                               \
-        __futex_atomic_ex_table("%4")                           \
-        : "=&r" (ret), "=&r" (oldval)                           \
+        __futex_atomic_ex_table("%5")                           \
+        : "=&r" (ret), "=&r" (oldval), "=&r" (tmp)              \
         : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT)              \
         : "cc", "memory")
 
@@ -117,7 +117,7 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
         int cmp = (encoded_op >> 24) & 15;
         int oparg = (encoded_op << 8) >> 20;
         int cmparg = (encoded_op << 20) >> 20;
-        int oldval = 0, ret;
+        int oldval = 0, ret, tmp;
 
         if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
                 oparg = 1 << oparg;
@@ -129,19 +129,19 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
 
         switch (op) {
         case FUTEX_OP_SET:
-                __futex_atomic_op("mov  %0, %3", ret, oldval, uaddr, oparg);
+                __futex_atomic_op("mov  %0, %4", ret, oldval, tmp, uaddr, oparg);
                 break;
         case FUTEX_OP_ADD:
-                __futex_atomic_op("add  %0, %1, %3", ret, oldval, uaddr, oparg);
+                __futex_atomic_op("add  %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
                 break;
         case FUTEX_OP_OR:
-                __futex_atomic_op("orr  %0, %1, %3", ret, oldval, uaddr, oparg);
+                __futex_atomic_op("orr  %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
                 break;
         case FUTEX_OP_ANDN:
-                __futex_atomic_op("and  %0, %1, %3", ret, oldval, uaddr, ~oparg);
+                __futex_atomic_op("and  %0, %1, %4", ret, oldval, tmp, uaddr, ~oparg);
                 break;
         case FUTEX_OP_XOR:
-                __futex_atomic_op("eor  %0, %1, %3", ret, oldval, uaddr, oparg);
+                __futex_atomic_op("eor  %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
                 break;
         default:
                 ret = -ENOSYS;
diff --git a/arch/arm/include/asm/hardware/pl080.h b/arch/arm/include/asm/hardware/pl080.h
index e4a04e4e5627..33c78d7af2e1 100644
--- a/arch/arm/include/asm/hardware/pl080.h
+++ b/arch/arm/include/asm/hardware/pl080.h
@@ -21,6 +21,9 @@
  * OneNAND features.
 */
 
+#ifndef ASM_PL080_H
+#define ASM_PL080_H
+
 #define PL080_INT_STATUS                        (0x00)
 #define PL080_TC_STATUS                         (0x04)
 #define PL080_TC_CLEAR                          (0x08)
@@ -138,3 +141,4 @@ struct pl080s_lli {
         u32     control1;
 };
 
+#endif /* ASM_PL080_H */
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 2c04ed5efeb5..c60a2944f95b 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -478,8 +478,8 @@
 /*
  * Unimplemented (or alternatively implemented) syscalls
  */
-#define __IGNORE_fadvise64_64           1
-#define __IGNORE_migrate_pages          1
+#define __IGNORE_fadvise64_64
+#define __IGNORE_migrate_pages
 
 #endif /* __KERNEL__ */
 #endif /* __ASM_ARM_UNISTD_H */
diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c
index 79ed5e7f204a..7fcddb75c877 100644
--- a/arch/arm/kernel/smp_scu.c
+++ b/arch/arm/kernel/smp_scu.c
@@ -13,6 +13,7 @@
 
 #include <asm/smp_scu.h>
 #include <asm/cacheflush.h>
+#include <asm/cputype.h>
 
 #define SCU_CTRL                0x00
 #define SCU_CONFIG              0x04
@@ -37,6 +38,15 @@ void __init scu_enable(void __iomem *scu_base)
 {
         u32 scu_ctrl;
 
+#ifdef CONFIG_ARM_ERRATA_764369
+        /* Cortex-A9 only */
+        if ((read_cpuid(CPUID_ID) & 0xff0ffff0) == 0x410fc090) {
+                scu_ctrl = __raw_readl(scu_base + 0x30);
+                if (!(scu_ctrl & 1))
+                        __raw_writel(scu_ctrl | 0x1, scu_base + 0x30);
+        }
+#endif
+
         scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
         /* already enabled? */
         if (scu_ctrl & 1)
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index bf977f8514f6..4e66f62b8d41 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -23,8 +23,10 @@
 
 #if defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK)
 #define ARM_EXIT_KEEP(x)        x
+#define ARM_EXIT_DISCARD(x)
 #else
 #define ARM_EXIT_KEEP(x)
+#define ARM_EXIT_DISCARD(x)     x
 #endif
 
 OUTPUT_ARCH(arm)
@@ -39,6 +41,11 @@ jiffies = jiffies_64 + 4;
 SECTIONS
 {
         /*
+         * XXX: The linker does not define how output sections are
+         * assigned to input sections when there are multiple statements
+         * matching the same input section name.  There is no documented
+         * order of matching.
+         *
          * unwind exit sections must be discarded before the rest of the
          * unwind sections get included.
          */
@@ -47,6 +54,9 @@ SECTIONS
                 *(.ARM.extab.exit.text)
                 ARM_CPU_DISCARD(*(.ARM.exidx.cpuexit.text))
                 ARM_CPU_DISCARD(*(.ARM.extab.cpuexit.text))
+                ARM_EXIT_DISCARD(EXIT_TEXT)
+                ARM_EXIT_DISCARD(EXIT_DATA)
+                EXIT_CALL
 #ifndef CONFIG_HOTPLUG
                 *(.ARM.exidx.devexit.text)
                 *(.ARM.extab.devexit.text)
@@ -58,6 +68,8 @@ SECTIONS
 #ifndef CONFIG_SMP_ON_UP
                 *(.alt.smp.init)
 #endif
+                *(.discard)
+                *(.discard.*)
         }
 
 #ifdef CONFIG_XIP_KERNEL
@@ -279,9 +291,6 @@ SECTIONS
 
         STABS_DEBUG
         .comment 0 : { *(.comment) }
-
-        /* Default discards */
-        DISCARDS
 }
 
 /*
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 83dce859886d..a9e0dae86a26 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -158,7 +158,7 @@ void __init dove_spi0_init(void)
 
 void __init dove_spi1_init(void)
 {
-        orion_spi_init(DOVE_SPI1_PHYS_BASE, get_tclk());
+        orion_spi_1_init(DOVE_SPI1_PHYS_BASE, get_tclk());
 }
 
 /*****************************************************************************
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index 0c77ab99fa16..dd660eb20204 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -11,10 +11,24 @@ if ARCH_EXYNOS4
 
 config CPU_EXYNOS4210
         bool
-        select S3C_PL330_DMA
+        select SAMSUNG_DMADEV
+        select S5P_PM if PM
+        select S5P_SLEEP if PM
         help
           Enable EXYNOS4210 CPU support
 
+config SOC_EXYNOS4212
+        bool
+        select S5P_PM if PM
+        select S5P_SLEEP if PM
+        help
+          Enable EXYNOS4212 SoC support
+
+config SOC_EXYNOS4412
+        bool
+        help
+          Enable EXYNOS4412 SoC support
+
 config EXYNOS4_MCT
         bool
         default y
@@ -111,24 +125,11 @@ config EXYNOS4_SETUP_USB_PHY
 
 menu "EXYNOS4 Machines"
 
+comment "EXYNOS4210 Boards"
+
 config MACH_SMDKC210
         bool "SMDKC210"
-        select CPU_EXYNOS4210
-        select S5P_DEV_FIMD0
-        select S3C_DEV_RTC
-        select S3C_DEV_WDT
-        select S3C_DEV_I2C1
-        select S3C_DEV_HSMMC
-        select S3C_DEV_HSMMC1
-        select S3C_DEV_HSMMC2
-        select S3C_DEV_HSMMC3
-        select SAMSUNG_DEV_PWM
-        select SAMSUNG_DEV_BACKLIGHT
-        select EXYNOS4_DEV_PD
-        select EXYNOS4_DEV_SYSMMU
-        select EXYNOS4_SETUP_FIMD0
-        select EXYNOS4_SETUP_I2C1
-        select EXYNOS4_SETUP_SDHCI
+        select MACH_SMDKV310
         help
           Machine support for Samsung SMDKC210
 
@@ -139,6 +140,14 @@ config MACH_SMDKV310
         select S3C_DEV_RTC
         select S3C_DEV_WDT
         select S3C_DEV_I2C1
+        select S5P_DEV_FIMC0
+        select S5P_DEV_FIMC1
+        select S5P_DEV_FIMC2
+        select S5P_DEV_FIMC3
+        select S5P_DEV_I2C_HDMIPHY
+        select S5P_DEV_MFC
+        select S5P_DEV_TV
+        select S5P_DEV_USB_EHCI
         select S3C_DEV_HSMMC
         select S3C_DEV_HSMMC1
         select S3C_DEV_HSMMC2
@@ -153,6 +162,7 @@ config MACH_SMDKV310
         select EXYNOS4_SETUP_I2C1
         select EXYNOS4_SETUP_KEYPAD
         select EXYNOS4_SETUP_SDHCI
+        select EXYNOS4_SETUP_USB_PHY
         help
           Machine support for Samsung SMDKV310
 
@@ -178,19 +188,26 @@ config MACH_UNIVERSAL_C210
         select S5P_DEV_FIMC1
         select S5P_DEV_FIMC2
         select S5P_DEV_FIMC3
+        select S5P_DEV_CSIS0
+        select S5P_DEV_FIMD0
         select S3C_DEV_HSMMC
         select S3C_DEV_HSMMC2
         select S3C_DEV_HSMMC3
         select S3C_DEV_I2C1
         select S3C_DEV_I2C3
         select S3C_DEV_I2C5
+        select S5P_DEV_I2C_HDMIPHY
         select S5P_DEV_MFC
         select S5P_DEV_ONENAND
+        select S5P_DEV_TV
         select EXYNOS4_DEV_PD
+        select EXYNOS4_SETUP_FIMD0
         select EXYNOS4_SETUP_I2C1
         select EXYNOS4_SETUP_I2C3
         select EXYNOS4_SETUP_I2C5
         select EXYNOS4_SETUP_SDHCI
+        select EXYNOS4_SETUP_FIMC
+        select S5P_SETUP_MIPIPHY
         help
           Machine support for Samsung Mobile Universal S5PC210 Reference
           Board.
@@ -199,6 +216,8 @@ config MACH_NURI
         bool "Mobile NURI Board"
         select CPU_EXYNOS4210
         select S3C_DEV_WDT
+        select S3C_DEV_RTC
+        select S5P_DEV_FIMD0
         select S3C_DEV_HSMMC
         select S3C_DEV_HSMMC2
         select S3C_DEV_HSMMC3
@@ -208,6 +227,7 @@ config MACH_NURI
         select S5P_DEV_MFC
         select S5P_DEV_USB_EHCI
         select EXYNOS4_DEV_PD
+        select EXYNOS4_SETUP_FIMD0
         select EXYNOS4_SETUP_I2C1
         select EXYNOS4_SETUP_I2C3
         select EXYNOS4_SETUP_I2C5
@@ -218,6 +238,62 @@ config MACH_NURI
         help
           Machine support for Samsung Mobile NURI Board.
 
+config MACH_ORIGEN
+        bool "ORIGEN"
+        select CPU_EXYNOS4210
+        select S3C_DEV_RTC
+        select S3C_DEV_WDT
+        select S3C_DEV_HSMMC
+        select S3C_DEV_HSMMC2
+        select S5P_DEV_FIMC0
+        select S5P_DEV_FIMC1
+        select S5P_DEV_FIMC2
+        select S5P_DEV_FIMC3
+        select S5P_DEV_FIMD0
+        select S5P_DEV_I2C_HDMIPHY
+        select S5P_DEV_TV
+        select S5P_DEV_USB_EHCI
+        select EXYNOS4_DEV_PD
+        select SAMSUNG_DEV_BACKLIGHT
+        select SAMSUNG_DEV_PWM
+        select EXYNOS4_SETUP_FIMD0
+        select EXYNOS4_SETUP_SDHCI
+        select EXYNOS4_SETUP_USB_PHY
+        help
+          Machine support for ORIGEN based on Samsung EXYNOS4210
+
+comment "EXYNOS4212 Boards"
+
+config MACH_SMDK4212
+        bool "SMDK4212"
+        select SOC_EXYNOS4212
+        select S3C_DEV_HSMMC2
+        select S3C_DEV_HSMMC3
+        select S3C_DEV_I2C1
+        select S3C_DEV_I2C3
+        select S3C_DEV_I2C7
+        select S3C_DEV_RTC
+        select S3C_DEV_WDT
+        select SAMSUNG_DEV_BACKLIGHT
+        select SAMSUNG_DEV_KEYPAD
+        select SAMSUNG_DEV_PWM
+        select EXYNOS4_SETUP_I2C1
+        select EXYNOS4_SETUP_I2C3
+        select EXYNOS4_SETUP_I2C7
+        select EXYNOS4_SETUP_KEYPAD
+        select EXYNOS4_SETUP_SDHCI
+        help
+          Machine support for Samsung SMDK4212
+
+comment "EXYNOS4412 Boards"
+
+config MACH_SMDK4412
+        bool "SMDK4412"
+        select SOC_EXYNOS4412
+        select MACH_SMDK4212
+        help
+          Machine support for Samsung SMDK4412
+
 endmenu
 
 comment "Configuration for HSMMC bus width"
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index b7fe1d7b0b1f..2bb18f431db9 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -12,9 +12,11 @@ obj-				:=
 
 # Core support for EXYNOS4 system
 
-obj-$(CONFIG_CPU_EXYNOS4210)    += cpu.o init.o clock.o irq-combiner.o
-obj-$(CONFIG_CPU_EXYNOS4210)    += setup-i2c0.o irq-eint.o dma.o pmu.o
-obj-$(CONFIG_PM)                += pm.o sleep.o
+obj-$(CONFIG_ARCH_EXYNOS4)      += cpu.o init.o clock.o irq-combiner.o
+obj-$(CONFIG_ARCH_EXYNOS4)      += setup-i2c0.o irq-eint.o dma.o pmu.o
+obj-$(CONFIG_CPU_EXYNOS4210)    += clock-exynos4210.o
+obj-$(CONFIG_SOC_EXYNOS4212)    += clock-exynos4212.o
+obj-$(CONFIG_PM)                += pm.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
 
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
@@ -25,11 +27,15 @@ obj-$(CONFIG_HOTPLUG_CPU)	+= hotplug.o
 
 # machine support
 
-obj-$(CONFIG_MACH_SMDKC210)             += mach-smdkc210.o
+obj-$(CONFIG_MACH_SMDKC210)             += mach-smdkv310.o
 obj-$(CONFIG_MACH_SMDKV310)             += mach-smdkv310.o
 obj-$(CONFIG_MACH_ARMLEX4210)           += mach-armlex4210.o
 obj-$(CONFIG_MACH_UNIVERSAL_C210)       += mach-universal_c210.o
 obj-$(CONFIG_MACH_NURI)                 += mach-nuri.o
+obj-$(CONFIG_MACH_ORIGEN)               += mach-origen.o
+
+obj-$(CONFIG_MACH_SMDK4212)             += mach-smdk4x12.o
+obj-$(CONFIG_MACH_SMDK4412)             += mach-smdk4x12.o
 
 # device support
 
diff --git a/arch/arm/mach-exynos4/clock-exynos4210.c b/arch/arm/mach-exynos4/clock-exynos4210.c
new file mode 100644
index 000000000000..b9d5ef670eb4
--- /dev/null
+++ b/arch/arm/mach-exynos4/clock-exynos4210.c
@@ -0,0 +1,139 @@
+/*
+ * linux/arch/arm/mach-exynos4/clock-exynos4210.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * EXYNOS4210 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/syscore_ops.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/exynos4.h>
+#include <plat/pm.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/exynos4-clock.h>
+
+static struct sleep_save exynos4210_clock_save[] = {
+        SAVE_ITEM(S5P_CLKSRC_IMAGE),
+        SAVE_ITEM(S5P_CLKSRC_LCD1),
+        SAVE_ITEM(S5P_CLKDIV_IMAGE),
+        SAVE_ITEM(S5P_CLKDIV_LCD1),
+        SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
+        SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
+        SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
+        SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
+};
+
+static struct clksrc_clk *sysclks[] = {
+        /* nothing here yet */
+};
+
+static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
+}
+
+static struct clksrc_clk clksrcs[] = {
+        {
+                .clk            = {
+                        .name           = "sclk_sata",
+                        .id             = -1,
+                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                        .ctrlbit        = (1 << 24),
+                },
+                .sources = &clkset_mout_corebus,
+                .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
+                .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_fimd",
+                        .devname        = "exynos4-fb.1",
+                        .enable         = exynos4_clksrc_mask_lcd1_ctrl,
+                        .ctrlbit        = (1 << 0),
+                },
+                .sources = &clkset_group,
+                .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
+                .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
+        },
+};
+
+static struct clk init_clocks_off[] = {
+        {
+                .name           = "sataphy",
+                .id             = -1,
+                .parent         = &clk_aclk_133.clk,
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "sata",
+                .id             = -1,
+                .parent         = &clk_aclk_133.clk,
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 10),
+        }, {
+                .name           = "fimd",
+                .devname        = "exynos4-fb.1",
+                .enable         = exynos4_clk_ip_lcd1_ctrl,
+                .ctrlbit        = (1 << 0),
+        },
+};
+
+#ifdef CONFIG_PM_SLEEP
+static int exynos4210_clock_suspend(void)
+{
+        s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
+
+        return 0;
+}
+
+static void exynos4210_clock_resume(void)
+{
+        s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
+}
+
+#else
+#define exynos4210_clock_suspend NULL
+#define exynos4210_clock_resume NULL
+#endif
+
+struct syscore_ops exynos4210_clock_syscore_ops = {
+        .suspend        = exynos4210_clock_suspend,
+        .resume         = exynos4210_clock_resume,
+};
+
+void __init exynos4210_register_clocks(void)
+{
+        int ptr;
+
+        clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU;
+        clk_mout_mpll.reg_src.shift = 8;
+        clk_mout_mpll.reg_src.size = 1;
+
+        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
+                s3c_register_clksrc(sysclks[ptr], 1);
+
+        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+
+        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+
+        register_syscore_ops(&exynos4210_clock_syscore_ops);
+}
diff --git a/arch/arm/mach-exynos4/clock-exynos4212.c b/arch/arm/mach-exynos4/clock-exynos4212.c
new file mode 100644
index 000000000000..77d5decb34fd
--- /dev/null
+++ b/arch/arm/mach-exynos4/clock-exynos4212.c
@@ -0,0 +1,118 @@
+/*
+ * linux/arch/arm/mach-exynos4/clock-exynos4212.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * EXYNOS4212 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/syscore_ops.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/exynos4.h>
+#include <plat/pm.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/exynos4-clock.h>
+
+static struct sleep_save exynos4212_clock_save[] = {
+        SAVE_ITEM(S5P_CLKSRC_IMAGE),
+        SAVE_ITEM(S5P_CLKDIV_IMAGE),
+        SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
+        SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
+};
+
+static struct clk *clk_src_mpll_user_list[] = {
+        [0] = &clk_fin_mpll,
+        [1] = &clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources clk_src_mpll_user = {
+        .sources        = clk_src_mpll_user_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_mpll_user_list),
+};
+
+static struct clksrc_clk clk_mout_mpll_user = {
+        .clk = {
+                .name           = "mout_mpll_user",
+        },
+        .sources        = &clk_src_mpll_user,
+        .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 },
+};
+
+static struct clksrc_clk *sysclks[] = {
+        &clk_mout_mpll_user,
+};
+
+static struct clksrc_clk clksrcs[] = {
+        /* nothing here yet */
+};
+
+static struct clk init_clocks_off[] = {
+        /* nothing here yet */
+};
+
+#ifdef CONFIG_PM_SLEEP
+static int exynos4212_clock_suspend(void)
+{
+        s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
+
+        return 0;
+}
+
+static void exynos4212_clock_resume(void)
+{
+        s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
+}
+
+#else
+#define exynos4212_clock_suspend NULL
+#define exynos4212_clock_resume NULL
+#endif
+
+struct syscore_ops exynos4212_clock_syscore_ops = {
+        .suspend        = exynos4212_clock_suspend,
+        .resume         = exynos4212_clock_resume,
+};
+
+void __init exynos4212_register_clocks(void)
+{
+        int ptr;
+
+        /* usbphy1 is removed */
+        clkset_group_list[4] = NULL;
+
+        /* mout_mpll_user is used */
+        clkset_group_list[6] = &clk_mout_mpll_user.clk;
+        clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
+
+        clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC;
+        clk_mout_mpll.reg_src.shift = 12;
+        clk_mout_mpll.reg_src.size = 1;
+
+        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
+                s3c_register_clksrc(sysclks[ptr], 1);
+
+        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+
+        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+
+        register_syscore_ops(&exynos4212_clock_syscore_ops);
+}
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index 1561b036a9bf..db616916d7a4 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -13,6 +13,7 @@
 #include <linux/kernel.h>
 #include <linux/err.h>
 #include <linux/io.h>
+#include <linux/syscore_ops.h>
 
 #include <plat/cpu-freq.h>
 #include <plat/clock.h>
@@ -20,29 +21,101 @@
 #include <plat/pll.h>
 #include <plat/s5p-clock.h>
 #include <plat/clock-clksrc.h>
+#include <plat/exynos4.h>
+#include <plat/pm.h>
 
 #include <mach/map.h>
 #include <mach/regs-clock.h>
 #include <mach/sysmmu.h>
-
-static struct clk clk_sclk_hdmi27m = {
+#include <mach/exynos4-clock.h>
+
+static struct sleep_save exynos4_clock_save[] = {
+        SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
+        SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
+        SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
+        SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
+        SAVE_ITEM(S5P_CLKSRC_TOP0),
+        SAVE_ITEM(S5P_CLKSRC_TOP1),
+        SAVE_ITEM(S5P_CLKSRC_CAM),
+        SAVE_ITEM(S5P_CLKSRC_TV),
+        SAVE_ITEM(S5P_CLKSRC_MFC),
+        SAVE_ITEM(S5P_CLKSRC_G3D),
+        SAVE_ITEM(S5P_CLKSRC_LCD0),
+        SAVE_ITEM(S5P_CLKSRC_MAUDIO),
+        SAVE_ITEM(S5P_CLKSRC_FSYS),
+        SAVE_ITEM(S5P_CLKSRC_PERIL0),
+        SAVE_ITEM(S5P_CLKSRC_PERIL1),
+        SAVE_ITEM(S5P_CLKDIV_CAM),
+        SAVE_ITEM(S5P_CLKDIV_TV),
+        SAVE_ITEM(S5P_CLKDIV_MFC),
+        SAVE_ITEM(S5P_CLKDIV_G3D),
+        SAVE_ITEM(S5P_CLKDIV_LCD0),
+        SAVE_ITEM(S5P_CLKDIV_MAUDIO),
+        SAVE_ITEM(S5P_CLKDIV_FSYS0),
+        SAVE_ITEM(S5P_CLKDIV_FSYS1),
+        SAVE_ITEM(S5P_CLKDIV_FSYS2),
+        SAVE_ITEM(S5P_CLKDIV_FSYS3),
+        SAVE_ITEM(S5P_CLKDIV_PERIL0),
+        SAVE_ITEM(S5P_CLKDIV_PERIL1),
+        SAVE_ITEM(S5P_CLKDIV_PERIL2),
+        SAVE_ITEM(S5P_CLKDIV_PERIL3),
+        SAVE_ITEM(S5P_CLKDIV_PERIL4),
+        SAVE_ITEM(S5P_CLKDIV_PERIL5),
+        SAVE_ITEM(S5P_CLKDIV_TOP),
+        SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
+        SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
+        SAVE_ITEM(S5P_CLKSRC_MASK_TV),
+        SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
+        SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
+        SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
+        SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
+        SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
+        SAVE_ITEM(S5P_CLKDIV2_RATIO),
+        SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
+        SAVE_ITEM(S5P_CLKGATE_IP_CAM),
+        SAVE_ITEM(S5P_CLKGATE_IP_TV),
+        SAVE_ITEM(S5P_CLKGATE_IP_MFC),
+        SAVE_ITEM(S5P_CLKGATE_IP_G3D),
+        SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
+        SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
+        SAVE_ITEM(S5P_CLKGATE_IP_GPS),
+        SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
+        SAVE_ITEM(S5P_CLKGATE_BLOCK),
+        SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
+        SAVE_ITEM(S5P_CLKSRC_DMC),
+        SAVE_ITEM(S5P_CLKDIV_DMC0),
+        SAVE_ITEM(S5P_CLKDIV_DMC1),
+        SAVE_ITEM(S5P_CLKGATE_IP_DMC),
+        SAVE_ITEM(S5P_CLKSRC_CPU),
+        SAVE_ITEM(S5P_CLKDIV_CPU),
+        SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
+        SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
+        SAVE_ITEM(S5P_CLKGATE_IP_CPU),
+};
+
+struct clk clk_sclk_hdmi27m = {
         .name           = "sclk_hdmi27m",
         .rate           = 27000000,
 };
 
-static struct clk clk_sclk_hdmiphy = {
+struct clk clk_sclk_hdmiphy = {
         .name           = "sclk_hdmiphy",
 };
 
-static struct clk clk_sclk_usbphy0 = {
+struct clk clk_sclk_usbphy0 = {
         .name           = "sclk_usbphy0",
         .rate           = 27000000,
 };
 
-static struct clk clk_sclk_usbphy1 = {
+struct clk clk_sclk_usbphy1 = {
         .name           = "sclk_usbphy1",
 };
 
+static struct clk dummy_apb_pclk = {
+        .name           = "apb_pclk",
+        .id             = -1,
+};
+
 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
@@ -58,12 +131,7 @@ static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
         return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
 }
 
-static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
-}
-
-static int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
+int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
 }
@@ -83,6 +151,11 @@ static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
         return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
 }
 
+static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable);
+}
+
 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
@@ -103,12 +176,12 @@ static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
         return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
 }
 
-static int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
+int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
 }
 
-static int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
+int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
 }
@@ -123,6 +196,16 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
         return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
 }
 
+static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
+}
+
+static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
+}
+
 /* Core list of CMU_CPU side */
 
 static struct clksrc_clk clk_mout_apll = {
@@ -133,7 +216,7 @@ static struct clksrc_clk clk_mout_apll = {
         .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
 };
 
-static struct clksrc_clk clk_sclk_apll = {
+struct clksrc_clk clk_sclk_apll = {
         .clk    = {
                 .name           = "sclk_apll",
                 .parent         = &clk_mout_apll.clk,
@@ -141,7 +224,7 @@ static struct clksrc_clk clk_sclk_apll = {
         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
 };
 
-static struct clksrc_clk clk_mout_epll = {
+struct clksrc_clk clk_mout_epll = {
         .clk    = {
                 .name           = "mout_epll",
         },
@@ -149,12 +232,13 @@ static struct clksrc_clk clk_mout_epll = {
         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
 };
 
-static struct clksrc_clk clk_mout_mpll = {
+struct clksrc_clk clk_mout_mpll = {
         .clk = {
                 .name           = "mout_mpll",
         },
         .sources        = &clk_src_mpll,
-        .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
+
+        /* reg_src will be added in each SoCs' clock */
 };
 
 static struct clk *clkset_moutcore_list[] = {
@@ -224,12 +308,12 @@ static struct clksrc_clk clk_periphclk = {
 
 /* Core list of CMU_CORE side */
 
-static struct clk *clkset_corebus_list[] = {
+struct clk *clkset_corebus_list[] = {
         [0] = &clk_mout_mpll.clk,
         [1] = &clk_sclk_apll.clk,
 };
 
-static struct clksrc_sources clkset_mout_corebus = {
+struct clksrc_sources clkset_mout_corebus = {
         .sources        = clkset_corebus_list,
         .nr_sources     = ARRAY_SIZE(clkset_corebus_list),
 };
@@ -284,12 +368,12 @@ static struct clksrc_clk clk_pclk_acp = {
 
 /* Core list of CMU_TOP side */
 
-static struct clk *clkset_aclk_top_list[] = {
+struct clk *clkset_aclk_top_list[] = {
         [0] = &clk_mout_mpll.clk,
         [1] = &clk_sclk_apll.clk,
 };
 
-static struct clksrc_sources clkset_aclk = {
+struct clksrc_sources clkset_aclk = {
         .sources        = clkset_aclk_top_list,
         .nr_sources     = ARRAY_SIZE(clkset_aclk_top_list),
 };
@@ -321,7 +405,7 @@ static struct clksrc_clk clk_aclk_160 = {
         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
 };
 
-static struct clksrc_clk clk_aclk_133 = {
+struct clksrc_clk clk_aclk_133 = {
         .clk    = {
                 .name           = "aclk_133",
         },
@@ -360,7 +444,7 @@ static struct clksrc_sources clkset_sclk_vpll = {
         .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
 };
 
-static struct clksrc_clk clk_sclk_vpll = {
+struct clksrc_clk clk_sclk_vpll = {
         .clk    = {
                 .name           = "sclk_vpll",
         },
@@ -410,16 +494,6 @@ static struct clk init_clocks_off[] = {
                 .enable         = exynos4_clk_ip_lcd0_ctrl,
                 .ctrlbit        = (1 << 0),
         }, {
-                .name           = "fimd",
-                .devname        = "exynos4-fb.1",
-                .enable         = exynos4_clk_ip_lcd1_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "sataphy",
-                .parent         = &clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
                 .name           = "hsmmc",
                 .devname        = "s3c-sdhci.0",
                 .parent         = &clk_aclk_133.clk,
@@ -449,18 +523,48 @@ static struct clk init_clocks_off[] = {
                 .enable         = exynos4_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 9),
         }, {
+                .name           = "dac",
+                .devname        = "s5p-sdo",
+                .enable         = exynos4_clk_ip_tv_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "mixer",
+                .devname        = "s5p-mixer",
+                .enable         = exynos4_clk_ip_tv_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "vp",
+                .devname        = "s5p-mixer",
+                .enable         = exynos4_clk_ip_tv_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "hdmi",
+                .devname        = "exynos4-hdmi",
+                .enable         = exynos4_clk_ip_tv_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "hdmiphy",
+                .devname        = "exynos4-hdmi",
+                .enable         = exynos4_clk_hdmiphy_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "dacphy",
+                .devname        = "s5p-sdo",
+                .enable         = exynos4_clk_dac_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
                 .name           = "sata",
                 .parent         = &clk_aclk_133.clk,
                 .enable         = exynos4_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 10),
         }, {
-                .name           = "pdma",
-                .devname        = "s3c-pl330.0",
+                .name           = "dma",
+                .devname        = "dma-pl330.0",
                 .enable         = exynos4_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 0),
         }, {
-                .name           = "pdma",
-                .devname        = "s3c-pl330.1",
+                .name           = "dma",
+                .devname        = "dma-pl330.1",
                 .enable         = exynos4_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 1),
         }, {
@@ -581,6 +685,12 @@ static struct clk init_clocks_off[] = {
                 .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 13),
         }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-hdmiphy-i2c",
+                .parent         = &clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 14),
+        }, {
                 .name           = "SYSMMU_MDMA",
                 .enable         = exynos4_clk_ip_image_ctrl,
                 .ctrlbit        = (1 << 5),
@@ -673,7 +783,7 @@ static struct clk init_clocks[] = {
         }
 };
 
-static struct clk *clkset_group_list[] = {
+struct clk *clkset_group_list[] = {
         [0] = &clk_ext_xtal_mux,
         [1] = &clk_xusbxti,
         [2] = &clk_sclk_hdmi27m,
@@ -685,7 +795,7 @@ static struct clk *clkset_group_list[] = {
         [8] = &clk_sclk_vpll.clk,
 };
 
-static struct clksrc_sources clkset_group = {
+struct clksrc_sources clkset_group = {
         .sources        = clkset_group_list,
         .nr_sources     = ARRAY_SIZE(clkset_group_list),
 };
@@ -782,6 +892,81 @@ static struct clksrc_sources clkset_mout_mfc = {
         .nr_sources     = ARRAY_SIZE(clkset_mout_mfc_list),
 };
 
+static struct clk *clkset_sclk_dac_list[] = {
+        [0] = &clk_sclk_vpll.clk,
+        [1] = &clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources clkset_sclk_dac = {
+        .sources        = clkset_sclk_dac_list,
+        .nr_sources     = ARRAY_SIZE(clkset_sclk_dac_list),
+};
+
+static struct clksrc_clk clk_sclk_dac = {
+        .clk            = {
+                .name           = "sclk_dac",
+                .enable         = exynos4_clksrc_mask_tv_ctrl,
+                .ctrlbit        = (1 << 8),
+        },
+        .sources = &clkset_sclk_dac,
+        .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 },
+};
+
+static struct clksrc_clk clk_sclk_pixel = {
+        .clk            = {
+                .name           = "sclk_pixel",
+                .parent = &clk_sclk_vpll.clk,
+        },
+        .reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 },
+};
+
+static struct clk *clkset_sclk_hdmi_list[] = {
+        [0] = &clk_sclk_pixel.clk,
+        [1] = &clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources clkset_sclk_hdmi = {
+        .sources        = clkset_sclk_hdmi_list,
+        .nr_sources     = ARRAY_SIZE(clkset_sclk_hdmi_list),
+};
+
+static struct clksrc_clk clk_sclk_hdmi = {
+        .clk            = {
+                .name           = "sclk_hdmi",
+                .enable         = exynos4_clksrc_mask_tv_ctrl,
+                .ctrlbit        = (1 << 0),
+        },
+        .sources = &clkset_sclk_hdmi,
+        .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 },
+};
+
+static struct clk *clkset_sclk_mixer_list[] = {
+        [0] = &clk_sclk_dac.clk,
+        [1] = &clk_sclk_hdmi.clk,
+};
+
+static struct clksrc_sources clkset_sclk_mixer = {
+        .sources        = clkset_sclk_mixer_list,
+        .nr_sources     = ARRAY_SIZE(clkset_sclk_mixer_list),
+};
+
+static struct clksrc_clk clk_sclk_mixer = {
+        .clk            = {
+                .name           = "sclk_mixer",
+                .enable         = exynos4_clksrc_mask_tv_ctrl,
+                .ctrlbit        = (1 << 4),
+        },
+        .sources = &clkset_sclk_mixer,
+        .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 },
+};
+
+static struct clksrc_clk *sclk_tv[] = {
+        &clk_sclk_dac,
+        &clk_sclk_pixel,
+        &clk_sclk_hdmi,
+        &clk_sclk_mixer,
+};
+
 static struct clksrc_clk clk_dout_mmc0 = {
         .clk            = {
                 .name           = "dout_mmc0",
@@ -899,8 +1084,7 @@ static struct clksrc_clk clksrcs[] = {
                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
         }, {
                 .clk            = {
-                        .name           = "sclk_cam",
-                        .devname        = "exynos4-fimc.0",
+                        .name           = "sclk_cam0",
                         .enable         = exynos4_clksrc_mask_cam_ctrl,
                         .ctrlbit        = (1 << 16),
                 },
@@ -909,8 +1093,7 @@ static struct clksrc_clk clksrcs[] = {
                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
         }, {
                 .clk            = {
-                        .name           = "sclk_cam",
-                        .devname        = "exynos4-fimc.1",
+                        .name           = "sclk_cam1",
                         .enable         = exynos4_clksrc_mask_cam_ctrl,
                         .ctrlbit        = (1 << 20),
                 },
@@ -969,25 +1152,6 @@ static struct clksrc_clk clksrcs[] = {
                 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
         }, {
                 .clk            = {
-                        .name           = "sclk_fimd",
-                        .devname        = "exynos4-fb.1",
-                        .enable         = exynos4_clksrc_mask_lcd1_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_sata",
-                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &clkset_mout_corebus,
-                .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
-                .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
-        }, {
-                .clk            = {
                         .name           = "sclk_spi",
                         .devname        = "s3c64xx-spi.0",
                         .enable         = exynos4_clksrc_mask_peril1_ctrl,
@@ -1116,20 +1280,91 @@ static int xtal_rate;
 
 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
 {
-        return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508);
+        if (soc_is_exynos4210())
+                return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
+                                        pll_4508);
+        else if (soc_is_exynos4212() || soc_is_exynos4412())
+                return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
+        else
+                return 0;
 }
 
 static struct clk_ops exynos4_fout_apll_ops = {
         .get_rate = exynos4_fout_apll_get_rate,
 };
 
+static u32 vpll_div[][8] = {
+        {  54000000, 3, 53, 3, 1024, 0, 17, 0 },
+        { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
+};
+
+static unsigned long exynos4_vpll_get_rate(struct clk *clk)
+{
+        return clk->rate;
+}
+
+static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned int vpll_con0, vpll_con1 = 0;
+        unsigned int i;
+
+        /* Return if nothing changed */
+        if (clk->rate == rate)
+                return 0;
+
+        vpll_con0 = __raw_readl(S5P_VPLL_CON0);
+        vpll_con0 &= ~(0x1 << 27 |                                      \
+                        PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |       \
+                        PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |       \
+                        PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
+
+        vpll_con1 = __raw_readl(S5P_VPLL_CON1);
+        vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT |  \
+                        PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
+                        PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
+
+        for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
+                if (vpll_div[i][0] == rate) {
+                        vpll_con0 |= vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
+                        vpll_con0 |= vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
+                        vpll_con0 |= vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
+                        vpll_con1 |= vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
+                        vpll_con1 |= vpll_div[i][5] << PLL46XX_MFR_SHIFT;
+                        vpll_con1 |= vpll_div[i][6] << PLL46XX_MRR_SHIFT;
+                        vpll_con0 |= vpll_div[i][7] << 27;
+                        break;
+                }
+        }
+
+        if (i == ARRAY_SIZE(vpll_div)) {
+                printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
+                                __func__);
+                return -EINVAL;
+        }
+
+        __raw_writel(vpll_con0, S5P_VPLL_CON0);
+        __raw_writel(vpll_con1, S5P_VPLL_CON1);
+
+        /* Wait for VPLL lock */
+        while (!(__raw_readl(S5P_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
+                continue;
+
+        clk->rate = rate;
+        return 0;
+}
+
+static struct clk_ops exynos4_vpll_ops = {
+        .get_rate = exynos4_vpll_get_rate,
+        .set_rate = exynos4_vpll_set_rate,
+};
+
 void __init_or_cpufreq exynos4_setup_clocks(void)
 {
         struct clk *xtal_clk;
-        unsigned long apll;
-        unsigned long mpll;
-        unsigned long epll;
-        unsigned long vpll;
+        unsigned long apll = 0;
+        unsigned long mpll = 0;
+        unsigned long epll = 0;
+        unsigned long vpll = 0;
         unsigned long vpllsrc;
         unsigned long xtal;
         unsigned long armclk;
@@ -1153,18 +1388,34 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
 
         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
 
-        apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
-        mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
-        epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
-                                __raw_readl(S5P_EPLL_CON1), pll_4600);
-
-        vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
-        vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
-                                __raw_readl(S5P_VPLL_CON1), pll_4650);
+        if (soc_is_exynos4210()) {
+                apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0),
+                                        pll_4508);
+                mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0),
+                                        pll_4508);
+                epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
+                                        __raw_readl(S5P_EPLL_CON1), pll_4600);
+
+                vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
+                vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
+                                        __raw_readl(S5P_VPLL_CON1), pll_4650c);
+        } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
+                apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
+                mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
+                epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
+                                        __raw_readl(S5P_EPLL_CON1));
+
+                vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
+                vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
+                                        __raw_readl(S5P_VPLL_CON1));
+        } else {
+                /* nothing */
+        }
 
         clk_fout_apll.ops = &exynos4_fout_apll_ops;
         clk_fout_mpll.rate = mpll;
         clk_fout_epll.rate = epll;
+        clk_fout_vpll.ops = &exynos4_vpll_ops;
         clk_fout_vpll.rate = vpll;
 
         printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
@@ -1192,7 +1443,32 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
 }
 
 static struct clk *clks[] __initdata = {
-        /* Nothing here yet */
+        &clk_sclk_hdmi27m,
+        &clk_sclk_hdmiphy,
+        &clk_sclk_usbphy0,
+        &clk_sclk_usbphy1,
+};
+
+#ifdef CONFIG_PM_SLEEP
+static int exynos4_clock_suspend(void)
+{
+        s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
+        return 0;
+}
+
+static void exynos4_clock_resume(void)
+{
+        s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
+}
+
+#else
+#define exynos4_clock_suspend NULL
+#define exynos4_clock_resume NULL
+#endif
+
+struct syscore_ops exynos4_clock_syscore_ops = {
+        .suspend        = exynos4_clock_suspend,
+        .resume         = exynos4_clock_resume,
 };
 
 void __init exynos4_register_clocks(void)
@@ -1204,11 +1480,17 @@ void __init exynos4_register_clocks(void)
         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
                 s3c_register_clksrc(sysclks[ptr], 1);
 
+        for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
+                s3c_register_clksrc(sclk_tv[ptr], 1);
+
         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 
         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 
+        register_syscore_ops(&exynos4_clock_syscore_ops);
+        s3c24xx_register_clock(&dummy_apb_pclk);
+
         s3c_pwmclk_init();
 }
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 746d6fc6d397..5b1765b37f75 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -28,10 +28,13 @@
 #include <plat/fimc-core.h>
 #include <plat/iic-core.h>
 #include <plat/reset.h>
+#include <plat/tv-core.h>
 
 #include <mach/regs-irq.h>
 #include <mach/regs-pmu.h>
 
+unsigned int gic_bank_offset __read_mostly;
+
 extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
                          unsigned int irq_start);
 extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
@@ -44,11 +47,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = (unsigned long)S5P_VA_SYSRAM,
-                .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
                 .virtual        = (unsigned long)S5P_VA_CMU,
                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
                 .length         = SZ_128K,
@@ -121,6 +119,24 @@ static struct map_desc exynos4_iodesc[] __initdata = {
         },
 };
 
+static struct map_desc exynos4_iodesc0[] __initdata = {
+        {
+                .virtual        = (unsigned long)S5P_VA_SYSRAM,
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        },
+};
+
+static struct map_desc exynos4_iodesc1[] __initdata = {
+        {
+                .virtual        = (unsigned long)S5P_VA_SYSRAM,
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        },
+};
+
 static void exynos4_idle(void)
 {
         if (!need_resched())
@@ -143,6 +159,11 @@ void __init exynos4_map_io(void)
 {
         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 
+        if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
+                iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
+        else
+                iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
+
         /* initialize device information early */
         exynos4_default_sdhci0();
         exynos4_default_sdhci1();
@@ -162,6 +183,7 @@ void __init exynos4_map_io(void)
         s3c_i2c2_setname("s3c2440-i2c");
 
         s5p_fb_setname(0, "exynos4-fb");
+        s5p_hdmi_setname("exynos4-hdmi");
 }
 
 void __init exynos4_init_clocks(int xtal)
@@ -170,24 +192,37 @@ void __init exynos4_init_clocks(int xtal)
 
         s3c24xx_register_baseclocks(xtal);
         s5p_register_clocks(xtal);
+
+        if (soc_is_exynos4210())
+                exynos4210_register_clocks();
+        else if (soc_is_exynos4212() || soc_is_exynos4412())
+                exynos4212_register_clocks();
+
         exynos4_register_clocks();
         exynos4_setup_clocks();
 }
 
-static void exynos4_gic_irq_eoi(struct irq_data *d)
+static void exynos4_gic_irq_fix_base(struct irq_data *d)
 {
         struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
 
         gic_data->cpu_base = S5P_VA_GIC_CPU +
-                            (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
+                            (gic_bank_offset * smp_processor_id());
+
+        gic_data->dist_base = S5P_VA_GIC_DIST +
+                            (gic_bank_offset * smp_processor_id());
 }
 
 void __init exynos4_init_irq(void)
 {
         int irq;
 
-        gic_init(0, IRQ_SPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
-        gic_arch_extn.irq_eoi = exynos4_gic_irq_eoi;
+        gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
+
+        gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+        gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
+        gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
+        gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;
 
         for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
 
@@ -223,7 +258,11 @@ static int __init exynos4_l2x0_cache_init(void)
 {
         /* TAG, Data Latency Control: 2cycle */
         __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
-        __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
+
+        if (soc_is_exynos4210())
+                __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
+        else if (soc_is_exynos4212() || soc_is_exynos4412())
+                __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 
         /* L2X0 Prefetch Control */
         __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
diff --git a/arch/arm/mach-exynos4/dma.c b/arch/arm/mach-exynos4/dma.c
index 564bb530f332..9667c61e64fb 100644
--- a/arch/arm/mach-exynos4/dma.c
+++ b/arch/arm/mach-exynos4/dma.c
@@ -21,151 +21,229 @@
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
-#include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/pl330.h>
 
+#include <asm/irq.h>
 #include <plat/devs.h>
 #include <plat/irqs.h>
 
 #include <mach/map.h>
 #include <mach/irqs.h>
-
-#include <plat/s3c-pl330-pdata.h>
+#include <mach/dma.h>
 
 static u64 dma_dmamask = DMA_BIT_MASK(32);
 
-static struct resource exynos4_pdma0_resource[] = {
-        [0] = {
-                .start  = EXYNOS4_PA_PDMA0,
-                .end    = EXYNOS4_PA_PDMA0 + SZ_4K,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_PDMA0,
-                .end    = IRQ_PDMA0,
-                .flags  = IORESOURCE_IRQ,
+struct dma_pl330_peri pdma0_peri[28] = {
+        {
+                .peri_id = (u8)DMACH_PCM0_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_PCM0_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_PCM2_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_PCM2_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_MSM_REQ0,
+        }, {
+                .peri_id = (u8)DMACH_MSM_REQ2,
+        }, {
+                .peri_id = (u8)DMACH_SPI0_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_SPI0_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_SPI2_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_SPI2_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_I2S0S_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_I2S0_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_I2S0_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_UART0_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART0_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_UART2_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART2_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_UART4_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART4_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_SLIMBUS0_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_SLIMBUS0_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_SLIMBUS2_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_SLIMBUS2_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_SLIMBUS4_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_SLIMBUS4_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_AC97_MICIN,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_AC97_PCMIN,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_AC97_PCMOUT,
+                .rqtype = MEMTODEV,
         },
 };
 
-static struct s3c_pl330_platdata exynos4_pdma0_pdata = {
-        .peri = {
-                [0] = DMACH_PCM0_RX,
-                [1] = DMACH_PCM0_TX,
-                [2] = DMACH_PCM2_RX,
-                [3] = DMACH_PCM2_TX,
-                [4] = DMACH_MSM_REQ0,
-                [5] = DMACH_MSM_REQ2,
-                [6] = DMACH_SPI0_RX,
-                [7] = DMACH_SPI0_TX,
-                [8] = DMACH_SPI2_RX,
-                [9] = DMACH_SPI2_TX,
-                [10] = DMACH_I2S0S_TX,
-                [11] = DMACH_I2S0_RX,
-                [12] = DMACH_I2S0_TX,
-                [13] = DMACH_I2S2_RX,
-                [14] = DMACH_I2S2_TX,
-                [15] = DMACH_UART0_RX,
-                [16] = DMACH_UART0_TX,
-                [17] = DMACH_UART2_RX,
-                [18] = DMACH_UART2_TX,
-                [19] = DMACH_UART4_RX,
-                [20] = DMACH_UART4_TX,
-                [21] = DMACH_SLIMBUS0_RX,
-                [22] = DMACH_SLIMBUS0_TX,
-                [23] = DMACH_SLIMBUS2_RX,
-                [24] = DMACH_SLIMBUS2_TX,
-                [25] = DMACH_SLIMBUS4_RX,
-                [26] = DMACH_SLIMBUS4_TX,
-                [27] = DMACH_AC97_MICIN,
-                [28] = DMACH_AC97_PCMIN,
-                [29] = DMACH_AC97_PCMOUT,
-                [30] = DMACH_MAX,
-                [31] = DMACH_MAX,
-        },
+struct dma_pl330_platdata exynos4_pdma0_pdata = {
+        .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
+        .peri = pdma0_peri,
 };
 
-static struct platform_device exynos4_device_pdma0 = {
-        .name           = "s3c-pl330",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(exynos4_pdma0_resource),
-        .resource       = exynos4_pdma0_resource,
-        .dev            = {
+struct amba_device exynos4_device_pdma0 = {
+        .dev = {
+                .init_name = "dma-pl330.0",
                 .dma_mask = &dma_dmamask,
                 .coherent_dma_mask = DMA_BIT_MASK(32),
                 .platform_data = &exynos4_pdma0_pdata,
         },
+        .res = {
+                .start = EXYNOS4_PA_PDMA0,
+                .end = EXYNOS4_PA_PDMA0 + SZ_4K,
+                .flags = IORESOURCE_MEM,
+        },
+        .irq = {IRQ_PDMA0, NO_IRQ},
+        .periphid = 0x00041330,
 };
 
-static struct resource exynos4_pdma1_resource[] = {
-        [0] = {
-                .start  = EXYNOS4_PA_PDMA1,
-                .end    = EXYNOS4_PA_PDMA1 + SZ_4K,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_PDMA1,
-                .end    = IRQ_PDMA1,
-                .flags  = IORESOURCE_IRQ,
+struct dma_pl330_peri pdma1_peri[25] = {
+        {
+                .peri_id = (u8)DMACH_PCM0_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_PCM0_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_PCM1_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_PCM1_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_MSM_REQ1,
+        }, {
+                .peri_id = (u8)DMACH_MSM_REQ3,
+        }, {
+                .peri_id = (u8)DMACH_SPI1_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_SPI1_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_I2S0S_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_I2S0_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_I2S0_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_I2S1_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_I2S1_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_UART0_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART0_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_UART1_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART1_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_UART3_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART3_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_SLIMBUS1_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_SLIMBUS1_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_SLIMBUS3_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_SLIMBUS3_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_SLIMBUS5_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_SLIMBUS5_TX,
+                .rqtype = MEMTODEV,
         },
 };
 
-static struct s3c_pl330_platdata exynos4_pdma1_pdata = {
-        .peri = {
-                [0] = DMACH_PCM0_RX,
-                [1] = DMACH_PCM0_TX,
-                [2] = DMACH_PCM1_RX,
-                [3] = DMACH_PCM1_TX,
-                [4] = DMACH_MSM_REQ1,
-                [5] = DMACH_MSM_REQ3,
-                [6] = DMACH_SPI1_RX,
-                [7] = DMACH_SPI1_TX,
-                [8] = DMACH_I2S0S_TX,
-                [9] = DMACH_I2S0_RX,
-                [10] = DMACH_I2S0_TX,
-                [11] = DMACH_I2S1_RX,
-                [12] = DMACH_I2S1_TX,
-                [13] = DMACH_UART0_RX,
-                [14] = DMACH_UART0_TX,
-                [15] = DMACH_UART1_RX,
-                [16] = DMACH_UART1_TX,
-                [17] = DMACH_UART3_RX,
-                [18] = DMACH_UART3_TX,
-                [19] = DMACH_SLIMBUS1_RX,
-                [20] = DMACH_SLIMBUS1_TX,
-                [21] = DMACH_SLIMBUS3_RX,
-                [22] = DMACH_SLIMBUS3_TX,
-                [23] = DMACH_SLIMBUS5_RX,
-                [24] = DMACH_SLIMBUS5_TX,
-                [25] = DMACH_SLIMBUS0AUX_RX,
-                [26] = DMACH_SLIMBUS0AUX_TX,
-                [27] = DMACH_SPDIF,
-                [28] = DMACH_MAX,
-                [29] = DMACH_MAX,
-                [30] = DMACH_MAX,
-                [31] = DMACH_MAX,
-        },
+struct dma_pl330_platdata exynos4_pdma1_pdata = {
+        .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
+        .peri = pdma1_peri,
 };
 
-static struct platform_device exynos4_device_pdma1 = {
-        .name           = "s3c-pl330",
-        .id             = 1,
-        .num_resources  = ARRAY_SIZE(exynos4_pdma1_resource),
-        .resource       = exynos4_pdma1_resource,
-        .dev            = {
+struct amba_device exynos4_device_pdma1 = {
+        .dev = {
+                .init_name = "dma-pl330.1",
                 .dma_mask = &dma_dmamask,
                 .coherent_dma_mask = DMA_BIT_MASK(32),
                 .platform_data = &exynos4_pdma1_pdata,
         },
-};
-
-static struct platform_device *exynos4_dmacs[] __initdata = {
-        &exynos4_device_pdma0,
-        &exynos4_device_pdma1,
+        .res = {
+                .start = EXYNOS4_PA_PDMA1,
+                .end = EXYNOS4_PA_PDMA1 + SZ_4K,
+                .flags = IORESOURCE_MEM,
+        },
+        .irq = {IRQ_PDMA1, NO_IRQ},
+        .periphid = 0x00041330,
 };
 
 static int __init exynos4_dma_init(void)
 {
-        platform_add_devices(exynos4_dmacs, ARRAY_SIZE(exynos4_dmacs));
+        amba_device_register(&exynos4_device_pdma0, &iomem_resource);
+        amba_device_register(&exynos4_device_pdma1, &iomem_resource);
 
         return 0;
 }
diff --git a/arch/arm/mach-exynos4/include/mach/clkdev.h b/arch/arm/mach-exynos4/include/mach/clkdev.h
deleted file mode 100644
index 7dffa83d23ff..000000000000
--- a/arch/arm/mach-exynos4/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __MACH_CLKDEV_H__
-#define __MACH_CLKDEV_H__
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do {} while (0)
-
-#endif
diff --git a/arch/arm/mach-exynos4/include/mach/dma.h b/arch/arm/mach-exynos4/include/mach/dma.h
index 81209eb1409b..201842a3769e 100644
--- a/arch/arm/mach-exynos4/include/mach/dma.h
+++ b/arch/arm/mach-exynos4/include/mach/dma.h
@@ -20,7 +20,7 @@
 #ifndef __MACH_DMA_H
 #define __MACH_DMA_H
 
-/* This platform uses the common S3C DMA API driver for PL330 */
-#include <plat/s3c-dma-pl330.h>
+/* This platform uses the common DMA API driver for PL330 */
+#include <plat/dma-pl330.h>
 
 #endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-exynos4/include/mach/entry-macro.S b/arch/arm/mach-exynos4/include/mach/entry-macro.S
index d7a1e281ce7a..4c9adbd87eac 100644
--- a/arch/arm/mach-exynos4/include/mach/entry-macro.S
+++ b/arch/arm/mach-exynos4/include/mach/entry-macro.S
@@ -17,12 +17,25 @@
                 .endm
 
                 .macro  get_irqnr_preamble, base, tmp
-                ldr     \base, =gic_cpu_base_addr
+                mov     \tmp, #0
+
+                mrc     p15, 0, \base, c0, c0, 5
+                and     \base, \base, #3
+                cmp     \base, #0
+                beq     1f
+
+                ldr     \tmp, =gic_bank_offset
+                ldr     \tmp, [\tmp]
+                cmp     \base, #1
+                beq     1f
+
+                cmp     \base, #2
+                addeq   \tmp, \tmp, \tmp
+                addne   \tmp, \tmp, \tmp, LSL #1
+
+1:              ldr     \base, =gic_cpu_base_addr
                 ldr     \base, [\base]
-                mrc     p15, 0, \tmp, c0, c0, 5
-                and     \tmp, \tmp, #3
-                cmp     \tmp, #1
-                addeq   \base, \base, #EXYNOS4_GIC_BANK_OFFSET
+                add     \base, \base, \tmp
                 .endm
 
                 .macro  arch_ret_to_user, tmp1, tmp2
@@ -80,4 +93,10 @@
                 /* As above, this assumes that irqstat and base are preserved.. */
 
                 .macro test_for_ltirq, irqnr, irqstat, base, tmp
+                bic     \irqnr, \irqstat, #0x1c00
+                mov     \tmp, #0
+                cmp     \irqnr, #28
+                moveq   \tmp, #1
+                streq   \irqstat, [\base, #GIC_CPU_EOI]
+                cmp     \tmp, #0
                 .endm
diff --git a/arch/arm/mach-exynos4/include/mach/exynos4-clock.h b/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
new file mode 100644
index 000000000000..a07fcbf55251
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
@@ -0,0 +1,43 @@
+/*
+ * linux/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Header file for exynos4 clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H __FILE__
+
+#include <linux/clk.h>
+
+extern struct clk clk_sclk_hdmi27m;
+extern struct clk clk_sclk_usbphy0;
+extern struct clk clk_sclk_usbphy1;
+extern struct clk clk_sclk_hdmiphy;
+
+extern struct clksrc_clk clk_sclk_apll;
+extern struct clksrc_clk clk_mout_mpll;
+extern struct clksrc_clk clk_aclk_133;
+extern struct clksrc_clk clk_mout_epll;
+extern struct clksrc_clk clk_sclk_vpll;
+
+extern struct clk *clkset_corebus_list[];
+extern struct clksrc_sources clkset_mout_corebus;
+
+extern struct clk *clkset_aclk_top_list[];
+extern struct clksrc_sources clkset_aclk;
+
+extern struct clk *clkset_group_list[];
+extern struct clksrc_sources clkset_group;
+
+extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos4/include/mach/i2c-hdmiphy.h b/arch/arm/mach-exynos4/include/mach/i2c-hdmiphy.h
new file mode 100644
index 000000000000..9dbe3179ad59
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/i2c-hdmiphy.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co., Ltd.
+ *
+ * S5P series i2c hdmiphy helper definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef PLAT_S5P_I2C_HDMIPHY_H_
+#define PLAT_S5P_I2C_HDMIPHY_H_
+
+#define S5P_I2C_HDMIPHY_BUS_NUM         (8)
+
+#endif
diff --git a/arch/arm/mach-exynos4/include/mach/irqs.h b/arch/arm/mach-exynos4/include/mach/irqs.h
index f8952f8f3757..dfd4b7eecb90 100644
--- a/arch/arm/mach-exynos4/include/mach/irqs.h
+++ b/arch/arm/mach-exynos4/include/mach/irqs.h
@@ -19,6 +19,8 @@
 
 #define IRQ_PPI(x)              S5P_IRQ(x+16)
 
+#define IRQ_MCT_LOCALTIMER      IRQ_PPI(12)
+
 /* SPI: Shared Peripheral Interrupt */
 
 #define IRQ_SPI(x)              S5P_IRQ(x+32)
@@ -93,7 +95,11 @@
 #define IRQ_2D                  IRQ_SPI(89)
 #define IRQ_PCIE                IRQ_SPI(90)
 
+#define IRQ_MIXER               IRQ_SPI(91)
+#define IRQ_HDMI                IRQ_SPI(92)
+#define IRQ_IIC_HDMIPHY         IRQ_SPI(93)
 #define IRQ_MFC                 IRQ_SPI(94)
+#define IRQ_SDO                 IRQ_SPI(95)
 
 #define IRQ_AUDIO_SS            IRQ_SPI(96)
 #define IRQ_I2S0                IRQ_SPI(97)
diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h
index d32296dc65e2..918a979181af 100644
--- a/arch/arm/mach-exynos4/include/mach/map.h
+++ b/arch/arm/mach-exynos4/include/mach/map.h
@@ -23,7 +23,8 @@
 
 #include <plat/map-s5p.h>
 
-#define EXYNOS4_PA_SYSRAM               0x02020000
+#define EXYNOS4_PA_SYSRAM0              0x02025000
+#define EXYNOS4_PA_SYSRAM1              0x02020000
 
 #define EXYNOS4_PA_FIMC0                0x11800000
 #define EXYNOS4_PA_FIMC1                0x11810000
@@ -61,7 +62,6 @@
 
 #define EXYNOS4_PA_GIC_CPU              0x10480000
 #define EXYNOS4_PA_GIC_DIST             0x10490000
-#define EXYNOS4_GIC_BANK_OFFSET         0x8000
 
 #define EXYNOS4_PA_COREPERI             0x10500000
 #define EXYNOS4_PA_TWD                  0x10500600
@@ -112,6 +112,12 @@
 
 #define EXYNOS4_PA_UART                 0x13800000
 
+#define EXYNOS4_PA_VP                   0x12C00000
+#define EXYNOS4_PA_MIXER                0x12C10000
+#define EXYNOS4_PA_SDO                  0x12C20000
+#define EXYNOS4_PA_HDMI                 0x12D00000
+#define EXYNOS4_PA_IIC_HDMIPHY          0x138E0000
+
 #define EXYNOS4_PA_IIC(x)               (0x13860000 + ((x) * 0x10000))
 
 #define EXYNOS4_PA_ADC                  0x13910000
@@ -161,6 +167,12 @@
 #define S5P_PA_TIMER                    EXYNOS4_PA_TIMER
 #define S5P_PA_EHCI                     EXYNOS4_PA_EHCI
 
+#define S5P_PA_SDO                      EXYNOS4_PA_SDO
+#define S5P_PA_VP                       EXYNOS4_PA_VP
+#define S5P_PA_MIXER                    EXYNOS4_PA_MIXER
+#define S5P_PA_HDMI                     EXYNOS4_PA_HDMI
+#define S5P_PA_IIC_HDMIPHY              EXYNOS4_PA_IIC_HDMIPHY
+
 #define SAMSUNG_PA_KEYPAD               EXYNOS4_PA_KEYPAD
 
 /* UART */
diff --git a/arch/arm/mach-exynos4/include/mach/pm-core.h b/arch/arm/mach-exynos4/include/mach/pm-core.h
index 1df3b81f96e8..9d8da51e35ca 100644
--- a/arch/arm/mach-exynos4/include/mach/pm-core.h
+++ b/arch/arm/mach-exynos4/include/mach/pm-core.h
@@ -14,6 +14,10 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
 */
+
+#ifndef __ASM_ARCH_PM_CORE_H
+#define __ASM_ARCH_PM_CORE_H __FILE__
+
 #include <mach/regs-pmu.h>
 
 static inline void s3c_pm_debug_init_uart(void)
@@ -53,7 +57,9 @@ static inline void s3c_pm_restored_gpios(void)
         /* nothing here yet */
 }
 
-static inline void s3c_pm_saved_gpios(void)
+static inline void samsung_pm_saved_gpios(void)
 {
         /* nothing here yet */
 }
+
+#endif /* __ASM_ARCH_PM_CORE_H */
diff --git a/arch/arm/mach-exynos4/include/mach/pmu.h b/arch/arm/mach-exynos4/include/mach/pmu.h
index a952904b010e..632dd5630138 100644
--- a/arch/arm/mach-exynos4/include/mach/pmu.h
+++ b/arch/arm/mach-exynos4/include/mach/pmu.h
@@ -13,6 +13,8 @@
 #ifndef __ASM_ARCH_PMU_H
 #define __ASM_ARCH_PMU_H __FILE__
 
+#define PMU_TABLE_END   NULL
+
 enum sys_powerdown {
         SYS_AFTR,
         SYS_LPA,
@@ -20,6 +22,11 @@ enum sys_powerdown {
         NUM_SYS_POWERDOWN,
 };
 
+struct exynos4_pmu_conf {
+        void __iomem *reg;
+        unsigned int val[NUM_SYS_POWERDOWN];
+};
+
 extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
 
 #endif /* __ASM_ARCH_PMU_H */
diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h
index d493fdb422ff..6c37ebe94829 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h
@@ -13,6 +13,7 @@
 #ifndef __ASM_ARCH_REGS_CLOCK_H
 #define __ASM_ARCH_REGS_CLOCK_H __FILE__
 
+#include <plat/cpu.h>
 #include <mach/map.h>
 
 #define S5P_CLKREG(x)                   (S5P_VA_CMU + (x))
@@ -41,12 +42,20 @@
 #define S5P_CLKSRC_G3D                  S5P_CLKREG(0x0C22C)
 #define S5P_CLKSRC_IMAGE                S5P_CLKREG(0x0C230)
 #define S5P_CLKSRC_LCD0                 S5P_CLKREG(0x0C234)
-#define S5P_CLKSRC_LCD1                 S5P_CLKREG(0x0C238)
 #define S5P_CLKSRC_MAUDIO               S5P_CLKREG(0x0C23C)
 #define S5P_CLKSRC_FSYS                 S5P_CLKREG(0x0C240)
 #define S5P_CLKSRC_PERIL0               S5P_CLKREG(0x0C250)
 #define S5P_CLKSRC_PERIL1               S5P_CLKREG(0x0C254)
 
+#define S5P_CLKSRC_MASK_TOP             S5P_CLKREG(0x0C310)
+#define S5P_CLKSRC_MASK_CAM             S5P_CLKREG(0x0C320)
+#define S5P_CLKSRC_MASK_TV              S5P_CLKREG(0x0C324)
+#define S5P_CLKSRC_MASK_LCD0            S5P_CLKREG(0x0C334)
+#define S5P_CLKSRC_MASK_MAUDIO          S5P_CLKREG(0x0C33C)
+#define S5P_CLKSRC_MASK_FSYS            S5P_CLKREG(0x0C340)
+#define S5P_CLKSRC_MASK_PERIL0          S5P_CLKREG(0x0C350)
+#define S5P_CLKSRC_MASK_PERIL1          S5P_CLKREG(0x0C354)
+
 #define S5P_CLKDIV_TOP                  S5P_CLKREG(0x0C510)
 #define S5P_CLKDIV_CAM                  S5P_CLKREG(0x0C520)
 #define S5P_CLKDIV_TV                   S5P_CLKREG(0x0C524)
@@ -54,7 +63,6 @@
 #define S5P_CLKDIV_G3D                  S5P_CLKREG(0x0C52C)
 #define S5P_CLKDIV_IMAGE                S5P_CLKREG(0x0C530)
 #define S5P_CLKDIV_LCD0                 S5P_CLKREG(0x0C534)
-#define S5P_CLKDIV_LCD1                 S5P_CLKREG(0x0C538)
 #define S5P_CLKDIV_MAUDIO               S5P_CLKREG(0x0C53C)
 #define S5P_CLKDIV_FSYS0                S5P_CLKREG(0x0C540)
 #define S5P_CLKDIV_FSYS1                S5P_CLKREG(0x0C544)
@@ -68,16 +76,6 @@
 #define S5P_CLKDIV_PERIL5               S5P_CLKREG(0x0C564)
 #define S5P_CLKDIV2_RATIO               S5P_CLKREG(0x0C580)
 
-#define S5P_CLKSRC_MASK_TOP             S5P_CLKREG(0x0C310)
-#define S5P_CLKSRC_MASK_CAM             S5P_CLKREG(0x0C320)
-#define S5P_CLKSRC_MASK_TV              S5P_CLKREG(0x0C324)
-#define S5P_CLKSRC_MASK_LCD0            S5P_CLKREG(0x0C334)
-#define S5P_CLKSRC_MASK_LCD1            S5P_CLKREG(0x0C338)
-#define S5P_CLKSRC_MASK_MAUDIO          S5P_CLKREG(0x0C33C)
-#define S5P_CLKSRC_MASK_FSYS            S5P_CLKREG(0x0C340)
-#define S5P_CLKSRC_MASK_PERIL0          S5P_CLKREG(0x0C350)
-#define S5P_CLKSRC_MASK_PERIL1          S5P_CLKREG(0x0C354)
-
 #define S5P_CLKDIV_STAT_TOP             S5P_CLKREG(0x0C610)
 
 #define S5P_CLKGATE_SCLKCAM             S5P_CLKREG(0x0C820)
@@ -85,13 +83,20 @@
 #define S5P_CLKGATE_IP_TV               S5P_CLKREG(0x0C924)
 #define S5P_CLKGATE_IP_MFC              S5P_CLKREG(0x0C928)
 #define S5P_CLKGATE_IP_G3D              S5P_CLKREG(0x0C92C)
-#define S5P_CLKGATE_IP_IMAGE            S5P_CLKREG(0x0C930)
+#define S5P_CLKGATE_IP_IMAGE            (soc_is_exynos4210() ? \
+                                        S5P_CLKREG(0x0C930) : \
+                                        S5P_CLKREG(0x04930))
+#define S5P_CLKGATE_IP_IMAGE_4210       S5P_CLKREG(0x0C930)
+#define S5P_CLKGATE_IP_IMAGE_4212       S5P_CLKREG(0x04930)
 #define S5P_CLKGATE_IP_LCD0             S5P_CLKREG(0x0C934)
-#define S5P_CLKGATE_IP_LCD1             S5P_CLKREG(0x0C938)
 #define S5P_CLKGATE_IP_FSYS             S5P_CLKREG(0x0C940)
 #define S5P_CLKGATE_IP_GPS              S5P_CLKREG(0x0C94C)
 #define S5P_CLKGATE_IP_PERIL            S5P_CLKREG(0x0C950)
-#define S5P_CLKGATE_IP_PERIR            S5P_CLKREG(0x0C960)
+#define S5P_CLKGATE_IP_PERIR            (soc_is_exynos4210() ? \
+                                        S5P_CLKREG(0x0C960) : \
+                                        S5P_CLKREG(0x08960))
+#define S5P_CLKGATE_IP_PERIR_4210       S5P_CLKREG(0x0C960)
+#define S5P_CLKGATE_IP_PERIR_4212       S5P_CLKREG(0x08960)
 #define S5P_CLKGATE_BLOCK               S5P_CLKREG(0x0C970)
 
 #define S5P_CLKSRC_MASK_DMC             S5P_CLKREG(0x10300)
@@ -102,11 +107,17 @@
 #define S5P_CLKGATE_IP_DMC              S5P_CLKREG(0x10900)
 
 #define S5P_APLL_LOCK                   S5P_CLKREG(0x14000)
-#define S5P_MPLL_LOCK                   S5P_CLKREG(0x14004)
+#define S5P_MPLL_LOCK                   (soc_is_exynos4210() ? \
+                                        S5P_CLKREG(0x14004) :  \
+                                        S5P_CLKREG(0x10008))
 #define S5P_APLL_CON0                   S5P_CLKREG(0x14100)
 #define S5P_APLL_CON1                   S5P_CLKREG(0x14104)
-#define S5P_MPLL_CON0                   S5P_CLKREG(0x14108)
-#define S5P_MPLL_CON1                   S5P_CLKREG(0x1410C)
+#define S5P_MPLL_CON0                   (soc_is_exynos4210() ? \
+                                        S5P_CLKREG(0x14108) : \
+                                        S5P_CLKREG(0x10108))
+#define S5P_MPLL_CON1                   (soc_is_exynos4210() ? \
+                                        S5P_CLKREG(0x1410C) : \
+                                        S5P_CLKREG(0x1010C))
 
 #define S5P_CLKSRC_CPU                  S5P_CLKREG(0x14200)
 #define S5P_CLKMUX_STATCPU              S5P_CLKREG(0x14400)
@@ -183,6 +194,13 @@
 #define S5P_CLKDIV_BUS_GPLR_SHIFT       (4)
 #define S5P_CLKDIV_BUS_GPLR_MASK        (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)
 
+/* Only for EXYNOS4210 */
+
+#define S5P_CLKSRC_LCD1                 S5P_CLKREG(0x0C238)
+#define S5P_CLKSRC_MASK_LCD1            S5P_CLKREG(0x0C338)
+#define S5P_CLKDIV_LCD1                 S5P_CLKREG(0x0C538)
+#define S5P_CLKGATE_IP_LCD1             S5P_CLKREG(0x0C938)
+
 /* Compatibility defines and inclusion */
 
 #include <mach/regs-pmu.h>
diff --git a/arch/arm/mach-exynos4/include/mach/regs-mct.h b/arch/arm/mach-exynos4/include/mach/regs-mct.h
index ca9c8434b023..80dd02ad6d61 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-mct.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-mct.h
@@ -31,8 +31,9 @@
 #define EXYNOS4_MCT_G_INT_ENB           EXYNOS4_MCTREG(0x248)
 #define EXYNOS4_MCT_G_WSTAT             EXYNOS4_MCTREG(0x24C)
 
-#define EXYNOS4_MCT_L0_BASE             EXYNOS4_MCTREG(0x300)
-#define EXYNOS4_MCT_L1_BASE             EXYNOS4_MCTREG(0x400)
+#define _EXYNOS4_MCT_L_BASE             EXYNOS4_MCTREG(0x300)
+#define EXYNOS4_MCT_L_BASE(x)           (_EXYNOS4_MCT_L_BASE + (0x100 * x))
+#define EXYNOS4_MCT_L_MASK              (0xffffff00)
 
 #define MCT_L_TCNTB_OFFSET              (0x00)
 #define MCT_L_ICNTB_OFFSET              (0x08)
diff --git a/arch/arm/mach-exynos4/include/mach/regs-pmu.h b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
index cdf9b47c303c..4fff8e938fec 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
@@ -25,9 +25,10 @@
 
 #define S5P_USE_STANDBY_WFI0                    (1 << 16)
 #define S5P_USE_STANDBY_WFI1                    (1 << 17)
+#define S5P_USE_STANDBYWFI_ISP_ARM              (1 << 18)
 #define S5P_USE_STANDBY_WFE0                    (1 << 24)
 #define S5P_USE_STANDBY_WFE1                    (1 << 25)
-#define S5P_USE_MASK                            ((0x3 << 16) | (0x3 << 24))
+#define S5P_USE_STANDBYWFE_ISP_ARM              (1 << 26)
 
 #define S5P_SWRESET                             S5P_PMUREG(0x0400)
 
@@ -35,15 +36,17 @@
 #define S5P_EINT_WAKEUP_MASK                    S5P_PMUREG(0x0604)
 #define S5P_WAKEUP_MASK                         S5P_PMUREG(0x0608)
 
-#define S5P_USBHOST_PHY_CONTROL                 S5P_PMUREG(0x0708)
-#define S5P_USBHOST_PHY_ENABLE                  (1 << 0)
+#define S5P_HDMI_PHY_CONTROL                    S5P_PMUREG(0x0700)
+#define S5P_HDMI_PHY_ENABLE                     (1 << 0)
+
+#define S5P_DAC_PHY_CONTROL                     S5P_PMUREG(0x070C)
+#define S5P_DAC_PHY_ENABLE                      (1 << 0)
 
 #define S5P_MIPI_DPHY_CONTROL(n)                S5P_PMUREG(0x0710 + (n) * 4)
 #define S5P_MIPI_DPHY_ENABLE                    (1 << 0)
 #define S5P_MIPI_DPHY_SRESETN                   (1 << 1)
 #define S5P_MIPI_DPHY_MRESETN                   (1 << 2)
 
-#define S5P_PMU_SATA_PHY_CONTROL                S5P_PMUREG(0x0720)
 #define S5P_INFORM0                             S5P_PMUREG(0x0800)
 #define S5P_INFORM1                             S5P_PMUREG(0x0804)
 #define S5P_INFORM2                             S5P_PMUREG(0x0808)
@@ -76,7 +79,6 @@
 #define S5P_CMU_CLKSTOP_MFC_LOWPWR              S5P_PMUREG(0x1148)
 #define S5P_CMU_CLKSTOP_G3D_LOWPWR              S5P_PMUREG(0x114C)
 #define S5P_CMU_CLKSTOP_LCD0_LOWPWR             S5P_PMUREG(0x1150)
-#define S5P_CMU_CLKSTOP_LCD1_LOWPWR             S5P_PMUREG(0x1154)
 #define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR           S5P_PMUREG(0x1158)
 #define S5P_CMU_CLKSTOP_GPS_LOWPWR              S5P_PMUREG(0x115C)
 #define S5P_CMU_RESET_CAM_LOWPWR                S5P_PMUREG(0x1160)
@@ -84,7 +86,6 @@
 #define S5P_CMU_RESET_MFC_LOWPWR                S5P_PMUREG(0x1168)
 #define S5P_CMU_RESET_G3D_LOWPWR                S5P_PMUREG(0x116C)
 #define S5P_CMU_RESET_LCD0_LOWPWR               S5P_PMUREG(0x1170)
-#define S5P_CMU_RESET_LCD1_LOWPWR               S5P_PMUREG(0x1174)
 #define S5P_CMU_RESET_MAUDIO_LOWPWR             S5P_PMUREG(0x1178)
 #define S5P_CMU_RESET_GPS_LOWPWR                S5P_PMUREG(0x117C)
 #define S5P_TOP_BUS_LOWPWR                      S5P_PMUREG(0x1180)
@@ -92,14 +93,11 @@
 #define S5P_TOP_PWR_LOWPWR                      S5P_PMUREG(0x1188)
 #define S5P_LOGIC_RESET_LOWPWR                  S5P_PMUREG(0x11A0)
 #define S5P_ONENAND_MEM_LOWPWR                  S5P_PMUREG(0x11C0)
-#define S5P_MODIMIF_MEM_LOWPWR                  S5P_PMUREG(0x11C4)
 #define S5P_G2D_ACP_MEM_LOWPWR                  S5P_PMUREG(0x11C8)
 #define S5P_USBOTG_MEM_LOWPWR                   S5P_PMUREG(0x11CC)
 #define S5P_HSMMC_MEM_LOWPWR                    S5P_PMUREG(0x11D0)
 #define S5P_CSSYS_MEM_LOWPWR                    S5P_PMUREG(0x11D4)
 #define S5P_SECSS_MEM_LOWPWR                    S5P_PMUREG(0x11D8)
-#define S5P_PCIE_MEM_LOWPWR                     S5P_PMUREG(0x11E0)
-#define S5P_SATA_MEM_LOWPWR                     S5P_PMUREG(0x11E4)
 #define S5P_PAD_RETENTION_DRAM_LOWPWR           S5P_PMUREG(0x1200)
 #define S5P_PAD_RETENTION_MAUDIO_LOWPWR         S5P_PMUREG(0x1204)
 #define S5P_PAD_RETENTION_GPIO_LOWPWR           S5P_PMUREG(0x1220)
@@ -120,7 +118,6 @@
 #define S5P_MFC_LOWPWR                          S5P_PMUREG(0x1388)
 #define S5P_G3D_LOWPWR                          S5P_PMUREG(0x138C)
 #define S5P_LCD0_LOWPWR                         S5P_PMUREG(0x1390)
-#define S5P_LCD1_LOWPWR                         S5P_PMUREG(0x1394)
 #define S5P_MAUDIO_LOWPWR                       S5P_PMUREG(0x1398)
 #define S5P_GPS_LOWPWR                          S5P_PMUREG(0x139C)
 #define S5P_GPS_ALIVE_LOWPWR                    S5P_PMUREG(0x13A0)
@@ -156,7 +153,6 @@
 #define S5P_PMU_MFC_CONF                        S5P_PMUREG(0x3C40)
 #define S5P_PMU_G3D_CONF                        S5P_PMUREG(0x3C60)
 #define S5P_PMU_LCD0_CONF                       S5P_PMUREG(0x3C80)
-#define S5P_PMU_LCD1_CONF                       S5P_PMUREG(0x3CA0)
 #define S5P_PMU_GPS_CONF                        S5P_PMUREG(0x3CE0)
 
 #define S5P_PMU_SATA_PHY_CONTROL_EN             0x1
@@ -165,4 +161,60 @@
 
 #define S5P_CHECK_SLEEP                         0x00000BAD
 
+/* Only for EXYNOS4210 */
+#define S5P_USBHOST_PHY_CONTROL         S5P_PMUREG(0x0708)
+#define S5P_USBHOST_PHY_ENABLE          (1 << 0)
+
+#define S5P_PMU_SATA_PHY_CONTROL        S5P_PMUREG(0x0720)
+
+#define S5P_CMU_CLKSTOP_LCD1_LOWPWR     S5P_PMUREG(0x1154)
+#define S5P_CMU_RESET_LCD1_LOWPWR       S5P_PMUREG(0x1174)
+#define S5P_MODIMIF_MEM_LOWPWR          S5P_PMUREG(0x11C4)
+#define S5P_PCIE_MEM_LOWPWR             S5P_PMUREG(0x11E0)
+#define S5P_SATA_MEM_LOWPWR             S5P_PMUREG(0x11E4)
+#define S5P_LCD1_LOWPWR                 S5P_PMUREG(0x1394)
+
+#define S5P_PMU_LCD1_CONF               S5P_PMUREG(0x3CA0)
+
+/* Only for EXYNOS4212 */
+#define S5P_ISP_ARM_LOWPWR                      S5P_PMUREG(0x1050)
+#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR        S5P_PMUREG(0x1054)
+#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR      S5P_PMUREG(0x1058)
+#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR         S5P_PMUREG(0x1110)
+#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR         S5P_PMUREG(0x1114)
+#define S5P_CMU_RESET_COREBLK_LOWPWR            S5P_PMUREG(0x111C)
+#define S5P_MPLLUSER_SYSCLK_LOWPWR              S5P_PMUREG(0x1130)
+#define S5P_CMU_CLKSTOP_ISP_LOWPWR              S5P_PMUREG(0x1154)
+#define S5P_CMU_RESET_ISP_LOWPWR                S5P_PMUREG(0x1174)
+#define S5P_TOP_BUS_COREBLK_LOWPWR              S5P_PMUREG(0x1190)
+#define S5P_TOP_RETENTION_COREBLK_LOWPWR        S5P_PMUREG(0x1194)
+#define S5P_TOP_PWR_COREBLK_LOWPWR              S5P_PMUREG(0x1198)
+#define S5P_OSCCLK_GATE_LOWPWR                  S5P_PMUREG(0x11A4)
+#define S5P_LOGIC_RESET_COREBLK_LOWPWR          S5P_PMUREG(0x11B0)
+#define S5P_OSCCLK_GATE_COREBLK_LOWPWR          S5P_PMUREG(0x11B4)
+#define S5P_HSI_MEM_LOWPWR                      S5P_PMUREG(0x11C4)
+#define S5P_ROTATOR_MEM_LOWPWR                  S5P_PMUREG(0x11DC)
+#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR   S5P_PMUREG(0x123C)
+#define S5P_PAD_ISOLATION_COREBLK_LOWPWR        S5P_PMUREG(0x1250)
+#define S5P_GPIO_MODE_COREBLK_LOWPWR            S5P_PMUREG(0x1320)
+#define S5P_TOP_ASB_RESET_LOWPWR                S5P_PMUREG(0x1344)
+#define S5P_TOP_ASB_ISOLATION_LOWPWR            S5P_PMUREG(0x1348)
+#define S5P_ISP_LOWPWR                          S5P_PMUREG(0x1394)
+#define S5P_DRAM_FREQ_DOWN_LOWPWR               S5P_PMUREG(0x13B0)
+#define S5P_DDRPHY_DLLOFF_LOWPWR                S5P_PMUREG(0x13B4)
+#define S5P_CMU_SYSCLK_ISP_LOWPWR               S5P_PMUREG(0x13B8)
+#define S5P_CMU_SYSCLK_GPS_LOWPWR               S5P_PMUREG(0x13BC)
+#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR           S5P_PMUREG(0x13C0)
+
+#define S5P_ARM_L2_0_OPTION                     S5P_PMUREG(0x2608)
+#define S5P_ARM_L2_1_OPTION                     S5P_PMUREG(0x2628)
+#define S5P_ONENAND_MEM_OPTION                  S5P_PMUREG(0x2E08)
+#define S5P_HSI_MEM_OPTION                      S5P_PMUREG(0x2E28)
+#define S5P_G2D_ACP_MEM_OPTION                  S5P_PMUREG(0x2E48)
+#define S5P_USBOTG_MEM_OPTION                   S5P_PMUREG(0x2E68)
+#define S5P_HSMMC_MEM_OPTION                    S5P_PMUREG(0x2E88)
+#define S5P_CSSYS_MEM_OPTION                    S5P_PMUREG(0x2EA8)
+#define S5P_SECSS_MEM_OPTION                    S5P_PMUREG(0x2EC8)
+#define S5P_ROTATOR_MEM_OPTION                  S5P_PMUREG(0x2F48)
+
 #endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-exynos4/mach-nuri.c b/arch/arm/mach-exynos4/mach-nuri.c
index 43be71b799cb..bbd13f454151 100644
--- a/arch/arm/mach-exynos4/mach-nuri.c
+++ b/arch/arm/mach-exynos4/mach-nuri.c
@@ -32,10 +32,12 @@
 #include <asm/mach-types.h>
 
 #include <plat/adc.h>
+#include <plat/regs-fb-v4.h>
 #include <plat/regs-serial.h>
 #include <plat/exynos4.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
+#include <plat/fb.h>
 #include <plat/sdhci.h>
 #include <plat/ehci.h>
 #include <plat/clock.h>
@@ -199,6 +201,33 @@ static struct platform_device nuri_gpio_keys = {
         },
 };
 
+/* Frame Buffer */
+static struct s3c_fb_pd_win nuri_fb_win0 = {
+        .win_mode = {
+                .left_margin    = 64,
+                .right_margin   = 16,
+                .upper_margin   = 64,
+                .lower_margin   = 1,
+                .hsync_len      = 48,
+                .vsync_len      = 3,
+                .xres           = 1280,
+                .yres           = 800,
+                .refresh        = 60,
+        },
+        .max_bpp        = 24,
+        .default_bpp    = 16,
+        .virtual_x      = 1280,
+        .virtual_y      = 800,
+};
+
+static struct s3c_fb_platdata nuri_fb_pdata __initdata = {
+        .win[0]         = &nuri_fb_win0,
+        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
+                          VIDCON0_CLKSEL_LCD,
+        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+        .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
+};
+
 static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
 {
         int gpio = EXYNOS4_GPE1(5);
@@ -1092,6 +1121,7 @@ static struct platform_device *nuri_devices[] __initdata = {
         /* Samsung Platform Devices */
         &s3c_device_i2c5, /* PMIC should initialize first */
         &emmc_fixed_voltage,
+        &s5p_device_fimd0,
         &s3c_device_hsmmc0,
         &s3c_device_hsmmc2,
         &s3c_device_hsmmc3,
@@ -1106,6 +1136,7 @@ static struct platform_device *nuri_devices[] __initdata = {
         &s5p_device_mfc_l,
         &s5p_device_mfc_r,
         &exynos4_device_pd[PD_MFC],
+        &exynos4_device_pd[PD_LCD0],
 
         /* NURI Devices */
         &nuri_gpio_keys,
@@ -1142,12 +1173,15 @@ static void __init nuri_machine_init(void)
         i2c9_devs[I2C9_MAX17042].irq = gpio_to_irq(EXYNOS4_GPX2(3));
         i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs));
 
+        s5p_fimd0_set_platdata(&nuri_fb_pdata);
+
         nuri_ehci_init();
         clk_xusbxti.rate = 24000000;
 
         /* Last */
         platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
         s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
+        s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
 }
 
 MACHINE_START(NURI, "NURI")
diff --git a/arch/arm/mach-exynos4/mach-origen.c b/arch/arm/mach-exynos4/mach-origen.c
new file mode 100644
index 000000000000..71db8480bb5a
--- /dev/null
+++ b/arch/arm/mach-exynos4/mach-origen.c
@@ -0,0 +1,679 @@
+/* linux/arch/arm/mach-exynos4/mach-origen.c
+ *
+ * Copyright (c) 2011 Insignal Co., Ltd.
+ *              http://www.insignal.co.kr/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/serial_core.h>
+#include <linux/gpio.h>
+#include <linux/mmc/host.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/input.h>
+#include <linux/pwm_backlight.h>
+#include <linux/gpio_keys.h>
+#include <linux/i2c.h>
+#include <linux/regulator/machine.h>
+#include <linux/mfd/max8997.h>
+#include <linux/lcd.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <video/platform_lcd.h>
+
+#include <plat/regs-serial.h>
+#include <plat/regs-fb-v4.h>
+#include <plat/exynos4.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/sdhci.h>
+#include <plat/iic.h>
+#include <plat/ehci.h>
+#include <plat/clock.h>
+#include <plat/gpio-cfg.h>
+#include <plat/backlight.h>
+#include <plat/pd.h>
+#include <plat/fb.h>
+
+#include <mach/map.h>
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define ORIGEN_UCON_DEFAULT     (S3C2410_UCON_TXILEVEL |        \
+                                 S3C2410_UCON_RXILEVEL |        \
+                                 S3C2410_UCON_TXIRQMODE |       \
+                                 S3C2410_UCON_RXIRQMODE |       \
+                                 S3C2410_UCON_RXFIFO_TOI |      \
+                                 S3C2443_UCON_RXERR_IRQEN)
+
+#define ORIGEN_ULCON_DEFAULT    S3C2410_LCON_CS8
+
+#define ORIGEN_UFCON_DEFAULT    (S3C2410_UFCON_FIFOMODE |       \
+                                 S5PV210_UFCON_TXTRIG4 |        \
+                                 S5PV210_UFCON_RXTRIG4)
+
+static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = {
+        [0] = {
+                .hwport         = 0,
+                .flags          = 0,
+                .ucon           = ORIGEN_UCON_DEFAULT,
+                .ulcon          = ORIGEN_ULCON_DEFAULT,
+                .ufcon          = ORIGEN_UFCON_DEFAULT,
+        },
+        [1] = {
+                .hwport         = 1,
+                .flags          = 0,
+                .ucon           = ORIGEN_UCON_DEFAULT,
+                .ulcon          = ORIGEN_ULCON_DEFAULT,
+                .ufcon          = ORIGEN_UFCON_DEFAULT,
+        },
+        [2] = {
+                .hwport         = 2,
+                .flags          = 0,
+                .ucon           = ORIGEN_UCON_DEFAULT,
+                .ulcon          = ORIGEN_ULCON_DEFAULT,
+                .ufcon          = ORIGEN_UFCON_DEFAULT,
+        },
+        [3] = {
+                .hwport         = 3,
+                .flags          = 0,
+                .ucon           = ORIGEN_UCON_DEFAULT,
+                .ulcon          = ORIGEN_ULCON_DEFAULT,
+                .ufcon          = ORIGEN_UFCON_DEFAULT,
+        },
+};
+
+static struct regulator_consumer_supply __initdata ldo3_consumer[] = {
+        REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */
+};
+static struct regulator_consumer_supply __initdata ldo6_consumer[] = {
+        REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), /* MIPI */
+};
+static struct regulator_consumer_supply __initdata ldo7_consumer[] = {
+        REGULATOR_SUPPLY("avdd", "alc5625"), /* Realtek ALC5625 */
+};
+static struct regulator_consumer_supply __initdata ldo8_consumer[] = {
+        REGULATOR_SUPPLY("vdd", "s5p-adc"), /* ADC */
+};
+static struct regulator_consumer_supply __initdata ldo9_consumer[] = {
+        REGULATOR_SUPPLY("dvdd", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
+};
+static struct regulator_consumer_supply __initdata ldo11_consumer[] = {
+        REGULATOR_SUPPLY("dvdd", "alc5625"), /* Realtek ALC5625 */
+};
+static struct regulator_consumer_supply __initdata ldo14_consumer[] = {
+        REGULATOR_SUPPLY("avdd18", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
+};
+static struct regulator_consumer_supply __initdata ldo17_consumer[] = {
+        REGULATOR_SUPPLY("vdd33", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
+};
+static struct regulator_consumer_supply __initdata buck1_consumer[] = {
+        REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */
+};
+static struct regulator_consumer_supply __initdata buck2_consumer[] = {
+        REGULATOR_SUPPLY("vdd_int", NULL), /* CPUFREQ */
+};
+static struct regulator_consumer_supply __initdata buck3_consumer[] = {
+        REGULATOR_SUPPLY("vdd_g3d", "mali_drm"), /* G3D */
+};
+static struct regulator_consumer_supply __initdata buck7_consumer[] = {
+        REGULATOR_SUPPLY("vcc", "platform-lcd"), /* LCD */
+};
+
+static struct regulator_init_data __initdata max8997_ldo1_data = {
+        .constraints    = {
+                .name           = "VDD_ABB_3.3V",
+                .min_uV         = 3300000,
+                .max_uV         = 3300000,
+                .apply_uV       = 1,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+};
+
+static struct regulator_init_data __initdata max8997_ldo2_data  = {
+        .constraints    = {
+                .name           = "VDD_ALIVE_1.1V",
+                .min_uV         = 1100000,
+                .max_uV         = 1100000,
+                .apply_uV       = 1,
+                .always_on      = 1,
+                .state_mem      = {
+                        .enabled        = 1,
+                },
+        },
+};
+
+static struct regulator_init_data __initdata max8997_ldo3_data = {
+        .constraints    = {
+                .name           = "VMIPI_1.1V",
+                .min_uV         = 1100000,
+                .max_uV         = 1100000,
+                .apply_uV       = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(ldo3_consumer),
+        .consumer_supplies      = ldo3_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo4_data = {
+        .constraints    = {
+                .name           = "VDD_RTC_1.8V",
+                .min_uV         = 1800000,
+                .max_uV         = 1800000,
+                .apply_uV       = 1,
+                .always_on      = 1,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+};
+
+static struct regulator_init_data __initdata max8997_ldo6_data = {
+        .constraints    = {
+                .name           = "VMIPI_1.8V",
+                .min_uV         = 1800000,
+                .max_uV         = 1800000,
+                .apply_uV       = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(ldo6_consumer),
+        .consumer_supplies      = ldo6_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo7_data = {
+        .constraints    = {
+                .name           = "VDD_AUD_1.8V",
+                .min_uV         = 1800000,
+                .max_uV         = 1800000,
+                .apply_uV       = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(ldo7_consumer),
+        .consumer_supplies      = ldo7_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo8_data = {
+        .constraints    = {
+                .name           = "VADC_3.3V",
+                .min_uV         = 3300000,
+                .max_uV         = 3300000,
+                .apply_uV       = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(ldo8_consumer),
+        .consumer_supplies      = ldo8_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo9_data = {
+        .constraints    = {
+                .name           = "DVDD_SWB_2.8V",
+                .min_uV         = 2800000,
+                .max_uV         = 2800000,
+                .apply_uV       = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(ldo9_consumer),
+        .consumer_supplies      = ldo9_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo10_data = {
+        .constraints    = {
+                .name           = "VDD_PLL_1.1V",
+                .min_uV         = 1100000,
+                .max_uV         = 1100000,
+                .apply_uV       = 1,
+                .always_on      = 1,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+};
+
+static struct regulator_init_data __initdata max8997_ldo11_data = {
+        .constraints    = {
+                .name           = "VDD_AUD_3V",
+                .min_uV         = 3000000,
+                .max_uV         = 3000000,
+                .apply_uV       = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(ldo11_consumer),
+        .consumer_supplies      = ldo11_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo14_data = {
+        .constraints    = {
+                .name           = "AVDD18_SWB_1.8V",
+                .min_uV         = 1800000,
+                .max_uV         = 1800000,
+                .apply_uV       = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(ldo14_consumer),
+        .consumer_supplies      = ldo14_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo17_data = {
+        .constraints    = {
+                .name           = "VDD_SWB_3.3V",
+                .min_uV         = 3300000,
+                .max_uV         = 3300000,
+                .apply_uV       = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(ldo17_consumer),
+        .consumer_supplies      = ldo17_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_ldo21_data = {
+        .constraints    = {
+                .name           = "VDD_MIF_1.2V",
+                .min_uV         = 1200000,
+                .max_uV         = 1200000,
+                .apply_uV       = 1,
+                .always_on      = 1,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+};
+
+static struct regulator_init_data __initdata max8997_buck1_data = {
+        .constraints    = {
+                .name           = "VDD_ARM_1.2V",
+                .min_uV         = 950000,
+                .max_uV         = 1350000,
+                .always_on      = 1,
+                .boot_on        = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(buck1_consumer),
+        .consumer_supplies      = buck1_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_buck2_data = {
+        .constraints    = {
+                .name           = "VDD_INT_1.1V",
+                .min_uV         = 900000,
+                .max_uV         = 1100000,
+                .always_on      = 1,
+                .boot_on        = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(buck2_consumer),
+        .consumer_supplies      = buck2_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_buck3_data = {
+        .constraints    = {
+                .name           = "VDD_G3D_1.1V",
+                .min_uV         = 900000,
+                .max_uV         = 1100000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                        REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(buck3_consumer),
+        .consumer_supplies      = buck3_consumer,
+};
+
+static struct regulator_init_data __initdata max8997_buck5_data = {
+        .constraints    = {
+                .name           = "VDDQ_M1M2_1.2V",
+                .min_uV         = 1200000,
+                .max_uV         = 1200000,
+                .apply_uV       = 1,
+                .always_on      = 1,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+};
+
+static struct regulator_init_data __initdata max8997_buck7_data = {
+        .constraints    = {
+                .name           = "VDD_LCD_3.3V",
+                .min_uV         = 3300000,
+                .max_uV         = 3300000,
+                .boot_on        = 1,
+                .apply_uV       = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .disabled       = 1
+                },
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(buck7_consumer),
+        .consumer_supplies      = buck7_consumer,
+};
+
+static struct max8997_regulator_data __initdata origen_max8997_regulators[] = {
+        { MAX8997_LDO1,         &max8997_ldo1_data },
+        { MAX8997_LDO2,         &max8997_ldo2_data },
+        { MAX8997_LDO3,         &max8997_ldo3_data },
+        { MAX8997_LDO4,         &max8997_ldo4_data },
+        { MAX8997_LDO6,         &max8997_ldo6_data },
+        { MAX8997_LDO7,         &max8997_ldo7_data },
+        { MAX8997_LDO8,         &max8997_ldo8_data },
+        { MAX8997_LDO9,         &max8997_ldo9_data },
+        { MAX8997_LDO10,        &max8997_ldo10_data },
+        { MAX8997_LDO11,        &max8997_ldo11_data },
+        { MAX8997_LDO14,        &max8997_ldo14_data },
+        { MAX8997_LDO17,        &max8997_ldo17_data },
+        { MAX8997_LDO21,        &max8997_ldo21_data },
+        { MAX8997_BUCK1,        &max8997_buck1_data },
+        { MAX8997_BUCK2,        &max8997_buck2_data },
+        { MAX8997_BUCK3,        &max8997_buck3_data },
+        { MAX8997_BUCK5,        &max8997_buck5_data },
+        { MAX8997_BUCK7,        &max8997_buck7_data },
+};
+
+struct max8997_platform_data __initdata origen_max8997_pdata = {
+        .num_regulators = ARRAY_SIZE(origen_max8997_regulators),
+        .regulators     = origen_max8997_regulators,
+
+        .wakeup = true,
+        .buck1_gpiodvs  = false,
+        .buck2_gpiodvs  = false,
+        .buck5_gpiodvs  = false,
+        .irq_base       = IRQ_GPIO_END + 1,
+
+        .ignore_gpiodvs_side_effect = true,
+        .buck125_default_idx = 0x0,
+
+        .buck125_gpios[0]       = EXYNOS4_GPX0(0),
+        .buck125_gpios[1]       = EXYNOS4_GPX0(1),
+        .buck125_gpios[2]       = EXYNOS4_GPX0(2),
+
+        .buck1_voltage[0]       = 1350000,
+        .buck1_voltage[1]       = 1300000,
+        .buck1_voltage[2]       = 1250000,
+        .buck1_voltage[3]       = 1200000,
+        .buck1_voltage[4]       = 1150000,
+        .buck1_voltage[5]       = 1100000,
+        .buck1_voltage[6]       = 1000000,
+        .buck1_voltage[7]       = 950000,
+
+        .buck2_voltage[0]       = 1100000,
+        .buck2_voltage[1]       = 1100000,
+        .buck2_voltage[2]       = 1100000,
+        .buck2_voltage[3]       = 1100000,
+        .buck2_voltage[4]       = 1000000,
+        .buck2_voltage[5]       = 1000000,
+        .buck2_voltage[6]       = 1000000,
+        .buck2_voltage[7]       = 1000000,
+
+        .buck5_voltage[0]       = 1200000,
+        .buck5_voltage[1]       = 1200000,
+        .buck5_voltage[2]       = 1200000,
+        .buck5_voltage[3]       = 1200000,
+        .buck5_voltage[4]       = 1200000,
+        .buck5_voltage[5]       = 1200000,
+        .buck5_voltage[6]       = 1200000,
+        .buck5_voltage[7]       = 1200000,
+};
+
+/* I2C0 */
+static struct i2c_board_info i2c0_devs[] __initdata = {
+        {
+                I2C_BOARD_INFO("max8997", (0xCC >> 1)),
+                .platform_data  = &origen_max8997_pdata,
+                .irq            = IRQ_EINT(4),
+        },
+};
+
+static struct s3c_sdhci_platdata origen_hsmmc0_pdata __initdata = {
+        .cd_type                = S3C_SDHCI_CD_INTERNAL,
+        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = {
+        .cd_type                = S3C_SDHCI_CD_INTERNAL,
+        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+/* USB EHCI */
+static struct s5p_ehci_platdata origen_ehci_pdata;
+
+static void __init origen_ehci_init(void)
+{
+        struct s5p_ehci_platdata *pdata = &origen_ehci_pdata;
+
+        s5p_ehci_set_platdata(pdata);
+}
+
+static struct gpio_keys_button origen_gpio_keys_table[] = {
+        {
+                .code                   = KEY_MENU,
+                .gpio                   = EXYNOS4_GPX1(5),
+                .desc                   = "gpio-keys: KEY_MENU",
+                .type                   = EV_KEY,
+                .active_low             = 1,
+                .wakeup                 = 1,
+                .debounce_interval      = 1,
+        }, {
+                .code                   = KEY_HOME,
+                .gpio                   = EXYNOS4_GPX1(6),
+                .desc                   = "gpio-keys: KEY_HOME",
+                .type                   = EV_KEY,
+                .active_low             = 1,
+                .wakeup                 = 1,
+                .debounce_interval      = 1,
+        }, {
+                .code                   = KEY_BACK,
+                .gpio                   = EXYNOS4_GPX1(7),
+                .desc                   = "gpio-keys: KEY_BACK",
+                .type                   = EV_KEY,
+                .active_low             = 1,
+                .wakeup                 = 1,
+                .debounce_interval      = 1,
+        }, {
+                .code                   = KEY_UP,
+                .gpio                   = EXYNOS4_GPX2(0),
+                .desc                   = "gpio-keys: KEY_UP",
+                .type                   = EV_KEY,
+                .active_low             = 1,
+                .wakeup                 = 1,
+                .debounce_interval      = 1,
+        }, {
+                .code                   = KEY_DOWN,
+                .gpio                   = EXYNOS4_GPX2(1),
+                .desc                   = "gpio-keys: KEY_DOWN",
+                .type                   = EV_KEY,
+                .active_low             = 1,
+                .wakeup                 = 1,
+                .debounce_interval      = 1,
+        },
+};
+
+static struct gpio_keys_platform_data origen_gpio_keys_data = {
+        .buttons        = origen_gpio_keys_table,
+        .nbuttons       = ARRAY_SIZE(origen_gpio_keys_table),
+};
+
+static struct platform_device origen_device_gpiokeys = {
+        .name           = "gpio-keys",
+        .dev            = {
+                .platform_data  = &origen_gpio_keys_data,
+        },
+};
+
+static void lcd_hv070wsa_set_power(struct plat_lcd_data *pd, unsigned int power)
+{
+        int ret;
+
+        if (power)
+                ret = gpio_request_one(EXYNOS4_GPE3(4),
+                                        GPIOF_OUT_INIT_HIGH, "GPE3_4");
+        else
+                ret = gpio_request_one(EXYNOS4_GPE3(4),
+                                        GPIOF_OUT_INIT_LOW, "GPE3_4");
+
+        gpio_free(EXYNOS4_GPE3(4));
+
+        if (ret)
+                pr_err("failed to request gpio for LCD power: %d\n", ret);
+}
+
+static struct plat_lcd_data origen_lcd_hv070wsa_data = {
+        .set_power = lcd_hv070wsa_set_power,
+};
+
+static struct platform_device origen_lcd_hv070wsa = {
+        .name                   = "platform-lcd",
+        .dev.parent             = &s5p_device_fimd0.dev,
+        .dev.platform_data      = &origen_lcd_hv070wsa_data,
+};
+
+static struct s3c_fb_pd_win origen_fb_win0 = {
+        .win_mode = {
+                .left_margin    = 64,
+                .right_margin   = 16,
+                .upper_margin   = 64,
+                .lower_margin   = 16,
+                .hsync_len      = 48,
+                .vsync_len      = 3,
+                .xres           = 1024,
+                .yres           = 600,
+        },
+        .max_bpp                = 32,
+        .default_bpp            = 24,
+};
+
+static struct s3c_fb_platdata origen_lcd_pdata __initdata = {
+        .win[0]         = &origen_fb_win0,
+        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+        .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
+};
+
+static struct platform_device *origen_devices[] __initdata = {
+        &s3c_device_hsmmc2,
+        &s3c_device_hsmmc0,
+        &s3c_device_i2c0,
+        &s3c_device_rtc,
+        &s3c_device_wdt,
+        &s5p_device_ehci,
+        &s5p_device_fimc0,
+        &s5p_device_fimc1,
+        &s5p_device_fimc2,
+        &s5p_device_fimc3,
+        &s5p_device_fimd0,
+        &s5p_device_hdmi,
+        &s5p_device_i2c_hdmiphy,
+        &s5p_device_mixer,
+        &exynos4_device_pd[PD_LCD0],
+        &exynos4_device_pd[PD_TV],
+        &origen_device_gpiokeys,
+        &origen_lcd_hv070wsa,
+};
+
+/* LCD Backlight data */
+static struct samsung_bl_gpio_info origen_bl_gpio_info = {
+        .no             = EXYNOS4_GPD0(0),
+        .func           = S3C_GPIO_SFN(2),
+};
+
+static struct platform_pwm_backlight_data origen_bl_data = {
+        .pwm_id         = 0,
+        .pwm_period_ns  = 1000,
+};
+
+static void s5p_tv_setup(void)
+{
+        /* Direct HPD to HDMI chip */
+        gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug");
+        s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
+        s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
+}
+
+static void __init origen_map_io(void)
+{
+        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+        s3c24xx_init_clocks(24000000);
+        s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
+}
+
+static void __init origen_power_init(void)
+{
+        gpio_request(EXYNOS4_GPX0(4), "PMIC_IRQ");
+        s3c_gpio_cfgpin(EXYNOS4_GPX0(4), S3C_GPIO_SFN(0xf));
+        s3c_gpio_setpull(EXYNOS4_GPX0(4), S3C_GPIO_PULL_NONE);
+}
+
+static void __init origen_machine_init(void)
+{
+        origen_power_init();
+
+        s3c_i2c0_set_platdata(NULL);
+        i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
+
+        /*
+         * Since sdhci instance 2 can contain a bootable media,
+         * sdhci instance 0 is registered after instance 2.
+         */
+        s3c_sdhci2_set_platdata(&origen_hsmmc2_pdata);
+        s3c_sdhci0_set_platdata(&origen_hsmmc0_pdata);
+
+        origen_ehci_init();
+        clk_xusbxti.rate = 24000000;
+
+        s5p_tv_setup();
+        s5p_i2c_hdmiphy_set_platdata(NULL);
+
+        s5p_fimd0_set_platdata(&origen_lcd_pdata);
+
+        platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices));
+        s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+
+        s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
+        s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
+
+        samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data);
+}
+
+MACHINE_START(ORIGEN, "ORIGEN")
+        /* Maintainer: JeongHyeon Kim <jhkim@insignal.co.kr> */
+        .atag_offset    = 0x100,
+        .init_irq       = exynos4_init_irq,
+        .map_io         = origen_map_io,
+        .init_machine   = origen_machine_init,
+        .timer          = &exynos4_timer,
+MACHINE_END
diff --git a/arch/arm/mach-exynos4/mach-smdk4x12.c b/arch/arm/mach-exynos4/mach-smdk4x12.c
new file mode 100644
index 000000000000..fcf2e0e23d53
--- /dev/null
+++ b/arch/arm/mach-exynos4/mach-smdk4x12.c
@@ -0,0 +1,302 @@
+/*
+ * linux/arch/arm/mach-exynos4/mach-smdk4x12.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/input.h>
+#include <linux/io.h>
+#include <linux/mfd/max8997.h>
+#include <linux/mmc/host.h>
+#include <linux/platform_device.h>
+#include <linux/pwm_backlight.h>
+#include <linux/regulator/machine.h>
+#include <linux/serial_core.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <plat/backlight.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/exynos4.h>
+#include <plat/gpio-cfg.h>
+#include <plat/iic.h>
+#include <plat/keypad.h>
+#include <plat/regs-serial.h>
+#include <plat/sdhci.h>
+
+#include <mach/map.h>
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define SMDK4X12_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
+                                 S3C2410_UCON_RXILEVEL |        \
+                                 S3C2410_UCON_TXIRQMODE |       \
+                                 S3C2410_UCON_RXIRQMODE |       \
+                                 S3C2410_UCON_RXFIFO_TOI |      \
+                                 S3C2443_UCON_RXERR_IRQEN)
+
+#define SMDK4X12_ULCON_DEFAULT  S3C2410_LCON_CS8
+
+#define SMDK4X12_UFCON_DEFAULT  (S3C2410_UFCON_FIFOMODE |       \
+                                 S5PV210_UFCON_TXTRIG4 |        \
+                                 S5PV210_UFCON_RXTRIG4)
+
+static struct s3c2410_uartcfg smdk4x12_uartcfgs[] __initdata = {
+        [0] = {
+                .hwport         = 0,
+                .flags          = 0,
+                .ucon           = SMDK4X12_UCON_DEFAULT,
+                .ulcon          = SMDK4X12_ULCON_DEFAULT,
+                .ufcon          = SMDK4X12_UFCON_DEFAULT,
+        },
+        [1] = {
+                .hwport         = 1,
+                .flags          = 0,
+                .ucon           = SMDK4X12_UCON_DEFAULT,
+                .ulcon          = SMDK4X12_ULCON_DEFAULT,
+                .ufcon          = SMDK4X12_UFCON_DEFAULT,
+        },
+        [2] = {
+                .hwport         = 2,
+                .flags          = 0,
+                .ucon           = SMDK4X12_UCON_DEFAULT,
+                .ulcon          = SMDK4X12_ULCON_DEFAULT,
+                .ufcon          = SMDK4X12_UFCON_DEFAULT,
+        },
+        [3] = {
+                .hwport         = 3,
+                .flags          = 0,
+                .ucon           = SMDK4X12_UCON_DEFAULT,
+                .ulcon          = SMDK4X12_ULCON_DEFAULT,
+                .ufcon          = SMDK4X12_UFCON_DEFAULT,
+        },
+};
+
+static struct s3c_sdhci_platdata smdk4x12_hsmmc2_pdata __initdata = {
+        .cd_type                = S3C_SDHCI_CD_INTERNAL,
+        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
+        .max_width              = 8,
+        .host_caps              = MMC_CAP_8_BIT_DATA,
+#endif
+};
+
+static struct s3c_sdhci_platdata smdk4x12_hsmmc3_pdata __initdata = {
+        .cd_type                = S3C_SDHCI_CD_INTERNAL,
+        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+static struct regulator_consumer_supply max8997_buck1 =
+        REGULATOR_SUPPLY("vdd_arm", NULL);
+
+static struct regulator_consumer_supply max8997_buck2 =
+        REGULATOR_SUPPLY("vdd_int", NULL);
+
+static struct regulator_consumer_supply max8997_buck3 =
+        REGULATOR_SUPPLY("vdd_g3d", NULL);
+
+static struct regulator_init_data max8997_buck1_data = {
+        .constraints    = {
+                .name           = "VDD_ARM_SMDK4X12",
+                .min_uV         = 925000,
+                .max_uV         = 1350000,
+                .always_on      = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &max8997_buck1,
+};
+
+static struct regulator_init_data max8997_buck2_data = {
+        .constraints    = {
+                .name           = "VDD_INT_SMDK4X12",
+                .min_uV         = 950000,
+                .max_uV         = 1150000,
+                .always_on      = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &max8997_buck2,
+};
+
+static struct regulator_init_data max8997_buck3_data = {
+        .constraints    = {
+                .name           = "VDD_G3D_SMDK4X12",
+                .min_uV         = 950000,
+                .max_uV         = 1150000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                  REGULATOR_CHANGE_STATUS,
+                .state_mem      = {
+                        .disabled       = 1,
+                },
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &max8997_buck3,
+};
+
+static struct max8997_regulator_data smdk4x12_max8997_regulators[] = {
+        { MAX8997_BUCK1, &max8997_buck1_data },
+        { MAX8997_BUCK2, &max8997_buck2_data },
+        { MAX8997_BUCK3, &max8997_buck3_data },
+};
+
+static struct max8997_platform_data smdk4x12_max8997_pdata = {
+        .num_regulators = ARRAY_SIZE(smdk4x12_max8997_regulators),
+        .regulators     = smdk4x12_max8997_regulators,
+
+        .buck1_voltage[0] = 1100000,    /* 1.1V */
+        .buck1_voltage[1] = 1100000,    /* 1.1V */
+        .buck1_voltage[2] = 1100000,    /* 1.1V */
+        .buck1_voltage[3] = 1100000,    /* 1.1V */
+        .buck1_voltage[4] = 1100000,    /* 1.1V */
+        .buck1_voltage[5] = 1100000,    /* 1.1V */
+        .buck1_voltage[6] = 1000000,    /* 1.0V */
+        .buck1_voltage[7] = 950000,     /* 0.95V */
+
+        .buck2_voltage[0] = 1100000,    /* 1.1V */
+        .buck2_voltage[1] = 1000000,    /* 1.0V */
+        .buck2_voltage[2] = 950000,     /* 0.95V */
+        .buck2_voltage[3] = 900000,     /* 0.9V */
+        .buck2_voltage[4] = 1100000,    /* 1.1V */
+        .buck2_voltage[5] = 1000000,    /* 1.0V */
+        .buck2_voltage[6] = 950000,     /* 0.95V */
+        .buck2_voltage[7] = 900000,     /* 0.9V */
+
+        .buck5_voltage[0] = 1100000,    /* 1.1V */
+        .buck5_voltage[1] = 1100000,    /* 1.1V */
+        .buck5_voltage[2] = 1100000,    /* 1.1V */
+        .buck5_voltage[3] = 1100000,    /* 1.1V */
+        .buck5_voltage[4] = 1100000,    /* 1.1V */
+        .buck5_voltage[5] = 1100000,    /* 1.1V */
+        .buck5_voltage[6] = 1100000,    /* 1.1V */
+        .buck5_voltage[7] = 1100000,    /* 1.1V */
+};
+
+static struct i2c_board_info smdk4x12_i2c_devs0[] __initdata = {
+        {
+                I2C_BOARD_INFO("max8997", 0x66),
+                .platform_data  = &smdk4x12_max8997_pdata,
+        }
+};
+
+static struct i2c_board_info smdk4x12_i2c_devs1[] __initdata = {
+        { I2C_BOARD_INFO("wm8994", 0x1a), }
+};
+
+static struct i2c_board_info smdk4x12_i2c_devs3[] __initdata = {
+        /* nothing here yet */
+};
+
+static struct i2c_board_info smdk4x12_i2c_devs7[] __initdata = {
+        /* nothing here yet */
+};
+
+static struct samsung_bl_gpio_info smdk4x12_bl_gpio_info = {
+        .no = EXYNOS4_GPD0(1),
+        .func = S3C_GPIO_SFN(2),
+};
+
+static struct platform_pwm_backlight_data smdk4x12_bl_data = {
+        .pwm_id = 1,
+        .pwm_period_ns  = 1000,
+};
+
+static uint32_t smdk4x12_keymap[] __initdata = {
+        /* KEY(row, col, keycode) */
+        KEY(1, 0, KEY_D), KEY(1, 1, KEY_A), KEY(1, 2, KEY_B),
+        KEY(1, 3, KEY_E), KEY(1, 4, KEY_C)
+};
+
+static struct matrix_keymap_data smdk4x12_keymap_data __initdata = {
+        .keymap         = smdk4x12_keymap,
+        .keymap_size    = ARRAY_SIZE(smdk4x12_keymap),
+};
+
+static struct samsung_keypad_platdata smdk4x12_keypad_data __initdata = {
+        .keymap_data    = &smdk4x12_keymap_data,
+        .rows           = 2,
+        .cols           = 5,
+};
+
+static struct platform_device *smdk4x12_devices[] __initdata = {
+        &s3c_device_hsmmc2,
+        &s3c_device_hsmmc3,
+        &s3c_device_i2c0,
+        &s3c_device_i2c1,
+        &s3c_device_i2c3,
+        &s3c_device_i2c7,
+        &s3c_device_rtc,
+        &s3c_device_wdt,
+        &samsung_device_keypad,
+};
+
+static void __init smdk4x12_map_io(void)
+{
+        clk_xusbxti.rate = 24000000;
+
+        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+        s3c24xx_init_clocks(clk_xusbxti.rate);
+        s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
+}
+
+static void __init smdk4x12_machine_init(void)
+{
+        s3c_i2c0_set_platdata(NULL);
+        i2c_register_board_info(0, smdk4x12_i2c_devs0,
+                                ARRAY_SIZE(smdk4x12_i2c_devs0));
+
+        s3c_i2c1_set_platdata(NULL);
+        i2c_register_board_info(1, smdk4x12_i2c_devs1,
+                                ARRAY_SIZE(smdk4x12_i2c_devs1));
+
+        s3c_i2c3_set_platdata(NULL);
+        i2c_register_board_info(3, smdk4x12_i2c_devs3,
+                                ARRAY_SIZE(smdk4x12_i2c_devs3));
+
+        s3c_i2c7_set_platdata(NULL);
+        i2c_register_board_info(7, smdk4x12_i2c_devs7,
+                                ARRAY_SIZE(smdk4x12_i2c_devs7));
+
+        samsung_bl_set(&smdk4x12_bl_gpio_info, &smdk4x12_bl_data);
+
+        samsung_keypad_set_platdata(&smdk4x12_keypad_data);
+
+        s3c_sdhci2_set_platdata(&smdk4x12_hsmmc2_pdata);
+        s3c_sdhci3_set_platdata(&smdk4x12_hsmmc3_pdata);
+
+        platform_add_devices(smdk4x12_devices, ARRAY_SIZE(smdk4x12_devices));
+}
+
+MACHINE_START(SMDK4212, "SMDK4212")
+        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+        .atag_offset    = 0x100,
+        .init_irq       = exynos4_init_irq,
+        .map_io         = smdk4x12_map_io,
+        .init_machine   = smdk4x12_machine_init,
+        .timer          = &exynos4_timer,
+MACHINE_END
+
+MACHINE_START(SMDK4412, "SMDK4412")
+        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+        /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
+        .atag_offset    = 0x100,
+        .init_irq       = exynos4_init_irq,
+        .map_io         = smdk4x12_map_io,
+        .init_machine   = smdk4x12_machine_init,
+        .timer          = &exynos4_timer,
+MACHINE_END
diff --git a/arch/arm/mach-exynos4/mach-smdkc210.c b/arch/arm/mach-exynos4/mach-smdkc210.c
deleted file mode 100644
index a7c65e05c1eb..000000000000
--- a/arch/arm/mach-exynos4/mach-smdkc210.c
+++ /dev/null
@@ -1,309 +0,0 @@
-/* linux/arch/arm/mach-exynos4/mach-smdkc210.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/serial_core.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/lcd.h>
-#include <linux/mmc/host.h>
-#include <linux/platform_device.h>
-#include <linux/smsc911x.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
-#include <linux/pwm_backlight.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <video/platform_lcd.h>
-
-#include <plat/regs-serial.h>
-#include <plat/regs-srom.h>
-#include <plat/regs-fb-v4.h>
-#include <plat/exynos4.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/fb.h>
-#include <plat/sdhci.h>
-#include <plat/iic.h>
-#include <plat/pd.h>
-#include <plat/gpio-cfg.h>
-#include <plat/backlight.h>
-
-#include <mach/map.h>
-
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define SMDKC210_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
-                                 S3C2410_UCON_RXILEVEL |        \
-                                 S3C2410_UCON_TXIRQMODE |       \
-                                 S3C2410_UCON_RXIRQMODE |       \
-                                 S3C2410_UCON_RXFIFO_TOI |      \
-                                 S3C2443_UCON_RXERR_IRQEN)
-
-#define SMDKC210_ULCON_DEFAULT  S3C2410_LCON_CS8
-
-#define SMDKC210_UFCON_DEFAULT  (S3C2410_UFCON_FIFOMODE |       \
-                                 S5PV210_UFCON_TXTRIG4 |        \
-                                 S5PV210_UFCON_RXTRIG4)
-
-static struct s3c2410_uartcfg smdkc210_uartcfgs[] __initdata = {
-        [0] = {
-                .hwport         = 0,
-                .flags          = 0,
-                .ucon           = SMDKC210_UCON_DEFAULT,
-                .ulcon          = SMDKC210_ULCON_DEFAULT,
-                .ufcon          = SMDKC210_UFCON_DEFAULT,
-        },
-        [1] = {
-                .hwport         = 1,
-                .flags          = 0,
-                .ucon           = SMDKC210_UCON_DEFAULT,
-                .ulcon          = SMDKC210_ULCON_DEFAULT,
-                .ufcon          = SMDKC210_UFCON_DEFAULT,
-        },
-        [2] = {
-                .hwport         = 2,
-                .flags          = 0,
-                .ucon           = SMDKC210_UCON_DEFAULT,
-                .ulcon          = SMDKC210_ULCON_DEFAULT,
-                .ufcon          = SMDKC210_UFCON_DEFAULT,
-        },
-        [3] = {
-                .hwport         = 3,
-                .flags          = 0,
-                .ucon           = SMDKC210_UCON_DEFAULT,
-                .ulcon          = SMDKC210_ULCON_DEFAULT,
-                .ufcon          = SMDKC210_UFCON_DEFAULT,
-        },
-};
-
-static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = EXYNOS4_GPK0(2),
-        .ext_cd_gpio_invert     = 1,
-        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
-        .max_width              = 8,
-        .host_caps              = MMC_CAP_8_BIT_DATA,
-#endif
-};
-
-static struct s3c_sdhci_platdata smdkc210_hsmmc1_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = EXYNOS4_GPK0(2),
-        .ext_cd_gpio_invert     = 1,
-        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-};
-
-static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = EXYNOS4_GPK2(2),
-        .ext_cd_gpio_invert     = 1,
-        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
-        .max_width              = 8,
-        .host_caps              = MMC_CAP_8_BIT_DATA,
-#endif
-};
-
-static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = EXYNOS4_GPK2(2),
-        .ext_cd_gpio_invert     = 1,
-        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
-};
-
-static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
-                                   unsigned int power)
-{
-        if (power) {
-#if !defined(CONFIG_BACKLIGHT_PWM)
-                gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
-                gpio_free(EXYNOS4_GPD0(1));
-#endif
-                /* fire nRESET on power up */
-                gpio_request(EXYNOS4_GPX0(6), "GPX0");
-
-                gpio_direction_output(EXYNOS4_GPX0(6), 1);
-                mdelay(100);
-
-                gpio_set_value(EXYNOS4_GPX0(6), 0);
-                mdelay(10);
-
-                gpio_set_value(EXYNOS4_GPX0(6), 1);
-                mdelay(10);
-
-                gpio_free(EXYNOS4_GPX0(6));
-        } else {
-#if !defined(CONFIG_BACKLIGHT_PWM)
-                gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
-                gpio_free(EXYNOS4_GPD0(1));
-#endif
-        }
-}
-
-static struct plat_lcd_data smdkc210_lcd_lte480wv_data = {
-        .set_power              = lcd_lte480wv_set_power,
-};
-
-static struct platform_device smdkc210_lcd_lte480wv = {
-        .name                   = "platform-lcd",
-        .dev.parent             = &s5p_device_fimd0.dev,
-        .dev.platform_data      = &smdkc210_lcd_lte480wv_data,
-};
-
-static struct s3c_fb_pd_win smdkc210_fb_win0 = {
-        .win_mode = {
-                .left_margin    = 13,
-                .right_margin   = 8,
-                .upper_margin   = 7,
-                .lower_margin   = 5,
-                .hsync_len      = 3,
-                .vsync_len      = 1,
-                .xres           = 800,
-                .yres           = 480,
-        },
-        .max_bpp                = 32,
-        .default_bpp            = 24,
-};
-
-static struct s3c_fb_platdata smdkc210_lcd0_pdata __initdata = {
-        .win[0]         = &smdkc210_fb_win0,
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
-};
-
-static struct resource smdkc210_smsc911x_resources[] = {
-        [0] = {
-                .start  = EXYNOS4_PA_SROM_BANK(1),
-                .end    = EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_EINT(5),
-                .end    = IRQ_EINT(5),
-                .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
-        },
-};
-
-static struct smsc911x_platform_config smsc9215_config = {
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
-        .flags          = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
-        .phy_interface  = PHY_INTERFACE_MODE_MII,
-        .mac            = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
-};
-
-static struct platform_device smdkc210_smsc911x = {
-        .name           = "smsc911x",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(smdkc210_smsc911x_resources),
-        .resource       = smdkc210_smsc911x_resources,
-        .dev            = {
-                .platform_data  = &smsc9215_config,
-        },
-};
-
-static struct i2c_board_info i2c_devs1[] __initdata = {
-        {I2C_BOARD_INFO("wm8994", 0x1a),},
-};
-
-static struct platform_device *smdkc210_devices[] __initdata = {
-        &s3c_device_hsmmc0,
-        &s3c_device_hsmmc1,
-        &s3c_device_hsmmc2,
-        &s3c_device_hsmmc3,
-        &s3c_device_i2c1,
-        &s3c_device_rtc,
-        &s3c_device_wdt,
-        &exynos4_device_ac97,
-        &exynos4_device_i2s0,
-        &exynos4_device_pd[PD_MFC],
-        &exynos4_device_pd[PD_G3D],
-        &exynos4_device_pd[PD_LCD0],
-        &exynos4_device_pd[PD_LCD1],
-        &exynos4_device_pd[PD_CAM],
-        &exynos4_device_pd[PD_TV],
-        &exynos4_device_pd[PD_GPS],
-        &exynos4_device_sysmmu,
-        &samsung_asoc_dma,
-        &s5p_device_fimd0,
-        &smdkc210_lcd_lte480wv,
-        &smdkc210_smsc911x,
-};
-
-static void __init smdkc210_smsc911x_init(void)
-{
-        u32 cs1;
-
-        /* configure nCS1 width to 16 bits */
-        cs1 = __raw_readl(S5P_SROM_BW) &
-                ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
-        cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
-                (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
-                (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
-                S5P_SROM_BW__NCS1__SHIFT;
-        __raw_writel(cs1, S5P_SROM_BW);
-
-        /* set timing for nCS1 suitable for ethernet chip */
-        __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
-                     (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
-                     (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
-                     (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
-                     (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
-                     (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
-                     (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
-}
-
-/* LCD Backlight data */
-static struct samsung_bl_gpio_info smdkc210_bl_gpio_info = {
-        .no = EXYNOS4_GPD0(1),
-        .func = S3C_GPIO_SFN(2),
-};
-
-static struct platform_pwm_backlight_data smdkc210_bl_data = {
-        .pwm_id = 1,
-        .pwm_period_ns  = 1000,
-};
-
-static void __init smdkc210_map_io(void)
-{
-        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
-        s3c24xx_init_clocks(24000000);
-        s3c24xx_init_uarts(smdkc210_uartcfgs, ARRAY_SIZE(smdkc210_uartcfgs));
-}
-
-static void __init smdkc210_machine_init(void)
-{
-        s3c_i2c1_set_platdata(NULL);
-        i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
-
-        smdkc210_smsc911x_init();
-
-        s3c_sdhci0_set_platdata(&smdkc210_hsmmc0_pdata);
-        s3c_sdhci1_set_platdata(&smdkc210_hsmmc1_pdata);
-        s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata);
-        s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata);
-
-        samsung_bl_set(&smdkc210_bl_gpio_info, &smdkc210_bl_data);
-        s5p_fimd0_set_platdata(&smdkc210_lcd0_pdata);
-
-        platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices));
-}
-
-MACHINE_START(SMDKC210, "SMDKC210")
-        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        .boot_params    = S5P_PA_SDRAM + 0x100,
-        .init_irq       = exynos4_init_irq,
-        .map_io         = smdkc210_map_io,
-        .init_machine   = smdkc210_machine_init,
-        .timer          = &exynos4_timer,
-MACHINE_END
diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c
index ea4149556860..cec2afabe7b4 100644
--- a/arch/arm/mach-exynos4/mach-smdkv310.c
+++ b/arch/arm/mach-exynos4/mach-smdkv310.c
@@ -9,7 +9,9 @@
 */
 
 #include <linux/serial_core.h>
+#include <linux/delay.h>
 #include <linux/gpio.h>
+#include <linux/lcd.h>
 #include <linux/mmc/host.h>
 #include <linux/platform_device.h>
 #include <linux/smsc911x.h>
@@ -21,17 +23,23 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
+#include <video/platform_lcd.h>
 #include <plat/regs-serial.h>
 #include <plat/regs-srom.h>
+#include <plat/regs-fb-v4.h>
 #include <plat/exynos4.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
+#include <plat/fb.h>
 #include <plat/keypad.h>
 #include <plat/sdhci.h>
 #include <plat/iic.h>
 #include <plat/pd.h>
 #include <plat/gpio-cfg.h>
 #include <plat/backlight.h>
+#include <plat/mfc.h>
+#include <plat/ehci.h>
+#include <plat/clock.h>
 
 #include <mach/map.h>
 
@@ -112,6 +120,67 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
         .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 };
 
+static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
+                                   unsigned int power)
+{
+        if (power) {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+                gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
+                gpio_free(EXYNOS4_GPD0(1));
+#endif
+                /* fire nRESET on power up */
+                gpio_request(EXYNOS4_GPX0(6), "GPX0");
+
+                gpio_direction_output(EXYNOS4_GPX0(6), 1);
+                mdelay(100);
+
+                gpio_set_value(EXYNOS4_GPX0(6), 0);
+                mdelay(10);
+
+                gpio_set_value(EXYNOS4_GPX0(6), 1);
+                mdelay(10);
+
+                gpio_free(EXYNOS4_GPX0(6));
+        } else {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+                gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
+                gpio_free(EXYNOS4_GPD0(1));
+#endif
+        }
+}
+
+static struct plat_lcd_data smdkv310_lcd_lte480wv_data = {
+        .set_power              = lcd_lte480wv_set_power,
+};
+
+static struct platform_device smdkv310_lcd_lte480wv = {
+        .name                   = "platform-lcd",
+        .dev.parent             = &s5p_device_fimd0.dev,
+        .dev.platform_data      = &smdkv310_lcd_lte480wv_data,
+};
+
+static struct s3c_fb_pd_win smdkv310_fb_win0 = {
+        .win_mode = {
+                .left_margin    = 13,
+                .right_margin   = 8,
+                .upper_margin   = 7,
+                .lower_margin   = 5,
+                .hsync_len      = 3,
+                .vsync_len      = 1,
+                .xres           = 800,
+                .yres           = 480,
+        },
+        .max_bpp                = 32,
+        .default_bpp            = 24,
+};
+
+static struct s3c_fb_platdata smdkv310_lcd0_pdata __initdata = {
+        .win[0]         = &smdkv310_fb_win0,
+        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+        .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
+};
+
 static struct resource smdkv310_smsc911x_resources[] = {
         [0] = {
                 .start  = EXYNOS4_PA_SROM_BANK(1),
@@ -166,17 +235,36 @@ static struct i2c_board_info i2c_devs1[] __initdata = {
         {I2C_BOARD_INFO("wm8994", 0x1a),},
 };
 
+/* USB EHCI */
+static struct s5p_ehci_platdata smdkv310_ehci_pdata;
+
+static void __init smdkv310_ehci_init(void)
+{
+        struct s5p_ehci_platdata *pdata = &smdkv310_ehci_pdata;
+
+        s5p_ehci_set_platdata(pdata);
+}
+
 static struct platform_device *smdkv310_devices[] __initdata = {
         &s3c_device_hsmmc0,
         &s3c_device_hsmmc1,
         &s3c_device_hsmmc2,
         &s3c_device_hsmmc3,
         &s3c_device_i2c1,
+        &s5p_device_i2c_hdmiphy,
         &s3c_device_rtc,
         &s3c_device_wdt,
+        &s5p_device_ehci,
+        &s5p_device_fimc0,
+        &s5p_device_fimc1,
+        &s5p_device_fimc2,
+        &s5p_device_fimc3,
         &exynos4_device_ac97,
         &exynos4_device_i2s0,
         &samsung_device_keypad,
+        &s5p_device_mfc,
+        &s5p_device_mfc_l,
+        &s5p_device_mfc_r,
         &exynos4_device_pd[PD_MFC],
         &exynos4_device_pd[PD_G3D],
         &exynos4_device_pd[PD_LCD0],
@@ -188,8 +276,12 @@ static struct platform_device *smdkv310_devices[] __initdata = {
         &exynos4_device_sysmmu,
         &samsung_asoc_dma,
         &samsung_asoc_idma,
+        &s5p_device_fimd0,
+        &smdkv310_lcd_lte480wv,
         &smdkv310_smsc911x,
         &exynos4_device_ahci,
+        &s5p_device_hdmi,
+        &s5p_device_mixer,
 };
 
 static void __init smdkv310_smsc911x_init(void)
@@ -226,6 +318,18 @@ static struct platform_pwm_backlight_data smdkv310_bl_data = {
         .pwm_period_ns  = 1000,
 };
 
+static void s5p_tv_setup(void)
+{
+        /* direct HPD to HDMI chip */
+        WARN_ON(gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"));
+        s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
+        s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
+
+        /* setup dependencies between TV devices */
+        s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
+        s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
+}
+
 static void __init smdkv310_map_io(void)
 {
         s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@@ -233,6 +337,11 @@ static void __init smdkv310_map_io(void)
         s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
 }
 
+static void __init smdkv310_reserve(void)
+{
+        s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
+}
+
 static void __init smdkv310_machine_init(void)
 {
         s3c_i2c1_set_platdata(NULL);
@@ -245,17 +354,35 @@ static void __init smdkv310_machine_init(void)
         s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
         s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);
 
+        s5p_tv_setup();
+        s5p_i2c_hdmiphy_set_platdata(NULL);
+
         samsung_keypad_set_platdata(&smdkv310_keypad_data);
 
         samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data);
+        s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata);
+
+        smdkv310_ehci_init();
+        clk_xusbxti.rate = 24000000;
 
         platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
+        s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
 }
 
 MACHINE_START(SMDKV310, "SMDKV310")
         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
         /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
-        .boot_params    = S5P_PA_SDRAM + 0x100,
+        .atag_offset    = 0x100,
+        .init_irq       = exynos4_init_irq,
+        .map_io         = smdkv310_map_io,
+        .init_machine   = smdkv310_machine_init,
+        .timer          = &exynos4_timer,
+        .reserve        = &smdkv310_reserve,
+MACHINE_END
+
+MACHINE_START(SMDKC210, "SMDKC210")
+        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+        .atag_offset    = 0x100,
         .init_irq       = exynos4_init_irq,
         .map_io         = smdkv310_map_io,
         .init_machine   = smdkv310_machine_init,
diff --git a/arch/arm/mach-exynos4/mach-universal_c210.c b/arch/arm/mach-exynos4/mach-universal_c210.c
index b3b5d8911004..18cf5c7cf56d 100644
--- a/arch/arm/mach-exynos4/mach-universal_c210.c
+++ b/arch/arm/mach-exynos4/mach-universal_c210.c
@@ -13,6 +13,7 @@
 #include <linux/i2c.h>
 #include <linux/gpio_keys.h>
 #include <linux/gpio.h>
+#include <linux/fb.h>
 #include <linux/mfd/max8998.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
@@ -31,12 +32,21 @@
 #include <plat/devs.h>
 #include <plat/iic.h>
 #include <plat/gpio-cfg.h>
+#include <plat/fb.h>
 #include <plat/mfc.h>
 #include <plat/sdhci.h>
 #include <plat/pd.h>
+#include <plat/regs-fb-v4.h>
+#include <plat/fimc-core.h>
+#include <plat/camport.h>
+#include <plat/mipi_csis.h>
 
 #include <mach/map.h>
 
+#include <media/v4l2-mediabus.h>
+#include <media/s5p_fimc.h>
+#include <media/m5mols.h>
+
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define UNIVERSAL_UCON_DEFAULT  (S3C2410_UCON_TXILEVEL |        \
                                  S3C2410_UCON_RXILEVEL |        \
@@ -110,6 +120,9 @@ static struct regulator_consumer_supply lp3974_buck1_consumer =
 static struct regulator_consumer_supply lp3974_buck2_consumer =
         REGULATOR_SUPPLY("vddg3d", NULL);
 
+static struct regulator_consumer_supply lp3974_buck3_consumer =
+        REGULATOR_SUPPLY("vdet", "s5p-sdo");
+
 static struct regulator_init_data lp3974_buck1_data = {
         .constraints    = {
                 .name           = "VINT_1.1V",
@@ -153,6 +166,8 @@ static struct regulator_init_data lp3974_buck3_data = {
                         .enabled        = 1,
                 },
         },
+        .num_consumer_supplies = 1,
+        .consumer_supplies = &lp3974_buck3_consumer,
 };
 
 static struct regulator_init_data lp3974_buck4_data = {
@@ -181,6 +196,12 @@ static struct regulator_init_data lp3974_ldo2_data = {
         },
 };
 
+static struct regulator_consumer_supply lp3974_ldo3_consumer[] = {
+        REGULATOR_SUPPLY("vdd", "exynos4-hdmi"),
+        REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"),
+        REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"),
+};
+
 static struct regulator_init_data lp3974_ldo3_data = {
         .constraints    = {
                 .name           = "VUSB+MIPI_1.1V",
@@ -192,6 +213,12 @@ static struct regulator_init_data lp3974_ldo3_data = {
                         .disabled       = 1,
                 },
         },
+        .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo3_consumer),
+        .consumer_supplies = lp3974_ldo3_consumer,
+};
+
+static struct regulator_consumer_supply lp3974_ldo4_consumer[] = {
+        REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"),
 };
 
 static struct regulator_init_data lp3974_ldo4_data = {
@@ -205,6 +232,8 @@ static struct regulator_init_data lp3974_ldo4_data = {
                         .disabled       = 1,
                 },
         },
+        .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo4_consumer),
+        .consumer_supplies = lp3974_ldo4_consumer,
 };
 
 static struct regulator_init_data lp3974_ldo5_data = {
@@ -233,6 +262,10 @@ static struct regulator_init_data lp3974_ldo6_data = {
         },
 };
 
+static struct regulator_consumer_supply lp3974_ldo7_consumer[] = {
+        REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"),
+};
+
 static struct regulator_init_data lp3974_ldo7_data = {
         .constraints    = {
                 .name           = "VLCD+VMIPI_1.8V",
@@ -244,6 +277,12 @@ static struct regulator_init_data lp3974_ldo7_data = {
                         .disabled       = 1,
                 },
         },
+        .num_consumer_supplies  = ARRAY_SIZE(lp3974_ldo7_consumer),
+        .consumer_supplies      = lp3974_ldo7_consumer,
+};
+
+static struct regulator_consumer_supply lp3974_ldo8_consumer[] = {
+        REGULATOR_SUPPLY("vdd33a_dac", "s5p-sdo"),
 };
 
 static struct regulator_init_data lp3974_ldo8_data = {
@@ -257,6 +296,8 @@ static struct regulator_init_data lp3974_ldo8_data = {
                         .disabled       = 1,
                 },
         },
+        .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo8_consumer),
+        .consumer_supplies = lp3974_ldo8_consumer,
 };
 
 static struct regulator_init_data lp3974_ldo9_data = {
@@ -286,6 +327,9 @@ static struct regulator_init_data lp3974_ldo10_data = {
         },
 };
 
+static struct regulator_consumer_supply lp3974_ldo11_consumer =
+        REGULATOR_SUPPLY("dig_28", "0-001f");
+
 static struct regulator_init_data lp3974_ldo11_data = {
         .constraints    = {
                 .name           = "CAM_AF_3.3V",
@@ -297,6 +341,8 @@ static struct regulator_init_data lp3974_ldo11_data = {
                         .disabled       = 1,
                 },
         },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &lp3974_ldo11_consumer,
 };
 
 static struct regulator_init_data lp3974_ldo12_data = {
@@ -325,6 +371,9 @@ static struct regulator_init_data lp3974_ldo13_data = {
         },
 };
 
+static struct regulator_consumer_supply lp3974_ldo14_consumer =
+        REGULATOR_SUPPLY("dig_18", "0-001f");
+
 static struct regulator_init_data lp3974_ldo14_data = {
         .constraints    = {
                 .name           = "CAM_I_HOST_1.8V",
@@ -336,8 +385,14 @@ static struct regulator_init_data lp3974_ldo14_data = {
                         .disabled       = 1,
                 },
         },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &lp3974_ldo14_consumer,
 };
 
+
+static struct regulator_consumer_supply lp3974_ldo15_consumer =
+        REGULATOR_SUPPLY("dig_12", "0-001f");
+
 static struct regulator_init_data lp3974_ldo15_data = {
         .constraints    = {
                 .name           = "CAM_S_DIG+FM33_CORE_1.2V",
@@ -349,6 +404,12 @@ static struct regulator_init_data lp3974_ldo15_data = {
                         .disabled       = 1,
                 },
         },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &lp3974_ldo15_consumer,
+};
+
+static struct regulator_consumer_supply lp3974_ldo16_consumer[] = {
+        REGULATOR_SUPPLY("a_sensor", "0-001f"),
 };
 
 static struct regulator_init_data lp3974_ldo16_data = {
@@ -362,6 +423,8 @@ static struct regulator_init_data lp3974_ldo16_data = {
                         .disabled       = 1,
                 },
         },
+        .num_consumer_supplies  = ARRAY_SIZE(lp3974_ldo16_consumer),
+        .consumer_supplies      = lp3974_ldo16_consumer,
 };
 
 static struct regulator_init_data lp3974_ldo17_data = {
@@ -472,6 +535,43 @@ static struct max8998_platform_data universal_lp3974_pdata = {
         .wakeup                 = true,
 };
 
+
+enum fixed_regulator_id {
+        FIXED_REG_ID_MMC0,
+        FIXED_REG_ID_HDMI_5V,
+        FIXED_REG_ID_CAM_S_IF,
+        FIXED_REG_ID_CAM_I_CORE,
+        FIXED_REG_ID_CAM_VT_DIO,
+};
+
+static struct regulator_consumer_supply hdmi_fixed_consumer =
+        REGULATOR_SUPPLY("hdmi-en", "exynos4-hdmi");
+
+static struct regulator_init_data hdmi_fixed_voltage_init_data = {
+        .constraints            = {
+                .name           = "HDMI_5V",
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &hdmi_fixed_consumer,
+};
+
+static struct fixed_voltage_config hdmi_fixed_voltage_config = {
+        .supply_name            = "HDMI_EN1",
+        .microvolts             = 5000000,
+        .gpio                   = EXYNOS4_GPE0(1),
+        .enable_high            = true,
+        .init_data              = &hdmi_fixed_voltage_init_data,
+};
+
+static struct platform_device hdmi_fixed_voltage = {
+        .name                   = "reg-fixed-voltage",
+        .id                     = FIXED_REG_ID_HDMI_5V,
+        .dev                    = {
+                .platform_data  = &hdmi_fixed_voltage_config,
+        },
+};
+
 /* GPIO I2C 5 (PMIC) */
 static struct i2c_board_info i2c5_devs[] __initdata = {
         {
@@ -573,6 +673,11 @@ static void __init universal_touchkey_init(void)
         gpio_direction_output(gpio, 1);
 }
 
+static struct s3c2410_platform_i2c universal_i2c0_platdata __initdata = {
+        .frequency      = 300 * 1000,
+        .sda_delay      = 200,
+};
+
 /* GPIO KEYS */
 static struct gpio_keys_button universal_gpio_keys_tables[] = {
         {
@@ -658,7 +763,7 @@ static struct fixed_voltage_config mmc0_fixed_voltage_config = {
 
 static struct platform_device mmc0_fixed_voltage = {
         .name                   = "reg-fixed-voltage",
-        .id                     = 0,
+        .id                     = FIXED_REG_ID_MMC0,
         .dev                    = {
                 .platform_data  = &mmc0_fixed_voltage_config,
         },
@@ -692,18 +797,170 @@ static void __init universal_sdhci_init(void)
         s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
 }
 
-/* I2C0 */
-static struct i2c_board_info i2c0_devs[] __initdata = {
-        /* Camera, To be updated */
-};
-
 /* I2C1 */
 static struct i2c_board_info i2c1_devs[] __initdata = {
         /* Gyro, To be updated */
 };
 
+/* Frame Buffer */
+static struct s3c_fb_pd_win universal_fb_win0 = {
+        .win_mode = {
+                .left_margin    = 16,
+                .right_margin   = 16,
+                .upper_margin   = 2,
+                .lower_margin   = 28,
+                .hsync_len      = 2,
+                .vsync_len      = 1,
+                .xres           = 480,
+                .yres           = 800,
+                .refresh        = 55,
+        },
+        .max_bpp        = 32,
+        .default_bpp    = 16,
+};
+
+static struct s3c_fb_platdata universal_lcd_pdata __initdata = {
+        .win[0]         = &universal_fb_win0,
+        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
+                          VIDCON0_CLKSEL_LCD,
+        .vidcon1        = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
+                          | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+        .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
+};
+
+static struct regulator_consumer_supply cam_i_core_supply =
+        REGULATOR_SUPPLY("core", "0-001f");
+
+static struct regulator_init_data cam_i_core_reg_init_data = {
+        .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
+        .num_consumer_supplies = 1,
+        .consumer_supplies = &cam_i_core_supply,
+};
+
+static struct fixed_voltage_config cam_i_core_fixed_voltage_cfg = {
+        .supply_name    = "CAM_I_CORE_1.2V",
+        .microvolts     = 1200000,
+        .gpio           = EXYNOS4_GPE2(2),      /* CAM_8M_CORE_EN */
+        .enable_high    = 1,
+        .init_data      = &cam_i_core_reg_init_data,
+};
+
+static struct platform_device cam_i_core_fixed_reg_dev = {
+        .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_I_CORE,
+        .dev = { .platform_data = &cam_i_core_fixed_voltage_cfg },
+};
+
+static struct regulator_consumer_supply cam_s_if_supply =
+        REGULATOR_SUPPLY("d_sensor", "0-001f");
+
+static struct regulator_init_data cam_s_if_reg_init_data = {
+        .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
+        .num_consumer_supplies = 1,
+        .consumer_supplies = &cam_s_if_supply,
+};
+
+static struct fixed_voltage_config cam_s_if_fixed_voltage_cfg = {
+        .supply_name    = "CAM_S_IF_1.8V",
+        .microvolts     = 1800000,
+        .gpio           = EXYNOS4_GPE3(0),      /* CAM_PWR_EN1 */
+        .enable_high    = 1,
+        .init_data      = &cam_s_if_reg_init_data,
+};
+
+static struct platform_device cam_s_if_fixed_reg_dev = {
+        .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_S_IF,
+        .dev = { .platform_data = &cam_s_if_fixed_voltage_cfg },
+};
+
+static struct s5p_platform_mipi_csis mipi_csis_platdata = {
+        .clk_rate       = 166000000UL,
+        .lanes          = 2,
+        .alignment      = 32,
+        .hs_settle      = 12,
+        .phy_enable     = s5p_csis_phy_enable,
+};
+
+#define GPIO_CAM_LEVEL_EN(n)    EXYNOS4_GPE4(n + 3)
+#define GPIO_CAM_8M_ISP_INT     EXYNOS4_GPX1(5) /* XEINT_13 */
+#define GPIO_CAM_MEGA_nRST      EXYNOS4_GPE2(5)
+
+static int m5mols_set_power(struct device *dev, int on)
+{
+        gpio_set_value(GPIO_CAM_LEVEL_EN(1), !on);
+        gpio_set_value(GPIO_CAM_LEVEL_EN(2), !!on);
+        return 0;
+}
+
+static struct m5mols_platform_data m5mols_platdata = {
+        .gpio_reset     = GPIO_CAM_MEGA_nRST,
+        .reset_polarity = 0,
+        .set_power      = m5mols_set_power,
+};
+
+static struct i2c_board_info m5mols_board_info = {
+        I2C_BOARD_INFO("M5MOLS", 0x1F),
+        .platform_data = &m5mols_platdata,
+};
+
+static struct s5p_fimc_isp_info universal_camera_sensors[] = {
+        {
+                .mux_id         = 0,
+                .flags          = V4L2_MBUS_PCLK_SAMPLE_FALLING |
+                                  V4L2_MBUS_VSYNC_ACTIVE_LOW,
+                .bus_type       = FIMC_MIPI_CSI2,
+                .board_info     = &m5mols_board_info,
+                .i2c_bus_num    = 0,
+                .clk_frequency  = 21600000UL,
+                .csi_data_align = 32,
+        },
+};
+
+static struct s5p_platform_fimc fimc_md_platdata = {
+        .isp_info       = universal_camera_sensors,
+        .num_clients    = ARRAY_SIZE(universal_camera_sensors),
+};
+
+struct platform_device s5p_device_fimc_md = {
+        .name   = "s5p-fimc-md",
+        .id     = -1,
+};
+
+static struct gpio universal_camera_gpios[] = {
+        { GPIO_CAM_LEVEL_EN(1), GPIOF_OUT_INIT_HIGH, "CAM_LVL_EN1" },
+        { GPIO_CAM_LEVEL_EN(2), GPIOF_OUT_INIT_LOW,  "CAM_LVL_EN2" },
+        { GPIO_CAM_8M_ISP_INT,  GPIOF_IN,            "8M_ISP_INT"  },
+        { GPIO_CAM_MEGA_nRST,   GPIOF_OUT_INIT_LOW,  "CAM_8M_NRST" },
+};
+
+static void universal_camera_init(void)
+{
+        s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
+                         &s5p_device_mipi_csis0);
+        s3c_set_platdata(&fimc_md_platdata,  sizeof(fimc_md_platdata),
+                         &s5p_device_fimc_md);
+
+        if (gpio_request_array(universal_camera_gpios,
+                               ARRAY_SIZE(universal_camera_gpios))) {
+                pr_err("%s: GPIO request failed\n", __func__);
+                return;
+        }
+
+        if (!s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xf)))
+                m5mols_board_info.irq = gpio_to_irq(GPIO_CAM_8M_ISP_INT);
+        else
+                pr_err("Failed to configure 8M_ISP_INT GPIO\n");
+
+        /* Free GPIOs controlled directly by the sensor drivers. */
+        gpio_free(GPIO_CAM_MEGA_nRST);
+        gpio_free(GPIO_CAM_8M_ISP_INT);
+
+        if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A))
+                pr_err("Camera port A setup failed\n");
+}
+
 static struct platform_device *universal_devices[] __initdata = {
         /* Samsung Platform Devices */
+        &s5p_device_mipi_csis0,
         &s5p_device_fimc0,
         &s5p_device_fimc1,
         &s5p_device_fimc2,
@@ -712,17 +969,30 @@ static struct platform_device *universal_devices[] __initdata = {
         &s3c_device_hsmmc0,
         &s3c_device_hsmmc2,
         &s3c_device_hsmmc3,
+        &s3c_device_i2c0,
         &s3c_device_i2c3,
         &s3c_device_i2c5,
+        &s5p_device_i2c_hdmiphy,
+        &hdmi_fixed_voltage,
+        &exynos4_device_pd[PD_TV],
+        &s5p_device_hdmi,
+        &s5p_device_sdo,
+        &s5p_device_mixer,
 
         /* Universal Devices */
         &i2c_gpio12,
         &universal_gpio_keys,
         &s5p_device_onenand,
+        &s5p_device_fimd0,
         &s5p_device_mfc,
         &s5p_device_mfc_l,
         &s5p_device_mfc_r,
         &exynos4_device_pd[PD_MFC],
+        &exynos4_device_pd[PD_LCD0],
+        &exynos4_device_pd[PD_CAM],
+        &cam_i_core_fixed_reg_dev,
+        &cam_s_if_fixed_reg_dev,
+        &s5p_device_fimc_md,
 };
 
 static void __init universal_map_io(void)
@@ -732,6 +1002,20 @@ static void __init universal_map_io(void)
         s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
 }
 
+void s5p_tv_setup(void)
+{
+        /* direct HPD to HDMI chip */
+        gpio_request(EXYNOS4_GPX3(7), "hpd-plug");
+
+        gpio_direction_input(EXYNOS4_GPX3(7));
+        s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
+        s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
+
+        /* setup dependencies between TV devices */
+        s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
+        s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
+}
+
 static void __init universal_reserve(void)
 {
         s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
@@ -740,8 +1024,9 @@ static void __init universal_reserve(void)
 static void __init universal_machine_init(void)
 {
         universal_sdhci_init();
+        s5p_tv_setup();
 
-        i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
+        s3c_i2c0_set_platdata(&universal_i2c0_platdata);
         i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
 
         universal_tsp_init();
@@ -749,15 +1034,28 @@ static void __init universal_machine_init(void)
         i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
 
         s3c_i2c5_set_platdata(NULL);
+        s5p_i2c_hdmiphy_set_platdata(NULL);
         i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
 
+        s5p_fimd0_set_platdata(&universal_lcd_pdata);
+
         universal_touchkey_init();
         i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs,
                         ARRAY_SIZE(i2c_gpio12_devs));
 
+        universal_camera_init();
+
         /* Last */
         platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
+
         s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
+        s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
+
+        s5p_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+        s5p_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+        s5p_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+        s5p_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
+        s5p_device_mipi_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
 }
 
 MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
diff --git a/arch/arm/mach-exynos4/mct.c b/arch/arm/mach-exynos4/mct.c
index 1ae059b7ad7b..eb182f29f48f 100644
--- a/arch/arm/mach-exynos4/mct.c
+++ b/arch/arm/mach-exynos4/mct.c
@@ -20,19 +20,31 @@
 #include <linux/delay.h>
 #include <linux/percpu.h>
 
+#include <asm/hardware/gic.h>
+
+#include <plat/cpu.h>
+
 #include <mach/map.h>
+#include <mach/irqs.h>
 #include <mach/regs-mct.h>
 #include <asm/mach/time.h>
 
+enum {
+        MCT_INT_SPI,
+        MCT_INT_PPI
+};
+
 static unsigned long clk_cnt_per_tick;
 static unsigned long clk_rate;
+static unsigned int mct_int_type;
 
 struct mct_clock_event_device {
         struct clock_event_device *evt;
         void __iomem *base;
+        char name[10];
 };
 
-struct mct_clock_event_device mct_tick[2];
+struct mct_clock_event_device mct_tick[NR_CPUS];
 
 static void exynos4_mct_write(unsigned int value, void *addr)
 {
@@ -42,57 +54,53 @@ static void exynos4_mct_write(unsigned int value, void *addr)
 
         __raw_writel(value, addr);
 
-        switch ((u32) addr) {
-        case (u32) EXYNOS4_MCT_G_TCON:
-                stat_addr = EXYNOS4_MCT_G_WSTAT;
-                mask = 1 << 16;         /* G_TCON write status */
-                break;
-        case (u32) EXYNOS4_MCT_G_COMP0_L:
-                stat_addr = EXYNOS4_MCT_G_WSTAT;
-                mask = 1 << 0;          /* G_COMP0_L write status */
-                break;
-        case (u32) EXYNOS4_MCT_G_COMP0_U:
-                stat_addr = EXYNOS4_MCT_G_WSTAT;
-                mask = 1 << 1;          /* G_COMP0_U write status */
-                break;
-        case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
-                stat_addr = EXYNOS4_MCT_G_WSTAT;
-                mask = 1 << 2;          /* G_COMP0_ADD_INCR write status */
-                break;
-        case (u32) EXYNOS4_MCT_G_CNT_L:
-                stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
-                mask = 1 << 0;          /* G_CNT_L write status */
-                break;
-        case (u32) EXYNOS4_MCT_G_CNT_U:
-                stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
-                mask = 1 << 1;          /* G_CNT_U write status */
-                break;
-        case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCON_OFFSET):
-                stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
-                mask = 1 << 3;          /* L0_TCON write status */
-                break;
-        case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCON_OFFSET):
-                stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
-                mask = 1 << 3;          /* L1_TCON write status */
-                break;
-        case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCNTB_OFFSET):
-                stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
-                mask = 1 << 0;          /* L0_TCNTB write status */
-                break;
-        case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCNTB_OFFSET):
-                stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
-                mask = 1 << 0;          /* L1_TCNTB write status */
-                break;
-        case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_ICNTB_OFFSET):
-                stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
-                mask = 1 << 1;          /* L0_ICNTB write status */
-                break;
-        case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_ICNTB_OFFSET):
-                stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
-                mask = 1 << 1;          /* L1_ICNTB write status */
-                break;
-        default:
-                return;
+        if (likely(addr >= EXYNOS4_MCT_L_BASE(0))) {
+                u32 base = (u32) addr & EXYNOS4_MCT_L_MASK;
+                switch ((u32) addr & ~EXYNOS4_MCT_L_MASK) {
+                case (u32) MCT_L_TCON_OFFSET:
+                        stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
+                        mask = 1 << 3;          /* L_TCON write status */
+                        break;
+                case (u32) MCT_L_ICNTB_OFFSET:
+                        stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
+                        mask = 1 << 1;          /* L_ICNTB write status */
+                        break;
+                case (u32) MCT_L_TCNTB_OFFSET:
+                        stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
+                        mask = 1 << 0;          /* L_TCNTB write status */
+                        break;
+                default:
+                        return;
+                }
+        } else {
+                switch ((u32) addr) {
+                case (u32) EXYNOS4_MCT_G_TCON:
+                        stat_addr = EXYNOS4_MCT_G_WSTAT;
+                        mask = 1 << 16;         /* G_TCON write status */
+                        break;
+                case (u32) EXYNOS4_MCT_G_COMP0_L:
+                        stat_addr = EXYNOS4_MCT_G_WSTAT;
+                        mask = 1 << 0;          /* G_COMP0_L write status */
+                        break;
+                case (u32) EXYNOS4_MCT_G_COMP0_U:
+                        stat_addr = EXYNOS4_MCT_G_WSTAT;
+                        mask = 1 << 1;          /* G_COMP0_U write status */
+                        break;
+                case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
+                        stat_addr = EXYNOS4_MCT_G_WSTAT;
+                        mask = 1 << 2;          /* G_COMP0_ADD_INCR w status */
+                        break;
+                case (u32) EXYNOS4_MCT_G_CNT_L:
+                        stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
+                        mask = 1 << 0;          /* G_CNT_L write status */
+                        break;
+                case (u32) EXYNOS4_MCT_G_CNT_U:
+                        stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
+                        mask = 1 << 1;          /* G_CNT_U write status */
+                        break;
+                default:
+                        return;
+                }
         }
 
         /* Wait maximum 1 ms until written values are applied */
@@ -132,12 +140,18 @@ static cycle_t exynos4_frc_read(struct clocksource *cs)
         return ((cycle_t)hi << 32) | lo;
 }
 
+static void exynos4_frc_resume(struct clocksource *cs)
+{
+        exynos4_mct_frc_start(0, 0);
+}
+
 struct clocksource mct_frc = {
         .name           = "mct-frc",
         .rating         = 400,
         .read           = exynos4_frc_read,
         .mask           = CLOCKSOURCE_MASK(64),
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+        .resume         = exynos4_frc_resume,
 };
 
 static void __init exynos4_clocksource_init(void)
@@ -315,9 +329,8 @@ static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
         }
 }
 
-static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
+static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
 {
-        struct mct_clock_event_device *mevt = dev_id;
         struct clock_event_device *evt = mevt->evt;
 
         /*
@@ -329,7 +342,20 @@ static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
                 exynos4_mct_tick_stop(mevt);
 
         /* Clear the MCT tick interrupt */
-        exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
+        if (__raw_readl(mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
+                exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
+                return 1;
+        } else {
+                return 0;
+        }
+}
+
+static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
+{
+        struct mct_clock_event_device *mevt = dev_id;
+        struct clock_event_device *evt = mevt->evt;
+
+        exynos4_mct_tick_clear(mevt);
 
         evt->event_handler(evt);
 
@@ -354,14 +380,10 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
 
         mct_tick[cpu].evt = evt;
 
-        if (cpu == 0) {
-                mct_tick[cpu].base = EXYNOS4_MCT_L0_BASE;
-                evt->name = "mct_tick0";
-        } else {
-                mct_tick[cpu].base = EXYNOS4_MCT_L1_BASE;
-                evt->name = "mct_tick1";
-        }
+        mct_tick[cpu].base = EXYNOS4_MCT_L_BASE(cpu);
+        sprintf(mct_tick[cpu].name, "mct_tick%d", cpu);
 
+        evt->name = mct_tick[cpu].name;
         evt->cpumask = cpumask_of(cpu);
         evt->set_next_event = exynos4_tick_set_next_event;
         evt->set_mode = exynos4_tick_set_mode;
@@ -378,25 +400,34 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
 
         exynos4_mct_write(0x1, mct_tick[cpu].base + MCT_L_TCNTB_OFFSET);
 
-        if (cpu == 0) {
-                mct_tick0_event_irq.dev_id = &mct_tick[cpu];
-                setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
+        if (mct_int_type == MCT_INT_SPI) {
+                if (cpu == 0) {
+                        mct_tick0_event_irq.dev_id = &mct_tick[cpu];
+                        setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
+                } else {
+                        mct_tick1_event_irq.dev_id = &mct_tick[cpu];
+                        setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
+                        irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
+                }
         } else {
-                mct_tick1_event_irq.dev_id = &mct_tick[cpu];
-                setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
-                irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
+                gic_enable_ppi(IRQ_MCT_LOCALTIMER);
         }
 }
 
 /* Setup the local clock events for a CPU */
-void __cpuinit local_timer_setup(struct clock_event_device *evt)
+int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
         exynos4_mct_tick_init(evt);
+
+        return 0;
 }
 
 int local_timer_ack(void)
 {
-        return 0;
+        unsigned int cpu = smp_processor_id();
+        struct mct_clock_event_device *mevt = &mct_tick[cpu];
+
+        return exynos4_mct_tick_clear(mevt);
 }
 
 #endif /* CONFIG_LOCAL_TIMERS */
@@ -411,6 +442,11 @@ static void __init exynos4_timer_resources(void)
 
 static void __init exynos4_timer_init(void)
 {
+        if (soc_is_exynos4210())
+                mct_int_type = MCT_INT_SPI;
+        else
+                mct_int_type = MCT_INT_PPI;
+
         exynos4_timer_resources();
         exynos4_clocksource_init();
         exynos4_clockevent_init();
diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c
index 7c2282c6ba81..d5f0f299ba0d 100644
--- a/arch/arm/mach-exynos4/platsmp.c
+++ b/arch/arm/mach-exynos4/platsmp.c
@@ -30,9 +30,13 @@
 #include <mach/regs-clock.h>
 #include <mach/regs-pmu.h>
 
+#include <plat/cpu.h>
+
+extern unsigned int gic_bank_offset;
 extern void exynos4_secondary_startup(void);
 
-#define CPU1_BOOT_REG S5P_VA_SYSRAM
+#define CPU1_BOOT_REG           (samsung_rev() == EXYNOS4210_REV_1_1 ? \
+                                S5P_INFORM5 : S5P_VA_SYSRAM)
 
 /*
  * control for which core is the next to come out of the secondary
@@ -64,9 +68,9 @@ static DEFINE_SPINLOCK(boot_lock);
 static void __cpuinit exynos4_gic_secondary_init(void)
 {
         void __iomem *dist_base = S5P_VA_GIC_DIST +
-                                 (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
+                                (gic_bank_offset * smp_processor_id());
         void __iomem *cpu_base = S5P_VA_GIC_CPU +
-                                (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
+                                (gic_bank_offset * smp_processor_id());
         int i;
 
         /*
@@ -106,6 +110,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
          */
         spin_lock(&boot_lock);
         spin_unlock(&boot_lock);
+
+        set_cpu_online(cpu, true);
 }
 
 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
@@ -216,5 +222,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
          * until it receives a soft interrupt, and then the
          * secondary CPU branches to this address.
          */
-        __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), S5P_VA_SYSRAM);
+        __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
+                        CPU1_BOOT_REG);
 }
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index bc6ca9482de1..509a435afd4b 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -41,7 +41,6 @@ static struct sleep_save exynos4_set_clksrc[] = {
         { .reg = S5P_CLKSRC_MASK_CAM                    , .val = 0x11111111, },
         { .reg = S5P_CLKSRC_MASK_TV                     , .val = 0x00000111, },
         { .reg = S5P_CLKSRC_MASK_LCD0                   , .val = 0x00001111, },
-        { .reg = S5P_CLKSRC_MASK_LCD1                   , .val = 0x00001111, },
         { .reg = S5P_CLKSRC_MASK_MAUDIO                 , .val = 0x00000001, },
         { .reg = S5P_CLKSRC_MASK_FSYS                   , .val = 0x01011111, },
         { .reg = S5P_CLKSRC_MASK_PERIL0                 , .val = 0x01111111, },
@@ -49,6 +48,10 @@ static struct sleep_save exynos4_set_clksrc[] = {
         { .reg = S5P_CLKSRC_MASK_DMC                    , .val = 0x00010000, },
 };
 
+static struct sleep_save exynos4210_set_clksrc[] = {
+        { .reg = S5P_CLKSRC_MASK_LCD1                   , .val = 0x00001111, },
+};
+
 static struct sleep_save exynos4_epll_save[] = {
         SAVE_ITEM(S5P_EPLL_CON0),
         SAVE_ITEM(S5P_EPLL_CON1),
@@ -60,77 +63,6 @@ static struct sleep_save exynos4_vpll_save[] = {
 };
 
 static struct sleep_save exynos4_core_save[] = {
-        /* CMU side */
-        SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
-        SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
-        SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
-        SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
-        SAVE_ITEM(S5P_CLKSRC_TOP0),
-        SAVE_ITEM(S5P_CLKSRC_TOP1),
-        SAVE_ITEM(S5P_CLKSRC_CAM),
-        SAVE_ITEM(S5P_CLKSRC_TV),
-        SAVE_ITEM(S5P_CLKSRC_MFC),
-        SAVE_ITEM(S5P_CLKSRC_G3D),
-        SAVE_ITEM(S5P_CLKSRC_IMAGE),
-        SAVE_ITEM(S5P_CLKSRC_LCD0),
-        SAVE_ITEM(S5P_CLKSRC_LCD1),
-        SAVE_ITEM(S5P_CLKSRC_MAUDIO),
-        SAVE_ITEM(S5P_CLKSRC_FSYS),
-        SAVE_ITEM(S5P_CLKSRC_PERIL0),
-        SAVE_ITEM(S5P_CLKSRC_PERIL1),
-        SAVE_ITEM(S5P_CLKDIV_CAM),
-        SAVE_ITEM(S5P_CLKDIV_TV),
-        SAVE_ITEM(S5P_CLKDIV_MFC),
-        SAVE_ITEM(S5P_CLKDIV_G3D),
-        SAVE_ITEM(S5P_CLKDIV_IMAGE),
-        SAVE_ITEM(S5P_CLKDIV_LCD0),
-        SAVE_ITEM(S5P_CLKDIV_LCD1),
-        SAVE_ITEM(S5P_CLKDIV_MAUDIO),
-        SAVE_ITEM(S5P_CLKDIV_FSYS0),
-        SAVE_ITEM(S5P_CLKDIV_FSYS1),
-        SAVE_ITEM(S5P_CLKDIV_FSYS2),
-        SAVE_ITEM(S5P_CLKDIV_FSYS3),
-        SAVE_ITEM(S5P_CLKDIV_PERIL0),
-        SAVE_ITEM(S5P_CLKDIV_PERIL1),
-        SAVE_ITEM(S5P_CLKDIV_PERIL2),
-        SAVE_ITEM(S5P_CLKDIV_PERIL3),
-        SAVE_ITEM(S5P_CLKDIV_PERIL4),
-        SAVE_ITEM(S5P_CLKDIV_PERIL5),
-        SAVE_ITEM(S5P_CLKDIV_TOP),
-        SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
-        SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
-        SAVE_ITEM(S5P_CLKSRC_MASK_TV),
-        SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
-        SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
-        SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
-        SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
-        SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
-        SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
-        SAVE_ITEM(S5P_CLKDIV2_RATIO),
-        SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
-        SAVE_ITEM(S5P_CLKGATE_IP_CAM),
-        SAVE_ITEM(S5P_CLKGATE_IP_TV),
-        SAVE_ITEM(S5P_CLKGATE_IP_MFC),
-        SAVE_ITEM(S5P_CLKGATE_IP_G3D),
-        SAVE_ITEM(S5P_CLKGATE_IP_IMAGE),
-        SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
-        SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
-        SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
-        SAVE_ITEM(S5P_CLKGATE_IP_GPS),
-        SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
-        SAVE_ITEM(S5P_CLKGATE_IP_PERIR),
-        SAVE_ITEM(S5P_CLKGATE_BLOCK),
-        SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
-        SAVE_ITEM(S5P_CLKSRC_DMC),
-        SAVE_ITEM(S5P_CLKDIV_DMC0),
-        SAVE_ITEM(S5P_CLKDIV_DMC1),
-        SAVE_ITEM(S5P_CLKGATE_IP_DMC),
-        SAVE_ITEM(S5P_CLKSRC_CPU),
-        SAVE_ITEM(S5P_CLKDIV_CPU),
-        SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
-        SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
-        SAVE_ITEM(S5P_CLKGATE_IP_CPU),
-
         /* GIC side */
         SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
         SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
@@ -268,6 +200,9 @@ static void exynos4_pm_prepare(void)
 
         s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
 
+        if (soc_is_exynos4210())
+                s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
+
 }
 
 static int exynos4_pm_add(struct sys_device *sysdev)
@@ -404,6 +339,13 @@ static int exynos4_pm_suspend(void)
         tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
         __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 
+        if (soc_is_exynos4212()) {
+                tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
+                tmp &= ~(S5P_USE_STANDBYWFI_ISP_ARM |
+                         S5P_USE_STANDBYWFE_ISP_ARM);
+                __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
+        }
+
         /* Save Power control register */
         asm ("mrc p15, 0, %0, c15, c0, 0"
              : "=r" (tmp) : : "cc");
diff --git a/arch/arm/mach-exynos4/pmu.c b/arch/arm/mach-exynos4/pmu.c
index 7ea9eb2a20d2..bba48f5c3e8f 100644
--- a/arch/arm/mach-exynos4/pmu.c
+++ b/arch/arm/mach-exynos4/pmu.c
@@ -16,160 +16,215 @@
 #include <mach/regs-clock.h>
 #include <mach/pmu.h>
 
-static void __iomem *sys_powerdown_reg[] = {
-        S5P_ARM_CORE0_LOWPWR,
-        S5P_DIS_IRQ_CORE0,
-        S5P_DIS_IRQ_CENTRAL0,
-        S5P_ARM_CORE1_LOWPWR,
-        S5P_DIS_IRQ_CORE1,
-        S5P_DIS_IRQ_CENTRAL1,
-        S5P_ARM_COMMON_LOWPWR,
-        S5P_L2_0_LOWPWR,
-        S5P_L2_1_LOWPWR,
-        S5P_CMU_ACLKSTOP_LOWPWR,
-        S5P_CMU_SCLKSTOP_LOWPWR,
-        S5P_CMU_RESET_LOWPWR,
-        S5P_APLL_SYSCLK_LOWPWR,
-        S5P_MPLL_SYSCLK_LOWPWR,
-        S5P_VPLL_SYSCLK_LOWPWR,
-        S5P_EPLL_SYSCLK_LOWPWR,
-        S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,
-        S5P_CMU_RESET_GPSALIVE_LOWPWR,
-        S5P_CMU_CLKSTOP_CAM_LOWPWR,
-        S5P_CMU_CLKSTOP_TV_LOWPWR,
-        S5P_CMU_CLKSTOP_MFC_LOWPWR,
-        S5P_CMU_CLKSTOP_G3D_LOWPWR,
-        S5P_CMU_CLKSTOP_LCD0_LOWPWR,
-        S5P_CMU_CLKSTOP_LCD1_LOWPWR,
-        S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,
-        S5P_CMU_CLKSTOP_GPS_LOWPWR,
-        S5P_CMU_RESET_CAM_LOWPWR,
-        S5P_CMU_RESET_TV_LOWPWR,
-        S5P_CMU_RESET_MFC_LOWPWR,
-        S5P_CMU_RESET_G3D_LOWPWR,
-        S5P_CMU_RESET_LCD0_LOWPWR,
-        S5P_CMU_RESET_LCD1_LOWPWR,
-        S5P_CMU_RESET_MAUDIO_LOWPWR,
-        S5P_CMU_RESET_GPS_LOWPWR,
-        S5P_TOP_BUS_LOWPWR,
-        S5P_TOP_RETENTION_LOWPWR,
-        S5P_TOP_PWR_LOWPWR,
-        S5P_LOGIC_RESET_LOWPWR,
-        S5P_ONENAND_MEM_LOWPWR,
-        S5P_MODIMIF_MEM_LOWPWR,
-        S5P_G2D_ACP_MEM_LOWPWR,
-        S5P_USBOTG_MEM_LOWPWR,
-        S5P_HSMMC_MEM_LOWPWR,
-        S5P_CSSYS_MEM_LOWPWR,
-        S5P_SECSS_MEM_LOWPWR,
-        S5P_PCIE_MEM_LOWPWR,
-        S5P_SATA_MEM_LOWPWR,
-        S5P_PAD_RETENTION_DRAM_LOWPWR,
-        S5P_PAD_RETENTION_MAUDIO_LOWPWR,
-        S5P_PAD_RETENTION_GPIO_LOWPWR,
-        S5P_PAD_RETENTION_UART_LOWPWR,
-        S5P_PAD_RETENTION_MMCA_LOWPWR,
-        S5P_PAD_RETENTION_MMCB_LOWPWR,
-        S5P_PAD_RETENTION_EBIA_LOWPWR,
-        S5P_PAD_RETENTION_EBIB_LOWPWR,
-        S5P_PAD_RETENTION_ISOLATION_LOWPWR,
-        S5P_PAD_RETENTION_ALV_SEL_LOWPWR,
-        S5P_XUSBXTI_LOWPWR,
-        S5P_XXTI_LOWPWR,
-        S5P_EXT_REGULATOR_LOWPWR,
-        S5P_GPIO_MODE_LOWPWR,
-        S5P_GPIO_MODE_MAUDIO_LOWPWR,
-        S5P_CAM_LOWPWR,
-        S5P_TV_LOWPWR,
-        S5P_MFC_LOWPWR,
-        S5P_G3D_LOWPWR,
-        S5P_LCD0_LOWPWR,
-        S5P_LCD1_LOWPWR,
-        S5P_MAUDIO_LOWPWR,
-        S5P_GPS_LOWPWR,
-        S5P_GPS_ALIVE_LOWPWR,
+static struct exynos4_pmu_conf *exynos4_pmu_config;
+
+static struct exynos4_pmu_conf exynos4210_pmu_config[] = {
+        /* { .reg = address, .val = { AFTR, LPA, SLEEP } */
+        { S5P_ARM_CORE0_LOWPWR,                 { 0x0, 0x0, 0x2 } },
+        { S5P_DIS_IRQ_CORE0,                    { 0x0, 0x0, 0x0 } },
+        { S5P_DIS_IRQ_CENTRAL0,                 { 0x0, 0x0, 0x0 } },
+        { S5P_ARM_CORE1_LOWPWR,                 { 0x0, 0x0, 0x2 } },
+        { S5P_DIS_IRQ_CORE1,                    { 0x0, 0x0, 0x0 } },
+        { S5P_DIS_IRQ_CENTRAL1,                 { 0x0, 0x0, 0x0 } },
+        { S5P_ARM_COMMON_LOWPWR,                { 0x0, 0x0, 0x2 } },
+        { S5P_L2_0_LOWPWR,                      { 0x2, 0x2, 0x3 } },
+        { S5P_L2_1_LOWPWR,                      { 0x2, 0x2, 0x3 } },
+        { S5P_CMU_ACLKSTOP_LOWPWR,              { 0x1, 0x0, 0x0 } },
+        { S5P_CMU_SCLKSTOP_LOWPWR,              { 0x1, 0x0, 0x0 } },
+        { S5P_CMU_RESET_LOWPWR,                 { 0x1, 0x1, 0x0 } },
+        { S5P_APLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
+        { S5P_MPLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
+        { S5P_VPLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
+        { S5P_EPLL_SYSCLK_LOWPWR,               { 0x1, 0x1, 0x0 } },
+        { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,     { 0x1, 0x1, 0x0 } },
+        { S5P_CMU_RESET_GPSALIVE_LOWPWR,        { 0x1, 0x1, 0x0 } },
+        { S5P_CMU_CLKSTOP_CAM_LOWPWR,           { 0x1, 0x1, 0x0 } },
+        { S5P_CMU_CLKSTOP_TV_LOWPWR,            { 0x1, 0x1, 0x0 } },
+        { S5P_CMU_CLKSTOP_MFC_LOWPWR,           { 0x1, 0x1, 0x0 } },
+        { S5P_CMU_CLKSTOP_G3D_LOWPWR,           { 0x1, 0x1, 0x0 } },
+        { S5P_CMU_CLKSTOP_LCD0_LOWPWR,          { 0x1, 0x1, 0x0 } },
+        { S5P_CMU_CLKSTOP_LCD1_LOWPWR,          { 0x1, 0x1, 0x0 } },
+        { S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,        { 0x1, 0x1, 0x0 } },
+        { S5P_CMU_CLKSTOP_GPS_LOWPWR,           { 0x1, 0x1, 0x0 } },
+        { S5P_CMU_RESET_CAM_LOWPWR,             { 0x1, 0x1, 0x0 } },
+        { S5P_CMU_RESET_TV_LOWPWR,              { 0x1, 0x1, 0x0 } },
+        { S5P_CMU_RESET_MFC_LOWPWR,             { 0x1, 0x1, 0x0 } },
+        { S5P_CMU_RESET_G3D_LOWPWR,             { 0x1, 0x1, 0x0 } },
+        { S5P_CMU_RESET_LCD0_LOWPWR,            { 0x1, 0x1, 0x0 } },
+        { S5P_CMU_RESET_LCD1_LOWPWR,            { 0x1, 0x1, 0x0 } },
+        { S5P_CMU_RESET_MAUDIO_LOWPWR,          { 0x1, 0x1, 0x0 } },
+        { S5P_CMU_RESET_GPS_LOWPWR,             { 0x1, 0x1, 0x0 } },
+        { S5P_TOP_BUS_LOWPWR,                   { 0x3, 0x0, 0x0 } },
+        { S5P_TOP_RETENTION_LOWPWR,             { 0x1, 0x0, 0x1 } },
+        { S5P_TOP_PWR_LOWPWR,                   { 0x3, 0x0, 0x3 } },
+        { S5P_LOGIC_RESET_LOWPWR,               { 0x1, 0x1, 0x0 } },
+        { S5P_ONENAND_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
+        { S5P_MODIMIF_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
+        { S5P_G2D_ACP_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
+        { S5P_USBOTG_MEM_LOWPWR,                { 0x3, 0x0, 0x0 } },
+        { S5P_HSMMC_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
+        { S5P_CSSYS_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
+        { S5P_SECSS_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
+        { S5P_PCIE_MEM_LOWPWR,                  { 0x3, 0x0, 0x0 } },
+        { S5P_SATA_MEM_LOWPWR,                  { 0x3, 0x0, 0x0 } },
+        { S5P_PAD_RETENTION_DRAM_LOWPWR,        { 0x1, 0x0, 0x0 } },
+        { S5P_PAD_RETENTION_MAUDIO_LOWPWR,      { 0x1, 0x1, 0x0 } },
+        { S5P_PAD_RETENTION_GPIO_LOWPWR,        { 0x1, 0x0, 0x0 } },
+        { S5P_PAD_RETENTION_UART_LOWPWR,        { 0x1, 0x0, 0x0 } },
+        { S5P_PAD_RETENTION_MMCA_LOWPWR,        { 0x1, 0x0, 0x0 } },
+        { S5P_PAD_RETENTION_MMCB_LOWPWR,        { 0x1, 0x0, 0x0 } },
+        { S5P_PAD_RETENTION_EBIA_LOWPWR,        { 0x1, 0x0, 0x0 } },
+        { S5P_PAD_RETENTION_EBIB_LOWPWR,        { 0x1, 0x0, 0x0 } },
+        { S5P_PAD_RETENTION_ISOLATION_LOWPWR,   { 0x1, 0x0, 0x0 } },
+        { S5P_PAD_RETENTION_ALV_SEL_LOWPWR,     { 0x1, 0x0, 0x0 } },
+        { S5P_XUSBXTI_LOWPWR,                   { 0x1, 0x1, 0x0 } },
+        { S5P_XXTI_LOWPWR,                      { 0x1, 0x1, 0x0 } },
+        { S5P_EXT_REGULATOR_LOWPWR,             { 0x1, 0x1, 0x0 } },
+        { S5P_GPIO_MODE_LOWPWR,                 { 0x1, 0x0, 0x0 } },
+        { S5P_GPIO_MODE_MAUDIO_LOWPWR,          { 0x1, 0x1, 0x0 } },
+        { S5P_CAM_LOWPWR,                       { 0x7, 0x0, 0x0 } },
+        { S5P_TV_LOWPWR,                        { 0x7, 0x0, 0x0 } },
+        { S5P_MFC_LOWPWR,                       { 0x7, 0x0, 0x0 } },
+        { S5P_G3D_LOWPWR,                       { 0x7, 0x0, 0x0 } },
+        { S5P_LCD0_LOWPWR,                      { 0x7, 0x0, 0x0 } },
+        { S5P_LCD1_LOWPWR,                      { 0x7, 0x0, 0x0 } },
+        { S5P_MAUDIO_LOWPWR,                    { 0x7, 0x7, 0x0 } },
+        { S5P_GPS_LOWPWR,                       { 0x7, 0x0, 0x0 } },
+        { S5P_GPS_ALIVE_LOWPWR,                 { 0x7, 0x0, 0x0 } },
+        { PMU_TABLE_END,},
 };
 
-static const unsigned int sys_powerdown_val[][NUM_SYS_POWERDOWN] = {
-        /* { AFTR, LPA, SLEEP }*/
-        { 0, 0, 2 },    /* ARM_CORE0 */
-        { 0, 0, 0 },    /* ARM_DIS_IRQ_CORE0 */
-        { 0, 0, 0 },    /* ARM_DIS_IRQ_CENTRAL0 */
-        { 0, 0, 2 },    /* ARM_CORE1 */
-        { 0, 0, 0 },    /* ARM_DIS_IRQ_CORE1 */
-        { 0, 0, 0 },    /* ARM_DIS_IRQ_CENTRAL1 */
-        { 0, 0, 2 },    /* ARM_COMMON */
-        { 2, 2, 3 },    /* ARM_CPU_L2_0 */
-        { 2, 2, 3 },    /* ARM_CPU_L2_1 */
-        { 1, 0, 0 },    /* CMU_ACLKSTOP */
-        { 1, 0, 0 },    /* CMU_SCLKSTOP */
-        { 1, 1, 0 },    /* CMU_RESET */
-        { 1, 0, 0 },    /* APLL_SYSCLK */
-        { 1, 0, 0 },    /* MPLL_SYSCLK */
-        { 1, 0, 0 },    /* VPLL_SYSCLK */
-        { 1, 1, 0 },    /* EPLL_SYSCLK */
-        { 1, 1, 0 },    /* CMU_CLKSTOP_GPS_ALIVE */
-        { 1, 1, 0 },    /* CMU_RESET_GPS_ALIVE */
-        { 1, 1, 0 },    /* CMU_CLKSTOP_CAM */
-        { 1, 1, 0 },    /* CMU_CLKSTOP_TV */
-        { 1, 1, 0 },    /* CMU_CLKSTOP_MFC */
-        { 1, 1, 0 },    /* CMU_CLKSTOP_G3D */
-        { 1, 1, 0 },    /* CMU_CLKSTOP_LCD0 */
-        { 1, 1, 0 },    /* CMU_CLKSTOP_LCD1 */
-        { 1, 1, 0 },    /* CMU_CLKSTOP_MAUDIO */
-        { 1, 1, 0 },    /* CMU_CLKSTOP_GPS */
-        { 1, 1, 0 },    /* CMU_RESET_CAM */
-        { 1, 1, 0 },    /* CMU_RESET_TV */
-        { 1, 1, 0 },    /* CMU_RESET_MFC */
-        { 1, 1, 0 },    /* CMU_RESET_G3D */
-        { 1, 1, 0 },    /* CMU_RESET_LCD0 */
-        { 1, 1, 0 },    /* CMU_RESET_LCD1 */
-        { 1, 1, 0 },    /* CMU_RESET_MAUDIO */
-        { 1, 1, 0 },    /* CMU_RESET_GPS */
-        { 3, 0, 0 },    /* TOP_BUS */
-        { 1, 0, 1 },    /* TOP_RETENTION */
-        { 3, 0, 3 },    /* TOP_PWR */
-        { 1, 1, 0 },    /* LOGIC_RESET */
-        { 3, 0, 0 },    /* ONENAND_MEM */
-        { 3, 0, 0 },    /* MODIMIF_MEM */
-        { 3, 0, 0 },    /* G2D_ACP_MEM */
-        { 3, 0, 0 },    /* USBOTG_MEM */
-        { 3, 0, 0 },    /* HSMMC_MEM */
-        { 3, 0, 0 },    /* CSSYS_MEM */
-        { 3, 0, 0 },    /* SECSS_MEM */
-        { 3, 0, 0 },    /* PCIE_MEM */
-        { 3, 0, 0 },    /* SATA_MEM */
-        { 1, 0, 0 },    /* PAD_RETENTION_DRAM */
-        { 1, 1, 0 },    /* PAD_RETENTION_MAUDIO */
-        { 1, 0, 0 },    /* PAD_RETENTION_GPIO */
-        { 1, 0, 0 },    /* PAD_RETENTION_UART */
-        { 1, 0, 0 },    /* PAD_RETENTION_MMCA */
-        { 1, 0, 0 },    /* PAD_RETENTION_MMCB */
-        { 1, 0, 0 },    /* PAD_RETENTION_EBIA */
-        { 1, 0, 0 },    /* PAD_RETENTION_EBIB */
-        { 1, 0, 0 },    /* PAD_RETENTION_ISOLATION */
-        { 1, 0, 0 },    /* PAD_RETENTION_ALV_SEL */
-        { 1, 1, 0 },    /* XUSBXTI */
-        { 1, 1, 0 },    /* XXTI */
-        { 1, 1, 0 },    /* EXT_REGULATOR */
-        { 1, 0, 0 },    /* GPIO_MODE */
-        { 1, 1, 0 },    /* GPIO_MODE_MAUDIO */
-        { 7, 0, 0 },    /* CAM */
-        { 7, 0, 0 },    /* TV */
-        { 7, 0, 0 },    /* MFC */
-        { 7, 0, 0 },    /* G3D */
-        { 7, 0, 0 },    /* LCD0 */
-        { 7, 0, 0 },    /* LCD1 */
-        { 7, 7, 0 },    /* MAUDIO */
-        { 7, 0, 0 },    /* GPS */
-        { 7, 0, 0 },    /* GPS_ALIVE */
+static struct exynos4_pmu_conf exynos4212_pmu_config[] = {
+        { S5P_ARM_CORE0_LOWPWR,                 { 0x0, 0x0, 0x2 } },
+        { S5P_DIS_IRQ_CORE0,                    { 0x0, 0x0, 0x0 } },
+        { S5P_DIS_IRQ_CENTRAL0,                 { 0x0, 0x0, 0x0 } },
+        { S5P_ARM_CORE1_LOWPWR,                 { 0x0, 0x0, 0x2 } },
+        { S5P_DIS_IRQ_CORE1,                    { 0x0, 0x0, 0x0 } },
+        { S5P_DIS_IRQ_CENTRAL1,                 { 0x0, 0x0, 0x0 } },
+        { S5P_ISP_ARM_LOWPWR,                   { 0x1, 0x0, 0x0 } },
+        { S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR,     { 0x0, 0x0, 0x0 } },
+        { S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR,   { 0x0, 0x0, 0x0 } },
+        { S5P_ARM_COMMON_LOWPWR,                { 0x0, 0x0, 0x2 } },
+        { S5P_L2_0_LOWPWR,                      { 0x0, 0x0, 0x3 } },
+        /* XXX_OPTION register should be set other field */
+        { S5P_ARM_L2_0_OPTION,                  { 0x10, 0x10, 0x0 } },
+        { S5P_L2_1_LOWPWR,                      { 0x0, 0x0, 0x3 } },
+        { S5P_ARM_L2_1_OPTION,                  { 0x10, 0x10, 0x0 } },
+        { S5P_CMU_ACLKSTOP_LOWPWR,              { 0x1, 0x0, 0x0 } },
+        { S5P_CMU_SCLKSTOP_LOWPWR,              { 0x1, 0x0, 0x0 } },
+        { S5P_CMU_RESET_LOWPWR,                 { 0x1, 0x1, 0x0 } },
+        { S5P_DRAM_FREQ_DOWN_LOWPWR,            { 0x1, 0x1, 0x1 } },
+        { S5P_DDRPHY_DLLOFF_LOWPWR,             { 0x1, 0x1, 0x1 } },
+        { S5P_LPDDR_PHY_DLL_LOCK_LOWPWR,        { 0x1, 0x1, 0x1 } },
+        { S5P_CMU_ACLKSTOP_COREBLK_LOWPWR,      { 0x1, 0x0, 0x0 } },
+        { S5P_CMU_SCLKSTOP_COREBLK_LOWPWR,      { 0x1, 0x0, 0x0 } },
+        { S5P_CMU_RESET_COREBLK_LOWPWR,         { 0x1, 0x1, 0x0 } },
+        { S5P_APLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
+        { S5P_MPLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
+        { S5P_VPLL_SYSCLK_LOWPWR,               { 0x1, 0x0, 0x0 } },
+        { S5P_EPLL_SYSCLK_LOWPWR,               { 0x1, 0x1, 0x0 } },
+        { S5P_MPLLUSER_SYSCLK_LOWPWR,           { 0x1, 0x0, 0x0 } },
+        { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,     { 0x1, 0x0, 0x0 } },
+        { S5P_CMU_RESET_GPSALIVE_LOWPWR,        { 0x1, 0x0, 0x0 } },
+        { S5P_CMU_CLKSTOP_CAM_LOWPWR,           { 0x1, 0x0, 0x0 } },
+        { S5P_CMU_CLKSTOP_TV_LOWPWR,            { 0x1, 0x0, 0x0 } },
+        { S5P_CMU_CLKSTOP_MFC_LOWPWR,           { 0x1, 0x0, 0x0 } },
+        { S5P_CMU_CLKSTOP_G3D_LOWPWR,           { 0x1, 0x0, 0x0 } },
+        { S5P_CMU_CLKSTOP_LCD0_LOWPWR,          { 0x1, 0x0, 0x0 } },
+        { S5P_CMU_CLKSTOP_ISP_LOWPWR,           { 0x1, 0x0, 0x0 } },
+        { S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,        { 0x1, 0x0, 0x0 } },
+        { S5P_CMU_CLKSTOP_GPS_LOWPWR,           { 0x1, 0x0, 0x0 } },
+        { S5P_CMU_RESET_CAM_LOWPWR,             { 0x1, 0x0, 0x0 } },
+        { S5P_CMU_RESET_TV_LOWPWR,              { 0x1, 0x0, 0x0 } },
+        { S5P_CMU_RESET_MFC_LOWPWR,             { 0x1, 0x0, 0x0 } },
+        { S5P_CMU_RESET_G3D_LOWPWR,             { 0x1, 0x0, 0x0 } },
+        { S5P_CMU_RESET_LCD0_LOWPWR,            { 0x1, 0x0, 0x0 } },
+        { S5P_CMU_RESET_ISP_LOWPWR,             { 0x1, 0x0, 0x0 } },
+        { S5P_CMU_RESET_MAUDIO_LOWPWR,          { 0x1, 0x1, 0x0 } },
+        { S5P_CMU_RESET_GPS_LOWPWR,             { 0x1, 0x0, 0x0 } },
+        { S5P_TOP_BUS_LOWPWR,                   { 0x3, 0x0, 0x0 } },
+        { S5P_TOP_RETENTION_LOWPWR,             { 0x1, 0x0, 0x1 } },
+        { S5P_TOP_PWR_LOWPWR,                   { 0x3, 0x0, 0x3 } },
+        { S5P_TOP_BUS_COREBLK_LOWPWR,           { 0x3, 0x0, 0x0 } },
+        { S5P_TOP_RETENTION_COREBLK_LOWPWR,     { 0x1, 0x0, 0x1 } },
+        { S5P_TOP_PWR_COREBLK_LOWPWR,           { 0x3, 0x0, 0x3 } },
+        { S5P_LOGIC_RESET_LOWPWR,               { 0x1, 0x1, 0x0 } },
+        { S5P_OSCCLK_GATE_LOWPWR,               { 0x1, 0x0, 0x1 } },
+        { S5P_LOGIC_RESET_COREBLK_LOWPWR,       { 0x1, 0x1, 0x0 } },
+        { S5P_OSCCLK_GATE_COREBLK_LOWPWR,       { 0x1, 0x0, 0x1 } },
+        { S5P_ONENAND_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
+        { S5P_ONENAND_MEM_OPTION,               { 0x10, 0x10, 0x0 } },
+        { S5P_HSI_MEM_LOWPWR,                   { 0x3, 0x0, 0x0 } },
+        { S5P_HSI_MEM_OPTION,                   { 0x10, 0x10, 0x0 } },
+        { S5P_G2D_ACP_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
+        { S5P_G2D_ACP_MEM_OPTION,               { 0x10, 0x10, 0x0 } },
+        { S5P_USBOTG_MEM_LOWPWR,                { 0x3, 0x0, 0x0 } },
+        { S5P_USBOTG_MEM_OPTION,                { 0x10, 0x10, 0x0 } },
+        { S5P_HSMMC_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
+        { S5P_HSMMC_MEM_OPTION,                 { 0x10, 0x10, 0x0 } },
+        { S5P_CSSYS_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
+        { S5P_CSSYS_MEM_OPTION,                 { 0x10, 0x10, 0x0 } },
+        { S5P_SECSS_MEM_LOWPWR,                 { 0x3, 0x0, 0x0 } },
+        { S5P_SECSS_MEM_OPTION,                 { 0x10, 0x10, 0x0 } },
+        { S5P_ROTATOR_MEM_LOWPWR,               { 0x3, 0x0, 0x0 } },
+        { S5P_ROTATOR_MEM_OPTION,               { 0x10, 0x10, 0x0 } },
+        { S5P_PAD_RETENTION_DRAM_LOWPWR,        { 0x1, 0x0, 0x0 } },
+        { S5P_PAD_RETENTION_MAUDIO_LOWPWR,      { 0x1, 0x1, 0x0 } },
+        { S5P_PAD_RETENTION_GPIO_LOWPWR,        { 0x1, 0x0, 0x0 } },
+        { S5P_PAD_RETENTION_UART_LOWPWR,        { 0x1, 0x0, 0x0 } },
+        { S5P_PAD_RETENTION_MMCA_LOWPWR,        { 0x1, 0x0, 0x0 } },
+        { S5P_PAD_RETENTION_MMCB_LOWPWR,        { 0x1, 0x0, 0x0 } },
+        { S5P_PAD_RETENTION_EBIA_LOWPWR,        { 0x1, 0x0, 0x0 } },
+        { S5P_PAD_RETENTION_EBIB_LOWPWR,        { 0x1, 0x0, 0x0 } },
+        { S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR,{ 0x1, 0x0, 0x0 } },
+        { S5P_PAD_RETENTION_ISOLATION_LOWPWR,   { 0x1, 0x0, 0x0 } },
+        { S5P_PAD_ISOLATION_COREBLK_LOWPWR,     { 0x1, 0x0, 0x0 } },
+        { S5P_PAD_RETENTION_ALV_SEL_LOWPWR,     { 0x1, 0x0, 0x0 } },
+        { S5P_XUSBXTI_LOWPWR,                   { 0x1, 0x1, 0x0 } },
+        { S5P_XXTI_LOWPWR,                      { 0x1, 0x1, 0x0 } },
+        { S5P_EXT_REGULATOR_LOWPWR,             { 0x1, 0x1, 0x0 } },
+        { S5P_GPIO_MODE_LOWPWR,                 { 0x1, 0x0, 0x0 } },
+        { S5P_GPIO_MODE_COREBLK_LOWPWR,         { 0x1, 0x0, 0x0 } },
+        { S5P_GPIO_MODE_MAUDIO_LOWPWR,          { 0x1, 0x1, 0x0 } },
+        { S5P_TOP_ASB_RESET_LOWPWR,             { 0x1, 0x1, 0x1 } },
+        { S5P_TOP_ASB_ISOLATION_LOWPWR,         { 0x1, 0x0, 0x1 } },
+        { S5P_CAM_LOWPWR,                       { 0x7, 0x0, 0x0 } },
+        { S5P_TV_LOWPWR,                        { 0x7, 0x0, 0x0 } },
+        { S5P_MFC_LOWPWR,                       { 0x7, 0x0, 0x0 } },
+        { S5P_G3D_LOWPWR,                       { 0x7, 0x0, 0x0 } },
+        { S5P_LCD0_LOWPWR,                      { 0x7, 0x0, 0x0 } },
+        { S5P_ISP_LOWPWR,                       { 0x7, 0x0, 0x0 } },
+        { S5P_MAUDIO_LOWPWR,                    { 0x7, 0x7, 0x0 } },
+        { S5P_GPS_LOWPWR,                       { 0x7, 0x0, 0x0 } },
+        { S5P_GPS_ALIVE_LOWPWR,                 { 0x7, 0x0, 0x0 } },
+        { S5P_CMU_SYSCLK_ISP_LOWPWR,            { 0x1, 0x0, 0x0 } },
+        { S5P_CMU_SYSCLK_GPS_LOWPWR,            { 0x1, 0x0, 0x0 } },
+        { PMU_TABLE_END,},
 };
 
 void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
 {
-        unsigned int count = ARRAY_SIZE(sys_powerdown_reg);
+        unsigned int i;
+
+        for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++)
+                __raw_writel(exynos4_pmu_config[i].val[mode],
+                                exynos4_pmu_config[i].reg);
+}
+
+static int __init exynos4_pmu_init(void)
+{
+        exynos4_pmu_config = exynos4210_pmu_config;
+
+        if (soc_is_exynos4210()) {
+                exynos4_pmu_config = exynos4210_pmu_config;
+                pr_info("EXYNOS4210 PMU Initialize\n");
+        } else if (soc_is_exynos4212()) {
+                exynos4_pmu_config = exynos4212_pmu_config;
+                pr_info("EXYNOS4212 PMU Initialize\n");
+        } else {
+                pr_info("EXYNOS4: PMU not supported\n");
+        }
 
-        for (; count > 0; count--)
-                __raw_writel(sys_powerdown_val[count - 1][mode],
-                                sys_powerdown_reg[count - 1]);
+        return 0;
 }
+arch_initcall(exynos4_pmu_init);
diff --git a/arch/arm/mach-exynos4/setup-keypad.c b/arch/arm/mach-exynos4/setup-keypad.c
index 1ee0ebff111f..7862bfb5933d 100644
--- a/arch/arm/mach-exynos4/setup-keypad.c
+++ b/arch/arm/mach-exynos4/setup-keypad.c
@@ -19,15 +19,16 @@ void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
 
         if (rows > 8) {
                 /* Set all the necessary GPX2 pins: KP_ROW[0~7] */
-                s3c_gpio_cfgrange_nopull(EXYNOS4_GPX2(0), 8, S3C_GPIO_SFN(3));
+                s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), 8, S3C_GPIO_SFN(3),
+                                        S3C_GPIO_PULL_UP);
 
                 /* Set all the necessary GPX3 pins: KP_ROW[8~] */
-                s3c_gpio_cfgrange_nopull(EXYNOS4_GPX3(0), (rows - 8),
-                                         S3C_GPIO_SFN(3));
+                s3c_gpio_cfgall_range(EXYNOS4_GPX3(0), (rows - 8),
+                                         S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
         } else {
                 /* Set all the necessary GPX2 pins: KP_ROW[x] */
-                s3c_gpio_cfgrange_nopull(EXYNOS4_GPX2(0), rows,
-                                         S3C_GPIO_SFN(3));
+                s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), rows, S3C_GPIO_SFN(3),
+                                        S3C_GPIO_PULL_UP);
         }
 
         /* Set all the necessary GPX1 pins to special-function 3: KP_COL[x] */
diff --git a/arch/arm/mach-exynos4/setup-sdhci.c b/arch/arm/mach-exynos4/setup-sdhci.c
index 1e83f8cf236d..92937b410906 100644
--- a/arch/arm/mach-exynos4/setup-sdhci.c
+++ b/arch/arm/mach-exynos4/setup-sdhci.c
@@ -10,16 +10,7 @@
  * published by the Free Software Foundation.
 */
 
-#include <linux/kernel.h>
 #include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-
-#include <linux/mmc/card.h>
-#include <linux/mmc/host.h>
-
-#include <plat/regs-sdhci.h>
 
 /* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
 
@@ -29,41 +20,3 @@ char *exynos4_hsmmc_clksrcs[4] = {
         [2] = "sclk_mmc",       /* mmc_bus */
         [3] = NULL,
 };
-
-void exynos4_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r,
-                                  struct mmc_ios *ios, struct mmc_card *card)
-{
-        u32 ctrl2, ctrl3;
-
-        /* don't need to alter anything according to card-type */
-
-        ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
-
-        /* select base clock source to HCLK */
-
-        ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
-
-        /*
-         * clear async mode, enable conflict mask, rx feedback ctrl, SD
-         * clk hold and no use debounce count
-         */
-
-        ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
-                  S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
-                  S3C_SDHCI_CTRL2_ENFBCLKRX |
-                  S3C_SDHCI_CTRL2_DFCNT_NONE |
-                  S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
-
-        /* Tx and Rx feedback clock delay control */
-
-        if (ios->clock < 25 * 1000000)
-                ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
-                         S3C_SDHCI_CTRL3_FCSEL2 |
-                         S3C_SDHCI_CTRL3_FCSEL1 |
-                         S3C_SDHCI_CTRL3_FCSEL0);
-        else
-                ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
-
-        writel(ctrl2, r + S3C_SDHCI_CONTROL2);
-        writel(ctrl3, r + S3C_SDHCI_CONTROL3);
-}
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index fcf0ae95651f..8cdc730dcb3a 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -32,6 +32,7 @@
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/mtd/physmap.h>
+#include <video/vga.h>
 
 #include <mach/hardware.h>
 #include <mach/platform.h>
@@ -154,6 +155,7 @@ static struct map_desc ap_io_desc[] __initdata = {
 static void __init ap_map_io(void)
 {
         iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
+        vga_base = PCI_MEMORY_VADDR;
 }
 
 #define INTEGRATOR_SC_VALID_INT 0x003fffff
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index dd56bfb351e3..11b86e5b71c2 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -27,7 +27,6 @@
 #include <linux/spinlock.h>
 #include <linux/init.h>
 #include <linux/io.h>
-#include <video/vga.h>
 
 #include <mach/hardware.h>
 #include <mach/platform.h>
@@ -505,7 +504,6 @@ void __init pci_v3_preinit(void)
 
         pcibios_min_io = 0x6000;
         pcibios_min_mem = 0x00100000;
-        vga_base = PCI_MEMORY_VADDR;
 
         /*
          * Hook in our fault handler for PCI errors
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index 7245a55795dc..5261a7ed0999 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -6,9 +6,7 @@ config CPU_S3C2410
         bool
         depends on ARCH_S3C2410
         select CPU_ARM920T
-        select S3C_GPIO_PULL_UP
         select S3C2410_CLOCK
-        select S3C2410_GPIO
         select CPU_LLSERIAL_S3C2410
         select S3C2410_PM if PM
         select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX
@@ -28,11 +26,6 @@ config S3C2410_PM
         help
           Power Management code common to S3C2410 and better
 
-config S3C2410_GPIO
-        bool
-        help
-          GPIO code for S3C2410 and similar processors
-
 config SIMTEC_NOR
         bool
         help
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
index 81695353d8f4..782fd81144e9 100644
--- a/arch/arm/mach-s3c2410/Makefile
+++ b/arch/arm/mach-s3c2410/Makefile
@@ -13,7 +13,6 @@ obj-$(CONFIG_CPU_S3C2410)	+= s3c2410.o
 obj-$(CONFIG_CPU_S3C2410_DMA)   += dma.o
 obj-$(CONFIG_CPU_S3C2410_DMA)   += dma.o
 obj-$(CONFIG_S3C2410_PM)        += pm.o sleep.o
-obj-$(CONFIG_S3C2410_GPIO)      += gpio.o
 obj-$(CONFIG_S3C2410_CPUFREQ)   += cpu-freq.o
 obj-$(CONFIG_S3C2410_PLLTABLE)  += pll.o
 
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
index 0d8e043804c2..dbe43df8cfec 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -47,38 +47,26 @@ static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
                 .channels[0]    = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
                 .channels[2]    = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
                 .channels[3]    = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_IIS + S3C2410_IISFIFO,
-                .hw_addr.from   = S3C2410_PA_IIS + S3C2410_IISFIFO,
         },
         [DMACH_SPI0] = {
                 .name           = "spi0",
                 .channels[1]    = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_SPI + S3C2410_SPTDAT,
-                .hw_addr.from   = S3C2410_PA_SPI + S3C2410_SPRDAT,
         },
         [DMACH_SPI1] = {
                 .name           = "spi1",
                 .channels[3]    = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
-                .hw_addr.from   = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
         },
         [DMACH_UART0] = {
                 .name           = "uart0",
                 .channels[0]    = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_UART0 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART0 + S3C2410_URXH,
         },
         [DMACH_UART1] = {
                 .name           = "uart1",
                 .channels[1]    = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_UART1 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART1 + S3C2410_URXH,
         },
         [DMACH_UART2] = {
                 .name           = "uart2",
                 .channels[3]    = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_UART2 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART2 + S3C2410_URXH,
         },
         [DMACH_TIMER] = {
                 .name           = "timer",
@@ -90,12 +78,10 @@ static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
                 .name           = "i2s-sdi",
                 .channels[1]    = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
                 .channels[2]    = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
-                .hw_addr.from   = S3C2410_PA_IIS + S3C2410_IISFIFO,
         },
         [DMACH_I2S_OUT] = {
                 .name           = "i2s-sdo",
                 .channels[2]    = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_IIS + S3C2410_IISFIFO,
         },
         [DMACH_USB_EP1] = {
                 .name           = "usb-ep1",
diff --git a/arch/arm/mach-s3c2410/gpio.c b/arch/arm/mach-s3c2410/gpio.c
deleted file mode 100644
index 9664e011dae2..000000000000
--- a/arch/arm/mach-s3c2410/gpio.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/* linux/arch/arm/mach-s3c2410/gpio.c
- *
- * Copyright (c) 2004-2006 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 GPIO support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <mach/gpio-fns.h>
-#include <asm/irq.h>
-
-#include <mach/regs-gpio.h>
-
-int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
-                           unsigned int config)
-{
-        void __iomem *reg = S3C24XX_EINFLT0;
-        unsigned long flags;
-        unsigned long val;
-
-        if (pin < S3C2410_GPG(8) || pin > S3C2410_GPG(15))
-                return -EINVAL;
-
-        config &= 0xff;
-
-        pin -= S3C2410_GPG(8);
-        reg += pin & ~3;
-
-        local_irq_save(flags);
-
-        /* update filter width and clock source */
-
-        val = __raw_readl(reg);
-        val &= ~(0xff << ((pin & 3) * 8));
-        val |= config << ((pin & 3) * 8);
-        __raw_writel(val, reg);
-
-        /* update filter enable */
-
-        val = __raw_readl(S3C24XX_EXTINT2);
-        val &= ~(1 << ((pin * 4) + 3));
-        val |= on << ((pin * 4) + 3);
-        __raw_writel(val, S3C24XX_EXTINT2);
-
-        local_irq_restore(flags);
-
-        return 0;
-}
-
-EXPORT_SYMBOL(s3c2410_gpio_irqfilter);
diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h
index b2b2a5bb275e..ae8e482b6427 100644
--- a/arch/arm/mach-s3c2410/include/mach/dma.h
+++ b/arch/arm/mach-s3c2410/include/mach/dma.h
@@ -13,7 +13,6 @@
 #ifndef __ASM_ARCH_DMA_H
 #define __ASM_ARCH_DMA_H __FILE__
 
-#include <plat/dma.h>
 #include <linux/sysdev.h>
 
 #define MAX_DMA_TRANSFER_SIZE   0x100000 /* Data Unit is half word  */
@@ -51,6 +50,18 @@ enum dma_ch {
         DMACH_MAX,              /* the end entry */
 };
 
+static inline bool samsung_dma_has_circular(void)
+{
+        return false;
+}
+
+static inline bool samsung_dma_is_dmadev(void)
+{
+        return false;
+}
+
+#include <plat/dma.h>
+
 #define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
 
 /* we have 4 dma channels */
@@ -163,7 +174,7 @@ struct s3c2410_dma_chan {
         struct s3c2410_dma_client *client;
 
         /* channel configuration */
-        enum s3c2410_dmasrc      source;
+        enum dma_data_direction  source;
         enum dma_ch              req_ch;
         unsigned long            dev_addr;
         unsigned long            load_timeout;
@@ -196,9 +207,4 @@ struct s3c2410_dma_chan {
 
 typedef unsigned long dma_device_t;
 
-static inline bool s3c_dma_has_circular(void)
-{
-        return false;
-}
-
 #endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
index bab139201761..c53ad34c6579 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
@@ -1,98 +1 @@
-/* arch/arm/mach-s3c2410/include/mach/gpio-fns.h
- *
- * Copyright (c) 2003-2009 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - hardware
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __MACH_GPIO_FNS_H
-#define __MACH_GPIO_FNS_H __FILE__
-
-/* These functions are in the to-be-removed category and it is strongly
- * encouraged not to use these in new code. They will be marked deprecated
- * very soon.
- *
- * Most of the functionality can be either replaced by the gpiocfg calls
- * for the s3c platform or by the generic GPIOlib API.
- *
- * As of 2.6.35-rc, these will be removed, with the few drivers using them
- * either replaced or given a wrapper until the calls can be removed.
-*/
-
-#include <plat/gpio-cfg.h>
-
-static inline void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int cfg)
-{
-        /* 1:1 mapping between cfgpin and setcfg calls at the moment */
-        s3c_gpio_cfgpin(pin, cfg);
-}
-
-/* external functions for GPIO support
- *
- * These allow various different clients to access the same GPIO
- * registers without conflicting. If your driver only owns the entire
- * GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
-*/
-
-extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
-
-/* s3c2410_gpio_getirq
- *
- * turn the given pin number into the corresponding IRQ number
- *
- * returns:
- *      < 0 = no interrupt for this pin
- *      >=0 = interrupt number for the pin
-*/
-
-extern int s3c2410_gpio_getirq(unsigned int pin);
-
-/* s3c2410_gpio_irqfilter
- *
- * set the irq filtering on the given pin
- *
- * on = 0 => disable filtering
- *      1 => enable filtering
- *
- * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with
- *          width of filter (0 through 63)
- *
- *
-*/
-
-extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
-                                  unsigned int config);
-
-/* s3c2410_gpio_pullup
- *
- * This call should be replaced with s3c_gpio_setpull().
- *
- * As a note, there is currently no distinction between pull-up and pull-down
- * in the s3c24xx series devices with only an on/off configuration.
- */
-
-/* s3c2410_gpio_pullup
- *
- * configure the pull-up control on the given pin
- *
- * to = 1 => disable the pull-up
- *      0 => enable the pull-up
- *
- * eg;
- *
- *   s3c2410_gpio_pullup(S3C2410_GPB(0), 0);
- *   s3c2410_gpio_pullup(S3C2410_GPE(8), 0);
-*/
-
-extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
-
-extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
-
-extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
-
-#endif /* __MACH_GPIO_FNS_H */
+#include <plat/gpio-fns.h>
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-track.h b/arch/arm/mach-s3c2410/include/mach/gpio-track.h
index d67819dde42a..c410a078622c 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-track.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-track.h
@@ -17,11 +17,11 @@
 
 #include <mach/regs-gpio.h>
 
-extern struct s3c_gpio_chip s3c24xx_gpios[];
+extern struct samsung_gpio_chip s3c24xx_gpios[];
 
-static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin)
+static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int pin)
 {
-        struct s3c_gpio_chip *chip;
+        struct samsung_gpio_chip *chip;
 
         if (pin > S3C_GPIO_END)
                 return NULL;
diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h
index 425552d84b60..4cf495f813a7 100644
--- a/arch/arm/mach-s3c2410/include/mach/map.h
+++ b/arch/arm/mach-s3c2410/include/mach/map.h
@@ -14,9 +14,53 @@
 #define __ASM_ARCH_MAP_H
 
 #include <plat/map-base.h>
-#include <plat/map.h>
 
-#define S3C2410_ADDR(x)         S3C_ADDR(x)
+/*
+ * S3C2410 UART offset is 0x4000 but the other SoCs are 0x400.
+ * So need to define it, and here is to avoid redefinition warning.
+ */
+#define S3C_UART_OFFSET         (0x4000)
+
+#include <plat/map-s3c.h>
+
+/*
+ * interrupt controller is the first thing we put in, to make
+ * the assembly code for the irq detection easier
+ */
+#define S3C2410_PA_IRQ          (0x4A000000)
+#define S3C24XX_SZ_IRQ          SZ_1M
+
+/* memory controller registers */
+#define S3C2410_PA_MEMCTRL      (0x48000000)
+#define S3C24XX_SZ_MEMCTRL      SZ_1M
+
+/* UARTs */
+#define S3C_VA_UARTx(uart)      (S3C_VA_UART + ((uart * S3C_UART_OFFSET)))
+
+/* Timers */
+#define S3C2410_PA_TIMER        (0x51000000)
+#define S3C24XX_SZ_TIMER        SZ_1M
+
+/* Clock and Power management */
+#define S3C24XX_SZ_CLKPWR       SZ_1M
+
+/* USB Device port */
+#define S3C2410_PA_USBDEV       (0x52000000)
+#define S3C24XX_SZ_USBDEV       SZ_1M
+
+/* Watchdog */
+#define S3C2410_PA_WATCHDOG     (0x53000000)
+#define S3C24XX_SZ_WATCHDOG     SZ_1M
+
+/* Standard size definitions for peripheral blocks. */
+
+#define S3C24XX_SZ_UART         SZ_1M
+#define S3C24XX_SZ_IIS          SZ_1M
+#define S3C24XX_SZ_ADC          SZ_1M
+#define S3C24XX_SZ_SPI          SZ_1M
+#define S3C24XX_SZ_SDI          SZ_1M
+#define S3C24XX_SZ_NAND         SZ_1M
+#define S3C24XX_SZ_GPIO         SZ_1M
 
 /* USB host controller */
 #define S3C2410_PA_USBHOST (0x49000000)
@@ -75,10 +119,8 @@
 
 /* S3C2412 memory and IO controls */
 #define S3C2412_PA_SSMC (0x4F000000)
-#define S3C2412_VA_SSMC S3C_ADDR_CPU(0x00000000)
 
 #define S3C2412_PA_EBI  (0x48800000)
-#define S3C2412_VA_EBI  S3C_ADDR_CPU(0x00010000)
 
 /* physical addresses of all the chip-select areas */
 
@@ -100,12 +142,10 @@
 #define S3C24XX_PA_DMA      S3C2410_PA_DMA
 #define S3C24XX_PA_CLKPWR   S3C2410_PA_CLKPWR
 #define S3C24XX_PA_LCD      S3C2410_PA_LCD
-#define S3C24XX_PA_UART     S3C2410_PA_UART
 #define S3C24XX_PA_TIMER    S3C2410_PA_TIMER
 #define S3C24XX_PA_USBDEV   S3C2410_PA_USBDEV
 #define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
 #define S3C24XX_PA_IIS      S3C2410_PA_IIS
-#define S3C24XX_PA_GPIO     S3C2410_PA_GPIO
 #define S3C24XX_PA_RTC      S3C2410_PA_RTC
 #define S3C24XX_PA_ADC      S3C2410_PA_ADC
 #define S3C24XX_PA_SPI      S3C2410_PA_SPI
diff --git a/arch/arm/mach-s3c2410/include/mach/pm-core.h b/arch/arm/mach-s3c2410/include/mach/pm-core.h
index 45eea5210c87..2eef7e6f7675 100644
--- a/arch/arm/mach-s3c2410/include/mach/pm-core.h
+++ b/arch/arm/mach-s3c2410/include/mach/pm-core.h
@@ -64,4 +64,4 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
 }
 
 static inline void s3c_pm_restored_gpios(void) { }
-static inline void s3c_pm_saved_gpios(void) { }
+static inline void samsung_pm_saved_gpios(void) { }
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
index 5e06c7265835..df6434f326f0 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
@@ -102,6 +102,7 @@
 #define S3C2443_PCLKCON_UART3           (1<<3)
 #define S3C2443_PCLKCON_IIC             (1<<4)
 #define S3C2443_PCLKCON_SDI             (1<<5)
+#define S3C2443_PCLKCON_HSSPI           (1<<6)
 #define S3C2443_PCLKCON_ADC             (1<<7)
 #define S3C2443_PCLKCON_AC97            (1<<8)
 #define S3C2443_PCLKCON_IIS             (1<<9)
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 2a2fa0620133..a9201eaeb0f1 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -696,9 +696,9 @@ static void __init h1940_init(void)
                               S3C2410_MISCCR_USBSUSPND0 |
                               S3C2410_MISCCR_USBSUSPND1, 0x0);
 
-        tmp =   (0x78 << S3C24XX_PLLCON_MDIVSHIFT)
-              | (0x02 << S3C24XX_PLLCON_PDIVSHIFT)
-              | (0x03 << S3C24XX_PLLCON_SDIVSHIFT);
+        tmp =   (0x78 << S3C24XX_PLL_MDIV_SHIFT)
+              | (0x02 << S3C24XX_PLL_PDIV_SHIFT)
+              | (0x03 << S3C24XX_PLL_SDIV_SHIFT);
         writel(tmp, S3C2410_UPLLCON);
 
         gpio_request(S3C2410_GPC(0), "LCD power");
diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c
index f1d3bd8f6f17..a99c2f4a523f 100644
--- a/arch/arm/mach-s3c2410/s3c2410.c
+++ b/arch/arm/mach-s3c2410/s3c2410.c
@@ -72,8 +72,8 @@ void __init s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 
 void __init s3c2410_map_io(void)
 {
-        s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1up;
-        s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1up;
+        s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1up;
+        s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1up;
 
         iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc));
 }
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
index c2cf4e569989..b8b9029e9f2d 100644
--- a/arch/arm/mach-s3c2412/Kconfig
+++ b/arch/arm/mach-s3c2412/Kconfig
@@ -9,7 +9,6 @@ config CPU_S3C2412
         select CPU_LLSERIAL_S3C2440
         select S3C2412_PM if PM
         select S3C2412_DMA if S3C2410_DMA
-        select S3C2410_GPIO
         help
           Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line
 
diff --git a/arch/arm/mach-s3c2412/Makefile b/arch/arm/mach-s3c2412/Makefile
index 6c48a91ea39e..7e4d95fa8a97 100644
--- a/arch/arm/mach-s3c2412/Makefile
+++ b/arch/arm/mach-s3c2412/Makefile
@@ -12,7 +12,6 @@ obj-				:=
 obj-$(CONFIG_CPU_S3C2412)       += s3c2412.o
 obj-$(CONFIG_CPU_S3C2412)       += irq.o
 obj-$(CONFIG_CPU_S3C2412)       += clock.o
-obj-$(CONFIG_CPU_S3C2412)       += gpio.o
 obj-$(CONFIG_S3C2412_DMA)       += dma.o
 obj-$(CONFIG_S3C2412_PM)        += pm.o
 obj-$(CONFIG_S3C2412_PM_SLEEP)  += sleep.o
diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c
index 7abecfca0b7e..d2a7d5ef3e67 100644
--- a/arch/arm/mach-s3c2412/dma.c
+++ b/arch/arm/mach-s3c2412/dma.c
@@ -50,64 +50,46 @@ static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
                 .name           = "sdi",
                 .channels       = MAP(S3C2412_DMAREQSEL_SDI),
                 .channels_rx    = MAP(S3C2412_DMAREQSEL_SDI),
-                .hw_addr.to     = S3C2410_PA_SDI + S3C2410_SDIDATA,
-                .hw_addr.from   = S3C2410_PA_SDI + S3C2410_SDIDATA,
         },
         [DMACH_SPI0] = {
                 .name           = "spi0",
                 .channels       = MAP(S3C2412_DMAREQSEL_SPI0TX),
                 .channels_rx    = MAP(S3C2412_DMAREQSEL_SPI0RX),
-                .hw_addr.to     = S3C2410_PA_SPI + S3C2410_SPTDAT,
-                .hw_addr.from   = S3C2410_PA_SPI + S3C2410_SPRDAT,
         },
         [DMACH_SPI1] = {
                 .name           = "spi1",
                 .channels       = MAP(S3C2412_DMAREQSEL_SPI1TX),
                 .channels_rx    = MAP(S3C2412_DMAREQSEL_SPI1RX),
-                .hw_addr.to     = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPTDAT,
-                .hw_addr.from   = S3C2410_PA_SPI + S3C2412_SPI1  + S3C2410_SPRDAT,
         },
         [DMACH_UART0] = {
                 .name           = "uart0",
                 .channels       = MAP(S3C2412_DMAREQSEL_UART0_0),
                 .channels_rx    = MAP(S3C2412_DMAREQSEL_UART0_0),
-                .hw_addr.to     = S3C2410_PA_UART0 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART0 + S3C2410_URXH,
         },
         [DMACH_UART1] = {
                 .name           = "uart1",
                 .channels       = MAP(S3C2412_DMAREQSEL_UART1_0),
                 .channels_rx    = MAP(S3C2412_DMAREQSEL_UART1_0),
-                .hw_addr.to     = S3C2410_PA_UART1 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART1 + S3C2410_URXH,
         },
         [DMACH_UART2] = {
                 .name           = "uart2",
                 .channels       = MAP(S3C2412_DMAREQSEL_UART2_0),
                 .channels_rx    = MAP(S3C2412_DMAREQSEL_UART2_0),
-                .hw_addr.to     = S3C2410_PA_UART2 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART2 + S3C2410_URXH,
         },
         [DMACH_UART0_SRC2] = {
                 .name           = "uart0",
                 .channels       = MAP(S3C2412_DMAREQSEL_UART0_1),
                 .channels_rx    = MAP(S3C2412_DMAREQSEL_UART0_1),
-                .hw_addr.to     = S3C2410_PA_UART0 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART0 + S3C2410_URXH,
         },
         [DMACH_UART1_SRC2] = {
                 .name           = "uart1",
                 .channels       = MAP(S3C2412_DMAREQSEL_UART1_1),
                 .channels_rx    = MAP(S3C2412_DMAREQSEL_UART1_1),
-                .hw_addr.to     = S3C2410_PA_UART1 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART1 + S3C2410_URXH,
         },
         [DMACH_UART2_SRC2] = {
                 .name           = "uart2",
                 .channels       = MAP(S3C2412_DMAREQSEL_UART2_1),
                 .channels_rx    = MAP(S3C2412_DMAREQSEL_UART2_1),
-                .hw_addr.to     = S3C2410_PA_UART2 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART2 + S3C2410_URXH,
         },
         [DMACH_TIMER] = {
                 .name           = "timer",
@@ -148,11 +130,11 @@ static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
 
 static void s3c2412_dma_direction(struct s3c2410_dma_chan *chan,
                                   struct s3c24xx_dma_map *map,
-                                  enum s3c2410_dmasrc dir)
+                                  enum dma_data_direction dir)
 {
         unsigned long chsel;
 
-        if (dir == S3C2410_DMASRC_HW)
+        if (dir == DMA_FROM_DEVICE)
                 chsel = map->channels_rx[0];
         else
                 chsel = map->channels[0];
diff --git a/arch/arm/mach-s3c2412/gpio.c b/arch/arm/mach-s3c2412/gpio.c
index 3404a876b33e..4526f6ba31a8 100644
--- a/arch/arm/mach-s3c2412/gpio.c
+++ b/arch/arm/mach-s3c2412/gpio.c
@@ -28,7 +28,7 @@
 
 int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state)
 {
-        struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
+        struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
         unsigned long offs = pin - chip->chip.base;
         unsigned long flags;
         unsigned long slpcon;
diff --git a/arch/arm/mach-s3c2416/Kconfig b/arch/arm/mach-s3c2416/Kconfig
index 69b48a7d1dbd..84c7b03e5a30 100644
--- a/arch/arm/mach-s3c2416/Kconfig
+++ b/arch/arm/mach-s3c2416/Kconfig
@@ -13,7 +13,6 @@ config CPU_S3C2416
         select CPU_ARM926T
         select S3C2416_DMA if S3C2410_DMA
         select CPU_LLSERIAL_S3C2440
-        select S3C_GPIO_PULL_UPDOWN
         select SAMSUNG_CLKSRC
         select S3C2443_CLOCK
         help
diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c
index 21a5e81f0ab5..72b7c6274c79 100644
--- a/arch/arm/mach-s3c2416/clock.c
+++ b/arch/arm/mach-s3c2416/clock.c
@@ -21,7 +21,6 @@
 #include <plat/cpu.h>
 
 #include <plat/cpu-freq.h>
-#include <plat/pll6553x.h>
 #include <plat/pll.h>
 
 #include <asm/mach/map.h>
@@ -38,6 +37,32 @@ static unsigned int armdiv[8] = {
         [7] = 8,
 };
 
+static struct clksrc_clk hsspi_eplldiv = {
+        .clk = {
+                .name   = "hsspi-eplldiv",
+                .parent = &clk_esysclk.clk,
+                .ctrlbit = (1 << 14),
+                .enable = s3c2443_clkcon_enable_s,
+        },
+        .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 24 },
+};
+
+static struct clk *hsspi_sources[] = {
+        [0] = &hsspi_eplldiv.clk,
+        [1] = NULL, /* to fix */
+};
+
+static struct clksrc_clk hsspi_mux = {
+        .clk    = {
+                .name   = "hsspi-if",
+        },
+        .sources = &(struct clksrc_sources) {
+                .sources = hsspi_sources,
+                .nr_sources = ARRAY_SIZE(hsspi_sources),
+        },
+        .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 18 },
+};
+
 static struct clksrc_clk hsmmc_div[] = {
         [0] = {
                 .clk = {
@@ -114,6 +139,8 @@ void __init_or_cpufreq s3c2416_setup_clocks(void)
 
 
 static struct clksrc_clk *clksrcs[] __initdata = {
+        &hsspi_eplldiv,
+        &hsspi_mux,
         &hsmmc_div[0],
         &hsmmc_div[1],
         &hsmmc_mux[0],
diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c
index 494ce913dc95..3156b7a71371 100644
--- a/arch/arm/mach-s3c2416/s3c2416.c
+++ b/arch/arm/mach-s3c2416/s3c2416.c
@@ -118,8 +118,8 @@ void __init s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 
 void __init s3c2416_map_io(void)
 {
-        s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_updown;
-        s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_updown;
+        s3c24xx_gpiocfg_default.set_pull = samsung_gpio_setpull_updown;
+        s3c24xx_gpiocfg_default.get_pull = samsung_gpio_getpull_updown;
 
         /* initialize device information early */
         s3c2416_default_sdhci0();
diff --git a/arch/arm/mach-s3c2416/setup-sdhci.c b/arch/arm/mach-s3c2416/setup-sdhci.c
index ed34fad8f2c6..cee53955eb02 100644
--- a/arch/arm/mach-s3c2416/setup-sdhci.c
+++ b/arch/arm/mach-s3c2416/setup-sdhci.c
@@ -12,17 +12,7 @@
  * published by the Free Software Foundation.
 */
 
-#include <linux/kernel.h>
 #include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-
-#include <linux/mmc/card.h>
-#include <linux/mmc/host.h>
-
-#include <plat/regs-sdhci.h>
-#include <plat/sdhci.h>
 
 /* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
 
@@ -32,30 +22,3 @@ char *s3c2416_hsmmc_clksrcs[4] = {
         [2] = "hsmmc-if",
         /* [3] = "48m", - note not successfully used yet */
 };
-
-void s3c2416_setup_sdhci_cfg_card(struct platform_device *dev,
-                                  void __iomem *r,
-                                  struct mmc_ios *ios,
-                                  struct mmc_card *card)
-{
-        u32 ctrl2, ctrl3;
-
-        ctrl2 = __raw_readl(r + S3C_SDHCI_CONTROL2);
-        ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
-        ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
-                  S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
-                  S3C_SDHCI_CTRL2_ENFBCLKRX |
-                  S3C_SDHCI_CTRL2_DFCNT_NONE |
-                  S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
-
-        if (ios->clock < 25 * 1000000)
-                ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
-                         S3C_SDHCI_CTRL3_FCSEL2 |
-                         S3C_SDHCI_CTRL3_FCSEL1 |
-                         S3C_SDHCI_CTRL3_FCSEL0);
-        else
-                ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
-
-        __raw_writel(ctrl2, r + S3C_SDHCI_CONTROL2);
-        __raw_writel(ctrl3, r + S3C_SDHCI_CONTROL3);
-}
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
index 50825a3f91cc..914e620f1257 100644
--- a/arch/arm/mach-s3c2440/Kconfig
+++ b/arch/arm/mach-s3c2440/Kconfig
@@ -5,10 +5,8 @@
 config CPU_S3C2440
         bool
         select CPU_ARM920T
-        select S3C_GPIO_PULL_UP
         select S3C2410_CLOCK
         select S3C2410_PM if PM
-        select S3C2410_GPIO
         select S3C2440_DMA if S3C2410_DMA
         select CPU_S3C244X
         select CPU_LLSERIAL_S3C2440
@@ -18,9 +16,7 @@ config CPU_S3C2440
 config CPU_S3C2442
         bool
         select CPU_ARM920T
-        select S3C_GPIO_PULL_DOWN
         select S3C2410_CLOCK
-        select S3C2410_GPIO
         select S3C2410_PM if PM
         select CPU_S3C244X
         select CPU_LLSERIAL_S3C2440
diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c
index 3b0529f54e9c..0e73f8f9d132 100644
--- a/arch/arm/mach-s3c2440/dma.c
+++ b/arch/arm/mach-s3c2440/dma.c
@@ -48,38 +48,26 @@ static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
                 .channels[1]    = S3C2440_DCON_CH1_SDI | DMA_CH_VALID,
                 .channels[2]    = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
                 .channels[3]    = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_IIS + S3C2410_IISFIFO,
-                .hw_addr.from   = S3C2410_PA_IIS + S3C2410_IISFIFO,
         },
         [DMACH_SPI0] = {
                 .name           = "spi0",
                 .channels[1]    = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_SPI + S3C2410_SPTDAT,
-                .hw_addr.from   = S3C2410_PA_SPI + S3C2410_SPRDAT,
         },
         [DMACH_SPI1] = {
                 .name           = "spi1",
                 .channels[3]    = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
-                .hw_addr.from   = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
         },
         [DMACH_UART0] = {
                 .name           = "uart0",
                 .channels[0]    = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_UART0 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART0 + S3C2410_URXH,
         },
         [DMACH_UART1] = {
                 .name           = "uart1",
                 .channels[1]    = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_UART1 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART1 + S3C2410_URXH,
         },
         [DMACH_UART2] = {
                 .name           = "uart2",
                 .channels[3]    = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_UART2 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART2 + S3C2410_URXH,
         },
         [DMACH_TIMER] = {
                 .name           = "timer",
@@ -91,31 +79,26 @@ static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
                 .name           = "i2s-sdi",
                 .channels[1]    = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
                 .channels[2]    = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
-                .hw_addr.from   = S3C2410_PA_IIS + S3C2410_IISFIFO,
         },
         [DMACH_I2S_OUT] = {
                 .name           = "i2s-sdo",
                 .channels[0]    = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID,
                 .channels[2]    = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
-                .hw_addr.to     = S3C2410_PA_IIS + S3C2410_IISFIFO,
         },
         [DMACH_PCM_IN] = {
                 .name           = "pcm-in",
                 .channels[0]    = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID,
                 .channels[2]    = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID,
-                .hw_addr.from   = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
         },
         [DMACH_PCM_OUT] = {
                 .name           = "pcm-out",
                 .channels[1]    = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID,
                 .channels[3]    = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID,
-                .hw_addr.to     = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
         },
         [DMACH_MIC_IN] = {
                 .name           = "mic-in",
                 .channels[2]    = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID,
                 .channels[3]    = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID,
-                .hw_addr.from   = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
         },
         [DMACH_USB_EP1] = {
                 .name           = "usb-ep1",
diff --git a/arch/arm/mach-s3c2440/s3c2440.c b/arch/arm/mach-s3c2440/s3c2440.c
index ce99ff72838d..fc84e481efcf 100644
--- a/arch/arm/mach-s3c2440/s3c2440.c
+++ b/arch/arm/mach-s3c2440/s3c2440.c
@@ -68,6 +68,6 @@ void __init s3c2440_map_io(void)
 {
         s3c244x_map_io();
 
-        s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1up;
-        s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1up;
+        s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1up;
+        s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1up;
 }
diff --git a/arch/arm/mach-s3c2440/s3c2442.c b/arch/arm/mach-s3c2440/s3c2442.c
index 9ad99f8016a1..48e273ce9f9a 100644
--- a/arch/arm/mach-s3c2440/s3c2442.c
+++ b/arch/arm/mach-s3c2440/s3c2442.c
@@ -180,6 +180,6 @@ void __init s3c2442_map_io(void)
 {
         s3c244x_map_io();
 
-        s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1down;
-        s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1down;
+        s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1down;
+        s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1down;
 }
diff --git a/arch/arm/mach-s3c2443/Kconfig b/arch/arm/mach-s3c2443/Kconfig
index d8eb86823df7..8814031516ce 100644
--- a/arch/arm/mach-s3c2443/Kconfig
+++ b/arch/arm/mach-s3c2443/Kconfig
@@ -10,7 +10,6 @@ config CPU_S3C2443
         select CPU_LLSERIAL_S3C2440
         select SAMSUNG_CLKSRC
         select S3C2443_CLOCK
-        select S3C_GPIO_PULL_S3C2443
         help
           Support for the S3C2443 SoC from the S3C24XX line
 
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index a1a7176675b9..cd51d04e1de7 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -57,10 +57,6 @@
 
 /* clock selections */
 
-static struct clk clk_i2s_ext = {
-        .name           = "i2s-ext",
-};
-
 /* armdiv
  *
  * this clock is sourced from msysclk and can have a number of
@@ -128,7 +124,7 @@ static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
                 unsigned long clkcon0;
 
                 clkcon0 = __raw_readl(S3C2443_CLKDIV0);
-                clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK;
+                clkcon0 &= ~S3C2443_CLKDIV0_ARMDIV_MASK;
                 clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT;
                 __raw_writel(clkcon0, S3C2443_CLKDIV0);
         }
@@ -173,7 +169,7 @@ static struct clksrc_clk clk_arm = {
 
 static struct clksrc_clk clk_hsspi = {
         .clk    = {
-                .name           = "hsspi",
+                .name           = "hsspi-if",
                 .parent         = &clk_esysclk.clk,
                 .ctrlbit        = S3C2443_SCLKCON_HSSPICLK,
                 .enable         = s3c2443_clkcon_enable_s,
@@ -235,48 +231,6 @@ static struct clk clk_hsmmc = {
         },
 };
 
-/* i2s_eplldiv
- *
- * This clock is the output from the I2S divisor of ESYSCLK, and is separate
- * from the mux that comes after it (cannot merge into one single clock)
-*/
-
-static struct clksrc_clk clk_i2s_eplldiv = {
-        .clk    = {
-                .name           = "i2s-eplldiv",
-                .parent         = &clk_esysclk.clk,
-        },
-        .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
-};
-
-/* i2s-ref
- *
- * i2s bus reference clock, selectable from external, esysclk or epllref
- *
- * Note, this used to be two clocks, but was compressed into one.
-*/
-
-struct clk *clk_i2s_srclist[] = {
-        [0] = &clk_i2s_eplldiv.clk,
-        [1] = &clk_i2s_ext,
-        [2] = &clk_epllref.clk,
-        [3] = &clk_epllref.clk,
-};
-
-static struct clksrc_clk clk_i2s = {
-        .clk    = {
-                .name           = "i2s-if",
-                .ctrlbit        = S3C2443_SCLKCON_I2SCLK,
-                .enable         = s3c2443_clkcon_enable_s,
-
-        },
-        .sources = &(struct clksrc_sources) {
-                .sources = clk_i2s_srclist,
-                .nr_sources = ARRAY_SIZE(clk_i2s_srclist),
-        },
-        .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },
-};
-
 /* standard clock definitions */
 
 static struct clk init_clocks_off[] = {
@@ -286,11 +240,6 @@ static struct clk init_clocks_off[] = {
                 .enable         = s3c2443_clkcon_enable_p,
                 .ctrlbit        = S3C2443_PCLKCON_SDI,
         }, {
-                .name           = "iis",
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_IIS,
-        }, {
                 .name           = "spi",
                 .devname        = "s3c2410-spi.0",
                 .parent         = &clk_p,
@@ -312,8 +261,6 @@ static struct clk init_clocks[] = {
 
 static struct clksrc_clk *clksrcs[] __initdata = {
         &clk_arm,
-        &clk_i2s_eplldiv,
-        &clk_i2s,
         &clk_hsspi,
         &clk_hsmmc_div,
 };
diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c
index 3f658685ec16..fe52151d2e84 100644
--- a/arch/arm/mach-s3c2443/dma.c
+++ b/arch/arm/mach-s3c2443/dma.c
@@ -54,68 +54,46 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
         [DMACH_SDI] = {
                 .name           = "sdi",
                 .channels       = MAP(S3C2443_DMAREQSEL_SDI),
-                .hw_addr.to     = S3C2410_PA_IIS + S3C2410_IISFIFO,
-                .hw_addr.from   = S3C2410_PA_IIS + S3C2410_IISFIFO,
         },
         [DMACH_SPI0] = {
                 .name           = "spi0",
                 .channels       = MAP(S3C2443_DMAREQSEL_SPI0TX),
-                .hw_addr.to     = S3C2410_PA_SPI + S3C2410_SPTDAT,
-                .hw_addr.from   = S3C2410_PA_SPI + S3C2410_SPRDAT,
         },
         [DMACH_SPI1] = {
                 .name           = "spi1",
                 .channels       = MAP(S3C2443_DMAREQSEL_SPI1TX),
-                .hw_addr.to     = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
-                .hw_addr.from   = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
         },
         [DMACH_UART0] = {
                 .name           = "uart0",
                 .channels       = MAP(S3C2443_DMAREQSEL_UART0_0),
-                .hw_addr.to     = S3C2410_PA_UART0 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART0 + S3C2410_URXH,
         },
         [DMACH_UART1] = {
                 .name           = "uart1",
                 .channels       = MAP(S3C2443_DMAREQSEL_UART1_0),
-                .hw_addr.to     = S3C2410_PA_UART1 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART1 + S3C2410_URXH,
         },
         [DMACH_UART2] = {
                 .name           = "uart2",
                 .channels       = MAP(S3C2443_DMAREQSEL_UART2_0),
-                .hw_addr.to     = S3C2410_PA_UART2 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART2 + S3C2410_URXH,
         },
         [DMACH_UART3] = {
                 .name           = "uart3",
                 .channels       = MAP(S3C2443_DMAREQSEL_UART3_0),
-                .hw_addr.to     = S3C2443_PA_UART3 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2443_PA_UART3 + S3C2410_URXH,
         },
         [DMACH_UART0_SRC2] = {
                 .name           = "uart0",
                 .channels       = MAP(S3C2443_DMAREQSEL_UART0_1),
-                .hw_addr.to     = S3C2410_PA_UART0 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART0 + S3C2410_URXH,
         },
         [DMACH_UART1_SRC2] = {
                 .name           = "uart1",
                 .channels       = MAP(S3C2443_DMAREQSEL_UART1_1),
-                .hw_addr.to     = S3C2410_PA_UART1 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART1 + S3C2410_URXH,
         },
         [DMACH_UART2_SRC2] = {
                 .name           = "uart2",
                 .channels       = MAP(S3C2443_DMAREQSEL_UART2_1),
-                .hw_addr.to     = S3C2410_PA_UART2 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2410_PA_UART2 + S3C2410_URXH,
         },
         [DMACH_UART3_SRC2] = {
                 .name           = "uart3",
                 .channels       = MAP(S3C2443_DMAREQSEL_UART3_1),
-                .hw_addr.to     = S3C2443_PA_UART3 + S3C2410_UTXH,
-                .hw_addr.from   = S3C2443_PA_UART3 + S3C2410_URXH,
         },
         [DMACH_TIMER] = {
                 .name           = "timer",
@@ -124,27 +102,22 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
         [DMACH_I2S_IN] = {
                 .name           = "i2s-sdi",
                 .channels       = MAP(S3C2443_DMAREQSEL_I2SRX),
-                .hw_addr.from   = S3C2410_PA_IIS + S3C2410_IISFIFO,
         },
         [DMACH_I2S_OUT] = {
                 .name           = "i2s-sdo",
                 .channels       = MAP(S3C2443_DMAREQSEL_I2STX),
-                .hw_addr.to     = S3C2410_PA_IIS + S3C2410_IISFIFO,
         },
         [DMACH_PCM_IN] = {
                 .name           = "pcm-in",
                 .channels       = MAP(S3C2443_DMAREQSEL_PCMIN),
-                .hw_addr.from   = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
         },
         [DMACH_PCM_OUT] = {
                 .name           = "pcm-out",
                 .channels       = MAP(S3C2443_DMAREQSEL_PCMOUT),
-                .hw_addr.to     = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
         },
         [DMACH_MIC_IN] = {
                 .name           = "mic-in",
                 .channels       = MAP(S3C2443_DMAREQSEL_MICIN),
-                .hw_addr.from   = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
         },
 };
 
diff --git a/arch/arm/mach-s3c2443/s3c2443.c b/arch/arm/mach-s3c2443/s3c2443.c
index e6a28ba52c7d..5df6458ddd42 100644
--- a/arch/arm/mach-s3c2443/s3c2443.c
+++ b/arch/arm/mach-s3c2443/s3c2443.c
@@ -90,8 +90,8 @@ void __init s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 
 void __init s3c2443_map_io(void)
 {
-        s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_s3c2443;
-        s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_s3c2443;
+        s3c24xx_gpiocfg_default.set_pull = s3c2443_gpio_setpull;
+        s3c24xx_gpiocfg_default.get_pull = s3c2443_gpio_getpull;
 
         iotable_init(s3c2443_iodesc, ARRAY_SIZE(s3c2443_iodesc));
 }
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index f057b6ae4f90..5552e048c2be 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -288,5 +288,6 @@ config MACH_WLF_CRAGG_6410
         select S3C_DEV_RTC
         select S3C64XX_DEV_SPI
         select S3C24XX_GPIO_EXTRA128
+        select I2C
         help
           Machine support for the Wolfson Cragganmore S3C6410 variant.
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index 61b4034a0c22..902ab9ace93b 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -13,7 +13,6 @@ obj-				:=
 # Core files
 obj-y                           += cpu.o
 obj-y                           += clock.o
-obj-y                           += gpiolib.o
 
 # Core support for S3C6400 system
 
@@ -55,7 +54,7 @@ obj-$(CONFIG_MACH_HMT)		+= mach-hmt.o
 obj-$(CONFIG_MACH_SMARTQ)       += mach-smartq.o
 obj-$(CONFIG_MACH_SMARTQ5)      += mach-smartq5.o
 obj-$(CONFIG_MACH_SMARTQ7)      += mach-smartq7.o
-obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o
+obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o mach-crag6410-module.o
 
 # device support
 
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 8cf39e33579e..39c238d7a3dc 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -25,13 +25,13 @@
 
 #include <mach/regs-sys.h>
 #include <mach/regs-clock.h>
-#include <mach/pll.h>
 
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/cpu-freq.h>
 #include <plat/clock.h>
 #include <plat/clock-clksrc.h>
+#include <plat/pll.h>
 
 /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
  * ext_xtal_mux for want of an actual name from the manual.
@@ -735,7 +735,8 @@ void __init_or_cpufreq s3c6400_setup_clocks(void)
         /* For now assume the mux always selects the crystal */
         clk_ext_xtal_mux.parent = xtal_clk;
 
-        epll = s3c6400_get_epll(xtal);
+        epll = s3c_get_pll6553x(xtal, __raw_readl(S3C_EPLL_CON0),
+                                __raw_readl(S3C_EPLL_CON1));
         mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
         apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
 
@@ -744,7 +745,13 @@ void __init_or_cpufreq s3c6400_setup_clocks(void)
         printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
                apll, mpll, epll);
 
-        hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
+        if(__raw_readl(S3C64XX_OTHERS) & S3C64XX_OTHERS_SYNCMUXSEL)
+                /* Synchronous mode */
+                hclk2 = apll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
+        else
+                /* Asynchronous mode */
+                hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
+
         hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
         pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
 
diff --git a/arch/arm/mach-s3c64xx/cpu.c b/arch/arm/mach-s3c64xx/cpu.c
index 374e45e566b8..cefd7f6dd4f3 100644
--- a/arch/arm/mach-s3c64xx/cpu.c
+++ b/arch/arm/mach-s3c64xx/cpu.c
@@ -33,8 +33,8 @@
 #include <plat/devs.h>
 #include <plat/clock.h>
 
-#include <mach/s3c6400.h>
-#include <mach/s3c6410.h>
+#include <plat/s3c6400.h>
+#include <plat/s3c6410.h>
 
 /* table of supported CPUs */
 
@@ -43,16 +43,16 @@ static const char name_s3c6410[] = "S3C6410";
 
 static struct cpu_table cpu_ids[] __initdata = {
         {
-                .idcode         = 0x36400000,
-                .idmask         = 0xfffff000,
+                .idcode         = S3C6400_CPU_ID,
+                .idmask         = S3C64XX_CPU_MASK,
                 .map_io         = s3c6400_map_io,
                 .init_clocks    = s3c6400_init_clocks,
                 .init_uarts     = s3c6400_init_uarts,
                 .init           = s3c6400_init,
                 .name           = name_s3c6400,
         }, {
-                .idcode         = 0x36410100,
-                .idmask         = 0xffffff00,
+                .idcode         = S3C6410_CPU_ID,
+                .idmask         = S3C64XX_CPU_MASK,
                 .map_io         = s3c6410_map_io,
                 .init_clocks    = s3c6410_init_clocks,
                 .init_uarts     = s3c6410_init_uarts,
@@ -140,22 +140,14 @@ void __init s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 
 void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
 {
-        unsigned long idcode;
-
         /* initialise the io descriptors we need for initialisation */
         iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
         iotable_init(mach_desc, size);
 
-        idcode = __raw_readl(S3C_VA_SYS + 0x118);
-        if (!idcode) {
-                /* S3C6400 has the ID register in a different place,
-                 * and needs a write before it can be read. */
-
-                __raw_writel(0x0, S3C_VA_SYS + 0xA1C);
-                idcode = __raw_readl(S3C_VA_SYS + 0xA1C);
-        }
+        /* detect cpu id */
+        s3c64xx_init_cpu();
 
-        s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
+        s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 }
 
 static __init int s3c64xx_sysdev_init(void)
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c
index 204bfafe4bfc..17d62f4f8204 100644
--- a/arch/arm/mach-s3c64xx/dma.c
+++ b/arch/arm/mach-s3c64xx/dma.c
@@ -147,14 +147,14 @@ static void s3c64xx_dma_fill_lli(struct s3c2410_dma_chan *chan,
         u32 control0, control1;
 
         switch (chan->source) {
-        case S3C2410_DMASRC_HW:
+        case DMA_FROM_DEVICE:
                 src = chan->dev_addr;
                 dst = data;
                 control0 = PL080_CONTROL_SRC_AHB2;
                 control0 |= PL080_CONTROL_DST_INCR;
                 break;
 
-        case S3C2410_DMASRC_MEM:
+        case DMA_TO_DEVICE:
                 src = data;
                 dst = chan->dev_addr;
                 control0 = PL080_CONTROL_DST_AHB2;
@@ -416,7 +416,7 @@ EXPORT_SYMBOL(s3c2410_dma_enqueue);
 
 
 int s3c2410_dma_devconfig(enum dma_ch channel,
-                          enum s3c2410_dmasrc source,
+                          enum dma_data_direction source,
                           unsigned long devaddr)
 {
         struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
@@ -437,11 +437,11 @@ int s3c2410_dma_devconfig(enum dma_ch channel,
         pr_debug("%s: peripheral %d\n", __func__, peripheral);
 
         switch (source) {
-        case S3C2410_DMASRC_HW:
+        case DMA_FROM_DEVICE:
                 config = 2 << PL080_CONFIG_FLOW_CONTROL_SHIFT;
                 config |= peripheral << PL080_CONFIG_SRC_SEL_SHIFT;
                 break;
-        case S3C2410_DMASRC_MEM:
+        case DMA_TO_DEVICE:
                 config = 1 << PL080_CONFIG_FLOW_CONTROL_SHIFT;
                 config |= peripheral << PL080_CONFIG_DST_SEL_SHIFT;
                 break;
@@ -740,7 +740,7 @@ static int __init s3c64xx_dma_init(void)
         }
 
         /* Set all DMA configuration to be DMA, not SDMA */
-        writel(0xffffff, S3C_SYSREG(0x110));
+        writel(0xffffff, S3C64XX_SDMA_SEL);
 
         /* Register standard DMA controllers */
         s3c64xx_dma_init1(0, DMACH_UART0, IRQ_DMA0, 0x75000000);
diff --git a/arch/arm/mach-s3c64xx/gpiolib.c b/arch/arm/mach-s3c64xx/gpiolib.c
deleted file mode 100644
index 92b09085caaa..000000000000
--- a/arch/arm/mach-s3c64xx/gpiolib.c
+++ /dev/null
@@ -1,290 +0,0 @@
-/* arch/arm/plat-s3c64xx/gpiolib.c
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S3C64XX - GPIOlib support 
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-
-#include <mach/map.h>
-
-#include <plat/gpio-core.h>
-#include <plat/gpio-cfg.h>
-#include <plat/gpio-cfg-helpers.h>
-#include <mach/regs-gpio.h>
-
-/* GPIO bank summary:
- *
- * Bank GPIOs   Style   SlpCon  ExtInt Group
- * A    8       4Bit    Yes     1
- * B    7       4Bit    Yes     1
- * C    8       4Bit    Yes     2
- * D    5       4Bit    Yes     3
- * E    5       4Bit    Yes     None
- * F    16      2Bit    Yes     4 [1]
- * G    7       4Bit    Yes     5
- * H    10      4Bit[2] Yes     6
- * I    16      2Bit    Yes     None
- * J    12      2Bit    Yes     None
- * K    16      4Bit[2] No      None
- * L    15      4Bit[2] No      None
- * M    6       4Bit    No      IRQ_EINT
- * N    16      2Bit    No      IRQ_EINT
- * O    16      2Bit    Yes     7
- * P    15      2Bit    Yes     8
- * Q    9       2Bit    Yes     9
- *
- * [1] BANKF pins 14,15 do not form part of the external interrupt sources
- * [2] BANK has two control registers, GPxCON0 and GPxCON1
- */
-
-static struct s3c_gpio_cfg gpio_4bit_cfg_noint = {
-        .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
-        .get_config     = s3c_gpio_getcfg_s3c64xx_4bit,
-        .set_pull       = s3c_gpio_setpull_updown,
-        .get_pull       = s3c_gpio_getpull_updown,
-};
-
-static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = {
-        .cfg_eint       = 7,
-        .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
-        .get_config     = s3c_gpio_getcfg_s3c64xx_4bit,
-        .set_pull       = s3c_gpio_setpull_updown,
-        .get_pull       = s3c_gpio_getpull_updown,
-};
-
-static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = {
-        .cfg_eint       = 3,
-        .get_config     = s3c_gpio_getcfg_s3c64xx_4bit,
-        .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
-        .set_pull       = s3c_gpio_setpull_updown,
-        .get_pull       = s3c_gpio_getpull_updown,
-};
-
-static int s3c64xx_gpio2int_gpm(struct gpio_chip *chip, unsigned pin)
-{
-        return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
-}
-
-static struct s3c_gpio_chip gpio_4bit[] = {
-        {
-                .base   = S3C64XX_GPA_BASE,
-                .config = &gpio_4bit_cfg_eint0111,
-                .chip   = {
-                        .base   = S3C64XX_GPA(0),
-                        .ngpio  = S3C64XX_GPIO_A_NR,
-                        .label  = "GPA",
-                },
-        }, {
-                .base   = S3C64XX_GPB_BASE,
-                .config = &gpio_4bit_cfg_eint0111,
-                .chip   = {
-                        .base   = S3C64XX_GPB(0),
-                        .ngpio  = S3C64XX_GPIO_B_NR,
-                        .label  = "GPB",
-                },
-        }, {
-                .base   = S3C64XX_GPC_BASE,
-                .config = &gpio_4bit_cfg_eint0111,
-                .chip   = {
-                        .base   = S3C64XX_GPC(0),
-                        .ngpio  = S3C64XX_GPIO_C_NR,
-                        .label  = "GPC",
-                },
-        }, {
-                .base   = S3C64XX_GPD_BASE,
-                .config = &gpio_4bit_cfg_eint0111,
-                .chip   = {
-                        .base   = S3C64XX_GPD(0),
-                        .ngpio  = S3C64XX_GPIO_D_NR,
-                        .label  = "GPD",
-                },
-        }, {
-                .base   = S3C64XX_GPE_BASE,
-                .config = &gpio_4bit_cfg_noint,
-                .chip   = {
-                        .base   = S3C64XX_GPE(0),
-                        .ngpio  = S3C64XX_GPIO_E_NR,
-                        .label  = "GPE",
-                },
-        }, {
-                .base   = S3C64XX_GPG_BASE,
-                .config = &gpio_4bit_cfg_eint0111,
-                .chip   = {
-                        .base   = S3C64XX_GPG(0),
-                        .ngpio  = S3C64XX_GPIO_G_NR,
-                        .label  = "GPG",
-                },
-        }, {
-                .base   = S3C64XX_GPM_BASE,
-                .config = &gpio_4bit_cfg_eint0011,
-                .chip   = {
-                        .base   = S3C64XX_GPM(0),
-                        .ngpio  = S3C64XX_GPIO_M_NR,
-                        .label  = "GPM",
-                        .to_irq = s3c64xx_gpio2int_gpm,
-                },
-        },
-};
-
-static int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin)
-{
-        return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
-}
-
-static struct s3c_gpio_chip gpio_4bit2[] = {
-        {
-                .base   = S3C64XX_GPH_BASE + 0x4,
-                .config = &gpio_4bit_cfg_eint0111,
-                .chip   = {
-                        .base   = S3C64XX_GPH(0),
-                        .ngpio  = S3C64XX_GPIO_H_NR,
-                        .label  = "GPH",
-                },
-        }, {
-                .base   = S3C64XX_GPK_BASE + 0x4,
-                .config = &gpio_4bit_cfg_noint,
-                .chip   = {
-                        .base   = S3C64XX_GPK(0),
-                        .ngpio  = S3C64XX_GPIO_K_NR,
-                        .label  = "GPK",
-                },
-        }, {
-                .base   = S3C64XX_GPL_BASE + 0x4,
-                .config = &gpio_4bit_cfg_eint0011,
-                .chip   = {
-                        .base   = S3C64XX_GPL(0),
-                        .ngpio  = S3C64XX_GPIO_L_NR,
-                        .label  = "GPL",
-                        .to_irq = s3c64xx_gpio2int_gpl,
-                },
-        },
-};
-
-static struct s3c_gpio_cfg gpio_2bit_cfg_noint = {
-        .set_config     = s3c_gpio_setcfg_s3c24xx,
-        .get_config     = s3c_gpio_getcfg_s3c24xx,
-        .set_pull       = s3c_gpio_setpull_updown,
-        .get_pull       = s3c_gpio_getpull_updown,
-};
-
-static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = {
-        .cfg_eint       = 2,
-        .set_config     = s3c_gpio_setcfg_s3c24xx,
-        .get_config     = s3c_gpio_getcfg_s3c24xx,
-        .set_pull       = s3c_gpio_setpull_updown,
-        .get_pull       = s3c_gpio_getpull_updown,
-};
-
-static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
-        .cfg_eint       = 3,
-        .set_config     = s3c_gpio_setcfg_s3c24xx,
-        .get_config     = s3c_gpio_getcfg_s3c24xx,
-        .set_pull       = s3c_gpio_setpull_updown,
-        .get_pull       = s3c_gpio_getpull_updown,
-};
-
-static struct s3c_gpio_chip gpio_2bit[] = {
-        {
-                .base   = S3C64XX_GPF_BASE,
-                .config = &gpio_2bit_cfg_eint11,
-                .chip   = {
-                        .base   = S3C64XX_GPF(0),
-                        .ngpio  = S3C64XX_GPIO_F_NR,
-                        .label  = "GPF",
-                },
-        }, {
-                .base   = S3C64XX_GPI_BASE,
-                .config = &gpio_2bit_cfg_noint,
-                .chip   = {
-                        .base   = S3C64XX_GPI(0),
-                        .ngpio  = S3C64XX_GPIO_I_NR,
-                        .label  = "GPI",
-                },
-        }, {
-                .base   = S3C64XX_GPJ_BASE,
-                .config = &gpio_2bit_cfg_noint,
-                .chip   = {
-                        .base   = S3C64XX_GPJ(0),
-                        .ngpio  = S3C64XX_GPIO_J_NR,
-                        .label  = "GPJ",
-                },
-        }, {
-                .base   = S3C64XX_GPN_BASE,
-                .irq_base = IRQ_EINT(0),
-                .config = &gpio_2bit_cfg_eint10,
-                .chip   = {
-                        .base   = S3C64XX_GPN(0),
-                        .ngpio  = S3C64XX_GPIO_N_NR,
-                        .label  = "GPN",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        }, {
-                .base   = S3C64XX_GPO_BASE,
-                .config = &gpio_2bit_cfg_eint11,
-                .chip   = {
-                        .base   = S3C64XX_GPO(0),
-                        .ngpio  = S3C64XX_GPIO_O_NR,
-                        .label  = "GPO",
-                },
-        }, {
-                .base   = S3C64XX_GPP_BASE,
-                .config = &gpio_2bit_cfg_eint11,
-                .chip   = {
-                        .base   = S3C64XX_GPP(0),
-                        .ngpio  = S3C64XX_GPIO_P_NR,
-                        .label  = "GPP",
-                },
-        }, {
-                .base   = S3C64XX_GPQ_BASE,
-                .config = &gpio_2bit_cfg_eint11,
-                .chip   = {
-                        .base   = S3C64XX_GPQ(0),
-                        .ngpio  = S3C64XX_GPIO_Q_NR,
-                        .label  = "GPQ",
-                },
-        },
-};
-
-static __init void s3c64xx_gpiolib_add_2bit(struct s3c_gpio_chip *chip)
-{
-        chip->pm = __gpio_pm(&s3c_gpio_pm_2bit);
-}
-
-static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips,
-                                       int nr_chips,
-                                       void (*fn)(struct s3c_gpio_chip *))
-{
-        for (; nr_chips > 0; nr_chips--, chips++) {
-                if (fn)
-                        (fn)(chips);
-                s3c_gpiolib_add(chips);
-        }
-}
-
-static __init int s3c64xx_gpiolib_init(void)
-{
-        s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit),
-                            samsung_gpiolib_add_4bit);
-
-        s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2),
-                            samsung_gpiolib_add_4bit2);
-
-        s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit),
-                            s3c64xx_gpiolib_add_2bit);
-
-        return 0;
-}
-
-core_initcall(s3c64xx_gpiolib_init);
diff --git a/arch/arm/mach-s3c64xx/include/mach/clkdev.h b/arch/arm/mach-s3c64xx/include/mach/clkdev.h
deleted file mode 100644
index 7dffa83d23ff..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __MACH_CLKDEV_H__
-#define __MACH_CLKDEV_H__
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do {} while (0)
-
-#endif
diff --git a/arch/arm/mach-s3c64xx/include/mach/crag6410.h b/arch/arm/mach-s3c64xx/include/mach/crag6410.h
new file mode 100644
index 000000000000..be9074e17dfd
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/crag6410.h
@@ -0,0 +1,23 @@
+/* Cragganmore 6410 shared definitions
+ *
+ * Copyright 2011 Wolfson Microelectronics plc
+ *      Mark Brown <broonie@opensource.wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef MACH_CRAG6410_H
+#define MACH_CRAG6410_H
+
+#include <linux/gpio.h>
+
+#define BANFF_PMIC_IRQ_BASE             IRQ_BOARD_START
+#define GLENFARCLAS_PMIC_IRQ_BASE       (IRQ_BOARD_START + 64)
+
+#define PCA935X_GPIO_BASE               GPIO_BOARD_START
+#define CODEC_GPIO_BASE         (GPIO_BOARD_START + 8)
+#define GLENFARCLAS_PMIC_GPIO_BASE      (GPIO_BOARD_START + 16)
+
+#endif
diff --git a/arch/arm/mach-s3c64xx/include/mach/dma.h b/arch/arm/mach-s3c64xx/include/mach/dma.h
index 0a5d9268a23e..fe1a98cf0e4c 100644
--- a/arch/arm/mach-s3c64xx/include/mach/dma.h
+++ b/arch/arm/mach-s3c64xx/include/mach/dma.h
@@ -58,11 +58,15 @@ enum dma_ch {
         DMACH_MAX               /* the end */
 };
 
-static __inline__ bool s3c_dma_has_circular(void)
+static inline bool samsung_dma_has_circular(void)
 {
         return true;
 }
 
+static inline bool samsung_dma_is_dmadev(void)
+{
+        return false;
+}
 #define S3C2410_DMAF_CIRCULAR           (1 << 0)
 
 #include <plat/dma.h>
@@ -95,7 +99,7 @@ struct s3c2410_dma_chan {
         unsigned char            peripheral;
 
         unsigned int             flags;
-        enum s3c2410_dmasrc      source;
+        enum dma_data_direction  source;
 
 
         dma_addr_t              dev_addr;
diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h
index a1f13f02c841..23a1d71e4d53 100644
--- a/arch/arm/mach-s3c64xx/include/mach/map.h
+++ b/arch/arm/mach-s3c64xx/include/mach/map.h
@@ -16,6 +16,7 @@
 #define __ASM_ARCH_MAP_H __FILE__
 
 #include <plat/map-base.h>
+#include <plat/map-s3c.h>
 
 /*
  * Post-mux Chip Select Regions Xm0CSn_
@@ -83,7 +84,6 @@
 #define S3C64XX_PA_IIC1         (0x7F00F000)
 
 #define S3C64XX_PA_GPIO         (0x7F008000)
-#define S3C64XX_VA_GPIO         S3C_ADDR_CPU(0x00000000)
 #define S3C64XX_SZ_GPIO         SZ_4K
 
 #define S3C64XX_PA_SDRAM        (0x50000000)
@@ -94,16 +94,10 @@
 #define S3C64XX_PA_VIC1         (0x71300000)
 
 #define S3C64XX_PA_MODEM        (0x74108000)
-#define S3C64XX_VA_MODEM        S3C_ADDR_CPU(0x00100000)
 
 #define S3C64XX_PA_USBHOST      (0x74300000)
 
 #define S3C64XX_PA_USB_HSPHY    (0x7C100000)
-#define S3C64XX_VA_USB_HSPHY    S3C_ADDR_CPU(0x00200000)
-
-/* place VICs close together */
-#define VA_VIC0                 (S3C_VA_IRQ + 0x00)
-#define VA_VIC1                 (S3C_VA_IRQ + 0x10000)
 
 /* compatibiltiy defines. */
 #define S3C_PA_TIMER            S3C64XX_PA_TIMER
@@ -119,7 +113,6 @@
 #define S3C_PA_FB               S3C64XX_PA_FB
 #define S3C_PA_USBHOST          S3C64XX_PA_USBHOST
 #define S3C_PA_USB_HSOTG        S3C64XX_PA_USB_HSOTG
-#define S3C_VA_USB_HSPHY        S3C64XX_VA_USB_HSPHY
 #define S3C_PA_RTC              S3C64XX_PA_RTC
 #define S3C_PA_WDT              S3C64XX_PA_WATCHDOG
 
diff --git a/arch/arm/mach-s3c64xx/include/mach/pll.h b/arch/arm/mach-s3c64xx/include/mach/pll.h
deleted file mode 100644
index 5ef0bb698ee0..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/pll.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* arch/arm/plat-s3c64xx/include/plat/pll.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S3C64XX PLL code
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#define S3C6400_PLL_MDIV_MASK   ((1 << (25-16+1)) - 1)
-#define S3C6400_PLL_PDIV_MASK   ((1 << (13-8+1)) - 1)
-#define S3C6400_PLL_SDIV_MASK   ((1 << (2-0+1)) - 1)
-#define S3C6400_PLL_MDIV_SHIFT  (16)
-#define S3C6400_PLL_PDIV_SHIFT  (8)
-#define S3C6400_PLL_SDIV_SHIFT  (0)
-
-#include <asm/div64.h>
-#include <plat/pll6553x.h>
-
-static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
-                                            u32 pllcon)
-{
-        u32 mdiv, pdiv, sdiv;
-        u64 fvco = baseclk;
-
-        mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK;
-        pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK;
-        sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK;
-
-        fvco *= mdiv;
-        do_div(fvco, (pdiv << sdiv));
-
-        return (unsigned long)fvco;
-}
-
-static inline unsigned long s3c6400_get_epll(unsigned long baseclk)
-{
-        return s3c_get_pll6553x(baseclk, __raw_readl(S3C_EPLL_CON0),
-                                __raw_readl(S3C_EPLL_CON1));
-}
diff --git a/arch/arm/mach-s3c64xx/include/mach/pm-core.h b/arch/arm/mach-s3c64xx/include/mach/pm-core.h
index 38659bebe4b1..fcf3dcabb694 100644
--- a/arch/arm/mach-s3c64xx/include/mach/pm-core.h
+++ b/arch/arm/mach-s3c64xx/include/mach/pm-core.h
@@ -104,7 +104,7 @@ static inline void s3c_pm_restored_gpios(void)
         __raw_writel(0, S3C64XX_SLPEN);
 }
 
-static inline void s3c_pm_saved_gpios(void)
+static inline void samsung_pm_saved_gpios(void)
 {
         /* turn on the sleep mode and keep it there, as it seems that during
          * suspend the xCON registers get re-set and thus you can end up with
diff --git a/arch/arm/mach-s3c64xx/include/mach/pwm-clock.h b/arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
deleted file mode 100644
index b25bedee0d52..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* linux/arch/arm/mach-s3c6400/include/mach/pwm-clock.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S3C64xx - pwm clock and timer support
- */
-
-/**
- * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
- * @tcfg: The timer TCFG1 register bits shifted down to 0.
- *
- * Return true if the given configuration from TCFG1 is a TCLK instead
- * any of the TDIV clocks.
- */
-static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
-{
-        return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
-}
-
-/**
- * tcfg_to_divisor() - convert tcfg1 setting to a divisor
- * @tcfg1: The tcfg1 setting, shifted down.
- *
- * Get the divisor value for the given tcfg1 setting. We assume the
- * caller has already checked to see if this is not a TCLK source.
- */
-static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
-{
-        return 1 << tcfg1;
-}
-
-/**
- * pwm_tdiv_has_div1() - does the tdiv setting have a /1
- *
- * Return true if we have a /1 in the tdiv setting.
- */
-static inline unsigned int pwm_tdiv_has_div1(void)
-{
-        return 1;
-}
-
-/**
- * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
- * @div: The divisor to calculate the bit information for.
- *
- * Turn a divisor into the necessary bit field for TCFG1.
- */
-static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
-{
-        return ilog2(div);
-}
-
-#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-sys.h b/arch/arm/mach-s3c64xx/include/mach/regs-sys.h
index 69b78d9f83b8..b91e02093289 100644
--- a/arch/arm/mach-s3c64xx/include/mach/regs-sys.h
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-sys.h
@@ -21,8 +21,11 @@
 #define S3C64XX_AHB_CON1        S3C_SYSREG(0x104)
 #define S3C64XX_AHB_CON2        S3C_SYSREG(0x108)
 
+#define S3C64XX_SDMA_SEL        S3C_SYSREG(0x110)
+
 #define S3C64XX_OTHERS          S3C_SYSREG(0x900)
 
 #define S3C64XX_OTHERS_USBMASK  (1 << 16)
+#define S3C64XX_OTHERS_SYNCMUXSEL       (1 << 6)
 
 #endif /* _PLAT_REGS_SYS_H */
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index cb8864327ac4..d2a68d22eda9 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -45,7 +45,7 @@
 #include <plat/fb.h>
 #include <plat/regs-fb-v4.h>
 
-#include <mach/s3c6410.h>
+#include <plat/s3c6410.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
new file mode 100644
index 000000000000..66668565ee75
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
@@ -0,0 +1,182 @@
+/* Speyside modules for Cragganmore - board data probing
+ *
+ * Copyright 2011 Wolfson Microelectronics plc
+ *      Mark Brown <broonie@opensource.wolfsonmicro.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/i2c.h>
+
+#include <linux/mfd/wm831x/irq.h>
+#include <linux/mfd/wm831x/gpio.h>
+
+#include <sound/wm8996.h>
+#include <sound/wm8962.h>
+#include <sound/wm9081.h>
+
+#include <mach/crag6410.h>
+
+static struct wm8996_retune_mobile_config wm8996_retune[] = {
+        {
+                .name = "Sub LPF",
+                .rate = 48000,
+                .regs = {
+                        0x6318, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
+                        0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
+                        0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
+                },
+        },
+        {
+                .name = "Sub HPF",
+                .rate = 48000,
+                .regs = {
+                        0x000A, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
+                        0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
+                        0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
+                },
+        },
+};
+
+static struct wm8996_pdata wm8996_pdata __initdata = {
+        .ldo_ena = S3C64XX_GPN(7),
+        .gpio_base = CODEC_GPIO_BASE,
+        .micdet_def = 1,
+        .inl_mode = WM8996_DIFFERRENTIAL_1,
+        .inr_mode = WM8996_DIFFERRENTIAL_1,
+
+        .irq_flags = IRQF_TRIGGER_RISING,
+
+        .gpio_default = {
+                0x8001, /* GPIO1 == ADCLRCLK1 */
+                0x8001, /* GPIO2 == ADCLRCLK2, input due to CPU */
+                0x0141, /* GPIO3 == HP_SEL */
+                0x0002, /* GPIO4 == IRQ */
+                0x020e, /* GPIO5 == CLKOUT */
+        },
+
+        .retune_mobile_cfgs = wm8996_retune,
+        .num_retune_mobile_cfgs = ARRAY_SIZE(wm8996_retune),
+};
+
+static struct wm8962_pdata wm8962_pdata __initdata = {
+        .gpio_init = {
+                0,
+                WM8962_GPIO_FN_OPCLK,
+                WM8962_GPIO_FN_DMICCLK,
+                0,
+                0x8000 | WM8962_GPIO_FN_DMICDAT,
+                WM8962_GPIO_FN_IRQ,    /* Open drain mode */
+        },
+        .irq_active_low = true,
+};
+
+static struct wm9081_pdata wm9081_pdata __initdata = {
+        .irq_high = false,
+        .irq_cmos = false,
+};
+
+static const struct i2c_board_info wm1254_devs[] = {
+        { I2C_BOARD_INFO("wm8996", 0x1a),
+          .platform_data = &wm8996_pdata,
+          .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
+        },
+        { I2C_BOARD_INFO("wm9081", 0x6c),
+          .platform_data = &wm9081_pdata, },
+};
+
+static const struct i2c_board_info wm1255_devs[] = {
+        { I2C_BOARD_INFO("wm5100", 0x1a),
+          .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
+        },
+        { I2C_BOARD_INFO("wm9081", 0x6c),
+          .platform_data = &wm9081_pdata, },
+};
+
+static const struct i2c_board_info wm1259_devs[] = {
+        { I2C_BOARD_INFO("wm8962", 0x1a),
+          .platform_data = &wm8962_pdata,
+          .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
+        },
+};
+
+
+static __devinitdata const struct {
+        u8 id;
+        const char *name;
+        const struct i2c_board_info *i2c_devs;
+        int num_i2c_devs;
+} gf_mods[] = {
+        { .id = 0x01, .name = "1250-EV1 Springbank" },
+        { .id = 0x02, .name = "1251-EV1 Jura" },
+        { .id = 0x03, .name = "1252-EV1 Glenlivet" },
+        { .id = 0x11, .name = "6249-EV2 Glenfarclas", },
+        { .id = 0x21, .name = "1275-EV1 Mortlach" },
+        { .id = 0x25, .name = "1274-EV1 Glencadam" },
+        { .id = 0x31, .name = "1253-EV1 Tomatin", },
+        { .id = 0x39, .name = "1254-EV1 Dallas Dhu",
+          .i2c_devs = wm1254_devs, .num_i2c_devs = ARRAY_SIZE(wm1254_devs) },
+        { .id = 0x3a, .name = "1259-EV1 Tobermory",
+          .i2c_devs = wm1259_devs, .num_i2c_devs = ARRAY_SIZE(wm1259_devs) },
+        { .id = 0x3b, .name = "1255-EV1 Kilchoman",
+          .i2c_devs = wm1255_devs, .num_i2c_devs = ARRAY_SIZE(wm1255_devs) },
+        { .id = 0x3c, .name = "1273-EV1 Longmorn" },
+};
+
+static __devinit int wlf_gf_module_probe(struct i2c_client *i2c,
+                                         const struct i2c_device_id *i2c_id)
+{
+        int ret, i, j, id, rev;
+
+        ret = i2c_smbus_read_byte_data(i2c, 0);
+        if (ret < 0) {
+                dev_err(&i2c->dev, "Failed to read ID: %d\n", ret);
+                return ret;
+        }
+
+        id = (ret & 0xfe) >> 2;
+        rev = ret & 0x3;
+        for (i = 0; i < ARRAY_SIZE(gf_mods); i++)
+                if (id == gf_mods[i].id)
+                        break;
+
+        if (i < ARRAY_SIZE(gf_mods)) {
+                dev_info(&i2c->dev, "%s revision %d\n",
+                         gf_mods[i].name, rev + 1);
+                for (j = 0; j < gf_mods[i].num_i2c_devs; j++) {
+                        if (!i2c_new_device(i2c->adapter,
+                                            &(gf_mods[i].i2c_devs[j])))
+                                dev_err(&i2c->dev,
+                                        "Failed to register dev: %d\n", ret);
+                }
+        } else {
+                dev_warn(&i2c->dev, "Unknown module ID %d revision %d\n",
+                         id, rev);
+        }
+
+        return 0;
+}
+
+static const struct i2c_device_id wlf_gf_module_id[] = {
+        { "wlf-gf-module", 0 },
+        { }
+};
+
+static struct i2c_driver wlf_gf_module_driver = {
+        .driver = {
+                .name = "wlf-gf-module",
+                .owner = THIS_MODULE,
+        },
+        .probe = wlf_gf_module_probe,
+        .id_table = wlf_gf_module_id,
+};
+
+static int __init wlf_gf_module_register(void)
+{
+        return i2c_add_driver(&wlf_gf_module_driver);
+}
+module_init(wlf_gf_module_register);
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index af0c2fe1ea37..fb3d9cd18156 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -43,13 +43,14 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
 
-#include <mach/s3c6410.h>
 #include <mach/regs-sys.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-modem.h>
+#include <mach/crag6410.h>
 
 #include <mach/regs-gpio-memport.h>
 
+#include <plat/s3c6410.h>
 #include <plat/regs-serial.h>
 #include <plat/regs-fb-v4.h>
 #include <plat/fb.h>
@@ -65,17 +66,6 @@
 #include <plat/iic.h>
 #include <plat/pm.h>
 
-#include <sound/wm8996.h>
-#include <sound/wm8962.h>
-#include <sound/wm9081.h>
-
-#define BANFF_PMIC_IRQ_BASE             IRQ_BOARD_START
-#define GLENFARCLAS_PMIC_IRQ_BASE       (IRQ_BOARD_START + 64)
-
-#define PCA935X_GPIO_BASE               GPIO_BOARD_START
-#define CODEC_GPIO_BASE         (GPIO_BOARD_START + 8)
-#define GLENFARCLAS_PMIC_GPIO_BASE      (GPIO_BOARD_START + 16)
-
 /* serial port setup */
 
 #define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
@@ -287,6 +277,11 @@ static struct platform_device speyside_device = {
         .id             = -1,
 };
 
+static struct platform_device lowland_device = {
+        .name           = "lowland",
+        .id             = -1,
+};
+
 static struct platform_device speyside_wm8962_device = {
         .name           = "speyside-wm8962",
         .id             = -1,
@@ -295,6 +290,8 @@ static struct platform_device speyside_wm8962_device = {
 static struct regulator_consumer_supply wallvdd_consumers[] = {
         REGULATOR_SUPPLY("SPKVDD1", "1-001a"),
         REGULATOR_SUPPLY("SPKVDD2", "1-001a"),
+        REGULATOR_SUPPLY("SPKVDDL", "1-001a"),
+        REGULATOR_SUPPLY("SPKVDDR", "1-001a"),
 };
 
 static struct regulator_init_data wallvdd_data = {
@@ -329,9 +326,6 @@ static struct platform_device *crag6410_devices[] __initdata = {
         &s3c_device_fb,
         &s3c_device_ohci,
         &s3c_device_usb_hsotg,
-        &s3c_device_adc,
-        &s3c_device_rtc,
-        &s3c_device_ts,
         &s3c_device_timer[0],
         &s3c64xx_device_iis0,
         &s3c64xx_device_iis1,
@@ -345,6 +339,7 @@ static struct platform_device *crag6410_devices[] __initdata = {
         &crag6410_backlight_device,
         &speyside_device,
         &speyside_wm8962_device,
+        &lowland_device,
         &wallvdd_device,
 };
 
@@ -353,6 +348,12 @@ static struct pca953x_platform_data crag6410_pca_data = {
         .irq_base       = 0,
 };
 
+/* VDDARM is controlled by DVS1 connected to GPK(0) */
+static struct wm831x_buckv_pdata vddarm_pdata = {
+        .dvs_control_src = 1,
+        .dvs_gpio = S3C64XX_GPK(0),
+};
+
 static struct regulator_consumer_supply vddarm_consumers[] __initdata = {
         REGULATOR_SUPPLY("vddarm", NULL),
 };
@@ -368,6 +369,7 @@ static struct regulator_init_data vddarm __initdata = {
         .num_consumer_supplies = ARRAY_SIZE(vddarm_consumers),
         .consumer_supplies = vddarm_consumers,
         .supply_regulator = "WALLVDD",
+        .driver_data = &vddarm_pdata,
 };
 
 static struct regulator_init_data vddint __initdata = {
@@ -503,6 +505,8 @@ static struct wm831x_pdata crag_pmic_pdata __initdata = {
         .backup = &banff_backup_pdata,
 
         .gpio_defaults = {
+                /* GPIO5: DVS1_REQ - CMOS, DBVDD, active high */
+                [4] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA | 0x8,
                 /* GPIO11: Touchscreen data - CMOS, DBVDD, active high*/
                 [10] = WM831X_GPN_POL | WM831X_GPN_ENA | 0x6,
                 /* GPIO12: Touchscreen pen down - CMOS, DBVDD, active high*/
@@ -560,8 +564,12 @@ static struct regulator_init_data pvdd_1v2 __initdata = {
 };
 
 static struct regulator_consumer_supply pvdd_1v8_consumers[] __initdata = {
+        REGULATOR_SUPPLY("LDOVDD", "1-001a"),
         REGULATOR_SUPPLY("PLLVDD", "1-001a"),
         REGULATOR_SUPPLY("DBVDD", "1-001a"),
+        REGULATOR_SUPPLY("DBVDD1", "1-001a"),
+        REGULATOR_SUPPLY("DBVDD2", "1-001a"),
+        REGULATOR_SUPPLY("DBVDD3", "1-001a"),
         REGULATOR_SUPPLY("CPVDD", "1-001a"),
         REGULATOR_SUPPLY("AVDD2", "1-001a"),
         REGULATOR_SUPPLY("DCVDD", "1-001a"),
@@ -614,81 +622,16 @@ static struct wm831x_pdata glenfarclas_pmic_pdata __initdata = {
         .disable_touch = true,
 };
 
-static struct wm8996_retune_mobile_config wm8996_retune[] = {
-        {
-                .name = "Sub LPF",
-                .rate = 48000,
-                .regs = {
-                        0x6318, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
-                        0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
-                        0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
-                },
-        },
-        {
-                .name = "Sub HPF",
-                .rate = 48000,
-                .regs = {
-                        0x000A, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
-                        0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
-                        0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
-                },
-        },
-};
-
-static struct wm8996_pdata wm8996_pdata __initdata = {
-        .ldo_ena = S3C64XX_GPN(7),
-        .gpio_base = CODEC_GPIO_BASE,
-        .micdet_def = 1,
-        .inl_mode = WM8996_DIFFERRENTIAL_1,
-        .inr_mode = WM8996_DIFFERRENTIAL_1,
-
-        .irq_flags = IRQF_TRIGGER_RISING,
-
-        .gpio_default = {
-                0x8001, /* GPIO1 == ADCLRCLK1 */
-                0x8001, /* GPIO2 == ADCLRCLK2, input due to CPU */
-                0x0141, /* GPIO3 == HP_SEL */
-                0x0002, /* GPIO4 == IRQ */
-                0x020e, /* GPIO5 == CLKOUT */
-        },
-
-        .retune_mobile_cfgs = wm8996_retune,
-        .num_retune_mobile_cfgs = ARRAY_SIZE(wm8996_retune),
-};
-
-static struct wm8962_pdata wm8962_pdata __initdata = {
-        .gpio_init = {
-                0,
-                WM8962_GPIO_FN_OPCLK,
-                WM8962_GPIO_FN_DMICCLK,
-                0,
-                0x8000 | WM8962_GPIO_FN_DMICDAT,
-                WM8962_GPIO_FN_IRQ,    /* Open drain mode */
-        },
-        .irq_active_low = true,
-};
-
-static struct wm9081_pdata wm9081_pdata __initdata = {
-        .irq_high = false,
-        .irq_cmos = false,
-};
-
 static struct i2c_board_info i2c_devs1[] __initdata = {
         { I2C_BOARD_INFO("wm8311", 0x34),
           .irq = S3C_EINT(0),
           .platform_data = &glenfarclas_pmic_pdata },
 
+        { I2C_BOARD_INFO("wlf-gf-module", 0x24) },
+        { I2C_BOARD_INFO("wlf-gf-module", 0x25) },
+        { I2C_BOARD_INFO("wlf-gf-module", 0x26) },
+
         { I2C_BOARD_INFO("wm1250-ev1", 0x27) },
-        { I2C_BOARD_INFO("wm8996", 0x1a),
-          .platform_data = &wm8996_pdata,
-          .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
-        },
-        { I2C_BOARD_INFO("wm9081", 0x6c),
-          .platform_data = &wm9081_pdata, },
-        { I2C_BOARD_INFO("wm8962", 0x1a),
-          .platform_data = &wm8962_pdata,
-          .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
-        },
 };
 
 static void __init crag6410_map_io(void)
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index b3d93cc8dde0..61f4fde088e9 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -37,7 +37,7 @@
 #include <plat/fb.h>
 #include <plat/nand.h>
 
-#include <mach/s3c6410.h>
+#include <plat/s3c6410.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index 527f49bd1b57..5abb6d442523 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -32,8 +32,8 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-modem.h>
 #include <mach/regs-srom.h>
-#include <mach/s3c6410.h>
 
+#include <plat/s3c6410.h>
 #include <plat/adc.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
@@ -205,12 +205,6 @@ static struct platform_device mini6410_lcd_powerdev = {
         .dev.platform_data      = &mini6410_lcd_power_data,
 };
 
-static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
-        .delay                  = 10000,
-        .presc                  = 49,
-        .oversampling_shift     = 2,
-};
-
 static struct platform_device *mini6410_devices[] __initdata = {
         &mini6410_device_eth,
         &s3c_device_hsmmc0,
@@ -319,7 +313,7 @@ static void __init mini6410_machine_init(void)
 
         s3c_nand_set_platdata(&mini6410_nand_info);
         s3c_fb_set_platdata(&mini6410_lcd_pdata);
-        s3c24xx_ts_set_platdata(&s3c_ts_platform);
+        s3c24xx_ts_set_platdata(NULL);
 
         /* configure nCS1 width to 16 bits */
 
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
index 01c6857c5b63..0f4316a2dc0b 100644
--- a/arch/arm/mach-s3c64xx/mach-ncp.c
+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
@@ -39,7 +39,7 @@
 #include <plat/iic.h>
 #include <plat/fb.h>
 
-#include <mach/s3c6410.h>
+#include <plat/s3c6410.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index 95b04b1729e3..1073d8105bab 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -33,8 +33,8 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-modem.h>
 #include <mach/regs-srom.h>
-#include <mach/s3c6410.h>
 
+#include <plat/s3c6410.h>
 #include <plat/adc.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
@@ -198,12 +198,6 @@ static struct platform_device *real6410_devices[] __initdata = {
         &s3c_device_ohci,
 };
 
-static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
-        .delay                  = 10000,
-        .presc                  = 49,
-        .oversampling_shift     = 2,
-};
-
 static void __init real6410_map_io(void)
 {
         u32 tmp;
@@ -300,7 +294,7 @@ static void __init real6410_machine_init(void)
 
         s3c_fb_set_platdata(&real6410_lcd_pdata);
         s3c_nand_set_platdata(&real6410_nand_info);
-        s3c24xx_ts_set_platdata(&s3c_ts_platform);
+        s3c24xx_ts_set_platdata(NULL);
 
         /* configure nCS1 width to 16 bits */
 
diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c
index 342e8dfddf8b..30e906b842ea 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq5.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq5.c
@@ -22,8 +22,8 @@
 
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
-#include <mach/s3c6410.h>
 
+#include <plat/s3c6410.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/fb.h>
diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c
index 57963977da8e..9a71c2bf610d 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq7.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq7.c
@@ -22,8 +22,8 @@
 
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
-#include <mach/s3c6410.h>
 
+#include <plat/s3c6410.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/fb.h>
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c
index 3cca642f1e6d..fc7cb03e188d 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6400.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c
@@ -31,7 +31,7 @@
 
 #include <plat/regs-serial.h>
 
-#include <mach/s3c6400.h>
+#include <plat/s3c6400.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index ecbea92bf83b..a817d629c0e9 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -63,7 +63,7 @@
 #include <plat/fb.h>
 #include <plat/gpio-cfg.h>
 
-#include <mach/s3c6410.h>
+#include <plat/s3c6410.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
@@ -262,45 +262,6 @@ static struct samsung_keypad_platdata smdk6410_keypad_data __initdata = {
         .cols           = 8,
 };
 
-static int smdk6410_backlight_init(struct device *dev)
-{
-        int ret;
-
-        ret = gpio_request(S3C64XX_GPF(15), "Backlight");
-        if (ret) {
-                printk(KERN_ERR "failed to request GPF for PWM-OUT1\n");
-                return ret;
-        }
-
-        /* Configure GPIO pin with S3C64XX_GPF15_PWM_TOUT1 */
-        s3c_gpio_cfgpin(S3C64XX_GPF(15), S3C_GPIO_SFN(2));
-
-        return 0;
-}
-
-static void smdk6410_backlight_exit(struct device *dev)
-{
-        s3c_gpio_cfgpin(S3C64XX_GPF(15), S3C_GPIO_OUTPUT);
-        gpio_free(S3C64XX_GPF(15));
-}
-
-static struct platform_pwm_backlight_data smdk6410_backlight_data = {
-        .pwm_id         = 1,
-        .max_brightness = 255,
-        .dft_brightness = 255,
-        .pwm_period_ns  = 78770,
-        .init           = smdk6410_backlight_init,
-        .exit           = smdk6410_backlight_exit,
-};
-
-static struct platform_device smdk6410_backlight_device = {
-        .name           = "pwm-backlight",
-        .dev            = {
-                .parent         = &s3c_device_timer[1].dev,
-                .platform_data  = &smdk6410_backlight_data,
-        },
-};
-
 static struct map_desc smdk6410_iodesc[] = {};
 
 static struct platform_device *smdk6410_devices[] __initdata = {
@@ -658,12 +619,6 @@ static struct i2c_board_info i2c_devs1[] __initdata = {
         { I2C_BOARD_INFO("24c128", 0x57), },    /* Samsung S524AD0XD1 */
 };
 
-static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
-        .delay                  = 10000,
-        .presc                  = 49,
-        .oversampling_shift     = 2,
-};
-
 /* LCD Backlight data */
 static struct samsung_bl_gpio_info smdk6410_bl_gpio_info = {
         .no = S3C64XX_GPF(15),
@@ -705,7 +660,7 @@ static void __init smdk6410_machine_init(void)
 
         samsung_keypad_set_platdata(&smdk6410_keypad_data);
 
-        s3c24xx_ts_set_platdata(&s3c_ts_platform);
+        s3c24xx_ts_set_platdata(NULL);
 
         /* configure nCS1 width to 16 bits */
 
diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
index 055e2858b0dd..b375cd5c47cb 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c64xx/pm.c
@@ -29,6 +29,7 @@
 #include <mach/regs-clock.h>
 #include <mach/regs-syscon-power.h>
 #include <mach/regs-gpio-memport.h>
+#include <mach/regs-modem.h>
 
 #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
 void s3c_pm_debug_smdkled(u32 set, u32 clear)
@@ -85,6 +86,9 @@ static struct sleep_save misc_save[] = {
         SAVE_ITEM(S3C64XX_MEM0CONSLP0),
         SAVE_ITEM(S3C64XX_MEM0CONSLP1),
         SAVE_ITEM(S3C64XX_MEM1CONSLP),
+
+        SAVE_ITEM(S3C64XX_SDMA_SEL),
+        SAVE_ITEM(S3C64XX_MODEM_MIFPCON),
 };
 
 void s3c_pm_configure_extint(void)
diff --git a/arch/arm/mach-s3c64xx/s3c6400.c b/arch/arm/mach-s3c64xx/s3c6400.c
index 5e93fe3f3f40..7a3bc32df425 100644
--- a/arch/arm/mach-s3c64xx/s3c6400.c
+++ b/arch/arm/mach-s3c64xx/s3c6400.c
@@ -38,7 +38,7 @@
 #include <plat/sdhci.h>
 #include <plat/iic-core.h>
 #include <plat/onenand-core.h>
-#include <mach/s3c6400.h>
+#include <plat/s3c6400.h>
 
 void __init s3c6400_map_io(void)
 {
diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c
index 312aa6b115e8..4117003464ad 100644
--- a/arch/arm/mach-s3c64xx/s3c6410.c
+++ b/arch/arm/mach-s3c64xx/s3c6410.c
@@ -41,8 +41,8 @@
 #include <plat/adc-core.h>
 #include <plat/iic-core.h>
 #include <plat/onenand-core.h>
-#include <mach/s3c6400.h>
-#include <mach/s3c6410.h>
+#include <plat/s3c6400.h>
+#include <plat/s3c6410.h>
 
 void __init s3c6410_map_io(void)
 {
diff --git a/arch/arm/mach-s3c64xx/setup-sdhci.c b/arch/arm/mach-s3c64xx/setup-sdhci.c
index f344a222bc84..c75a71b21165 100644
--- a/arch/arm/mach-s3c64xx/setup-sdhci.c
+++ b/arch/arm/mach-s3c64xx/setup-sdhci.c
@@ -12,17 +12,7 @@
  * published by the Free Software Foundation.
 */
 
-#include <linux/kernel.h>
 #include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-
-#include <linux/mmc/card.h>
-#include <linux/mmc/host.h>
-
-#include <plat/regs-sdhci.h>
-#include <plat/sdhci.h>
 
 /* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
 
@@ -32,41 +22,3 @@ char *s3c64xx_hsmmc_clksrcs[4] = {
         [2] = "mmc_bus",
         /* [3] = "48m", - note not successfully used yet */
 };
-
-void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,
-                                  void __iomem *r,
-                                  struct mmc_ios *ios,
-                                  struct mmc_card *card)
-{
-        u32 ctrl2, ctrl3;
-
-        ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
-        ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
-        ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
-                  S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
-                  S3C_SDHCI_CTRL2_ENFBCLKRX |
-                  S3C_SDHCI_CTRL2_DFCNT_NONE |
-                  S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
-
-        if (ios->clock < 25 * 1000000)
-                ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
-                         S3C_SDHCI_CTRL3_FCSEL2 |
-                         S3C_SDHCI_CTRL3_FCSEL1 |
-                         S3C_SDHCI_CTRL3_FCSEL0);
-        else
-                ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
-
-        pr_debug("%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3);
-        writel(ctrl2, r + S3C_SDHCI_CONTROL2);
-        writel(ctrl3, r + S3C_SDHCI_CONTROL3);
-}
-
-void s3c6410_setup_sdhci_cfg_card(struct platform_device *dev,
-                                  void __iomem *r,
-                                  struct mmc_ios *ios,
-                                  struct mmc_card *card)
-{
-        writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);
-
-        s3c6400_setup_sdhci_cfg_card(dev, r, ios, card);
-}
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
index 65c7518dad7f..18690c5f99e6 100644
--- a/arch/arm/mach-s5p64x0/Kconfig
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -9,18 +9,28 @@ if ARCH_S5P64X0
 
 config CPU_S5P6440
         bool
-        select S3C_PL330_DMA
+        select SAMSUNG_DMADEV
         select S5P_HRT
+        select S5P_SLEEP if PM
+        select SAMSUNG_WAKEMASK if PM
         help
           Enable S5P6440 CPU support
 
 config CPU_S5P6450
         bool
-        select S3C_PL330_DMA
+        select SAMSUNG_DMADEV
         select S5P_HRT
+        select S5P_SLEEP if PM
+        select SAMSUNG_WAKEMASK if PM
         help
           Enable S5P6450 CPU support
 
+config S5P64X0_SETUP_FB_24BPP
+        bool
+        help
+          Common setup code for S5P64X0 based boards with a LCD display
+          through RGB interface.
+
 config S5P64X0_SETUP_I2C1
         bool
         help
@@ -31,6 +41,7 @@ config S5P64X0_SETUP_I2C1
 config MACH_SMDK6440
         bool "SMDK6440"
         select CPU_S5P6440
+        select S3C_DEV_FB
         select S3C_DEV_I2C1
         select S3C_DEV_RTC
         select S3C_DEV_WDT
@@ -39,6 +50,7 @@ config MACH_SMDK6440
         select SAMSUNG_DEV_BACKLIGHT
         select SAMSUNG_DEV_PWM
         select SAMSUNG_DEV_TS
+        select S5P64X0_SETUP_FB_24BPP
         select S5P64X0_SETUP_I2C1
         help
           Machine support for the Samsung SMDK6440
@@ -46,6 +58,7 @@ config MACH_SMDK6440
 config MACH_SMDK6450
         bool "SMDK6450"
         select CPU_S5P6450
+        select S3C_DEV_FB
         select S3C_DEV_I2C1
         select S3C_DEV_RTC
         select S3C_DEV_WDT
@@ -54,6 +67,7 @@ config MACH_SMDK6450
         select SAMSUNG_DEV_BACKLIGHT
         select SAMSUNG_DEV_PWM
         select SAMSUNG_DEV_TS
+        select S5P64X0_SETUP_FB_24BPP
         select S5P64X0_SETUP_I2C1
         help
           Machine support for the Samsung SMDK6450
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile
index 5f6afdf067ed..a1324d8dc4e0 100644
--- a/arch/arm/mach-s5p64x0/Makefile
+++ b/arch/arm/mach-s5p64x0/Makefile
@@ -12,10 +12,11 @@ obj-				:=
 
 # Core support for S5P64X0 system
 
-obj-$(CONFIG_ARCH_S5P64X0)      += cpu.o init.o clock.o dma.o gpiolib.o
+obj-$(CONFIG_ARCH_S5P64X0)      += cpu.o init.o clock.o dma.o
 obj-$(CONFIG_ARCH_S5P64X0)      += setup-i2c0.o irq-eint.o
 obj-$(CONFIG_CPU_S5P6440)       += clock-s5p6440.o
 obj-$(CONFIG_CPU_S5P6450)       += clock-s5p6450.o
+obj-$(CONFIG_PM)                += pm.o irq-pm.o
 
 # machine support
 
@@ -28,3 +29,4 @@ obj-y				+= dev-audio.o
 obj-$(CONFIG_S3C64XX_DEV_SPI)   += dev-spi.o
 
 obj-$(CONFIG_S5P64X0_SETUP_I2C1)        += setup-i2c1.o
+obj-$(CONFIG_S5P64X0_SETUP_FB_24BPP)    += setup-fb-24bpp.o
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index 0e9cd3092dd2..c54c65d511f0 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -146,7 +146,8 @@ static struct clk init_clocks_off[] = {
                 .enable         = s5p64x0_hclk0_ctrl,
                 .ctrlbit        = (1 << 8),
         }, {
-                .name           = "pdma",
+                .name           = "dma",
+                .devname        = "dma-pl330",
                 .parent         = &clk_hclk_low.clk,
                 .enable         = s5p64x0_hclk0_ctrl,
                 .ctrlbit        = (1 << 12),
@@ -499,6 +500,11 @@ static struct clksrc_clk *sysclks[] = {
         &clk_pclk_low,
 };
 
+static struct clk dummy_apb_pclk = {
+        .name           = "apb_pclk",
+        .id             = -1,
+};
+
 void __init_or_cpufreq s5p6440_setup_clocks(void)
 {
         struct clk *xtal_clk;
@@ -581,5 +587,7 @@ void __init s5p6440_register_clocks(void)
         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 
+        s3c24xx_register_clock(&dummy_apb_pclk);
+
         s3c_pwmclk_init();
 }
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index d9dc16cde109..2d04abfba12e 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -179,7 +179,8 @@ static struct clk init_clocks_off[] = {
                 .enable         = s5p64x0_hclk0_ctrl,
                 .ctrlbit        = (1 << 3),
         }, {
-                .name           = "pdma",
+                .name           = "dma",
+                .devname        = "dma-pl330",
                 .parent         = &clk_hclk_low.clk,
                 .enable         = s5p64x0_hclk0_ctrl,
                 .ctrlbit        = (1 << 12),
@@ -553,6 +554,11 @@ static struct clksrc_clk *sysclks[] = {
         &clk_sclk_audio0,
 };
 
+static struct clk dummy_apb_pclk = {
+        .name           = "apb_pclk",
+        .id             = -1,
+};
+
 void __init_or_cpufreq s5p6450_setup_clocks(void)
 {
         struct clk *xtal_clk;
@@ -632,5 +638,7 @@ void __init s5p6450_register_clocks(void)
         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 
+        s3c24xx_register_clock(&dummy_apb_pclk);
+
         s3c_pwmclk_init();
 }
diff --git a/arch/arm/mach-s5p64x0/cpu.c b/arch/arm/mach-s5p64x0/cpu.c
index a5c00952ea35..617da3b3bfb7 100644
--- a/arch/arm/mach-s5p64x0/cpu.c
+++ b/arch/arm/mach-s5p64x0/cpu.c
@@ -38,6 +38,7 @@
 #include <plat/s5p6440.h>
 #include <plat/s5p6450.h>
 #include <plat/adc-core.h>
+#include <plat/fb-core.h>
 
 /* Initial IO mappings */
 
@@ -108,6 +109,7 @@ void __init s5p6440_map_io(void)
 {
         /* initialize any device information early */
         s3c_adc_setname("s3c64xx-adc");
+        s3c_fb_setname("s5p64x0-fb");
 
         iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
         iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
@@ -117,6 +119,7 @@ void __init s5p6450_map_io(void)
 {
         /* initialize any device information early */
         s3c_adc_setname("s3c64xx-adc");
+        s3c_fb_setname("s5p64x0-fb");
 
         iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
         iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
diff --git a/arch/arm/mach-s5p64x0/dev-spi.c b/arch/arm/mach-s5p64x0/dev-spi.c
index ac825e826326..1fd9c79c7dbc 100644
--- a/arch/arm/mach-s5p64x0/dev-spi.c
+++ b/arch/arm/mach-s5p64x0/dev-spi.c
@@ -21,6 +21,7 @@
 #include <mach/regs-clock.h>
 #include <mach/spi-clocks.h>
 
+#include <plat/cpu.h>
 #include <plat/s3c64xx-spi.h>
 #include <plat/gpio-cfg.h>
 
@@ -185,11 +186,8 @@ struct platform_device s5p64x0_device_spi1 = {
 
 void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
 {
-        unsigned int id;
         struct s3c64xx_spi_info *pd;
 
-        id = __raw_readl(S5P64X0_SYS_ID) & 0xFF000;
-
         /* Reject invalid configuration */
         if (!num_cs || src_clk_nr < 0
                         || src_clk_nr > S5P64X0_SPI_SRCCLK_SCLK) {
@@ -199,7 +197,7 @@ void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
 
         switch (cntrlr) {
         case 0:
-                if (id == 0x50000)
+                if (soc_is_s5p6450())
                         pd = &s5p6450_spi0_pdata;
                 else
                         pd = &s5p6440_spi0_pdata;
@@ -207,7 +205,7 @@ void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
                 s5p64x0_device_spi0.dev.platform_data = pd;
                 break;
         case 1:
-                if (id == 0x50000)
+                if (soc_is_s5p6450())
                         pd = &s5p6450_spi1_pdata;
                 else
                         pd = &s5p6440_spi1_pdata;
diff --git a/arch/arm/mach-s5p64x0/dma.c b/arch/arm/mach-s5p64x0/dma.c
index d7ad944b3475..442dd4ad12da 100644
--- a/arch/arm/mach-s5p64x0/dma.c
+++ b/arch/arm/mach-s5p64x0/dma.c
@@ -21,128 +21,218 @@
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */
 
-#include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/pl330.h>
+
+#include <asm/irq.h>
 
 #include <mach/map.h>
 #include <mach/irqs.h>
 #include <mach/regs-clock.h>
+#include <mach/dma.h>
 
+#include <plat/cpu.h>
 #include <plat/devs.h>
-#include <plat/s3c-pl330-pdata.h>
+#include <plat/irqs.h>
 
 static u64 dma_dmamask = DMA_BIT_MASK(32);
 
-static struct resource s5p64x0_pdma_resource[] = {
-        [0] = {
-                .start  = S5P64X0_PA_PDMA,
-                .end    = S5P64X0_PA_PDMA + SZ_4K,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_DMA0,
-                .end    = IRQ_DMA0,
-                .flags  = IORESOURCE_IRQ,
+struct dma_pl330_peri s5p6440_pdma_peri[22] = {
+        {
+                .peri_id = (u8)DMACH_UART0_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART0_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_UART1_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART1_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_UART2_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART2_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_UART3_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART3_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = DMACH_MAX,
+        }, {
+                .peri_id = DMACH_MAX,
+        }, {
+                .peri_id = (u8)DMACH_PCM0_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_PCM0_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_I2S0_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_I2S0_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_SPI0_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_SPI0_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_MAX,
+        }, {
+                .peri_id = (u8)DMACH_MAX,
+        }, {
+                .peri_id = (u8)DMACH_MAX,
+        }, {
+                .peri_id = (u8)DMACH_MAX,
+        }, {
+                .peri_id = (u8)DMACH_SPI1_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_SPI1_RX,
+                .rqtype = DEVTOMEM,
         },
 };
 
-static struct s3c_pl330_platdata s5p6440_pdma_pdata = {
-        .peri = {
-                [0] = DMACH_UART0_RX,
-                [1] = DMACH_UART0_TX,
-                [2] = DMACH_UART1_RX,
-                [3] = DMACH_UART1_TX,
-                [4] = DMACH_UART2_RX,
-                [5] = DMACH_UART2_TX,
-                [6] = DMACH_UART3_RX,
-                [7] = DMACH_UART3_TX,
-                [8] = DMACH_MAX,
-                [9] = DMACH_MAX,
-                [10] = DMACH_PCM0_TX,
-                [11] = DMACH_PCM0_RX,
-                [12] = DMACH_I2S0_TX,
-                [13] = DMACH_I2S0_RX,
-                [14] = DMACH_SPI0_TX,
-                [15] = DMACH_SPI0_RX,
-                [16] = DMACH_MAX,
-                [17] = DMACH_MAX,
-                [18] = DMACH_MAX,
-                [19] = DMACH_MAX,
-                [20] = DMACH_SPI1_TX,
-                [21] = DMACH_SPI1_RX,
-                [22] = DMACH_MAX,
-                [23] = DMACH_MAX,
-                [24] = DMACH_MAX,
-                [25] = DMACH_MAX,
-                [26] = DMACH_MAX,
-                [27] = DMACH_MAX,
-                [28] = DMACH_MAX,
-                [29] = DMACH_PWM,
-                [30] = DMACH_MAX,
-                [31] = DMACH_MAX,
-        },
+struct dma_pl330_platdata s5p6440_pdma_pdata = {
+        .nr_valid_peri = ARRAY_SIZE(s5p6440_pdma_peri),
+        .peri = s5p6440_pdma_peri,
 };
 
-static struct s3c_pl330_platdata s5p6450_pdma_pdata = {
-        .peri = {
-                [0] = DMACH_UART0_RX,
-                [1] = DMACH_UART0_TX,
-                [2] = DMACH_UART1_RX,
-                [3] = DMACH_UART1_TX,
-                [4] = DMACH_UART2_RX,
-                [5] = DMACH_UART2_TX,
-                [6] = DMACH_UART3_RX,
-                [7] = DMACH_UART3_TX,
-                [8] = DMACH_UART4_RX,
-                [9] = DMACH_UART4_TX,
-                [10] = DMACH_PCM0_TX,
-                [11] = DMACH_PCM0_RX,
-                [12] = DMACH_I2S0_TX,
-                [13] = DMACH_I2S0_RX,
-                [14] = DMACH_SPI0_TX,
-                [15] = DMACH_SPI0_RX,
-                [16] = DMACH_PCM1_TX,
-                [17] = DMACH_PCM1_RX,
-                [18] = DMACH_PCM2_TX,
-                [19] = DMACH_PCM2_RX,
-                [20] = DMACH_SPI1_TX,
-                [21] = DMACH_SPI1_RX,
-                [22] = DMACH_USI_TX,
-                [23] = DMACH_USI_RX,
-                [24] = DMACH_MAX,
-                [25] = DMACH_I2S1_TX,
-                [26] = DMACH_I2S1_RX,
-                [27] = DMACH_I2S2_TX,
-                [28] = DMACH_I2S2_RX,
-                [29] = DMACH_PWM,
-                [30] = DMACH_UART5_RX,
-                [31] = DMACH_UART5_TX,
+struct dma_pl330_peri s5p6450_pdma_peri[32] = {
+        {
+                .peri_id = (u8)DMACH_UART0_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART0_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_UART1_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART1_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_UART2_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART2_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_UART3_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART3_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_UART4_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART4_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_PCM0_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_PCM0_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_I2S0_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_I2S0_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_SPI0_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_SPI0_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_PCM1_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_PCM1_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_PCM2_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_PCM2_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_SPI1_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_SPI1_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_USI_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_USI_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_MAX,
+        }, {
+                .peri_id = (u8)DMACH_I2S1_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_I2S1_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_I2S2_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_I2S2_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_PWM,
+        }, {
+                .peri_id = (u8)DMACH_UART5_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART5_TX,
+                .rqtype = MEMTODEV,
         },
 };
 
-static struct platform_device s5p64x0_device_pdma = {
-        .name           = "s3c-pl330",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(s5p64x0_pdma_resource),
-        .resource       = s5p64x0_pdma_resource,
-        .dev            = {
+struct dma_pl330_platdata s5p6450_pdma_pdata = {
+        .nr_valid_peri = ARRAY_SIZE(s5p6450_pdma_peri),
+        .peri = s5p6450_pdma_peri,
+};
+
+struct amba_device s5p64x0_device_pdma = {
+        .dev = {
+                .init_name = "dma-pl330",
                 .dma_mask = &dma_dmamask,
                 .coherent_dma_mask = DMA_BIT_MASK(32),
         },
+        .res = {
+                .start = S5P64X0_PA_PDMA,
+                .end = S5P64X0_PA_PDMA + SZ_4K,
+                .flags = IORESOURCE_MEM,
+        },
+        .irq = {IRQ_DMA0, NO_IRQ},
+        .periphid = 0x00041330,
 };
 
 static int __init s5p64x0_dma_init(void)
 {
-        unsigned int id;
-
-        id = __raw_readl(S5P64X0_SYS_ID) & 0xFF000;
-
-        if (id == 0x50000)
+        if (soc_is_s5p6450())
                 s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata;
         else
                 s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata;
 
-        platform_device_register(&s5p64x0_device_pdma);
+        amba_device_register(&s5p64x0_device_pdma, &iomem_resource);
 
         return 0;
 }
diff --git a/arch/arm/mach-s5p64x0/gpiolib.c b/arch/arm/mach-s5p64x0/gpiolib.c
index e7fb3b004e77..700dac6c43f3 100644
--- a/arch/arm/mach-s5p64x0/gpiolib.c
+++ b/arch/arm/mach-s5p64x0/gpiolib.c
@@ -19,6 +19,7 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-clock.h>
 
+#include <plat/cpu.h>
 #include <plat/gpio-core.h>
 #include <plat/gpio-cfg.h>
 #include <plat/gpio-cfg-helpers.h>
@@ -473,14 +474,10 @@ static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
 
 static int __init s5p64x0_gpiolib_init(void)
 {
-        unsigned int chipid;
-
-        chipid = __raw_readl(S5P64X0_SYS_ID);
-
         s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs,
                                 ARRAY_SIZE(s5p64x0_gpio_cfgs));
 
-        if ((chipid & 0xff000) == 0x50000) {
+        if (soc_is_s5p6450()) {
                 samsung_gpiolib_add_2bit_chips(s5p6450_gpio_2bit,
                                         ARRAY_SIZE(s5p6450_gpio_2bit));
 
diff --git a/arch/arm/mach-s5p64x0/include/mach/clkdev.h b/arch/arm/mach-s5p64x0/include/mach/clkdev.h
deleted file mode 100644
index 7dffa83d23ff..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __MACH_CLKDEV_H__
-#define __MACH_CLKDEV_H__
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do {} while (0)
-
-#endif
diff --git a/arch/arm/mach-s5p64x0/include/mach/dma.h b/arch/arm/mach-s5p64x0/include/mach/dma.h
index 81209eb1409b..5a622af461d7 100644
--- a/arch/arm/mach-s5p64x0/include/mach/dma.h
+++ b/arch/arm/mach-s5p64x0/include/mach/dma.h
@@ -20,7 +20,7 @@
 #ifndef __MACH_DMA_H
 #define __MACH_DMA_H
 
-/* This platform uses the common S3C DMA API driver for PL330 */
-#include <plat/s3c-dma-pl330.h>
+/* This platform uses the common common DMA API driver for PL330 */
+#include <plat/dma-pl330.h>
 
 #endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/irqs.h b/arch/arm/mach-s5p64x0/include/mach/irqs.h
index 5837a36ece8d..53982db9d259 100644
--- a/arch/arm/mach-s5p64x0/include/mach/irqs.h
+++ b/arch/arm/mach-s5p64x0/include/mach/irqs.h
@@ -87,6 +87,10 @@
 
 #define IRQ_I2S0                IRQ_I2SV40
 
+#define IRQ_LCD_FIFO            IRQ_DISPCON0
+#define IRQ_LCD_VSYNC           IRQ_DISPCON1
+#define IRQ_LCD_SYSTEM          IRQ_DISPCON2
+
 /* S5P6450 EINT feature will be added */
 
 /*
diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h
index 95c91257c7ca..4d3ac8a3709d 100644
--- a/arch/arm/mach-s5p64x0/include/mach/map.h
+++ b/arch/arm/mach-s5p64x0/include/mach/map.h
@@ -47,6 +47,8 @@
 
 #define S5P64X0_PA_HSMMC(x)     (0xED800000 + ((x) * 0x100000))
 
+#define S5P64X0_PA_FB           0xEE000000
+
 #define S5P64X0_PA_I2S          0xF2000000
 #define S5P6450_PA_I2S1         0xF2800000
 #define S5P6450_PA_I2S2         0xF2900000
@@ -64,6 +66,7 @@
 #define S3C_PA_IIC1             S5P6440_PA_IIC1
 #define S3C_PA_RTC              S5P64X0_PA_RTC
 #define S3C_PA_WDT              S5P64X0_PA_WDT
+#define S3C_PA_FB               S5P64X0_PA_FB
 
 #define S5P_PA_CHIPID           S5P64X0_PA_CHIPID
 #define S5P_PA_SROMC            S5P64X0_PA_SROMC
@@ -85,5 +88,6 @@
 #define S5P_PA_UART5            S5P6450_PA_UART(5)
 
 #define S5P_SZ_UART             SZ_256
+#define S3C_VA_UARTx(x)         (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
 
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/pm-core.h b/arch/arm/mach-s5p64x0/include/mach/pm-core.h
new file mode 100644
index 000000000000..e52f7545d3aa
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/pm-core.h
@@ -0,0 +1,117 @@
+/* linux/arch/arm/mach-s5p64x0/include/mach/pm-core.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 - PM core support for arch/arm/plat-samsung/pm.c
+ *
+ * Based on PM core support for S3C64XX by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <mach/regs-gpio.h>
+
+static inline void s3c_pm_debug_init_uart(void)
+{
+        u32 tmp = __raw_readl(S5P64X0_CLK_GATE_PCLK);
+
+        /*
+         * As a note, since the S5P64X0 UARTs generally have multiple
+         * clock sources, we simply enable PCLK at the moment and hope
+         * that the resume settings for the UART are suitable for the
+         * use with PCLK.
+         */
+        tmp |= S5P64X0_CLK_GATE_PCLK_UART0;
+        tmp |= S5P64X0_CLK_GATE_PCLK_UART1;
+        tmp |= S5P64X0_CLK_GATE_PCLK_UART2;
+        tmp |= S5P64X0_CLK_GATE_PCLK_UART3;
+
+        __raw_writel(tmp, S5P64X0_CLK_GATE_PCLK);
+        udelay(10);
+}
+
+static inline void s3c_pm_arch_prepare_irqs(void)
+{
+        /* VIC should have already been taken care of */
+
+        /* clear any pending EINT0 interrupts */
+        __raw_writel(__raw_readl(S5P64X0_EINT0PEND), S5P64X0_EINT0PEND);
+}
+
+static inline void s3c_pm_arch_stop_clocks(void) { }
+static inline void s3c_pm_arch_show_resume_irqs(void) { }
+
+/*
+ * make these defines, we currently do not have any need to change
+ * the IRQ wake controls depending on the CPU we are running on
+ */
+#define s3c_irqwake_eintallow   ((1 << 16) - 1)
+#define s3c_irqwake_intallow    (~0)
+
+static inline void s3c_pm_arch_update_uart(void __iomem *regs,
+                                        struct pm_uart_save *save)
+{
+        u32 ucon = __raw_readl(regs + S3C2410_UCON);
+        u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK;
+        u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK;
+        u32 new_ucon;
+        u32 delta;
+
+        /*
+         * S5P64X0 UART blocks only support level interrupts, so ensure that
+         * when we restore unused UART blocks we force the level interrupt
+         * settings.
+         */
+        save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL;
+
+        /*
+         * We have a constraint on changing the clock type of the UART
+         * between UCLKx and PCLK, so ensure that when we restore UCON
+         * that the CLK field is correctly modified if the bootloader
+         * has changed anything.
+         */
+        if (ucon_clk != save_clk) {
+                new_ucon = save->ucon;
+                delta = ucon_clk ^ save_clk;
+
+                /*
+                 * change from UCLKx => wrong PCLK,
+                 * either UCLK can be tested for by a bit-test
+                 * with UCLK0
+                 */
+                if (ucon_clk & S3C6400_UCON_UCLK0 &&
+                !(save_clk & S3C6400_UCON_UCLK0) &&
+                delta & S3C6400_UCON_PCLK2) {
+                        new_ucon &= ~S3C6400_UCON_UCLK0;
+                } else if (delta == S3C6400_UCON_PCLK2) {
+                        /*
+                         * as a precaution, don't change from
+                         * PCLK2 => PCLK or vice-versa
+                         */
+                        new_ucon ^= S3C6400_UCON_PCLK2;
+                }
+
+                S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n",
+                        ucon, new_ucon, save->ucon);
+                save->ucon = new_ucon;
+        }
+}
+
+static inline void s3c_pm_restored_gpios(void)
+{
+        /* ensure sleep mode has been cleared from the system */
+        __raw_writel(0, S5P64X0_SLPEN);
+}
+
+static inline void samsung_pm_saved_gpios(void)
+{
+        /*
+         * turn on the sleep mode and keep it there, as it seems that during
+         * suspend the xCON registers get re-set and thus you can end up with
+         * problems between going to sleep and resuming.
+         */
+        __raw_writel(S5P64X0_SLPEN_USE_xSLP, S5P64X0_SLPEN);
+}
diff --git a/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h b/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
deleted file mode 100644
index 19fff8b701c0..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S5P64X0 - pwm clock and timer support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_PWMCLK_H
-#define __ASM_ARCH_PWMCLK_H __FILE__
-
-/**
- * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
- * @tcfg: The timer TCFG1 register bits shifted down to 0.
- *
- * Return true if the given configuration from TCFG1 is a TCLK instead
- * any of the TDIV clocks.
- */
-static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
-{
-        return 0;
-}
-
-/**
- * tcfg_to_divisor() - convert tcfg1 setting to a divisor
- * @tcfg1: The tcfg1 setting, shifted down.
- *
- * Get the divisor value for the given tcfg1 setting. We assume the
- * caller has already checked to see if this is not a TCLK source.
- */
-static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
-{
-        return 1 << tcfg1;
-}
-
-/**
- * pwm_tdiv_has_div1() - does the tdiv setting have a /1
- *
- * Return true if we have a /1 in the tdiv setting.
- */
-static inline unsigned int pwm_tdiv_has_div1(void)
-{
-        return 1;
-}
-
-/**
- * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
- * @div: The divisor to calculate the bit information for.
- *
- * Turn a divisor into the necessary bit field for TCFG1.
- */
-static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
-{
-        return ilog2(div);
-}
-
-#define S3C_TCFG1_MUX_TCLK 0
-
-#endif /* __ASM_ARCH_PWMCLK_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
index a133f22fa155..bd91112c813c 100644
--- a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
@@ -41,17 +41,50 @@
 #define S5P6450_DPLL_CON                S5P_CLKREG(0x50)
 #define S5P6450_DPLL_CON_K              S5P_CLKREG(0x54)
 
+#define S5P64X0_AHB_CON0                S5P_CLKREG(0x100)
 #define S5P64X0_CLK_SRC1                S5P_CLKREG(0x10C)
 
 #define S5P64X0_SYS_ID                  S5P_CLKREG(0x118)
 #define S5P64X0_SYS_OTHERS              S5P_CLKREG(0x11C)
 
 #define S5P64X0_PWR_CFG                 S5P_CLKREG(0x804)
+#define S5P64X0_EINT_WAKEUP_MASK        S5P_CLKREG(0x808)
+#define S5P64X0_SLEEP_CFG               S5P_CLKREG(0x818)
+#define S5P64X0_PWR_STABLE              S5P_CLKREG(0x828)
+
 #define S5P64X0_OTHERS                  S5P_CLKREG(0x900)
+#define S5P64X0_WAKEUP_STAT             S5P_CLKREG(0x908)
+
+#define S5P64X0_INFORM0                 S5P_CLKREG(0xA00)
 
 #define S5P64X0_CLKDIV0_HCLK_SHIFT      (8)
 #define S5P64X0_CLKDIV0_HCLK_MASK       (0xF << S5P64X0_CLKDIV0_HCLK_SHIFT)
 
+/* HCLK GATE Registers */
+#define S5P64X0_CLK_GATE_HCLK1_FIMGVG   (1 << 2)
+#define S5P64X0_CLK_GATE_SCLK1_FIMGVG   (1 << 2)
+
+/* PCLK GATE Registers */
+#define S5P64X0_CLK_GATE_PCLK_UART3     (1 << 4)
+#define S5P64X0_CLK_GATE_PCLK_UART2     (1 << 3)
+#define S5P64X0_CLK_GATE_PCLK_UART1     (1 << 2)
+#define S5P64X0_CLK_GATE_PCLK_UART0     (1 << 1)
+
+#define S5P64X0_PWR_CFG_MMC1_DISABLE            (1 << 15)
+#define S5P64X0_PWR_CFG_MMC0_DISABLE            (1 << 14)
+#define S5P64X0_PWR_CFG_RTC_TICK_DISABLE        (1 << 11)
+#define S5P64X0_PWR_CFG_RTC_ALRM_DISABLE        (1 << 10)
+#define S5P64X0_PWR_CFG_WFI_MASK                (3 << 5)
+#define S5P64X0_PWR_CFG_WFI_SLEEP               (3 << 5)
+
+#define S5P64X0_SLEEP_CFG_OSC_EN        (1 << 0)
+
+#define S5P64X0_PWR_STABLE_PWR_CNT_VAL4 (4 << 0)
+
+#define S5P6450_OTHERS_DISABLE_INT      (1 << 31)
+#define S5P64X0_OTHERS_RET_UART         (1 << 26)
+#define S5P64X0_OTHERS_RET_MMC1         (1 << 25)
+#define S5P64X0_OTHERS_RET_MMC0         (1 << 24)
 #define S5P64X0_OTHERS_USB_SIG_MASK     (1 << 16)
 
 /* Compatibility defines */
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
index 6ce254729f3b..cfdfa4fdadf2 100644
--- a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
@@ -34,14 +34,35 @@
 #define S5P6450_GPQ_BASE                (S5P_VA_GPIO + 0x0180)
 #define S5P6450_GPS_BASE                (S5P_VA_GPIO + 0x0300)
 
+#define S5P64X0_SPCON0                  (S5P_VA_GPIO + 0x1A0)
+#define S5P64X0_SPCON0_LCD_SEL_MASK     (0x3 << 0)
+#define S5P64X0_SPCON0_LCD_SEL_RGB      (0x1 << 0)
+#define S5P64X0_SPCON1                  (S5P_VA_GPIO + 0x2B0)
+
+#define S5P64X0_MEM0CONSLP0             (S5P_VA_GPIO + 0x1C0)
+#define S5P64X0_MEM0CONSLP1             (S5P_VA_GPIO + 0x1C4)
+#define S5P64X0_MEM0DRVCON              (S5P_VA_GPIO + 0x1D0)
+#define S5P64X0_MEM1DRVCON              (S5P_VA_GPIO + 0x1D4)
+
+#define S5P64X0_EINT12CON               (S5P_VA_GPIO + 0x200)
+#define S5P64X0_EINT12FLTCON            (S5P_VA_GPIO + 0x220)
+#define S5P64X0_EINT12MASK              (S5P_VA_GPIO + 0x240)
+
 /* External interrupt control registers for group0 */
 
 #define EINT0CON0_OFFSET                (0x900)
+#define EINT0FLTCON0_OFFSET             (0x910)
+#define EINT0FLTCON1_OFFSET             (0x914)
 #define EINT0MASK_OFFSET                (0x920)
 #define EINT0PEND_OFFSET                (0x924)
 
 #define S5P64X0_EINT0CON0               (S5P_VA_GPIO + EINT0CON0_OFFSET)
+#define S5P64X0_EINT0FLTCON0            (S5P_VA_GPIO + EINT0FLTCON0_OFFSET)
+#define S5P64X0_EINT0FLTCON1            (S5P_VA_GPIO + EINT0FLTCON1_OFFSET)
 #define S5P64X0_EINT0MASK               (S5P_VA_GPIO + EINT0MASK_OFFSET)
 #define S5P64X0_EINT0PEND               (S5P_VA_GPIO + EINT0PEND_OFFSET)
 
+#define S5P64X0_SLPEN                   (S5P_VA_GPIO + 0x930)
+#define S5P64X0_SLPEN_USE_xSLP          (1 << 0)
+
 #endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-s5p64x0/irq-eint.c b/arch/arm/mach-s5p64x0/irq-eint.c
index fe7380f5c3cd..275dc74f4a7b 100644
--- a/arch/arm/mach-s5p64x0/irq-eint.c
+++ b/arch/arm/mach-s5p64x0/irq-eint.c
@@ -17,8 +17,10 @@
 #include <linux/irq.h>
 #include <linux/io.h>
 
+#include <plat/cpu.h>
 #include <plat/regs-irqtype.h>
 #include <plat/gpio-cfg.h>
+#include <plat/pm.h>
 
 #include <mach/regs-gpio.h>
 #include <mach/regs-clock.h>
@@ -67,7 +69,7 @@ static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
         __raw_writel(ctrl, S5P64X0_EINT0CON0);
 
         /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
-        if (0x50000 == (__raw_readl(S5P64X0_SYS_ID) & 0xFF000))
+        if (soc_is_s5p6450())
                 s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
         else
                 s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
@@ -133,6 +135,7 @@ static int s5p64x0_alloc_gc(void)
         ct->chip.irq_mask = irq_gc_mask_set_bit;
         ct->chip.irq_unmask = irq_gc_mask_clr_bit;
         ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
+        ct->chip.irq_set_wake = s3c_irqext_wake;
         ct->regs.ack = EINT0PEND_OFFSET;
         ct->regs.mask = EINT0MASK_OFFSET;
         irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
diff --git a/arch/arm/mach-s5p64x0/irq-pm.c b/arch/arm/mach-s5p64x0/irq-pm.c
new file mode 100644
index 000000000000..3e6f2456ee9d
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/irq-pm.c
@@ -0,0 +1,92 @@
+/* linux/arch/arm/mach-s5p64x0/irq-pm.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 - Interrupt handling Power Management
+ *
+ * Based on arch/arm/mach-s3c64xx/irq-pm.c by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/syscore_ops.h>
+#include <linux/serial_core.h>
+#include <linux/io.h>
+
+#include <plat/regs-serial.h>
+#include <plat/pm.h>
+
+#include <mach/regs-gpio.h>
+
+static struct sleep_save irq_save[] = {
+        SAVE_ITEM(S5P64X0_EINT0CON0),
+        SAVE_ITEM(S5P64X0_EINT0FLTCON0),
+        SAVE_ITEM(S5P64X0_EINT0FLTCON1),
+        SAVE_ITEM(S5P64X0_EINT0MASK),
+};
+
+static struct irq_grp_save {
+        u32     con;
+        u32     fltcon;
+        u32     mask;
+} eint_grp_save[4];
+
+static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS];
+
+static int s5p64x0_irq_pm_suspend(void)
+{
+        struct irq_grp_save *grp = eint_grp_save;
+        int i;
+
+        S3C_PMDBG("%s: suspending IRQs\n", __func__);
+
+        s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
+
+        for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
+                irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM);
+
+        for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
+                grp->con = __raw_readl(S5P64X0_EINT12CON + (i * 4));
+                grp->mask = __raw_readl(S5P64X0_EINT12MASK + (i * 4));
+                grp->fltcon = __raw_readl(S5P64X0_EINT12FLTCON + (i * 4));
+        }
+
+        return 0;
+}
+
+static void s5p64x0_irq_pm_resume(void)
+{
+        struct irq_grp_save *grp = eint_grp_save;
+        int i;
+
+        S3C_PMDBG("%s: resuming IRQs\n", __func__);
+
+        s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
+
+        for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
+                __raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM);
+
+        for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
+                __raw_writel(grp->con, S5P64X0_EINT12CON + (i * 4));
+                __raw_writel(grp->mask, S5P64X0_EINT12MASK + (i * 4));
+                __raw_writel(grp->fltcon, S5P64X0_EINT12FLTCON + (i * 4));
+        }
+
+        S3C_PMDBG("%s: IRQ configuration restored\n", __func__);
+}
+
+static struct syscore_ops s5p64x0_irq_syscore_ops = {
+        .suspend = s5p64x0_irq_pm_suspend,
+        .resume  = s5p64x0_irq_pm_resume,
+};
+
+static int __init s5p64x0_syscore_init(void)
+{
+        register_syscore_ops(&s5p64x0_irq_syscore_ops);
+
+        return 0;
+}
+core_initcall(s5p64x0_syscore_init);
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 346f8dfa6f35..b0465d4e84e7 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -23,6 +23,9 @@
 #include <linux/clk.h>
 #include <linux/gpio.h>
 #include <linux/pwm_backlight.h>
+#include <linux/fb.h>
+
+#include <video/platform_lcd.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -47,6 +50,8 @@
 #include <plat/ts.h>
 #include <plat/s5p-time.h>
 #include <plat/backlight.h>
+#include <plat/fb.h>
+#include <plat/regs-fb.h>
 
 #define SMDK6440_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
                                 S3C2410_UCON_RXILEVEL |         \
@@ -92,6 +97,59 @@ static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = {
         },
 };
 
+/* Frame Buffer */
+static struct s3c_fb_pd_win smdk6440_fb_win0 = {
+        .win_mode = {
+                .left_margin    = 8,
+                .right_margin   = 13,
+                .upper_margin   = 7,
+                .lower_margin   = 5,
+                .hsync_len      = 3,
+                .vsync_len      = 1,
+                .xres           = 800,
+                .yres           = 480,
+        },
+        .max_bpp        = 32,
+        .default_bpp    = 24,
+};
+
+static struct s3c_fb_platdata smdk6440_lcd_pdata __initdata = {
+        .win[0]         = &smdk6440_fb_win0,
+        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+        .setup_gpio     = s5p64x0_fb_gpio_setup_24bpp,
+};
+
+/* LCD power controller */
+static void smdk6440_lte480_reset_power(struct plat_lcd_data *pd,
+                                         unsigned int power)
+{
+        int err;
+
+        if (power) {
+                err = gpio_request(S5P6440_GPN(5), "GPN");
+                if (err) {
+                        printk(KERN_ERR "failed to request GPN for lcd reset\n");
+                        return;
+                }
+
+                gpio_direction_output(S5P6440_GPN(5), 1);
+                gpio_set_value(S5P6440_GPN(5), 0);
+                gpio_set_value(S5P6440_GPN(5), 1);
+                gpio_free(S5P6440_GPN(5));
+        }
+}
+
+static struct plat_lcd_data smdk6440_lcd_power_data = {
+        .set_power      = smdk6440_lte480_reset_power,
+};
+
+static struct platform_device smdk6440_lcd_lte480wv = {
+        .name                   = "platform-lcd",
+        .dev.parent             = &s3c_device_fb.dev,
+        .dev.platform_data      = &smdk6440_lcd_power_data,
+};
+
 static struct platform_device *smdk6440_devices[] __initdata = {
         &s3c_device_adc,
         &s3c_device_rtc,
@@ -101,6 +159,8 @@ static struct platform_device *smdk6440_devices[] __initdata = {
         &s3c_device_wdt,
         &samsung_asoc_dma,
         &s5p6440_device_iis,
+        &s3c_device_fb,
+        &smdk6440_lcd_lte480wv,
 };
 
 static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = {
@@ -129,12 +189,6 @@ static struct i2c_board_info smdk6440_i2c_devs1[] __initdata = {
         /* To be populated */
 };
 
-static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
-        .delay                  = 10000,
-        .presc                  = 49,
-        .oversampling_shift     = 2,
-};
-
 /* LCD Backlight data */
 static struct samsung_bl_gpio_info smdk6440_bl_gpio_info = {
         .no = S5P6440_GPF(15),
@@ -153,9 +207,20 @@ static void __init smdk6440_map_io(void)
         s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
 }
 
+static void s5p6440_set_lcd_interface(void)
+{
+        unsigned int cfg;
+
+        /* select TFT LCD type (RGB I/F) */
+        cfg = __raw_readl(S5P64X0_SPCON0);
+        cfg &= ~S5P64X0_SPCON0_LCD_SEL_MASK;
+        cfg |= S5P64X0_SPCON0_LCD_SEL_RGB;
+        __raw_writel(cfg, S5P64X0_SPCON0);
+}
+
 static void __init smdk6440_machine_init(void)
 {
-        s3c24xx_ts_set_platdata(&s3c_ts_platform);
+        s3c24xx_ts_set_platdata(NULL);
 
         s3c_i2c0_set_platdata(&s5p6440_i2c0_data);
         s3c_i2c1_set_platdata(&s5p6440_i2c1_data);
@@ -166,6 +231,9 @@ static void __init smdk6440_machine_init(void)
 
         samsung_bl_set(&smdk6440_bl_gpio_info, &smdk6440_bl_data);
 
+        s5p6440_set_lcd_interface();
+        s3c_fb_set_platdata(&smdk6440_lcd_pdata);
+
         platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices));
 }
 
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index 33f2adf8f3fe..2a69caa70afd 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -23,6 +23,9 @@
 #include <linux/clk.h>
 #include <linux/gpio.h>
 #include <linux/pwm_backlight.h>
+#include <linux/fb.h>
+
+#include <video/platform_lcd.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -47,6 +50,8 @@
 #include <plat/ts.h>
 #include <plat/s5p-time.h>
 #include <plat/backlight.h>
+#include <plat/fb.h>
+#include <plat/regs-fb.h>
 
 #define SMDK6450_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
                                 S3C2410_UCON_RXILEVEL |         \
@@ -110,6 +115,59 @@ static struct s3c2410_uartcfg smdk6450_uartcfgs[] __initdata = {
 #endif
 };
 
+/* Frame Buffer */
+static struct s3c_fb_pd_win smdk6450_fb_win0 = {
+        .win_mode       = {
+                .left_margin    = 8,
+                .right_margin   = 13,
+                .upper_margin   = 7,
+                .lower_margin   = 5,
+                .hsync_len      = 3,
+                .vsync_len      = 1,
+                .xres           = 800,
+                .yres           = 480,
+        },
+        .max_bpp        = 32,
+        .default_bpp    = 24,
+};
+
+static struct s3c_fb_platdata smdk6450_lcd_pdata __initdata = {
+        .win[0]         = &smdk6450_fb_win0,
+        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+        .setup_gpio     = s5p64x0_fb_gpio_setup_24bpp,
+};
+
+/* LCD power controller */
+static void smdk6450_lte480_reset_power(struct plat_lcd_data *pd,
+                                         unsigned int power)
+{
+        int err;
+
+        if (power) {
+                err = gpio_request(S5P6450_GPN(5), "GPN");
+                if (err) {
+                        printk(KERN_ERR "failed to request GPN for lcd reset\n");
+                        return;
+                }
+
+                gpio_direction_output(S5P6450_GPN(5), 1);
+                gpio_set_value(S5P6450_GPN(5), 0);
+                gpio_set_value(S5P6450_GPN(5), 1);
+                gpio_free(S5P6450_GPN(5));
+        }
+}
+
+static struct plat_lcd_data smdk6450_lcd_power_data = {
+        .set_power      = smdk6450_lte480_reset_power,
+};
+
+static struct platform_device smdk6450_lcd_lte480wv = {
+        .name                   = "platform-lcd",
+        .dev.parent             = &s3c_device_fb.dev,
+        .dev.platform_data      = &smdk6450_lcd_power_data,
+};
+
 static struct platform_device *smdk6450_devices[] __initdata = {
         &s3c_device_adc,
         &s3c_device_rtc,
@@ -119,6 +177,9 @@ static struct platform_device *smdk6450_devices[] __initdata = {
         &s3c_device_wdt,
         &samsung_asoc_dma,
         &s5p6450_device_iis0,
+        &s3c_device_fb,
+        &smdk6450_lcd_lte480wv,
+
         /* s5p6450_device_spi0 will be added */
 };
 
@@ -148,12 +209,6 @@ static struct i2c_board_info smdk6450_i2c_devs1[] __initdata = {
         { I2C_BOARD_INFO("24c128", 0x57), },/* Samsung S524AD0XD1 EEPROM */
 };
 
-static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
-        .delay                  = 10000,
-        .presc                  = 49,
-        .oversampling_shift     = 2,
-};
-
 /* LCD Backlight data */
 static struct samsung_bl_gpio_info smdk6450_bl_gpio_info = {
         .no = S5P6450_GPF(15),
@@ -172,9 +227,20 @@ static void __init smdk6450_map_io(void)
         s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
 }
 
+static void s5p6450_set_lcd_interface(void)
+{
+        unsigned int cfg;
+
+        /* select TFT LCD type (RGB I/F) */
+        cfg = __raw_readl(S5P64X0_SPCON0);
+        cfg &= ~S5P64X0_SPCON0_LCD_SEL_MASK;
+        cfg |= S5P64X0_SPCON0_LCD_SEL_RGB;
+        __raw_writel(cfg, S5P64X0_SPCON0);
+}
+
 static void __init smdk6450_machine_init(void)
 {
-        s3c24xx_ts_set_platdata(&s3c_ts_platform);
+        s3c24xx_ts_set_platdata(NULL);
 
         s3c_i2c0_set_platdata(&s5p6450_i2c0_data);
         s3c_i2c1_set_platdata(&s5p6450_i2c1_data);
@@ -185,6 +251,9 @@ static void __init smdk6450_machine_init(void)
 
         samsung_bl_set(&smdk6450_bl_gpio_info, &smdk6450_bl_data);
 
+        s5p6450_set_lcd_interface();
+        s3c_fb_set_platdata(&smdk6450_lcd_pdata);
+
         platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices));
 }
 
diff --git a/arch/arm/mach-s5p64x0/pm.c b/arch/arm/mach-s5p64x0/pm.c
new file mode 100644
index 000000000000..69927243d25f
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/pm.c
@@ -0,0 +1,204 @@
+/* linux/arch/arm/mach-s5p64x0/pm.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P64X0 Power Management Support
+ *
+ * Based on arch/arm/mach-s3c64xx/pm.c by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/suspend.h>
+#include <linux/syscore_ops.h>
+#include <linux/io.h>
+
+#include <plat/cpu.h>
+#include <plat/pm.h>
+#include <plat/regs-timer.h>
+#include <plat/wakeup-mask.h>
+
+#include <mach/regs-clock.h>
+#include <mach/regs-gpio.h>
+
+static struct sleep_save s5p64x0_core_save[] = {
+        SAVE_ITEM(S5P64X0_APLL_CON),
+        SAVE_ITEM(S5P64X0_MPLL_CON),
+        SAVE_ITEM(S5P64X0_EPLL_CON),
+        SAVE_ITEM(S5P64X0_EPLL_CON_K),
+        SAVE_ITEM(S5P64X0_CLK_SRC0),
+        SAVE_ITEM(S5P64X0_CLK_SRC1),
+        SAVE_ITEM(S5P64X0_CLK_DIV0),
+        SAVE_ITEM(S5P64X0_CLK_DIV1),
+        SAVE_ITEM(S5P64X0_CLK_DIV2),
+        SAVE_ITEM(S5P64X0_CLK_DIV3),
+        SAVE_ITEM(S5P64X0_CLK_GATE_MEM0),
+        SAVE_ITEM(S5P64X0_CLK_GATE_HCLK1),
+        SAVE_ITEM(S5P64X0_CLK_GATE_SCLK1),
+};
+
+static struct sleep_save s5p64x0_misc_save[] = {
+        SAVE_ITEM(S5P64X0_AHB_CON0),
+        SAVE_ITEM(S5P64X0_SPCON0),
+        SAVE_ITEM(S5P64X0_SPCON1),
+        SAVE_ITEM(S5P64X0_MEM0CONSLP0),
+        SAVE_ITEM(S5P64X0_MEM0CONSLP1),
+        SAVE_ITEM(S5P64X0_MEM0DRVCON),
+        SAVE_ITEM(S5P64X0_MEM1DRVCON),
+
+        SAVE_ITEM(S3C64XX_TINT_CSTAT),
+};
+
+/* DPLL is present only in S5P6450 */
+static struct sleep_save s5p6450_core_save[] = {
+        SAVE_ITEM(S5P6450_DPLL_CON),
+        SAVE_ITEM(S5P6450_DPLL_CON_K),
+};
+
+void s3c_pm_configure_extint(void)
+{
+        __raw_writel(s3c_irqwake_eintmask, S5P64X0_EINT_WAKEUP_MASK);
+}
+
+void s3c_pm_restore_core(void)
+{
+        __raw_writel(0, S5P64X0_EINT_WAKEUP_MASK);
+
+        s3c_pm_do_restore_core(s5p64x0_core_save,
+                                ARRAY_SIZE(s5p64x0_core_save));
+
+        if (soc_is_s5p6450())
+                s3c_pm_do_restore_core(s5p6450_core_save,
+                                ARRAY_SIZE(s5p6450_core_save));
+
+        s3c_pm_do_restore(s5p64x0_misc_save, ARRAY_SIZE(s5p64x0_misc_save));
+}
+
+void s3c_pm_save_core(void)
+{
+        s3c_pm_do_save(s5p64x0_misc_save, ARRAY_SIZE(s5p64x0_misc_save));
+
+        if (soc_is_s5p6450())
+                s3c_pm_do_save(s5p6450_core_save,
+                                ARRAY_SIZE(s5p6450_core_save));
+
+        s3c_pm_do_save(s5p64x0_core_save, ARRAY_SIZE(s5p64x0_core_save));
+}
+
+static int s5p64x0_cpu_suspend(unsigned long arg)
+{
+        unsigned long tmp = 0;
+
+        /*
+         * Issue the standby signal into the pm unit. Note, we
+         * issue a write-buffer drain just in case.
+         */
+        asm("b 1f\n\t"
+            ".align 5\n\t"
+            "1:\n\t"
+            "mcr p15, 0, %0, c7, c10, 5\n\t"
+            "mcr p15, 0, %0, c7, c10, 4\n\t"
+            "mcr p15, 0, %0, c7, c0, 4" : : "r" (tmp));
+
+        /* we should never get past here */
+        panic("sleep resumed to originator?");
+}
+
+/* mapping of interrupts to parts of the wakeup mask */
+static struct samsung_wakeup_mask s5p64x0_wake_irqs[] = {
+        { .irq = IRQ_RTC_ALARM, .bit = S5P64X0_PWR_CFG_RTC_ALRM_DISABLE, },
+        { .irq = IRQ_RTC_TIC,   .bit = S5P64X0_PWR_CFG_RTC_TICK_DISABLE, },
+        { .irq = IRQ_HSMMC0,    .bit = S5P64X0_PWR_CFG_MMC0_DISABLE, },
+        { .irq = IRQ_HSMMC1,    .bit = S5P64X0_PWR_CFG_MMC1_DISABLE, },
+};
+
+static void s5p64x0_pm_prepare(void)
+{
+        u32 tmp;
+
+        samsung_sync_wakemask(S5P64X0_PWR_CFG,
+                        s5p64x0_wake_irqs, ARRAY_SIZE(s5p64x0_wake_irqs));
+
+        /* store the resume address in INFORM0 register */
+        __raw_writel(virt_to_phys(s3c_cpu_resume), S5P64X0_INFORM0);
+
+        /* setup clock gating for FIMGVG block */
+        __raw_writel((__raw_readl(S5P64X0_CLK_GATE_HCLK1) | \
+                (S5P64X0_CLK_GATE_HCLK1_FIMGVG)), S5P64X0_CLK_GATE_HCLK1);
+        __raw_writel((__raw_readl(S5P64X0_CLK_GATE_SCLK1) | \
+                (S5P64X0_CLK_GATE_SCLK1_FIMGVG)), S5P64X0_CLK_GATE_SCLK1);
+
+        /* Configure the stabilization counter with wait time required */
+        __raw_writel(S5P64X0_PWR_STABLE_PWR_CNT_VAL4, S5P64X0_PWR_STABLE);
+
+        /* set WFI to SLEEP mode configuration */
+        tmp = __raw_readl(S5P64X0_SLEEP_CFG);
+        tmp &= ~(S5P64X0_SLEEP_CFG_OSC_EN);
+        __raw_writel(tmp, S5P64X0_SLEEP_CFG);
+
+        tmp = __raw_readl(S5P64X0_PWR_CFG);
+        tmp &= ~(S5P64X0_PWR_CFG_WFI_MASK);
+        tmp |= S5P64X0_PWR_CFG_WFI_SLEEP;
+        __raw_writel(tmp, S5P64X0_PWR_CFG);
+
+        /*
+         * set OTHERS register to disable interrupt before going to
+         * sleep. This bit is present only in S5P6450, it is reserved
+         * in S5P6440.
+         */
+        if (soc_is_s5p6450()) {
+                tmp = __raw_readl(S5P64X0_OTHERS);
+                tmp |= S5P6450_OTHERS_DISABLE_INT;
+                __raw_writel(tmp, S5P64X0_OTHERS);
+        }
+
+        /* ensure previous wakeup state is cleared before sleeping */
+        __raw_writel(__raw_readl(S5P64X0_WAKEUP_STAT), S5P64X0_WAKEUP_STAT);
+
+}
+
+static int s5p64x0_pm_add(struct sys_device *sysdev)
+{
+        pm_cpu_prep = s5p64x0_pm_prepare;
+        pm_cpu_sleep = s5p64x0_cpu_suspend;
+        pm_uart_udivslot = 1;
+
+        return 0;
+}
+
+static struct sysdev_driver s5p64x0_pm_driver = {
+        .add            = s5p64x0_pm_add,
+};
+
+static __init int s5p64x0_pm_drvinit(void)
+{
+        s3c_pm_init();
+
+        return sysdev_driver_register(&s5p64x0_sysclass, &s5p64x0_pm_driver);
+}
+arch_initcall(s5p64x0_pm_drvinit);
+
+static void s5p64x0_pm_resume(void)
+{
+        u32 tmp;
+
+        tmp = __raw_readl(S5P64X0_OTHERS);
+        tmp |= (S5P64X0_OTHERS_RET_MMC0 | S5P64X0_OTHERS_RET_MMC1 | \
+                        S5P64X0_OTHERS_RET_UART);
+        __raw_writel(tmp , S5P64X0_OTHERS);
+}
+
+static struct syscore_ops s5p64x0_pm_syscore_ops = {
+        .resume         = s5p64x0_pm_resume,
+};
+
+static __init int s5p64x0_pm_syscore_init(void)
+{
+        register_syscore_ops(&s5p64x0_pm_syscore_ops);
+
+        return 0;
+}
+arch_initcall(s5p64x0_pm_syscore_init);
diff --git a/arch/arm/mach-s5p64x0/setup-fb-24bpp.c b/arch/arm/mach-s5p64x0/setup-fb-24bpp.c
new file mode 100644
index 000000000000..f346ee4af54d
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/setup-fb-24bpp.c
@@ -0,0 +1,29 @@
+/* linux/arch/arm/mach-s5p64x0/setup-fb-24bpp.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com/
+ *
+ * Base S5P64X0 GPIO setup information for LCD framebuffer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/fb.h>
+#include <linux/gpio.h>
+
+#include <plat/cpu.h>
+#include <plat/fb.h>
+#include <plat/gpio-cfg.h>
+
+void s5p64x0_fb_gpio_setup_24bpp(void)
+{
+        if (soc_is_s5p6440()) {
+                s3c_gpio_cfgrange_nopull(S5P6440_GPI(0), 16, S3C_GPIO_SFN(2));
+                s3c_gpio_cfgrange_nopull(S5P6440_GPJ(0), 12, S3C_GPIO_SFN(2));
+        } else if (soc_is_s5p6450()) {
+                s3c_gpio_cfgrange_nopull(S5P6450_GPI(0), 16, S3C_GPIO_SFN(2));
+                s3c_gpio_cfgrange_nopull(S5P6450_GPJ(0), 12, S3C_GPIO_SFN(2));
+        }
+}
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index e8a33c4b054c..e538a4c67e9c 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -10,7 +10,7 @@ if ARCH_S5PC100
 config CPU_S5PC100
         bool
         select S5P_EXT_INT
-        select S3C_PL330_DMA
+        select SAMSUNG_DMADEV
         help
           Enable S5PC100 CPU support
 
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index ff5cbb30de5b..8d47709da713 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -33,6 +33,11 @@ static struct clk s5p_clk_otgphy = {
         .name           = "otg_phy",
 };
 
+static struct clk dummy_apb_pclk = {
+        .name           = "apb_pclk",
+        .id             = -1,
+};
+
 static struct clk *clk_src_mout_href_list[] = {
         [0] = &s5p_clk_27m,
         [1] = &clk_fin_hpll,
@@ -454,14 +459,14 @@ static struct clk init_clocks_off[] = {
                 .enable         = s5pc100_d1_0_ctrl,
                 .ctrlbit        = (1 << 2),
         }, {
-                .name           = "pdma",
-                .devname        = "s3c-pl330.1",
+                .name           = "dma",
+                .devname        = "dma-pl330.1",
                 .parent         = &clk_div_d1_bus.clk,
                 .enable         = s5pc100_d1_0_ctrl,
                 .ctrlbit        = (1 << 1),
         }, {
-                .name           = "pdma",
-                .devname        = "s3c-pl330.0",
+                .name           = "dma",
+                .devname        = "dma-pl330.0",
                 .parent         = &clk_div_d1_bus.clk,
                 .enable         = s5pc100_d1_0_ctrl,
                 .ctrlbit        = (1 << 0),
@@ -1276,5 +1281,7 @@ void __init s5pc100_register_clocks(void)
         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 
+        s3c24xx_register_clock(&dummy_apb_pclk);
+
         s3c_pwmclk_init();
 }
diff --git a/arch/arm/mach-s5pc100/dma.c b/arch/arm/mach-s5pc100/dma.c
index bf4cd0fb97c6..065a087f5a8b 100644
--- a/arch/arm/mach-s5pc100/dma.c
+++ b/arch/arm/mach-s5pc100/dma.c
@@ -1,4 +1,8 @@
-/*
+/* linux/arch/arm/mach-s5pc100/dma.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
  * Copyright (C) 2010 Samsung Electronics Co. Ltd.
  *      Jaswinder Singh <jassi.brar@samsung.com>
  *
@@ -17,150 +21,246 @@
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
-#include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/pl330.h>
 
+#include <asm/irq.h>
 #include <plat/devs.h>
+#include <plat/irqs.h>
 
 #include <mach/map.h>
 #include <mach/irqs.h>
-
-#include <plat/s3c-pl330-pdata.h>
+#include <mach/dma.h>
 
 static u64 dma_dmamask = DMA_BIT_MASK(32);
 
-static struct resource s5pc100_pdma0_resource[] = {
-        [0] = {
-                .start  = S5PC100_PA_PDMA0,
-                .end    = S5PC100_PA_PDMA0 + SZ_4K,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_PDMA0,
-                .end    = IRQ_PDMA0,
-                .flags  = IORESOURCE_IRQ,
+struct dma_pl330_peri pdma0_peri[30] = {
+        {
+                .peri_id = (u8)DMACH_UART0_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART0_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_UART1_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART1_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_UART2_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART2_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_UART3_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART3_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = DMACH_IRDA,
+        }, {
+                .peri_id = (u8)DMACH_I2S0_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_I2S0_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_I2S0S_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_I2S1_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_I2S1_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_I2S2_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_I2S2_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_SPI0_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_SPI0_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_SPI1_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_SPI1_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_SPI2_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_SPI2_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_AC97_MICIN,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_AC97_PCMIN,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_AC97_PCMOUT,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_EXTERNAL,
+        }, {
+                .peri_id = (u8)DMACH_PWM,
+        }, {
+                .peri_id = (u8)DMACH_SPDIF,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_HSI_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_HSI_TX,
+                .rqtype = MEMTODEV,
         },
 };
 
-static struct s3c_pl330_platdata s5pc100_pdma0_pdata = {
-        .peri = {
-                [0] = DMACH_UART0_RX,
-                [1] = DMACH_UART0_TX,
-                [2] = DMACH_UART1_RX,
-                [3] = DMACH_UART1_TX,
-                [4] = DMACH_UART2_RX,
-                [5] = DMACH_UART2_TX,
-                [6] = DMACH_UART3_RX,
-                [7] = DMACH_UART3_TX,
-                [8] = DMACH_IRDA,
-                [9] = DMACH_I2S0_RX,
-                [10] = DMACH_I2S0_TX,
-                [11] = DMACH_I2S0S_TX,
-                [12] = DMACH_I2S1_RX,
-                [13] = DMACH_I2S1_TX,
-                [14] = DMACH_I2S2_RX,
-                [15] = DMACH_I2S2_TX,
-                [16] = DMACH_SPI0_RX,
-                [17] = DMACH_SPI0_TX,
-                [18] = DMACH_SPI1_RX,
-                [19] = DMACH_SPI1_TX,
-                [20] = DMACH_SPI2_RX,
-                [21] = DMACH_SPI2_TX,
-                [22] = DMACH_AC97_MICIN,
-                [23] = DMACH_AC97_PCMIN,
-                [24] = DMACH_AC97_PCMOUT,
-                [25] = DMACH_EXTERNAL,
-                [26] = DMACH_PWM,
-                [27] = DMACH_SPDIF,
-                [28] = DMACH_HSI_RX,
-                [29] = DMACH_HSI_TX,
-                [30] = DMACH_MAX,
-                [31] = DMACH_MAX,
-        },
+struct dma_pl330_platdata s5pc100_pdma0_pdata = {
+        .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
+        .peri = pdma0_peri,
 };
 
-static struct platform_device s5pc100_device_pdma0 = {
-        .name           = "s3c-pl330",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(s5pc100_pdma0_resource),
-        .resource       = s5pc100_pdma0_resource,
-        .dev            = {
+struct amba_device s5pc100_device_pdma0 = {
+        .dev = {
+                .init_name = "dma-pl330.0",
                 .dma_mask = &dma_dmamask,
                 .coherent_dma_mask = DMA_BIT_MASK(32),
                 .platform_data = &s5pc100_pdma0_pdata,
         },
-};
-
-static struct resource s5pc100_pdma1_resource[] = {
-        [0] = {
-                .start  = S5PC100_PA_PDMA1,
-                .end    = S5PC100_PA_PDMA1 + SZ_4K,
+        .res = {
+                .start = S5PC100_PA_PDMA0,
+                .end = S5PC100_PA_PDMA0 + SZ_4K,
                 .flags = IORESOURCE_MEM,
         },
-        [1] = {
-                .start  = IRQ_PDMA1,
-                .end    = IRQ_PDMA1,
-                .flags  = IORESOURCE_IRQ,
-        },
+        .irq = {IRQ_PDMA0, NO_IRQ},
+        .periphid = 0x00041330,
 };
 
-static struct s3c_pl330_platdata s5pc100_pdma1_pdata = {
-        .peri = {
-                [0] = DMACH_UART0_RX,
-                [1] = DMACH_UART0_TX,
-                [2] = DMACH_UART1_RX,
-                [3] = DMACH_UART1_TX,
-                [4] = DMACH_UART2_RX,
-                [5] = DMACH_UART2_TX,
-                [6] = DMACH_UART3_RX,
-                [7] = DMACH_UART3_TX,
-                [8] = DMACH_IRDA,
-                [9] = DMACH_I2S0_RX,
-                [10] = DMACH_I2S0_TX,
-                [11] = DMACH_I2S0S_TX,
-                [12] = DMACH_I2S1_RX,
-                [13] = DMACH_I2S1_TX,
-                [14] = DMACH_I2S2_RX,
-                [15] = DMACH_I2S2_TX,
-                [16] = DMACH_SPI0_RX,
-                [17] = DMACH_SPI0_TX,
-                [18] = DMACH_SPI1_RX,
-                [19] = DMACH_SPI1_TX,
-                [20] = DMACH_SPI2_RX,
-                [21] = DMACH_SPI2_TX,
-                [22] = DMACH_PCM0_RX,
-                [23] = DMACH_PCM0_TX,
-                [24] = DMACH_PCM1_RX,
-                [25] = DMACH_PCM1_TX,
-                [26] = DMACH_MSM_REQ0,
-                [27] = DMACH_MSM_REQ1,
-                [28] = DMACH_MSM_REQ2,
-                [29] = DMACH_MSM_REQ3,
-                [30] = DMACH_MAX,
-                [31] = DMACH_MAX,
+struct dma_pl330_peri pdma1_peri[30] = {
+        {
+                .peri_id = (u8)DMACH_UART0_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART0_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_UART1_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART1_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_UART2_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART2_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_UART3_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART3_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = DMACH_IRDA,
+        }, {
+                .peri_id = (u8)DMACH_I2S0_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_I2S0_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_I2S0S_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_I2S1_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_I2S1_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_I2S2_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_I2S2_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_SPI0_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_SPI0_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_SPI1_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_SPI1_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_SPI2_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_SPI2_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_PCM0_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_PCM1_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_PCM1_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_PCM1_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_MSM_REQ0,
+        }, {
+                .peri_id = (u8)DMACH_MSM_REQ1,
+        }, {
+                .peri_id = (u8)DMACH_MSM_REQ2,
+        }, {
+                .peri_id = (u8)DMACH_MSM_REQ3,
         },
 };
 
-static struct platform_device s5pc100_device_pdma1 = {
-        .name           = "s3c-pl330",
-        .id             = 1,
-        .num_resources  = ARRAY_SIZE(s5pc100_pdma1_resource),
-        .resource       = s5pc100_pdma1_resource,
-        .dev            = {
+struct dma_pl330_platdata s5pc100_pdma1_pdata = {
+        .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
+        .peri = pdma1_peri,
+};
+
+struct amba_device s5pc100_device_pdma1 = {
+        .dev = {
+                .init_name = "dma-pl330.1",
                 .dma_mask = &dma_dmamask,
                 .coherent_dma_mask = DMA_BIT_MASK(32),
                 .platform_data = &s5pc100_pdma1_pdata,
         },
-};
-
-static struct platform_device *s5pc100_dmacs[] __initdata = {
-        &s5pc100_device_pdma0,
-        &s5pc100_device_pdma1,
+        .res = {
+                .start = S5PC100_PA_PDMA1,
+                .end = S5PC100_PA_PDMA1 + SZ_4K,
+                .flags = IORESOURCE_MEM,
+        },
+        .irq = {IRQ_PDMA1, NO_IRQ},
+        .periphid = 0x00041330,
 };
 
 static int __init s5pc100_dma_init(void)
 {
-        platform_add_devices(s5pc100_dmacs, ARRAY_SIZE(s5pc100_dmacs));
+        amba_device_register(&s5pc100_device_pdma0, &iomem_resource);
+        amba_device_register(&s5pc100_device_pdma1, &iomem_resource);
 
         return 0;
 }
diff --git a/arch/arm/mach-s5pc100/include/mach/clkdev.h b/arch/arm/mach-s5pc100/include/mach/clkdev.h
deleted file mode 100644
index 7dffa83d23ff..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __MACH_CLKDEV_H__
-#define __MACH_CLKDEV_H__
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do {} while (0)
-
-#endif
diff --git a/arch/arm/mach-s5pc100/include/mach/dma.h b/arch/arm/mach-s5pc100/include/mach/dma.h
index 81209eb1409b..201842a3769e 100644
--- a/arch/arm/mach-s5pc100/include/mach/dma.h
+++ b/arch/arm/mach-s5pc100/include/mach/dma.h
@@ -20,7 +20,7 @@
 #ifndef __MACH_DMA_H
 #define __MACH_DMA_H
 
-/* This platform uses the common S3C DMA API driver for PL330 */
-#include <plat/s3c-dma-pl330.h>
+/* This platform uses the common DMA API driver for PL330 */
+#include <plat/dma-pl330.h>
 
 #endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/pwm-clock.h b/arch/arm/mach-s5pc100/include/mach/pwm-clock.h
deleted file mode 100644
index b34d2f7aae52..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/pwm-clock.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* linux/arch/arm/mach-s5pc100/include/mach/pwm-clock.h
- *
- * Copyright 2009 Samsung Electronics Co.
- *      Byungho Min <bhmin@samsung.com>
- *
- * S5PC100 - pwm clock and timer support
- *
- * Based on mach-s3c6400/include/mach/pwm-clock.h
- */
-
-/**
- * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
- * @tcfg: The timer TCFG1 register bits shifted down to 0.
- *
- * Return true if the given configuration from TCFG1 is a TCLK instead
- * any of the TDIV clocks.
- */
-static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
-{
-        return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
-}
-
-/**
- * tcfg_to_divisor() - convert tcfg1 setting to a divisor
- * @tcfg1: The tcfg1 setting, shifted down.
- *
- * Get the divisor value for the given tcfg1 setting. We assume the
- * caller has already checked to see if this is not a TCLK source.
- */
-static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
-{
-        return 1 << tcfg1;
-}
-
-/**
- * pwm_tdiv_has_div1() - does the tdiv setting have a /1
- *
- * Return true if we have a /1 in the tdiv setting.
- */
-static inline unsigned int pwm_tdiv_has_div1(void)
-{
-        return 1;
-}
-
-/**
- * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
- * @div: The divisor to calculate the bit information for.
- *
- * Turn a divisor into the necessary bit field for TCFG1.
- */
-static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
-{
-        return ilog2(div);
-}
-
-#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 227d8908aab6..0b70762ebf1a 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -203,12 +203,6 @@ static struct platform_device *smdkc100_devices[] __initdata = {
         &s5pc100_device_spdif,
 };
 
-static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
-        .delay                  = 10000,
-        .presc                  = 49,
-        .oversampling_shift     = 2,
-};
-
 /* LCD Backlight data */
 static struct samsung_bl_gpio_info smdkc100_bl_gpio_info = {
         .no = S5PC100_GPD(0),
@@ -228,7 +222,7 @@ static void __init smdkc100_map_io(void)
 
 static void __init smdkc100_machine_init(void)
 {
-        s3c24xx_ts_set_platdata(&s3c_ts_platform);
+        s3c24xx_ts_set_platdata(NULL);
 
         /* I2C */
         s3c_i2c0_set_platdata(NULL);
diff --git a/arch/arm/mach-s5pc100/setup-sdhci.c b/arch/arm/mach-s5pc100/setup-sdhci.c
index be25879bb2ee..6418c6e8a7b7 100644
--- a/arch/arm/mach-s5pc100/setup-sdhci.c
+++ b/arch/arm/mach-s5pc100/setup-sdhci.c
@@ -11,17 +11,7 @@
  * published by the Free Software Foundation.
 */
 
-#include <linux/kernel.h>
 #include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-
-#include <linux/mmc/card.h>
-#include <linux/mmc/host.h>
-
-#include <plat/regs-sdhci.h>
-#include <plat/sdhci.h>
 
 /* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
 
@@ -31,35 +21,3 @@ char *s5pc100_hsmmc_clksrcs[4] = {
         [2] = "sclk_mmc",       /* mmc_bus */
         /* [3] = "48m",         - note not successfully used yet */
 };
-
-
-void s5pc100_setup_sdhci0_cfg_card(struct platform_device *dev,
-                                    void __iomem *r,
-                                    struct mmc_ios *ios,
-                                    struct mmc_card *card)
-{
-        u32 ctrl2, ctrl3;
-
-        /* don't need to alter anything according to card-type */
-
-        writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);
-
-        ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
-        ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
-        ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
-                  S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
-                  S3C_SDHCI_CTRL2_ENFBCLKRX |
-                  S3C_SDHCI_CTRL2_DFCNT_NONE |
-                  S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
-
-        if (ios->clock < 25 * 1000000)
-                ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
-                         S3C_SDHCI_CTRL3_FCSEL2 |
-                         S3C_SDHCI_CTRL3_FCSEL1 |
-                         S3C_SDHCI_CTRL3_FCSEL0);
-        else
-                ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
-
-        writel(ctrl2, r + S3C_SDHCI_CONTROL2);
-        writel(ctrl3, r + S3C_SDHCI_CONTROL3);
-}
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 69dd87cd8e22..646057ab2e4c 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -11,10 +11,11 @@ if ARCH_S5PV210
 
 config CPU_S5PV210
         bool
-        select S3C_PL330_DMA
+        select SAMSUNG_DMADEV
         select S5P_EXT_INT
         select S5P_HRT
-        select S5PV210_PM if PM
+        select S5P_PM if PM
+        select S5P_SLEEP if PM
         help
           Enable S5PV210 CPU support
 
@@ -94,11 +95,13 @@ config MACH_GONI
         select S3C_DEV_USB_HSOTG
         select S5P_DEV_ONENAND
         select SAMSUNG_DEV_KEYPAD
+        select S5P_DEV_TV
         select S5PV210_SETUP_FB_24BPP
         select S5PV210_SETUP_I2C1
         select S5PV210_SETUP_I2C2
         select S5PV210_SETUP_KEYPAD
         select S5PV210_SETUP_SDHCI
+        select S5PV210_SETUP_FIMC
         help
           Machine support for Samsung GONI board
           S5PC110(MCP) is one of package option of S5PV210
@@ -169,9 +172,4 @@ config MACH_TORBRECK
 
 endmenu
 
-config S5PV210_PM
-        bool
-        help
-          Power Management code common to S5PV210
-
 endif
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 599a3c0e8f6c..009fbe53df96 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -14,7 +14,7 @@ obj-				:=
 
 obj-$(CONFIG_CPU_S5PV210)       += cpu.o init.o clock.o dma.o
 obj-$(CONFIG_CPU_S5PV210)       += setup-i2c0.o
-obj-$(CONFIG_S5PV210_PM)        += pm.o sleep.o
+obj-$(CONFIG_PM)                += pm.o
 
 # machine support
 
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 52a8e607bcc2..4c5ac7a69e9e 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -174,6 +174,16 @@ static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
         return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
 }
 
+static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
+}
+
+static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
+}
+
 static struct clk clk_sclk_hdmi27m = {
         .name           = "sclk_hdmi27m",
         .rate           = 27000000,
@@ -203,6 +213,11 @@ static struct clk clk_pcmcdclk2 = {
         .name           = "pcmcdclk",
 };
 
+static struct clk dummy_apb_pclk = {
+        .name           = "apb_pclk",
+        .id             = -1,
+};
+
 static struct clk *clkset_vpllsrc_list[] = {
         [0] = &clk_fin_vpll,
         [1] = &clk_sclk_hdmi27m,
@@ -289,14 +304,14 @@ static struct clk_ops clk_fout_apll_ops = {
 
 static struct clk init_clocks_off[] = {
         {
-                .name           = "pdma",
-                .devname        = "s3c-pl330.0",
+                .name           = "dma",
+                .devname        = "dma-pl330.0",
                 .parent         = &clk_hclk_psys.clk,
                 .enable         = s5pv210_clk_ip0_ctrl,
                 .ctrlbit        = (1 << 3),
         }, {
-                .name           = "pdma",
-                .devname        = "s3c-pl330.1",
+                .name           = "dma",
+                .devname        = "dma-pl330.1",
                 .parent         = &clk_hclk_psys.clk,
                 .enable         = s5pv210_clk_ip0_ctrl,
                 .ctrlbit        = (1 << 4),
@@ -330,6 +345,40 @@ static struct clk init_clocks_off[] = {
                 .enable         = s5pv210_clk_ip0_ctrl,
                 .ctrlbit        = (1 << 16),
         }, {
+                .name           = "dac",
+                .devname        = "s5p-sdo",
+                .parent         = &clk_hclk_dsys.clk,
+                .enable         = s5pv210_clk_ip1_ctrl,
+                .ctrlbit        = (1 << 10),
+        }, {
+                .name           = "mixer",
+                .devname        = "s5p-mixer",
+                .parent         = &clk_hclk_dsys.clk,
+                .enable         = s5pv210_clk_ip1_ctrl,
+                .ctrlbit        = (1 << 9),
+        }, {
+                .name           = "vp",
+                .devname        = "s5p-mixer",
+                .parent         = &clk_hclk_dsys.clk,
+                .enable         = s5pv210_clk_ip1_ctrl,
+                .ctrlbit        = (1 << 8),
+        }, {
+                .name           = "hdmi",
+                .devname        = "s5pv210-hdmi",
+                .parent         = &clk_hclk_dsys.clk,
+                .enable         = s5pv210_clk_ip1_ctrl,
+                .ctrlbit        = (1 << 11),
+        }, {
+                .name           = "hdmiphy",
+                .devname        = "s5pv210-hdmi",
+                .enable         = exynos4_clk_hdmiphy_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "dacphy",
+                .devname        = "s5p-sdo",
+                .enable         = exynos4_clk_dac_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
                 .name           = "otg",
                 .parent         = &clk_hclk_psys.clk,
                 .enable         = s5pv210_clk_ip1_ctrl,
@@ -407,6 +456,12 @@ static struct clk init_clocks_off[] = {
                 .enable         = s5pv210_clk_ip3_ctrl,
                 .ctrlbit        = (1<<9),
         }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-hdmiphy-i2c",
+                .parent         = &clk_pclk_psys.clk,
+                .enable         = s5pv210_clk_ip3_ctrl,
+                .ctrlbit        = (1 << 11),
+        }, {
                 .name           = "spi",
                 .devname        = "s3c64xx-spi.0",
                 .parent         = &clk_pclk_psys.clk,
@@ -594,6 +649,23 @@ static struct clksrc_sources clkset_sclk_mixer = {
         .nr_sources     = ARRAY_SIZE(clkset_sclk_mixer_list),
 };
 
+static struct clksrc_clk clk_sclk_mixer = {
+        .clk            = {
+                .name           = "sclk_mixer",
+                .enable         = s5pv210_clk_mask0_ctrl,
+                .ctrlbit        = (1 << 1),
+        },
+        .sources = &clkset_sclk_mixer,
+        .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
+};
+
+static struct clksrc_clk *sclk_tv[] = {
+        &clk_sclk_dac,
+        &clk_sclk_pixel,
+        &clk_sclk_hdmi,
+        &clk_sclk_mixer,
+};
+
 static struct clk *clkset_sclk_audio0_list[] = {
         [0] = &clk_ext_xtal_mux,
         [1] = &clk_pcmcdclk0,
@@ -777,14 +849,6 @@ static struct clksrc_clk clksrcs[] = {
                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
         }, {
                 .clk    = {
-                        .name           = "sclk_mixer",
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 1),
-                },
-                .sources = &clkset_sclk_mixer,
-                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
-        }, {
-                .clk    = {
                         .name           = "sclk_fimc",
                         .devname        = "s5pv210-fimc.0",
                         .enable         = s5pv210_clk_mask1_ctrl,
@@ -815,8 +879,7 @@ static struct clksrc_clk clksrcs[] = {
                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
         }, {
                 .clk            = {
-                        .name           = "sclk_cam",
-                        .devname        = "s5pv210-fimc.0",
+                        .name           = "sclk_cam0",
                         .enable         = s5pv210_clk_mask0_ctrl,
                         .ctrlbit        = (1 << 3),
                 },
@@ -825,8 +888,7 @@ static struct clksrc_clk clksrcs[] = {
                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
         }, {
                 .clk            = {
-                        .name           = "sclk_cam",
-                        .devname        = "s5pv210-fimc.1",
+                        .name           = "sclk_cam1",
                         .enable         = s5pv210_clk_mask0_ctrl,
                         .ctrlbit        = (1 << 4),
                 },
@@ -975,9 +1037,6 @@ static struct clksrc_clk *sysclks[] = {
         &clk_pclk_psys,
         &clk_vpllsrc,
         &clk_sclk_vpll,
-        &clk_sclk_dac,
-        &clk_sclk_pixel,
-        &clk_sclk_hdmi,
         &clk_mout_dmc0,
         &clk_sclk_dmc0,
         &clk_sclk_audio0,
@@ -1062,6 +1121,61 @@ static struct clk_ops s5pv210_epll_ops = {
         .get_rate = s5p_epll_get_rate,
 };
 
+static u32 vpll_div[][5] = {
+        {  54000000, 3, 53, 3, 0 },
+        { 108000000, 3, 53, 2, 0 },
+};
+
+static unsigned long s5pv210_vpll_get_rate(struct clk *clk)
+{
+        return clk->rate;
+}
+
+static int s5pv210_vpll_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned int vpll_con;
+        unsigned int i;
+
+        /* Return if nothing changed */
+        if (clk->rate == rate)
+                return 0;
+
+        vpll_con = __raw_readl(S5P_VPLL_CON);
+        vpll_con &= ~(0x1 << 27 |                                       \
+                        PLL90XX_MDIV_MASK << PLL90XX_MDIV_SHIFT |       \
+                        PLL90XX_PDIV_MASK << PLL90XX_PDIV_SHIFT |       \
+                        PLL90XX_SDIV_MASK << PLL90XX_SDIV_SHIFT);
+
+        for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
+                if (vpll_div[i][0] == rate) {
+                        vpll_con |= vpll_div[i][1] << PLL90XX_PDIV_SHIFT;
+                        vpll_con |= vpll_div[i][2] << PLL90XX_MDIV_SHIFT;
+                        vpll_con |= vpll_div[i][3] << PLL90XX_SDIV_SHIFT;
+                        vpll_con |= vpll_div[i][4] << 27;
+                        break;
+                }
+        }
+
+        if (i == ARRAY_SIZE(vpll_div)) {
+                printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
+                                __func__);
+                return -EINVAL;
+        }
+
+        __raw_writel(vpll_con, S5P_VPLL_CON);
+
+        /* Wait for VPLL lock */
+        while (!(__raw_readl(S5P_VPLL_CON) & (1 << PLL90XX_LOCKED_SHIFT)))
+                continue;
+
+        clk->rate = rate;
+        return 0;
+}
+static struct clk_ops s5pv210_vpll_ops = {
+        .get_rate = s5pv210_vpll_get_rate,
+        .set_rate = s5pv210_vpll_set_rate,
+};
+
 void __init_or_cpufreq s5pv210_setup_clocks(void)
 {
         struct clk *xtal_clk;
@@ -1110,6 +1224,7 @@ void __init_or_cpufreq s5pv210_setup_clocks(void)
         clk_fout_apll.ops = &clk_fout_apll_ops;
         clk_fout_mpll.rate = mpll;
         clk_fout_epll.rate = epll;
+        clk_fout_vpll.ops = &s5pv210_vpll_ops;
         clk_fout_vpll.rate = vpll;
 
         printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
@@ -1155,11 +1270,15 @@ void __init s5pv210_register_clocks(void)
         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
                 s3c_register_clksrc(sysclks[ptr], 1);
 
+        for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
+                s3c_register_clksrc(sclk_tv[ptr], 1);
+
         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 
         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 
+        s3c24xx_register_clock(&dummy_apb_pclk);
         s3c_pwmclk_init();
 }
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
index 79907ec78d43..6b8cdccbe931 100644
--- a/arch/arm/mach-s5pv210/cpu.c
+++ b/arch/arm/mach-s5pv210/cpu.c
@@ -41,6 +41,7 @@
 #include <plat/keypad-core.h>
 #include <plat/sdhci.h>
 #include <plat/reset.h>
+#include <plat/tv-core.h>
 
 /* Initial IO mappings */
 
@@ -143,6 +144,9 @@ void __init s5pv210_map_io(void)
 
         /* Use s5pv210-keypad instead of samsung-keypad */
         samsung_keypad_setname("s5pv210-keypad");
+
+        /* setup TV devices */
+        s5p_hdmi_setname("s5pv210-hdmi");
 }
 
 void __init s5pv210_init_clocks(int xtal)
diff --git a/arch/arm/mach-s5pv210/dma.c b/arch/arm/mach-s5pv210/dma.c
index 497d3439a142..86b749c18b77 100644
--- a/arch/arm/mach-s5pv210/dma.c
+++ b/arch/arm/mach-s5pv210/dma.c
@@ -1,4 +1,8 @@
-/*
+/* linux/arch/arm/mach-s5pv210/dma.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
  * Copyright (C) 2010 Samsung Electronics Co. Ltd.
  *      Jaswinder Singh <jassi.brar@samsung.com>
  *
@@ -17,151 +21,240 @@
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
-#include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/pl330.h>
 
+#include <asm/irq.h>
 #include <plat/devs.h>
 #include <plat/irqs.h>
 
 #include <mach/map.h>
 #include <mach/irqs.h>
-
-#include <plat/s3c-pl330-pdata.h>
+#include <mach/dma.h>
 
 static u64 dma_dmamask = DMA_BIT_MASK(32);
 
-static struct resource s5pv210_pdma0_resource[] = {
-        [0] = {
-                .start  = S5PV210_PA_PDMA0,
-                .end    = S5PV210_PA_PDMA0 + SZ_4K,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_PDMA0,
-                .end    = IRQ_PDMA0,
-                .flags  = IORESOURCE_IRQ,
+struct dma_pl330_peri pdma0_peri[28] = {
+        {
+                .peri_id = (u8)DMACH_UART0_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART0_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_UART1_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART1_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_UART2_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART2_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_UART3_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART3_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = DMACH_MAX,
+        }, {
+                .peri_id = (u8)DMACH_I2S0_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_I2S0_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_I2S0S_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_I2S1_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_I2S1_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_MAX,
+        }, {
+                .peri_id = (u8)DMACH_MAX,
+        }, {
+                .peri_id = (u8)DMACH_SPI0_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_SPI0_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_SPI1_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_SPI1_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_MAX,
+        }, {
+                .peri_id = (u8)DMACH_MAX,
+        }, {
+                .peri_id = (u8)DMACH_AC97_MICIN,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_AC97_PCMIN,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_AC97_PCMOUT,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_MAX,
+        }, {
+                .peri_id = (u8)DMACH_PWM,
+        }, {
+                .peri_id = (u8)DMACH_SPDIF,
+                .rqtype = MEMTODEV,
         },
 };
 
-static struct s3c_pl330_platdata s5pv210_pdma0_pdata = {
-        .peri = {
-                [0] = DMACH_UART0_RX,
-                [1] = DMACH_UART0_TX,
-                [2] = DMACH_UART1_RX,
-                [3] = DMACH_UART1_TX,
-                [4] = DMACH_UART2_RX,
-                [5] = DMACH_UART2_TX,
-                [6] = DMACH_UART3_RX,
-                [7] = DMACH_UART3_TX,
-                [8] = DMACH_MAX,
-                [9] = DMACH_I2S0_RX,
-                [10] = DMACH_I2S0_TX,
-                [11] = DMACH_I2S0S_TX,
-                [12] = DMACH_I2S1_RX,
-                [13] = DMACH_I2S1_TX,
-                [14] = DMACH_MAX,
-                [15] = DMACH_MAX,
-                [16] = DMACH_SPI0_RX,
-                [17] = DMACH_SPI0_TX,
-                [18] = DMACH_SPI1_RX,
-                [19] = DMACH_SPI1_TX,
-                [20] = DMACH_MAX,
-                [21] = DMACH_MAX,
-                [22] = DMACH_AC97_MICIN,
-                [23] = DMACH_AC97_PCMIN,
-                [24] = DMACH_AC97_PCMOUT,
-                [25] = DMACH_MAX,
-                [26] = DMACH_PWM,
-                [27] = DMACH_SPDIF,
-                [28] = DMACH_MAX,
-                [29] = DMACH_MAX,
-                [30] = DMACH_MAX,
-                [31] = DMACH_MAX,
-        },
+struct dma_pl330_platdata s5pv210_pdma0_pdata = {
+        .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
+        .peri = pdma0_peri,
 };
 
-static struct platform_device s5pv210_device_pdma0 = {
-        .name           = "s3c-pl330",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(s5pv210_pdma0_resource),
-        .resource       = s5pv210_pdma0_resource,
-        .dev            = {
+struct amba_device s5pv210_device_pdma0 = {
+        .dev = {
+                .init_name = "dma-pl330.0",
                 .dma_mask = &dma_dmamask,
                 .coherent_dma_mask = DMA_BIT_MASK(32),
                 .platform_data = &s5pv210_pdma0_pdata,
         },
-};
-
-static struct resource s5pv210_pdma1_resource[] = {
-        [0] = {
-                .start  = S5PV210_PA_PDMA1,
-                .end    = S5PV210_PA_PDMA1 + SZ_4K,
+        .res = {
+                .start = S5PV210_PA_PDMA0,
+                .end = S5PV210_PA_PDMA0 + SZ_4K,
                 .flags = IORESOURCE_MEM,
         },
-        [1] = {
-                .start  = IRQ_PDMA1,
-                .end    = IRQ_PDMA1,
-                .flags  = IORESOURCE_IRQ,
-        },
+        .irq = {IRQ_PDMA0, NO_IRQ},
+        .periphid = 0x00041330,
 };
 
-static struct s3c_pl330_platdata s5pv210_pdma1_pdata = {
-        .peri = {
-                [0] = DMACH_UART0_RX,
-                [1] = DMACH_UART0_TX,
-                [2] = DMACH_UART1_RX,
-                [3] = DMACH_UART1_TX,
-                [4] = DMACH_UART2_RX,
-                [5] = DMACH_UART2_TX,
-                [6] = DMACH_UART3_RX,
-                [7] = DMACH_UART3_TX,
-                [8] = DMACH_MAX,
-                [9] = DMACH_I2S0_RX,
-                [10] = DMACH_I2S0_TX,
-                [11] = DMACH_I2S0S_TX,
-                [12] = DMACH_I2S1_RX,
-                [13] = DMACH_I2S1_TX,
-                [14] = DMACH_I2S2_RX,
-                [15] = DMACH_I2S2_TX,
-                [16] = DMACH_SPI0_RX,
-                [17] = DMACH_SPI0_TX,
-                [18] = DMACH_SPI1_RX,
-                [19] = DMACH_SPI1_TX,
-                [20] = DMACH_MAX,
-                [21] = DMACH_MAX,
-                [22] = DMACH_PCM0_RX,
-                [23] = DMACH_PCM0_TX,
-                [24] = DMACH_PCM1_RX,
-                [25] = DMACH_PCM1_TX,
-                [26] = DMACH_MSM_REQ0,
-                [27] = DMACH_MSM_REQ1,
-                [28] = DMACH_MSM_REQ2,
-                [29] = DMACH_MSM_REQ3,
-                [30] = DMACH_PCM2_RX,
-                [31] = DMACH_PCM2_TX,
+struct dma_pl330_peri pdma1_peri[32] = {
+        {
+                .peri_id = (u8)DMACH_UART0_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART0_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_UART1_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART1_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_UART2_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART2_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_UART3_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_UART3_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = DMACH_MAX,
+        }, {
+                .peri_id = (u8)DMACH_I2S0_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_I2S0_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_I2S0S_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_I2S1_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_I2S1_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_I2S2_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_I2S2_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_SPI0_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_SPI0_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_SPI1_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_SPI1_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_MAX,
+        }, {
+                .peri_id = (u8)DMACH_MAX,
+        }, {
+                .peri_id = (u8)DMACH_PCM0_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_PCM0_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_PCM1_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_PCM1_TX,
+                .rqtype = MEMTODEV,
+        }, {
+                .peri_id = (u8)DMACH_MSM_REQ0,
+        }, {
+                .peri_id = (u8)DMACH_MSM_REQ1,
+        }, {
+                .peri_id = (u8)DMACH_MSM_REQ2,
+        }, {
+                .peri_id = (u8)DMACH_MSM_REQ3,
+        }, {
+                .peri_id = (u8)DMACH_PCM2_RX,
+                .rqtype = DEVTOMEM,
+        }, {
+                .peri_id = (u8)DMACH_PCM2_TX,
+                .rqtype = MEMTODEV,
         },
 };
 
-static struct platform_device s5pv210_device_pdma1 = {
-        .name           = "s3c-pl330",
-        .id             = 1,
-        .num_resources  = ARRAY_SIZE(s5pv210_pdma1_resource),
-        .resource       = s5pv210_pdma1_resource,
-        .dev            = {
+struct dma_pl330_platdata s5pv210_pdma1_pdata = {
+        .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
+        .peri = pdma1_peri,
+};
+
+struct amba_device s5pv210_device_pdma1 = {
+        .dev = {
+                .init_name = "dma-pl330.1",
                 .dma_mask = &dma_dmamask,
                 .coherent_dma_mask = DMA_BIT_MASK(32),
                 .platform_data = &s5pv210_pdma1_pdata,
         },
-};
-
-static struct platform_device *s5pv210_dmacs[] __initdata = {
-        &s5pv210_device_pdma0,
-        &s5pv210_device_pdma1,
+        .res = {
+                .start = S5PV210_PA_PDMA1,
+                .end = S5PV210_PA_PDMA1 + SZ_4K,
+                .flags = IORESOURCE_MEM,
+        },
+        .irq = {IRQ_PDMA1, NO_IRQ},
+        .periphid = 0x00041330,
 };
 
 static int __init s5pv210_dma_init(void)
 {
-        platform_add_devices(s5pv210_dmacs, ARRAY_SIZE(s5pv210_dmacs));
+        amba_device_register(&s5pv210_device_pdma0, &iomem_resource);
+        amba_device_register(&s5pv210_device_pdma1, &iomem_resource);
 
         return 0;
 }
diff --git a/arch/arm/mach-s5pv210/include/mach/clkdev.h b/arch/arm/mach-s5pv210/include/mach/clkdev.h
deleted file mode 100644
index 7dffa83d23ff..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __MACH_CLKDEV_H__
-#define __MACH_CLKDEV_H__
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do {} while (0)
-
-#endif
diff --git a/arch/arm/mach-s5pv210/include/mach/dma.h b/arch/arm/mach-s5pv210/include/mach/dma.h
index 81209eb1409b..201842a3769e 100644
--- a/arch/arm/mach-s5pv210/include/mach/dma.h
+++ b/arch/arm/mach-s5pv210/include/mach/dma.h
@@ -20,7 +20,7 @@
 #ifndef __MACH_DMA_H
 #define __MACH_DMA_H
 
-/* This platform uses the common S3C DMA API driver for PL330 */
-#include <plat/s3c-dma-pl330.h>
+/* This platform uses the common DMA API driver for PL330 */
+#include <plat/dma-pl330.h>
 
 #endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/i2c-hdmiphy.h b/arch/arm/mach-s5pv210/include/mach/i2c-hdmiphy.h
new file mode 100644
index 000000000000..6afa6242c588
--- /dev/null
+++ b/arch/arm/mach-s5pv210/include/mach/i2c-hdmiphy.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co., Ltd.
+ *
+ * S5P series i2c hdmiphy helper definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef PLAT_S5P_I2C_HDMIPHY_H_
+#define PLAT_S5P_I2C_HDMIPHY_H_
+
+#define S5P_I2C_HDMIPHY_BUS_NUM         (3)
+
+#endif
diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h
index b9f9ec33384d..5e0de3a31f3d 100644
--- a/arch/arm/mach-s5pv210/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv210/include/mach/irqs.h
@@ -56,7 +56,7 @@
 #define IRQ_SPI2                S5P_IRQ_VIC1(17)
 #define IRQ_IRDA                S5P_IRQ_VIC1(18)
 #define IRQ_IIC2                S5P_IRQ_VIC1(19)
-#define IRQ_IIC3                S5P_IRQ_VIC1(20)
+#define IRQ_IIC_HDMIPHY         S5P_IRQ_VIC1(20)
 #define IRQ_HSIRX               S5P_IRQ_VIC1(21)
 #define IRQ_HSITX               S5P_IRQ_VIC1(22)
 #define IRQ_UHOST               S5P_IRQ_VIC1(23)
@@ -86,7 +86,7 @@
 #define IRQ_HDMI                S5P_IRQ_VIC2(12)
 #define IRQ_IIC1                S5P_IRQ_VIC2(13)
 #define IRQ_MFC                 S5P_IRQ_VIC2(14)
-#define IRQ_TVENC               S5P_IRQ_VIC2(15)
+#define IRQ_SDO                 S5P_IRQ_VIC2(15)
 #define IRQ_I2S0                S5P_IRQ_VIC2(16)
 #define IRQ_I2S1                S5P_IRQ_VIC2(17)
 #define IRQ_I2S2                S5P_IRQ_VIC2(18)
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index aac343c180b2..7ff609f1568b 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -90,6 +90,12 @@
 #define S5PV210_PA_FIMC1                0xFB300000
 #define S5PV210_PA_FIMC2                0xFB400000
 
+#define S5PV210_PA_SDO                  0xF9000000
+#define S5PV210_PA_VP                   0xF9100000
+#define S5PV210_PA_MIXER                0xF9200000
+#define S5PV210_PA_HDMI                 0xFA100000
+#define S5PV210_PA_IIC_HDMIPHY          0xFA900000
+
 /* Compatibiltiy Defines */
 
 #define S3C_PA_FB                       S5PV210_PA_FB
@@ -110,6 +116,13 @@
 #define S5P_PA_FIMC2                    S5PV210_PA_FIMC2
 #define S5P_PA_MIPI_CSIS0               S5PV210_PA_MIPI_CSIS
 #define S5P_PA_MFC                      S5PV210_PA_MFC
+#define S5P_PA_IIC_HDMIPHY              S5PV210_PA_IIC_HDMIPHY
+
+#define S5P_PA_SDO                      S5PV210_PA_SDO
+#define S5P_PA_VP                       S5PV210_PA_VP
+#define S5P_PA_MIXER                    S5PV210_PA_MIXER
+#define S5P_PA_HDMI                     S5PV210_PA_HDMI
+
 #define S5P_PA_ONENAND                  S5PC110_PA_ONENAND
 #define S5P_PA_ONENAND_DMA              S5PC110_PA_ONENAND_DMA
 #define S5P_PA_SDRAM                    S5PV210_PA_SDRAM
diff --git a/arch/arm/mach-s5pv210/include/mach/pm-core.h b/arch/arm/mach-s5pv210/include/mach/pm-core.h
index 3e22109e1b7b..eba8aea63ed8 100644
--- a/arch/arm/mach-s5pv210/include/mach/pm-core.h
+++ b/arch/arm/mach-s5pv210/include/mach/pm-core.h
@@ -43,4 +43,4 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
 }
 
 static inline void s3c_pm_restored_gpios(void) { }
-static inline void s3c_pm_saved_gpios(void) { }
+static inline void samsung_pm_saved_gpios(void) { }
diff --git a/arch/arm/mach-s5pv210/include/mach/pwm-clock.h b/arch/arm/mach-s5pv210/include/mach/pwm-clock.h
deleted file mode 100644
index f8a9f1b330e0..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/pwm-clock.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/include/mach/pwm-clock.h
- *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
- *
- * S5PV210 - pwm clock and timer support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_PWMCLK_H
-#define __ASM_ARCH_PWMCLK_H __FILE__
-
-/**
- * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
- * @tcfg: The timer TCFG1 register bits shifted down to 0.
- *
- * Return true if the given configuration from TCFG1 is a TCLK instead
- * any of the TDIV clocks.
- */
-static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
-{
-        return tcfg == S3C64XX_TCFG1_MUX_TCLK;
-}
-
-/**
- * tcfg_to_divisor() - convert tcfg1 setting to a divisor
- * @tcfg1: The tcfg1 setting, shifted down.
- *
- * Get the divisor value for the given tcfg1 setting. We assume the
- * caller has already checked to see if this is not a TCLK source.
- */
-static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
-{
-        return 1 << tcfg1;
-}
-
-/**
- * pwm_tdiv_has_div1() - does the tdiv setting have a /1
- *
- * Return true if we have a /1 in the tdiv setting.
- */
-static inline unsigned int pwm_tdiv_has_div1(void)
-{
-        return 1;
-}
-
-/**
- * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
- * @div: The divisor to calculate the bit information for.
- *
- * Turn a divisor into the necessary bit field for TCFG1.
- */
-static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
-{
-        return ilog2(div);
-}
-
-#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
-
-#endif /* __ASM_ARCH_PWMCLK_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
index 78925c516346..032de66fb8be 100644
--- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
@@ -144,8 +144,9 @@
 
 #define S5P_OTHERS              S5P_CLKREG(0xE000)
 #define S5P_OM_STAT             S5P_CLKREG(0xE100)
+#define S5P_HDMI_PHY_CONTROL    S5P_CLKREG(0xE804)
 #define S5P_USB_PHY_CONTROL     S5P_CLKREG(0xE80C)
-#define S5P_DAC_CONTROL         S5P_CLKREG(0xE810)
+#define S5P_DAC_PHY_CONTROL     S5P_CLKREG(0xE810)
 #define S5P_MIPI_DPHY_CONTROL(x) S5P_CLKREG(0xE814)
 #define S5P_MIPI_DPHY_ENABLE    (1 << 0)
 #define S5P_MIPI_DPHY_SRESETN   (1 << 1)
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 85c2d51a0956..01e4867e25ad 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -48,6 +48,11 @@
 #include <plat/s5p-time.h>
 #include <plat/mfc.h>
 #include <plat/regs-fb-v4.h>
+#include <plat/camport.h>
+
+#include <media/v4l2-mediabus.h>
+#include <media/s5p_fimc.h>
+#include <media/noon010pc30.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define GONI_UCON_DEFAULT       (S3C2410_UCON_TXILEVEL |        \
@@ -272,6 +277,14 @@ static void __init goni_tsp_init(void)
         i2c2_devs[0].irq = gpio_to_irq(gpio);
 }
 
+static void goni_camera_init(void)
+{
+        s5pv210_fimc_setup_gpio(S5P_CAMPORT_A);
+
+        /* Set max driver strength on CAM_A_CLKOUT pin. */
+        s5p_gpio_set_drvstr(S5PV210_GPE1(3), S5P_GPIO_DRVSTR_LV4);
+}
+
 /* MAX8998 regulators */
 #if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE)
 
@@ -285,6 +298,7 @@ static struct regulator_consumer_supply goni_ldo5_consumers[] = {
 
 static struct regulator_consumer_supply goni_ldo8_consumers[] = {
         REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"),
+        REGULATOR_SUPPLY("vdd33a_dac", "s5p-sdo"),
 };
 
 static struct regulator_consumer_supply goni_ldo11_consumers[] = {
@@ -475,6 +489,10 @@ static struct regulator_consumer_supply buck1_consumer =
 static struct regulator_consumer_supply buck2_consumer =
         REGULATOR_SUPPLY("vddint", NULL);
 
+static struct regulator_consumer_supply buck3_consumer =
+        REGULATOR_SUPPLY("vdet", "s5p-sdo");
+
+
 static struct regulator_init_data goni_buck1_data = {
         .constraints    = {
                 .name           = "VARM_1.2V",
@@ -511,6 +529,8 @@ static struct regulator_init_data goni_buck3_data = {
                         .enabled = 1,
                 },
         },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &buck3_consumer,
 };
 
 static struct regulator_init_data goni_buck4_data = {
@@ -801,6 +821,39 @@ static void goni_setup_sdhci(void)
         s3c_sdhci2_set_platdata(&goni_hsmmc2_data);
 };
 
+static struct noon010pc30_platform_data noon010pc30_pldata = {
+        .clk_rate       = 16000000UL,
+        .gpio_nreset    = S5PV210_GPB(2), /* CAM_CIF_NRST */
+        .gpio_nstby     = S5PV210_GPB(0), /* CAM_CIF_NSTBY */
+};
+
+static struct i2c_board_info noon010pc30_board_info = {
+        I2C_BOARD_INFO("NOON010PC30", 0x60 >> 1),
+        .platform_data = &noon010pc30_pldata,
+};
+
+static struct s5p_fimc_isp_info goni_camera_sensors[] = {
+        {
+                .mux_id         = 0,
+                .flags          = V4L2_MBUS_PCLK_SAMPLE_FALLING |
+                                  V4L2_MBUS_VSYNC_ACTIVE_LOW,
+                .bus_type       = FIMC_ITU_601,
+                .board_info     = &noon010pc30_board_info,
+                .i2c_bus_num    = 0,
+                .clk_frequency  = 16000000UL,
+        },
+};
+
+struct s5p_platform_fimc goni_fimc_md_platdata __initdata = {
+        .isp_info       = goni_camera_sensors,
+        .num_clients    = ARRAY_SIZE(goni_camera_sensors),
+};
+
+struct platform_device s5p_device_fimc_md = {
+        .name           = "s5p-fimc-md",
+        .id             = -1,
+};
+
 static struct platform_device *goni_devices[] __initdata = {
         &s3c_device_fb,
         &s5p_device_onenand,
@@ -812,10 +865,13 @@ static struct platform_device *goni_devices[] __initdata = {
         &s5p_device_mfc,
         &s5p_device_mfc_l,
         &s5p_device_mfc_r,
+        &s5p_device_mixer,
+        &s5p_device_sdo,
         &s3c_device_i2c0,
         &s5p_device_fimc0,
         &s5p_device_fimc1,
         &s5p_device_fimc2,
+        &s5p_device_fimc_md,
         &s3c_device_hsmmc0,
         &s3c_device_hsmmc1,
         &s3c_device_hsmmc2,
@@ -884,6 +940,12 @@ static void __init goni_machine_init(void)
         /* FB */
         s3c_fb_set_platdata(&goni_lcd_pdata);
 
+        /* FIMC */
+        s3c_set_platdata(&goni_fimc_md_platdata, sizeof(goni_fimc_md_platdata),
+                         &s5p_device_fimc_md);
+
+        goni_camera_init();
+
         /* SPI */
         spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
 
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 5e011fc6720d..4b27bcaf676a 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -265,12 +265,6 @@ static struct i2c_board_info smdkv210_i2c_devs2[] __initdata = {
         /* To Be Updated */
 };
 
-static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
-        .delay                  = 10000,
-        .presc                  = 49,
-        .oversampling_shift     = 2,
-};
-
 /* LCD Backlight data */
 static struct samsung_bl_gpio_info smdkv210_bl_gpio_info = {
         .no = S5PV210_GPD0(3),
@@ -296,7 +290,7 @@ static void __init smdkv210_machine_init(void)
         smdkv210_dm9000_init();
 
         samsung_keypad_set_platdata(&smdkv210_keypad_data);
-        s3c24xx_ts_set_platdata(&s3c_ts_platform);
+        s3c24xx_ts_set_platdata(NULL);
 
         s3c_i2c0_set_platdata(NULL);
         s3c_i2c1_set_platdata(NULL);
diff --git a/arch/arm/mach-s5pv210/setup-sdhci.c b/arch/arm/mach-s5pv210/setup-sdhci.c
index a83b6c909f6b..6b8ccc4d35fd 100644
--- a/arch/arm/mach-s5pv210/setup-sdhci.c
+++ b/arch/arm/mach-s5pv210/setup-sdhci.c
@@ -10,17 +10,7 @@
  * published by the Free Software Foundation.
 */
 
-#include <linux/kernel.h>
 #include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-
-#include <linux/mmc/card.h>
-#include <linux/mmc/host.h>
-
-#include <plat/regs-sdhci.h>
-#include <plat/sdhci.h>
 
 /* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
 
@@ -30,34 +20,3 @@ char *s5pv210_hsmmc_clksrcs[4] = {
         [2] = "sclk_mmc",       /* mmc_bus */
         /* [3] = NULL,          - reserved */
 };
-
-void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev,
-                                    void __iomem *r,
-                                    struct mmc_ios *ios,
-                                    struct mmc_card *card)
-{
-        u32 ctrl2, ctrl3;
-
-        /* don't need to alter anything according to card-type */
-
-        writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);
-
-        ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
-        ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
-        ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
-                  S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
-                  S3C_SDHCI_CTRL2_ENFBCLKRX |
-                  S3C_SDHCI_CTRL2_DFCNT_NONE |
-                  S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
-
-        if (ios->clock < 25 * 1000000)
-                ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
-                         S3C_SDHCI_CTRL3_FCSEL2 |
-                         S3C_SDHCI_CTRL3_FCSEL1 |
-                         S3C_SDHCI_CTRL3_FCSEL0);
-        else
-                ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
-
-        writel(ctrl2, r + S3C_SDHCI_CONTROL2);
-        writel(ctrl3, r + S3C_SDHCI_CONTROL3);
-}
diff --git a/arch/arm/mach-s5pv210/sleep.S b/arch/arm/mach-s5pv210/sleep.S
deleted file mode 100644
index e3452ccd4b08..000000000000
--- a/arch/arm/mach-s5pv210/sleep.S
+++ /dev/null
@@ -1,52 +0,0 @@
-/* linux/arch/arm/plat-s5p/sleep.S
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * S5PV210 power Manager (Suspend-To-RAM) support
- * Based on S3C2410 sleep code by:
- *      Ben Dooks, (c) 2004 Simtec Electronics
- *
- * Based on PXA/SA1100 sleep code by:
- *      Nicolas Pitre, (c) 2002 Monta Vista Software Inc
- *      Cliff Brake, (c) 2001
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <asm/memory.h>
-
-        .text
-
-        /* sleep magic, to allow the bootloader to check for an valid
-         * image to resume to. Must be the first word before the
-         * s3c_cpu_resume entry.
-        */
-
-        .word   0x2bedf00d
-
-        /* s3c_cpu_resume
-         *
-         * resume code entry for bootloader to call
-         *
-         * we must put this code here in the data segment as we have no
-         * other way of restoring the stack pointer after sleep, and we
-         * must not write to the code segment (code is read-only)
-        */
-
-ENTRY(s3c_cpu_resume)
-        b       cpu_resume
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 3b24bfa3b828..07c4bc8ea0a4 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -174,6 +174,10 @@ ENTRY(v7_coherent_user_range)
         dcache_line_size r2, r3
         sub     r3, r2, #1
         bic     r12, r0, r3
+#ifdef CONFIG_ARM_ERRATA_764369
+        ALT_SMP(W(dsb))
+        ALT_UP(W(nop))
+#endif
 1:
  USER(  mcr     p15, 0, r12, c7, c11, 1 )       @ clean D line to the point of unification
         add     r12, r12, r2
@@ -223,6 +227,10 @@ ENTRY(v7_flush_kern_dcache_area)
         add     r1, r0, r1
         sub     r3, r2, #1
         bic     r0, r0, r3
+#ifdef CONFIG_ARM_ERRATA_764369
+        ALT_SMP(W(dsb))
+        ALT_UP(W(nop))
+#endif
 1:
         mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D line / unified line
         add     r0, r0, r2
@@ -247,6 +255,10 @@ v7_dma_inv_range:
         sub     r3, r2, #1
         tst     r0, r3
         bic     r0, r0, r3
+#ifdef CONFIG_ARM_ERRATA_764369
+        ALT_SMP(W(dsb))
+        ALT_UP(W(nop))
+#endif
         mcrne   p15, 0, r0, c7, c14, 1          @ clean & invalidate D / U line
 
         tst     r1, r3
@@ -270,6 +282,10 @@ v7_dma_clean_range:
         dcache_line_size r2, r3
         sub     r3, r2, #1
         bic     r0, r0, r3
+#ifdef CONFIG_ARM_ERRATA_764369
+        ALT_SMP(W(dsb))
+        ALT_UP(W(nop))
+#endif
 1:
         mcr     p15, 0, r0, c7, c10, 1          @ clean D / U line
         add     r0, r0, r2
@@ -288,6 +304,10 @@ ENTRY(v7_dma_flush_range)
         dcache_line_size r2, r3
         sub     r3, r2, #1
         bic     r0, r0, r3
+#ifdef CONFIG_ARM_ERRATA_764369
+        ALT_SMP(W(dsb))
+        ALT_UP(W(nop))
+#endif
 1:
         mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D / U line
         add     r0, r0, r2
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 0a0a1e7c20d2..c3ff82f92d9c 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -324,6 +324,8 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
 
         if (addr)
                 *handle = pfn_to_dma(dev, page_to_pfn(page));
+        else
+                __dma_free_buffer(page, size);
 
         return addr;
 }
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index 8c5b3029b39f..d8973ac46bc4 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -9,7 +9,6 @@ config PLAT_S3C24XX
         select NO_IOPORT
         select ARCH_REQUIRE_GPIOLIB
         select S3C_DEV_NAND
-        select S3C_GPIO_CFG_S3C24XX
         help
           Base platform code for any Samsung S3C24XX device
 
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
index 0291bd6e236e..e4f46495ed30 100644
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -15,8 +15,6 @@ obj-				:=
 obj-y                           += cpu.o
 obj-y                           += irq.o
 obj-y                           += devs.o
-obj-y                           += gpio.o
-obj-y                           += gpiolib.o
 obj-y                           += clock.o
 obj-$(CONFIG_S3C24XX_DCLK)      += clock-dclk.o
 
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index c1fc6c6fac72..3c6335307fb1 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -215,19 +215,18 @@ static void s3c24xx_pm_restart(char mode, const char *cmd)
 
 void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
 {
-        unsigned long idcode = 0x0;
-
         /* initialise the io descriptors we need for initialisation */
         iotable_init(mach_desc, size);
         iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
 
         if (cpu_architecture() >= CPU_ARCH_ARMv5) {
-                idcode = s3c24xx_read_idcode_v5();
+                samsung_cpu_id = s3c24xx_read_idcode_v5();
         } else {
-                idcode = s3c24xx_read_idcode_v4();
+                samsung_cpu_id = s3c24xx_read_idcode_v4();
         }
+        s3c24xx_init_cpu();
 
         arm_pm_restart = s3c24xx_pm_restart;
 
-        s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
+        s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 }
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index 539bd0e3defd..53754bcf15a7 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -1094,14 +1094,14 @@ EXPORT_SYMBOL(s3c2410_dma_config);
  *
  * configure the dma source/destination hardware type and address
  *
- * source:    S3C2410_DMASRC_HW: source is hardware
- *            S3C2410_DMASRC_MEM: source is memory
+ * source:    DMA_FROM_DEVICE: source is hardware
+ *            DMA_TO_DEVICE: source is memory
  *
  * devaddr:   physical address of the source
 */
 
 int s3c2410_dma_devconfig(enum dma_ch channel,
-                          enum s3c2410_dmasrc source,
+                          enum dma_data_direction source,
                           unsigned long devaddr)
 {
         struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
@@ -1131,7 +1131,7 @@ int s3c2410_dma_devconfig(enum dma_ch channel,
          hwcfg |= S3C2410_DISRCC_INC;
 
         switch (source) {
-        case S3C2410_DMASRC_HW:
+        case DMA_FROM_DEVICE:
                 /* source is hardware */
                 pr_debug("%s: hw source, devaddr=%08lx, hwcfg=%d\n",
                          __func__, devaddr, hwcfg);
@@ -1142,7 +1142,7 @@ int s3c2410_dma_devconfig(enum dma_ch channel,
                 chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DIDST);
                 break;
 
-        case S3C2410_DMASRC_MEM:
+        case DMA_TO_DEVICE:
                 /* source is memory */
                 pr_debug("%s: mem source, devaddr=%08lx, hwcfg=%d\n",
                          __func__, devaddr, hwcfg);
diff --git a/arch/arm/plat-s3c24xx/gpio.c b/arch/arm/plat-s3c24xx/gpio.c
deleted file mode 100644
index 2f3d7c089dfa..000000000000
--- a/arch/arm/plat-s3c24xx/gpio.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/* linux/arch/arm/plat-s3c24xx/gpio.c
- *
- * Copyright (c) 2004-2010 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C24XX GPIO support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/gpio.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <mach/gpio-fns.h>
-#include <asm/irq.h>
-
-#include <mach/regs-gpio.h>
-
-#include <plat/gpio-core.h>
-
-/* gpiolib wrappers until these are totally eliminated */
-
-void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
-{
-        int ret;
-
-        WARN_ON(to);    /* should be none of these left */
-
-        if (!to) {
-                /* if pull is enabled, try first with up, and if that
-                 * fails, try using down */
-
-                ret = s3c_gpio_setpull(pin, S3C_GPIO_PULL_UP);
-                if (ret)
-                        s3c_gpio_setpull(pin, S3C_GPIO_PULL_DOWN);
-        } else {
-                s3c_gpio_setpull(pin, S3C_GPIO_PULL_NONE);
-        }
-}
-EXPORT_SYMBOL(s3c2410_gpio_pullup);
-
-void s3c2410_gpio_setpin(unsigned int pin, unsigned int to)
-{
-        /* do this via gpiolib until all users removed */
-
-        gpio_request(pin, "temporary");
-        gpio_set_value(pin, to);
-        gpio_free(pin);
-}
-
-EXPORT_SYMBOL(s3c2410_gpio_setpin);
-
-unsigned int s3c2410_gpio_getpin(unsigned int pin)
-{
-        struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
-        unsigned long offs = pin - chip->chip.base;
-
-        return __raw_readl(chip->base + 0x04) & (1<< offs);
-}
-
-EXPORT_SYMBOL(s3c2410_gpio_getpin);
-
-unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
-{
-        unsigned long flags;
-        unsigned long misccr;
-
-        local_irq_save(flags);
-        misccr = __raw_readl(S3C24XX_MISCCR);
-        misccr &= ~clear;
-        misccr ^= change;
-        __raw_writel(misccr, S3C24XX_MISCCR);
-        local_irq_restore(flags);
-
-        return misccr;
-}
-
-EXPORT_SYMBOL(s3c2410_modify_misccr);
diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c
deleted file mode 100644
index 243b6411050d..000000000000
--- a/arch/arm/plat-s3c24xx/gpiolib.c
+++ /dev/null
@@ -1,229 +0,0 @@
-/* linux/arch/arm/plat-s3c24xx/gpiolib.c
- *
- * Copyright (c) 2008-2010 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C24XX GPIOlib support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License.
-*/
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/sysdev.h>
-#include <linux/ioport.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-
-#include <plat/gpio-core.h>
-#include <plat/gpio-cfg.h>
-#include <plat/gpio-cfg-helpers.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <plat/pm.h>
-
-#include <mach/regs-gpio.h>
-
-static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
-{
-        return -EINVAL;
-}
-
-static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
-                                        unsigned offset, int value)
-{
-        struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
-        void __iomem *base = ourchip->base;
-        unsigned long flags;
-        unsigned long dat;
-        unsigned long con;
-
-        local_irq_save(flags);
-
-        con = __raw_readl(base + 0x00);
-        dat = __raw_readl(base + 0x04);
-
-        dat &= ~(1 << offset);
-        if (value)
-                dat |= 1 << offset;
-
-        __raw_writel(dat, base + 0x04);
-
-        con &= ~(1 << offset);
-
-        __raw_writel(con, base + 0x00);
-        __raw_writel(dat, base + 0x04);
-
-        local_irq_restore(flags);
-        return 0;
-}
-
-static int s3c24xx_gpiolib_bankf_toirq(struct gpio_chip *chip, unsigned offset)
-{
-        if (offset < 4)
-                return IRQ_EINT0 + offset;
-        
-        if (offset < 8)
-                return IRQ_EINT4 + offset - 4;
-        
-        return -EINVAL;
-}
-
-static struct s3c_gpio_cfg s3c24xx_gpiocfg_banka = {
-        .set_config     = s3c_gpio_setcfg_s3c24xx_a,
-        .get_config     = s3c_gpio_getcfg_s3c24xx_a,
-};
-
-struct s3c_gpio_cfg s3c24xx_gpiocfg_default = {
-        .set_config     = s3c_gpio_setcfg_s3c24xx,
-        .get_config     = s3c_gpio_getcfg_s3c24xx,
-};
-
-struct s3c_gpio_chip s3c24xx_gpios[] = {
-        [0] = {
-                .base   = S3C2410_GPACON,
-                .pm     = __gpio_pm(&s3c_gpio_pm_1bit),
-                .config = &s3c24xx_gpiocfg_banka,
-                .chip   = {
-                        .base                   = S3C2410_GPA(0),
-                        .owner                  = THIS_MODULE,
-                        .label                  = "GPIOA",
-                        .ngpio                  = 24,
-                        .direction_input        = s3c24xx_gpiolib_banka_input,
-                        .direction_output       = s3c24xx_gpiolib_banka_output,
-                },
-        },
-        [1] = {
-                .base   = S3C2410_GPBCON,
-                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
-                .chip   = {
-                        .base                   = S3C2410_GPB(0),
-                        .owner                  = THIS_MODULE,
-                        .label                  = "GPIOB",
-                        .ngpio                  = 16,
-                },
-        },
-        [2] = {
-                .base   = S3C2410_GPCCON,
-                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
-                .chip   = {
-                        .base                   = S3C2410_GPC(0),
-                        .owner                  = THIS_MODULE,
-                        .label                  = "GPIOC",
-                        .ngpio                  = 16,
-                },
-        },
-        [3] = {
-                .base   = S3C2410_GPDCON,
-                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
-                .chip   = {
-                        .base                   = S3C2410_GPD(0),
-                        .owner                  = THIS_MODULE,
-                        .label                  = "GPIOD",
-                        .ngpio                  = 16,
-                },
-        },
-        [4] = {
-                .base   = S3C2410_GPECON,
-                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
-                .chip   = {
-                        .base                   = S3C2410_GPE(0),
-                        .label                  = "GPIOE",
-                        .owner                  = THIS_MODULE,
-                        .ngpio                  = 16,
-                },
-        },
-        [5] = {
-                .base   = S3C2410_GPFCON,
-                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
-                .chip   = {
-                        .base                   = S3C2410_GPF(0),
-                        .owner                  = THIS_MODULE,
-                        .label                  = "GPIOF",
-                        .ngpio                  = 8,
-                        .to_irq                 = s3c24xx_gpiolib_bankf_toirq,
-                },
-        },
-        [6] = {
-                .base   = S3C2410_GPGCON,
-                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
-                .irq_base = IRQ_EINT8,
-                .chip   = {
-                        .base                   = S3C2410_GPG(0),
-                        .owner                  = THIS_MODULE,
-                        .label                  = "GPIOG",
-                        .ngpio                  = 16,
-                        .to_irq                 = samsung_gpiolib_to_irq,
-                },
-        }, {
-                .base   = S3C2410_GPHCON,
-                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
-                .chip   = {
-                        .base                   = S3C2410_GPH(0),
-                        .owner                  = THIS_MODULE,
-                        .label                  = "GPIOH",
-                        .ngpio                  = 11,
-                },
-        },
-                /* GPIOS for the S3C2443 and later devices. */
-        {
-                .base   = S3C2440_GPJCON,
-                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
-                .chip   = {
-                        .base                   = S3C2410_GPJ(0),
-                        .owner                  = THIS_MODULE,
-                        .label                  = "GPIOJ",
-                        .ngpio                  = 16,
-                },
-        }, {
-                .base   = S3C2443_GPKCON,
-                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
-                .chip   = {
-                        .base                   = S3C2410_GPK(0),
-                        .owner                  = THIS_MODULE,
-                        .label                  = "GPIOK",
-                        .ngpio                  = 16,
-                },
-        }, {
-                .base   = S3C2443_GPLCON,
-                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
-                .chip   = {
-                        .base                   = S3C2410_GPL(0),
-                        .owner                  = THIS_MODULE,
-                        .label                  = "GPIOL",
-                        .ngpio                  = 15,
-                },
-        }, {
-                .base   = S3C2443_GPMCON,
-                .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
-                .chip   = {
-                        .base                   = S3C2410_GPM(0),
-                        .owner                  = THIS_MODULE,
-                        .label                  = "GPIOM",
-                        .ngpio                  = 2,
-                },
-        },
-};
-
-
-static __init int s3c24xx_gpiolib_init(void)
-{
-        struct s3c_gpio_chip *chip = s3c24xx_gpios;
-        int gpn;
-
-        for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++) {
-                if (!chip->config)
-                        chip->config = &s3c24xx_gpiocfg_default;
-
-                s3c_gpiolib_add(chip);
-        }
-
-        return 0;
-}
-
-core_initcall(s3c24xx_gpiolib_init);
diff --git a/arch/arm/plat-s3c24xx/include/mach/clkdev.h b/arch/arm/plat-s3c24xx/include/mach/clkdev.h
deleted file mode 100644
index 7dffa83d23ff..000000000000
--- a/arch/arm/plat-s3c24xx/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __MACH_CLKDEV_H__
-#define __MACH_CLKDEV_H__
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do {} while (0)
-
-#endif
diff --git a/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h b/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
deleted file mode 100644
index a087de21bc20..000000000000
--- a/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* linux/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
- *
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S3C24xx - pwm clock and timer support
- */
-
-/**
- * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
- * @cfg: The timer TCFG1 register bits shifted down to 0.
- *
- * Return true if the given configuration from TCFG1 is a TCLK instead
- * any of the TDIV clocks.
- */
-static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
-{
-        return tcfg == S3C2410_TCFG1_MUX_TCLK;
-}
-
-/**
- * tcfg_to_divisor() - convert tcfg1 setting to a divisor
- * @tcfg1: The tcfg1 setting, shifted down.
- *
- * Get the divisor value for the given tcfg1 setting. We assume the
- * caller has already checked to see if this is not a TCLK source.
- */
-static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
-{
-        return 1 << (1 + tcfg1);
-}
-
-/**
- * pwm_tdiv_has_div1() - does the tdiv setting have a /1
- *
- * Return true if we have a /1 in the tdiv setting.
- */
-static inline unsigned int pwm_tdiv_has_div1(void)
-{
-        return 0;
-}
-
-/**
- * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
- * @div: The divisor to calculate the bit information for.
- *
- * Turn a divisor into the necessary bit field for TCFG1.
- */
-static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
-{
-        return ilog2(div) - 1;
-}
-
-#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK
diff --git a/arch/arm/plat-s3c24xx/include/plat/map.h b/arch/arm/plat-s3c24xx/include/plat/map.h
deleted file mode 100644
index bd534d32b993..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/map.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/map.h
- *
- * Copyright (c) 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C24XX - Memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_PLAT_S3C24XX_MAP_H
-#define __ASM_PLAT_S3C24XX_MAP_H
-
-/* interrupt controller is the first thing we put in, to make
- * the assembly code for the irq detection easier
- */
-#define S3C24XX_VA_IRQ     S3C_VA_IRQ
-#define S3C2410_PA_IRQ     (0x4A000000)
-#define S3C24XX_SZ_IRQ     SZ_1M
-
-/* memory controller registers */
-#define S3C24XX_VA_MEMCTRL S3C_VA_MEM
-#define S3C2410_PA_MEMCTRL (0x48000000)
-#define S3C24XX_SZ_MEMCTRL SZ_1M
-
-/* UARTs */
-#define S3C24XX_VA_UART    S3C_VA_UART
-#define S3C2410_PA_UART    (0x50000000)
-#define S3C24XX_SZ_UART    SZ_1M
-#define S3C_UART_OFFSET    (0x4000)
-
-#define S3C_VA_UARTx(uart) (S3C_VA_UART + ((uart * S3C_UART_OFFSET)))
-
-/* Timers */
-#define S3C24XX_VA_TIMER   S3C_VA_TIMER
-#define S3C2410_PA_TIMER   (0x51000000)
-#define S3C24XX_SZ_TIMER   SZ_1M
-
-/* Clock and Power management */
-#define S3C24XX_VA_CLKPWR  S3C_VA_SYS
-#define S3C24XX_SZ_CLKPWR  SZ_1M
-
-/* USB Device port */
-#define S3C2410_PA_USBDEV  (0x52000000)
-#define S3C24XX_SZ_USBDEV  SZ_1M
-
-/* Watchdog */
-#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG
-#define S3C2410_PA_WATCHDOG (0x53000000)
-#define S3C24XX_SZ_WATCHDOG SZ_1M
-
-/* Standard size definitions for peripheral blocks. */
-
-#define S3C24XX_SZ_IIS          SZ_1M
-#define S3C24XX_SZ_ADC          SZ_1M
-#define S3C24XX_SZ_SPI          SZ_1M
-#define S3C24XX_SZ_SDI          SZ_1M
-#define S3C24XX_SZ_NAND         SZ_1M
-
-/* GPIO ports */
-
-/* the calculation for the VA of this must ensure that
- * it is the same distance apart from the UART in the
- * phsyical address space, as the initial mapping for the IO
- * is done as a 1:1 mapping. This puts it (currently) at
- * 0xFA800000, which is not in the way of any current mapping
- * by the base system.
-*/
-
-#define S3C2410_PA_GPIO    (0x56000000)
-#define S3C24XX_VA_GPIO    ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
-#define S3C24XX_SZ_GPIO    SZ_1M
-
-
-/* ISA style IO, for each machine to sort out mappings for, if it
- * implements it. We reserve two 16M regions for ISA.
- */
-
-#define S3C24XX_VA_ISA_WORD  S3C2410_ADDR(0x02000000)
-#define S3C24XX_VA_ISA_BYTE  S3C2410_ADDR(0x03000000)
-
-/* deal with the registers that move under the 2412/2413 */
-
-#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
-#ifndef __ASSEMBLY__
-extern void __iomem *s3c24xx_va_gpio2;
-#endif
-#ifdef CONFIG_CPU_S3C2412_ONLY
-#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
-#else
-#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
-#endif
-#else
-#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
-#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
-#endif
-
-#endif /* __ASM_PLAT_S3C24XX_MAP_H */
diff --git a/arch/arm/plat-s3c24xx/include/plat/pll.h b/arch/arm/plat-s3c24xx/include/plat/pll.h
deleted file mode 100644
index 005729a1077a..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/pll.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* linux/arch/arm/plat-s3c24xx/include/plat/pll.h
- *
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S3C24xx - common pll registers and code
- */
-
-#define S3C24XX_PLLCON_MDIVSHIFT        12
-#define S3C24XX_PLLCON_PDIVSHIFT        4
-#define S3C24XX_PLLCON_SDIVSHIFT        0
-#define S3C24XX_PLLCON_MDIVMASK         ((1<<(1+(19-12)))-1)
-#define S3C24XX_PLLCON_PDIVMASK         ((1<<5)-1)
-#define S3C24XX_PLLCON_SDIVMASK         3
-
-#include <asm/div64.h>
-
-static inline unsigned int
-s3c24xx_get_pll(unsigned int pllval, unsigned int baseclk)
-{
-        unsigned int mdiv, pdiv, sdiv;
-        uint64_t fvco;
-
-        mdiv = pllval >> S3C24XX_PLLCON_MDIVSHIFT;
-        pdiv = pllval >> S3C24XX_PLLCON_PDIVSHIFT;
-        sdiv = pllval >> S3C24XX_PLLCON_SDIVSHIFT;
-
-        mdiv &= S3C24XX_PLLCON_MDIVMASK;
-        pdiv &= S3C24XX_PLLCON_PDIVMASK;
-        sdiv &= S3C24XX_PLLCON_SDIVMASK;
-
-        fvco = (uint64_t)baseclk * (mdiv + 8);
-        do_div(fvco, (pdiv + 2) << sdiv);
-
-        return (unsigned int)fvco;
-}
-
-#define S3C2416_PLL_M_SHIFT     (14)
-#define S3C2416_PLL_P_SHIFT     (5)
-#define S3C2416_PLL_S_MASK      (7)
-#define S3C2416_PLL_M_MASK      ((1 << 10) - 1)
-#define S3C2416_PLL_P_MASK      (63)
-
-static inline unsigned int
-s3c2416_get_pll(unsigned int pllval, unsigned int baseclk)
-{
-        unsigned int m, p, s;
-        uint64_t fvco;
-
-        m = pllval >> S3C2416_PLL_M_SHIFT;
-        p = pllval >> S3C2416_PLL_P_SHIFT;
-
-        s = pllval & S3C2416_PLL_S_MASK;
-        m &= S3C2416_PLL_M_MASK;
-        p &= S3C2416_PLL_P_MASK;
-
-        fvco = (uint64_t)baseclk * m;
-        do_div(fvco, (p << s));
-
-        return (unsigned int)fvco;
-}
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-iis.h b/arch/arm/plat-s3c24xx/include/plat/regs-iis.h
deleted file mode 100644
index cc44e0e931e9..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/regs-iis.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-iis.h
- *
- * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
- *                    http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 IIS register definition
-*/
-
-#ifndef __ASM_ARCH_REGS_IIS_H
-#define __ASM_ARCH_REGS_IIS_H
-
-#define S3C2410_IISCON   (0x00)
-
-#define S3C2410_IISCON_LRINDEX    (1<<8)
-#define S3C2410_IISCON_TXFIFORDY  (1<<7)
-#define S3C2410_IISCON_RXFIFORDY  (1<<6)
-#define S3C2410_IISCON_TXDMAEN    (1<<5)
-#define S3C2410_IISCON_RXDMAEN    (1<<4)
-#define S3C2410_IISCON_TXIDLE     (1<<3)
-#define S3C2410_IISCON_RXIDLE     (1<<2)
-#define S3C2410_IISCON_PSCEN      (1<<1)
-#define S3C2410_IISCON_IISEN      (1<<0)
-
-#define S3C2410_IISMOD   (0x04)
-
-#define S3C2440_IISMOD_MPLL       (1<<9)
-#define S3C2410_IISMOD_SLAVE      (1<<8)
-#define S3C2410_IISMOD_NOXFER     (0<<6)
-#define S3C2410_IISMOD_RXMODE     (1<<6)
-#define S3C2410_IISMOD_TXMODE     (2<<6)
-#define S3C2410_IISMOD_TXRXMODE   (3<<6)
-#define S3C2410_IISMOD_LR_LLOW    (0<<5)
-#define S3C2410_IISMOD_LR_RLOW    (1<<5)
-#define S3C2410_IISMOD_IIS        (0<<4)
-#define S3C2410_IISMOD_MSB        (1<<4)
-#define S3C2410_IISMOD_8BIT       (0<<3)
-#define S3C2410_IISMOD_16BIT      (1<<3)
-#define S3C2410_IISMOD_BITMASK    (1<<3)
-#define S3C2410_IISMOD_256FS      (0<<2)
-#define S3C2410_IISMOD_384FS      (1<<2)
-#define S3C2410_IISMOD_16FS       (0<<0)
-#define S3C2410_IISMOD_32FS       (1<<0)
-#define S3C2410_IISMOD_48FS       (2<<0)
-#define S3C2410_IISMOD_FS_MASK    (3<<0)
-
-#define S3C2410_IISPSR          (0x08)
-#define S3C2410_IISPSR_INTMASK  (31<<5)
-#define S3C2410_IISPSR_INTSHIFT (5)
-#define S3C2410_IISPSR_EXTMASK  (31<<0)
-#define S3C2410_IISPSR_EXTSHFIT (0)
-
-#define S3C2410_IISFCON  (0x0c)
-
-#define S3C2410_IISFCON_TXDMA     (1<<15)
-#define S3C2410_IISFCON_RXDMA     (1<<14)
-#define S3C2410_IISFCON_TXENABLE  (1<<13)
-#define S3C2410_IISFCON_RXENABLE  (1<<12)
-#define S3C2410_IISFCON_TXMASK    (0x3f << 6)
-#define S3C2410_IISFCON_TXSHIFT   (6)
-#define S3C2410_IISFCON_RXMASK    (0x3f)
-#define S3C2410_IISFCON_RXSHIFT   (0)
-
-#define S3C2410_IISFIFO  (0x10)
-#endif /* __ASM_ARCH_REGS_IIS_H */
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-spi.h b/arch/arm/plat-s3c24xx/include/plat/regs-spi.h
deleted file mode 100644
index 892e2f680fca..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/regs-spi.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-spi.h
- *
- * Copyright (c) 2004 Fetron GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 SPI register definition
-*/
-
-#ifndef __ASM_ARCH_REGS_SPI_H
-#define __ASM_ARCH_REGS_SPI_H
-
-#define S3C2410_SPI1    (0x20)
-#define S3C2412_SPI1    (0x100)
-
-#define S3C2410_SPCON   (0x00)
-
-#define S3C2412_SPCON_RXFIFO_RB2        (0<<14)
-#define S3C2412_SPCON_RXFIFO_RB4        (1<<14)
-#define S3C2412_SPCON_RXFIFO_RB12       (2<<14)
-#define S3C2412_SPCON_RXFIFO_RB14       (3<<14)
-#define S3C2412_SPCON_TXFIFO_RB2        (0<<12)
-#define S3C2412_SPCON_TXFIFO_RB4        (1<<12)
-#define S3C2412_SPCON_TXFIFO_RB12       (2<<12)
-#define S3C2412_SPCON_TXFIFO_RB14       (3<<12)
-#define S3C2412_SPCON_RXFIFO_RESET      (1<<11) /* RxFIFO reset */
-#define S3C2412_SPCON_TXFIFO_RESET      (1<<10) /* TxFIFO reset */
-#define S3C2412_SPCON_RXFIFO_EN         (1<<9)  /* RxFIFO Enable */
-#define S3C2412_SPCON_TXFIFO_EN         (1<<8)  /* TxFIFO Enable */
-
-#define S3C2412_SPCON_DIRC_RX     (1<<7)
-
-#define S3C2410_SPCON_SMOD_DMA    (2<<5)        /* DMA mode */
-#define S3C2410_SPCON_SMOD_INT    (1<<5)        /* interrupt mode */
-#define S3C2410_SPCON_SMOD_POLL   (0<<5)        /* polling mode */
-#define S3C2410_SPCON_ENSCK       (1<<4)        /* Enable SCK */
-#define S3C2410_SPCON_MSTR        (1<<3)        /* Master/Slave select
-                                                   0: slave, 1: master */
-#define S3C2410_SPCON_CPOL_HIGH   (1<<2)        /* Clock polarity select */
-#define S3C2410_SPCON_CPOL_LOW    (0<<2)        /* Clock polarity select */
-
-#define S3C2410_SPCON_CPHA_FMTB   (1<<1)        /* Clock Phase Select */
-#define S3C2410_SPCON_CPHA_FMTA   (0<<1)        /* Clock Phase Select */
-
-#define S3C2410_SPCON_TAGD        (1<<0)        /* Tx auto garbage data mode */
-
-
-#define S3C2410_SPSTA    (0x04)
-
-#define S3C2412_SPSTA_RXFIFO_AE         (1<<11)
-#define S3C2412_SPSTA_TXFIFO_AE         (1<<10)
-#define S3C2412_SPSTA_RXFIFO_ERROR      (1<<9)
-#define S3C2412_SPSTA_TXFIFO_ERROR      (1<<8)
-#define S3C2412_SPSTA_RXFIFO_FIFO       (1<<7)
-#define S3C2412_SPSTA_RXFIFO_EMPTY      (1<<6)
-#define S3C2412_SPSTA_TXFIFO_NFULL      (1<<5)
-#define S3C2412_SPSTA_TXFIFO_EMPTY      (1<<4)
-
-#define S3C2410_SPSTA_DCOL        (1<<2)        /* Data Collision Error */
-#define S3C2410_SPSTA_MULD        (1<<1)        /* Multi Master Error */
-#define S3C2410_SPSTA_READY       (1<<0)        /* Data Tx/Rx ready */
-#define S3C2412_SPSTA_READY_ORG   (1<<3)
-
-#define S3C2410_SPPIN    (0x08)
-
-#define S3C2410_SPPIN_ENMUL       (1<<2)        /* Multi Master Error detect */
-#define S3C2410_SPPIN_RESERVED    (1<<1)
-#define S3C2410_SPPIN_KEEP        (1<<0)        /* Master Out keep */
-
-#define S3C2410_SPPRE    (0x0C)
-#define S3C2410_SPTDAT   (0x10)
-#define S3C2410_SPRDAT   (0x14)
-
-#define S3C2412_TXFIFO   (0x18)
-#define S3C2412_RXFIFO   (0x18)
-#define S3C2412_SPFIC    (0x24)
-
-
-#endif /* __ASM_ARCH_REGS_SPI_H */
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c
index 59552c0ea5fb..07a4c81587ac 100644
--- a/arch/arm/plat-s3c24xx/s3c2443-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c
@@ -205,9 +205,64 @@ static struct clksrc_clk clksrc_clks[] = {
         },
 };
 
+static struct clk clk_i2s_ext = {
+        .name           = "i2s-ext",
+};
+
+/* i2s_eplldiv
+ *
+ * This clock is the output from the I2S divisor of ESYSCLK, and is separate
+ * from the mux that comes after it (cannot merge into one single clock)
+*/
+
+static struct clksrc_clk clk_i2s_eplldiv = {
+        .clk    = {
+                .name           = "i2s-eplldiv",
+                .parent         = &clk_esysclk.clk,
+        },
+        .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
+};
+
+/* i2s-ref
+ *
+ * i2s bus reference clock, selectable from external, esysclk or epllref
+ *
+ * Note, this used to be two clocks, but was compressed into one.
+*/
+
+static struct clk *clk_i2s_srclist[] = {
+        [0] = &clk_i2s_eplldiv.clk,
+        [1] = &clk_i2s_ext,
+        [2] = &clk_epllref.clk,
+        [3] = &clk_epllref.clk,
+};
+
+static struct clksrc_clk clk_i2s = {
+        .clk    = {
+                .name           = "i2s-if",
+                .ctrlbit        = S3C2443_SCLKCON_I2SCLK,
+                .enable         = s3c2443_clkcon_enable_s,
+
+        },
+        .sources = &(struct clksrc_sources) {
+                .sources = clk_i2s_srclist,
+                .nr_sources = ARRAY_SIZE(clk_i2s_srclist),
+        },
+        .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },
+};
 
 static struct clk init_clocks_off[] = {
         {
+                .name           = "iis",
+                .parent         = &clk_p,
+                .enable         = s3c2443_clkcon_enable_p,
+                .ctrlbit        = S3C2443_PCLKCON_IIS,
+        }, {
+                .name           = "hsspi",
+                .parent         = &clk_p,
+                .enable         = s3c2443_clkcon_enable_p,
+                .ctrlbit        = S3C2443_PCLKCON_HSSPI,
+        }, {
                 .name           = "adc",
                 .parent         = &clk_p,
                 .enable         = s3c2443_clkcon_enable_p,
@@ -406,6 +461,8 @@ static struct clk *clks[] __initdata = {
 };
 
 static struct clksrc_clk *clksrcs[] __initdata = {
+        &clk_i2s_eplldiv,
+        &clk_i2s,
         &clk_usb_bus_host,
         &clk_epllref,
         &clk_esysclk,
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 9843c954c042..7b9dadadb0a5 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -16,9 +16,6 @@ config PLAT_S5P
         select S3C_GPIO_TRACK
         select S5P_GPIO_DRVSTR
         select SAMSUNG_GPIOLIB_4BIT
-        select S3C_GPIO_CFG_S3C64XX
-        select S3C_GPIO_PULL_UPDOWN
-        select S3C_GPIO_CFG_S3C24XX
         select PLAT_SAMSUNG
         select SAMSUNG_CLKSRC
         select SAMSUNG_IRQ_VIC_TIMER
@@ -43,6 +40,12 @@ config S5P_HRT
         help
           Use the High Resolution timer support
 
+config S5P_PM
+        bool
+        help
+          Common code for power management support on S5P and newer SoCs
+          Note: Do not select this for S5P6440 and S5P6450.
+
 comment "System MMU"
 
 config S5P_SYSTEM_MMU
@@ -51,6 +54,12 @@ config S5P_SYSTEM_MMU
         help
           Say Y here if you want to enable System MMU
 
+config S5P_SLEEP
+        bool
+        help
+          Internal config node to apply common S5P sleep management code.
+          Can be selected by S5P and newer SoCs with similar sleep procedure.
+
 config S5P_DEV_FIMC0
         bool
         help
@@ -76,6 +85,11 @@ config S5P_DEV_FIMD0
         help
           Compile in platform device definitions for FIMD controller 0
 
+config S5P_DEV_I2C_HDMIPHY
+        bool
+        help
+          Compile in platform device definitions for I2C HDMIPHY controller
+
 config S5P_DEV_MFC
         bool
         help
@@ -96,6 +110,11 @@ config S5P_DEV_CSIS1
         help
           Compile in platform device definitions for MIPI-CSIS channel 1
 
+config S5P_DEV_TV
+        bool
+        help
+          Compile in platform device definition for TV interface
+
 config S5P_DEV_USB_EHCI
         bool
         help
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index 4b53e04eeca4..06401dc37b81 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -20,8 +20,8 @@ obj-y				+= irq.o
 obj-$(CONFIG_S5P_EXT_INT)       += irq-eint.o
 obj-$(CONFIG_S5P_GPIO_INT)      += irq-gpioint.o
 obj-$(CONFIG_S5P_SYSTEM_MMU)    += sysmmu.o
-obj-$(CONFIG_PM)                += pm.o
-obj-$(CONFIG_PM)                += irq-pm.o
+obj-$(CONFIG_S5P_PM)            += pm.o irq-pm.o
+obj-$(CONFIG_S5P_SLEEP)         += sleep.o
 obj-$(CONFIG_S5P_HRT)           += s5p-time.o
 
 # devices
@@ -31,8 +31,10 @@ obj-$(CONFIG_S5P_DEV_FIMC1)	+= dev-fimc1.o
 obj-$(CONFIG_S5P_DEV_FIMC2)     += dev-fimc2.o
 obj-$(CONFIG_S5P_DEV_FIMC3)     += dev-fimc3.o
 obj-$(CONFIG_S5P_DEV_FIMD0)     += dev-fimd0.o
+obj-$(CONFIG_S5P_DEV_I2C_HDMIPHY) += dev-i2c-hdmiphy.o
 obj-$(CONFIG_S5P_DEV_ONENAND)   += dev-onenand.o
 obj-$(CONFIG_S5P_DEV_CSIS0)     += dev-csis0.o
 obj-$(CONFIG_S5P_DEV_CSIS1)     += dev-csis1.o
+obj-$(CONFIG_S5P_DEV_TV)        += dev-tv.o
 obj-$(CONFIG_S5P_DEV_USB_EHCI)  += dev-ehci.o
 obj-$(CONFIG_S5P_SETUP_MIPIPHY) += setup-mipiphy.o
diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
index bbc2aa7449ca..7b0a28f73a68 100644
--- a/arch/arm/plat-s5p/cpu.c
+++ b/arch/arm/plat-s5p/cpu.c
@@ -33,48 +33,66 @@ static const char name_s5p6450[] = "S5P6450";
 static const char name_s5pc100[] = "S5PC100";
 static const char name_s5pv210[] = "S5PV210/S5PC110";
 static const char name_exynos4210[] = "EXYNOS4210";
+static const char name_exynos4212[] = "EXYNOS4212";
+static const char name_exynos4412[] = "EXYNOS4412";
 
 static struct cpu_table cpu_ids[] __initdata = {
         {
-                .idcode         = 0x56440100,
-                .idmask         = 0xfffff000,
+                .idcode         = S5P6440_CPU_ID,
+                .idmask         = S5P64XX_CPU_MASK,
                 .map_io         = s5p6440_map_io,
                 .init_clocks    = s5p6440_init_clocks,
                 .init_uarts     = s5p6440_init_uarts,
                 .init           = s5p64x0_init,
                 .name           = name_s5p6440,
         }, {
-                .idcode         = 0x36450000,
-                .idmask         = 0xfffff000,
+                .idcode         = S5P6450_CPU_ID,
+                .idmask         = S5P64XX_CPU_MASK,
                 .map_io         = s5p6450_map_io,
                 .init_clocks    = s5p6450_init_clocks,
                 .init_uarts     = s5p6450_init_uarts,
                 .init           = s5p64x0_init,
                 .name           = name_s5p6450,
         }, {
-                .idcode         = 0x43100000,
-                .idmask         = 0xfffff000,
+                .idcode         = S5PC100_CPU_ID,
+                .idmask         = S5PC100_CPU_MASK,
                 .map_io         = s5pc100_map_io,
                 .init_clocks    = s5pc100_init_clocks,
                 .init_uarts     = s5pc100_init_uarts,
                 .init           = s5pc100_init,
                 .name           = name_s5pc100,
         }, {
-                .idcode         = 0x43110000,
-                .idmask         = 0xfffff000,
+                .idcode         = S5PV210_CPU_ID,
+                .idmask         = S5PV210_CPU_MASK,
                 .map_io         = s5pv210_map_io,
                 .init_clocks    = s5pv210_init_clocks,
                 .init_uarts     = s5pv210_init_uarts,
                 .init           = s5pv210_init,
                 .name           = name_s5pv210,
         }, {
-                .idcode         = 0x43210000,
-                .idmask         = 0xfffe0000,
+                .idcode         = EXYNOS4210_CPU_ID,
+                .idmask         = EXYNOS4_CPU_MASK,
                 .map_io         = exynos4_map_io,
                 .init_clocks    = exynos4_init_clocks,
                 .init_uarts     = exynos4_init_uarts,
                 .init           = exynos4_init,
                 .name           = name_exynos4210,
+        }, {
+                .idcode         = EXYNOS4212_CPU_ID,
+                .idmask         = EXYNOS4_CPU_MASK,
+                .map_io         = exynos4_map_io,
+                .init_clocks    = exynos4_init_clocks,
+                .init_uarts     = exynos4_init_uarts,
+                .init           = exynos4_init,
+                .name           = name_exynos4212,
+        }, {
+                .idcode         = EXYNOS4412_CPU_ID,
+                .idmask         = EXYNOS4_CPU_MASK,
+                .map_io         = exynos4_map_io,
+                .init_clocks    = exynos4_init_clocks,
+                .init_uarts     = exynos4_init_uarts,
+                .init           = exynos4_init,
+                .name           = name_exynos4412,
         },
 };
 
@@ -114,13 +132,13 @@ static struct map_desc s5p_iodesc[] __initdata = {
 void __init s5p_init_io(struct map_desc *mach_desc,
                         int size, void __iomem *cpuid_addr)
 {
-        unsigned long idcode;
-
         /* initialize the io descriptors we need for initialization */
         iotable_init(s5p_iodesc, ARRAY_SIZE(s5p_iodesc));
         if (mach_desc)
                 iotable_init(mach_desc, size);
 
-        idcode = __raw_readl(cpuid_addr);
-        s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
+        /* detect cpu id and rev. */
+        s5p_init_cpu(cpuid_addr);
+
+        s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 }
diff --git a/arch/arm/plat-s5p/dev-i2c-hdmiphy.c b/arch/arm/plat-s5p/dev-i2c-hdmiphy.c
new file mode 100644
index 000000000000..37343f1999f0
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-i2c-hdmiphy.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * S5P series device definition for i2c for hdmiphy device
+ *
+ * Based on plat-samsung/dev-i2c7.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/gfp.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+#include <mach/i2c-hdmiphy.h>
+
+#include <plat/regs-iic.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+#include <plat/iic.h>
+
+static struct resource s5p_i2c_resource[] = {
+        [0] = {
+                .start = S5P_PA_IIC_HDMIPHY,
+                .end   = S5P_PA_IIC_HDMIPHY + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_IIC_HDMIPHY,
+                .end   = IRQ_IIC_HDMIPHY,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device s5p_device_i2c_hdmiphy = {
+        .name             = "s3c2440-hdmiphy-i2c",
+        .id               = -1,
+        .num_resources    = ARRAY_SIZE(s5p_i2c_resource),
+        .resource         = s5p_i2c_resource,
+};
+
+void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
+{
+        struct s3c2410_platform_i2c *npd;
+
+        if (!pd) {
+                pd = &default_i2c_data;
+                pd->bus_num = S5P_I2C_HDMIPHY_BUS_NUM;
+        }
+
+        npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
+                               &s5p_device_i2c_hdmiphy);
+}
diff --git a/arch/arm/plat-s5p/dev-tv.c b/arch/arm/plat-s5p/dev-tv.c
new file mode 100644
index 000000000000..361a1b63a81b
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-tv.c
@@ -0,0 +1,98 @@
+/* linux/arch/arm/plat-s5p/dev-tv.c
+ *
+ * Copyright (C) 2011 Samsung Electronics Co.Ltd
+ * Author: Tomasz Stanislawski <t.stanislaws@samsung.com>
+ *
+ * S5P series device definition for TV device
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/dma-mapping.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include <plat/devs.h>
+
+/* HDMI interface */
+static struct resource s5p_hdmi_resources[] = {
+        [0] = {
+                .start  = S5P_PA_HDMI,
+                .end    = S5P_PA_HDMI + SZ_1M - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_HDMI,
+                .end    = IRQ_HDMI,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device s5p_device_hdmi = {
+        .name           = "s5p-hdmi",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(s5p_hdmi_resources),
+        .resource       = s5p_hdmi_resources,
+};
+EXPORT_SYMBOL(s5p_device_hdmi);
+
+/* SDO interface */
+static struct resource s5p_sdo_resources[] = {
+        [0] = {
+                .start  = S5P_PA_SDO,
+                .end    = S5P_PA_SDO + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_SDO,
+                .end    = IRQ_SDO,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device s5p_device_sdo = {
+        .name           = "s5p-sdo",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(s5p_sdo_resources),
+        .resource       = s5p_sdo_resources,
+};
+EXPORT_SYMBOL(s5p_device_sdo);
+
+/* MIXER */
+static struct resource s5p_mixer_resources[] = {
+        [0] = {
+                .start  = S5P_PA_MIXER,
+                .end    = S5P_PA_MIXER + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+                .name   = "mxr"
+        },
+        [1] = {
+                .start  = S5P_PA_VP,
+                .end    = S5P_PA_VP + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+                .name   = "vp"
+        },
+        [2] = {
+                .start  = IRQ_MIXER,
+                .end    = IRQ_MIXER,
+                .flags  = IORESOURCE_IRQ,
+                .name   = "irq"
+        }
+};
+
+static u64 s5p_tv_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device s5p_device_mixer = {
+        .name           = "s5p-mixer",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(s5p_mixer_resources),
+        .resource       = s5p_mixer_resources,
+        .dev            = {
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+                .dma_mask = &s5p_tv_dmamask,
+        }
+};
+EXPORT_SYMBOL(s5p_device_mixer);
diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-s5p/include/plat/pll.h
deleted file mode 100644
index bf28fadee7ae..000000000000
--- a/arch/arm/plat-s5p/include/plat/pll.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/* arch/arm/plat-s5p/include/plat/pll.h
- *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5P PLL code
- *
- * Based on arch/arm/plat-s3c64xx/include/plat/pll.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#define PLL45XX_MDIV_MASK       (0x3FF)
-#define PLL45XX_PDIV_MASK       (0x3F)
-#define PLL45XX_SDIV_MASK       (0x7)
-#define PLL45XX_MDIV_SHIFT      (16)
-#define PLL45XX_PDIV_SHIFT      (8)
-#define PLL45XX_SDIV_SHIFT      (0)
-
-#include <asm/div64.h>
-
-enum pll45xx_type_t {
-        pll_4500,
-        pll_4502,
-        pll_4508
-};
-
-static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con,
-                                            enum pll45xx_type_t pll_type)
-{
-        u32 mdiv, pdiv, sdiv;
-        u64 fvco = baseclk;
-
-        mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
-        pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
-        sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
-
-        if (pll_type == pll_4508)
-                sdiv = sdiv - 1;
-
-        fvco *= mdiv;
-        do_div(fvco, (pdiv << sdiv));
-
-        return (unsigned long)fvco;
-}
-
-#define PLL46XX_KDIV_MASK       (0xFFFF)
-#define PLL4650C_KDIV_MASK      (0xFFF)
-#define PLL46XX_MDIV_MASK       (0x1FF)
-#define PLL46XX_PDIV_MASK       (0x3F)
-#define PLL46XX_SDIV_MASK       (0x7)
-#define PLL46XX_MDIV_SHIFT      (16)
-#define PLL46XX_PDIV_SHIFT      (8)
-#define PLL46XX_SDIV_SHIFT      (0)
-
-enum pll46xx_type_t {
-        pll_4600,
-        pll_4650,
-        pll_4650c,
-};
-
-static inline unsigned long s5p_get_pll46xx(unsigned long baseclk,
-                                            u32 pll_con0, u32 pll_con1,
-                                            enum pll46xx_type_t pll_type)
-{
-        unsigned long result;
-        u32 mdiv, pdiv, sdiv, kdiv;
-        u64 tmp;
-
-        mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
-        pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
-        sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
-        kdiv = pll_con1 & PLL46XX_KDIV_MASK;
-
-        if (pll_type == pll_4650c)
-                kdiv = pll_con1 & PLL4650C_KDIV_MASK;
-        else
-                kdiv = pll_con1 & PLL46XX_KDIV_MASK;
-
-        tmp = baseclk;
-
-        if (pll_type == pll_4600) {
-                tmp *= (mdiv << 16) + kdiv;
-                do_div(tmp, (pdiv << sdiv));
-                result = tmp >> 16;
-        } else {
-                tmp *= (mdiv << 10) + kdiv;
-                do_div(tmp, (pdiv << sdiv));
-                result = tmp >> 10;
-        }
-
-        return result;
-}
-
-#define PLL90XX_MDIV_MASK       (0xFF)
-#define PLL90XX_PDIV_MASK       (0x3F)
-#define PLL90XX_SDIV_MASK       (0x7)
-#define PLL90XX_KDIV_MASK       (0xffff)
-#define PLL90XX_MDIV_SHIFT      (16)
-#define PLL90XX_PDIV_SHIFT      (8)
-#define PLL90XX_SDIV_SHIFT      (0)
-#define PLL90XX_KDIV_SHIFT      (0)
-
-static inline unsigned long s5p_get_pll90xx(unsigned long baseclk,
-                                            u32 pll_con, u32 pll_conk)
-{
-        unsigned long result;
-        u32 mdiv, pdiv, sdiv, kdiv;
-        u64 tmp;
-
-        mdiv = (pll_con >> PLL90XX_MDIV_SHIFT) & PLL90XX_MDIV_MASK;
-        pdiv = (pll_con >> PLL90XX_PDIV_SHIFT) & PLL90XX_PDIV_MASK;
-        sdiv = (pll_con >> PLL90XX_SDIV_SHIFT) & PLL90XX_SDIV_MASK;
-        kdiv = pll_conk & PLL90XX_KDIV_MASK;
-
-        /* We need to multiple baseclk by mdiv (the integer part) and kdiv
-         * which is in 2^16ths, so shift mdiv up (does not overflow) and
-         * add kdiv before multiplying. The use of tmp is to avoid any
-         * overflows before shifting bac down into result when multipling
-         * by the mdiv and kdiv pair.
-         */
-
-        tmp = baseclk;
-        tmp *= (mdiv << 16) + kdiv;
-        do_div(tmp, (pdiv << sdiv));
-        result = tmp >> 16;
-
-        return result;
-}
-
-#define PLL65XX_MDIV_MASK       (0x3FF)
-#define PLL65XX_PDIV_MASK       (0x3F)
-#define PLL65XX_SDIV_MASK       (0x7)
-#define PLL65XX_MDIV_SHIFT      (16)
-#define PLL65XX_PDIV_SHIFT      (8)
-#define PLL65XX_SDIV_SHIFT      (0)
-
-static inline unsigned long s5p_get_pll65xx(unsigned long baseclk, u32 pll_con)
-{
-        u32 mdiv, pdiv, sdiv;
-        u64 fvco = baseclk;
-
-        mdiv = (pll_con >> PLL65XX_MDIV_SHIFT) & PLL65XX_MDIV_MASK;
-        pdiv = (pll_con >> PLL65XX_PDIV_SHIFT) & PLL65XX_PDIV_MASK;
-        sdiv = (pll_con >> PLL65XX_SDIV_SHIFT) & PLL65XX_SDIV_MASK;
-
-        fvco *= mdiv;
-        do_div(fvco, (pdiv << sdiv));
-
-        return (unsigned long)fvco;
-}
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c
index f71078ef6bb5..a566523d34ec 100644
--- a/arch/arm/plat-s5p/irq-gpioint.c
+++ b/arch/arm/plat-s5p/irq-gpioint.c
@@ -37,7 +37,7 @@ struct s5p_gpioint_bank {
         int                     start;
         int                     nr_groups;
         int                     irq;
-        struct s3c_gpio_chip    **chips;
+        struct samsung_gpio_chip        **chips;
         void                    (*handler)(unsigned int, struct irq_desc *);
 };
 
@@ -87,7 +87,7 @@ static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
         chained_irq_enter(chip, desc);
 
         for (group = 0; group < bank->nr_groups; group++) {
-                struct s3c_gpio_chip *chip = bank->chips[group];
+                struct samsung_gpio_chip *chip = bank->chips[group];
                 if (!chip)
                         continue;
 
@@ -110,27 +110,28 @@ static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
         chained_irq_exit(chip, desc);
 }
 
-static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
+static __init int s5p_gpioint_add(struct samsung_gpio_chip *chip)
 {
         static int used_gpioint_groups = 0;
         int group = chip->group;
-        struct s5p_gpioint_bank *bank = NULL;
+        struct s5p_gpioint_bank *b, *bank = NULL;
         struct irq_chip_generic *gc;
         struct irq_chip_type *ct;
 
         if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT)
                 return -ENOMEM;
 
-        list_for_each_entry(bank, &banks, list) {
-                if (group >= bank->start &&
-                    group < bank->start + bank->nr_groups)
+        list_for_each_entry(b, &banks, list) {
+                if (group >= b->start && group < b->start + b->nr_groups) {
+                        bank = b;
                         break;
+                }
         }
         if (!bank)
                 return -EINVAL;
 
         if (!bank->handler) {
-                bank->chips = kzalloc(sizeof(struct s3c_gpio_chip *) *
+                bank->chips = kzalloc(sizeof(struct samsung_gpio_chip *) *
                                       bank->nr_groups, GFP_KERNEL);
                 if (!bank->chips)
                         return -ENOMEM;
@@ -173,7 +174,7 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
 
 int __init s5p_register_gpio_interrupt(int pin)
 {
-        struct s3c_gpio_chip *my_chip = s3c_gpiolib_getchip(pin);
+        struct samsung_gpio_chip *my_chip = samsung_gpiolib_getchip(pin);
         int offset, group;
         int ret;
 
diff --git a/arch/arm/mach-exynos4/sleep.S b/arch/arm/plat-s5p/sleep.S
index 0984078f1eba..0fd591bfc9fd 100644
--- a/arch/arm/mach-exynos4/sleep.S
+++ b/arch/arm/plat-s5p/sleep.S
@@ -1,15 +1,11 @@
-/* linux/arch/arm/mach-exynos4/sleep.S
+/* linux/arch/arm/plat-s5p/sleep.S
  *
  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
  *
- * EXYNOS4210 power Manager (Suspend-To-RAM) support
- * Based on S3C2410 sleep code by:
- *      Ben Dooks, (c) 2004 Simtec Electronics
- *
- * Based on PXA/SA1100 sleep code by:
- *      Nicolas Pitre, (c) 2002 Monta Vista Software Inc
- *      Cliff Brake, (c) 2001
+ * Common S5P Sleep Code
+ * Based on S3C64XX sleep code by:
+ *      Ben Dooks, (c) 2008 Simtec Electronics
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -28,7 +24,6 @@
 
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-#include <asm/memory.h>
 
         .text
 
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index b3e10659e4b8..74714c155e14 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -79,39 +79,12 @@ config SAMSUNG_GPIOLIB_4BIT
           configuration. GPIOlib shall be compiled only for S3C64XX and S5P
           series of processors.
 
-config S3C_GPIO_CFG_S3C24XX
-        bool
-        help
-          Internal configuration to enable S3C24XX style GPIO configuration
-          functions.
-
 config S3C_GPIO_CFG_S3C64XX
         bool
         help
           Internal configuration to enable S3C64XX style GPIO configuration
           functions.
 
-config S3C_GPIO_PULL_UPDOWN
-        bool
-        help
-          Internal configuration to enable the correct GPIO pull helper
-
-config S3C_GPIO_PULL_S3C2443
-        bool
-        select S3C_GPIO_PULL_UPDOWN
-        help
-          Internal configuration to enable the correct GPIO pull helper for S3C2443-style GPIO
-
-config S3C_GPIO_PULL_DOWN
-        bool
-        help
-          Internal configuration to enable the correct GPIO pull helper
-
-config S3C_GPIO_PULL_UP
-        bool
-        help
-          Internal configuration to enable the correct GPIO pull helper
-
 config S5P_GPIO_DRVSTR
         bool
         help
@@ -300,11 +273,14 @@ config S3C_DMA
         help
           Internal configuration for S3C DMA core
 
-config S3C_PL330_DMA
+config SAMSUNG_DMADEV
         bool
-        select PL330
+        select DMADEVICES
+        select PL330_DMA if (CPU_EXYNOS4210 || CPU_S5PV210 || CPU_S5PC100 || \
+                                        CPU_S5P6450 || CPU_S5P6440)
+        select ARM_AMBA
         help
-          S3C DMA API Driver for PL330 DMAC.
+          Use DMA device engine for PL330 DMAC.
 
 comment "Power management"
 
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 853764ba8cc5..5a5435482595 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -11,12 +11,10 @@ obj-				:=
 
 # Objects we always build independent of SoC choice
 
-obj-y                           += init.o
+obj-y                           += init.o cpu.o
 obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET)   += time.o
 obj-y                           += clock.o
 obj-y                           += pwm-clock.o
-obj-y                           += gpio.o
-obj-y                           += gpio-config.o
 obj-y                           += dev-asocdma.o
 
 obj-$(CONFIG_SAMSUNG_CLKSRC)    += clock-clksrc.o
@@ -63,9 +61,9 @@ obj-$(CONFIG_SAMSUNG_DEV_BACKLIGHT)	+= dev-backlight.o
 
 # DMA support
 
-obj-$(CONFIG_S3C_DMA)           += dma.o
+obj-$(CONFIG_S3C_DMA)           += dma.o s3c-dma-ops.o
 
-obj-$(CONFIG_S3C_PL330_DMA)     += s3c-pl330.o
+obj-$(CONFIG_SAMSUNG_DMADEV)    += dma-ops.o
 
 # PM support
 
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index 302c42670bd1..3b4451979d1b 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -64,6 +64,17 @@ static LIST_HEAD(clocks);
  */
 DEFINE_SPINLOCK(clocks_lock);
 
+/* Global watchdog clock used by arch_wtd_reset() callback */
+struct clk *s3c2410_wdtclk;
+static int __init s3c_wdt_reset_init(void)
+{
+        s3c2410_wdtclk = clk_get(NULL, "watchdog");
+        if (IS_ERR(s3c2410_wdtclk))
+                printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
+        return 0;
+}
+arch_initcall(s3c_wdt_reset_init);
+
 /* enable and disable calls for use with the clk struct */
 
 static int clk_null_enable(struct clk *clk, int enable)
diff --git a/arch/arm/plat-samsung/cpu.c b/arch/arm/plat-samsung/cpu.c
new file mode 100644
index 000000000000..81c06d44c11e
--- /dev/null
+++ b/arch/arm/plat-samsung/cpu.c
@@ -0,0 +1,58 @@
+/* linux/arch/arm/plat-samsung/cpu.c
+ *
+ * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Samsung CPU Support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+
+#include <asm/system.h>
+
+#include <mach/map.h>
+#include <plat/cpu.h>
+
+unsigned long samsung_cpu_id;
+static unsigned int samsung_cpu_rev;
+
+unsigned int samsung_rev(void)
+{
+        return samsung_cpu_rev;
+}
+EXPORT_SYMBOL(samsung_rev);
+
+void __init s3c24xx_init_cpu(void)
+{
+        /* nothing here yet */
+
+        samsung_cpu_rev = 0;
+}
+
+void __init s3c64xx_init_cpu(void)
+{
+        samsung_cpu_id = __raw_readl(S3C_VA_SYS + 0x118);
+        if (!samsung_cpu_id) {
+                /*
+                 * S3C6400 has the ID register in a different place,
+                 * and needs a write before it can be read.
+                 */
+                __raw_writel(0x0, S3C_VA_SYS + 0xA1C);
+                samsung_cpu_id = __raw_readl(S3C_VA_SYS + 0xA1C);
+        }
+
+        samsung_cpu_rev = 0;
+}
+
+void __init s5p_init_cpu(void __iomem *cpuid_addr)
+{
+        samsung_cpu_id = __raw_readl(cpuid_addr);
+        samsung_cpu_rev = samsung_cpu_id & 0xFF;
+}
diff --git a/arch/arm/plat-samsung/dev-hsmmc.c b/arch/arm/plat-samsung/dev-hsmmc.c
index db7a65c7f127..06825c4276de 100644
--- a/arch/arm/plat-samsung/dev-hsmmc.c
+++ b/arch/arm/plat-samsung/dev-hsmmc.c
@@ -58,22 +58,5 @@ struct platform_device s3c_device_hsmmc0 = {
 
 void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
 {
-        struct s3c_sdhci_platdata *set = &s3c_hsmmc0_def_platdata;
-
-        set->cd_type = pd->cd_type;
-        set->ext_cd_init = pd->ext_cd_init;
-        set->ext_cd_cleanup = pd->ext_cd_cleanup;
-        set->ext_cd_gpio = pd->ext_cd_gpio;
-        set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
-
-        if (pd->max_width)
-                set->max_width = pd->max_width;
-        if (pd->cfg_gpio)
-                set->cfg_gpio = pd->cfg_gpio;
-        if (pd->cfg_card)
-                set->cfg_card = pd->cfg_card;
-        if (pd->host_caps)
-                set->host_caps |= pd->host_caps;
-        if (pd->clk_type)
-                set->clk_type = pd->clk_type;
+        s3c_sdhci_set_platdata(pd, &s3c_hsmmc0_def_platdata);
 }
diff --git a/arch/arm/plat-samsung/dev-hsmmc1.c b/arch/arm/plat-samsung/dev-hsmmc1.c
index 2497321f08d7..4524ef440010 100644
--- a/arch/arm/plat-samsung/dev-hsmmc1.c
+++ b/arch/arm/plat-samsung/dev-hsmmc1.c
@@ -58,22 +58,5 @@ struct platform_device s3c_device_hsmmc1 = {
 
 void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
 {
-        struct s3c_sdhci_platdata *set = &s3c_hsmmc1_def_platdata;
-
-        set->cd_type = pd->cd_type;
-        set->ext_cd_init = pd->ext_cd_init;
-        set->ext_cd_cleanup = pd->ext_cd_cleanup;
-        set->ext_cd_gpio = pd->ext_cd_gpio;
-        set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
-
-        if (pd->max_width)
-                set->max_width = pd->max_width;
-        if (pd->cfg_gpio)
-                set->cfg_gpio = pd->cfg_gpio;
-        if (pd->cfg_card)
-                set->cfg_card = pd->cfg_card;
-        if (pd->host_caps)
-                set->host_caps |= pd->host_caps;
-        if (pd->clk_type)
-                set->clk_type = pd->clk_type;
+        s3c_sdhci_set_platdata(pd, &s3c_hsmmc1_def_platdata);
 }
diff --git a/arch/arm/plat-samsung/dev-hsmmc2.c b/arch/arm/plat-samsung/dev-hsmmc2.c
index f60aedba417c..9cede9615e48 100644
--- a/arch/arm/plat-samsung/dev-hsmmc2.c
+++ b/arch/arm/plat-samsung/dev-hsmmc2.c
@@ -59,22 +59,5 @@ struct platform_device s3c_device_hsmmc2 = {
 
 void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
 {
-        struct s3c_sdhci_platdata *set = &s3c_hsmmc2_def_platdata;
-
-        set->cd_type = pd->cd_type;
-        set->ext_cd_init = pd->ext_cd_init;
-        set->ext_cd_cleanup = pd->ext_cd_cleanup;
-        set->ext_cd_gpio = pd->ext_cd_gpio;
-        set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
-
-        if (pd->max_width)
-                set->max_width = pd->max_width;
-        if (pd->cfg_gpio)
-                set->cfg_gpio = pd->cfg_gpio;
-        if (pd->cfg_card)
-                set->cfg_card = pd->cfg_card;
-        if (pd->host_caps)
-                set->host_caps |= pd->host_caps;
-        if (pd->clk_type)
-                set->clk_type = pd->clk_type;
+        s3c_sdhci_set_platdata(pd, &s3c_hsmmc2_def_platdata);
 }
diff --git a/arch/arm/plat-samsung/dev-hsmmc3.c b/arch/arm/plat-samsung/dev-hsmmc3.c
index ede776f20e62..0358ef4a8f66 100644
--- a/arch/arm/plat-samsung/dev-hsmmc3.c
+++ b/arch/arm/plat-samsung/dev-hsmmc3.c
@@ -62,22 +62,5 @@ struct platform_device s3c_device_hsmmc3 = {
 
 void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd)
 {
-        struct s3c_sdhci_platdata *set = &s3c_hsmmc3_def_platdata;
-
-        set->cd_type = pd->cd_type;
-        set->ext_cd_init = pd->ext_cd_init;
-        set->ext_cd_cleanup = pd->ext_cd_cleanup;
-        set->ext_cd_gpio = pd->ext_cd_gpio;
-        set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
-
-        if (pd->max_width)
-                set->max_width = pd->max_width;
-        if (pd->cfg_gpio)
-                set->cfg_gpio = pd->cfg_gpio;
-        if (pd->cfg_card)
-                set->cfg_card = pd->cfg_card;
-        if (pd->host_caps)
-                set->host_caps |= pd->host_caps;
-        if (pd->clk_type)
-                set->clk_type = pd->clk_type;
+        s3c_sdhci_set_platdata(pd, &s3c_hsmmc3_def_platdata);
 }
diff --git a/arch/arm/plat-samsung/dev-ts.c b/arch/arm/plat-samsung/dev-ts.c
index 82543f0248ac..5f3d46a9bd88 100644
--- a/arch/arm/plat-samsung/dev-ts.c
+++ b/arch/arm/plat-samsung/dev-ts.c
@@ -43,8 +43,17 @@ struct platform_device s3c_device_ts = {
         .resource       = s3c_ts_resource,
 };
 
+static struct s3c2410_ts_mach_info default_ts_data __initdata = {
+        .delay                  = 10000,
+        .presc                  = 49,
+        .oversampling_shift     = 2,
+};
+
 void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
 {
+        if (!pd)
+                pd = &default_ts_data;
+
         s3c_set_platdata(pd, sizeof(struct s3c2410_ts_mach_info),
                          &s3c_device_ts);
 }
diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
new file mode 100644
index 000000000000..6e3d9abc9e2e
--- /dev/null
+++ b/arch/arm/plat-samsung/dma-ops.c
@@ -0,0 +1,131 @@
+/* linux/arch/arm/plat-samsung/dma-ops.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Samsung DMA Operations
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/amba/pl330.h>
+#include <linux/scatterlist.h>
+
+#include <mach/dma.h>
+
+static inline bool pl330_filter(struct dma_chan *chan, void *param)
+{
+        struct dma_pl330_peri *peri = chan->private;
+        return peri->peri_id == (unsigned)param;
+}
+
+static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
+                                struct samsung_dma_info *info)
+{
+        struct dma_chan *chan;
+        dma_cap_mask_t mask;
+        struct dma_slave_config slave_config;
+
+        dma_cap_zero(mask);
+        dma_cap_set(info->cap, mask);
+
+        chan = dma_request_channel(mask, pl330_filter, (void *)dma_ch);
+
+        if (info->direction == DMA_FROM_DEVICE) {
+                memset(&slave_config, 0, sizeof(struct dma_slave_config));
+                slave_config.direction = info->direction;
+                slave_config.src_addr = info->fifo;
+                slave_config.src_addr_width = info->width;
+                slave_config.src_maxburst = 1;
+                dmaengine_slave_config(chan, &slave_config);
+        } else if (info->direction == DMA_TO_DEVICE) {
+                memset(&slave_config, 0, sizeof(struct dma_slave_config));
+                slave_config.direction = info->direction;
+                slave_config.dst_addr = info->fifo;
+                slave_config.dst_addr_width = info->width;
+                slave_config.dst_maxburst = 1;
+                dmaengine_slave_config(chan, &slave_config);
+        }
+
+        return (unsigned)chan;
+}
+
+static int samsung_dmadev_release(unsigned ch,
+                        struct s3c2410_dma_client *client)
+{
+        dma_release_channel((struct dma_chan *)ch);
+
+        return 0;
+}
+
+static int samsung_dmadev_prepare(unsigned ch,
+                        struct samsung_dma_prep_info *info)
+{
+        struct scatterlist sg;
+        struct dma_chan *chan = (struct dma_chan *)ch;
+        struct dma_async_tx_descriptor *desc;
+
+        switch (info->cap) {
+        case DMA_SLAVE:
+                sg_init_table(&sg, 1);
+                sg_dma_len(&sg) = info->len;
+                sg_set_page(&sg, pfn_to_page(PFN_DOWN(info->buf)),
+                            info->len, offset_in_page(info->buf));
+                sg_dma_address(&sg) = info->buf;
+
+                desc = chan->device->device_prep_slave_sg(chan,
+                        &sg, 1, info->direction, DMA_PREP_INTERRUPT);
+                break;
+        case DMA_CYCLIC:
+                desc = chan->device->device_prep_dma_cyclic(chan,
+                        info->buf, info->len, info->period, info->direction);
+                break;
+        default:
+                dev_err(&chan->dev->device, "unsupported format\n");
+                return -EFAULT;
+        }
+
+        if (!desc) {
+                dev_err(&chan->dev->device, "cannot prepare cyclic dma\n");
+                return -EFAULT;
+        }
+
+        desc->callback = info->fp;
+        desc->callback_param = info->fp_param;
+
+        dmaengine_submit((struct dma_async_tx_descriptor *)desc);
+
+        return 0;
+}
+
+static inline int samsung_dmadev_trigger(unsigned ch)
+{
+        dma_async_issue_pending((struct dma_chan *)ch);
+
+        return 0;
+}
+
+static inline int samsung_dmadev_flush(unsigned ch)
+{
+        return dmaengine_terminate_all((struct dma_chan *)ch);
+}
+
+struct samsung_dma_ops dmadev_ops = {
+        .request        = samsung_dmadev_request,
+        .release        = samsung_dmadev_release,
+        .prepare        = samsung_dmadev_prepare,
+        .trigger        = samsung_dmadev_trigger,
+        .started        = NULL,
+        .flush          = samsung_dmadev_flush,
+        .stop           = samsung_dmadev_flush,
+};
+
+void *samsung_dmadev_get_ops(void)
+{
+        return &dmadev_ops;
+}
+EXPORT_SYMBOL(samsung_dmadev_get_ops);
diff --git a/arch/arm/plat-samsung/gpio-config.c b/arch/arm/plat-samsung/gpio-config.c
deleted file mode 100644
index 1c0b0401594b..000000000000
--- a/arch/arm/plat-samsung/gpio-config.c
+++ /dev/null
@@ -1,431 +0,0 @@
-/* linux/arch/arm/plat-s3c/gpio-config.c
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008-2010 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S3C series GPIO configuration core
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/gpio.h>
-#include <linux/io.h>
-
-#include <plat/gpio-core.h>
-#include <plat/gpio-cfg.h>
-#include <plat/gpio-cfg-helpers.h>
-
-int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
-{
-        struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
-        unsigned long flags;
-        int offset;
-        int ret;
-
-        if (!chip)
-                return -EINVAL;
-
-        offset = pin - chip->chip.base;
-
-        s3c_gpio_lock(chip, flags);
-        ret = s3c_gpio_do_setcfg(chip, offset, config);
-        s3c_gpio_unlock(chip, flags);
-
-        return ret;
-}
-EXPORT_SYMBOL(s3c_gpio_cfgpin);
-
-int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
-                          unsigned int cfg)
-{
-        int ret;
-
-        for (; nr > 0; nr--, start++) {
-                ret = s3c_gpio_cfgpin(start, cfg);
-                if (ret != 0)
-                        return ret;
-        }
-
-        return 0;
-}
-EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
-
-int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
-                          unsigned int cfg, s3c_gpio_pull_t pull)
-{
-        int ret;
-
-        for (; nr > 0; nr--, start++) {
-                s3c_gpio_setpull(start, pull);
-                ret = s3c_gpio_cfgpin(start, cfg);
-                if (ret != 0)
-                        return ret;
-        }
-
-        return 0;
-}
-EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
-
-unsigned s3c_gpio_getcfg(unsigned int pin)
-{
-        struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
-        unsigned long flags;
-        unsigned ret = 0;
-        int offset;
-
-        if (chip) {
-                offset = pin - chip->chip.base;
-
-                s3c_gpio_lock(chip, flags);
-                ret = s3c_gpio_do_getcfg(chip, offset);
-                s3c_gpio_unlock(chip, flags);
-        }
-
-        return ret;
-}
-EXPORT_SYMBOL(s3c_gpio_getcfg);
-
-
-int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull)
-{
-        struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
-        unsigned long flags;
-        int offset, ret;
-
-        if (!chip)
-                return -EINVAL;
-
-        offset = pin - chip->chip.base;
-
-        s3c_gpio_lock(chip, flags);
-        ret = s3c_gpio_do_setpull(chip, offset, pull);
-        s3c_gpio_unlock(chip, flags);
-
-        return ret;
-}
-EXPORT_SYMBOL(s3c_gpio_setpull);
-
-s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
-{
-        struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
-        unsigned long flags;
-        int offset;
-        u32 pup = 0;
-
-        if (chip) {
-                offset = pin - chip->chip.base;
-
-                s3c_gpio_lock(chip, flags);
-                pup = s3c_gpio_do_getpull(chip, offset);
-                s3c_gpio_unlock(chip, flags);
-        }
-
-        return (__force s3c_gpio_pull_t)pup;
-}
-EXPORT_SYMBOL(s3c_gpio_getpull);
-
-#ifdef CONFIG_S3C_GPIO_CFG_S3C24XX
-int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
-                              unsigned int off, unsigned int cfg)
-{
-        void __iomem *reg = chip->base;
-        unsigned int shift = off;
-        u32 con;
-
-        if (s3c_gpio_is_cfg_special(cfg)) {
-                cfg &= 0xf;
-
-                /* Map output to 0, and SFN2 to 1 */
-                cfg -= 1;
-                if (cfg > 1)
-                        return -EINVAL;
-
-                cfg <<= shift;
-        }
-
-        con = __raw_readl(reg);
-        con &= ~(0x1 << shift);
-        con |= cfg;
-        __raw_writel(con, reg);
-
-        return 0;
-}
-
-unsigned s3c_gpio_getcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
-                                   unsigned int off)
-{
-        u32 con;
-
-        con = __raw_readl(chip->base);
-        con >>= off;
-        con &= 1;
-        con++;
-
-        return S3C_GPIO_SFN(con);
-}
-
-int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
-                            unsigned int off, unsigned int cfg)
-{
-        void __iomem *reg = chip->base;
-        unsigned int shift = off * 2;
-        u32 con;
-
-        if (s3c_gpio_is_cfg_special(cfg)) {
-                cfg &= 0xf;
-                if (cfg > 3)
-                        return -EINVAL;
-
-                cfg <<= shift;
-        }
-
-        con = __raw_readl(reg);
-        con &= ~(0x3 << shift);
-        con |= cfg;
-        __raw_writel(con, reg);
-
-        return 0;
-}
-
-unsigned int s3c_gpio_getcfg_s3c24xx(struct s3c_gpio_chip *chip,
-                                     unsigned int off)
-{
-        u32 con;
-
-        con = __raw_readl(chip->base);
-        con >>= off * 2;
-        con &= 3;
-
-        /* this conversion works for IN and OUT as well as special mode */
-        return S3C_GPIO_SPECIAL(con);
-}
-#endif
-
-#ifdef CONFIG_S3C_GPIO_CFG_S3C64XX
-int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
-                                 unsigned int off, unsigned int cfg)
-{
-        void __iomem *reg = chip->base;
-        unsigned int shift = (off & 7) * 4;
-        u32 con;
-
-        if (off < 8 && chip->chip.ngpio > 8)
-                reg -= 4;
-
-        if (s3c_gpio_is_cfg_special(cfg)) {
-                cfg &= 0xf;
-                cfg <<= shift;
-        }
-
-        con = __raw_readl(reg);
-        con &= ~(0xf << shift);
-        con |= cfg;
-        __raw_writel(con, reg);
-
-        return 0;
-}
-
-unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
-                                      unsigned int off)
-{
-        void __iomem *reg = chip->base;
-        unsigned int shift = (off & 7) * 4;
-        u32 con;
-
-        if (off < 8 && chip->chip.ngpio > 8)
-                reg -= 4;
-
-        con = __raw_readl(reg);
-        con >>= shift;
-        con &= 0xf;
-
-        /* this conversion works for IN and OUT as well as special mode */
-        return S3C_GPIO_SPECIAL(con);
-}
-
-#endif /* CONFIG_S3C_GPIO_CFG_S3C64XX */
-
-#ifdef CONFIG_S3C_GPIO_PULL_UPDOWN
-int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip,
-                            unsigned int off, s3c_gpio_pull_t pull)
-{
-        void __iomem *reg = chip->base + 0x08;
-        int shift = off * 2;
-        u32 pup;
-
-        pup = __raw_readl(reg);
-        pup &= ~(3 << shift);
-        pup |= pull << shift;
-        __raw_writel(pup, reg);
-
-        return 0;
-}
-
-s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
-                                        unsigned int off)
-{
-        void __iomem *reg = chip->base + 0x08;
-        int shift = off * 2;
-        u32 pup = __raw_readl(reg);
-
-        pup >>= shift;
-        pup &= 0x3;
-        return (__force s3c_gpio_pull_t)pup;
-}
-
-#ifdef CONFIG_S3C_GPIO_PULL_S3C2443
-int s3c_gpio_setpull_s3c2443(struct s3c_gpio_chip *chip,
-                                unsigned int off, s3c_gpio_pull_t pull)
-{
-        switch (pull) {
-        case S3C_GPIO_PULL_NONE:
-                pull = 0x01;
-                break;
-        case S3C_GPIO_PULL_UP:
-                pull = 0x00;
-                break;
-        case S3C_GPIO_PULL_DOWN:
-                pull = 0x02;
-                break;
-        }
-        return s3c_gpio_setpull_updown(chip, off, pull);
-}
-
-s3c_gpio_pull_t s3c_gpio_getpull_s3c2443(struct s3c_gpio_chip *chip,
-                                        unsigned int off)
-{
-        s3c_gpio_pull_t pull;
-
-        pull = s3c_gpio_getpull_updown(chip, off);
-
-        switch (pull) {
-        case 0x00:
-                pull = S3C_GPIO_PULL_UP;
-                break;
-        case 0x01:
-        case 0x03:
-                pull = S3C_GPIO_PULL_NONE;
-                break;
-        case 0x02:
-                pull = S3C_GPIO_PULL_DOWN;
-                break;
-        }
-
-        return pull;
-}
-#endif
-#endif
-
-#if defined(CONFIG_S3C_GPIO_PULL_UP) || defined(CONFIG_S3C_GPIO_PULL_DOWN)
-static int s3c_gpio_setpull_1(struct s3c_gpio_chip *chip,
-                         unsigned int off, s3c_gpio_pull_t pull,
-                         s3c_gpio_pull_t updown)
-{
-        void __iomem *reg = chip->base + 0x08;
-        u32 pup = __raw_readl(reg);
-
-        if (pull == updown)
-                pup &= ~(1 << off);
-        else if (pull == S3C_GPIO_PULL_NONE)
-                pup |= (1 << off);
-        else
-                return -EINVAL;
-
-        __raw_writel(pup, reg);
-        return 0;
-}
-
-static s3c_gpio_pull_t s3c_gpio_getpull_1(struct s3c_gpio_chip *chip,
-                                     unsigned int off, s3c_gpio_pull_t updown)
-{
-        void __iomem *reg = chip->base + 0x08;
-        u32 pup = __raw_readl(reg);
-
-        pup &= (1 << off);
-        return pup ? S3C_GPIO_PULL_NONE : updown;
-}
-#endif /* CONFIG_S3C_GPIO_PULL_UP || CONFIG_S3C_GPIO_PULL_DOWN */
-
-#ifdef CONFIG_S3C_GPIO_PULL_UP
-s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip,
-                                     unsigned int off)
-{
-        return s3c_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP);
-}
-
-int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,
-                         unsigned int off, s3c_gpio_pull_t pull)
-{
-        return s3c_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP);
-}
-#endif /* CONFIG_S3C_GPIO_PULL_UP */
-
-#ifdef CONFIG_S3C_GPIO_PULL_DOWN
-s3c_gpio_pull_t s3c_gpio_getpull_1down(struct s3c_gpio_chip *chip,
-                                     unsigned int off)
-{
-        return s3c_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN);
-}
-
-int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip,
-                         unsigned int off, s3c_gpio_pull_t pull)
-{
-        return s3c_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
-}
-#endif /* CONFIG_S3C_GPIO_PULL_DOWN */
-
-#ifdef CONFIG_S5P_GPIO_DRVSTR
-s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
-{
-        struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
-        unsigned int off;
-        void __iomem *reg;
-        int shift;
-        u32 drvstr;
-
-        if (!chip)
-                return -EINVAL;
-
-        off = pin - chip->chip.base;
-        shift = off * 2;
-        reg = chip->base + 0x0C;
-
-        drvstr = __raw_readl(reg);
-        drvstr = drvstr >> shift;
-        drvstr &= 0x3;
-
-        return (__force s5p_gpio_drvstr_t)drvstr;
-}
-EXPORT_SYMBOL(s5p_gpio_get_drvstr);
-
-int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
-{
-        struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
-        unsigned int off;
-        void __iomem *reg;
-        int shift;
-        u32 tmp;
-
-        if (!chip)
-                return -EINVAL;
-
-        off = pin - chip->chip.base;
-        shift = off * 2;
-        reg = chip->base + 0x0C;
-
-        tmp = __raw_readl(reg);
-        tmp &= ~(0x3 << shift);
-        tmp |= drvstr << shift;
-
-        __raw_writel(tmp, reg);
-
-        return 0;
-}
-EXPORT_SYMBOL(s5p_gpio_set_drvstr);
-#endif  /* CONFIG_S5P_GPIO_DRVSTR */
diff --git a/arch/arm/plat-samsung/gpio.c b/arch/arm/plat-samsung/gpio.c
deleted file mode 100644
index 7743c4b8b2fb..000000000000
--- a/arch/arm/plat-samsung/gpio.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/* linux/arch/arm/plat-s3c/gpio.c
- *
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S3C series GPIO core
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/spinlock.h>
-
-#include <plat/gpio-core.h>
-
-#ifdef CONFIG_S3C_GPIO_TRACK
-struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
-
-static __init void s3c_gpiolib_track(struct s3c_gpio_chip *chip)
-{
-        unsigned int gpn;
-        int i;
-
-        gpn = chip->chip.base;
-        for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
-                BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios));
-                s3c_gpios[gpn] = chip;
-        }
-}
-#endif /* CONFIG_S3C_GPIO_TRACK */
-
-/* Default routines for controlling GPIO, based on the original S3C24XX
- * GPIO functions which deal with the case where each gpio bank of the
- * chip is as following:
- *
- * base + 0x00: Control register, 2 bits per gpio
- *              gpio n: 2 bits starting at (2*n)
- *              00 = input, 01 = output, others mean special-function
- * base + 0x04: Data register, 1 bit per gpio
- *              bit n: data bit n
-*/
-
-static int s3c_gpiolib_input(struct gpio_chip *chip, unsigned offset)
-{
-        struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
-        void __iomem *base = ourchip->base;
-        unsigned long flags;
-        unsigned long con;
-
-        s3c_gpio_lock(ourchip, flags);
-
-        con = __raw_readl(base + 0x00);
-        con &= ~(3 << (offset * 2));
-
-        __raw_writel(con, base + 0x00);
-
-        s3c_gpio_unlock(ourchip, flags);
-        return 0;
-}
-
-static int s3c_gpiolib_output(struct gpio_chip *chip,
-                              unsigned offset, int value)
-{
-        struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
-        void __iomem *base = ourchip->base;
-        unsigned long flags;
-        unsigned long dat;
-        unsigned long con;
-
-        s3c_gpio_lock(ourchip, flags);
-
-        dat = __raw_readl(base + 0x04);
-        dat &= ~(1 << offset);
-        if (value)
-                dat |= 1 << offset;
-        __raw_writel(dat, base + 0x04);
-
-        con = __raw_readl(base + 0x00);
-        con &= ~(3 << (offset * 2));
-        con |= 1 << (offset * 2);
-
-        __raw_writel(con, base + 0x00);
-        __raw_writel(dat, base + 0x04);
-
-        s3c_gpio_unlock(ourchip, flags);
-        return 0;
-}
-
-static void s3c_gpiolib_set(struct gpio_chip *chip,
-                            unsigned offset, int value)
-{
-        struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
-        void __iomem *base = ourchip->base;
-        unsigned long flags;
-        unsigned long dat;
-
-        s3c_gpio_lock(ourchip, flags);
-
-        dat = __raw_readl(base + 0x04);
-        dat &= ~(1 << offset);
-        if (value)
-                dat |= 1 << offset;
-        __raw_writel(dat, base + 0x04);
-
-        s3c_gpio_unlock(ourchip, flags);
-}
-
-static int s3c_gpiolib_get(struct gpio_chip *chip, unsigned offset)
-{
-        struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
-        unsigned long val;
-
-        val = __raw_readl(ourchip->base + 0x04);
-        val >>= offset;
-        val &= 1;
-
-        return val;
-}
-
-__init void s3c_gpiolib_add(struct s3c_gpio_chip *chip)
-{
-        struct gpio_chip *gc = &chip->chip;
-        int ret;
-
-        BUG_ON(!chip->base);
-        BUG_ON(!gc->label);
-        BUG_ON(!gc->ngpio);
-
-        spin_lock_init(&chip->lock);
-
-        if (!gc->direction_input)
-                gc->direction_input = s3c_gpiolib_input;
-        if (!gc->direction_output)
-                gc->direction_output = s3c_gpiolib_output;
-        if (!gc->set)
-                gc->set = s3c_gpiolib_set;
-        if (!gc->get)
-                gc->get = s3c_gpiolib_get;
-
-#ifdef CONFIG_PM
-        if (chip->pm != NULL) {
-                if (!chip->pm->save || !chip->pm->resume)
-                        printk(KERN_ERR "gpio: %s has missing PM functions\n",
-                               gc->label);
-        } else
-                printk(KERN_ERR "gpio: %s has no PM function\n", gc->label);
-#endif
-
-        /* gpiochip_add() prints own failure message on error. */
-        ret = gpiochip_add(gc);
-        if (ret >= 0)
-                s3c_gpiolib_track(chip);
-}
-
-int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
-{
-        struct s3c_gpio_chip *s3c_chip = container_of(chip,
-                        struct s3c_gpio_chip, chip);
-
-        return s3c_chip->irq_base + offset;
-}
diff --git a/arch/arm/plat-s3c24xx/include/plat/audio-simtec.h b/arch/arm/plat-samsung/include/plat/audio-simtec.h
index de5e88fdcb31..5345364e7420 100644
--- a/arch/arm/plat-s3c24xx/include/plat/audio-simtec.h
+++ b/arch/arm/plat-samsung/include/plat/audio-simtec.h
@@ -1,4 +1,4 @@
-/* arch/arm/plat-s3c24xx/include/plat/audio-simtec.h
+/* arch/arm/plat-samsung/include/plat/audio-simtec.h
  *
  * Copyright 2008 Simtec Electronics
  *      http://armlinux.simtec.co.uk/
diff --git a/arch/arm/plat-s5p/include/plat/camport.h b/arch/arm/plat-samsung/include/plat/camport.h
index 71688c8ba288..a5708bf84b3a 100644
--- a/arch/arm/plat-s5p/include/plat/camport.h
+++ b/arch/arm/plat-samsung/include/plat/camport.h
@@ -8,8 +8,8 @@
  * published by the Free Software Foundation.
  */
 
-#ifndef PLAT_S5P_CAMPORT_H_
-#define PLAT_S5P_CAMPORT_H_ __FILE__
+#ifndef __PLAT_SAMSUNG_CAMPORT_H_
+#define __PLAT_SAMSUNG_CAMPORT_H_ __FILE__
 
 enum s5p_camport_id {
         S5P_CAMPORT_A,
@@ -25,4 +25,4 @@ enum s5p_camport_id {
 int s5pv210_fimc_setup_gpio(enum s5p_camport_id id);
 int exynos4_fimc_setup_gpio(enum s5p_camport_id id);
 
-#endif
+#endif /* __PLAT_SAMSUNG_CAMPORT_H */
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
index 87d5b38a86fb..73c66d4d10fa 100644
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -9,6 +9,9 @@
  * published by the Free Software Foundation.
 */
 
+#ifndef __ASM_PLAT_CLOCK_H
+#define __ASM_PLAT_CLOCK_H __FILE__
+
 #include <linux/spinlock.h>
 #include <linux/clkdev.h>
 
@@ -121,3 +124,8 @@ extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable);
 
 extern void s3c_pwmclk_init(void);
 
+/* Global watchdog clock used by arch_wtd_reset() callback */
+
+extern struct clk *s3c2410_wdtclk;
+
+#endif /* __ASM_PLAT_CLOCK_H */
diff --git a/arch/arm/plat-s3c24xx/include/plat/common-smdk.h b/arch/arm/plat-samsung/include/plat/common-smdk.h
index 58d9094c935c..ba028f1ed30b 100644
--- a/arch/arm/plat-s3c24xx/include/plat/common-smdk.h
+++ b/arch/arm/plat-samsung/include/plat/common-smdk.h
@@ -1,4 +1,4 @@
-/* linux/include/asm-arm/plat-s3c24xx/common-smdk.h
+/* linux/arch/arm/plat-samsung/include/plat/common-smdk.h
  *
  * Copyright (c) 2006 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
diff --git a/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
index d623235ae961..dac4760c0f0a 100644
--- a/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h
+++ b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
@@ -1,4 +1,4 @@
-/* arch/arm/plat-s3c/include/plat/cpu-freq.h
+/* arch/arm/plat-samsung/include/plat/cpu-freq-core.h
  *
  * Copyright (c) 2006-2009 Simtec Electronics
  *      http://armlinux.simtec.co.uk/
@@ -195,7 +195,8 @@ struct s3c_cpufreq_info {
 
 extern int s3c_cpufreq_register(struct s3c_cpufreq_info *info);
 
-extern int s3c_plltab_register(struct cpufreq_frequency_table *plls, unsigned int plls_no);
+extern int s3c_plltab_register(struct cpufreq_frequency_table *plls,
+                               unsigned int plls_no);
 
 /* exports and utilities for debugfs */
 extern struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void);
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index c0a5741b23e6..54f370f0fc07 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -1,9 +1,12 @@
 /* linux/arch/arm/plat-samsung/include/plat/cpu.h
  *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
  * Copyright (c) 2004-2005 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
  *
- * Header file for S3C24XX CPU support
+ * Header file for Samsung CPU support
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -15,6 +18,108 @@
 #ifndef __SAMSUNG_PLAT_CPU_H
 #define __SAMSUNG_PLAT_CPU_H
 
+extern unsigned long samsung_cpu_id;
+
+#define S3C24XX_CPU_ID          0x32400000
+#define S3C24XX_CPU_MASK        0xFFF00000
+
+#define S3C6400_CPU_ID          0x36400000
+#define S3C6410_CPU_ID          0x36410000
+#define S3C64XX_CPU_ID          (S3C6400_CPU_ID & S3C6410_CPU_ID)
+#define S3C64XX_CPU_MASK        0xFFFFF000
+
+#define S5P6440_CPU_ID          0x56440000
+#define S5P6450_CPU_ID          0x36450000
+#define S5P64XX_CPU_MASK        0xFFFFF000
+
+#define S5PC100_CPU_ID          0x43100000
+#define S5PC100_CPU_MASK        0xFFFFF000
+
+#define S5PV210_CPU_ID          0x43110000
+#define S5PV210_CPU_MASK        0xFFFFF000
+
+#define EXYNOS4210_CPU_ID       0x43210000
+#define EXYNOS4212_CPU_ID       0x43220000
+#define EXYNOS4412_CPU_ID       0xE4412200
+#define EXYNOS4_CPU_MASK        0xFFFE0000
+
+#define IS_SAMSUNG_CPU(name, id, mask)          \
+static inline int is_samsung_##name(void)       \
+{                                               \
+        return ((samsung_cpu_id & mask) == (id & mask));        \
+}
+
+IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK)
+IS_SAMSUNG_CPU(s3c64xx, S3C64XX_CPU_ID, S3C64XX_CPU_MASK)
+IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK)
+IS_SAMSUNG_CPU(s5p6450, S5P6450_CPU_ID, S5P64XX_CPU_MASK)
+IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK)
+IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
+IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
+IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
+IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
+
+#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
+    defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
+    defined(CONFIG_CPU_S3C2442) || defined(CONFIG_CPU_S3C244X) || \
+    defined(CONFIG_CPU_S3C2443)
+# define soc_is_s3c24xx()       is_samsung_s3c24xx()
+#else
+# define soc_is_s3c24xx()       0
+#endif
+
+#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
+# define soc_is_s3c64xx()       is_samsung_s3c64xx()
+#else
+# define soc_is_s3c64xx()       0
+#endif
+
+#if defined(CONFIG_CPU_S5P6440)
+# define soc_is_s5p6440()       is_samsung_s5p6440()
+#else
+# define soc_is_s5p6440()       0
+#endif
+
+#if defined(CONFIG_CPU_S5P6450)
+# define soc_is_s5p6450()       is_samsung_s5p6450()
+#else
+# define soc_is_s5p6450()       0
+#endif
+
+#if defined(CONFIG_CPU_S5PC100)
+# define soc_is_s5pc100()       is_samsung_s5pc100()
+#else
+# define soc_is_s5pc100()       0
+#endif
+
+#if defined(CONFIG_CPU_S5PV210)
+# define soc_is_s5pv210()       is_samsung_s5pv210()
+#else
+# define soc_is_s5pv210()       0
+#endif
+
+#if defined(CONFIG_CPU_EXYNOS4210)
+# define soc_is_exynos4210()    is_samsung_exynos4210()
+#else
+# define soc_is_exynos4210()    0
+#endif
+
+#if defined(CONFIG_SOC_EXYNOS4212)
+# define soc_is_exynos4212()    is_samsung_exynos4212()
+#else
+# define soc_is_exynos4212()    0
+#endif
+
+#if defined(CONFIG_SOC_EXYNOS4412)
+# define soc_is_exynos4412()    is_samsung_exynos4412()
+#else
+# define soc_is_exynos4412()    0
+#endif
+
+#define EXYNOS4210_REV_0        (0x0)
+#define EXYNOS4210_REV_1_0      (0x10)
+#define EXYNOS4210_REV_1_1      (0x11)
+
 #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
 
 #ifndef MHZ
@@ -55,6 +160,12 @@ extern void s3c64xx_init_io(struct map_desc *mach_desc, int size);
 extern void s5p_init_io(struct map_desc *mach_desc,
                         int size, void __iomem *cpuid_addr);
 
+extern void s3c24xx_init_cpu(void);
+extern void s3c64xx_init_cpu(void);
+extern void s5p_init_cpu(void __iomem *cpuid_addr);
+
+extern unsigned int samsung_rev(void);
+
 extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 
 extern void s3c24xx_init_clocks(int xtal);
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 24ebb1e1de41..ee5014a7cc96 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -62,6 +62,7 @@ extern struct platform_device s3c_device_i2c4;
 extern struct platform_device s3c_device_i2c5;
 extern struct platform_device s3c_device_i2c6;
 extern struct platform_device s3c_device_i2c7;
+extern struct platform_device s5p_device_i2c_hdmiphy;
 extern struct platform_device s3c_device_rtc;
 extern struct platform_device s3c_device_adc;
 extern struct platform_device s3c_device_sdi;
@@ -142,6 +143,11 @@ extern struct platform_device s5p_device_fimc3;
 extern struct platform_device s5p_device_mfc;
 extern struct platform_device s5p_device_mfc_l;
 extern struct platform_device s5p_device_mfc_r;
+
+extern struct platform_device s5p_device_hdmi;
+extern struct platform_device s5p_device_mixer;
+extern struct platform_device s5p_device_sdo;
+
 extern struct platform_device s5p_device_mipi_csis0;
 extern struct platform_device s5p_device_mipi_csis1;
 
diff --git a/arch/arm/plat-samsung/include/plat/dma-ops.h b/arch/arm/plat-samsung/include/plat/dma-ops.h
new file mode 100644
index 000000000000..4c1a363526cf
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/dma-ops.h
@@ -0,0 +1,63 @@
+/* arch/arm/plat-samsung/include/plat/dma-ops.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Samsung DMA support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __SAMSUNG_DMA_OPS_H_
+#define __SAMSUNG_DMA_OPS_H_ __FILE__
+
+#include <linux/dmaengine.h>
+
+struct samsung_dma_prep_info {
+        enum dma_transaction_type cap;
+        enum dma_data_direction direction;
+        dma_addr_t buf;
+        unsigned long period;
+        unsigned long len;
+        void (*fp)(void *data);
+        void *fp_param;
+};
+
+struct samsung_dma_info {
+        enum dma_transaction_type cap;
+        enum dma_data_direction direction;
+        enum dma_slave_buswidth width;
+        dma_addr_t fifo;
+        struct s3c2410_dma_client *client;
+};
+
+struct samsung_dma_ops {
+        unsigned (*request)(enum dma_ch ch, struct samsung_dma_info *info);
+        int (*release)(unsigned ch, struct s3c2410_dma_client *client);
+        int (*prepare)(unsigned ch, struct samsung_dma_prep_info *info);
+        int (*trigger)(unsigned ch);
+        int (*started)(unsigned ch);
+        int (*flush)(unsigned ch);
+        int (*stop)(unsigned ch);
+};
+
+extern void *samsung_dmadev_get_ops(void);
+extern void *s3c_dma_get_ops(void);
+
+static inline void *__samsung_dma_get_ops(void)
+{
+        if (samsung_dma_is_dmadev())
+                return samsung_dmadev_get_ops();
+        else
+                return s3c_dma_get_ops();
+}
+
+/*
+ * samsung_dma_get_ops
+ * get the set of samsung dma operations
+ */
+#define samsung_dma_get_ops() __samsung_dma_get_ops()
+
+#endif /* __SAMSUNG_DMA_OPS_H_ */
diff --git a/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h b/arch/arm/plat-samsung/include/plat/dma-pl330.h
index 810744213120..2e55e5958674 100644
--- a/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h
+++ b/arch/arm/plat-samsung/include/plat/dma-pl330.h
@@ -8,11 +8,8 @@
  * (at your option) any later version.
  */
 
-#ifndef __S3C_DMA_PL330_H_
-#define __S3C_DMA_PL330_H_
-
-#define S3C2410_DMAF_AUTOSTART          (1 << 0)
-#define S3C2410_DMAF_CIRCULAR           (1 << 1)
+#ifndef __DMA_PL330_H_
+#define __DMA_PL330_H_ __FILE__
 
 /*
  * PL330 can assign any channel to communicate with
@@ -20,7 +17,7 @@
  * For the sake of consistency across client drivers,
  * We keep the channel names unchanged and only add
  * missing peripherals are added.
- * Order is not important since S3C PL330 API driver
+ * Order is not important since DMA PL330 API driver
  * use these just as IDs.
  */
 enum dma_ch {
@@ -88,11 +85,20 @@ enum dma_ch {
         DMACH_MAX,
 };
 
-static inline bool s3c_dma_has_circular(void)
+struct s3c2410_dma_client {
+        char    *name;
+};
+
+static inline bool samsung_dma_has_circular(void)
+{
+        return true;
+}
+
+static inline bool samsung_dma_is_dmadev(void)
 {
         return true;
 }
 
-#include <plat/dma.h>
+#include <plat/dma-ops.h>
 
-#endif  /* __S3C_DMA_PL330_H_ */
+#endif  /* __DMA_PL330_H_ */
diff --git a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
index 336d5ac02035..1c1ed5481253 100644
--- a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
+++ b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
@@ -18,11 +18,6 @@ extern struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
 #define DMA_CH_VALID            (1<<31)
 #define DMA_CH_NEVER            (1<<30)
 
-struct s3c24xx_dma_addr {
-        unsigned long           from;
-        unsigned long           to;
-};
-
 /* struct s3c24xx_dma_map
  *
  * this holds the mapping information for the channel selected
@@ -31,7 +26,6 @@ struct s3c24xx_dma_addr {
 
 struct s3c24xx_dma_map {
         const char              *name;
-        struct s3c24xx_dma_addr  hw_addr;
 
         unsigned long            channels[S3C_DMA_CHANNELS];
         unsigned long            channels_rx[S3C_DMA_CHANNELS];
@@ -47,7 +41,7 @@ struct s3c24xx_dma_selection {
 
         void    (*direction)(struct s3c2410_dma_chan *chan,
                              struct s3c24xx_dma_map *map,
-                             enum s3c2410_dmasrc dir);
+                             enum dma_data_direction dir);
 };
 
 extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
diff --git a/arch/arm/plat-samsung/include/plat/dma.h b/arch/arm/plat-samsung/include/plat/dma.h
index 8c273b7a6f56..b9061128abde 100644
--- a/arch/arm/plat-samsung/include/plat/dma.h
+++ b/arch/arm/plat-samsung/include/plat/dma.h
@@ -10,17 +10,14 @@
  * published by the Free Software Foundation.
 */
 
+#include <linux/dma-mapping.h>
+
 enum s3c2410_dma_buffresult {
         S3C2410_RES_OK,
         S3C2410_RES_ERR,
         S3C2410_RES_ABORT
 };
 
-enum s3c2410_dmasrc {
-        S3C2410_DMASRC_HW,              /* source is memory */
-        S3C2410_DMASRC_MEM              /* source is hardware */
-};
-
 /* enum s3c2410_chan_op
  *
  * operation codes passed to the DMA code by the user, and also used
@@ -112,7 +109,7 @@ extern int s3c2410_dma_config(enum dma_ch channel, int xferunit);
 */
 
 extern int s3c2410_dma_devconfig(enum dma_ch channel,
-                enum s3c2410_dmasrc source, unsigned long devaddr);
+                enum dma_data_direction source, unsigned long devaddr);
 
 /* s3c2410_dma_getposition
  *
@@ -126,3 +123,4 @@ extern int s3c2410_dma_set_opfn(enum dma_ch, s3c2410_dma_opfn_t rtn);
 extern int s3c2410_dma_set_buffdone_fn(enum dma_ch, s3c2410_dma_cbfn_t rtn);
 
 
+#include <plat/dma-ops.h>
diff --git a/arch/arm/plat-s5p/include/plat/ehci.h b/arch/arm/plat-samsung/include/plat/ehci.h
index 6ae6810c7569..5f28cae18582 100644
--- a/arch/arm/plat-s5p/include/plat/ehci.h
+++ b/arch/arm/plat-samsung/include/plat/ehci.h
@@ -8,8 +8,8 @@
  * option) any later version.
  */
 
-#ifndef __PLAT_S5P_EHCI_H
-#define __PLAT_S5P_EHCI_H
+#ifndef __PLAT_SAMSUNG_EHCI_H
+#define __PLAT_SAMSUNG_EHCI_H __FILE__
 
 struct s5p_ehci_platdata {
         int (*phy_init)(struct platform_device *pdev, int type);
@@ -18,4 +18,4 @@ struct s5p_ehci_platdata {
 
 extern void s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd);
 
-#endif /* __PLAT_S5P_EHCI_H */
+#endif /* __PLAT_SAMSUNG_EHCI_H */
diff --git a/arch/arm/plat-s5p/include/plat/exynos4.h b/arch/arm/plat-samsung/include/plat/exynos4.h
index 907caab53dcf..20d73bf77537 100644
--- a/arch/arm/plat-s5p/include/plat/exynos4.h
+++ b/arch/arm/plat-samsung/include/plat/exynos4.h
@@ -1,4 +1,4 @@
-/* linux/arch/arm/plat-s5p/include/plat/exynos4.h
+/* linux/arch/arm/plat-samsung/include/plat/exynos4.h
  *
  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
@@ -14,10 +14,11 @@
 
 extern void exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 extern void exynos4_register_clocks(void);
+extern void exynos4210_register_clocks(void);
+extern void exynos4212_register_clocks(void);
 extern void exynos4_setup_clocks(void);
 
-#ifdef CONFIG_CPU_EXYNOS4210
-
+#ifdef CONFIG_ARCH_EXYNOS4
 extern  int exynos4_init(void);
 extern void exynos4_init_irq(void);
 extern void exynos4_map_io(void);
diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h
index 01f10e4d00c7..0fedf47fa502 100644
--- a/arch/arm/plat-samsung/include/plat/fb.h
+++ b/arch/arm/plat-samsung/include/plat/fb.h
@@ -109,4 +109,11 @@ extern void s5pv210_fb_gpio_setup_24bpp(void);
  */
 extern void exynos4_fimd0_gpio_setup_24bpp(void);
 
+/**
+ * s5p64x0_fb_gpio_setup_24bpp() - S5P6440/S5P6450 setup function for 24bpp LCD
+ *
+ * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
+ */
+extern void s5p64x0_fb_gpio_setup_24bpp(void);
+
 #endif /* __PLAT_S3C_FB_H */
diff --git a/arch/arm/plat-s3c24xx/include/plat/fiq.h b/arch/arm/plat-samsung/include/plat/fiq.h
index 8521b8372c5f..535d06a35628 100644
--- a/arch/arm/plat-s3c24xx/include/plat/fiq.h
+++ b/arch/arm/plat-samsung/include/plat/fiq.h
@@ -1,4 +1,4 @@
-/* linux/include/asm-arm/plat-s3c24xx/fiq.h
+/* linux/arch/arm/plat-samsung/include/plat/fiq.h
  *
  * Copyright (c) 2009 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
index 9a4e53d52967..a181d7ce81cf 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
@@ -1,11 +1,11 @@
-/* linux/arch/arm/plat-s3c/include/plat/gpio-cfg-helper.h
+/* linux/arch/arm/plat-samsung/include/plat/gpio-cfg-helper.h
  *
  * Copyright 2008 Openmoko, Inc.
  * Copyright 2008 Simtec Electronics
  *      http://armlinux.simtec.co.uk/
  *      Ben Dooks <ben@simtec.co.uk>
  *
- * S3C Platform - GPIO pin configuration helper definitions
+ * Samsung Platform - GPIO pin configuration helper definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -24,120 +24,30 @@
  * by disabling interrupts.
 */
 
-static inline int s3c_gpio_do_setcfg(struct s3c_gpio_chip *chip,
-                                     unsigned int off, unsigned int config)
+static inline int samsung_gpio_do_setcfg(struct samsung_gpio_chip *chip,
+                                         unsigned int off, unsigned int config)
 {
         return (chip->config->set_config)(chip, off, config);
 }
 
-static inline unsigned s3c_gpio_do_getcfg(struct s3c_gpio_chip *chip,
-                                          unsigned int off)
+static inline unsigned samsung_gpio_do_getcfg(struct samsung_gpio_chip *chip,
+                                              unsigned int off)
 {
         return (chip->config->get_config)(chip, off);
 }
 
-static inline int s3c_gpio_do_setpull(struct s3c_gpio_chip *chip,
-                                      unsigned int off, s3c_gpio_pull_t pull)
+static inline int samsung_gpio_do_setpull(struct samsung_gpio_chip *chip,
+                                          unsigned int off, samsung_gpio_pull_t pull)
 {
         return (chip->config->set_pull)(chip, off, pull);
 }
 
-static inline s3c_gpio_pull_t s3c_gpio_do_getpull(struct s3c_gpio_chip *chip,
-                                                  unsigned int off)
+static inline samsung_gpio_pull_t samsung_gpio_do_getpull(struct samsung_gpio_chip *chip,
+                                                          unsigned int off)
 {
         return chip->config->get_pull(chip, off);
 }
 
-/**
- * s3c_gpio_setcfg_s3c24xx - S3C24XX style GPIO configuration.
- * @chip: The gpio chip that is being configured.
- * @off: The offset for the GPIO being configured.
- * @cfg: The configuration value to set.
- *
- * This helper deal with the GPIO cases where the control register
- * has two bits of configuration per gpio, which have the following
- * functions:
- *      00 = input
- *      01 = output
- *      1x = special function
-*/
-extern int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
-                                   unsigned int off, unsigned int cfg);
-
-/**
- * s3c_gpio_getcfg_s3c24xx - S3C24XX style GPIO configuration read.
- * @chip: The gpio chip that is being configured.
- * @off: The offset for the GPIO being configured.
- *
- * The reverse of s3c_gpio_setcfg_s3c24xx(). Will return a value whicg
- * could be directly passed back to s3c_gpio_setcfg_s3c24xx(), from the
- * S3C_GPIO_SPECIAL() macro.
- */
-unsigned int s3c_gpio_getcfg_s3c24xx(struct s3c_gpio_chip *chip,
-                                     unsigned int off);
-
-/**
- * s3c_gpio_setcfg_s3c24xx_a - S3C24XX style GPIO configuration (Bank A)
- * @chip: The gpio chip that is being configured.
- * @off: The offset for the GPIO being configured.
- * @cfg: The configuration value to set.
- *
- * This helper deal with the GPIO cases where the control register
- * has one bit of configuration for the gpio, where setting the bit
- * means the pin is in special function mode and unset means output.
-*/
-extern int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
-                                     unsigned int off, unsigned int cfg);
-
-
-/**
- * s3c_gpio_getcfg_s3c24xx_a - S3C24XX style GPIO configuration read (Bank A)
- * @chip: The gpio chip that is being configured.
- * @off: The offset for the GPIO being configured.
- *
- * The reverse of s3c_gpio_setcfg_s3c24xx_a() turning an GPIO into a usable
- * GPIO configuration value.
- *
- * @sa s3c_gpio_getcfg_s3c24xx
- * @sa s3c_gpio_getcfg_s3c64xx_4bit
- */
-extern unsigned s3c_gpio_getcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
-                                          unsigned int off);
-
-/**
- * s3c_gpio_setcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config.
- * @chip: The gpio chip that is being configured.
- * @off: The offset for the GPIO being configured.
- * @cfg: The configuration value to set.
- *
- * This helper deal with the GPIO cases where the control register has 4 bits
- * of control per GPIO, generally in the form of:
- *      0000 = Input
- *      0001 = Output
- *      others = Special functions (dependent on bank)
- *
- * Note, since the code to deal with the case where there are two control
- * registers instead of one, we do not have a separate set of functions for
- * each case.
-*/
-extern int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
-                                        unsigned int off, unsigned int cfg);
-
-
-/**
- * s3c_gpio_getcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config read.
- * @chip: The gpio chip that is being configured.
- * @off: The offset for the GPIO being configured.
- *
- * The reverse of s3c_gpio_setcfg_s3c64xx_4bit(), turning a gpio configuration
- * register setting into a value the software can use, such as could be passed
- * to s3c_gpio_setcfg_s3c64xx_4bit().
- *
- * @sa s3c_gpio_getcfg_s3c24xx
- */
-extern unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
-                                             unsigned int off);
-
 /* Pull-{up,down} resistor controls.
  *
  * S3C2410,S3C2440 = Pull-UP,
@@ -147,7 +57,7 @@ extern unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
  */
 
 /**
- * s3c_gpio_setpull_1up() - Pull configuration for choice of up or none.
+ * s3c24xx_gpio_setpull_1up() - Pull configuration for choice of up or none.
  * @chip: The gpio chip that is being configured.
  * @off: The offset for the GPIO being configured.
  * @param: pull: The pull mode being requested.
@@ -155,11 +65,11 @@ extern unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
  * This is a helper function for the case where we have GPIOs with one
  * bit configuring the presence of a pull-up resistor.
  */
-extern int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,
-                                unsigned int off, s3c_gpio_pull_t pull);
+extern int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip,
+                                    unsigned int off, samsung_gpio_pull_t pull);
 
 /**
- * s3c_gpio_setpull_1down() - Pull configuration for choice of down or none
+ * s3c24xx_gpio_setpull_1down() - Pull configuration for choice of down or none
  * @chip: The gpio chip that is being configured
  * @off: The offset for the GPIO being configured
  * @param: pull: The pull mode being requested
@@ -167,11 +77,13 @@ extern int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,
  * This is a helper function for the case where we have GPIOs with one
  * bit configuring the presence of a pull-down resistor.
  */
-extern int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip,
-                                  unsigned int off, s3c_gpio_pull_t pull);
+extern int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip,
+                                      unsigned int off, samsung_gpio_pull_t pull);
 
 /**
- * s3c_gpio_setpull_upown() - Pull configuration for choice of up, down or none
+ * samsung_gpio_setpull_upown() - Pull configuration for choice of up,
+ * down or none
+ *
  * @chip: The gpio chip that is being configured.
  * @off: The offset for the GPIO being configured.
  * @param: pull: The pull mode being requested.
@@ -183,45 +95,46 @@ extern int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip,
  *      01 = Pull-up resistor connected
  *      10 = Pull-down resistor connected
  */
-extern int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip,
-                                   unsigned int off, s3c_gpio_pull_t pull);
-
+extern int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
+                                       unsigned int off, samsung_gpio_pull_t pull);
 
 /**
- * s3c_gpio_getpull_updown() - Get configuration for choice of up, down or none
+ * samsung_gpio_getpull_updown() - Get configuration for choice of up,
+ * down or none
+ *
  * @chip: The gpio chip that the GPIO pin belongs to
  * @off: The offset to the pin to get the configuration of.
  *
- * This helper function reads the state of the pull-{up,down} resistor for the
- * given GPIO in the same case as s3c_gpio_setpull_upown.
+ * This helper function reads the state of the pull-{up,down} resistor
+ * for the given GPIO in the same case as samsung_gpio_setpull_upown.
 */
-extern s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
-                                               unsigned int off);
+extern samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
+                                                       unsigned int off);
 
 /**
- * s3c_gpio_getpull_1up() - Get configuration for choice of up or none
+ * s3c24xx_gpio_getpull_1up() - Get configuration for choice of up or none
  * @chip: The gpio chip that the GPIO pin belongs to
  * @off: The offset to the pin to get the configuration of.
  *
  * This helper function reads the state of the pull-up resistor for the
- * given GPIO in the same case as s3c_gpio_setpull_1up.
+ * given GPIO in the same case as s3c24xx_gpio_setpull_1up.
 */
-extern s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip,
-                                            unsigned int off);
+extern samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip,
+                                                    unsigned int off);
 
 /**
- * s3c_gpio_getpull_1down() - Get configuration for choice of down or none
+ * s3c24xx_gpio_getpull_1down() - Get configuration for choice of down or none
  * @chip: The gpio chip that the GPIO pin belongs to
  * @off: The offset to the pin to get the configuration of.
  *
  * This helper function reads the state of the pull-down resistor for the
- * given GPIO in the same case as s3c_gpio_setpull_1down.
+ * given GPIO in the same case as s3c24xx_gpio_setpull_1down.
 */
-extern s3c_gpio_pull_t s3c_gpio_getpull_1down(struct s3c_gpio_chip *chip,
-                                            unsigned int off);
+extern samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip,
+                                                      unsigned int off);
 
 /**
- * s3c_gpio_setpull_s3c2443() - Pull configuration for s3c2443.
+ * s3c2443_gpio_setpull() - Pull configuration for s3c2443.
  * @chip: The gpio chip that is being configured.
  * @off: The offset for the GPIO being configured.
  * @param: pull: The pull mode being requested.
@@ -233,19 +146,18 @@ extern s3c_gpio_pull_t s3c_gpio_getpull_1down(struct s3c_gpio_chip *chip,
  *      10 = Pull-down resistor connected
  *      x1 = No pull up resistor
  */
-extern int s3c_gpio_setpull_s3c2443(struct s3c_gpio_chip *chip,
-                                    unsigned int off, s3c_gpio_pull_t pull);
+extern int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip,
+                                unsigned int off, samsung_gpio_pull_t pull);
 
 /**
- * s3c_gpio_getpull_s3c2443() - Get configuration for s3c2443 pull resistors
+ * s3c2443_gpio_getpull() - Get configuration for s3c2443 pull resistors
  * @chip: The gpio chip that the GPIO pin belongs to.
  * @off: The offset to the pin to get the configuration of.
  *
  * This helper function reads the state of the pull-{up,down} resistor for the
- * given GPIO in the same case as s3c_gpio_setpull_upown.
+ * given GPIO in the same case as samsung_gpio_setpull_upown.
 */
-extern s3c_gpio_pull_t s3c_gpio_getpull_s3c2443(struct s3c_gpio_chip *chip,
+extern samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip,
                                                 unsigned int off);
 
 #endif /* __PLAT_GPIO_CFG_HELPERS_H */
-
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
index 1762dcb4cb9e..d48245bb02b3 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
@@ -24,14 +24,14 @@
 #ifndef __PLAT_GPIO_CFG_H
 #define __PLAT_GPIO_CFG_H __FILE__
 
-typedef unsigned int __bitwise__ s3c_gpio_pull_t;
+typedef unsigned int __bitwise__ samsung_gpio_pull_t;
 typedef unsigned int __bitwise__ s5p_gpio_drvstr_t;
 
 /* forward declaration if gpio-core.h hasn't been included */
-struct s3c_gpio_chip;
+struct samsung_gpio_chip;
 
 /**
- * struct s3c_gpio_cfg GPIO configuration
+ * struct samsung_gpio_cfg GPIO configuration
  * @cfg_eint: Configuration setting when used for external interrupt source
  * @get_pull: Read the current pull configuration for the GPIO
  * @set_pull: Set the current pull configuraiton for the GPIO
@@ -44,20 +44,20 @@ struct s3c_gpio_chip;
  * per-bank configuration information that other systems such as the
  * external interrupt code will need.
  *
- * @sa s3c_gpio_cfgpin
+ * @sa samsung_gpio_cfgpin
  * @sa s3c_gpio_getcfg
  * @sa s3c_gpio_setpull
  * @sa s3c_gpio_getpull
  */
-struct s3c_gpio_cfg {
+struct samsung_gpio_cfg {
         unsigned int    cfg_eint;
 
-        s3c_gpio_pull_t (*get_pull)(struct s3c_gpio_chip *chip, unsigned offs);
-        int             (*set_pull)(struct s3c_gpio_chip *chip, unsigned offs,
-                                    s3c_gpio_pull_t pull);
+        samsung_gpio_pull_t     (*get_pull)(struct samsung_gpio_chip *chip, unsigned offs);
+        int             (*set_pull)(struct samsung_gpio_chip *chip, unsigned offs,
+                                    samsung_gpio_pull_t pull);
 
-        unsigned (*get_config)(struct s3c_gpio_chip *chip, unsigned offs);
-        int      (*set_config)(struct s3c_gpio_chip *chip, unsigned offs,
+        unsigned (*get_config)(struct samsung_gpio_chip *chip, unsigned offs);
+        int      (*set_config)(struct samsung_gpio_chip *chip, unsigned offs,
                                unsigned config);
 };
 
@@ -69,7 +69,7 @@ struct s3c_gpio_cfg {
 #define S3C_GPIO_OUTPUT (S3C_GPIO_SPECIAL(1))
 #define S3C_GPIO_SFN(x) (S3C_GPIO_SPECIAL(x))
 
-#define s3c_gpio_is_cfg_special(_cfg) \
+#define samsung_gpio_is_cfg_special(_cfg) \
         (((_cfg) & S3C_GPIO_SPECIAL_MARK) == S3C_GPIO_SPECIAL_MARK)
 
 /**
@@ -128,9 +128,9 @@ extern int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
  * up or down settings, and it may be dependent on the chip that is being
  * used to whether the particular mode is available.
  */
-#define S3C_GPIO_PULL_NONE      ((__force s3c_gpio_pull_t)0x00)
-#define S3C_GPIO_PULL_DOWN      ((__force s3c_gpio_pull_t)0x01)
-#define S3C_GPIO_PULL_UP        ((__force s3c_gpio_pull_t)0x02)
+#define S3C_GPIO_PULL_NONE      ((__force samsung_gpio_pull_t)0x00)
+#define S3C_GPIO_PULL_DOWN      ((__force samsung_gpio_pull_t)0x01)
+#define S3C_GPIO_PULL_UP        ((__force samsung_gpio_pull_t)0x02)
 
 /**
  * s3c_gpio_setpull() - set the state of a gpio pin pull resistor
@@ -143,7 +143,7 @@ extern int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
  *
  * @pull is one of S3C_GPIO_PULL_NONE, S3C_GPIO_PULL_DOWN or S3C_GPIO_PULL_UP.
 */
-extern int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull);
+extern int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull);
 
 /**
  * s3c_gpio_getpull() - get the pull resistor state of a gpio pin
@@ -151,7 +151,7 @@ extern int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull);
  *
  * Read the pull resistor value for the specified pin.
 */
-extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin);
+extern samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin);
 
 /* configure `all` aspects of an gpio */
 
@@ -170,7 +170,7 @@ extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin);
  * @sa s3c_gpio_cfgpin_range
  */
 extern int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
-                                 unsigned int cfg, s3c_gpio_pull_t pull);
+                                 unsigned int cfg, samsung_gpio_pull_t pull);
 
 static inline int s3c_gpio_cfgrange_nopull(unsigned int pin, unsigned int size,
                                            unsigned int cfg)
diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h
index 8cad4cf19c3c..1fe6917f6a2a 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-core.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-core.h
@@ -25,22 +25,22 @@
  * specific code.
 */
 
-struct s3c_gpio_chip;
+struct samsung_gpio_chip;
 
 /**
- * struct s3c_gpio_pm - power management (suspend/resume) information
+ * struct samsung_gpio_pm - power management (suspend/resume) information
  * @save: Routine to save the state of the GPIO block
  * @resume: Routine to resume the GPIO block.
  */
-struct s3c_gpio_pm {
-        void (*save)(struct s3c_gpio_chip *chip);
-        void (*resume)(struct s3c_gpio_chip *chip);
+struct samsung_gpio_pm {
+        void (*save)(struct samsung_gpio_chip *chip);
+        void (*resume)(struct samsung_gpio_chip *chip);
 };
 
-struct s3c_gpio_cfg;
+struct samsung_gpio_cfg;
 
 /**
- * struct s3c_gpio_chip - wrapper for specific implementation of gpio
+ * struct samsung_gpio_chip - wrapper for specific implementation of gpio
  * @chip: The chip structure to be exported via gpiolib.
  * @base: The base pointer to the gpio configuration registers.
  * @group: The group register number for gpio interrupt support.
@@ -60,10 +60,10 @@ struct s3c_gpio_cfg;
  * CPU cores trying to get one lock for different GPIO banks, where each
  * bank of GPIO has its own register space and configuration registers.
  */
-struct s3c_gpio_chip {
+struct samsung_gpio_chip {
         struct gpio_chip        chip;
-        struct s3c_gpio_cfg     *config;
-        struct s3c_gpio_pm      *pm;
+        struct samsung_gpio_cfg *config;
+        struct samsung_gpio_pm  *pm;
         void __iomem            *base;
         int                     irq_base;
         int                     group;
@@ -73,58 +73,11 @@ struct s3c_gpio_chip {
 #endif
 };
 
-static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc)
+static inline struct samsung_gpio_chip *to_samsung_gpio(struct gpio_chip *gpc)
 {
-        return container_of(gpc, struct s3c_gpio_chip, chip);
+        return container_of(gpc, struct samsung_gpio_chip, chip);
 }
 
-/** s3c_gpiolib_add() - add the s3c specific version of a gpio_chip.
- * @chip: The chip to register
- *
- * This is a wrapper to gpiochip_add() that takes our specific gpio chip
- * information and makes the necessary alterations for the platform and
- * notes the information for use with the configuration systems and any
- * other parts of the system.
- */
-extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip);
-
-/* CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
- * for use with the configuration calls, and other parts of the s3c gpiolib
- * support code.
- *
- * Not all s3c support code will need this, as some configurations of cpu
- * may only support one or two different configuration options and have an
- * easy gpio to s3c_gpio_chip mapping function. If this is the case, then
- * the machine support file should provide its own s3c_gpiolib_getchip()
- * and any other necessary functions.
- */
-
-/**
- * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
- * @chip: The gpio chip that is being configured.
- * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
- *
- * This helper deal with the GPIO cases where the control register has 4 bits
- * of control per GPIO, generally in the form of:
- * 0000 = Input
- * 0001 = Output
- * others = Special functions (dependent on bank)
- *
- * Note, since the code to deal with the case where there are two control
- * registers instead of one, we do not have a separate set of function
- * (samsung_gpiolib_add_4bit2_chips)for each case.
- */
-extern void samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip,
-                                           int nr_chips);
-extern void samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip,
-                                            int nr_chips);
-extern void samsung_gpiolib_add_2bit_chips(struct s3c_gpio_chip *chip,
-                                           int nr_chips);
-
-extern void samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip);
-extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip);
-
-
 /**
  * samsung_gpiolib_to_irq - convert gpio pin to irq number
  * @chip: The gpio chip that the pin belongs to.
@@ -136,36 +89,36 @@ extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip);
 extern int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset);
 
 /* exported for core SoC support to change */
-extern struct s3c_gpio_cfg s3c24xx_gpiocfg_default;
+extern struct samsung_gpio_cfg s3c24xx_gpiocfg_default;
 
 #ifdef CONFIG_S3C_GPIO_TRACK
-extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
+extern struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END];
 
-static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip)
+static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int chip)
 {
         return (chip < S3C_GPIO_END) ? s3c_gpios[chip] : NULL;
 }
 #else
-/* machine specific code should provide s3c_gpiolib_getchip */
+/* machine specific code should provide samsung_gpiolib_getchip */
 
 #include <mach/gpio-track.h>
 
-static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { }
+static inline void s3c_gpiolib_track(struct samsung_gpio_chip *chip) { }
 #endif
 
 #ifdef CONFIG_PM
-extern struct s3c_gpio_pm s3c_gpio_pm_1bit;
-extern struct s3c_gpio_pm s3c_gpio_pm_2bit;
-extern struct s3c_gpio_pm s3c_gpio_pm_4bit;
+extern struct samsung_gpio_pm samsung_gpio_pm_1bit;
+extern struct samsung_gpio_pm samsung_gpio_pm_2bit;
+extern struct samsung_gpio_pm samsung_gpio_pm_4bit;
 #define __gpio_pm(x) x
 #else
-#define s3c_gpio_pm_1bit NULL
-#define s3c_gpio_pm_2bit NULL
-#define s3c_gpio_pm_4bit NULL
+#define samsung_gpio_pm_1bit NULL
+#define samsung_gpio_pm_2bit NULL
+#define samsung_gpio_pm_4bit NULL
 #define __gpio_pm(x) NULL
 
 #endif /* CONFIG_PM */
 
 /* locking wrappers to deal with multiple access to the same gpio bank */
-#define s3c_gpio_lock(_oc, _fl) spin_lock_irqsave(&(_oc)->lock, _fl)
-#define s3c_gpio_unlock(_oc, _fl) spin_unlock_irqrestore(&(_oc)->lock, _fl)
+#define samsung_gpio_lock(_oc, _fl) spin_lock_irqsave(&(_oc)->lock, _fl)
+#define samsung_gpio_unlock(_oc, _fl) spin_unlock_irqrestore(&(_oc)->lock, _fl)
diff --git a/arch/arm/plat-samsung/include/plat/gpio-fns.h b/arch/arm/plat-samsung/include/plat/gpio-fns.h
new file mode 100644
index 000000000000..bab139201761
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/gpio-fns.h
@@ -0,0 +1,98 @@
+/* arch/arm/mach-s3c2410/include/mach/gpio-fns.h
+ *
+ * Copyright (c) 2003-2009 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - hardware
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __MACH_GPIO_FNS_H
+#define __MACH_GPIO_FNS_H __FILE__
+
+/* These functions are in the to-be-removed category and it is strongly
+ * encouraged not to use these in new code. They will be marked deprecated
+ * very soon.
+ *
+ * Most of the functionality can be either replaced by the gpiocfg calls
+ * for the s3c platform or by the generic GPIOlib API.
+ *
+ * As of 2.6.35-rc, these will be removed, with the few drivers using them
+ * either replaced or given a wrapper until the calls can be removed.
+*/
+
+#include <plat/gpio-cfg.h>
+
+static inline void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int cfg)
+{
+        /* 1:1 mapping between cfgpin and setcfg calls at the moment */
+        s3c_gpio_cfgpin(pin, cfg);
+}
+
+/* external functions for GPIO support
+ *
+ * These allow various different clients to access the same GPIO
+ * registers without conflicting. If your driver only owns the entire
+ * GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
+*/
+
+extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
+
+/* s3c2410_gpio_getirq
+ *
+ * turn the given pin number into the corresponding IRQ number
+ *
+ * returns:
+ *      < 0 = no interrupt for this pin
+ *      >=0 = interrupt number for the pin
+*/
+
+extern int s3c2410_gpio_getirq(unsigned int pin);
+
+/* s3c2410_gpio_irqfilter
+ *
+ * set the irq filtering on the given pin
+ *
+ * on = 0 => disable filtering
+ *      1 => enable filtering
+ *
+ * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with
+ *          width of filter (0 through 63)
+ *
+ *
+*/
+
+extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
+                                  unsigned int config);
+
+/* s3c2410_gpio_pullup
+ *
+ * This call should be replaced with s3c_gpio_setpull().
+ *
+ * As a note, there is currently no distinction between pull-up and pull-down
+ * in the s3c24xx series devices with only an on/off configuration.
+ */
+
+/* s3c2410_gpio_pullup
+ *
+ * configure the pull-up control on the given pin
+ *
+ * to = 1 => disable the pull-up
+ *      0 => enable the pull-up
+ *
+ * eg;
+ *
+ *   s3c2410_gpio_pullup(S3C2410_GPB(0), 0);
+ *   s3c2410_gpio_pullup(S3C2410_GPE(8), 0);
+*/
+
+extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
+
+extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
+
+extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
+
+#endif /* __MACH_GPIO_FNS_H */
diff --git a/arch/arm/plat-samsung/include/plat/iic.h b/arch/arm/plat-samsung/include/plat/iic.h
index 56b0059439e1..51d52e767a19 100644
--- a/arch/arm/plat-samsung/include/plat/iic.h
+++ b/arch/arm/plat-samsung/include/plat/iic.h
@@ -60,6 +60,7 @@ extern void s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *i2c);
 extern void s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *i2c);
 extern void s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *i2c);
 extern void s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *i2c);
+extern void s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *i2c);
 
 /* defined by architecture to configure gpio */
 extern void s3c_i2c0_cfg_gpio(struct platform_device *dev);
diff --git a/arch/arm/plat-s3c24xx/include/plat/irq.h b/arch/arm/plat-samsung/include/plat/irq.h
index ec087d6054b1..e21a89bc26c9 100644
--- a/arch/arm/plat-s3c24xx/include/plat/irq.h
+++ b/arch/arm/plat-samsung/include/plat/irq.h
@@ -1,4 +1,4 @@
-/* linux/include/asm-arm/plat-s3c24xx/irq.h
+/* linux/arch/arm/plat-samsung/include/plat/irq.h
  *
  * Copyright (c) 2004-2005 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
@@ -25,9 +25,9 @@
 extern struct irq_chip s3c_irq_level_chip;
 extern struct irq_chip s3c_irq_chip;
 
-static inline void
-s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,
-                int subcheck)
+static inline void s3c_irqsub_mask(unsigned int irqno,
+                                   unsigned int parentbit,
+                                   int subcheck)
 {
         unsigned long mask;
         unsigned long submask;
@@ -39,17 +39,16 @@ s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,
 
         /* check to see if we need to mask the parent IRQ */
 
-        if ((submask  & subcheck) == subcheck) {
+        if ((submask  & subcheck) == subcheck)
                 __raw_writel(mask | parentbit, S3C2410_INTMSK);
-        }
 
         /* write back masks */
         __raw_writel(submask, S3C2410_INTSUBMSK);
 
 }
 
-static inline void
-s3c_irqsub_unmask(unsigned int irqno, unsigned int parentbit)
+static inline void s3c_irqsub_unmask(unsigned int irqno,
+                                     unsigned int parentbit)
 {
         unsigned long mask;
         unsigned long submask;
@@ -66,8 +65,9 @@ s3c_irqsub_unmask(unsigned int irqno, unsigned int parentbit)
 }
 
 
-static inline void
-s3c_irqsub_maskack(unsigned int irqno, unsigned int parentmask, unsigned int group)
+static inline void s3c_irqsub_maskack(unsigned int irqno,
+                                      unsigned int parentmask,
+                                      unsigned int group)
 {
         unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
 
@@ -86,8 +86,9 @@ s3c_irqsub_maskack(unsigned int irqno, unsigned int parentmask, unsigned int gro
         }
 }
 
-static inline void
-s3c_irqsub_ack(unsigned int irqno, unsigned int parentmask, unsigned int group)
+static inline void s3c_irqsub_ack(unsigned int irqno,
+                                  unsigned int parentmask,
+                                  unsigned int group)
 {
         unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
 
diff --git a/arch/arm/plat-s5p/include/plat/irqs.h b/arch/arm/plat-samsung/include/plat/irqs.h
index ba9121c60a2a..94ecf8c5c857 100644
--- a/arch/arm/plat-s5p/include/plat/irqs.h
+++ b/arch/arm/plat-samsung/include/plat/irqs.h
@@ -1,4 +1,4 @@
-/* linux/arch/arm/plat-s5p/include/plat/irqs.h
+/* linux/arch/arm/plat-samsung/include/plat/irqs.h
  *
  * Copyright (c) 2009 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com/
@@ -10,8 +10,8 @@
  * published by the Free Software Foundation.
 */
 
-#ifndef __ASM_PLAT_S5P_IRQS_H
-#define __ASM_PLAT_S5P_IRQS_H __FILE__
+#ifndef __PLAT_SAMSUNG_IRQS_H
+#define __PLAT_SAMSUNG_IRQS_H __FILE__
 
 /* we keep the first set of CPU IRQs out of the range of
  * the ISA space, so that the PC104 has them to itself
@@ -112,4 +112,4 @@
 #define S5P_IRQ_TYPE_EDGE_RISING        (0x03)
 #define S5P_IRQ_TYPE_EDGE_BOTH          (0x04)
 
-#endif /* __ASM_PLAT_S5P_IRQS_H */
+#endif /* __PLAT_SAMSUNG_IRQS_H */
diff --git a/arch/arm/plat-samsung/include/plat/map-s3c.h b/arch/arm/plat-samsung/include/plat/map-s3c.h
new file mode 100644
index 000000000000..7d048759b772
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/map-s3c.h
@@ -0,0 +1,84 @@
+/* linux/arch/arm/plat-samsung/include/plat/map-s3c.h
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_MAP_S3C_H
+#define __ASM_PLAT_MAP_S3C_H __FILE__
+
+#define S3C24XX_VA_IRQ          S3C_VA_IRQ
+#define S3C24XX_VA_MEMCTRL      S3C_VA_MEM
+#define S3C24XX_VA_UART         S3C_VA_UART
+
+#define S3C24XX_VA_TIMER        S3C_VA_TIMER
+#define S3C24XX_VA_CLKPWR       S3C_VA_SYS
+#define S3C24XX_VA_WATCHDOG     S3C_VA_WATCHDOG
+
+#define S3C2412_VA_SSMC         S3C_ADDR_CPU(0x00000000)
+#define S3C2412_VA_EBI          S3C_ADDR_CPU(0x00010000)
+
+#define S3C2410_PA_UART         (0x50000000)
+#define S3C24XX_PA_UART         S3C2410_PA_UART
+
+#ifndef S3C_UART_OFFSET
+#define S3C_UART_OFFSET         (0x400)
+#endif
+
+/*
+ * GPIO ports
+ *
+ * the calculation for the VA of this must ensure that
+ * it is the same distance apart from the UART in the
+ * phsyical address space, as the initial mapping for the IO
+ * is done as a 1:1 mapping. This puts it (currently) at
+ * 0xFA800000, which is not in the way of any current mapping
+ * by the base system.
+*/
+
+#define S3C2410_PA_GPIO         (0x56000000)
+#define S3C24XX_PA_GPIO         S3C2410_PA_GPIO
+
+#define S3C24XX_VA_GPIO         ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
+#define S3C64XX_VA_GPIO         S3C_ADDR_CPU(0x00000000)
+
+#define S3C64XX_VA_MODEM        S3C_ADDR_CPU(0x00100000)
+#define S3C64XX_VA_USB_HSPHY    S3C_ADDR_CPU(0x00200000)
+
+#define S3C_VA_USB_HSPHY        S3C64XX_VA_USB_HSPHY
+
+/*
+ * ISA style IO, for each machine to sort out mappings for,
+ * if it implements it. We reserve two 16M regions for ISA.
+ */
+
+#define S3C2410_ADDR(x)         S3C_ADDR(x)
+
+#define S3C24XX_VA_ISA_WORD     S3C2410_ADDR(0x02000000)
+#define S3C24XX_VA_ISA_BYTE     S3C2410_ADDR(0x03000000)
+
+/* deal with the registers that move under the 2412/2413 */
+
+#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
+#ifndef __ASSEMBLY__
+extern void __iomem *s3c24xx_va_gpio2;
+#endif
+#ifdef CONFIG_CPU_S3C2412_ONLY
+#define S3C24XX_VA_GPIO2        (S3C24XX_VA_GPIO + 0x10)
+#else
+#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
+#endif
+#else
+#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
+#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
+#endif
+
+#include <plat/map-s5p.h>
+
+#endif /* __ASM_PLAT_MAP_S3C_H */
diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-samsung/include/plat/map-s5p.h
index 36d3551173b2..c2d7bdae5891 100644
--- a/arch/arm/plat-s5p/include/plat/map-s5p.h
+++ b/arch/arm/plat-samsung/include/plat/map-s5p.h
@@ -1,4 +1,4 @@
-/* linux/arch/arm/plat-s5p/include/plat/map-s5p.h
+/* linux/arch/arm/plat-samsung/include/plat/map-s5p.h
  *
  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com/
@@ -40,8 +40,6 @@
 #define S5P_VA_GIC_CPU          S3C_ADDR(0x02810000)
 #define S5P_VA_GIC_DIST         S3C_ADDR(0x02820000)
 
-#define S3C_VA_USB_HSPHY        S3C_ADDR(0x02900000)
-
 #define VA_VIC(x)               (S3C_VA_IRQ + ((x) * 0x10000))
 #define VA_VIC0                 VA_VIC(0)
 #define VA_VIC1                 VA_VIC(1)
@@ -58,4 +56,6 @@
 #define S3C_UART_OFFSET         (0x400)
 #endif
 
+#include <plat/map-s3c.h>
+
 #endif /* __ASM_PLAT_MAP_S5P_H */
diff --git a/arch/arm/plat-s3c24xx/include/plat/mci.h b/arch/arm/plat-samsung/include/plat/mci.h
index 2ac2b21ec490..c42d31711944 100644
--- a/arch/arm/plat-s3c24xx/include/plat/mci.h
+++ b/arch/arm/plat-samsung/include/plat/mci.h
@@ -27,11 +27,11 @@
  * to a non-zero value, otherwise the default of 3.2-3.4V is used.
  */
 struct s3c24xx_mci_pdata {
-        unsigned int    no_wprotect : 1;
-        unsigned int    no_detect : 1;
-        unsigned int    wprotect_invert : 1;
-        unsigned int    detect_invert : 1;   /* set => detect active high. */
-        unsigned int    use_dma : 1;
+        unsigned int    no_wprotect:1;
+        unsigned int    no_detect:1;
+        unsigned int    wprotect_invert:1;
+        unsigned int    detect_invert:1;        /* set => detect active high */
+        unsigned int    use_dma:1;
 
         unsigned int    gpio_detect;
         unsigned int    gpio_wprotect;
diff --git a/arch/arm/plat-s5p/include/plat/mfc.h b/arch/arm/plat-samsung/include/plat/mfc.h
index 6697f8cb2949..ac13227272f0 100644
--- a/arch/arm/plat-s5p/include/plat/mfc.h
+++ b/arch/arm/plat-samsung/include/plat/mfc.h
@@ -7,8 +7,8 @@
  * option) any later version.
  */
 
-#ifndef __PLAT_S5P_MFC_H
-#define __PLAT_S5P_MFC_H
+#ifndef __PLAT_SAMSUNG_MFC_H
+#define __PLAT_SAMSUNG_MFC_H __FILE__
 
 /**
  * s5p_mfc_reserve_mem - function to early reserve memory for MFC driver
@@ -24,4 +24,4 @@
 void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
                                 phys_addr_t lbase, unsigned int lsize);
 
-#endif /* __PLAT_S5P_MFC_H */
+#endif /* __PLAT_SAMSUNG_MFC_H */
diff --git a/arch/arm/plat-s5p/include/plat/mipi_csis.h b/arch/arm/plat-samsung/include/plat/mipi_csis.h
index 9bd254c5ed22..c45b1e8d4c2e 100644
--- a/arch/arm/plat-s5p/include/plat/mipi_csis.h
+++ b/arch/arm/plat-samsung/include/plat/mipi_csis.h
@@ -8,8 +8,8 @@
  * published by the Free Software Foundation.
  */
 
-#ifndef PLAT_S5P_MIPI_CSIS_H_
-#define PLAT_S5P_MIPI_CSIS_H_ __FILE__
+#ifndef __PLAT_SAMSUNG_MIPI_CSIS_H_
+#define __PLAT_SAMSUNG_MIPI_CSIS_H_ __FILE__
 
 struct platform_device;
 
@@ -40,4 +40,4 @@ struct s5p_platform_mipi_csis {
  */
 int s5p_csis_phy_enable(struct platform_device *pdev, bool on);
 
-#endif /* PLAT_S5P_MIPI_CSIS_H_ */
+#endif /* __PLAT_SAMSUNG_MIPI_CSIS_H_ */
diff --git a/arch/arm/plat-samsung/include/plat/pll.h b/arch/arm/plat-samsung/include/plat/pll.h
new file mode 100644
index 000000000000..357af7c1c664
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/pll.h
@@ -0,0 +1,323 @@
+/* linux/arch/arm/plat-samsung/include/plat/pll.h
+ *
+ * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * Samsung PLL codes
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <asm/div64.h>
+
+#define S3C24XX_PLL_MDIV_MASK           (0xFF)
+#define S3C24XX_PLL_PDIV_MASK           (0x1F)
+#define S3C24XX_PLL_SDIV_MASK           (0x3)
+#define S3C24XX_PLL_MDIV_SHIFT          (12)
+#define S3C24XX_PLL_PDIV_SHIFT          (4)
+#define S3C24XX_PLL_SDIV_SHIFT          (0)
+
+static inline unsigned int s3c24xx_get_pll(unsigned int pllval,
+                                           unsigned int baseclk)
+{
+        unsigned int mdiv, pdiv, sdiv;
+        uint64_t fvco;
+
+        mdiv = (pllval >> S3C24XX_PLL_MDIV_SHIFT) & S3C24XX_PLL_MDIV_MASK;
+        pdiv = (pllval >> S3C24XX_PLL_PDIV_SHIFT) & S3C24XX_PLL_PDIV_MASK;
+        sdiv = (pllval >> S3C24XX_PLL_SDIV_SHIFT) & S3C24XX_PLL_SDIV_MASK;
+
+        fvco = (uint64_t)baseclk * (mdiv + 8);
+        do_div(fvco, (pdiv + 2) << sdiv);
+
+        return (unsigned int)fvco;
+}
+
+#define S3C2416_PLL_MDIV_MASK           (0x3FF)
+#define S3C2416_PLL_PDIV_MASK           (0x3F)
+#define S3C2416_PLL_SDIV_MASK           (0x7)
+#define S3C2416_PLL_MDIV_SHIFT          (14)
+#define S3C2416_PLL_PDIV_SHIFT          (5)
+#define S3C2416_PLL_SDIV_SHIFT          (0)
+
+static inline unsigned int s3c2416_get_pll(unsigned int pllval,
+                                           unsigned int baseclk)
+{
+        unsigned int mdiv, pdiv, sdiv;
+        uint64_t fvco;
+
+        mdiv = (pllval >> S3C2416_PLL_MDIV_SHIFT) & S3C2416_PLL_MDIV_MASK;
+        pdiv = (pllval >> S3C2416_PLL_PDIV_SHIFT) & S3C2416_PLL_PDIV_MASK;
+        sdiv = (pllval >> S3C2416_PLL_SDIV_SHIFT) & S3C2416_PLL_SDIV_MASK;
+
+        fvco = (uint64_t)baseclk * mdiv;
+        do_div(fvco, (pdiv << sdiv));
+
+        return (unsigned int)fvco;
+}
+
+#define S3C6400_PLL_MDIV_MASK           (0x3FF)
+#define S3C6400_PLL_PDIV_MASK           (0x3F)
+#define S3C6400_PLL_SDIV_MASK           (0x7)
+#define S3C6400_PLL_MDIV_SHIFT          (16)
+#define S3C6400_PLL_PDIV_SHIFT          (8)
+#define S3C6400_PLL_SDIV_SHIFT          (0)
+
+static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
+                                            u32 pllcon)
+{
+        u32 mdiv, pdiv, sdiv;
+        u64 fvco = baseclk;
+
+        mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK;
+        pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK;
+        sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK;
+
+        fvco *= mdiv;
+        do_div(fvco, (pdiv << sdiv));
+
+        return (unsigned long)fvco;
+}
+
+#define PLL6553X_MDIV_MASK      (0x7F)
+#define PLL6553X_PDIV_MASK      (0x1F)
+#define PLL6553X_SDIV_MASK      (0x3)
+#define PLL6553X_KDIV_MASK      (0xFFFF)
+#define PLL6553X_MDIV_SHIFT     (16)
+#define PLL6553X_PDIV_SHIFT     (8)
+#define PLL6553X_SDIV_SHIFT     (0)
+
+static inline unsigned long s3c_get_pll6553x(unsigned long baseclk,
+                                             u32 pll_con0, u32 pll_con1)
+{
+        unsigned long result;
+        u32 mdiv, pdiv, sdiv, kdiv;
+        u64 tmp;
+
+        mdiv = (pll_con0 >> PLL6553X_MDIV_SHIFT) & PLL6553X_MDIV_MASK;
+        pdiv = (pll_con0 >> PLL6553X_PDIV_SHIFT) & PLL6553X_PDIV_MASK;
+        sdiv = (pll_con0 >> PLL6553X_SDIV_SHIFT) & PLL6553X_SDIV_MASK;
+        kdiv = pll_con1 & PLL6553X_KDIV_MASK;
+
+        /*
+         * We need to multiple baseclk by mdiv (the integer part) and kdiv
+         * which is in 2^16ths, so shift mdiv up (does not overflow) and
+         * add kdiv before multiplying. The use of tmp is to avoid any
+         * overflows before shifting bac down into result when multipling
+         * by the mdiv and kdiv pair.
+         */
+
+        tmp = baseclk;
+        tmp *= (mdiv << 16) + kdiv;
+        do_div(tmp, (pdiv << sdiv));
+        result = tmp >> 16;
+
+        return result;
+}
+
+#define PLL35XX_MDIV_MASK       (0x3FF)
+#define PLL35XX_PDIV_MASK       (0x3F)
+#define PLL35XX_SDIV_MASK       (0x7)
+#define PLL35XX_MDIV_SHIFT      (16)
+#define PLL35XX_PDIV_SHIFT      (8)
+#define PLL35XX_SDIV_SHIFT      (0)
+
+static inline unsigned long s5p_get_pll35xx(unsigned long baseclk, u32 pll_con)
+{
+        u32 mdiv, pdiv, sdiv;
+        u64 fvco = baseclk;
+
+        mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
+        pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
+        sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
+
+        fvco *= mdiv;
+        do_div(fvco, (pdiv << sdiv));
+
+        return (unsigned long)fvco;
+}
+
+#define PLL36XX_KDIV_MASK       (0xFFFF)
+#define PLL36XX_MDIV_MASK       (0x1FF)
+#define PLL36XX_PDIV_MASK       (0x3F)
+#define PLL36XX_SDIV_MASK       (0x7)
+#define PLL36XX_MDIV_SHIFT      (16)
+#define PLL36XX_PDIV_SHIFT      (8)
+#define PLL36XX_SDIV_SHIFT      (0)
+
+static inline unsigned long s5p_get_pll36xx(unsigned long baseclk,
+                                            u32 pll_con0, u32 pll_con1)
+{
+        unsigned long result;
+        u32 mdiv, pdiv, sdiv, kdiv;
+        u64 tmp;
+
+        mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
+        pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
+        sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
+        kdiv = pll_con1 & PLL36XX_KDIV_MASK;
+
+        tmp = baseclk;
+
+        tmp *= (mdiv << 16) + kdiv;
+        do_div(tmp, (pdiv << sdiv));
+        result = tmp >> 16;
+
+        return result;
+}
+
+#define PLL45XX_MDIV_MASK       (0x3FF)
+#define PLL45XX_PDIV_MASK       (0x3F)
+#define PLL45XX_SDIV_MASK       (0x7)
+#define PLL45XX_MDIV_SHIFT      (16)
+#define PLL45XX_PDIV_SHIFT      (8)
+#define PLL45XX_SDIV_SHIFT      (0)
+
+enum pll45xx_type_t {
+        pll_4500,
+        pll_4502,
+        pll_4508
+};
+
+static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con,
+                                            enum pll45xx_type_t pll_type)
+{
+        u32 mdiv, pdiv, sdiv;
+        u64 fvco = baseclk;
+
+        mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
+        pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
+        sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
+
+        if (pll_type == pll_4508)
+                sdiv = sdiv - 1;
+
+        fvco *= mdiv;
+        do_div(fvco, (pdiv << sdiv));
+
+        return (unsigned long)fvco;
+}
+
+/* CON0 bit-fields */
+#define PLL46XX_MDIV_MASK       (0x1FF)
+#define PLL46XX_PDIV_MASK       (0x3F)
+#define PLL46XX_SDIV_MASK       (0x7)
+#define PLL46XX_LOCKED_SHIFT    (29)
+#define PLL46XX_MDIV_SHIFT      (16)
+#define PLL46XX_PDIV_SHIFT      (8)
+#define PLL46XX_SDIV_SHIFT      (0)
+
+/* CON1 bit-fields */
+#define PLL46XX_MRR_MASK        (0x1F)
+#define PLL46XX_MFR_MASK        (0x3F)
+#define PLL46XX_KDIV_MASK       (0xFFFF)
+#define PLL4650C_KDIV_MASK      (0xFFF)
+#define PLL46XX_MRR_SHIFT       (24)
+#define PLL46XX_MFR_SHIFT       (16)
+#define PLL46XX_KDIV_SHIFT      (0)
+
+enum pll46xx_type_t {
+        pll_4600,
+        pll_4650,
+        pll_4650c,
+};
+
+static inline unsigned long s5p_get_pll46xx(unsigned long baseclk,
+                                            u32 pll_con0, u32 pll_con1,
+                                            enum pll46xx_type_t pll_type)
+{
+        unsigned long result;
+        u32 mdiv, pdiv, sdiv, kdiv;
+        u64 tmp;
+
+        mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
+        pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
+        sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
+        kdiv = pll_con1 & PLL46XX_KDIV_MASK;
+
+        if (pll_type == pll_4650c)
+                kdiv = pll_con1 & PLL4650C_KDIV_MASK;
+        else
+                kdiv = pll_con1 & PLL46XX_KDIV_MASK;
+
+        tmp = baseclk;
+
+        if (pll_type == pll_4600) {
+                tmp *= (mdiv << 16) + kdiv;
+                do_div(tmp, (pdiv << sdiv));
+                result = tmp >> 16;
+        } else {
+                tmp *= (mdiv << 10) + kdiv;
+                do_div(tmp, (pdiv << sdiv));
+                result = tmp >> 10;
+        }
+
+        return result;
+}
+
+#define PLL90XX_MDIV_MASK       (0xFF)
+#define PLL90XX_PDIV_MASK       (0x3F)
+#define PLL90XX_SDIV_MASK       (0x7)
+#define PLL90XX_KDIV_MASK       (0xffff)
+#define PLL90XX_LOCKED_SHIFT    (29)
+#define PLL90XX_MDIV_SHIFT      (16)
+#define PLL90XX_PDIV_SHIFT      (8)
+#define PLL90XX_SDIV_SHIFT      (0)
+#define PLL90XX_KDIV_SHIFT      (0)
+
+static inline unsigned long s5p_get_pll90xx(unsigned long baseclk,
+                                            u32 pll_con, u32 pll_conk)
+{
+        unsigned long result;
+        u32 mdiv, pdiv, sdiv, kdiv;
+        u64 tmp;
+
+        mdiv = (pll_con >> PLL90XX_MDIV_SHIFT) & PLL90XX_MDIV_MASK;
+        pdiv = (pll_con >> PLL90XX_PDIV_SHIFT) & PLL90XX_PDIV_MASK;
+        sdiv = (pll_con >> PLL90XX_SDIV_SHIFT) & PLL90XX_SDIV_MASK;
+        kdiv = pll_conk & PLL90XX_KDIV_MASK;
+
+        /*
+         * We need to multiple baseclk by mdiv (the integer part) and kdiv
+         * which is in 2^16ths, so shift mdiv up (does not overflow) and
+         * add kdiv before multiplying. The use of tmp is to avoid any
+         * overflows before shifting bac down into result when multipling
+         * by the mdiv and kdiv pair.
+         */
+
+        tmp = baseclk;
+        tmp *= (mdiv << 16) + kdiv;
+        do_div(tmp, (pdiv << sdiv));
+        result = tmp >> 16;
+
+        return result;
+}
+
+#define PLL65XX_MDIV_MASK       (0x3FF)
+#define PLL65XX_PDIV_MASK       (0x3F)
+#define PLL65XX_SDIV_MASK       (0x7)
+#define PLL65XX_MDIV_SHIFT      (16)
+#define PLL65XX_PDIV_SHIFT      (8)
+#define PLL65XX_SDIV_SHIFT      (0)
+
+static inline unsigned long s5p_get_pll65xx(unsigned long baseclk, u32 pll_con)
+{
+        u32 mdiv, pdiv, sdiv;
+        u64 fvco = baseclk;
+
+        mdiv = (pll_con >> PLL65XX_MDIV_SHIFT) & PLL65XX_MDIV_MASK;
+        pdiv = (pll_con >> PLL65XX_PDIV_SHIFT) & PLL65XX_PDIV_MASK;
+        sdiv = (pll_con >> PLL65XX_SDIV_SHIFT) & PLL65XX_SDIV_MASK;
+
+        fvco *= mdiv;
+        do_div(fvco, (pdiv << sdiv));
+
+        return (unsigned long)fvco;
+}
diff --git a/arch/arm/plat-samsung/include/plat/pll6553x.h b/arch/arm/plat-samsung/include/plat/pll6553x.h
deleted file mode 100644
index b8b7e1d884f8..000000000000
--- a/arch/arm/plat-samsung/include/plat/pll6553x.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* arch/arm/plat-samsung/include/plat/pll6553x.h
- *      partially from arch/arm/mach-s3c64xx/include/mach/pll.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * Samsung PLL6553x PLL code
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* S3C6400 and compatible (S3C2416, etc.) EPLL code */
-
-#define PLL6553X_MDIV_MASK      ((1 << (23-16)) - 1)
-#define PLL6553X_PDIV_MASK      ((1 << (13-8)) - 1)
-#define PLL6553X_SDIV_MASK      ((1 << (2-0)) - 1)
-#define PLL6553X_MDIV_SHIFT     (16)
-#define PLL6553X_PDIV_SHIFT     (8)
-#define PLL6553X_SDIV_SHIFT     (0)
-#define PLL6553X_KDIV_MASK      (0xffff)
-
-static inline unsigned long s3c_get_pll6553x(unsigned long baseclk,
-                                             u32 pll0, u32 pll1)
-{
-        unsigned long result;
-        u32 mdiv, pdiv, sdiv, kdiv;
-        u64 tmp;
-
-        mdiv = (pll0 >> PLL6553X_MDIV_SHIFT) & PLL6553X_MDIV_MASK;
-        pdiv = (pll0 >> PLL6553X_PDIV_SHIFT) & PLL6553X_PDIV_MASK;
-        sdiv = (pll0 >> PLL6553X_SDIV_SHIFT) & PLL6553X_SDIV_MASK;
-        kdiv = pll1 & PLL6553X_KDIV_MASK;
-
-        /* We need to multiple baseclk by mdiv (the integer part) and kdiv
-         * which is in 2^16ths, so shift mdiv up (does not overflow) and
-         * add kdiv before multiplying. The use of tmp is to avoid any
-         * overflows before shifting bac down into result when multipling
-         * by the mdiv and kdiv pair.
-         */
-
-        tmp = baseclk;
-        tmp *= (mdiv << 16) + kdiv;
-        do_div(tmp, (pdiv << sdiv));
-        result = tmp >> 16;
-
-        return result;
-}
diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h
index f6749916d194..dcf68709f9cf 100644
--- a/arch/arm/plat-samsung/include/plat/pm.h
+++ b/arch/arm/plat-samsung/include/plat/pm.h
@@ -165,20 +165,20 @@ extern void s3c_pm_check_store(void);
 extern void s3c_pm_configure_extint(void);
 
 /**
- * s3c_pm_restore_gpios() - restore the state of the gpios after sleep.
+ * samsung_pm_restore_gpios() - restore the state of the gpios after sleep.
  *
  * Restore the state of the GPIO pins after sleep, which may involve ensuring
  * that we do not glitch the state of the pins from that the bootloader's
  * resume code has done.
 */
-extern void s3c_pm_restore_gpios(void);
+extern void samsung_pm_restore_gpios(void);
 
 /**
- * s3c_pm_save_gpios() - save the state of the GPIOs for restoring after sleep.
+ * samsung_pm_save_gpios() - save the state of the GPIOs for restoring after sleep.
  *
- * Save the GPIO states for resotration on resume. See s3c_pm_restore_gpios().
+ * Save the GPIO states for resotration on resume. See samsung_pm_restore_gpios().
  */
-extern void s3c_pm_save_gpios(void);
+extern void samsung_pm_save_gpios(void);
 
 extern void s3c_pm_save_core(void);
 extern void s3c_pm_restore_core(void);
diff --git a/arch/arm/mach-exynos4/include/mach/pwm-clock.h b/arch/arm/plat-samsung/include/plat/pwm-clock.h
index 8e12090287bb..bf6a60eb6237 100644
--- a/arch/arm/mach-exynos4/include/mach/pwm-clock.h
+++ b/arch/arm/plat-samsung/include/plat/pwm-clock.h
@@ -1,4 +1,4 @@
-/* linux/arch/arm/mach-exynos4/include/mach/pwm-clock.h
+/* linux/arch/arm/plat-samsung/include/plat/pwm-clock.h
  *
  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
@@ -8,17 +8,15 @@
  *      Ben Dooks <ben@simtec.co.uk>
  *      http://armlinux.simtec.co.uk/
  *
- * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
- *
- * EXYNOS4 - pwm clock and timer support
+ * SAMSUNG - pwm clock and timer support
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
 */
 
-#ifndef __ASM_ARCH_PWMCLK_H
-#define __ASM_ARCH_PWMCLK_H __FILE__
+#ifndef __ASM_PLAT_PWM_CLOCK_H
+#define __ASM_PLAT_PWM_CLOCK_H __FILE__
 
 /**
  * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
@@ -29,7 +27,14 @@
  */
 static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
 {
-        return tcfg == S3C64XX_TCFG1_MUX_TCLK;
+        if (soc_is_s3c24xx())
+                return tcfg == S3C2410_TCFG1_MUX_TCLK;
+        else if (soc_is_s3c64xx() || soc_is_s5pc100())
+                return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
+        else if (soc_is_s5p6440() || soc_is_s5p6450())
+                return 0;
+        else
+                return tcfg == S3C64XX_TCFG1_MUX_TCLK;
 }
 
 /**
@@ -41,7 +46,10 @@ static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
  */
 static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
 {
-        return 1 << tcfg1;
+        if (soc_is_s3c24xx())
+                return 1 << (tcfg1 + 1);
+        else
+                return 1 << tcfg1;
 }
 
 /**
@@ -51,7 +59,10 @@ static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
  */
 static inline unsigned int pwm_tdiv_has_div1(void)
 {
-        return 1;
+        if (soc_is_s3c24xx())
+                return 0;
+        else
+                return 1;
 }
 
 /**
@@ -62,9 +73,9 @@ static inline unsigned int pwm_tdiv_has_div1(void)
  */
 static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
 {
-        return ilog2(div);
+        if (soc_is_s3c24xx())
+                return ilog2(div) - 1;
+        else
+                return ilog2(div);
 }
-
-#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
-
-#endif /* __ASM_ARCH_PWMCLK_H */
+#endif /* __ASM_PLAT_PWM_CLOCK_H */
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-dma.h b/arch/arm/plat-samsung/include/plat/regs-dma.h
index 1b0f4c36d384..178bccbe4804 100644
--- a/arch/arm/plat-s3c24xx/include/plat/regs-dma.h
+++ b/arch/arm/plat-samsung/include/plat/regs-dma.h
@@ -1,4 +1,4 @@
-/* arch/arm/mach-s3c2410/include/mach/dma.h
+/* arch/arm/plat-samsung/include/plat/regs-dma.h
  *
  * Copyright (C) 2003-2006 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
@@ -10,7 +10,8 @@
  * published by the Free Software Foundation.
 */
 
-/* DMA Register definitions */
+#ifndef __ASM_PLAT_REGS_DMA_H
+#define __ASM_PLAT_REGS_DMA_H __FILE__
 
 #define S3C2410_DMA_DISRC               (0x00)
 #define S3C2410_DMA_DISRCC              (0x04)
@@ -24,74 +25,75 @@
 #define S3C2412_DMA_DMAREQSEL           (0x24)
 #define S3C2443_DMA_DMAREQSEL           (0x24)
 
-#define S3C2410_DISRCC_INC              (1<<0)
-#define S3C2410_DISRCC_APB              (1<<1)
+#define S3C2410_DISRCC_INC              (1 << 0)
+#define S3C2410_DISRCC_APB              (1 << 1)
 
-#define S3C2410_DMASKTRIG_STOP          (1<<2)
-#define S3C2410_DMASKTRIG_ON            (1<<1)
-#define S3C2410_DMASKTRIG_SWTRIG        (1<<0)
+#define S3C2410_DMASKTRIG_STOP          (1 << 2)
+#define S3C2410_DMASKTRIG_ON            (1 << 1)
+#define S3C2410_DMASKTRIG_SWTRIG        (1 << 0)
 
-#define S3C2410_DCON_DEMAND             (0<<31)
-#define S3C2410_DCON_HANDSHAKE          (1<<31)
-#define S3C2410_DCON_SYNC_PCLK          (0<<30)
-#define S3C2410_DCON_SYNC_HCLK          (1<<30)
+#define S3C2410_DCON_DEMAND             (0 << 31)
+#define S3C2410_DCON_HANDSHAKE          (1 << 31)
+#define S3C2410_DCON_SYNC_PCLK          (0 << 30)
+#define S3C2410_DCON_SYNC_HCLK          (1 << 30)
 
-#define S3C2410_DCON_INTREQ             (1<<29)
+#define S3C2410_DCON_INTREQ             (1 << 29)
 
-#define S3C2410_DCON_CH0_XDREQ0         (0<<24)
-#define S3C2410_DCON_CH0_UART0          (1<<24)
-#define S3C2410_DCON_CH0_SDI            (2<<24)
-#define S3C2410_DCON_CH0_TIMER          (3<<24)
-#define S3C2410_DCON_CH0_USBEP1         (4<<24)
+#define S3C2410_DCON_CH0_XDREQ0         (0 << 24)
+#define S3C2410_DCON_CH0_UART0          (1 << 24)
+#define S3C2410_DCON_CH0_SDI            (2 << 24)
+#define S3C2410_DCON_CH0_TIMER          (3 << 24)
+#define S3C2410_DCON_CH0_USBEP1         (4 << 24)
 
-#define S3C2410_DCON_CH1_XDREQ1         (0<<24)
-#define S3C2410_DCON_CH1_UART1          (1<<24)
-#define S3C2410_DCON_CH1_I2SSDI         (2<<24)
-#define S3C2410_DCON_CH1_SPI            (3<<24)
-#define S3C2410_DCON_CH1_USBEP2         (4<<24)
+#define S3C2410_DCON_CH1_XDREQ1         (0 << 24)
+#define S3C2410_DCON_CH1_UART1          (1 << 24)
+#define S3C2410_DCON_CH1_I2SSDI         (2 << 24)
+#define S3C2410_DCON_CH1_SPI            (3 << 24)
+#define S3C2410_DCON_CH1_USBEP2         (4 << 24)
 
-#define S3C2410_DCON_CH2_I2SSDO         (0<<24)
-#define S3C2410_DCON_CH2_I2SSDI         (1<<24)
-#define S3C2410_DCON_CH2_SDI            (2<<24)
-#define S3C2410_DCON_CH2_TIMER          (3<<24)
-#define S3C2410_DCON_CH2_USBEP3         (4<<24)
+#define S3C2410_DCON_CH2_I2SSDO         (0 << 24)
+#define S3C2410_DCON_CH2_I2SSDI         (1 << 24)
+#define S3C2410_DCON_CH2_SDI            (2 << 24)
+#define S3C2410_DCON_CH2_TIMER          (3 << 24)
+#define S3C2410_DCON_CH2_USBEP3         (4 << 24)
 
-#define S3C2410_DCON_CH3_UART2          (0<<24)
-#define S3C2410_DCON_CH3_SDI            (1<<24)
-#define S3C2410_DCON_CH3_SPI            (2<<24)
-#define S3C2410_DCON_CH3_TIMER          (3<<24)
-#define S3C2410_DCON_CH3_USBEP4         (4<<24)
+#define S3C2410_DCON_CH3_UART2          (0 << 24)
+#define S3C2410_DCON_CH3_SDI            (1 << 24)
+#define S3C2410_DCON_CH3_SPI            (2 << 24)
+#define S3C2410_DCON_CH3_TIMER          (3 << 24)
+#define S3C2410_DCON_CH3_USBEP4         (4 << 24)
 
 #define S3C2410_DCON_SRCSHIFT           (24)
-#define S3C2410_DCON_SRCMASK            (7<<24)
+#define S3C2410_DCON_SRCMASK            (7 << 24)
 
-#define S3C2410_DCON_BYTE               (0<<20)
-#define S3C2410_DCON_HALFWORD           (1<<20)
-#define S3C2410_DCON_WORD               (2<<20)
+#define S3C2410_DCON_BYTE               (0 << 20)
+#define S3C2410_DCON_HALFWORD           (1 << 20)
+#define S3C2410_DCON_WORD               (2 << 20)
 
-#define S3C2410_DCON_AUTORELOAD         (0<<22)
-#define S3C2410_DCON_NORELOAD           (1<<22)
-#define S3C2410_DCON_HWTRIG             (1<<23)
+#define S3C2410_DCON_AUTORELOAD         (0 << 22)
+#define S3C2410_DCON_NORELOAD           (1 << 22)
+#define S3C2410_DCON_HWTRIG             (1 << 23)
 
 #ifdef CONFIG_CPU_S3C2440
-#define S3C2440_DIDSTC_CHKINT           (1<<2)
 
-#define S3C2440_DCON_CH0_I2SSDO         (5<<24)
-#define S3C2440_DCON_CH0_PCMIN          (6<<24)
+#define S3C2440_DIDSTC_CHKINT           (1 << 2)
 
-#define S3C2440_DCON_CH1_PCMOUT         (5<<24)
-#define S3C2440_DCON_CH1_SDI            (6<<24)
+#define S3C2440_DCON_CH0_I2SSDO         (5 << 24)
+#define S3C2440_DCON_CH0_PCMIN          (6 << 24)
 
-#define S3C2440_DCON_CH2_PCMIN          (5<<24)
-#define S3C2440_DCON_CH2_MICIN          (6<<24)
+#define S3C2440_DCON_CH1_PCMOUT         (5 << 24)
+#define S3C2440_DCON_CH1_SDI            (6 << 24)
 
-#define S3C2440_DCON_CH3_MICIN          (5<<24)
-#define S3C2440_DCON_CH3_PCMOUT         (6<<24)
-#endif
+#define S3C2440_DCON_CH2_PCMIN          (5 << 24)
+#define S3C2440_DCON_CH2_MICIN          (6 << 24)
+
+#define S3C2440_DCON_CH3_MICIN          (5 << 24)
+#define S3C2440_DCON_CH3_PCMOUT         (6 << 24)
+#endif /* CONFIG_CPU_S3C2440 */
 
 #ifdef CONFIG_CPU_S3C2412
 
-#define S3C2412_DMAREQSEL_SRC(x)        ((x)<<1)
+#define S3C2412_DMAREQSEL_SRC(x)        ((x) << 1)
 
 #define S3C2412_DMAREQSEL_HW            (1)
 
@@ -115,10 +117,11 @@
 #define S3C2412_DMAREQSEL_UART1_1       S3C2412_DMAREQSEL_SRC(22)
 #define S3C2412_DMAREQSEL_UART2_0       S3C2412_DMAREQSEL_SRC(23)
 #define S3C2412_DMAREQSEL_UART2_1       S3C2412_DMAREQSEL_SRC(24)
+#endif /* CONFIG_CPU_S3C2412 */
 
-#endif
+#ifdef CONFIG_CPU_S3C2443
 
-#define S3C2443_DMAREQSEL_SRC(x)        ((x)<<1)
+#define S3C2443_DMAREQSEL_SRC(x)        ((x) << 1)
 
 #define S3C2443_DMAREQSEL_HW            (1)
 
@@ -141,5 +144,8 @@
 #define S3C2443_DMAREQSEL_UART3_0       S3C2443_DMAREQSEL_SRC(25)
 #define S3C2443_DMAREQSEL_UART3_1       S3C2443_DMAREQSEL_SRC(26)
 #define S3C2443_DMAREQSEL_PCMOUT        S3C2443_DMAREQSEL_SRC(27)
-#define S3C2443_DMAREQSEL_PCMIN         S3C2443_DMAREQSEL_SRC(28)
+#define S3C2443_DMAREQSEL_PCMIN         S3C2443_DMAREQSEL_SRC(28)
 #define S3C2443_DMAREQSEL_MICIN         S3C2443_DMAREQSEL_SRC(29)
+#endif /* CONFIG_CPU_S3C2443 */
+
+#endif /* __ASM_PLAT_REGS_DMA_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-iis.h b/arch/arm/plat-samsung/include/plat/regs-iis.h
new file mode 100644
index 000000000000..a18d35e7a735
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-iis.h
@@ -0,0 +1,70 @@
+/* arch/arm/plat-samsung/include/plat/regs-iis.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *                    http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 IIS register definition
+*/
+
+#ifndef __ASM_ARCH_REGS_IIS_H
+#define __ASM_ARCH_REGS_IIS_H
+
+#define S3C2410_IISCON                  (0x00)
+
+#define S3C2410_IISCON_LRINDEX          (1 << 8)
+#define S3C2410_IISCON_TXFIFORDY        (1 << 7)
+#define S3C2410_IISCON_RXFIFORDY        (1 << 6)
+#define S3C2410_IISCON_TXDMAEN          (1 << 5)
+#define S3C2410_IISCON_RXDMAEN          (1 << 4)
+#define S3C2410_IISCON_TXIDLE           (1 << 3)
+#define S3C2410_IISCON_RXIDLE           (1 << 2)
+#define S3C2410_IISCON_PSCEN            (1 << 1)
+#define S3C2410_IISCON_IISEN            (1 << 0)
+
+#define S3C2410_IISMOD                  (0x04)
+
+#define S3C2440_IISMOD_MPLL             (1 << 9)
+#define S3C2410_IISMOD_SLAVE            (1 << 8)
+#define S3C2410_IISMOD_NOXFER           (0 << 6)
+#define S3C2410_IISMOD_RXMODE           (1 << 6)
+#define S3C2410_IISMOD_TXMODE           (2 << 6)
+#define S3C2410_IISMOD_TXRXMODE         (3 << 6)
+#define S3C2410_IISMOD_LR_LLOW          (0 << 5)
+#define S3C2410_IISMOD_LR_RLOW          (1 << 5)
+#define S3C2410_IISMOD_IIS              (0 << 4)
+#define S3C2410_IISMOD_MSB              (1 << 4)
+#define S3C2410_IISMOD_8BIT             (0 << 3)
+#define S3C2410_IISMOD_16BIT            (1 << 3)
+#define S3C2410_IISMOD_BITMASK          (1 << 3)
+#define S3C2410_IISMOD_256FS            (0 << 2)
+#define S3C2410_IISMOD_384FS            (1 << 2)
+#define S3C2410_IISMOD_16FS             (0 << 0)
+#define S3C2410_IISMOD_32FS             (1 << 0)
+#define S3C2410_IISMOD_48FS             (2 << 0)
+#define S3C2410_IISMOD_FS_MASK          (3 << 0)
+
+#define S3C2410_IISPSR                  (0x08)
+
+#define S3C2410_IISPSR_INTMASK          (31 << 5)
+#define S3C2410_IISPSR_INTSHIFT         (5)
+#define S3C2410_IISPSR_EXTMASK          (31 << 0)
+#define S3C2410_IISPSR_EXTSHFIT         (0)
+
+#define S3C2410_IISFCON                 (0x0c)
+
+#define S3C2410_IISFCON_TXDMA           (1 << 15)
+#define S3C2410_IISFCON_RXDMA           (1 << 14)
+#define S3C2410_IISFCON_TXENABLE        (1 << 13)
+#define S3C2410_IISFCON_RXENABLE        (1 << 12)
+#define S3C2410_IISFCON_TXMASK          (0x3f << 6)
+#define S3C2410_IISFCON_TXSHIFT         (6)
+#define S3C2410_IISFCON_RXMASK          (0x3f)
+#define S3C2410_IISFCON_RXSHIFT         (0)
+
+#define S3C2410_IISFIFO                 (0x10)
+
+#endif /* __ASM_ARCH_REGS_IIS_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-spi.h b/arch/arm/plat-samsung/include/plat/regs-spi.h
new file mode 100644
index 000000000000..552fe7cfe281
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-spi.h
@@ -0,0 +1,48 @@
+/* arch/arm/plat-samsung/include/plat/regs-spi.h
+ *
+ * Copyright (c) 2004 Fetron GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 SPI register definition
+*/
+
+#ifndef __ASM_ARCH_REGS_SPI_H
+#define __ASM_ARCH_REGS_SPI_H
+
+#define S3C2410_SPI1            (0x20)
+#define S3C2412_SPI1            (0x100)
+
+#define S3C2410_SPCON           (0x00)
+
+#define S3C2410_SPCON_SMOD_DMA  (2 << 5)        /* DMA mode */
+#define S3C2410_SPCON_SMOD_INT  (1 << 5)        /* interrupt mode */
+#define S3C2410_SPCON_SMOD_POLL (0 << 5)        /* polling mode */
+#define S3C2410_SPCON_ENSCK     (1 << 4)        /* Enable SCK */
+#define S3C2410_SPCON_MSTR      (1 << 3)        /* Master:1, Slave:0 select */
+#define S3C2410_SPCON_CPOL_HIGH (1 << 2)        /* Clock polarity select */
+#define S3C2410_SPCON_CPOL_LOW  (0 << 2)        /* Clock polarity select */
+
+#define S3C2410_SPCON_CPHA_FMTB (1 << 1)        /* Clock Phase Select */
+#define S3C2410_SPCON_CPHA_FMTA (0 << 1)        /* Clock Phase Select */
+
+#define S3C2410_SPSTA           (0x04)
+
+#define S3C2410_SPSTA_DCOL      (1 << 2)        /* Data Collision Error */
+#define S3C2410_SPSTA_MULD      (1 << 1)        /* Multi Master Error */
+#define S3C2410_SPSTA_READY     (1 << 0)        /* Data Tx/Rx ready */
+#define S3C2412_SPSTA_READY_ORG (1 << 3)
+
+#define S3C2410_SPPIN           (0x08)
+
+#define S3C2410_SPPIN_ENMUL     (1 << 2)        /* Multi Master Error detect */
+#define S3C2410_SPPIN_RESERVED  (1 << 1)
+#define S3C2410_SPPIN_KEEP      (1 << 0)        /* Master Out keep */
+
+#define S3C2410_SPPRE           (0x0C)
+#define S3C2410_SPTDAT          (0x10)
+#define S3C2410_SPRDAT          (0x14)
+
+#endif /* __ASM_ARCH_REGS_SPI_H */
diff --git a/arch/arm/plat-s5p/include/plat/regs-srom.h b/arch/arm/plat-samsung/include/plat/regs-srom.h
index f121ab5e76cb..9b6729c81cda 100644
--- a/arch/arm/plat-s5p/include/plat/regs-srom.h
+++ b/arch/arm/plat-samsung/include/plat/regs-srom.h
@@ -1,4 +1,4 @@
-/* linux/arch/arm/plat-s5p/include/plat/regs-srom.h
+/* linux/arch/arm/plat-samsung/include/plat/regs-srom.h
  *
  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
@@ -10,8 +10,8 @@
  * published by the Free Software Foundation.
 */
 
-#ifndef __ASM_PLAT_S5P_REGS_SROM_H
-#define __ASM_PLAT_S5P_REGS_SROM_H __FILE__
+#ifndef __PLAT_SAMSUNG_REGS_SROM_H
+#define __PLAT_SAMSUNG_REGS_SROM_H __FILE__
 
 #include <mach/map.h>
 
@@ -51,4 +51,4 @@
 #define S5P_SROM_BCX__TCOS__SHIFT               24
 #define S5P_SROM_BCX__TACS__SHIFT               28
 
-#endif /* __ASM_PLAT_S5P_REGS_SROM_H */
+#endif /* __PLAT_SAMSUNG_REGS_SROM_H */
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-udc.h b/arch/arm/plat-samsung/include/plat/regs-udc.h
index f0dd4a41b37b..4003d3dab4e7 100644
--- a/arch/arm/plat-s3c24xx/include/plat/regs-udc.h
+++ b/arch/arm/plat-samsung/include/plat/regs-udc.h
@@ -1,4 +1,4 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-udc.h
+/* arch/arm/plat-samsung/include/plat/regs-udc.h
  *
  * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
  *
@@ -75,79 +75,77 @@
 #define S3C2410_UDC_OUT_FIFO_CNT1_REG   S3C2410_USBDREG(0x0198)
 #define S3C2410_UDC_OUT_FIFO_CNT2_REG   S3C2410_USBDREG(0x019c)
 
-#define S3C2410_UDC_FUNCADDR_UPDATE     (1<<7)
+#define S3C2410_UDC_FUNCADDR_UPDATE     (1 << 7)
 
-#define S3C2410_UDC_PWR_ISOUP           (1<<7) // R/W
-#define S3C2410_UDC_PWR_RESET           (1<<3) // R
-#define S3C2410_UDC_PWR_RESUME          (1<<2) // R/W
-#define S3C2410_UDC_PWR_SUSPEND         (1<<1) // R
-#define S3C2410_UDC_PWR_ENSUSPEND       (1<<0) // R/W
+#define S3C2410_UDC_PWR_ISOUP           (1 << 7) /* R/W */
+#define S3C2410_UDC_PWR_RESET           (1 << 3) /* R   */
+#define S3C2410_UDC_PWR_RESUME          (1 << 2) /* R/W */
+#define S3C2410_UDC_PWR_SUSPEND         (1 << 1) /* R   */
+#define S3C2410_UDC_PWR_ENSUSPEND       (1 << 0) /* R/W */
 
-#define S3C2410_UDC_PWR_DEFAULT         0x00
+#define S3C2410_UDC_PWR_DEFAULT         (0x00)
 
-#define S3C2410_UDC_INT_EP4             (1<<4) // R/W (clear only)
-#define S3C2410_UDC_INT_EP3             (1<<3) // R/W (clear only)
-#define S3C2410_UDC_INT_EP2             (1<<2) // R/W (clear only)
-#define S3C2410_UDC_INT_EP1             (1<<1) // R/W (clear only)
-#define S3C2410_UDC_INT_EP0             (1<<0) // R/W (clear only)
+#define S3C2410_UDC_INT_EP4             (1 << 4) /* R/W (clear only) */
+#define S3C2410_UDC_INT_EP3             (1 << 3) /* R/W (clear only) */
+#define S3C2410_UDC_INT_EP2             (1 << 2) /* R/W (clear only) */
+#define S3C2410_UDC_INT_EP1             (1 << 1) /* R/W (clear only) */
+#define S3C2410_UDC_INT_EP0             (1 << 0) /* R/W (clear only) */
 
-#define S3C2410_UDC_USBINT_RESET        (1<<2) // R/W (clear only)
-#define S3C2410_UDC_USBINT_RESUME       (1<<1) // R/W (clear only)
-#define S3C2410_UDC_USBINT_SUSPEND      (1<<0) // R/W (clear only)
+#define S3C2410_UDC_USBINT_RESET        (1 << 2) /* R/W (clear only) */
+#define S3C2410_UDC_USBINT_RESUME       (1 << 1) /* R/W (clear only) */
+#define S3C2410_UDC_USBINT_SUSPEND      (1 << 0) /* R/W (clear only) */
 
-#define S3C2410_UDC_INTE_EP4            (1<<4) // R/W
-#define S3C2410_UDC_INTE_EP3            (1<<3) // R/W
-#define S3C2410_UDC_INTE_EP2            (1<<2) // R/W
-#define S3C2410_UDC_INTE_EP1            (1<<1) // R/W
-#define S3C2410_UDC_INTE_EP0            (1<<0) // R/W
-
-#define S3C2410_UDC_USBINTE_RESET       (1<<2) // R/W
-#define S3C2410_UDC_USBINTE_SUSPEND     (1<<0) // R/W
+#define S3C2410_UDC_INTE_EP4            (1 << 4) /* R/W */
+#define S3C2410_UDC_INTE_EP3            (1 << 3) /* R/W */
+#define S3C2410_UDC_INTE_EP2            (1 << 2) /* R/W */
+#define S3C2410_UDC_INTE_EP1            (1 << 1) /* R/W */
+#define S3C2410_UDC_INTE_EP0            (1 << 0) /* R/W */
 
+#define S3C2410_UDC_USBINTE_RESET       (1 << 2) /* R/W */
+#define S3C2410_UDC_USBINTE_SUSPEND     (1 << 0) /* R/W */
 
 #define S3C2410_UDC_INDEX_EP0           (0x00)
-#define S3C2410_UDC_INDEX_EP1           (0x01) // ??
-#define S3C2410_UDC_INDEX_EP2           (0x02) // ??
-#define S3C2410_UDC_INDEX_EP3           (0x03) // ??
-#define S3C2410_UDC_INDEX_EP4           (0x04) // ??
-
-#define S3C2410_UDC_ICSR1_CLRDT         (1<<6) // R/W
-#define S3C2410_UDC_ICSR1_SENTSTL       (1<<5) // R/W (clear only)
-#define S3C2410_UDC_ICSR1_SENDSTL       (1<<4) // R/W
-#define S3C2410_UDC_ICSR1_FFLUSH        (1<<3) // W   (set only)
-#define S3C2410_UDC_ICSR1_UNDRUN        (1<<2) // R/W (clear only)
-#define S3C2410_UDC_ICSR1_PKTRDY        (1<<0) // R/W (set only)
-
-#define S3C2410_UDC_ICSR2_AUTOSET       (1<<7) // R/W
-#define S3C2410_UDC_ICSR2_ISO           (1<<6) // R/W
-#define S3C2410_UDC_ICSR2_MODEIN        (1<<5) // R/W
-#define S3C2410_UDC_ICSR2_DMAIEN        (1<<4) // R/W
-
-#define S3C2410_UDC_OCSR1_CLRDT         (1<<7) // R/W
-#define S3C2410_UDC_OCSR1_SENTSTL       (1<<6) // R/W (clear only)
-#define S3C2410_UDC_OCSR1_SENDSTL       (1<<5) // R/W
-#define S3C2410_UDC_OCSR1_FFLUSH        (1<<4) // R/W
-#define S3C2410_UDC_OCSR1_DERROR        (1<<3) // R
-#define S3C2410_UDC_OCSR1_OVRRUN        (1<<2) // R/W (clear only)
-#define S3C2410_UDC_OCSR1_PKTRDY        (1<<0) // R/W (clear only)
-
-#define S3C2410_UDC_OCSR2_AUTOCLR       (1<<7) // R/W
-#define S3C2410_UDC_OCSR2_ISO           (1<<6) // R/W
-#define S3C2410_UDC_OCSR2_DMAIEN        (1<<5) // R/W
-
-#define S3C2410_UDC_EP0_CSR_OPKRDY      (1<<0)
-#define S3C2410_UDC_EP0_CSR_IPKRDY      (1<<1)
-#define S3C2410_UDC_EP0_CSR_SENTSTL     (1<<2)
-#define S3C2410_UDC_EP0_CSR_DE          (1<<3)
-#define S3C2410_UDC_EP0_CSR_SE          (1<<4)
-#define S3C2410_UDC_EP0_CSR_SENDSTL     (1<<5)
-#define S3C2410_UDC_EP0_CSR_SOPKTRDY    (1<<6)
-#define S3C2410_UDC_EP0_CSR_SSE (1<<7)
-
-#define S3C2410_UDC_MAXP_8              (1<<0)
-#define S3C2410_UDC_MAXP_16             (1<<1)
-#define S3C2410_UDC_MAXP_32             (1<<2)
-#define S3C2410_UDC_MAXP_64             (1<<3)
-
+#define S3C2410_UDC_INDEX_EP1           (0x01)
+#define S3C2410_UDC_INDEX_EP2           (0x02)
+#define S3C2410_UDC_INDEX_EP3           (0x03)
+#define S3C2410_UDC_INDEX_EP4           (0x04)
+
+#define S3C2410_UDC_ICSR1_CLRDT         (1 << 6) /* R/W */
+#define S3C2410_UDC_ICSR1_SENTSTL       (1 << 5) /* R/W (clear only) */
+#define S3C2410_UDC_ICSR1_SENDSTL       (1 << 4) /* R/W */
+#define S3C2410_UDC_ICSR1_FFLUSH        (1 << 3) /* W   (set only) */
+#define S3C2410_UDC_ICSR1_UNDRUN        (1 << 2) /* R/W (clear only) */
+#define S3C2410_UDC_ICSR1_PKTRDY        (1 << 0) /* R/W (set only) */
+
+#define S3C2410_UDC_ICSR2_AUTOSET       (1 << 7) /* R/W */
+#define S3C2410_UDC_ICSR2_ISO           (1 << 6) /* R/W */
+#define S3C2410_UDC_ICSR2_MODEIN        (1 << 5) /* R/W */
+#define S3C2410_UDC_ICSR2_DMAIEN        (1 << 4) /* R/W */
+
+#define S3C2410_UDC_OCSR1_CLRDT         (1 << 7) /* R/W */
+#define S3C2410_UDC_OCSR1_SENTSTL       (1 << 6) /* R/W (clear only) */
+#define S3C2410_UDC_OCSR1_SENDSTL       (1 << 5) /* R/W */
+#define S3C2410_UDC_OCSR1_FFLUSH        (1 << 4) /* R/W */
+#define S3C2410_UDC_OCSR1_DERROR        (1 << 3) /* R   */
+#define S3C2410_UDC_OCSR1_OVRRUN        (1 << 2) /* R/W (clear only) */
+#define S3C2410_UDC_OCSR1_PKTRDY        (1 << 0) /* R/W (clear only) */
+
+#define S3C2410_UDC_OCSR2_AUTOCLR       (1 << 7) /* R/W */
+#define S3C2410_UDC_OCSR2_ISO           (1 << 6) /* R/W */
+#define S3C2410_UDC_OCSR2_DMAIEN        (1 << 5) /* R/W */
+
+#define S3C2410_UDC_EP0_CSR_OPKRDY      (1 << 0)
+#define S3C2410_UDC_EP0_CSR_IPKRDY      (1 << 1)
+#define S3C2410_UDC_EP0_CSR_SENTSTL     (1 << 2)
+#define S3C2410_UDC_EP0_CSR_DE          (1 << 3)
+#define S3C2410_UDC_EP0_CSR_SE          (1 << 4)
+#define S3C2410_UDC_EP0_CSR_SENDSTL     (1 << 5)
+#define S3C2410_UDC_EP0_CSR_SOPKTRDY    (1 << 6)
+#define S3C2410_UDC_EP0_CSR_SSE         (1 << 7)
+
+#define S3C2410_UDC_MAXP_8              (1 << 0)
+#define S3C2410_UDC_MAXP_16             (1 << 1)
+#define S3C2410_UDC_MAXP_32             (1 << 2)
+#define S3C2410_UDC_MAXP_64             (1 << 3)
 
 #endif
diff --git a/arch/arm/plat-s5p/include/plat/reset.h b/arch/arm/plat-samsung/include/plat/reset.h
index 335e97812eed..32ca5179c6e1 100644
--- a/arch/arm/plat-s5p/include/plat/reset.h
+++ b/arch/arm/plat-samsung/include/plat/reset.h
@@ -1,4 +1,4 @@
-/* linux/arch/arm/plat-s5p/include/plat/reset.h
+/* linux/arch/arm/plat-samsung/include/plat/reset.h
  *
  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com/
@@ -8,9 +8,9 @@
  * published by the Free Software Foundation.
 */
 
-#ifndef __ASM_PLAT_S5P_RESET_H
-#define __ASM_PLAT_S5P_RESET_H __FILE__
+#ifndef __PLAT_SAMSUNG_RESET_H
+#define __PLAT_SAMSUNG_RESET_H __FILE__
 
 extern void (*s5p_reset_hook)(void);
 
-#endif /* __ASM_PLAT_S5P_RESET_H */
+#endif /* __PLAT_SAMSUNG_RESET_H */
diff --git a/arch/arm/plat-samsung/include/plat/s3c-pl330-pdata.h b/arch/arm/plat-samsung/include/plat/s3c-pl330-pdata.h
deleted file mode 100644
index bf5e2a9d408d..000000000000
--- a/arch/arm/plat-samsung/include/plat/s3c-pl330-pdata.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/s3c-pl330-pdata.h
- *
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef __S3C_PL330_PDATA_H
-#define __S3C_PL330_PDATA_H
-
-#include <plat/s3c-dma-pl330.h>
-
-/*
- * Every PL330 DMAC has max 32 peripheral interfaces,
- * of which some may be not be really used in your
- * DMAC's configuration.
- * Populate this array of 32 peri i/fs with relevant
- * channel IDs for used peri i/f and DMACH_MAX for
- * those unused.
- *
- * The platforms just need to provide this info
- * to the S3C DMA API driver for PL330.
- */
-struct s3c_pl330_platdata {
-        enum dma_ch peri[32];
-};
-
-#endif /* __S3C_PL330_PDATA_H */
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2410.h b/arch/arm/plat-samsung/include/plat/s3c2410.h
index 82ab4aad1bbe..3986497dd3f7 100644
--- a/arch/arm/plat-s3c24xx/include/plat/s3c2410.h
+++ b/arch/arm/plat-samsung/include/plat/s3c2410.h
@@ -1,4 +1,4 @@
-/* linux/include/asm-arm/plat-s3c24xx/s3c2410.h
+/* linux/arch/arm/plat-samsung/include/plat/s3c2410.h
  *
  * Copyright (c) 2004 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2412.h b/arch/arm/plat-samsung/include/plat/s3c2412.h
index bb15d3b68be5..5bcfd143ba16 100644
--- a/arch/arm/plat-s3c24xx/include/plat/s3c2412.h
+++ b/arch/arm/plat-samsung/include/plat/s3c2412.h
@@ -1,4 +1,4 @@
-/* linux/include/asm-arm/plat-s3c24xx/s3c2412.h
+/* linux/arch/arm/plat-samsung/include/plat/s3c2412.h
  *
  * Copyright (c) 2006 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2416.h b/arch/arm/plat-samsung/include/plat/s3c2416.h
index dc3c0907d221..a764f8503f52 100644
--- a/arch/arm/plat-s3c24xx/include/plat/s3c2416.h
+++ b/arch/arm/plat-samsung/include/plat/s3c2416.h
@@ -1,4 +1,4 @@
-/* linux/include/asm-arm/plat-s3c24xx/s3c2443.h
+/* linux/arch/arm/plat-samsung/include/plat/s3c2416.h
  *
  * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>
  *
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2443.h b/arch/arm/plat-samsung/include/plat/s3c2443.h
index a19715feb798..4b2ac9a272b2 100644
--- a/arch/arm/plat-s3c24xx/include/plat/s3c2443.h
+++ b/arch/arm/plat-samsung/include/plat/s3c2443.h
@@ -1,4 +1,4 @@
-/* linux/include/asm-arm/plat-s3c24xx/s3c2443.h
+/* linux/arch/arm/plat-samsung/include/plat/s3c2443.h
  *
  * Copyright (c) 2004-2005 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c244x.h b/arch/arm/plat-samsung/include/plat/s3c244x.h
index 89e8d0a25f87..ea0c961b7603 100644
--- a/arch/arm/plat-s3c24xx/include/plat/s3c244x.h
+++ b/arch/arm/plat-samsung/include/plat/s3c244x.h
@@ -1,4 +1,4 @@
-/* linux/arch/arm/plat-s3c24xx/include/plat/s3c244x.h
+/* linux/arch/arm/plat-samsung/include/plat/s3c244x.h
  *
  * Copyright (c) 2004-2005 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
diff --git a/arch/arm/mach-s3c64xx/include/mach/s3c6400.h b/arch/arm/plat-samsung/include/plat/s3c6400.h
index f86958d05352..37d428aaaebb 100644
--- a/arch/arm/mach-s3c64xx/include/mach/s3c6400.h
+++ b/arch/arm/plat-samsung/include/plat/s3c6400.h
@@ -1,4 +1,4 @@
-/* arch/arm/mach-s3c64xx/include/macht/s3c6400.h
+/* linux/arch/arm/plat-samsung/include/plat/s3c6400.h
  *
  * Copyright 2008 Openmoko, Inc.
  * Copyright 2008 Simtec Electronics
diff --git a/arch/arm/mach-s3c64xx/include/mach/s3c6410.h b/arch/arm/plat-samsung/include/plat/s3c6410.h
index 24f1141ffcb7..20a6675b9d17 100644
--- a/arch/arm/mach-s3c64xx/include/mach/s3c6410.h
+++ b/arch/arm/plat-samsung/include/plat/s3c6410.h
@@ -1,4 +1,4 @@
-/* arch/arm/mach-s3c64xx/include/mach/s3c6410.h
+/* linux/arch/arm/plat-samsung/include/plat/s3c6410.h
  *
  * Copyright 2008 Openmoko,  Inc.
  * Copyright 2008 Simtec Electronics
diff --git a/arch/arm/plat-s5p/include/plat/s5p-clock.h b/arch/arm/plat-samsung/include/plat/s5p-clock.h
index 769b5bdfb046..984bf9e7bc89 100644
--- a/arch/arm/plat-s5p/include/plat/s5p-clock.h
+++ b/arch/arm/plat-samsung/include/plat/s5p-clock.h
@@ -1,4 +1,4 @@
-/* linux/arch/arm/plat-s5p/include/plat/s5p-clock.h
+/* linux/arch/arm/plat-samsung/include/plat/s5p-clock.h
  *
  * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
diff --git a/arch/arm/plat-s5p/include/plat/s5p-time.h b/arch/arm/plat-samsung/include/plat/s5p-time.h
index 575e88109db8..3a70aebc9205 100644
--- a/arch/arm/plat-s5p/include/plat/s5p-time.h
+++ b/arch/arm/plat-samsung/include/plat/s5p-time.h
@@ -1,4 +1,4 @@
-/* linux/arch/arm/plat-s5p/include/plat/s5p-time.h
+/* linux/arch/arm/plat-samsung/include/plat/s5p-time.h
  *
  * Copyright 2011 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com/
diff --git a/arch/arm/plat-s5p/include/plat/s5p6440.h b/arch/arm/plat-samsung/include/plat/s5p6440.h
index 528585d2cafc..bf85ebbb4fbc 100644
--- a/arch/arm/plat-s5p/include/plat/s5p6440.h
+++ b/arch/arm/plat-samsung/include/plat/s5p6440.h
@@ -1,4 +1,4 @@
-/* arch/arm/plat-s5p/include/plat/s5p6440.h
+/* linux/arch/arm/plat-samsung/include/plat/s5p6440.h
  *
  * Copyright (c) 2009 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com/
diff --git a/arch/arm/plat-s5p/include/plat/s5p6450.h b/arch/arm/plat-samsung/include/plat/s5p6450.h
index 640a41c26be3..da25f9a1c54a 100644
--- a/arch/arm/plat-s5p/include/plat/s5p6450.h
+++ b/arch/arm/plat-samsung/include/plat/s5p6450.h
@@ -1,4 +1,4 @@
-/* arch/arm/plat-s5p/include/plat/s5p6450.h
+/* linux/arch/arm/plat-samsung/include/plat/s5p6450.h
  *
  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
diff --git a/arch/arm/plat-s5p/include/plat/s5pc100.h b/arch/arm/plat-samsung/include/plat/s5pc100.h
index 5f6099dd7cad..9a21aeaaf452 100644
--- a/arch/arm/plat-s5p/include/plat/s5pc100.h
+++ b/arch/arm/plat-samsung/include/plat/s5pc100.h
@@ -1,4 +1,4 @@
-/* arch/arm/plat-s5p/include/plat/s5pc100.h
+/* linux/arch/arm/plat-samsung/include/plat/s5pc100.h
  *
  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com/
diff --git a/arch/arm/plat-s5p/include/plat/s5pv210.h b/arch/arm/plat-samsung/include/plat/s5pv210.h
index 6c93a0c78100..b4bc6be77072 100644
--- a/arch/arm/plat-s5p/include/plat/s5pv210.h
+++ b/arch/arm/plat-samsung/include/plat/s5pv210.h
@@ -1,4 +1,4 @@
-/* linux/arch/arm/plat-s5p/include/plat/s5pv210.h
+/* linux/arch/arm/plat-samsung/include/plat/s5pv210.h
  *
  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com/
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 058e09654fe8..e7b3c752e919 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -55,10 +55,6 @@ enum clk_types {
  *               cd_type == S3C_SDHCI_CD_GPIO
  * @ext_cd_gpio_invert: invert values for external CD gpio line
  * @cfg_gpio: Configure the GPIO for a specific card bit-width
- * @cfg_card: Configure the interface for a specific card and speed. This
- *            is necessary the controllers and/or GPIO blocks require the
- *            changing of driver-strength and other controls dependent on
- *            the card and speed of operation.
  *
  * Initialisation data specific to either the machine or the platform
  * for the device driver to use or call-back when configuring gpio or
@@ -80,12 +76,15 @@ struct s3c_sdhci_platdata {
                                                       int state));
 
         void    (*cfg_gpio)(struct platform_device *dev, int width);
-        void    (*cfg_card)(struct platform_device *dev,
-                            void __iomem *regbase,
-                            struct mmc_ios *ios,
-                            struct mmc_card *card);
 };
 
+/* s3c_sdhci_set_platdata() - common helper for setting SDHCI platform data
+ * @pd: The default platform data for this device.
+ * @set: Pointer to the platform data to fill in.
+ */
+extern void s3c_sdhci_set_platdata(struct s3c_sdhci_platdata *pd,
+                                    struct s3c_sdhci_platdata *set);
+
 /**
  * s3c_sdhci0_set_platdata - Set platform data for S3C SDHCI device.
  * @pd: Platform data to register to device.
@@ -132,17 +131,11 @@ extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
 #ifdef CONFIG_S3C2416_SETUP_SDHCI
 extern char *s3c2416_hsmmc_clksrcs[4];
 
-extern void s3c2416_setup_sdhci_cfg_card(struct platform_device *dev,
-                                           void __iomem *r,
-                                           struct mmc_ios *ios,
-                                           struct mmc_card *card);
-
 static inline void s3c2416_default_sdhci0(void)
 {
 #ifdef CONFIG_S3C_DEV_HSMMC
         s3c_hsmmc0_def_platdata.clocks = s3c2416_hsmmc_clksrcs;
         s3c_hsmmc0_def_platdata.cfg_gpio = s3c2416_setup_sdhci0_cfg_gpio;
-        s3c_hsmmc0_def_platdata.cfg_card = s3c2416_setup_sdhci_cfg_card;
 #endif /* CONFIG_S3C_DEV_HSMMC */
 }
 
@@ -151,7 +144,6 @@ static inline void s3c2416_default_sdhci1(void)
 #ifdef CONFIG_S3C_DEV_HSMMC1
         s3c_hsmmc1_def_platdata.clocks = s3c2416_hsmmc_clksrcs;
         s3c_hsmmc1_def_platdata.cfg_gpio = s3c2416_setup_sdhci1_cfg_gpio;
-        s3c_hsmmc1_def_platdata.cfg_card = s3c2416_setup_sdhci_cfg_card;
 #endif /* CONFIG_S3C_DEV_HSMMC1 */
 }
 
@@ -165,17 +157,11 @@ static inline void s3c2416_default_sdhci1(void) { }
 #ifdef CONFIG_S3C64XX_SETUP_SDHCI
 extern char *s3c64xx_hsmmc_clksrcs[4];
 
-extern void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,
-                                         void __iomem *r,
-                                         struct mmc_ios *ios,
-                                         struct mmc_card *card);
-
 static inline void s3c6400_default_sdhci0(void)
 {
 #ifdef CONFIG_S3C_DEV_HSMMC
         s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
         s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
-        s3c_hsmmc0_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
 #endif
 }
 
@@ -184,7 +170,6 @@ static inline void s3c6400_default_sdhci1(void)
 #ifdef CONFIG_S3C_DEV_HSMMC1
         s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
         s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
-        s3c_hsmmc1_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
 #endif
 }
 
@@ -193,21 +178,14 @@ static inline void s3c6400_default_sdhci2(void)
 #ifdef CONFIG_S3C_DEV_HSMMC2
         s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
         s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
-        s3c_hsmmc2_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
 #endif
 }
 
-extern void s3c6410_setup_sdhci_cfg_card(struct platform_device *dev,
-                                         void __iomem *r,
-                                         struct mmc_ios *ios,
-                                         struct mmc_card *card);
-
 static inline void s3c6410_default_sdhci0(void)
 {
 #ifdef CONFIG_S3C_DEV_HSMMC
         s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
         s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
-        s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card;
 #endif
 }
 
@@ -216,7 +194,6 @@ static inline void s3c6410_default_sdhci1(void)
 #ifdef CONFIG_S3C_DEV_HSMMC1
         s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
         s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
-        s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card;
 #endif
 }
 
@@ -225,7 +202,6 @@ static inline void s3c6410_default_sdhci2(void)
 #ifdef CONFIG_S3C_DEV_HSMMC2
         s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
         s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
-        s3c_hsmmc2_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card;
 #endif
 }
 
@@ -244,17 +220,11 @@ static inline void s3c6400_default_sdhci2(void) { }
 #ifdef CONFIG_S5PC100_SETUP_SDHCI
 extern char *s5pc100_hsmmc_clksrcs[4];
 
-extern void s5pc100_setup_sdhci0_cfg_card(struct platform_device *dev,
-                                           void __iomem *r,
-                                           struct mmc_ios *ios,
-                                           struct mmc_card *card);
-
 static inline void s5pc100_default_sdhci0(void)
 {
 #ifdef CONFIG_S3C_DEV_HSMMC
         s3c_hsmmc0_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
         s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio;
-        s3c_hsmmc0_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card;
 #endif
 }
 
@@ -263,7 +233,6 @@ static inline void s5pc100_default_sdhci1(void)
 #ifdef CONFIG_S3C_DEV_HSMMC1
         s3c_hsmmc1_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
         s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio;
-        s3c_hsmmc1_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card;
 #endif
 }
 
@@ -272,7 +241,6 @@ static inline void s5pc100_default_sdhci2(void)
 #ifdef CONFIG_S3C_DEV_HSMMC2
         s3c_hsmmc2_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
         s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio;
-        s3c_hsmmc2_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card;
 #endif
 }
 
@@ -288,17 +256,11 @@ static inline void s5pc100_default_sdhci2(void) { }
 #ifdef CONFIG_S5PV210_SETUP_SDHCI
 extern char *s5pv210_hsmmc_clksrcs[4];
 
-extern void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev,
-                                           void __iomem *r,
-                                           struct mmc_ios *ios,
-                                           struct mmc_card *card);
-
 static inline void s5pv210_default_sdhci0(void)
 {
 #ifdef CONFIG_S3C_DEV_HSMMC
         s3c_hsmmc0_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
         s3c_hsmmc0_def_platdata.cfg_gpio = s5pv210_setup_sdhci0_cfg_gpio;
-        s3c_hsmmc0_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card;
 #endif
 }
 
@@ -307,7 +269,6 @@ static inline void s5pv210_default_sdhci1(void)
 #ifdef CONFIG_S3C_DEV_HSMMC1
         s3c_hsmmc1_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
         s3c_hsmmc1_def_platdata.cfg_gpio = s5pv210_setup_sdhci1_cfg_gpio;
-        s3c_hsmmc1_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card;
 #endif
 }
 
@@ -316,7 +277,6 @@ static inline void s5pv210_default_sdhci2(void)
 #ifdef CONFIG_S3C_DEV_HSMMC2
         s3c_hsmmc2_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
         s3c_hsmmc2_def_platdata.cfg_gpio = s5pv210_setup_sdhci2_cfg_gpio;
-        s3c_hsmmc2_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card;
 #endif
 }
 
@@ -325,7 +285,6 @@ static inline void s5pv210_default_sdhci3(void)
 #ifdef CONFIG_S3C_DEV_HSMMC3
         s3c_hsmmc3_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
         s3c_hsmmc3_def_platdata.cfg_gpio = s5pv210_setup_sdhci3_cfg_gpio;
-        s3c_hsmmc3_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card;
 #endif
 }
 
@@ -341,17 +300,11 @@ static inline void s5pv210_default_sdhci3(void) { }
 #ifdef CONFIG_EXYNOS4_SETUP_SDHCI
 extern char *exynos4_hsmmc_clksrcs[4];
 
-extern void exynos4_setup_sdhci_cfg_card(struct platform_device *dev,
-                                           void __iomem *r,
-                                           struct mmc_ios *ios,
-                                           struct mmc_card *card);
-
 static inline void exynos4_default_sdhci0(void)
 {
 #ifdef CONFIG_S3C_DEV_HSMMC
         s3c_hsmmc0_def_platdata.clocks = exynos4_hsmmc_clksrcs;
         s3c_hsmmc0_def_platdata.cfg_gpio = exynos4_setup_sdhci0_cfg_gpio;
-        s3c_hsmmc0_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
 #endif
 }
 
@@ -360,7 +313,6 @@ static inline void exynos4_default_sdhci1(void)
 #ifdef CONFIG_S3C_DEV_HSMMC1
         s3c_hsmmc1_def_platdata.clocks = exynos4_hsmmc_clksrcs;
         s3c_hsmmc1_def_platdata.cfg_gpio = exynos4_setup_sdhci1_cfg_gpio;
-        s3c_hsmmc1_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
 #endif
 }
 
@@ -369,7 +321,6 @@ static inline void exynos4_default_sdhci2(void)
 #ifdef CONFIG_S3C_DEV_HSMMC2
         s3c_hsmmc2_def_platdata.clocks = exynos4_hsmmc_clksrcs;
         s3c_hsmmc2_def_platdata.cfg_gpio = exynos4_setup_sdhci2_cfg_gpio;
-        s3c_hsmmc2_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
 #endif
 }
 
@@ -378,7 +329,6 @@ static inline void exynos4_default_sdhci3(void)
 #ifdef CONFIG_S3C_DEV_HSMMC3
         s3c_hsmmc3_def_platdata.clocks = exynos4_hsmmc_clksrcs;
         s3c_hsmmc3_def_platdata.cfg_gpio = exynos4_setup_sdhci3_cfg_gpio;
-        s3c_hsmmc3_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
 #endif
 }
 
diff --git a/arch/arm/plat-s5p/include/plat/sysmmu.h b/arch/arm/plat-samsung/include/plat/sysmmu.h
index bf5283c2a19d..5fe8ee01a5ba 100644
--- a/arch/arm/plat-s5p/include/plat/sysmmu.h
+++ b/arch/arm/plat-samsung/include/plat/sysmmu.h
@@ -1,4 +1,4 @@
-/* linux/arch/arm/plat-s5p/include/plat/sysmmu.h
+/* linux/arch/arm/plat-samsung/include/plat/sysmmu.h
  *
  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
@@ -10,8 +10,8 @@
  * published by the Free Software Foundation.
 */
 
-#ifndef __ASM__PLAT_SYSMMU_H
-#define __ASM__PLAT_SYSMMU_H __FILE__
+#ifndef __PLAT_SAMSUNG_SYSMMU_H
+#define __PLAT_SAMSUNG_SYSMMU_H __FILE__
 
 enum S5P_SYSMMU_INTERRUPT_TYPE {
         SYSMMU_PAGEFAULT,
diff --git a/arch/arm/plat-s5p/include/plat/system-reset.h b/arch/arm/plat-samsung/include/plat/system-reset.h
index f307f34e6422..a448e990964d 100644
--- a/arch/arm/plat-s5p/include/plat/system-reset.h
+++ b/arch/arm/plat-samsung/include/plat/system-reset.h
@@ -1,4 +1,4 @@
-/* linux/arch/arm/plat-s5p/include/plat/system-reset.h
+/* linux/arch/arm/plat-samsung/include/plat/system-reset.h
  *
  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
diff --git a/arch/arm/plat-samsung/include/plat/tv-core.h b/arch/arm/plat-samsung/include/plat/tv-core.h
new file mode 100644
index 000000000000..3bc34f3ce28f
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/tv-core.h
@@ -0,0 +1,44 @@
+/*
+ * arch/arm/plat-samsung/include/plat/tv.h
+ *
+ * Copyright 2011 Samsung Electronics Co., Ltd.
+ *      Tomasz Stanislawski <t.stanislaws@samsung.com>
+ *
+ * Samsung TV driver core functions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __SAMSUNG_PLAT_TV_H
+#define __SAMSUNG_PLAT_TV_H __FILE__
+
+/*
+ * These functions are only for use with the core support code, such as
+ * the CPU-specific initialization code.
+ */
+
+/* Re-define device name to differentiate the subsystem in various SoCs. */
+static inline void s5p_hdmi_setname(char *name)
+{
+#ifdef CONFIG_S5P_DEV_TV
+        s5p_device_hdmi.name = name;
+#endif
+}
+
+static inline void s5p_mixer_setname(char *name)
+{
+#ifdef CONFIG_S5P_DEV_TV
+        s5p_device_mixer.name = name;
+#endif
+}
+
+static inline void s5p_sdo_setname(char *name)
+{
+#ifdef CONFIG_S5P_DEV_TV
+        s5p_device_sdo.name = name;
+#endif
+}
+
+#endif /* __SAMSUNG_PLAT_TV_H */
diff --git a/arch/arm/plat-s3c24xx/include/plat/udc.h b/arch/arm/plat-samsung/include/plat/udc.h
index f63884242506..8c22d586befb 100644
--- a/arch/arm/plat-s3c24xx/include/plat/udc.h
+++ b/arch/arm/plat-samsung/include/plat/udc.h
@@ -1,4 +1,4 @@
-/* arch/arm/mach-s3c2410/include/mach/udc.h
+/* arch/arm/plat-samsung/include/plat/udc.h
  *
  * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org>
  *
@@ -26,7 +26,7 @@ enum s3c2410_udc_cmd_e {
 
 struct s3c2410_udc_mach_info {
         void    (*udc_command)(enum s3c2410_udc_cmd_e);
-        void    (*vbus_draw)(unsigned int ma);
+        void    (*vbus_draw)(unsigned int ma);
 
         unsigned int pullup_pin;
         unsigned int pullup_pin_inverted;
diff --git a/arch/arm/plat-s5p/include/plat/usb-phy.h b/arch/arm/plat-samsung/include/plat/usb-phy.h
index 6dd6bcfca3ce..959bcdb03a25 100644
--- a/arch/arm/plat-s5p/include/plat/usb-phy.h
+++ b/arch/arm/plat-samsung/include/plat/usb-phy.h
@@ -8,8 +8,8 @@
  * option) any later version.
  */
 
-#ifndef __PLAT_S5P_USB_PHY_H
-#define __PLAT_S5P_USB_PHY_H
+#ifndef __PLAT_SAMSUNG_USB_PHY_H
+#define __PLAT_SAMSUNG_USB_PHY_H __FILE__
 
 enum s5p_usb_phy_type {
         S5P_USB_PHY_DEVICE,
@@ -19,4 +19,4 @@ enum s5p_usb_phy_type {
 extern int s5p_usb_phy_init(struct platform_device *pdev, int type);
 extern int s5p_usb_phy_exit(struct platform_device *pdev, int type);
 
-#endif /* __PLAT_S5P_REGS_USB_PHY_H */
+#endif /* __PLAT_SAMSUNG_USB_PHY_H */
diff --git a/arch/arm/plat-samsung/include/plat/watchdog-reset.h b/arch/arm/plat-samsung/include/plat/watchdog-reset.h
index 54b762acb5a0..40dbb2b0ae22 100644
--- a/arch/arm/plat-samsung/include/plat/watchdog-reset.h
+++ b/arch/arm/plat-samsung/include/plat/watchdog-reset.h
@@ -10,6 +10,7 @@
  * published by the Free Software Foundation.
 */
 
+#include <plat/clock.h>
 #include <plat/regs-watchdog.h>
 #include <mach/map.h>
 
@@ -19,17 +20,12 @@
 
 static inline void arch_wdt_reset(void)
 {
-        struct clk *wdtclk;
-
         printk("arch_reset: attempting watchdog reset\n");
 
         __raw_writel(0, S3C2410_WTCON);   /* disable watchdog, to be safe  */
 
-        wdtclk = clk_get(NULL, "watchdog");
-        if (!IS_ERR(wdtclk)) {
-                clk_enable(wdtclk);
-        } else
-                printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
+        if (s3c2410_wdtclk)
+                clk_enable(s3c2410_wdtclk);
 
         /* put initial values into count and data */
         __raw_writel(0x80, S3C2410_WTCNT);
diff --git a/arch/arm/plat-samsung/platformdata.c b/arch/arm/plat-samsung/platformdata.c
index 7cf2e1e3b20f..4c9a20734fe3 100644
--- a/arch/arm/plat-samsung/platformdata.c
+++ b/arch/arm/plat-samsung/platformdata.c
@@ -14,6 +14,7 @@
 #include <linux/platform_device.h>
 
 #include <plat/devs.h>
+#include <plat/sdhci.h>
 
 void __init *s3c_set_platdata(void *pd, size_t pdsize,
                               struct platform_device *pdev)
@@ -35,3 +36,22 @@ void __init *s3c_set_platdata(void *pd, size_t pdsize,
         pdev->dev.platform_data = npd;
         return npd;
 }
+
+void s3c_sdhci_set_platdata(struct s3c_sdhci_platdata *pd,
+                             struct s3c_sdhci_platdata *set)
+{
+        set->cd_type = pd->cd_type;
+        set->ext_cd_init = pd->ext_cd_init;
+        set->ext_cd_cleanup = pd->ext_cd_cleanup;
+        set->ext_cd_gpio = pd->ext_cd_gpio;
+        set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
+
+        if (pd->max_width)
+                set->max_width = pd->max_width;
+        if (pd->cfg_gpio)
+                set->cfg_gpio = pd->cfg_gpio;
+        if (pd->host_caps)
+                set->host_caps |= pd->host_caps;
+        if (pd->clk_type)
+                set->clk_type = pd->clk_type;
+}
diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c
index 96528200eb79..4be016eaa6db 100644
--- a/arch/arm/plat-samsung/pm-gpio.c
+++ b/arch/arm/plat-samsung/pm-gpio.c
@@ -28,13 +28,13 @@
 #define OFFS_DAT        (0x04)
 #define OFFS_UP         (0x08)
 
-static void s3c_gpio_pm_1bit_save(struct s3c_gpio_chip *chip)
+static void samsung_gpio_pm_1bit_save(struct samsung_gpio_chip *chip)
 {
         chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
         chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
 }
 
-static void s3c_gpio_pm_1bit_resume(struct s3c_gpio_chip *chip)
+static void samsung_gpio_pm_1bit_resume(struct samsung_gpio_chip *chip)
 {
         void __iomem *base = chip->base;
         u32 old_gpcon = __raw_readl(base + OFFS_CON);
@@ -60,12 +60,12 @@ static void s3c_gpio_pm_1bit_resume(struct s3c_gpio_chip *chip)
                   chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
 }
 
-struct s3c_gpio_pm s3c_gpio_pm_1bit = {
-        .save   = s3c_gpio_pm_1bit_save,
-        .resume = s3c_gpio_pm_1bit_resume,
+struct samsung_gpio_pm samsung_gpio_pm_1bit = {
+        .save   = samsung_gpio_pm_1bit_save,
+        .resume = samsung_gpio_pm_1bit_resume,
 };
 
-static void s3c_gpio_pm_2bit_save(struct s3c_gpio_chip *chip)
+static void samsung_gpio_pm_2bit_save(struct samsung_gpio_chip *chip)
 {
         chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
         chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
@@ -95,7 +95,7 @@ static inline int is_out(unsigned long con)
 }
 
 /**
- * s3c_gpio_pm_2bit_resume() - restore the given GPIO bank
+ * samsung_gpio_pm_2bit_resume() - restore the given GPIO bank
  * @chip: The chip information to resume.
  *
  * Restore one of the GPIO banks that was saved during suspend. This is
@@ -121,7 +121,7 @@ static inline int is_out(unsigned long con)
  * [1] this assumes that writing to a pin DAT whilst in SFN will set the
  *     state for when it is next output.
  */
-static void s3c_gpio_pm_2bit_resume(struct s3c_gpio_chip *chip)
+static void samsung_gpio_pm_2bit_resume(struct samsung_gpio_chip *chip)
 {
         void __iomem *base = chip->base;
         u32 old_gpcon = __raw_readl(base + OFFS_CON);
@@ -187,13 +187,13 @@ static void s3c_gpio_pm_2bit_resume(struct s3c_gpio_chip *chip)
                   chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
 }
 
-struct s3c_gpio_pm s3c_gpio_pm_2bit = {
-        .save   = s3c_gpio_pm_2bit_save,
-        .resume = s3c_gpio_pm_2bit_resume,
+struct samsung_gpio_pm samsung_gpio_pm_2bit = {
+        .save   = samsung_gpio_pm_2bit_save,
+        .resume = samsung_gpio_pm_2bit_resume,
 };
 
 #if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P)
-static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip)
+static void samsung_gpio_pm_4bit_save(struct samsung_gpio_chip *chip)
 {
         chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
         chip->pm_save[2] = __raw_readl(chip->base + OFFS_DAT);
@@ -203,7 +203,7 @@ static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip)
                 chip->pm_save[0] = __raw_readl(chip->base - 4);
 }
 
-static u32 s3c_gpio_pm_4bit_mask(u32 old_gpcon, u32 gps_gpcon)
+static u32 samsung_gpio_pm_4bit_mask(u32 old_gpcon, u32 gps_gpcon)
 {
         u32 old, new, mask;
         u32 change_mask = 0x0;
@@ -242,14 +242,14 @@ static u32 s3c_gpio_pm_4bit_mask(u32 old_gpcon, u32 gps_gpcon)
         return change_mask;
 }
 
-static void s3c_gpio_pm_4bit_con(struct s3c_gpio_chip *chip, int index)
+static void samsung_gpio_pm_4bit_con(struct samsung_gpio_chip *chip, int index)
 {
         void __iomem *con = chip->base + (index * 4);
         u32 old_gpcon = __raw_readl(con);
         u32 gps_gpcon = chip->pm_save[index + 1];
         u32 gpcon, mask;
 
-        mask = s3c_gpio_pm_4bit_mask(old_gpcon, gps_gpcon);
+        mask = samsung_gpio_pm_4bit_mask(old_gpcon, gps_gpcon);
 
         gpcon = old_gpcon & ~mask;
         gpcon |= gps_gpcon & mask;
@@ -257,7 +257,7 @@ static void s3c_gpio_pm_4bit_con(struct s3c_gpio_chip *chip, int index)
         __raw_writel(gpcon, con);
 }
 
-static void s3c_gpio_pm_4bit_resume(struct s3c_gpio_chip *chip)
+static void samsung_gpio_pm_4bit_resume(struct samsung_gpio_chip *chip)
 {
         void __iomem *base = chip->base;
         u32 old_gpcon[2];
@@ -269,10 +269,10 @@ static void s3c_gpio_pm_4bit_resume(struct s3c_gpio_chip *chip)
         old_gpcon[0] = 0;
         old_gpcon[1] = __raw_readl(base + OFFS_CON);
 
-        s3c_gpio_pm_4bit_con(chip, 0);
+        samsung_gpio_pm_4bit_con(chip, 0);
         if (chip->chip.ngpio > 8) {
                 old_gpcon[0] = __raw_readl(base - 4);
-                s3c_gpio_pm_4bit_con(chip, -1);
+                samsung_gpio_pm_4bit_con(chip, -1);
         }
 
         /* Now change the configurations that require DAT,CON */
@@ -298,19 +298,19 @@ static void s3c_gpio_pm_4bit_resume(struct s3c_gpio_chip *chip)
                           old_gpdat, gps_gpdat);
 }
 
-struct s3c_gpio_pm s3c_gpio_pm_4bit = {
-        .save   = s3c_gpio_pm_4bit_save,
-        .resume = s3c_gpio_pm_4bit_resume,
+struct samsung_gpio_pm samsung_gpio_pm_4bit = {
+        .save   = samsung_gpio_pm_4bit_save,
+        .resume = samsung_gpio_pm_4bit_resume,
 };
 #endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P */
 
 /**
- * s3c_pm_save_gpio() - save gpio chip data for suspend
+ * samsung_pm_save_gpio() - save gpio chip data for suspend
  * @ourchip: The chip for suspend.
  */
-static void s3c_pm_save_gpio(struct s3c_gpio_chip *ourchip)
+static void samsung_pm_save_gpio(struct samsung_gpio_chip *ourchip)
 {
-        struct s3c_gpio_pm *pm = ourchip->pm;
+        struct samsung_gpio_pm *pm = ourchip->pm;
 
         if (pm == NULL || pm->save == NULL)
                 S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label);
@@ -319,24 +319,24 @@ static void s3c_pm_save_gpio(struct s3c_gpio_chip *ourchip)
 }
 
 /**
- * s3c_pm_save_gpios() - Save the state of the GPIO banks.
+ * samsung_pm_save_gpios() - Save the state of the GPIO banks.
  *
  * For all the GPIO banks, save the state of each one ready for going
  * into a suspend mode.
  */
-void s3c_pm_save_gpios(void)
+void samsung_pm_save_gpios(void)
 {
-        struct s3c_gpio_chip *ourchip;
+        struct samsung_gpio_chip *ourchip;
         unsigned int gpio_nr;
 
         for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) {
-                ourchip = s3c_gpiolib_getchip(gpio_nr);
+                ourchip = samsung_gpiolib_getchip(gpio_nr);
                 if (!ourchip) {
                         gpio_nr++;
                         continue;
                 }
 
-                s3c_pm_save_gpio(ourchip);
+                samsung_pm_save_gpio(ourchip);
 
                 S3C_PMDBG("%s: save %08x,%08x,%08x,%08x\n",
                           ourchip->chip.label,
@@ -351,12 +351,12 @@ void s3c_pm_save_gpios(void)
 }
 
 /**
- * s3c_pm_resume_gpio() - restore gpio chip data after suspend
+ * samsung_pm_resume_gpio() - restore gpio chip data after suspend
  * @ourchip: The suspended chip.
  */
-static void s3c_pm_resume_gpio(struct s3c_gpio_chip *ourchip)
+static void samsung_pm_resume_gpio(struct samsung_gpio_chip *ourchip)
 {
-        struct s3c_gpio_pm *pm = ourchip->pm;
+        struct samsung_gpio_pm *pm = ourchip->pm;
 
         if (pm == NULL || pm->resume == NULL)
                 S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label);
@@ -364,19 +364,19 @@ static void s3c_pm_resume_gpio(struct s3c_gpio_chip *ourchip)
                 pm->resume(ourchip);
 }
 
-void s3c_pm_restore_gpios(void)
+void samsung_pm_restore_gpios(void)
 {
-        struct s3c_gpio_chip *ourchip;
+        struct samsung_gpio_chip *ourchip;
         unsigned int gpio_nr;
 
         for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) {
-                ourchip = s3c_gpiolib_getchip(gpio_nr);
+                ourchip = samsung_gpiolib_getchip(gpio_nr);
                 if (!ourchip) {
                         gpio_nr++;
                         continue;
                 }
 
-                s3c_pm_resume_gpio(ourchip);
+                samsung_pm_resume_gpio(ourchip);
 
                 gpio_nr += ourchip->chip.ngpio;
                 gpio_nr += CONFIG_S3C_GPIO_SPACE;
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index ae6f99834cdd..64ab65f0fdbc 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -268,8 +268,8 @@ static int s3c_pm_enter(suspend_state_t state)
 
         /* save all necessary core registers not covered by the drivers */
 
-        s3c_pm_save_gpios();
-        s3c_pm_saved_gpios();
+        samsung_pm_save_gpios();
+        samsung_pm_saved_gpios();
         s3c_pm_save_uarts();
         s3c_pm_save_core();
 
@@ -306,7 +306,7 @@ static int s3c_pm_enter(suspend_state_t state)
 
         s3c_pm_restore_core();
         s3c_pm_restore_uarts();
-        s3c_pm_restore_gpios();
+        samsung_pm_restore_gpios();
         s3c_pm_restored_gpios();
 
         s3c_pm_debug_init();
diff --git a/arch/arm/plat-samsung/pwm-clock.c b/arch/arm/plat-samsung/pwm-clock.c
index f1bba88ed2f5..a35ff3bcffe4 100644
--- a/arch/arm/plat-samsung/pwm-clock.c
+++ b/arch/arm/plat-samsung/pwm-clock.c
@@ -27,7 +27,7 @@
 #include <plat/cpu.h>
 
 #include <plat/regs-timer.h>
-#include <mach/pwm-clock.h>
+#include <plat/pwm-clock.h>
 
 /* Each of the timers 0 through 5 go through the following
  * clock tree, with the inputs depending on the timers.
@@ -339,8 +339,17 @@ static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent)
         unsigned long bits;
         unsigned long shift = S3C2410_TCFG1_SHIFT(id);
 
+        unsigned long mux_tclk;
+
+        if (soc_is_s3c24xx())
+                mux_tclk = S3C2410_TCFG1_MUX_TCLK;
+        else if (soc_is_s5p6440() || soc_is_s5p6450())
+                mux_tclk = 0;
+        else
+                mux_tclk = S3C64XX_TCFG1_MUX_TCLK;
+
         if (parent == s3c24xx_pwmclk_tclk(id))
-                bits = S3C_TCFG1_MUX_TCLK << shift;
+                bits = mux_tclk << shift;
         else if (parent == s3c24xx_pwmclk_tdiv(id))
                 bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift;
         else
diff --git a/arch/arm/plat-samsung/s3c-dma-ops.c b/arch/arm/plat-samsung/s3c-dma-ops.c
new file mode 100644
index 000000000000..582333c70585
--- /dev/null
+++ b/arch/arm/plat-samsung/s3c-dma-ops.c
@@ -0,0 +1,130 @@
+/* linux/arch/arm/plat-samsung/s3c-dma-ops.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Samsung S3C-DMA Operations
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+
+#include <mach/dma.h>
+
+struct cb_data {
+        void (*fp) (void *);
+        void *fp_param;
+        unsigned ch;
+        struct list_head node;
+};
+
+static LIST_HEAD(dma_list);
+
+static void s3c_dma_cb(struct s3c2410_dma_chan *channel, void *param,
+                       int size, enum s3c2410_dma_buffresult res)
+{
+        struct cb_data *data = param;
+
+        data->fp(data->fp_param);
+}
+
+static unsigned s3c_dma_request(enum dma_ch dma_ch,
+                                 struct samsung_dma_info *info)
+{
+        struct cb_data *data;
+
+        if (s3c2410_dma_request(dma_ch, info->client, NULL) < 0) {
+                s3c2410_dma_free(dma_ch, info->client);
+                return 0;
+        }
+
+        data = kzalloc(sizeof(struct cb_data), GFP_KERNEL);
+        data->ch = dma_ch;
+        list_add_tail(&data->node, &dma_list);
+
+        s3c2410_dma_devconfig(dma_ch, info->direction, info->fifo);
+
+        if (info->cap == DMA_CYCLIC)
+                s3c2410_dma_setflags(dma_ch, S3C2410_DMAF_CIRCULAR);
+
+        s3c2410_dma_config(dma_ch, info->width);
+
+        return (unsigned)dma_ch;
+}
+
+static int s3c_dma_release(unsigned ch, struct s3c2410_dma_client *client)
+{
+        struct cb_data *data;
+
+        list_for_each_entry(data, &dma_list, node)
+                if (data->ch == ch)
+                        break;
+        list_del(&data->node);
+
+        s3c2410_dma_free(ch, client);
+        kfree(data);
+
+        return 0;
+}
+
+static int s3c_dma_prepare(unsigned ch, struct samsung_dma_prep_info *info)
+{
+        struct cb_data *data;
+        int len = (info->cap == DMA_CYCLIC) ? info->period : info->len;
+
+        list_for_each_entry(data, &dma_list, node)
+                if (data->ch == ch)
+                        break;
+
+        if (!data->fp) {
+                s3c2410_dma_set_buffdone_fn(ch, s3c_dma_cb);
+                data->fp = info->fp;
+                data->fp_param = info->fp_param;
+        }
+
+        s3c2410_dma_enqueue(ch, (void *)data, info->buf, len);
+
+        return 0;
+}
+
+static inline int s3c_dma_trigger(unsigned ch)
+{
+        return s3c2410_dma_ctrl(ch, S3C2410_DMAOP_START);
+}
+
+static inline int s3c_dma_started(unsigned ch)
+{
+        return s3c2410_dma_ctrl(ch, S3C2410_DMAOP_STARTED);
+}
+
+static inline int s3c_dma_flush(unsigned ch)
+{
+        return s3c2410_dma_ctrl(ch, S3C2410_DMAOP_FLUSH);
+}
+
+static inline int s3c_dma_stop(unsigned ch)
+{
+        return s3c2410_dma_ctrl(ch, S3C2410_DMAOP_STOP);
+}
+
+static struct samsung_dma_ops s3c_dma_ops = {
+        .request        = s3c_dma_request,
+        .release        = s3c_dma_release,
+        .prepare        = s3c_dma_prepare,
+        .trigger        = s3c_dma_trigger,
+        .started        = s3c_dma_started,
+        .flush          = s3c_dma_flush,
+        .stop           = s3c_dma_stop,
+};
+
+void *s3c_dma_get_ops(void)
+{
+        return &s3c_dma_ops;
+}
+EXPORT_SYMBOL(s3c_dma_get_ops);
diff --git a/arch/arm/plat-samsung/s3c-pl330.c b/arch/arm/plat-samsung/s3c-pl330.c
deleted file mode 100644
index f85638c6f5ae..000000000000
--- a/arch/arm/plat-samsung/s3c-pl330.c
+++ /dev/null
@@ -1,1244 +0,0 @@
-/* linux/arch/arm/plat-samsung/s3c-pl330.c
- *
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/platform_device.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-
-#include <asm/hardware/pl330.h>
-
-#include <plat/s3c-pl330-pdata.h>
-
-/**
- * struct s3c_pl330_dmac - Logical representation of a PL330 DMAC.
- * @busy_chan: Number of channels currently busy.
- * @peri: List of IDs of peripherals this DMAC can work with.
- * @node: To attach to the global list of DMACs.
- * @pi: PL330 configuration info for the DMAC.
- * @kmcache: Pool to quickly allocate xfers for all channels in the dmac.
- * @clk: Pointer of DMAC operation clock.
- */
-struct s3c_pl330_dmac {
-        unsigned                busy_chan;
-        enum dma_ch             *peri;
-        struct list_head        node;
-        struct pl330_info       *pi;
-        struct kmem_cache       *kmcache;
-        struct clk              *clk;
-};
-
-/**
- * struct s3c_pl330_xfer - A request submitted by S3C DMA clients.
- * @token: Xfer ID provided by the client.
- * @node: To attach to the list of xfers on a channel.
- * @px: Xfer for PL330 core.
- * @chan: Owner channel of this xfer.
- */
-struct s3c_pl330_xfer {
-        void                    *token;
-        struct list_head        node;
-        struct pl330_xfer       px;
-        struct s3c_pl330_chan   *chan;
-};
-
-/**
- * struct s3c_pl330_chan - Logical channel to communicate with
- *      a Physical peripheral.
- * @pl330_chan_id: Token of a hardware channel thread of PL330 DMAC.
- *      NULL if the channel is available to be acquired.
- * @id: ID of the peripheral that this channel can communicate with.
- * @options: Options specified by the client.
- * @sdaddr: Address provided via s3c2410_dma_devconfig.
- * @node: To attach to the global list of channels.
- * @lrq: Pointer to the last submitted pl330_req to PL330 core.
- * @xfer_list: To manage list of xfers enqueued.
- * @req: Two requests to communicate with the PL330 engine.
- * @callback_fn: Callback function to the client.
- * @rqcfg: Channel configuration for the xfers.
- * @xfer_head: Pointer to the xfer to be next executed.
- * @dmac: Pointer to the DMAC that manages this channel, NULL if the
- *      channel is available to be acquired.
- * @client: Client of this channel. NULL if the
- *      channel is available to be acquired.
- */
-struct s3c_pl330_chan {
-        void                            *pl330_chan_id;
-        enum dma_ch                     id;
-        unsigned int                    options;
-        unsigned long                   sdaddr;
-        struct list_head                node;
-        struct pl330_req                *lrq;
-        struct list_head                xfer_list;
-        struct pl330_req                req[2];
-        s3c2410_dma_cbfn_t              callback_fn;
-        struct pl330_reqcfg             rqcfg;
-        struct s3c_pl330_xfer           *xfer_head;
-        struct s3c_pl330_dmac           *dmac;
-        struct s3c2410_dma_client       *client;
-};
-
-/* All DMACs in the platform */
-static LIST_HEAD(dmac_list);
-
-/* All channels to peripherals in the platform */
-static LIST_HEAD(chan_list);
-
-/*
- * Since we add resources(DMACs and Channels) to the global pool,
- * we need to guard access to the resources using a global lock
- */
-static DEFINE_SPINLOCK(res_lock);
-
-/* Returns the channel with ID 'id' in the chan_list */
-static struct s3c_pl330_chan *id_to_chan(const enum dma_ch id)
-{
-        struct s3c_pl330_chan *ch;
-
-        list_for_each_entry(ch, &chan_list, node)
-                if (ch->id == id)
-                        return ch;
-
-        return NULL;
-}
-
-/* Allocate a new channel with ID 'id' and add to chan_list */
-static void chan_add(const enum dma_ch id)
-{
-        struct s3c_pl330_chan *ch = id_to_chan(id);
-
-        /* Return if the channel already exists */
-        if (ch)
-                return;
-
-        ch = kmalloc(sizeof(*ch), GFP_KERNEL);
-        /* Return silently to work with other channels */
-        if (!ch)
-                return;
-
-        ch->id = id;
-        ch->dmac = NULL;
-
-        list_add_tail(&ch->node, &chan_list);
-}
-
-/* If the channel is not yet acquired by any client */
-static bool chan_free(struct s3c_pl330_chan *ch)
-{
-        if (!ch)
-                return false;
-
-        /* Channel points to some DMAC only when it's acquired */
-        return ch->dmac ? false : true;
-}
-
-/*
- * Returns 0 is peripheral i/f is invalid or not present on the dmac.
- * Index + 1, otherwise.
- */
-static unsigned iface_of_dmac(struct s3c_pl330_dmac *dmac, enum dma_ch ch_id)
-{
-        enum dma_ch *id = dmac->peri;
-        int i;
-
-        /* Discount invalid markers */
-        if (ch_id == DMACH_MAX)
-                return 0;
-
-        for (i = 0; i < PL330_MAX_PERI; i++)
-                if (id[i] == ch_id)
-                        return i + 1;
-
-        return 0;
-}
-
-/* If all channel threads of the DMAC are busy */
-static inline bool dmac_busy(struct s3c_pl330_dmac *dmac)
-{
-        struct pl330_info *pi = dmac->pi;
-
-        return (dmac->busy_chan < pi->pcfg.num_chan) ? false : true;
-}
-
-/*
- * Returns the number of free channels that
- * can be handled by this dmac only.
- */
-static unsigned ch_onlyby_dmac(struct s3c_pl330_dmac *dmac)
-{
-        enum dma_ch *id = dmac->peri;
-        struct s3c_pl330_dmac *d;
-        struct s3c_pl330_chan *ch;
-        unsigned found, count = 0;
-        enum dma_ch p;
-        int i;
-
-        for (i = 0; i < PL330_MAX_PERI; i++) {
-                p = id[i];
-                ch = id_to_chan(p);
-
-                if (p == DMACH_MAX || !chan_free(ch))
-                        continue;
-
-                found = 0;
-                list_for_each_entry(d, &dmac_list, node) {
-                        if (d != dmac && iface_of_dmac(d, ch->id)) {
-                                found = 1;
-                                break;
-                        }
-                }
-                if (!found)
-                        count++;
-        }
-
-        return count;
-}
-
-/*
- * Measure of suitability of 'dmac' handling 'ch'
- *
- * 0 indicates 'dmac' can not handle 'ch' either
- * because it is not supported by the hardware or
- * because all dmac channels are currently busy.
- *
- * >0 vlaue indicates 'dmac' has the capability.
- * The bigger the value the more suitable the dmac.
- */
-#define MAX_SUIT        UINT_MAX
-#define MIN_SUIT        0
-
-static unsigned suitablility(struct s3c_pl330_dmac *dmac,
-                struct s3c_pl330_chan *ch)
-{
-        struct pl330_info *pi = dmac->pi;
-        enum dma_ch *id = dmac->peri;
-        struct s3c_pl330_dmac *d;
-        unsigned s;
-        int i;
-
-        s = MIN_SUIT;
-        /* If all the DMAC channel threads are busy */
-        if (dmac_busy(dmac))
-                return s;
-
-        for (i = 0; i < PL330_MAX_PERI; i++)
-                if (id[i] == ch->id)
-                        break;
-
-        /* If the 'dmac' can't talk to 'ch' */
-        if (i == PL330_MAX_PERI)
-                return s;
-
-        s = MAX_SUIT;
-        list_for_each_entry(d, &dmac_list, node) {
-                /*
-                 * If some other dmac can talk to this
-                 * peri and has some channel free.
-                 */
-                if (d != dmac && iface_of_dmac(d, ch->id) && !dmac_busy(d)) {
-                        s = 0;
-                        break;
-                }
-        }
-        if (s)
-                return s;
-
-        s = 100;
-
-        /* Good if free chans are more, bad otherwise */
-        s += (pi->pcfg.num_chan - dmac->busy_chan) - ch_onlyby_dmac(dmac);
-
-        return s;
-}
-
-/* More than one DMAC may have capability to transfer data with the
- * peripheral. This function assigns most suitable DMAC to manage the
- * channel and hence communicate with the peripheral.
- */
-static struct s3c_pl330_dmac *map_chan_to_dmac(struct s3c_pl330_chan *ch)
-{
-        struct s3c_pl330_dmac *d, *dmac = NULL;
-        unsigned sn, sl = MIN_SUIT;
-
-        list_for_each_entry(d, &dmac_list, node) {
-                sn = suitablility(d, ch);
-
-                if (sn == MAX_SUIT)
-                        return d;
-
-                if (sn > sl)
-                        dmac = d;
-        }
-
-        return dmac;
-}
-
-/* Acquire the channel for peripheral 'id' */
-static struct s3c_pl330_chan *chan_acquire(const enum dma_ch id)
-{
-        struct s3c_pl330_chan *ch = id_to_chan(id);
-        struct s3c_pl330_dmac *dmac;
-
-        /* If the channel doesn't exist or is already acquired */
-        if (!ch || !chan_free(ch)) {
-                ch = NULL;
-                goto acq_exit;
-        }
-
-        dmac = map_chan_to_dmac(ch);
-        /* If couldn't map */
-        if (!dmac) {
-                ch = NULL;
-                goto acq_exit;
-        }
-
-        dmac->busy_chan++;
-        ch->dmac = dmac;
-
-acq_exit:
-        return ch;
-}
-
-/* Delete xfer from the queue */
-static inline void del_from_queue(struct s3c_pl330_xfer *xfer)
-{
-        struct s3c_pl330_xfer *t;
-        struct s3c_pl330_chan *ch;
-        int found;
-
-        if (!xfer)
-                return;
-
-        ch = xfer->chan;
-
-        /* Make sure xfer is in the queue */
-        found = 0;
-        list_for_each_entry(t, &ch->xfer_list, node)
-                if (t == xfer) {
-                        found = 1;
-                        break;
-                }
-
-        if (!found)
-                return;
-
-        /* If xfer is last entry in the queue */
-        if (xfer->node.next == &ch->xfer_list)
-                t = list_entry(ch->xfer_list.next,
-                                struct s3c_pl330_xfer, node);
-        else
-                t = list_entry(xfer->node.next,
-                                struct s3c_pl330_xfer, node);
-
-        /* If there was only one node left */
-        if (t == xfer)
-                ch->xfer_head = NULL;
-        else if (ch->xfer_head == xfer)
-                ch->xfer_head = t;
-
-        list_del(&xfer->node);
-}
-
-/* Provides pointer to the next xfer in the queue.
- * If CIRCULAR option is set, the list is left intact,
- * otherwise the xfer is removed from the list.
- * Forced delete 'pluck' can be set to override the CIRCULAR option.
- */
-static struct s3c_pl330_xfer *get_from_queue(struct s3c_pl330_chan *ch,
-                int pluck)
-{
-        struct s3c_pl330_xfer *xfer = ch->xfer_head;
-
-        if (!xfer)
-                return NULL;
-
-        /* If xfer is last entry in the queue */
-        if (xfer->node.next == &ch->xfer_list)
-                ch->xfer_head = list_entry(ch->xfer_list.next,
-                                        struct s3c_pl330_xfer, node);
-        else
-                ch->xfer_head = list_entry(xfer->node.next,
-                                        struct s3c_pl330_xfer, node);
-
-        if (pluck || !(ch->options & S3C2410_DMAF_CIRCULAR))
-                del_from_queue(xfer);
-
-        return xfer;
-}
-
-static inline void add_to_queue(struct s3c_pl330_chan *ch,
-                struct s3c_pl330_xfer *xfer, int front)
-{
-        struct pl330_xfer *xt;
-
-        /* If queue empty */
-        if (ch->xfer_head == NULL)
-                ch->xfer_head = xfer;
-
-        xt = &ch->xfer_head->px;
-        /* If the head already submitted (CIRCULAR head) */
-        if (ch->options & S3C2410_DMAF_CIRCULAR &&
-                (xt == ch->req[0].x || xt == ch->req[1].x))
-                ch->xfer_head = xfer;
-
-        /* If this is a resubmission, it should go at the head */
-        if (front) {
-                ch->xfer_head = xfer;
-                list_add(&xfer->node, &ch->xfer_list);
-        } else {
-                list_add_tail(&xfer->node, &ch->xfer_list);
-        }
-}
-
-static inline void _finish_off(struct s3c_pl330_xfer *xfer,
-                enum s3c2410_dma_buffresult res, int ffree)
-{
-        struct s3c_pl330_chan *ch;
-
-        if (!xfer)
-                return;
-
-        ch = xfer->chan;
-
-        /* Do callback */
-        if (ch->callback_fn)
-                ch->callback_fn(NULL, xfer->token, xfer->px.bytes, res);
-
-        /* Force Free or if buffer is not needed anymore */
-        if (ffree || !(ch->options & S3C2410_DMAF_CIRCULAR))
-                kmem_cache_free(ch->dmac->kmcache, xfer);
-}
-
-static inline int s3c_pl330_submit(struct s3c_pl330_chan *ch,
-                struct pl330_req *r)
-{
-        struct s3c_pl330_xfer *xfer;
-        int ret = 0;
-
-        /* If already submitted */
-        if (r->x)
-                return 0;
-
-        xfer = get_from_queue(ch, 0);
-        if (xfer) {
-                r->x = &xfer->px;
-
-                /* Use max bandwidth for M<->M xfers */
-                if (r->rqtype == MEMTOMEM) {
-                        struct pl330_info *pi = xfer->chan->dmac->pi;
-                        int burst = 1 << ch->rqcfg.brst_size;
-                        u32 bytes = r->x->bytes;
-                        int bl;
-
-                        bl = pi->pcfg.data_bus_width / 8;
-                        bl *= pi->pcfg.data_buf_dep;
-                        bl /= burst;
-
-                        /* src/dst_burst_len can't be more than 16 */
-                        if (bl > 16)
-                                bl = 16;
-
-                        while (bl > 1) {
-                                if (!(bytes % (bl * burst)))
-                                        break;
-                                bl--;
-                        }
-
-                        ch->rqcfg.brst_len = bl;
-                } else {
-                        ch->rqcfg.brst_len = 1;
-                }
-
-                ret = pl330_submit_req(ch->pl330_chan_id, r);
-
-                /* If submission was successful */
-                if (!ret) {
-                        ch->lrq = r; /* latest submitted req */
-                        return 0;
-                }
-
-                r->x = NULL;
-
-                /* If both of the PL330 ping-pong buffers filled */
-                if (ret == -EAGAIN) {
-                        dev_err(ch->dmac->pi->dev, "%s:%d!\n",
-                                __func__, __LINE__);
-                        /* Queue back again */
-                        add_to_queue(ch, xfer, 1);
-                        ret = 0;
-                } else {
-                        dev_err(ch->dmac->pi->dev, "%s:%d!\n",
-                                __func__, __LINE__);
-                        _finish_off(xfer, S3C2410_RES_ERR, 0);
-                }
-        }
-
-        return ret;
-}
-
-static void s3c_pl330_rq(struct s3c_pl330_chan *ch,
-        struct pl330_req *r, enum pl330_op_err err)
-{
-        unsigned long flags;
-        struct s3c_pl330_xfer *xfer;
-        struct pl330_xfer *xl = r->x;
-        enum s3c2410_dma_buffresult res;
-
-        spin_lock_irqsave(&res_lock, flags);
-
-        r->x = NULL;
-
-        s3c_pl330_submit(ch, r);
-
-        spin_unlock_irqrestore(&res_lock, flags);
-
-        /* Map result to S3C DMA API */
-        if (err == PL330_ERR_NONE)
-                res = S3C2410_RES_OK;
-        else if (err == PL330_ERR_ABORT)
-                res = S3C2410_RES_ABORT;
-        else
-                res = S3C2410_RES_ERR;
-
-        /* If last request had some xfer */
-        if (xl) {
-                xfer = container_of(xl, struct s3c_pl330_xfer, px);
-                _finish_off(xfer, res, 0);
-        } else {
-                dev_info(ch->dmac->pi->dev, "%s:%d No Xfer?!\n",
-                        __func__, __LINE__);
-        }
-}
-
-static void s3c_pl330_rq0(void *token, enum pl330_op_err err)
-{
-        struct pl330_req *r = token;
-        struct s3c_pl330_chan *ch = container_of(r,
-                                        struct s3c_pl330_chan, req[0]);
-        s3c_pl330_rq(ch, r, err);
-}
-
-static void s3c_pl330_rq1(void *token, enum pl330_op_err err)
-{
-        struct pl330_req *r = token;
-        struct s3c_pl330_chan *ch = container_of(r,
-                                        struct s3c_pl330_chan, req[1]);
-        s3c_pl330_rq(ch, r, err);
-}
-
-/* Release an acquired channel */
-static void chan_release(struct s3c_pl330_chan *ch)
-{
-        struct s3c_pl330_dmac *dmac;
-
-        if (chan_free(ch))
-                return;
-
-        dmac = ch->dmac;
-        ch->dmac = NULL;
-        dmac->busy_chan--;
-}
-
-int s3c2410_dma_ctrl(enum dma_ch id, enum s3c2410_chan_op op)
-{
-        struct s3c_pl330_xfer *xfer;
-        enum pl330_chan_op pl330op;
-        struct s3c_pl330_chan *ch;
-        unsigned long flags;
-        int idx, ret;
-
-        spin_lock_irqsave(&res_lock, flags);
-
-        ch = id_to_chan(id);
-
-        if (!ch || chan_free(ch)) {
-                ret = -EINVAL;
-                goto ctrl_exit;
-        }
-
-        switch (op) {
-        case S3C2410_DMAOP_START:
-                /* Make sure both reqs are enqueued */
-                idx = (ch->lrq == &ch->req[0]) ? 1 : 0;
-                s3c_pl330_submit(ch, &ch->req[idx]);
-                s3c_pl330_submit(ch, &ch->req[1 - idx]);
-                pl330op = PL330_OP_START;
-                break;
-
-        case S3C2410_DMAOP_STOP:
-                pl330op = PL330_OP_ABORT;
-                break;
-
-        case S3C2410_DMAOP_FLUSH:
-                pl330op = PL330_OP_FLUSH;
-                break;
-
-        case S3C2410_DMAOP_PAUSE:
-        case S3C2410_DMAOP_RESUME:
-        case S3C2410_DMAOP_TIMEOUT:
-        case S3C2410_DMAOP_STARTED:
-                spin_unlock_irqrestore(&res_lock, flags);
-                return 0;
-
-        default:
-                spin_unlock_irqrestore(&res_lock, flags);
-                return -EINVAL;
-        }
-
-        ret = pl330_chan_ctrl(ch->pl330_chan_id, pl330op);
-
-        if (pl330op == PL330_OP_START) {
-                spin_unlock_irqrestore(&res_lock, flags);
-                return ret;
-        }
-
-        idx = (ch->lrq == &ch->req[0]) ? 1 : 0;
-
-        /* Abort the current xfer */
-        if (ch->req[idx].x) {
-                xfer = container_of(ch->req[idx].x,
-                                struct s3c_pl330_xfer, px);
-
-                /* Drop xfer during FLUSH */
-                if (pl330op == PL330_OP_FLUSH)
-                        del_from_queue(xfer);
-
-                ch->req[idx].x = NULL;
-
-                spin_unlock_irqrestore(&res_lock, flags);
-                _finish_off(xfer, S3C2410_RES_ABORT,
-                                pl330op == PL330_OP_FLUSH ? 1 : 0);
-                spin_lock_irqsave(&res_lock, flags);
-        }
-
-        /* Flush the whole queue */
-        if (pl330op == PL330_OP_FLUSH) {
-
-                if (ch->req[1 - idx].x) {
-                        xfer = container_of(ch->req[1 - idx].x,
-                                        struct s3c_pl330_xfer, px);
-
-                        del_from_queue(xfer);
-
-                        ch->req[1 - idx].x = NULL;
-
-                        spin_unlock_irqrestore(&res_lock, flags);
-                        _finish_off(xfer, S3C2410_RES_ABORT, 1);
-                        spin_lock_irqsave(&res_lock, flags);
-                }
-
-                /* Finish off the remaining in the queue */
-                xfer = ch->xfer_head;
-                while (xfer) {
-
-                        del_from_queue(xfer);
-
-                        spin_unlock_irqrestore(&res_lock, flags);
-                        _finish_off(xfer, S3C2410_RES_ABORT, 1);
-                        spin_lock_irqsave(&res_lock, flags);
-
-                        xfer = ch->xfer_head;
-                }
-        }
-
-ctrl_exit:
-        spin_unlock_irqrestore(&res_lock, flags);
-
-        return ret;
-}
-EXPORT_SYMBOL(s3c2410_dma_ctrl);
-
-int s3c2410_dma_enqueue(enum dma_ch id, void *token,
-                        dma_addr_t addr, int size)
-{
-        struct s3c_pl330_chan *ch;
-        struct s3c_pl330_xfer *xfer;
-        unsigned long flags;
-        int idx, ret = 0;
-
-        spin_lock_irqsave(&res_lock, flags);
-
-        ch = id_to_chan(id);
-
-        /* Error if invalid or free channel */
-        if (!ch || chan_free(ch)) {
-                ret = -EINVAL;
-                goto enq_exit;
-        }
-
-        /* Error if size is unaligned */
-        if (ch->rqcfg.brst_size && size % (1 << ch->rqcfg.brst_size)) {
-                ret = -EINVAL;
-                goto enq_exit;
-        }
-
-        xfer = kmem_cache_alloc(ch->dmac->kmcache, GFP_ATOMIC);
-        if (!xfer) {
-                ret = -ENOMEM;
-                goto enq_exit;
-        }
-
-        xfer->token = token;
-        xfer->chan = ch;
-        xfer->px.bytes = size;
-        xfer->px.next = NULL; /* Single request */
-
-        /* For S3C DMA API, direction is always fixed for all xfers */
-        if (ch->req[0].rqtype == MEMTODEV) {
-                xfer->px.src_addr = addr;
-                xfer->px.dst_addr = ch->sdaddr;
-        } else {
-                xfer->px.src_addr = ch->sdaddr;
-                xfer->px.dst_addr = addr;
-        }
-
-        add_to_queue(ch, xfer, 0);
-
-        /* Try submitting on either request */
-        idx = (ch->lrq == &ch->req[0]) ? 1 : 0;
-
-        if (!ch->req[idx].x)
-                s3c_pl330_submit(ch, &ch->req[idx]);
-        else
-                s3c_pl330_submit(ch, &ch->req[1 - idx]);
-
-        spin_unlock_irqrestore(&res_lock, flags);
-
-        if (ch->options & S3C2410_DMAF_AUTOSTART)
-                s3c2410_dma_ctrl(id, S3C2410_DMAOP_START);
-
-        return 0;
-
-enq_exit:
-        spin_unlock_irqrestore(&res_lock, flags);
-
-        return ret;
-}
-EXPORT_SYMBOL(s3c2410_dma_enqueue);
-
-int s3c2410_dma_request(enum dma_ch id,
-                        struct s3c2410_dma_client *client,
-                        void *dev)
-{
-        struct s3c_pl330_dmac *dmac;
-        struct s3c_pl330_chan *ch;
-        unsigned long flags;
-        int ret = 0;
-
-        spin_lock_irqsave(&res_lock, flags);
-
-        ch = chan_acquire(id);
-        if (!ch) {
-                ret = -EBUSY;
-                goto req_exit;
-        }
-
-        dmac = ch->dmac;
-
-        ch->pl330_chan_id = pl330_request_channel(dmac->pi);
-        if (!ch->pl330_chan_id) {
-                chan_release(ch);
-                ret = -EBUSY;
-                goto req_exit;
-        }
-
-        ch->client = client;
-        ch->options = 0; /* Clear any option */
-        ch->callback_fn = NULL; /* Clear any callback */
-        ch->lrq = NULL;
-
-        ch->rqcfg.brst_size = 2; /* Default word size */
-        ch->rqcfg.swap = SWAP_NO;
-        ch->rqcfg.scctl = SCCTRL0; /* Noncacheable and nonbufferable */
-        ch->rqcfg.dcctl = DCCTRL0; /* Noncacheable and nonbufferable */
-        ch->rqcfg.privileged = 0;
-        ch->rqcfg.insnaccess = 0;
-
-        /* Set invalid direction */
-        ch->req[0].rqtype = DEVTODEV;
-        ch->req[1].rqtype = ch->req[0].rqtype;
-
-        ch->req[0].cfg = &ch->rqcfg;
-        ch->req[1].cfg = ch->req[0].cfg;
-
-        ch->req[0].peri = iface_of_dmac(dmac, id) - 1; /* Original index */
-        ch->req[1].peri = ch->req[0].peri;
-
-        ch->req[0].token = &ch->req[0];
-        ch->req[0].xfer_cb = s3c_pl330_rq0;
-        ch->req[1].token = &ch->req[1];
-        ch->req[1].xfer_cb = s3c_pl330_rq1;
-
-        ch->req[0].x = NULL;
-        ch->req[1].x = NULL;
-
-        /* Reset xfer list */
-        INIT_LIST_HEAD(&ch->xfer_list);
-        ch->xfer_head = NULL;
-
-req_exit:
-        spin_unlock_irqrestore(&res_lock, flags);
-
-        return ret;
-}
-EXPORT_SYMBOL(s3c2410_dma_request);
-
-int s3c2410_dma_free(enum dma_ch id, struct s3c2410_dma_client *client)
-{
-        struct s3c_pl330_chan *ch;
-        struct s3c_pl330_xfer *xfer;
-        unsigned long flags;
-        int ret = 0;
-        unsigned idx;
-
-        spin_lock_irqsave(&res_lock, flags);
-
-        ch = id_to_chan(id);
-
-        if (!ch || chan_free(ch))
-                goto free_exit;
-
-        /* Refuse if someone else wanted to free the channel */
-        if (ch->client != client) {
-                ret = -EBUSY;
-                goto free_exit;
-        }
-
-        /* Stop any active xfer, Flushe the queue and do callbacks */
-        pl330_chan_ctrl(ch->pl330_chan_id, PL330_OP_FLUSH);
-
-        /* Abort the submitted requests */
-        idx = (ch->lrq == &ch->req[0]) ? 1 : 0;
-
-        if (ch->req[idx].x) {
-                xfer = container_of(ch->req[idx].x,
-                                struct s3c_pl330_xfer, px);
-
-                ch->req[idx].x = NULL;
-                del_from_queue(xfer);
-
-                spin_unlock_irqrestore(&res_lock, flags);
-                _finish_off(xfer, S3C2410_RES_ABORT, 1);
-                spin_lock_irqsave(&res_lock, flags);
-        }
-
-        if (ch->req[1 - idx].x) {
-                xfer = container_of(ch->req[1 - idx].x,
-                                struct s3c_pl330_xfer, px);
-
-                ch->req[1 - idx].x = NULL;
-                del_from_queue(xfer);
-
-                spin_unlock_irqrestore(&res_lock, flags);
-                _finish_off(xfer, S3C2410_RES_ABORT, 1);
-                spin_lock_irqsave(&res_lock, flags);
-        }
-
-        /* Pluck and Abort the queued requests in order */
-        do {
-                xfer = get_from_queue(ch, 1);
-
-                spin_unlock_irqrestore(&res_lock, flags);
-                _finish_off(xfer, S3C2410_RES_ABORT, 1);
-                spin_lock_irqsave(&res_lock, flags);
-        } while (xfer);
-
-        ch->client = NULL;
-
-        pl330_release_channel(ch->pl330_chan_id);
-
-        ch->pl330_chan_id = NULL;
-
-        chan_release(ch);
-
-free_exit:
-        spin_unlock_irqrestore(&res_lock, flags);
-
-        return ret;
-}
-EXPORT_SYMBOL(s3c2410_dma_free);
-
-int s3c2410_dma_config(enum dma_ch id, int xferunit)
-{
-        struct s3c_pl330_chan *ch;
-        struct pl330_info *pi;
-        unsigned long flags;
-        int i, dbwidth, ret = 0;
-
-        spin_lock_irqsave(&res_lock, flags);
-
-        ch = id_to_chan(id);
-
-        if (!ch || chan_free(ch)) {
-                ret = -EINVAL;
-                goto cfg_exit;
-        }
-
-        pi = ch->dmac->pi;
-        dbwidth = pi->pcfg.data_bus_width / 8;
-
-        /* Max size of xfer can be pcfg.data_bus_width */
-        if (xferunit > dbwidth) {
-                ret = -EINVAL;
-                goto cfg_exit;
-        }
-
-        i = 0;
-        while (xferunit != (1 << i))
-                i++;
-
-        /* If valid value */
-        if (xferunit == (1 << i))
-                ch->rqcfg.brst_size = i;
-        else
-                ret = -EINVAL;
-
-cfg_exit:
-        spin_unlock_irqrestore(&res_lock, flags);
-
-        return ret;
-}
-EXPORT_SYMBOL(s3c2410_dma_config);
-
-/* Options that are supported by this driver */
-#define S3C_PL330_FLAGS (S3C2410_DMAF_CIRCULAR | S3C2410_DMAF_AUTOSTART)
-
-int s3c2410_dma_setflags(enum dma_ch id, unsigned int options)
-{
-        struct s3c_pl330_chan *ch;
-        unsigned long flags;
-        int ret = 0;
-
-        spin_lock_irqsave(&res_lock, flags);
-
-        ch = id_to_chan(id);
-
-        if (!ch || chan_free(ch) || options & ~(S3C_PL330_FLAGS))
-                ret = -EINVAL;
-        else
-                ch->options = options;
-
-        spin_unlock_irqrestore(&res_lock, flags);
-
-        return 0;
-}
-EXPORT_SYMBOL(s3c2410_dma_setflags);
-
-int s3c2410_dma_set_buffdone_fn(enum dma_ch id, s3c2410_dma_cbfn_t rtn)
-{
-        struct s3c_pl330_chan *ch;
-        unsigned long flags;
-        int ret = 0;
-
-        spin_lock_irqsave(&res_lock, flags);
-
-        ch = id_to_chan(id);
-
-        if (!ch || chan_free(ch))
-                ret = -EINVAL;
-        else
-                ch->callback_fn = rtn;
-
-        spin_unlock_irqrestore(&res_lock, flags);
-
-        return ret;
-}
-EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
-
-int s3c2410_dma_devconfig(enum dma_ch id, enum s3c2410_dmasrc source,
-                          unsigned long address)
-{
-        struct s3c_pl330_chan *ch;
-        unsigned long flags;
-        int ret = 0;
-
-        spin_lock_irqsave(&res_lock, flags);
-
-        ch = id_to_chan(id);
-
-        if (!ch || chan_free(ch)) {
-                ret = -EINVAL;
-                goto devcfg_exit;
-        }
-
-        switch (source) {
-        case S3C2410_DMASRC_HW: /* P->M */
-                ch->req[0].rqtype = DEVTOMEM;
-                ch->req[1].rqtype = DEVTOMEM;
-                ch->rqcfg.src_inc = 0;
-                ch->rqcfg.dst_inc = 1;
-                break;
-        case S3C2410_DMASRC_MEM: /* M->P */
-                ch->req[0].rqtype = MEMTODEV;
-                ch->req[1].rqtype = MEMTODEV;
-                ch->rqcfg.src_inc = 1;
-                ch->rqcfg.dst_inc = 0;
-                break;
-        default:
-                ret = -EINVAL;
-                goto devcfg_exit;
-        }
-
-        ch->sdaddr = address;
-
-devcfg_exit:
-        spin_unlock_irqrestore(&res_lock, flags);
-
-        return ret;
-}
-EXPORT_SYMBOL(s3c2410_dma_devconfig);
-
-int s3c2410_dma_getposition(enum dma_ch id, dma_addr_t *src, dma_addr_t *dst)
-{
-        struct s3c_pl330_chan *ch = id_to_chan(id);
-        struct pl330_chanstatus status;
-        int ret;
-
-        if (!ch || chan_free(ch))
-                return -EINVAL;
-
-        ret = pl330_chan_status(ch->pl330_chan_id, &status);
-        if (ret < 0)
-                return ret;
-
-        *src = status.src_addr;
-        *dst = status.dst_addr;
-
-        return 0;
-}
-EXPORT_SYMBOL(s3c2410_dma_getposition);
-
-static irqreturn_t pl330_irq_handler(int irq, void *data)
-{
-        if (pl330_update(data))
-                return IRQ_HANDLED;
-        else
-                return IRQ_NONE;
-}
-
-static int pl330_probe(struct platform_device *pdev)
-{
-        struct s3c_pl330_dmac *s3c_pl330_dmac;
-        struct s3c_pl330_platdata *pl330pd;
-        struct pl330_info *pl330_info;
-        struct resource *res;
-        int i, ret, irq;
-
-        pl330pd = pdev->dev.platform_data;
-
-        /* Can't do without the list of _32_ peripherals */
-        if (!pl330pd || !pl330pd->peri) {
-                dev_err(&pdev->dev, "platform data missing!\n");
-                return -ENODEV;
-        }
-
-        pl330_info = kzalloc(sizeof(*pl330_info), GFP_KERNEL);
-        if (!pl330_info)
-                return -ENOMEM;
-
-        pl330_info->pl330_data = NULL;
-        pl330_info->dev = &pdev->dev;
-
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (!res) {
-                ret = -ENODEV;
-                goto probe_err1;
-        }
-
-        request_mem_region(res->start, resource_size(res), pdev->name);
-
-        pl330_info->base = ioremap(res->start, resource_size(res));
-        if (!pl330_info->base) {
-                ret = -ENXIO;
-                goto probe_err2;
-        }
-
-        irq = platform_get_irq(pdev, 0);
-        if (irq < 0) {
-                ret = irq;
-                goto probe_err3;
-        }
-
-        ret = request_irq(irq, pl330_irq_handler, 0,
-                        dev_name(&pdev->dev), pl330_info);
-        if (ret)
-                goto probe_err4;
-
-        /* Allocate a new DMAC */
-        s3c_pl330_dmac = kmalloc(sizeof(*s3c_pl330_dmac), GFP_KERNEL);
-        if (!s3c_pl330_dmac) {
-                ret = -ENOMEM;
-                goto probe_err5;
-        }
-
-        /* Get operation clock and enable it */
-        s3c_pl330_dmac->clk = clk_get(&pdev->dev, "pdma");
-        if (IS_ERR(s3c_pl330_dmac->clk)) {
-                dev_err(&pdev->dev, "Cannot get operation clock.\n");
-                ret = -EINVAL;
-                goto probe_err6;
-        }
-        clk_enable(s3c_pl330_dmac->clk);
-
-        ret = pl330_add(pl330_info);
-        if (ret)
-                goto probe_err7;
-
-        /* Hook the info */
-        s3c_pl330_dmac->pi = pl330_info;
-
-        /* No busy channels */
-        s3c_pl330_dmac->busy_chan = 0;
-
-        s3c_pl330_dmac->kmcache = kmem_cache_create(dev_name(&pdev->dev),
-                                sizeof(struct s3c_pl330_xfer), 0, 0, NULL);
-
-        if (!s3c_pl330_dmac->kmcache) {
-                ret = -ENOMEM;
-                goto probe_err8;
-        }
-
-        /* Get the list of peripherals */
-        s3c_pl330_dmac->peri = pl330pd->peri;
-
-        /* Attach to the list of DMACs */
-        list_add_tail(&s3c_pl330_dmac->node, &dmac_list);
-
-        /* Create a channel for each peripheral in the DMAC
-         * that is, if it doesn't already exist
-         */
-        for (i = 0; i < PL330_MAX_PERI; i++)
-                if (s3c_pl330_dmac->peri[i] != DMACH_MAX)
-                        chan_add(s3c_pl330_dmac->peri[i]);
-
-        printk(KERN_INFO
-                "Loaded driver for PL330 DMAC-%d %s\n", pdev->id, pdev->name);
-        printk(KERN_INFO
-                "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
-                pl330_info->pcfg.data_buf_dep,
-                pl330_info->pcfg.data_bus_width / 8, pl330_info->pcfg.num_chan,
-                pl330_info->pcfg.num_peri, pl330_info->pcfg.num_events);
-
-        return 0;
-
-probe_err8:
-        pl330_del(pl330_info);
-probe_err7:
-        clk_disable(s3c_pl330_dmac->clk);
-        clk_put(s3c_pl330_dmac->clk);
-probe_err6:
-        kfree(s3c_pl330_dmac);
-probe_err5:
-        free_irq(irq, pl330_info);
-probe_err4:
-probe_err3:
-        iounmap(pl330_info->base);
-probe_err2:
-        release_mem_region(res->start, resource_size(res));
-probe_err1:
-        kfree(pl330_info);
-
-        return ret;
-}
-
-static int pl330_remove(struct platform_device *pdev)
-{
-        struct s3c_pl330_dmac *dmac, *d;
-        struct s3c_pl330_chan *ch;
-        unsigned long flags;
-        int del, found;
-
-        if (!pdev->dev.platform_data)
-                return -EINVAL;
-
-        spin_lock_irqsave(&res_lock, flags);
-
-        found = 0;
-        list_for_each_entry(d, &dmac_list, node)
-                if (d->pi->dev == &pdev->dev) {
-                        found = 1;
-                        break;
-                }
-
-        if (!found) {
-                spin_unlock_irqrestore(&res_lock, flags);
-                return 0;
-        }
-
-        dmac = d;
-
-        /* Remove all Channels that are managed only by this DMAC */
-        list_for_each_entry(ch, &chan_list, node) {
-
-                /* Only channels that are handled by this DMAC */
-                if (iface_of_dmac(dmac, ch->id))
-                        del = 1;
-                else
-                        continue;
-
-                /* Don't remove if some other DMAC has it too */
-                list_for_each_entry(d, &dmac_list, node)
-                        if (d != dmac && iface_of_dmac(d, ch->id)) {
-                                del = 0;
-                                break;
-                        }
-
-                if (del) {
-                        spin_unlock_irqrestore(&res_lock, flags);
-                        s3c2410_dma_free(ch->id, ch->client);
-                        spin_lock_irqsave(&res_lock, flags);
-                        list_del(&ch->node);
-                        kfree(ch);
-                }
-        }
-
-        /* Disable operation clock */
-        clk_disable(dmac->clk);
-        clk_put(dmac->clk);
-
-        /* Remove the DMAC */
-        list_del(&dmac->node);
-        kfree(dmac);
-
-        spin_unlock_irqrestore(&res_lock, flags);
-
-        return 0;
-}
-
-static struct platform_driver pl330_driver = {
-        .driver         = {
-                .owner  = THIS_MODULE,
-                .name   = "s3c-pl330",
-        },
-        .probe          = pl330_probe,
-        .remove         = pl330_remove,
-};
-
-static int __init pl330_init(void)
-{
-        return platform_driver_register(&pl330_driver);
-}
-module_init(pl330_init);
-
-static void __exit pl330_exit(void)
-{
-        platform_driver_unregister(&pl330_driver);
-        return;
-}
-module_exit(pl330_exit);
-
-MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
-MODULE_DESCRIPTION("Driver for PL330 DMA Controller");
-MODULE_LICENSE("GPL");