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-rw-r--r--arch/arm/mach-s5pv310/Kconfig39
-rw-r--r--arch/arm/mach-s5pv310/Makefile2
-rw-r--r--arch/arm/mach-s5pv310/setup-sdhci-gpio.c152
-rw-r--r--arch/arm/mach-s5pv310/setup-sdhci.c69
4 files changed, 262 insertions, 0 deletions
diff --git a/arch/arm/mach-s5pv310/Kconfig b/arch/arm/mach-s5pv310/Kconfig
index 9941852b7a06..8cb3dc52b623 100644
--- a/arch/arm/mach-s5pv310/Kconfig
+++ b/arch/arm/mach-s5pv310/Kconfig
@@ -24,6 +24,17 @@ config S5PV310_SETUP_I2C2
24 help 24 help
25 Common setup code for i2c bus 2. 25 Common setup code for i2c bus 2.
26 26
27config S5PV310_SETUP_SDHCI
28 bool
29 select S5PV310_SETUP_SDHCI_GPIO
30 help
31 Internal helper functions for S5PV310 based SDHCI systems.
32
33config S5PV310_SETUP_SDHCI_GPIO
34 bool
35 help
36 Common setup code for SDHCI gpio.
37
27# machine support 38# machine support
28 39
29menu "S5PC210 Machines" 40menu "S5PC210 Machines"
@@ -33,6 +44,11 @@ config MACH_SMDKC210
33 select CPU_S5PV310 44 select CPU_S5PV310
34 select S3C_DEV_RTC 45 select S3C_DEV_RTC
35 select S3C_DEV_WDT 46 select S3C_DEV_WDT
47 select S3C_DEV_HSMMC
48 select S3C_DEV_HSMMC1
49 select S3C_DEV_HSMMC2
50 select S3C_DEV_HSMMC3
51 select S5PV310_SETUP_SDHCI
36 help 52 help
37 Machine support for Samsung SMDKC210 53 Machine support for Samsung SMDKC210
38 S5PC210(MCP) is one of package option of S5PV310 54 S5PC210(MCP) is one of package option of S5PV310
@@ -53,9 +69,32 @@ config MACH_SMDKV310
53 select CPU_S5PV310 69 select CPU_S5PV310
54 select S3C_DEV_RTC 70 select S3C_DEV_RTC
55 select S3C_DEV_WDT 71 select S3C_DEV_WDT
72 select S3C_DEV_HSMMC
73 select S3C_DEV_HSMMC1
74 select S3C_DEV_HSMMC2
75 select S3C_DEV_HSMMC3
76 select S5PV310_SETUP_SDHCI
56 help 77 help
57 Machine support for Samsung SMDKV310 78 Machine support for Samsung SMDKV310
58 79
59endmenu 80endmenu
60 81
82comment "Configuration for HSMMC bus width"
83
84menu "Use 8-bit bus width"
85
86config S5PV310_SDHCI_CH0_8BIT
87 bool "Channel 0 with 8-bit bus"
88 help
89 Support HSMMC Channel 0 8-bit bus.
90 If selected, Channel 1 is disabled.
91
92config S5PV310_SDHCI_CH2_8BIT
93 bool "Channel 2 with 8-bit bus"
94 help
95 Support HSMMC Channel 2 8-bit bus.
96 If selected, Channel 3 is disabled.
97
98endmenu
99
61endif 100endif
diff --git a/arch/arm/mach-s5pv310/Makefile b/arch/arm/mach-s5pv310/Makefile
index aefb14f23b8a..c89b6b024801 100644
--- a/arch/arm/mach-s5pv310/Makefile
+++ b/arch/arm/mach-s5pv310/Makefile
@@ -29,3 +29,5 @@ obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o
29 29
30obj-$(CONFIG_S5PV310_SETUP_I2C1) += setup-i2c1.o 30obj-$(CONFIG_S5PV310_SETUP_I2C1) += setup-i2c1.o
31obj-$(CONFIG_S5PV310_SETUP_I2C2) += setup-i2c2.o 31obj-$(CONFIG_S5PV310_SETUP_I2C2) += setup-i2c2.o
32obj-$(CONFIG_S5PV310_SETUP_SDHCI) += setup-sdhci.o
33obj-$(CONFIG_S5PV310_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
diff --git a/arch/arm/mach-s5pv310/setup-sdhci-gpio.c b/arch/arm/mach-s5pv310/setup-sdhci-gpio.c
new file mode 100644
index 000000000000..86d38cc49135
--- /dev/null
+++ b/arch/arm/mach-s5pv310/setup-sdhci-gpio.c
@@ -0,0 +1,152 @@
1/* linux/arch/arm/mach-s5pv310/setup-sdhci-gpio.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV310 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
17#include <linux/io.h>
18#include <linux/gpio.h>
19#include <linux/mmc/host.h>
20#include <linux/mmc/card.h>
21
22#include <plat/gpio-cfg.h>
23#include <plat/regs-sdhci.h>
24#include <plat/sdhci.h>
25
26void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
27{
28 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
29 unsigned int gpio;
30
31 /* Set all the necessary GPK0[0:1] pins to special-function 2 */
32 for (gpio = S5PV310_GPK0(0); gpio < S5PV310_GPK0(2); gpio++) {
33 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
34 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
35 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
36 }
37
38 switch (width) {
39 case 8:
40 for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6); gpio++) {
41 /* Data pin GPK1[3:6] to special-funtion 3 */
42 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
43 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
44 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
45 }
46 case 4:
47 for (gpio = S5PV310_GPK0(3); gpio <= S5PV310_GPK0(6); gpio++) {
48 /* Data pin GPK0[3:6] to special-funtion 2 */
49 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
50 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
51 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
52 }
53 default:
54 break;
55 }
56
57 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
58 s3c_gpio_cfgpin(S5PV310_GPK0(2), S3C_GPIO_SFN(2));
59 s3c_gpio_setpull(S5PV310_GPK0(2), S3C_GPIO_PULL_UP);
60 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
61 }
62}
63
64void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
65{
66 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
67 unsigned int gpio;
68
69 /* Set all the necessary GPK1[0:1] pins to special-function 2 */
70 for (gpio = S5PV310_GPK1(0); gpio < S5PV310_GPK1(2); gpio++) {
71 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
72 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
73 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
74 }
75
76 for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6); gpio++) {
77 /* Data pin GPK1[3:6] to special-function 2 */
78 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
79 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
80 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
81 }
82
83 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
84 s3c_gpio_cfgpin(S5PV310_GPK1(2), S3C_GPIO_SFN(2));
85 s3c_gpio_setpull(S5PV310_GPK1(2), S3C_GPIO_PULL_UP);
86 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
87 }
88}
89
90void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
91{
92 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
93 unsigned int gpio;
94
95 /* Set all the necessary GPK2[0:1] pins to special-function 2 */
96 for (gpio = S5PV310_GPK2(0); gpio < S5PV310_GPK2(2); gpio++) {
97 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
98 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
99 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
100 }
101
102 switch (width) {
103 case 8:
104 for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6); gpio++) {
105 /* Data pin GPK3[3:6] to special-function 3 */
106 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
107 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
108 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
109 }
110 case 4:
111 for (gpio = S5PV310_GPK2(3); gpio <= S5PV310_GPK2(6); gpio++) {
112 /* Data pin GPK2[3:6] to special-function 2 */
113 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
114 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
115 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
116 }
117 default:
118 break;
119 }
120
121 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
122 s3c_gpio_cfgpin(S5PV310_GPK2(2), S3C_GPIO_SFN(2));
123 s3c_gpio_setpull(S5PV310_GPK2(2), S3C_GPIO_PULL_UP);
124 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
125 }
126}
127
128void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
129{
130 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
131 unsigned int gpio;
132
133 /* Set all the necessary GPK3[0:1] pins to special-function 2 */
134 for (gpio = S5PV310_GPK3(0); gpio < S5PV310_GPK3(2); gpio++) {
135 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
136 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
137 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
138 }
139
140 for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6); gpio++) {
141 /* Data pin GPK3[3:6] to special-function 2 */
142 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
143 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
144 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
145 }
146
147 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
148 s3c_gpio_cfgpin(S5PV310_GPK3(2), S3C_GPIO_SFN(2));
149 s3c_gpio_setpull(S5PV310_GPK3(2), S3C_GPIO_PULL_UP);
150 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
151 }
152}
diff --git a/arch/arm/mach-s5pv310/setup-sdhci.c b/arch/arm/mach-s5pv310/setup-sdhci.c
new file mode 100644
index 000000000000..db8358fc4662
--- /dev/null
+++ b/arch/arm/mach-s5pv310/setup-sdhci.c
@@ -0,0 +1,69 @@
1/* linux/arch/arm/mach-s5pv310/setup-sdhci.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV310 - Helper functions for settign up SDHCI device(s) (HSMMC)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
17#include <linux/io.h>
18
19#include <linux/mmc/card.h>
20#include <linux/mmc/host.h>
21
22#include <plat/regs-sdhci.h>
23
24/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
25
26char *s5pv310_hsmmc_clksrcs[4] = {
27 [0] = NULL,
28 [1] = NULL,
29 [2] = "sclk_mmc", /* mmc_bus */
30 [3] = NULL,
31};
32
33void s5pv310_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r,
34 struct mmc_ios *ios, struct mmc_card *card)
35{
36 u32 ctrl2, ctrl3;
37
38 /* don't need to alter anything acording to card-type */
39
40 ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
41
42 /* select base clock source to HCLK */
43
44 ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
45
46 /*
47 * clear async mode, enable conflict mask, rx feedback ctrl, SD
48 * clk hold and no use debounce count
49 */
50
51 ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
52 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
53 S3C_SDHCI_CTRL2_ENFBCLKRX |
54 S3C_SDHCI_CTRL2_DFCNT_NONE |
55 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
56
57 /* Tx and Rx feedback clock delay control */
58
59 if (ios->clock < 25 * 1000000)
60 ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
61 S3C_SDHCI_CTRL3_FCSEL2 |
62 S3C_SDHCI_CTRL3_FCSEL1 |
63 S3C_SDHCI_CTRL3_FCSEL0);
64 else
65 ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
66
67 writel(ctrl2, r + S3C_SDHCI_CONTROL2);
68 writel(ctrl3, r + S3C_SDHCI_CONTROL3);
69}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 22:29:00 -0500