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-rw-r--r--arch/arm/mach-exynos/Kconfig5
-rw-r--r--arch/arm/mach-exynos/Makefile1
-rw-r--r--arch/arm/mach-exynos/clock.c73
-rw-r--r--arch/arm/mach-exynos/include/mach/irqs.h3
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h7
-rw-r--r--arch/arm/mach-exynos/include/mach/spi-clocks.h16
-rw-r--r--arch/arm/mach-exynos/setup-spi.c72
-rw-r--r--arch/arm/mach-s5p64x0/Kconfig24
-rw-r--r--arch/arm/mach-s5p64x0/Makefile1
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6440.c72
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6450.c72
-rw-r--r--arch/arm/mach-s5p64x0/cpu.c9
-rw-r--r--arch/arm/mach-s5p64x0/mach-smdk6440.c25
-rw-r--r--arch/arm/mach-s5p64x0/mach-smdk6450.c26
-rw-r--r--arch/arm/mach-s5p64x0/setup-sdhci-gpio.c104
-rw-r--r--arch/arm/plat-samsung/include/plat/sdhci.h44
16 files changed, 463 insertions, 91 deletions
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 0afcc3b0f870..c925fecfa50a 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -148,6 +148,11 @@ config EXYNOS4_SETUP_USB_PHY
148 help 148 help
149 Common setup code for USB PHY controller 149 Common setup code for USB PHY controller
150 150
151config EXYNOS4_SETUP_SPI
152 bool
153 help
154 Common setup code for SPI GPIO configurations.
155
151# machine support 156# machine support
152 157
153if ARCH_EXYNOS4 158if ARCH_EXYNOS4
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 57e529620804..979fdd3d14e6 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -60,3 +60,4 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o
60obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o 60obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o
61obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o 61obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
62obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o 62obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o
63obj-$(CONFIG_EXYNOS4_SETUP_SPI) += setup-spi.o
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
index 5d8d4831e244..da50b1af7568 100644
--- a/arch/arm/mach-exynos/clock.c
+++ b/arch/arm/mach-exynos/clock.c
@@ -1111,36 +1111,6 @@ static struct clksrc_clk clksrcs[] = {
1111 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 }, 1111 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
1112 }, { 1112 }, {
1113 .clk = { 1113 .clk = {
1114 .name = "sclk_spi",
1115 .devname = "s3c64xx-spi.0",
1116 .enable = exynos4_clksrc_mask_peril1_ctrl,
1117 .ctrlbit = (1 << 16),
1118 },
1119 .sources = &clkset_group,
1120 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1121 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1122 }, {
1123 .clk = {
1124 .name = "sclk_spi",
1125 .devname = "s3c64xx-spi.1",
1126 .enable = exynos4_clksrc_mask_peril1_ctrl,
1127 .ctrlbit = (1 << 20),
1128 },
1129 .sources = &clkset_group,
1130 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1131 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1132 }, {
1133 .clk = {
1134 .name = "sclk_spi",
1135 .devname = "s3c64xx-spi.2",
1136 .enable = exynos4_clksrc_mask_peril1_ctrl,
1137 .ctrlbit = (1 << 24),
1138 },
1139 .sources = &clkset_group,
1140 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1141 .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1142 }, {
1143 .clk = {
1144 .name = "sclk_fimg2d", 1114 .name = "sclk_fimg2d",
1145 }, 1115 },
1146 .sources = &clkset_mout_g2d, 1116 .sources = &clkset_mout_g2d,
@@ -1257,6 +1227,42 @@ static struct clksrc_clk clk_sclk_mmc3 = {
1257 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, 1227 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1258}; 1228};
1259 1229
1230static struct clksrc_clk clk_sclk_spi0 = {
1231 .clk = {
1232 .name = "sclk_spi",
1233 .devname = "s3c64xx-spi.0",
1234 .enable = exynos4_clksrc_mask_peril1_ctrl,
1235 .ctrlbit = (1 << 16),
1236 },
1237 .sources = &clkset_group,
1238 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1239 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1240};
1241
1242static struct clksrc_clk clk_sclk_spi1 = {
1243 .clk = {
1244 .name = "sclk_spi",
1245 .devname = "s3c64xx-spi.1",
1246 .enable = exynos4_clksrc_mask_peril1_ctrl,
1247 .ctrlbit = (1 << 20),
1248 },
1249 .sources = &clkset_group,
1250 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1251 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1252};
1253
1254static struct clksrc_clk clk_sclk_spi2 = {
1255 .clk = {
1256 .name = "sclk_spi",
1257 .devname = "s3c64xx-spi.2",
1258 .enable = exynos4_clksrc_mask_peril1_ctrl,
1259 .ctrlbit = (1 << 24),
1260 },
1261 .sources = &clkset_group,
1262 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1263 .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1264};
1265
1260/* Clock initialization code */ 1266/* Clock initialization code */
1261static struct clksrc_clk *sysclks[] = { 1267static struct clksrc_clk *sysclks[] = {
1262 &clk_mout_apll, 1268 &clk_mout_apll,
@@ -1305,6 +1311,10 @@ static struct clksrc_clk *clksrc_cdev[] = {
1305 &clk_sclk_mmc1, 1311 &clk_sclk_mmc1,
1306 &clk_sclk_mmc2, 1312 &clk_sclk_mmc2,
1307 &clk_sclk_mmc3, 1313 &clk_sclk_mmc3,
1314 &clk_sclk_spi0,
1315 &clk_sclk_spi1,
1316 &clk_sclk_spi2,
1317
1308}; 1318};
1309 1319
1310static struct clk_lookup exynos4_clk_lookup[] = { 1320static struct clk_lookup exynos4_clk_lookup[] = {
@@ -1318,6 +1328,9 @@ static struct clk_lookup exynos4_clk_lookup[] = {
1318 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk), 1328 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
1319 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0), 1329 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),
1320 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1), 1330 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),
1331 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &clk_sclk_spi0.clk),
1332 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &clk_sclk_spi1.clk),
1333 CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &clk_sclk_spi2.clk),
1321}; 1334};
1322 1335
1323static int xtal_rate; 1336static int xtal_rate;
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 713dd5251c64..f77bce04789a 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -72,6 +72,9 @@
72#define IRQ_IIC5 IRQ_SPI(63) 72#define IRQ_IIC5 IRQ_SPI(63)
73#define IRQ_IIC6 IRQ_SPI(64) 73#define IRQ_IIC6 IRQ_SPI(64)
74#define IRQ_IIC7 IRQ_SPI(65) 74#define IRQ_IIC7 IRQ_SPI(65)
75#define IRQ_SPI0 IRQ_SPI(66)
76#define IRQ_SPI1 IRQ_SPI(67)
77#define IRQ_SPI2 IRQ_SPI(68)
75 78
76#define IRQ_USB_HOST IRQ_SPI(70) 79#define IRQ_USB_HOST IRQ_SPI(70)
77#define IRQ_USB_HSOTG IRQ_SPI(71) 80#define IRQ_USB_HSOTG IRQ_SPI(71)
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 058541d45af0..e6ba01d115f6 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -87,6 +87,10 @@
87#define EXYNOS4_PA_SYSMMU_TV 0x12E20000 87#define EXYNOS4_PA_SYSMMU_TV 0x12E20000
88#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000 88#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000
89#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000 89#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000
90#define EXYNOS4_PA_SPI0 0x13920000
91#define EXYNOS4_PA_SPI1 0x13930000
92#define EXYNOS4_PA_SPI2 0x13940000
93
90 94
91#define EXYNOS4_PA_GPIO1 0x11400000 95#define EXYNOS4_PA_GPIO1 0x11400000
92#define EXYNOS4_PA_GPIO2 0x11000000 96#define EXYNOS4_PA_GPIO2 0x11000000
@@ -148,6 +152,9 @@
148#define S3C_PA_RTC EXYNOS4_PA_RTC 152#define S3C_PA_RTC EXYNOS4_PA_RTC
149#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG 153#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
150#define S3C_PA_UART EXYNOS4_PA_UART 154#define S3C_PA_UART EXYNOS4_PA_UART
155#define S3C_PA_SPI0 EXYNOS4_PA_SPI0
156#define S3C_PA_SPI1 EXYNOS4_PA_SPI1
157#define S3C_PA_SPI2 EXYNOS4_PA_SPI2
151 158
152#define S5P_PA_CHIPID EXYNOS4_PA_CHIPID 159#define S5P_PA_CHIPID EXYNOS4_PA_CHIPID
153#define S5P_PA_EHCI EXYNOS4_PA_EHCI 160#define S5P_PA_EHCI EXYNOS4_PA_EHCI
diff --git a/arch/arm/mach-exynos/include/mach/spi-clocks.h b/arch/arm/mach-exynos/include/mach/spi-clocks.h
new file mode 100644
index 000000000000..576efdf6d091
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/spi-clocks.h
@@ -0,0 +1,16 @@
1/* linux/arch/arm/mach-exynos4/include/mach/spi-clocks.h
2 *
3 * Copyright (C) 2011 Samsung Electronics Co. Ltd.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#ifndef __ASM_ARCH_SPI_CLKS_H
11#define __ASM_ARCH_SPI_CLKS_H __FILE__
12
13/* Must source from SCLK_SPI */
14#define EXYNOS4_SPI_SRCCLK_SCLK 0
15
16#endif /* __ASM_ARCH_SPI_CLKS_H */
diff --git a/arch/arm/mach-exynos/setup-spi.c b/arch/arm/mach-exynos/setup-spi.c
new file mode 100644
index 000000000000..833ff40ee0e8
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-spi.c
@@ -0,0 +1,72 @@
1/* linux/arch/arm/mach-exynos4/setup-spi.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/gpio.h>
12#include <linux/platform_device.h>
13
14#include <plat/gpio-cfg.h>
15#include <plat/s3c64xx-spi.h>
16
17#ifdef CONFIG_S3C64XX_DEV_SPI0
18struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
19 .fifo_lvl_mask = 0x1ff,
20 .rx_lvl_offset = 15,
21 .high_speed = 1,
22 .clk_from_cmu = true,
23 .tx_st_done = 25,
24};
25
26int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
27{
28 s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2));
29 s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP);
30 s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2,
31 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
32 return 0;
33}
34#endif
35
36#ifdef CONFIG_S3C64XX_DEV_SPI1
37struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
38 .fifo_lvl_mask = 0x7f,
39 .rx_lvl_offset = 15,
40 .high_speed = 1,
41 .clk_from_cmu = true,
42 .tx_st_done = 25,
43};
44
45int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
46{
47 s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2));
48 s3c_gpio_setpull(EXYNOS4_GPB(4), S3C_GPIO_PULL_UP);
49 s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2,
50 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
51 return 0;
52}
53#endif
54
55#ifdef CONFIG_S3C64XX_DEV_SPI2
56struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = {
57 .fifo_lvl_mask = 0x7f,
58 .rx_lvl_offset = 15,
59 .high_speed = 1,
60 .clk_from_cmu = true,
61 .tx_st_done = 25,
62};
63
64int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
65{
66 s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5));
67 s3c_gpio_setpull(EXYNOS4_GPC1(1), S3C_GPIO_PULL_UP);
68 s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2,
69 S3C_GPIO_SFN(5), S3C_GPIO_PULL_UP);
70 return 0;
71}
72#endif
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
index dd8c85ef6dab..c87f6108eeb1 100644
--- a/arch/arm/mach-s5p64x0/Kconfig
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -41,6 +41,11 @@ config S5P64X0_SETUP_SPI
41 help 41 help
42 Common setup code for SPI GPIO configurations 42 Common setup code for SPI GPIO configurations
43 43
44config S5P64X0_SETUP_SDHCI_GPIO
45 bool
46 help
47 Common setup code for SDHCI gpio.
48
44# machine support 49# machine support
45 50
46config MACH_SMDK6440 51config MACH_SMDK6440
@@ -50,12 +55,16 @@ config MACH_SMDK6440
50 select S3C_DEV_I2C1 55 select S3C_DEV_I2C1
51 select S3C_DEV_RTC 56 select S3C_DEV_RTC
52 select S3C_DEV_WDT 57 select S3C_DEV_WDT
58 select S3C_DEV_HSMMC
59 select S3C_DEV_HSMMC1
60 select S3C_DEV_HSMMC2
53 select SAMSUNG_DEV_ADC 61 select SAMSUNG_DEV_ADC
54 select SAMSUNG_DEV_BACKLIGHT 62 select SAMSUNG_DEV_BACKLIGHT
55 select SAMSUNG_DEV_PWM 63 select SAMSUNG_DEV_PWM
56 select SAMSUNG_DEV_TS 64 select SAMSUNG_DEV_TS
57 select S5P64X0_SETUP_FB_24BPP 65 select S5P64X0_SETUP_FB_24BPP
58 select S5P64X0_SETUP_I2C1 66 select S5P64X0_SETUP_I2C1
67 select S5P64X0_SETUP_SDHCI_GPIO
59 help 68 help
60 Machine support for the Samsung SMDK6440 69 Machine support for the Samsung SMDK6440
61 70
@@ -66,13 +75,28 @@ config MACH_SMDK6450
66 select S3C_DEV_I2C1 75 select S3C_DEV_I2C1
67 select S3C_DEV_RTC 76 select S3C_DEV_RTC
68 select S3C_DEV_WDT 77 select S3C_DEV_WDT
78 select S3C_DEV_HSMMC
79 select S3C_DEV_HSMMC1
80 select S3C_DEV_HSMMC2
69 select SAMSUNG_DEV_ADC 81 select SAMSUNG_DEV_ADC
70 select SAMSUNG_DEV_BACKLIGHT 82 select SAMSUNG_DEV_BACKLIGHT
71 select SAMSUNG_DEV_PWM 83 select SAMSUNG_DEV_PWM
72 select SAMSUNG_DEV_TS 84 select SAMSUNG_DEV_TS
73 select S5P64X0_SETUP_FB_24BPP 85 select S5P64X0_SETUP_FB_24BPP
74 select S5P64X0_SETUP_I2C1 86 select S5P64X0_SETUP_I2C1
87 select S5P64X0_SETUP_SDHCI_GPIO
75 help 88 help
76 Machine support for the Samsung SMDK6450 89 Machine support for the Samsung SMDK6450
77 90
91menu "Use 8-bit SDHCI bus width"
92
93config S5P64X0_SD_CH1_8BIT
94 bool "SDHCI Channel 1 (Slot 1)"
95 depends on MACH_SMDK6450 || MACH_SMDK6440
96 help
97 Support SDHCI Channel 1 8-bit bus.
98 If selected, Channel 2 is disabled.
99
100endmenu
101
78endif 102endif
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile
index a7d7a499d99e..b44cc044b3c3 100644
--- a/arch/arm/mach-s5p64x0/Makefile
+++ b/arch/arm/mach-s5p64x0/Makefile
@@ -30,3 +30,4 @@ obj-y += dev-audio.o
30obj-$(CONFIG_S5P64X0_SETUP_I2C1) += setup-i2c1.o 30obj-$(CONFIG_S5P64X0_SETUP_I2C1) += setup-i2c1.o
31obj-$(CONFIG_S5P64X0_SETUP_FB_24BPP) += setup-fb-24bpp.o 31obj-$(CONFIG_S5P64X0_SETUP_FB_24BPP) += setup-fb-24bpp.o
32obj-$(CONFIG_S5P64X0_SETUP_SPI) += setup-spi.o 32obj-$(CONFIG_S5P64X0_SETUP_SPI) += setup-spi.o
33obj-$(CONFIG_S5P64X0_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index 73c7cc9ef0dd..c041ad7fbd60 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -379,36 +379,6 @@ static struct clksrc_sources clkset_audio = {
379static struct clksrc_clk clksrcs[] = { 379static struct clksrc_clk clksrcs[] = {
380 { 380 {
381 .clk = { 381 .clk = {
382 .name = "sclk_mmc",
383 .devname = "s3c-sdhci.0",
384 .ctrlbit = (1 << 24),
385 .enable = s5p64x0_sclk_ctrl,
386 },
387 .sources = &clkset_group1,
388 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
389 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
390 }, {
391 .clk = {
392 .name = "sclk_mmc",
393 .devname = "s3c-sdhci.1",
394 .ctrlbit = (1 << 25),
395 .enable = s5p64x0_sclk_ctrl,
396 },
397 .sources = &clkset_group1,
398 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
399 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
400 }, {
401 .clk = {
402 .name = "sclk_mmc",
403 .devname = "s3c-sdhci.2",
404 .ctrlbit = (1 << 26),
405 .enable = s5p64x0_sclk_ctrl,
406 },
407 .sources = &clkset_group1,
408 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
409 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
410 }, {
411 .clk = {
412 .name = "sclk_post", 382 .name = "sclk_post",
413 .ctrlbit = (1 << 10), 383 .ctrlbit = (1 << 10),
414 .enable = s5p64x0_sclk_ctrl, 384 .enable = s5p64x0_sclk_ctrl,
@@ -446,6 +416,42 @@ static struct clksrc_clk clksrcs[] = {
446 }, 416 },
447}; 417};
448 418
419static struct clksrc_clk clk_sclk_mmc0 = {
420 .clk = {
421 .name = "sclk_mmc",
422 .devname = "s3c-sdhci.0",
423 .ctrlbit = (1 << 24),
424 .enable = s5p64x0_sclk_ctrl,
425 },
426 .sources = &clkset_group1,
427 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
428 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
429};
430
431static struct clksrc_clk clk_sclk_mmc1 = {
432 .clk = {
433 .name = "sclk_mmc",
434 .devname = "s3c-sdhci.1",
435 .ctrlbit = (1 << 25),
436 .enable = s5p64x0_sclk_ctrl,
437 },
438 .sources = &clkset_group1,
439 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
440 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
441};
442
443static struct clksrc_clk clk_sclk_mmc2 = {
444 .clk = {
445 .name = "sclk_mmc",
446 .devname = "s3c-sdhci.2",
447 .ctrlbit = (1 << 26),
448 .enable = s5p64x0_sclk_ctrl,
449 },
450 .sources = &clkset_group1,
451 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
452 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
453};
454
449static struct clksrc_clk clk_sclk_uclk = { 455static struct clksrc_clk clk_sclk_uclk = {
450 .clk = { 456 .clk = {
451 .name = "uclk1", 457 .name = "uclk1",
@@ -503,6 +509,9 @@ static struct clksrc_clk *clksrc_cdev[] = {
503 &clk_sclk_uclk, 509 &clk_sclk_uclk,
504 &clk_sclk_spi0, 510 &clk_sclk_spi0,
505 &clk_sclk_spi1, 511 &clk_sclk_spi1,
512 &clk_sclk_mmc0,
513 &clk_sclk_mmc1,
514 &clk_sclk_mmc2
506}; 515};
507 516
508static struct clk_lookup s5p6440_clk_lookup[] = { 517static struct clk_lookup s5p6440_clk_lookup[] = {
@@ -511,6 +520,9 @@ static struct clk_lookup s5p6440_clk_lookup[] = {
511 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), 520 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
512 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), 521 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
513 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), 522 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
523 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
524 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
525 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
514}; 526};
515 527
516void __init_or_cpufreq s5p6440_setup_clocks(void) 528void __init_or_cpufreq s5p6440_setup_clocks(void)
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index 50f90cbf7798..b5087cb6e818 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -413,36 +413,6 @@ static struct clksrc_clk clk_sclk_audio0 = {
413static struct clksrc_clk clksrcs[] = { 413static struct clksrc_clk clksrcs[] = {
414 { 414 {
415 .clk = { 415 .clk = {
416 .name = "sclk_mmc",
417 .devname = "s3c-sdhci.0",
418 .ctrlbit = (1 << 24),
419 .enable = s5p64x0_sclk_ctrl,
420 },
421 .sources = &clkset_group2,
422 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
423 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
424 }, {
425 .clk = {
426 .name = "sclk_mmc",
427 .devname = "s3c-sdhci.1",
428 .ctrlbit = (1 << 25),
429 .enable = s5p64x0_sclk_ctrl,
430 },
431 .sources = &clkset_group2,
432 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
433 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
434 }, {
435 .clk = {
436 .name = "sclk_mmc",
437 .devname = "s3c-sdhci.2",
438 .ctrlbit = (1 << 26),
439 .enable = s5p64x0_sclk_ctrl,
440 },
441 .sources = &clkset_group2,
442 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
443 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
444 }, {
445 .clk = {
446 .name = "sclk_fimc", 416 .name = "sclk_fimc",
447 .ctrlbit = (1 << 10), 417 .ctrlbit = (1 << 10),
448 .enable = s5p64x0_sclk_ctrl, 418 .enable = s5p64x0_sclk_ctrl,
@@ -507,6 +477,42 @@ static struct clksrc_clk clksrcs[] = {
507 }, 477 },
508}; 478};
509 479
480static struct clksrc_clk clk_sclk_mmc0 = {
481 .clk = {
482 .name = "sclk_mmc",
483 .devname = "s3c-sdhci.0",
484 .ctrlbit = (1 << 24),
485 .enable = s5p64x0_sclk_ctrl,
486 },
487 .sources = &clkset_group2,
488 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
489 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
490};
491
492static struct clksrc_clk clk_sclk_mmc1 = {
493 .clk = {
494 .name = "sclk_mmc",
495 .devname = "s3c-sdhci.1",
496 .ctrlbit = (1 << 25),
497 .enable = s5p64x0_sclk_ctrl,
498 },
499 .sources = &clkset_group2,
500 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
501 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
502};
503
504static struct clksrc_clk clk_sclk_mmc2 = {
505 .clk = {
506 .name = "sclk_mmc",
507 .devname = "s3c-sdhci.2",
508 .ctrlbit = (1 << 26),
509 .enable = s5p64x0_sclk_ctrl,
510 },
511 .sources = &clkset_group2,
512 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
513 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
514};
515
510static struct clksrc_clk clk_sclk_uclk = { 516static struct clksrc_clk clk_sclk_uclk = {
511 .clk = { 517 .clk = {
512 .name = "uclk1", 518 .name = "uclk1",
@@ -546,6 +552,9 @@ static struct clksrc_clk *clksrc_cdev[] = {
546 &clk_sclk_uclk, 552 &clk_sclk_uclk,
547 &clk_sclk_spi0, 553 &clk_sclk_spi0,
548 &clk_sclk_spi1, 554 &clk_sclk_spi1,
555 &clk_sclk_mmc0,
556 &clk_sclk_mmc1,
557 &clk_sclk_mmc2,
549}; 558};
550 559
551static struct clk_lookup s5p6450_clk_lookup[] = { 560static struct clk_lookup s5p6450_clk_lookup[] = {
@@ -554,6 +563,9 @@ static struct clk_lookup s5p6450_clk_lookup[] = {
554 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), 563 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
555 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), 564 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
556 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), 565 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
566 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
567 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
568 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
557}; 569};
558 570
559/* Clock initialization code */ 571/* Clock initialization code */
diff --git a/arch/arm/mach-s5p64x0/cpu.c b/arch/arm/mach-s5p64x0/cpu.c
index ecab40cf19ab..f6e24f3ef760 100644
--- a/arch/arm/mach-s5p64x0/cpu.c
+++ b/arch/arm/mach-s5p64x0/cpu.c
@@ -40,6 +40,7 @@
40#include <plat/s5p6450.h> 40#include <plat/s5p6450.h>
41#include <plat/adc-core.h> 41#include <plat/adc-core.h>
42#include <plat/fb-core.h> 42#include <plat/fb-core.h>
43#include <plat/sdhci.h>
43 44
44/* Initial IO mappings */ 45/* Initial IO mappings */
45 46
@@ -112,6 +113,10 @@ void __init s5p6440_map_io(void)
112 s3c_adc_setname("s3c64xx-adc"); 113 s3c_adc_setname("s3c64xx-adc");
113 s3c_fb_setname("s5p64x0-fb"); 114 s3c_fb_setname("s5p64x0-fb");
114 115
116 s5p64x0_default_sdhci0();
117 s5p64x0_default_sdhci1();
118 s5p6440_default_sdhci2();
119
115 iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc)); 120 iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
116 iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc)); 121 iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
117 init_consistent_dma_size(SZ_8M); 122 init_consistent_dma_size(SZ_8M);
@@ -123,6 +128,10 @@ void __init s5p6450_map_io(void)
123 s3c_adc_setname("s3c64xx-adc"); 128 s3c_adc_setname("s3c64xx-adc");
124 s3c_fb_setname("s5p64x0-fb"); 129 s3c_fb_setname("s5p64x0-fb");
125 130
131 s5p64x0_default_sdhci0();
132 s5p64x0_default_sdhci1();
133 s5p6450_default_sdhci2();
134
126 iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc)); 135 iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
127 iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc)); 136 iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
128 init_consistent_dma_size(SZ_8M); 137 init_consistent_dma_size(SZ_8M);
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 4a1250cd1356..fe168a087531 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -24,6 +24,7 @@
24#include <linux/gpio.h> 24#include <linux/gpio.h>
25#include <linux/pwm_backlight.h> 25#include <linux/pwm_backlight.h>
26#include <linux/fb.h> 26#include <linux/fb.h>
27#include <linux/mmc/host.h>
27 28
28#include <video/platform_lcd.h> 29#include <video/platform_lcd.h>
29 30
@@ -52,6 +53,7 @@
52#include <plat/backlight.h> 53#include <plat/backlight.h>
53#include <plat/fb.h> 54#include <plat/fb.h>
54#include <plat/regs-fb.h> 55#include <plat/regs-fb.h>
56#include <plat/sdhci.h>
55 57
56#define SMDK6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 58#define SMDK6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
57 S3C2410_UCON_RXILEVEL | \ 59 S3C2410_UCON_RXILEVEL | \
@@ -161,6 +163,25 @@ static struct platform_device *smdk6440_devices[] __initdata = {
161 &s5p6440_device_iis, 163 &s5p6440_device_iis,
162 &s3c_device_fb, 164 &s3c_device_fb,
163 &smdk6440_lcd_lte480wv, 165 &smdk6440_lcd_lte480wv,
166 &s3c_device_hsmmc0,
167 &s3c_device_hsmmc1,
168 &s3c_device_hsmmc2,
169};
170
171static struct s3c_sdhci_platdata smdk6440_hsmmc0_pdata __initdata = {
172 .cd_type = S3C_SDHCI_CD_NONE,
173};
174
175static struct s3c_sdhci_platdata smdk6440_hsmmc1_pdata __initdata = {
176 .cd_type = S3C_SDHCI_CD_INTERNAL,
177#if defined(CONFIG_S5P64X0_SD_CH1_8BIT)
178 .max_width = 8,
179 .host_caps = MMC_CAP_8_BIT_DATA,
180#endif
181};
182
183static struct s3c_sdhci_platdata smdk6440_hsmmc2_pdata __initdata = {
184 .cd_type = S3C_SDHCI_CD_NONE,
164}; 185};
165 186
166static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = { 187static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = {
@@ -234,6 +255,10 @@ static void __init smdk6440_machine_init(void)
234 s5p6440_set_lcd_interface(); 255 s5p6440_set_lcd_interface();
235 s3c_fb_set_platdata(&smdk6440_lcd_pdata); 256 s3c_fb_set_platdata(&smdk6440_lcd_pdata);
236 257
258 s3c_sdhci0_set_platdata(&smdk6440_hsmmc0_pdata);
259 s3c_sdhci1_set_platdata(&smdk6440_hsmmc1_pdata);
260 s3c_sdhci2_set_platdata(&smdk6440_hsmmc2_pdata);
261
237 platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices)); 262 platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices));
238} 263}
239 264
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index 0ab129ecf009..242a415dcf6b 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -24,6 +24,7 @@
24#include <linux/gpio.h> 24#include <linux/gpio.h>
25#include <linux/pwm_backlight.h> 25#include <linux/pwm_backlight.h>
26#include <linux/fb.h> 26#include <linux/fb.h>
27#include <linux/mmc/host.h>
27 28
28#include <video/platform_lcd.h> 29#include <video/platform_lcd.h>
29 30
@@ -52,6 +53,7 @@
52#include <plat/backlight.h> 53#include <plat/backlight.h>
53#include <plat/fb.h> 54#include <plat/fb.h>
54#include <plat/regs-fb.h> 55#include <plat/regs-fb.h>
56#include <plat/sdhci.h>
55 57
56#define SMDK6450_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 58#define SMDK6450_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
57 S3C2410_UCON_RXILEVEL | \ 59 S3C2410_UCON_RXILEVEL | \
@@ -179,10 +181,28 @@ static struct platform_device *smdk6450_devices[] __initdata = {
179 &s5p6450_device_iis0, 181 &s5p6450_device_iis0,
180 &s3c_device_fb, 182 &s3c_device_fb,
181 &smdk6450_lcd_lte480wv, 183 &smdk6450_lcd_lte480wv,
182 184 &s3c_device_hsmmc0,
185 &s3c_device_hsmmc1,
186 &s3c_device_hsmmc2,
183 /* s5p6450_device_spi0 will be added */ 187 /* s5p6450_device_spi0 will be added */
184}; 188};
185 189
190static struct s3c_sdhci_platdata smdk6450_hsmmc0_pdata __initdata = {
191 .cd_type = S3C_SDHCI_CD_NONE,
192};
193
194static struct s3c_sdhci_platdata smdk6450_hsmmc1_pdata __initdata = {
195 .cd_type = S3C_SDHCI_CD_NONE,
196#if defined(CONFIG_S5P64X0_SD_CH1_8BIT)
197 .max_width = 8,
198 .host_caps = MMC_CAP_8_BIT_DATA,
199#endif
200};
201
202static struct s3c_sdhci_platdata smdk6450_hsmmc2_pdata __initdata = {
203 .cd_type = S3C_SDHCI_CD_NONE,
204};
205
186static struct s3c2410_platform_i2c s5p6450_i2c0_data __initdata = { 206static struct s3c2410_platform_i2c s5p6450_i2c0_data __initdata = {
187 .flags = 0, 207 .flags = 0,
188 .slave_addr = 0x10, 208 .slave_addr = 0x10,
@@ -254,6 +274,10 @@ static void __init smdk6450_machine_init(void)
254 s5p6450_set_lcd_interface(); 274 s5p6450_set_lcd_interface();
255 s3c_fb_set_platdata(&smdk6450_lcd_pdata); 275 s3c_fb_set_platdata(&smdk6450_lcd_pdata);
256 276
277 s3c_sdhci0_set_platdata(&smdk6450_hsmmc0_pdata);
278 s3c_sdhci1_set_platdata(&smdk6450_hsmmc1_pdata);
279 s3c_sdhci2_set_platdata(&smdk6450_hsmmc2_pdata);
280
257 platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices)); 281 platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices));
258} 282}
259 283
diff --git a/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c b/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
new file mode 100644
index 000000000000..8410af0d12bf
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
@@ -0,0 +1,104 @@
1/* linux/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P64X0 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/platform_device.h>
14#include <linux/io.h>
15#include <linux/gpio.h>
16
17#include <mach/regs-gpio.h>
18#include <mach/regs-clock.h>
19
20#include <plat/gpio-cfg.h>
21#include <plat/sdhci.h>
22#include <plat/cpu.h>
23
24void s5p64x0_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
25{
26 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
27
28 /* Set all the necessary GPG pins to special-function 2 */
29 if (soc_is_s5p6450())
30 s3c_gpio_cfgrange_nopull(S5P6450_GPG(0), 2 + width,
31 S3C_GPIO_SFN(2));
32 else
33 s3c_gpio_cfgrange_nopull(S5P6440_GPG(0), 2 + width,
34 S3C_GPIO_SFN(2));
35
36 /* Set GPG[6] pin to special-function 2 - MMC0 CDn */
37 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
38 if (soc_is_s5p6450()) {
39 s3c_gpio_setpull(S5P6450_GPG(6), S3C_GPIO_PULL_UP);
40 s3c_gpio_cfgpin(S5P6450_GPG(6), S3C_GPIO_SFN(2));
41 } else {
42 s3c_gpio_setpull(S5P6440_GPG(6), S3C_GPIO_PULL_UP);
43 s3c_gpio_cfgpin(S5P6440_GPG(6), S3C_GPIO_SFN(2));
44 }
45 }
46}
47
48void s5p64x0_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
49{
50 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
51
52 /* Set GPH[0:1] pins to special-function 2 - CLK and CMD */
53 if (soc_is_s5p6450())
54 s3c_gpio_cfgrange_nopull(S5P6450_GPH(0), 2, S3C_GPIO_SFN(2));
55 else
56 s3c_gpio_cfgrange_nopull(S5P6440_GPH(0), 2 , S3C_GPIO_SFN(2));
57
58 switch (width) {
59 case 8:
60 /* Set data pins GPH[6:9] special-function 2 */
61 if (soc_is_s5p6450())
62 s3c_gpio_cfgrange_nopull(S5P6450_GPH(6), 4,
63 S3C_GPIO_SFN(2));
64 else
65 s3c_gpio_cfgrange_nopull(S5P6440_GPH(6), 4,
66 S3C_GPIO_SFN(2));
67 case 4:
68 /* set data pins GPH[2:5] special-function 2 */
69 if (soc_is_s5p6450())
70 s3c_gpio_cfgrange_nopull(S5P6450_GPH(2), 4,
71 S3C_GPIO_SFN(2));
72 else
73 s3c_gpio_cfgrange_nopull(S5P6440_GPH(2), 4,
74 S3C_GPIO_SFN(2));
75 default:
76 break;
77 }
78
79 /* Set GPG[6] pin to special-funtion 3 : MMC1 CDn */
80 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
81 if (soc_is_s5p6450()) {
82 s3c_gpio_setpull(S5P6450_GPG(6), S3C_GPIO_PULL_UP);
83 s3c_gpio_cfgpin(S5P6450_GPG(6), S3C_GPIO_SFN(3));
84 } else {
85 s3c_gpio_setpull(S5P6440_GPG(6), S3C_GPIO_PULL_UP);
86 s3c_gpio_cfgpin(S5P6440_GPG(6), S3C_GPIO_SFN(3));
87 }
88 }
89}
90
91void s5p6440_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
92{
93 /* Set GPC[4:5] pins to special-function 3 - CLK and CMD */
94 s3c_gpio_cfgrange_nopull(S5P6440_GPC(4), 2, S3C_GPIO_SFN(3));
95
96 /* Set data pins GPH[6:9] pins to special-function 3 */
97 s3c_gpio_cfgrange_nopull(S5P6440_GPH(6), 4, S3C_GPIO_SFN(3));
98}
99
100void s5p6450_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
101{
102 /* Set all the necessary GPG pins to special-function 3 */
103 s3c_gpio_cfgrange_nopull(S5P6450_GPG(7), 2 + width, S3C_GPIO_SFN(3));
104}
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index dcff7dd1ae8a..656dc00d30ed 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -123,6 +123,10 @@ extern void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
123extern void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *, int w); 123extern void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
124extern void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *, int w); 124extern void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
125extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w); 125extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
126extern void s5p64x0_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
127extern void s5p64x0_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
128extern void s5p6440_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
129extern void s5p6450_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
126 130
127/* S3C2416 SDHCI setup */ 131/* S3C2416 SDHCI setup */
128 132
@@ -146,6 +150,7 @@ static inline void s3c2416_default_sdhci0(void) { }
146static inline void s3c2416_default_sdhci1(void) { } 150static inline void s3c2416_default_sdhci1(void) { }
147 151
148#endif /* CONFIG_S3C2416_SETUP_SDHCI */ 152#endif /* CONFIG_S3C2416_SETUP_SDHCI */
153
149/* S3C64XX SDHCI setup */ 154/* S3C64XX SDHCI setup */
150 155
151#ifdef CONFIG_S3C64XX_SETUP_SDHCI 156#ifdef CONFIG_S3C64XX_SETUP_SDHCI
@@ -201,6 +206,45 @@ static inline void s3c6400_default_sdhci2(void) { }
201 206
202#endif /* CONFIG_S3C64XX_SETUP_SDHCI */ 207#endif /* CONFIG_S3C64XX_SETUP_SDHCI */
203 208
209/* S5P64X0 SDHCI setup */
210
211#ifdef CONFIG_S5P64X0_SETUP_SDHCI
212static inline void s5p64x0_default_sdhci0(void)
213{
214#ifdef CONFIG_S3C_DEV_HSMMC
215 s3c_hsmmc0_def_platdata.cfg_gpio = s5p64x0_setup_sdhci0_cfg_gpio;
216#endif
217}
218
219static inline void s5p64x0_default_sdhci1(void)
220{
221#ifdef CONFIG_S3C_DEV_HSMMC1
222 s3c_hsmmc1_def_platdata.cfg_gpio = s5p64x0_setup_sdhci1_cfg_gpio;
223#endif
224}
225
226static inline void s5p6440_default_sdhci2(void)
227{
228#ifdef CONFIG_S3C_DEV_HSMMC2
229 s3c_hsmmc2_def_platdata.cfg_gpio = s5p6440_setup_sdhci2_cfg_gpio;
230#endif
231}
232
233static inline void s5p6450_default_sdhci2(void)
234{
235#ifdef CONFIG_S3C_DEV_HSMMC2
236 s3c_hsmmc2_def_platdata.cfg_gpio = s5p6450_setup_sdhci2_cfg_gpio;
237#endif
238}
239
240#else
241static inline void s5p64x0_default_sdhci0(void) { }
242static inline void s5p64x0_default_sdhci1(void) { }
243static inline void s5p6440_default_sdhci2(void) { }
244static inline void s5p6450_default_sdhci2(void) { }
245
246#endif /* CONFIG_S5P64X0_SETUP_SDHCI */
247
204/* S5PC100 SDHCI setup */ 248/* S5PC100 SDHCI setup */
205 249
206#ifdef CONFIG_S5PC100_SETUP_SDHCI 250#ifdef CONFIG_S5PC100_SETUP_SDHCI
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 12:54:18 -0500