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-rw-r--r--arch/arm/Kconfig5
-rw-r--r--arch/arm/configs/at91rm9200_defconfig161
-rw-r--r--arch/arm/configs/at91sam9260_9g20_defconfig145
-rw-r--r--arch/arm/configs/at91sam9261_9g10_defconfig147
-rw-r--r--arch/arm/configs/at91sam9263_defconfig151
-rw-r--r--arch/arm/configs/at91sam9g45_defconfig175
-rw-r--r--arch/arm/configs/at91sam9rl_defconfig92
-rw-r--r--arch/arm/configs/at91x40_defconfig48
-rw-r--r--arch/arm/configs/sama5_defconfig1
-rw-r--r--arch/arm/mach-at91/Kconfig72
-rw-r--r--arch/arm/mach-at91/Kconfig.non_dt344
-rw-r--r--arch/arm/mach-at91/Makefile67
-rw-r--r--arch/arm/mach-at91/Makefile.boot6
-rw-r--r--arch/arm/mach-at91/at91_aic.h99
-rw-r--r--arch/arm/mach-at91/at91_tc.h146
-rw-r--r--arch/arm/mach-at91/at91rm9200.c341
-rw-r--r--arch/arm/mach-at91/at91rm9200_devices.c1212
-rw-r--r--arch/arm/mach-at91/at91rm9200_time.c23
-rw-r--r--arch/arm/mach-at91/at91sam9260.c397
-rw-r--r--arch/arm/mach-at91/at91sam9260_devices.c1364
-rw-r--r--arch/arm/mach-at91/at91sam9261.c375
-rw-r--r--arch/arm/mach-at91/at91sam9261_devices.c1098
-rw-r--r--arch/arm/mach-at91/at91sam9263.c399
-rw-r--r--arch/arm/mach-at91/at91sam9263_devices.c1538
-rw-r--r--arch/arm/mach-at91/at91sam9g45.c455
-rw-r--r--arch/arm/mach-at91/at91sam9g45_devices.c1915
-rw-r--r--arch/arm/mach-at91/at91sam9n12.c213
-rw-r--r--arch/arm/mach-at91/at91sam9rl.c377
-rw-r--r--arch/arm/mach-at91/at91sam9rl_devices.c1260
-rw-r--r--arch/arm/mach-at91/at91sam9x5.c311
-rw-r--r--arch/arm/mach-at91/at91x40.c93
-rw-r--r--arch/arm/mach-at91/at91x40_time.c85
-rw-r--r--arch/arm/mach-at91/board-1arm.c99
-rw-r--r--arch/arm/mach-at91/board-afeb-9260v1.c223
-rw-r--r--arch/arm/mach-at91/board-cam60.c199
-rw-r--r--arch/arm/mach-at91/board-carmeva.c167
-rw-r--r--arch/arm/mach-at91/board-cpu9krea.c386
-rw-r--r--arch/arm/mach-at91/board-cpuat91.c189
-rw-r--r--arch/arm/mach-at91/board-csb337.c260
-rw-r--r--arch/arm/mach-at91/board-csb637.c142
-rw-r--r--arch/arm/mach-at91/board-dt-rm9200.c3
-rw-r--r--arch/arm/mach-at91/board-dt-sam9.c2
-rw-r--r--arch/arm/mach-at91/board-dt-sama5.c1
-rw-r--r--arch/arm/mach-at91/board-eb01.c52
-rw-r--r--arch/arm/mach-at91/board-eb9200.c126
-rw-r--r--arch/arm/mach-at91/board-ecbat91.c191
-rw-r--r--arch/arm/mach-at91/board-eco920.c160
-rw-r--r--arch/arm/mach-at91/board-flexibity.c171
-rw-r--r--arch/arm/mach-at91/board-gsia18s.c585
-rw-r--r--arch/arm/mach-at91/board-kafa.c113
-rw-r--r--arch/arm/mach-at91/board-kb9202.c159
-rw-r--r--arch/arm/mach-at91/board-pcontrol-g20.c228
-rw-r--r--arch/arm/mach-at91/board-picotux200.c129
-rw-r--r--arch/arm/mach-at91/board-rm9200ek.c196
-rw-r--r--arch/arm/mach-at91/board-sam9-l9260.c230
-rw-r--r--arch/arm/mach-at91/board-sam9260ek.c354
-rw-r--r--arch/arm/mach-at91/board-sam9261ek.c623
-rw-r--r--arch/arm/mach-at91/board-sam9263ek.c493
-rw-r--r--arch/arm/mach-at91/board-sam9g20ek.c429
-rw-r--r--arch/arm/mach-at91/board-sam9m10g45ek.c527
-rw-r--r--arch/arm/mach-at91/board-sam9rlek.c333
-rw-r--r--arch/arm/mach-at91/board-snapper9260.c191
-rw-r--r--arch/arm/mach-at91/board-stamp9g20.c294
-rw-r--r--arch/arm/mach-at91/board-yl-9200.c597
-rw-r--r--arch/arm/mach-at91/board.h127
-rw-r--r--arch/arm/mach-at91/clock.c977
-rw-r--r--arch/arm/mach-at91/clock.h49
-rw-r--r--arch/arm/mach-at91/generic.h53
-rw-r--r--arch/arm/mach-at91/gpio.c982
-rw-r--r--arch/arm/mach-at91/gpio.h214
-rw-r--r--arch/arm/mach-at91/gsia18s.h33
-rw-r--r--arch/arm/mach-at91/include/mach/at91_dbgu.h3
-rw-r--r--arch/arm/mach-at91/include/mach/at91_ramc.h6
-rw-r--r--arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h63
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h124
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_sdramc.h85
-rw-r--r--arch/arm/mach-at91/include/mach/at91x40.h60
-rw-r--r--arch/arm/mach-at91/include/mach/cpu.h1
-rw-r--r--arch/arm/mach-at91/include/mach/hardware.h10
-rw-r--r--arch/arm/mach-at91/include/mach/uncompress.h7
-rw-r--r--arch/arm/mach-at91/irq.c296
-rw-r--r--arch/arm/mach-at91/leds.c56
-rw-r--r--arch/arm/mach-at91/pm.c33
-rw-r--r--arch/arm/mach-at91/pm.h1
-rw-r--r--arch/arm/mach-at91/setup.c67
-rw-r--r--arch/arm/mach-at91/soc.h6
-rw-r--r--arch/arm/mach-at91/stamp9g20.h7
87 files changed, 25 insertions, 24202 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 89c4b5ccc68d..92dbde801d9c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -376,10 +376,11 @@ config ARCH_AT91
376 select IRQ_DOMAIN 376 select IRQ_DOMAIN
377 select NEED_MACH_IO_H if PCCARD 377 select NEED_MACH_IO_H if PCCARD
378 select PINCTRL 378 select PINCTRL
379 select PINCTRL_AT91 if USE_OF 379 select PINCTRL_AT91
380 select USE_OF
380 help 381 help
381 This enables support for systems based on Atmel 382 This enables support for systems based on Atmel
382 AT91RM9200 and AT91SAM9* processors. 383 AT91RM9200, AT91SAM9 and SAMA5 processors.
383 384
384config ARCH_CLPS711X 385config ARCH_CLPS711X
385 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" 386 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
diff --git a/arch/arm/configs/at91rm9200_defconfig b/arch/arm/configs/at91rm9200_defconfig
deleted file mode 100644
index bf057719dab0..000000000000
--- a/arch/arm/configs/at91rm9200_defconfig
+++ /dev/null
@@ -1,161 +0,0 @@
1# CONFIG_LOCALVERSION_AUTO is not set
2# CONFIG_SWAP is not set
3CONFIG_SYSVIPC=y
4CONFIG_NO_HZ=y
5CONFIG_HIGH_RES_TIMERS=y
6CONFIG_IKCONFIG=y
7CONFIG_IKCONFIG_PROC=y
8CONFIG_LOG_BUF_SHIFT=14
9CONFIG_USER_NS=y
10CONFIG_BLK_DEV_INITRD=y
11CONFIG_MODULES=y
12CONFIG_MODULE_FORCE_LOAD=y
13CONFIG_MODULE_UNLOAD=y
14CONFIG_MODVERSIONS=y
15CONFIG_MODULE_SRCVERSION_ALL=y
16# CONFIG_BLK_DEV_BSG is not set
17# CONFIG_IOSCHED_CFQ is not set
18CONFIG_ARCH_AT91=y
19CONFIG_ARCH_AT91RM9200=y
20CONFIG_MACH_ONEARM=y
21CONFIG_MACH_AT91RM9200EK=y
22CONFIG_MACH_CSB337=y
23CONFIG_MACH_CSB637=y
24CONFIG_MACH_CARMEVA=y
25CONFIG_MACH_ATEB9200=y
26CONFIG_MACH_KB9200=y
27CONFIG_MACH_PICOTUX2XX=y
28CONFIG_MACH_KAFA=y
29CONFIG_MACH_ECBAT91=y
30CONFIG_MACH_YL9200=y
31CONFIG_MACH_CPUAT91=y
32CONFIG_MACH_ECO920=y
33CONFIG_MTD_AT91_DATAFLASH_CARD=y
34CONFIG_AT91_TIMER_HZ=100
35# CONFIG_ARM_THUMB is not set
36CONFIG_PCCARD=y
37CONFIG_AT91_CF=y
38CONFIG_AEABI=y
39# CONFIG_COMPACTION is not set
40CONFIG_ZBOOT_ROM_TEXT=0x10000000
41CONFIG_ZBOOT_ROM_BSS=0x20040000
42CONFIG_KEXEC=y
43CONFIG_AUTO_ZRELADDR=y
44CONFIG_FPE_NWFPE=y
45CONFIG_BINFMT_MISC=y
46CONFIG_NET=y
47CONFIG_PACKET=y
48CONFIG_UNIX=y
49CONFIG_INET=y
50CONFIG_IP_MULTICAST=y
51CONFIG_IP_PNP=y
52CONFIG_IP_PNP_DHCP=y
53CONFIG_IP_PNP_BOOTP=y
54# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
55# CONFIG_INET_XFRM_MODE_TUNNEL is not set
56# CONFIG_INET_XFRM_MODE_BEET is not set
57# CONFIG_INET_DIAG is not set
58CONFIG_IPV6=y
59CONFIG_IPV6_PRIVACY=y
60CONFIG_IPV6_ROUTER_PREF=y
61CONFIG_IPV6_ROUTE_INFO=y
62CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
63CONFIG_DEVTMPFS=y
64CONFIG_DEVTMPFS_MOUNT=y
65# CONFIG_STANDALONE is not set
66# CONFIG_PREVENT_FIRMWARE_BUILD is not set
67CONFIG_MTD=y
68CONFIG_MTD_CMDLINE_PARTS=y
69CONFIG_MTD_CHAR=y
70CONFIG_MTD_BLOCK=y
71CONFIG_MTD_CFI=y
72CONFIG_MTD_JEDECPROBE=y
73CONFIG_MTD_CFI_INTELEXT=y
74CONFIG_MTD_CFI_AMDSTD=y
75CONFIG_MTD_COMPLEX_MAPPINGS=y
76CONFIG_MTD_PHYSMAP=y
77CONFIG_MTD_PLATRAM=y
78CONFIG_MTD_DATAFLASH=y
79CONFIG_MTD_NAND=y
80CONFIG_MTD_NAND_ATMEL=y
81CONFIG_MTD_NAND_PLATFORM=y
82CONFIG_MTD_UBI=y
83CONFIG_MTD_UBI_GLUEBI=y
84CONFIG_BLK_DEV_LOOP=y
85CONFIG_BLK_DEV_RAM=y
86CONFIG_BLK_DEV_RAM_SIZE=8192
87CONFIG_NETDEVICES=y
88CONFIG_MII=y
89CONFIG_ARM_AT91_ETHER=y
90CONFIG_DAVICOM_PHY=y
91CONFIG_SMSC_PHY=y
92CONFIG_MICREL_PHY=y
93# CONFIG_WLAN is not set
94# CONFIG_INPUT_MOUSEDEV is not set
95CONFIG_INPUT_EVDEV=y
96CONFIG_KEYBOARD_GPIO=y
97# CONFIG_INPUT_MOUSE is not set
98CONFIG_INPUT_TOUCHSCREEN=y
99# CONFIG_LEGACY_PTYS is not set
100CONFIG_SERIAL_ATMEL=y
101CONFIG_SERIAL_ATMEL_CONSOLE=y
102CONFIG_HW_RANDOM=y
103CONFIG_I2C=y
104CONFIG_I2C_CHARDEV=y
105CONFIG_I2C_GPIO=y
106CONFIG_SPI=y
107CONFIG_SPI_ATMEL=y
108CONFIG_GPIO_SYSFS=y
109# CONFIG_HWMON is not set
110CONFIG_WATCHDOG=y
111CONFIG_WATCHDOG_NOWAYOUT=y
112CONFIG_AT91RM9200_WATCHDOG=y
113CONFIG_FB=y
114CONFIG_FB_MODE_HELPERS=y
115CONFIG_FB_TILEBLITTING=y
116CONFIG_FB_S1D13XXX=y
117CONFIG_BACKLIGHT_LCD_SUPPORT=y
118CONFIG_LCD_CLASS_DEVICE=y
119CONFIG_BACKLIGHT_CLASS_DEVICE=y
120# CONFIG_BACKLIGHT_GENERIC is not set
121CONFIG_FRAMEBUFFER_CONSOLE=y
122CONFIG_FONTS=y
123CONFIG_LOGO=y
124CONFIG_USB=y
125CONFIG_USB_OHCI_HCD=y
126CONFIG_USB_GADGET=y
127CONFIG_USB_AT91=y
128CONFIG_USB_G_SERIAL=y
129CONFIG_MMC=y
130CONFIG_MMC_ATMELMCI=y
131CONFIG_NEW_LEDS=y
132CONFIG_LEDS_CLASS=y
133CONFIG_LEDS_GPIO=y
134CONFIG_LEDS_TRIGGERS=y
135CONFIG_LEDS_TRIGGER_TIMER=y
136CONFIG_LEDS_TRIGGER_HEARTBEAT=y
137CONFIG_LEDS_TRIGGER_GPIO=y
138CONFIG_RTC_CLASS=y
139CONFIG_RTC_DRV_AT91RM9200=y
140CONFIG_EXT4_FS=y
141CONFIG_AUTOFS4_FS=y
142CONFIG_VFAT_FS=y
143CONFIG_TMPFS=y
144CONFIG_UBIFS_FS=y
145CONFIG_UBIFS_FS_ADVANCED_COMPR=y
146CONFIG_NFS_FS=y
147CONFIG_ROOT_NFS=y
148CONFIG_NLS_CODEPAGE_437=y
149CONFIG_NLS_CODEPAGE_850=y
150CONFIG_NLS_ISO8859_1=y
151CONFIG_NLS_UTF8=y
152CONFIG_MAGIC_SYSRQ=y
153CONFIG_DEBUG_FS=y
154CONFIG_DEBUG_KERNEL=y
155# CONFIG_FTRACE is not set
156CONFIG_DEBUG_USER=y
157CONFIG_DEBUG_LL=y
158CONFIG_EARLY_PRINTK=y
159CONFIG_CRYPTO_PCBC=y
160CONFIG_CRYPTO_SHA1=y
161CONFIG_XZ_DEC_ARMTHUMB=y
diff --git a/arch/arm/configs/at91sam9260_9g20_defconfig b/arch/arm/configs/at91sam9260_9g20_defconfig
deleted file mode 100644
index 3ada05d639ad..000000000000
--- a/arch/arm/configs/at91sam9260_9g20_defconfig
+++ /dev/null
@@ -1,145 +0,0 @@
1# CONFIG_LOCALVERSION_AUTO is not set
2# CONFIG_SWAP is not set
3CONFIG_SYSVIPC=y
4CONFIG_LOG_BUF_SHIFT=14
5CONFIG_BLK_DEV_INITRD=y
6CONFIG_EMBEDDED=y
7CONFIG_SLAB=y
8CONFIG_MODULES=y
9CONFIG_MODULE_UNLOAD=y
10# CONFIG_BLK_DEV_BSG is not set
11# CONFIG_IOSCHED_DEADLINE is not set
12# CONFIG_IOSCHED_CFQ is not set
13CONFIG_ARCH_AT91=y
14CONFIG_ARCH_AT91SAM9260=y
15CONFIG_MACH_AT91SAM9260EK=y
16CONFIG_MACH_CAM60=y
17CONFIG_MACH_SAM9_L9260=y
18CONFIG_MACH_AFEB9260=y
19CONFIG_MACH_CPU9260=y
20CONFIG_MACH_FLEXIBITY=y
21CONFIG_MACH_AT91SAM9G20EK=y
22CONFIG_MACH_AT91SAM9G20EK_2MMC=y
23CONFIG_MACH_CPU9G20=y
24CONFIG_MACH_ACMENETUSFOXG20=y
25CONFIG_MACH_PORTUXG20=y
26CONFIG_MACH_STAMP9G20=y
27CONFIG_MACH_PCONTROL_G20=y
28CONFIG_MACH_GSIA18S=y
29CONFIG_MACH_SNAPPER_9260=y
30CONFIG_MACH_AT91SAM9_DT=y
31CONFIG_AT91_SLOW_CLOCK=y
32# CONFIG_ARM_THUMB is not set
33CONFIG_AEABI=y
34CONFIG_ZBOOT_ROM_TEXT=0x0
35CONFIG_ZBOOT_ROM_BSS=0x0
36CONFIG_ARM_APPENDED_DTB=y
37CONFIG_ARM_ATAG_DTB_COMPAT=y
38CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
39CONFIG_AUTO_ZRELADDR=y
40CONFIG_NET=y
41CONFIG_PACKET=y
42CONFIG_UNIX=y
43CONFIG_INET=y
44CONFIG_IP_PNP=y
45CONFIG_IP_PNP_DHCP=y
46CONFIG_IP_PNP_BOOTP=y
47# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
48# CONFIG_INET_XFRM_MODE_TUNNEL is not set
49# CONFIG_INET_XFRM_MODE_BEET is not set
50# CONFIG_INET_LRO is not set
51# CONFIG_IPV6 is not set
52CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
53CONFIG_DEVTMPFS=y
54CONFIG_DEVTMPFS_MOUNT=y
55CONFIG_MTD=y
56CONFIG_MTD_CMDLINE_PARTS=y
57CONFIG_MTD_BLOCK=y
58CONFIG_MTD_DATAFLASH=y
59CONFIG_MTD_NAND=y
60CONFIG_MTD_NAND_ATMEL=y
61CONFIG_MTD_UBI=y
62CONFIG_BLK_DEV_LOOP=y
63CONFIG_BLK_DEV_RAM=y
64CONFIG_BLK_DEV_RAM_SIZE=8192
65CONFIG_EEPROM_AT25=y
66CONFIG_SCSI=y
67CONFIG_BLK_DEV_SD=y
68# CONFIG_SCSI_LOWLEVEL is not set
69CONFIG_NETDEVICES=y
70CONFIG_MACB=y
71# CONFIG_NET_VENDOR_BROADCOM is not set
72# CONFIG_NET_VENDOR_FARADAY is not set
73# CONFIG_NET_VENDOR_INTEL is not set
74# CONFIG_NET_VENDOR_MARVELL is not set
75# CONFIG_NET_VENDOR_MICREL is not set
76# CONFIG_NET_VENDOR_MICROCHIP is not set
77# CONFIG_NET_VENDOR_NATSEMI is not set
78# CONFIG_NET_VENDOR_SEEQ is not set
79# CONFIG_NET_VENDOR_SMSC is not set
80# CONFIG_NET_VENDOR_STMICRO is not set
81CONFIG_SMSC_PHY=y
82# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
83CONFIG_KEYBOARD_GPIO=y
84# CONFIG_INPUT_MOUSE is not set
85CONFIG_SERIAL_ATMEL=y
86CONFIG_SERIAL_ATMEL_CONSOLE=y
87CONFIG_HW_RANDOM=y
88CONFIG_I2C=y
89CONFIG_I2C_CHARDEV=y
90CONFIG_I2C_GPIO=y
91CONFIG_SPI=y
92CONFIG_SPI_ATMEL=y
93CONFIG_SPI_SPIDEV=y
94CONFIG_GPIO_SYSFS=y
95CONFIG_POWER_SUPPLY=y
96CONFIG_POWER_RESET=y
97# CONFIG_HWMON is not set
98CONFIG_WATCHDOG=y
99CONFIG_WATCHDOG_NOWAYOUT=y
100CONFIG_AT91SAM9X_WATCHDOG=y
101CONFIG_SOUND=y
102CONFIG_SND=y
103CONFIG_SND_SEQUENCER=y
104CONFIG_SND_MIXER_OSS=y
105CONFIG_SND_PCM_OSS=y
106CONFIG_SND_SEQUENCER_OSS=y
107# CONFIG_SND_VERBOSE_PROCFS is not set
108CONFIG_USB=y
109CONFIG_USB_MON=y
110CONFIG_USB_OHCI_HCD=y
111CONFIG_USB_STORAGE=y
112CONFIG_USB_GADGET=y
113CONFIG_USB_AT91=y
114CONFIG_USB_G_SERIAL=y
115CONFIG_MMC=y
116CONFIG_MMC_ATMELMCI=y
117CONFIG_MMC_SPI=y
118CONFIG_NEW_LEDS=y
119CONFIG_LEDS_CLASS=y
120CONFIG_LEDS_GPIO=y
121CONFIG_LEDS_TRIGGERS=y
122CONFIG_LEDS_TRIGGER_TIMER=y
123CONFIG_LEDS_TRIGGER_HEARTBEAT=y
124CONFIG_RTC_CLASS=y
125CONFIG_RTC_DRV_RV3029C2=y
126CONFIG_RTC_DRV_AT91SAM9=y
127CONFIG_IIO=y
128CONFIG_AT91_ADC=y
129CONFIG_EXT4_FS=y
130CONFIG_VFAT_FS=y
131CONFIG_TMPFS=y
132CONFIG_UBIFS_FS=y
133CONFIG_UBIFS_FS_ADVANCED_COMPR=y
134CONFIG_NFS_FS=y
135CONFIG_ROOT_NFS=y
136CONFIG_NLS_CODEPAGE_437=y
137CONFIG_NLS_CODEPAGE_850=y
138CONFIG_NLS_ISO8859_1=y
139CONFIG_NLS_ISO8859_15=y
140CONFIG_NLS_UTF8=y
141CONFIG_DEBUG_INFO=y
142# CONFIG_ENABLE_WARN_DEPRECATED is not set
143# CONFIG_FTRACE is not set
144CONFIG_DEBUG_LL=y
145CONFIG_EARLY_PRINTK=y
diff --git a/arch/arm/configs/at91sam9261_9g10_defconfig b/arch/arm/configs/at91sam9261_9g10_defconfig
deleted file mode 100644
index 0c505d801e25..000000000000
--- a/arch/arm/configs/at91sam9261_9g10_defconfig
+++ /dev/null
@@ -1,147 +0,0 @@
1# CONFIG_LOCALVERSION_AUTO is not set
2CONFIG_KERNEL_LZMA=y
3# CONFIG_SWAP is not set
4CONFIG_SYSVIPC=y
5CONFIG_IKCONFIG=y
6CONFIG_IKCONFIG_PROC=y
7CONFIG_LOG_BUF_SHIFT=14
8CONFIG_NAMESPACES=y
9CONFIG_EMBEDDED=y
10CONFIG_SLAB=y
11CONFIG_MODULES=y
12CONFIG_MODULE_UNLOAD=y
13# CONFIG_BLK_DEV_BSG is not set
14# CONFIG_IOSCHED_DEADLINE is not set
15# CONFIG_IOSCHED_CFQ is not set
16CONFIG_ARCH_AT91=y
17CONFIG_ARCH_AT91SAM9261=y
18CONFIG_MACH_AT91SAM9261EK=y
19CONFIG_MACH_AT91SAM9G10EK=y
20# CONFIG_ARM_THUMB is not set
21CONFIG_AEABI=y
22CONFIG_ZBOOT_ROM_TEXT=0x0
23CONFIG_ZBOOT_ROM_BSS=0x0
24CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
25CONFIG_AUTO_ZRELADDR=y
26CONFIG_VFP=y
27# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
28CONFIG_NET=y
29CONFIG_PACKET=y
30CONFIG_UNIX=y
31CONFIG_INET=y
32CONFIG_IP_MULTICAST=y
33CONFIG_IP_PNP=y
34CONFIG_IP_PNP_DHCP=y
35CONFIG_IP_PNP_BOOTP=y
36# CONFIG_INET_LRO is not set
37# CONFIG_IPV6 is not set
38CONFIG_CFG80211=y
39CONFIG_MAC80211=y
40CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
41CONFIG_DEVTMPFS=y
42CONFIG_DEVTMPFS_MOUNT=y
43CONFIG_MTD=y
44CONFIG_MTD_CMDLINE_PARTS=y
45CONFIG_MTD_BLOCK=y
46CONFIG_MTD_NAND=y
47CONFIG_MTD_NAND_ATMEL=y
48CONFIG_MTD_UBI=y
49CONFIG_MTD_UBI_GLUEBI=y
50CONFIG_BLK_DEV_RAM=y
51CONFIG_BLK_DEV_RAM_SIZE=8192
52CONFIG_ATMEL_TCLIB=y
53CONFIG_ATMEL_SSC=y
54CONFIG_SCSI=y
55CONFIG_BLK_DEV_SD=y
56CONFIG_NETDEVICES=y
57CONFIG_DM9000=y
58CONFIG_USB_ZD1201=m
59CONFIG_RTL8187=m
60CONFIG_LIBERTAS=m
61CONFIG_LIBERTAS_USB=m
62CONFIG_LIBERTAS_SDIO=m
63CONFIG_LIBERTAS_SPI=m
64CONFIG_RT2X00=m
65CONFIG_RT2500USB=m
66CONFIG_RT73USB=m
67CONFIG_ZD1211RW=m
68CONFIG_INPUT_POLLDEV=m
69# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
70CONFIG_INPUT_MOUSEDEV_SCREEN_X=240
71CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
72CONFIG_INPUT_EVDEV=y
73# CONFIG_KEYBOARD_ATKBD is not set
74CONFIG_KEYBOARD_GPIO=y
75# CONFIG_INPUT_MOUSE is not set
76CONFIG_INPUT_TOUCHSCREEN=y
77CONFIG_TOUCHSCREEN_ADS7846=y
78CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
79CONFIG_SERIAL_ATMEL=y
80CONFIG_SERIAL_ATMEL_CONSOLE=y
81CONFIG_HW_RANDOM=y
82CONFIG_I2C=y
83CONFIG_I2C_CHARDEV=y
84CONFIG_I2C_GPIO=y
85CONFIG_SPI=y
86CONFIG_SPI_ATMEL=y
87CONFIG_POWER_SUPPLY=y
88CONFIG_POWER_RESET=y
89# CONFIG_HWMON is not set
90CONFIG_WATCHDOG=y
91CONFIG_WATCHDOG_NOWAYOUT=y
92CONFIG_AT91SAM9X_WATCHDOG=y
93CONFIG_FB=y
94CONFIG_FB_ATMEL=y
95CONFIG_BACKLIGHT_LCD_SUPPORT=y
96# CONFIG_LCD_CLASS_DEVICE is not set
97CONFIG_BACKLIGHT_CLASS_DEVICE=y
98CONFIG_BACKLIGHT_ATMEL_LCDC=y
99# CONFIG_BACKLIGHT_GENERIC is not set
100CONFIG_FRAMEBUFFER_CONSOLE=y
101CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
102CONFIG_LOGO=y
103CONFIG_SOUND=y
104CONFIG_SND=y
105CONFIG_SND_SEQUENCER=y
106CONFIG_SND_MIXER_OSS=y
107CONFIG_SND_PCM_OSS=y
108# CONFIG_SND_SUPPORT_OLD_API is not set
109# CONFIG_SND_VERBOSE_PROCFS is not set
110# CONFIG_SND_DRIVERS is not set
111# CONFIG_SND_ARM is not set
112CONFIG_SND_AT73C213=y
113CONFIG_SND_USB_AUDIO=m
114# CONFIG_USB_HID is not set
115CONFIG_USB=y
116CONFIG_USB_OHCI_HCD=y
117CONFIG_USB_STORAGE=y
118CONFIG_USB_GADGET=y
119CONFIG_USB_AT91=y
120CONFIG_USB_G_SERIAL=y
121CONFIG_MMC=y
122CONFIG_MMC_ATMELMCI=m
123CONFIG_NEW_LEDS=y
124CONFIG_LEDS_CLASS=y
125CONFIG_LEDS_GPIO=y
126CONFIG_LEDS_TRIGGERS=y
127CONFIG_LEDS_TRIGGER_TIMER=y
128CONFIG_LEDS_TRIGGER_HEARTBEAT=y
129CONFIG_LEDS_TRIGGER_GPIO=y
130CONFIG_RTC_CLASS=y
131CONFIG_RTC_DRV_AT91SAM9=y
132CONFIG_MSDOS_FS=y
133CONFIG_VFAT_FS=y
134CONFIG_TMPFS=y
135CONFIG_UBIFS_FS=y
136CONFIG_UBIFS_FS_ADVANCED_COMPR=y
137CONFIG_SQUASHFS=y
138CONFIG_SQUASHFS_LZO=y
139CONFIG_SQUASHFS_XZ=y
140CONFIG_NFS_FS=y
141CONFIG_ROOT_NFS=y
142CONFIG_NLS_CODEPAGE_437=y
143CONFIG_NLS_CODEPAGE_850=y
144CONFIG_NLS_ISO8859_1=y
145CONFIG_NLS_ISO8859_15=y
146CONFIG_NLS_UTF8=y
147CONFIG_CRC_CCITT=m
diff --git a/arch/arm/configs/at91sam9263_defconfig b/arch/arm/configs/at91sam9263_defconfig
deleted file mode 100644
index 8b671c977b81..000000000000
--- a/arch/arm/configs/at91sam9263_defconfig
+++ /dev/null
@@ -1,151 +0,0 @@
1# CONFIG_LOCALVERSION_AUTO is not set
2# CONFIG_SWAP is not set
3CONFIG_SYSVIPC=y
4CONFIG_IKCONFIG=y
5CONFIG_IKCONFIG_PROC=y
6CONFIG_LOG_BUF_SHIFT=14
7CONFIG_NAMESPACES=y
8CONFIG_EMBEDDED=y
9CONFIG_SLAB=y
10CONFIG_MODULES=y
11CONFIG_MODULE_UNLOAD=y
12# CONFIG_BLK_DEV_BSG is not set
13# CONFIG_IOSCHED_DEADLINE is not set
14# CONFIG_IOSCHED_CFQ is not set
15CONFIG_ARCH_AT91=y
16CONFIG_ARCH_AT91SAM9263=y
17CONFIG_MACH_AT91SAM9263EK=y
18CONFIG_MTD_AT91_DATAFLASH_CARD=y
19# CONFIG_ARM_THUMB is not set
20CONFIG_AEABI=y
21CONFIG_ZBOOT_ROM_TEXT=0x0
22CONFIG_ZBOOT_ROM_BSS=0x0
23CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
24CONFIG_AUTO_ZRELADDR=y
25CONFIG_NET=y
26CONFIG_PACKET=y
27CONFIG_UNIX=y
28CONFIG_NET_KEY=y
29CONFIG_INET=y
30CONFIG_IP_MULTICAST=y
31CONFIG_IP_ADVANCED_ROUTER=y
32CONFIG_IP_ROUTE_VERBOSE=y
33CONFIG_IP_PNP=y
34CONFIG_IP_PNP_DHCP=y
35CONFIG_IP_PNP_BOOTP=y
36CONFIG_IP_PNP_RARP=y
37CONFIG_NET_IPIP=y
38CONFIG_IP_MROUTE=y
39CONFIG_IP_PIMSM_V1=y
40CONFIG_IP_PIMSM_V2=y
41# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
42# CONFIG_INET_XFRM_MODE_TUNNEL is not set
43# CONFIG_INET_XFRM_MODE_BEET is not set
44# CONFIG_INET_LRO is not set
45# CONFIG_INET_DIAG is not set
46CONFIG_IPV6=y
47# CONFIG_WIRELESS is not set
48CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
49CONFIG_DEVTMPFS=y
50CONFIG_DEVTMPFS_MOUNT=y
51CONFIG_MTD=y
52CONFIG_MTD_CMDLINE_PARTS=y
53CONFIG_MTD_BLOCK=y
54CONFIG_NFTL=y
55CONFIG_NFTL_RW=y
56CONFIG_MTD_DATAFLASH=y
57CONFIG_MTD_BLOCK2MTD=y
58CONFIG_MTD_NAND=y
59CONFIG_MTD_NAND_ATMEL=y
60CONFIG_MTD_UBI=y
61CONFIG_MTD_UBI_GLUEBI=y
62CONFIG_BLK_DEV_LOOP=y
63CONFIG_BLK_DEV_RAM=y
64CONFIG_BLK_DEV_RAM_SIZE=8192
65CONFIG_ATMEL_TCLIB=y
66CONFIG_SCSI=y
67CONFIG_BLK_DEV_SD=y
68CONFIG_NETDEVICES=y
69CONFIG_MACB=y
70CONFIG_SMSC_PHY=y
71# CONFIG_WLAN is not set
72CONFIG_INPUT_POLLDEV=m
73# CONFIG_INPUT_MOUSEDEV is not set
74CONFIG_INPUT_EVDEV=y
75# CONFIG_KEYBOARD_ATKBD is not set
76CONFIG_KEYBOARD_GPIO=y
77# CONFIG_INPUT_MOUSE is not set
78CONFIG_INPUT_TOUCHSCREEN=y
79CONFIG_TOUCHSCREEN_ADS7846=y
80# CONFIG_LEGACY_PTYS is not set
81CONFIG_SERIAL_ATMEL=y
82CONFIG_SERIAL_ATMEL_CONSOLE=y
83CONFIG_HW_RANDOM=y
84CONFIG_I2C=y
85CONFIG_I2C_CHARDEV=y
86CONFIG_I2C_GPIO=y
87CONFIG_SPI=y
88CONFIG_SPI_ATMEL=y
89CONFIG_GPIO_SYSFS=y
90CONFIG_POWER_SUPPLY=y
91CONFIG_POWER_RESET=y
92# CONFIG_HWMON is not set
93CONFIG_WATCHDOG=y
94CONFIG_WATCHDOG_NOWAYOUT=y
95CONFIG_AT91SAM9X_WATCHDOG=y
96CONFIG_FB=y
97CONFIG_FB_ATMEL=y
98CONFIG_BACKLIGHT_LCD_SUPPORT=y
99CONFIG_LCD_CLASS_DEVICE=y
100CONFIG_BACKLIGHT_CLASS_DEVICE=y
101CONFIG_FRAMEBUFFER_CONSOLE=y
102CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
103CONFIG_LOGO=y
104CONFIG_SOUND=y
105CONFIG_SND=y
106CONFIG_SND_SEQUENCER=y
107CONFIG_SND_MIXER_OSS=y
108CONFIG_SND_PCM_OSS=y
109# CONFIG_SND_SUPPORT_OLD_API is not set
110# CONFIG_SND_VERBOSE_PROCFS is not set
111# CONFIG_SND_DRIVERS is not set
112# CONFIG_SND_ARM is not set
113CONFIG_SND_ATMEL_AC97C=y
114# CONFIG_SND_SPI is not set
115CONFIG_SND_USB_AUDIO=m
116CONFIG_USB=y
117CONFIG_USB_MON=y
118CONFIG_USB_OHCI_HCD=y
119CONFIG_USB_STORAGE=y
120CONFIG_USB_GADGET=y
121CONFIG_USB_ATMEL_USBA=y
122CONFIG_USB_G_SERIAL=y
123CONFIG_MMC=y
124CONFIG_SDIO_UART=m
125CONFIG_MMC_ATMELMCI=m
126CONFIG_NEW_LEDS=y
127CONFIG_LEDS_CLASS=y
128CONFIG_LEDS_GPIO=y
129CONFIG_LEDS_PWM=y
130CONFIG_LEDS_TRIGGERS=y
131CONFIG_LEDS_TRIGGER_HEARTBEAT=y
132CONFIG_RTC_CLASS=y
133CONFIG_RTC_DRV_AT91SAM9=y
134CONFIG_PWM=y
135CONFIG_PWM_ATMEL=y
136CONFIG_EXT4_FS=y
137CONFIG_VFAT_FS=y
138CONFIG_TMPFS=y
139CONFIG_UBIFS_FS=y
140CONFIG_UBIFS_FS_ADVANCED_COMPR=y
141CONFIG_NFS_FS=y
142CONFIG_NFS_V3_ACL=y
143CONFIG_NFS_V4=y
144CONFIG_ROOT_NFS=y
145CONFIG_NLS_CODEPAGE_437=y
146CONFIG_NLS_CODEPAGE_850=y
147CONFIG_NLS_ISO8859_1=y
148CONFIG_NLS_UTF8=y
149CONFIG_DEBUG_USER=y
150CONFIG_XZ_DEC=y
151CONFIG_FONTS=y
diff --git a/arch/arm/configs/at91sam9g45_defconfig b/arch/arm/configs/at91sam9g45_defconfig
deleted file mode 100644
index f66d1a1b64bf..000000000000
--- a/arch/arm/configs/at91sam9g45_defconfig
+++ /dev/null
@@ -1,175 +0,0 @@
1# CONFIG_LOCALVERSION_AUTO is not set
2# CONFIG_SWAP is not set
3CONFIG_SYSVIPC=y
4CONFIG_LOG_BUF_SHIFT=14
5CONFIG_SYSFS_DEPRECATED=y
6CONFIG_SYSFS_DEPRECATED_V2=y
7CONFIG_BLK_DEV_INITRD=y
8CONFIG_CC_OPTIMIZE_FOR_SIZE=y
9CONFIG_EMBEDDED=y
10CONFIG_SLAB=y
11CONFIG_MODULES=y
12CONFIG_MODULE_UNLOAD=y
13# CONFIG_LBDAF is not set
14# CONFIG_BLK_DEV_BSG is not set
15# CONFIG_IOSCHED_DEADLINE is not set
16# CONFIG_IOSCHED_CFQ is not set
17CONFIG_ARCH_AT91=y
18CONFIG_ARCH_AT91SAM9G45=y
19CONFIG_MACH_AT91SAM9M10G45EK=y
20CONFIG_MACH_AT91SAM9_DT=y
21CONFIG_AT91_SLOW_CLOCK=y
22CONFIG_AEABI=y
23CONFIG_UACCESS_WITH_MEMCPY=y
24CONFIG_ZBOOT_ROM_TEXT=0x0
25CONFIG_ZBOOT_ROM_BSS=0x0
26CONFIG_CMDLINE="mem=128M console=ttyS0,115200 initrd=0x71100000,25165824 root=/dev/ram0 rw"
27CONFIG_AUTO_ZRELADDR=y
28# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
29CONFIG_NET=y
30CONFIG_PACKET=y
31CONFIG_UNIX=y
32CONFIG_INET=y
33CONFIG_IP_MULTICAST=y
34CONFIG_IP_PNP=y
35CONFIG_IP_PNP_DHCP=y
36CONFIG_IP_PNP_BOOTP=y
37# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
38# CONFIG_INET_XFRM_MODE_TUNNEL is not set
39# CONFIG_INET_XFRM_MODE_BEET is not set
40# CONFIG_INET_DIAG is not set
41CONFIG_IPV6=y
42# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
43# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
44# CONFIG_INET6_XFRM_MODE_BEET is not set
45CONFIG_IPV6_SIT_6RD=y
46CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
47CONFIG_DEVTMPFS=y
48CONFIG_DEVTMPFS_MOUNT=y
49# CONFIG_STANDALONE is not set
50# CONFIG_PREVENT_FIRMWARE_BUILD is not set
51CONFIG_MTD=y
52CONFIG_MTD_CMDLINE_PARTS=y
53CONFIG_MTD_BLOCK=y
54CONFIG_MTD_DATAFLASH=y
55CONFIG_MTD_NAND=y
56CONFIG_MTD_NAND_ATMEL=y
57CONFIG_MTD_UBI=y
58CONFIG_MTD_UBI_GLUEBI=y
59CONFIG_BLK_DEV_LOOP=y
60CONFIG_BLK_DEV_RAM=y
61CONFIG_BLK_DEV_RAM_COUNT=4
62CONFIG_BLK_DEV_RAM_SIZE=8192
63CONFIG_ATMEL_TCLIB=y
64CONFIG_ATMEL_SSC=y
65CONFIG_SCSI=y
66CONFIG_BLK_DEV_SD=y
67# CONFIG_SCSI_LOWLEVEL is not set
68CONFIG_NETDEVICES=y
69CONFIG_MACB=y
70CONFIG_DAVICOM_PHY=y
71# CONFIG_INPUT_MOUSEDEV is not set
72CONFIG_INPUT_JOYDEV=y
73CONFIG_INPUT_EVDEV=y
74# CONFIG_KEYBOARD_ATKBD is not set
75CONFIG_KEYBOARD_QT1070=y
76CONFIG_KEYBOARD_QT2160=y
77CONFIG_KEYBOARD_GPIO=y
78# CONFIG_INPUT_MOUSE is not set
79CONFIG_INPUT_TOUCHSCREEN=y
80CONFIG_TOUCHSCREEN_ATMEL_MXT=m
81# CONFIG_SERIO is not set
82# CONFIG_LEGACY_PTYS is not set
83CONFIG_SERIAL_ATMEL=y
84CONFIG_SERIAL_ATMEL_CONSOLE=y
85CONFIG_HW_RANDOM=y
86CONFIG_I2C=y
87CONFIG_I2C_CHARDEV=y
88CONFIG_I2C_GPIO=y
89CONFIG_SPI=y
90CONFIG_SPI_ATMEL=y
91CONFIG_POWER_SUPPLY=y
92CONFIG_POWER_RESET=y
93# CONFIG_HWMON is not set
94CONFIG_WATCHDOG=y
95CONFIG_WATCHDOG_NOWAYOUT=y
96CONFIG_AT91SAM9X_WATCHDOG=y
97CONFIG_FB=y
98CONFIG_FB_ATMEL=y
99CONFIG_BACKLIGHT_LCD_SUPPORT=y
100CONFIG_LCD_CLASS_DEVICE=y
101CONFIG_BACKLIGHT_CLASS_DEVICE=y
102CONFIG_BACKLIGHT_ATMEL_LCDC=y
103# CONFIG_BACKLIGHT_GENERIC is not set
104CONFIG_BACKLIGHT_PWM=y
105CONFIG_FRAMEBUFFER_CONSOLE=y
106CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
107CONFIG_LOGO=y
108CONFIG_SOUND=y
109CONFIG_SND=y
110CONFIG_SND_SEQUENCER=y
111CONFIG_SND_MIXER_OSS=y
112CONFIG_SND_PCM_OSS=y
113# CONFIG_SND_SUPPORT_OLD_API is not set
114# CONFIG_SND_VERBOSE_PROCFS is not set
115# CONFIG_SND_DRIVERS is not set
116# CONFIG_SND_ARM is not set
117CONFIG_SND_ATMEL_AC97C=y
118# CONFIG_SND_SPI is not set
119# CONFIG_SND_USB is not set
120# CONFIG_USB_HID is not set
121CONFIG_USB=y
122CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
123CONFIG_USB_EHCI_HCD=y
124CONFIG_USB_OHCI_HCD=y
125CONFIG_USB_ACM=y
126CONFIG_USB_STORAGE=y
127CONFIG_USB_GADGET=y
128CONFIG_USB_ATMEL_USBA=y
129CONFIG_USB_G_MULTI=y
130CONFIG_USB_G_MULTI_CDC=y
131CONFIG_MMC=y
132# CONFIG_MMC_BLOCK_BOUNCE is not set
133CONFIG_MMC_ATMELMCI=y
134CONFIG_NEW_LEDS=y
135CONFIG_LEDS_CLASS=y
136CONFIG_LEDS_GPIO=y
137CONFIG_LEDS_PWM=y
138CONFIG_LEDS_TRIGGERS=y
139CONFIG_LEDS_TRIGGER_TIMER=y
140CONFIG_LEDS_TRIGGER_HEARTBEAT=y
141CONFIG_LEDS_TRIGGER_GPIO=y
142CONFIG_RTC_CLASS=y
143CONFIG_RTC_DRV_AT91RM9200=y
144CONFIG_DMADEVICES=y
145CONFIG_AT_HDMAC=y
146CONFIG_DMATEST=m
147# CONFIG_IOMMU_SUPPORT is not set
148CONFIG_IIO=y
149CONFIG_AT91_ADC=y
150CONFIG_PWM=y
151CONFIG_PWM_ATMEL=y
152CONFIG_EXT4_FS=y
153CONFIG_FANOTIFY=y
154CONFIG_VFAT_FS=y
155CONFIG_TMPFS=y
156CONFIG_UBIFS_FS=y
157CONFIG_UBIFS_FS_ADVANCED_COMPR=y
158CONFIG_NFS_FS=y
159CONFIG_ROOT_NFS=y
160CONFIG_NLS_CODEPAGE_437=y
161CONFIG_NLS_CODEPAGE_850=y
162CONFIG_NLS_ISO8859_1=y
163CONFIG_STRIP_ASM_SYMS=y
164CONFIG_DEBUG_MEMORY_INIT=y
165# CONFIG_SCHED_DEBUG is not set
166# CONFIG_FTRACE is not set
167CONFIG_DEBUG_USER=y
168CONFIG_DEBUG_LL=y
169CONFIG_EARLY_PRINTK=y
170CONFIG_CRYPTO_ECB=y
171# CONFIG_CRYPTO_ANSI_CPRNG is not set
172CONFIG_CRYPTO_USER_API_HASH=m
173CONFIG_CRYPTO_USER_API_SKCIPHER=m
174# CONFIG_CRYPTO_HW is not set
175CONFIG_FONTS=y
diff --git a/arch/arm/configs/at91sam9rl_defconfig b/arch/arm/configs/at91sam9rl_defconfig
deleted file mode 100644
index 4c26d344ae88..000000000000
--- a/arch/arm/configs/at91sam9rl_defconfig
+++ /dev/null
@@ -1,92 +0,0 @@
1# CONFIG_LOCALVERSION_AUTO is not set
2# CONFIG_SWAP is not set
3CONFIG_SYSVIPC=y
4CONFIG_LOG_BUF_SHIFT=14
5CONFIG_BLK_DEV_INITRD=y
6CONFIG_EMBEDDED=y
7CONFIG_SLAB=y
8CONFIG_MODULES=y
9CONFIG_MODULE_UNLOAD=y
10# CONFIG_BLK_DEV_BSG is not set
11# CONFIG_IOSCHED_DEADLINE is not set
12# CONFIG_IOSCHED_CFQ is not set
13CONFIG_ARCH_AT91=y
14CONFIG_ARCH_AT91SAM9RL=y
15CONFIG_MACH_AT91SAM9RLEK=y
16# CONFIG_ARM_THUMB is not set
17CONFIG_AEABI=y
18CONFIG_ZBOOT_ROM_TEXT=0x0
19CONFIG_ZBOOT_ROM_BSS=0x0
20CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,17105363 root=/dev/ram0 rw"
21CONFIG_AUTO_ZRELADDR=y
22CONFIG_NET=y
23CONFIG_UNIX=y
24CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
25CONFIG_DEVTMPFS=y
26CONFIG_DEVTMPFS_MOUNT=y
27CONFIG_MTD=y
28CONFIG_MTD_CMDLINE_PARTS=y
29CONFIG_MTD_BLOCK=y
30CONFIG_MTD_DATAFLASH=y
31CONFIG_MTD_NAND=y
32CONFIG_MTD_NAND_ATMEL=y
33CONFIG_MTD_UBI=y
34CONFIG_BLK_DEV_LOOP=y
35CONFIG_BLK_DEV_RAM=y
36CONFIG_BLK_DEV_RAM_COUNT=4
37CONFIG_BLK_DEV_RAM_SIZE=24576
38CONFIG_SCSI=y
39CONFIG_BLK_DEV_SD=y
40# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
41CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
42CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
43CONFIG_INPUT_EVDEV=y
44# CONFIG_INPUT_KEYBOARD is not set
45# CONFIG_INPUT_MOUSE is not set
46CONFIG_INPUT_TOUCHSCREEN=y
47# CONFIG_SERIO is not set
48CONFIG_SERIAL_ATMEL=y
49CONFIG_SERIAL_ATMEL_CONSOLE=y
50# CONFIG_HW_RANDOM is not set
51CONFIG_I2C=y
52CONFIG_I2C_CHARDEV=y
53CONFIG_I2C_GPIO=y
54CONFIG_SPI=y
55CONFIG_SPI_ATMEL=y
56CONFIG_POWER_SUPPLY=y
57CONFIG_POWER_RESET=y
58# CONFIG_HWMON is not set
59CONFIG_WATCHDOG=y
60CONFIG_WATCHDOG_NOWAYOUT=y
61CONFIG_AT91SAM9X_WATCHDOG=y
62CONFIG_FB=y
63CONFIG_FB_ATMEL=y
64CONFIG_USB_GADGET=y
65CONFIG_USB_ATMEL_USBA=y
66CONFIG_MMC=y
67CONFIG_MMC_ATMELMCI=m
68CONFIG_NEW_LEDS=y
69CONFIG_LEDS_CLASS=y
70CONFIG_LEDS_GPIO=y
71CONFIG_LEDS_PWM=y
72CONFIG_LEDS_TRIGGERS=y
73CONFIG_LEDS_TRIGGER_HEARTBEAT=y
74CONFIG_RTC_CLASS=y
75CONFIG_RTC_DRV_AT91SAM9=y
76CONFIG_IIO=y
77CONFIG_AT91_ADC=y
78CONFIG_PWM=y
79CONFIG_PWM_ATMEL=y
80CONFIG_EXT4_FS=y
81CONFIG_VFAT_FS=y
82CONFIG_TMPFS=y
83CONFIG_UBIFS_FS=y
84CONFIG_CRAMFS=y
85CONFIG_NLS_CODEPAGE_437=y
86CONFIG_NLS_CODEPAGE_850=y
87CONFIG_NLS_ISO8859_1=y
88CONFIG_NLS_ISO8859_15=y
89CONFIG_NLS_UTF8=y
90CONFIG_DEBUG_INFO=y
91CONFIG_DEBUG_USER=y
92CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/at91x40_defconfig b/arch/arm/configs/at91x40_defconfig
deleted file mode 100644
index c55e9212fcbb..000000000000
--- a/arch/arm/configs/at91x40_defconfig
+++ /dev/null
@@ -1,48 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_LOG_BUF_SHIFT=14
3CONFIG_EMBEDDED=y
4# CONFIG_HOTPLUG is not set
5# CONFIG_ELF_CORE is not set
6# CONFIG_FUTEX is not set
7# CONFIG_TIMERFD is not set
8# CONFIG_VM_EVENT_COUNTERS is not set
9# CONFIG_COMPAT_BRK is not set
10CONFIG_SLAB=y
11# CONFIG_LBDAF is not set
12# CONFIG_BLK_DEV_BSG is not set
13# CONFIG_IOSCHED_DEADLINE is not set
14# CONFIG_IOSCHED_CFQ is not set
15# CONFIG_MMU is not set
16CONFIG_ARCH_AT91=y
17CONFIG_ARCH_AT91X40=y
18CONFIG_MACH_AT91EB01=y
19CONFIG_AT91_EARLY_USART0=y
20CONFIG_CPU_ARM7TDMI=y
21CONFIG_SET_MEM_PARAM=y
22CONFIG_DRAM_BASE=0x01000000
23CONFIG_DRAM_SIZE=0x00400000
24CONFIG_FLASH_MEM_BASE=0x01400000
25CONFIG_PROCESSOR_ID=0x14000040
26CONFIG_ZBOOT_ROM_TEXT=0x0
27CONFIG_ZBOOT_ROM_BSS=0x0
28CONFIG_BINFMT_FLAT=y
29# CONFIG_SUSPEND is not set
30# CONFIG_FW_LOADER is not set
31CONFIG_MTD=y
32CONFIG_MTD_PARTITIONS=y
33CONFIG_MTD_CHAR=y
34CONFIG_MTD_BLOCK=y
35CONFIG_MTD_RAM=y
36CONFIG_MTD_ROM=y
37CONFIG_BLK_DEV_RAM=y
38# CONFIG_INPUT is not set
39# CONFIG_SERIO is not set
40# CONFIG_VT is not set
41# CONFIG_DEVKMEM is not set
42# CONFIG_HW_RANDOM is not set
43# CONFIG_HWMON is not set
44# CONFIG_USB_SUPPORT is not set
45CONFIG_EXT2_FS=y
46# CONFIG_DNOTIFY is not set
47CONFIG_ROMFS_FS=y
48# CONFIG_ENABLE_MUST_CHECK is not set
diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig
index c9089c927daf..299ca18bbd75 100644
--- a/arch/arm/configs/sama5_defconfig
+++ b/arch/arm/configs/sama5_defconfig
@@ -20,7 +20,6 @@ CONFIG_ARCH_AT91=y
20CONFIG_SOC_SAM_V7=y 20CONFIG_SOC_SAM_V7=y
21CONFIG_SOC_SAMA5D3=y 21CONFIG_SOC_SAMA5D3=y
22CONFIG_SOC_SAMA5D4=y 22CONFIG_SOC_SAMA5D4=y
23CONFIG_MACH_SAMA5_DT=y
24CONFIG_AEABI=y 23CONFIG_AEABI=y
25CONFIG_UACCESS_WITH_MEMCPY=y 24CONFIG_UACCESS_WITH_MEMCPY=y
26CONFIG_ZBOOT_ROM_TEXT=0x0 25CONFIG_ZBOOT_ROM_TEXT=0x0
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 0e6d548b70d9..2395c68b3e32 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -15,27 +15,10 @@ config HAVE_AT91_DBGU1
15config HAVE_AT91_DBGU2 15config HAVE_AT91_DBGU2
16 bool 16 bool
17 17
18config AT91_USE_OLD_CLK
19 bool
20
21config AT91_PMC_UNIT
22 bool
23 default !ARCH_AT91X40
24
25config COMMON_CLK_AT91 18config COMMON_CLK_AT91
26 bool 19 bool
27 default AT91_PMC_UNIT && USE_OF && !AT91_USE_OLD_CLK
28 select COMMON_CLK 20 select COMMON_CLK
29 21
30config OLD_CLK_AT91
31 bool
32 default AT91_PMC_UNIT && AT91_USE_OLD_CLK
33
34config OLD_IRQ_AT91
35 bool
36 select MULTI_IRQ_HANDLER
37 select SPARSE_IRQ
38
39config HAVE_AT91_SMD 22config HAVE_AT91_SMD
40 bool 23 bool
41 24
@@ -44,20 +27,22 @@ config HAVE_AT91_H32MX
44 27
45config SOC_AT91SAM9 28config SOC_AT91SAM9
46 bool 29 bool
47 select ATMEL_AIC_IRQ if !OLD_IRQ_AT91 30 select ATMEL_AIC_IRQ
31 select COMMON_CLK_AT91
48 select CPU_ARM926T 32 select CPU_ARM926T
49 select GENERIC_CLOCKEVENTS 33 select GENERIC_CLOCKEVENTS
50 select MEMORY if USE_OF 34 select MEMORY
51 select ATMEL_SDRAMC if USE_OF 35 select ATMEL_SDRAMC
52 36
53config SOC_SAMA5 37config SOC_SAMA5
54 bool 38 bool
55 select ATMEL_AIC5_IRQ 39 select ATMEL_AIC5_IRQ
40 select COMMON_CLK_AT91
56 select CPU_V7 41 select CPU_V7
57 select GENERIC_CLOCKEVENTS 42 select GENERIC_CLOCKEVENTS
58 select USE_OF
59 select MEMORY 43 select MEMORY
60 select ATMEL_SDRAMC 44 select ATMEL_SDRAMC
45 select PHYLIB if NETDEVICES
61 46
62menu "Atmel AT91 System-on-Chip" 47menu "Atmel AT91 System-on-Chip"
63 48
@@ -65,16 +50,6 @@ choice
65 50
66 prompt "Core type" 51 prompt "Core type"
67 52
68config ARCH_AT91X40
69 bool "ARM7 AT91X40"
70 depends on !MMU
71 select CPU_ARM7TDMI
72 select ARCH_USES_GETTIMEOFFSET
73 select OLD_IRQ_AT91
74
75 help
76 Select this if you are using one of Atmel's AT91X40 SoC.
77
78config SOC_SAM_V4_V5 53config SOC_SAM_V4_V5
79 bool "ARM9 AT91SAM9/AT91RM9200" 54 bool "ARM9 AT91SAM9/AT91RM9200"
80 help 55 help
@@ -122,7 +97,8 @@ endif
122if SOC_SAM_V4_V5 97if SOC_SAM_V4_V5
123config SOC_AT91RM9200 98config SOC_AT91RM9200
124 bool "AT91RM9200" 99 bool "AT91RM9200"
125 select ATMEL_AIC_IRQ if !OLD_IRQ_AT91 100 select ATMEL_AIC_IRQ
101 select COMMON_CLK_AT91
126 select CPU_ARM920T 102 select CPU_ARM920T
127 select GENERIC_CLOCKEVENTS 103 select GENERIC_CLOCKEVENTS
128 select HAVE_AT91_DBGU0 104 select HAVE_AT91_DBGU0
@@ -198,37 +174,11 @@ config SOC_AT91SAM9N12
198# ---------------------------------------------------------- 174# ----------------------------------------------------------
199endif # SOC_SAM_V4_V5 175endif # SOC_SAM_V4_V5
200 176
201
202if SOC_SAM_V4_V5 || ARCH_AT91X40
203source arch/arm/mach-at91/Kconfig.non_dt
204endif
205
206comment "Generic Board Type"
207
208config MACH_AT91RM9200_DT 177config MACH_AT91RM9200_DT
209 bool "Atmel AT91RM9200 Evaluation Kits with device-tree support" 178 def_bool SOC_AT91RM9200
210 depends on SOC_AT91RM9200
211 select USE_OF
212 help
213 Select this if you want to experiment device-tree with
214 an Atmel RM9200 Evaluation Kit.
215 179
216config MACH_AT91SAM9_DT 180config MACH_AT91SAM9_DT
217 bool "Atmel AT91SAM Evaluation Kits with device-tree support" 181 def_bool SOC_AT91SAM9
218 depends on SOC_AT91SAM9
219 select USE_OF
220 help
221 Select this if you want to experiment device-tree with
222 an Atmel Evaluation Kit.
223
224config MACH_SAMA5_DT
225 bool "Atmel SAMA5 Evaluation Kits with device-tree support"
226 depends on SOC_SAMA5
227 select USE_OF
228 select PHYLIB if NETDEVICES
229 help
230 Select this if you want to experiment device-tree with
231 an Atmel Evaluation Kit.
232 182
233# ---------------------------------------------------------- 183# ----------------------------------------------------------
234 184
@@ -251,7 +201,7 @@ config AT91_TIMER_HZ
251 int "Kernel HZ (jiffies per second)" 201 int "Kernel HZ (jiffies per second)"
252 range 32 1024 202 range 32 1024
253 depends on ARCH_AT91 203 depends on ARCH_AT91
254 default "128" if ARCH_AT91RM9200 204 default "128" if SOC_AT91RM9200
255 default "100" 205 default "100"
256 help 206 help
257 On AT91rm9200 chips where you're using a system clock derived 207 On AT91rm9200 chips where you're using a system clock derived
diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt
deleted file mode 100644
index d8e88219edb4..000000000000
--- a/arch/arm/mach-at91/Kconfig.non_dt
+++ /dev/null
@@ -1,344 +0,0 @@
1menu "Atmel Non-DT world"
2
3config HAVE_AT91_DATAFLASH_CARD
4 bool
5
6choice
7 prompt "Atmel AT91 Processor Devices for non DT boards"
8 depends on !ARCH_AT91X40
9
10config ARCH_AT91_NONE
11 bool "None"
12
13config ARCH_AT91RM9200
14 bool "AT91RM9200"
15 select SOC_AT91RM9200
16 select AT91_USE_OLD_CLK
17 select OLD_IRQ_AT91
18
19config ARCH_AT91SAM9260
20 bool "AT91SAM9260 or AT91SAM9XE or AT91SAM9G20"
21 select SOC_AT91SAM9260
22 select AT91_USE_OLD_CLK
23 select OLD_IRQ_AT91
24
25config ARCH_AT91SAM9261
26 bool "AT91SAM9261 or AT91SAM9G10"
27 select SOC_AT91SAM9261
28 select AT91_USE_OLD_CLK
29 select OLD_IRQ_AT91
30
31config ARCH_AT91SAM9263
32 bool "AT91SAM9263"
33 select SOC_AT91SAM9263
34 select AT91_USE_OLD_CLK
35 select OLD_IRQ_AT91
36
37config ARCH_AT91SAM9RL
38 bool "AT91SAM9RL"
39 select SOC_AT91SAM9RL
40 select AT91_USE_OLD_CLK
41 select OLD_IRQ_AT91
42
43config ARCH_AT91SAM9G45
44 bool "AT91SAM9G45"
45 select SOC_AT91SAM9G45
46 select AT91_USE_OLD_CLK
47 select OLD_IRQ_AT91
48
49endchoice
50
51config ARCH_AT91SAM9G20
52 bool
53 select ARCH_AT91SAM9260
54
55config ARCH_AT91SAM9G10
56 bool
57 select ARCH_AT91SAM9261
58
59# ----------------------------------------------------------
60
61if ARCH_AT91RM9200
62
63comment "AT91RM9200 Board Type"
64
65config MACH_ONEARM
66 bool "Ajeco 1ARM Single Board Computer"
67 help
68 Select this if you are using Ajeco's 1ARM Single Board Computer.
69 <http://www.ajeco.fi/>
70
71config MACH_AT91RM9200EK
72 bool "Atmel AT91RM9200-EK Evaluation Kit"
73 select HAVE_AT91_DATAFLASH_CARD
74 help
75 Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit.
76 <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3507>
77
78config MACH_CSB337
79 bool "Cogent CSB337"
80 help
81 Select this if you are using Cogent's CSB337 board.
82 <http://www.cogcomp.com/csb_csb337.htm>
83
84config MACH_CSB637
85 bool "Cogent CSB637"
86 help
87 Select this if you are using Cogent's CSB637 board.
88 <http://www.cogcomp.com/csb_csb637.htm>
89
90config MACH_CARMEVA
91 bool "Conitec ARM&EVA"
92 help
93 Select this if you are using Conitec's AT91RM9200-MCU-Module.
94 <http://www.conitec.net/english/linuxboard.php>
95
96config MACH_ATEB9200
97 bool "Embest ATEB9200"
98 help
99 Select this if you are using Embest's ATEB9200 board.
100 <http://www.embedinfo.com/english/product/ATEB9200.asp>
101
102config MACH_KB9200
103 bool "KwikByte KB920x"
104 help
105 Select this if you are using KwikByte's KB920x board.
106 <http://www.kwikbyte.com/KB9202.html>
107
108config MACH_PICOTUX2XX
109 bool "picotux 200"
110 help
111 Select this if you are using a picotux 200.
112 <http://www.picotux.com/>
113
114config MACH_KAFA
115 bool "Sperry-Sun KAFA board"
116 help
117 Select this if you are using Sperry-Sun's KAFA board.
118
119config MACH_ECBAT91
120 bool "emQbit ECB_AT91 SBC"
121 select HAVE_AT91_DATAFLASH_CARD
122 help
123 Select this if you are using emQbit's ECB_AT91 board.
124 <http://wiki.emqbit.com/free-ecb-at91>
125
126config MACH_YL9200
127 bool "ucDragon YL-9200"
128 help
129 Select this if you are using the ucDragon YL-9200 board.
130
131config MACH_CPUAT91
132 bool "Eukrea CPUAT91"
133 help
134 Select this if you are using the Eukrea Electromatique's
135 CPUAT91 board <http://www.eukrea.com/>.
136
137config MACH_ECO920
138 bool "eco920"
139 help
140 Select this if you are using the eco920 board
141endif
142
143# ----------------------------------------------------------
144
145if ARCH_AT91SAM9260
146
147comment "AT91SAM9260 Variants"
148
149comment "AT91SAM9260 / AT91SAM9XE Board Type"
150
151config MACH_AT91SAM9260EK
152 bool "Atmel AT91SAM9260-EK / AT91SAM9XE Evaluation Kit"
153 select HAVE_AT91_DATAFLASH_CARD
154 help
155 Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit
156 <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933>
157
158config MACH_CAM60
159 bool "KwikByte KB9260 (CAM60) board"
160 help
161 Select this if you are using KwikByte's KB9260 (CAM60) board based on the Atmel AT91SAM9260.
162 <http://www.kwikbyte.com/KB9260.html>
163
164config MACH_SAM9_L9260
165 bool "Olimex SAM9-L9260 board"
166 select HAVE_AT91_DATAFLASH_CARD
167 help
168 Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260.
169 <http://www.olimex.com/dev/sam9-L9260.html>
170
171config MACH_AFEB9260
172 bool "Custom afeb9260 board v1"
173 help
174 Select this if you are using custom afeb9260 board based on
175 open hardware design. Select this for revision 1 of the board.
176 <svn://194.85.238.22/home/users/george/svn/arm9eb>
177 <http://groups.google.com/group/arm9fpga-evolution-board>
178
179config MACH_CPU9260
180 bool "Eukrea CPU9260 board"
181 help
182 Select this if you are using a Eukrea Electromatique's
183 CPU9260 Board <http://www.eukrea.com/>
184
185config MACH_FLEXIBITY
186 bool "Flexibity Connect board"
187 help
188 Select this if you are using Flexibity Connect board
189 <http://www.flexibity.com>
190
191comment "AT91SAM9G20 Board Type"
192
193config MACH_AT91SAM9G20EK
194 bool "Atmel AT91SAM9G20-EK Evaluation Kit"
195 select HAVE_AT91_DATAFLASH_CARD
196 help
197 Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit
198 that embeds only one SD/MMC slot.
199
200config MACH_AT91SAM9G20EK_2MMC
201 depends on MACH_AT91SAM9G20EK
202 bool "Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots"
203 help
204 Select this if you are using an Atmel AT91SAM9G20-EK Evaluation Kit
205 with 2 SD/MMC Slots. This is the case for AT91SAM9G20-EK rev. C and
206 onwards.
207 <http://www.atmel.com/tools/SAM9G20-EK.aspx>
208
209config MACH_CPU9G20
210 bool "Eukrea CPU9G20 board"
211 help
212 Select this if you are using a Eukrea Electromatique's
213 CPU9G20 Board <http://www.eukrea.com/>
214
215config MACH_PORTUXG20
216 bool "taskit PortuxG20"
217 help
218 Select this if you are using taskit's PortuxG20.
219 <http://www.taskit.de/en/>
220
221config MACH_STAMP9G20
222 bool "taskit Stamp9G20 CPU module"
223 help
224 Select this if you are using taskit's Stamp9G20 CPU module on its
225 evaluation board.
226 <http://www.taskit.de/en/>
227
228config MACH_PCONTROL_G20
229 bool "PControl G20 CPU module"
230 help
231 Select this if you are using taskit's Stamp9G20 CPU module on this
232 carrier board, being the decentralized unit of a building automation
233 system; featuring nvram, eth-switch, iso-rs485, display, io
234
235config MACH_GSIA18S
236 bool "GS_IA18_S board"
237 help
238 This enables support for the GS_IA18_S board
239 produced by GeoSIG Ltd company. This is an internet accelerograph.
240 <http://www.geosig.com>
241
242config MACH_SNAPPER_9260
243 bool "Bluewater Systems Snapper 9260/9G20 module"
244 help
245 Select this if you are using the Bluewater Systems Snapper 9260 or
246 Snapper 9G20 modules.
247 <http://www.bluewatersys.com/>
248endif
249
250# ----------------------------------------------------------
251
252if ARCH_AT91SAM9261
253
254comment "AT91SAM9261 Board Type"
255
256config MACH_AT91SAM9261EK
257 bool "Atmel AT91SAM9261-EK Evaluation Kit"
258 select HAVE_AT91_DATAFLASH_CARD
259 help
260 Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit.
261 <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820>
262
263comment "AT91SAM9G10 Board Type"
264
265config MACH_AT91SAM9G10EK
266 bool "Atmel AT91SAM9G10-EK Evaluation Kit"
267 select HAVE_AT91_DATAFLASH_CARD
268 help
269 Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit.
270 <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588>
271
272endif
273
274# ----------------------------------------------------------
275
276if ARCH_AT91SAM9263
277
278comment "AT91SAM9263 Board Type"
279
280config MACH_AT91SAM9263EK
281 bool "Atmel AT91SAM9263-EK Evaluation Kit"
282 select HAVE_AT91_DATAFLASH_CARD
283 help
284 Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit.
285 <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057>
286
287endif
288
289# ----------------------------------------------------------
290
291if ARCH_AT91SAM9RL
292
293comment "AT91SAM9RL Board Type"
294
295config MACH_AT91SAM9RLEK
296 bool "Atmel AT91SAM9RL-EK Evaluation Kit"
297 help
298 Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit.
299
300endif
301
302# ----------------------------------------------------------
303
304if ARCH_AT91SAM9G45
305
306comment "AT91SAM9G45 Board Type"
307
308config MACH_AT91SAM9M10G45EK
309 bool "Atmel AT91SAM9M10G45-EK Evaluation Kits"
310 help
311 Select this if you are using Atmel's AT91SAM9M10G45-EK Evaluation Kit.
312 Those boards can be populated with any SoC of AT91SAM9G45 or AT91SAM9M10
313 families: AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11.
314 <http://www.atmel.com/tools/SAM9M10-G45-EK.aspx>
315
316endif
317
318# ----------------------------------------------------------
319
320if ARCH_AT91X40
321
322comment "AT91X40 Board Type"
323
324config MACH_AT91EB01
325 bool "Atmel AT91EB01 Evaluation Kit"
326 help
327 Select this if you are using Atmel's AT91EB01 Evaluation Kit.
328 It is also a popular target for simulators such as GDB's
329 ARM simulator (commonly known as the ARMulator) and the
330 Skyeye simulator.
331
332endif
333
334# ----------------------------------------------------------
335
336comment "AT91 Board Options"
337
338config MTD_AT91_DATAFLASH_CARD
339 bool "Enable DataFlash Card support"
340 depends on HAVE_AT91_DATAFLASH_CARD
341 help
342 Enable support for the DataFlash card.
343
344endmenu
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 1b9ae0257a6e..7b6424d40764 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -2,10 +2,8 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5obj-y := gpio.o setup.o sysirq_mask.o 5obj-y := setup.o sysirq_mask.o
6 6
7obj-$(CONFIG_OLD_IRQ_AT91) += irq.o
8obj-$(CONFIG_OLD_CLK_AT91) += clock.o
9obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o 7obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o
10 8
11# CPU-specific support 9# CPU-specific support
@@ -20,73 +18,12 @@ obj-$(CONFIG_SOC_AT91SAM9RL) += at91sam9rl.o
20obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o 18obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o
21obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o 19obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o
22 20
23obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200_devices.o
24obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260_devices.o
25obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261_devices.o
26obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263_devices.o
27obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl_devices.o
28obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45_devices.o
29obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
30
31# AT91RM9200 board-specific support
32obj-$(CONFIG_MACH_ONEARM) += board-1arm.o
33obj-$(CONFIG_MACH_AT91RM9200EK) += board-rm9200ek.o
34obj-$(CONFIG_MACH_CSB337) += board-csb337.o
35obj-$(CONFIG_MACH_CSB637) += board-csb637.o
36obj-$(CONFIG_MACH_CARMEVA) += board-carmeva.o
37obj-$(CONFIG_MACH_KB9200) += board-kb9202.o
38obj-$(CONFIG_MACH_ATEB9200) += board-eb9200.o
39obj-$(CONFIG_MACH_KAFA) += board-kafa.o
40obj-$(CONFIG_MACH_PICOTUX2XX) += board-picotux200.o
41obj-$(CONFIG_MACH_ECBAT91) += board-ecbat91.o
42obj-$(CONFIG_MACH_YL9200) += board-yl-9200.o
43obj-$(CONFIG_MACH_CPUAT91) += board-cpuat91.o
44obj-$(CONFIG_MACH_ECO920) += board-eco920.o
45
46# AT91SAM9260 board-specific support
47obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
48obj-$(CONFIG_MACH_CAM60) += board-cam60.o
49obj-$(CONFIG_MACH_SAM9_L9260) += board-sam9-l9260.o
50obj-$(CONFIG_MACH_AFEB9260) += board-afeb-9260v1.o
51obj-$(CONFIG_MACH_CPU9260) += board-cpu9krea.o
52obj-$(CONFIG_MACH_FLEXIBITY) += board-flexibity.o
53
54# AT91SAM9261 board-specific support
55obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o
56obj-$(CONFIG_MACH_AT91SAM9G10EK) += board-sam9261ek.o
57
58# AT91SAM9263 board-specific support
59obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o
60
61# AT91SAM9RL board-specific support
62obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o
63
64# AT91SAM9G20 board-specific support
65obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o
66obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o
67obj-$(CONFIG_MACH_STAMP9G20) += board-stamp9g20.o
68obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o
69obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o board-stamp9g20.o
70obj-$(CONFIG_MACH_GSIA18S) += board-gsia18s.o board-stamp9g20.o
71
72# AT91SAM9260/AT91SAM9G20 board-specific support
73obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
74
75# AT91SAM9G45 board-specific support
76obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
77
78# AT91SAM board with device-tree 21# AT91SAM board with device-tree
79obj-$(CONFIG_MACH_AT91RM9200_DT) += board-dt-rm9200.o 22obj-$(CONFIG_MACH_AT91RM9200_DT) += board-dt-rm9200.o
80obj-$(CONFIG_MACH_AT91SAM9_DT) += board-dt-sam9.o 23obj-$(CONFIG_MACH_AT91SAM9_DT) += board-dt-sam9.o
81 24
82# SAMA5 board with device-tree 25# SAMA5 board with device-tree
83obj-$(CONFIG_MACH_SAMA5_DT) += board-dt-sama5.o 26obj-$(CONFIG_SOC_SAMA5) += board-dt-sama5.o
84
85# AT91X40 board-specific support
86obj-$(CONFIG_MACH_AT91EB01) += board-eb01.o
87
88# Drivers
89obj-y += leds.o
90 27
91# Power Management 28# Power Management
92obj-$(CONFIG_PM) += pm.o 29obj-$(CONFIG_PM) += pm.o
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
index 5309f9b6aabc..29ed0fa374ca 100644
--- a/arch/arm/mach-at91/Makefile.boot
+++ b/arch/arm/mach-at91/Makefile.boot
@@ -3,12 +3,6 @@
3# PARAMS_PHYS must be within 4MB of ZRELADDR 3# PARAMS_PHYS must be within 4MB of ZRELADDR
4# INITRD_PHYS must be in RAM 4# INITRD_PHYS must be in RAM
5 5
6ifeq ($(CONFIG_ARCH_AT91SAM9G45),y)
7 zreladdr-y += 0x70008000
8params_phys-y := 0x70000100
9initrd_phys-y := 0x70410000
10else
11 zreladdr-y += 0x20008000 6 zreladdr-y += 0x20008000
12params_phys-y := 0x20000100 7params_phys-y := 0x20000100
13initrd_phys-y := 0x20410000 8initrd_phys-y := 0x20410000
14endif
diff --git a/arch/arm/mach-at91/at91_aic.h b/arch/arm/mach-at91/at91_aic.h
deleted file mode 100644
index eaea66197fa1..000000000000
--- a/arch/arm/mach-at91/at91_aic.h
+++ /dev/null
@@ -1,99 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91_aic.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Advanced Interrupt Controller (AIC) - System peripherals registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_AIC_H
17#define AT91_AIC_H
18
19#ifndef __ASSEMBLY__
20extern void __iomem *at91_aic_base;
21
22#define at91_aic_read(field) \
23 __raw_readl(at91_aic_base + field)
24
25#define at91_aic_write(field, value) \
26 __raw_writel(value, at91_aic_base + field)
27#else
28.extern at91_aic_base
29#endif
30
31/* Number of irq lines managed by AIC */
32#define NR_AIC_IRQS 32
33#define NR_AIC5_IRQS 128
34
35#define AT91_AIC5_SSR 0x0 /* Source Select Register [AIC5] */
36#define AT91_AIC5_INTSEL_MSK (0x7f << 0) /* Interrupt Line Selection Mask */
37
38#define AT91_AIC_IRQ_MIN_PRIORITY 0
39#define AT91_AIC_IRQ_MAX_PRIORITY 7
40
41#define AT91_AIC_SMR(n) ((n) * 4) /* Source Mode Registers 0-31 */
42#define AT91_AIC5_SMR 0x4 /* Source Mode Register [AIC5] */
43#define AT91_AIC_PRIOR (7 << 0) /* Priority Level */
44#define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */
45#define AT91_AIC_SRCTYPE_LOW (0 << 5)
46#define AT91_AIC_SRCTYPE_FALLING (1 << 5)
47#define AT91_AIC_SRCTYPE_HIGH (2 << 5)
48#define AT91_AIC_SRCTYPE_RISING (3 << 5)
49
50#define AT91_AIC_SVR(n) (0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */
51#define AT91_AIC5_SVR 0x8 /* Source Vector Register [AIC5] */
52#define AT91_AIC_IVR 0x100 /* Interrupt Vector Register */
53#define AT91_AIC5_IVR 0x10 /* Interrupt Vector Register [AIC5] */
54#define AT91_AIC_FVR 0x104 /* Fast Interrupt Vector Register */
55#define AT91_AIC5_FVR 0x14 /* Fast Interrupt Vector Register [AIC5] */
56#define AT91_AIC_ISR 0x108 /* Interrupt Status Register */
57#define AT91_AIC5_ISR 0x18 /* Interrupt Status Register [AIC5] */
58#define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */
59
60#define AT91_AIC_IPR 0x10c /* Interrupt Pending Register */
61#define AT91_AIC5_IPR0 0x20 /* Interrupt Pending Register 0 [AIC5] */
62#define AT91_AIC5_IPR1 0x24 /* Interrupt Pending Register 1 [AIC5] */
63#define AT91_AIC5_IPR2 0x28 /* Interrupt Pending Register 2 [AIC5] */
64#define AT91_AIC5_IPR3 0x2c /* Interrupt Pending Register 3 [AIC5] */
65#define AT91_AIC_IMR 0x110 /* Interrupt Mask Register */
66#define AT91_AIC5_IMR 0x30 /* Interrupt Mask Register [AIC5] */
67#define AT91_AIC_CISR 0x114 /* Core Interrupt Status Register */
68#define AT91_AIC5_CISR 0x34 /* Core Interrupt Status Register [AIC5] */
69#define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */
70#define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */
71
72#define AT91_AIC_IECR 0x120 /* Interrupt Enable Command Register */
73#define AT91_AIC5_IECR 0x40 /* Interrupt Enable Command Register [AIC5] */
74#define AT91_AIC_IDCR 0x124 /* Interrupt Disable Command Register */
75#define AT91_AIC5_IDCR 0x44 /* Interrupt Disable Command Register [AIC5] */
76#define AT91_AIC_ICCR 0x128 /* Interrupt Clear Command Register */
77#define AT91_AIC5_ICCR 0x48 /* Interrupt Clear Command Register [AIC5] */
78#define AT91_AIC_ISCR 0x12c /* Interrupt Set Command Register */
79#define AT91_AIC5_ISCR 0x4c /* Interrupt Set Command Register [AIC5] */
80#define AT91_AIC_EOICR 0x130 /* End of Interrupt Command Register */
81#define AT91_AIC5_EOICR 0x38 /* End of Interrupt Command Register [AIC5] */
82#define AT91_AIC_SPU 0x134 /* Spurious Interrupt Vector Register */
83#define AT91_AIC5_SPU 0x3c /* Spurious Interrupt Vector Register [AIC5] */
84#define AT91_AIC_DCR 0x138 /* Debug Control Register */
85#define AT91_AIC5_DCR 0x6c /* Debug Control Register [AIC5] */
86#define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */
87#define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */
88
89#define AT91_AIC_FFER 0x140 /* Fast Forcing Enable Register [SAM9 only] */
90#define AT91_AIC5_FFER 0x50 /* Fast Forcing Enable Register [AIC5] */
91#define AT91_AIC_FFDR 0x144 /* Fast Forcing Disable Register [SAM9 only] */
92#define AT91_AIC5_FFDR 0x54 /* Fast Forcing Disable Register [AIC5] */
93#define AT91_AIC_FFSR 0x148 /* Fast Forcing Status Register [SAM9 only] */
94#define AT91_AIC5_FFSR 0x58 /* Fast Forcing Status Register [AIC5] */
95
96void at91_aic_handle_irq(struct pt_regs *regs);
97void at91_aic5_handle_irq(struct pt_regs *regs);
98
99#endif
diff --git a/arch/arm/mach-at91/at91_tc.h b/arch/arm/mach-at91/at91_tc.h
deleted file mode 100644
index 46a317fd7164..000000000000
--- a/arch/arm/mach-at91/at91_tc.h
+++ /dev/null
@@ -1,146 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91_tc.h
3 *
4 * Copyright (C) SAN People
5 *
6 * Timer/Counter Unit (TC) registers.
7 * Based on AT91RM9200 datasheet revision E.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91_TC_H
16#define AT91_TC_H
17
18#define AT91_TC_BCR 0xc0 /* TC Block Control Register */
19#define AT91_TC_SYNC (1 << 0) /* Synchro Command */
20
21#define AT91_TC_BMR 0xc4 /* TC Block Mode Register */
22#define AT91_TC_TC0XC0S (3 << 0) /* External Clock Signal 0 Selection */
23#define AT91_TC_TC0XC0S_TCLK0 (0 << 0)
24#define AT91_TC_TC0XC0S_NONE (1 << 0)
25#define AT91_TC_TC0XC0S_TIOA1 (2 << 0)
26#define AT91_TC_TC0XC0S_TIOA2 (3 << 0)
27#define AT91_TC_TC1XC1S (3 << 2) /* External Clock Signal 1 Selection */
28#define AT91_TC_TC1XC1S_TCLK1 (0 << 2)
29#define AT91_TC_TC1XC1S_NONE (1 << 2)
30#define AT91_TC_TC1XC1S_TIOA0 (2 << 2)
31#define AT91_TC_TC1XC1S_TIOA2 (3 << 2)
32#define AT91_TC_TC2XC2S (3 << 4) /* External Clock Signal 2 Selection */
33#define AT91_TC_TC2XC2S_TCLK2 (0 << 4)
34#define AT91_TC_TC2XC2S_NONE (1 << 4)
35#define AT91_TC_TC2XC2S_TIOA0 (2 << 4)
36#define AT91_TC_TC2XC2S_TIOA1 (3 << 4)
37
38
39#define AT91_TC_CCR 0x00 /* Channel Control Register */
40#define AT91_TC_CLKEN (1 << 0) /* Counter Clock Enable Command */
41#define AT91_TC_CLKDIS (1 << 1) /* Counter CLock Disable Command */
42#define AT91_TC_SWTRG (1 << 2) /* Software Trigger Command */
43
44#define AT91_TC_CMR 0x04 /* Channel Mode Register */
45#define AT91_TC_TCCLKS (7 << 0) /* Capture/Waveform Mode: Clock Selection */
46#define AT91_TC_TIMER_CLOCK1 (0 << 0)
47#define AT91_TC_TIMER_CLOCK2 (1 << 0)
48#define AT91_TC_TIMER_CLOCK3 (2 << 0)
49#define AT91_TC_TIMER_CLOCK4 (3 << 0)
50#define AT91_TC_TIMER_CLOCK5 (4 << 0)
51#define AT91_TC_XC0 (5 << 0)
52#define AT91_TC_XC1 (6 << 0)
53#define AT91_TC_XC2 (7 << 0)
54#define AT91_TC_CLKI (1 << 3) /* Capture/Waveform Mode: Clock Invert */
55#define AT91_TC_BURST (3 << 4) /* Capture/Waveform Mode: Burst Signal Selection */
56#define AT91_TC_LDBSTOP (1 << 6) /* Capture Mode: Counter Clock Stopped with TB Loading */
57#define AT91_TC_LDBDIS (1 << 7) /* Capture Mode: Counter Clock Disable with RB Loading */
58#define AT91_TC_ETRGEDG (3 << 8) /* Capture Mode: External Trigger Edge Selection */
59#define AT91_TC_ABETRG (1 << 10) /* Capture Mode: TIOA or TIOB External Trigger Selection */
60#define AT91_TC_CPCTRG (1 << 14) /* Capture Mode: RC Compare Trigger Enable */
61#define AT91_TC_WAVE (1 << 15) /* Capture/Waveform mode */
62#define AT91_TC_LDRA (3 << 16) /* Capture Mode: RA Loading Selection */
63#define AT91_TC_LDRB (3 << 18) /* Capture Mode: RB Loading Selection */
64
65#define AT91_TC_CPCSTOP (1 << 6) /* Waveform Mode: Counter Clock Stopped with RC Compare */
66#define AT91_TC_CPCDIS (1 << 7) /* Waveform Mode: Counter Clock Disable with RC Compare */
67#define AT91_TC_EEVTEDG (3 << 8) /* Waveform Mode: External Event Edge Selection */
68#define AT91_TC_EEVTEDG_NONE (0 << 8)
69#define AT91_TC_EEVTEDG_RISING (1 << 8)
70#define AT91_TC_EEVTEDG_FALLING (2 << 8)
71#define AT91_TC_EEVTEDG_BOTH (3 << 8)
72#define AT91_TC_EEVT (3 << 10) /* Waveform Mode: External Event Selection */
73#define AT91_TC_EEVT_TIOB (0 << 10)
74#define AT91_TC_EEVT_XC0 (1 << 10)
75#define AT91_TC_EEVT_XC1 (2 << 10)
76#define AT91_TC_EEVT_XC2 (3 << 10)
77#define AT91_TC_ENETRG (1 << 12) /* Waveform Mode: External Event Trigger Enable */
78#define AT91_TC_WAVESEL (3 << 13) /* Waveform Mode: Waveform Selection */
79#define AT91_TC_WAVESEL_UP (0 << 13)
80#define AT91_TC_WAVESEL_UP_AUTO (2 << 13)
81#define AT91_TC_WAVESEL_UPDOWN (1 << 13)
82#define AT91_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
83#define AT91_TC_ACPA (3 << 16) /* Waveform Mode: RA Compare Effect on TIOA */
84#define AT91_TC_ACPA_NONE (0 << 16)
85#define AT91_TC_ACPA_SET (1 << 16)
86#define AT91_TC_ACPA_CLEAR (2 << 16)
87#define AT91_TC_ACPA_TOGGLE (3 << 16)
88#define AT91_TC_ACPC (3 << 18) /* Waveform Mode: RC Compre Effect on TIOA */
89#define AT91_TC_ACPC_NONE (0 << 18)
90#define AT91_TC_ACPC_SET (1 << 18)
91#define AT91_TC_ACPC_CLEAR (2 << 18)
92#define AT91_TC_ACPC_TOGGLE (3 << 18)
93#define AT91_TC_AEEVT (3 << 20) /* Waveform Mode: External Event Effect on TIOA */
94#define AT91_TC_AEEVT_NONE (0 << 20)
95#define AT91_TC_AEEVT_SET (1 << 20)
96#define AT91_TC_AEEVT_CLEAR (2 << 20)
97#define AT91_TC_AEEVT_TOGGLE (3 << 20)
98#define AT91_TC_ASWTRG (3 << 22) /* Waveform Mode: Software Trigger Effect on TIOA */
99#define AT91_TC_ASWTRG_NONE (0 << 22)
100#define AT91_TC_ASWTRG_SET (1 << 22)
101#define AT91_TC_ASWTRG_CLEAR (2 << 22)
102#define AT91_TC_ASWTRG_TOGGLE (3 << 22)
103#define AT91_TC_BCPB (3 << 24) /* Waveform Mode: RB Compare Effect on TIOB */
104#define AT91_TC_BCPB_NONE (0 << 24)
105#define AT91_TC_BCPB_SET (1 << 24)
106#define AT91_TC_BCPB_CLEAR (2 << 24)
107#define AT91_TC_BCPB_TOGGLE (3 << 24)
108#define AT91_TC_BCPC (3 << 26) /* Waveform Mode: RC Compare Effect on TIOB */
109#define AT91_TC_BCPC_NONE (0 << 26)
110#define AT91_TC_BCPC_SET (1 << 26)
111#define AT91_TC_BCPC_CLEAR (2 << 26)
112#define AT91_TC_BCPC_TOGGLE (3 << 26)
113#define AT91_TC_BEEVT (3 << 28) /* Waveform Mode: External Event Effect on TIOB */
114#define AT91_TC_BEEVT_NONE (0 << 28)
115#define AT91_TC_BEEVT_SET (1 << 28)
116#define AT91_TC_BEEVT_CLEAR (2 << 28)
117#define AT91_TC_BEEVT_TOGGLE (3 << 28)
118#define AT91_TC_BSWTRG (3 << 30) /* Waveform Mode: Software Trigger Effect on TIOB */
119#define AT91_TC_BSWTRG_NONE (0 << 30)
120#define AT91_TC_BSWTRG_SET (1 << 30)
121#define AT91_TC_BSWTRG_CLEAR (2 << 30)
122#define AT91_TC_BSWTRG_TOGGLE (3 << 30)
123
124#define AT91_TC_CV 0x10 /* Counter Value */
125#define AT91_TC_RA 0x14 /* Register A */
126#define AT91_TC_RB 0x18 /* Register B */
127#define AT91_TC_RC 0x1c /* Register C */
128
129#define AT91_TC_SR 0x20 /* Status Register */
130#define AT91_TC_COVFS (1 << 0) /* Counter Overflow Status */
131#define AT91_TC_LOVRS (1 << 1) /* Load Overrun Status */
132#define AT91_TC_CPAS (1 << 2) /* RA Compare Status */
133#define AT91_TC_CPBS (1 << 3) /* RB Compare Status */
134#define AT91_TC_CPCS (1 << 4) /* RC Compare Status */
135#define AT91_TC_LDRAS (1 << 5) /* RA Loading Status */
136#define AT91_TC_LDRBS (1 << 6) /* RB Loading Status */
137#define AT91_TC_ETRGS (1 << 7) /* External Trigger Status */
138#define AT91_TC_CLKSTA (1 << 16) /* Clock Enabling Status */
139#define AT91_TC_MTIOA (1 << 17) /* TIOA Mirror */
140#define AT91_TC_MTIOB (1 << 18) /* TIOB Mirror */
141
142#define AT91_TC_IER 0x24 /* Interrupt Enable Register */
143#define AT91_TC_IDR 0x28 /* Interrupt Disable Register */
144#define AT91_TC_IMR 0x2c /* Interrupt Mask Register */
145
146#endif
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 038702ee8bc6..b52916947535 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -11,296 +11,15 @@
11 */ 11 */
12 12
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/reboot.h>
15#include <linux/clk/at91_pmc.h> 14#include <linux/clk/at91_pmc.h>
16 15
17#include <asm/irq.h>
18#include <asm/mach/arch.h>
19#include <asm/mach/map.h> 16#include <asm/mach/map.h>
20#include <asm/system_misc.h> 17#include <asm/system_misc.h>
21#include <mach/at91rm9200.h>
22#include <mach/at91_st.h> 18#include <mach/at91_st.h>
23#include <mach/cpu.h>
24#include <mach/hardware.h> 19#include <mach/hardware.h>
25 20
26#include "at91_aic.h"
27#include "soc.h" 21#include "soc.h"
28#include "generic.h" 22#include "generic.h"
29#include "sam9_smc.h"
30#include "pm.h"
31
32#if defined(CONFIG_OLD_CLK_AT91)
33#include "clock.h"
34/* --------------------------------------------------------------------
35 * Clocks
36 * -------------------------------------------------------------------- */
37
38/*
39 * The peripheral clocks.
40 */
41static struct clk udc_clk = {
42 .name = "udc_clk",
43 .pmc_mask = 1 << AT91RM9200_ID_UDP,
44 .type = CLK_TYPE_PERIPHERAL,
45};
46static struct clk ohci_clk = {
47 .name = "ohci_clk",
48 .pmc_mask = 1 << AT91RM9200_ID_UHP,
49 .type = CLK_TYPE_PERIPHERAL,
50};
51static struct clk ether_clk = {
52 .name = "ether_clk",
53 .pmc_mask = 1 << AT91RM9200_ID_EMAC,
54 .type = CLK_TYPE_PERIPHERAL,
55};
56static struct clk mmc_clk = {
57 .name = "mci_clk",
58 .pmc_mask = 1 << AT91RM9200_ID_MCI,
59 .type = CLK_TYPE_PERIPHERAL,
60};
61static struct clk twi_clk = {
62 .name = "twi_clk",
63 .pmc_mask = 1 << AT91RM9200_ID_TWI,
64 .type = CLK_TYPE_PERIPHERAL,
65};
66static struct clk usart0_clk = {
67 .name = "usart0_clk",
68 .pmc_mask = 1 << AT91RM9200_ID_US0,
69 .type = CLK_TYPE_PERIPHERAL,
70};
71static struct clk usart1_clk = {
72 .name = "usart1_clk",
73 .pmc_mask = 1 << AT91RM9200_ID_US1,
74 .type = CLK_TYPE_PERIPHERAL,
75};
76static struct clk usart2_clk = {
77 .name = "usart2_clk",
78 .pmc_mask = 1 << AT91RM9200_ID_US2,
79 .type = CLK_TYPE_PERIPHERAL,
80};
81static struct clk usart3_clk = {
82 .name = "usart3_clk",
83 .pmc_mask = 1 << AT91RM9200_ID_US3,
84 .type = CLK_TYPE_PERIPHERAL,
85};
86static struct clk spi_clk = {
87 .name = "spi_clk",
88 .pmc_mask = 1 << AT91RM9200_ID_SPI,
89 .type = CLK_TYPE_PERIPHERAL,
90};
91static struct clk pioA_clk = {
92 .name = "pioA_clk",
93 .pmc_mask = 1 << AT91RM9200_ID_PIOA,
94 .type = CLK_TYPE_PERIPHERAL,
95};
96static struct clk pioB_clk = {
97 .name = "pioB_clk",
98 .pmc_mask = 1 << AT91RM9200_ID_PIOB,
99 .type = CLK_TYPE_PERIPHERAL,
100};
101static struct clk pioC_clk = {
102 .name = "pioC_clk",
103 .pmc_mask = 1 << AT91RM9200_ID_PIOC,
104 .type = CLK_TYPE_PERIPHERAL,
105};
106static struct clk pioD_clk = {
107 .name = "pioD_clk",
108 .pmc_mask = 1 << AT91RM9200_ID_PIOD,
109 .type = CLK_TYPE_PERIPHERAL,
110};
111static struct clk ssc0_clk = {
112 .name = "ssc0_clk",
113 .pmc_mask = 1 << AT91RM9200_ID_SSC0,
114 .type = CLK_TYPE_PERIPHERAL,
115};
116static struct clk ssc1_clk = {
117 .name = "ssc1_clk",
118 .pmc_mask = 1 << AT91RM9200_ID_SSC1,
119 .type = CLK_TYPE_PERIPHERAL,
120};
121static struct clk ssc2_clk = {
122 .name = "ssc2_clk",
123 .pmc_mask = 1 << AT91RM9200_ID_SSC2,
124 .type = CLK_TYPE_PERIPHERAL,
125};
126static struct clk tc0_clk = {
127 .name = "tc0_clk",
128 .pmc_mask = 1 << AT91RM9200_ID_TC0,
129 .type = CLK_TYPE_PERIPHERAL,
130};
131static struct clk tc1_clk = {
132 .name = "tc1_clk",
133 .pmc_mask = 1 << AT91RM9200_ID_TC1,
134 .type = CLK_TYPE_PERIPHERAL,
135};
136static struct clk tc2_clk = {
137 .name = "tc2_clk",
138 .pmc_mask = 1 << AT91RM9200_ID_TC2,
139 .type = CLK_TYPE_PERIPHERAL,
140};
141static struct clk tc3_clk = {
142 .name = "tc3_clk",
143 .pmc_mask = 1 << AT91RM9200_ID_TC3,
144 .type = CLK_TYPE_PERIPHERAL,
145};
146static struct clk tc4_clk = {
147 .name = "tc4_clk",
148 .pmc_mask = 1 << AT91RM9200_ID_TC4,
149 .type = CLK_TYPE_PERIPHERAL,
150};
151static struct clk tc5_clk = {
152 .name = "tc5_clk",
153 .pmc_mask = 1 << AT91RM9200_ID_TC5,
154 .type = CLK_TYPE_PERIPHERAL,
155};
156
157static struct clk *periph_clocks[] __initdata = {
158 &pioA_clk,
159 &pioB_clk,
160 &pioC_clk,
161 &pioD_clk,
162 &usart0_clk,
163 &usart1_clk,
164 &usart2_clk,
165 &usart3_clk,
166 &mmc_clk,
167 &udc_clk,
168 &twi_clk,
169 &spi_clk,
170 &ssc0_clk,
171 &ssc1_clk,
172 &ssc2_clk,
173 &tc0_clk,
174 &tc1_clk,
175 &tc2_clk,
176 &tc3_clk,
177 &tc4_clk,
178 &tc5_clk,
179 &ohci_clk,
180 &ether_clk,
181 // irq0 .. irq6
182};
183
184static struct clk_lookup periph_clocks_lookups[] = {
185 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
186 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
187 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
188 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
189 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
190 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
191 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
192 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
193 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk),
194 CLKDEV_CON_DEV_ID("pclk", "fffd0000.ssc", &ssc0_clk),
195 CLKDEV_CON_DEV_ID("pclk", "fffd4000.ssc", &ssc1_clk),
196 CLKDEV_CON_DEV_ID("pclk", "fffd8000.ssc", &ssc2_clk),
197 CLKDEV_CON_DEV_ID(NULL, "i2c-at91rm9200.0", &twi_clk),
198 /* fake hclk clock */
199 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
200 CLKDEV_CON_ID("pioA", &pioA_clk),
201 CLKDEV_CON_ID("pioB", &pioB_clk),
202 CLKDEV_CON_ID("pioC", &pioC_clk),
203 CLKDEV_CON_ID("pioD", &pioD_clk),
204 /* usart lookup table for DT entries */
205 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
206 CLKDEV_CON_DEV_ID("usart", "fffc0000.serial", &usart0_clk),
207 CLKDEV_CON_DEV_ID("usart", "fffc4000.serial", &usart1_clk),
208 CLKDEV_CON_DEV_ID("usart", "fffc8000.serial", &usart2_clk),
209 CLKDEV_CON_DEV_ID("usart", "fffcc000.serial", &usart3_clk),
210 /* tc lookup table for DT entries */
211 CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
212 CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
213 CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
214 CLKDEV_CON_DEV_ID("t0_clk", "fffa4000.timer", &tc3_clk),
215 CLKDEV_CON_DEV_ID("t1_clk", "fffa4000.timer", &tc4_clk),
216 CLKDEV_CON_DEV_ID("t2_clk", "fffa4000.timer", &tc5_clk),
217 CLKDEV_CON_DEV_ID("mci_clk", "fffb4000.mmc", &mmc_clk),
218 CLKDEV_CON_DEV_ID("emac_clk", "fffbc000.ethernet", &ether_clk),
219 CLKDEV_CON_DEV_ID(NULL, "fffb8000.i2c", &twi_clk),
220 CLKDEV_CON_DEV_ID("hclk", "300000.ohci", &ohci_clk),
221 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
222 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
223 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
224 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk),
225};
226
227static struct clk_lookup usart_clocks_lookups[] = {
228 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
229 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
230 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
231 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
232 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
233};
234
235/*
236 * The four programmable clocks.
237 * You must configure pin multiplexing to bring these signals out.
238 */
239static struct clk pck0 = {
240 .name = "pck0",
241 .pmc_mask = AT91_PMC_PCK0,
242 .type = CLK_TYPE_PROGRAMMABLE,
243 .id = 0,
244};
245static struct clk pck1 = {
246 .name = "pck1",
247 .pmc_mask = AT91_PMC_PCK1,
248 .type = CLK_TYPE_PROGRAMMABLE,
249 .id = 1,
250};
251static struct clk pck2 = {
252 .name = "pck2",
253 .pmc_mask = AT91_PMC_PCK2,
254 .type = CLK_TYPE_PROGRAMMABLE,
255 .id = 2,
256};
257static struct clk pck3 = {
258 .name = "pck3",
259 .pmc_mask = AT91_PMC_PCK3,
260 .type = CLK_TYPE_PROGRAMMABLE,
261 .id = 3,
262};
263
264static void __init at91rm9200_register_clocks(void)
265{
266 int i;
267
268 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
269 clk_register(periph_clocks[i]);
270
271 clkdev_add_table(periph_clocks_lookups,
272 ARRAY_SIZE(periph_clocks_lookups));
273 clkdev_add_table(usart_clocks_lookups,
274 ARRAY_SIZE(usart_clocks_lookups));
275
276 clk_register(&pck0);
277 clk_register(&pck1);
278 clk_register(&pck2);
279 clk_register(&pck3);
280}
281#else
282#define at91rm9200_register_clocks NULL
283#endif
284
285/* --------------------------------------------------------------------
286 * GPIO
287 * -------------------------------------------------------------------- */
288
289static struct at91_gpio_bank at91rm9200_gpio[] __initdata = {
290 {
291 .id = AT91RM9200_ID_PIOA,
292 .regbase = AT91RM9200_BASE_PIOA,
293 }, {
294 .id = AT91RM9200_ID_PIOB,
295 .regbase = AT91RM9200_BASE_PIOB,
296 }, {
297 .id = AT91RM9200_ID_PIOC,
298 .regbase = AT91RM9200_BASE_PIOC,
299 }, {
300 .id = AT91RM9200_ID_PIOD,
301 .regbase = AT91RM9200_BASE_PIOD,
302 }
303};
304 23
305static void at91rm9200_idle(void) 24static void at91rm9200_idle(void)
306{ 25{
@@ -329,74 +48,14 @@ static void __init at91rm9200_map_io(void)
329 at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE); 48 at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE);
330} 49}
331 50
332static void __init at91rm9200_ioremap_registers(void)
333{
334 at91rm9200_ioremap_st(AT91RM9200_BASE_ST);
335 at91_ioremap_ramc(0, AT91RM9200_BASE_MC, 256);
336 at91_pm_set_standby(at91rm9200_standby);
337}
338
339static void __init at91rm9200_initialize(void) 51static void __init at91rm9200_initialize(void)
340{ 52{
341 arm_pm_idle = at91rm9200_idle; 53 arm_pm_idle = at91rm9200_idle;
342 arm_pm_restart = at91rm9200_restart; 54 arm_pm_restart = at91rm9200_restart;
343
344 /* Initialize GPIO subsystem */
345 at91_gpio_init(at91rm9200_gpio,
346 cpu_is_at91rm9200_bga() ? AT91RM9200_BGA : AT91RM9200_PQFP);
347} 55}
348 56
349 57
350/* --------------------------------------------------------------------
351 * Interrupt initialization
352 * -------------------------------------------------------------------- */
353
354/*
355 * The default interrupt priority levels (0 = lowest, 7 = highest).
356 */
357static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
358 7, /* Advanced Interrupt Controller (FIQ) */
359 7, /* System Peripherals */
360 1, /* Parallel IO Controller A */
361 1, /* Parallel IO Controller B */
362 1, /* Parallel IO Controller C */
363 1, /* Parallel IO Controller D */
364 5, /* USART 0 */
365 5, /* USART 1 */
366 5, /* USART 2 */
367 5, /* USART 3 */
368 0, /* Multimedia Card Interface */
369 2, /* USB Device Port */
370 6, /* Two-Wire Interface */
371 5, /* Serial Peripheral Interface */
372 4, /* Serial Synchronous Controller 0 */
373 4, /* Serial Synchronous Controller 1 */
374 4, /* Serial Synchronous Controller 2 */
375 0, /* Timer Counter 0 */
376 0, /* Timer Counter 1 */
377 0, /* Timer Counter 2 */
378 0, /* Timer Counter 3 */
379 0, /* Timer Counter 4 */
380 0, /* Timer Counter 5 */
381 2, /* USB Host port */
382 3, /* Ethernet MAC */
383 0, /* Advanced Interrupt Controller (IRQ0) */
384 0, /* Advanced Interrupt Controller (IRQ1) */
385 0, /* Advanced Interrupt Controller (IRQ2) */
386 0, /* Advanced Interrupt Controller (IRQ3) */
387 0, /* Advanced Interrupt Controller (IRQ4) */
388 0, /* Advanced Interrupt Controller (IRQ5) */
389 0 /* Advanced Interrupt Controller (IRQ6) */
390};
391
392AT91_SOC_START(at91rm9200) 58AT91_SOC_START(at91rm9200)
393 .map_io = at91rm9200_map_io, 59 .map_io = at91rm9200_map_io,
394 .default_irq_priority = at91rm9200_default_irq_priority,
395 .extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
396 | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
397 | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
398 | (1 << AT91RM9200_ID_IRQ6),
399 .ioremap_registers = at91rm9200_ioremap_registers,
400 .register_clocks = at91rm9200_register_clocks,
401 .init = at91rm9200_initialize, 60 .init = at91rm9200_initialize,
402AT91_SOC_END 61AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
deleted file mode 100644
index 74f1eaf97801..000000000000
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ /dev/null
@@ -1,1212 +0,0 @@
1/*
2 * arch/arm/mach-at91/at91rm9200_devices.c
3 *
4 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
5 * Copyright (C) 2005 David Brownell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13#include <asm/mach/arch.h>
14#include <asm/mach/map.h>
15
16#include <linux/dma-mapping.h>
17#include <linux/gpio.h>
18#include <linux/gpio/machine.h>
19#include <linux/platform_device.h>
20#include <linux/i2c-gpio.h>
21
22#include <mach/at91rm9200.h>
23#include <mach/at91rm9200_mc.h>
24#include <mach/at91_ramc.h>
25#include <mach/hardware.h>
26
27#include "board.h"
28#include "generic.h"
29#include "gpio.h"
30
31
32/* --------------------------------------------------------------------
33 * USB Host
34 * -------------------------------------------------------------------- */
35
36#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
37static u64 ohci_dmamask = DMA_BIT_MASK(32);
38static struct at91_usbh_data usbh_data;
39
40static struct resource usbh_resources[] = {
41 [0] = {
42 .start = AT91RM9200_UHP_BASE,
43 .end = AT91RM9200_UHP_BASE + SZ_1M - 1,
44 .flags = IORESOURCE_MEM,
45 },
46 [1] = {
47 .start = NR_IRQS_LEGACY + AT91RM9200_ID_UHP,
48 .end = NR_IRQS_LEGACY + AT91RM9200_ID_UHP,
49 .flags = IORESOURCE_IRQ,
50 },
51};
52
53static struct platform_device at91rm9200_usbh_device = {
54 .name = "at91_ohci",
55 .id = -1,
56 .dev = {
57 .dma_mask = &ohci_dmamask,
58 .coherent_dma_mask = DMA_BIT_MASK(32),
59 .platform_data = &usbh_data,
60 },
61 .resource = usbh_resources,
62 .num_resources = ARRAY_SIZE(usbh_resources),
63};
64
65void __init at91_add_device_usbh(struct at91_usbh_data *data)
66{
67 int i;
68
69 if (!data)
70 return;
71
72 /* Enable overcurrent notification */
73 for (i = 0; i < data->ports; i++) {
74 if (gpio_is_valid(data->overcurrent_pin[i]))
75 at91_set_gpio_input(data->overcurrent_pin[i], 1);
76 }
77
78 usbh_data = *data;
79 platform_device_register(&at91rm9200_usbh_device);
80}
81#else
82void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
83#endif
84
85
86/* --------------------------------------------------------------------
87 * USB Device (Gadget)
88 * -------------------------------------------------------------------- */
89
90#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
91static struct at91_udc_data udc_data;
92
93static struct resource udc_resources[] = {
94 [0] = {
95 .start = AT91RM9200_BASE_UDP,
96 .end = AT91RM9200_BASE_UDP + SZ_16K - 1,
97 .flags = IORESOURCE_MEM,
98 },
99 [1] = {
100 .start = NR_IRQS_LEGACY + AT91RM9200_ID_UDP,
101 .end = NR_IRQS_LEGACY + AT91RM9200_ID_UDP,
102 .flags = IORESOURCE_IRQ,
103 },
104};
105
106static struct platform_device at91rm9200_udc_device = {
107 .name = "at91_udc",
108 .id = -1,
109 .dev = {
110 .platform_data = &udc_data,
111 },
112 .resource = udc_resources,
113 .num_resources = ARRAY_SIZE(udc_resources),
114};
115
116void __init at91_add_device_udc(struct at91_udc_data *data)
117{
118 if (!data)
119 return;
120
121 if (gpio_is_valid(data->vbus_pin)) {
122 at91_set_gpio_input(data->vbus_pin, 0);
123 at91_set_deglitch(data->vbus_pin, 1);
124 }
125 if (gpio_is_valid(data->pullup_pin))
126 at91_set_gpio_output(data->pullup_pin, 0);
127
128 udc_data = *data;
129 platform_device_register(&at91rm9200_udc_device);
130}
131#else
132void __init at91_add_device_udc(struct at91_udc_data *data) {}
133#endif
134
135
136/* --------------------------------------------------------------------
137 * Ethernet
138 * -------------------------------------------------------------------- */
139
140#if defined(CONFIG_ARM_AT91_ETHER) || defined(CONFIG_ARM_AT91_ETHER_MODULE)
141static u64 eth_dmamask = DMA_BIT_MASK(32);
142static struct macb_platform_data eth_data;
143
144static struct resource eth_resources[] = {
145 [0] = {
146 .start = AT91RM9200_BASE_EMAC,
147 .end = AT91RM9200_BASE_EMAC + SZ_16K - 1,
148 .flags = IORESOURCE_MEM,
149 },
150 [1] = {
151 .start = NR_IRQS_LEGACY + AT91RM9200_ID_EMAC,
152 .end = NR_IRQS_LEGACY + AT91RM9200_ID_EMAC,
153 .flags = IORESOURCE_IRQ,
154 },
155};
156
157static struct platform_device at91rm9200_eth_device = {
158 .name = "at91_ether",
159 .id = -1,
160 .dev = {
161 .dma_mask = &eth_dmamask,
162 .coherent_dma_mask = DMA_BIT_MASK(32),
163 .platform_data = &eth_data,
164 },
165 .resource = eth_resources,
166 .num_resources = ARRAY_SIZE(eth_resources),
167};
168
169void __init at91_add_device_eth(struct macb_platform_data *data)
170{
171 if (!data)
172 return;
173
174 if (gpio_is_valid(data->phy_irq_pin)) {
175 at91_set_gpio_input(data->phy_irq_pin, 0);
176 at91_set_deglitch(data->phy_irq_pin, 1);
177 }
178
179 /* Pins used for MII and RMII */
180 at91_set_A_periph(AT91_PIN_PA16, 0); /* EMDIO */
181 at91_set_A_periph(AT91_PIN_PA15, 0); /* EMDC */
182 at91_set_A_periph(AT91_PIN_PA14, 0); /* ERXER */
183 at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
184 at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
185 at91_set_A_periph(AT91_PIN_PA11, 0); /* ECRS_ECRSDV */
186 at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX1 */
187 at91_set_A_periph(AT91_PIN_PA9, 0); /* ETX0 */
188 at91_set_A_periph(AT91_PIN_PA8, 0); /* ETXEN */
189 at91_set_A_periph(AT91_PIN_PA7, 0); /* ETXCK_EREFCK */
190
191 if (!data->is_rmii) {
192 at91_set_B_periph(AT91_PIN_PB19, 0); /* ERXCK */
193 at91_set_B_periph(AT91_PIN_PB18, 0); /* ECOL */
194 at91_set_B_periph(AT91_PIN_PB17, 0); /* ERXDV */
195 at91_set_B_periph(AT91_PIN_PB16, 0); /* ERX3 */
196 at91_set_B_periph(AT91_PIN_PB15, 0); /* ERX2 */
197 at91_set_B_periph(AT91_PIN_PB14, 0); /* ETXER */
198 at91_set_B_periph(AT91_PIN_PB13, 0); /* ETX3 */
199 at91_set_B_periph(AT91_PIN_PB12, 0); /* ETX2 */
200 }
201
202 eth_data = *data;
203 platform_device_register(&at91rm9200_eth_device);
204}
205#else
206void __init at91_add_device_eth(struct macb_platform_data *data) {}
207#endif
208
209
210/* --------------------------------------------------------------------
211 * Compact Flash / PCMCIA
212 * -------------------------------------------------------------------- */
213
214#if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
215static struct at91_cf_data cf_data;
216
217#define CF_BASE AT91_CHIPSELECT_4
218
219static struct resource cf_resources[] = {
220 [0] = {
221 .start = CF_BASE,
222 /* ties up CS4, CS5 and CS6 */
223 .end = CF_BASE + (0x30000000 - 1),
224 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
225 },
226};
227
228static struct platform_device at91rm9200_cf_device = {
229 .name = "at91_cf",
230 .id = -1,
231 .dev = {
232 .platform_data = &cf_data,
233 },
234 .resource = cf_resources,
235 .num_resources = ARRAY_SIZE(cf_resources),
236};
237
238void __init at91_add_device_cf(struct at91_cf_data *data)
239{
240 unsigned int csa;
241
242 if (!data)
243 return;
244
245 data->chipselect = 4; /* can only use EBI ChipSelect 4 */
246
247 /* CF takes over CS4, CS5, CS6 */
248 csa = at91_ramc_read(0, AT91_EBI_CSA);
249 at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
250
251 /*
252 * Static memory controller timing adjustments.
253 * REVISIT: these timings are in terms of MCK cycles, so
254 * when MCK changes (cpufreq etc) so must these values...
255 */
256 at91_ramc_write(0, AT91_SMC_CSR(4),
257 AT91_SMC_ACSS_STD
258 | AT91_SMC_DBW_16
259 | AT91_SMC_BAT
260 | AT91_SMC_WSEN
261 | AT91_SMC_NWS_(32) /* wait states */
262 | AT91_SMC_RWSETUP_(6) /* setup time */
263 | AT91_SMC_RWHOLD_(4) /* hold time */
264 );
265
266 /* input/irq */
267 if (gpio_is_valid(data->irq_pin)) {
268 at91_set_gpio_input(data->irq_pin, 1);
269 at91_set_deglitch(data->irq_pin, 1);
270 }
271 at91_set_gpio_input(data->det_pin, 1);
272 at91_set_deglitch(data->det_pin, 1);
273
274 /* outputs, initially off */
275 if (gpio_is_valid(data->vcc_pin))
276 at91_set_gpio_output(data->vcc_pin, 0);
277 at91_set_gpio_output(data->rst_pin, 0);
278
279 /* force poweron defaults for these pins ... */
280 at91_set_A_periph(AT91_PIN_PC9, 0); /* A25/CFRNW */
281 at91_set_A_periph(AT91_PIN_PC10, 0); /* NCS4/CFCS */
282 at91_set_A_periph(AT91_PIN_PC11, 0); /* NCS5/CFCE1 */
283 at91_set_A_periph(AT91_PIN_PC12, 0); /* NCS6/CFCE2 */
284
285 /* nWAIT is _not_ a default setting */
286 at91_set_A_periph(AT91_PIN_PC6, 1); /* nWAIT */
287
288 cf_data = *data;
289 platform_device_register(&at91rm9200_cf_device);
290}
291#else
292void __init at91_add_device_cf(struct at91_cf_data *data) {}
293#endif
294
295
296/* --------------------------------------------------------------------
297 * MMC / SD
298 * -------------------------------------------------------------------- */
299
300#if IS_ENABLED(CONFIG_MMC_ATMELMCI)
301static u64 mmc_dmamask = DMA_BIT_MASK(32);
302static struct mci_platform_data mmc_data;
303
304static struct resource mmc_resources[] = {
305 [0] = {
306 .start = AT91RM9200_BASE_MCI,
307 .end = AT91RM9200_BASE_MCI + SZ_16K - 1,
308 .flags = IORESOURCE_MEM,
309 },
310 [1] = {
311 .start = NR_IRQS_LEGACY + AT91RM9200_ID_MCI,
312 .end = NR_IRQS_LEGACY + AT91RM9200_ID_MCI,
313 .flags = IORESOURCE_IRQ,
314 },
315};
316
317static struct platform_device at91rm9200_mmc_device = {
318 .name = "atmel_mci",
319 .id = -1,
320 .dev = {
321 .dma_mask = &mmc_dmamask,
322 .coherent_dma_mask = DMA_BIT_MASK(32),
323 .platform_data = &mmc_data,
324 },
325 .resource = mmc_resources,
326 .num_resources = ARRAY_SIZE(mmc_resources),
327};
328
329void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
330{
331 unsigned int i;
332 unsigned int slot_count = 0;
333
334 if (!data)
335 return;
336
337 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
338
339 if (!data->slot[i].bus_width)
340 continue;
341
342 /* input/irq */
343 if (gpio_is_valid(data->slot[i].detect_pin)) {
344 at91_set_gpio_input(data->slot[i].detect_pin, 1);
345 at91_set_deglitch(data->slot[i].detect_pin, 1);
346 }
347 if (gpio_is_valid(data->slot[i].wp_pin))
348 at91_set_gpio_input(data->slot[i].wp_pin, 1);
349
350 switch (i) {
351 case 0: /* slot A */
352 /* CMD */
353 at91_set_A_periph(AT91_PIN_PA28, 1);
354 /* DAT0, maybe DAT1..DAT3 */
355 at91_set_A_periph(AT91_PIN_PA29, 1);
356 if (data->slot[i].bus_width == 4) {
357 at91_set_B_periph(AT91_PIN_PB3, 1);
358 at91_set_B_periph(AT91_PIN_PB4, 1);
359 at91_set_B_periph(AT91_PIN_PB5, 1);
360 }
361 slot_count++;
362 break;
363 case 1: /* slot B */
364 /* CMD */
365 at91_set_B_periph(AT91_PIN_PA8, 1);
366 /* DAT0, maybe DAT1..DAT3 */
367 at91_set_B_periph(AT91_PIN_PA9, 1);
368 if (data->slot[i].bus_width == 4) {
369 at91_set_B_periph(AT91_PIN_PA10, 1);
370 at91_set_B_periph(AT91_PIN_PA11, 1);
371 at91_set_B_periph(AT91_PIN_PA12, 1);
372 }
373 slot_count++;
374 break;
375 default:
376 printk(KERN_ERR
377 "AT91: SD/MMC slot %d not available\n", i);
378 break;
379 }
380 if (slot_count) {
381 /* CLK */
382 at91_set_A_periph(AT91_PIN_PA27, 0);
383
384 mmc_data = *data;
385 platform_device_register(&at91rm9200_mmc_device);
386 }
387 }
388
389}
390#else
391void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
392#endif
393
394
395/* --------------------------------------------------------------------
396 * NAND / SmartMedia
397 * -------------------------------------------------------------------- */
398
399#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
400static struct atmel_nand_data nand_data;
401
402#define NAND_BASE AT91_CHIPSELECT_3
403
404static struct resource nand_resources[] = {
405 {
406 .start = NAND_BASE,
407 .end = NAND_BASE + SZ_256M - 1,
408 .flags = IORESOURCE_MEM,
409 }
410};
411
412static struct platform_device at91rm9200_nand_device = {
413 .name = "atmel_nand",
414 .id = -1,
415 .dev = {
416 .platform_data = &nand_data,
417 },
418 .resource = nand_resources,
419 .num_resources = ARRAY_SIZE(nand_resources),
420};
421
422void __init at91_add_device_nand(struct atmel_nand_data *data)
423{
424 unsigned int csa;
425
426 if (!data)
427 return;
428
429 /* enable the address range of CS3 */
430 csa = at91_ramc_read(0, AT91_EBI_CSA);
431 at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
432
433 /* set the bus interface characteristics */
434 at91_ramc_write(0, AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
435 | AT91_SMC_NWS_(5)
436 | AT91_SMC_TDF_(1)
437 | AT91_SMC_RWSETUP_(0) /* tDS Data Set up Time 30 - ns */
438 | AT91_SMC_RWHOLD_(1) /* tDH Data Hold Time 20 - ns */
439 );
440
441 /* enable pin */
442 if (gpio_is_valid(data->enable_pin))
443 at91_set_gpio_output(data->enable_pin, 1);
444
445 /* ready/busy pin */
446 if (gpio_is_valid(data->rdy_pin))
447 at91_set_gpio_input(data->rdy_pin, 1);
448
449 /* card detect pin */
450 if (gpio_is_valid(data->det_pin))
451 at91_set_gpio_input(data->det_pin, 1);
452
453 at91_set_A_periph(AT91_PIN_PC1, 0); /* SMOE */
454 at91_set_A_periph(AT91_PIN_PC3, 0); /* SMWE */
455
456 nand_data = *data;
457 platform_device_register(&at91rm9200_nand_device);
458}
459#else
460void __init at91_add_device_nand(struct atmel_nand_data *data) {}
461#endif
462
463
464/* --------------------------------------------------------------------
465 * TWI (i2c)
466 * -------------------------------------------------------------------- */
467
468/*
469 * Prefer the GPIO code since the TWI controller isn't robust
470 * (gets overruns and underruns under load) and can only issue
471 * repeated STARTs in one scenario (the driver doesn't yet handle them).
472 */
473#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
474
475static struct i2c_gpio_platform_data pdata = {
476 .sda_pin = AT91_PIN_PA25,
477 .sda_is_open_drain = 1,
478 .scl_pin = AT91_PIN_PA26,
479 .scl_is_open_drain = 1,
480 .udelay = 2, /* ~100 kHz */
481};
482
483static struct platform_device at91rm9200_twi_device = {
484 .name = "i2c-gpio",
485 .id = 0,
486 .dev.platform_data = &pdata,
487};
488
489void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
490{
491 at91_set_GPIO_periph(AT91_PIN_PA25, 1); /* TWD (SDA) */
492 at91_set_multi_drive(AT91_PIN_PA25, 1);
493
494 at91_set_GPIO_periph(AT91_PIN_PA26, 1); /* TWCK (SCL) */
495 at91_set_multi_drive(AT91_PIN_PA26, 1);
496
497 i2c_register_board_info(0, devices, nr_devices);
498 platform_device_register(&at91rm9200_twi_device);
499}
500
501#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
502
503static struct resource twi_resources[] = {
504 [0] = {
505 .start = AT91RM9200_BASE_TWI,
506 .end = AT91RM9200_BASE_TWI + SZ_16K - 1,
507 .flags = IORESOURCE_MEM,
508 },
509 [1] = {
510 .start = NR_IRQS_LEGACY + AT91RM9200_ID_TWI,
511 .end = NR_IRQS_LEGACY + AT91RM9200_ID_TWI,
512 .flags = IORESOURCE_IRQ,
513 },
514};
515
516static struct platform_device at91rm9200_twi_device = {
517 .name = "i2c-at91rm9200",
518 .id = 0,
519 .resource = twi_resources,
520 .num_resources = ARRAY_SIZE(twi_resources),
521};
522
523void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
524{
525 /* pins used for TWI interface */
526 at91_set_A_periph(AT91_PIN_PA25, 0); /* TWD */
527 at91_set_multi_drive(AT91_PIN_PA25, 1);
528
529 at91_set_A_periph(AT91_PIN_PA26, 0); /* TWCK */
530 at91_set_multi_drive(AT91_PIN_PA26, 1);
531
532 i2c_register_board_info(0, devices, nr_devices);
533 platform_device_register(&at91rm9200_twi_device);
534}
535#else
536void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
537#endif
538
539
540/* --------------------------------------------------------------------
541 * SPI
542 * -------------------------------------------------------------------- */
543
544#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
545static u64 spi_dmamask = DMA_BIT_MASK(32);
546
547static struct resource spi_resources[] = {
548 [0] = {
549 .start = AT91RM9200_BASE_SPI,
550 .end = AT91RM9200_BASE_SPI + SZ_16K - 1,
551 .flags = IORESOURCE_MEM,
552 },
553 [1] = {
554 .start = NR_IRQS_LEGACY + AT91RM9200_ID_SPI,
555 .end = NR_IRQS_LEGACY + AT91RM9200_ID_SPI,
556 .flags = IORESOURCE_IRQ,
557 },
558};
559
560static struct platform_device at91rm9200_spi_device = {
561 .name = "atmel_spi",
562 .id = 0,
563 .dev = {
564 .dma_mask = &spi_dmamask,
565 .coherent_dma_mask = DMA_BIT_MASK(32),
566 },
567 .resource = spi_resources,
568 .num_resources = ARRAY_SIZE(spi_resources),
569};
570
571static const unsigned spi_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
572
573void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
574{
575 int i;
576 unsigned long cs_pin;
577
578 at91_set_A_periph(AT91_PIN_PA0, 0); /* MISO */
579 at91_set_A_periph(AT91_PIN_PA1, 0); /* MOSI */
580 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPCK */
581
582 /* Enable SPI chip-selects */
583 for (i = 0; i < nr_devices; i++) {
584 if (devices[i].controller_data)
585 cs_pin = (unsigned long) devices[i].controller_data;
586 else
587 cs_pin = spi_standard_cs[devices[i].chip_select];
588
589 if (devices[i].chip_select == 0) /* for CS0 errata */
590 at91_set_A_periph(cs_pin, 0);
591 else
592 at91_set_gpio_output(cs_pin, 1);
593
594
595 /* pass chip-select pin to driver */
596 devices[i].controller_data = (void *) cs_pin;
597 }
598
599 spi_register_board_info(devices, nr_devices);
600 platform_device_register(&at91rm9200_spi_device);
601}
602#else
603void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
604#endif
605
606
607/* --------------------------------------------------------------------
608 * Timer/Counter blocks
609 * -------------------------------------------------------------------- */
610
611#ifdef CONFIG_ATMEL_TCLIB
612
613static struct resource tcb0_resources[] = {
614 [0] = {
615 .start = AT91RM9200_BASE_TCB0,
616 .end = AT91RM9200_BASE_TCB0 + SZ_16K - 1,
617 .flags = IORESOURCE_MEM,
618 },
619 [1] = {
620 .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC0,
621 .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC0,
622 .flags = IORESOURCE_IRQ,
623 },
624 [2] = {
625 .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC1,
626 .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC1,
627 .flags = IORESOURCE_IRQ,
628 },
629 [3] = {
630 .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC2,
631 .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC2,
632 .flags = IORESOURCE_IRQ,
633 },
634};
635
636static struct platform_device at91rm9200_tcb0_device = {
637 .name = "atmel_tcb",
638 .id = 0,
639 .resource = tcb0_resources,
640 .num_resources = ARRAY_SIZE(tcb0_resources),
641};
642
643static struct resource tcb1_resources[] = {
644 [0] = {
645 .start = AT91RM9200_BASE_TCB1,
646 .end = AT91RM9200_BASE_TCB1 + SZ_16K - 1,
647 .flags = IORESOURCE_MEM,
648 },
649 [1] = {
650 .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC3,
651 .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC3,
652 .flags = IORESOURCE_IRQ,
653 },
654 [2] = {
655 .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC4,
656 .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC4,
657 .flags = IORESOURCE_IRQ,
658 },
659 [3] = {
660 .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC5,
661 .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC5,
662 .flags = IORESOURCE_IRQ,
663 },
664};
665
666static struct platform_device at91rm9200_tcb1_device = {
667 .name = "atmel_tcb",
668 .id = 1,
669 .resource = tcb1_resources,
670 .num_resources = ARRAY_SIZE(tcb1_resources),
671};
672
673static void __init at91_add_device_tc(void)
674{
675 platform_device_register(&at91rm9200_tcb0_device);
676 platform_device_register(&at91rm9200_tcb1_device);
677}
678#else
679static void __init at91_add_device_tc(void) { }
680#endif
681
682
683/* --------------------------------------------------------------------
684 * RTC
685 * -------------------------------------------------------------------- */
686
687#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
688static struct resource rtc_resources[] = {
689 [0] = {
690 .start = AT91RM9200_BASE_RTC,
691 .end = AT91RM9200_BASE_RTC + SZ_256 - 1,
692 .flags = IORESOURCE_MEM,
693 },
694 [1] = {
695 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
696 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
697 .flags = IORESOURCE_IRQ,
698 },
699};
700
701static struct platform_device at91rm9200_rtc_device = {
702 .name = "at91_rtc",
703 .id = -1,
704 .resource = rtc_resources,
705 .num_resources = ARRAY_SIZE(rtc_resources),
706};
707
708static void __init at91_add_device_rtc(void)
709{
710 platform_device_register(&at91rm9200_rtc_device);
711}
712#else
713static void __init at91_add_device_rtc(void) {}
714#endif
715
716
717/* --------------------------------------------------------------------
718 * Watchdog
719 * -------------------------------------------------------------------- */
720
721#if defined(CONFIG_AT91RM9200_WATCHDOG) || defined(CONFIG_AT91RM9200_WATCHDOG_MODULE)
722static struct platform_device at91rm9200_wdt_device = {
723 .name = "at91_wdt",
724 .id = -1,
725 .num_resources = 0,
726};
727
728static void __init at91_add_device_watchdog(void)
729{
730 platform_device_register(&at91rm9200_wdt_device);
731}
732#else
733static void __init at91_add_device_watchdog(void) {}
734#endif
735
736
737/* --------------------------------------------------------------------
738 * SSC -- Synchronous Serial Controller
739 * -------------------------------------------------------------------- */
740
741#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
742static u64 ssc0_dmamask = DMA_BIT_MASK(32);
743
744static struct resource ssc0_resources[] = {
745 [0] = {
746 .start = AT91RM9200_BASE_SSC0,
747 .end = AT91RM9200_BASE_SSC0 + SZ_16K - 1,
748 .flags = IORESOURCE_MEM,
749 },
750 [1] = {
751 .start = NR_IRQS_LEGACY + AT91RM9200_ID_SSC0,
752 .end = NR_IRQS_LEGACY + AT91RM9200_ID_SSC0,
753 .flags = IORESOURCE_IRQ,
754 },
755};
756
757static struct platform_device at91rm9200_ssc0_device = {
758 .name = "at91rm9200_ssc",
759 .id = 0,
760 .dev = {
761 .dma_mask = &ssc0_dmamask,
762 .coherent_dma_mask = DMA_BIT_MASK(32),
763 },
764 .resource = ssc0_resources,
765 .num_resources = ARRAY_SIZE(ssc0_resources),
766};
767
768static inline void configure_ssc0_pins(unsigned pins)
769{
770 if (pins & ATMEL_SSC_TF)
771 at91_set_A_periph(AT91_PIN_PB0, 1);
772 if (pins & ATMEL_SSC_TK)
773 at91_set_A_periph(AT91_PIN_PB1, 1);
774 if (pins & ATMEL_SSC_TD)
775 at91_set_A_periph(AT91_PIN_PB2, 1);
776 if (pins & ATMEL_SSC_RD)
777 at91_set_A_periph(AT91_PIN_PB3, 1);
778 if (pins & ATMEL_SSC_RK)
779 at91_set_A_periph(AT91_PIN_PB4, 1);
780 if (pins & ATMEL_SSC_RF)
781 at91_set_A_periph(AT91_PIN_PB5, 1);
782}
783
784static u64 ssc1_dmamask = DMA_BIT_MASK(32);
785
786static struct resource ssc1_resources[] = {
787 [0] = {
788 .start = AT91RM9200_BASE_SSC1,
789 .end = AT91RM9200_BASE_SSC1 + SZ_16K - 1,
790 .flags = IORESOURCE_MEM,
791 },
792 [1] = {
793 .start = NR_IRQS_LEGACY + AT91RM9200_ID_SSC1,
794 .end = NR_IRQS_LEGACY + AT91RM9200_ID_SSC1,
795 .flags = IORESOURCE_IRQ,
796 },
797};
798
799static struct platform_device at91rm9200_ssc1_device = {
800 .name = "at91rm9200_ssc",
801 .id = 1,
802 .dev = {
803 .dma_mask = &ssc1_dmamask,
804 .coherent_dma_mask = DMA_BIT_MASK(32),
805 },
806 .resource = ssc1_resources,
807 .num_resources = ARRAY_SIZE(ssc1_resources),
808};
809
810static inline void configure_ssc1_pins(unsigned pins)
811{
812 if (pins & ATMEL_SSC_TF)
813 at91_set_A_periph(AT91_PIN_PB6, 1);
814 if (pins & ATMEL_SSC_TK)
815 at91_set_A_periph(AT91_PIN_PB7, 1);
816 if (pins & ATMEL_SSC_TD)
817 at91_set_A_periph(AT91_PIN_PB8, 1);
818 if (pins & ATMEL_SSC_RD)
819 at91_set_A_periph(AT91_PIN_PB9, 1);
820 if (pins & ATMEL_SSC_RK)
821 at91_set_A_periph(AT91_PIN_PB10, 1);
822 if (pins & ATMEL_SSC_RF)
823 at91_set_A_periph(AT91_PIN_PB11, 1);
824}
825
826static u64 ssc2_dmamask = DMA_BIT_MASK(32);
827
828static struct resource ssc2_resources[] = {
829 [0] = {
830 .start = AT91RM9200_BASE_SSC2,
831 .end = AT91RM9200_BASE_SSC2 + SZ_16K - 1,
832 .flags = IORESOURCE_MEM,
833 },
834 [1] = {
835 .start = NR_IRQS_LEGACY + AT91RM9200_ID_SSC2,
836 .end = NR_IRQS_LEGACY + AT91RM9200_ID_SSC2,
837 .flags = IORESOURCE_IRQ,
838 },
839};
840
841static struct platform_device at91rm9200_ssc2_device = {
842 .name = "at91rm9200_ssc",
843 .id = 2,
844 .dev = {
845 .dma_mask = &ssc2_dmamask,
846 .coherent_dma_mask = DMA_BIT_MASK(32),
847 },
848 .resource = ssc2_resources,
849 .num_resources = ARRAY_SIZE(ssc2_resources),
850};
851
852static inline void configure_ssc2_pins(unsigned pins)
853{
854 if (pins & ATMEL_SSC_TF)
855 at91_set_A_periph(AT91_PIN_PB12, 1);
856 if (pins & ATMEL_SSC_TK)
857 at91_set_A_periph(AT91_PIN_PB13, 1);
858 if (pins & ATMEL_SSC_TD)
859 at91_set_A_periph(AT91_PIN_PB14, 1);
860 if (pins & ATMEL_SSC_RD)
861 at91_set_A_periph(AT91_PIN_PB15, 1);
862 if (pins & ATMEL_SSC_RK)
863 at91_set_A_periph(AT91_PIN_PB16, 1);
864 if (pins & ATMEL_SSC_RF)
865 at91_set_A_periph(AT91_PIN_PB17, 1);
866}
867
868/*
869 * SSC controllers are accessed through library code, instead of any
870 * kind of all-singing/all-dancing driver. For example one could be
871 * used by a particular I2S audio codec's driver, while another one
872 * on the same system might be used by a custom data capture driver.
873 */
874void __init at91_add_device_ssc(unsigned id, unsigned pins)
875{
876 struct platform_device *pdev;
877
878 /*
879 * NOTE: caller is responsible for passing information matching
880 * "pins" to whatever will be using each particular controller.
881 */
882 switch (id) {
883 case AT91RM9200_ID_SSC0:
884 pdev = &at91rm9200_ssc0_device;
885 configure_ssc0_pins(pins);
886 break;
887 case AT91RM9200_ID_SSC1:
888 pdev = &at91rm9200_ssc1_device;
889 configure_ssc1_pins(pins);
890 break;
891 case AT91RM9200_ID_SSC2:
892 pdev = &at91rm9200_ssc2_device;
893 configure_ssc2_pins(pins);
894 break;
895 default:
896 return;
897 }
898
899 platform_device_register(pdev);
900}
901
902#else
903void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
904#endif
905
906
907/* --------------------------------------------------------------------
908 * UART
909 * -------------------------------------------------------------------- */
910
911#if defined(CONFIG_SERIAL_ATMEL)
912static struct resource dbgu_resources[] = {
913 [0] = {
914 .start = AT91RM9200_BASE_DBGU,
915 .end = AT91RM9200_BASE_DBGU + SZ_512 - 1,
916 .flags = IORESOURCE_MEM,
917 },
918 [1] = {
919 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
920 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
921 .flags = IORESOURCE_IRQ,
922 },
923};
924
925static struct atmel_uart_data dbgu_data = {
926 .use_dma_tx = 0,
927 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
928};
929
930static u64 dbgu_dmamask = DMA_BIT_MASK(32);
931
932static struct platform_device at91rm9200_dbgu_device = {
933 .name = "atmel_usart",
934 .id = 0,
935 .dev = {
936 .dma_mask = &dbgu_dmamask,
937 .coherent_dma_mask = DMA_BIT_MASK(32),
938 .platform_data = &dbgu_data,
939 },
940 .resource = dbgu_resources,
941 .num_resources = ARRAY_SIZE(dbgu_resources),
942};
943
944static inline void configure_dbgu_pins(void)
945{
946 at91_set_A_periph(AT91_PIN_PA30, 0); /* DRXD */
947 at91_set_A_periph(AT91_PIN_PA31, 1); /* DTXD */
948}
949
950static struct resource uart0_resources[] = {
951 [0] = {
952 .start = AT91RM9200_BASE_US0,
953 .end = AT91RM9200_BASE_US0 + SZ_16K - 1,
954 .flags = IORESOURCE_MEM,
955 },
956 [1] = {
957 .start = NR_IRQS_LEGACY + AT91RM9200_ID_US0,
958 .end = NR_IRQS_LEGACY + AT91RM9200_ID_US0,
959 .flags = IORESOURCE_IRQ,
960 },
961};
962
963static struct atmel_uart_data uart0_data = {
964 .use_dma_tx = 1,
965 .use_dma_rx = 1,
966};
967
968static struct gpiod_lookup_table uart0_gpios_table = {
969 .dev_id = "atmel_usart",
970 .table = {
971 GPIO_LOOKUP("pioA", 21, "rts", GPIO_ACTIVE_LOW),
972 { },
973 },
974};
975
976static u64 uart0_dmamask = DMA_BIT_MASK(32);
977
978static struct platform_device at91rm9200_uart0_device = {
979 .name = "atmel_usart",
980 .id = 1,
981 .dev = {
982 .dma_mask = &uart0_dmamask,
983 .coherent_dma_mask = DMA_BIT_MASK(32),
984 .platform_data = &uart0_data,
985 },
986 .resource = uart0_resources,
987 .num_resources = ARRAY_SIZE(uart0_resources),
988};
989
990static inline void configure_usart0_pins(unsigned pins)
991{
992 at91_set_A_periph(AT91_PIN_PA17, 1); /* TXD0 */
993 at91_set_A_periph(AT91_PIN_PA18, 0); /* RXD0 */
994
995 if (pins & ATMEL_UART_CTS)
996 at91_set_A_periph(AT91_PIN_PA20, 0); /* CTS0 */
997
998 if (pins & ATMEL_UART_RTS) {
999 /*
1000 * AT91RM9200 Errata #39 - RTS0 is not internally connected to PA21.
1001 * We need to drive the pin manually. The serial driver will driver
1002 * this to high when initializing.
1003 */
1004 gpiod_add_lookup_table(&uart0_gpios_table);
1005 }
1006}
1007
1008static struct resource uart1_resources[] = {
1009 [0] = {
1010 .start = AT91RM9200_BASE_US1,
1011 .end = AT91RM9200_BASE_US1 + SZ_16K - 1,
1012 .flags = IORESOURCE_MEM,
1013 },
1014 [1] = {
1015 .start = NR_IRQS_LEGACY + AT91RM9200_ID_US1,
1016 .end = NR_IRQS_LEGACY + AT91RM9200_ID_US1,
1017 .flags = IORESOURCE_IRQ,
1018 },
1019};
1020
1021static struct atmel_uart_data uart1_data = {
1022 .use_dma_tx = 1,
1023 .use_dma_rx = 1,
1024};
1025
1026static u64 uart1_dmamask = DMA_BIT_MASK(32);
1027
1028static struct platform_device at91rm9200_uart1_device = {
1029 .name = "atmel_usart",
1030 .id = 2,
1031 .dev = {
1032 .dma_mask = &uart1_dmamask,
1033 .coherent_dma_mask = DMA_BIT_MASK(32),
1034 .platform_data = &uart1_data,
1035 },
1036 .resource = uart1_resources,
1037 .num_resources = ARRAY_SIZE(uart1_resources),
1038};
1039
1040static inline void configure_usart1_pins(unsigned pins)
1041{
1042 at91_set_A_periph(AT91_PIN_PB20, 1); /* TXD1 */
1043 at91_set_A_periph(AT91_PIN_PB21, 0); /* RXD1 */
1044
1045 if (pins & ATMEL_UART_RI)
1046 at91_set_A_periph(AT91_PIN_PB18, 0); /* RI1 */
1047 if (pins & ATMEL_UART_DTR)
1048 at91_set_A_periph(AT91_PIN_PB19, 0); /* DTR1 */
1049 if (pins & ATMEL_UART_DCD)
1050 at91_set_A_periph(AT91_PIN_PB23, 0); /* DCD1 */
1051 if (pins & ATMEL_UART_CTS)
1052 at91_set_A_periph(AT91_PIN_PB24, 0); /* CTS1 */
1053 if (pins & ATMEL_UART_DSR)
1054 at91_set_A_periph(AT91_PIN_PB25, 0); /* DSR1 */
1055 if (pins & ATMEL_UART_RTS)
1056 at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS1 */
1057}
1058
1059static struct resource uart2_resources[] = {
1060 [0] = {
1061 .start = AT91RM9200_BASE_US2,
1062 .end = AT91RM9200_BASE_US2 + SZ_16K - 1,
1063 .flags = IORESOURCE_MEM,
1064 },
1065 [1] = {
1066 .start = NR_IRQS_LEGACY + AT91RM9200_ID_US2,
1067 .end = NR_IRQS_LEGACY + AT91RM9200_ID_US2,
1068 .flags = IORESOURCE_IRQ,
1069 },
1070};
1071
1072static struct atmel_uart_data uart2_data = {
1073 .use_dma_tx = 1,
1074 .use_dma_rx = 1,
1075};
1076
1077static u64 uart2_dmamask = DMA_BIT_MASK(32);
1078
1079static struct platform_device at91rm9200_uart2_device = {
1080 .name = "atmel_usart",
1081 .id = 3,
1082 .dev = {
1083 .dma_mask = &uart2_dmamask,
1084 .coherent_dma_mask = DMA_BIT_MASK(32),
1085 .platform_data = &uart2_data,
1086 },
1087 .resource = uart2_resources,
1088 .num_resources = ARRAY_SIZE(uart2_resources),
1089};
1090
1091static inline void configure_usart2_pins(unsigned pins)
1092{
1093 at91_set_A_periph(AT91_PIN_PA22, 0); /* RXD2 */
1094 at91_set_A_periph(AT91_PIN_PA23, 1); /* TXD2 */
1095
1096 if (pins & ATMEL_UART_CTS)
1097 at91_set_B_periph(AT91_PIN_PA30, 0); /* CTS2 */
1098 if (pins & ATMEL_UART_RTS)
1099 at91_set_B_periph(AT91_PIN_PA31, 0); /* RTS2 */
1100}
1101
1102static struct resource uart3_resources[] = {
1103 [0] = {
1104 .start = AT91RM9200_BASE_US3,
1105 .end = AT91RM9200_BASE_US3 + SZ_16K - 1,
1106 .flags = IORESOURCE_MEM,
1107 },
1108 [1] = {
1109 .start = NR_IRQS_LEGACY + AT91RM9200_ID_US3,
1110 .end = NR_IRQS_LEGACY + AT91RM9200_ID_US3,
1111 .flags = IORESOURCE_IRQ,
1112 },
1113};
1114
1115static struct atmel_uart_data uart3_data = {
1116 .use_dma_tx = 1,
1117 .use_dma_rx = 1,
1118};
1119
1120static u64 uart3_dmamask = DMA_BIT_MASK(32);
1121
1122static struct platform_device at91rm9200_uart3_device = {
1123 .name = "atmel_usart",
1124 .id = 4,
1125 .dev = {
1126 .dma_mask = &uart3_dmamask,
1127 .coherent_dma_mask = DMA_BIT_MASK(32),
1128 .platform_data = &uart3_data,
1129 },
1130 .resource = uart3_resources,
1131 .num_resources = ARRAY_SIZE(uart3_resources),
1132};
1133
1134static inline void configure_usart3_pins(unsigned pins)
1135{
1136 at91_set_B_periph(AT91_PIN_PA5, 1); /* TXD3 */
1137 at91_set_B_periph(AT91_PIN_PA6, 0); /* RXD3 */
1138
1139 if (pins & ATMEL_UART_CTS)
1140 at91_set_B_periph(AT91_PIN_PB1, 0); /* CTS3 */
1141 if (pins & ATMEL_UART_RTS)
1142 at91_set_B_periph(AT91_PIN_PB0, 0); /* RTS3 */
1143}
1144
1145static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1146
1147void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1148{
1149 struct platform_device *pdev;
1150 struct atmel_uart_data *pdata;
1151
1152 switch (id) {
1153 case 0: /* DBGU */
1154 pdev = &at91rm9200_dbgu_device;
1155 configure_dbgu_pins();
1156 break;
1157 case AT91RM9200_ID_US0:
1158 pdev = &at91rm9200_uart0_device;
1159 configure_usart0_pins(pins);
1160 break;
1161 case AT91RM9200_ID_US1:
1162 pdev = &at91rm9200_uart1_device;
1163 configure_usart1_pins(pins);
1164 break;
1165 case AT91RM9200_ID_US2:
1166 pdev = &at91rm9200_uart2_device;
1167 configure_usart2_pins(pins);
1168 break;
1169 case AT91RM9200_ID_US3:
1170 pdev = &at91rm9200_uart3_device;
1171 configure_usart3_pins(pins);
1172 break;
1173 default:
1174 return;
1175 }
1176 pdata = pdev->dev.platform_data;
1177 pdata->num = portnr; /* update to mapped ID */
1178
1179 if (portnr < ATMEL_MAX_UART)
1180 at91_uarts[portnr] = pdev;
1181}
1182
1183void __init at91_add_device_serial(void)
1184{
1185 int i;
1186
1187 for (i = 0; i < ATMEL_MAX_UART; i++) {
1188 if (at91_uarts[i])
1189 platform_device_register(at91_uarts[i]);
1190 }
1191}
1192#else
1193void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1194void __init at91_add_device_serial(void) {}
1195#endif
1196
1197
1198/* -------------------------------------------------------------------- */
1199
1200/*
1201 * These devices are always present and don't need any board-specific
1202 * setup.
1203 */
1204static int __init at91_add_standard_devices(void)
1205{
1206 at91_add_device_rtc();
1207 at91_add_device_watchdog();
1208 at91_add_device_tc();
1209 return 0;
1210}
1211
1212arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index 7fd13aef9827..51761f8927b7 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -183,7 +183,6 @@ static struct clock_event_device clkevt = {
183void __iomem *at91_st_base; 183void __iomem *at91_st_base;
184EXPORT_SYMBOL_GPL(at91_st_base); 184EXPORT_SYMBOL_GPL(at91_st_base);
185 185
186#ifdef CONFIG_OF
187static struct of_device_id at91rm9200_st_timer_ids[] = { 186static struct of_device_id at91rm9200_st_timer_ids[] = {
188 { .compatible = "atmel,at91rm9200-st" }, 187 { .compatible = "atmel,at91rm9200-st" },
189 { /* sentinel */ } 188 { /* sentinel */ }
@@ -219,28 +218,6 @@ node_err:
219err: 218err:
220 return -EINVAL; 219 return -EINVAL;
221} 220}
222#else
223static int __init of_at91rm9200_st_init(void)
224{
225 return -EINVAL;
226}
227#endif
228
229void __init at91rm9200_ioremap_st(u32 addr)
230{
231#ifdef CONFIG_OF
232 struct device_node *np;
233
234 np = of_find_matching_node(NULL, at91rm9200_st_timer_ids);
235 if (np) {
236 of_node_put(np);
237 return;
238 }
239#endif
240 at91_st_base = ioremap(addr, 256);
241 if (!at91_st_base)
242 panic("Impossible to ioremap ST\n");
243}
244 221
245/* 222/*
246 * ST (system timer) module supports both clockevents and clocksource. 223 * ST (system timer) module supports both clockevents and clocksource.
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index aab1f969a7c3..78137c24d90b 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -10,305 +10,13 @@
10 * 10 *
11 */ 11 */
12 12
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/clk/at91_pmc.h>
16
17#include <asm/proc-fns.h>
18#include <asm/irq.h>
19#include <asm/mach/arch.h>
20#include <asm/mach/map.h>
21#include <asm/system_misc.h> 13#include <asm/system_misc.h>
22#include <mach/cpu.h> 14#include <mach/cpu.h>
23#include <mach/at91_dbgu.h> 15#include <mach/at91_dbgu.h>
24#include <mach/at91sam9260.h>
25#include <mach/hardware.h> 16#include <mach/hardware.h>
26 17
27#include "at91_aic.h"
28#include "soc.h" 18#include "soc.h"
29#include "generic.h" 19#include "generic.h"
30#include "sam9_smc.h"
31#include "pm.h"
32
33#if defined(CONFIG_OLD_CLK_AT91)
34#include "clock.h"
35/* --------------------------------------------------------------------
36 * Clocks
37 * -------------------------------------------------------------------- */
38
39/*
40 * The peripheral clocks.
41 */
42static struct clk pioA_clk = {
43 .name = "pioA_clk",
44 .pmc_mask = 1 << AT91SAM9260_ID_PIOA,
45 .type = CLK_TYPE_PERIPHERAL,
46};
47static struct clk pioB_clk = {
48 .name = "pioB_clk",
49 .pmc_mask = 1 << AT91SAM9260_ID_PIOB,
50 .type = CLK_TYPE_PERIPHERAL,
51};
52static struct clk pioC_clk = {
53 .name = "pioC_clk",
54 .pmc_mask = 1 << AT91SAM9260_ID_PIOC,
55 .type = CLK_TYPE_PERIPHERAL,
56};
57static struct clk adc_clk = {
58 .name = "adc_clk",
59 .pmc_mask = 1 << AT91SAM9260_ID_ADC,
60 .type = CLK_TYPE_PERIPHERAL,
61};
62
63static struct clk adc_op_clk = {
64 .name = "adc_op_clk",
65 .type = CLK_TYPE_PERIPHERAL,
66 .rate_hz = 5000000,
67};
68
69static struct clk usart0_clk = {
70 .name = "usart0_clk",
71 .pmc_mask = 1 << AT91SAM9260_ID_US0,
72 .type = CLK_TYPE_PERIPHERAL,
73};
74static struct clk usart1_clk = {
75 .name = "usart1_clk",
76 .pmc_mask = 1 << AT91SAM9260_ID_US1,
77 .type = CLK_TYPE_PERIPHERAL,
78};
79static struct clk usart2_clk = {
80 .name = "usart2_clk",
81 .pmc_mask = 1 << AT91SAM9260_ID_US2,
82 .type = CLK_TYPE_PERIPHERAL,
83};
84static struct clk mmc_clk = {
85 .name = "mci_clk",
86 .pmc_mask = 1 << AT91SAM9260_ID_MCI,
87 .type = CLK_TYPE_PERIPHERAL,
88};
89static struct clk udc_clk = {
90 .name = "udc_clk",
91 .pmc_mask = 1 << AT91SAM9260_ID_UDP,
92 .type = CLK_TYPE_PERIPHERAL,
93};
94static struct clk twi_clk = {
95 .name = "twi_clk",
96 .pmc_mask = 1 << AT91SAM9260_ID_TWI,
97 .type = CLK_TYPE_PERIPHERAL,
98};
99static struct clk spi0_clk = {
100 .name = "spi0_clk",
101 .pmc_mask = 1 << AT91SAM9260_ID_SPI0,
102 .type = CLK_TYPE_PERIPHERAL,
103};
104static struct clk spi1_clk = {
105 .name = "spi1_clk",
106 .pmc_mask = 1 << AT91SAM9260_ID_SPI1,
107 .type = CLK_TYPE_PERIPHERAL,
108};
109static struct clk ssc_clk = {
110 .name = "ssc_clk",
111 .pmc_mask = 1 << AT91SAM9260_ID_SSC,
112 .type = CLK_TYPE_PERIPHERAL,
113};
114static struct clk tc0_clk = {
115 .name = "tc0_clk",
116 .pmc_mask = 1 << AT91SAM9260_ID_TC0,
117 .type = CLK_TYPE_PERIPHERAL,
118};
119static struct clk tc1_clk = {
120 .name = "tc1_clk",
121 .pmc_mask = 1 << AT91SAM9260_ID_TC1,
122 .type = CLK_TYPE_PERIPHERAL,
123};
124static struct clk tc2_clk = {
125 .name = "tc2_clk",
126 .pmc_mask = 1 << AT91SAM9260_ID_TC2,
127 .type = CLK_TYPE_PERIPHERAL,
128};
129static struct clk ohci_clk = {
130 .name = "ohci_clk",
131 .pmc_mask = 1 << AT91SAM9260_ID_UHP,
132 .type = CLK_TYPE_PERIPHERAL,
133};
134static struct clk macb_clk = {
135 .name = "pclk",
136 .pmc_mask = 1 << AT91SAM9260_ID_EMAC,
137 .type = CLK_TYPE_PERIPHERAL,
138};
139static struct clk isi_clk = {
140 .name = "isi_clk",
141 .pmc_mask = 1 << AT91SAM9260_ID_ISI,
142 .type = CLK_TYPE_PERIPHERAL,
143};
144static struct clk usart3_clk = {
145 .name = "usart3_clk",
146 .pmc_mask = 1 << AT91SAM9260_ID_US3,
147 .type = CLK_TYPE_PERIPHERAL,
148};
149static struct clk usart4_clk = {
150 .name = "usart4_clk",
151 .pmc_mask = 1 << AT91SAM9260_ID_US4,
152 .type = CLK_TYPE_PERIPHERAL,
153};
154static struct clk usart5_clk = {
155 .name = "usart5_clk",
156 .pmc_mask = 1 << AT91SAM9260_ID_US5,
157 .type = CLK_TYPE_PERIPHERAL,
158};
159static struct clk tc3_clk = {
160 .name = "tc3_clk",
161 .pmc_mask = 1 << AT91SAM9260_ID_TC3,
162 .type = CLK_TYPE_PERIPHERAL,
163};
164static struct clk tc4_clk = {
165 .name = "tc4_clk",
166 .pmc_mask = 1 << AT91SAM9260_ID_TC4,
167 .type = CLK_TYPE_PERIPHERAL,
168};
169static struct clk tc5_clk = {
170 .name = "tc5_clk",
171 .pmc_mask = 1 << AT91SAM9260_ID_TC5,
172 .type = CLK_TYPE_PERIPHERAL,
173};
174
175static struct clk *periph_clocks[] __initdata = {
176 &pioA_clk,
177 &pioB_clk,
178 &pioC_clk,
179 &adc_clk,
180 &adc_op_clk,
181 &usart0_clk,
182 &usart1_clk,
183 &usart2_clk,
184 &mmc_clk,
185 &udc_clk,
186 &twi_clk,
187 &spi0_clk,
188 &spi1_clk,
189 &ssc_clk,
190 &tc0_clk,
191 &tc1_clk,
192 &tc2_clk,
193 &ohci_clk,
194 &macb_clk,
195 &isi_clk,
196 &usart3_clk,
197 &usart4_clk,
198 &usart5_clk,
199 &tc3_clk,
200 &tc4_clk,
201 &tc5_clk,
202 // irq0 .. irq2
203};
204
205static struct clk_lookup periph_clocks_lookups[] = {
206 /* One additional fake clock for macb_hclk */
207 CLKDEV_CON_ID("hclk", &macb_clk),
208 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
209 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
210 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
211 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
212 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
213 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
214 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
215 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
216 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc_clk),
217 CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc_clk),
218 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
219 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi_clk),
220 /* more usart lookup table for DT entries */
221 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
222 CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
223 CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk),
224 CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk),
225 CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
226 CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
227 CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
228 CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi_clk),
229 /* more tc lookup table for DT entries */
230 CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
231 CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
232 CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
233 CLKDEV_CON_DEV_ID("t0_clk", "fffdc000.timer", &tc3_clk),
234 CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
235 CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
236 CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk),
237 CLKDEV_CON_DEV_ID("mci_clk", "fffa8000.mmc", &mmc_clk),
238 CLKDEV_CON_DEV_ID("spi_clk", "fffc8000.spi", &spi0_clk),
239 CLKDEV_CON_DEV_ID("spi_clk", "fffcc000.spi", &spi1_clk),
240 /* fake hclk clock */
241 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
242 CLKDEV_CON_ID("pioA", &pioA_clk),
243 CLKDEV_CON_ID("pioB", &pioB_clk),
244 CLKDEV_CON_ID("pioC", &pioC_clk),
245 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
246 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
247 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
248};
249
250static struct clk_lookup usart_clocks_lookups[] = {
251 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
252 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
253 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
254 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
255 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
256 CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk),
257 CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk),
258};
259
260/*
261 * The two programmable clocks.
262 * You must configure pin multiplexing to bring these signals out.
263 */
264static struct clk pck0 = {
265 .name = "pck0",
266 .pmc_mask = AT91_PMC_PCK0,
267 .type = CLK_TYPE_PROGRAMMABLE,
268 .id = 0,
269};
270static struct clk pck1 = {
271 .name = "pck1",
272 .pmc_mask = AT91_PMC_PCK1,
273 .type = CLK_TYPE_PROGRAMMABLE,
274 .id = 1,
275};
276
277static void __init at91sam9260_register_clocks(void)
278{
279 int i;
280
281 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
282 clk_register(periph_clocks[i]);
283
284 clkdev_add_table(periph_clocks_lookups,
285 ARRAY_SIZE(periph_clocks_lookups));
286 clkdev_add_table(usart_clocks_lookups,
287 ARRAY_SIZE(usart_clocks_lookups));
288
289 clk_register(&pck0);
290 clk_register(&pck1);
291}
292#else
293#define at91sam9260_register_clocks NULL
294#endif
295
296/* --------------------------------------------------------------------
297 * GPIO
298 * -------------------------------------------------------------------- */
299
300static struct at91_gpio_bank at91sam9260_gpio[] __initdata = {
301 {
302 .id = AT91SAM9260_ID_PIOA,
303 .regbase = AT91SAM9260_BASE_PIOA,
304 }, {
305 .id = AT91SAM9260_ID_PIOB,
306 .regbase = AT91SAM9260_BASE_PIOB,
307 }, {
308 .id = AT91SAM9260_ID_PIOC,
309 .regbase = AT91SAM9260_BASE_PIOC,
310 }
311};
312 20
313/* -------------------------------------------------------------------- 21/* --------------------------------------------------------------------
314 * AT91SAM9260 processor initialization 22 * AT91SAM9260 processor initialization
@@ -340,119 +48,14 @@ static void __init at91sam9260_map_io(void)
340 at91_init_sram(0, AT91SAM9260_SRAM_BASE, AT91SAM9260_SRAM_SIZE); 48 at91_init_sram(0, AT91SAM9260_SRAM_BASE, AT91SAM9260_SRAM_SIZE);
341} 49}
342 50
343static void __init at91sam9260_ioremap_registers(void)
344{
345 at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512);
346 at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
347 at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
348 at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX);
349 at91_pm_set_standby(at91sam9_sdram_standby);
350}
351
352static void __init at91sam9260_initialize(void) 51static void __init at91sam9260_initialize(void)
353{ 52{
354 arm_pm_idle = at91sam9_idle; 53 arm_pm_idle = at91sam9_idle;
355 54
356 at91_sysirq_mask_rtt(AT91SAM9260_BASE_RTT); 55 at91_sysirq_mask_rtt(AT91SAM9260_BASE_RTT);
357
358 /* Register GPIO subsystem */
359 at91_gpio_init(at91sam9260_gpio, 3);
360}
361
362static struct resource rstc_resources[] = {
363 [0] = {
364 .start = AT91SAM9260_BASE_RSTC,
365 .end = AT91SAM9260_BASE_RSTC + SZ_16 - 1,
366 .flags = IORESOURCE_MEM,
367 },
368 [1] = {
369 .start = AT91SAM9260_BASE_SDRAMC,
370 .end = AT91SAM9260_BASE_SDRAMC + SZ_512 - 1,
371 .flags = IORESOURCE_MEM,
372 },
373};
374
375static struct platform_device rstc_device = {
376 .name = "at91-sam9260-reset",
377 .resource = rstc_resources,
378 .num_resources = ARRAY_SIZE(rstc_resources),
379};
380
381static struct resource shdwc_resources[] = {
382 [0] = {
383 .start = AT91SAM9260_BASE_SHDWC,
384 .end = AT91SAM9260_BASE_SHDWC + SZ_16 - 1,
385 .flags = IORESOURCE_MEM,
386 },
387};
388
389static struct platform_device shdwc_device = {
390 .name = "at91-poweroff",
391 .resource = shdwc_resources,
392 .num_resources = ARRAY_SIZE(shdwc_resources),
393};
394
395static void __init at91sam9260_register_devices(void)
396{
397 platform_device_register(&rstc_device);
398 platform_device_register(&shdwc_device);
399}
400
401/* --------------------------------------------------------------------
402 * Interrupt initialization
403 * -------------------------------------------------------------------- */
404
405/*
406 * The default interrupt priority levels (0 = lowest, 7 = highest).
407 */
408static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
409 7, /* Advanced Interrupt Controller */
410 7, /* System Peripherals */
411 1, /* Parallel IO Controller A */
412 1, /* Parallel IO Controller B */
413 1, /* Parallel IO Controller C */
414 0, /* Analog-to-Digital Converter */
415 5, /* USART 0 */
416 5, /* USART 1 */
417 5, /* USART 2 */
418 0, /* Multimedia Card Interface */
419 2, /* USB Device Port */
420 6, /* Two-Wire Interface */
421 5, /* Serial Peripheral Interface 0 */
422 5, /* Serial Peripheral Interface 1 */
423 5, /* Serial Synchronous Controller */
424 0,
425 0,
426 0, /* Timer Counter 0 */
427 0, /* Timer Counter 1 */
428 0, /* Timer Counter 2 */
429 2, /* USB Host port */
430 3, /* Ethernet */
431 0, /* Image Sensor Interface */
432 5, /* USART 3 */
433 5, /* USART 4 */
434 5, /* USART 5 */
435 0, /* Timer Counter 3 */
436 0, /* Timer Counter 4 */
437 0, /* Timer Counter 5 */
438 0, /* Advanced Interrupt Controller */
439 0, /* Advanced Interrupt Controller */
440 0, /* Advanced Interrupt Controller */
441};
442
443static void __init at91sam9260_init_time(void)
444{
445 at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS);
446} 56}
447 57
448AT91_SOC_START(at91sam9260) 58AT91_SOC_START(at91sam9260)
449 .map_io = at91sam9260_map_io, 59 .map_io = at91sam9260_map_io,
450 .default_irq_priority = at91sam9260_default_irq_priority,
451 .extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
452 | (1 << AT91SAM9260_ID_IRQ2),
453 .ioremap_registers = at91sam9260_ioremap_registers,
454 .register_clocks = at91sam9260_register_clocks,
455 .register_devices = at91sam9260_register_devices,
456 .init = at91sam9260_initialize, 60 .init = at91sam9260_initialize,
457 .init_time = at91sam9260_init_time,
458AT91_SOC_END 61AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
deleted file mode 100644
index ef88e0fe4e80..000000000000
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ /dev/null
@@ -1,1364 +0,0 @@
1/*
2 * arch/arm/mach-at91/at91sam9260_devices.c
3 *
4 * Copyright (C) 2006 Atmel
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12#include <asm/mach/arch.h>
13#include <asm/mach/map.h>
14
15#include <linux/dma-mapping.h>
16#include <linux/gpio.h>
17#include <linux/platform_device.h>
18#include <linux/i2c-gpio.h>
19
20#include <linux/platform_data/at91_adc.h>
21
22#include <mach/cpu.h>
23#include <mach/at91sam9260.h>
24#include <mach/at91sam9260_matrix.h>
25#include <mach/at91_matrix.h>
26#include <mach/at91sam9_smc.h>
27#include <mach/hardware.h>
28
29#include "board.h"
30#include "generic.h"
31#include "gpio.h"
32
33/* --------------------------------------------------------------------
34 * USB Host
35 * -------------------------------------------------------------------- */
36
37#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
38static u64 ohci_dmamask = DMA_BIT_MASK(32);
39static struct at91_usbh_data usbh_data;
40
41static struct resource usbh_resources[] = {
42 [0] = {
43 .start = AT91SAM9260_UHP_BASE,
44 .end = AT91SAM9260_UHP_BASE + SZ_1M - 1,
45 .flags = IORESOURCE_MEM,
46 },
47 [1] = {
48 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_UHP,
49 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_UHP,
50 .flags = IORESOURCE_IRQ,
51 },
52};
53
54static struct platform_device at91_usbh_device = {
55 .name = "at91_ohci",
56 .id = -1,
57 .dev = {
58 .dma_mask = &ohci_dmamask,
59 .coherent_dma_mask = DMA_BIT_MASK(32),
60 .platform_data = &usbh_data,
61 },
62 .resource = usbh_resources,
63 .num_resources = ARRAY_SIZE(usbh_resources),
64};
65
66void __init at91_add_device_usbh(struct at91_usbh_data *data)
67{
68 int i;
69
70 if (!data)
71 return;
72
73 /* Enable overcurrent notification */
74 for (i = 0; i < data->ports; i++) {
75 if (gpio_is_valid(data->overcurrent_pin[i]))
76 at91_set_gpio_input(data->overcurrent_pin[i], 1);
77 }
78
79 usbh_data = *data;
80 platform_device_register(&at91_usbh_device);
81}
82#else
83void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
84#endif
85
86
87/* --------------------------------------------------------------------
88 * USB Device (Gadget)
89 * -------------------------------------------------------------------- */
90
91#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
92static struct at91_udc_data udc_data;
93
94static struct resource udc_resources[] = {
95 [0] = {
96 .start = AT91SAM9260_BASE_UDP,
97 .end = AT91SAM9260_BASE_UDP + SZ_16K - 1,
98 .flags = IORESOURCE_MEM,
99 },
100 [1] = {
101 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_UDP,
102 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_UDP,
103 .flags = IORESOURCE_IRQ,
104 },
105};
106
107static struct platform_device at91_udc_device = {
108 .name = "at91_udc",
109 .id = -1,
110 .dev = {
111 .platform_data = &udc_data,
112 },
113 .resource = udc_resources,
114 .num_resources = ARRAY_SIZE(udc_resources),
115};
116
117void __init at91_add_device_udc(struct at91_udc_data *data)
118{
119 if (!data)
120 return;
121
122 if (gpio_is_valid(data->vbus_pin)) {
123 at91_set_gpio_input(data->vbus_pin, 0);
124 at91_set_deglitch(data->vbus_pin, 1);
125 }
126
127 /* Pullup pin is handled internally by USB device peripheral */
128
129 udc_data = *data;
130 platform_device_register(&at91_udc_device);
131}
132#else
133void __init at91_add_device_udc(struct at91_udc_data *data) {}
134#endif
135
136
137/* --------------------------------------------------------------------
138 * Ethernet
139 * -------------------------------------------------------------------- */
140
141#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
142static u64 eth_dmamask = DMA_BIT_MASK(32);
143static struct macb_platform_data eth_data;
144
145static struct resource eth_resources[] = {
146 [0] = {
147 .start = AT91SAM9260_BASE_EMAC,
148 .end = AT91SAM9260_BASE_EMAC + SZ_16K - 1,
149 .flags = IORESOURCE_MEM,
150 },
151 [1] = {
152 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_EMAC,
153 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_EMAC,
154 .flags = IORESOURCE_IRQ,
155 },
156};
157
158static struct platform_device at91sam9260_eth_device = {
159 .name = "macb",
160 .id = -1,
161 .dev = {
162 .dma_mask = &eth_dmamask,
163 .coherent_dma_mask = DMA_BIT_MASK(32),
164 .platform_data = &eth_data,
165 },
166 .resource = eth_resources,
167 .num_resources = ARRAY_SIZE(eth_resources),
168};
169
170void __init at91_add_device_eth(struct macb_platform_data *data)
171{
172 if (!data)
173 return;
174
175 if (gpio_is_valid(data->phy_irq_pin)) {
176 at91_set_gpio_input(data->phy_irq_pin, 0);
177 at91_set_deglitch(data->phy_irq_pin, 1);
178 }
179
180 /* Pins used for MII and RMII */
181 at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */
182 at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */
183 at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */
184 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */
185 at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */
186 at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */
187 at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */
188 at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */
189 at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */
190 at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */
191
192 if (!data->is_rmii) {
193 at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */
194 at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */
195 at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */
196 at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */
197 at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */
198 at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */
199 at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */
200 at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */
201 }
202
203 eth_data = *data;
204 platform_device_register(&at91sam9260_eth_device);
205}
206#else
207void __init at91_add_device_eth(struct macb_platform_data *data) {}
208#endif
209
210
211/* --------------------------------------------------------------------
212 * MMC / SD Slot for Atmel MCI Driver
213 * -------------------------------------------------------------------- */
214
215#if IS_ENABLED(CONFIG_MMC_ATMELMCI)
216static u64 mmc_dmamask = DMA_BIT_MASK(32);
217static struct mci_platform_data mmc_data;
218
219static struct resource mmc_resources[] = {
220 [0] = {
221 .start = AT91SAM9260_BASE_MCI,
222 .end = AT91SAM9260_BASE_MCI + SZ_16K - 1,
223 .flags = IORESOURCE_MEM,
224 },
225 [1] = {
226 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI,
227 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI,
228 .flags = IORESOURCE_IRQ,
229 },
230};
231
232static struct platform_device at91sam9260_mmc_device = {
233 .name = "atmel_mci",
234 .id = -1,
235 .dev = {
236 .dma_mask = &mmc_dmamask,
237 .coherent_dma_mask = DMA_BIT_MASK(32),
238 .platform_data = &mmc_data,
239 },
240 .resource = mmc_resources,
241 .num_resources = ARRAY_SIZE(mmc_resources),
242};
243
244void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
245{
246 unsigned int i;
247 unsigned int slot_count = 0;
248
249 if (!data)
250 return;
251
252 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
253 if (data->slot[i].bus_width) {
254 /* input/irq */
255 if (gpio_is_valid(data->slot[i].detect_pin)) {
256 at91_set_gpio_input(data->slot[i].detect_pin, 1);
257 at91_set_deglitch(data->slot[i].detect_pin, 1);
258 }
259 if (gpio_is_valid(data->slot[i].wp_pin))
260 at91_set_gpio_input(data->slot[i].wp_pin, 1);
261
262 switch (i) {
263 case 0:
264 /* CMD */
265 at91_set_A_periph(AT91_PIN_PA7, 1);
266 /* DAT0, maybe DAT1..DAT3 */
267 at91_set_A_periph(AT91_PIN_PA6, 1);
268 if (data->slot[i].bus_width == 4) {
269 at91_set_A_periph(AT91_PIN_PA9, 1);
270 at91_set_A_periph(AT91_PIN_PA10, 1);
271 at91_set_A_periph(AT91_PIN_PA11, 1);
272 }
273 slot_count++;
274 break;
275 case 1:
276 /* CMD */
277 at91_set_B_periph(AT91_PIN_PA1, 1);
278 /* DAT0, maybe DAT1..DAT3 */
279 at91_set_B_periph(AT91_PIN_PA0, 1);
280 if (data->slot[i].bus_width == 4) {
281 at91_set_B_periph(AT91_PIN_PA5, 1);
282 at91_set_B_periph(AT91_PIN_PA4, 1);
283 at91_set_B_periph(AT91_PIN_PA3, 1);
284 }
285 slot_count++;
286 break;
287 default:
288 printk(KERN_ERR
289 "AT91: SD/MMC slot %d not available\n", i);
290 break;
291 }
292 }
293 }
294
295 if (slot_count) {
296 /* CLK */
297 at91_set_A_periph(AT91_PIN_PA8, 0);
298
299 mmc_data = *data;
300 platform_device_register(&at91sam9260_mmc_device);
301 }
302}
303#else
304void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
305#endif
306
307
308/* --------------------------------------------------------------------
309 * NAND / SmartMedia
310 * -------------------------------------------------------------------- */
311
312#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
313static struct atmel_nand_data nand_data;
314
315#define NAND_BASE AT91_CHIPSELECT_3
316
317static struct resource nand_resources[] = {
318 [0] = {
319 .start = NAND_BASE,
320 .end = NAND_BASE + SZ_256M - 1,
321 .flags = IORESOURCE_MEM,
322 },
323 [1] = {
324 .start = AT91SAM9260_BASE_ECC,
325 .end = AT91SAM9260_BASE_ECC + SZ_512 - 1,
326 .flags = IORESOURCE_MEM,
327 }
328};
329
330static struct platform_device at91sam9260_nand_device = {
331 .name = "atmel_nand",
332 .id = -1,
333 .dev = {
334 .platform_data = &nand_data,
335 },
336 .resource = nand_resources,
337 .num_resources = ARRAY_SIZE(nand_resources),
338};
339
340void __init at91_add_device_nand(struct atmel_nand_data *data)
341{
342 unsigned long csa;
343
344 if (!data)
345 return;
346
347 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
348 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
349
350 /* enable pin */
351 if (gpio_is_valid(data->enable_pin))
352 at91_set_gpio_output(data->enable_pin, 1);
353
354 /* ready/busy pin */
355 if (gpio_is_valid(data->rdy_pin))
356 at91_set_gpio_input(data->rdy_pin, 1);
357
358 /* card detect pin */
359 if (gpio_is_valid(data->det_pin))
360 at91_set_gpio_input(data->det_pin, 1);
361
362 nand_data = *data;
363 platform_device_register(&at91sam9260_nand_device);
364}
365#else
366void __init at91_add_device_nand(struct atmel_nand_data *data) {}
367#endif
368
369
370/* --------------------------------------------------------------------
371 * TWI (i2c)
372 * -------------------------------------------------------------------- */
373
374/*
375 * Prefer the GPIO code since the TWI controller isn't robust
376 * (gets overruns and underruns under load) and can only issue
377 * repeated STARTs in one scenario (the driver doesn't yet handle them).
378 */
379
380#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
381
382static struct i2c_gpio_platform_data pdata = {
383 .sda_pin = AT91_PIN_PA23,
384 .sda_is_open_drain = 1,
385 .scl_pin = AT91_PIN_PA24,
386 .scl_is_open_drain = 1,
387 .udelay = 2, /* ~100 kHz */
388};
389
390static struct platform_device at91sam9260_twi_device = {
391 .name = "i2c-gpio",
392 .id = 0,
393 .dev.platform_data = &pdata,
394};
395
396void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
397{
398 at91_set_GPIO_periph(AT91_PIN_PA23, 1); /* TWD (SDA) */
399 at91_set_multi_drive(AT91_PIN_PA23, 1);
400
401 at91_set_GPIO_periph(AT91_PIN_PA24, 1); /* TWCK (SCL) */
402 at91_set_multi_drive(AT91_PIN_PA24, 1);
403
404 i2c_register_board_info(0, devices, nr_devices);
405 platform_device_register(&at91sam9260_twi_device);
406}
407
408#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
409
410static struct resource twi_resources[] = {
411 [0] = {
412 .start = AT91SAM9260_BASE_TWI,
413 .end = AT91SAM9260_BASE_TWI + SZ_16K - 1,
414 .flags = IORESOURCE_MEM,
415 },
416 [1] = {
417 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TWI,
418 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TWI,
419 .flags = IORESOURCE_IRQ,
420 },
421};
422
423static struct platform_device at91sam9260_twi_device = {
424 .id = 0,
425 .resource = twi_resources,
426 .num_resources = ARRAY_SIZE(twi_resources),
427};
428
429void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
430{
431 /* IP version is not the same on 9260 and g20 */
432 if (cpu_is_at91sam9g20()) {
433 at91sam9260_twi_device.name = "i2c-at91sam9g20";
434 } else {
435 at91sam9260_twi_device.name = "i2c-at91sam9260";
436 }
437
438 /* pins used for TWI interface */
439 at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */
440 at91_set_multi_drive(AT91_PIN_PA23, 1);
441
442 at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */
443 at91_set_multi_drive(AT91_PIN_PA24, 1);
444
445 i2c_register_board_info(0, devices, nr_devices);
446 platform_device_register(&at91sam9260_twi_device);
447}
448#else
449void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
450#endif
451
452
453/* --------------------------------------------------------------------
454 * SPI
455 * -------------------------------------------------------------------- */
456
457#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
458static u64 spi_dmamask = DMA_BIT_MASK(32);
459
460static struct resource spi0_resources[] = {
461 [0] = {
462 .start = AT91SAM9260_BASE_SPI0,
463 .end = AT91SAM9260_BASE_SPI0 + SZ_16K - 1,
464 .flags = IORESOURCE_MEM,
465 },
466 [1] = {
467 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI0,
468 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI0,
469 .flags = IORESOURCE_IRQ,
470 },
471};
472
473static struct platform_device at91sam9260_spi0_device = {
474 .name = "atmel_spi",
475 .id = 0,
476 .dev = {
477 .dma_mask = &spi_dmamask,
478 .coherent_dma_mask = DMA_BIT_MASK(32),
479 },
480 .resource = spi0_resources,
481 .num_resources = ARRAY_SIZE(spi0_resources),
482};
483
484static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PC11, AT91_PIN_PC16, AT91_PIN_PC17 };
485
486static struct resource spi1_resources[] = {
487 [0] = {
488 .start = AT91SAM9260_BASE_SPI1,
489 .end = AT91SAM9260_BASE_SPI1 + SZ_16K - 1,
490 .flags = IORESOURCE_MEM,
491 },
492 [1] = {
493 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI1,
494 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI1,
495 .flags = IORESOURCE_IRQ,
496 },
497};
498
499static struct platform_device at91sam9260_spi1_device = {
500 .name = "atmel_spi",
501 .id = 1,
502 .dev = {
503 .dma_mask = &spi_dmamask,
504 .coherent_dma_mask = DMA_BIT_MASK(32),
505 },
506 .resource = spi1_resources,
507 .num_resources = ARRAY_SIZE(spi1_resources),
508};
509
510static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PC5, AT91_PIN_PC4, AT91_PIN_PC3 };
511
512void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
513{
514 int i;
515 unsigned long cs_pin;
516 short enable_spi0 = 0;
517 short enable_spi1 = 0;
518
519 /* Choose SPI chip-selects */
520 for (i = 0; i < nr_devices; i++) {
521 if (devices[i].controller_data)
522 cs_pin = (unsigned long) devices[i].controller_data;
523 else if (devices[i].bus_num == 0)
524 cs_pin = spi0_standard_cs[devices[i].chip_select];
525 else
526 cs_pin = spi1_standard_cs[devices[i].chip_select];
527
528 if (!gpio_is_valid(cs_pin))
529 continue;
530
531 if (devices[i].bus_num == 0)
532 enable_spi0 = 1;
533 else
534 enable_spi1 = 1;
535
536 /* enable chip-select pin */
537 at91_set_gpio_output(cs_pin, 1);
538
539 /* pass chip-select pin to driver */
540 devices[i].controller_data = (void *) cs_pin;
541 }
542
543 spi_register_board_info(devices, nr_devices);
544
545 /* Configure SPI bus(es) */
546 if (enable_spi0) {
547 at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
548 at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
549 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI1_SPCK */
550
551 platform_device_register(&at91sam9260_spi0_device);
552 }
553 if (enable_spi1) {
554 at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI1_MISO */
555 at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI1_MOSI */
556 at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI1_SPCK */
557
558 platform_device_register(&at91sam9260_spi1_device);
559 }
560}
561#else
562void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
563#endif
564
565
566/* --------------------------------------------------------------------
567 * Timer/Counter blocks
568 * -------------------------------------------------------------------- */
569
570#ifdef CONFIG_ATMEL_TCLIB
571
572static struct resource tcb0_resources[] = {
573 [0] = {
574 .start = AT91SAM9260_BASE_TCB0,
575 .end = AT91SAM9260_BASE_TCB0 + SZ_256 - 1,
576 .flags = IORESOURCE_MEM,
577 },
578 [1] = {
579 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC0,
580 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC0,
581 .flags = IORESOURCE_IRQ,
582 },
583 [2] = {
584 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC1,
585 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC1,
586 .flags = IORESOURCE_IRQ,
587 },
588 [3] = {
589 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC2,
590 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC2,
591 .flags = IORESOURCE_IRQ,
592 },
593};
594
595static struct platform_device at91sam9260_tcb0_device = {
596 .name = "atmel_tcb",
597 .id = 0,
598 .resource = tcb0_resources,
599 .num_resources = ARRAY_SIZE(tcb0_resources),
600};
601
602static struct resource tcb1_resources[] = {
603 [0] = {
604 .start = AT91SAM9260_BASE_TCB1,
605 .end = AT91SAM9260_BASE_TCB1 + SZ_256 - 1,
606 .flags = IORESOURCE_MEM,
607 },
608 [1] = {
609 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC3,
610 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC3,
611 .flags = IORESOURCE_IRQ,
612 },
613 [2] = {
614 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC4,
615 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC4,
616 .flags = IORESOURCE_IRQ,
617 },
618 [3] = {
619 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC5,
620 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC5,
621 .flags = IORESOURCE_IRQ,
622 },
623};
624
625static struct platform_device at91sam9260_tcb1_device = {
626 .name = "atmel_tcb",
627 .id = 1,
628 .resource = tcb1_resources,
629 .num_resources = ARRAY_SIZE(tcb1_resources),
630};
631
632static void __init at91_add_device_tc(void)
633{
634 platform_device_register(&at91sam9260_tcb0_device);
635 platform_device_register(&at91sam9260_tcb1_device);
636}
637#else
638static void __init at91_add_device_tc(void) { }
639#endif
640
641
642/* --------------------------------------------------------------------
643 * RTT
644 * -------------------------------------------------------------------- */
645
646static struct resource rtt_resources[] = {
647 {
648 .start = AT91SAM9260_BASE_RTT,
649 .end = AT91SAM9260_BASE_RTT + SZ_16 - 1,
650 .flags = IORESOURCE_MEM,
651 }, {
652 .flags = IORESOURCE_MEM,
653 }, {
654 .flags = IORESOURCE_IRQ,
655 },
656};
657
658static struct platform_device at91sam9260_rtt_device = {
659 .name = "at91_rtt",
660 .id = 0,
661 .resource = rtt_resources,
662};
663
664
665#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
666static void __init at91_add_device_rtt_rtc(void)
667{
668 at91sam9260_rtt_device.name = "rtc-at91sam9";
669 /*
670 * The second resource is needed:
671 * GPBR will serve as the storage for RTC time offset
672 */
673 at91sam9260_rtt_device.num_resources = 3;
674 rtt_resources[1].start = AT91SAM9260_BASE_GPBR +
675 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
676 rtt_resources[1].end = rtt_resources[1].start + 3;
677 rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
678 rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
679}
680#else
681static void __init at91_add_device_rtt_rtc(void)
682{
683 /* Only one resource is needed: RTT not used as RTC */
684 at91sam9260_rtt_device.num_resources = 1;
685}
686#endif
687
688static void __init at91_add_device_rtt(void)
689{
690 at91_add_device_rtt_rtc();
691 platform_device_register(&at91sam9260_rtt_device);
692}
693
694
695/* --------------------------------------------------------------------
696 * Watchdog
697 * -------------------------------------------------------------------- */
698
699#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
700static struct resource wdt_resources[] = {
701 {
702 .start = AT91SAM9260_BASE_WDT,
703 .end = AT91SAM9260_BASE_WDT + SZ_16 - 1,
704 .flags = IORESOURCE_MEM,
705 }
706};
707
708static struct platform_device at91sam9260_wdt_device = {
709 .name = "at91_wdt",
710 .id = -1,
711 .resource = wdt_resources,
712 .num_resources = ARRAY_SIZE(wdt_resources),
713};
714
715static void __init at91_add_device_watchdog(void)
716{
717 platform_device_register(&at91sam9260_wdt_device);
718}
719#else
720static void __init at91_add_device_watchdog(void) {}
721#endif
722
723
724/* --------------------------------------------------------------------
725 * SSC -- Synchronous Serial Controller
726 * -------------------------------------------------------------------- */
727
728#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
729static u64 ssc_dmamask = DMA_BIT_MASK(32);
730
731static struct resource ssc_resources[] = {
732 [0] = {
733 .start = AT91SAM9260_BASE_SSC,
734 .end = AT91SAM9260_BASE_SSC + SZ_16K - 1,
735 .flags = IORESOURCE_MEM,
736 },
737 [1] = {
738 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_SSC,
739 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_SSC,
740 .flags = IORESOURCE_IRQ,
741 },
742};
743
744static struct platform_device at91sam9260_ssc_device = {
745 .name = "at91rm9200_ssc",
746 .id = 0,
747 .dev = {
748 .dma_mask = &ssc_dmamask,
749 .coherent_dma_mask = DMA_BIT_MASK(32),
750 },
751 .resource = ssc_resources,
752 .num_resources = ARRAY_SIZE(ssc_resources),
753};
754
755static inline void configure_ssc_pins(unsigned pins)
756{
757 if (pins & ATMEL_SSC_TF)
758 at91_set_A_periph(AT91_PIN_PB17, 1);
759 if (pins & ATMEL_SSC_TK)
760 at91_set_A_periph(AT91_PIN_PB16, 1);
761 if (pins & ATMEL_SSC_TD)
762 at91_set_A_periph(AT91_PIN_PB18, 1);
763 if (pins & ATMEL_SSC_RD)
764 at91_set_A_periph(AT91_PIN_PB19, 1);
765 if (pins & ATMEL_SSC_RK)
766 at91_set_A_periph(AT91_PIN_PB20, 1);
767 if (pins & ATMEL_SSC_RF)
768 at91_set_A_periph(AT91_PIN_PB21, 1);
769}
770
771/*
772 * SSC controllers are accessed through library code, instead of any
773 * kind of all-singing/all-dancing driver. For example one could be
774 * used by a particular I2S audio codec's driver, while another one
775 * on the same system might be used by a custom data capture driver.
776 */
777void __init at91_add_device_ssc(unsigned id, unsigned pins)
778{
779 struct platform_device *pdev;
780
781 /*
782 * NOTE: caller is responsible for passing information matching
783 * "pins" to whatever will be using each particular controller.
784 */
785 switch (id) {
786 case AT91SAM9260_ID_SSC:
787 pdev = &at91sam9260_ssc_device;
788 configure_ssc_pins(pins);
789 break;
790 default:
791 return;
792 }
793
794 platform_device_register(pdev);
795}
796
797#else
798void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
799#endif
800
801
802/* --------------------------------------------------------------------
803 * UART
804 * -------------------------------------------------------------------- */
805#if defined(CONFIG_SERIAL_ATMEL)
806static struct resource dbgu_resources[] = {
807 [0] = {
808 .start = AT91SAM9260_BASE_DBGU,
809 .end = AT91SAM9260_BASE_DBGU + SZ_512 - 1,
810 .flags = IORESOURCE_MEM,
811 },
812 [1] = {
813 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
814 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
815 .flags = IORESOURCE_IRQ,
816 },
817};
818
819static struct atmel_uart_data dbgu_data = {
820 .use_dma_tx = 0,
821 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
822};
823
824static u64 dbgu_dmamask = DMA_BIT_MASK(32);
825
826static struct platform_device at91sam9260_dbgu_device = {
827 .name = "atmel_usart",
828 .id = 0,
829 .dev = {
830 .dma_mask = &dbgu_dmamask,
831 .coherent_dma_mask = DMA_BIT_MASK(32),
832 .platform_data = &dbgu_data,
833 },
834 .resource = dbgu_resources,
835 .num_resources = ARRAY_SIZE(dbgu_resources),
836};
837
838static inline void configure_dbgu_pins(void)
839{
840 at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */
841 at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */
842}
843
844static struct resource uart0_resources[] = {
845 [0] = {
846 .start = AT91SAM9260_BASE_US0,
847 .end = AT91SAM9260_BASE_US0 + SZ_16K - 1,
848 .flags = IORESOURCE_MEM,
849 },
850 [1] = {
851 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US0,
852 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US0,
853 .flags = IORESOURCE_IRQ,
854 },
855};
856
857static struct atmel_uart_data uart0_data = {
858 .use_dma_tx = 1,
859 .use_dma_rx = 1,
860};
861
862static u64 uart0_dmamask = DMA_BIT_MASK(32);
863
864static struct platform_device at91sam9260_uart0_device = {
865 .name = "atmel_usart",
866 .id = 1,
867 .dev = {
868 .dma_mask = &uart0_dmamask,
869 .coherent_dma_mask = DMA_BIT_MASK(32),
870 .platform_data = &uart0_data,
871 },
872 .resource = uart0_resources,
873 .num_resources = ARRAY_SIZE(uart0_resources),
874};
875
876static inline void configure_usart0_pins(unsigned pins)
877{
878 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */
879 at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */
880
881 if (pins & ATMEL_UART_RTS)
882 at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS0 */
883 if (pins & ATMEL_UART_CTS)
884 at91_set_A_periph(AT91_PIN_PB27, 0); /* CTS0 */
885 if (pins & ATMEL_UART_DTR)
886 at91_set_A_periph(AT91_PIN_PB24, 0); /* DTR0 */
887 if (pins & ATMEL_UART_DSR)
888 at91_set_A_periph(AT91_PIN_PB22, 0); /* DSR0 */
889 if (pins & ATMEL_UART_DCD)
890 at91_set_A_periph(AT91_PIN_PB23, 0); /* DCD0 */
891 if (pins & ATMEL_UART_RI)
892 at91_set_A_periph(AT91_PIN_PB25, 0); /* RI0 */
893}
894
895static struct resource uart1_resources[] = {
896 [0] = {
897 .start = AT91SAM9260_BASE_US1,
898 .end = AT91SAM9260_BASE_US1 + SZ_16K - 1,
899 .flags = IORESOURCE_MEM,
900 },
901 [1] = {
902 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US1,
903 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US1,
904 .flags = IORESOURCE_IRQ,
905 },
906};
907
908static struct atmel_uart_data uart1_data = {
909 .use_dma_tx = 1,
910 .use_dma_rx = 1,
911};
912
913static u64 uart1_dmamask = DMA_BIT_MASK(32);
914
915static struct platform_device at91sam9260_uart1_device = {
916 .name = "atmel_usart",
917 .id = 2,
918 .dev = {
919 .dma_mask = &uart1_dmamask,
920 .coherent_dma_mask = DMA_BIT_MASK(32),
921 .platform_data = &uart1_data,
922 },
923 .resource = uart1_resources,
924 .num_resources = ARRAY_SIZE(uart1_resources),
925};
926
927static inline void configure_usart1_pins(unsigned pins)
928{
929 at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */
930 at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */
931
932 if (pins & ATMEL_UART_RTS)
933 at91_set_A_periph(AT91_PIN_PB28, 0); /* RTS1 */
934 if (pins & ATMEL_UART_CTS)
935 at91_set_A_periph(AT91_PIN_PB29, 0); /* CTS1 */
936}
937
938static struct resource uart2_resources[] = {
939 [0] = {
940 .start = AT91SAM9260_BASE_US2,
941 .end = AT91SAM9260_BASE_US2 + SZ_16K - 1,
942 .flags = IORESOURCE_MEM,
943 },
944 [1] = {
945 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US2,
946 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US2,
947 .flags = IORESOURCE_IRQ,
948 },
949};
950
951static struct atmel_uart_data uart2_data = {
952 .use_dma_tx = 1,
953 .use_dma_rx = 1,
954};
955
956static u64 uart2_dmamask = DMA_BIT_MASK(32);
957
958static struct platform_device at91sam9260_uart2_device = {
959 .name = "atmel_usart",
960 .id = 3,
961 .dev = {
962 .dma_mask = &uart2_dmamask,
963 .coherent_dma_mask = DMA_BIT_MASK(32),
964 .platform_data = &uart2_data,
965 },
966 .resource = uart2_resources,
967 .num_resources = ARRAY_SIZE(uart2_resources),
968};
969
970static inline void configure_usart2_pins(unsigned pins)
971{
972 at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */
973 at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */
974
975 if (pins & ATMEL_UART_RTS)
976 at91_set_A_periph(AT91_PIN_PA4, 0); /* RTS2 */
977 if (pins & ATMEL_UART_CTS)
978 at91_set_A_periph(AT91_PIN_PA5, 0); /* CTS2 */
979}
980
981static struct resource uart3_resources[] = {
982 [0] = {
983 .start = AT91SAM9260_BASE_US3,
984 .end = AT91SAM9260_BASE_US3 + SZ_16K - 1,
985 .flags = IORESOURCE_MEM,
986 },
987 [1] = {
988 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US3,
989 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US3,
990 .flags = IORESOURCE_IRQ,
991 },
992};
993
994static struct atmel_uart_data uart3_data = {
995 .use_dma_tx = 1,
996 .use_dma_rx = 1,
997};
998
999static u64 uart3_dmamask = DMA_BIT_MASK(32);
1000
1001static struct platform_device at91sam9260_uart3_device = {
1002 .name = "atmel_usart",
1003 .id = 4,
1004 .dev = {
1005 .dma_mask = &uart3_dmamask,
1006 .coherent_dma_mask = DMA_BIT_MASK(32),
1007 .platform_data = &uart3_data,
1008 },
1009 .resource = uart3_resources,
1010 .num_resources = ARRAY_SIZE(uart3_resources),
1011};
1012
1013static inline void configure_usart3_pins(unsigned pins)
1014{
1015 at91_set_A_periph(AT91_PIN_PB10, 1); /* TXD3 */
1016 at91_set_A_periph(AT91_PIN_PB11, 0); /* RXD3 */
1017
1018 if (pins & ATMEL_UART_RTS)
1019 at91_set_B_periph(AT91_PIN_PC8, 0); /* RTS3 */
1020 if (pins & ATMEL_UART_CTS)
1021 at91_set_B_periph(AT91_PIN_PC10, 0); /* CTS3 */
1022}
1023
1024static struct resource uart4_resources[] = {
1025 [0] = {
1026 .start = AT91SAM9260_BASE_US4,
1027 .end = AT91SAM9260_BASE_US4 + SZ_16K - 1,
1028 .flags = IORESOURCE_MEM,
1029 },
1030 [1] = {
1031 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US4,
1032 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US4,
1033 .flags = IORESOURCE_IRQ,
1034 },
1035};
1036
1037static struct atmel_uart_data uart4_data = {
1038 .use_dma_tx = 1,
1039 .use_dma_rx = 1,
1040};
1041
1042static u64 uart4_dmamask = DMA_BIT_MASK(32);
1043
1044static struct platform_device at91sam9260_uart4_device = {
1045 .name = "atmel_usart",
1046 .id = 5,
1047 .dev = {
1048 .dma_mask = &uart4_dmamask,
1049 .coherent_dma_mask = DMA_BIT_MASK(32),
1050 .platform_data = &uart4_data,
1051 },
1052 .resource = uart4_resources,
1053 .num_resources = ARRAY_SIZE(uart4_resources),
1054};
1055
1056static inline void configure_usart4_pins(void)
1057{
1058 at91_set_B_periph(AT91_PIN_PA31, 1); /* TXD4 */
1059 at91_set_B_periph(AT91_PIN_PA30, 0); /* RXD4 */
1060}
1061
1062static struct resource uart5_resources[] = {
1063 [0] = {
1064 .start = AT91SAM9260_BASE_US5,
1065 .end = AT91SAM9260_BASE_US5 + SZ_16K - 1,
1066 .flags = IORESOURCE_MEM,
1067 },
1068 [1] = {
1069 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US5,
1070 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US5,
1071 .flags = IORESOURCE_IRQ,
1072 },
1073};
1074
1075static struct atmel_uart_data uart5_data = {
1076 .use_dma_tx = 1,
1077 .use_dma_rx = 1,
1078};
1079
1080static u64 uart5_dmamask = DMA_BIT_MASK(32);
1081
1082static struct platform_device at91sam9260_uart5_device = {
1083 .name = "atmel_usart",
1084 .id = 6,
1085 .dev = {
1086 .dma_mask = &uart5_dmamask,
1087 .coherent_dma_mask = DMA_BIT_MASK(32),
1088 .platform_data = &uart5_data,
1089 },
1090 .resource = uart5_resources,
1091 .num_resources = ARRAY_SIZE(uart5_resources),
1092};
1093
1094static inline void configure_usart5_pins(void)
1095{
1096 at91_set_A_periph(AT91_PIN_PB12, 1); /* TXD5 */
1097 at91_set_A_periph(AT91_PIN_PB13, 0); /* RXD5 */
1098}
1099
1100static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1101
1102void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1103{
1104 struct platform_device *pdev;
1105 struct atmel_uart_data *pdata;
1106
1107 switch (id) {
1108 case 0: /* DBGU */
1109 pdev = &at91sam9260_dbgu_device;
1110 configure_dbgu_pins();
1111 break;
1112 case AT91SAM9260_ID_US0:
1113 pdev = &at91sam9260_uart0_device;
1114 configure_usart0_pins(pins);
1115 break;
1116 case AT91SAM9260_ID_US1:
1117 pdev = &at91sam9260_uart1_device;
1118 configure_usart1_pins(pins);
1119 break;
1120 case AT91SAM9260_ID_US2:
1121 pdev = &at91sam9260_uart2_device;
1122 configure_usart2_pins(pins);
1123 break;
1124 case AT91SAM9260_ID_US3:
1125 pdev = &at91sam9260_uart3_device;
1126 configure_usart3_pins(pins);
1127 break;
1128 case AT91SAM9260_ID_US4:
1129 pdev = &at91sam9260_uart4_device;
1130 configure_usart4_pins();
1131 break;
1132 case AT91SAM9260_ID_US5:
1133 pdev = &at91sam9260_uart5_device;
1134 configure_usart5_pins();
1135 break;
1136 default:
1137 return;
1138 }
1139 pdata = pdev->dev.platform_data;
1140 pdata->num = portnr; /* update to mapped ID */
1141
1142 if (portnr < ATMEL_MAX_UART)
1143 at91_uarts[portnr] = pdev;
1144}
1145
1146void __init at91_add_device_serial(void)
1147{
1148 int i;
1149
1150 for (i = 0; i < ATMEL_MAX_UART; i++) {
1151 if (at91_uarts[i])
1152 platform_device_register(at91_uarts[i]);
1153 }
1154}
1155#else
1156void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1157void __init at91_add_device_serial(void) {}
1158#endif
1159
1160/* --------------------------------------------------------------------
1161 * CF/IDE
1162 * -------------------------------------------------------------------- */
1163
1164#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \
1165 defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
1166
1167static struct at91_cf_data cf0_data;
1168
1169static struct resource cf0_resources[] = {
1170 [0] = {
1171 .start = AT91_CHIPSELECT_4,
1172 .end = AT91_CHIPSELECT_4 + SZ_256M - 1,
1173 .flags = IORESOURCE_MEM,
1174 }
1175};
1176
1177static struct platform_device cf0_device = {
1178 .id = 0,
1179 .dev = {
1180 .platform_data = &cf0_data,
1181 },
1182 .resource = cf0_resources,
1183 .num_resources = ARRAY_SIZE(cf0_resources),
1184};
1185
1186static struct at91_cf_data cf1_data;
1187
1188static struct resource cf1_resources[] = {
1189 [0] = {
1190 .start = AT91_CHIPSELECT_5,
1191 .end = AT91_CHIPSELECT_5 + SZ_256M - 1,
1192 .flags = IORESOURCE_MEM,
1193 }
1194};
1195
1196static struct platform_device cf1_device = {
1197 .id = 1,
1198 .dev = {
1199 .platform_data = &cf1_data,
1200 },
1201 .resource = cf1_resources,
1202 .num_resources = ARRAY_SIZE(cf1_resources),
1203};
1204
1205void __init at91_add_device_cf(struct at91_cf_data *data)
1206{
1207 struct platform_device *pdev;
1208 unsigned long csa;
1209
1210 if (!data)
1211 return;
1212
1213 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
1214
1215 switch (data->chipselect) {
1216 case 4:
1217 at91_set_multi_drive(AT91_PIN_PC8, 0);
1218 at91_set_A_periph(AT91_PIN_PC8, 0);
1219 csa |= AT91_MATRIX_CS4A_SMC_CF1;
1220 cf0_data = *data;
1221 pdev = &cf0_device;
1222 break;
1223 case 5:
1224 at91_set_multi_drive(AT91_PIN_PC9, 0);
1225 at91_set_A_periph(AT91_PIN_PC9, 0);
1226 csa |= AT91_MATRIX_CS5A_SMC_CF2;
1227 cf1_data = *data;
1228 pdev = &cf1_device;
1229 break;
1230 default:
1231 printk(KERN_ERR "AT91 CF: bad chip-select requested (%u)\n",
1232 data->chipselect);
1233 return;
1234 }
1235
1236 at91_matrix_write(AT91_MATRIX_EBICSA, csa);
1237
1238 if (gpio_is_valid(data->rst_pin)) {
1239 at91_set_multi_drive(data->rst_pin, 0);
1240 at91_set_gpio_output(data->rst_pin, 1);
1241 }
1242
1243 if (gpio_is_valid(data->irq_pin)) {
1244 at91_set_gpio_input(data->irq_pin, 0);
1245 at91_set_deglitch(data->irq_pin, 1);
1246 }
1247
1248 if (gpio_is_valid(data->det_pin)) {
1249 at91_set_gpio_input(data->det_pin, 0);
1250 at91_set_deglitch(data->det_pin, 1);
1251 }
1252
1253 at91_set_B_periph(AT91_PIN_PC6, 0); /* CFCE1 */
1254 at91_set_B_periph(AT91_PIN_PC7, 0); /* CFCE2 */
1255 at91_set_A_periph(AT91_PIN_PC10, 0); /* CFRNW */
1256 at91_set_A_periph(AT91_PIN_PC15, 1); /* NWAIT */
1257
1258 if (IS_ENABLED(CONFIG_PATA_AT91) && (data->flags & AT91_CF_TRUE_IDE))
1259 pdev->name = "pata_at91";
1260 else
1261 pdev->name = "at91_cf";
1262
1263 platform_device_register(pdev);
1264}
1265
1266#else
1267void __init at91_add_device_cf(struct at91_cf_data * data) {}
1268#endif
1269
1270/* --------------------------------------------------------------------
1271 * ADCs
1272 * -------------------------------------------------------------------- */
1273
1274#if IS_ENABLED(CONFIG_AT91_ADC)
1275static struct at91_adc_data adc_data;
1276
1277static struct resource adc_resources[] = {
1278 [0] = {
1279 .start = AT91SAM9260_BASE_ADC,
1280 .end = AT91SAM9260_BASE_ADC + SZ_16K - 1,
1281 .flags = IORESOURCE_MEM,
1282 },
1283 [1] = {
1284 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_ADC,
1285 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_ADC,
1286 .flags = IORESOURCE_IRQ,
1287 },
1288};
1289
1290static struct platform_device at91_adc_device = {
1291 .name = "at91sam9260-adc",
1292 .id = -1,
1293 .dev = {
1294 .platform_data = &adc_data,
1295 },
1296 .resource = adc_resources,
1297 .num_resources = ARRAY_SIZE(adc_resources),
1298};
1299
1300static struct at91_adc_trigger at91_adc_triggers[] = {
1301 [0] = {
1302 .name = "timer-counter-0",
1303 .value = 0x1,
1304 },
1305 [1] = {
1306 .name = "timer-counter-1",
1307 .value = 0x3,
1308 },
1309 [2] = {
1310 .name = "timer-counter-2",
1311 .value = 0x5,
1312 },
1313 [3] = {
1314 .name = "external",
1315 .value = 0xd,
1316 .is_external = true,
1317 },
1318};
1319
1320void __init at91_add_device_adc(struct at91_adc_data *data)
1321{
1322 if (!data)
1323 return;
1324
1325 if (test_bit(0, &data->channels_used))
1326 at91_set_A_periph(AT91_PIN_PC0, 0);
1327 if (test_bit(1, &data->channels_used))
1328 at91_set_A_periph(AT91_PIN_PC1, 0);
1329 if (test_bit(2, &data->channels_used))
1330 at91_set_A_periph(AT91_PIN_PC2, 0);
1331 if (test_bit(3, &data->channels_used))
1332 at91_set_A_periph(AT91_PIN_PC3, 0);
1333
1334 if (data->use_external_triggers)
1335 at91_set_A_periph(AT91_PIN_PA22, 0);
1336
1337 data->startup_time = 10;
1338 data->trigger_number = 4;
1339 data->trigger_list = at91_adc_triggers;
1340
1341 adc_data = *data;
1342 platform_device_register(&at91_adc_device);
1343}
1344#else
1345void __init at91_add_device_adc(struct at91_adc_data *data) {}
1346#endif
1347
1348/* -------------------------------------------------------------------- */
1349/*
1350 * These devices are always present and don't need any board-specific
1351 * setup.
1352 */
1353static int __init at91_add_standard_devices(void)
1354{
1355 if (of_have_populated_dt())
1356 return 0;
1357
1358 at91_add_device_rtt();
1359 at91_add_device_watchdog();
1360 at91_add_device_tc();
1361 return 0;
1362}
1363
1364arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index a8bd35963332..d29953ecb0c4 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -10,282 +10,12 @@
10 * 10 *
11 */ 11 */
12 12
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/clk/at91_pmc.h>
16
17#include <asm/proc-fns.h>
18#include <asm/irq.h>
19#include <asm/mach/arch.h>
20#include <asm/mach/map.h>
21#include <asm/system_misc.h> 13#include <asm/system_misc.h>
22#include <mach/cpu.h> 14#include <mach/cpu.h>
23#include <mach/at91sam9261.h>
24#include <mach/hardware.h> 15#include <mach/hardware.h>
25 16
26#include "at91_aic.h"
27#include "soc.h" 17#include "soc.h"
28#include "generic.h" 18#include "generic.h"
29#include "sam9_smc.h"
30#include "pm.h"
31
32#if defined(CONFIG_OLD_CLK_AT91)
33#include "clock.h"
34
35/* --------------------------------------------------------------------
36 * Clocks
37 * -------------------------------------------------------------------- */
38
39/*
40 * The peripheral clocks.
41 */
42static struct clk pioA_clk = {
43 .name = "pioA_clk",
44 .pmc_mask = 1 << AT91SAM9261_ID_PIOA,
45 .type = CLK_TYPE_PERIPHERAL,
46};
47static struct clk pioB_clk = {
48 .name = "pioB_clk",
49 .pmc_mask = 1 << AT91SAM9261_ID_PIOB,
50 .type = CLK_TYPE_PERIPHERAL,
51};
52static struct clk pioC_clk = {
53 .name = "pioC_clk",
54 .pmc_mask = 1 << AT91SAM9261_ID_PIOC,
55 .type = CLK_TYPE_PERIPHERAL,
56};
57static struct clk usart0_clk = {
58 .name = "usart0_clk",
59 .pmc_mask = 1 << AT91SAM9261_ID_US0,
60 .type = CLK_TYPE_PERIPHERAL,
61};
62static struct clk usart1_clk = {
63 .name = "usart1_clk",
64 .pmc_mask = 1 << AT91SAM9261_ID_US1,
65 .type = CLK_TYPE_PERIPHERAL,
66};
67static struct clk usart2_clk = {
68 .name = "usart2_clk",
69 .pmc_mask = 1 << AT91SAM9261_ID_US2,
70 .type = CLK_TYPE_PERIPHERAL,
71};
72static struct clk mmc_clk = {
73 .name = "mci_clk",
74 .pmc_mask = 1 << AT91SAM9261_ID_MCI,
75 .type = CLK_TYPE_PERIPHERAL,
76};
77static struct clk udc_clk = {
78 .name = "udc_clk",
79 .pmc_mask = 1 << AT91SAM9261_ID_UDP,
80 .type = CLK_TYPE_PERIPHERAL,
81};
82static struct clk twi_clk = {
83 .name = "twi_clk",
84 .pmc_mask = 1 << AT91SAM9261_ID_TWI,
85 .type = CLK_TYPE_PERIPHERAL,
86};
87static struct clk spi0_clk = {
88 .name = "spi0_clk",
89 .pmc_mask = 1 << AT91SAM9261_ID_SPI0,
90 .type = CLK_TYPE_PERIPHERAL,
91};
92static struct clk spi1_clk = {
93 .name = "spi1_clk",
94 .pmc_mask = 1 << AT91SAM9261_ID_SPI1,
95 .type = CLK_TYPE_PERIPHERAL,
96};
97static struct clk ssc0_clk = {
98 .name = "ssc0_clk",
99 .pmc_mask = 1 << AT91SAM9261_ID_SSC0,
100 .type = CLK_TYPE_PERIPHERAL,
101};
102static struct clk ssc1_clk = {
103 .name = "ssc1_clk",
104 .pmc_mask = 1 << AT91SAM9261_ID_SSC1,
105 .type = CLK_TYPE_PERIPHERAL,
106};
107static struct clk ssc2_clk = {
108 .name = "ssc2_clk",
109 .pmc_mask = 1 << AT91SAM9261_ID_SSC2,
110 .type = CLK_TYPE_PERIPHERAL,
111};
112static struct clk tc0_clk = {
113 .name = "tc0_clk",
114 .pmc_mask = 1 << AT91SAM9261_ID_TC0,
115 .type = CLK_TYPE_PERIPHERAL,
116};
117static struct clk tc1_clk = {
118 .name = "tc1_clk",
119 .pmc_mask = 1 << AT91SAM9261_ID_TC1,
120 .type = CLK_TYPE_PERIPHERAL,
121};
122static struct clk tc2_clk = {
123 .name = "tc2_clk",
124 .pmc_mask = 1 << AT91SAM9261_ID_TC2,
125 .type = CLK_TYPE_PERIPHERAL,
126};
127static struct clk ohci_clk = {
128 .name = "ohci_clk",
129 .pmc_mask = 1 << AT91SAM9261_ID_UHP,
130 .type = CLK_TYPE_PERIPHERAL,
131};
132static struct clk lcdc_clk = {
133 .name = "lcdc_clk",
134 .pmc_mask = 1 << AT91SAM9261_ID_LCDC,
135 .type = CLK_TYPE_PERIPHERAL,
136};
137
138/* HClocks */
139static struct clk hck0 = {
140 .name = "hck0",
141 .pmc_mask = AT91_PMC_HCK0,
142 .type = CLK_TYPE_SYSTEM,
143 .id = 0,
144};
145static struct clk hck1 = {
146 .name = "hck1",
147 .pmc_mask = AT91_PMC_HCK1,
148 .type = CLK_TYPE_SYSTEM,
149 .id = 1,
150};
151
152static struct clk *periph_clocks[] __initdata = {
153 &pioA_clk,
154 &pioB_clk,
155 &pioC_clk,
156 &usart0_clk,
157 &usart1_clk,
158 &usart2_clk,
159 &mmc_clk,
160 &udc_clk,
161 &twi_clk,
162 &spi0_clk,
163 &spi1_clk,
164 &ssc0_clk,
165 &ssc1_clk,
166 &ssc2_clk,
167 &tc0_clk,
168 &tc1_clk,
169 &tc2_clk,
170 &ohci_clk,
171 &lcdc_clk,
172 // irq0 .. irq2
173};
174
175static struct clk_lookup periph_clocks_lookups[] = {
176 CLKDEV_CON_DEV_ID("hclk", "at91sam9261-lcdfb.0", &hck1),
177 CLKDEV_CON_DEV_ID("hclk", "at91sam9g10-lcdfb.0", &hck1),
178 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
179 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
180 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
181 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
182 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
183 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
184 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
185 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk),
186 CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc0_clk),
187 CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc1_clk),
188 CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc2_clk),
189 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0),
190 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9261.0", &twi_clk),
191 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi_clk),
192 CLKDEV_CON_ID("pioA", &pioA_clk),
193 CLKDEV_CON_ID("pioB", &pioB_clk),
194 CLKDEV_CON_ID("pioC", &pioC_clk),
195 /* more lookup table for DT entries */
196 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
197 CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
198 CLKDEV_CON_DEV_ID("usart", "ffffb400.serial", &usart1_clk),
199 CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
200 CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
201 CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
202 CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
203 CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &hck0),
204 CLKDEV_CON_DEV_ID("hclk", "600000.fb", &hck1),
205 CLKDEV_CON_DEV_ID("spi_clk", "fffc8000.spi", &spi0_clk),
206 CLKDEV_CON_DEV_ID("spi_clk", "fffcc000.spi", &spi1_clk),
207 CLKDEV_CON_DEV_ID("mci_clk", "fffa8000.mmc", &mmc_clk),
208 CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi_clk),
209 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
210 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
211 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
212};
213
214static struct clk_lookup usart_clocks_lookups[] = {
215 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
216 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
217 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
218 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
219};
220
221/*
222 * The four programmable clocks.
223 * You must configure pin multiplexing to bring these signals out.
224 */
225static struct clk pck0 = {
226 .name = "pck0",
227 .pmc_mask = AT91_PMC_PCK0,
228 .type = CLK_TYPE_PROGRAMMABLE,
229 .id = 0,
230};
231static struct clk pck1 = {
232 .name = "pck1",
233 .pmc_mask = AT91_PMC_PCK1,
234 .type = CLK_TYPE_PROGRAMMABLE,
235 .id = 1,
236};
237static struct clk pck2 = {
238 .name = "pck2",
239 .pmc_mask = AT91_PMC_PCK2,
240 .type = CLK_TYPE_PROGRAMMABLE,
241 .id = 2,
242};
243static struct clk pck3 = {
244 .name = "pck3",
245 .pmc_mask = AT91_PMC_PCK3,
246 .type = CLK_TYPE_PROGRAMMABLE,
247 .id = 3,
248};
249
250static void __init at91sam9261_register_clocks(void)
251{
252 int i;
253
254 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
255 clk_register(periph_clocks[i]);
256
257 clkdev_add_table(periph_clocks_lookups,
258 ARRAY_SIZE(periph_clocks_lookups));
259 clkdev_add_table(usart_clocks_lookups,
260 ARRAY_SIZE(usart_clocks_lookups));
261
262 clk_register(&pck0);
263 clk_register(&pck1);
264 clk_register(&pck2);
265 clk_register(&pck3);
266
267 clk_register(&hck0);
268 clk_register(&hck1);
269}
270#else
271#define at91sam9261_register_clocks NULL
272#endif
273/* --------------------------------------------------------------------
274 * GPIO
275 * -------------------------------------------------------------------- */
276
277static struct at91_gpio_bank at91sam9261_gpio[] __initdata = {
278 {
279 .id = AT91SAM9261_ID_PIOA,
280 .regbase = AT91SAM9261_BASE_PIOA,
281 }, {
282 .id = AT91SAM9261_ID_PIOB,
283 .regbase = AT91SAM9261_BASE_PIOB,
284 }, {
285 .id = AT91SAM9261_ID_PIOC,
286 .regbase = AT91SAM9261_BASE_PIOC,
287 }
288};
289 19
290/* -------------------------------------------------------------------- 20/* --------------------------------------------------------------------
291 * AT91SAM9261 processor initialization 21 * AT91SAM9261 processor initialization
@@ -299,119 +29,14 @@ static void __init at91sam9261_map_io(void)
299 at91_init_sram(0, AT91SAM9261_SRAM_BASE, AT91SAM9261_SRAM_SIZE); 29 at91_init_sram(0, AT91SAM9261_SRAM_BASE, AT91SAM9261_SRAM_SIZE);
300} 30}
301 31
302static void __init at91sam9261_ioremap_registers(void)
303{
304 at91_ioremap_ramc(0, AT91SAM9261_BASE_SDRAMC, 512);
305 at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
306 at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
307 at91_ioremap_matrix(AT91SAM9261_BASE_MATRIX);
308 at91_pm_set_standby(at91sam9_sdram_standby);
309}
310
311static void __init at91sam9261_initialize(void) 32static void __init at91sam9261_initialize(void)
312{ 33{
313 arm_pm_idle = at91sam9_idle; 34 arm_pm_idle = at91sam9_idle;
314 35
315 at91_sysirq_mask_rtt(AT91SAM9261_BASE_RTT); 36 at91_sysirq_mask_rtt(AT91SAM9261_BASE_RTT);
316
317 /* Register GPIO subsystem */
318 at91_gpio_init(at91sam9261_gpio, 3);
319}
320
321static struct resource rstc_resources[] = {
322 [0] = {
323 .start = AT91SAM9261_BASE_RSTC,
324 .end = AT91SAM9261_BASE_RSTC + SZ_16 - 1,
325 .flags = IORESOURCE_MEM,
326 },
327 [1] = {
328 .start = AT91SAM9261_BASE_SDRAMC,
329 .end = AT91SAM9261_BASE_SDRAMC + SZ_512 - 1,
330 .flags = IORESOURCE_MEM,
331 },
332};
333
334static struct platform_device rstc_device = {
335 .name = "at91-sam9260-reset",
336 .resource = rstc_resources,
337 .num_resources = ARRAY_SIZE(rstc_resources),
338};
339
340static struct resource shdwc_resources[] = {
341 [0] = {
342 .start = AT91SAM9261_BASE_SHDWC,
343 .end = AT91SAM9261_BASE_SHDWC + SZ_16 - 1,
344 .flags = IORESOURCE_MEM,
345 },
346};
347
348static struct platform_device shdwc_device = {
349 .name = "at91-poweroff",
350 .resource = shdwc_resources,
351 .num_resources = ARRAY_SIZE(shdwc_resources),
352};
353
354static void __init at91sam9261_register_devices(void)
355{
356 platform_device_register(&rstc_device);
357 platform_device_register(&shdwc_device);
358}
359
360/* --------------------------------------------------------------------
361 * Interrupt initialization
362 * -------------------------------------------------------------------- */
363
364/*
365 * The default interrupt priority levels (0 = lowest, 7 = highest).
366 */
367static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
368 7, /* Advanced Interrupt Controller */
369 7, /* System Peripherals */
370 1, /* Parallel IO Controller A */
371 1, /* Parallel IO Controller B */
372 1, /* Parallel IO Controller C */
373 0,
374 5, /* USART 0 */
375 5, /* USART 1 */
376 5, /* USART 2 */
377 0, /* Multimedia Card Interface */
378 2, /* USB Device Port */
379 6, /* Two-Wire Interface */
380 5, /* Serial Peripheral Interface 0 */
381 5, /* Serial Peripheral Interface 1 */
382 4, /* Serial Synchronous Controller 0 */
383 4, /* Serial Synchronous Controller 1 */
384 4, /* Serial Synchronous Controller 2 */
385 0, /* Timer Counter 0 */
386 0, /* Timer Counter 1 */
387 0, /* Timer Counter 2 */
388 2, /* USB Host port */
389 3, /* LCD Controller */
390 0,
391 0,
392 0,
393 0,
394 0,
395 0,
396 0,
397 0, /* Advanced Interrupt Controller */
398 0, /* Advanced Interrupt Controller */
399 0, /* Advanced Interrupt Controller */
400};
401
402static void __init at91sam9261_init_time(void)
403{
404 at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS);
405} 37}
406 38
407AT91_SOC_START(at91sam9261) 39AT91_SOC_START(at91sam9261)
408 .map_io = at91sam9261_map_io, 40 .map_io = at91sam9261_map_io,
409 .default_irq_priority = at91sam9261_default_irq_priority,
410 .extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
411 | (1 << AT91SAM9261_ID_IRQ2),
412 .ioremap_registers = at91sam9261_ioremap_registers,
413 .register_clocks = at91sam9261_register_clocks,
414 .register_devices = at91sam9261_register_devices,
415 .init = at91sam9261_initialize, 41 .init = at91sam9261_initialize,
416 .init_time = at91sam9261_init_time,
417AT91_SOC_END 42AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
deleted file mode 100644
index 29baacb5c359..000000000000
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ /dev/null
@@ -1,1098 +0,0 @@
1/*
2 * arch/arm/mach-at91/at91sam9261_devices.c
3 *
4 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
5 * Copyright (C) 2005 David Brownell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13#include <asm/mach/arch.h>
14#include <asm/mach/map.h>
15
16#include <linux/dma-mapping.h>
17#include <linux/gpio.h>
18#include <linux/platform_device.h>
19#include <linux/i2c-gpio.h>
20
21#include <linux/fb.h>
22#include <video/atmel_lcdc.h>
23
24#include <mach/at91sam9261.h>
25#include <mach/at91sam9261_matrix.h>
26#include <mach/at91_matrix.h>
27#include <mach/at91sam9_smc.h>
28#include <mach/hardware.h>
29
30#include "board.h"
31#include "generic.h"
32#include "gpio.h"
33
34/* --------------------------------------------------------------------
35 * USB Host
36 * -------------------------------------------------------------------- */
37
38#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
39static u64 ohci_dmamask = DMA_BIT_MASK(32);
40static struct at91_usbh_data usbh_data;
41
42static struct resource usbh_resources[] = {
43 [0] = {
44 .start = AT91SAM9261_UHP_BASE,
45 .end = AT91SAM9261_UHP_BASE + SZ_1M - 1,
46 .flags = IORESOURCE_MEM,
47 },
48 [1] = {
49 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_UHP,
50 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_UHP,
51 .flags = IORESOURCE_IRQ,
52 },
53};
54
55static struct platform_device at91sam9261_usbh_device = {
56 .name = "at91_ohci",
57 .id = -1,
58 .dev = {
59 .dma_mask = &ohci_dmamask,
60 .coherent_dma_mask = DMA_BIT_MASK(32),
61 .platform_data = &usbh_data,
62 },
63 .resource = usbh_resources,
64 .num_resources = ARRAY_SIZE(usbh_resources),
65};
66
67void __init at91_add_device_usbh(struct at91_usbh_data *data)
68{
69 int i;
70
71 if (!data)
72 return;
73
74 /* Enable overcurrent notification */
75 for (i = 0; i < data->ports; i++) {
76 if (gpio_is_valid(data->overcurrent_pin[i]))
77 at91_set_gpio_input(data->overcurrent_pin[i], 1);
78 }
79
80 usbh_data = *data;
81 platform_device_register(&at91sam9261_usbh_device);
82}
83#else
84void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
85#endif
86
87
88/* --------------------------------------------------------------------
89 * USB Device (Gadget)
90 * -------------------------------------------------------------------- */
91
92#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
93static struct at91_udc_data udc_data;
94
95static struct resource udc_resources[] = {
96 [0] = {
97 .start = AT91SAM9261_BASE_UDP,
98 .end = AT91SAM9261_BASE_UDP + SZ_16K - 1,
99 .flags = IORESOURCE_MEM,
100 },
101 [1] = {
102 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_UDP,
103 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_UDP,
104 .flags = IORESOURCE_IRQ,
105 },
106};
107
108static struct platform_device at91sam9261_udc_device = {
109 .name = "at91_udc",
110 .id = -1,
111 .dev = {
112 .platform_data = &udc_data,
113 },
114 .resource = udc_resources,
115 .num_resources = ARRAY_SIZE(udc_resources),
116};
117
118void __init at91_add_device_udc(struct at91_udc_data *data)
119{
120 if (!data)
121 return;
122
123 if (gpio_is_valid(data->vbus_pin)) {
124 at91_set_gpio_input(data->vbus_pin, 0);
125 at91_set_deglitch(data->vbus_pin, 1);
126 }
127
128 /* Pullup pin is handled internally by USB device peripheral */
129
130 udc_data = *data;
131 platform_device_register(&at91sam9261_udc_device);
132}
133#else
134void __init at91_add_device_udc(struct at91_udc_data *data) {}
135#endif
136
137/* --------------------------------------------------------------------
138 * MMC / SD
139 * -------------------------------------------------------------------- */
140
141#if IS_ENABLED(CONFIG_MMC_ATMELMCI)
142static u64 mmc_dmamask = DMA_BIT_MASK(32);
143static struct mci_platform_data mmc_data;
144
145static struct resource mmc_resources[] = {
146 [0] = {
147 .start = AT91SAM9261_BASE_MCI,
148 .end = AT91SAM9261_BASE_MCI + SZ_16K - 1,
149 .flags = IORESOURCE_MEM,
150 },
151 [1] = {
152 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_MCI,
153 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_MCI,
154 .flags = IORESOURCE_IRQ,
155 },
156};
157
158static struct platform_device at91sam9261_mmc_device = {
159 .name = "atmel_mci",
160 .id = -1,
161 .dev = {
162 .dma_mask = &mmc_dmamask,
163 .coherent_dma_mask = DMA_BIT_MASK(32),
164 .platform_data = &mmc_data,
165 },
166 .resource = mmc_resources,
167 .num_resources = ARRAY_SIZE(mmc_resources),
168};
169
170void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
171{
172 if (!data)
173 return;
174
175 if (data->slot[0].bus_width) {
176 /* input/irq */
177 if (gpio_is_valid(data->slot[0].detect_pin)) {
178 at91_set_gpio_input(data->slot[0].detect_pin, 1);
179 at91_set_deglitch(data->slot[0].detect_pin, 1);
180 }
181 if (gpio_is_valid(data->slot[0].wp_pin))
182 at91_set_gpio_input(data->slot[0].wp_pin, 1);
183
184 /* CLK */
185 at91_set_B_periph(AT91_PIN_PA2, 0);
186
187 /* CMD */
188 at91_set_B_periph(AT91_PIN_PA1, 1);
189
190 /* DAT0, maybe DAT1..DAT3 */
191 at91_set_B_periph(AT91_PIN_PA0, 1);
192 if (data->slot[0].bus_width == 4) {
193 at91_set_B_periph(AT91_PIN_PA4, 1);
194 at91_set_B_periph(AT91_PIN_PA5, 1);
195 at91_set_B_periph(AT91_PIN_PA6, 1);
196 }
197
198 mmc_data = *data;
199 platform_device_register(&at91sam9261_mmc_device);
200 }
201}
202#else
203void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
204#endif
205
206
207/* --------------------------------------------------------------------
208 * NAND / SmartMedia
209 * -------------------------------------------------------------------- */
210
211#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
212static struct atmel_nand_data nand_data;
213
214#define NAND_BASE AT91_CHIPSELECT_3
215
216static struct resource nand_resources[] = {
217 {
218 .start = NAND_BASE,
219 .end = NAND_BASE + SZ_256M - 1,
220 .flags = IORESOURCE_MEM,
221 }
222};
223
224static struct platform_device atmel_nand_device = {
225 .name = "atmel_nand",
226 .id = -1,
227 .dev = {
228 .platform_data = &nand_data,
229 },
230 .resource = nand_resources,
231 .num_resources = ARRAY_SIZE(nand_resources),
232};
233
234void __init at91_add_device_nand(struct atmel_nand_data *data)
235{
236 unsigned long csa;
237
238 if (!data)
239 return;
240
241 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
242 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
243
244 /* enable pin */
245 if (gpio_is_valid(data->enable_pin))
246 at91_set_gpio_output(data->enable_pin, 1);
247
248 /* ready/busy pin */
249 if (gpio_is_valid(data->rdy_pin))
250 at91_set_gpio_input(data->rdy_pin, 1);
251
252 /* card detect pin */
253 if (gpio_is_valid(data->det_pin))
254 at91_set_gpio_input(data->det_pin, 1);
255
256 at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
257 at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
258
259 nand_data = *data;
260 platform_device_register(&atmel_nand_device);
261}
262
263#else
264void __init at91_add_device_nand(struct atmel_nand_data *data) {}
265#endif
266
267
268/* --------------------------------------------------------------------
269 * TWI (i2c)
270 * -------------------------------------------------------------------- */
271
272/*
273 * Prefer the GPIO code since the TWI controller isn't robust
274 * (gets overruns and underruns under load) and can only issue
275 * repeated STARTs in one scenario (the driver doesn't yet handle them).
276 */
277#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
278
279static struct i2c_gpio_platform_data pdata = {
280 .sda_pin = AT91_PIN_PA7,
281 .sda_is_open_drain = 1,
282 .scl_pin = AT91_PIN_PA8,
283 .scl_is_open_drain = 1,
284 .udelay = 2, /* ~100 kHz */
285};
286
287static struct platform_device at91sam9261_twi_device = {
288 .name = "i2c-gpio",
289 .id = 0,
290 .dev.platform_data = &pdata,
291};
292
293void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
294{
295 at91_set_GPIO_periph(AT91_PIN_PA7, 1); /* TWD (SDA) */
296 at91_set_multi_drive(AT91_PIN_PA7, 1);
297
298 at91_set_GPIO_periph(AT91_PIN_PA8, 1); /* TWCK (SCL) */
299 at91_set_multi_drive(AT91_PIN_PA8, 1);
300
301 i2c_register_board_info(0, devices, nr_devices);
302 platform_device_register(&at91sam9261_twi_device);
303}
304
305#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
306
307static struct resource twi_resources[] = {
308 [0] = {
309 .start = AT91SAM9261_BASE_TWI,
310 .end = AT91SAM9261_BASE_TWI + SZ_16K - 1,
311 .flags = IORESOURCE_MEM,
312 },
313 [1] = {
314 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TWI,
315 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TWI,
316 .flags = IORESOURCE_IRQ,
317 },
318};
319
320static struct platform_device at91sam9261_twi_device = {
321 .id = 0,
322 .resource = twi_resources,
323 .num_resources = ARRAY_SIZE(twi_resources),
324};
325
326void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
327{
328 /* IP version is not the same on 9261 and g10 */
329 if (cpu_is_at91sam9g10()) {
330 at91sam9261_twi_device.name = "i2c-at91sam9g10";
331 /* I2C PIO must not be configured as open-drain on this chip */
332 } else {
333 at91sam9261_twi_device.name = "i2c-at91sam9261";
334 at91_set_multi_drive(AT91_PIN_PA7, 1);
335 at91_set_multi_drive(AT91_PIN_PA8, 1);
336 }
337
338 /* pins used for TWI interface */
339 at91_set_A_periph(AT91_PIN_PA7, 0); /* TWD */
340 at91_set_A_periph(AT91_PIN_PA8, 0); /* TWCK */
341
342 i2c_register_board_info(0, devices, nr_devices);
343 platform_device_register(&at91sam9261_twi_device);
344}
345#else
346void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
347#endif
348
349
350/* --------------------------------------------------------------------
351 * SPI
352 * -------------------------------------------------------------------- */
353
354#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
355static u64 spi_dmamask = DMA_BIT_MASK(32);
356
357static struct resource spi0_resources[] = {
358 [0] = {
359 .start = AT91SAM9261_BASE_SPI0,
360 .end = AT91SAM9261_BASE_SPI0 + SZ_16K - 1,
361 .flags = IORESOURCE_MEM,
362 },
363 [1] = {
364 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI0,
365 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI0,
366 .flags = IORESOURCE_IRQ,
367 },
368};
369
370static struct platform_device at91sam9261_spi0_device = {
371 .name = "atmel_spi",
372 .id = 0,
373 .dev = {
374 .dma_mask = &spi_dmamask,
375 .coherent_dma_mask = DMA_BIT_MASK(32),
376 },
377 .resource = spi0_resources,
378 .num_resources = ARRAY_SIZE(spi0_resources),
379};
380
381static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
382
383static struct resource spi1_resources[] = {
384 [0] = {
385 .start = AT91SAM9261_BASE_SPI1,
386 .end = AT91SAM9261_BASE_SPI1 + SZ_16K - 1,
387 .flags = IORESOURCE_MEM,
388 },
389 [1] = {
390 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI1,
391 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI1,
392 .flags = IORESOURCE_IRQ,
393 },
394};
395
396static struct platform_device at91sam9261_spi1_device = {
397 .name = "atmel_spi",
398 .id = 1,
399 .dev = {
400 .dma_mask = &spi_dmamask,
401 .coherent_dma_mask = DMA_BIT_MASK(32),
402 },
403 .resource = spi1_resources,
404 .num_resources = ARRAY_SIZE(spi1_resources),
405};
406
407static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB28, AT91_PIN_PA24, AT91_PIN_PA25, AT91_PIN_PA26 };
408
409void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
410{
411 int i;
412 unsigned long cs_pin;
413 short enable_spi0 = 0;
414 short enable_spi1 = 0;
415
416 /* Choose SPI chip-selects */
417 for (i = 0; i < nr_devices; i++) {
418 if (devices[i].controller_data)
419 cs_pin = (unsigned long) devices[i].controller_data;
420 else if (devices[i].bus_num == 0)
421 cs_pin = spi0_standard_cs[devices[i].chip_select];
422 else
423 cs_pin = spi1_standard_cs[devices[i].chip_select];
424
425 if (!gpio_is_valid(cs_pin))
426 continue;
427
428 if (devices[i].bus_num == 0)
429 enable_spi0 = 1;
430 else
431 enable_spi1 = 1;
432
433 /* enable chip-select pin */
434 at91_set_gpio_output(cs_pin, 1);
435
436 /* pass chip-select pin to driver */
437 devices[i].controller_data = (void *) cs_pin;
438 }
439
440 spi_register_board_info(devices, nr_devices);
441
442 /* Configure SPI bus(es) */
443 if (enable_spi0) {
444 at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
445 at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
446 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
447
448 platform_device_register(&at91sam9261_spi0_device);
449 }
450 if (enable_spi1) {
451 at91_set_A_periph(AT91_PIN_PB30, 0); /* SPI1_MISO */
452 at91_set_A_periph(AT91_PIN_PB31, 0); /* SPI1_MOSI */
453 at91_set_A_periph(AT91_PIN_PB29, 0); /* SPI1_SPCK */
454
455 platform_device_register(&at91sam9261_spi1_device);
456 }
457}
458#else
459void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
460#endif
461
462
463/* --------------------------------------------------------------------
464 * LCD Controller
465 * -------------------------------------------------------------------- */
466
467#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
468static u64 lcdc_dmamask = DMA_BIT_MASK(32);
469static struct atmel_lcdfb_pdata lcdc_data;
470
471static struct resource lcdc_resources[] = {
472 [0] = {
473 .start = AT91SAM9261_LCDC_BASE,
474 .end = AT91SAM9261_LCDC_BASE + SZ_4K - 1,
475 .flags = IORESOURCE_MEM,
476 },
477 [1] = {
478 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_LCDC,
479 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_LCDC,
480 .flags = IORESOURCE_IRQ,
481 },
482#if defined(CONFIG_FB_INTSRAM)
483 [2] = {
484 .start = AT91SAM9261_SRAM_BASE,
485 .end = AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE - 1,
486 .flags = IORESOURCE_MEM,
487 },
488#endif
489};
490
491static struct platform_device at91_lcdc_device = {
492 .id = 0,
493 .dev = {
494 .dma_mask = &lcdc_dmamask,
495 .coherent_dma_mask = DMA_BIT_MASK(32),
496 .platform_data = &lcdc_data,
497 },
498 .resource = lcdc_resources,
499 .num_resources = ARRAY_SIZE(lcdc_resources),
500};
501
502void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data)
503{
504 if (!data) {
505 return;
506 }
507
508 if (cpu_is_at91sam9g10())
509 at91_lcdc_device.name = "at91sam9g10-lcdfb";
510 else
511 at91_lcdc_device.name = "at91sam9261-lcdfb";
512
513#if defined(CONFIG_FB_ATMEL_STN)
514 at91_set_A_periph(AT91_PIN_PB0, 0); /* LCDVSYNC */
515 at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
516 at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
517 at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
518 at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
519 at91_set_A_periph(AT91_PIN_PB5, 0); /* LCDD0 */
520 at91_set_A_periph(AT91_PIN_PB6, 0); /* LCDD1 */
521 at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
522 at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
523#else
524 at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
525 at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
526 at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
527 at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
528 at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
529 at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
530 at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
531 at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
532 at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
533 at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
534 at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
535 at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
536 at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
537 at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
538 at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
539 at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
540 at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */
541 at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */
542 at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */
543 at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */
544 at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
545 at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
546#endif
547
548 if (ARRAY_SIZE(lcdc_resources) > 2) {
549 void __iomem *fb;
550 struct resource *fb_res = &lcdc_resources[2];
551 size_t fb_len = resource_size(fb_res);
552
553 fb = ioremap(fb_res->start, fb_len);
554 if (fb) {
555 memset(fb, 0, fb_len);
556 iounmap(fb);
557 }
558 }
559 lcdc_data = *data;
560 platform_device_register(&at91_lcdc_device);
561}
562#else
563void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) {}
564#endif
565
566
567/* --------------------------------------------------------------------
568 * Timer/Counter block
569 * -------------------------------------------------------------------- */
570
571#ifdef CONFIG_ATMEL_TCLIB
572
573static struct resource tcb_resources[] = {
574 [0] = {
575 .start = AT91SAM9261_BASE_TCB0,
576 .end = AT91SAM9261_BASE_TCB0 + SZ_16K - 1,
577 .flags = IORESOURCE_MEM,
578 },
579 [1] = {
580 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TC0,
581 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TC0,
582 .flags = IORESOURCE_IRQ,
583 },
584 [2] = {
585 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TC1,
586 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TC1,
587 .flags = IORESOURCE_IRQ,
588 },
589 [3] = {
590 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TC2,
591 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TC2,
592 .flags = IORESOURCE_IRQ,
593 },
594};
595
596static struct platform_device at91sam9261_tcb_device = {
597 .name = "atmel_tcb",
598 .id = 0,
599 .resource = tcb_resources,
600 .num_resources = ARRAY_SIZE(tcb_resources),
601};
602
603static void __init at91_add_device_tc(void)
604{
605 platform_device_register(&at91sam9261_tcb_device);
606}
607#else
608static void __init at91_add_device_tc(void) { }
609#endif
610
611
612/* --------------------------------------------------------------------
613 * RTT
614 * -------------------------------------------------------------------- */
615
616static struct resource rtt_resources[] = {
617 {
618 .start = AT91SAM9261_BASE_RTT,
619 .end = AT91SAM9261_BASE_RTT + SZ_16 - 1,
620 .flags = IORESOURCE_MEM,
621 }, {
622 .flags = IORESOURCE_MEM,
623 }, {
624 .flags = IORESOURCE_IRQ,
625 }
626};
627
628static struct platform_device at91sam9261_rtt_device = {
629 .name = "at91_rtt",
630 .id = 0,
631 .resource = rtt_resources,
632};
633
634#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
635static void __init at91_add_device_rtt_rtc(void)
636{
637 at91sam9261_rtt_device.name = "rtc-at91sam9";
638 /*
639 * The second resource is needed:
640 * GPBR will serve as the storage for RTC time offset
641 */
642 at91sam9261_rtt_device.num_resources = 3;
643 rtt_resources[1].start = AT91SAM9261_BASE_GPBR +
644 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
645 rtt_resources[1].end = rtt_resources[1].start + 3;
646 rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
647 rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
648}
649#else
650static void __init at91_add_device_rtt_rtc(void)
651{
652 /* Only one resource is needed: RTT not used as RTC */
653 at91sam9261_rtt_device.num_resources = 1;
654}
655#endif
656
657static void __init at91_add_device_rtt(void)
658{
659 at91_add_device_rtt_rtc();
660 platform_device_register(&at91sam9261_rtt_device);
661}
662
663
664/* --------------------------------------------------------------------
665 * Watchdog
666 * -------------------------------------------------------------------- */
667
668#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
669static struct resource wdt_resources[] = {
670 {
671 .start = AT91SAM9261_BASE_WDT,
672 .end = AT91SAM9261_BASE_WDT + SZ_16 - 1,
673 .flags = IORESOURCE_MEM,
674 }
675};
676
677static struct platform_device at91sam9261_wdt_device = {
678 .name = "at91_wdt",
679 .id = -1,
680 .resource = wdt_resources,
681 .num_resources = ARRAY_SIZE(wdt_resources),
682};
683
684static void __init at91_add_device_watchdog(void)
685{
686 platform_device_register(&at91sam9261_wdt_device);
687}
688#else
689static void __init at91_add_device_watchdog(void) {}
690#endif
691
692
693/* --------------------------------------------------------------------
694 * SSC -- Synchronous Serial Controller
695 * -------------------------------------------------------------------- */
696
697#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
698static u64 ssc0_dmamask = DMA_BIT_MASK(32);
699
700static struct resource ssc0_resources[] = {
701 [0] = {
702 .start = AT91SAM9261_BASE_SSC0,
703 .end = AT91SAM9261_BASE_SSC0 + SZ_16K - 1,
704 .flags = IORESOURCE_MEM,
705 },
706 [1] = {
707 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC0,
708 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC0,
709 .flags = IORESOURCE_IRQ,
710 },
711};
712
713static struct platform_device at91sam9261_ssc0_device = {
714 .name = "at91rm9200_ssc",
715 .id = 0,
716 .dev = {
717 .dma_mask = &ssc0_dmamask,
718 .coherent_dma_mask = DMA_BIT_MASK(32),
719 },
720 .resource = ssc0_resources,
721 .num_resources = ARRAY_SIZE(ssc0_resources),
722};
723
724static inline void configure_ssc0_pins(unsigned pins)
725{
726 if (pins & ATMEL_SSC_TF)
727 at91_set_A_periph(AT91_PIN_PB21, 1);
728 if (pins & ATMEL_SSC_TK)
729 at91_set_A_periph(AT91_PIN_PB22, 1);
730 if (pins & ATMEL_SSC_TD)
731 at91_set_A_periph(AT91_PIN_PB23, 1);
732 if (pins & ATMEL_SSC_RD)
733 at91_set_A_periph(AT91_PIN_PB24, 1);
734 if (pins & ATMEL_SSC_RK)
735 at91_set_A_periph(AT91_PIN_PB25, 1);
736 if (pins & ATMEL_SSC_RF)
737 at91_set_A_periph(AT91_PIN_PB26, 1);
738}
739
740static u64 ssc1_dmamask = DMA_BIT_MASK(32);
741
742static struct resource ssc1_resources[] = {
743 [0] = {
744 .start = AT91SAM9261_BASE_SSC1,
745 .end = AT91SAM9261_BASE_SSC1 + SZ_16K - 1,
746 .flags = IORESOURCE_MEM,
747 },
748 [1] = {
749 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC1,
750 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC1,
751 .flags = IORESOURCE_IRQ,
752 },
753};
754
755static struct platform_device at91sam9261_ssc1_device = {
756 .name = "at91rm9200_ssc",
757 .id = 1,
758 .dev = {
759 .dma_mask = &ssc1_dmamask,
760 .coherent_dma_mask = DMA_BIT_MASK(32),
761 },
762 .resource = ssc1_resources,
763 .num_resources = ARRAY_SIZE(ssc1_resources),
764};
765
766static inline void configure_ssc1_pins(unsigned pins)
767{
768 if (pins & ATMEL_SSC_TF)
769 at91_set_B_periph(AT91_PIN_PA17, 1);
770 if (pins & ATMEL_SSC_TK)
771 at91_set_B_periph(AT91_PIN_PA18, 1);
772 if (pins & ATMEL_SSC_TD)
773 at91_set_B_periph(AT91_PIN_PA19, 1);
774 if (pins & ATMEL_SSC_RD)
775 at91_set_B_periph(AT91_PIN_PA20, 1);
776 if (pins & ATMEL_SSC_RK)
777 at91_set_B_periph(AT91_PIN_PA21, 1);
778 if (pins & ATMEL_SSC_RF)
779 at91_set_B_periph(AT91_PIN_PA22, 1);
780}
781
782static u64 ssc2_dmamask = DMA_BIT_MASK(32);
783
784static struct resource ssc2_resources[] = {
785 [0] = {
786 .start = AT91SAM9261_BASE_SSC2,
787 .end = AT91SAM9261_BASE_SSC2 + SZ_16K - 1,
788 .flags = IORESOURCE_MEM,
789 },
790 [1] = {
791 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC2,
792 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC2,
793 .flags = IORESOURCE_IRQ,
794 },
795};
796
797static struct platform_device at91sam9261_ssc2_device = {
798 .name = "at91rm9200_ssc",
799 .id = 2,
800 .dev = {
801 .dma_mask = &ssc2_dmamask,
802 .coherent_dma_mask = DMA_BIT_MASK(32),
803 },
804 .resource = ssc2_resources,
805 .num_resources = ARRAY_SIZE(ssc2_resources),
806};
807
808static inline void configure_ssc2_pins(unsigned pins)
809{
810 if (pins & ATMEL_SSC_TF)
811 at91_set_B_periph(AT91_PIN_PC25, 1);
812 if (pins & ATMEL_SSC_TK)
813 at91_set_B_periph(AT91_PIN_PC26, 1);
814 if (pins & ATMEL_SSC_TD)
815 at91_set_B_periph(AT91_PIN_PC27, 1);
816 if (pins & ATMEL_SSC_RD)
817 at91_set_B_periph(AT91_PIN_PC28, 1);
818 if (pins & ATMEL_SSC_RK)
819 at91_set_B_periph(AT91_PIN_PC29, 1);
820 if (pins & ATMEL_SSC_RF)
821 at91_set_B_periph(AT91_PIN_PC30, 1);
822}
823
824/*
825 * SSC controllers are accessed through library code, instead of any
826 * kind of all-singing/all-dancing driver. For example one could be
827 * used by a particular I2S audio codec's driver, while another one
828 * on the same system might be used by a custom data capture driver.
829 */
830void __init at91_add_device_ssc(unsigned id, unsigned pins)
831{
832 struct platform_device *pdev;
833
834 /*
835 * NOTE: caller is responsible for passing information matching
836 * "pins" to whatever will be using each particular controller.
837 */
838 switch (id) {
839 case AT91SAM9261_ID_SSC0:
840 pdev = &at91sam9261_ssc0_device;
841 configure_ssc0_pins(pins);
842 break;
843 case AT91SAM9261_ID_SSC1:
844 pdev = &at91sam9261_ssc1_device;
845 configure_ssc1_pins(pins);
846 break;
847 case AT91SAM9261_ID_SSC2:
848 pdev = &at91sam9261_ssc2_device;
849 configure_ssc2_pins(pins);
850 break;
851 default:
852 return;
853 }
854
855 platform_device_register(pdev);
856}
857
858#else
859void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
860#endif
861
862
863/* --------------------------------------------------------------------
864 * UART
865 * -------------------------------------------------------------------- */
866
867#if defined(CONFIG_SERIAL_ATMEL)
868static struct resource dbgu_resources[] = {
869 [0] = {
870 .start = AT91SAM9261_BASE_DBGU,
871 .end = AT91SAM9261_BASE_DBGU + SZ_512 - 1,
872 .flags = IORESOURCE_MEM,
873 },
874 [1] = {
875 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
876 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
877 .flags = IORESOURCE_IRQ,
878 },
879};
880
881static struct atmel_uart_data dbgu_data = {
882 .use_dma_tx = 0,
883 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
884};
885
886static u64 dbgu_dmamask = DMA_BIT_MASK(32);
887
888static struct platform_device at91sam9261_dbgu_device = {
889 .name = "atmel_usart",
890 .id = 0,
891 .dev = {
892 .dma_mask = &dbgu_dmamask,
893 .coherent_dma_mask = DMA_BIT_MASK(32),
894 .platform_data = &dbgu_data,
895 },
896 .resource = dbgu_resources,
897 .num_resources = ARRAY_SIZE(dbgu_resources),
898};
899
900static inline void configure_dbgu_pins(void)
901{
902 at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */
903 at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */
904}
905
906static struct resource uart0_resources[] = {
907 [0] = {
908 .start = AT91SAM9261_BASE_US0,
909 .end = AT91SAM9261_BASE_US0 + SZ_16K - 1,
910 .flags = IORESOURCE_MEM,
911 },
912 [1] = {
913 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_US0,
914 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_US0,
915 .flags = IORESOURCE_IRQ,
916 },
917};
918
919static struct atmel_uart_data uart0_data = {
920 .use_dma_tx = 1,
921 .use_dma_rx = 1,
922};
923
924static u64 uart0_dmamask = DMA_BIT_MASK(32);
925
926static struct platform_device at91sam9261_uart0_device = {
927 .name = "atmel_usart",
928 .id = 1,
929 .dev = {
930 .dma_mask = &uart0_dmamask,
931 .coherent_dma_mask = DMA_BIT_MASK(32),
932 .platform_data = &uart0_data,
933 },
934 .resource = uart0_resources,
935 .num_resources = ARRAY_SIZE(uart0_resources),
936};
937
938static inline void configure_usart0_pins(unsigned pins)
939{
940 at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */
941 at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */
942
943 if (pins & ATMEL_UART_RTS)
944 at91_set_A_periph(AT91_PIN_PC10, 0); /* RTS0 */
945 if (pins & ATMEL_UART_CTS)
946 at91_set_A_periph(AT91_PIN_PC11, 0); /* CTS0 */
947}
948
949static struct resource uart1_resources[] = {
950 [0] = {
951 .start = AT91SAM9261_BASE_US1,
952 .end = AT91SAM9261_BASE_US1 + SZ_16K - 1,
953 .flags = IORESOURCE_MEM,
954 },
955 [1] = {
956 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_US1,
957 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_US1,
958 .flags = IORESOURCE_IRQ,
959 },
960};
961
962static struct atmel_uart_data uart1_data = {
963 .use_dma_tx = 1,
964 .use_dma_rx = 1,
965};
966
967static u64 uart1_dmamask = DMA_BIT_MASK(32);
968
969static struct platform_device at91sam9261_uart1_device = {
970 .name = "atmel_usart",
971 .id = 2,
972 .dev = {
973 .dma_mask = &uart1_dmamask,
974 .coherent_dma_mask = DMA_BIT_MASK(32),
975 .platform_data = &uart1_data,
976 },
977 .resource = uart1_resources,
978 .num_resources = ARRAY_SIZE(uart1_resources),
979};
980
981static inline void configure_usart1_pins(unsigned pins)
982{
983 at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */
984 at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */
985
986 if (pins & ATMEL_UART_RTS)
987 at91_set_B_periph(AT91_PIN_PA12, 0); /* RTS1 */
988 if (pins & ATMEL_UART_CTS)
989 at91_set_B_periph(AT91_PIN_PA13, 0); /* CTS1 */
990}
991
992static struct resource uart2_resources[] = {
993 [0] = {
994 .start = AT91SAM9261_BASE_US2,
995 .end = AT91SAM9261_BASE_US2 + SZ_16K - 1,
996 .flags = IORESOURCE_MEM,
997 },
998 [1] = {
999 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_US2,
1000 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_US2,
1001 .flags = IORESOURCE_IRQ,
1002 },
1003};
1004
1005static struct atmel_uart_data uart2_data = {
1006 .use_dma_tx = 1,
1007 .use_dma_rx = 1,
1008};
1009
1010static u64 uart2_dmamask = DMA_BIT_MASK(32);
1011
1012static struct platform_device at91sam9261_uart2_device = {
1013 .name = "atmel_usart",
1014 .id = 3,
1015 .dev = {
1016 .dma_mask = &uart2_dmamask,
1017 .coherent_dma_mask = DMA_BIT_MASK(32),
1018 .platform_data = &uart2_data,
1019 },
1020 .resource = uart2_resources,
1021 .num_resources = ARRAY_SIZE(uart2_resources),
1022};
1023
1024static inline void configure_usart2_pins(unsigned pins)
1025{
1026 at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */
1027 at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */
1028
1029 if (pins & ATMEL_UART_RTS)
1030 at91_set_B_periph(AT91_PIN_PA15, 0); /* RTS2*/
1031 if (pins & ATMEL_UART_CTS)
1032 at91_set_B_periph(AT91_PIN_PA16, 0); /* CTS2 */
1033}
1034
1035static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1036
1037void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1038{
1039 struct platform_device *pdev;
1040 struct atmel_uart_data *pdata;
1041
1042 switch (id) {
1043 case 0: /* DBGU */
1044 pdev = &at91sam9261_dbgu_device;
1045 configure_dbgu_pins();
1046 break;
1047 case AT91SAM9261_ID_US0:
1048 pdev = &at91sam9261_uart0_device;
1049 configure_usart0_pins(pins);
1050 break;
1051 case AT91SAM9261_ID_US1:
1052 pdev = &at91sam9261_uart1_device;
1053 configure_usart1_pins(pins);
1054 break;
1055 case AT91SAM9261_ID_US2:
1056 pdev = &at91sam9261_uart2_device;
1057 configure_usart2_pins(pins);
1058 break;
1059 default:
1060 return;
1061 }
1062 pdata = pdev->dev.platform_data;
1063 pdata->num = portnr; /* update to mapped ID */
1064
1065 if (portnr < ATMEL_MAX_UART)
1066 at91_uarts[portnr] = pdev;
1067}
1068
1069void __init at91_add_device_serial(void)
1070{
1071 int i;
1072
1073 for (i = 0; i < ATMEL_MAX_UART; i++) {
1074 if (at91_uarts[i])
1075 platform_device_register(at91_uarts[i]);
1076 }
1077}
1078#else
1079void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1080void __init at91_add_device_serial(void) {}
1081#endif
1082
1083
1084/* -------------------------------------------------------------------- */
1085
1086/*
1087 * These devices are always present and don't need any board-specific
1088 * setup.
1089 */
1090static int __init at91_add_standard_devices(void)
1091{
1092 at91_add_device_rtt();
1093 at91_add_device_watchdog();
1094 at91_add_device_tc();
1095 return 0;
1096}
1097
1098arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index fbff228cc63e..e7ad14864083 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -10,304 +10,11 @@
10 * 10 *
11 */ 11 */
12 12
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/clk/at91_pmc.h>
16
17#include <asm/proc-fns.h>
18#include <asm/irq.h>
19#include <asm/mach/arch.h>
20#include <asm/mach/map.h>
21#include <asm/system_misc.h> 13#include <asm/system_misc.h>
22#include <mach/at91sam9263.h>
23#include <mach/hardware.h> 14#include <mach/hardware.h>
24 15
25#include "at91_aic.h"
26#include "soc.h" 16#include "soc.h"
27#include "generic.h" 17#include "generic.h"
28#include "sam9_smc.h"
29#include "pm.h"
30
31#if defined(CONFIG_OLD_CLK_AT91)
32#include "clock.h"
33/* --------------------------------------------------------------------
34 * Clocks
35 * -------------------------------------------------------------------- */
36
37/*
38 * The peripheral clocks.
39 */
40static struct clk pioA_clk = {
41 .name = "pioA_clk",
42 .pmc_mask = 1 << AT91SAM9263_ID_PIOA,
43 .type = CLK_TYPE_PERIPHERAL,
44};
45static struct clk pioB_clk = {
46 .name = "pioB_clk",
47 .pmc_mask = 1 << AT91SAM9263_ID_PIOB,
48 .type = CLK_TYPE_PERIPHERAL,
49};
50static struct clk pioCDE_clk = {
51 .name = "pioCDE_clk",
52 .pmc_mask = 1 << AT91SAM9263_ID_PIOCDE,
53 .type = CLK_TYPE_PERIPHERAL,
54};
55static struct clk usart0_clk = {
56 .name = "usart0_clk",
57 .pmc_mask = 1 << AT91SAM9263_ID_US0,
58 .type = CLK_TYPE_PERIPHERAL,
59};
60static struct clk usart1_clk = {
61 .name = "usart1_clk",
62 .pmc_mask = 1 << AT91SAM9263_ID_US1,
63 .type = CLK_TYPE_PERIPHERAL,
64};
65static struct clk usart2_clk = {
66 .name = "usart2_clk",
67 .pmc_mask = 1 << AT91SAM9263_ID_US2,
68 .type = CLK_TYPE_PERIPHERAL,
69};
70static struct clk mmc0_clk = {
71 .name = "mci0_clk",
72 .pmc_mask = 1 << AT91SAM9263_ID_MCI0,
73 .type = CLK_TYPE_PERIPHERAL,
74};
75static struct clk mmc1_clk = {
76 .name = "mci1_clk",
77 .pmc_mask = 1 << AT91SAM9263_ID_MCI1,
78 .type = CLK_TYPE_PERIPHERAL,
79};
80static struct clk can_clk = {
81 .name = "can_clk",
82 .pmc_mask = 1 << AT91SAM9263_ID_CAN,
83 .type = CLK_TYPE_PERIPHERAL,
84};
85static struct clk twi_clk = {
86 .name = "twi_clk",
87 .pmc_mask = 1 << AT91SAM9263_ID_TWI,
88 .type = CLK_TYPE_PERIPHERAL,
89};
90static struct clk spi0_clk = {
91 .name = "spi0_clk",
92 .pmc_mask = 1 << AT91SAM9263_ID_SPI0,
93 .type = CLK_TYPE_PERIPHERAL,
94};
95static struct clk spi1_clk = {
96 .name = "spi1_clk",
97 .pmc_mask = 1 << AT91SAM9263_ID_SPI1,
98 .type = CLK_TYPE_PERIPHERAL,
99};
100static struct clk ssc0_clk = {
101 .name = "ssc0_clk",
102 .pmc_mask = 1 << AT91SAM9263_ID_SSC0,
103 .type = CLK_TYPE_PERIPHERAL,
104};
105static struct clk ssc1_clk = {
106 .name = "ssc1_clk",
107 .pmc_mask = 1 << AT91SAM9263_ID_SSC1,
108 .type = CLK_TYPE_PERIPHERAL,
109};
110static struct clk ac97_clk = {
111 .name = "ac97_clk",
112 .pmc_mask = 1 << AT91SAM9263_ID_AC97C,
113 .type = CLK_TYPE_PERIPHERAL,
114};
115static struct clk tcb_clk = {
116 .name = "tcb_clk",
117 .pmc_mask = 1 << AT91SAM9263_ID_TCB,
118 .type = CLK_TYPE_PERIPHERAL,
119};
120static struct clk pwm_clk = {
121 .name = "pwm_clk",
122 .pmc_mask = 1 << AT91SAM9263_ID_PWMC,
123 .type = CLK_TYPE_PERIPHERAL,
124};
125static struct clk macb_clk = {
126 .name = "pclk",
127 .pmc_mask = 1 << AT91SAM9263_ID_EMAC,
128 .type = CLK_TYPE_PERIPHERAL,
129};
130static struct clk dma_clk = {
131 .name = "dma_clk",
132 .pmc_mask = 1 << AT91SAM9263_ID_DMA,
133 .type = CLK_TYPE_PERIPHERAL,
134};
135static struct clk twodge_clk = {
136 .name = "2dge_clk",
137 .pmc_mask = 1 << AT91SAM9263_ID_2DGE,
138 .type = CLK_TYPE_PERIPHERAL,
139};
140static struct clk udc_clk = {
141 .name = "udc_clk",
142 .pmc_mask = 1 << AT91SAM9263_ID_UDP,
143 .type = CLK_TYPE_PERIPHERAL,
144};
145static struct clk isi_clk = {
146 .name = "isi_clk",
147 .pmc_mask = 1 << AT91SAM9263_ID_ISI,
148 .type = CLK_TYPE_PERIPHERAL,
149};
150static struct clk lcdc_clk = {
151 .name = "lcdc_clk",
152 .pmc_mask = 1 << AT91SAM9263_ID_LCDC,
153 .type = CLK_TYPE_PERIPHERAL,
154};
155static struct clk ohci_clk = {
156 .name = "ohci_clk",
157 .pmc_mask = 1 << AT91SAM9263_ID_UHP,
158 .type = CLK_TYPE_PERIPHERAL,
159};
160
161static struct clk *periph_clocks[] __initdata = {
162 &pioA_clk,
163 &pioB_clk,
164 &pioCDE_clk,
165 &usart0_clk,
166 &usart1_clk,
167 &usart2_clk,
168 &mmc0_clk,
169 &mmc1_clk,
170 &can_clk,
171 &twi_clk,
172 &spi0_clk,
173 &spi1_clk,
174 &ssc0_clk,
175 &ssc1_clk,
176 &ac97_clk,
177 &tcb_clk,
178 &pwm_clk,
179 &macb_clk,
180 &twodge_clk,
181 &udc_clk,
182 &isi_clk,
183 &lcdc_clk,
184 &dma_clk,
185 &ohci_clk,
186 // irq0 .. irq1
187};
188
189static struct clk_lookup periph_clocks_lookups[] = {
190 /* One additional fake clock for macb_hclk */
191 CLKDEV_CON_ID("hclk", &macb_clk),
192 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
193 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
194 CLKDEV_CON_DEV_ID("pclk", "fff98000.ssc", &ssc0_clk),
195 CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc1_clk),
196 CLKDEV_CON_DEV_ID("hclk", "at91sam9263-lcdfb.0", &lcdc_clk),
197 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
198 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
199 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
200 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
201 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
202 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
203 CLKDEV_CON_DEV_ID(NULL, "at91sam9rl-pwm", &pwm_clk),
204 /* fake hclk clock */
205 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
206 CLKDEV_CON_ID("pioA", &pioA_clk),
207 CLKDEV_CON_ID("pioB", &pioB_clk),
208 CLKDEV_CON_ID("pioC", &pioCDE_clk),
209 CLKDEV_CON_ID("pioD", &pioCDE_clk),
210 CLKDEV_CON_ID("pioE", &pioCDE_clk),
211 /* more usart lookup table for DT entries */
212 CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
213 CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
214 CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
215 CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
216 /* more tc lookup table for DT entries */
217 CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb_clk),
218 CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk),
219 CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
220 CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
221 CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
222 CLKDEV_CON_DEV_ID("mci_clk", "fff84000.mmc", &mmc1_clk),
223 CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi_clk),
224 CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
225 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
226 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioCDE_clk),
227 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCDE_clk),
228 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCDE_clk),
229 CLKDEV_CON_DEV_ID(NULL, "fffb8000.pwm", &pwm_clk),
230};
231
232static struct clk_lookup usart_clocks_lookups[] = {
233 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
234 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
235 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
236 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
237};
238
239/*
240 * The four programmable clocks.
241 * You must configure pin multiplexing to bring these signals out.
242 */
243static struct clk pck0 = {
244 .name = "pck0",
245 .pmc_mask = AT91_PMC_PCK0,
246 .type = CLK_TYPE_PROGRAMMABLE,
247 .id = 0,
248};
249static struct clk pck1 = {
250 .name = "pck1",
251 .pmc_mask = AT91_PMC_PCK1,
252 .type = CLK_TYPE_PROGRAMMABLE,
253 .id = 1,
254};
255static struct clk pck2 = {
256 .name = "pck2",
257 .pmc_mask = AT91_PMC_PCK2,
258 .type = CLK_TYPE_PROGRAMMABLE,
259 .id = 2,
260};
261static struct clk pck3 = {
262 .name = "pck3",
263 .pmc_mask = AT91_PMC_PCK3,
264 .type = CLK_TYPE_PROGRAMMABLE,
265 .id = 3,
266};
267
268static void __init at91sam9263_register_clocks(void)
269{
270 int i;
271
272 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
273 clk_register(periph_clocks[i]);
274
275 clkdev_add_table(periph_clocks_lookups,
276 ARRAY_SIZE(periph_clocks_lookups));
277 clkdev_add_table(usart_clocks_lookups,
278 ARRAY_SIZE(usart_clocks_lookups));
279
280 clk_register(&pck0);
281 clk_register(&pck1);
282 clk_register(&pck2);
283 clk_register(&pck3);
284}
285#else
286#define at91sam9263_register_clocks NULL
287#endif
288
289/* --------------------------------------------------------------------
290 * GPIO
291 * -------------------------------------------------------------------- */
292
293static struct at91_gpio_bank at91sam9263_gpio[] __initdata = {
294 {
295 .id = AT91SAM9263_ID_PIOA,
296 .regbase = AT91SAM9263_BASE_PIOA,
297 }, {
298 .id = AT91SAM9263_ID_PIOB,
299 .regbase = AT91SAM9263_BASE_PIOB,
300 }, {
301 .id = AT91SAM9263_ID_PIOCDE,
302 .regbase = AT91SAM9263_BASE_PIOC,
303 }, {
304 .id = AT91SAM9263_ID_PIOCDE,
305 .regbase = AT91SAM9263_BASE_PIOD,
306 }, {
307 .id = AT91SAM9263_ID_PIOCDE,
308 .regbase = AT91SAM9263_BASE_PIOE,
309 }
310};
311 18
312/* -------------------------------------------------------------------- 19/* --------------------------------------------------------------------
313 * AT91SAM9263 processor initialization 20 * AT91SAM9263 processor initialization
@@ -319,121 +26,15 @@ static void __init at91sam9263_map_io(void)
319 at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE); 26 at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE);
320} 27}
321 28
322static void __init at91sam9263_ioremap_registers(void)
323{
324 at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512);
325 at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512);
326 at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
327 at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
328 at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
329 at91_ioremap_matrix(AT91SAM9263_BASE_MATRIX);
330 at91_pm_set_standby(at91sam9_sdram_standby);
331}
332
333static void __init at91sam9263_initialize(void) 29static void __init at91sam9263_initialize(void)
334{ 30{
335 arm_pm_idle = at91sam9_idle; 31 arm_pm_idle = at91sam9_idle;
336 32
337 at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT0); 33 at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT0);
338 at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT1); 34 at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT1);
339
340 /* Register GPIO subsystem */
341 at91_gpio_init(at91sam9263_gpio, 5);
342}
343
344static struct resource rstc_resources[] = {
345 [0] = {
346 .start = AT91SAM9263_BASE_RSTC,
347 .end = AT91SAM9263_BASE_RSTC + SZ_16 - 1,
348 .flags = IORESOURCE_MEM,
349 },
350 [1] = {
351 .start = AT91SAM9263_BASE_SDRAMC0,
352 .end = AT91SAM9263_BASE_SDRAMC0 + SZ_512 - 1,
353 .flags = IORESOURCE_MEM,
354 },
355};
356
357static struct platform_device rstc_device = {
358 .name = "at91-sam9260-reset",
359 .resource = rstc_resources,
360 .num_resources = ARRAY_SIZE(rstc_resources),
361};
362
363static struct resource shdwc_resources[] = {
364 [0] = {
365 .start = AT91SAM9263_BASE_SHDWC,
366 .end = AT91SAM9263_BASE_SHDWC + SZ_16 - 1,
367 .flags = IORESOURCE_MEM,
368 },
369};
370
371static struct platform_device shdwc_device = {
372 .name = "at91-poweroff",
373 .resource = shdwc_resources,
374 .num_resources = ARRAY_SIZE(shdwc_resources),
375};
376
377static void __init at91sam9263_register_devices(void)
378{
379 platform_device_register(&rstc_device);
380 platform_device_register(&shdwc_device);
381}
382
383/* --------------------------------------------------------------------
384 * Interrupt initialization
385 * -------------------------------------------------------------------- */
386
387/*
388 * The default interrupt priority levels (0 = lowest, 7 = highest).
389 */
390static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
391 7, /* Advanced Interrupt Controller (FIQ) */
392 7, /* System Peripherals */
393 1, /* Parallel IO Controller A */
394 1, /* Parallel IO Controller B */
395 1, /* Parallel IO Controller C, D and E */
396 0,
397 0,
398 5, /* USART 0 */
399 5, /* USART 1 */
400 5, /* USART 2 */
401 0, /* Multimedia Card Interface 0 */
402 0, /* Multimedia Card Interface 1 */
403 3, /* CAN */
404 6, /* Two-Wire Interface */
405 5, /* Serial Peripheral Interface 0 */
406 5, /* Serial Peripheral Interface 1 */
407 4, /* Serial Synchronous Controller 0 */
408 4, /* Serial Synchronous Controller 1 */
409 5, /* AC97 Controller */
410 0, /* Timer Counter 0, 1 and 2 */
411 0, /* Pulse Width Modulation Controller */
412 3, /* Ethernet */
413 0,
414 0, /* 2D Graphic Engine */
415 2, /* USB Device Port */
416 0, /* Image Sensor Interface */
417 3, /* LDC Controller */
418 0, /* DMA Controller */
419 0,
420 2, /* USB Host port */
421 0, /* Advanced Interrupt Controller (IRQ0) */
422 0, /* Advanced Interrupt Controller (IRQ1) */
423};
424
425static void __init at91sam9263_init_time(void)
426{
427 at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS);
428} 35}
429 36
430AT91_SOC_START(at91sam9263) 37AT91_SOC_START(at91sam9263)
431 .map_io = at91sam9263_map_io, 38 .map_io = at91sam9263_map_io,
432 .default_irq_priority = at91sam9263_default_irq_priority,
433 .extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1),
434 .ioremap_registers = at91sam9263_ioremap_registers,
435 .register_clocks = at91sam9263_register_clocks,
436 .register_devices = at91sam9263_register_devices,
437 .init = at91sam9263_initialize, 39 .init = at91sam9263_initialize,
438 .init_time = at91sam9263_init_time,
439AT91_SOC_END 40AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
deleted file mode 100644
index cef0e2f57068..000000000000
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ /dev/null
@@ -1,1538 +0,0 @@
1/*
2 * arch/arm/mach-at91/at91sam9263_devices.c
3 *
4 * Copyright (C) 2007 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12#include <asm/mach/arch.h>
13#include <asm/mach/map.h>
14
15#include <linux/dma-mapping.h>
16#include <linux/gpio.h>
17#include <linux/platform_device.h>
18#include <linux/i2c-gpio.h>
19
20#include <linux/fb.h>
21#include <video/atmel_lcdc.h>
22
23#include <mach/at91sam9263.h>
24#include <mach/at91sam9263_matrix.h>
25#include <mach/at91_matrix.h>
26#include <mach/at91sam9_smc.h>
27#include <mach/hardware.h>
28
29#include "board.h"
30#include "generic.h"
31#include "gpio.h"
32
33
34/* --------------------------------------------------------------------
35 * USB Host
36 * -------------------------------------------------------------------- */
37
38#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
39static u64 ohci_dmamask = DMA_BIT_MASK(32);
40static struct at91_usbh_data usbh_data;
41
42static struct resource usbh_resources[] = {
43 [0] = {
44 .start = AT91SAM9263_UHP_BASE,
45 .end = AT91SAM9263_UHP_BASE + SZ_1M - 1,
46 .flags = IORESOURCE_MEM,
47 },
48 [1] = {
49 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_UHP,
50 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_UHP,
51 .flags = IORESOURCE_IRQ,
52 },
53};
54
55static struct platform_device at91_usbh_device = {
56 .name = "at91_ohci",
57 .id = -1,
58 .dev = {
59 .dma_mask = &ohci_dmamask,
60 .coherent_dma_mask = DMA_BIT_MASK(32),
61 .platform_data = &usbh_data,
62 },
63 .resource = usbh_resources,
64 .num_resources = ARRAY_SIZE(usbh_resources),
65};
66
67void __init at91_add_device_usbh(struct at91_usbh_data *data)
68{
69 int i;
70
71 if (!data)
72 return;
73
74 /* Enable VBus control for UHP ports */
75 for (i = 0; i < data->ports; i++) {
76 if (gpio_is_valid(data->vbus_pin[i]))
77 at91_set_gpio_output(data->vbus_pin[i],
78 data->vbus_pin_active_low[i]);
79 }
80
81 /* Enable overcurrent notification */
82 for (i = 0; i < data->ports; i++) {
83 if (gpio_is_valid(data->overcurrent_pin[i]))
84 at91_set_gpio_input(data->overcurrent_pin[i], 1);
85 }
86
87 usbh_data = *data;
88 platform_device_register(&at91_usbh_device);
89}
90#else
91void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
92#endif
93
94
95/* --------------------------------------------------------------------
96 * USB Device (Gadget)
97 * -------------------------------------------------------------------- */
98
99#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
100static struct at91_udc_data udc_data;
101
102static struct resource udc_resources[] = {
103 [0] = {
104 .start = AT91SAM9263_BASE_UDP,
105 .end = AT91SAM9263_BASE_UDP + SZ_16K - 1,
106 .flags = IORESOURCE_MEM,
107 },
108 [1] = {
109 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_UDP,
110 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_UDP,
111 .flags = IORESOURCE_IRQ,
112 },
113};
114
115static struct platform_device at91_udc_device = {
116 .name = "at91_udc",
117 .id = -1,
118 .dev = {
119 .platform_data = &udc_data,
120 },
121 .resource = udc_resources,
122 .num_resources = ARRAY_SIZE(udc_resources),
123};
124
125void __init at91_add_device_udc(struct at91_udc_data *data)
126{
127 if (!data)
128 return;
129
130 if (gpio_is_valid(data->vbus_pin)) {
131 at91_set_gpio_input(data->vbus_pin, 0);
132 at91_set_deglitch(data->vbus_pin, 1);
133 }
134
135 /* Pullup pin is handled internally by USB device peripheral */
136
137 udc_data = *data;
138 platform_device_register(&at91_udc_device);
139}
140#else
141void __init at91_add_device_udc(struct at91_udc_data *data) {}
142#endif
143
144
145/* --------------------------------------------------------------------
146 * Ethernet
147 * -------------------------------------------------------------------- */
148
149#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
150static u64 eth_dmamask = DMA_BIT_MASK(32);
151static struct macb_platform_data eth_data;
152
153static struct resource eth_resources[] = {
154 [0] = {
155 .start = AT91SAM9263_BASE_EMAC,
156 .end = AT91SAM9263_BASE_EMAC + SZ_16K - 1,
157 .flags = IORESOURCE_MEM,
158 },
159 [1] = {
160 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_EMAC,
161 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_EMAC,
162 .flags = IORESOURCE_IRQ,
163 },
164};
165
166static struct platform_device at91sam9263_eth_device = {
167 .name = "macb",
168 .id = -1,
169 .dev = {
170 .dma_mask = &eth_dmamask,
171 .coherent_dma_mask = DMA_BIT_MASK(32),
172 .platform_data = &eth_data,
173 },
174 .resource = eth_resources,
175 .num_resources = ARRAY_SIZE(eth_resources),
176};
177
178void __init at91_add_device_eth(struct macb_platform_data *data)
179{
180 if (!data)
181 return;
182
183 if (gpio_is_valid(data->phy_irq_pin)) {
184 at91_set_gpio_input(data->phy_irq_pin, 0);
185 at91_set_deglitch(data->phy_irq_pin, 1);
186 }
187
188 /* Pins used for MII and RMII */
189 at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */
190 at91_set_B_periph(AT91_PIN_PC25, 0); /* ERXDV */
191 at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */
192 at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */
193 at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */
194 at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */
195 at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */
196 at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */
197 at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */
198 at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */
199
200 if (!data->is_rmii) {
201 at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */
202 at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
203 at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
204 at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
205 at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
206 at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
207 at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
208 at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
209 }
210
211 eth_data = *data;
212 platform_device_register(&at91sam9263_eth_device);
213}
214#else
215void __init at91_add_device_eth(struct macb_platform_data *data) {}
216#endif
217
218
219/* --------------------------------------------------------------------
220 * MMC / SD
221 * -------------------------------------------------------------------- */
222
223#if IS_ENABLED(CONFIG_MMC_ATMELMCI)
224static u64 mmc_dmamask = DMA_BIT_MASK(32);
225static struct mci_platform_data mmc0_data, mmc1_data;
226
227static struct resource mmc0_resources[] = {
228 [0] = {
229 .start = AT91SAM9263_BASE_MCI0,
230 .end = AT91SAM9263_BASE_MCI0 + SZ_16K - 1,
231 .flags = IORESOURCE_MEM,
232 },
233 [1] = {
234 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI0,
235 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI0,
236 .flags = IORESOURCE_IRQ,
237 },
238};
239
240static struct platform_device at91sam9263_mmc0_device = {
241 .name = "atmel_mci",
242 .id = 0,
243 .dev = {
244 .dma_mask = &mmc_dmamask,
245 .coherent_dma_mask = DMA_BIT_MASK(32),
246 .platform_data = &mmc0_data,
247 },
248 .resource = mmc0_resources,
249 .num_resources = ARRAY_SIZE(mmc0_resources),
250};
251
252static struct resource mmc1_resources[] = {
253 [0] = {
254 .start = AT91SAM9263_BASE_MCI1,
255 .end = AT91SAM9263_BASE_MCI1 + SZ_16K - 1,
256 .flags = IORESOURCE_MEM,
257 },
258 [1] = {
259 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI1,
260 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI1,
261 .flags = IORESOURCE_IRQ,
262 },
263};
264
265static struct platform_device at91sam9263_mmc1_device = {
266 .name = "atmel_mci",
267 .id = 1,
268 .dev = {
269 .dma_mask = &mmc_dmamask,
270 .coherent_dma_mask = DMA_BIT_MASK(32),
271 .platform_data = &mmc1_data,
272 },
273 .resource = mmc1_resources,
274 .num_resources = ARRAY_SIZE(mmc1_resources),
275};
276
277void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
278{
279 unsigned int i;
280 unsigned int slot_count = 0;
281
282 if (!data)
283 return;
284
285 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
286
287 if (!data->slot[i].bus_width)
288 continue;
289
290 /* input/irq */
291 if (gpio_is_valid(data->slot[i].detect_pin)) {
292 at91_set_gpio_input(data->slot[i].detect_pin,
293 1);
294 at91_set_deglitch(data->slot[i].detect_pin,
295 1);
296 }
297 if (gpio_is_valid(data->slot[i].wp_pin))
298 at91_set_gpio_input(data->slot[i].wp_pin, 1);
299
300 if (mmc_id == 0) { /* MCI0 */
301 switch (i) {
302 case 0: /* slot A */
303 /* CMD */
304 at91_set_A_periph(AT91_PIN_PA1, 1);
305 /* DAT0, maybe DAT1..DAT3 */
306 at91_set_A_periph(AT91_PIN_PA0, 1);
307 if (data->slot[i].bus_width == 4) {
308 at91_set_A_periph(AT91_PIN_PA3, 1);
309 at91_set_A_periph(AT91_PIN_PA4, 1);
310 at91_set_A_periph(AT91_PIN_PA5, 1);
311 }
312 slot_count++;
313 break;
314 case 1: /* slot B */
315 /* CMD */
316 at91_set_A_periph(AT91_PIN_PA16, 1);
317 /* DAT0, maybe DAT1..DAT3 */
318 at91_set_A_periph(AT91_PIN_PA17, 1);
319 if (data->slot[i].bus_width == 4) {
320 at91_set_A_periph(AT91_PIN_PA18, 1);
321 at91_set_A_periph(AT91_PIN_PA19, 1);
322 at91_set_A_periph(AT91_PIN_PA20, 1);
323 }
324 slot_count++;
325 break;
326 default:
327 printk(KERN_ERR
328 "AT91: SD/MMC slot %d not available\n", i);
329 break;
330 }
331 if (slot_count) {
332 /* CLK */
333 at91_set_A_periph(AT91_PIN_PA12, 0);
334
335 mmc0_data = *data;
336 platform_device_register(&at91sam9263_mmc0_device);
337 }
338 } else if (mmc_id == 1) { /* MCI1 */
339 switch (i) {
340 case 0: /* slot A */
341 /* CMD */
342 at91_set_A_periph(AT91_PIN_PA7, 1);
343 /* DAT0, maybe DAT1..DAT3 */
344 at91_set_A_periph(AT91_PIN_PA8, 1);
345 if (data->slot[i].bus_width == 4) {
346 at91_set_A_periph(AT91_PIN_PA9, 1);
347 at91_set_A_periph(AT91_PIN_PA10, 1);
348 at91_set_A_periph(AT91_PIN_PA11, 1);
349 }
350 slot_count++;
351 break;
352 case 1: /* slot B */
353 /* CMD */
354 at91_set_A_periph(AT91_PIN_PA21, 1);
355 /* DAT0, maybe DAT1..DAT3 */
356 at91_set_A_periph(AT91_PIN_PA22, 1);
357 if (data->slot[i].bus_width == 4) {
358 at91_set_A_periph(AT91_PIN_PA23, 1);
359 at91_set_A_periph(AT91_PIN_PA24, 1);
360 at91_set_A_periph(AT91_PIN_PA25, 1);
361 }
362 slot_count++;
363 break;
364 default:
365 printk(KERN_ERR
366 "AT91: SD/MMC slot %d not available\n", i);
367 break;
368 }
369 if (slot_count) {
370 /* CLK */
371 at91_set_A_periph(AT91_PIN_PA6, 0);
372
373 mmc1_data = *data;
374 platform_device_register(&at91sam9263_mmc1_device);
375 }
376 }
377 }
378}
379#else
380void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
381#endif
382
383/* --------------------------------------------------------------------
384 * Compact Flash (PCMCIA or IDE)
385 * -------------------------------------------------------------------- */
386
387#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \
388 defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
389
390static struct at91_cf_data cf0_data;
391
392static struct resource cf0_resources[] = {
393 [0] = {
394 .start = AT91_CHIPSELECT_4,
395 .end = AT91_CHIPSELECT_4 + SZ_256M - 1,
396 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
397 }
398};
399
400static struct platform_device cf0_device = {
401 .id = 0,
402 .dev = {
403 .platform_data = &cf0_data,
404 },
405 .resource = cf0_resources,
406 .num_resources = ARRAY_SIZE(cf0_resources),
407};
408
409static struct at91_cf_data cf1_data;
410
411static struct resource cf1_resources[] = {
412 [0] = {
413 .start = AT91_CHIPSELECT_5,
414 .end = AT91_CHIPSELECT_5 + SZ_256M - 1,
415 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
416 }
417};
418
419static struct platform_device cf1_device = {
420 .id = 1,
421 .dev = {
422 .platform_data = &cf1_data,
423 },
424 .resource = cf1_resources,
425 .num_resources = ARRAY_SIZE(cf1_resources),
426};
427
428void __init at91_add_device_cf(struct at91_cf_data *data)
429{
430 unsigned long ebi0_csa;
431 struct platform_device *pdev;
432
433 if (!data)
434 return;
435
436 /*
437 * assign CS4 or CS5 to SMC with Compact Flash logic support,
438 * we assume SMC timings are configured by board code,
439 * except True IDE where timings are controlled by driver
440 */
441 ebi0_csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
442 switch (data->chipselect) {
443 case 4:
444 at91_set_A_periph(AT91_PIN_PD6, 0); /* EBI0_NCS4/CFCS0 */
445 ebi0_csa |= AT91_MATRIX_EBI0_CS4A_SMC_CF1;
446 cf0_data = *data;
447 pdev = &cf0_device;
448 break;
449 case 5:
450 at91_set_A_periph(AT91_PIN_PD7, 0); /* EBI0_NCS5/CFCS1 */
451 ebi0_csa |= AT91_MATRIX_EBI0_CS5A_SMC_CF2;
452 cf1_data = *data;
453 pdev = &cf1_device;
454 break;
455 default:
456 printk(KERN_ERR "AT91 CF: bad chip-select requested (%u)\n",
457 data->chipselect);
458 return;
459 }
460 at91_matrix_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
461
462 if (gpio_is_valid(data->det_pin)) {
463 at91_set_gpio_input(data->det_pin, 1);
464 at91_set_deglitch(data->det_pin, 1);
465 }
466
467 if (gpio_is_valid(data->irq_pin)) {
468 at91_set_gpio_input(data->irq_pin, 1);
469 at91_set_deglitch(data->irq_pin, 1);
470 }
471
472 if (gpio_is_valid(data->vcc_pin))
473 /* initially off */
474 at91_set_gpio_output(data->vcc_pin, 0);
475
476 /* enable EBI controlled pins */
477 at91_set_A_periph(AT91_PIN_PD5, 1); /* NWAIT */
478 at91_set_A_periph(AT91_PIN_PD8, 0); /* CFCE1 */
479 at91_set_A_periph(AT91_PIN_PD9, 0); /* CFCE2 */
480 at91_set_A_periph(AT91_PIN_PD14, 0); /* CFNRW */
481
482 pdev->name = (data->flags & AT91_CF_TRUE_IDE) ? "pata_at91" : "at91_cf";
483 platform_device_register(pdev);
484}
485#else
486void __init at91_add_device_cf(struct at91_cf_data *data) {}
487#endif
488
489/* --------------------------------------------------------------------
490 * NAND / SmartMedia
491 * -------------------------------------------------------------------- */
492
493#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
494static struct atmel_nand_data nand_data;
495
496#define NAND_BASE AT91_CHIPSELECT_3
497
498static struct resource nand_resources[] = {
499 [0] = {
500 .start = NAND_BASE,
501 .end = NAND_BASE + SZ_256M - 1,
502 .flags = IORESOURCE_MEM,
503 },
504 [1] = {
505 .start = AT91SAM9263_BASE_ECC0,
506 .end = AT91SAM9263_BASE_ECC0 + SZ_512 - 1,
507 .flags = IORESOURCE_MEM,
508 }
509};
510
511static struct platform_device at91sam9263_nand_device = {
512 .name = "atmel_nand",
513 .id = -1,
514 .dev = {
515 .platform_data = &nand_data,
516 },
517 .resource = nand_resources,
518 .num_resources = ARRAY_SIZE(nand_resources),
519};
520
521void __init at91_add_device_nand(struct atmel_nand_data *data)
522{
523 unsigned long csa;
524
525 if (!data)
526 return;
527
528 csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
529 at91_matrix_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
530
531 /* enable pin */
532 if (gpio_is_valid(data->enable_pin))
533 at91_set_gpio_output(data->enable_pin, 1);
534
535 /* ready/busy pin */
536 if (gpio_is_valid(data->rdy_pin))
537 at91_set_gpio_input(data->rdy_pin, 1);
538
539 /* card detect pin */
540 if (gpio_is_valid(data->det_pin))
541 at91_set_gpio_input(data->det_pin, 1);
542
543 nand_data = *data;
544 platform_device_register(&at91sam9263_nand_device);
545}
546#else
547void __init at91_add_device_nand(struct atmel_nand_data *data) {}
548#endif
549
550
551/* --------------------------------------------------------------------
552 * TWI (i2c)
553 * -------------------------------------------------------------------- */
554
555/*
556 * Prefer the GPIO code since the TWI controller isn't robust
557 * (gets overruns and underruns under load) and can only issue
558 * repeated STARTs in one scenario (the driver doesn't yet handle them).
559 */
560#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
561
562static struct i2c_gpio_platform_data pdata = {
563 .sda_pin = AT91_PIN_PB4,
564 .sda_is_open_drain = 1,
565 .scl_pin = AT91_PIN_PB5,
566 .scl_is_open_drain = 1,
567 .udelay = 2, /* ~100 kHz */
568};
569
570static struct platform_device at91sam9263_twi_device = {
571 .name = "i2c-gpio",
572 .id = 0,
573 .dev.platform_data = &pdata,
574};
575
576void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
577{
578 at91_set_GPIO_periph(AT91_PIN_PB4, 1); /* TWD (SDA) */
579 at91_set_multi_drive(AT91_PIN_PB4, 1);
580
581 at91_set_GPIO_periph(AT91_PIN_PB5, 1); /* TWCK (SCL) */
582 at91_set_multi_drive(AT91_PIN_PB5, 1);
583
584 i2c_register_board_info(0, devices, nr_devices);
585 platform_device_register(&at91sam9263_twi_device);
586}
587
588#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
589
590static struct resource twi_resources[] = {
591 [0] = {
592 .start = AT91SAM9263_BASE_TWI,
593 .end = AT91SAM9263_BASE_TWI + SZ_16K - 1,
594 .flags = IORESOURCE_MEM,
595 },
596 [1] = {
597 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_TWI,
598 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_TWI,
599 .flags = IORESOURCE_IRQ,
600 },
601};
602
603static struct platform_device at91sam9263_twi_device = {
604 .name = "i2c-at91sam9260",
605 .id = 0,
606 .resource = twi_resources,
607 .num_resources = ARRAY_SIZE(twi_resources),
608};
609
610void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
611{
612 /* pins used for TWI interface */
613 at91_set_A_periph(AT91_PIN_PB4, 0); /* TWD */
614 at91_set_multi_drive(AT91_PIN_PB4, 1);
615
616 at91_set_A_periph(AT91_PIN_PB5, 0); /* TWCK */
617 at91_set_multi_drive(AT91_PIN_PB5, 1);
618
619 i2c_register_board_info(0, devices, nr_devices);
620 platform_device_register(&at91sam9263_twi_device);
621}
622#else
623void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
624#endif
625
626
627/* --------------------------------------------------------------------
628 * SPI
629 * -------------------------------------------------------------------- */
630
631#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
632static u64 spi_dmamask = DMA_BIT_MASK(32);
633
634static struct resource spi0_resources[] = {
635 [0] = {
636 .start = AT91SAM9263_BASE_SPI0,
637 .end = AT91SAM9263_BASE_SPI0 + SZ_16K - 1,
638 .flags = IORESOURCE_MEM,
639 },
640 [1] = {
641 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI0,
642 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI0,
643 .flags = IORESOURCE_IRQ,
644 },
645};
646
647static struct platform_device at91sam9263_spi0_device = {
648 .name = "atmel_spi",
649 .id = 0,
650 .dev = {
651 .dma_mask = &spi_dmamask,
652 .coherent_dma_mask = DMA_BIT_MASK(32),
653 },
654 .resource = spi0_resources,
655 .num_resources = ARRAY_SIZE(spi0_resources),
656};
657
658static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA5, AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PB11 };
659
660static struct resource spi1_resources[] = {
661 [0] = {
662 .start = AT91SAM9263_BASE_SPI1,
663 .end = AT91SAM9263_BASE_SPI1 + SZ_16K - 1,
664 .flags = IORESOURCE_MEM,
665 },
666 [1] = {
667 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI1,
668 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI1,
669 .flags = IORESOURCE_IRQ,
670 },
671};
672
673static struct platform_device at91sam9263_spi1_device = {
674 .name = "atmel_spi",
675 .id = 1,
676 .dev = {
677 .dma_mask = &spi_dmamask,
678 .coherent_dma_mask = DMA_BIT_MASK(32),
679 },
680 .resource = spi1_resources,
681 .num_resources = ARRAY_SIZE(spi1_resources),
682};
683
684static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB15, AT91_PIN_PB16, AT91_PIN_PB17, AT91_PIN_PB18 };
685
686void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
687{
688 int i;
689 unsigned long cs_pin;
690 short enable_spi0 = 0;
691 short enable_spi1 = 0;
692
693 /* Choose SPI chip-selects */
694 for (i = 0; i < nr_devices; i++) {
695 if (devices[i].controller_data)
696 cs_pin = (unsigned long) devices[i].controller_data;
697 else if (devices[i].bus_num == 0)
698 cs_pin = spi0_standard_cs[devices[i].chip_select];
699 else
700 cs_pin = spi1_standard_cs[devices[i].chip_select];
701
702 if (!gpio_is_valid(cs_pin))
703 continue;
704
705 if (devices[i].bus_num == 0)
706 enable_spi0 = 1;
707 else
708 enable_spi1 = 1;
709
710 /* enable chip-select pin */
711 at91_set_gpio_output(cs_pin, 1);
712
713 /* pass chip-select pin to driver */
714 devices[i].controller_data = (void *) cs_pin;
715 }
716
717 spi_register_board_info(devices, nr_devices);
718
719 /* Configure SPI bus(es) */
720 if (enable_spi0) {
721 at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
722 at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
723 at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
724
725 platform_device_register(&at91sam9263_spi0_device);
726 }
727 if (enable_spi1) {
728 at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */
729 at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */
730 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */
731
732 platform_device_register(&at91sam9263_spi1_device);
733 }
734}
735#else
736void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
737#endif
738
739
740/* --------------------------------------------------------------------
741 * AC97
742 * -------------------------------------------------------------------- */
743
744#if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
745static u64 ac97_dmamask = DMA_BIT_MASK(32);
746static struct ac97c_platform_data ac97_data;
747
748static struct resource ac97_resources[] = {
749 [0] = {
750 .start = AT91SAM9263_BASE_AC97C,
751 .end = AT91SAM9263_BASE_AC97C + SZ_16K - 1,
752 .flags = IORESOURCE_MEM,
753 },
754 [1] = {
755 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_AC97C,
756 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_AC97C,
757 .flags = IORESOURCE_IRQ,
758 },
759};
760
761static struct platform_device at91sam9263_ac97_device = {
762 .name = "atmel_ac97c",
763 .id = 0,
764 .dev = {
765 .dma_mask = &ac97_dmamask,
766 .coherent_dma_mask = DMA_BIT_MASK(32),
767 .platform_data = &ac97_data,
768 },
769 .resource = ac97_resources,
770 .num_resources = ARRAY_SIZE(ac97_resources),
771};
772
773void __init at91_add_device_ac97(struct ac97c_platform_data *data)
774{
775 if (!data)
776 return;
777
778 at91_set_A_periph(AT91_PIN_PB0, 0); /* AC97FS */
779 at91_set_A_periph(AT91_PIN_PB1, 0); /* AC97CK */
780 at91_set_A_periph(AT91_PIN_PB2, 0); /* AC97TX */
781 at91_set_A_periph(AT91_PIN_PB3, 0); /* AC97RX */
782
783 /* reset */
784 if (gpio_is_valid(data->reset_pin))
785 at91_set_gpio_output(data->reset_pin, 0);
786
787 ac97_data = *data;
788 platform_device_register(&at91sam9263_ac97_device);
789}
790#else
791void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
792#endif
793
794/* --------------------------------------------------------------------
795 * CAN Controller
796 * -------------------------------------------------------------------- */
797
798#if defined(CONFIG_CAN_AT91) || defined(CONFIG_CAN_AT91_MODULE)
799static struct resource can_resources[] = {
800 [0] = {
801 .start = AT91SAM9263_BASE_CAN,
802 .end = AT91SAM9263_BASE_CAN + SZ_16K - 1,
803 .flags = IORESOURCE_MEM,
804 },
805 [1] = {
806 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_CAN,
807 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_CAN,
808 .flags = IORESOURCE_IRQ,
809 },
810};
811
812static struct platform_device at91sam9263_can_device = {
813 .name = "at91_can",
814 .id = -1,
815 .resource = can_resources,
816 .num_resources = ARRAY_SIZE(can_resources),
817};
818
819void __init at91_add_device_can(struct at91_can_data *data)
820{
821 at91_set_A_periph(AT91_PIN_PA13, 0); /* CANTX */
822 at91_set_A_periph(AT91_PIN_PA14, 0); /* CANRX */
823 at91sam9263_can_device.dev.platform_data = data;
824
825 platform_device_register(&at91sam9263_can_device);
826}
827#else
828void __init at91_add_device_can(struct at91_can_data *data) {}
829#endif
830
831/* --------------------------------------------------------------------
832 * LCD Controller
833 * -------------------------------------------------------------------- */
834
835#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
836static u64 lcdc_dmamask = DMA_BIT_MASK(32);
837static struct atmel_lcdfb_pdata lcdc_data;
838
839static struct resource lcdc_resources[] = {
840 [0] = {
841 .start = AT91SAM9263_LCDC_BASE,
842 .end = AT91SAM9263_LCDC_BASE + SZ_4K - 1,
843 .flags = IORESOURCE_MEM,
844 },
845 [1] = {
846 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_LCDC,
847 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_LCDC,
848 .flags = IORESOURCE_IRQ,
849 },
850};
851
852static struct platform_device at91_lcdc_device = {
853 .name = "at91sam9263-lcdfb",
854 .id = 0,
855 .dev = {
856 .dma_mask = &lcdc_dmamask,
857 .coherent_dma_mask = DMA_BIT_MASK(32),
858 .platform_data = &lcdc_data,
859 },
860 .resource = lcdc_resources,
861 .num_resources = ARRAY_SIZE(lcdc_resources),
862};
863
864void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data)
865{
866 if (!data)
867 return;
868
869 at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
870 at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
871 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
872 at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
873 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
874 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
875 at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
876 at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
877 at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
878 at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
879 at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
880 at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
881 at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
882 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */
883 at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
884 at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
885 at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
886 at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
887 at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
888 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */
889 at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
890 at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
891
892 lcdc_data = *data;
893 platform_device_register(&at91_lcdc_device);
894}
895#else
896void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) {}
897#endif
898
899
900/* --------------------------------------------------------------------
901 * Image Sensor Interface
902 * -------------------------------------------------------------------- */
903
904#if defined(CONFIG_VIDEO_AT91_ISI) || defined(CONFIG_VIDEO_AT91_ISI_MODULE)
905
906struct resource isi_resources[] = {
907 [0] = {
908 .start = AT91SAM9263_BASE_ISI,
909 .end = AT91SAM9263_BASE_ISI + SZ_16K - 1,
910 .flags = IORESOURCE_MEM,
911 },
912 [1] = {
913 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_ISI,
914 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_ISI,
915 .flags = IORESOURCE_IRQ,
916 },
917};
918
919static struct platform_device at91sam9263_isi_device = {
920 .name = "at91_isi",
921 .id = -1,
922 .resource = isi_resources,
923 .num_resources = ARRAY_SIZE(isi_resources),
924};
925
926void __init at91_add_device_isi(struct isi_platform_data *data,
927 bool use_pck_as_mck)
928{
929 at91_set_A_periph(AT91_PIN_PE0, 0); /* ISI_D0 */
930 at91_set_A_periph(AT91_PIN_PE1, 0); /* ISI_D1 */
931 at91_set_A_periph(AT91_PIN_PE2, 0); /* ISI_D2 */
932 at91_set_A_periph(AT91_PIN_PE3, 0); /* ISI_D3 */
933 at91_set_A_periph(AT91_PIN_PE4, 0); /* ISI_D4 */
934 at91_set_A_periph(AT91_PIN_PE5, 0); /* ISI_D5 */
935 at91_set_A_periph(AT91_PIN_PE6, 0); /* ISI_D6 */
936 at91_set_A_periph(AT91_PIN_PE7, 0); /* ISI_D7 */
937 at91_set_A_periph(AT91_PIN_PE8, 0); /* ISI_PCK */
938 at91_set_A_periph(AT91_PIN_PE9, 0); /* ISI_HSYNC */
939 at91_set_A_periph(AT91_PIN_PE10, 0); /* ISI_VSYNC */
940 at91_set_B_periph(AT91_PIN_PE12, 0); /* ISI_PD8 */
941 at91_set_B_periph(AT91_PIN_PE13, 0); /* ISI_PD9 */
942 at91_set_B_periph(AT91_PIN_PE14, 0); /* ISI_PD10 */
943 at91_set_B_periph(AT91_PIN_PE15, 0); /* ISI_PD11 */
944
945 if (use_pck_as_mck) {
946 at91_set_B_periph(AT91_PIN_PE11, 0); /* ISI_MCK (PCK3) */
947
948 /* TODO: register the PCK for ISI_MCK and set its parent */
949 }
950}
951#else
952void __init at91_add_device_isi(struct isi_platform_data *data,
953 bool use_pck_as_mck) {}
954#endif
955
956
957/* --------------------------------------------------------------------
958 * Timer/Counter block
959 * -------------------------------------------------------------------- */
960
961#ifdef CONFIG_ATMEL_TCLIB
962
963static struct resource tcb_resources[] = {
964 [0] = {
965 .start = AT91SAM9263_BASE_TCB0,
966 .end = AT91SAM9263_BASE_TCB0 + SZ_16K - 1,
967 .flags = IORESOURCE_MEM,
968 },
969 [1] = {
970 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_TCB,
971 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_TCB,
972 .flags = IORESOURCE_IRQ,
973 },
974};
975
976static struct platform_device at91sam9263_tcb_device = {
977 .name = "atmel_tcb",
978 .id = 0,
979 .resource = tcb_resources,
980 .num_resources = ARRAY_SIZE(tcb_resources),
981};
982
983#if defined(CONFIG_OF)
984static struct of_device_id tcb_ids[] = {
985 { .compatible = "atmel,at91rm9200-tcb" },
986 { /*sentinel*/ }
987};
988#endif
989
990static void __init at91_add_device_tc(void)
991{
992#if defined(CONFIG_OF)
993 struct device_node *np;
994
995 np = of_find_matching_node(NULL, tcb_ids);
996 if (np) {
997 of_node_put(np);
998 return;
999 }
1000#endif
1001
1002 platform_device_register(&at91sam9263_tcb_device);
1003}
1004#else
1005static void __init at91_add_device_tc(void) { }
1006#endif
1007
1008
1009/* --------------------------------------------------------------------
1010 * RTT
1011 * -------------------------------------------------------------------- */
1012
1013static struct resource rtt0_resources[] = {
1014 {
1015 .start = AT91SAM9263_BASE_RTT0,
1016 .end = AT91SAM9263_BASE_RTT0 + SZ_16 - 1,
1017 .flags = IORESOURCE_MEM,
1018 }, {
1019 .flags = IORESOURCE_MEM,
1020 }, {
1021 .flags = IORESOURCE_IRQ,
1022 }
1023};
1024
1025static struct platform_device at91sam9263_rtt0_device = {
1026 .name = "at91_rtt",
1027 .id = 0,
1028 .resource = rtt0_resources,
1029};
1030
1031static struct resource rtt1_resources[] = {
1032 {
1033 .start = AT91SAM9263_BASE_RTT1,
1034 .end = AT91SAM9263_BASE_RTT1 + SZ_16 - 1,
1035 .flags = IORESOURCE_MEM,
1036 }, {
1037 .flags = IORESOURCE_MEM,
1038 }, {
1039 .flags = IORESOURCE_IRQ,
1040 }
1041};
1042
1043static struct platform_device at91sam9263_rtt1_device = {
1044 .name = "at91_rtt",
1045 .id = 1,
1046 .resource = rtt1_resources,
1047};
1048
1049#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
1050static void __init at91_add_device_rtt_rtc(void)
1051{
1052 struct platform_device *pdev;
1053 struct resource *r;
1054
1055 switch (CONFIG_RTC_DRV_AT91SAM9_RTT) {
1056 case 0:
1057 /*
1058 * The second resource is needed only for the chosen RTT:
1059 * GPBR will serve as the storage for RTC time offset
1060 */
1061 at91sam9263_rtt0_device.num_resources = 3;
1062 at91sam9263_rtt1_device.num_resources = 1;
1063 pdev = &at91sam9263_rtt0_device;
1064 r = rtt0_resources;
1065 break;
1066 case 1:
1067 at91sam9263_rtt0_device.num_resources = 1;
1068 at91sam9263_rtt1_device.num_resources = 3;
1069 pdev = &at91sam9263_rtt1_device;
1070 r = rtt1_resources;
1071 break;
1072 default:
1073 pr_err("at91sam9263: only supports 2 RTT (%d)\n",
1074 CONFIG_RTC_DRV_AT91SAM9_RTT);
1075 return;
1076 }
1077
1078 pdev->name = "rtc-at91sam9";
1079 r[1].start = AT91SAM9263_BASE_GPBR + 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
1080 r[1].end = r[1].start + 3;
1081 r[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
1082 r[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
1083}
1084#else
1085static void __init at91_add_device_rtt_rtc(void)
1086{
1087 /* Only one resource is needed: RTT not used as RTC */
1088 at91sam9263_rtt0_device.num_resources = 1;
1089 at91sam9263_rtt1_device.num_resources = 1;
1090}
1091#endif
1092
1093static void __init at91_add_device_rtt(void)
1094{
1095 at91_add_device_rtt_rtc();
1096 platform_device_register(&at91sam9263_rtt0_device);
1097 platform_device_register(&at91sam9263_rtt1_device);
1098}
1099
1100
1101/* --------------------------------------------------------------------
1102 * Watchdog
1103 * -------------------------------------------------------------------- */
1104
1105#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
1106static struct resource wdt_resources[] = {
1107 {
1108 .start = AT91SAM9263_BASE_WDT,
1109 .end = AT91SAM9263_BASE_WDT + SZ_16 - 1,
1110 .flags = IORESOURCE_MEM,
1111 }
1112};
1113
1114static struct platform_device at91sam9263_wdt_device = {
1115 .name = "at91_wdt",
1116 .id = -1,
1117 .resource = wdt_resources,
1118 .num_resources = ARRAY_SIZE(wdt_resources),
1119};
1120
1121static void __init at91_add_device_watchdog(void)
1122{
1123 platform_device_register(&at91sam9263_wdt_device);
1124}
1125#else
1126static void __init at91_add_device_watchdog(void) {}
1127#endif
1128
1129
1130/* --------------------------------------------------------------------
1131 * PWM
1132 * --------------------------------------------------------------------*/
1133
1134#if IS_ENABLED(CONFIG_PWM_ATMEL)
1135static struct resource pwm_resources[] = {
1136 [0] = {
1137 .start = AT91SAM9263_BASE_PWMC,
1138 .end = AT91SAM9263_BASE_PWMC + SZ_16K - 1,
1139 .flags = IORESOURCE_MEM,
1140 },
1141 [1] = {
1142 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_PWMC,
1143 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_PWMC,
1144 .flags = IORESOURCE_IRQ,
1145 },
1146};
1147
1148static struct platform_device at91sam9263_pwm0_device = {
1149 .name = "at91sam9rl-pwm",
1150 .id = -1,
1151 .resource = pwm_resources,
1152 .num_resources = ARRAY_SIZE(pwm_resources),
1153};
1154
1155void __init at91_add_device_pwm(u32 mask)
1156{
1157 if (mask & (1 << AT91_PWM0))
1158 at91_set_B_periph(AT91_PIN_PB7, 1); /* enable PWM0 */
1159
1160 if (mask & (1 << AT91_PWM1))
1161 at91_set_B_periph(AT91_PIN_PB8, 1); /* enable PWM1 */
1162
1163 if (mask & (1 << AT91_PWM2))
1164 at91_set_B_periph(AT91_PIN_PC29, 1); /* enable PWM2 */
1165
1166 if (mask & (1 << AT91_PWM3))
1167 at91_set_B_periph(AT91_PIN_PB29, 1); /* enable PWM3 */
1168
1169 platform_device_register(&at91sam9263_pwm0_device);
1170}
1171#else
1172void __init at91_add_device_pwm(u32 mask) {}
1173#endif
1174
1175
1176/* --------------------------------------------------------------------
1177 * SSC -- Synchronous Serial Controller
1178 * -------------------------------------------------------------------- */
1179
1180#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
1181static u64 ssc0_dmamask = DMA_BIT_MASK(32);
1182
1183static struct resource ssc0_resources[] = {
1184 [0] = {
1185 .start = AT91SAM9263_BASE_SSC0,
1186 .end = AT91SAM9263_BASE_SSC0 + SZ_16K - 1,
1187 .flags = IORESOURCE_MEM,
1188 },
1189 [1] = {
1190 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC0,
1191 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC0,
1192 .flags = IORESOURCE_IRQ,
1193 },
1194};
1195
1196static struct platform_device at91sam9263_ssc0_device = {
1197 .name = "at91rm9200_ssc",
1198 .id = 0,
1199 .dev = {
1200 .dma_mask = &ssc0_dmamask,
1201 .coherent_dma_mask = DMA_BIT_MASK(32),
1202 },
1203 .resource = ssc0_resources,
1204 .num_resources = ARRAY_SIZE(ssc0_resources),
1205};
1206
1207static inline void configure_ssc0_pins(unsigned pins)
1208{
1209 if (pins & ATMEL_SSC_TF)
1210 at91_set_B_periph(AT91_PIN_PB0, 1);
1211 if (pins & ATMEL_SSC_TK)
1212 at91_set_B_periph(AT91_PIN_PB1, 1);
1213 if (pins & ATMEL_SSC_TD)
1214 at91_set_B_periph(AT91_PIN_PB2, 1);
1215 if (pins & ATMEL_SSC_RD)
1216 at91_set_B_periph(AT91_PIN_PB3, 1);
1217 if (pins & ATMEL_SSC_RK)
1218 at91_set_B_periph(AT91_PIN_PB4, 1);
1219 if (pins & ATMEL_SSC_RF)
1220 at91_set_B_periph(AT91_PIN_PB5, 1);
1221}
1222
1223static u64 ssc1_dmamask = DMA_BIT_MASK(32);
1224
1225static struct resource ssc1_resources[] = {
1226 [0] = {
1227 .start = AT91SAM9263_BASE_SSC1,
1228 .end = AT91SAM9263_BASE_SSC1 + SZ_16K - 1,
1229 .flags = IORESOURCE_MEM,
1230 },
1231 [1] = {
1232 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC1,
1233 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC1,
1234 .flags = IORESOURCE_IRQ,
1235 },
1236};
1237
1238static struct platform_device at91sam9263_ssc1_device = {
1239 .name = "at91rm9200_ssc",
1240 .id = 1,
1241 .dev = {
1242 .dma_mask = &ssc1_dmamask,
1243 .coherent_dma_mask = DMA_BIT_MASK(32),
1244 },
1245 .resource = ssc1_resources,
1246 .num_resources = ARRAY_SIZE(ssc1_resources),
1247};
1248
1249static inline void configure_ssc1_pins(unsigned pins)
1250{
1251 if (pins & ATMEL_SSC_TF)
1252 at91_set_A_periph(AT91_PIN_PB6, 1);
1253 if (pins & ATMEL_SSC_TK)
1254 at91_set_A_periph(AT91_PIN_PB7, 1);
1255 if (pins & ATMEL_SSC_TD)
1256 at91_set_A_periph(AT91_PIN_PB8, 1);
1257 if (pins & ATMEL_SSC_RD)
1258 at91_set_A_periph(AT91_PIN_PB9, 1);
1259 if (pins & ATMEL_SSC_RK)
1260 at91_set_A_periph(AT91_PIN_PB10, 1);
1261 if (pins & ATMEL_SSC_RF)
1262 at91_set_A_periph(AT91_PIN_PB11, 1);
1263}
1264
1265/*
1266 * SSC controllers are accessed through library code, instead of any
1267 * kind of all-singing/all-dancing driver. For example one could be
1268 * used by a particular I2S audio codec's driver, while another one
1269 * on the same system might be used by a custom data capture driver.
1270 */
1271void __init at91_add_device_ssc(unsigned id, unsigned pins)
1272{
1273 struct platform_device *pdev;
1274
1275 /*
1276 * NOTE: caller is responsible for passing information matching
1277 * "pins" to whatever will be using each particular controller.
1278 */
1279 switch (id) {
1280 case AT91SAM9263_ID_SSC0:
1281 pdev = &at91sam9263_ssc0_device;
1282 configure_ssc0_pins(pins);
1283 break;
1284 case AT91SAM9263_ID_SSC1:
1285 pdev = &at91sam9263_ssc1_device;
1286 configure_ssc1_pins(pins);
1287 break;
1288 default:
1289 return;
1290 }
1291
1292 platform_device_register(pdev);
1293}
1294
1295#else
1296void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1297#endif
1298
1299
1300/* --------------------------------------------------------------------
1301 * UART
1302 * -------------------------------------------------------------------- */
1303
1304#if defined(CONFIG_SERIAL_ATMEL)
1305
1306static struct resource dbgu_resources[] = {
1307 [0] = {
1308 .start = AT91SAM9263_BASE_DBGU,
1309 .end = AT91SAM9263_BASE_DBGU + SZ_512 - 1,
1310 .flags = IORESOURCE_MEM,
1311 },
1312 [1] = {
1313 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
1314 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
1315 .flags = IORESOURCE_IRQ,
1316 },
1317};
1318
1319static struct atmel_uart_data dbgu_data = {
1320 .use_dma_tx = 0,
1321 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
1322};
1323
1324static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1325
1326static struct platform_device at91sam9263_dbgu_device = {
1327 .name = "atmel_usart",
1328 .id = 0,
1329 .dev = {
1330 .dma_mask = &dbgu_dmamask,
1331 .coherent_dma_mask = DMA_BIT_MASK(32),
1332 .platform_data = &dbgu_data,
1333 },
1334 .resource = dbgu_resources,
1335 .num_resources = ARRAY_SIZE(dbgu_resources),
1336};
1337
1338static inline void configure_dbgu_pins(void)
1339{
1340 at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
1341 at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
1342}
1343
1344static struct resource uart0_resources[] = {
1345 [0] = {
1346 .start = AT91SAM9263_BASE_US0,
1347 .end = AT91SAM9263_BASE_US0 + SZ_16K - 1,
1348 .flags = IORESOURCE_MEM,
1349 },
1350 [1] = {
1351 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_US0,
1352 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_US0,
1353 .flags = IORESOURCE_IRQ,
1354 },
1355};
1356
1357static struct atmel_uart_data uart0_data = {
1358 .use_dma_tx = 1,
1359 .use_dma_rx = 1,
1360};
1361
1362static u64 uart0_dmamask = DMA_BIT_MASK(32);
1363
1364static struct platform_device at91sam9263_uart0_device = {
1365 .name = "atmel_usart",
1366 .id = 1,
1367 .dev = {
1368 .dma_mask = &uart0_dmamask,
1369 .coherent_dma_mask = DMA_BIT_MASK(32),
1370 .platform_data = &uart0_data,
1371 },
1372 .resource = uart0_resources,
1373 .num_resources = ARRAY_SIZE(uart0_resources),
1374};
1375
1376static inline void configure_usart0_pins(unsigned pins)
1377{
1378 at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */
1379 at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */
1380
1381 if (pins & ATMEL_UART_RTS)
1382 at91_set_A_periph(AT91_PIN_PA28, 0); /* RTS0 */
1383 if (pins & ATMEL_UART_CTS)
1384 at91_set_A_periph(AT91_PIN_PA29, 0); /* CTS0 */
1385}
1386
1387static struct resource uart1_resources[] = {
1388 [0] = {
1389 .start = AT91SAM9263_BASE_US1,
1390 .end = AT91SAM9263_BASE_US1 + SZ_16K - 1,
1391 .flags = IORESOURCE_MEM,
1392 },
1393 [1] = {
1394 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_US1,
1395 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_US1,
1396 .flags = IORESOURCE_IRQ,
1397 },
1398};
1399
1400static struct atmel_uart_data uart1_data = {
1401 .use_dma_tx = 1,
1402 .use_dma_rx = 1,
1403};
1404
1405static u64 uart1_dmamask = DMA_BIT_MASK(32);
1406
1407static struct platform_device at91sam9263_uart1_device = {
1408 .name = "atmel_usart",
1409 .id = 2,
1410 .dev = {
1411 .dma_mask = &uart1_dmamask,
1412 .coherent_dma_mask = DMA_BIT_MASK(32),
1413 .platform_data = &uart1_data,
1414 },
1415 .resource = uart1_resources,
1416 .num_resources = ARRAY_SIZE(uart1_resources),
1417};
1418
1419static inline void configure_usart1_pins(unsigned pins)
1420{
1421 at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
1422 at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
1423
1424 if (pins & ATMEL_UART_RTS)
1425 at91_set_B_periph(AT91_PIN_PD7, 0); /* RTS1 */
1426 if (pins & ATMEL_UART_CTS)
1427 at91_set_B_periph(AT91_PIN_PD8, 0); /* CTS1 */
1428}
1429
1430static struct resource uart2_resources[] = {
1431 [0] = {
1432 .start = AT91SAM9263_BASE_US2,
1433 .end = AT91SAM9263_BASE_US2 + SZ_16K - 1,
1434 .flags = IORESOURCE_MEM,
1435 },
1436 [1] = {
1437 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_US2,
1438 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_US2,
1439 .flags = IORESOURCE_IRQ,
1440 },
1441};
1442
1443static struct atmel_uart_data uart2_data = {
1444 .use_dma_tx = 1,
1445 .use_dma_rx = 1,
1446};
1447
1448static u64 uart2_dmamask = DMA_BIT_MASK(32);
1449
1450static struct platform_device at91sam9263_uart2_device = {
1451 .name = "atmel_usart",
1452 .id = 3,
1453 .dev = {
1454 .dma_mask = &uart2_dmamask,
1455 .coherent_dma_mask = DMA_BIT_MASK(32),
1456 .platform_data = &uart2_data,
1457 },
1458 .resource = uart2_resources,
1459 .num_resources = ARRAY_SIZE(uart2_resources),
1460};
1461
1462static inline void configure_usart2_pins(unsigned pins)
1463{
1464 at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
1465 at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
1466
1467 if (pins & ATMEL_UART_RTS)
1468 at91_set_B_periph(AT91_PIN_PD5, 0); /* RTS2 */
1469 if (pins & ATMEL_UART_CTS)
1470 at91_set_B_periph(AT91_PIN_PD6, 0); /* CTS2 */
1471}
1472
1473static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1474
1475void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1476{
1477 struct platform_device *pdev;
1478 struct atmel_uart_data *pdata;
1479
1480 switch (id) {
1481 case 0: /* DBGU */
1482 pdev = &at91sam9263_dbgu_device;
1483 configure_dbgu_pins();
1484 break;
1485 case AT91SAM9263_ID_US0:
1486 pdev = &at91sam9263_uart0_device;
1487 configure_usart0_pins(pins);
1488 break;
1489 case AT91SAM9263_ID_US1:
1490 pdev = &at91sam9263_uart1_device;
1491 configure_usart1_pins(pins);
1492 break;
1493 case AT91SAM9263_ID_US2:
1494 pdev = &at91sam9263_uart2_device;
1495 configure_usart2_pins(pins);
1496 break;
1497 default:
1498 return;
1499 }
1500 pdata = pdev->dev.platform_data;
1501 pdata->num = portnr; /* update to mapped ID */
1502
1503 if (portnr < ATMEL_MAX_UART)
1504 at91_uarts[portnr] = pdev;
1505}
1506
1507void __init at91_add_device_serial(void)
1508{
1509 int i;
1510
1511 for (i = 0; i < ATMEL_MAX_UART; i++) {
1512 if (at91_uarts[i])
1513 platform_device_register(at91_uarts[i]);
1514 }
1515}
1516#else
1517void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1518void __init at91_add_device_serial(void) {}
1519#endif
1520
1521
1522/* -------------------------------------------------------------------- */
1523/*
1524 * These devices are always present and don't need any board-specific
1525 * setup.
1526 */
1527static int __init at91_add_standard_devices(void)
1528{
1529 if (of_have_populated_dt())
1530 return 0;
1531
1532 at91_add_device_rtt();
1533 at91_add_device_watchdog();
1534 at91_add_device_tc();
1535 return 0;
1536}
1537
1538arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 405427ec05f8..3d225105e0d1 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -10,356 +10,11 @@
10 * 10 *
11 */ 11 */
12 12
13#include <linux/module.h>
14#include <linux/dma-mapping.h>
15#include <linux/clk/at91_pmc.h>
16#include <linux/platform_device.h>
17
18#include <asm/irq.h>
19#include <asm/mach/arch.h>
20#include <asm/mach/map.h>
21#include <asm/system_misc.h> 13#include <asm/system_misc.h>
22#include <mach/at91sam9g45.h>
23#include <mach/cpu.h>
24#include <mach/hardware.h> 14#include <mach/hardware.h>
25 15
26#include "at91_aic.h"
27#include "soc.h" 16#include "soc.h"
28#include "generic.h" 17#include "generic.h"
29#include "sam9_smc.h"
30#include "pm.h"
31
32#if defined(CONFIG_OLD_CLK_AT91)
33#include "clock.h"
34/* --------------------------------------------------------------------
35 * Clocks
36 * -------------------------------------------------------------------- */
37
38/*
39 * The peripheral clocks.
40 */
41static struct clk pioA_clk = {
42 .name = "pioA_clk",
43 .pmc_mask = 1 << AT91SAM9G45_ID_PIOA,
44 .type = CLK_TYPE_PERIPHERAL,
45};
46static struct clk pioB_clk = {
47 .name = "pioB_clk",
48 .pmc_mask = 1 << AT91SAM9G45_ID_PIOB,
49 .type = CLK_TYPE_PERIPHERAL,
50};
51static struct clk pioC_clk = {
52 .name = "pioC_clk",
53 .pmc_mask = 1 << AT91SAM9G45_ID_PIOC,
54 .type = CLK_TYPE_PERIPHERAL,
55};
56static struct clk pioDE_clk = {
57 .name = "pioDE_clk",
58 .pmc_mask = 1 << AT91SAM9G45_ID_PIODE,
59 .type = CLK_TYPE_PERIPHERAL,
60};
61static struct clk trng_clk = {
62 .name = "trng_clk",
63 .pmc_mask = 1 << AT91SAM9G45_ID_TRNG,
64 .type = CLK_TYPE_PERIPHERAL,
65};
66static struct clk usart0_clk = {
67 .name = "usart0_clk",
68 .pmc_mask = 1 << AT91SAM9G45_ID_US0,
69 .type = CLK_TYPE_PERIPHERAL,
70};
71static struct clk usart1_clk = {
72 .name = "usart1_clk",
73 .pmc_mask = 1 << AT91SAM9G45_ID_US1,
74 .type = CLK_TYPE_PERIPHERAL,
75};
76static struct clk usart2_clk = {
77 .name = "usart2_clk",
78 .pmc_mask = 1 << AT91SAM9G45_ID_US2,
79 .type = CLK_TYPE_PERIPHERAL,
80};
81static struct clk usart3_clk = {
82 .name = "usart3_clk",
83 .pmc_mask = 1 << AT91SAM9G45_ID_US3,
84 .type = CLK_TYPE_PERIPHERAL,
85};
86static struct clk mmc0_clk = {
87 .name = "mci0_clk",
88 .pmc_mask = 1 << AT91SAM9G45_ID_MCI0,
89 .type = CLK_TYPE_PERIPHERAL,
90};
91static struct clk twi0_clk = {
92 .name = "twi0_clk",
93 .pmc_mask = 1 << AT91SAM9G45_ID_TWI0,
94 .type = CLK_TYPE_PERIPHERAL,
95};
96static struct clk twi1_clk = {
97 .name = "twi1_clk",
98 .pmc_mask = 1 << AT91SAM9G45_ID_TWI1,
99 .type = CLK_TYPE_PERIPHERAL,
100};
101static struct clk spi0_clk = {
102 .name = "spi0_clk",
103 .pmc_mask = 1 << AT91SAM9G45_ID_SPI0,
104 .type = CLK_TYPE_PERIPHERAL,
105};
106static struct clk spi1_clk = {
107 .name = "spi1_clk",
108 .pmc_mask = 1 << AT91SAM9G45_ID_SPI1,
109 .type = CLK_TYPE_PERIPHERAL,
110};
111static struct clk ssc0_clk = {
112 .name = "ssc0_clk",
113 .pmc_mask = 1 << AT91SAM9G45_ID_SSC0,
114 .type = CLK_TYPE_PERIPHERAL,
115};
116static struct clk ssc1_clk = {
117 .name = "ssc1_clk",
118 .pmc_mask = 1 << AT91SAM9G45_ID_SSC1,
119 .type = CLK_TYPE_PERIPHERAL,
120};
121static struct clk tcb0_clk = {
122 .name = "tcb0_clk",
123 .pmc_mask = 1 << AT91SAM9G45_ID_TCB,
124 .type = CLK_TYPE_PERIPHERAL,
125};
126static struct clk pwm_clk = {
127 .name = "pwm_clk",
128 .pmc_mask = 1 << AT91SAM9G45_ID_PWMC,
129 .type = CLK_TYPE_PERIPHERAL,
130};
131static struct clk tsc_clk = {
132 .name = "tsc_clk",
133 .pmc_mask = 1 << AT91SAM9G45_ID_TSC,
134 .type = CLK_TYPE_PERIPHERAL,
135};
136static struct clk dma_clk = {
137 .name = "dma_clk",
138 .pmc_mask = 1 << AT91SAM9G45_ID_DMA,
139 .type = CLK_TYPE_PERIPHERAL,
140};
141static struct clk uhphs_clk = {
142 .name = "uhphs_clk",
143 .pmc_mask = 1 << AT91SAM9G45_ID_UHPHS,
144 .type = CLK_TYPE_PERIPHERAL,
145};
146static struct clk lcdc_clk = {
147 .name = "lcdc_clk",
148 .pmc_mask = 1 << AT91SAM9G45_ID_LCDC,
149 .type = CLK_TYPE_PERIPHERAL,
150};
151static struct clk ac97_clk = {
152 .name = "ac97_clk",
153 .pmc_mask = 1 << AT91SAM9G45_ID_AC97C,
154 .type = CLK_TYPE_PERIPHERAL,
155};
156static struct clk macb_clk = {
157 .name = "pclk",
158 .pmc_mask = 1 << AT91SAM9G45_ID_EMAC,
159 .type = CLK_TYPE_PERIPHERAL,
160};
161static struct clk isi_clk = {
162 .name = "isi_clk",
163 .pmc_mask = 1 << AT91SAM9G45_ID_ISI,
164 .type = CLK_TYPE_PERIPHERAL,
165};
166static struct clk udphs_clk = {
167 .name = "udphs_clk",
168 .pmc_mask = 1 << AT91SAM9G45_ID_UDPHS,
169 .type = CLK_TYPE_PERIPHERAL,
170};
171static struct clk mmc1_clk = {
172 .name = "mci1_clk",
173 .pmc_mask = 1 << AT91SAM9G45_ID_MCI1,
174 .type = CLK_TYPE_PERIPHERAL,
175};
176
177/* Video decoder clock - Only for sam9m10/sam9m11 */
178static struct clk vdec_clk = {
179 .name = "vdec_clk",
180 .pmc_mask = 1 << AT91SAM9G45_ID_VDEC,
181 .type = CLK_TYPE_PERIPHERAL,
182};
183
184static struct clk adc_op_clk = {
185 .name = "adc_op_clk",
186 .type = CLK_TYPE_PERIPHERAL,
187 .rate_hz = 300000,
188};
189
190/* AES/TDES/SHA clock - Only for sam9m11/sam9g56 */
191static struct clk aestdessha_clk = {
192 .name = "aestdessha_clk",
193 .pmc_mask = 1 << AT91SAM9G45_ID_AESTDESSHA,
194 .type = CLK_TYPE_PERIPHERAL,
195};
196
197static struct clk *periph_clocks[] __initdata = {
198 &pioA_clk,
199 &pioB_clk,
200 &pioC_clk,
201 &pioDE_clk,
202 &trng_clk,
203 &usart0_clk,
204 &usart1_clk,
205 &usart2_clk,
206 &usart3_clk,
207 &mmc0_clk,
208 &twi0_clk,
209 &twi1_clk,
210 &spi0_clk,
211 &spi1_clk,
212 &ssc0_clk,
213 &ssc1_clk,
214 &tcb0_clk,
215 &pwm_clk,
216 &tsc_clk,
217 &dma_clk,
218 &uhphs_clk,
219 &lcdc_clk,
220 &ac97_clk,
221 &macb_clk,
222 &isi_clk,
223 &udphs_clk,
224 &mmc1_clk,
225 &adc_op_clk,
226 &aestdessha_clk,
227 // irq0
228};
229
230static struct clk_lookup periph_clocks_lookups[] = {
231 /* One additional fake clock for macb_hclk */
232 CLKDEV_CON_ID("hclk", &macb_clk),
233 /* One additional fake clock for ohci */
234 CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
235 CLKDEV_CON_DEV_ID("hclk", "at91sam9g45-lcdfb.0", &lcdc_clk),
236 CLKDEV_CON_DEV_ID("hclk", "at91sam9g45es-lcdfb.0", &lcdc_clk),
237 CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
238 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
239 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
240 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
241 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
242 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
243 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
244 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
245 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
246 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi0_clk),
247 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.1", &twi1_clk),
248 CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.0", &ssc0_clk),
249 CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.1", &ssc1_clk),
250 CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc0_clk),
251 CLKDEV_CON_DEV_ID("pclk", "fffa0000.ssc", &ssc1_clk),
252 CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
253 CLKDEV_CON_DEV_ID(NULL, "atmel_sha", &aestdessha_clk),
254 CLKDEV_CON_DEV_ID(NULL, "atmel_tdes", &aestdessha_clk),
255 CLKDEV_CON_DEV_ID(NULL, "atmel_aes", &aestdessha_clk),
256 CLKDEV_CON_DEV_ID(NULL, "at91sam9rl-pwm", &pwm_clk),
257 /* more usart lookup table for DT entries */
258 CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
259 CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
260 CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
261 CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
262 CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
263 /* more tc lookup table for DT entries */
264 CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb0_clk),
265 CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
266 CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
267 CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
268 CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
269 CLKDEV_CON_DEV_ID("mci_clk", "fffd0000.mmc", &mmc1_clk),
270 CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
271 CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
272 CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
273 CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
274 CLKDEV_CON_DEV_ID("hclk", "600000.gadget", &utmi_clk),
275 CLKDEV_CON_DEV_ID("pclk", "600000.gadget", &udphs_clk),
276 /* fake hclk clock */
277 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
278 CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
279 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
280 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
281 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioDE_clk),
282 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioDE_clk),
283
284 CLKDEV_CON_ID("pioA", &pioA_clk),
285 CLKDEV_CON_ID("pioB", &pioB_clk),
286 CLKDEV_CON_ID("pioC", &pioC_clk),
287 CLKDEV_CON_ID("pioD", &pioDE_clk),
288 CLKDEV_CON_ID("pioE", &pioDE_clk),
289 /* Fake adc clock */
290 CLKDEV_CON_ID("adc_clk", &tsc_clk),
291 CLKDEV_CON_DEV_ID(NULL, "fffb8000.pwm", &pwm_clk),
292};
293
294static struct clk_lookup usart_clocks_lookups[] = {
295 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
296 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
297 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
298 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
299 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
300};
301
302/*
303 * The two programmable clocks.
304 * You must configure pin multiplexing to bring these signals out.
305 */
306static struct clk pck0 = {
307 .name = "pck0",
308 .pmc_mask = AT91_PMC_PCK0,
309 .type = CLK_TYPE_PROGRAMMABLE,
310 .id = 0,
311};
312static struct clk pck1 = {
313 .name = "pck1",
314 .pmc_mask = AT91_PMC_PCK1,
315 .type = CLK_TYPE_PROGRAMMABLE,
316 .id = 1,
317};
318
319static void __init at91sam9g45_register_clocks(void)
320{
321 int i;
322
323 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
324 clk_register(periph_clocks[i]);
325
326 clkdev_add_table(periph_clocks_lookups,
327 ARRAY_SIZE(periph_clocks_lookups));
328 clkdev_add_table(usart_clocks_lookups,
329 ARRAY_SIZE(usart_clocks_lookups));
330
331 if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
332 clk_register(&vdec_clk);
333
334 clk_register(&pck0);
335 clk_register(&pck1);
336}
337#else
338#define at91sam9g45_register_clocks NULL
339#endif
340
341/* --------------------------------------------------------------------
342 * GPIO
343 * -------------------------------------------------------------------- */
344
345static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
346 {
347 .id = AT91SAM9G45_ID_PIOA,
348 .regbase = AT91SAM9G45_BASE_PIOA,
349 }, {
350 .id = AT91SAM9G45_ID_PIOB,
351 .regbase = AT91SAM9G45_BASE_PIOB,
352 }, {
353 .id = AT91SAM9G45_ID_PIOC,
354 .regbase = AT91SAM9G45_BASE_PIOC,
355 }, {
356 .id = AT91SAM9G45_ID_PIODE,
357 .regbase = AT91SAM9G45_BASE_PIOD,
358 }, {
359 .id = AT91SAM9G45_ID_PIODE,
360 .regbase = AT91SAM9G45_BASE_PIOE,
361 }
362};
363 18
364/* -------------------------------------------------------------------- 19/* --------------------------------------------------------------------
365 * AT91SAM9G45 processor initialization 20 * AT91SAM9G45 processor initialization
@@ -370,125 +25,15 @@ static void __init at91sam9g45_map_io(void)
370 at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE); 25 at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE);
371} 26}
372 27
373static void __init at91sam9g45_ioremap_registers(void)
374{
375 at91_ioremap_ramc(0, AT91SAM9G45_BASE_DDRSDRC1, 512);
376 at91_ioremap_ramc(1, AT91SAM9G45_BASE_DDRSDRC0, 512);
377 at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
378 at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
379 at91_ioremap_matrix(AT91SAM9G45_BASE_MATRIX);
380 at91_pm_set_standby(at91_ddr_standby);
381}
382
383static void __init at91sam9g45_initialize(void) 28static void __init at91sam9g45_initialize(void)
384{ 29{
385 arm_pm_idle = at91sam9_idle; 30 arm_pm_idle = at91sam9_idle;
386 31
387 at91_sysirq_mask_rtc(AT91SAM9G45_BASE_RTC); 32 at91_sysirq_mask_rtc(AT91SAM9G45_BASE_RTC);
388 at91_sysirq_mask_rtt(AT91SAM9G45_BASE_RTT); 33 at91_sysirq_mask_rtt(AT91SAM9G45_BASE_RTT);
389
390 /* Register GPIO subsystem */
391 at91_gpio_init(at91sam9g45_gpio, 5);
392}
393
394static struct resource rstc_resources[] = {
395 [0] = {
396 .start = AT91SAM9G45_BASE_RSTC,
397 .end = AT91SAM9G45_BASE_RSTC + SZ_16 - 1,
398 .flags = IORESOURCE_MEM,
399 },
400 [1] = {
401 .start = AT91SAM9G45_BASE_DDRSDRC1,
402 .end = AT91SAM9G45_BASE_DDRSDRC1 + SZ_512 - 1,
403 .flags = IORESOURCE_MEM,
404 },
405 [2] = {
406 .start = AT91SAM9G45_BASE_DDRSDRC0,
407 .end = AT91SAM9G45_BASE_DDRSDRC0 + SZ_512 - 1,
408 .flags = IORESOURCE_MEM,
409 },
410};
411
412static struct platform_device rstc_device = {
413 .name = "at91-sam9g45-reset",
414 .resource = rstc_resources,
415 .num_resources = ARRAY_SIZE(rstc_resources),
416};
417
418static struct resource shdwc_resources[] = {
419 [0] = {
420 .start = AT91SAM9G45_BASE_SHDWC,
421 .end = AT91SAM9G45_BASE_SHDWC + SZ_16 - 1,
422 .flags = IORESOURCE_MEM,
423 },
424};
425
426static struct platform_device shdwc_device = {
427 .name = "at91-poweroff",
428 .resource = shdwc_resources,
429 .num_resources = ARRAY_SIZE(shdwc_resources),
430};
431
432static void __init at91sam9g45_register_devices(void)
433{
434 platform_device_register(&rstc_device);
435 platform_device_register(&shdwc_device);
436}
437
438/* --------------------------------------------------------------------
439 * Interrupt initialization
440 * -------------------------------------------------------------------- */
441
442/*
443 * The default interrupt priority levels (0 = lowest, 7 = highest).
444 */
445static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
446 7, /* Advanced Interrupt Controller (FIQ) */
447 7, /* System Peripherals */
448 1, /* Parallel IO Controller A */
449 1, /* Parallel IO Controller B */
450 1, /* Parallel IO Controller C */
451 1, /* Parallel IO Controller D and E */
452 0,
453 5, /* USART 0 */
454 5, /* USART 1 */
455 5, /* USART 2 */
456 5, /* USART 3 */
457 0, /* Multimedia Card Interface 0 */
458 6, /* Two-Wire Interface 0 */
459 6, /* Two-Wire Interface 1 */
460 5, /* Serial Peripheral Interface 0 */
461 5, /* Serial Peripheral Interface 1 */
462 4, /* Serial Synchronous Controller 0 */
463 4, /* Serial Synchronous Controller 1 */
464 0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
465 0, /* Pulse Width Modulation Controller */
466 0, /* Touch Screen Controller */
467 0, /* DMA Controller */
468 2, /* USB Host High Speed port */
469 3, /* LDC Controller */
470 5, /* AC97 Controller */
471 3, /* Ethernet */
472 0, /* Image Sensor Interface */
473 2, /* USB Device High speed port */
474 0, /* AESTDESSHA Crypto HW Accelerators */
475 0, /* Multimedia Card Interface 1 */
476 0,
477 0, /* Advanced Interrupt Controller (IRQ0) */
478};
479
480static void __init at91sam9g45_init_time(void)
481{
482 at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS);
483} 34}
484 35
485AT91_SOC_START(at91sam9g45) 36AT91_SOC_START(at91sam9g45)
486 .map_io = at91sam9g45_map_io, 37 .map_io = at91sam9g45_map_io,
487 .default_irq_priority = at91sam9g45_default_irq_priority,
488 .extern_irq = (1 << AT91SAM9G45_ID_IRQ0),
489 .ioremap_registers = at91sam9g45_ioremap_registers,
490 .register_clocks = at91sam9g45_register_clocks,
491 .register_devices = at91sam9g45_register_devices,
492 .init = at91sam9g45_initialize, 38 .init = at91sam9g45_initialize,
493 .init_time = at91sam9g45_init_time,
494AT91_SOC_END 39AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
deleted file mode 100644
index 06ecbafd01ee..000000000000
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ /dev/null
@@ -1,1915 +0,0 @@
1/*
2 * On-Chip devices setup code for the AT91SAM9G45 family
3 *
4 * Copyright (C) 2009 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12#include <asm/mach/arch.h>
13#include <asm/mach/map.h>
14
15#include <linux/dma-mapping.h>
16#include <linux/gpio.h>
17#include <linux/clk.h>
18#include <linux/platform_device.h>
19#include <linux/i2c-gpio.h>
20#include <linux/atmel-mci.h>
21#include <linux/platform_data/crypto-atmel.h>
22#include <linux/platform_data/mmc-atmel-mci.h>
23
24#include <linux/platform_data/at91_adc.h>
25
26#include <linux/fb.h>
27#include <video/atmel_lcdc.h>
28
29#include <mach/at91sam9g45.h>
30#include <mach/at91sam9g45_matrix.h>
31#include <mach/at91_matrix.h>
32#include <mach/at91sam9_smc.h>
33#include <linux/platform_data/dma-atmel.h>
34#include <mach/hardware.h>
35
36#include <media/atmel-isi.h>
37
38#include "board.h"
39#include "generic.h"
40#include "clock.h"
41#include "gpio.h"
42
43
44/* --------------------------------------------------------------------
45 * HDMAC - AHB DMA Controller
46 * -------------------------------------------------------------------- */
47
48#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
49static u64 hdmac_dmamask = DMA_BIT_MASK(32);
50
51static struct resource hdmac_resources[] = {
52 [0] = {
53 .start = AT91SAM9G45_BASE_DMA,
54 .end = AT91SAM9G45_BASE_DMA + SZ_512 - 1,
55 .flags = IORESOURCE_MEM,
56 },
57 [1] = {
58 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_DMA,
59 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_DMA,
60 .flags = IORESOURCE_IRQ,
61 },
62};
63
64static struct platform_device at_hdmac_device = {
65 .name = "at91sam9g45_dma",
66 .id = -1,
67 .dev = {
68 .dma_mask = &hdmac_dmamask,
69 .coherent_dma_mask = DMA_BIT_MASK(32),
70 },
71 .resource = hdmac_resources,
72 .num_resources = ARRAY_SIZE(hdmac_resources),
73};
74
75void __init at91_add_device_hdmac(void)
76{
77 platform_device_register(&at_hdmac_device);
78}
79#else
80void __init at91_add_device_hdmac(void) {}
81#endif
82
83
84/* --------------------------------------------------------------------
85 * USB Host (OHCI)
86 * -------------------------------------------------------------------- */
87
88#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
89static u64 ohci_dmamask = DMA_BIT_MASK(32);
90static struct at91_usbh_data usbh_ohci_data;
91
92static struct resource usbh_ohci_resources[] = {
93 [0] = {
94 .start = AT91SAM9G45_OHCI_BASE,
95 .end = AT91SAM9G45_OHCI_BASE + SZ_1M - 1,
96 .flags = IORESOURCE_MEM,
97 },
98 [1] = {
99 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
100 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
101 .flags = IORESOURCE_IRQ,
102 },
103};
104
105static struct platform_device at91_usbh_ohci_device = {
106 .name = "at91_ohci",
107 .id = -1,
108 .dev = {
109 .dma_mask = &ohci_dmamask,
110 .coherent_dma_mask = DMA_BIT_MASK(32),
111 .platform_data = &usbh_ohci_data,
112 },
113 .resource = usbh_ohci_resources,
114 .num_resources = ARRAY_SIZE(usbh_ohci_resources),
115};
116
117void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
118{
119 int i;
120
121 if (!data)
122 return;
123
124 /* Enable VBus control for UHP ports */
125 for (i = 0; i < data->ports; i++) {
126 if (gpio_is_valid(data->vbus_pin[i]))
127 at91_set_gpio_output(data->vbus_pin[i],
128 data->vbus_pin_active_low[i]);
129 }
130
131 /* Enable overcurrent notification */
132 for (i = 0; i < data->ports; i++) {
133 if (gpio_is_valid(data->overcurrent_pin[i]))
134 at91_set_gpio_input(data->overcurrent_pin[i], 1);
135 }
136
137 usbh_ohci_data = *data;
138 platform_device_register(&at91_usbh_ohci_device);
139}
140#else
141void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
142#endif
143
144
145/* --------------------------------------------------------------------
146 * USB Host HS (EHCI)
147 * Needs an OHCI host for low and full speed management
148 * -------------------------------------------------------------------- */
149
150#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
151static u64 ehci_dmamask = DMA_BIT_MASK(32);
152static struct at91_usbh_data usbh_ehci_data;
153
154static struct resource usbh_ehci_resources[] = {
155 [0] = {
156 .start = AT91SAM9G45_EHCI_BASE,
157 .end = AT91SAM9G45_EHCI_BASE + SZ_1M - 1,
158 .flags = IORESOURCE_MEM,
159 },
160 [1] = {
161 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
162 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
163 .flags = IORESOURCE_IRQ,
164 },
165};
166
167static struct platform_device at91_usbh_ehci_device = {
168 .name = "atmel-ehci",
169 .id = -1,
170 .dev = {
171 .dma_mask = &ehci_dmamask,
172 .coherent_dma_mask = DMA_BIT_MASK(32),
173 .platform_data = &usbh_ehci_data,
174 },
175 .resource = usbh_ehci_resources,
176 .num_resources = ARRAY_SIZE(usbh_ehci_resources),
177};
178
179void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data)
180{
181 int i;
182
183 if (!data)
184 return;
185
186 /* Enable VBus control for UHP ports */
187 for (i = 0; i < data->ports; i++) {
188 if (gpio_is_valid(data->vbus_pin[i]))
189 at91_set_gpio_output(data->vbus_pin[i],
190 data->vbus_pin_active_low[i]);
191 }
192
193 usbh_ehci_data = *data;
194 platform_device_register(&at91_usbh_ehci_device);
195}
196#else
197void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) {}
198#endif
199
200
201/* --------------------------------------------------------------------
202 * USB HS Device (Gadget)
203 * -------------------------------------------------------------------- */
204
205#if defined(CONFIG_USB_ATMEL_USBA) || defined(CONFIG_USB_ATMEL_USBA_MODULE)
206static struct resource usba_udc_resources[] = {
207 [0] = {
208 .start = AT91SAM9G45_UDPHS_FIFO,
209 .end = AT91SAM9G45_UDPHS_FIFO + SZ_512K - 1,
210 .flags = IORESOURCE_MEM,
211 },
212 [1] = {
213 .start = AT91SAM9G45_BASE_UDPHS,
214 .end = AT91SAM9G45_BASE_UDPHS + SZ_1K - 1,
215 .flags = IORESOURCE_MEM,
216 },
217 [2] = {
218 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UDPHS,
219 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UDPHS,
220 .flags = IORESOURCE_IRQ,
221 },
222};
223
224#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
225 [idx] = { \
226 .name = nam, \
227 .index = idx, \
228 .fifo_size = maxpkt, \
229 .nr_banks = maxbk, \
230 .can_dma = dma, \
231 .can_isoc = isoc, \
232 }
233
234static struct usba_ep_data usba_udc_ep[] __initdata = {
235 EP("ep0", 0, 64, 1, 0, 0),
236 EP("ep1", 1, 1024, 2, 1, 1),
237 EP("ep2", 2, 1024, 2, 1, 1),
238 EP("ep3", 3, 1024, 3, 1, 0),
239 EP("ep4", 4, 1024, 3, 1, 0),
240 EP("ep5", 5, 1024, 3, 1, 1),
241 EP("ep6", 6, 1024, 3, 1, 1),
242};
243
244#undef EP
245
246/*
247 * pdata doesn't have room for any endpoints, so we need to
248 * append room for the ones we need right after it.
249 */
250static struct {
251 struct usba_platform_data pdata;
252 struct usba_ep_data ep[7];
253} usba_udc_data;
254
255static struct platform_device at91_usba_udc_device = {
256 .name = "atmel_usba_udc",
257 .id = -1,
258 .dev = {
259 .platform_data = &usba_udc_data.pdata,
260 },
261 .resource = usba_udc_resources,
262 .num_resources = ARRAY_SIZE(usba_udc_resources),
263};
264
265void __init at91_add_device_usba(struct usba_platform_data *data)
266{
267 usba_udc_data.pdata.vbus_pin = -EINVAL;
268 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
269 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
270
271 if (data && gpio_is_valid(data->vbus_pin)) {
272 at91_set_gpio_input(data->vbus_pin, 0);
273 at91_set_deglitch(data->vbus_pin, 1);
274 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
275 }
276
277 /* Pullup pin is handled internally by USB device peripheral */
278
279 platform_device_register(&at91_usba_udc_device);
280}
281#else
282void __init at91_add_device_usba(struct usba_platform_data *data) {}
283#endif
284
285
286/* --------------------------------------------------------------------
287 * Ethernet
288 * -------------------------------------------------------------------- */
289
290#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
291static u64 eth_dmamask = DMA_BIT_MASK(32);
292static struct macb_platform_data eth_data;
293
294static struct resource eth_resources[] = {
295 [0] = {
296 .start = AT91SAM9G45_BASE_EMAC,
297 .end = AT91SAM9G45_BASE_EMAC + SZ_16K - 1,
298 .flags = IORESOURCE_MEM,
299 },
300 [1] = {
301 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_EMAC,
302 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_EMAC,
303 .flags = IORESOURCE_IRQ,
304 },
305};
306
307static struct platform_device at91sam9g45_eth_device = {
308 .name = "macb",
309 .id = -1,
310 .dev = {
311 .dma_mask = &eth_dmamask,
312 .coherent_dma_mask = DMA_BIT_MASK(32),
313 .platform_data = &eth_data,
314 },
315 .resource = eth_resources,
316 .num_resources = ARRAY_SIZE(eth_resources),
317};
318
319void __init at91_add_device_eth(struct macb_platform_data *data)
320{
321 if (!data)
322 return;
323
324 if (gpio_is_valid(data->phy_irq_pin)) {
325 at91_set_gpio_input(data->phy_irq_pin, 0);
326 at91_set_deglitch(data->phy_irq_pin, 1);
327 }
328
329 /* Pins used for MII and RMII */
330 at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */
331 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */
332 at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
333 at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
334 at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */
335 at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */
336 at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */
337 at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */
338 at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */
339 at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */
340
341 if (!data->is_rmii) {
342 at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */
343 at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */
344 at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */
345 at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */
346 at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */
347 at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */
348 at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */
349 at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */
350 }
351
352 eth_data = *data;
353 platform_device_register(&at91sam9g45_eth_device);
354}
355#else
356void __init at91_add_device_eth(struct macb_platform_data *data) {}
357#endif
358
359
360/* --------------------------------------------------------------------
361 * MMC / SD
362 * -------------------------------------------------------------------- */
363
364#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
365static u64 mmc_dmamask = DMA_BIT_MASK(32);
366static struct mci_platform_data mmc0_data, mmc1_data;
367
368static struct resource mmc0_resources[] = {
369 [0] = {
370 .start = AT91SAM9G45_BASE_MCI0,
371 .end = AT91SAM9G45_BASE_MCI0 + SZ_16K - 1,
372 .flags = IORESOURCE_MEM,
373 },
374 [1] = {
375 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI0,
376 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI0,
377 .flags = IORESOURCE_IRQ,
378 },
379};
380
381static struct platform_device at91sam9g45_mmc0_device = {
382 .name = "atmel_mci",
383 .id = 0,
384 .dev = {
385 .dma_mask = &mmc_dmamask,
386 .coherent_dma_mask = DMA_BIT_MASK(32),
387 .platform_data = &mmc0_data,
388 },
389 .resource = mmc0_resources,
390 .num_resources = ARRAY_SIZE(mmc0_resources),
391};
392
393static struct resource mmc1_resources[] = {
394 [0] = {
395 .start = AT91SAM9G45_BASE_MCI1,
396 .end = AT91SAM9G45_BASE_MCI1 + SZ_16K - 1,
397 .flags = IORESOURCE_MEM,
398 },
399 [1] = {
400 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI1,
401 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI1,
402 .flags = IORESOURCE_IRQ,
403 },
404};
405
406static struct platform_device at91sam9g45_mmc1_device = {
407 .name = "atmel_mci",
408 .id = 1,
409 .dev = {
410 .dma_mask = &mmc_dmamask,
411 .coherent_dma_mask = DMA_BIT_MASK(32),
412 .platform_data = &mmc1_data,
413 },
414 .resource = mmc1_resources,
415 .num_resources = ARRAY_SIZE(mmc1_resources),
416};
417
418/* Consider only one slot : slot 0 */
419void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
420{
421
422 if (!data)
423 return;
424
425 /* Must have at least one usable slot */
426 if (!data->slot[0].bus_width)
427 return;
428
429#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
430 {
431 struct at_dma_slave *atslave;
432 struct mci_dma_data *alt_atslave;
433
434 alt_atslave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
435 atslave = &alt_atslave->sdata;
436
437 /* DMA slave channel configuration */
438 atslave->dma_dev = &at_hdmac_device.dev;
439 atslave->cfg = ATC_FIFOCFG_HALFFIFO
440 | ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW;
441 if (mmc_id == 0) /* MCI0 */
442 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI0)
443 | ATC_DST_PER(AT_DMA_ID_MCI0);
444
445 else /* MCI1 */
446 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI1)
447 | ATC_DST_PER(AT_DMA_ID_MCI1);
448
449 data->dma_slave = alt_atslave;
450 }
451#endif
452
453
454 /* input/irq */
455 if (gpio_is_valid(data->slot[0].detect_pin)) {
456 at91_set_gpio_input(data->slot[0].detect_pin, 1);
457 at91_set_deglitch(data->slot[0].detect_pin, 1);
458 }
459 if (gpio_is_valid(data->slot[0].wp_pin))
460 at91_set_gpio_input(data->slot[0].wp_pin, 1);
461
462 if (mmc_id == 0) { /* MCI0 */
463
464 /* CLK */
465 at91_set_A_periph(AT91_PIN_PA0, 0);
466
467 /* CMD */
468 at91_set_A_periph(AT91_PIN_PA1, 1);
469
470 /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
471 at91_set_A_periph(AT91_PIN_PA2, 1);
472 if (data->slot[0].bus_width == 4) {
473 at91_set_A_periph(AT91_PIN_PA3, 1);
474 at91_set_A_periph(AT91_PIN_PA4, 1);
475 at91_set_A_periph(AT91_PIN_PA5, 1);
476 if (data->slot[0].bus_width == 8) {
477 at91_set_A_periph(AT91_PIN_PA6, 1);
478 at91_set_A_periph(AT91_PIN_PA7, 1);
479 at91_set_A_periph(AT91_PIN_PA8, 1);
480 at91_set_A_periph(AT91_PIN_PA9, 1);
481 }
482 }
483
484 mmc0_data = *data;
485 platform_device_register(&at91sam9g45_mmc0_device);
486
487 } else { /* MCI1 */
488
489 /* CLK */
490 at91_set_A_periph(AT91_PIN_PA31, 0);
491
492 /* CMD */
493 at91_set_A_periph(AT91_PIN_PA22, 1);
494
495 /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
496 at91_set_A_periph(AT91_PIN_PA23, 1);
497 if (data->slot[0].bus_width == 4) {
498 at91_set_A_periph(AT91_PIN_PA24, 1);
499 at91_set_A_periph(AT91_PIN_PA25, 1);
500 at91_set_A_periph(AT91_PIN_PA26, 1);
501 if (data->slot[0].bus_width == 8) {
502 at91_set_A_periph(AT91_PIN_PA27, 1);
503 at91_set_A_periph(AT91_PIN_PA28, 1);
504 at91_set_A_periph(AT91_PIN_PA29, 1);
505 at91_set_A_periph(AT91_PIN_PA30, 1);
506 }
507 }
508
509 mmc1_data = *data;
510 platform_device_register(&at91sam9g45_mmc1_device);
511
512 }
513}
514#else
515void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
516#endif
517
518
519/* --------------------------------------------------------------------
520 * NAND / SmartMedia
521 * -------------------------------------------------------------------- */
522
523#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
524static struct atmel_nand_data nand_data;
525
526#define NAND_BASE AT91_CHIPSELECT_3
527
528static struct resource nand_resources[] = {
529 [0] = {
530 .start = NAND_BASE,
531 .end = NAND_BASE + SZ_256M - 1,
532 .flags = IORESOURCE_MEM,
533 },
534 [1] = {
535 .start = AT91SAM9G45_BASE_ECC,
536 .end = AT91SAM9G45_BASE_ECC + SZ_512 - 1,
537 .flags = IORESOURCE_MEM,
538 }
539};
540
541static struct platform_device at91sam9g45_nand_device = {
542 .name = "atmel_nand",
543 .id = -1,
544 .dev = {
545 .platform_data = &nand_data,
546 },
547 .resource = nand_resources,
548 .num_resources = ARRAY_SIZE(nand_resources),
549};
550
551void __init at91_add_device_nand(struct atmel_nand_data *data)
552{
553 unsigned long csa;
554
555 if (!data)
556 return;
557
558 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
559 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
560
561 /* enable pin */
562 if (gpio_is_valid(data->enable_pin))
563 at91_set_gpio_output(data->enable_pin, 1);
564
565 /* ready/busy pin */
566 if (gpio_is_valid(data->rdy_pin))
567 at91_set_gpio_input(data->rdy_pin, 1);
568
569 /* card detect pin */
570 if (gpio_is_valid(data->det_pin))
571 at91_set_gpio_input(data->det_pin, 1);
572
573 nand_data = *data;
574 platform_device_register(&at91sam9g45_nand_device);
575}
576#else
577void __init at91_add_device_nand(struct atmel_nand_data *data) {}
578#endif
579
580
581/* --------------------------------------------------------------------
582 * TWI (i2c)
583 * -------------------------------------------------------------------- */
584
585/*
586 * Prefer the GPIO code since the TWI controller isn't robust
587 * (gets overruns and underruns under load) and can only issue
588 * repeated STARTs in one scenario (the driver doesn't yet handle them).
589 */
590#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
591static struct i2c_gpio_platform_data pdata_i2c0 = {
592 .sda_pin = AT91_PIN_PA20,
593 .sda_is_open_drain = 1,
594 .scl_pin = AT91_PIN_PA21,
595 .scl_is_open_drain = 1,
596 .udelay = 5, /* ~100 kHz */
597};
598
599static struct platform_device at91sam9g45_twi0_device = {
600 .name = "i2c-gpio",
601 .id = 0,
602 .dev.platform_data = &pdata_i2c0,
603};
604
605static struct i2c_gpio_platform_data pdata_i2c1 = {
606 .sda_pin = AT91_PIN_PB10,
607 .sda_is_open_drain = 1,
608 .scl_pin = AT91_PIN_PB11,
609 .scl_is_open_drain = 1,
610 .udelay = 5, /* ~100 kHz */
611};
612
613static struct platform_device at91sam9g45_twi1_device = {
614 .name = "i2c-gpio",
615 .id = 1,
616 .dev.platform_data = &pdata_i2c1,
617};
618
619void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
620{
621 i2c_register_board_info(i2c_id, devices, nr_devices);
622
623 if (i2c_id == 0) {
624 at91_set_GPIO_periph(AT91_PIN_PA20, 1); /* TWD (SDA) */
625 at91_set_multi_drive(AT91_PIN_PA20, 1);
626
627 at91_set_GPIO_periph(AT91_PIN_PA21, 1); /* TWCK (SCL) */
628 at91_set_multi_drive(AT91_PIN_PA21, 1);
629
630 platform_device_register(&at91sam9g45_twi0_device);
631 } else {
632 at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* TWD (SDA) */
633 at91_set_multi_drive(AT91_PIN_PB10, 1);
634
635 at91_set_GPIO_periph(AT91_PIN_PB11, 1); /* TWCK (SCL) */
636 at91_set_multi_drive(AT91_PIN_PB11, 1);
637
638 platform_device_register(&at91sam9g45_twi1_device);
639 }
640}
641
642#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
643static struct resource twi0_resources[] = {
644 [0] = {
645 .start = AT91SAM9G45_BASE_TWI0,
646 .end = AT91SAM9G45_BASE_TWI0 + SZ_16K - 1,
647 .flags = IORESOURCE_MEM,
648 },
649 [1] = {
650 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI0,
651 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI0,
652 .flags = IORESOURCE_IRQ,
653 },
654};
655
656static struct platform_device at91sam9g45_twi0_device = {
657 .name = "i2c-at91sam9g10",
658 .id = 0,
659 .resource = twi0_resources,
660 .num_resources = ARRAY_SIZE(twi0_resources),
661};
662
663static struct resource twi1_resources[] = {
664 [0] = {
665 .start = AT91SAM9G45_BASE_TWI1,
666 .end = AT91SAM9G45_BASE_TWI1 + SZ_16K - 1,
667 .flags = IORESOURCE_MEM,
668 },
669 [1] = {
670 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI1,
671 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI1,
672 .flags = IORESOURCE_IRQ,
673 },
674};
675
676static struct platform_device at91sam9g45_twi1_device = {
677 .name = "i2c-at91sam9g10",
678 .id = 1,
679 .resource = twi1_resources,
680 .num_resources = ARRAY_SIZE(twi1_resources),
681};
682
683void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
684{
685 i2c_register_board_info(i2c_id, devices, nr_devices);
686
687 /* pins used for TWI interface */
688 if (i2c_id == 0) {
689 at91_set_A_periph(AT91_PIN_PA20, 0); /* TWD */
690 at91_set_A_periph(AT91_PIN_PA21, 0); /* TWCK */
691
692 platform_device_register(&at91sam9g45_twi0_device);
693 } else {
694 at91_set_A_periph(AT91_PIN_PB10, 0); /* TWD */
695 at91_set_A_periph(AT91_PIN_PB11, 0); /* TWCK */
696
697 platform_device_register(&at91sam9g45_twi1_device);
698 }
699}
700#else
701void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
702#endif
703
704
705/* --------------------------------------------------------------------
706 * SPI
707 * -------------------------------------------------------------------- */
708
709#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
710static u64 spi_dmamask = DMA_BIT_MASK(32);
711
712static struct resource spi0_resources[] = {
713 [0] = {
714 .start = AT91SAM9G45_BASE_SPI0,
715 .end = AT91SAM9G45_BASE_SPI0 + SZ_16K - 1,
716 .flags = IORESOURCE_MEM,
717 },
718 [1] = {
719 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI0,
720 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI0,
721 .flags = IORESOURCE_IRQ,
722 },
723};
724
725static struct platform_device at91sam9g45_spi0_device = {
726 .name = "atmel_spi",
727 .id = 0,
728 .dev = {
729 .dma_mask = &spi_dmamask,
730 .coherent_dma_mask = DMA_BIT_MASK(32),
731 },
732 .resource = spi0_resources,
733 .num_resources = ARRAY_SIZE(spi0_resources),
734};
735
736static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 };
737
738static struct resource spi1_resources[] = {
739 [0] = {
740 .start = AT91SAM9G45_BASE_SPI1,
741 .end = AT91SAM9G45_BASE_SPI1 + SZ_16K - 1,
742 .flags = IORESOURCE_MEM,
743 },
744 [1] = {
745 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI1,
746 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI1,
747 .flags = IORESOURCE_IRQ,
748 },
749};
750
751static struct platform_device at91sam9g45_spi1_device = {
752 .name = "atmel_spi",
753 .id = 1,
754 .dev = {
755 .dma_mask = &spi_dmamask,
756 .coherent_dma_mask = DMA_BIT_MASK(32),
757 },
758 .resource = spi1_resources,
759 .num_resources = ARRAY_SIZE(spi1_resources),
760};
761
762static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 };
763
764void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
765{
766 int i;
767 unsigned long cs_pin;
768 short enable_spi0 = 0;
769 short enable_spi1 = 0;
770
771 /* Choose SPI chip-selects */
772 for (i = 0; i < nr_devices; i++) {
773 if (devices[i].controller_data)
774 cs_pin = (unsigned long) devices[i].controller_data;
775 else if (devices[i].bus_num == 0)
776 cs_pin = spi0_standard_cs[devices[i].chip_select];
777 else
778 cs_pin = spi1_standard_cs[devices[i].chip_select];
779
780 if (!gpio_is_valid(cs_pin))
781 continue;
782
783 if (devices[i].bus_num == 0)
784 enable_spi0 = 1;
785 else
786 enable_spi1 = 1;
787
788 /* enable chip-select pin */
789 at91_set_gpio_output(cs_pin, 1);
790
791 /* pass chip-select pin to driver */
792 devices[i].controller_data = (void *) cs_pin;
793 }
794
795 spi_register_board_info(devices, nr_devices);
796
797 /* Configure SPI bus(es) */
798 if (enable_spi0) {
799 at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */
800 at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */
801 at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */
802
803 platform_device_register(&at91sam9g45_spi0_device);
804 }
805 if (enable_spi1) {
806 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_MISO */
807 at91_set_A_periph(AT91_PIN_PB15, 0); /* SPI1_MOSI */
808 at91_set_A_periph(AT91_PIN_PB16, 0); /* SPI1_SPCK */
809
810 platform_device_register(&at91sam9g45_spi1_device);
811 }
812}
813#else
814void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
815#endif
816
817
818/* --------------------------------------------------------------------
819 * AC97
820 * -------------------------------------------------------------------- */
821
822#if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
823static u64 ac97_dmamask = DMA_BIT_MASK(32);
824static struct ac97c_platform_data ac97_data;
825
826static struct resource ac97_resources[] = {
827 [0] = {
828 .start = AT91SAM9G45_BASE_AC97C,
829 .end = AT91SAM9G45_BASE_AC97C + SZ_16K - 1,
830 .flags = IORESOURCE_MEM,
831 },
832 [1] = {
833 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AC97C,
834 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AC97C,
835 .flags = IORESOURCE_IRQ,
836 },
837};
838
839static struct platform_device at91sam9g45_ac97_device = {
840 .name = "atmel_ac97c",
841 .id = 0,
842 .dev = {
843 .dma_mask = &ac97_dmamask,
844 .coherent_dma_mask = DMA_BIT_MASK(32),
845 .platform_data = &ac97_data,
846 },
847 .resource = ac97_resources,
848 .num_resources = ARRAY_SIZE(ac97_resources),
849};
850
851void __init at91_add_device_ac97(struct ac97c_platform_data *data)
852{
853 if (!data)
854 return;
855
856 at91_set_A_periph(AT91_PIN_PD8, 0); /* AC97FS */
857 at91_set_A_periph(AT91_PIN_PD9, 0); /* AC97CK */
858 at91_set_A_periph(AT91_PIN_PD7, 0); /* AC97TX */
859 at91_set_A_periph(AT91_PIN_PD6, 0); /* AC97RX */
860
861 /* reset */
862 if (gpio_is_valid(data->reset_pin))
863 at91_set_gpio_output(data->reset_pin, 0);
864
865 ac97_data = *data;
866 platform_device_register(&at91sam9g45_ac97_device);
867}
868#else
869void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
870#endif
871
872/* --------------------------------------------------------------------
873 * Image Sensor Interface
874 * -------------------------------------------------------------------- */
875#if defined(CONFIG_VIDEO_ATMEL_ISI) || defined(CONFIG_VIDEO_ATMEL_ISI_MODULE)
876static u64 isi_dmamask = DMA_BIT_MASK(32);
877static struct isi_platform_data isi_data;
878
879struct resource isi_resources[] = {
880 [0] = {
881 .start = AT91SAM9G45_BASE_ISI,
882 .end = AT91SAM9G45_BASE_ISI + SZ_16K - 1,
883 .flags = IORESOURCE_MEM,
884 },
885 [1] = {
886 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_ISI,
887 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_ISI,
888 .flags = IORESOURCE_IRQ,
889 },
890};
891
892static struct platform_device at91sam9g45_isi_device = {
893 .name = "atmel_isi",
894 .id = 0,
895 .dev = {
896 .dma_mask = &isi_dmamask,
897 .coherent_dma_mask = DMA_BIT_MASK(32),
898 .platform_data = &isi_data,
899 },
900 .resource = isi_resources,
901 .num_resources = ARRAY_SIZE(isi_resources),
902};
903
904static struct clk_lookup isi_mck_lookups[] = {
905 CLKDEV_CON_DEV_ID("isi_mck", "atmel_isi.0", NULL),
906};
907
908void __init at91_add_device_isi(struct isi_platform_data *data,
909 bool use_pck_as_mck)
910{
911 struct clk *pck;
912 struct clk *parent;
913
914 if (!data)
915 return;
916 isi_data = *data;
917
918 at91_set_A_periph(AT91_PIN_PB20, 0); /* ISI_D0 */
919 at91_set_A_periph(AT91_PIN_PB21, 0); /* ISI_D1 */
920 at91_set_A_periph(AT91_PIN_PB22, 0); /* ISI_D2 */
921 at91_set_A_periph(AT91_PIN_PB23, 0); /* ISI_D3 */
922 at91_set_A_periph(AT91_PIN_PB24, 0); /* ISI_D4 */
923 at91_set_A_periph(AT91_PIN_PB25, 0); /* ISI_D5 */
924 at91_set_A_periph(AT91_PIN_PB26, 0); /* ISI_D6 */
925 at91_set_A_periph(AT91_PIN_PB27, 0); /* ISI_D7 */
926 at91_set_A_periph(AT91_PIN_PB28, 0); /* ISI_PCK */
927 at91_set_A_periph(AT91_PIN_PB30, 0); /* ISI_HSYNC */
928 at91_set_A_periph(AT91_PIN_PB29, 0); /* ISI_VSYNC */
929 at91_set_B_periph(AT91_PIN_PB8, 0); /* ISI_PD8 */
930 at91_set_B_periph(AT91_PIN_PB9, 0); /* ISI_PD9 */
931 at91_set_B_periph(AT91_PIN_PB10, 0); /* ISI_PD10 */
932 at91_set_B_periph(AT91_PIN_PB11, 0); /* ISI_PD11 */
933
934 platform_device_register(&at91sam9g45_isi_device);
935
936 if (use_pck_as_mck) {
937 at91_set_B_periph(AT91_PIN_PB31, 0); /* ISI_MCK (PCK1) */
938
939 pck = clk_get(NULL, "pck1");
940 parent = clk_get(NULL, "plla");
941
942 BUG_ON(IS_ERR(pck) || IS_ERR(parent));
943
944 if (clk_set_parent(pck, parent)) {
945 pr_err("Failed to set PCK's parent\n");
946 } else {
947 /* Register PCK as ISI_MCK */
948 isi_mck_lookups[0].clk = pck;
949 clkdev_add_table(isi_mck_lookups,
950 ARRAY_SIZE(isi_mck_lookups));
951 }
952
953 clk_put(pck);
954 clk_put(parent);
955 }
956}
957#else
958void __init at91_add_device_isi(struct isi_platform_data *data,
959 bool use_pck_as_mck) {}
960#endif
961
962
963/* --------------------------------------------------------------------
964 * LCD Controller
965 * -------------------------------------------------------------------- */
966
967#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
968static u64 lcdc_dmamask = DMA_BIT_MASK(32);
969static struct atmel_lcdfb_pdata lcdc_data;
970
971static struct resource lcdc_resources[] = {
972 [0] = {
973 .start = AT91SAM9G45_LCDC_BASE,
974 .end = AT91SAM9G45_LCDC_BASE + SZ_4K - 1,
975 .flags = IORESOURCE_MEM,
976 },
977 [1] = {
978 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_LCDC,
979 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_LCDC,
980 .flags = IORESOURCE_IRQ,
981 },
982};
983
984static struct platform_device at91_lcdc_device = {
985 .id = 0,
986 .dev = {
987 .dma_mask = &lcdc_dmamask,
988 .coherent_dma_mask = DMA_BIT_MASK(32),
989 .platform_data = &lcdc_data,
990 },
991 .resource = lcdc_resources,
992 .num_resources = ARRAY_SIZE(lcdc_resources),
993};
994
995void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data)
996{
997 if (!data)
998 return;
999
1000 if (cpu_is_at91sam9g45es())
1001 at91_lcdc_device.name = "at91sam9g45es-lcdfb";
1002 else
1003 at91_lcdc_device.name = "at91sam9g45-lcdfb";
1004
1005 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
1006
1007 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
1008 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
1009 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
1010 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
1011 at91_set_A_periph(AT91_PIN_PE6, 0); /* LCDDEN */
1012 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
1013 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
1014 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
1015 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
1016 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
1017 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
1018 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
1019 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
1020 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
1021 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
1022 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
1023 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
1024 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
1025 at91_set_A_periph(AT91_PIN_PE20, 0); /* LCDD13 */
1026 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
1027 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
1028 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
1029 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
1030 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
1031 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
1032 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
1033 at91_set_A_periph(AT91_PIN_PE28, 0); /* LCDD21 */
1034 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
1035 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
1036
1037 lcdc_data = *data;
1038 platform_device_register(&at91_lcdc_device);
1039}
1040#else
1041void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) {}
1042#endif
1043
1044
1045/* --------------------------------------------------------------------
1046 * Timer/Counter block
1047 * -------------------------------------------------------------------- */
1048
1049#ifdef CONFIG_ATMEL_TCLIB
1050static struct resource tcb0_resources[] = {
1051 [0] = {
1052 .start = AT91SAM9G45_BASE_TCB0,
1053 .end = AT91SAM9G45_BASE_TCB0 + SZ_256 - 1,
1054 .flags = IORESOURCE_MEM,
1055 },
1056 [1] = {
1057 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
1058 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
1059 .flags = IORESOURCE_IRQ,
1060 },
1061};
1062
1063static struct platform_device at91sam9g45_tcb0_device = {
1064 .name = "atmel_tcb",
1065 .id = 0,
1066 .resource = tcb0_resources,
1067 .num_resources = ARRAY_SIZE(tcb0_resources),
1068};
1069
1070/* TCB1 begins with TC3 */
1071static struct resource tcb1_resources[] = {
1072 [0] = {
1073 .start = AT91SAM9G45_BASE_TCB1,
1074 .end = AT91SAM9G45_BASE_TCB1 + SZ_256 - 1,
1075 .flags = IORESOURCE_MEM,
1076 },
1077 [1] = {
1078 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
1079 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
1080 .flags = IORESOURCE_IRQ,
1081 },
1082};
1083
1084static struct platform_device at91sam9g45_tcb1_device = {
1085 .name = "atmel_tcb",
1086 .id = 1,
1087 .resource = tcb1_resources,
1088 .num_resources = ARRAY_SIZE(tcb1_resources),
1089};
1090
1091static void __init at91_add_device_tc(void)
1092{
1093 platform_device_register(&at91sam9g45_tcb0_device);
1094 platform_device_register(&at91sam9g45_tcb1_device);
1095}
1096#else
1097static void __init at91_add_device_tc(void) { }
1098#endif
1099
1100
1101/* --------------------------------------------------------------------
1102 * RTC
1103 * -------------------------------------------------------------------- */
1104
1105#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
1106static struct resource rtc_resources[] = {
1107 [0] = {
1108 .start = AT91SAM9G45_BASE_RTC,
1109 .end = AT91SAM9G45_BASE_RTC + SZ_256 - 1,
1110 .flags = IORESOURCE_MEM,
1111 },
1112 [1] = {
1113 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
1114 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
1115 .flags = IORESOURCE_IRQ,
1116 },
1117};
1118
1119static struct platform_device at91sam9g45_rtc_device = {
1120 .name = "at91_rtc",
1121 .id = -1,
1122 .resource = rtc_resources,
1123 .num_resources = ARRAY_SIZE(rtc_resources),
1124};
1125
1126static void __init at91_add_device_rtc(void)
1127{
1128 platform_device_register(&at91sam9g45_rtc_device);
1129}
1130#else
1131static void __init at91_add_device_rtc(void) {}
1132#endif
1133
1134
1135/* --------------------------------------------------------------------
1136 * ADC and touchscreen
1137 * -------------------------------------------------------------------- */
1138
1139#if IS_ENABLED(CONFIG_AT91_ADC)
1140static struct at91_adc_data adc_data;
1141
1142static struct resource adc_resources[] = {
1143 [0] = {
1144 .start = AT91SAM9G45_BASE_TSC,
1145 .end = AT91SAM9G45_BASE_TSC + SZ_16K - 1,
1146 .flags = IORESOURCE_MEM,
1147 },
1148 [1] = {
1149 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
1150 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
1151 .flags = IORESOURCE_IRQ,
1152 }
1153};
1154
1155static struct platform_device at91_adc_device = {
1156 .name = "at91sam9g45-adc",
1157 .id = -1,
1158 .dev = {
1159 .platform_data = &adc_data,
1160 },
1161 .resource = adc_resources,
1162 .num_resources = ARRAY_SIZE(adc_resources),
1163};
1164
1165static struct at91_adc_trigger at91_adc_triggers[] = {
1166 [0] = {
1167 .name = "external-rising",
1168 .value = 1,
1169 .is_external = true,
1170 },
1171 [1] = {
1172 .name = "external-falling",
1173 .value = 2,
1174 .is_external = true,
1175 },
1176 [2] = {
1177 .name = "external-any",
1178 .value = 3,
1179 .is_external = true,
1180 },
1181 [3] = {
1182 .name = "continuous",
1183 .value = 6,
1184 .is_external = false,
1185 },
1186};
1187
1188void __init at91_add_device_adc(struct at91_adc_data *data)
1189{
1190 if (!data)
1191 return;
1192
1193 if (test_bit(0, &data->channels_used))
1194 at91_set_gpio_input(AT91_PIN_PD20, 0);
1195 if (test_bit(1, &data->channels_used))
1196 at91_set_gpio_input(AT91_PIN_PD21, 0);
1197 if (test_bit(2, &data->channels_used))
1198 at91_set_gpio_input(AT91_PIN_PD22, 0);
1199 if (test_bit(3, &data->channels_used))
1200 at91_set_gpio_input(AT91_PIN_PD23, 0);
1201 if (test_bit(4, &data->channels_used))
1202 at91_set_gpio_input(AT91_PIN_PD24, 0);
1203 if (test_bit(5, &data->channels_used))
1204 at91_set_gpio_input(AT91_PIN_PD25, 0);
1205 if (test_bit(6, &data->channels_used))
1206 at91_set_gpio_input(AT91_PIN_PD26, 0);
1207 if (test_bit(7, &data->channels_used))
1208 at91_set_gpio_input(AT91_PIN_PD27, 0);
1209
1210 if (data->use_external_triggers)
1211 at91_set_A_periph(AT91_PIN_PD28, 0);
1212
1213 data->startup_time = 40;
1214 data->trigger_number = 4;
1215 data->trigger_list = at91_adc_triggers;
1216
1217 adc_data = *data;
1218 platform_device_register(&at91_adc_device);
1219}
1220#else
1221void __init at91_add_device_adc(struct at91_adc_data *data) {}
1222#endif
1223
1224/* --------------------------------------------------------------------
1225 * RTT
1226 * -------------------------------------------------------------------- */
1227
1228static struct resource rtt_resources[] = {
1229 {
1230 .start = AT91SAM9G45_BASE_RTT,
1231 .end = AT91SAM9G45_BASE_RTT + SZ_16 - 1,
1232 .flags = IORESOURCE_MEM,
1233 }, {
1234 .flags = IORESOURCE_MEM,
1235 }, {
1236 .flags = IORESOURCE_IRQ,
1237 }
1238};
1239
1240static struct platform_device at91sam9g45_rtt_device = {
1241 .name = "at91_rtt",
1242 .id = 0,
1243 .resource = rtt_resources,
1244};
1245
1246#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
1247static void __init at91_add_device_rtt_rtc(void)
1248{
1249 at91sam9g45_rtt_device.name = "rtc-at91sam9";
1250 /*
1251 * The second resource is needed:
1252 * GPBR will serve as the storage for RTC time offset
1253 */
1254 at91sam9g45_rtt_device.num_resources = 3;
1255 rtt_resources[1].start = AT91SAM9G45_BASE_GPBR +
1256 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
1257 rtt_resources[1].end = rtt_resources[1].start + 3;
1258 rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
1259 rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
1260}
1261#else
1262static void __init at91_add_device_rtt_rtc(void)
1263{
1264 /* Only one resource is needed: RTT not used as RTC */
1265 at91sam9g45_rtt_device.num_resources = 1;
1266}
1267#endif
1268
1269static void __init at91_add_device_rtt(void)
1270{
1271 at91_add_device_rtt_rtc();
1272 platform_device_register(&at91sam9g45_rtt_device);
1273}
1274
1275
1276/* --------------------------------------------------------------------
1277 * TRNG
1278 * -------------------------------------------------------------------- */
1279
1280#if defined(CONFIG_HW_RANDOM_ATMEL) || defined(CONFIG_HW_RANDOM_ATMEL_MODULE)
1281static struct resource trng_resources[] = {
1282 {
1283 .start = AT91SAM9G45_BASE_TRNG,
1284 .end = AT91SAM9G45_BASE_TRNG + SZ_16K - 1,
1285 .flags = IORESOURCE_MEM,
1286 },
1287};
1288
1289static struct platform_device at91sam9g45_trng_device = {
1290 .name = "atmel-trng",
1291 .id = -1,
1292 .resource = trng_resources,
1293 .num_resources = ARRAY_SIZE(trng_resources),
1294};
1295
1296static void __init at91_add_device_trng(void)
1297{
1298 platform_device_register(&at91sam9g45_trng_device);
1299}
1300#else
1301static void __init at91_add_device_trng(void) {}
1302#endif
1303
1304/* --------------------------------------------------------------------
1305 * Watchdog
1306 * -------------------------------------------------------------------- */
1307
1308#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
1309static struct resource wdt_resources[] = {
1310 {
1311 .start = AT91SAM9G45_BASE_WDT,
1312 .end = AT91SAM9G45_BASE_WDT + SZ_16 - 1,
1313 .flags = IORESOURCE_MEM,
1314 }
1315};
1316
1317static struct platform_device at91sam9g45_wdt_device = {
1318 .name = "at91_wdt",
1319 .id = -1,
1320 .resource = wdt_resources,
1321 .num_resources = ARRAY_SIZE(wdt_resources),
1322};
1323
1324static void __init at91_add_device_watchdog(void)
1325{
1326 platform_device_register(&at91sam9g45_wdt_device);
1327}
1328#else
1329static void __init at91_add_device_watchdog(void) {}
1330#endif
1331
1332
1333/* --------------------------------------------------------------------
1334 * PWM
1335 * --------------------------------------------------------------------*/
1336
1337#if IS_ENABLED(CONFIG_PWM_ATMEL)
1338static struct resource pwm_resources[] = {
1339 [0] = {
1340 .start = AT91SAM9G45_BASE_PWMC,
1341 .end = AT91SAM9G45_BASE_PWMC + SZ_16K - 1,
1342 .flags = IORESOURCE_MEM,
1343 },
1344 [1] = {
1345 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_PWMC,
1346 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_PWMC,
1347 .flags = IORESOURCE_IRQ,
1348 },
1349};
1350
1351static struct platform_device at91sam9g45_pwm0_device = {
1352 .name = "at91sam9rl-pwm",
1353 .id = -1,
1354 .resource = pwm_resources,
1355 .num_resources = ARRAY_SIZE(pwm_resources),
1356};
1357
1358void __init at91_add_device_pwm(u32 mask)
1359{
1360 if (mask & (1 << AT91_PWM0))
1361 at91_set_B_periph(AT91_PIN_PD24, 1); /* enable PWM0 */
1362
1363 if (mask & (1 << AT91_PWM1))
1364 at91_set_B_periph(AT91_PIN_PD31, 1); /* enable PWM1 */
1365
1366 if (mask & (1 << AT91_PWM2))
1367 at91_set_B_periph(AT91_PIN_PD26, 1); /* enable PWM2 */
1368
1369 if (mask & (1 << AT91_PWM3))
1370 at91_set_B_periph(AT91_PIN_PD0, 1); /* enable PWM3 */
1371
1372 platform_device_register(&at91sam9g45_pwm0_device);
1373}
1374#else
1375void __init at91_add_device_pwm(u32 mask) {}
1376#endif
1377
1378
1379/* --------------------------------------------------------------------
1380 * SSC -- Synchronous Serial Controller
1381 * -------------------------------------------------------------------- */
1382
1383#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
1384static u64 ssc0_dmamask = DMA_BIT_MASK(32);
1385
1386static struct resource ssc0_resources[] = {
1387 [0] = {
1388 .start = AT91SAM9G45_BASE_SSC0,
1389 .end = AT91SAM9G45_BASE_SSC0 + SZ_16K - 1,
1390 .flags = IORESOURCE_MEM,
1391 },
1392 [1] = {
1393 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC0,
1394 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC0,
1395 .flags = IORESOURCE_IRQ,
1396 },
1397};
1398
1399static struct platform_device at91sam9g45_ssc0_device = {
1400 .name = "at91sam9g45_ssc",
1401 .id = 0,
1402 .dev = {
1403 .dma_mask = &ssc0_dmamask,
1404 .coherent_dma_mask = DMA_BIT_MASK(32),
1405 },
1406 .resource = ssc0_resources,
1407 .num_resources = ARRAY_SIZE(ssc0_resources),
1408};
1409
1410static inline void configure_ssc0_pins(unsigned pins)
1411{
1412 if (pins & ATMEL_SSC_TF)
1413 at91_set_A_periph(AT91_PIN_PD1, 1);
1414 if (pins & ATMEL_SSC_TK)
1415 at91_set_A_periph(AT91_PIN_PD0, 1);
1416 if (pins & ATMEL_SSC_TD)
1417 at91_set_A_periph(AT91_PIN_PD2, 1);
1418 if (pins & ATMEL_SSC_RD)
1419 at91_set_A_periph(AT91_PIN_PD3, 1);
1420 if (pins & ATMEL_SSC_RK)
1421 at91_set_A_periph(AT91_PIN_PD4, 1);
1422 if (pins & ATMEL_SSC_RF)
1423 at91_set_A_periph(AT91_PIN_PD5, 1);
1424}
1425
1426static u64 ssc1_dmamask = DMA_BIT_MASK(32);
1427
1428static struct resource ssc1_resources[] = {
1429 [0] = {
1430 .start = AT91SAM9G45_BASE_SSC1,
1431 .end = AT91SAM9G45_BASE_SSC1 + SZ_16K - 1,
1432 .flags = IORESOURCE_MEM,
1433 },
1434 [1] = {
1435 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC1,
1436 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC1,
1437 .flags = IORESOURCE_IRQ,
1438 },
1439};
1440
1441static struct platform_device at91sam9g45_ssc1_device = {
1442 .name = "at91sam9g45_ssc",
1443 .id = 1,
1444 .dev = {
1445 .dma_mask = &ssc1_dmamask,
1446 .coherent_dma_mask = DMA_BIT_MASK(32),
1447 },
1448 .resource = ssc1_resources,
1449 .num_resources = ARRAY_SIZE(ssc1_resources),
1450};
1451
1452static inline void configure_ssc1_pins(unsigned pins)
1453{
1454 if (pins & ATMEL_SSC_TF)
1455 at91_set_A_periph(AT91_PIN_PD14, 1);
1456 if (pins & ATMEL_SSC_TK)
1457 at91_set_A_periph(AT91_PIN_PD12, 1);
1458 if (pins & ATMEL_SSC_TD)
1459 at91_set_A_periph(AT91_PIN_PD10, 1);
1460 if (pins & ATMEL_SSC_RD)
1461 at91_set_A_periph(AT91_PIN_PD11, 1);
1462 if (pins & ATMEL_SSC_RK)
1463 at91_set_A_periph(AT91_PIN_PD13, 1);
1464 if (pins & ATMEL_SSC_RF)
1465 at91_set_A_periph(AT91_PIN_PD15, 1);
1466}
1467
1468/*
1469 * SSC controllers are accessed through library code, instead of any
1470 * kind of all-singing/all-dancing driver. For example one could be
1471 * used by a particular I2S audio codec's driver, while another one
1472 * on the same system might be used by a custom data capture driver.
1473 */
1474void __init at91_add_device_ssc(unsigned id, unsigned pins)
1475{
1476 struct platform_device *pdev;
1477
1478 /*
1479 * NOTE: caller is responsible for passing information matching
1480 * "pins" to whatever will be using each particular controller.
1481 */
1482 switch (id) {
1483 case AT91SAM9G45_ID_SSC0:
1484 pdev = &at91sam9g45_ssc0_device;
1485 configure_ssc0_pins(pins);
1486 break;
1487 case AT91SAM9G45_ID_SSC1:
1488 pdev = &at91sam9g45_ssc1_device;
1489 configure_ssc1_pins(pins);
1490 break;
1491 default:
1492 return;
1493 }
1494
1495 platform_device_register(pdev);
1496}
1497
1498#else
1499void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1500#endif
1501
1502
1503/* --------------------------------------------------------------------
1504 * UART
1505 * -------------------------------------------------------------------- */
1506
1507#if defined(CONFIG_SERIAL_ATMEL)
1508static struct resource dbgu_resources[] = {
1509 [0] = {
1510 .start = AT91SAM9G45_BASE_DBGU,
1511 .end = AT91SAM9G45_BASE_DBGU + SZ_512 - 1,
1512 .flags = IORESOURCE_MEM,
1513 },
1514 [1] = {
1515 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
1516 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
1517 .flags = IORESOURCE_IRQ,
1518 },
1519};
1520
1521static struct atmel_uart_data dbgu_data = {
1522 .use_dma_tx = 0,
1523 .use_dma_rx = 0,
1524};
1525
1526static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1527
1528static struct platform_device at91sam9g45_dbgu_device = {
1529 .name = "atmel_usart",
1530 .id = 0,
1531 .dev = {
1532 .dma_mask = &dbgu_dmamask,
1533 .coherent_dma_mask = DMA_BIT_MASK(32),
1534 .platform_data = &dbgu_data,
1535 },
1536 .resource = dbgu_resources,
1537 .num_resources = ARRAY_SIZE(dbgu_resources),
1538};
1539
1540static inline void configure_dbgu_pins(void)
1541{
1542 at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */
1543 at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */
1544}
1545
1546static struct resource uart0_resources[] = {
1547 [0] = {
1548 .start = AT91SAM9G45_BASE_US0,
1549 .end = AT91SAM9G45_BASE_US0 + SZ_16K - 1,
1550 .flags = IORESOURCE_MEM,
1551 },
1552 [1] = {
1553 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0,
1554 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0,
1555 .flags = IORESOURCE_IRQ,
1556 },
1557};
1558
1559static struct atmel_uart_data uart0_data = {
1560 .use_dma_tx = 1,
1561 .use_dma_rx = 1,
1562};
1563
1564static u64 uart0_dmamask = DMA_BIT_MASK(32);
1565
1566static struct platform_device at91sam9g45_uart0_device = {
1567 .name = "atmel_usart",
1568 .id = 1,
1569 .dev = {
1570 .dma_mask = &uart0_dmamask,
1571 .coherent_dma_mask = DMA_BIT_MASK(32),
1572 .platform_data = &uart0_data,
1573 },
1574 .resource = uart0_resources,
1575 .num_resources = ARRAY_SIZE(uart0_resources),
1576};
1577
1578static inline void configure_usart0_pins(unsigned pins)
1579{
1580 at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */
1581 at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */
1582
1583 if (pins & ATMEL_UART_RTS)
1584 at91_set_B_periph(AT91_PIN_PB17, 0); /* RTS0 */
1585 if (pins & ATMEL_UART_CTS)
1586 at91_set_B_periph(AT91_PIN_PB15, 0); /* CTS0 */
1587}
1588
1589static struct resource uart1_resources[] = {
1590 [0] = {
1591 .start = AT91SAM9G45_BASE_US1,
1592 .end = AT91SAM9G45_BASE_US1 + SZ_16K - 1,
1593 .flags = IORESOURCE_MEM,
1594 },
1595 [1] = {
1596 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US1,
1597 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US1,
1598 .flags = IORESOURCE_IRQ,
1599 },
1600};
1601
1602static struct atmel_uart_data uart1_data = {
1603 .use_dma_tx = 1,
1604 .use_dma_rx = 1,
1605};
1606
1607static u64 uart1_dmamask = DMA_BIT_MASK(32);
1608
1609static struct platform_device at91sam9g45_uart1_device = {
1610 .name = "atmel_usart",
1611 .id = 2,
1612 .dev = {
1613 .dma_mask = &uart1_dmamask,
1614 .coherent_dma_mask = DMA_BIT_MASK(32),
1615 .platform_data = &uart1_data,
1616 },
1617 .resource = uart1_resources,
1618 .num_resources = ARRAY_SIZE(uart1_resources),
1619};
1620
1621static inline void configure_usart1_pins(unsigned pins)
1622{
1623 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */
1624 at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */
1625
1626 if (pins & ATMEL_UART_RTS)
1627 at91_set_A_periph(AT91_PIN_PD16, 0); /* RTS1 */
1628 if (pins & ATMEL_UART_CTS)
1629 at91_set_A_periph(AT91_PIN_PD17, 0); /* CTS1 */
1630}
1631
1632static struct resource uart2_resources[] = {
1633 [0] = {
1634 .start = AT91SAM9G45_BASE_US2,
1635 .end = AT91SAM9G45_BASE_US2 + SZ_16K - 1,
1636 .flags = IORESOURCE_MEM,
1637 },
1638 [1] = {
1639 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US2,
1640 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US2,
1641 .flags = IORESOURCE_IRQ,
1642 },
1643};
1644
1645static struct atmel_uart_data uart2_data = {
1646 .use_dma_tx = 1,
1647 .use_dma_rx = 1,
1648};
1649
1650static u64 uart2_dmamask = DMA_BIT_MASK(32);
1651
1652static struct platform_device at91sam9g45_uart2_device = {
1653 .name = "atmel_usart",
1654 .id = 3,
1655 .dev = {
1656 .dma_mask = &uart2_dmamask,
1657 .coherent_dma_mask = DMA_BIT_MASK(32),
1658 .platform_data = &uart2_data,
1659 },
1660 .resource = uart2_resources,
1661 .num_resources = ARRAY_SIZE(uart2_resources),
1662};
1663
1664static inline void configure_usart2_pins(unsigned pins)
1665{
1666 at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD2 */
1667 at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD2 */
1668
1669 if (pins & ATMEL_UART_RTS)
1670 at91_set_B_periph(AT91_PIN_PC9, 0); /* RTS2 */
1671 if (pins & ATMEL_UART_CTS)
1672 at91_set_B_periph(AT91_PIN_PC11, 0); /* CTS2 */
1673}
1674
1675static struct resource uart3_resources[] = {
1676 [0] = {
1677 .start = AT91SAM9G45_BASE_US3,
1678 .end = AT91SAM9G45_BASE_US3 + SZ_16K - 1,
1679 .flags = IORESOURCE_MEM,
1680 },
1681 [1] = {
1682 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US3,
1683 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US3,
1684 .flags = IORESOURCE_IRQ,
1685 },
1686};
1687
1688static struct atmel_uart_data uart3_data = {
1689 .use_dma_tx = 1,
1690 .use_dma_rx = 1,
1691};
1692
1693static u64 uart3_dmamask = DMA_BIT_MASK(32);
1694
1695static struct platform_device at91sam9g45_uart3_device = {
1696 .name = "atmel_usart",
1697 .id = 4,
1698 .dev = {
1699 .dma_mask = &uart3_dmamask,
1700 .coherent_dma_mask = DMA_BIT_MASK(32),
1701 .platform_data = &uart3_data,
1702 },
1703 .resource = uart3_resources,
1704 .num_resources = ARRAY_SIZE(uart3_resources),
1705};
1706
1707static inline void configure_usart3_pins(unsigned pins)
1708{
1709 at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD3 */
1710 at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD3 */
1711
1712 if (pins & ATMEL_UART_RTS)
1713 at91_set_B_periph(AT91_PIN_PA23, 0); /* RTS3 */
1714 if (pins & ATMEL_UART_CTS)
1715 at91_set_B_periph(AT91_PIN_PA24, 0); /* CTS3 */
1716}
1717
1718static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1719
1720void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1721{
1722 struct platform_device *pdev;
1723 struct atmel_uart_data *pdata;
1724
1725 switch (id) {
1726 case 0: /* DBGU */
1727 pdev = &at91sam9g45_dbgu_device;
1728 configure_dbgu_pins();
1729 break;
1730 case AT91SAM9G45_ID_US0:
1731 pdev = &at91sam9g45_uart0_device;
1732 configure_usart0_pins(pins);
1733 break;
1734 case AT91SAM9G45_ID_US1:
1735 pdev = &at91sam9g45_uart1_device;
1736 configure_usart1_pins(pins);
1737 break;
1738 case AT91SAM9G45_ID_US2:
1739 pdev = &at91sam9g45_uart2_device;
1740 configure_usart2_pins(pins);
1741 break;
1742 case AT91SAM9G45_ID_US3:
1743 pdev = &at91sam9g45_uart3_device;
1744 configure_usart3_pins(pins);
1745 break;
1746 default:
1747 return;
1748 }
1749 pdata = pdev->dev.platform_data;
1750 pdata->num = portnr; /* update to mapped ID */
1751
1752 if (portnr < ATMEL_MAX_UART)
1753 at91_uarts[portnr] = pdev;
1754}
1755
1756void __init at91_add_device_serial(void)
1757{
1758 int i;
1759
1760 for (i = 0; i < ATMEL_MAX_UART; i++) {
1761 if (at91_uarts[i])
1762 platform_device_register(at91_uarts[i]);
1763 }
1764}
1765#else
1766void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1767void __init at91_add_device_serial(void) {}
1768#endif
1769
1770/* --------------------------------------------------------------------
1771 * SHA1/SHA256
1772 * -------------------------------------------------------------------- */
1773
1774#if defined(CONFIG_CRYPTO_DEV_ATMEL_SHA) || defined(CONFIG_CRYPTO_DEV_ATMEL_SHA_MODULE)
1775static struct resource sha_resources[] = {
1776 {
1777 .start = AT91SAM9G45_BASE_SHA,
1778 .end = AT91SAM9G45_BASE_SHA + SZ_16K - 1,
1779 .flags = IORESOURCE_MEM,
1780 },
1781 [1] = {
1782 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1783 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1784 .flags = IORESOURCE_IRQ,
1785 },
1786};
1787
1788static struct platform_device at91sam9g45_sha_device = {
1789 .name = "atmel_sha",
1790 .id = -1,
1791 .resource = sha_resources,
1792 .num_resources = ARRAY_SIZE(sha_resources),
1793};
1794
1795static void __init at91_add_device_sha(void)
1796{
1797 platform_device_register(&at91sam9g45_sha_device);
1798}
1799#else
1800static void __init at91_add_device_sha(void) {}
1801#endif
1802
1803/* --------------------------------------------------------------------
1804 * DES/TDES
1805 * -------------------------------------------------------------------- */
1806
1807#if defined(CONFIG_CRYPTO_DEV_ATMEL_TDES) || defined(CONFIG_CRYPTO_DEV_ATMEL_TDES_MODULE)
1808static struct resource tdes_resources[] = {
1809 [0] = {
1810 .start = AT91SAM9G45_BASE_TDES,
1811 .end = AT91SAM9G45_BASE_TDES + SZ_16K - 1,
1812 .flags = IORESOURCE_MEM,
1813 },
1814 [1] = {
1815 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1816 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1817 .flags = IORESOURCE_IRQ,
1818 },
1819};
1820
1821static struct platform_device at91sam9g45_tdes_device = {
1822 .name = "atmel_tdes",
1823 .id = -1,
1824 .resource = tdes_resources,
1825 .num_resources = ARRAY_SIZE(tdes_resources),
1826};
1827
1828static void __init at91_add_device_tdes(void)
1829{
1830 platform_device_register(&at91sam9g45_tdes_device);
1831}
1832#else
1833static void __init at91_add_device_tdes(void) {}
1834#endif
1835
1836/* --------------------------------------------------------------------
1837 * AES
1838 * -------------------------------------------------------------------- */
1839
1840#if defined(CONFIG_CRYPTO_DEV_ATMEL_AES) || defined(CONFIG_CRYPTO_DEV_ATMEL_AES_MODULE)
1841static struct crypto_platform_data aes_data;
1842static struct crypto_dma_data alt_atslave;
1843static u64 aes_dmamask = DMA_BIT_MASK(32);
1844
1845static struct resource aes_resources[] = {
1846 [0] = {
1847 .start = AT91SAM9G45_BASE_AES,
1848 .end = AT91SAM9G45_BASE_AES + SZ_16K - 1,
1849 .flags = IORESOURCE_MEM,
1850 },
1851 [1] = {
1852 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1853 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1854 .flags = IORESOURCE_IRQ,
1855 },
1856};
1857
1858static struct platform_device at91sam9g45_aes_device = {
1859 .name = "atmel_aes",
1860 .id = -1,
1861 .dev = {
1862 .dma_mask = &aes_dmamask,
1863 .coherent_dma_mask = DMA_BIT_MASK(32),
1864 .platform_data = &aes_data,
1865 },
1866 .resource = aes_resources,
1867 .num_resources = ARRAY_SIZE(aes_resources),
1868};
1869
1870static void __init at91_add_device_aes(void)
1871{
1872 struct at_dma_slave *atslave;
1873
1874 /* DMA TX slave channel configuration */
1875 atslave = &alt_atslave.txdata;
1876 atslave->dma_dev = &at_hdmac_device.dev;
1877 atslave->cfg = ATC_FIFOCFG_ENOUGHSPACE | ATC_SRC_H2SEL_HW |
1878 ATC_SRC_PER(AT_DMA_ID_AES_RX);
1879
1880 /* DMA RX slave channel configuration */
1881 atslave = &alt_atslave.rxdata;
1882 atslave->dma_dev = &at_hdmac_device.dev;
1883 atslave->cfg = ATC_FIFOCFG_ENOUGHSPACE | ATC_DST_H2SEL_HW |
1884 ATC_DST_PER(AT_DMA_ID_AES_TX);
1885
1886 aes_data.dma_slave = &alt_atslave;
1887 platform_device_register(&at91sam9g45_aes_device);
1888}
1889#else
1890static void __init at91_add_device_aes(void) {}
1891#endif
1892
1893/* -------------------------------------------------------------------- */
1894/*
1895 * These devices are always present and don't need any board-specific
1896 * setup.
1897 */
1898static int __init at91_add_standard_devices(void)
1899{
1900 if (of_have_populated_dt())
1901 return 0;
1902
1903 at91_add_device_hdmac();
1904 at91_add_device_rtc();
1905 at91_add_device_rtt();
1906 at91_add_device_trng();
1907 at91_add_device_watchdog();
1908 at91_add_device_tc();
1909 at91_add_device_sha();
1910 at91_add_device_tdes();
1911 at91_add_device_aes();
1912 return 0;
1913}
1914
1915arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index c8988fe5ff70..dee569b1987e 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -6,219 +6,11 @@
6 * Licensed under GPLv2 or later. 6 * Licensed under GPLv2 or later.
7 */ 7 */
8 8
9#include <linux/module.h> 9#include <asm/system_misc.h>
10#include <linux/dma-mapping.h> 10#include <mach/hardware.h>
11#include <linux/clk/at91_pmc.h>
12 11
13#include <asm/irq.h>
14#include <asm/mach/arch.h>
15#include <asm/mach/map.h>
16#include <mach/at91sam9n12.h>
17#include <mach/cpu.h>
18
19#include "board.h"
20#include "soc.h" 12#include "soc.h"
21#include "generic.h" 13#include "generic.h"
22#include "sam9_smc.h"
23
24#if defined(CONFIG_OLD_CLK_AT91)
25#include "clock.h"
26/* --------------------------------------------------------------------
27 * Clocks
28 * -------------------------------------------------------------------- */
29
30/*
31 * The peripheral clocks.
32 */
33static struct clk pioAB_clk = {
34 .name = "pioAB_clk",
35 .pmc_mask = 1 << AT91SAM9N12_ID_PIOAB,
36 .type = CLK_TYPE_PERIPHERAL,
37};
38static struct clk pioCD_clk = {
39 .name = "pioCD_clk",
40 .pmc_mask = 1 << AT91SAM9N12_ID_PIOCD,
41 .type = CLK_TYPE_PERIPHERAL,
42};
43static struct clk usart0_clk = {
44 .name = "usart0_clk",
45 .pmc_mask = 1 << AT91SAM9N12_ID_USART0,
46 .type = CLK_TYPE_PERIPHERAL,
47};
48static struct clk usart1_clk = {
49 .name = "usart1_clk",
50 .pmc_mask = 1 << AT91SAM9N12_ID_USART1,
51 .type = CLK_TYPE_PERIPHERAL,
52};
53static struct clk usart2_clk = {
54 .name = "usart2_clk",
55 .pmc_mask = 1 << AT91SAM9N12_ID_USART2,
56 .type = CLK_TYPE_PERIPHERAL,
57};
58static struct clk usart3_clk = {
59 .name = "usart3_clk",
60 .pmc_mask = 1 << AT91SAM9N12_ID_USART3,
61 .type = CLK_TYPE_PERIPHERAL,
62};
63static struct clk twi0_clk = {
64 .name = "twi0_clk",
65 .pmc_mask = 1 << AT91SAM9N12_ID_TWI0,
66 .type = CLK_TYPE_PERIPHERAL,
67};
68static struct clk twi1_clk = {
69 .name = "twi1_clk",
70 .pmc_mask = 1 << AT91SAM9N12_ID_TWI1,
71 .type = CLK_TYPE_PERIPHERAL,
72};
73static struct clk mmc_clk = {
74 .name = "mci_clk",
75 .pmc_mask = 1 << AT91SAM9N12_ID_MCI,
76 .type = CLK_TYPE_PERIPHERAL,
77};
78static struct clk spi0_clk = {
79 .name = "spi0_clk",
80 .pmc_mask = 1 << AT91SAM9N12_ID_SPI0,
81 .type = CLK_TYPE_PERIPHERAL,
82};
83static struct clk spi1_clk = {
84 .name = "spi1_clk",
85 .pmc_mask = 1 << AT91SAM9N12_ID_SPI1,
86 .type = CLK_TYPE_PERIPHERAL,
87};
88static struct clk uart0_clk = {
89 .name = "uart0_clk",
90 .pmc_mask = 1 << AT91SAM9N12_ID_UART0,
91 .type = CLK_TYPE_PERIPHERAL,
92};
93static struct clk uart1_clk = {
94 .name = "uart1_clk",
95 .pmc_mask = 1 << AT91SAM9N12_ID_UART1,
96 .type = CLK_TYPE_PERIPHERAL,
97};
98static struct clk tcb_clk = {
99 .name = "tcb_clk",
100 .pmc_mask = 1 << AT91SAM9N12_ID_TCB,
101 .type = CLK_TYPE_PERIPHERAL,
102};
103static struct clk pwm_clk = {
104 .name = "pwm_clk",
105 .pmc_mask = 1 << AT91SAM9N12_ID_PWM,
106 .type = CLK_TYPE_PERIPHERAL,
107};
108static struct clk adc_clk = {
109 .name = "adc_clk",
110 .pmc_mask = 1 << AT91SAM9N12_ID_ADC,
111 .type = CLK_TYPE_PERIPHERAL,
112};
113static struct clk dma_clk = {
114 .name = "dma_clk",
115 .pmc_mask = 1 << AT91SAM9N12_ID_DMA,
116 .type = CLK_TYPE_PERIPHERAL,
117};
118static struct clk uhp_clk = {
119 .name = "uhp",
120 .pmc_mask = 1 << AT91SAM9N12_ID_UHP,
121 .type = CLK_TYPE_PERIPHERAL,
122};
123static struct clk udp_clk = {
124 .name = "udp_clk",
125 .pmc_mask = 1 << AT91SAM9N12_ID_UDP,
126 .type = CLK_TYPE_PERIPHERAL,
127};
128static struct clk lcdc_clk = {
129 .name = "lcdc_clk",
130 .pmc_mask = 1 << AT91SAM9N12_ID_LCDC,
131 .type = CLK_TYPE_PERIPHERAL,
132};
133static struct clk ssc_clk = {
134 .name = "ssc_clk",
135 .pmc_mask = 1 << AT91SAM9N12_ID_SSC,
136 .type = CLK_TYPE_PERIPHERAL,
137};
138
139static struct clk *periph_clocks[] __initdata = {
140 &pioAB_clk,
141 &pioCD_clk,
142 &usart0_clk,
143 &usart1_clk,
144 &usart2_clk,
145 &usart3_clk,
146 &twi0_clk,
147 &twi1_clk,
148 &mmc_clk,
149 &spi0_clk,
150 &spi1_clk,
151 &lcdc_clk,
152 &uart0_clk,
153 &uart1_clk,
154 &tcb_clk,
155 &pwm_clk,
156 &adc_clk,
157 &dma_clk,
158 &uhp_clk,
159 &udp_clk,
160 &ssc_clk,
161};
162
163static struct clk_lookup periph_clocks_lookups[] = {
164 /* lookup table for DT entries */
165 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
166 CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
167 CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
168 CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
169 CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
170 CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk),
171 CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk),
172 CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc_clk),
173 CLKDEV_CON_DEV_ID(NULL, "f0010000.ssc", &ssc_clk),
174 CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
175 CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
176 CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
177 CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
178 CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
179 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
180 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
181 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
182 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
183 /* additional fake clock for macb_hclk */
184 CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &uhp_clk),
185 CLKDEV_CON_DEV_ID("ohci_clk", "500000.ohci", &uhp_clk),
186 CLKDEV_CON_DEV_ID(NULL, "f8034000.pwm", &pwm_clk),
187};
188
189/*
190 * The two programmable clocks.
191 * You must configure pin multiplexing to bring these signals out.
192 */
193static struct clk pck0 = {
194 .name = "pck0",
195 .pmc_mask = AT91_PMC_PCK0,
196 .type = CLK_TYPE_PROGRAMMABLE,
197 .id = 0,
198};
199static struct clk pck1 = {
200 .name = "pck1",
201 .pmc_mask = AT91_PMC_PCK1,
202 .type = CLK_TYPE_PROGRAMMABLE,
203 .id = 1,
204};
205
206static void __init at91sam9n12_register_clocks(void)
207{
208 int i;
209
210 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
211 clk_register(periph_clocks[i]);
212 clk_register(&pck0);
213 clk_register(&pck1);
214
215 clkdev_add_table(periph_clocks_lookups,
216 ARRAY_SIZE(periph_clocks_lookups));
217
218}
219#else
220#define at91sam9n12_register_clocks NULL
221#endif
222 14
223/* -------------------------------------------------------------------- 15/* --------------------------------------------------------------------
224 * AT91SAM9N12 processor initialization 16 * AT91SAM9N12 processor initialization
@@ -236,6 +28,5 @@ static void __init at91sam9n12_initialize(void)
236 28
237AT91_SOC_START(at91sam9n12) 29AT91_SOC_START(at91sam9n12)
238 .map_io = at91sam9n12_map_io, 30 .map_io = at91sam9n12_map_io,
239 .register_clocks = at91sam9n12_register_clocks,
240 .init = at91sam9n12_initialize, 31 .init = at91sam9n12_initialize,
241AT91_SOC_END 32AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index f553e4ea034b..bd7e56889b43 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -9,284 +9,13 @@
9 * more details. 9 * more details.
10 */ 10 */
11 11
12#include <linux/module.h>
13#include <linux/platform_device.h>
14#include <linux/clk/at91_pmc.h>
15
16#include <asm/proc-fns.h>
17#include <asm/irq.h>
18#include <asm/mach/arch.h>
19#include <asm/mach/map.h>
20#include <asm/system_misc.h> 12#include <asm/system_misc.h>
21#include <mach/cpu.h> 13#include <mach/cpu.h>
22#include <mach/at91_dbgu.h> 14#include <mach/at91_dbgu.h>
23#include <mach/at91sam9rl.h>
24#include <mach/hardware.h> 15#include <mach/hardware.h>
25 16
26#include "at91_aic.h"
27#include "soc.h" 17#include "soc.h"
28#include "generic.h" 18#include "generic.h"
29#include "sam9_smc.h"
30#include "pm.h"
31
32/* --------------------------------------------------------------------
33 * Clocks
34 * -------------------------------------------------------------------- */
35#if defined(CONFIG_OLD_CLK_AT91)
36#include "clock.h"
37
38/*
39 * The peripheral clocks.
40 */
41static struct clk pioA_clk = {
42 .name = "pioA_clk",
43 .pmc_mask = 1 << AT91SAM9RL_ID_PIOA,
44 .type = CLK_TYPE_PERIPHERAL,
45};
46static struct clk pioB_clk = {
47 .name = "pioB_clk",
48 .pmc_mask = 1 << AT91SAM9RL_ID_PIOB,
49 .type = CLK_TYPE_PERIPHERAL,
50};
51static struct clk pioC_clk = {
52 .name = "pioC_clk",
53 .pmc_mask = 1 << AT91SAM9RL_ID_PIOC,
54 .type = CLK_TYPE_PERIPHERAL,
55};
56static struct clk pioD_clk = {
57 .name = "pioD_clk",
58 .pmc_mask = 1 << AT91SAM9RL_ID_PIOD,
59 .type = CLK_TYPE_PERIPHERAL,
60};
61static struct clk usart0_clk = {
62 .name = "usart0_clk",
63 .pmc_mask = 1 << AT91SAM9RL_ID_US0,
64 .type = CLK_TYPE_PERIPHERAL,
65};
66static struct clk usart1_clk = {
67 .name = "usart1_clk",
68 .pmc_mask = 1 << AT91SAM9RL_ID_US1,
69 .type = CLK_TYPE_PERIPHERAL,
70};
71static struct clk usart2_clk = {
72 .name = "usart2_clk",
73 .pmc_mask = 1 << AT91SAM9RL_ID_US2,
74 .type = CLK_TYPE_PERIPHERAL,
75};
76static struct clk usart3_clk = {
77 .name = "usart3_clk",
78 .pmc_mask = 1 << AT91SAM9RL_ID_US3,
79 .type = CLK_TYPE_PERIPHERAL,
80};
81static struct clk mmc_clk = {
82 .name = "mci_clk",
83 .pmc_mask = 1 << AT91SAM9RL_ID_MCI,
84 .type = CLK_TYPE_PERIPHERAL,
85};
86static struct clk twi0_clk = {
87 .name = "twi0_clk",
88 .pmc_mask = 1 << AT91SAM9RL_ID_TWI0,
89 .type = CLK_TYPE_PERIPHERAL,
90};
91static struct clk twi1_clk = {
92 .name = "twi1_clk",
93 .pmc_mask = 1 << AT91SAM9RL_ID_TWI1,
94 .type = CLK_TYPE_PERIPHERAL,
95};
96static struct clk spi_clk = {
97 .name = "spi_clk",
98 .pmc_mask = 1 << AT91SAM9RL_ID_SPI,
99 .type = CLK_TYPE_PERIPHERAL,
100};
101static struct clk ssc0_clk = {
102 .name = "ssc0_clk",
103 .pmc_mask = 1 << AT91SAM9RL_ID_SSC0,
104 .type = CLK_TYPE_PERIPHERAL,
105};
106static struct clk ssc1_clk = {
107 .name = "ssc1_clk",
108 .pmc_mask = 1 << AT91SAM9RL_ID_SSC1,
109 .type = CLK_TYPE_PERIPHERAL,
110};
111static struct clk tc0_clk = {
112 .name = "tc0_clk",
113 .pmc_mask = 1 << AT91SAM9RL_ID_TC0,
114 .type = CLK_TYPE_PERIPHERAL,
115};
116static struct clk tc1_clk = {
117 .name = "tc1_clk",
118 .pmc_mask = 1 << AT91SAM9RL_ID_TC1,
119 .type = CLK_TYPE_PERIPHERAL,
120};
121static struct clk tc2_clk = {
122 .name = "tc2_clk",
123 .pmc_mask = 1 << AT91SAM9RL_ID_TC2,
124 .type = CLK_TYPE_PERIPHERAL,
125};
126static struct clk pwm_clk = {
127 .name = "pwm_clk",
128 .pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
129 .type = CLK_TYPE_PERIPHERAL,
130};
131static struct clk tsc_clk = {
132 .name = "tsc_clk",
133 .pmc_mask = 1 << AT91SAM9RL_ID_TSC,
134 .type = CLK_TYPE_PERIPHERAL,
135};
136static struct clk dma_clk = {
137 .name = "dma_clk",
138 .pmc_mask = 1 << AT91SAM9RL_ID_DMA,
139 .type = CLK_TYPE_PERIPHERAL,
140};
141static struct clk udphs_clk = {
142 .name = "udphs_clk",
143 .pmc_mask = 1 << AT91SAM9RL_ID_UDPHS,
144 .type = CLK_TYPE_PERIPHERAL,
145};
146static struct clk lcdc_clk = {
147 .name = "lcdc_clk",
148 .pmc_mask = 1 << AT91SAM9RL_ID_LCDC,
149 .type = CLK_TYPE_PERIPHERAL,
150};
151static struct clk ac97_clk = {
152 .name = "ac97_clk",
153 .pmc_mask = 1 << AT91SAM9RL_ID_AC97C,
154 .type = CLK_TYPE_PERIPHERAL,
155};
156static struct clk adc_op_clk = {
157 .name = "adc_op_clk",
158 .type = CLK_TYPE_PERIPHERAL,
159 .rate_hz = 1000000,
160};
161
162static struct clk *periph_clocks[] __initdata = {
163 &pioA_clk,
164 &pioB_clk,
165 &pioC_clk,
166 &pioD_clk,
167 &usart0_clk,
168 &usart1_clk,
169 &usart2_clk,
170 &usart3_clk,
171 &mmc_clk,
172 &twi0_clk,
173 &twi1_clk,
174 &spi_clk,
175 &ssc0_clk,
176 &ssc1_clk,
177 &tc0_clk,
178 &tc1_clk,
179 &tc2_clk,
180 &pwm_clk,
181 &tsc_clk,
182 &dma_clk,
183 &udphs_clk,
184 &lcdc_clk,
185 &ac97_clk,
186 &adc_op_clk,
187 // irq0
188};
189
190static struct clk_lookup periph_clocks_lookups[] = {
191 CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk),
192 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
193 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
194 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
195 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
196 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
197 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
198 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
199 CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc0_clk),
200 CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc1_clk),
201 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk),
202 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk),
203 CLKDEV_CON_DEV_ID(NULL, "at91sam9rl-pwm", &pwm_clk),
204 CLKDEV_CON_ID("pioA", &pioA_clk),
205 CLKDEV_CON_ID("pioB", &pioB_clk),
206 CLKDEV_CON_ID("pioC", &pioC_clk),
207 CLKDEV_CON_ID("pioD", &pioD_clk),
208 /* more lookup table for DT entries */
209 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
210 CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
211 CLKDEV_CON_DEV_ID("usart", "ffffb400.serial", &usart1_clk),
212 CLKDEV_CON_DEV_ID("usart", "ffffb800.serial", &usart2_clk),
213 CLKDEV_CON_DEV_ID("usart", "ffffbc00.serial", &usart3_clk),
214 CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
215 CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
216 CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
217 CLKDEV_CON_DEV_ID("mci_clk", "fffa4000.mmc", &mmc_clk),
218 CLKDEV_CON_DEV_ID(NULL, "fffa8000.i2c", &twi0_clk),
219 CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi1_clk),
220 CLKDEV_CON_DEV_ID(NULL, "fffc8000.pwm", &pwm_clk),
221 CLKDEV_CON_DEV_ID(NULL, "ffffc800.pwm", &pwm_clk),
222 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
223 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
224 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
225 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk),
226 CLKDEV_CON_ID("adc_clk", &tsc_clk),
227};
228
229static struct clk_lookup usart_clocks_lookups[] = {
230 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
231 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
232 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
233 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
234 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
235};
236
237/*
238 * The two programmable clocks.
239 * You must configure pin multiplexing to bring these signals out.
240 */
241static struct clk pck0 = {
242 .name = "pck0",
243 .pmc_mask = AT91_PMC_PCK0,
244 .type = CLK_TYPE_PROGRAMMABLE,
245 .id = 0,
246};
247static struct clk pck1 = {
248 .name = "pck1",
249 .pmc_mask = AT91_PMC_PCK1,
250 .type = CLK_TYPE_PROGRAMMABLE,
251 .id = 1,
252};
253
254static void __init at91sam9rl_register_clocks(void)
255{
256 int i;
257
258 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
259 clk_register(periph_clocks[i]);
260
261 clkdev_add_table(periph_clocks_lookups,
262 ARRAY_SIZE(periph_clocks_lookups));
263 clkdev_add_table(usart_clocks_lookups,
264 ARRAY_SIZE(usart_clocks_lookups));
265
266 clk_register(&pck0);
267 clk_register(&pck1);
268}
269#endif
270
271/* --------------------------------------------------------------------
272 * GPIO
273 * -------------------------------------------------------------------- */
274
275static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = {
276 {
277 .id = AT91SAM9RL_ID_PIOA,
278 .regbase = AT91SAM9RL_BASE_PIOA,
279 }, {
280 .id = AT91SAM9RL_ID_PIOB,
281 .regbase = AT91SAM9RL_BASE_PIOB,
282 }, {
283 .id = AT91SAM9RL_ID_PIOC,
284 .regbase = AT91SAM9RL_BASE_PIOC,
285 }, {
286 .id = AT91SAM9RL_ID_PIOD,
287 .regbase = AT91SAM9RL_BASE_PIOD,
288 }
289};
290 19
291/* -------------------------------------------------------------------- 20/* --------------------------------------------------------------------
292 * AT91SAM9RL processor initialization 21 * AT91SAM9RL processor initialization
@@ -309,121 +38,15 @@ static void __init at91sam9rl_map_io(void)
309 at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size); 38 at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
310} 39}
311 40
312static void __init at91sam9rl_ioremap_registers(void)
313{
314 at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
315 at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
316 at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
317 at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
318 at91_pm_set_standby(at91sam9_sdram_standby);
319}
320
321static void __init at91sam9rl_initialize(void) 41static void __init at91sam9rl_initialize(void)
322{ 42{
323 arm_pm_idle = at91sam9_idle; 43 arm_pm_idle = at91sam9_idle;
324 44
325 at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC); 45 at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC);
326 at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT); 46 at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT);
327
328 /* Register GPIO subsystem */
329 at91_gpio_init(at91sam9rl_gpio, 4);
330}
331
332static struct resource rstc_resources[] = {
333 [0] = {
334 .start = AT91SAM9RL_BASE_RSTC,
335 .end = AT91SAM9RL_BASE_RSTC + SZ_16 - 1,
336 .flags = IORESOURCE_MEM,
337 },
338 [1] = {
339 .start = AT91SAM9RL_BASE_SDRAMC,
340 .end = AT91SAM9RL_BASE_SDRAMC + SZ_512 - 1,
341 .flags = IORESOURCE_MEM,
342 },
343};
344
345static struct platform_device rstc_device = {
346 .name = "at91-sam9260-reset",
347 .resource = rstc_resources,
348 .num_resources = ARRAY_SIZE(rstc_resources),
349};
350
351static struct resource shdwc_resources[] = {
352 [0] = {
353 .start = AT91SAM9RL_BASE_SHDWC,
354 .end = AT91SAM9RL_BASE_SHDWC + SZ_16 - 1,
355 .flags = IORESOURCE_MEM,
356 },
357};
358
359static struct platform_device shdwc_device = {
360 .name = "at91-poweroff",
361 .resource = shdwc_resources,
362 .num_resources = ARRAY_SIZE(shdwc_resources),
363};
364
365static void __init at91sam9rl_register_devices(void)
366{
367 platform_device_register(&rstc_device);
368 platform_device_register(&shdwc_device);
369}
370
371/* --------------------------------------------------------------------
372 * Interrupt initialization
373 * -------------------------------------------------------------------- */
374
375/*
376 * The default interrupt priority levels (0 = lowest, 7 = highest).
377 */
378static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
379 7, /* Advanced Interrupt Controller */
380 7, /* System Peripherals */
381 1, /* Parallel IO Controller A */
382 1, /* Parallel IO Controller B */
383 1, /* Parallel IO Controller C */
384 1, /* Parallel IO Controller D */
385 5, /* USART 0 */
386 5, /* USART 1 */
387 5, /* USART 2 */
388 5, /* USART 3 */
389 0, /* Multimedia Card Interface */
390 6, /* Two-Wire Interface 0 */
391 6, /* Two-Wire Interface 1 */
392 5, /* Serial Peripheral Interface */
393 4, /* Serial Synchronous Controller 0 */
394 4, /* Serial Synchronous Controller 1 */
395 0, /* Timer Counter 0 */
396 0, /* Timer Counter 1 */
397 0, /* Timer Counter 2 */
398 0,
399 0, /* Touch Screen Controller */
400 0, /* DMA Controller */
401 2, /* USB Device High speed port */
402 2, /* LCD Controller */
403 6, /* AC97 Controller */
404 0,
405 0,
406 0,
407 0,
408 0,
409 0,
410 0, /* Advanced Interrupt Controller */
411};
412
413static void __init at91sam9rl_init_time(void)
414{
415 at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS);
416} 47}
417 48
418AT91_SOC_START(at91sam9rl) 49AT91_SOC_START(at91sam9rl)
419 .map_io = at91sam9rl_map_io, 50 .map_io = at91sam9rl_map_io,
420 .default_irq_priority = at91sam9rl_default_irq_priority,
421 .extern_irq = (1 << AT91SAM9RL_ID_IRQ0),
422 .ioremap_registers = at91sam9rl_ioremap_registers,
423#if defined(CONFIG_OLD_CLK_AT91)
424 .register_clocks = at91sam9rl_register_clocks,
425#endif
426 .register_devices = at91sam9rl_register_devices,
427 .init = at91sam9rl_initialize, 51 .init = at91sam9rl_initialize,
428 .init_time = at91sam9rl_init_time,
429AT91_SOC_END 52AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
deleted file mode 100644
index 37d1c9ed4562..000000000000
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ /dev/null
@@ -1,1260 +0,0 @@
1/*
2 * Copyright (C) 2007 Atmel Corporation
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file COPYING in the main directory of this archive for
6 * more details.
7 */
8
9#include <asm/mach/arch.h>
10#include <asm/mach/map.h>
11
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14#include <linux/platform_device.h>
15#include <linux/i2c-gpio.h>
16
17#include <linux/fb.h>
18#include <video/atmel_lcdc.h>
19
20#include <mach/at91sam9rl.h>
21#include <mach/at91sam9rl_matrix.h>
22#include <mach/at91_matrix.h>
23#include <mach/at91sam9_smc.h>
24#include <mach/hardware.h>
25#include <linux/platform_data/dma-atmel.h>
26#include <linux/platform_data/at91_adc.h>
27
28#include "board.h"
29#include "generic.h"
30#include "gpio.h"
31
32
33/* --------------------------------------------------------------------
34 * HDMAC - AHB DMA Controller
35 * -------------------------------------------------------------------- */
36
37#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
38static u64 hdmac_dmamask = DMA_BIT_MASK(32);
39
40static struct resource hdmac_resources[] = {
41 [0] = {
42 .start = AT91SAM9RL_BASE_DMA,
43 .end = AT91SAM9RL_BASE_DMA + SZ_512 - 1,
44 .flags = IORESOURCE_MEM,
45 },
46 [2] = {
47 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_DMA,
48 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_DMA,
49 .flags = IORESOURCE_IRQ,
50 },
51};
52
53static struct platform_device at_hdmac_device = {
54 .name = "at91sam9rl_dma",
55 .id = -1,
56 .dev = {
57 .dma_mask = &hdmac_dmamask,
58 .coherent_dma_mask = DMA_BIT_MASK(32),
59 },
60 .resource = hdmac_resources,
61 .num_resources = ARRAY_SIZE(hdmac_resources),
62};
63
64void __init at91_add_device_hdmac(void)
65{
66 platform_device_register(&at_hdmac_device);
67}
68#else
69void __init at91_add_device_hdmac(void) {}
70#endif
71
72/* --------------------------------------------------------------------
73 * USB HS Device (Gadget)
74 * -------------------------------------------------------------------- */
75
76#if defined(CONFIG_USB_ATMEL_USBA) || defined(CONFIG_USB_ATMEL_USBA_MODULE)
77
78static struct resource usba_udc_resources[] = {
79 [0] = {
80 .start = AT91SAM9RL_UDPHS_FIFO,
81 .end = AT91SAM9RL_UDPHS_FIFO + SZ_512K - 1,
82 .flags = IORESOURCE_MEM,
83 },
84 [1] = {
85 .start = AT91SAM9RL_BASE_UDPHS,
86 .end = AT91SAM9RL_BASE_UDPHS + SZ_1K - 1,
87 .flags = IORESOURCE_MEM,
88 },
89 [2] = {
90 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_UDPHS,
91 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_UDPHS,
92 .flags = IORESOURCE_IRQ,
93 },
94};
95
96#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
97 [idx] = { \
98 .name = nam, \
99 .index = idx, \
100 .fifo_size = maxpkt, \
101 .nr_banks = maxbk, \
102 .can_dma = dma, \
103 .can_isoc = isoc, \
104 }
105
106static struct usba_ep_data usba_udc_ep[] __initdata = {
107 EP("ep0", 0, 64, 1, 0, 0),
108 EP("ep1", 1, 1024, 2, 1, 1),
109 EP("ep2", 2, 1024, 2, 1, 1),
110 EP("ep3", 3, 1024, 3, 1, 0),
111 EP("ep4", 4, 1024, 3, 1, 0),
112 EP("ep5", 5, 1024, 3, 1, 1),
113 EP("ep6", 6, 1024, 3, 1, 1),
114};
115
116#undef EP
117
118/*
119 * pdata doesn't have room for any endpoints, so we need to
120 * append room for the ones we need right after it.
121 */
122static struct {
123 struct usba_platform_data pdata;
124 struct usba_ep_data ep[7];
125} usba_udc_data;
126
127static struct platform_device at91_usba_udc_device = {
128 .name = "atmel_usba_udc",
129 .id = -1,
130 .dev = {
131 .platform_data = &usba_udc_data.pdata,
132 },
133 .resource = usba_udc_resources,
134 .num_resources = ARRAY_SIZE(usba_udc_resources),
135};
136
137void __init at91_add_device_usba(struct usba_platform_data *data)
138{
139 /*
140 * Invalid pins are 0 on AT91, but the usba driver is shared
141 * with AVR32, which use negative values instead. Once/if
142 * gpio_is_valid() is ported to AT91, revisit this code.
143 */
144 usba_udc_data.pdata.vbus_pin = -EINVAL;
145 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
146 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
147
148 if (data && gpio_is_valid(data->vbus_pin)) {
149 at91_set_gpio_input(data->vbus_pin, 0);
150 at91_set_deglitch(data->vbus_pin, 1);
151 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
152 }
153
154 /* Pullup pin is handled internally by USB device peripheral */
155
156 platform_device_register(&at91_usba_udc_device);
157}
158#else
159void __init at91_add_device_usba(struct usba_platform_data *data) {}
160#endif
161
162
163/* --------------------------------------------------------------------
164 * MMC / SD
165 * -------------------------------------------------------------------- */
166
167#if IS_ENABLED(CONFIG_MMC_ATMELMCI)
168static u64 mmc_dmamask = DMA_BIT_MASK(32);
169static struct mci_platform_data mmc_data;
170
171static struct resource mmc_resources[] = {
172 [0] = {
173 .start = AT91SAM9RL_BASE_MCI,
174 .end = AT91SAM9RL_BASE_MCI + SZ_16K - 1,
175 .flags = IORESOURCE_MEM,
176 },
177 [1] = {
178 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_MCI,
179 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_MCI,
180 .flags = IORESOURCE_IRQ,
181 },
182};
183
184static struct platform_device at91sam9rl_mmc_device = {
185 .name = "atmel_mci",
186 .id = -1,
187 .dev = {
188 .dma_mask = &mmc_dmamask,
189 .coherent_dma_mask = DMA_BIT_MASK(32),
190 .platform_data = &mmc_data,
191 },
192 .resource = mmc_resources,
193 .num_resources = ARRAY_SIZE(mmc_resources),
194};
195
196void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
197{
198 if (!data)
199 return;
200
201 if (data->slot[0].bus_width) {
202 /* input/irq */
203 if (gpio_is_valid(data->slot[0].detect_pin)) {
204 at91_set_gpio_input(data->slot[0].detect_pin, 1);
205 at91_set_deglitch(data->slot[0].detect_pin, 1);
206 }
207 if (gpio_is_valid(data->slot[0].wp_pin))
208 at91_set_gpio_input(data->slot[0].wp_pin, 1);
209
210 /* CLK */
211 at91_set_A_periph(AT91_PIN_PA2, 0);
212
213 /* CMD */
214 at91_set_A_periph(AT91_PIN_PA1, 1);
215
216 /* DAT0, maybe DAT1..DAT3 */
217 at91_set_A_periph(AT91_PIN_PA0, 1);
218 if (data->slot[0].bus_width == 4) {
219 at91_set_A_periph(AT91_PIN_PA3, 1);
220 at91_set_A_periph(AT91_PIN_PA4, 1);
221 at91_set_A_periph(AT91_PIN_PA5, 1);
222 }
223
224 mmc_data = *data;
225 platform_device_register(&at91sam9rl_mmc_device);
226 }
227}
228#else
229void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
230#endif
231
232
233/* --------------------------------------------------------------------
234 * NAND / SmartMedia
235 * -------------------------------------------------------------------- */
236
237#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
238static struct atmel_nand_data nand_data;
239
240#define NAND_BASE AT91_CHIPSELECT_3
241
242static struct resource nand_resources[] = {
243 [0] = {
244 .start = NAND_BASE,
245 .end = NAND_BASE + SZ_256M - 1,
246 .flags = IORESOURCE_MEM,
247 },
248 [1] = {
249 .start = AT91SAM9RL_BASE_ECC,
250 .end = AT91SAM9RL_BASE_ECC + SZ_512 - 1,
251 .flags = IORESOURCE_MEM,
252 }
253};
254
255static struct platform_device atmel_nand_device = {
256 .name = "atmel_nand",
257 .id = -1,
258 .dev = {
259 .platform_data = &nand_data,
260 },
261 .resource = nand_resources,
262 .num_resources = ARRAY_SIZE(nand_resources),
263};
264
265void __init at91_add_device_nand(struct atmel_nand_data *data)
266{
267 unsigned long csa;
268
269 if (!data)
270 return;
271
272 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
273 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
274
275 /* enable pin */
276 if (gpio_is_valid(data->enable_pin))
277 at91_set_gpio_output(data->enable_pin, 1);
278
279 /* ready/busy pin */
280 if (gpio_is_valid(data->rdy_pin))
281 at91_set_gpio_input(data->rdy_pin, 1);
282
283 /* card detect pin */
284 if (gpio_is_valid(data->det_pin))
285 at91_set_gpio_input(data->det_pin, 1);
286
287 at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
288 at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
289
290 nand_data = *data;
291 platform_device_register(&atmel_nand_device);
292}
293
294#else
295void __init at91_add_device_nand(struct atmel_nand_data *data) {}
296#endif
297
298
299/* --------------------------------------------------------------------
300 * TWI (i2c)
301 * -------------------------------------------------------------------- */
302
303/*
304 * Prefer the GPIO code since the TWI controller isn't robust
305 * (gets overruns and underruns under load) and can only issue
306 * repeated STARTs in one scenario (the driver doesn't yet handle them).
307 */
308#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
309
310static struct i2c_gpio_platform_data pdata = {
311 .sda_pin = AT91_PIN_PA23,
312 .sda_is_open_drain = 1,
313 .scl_pin = AT91_PIN_PA24,
314 .scl_is_open_drain = 1,
315 .udelay = 2, /* ~100 kHz */
316};
317
318static struct platform_device at91sam9rl_twi_device = {
319 .name = "i2c-gpio",
320 .id = 0,
321 .dev.platform_data = &pdata,
322};
323
324void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
325{
326 at91_set_GPIO_periph(AT91_PIN_PA23, 1); /* TWD (SDA) */
327 at91_set_multi_drive(AT91_PIN_PA23, 1);
328
329 at91_set_GPIO_periph(AT91_PIN_PA24, 1); /* TWCK (SCL) */
330 at91_set_multi_drive(AT91_PIN_PA24, 1);
331
332 i2c_register_board_info(0, devices, nr_devices);
333 platform_device_register(&at91sam9rl_twi_device);
334}
335
336#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
337
338static struct resource twi_resources[] = {
339 [0] = {
340 .start = AT91SAM9RL_BASE_TWI0,
341 .end = AT91SAM9RL_BASE_TWI0 + SZ_16K - 1,
342 .flags = IORESOURCE_MEM,
343 },
344 [1] = {
345 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TWI0,
346 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TWI0,
347 .flags = IORESOURCE_IRQ,
348 },
349};
350
351static struct platform_device at91sam9rl_twi_device = {
352 .name = "i2c-at91sam9g20",
353 .id = 0,
354 .resource = twi_resources,
355 .num_resources = ARRAY_SIZE(twi_resources),
356};
357
358void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
359{
360 /* pins used for TWI interface */
361 at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */
362 at91_set_multi_drive(AT91_PIN_PA23, 1);
363
364 at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */
365 at91_set_multi_drive(AT91_PIN_PA24, 1);
366
367 i2c_register_board_info(0, devices, nr_devices);
368 platform_device_register(&at91sam9rl_twi_device);
369}
370#else
371void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
372#endif
373
374
375/* --------------------------------------------------------------------
376 * SPI
377 * -------------------------------------------------------------------- */
378
379#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
380static u64 spi_dmamask = DMA_BIT_MASK(32);
381
382static struct resource spi_resources[] = {
383 [0] = {
384 .start = AT91SAM9RL_BASE_SPI,
385 .end = AT91SAM9RL_BASE_SPI + SZ_16K - 1,
386 .flags = IORESOURCE_MEM,
387 },
388 [1] = {
389 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_SPI,
390 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_SPI,
391 .flags = IORESOURCE_IRQ,
392 },
393};
394
395static struct platform_device at91sam9rl_spi_device = {
396 .name = "atmel_spi",
397 .id = 0,
398 .dev = {
399 .dma_mask = &spi_dmamask,
400 .coherent_dma_mask = DMA_BIT_MASK(32),
401 },
402 .resource = spi_resources,
403 .num_resources = ARRAY_SIZE(spi_resources),
404};
405
406static const unsigned spi_standard_cs[4] = { AT91_PIN_PA28, AT91_PIN_PB7, AT91_PIN_PD8, AT91_PIN_PD9 };
407
408
409void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
410{
411 int i;
412 unsigned long cs_pin;
413
414 at91_set_A_periph(AT91_PIN_PA25, 0); /* MISO */
415 at91_set_A_periph(AT91_PIN_PA26, 0); /* MOSI */
416 at91_set_A_periph(AT91_PIN_PA27, 0); /* SPCK */
417
418 /* Enable SPI chip-selects */
419 for (i = 0; i < nr_devices; i++) {
420 if (devices[i].controller_data)
421 cs_pin = (unsigned long) devices[i].controller_data;
422 else
423 cs_pin = spi_standard_cs[devices[i].chip_select];
424
425 if (!gpio_is_valid(cs_pin))
426 continue;
427
428 /* enable chip-select pin */
429 at91_set_gpio_output(cs_pin, 1);
430
431 /* pass chip-select pin to driver */
432 devices[i].controller_data = (void *) cs_pin;
433 }
434
435 spi_register_board_info(devices, nr_devices);
436 platform_device_register(&at91sam9rl_spi_device);
437}
438#else
439void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
440#endif
441
442
443/* --------------------------------------------------------------------
444 * AC97
445 * -------------------------------------------------------------------- */
446
447#if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
448static u64 ac97_dmamask = DMA_BIT_MASK(32);
449static struct ac97c_platform_data ac97_data;
450
451static struct resource ac97_resources[] = {
452 [0] = {
453 .start = AT91SAM9RL_BASE_AC97C,
454 .end = AT91SAM9RL_BASE_AC97C + SZ_16K - 1,
455 .flags = IORESOURCE_MEM,
456 },
457 [1] = {
458 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_AC97C,
459 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_AC97C,
460 .flags = IORESOURCE_IRQ,
461 },
462};
463
464static struct platform_device at91sam9rl_ac97_device = {
465 .name = "atmel_ac97c",
466 .id = 0,
467 .dev = {
468 .dma_mask = &ac97_dmamask,
469 .coherent_dma_mask = DMA_BIT_MASK(32),
470 .platform_data = &ac97_data,
471 },
472 .resource = ac97_resources,
473 .num_resources = ARRAY_SIZE(ac97_resources),
474};
475
476void __init at91_add_device_ac97(struct ac97c_platform_data *data)
477{
478 if (!data)
479 return;
480
481 at91_set_A_periph(AT91_PIN_PD1, 0); /* AC97FS */
482 at91_set_A_periph(AT91_PIN_PD2, 0); /* AC97CK */
483 at91_set_A_periph(AT91_PIN_PD3, 0); /* AC97TX */
484 at91_set_A_periph(AT91_PIN_PD4, 0); /* AC97RX */
485
486 /* reset */
487 if (gpio_is_valid(data->reset_pin))
488 at91_set_gpio_output(data->reset_pin, 0);
489
490 ac97_data = *data;
491 platform_device_register(&at91sam9rl_ac97_device);
492}
493#else
494void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
495#endif
496
497
498/* --------------------------------------------------------------------
499 * LCD Controller
500 * -------------------------------------------------------------------- */
501
502#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
503static u64 lcdc_dmamask = DMA_BIT_MASK(32);
504static struct atmel_lcdfb_pdata lcdc_data;
505
506static struct resource lcdc_resources[] = {
507 [0] = {
508 .start = AT91SAM9RL_LCDC_BASE,
509 .end = AT91SAM9RL_LCDC_BASE + SZ_4K - 1,
510 .flags = IORESOURCE_MEM,
511 },
512 [1] = {
513 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_LCDC,
514 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_LCDC,
515 .flags = IORESOURCE_IRQ,
516 },
517};
518
519static struct platform_device at91_lcdc_device = {
520 .name = "at91sam9rl-lcdfb",
521 .id = 0,
522 .dev = {
523 .dma_mask = &lcdc_dmamask,
524 .coherent_dma_mask = DMA_BIT_MASK(32),
525 .platform_data = &lcdc_data,
526 },
527 .resource = lcdc_resources,
528 .num_resources = ARRAY_SIZE(lcdc_resources),
529};
530
531void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data)
532{
533 if (!data) {
534 return;
535 }
536
537 at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */
538 at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */
539 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */
540 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */
541 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */
542 at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */
543 at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */
544 at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */
545 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */
546 at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */
547 at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */
548 at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */
549 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */
550 at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */
551 at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */
552 at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */
553 at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */
554 at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */
555 at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */
556 at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */
557 at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */
558
559 lcdc_data = *data;
560 platform_device_register(&at91_lcdc_device);
561}
562#else
563void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) {}
564#endif
565
566
567/* --------------------------------------------------------------------
568 * Timer/Counter block
569 * -------------------------------------------------------------------- */
570
571#ifdef CONFIG_ATMEL_TCLIB
572
573static struct resource tcb_resources[] = {
574 [0] = {
575 .start = AT91SAM9RL_BASE_TCB0,
576 .end = AT91SAM9RL_BASE_TCB0 + SZ_16K - 1,
577 .flags = IORESOURCE_MEM,
578 },
579 [1] = {
580 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC0,
581 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC0,
582 .flags = IORESOURCE_IRQ,
583 },
584 [2] = {
585 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC1,
586 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC1,
587 .flags = IORESOURCE_IRQ,
588 },
589 [3] = {
590 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC2,
591 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC2,
592 .flags = IORESOURCE_IRQ,
593 },
594};
595
596static struct platform_device at91sam9rl_tcb_device = {
597 .name = "atmel_tcb",
598 .id = 0,
599 .resource = tcb_resources,
600 .num_resources = ARRAY_SIZE(tcb_resources),
601};
602
603static void __init at91_add_device_tc(void)
604{
605 platform_device_register(&at91sam9rl_tcb_device);
606}
607#else
608static void __init at91_add_device_tc(void) { }
609#endif
610
611
612/* --------------------------------------------------------------------
613 * ADC and Touchscreen
614 * -------------------------------------------------------------------- */
615
616#if IS_ENABLED(CONFIG_AT91_ADC)
617static struct at91_adc_data adc_data;
618
619static struct resource adc_resources[] = {
620 [0] = {
621 .start = AT91SAM9RL_BASE_TSC,
622 .end = AT91SAM9RL_BASE_TSC + SZ_16K - 1,
623 .flags = IORESOURCE_MEM,
624 },
625 [1] = {
626 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TSC,
627 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TSC,
628 .flags = IORESOURCE_IRQ,
629 }
630};
631
632static struct platform_device at91_adc_device = {
633 .name = "at91sam9rl-adc",
634 .id = -1,
635 .dev = {
636 .platform_data = &adc_data,
637 },
638 .resource = adc_resources,
639 .num_resources = ARRAY_SIZE(adc_resources),
640};
641
642static struct at91_adc_trigger at91_adc_triggers[] = {
643 [0] = {
644 .name = "external-rising",
645 .value = 1,
646 .is_external = true,
647 },
648 [1] = {
649 .name = "external-falling",
650 .value = 2,
651 .is_external = true,
652 },
653 [2] = {
654 .name = "external-any",
655 .value = 3,
656 .is_external = true,
657 },
658 [3] = {
659 .name = "continuous",
660 .value = 6,
661 .is_external = false,
662 },
663};
664
665void __init at91_add_device_adc(struct at91_adc_data *data)
666{
667 if (!data)
668 return;
669
670 if (test_bit(0, &data->channels_used))
671 at91_set_A_periph(AT91_PIN_PA17, 0);
672 if (test_bit(1, &data->channels_used))
673 at91_set_A_periph(AT91_PIN_PA18, 0);
674 if (test_bit(2, &data->channels_used))
675 at91_set_A_periph(AT91_PIN_PA19, 0);
676 if (test_bit(3, &data->channels_used))
677 at91_set_A_periph(AT91_PIN_PA20, 0);
678 if (test_bit(4, &data->channels_used))
679 at91_set_A_periph(AT91_PIN_PD6, 0);
680 if (test_bit(5, &data->channels_used))
681 at91_set_A_periph(AT91_PIN_PD7, 0);
682
683 if (data->use_external_triggers)
684 at91_set_A_periph(AT91_PIN_PB15, 0);
685
686 data->startup_time = 40;
687 data->trigger_number = 4;
688 data->trigger_list = at91_adc_triggers;
689
690 adc_data = *data;
691 platform_device_register(&at91_adc_device);
692}
693#else
694void __init at91_add_device_adc(struct at91_adc_data *data) {}
695#endif
696
697/* --------------------------------------------------------------------
698 * RTC
699 * -------------------------------------------------------------------- */
700
701#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
702static struct platform_device at91sam9rl_rtc_device = {
703 .name = "at91_rtc",
704 .id = -1,
705 .num_resources = 0,
706};
707
708static void __init at91_add_device_rtc(void)
709{
710 platform_device_register(&at91sam9rl_rtc_device);
711}
712#else
713static void __init at91_add_device_rtc(void) {}
714#endif
715
716
717/* --------------------------------------------------------------------
718 * RTT
719 * -------------------------------------------------------------------- */
720
721static struct resource rtt_resources[] = {
722 {
723 .start = AT91SAM9RL_BASE_RTT,
724 .end = AT91SAM9RL_BASE_RTT + SZ_16 - 1,
725 .flags = IORESOURCE_MEM,
726 }, {
727 .flags = IORESOURCE_MEM,
728 }, {
729 .flags = IORESOURCE_IRQ,
730 }
731};
732
733static struct platform_device at91sam9rl_rtt_device = {
734 .name = "at91_rtt",
735 .id = 0,
736 .resource = rtt_resources,
737};
738
739#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
740static void __init at91_add_device_rtt_rtc(void)
741{
742 at91sam9rl_rtt_device.name = "rtc-at91sam9";
743 /*
744 * The second resource is needed:
745 * GPBR will serve as the storage for RTC time offset
746 */
747 at91sam9rl_rtt_device.num_resources = 3;
748 rtt_resources[1].start = AT91SAM9RL_BASE_GPBR +
749 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
750 rtt_resources[1].end = rtt_resources[1].start + 3;
751 rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
752 rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
753}
754#else
755static void __init at91_add_device_rtt_rtc(void)
756{
757 /* Only one resource is needed: RTT not used as RTC */
758 at91sam9rl_rtt_device.num_resources = 1;
759}
760#endif
761
762static void __init at91_add_device_rtt(void)
763{
764 at91_add_device_rtt_rtc();
765 platform_device_register(&at91sam9rl_rtt_device);
766}
767
768
769/* --------------------------------------------------------------------
770 * Watchdog
771 * -------------------------------------------------------------------- */
772
773#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
774static struct resource wdt_resources[] = {
775 {
776 .start = AT91SAM9RL_BASE_WDT,
777 .end = AT91SAM9RL_BASE_WDT + SZ_16 - 1,
778 .flags = IORESOURCE_MEM,
779 }
780};
781
782static struct platform_device at91sam9rl_wdt_device = {
783 .name = "at91_wdt",
784 .id = -1,
785 .resource = wdt_resources,
786 .num_resources = ARRAY_SIZE(wdt_resources),
787};
788
789static void __init at91_add_device_watchdog(void)
790{
791 platform_device_register(&at91sam9rl_wdt_device);
792}
793#else
794static void __init at91_add_device_watchdog(void) {}
795#endif
796
797
798/* --------------------------------------------------------------------
799 * PWM
800 * --------------------------------------------------------------------*/
801
802#if IS_ENABLED(CONFIG_PWM_ATMEL)
803static struct resource pwm_resources[] = {
804 [0] = {
805 .start = AT91SAM9RL_BASE_PWMC,
806 .end = AT91SAM9RL_BASE_PWMC + SZ_16K - 1,
807 .flags = IORESOURCE_MEM,
808 },
809 [1] = {
810 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_PWMC,
811 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_PWMC,
812 .flags = IORESOURCE_IRQ,
813 },
814};
815
816static struct platform_device at91sam9rl_pwm0_device = {
817 .name = "at91sam9rl-pwm",
818 .id = -1,
819 .resource = pwm_resources,
820 .num_resources = ARRAY_SIZE(pwm_resources),
821};
822
823void __init at91_add_device_pwm(u32 mask)
824{
825 if (mask & (1 << AT91_PWM0))
826 at91_set_B_periph(AT91_PIN_PB8, 1); /* enable PWM0 */
827
828 if (mask & (1 << AT91_PWM1))
829 at91_set_B_periph(AT91_PIN_PB9, 1); /* enable PWM1 */
830
831 if (mask & (1 << AT91_PWM2))
832 at91_set_B_periph(AT91_PIN_PD5, 1); /* enable PWM2 */
833
834 if (mask & (1 << AT91_PWM3))
835 at91_set_B_periph(AT91_PIN_PD8, 1); /* enable PWM3 */
836
837 platform_device_register(&at91sam9rl_pwm0_device);
838}
839#else
840void __init at91_add_device_pwm(u32 mask) {}
841#endif
842
843
844/* --------------------------------------------------------------------
845 * SSC -- Synchronous Serial Controller
846 * -------------------------------------------------------------------- */
847
848#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
849static u64 ssc0_dmamask = DMA_BIT_MASK(32);
850
851static struct resource ssc0_resources[] = {
852 [0] = {
853 .start = AT91SAM9RL_BASE_SSC0,
854 .end = AT91SAM9RL_BASE_SSC0 + SZ_16K - 1,
855 .flags = IORESOURCE_MEM,
856 },
857 [1] = {
858 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC0,
859 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC0,
860 .flags = IORESOURCE_IRQ,
861 },
862};
863
864static struct platform_device at91sam9rl_ssc0_device = {
865 .name = "at91rm9200_ssc",
866 .id = 0,
867 .dev = {
868 .dma_mask = &ssc0_dmamask,
869 .coherent_dma_mask = DMA_BIT_MASK(32),
870 },
871 .resource = ssc0_resources,
872 .num_resources = ARRAY_SIZE(ssc0_resources),
873};
874
875static inline void configure_ssc0_pins(unsigned pins)
876{
877 if (pins & ATMEL_SSC_TF)
878 at91_set_A_periph(AT91_PIN_PC0, 1);
879 if (pins & ATMEL_SSC_TK)
880 at91_set_A_periph(AT91_PIN_PC1, 1);
881 if (pins & ATMEL_SSC_TD)
882 at91_set_A_periph(AT91_PIN_PA15, 1);
883 if (pins & ATMEL_SSC_RD)
884 at91_set_A_periph(AT91_PIN_PA16, 1);
885 if (pins & ATMEL_SSC_RK)
886 at91_set_B_periph(AT91_PIN_PA10, 1);
887 if (pins & ATMEL_SSC_RF)
888 at91_set_B_periph(AT91_PIN_PA22, 1);
889}
890
891static u64 ssc1_dmamask = DMA_BIT_MASK(32);
892
893static struct resource ssc1_resources[] = {
894 [0] = {
895 .start = AT91SAM9RL_BASE_SSC1,
896 .end = AT91SAM9RL_BASE_SSC1 + SZ_16K - 1,
897 .flags = IORESOURCE_MEM,
898 },
899 [1] = {
900 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC1,
901 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC1,
902 .flags = IORESOURCE_IRQ,
903 },
904};
905
906static struct platform_device at91sam9rl_ssc1_device = {
907 .name = "at91rm9200_ssc",
908 .id = 1,
909 .dev = {
910 .dma_mask = &ssc1_dmamask,
911 .coherent_dma_mask = DMA_BIT_MASK(32),
912 },
913 .resource = ssc1_resources,
914 .num_resources = ARRAY_SIZE(ssc1_resources),
915};
916
917static inline void configure_ssc1_pins(unsigned pins)
918{
919 if (pins & ATMEL_SSC_TF)
920 at91_set_B_periph(AT91_PIN_PA29, 1);
921 if (pins & ATMEL_SSC_TK)
922 at91_set_B_periph(AT91_PIN_PA30, 1);
923 if (pins & ATMEL_SSC_TD)
924 at91_set_B_periph(AT91_PIN_PA13, 1);
925 if (pins & ATMEL_SSC_RD)
926 at91_set_B_periph(AT91_PIN_PA14, 1);
927 if (pins & ATMEL_SSC_RK)
928 at91_set_B_periph(AT91_PIN_PA9, 1);
929 if (pins & ATMEL_SSC_RF)
930 at91_set_B_periph(AT91_PIN_PA8, 1);
931}
932
933/*
934 * SSC controllers are accessed through library code, instead of any
935 * kind of all-singing/all-dancing driver. For example one could be
936 * used by a particular I2S audio codec's driver, while another one
937 * on the same system might be used by a custom data capture driver.
938 */
939void __init at91_add_device_ssc(unsigned id, unsigned pins)
940{
941 struct platform_device *pdev;
942
943 /*
944 * NOTE: caller is responsible for passing information matching
945 * "pins" to whatever will be using each particular controller.
946 */
947 switch (id) {
948 case AT91SAM9RL_ID_SSC0:
949 pdev = &at91sam9rl_ssc0_device;
950 configure_ssc0_pins(pins);
951 break;
952 case AT91SAM9RL_ID_SSC1:
953 pdev = &at91sam9rl_ssc1_device;
954 configure_ssc1_pins(pins);
955 break;
956 default:
957 return;
958 }
959
960 platform_device_register(pdev);
961}
962
963#else
964void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
965#endif
966
967
968/* --------------------------------------------------------------------
969 * UART
970 * -------------------------------------------------------------------- */
971
972#if defined(CONFIG_SERIAL_ATMEL)
973static struct resource dbgu_resources[] = {
974 [0] = {
975 .start = AT91SAM9RL_BASE_DBGU,
976 .end = AT91SAM9RL_BASE_DBGU + SZ_512 - 1,
977 .flags = IORESOURCE_MEM,
978 },
979 [1] = {
980 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
981 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
982 .flags = IORESOURCE_IRQ,
983 },
984};
985
986static struct atmel_uart_data dbgu_data = {
987 .use_dma_tx = 0,
988 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
989};
990
991static u64 dbgu_dmamask = DMA_BIT_MASK(32);
992
993static struct platform_device at91sam9rl_dbgu_device = {
994 .name = "atmel_usart",
995 .id = 0,
996 .dev = {
997 .dma_mask = &dbgu_dmamask,
998 .coherent_dma_mask = DMA_BIT_MASK(32),
999 .platform_data = &dbgu_data,
1000 },
1001 .resource = dbgu_resources,
1002 .num_resources = ARRAY_SIZE(dbgu_resources),
1003};
1004
1005static inline void configure_dbgu_pins(void)
1006{
1007 at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */
1008 at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */
1009}
1010
1011static struct resource uart0_resources[] = {
1012 [0] = {
1013 .start = AT91SAM9RL_BASE_US0,
1014 .end = AT91SAM9RL_BASE_US0 + SZ_16K - 1,
1015 .flags = IORESOURCE_MEM,
1016 },
1017 [1] = {
1018 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_US0,
1019 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_US0,
1020 .flags = IORESOURCE_IRQ,
1021 },
1022};
1023
1024static struct atmel_uart_data uart0_data = {
1025 .use_dma_tx = 1,
1026 .use_dma_rx = 1,
1027};
1028
1029static u64 uart0_dmamask = DMA_BIT_MASK(32);
1030
1031static struct platform_device at91sam9rl_uart0_device = {
1032 .name = "atmel_usart",
1033 .id = 1,
1034 .dev = {
1035 .dma_mask = &uart0_dmamask,
1036 .coherent_dma_mask = DMA_BIT_MASK(32),
1037 .platform_data = &uart0_data,
1038 },
1039 .resource = uart0_resources,
1040 .num_resources = ARRAY_SIZE(uart0_resources),
1041};
1042
1043static inline void configure_usart0_pins(unsigned pins)
1044{
1045 at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */
1046 at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
1047
1048 if (pins & ATMEL_UART_RTS)
1049 at91_set_A_periph(AT91_PIN_PA9, 0); /* RTS0 */
1050 if (pins & ATMEL_UART_CTS)
1051 at91_set_A_periph(AT91_PIN_PA10, 0); /* CTS0 */
1052 if (pins & ATMEL_UART_DSR)
1053 at91_set_A_periph(AT91_PIN_PD14, 0); /* DSR0 */
1054 if (pins & ATMEL_UART_DTR)
1055 at91_set_A_periph(AT91_PIN_PD15, 0); /* DTR0 */
1056 if (pins & ATMEL_UART_DCD)
1057 at91_set_A_periph(AT91_PIN_PD16, 0); /* DCD0 */
1058 if (pins & ATMEL_UART_RI)
1059 at91_set_A_periph(AT91_PIN_PD17, 0); /* RI0 */
1060}
1061
1062static struct resource uart1_resources[] = {
1063 [0] = {
1064 .start = AT91SAM9RL_BASE_US1,
1065 .end = AT91SAM9RL_BASE_US1 + SZ_16K - 1,
1066 .flags = IORESOURCE_MEM,
1067 },
1068 [1] = {
1069 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_US1,
1070 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_US1,
1071 .flags = IORESOURCE_IRQ,
1072 },
1073};
1074
1075static struct atmel_uart_data uart1_data = {
1076 .use_dma_tx = 1,
1077 .use_dma_rx = 1,
1078};
1079
1080static u64 uart1_dmamask = DMA_BIT_MASK(32);
1081
1082static struct platform_device at91sam9rl_uart1_device = {
1083 .name = "atmel_usart",
1084 .id = 2,
1085 .dev = {
1086 .dma_mask = &uart1_dmamask,
1087 .coherent_dma_mask = DMA_BIT_MASK(32),
1088 .platform_data = &uart1_data,
1089 },
1090 .resource = uart1_resources,
1091 .num_resources = ARRAY_SIZE(uart1_resources),
1092};
1093
1094static inline void configure_usart1_pins(unsigned pins)
1095{
1096 at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */
1097 at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */
1098
1099 if (pins & ATMEL_UART_RTS)
1100 at91_set_B_periph(AT91_PIN_PA18, 0); /* RTS1 */
1101 if (pins & ATMEL_UART_CTS)
1102 at91_set_B_periph(AT91_PIN_PA19, 0); /* CTS1 */
1103}
1104
1105static struct resource uart2_resources[] = {
1106 [0] = {
1107 .start = AT91SAM9RL_BASE_US2,
1108 .end = AT91SAM9RL_BASE_US2 + SZ_16K - 1,
1109 .flags = IORESOURCE_MEM,
1110 },
1111 [1] = {
1112 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_US2,
1113 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_US2,
1114 .flags = IORESOURCE_IRQ,
1115 },
1116};
1117
1118static struct atmel_uart_data uart2_data = {
1119 .use_dma_tx = 1,
1120 .use_dma_rx = 1,
1121};
1122
1123static u64 uart2_dmamask = DMA_BIT_MASK(32);
1124
1125static struct platform_device at91sam9rl_uart2_device = {
1126 .name = "atmel_usart",
1127 .id = 3,
1128 .dev = {
1129 .dma_mask = &uart2_dmamask,
1130 .coherent_dma_mask = DMA_BIT_MASK(32),
1131 .platform_data = &uart2_data,
1132 },
1133 .resource = uart2_resources,
1134 .num_resources = ARRAY_SIZE(uart2_resources),
1135};
1136
1137static inline void configure_usart2_pins(unsigned pins)
1138{
1139 at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */
1140 at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */
1141
1142 if (pins & ATMEL_UART_RTS)
1143 at91_set_A_periph(AT91_PIN_PA29, 0); /* RTS2 */
1144 if (pins & ATMEL_UART_CTS)
1145 at91_set_A_periph(AT91_PIN_PA30, 0); /* CTS2 */
1146}
1147
1148static struct resource uart3_resources[] = {
1149 [0] = {
1150 .start = AT91SAM9RL_BASE_US3,
1151 .end = AT91SAM9RL_BASE_US3 + SZ_16K - 1,
1152 .flags = IORESOURCE_MEM,
1153 },
1154 [1] = {
1155 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_US3,
1156 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_US3,
1157 .flags = IORESOURCE_IRQ,
1158 },
1159};
1160
1161static struct atmel_uart_data uart3_data = {
1162 .use_dma_tx = 1,
1163 .use_dma_rx = 1,
1164};
1165
1166static u64 uart3_dmamask = DMA_BIT_MASK(32);
1167
1168static struct platform_device at91sam9rl_uart3_device = {
1169 .name = "atmel_usart",
1170 .id = 4,
1171 .dev = {
1172 .dma_mask = &uart3_dmamask,
1173 .coherent_dma_mask = DMA_BIT_MASK(32),
1174 .platform_data = &uart3_data,
1175 },
1176 .resource = uart3_resources,
1177 .num_resources = ARRAY_SIZE(uart3_resources),
1178};
1179
1180static inline void configure_usart3_pins(unsigned pins)
1181{
1182 at91_set_A_periph(AT91_PIN_PB0, 1); /* TXD3 */
1183 at91_set_A_periph(AT91_PIN_PB1, 0); /* RXD3 */
1184
1185 if (pins & ATMEL_UART_RTS)
1186 at91_set_B_periph(AT91_PIN_PD4, 0); /* RTS3 */
1187 if (pins & ATMEL_UART_CTS)
1188 at91_set_B_periph(AT91_PIN_PD3, 0); /* CTS3 */
1189}
1190
1191static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1192
1193void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1194{
1195 struct platform_device *pdev;
1196 struct atmel_uart_data *pdata;
1197
1198 switch (id) {
1199 case 0: /* DBGU */
1200 pdev = &at91sam9rl_dbgu_device;
1201 configure_dbgu_pins();
1202 break;
1203 case AT91SAM9RL_ID_US0:
1204 pdev = &at91sam9rl_uart0_device;
1205 configure_usart0_pins(pins);
1206 break;
1207 case AT91SAM9RL_ID_US1:
1208 pdev = &at91sam9rl_uart1_device;
1209 configure_usart1_pins(pins);
1210 break;
1211 case AT91SAM9RL_ID_US2:
1212 pdev = &at91sam9rl_uart2_device;
1213 configure_usart2_pins(pins);
1214 break;
1215 case AT91SAM9RL_ID_US3:
1216 pdev = &at91sam9rl_uart3_device;
1217 configure_usart3_pins(pins);
1218 break;
1219 default:
1220 return;
1221 }
1222 pdata = pdev->dev.platform_data;
1223 pdata->num = portnr; /* update to mapped ID */
1224
1225 if (portnr < ATMEL_MAX_UART)
1226 at91_uarts[portnr] = pdev;
1227}
1228
1229void __init at91_add_device_serial(void)
1230{
1231 int i;
1232
1233 for (i = 0; i < ATMEL_MAX_UART; i++) {
1234 if (at91_uarts[i])
1235 platform_device_register(at91_uarts[i]);
1236 }
1237}
1238#else
1239void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1240void __init at91_add_device_serial(void) {}
1241#endif
1242
1243
1244/* -------------------------------------------------------------------- */
1245
1246/*
1247 * These devices are always present and don't need any board-specific
1248 * setup.
1249 */
1250static int __init at91_add_standard_devices(void)
1251{
1252 at91_add_device_hdmac();
1253 at91_add_device_rtc();
1254 at91_add_device_rtt();
1255 at91_add_device_watchdog();
1256 at91_add_device_tc();
1257 return 0;
1258}
1259
1260arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 028268ff3722..f0d5a69a7237 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -6,317 +6,11 @@
6 * Licensed under GPLv2 or later. 6 * Licensed under GPLv2 or later.
7 */ 7 */
8 8
9#include <linux/module.h> 9#include <asm/system_misc.h>
10#include <linux/dma-mapping.h> 10#include <mach/hardware.h>
11#include <linux/clk/at91_pmc.h>
12 11
13#include <asm/irq.h>
14#include <asm/mach/arch.h>
15#include <asm/mach/map.h>
16#include <mach/at91sam9x5.h>
17#include <mach/cpu.h>
18
19#include "board.h"
20#include "soc.h" 12#include "soc.h"
21#include "generic.h" 13#include "generic.h"
22#include "sam9_smc.h"
23
24#if defined(CONFIG_OLD_CLK_AT91)
25#include "clock.h"
26/* --------------------------------------------------------------------
27 * Clocks
28 * -------------------------------------------------------------------- */
29
30/*
31 * The peripheral clocks.
32 */
33static struct clk pioAB_clk = {
34 .name = "pioAB_clk",
35 .pmc_mask = 1 << AT91SAM9X5_ID_PIOAB,
36 .type = CLK_TYPE_PERIPHERAL,
37};
38static struct clk pioCD_clk = {
39 .name = "pioCD_clk",
40 .pmc_mask = 1 << AT91SAM9X5_ID_PIOCD,
41 .type = CLK_TYPE_PERIPHERAL,
42};
43static struct clk smd_clk = {
44 .name = "smd_clk",
45 .pmc_mask = 1 << AT91SAM9X5_ID_SMD,
46 .type = CLK_TYPE_PERIPHERAL,
47};
48static struct clk usart0_clk = {
49 .name = "usart0_clk",
50 .pmc_mask = 1 << AT91SAM9X5_ID_USART0,
51 .type = CLK_TYPE_PERIPHERAL,
52};
53static struct clk usart1_clk = {
54 .name = "usart1_clk",
55 .pmc_mask = 1 << AT91SAM9X5_ID_USART1,
56 .type = CLK_TYPE_PERIPHERAL,
57};
58static struct clk usart2_clk = {
59 .name = "usart2_clk",
60 .pmc_mask = 1 << AT91SAM9X5_ID_USART2,
61 .type = CLK_TYPE_PERIPHERAL,
62};
63/* USART3 clock - Only for sam9g25/sam9x25 */
64static struct clk usart3_clk = {
65 .name = "usart3_clk",
66 .pmc_mask = 1 << AT91SAM9X5_ID_USART3,
67 .type = CLK_TYPE_PERIPHERAL,
68};
69static struct clk twi0_clk = {
70 .name = "twi0_clk",
71 .pmc_mask = 1 << AT91SAM9X5_ID_TWI0,
72 .type = CLK_TYPE_PERIPHERAL,
73};
74static struct clk twi1_clk = {
75 .name = "twi1_clk",
76 .pmc_mask = 1 << AT91SAM9X5_ID_TWI1,
77 .type = CLK_TYPE_PERIPHERAL,
78};
79static struct clk twi2_clk = {
80 .name = "twi2_clk",
81 .pmc_mask = 1 << AT91SAM9X5_ID_TWI2,
82 .type = CLK_TYPE_PERIPHERAL,
83};
84static struct clk mmc0_clk = {
85 .name = "mci0_clk",
86 .pmc_mask = 1 << AT91SAM9X5_ID_MCI0,
87 .type = CLK_TYPE_PERIPHERAL,
88};
89static struct clk spi0_clk = {
90 .name = "spi0_clk",
91 .pmc_mask = 1 << AT91SAM9X5_ID_SPI0,
92 .type = CLK_TYPE_PERIPHERAL,
93};
94static struct clk spi1_clk = {
95 .name = "spi1_clk",
96 .pmc_mask = 1 << AT91SAM9X5_ID_SPI1,
97 .type = CLK_TYPE_PERIPHERAL,
98};
99static struct clk uart0_clk = {
100 .name = "uart0_clk",
101 .pmc_mask = 1 << AT91SAM9X5_ID_UART0,
102 .type = CLK_TYPE_PERIPHERAL,
103};
104static struct clk uart1_clk = {
105 .name = "uart1_clk",
106 .pmc_mask = 1 << AT91SAM9X5_ID_UART1,
107 .type = CLK_TYPE_PERIPHERAL,
108};
109static struct clk tcb0_clk = {
110 .name = "tcb0_clk",
111 .pmc_mask = 1 << AT91SAM9X5_ID_TCB,
112 .type = CLK_TYPE_PERIPHERAL,
113};
114static struct clk pwm_clk = {
115 .name = "pwm_clk",
116 .pmc_mask = 1 << AT91SAM9X5_ID_PWM,
117 .type = CLK_TYPE_PERIPHERAL,
118};
119static struct clk adc_clk = {
120 .name = "adc_clk",
121 .pmc_mask = 1 << AT91SAM9X5_ID_ADC,
122 .type = CLK_TYPE_PERIPHERAL,
123};
124static struct clk adc_op_clk = {
125 .name = "adc_op_clk",
126 .type = CLK_TYPE_PERIPHERAL,
127 .rate_hz = 5000000,
128};
129static struct clk dma0_clk = {
130 .name = "dma0_clk",
131 .pmc_mask = 1 << AT91SAM9X5_ID_DMA0,
132 .type = CLK_TYPE_PERIPHERAL,
133};
134static struct clk dma1_clk = {
135 .name = "dma1_clk",
136 .pmc_mask = 1 << AT91SAM9X5_ID_DMA1,
137 .type = CLK_TYPE_PERIPHERAL,
138};
139static struct clk uhphs_clk = {
140 .name = "uhphs",
141 .pmc_mask = 1 << AT91SAM9X5_ID_UHPHS,
142 .type = CLK_TYPE_PERIPHERAL,
143};
144static struct clk udphs_clk = {
145 .name = "udphs_clk",
146 .pmc_mask = 1 << AT91SAM9X5_ID_UDPHS,
147 .type = CLK_TYPE_PERIPHERAL,
148};
149/* emac0 clock - Only for sam9g25/sam9x25/sam9g35/sam9x35 */
150static struct clk macb0_clk = {
151 .name = "pclk",
152 .pmc_mask = 1 << AT91SAM9X5_ID_EMAC0,
153 .type = CLK_TYPE_PERIPHERAL,
154};
155/* lcd clock - Only for sam9g15/sam9g35/sam9x35 */
156static struct clk lcdc_clk = {
157 .name = "lcdc_clk",
158 .pmc_mask = 1 << AT91SAM9X5_ID_LCDC,
159 .type = CLK_TYPE_PERIPHERAL,
160};
161/* isi clock - Only for sam9g25 */
162static struct clk isi_clk = {
163 .name = "isi_clk",
164 .pmc_mask = 1 << AT91SAM9X5_ID_ISI,
165 .type = CLK_TYPE_PERIPHERAL,
166};
167static struct clk mmc1_clk = {
168 .name = "mci1_clk",
169 .pmc_mask = 1 << AT91SAM9X5_ID_MCI1,
170 .type = CLK_TYPE_PERIPHERAL,
171};
172/* emac1 clock - Only for sam9x25 */
173static struct clk macb1_clk = {
174 .name = "pclk",
175 .pmc_mask = 1 << AT91SAM9X5_ID_EMAC1,
176 .type = CLK_TYPE_PERIPHERAL,
177};
178static struct clk ssc_clk = {
179 .name = "ssc_clk",
180 .pmc_mask = 1 << AT91SAM9X5_ID_SSC,
181 .type = CLK_TYPE_PERIPHERAL,
182};
183/* can0 clock - Only for sam9x35 */
184static struct clk can0_clk = {
185 .name = "can0_clk",
186 .pmc_mask = 1 << AT91SAM9X5_ID_CAN0,
187 .type = CLK_TYPE_PERIPHERAL,
188};
189/* can1 clock - Only for sam9x35 */
190static struct clk can1_clk = {
191 .name = "can1_clk",
192 .pmc_mask = 1 << AT91SAM9X5_ID_CAN1,
193 .type = CLK_TYPE_PERIPHERAL,
194};
195
196static struct clk *periph_clocks[] __initdata = {
197 &pioAB_clk,
198 &pioCD_clk,
199 &smd_clk,
200 &usart0_clk,
201 &usart1_clk,
202 &usart2_clk,
203 &twi0_clk,
204 &twi1_clk,
205 &twi2_clk,
206 &mmc0_clk,
207 &spi0_clk,
208 &spi1_clk,
209 &uart0_clk,
210 &uart1_clk,
211 &tcb0_clk,
212 &pwm_clk,
213 &adc_clk,
214 &adc_op_clk,
215 &dma0_clk,
216 &dma1_clk,
217 &uhphs_clk,
218 &udphs_clk,
219 &mmc1_clk,
220 &ssc_clk,
221 // irq0
222};
223
224static struct clk_lookup periph_clocks_lookups[] = {
225 /* lookup table for DT entries */
226 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
227 CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
228 CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
229 CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
230 CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
231 CLKDEV_CON_DEV_ID("usart", "f8040000.serial", &uart0_clk),
232 CLKDEV_CON_DEV_ID("usart", "f8044000.serial", &uart1_clk),
233 CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk),
234 CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
235 CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc0_clk),
236 CLKDEV_CON_DEV_ID("mci_clk", "f000c000.mmc", &mmc1_clk),
237 CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
238 CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
239 CLKDEV_CON_DEV_ID("pclk", "f0010000.ssc", &ssc_clk),
240 CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
241 CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
242 CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk),
243 CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
244 CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
245 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
246 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
247 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
248 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
249 /* additional fake clock for macb_hclk */
250 CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk),
251 CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk),
252 CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
253 CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
254 CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
255 CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
256 CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
257 CLKDEV_CON_DEV_ID(NULL, "f8034000.pwm", &pwm_clk),
258};
259
260/*
261 * The two programmable clocks.
262 * You must configure pin multiplexing to bring these signals out.
263 */
264static struct clk pck0 = {
265 .name = "pck0",
266 .pmc_mask = AT91_PMC_PCK0,
267 .type = CLK_TYPE_PROGRAMMABLE,
268 .id = 0,
269};
270static struct clk pck1 = {
271 .name = "pck1",
272 .pmc_mask = AT91_PMC_PCK1,
273 .type = CLK_TYPE_PROGRAMMABLE,
274 .id = 1,
275};
276
277static void __init at91sam9x5_register_clocks(void)
278{
279 int i;
280
281 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
282 clk_register(periph_clocks[i]);
283
284 clkdev_add_table(periph_clocks_lookups,
285 ARRAY_SIZE(periph_clocks_lookups));
286
287 if (cpu_is_at91sam9g25()
288 || cpu_is_at91sam9x25())
289 clk_register(&usart3_clk);
290
291 if (cpu_is_at91sam9g25()
292 || cpu_is_at91sam9x25()
293 || cpu_is_at91sam9g35()
294 || cpu_is_at91sam9x35())
295 clk_register(&macb0_clk);
296
297 if (cpu_is_at91sam9g15()
298 || cpu_is_at91sam9g35()
299 || cpu_is_at91sam9x35())
300 clk_register(&lcdc_clk);
301
302 if (cpu_is_at91sam9g25())
303 clk_register(&isi_clk);
304
305 if (cpu_is_at91sam9x25())
306 clk_register(&macb1_clk);
307
308 if (cpu_is_at91sam9x25()
309 || cpu_is_at91sam9x35()) {
310 clk_register(&can0_clk);
311 clk_register(&can1_clk);
312 }
313
314 clk_register(&pck0);
315 clk_register(&pck1);
316}
317#else
318#define at91sam9x5_register_clocks NULL
319#endif
320 14
321/* -------------------------------------------------------------------- 15/* --------------------------------------------------------------------
322 * AT91SAM9x5 processor initialization 16 * AT91SAM9x5 processor initialization
@@ -338,6 +32,5 @@ static void __init at91sam9x5_initialize(void)
338 32
339AT91_SOC_START(at91sam9x5) 33AT91_SOC_START(at91sam9x5)
340 .map_io = at91sam9x5_map_io, 34 .map_io = at91sam9x5_map_io,
341 .register_clocks = at91sam9x5_register_clocks,
342 .init = at91sam9x5_initialize, 35 .init = at91sam9x5_initialize,
343AT91_SOC_END 36AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
deleted file mode 100644
index 7523f1cdfe1d..000000000000
--- a/arch/arm/mach-at91/at91x40.c
+++ /dev/null
@@ -1,93 +0,0 @@
1/*
2 * arch/arm/mach-at91/at91x40.c
3 *
4 * (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com>
5 * Copyright (C) 2005 SAN People
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17#include <asm/proc-fns.h>
18#include <asm/system_misc.h>
19#include <asm/mach/arch.h>
20#include <mach/at91x40.h>
21#include <mach/at91_st.h>
22#include <mach/hardware.h>
23
24#include "at91_aic.h"
25#include "generic.h"
26
27/*
28 * Export the clock functions for the AT91X40. Some external code common
29 * to all AT91 family parts relys on this, like the gpio and serial support.
30 */
31int clk_enable(struct clk *clk)
32{
33 return 0;
34}
35
36void clk_disable(struct clk *clk)
37{
38}
39
40unsigned long clk_get_rate(struct clk *clk)
41{
42 return AT91X40_MASTER_CLOCK;
43}
44
45static void at91x40_idle(void)
46{
47 /*
48 * Disable the processor clock. The processor will be automatically
49 * re-enabled by an interrupt or by a reset.
50 */
51 __raw_writel(AT91_PS_CR_CPU, AT91_IO_P2V(AT91_PS_CR));
52 cpu_do_idle();
53}
54
55void __init at91x40_initialize(unsigned long main_clock)
56{
57 arm_pm_idle = at91x40_idle;
58}
59
60/*
61 * The default interrupt priority levels (0 = lowest, 7 = highest).
62 */
63static unsigned int at91x40_default_irq_priority[NR_AIC_IRQS] __initdata = {
64 7, /* Advanced Interrupt Controller (FIQ) */
65 0, /* System Peripherals */
66 0, /* USART 0 */
67 0, /* USART 1 */
68 2, /* Timer Counter 0 */
69 2, /* Timer Counter 1 */
70 2, /* Timer Counter 2 */
71 0, /* Watchdog timer */
72 0, /* Parallel IO Controller A */
73 0, /* Reserved */
74 0, /* Reserved */
75 0, /* Reserved */
76 0, /* Reserved */
77 0, /* Reserved */
78 0, /* Reserved */
79 0, /* Reserved */
80 0, /* External IRQ0 */
81 0, /* External IRQ1 */
82 0, /* External IRQ2 */
83};
84
85void __init at91x40_init_interrupts(unsigned int priority[NR_AIC_IRQS])
86{
87 u32 extern_irq = (1 << AT91X40_ID_IRQ0) | (1 << AT91X40_ID_IRQ1)
88 | (1 << AT91X40_ID_IRQ2);
89 if (!priority)
90 priority = at91x40_default_irq_priority;
91
92 at91_aic_init(priority, extern_irq);
93}
diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c
deleted file mode 100644
index 07d0bf2ac2da..000000000000
--- a/arch/arm/mach-at91/at91x40_time.c
+++ /dev/null
@@ -1,85 +0,0 @@
1/*
2 * arch/arm/mach-at91/at91x40_time.c
3 *
4 * (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/time.h>
26#include <linux/io.h>
27#include <mach/hardware.h>
28#include <mach/at91x40.h>
29#include <asm/mach/time.h>
30
31#include "at91_tc.h"
32
33#define at91_tc_read(field) \
34 __raw_readl(AT91_IO_P2V(AT91_TC) + field)
35
36#define at91_tc_write(field, value) \
37 __raw_writel(value, AT91_IO_P2V(AT91_TC) + field)
38
39/*
40 * 3 counter/timer units present.
41 */
42#define AT91_TC_CLK0BASE 0
43#define AT91_TC_CLK1BASE 0x40
44#define AT91_TC_CLK2BASE 0x80
45
46static u32 at91x40_gettimeoffset(void)
47{
48 return (at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 /
49 (AT91X40_MASTER_CLOCK / 128)) * 1000;
50}
51
52static irqreturn_t at91x40_timer_interrupt(int irq, void *dev_id)
53{
54 at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_SR);
55 timer_tick();
56 return IRQ_HANDLED;
57}
58
59static struct irqaction at91x40_timer_irq = {
60 .name = "at91_tick",
61 .flags = IRQF_TIMER,
62 .handler = at91x40_timer_interrupt
63};
64
65void __init at91x40_timer_init(void)
66{
67 unsigned int v;
68
69 arch_gettimeoffset = at91x40_gettimeoffset;
70
71 at91_tc_write(AT91_TC_BCR, 0);
72 v = at91_tc_read(AT91_TC_BMR);
73 v = (v & ~AT91_TC_TC1XC1S) | AT91_TC_TC1XC1S_NONE;
74 at91_tc_write(AT91_TC_BMR, v);
75
76 at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS);
77 at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG));
78 at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff);
79 at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1);
80 at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4));
81
82 setup_irq(AT91X40_ID_TC1, &at91x40_timer_irq);
83
84 at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN));
85}
diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
deleted file mode 100644
index 3f6dbcc34022..000000000000
--- a/arch/arm/mach-at91/board-1arm.c
+++ /dev/null
@@ -1,99 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-1arm.c
3 *
4 * Copyright (C) 2005 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/types.h>
22#include <linux/gpio.h>
23#include <linux/init.h>
24#include <linux/mm.h>
25#include <linux/module.h>
26#include <linux/platform_device.h>
27
28#include <mach/hardware.h>
29#include <asm/setup.h>
30#include <asm/mach-types.h>
31#include <asm/irq.h>
32
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35#include <asm/mach/irq.h>
36
37#include <mach/cpu.h>
38
39#include "at91_aic.h"
40#include "board.h"
41#include "generic.h"
42#include "gpio.h"
43
44static void __init onearm_init_early(void)
45{
46 /* Set cpu type: PQFP */
47 at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
48
49 /* Initialize processor: 18.432 MHz crystal */
50 at91_initialize(18432000);
51}
52
53static struct macb_platform_data __initdata onearm_eth_data = {
54 .phy_irq_pin = AT91_PIN_PC4,
55 .is_rmii = 1,
56};
57
58static struct at91_usbh_data __initdata onearm_usbh_data = {
59 .ports = 1,
60 .vbus_pin = {-EINVAL, -EINVAL},
61 .overcurrent_pin= {-EINVAL, -EINVAL},
62};
63
64static struct at91_udc_data __initdata onearm_udc_data = {
65 .vbus_pin = AT91_PIN_PC2,
66 .pullup_pin = AT91_PIN_PC3,
67};
68
69static void __init onearm_board_init(void)
70{
71 /* Serial */
72 /* DBGU on ttyS0. (Rx & Tx only) */
73 at91_register_uart(0, 0, 0);
74
75 /* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */
76 at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
77
78 /* USART1 on ttyS2 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
79 at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS
80 | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
81 | ATMEL_UART_RI);
82 at91_add_device_serial();
83 /* Ethernet */
84 at91_add_device_eth(&onearm_eth_data);
85 /* USB Host */
86 at91_add_device_usbh(&onearm_usbh_data);
87 /* USB Device */
88 at91_add_device_udc(&onearm_udc_data);
89}
90
91MACHINE_START(ONEARM, "Ajeco 1ARM single board computer")
92 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
93 .init_time = at91rm9200_timer_init,
94 .map_io = at91_map_io,
95 .handle_irq = at91_aic_handle_irq,
96 .init_early = onearm_init_early,
97 .init_irq = at91_init_irq_default,
98 .init_machine = onearm_board_init,
99MACHINE_END
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
deleted file mode 100644
index e76e35ce81e7..000000000000
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ /dev/null
@@ -1,223 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-afeb-9260v1.c
3 *
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2006 Atmel
6 * Copyright (C) 2008 Sergey Lapin
7 *
8 * A custom board designed as open hardware; PCBs and various information
9 * is available at http://groups.google.com/group/arm9fpga-evolution-board/
10 * Subversion repository: svn://194.85.238.22/home/users/george/svn/arm9eb
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 */
26
27#include <linux/types.h>
28#include <linux/gpio.h>
29#include <linux/init.h>
30#include <linux/mm.h>
31#include <linux/module.h>
32#include <linux/platform_device.h>
33#include <linux/spi/spi.h>
34#include <linux/clk.h>
35#include <linux/dma-mapping.h>
36
37#include <mach/hardware.h>
38#include <asm/setup.h>
39#include <asm/mach-types.h>
40#include <asm/irq.h>
41
42#include <asm/mach/arch.h>
43#include <asm/mach/map.h>
44#include <asm/mach/irq.h>
45
46#include "at91_aic.h"
47#include "board.h"
48#include "generic.h"
49#include "gpio.h"
50
51
52static void __init afeb9260_init_early(void)
53{
54 /* Initialize processor: 18.432 MHz crystal */
55 at91_initialize(18432000);
56}
57
58/*
59 * USB Host port
60 */
61static struct at91_usbh_data __initdata afeb9260_usbh_data = {
62 .ports = 1,
63 .vbus_pin = {-EINVAL, -EINVAL},
64 .overcurrent_pin= {-EINVAL, -EINVAL},
65};
66
67/*
68 * USB Device port
69 */
70static struct at91_udc_data __initdata afeb9260_udc_data = {
71 .vbus_pin = AT91_PIN_PC5,
72 .pullup_pin = -EINVAL, /* pull-up driven by UDC */
73};
74
75
76
77/*
78 * SPI devices.
79 */
80static struct spi_board_info afeb9260_spi_devices[] = {
81 { /* DataFlash chip */
82 .modalias = "mtd_dataflash",
83 .chip_select = 1,
84 .max_speed_hz = 15 * 1000 * 1000,
85 .bus_num = 0,
86 },
87};
88
89
90/*
91 * MACB Ethernet device
92 */
93static struct macb_platform_data __initdata afeb9260_macb_data = {
94 .phy_irq_pin = AT91_PIN_PA9,
95 .is_rmii = 0,
96};
97
98
99/*
100 * NAND flash
101 */
102static struct mtd_partition __initdata afeb9260_nand_partition[] = {
103 {
104 .name = "bootloader",
105 .offset = 0,
106 .size = (640 * SZ_1K),
107 },
108 {
109 .name = "kernel",
110 .offset = MTDPART_OFS_NXTBLK,
111 .size = SZ_2M,
112 },
113 {
114 .name = "rootfs",
115 .offset = MTDPART_OFS_NXTBLK,
116 .size = MTDPART_SIZ_FULL,
117 },
118};
119
120static struct atmel_nand_data __initdata afeb9260_nand_data = {
121 .ale = 21,
122 .cle = 22,
123 .rdy_pin = AT91_PIN_PC13,
124 .enable_pin = AT91_PIN_PC14,
125 .bus_width_16 = 0,
126 .ecc_mode = NAND_ECC_SOFT,
127 .parts = afeb9260_nand_partition,
128 .num_parts = ARRAY_SIZE(afeb9260_nand_partition),
129 .det_pin = -EINVAL,
130};
131
132
133/*
134 * MCI (SD/MMC)
135 */
136static struct mci_platform_data __initdata afeb9260_mci0_data = {
137 .slot[1] = {
138 .bus_width = 4,
139 .detect_pin = AT91_PIN_PC9,
140 .wp_pin = AT91_PIN_PC4,
141 },
142};
143
144
145
146static struct i2c_board_info __initdata afeb9260_i2c_devices[] = {
147 {
148 I2C_BOARD_INFO("tlv320aic23", 0x1a),
149 }, {
150 I2C_BOARD_INFO("fm3130", 0x68),
151 }, {
152 I2C_BOARD_INFO("24c64", 0x50),
153 },
154};
155
156/*
157 * IDE (CF True IDE mode)
158 */
159static struct at91_cf_data afeb9260_cf_data = {
160 .chipselect = 4,
161 .irq_pin = AT91_PIN_PA6,
162 .det_pin = -EINVAL,
163 .vcc_pin = -EINVAL,
164 .rst_pin = AT91_PIN_PA7,
165 .flags = AT91_CF_TRUE_IDE,
166};
167
168static void __init afeb9260_board_init(void)
169{
170 at91_register_devices();
171
172 /* Serial */
173 /* DBGU on ttyS0. (Rx & Tx only) */
174 at91_register_uart(0, 0, 0);
175
176 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
177 at91_register_uart(AT91SAM9260_ID_US0, 1,
178 ATMEL_UART_CTS | ATMEL_UART_RTS
179 | ATMEL_UART_DTR | ATMEL_UART_DSR
180 | ATMEL_UART_DCD | ATMEL_UART_RI);
181
182 /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
183 at91_register_uart(AT91SAM9260_ID_US1, 2,
184 ATMEL_UART_CTS | ATMEL_UART_RTS);
185 at91_add_device_serial();
186 /* USB Host */
187 at91_add_device_usbh(&afeb9260_usbh_data);
188 /* USB Device */
189 at91_add_device_udc(&afeb9260_udc_data);
190 /* SPI */
191 at91_add_device_spi(afeb9260_spi_devices,
192 ARRAY_SIZE(afeb9260_spi_devices));
193 /* NAND */
194 at91_add_device_nand(&afeb9260_nand_data);
195 /* Ethernet */
196 at91_add_device_eth(&afeb9260_macb_data);
197
198 /* Standard function's pin assignments are not
199 * appropriate for us and generic code provide
200 * no API to configure these pins any other way */
201 at91_set_B_periph(AT91_PIN_PA10, 0); /* ETX2 */
202 at91_set_B_periph(AT91_PIN_PA11, 0); /* ETX3 */
203 /* MMC */
204 at91_add_device_mci(0, &afeb9260_mci0_data);
205 /* I2C */
206 at91_add_device_i2c(afeb9260_i2c_devices,
207 ARRAY_SIZE(afeb9260_i2c_devices));
208 /* Audio */
209 at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX);
210 /* IDE */
211 at91_add_device_cf(&afeb9260_cf_data);
212}
213
214MACHINE_START(AFEB9260, "Custom afeb9260 board")
215 /* Maintainer: Sergey Lapin <slapin@ossfans.org> */
216 .init_time = at91_init_time,
217 .map_io = at91_map_io,
218 .handle_irq = at91_aic_handle_irq,
219 .init_early = afeb9260_init_early,
220 .init_irq = at91_init_irq_default,
221 .init_machine = afeb9260_board_init,
222MACHINE_END
223
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
deleted file mode 100644
index ae827dd2d0d2..000000000000
--- a/arch/arm/mach-at91/board-cam60.c
+++ /dev/null
@@ -1,199 +0,0 @@
1/*
2 * KwikByte CAM60 (KB9260)
3 *
4 * based on board-sam9260ek.c
5 * Copyright (C) 2005 SAN People
6 * Copyright (C) 2006 Atmel
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/types.h>
24#include <linux/gpio.h>
25#include <linux/init.h>
26#include <linux/mm.h>
27#include <linux/module.h>
28#include <linux/platform_device.h>
29#include <linux/spi/spi.h>
30#include <linux/spi/flash.h>
31
32#include <mach/hardware.h>
33#include <asm/setup.h>
34#include <asm/mach-types.h>
35#include <asm/irq.h>
36
37#include <asm/mach/arch.h>
38#include <asm/mach/map.h>
39#include <asm/mach/irq.h>
40
41#include <mach/at91sam9_smc.h>
42
43#include "at91_aic.h"
44#include "board.h"
45#include "sam9_smc.h"
46#include "generic.h"
47#include "gpio.h"
48
49
50static void __init cam60_init_early(void)
51{
52 /* Initialize processor: 10 MHz crystal */
53 at91_initialize(10000000);
54}
55
56/*
57 * USB Host
58 */
59static struct at91_usbh_data __initdata cam60_usbh_data = {
60 .ports = 1,
61 .vbus_pin = {-EINVAL, -EINVAL},
62 .overcurrent_pin= {-EINVAL, -EINVAL},
63};
64
65
66/*
67 * SPI devices.
68 */
69#if defined(CONFIG_MTD_DATAFLASH)
70static struct mtd_partition cam60_spi_partitions[] = {
71 {
72 .name = "BOOT1",
73 .offset = 0,
74 .size = 4 * 1056,
75 },
76 {
77 .name = "BOOT2",
78 .offset = MTDPART_OFS_NXTBLK,
79 .size = 256 * 1056,
80 },
81 {
82 .name = "kernel",
83 .offset = MTDPART_OFS_NXTBLK,
84 .size = 2222 * 1056,
85 },
86 {
87 .name = "file system",
88 .offset = MTDPART_OFS_NXTBLK,
89 .size = MTDPART_SIZ_FULL,
90 },
91};
92
93static struct flash_platform_data cam60_spi_flash_platform_data = {
94 .name = "spi_flash",
95 .parts = cam60_spi_partitions,
96 .nr_parts = ARRAY_SIZE(cam60_spi_partitions)
97};
98#endif
99
100static struct spi_board_info cam60_spi_devices[] __initdata = {
101#if defined(CONFIG_MTD_DATAFLASH)
102 { /* DataFlash chip */
103 .modalias = "mtd_dataflash",
104 .chip_select = 0,
105 .max_speed_hz = 15 * 1000 * 1000,
106 .bus_num = 0,
107 .platform_data = &cam60_spi_flash_platform_data
108 },
109#endif
110};
111
112
113/*
114 * MACB Ethernet device
115 */
116static struct macb_platform_data cam60_macb_data __initdata = {
117 .phy_irq_pin = AT91_PIN_PB5,
118 .is_rmii = 0,
119};
120
121
122/*
123 * NAND Flash
124 */
125static struct mtd_partition __initdata cam60_nand_partition[] = {
126 {
127 .name = "nand_fs",
128 .offset = 0,
129 .size = MTDPART_SIZ_FULL,
130 },
131};
132
133static struct atmel_nand_data __initdata cam60_nand_data = {
134 .ale = 21,
135 .cle = 22,
136 .det_pin = -EINVAL,
137 .rdy_pin = AT91_PIN_PA9,
138 .enable_pin = AT91_PIN_PA7,
139 .ecc_mode = NAND_ECC_SOFT,
140 .parts = cam60_nand_partition,
141 .num_parts = ARRAY_SIZE(cam60_nand_partition),
142};
143
144static struct sam9_smc_config __initdata cam60_nand_smc_config = {
145 .ncs_read_setup = 0,
146 .nrd_setup = 1,
147 .ncs_write_setup = 0,
148 .nwe_setup = 1,
149
150 .ncs_read_pulse = 3,
151 .nrd_pulse = 3,
152 .ncs_write_pulse = 3,
153 .nwe_pulse = 3,
154
155 .read_cycle = 5,
156 .write_cycle = 5,
157
158 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
159 .tdf_cycles = 2,
160};
161
162static void __init cam60_add_device_nand(void)
163{
164 /* configure chip-select 3 (NAND) */
165 sam9_smc_configure(0, 3, &cam60_nand_smc_config);
166
167 at91_add_device_nand(&cam60_nand_data);
168}
169
170
171static void __init cam60_board_init(void)
172{
173 at91_register_devices();
174
175 /* Serial */
176 /* DBGU on ttyS0. (Rx & Tx only) */
177 at91_register_uart(0, 0, 0);
178 at91_add_device_serial();
179 /* SPI */
180 at91_add_device_spi(cam60_spi_devices, ARRAY_SIZE(cam60_spi_devices));
181 /* Ethernet */
182 at91_add_device_eth(&cam60_macb_data);
183 /* USB Host */
184 /* enable USB power supply circuit */
185 at91_set_gpio_output(AT91_PIN_PB18, 1);
186 at91_add_device_usbh(&cam60_usbh_data);
187 /* NAND */
188 cam60_add_device_nand();
189}
190
191MACHINE_START(CAM60, "KwikByte CAM60")
192 /* Maintainer: KwikByte */
193 .init_time = at91_init_time,
194 .map_io = at91_map_io,
195 .handle_irq = at91_aic_handle_irq,
196 .init_early = cam60_init_early,
197 .init_irq = at91_init_irq_default,
198 .init_machine = cam60_board_init,
199MACHINE_END
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
deleted file mode 100644
index 47313d3ee037..000000000000
--- a/arch/arm/mach-at91/board-carmeva.c
+++ /dev/null
@@ -1,167 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-carmeva.c
3 *
4 * Copyright (c) 2005 Peer Georgi
5 * Conitec Datasystems
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/types.h>
23#include <linux/gpio.h>
24#include <linux/init.h>
25#include <linux/mm.h>
26#include <linux/module.h>
27#include <linux/platform_device.h>
28
29#include <asm/setup.h>
30#include <asm/mach-types.h>
31#include <asm/irq.h>
32
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35#include <asm/mach/irq.h>
36
37#include <mach/hardware.h>
38
39#include "at91_aic.h"
40#include "board.h"
41#include "generic.h"
42#include "gpio.h"
43
44
45static void __init carmeva_init_early(void)
46{
47 /* Initialize processor: 20.000 MHz crystal */
48 at91_initialize(20000000);
49}
50
51static struct macb_platform_data __initdata carmeva_eth_data = {
52 .phy_irq_pin = AT91_PIN_PC4,
53 .is_rmii = 1,
54};
55
56static struct at91_usbh_data __initdata carmeva_usbh_data = {
57 .ports = 2,
58 .vbus_pin = {-EINVAL, -EINVAL},
59 .overcurrent_pin= {-EINVAL, -EINVAL},
60};
61
62static struct at91_udc_data __initdata carmeva_udc_data = {
63 .vbus_pin = AT91_PIN_PD12,
64 .pullup_pin = AT91_PIN_PD9,
65};
66
67/* FIXME: user dependent */
68// static struct at91_cf_data __initdata carmeva_cf_data = {
69// .det_pin = AT91_PIN_PB0,
70// .rst_pin = AT91_PIN_PC5,
71 // .irq_pin = -EINVAL,
72 // .vcc_pin = -EINVAL,
73// };
74
75static struct mci_platform_data __initdata carmeva_mci0_data = {
76 .slot[0] = {
77 .bus_width = 4,
78 .detect_pin = AT91_PIN_PB10,
79 .wp_pin = AT91_PIN_PC14,
80 },
81};
82
83static struct spi_board_info carmeva_spi_devices[] = {
84 { /* DataFlash chip */
85 .modalias = "mtd_dataflash",
86 .chip_select = 0,
87 .max_speed_hz = 10 * 1000 * 1000,
88 },
89 { /* User accessible spi - cs1 (250KHz) */
90 .modalias = "spi-cs1",
91 .chip_select = 1,
92 .max_speed_hz = 250 * 1000,
93 },
94 { /* User accessible spi - cs2 (1MHz) */
95 .modalias = "spi-cs2",
96 .chip_select = 2,
97 .max_speed_hz = 1 * 1000 * 1000,
98 },
99 { /* User accessible spi - cs3 (10MHz) */
100 .modalias = "spi-cs3",
101 .chip_select = 3,
102 .max_speed_hz = 10 * 1000 * 1000,
103 },
104};
105
106static struct gpio_led carmeva_leds[] = {
107 { /* "user led 1", LED9 */
108 .name = "led9",
109 .gpio = AT91_PIN_PA21,
110 .active_low = 1,
111 .default_trigger = "heartbeat",
112 },
113 { /* "user led 2", LED10 */
114 .name = "led10",
115 .gpio = AT91_PIN_PA25,
116 .active_low = 1,
117 },
118 { /* "user led 3", LED11 */
119 .name = "led11",
120 .gpio = AT91_PIN_PA26,
121 .active_low = 1,
122 },
123 { /* "user led 4", LED12 */
124 .name = "led12",
125 .gpio = AT91_PIN_PA18,
126 .active_low = 1,
127 }
128};
129
130static void __init carmeva_board_init(void)
131{
132 /* Serial */
133 /* DBGU on ttyS0. (Rx & Tx only) */
134 at91_register_uart(0, 0, 0);
135
136 /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
137 at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
138 | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
139 | ATMEL_UART_RI);
140 at91_add_device_serial();
141 /* Ethernet */
142 at91_add_device_eth(&carmeva_eth_data);
143 /* USB Host */
144 at91_add_device_usbh(&carmeva_usbh_data);
145 /* USB Device */
146 at91_add_device_udc(&carmeva_udc_data);
147 /* I2C */
148 at91_add_device_i2c(NULL, 0);
149 /* SPI */
150 at91_add_device_spi(carmeva_spi_devices, ARRAY_SIZE(carmeva_spi_devices));
151 /* Compact Flash */
152// at91_add_device_cf(&carmeva_cf_data);
153 /* MMC */
154 at91_add_device_mci(0, &carmeva_mci0_data);
155 /* LEDs */
156 at91_gpio_leds(carmeva_leds, ARRAY_SIZE(carmeva_leds));
157}
158
159MACHINE_START(CARMEVA, "Carmeva")
160 /* Maintainer: Conitec Datasystems */
161 .init_time = at91rm9200_timer_init,
162 .map_io = at91_map_io,
163 .handle_irq = at91_aic_handle_irq,
164 .init_early = carmeva_init_early,
165 .init_irq = at91_init_irq_default,
166 .init_machine = carmeva_board_init,
167MACHINE_END
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
deleted file mode 100644
index 731c8318f4f5..000000000000
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ /dev/null
@@ -1,386 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-cpu9krea.c
3 *
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2006 Atmel
6 * Copyright (C) 2009 Eric Benard - eric@eukrea.com
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/types.h>
24#include <linux/gpio.h>
25#include <linux/init.h>
26#include <linux/mm.h>
27#include <linux/module.h>
28#include <linux/platform_device.h>
29#include <linux/clk.h>
30#include <linux/gpio_keys.h>
31#include <linux/input.h>
32#include <linux/mtd/physmap.h>
33
34#include <asm/setup.h>
35#include <asm/mach-types.h>
36#include <asm/irq.h>
37
38#include <asm/mach/arch.h>
39#include <asm/mach/map.h>
40#include <asm/mach/irq.h>
41
42#include <mach/hardware.h>
43#include <mach/at91sam9_smc.h>
44#include <mach/at91sam9260_matrix.h>
45#include <mach/at91_matrix.h>
46
47#include "at91_aic.h"
48#include "board.h"
49#include "sam9_smc.h"
50#include "generic.h"
51#include "gpio.h"
52
53static void __init cpu9krea_init_early(void)
54{
55 /* Initialize processor: 18.432 MHz crystal */
56 at91_initialize(18432000);
57}
58
59/*
60 * USB Host port
61 */
62static struct at91_usbh_data __initdata cpu9krea_usbh_data = {
63 .ports = 2,
64 .vbus_pin = {-EINVAL, -EINVAL},
65 .overcurrent_pin= {-EINVAL, -EINVAL},
66};
67
68/*
69 * USB Device port
70 */
71static struct at91_udc_data __initdata cpu9krea_udc_data = {
72 .vbus_pin = AT91_PIN_PC8,
73 .pullup_pin = -EINVAL, /* pull-up driven by UDC */
74};
75
76/*
77 * MACB Ethernet device
78 */
79static struct macb_platform_data __initdata cpu9krea_macb_data = {
80 .phy_irq_pin = -EINVAL,
81 .is_rmii = 1,
82};
83
84/*
85 * NAND flash
86 */
87static struct atmel_nand_data __initdata cpu9krea_nand_data = {
88 .ale = 21,
89 .cle = 22,
90 .rdy_pin = AT91_PIN_PC13,
91 .enable_pin = AT91_PIN_PC14,
92 .bus_width_16 = 0,
93 .det_pin = -EINVAL,
94 .ecc_mode = NAND_ECC_SOFT,
95};
96
97#ifdef CONFIG_MACH_CPU9260
98static struct sam9_smc_config __initdata cpu9krea_nand_smc_config = {
99 .ncs_read_setup = 0,
100 .nrd_setup = 1,
101 .ncs_write_setup = 0,
102 .nwe_setup = 1,
103
104 .ncs_read_pulse = 3,
105 .nrd_pulse = 3,
106 .ncs_write_pulse = 3,
107 .nwe_pulse = 3,
108
109 .read_cycle = 5,
110 .write_cycle = 5,
111
112 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE
113 | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
114 .tdf_cycles = 2,
115};
116#else
117static struct sam9_smc_config __initdata cpu9krea_nand_smc_config = {
118 .ncs_read_setup = 0,
119 .nrd_setup = 2,
120 .ncs_write_setup = 0,
121 .nwe_setup = 2,
122
123 .ncs_read_pulse = 4,
124 .nrd_pulse = 4,
125 .ncs_write_pulse = 4,
126 .nwe_pulse = 4,
127
128 .read_cycle = 7,
129 .write_cycle = 7,
130
131 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE
132 | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
133 .tdf_cycles = 3,
134};
135#endif
136
137static void __init cpu9krea_add_device_nand(void)
138{
139 sam9_smc_configure(0, 3, &cpu9krea_nand_smc_config);
140 at91_add_device_nand(&cpu9krea_nand_data);
141}
142
143/*
144 * NOR flash
145 */
146static struct physmap_flash_data cpuat9260_nor_data = {
147 .width = 2,
148};
149
150#define NOR_BASE AT91_CHIPSELECT_0
151#define NOR_SIZE SZ_64M
152
153static struct resource nor_flash_resources[] = {
154 {
155 .start = NOR_BASE,
156 .end = NOR_BASE + NOR_SIZE - 1,
157 .flags = IORESOURCE_MEM,
158 }
159};
160
161static struct platform_device cpu9krea_nor_flash = {
162 .name = "physmap-flash",
163 .id = 0,
164 .dev = {
165 .platform_data = &cpuat9260_nor_data,
166 },
167 .resource = nor_flash_resources,
168 .num_resources = ARRAY_SIZE(nor_flash_resources),
169};
170
171#ifdef CONFIG_MACH_CPU9260
172static struct sam9_smc_config __initdata cpu9krea_nor_smc_config = {
173 .ncs_read_setup = 0,
174 .nrd_setup = 1,
175 .ncs_write_setup = 0,
176 .nwe_setup = 1,
177
178 .ncs_read_pulse = 10,
179 .nrd_pulse = 10,
180 .ncs_write_pulse = 6,
181 .nwe_pulse = 6,
182
183 .read_cycle = 12,
184 .write_cycle = 8,
185
186 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE
187 | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE
188 | AT91_SMC_DBW_16,
189 .tdf_cycles = 2,
190};
191#else
192static struct sam9_smc_config __initdata cpu9krea_nor_smc_config = {
193 .ncs_read_setup = 0,
194 .nrd_setup = 1,
195 .ncs_write_setup = 0,
196 .nwe_setup = 1,
197
198 .ncs_read_pulse = 13,
199 .nrd_pulse = 13,
200 .ncs_write_pulse = 8,
201 .nwe_pulse = 8,
202
203 .read_cycle = 15,
204 .write_cycle = 10,
205
206 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE
207 | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE
208 | AT91_SMC_DBW_16,
209 .tdf_cycles = 2,
210};
211#endif
212
213static __init void cpu9krea_add_device_nor(void)
214{
215 unsigned long csa;
216
217 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
218 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V);
219
220 /* configure chip-select 0 (NOR) */
221 sam9_smc_configure(0, 0, &cpu9krea_nor_smc_config);
222
223 platform_device_register(&cpu9krea_nor_flash);
224}
225
226/*
227 * LEDs
228 */
229static struct gpio_led cpu9krea_leds[] = {
230 { /* LED1 */
231 .name = "LED1",
232 .gpio = AT91_PIN_PC11,
233 .active_low = 1,
234 .default_trigger = "timer",
235 },
236 { /* LED2 */
237 .name = "LED2",
238 .gpio = AT91_PIN_PC12,
239 .active_low = 1,
240 .default_trigger = "heartbeat",
241 },
242 { /* LED3 */
243 .name = "LED3",
244 .gpio = AT91_PIN_PC7,
245 .active_low = 1,
246 .default_trigger = "none",
247 },
248 { /* LED4 */
249 .name = "LED4",
250 .gpio = AT91_PIN_PC9,
251 .active_low = 1,
252 .default_trigger = "none",
253 }
254};
255
256static struct i2c_board_info __initdata cpu9krea_i2c_devices[] = {
257 {
258 I2C_BOARD_INFO("ds1339", 0x68),
259 },
260};
261
262/*
263 * GPIO Buttons
264 */
265#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
266static struct gpio_keys_button cpu9krea_buttons[] = {
267 {
268 .gpio = AT91_PIN_PC3,
269 .code = BTN_0,
270 .desc = "BP1",
271 .active_low = 1,
272 .wakeup = 1,
273 },
274 {
275 .gpio = AT91_PIN_PB20,
276 .code = BTN_1,
277 .desc = "BP2",
278 .active_low = 1,
279 .wakeup = 1,
280 }
281};
282
283static struct gpio_keys_platform_data cpu9krea_button_data = {
284 .buttons = cpu9krea_buttons,
285 .nbuttons = ARRAY_SIZE(cpu9krea_buttons),
286};
287
288static struct platform_device cpu9krea_button_device = {
289 .name = "gpio-keys",
290 .id = -1,
291 .num_resources = 0,
292 .dev = {
293 .platform_data = &cpu9krea_button_data,
294 }
295};
296
297static void __init cpu9krea_add_device_buttons(void)
298{
299 at91_set_gpio_input(AT91_PIN_PC3, 1); /* BP1 */
300 at91_set_deglitch(AT91_PIN_PC3, 1);
301 at91_set_gpio_input(AT91_PIN_PB20, 1); /* BP2 */
302 at91_set_deglitch(AT91_PIN_PB20, 1);
303
304 platform_device_register(&cpu9krea_button_device);
305}
306#else
307static void __init cpu9krea_add_device_buttons(void)
308{
309}
310#endif
311
312/*
313 * MCI (SD/MMC)
314 */
315static struct mci_platform_data __initdata cpu9krea_mci0_data = {
316 .slot[0] = {
317 .bus_width = 4,
318 .detect_pin = AT91_PIN_PA29,
319 .wp_pin = -EINVAL,
320 },
321};
322
323static void __init cpu9krea_board_init(void)
324{
325 at91_register_devices();
326
327 /* NOR */
328 cpu9krea_add_device_nor();
329 /* Serial */
330 /* DGBU on ttyS0. (Rx & Tx only) */
331 at91_register_uart(0, 0, 0);
332
333 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
334 at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS |
335 ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR |
336 ATMEL_UART_DCD | ATMEL_UART_RI);
337
338 /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
339 at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS |
340 ATMEL_UART_RTS);
341
342 /* USART2 on ttyS3. (Rx, Tx, RTS, CTS) */
343 at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS |
344 ATMEL_UART_RTS);
345
346 /* USART3 on ttyS4. (Rx, Tx) */
347 at91_register_uart(AT91SAM9260_ID_US3, 4, 0);
348
349 /* USART4 on ttyS5. (Rx, Tx) */
350 at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
351
352 /* USART5 on ttyS6. (Rx, Tx) */
353 at91_register_uart(AT91SAM9260_ID_US5, 6, 0);
354 at91_add_device_serial();
355 /* USB Host */
356 at91_add_device_usbh(&cpu9krea_usbh_data);
357 /* USB Device */
358 at91_add_device_udc(&cpu9krea_udc_data);
359 /* NAND */
360 cpu9krea_add_device_nand();
361 /* Ethernet */
362 at91_add_device_eth(&cpu9krea_macb_data);
363 /* MMC */
364 at91_add_device_mci(0, &cpu9krea_mci0_data);
365 /* I2C */
366 at91_add_device_i2c(cpu9krea_i2c_devices,
367 ARRAY_SIZE(cpu9krea_i2c_devices));
368 /* LEDs */
369 at91_gpio_leds(cpu9krea_leds, ARRAY_SIZE(cpu9krea_leds));
370 /* Push Buttons */
371 cpu9krea_add_device_buttons();
372}
373
374#ifdef CONFIG_MACH_CPU9260
375MACHINE_START(CPUAT9260, "Eukrea CPU9260")
376#else
377MACHINE_START(CPUAT9G20, "Eukrea CPU9G20")
378#endif
379 /* Maintainer: Eric Benard - EUKREA Electromatique */
380 .init_time = at91_init_time,
381 .map_io = at91_map_io,
382 .handle_irq = at91_aic_handle_irq,
383 .init_early = cpu9krea_init_early,
384 .init_irq = at91_init_irq_default,
385 .init_machine = cpu9krea_board_init,
386MACHINE_END
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
deleted file mode 100644
index c094350c9314..000000000000
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ /dev/null
@@ -1,189 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-cpuat91.c
3 *
4 * Copyright (C) 2009 Eric Benard - eric@eukrea.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/types.h>
22#include <linux/gpio.h>
23#include <linux/init.h>
24#include <linux/mm.h>
25#include <linux/module.h>
26#include <linux/platform_device.h>
27#include <linux/mtd/physmap.h>
28#include <linux/mtd/plat-ram.h>
29
30#include <mach/hardware.h>
31#include <asm/setup.h>
32#include <asm/mach-types.h>
33#include <asm/irq.h>
34
35#include <asm/mach/arch.h>
36#include <asm/mach/map.h>
37#include <asm/mach/irq.h>
38
39#include <mach/at91rm9200_mc.h>
40#include <mach/at91_ramc.h>
41#include <mach/cpu.h>
42
43#include "at91_aic.h"
44#include "board.h"
45#include "generic.h"
46#include "gpio.h"
47
48
49static struct gpio_led cpuat91_leds[] = {
50 {
51 .name = "led1",
52 .default_trigger = "heartbeat",
53 .active_low = 1,
54 .gpio = AT91_PIN_PC0,
55 },
56};
57
58static void __init cpuat91_init_early(void)
59{
60 /* Set cpu type: PQFP */
61 at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
62
63 /* Initialize processor: 18.432 MHz crystal */
64 at91_initialize(18432000);
65}
66
67static struct macb_platform_data __initdata cpuat91_eth_data = {
68 .phy_irq_pin = -EINVAL,
69 .is_rmii = 1,
70};
71
72static struct at91_usbh_data __initdata cpuat91_usbh_data = {
73 .ports = 1,
74 .vbus_pin = {-EINVAL, -EINVAL},
75 .overcurrent_pin= {-EINVAL, -EINVAL},
76};
77
78static struct at91_udc_data __initdata cpuat91_udc_data = {
79 .vbus_pin = AT91_PIN_PC15,
80 .pullup_pin = AT91_PIN_PC14,
81};
82
83static struct mci_platform_data __initdata cpuat91_mci0_data = {
84 .slot[0] = {
85 .bus_width = 4,
86 .detect_pin = AT91_PIN_PC2,
87 .wp_pin = -EINVAL,
88 },
89};
90
91static struct physmap_flash_data cpuat91_flash_data = {
92 .width = 2,
93};
94
95static struct resource cpuat91_flash_resource = {
96 .start = AT91_CHIPSELECT_0,
97 .end = AT91_CHIPSELECT_0 + SZ_16M - 1,
98 .flags = IORESOURCE_MEM,
99};
100
101static struct platform_device cpuat91_norflash = {
102 .name = "physmap-flash",
103 .id = 0,
104 .dev = {
105 .platform_data = &cpuat91_flash_data,
106 },
107 .resource = &cpuat91_flash_resource,
108 .num_resources = 1,
109};
110
111#ifdef CONFIG_MTD_PLATRAM
112struct platdata_mtd_ram at91_sram_pdata = {
113 .mapname = "SRAM",
114 .bankwidth = 2,
115};
116
117static struct resource at91_sram_resource[] = {
118 [0] = {
119 .start = AT91RM9200_SRAM_BASE,
120 .end = AT91RM9200_SRAM_BASE + AT91RM9200_SRAM_SIZE - 1,
121 .flags = IORESOURCE_MEM,
122 },
123};
124
125static struct platform_device at91_sram = {
126 .name = "mtd-ram",
127 .id = 0,
128 .resource = at91_sram_resource,
129 .num_resources = ARRAY_SIZE(at91_sram_resource),
130 .dev = {
131 .platform_data = &at91_sram_pdata,
132 },
133};
134#endif /* MTD_PLATRAM */
135
136static struct platform_device *platform_devices[] __initdata = {
137 &cpuat91_norflash,
138#ifdef CONFIG_MTD_PLATRAM
139 &at91_sram,
140#endif /* CONFIG_MTD_PLATRAM */
141};
142
143static void __init cpuat91_board_init(void)
144{
145 /* Serial */
146 /* DBGU on ttyS0. (Rx & Tx only) */
147 at91_register_uart(0, 0, 0);
148
149 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */
150 at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS |
151 ATMEL_UART_RTS);
152
153 /* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
154 at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS |
155 ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR |
156 ATMEL_UART_DCD | ATMEL_UART_RI);
157
158 /* USART2 on ttyS3 (Rx, Tx) */
159 at91_register_uart(AT91RM9200_ID_US2, 3, 0);
160
161 /* USART3 on ttyS4 (Rx, Tx, CTS, RTS) */
162 at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_CTS |
163 ATMEL_UART_RTS);
164 at91_add_device_serial();
165 /* LEDs. */
166 at91_gpio_leds(cpuat91_leds, ARRAY_SIZE(cpuat91_leds));
167 /* Ethernet */
168 at91_add_device_eth(&cpuat91_eth_data);
169 /* USB Host */
170 at91_add_device_usbh(&cpuat91_usbh_data);
171 /* USB Device */
172 at91_add_device_udc(&cpuat91_udc_data);
173 /* MMC */
174 at91_add_device_mci(0, &cpuat91_mci0_data);
175 /* I2C */
176 at91_add_device_i2c(NULL, 0);
177 /* Platform devices */
178 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
179}
180
181MACHINE_START(CPUAT91, "Eukrea")
182 /* Maintainer: Eric Benard - EUKREA Electromatique */
183 .init_time = at91rm9200_timer_init,
184 .map_io = at91_map_io,
185 .handle_irq = at91_aic_handle_irq,
186 .init_early = cpuat91_init_early,
187 .init_irq = at91_init_irq_default,
188 .init_machine = cpuat91_board_init,
189MACHINE_END
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
deleted file mode 100644
index 0e35a45cf8d4..000000000000
--- a/arch/arm/mach-at91/board-csb337.c
+++ /dev/null
@@ -1,260 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-csb337.c
3 *
4 * Copyright (C) 2005 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/types.h>
22#include <linux/gpio.h>
23#include <linux/init.h>
24#include <linux/mm.h>
25#include <linux/module.h>
26#include <linux/platform_device.h>
27#include <linux/spi/spi.h>
28#include <linux/mtd/physmap.h>
29#include <linux/input.h>
30#include <linux/gpio_keys.h>
31
32#include <asm/setup.h>
33#include <asm/mach-types.h>
34#include <asm/irq.h>
35
36#include <asm/mach/arch.h>
37#include <asm/mach/map.h>
38#include <asm/mach/irq.h>
39
40#include <mach/hardware.h>
41
42#include "at91_aic.h"
43#include "board.h"
44#include "generic.h"
45#include "gpio.h"
46
47static void __init csb337_init_early(void)
48{
49 /* Initialize processor: 3.6864 MHz crystal */
50 at91_initialize(3686400);
51}
52
53static struct macb_platform_data __initdata csb337_eth_data = {
54 .phy_irq_pin = AT91_PIN_PC2,
55 .is_rmii = 0,
56 /* The CSB337 bootloader stores the MAC the wrong-way around */
57 .rev_eth_addr = 1,
58};
59
60static struct at91_usbh_data __initdata csb337_usbh_data = {
61 .ports = 2,
62 .vbus_pin = {-EINVAL, -EINVAL},
63 .overcurrent_pin= {-EINVAL, -EINVAL},
64};
65
66static struct at91_udc_data __initdata csb337_udc_data = {
67 .pullup_pin = AT91_PIN_PA24,
68 .vbus_pin = -EINVAL,
69};
70
71static struct i2c_board_info __initdata csb337_i2c_devices[] = {
72 {
73 I2C_BOARD_INFO("ds1307", 0x68),
74 },
75};
76
77static struct at91_cf_data __initdata csb337_cf_data = {
78 /*
79 * connector P4 on the CSB 337 mates to
80 * connector P8 on the CSB 300CF
81 */
82
83 /* CSB337 specific */
84 .det_pin = AT91_PIN_PC3,
85
86 /* CSB300CF specific */
87 .irq_pin = AT91_PIN_PA19,
88 .vcc_pin = AT91_PIN_PD0,
89 .rst_pin = AT91_PIN_PD2,
90};
91
92static struct mci_platform_data __initdata csb337_mci0_data = {
93 .slot[0] = {
94 .bus_width = 4,
95 .detect_pin = AT91_PIN_PD5,
96 .wp_pin = AT91_PIN_PD6,
97 },
98};
99
100static struct spi_board_info csb337_spi_devices[] = {
101 { /* CAN controller */
102 .modalias = "sak82c900",
103 .chip_select = 0,
104 .max_speed_hz = 6 * 1000 * 1000,
105 },
106};
107
108#define CSB_FLASH_BASE AT91_CHIPSELECT_0
109#define CSB_FLASH_SIZE SZ_8M
110
111static struct mtd_partition csb_flash_partitions[] = {
112 {
113 .name = "uMON flash",
114 .offset = 0,
115 .size = MTDPART_SIZ_FULL,
116 .mask_flags = MTD_WRITEABLE, /* read only */
117 }
118};
119
120static struct physmap_flash_data csb_flash_data = {
121 .width = 2,
122 .parts = csb_flash_partitions,
123 .nr_parts = ARRAY_SIZE(csb_flash_partitions),
124};
125
126static struct resource csb_flash_resources[] = {
127 {
128 .start = CSB_FLASH_BASE,
129 .end = CSB_FLASH_BASE + CSB_FLASH_SIZE - 1,
130 .flags = IORESOURCE_MEM,
131 }
132};
133
134static struct platform_device csb_flash = {
135 .name = "physmap-flash",
136 .id = 0,
137 .dev = {
138 .platform_data = &csb_flash_data,
139 },
140 .resource = csb_flash_resources,
141 .num_resources = ARRAY_SIZE(csb_flash_resources),
142};
143
144/*
145 * GPIO Buttons (on CSB300)
146 */
147#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
148static struct gpio_keys_button csb300_buttons[] = {
149 {
150 .gpio = AT91_PIN_PB29,
151 .code = BTN_0,
152 .desc = "sw0",
153 .active_low = 1,
154 .wakeup = 1,
155 },
156 {
157 .gpio = AT91_PIN_PB28,
158 .code = BTN_1,
159 .desc = "sw1",
160 .active_low = 1,
161 .wakeup = 1,
162 },
163 {
164 .gpio = AT91_PIN_PA21,
165 .code = BTN_2,
166 .desc = "sw2",
167 .active_low = 1,
168 .wakeup = 1,
169 }
170};
171
172static struct gpio_keys_platform_data csb300_button_data = {
173 .buttons = csb300_buttons,
174 .nbuttons = ARRAY_SIZE(csb300_buttons),
175};
176
177static struct platform_device csb300_button_device = {
178 .name = "gpio-keys",
179 .id = -1,
180 .num_resources = 0,
181 .dev = {
182 .platform_data = &csb300_button_data,
183 }
184};
185
186static void __init csb300_add_device_buttons(void)
187{
188 at91_set_gpio_input(AT91_PIN_PB29, 1); /* sw0 */
189 at91_set_deglitch(AT91_PIN_PB29, 1);
190 at91_set_gpio_input(AT91_PIN_PB28, 1); /* sw1 */
191 at91_set_deglitch(AT91_PIN_PB28, 1);
192 at91_set_gpio_input(AT91_PIN_PA21, 1); /* sw2 */
193 at91_set_deglitch(AT91_PIN_PA21, 1);
194
195 platform_device_register(&csb300_button_device);
196}
197#else
198static void __init csb300_add_device_buttons(void) {}
199#endif
200
201static struct gpio_led csb_leds[] = {
202 { /* "led0", yellow */
203 .name = "led0",
204 .gpio = AT91_PIN_PB2,
205 .active_low = 1,
206 .default_trigger = "heartbeat",
207 },
208 { /* "led1", green */
209 .name = "led1",
210 .gpio = AT91_PIN_PB1,
211 .active_low = 1,
212 .default_trigger = "mmc0",
213 },
214 { /* "led2", yellow */
215 .name = "led2",
216 .gpio = AT91_PIN_PB0,
217 .active_low = 1,
218 .default_trigger = "ide-disk",
219 }
220};
221
222
223static void __init csb337_board_init(void)
224{
225 /* Serial */
226 /* DBGU on ttyS0 */
227 at91_register_uart(0, 0, 0);
228 at91_add_device_serial();
229 /* Ethernet */
230 at91_add_device_eth(&csb337_eth_data);
231 /* USB Host */
232 at91_add_device_usbh(&csb337_usbh_data);
233 /* USB Device */
234 at91_add_device_udc(&csb337_udc_data);
235 /* I2C */
236 at91_add_device_i2c(csb337_i2c_devices, ARRAY_SIZE(csb337_i2c_devices));
237 /* Compact Flash */
238 at91_set_gpio_input(AT91_PIN_PB22, 1); /* IOIS16 */
239 at91_add_device_cf(&csb337_cf_data);
240 /* SPI */
241 at91_add_device_spi(csb337_spi_devices, ARRAY_SIZE(csb337_spi_devices));
242 /* MMC */
243 at91_add_device_mci(0, &csb337_mci0_data);
244 /* NOR flash */
245 platform_device_register(&csb_flash);
246 /* LEDs */
247 at91_gpio_leds(csb_leds, ARRAY_SIZE(csb_leds));
248 /* Switches on CSB300 */
249 csb300_add_device_buttons();
250}
251
252MACHINE_START(CSB337, "Cogent CSB337")
253 /* Maintainer: Bill Gatliff */
254 .init_time = at91rm9200_timer_init,
255 .map_io = at91_map_io,
256 .handle_irq = at91_aic_handle_irq,
257 .init_early = csb337_init_early,
258 .init_irq = at91_init_irq_default,
259 .init_machine = csb337_board_init,
260MACHINE_END
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
deleted file mode 100644
index 18d027f529a8..000000000000
--- a/arch/arm/mach-at91/board-csb637.c
+++ /dev/null
@@ -1,142 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-csb637.c
3 *
4 * Copyright (C) 2005 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/types.h>
22#include <linux/init.h>
23#include <linux/gpio.h>
24#include <linux/mm.h>
25#include <linux/module.h>
26#include <linux/platform_device.h>
27#include <linux/mtd/physmap.h>
28
29#include <asm/setup.h>
30#include <asm/mach-types.h>
31#include <asm/irq.h>
32
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35#include <asm/mach/irq.h>
36
37#include <mach/hardware.h>
38
39#include "at91_aic.h"
40#include "board.h"
41#include "generic.h"
42#include "gpio.h"
43
44
45static void __init csb637_init_early(void)
46{
47 /* Initialize processor: 3.6864 MHz crystal */
48 at91_initialize(3686400);
49}
50
51static struct macb_platform_data __initdata csb637_eth_data = {
52 .phy_irq_pin = AT91_PIN_PC0,
53 .is_rmii = 0,
54};
55
56static struct at91_usbh_data __initdata csb637_usbh_data = {
57 .ports = 2,
58 .vbus_pin = {-EINVAL, -EINVAL},
59 .overcurrent_pin= {-EINVAL, -EINVAL},
60};
61
62static struct at91_udc_data __initdata csb637_udc_data = {
63 .vbus_pin = AT91_PIN_PB28,
64 .pullup_pin = AT91_PIN_PB1,
65};
66
67#define CSB_FLASH_BASE AT91_CHIPSELECT_0
68#define CSB_FLASH_SIZE SZ_16M
69
70static struct mtd_partition csb_flash_partitions[] = {
71 {
72 .name = "uMON flash",
73 .offset = 0,
74 .size = MTDPART_SIZ_FULL,
75 .mask_flags = MTD_WRITEABLE, /* read only */
76 }
77};
78
79static struct physmap_flash_data csb_flash_data = {
80 .width = 2,
81 .parts = csb_flash_partitions,
82 .nr_parts = ARRAY_SIZE(csb_flash_partitions),
83};
84
85static struct resource csb_flash_resources[] = {
86 {
87 .start = CSB_FLASH_BASE,
88 .end = CSB_FLASH_BASE + CSB_FLASH_SIZE - 1,
89 .flags = IORESOURCE_MEM,
90 }
91};
92
93static struct platform_device csb_flash = {
94 .name = "physmap-flash",
95 .id = 0,
96 .dev = {
97 .platform_data = &csb_flash_data,
98 },
99 .resource = csb_flash_resources,
100 .num_resources = ARRAY_SIZE(csb_flash_resources),
101};
102
103static struct gpio_led csb_leds[] = {
104 { /* "d1", red */
105 .name = "d1",
106 .gpio = AT91_PIN_PB2,
107 .active_low = 1,
108 .default_trigger = "heartbeat",
109 },
110};
111
112static void __init csb637_board_init(void)
113{
114 /* LED(s) */
115 at91_gpio_leds(csb_leds, ARRAY_SIZE(csb_leds));
116 /* Serial */
117 /* DBGU on ttyS0. (Rx & Tx only) */
118 at91_register_uart(0, 0, 0);
119 at91_add_device_serial();
120 /* Ethernet */
121 at91_add_device_eth(&csb637_eth_data);
122 /* USB Host */
123 at91_add_device_usbh(&csb637_usbh_data);
124 /* USB Device */
125 at91_add_device_udc(&csb637_udc_data);
126 /* I2C */
127 at91_add_device_i2c(NULL, 0);
128 /* SPI */
129 at91_add_device_spi(NULL, 0);
130 /* NOR flash */
131 platform_device_register(&csb_flash);
132}
133
134MACHINE_START(CSB637, "Cogent CSB637")
135 /* Maintainer: Bill Gatliff */
136 .init_time = at91rm9200_timer_init,
137 .map_io = at91_map_io,
138 .handle_irq = at91_aic_handle_irq,
139 .init_early = csb637_init_early,
140 .init_irq = at91_init_irq_default,
141 .init_machine = csb637_board_init,
142MACHINE_END
diff --git a/arch/arm/mach-at91/board-dt-rm9200.c b/arch/arm/mach-at91/board-dt-rm9200.c
index 226563f850b8..76dfe8f9af50 100644
--- a/arch/arm/mach-at91/board-dt-rm9200.c
+++ b/arch/arm/mach-at91/board-dt-rm9200.c
@@ -22,14 +22,11 @@
22#include <asm/mach/map.h> 22#include <asm/mach/map.h>
23#include <asm/mach/irq.h> 23#include <asm/mach/irq.h>
24 24
25#include "at91_aic.h"
26#include "generic.h" 25#include "generic.h"
27 26
28static void __init at91rm9200_dt_timer_init(void) 27static void __init at91rm9200_dt_timer_init(void)
29{ 28{
30#if defined(CONFIG_COMMON_CLK)
31 of_clk_init(NULL); 29 of_clk_init(NULL);
32#endif
33 at91rm9200_timer_init(); 30 at91rm9200_timer_init();
34} 31}
35 32
diff --git a/arch/arm/mach-at91/board-dt-sam9.c b/arch/arm/mach-at91/board-dt-sam9.c
index d3048ccdc41f..f99246aa9b38 100644
--- a/arch/arm/mach-at91/board-dt-sam9.c
+++ b/arch/arm/mach-at91/board-dt-sam9.c
@@ -21,8 +21,6 @@
21#include <asm/mach/map.h> 21#include <asm/mach/map.h>
22#include <asm/mach/irq.h> 22#include <asm/mach/irq.h>
23 23
24#include "at91_aic.h"
25#include "board.h"
26#include "generic.h" 24#include "generic.h"
27 25
28static const char *at91_dt_board_compat[] __initdata = { 26static const char *at91_dt_board_compat[] __initdata = {
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index 129e2917506b..8fb9ef5333f1 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -24,7 +24,6 @@
24#include <asm/mach/map.h> 24#include <asm/mach/map.h>
25#include <asm/mach/irq.h> 25#include <asm/mach/irq.h>
26 26
27#include "at91_aic.h"
28#include "generic.h" 27#include "generic.h"
29 28
30static void __init sama5_dt_device_init(void) 29static void __init sama5_dt_device_init(void)
diff --git a/arch/arm/mach-at91/board-eb01.c b/arch/arm/mach-at91/board-eb01.c
deleted file mode 100644
index becf0a6a289e..000000000000
--- a/arch/arm/mach-at91/board-eb01.c
+++ /dev/null
@@ -1,52 +0,0 @@
1/*
2 * arch/arm/mach-at91/board-eb01.c
3 *
4 * (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/irq.h>
26#include <asm/mach-types.h>
27#include <mach/hardware.h>
28#include <asm/mach/arch.h>
29#include <asm/mach/map.h>
30
31#include "at91_aic.h"
32#include "board.h"
33#include "generic.h"
34
35static void __init at91eb01_init_irq(void)
36{
37 at91x40_init_interrupts(NULL);
38}
39
40static void __init at91eb01_init_early(void)
41{
42 at91x40_initialize(40000000);
43}
44
45MACHINE_START(AT91EB01, "Atmel AT91 EB01")
46 /* Maintainer: Greg Ungerer <gerg@snapgear.com> */
47 .init_time = at91x40_timer_init,
48 .handle_irq = at91_aic_handle_irq,
49 .init_early = at91eb01_init_early,
50 .init_irq = at91eb01_init_irq,
51MACHINE_END
52
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
deleted file mode 100644
index aa457a8b22f5..000000000000
--- a/arch/arm/mach-at91/board-eb9200.c
+++ /dev/null
@@ -1,126 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-eb9200.c
3 *
4 * Copyright (C) 2005 SAN People, adapted for ATEB9200 from Embest
5 * by Andrew Patrikalakis
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/types.h>
23#include <linux/gpio.h>
24#include <linux/init.h>
25#include <linux/mm.h>
26#include <linux/module.h>
27#include <linux/device.h>
28
29#include <mach/hardware.h>
30#include <asm/setup.h>
31#include <asm/mach-types.h>
32#include <asm/irq.h>
33
34#include <asm/mach/arch.h>
35#include <asm/mach/map.h>
36#include <asm/mach/irq.h>
37
38#include "at91_aic.h"
39#include "board.h"
40#include "generic.h"
41#include "gpio.h"
42
43
44static void __init eb9200_init_early(void)
45{
46 /* Initialize processor: 18.432 MHz crystal */
47 at91_initialize(18432000);
48}
49
50static struct macb_platform_data __initdata eb9200_eth_data = {
51 .phy_irq_pin = AT91_PIN_PC4,
52 .is_rmii = 1,
53};
54
55static struct at91_usbh_data __initdata eb9200_usbh_data = {
56 .ports = 2,
57 .vbus_pin = {-EINVAL, -EINVAL},
58 .overcurrent_pin= {-EINVAL, -EINVAL},
59};
60
61static struct at91_udc_data __initdata eb9200_udc_data = {
62 .vbus_pin = AT91_PIN_PD4,
63 .pullup_pin = AT91_PIN_PD5,
64};
65
66static struct at91_cf_data __initdata eb9200_cf_data = {
67 .irq_pin = -EINVAL,
68 .det_pin = AT91_PIN_PB0,
69 .vcc_pin = -EINVAL,
70 .rst_pin = AT91_PIN_PC5,
71};
72
73static struct mci_platform_data __initdata eb9200_mci0_data = {
74 .slot[0] = {
75 .bus_width = 4,
76 .detect_pin = -EINVAL,
77 .wp_pin = -EINVAL,
78 },
79};
80
81static struct i2c_board_info __initdata eb9200_i2c_devices[] = {
82 {
83 I2C_BOARD_INFO("24c512", 0x50),
84 },
85};
86
87
88static void __init eb9200_board_init(void)
89{
90 /* Serial */
91 /* DBGU on ttyS0. (Rx & Tx only) */
92 at91_register_uart(0, 0, 0);
93
94 /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
95 at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
96 | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
97 | ATMEL_UART_RI);
98
99 /* USART2 on ttyS2. (Rx, Tx) - IRDA */
100 at91_register_uart(AT91RM9200_ID_US2, 2, 0);
101 at91_add_device_serial();
102 /* Ethernet */
103 at91_add_device_eth(&eb9200_eth_data);
104 /* USB Host */
105 at91_add_device_usbh(&eb9200_usbh_data);
106 /* USB Device */
107 at91_add_device_udc(&eb9200_udc_data);
108 /* I2C */
109 at91_add_device_i2c(eb9200_i2c_devices, ARRAY_SIZE(eb9200_i2c_devices));
110 /* Compact Flash */
111 at91_add_device_cf(&eb9200_cf_data);
112 /* SPI */
113 at91_add_device_spi(NULL, 0);
114 /* MMC */
115 /* only supports 1 or 4 bit interface, not wired through to SPI */
116 at91_add_device_mci(0, &eb9200_mci0_data);
117}
118
119MACHINE_START(ATEB9200, "Embest ATEB9200")
120 .init_time = at91rm9200_timer_init,
121 .map_io = at91_map_io,
122 .handle_irq = at91_aic_handle_irq,
123 .init_early = eb9200_init_early,
124 .init_irq = at91_init_irq_default,
125 .init_machine = eb9200_board_init,
126MACHINE_END
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
deleted file mode 100644
index ede1373ccaba..000000000000
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ /dev/null
@@ -1,191 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91rm9200/board-ecbat91.c
3 * Copyright (C) 2007 emQbit.com.
4 *
5 * We started from board-dk.c, which is Copyright (C) 2005 SAN People.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/types.h>
23#include <linux/gpio.h>
24#include <linux/init.h>
25#include <linux/mm.h>
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/spi/spi.h>
29#include <linux/spi/flash.h>
30
31#include <mach/hardware.h>
32#include <asm/setup.h>
33#include <asm/mach-types.h>
34#include <asm/irq.h>
35
36#include <asm/mach/arch.h>
37#include <asm/mach/map.h>
38#include <asm/mach/irq.h>
39
40#include <mach/cpu.h>
41
42#include "at91_aic.h"
43#include "board.h"
44#include "generic.h"
45#include "gpio.h"
46
47
48static void __init ecb_at91init_early(void)
49{
50 /* Set cpu type: PQFP */
51 at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
52
53 /* Initialize processor: 18.432 MHz crystal */
54 at91_initialize(18432000);
55}
56
57static struct macb_platform_data __initdata ecb_at91eth_data = {
58 .phy_irq_pin = AT91_PIN_PC4,
59 .is_rmii = 0,
60};
61
62static struct at91_usbh_data __initdata ecb_at91usbh_data = {
63 .ports = 1,
64 .vbus_pin = {-EINVAL, -EINVAL},
65 .overcurrent_pin= {-EINVAL, -EINVAL},
66};
67
68static struct mci_platform_data __initdata ecbat91_mci0_data = {
69 .slot[0] = {
70 .bus_width = 4,
71 .detect_pin = -EINVAL,
72 .wp_pin = -EINVAL,
73 },
74};
75
76
77#if defined(CONFIG_MTD_DATAFLASH)
78static struct mtd_partition __initdata my_flash0_partitions[] =
79{
80 { /* 0x8400 */
81 .name = "Darrell-loader",
82 .offset = 0,
83 .size = 12 * 1056,
84 },
85 {
86 .name = "U-boot",
87 .offset = MTDPART_OFS_NXTBLK,
88 .size = 110 * 1056,
89 },
90 { /* 1336 (167 blocks) pages * 1056 bytes = 0x158700 bytes */
91 .name = "UBoot-env",
92 .offset = MTDPART_OFS_NXTBLK,
93 .size = 8 * 1056,
94 },
95 { /* 1336 (167 blocks) pages * 1056 bytes = 0x158700 bytes */
96 .name = "Kernel",
97 .offset = MTDPART_OFS_NXTBLK,
98 .size = 1534 * 1056,
99 },
100 { /* 190200 - jffs2 root filesystem */
101 .name = "Filesystem",
102 .offset = MTDPART_OFS_NXTBLK,
103 .size = MTDPART_SIZ_FULL, /* 26 sectors */
104 }
105};
106
107static struct flash_platform_data __initdata my_flash0_platform = {
108 .name = "Removable flash card",
109 .parts = my_flash0_partitions,
110 .nr_parts = ARRAY_SIZE(my_flash0_partitions)
111};
112
113#endif
114
115static struct spi_board_info __initdata ecb_at91spi_devices[] = {
116 { /* DataFlash chip */
117 .modalias = "mtd_dataflash",
118 .chip_select = 0,
119 .max_speed_hz = 10 * 1000 * 1000,
120 .bus_num = 0,
121#if defined(CONFIG_MTD_DATAFLASH)
122 .platform_data = &my_flash0_platform,
123#endif
124 },
125 { /* User accessible spi - cs1 (250KHz) */
126 .modalias = "spi-cs1",
127 .chip_select = 1,
128 .max_speed_hz = 250 * 1000,
129 },
130 { /* User accessible spi - cs2 (1MHz) */
131 .modalias = "spi-cs2",
132 .chip_select = 2,
133 .max_speed_hz = 1 * 1000 * 1000,
134 },
135 { /* User accessible spi - cs3 (10MHz) */
136 .modalias = "spi-cs3",
137 .chip_select = 3,
138 .max_speed_hz = 10 * 1000 * 1000,
139 },
140};
141
142/*
143 * LEDs
144 */
145static struct gpio_led ecb_leds[] = {
146 { /* D1 */
147 .name = "led1",
148 .gpio = AT91_PIN_PC7,
149 .active_low = 1,
150 .default_trigger = "heartbeat",
151 }
152};
153
154static void __init ecb_at91board_init(void)
155{
156 /* Serial */
157 /* DBGU on ttyS0. (Rx & Tx only) */
158 at91_register_uart(0, 0, 0);
159
160 /* USART0 on ttyS1. (Rx & Tx only) */
161 at91_register_uart(AT91RM9200_ID_US0, 1, 0);
162 at91_add_device_serial();
163
164 /* Ethernet */
165 at91_add_device_eth(&ecb_at91eth_data);
166
167 /* USB Host */
168 at91_add_device_usbh(&ecb_at91usbh_data);
169
170 /* I2C */
171 at91_add_device_i2c(NULL, 0);
172
173 /* MMC */
174 at91_add_device_mci(0, &ecbat91_mci0_data);
175
176 /* SPI */
177 at91_add_device_spi(ecb_at91spi_devices, ARRAY_SIZE(ecb_at91spi_devices));
178
179 /* LEDs */
180 at91_gpio_leds(ecb_leds, ARRAY_SIZE(ecb_leds));
181}
182
183MACHINE_START(ECBAT91, "emQbit's ECB_AT91")
184 /* Maintainer: emQbit.com */
185 .init_time = at91rm9200_timer_init,
186 .map_io = at91_map_io,
187 .handle_irq = at91_aic_handle_irq,
188 .init_early = ecb_at91init_early,
189 .init_irq = at91_init_irq_default,
190 .init_machine = ecb_at91board_init,
191MACHINE_END
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
deleted file mode 100644
index 4e75321a8f2a..000000000000
--- a/arch/arm/mach-at91/board-eco920.c
+++ /dev/null
@@ -1,160 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
15 */
16
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/mtd/physmap.h>
20#include <linux/gpio.h>
21
22#include <asm/mach-types.h>
23
24#include <asm/mach/arch.h>
25#include <asm/mach/map.h>
26
27#include <mach/at91rm9200_mc.h>
28#include <mach/at91_ramc.h>
29#include <mach/cpu.h>
30
31#include "at91_aic.h"
32#include "board.h"
33#include "generic.h"
34#include "gpio.h"
35
36
37static void __init eco920_init_early(void)
38{
39 /* Set cpu type: PQFP */
40 at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
41
42 at91_initialize(18432000);
43}
44
45static struct macb_platform_data __initdata eco920_eth_data = {
46 .phy_irq_pin = AT91_PIN_PC2,
47 .is_rmii = 1,
48};
49
50static struct at91_usbh_data __initdata eco920_usbh_data = {
51 .ports = 1,
52 .vbus_pin = {-EINVAL, -EINVAL},
53 .overcurrent_pin= {-EINVAL, -EINVAL},
54};
55
56static struct at91_udc_data __initdata eco920_udc_data = {
57 .vbus_pin = AT91_PIN_PB12,
58 .pullup_pin = AT91_PIN_PB13,
59};
60
61static struct mci_platform_data __initdata eco920_mci0_data = {
62 .slot[0] = {
63 .bus_width = 1,
64 .detect_pin = -EINVAL,
65 .wp_pin = -EINVAL,
66 },
67};
68
69static struct physmap_flash_data eco920_flash_data = {
70 .width = 2,
71};
72
73static struct resource eco920_flash_resource = {
74 .start = 0x11000000,
75 .end = 0x11ffffff,
76 .flags = IORESOURCE_MEM,
77};
78
79static struct platform_device eco920_flash = {
80 .name = "physmap-flash",
81 .id = 0,
82 .dev = {
83 .platform_data = &eco920_flash_data,
84 },
85 .resource = &eco920_flash_resource,
86 .num_resources = 1,
87};
88
89static struct spi_board_info eco920_spi_devices[] = {
90 { /* CAN controller */
91 .modalias = "tlv5638",
92 .chip_select = 3,
93 .max_speed_hz = 20 * 1000 * 1000,
94 .mode = SPI_CPHA,
95 },
96};
97
98/*
99 * LEDs
100 */
101static struct gpio_led eco920_leds[] = {
102 { /* D1 */
103 .name = "led1",
104 .gpio = AT91_PIN_PB0,
105 .active_low = 1,
106 .default_trigger = "heartbeat",
107 },
108 { /* D2 */
109 .name = "led2",
110 .gpio = AT91_PIN_PB1,
111 .active_low = 1,
112 .default_trigger = "timer",
113 }
114};
115
116static void __init eco920_board_init(void)
117{
118 /* DBGU on ttyS0. (Rx & Tx only */
119 at91_register_uart(0, 0, 0);
120 at91_add_device_serial();
121 at91_add_device_eth(&eco920_eth_data);
122 at91_add_device_usbh(&eco920_usbh_data);
123 at91_add_device_udc(&eco920_udc_data);
124
125 at91_add_device_mci(0, &eco920_mci0_data);
126 platform_device_register(&eco920_flash);
127
128 at91_ramc_write(0, AT91_SMC_CSR(7), AT91_SMC_RWHOLD_(1)
129 | AT91_SMC_RWSETUP_(1)
130 | AT91_SMC_DBW_8
131 | AT91_SMC_WSEN
132 | AT91_SMC_NWS_(15));
133
134 at91_set_A_periph(AT91_PIN_PC6, 1);
135
136 at91_set_gpio_input(AT91_PIN_PA23, 0);
137 at91_set_deglitch(AT91_PIN_PA23, 1);
138
139/* Initialization of the Static Memory Controller for Chip Select 3 */
140 at91_ramc_write(0, AT91_SMC_CSR(3),
141 AT91_SMC_DBW_16 | /* 16 bit */
142 AT91_SMC_WSEN |
143 AT91_SMC_NWS_(5) | /* wait states */
144 AT91_SMC_TDF_(1) /* float time */
145 );
146
147 at91_add_device_spi(eco920_spi_devices, ARRAY_SIZE(eco920_spi_devices));
148 /* LEDs */
149 at91_gpio_leds(eco920_leds, ARRAY_SIZE(eco920_leds));
150}
151
152MACHINE_START(ECO920, "eco920")
153 /* Maintainer: Sascha Hauer */
154 .init_time = at91rm9200_timer_init,
155 .map_io = at91_map_io,
156 .handle_irq = at91_aic_handle_irq,
157 .init_early = eco920_init_early,
158 .init_irq = at91_init_irq_default,
159 .init_machine = eco920_board_init,
160MACHINE_END
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
deleted file mode 100644
index a6aa4a2432f2..000000000000
--- a/arch/arm/mach-at91/board-flexibity.c
+++ /dev/null
@@ -1,171 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-flexibity.c
3 *
4 * Copyright (C) 2010-2011 Flexibity
5 * Copyright (C) 2005 SAN People
6 * Copyright (C) 2006 Atmel
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/init.h>
24#include <linux/platform_device.h>
25#include <linux/spi/spi.h>
26#include <linux/input.h>
27#include <linux/gpio.h>
28
29#include <asm/mach-types.h>
30
31#include <asm/mach/arch.h>
32#include <asm/mach/map.h>
33#include <asm/mach/irq.h>
34
35#include <mach/hardware.h>
36
37#include "at91_aic.h"
38#include "board.h"
39#include "generic.h"
40#include "gpio.h"
41
42static void __init flexibity_init_early(void)
43{
44 /* Initialize processor: 18.432 MHz crystal */
45 at91_initialize(18432000);
46}
47
48/* USB Host port */
49static struct at91_usbh_data __initdata flexibity_usbh_data = {
50 .ports = 2,
51 .vbus_pin = {-EINVAL, -EINVAL},
52 .overcurrent_pin= {-EINVAL, -EINVAL},
53};
54
55/* USB Device port */
56static struct at91_udc_data __initdata flexibity_udc_data = {
57 .vbus_pin = AT91_PIN_PC5,
58 .pullup_pin = -EINVAL, /* pull-up driven by UDC */
59};
60
61/* I2C devices */
62static struct i2c_board_info __initdata flexibity_i2c_devices[] = {
63 {
64 I2C_BOARD_INFO("ds1307", 0x68),
65 },
66};
67
68/* SPI devices */
69static struct spi_board_info flexibity_spi_devices[] = {
70 { /* DataFlash chip */
71 .modalias = "mtd_dataflash",
72 .chip_select = 1,
73 .max_speed_hz = 15 * 1000 * 1000,
74 .bus_num = 0,
75 },
76};
77
78/* MCI (SD/MMC) */
79static struct mci_platform_data __initdata flexibity_mci0_data = {
80 .slot[0] = {
81 .bus_width = 4,
82 .detect_pin = AT91_PIN_PC9,
83 .wp_pin = AT91_PIN_PC4,
84 },
85};
86
87/* LEDs */
88static struct gpio_led flexibity_leds[] = {
89 {
90 .name = "usb1:green",
91 .gpio = AT91_PIN_PA12,
92 .active_low = 1,
93 .default_trigger = "default-on",
94 },
95 {
96 .name = "usb1:red",
97 .gpio = AT91_PIN_PA13,
98 .active_low = 1,
99 .default_trigger = "default-on",
100 },
101 {
102 .name = "usb2:green",
103 .gpio = AT91_PIN_PB26,
104 .active_low = 1,
105 .default_trigger = "default-on",
106 },
107 {
108 .name = "usb2:red",
109 .gpio = AT91_PIN_PB27,
110 .active_low = 1,
111 .default_trigger = "default-on",
112 },
113 {
114 .name = "usb3:green",
115 .gpio = AT91_PIN_PC8,
116 .active_low = 1,
117 .default_trigger = "default-on",
118 },
119 {
120 .name = "usb3:red",
121 .gpio = AT91_PIN_PC6,
122 .active_low = 1,
123 .default_trigger = "default-on",
124 },
125 {
126 .name = "usb4:green",
127 .gpio = AT91_PIN_PB4,
128 .active_low = 1,
129 .default_trigger = "default-on",
130 },
131 {
132 .name = "usb4:red",
133 .gpio = AT91_PIN_PB5,
134 .active_low = 1,
135 .default_trigger = "default-on",
136 }
137};
138
139static void __init flexibity_board_init(void)
140{
141 at91_register_devices();
142
143 /* Serial */
144 /* DBGU on ttyS0. (Rx & Tx only) */
145 at91_register_uart(0, 0, 0);
146 at91_add_device_serial();
147 /* USB Host */
148 at91_add_device_usbh(&flexibity_usbh_data);
149 /* USB Device */
150 at91_add_device_udc(&flexibity_udc_data);
151 /* I2C */
152 at91_add_device_i2c(flexibity_i2c_devices,
153 ARRAY_SIZE(flexibity_i2c_devices));
154 /* SPI */
155 at91_add_device_spi(flexibity_spi_devices,
156 ARRAY_SIZE(flexibity_spi_devices));
157 /* MMC */
158 at91_add_device_mci(0, &flexibity_mci0_data);
159 /* LEDs */
160 at91_gpio_leds(flexibity_leds, ARRAY_SIZE(flexibity_leds));
161}
162
163MACHINE_START(FLEXIBITY, "Flexibity Connect")
164 /* Maintainer: Maxim Osipov */
165 .init_time = at91_init_time,
166 .map_io = at91_map_io,
167 .handle_irq = at91_aic_handle_irq,
168 .init_early = flexibity_init_early,
169 .init_irq = at91_init_irq_default,
170 .init_machine = flexibity_board_init,
171MACHINE_END
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
deleted file mode 100644
index bf5cc55c7db6..000000000000
--- a/arch/arm/mach-at91/board-gsia18s.c
+++ /dev/null
@@ -1,585 +0,0 @@
1/*
2 * Copyright (C) 2010 Christian Glindkamp <christian.glindkamp@taskit.de>
3 * taskit GmbH
4 * 2010 Igor Plyatov <plyatov@gmail.com>
5 * GeoSIG Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/platform_device.h>
23#include <linux/gpio.h>
24#include <linux/w1-gpio.h>
25#include <linux/i2c.h>
26#include <linux/i2c/pcf857x.h>
27#include <linux/gpio_keys.h>
28#include <linux/input.h>
29
30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32
33#include <mach/at91sam9_smc.h>
34#include <mach/hardware.h>
35
36#include "at91_aic.h"
37#include "board.h"
38#include "sam9_smc.h"
39#include "generic.h"
40#include "gsia18s.h"
41#include "stamp9g20.h"
42#include "gpio.h"
43
44static void __init gsia18s_init_early(void)
45{
46 stamp9g20_init_early();
47}
48
49/*
50 * Two USB Host ports
51 */
52static struct at91_usbh_data __initdata usbh_data = {
53 .ports = 2,
54 .vbus_pin = {-EINVAL, -EINVAL},
55 .overcurrent_pin= {-EINVAL, -EINVAL},
56};
57
58/*
59 * USB Device port
60 */
61static struct at91_udc_data __initdata udc_data = {
62 .vbus_pin = AT91_PIN_PA22,
63 .pullup_pin = -EINVAL, /* pull-up driven by UDC */
64};
65
66/*
67 * MACB Ethernet device
68 */
69static struct macb_platform_data __initdata macb_data = {
70 .phy_irq_pin = AT91_PIN_PA28,
71 .is_rmii = 1,
72};
73
74/*
75 * LEDs and GPOs
76 */
77static struct gpio_led gpio_leds[] = {
78 {
79 .name = "gpo:spi1reset",
80 .gpio = AT91_PIN_PC1,
81 .active_low = 0,
82 .default_trigger = "none",
83 .default_state = LEDS_GPIO_DEFSTATE_OFF,
84 },
85 {
86 .name = "gpo:trig_net_out",
87 .gpio = AT91_PIN_PB20,
88 .active_low = 0,
89 .default_trigger = "none",
90 .default_state = LEDS_GPIO_DEFSTATE_OFF,
91 },
92 {
93 .name = "gpo:trig_net_dir",
94 .gpio = AT91_PIN_PB19,
95 .active_low = 0,
96 .default_trigger = "none",
97 .default_state = LEDS_GPIO_DEFSTATE_OFF,
98 },
99 {
100 .name = "gpo:charge_dis",
101 .gpio = AT91_PIN_PC2,
102 .active_low = 0,
103 .default_trigger = "none",
104 .default_state = LEDS_GPIO_DEFSTATE_OFF,
105 },
106 {
107 .name = "led:event",
108 .gpio = AT91_PIN_PB17,
109 .active_low = 1,
110 .default_trigger = "none",
111 .default_state = LEDS_GPIO_DEFSTATE_OFF,
112 },
113 {
114 .name = "led:lan",
115 .gpio = AT91_PIN_PB18,
116 .active_low = 1,
117 .default_trigger = "none",
118 .default_state = LEDS_GPIO_DEFSTATE_OFF,
119 },
120 {
121 .name = "led:error",
122 .gpio = AT91_PIN_PB16,
123 .active_low = 1,
124 .default_trigger = "none",
125 .default_state = LEDS_GPIO_DEFSTATE_ON,
126 }
127};
128
129static struct gpio_led_platform_data gpio_led_info = {
130 .leds = gpio_leds,
131 .num_leds = ARRAY_SIZE(gpio_leds),
132};
133
134static struct platform_device leds = {
135 .name = "leds-gpio",
136 .id = 0,
137 .dev = {
138 .platform_data = &gpio_led_info,
139 }
140};
141
142static void __init gsia18s_leds_init(void)
143{
144 platform_device_register(&leds);
145}
146
147/* PCF8574 0x20 GPIO - U1 on the GS_IA18-CB_V3 board */
148static struct gpio_led pcf_gpio_leds1[] = {
149 { /* bit 0 */
150 .name = "gpo:hdc_power",
151 .gpio = PCF_GPIO_HDC_POWER,
152 .active_low = 0,
153 .default_trigger = "none",
154 .default_state = LEDS_GPIO_DEFSTATE_OFF,
155 },
156 { /* bit 1 */
157 .name = "gpo:wifi_setup",
158 .gpio = PCF_GPIO_WIFI_SETUP,
159 .active_low = 1,
160 .default_trigger = "none",
161 .default_state = LEDS_GPIO_DEFSTATE_OFF,
162 },
163 { /* bit 2 */
164 .name = "gpo:wifi_enable",
165 .gpio = PCF_GPIO_WIFI_ENABLE,
166 .active_low = 1,
167 .default_trigger = "none",
168 .default_state = LEDS_GPIO_DEFSTATE_OFF,
169 },
170 { /* bit 3 */
171 .name = "gpo:wifi_reset",
172 .gpio = PCF_GPIO_WIFI_RESET,
173 .active_low = 1,
174 .default_trigger = "none",
175 .default_state = LEDS_GPIO_DEFSTATE_ON,
176 },
177 /* bit 4 used as GPI */
178 { /* bit 5 */
179 .name = "gpo:gps_setup",
180 .gpio = PCF_GPIO_GPS_SETUP,
181 .active_low = 1,
182 .default_trigger = "none",
183 .default_state = LEDS_GPIO_DEFSTATE_OFF,
184 },
185 { /* bit 6 */
186 .name = "gpo:gps_standby",
187 .gpio = PCF_GPIO_GPS_STANDBY,
188 .active_low = 0,
189 .default_trigger = "none",
190 .default_state = LEDS_GPIO_DEFSTATE_ON,
191 },
192 { /* bit 7 */
193 .name = "gpo:gps_power",
194 .gpio = PCF_GPIO_GPS_POWER,
195 .active_low = 0,
196 .default_trigger = "none",
197 .default_state = LEDS_GPIO_DEFSTATE_OFF,
198 }
199};
200
201static struct gpio_led_platform_data pcf_gpio_led_info1 = {
202 .leds = pcf_gpio_leds1,
203 .num_leds = ARRAY_SIZE(pcf_gpio_leds1),
204};
205
206static struct platform_device pcf_leds1 = {
207 .name = "leds-gpio", /* GS_IA18-CB_board */
208 .id = 1,
209 .dev = {
210 .platform_data = &pcf_gpio_led_info1,
211 }
212};
213
214/* PCF8574 0x22 GPIO - U1 on the GS_2G_OPT1-A_V0 board (Alarm) */
215static struct gpio_led pcf_gpio_leds2[] = {
216 { /* bit 0 */
217 .name = "gpo:alarm_1",
218 .gpio = PCF_GPIO_ALARM1,
219 .active_low = 1,
220 .default_trigger = "none",
221 .default_state = LEDS_GPIO_DEFSTATE_OFF,
222 },
223 { /* bit 1 */
224 .name = "gpo:alarm_2",
225 .gpio = PCF_GPIO_ALARM2,
226 .active_low = 1,
227 .default_trigger = "none",
228 .default_state = LEDS_GPIO_DEFSTATE_OFF,
229 },
230 { /* bit 2 */
231 .name = "gpo:alarm_3",
232 .gpio = PCF_GPIO_ALARM3,
233 .active_low = 1,
234 .default_trigger = "none",
235 .default_state = LEDS_GPIO_DEFSTATE_OFF,
236 },
237 { /* bit 3 */
238 .name = "gpo:alarm_4",
239 .gpio = PCF_GPIO_ALARM4,
240 .active_low = 1,
241 .default_trigger = "none",
242 .default_state = LEDS_GPIO_DEFSTATE_OFF,
243 },
244 /* bits 4, 5, 6 not used */
245 { /* bit 7 */
246 .name = "gpo:alarm_v_relay_on",
247 .gpio = PCF_GPIO_ALARM_V_RELAY_ON,
248 .active_low = 0,
249 .default_trigger = "none",
250 .default_state = LEDS_GPIO_DEFSTATE_OFF,
251 },
252};
253
254static struct gpio_led_platform_data pcf_gpio_led_info2 = {
255 .leds = pcf_gpio_leds2,
256 .num_leds = ARRAY_SIZE(pcf_gpio_leds2),
257};
258
259static struct platform_device pcf_leds2 = {
260 .name = "leds-gpio",
261 .id = 2,
262 .dev = {
263 .platform_data = &pcf_gpio_led_info2,
264 }
265};
266
267/* PCF8574 0x24 GPIO U1 on the GS_2G-OPT23-A_V0 board (Modem) */
268static struct gpio_led pcf_gpio_leds3[] = {
269 { /* bit 0 */
270 .name = "gpo:modem_power",
271 .gpio = PCF_GPIO_MODEM_POWER,
272 .active_low = 1,
273 .default_trigger = "none",
274 .default_state = LEDS_GPIO_DEFSTATE_OFF,
275 },
276 /* bits 1 and 2 not used */
277 { /* bit 3 */
278 .name = "gpo:modem_reset",
279 .gpio = PCF_GPIO_MODEM_RESET,
280 .active_low = 1,
281 .default_trigger = "none",
282 .default_state = LEDS_GPIO_DEFSTATE_ON,
283 },
284 /* bits 4, 5 and 6 not used */
285 { /* bit 7 */
286 .name = "gpo:trx_reset",
287 .gpio = PCF_GPIO_TRX_RESET,
288 .active_low = 1,
289 .default_trigger = "none",
290 .default_state = LEDS_GPIO_DEFSTATE_ON,
291 }
292};
293
294static struct gpio_led_platform_data pcf_gpio_led_info3 = {
295 .leds = pcf_gpio_leds3,
296 .num_leds = ARRAY_SIZE(pcf_gpio_leds3),
297};
298
299static struct platform_device pcf_leds3 = {
300 .name = "leds-gpio",
301 .id = 3,
302 .dev = {
303 .platform_data = &pcf_gpio_led_info3,
304 }
305};
306
307static void __init gsia18s_pcf_leds_init(void)
308{
309 platform_device_register(&pcf_leds1);
310 platform_device_register(&pcf_leds2);
311 platform_device_register(&pcf_leds3);
312}
313
314/*
315 * SPI busses.
316 */
317static struct spi_board_info gsia18s_spi_devices[] = {
318 { /* User accessible spi0, cs0 used for communication with MSP RTC */
319 .modalias = "spidev",
320 .bus_num = 0,
321 .chip_select = 0,
322 .max_speed_hz = 580000,
323 .mode = SPI_MODE_1,
324 },
325 { /* User accessible spi1, cs0 used for communication with int. DSP */
326 .modalias = "spidev",
327 .bus_num = 1,
328 .chip_select = 0,
329 .max_speed_hz = 5600000,
330 .mode = SPI_MODE_0,
331 },
332 { /* User accessible spi1, cs1 used for communication with ext. DSP */
333 .modalias = "spidev",
334 .bus_num = 1,
335 .chip_select = 1,
336 .max_speed_hz = 5600000,
337 .mode = SPI_MODE_0,
338 },
339 { /* User accessible spi1, cs2 used for communication with ext. DSP */
340 .modalias = "spidev",
341 .bus_num = 1,
342 .chip_select = 2,
343 .max_speed_hz = 5600000,
344 .mode = SPI_MODE_0,
345 },
346 { /* User accessible spi1, cs3 used for communication with ext. DSP */
347 .modalias = "spidev",
348 .bus_num = 1,
349 .chip_select = 3,
350 .max_speed_hz = 5600000,
351 .mode = SPI_MODE_0,
352 }
353};
354
355/*
356 * GPI Buttons
357 */
358static struct gpio_keys_button buttons[] = {
359 {
360 .gpio = GPIO_TRIG_NET_IN,
361 .code = BTN_1,
362 .desc = "TRIG_NET_IN",
363 .type = EV_KEY,
364 .active_low = 0,
365 .wakeup = 1,
366 },
367 { /* SW80 on the GS_IA18_S-MN board*/
368 .gpio = GPIO_CARD_UNMOUNT_0,
369 .code = BTN_2,
370 .desc = "Card umount 0",
371 .type = EV_KEY,
372 .active_low = 1,
373 .wakeup = 1,
374 },
375 { /* SW79 on the GS_IA18_S-MN board*/
376 .gpio = GPIO_CARD_UNMOUNT_1,
377 .code = BTN_3,
378 .desc = "Card umount 1",
379 .type = EV_KEY,
380 .active_low = 1,
381 .wakeup = 1,
382 },
383 { /* SW280 on the GS_IA18-CB board*/
384 .gpio = GPIO_KEY_POWER,
385 .code = KEY_POWER,
386 .desc = "Power Off Button",
387 .type = EV_KEY,
388 .active_low = 0,
389 .wakeup = 1,
390 }
391};
392
393static struct gpio_keys_platform_data button_data = {
394 .buttons = buttons,
395 .nbuttons = ARRAY_SIZE(buttons),
396};
397
398static struct platform_device button_device = {
399 .name = "gpio-keys",
400 .id = -1,
401 .num_resources = 0,
402 .dev = {
403 .platform_data = &button_data,
404 }
405};
406
407static void __init gsia18s_add_device_buttons(void)
408{
409 at91_set_gpio_input(GPIO_TRIG_NET_IN, 1);
410 at91_set_deglitch(GPIO_TRIG_NET_IN, 1);
411 at91_set_gpio_input(GPIO_CARD_UNMOUNT_0, 1);
412 at91_set_deglitch(GPIO_CARD_UNMOUNT_0, 1);
413 at91_set_gpio_input(GPIO_CARD_UNMOUNT_1, 1);
414 at91_set_deglitch(GPIO_CARD_UNMOUNT_1, 1);
415 at91_set_gpio_input(GPIO_KEY_POWER, 0);
416 at91_set_deglitch(GPIO_KEY_POWER, 1);
417
418 platform_device_register(&button_device);
419}
420
421/*
422 * I2C
423 */
424static int pcf8574x_0x20_setup(struct i2c_client *client, int gpio,
425 unsigned int ngpio, void *context)
426{
427 int status;
428
429 status = gpio_request(gpio + PCF_GPIO_ETH_DETECT, "eth_det");
430 if (status < 0) {
431 pr_err("error: can't request GPIO%d\n",
432 gpio + PCF_GPIO_ETH_DETECT);
433 return status;
434 }
435 status = gpio_direction_input(gpio + PCF_GPIO_ETH_DETECT);
436 if (status < 0) {
437 pr_err("error: can't setup GPIO%d as input\n",
438 gpio + PCF_GPIO_ETH_DETECT);
439 return status;
440 }
441 status = gpio_export(gpio + PCF_GPIO_ETH_DETECT, false);
442 if (status < 0) {
443 pr_err("error: can't export GPIO%d\n",
444 gpio + PCF_GPIO_ETH_DETECT);
445 return status;
446 }
447 status = gpio_sysfs_set_active_low(gpio + PCF_GPIO_ETH_DETECT, 1);
448 if (status < 0) {
449 pr_err("error: gpio_sysfs_set active_low(GPIO%d, 1)\n",
450 gpio + PCF_GPIO_ETH_DETECT);
451 return status;
452 }
453
454 return 0;
455}
456
457static int pcf8574x_0x20_teardown(struct i2c_client *client, int gpio,
458 unsigned ngpio, void *context)
459{
460 gpio_free(gpio + PCF_GPIO_ETH_DETECT);
461 return 0;
462}
463
464static struct pcf857x_platform_data pcf20_pdata = {
465 .gpio_base = GS_IA18_S_PCF_GPIO_BASE0,
466 .n_latch = (1 << 4),
467 .setup = pcf8574x_0x20_setup,
468 .teardown = pcf8574x_0x20_teardown,
469};
470
471static struct pcf857x_platform_data pcf22_pdata = {
472 .gpio_base = GS_IA18_S_PCF_GPIO_BASE1,
473};
474
475static struct pcf857x_platform_data pcf24_pdata = {
476 .gpio_base = GS_IA18_S_PCF_GPIO_BASE2,
477};
478
479static struct i2c_board_info __initdata gsia18s_i2c_devices[] = {
480 { /* U1 on the GS_IA18-CB_V3 board */
481 I2C_BOARD_INFO("pcf8574", 0x20),
482 .platform_data = &pcf20_pdata,
483 },
484 { /* U1 on the GS_2G_OPT1-A_V0 board (Alarm) */
485 I2C_BOARD_INFO("pcf8574", 0x22),
486 .platform_data = &pcf22_pdata,
487 },
488 { /* U1 on the GS_2G-OPT23-A_V0 board (Modem) */
489 I2C_BOARD_INFO("pcf8574", 0x24),
490 .platform_data = &pcf24_pdata,
491 },
492 { /* U161 on the GS_IA18_S-MN board */
493 I2C_BOARD_INFO("24c1024", 0x50),
494 },
495 { /* U162 on the GS_IA18_S-MN board */
496 I2C_BOARD_INFO("24c01", 0x53),
497 },
498};
499
500/*
501 * Compact Flash
502 */
503static struct at91_cf_data __initdata gsia18s_cf1_data = {
504 .irq_pin = AT91_PIN_PA27,
505 .det_pin = AT91_PIN_PB30,
506 .vcc_pin = -EINVAL,
507 .rst_pin = AT91_PIN_PB31,
508 .chipselect = 5,
509 .flags = AT91_CF_TRUE_IDE,
510};
511
512/* Power Off by RTC */
513static void gsia18s_power_off(void)
514{
515 pr_notice("Power supply will be switched off automatically now or after 60 seconds without ArmDAS.\n");
516 at91_set_gpio_output(AT91_PIN_PA25, 1);
517 /* Spin to death... */
518 while (1)
519 ;
520}
521
522static int __init gsia18s_power_off_init(void)
523{
524 pm_power_off = gsia18s_power_off;
525 return 0;
526}
527
528/* ---------------------------------------------------------------------------*/
529
530static void __init gsia18s_board_init(void)
531{
532 /*
533 * USART0 on ttyS1 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI).
534 * Used for Internal Analog Modem.
535 */
536 at91_register_uart(AT91SAM9260_ID_US0, 1,
537 ATMEL_UART_CTS | ATMEL_UART_RTS |
538 ATMEL_UART_DTR | ATMEL_UART_DSR |
539 ATMEL_UART_DCD | ATMEL_UART_RI);
540 /*
541 * USART1 on ttyS2 (Rx, Tx, CTS, RTS).
542 * Used for GPS or WiFi or Data stream.
543 */
544 at91_register_uart(AT91SAM9260_ID_US1, 2,
545 ATMEL_UART_CTS | ATMEL_UART_RTS);
546 /*
547 * USART2 on ttyS3 (Rx, Tx, CTS, RTS).
548 * Used for External Modem.
549 */
550 at91_register_uart(AT91SAM9260_ID_US2, 3,
551 ATMEL_UART_CTS | ATMEL_UART_RTS);
552 /*
553 * USART3 on ttyS4 (Rx, Tx, RTS).
554 * Used for RS-485.
555 */
556 at91_register_uart(AT91SAM9260_ID_US3, 4, ATMEL_UART_RTS);
557
558 /*
559 * USART4 on ttyS5 (Rx, Tx).
560 * Used for TRX433 Radio Module.
561 */
562 at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
563 stamp9g20_board_init();
564 at91_add_device_usbh(&usbh_data);
565 at91_add_device_udc(&udc_data);
566 at91_add_device_eth(&macb_data);
567 gsia18s_leds_init();
568 gsia18s_pcf_leds_init();
569 gsia18s_add_device_buttons();
570 at91_add_device_i2c(gsia18s_i2c_devices,
571 ARRAY_SIZE(gsia18s_i2c_devices));
572 at91_add_device_cf(&gsia18s_cf1_data);
573 at91_add_device_spi(gsia18s_spi_devices,
574 ARRAY_SIZE(gsia18s_spi_devices));
575 gsia18s_power_off_init();
576}
577
578MACHINE_START(GSIA18S, "GS_IA18_S")
579 .init_time = at91_init_time,
580 .map_io = at91_map_io,
581 .handle_irq = at91_aic_handle_irq,
582 .init_early = gsia18s_init_early,
583 .init_irq = at91_init_irq_default,
584 .init_machine = gsia18s_board_init,
585MACHINE_END
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
deleted file mode 100644
index 93b1df42f639..000000000000
--- a/arch/arm/mach-at91/board-kafa.c
+++ /dev/null
@@ -1,113 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-kafa.c
3 *
4 * Copyright (C) 2006 Sperry-Sun
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/types.h>
22#include <linux/gpio.h>
23#include <linux/init.h>
24#include <linux/mm.h>
25#include <linux/module.h>
26#include <linux/platform_device.h>
27
28#include <mach/hardware.h>
29#include <asm/setup.h>
30#include <asm/mach-types.h>
31#include <asm/irq.h>
32
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35#include <asm/mach/irq.h>
36
37#include <mach/cpu.h>
38
39#include "at91_aic.h"
40#include "board.h"
41#include "generic.h"
42#include "gpio.h"
43
44
45static void __init kafa_init_early(void)
46{
47 /* Set cpu type: PQFP */
48 at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
49
50 /* Initialize processor: 18.432 MHz crystal */
51 at91_initialize(18432000);
52}
53
54static struct macb_platform_data __initdata kafa_eth_data = {
55 .phy_irq_pin = AT91_PIN_PC4,
56 .is_rmii = 0,
57};
58
59static struct at91_usbh_data __initdata kafa_usbh_data = {
60 .ports = 1,
61 .vbus_pin = {-EINVAL, -EINVAL},
62 .overcurrent_pin= {-EINVAL, -EINVAL},
63};
64
65static struct at91_udc_data __initdata kafa_udc_data = {
66 .vbus_pin = AT91_PIN_PB6,
67 .pullup_pin = AT91_PIN_PB7,
68};
69
70/*
71 * LEDs
72 */
73static struct gpio_led kafa_leds[] = {
74 { /* D1 */
75 .name = "led1",
76 .gpio = AT91_PIN_PB4,
77 .active_low = 1,
78 .default_trigger = "heartbeat",
79 },
80};
81
82static void __init kafa_board_init(void)
83{
84 /* Serial */
85 /* DBGU on ttyS0. (Rx & Tx only) */
86 at91_register_uart(0, 0, 0);
87
88 /* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */
89 at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
90 at91_add_device_serial();
91 /* Ethernet */
92 at91_add_device_eth(&kafa_eth_data);
93 /* USB Host */
94 at91_add_device_usbh(&kafa_usbh_data);
95 /* USB Device */
96 at91_add_device_udc(&kafa_udc_data);
97 /* I2C */
98 at91_add_device_i2c(NULL, 0);
99 /* SPI */
100 at91_add_device_spi(NULL, 0);
101 /* LEDs */
102 at91_gpio_leds(kafa_leds, ARRAY_SIZE(kafa_leds));
103}
104
105MACHINE_START(KAFA, "Sperry-Sun KAFA")
106 /* Maintainer: Sergei Sharonov */
107 .init_time = at91rm9200_timer_init,
108 .map_io = at91_map_io,
109 .handle_irq = at91_aic_handle_irq,
110 .init_early = kafa_init_early,
111 .init_irq = at91_init_irq_default,
112 .init_machine = kafa_board_init,
113MACHINE_END
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
deleted file mode 100644
index d58d36225e08..000000000000
--- a/arch/arm/mach-at91/board-kb9202.c
+++ /dev/null
@@ -1,159 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-kb9202.c
3 *
4 * Copyright (c) 2005 kb_admin
5 * KwikByte, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/types.h>
23#include <linux/gpio.h>
24#include <linux/init.h>
25#include <linux/mm.h>
26#include <linux/module.h>
27#include <linux/platform_device.h>
28
29#include <mach/hardware.h>
30#include <asm/setup.h>
31#include <asm/mach-types.h>
32#include <asm/irq.h>
33
34#include <asm/mach/arch.h>
35#include <asm/mach/map.h>
36#include <asm/mach/irq.h>
37
38#include <mach/cpu.h>
39#include <mach/at91rm9200_mc.h>
40#include <mach/at91_ramc.h>
41
42#include "at91_aic.h"
43#include "board.h"
44#include "generic.h"
45#include "gpio.h"
46
47
48static void __init kb9202_init_early(void)
49{
50 /* Set cpu type: PQFP */
51 at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
52
53 /* Initialize processor: 10 MHz crystal */
54 at91_initialize(10000000);
55}
56
57static struct macb_platform_data __initdata kb9202_eth_data = {
58 .phy_irq_pin = AT91_PIN_PB29,
59 .is_rmii = 0,
60};
61
62static struct at91_usbh_data __initdata kb9202_usbh_data = {
63 .ports = 1,
64 .vbus_pin = {-EINVAL, -EINVAL},
65 .overcurrent_pin= {-EINVAL, -EINVAL},
66};
67
68static struct at91_udc_data __initdata kb9202_udc_data = {
69 .vbus_pin = AT91_PIN_PB24,
70 .pullup_pin = AT91_PIN_PB22,
71};
72
73static struct mci_platform_data __initdata kb9202_mci0_data = {
74 .slot[0] = {
75 .bus_width = 4,
76 .detect_pin = AT91_PIN_PB2,
77 .wp_pin = -EINVAL,
78 },
79};
80
81static struct mtd_partition __initdata kb9202_nand_partition[] = {
82 {
83 .name = "nand_fs",
84 .offset = 0,
85 .size = MTDPART_SIZ_FULL,
86 },
87};
88
89static struct atmel_nand_data __initdata kb9202_nand_data = {
90 .ale = 22,
91 .cle = 21,
92 .det_pin = -EINVAL,
93 .rdy_pin = AT91_PIN_PC29,
94 .enable_pin = AT91_PIN_PC28,
95 .ecc_mode = NAND_ECC_SOFT,
96 .parts = kb9202_nand_partition,
97 .num_parts = ARRAY_SIZE(kb9202_nand_partition),
98};
99
100/*
101 * LEDs
102 */
103static struct gpio_led kb9202_leds[] = {
104 { /* D1 */
105 .name = "led1",
106 .gpio = AT91_PIN_PC19,
107 .active_low = 1,
108 .default_trigger = "heartbeat",
109 },
110 { /* D2 */
111 .name = "led2",
112 .gpio = AT91_PIN_PC18,
113 .active_low = 1,
114 .default_trigger = "timer",
115 }
116};
117
118static void __init kb9202_board_init(void)
119{
120 /* Serial */
121 /* DBGU on ttyS0. (Rx & Tx only) */
122 at91_register_uart(0, 0, 0);
123
124 /* USART0 on ttyS1 (Rx & Tx only) */
125 at91_register_uart(AT91RM9200_ID_US0, 1, 0);
126
127 /* USART1 on ttyS2 (Rx & Tx only) - IRDA (optional) */
128 at91_register_uart(AT91RM9200_ID_US1, 2, 0);
129
130 /* USART3 on ttyS3 (Rx, Tx, CTS, RTS) - RS485 (optional) */
131 at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_CTS | ATMEL_UART_RTS);
132 at91_add_device_serial();
133 /* Ethernet */
134 at91_add_device_eth(&kb9202_eth_data);
135 /* USB Host */
136 at91_add_device_usbh(&kb9202_usbh_data);
137 /* USB Device */
138 at91_add_device_udc(&kb9202_udc_data);
139 /* MMC */
140 at91_add_device_mci(0, &kb9202_mci0_data);
141 /* I2C */
142 at91_add_device_i2c(NULL, 0);
143 /* SPI */
144 at91_add_device_spi(NULL, 0);
145 /* NAND */
146 at91_add_device_nand(&kb9202_nand_data);
147 /* LEDs */
148 at91_gpio_leds(kb9202_leds, ARRAY_SIZE(kb9202_leds));
149}
150
151MACHINE_START(KB9200, "KB920x")
152 /* Maintainer: KwikByte, Inc. */
153 .init_time = at91rm9200_timer_init,
154 .map_io = at91_map_io,
155 .handle_irq = at91_aic_handle_irq,
156 .init_early = kb9202_init_early,
157 .init_irq = at91_init_irq_default,
158 .init_machine = kb9202_board_init,
159MACHINE_END
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
deleted file mode 100644
index 9c26b94ce448..000000000000
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ /dev/null
@@ -1,228 +0,0 @@
1/*
2 * Copyright (C) 2010 Christian Glindkamp <christian.glindkamp@taskit.de>
3 * taskit GmbH
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19/*
20 * copied and adjusted from board-stamp9g20.c
21 * by Peter Gsellmann <pgsellmann@portner-elektronik.at>
22 */
23
24#include <linux/mm.h>
25#include <linux/platform_device.h>
26#include <linux/gpio.h>
27#include <linux/w1-gpio.h>
28
29#include <asm/mach-types.h>
30#include <asm/mach/arch.h>
31
32#include <mach/at91sam9_smc.h>
33#include <mach/hardware.h>
34
35#include "at91_aic.h"
36#include "board.h"
37#include "sam9_smc.h"
38#include "generic.h"
39#include "stamp9g20.h"
40#include "gpio.h"
41
42
43static void __init pcontrol_g20_init_early(void)
44{
45 stamp9g20_init_early();
46}
47
48static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { {
49 .ncs_read_setup = 16,
50 .nrd_setup = 18,
51 .ncs_write_setup = 16,
52 .nwe_setup = 18,
53
54 .ncs_read_pulse = 63,
55 .nrd_pulse = 55,
56 .ncs_write_pulse = 63,
57 .nwe_pulse = 55,
58
59 .read_cycle = 127,
60 .write_cycle = 127,
61
62 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE
63 | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_SELECT
64 | AT91_SMC_DBW_8 | AT91_SMC_PS_4
65 | AT91_SMC_TDFMODE,
66 .tdf_cycles = 3,
67}, {
68 .ncs_read_setup = 0,
69 .nrd_setup = 0,
70 .ncs_write_setup = 0,
71 .nwe_setup = 1,
72
73 .ncs_read_pulse = 8,
74 .nrd_pulse = 8,
75 .ncs_write_pulse = 5,
76 .nwe_pulse = 4,
77
78 .read_cycle = 8,
79 .write_cycle = 7,
80
81 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE
82 | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_SELECT
83 | AT91_SMC_DBW_16 | AT91_SMC_PS_8
84 | AT91_SMC_TDFMODE,
85 .tdf_cycles = 1,
86} };
87
88static void __init add_device_pcontrol(void)
89{
90 /* configure chip-select 4 (IO compatible to 8051 X4 ) */
91 sam9_smc_configure(0, 4, &pcontrol_smc_config[0]);
92 /* configure chip-select 7 (FerroRAM 256KiBx16bit MR2A16A D4 ) */
93 sam9_smc_configure(0, 7, &pcontrol_smc_config[1]);
94}
95
96
97/*
98 * USB Host port
99 */
100static struct at91_usbh_data __initdata usbh_data = {
101 .ports = 2,
102 .vbus_pin = {-EINVAL, -EINVAL},
103 .overcurrent_pin= {-EINVAL, -EINVAL},
104};
105
106
107/*
108 * USB Device port
109 */
110static struct at91_udc_data __initdata pcontrol_g20_udc_data = {
111 .vbus_pin = AT91_PIN_PA22, /* Detect +5V bus voltage */
112 .pullup_pin = AT91_PIN_PA4, /* K-state, active low */
113};
114
115
116/*
117 * MACB Ethernet device
118 */
119static struct macb_platform_data __initdata macb_data = {
120 .phy_irq_pin = AT91_PIN_PA28,
121 .is_rmii = 1,
122};
123
124
125/*
126 * I2C devices: eeprom and phy/switch
127 */
128static struct i2c_board_info __initdata pcontrol_g20_i2c_devices[] = {
129{ /* D7 address width=2, 8KiB */
130 I2C_BOARD_INFO("24c64", 0x50)
131}, { /* D8 address width=1, 1 byte has 32 bits! */
132 I2C_BOARD_INFO("lan9303", 0x0a)
133}, };
134
135
136/*
137 * LEDs
138 */
139static struct gpio_led pcontrol_g20_leds[] = {
140 {
141 .name = "LED1", /* red H5 */
142 .gpio = AT91_PIN_PB18,
143 .active_low = 1,
144 .default_trigger = "none", /* supervisor */
145 }, {
146 .name = "LED2", /* yellow H7 */
147 .gpio = AT91_PIN_PB19,
148 .active_low = 1,
149 .default_trigger = "mmc0", /* SD-card activity */
150 }, {
151 .name = "LED3", /* green H2 */
152 .gpio = AT91_PIN_PB20,
153 .active_low = 1,
154 .default_trigger = "heartbeat", /* blinky */
155 }, {
156 .name = "LED4", /* red H3 */
157 .gpio = AT91_PIN_PC6,
158 .active_low = 1,
159 .default_trigger = "none", /* connection lost */
160 }, {
161 .name = "LED5", /* yellow H6 */
162 .gpio = AT91_PIN_PC7,
163 .active_low = 1,
164 .default_trigger = "none", /* unsent data */
165 }, {
166 .name = "LED6", /* green H1 */
167 .gpio = AT91_PIN_PC9,
168 .active_low = 1,
169 .default_trigger = "none", /* snafu */
170 }
171};
172
173
174/*
175 * SPI devices
176 */
177static struct spi_board_info pcontrol_g20_spi_devices[] = {
178 {
179 .modalias = "spidev", /* HMI port X4 */
180 .chip_select = 1,
181 .max_speed_hz = 50 * 1000 * 1000,
182 .bus_num = 0,
183 }, {
184 .modalias = "spidev", /* piggyback A2 */
185 .chip_select = 0,
186 .max_speed_hz = 50 * 1000 * 1000,
187 .bus_num = 1,
188 },
189};
190
191
192static void __init pcontrol_g20_board_init(void)
193{
194 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) piggyback A2 */
195 at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS
196 | ATMEL_UART_RTS);
197
198 /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) isolated RS485 X5 */
199 at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS
200 | ATMEL_UART_RTS);
201
202 /* USART2 on ttyS3. (Rx, Tx) 9bit-Bus Multidrop-mode X4 */
203 at91_register_uart(AT91SAM9260_ID_US4, 3, 0);
204 stamp9g20_board_init();
205 at91_add_device_usbh(&usbh_data);
206 at91_add_device_eth(&macb_data);
207 at91_add_device_i2c(pcontrol_g20_i2c_devices,
208 ARRAY_SIZE(pcontrol_g20_i2c_devices));
209 add_device_pcontrol();
210 at91_add_device_spi(pcontrol_g20_spi_devices,
211 ARRAY_SIZE(pcontrol_g20_spi_devices));
212 at91_add_device_udc(&pcontrol_g20_udc_data);
213 at91_gpio_leds(pcontrol_g20_leds,
214 ARRAY_SIZE(pcontrol_g20_leds));
215 /* piggyback A2 */
216 at91_set_gpio_output(AT91_PIN_PB31, 1);
217}
218
219
220MACHINE_START(PCONTROL_G20, "PControl G20")
221 /* Maintainer: pgsellmann@portner-elektronik.at */
222 .init_time = at91_init_time,
223 .map_io = at91_map_io,
224 .handle_irq = at91_aic_handle_irq,
225 .init_early = pcontrol_g20_init_early,
226 .init_irq = at91_init_irq_default,
227 .init_machine = pcontrol_g20_board_init,
228MACHINE_END
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
deleted file mode 100644
index 2c0f2d554d84..000000000000
--- a/arch/arm/mach-at91/board-picotux200.c
+++ /dev/null
@@ -1,129 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-picotux200.c
3 *
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2007 Kleinhenz Elektronik GmbH
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/types.h>
23#include <linux/gpio.h>
24#include <linux/init.h>
25#include <linux/mm.h>
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/spi/spi.h>
29#include <linux/mtd/physmap.h>
30
31#include <mach/hardware.h>
32#include <asm/setup.h>
33#include <asm/mach-types.h>
34#include <asm/irq.h>
35
36#include <asm/mach/arch.h>
37#include <asm/mach/map.h>
38#include <asm/mach/irq.h>
39
40#include <mach/at91rm9200_mc.h>
41#include <mach/at91_ramc.h>
42
43#include "at91_aic.h"
44#include "board.h"
45#include "generic.h"
46#include "gpio.h"
47
48
49static void __init picotux200_init_early(void)
50{
51 /* Initialize processor: 18.432 MHz crystal */
52 at91_initialize(18432000);
53}
54
55static struct macb_platform_data __initdata picotux200_eth_data = {
56 .phy_irq_pin = AT91_PIN_PC4,
57 .is_rmii = 1,
58};
59
60static struct at91_usbh_data __initdata picotux200_usbh_data = {
61 .ports = 1,
62 .vbus_pin = {-EINVAL, -EINVAL},
63 .overcurrent_pin= {-EINVAL, -EINVAL},
64};
65
66static struct mci_platform_data __initdata picotux200_mci0_data = {
67 .slot[0] = {
68 .bus_width = 4,
69 .detect_pin = AT91_PIN_PB27,
70 .wp_pin = AT91_PIN_PA17,
71 },
72};
73
74#define PICOTUX200_FLASH_BASE AT91_CHIPSELECT_0
75#define PICOTUX200_FLASH_SIZE SZ_4M
76
77static struct physmap_flash_data picotux200_flash_data = {
78 .width = 2,
79};
80
81static struct resource picotux200_flash_resource = {
82 .start = PICOTUX200_FLASH_BASE,
83 .end = PICOTUX200_FLASH_BASE + PICOTUX200_FLASH_SIZE - 1,
84 .flags = IORESOURCE_MEM,
85};
86
87static struct platform_device picotux200_flash = {
88 .name = "physmap-flash",
89 .id = 0,
90 .dev = {
91 .platform_data = &picotux200_flash_data,
92 },
93 .resource = &picotux200_flash_resource,
94 .num_resources = 1,
95};
96
97static void __init picotux200_board_init(void)
98{
99 /* Serial */
100 /* DBGU on ttyS0. (Rx & Tx only) */
101 at91_register_uart(0, 0, 0);
102
103 /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
104 at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
105 | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
106 | ATMEL_UART_RI);
107 at91_add_device_serial();
108 /* Ethernet */
109 at91_add_device_eth(&picotux200_eth_data);
110 /* USB Host */
111 at91_add_device_usbh(&picotux200_usbh_data);
112 /* I2C */
113 at91_add_device_i2c(NULL, 0);
114 /* MMC */
115 at91_set_gpio_output(AT91_PIN_PB22, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */
116 at91_add_device_mci(0, &picotux200_mci0_data);
117 /* NOR Flash */
118 platform_device_register(&picotux200_flash);
119}
120
121MACHINE_START(PICOTUX2XX, "picotux 200")
122 /* Maintainer: Kleinhenz Elektronik GmbH */
123 .init_time = at91rm9200_timer_init,
124 .map_io = at91_map_io,
125 .handle_irq = at91_aic_handle_irq,
126 .init_early = picotux200_init_early,
127 .init_irq = at91_init_irq_default,
128 .init_machine = picotux200_board_init,
129MACHINE_END
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
deleted file mode 100644
index 953cea416754..000000000000
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ /dev/null
@@ -1,196 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-rm9200ek.c
3 *
4 * Copyright (C) 2005 SAN People
5 *
6 * Epson S1D framebuffer glue code is:
7 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/types.h>
25#include <linux/gpio.h>
26#include <linux/init.h>
27#include <linux/mm.h>
28#include <linux/module.h>
29#include <linux/platform_device.h>
30#include <linux/spi/spi.h>
31#include <linux/mtd/physmap.h>
32
33#include <asm/setup.h>
34#include <asm/mach-types.h>
35#include <asm/irq.h>
36
37#include <asm/mach/arch.h>
38#include <asm/mach/map.h>
39#include <asm/mach/irq.h>
40
41#include <mach/hardware.h>
42#include <mach/at91rm9200_mc.h>
43#include <mach/at91_ramc.h>
44
45#include "at91_aic.h"
46#include "board.h"
47#include "generic.h"
48#include "gpio.h"
49
50
51static void __init ek_init_early(void)
52{
53 /* Initialize processor: 18.432 MHz crystal */
54 at91_initialize(18432000);
55}
56
57static struct macb_platform_data __initdata ek_eth_data = {
58 .phy_irq_pin = AT91_PIN_PC4,
59 .is_rmii = 1,
60};
61
62static struct at91_usbh_data __initdata ek_usbh_data = {
63 .ports = 2,
64 .vbus_pin = {-EINVAL, -EINVAL},
65 .overcurrent_pin= {-EINVAL, -EINVAL},
66};
67
68static struct at91_udc_data __initdata ek_udc_data = {
69 .vbus_pin = AT91_PIN_PD4,
70 .pullup_pin = AT91_PIN_PD5,
71};
72
73#ifndef CONFIG_MTD_AT91_DATAFLASH_CARD
74static struct mci_platform_data __initdata ek_mci0_data = {
75 .slot[0] = {
76 .bus_width = 4,
77 .detect_pin = AT91_PIN_PB27,
78 .wp_pin = AT91_PIN_PA17,
79 }
80};
81#endif
82
83static struct spi_board_info ek_spi_devices[] = {
84 { /* DataFlash chip */
85 .modalias = "mtd_dataflash",
86 .chip_select = 0,
87 .max_speed_hz = 15 * 1000 * 1000,
88 },
89#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD
90 { /* DataFlash card */
91 .modalias = "mtd_dataflash",
92 .chip_select = 3,
93 .max_speed_hz = 15 * 1000 * 1000,
94 },
95#endif
96};
97
98static struct i2c_board_info __initdata ek_i2c_devices[] = {
99 {
100 I2C_BOARD_INFO("ics1523", 0x26),
101 },
102 {
103 I2C_BOARD_INFO("dac3550", 0x4d),
104 }
105};
106
107#define EK_FLASH_BASE AT91_CHIPSELECT_0
108#define EK_FLASH_SIZE SZ_8M
109
110static struct physmap_flash_data ek_flash_data = {
111 .width = 2,
112};
113
114static struct resource ek_flash_resource = {
115 .start = EK_FLASH_BASE,
116 .end = EK_FLASH_BASE + EK_FLASH_SIZE - 1,
117 .flags = IORESOURCE_MEM,
118};
119
120static struct platform_device ek_flash = {
121 .name = "physmap-flash",
122 .id = 0,
123 .dev = {
124 .platform_data = &ek_flash_data,
125 },
126 .resource = &ek_flash_resource,
127 .num_resources = 1,
128};
129
130static struct gpio_led ek_leds[] = {
131 { /* "user led 1", DS2 */
132 .name = "green",
133 .gpio = AT91_PIN_PB0,
134 .active_low = 1,
135 .default_trigger = "mmc0",
136 },
137 { /* "user led 2", DS4 */
138 .name = "yellow",
139 .gpio = AT91_PIN_PB1,
140 .active_low = 1,
141 .default_trigger = "heartbeat",
142 },
143 { /* "user led 3", DS6 */
144 .name = "red",
145 .gpio = AT91_PIN_PB2,
146 .active_low = 1,
147 }
148};
149
150static void __init ek_board_init(void)
151{
152 /* Serial */
153 /* DBGU on ttyS0. (Rx & Tx only) */
154 at91_register_uart(0, 0, 0);
155
156 /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
157 at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
158 | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
159 | ATMEL_UART_RI);
160 at91_add_device_serial();
161 /* Ethernet */
162 at91_add_device_eth(&ek_eth_data);
163 /* USB Host */
164 at91_add_device_usbh(&ek_usbh_data);
165 /* USB Device */
166 at91_add_device_udc(&ek_udc_data);
167 at91_set_multi_drive(ek_udc_data.pullup_pin, 1); /* pullup_pin is connected to reset */
168 /* I2C */
169 at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
170 /* SPI */
171 at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
172#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD
173 /* DataFlash card */
174 at91_set_gpio_output(AT91_PIN_PB22, 0);
175#else
176 /* MMC */
177 at91_set_gpio_output(AT91_PIN_PB22, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */
178 at91_add_device_mci(0, &ek_mci0_data);
179#endif
180 /* NOR Flash */
181 platform_device_register(&ek_flash);
182 /* LEDs */
183 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
184 /* VGA */
185// ek_add_device_video();
186}
187
188MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK")
189 /* Maintainer: SAN People/Atmel */
190 .init_time = at91rm9200_timer_init,
191 .map_io = at91_map_io,
192 .handle_irq = at91_aic_handle_irq,
193 .init_early = ek_init_early,
194 .init_irq = at91_init_irq_default,
195 .init_machine = ek_board_init,
196MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
deleted file mode 100644
index c2166e3a236c..000000000000
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ /dev/null
@@ -1,230 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-sam9-l9260.c
3 *
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2006 Atmel
6 * Copyright (C) 2007 Olimex Ltd
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/types.h>
24#include <linux/gpio.h>
25#include <linux/init.h>
26#include <linux/mm.h>
27#include <linux/module.h>
28#include <linux/platform_device.h>
29#include <linux/spi/spi.h>
30
31#include <mach/hardware.h>
32#include <asm/setup.h>
33#include <asm/mach-types.h>
34#include <asm/irq.h>
35
36#include <asm/mach/arch.h>
37#include <asm/mach/map.h>
38#include <asm/mach/irq.h>
39
40#include <mach/at91sam9_smc.h>
41
42#include "at91_aic.h"
43#include "board.h"
44#include "sam9_smc.h"
45#include "generic.h"
46#include "gpio.h"
47
48
49static void __init ek_init_early(void)
50{
51 /* Initialize processor: 18.432 MHz crystal */
52 at91_initialize(18432000);
53}
54
55/*
56 * USB Host port
57 */
58static struct at91_usbh_data __initdata ek_usbh_data = {
59 .ports = 2,
60 .vbus_pin = {-EINVAL, -EINVAL},
61 .overcurrent_pin= {-EINVAL, -EINVAL},
62};
63
64/*
65 * USB Device port
66 */
67static struct at91_udc_data __initdata ek_udc_data = {
68 .vbus_pin = AT91_PIN_PC5,
69 .pullup_pin = -EINVAL, /* pull-up driven by UDC */
70};
71
72
73/*
74 * SPI devices.
75 */
76static struct spi_board_info ek_spi_devices[] = {
77#if !IS_ENABLED(CONFIG_MMC_ATMELMCI)
78 { /* DataFlash chip */
79 .modalias = "mtd_dataflash",
80 .chip_select = 1,
81 .max_speed_hz = 15 * 1000 * 1000,
82 .bus_num = 0,
83 },
84#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
85 { /* DataFlash card */
86 .modalias = "mtd_dataflash",
87 .chip_select = 0,
88 .max_speed_hz = 15 * 1000 * 1000,
89 .bus_num = 0,
90 },
91#endif
92#endif
93};
94
95
96/*
97 * MACB Ethernet device
98 */
99static struct macb_platform_data __initdata ek_macb_data = {
100 .phy_irq_pin = AT91_PIN_PA7,
101 .is_rmii = 0,
102};
103
104
105/*
106 * NAND flash
107 */
108static struct mtd_partition __initdata ek_nand_partition[] = {
109 {
110 .name = "Bootloader Area",
111 .offset = 0,
112 .size = 10 * SZ_1M,
113 },
114 {
115 .name = "User Area",
116 .offset = MTDPART_OFS_NXTBLK,
117 .size = MTDPART_SIZ_FULL,
118 },
119};
120
121static struct atmel_nand_data __initdata ek_nand_data = {
122 .ale = 21,
123 .cle = 22,
124 .det_pin = -EINVAL,
125 .rdy_pin = AT91_PIN_PC13,
126 .enable_pin = AT91_PIN_PC14,
127 .ecc_mode = NAND_ECC_SOFT,
128 .parts = ek_nand_partition,
129 .num_parts = ARRAY_SIZE(ek_nand_partition),
130};
131
132static struct sam9_smc_config __initdata ek_nand_smc_config = {
133 .ncs_read_setup = 0,
134 .nrd_setup = 1,
135 .ncs_write_setup = 0,
136 .nwe_setup = 1,
137
138 .ncs_read_pulse = 3,
139 .nrd_pulse = 3,
140 .ncs_write_pulse = 3,
141 .nwe_pulse = 3,
142
143 .read_cycle = 5,
144 .write_cycle = 5,
145
146 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
147 .tdf_cycles = 2,
148};
149
150static void __init ek_add_device_nand(void)
151{
152 /* configure chip-select 3 (NAND) */
153 sam9_smc_configure(0, 3, &ek_nand_smc_config);
154
155 at91_add_device_nand(&ek_nand_data);
156}
157
158
159/*
160 * MCI (SD/MMC)
161 */
162static struct mci_platform_data __initdata ek_mci0_data = {
163 .slot[1] = {
164 .bus_width = 4,
165 .detect_pin = AT91_PIN_PC8,
166 .wp_pin = AT91_PIN_PC4,
167 },
168};
169
170/*
171 * LEDs
172 */
173static struct gpio_led ek_leds[] = {
174 { /* D1 */
175 .name = "led1",
176 .gpio = AT91_PIN_PA9,
177 .active_low = 1,
178 .default_trigger = "heartbeat",
179 },
180 { /* D2 */
181 .name = "led2",
182 .gpio = AT91_PIN_PA6,
183 .active_low = 1,
184 .default_trigger = "timer",
185 }
186};
187
188static void __init ek_board_init(void)
189{
190 at91_register_devices();
191
192 /* Serial */
193 /* DBGU on ttyS0. (Rx & Tx only) */
194 at91_register_uart(0, 0, 0);
195
196 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
197 at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
198 | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
199 | ATMEL_UART_RI);
200
201 /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */
202 at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
203 at91_add_device_serial();
204 /* USB Host */
205 at91_add_device_usbh(&ek_usbh_data);
206 /* USB Device */
207 at91_add_device_udc(&ek_udc_data);
208 /* SPI */
209 at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
210 /* NAND */
211 ek_add_device_nand();
212 /* Ethernet */
213 at91_add_device_eth(&ek_macb_data);
214 /* MMC */
215 at91_add_device_mci(0, &ek_mci0_data);
216 /* I2C */
217 at91_add_device_i2c(NULL, 0);
218 /* LEDs */
219 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
220}
221
222MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260")
223 /* Maintainer: Olimex */
224 .init_time = at91_init_time,
225 .map_io = at91_map_io,
226 .handle_irq = at91_aic_handle_irq,
227 .init_early = ek_init_early,
228 .init_irq = at91_init_irq_default,
229 .init_machine = ek_board_init,
230MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
deleted file mode 100644
index bf8a946b4cd0..000000000000
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ /dev/null
@@ -1,354 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-sam9260ek.c
3 *
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2006 Atmel
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/types.h>
23#include <linux/gpio.h>
24#include <linux/init.h>
25#include <linux/mm.h>
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/spi/spi.h>
29#include <linux/spi/at73c213.h>
30#include <linux/clk.h>
31#include <linux/platform_data/at24.h>
32#include <linux/gpio_keys.h>
33#include <linux/input.h>
34
35#include <asm/setup.h>
36#include <asm/mach-types.h>
37#include <asm/irq.h>
38
39#include <asm/mach/arch.h>
40#include <asm/mach/map.h>
41#include <asm/mach/irq.h>
42
43#include <mach/hardware.h>
44#include <mach/at91sam9_smc.h>
45#include <mach/system_rev.h>
46
47#include "at91_aic.h"
48#include "board.h"
49#include "sam9_smc.h"
50#include "generic.h"
51#include "gpio.h"
52
53
54static void __init ek_init_early(void)
55{
56 /* Initialize processor: 18.432 MHz crystal */
57 at91_initialize(18432000);
58}
59
60/*
61 * USB Host port
62 */
63static struct at91_usbh_data __initdata ek_usbh_data = {
64 .ports = 2,
65 .vbus_pin = {-EINVAL, -EINVAL},
66 .overcurrent_pin= {-EINVAL, -EINVAL},
67};
68
69/*
70 * USB Device port
71 */
72static struct at91_udc_data __initdata ek_udc_data = {
73 .vbus_pin = AT91_PIN_PC5,
74 .pullup_pin = -EINVAL, /* pull-up driven by UDC */
75};
76
77
78/*
79 * Audio
80 */
81static struct at73c213_board_info at73c213_data = {
82 .ssc_id = 0,
83 .shortname = "AT91SAM9260-EK external DAC",
84};
85
86#if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
87static void __init at73c213_set_clk(struct at73c213_board_info *info)
88{
89 struct clk *pck0;
90 struct clk *plla;
91
92 pck0 = clk_get(NULL, "pck0");
93 plla = clk_get(NULL, "plla");
94
95 /* AT73C213 MCK Clock */
96 at91_set_B_periph(AT91_PIN_PC1, 0); /* PCK0 */
97
98 clk_set_parent(pck0, plla);
99 clk_put(plla);
100
101 info->dac_clk = pck0;
102}
103#else
104static void __init at73c213_set_clk(struct at73c213_board_info *info) {}
105#endif
106
107/*
108 * SPI devices.
109 */
110static struct spi_board_info ek_spi_devices[] = {
111#if !IS_ENABLED(CONFIG_MMC_ATMELMCI)
112 { /* DataFlash chip */
113 .modalias = "mtd_dataflash",
114 .chip_select = 1,
115 .max_speed_hz = 15 * 1000 * 1000,
116 .bus_num = 0,
117 },
118#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
119 { /* DataFlash card */
120 .modalias = "mtd_dataflash",
121 .chip_select = 0,
122 .max_speed_hz = 15 * 1000 * 1000,
123 .bus_num = 0,
124 },
125#endif
126#endif
127#if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
128 { /* AT73C213 DAC */
129 .modalias = "at73c213",
130 .chip_select = 0,
131 .max_speed_hz = 10 * 1000 * 1000,
132 .bus_num = 1,
133 .mode = SPI_MODE_1,
134 .platform_data = &at73c213_data,
135 },
136#endif
137};
138
139
140/*
141 * MACB Ethernet device
142 */
143static struct macb_platform_data __initdata ek_macb_data = {
144 .phy_irq_pin = AT91_PIN_PA7,
145 .is_rmii = 1,
146};
147
148
149/*
150 * NAND flash
151 */
152static struct mtd_partition __initdata ek_nand_partition[] = {
153 {
154 .name = "Partition 1",
155 .offset = 0,
156 .size = SZ_256K,
157 },
158 {
159 .name = "Partition 2",
160 .offset = MTDPART_OFS_NXTBLK,
161 .size = MTDPART_SIZ_FULL,
162 },
163};
164
165static struct atmel_nand_data __initdata ek_nand_data = {
166 .ale = 21,
167 .cle = 22,
168 .det_pin = -EINVAL,
169 .rdy_pin = AT91_PIN_PC13,
170 .enable_pin = AT91_PIN_PC14,
171 .ecc_mode = NAND_ECC_SOFT,
172 .on_flash_bbt = 1,
173 .parts = ek_nand_partition,
174 .num_parts = ARRAY_SIZE(ek_nand_partition),
175};
176
177static struct sam9_smc_config __initdata ek_nand_smc_config = {
178 .ncs_read_setup = 0,
179 .nrd_setup = 1,
180 .ncs_write_setup = 0,
181 .nwe_setup = 1,
182
183 .ncs_read_pulse = 3,
184 .nrd_pulse = 3,
185 .ncs_write_pulse = 3,
186 .nwe_pulse = 3,
187
188 .read_cycle = 5,
189 .write_cycle = 5,
190
191 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
192 .tdf_cycles = 2,
193};
194
195static void __init ek_add_device_nand(void)
196{
197 ek_nand_data.bus_width_16 = board_have_nand_16bit();
198 /* setup bus-width (8 or 16) */
199 if (ek_nand_data.bus_width_16)
200 ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
201 else
202 ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
203
204 /* configure chip-select 3 (NAND) */
205 sam9_smc_configure(0, 3, &ek_nand_smc_config);
206
207 at91_add_device_nand(&ek_nand_data);
208}
209
210
211/*
212 * MCI (SD/MMC)
213 */
214static struct mci_platform_data __initdata ek_mci0_data = {
215 .slot[1] = {
216 .bus_width = 4,
217 .detect_pin = -EINVAL,
218 .wp_pin = -EINVAL,
219 },
220};
221
222
223/*
224 * LEDs
225 */
226static struct gpio_led ek_leds[] = {
227 { /* "bottom" led, green, userled1 to be defined */
228 .name = "ds5",
229 .gpio = AT91_PIN_PA6,
230 .active_low = 1,
231 .default_trigger = "none",
232 },
233 { /* "power" led, yellow */
234 .name = "ds1",
235 .gpio = AT91_PIN_PA9,
236 .default_trigger = "heartbeat",
237 }
238};
239
240/*
241 * I2C devices
242 */
243static struct at24_platform_data at24c512 = {
244 .byte_len = SZ_512K / 8,
245 .page_size = 128,
246 .flags = AT24_FLAG_ADDR16,
247};
248
249static struct i2c_board_info __initdata ek_i2c_devices[] = {
250 {
251 I2C_BOARD_INFO("24c512", 0x50),
252 .platform_data = &at24c512,
253 },
254 /* more devices can be added using expansion connectors */
255};
256
257
258/*
259 * GPIO Buttons
260 */
261#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
262static struct gpio_keys_button ek_buttons[] = {
263 {
264 .gpio = AT91_PIN_PA30,
265 .code = BTN_3,
266 .desc = "Button 3",
267 .active_low = 1,
268 .wakeup = 1,
269 },
270 {
271 .gpio = AT91_PIN_PA31,
272 .code = BTN_4,
273 .desc = "Button 4",
274 .active_low = 1,
275 .wakeup = 1,
276 }
277};
278
279static struct gpio_keys_platform_data ek_button_data = {
280 .buttons = ek_buttons,
281 .nbuttons = ARRAY_SIZE(ek_buttons),
282};
283
284static struct platform_device ek_button_device = {
285 .name = "gpio-keys",
286 .id = -1,
287 .num_resources = 0,
288 .dev = {
289 .platform_data = &ek_button_data,
290 }
291};
292
293static void __init ek_add_device_buttons(void)
294{
295 at91_set_gpio_input(AT91_PIN_PA30, 1); /* btn3 */
296 at91_set_deglitch(AT91_PIN_PA30, 1);
297 at91_set_gpio_input(AT91_PIN_PA31, 1); /* btn4 */
298 at91_set_deglitch(AT91_PIN_PA31, 1);
299
300 platform_device_register(&ek_button_device);
301}
302#else
303static void __init ek_add_device_buttons(void) {}
304#endif
305
306
307static void __init ek_board_init(void)
308{
309 at91_register_devices();
310
311 /* Serial */
312 /* DBGU on ttyS0. (Rx & Tx only) */
313 at91_register_uart(0, 0, 0);
314
315 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
316 at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
317 | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
318 | ATMEL_UART_RI);
319
320 /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
321 at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
322 at91_add_device_serial();
323 /* USB Host */
324 at91_add_device_usbh(&ek_usbh_data);
325 /* USB Device */
326 at91_add_device_udc(&ek_udc_data);
327 /* SPI */
328 at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
329 /* NAND */
330 ek_add_device_nand();
331 /* Ethernet */
332 at91_add_device_eth(&ek_macb_data);
333 /* MMC */
334 at91_add_device_mci(0, &ek_mci0_data);
335 /* I2C */
336 at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
337 /* SSC (to AT73C213) */
338 at73c213_set_clk(&at73c213_data);
339 at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX);
340 /* LEDs */
341 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
342 /* Push Buttons */
343 ek_add_device_buttons();
344}
345
346MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")
347 /* Maintainer: Atmel */
348 .init_time = at91_init_time,
349 .map_io = at91_map_io,
350 .handle_irq = at91_aic_handle_irq,
351 .init_early = ek_init_early,
352 .init_irq = at91_init_irq_default,
353 .init_machine = ek_board_init,
354MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
deleted file mode 100644
index e85ada820bfb..000000000000
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ /dev/null
@@ -1,623 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-sam9261ek.c
3 *
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2006 Atmel
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/types.h>
23#include <linux/gpio.h>
24#include <linux/init.h>
25#include <linux/mm.h>
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/spi/spi.h>
29#include <linux/spi/ads7846.h>
30#include <linux/spi/at73c213.h>
31#include <linux/clk.h>
32#include <linux/dm9000.h>
33#include <linux/fb.h>
34#include <linux/gpio_keys.h>
35#include <linux/input.h>
36
37#include <video/atmel_lcdc.h>
38
39#include <asm/setup.h>
40#include <asm/mach-types.h>
41#include <asm/irq.h>
42
43#include <asm/mach/arch.h>
44#include <asm/mach/map.h>
45#include <asm/mach/irq.h>
46
47#include <mach/hardware.h>
48#include <mach/at91sam9_smc.h>
49#include <mach/system_rev.h>
50
51#include "at91_aic.h"
52#include "board.h"
53#include "sam9_smc.h"
54#include "generic.h"
55#include "gpio.h"
56
57
58static void __init ek_init_early(void)
59{
60 /* Initialize processor: 18.432 MHz crystal */
61 at91_initialize(18432000);
62}
63
64/*
65 * DM9000 ethernet device
66 */
67#if defined(CONFIG_DM9000)
68static struct resource dm9000_resource[] = {
69 [0] = {
70 .start = AT91_CHIPSELECT_2,
71 .end = AT91_CHIPSELECT_2 + 3,
72 .flags = IORESOURCE_MEM
73 },
74 [1] = {
75 .start = AT91_CHIPSELECT_2 + 0x44,
76 .end = AT91_CHIPSELECT_2 + 0xFF,
77 .flags = IORESOURCE_MEM
78 },
79 [2] = {
80 .flags = IORESOURCE_IRQ
81 | IORESOURCE_IRQ_LOWEDGE | IORESOURCE_IRQ_HIGHEDGE,
82 }
83};
84
85static struct dm9000_plat_data dm9000_platdata = {
86 .flags = DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM,
87};
88
89static struct platform_device dm9000_device = {
90 .name = "dm9000",
91 .id = 0,
92 .num_resources = ARRAY_SIZE(dm9000_resource),
93 .resource = dm9000_resource,
94 .dev = {
95 .platform_data = &dm9000_platdata,
96 }
97};
98
99/*
100 * SMC timings for the DM9000.
101 * Note: These timings were calculated for MASTER_CLOCK = 100000000 according to the DM9000 timings.
102 */
103static struct sam9_smc_config __initdata dm9000_smc_config = {
104 .ncs_read_setup = 0,
105 .nrd_setup = 2,
106 .ncs_write_setup = 0,
107 .nwe_setup = 2,
108
109 .ncs_read_pulse = 8,
110 .nrd_pulse = 4,
111 .ncs_write_pulse = 8,
112 .nwe_pulse = 4,
113
114 .read_cycle = 16,
115 .write_cycle = 16,
116
117 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16,
118 .tdf_cycles = 1,
119};
120
121static void __init ek_add_device_dm9000(void)
122{
123 struct resource *r = &dm9000_resource[2];
124
125 /* Configure chip-select 2 (DM9000) */
126 sam9_smc_configure(0, 2, &dm9000_smc_config);
127
128 /* Configure Reset signal as output */
129 at91_set_gpio_output(AT91_PIN_PC10, 0);
130
131 /* Configure Interrupt pin as input, no pull-up */
132 at91_set_gpio_input(AT91_PIN_PC11, 0);
133
134 r->start = r->end = gpio_to_irq(AT91_PIN_PC11);
135 platform_device_register(&dm9000_device);
136}
137#else
138static void __init ek_add_device_dm9000(void) {}
139#endif /* CONFIG_DM9000 */
140
141
142/*
143 * USB Host Port
144 */
145static struct at91_usbh_data __initdata ek_usbh_data = {
146 .ports = 2,
147 .vbus_pin = {-EINVAL, -EINVAL},
148 .overcurrent_pin= {-EINVAL, -EINVAL},
149};
150
151
152/*
153 * USB Device Port
154 */
155static struct at91_udc_data __initdata ek_udc_data = {
156 .vbus_pin = AT91_PIN_PB29,
157 .pullup_pin = -EINVAL, /* pull-up driven by UDC */
158};
159
160
161/*
162 * NAND flash
163 */
164static struct mtd_partition __initdata ek_nand_partition[] = {
165 {
166 .name = "Partition 1",
167 .offset = 0,
168 .size = SZ_256K,
169 },
170 {
171 .name = "Partition 2",
172 .offset = MTDPART_OFS_NXTBLK,
173 .size = MTDPART_SIZ_FULL,
174 },
175};
176
177static struct atmel_nand_data __initdata ek_nand_data = {
178 .ale = 22,
179 .cle = 21,
180 .det_pin = -EINVAL,
181 .rdy_pin = AT91_PIN_PC15,
182 .enable_pin = AT91_PIN_PC14,
183 .ecc_mode = NAND_ECC_SOFT,
184 .on_flash_bbt = 1,
185 .parts = ek_nand_partition,
186 .num_parts = ARRAY_SIZE(ek_nand_partition),
187};
188
189static struct sam9_smc_config __initdata ek_nand_smc_config = {
190 .ncs_read_setup = 0,
191 .nrd_setup = 1,
192 .ncs_write_setup = 0,
193 .nwe_setup = 1,
194
195 .ncs_read_pulse = 3,
196 .nrd_pulse = 3,
197 .ncs_write_pulse = 3,
198 .nwe_pulse = 3,
199
200 .read_cycle = 5,
201 .write_cycle = 5,
202
203 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
204 .tdf_cycles = 2,
205};
206
207static void __init ek_add_device_nand(void)
208{
209 ek_nand_data.bus_width_16 = board_have_nand_16bit();
210 /* setup bus-width (8 or 16) */
211 if (ek_nand_data.bus_width_16)
212 ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
213 else
214 ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
215
216 /* configure chip-select 3 (NAND) */
217 sam9_smc_configure(0, 3, &ek_nand_smc_config);
218
219 at91_add_device_nand(&ek_nand_data);
220}
221
222/*
223 * SPI related devices
224 */
225#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
226
227/*
228 * ADS7846 Touchscreen
229 */
230#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
231
232static int ads7843_pendown_state(void)
233{
234 return !at91_get_gpio_value(AT91_PIN_PC2); /* Touchscreen PENIRQ */
235}
236
237static struct ads7846_platform_data ads_info = {
238 .model = 7843,
239 .x_min = 150,
240 .x_max = 3830,
241 .y_min = 190,
242 .y_max = 3830,
243 .vref_delay_usecs = 100,
244 .x_plate_ohms = 450,
245 .y_plate_ohms = 250,
246 .pressure_max = 15000,
247 .debounce_max = 1,
248 .debounce_rep = 0,
249 .debounce_tol = (~0),
250 .get_pendown_state = ads7843_pendown_state,
251};
252
253static void __init ek_add_device_ts(void)
254{
255 at91_set_B_periph(AT91_PIN_PC2, 1); /* External IRQ0, with pullup */
256 at91_set_gpio_input(AT91_PIN_PA11, 1); /* Touchscreen BUSY signal */
257}
258#else
259static void __init ek_add_device_ts(void) {}
260#endif
261
262/*
263 * Audio
264 */
265static struct at73c213_board_info at73c213_data = {
266 .ssc_id = 1,
267 .shortname = "AT91SAM9261/9G10-EK external DAC",
268};
269
270#if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
271static void __init at73c213_set_clk(struct at73c213_board_info *info)
272{
273 struct clk *pck2;
274 struct clk *plla;
275
276 pck2 = clk_get(NULL, "pck2");
277 plla = clk_get(NULL, "plla");
278
279 /* AT73C213 MCK Clock */
280 at91_set_B_periph(AT91_PIN_PB31, 0); /* PCK2 */
281
282 clk_set_parent(pck2, plla);
283 clk_put(plla);
284
285 info->dac_clk = pck2;
286}
287#else
288static void __init at73c213_set_clk(struct at73c213_board_info *info) {}
289#endif
290
291/*
292 * SPI devices
293 */
294static struct spi_board_info ek_spi_devices[] = {
295 { /* DataFlash chip */
296 .modalias = "mtd_dataflash",
297 .chip_select = 0,
298 .max_speed_hz = 15 * 1000 * 1000,
299 .bus_num = 0,
300 },
301#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
302 {
303 .modalias = "ads7846",
304 .chip_select = 2,
305 .max_speed_hz = 125000 * 26, /* (max sample rate @ 3V) * (cmd + data + overhead) */
306 .bus_num = 0,
307 .platform_data = &ads_info,
308 .irq = NR_IRQS_LEGACY + AT91SAM9261_ID_IRQ0,
309 .controller_data = (void *) AT91_PIN_PA28, /* CS pin */
310 },
311#endif
312#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
313 { /* DataFlash card - jumper (J12) configurable to CS3 or CS0 */
314 .modalias = "mtd_dataflash",
315 .chip_select = 3,
316 .max_speed_hz = 15 * 1000 * 1000,
317 .bus_num = 0,
318 },
319#elif defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
320 { /* AT73C213 DAC */
321 .modalias = "at73c213",
322 .chip_select = 3,
323 .max_speed_hz = 10 * 1000 * 1000,
324 .bus_num = 0,
325 .mode = SPI_MODE_1,
326 .platform_data = &at73c213_data,
327 .controller_data = (void*) AT91_PIN_PA29, /* default for CS3 is PA6, but it must be PA29 */
328 },
329#endif
330};
331
332#else /* CONFIG_SPI_ATMEL_* */
333/* spi0 and mmc/sd share the same PIO pins: cannot be used at the same time */
334
335/*
336 * MCI (SD/MMC)
337 * det_pin, wp_pin and vcc_pin are not connected
338 */
339static struct mci_platform_data __initdata mci0_data = {
340 .slot[0] = {
341 .bus_width = 4,
342 .detect_pin = -EINVAL,
343 .wp_pin = -EINVAL,
344 },
345};
346
347#endif /* CONFIG_SPI_ATMEL_* */
348
349
350/*
351 * LCD Controller
352 */
353#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
354
355#if defined(CONFIG_FB_ATMEL_STN)
356
357/* STN */
358static struct fb_videomode at91_stn_modes[] = {
359 {
360 .name = "SP06Q002 @ 75",
361 .refresh = 75,
362 .xres = 320, .yres = 240,
363 .pixclock = KHZ2PICOS(1440),
364
365 .left_margin = 1, .right_margin = 1,
366 .upper_margin = 0, .lower_margin = 0,
367 .hsync_len = 1, .vsync_len = 1,
368
369 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
370 .vmode = FB_VMODE_NONINTERLACED,
371 },
372};
373
374static struct fb_monspecs at91fb_default_stn_monspecs = {
375 .manufacturer = "HIT",
376 .monitor = "SP06Q002",
377
378 .modedb = at91_stn_modes,
379 .modedb_len = ARRAY_SIZE(at91_stn_modes),
380 .hfmin = 15000,
381 .hfmax = 64000,
382 .vfmin = 50,
383 .vfmax = 150,
384};
385
386#define AT91SAM9261_DEFAULT_STN_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
387 | ATMEL_LCDC_DISTYPE_STNMONO \
388 | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE \
389 | ATMEL_LCDC_IFWIDTH_4 \
390 | ATMEL_LCDC_SCANMOD_SINGLE)
391
392static void at91_lcdc_stn_power_control(struct atmel_lcdfb_pdata *pdata, int on)
393{
394 /* backlight */
395 if (on) { /* power up */
396 at91_set_gpio_value(AT91_PIN_PC14, 0);
397 at91_set_gpio_value(AT91_PIN_PC15, 0);
398 } else { /* power down */
399 at91_set_gpio_value(AT91_PIN_PC14, 1);
400 at91_set_gpio_value(AT91_PIN_PC15, 1);
401 }
402}
403
404static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = {
405 .default_bpp = 1,
406 .default_dmacon = ATMEL_LCDC_DMAEN,
407 .default_lcdcon2 = AT91SAM9261_DEFAULT_STN_LCDCON2,
408 .default_monspecs = &at91fb_default_stn_monspecs,
409 .atmel_lcdfb_power_control = at91_lcdc_stn_power_control,
410 .guard_time = 1,
411};
412
413#else
414
415/* TFT */
416static struct fb_videomode at91_tft_vga_modes[] = {
417 {
418 .name = "TX09D50VM1CCA @ 60",
419 .refresh = 60,
420 .xres = 240, .yres = 320,
421 .pixclock = KHZ2PICOS(4965),
422
423 .left_margin = 1, .right_margin = 33,
424 .upper_margin = 1, .lower_margin = 0,
425 .hsync_len = 5, .vsync_len = 1,
426
427 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
428 .vmode = FB_VMODE_NONINTERLACED,
429 },
430};
431
432static struct fb_monspecs at91fb_default_tft_monspecs = {
433 .manufacturer = "HIT",
434 .monitor = "TX09D50VM1CCA",
435
436 .modedb = at91_tft_vga_modes,
437 .modedb_len = ARRAY_SIZE(at91_tft_vga_modes),
438 .hfmin = 15000,
439 .hfmax = 64000,
440 .vfmin = 50,
441 .vfmax = 150,
442};
443
444#define AT91SAM9261_DEFAULT_TFT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
445 | ATMEL_LCDC_DISTYPE_TFT \
446 | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
447
448static void at91_lcdc_tft_power_control(struct atmel_lcdfb_pdata *pdata, int on)
449{
450 if (on)
451 at91_set_gpio_value(AT91_PIN_PA12, 0); /* power up */
452 else
453 at91_set_gpio_value(AT91_PIN_PA12, 1); /* power down */
454}
455
456static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = {
457 .lcdcon_is_backlight = true,
458 .default_bpp = 16,
459 .default_dmacon = ATMEL_LCDC_DMAEN,
460 .default_lcdcon2 = AT91SAM9261_DEFAULT_TFT_LCDCON2,
461 .default_monspecs = &at91fb_default_tft_monspecs,
462 .atmel_lcdfb_power_control = at91_lcdc_tft_power_control,
463 .guard_time = 1,
464};
465#endif
466
467#else
468static struct atmel_lcdfb_pdata __initdata ek_lcdc_data;
469#endif
470
471
472/*
473 * GPIO Buttons
474 */
475#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
476static struct gpio_keys_button ek_buttons[] = {
477 {
478 .gpio = AT91_PIN_PA27,
479 .code = BTN_0,
480 .desc = "Button 0",
481 .active_low = 1,
482 .wakeup = 1,
483 },
484 {
485 .gpio = AT91_PIN_PA26,
486 .code = BTN_1,
487 .desc = "Button 1",
488 .active_low = 1,
489 .wakeup = 1,
490 },
491 {
492 .gpio = AT91_PIN_PA25,
493 .code = BTN_2,
494 .desc = "Button 2",
495 .active_low = 1,
496 .wakeup = 1,
497 },
498 {
499 .gpio = AT91_PIN_PA24,
500 .code = BTN_3,
501 .desc = "Button 3",
502 .active_low = 1,
503 .wakeup = 1,
504 }
505};
506
507static struct gpio_keys_platform_data ek_button_data = {
508 .buttons = ek_buttons,
509 .nbuttons = ARRAY_SIZE(ek_buttons),
510};
511
512static struct platform_device ek_button_device = {
513 .name = "gpio-keys",
514 .id = -1,
515 .num_resources = 0,
516 .dev = {
517 .platform_data = &ek_button_data,
518 }
519};
520
521static void __init ek_add_device_buttons(void)
522{
523 at91_set_gpio_input(AT91_PIN_PA27, 1); /* btn0 */
524 at91_set_deglitch(AT91_PIN_PA27, 1);
525 at91_set_gpio_input(AT91_PIN_PA26, 1); /* btn1 */
526 at91_set_deglitch(AT91_PIN_PA26, 1);
527 at91_set_gpio_input(AT91_PIN_PA25, 1); /* btn2 */
528 at91_set_deglitch(AT91_PIN_PA25, 1);
529 at91_set_gpio_input(AT91_PIN_PA24, 1); /* btn3 */
530 at91_set_deglitch(AT91_PIN_PA24, 1);
531
532 platform_device_register(&ek_button_device);
533}
534#else
535static void __init ek_add_device_buttons(void) {}
536#endif
537
538/*
539 * LEDs
540 */
541static struct gpio_led ek_leds[] = {
542 { /* "bottom" led, green, userled1 to be defined */
543 .name = "ds7",
544 .gpio = AT91_PIN_PA14,
545 .active_low = 1,
546 .default_trigger = "none",
547 },
548 { /* "top" led, green, userled2 to be defined */
549 .name = "ds8",
550 .gpio = AT91_PIN_PA13,
551 .active_low = 1,
552 .default_trigger = "none",
553 },
554 { /* "power" led, yellow */
555 .name = "ds1",
556 .gpio = AT91_PIN_PA23,
557 .default_trigger = "heartbeat",
558 }
559};
560
561static void __init ek_board_init(void)
562{
563 at91_register_devices();
564
565 /* Serial */
566 /* DBGU on ttyS0. (Rx & Tx only) */
567 at91_register_uart(0, 0, 0);
568 at91_add_device_serial();
569
570 if (cpu_is_at91sam9g10())
571 ek_lcdc_data.lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB;
572
573 /* USB Host */
574 at91_add_device_usbh(&ek_usbh_data);
575 /* USB Device */
576 at91_add_device_udc(&ek_udc_data);
577 /* I2C */
578 at91_add_device_i2c(NULL, 0);
579 /* NAND */
580 ek_add_device_nand();
581 /* DM9000 ethernet */
582 ek_add_device_dm9000();
583
584 /* spi0 and mmc/sd share the same PIO pins */
585#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
586 /* SPI */
587 at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
588 /* Touchscreen */
589 ek_add_device_ts();
590 /* SSC (to AT73C213) */
591 at73c213_set_clk(&at73c213_data);
592 at91_add_device_ssc(AT91SAM9261_ID_SSC1, ATMEL_SSC_TX);
593#else
594 /* MMC */
595 at91_add_device_mci(0, &mci0_data);
596#endif
597 /* LCD Controller */
598 at91_add_device_lcdc(&ek_lcdc_data);
599 /* Push Buttons */
600 ek_add_device_buttons();
601 /* LEDs */
602 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
603}
604
605MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK")
606 /* Maintainer: Atmel */
607 .init_time = at91_init_time,
608 .map_io = at91_map_io,
609 .handle_irq = at91_aic_handle_irq,
610 .init_early = ek_init_early,
611 .init_irq = at91_init_irq_default,
612 .init_machine = ek_board_init,
613MACHINE_END
614
615MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK")
616 /* Maintainer: Atmel */
617 .init_time = at91_init_time,
618 .map_io = at91_map_io,
619 .handle_irq = at91_aic_handle_irq,
620 .init_early = ek_init_early,
621 .init_irq = at91_init_irq_default,
622 .init_machine = ek_board_init,
623MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
deleted file mode 100644
index d76680f2a209..000000000000
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ /dev/null
@@ -1,493 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-sam9263ek.c
3 *
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2007 Atmel Corporation.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/types.h>
23#include <linux/gpio.h>
24#include <linux/init.h>
25#include <linux/mm.h>
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/spi/spi.h>
29#include <linux/spi/ads7846.h>
30#include <linux/platform_data/at24.h>
31#include <linux/fb.h>
32#include <linux/gpio_keys.h>
33#include <linux/input.h>
34#include <linux/leds.h>
35#include <linux/pwm.h>
36#include <linux/leds_pwm.h>
37
38#include <video/atmel_lcdc.h>
39
40#include <asm/setup.h>
41#include <asm/mach-types.h>
42#include <asm/irq.h>
43
44#include <asm/mach/arch.h>
45#include <asm/mach/map.h>
46#include <asm/mach/irq.h>
47
48#include <mach/hardware.h>
49#include <mach/at91sam9_smc.h>
50#include <mach/system_rev.h>
51
52#include "at91_aic.h"
53#include "board.h"
54#include "sam9_smc.h"
55#include "generic.h"
56#include "gpio.h"
57
58
59static void __init ek_init_early(void)
60{
61 /* Initialize processor: 16.367 MHz crystal */
62 at91_initialize(16367660);
63}
64
65/*
66 * USB Host port
67 */
68static struct at91_usbh_data __initdata ek_usbh_data = {
69 .ports = 2,
70 .vbus_pin = { AT91_PIN_PA24, AT91_PIN_PA21 },
71 .vbus_pin_active_low = {1, 1},
72 .overcurrent_pin= {-EINVAL, -EINVAL},
73};
74
75/*
76 * USB Device port
77 */
78static struct at91_udc_data __initdata ek_udc_data = {
79 .vbus_pin = AT91_PIN_PA25,
80 .pullup_pin = -EINVAL, /* pull-up driven by UDC */
81};
82
83
84/*
85 * ADS7846 Touchscreen
86 */
87#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
88static int ads7843_pendown_state(void)
89{
90 return !at91_get_gpio_value(AT91_PIN_PA15); /* Touchscreen PENIRQ */
91}
92
93static struct ads7846_platform_data ads_info = {
94 .model = 7843,
95 .x_min = 150,
96 .x_max = 3830,
97 .y_min = 190,
98 .y_max = 3830,
99 .vref_delay_usecs = 100,
100 .x_plate_ohms = 450,
101 .y_plate_ohms = 250,
102 .pressure_max = 15000,
103 .debounce_max = 1,
104 .debounce_rep = 0,
105 .debounce_tol = (~0),
106 .get_pendown_state = ads7843_pendown_state,
107};
108
109static void __init ek_add_device_ts(void)
110{
111 at91_set_B_periph(AT91_PIN_PA15, 1); /* External IRQ1, with pullup */
112 at91_set_gpio_input(AT91_PIN_PA31, 1); /* Touchscreen BUSY signal */
113}
114#else
115static void __init ek_add_device_ts(void) {}
116#endif
117
118/*
119 * SPI devices.
120 */
121static struct spi_board_info ek_spi_devices[] = {
122#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
123 { /* DataFlash card */
124 .modalias = "mtd_dataflash",
125 .chip_select = 0,
126 .max_speed_hz = 15 * 1000 * 1000,
127 .bus_num = 0,
128 },
129#endif
130#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
131 {
132 .modalias = "ads7846",
133 .chip_select = 3,
134 .max_speed_hz = 125000 * 26, /* (max sample rate @ 3V) * (cmd + data + overhead) */
135 .bus_num = 0,
136 .platform_data = &ads_info,
137 .irq = NR_IRQS_LEGACY + AT91SAM9263_ID_IRQ1,
138 },
139#endif
140};
141
142
143/*
144 * MCI (SD/MMC)
145 */
146static struct mci_platform_data __initdata mci1_data = {
147 .slot[0] = {
148 .bus_width = 4,
149 .detect_pin = AT91_PIN_PE18,
150 .wp_pin = AT91_PIN_PE19,
151 },
152};
153
154
155/*
156 * MACB Ethernet device
157 */
158static struct macb_platform_data __initdata ek_macb_data = {
159 .phy_irq_pin = AT91_PIN_PE31,
160 .is_rmii = 1,
161};
162
163
164/*
165 * NAND flash
166 */
167static struct mtd_partition __initdata ek_nand_partition[] = {
168 {
169 .name = "Partition 1",
170 .offset = 0,
171 .size = SZ_64M,
172 },
173 {
174 .name = "Partition 2",
175 .offset = MTDPART_OFS_NXTBLK,
176 .size = MTDPART_SIZ_FULL,
177 },
178};
179
180static struct atmel_nand_data __initdata ek_nand_data = {
181 .ale = 21,
182 .cle = 22,
183 .det_pin = -EINVAL,
184 .rdy_pin = AT91_PIN_PA22,
185 .enable_pin = AT91_PIN_PD15,
186 .ecc_mode = NAND_ECC_SOFT,
187 .on_flash_bbt = 1,
188 .parts = ek_nand_partition,
189 .num_parts = ARRAY_SIZE(ek_nand_partition),
190};
191
192static struct sam9_smc_config __initdata ek_nand_smc_config = {
193 .ncs_read_setup = 0,
194 .nrd_setup = 1,
195 .ncs_write_setup = 0,
196 .nwe_setup = 1,
197
198 .ncs_read_pulse = 3,
199 .nrd_pulse = 3,
200 .ncs_write_pulse = 3,
201 .nwe_pulse = 3,
202
203 .read_cycle = 5,
204 .write_cycle = 5,
205
206 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
207 .tdf_cycles = 2,
208};
209
210static void __init ek_add_device_nand(void)
211{
212 ek_nand_data.bus_width_16 = board_have_nand_16bit();
213 /* setup bus-width (8 or 16) */
214 if (ek_nand_data.bus_width_16)
215 ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
216 else
217 ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
218
219 /* configure chip-select 3 (NAND) */
220 sam9_smc_configure(0, 3, &ek_nand_smc_config);
221
222 at91_add_device_nand(&ek_nand_data);
223}
224
225
226/*
227 * I2C devices
228 */
229static struct at24_platform_data at24c512 = {
230 .byte_len = SZ_512K / 8,
231 .page_size = 128,
232 .flags = AT24_FLAG_ADDR16,
233};
234
235
236static struct i2c_board_info __initdata ek_i2c_devices[] = {
237 {
238 I2C_BOARD_INFO("24c512", 0x50),
239 .platform_data = &at24c512,
240 },
241 /* more devices can be added using expansion connectors */
242};
243
244/*
245 * LCD Controller
246 */
247#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
248static struct fb_videomode at91_tft_vga_modes[] = {
249 {
250 .name = "TX09D50VM1CCA @ 60",
251 .refresh = 60,
252 .xres = 240, .yres = 320,
253 .pixclock = KHZ2PICOS(4965),
254
255 .left_margin = 1, .right_margin = 33,
256 .upper_margin = 1, .lower_margin = 0,
257 .hsync_len = 5, .vsync_len = 1,
258
259 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
260 .vmode = FB_VMODE_NONINTERLACED,
261 },
262};
263
264static struct fb_monspecs at91fb_default_monspecs = {
265 .manufacturer = "HIT",
266 .monitor = "TX09D70VM1CCA",
267
268 .modedb = at91_tft_vga_modes,
269 .modedb_len = ARRAY_SIZE(at91_tft_vga_modes),
270 .hfmin = 15000,
271 .hfmax = 64000,
272 .vfmin = 50,
273 .vfmax = 150,
274};
275
276#define AT91SAM9263_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
277 | ATMEL_LCDC_DISTYPE_TFT \
278 | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
279
280static void at91_lcdc_power_control(struct atmel_lcdfb_pdata *pdata, int on)
281{
282 at91_set_gpio_value(AT91_PIN_PA30, on);
283}
284
285/* Driver datas */
286static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = {
287 .lcdcon_is_backlight = true,
288 .default_bpp = 16,
289 .default_dmacon = ATMEL_LCDC_DMAEN,
290 .default_lcdcon2 = AT91SAM9263_DEFAULT_LCDCON2,
291 .default_monspecs = &at91fb_default_monspecs,
292 .atmel_lcdfb_power_control = at91_lcdc_power_control,
293 .guard_time = 1,
294};
295
296#else
297static struct atmel_lcdfb_pdata __initdata ek_lcdc_data;
298#endif
299
300
301/*
302 * GPIO Buttons
303 */
304#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
305static struct gpio_keys_button ek_buttons[] = {
306 { /* BP1, "leftclic" */
307 .code = BTN_LEFT,
308 .gpio = AT91_PIN_PC5,
309 .active_low = 1,
310 .desc = "left_click",
311 .wakeup = 1,
312 },
313 { /* BP2, "rightclic" */
314 .code = BTN_RIGHT,
315 .gpio = AT91_PIN_PC4,
316 .active_low = 1,
317 .desc = "right_click",
318 .wakeup = 1,
319 }
320};
321
322static struct gpio_keys_platform_data ek_button_data = {
323 .buttons = ek_buttons,
324 .nbuttons = ARRAY_SIZE(ek_buttons),
325};
326
327static struct platform_device ek_button_device = {
328 .name = "gpio-keys",
329 .id = -1,
330 .num_resources = 0,
331 .dev = {
332 .platform_data = &ek_button_data,
333 }
334};
335
336static void __init ek_add_device_buttons(void)
337{
338 at91_set_GPIO_periph(AT91_PIN_PC5, 1); /* left button */
339 at91_set_deglitch(AT91_PIN_PC5, 1);
340 at91_set_GPIO_periph(AT91_PIN_PC4, 1); /* right button */
341 at91_set_deglitch(AT91_PIN_PC4, 1);
342
343 platform_device_register(&ek_button_device);
344}
345#else
346static void __init ek_add_device_buttons(void) {}
347#endif
348
349
350/*
351 * AC97
352 * reset_pin is not connected: NRST
353 */
354static struct ac97c_platform_data ek_ac97_data = {
355 .reset_pin = -EINVAL,
356};
357
358
359/*
360 * LEDs ... these could all be PWM-driven, for variable brightness
361 */
362static struct gpio_led ek_leds[] = {
363 { /* "right" led, green, userled2 (could be driven by pwm2) */
364 .name = "ds2",
365 .gpio = AT91_PIN_PC29,
366 .active_low = 1,
367 .default_trigger = "nand-disk",
368 },
369 { /* "power" led, yellow (could be driven by pwm0) */
370 .name = "ds3",
371 .gpio = AT91_PIN_PB7,
372 .default_trigger = "heartbeat",
373 },
374#if !IS_ENABLED(CONFIG_LEDS_PWM)
375 {
376 .name = "ds1",
377 .gpio = AT91_PIN_PB8,
378 .active_low = 1,
379 .default_trigger = "none",
380 }
381#endif
382};
383
384/*
385 * PWM Leds
386 */
387static struct pwm_lookup pwm_lookup[] = {
388 PWM_LOOKUP("at91sam9rl-pwm", 1, "leds_pwm", "ds1",
389 5000, PWM_POLARITY_INVERSED),
390};
391
392#if IS_ENABLED(CONFIG_LEDS_PWM)
393static struct led_pwm pwm_leds[] = {
394 {
395 .name = "ds1",
396 .max_brightness = 255,
397 },
398};
399
400static struct led_pwm_platform_data pwm_data = {
401 .num_leds = ARRAY_SIZE(pwm_leds),
402 .leds = pwm_leds,
403};
404
405static struct platform_device leds_pwm = {
406 .name = "leds_pwm",
407 .id = -1,
408 .dev = {
409 .platform_data = &pwm_data,
410 },
411};
412#endif
413
414
415/*
416 * CAN
417 */
418static void sam9263ek_transceiver_switch(int on)
419{
420 if (on) {
421 at91_set_gpio_output(AT91_PIN_PA18, 1); /* CANRXEN */
422 at91_set_gpio_output(AT91_PIN_PA19, 0); /* CANRS */
423 } else {
424 at91_set_gpio_output(AT91_PIN_PA18, 0); /* CANRXEN */
425 at91_set_gpio_output(AT91_PIN_PA19, 1); /* CANRS */
426 }
427}
428
429static struct at91_can_data ek_can_data = {
430 .transceiver_switch = sam9263ek_transceiver_switch,
431};
432
433static struct platform_device *devices[] __initdata = {
434#if IS_ENABLED(CONFIG_LEDS_PWM)
435 &leds_pwm,
436#endif
437};
438
439static void __init ek_board_init(void)
440{
441 at91_register_devices();
442
443 /* Serial */
444 /* DBGU on ttyS0. (Rx & Tx only) */
445 at91_register_uart(0, 0, 0);
446
447 /* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */
448 at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
449 at91_add_device_serial();
450 /* USB Host */
451 at91_add_device_usbh(&ek_usbh_data);
452 /* USB Device */
453 at91_add_device_udc(&ek_udc_data);
454 /* SPI */
455 at91_set_gpio_output(AT91_PIN_PE20, 1); /* select spi0 clock */
456 at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
457 /* Touchscreen */
458 ek_add_device_ts();
459 /* MMC */
460 at91_add_device_mci(1, &mci1_data);
461 /* Ethernet */
462 at91_add_device_eth(&ek_macb_data);
463 /* NAND */
464 ek_add_device_nand();
465 /* I2C */
466 at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
467 /* LCD Controller */
468 at91_add_device_lcdc(&ek_lcdc_data);
469 /* Push Buttons */
470 ek_add_device_buttons();
471 /* AC97 */
472 at91_add_device_ac97(&ek_ac97_data);
473 /* LEDs */
474 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
475 pwm_add_table(pwm_lookup, ARRAY_SIZE(pwm_lookup));
476#if IS_ENABLED(CONFIG_LEDS_PWM)
477 at91_add_device_pwm(1 << AT91_PWM1);
478#endif
479 /* CAN */
480 at91_add_device_can(&ek_can_data);
481 /* Other platform devices */
482 platform_add_devices(devices, ARRAY_SIZE(devices));
483}
484
485MACHINE_START(AT91SAM9263EK, "Atmel AT91SAM9263-EK")
486 /* Maintainer: Atmel */
487 .init_time = at91_init_time,
488 .map_io = at91_map_io,
489 .handle_irq = at91_aic_handle_irq,
490 .init_early = ek_init_early,
491 .init_irq = at91_init_irq_default,
492 .init_machine = ek_board_init,
493MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
deleted file mode 100644
index 49f075213451..000000000000
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ /dev/null
@@ -1,429 +0,0 @@
1/*
2 * Copyright (C) 2005 SAN People
3 * Copyright (C) 2008 Atmel
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/types.h>
21#include <linux/gpio.h>
22#include <linux/init.h>
23#include <linux/mm.h>
24#include <linux/module.h>
25#include <linux/platform_device.h>
26#include <linux/spi/spi.h>
27#include <linux/spi/at73c213.h>
28#include <linux/gpio_keys.h>
29#include <linux/input.h>
30#include <linux/clk.h>
31#include <linux/regulator/machine.h>
32#include <linux/regulator/fixed.h>
33#include <linux/regulator/consumer.h>
34
35#include <linux/platform_data/at91_adc.h>
36
37#include <mach/hardware.h>
38#include <asm/setup.h>
39#include <asm/mach-types.h>
40#include <asm/irq.h>
41
42#include <asm/mach/arch.h>
43#include <asm/mach/map.h>
44#include <asm/mach/irq.h>
45
46#include <mach/at91sam9_smc.h>
47#include <mach/system_rev.h>
48
49#include "at91_aic.h"
50#include "board.h"
51#include "sam9_smc.h"
52#include "generic.h"
53#include "gpio.h"
54
55/*
56 * board revision encoding
57 * bit 0:
58 * 0 => 1 sd/mmc slot
59 * 1 => 2 sd/mmc slots connectors (board from revision C)
60 */
61#define HAVE_2MMC (1 << 0)
62static int inline ek_have_2mmc(void)
63{
64 return machine_is_at91sam9g20ek_2mmc() || (system_rev & HAVE_2MMC);
65}
66
67
68static void __init ek_init_early(void)
69{
70 /* Initialize processor: 18.432 MHz crystal */
71 at91_initialize(18432000);
72}
73
74/*
75 * USB Host port
76 */
77static struct at91_usbh_data __initdata ek_usbh_data = {
78 .ports = 2,
79 .vbus_pin = {-EINVAL, -EINVAL},
80 .overcurrent_pin= {-EINVAL, -EINVAL},
81};
82
83/*
84 * USB Device port
85 */
86static struct at91_udc_data __initdata ek_udc_data = {
87 .vbus_pin = AT91_PIN_PC5,
88 .pullup_pin = -EINVAL, /* pull-up driven by UDC */
89};
90
91
92/*
93 * SPI devices.
94 */
95static struct spi_board_info ek_spi_devices[] = {
96#if !IS_ENABLED(CONFIG_MMC_ATMELMCI)
97 { /* DataFlash chip */
98 .modalias = "mtd_dataflash",
99 .chip_select = 1,
100 .max_speed_hz = 15 * 1000 * 1000,
101 .bus_num = 0,
102 },
103#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
104 { /* DataFlash card */
105 .modalias = "mtd_dataflash",
106 .chip_select = 0,
107 .max_speed_hz = 15 * 1000 * 1000,
108 .bus_num = 0,
109 },
110#endif
111#endif
112};
113
114
115/*
116 * MACB Ethernet device
117 */
118static struct macb_platform_data __initdata ek_macb_data = {
119 .phy_irq_pin = AT91_PIN_PA7,
120 .is_rmii = 1,
121};
122
123static void __init ek_add_device_macb(void)
124{
125 if (ek_have_2mmc())
126 ek_macb_data.phy_irq_pin = AT91_PIN_PB0;
127
128 at91_add_device_eth(&ek_macb_data);
129}
130
131/*
132 * NAND flash
133 */
134static struct mtd_partition __initdata ek_nand_partition[] = {
135 {
136 .name = "Bootstrap",
137 .offset = 0,
138 .size = 4 * SZ_1M,
139 },
140 {
141 .name = "Partition 1",
142 .offset = MTDPART_OFS_NXTBLK,
143 .size = 60 * SZ_1M,
144 },
145 {
146 .name = "Partition 2",
147 .offset = MTDPART_OFS_NXTBLK,
148 .size = MTDPART_SIZ_FULL,
149 },
150};
151
152/* det_pin is not connected */
153static struct atmel_nand_data __initdata ek_nand_data = {
154 .ale = 21,
155 .cle = 22,
156 .rdy_pin = AT91_PIN_PC13,
157 .enable_pin = AT91_PIN_PC14,
158 .det_pin = -EINVAL,
159 .ecc_mode = NAND_ECC_SOFT,
160 .on_flash_bbt = 1,
161 .parts = ek_nand_partition,
162 .num_parts = ARRAY_SIZE(ek_nand_partition),
163};
164
165static struct sam9_smc_config __initdata ek_nand_smc_config = {
166 .ncs_read_setup = 0,
167 .nrd_setup = 2,
168 .ncs_write_setup = 0,
169 .nwe_setup = 2,
170
171 .ncs_read_pulse = 4,
172 .nrd_pulse = 4,
173 .ncs_write_pulse = 4,
174 .nwe_pulse = 4,
175
176 .read_cycle = 7,
177 .write_cycle = 7,
178
179 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
180 .tdf_cycles = 3,
181};
182
183static void __init ek_add_device_nand(void)
184{
185 ek_nand_data.bus_width_16 = board_have_nand_16bit();
186 /* setup bus-width (8 or 16) */
187 if (ek_nand_data.bus_width_16)
188 ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
189 else
190 ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
191
192 /* configure chip-select 3 (NAND) */
193 sam9_smc_configure(0, 3, &ek_nand_smc_config);
194
195 at91_add_device_nand(&ek_nand_data);
196}
197
198
199/*
200 * MCI (SD/MMC)
201 * wp_pin and vcc_pin are not connected
202 */
203static struct mci_platform_data __initdata ek_mmc_data = {
204 .slot[1] = {
205 .bus_width = 4,
206 .detect_pin = AT91_PIN_PC9,
207 .wp_pin = -EINVAL,
208 },
209
210};
211
212static void __init ek_add_device_mmc(void)
213{
214 if (ek_have_2mmc()) {
215 ek_mmc_data.slot[0].bus_width = 4;
216 ek_mmc_data.slot[0].detect_pin = AT91_PIN_PC2;
217 ek_mmc_data.slot[0].wp_pin = -1;
218 }
219 at91_add_device_mci(0, &ek_mmc_data);
220}
221
222/*
223 * LEDs
224 */
225static struct gpio_led ek_leds[] = {
226 { /* "bottom" led, green, userled1 to be defined */
227 .name = "ds5",
228 .gpio = AT91_PIN_PA6,
229 .active_low = 1,
230 .default_trigger = "none",
231 },
232 { /* "power" led, yellow */
233 .name = "ds1",
234 .gpio = AT91_PIN_PA9,
235 .default_trigger = "heartbeat",
236 }
237};
238
239static void __init ek_add_device_gpio_leds(void)
240{
241 if (ek_have_2mmc()) {
242 ek_leds[0].gpio = AT91_PIN_PB8;
243 ek_leds[1].gpio = AT91_PIN_PB9;
244 }
245
246 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
247}
248
249/*
250 * GPIO Buttons
251 */
252#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
253static struct gpio_keys_button ek_buttons[] = {
254 {
255 .gpio = AT91_PIN_PA30,
256 .code = BTN_3,
257 .desc = "Button 3",
258 .active_low = 1,
259 .wakeup = 1,
260 },
261 {
262 .gpio = AT91_PIN_PA31,
263 .code = BTN_4,
264 .desc = "Button 4",
265 .active_low = 1,
266 .wakeup = 1,
267 }
268};
269
270static struct gpio_keys_platform_data ek_button_data = {
271 .buttons = ek_buttons,
272 .nbuttons = ARRAY_SIZE(ek_buttons),
273};
274
275static struct platform_device ek_button_device = {
276 .name = "gpio-keys",
277 .id = -1,
278 .num_resources = 0,
279 .dev = {
280 .platform_data = &ek_button_data,
281 }
282};
283
284static void __init ek_add_device_buttons(void)
285{
286 at91_set_gpio_input(AT91_PIN_PA30, 1); /* btn3 */
287 at91_set_deglitch(AT91_PIN_PA30, 1);
288 at91_set_gpio_input(AT91_PIN_PA31, 1); /* btn4 */
289 at91_set_deglitch(AT91_PIN_PA31, 1);
290
291 platform_device_register(&ek_button_device);
292}
293#else
294static void __init ek_add_device_buttons(void) {}
295#endif
296
297/*
298 * ADCs
299 */
300
301static struct at91_adc_data ek_adc_data = {
302 .channels_used = BIT(0) | BIT(1) | BIT(2) | BIT(3),
303 .use_external_triggers = true,
304 .vref = 3300,
305};
306
307#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
308static struct regulator_consumer_supply ek_audio_consumer_supplies[] = {
309 REGULATOR_SUPPLY("AVDD", "0-001b"),
310 REGULATOR_SUPPLY("HPVDD", "0-001b"),
311 REGULATOR_SUPPLY("DBVDD", "0-001b"),
312 REGULATOR_SUPPLY("DCVDD", "0-001b"),
313};
314
315static struct regulator_init_data ek_avdd_reg_init_data = {
316 .constraints = {
317 .name = "3V3",
318 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
319 },
320 .consumer_supplies = ek_audio_consumer_supplies,
321 .num_consumer_supplies = ARRAY_SIZE(ek_audio_consumer_supplies),
322};
323
324static struct fixed_voltage_config ek_vdd_pdata = {
325 .supply_name = "board-3V3",
326 .microvolts = 3300000,
327 .gpio = -EINVAL,
328 .enabled_at_boot = 0,
329 .init_data = &ek_avdd_reg_init_data,
330};
331static struct platform_device ek_voltage_regulator = {
332 .name = "reg-fixed-voltage",
333 .id = -1,
334 .num_resources = 0,
335 .dev = {
336 .platform_data = &ek_vdd_pdata,
337 },
338};
339static void __init ek_add_regulators(void)
340{
341 platform_device_register(&ek_voltage_regulator);
342}
343#else
344static void __init ek_add_regulators(void) {}
345#endif
346
347
348static struct i2c_board_info __initdata ek_i2c_devices[] = {
349 {
350 I2C_BOARD_INFO("24c512", 0x50)
351 },
352 {
353 I2C_BOARD_INFO("wm8731", 0x1b)
354 },
355};
356
357static struct platform_device sam9g20ek_audio_device = {
358 .name = "at91sam9g20ek-audio",
359 .id = -1,
360};
361
362static void __init ek_add_device_audio(void)
363{
364 platform_device_register(&sam9g20ek_audio_device);
365}
366
367
368static void __init ek_board_init(void)
369{
370 /* Serial */
371 /* DBGU on ttyS0. (Rx & Tx only) */
372 at91_register_uart(0, 0, 0);
373
374 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
375 at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
376 | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
377 | ATMEL_UART_RI);
378
379 /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
380 at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
381 at91_add_device_serial();
382 /* USB Host */
383 at91_add_device_usbh(&ek_usbh_data);
384 /* USB Device */
385 at91_add_device_udc(&ek_udc_data);
386 /* SPI */
387 at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
388 /* NAND */
389 ek_add_device_nand();
390 /* Ethernet */
391 ek_add_device_macb();
392 /* Regulators */
393 ek_add_regulators();
394 /* MMC */
395 ek_add_device_mmc();
396 /* I2C */
397 at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
398 /* LEDs */
399 ek_add_device_gpio_leds();
400 /* Push Buttons */
401 ek_add_device_buttons();
402 /* ADCs */
403 at91_add_device_adc(&ek_adc_data);
404 /* PCK0 provides MCLK to the WM8731 */
405 at91_set_B_periph(AT91_PIN_PC1, 0);
406 /* SSC (for WM8731) */
407 at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX);
408 ek_add_device_audio();
409}
410
411MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK")
412 /* Maintainer: Atmel */
413 .init_time = at91_init_time,
414 .map_io = at91_map_io,
415 .handle_irq = at91_aic_handle_irq,
416 .init_early = ek_init_early,
417 .init_irq = at91_init_irq_default,
418 .init_machine = ek_board_init,
419MACHINE_END
420
421MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod")
422 /* Maintainer: Atmel */
423 .init_time = at91_init_time,
424 .map_io = at91_map_io,
425 .handle_irq = at91_aic_handle_irq,
426 .init_early = ek_init_early,
427 .init_irq = at91_init_irq_default,
428 .init_machine = ek_board_init,
429MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
deleted file mode 100644
index a517c7f7af92..000000000000
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ /dev/null
@@ -1,527 +0,0 @@
1/*
2 * Board-specific setup code for the AT91SAM9M10G45 Evaluation Kit family
3 *
4 * Covers: * AT91SAM9G45-EKES board
5 * * AT91SAM9M10G45-EK board
6 *
7 * Copyright (C) 2009 Atmel Corporation.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 */
15
16#include <linux/types.h>
17#include <linux/gpio.h>
18#include <linux/init.h>
19#include <linux/mm.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/spi/spi.h>
23#include <linux/fb.h>
24#include <linux/gpio_keys.h>
25#include <linux/input.h>
26#include <linux/leds.h>
27#include <linux/atmel-mci.h>
28#include <linux/delay.h>
29#include <linux/pwm.h>
30#include <linux/leds_pwm.h>
31
32#include <linux/platform_data/at91_adc.h>
33
34#include <mach/hardware.h>
35#include <video/atmel_lcdc.h>
36#include <media/soc_camera.h>
37#include <media/atmel-isi.h>
38
39#include <asm/setup.h>
40#include <asm/mach-types.h>
41#include <asm/irq.h>
42
43#include <asm/mach/arch.h>
44#include <asm/mach/map.h>
45#include <asm/mach/irq.h>
46
47#include <mach/at91sam9_smc.h>
48#include <mach/system_rev.h>
49
50#include "at91_aic.h"
51#include "board.h"
52#include "sam9_smc.h"
53#include "generic.h"
54#include "gpio.h"
55
56
57static void __init ek_init_early(void)
58{
59 /* Initialize processor: 12.000 MHz crystal */
60 at91_initialize(12000000);
61}
62
63/*
64 * USB HS Host port (common to OHCI & EHCI)
65 */
66static struct at91_usbh_data __initdata ek_usbh_hs_data = {
67 .ports = 2,
68 .vbus_pin = {AT91_PIN_PD1, AT91_PIN_PD3},
69 .vbus_pin_active_low = {1, 1},
70 .overcurrent_pin= {-EINVAL, -EINVAL},
71};
72
73
74/*
75 * USB HS Device port
76 */
77static struct usba_platform_data __initdata ek_usba_udc_data = {
78 .vbus_pin = AT91_PIN_PB19,
79};
80
81
82/*
83 * SPI devices.
84 */
85static struct spi_board_info ek_spi_devices[] = {
86 { /* DataFlash chip */
87 .modalias = "mtd_dataflash",
88 .chip_select = 0,
89 .max_speed_hz = 15 * 1000 * 1000,
90 .bus_num = 0,
91 },
92};
93
94
95/*
96 * MCI (SD/MMC)
97 */
98static struct mci_platform_data __initdata mci0_data = {
99 .slot[0] = {
100 .bus_width = 4,
101 .detect_pin = AT91_PIN_PD10,
102 .wp_pin = -EINVAL,
103 },
104};
105
106static struct mci_platform_data __initdata mci1_data = {
107 .slot[0] = {
108 .bus_width = 4,
109 .detect_pin = AT91_PIN_PD11,
110 .wp_pin = AT91_PIN_PD29,
111 },
112};
113
114
115/*
116 * MACB Ethernet device
117 */
118static struct macb_platform_data __initdata ek_macb_data = {
119 .phy_irq_pin = AT91_PIN_PD5,
120 .is_rmii = 1,
121};
122
123
124/*
125 * NAND flash
126 */
127static struct mtd_partition __initdata ek_nand_partition[] = {
128 {
129 .name = "Partition 1",
130 .offset = 0,
131 .size = SZ_64M,
132 },
133 {
134 .name = "Partition 2",
135 .offset = MTDPART_OFS_NXTBLK,
136 .size = MTDPART_SIZ_FULL,
137 },
138};
139
140/* det_pin is not connected */
141static struct atmel_nand_data __initdata ek_nand_data = {
142 .ale = 21,
143 .cle = 22,
144 .rdy_pin = AT91_PIN_PC8,
145 .enable_pin = AT91_PIN_PC14,
146 .det_pin = -EINVAL,
147 .ecc_mode = NAND_ECC_SOFT,
148 .on_flash_bbt = 1,
149 .parts = ek_nand_partition,
150 .num_parts = ARRAY_SIZE(ek_nand_partition),
151};
152
153static struct sam9_smc_config __initdata ek_nand_smc_config = {
154 .ncs_read_setup = 0,
155 .nrd_setup = 2,
156 .ncs_write_setup = 0,
157 .nwe_setup = 2,
158
159 .ncs_read_pulse = 4,
160 .nrd_pulse = 4,
161 .ncs_write_pulse = 4,
162 .nwe_pulse = 4,
163
164 .read_cycle = 7,
165 .write_cycle = 7,
166
167 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
168 .tdf_cycles = 3,
169};
170
171static void __init ek_add_device_nand(void)
172{
173 ek_nand_data.bus_width_16 = board_have_nand_16bit();
174 /* setup bus-width (8 or 16) */
175 if (ek_nand_data.bus_width_16)
176 ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
177 else
178 ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
179
180 /* configure chip-select 3 (NAND) */
181 sam9_smc_configure(0, 3, &ek_nand_smc_config);
182
183 at91_add_device_nand(&ek_nand_data);
184}
185
186
187/*
188 * ISI
189 */
190static struct isi_platform_data __initdata isi_data = {
191 .frate = ISI_CFG1_FRATE_CAPTURE_ALL,
192 /* to use codec and preview path simultaneously */
193 .full_mode = 1,
194 .data_width_flags = ISI_DATAWIDTH_8 | ISI_DATAWIDTH_10,
195 /* ISI_MCK is provided by programmable clock or external clock */
196 .mck_hz = 25000000,
197};
198
199
200/*
201 * soc-camera OV2640
202 */
203#if defined(CONFIG_SOC_CAMERA_OV2640) || \
204 defined(CONFIG_SOC_CAMERA_OV2640_MODULE)
205static unsigned long isi_camera_query_bus_param(struct soc_camera_link *link)
206{
207 /* ISI board for ek using default 8-bits connection */
208 return SOCAM_DATAWIDTH_8;
209}
210
211static int i2c_camera_power(struct device *dev, int on)
212{
213 /* enable or disable the camera */
214 pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
215 at91_set_gpio_output(AT91_PIN_PD13, !on);
216
217 if (!on)
218 goto out;
219
220 /* If enabled, give a reset impulse */
221 at91_set_gpio_output(AT91_PIN_PD12, 0);
222 msleep(20);
223 at91_set_gpio_output(AT91_PIN_PD12, 1);
224 msleep(100);
225
226out:
227 return 0;
228}
229
230static struct i2c_board_info i2c_camera = {
231 I2C_BOARD_INFO("ov2640", 0x30),
232};
233
234static struct soc_camera_link iclink_ov2640 = {
235 .bus_id = 0,
236 .board_info = &i2c_camera,
237 .i2c_adapter_id = 0,
238 .power = i2c_camera_power,
239 .query_bus_param = isi_camera_query_bus_param,
240};
241
242static struct platform_device isi_ov2640 = {
243 .name = "soc-camera-pdrv",
244 .id = 0,
245 .dev = {
246 .platform_data = &iclink_ov2640,
247 },
248};
249#endif
250
251
252/*
253 * LCD Controller
254 */
255#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
256static struct fb_videomode at91_tft_vga_modes[] = {
257 {
258 .name = "LG",
259 .refresh = 60,
260 .xres = 480, .yres = 272,
261 .pixclock = KHZ2PICOS(9000),
262
263 .left_margin = 1, .right_margin = 1,
264 .upper_margin = 40, .lower_margin = 1,
265 .hsync_len = 45, .vsync_len = 1,
266
267 .sync = 0,
268 .vmode = FB_VMODE_NONINTERLACED,
269 },
270};
271
272static struct fb_monspecs at91fb_default_monspecs = {
273 .manufacturer = "LG",
274 .monitor = "LB043WQ1",
275
276 .modedb = at91_tft_vga_modes,
277 .modedb_len = ARRAY_SIZE(at91_tft_vga_modes),
278 .hfmin = 15000,
279 .hfmax = 17640,
280 .vfmin = 57,
281 .vfmax = 67,
282};
283
284#define AT91SAM9G45_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
285 | ATMEL_LCDC_DISTYPE_TFT \
286 | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
287
288/* Driver datas */
289static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = {
290 .lcdcon_is_backlight = true,
291 .default_bpp = 32,
292 .default_dmacon = ATMEL_LCDC_DMAEN,
293 .default_lcdcon2 = AT91SAM9G45_DEFAULT_LCDCON2,
294 .default_monspecs = &at91fb_default_monspecs,
295 .guard_time = 9,
296 .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB,
297};
298
299#else
300static struct atmel_lcdfb_pdata __initdata ek_lcdc_data;
301#endif
302
303
304/*
305 * ADCs and touchscreen
306 */
307static struct at91_adc_data ek_adc_data = {
308 .channels_used = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7),
309 .use_external_triggers = true,
310 .vref = 3300,
311 .touchscreen_type = ATMEL_ADC_TOUCHSCREEN_4WIRE,
312};
313
314/*
315 * GPIO Buttons
316 */
317#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
318static struct gpio_keys_button ek_buttons[] = {
319 { /* BP1, "leftclic" */
320 .code = BTN_LEFT,
321 .gpio = AT91_PIN_PB6,
322 .active_low = 1,
323 .desc = "left_click",
324 .wakeup = 1,
325 },
326 { /* BP2, "rightclic" */
327 .code = BTN_RIGHT,
328 .gpio = AT91_PIN_PB7,
329 .active_low = 1,
330 .desc = "right_click",
331 .wakeup = 1,
332 },
333 /* BP3, "joystick" */
334 {
335 .code = KEY_LEFT,
336 .gpio = AT91_PIN_PB14,
337 .active_low = 1,
338 .desc = "Joystick Left",
339 },
340 {
341 .code = KEY_RIGHT,
342 .gpio = AT91_PIN_PB15,
343 .active_low = 1,
344 .desc = "Joystick Right",
345 },
346 {
347 .code = KEY_UP,
348 .gpio = AT91_PIN_PB16,
349 .active_low = 1,
350 .desc = "Joystick Up",
351 },
352 {
353 .code = KEY_DOWN,
354 .gpio = AT91_PIN_PB17,
355 .active_low = 1,
356 .desc = "Joystick Down",
357 },
358 {
359 .code = KEY_ENTER,
360 .gpio = AT91_PIN_PB18,
361 .active_low = 1,
362 .desc = "Joystick Press",
363 },
364};
365
366static struct gpio_keys_platform_data ek_button_data = {
367 .buttons = ek_buttons,
368 .nbuttons = ARRAY_SIZE(ek_buttons),
369};
370
371static struct platform_device ek_button_device = {
372 .name = "gpio-keys",
373 .id = -1,
374 .num_resources = 0,
375 .dev = {
376 .platform_data = &ek_button_data,
377 }
378};
379
380static void __init ek_add_device_buttons(void)
381{
382 int i;
383
384 for (i = 0; i < ARRAY_SIZE(ek_buttons); i++) {
385 at91_set_GPIO_periph(ek_buttons[i].gpio, 1);
386 at91_set_deglitch(ek_buttons[i].gpio, 1);
387 }
388
389 platform_device_register(&ek_button_device);
390}
391#else
392static void __init ek_add_device_buttons(void) {}
393#endif
394
395
396/*
397 * AC97
398 * reset_pin is not connected: NRST
399 */
400static struct ac97c_platform_data ek_ac97_data = {
401 .reset_pin = -EINVAL,
402};
403
404
405/*
406 * LEDs ... these could all be PWM-driven, for variable brightness
407 */
408static struct gpio_led ek_leds[] = {
409 { /* "top" led, red, powerled */
410 .name = "d8",
411 .gpio = AT91_PIN_PD30,
412 .default_trigger = "heartbeat",
413 },
414 { /* "left" led, green, userled2, pwm3 */
415 .name = "d6",
416 .gpio = AT91_PIN_PD0,
417 .active_low = 1,
418 .default_trigger = "nand-disk",
419 },
420#if !IS_ENABLED(CONFIG_LEDS_PWM)
421 { /* "right" led, green, userled1, pwm1 */
422 .name = "d7",
423 .gpio = AT91_PIN_PD31,
424 .active_low = 1,
425 .default_trigger = "mmc0",
426 },
427#endif
428};
429
430
431/*
432 * PWM Leds
433 */
434static struct pwm_lookup pwm_lookup[] = {
435 PWM_LOOKUP("at91sam9rl-pwm", 1, "leds_pwm", "d7",
436 5000, PWM_POLARITY_INVERSED),
437};
438
439#if IS_ENABLED(CONFIG_LEDS_PWM)
440static struct led_pwm pwm_leds[] = {
441 { /* "right" led, green, userled1, pwm1 */
442 .name = "d7",
443 .max_brightness = 255,
444 },
445};
446
447static struct led_pwm_platform_data pwm_data = {
448 .num_leds = ARRAY_SIZE(pwm_leds),
449 .leds = pwm_leds,
450};
451
452static struct platform_device leds_pwm = {
453 .name = "leds_pwm",
454 .id = -1,
455 .dev = {
456 .platform_data = &pwm_data,
457 },
458};
459#endif
460
461static struct platform_device *devices[] __initdata = {
462#if defined(CONFIG_SOC_CAMERA_OV2640) || \
463 defined(CONFIG_SOC_CAMERA_OV2640_MODULE)
464 &isi_ov2640,
465#endif
466#if IS_ENABLED(CONFIG_LEDS_PWM)
467 &leds_pwm,
468#endif
469};
470
471static void __init ek_board_init(void)
472{
473 at91_register_devices();
474
475 /* Serial */
476 /* DGBU on ttyS0. (Rx & Tx only) */
477 at91_register_uart(0, 0, 0);
478
479 /* USART0 not connected on the -EK board */
480 /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
481 at91_register_uart(AT91SAM9G45_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
482 at91_add_device_serial();
483 /* USB HS Host */
484 at91_add_device_usbh_ohci(&ek_usbh_hs_data);
485 at91_add_device_usbh_ehci(&ek_usbh_hs_data);
486 /* USB HS Device */
487 at91_add_device_usba(&ek_usba_udc_data);
488 /* SPI */
489 at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
490 /* MMC */
491 at91_add_device_mci(0, &mci0_data);
492 at91_add_device_mci(1, &mci1_data);
493 /* Ethernet */
494 at91_add_device_eth(&ek_macb_data);
495 /* NAND */
496 ek_add_device_nand();
497 /* I2C */
498 at91_add_device_i2c(0, NULL, 0);
499 /* ISI, using programmable clock as ISI_MCK */
500 at91_add_device_isi(&isi_data, true);
501 /* LCD Controller */
502 at91_add_device_lcdc(&ek_lcdc_data);
503 /* ADC and touchscreen */
504 at91_add_device_adc(&ek_adc_data);
505 /* Push Buttons */
506 ek_add_device_buttons();
507 /* AC97 */
508 at91_add_device_ac97(&ek_ac97_data);
509 /* LEDs */
510 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
511 pwm_add_table(pwm_lookup, ARRAY_SIZE(pwm_lookup));
512#if IS_ENABLED(CONFIG_LEDS_PWM)
513 at91_add_device_pwm(1 << AT91_PWM1);
514#endif
515 /* Other platform devices */
516 platform_add_devices(devices, ARRAY_SIZE(devices));
517}
518
519MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK")
520 /* Maintainer: Atmel */
521 .init_time = at91_init_time,
522 .map_io = at91_map_io,
523 .handle_irq = at91_aic_handle_irq,
524 .init_early = ek_init_early,
525 .init_irq = at91_init_irq_default,
526 .init_machine = ek_board_init,
527MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
deleted file mode 100644
index 8bca329b0293..000000000000
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ /dev/null
@@ -1,333 +0,0 @@
1/*
2 * Copyright (C) 2005 SAN People
3 * Copyright (C) 2007 Atmel Corporation
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file COPYING in the main directory of this archive for
7 * more details.
8 */
9
10#include <linux/types.h>
11#include <linux/gpio.h>
12#include <linux/init.h>
13#include <linux/mm.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/spi/spi.h>
17#include <linux/fb.h>
18#include <linux/clk.h>
19#include <linux/input.h>
20#include <linux/gpio_keys.h>
21#include <linux/platform_data/at91_adc.h>
22
23#include <video/atmel_lcdc.h>
24
25#include <asm/setup.h>
26#include <asm/mach-types.h>
27#include <asm/irq.h>
28
29#include <asm/mach/arch.h>
30#include <asm/mach/map.h>
31#include <asm/mach/irq.h>
32
33#include <mach/hardware.h>
34#include <mach/at91sam9_smc.h>
35
36
37#include "at91_aic.h"
38#include "board.h"
39#include "sam9_smc.h"
40#include "generic.h"
41#include "gpio.h"
42
43
44static void __init ek_init_early(void)
45{
46 /* Initialize processor: 12.000 MHz crystal */
47 at91_initialize(12000000);
48}
49
50/*
51 * USB HS Device port
52 */
53static struct usba_platform_data __initdata ek_usba_udc_data = {
54 .vbus_pin = AT91_PIN_PA8,
55};
56
57
58/*
59 * MCI (SD/MMC)
60 */
61static struct mci_platform_data __initdata mci0_data = {
62 .slot[0] = {
63 .bus_width = 4,
64 .detect_pin = AT91_PIN_PA15,
65 .wp_pin = -EINVAL,
66 },
67};
68
69
70/*
71 * NAND flash
72 */
73static struct mtd_partition __initdata ek_nand_partition[] = {
74 {
75 .name = "Partition 1",
76 .offset = 0,
77 .size = SZ_256K,
78 },
79 {
80 .name = "Partition 2",
81 .offset = MTDPART_OFS_NXTBLK,
82 .size = MTDPART_SIZ_FULL,
83 },
84};
85
86static struct atmel_nand_data __initdata ek_nand_data = {
87 .ale = 21,
88 .cle = 22,
89 .det_pin = -EINVAL,
90 .rdy_pin = AT91_PIN_PD17,
91 .enable_pin = AT91_PIN_PB6,
92 .ecc_mode = NAND_ECC_SOFT,
93 .on_flash_bbt = 1,
94 .parts = ek_nand_partition,
95 .num_parts = ARRAY_SIZE(ek_nand_partition),
96};
97
98static struct sam9_smc_config __initdata ek_nand_smc_config = {
99 .ncs_read_setup = 0,
100 .nrd_setup = 1,
101 .ncs_write_setup = 0,
102 .nwe_setup = 1,
103
104 .ncs_read_pulse = 3,
105 .nrd_pulse = 3,
106 .ncs_write_pulse = 3,
107 .nwe_pulse = 3,
108
109 .read_cycle = 5,
110 .write_cycle = 5,
111
112 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
113 .tdf_cycles = 2,
114};
115
116static void __init ek_add_device_nand(void)
117{
118 /* configure chip-select 3 (NAND) */
119 sam9_smc_configure(0, 3, &ek_nand_smc_config);
120
121 at91_add_device_nand(&ek_nand_data);
122}
123
124
125/*
126 * SPI devices
127 */
128static struct spi_board_info ek_spi_devices[] = {
129 { /* DataFlash chip */
130 .modalias = "mtd_dataflash",
131 .chip_select = 0,
132 .max_speed_hz = 15 * 1000 * 1000,
133 .bus_num = 0,
134 },
135};
136
137
138/*
139 * LCD Controller
140 */
141#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
142static struct fb_videomode at91_tft_vga_modes[] = {
143 {
144 .name = "TX09D50VM1CCA @ 60",
145 .refresh = 60,
146 .xres = 240, .yres = 320,
147 .pixclock = KHZ2PICOS(4965),
148
149 .left_margin = 1, .right_margin = 33,
150 .upper_margin = 1, .lower_margin = 0,
151 .hsync_len = 5, .vsync_len = 1,
152
153 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
154 .vmode = FB_VMODE_NONINTERLACED,
155 },
156};
157
158static struct fb_monspecs at91fb_default_monspecs = {
159 .manufacturer = "HIT",
160 .monitor = "TX09D50VM1CCA",
161
162 .modedb = at91_tft_vga_modes,
163 .modedb_len = ARRAY_SIZE(at91_tft_vga_modes),
164 .hfmin = 15000,
165 .hfmax = 64000,
166 .vfmin = 50,
167 .vfmax = 150,
168};
169
170#define AT91SAM9RL_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
171 | ATMEL_LCDC_DISTYPE_TFT \
172 | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
173
174static void at91_lcdc_power_control(struct atmel_lcdfb_pdata *pdata, int on)
175{
176 if (on)
177 at91_set_gpio_value(AT91_PIN_PC1, 0); /* power up */
178 else
179 at91_set_gpio_value(AT91_PIN_PC1, 1); /* power down */
180}
181
182/* Driver datas */
183static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = {
184 .lcdcon_is_backlight = true,
185 .default_bpp = 16,
186 .default_dmacon = ATMEL_LCDC_DMAEN,
187 .default_lcdcon2 = AT91SAM9RL_DEFAULT_LCDCON2,
188 .default_monspecs = &at91fb_default_monspecs,
189 .atmel_lcdfb_power_control = at91_lcdc_power_control,
190 .guard_time = 1,
191 .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB,
192};
193
194#else
195static struct atmel_lcdfb_pdata __initdata ek_lcdc_data;
196#endif
197
198
199/*
200 * AC97
201 * reset_pin is not connected: NRST
202 */
203static struct ac97c_platform_data ek_ac97_data = {
204 .reset_pin = -EINVAL,
205};
206
207
208/*
209 * LEDs
210 */
211static struct gpio_led ek_leds[] = {
212 { /* "bottom" led, green, userled1 to be defined */
213 .name = "ds1",
214 .gpio = AT91_PIN_PD15,
215 .active_low = 1,
216 .default_trigger = "none",
217 },
218 { /* "bottom" led, green, userled2 to be defined */
219 .name = "ds2",
220 .gpio = AT91_PIN_PD16,
221 .active_low = 1,
222 .default_trigger = "none",
223 },
224 { /* "power" led, yellow */
225 .name = "ds3",
226 .gpio = AT91_PIN_PD14,
227 .default_trigger = "heartbeat",
228 }
229};
230
231
232/*
233 * ADC + Touchscreen
234 */
235static struct at91_adc_data ek_adc_data = {
236 .channels_used = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5),
237 .use_external_triggers = true,
238 .vref = 3300,
239 .touchscreen_type = ATMEL_ADC_TOUCHSCREEN_4WIRE,
240};
241
242
243/*
244 * GPIO Buttons
245 */
246#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
247static struct gpio_keys_button ek_buttons[] = {
248 {
249 .gpio = AT91_PIN_PB0,
250 .code = BTN_2,
251 .desc = "Right Click",
252 .active_low = 1,
253 .wakeup = 1,
254 },
255 {
256 .gpio = AT91_PIN_PB1,
257 .code = BTN_1,
258 .desc = "Left Click",
259 .active_low = 1,
260 .wakeup = 1,
261 }
262};
263
264static struct gpio_keys_platform_data ek_button_data = {
265 .buttons = ek_buttons,
266 .nbuttons = ARRAY_SIZE(ek_buttons),
267};
268
269static struct platform_device ek_button_device = {
270 .name = "gpio-keys",
271 .id = -1,
272 .num_resources = 0,
273 .dev = {
274 .platform_data = &ek_button_data,
275 }
276};
277
278static void __init ek_add_device_buttons(void)
279{
280 at91_set_gpio_input(AT91_PIN_PB1, 1); /* btn1 */
281 at91_set_deglitch(AT91_PIN_PB1, 1);
282 at91_set_gpio_input(AT91_PIN_PB0, 1); /* btn2 */
283 at91_set_deglitch(AT91_PIN_PB0, 1);
284
285 platform_device_register(&ek_button_device);
286}
287#else
288static void __init ek_add_device_buttons(void) {}
289#endif
290
291
292static void __init ek_board_init(void)
293{
294 at91_register_devices();
295
296 /* Serial */
297 /* DBGU on ttyS0. (Rx & Tx only) */
298 at91_register_uart(0, 0, 0);
299
300 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */
301 at91_register_uart(AT91SAM9RL_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
302 at91_add_device_serial();
303 /* USB HS */
304 at91_add_device_usba(&ek_usba_udc_data);
305 /* I2C */
306 at91_add_device_i2c(NULL, 0);
307 /* NAND */
308 ek_add_device_nand();
309 /* SPI */
310 at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
311 /* MMC */
312 at91_add_device_mci(0, &mci0_data);
313 /* LCD Controller */
314 at91_add_device_lcdc(&ek_lcdc_data);
315 /* AC97 */
316 at91_add_device_ac97(&ek_ac97_data);
317 /* Touch Screen Controller + ADC */
318 at91_add_device_adc(&ek_adc_data);
319 /* LEDs */
320 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
321 /* Push Buttons */
322 ek_add_device_buttons();
323}
324
325MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK")
326 /* Maintainer: Atmel */
327 .init_time = at91_init_time,
328 .map_io = at91_map_io,
329 .handle_irq = at91_aic_handle_irq,
330 .init_early = ek_init_early,
331 .init_irq = at91_init_irq_default,
332 .init_machine = ek_board_init,
333MACHINE_END
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
deleted file mode 100644
index b4aff840a1a0..000000000000
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ /dev/null
@@ -1,191 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-snapper9260.c
3 *
4 * Copyright (C) 2010 Bluewater System Ltd
5 *
6 * Author: Andre Renaud <andre@bluewatersys.com>
7 * Author: Ryan Mallon
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#include <linux/init.h>
26#include <linux/gpio.h>
27#include <linux/platform_device.h>
28#include <linux/spi/spi.h>
29#include <linux/platform_data/pca953x.h>
30
31#include <asm/mach-types.h>
32#include <asm/mach/arch.h>
33
34#include <mach/hardware.h>
35#include <mach/at91sam9_smc.h>
36
37#include "at91_aic.h"
38#include "board.h"
39#include "sam9_smc.h"
40#include "generic.h"
41#include "gpio.h"
42
43#define SNAPPER9260_IO_EXP_GPIO(x) (NR_BUILTIN_GPIO + (x))
44
45static void __init snapper9260_init_early(void)
46{
47 at91_initialize(18432000);
48}
49
50static struct at91_usbh_data __initdata snapper9260_usbh_data = {
51 .ports = 2,
52 .vbus_pin = {-EINVAL, -EINVAL},
53 .overcurrent_pin= {-EINVAL, -EINVAL},
54};
55
56static struct at91_udc_data __initdata snapper9260_udc_data = {
57 .vbus_pin = SNAPPER9260_IO_EXP_GPIO(5),
58 .vbus_active_low = 1,
59 .vbus_polled = 1,
60 .pullup_pin = -EINVAL,
61};
62
63static struct macb_platform_data snapper9260_macb_data = {
64 .phy_irq_pin = -EINVAL,
65 .is_rmii = 1,
66};
67
68static struct mtd_partition __initdata snapper9260_nand_partitions[] = {
69 {
70 .name = "Preboot",
71 .offset = 0,
72 .size = SZ_128K,
73 },
74 {
75 .name = "Bootloader",
76 .offset = MTDPART_OFS_APPEND,
77 .size = SZ_256K,
78 },
79 {
80 .name = "Environment",
81 .offset = MTDPART_OFS_APPEND,
82 .size = SZ_128K,
83 },
84 {
85 .name = "Kernel",
86 .offset = MTDPART_OFS_APPEND,
87 .size = SZ_4M,
88 },
89 {
90 .name = "Filesystem",
91 .offset = MTDPART_OFS_APPEND,
92 .size = MTDPART_SIZ_FULL,
93 },
94};
95
96static struct atmel_nand_data __initdata snapper9260_nand_data = {
97 .ale = 21,
98 .cle = 22,
99 .rdy_pin = AT91_PIN_PC13,
100 .parts = snapper9260_nand_partitions,
101 .num_parts = ARRAY_SIZE(snapper9260_nand_partitions),
102 .bus_width_16 = 0,
103 .enable_pin = -EINVAL,
104 .det_pin = -EINVAL,
105 .ecc_mode = NAND_ECC_SOFT,
106};
107
108static struct sam9_smc_config __initdata snapper9260_nand_smc_config = {
109 .ncs_read_setup = 0,
110 .nrd_setup = 0,
111 .ncs_write_setup = 0,
112 .nwe_setup = 0,
113
114 .ncs_read_pulse = 5,
115 .nrd_pulse = 2,
116 .ncs_write_pulse = 5,
117 .nwe_pulse = 2,
118
119 .read_cycle = 7,
120 .write_cycle = 7,
121
122 .mode = (AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
123 AT91_SMC_EXNWMODE_DISABLE),
124 .tdf_cycles = 1,
125};
126
127static struct pca953x_platform_data snapper9260_io_expander_data = {
128 .gpio_base = SNAPPER9260_IO_EXP_GPIO(0),
129};
130
131static struct i2c_board_info __initdata snapper9260_i2c_devices[] = {
132 {
133 /* IO expander */
134 I2C_BOARD_INFO("max7312", 0x28),
135 .platform_data = &snapper9260_io_expander_data,
136 },
137 {
138 /* Audio codec */
139 I2C_BOARD_INFO("tlv320aic23", 0x1a),
140 },
141};
142
143static struct i2c_board_info __initdata snapper9260_i2c_isl1208 = {
144 /* RTC */
145 I2C_BOARD_INFO("isl1208", 0x6f),
146};
147
148static void __init snapper9260_add_device_nand(void)
149{
150 at91_set_A_periph(AT91_PIN_PC14, 0);
151 sam9_smc_configure(0, 3, &snapper9260_nand_smc_config);
152 at91_add_device_nand(&snapper9260_nand_data);
153}
154
155static void __init snapper9260_board_init(void)
156{
157 at91_register_devices();
158
159 at91_add_device_i2c(snapper9260_i2c_devices,
160 ARRAY_SIZE(snapper9260_i2c_devices));
161
162 snapper9260_i2c_isl1208.irq = gpio_to_irq(AT91_PIN_PA31);
163 i2c_register_board_info(0, &snapper9260_i2c_isl1208, 1);
164
165 /* Debug on ttyS0 */
166 at91_register_uart(0, 0, 0);
167
168 at91_register_uart(AT91SAM9260_ID_US0, 1,
169 ATMEL_UART_CTS | ATMEL_UART_RTS);
170 at91_register_uart(AT91SAM9260_ID_US1, 2,
171 ATMEL_UART_CTS | ATMEL_UART_RTS);
172 at91_register_uart(AT91SAM9260_ID_US2, 3, 0);
173 at91_add_device_serial();
174 at91_add_device_usbh(&snapper9260_usbh_data);
175 at91_add_device_udc(&snapper9260_udc_data);
176 at91_add_device_eth(&snapper9260_macb_data);
177 at91_add_device_ssc(AT91SAM9260_ID_SSC, (ATMEL_SSC_TF | ATMEL_SSC_TK |
178 ATMEL_SSC_TD | ATMEL_SSC_RD));
179 snapper9260_add_device_nand();
180}
181
182MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module")
183 .init_time = at91_init_time,
184 .map_io = at91_map_io,
185 .handle_irq = at91_aic_handle_irq,
186 .init_early = snapper9260_init_early,
187 .init_irq = at91_init_irq_default,
188 .init_machine = snapper9260_board_init,
189MACHINE_END
190
191
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
deleted file mode 100644
index e825641a1dee..000000000000
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ /dev/null
@@ -1,294 +0,0 @@
1/*
2 * Copyright (C) 2010 Christian Glindkamp <christian.glindkamp@taskit.de>
3 * taskit GmbH
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/mm.h>
21#include <linux/platform_device.h>
22#include <linux/gpio.h>
23#include <linux/w1-gpio.h>
24
25#include <asm/mach-types.h>
26#include <asm/mach/arch.h>
27
28#include <mach/at91sam9_smc.h>
29#include <mach/hardware.h>
30
31#include "at91_aic.h"
32#include "board.h"
33#include "sam9_smc.h"
34#include "generic.h"
35#include "gpio.h"
36
37
38void __init stamp9g20_init_early(void)
39{
40 /* Initialize processor: 18.432 MHz crystal */
41 at91_initialize(18432000);
42}
43
44/*
45 * NAND flash
46 */
47static struct atmel_nand_data __initdata nand_data = {
48 .ale = 21,
49 .cle = 22,
50 .rdy_pin = AT91_PIN_PC13,
51 .enable_pin = AT91_PIN_PC14,
52 .bus_width_16 = 0,
53 .det_pin = -EINVAL,
54 .ecc_mode = NAND_ECC_SOFT,
55};
56
57static struct sam9_smc_config __initdata nand_smc_config = {
58 .ncs_read_setup = 0,
59 .nrd_setup = 2,
60 .ncs_write_setup = 0,
61 .nwe_setup = 2,
62
63 .ncs_read_pulse = 4,
64 .nrd_pulse = 4,
65 .ncs_write_pulse = 4,
66 .nwe_pulse = 4,
67
68 .read_cycle = 7,
69 .write_cycle = 7,
70
71 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
72 .tdf_cycles = 3,
73};
74
75static void __init add_device_nand(void)
76{
77 /* configure chip-select 3 (NAND) */
78 sam9_smc_configure(0, 3, &nand_smc_config);
79
80 at91_add_device_nand(&nand_data);
81}
82
83
84/*
85 * MCI (SD/MMC)
86 * det_pin, wp_pin and vcc_pin are not connected
87 */
88static struct mci_platform_data __initdata mmc_data = {
89 .slot[0] = {
90 .bus_width = 4,
91 .detect_pin = -1,
92 .wp_pin = -1,
93 },
94};
95
96
97/*
98 * USB Host port
99 */
100static struct at91_usbh_data __initdata usbh_data = {
101 .ports = 2,
102 .vbus_pin = {-EINVAL, -EINVAL},
103 .overcurrent_pin= {-EINVAL, -EINVAL},
104};
105
106
107/*
108 * USB Device port
109 */
110static struct at91_udc_data __initdata portuxg20_udc_data = {
111 .vbus_pin = AT91_PIN_PC7,
112 .pullup_pin = -EINVAL, /* pull-up driven by UDC */
113};
114
115static struct at91_udc_data __initdata stamp9g20evb_udc_data = {
116 .vbus_pin = AT91_PIN_PA22,
117 .pullup_pin = -EINVAL, /* pull-up driven by UDC */
118};
119
120
121/*
122 * MACB Ethernet device
123 */
124static struct macb_platform_data __initdata macb_data = {
125 .phy_irq_pin = AT91_PIN_PA28,
126 .is_rmii = 1,
127};
128
129
130/*
131 * LEDs
132 */
133static struct gpio_led portuxg20_leds[] = {
134 {
135 .name = "LED2",
136 .gpio = AT91_PIN_PC5,
137 .default_trigger = "none",
138 }, {
139 .name = "LED3",
140 .gpio = AT91_PIN_PC4,
141 .default_trigger = "none",
142 }, {
143 .name = "LED4",
144 .gpio = AT91_PIN_PC10,
145 .default_trigger = "heartbeat",
146 }
147};
148
149static struct gpio_led stamp9g20evb_leds[] = {
150 {
151 .name = "D8",
152 .gpio = AT91_PIN_PB18,
153 .active_low = 1,
154 .default_trigger = "none",
155 }, {
156 .name = "D9",
157 .gpio = AT91_PIN_PB19,
158 .active_low = 1,
159 .default_trigger = "none",
160 }, {
161 .name = "D10",
162 .gpio = AT91_PIN_PB20,
163 .active_low = 1,
164 .default_trigger = "heartbeat",
165 }
166};
167
168
169/*
170 * SPI devices
171 */
172static struct spi_board_info portuxg20_spi_devices[] = {
173 {
174 .modalias = "spidev",
175 .chip_select = 0,
176 .max_speed_hz = 1 * 1000 * 1000,
177 .bus_num = 0,
178 }, {
179 .modalias = "spidev",
180 .chip_select = 0,
181 .max_speed_hz = 1 * 1000 * 1000,
182 .bus_num = 1,
183 },
184};
185
186
187/*
188 * Dallas 1-Wire
189 */
190static struct w1_gpio_platform_data w1_gpio_pdata = {
191 .pin = AT91_PIN_PA29,
192 .is_open_drain = 1,
193 .ext_pullup_enable_pin = -EINVAL,
194};
195
196static struct platform_device w1_device = {
197 .name = "w1-gpio",
198 .id = -1,
199 .dev.platform_data = &w1_gpio_pdata,
200};
201
202void add_w1(void)
203{
204 at91_set_GPIO_periph(w1_gpio_pdata.pin, 1);
205 at91_set_multi_drive(w1_gpio_pdata.pin, 1);
206 platform_device_register(&w1_device);
207}
208
209
210void __init stamp9g20_board_init(void)
211{
212 /* Serial */
213 /* DGBU on ttyS0. (Rx & Tx only) */
214 at91_register_uart(0, 0, 0);
215 at91_add_device_serial();
216 /* NAND */
217 add_device_nand();
218 /* MMC */
219 at91_add_device_mci(0, &mmc_data);
220 /* W1 */
221 add_w1();
222}
223
224static void __init portuxg20_board_init(void)
225{
226 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
227 at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
228 | ATMEL_UART_DTR | ATMEL_UART_DSR
229 | ATMEL_UART_DCD | ATMEL_UART_RI);
230
231 /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */
232 at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
233
234 /* USART2 on ttyS3. (Rx, Tx, CTS, RTS) */
235 at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ATMEL_UART_RTS);
236
237 /* USART4 on ttyS5. (Rx, Tx only) */
238 at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
239
240 /* USART5 on ttyS6. (Rx, Tx only) */
241 at91_register_uart(AT91SAM9260_ID_US5, 6, 0);
242 stamp9g20_board_init();
243 /* USB Host */
244 at91_add_device_usbh(&usbh_data);
245 /* USB Device */
246 at91_add_device_udc(&portuxg20_udc_data);
247 /* Ethernet */
248 at91_add_device_eth(&macb_data);
249 /* I2C */
250 at91_add_device_i2c(NULL, 0);
251 /* SPI */
252 at91_add_device_spi(portuxg20_spi_devices, ARRAY_SIZE(portuxg20_spi_devices));
253 /* LEDs */
254 at91_gpio_leds(portuxg20_leds, ARRAY_SIZE(portuxg20_leds));
255}
256
257static void __init stamp9g20evb_board_init(void)
258{
259 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
260 at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
261 | ATMEL_UART_DTR | ATMEL_UART_DSR
262 | ATMEL_UART_DCD | ATMEL_UART_RI);
263 stamp9g20_board_init();
264 /* USB Host */
265 at91_add_device_usbh(&usbh_data);
266 /* USB Device */
267 at91_add_device_udc(&stamp9g20evb_udc_data);
268 /* Ethernet */
269 at91_add_device_eth(&macb_data);
270 /* I2C */
271 at91_add_device_i2c(NULL, 0);
272 /* LEDs */
273 at91_gpio_leds(stamp9g20evb_leds, ARRAY_SIZE(stamp9g20evb_leds));
274}
275
276MACHINE_START(PORTUXG20, "taskit PortuxG20")
277 /* Maintainer: taskit GmbH */
278 .init_time = at91_init_time,
279 .map_io = at91_map_io,
280 .handle_irq = at91_aic_handle_irq,
281 .init_early = stamp9g20_init_early,
282 .init_irq = at91_init_irq_default,
283 .init_machine = portuxg20_board_init,
284MACHINE_END
285
286MACHINE_START(STAMP9G20, "taskit Stamp9G20")
287 /* Maintainer: taskit GmbH */
288 .init_time = at91_init_time,
289 .map_io = at91_map_io,
290 .handle_irq = at91_aic_handle_irq,
291 .init_early = stamp9g20_init_early,
292 .init_irq = at91_init_irq_default,
293 .init_machine = stamp9g20evb_board_init,
294MACHINE_END
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
deleted file mode 100644
index 46fdb0c68a68..000000000000
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ /dev/null
@@ -1,597 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-yl-9200.c
3 *
4 * Adapted from various board files in arch/arm/mach-at91
5 *
6 * Modifications for YL-9200 platform:
7 * Copyright (C) 2007 S. Birtles
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/types.h>
25#include <linux/gpio.h>
26#include <linux/init.h>
27#include <linux/mm.h>
28#include <linux/module.h>
29#include <linux/dma-mapping.h>
30#include <linux/platform_device.h>
31#include <linux/spi/spi.h>
32#include <linux/spi/ads7846.h>
33#include <linux/mtd/physmap.h>
34#include <linux/gpio_keys.h>
35#include <linux/input.h>
36
37#include <asm/setup.h>
38#include <asm/mach-types.h>
39#include <asm/irq.h>
40
41#include <asm/mach/arch.h>
42#include <asm/mach/map.h>
43#include <asm/mach/irq.h>
44
45#include <mach/hardware.h>
46#include <mach/at91rm9200_mc.h>
47#include <mach/at91_ramc.h>
48#include <mach/cpu.h>
49
50#include "at91_aic.h"
51#include "board.h"
52#include "generic.h"
53#include "gpio.h"
54
55
56static void __init yl9200_init_early(void)
57{
58 /* Set cpu type: PQFP */
59 at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
60
61 /* Initialize processor: 18.432 MHz crystal */
62 at91_initialize(18432000);
63}
64
65/*
66 * LEDs
67 */
68static struct gpio_led yl9200_leds[] = {
69 { /* D2 */
70 .name = "led2",
71 .gpio = AT91_PIN_PB17,
72 .active_low = 1,
73 .default_trigger = "timer",
74 },
75 { /* D3 */
76 .name = "led3",
77 .gpio = AT91_PIN_PB16,
78 .active_low = 1,
79 .default_trigger = "heartbeat",
80 },
81 { /* D4 */
82 .name = "led4",
83 .gpio = AT91_PIN_PB15,
84 .active_low = 1,
85 },
86 { /* D5 */
87 .name = "led5",
88 .gpio = AT91_PIN_PB8,
89 .active_low = 1,
90 }
91};
92
93/*
94 * Ethernet
95 */
96static struct macb_platform_data __initdata yl9200_eth_data = {
97 .phy_irq_pin = AT91_PIN_PB28,
98 .is_rmii = 1,
99};
100
101/*
102 * USB Host
103 */
104static struct at91_usbh_data __initdata yl9200_usbh_data = {
105 .ports = 1, /* PQFP version of AT91RM9200 */
106 .vbus_pin = {-EINVAL, -EINVAL},
107 .overcurrent_pin= {-EINVAL, -EINVAL},
108};
109
110/*
111 * USB Device
112 */
113static struct at91_udc_data __initdata yl9200_udc_data = {
114 .pullup_pin = AT91_PIN_PC4,
115 .vbus_pin = AT91_PIN_PC5,
116 .pullup_active_low = 1, /* Active Low due to PNP transistor (pg 7) */
117
118};
119
120/*
121 * MMC
122 */
123static struct mci_platform_data __initdata yl9200_mci0_data = {
124 .slot[0] = {
125 .bus_width = 4,
126 .detect_pin = AT91_PIN_PB9,
127 .wp_pin = -EINVAL,
128 },
129};
130
131/*
132 * NAND Flash
133 */
134static struct mtd_partition __initdata yl9200_nand_partition[] = {
135 {
136 .name = "AT91 NAND partition 1, boot",
137 .offset = 0,
138 .size = SZ_256K
139 },
140 {
141 .name = "AT91 NAND partition 2, kernel",
142 .offset = MTDPART_OFS_NXTBLK,
143 .size = (2 * SZ_1M) - SZ_256K
144 },
145 {
146 .name = "AT91 NAND partition 3, filesystem",
147 .offset = MTDPART_OFS_NXTBLK,
148 .size = 14 * SZ_1M
149 },
150 {
151 .name = "AT91 NAND partition 4, storage",
152 .offset = MTDPART_OFS_NXTBLK,
153 .size = SZ_16M
154 },
155 {
156 .name = "AT91 NAND partition 5, ext-fs",
157 .offset = MTDPART_OFS_NXTBLK,
158 .size = SZ_32M
159 }
160};
161
162static struct atmel_nand_data __initdata yl9200_nand_data = {
163 .ale = 6,
164 .cle = 7,
165 .det_pin = -EINVAL,
166 .rdy_pin = AT91_PIN_PC14, /* R/!B (Sheet10) */
167 .enable_pin = AT91_PIN_PC15, /* !CE (Sheet10) */
168 .ecc_mode = NAND_ECC_SOFT,
169 .parts = yl9200_nand_partition,
170 .num_parts = ARRAY_SIZE(yl9200_nand_partition),
171};
172
173/*
174 * NOR Flash
175 */
176#define YL9200_FLASH_BASE AT91_CHIPSELECT_0
177#define YL9200_FLASH_SIZE SZ_16M
178
179static struct mtd_partition yl9200_flash_partitions[] = {
180 {
181 .name = "Bootloader",
182 .offset = 0,
183 .size = SZ_256K,
184 .mask_flags = MTD_WRITEABLE, /* force read-only */
185 },
186 {
187 .name = "Kernel",
188 .offset = MTDPART_OFS_NXTBLK,
189 .size = (2 * SZ_1M) - SZ_256K
190 },
191 {
192 .name = "Filesystem",
193 .offset = MTDPART_OFS_NXTBLK,
194 .size = MTDPART_SIZ_FULL
195 }
196};
197
198static struct physmap_flash_data yl9200_flash_data = {
199 .width = 2,
200 .parts = yl9200_flash_partitions,
201 .nr_parts = ARRAY_SIZE(yl9200_flash_partitions),
202};
203
204static struct resource yl9200_flash_resources[] = {
205 {
206 .start = YL9200_FLASH_BASE,
207 .end = YL9200_FLASH_BASE + YL9200_FLASH_SIZE - 1,
208 .flags = IORESOURCE_MEM,
209 }
210};
211
212static struct platform_device yl9200_flash = {
213 .name = "physmap-flash",
214 .id = 0,
215 .dev = {
216 .platform_data = &yl9200_flash_data,
217 },
218 .resource = yl9200_flash_resources,
219 .num_resources = ARRAY_SIZE(yl9200_flash_resources),
220};
221
222/*
223 * I2C (TWI)
224 */
225static struct i2c_board_info __initdata yl9200_i2c_devices[] = {
226 { /* EEPROM */
227 I2C_BOARD_INFO("24c128", 0x50),
228 }
229};
230
231/*
232 * GPIO Buttons
233*/
234#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
235static struct gpio_keys_button yl9200_buttons[] = {
236 {
237 .gpio = AT91_PIN_PA24,
238 .code = BTN_2,
239 .desc = "SW2",
240 .active_low = 1,
241 .wakeup = 1,
242 },
243 {
244 .gpio = AT91_PIN_PB1,
245 .code = BTN_3,
246 .desc = "SW3",
247 .active_low = 1,
248 .wakeup = 1,
249 },
250 {
251 .gpio = AT91_PIN_PB2,
252 .code = BTN_4,
253 .desc = "SW4",
254 .active_low = 1,
255 .wakeup = 1,
256 },
257 {
258 .gpio = AT91_PIN_PB6,
259 .code = BTN_5,
260 .desc = "SW5",
261 .active_low = 1,
262 .wakeup = 1,
263 }
264};
265
266static struct gpio_keys_platform_data yl9200_button_data = {
267 .buttons = yl9200_buttons,
268 .nbuttons = ARRAY_SIZE(yl9200_buttons),
269};
270
271static struct platform_device yl9200_button_device = {
272 .name = "gpio-keys",
273 .id = -1,
274 .num_resources = 0,
275 .dev = {
276 .platform_data = &yl9200_button_data,
277 }
278};
279
280static void __init yl9200_add_device_buttons(void)
281{
282 at91_set_gpio_input(AT91_PIN_PA24, 1); /* SW2 */
283 at91_set_deglitch(AT91_PIN_PA24, 1);
284 at91_set_gpio_input(AT91_PIN_PB1, 1); /* SW3 */
285 at91_set_deglitch(AT91_PIN_PB1, 1);
286 at91_set_gpio_input(AT91_PIN_PB2, 1); /* SW4 */
287 at91_set_deglitch(AT91_PIN_PB2, 1);
288 at91_set_gpio_input(AT91_PIN_PB6, 1); /* SW5 */
289 at91_set_deglitch(AT91_PIN_PB6, 1);
290
291 /* Enable buttons (Sheet 5) */
292 at91_set_gpio_output(AT91_PIN_PB7, 1);
293
294 platform_device_register(&yl9200_button_device);
295}
296#else
297static void __init yl9200_add_device_buttons(void) {}
298#endif
299
300/*
301 * Touchscreen
302 */
303#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
304static int ads7843_pendown_state(void)
305{
306 return !at91_get_gpio_value(AT91_PIN_PB11); /* Touchscreen PENIRQ */
307}
308
309static struct ads7846_platform_data ads_info = {
310 .model = 7843,
311 .x_min = 150,
312 .x_max = 3830,
313 .y_min = 190,
314 .y_max = 3830,
315 .vref_delay_usecs = 100,
316
317 /* For a 8" touch-screen */
318 // .x_plate_ohms = 603,
319 // .y_plate_ohms = 332,
320
321 /* For a 10.4" touch-screen */
322 // .x_plate_ohms = 611,
323 // .y_plate_ohms = 325,
324
325 .x_plate_ohms = 576,
326 .y_plate_ohms = 366,
327
328 .pressure_max = 15000, /* generally nonsense on the 7843 */
329 .debounce_max = 1,
330 .debounce_rep = 0,
331 .debounce_tol = (~0),
332 .get_pendown_state = ads7843_pendown_state,
333};
334
335static void __init yl9200_add_device_ts(void)
336{
337 at91_set_gpio_input(AT91_PIN_PB11, 1); /* Touchscreen interrupt pin */
338 at91_set_gpio_input(AT91_PIN_PB10, 1); /* Touchscreen BUSY signal - not used! */
339}
340#else
341static void __init yl9200_add_device_ts(void) {}
342#endif
343
344/*
345 * SPI devices
346 */
347static struct spi_board_info yl9200_spi_devices[] = {
348#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
349 { /* Touchscreen */
350 .modalias = "ads7846",
351 .chip_select = 0,
352 .max_speed_hz = 5000 * 26,
353 .platform_data = &ads_info,
354 .irq = AT91_PIN_PB11,
355 },
356#endif
357 { /* CAN */
358 .modalias = "mcp2510",
359 .chip_select = 1,
360 .max_speed_hz = 25000 * 26,
361 .irq = AT91_PIN_PC0,
362 }
363};
364
365/*
366 * LCD / VGA
367 *
368 * EPSON S1D13806 FB (discontinued chip)
369 * EPSON S1D13506 FB
370 */
371#if defined(CONFIG_FB_S1D13XXX) || defined(CONFIG_FB_S1D13XXX_MODULE)
372#include <video/s1d13xxxfb.h>
373
374
375static void yl9200_init_video(void)
376{
377 /* NWAIT Signal */
378 at91_set_A_periph(AT91_PIN_PC6, 0);
379
380 /* Initialization of the Static Memory Controller for Chip Select 2 */
381 at91_ramc_write(0, AT91_SMC_CSR(2), AT91_SMC_DBW_16 /* 16 bit */
382 | AT91_SMC_WSEN | AT91_SMC_NWS_(0x4) /* wait states */
383 | AT91_SMC_TDF_(0x100) /* float time */
384 );
385}
386
387static struct s1d13xxxfb_regval yl9200_s1dfb_initregs[] =
388{
389 {S1DREG_MISC, 0x00}, /* Miscellaneous Register*/
390 {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/
391 {S1DREG_GPIO_CNF0, 0x00}, /* General IO Pins Configuration Register*/
392 {S1DREG_GPIO_CTL0, 0x00}, /* General IO Pins Control Register*/
393 {S1DREG_CLK_CNF, 0x11}, /* Memory Clock Configuration Register*/
394 {S1DREG_LCD_CLK_CNF, 0x10}, /* LCD Pixel Clock Configuration Register*/
395 {S1DREG_CRT_CLK_CNF, 0x12}, /* CRT/TV Pixel Clock Configuration Register*/
396 {S1DREG_MPLUG_CLK_CNF, 0x01}, /* MediaPlug Clock Configuration Register*/
397 {S1DREG_CPU2MEM_WST_SEL, 0x02}, /* CPU To Memory Wait State Select Register*/
398 {S1DREG_MEM_CNF, 0x00}, /* Memory Configuration Register*/
399 {S1DREG_SDRAM_REF_RATE, 0x04}, /* DRAM Refresh Rate Register, MCLK source*/
400 {S1DREG_SDRAM_TC0, 0x12}, /* DRAM Timings Control Register 0*/
401 {S1DREG_SDRAM_TC1, 0x02}, /* DRAM Timings Control Register 1*/
402 {S1DREG_PANEL_TYPE, 0x25}, /* Panel Type Register*/
403 {S1DREG_MOD_RATE, 0x00}, /* MOD Rate Register*/
404 {S1DREG_LCD_DISP_HWIDTH, 0x4F}, /* LCD Horizontal Display Width Register*/
405 {S1DREG_LCD_NDISP_HPER, 0x13}, /* LCD Horizontal Non-Display Period Register*/
406 {S1DREG_TFT_FPLINE_START, 0x01}, /* TFT FPLINE Start Position Register*/
407 {S1DREG_TFT_FPLINE_PWIDTH, 0x0c}, /* TFT FPLINE Pulse Width Register*/
408 {S1DREG_LCD_DISP_VHEIGHT0, 0xDF}, /* LCD Vertical Display Height Register 0*/
409 {S1DREG_LCD_DISP_VHEIGHT1, 0x01}, /* LCD Vertical Display Height Register 1*/
410 {S1DREG_LCD_NDISP_VPER, 0x2c}, /* LCD Vertical Non-Display Period Register*/
411 {S1DREG_TFT_FPFRAME_START, 0x0a}, /* TFT FPFRAME Start Position Register*/
412 {S1DREG_TFT_FPFRAME_PWIDTH, 0x02}, /* TFT FPFRAME Pulse Width Register*/
413 {S1DREG_LCD_DISP_MODE, 0x05}, /* LCD Display Mode Register*/
414 {S1DREG_LCD_MISC, 0x01}, /* LCD Miscellaneous Register*/
415 {S1DREG_LCD_DISP_START0, 0x00}, /* LCD Display Start Address Register 0*/
416 {S1DREG_LCD_DISP_START1, 0x00}, /* LCD Display Start Address Register 1*/
417 {S1DREG_LCD_DISP_START2, 0x00}, /* LCD Display Start Address Register 2*/
418 {S1DREG_LCD_MEM_OFF0, 0x80}, /* LCD Memory Address Offset Register 0*/
419 {S1DREG_LCD_MEM_OFF1, 0x02}, /* LCD Memory Address Offset Register 1*/
420 {S1DREG_LCD_PIX_PAN, 0x03}, /* LCD Pixel Panning Register*/
421 {S1DREG_LCD_DISP_FIFO_HTC, 0x00}, /* LCD Display FIFO High Threshold Control Register*/
422 {S1DREG_LCD_DISP_FIFO_LTC, 0x00}, /* LCD Display FIFO Low Threshold Control Register*/
423 {S1DREG_CRT_DISP_HWIDTH, 0x4F}, /* CRT/TV Horizontal Display Width Register*/
424 {S1DREG_CRT_NDISP_HPER, 0x13}, /* CRT/TV Horizontal Non-Display Period Register*/
425 {S1DREG_CRT_HRTC_START, 0x01}, /* CRT/TV HRTC Start Position Register*/
426 {S1DREG_CRT_HRTC_PWIDTH, 0x0B}, /* CRT/TV HRTC Pulse Width Register*/
427 {S1DREG_CRT_DISP_VHEIGHT0, 0xDF}, /* CRT/TV Vertical Display Height Register 0*/
428 {S1DREG_CRT_DISP_VHEIGHT1, 0x01}, /* CRT/TV Vertical Display Height Register 1*/
429 {S1DREG_CRT_NDISP_VPER, 0x2B}, /* CRT/TV Vertical Non-Display Period Register*/
430 {S1DREG_CRT_VRTC_START, 0x09}, /* CRT/TV VRTC Start Position Register*/
431 {S1DREG_CRT_VRTC_PWIDTH, 0x01}, /* CRT/TV VRTC Pulse Width Register*/
432 {S1DREG_TV_OUT_CTL, 0x18}, /* TV Output Control Register */
433 {S1DREG_CRT_DISP_MODE, 0x05}, /* CRT/TV Display Mode Register, 16BPP*/
434 {S1DREG_CRT_DISP_START0, 0x00}, /* CRT/TV Display Start Address Register 0*/
435 {S1DREG_CRT_DISP_START1, 0x00}, /* CRT/TV Display Start Address Register 1*/
436 {S1DREG_CRT_DISP_START2, 0x00}, /* CRT/TV Display Start Address Register 2*/
437 {S1DREG_CRT_MEM_OFF0, 0x80}, /* CRT/TV Memory Address Offset Register 0*/
438 {S1DREG_CRT_MEM_OFF1, 0x02}, /* CRT/TV Memory Address Offset Register 1*/
439 {S1DREG_CRT_PIX_PAN, 0x00}, /* CRT/TV Pixel Panning Register*/
440 {S1DREG_CRT_DISP_FIFO_HTC, 0x00}, /* CRT/TV Display FIFO High Threshold Control Register*/
441 {S1DREG_CRT_DISP_FIFO_LTC, 0x00}, /* CRT/TV Display FIFO Low Threshold Control Register*/
442 {S1DREG_LCD_CUR_CTL, 0x00}, /* LCD Ink/Cursor Control Register*/
443 {S1DREG_LCD_CUR_START, 0x01}, /* LCD Ink/Cursor Start Address Register*/
444 {S1DREG_LCD_CUR_XPOS0, 0x00}, /* LCD Cursor X Position Register 0*/
445 {S1DREG_LCD_CUR_XPOS1, 0x00}, /* LCD Cursor X Position Register 1*/
446 {S1DREG_LCD_CUR_YPOS0, 0x00}, /* LCD Cursor Y Position Register 0*/
447 {S1DREG_LCD_CUR_YPOS1, 0x00}, /* LCD Cursor Y Position Register 1*/
448 {S1DREG_LCD_CUR_BCTL0, 0x00}, /* LCD Ink/Cursor Blue Color 0 Register*/
449 {S1DREG_LCD_CUR_GCTL0, 0x00}, /* LCD Ink/Cursor Green Color 0 Register*/
450 {S1DREG_LCD_CUR_RCTL0, 0x00}, /* LCD Ink/Cursor Red Color 0 Register*/
451 {S1DREG_LCD_CUR_BCTL1, 0x1F}, /* LCD Ink/Cursor Blue Color 1 Register*/
452 {S1DREG_LCD_CUR_GCTL1, 0x3F}, /* LCD Ink/Cursor Green Color 1 Register*/
453 {S1DREG_LCD_CUR_RCTL1, 0x1F}, /* LCD Ink/Cursor Red Color 1 Register*/
454 {S1DREG_LCD_CUR_FIFO_HTC, 0x00}, /* LCD Ink/Cursor FIFO Threshold Register*/
455 {S1DREG_CRT_CUR_CTL, 0x00}, /* CRT/TV Ink/Cursor Control Register*/
456 {S1DREG_CRT_CUR_START, 0x01}, /* CRT/TV Ink/Cursor Start Address Register*/
457 {S1DREG_CRT_CUR_XPOS0, 0x00}, /* CRT/TV Cursor X Position Register 0*/
458 {S1DREG_CRT_CUR_XPOS1, 0x00}, /* CRT/TV Cursor X Position Register 1*/
459 {S1DREG_CRT_CUR_YPOS0, 0x00}, /* CRT/TV Cursor Y Position Register 0*/
460 {S1DREG_CRT_CUR_YPOS1, 0x00}, /* CRT/TV Cursor Y Position Register 1*/
461 {S1DREG_CRT_CUR_BCTL0, 0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register*/
462 {S1DREG_CRT_CUR_GCTL0, 0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register*/
463 {S1DREG_CRT_CUR_RCTL0, 0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register*/
464 {S1DREG_CRT_CUR_BCTL1, 0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register*/
465 {S1DREG_CRT_CUR_GCTL1, 0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register*/
466 {S1DREG_CRT_CUR_RCTL1, 0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register*/
467 {S1DREG_CRT_CUR_FIFO_HTC, 0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register*/
468 {S1DREG_BBLT_CTL0, 0x00}, /* BitBlt Control Register 0*/
469 {S1DREG_BBLT_CTL1, 0x01}, /* BitBlt Control Register 1*/
470 {S1DREG_BBLT_CC_EXP, 0x00}, /* BitBlt ROP Code/Color Expansion Register*/
471 {S1DREG_BBLT_OP, 0x00}, /* BitBlt Operation Register*/
472 {S1DREG_BBLT_SRC_START0, 0x00}, /* BitBlt Source Start Address Register 0*/
473 {S1DREG_BBLT_SRC_START1, 0x00}, /* BitBlt Source Start Address Register 1*/
474 {S1DREG_BBLT_SRC_START2, 0x00}, /* BitBlt Source Start Address Register 2*/
475 {S1DREG_BBLT_DST_START0, 0x00}, /* BitBlt Destination Start Address Register 0*/
476 {S1DREG_BBLT_DST_START1, 0x00}, /* BitBlt Destination Start Address Register 1*/
477 {S1DREG_BBLT_DST_START2, 0x00}, /* BitBlt Destination Start Address Register 2*/
478 {S1DREG_BBLT_MEM_OFF0, 0x00}, /* BitBlt Memory Address Offset Register 0*/
479 {S1DREG_BBLT_MEM_OFF1, 0x00}, /* BitBlt Memory Address Offset Register 1*/
480 {S1DREG_BBLT_WIDTH0, 0x00}, /* BitBlt Width Register 0*/
481 {S1DREG_BBLT_WIDTH1, 0x00}, /* BitBlt Width Register 1*/
482 {S1DREG_BBLT_HEIGHT0, 0x00}, /* BitBlt Height Register 0*/
483 {S1DREG_BBLT_HEIGHT1, 0x00}, /* BitBlt Height Register 1*/
484 {S1DREG_BBLT_BGC0, 0x00}, /* BitBlt Background Color Register 0*/
485 {S1DREG_BBLT_BGC1, 0x00}, /* BitBlt Background Color Register 1*/
486 {S1DREG_BBLT_FGC0, 0x00}, /* BitBlt Foreground Color Register 0*/
487 {S1DREG_BBLT_FGC1, 0x00}, /* BitBlt Foreground Color Register 1*/
488 {S1DREG_LKUP_MODE, 0x00}, /* Look-Up Table Mode Register*/
489 {S1DREG_LKUP_ADDR, 0x00}, /* Look-Up Table Address Register*/
490 {S1DREG_PS_CNF, 0x00}, /* Power Save Configuration Register*/
491 {S1DREG_PS_STATUS, 0x00}, /* Power Save Status Register*/
492 {S1DREG_CPU2MEM_WDOGT, 0x00}, /* CPU-to-Memory Access Watchdog Timer Register*/
493 {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/
494};
495
496static struct s1d13xxxfb_pdata yl9200_s1dfb_pdata = {
497 .initregs = yl9200_s1dfb_initregs,
498 .initregssize = ARRAY_SIZE(yl9200_s1dfb_initregs),
499 .platform_init_video = yl9200_init_video,
500};
501
502#define YL9200_FB_REG_BASE AT91_CHIPSELECT_7
503#define YL9200_FB_VMEM_BASE YL9200_FB_REG_BASE + SZ_2M
504#define YL9200_FB_VMEM_SIZE SZ_2M
505
506static struct resource yl9200_s1dfb_resource[] = {
507 [0] = { /* video mem */
508 .name = "s1d13xxxfb memory",
509 .start = YL9200_FB_VMEM_BASE,
510 .end = YL9200_FB_VMEM_BASE + YL9200_FB_VMEM_SIZE -1,
511 .flags = IORESOURCE_MEM,
512 },
513 [1] = { /* video registers */
514 .name = "s1d13xxxfb registers",
515 .start = YL9200_FB_REG_BASE,
516 .end = YL9200_FB_REG_BASE + SZ_512 -1,
517 .flags = IORESOURCE_MEM,
518 },
519};
520
521static u64 s1dfb_dmamask = DMA_BIT_MASK(32);
522
523static struct platform_device yl9200_s1dfb_device = {
524 .name = "s1d13806fb",
525 .id = -1,
526 .dev = {
527 .dma_mask = &s1dfb_dmamask,
528 .coherent_dma_mask = DMA_BIT_MASK(32),
529 .platform_data = &yl9200_s1dfb_pdata,
530 },
531 .resource = yl9200_s1dfb_resource,
532 .num_resources = ARRAY_SIZE(yl9200_s1dfb_resource),
533};
534
535void __init yl9200_add_device_video(void)
536{
537 platform_device_register(&yl9200_s1dfb_device);
538}
539#else
540void __init yl9200_add_device_video(void) {}
541#endif
542
543
544static void __init yl9200_board_init(void)
545{
546 /* Serial */
547 /* DBGU on ttyS0. (Rx & Tx only) */
548 at91_register_uart(0, 0, 0);
549
550 /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
551 at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
552 | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
553 | ATMEL_UART_RI);
554
555 /* USART0 on ttyS2. (Rx & Tx only to JP3) */
556 at91_register_uart(AT91RM9200_ID_US0, 2, 0);
557
558 /* USART3 on ttyS3. (Rx, Tx, RTS - RS485 interface) */
559 at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_RTS);
560 at91_add_device_serial();
561 /* Ethernet */
562 at91_add_device_eth(&yl9200_eth_data);
563 /* USB Host */
564 at91_add_device_usbh(&yl9200_usbh_data);
565 /* USB Device */
566 at91_add_device_udc(&yl9200_udc_data);
567 /* I2C */
568 at91_add_device_i2c(yl9200_i2c_devices, ARRAY_SIZE(yl9200_i2c_devices));
569 /* MMC */
570 at91_add_device_mci(0, &yl9200_mci0_data);
571 /* NAND */
572 at91_add_device_nand(&yl9200_nand_data);
573 /* NOR Flash */
574 platform_device_register(&yl9200_flash);
575#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
576 /* SPI */
577 at91_add_device_spi(yl9200_spi_devices, ARRAY_SIZE(yl9200_spi_devices));
578 /* Touchscreen */
579 yl9200_add_device_ts();
580#endif
581 /* LEDs. */
582 at91_gpio_leds(yl9200_leds, ARRAY_SIZE(yl9200_leds));
583 /* Push Buttons */
584 yl9200_add_device_buttons();
585 /* VGA */
586 yl9200_add_device_video();
587}
588
589MACHINE_START(YL9200, "uCdragon YL-9200")
590 /* Maintainer: S.Birtles */
591 .init_time = at91rm9200_timer_init,
592 .map_io = at91_map_io,
593 .handle_irq = at91_aic_handle_irq,
594 .init_early = yl9200_init_early,
595 .init_irq = at91_init_irq_default,
596 .init_machine = yl9200_board_init,
597MACHINE_END
diff --git a/arch/arm/mach-at91/board.h b/arch/arm/mach-at91/board.h
deleted file mode 100644
index 836e9a537e0c..000000000000
--- a/arch/arm/mach-at91/board.h
+++ /dev/null
@@ -1,127 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/board.h
3 *
4 * Copyright (C) 2005 HP Labs
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/*
22 * These are data structures found in platform_device.dev.platform_data,
23 * and describing board-specific data needed by drivers. For example,
24 * which pin is used for a given GPIO role.
25 *
26 * In 2.6, drivers should strongly avoid board-specific knowledge so
27 * that supporting new boards normally won't require driver patches.
28 * Most board-specific knowledge should be in arch/.../board-*.c files.
29 */
30
31#ifndef __ASM_ARCH_BOARD_H
32#define __ASM_ARCH_BOARD_H
33
34#include <linux/platform_data/atmel.h>
35
36 /* USB Device */
37extern void __init at91_add_device_udc(struct at91_udc_data *data);
38
39 /* USB High Speed Device */
40extern void __init at91_add_device_usba(struct usba_platform_data *data);
41
42 /* Compact Flash */
43extern void __init at91_add_device_cf(struct at91_cf_data *data);
44
45 /* MMC / SD */
46 /* atmel-mci platform config */
47extern void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data);
48
49extern void __init at91_add_device_eth(struct macb_platform_data *data);
50
51 /* USB Host */
52extern void __init at91_add_device_usbh(struct at91_usbh_data *data);
53extern void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data);
54extern void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data);
55
56extern void __init at91_add_device_nand(struct atmel_nand_data *data);
57
58 /* I2C*/
59#if defined(CONFIG_ARCH_AT91SAM9G45)
60extern void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices);
61#else
62extern void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices);
63#endif
64
65 /* SPI */
66extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices);
67
68 /* Serial */
69#define ATMEL_UART_CTS 0x01
70#define ATMEL_UART_RTS 0x02
71#define ATMEL_UART_DSR 0x04
72#define ATMEL_UART_DTR 0x08
73#define ATMEL_UART_DCD 0x10
74#define ATMEL_UART_RI 0x20
75
76extern void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins);
77
78extern struct platform_device *atmel_default_console_device;
79
80extern void __init at91_add_device_serial(void);
81
82/*
83 * PWM
84 */
85#define AT91_PWM0 0
86#define AT91_PWM1 1
87#define AT91_PWM2 2
88#define AT91_PWM3 3
89
90extern void __init at91_add_device_pwm(u32 mask);
91
92/*
93 * SSC -- accessed through ssc_request(id). Drivers don't bind to SSC
94 * platform devices. Their SSC ID is part of their configuration data,
95 * along with information about which SSC signals they should use.
96 */
97#define ATMEL_SSC_TK 0x01
98#define ATMEL_SSC_TF 0x02
99#define ATMEL_SSC_TD 0x04
100#define ATMEL_SSC_TX (ATMEL_SSC_TK | ATMEL_SSC_TF | ATMEL_SSC_TD)
101
102#define ATMEL_SSC_RK 0x10
103#define ATMEL_SSC_RF 0x20
104#define ATMEL_SSC_RD 0x40
105#define ATMEL_SSC_RX (ATMEL_SSC_RK | ATMEL_SSC_RF | ATMEL_SSC_RD)
106
107extern void __init at91_add_device_ssc(unsigned id, unsigned pins);
108
109 /* LCD Controller */
110struct atmel_lcdfb_pdata;
111extern void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data);
112
113 /* AC97 */
114extern void __init at91_add_device_ac97(struct ac97c_platform_data *data);
115
116 /* ISI */
117struct isi_platform_data;
118extern void __init at91_add_device_isi(struct isi_platform_data *data,
119 bool use_pck_as_mck);
120
121/* CAN */
122extern void __init at91_add_device_can(struct at91_can_data *data);
123
124 /* LEDs */
125extern void __init at91_gpio_leds(struct gpio_led *leds, int nr);
126
127#endif
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
deleted file mode 100644
index d66f102c352a..000000000000
--- a/arch/arm/mach-at91/clock.c
+++ /dev/null
@@ -1,977 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/clock.c
3 *
4 * Copyright (C) 2005 David Brownell
5 * Copyright (C) 2005 Ivan Kokshaysky
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/fs.h>
17#include <linux/debugfs.h>
18#include <linux/seq_file.h>
19#include <linux/list.h>
20#include <linux/errno.h>
21#include <linux/err.h>
22#include <linux/spinlock.h>
23#include <linux/delay.h>
24#include <linux/clk.h>
25#include <linux/io.h>
26#include <linux/of_address.h>
27#include <linux/clk/at91_pmc.h>
28
29#include <mach/hardware.h>
30#include <mach/cpu.h>
31
32#include <asm/proc-fns.h>
33
34#include "clock.h"
35#include "generic.h"
36
37void __iomem *at91_pmc_base;
38EXPORT_SYMBOL_GPL(at91_pmc_base);
39
40/*
41 * There's a lot more which can be done with clocks, including cpufreq
42 * integration, slow clock mode support (for system suspend), letting
43 * PLLB be used at other rates (on boards that don't need USB), etc.
44 */
45
46#define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY)
47#define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
48#define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL)
49#define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM)
50
51
52/*
53 * Chips have some kind of clocks : group them by functionality
54 */
55#define cpu_has_utmi() ( cpu_is_at91sam9rl() \
56 || cpu_is_at91sam9g45() \
57 || cpu_is_at91sam9x5() \
58 || cpu_is_sama5d3())
59
60#define cpu_has_1056M_plla() (cpu_is_sama5d3())
61
62#define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \
63 || cpu_is_at91sam9g45() \
64 || cpu_is_at91sam9x5() \
65 || cpu_is_at91sam9n12())
66
67#define cpu_has_300M_plla() (cpu_is_at91sam9g10())
68
69#define cpu_has_240M_plla() (cpu_is_at91sam9261() \
70 || cpu_is_at91sam9263() \
71 || cpu_is_at91sam9rl())
72
73#define cpu_has_210M_plla() (cpu_is_at91sam9260())
74
75#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
76 || cpu_is_at91sam9g45() \
77 || cpu_is_at91sam9x5() \
78 || cpu_is_sama5d3()))
79
80#define cpu_has_upll() (cpu_is_at91sam9g45() \
81 || cpu_is_at91sam9x5() \
82 || cpu_is_sama5d3())
83
84/* USB host HS & FS */
85#define cpu_has_uhp() (!cpu_is_at91sam9rl())
86
87/* USB device FS only */
88#define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \
89 || cpu_is_at91sam9g45() \
90 || cpu_is_at91sam9x5() \
91 || cpu_is_sama5d3()))
92
93#define cpu_has_plladiv2() (cpu_is_at91sam9g45() \
94 || cpu_is_at91sam9x5() \
95 || cpu_is_at91sam9n12() \
96 || cpu_is_sama5d3())
97
98#define cpu_has_mdiv3() (cpu_is_at91sam9g45() \
99 || cpu_is_at91sam9x5() \
100 || cpu_is_at91sam9n12() \
101 || cpu_is_sama5d3())
102
103#define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \
104 || cpu_is_at91sam9n12() \
105 || cpu_is_sama5d3())
106
107static LIST_HEAD(clocks);
108static DEFINE_SPINLOCK(clk_lock);
109
110static u32 at91_pllb_usb_init;
111
112/*
113 * Four primary clock sources: two crystal oscillators (32K, main), and
114 * two PLLs. PLLA usually runs the master clock; and PLLB must run at
115 * 48 MHz (unless no USB function clocks are needed). The main clock and
116 * both PLLs are turned off to run in "slow clock mode" (system suspend).
117 */
118static struct clk clk32k = {
119 .name = "clk32k",
120 .rate_hz = AT91_SLOW_CLOCK,
121 .users = 1, /* always on */
122 .id = 0,
123 .type = CLK_TYPE_PRIMARY,
124};
125static struct clk main_clk = {
126 .name = "main",
127 .pmc_mask = AT91_PMC_MOSCS, /* in PMC_SR */
128 .id = 1,
129 .type = CLK_TYPE_PRIMARY,
130};
131static struct clk plla = {
132 .name = "plla",
133 .parent = &main_clk,
134 .pmc_mask = AT91_PMC_LOCKA, /* in PMC_SR */
135 .id = 2,
136 .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
137};
138
139static void pllb_mode(struct clk *clk, int is_on)
140{
141 u32 value;
142
143 if (is_on) {
144 is_on = AT91_PMC_LOCKB;
145 value = at91_pllb_usb_init;
146 } else
147 value = 0;
148
149 // REVISIT: Add work-around for AT91RM9200 Errata #26 ?
150 at91_pmc_write(AT91_CKGR_PLLBR, value);
151
152 do {
153 cpu_relax();
154 } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
155}
156
157static struct clk pllb = {
158 .name = "pllb",
159 .parent = &main_clk,
160 .pmc_mask = AT91_PMC_LOCKB, /* in PMC_SR */
161 .mode = pllb_mode,
162 .id = 3,
163 .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
164};
165
166static void pmc_sys_mode(struct clk *clk, int is_on)
167{
168 if (is_on)
169 at91_pmc_write(AT91_PMC_SCER, clk->pmc_mask);
170 else
171 at91_pmc_write(AT91_PMC_SCDR, clk->pmc_mask);
172}
173
174static void pmc_uckr_mode(struct clk *clk, int is_on)
175{
176 unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR);
177
178 if (is_on) {
179 is_on = AT91_PMC_LOCKU;
180 at91_pmc_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
181 } else
182 at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
183
184 do {
185 cpu_relax();
186 } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
187}
188
189/* USB function clocks (PLLB must be 48 MHz) */
190static struct clk udpck = {
191 .name = "udpck",
192 .parent = &pllb,
193 .mode = pmc_sys_mode,
194};
195struct clk utmi_clk = {
196 .name = "utmi_clk",
197 .parent = &main_clk,
198 .pmc_mask = AT91_PMC_UPLLEN, /* in CKGR_UCKR */
199 .mode = pmc_uckr_mode,
200 .type = CLK_TYPE_PLL,
201};
202static struct clk uhpck = {
203 .name = "uhpck",
204 /*.parent = ... we choose parent at runtime */
205 .mode = pmc_sys_mode,
206};
207
208
209/*
210 * The master clock is divided from the CPU clock (by 1-4). It's used for
211 * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
212 * (e.g baud rate generation). It's sourced from one of the primary clocks.
213 */
214struct clk mck = {
215 .name = "mck",
216 .pmc_mask = AT91_PMC_MCKRDY, /* in PMC_SR */
217};
218
219static void pmc_periph_mode(struct clk *clk, int is_on)
220{
221 u32 regval = 0;
222
223 /*
224 * With sama5d3 devices, we are managing clock division so we have to
225 * use the Peripheral Control Register introduced from at91sam9x5
226 * devices.
227 */
228 if (cpu_is_sama5d3()) {
229 regval |= AT91_PMC_PCR_CMD; /* write command */
230 regval |= clk->pid & AT91_PMC_PCR_PID; /* peripheral selection */
231 regval |= AT91_PMC_PCR_DIV(clk->div);
232 if (is_on)
233 regval |= AT91_PMC_PCR_EN; /* enable clock */
234 at91_pmc_write(AT91_PMC_PCR, regval);
235 } else {
236 if (is_on)
237 at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
238 else
239 at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
240 }
241}
242
243static struct clk __init *at91_css_to_clk(unsigned long css)
244{
245 switch (css) {
246 case AT91_PMC_CSS_SLOW:
247 return &clk32k;
248 case AT91_PMC_CSS_MAIN:
249 return &main_clk;
250 case AT91_PMC_CSS_PLLA:
251 return &plla;
252 case AT91_PMC_CSS_PLLB:
253 if (cpu_has_upll())
254 /* CSS_PLLB == CSS_UPLL */
255 return &utmi_clk;
256 else if (cpu_has_pllb())
257 return &pllb;
258 break;
259 /* alternate PMC: can use master clock */
260 case AT91_PMC_CSS_MASTER:
261 return &mck;
262 }
263
264 return NULL;
265}
266
267static int pmc_prescaler_divider(u32 reg)
268{
269 if (cpu_has_alt_prescaler()) {
270 return 1 << ((reg & AT91_PMC_ALT_PRES) >> PMC_ALT_PRES_OFFSET);
271 } else {
272 return 1 << ((reg & AT91_PMC_PRES) >> PMC_PRES_OFFSET);
273 }
274}
275
276static void __clk_enable(struct clk *clk)
277{
278 if (clk->parent)
279 __clk_enable(clk->parent);
280 if (clk->users++ == 0 && clk->mode)
281 clk->mode(clk, 1);
282}
283
284int clk_enable(struct clk *clk)
285{
286 unsigned long flags;
287
288 spin_lock_irqsave(&clk_lock, flags);
289 __clk_enable(clk);
290 spin_unlock_irqrestore(&clk_lock, flags);
291 return 0;
292}
293EXPORT_SYMBOL(clk_enable);
294
295static void __clk_disable(struct clk *clk)
296{
297 BUG_ON(clk->users == 0);
298 if (--clk->users == 0 && clk->mode)
299 clk->mode(clk, 0);
300 if (clk->parent)
301 __clk_disable(clk->parent);
302}
303
304void clk_disable(struct clk *clk)
305{
306 unsigned long flags;
307
308 spin_lock_irqsave(&clk_lock, flags);
309 __clk_disable(clk);
310 spin_unlock_irqrestore(&clk_lock, flags);
311}
312EXPORT_SYMBOL(clk_disable);
313
314unsigned long clk_get_rate(struct clk *clk)
315{
316 unsigned long flags;
317 unsigned long rate;
318
319 spin_lock_irqsave(&clk_lock, flags);
320 for (;;) {
321 rate = clk->rate_hz;
322 if (rate || !clk->parent)
323 break;
324 clk = clk->parent;
325 }
326 spin_unlock_irqrestore(&clk_lock, flags);
327 return rate;
328}
329EXPORT_SYMBOL(clk_get_rate);
330
331/*------------------------------------------------------------------------*/
332
333/*
334 * For now, only the programmable clocks support reparenting (MCK could
335 * do this too, with care) or rate changing (the PLLs could do this too,
336 * ditto MCK but that's more for cpufreq). Drivers may reparent to get
337 * a better rate match; we don't.
338 */
339
340long clk_round_rate(struct clk *clk, unsigned long rate)
341{
342 unsigned long flags;
343 unsigned prescale;
344 unsigned long actual;
345 unsigned long prev = ULONG_MAX;
346
347 if (!clk_is_programmable(clk))
348 return -EINVAL;
349 spin_lock_irqsave(&clk_lock, flags);
350
351 actual = clk->parent->rate_hz;
352 for (prescale = 0; prescale < 7; prescale++) {
353 if (actual > rate)
354 prev = actual;
355
356 if (actual && actual <= rate) {
357 if ((prev - rate) < (rate - actual)) {
358 actual = prev;
359 prescale--;
360 }
361 break;
362 }
363 actual >>= 1;
364 }
365
366 spin_unlock_irqrestore(&clk_lock, flags);
367 return (prescale < 7) ? actual : -ENOENT;
368}
369EXPORT_SYMBOL(clk_round_rate);
370
371int clk_set_rate(struct clk *clk, unsigned long rate)
372{
373 unsigned long flags;
374 unsigned prescale;
375 unsigned long prescale_offset, css_mask;
376 unsigned long actual;
377
378 if (!clk_is_programmable(clk))
379 return -EINVAL;
380 if (clk->users)
381 return -EBUSY;
382
383 if (cpu_has_alt_prescaler()) {
384 prescale_offset = PMC_ALT_PRES_OFFSET;
385 css_mask = AT91_PMC_ALT_PCKR_CSS;
386 } else {
387 prescale_offset = PMC_PRES_OFFSET;
388 css_mask = AT91_PMC_CSS;
389 }
390
391 spin_lock_irqsave(&clk_lock, flags);
392
393 actual = clk->parent->rate_hz;
394 for (prescale = 0; prescale < 7; prescale++) {
395 if (actual && actual <= rate) {
396 u32 pckr;
397
398 pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
399 pckr &= css_mask; /* keep clock selection */
400 pckr |= prescale << prescale_offset;
401 at91_pmc_write(AT91_PMC_PCKR(clk->id), pckr);
402 clk->rate_hz = actual;
403 break;
404 }
405 actual >>= 1;
406 }
407
408 spin_unlock_irqrestore(&clk_lock, flags);
409 return (prescale < 7) ? actual : -ENOENT;
410}
411EXPORT_SYMBOL(clk_set_rate);
412
413struct clk *clk_get_parent(struct clk *clk)
414{
415 return clk->parent;
416}
417EXPORT_SYMBOL(clk_get_parent);
418
419int clk_set_parent(struct clk *clk, struct clk *parent)
420{
421 unsigned long flags;
422
423 if (clk->users)
424 return -EBUSY;
425 if (!clk_is_primary(parent) || !clk_is_programmable(clk))
426 return -EINVAL;
427
428 if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB)
429 return -EINVAL;
430
431 spin_lock_irqsave(&clk_lock, flags);
432
433 clk->rate_hz = parent->rate_hz;
434 clk->parent = parent;
435 at91_pmc_write(AT91_PMC_PCKR(clk->id), parent->id);
436
437 spin_unlock_irqrestore(&clk_lock, flags);
438 return 0;
439}
440EXPORT_SYMBOL(clk_set_parent);
441
442/* establish PCK0..PCKN parentage and rate */
443static void __init init_programmable_clock(struct clk *clk)
444{
445 struct clk *parent;
446 u32 pckr;
447 unsigned int css_mask;
448
449 if (cpu_has_alt_prescaler())
450 css_mask = AT91_PMC_ALT_PCKR_CSS;
451 else
452 css_mask = AT91_PMC_CSS;
453
454 pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
455 parent = at91_css_to_clk(pckr & css_mask);
456 clk->parent = parent;
457 clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr);
458}
459
460/*------------------------------------------------------------------------*/
461
462#ifdef CONFIG_DEBUG_FS
463
464static int at91_clk_show(struct seq_file *s, void *unused)
465{
466 u32 scsr, pcsr, pcsr1 = 0, uckr = 0, sr;
467 struct clk *clk;
468
469 scsr = at91_pmc_read(AT91_PMC_SCSR);
470 pcsr = at91_pmc_read(AT91_PMC_PCSR);
471 if (cpu_is_sama5d3())
472 pcsr1 = at91_pmc_read(AT91_PMC_PCSR1);
473 sr = at91_pmc_read(AT91_PMC_SR);
474 seq_printf(s, "SCSR = %8x\n", scsr);
475 seq_printf(s, "PCSR = %8x\n", pcsr);
476 if (cpu_is_sama5d3())
477 seq_printf(s, "PCSR1 = %8x\n", pcsr1);
478 seq_printf(s, "MOR = %8x\n", at91_pmc_read(AT91_CKGR_MOR));
479 seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR));
480 seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR));
481 if (cpu_has_pllb())
482 seq_printf(s, "PLLB = %8x\n", at91_pmc_read(AT91_CKGR_PLLBR));
483 if (cpu_has_utmi()) {
484 uckr = at91_pmc_read(AT91_CKGR_UCKR);
485 seq_printf(s, "UCKR = %8x\n", uckr);
486 }
487 seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
488 if (cpu_has_upll() || cpu_is_at91sam9n12())
489 seq_printf(s, "USB = %8x\n", at91_pmc_read(AT91_PMC_USB));
490 seq_printf(s, "SR = %8x\n", sr);
491
492 seq_printf(s, "\n");
493
494 list_for_each_entry(clk, &clocks, node) {
495 char *state;
496
497 if (clk->mode == pmc_sys_mode) {
498 state = (scsr & clk->pmc_mask) ? "on" : "off";
499 } else if (clk->mode == pmc_periph_mode) {
500 if (cpu_is_sama5d3()) {
501 u32 pmc_mask = 1 << (clk->pid % 32);
502
503 if (clk->pid > 31)
504 state = (pcsr1 & pmc_mask) ? "on" : "off";
505 else
506 state = (pcsr & pmc_mask) ? "on" : "off";
507 } else {
508 state = (pcsr & clk->pmc_mask) ? "on" : "off";
509 }
510 } else if (clk->mode == pmc_uckr_mode) {
511 state = (uckr & clk->pmc_mask) ? "on" : "off";
512 } else if (clk->pmc_mask) {
513 state = (sr & clk->pmc_mask) ? "on" : "off";
514 } else if (clk == &clk32k || clk == &main_clk) {
515 state = "on";
516 } else {
517 state = "";
518 }
519
520 seq_printf(s, "%-10s users=%2d %-3s %9lu Hz %s\n",
521 clk->name, clk->users, state, clk_get_rate(clk),
522 clk->parent ? clk->parent->name : "");
523 }
524 return 0;
525}
526
527static int at91_clk_open(struct inode *inode, struct file *file)
528{
529 return single_open(file, at91_clk_show, NULL);
530}
531
532static const struct file_operations at91_clk_operations = {
533 .open = at91_clk_open,
534 .read = seq_read,
535 .llseek = seq_lseek,
536 .release = single_release,
537};
538
539static int __init at91_clk_debugfs_init(void)
540{
541 /* /sys/kernel/debug/at91_clk */
542 (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);
543
544 return 0;
545}
546postcore_initcall(at91_clk_debugfs_init);
547
548#endif
549
550/*------------------------------------------------------------------------*/
551
552/* Register a new clock */
553static void __init at91_clk_add(struct clk *clk)
554{
555 list_add_tail(&clk->node, &clocks);
556
557 clk->cl.con_id = clk->name;
558 clk->cl.clk = clk;
559 clkdev_add(&clk->cl);
560}
561
562int __init clk_register(struct clk *clk)
563{
564 if (clk_is_peripheral(clk)) {
565 if (!clk->parent)
566 clk->parent = &mck;
567 if (cpu_is_sama5d3())
568 clk->rate_hz = DIV_ROUND_UP(clk->parent->rate_hz,
569 1 << clk->div);
570 clk->mode = pmc_periph_mode;
571 }
572 else if (clk_is_sys(clk)) {
573 clk->parent = &mck;
574 clk->mode = pmc_sys_mode;
575 }
576 else if (clk_is_programmable(clk)) {
577 clk->mode = pmc_sys_mode;
578 init_programmable_clock(clk);
579 }
580
581 at91_clk_add(clk);
582
583 return 0;
584}
585
586/*------------------------------------------------------------------------*/
587
588static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
589{
590 unsigned mul, div;
591
592 div = reg & 0xff;
593 if (cpu_is_sama5d3())
594 mul = AT91_PMC3_MUL_GET(reg);
595 else
596 mul = AT91_PMC_MUL_GET(reg);
597
598 if (div && mul) {
599 freq /= div;
600 freq *= mul + 1;
601 } else
602 freq = 0;
603
604 return freq;
605}
606
607static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
608{
609 if (pll == &pllb && (reg & AT91_PMC_USB96M))
610 return freq / 2;
611 else if (pll == &utmi_clk || cpu_is_at91sam9n12())
612 return freq / (1 + ((reg & AT91_PMC_OHCIUSBDIV) >> 8));
613 else
614 return freq;
615}
616
617static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
618{
619 unsigned i, div = 0, mul = 0, diff = 1 << 30;
620 unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
621
622 /* PLL output max 240 MHz (or 180 MHz per errata) */
623 if (out_freq > 240000000)
624 goto fail;
625
626 for (i = 1; i < 256; i++) {
627 int diff1;
628 unsigned input, mul1;
629
630 /*
631 * PLL input between 1MHz and 32MHz per spec, but lower
632 * frequences seem necessary in some cases so allow 100K.
633 * Warning: some newer products need 2MHz min.
634 */
635 input = main_freq / i;
636 if (cpu_is_at91sam9g20() && input < 2000000)
637 continue;
638 if (input < 100000)
639 continue;
640 if (input > 32000000)
641 continue;
642
643 mul1 = out_freq / input;
644 if (cpu_is_at91sam9g20() && mul > 63)
645 continue;
646 if (mul1 > 2048)
647 continue;
648 if (mul1 < 2)
649 goto fail;
650
651 diff1 = out_freq - input * mul1;
652 if (diff1 < 0)
653 diff1 = -diff1;
654 if (diff > diff1) {
655 diff = diff1;
656 div = i;
657 mul = mul1;
658 if (diff == 0)
659 break;
660 }
661 }
662 if (i == 256 && diff > (out_freq >> 5))
663 goto fail;
664 return ret | ((mul - 1) << 16) | div;
665fail:
666 return 0;
667}
668
669static struct clk *const standard_pmc_clocks[] __initconst = {
670 /* four primary clocks */
671 &clk32k,
672 &main_clk,
673 &plla,
674
675 /* MCK */
676 &mck
677};
678
679/* PLLB generated USB full speed clock init */
680static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
681{
682 unsigned int reg;
683
684 /*
685 * USB clock init: choose 48 MHz PLLB value,
686 * disable 48MHz clock during usb peripheral suspend.
687 *
688 * REVISIT: assumes MCK doesn't derive from PLLB!
689 */
690 uhpck.parent = &pllb;
691
692 reg = at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2);
693 pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
694 if (cpu_is_at91rm9200()) {
695 reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
696 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
697 udpck.pmc_mask = AT91RM9200_PMC_UDP;
698 at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
699 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
700 cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
701 cpu_is_at91sam9g10()) {
702 reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
703 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
704 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
705 } else if (cpu_is_at91sam9n12()) {
706 /* Divider for USB clock is in USB clock register for 9n12 */
707 reg = AT91_PMC_USBS_PLLB;
708
709 /* For PLLB output 96M, set usb divider 2 (USBDIV + 1) */
710 reg |= AT91_PMC_OHCIUSBDIV_2;
711 at91_pmc_write(AT91_PMC_USB, reg);
712
713 /* Still setup masks */
714 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
715 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
716 }
717 at91_pmc_write(AT91_CKGR_PLLBR, 0);
718
719 udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
720 uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
721}
722
723/* UPLL generated USB full speed clock init */
724static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
725{
726 /*
727 * USB clock init: choose 480 MHz from UPLL,
728 */
729 unsigned int usbr = AT91_PMC_USBS_UPLL;
730
731 /* Setup divider by 10 to reach 48 MHz */
732 usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
733
734 at91_pmc_write(AT91_PMC_USB, usbr);
735
736 /* Now set uhpck values */
737 uhpck.parent = &utmi_clk;
738 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
739 uhpck.rate_hz = at91_usb_rate(&utmi_clk, utmi_clk.rate_hz, usbr);
740}
741
742static int __init at91_pmc_init(unsigned long main_clock)
743{
744 unsigned tmp, freq, mckr;
745 int i;
746 int pll_overclock = false;
747
748 /*
749 * When the bootloader initialized the main oscillator correctly,
750 * there's no problem using the cycle counter. But if it didn't,
751 * or when using oscillator bypass mode, we must be told the speed
752 * of the main clock.
753 */
754 if (!main_clock) {
755 do {
756 tmp = at91_pmc_read(AT91_CKGR_MCFR);
757 } while (!(tmp & AT91_PMC_MAINRDY));
758 main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
759 }
760 main_clk.rate_hz = main_clock;
761
762 /* report if PLLA is more than mildly overclocked */
763 plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR));
764 if (cpu_has_1056M_plla()) {
765 if (plla.rate_hz > 1056000000)
766 pll_overclock = true;
767 } else if (cpu_has_800M_plla()) {
768 if (plla.rate_hz > 800000000)
769 pll_overclock = true;
770 } else if (cpu_has_300M_plla()) {
771 if (plla.rate_hz > 300000000)
772 pll_overclock = true;
773 } else if (cpu_has_240M_plla()) {
774 if (plla.rate_hz > 240000000)
775 pll_overclock = true;
776 } else if (cpu_has_210M_plla()) {
777 if (plla.rate_hz > 210000000)
778 pll_overclock = true;
779 } else {
780 if (plla.rate_hz > 209000000)
781 pll_overclock = true;
782 }
783 if (pll_overclock)
784 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
785
786 if (cpu_has_plladiv2()) {
787 mckr = at91_pmc_read(AT91_PMC_MCKR);
788 plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */
789 }
790
791 if (!cpu_has_pllb() && cpu_has_upll()) {
792 /* setup UTMI clock as the fourth primary clock
793 * (instead of pllb) */
794 utmi_clk.type |= CLK_TYPE_PRIMARY;
795 utmi_clk.id = 3;
796 }
797
798
799 /*
800 * USB HS clock init
801 */
802 if (cpu_has_utmi()) {
803 /*
804 * multiplier is hard-wired to 40
805 * (obtain the USB High Speed 480 MHz when input is 12 MHz)
806 */
807 utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
808
809 /* UTMI bias and PLL are managed at the same time */
810 if (cpu_has_upll())
811 utmi_clk.pmc_mask |= AT91_PMC_BIASEN;
812 }
813
814 /*
815 * USB FS clock init
816 */
817 if (cpu_has_pllb())
818 at91_pllb_usbfs_clock_init(main_clock);
819 if (cpu_has_upll())
820 /* assumes that we choose UPLL for USB and not PLLA */
821 at91_upll_usbfs_clock_init(main_clock);
822
823 /*
824 * MCK and CPU derive from one of those primary clocks.
825 * For now, assume this parentage won't change.
826 */
827 mckr = at91_pmc_read(AT91_PMC_MCKR);
828 mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
829 freq = mck.parent->rate_hz;
830 freq /= pmc_prescaler_divider(mckr); /* prescale */
831 if (cpu_is_at91rm9200()) {
832 mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
833 } else if (cpu_is_at91sam9g20()) {
834 mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
835 freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
836 if (mckr & AT91_PMC_PDIV)
837 freq /= 2; /* processor clock division */
838 } else if (cpu_has_mdiv3()) {
839 mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
840 freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
841 } else {
842 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
843 }
844
845 if (cpu_has_alt_prescaler()) {
846 /* Programmable clocks can use MCK */
847 mck.type |= CLK_TYPE_PRIMARY;
848 mck.id = 4;
849 }
850
851 /* Register the PMC's standard clocks */
852 for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
853 at91_clk_add(standard_pmc_clocks[i]);
854
855 if (cpu_has_pllb())
856 at91_clk_add(&pllb);
857
858 if (cpu_has_uhp())
859 at91_clk_add(&uhpck);
860
861 if (cpu_has_udpfs())
862 at91_clk_add(&udpck);
863
864 if (cpu_has_utmi())
865 at91_clk_add(&utmi_clk);
866
867 /* MCK and CPU clock are "always on" */
868 clk_enable(&mck);
869
870 printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
871 freq / 1000000, (unsigned) mck.rate_hz / 1000000,
872 (unsigned) main_clock / 1000000,
873 ((unsigned) main_clock % 1000000) / 1000);
874
875 return 0;
876}
877
878#if defined(CONFIG_OF)
879static struct of_device_id pmc_ids[] = {
880 { .compatible = "atmel,at91rm9200-pmc" },
881 { .compatible = "atmel,at91sam9260-pmc" },
882 { .compatible = "atmel,at91sam9g45-pmc" },
883 { .compatible = "atmel,at91sam9n12-pmc" },
884 { .compatible = "atmel,at91sam9x5-pmc" },
885 { .compatible = "atmel,sama5d3-pmc" },
886 { /*sentinel*/ }
887};
888
889static struct of_device_id osc_ids[] = {
890 { .compatible = "atmel,osc" },
891 { /*sentinel*/ }
892};
893
894int __init at91_dt_clock_init(void)
895{
896 struct device_node *np;
897 u32 main_clock = 0;
898
899 np = of_find_matching_node(NULL, pmc_ids);
900 if (!np)
901 panic("unable to find compatible pmc node in dtb\n");
902
903 at91_pmc_base = of_iomap(np, 0);
904 if (!at91_pmc_base)
905 panic("unable to map pmc cpu registers\n");
906
907 of_node_put(np);
908
909 /* retrieve the freqency of fixed clocks from device tree */
910 np = of_find_matching_node(NULL, osc_ids);
911 if (np) {
912 u32 rate;
913 if (!of_property_read_u32(np, "clock-frequency", &rate))
914 main_clock = rate;
915 }
916
917 of_node_put(np);
918
919 return at91_pmc_init(main_clock);
920}
921#endif
922
923int __init at91_clock_init(unsigned long main_clock)
924{
925 at91_pmc_base = ioremap(AT91_PMC, 256);
926 if (!at91_pmc_base)
927 panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);
928
929 return at91_pmc_init(main_clock);
930}
931
932/*
933 * Several unused clocks may be active. Turn them off.
934 */
935static int __init at91_clock_reset(void)
936{
937 unsigned long pcdr = 0;
938 unsigned long pcdr1 = 0;
939 unsigned long scdr = 0;
940 struct clk *clk;
941
942 list_for_each_entry(clk, &clocks, node) {
943 if (clk->users > 0)
944 continue;
945
946 if (clk->mode == pmc_periph_mode) {
947 if (cpu_is_sama5d3()) {
948 u32 pmc_mask = 1 << (clk->pid % 32);
949
950 if (clk->pid > 31)
951 pcdr1 |= pmc_mask;
952 else
953 pcdr |= pmc_mask;
954 } else
955 pcdr |= clk->pmc_mask;
956 }
957
958 if (clk->mode == pmc_sys_mode)
959 scdr |= clk->pmc_mask;
960
961 pr_debug("Clocks: disable unused %s\n", clk->name);
962 }
963
964 at91_pmc_write(AT91_PMC_SCDR, scdr);
965 at91_pmc_write(AT91_PMC_PCDR, pcdr);
966 if (cpu_is_sama5d3())
967 at91_pmc_write(AT91_PMC_PCDR1, pcdr1);
968
969 return 0;
970}
971late_initcall(at91_clock_reset);
972
973void at91sam9_idle(void)
974{
975 at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
976 cpu_do_idle();
977}
diff --git a/arch/arm/mach-at91/clock.h b/arch/arm/mach-at91/clock.h
deleted file mode 100644
index a98a39bbd883..000000000000
--- a/arch/arm/mach-at91/clock.h
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/clock.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/clkdev.h>
10
11#define CLK_TYPE_PRIMARY 0x1
12#define CLK_TYPE_PLL 0x2
13#define CLK_TYPE_PROGRAMMABLE 0x4
14#define CLK_TYPE_PERIPHERAL 0x8
15#define CLK_TYPE_SYSTEM 0x10
16
17
18struct clk {
19 struct list_head node;
20 const char *name; /* unique clock name */
21 struct clk_lookup cl;
22 unsigned long rate_hz;
23 unsigned div; /* parent clock divider */
24 struct clk *parent;
25 unsigned pid; /* peripheral ID */
26 u32 pmc_mask;
27 void (*mode)(struct clk *, int);
28 unsigned id:3; /* PCK0..4, or 32k/main/a/b */
29 unsigned type; /* clock type */
30 u16 users;
31};
32
33
34extern int __init clk_register(struct clk *clk);
35extern struct clk mck;
36extern struct clk utmi_clk;
37
38#define CLKDEV_CON_ID(_id, _clk) \
39 { \
40 .con_id = _id, \
41 .clk = _clk, \
42 }
43
44#define CLKDEV_CON_DEV_ID(_con_id, _dev_id, _clk) \
45 { \
46 .con_id = _con_id, \
47 .dev_id = _dev_id, \
48 .clk = _clk, \
49 }
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 81959cf4a137..d53324210adf 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -11,7 +11,6 @@
11#ifndef _AT91_GENERIC_H 11#ifndef _AT91_GENERIC_H
12#define _AT91_GENERIC_H 12#define _AT91_GENERIC_H
13 13
14#include <linux/clkdev.h>
15#include <linux/of.h> 14#include <linux/of.h>
16#include <linux/reboot.h> 15#include <linux/reboot.h>
17 16
@@ -23,71 +22,19 @@ extern void __init at91_init_sram(int bank, unsigned long base,
23 22
24 /* Processors */ 23 /* Processors */
25extern void __init at91rm9200_set_type(int type); 24extern void __init at91rm9200_set_type(int type);
26extern void __init at91_initialize(unsigned long main_clock);
27extern void __init at91x40_initialize(unsigned long main_clock);
28extern void __init at91rm9200_dt_initialize(void); 25extern void __init at91rm9200_dt_initialize(void);
29extern void __init at91_dt_initialize(void); 26extern void __init at91_dt_initialize(void);
30 27
31 /* Interrupts */ 28 /* Interrupts */
32extern void __init at91_init_irq_default(void);
33extern void __init at91_init_interrupts(unsigned int priority[]);
34extern void __init at91x40_init_interrupts(unsigned int priority[]);
35extern void __init at91_aic_init(unsigned int priority[],
36 unsigned int ext_irq_mask);
37extern int __init at91_aic_of_init(struct device_node *node,
38 struct device_node *parent);
39extern int __init at91_aic5_of_init(struct device_node *node,
40 struct device_node *parent);
41extern void __init at91_sysirq_mask_rtc(u32 rtc_base); 29extern void __init at91_sysirq_mask_rtc(u32 rtc_base);
42extern void __init at91_sysirq_mask_rtt(u32 rtt_base); 30extern void __init at91_sysirq_mask_rtt(u32 rtt_base);
43 31
44 /* Devices */
45extern void __init at91_register_devices(void);
46
47 /* Timer */ 32 /* Timer */
48extern void __init at91_init_time(void);
49extern void at91rm9200_ioremap_st(u32 addr);
50extern void at91rm9200_timer_init(void); 33extern void at91rm9200_timer_init(void);
51extern void at91sam926x_ioremap_pit(u32 addr);
52extern void at91sam926x_pit_init(int irq);
53extern void at91x40_timer_init(void);
54
55 /* Clocks */
56#ifdef CONFIG_OLD_CLK_AT91
57extern int __init at91_clock_init(unsigned long main_clock);
58extern int __init at91_dt_clock_init(void);
59#else
60static int inline at91_clock_init(unsigned long main_clock) { return 0; }
61static int inline at91_dt_clock_init(void) { return 0; }
62#endif
63struct device;
64
65 /* Power Management */
66extern void at91_irq_suspend(void);
67extern void at91_irq_resume(void);
68 34
69/* idle */ 35/* idle */
70extern void at91sam9_idle(void); 36extern void at91sam9_idle(void);
71 37
72/* Matrix */ 38/* Matrix */
73extern void at91_ioremap_matrix(u32 base_addr); 39extern void at91_ioremap_matrix(u32 base_addr);
74
75/* Ram Controler */
76extern void at91_ioremap_ramc(int id, u32 addr, u32 size);
77
78 /* GPIO */
79#define AT91RM9200_PQFP 3 /* AT91RM9200 PQFP package has 3 banks */
80#define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */
81
82struct at91_gpio_bank {
83 unsigned short id; /* peripheral ID */
84 unsigned long regbase; /* offset from system peripheral base */
85};
86extern void __init at91_gpio_init(struct at91_gpio_bank *, int nr_banks);
87extern void __init at91_gpio_irq_setup(void);
88extern int __init at91_gpio_of_irq_setup(struct device_node *node,
89 struct device_node *parent);
90
91extern u32 at91_get_extern_irq(void);
92
93#endif /* _AT91_GENERIC_H */ 40#endif /* _AT91_GENERIC_H */
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
deleted file mode 100644
index d3f05aaad8ba..000000000000
--- a/arch/arm/mach-at91/gpio.c
+++ /dev/null
@@ -1,982 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/gpio.c
3 *
4 * Copyright (C) 2005 HP Labs
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/clk.h>
13#include <linux/errno.h>
14#include <linux/device.h>
15#include <linux/gpio.h>
16#include <linux/interrupt.h>
17#include <linux/irq.h>
18#include <linux/debugfs.h>
19#include <linux/seq_file.h>
20#include <linux/kernel.h>
21#include <linux/list.h>
22#include <linux/module.h>
23#include <linux/io.h>
24#include <linux/irqdomain.h>
25#include <linux/irqchip/chained_irq.h>
26#include <linux/of_address.h>
27
28#include <mach/hardware.h>
29#include <mach/at91_pio.h>
30
31#include "generic.h"
32#include "gpio.h"
33
34#define MAX_NB_GPIO_PER_BANK 32
35
36struct at91_gpio_chip {
37 struct gpio_chip chip;
38 struct at91_gpio_chip *next; /* Bank sharing same clock */
39 int pioc_hwirq; /* PIO bank interrupt identifier on AIC */
40 int pioc_virq; /* PIO bank Linux virtual interrupt */
41 int pioc_idx; /* PIO bank index */
42 void __iomem *regbase; /* PIO bank virtual address */
43 struct clk *clock; /* associated clock */
44 struct irq_domain *domain; /* associated irq domain */
45};
46
47#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
48
49static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset);
50static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip);
51static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val);
52static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset);
53static int at91_gpiolib_get_direction(struct gpio_chip *chip, unsigned offset);
54static int at91_gpiolib_direction_output(struct gpio_chip *chip,
55 unsigned offset, int val);
56static int at91_gpiolib_direction_input(struct gpio_chip *chip,
57 unsigned offset);
58static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset);
59
60#define AT91_GPIO_CHIP(name) \
61 { \
62 .chip = { \
63 .label = name, \
64 .request = at91_gpiolib_request, \
65 .get_direction = at91_gpiolib_get_direction, \
66 .direction_input = at91_gpiolib_direction_input, \
67 .direction_output = at91_gpiolib_direction_output, \
68 .get = at91_gpiolib_get, \
69 .set = at91_gpiolib_set, \
70 .dbg_show = at91_gpiolib_dbg_show, \
71 .to_irq = at91_gpiolib_to_irq, \
72 .ngpio = MAX_NB_GPIO_PER_BANK, \
73 }, \
74 }
75
76static struct at91_gpio_chip gpio_chip[] = {
77 AT91_GPIO_CHIP("pioA"),
78 AT91_GPIO_CHIP("pioB"),
79 AT91_GPIO_CHIP("pioC"),
80 AT91_GPIO_CHIP("pioD"),
81 AT91_GPIO_CHIP("pioE"),
82};
83
84static int gpio_banks;
85static unsigned long at91_gpio_caps;
86
87/* All PIO controllers support PIO3 features */
88#define AT91_GPIO_CAP_PIO3 (1 << 0)
89
90#define has_pio3() (at91_gpio_caps & AT91_GPIO_CAP_PIO3)
91
92/*--------------------------------------------------------------------------*/
93
94static inline void __iomem *pin_to_controller(unsigned pin)
95{
96 pin /= MAX_NB_GPIO_PER_BANK;
97 if (likely(pin < gpio_banks))
98 return gpio_chip[pin].regbase;
99
100 return NULL;
101}
102
103static inline unsigned pin_to_mask(unsigned pin)
104{
105 return 1 << (pin % MAX_NB_GPIO_PER_BANK);
106}
107
108
109static char peripheral_function(void __iomem *pio, unsigned mask)
110{
111 char ret = 'X';
112 u8 select;
113
114 if (pio) {
115 if (has_pio3()) {
116 select = !!(__raw_readl(pio + PIO_ABCDSR1) & mask);
117 select |= (!!(__raw_readl(pio + PIO_ABCDSR2) & mask) << 1);
118 ret = 'A' + select;
119 } else {
120 ret = __raw_readl(pio + PIO_ABSR) & mask ?
121 'B' : 'A';
122 }
123 }
124
125 return ret;
126}
127
128/*--------------------------------------------------------------------------*/
129
130/* Not all hardware capabilities are exposed through these calls; they
131 * only encapsulate the most common features and modes. (So if you
132 * want to change signals in groups, do it directly.)
133 *
134 * Bootloaders will usually handle some of the pin multiplexing setup.
135 * The intent is certainly that by the time Linux is fully booted, all
136 * pins should have been fully initialized. These setup calls should
137 * only be used by board setup routines, or possibly in driver probe().
138 *
139 * For bootloaders doing all that setup, these calls could be inlined
140 * as NOPs so Linux won't duplicate any setup code
141 */
142
143
144/*
145 * mux the pin to the "GPIO" peripheral role.
146 */
147int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup)
148{
149 void __iomem *pio = pin_to_controller(pin);
150 unsigned mask = pin_to_mask(pin);
151
152 if (!pio)
153 return -EINVAL;
154 __raw_writel(mask, pio + PIO_IDR);
155 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
156 __raw_writel(mask, pio + PIO_PER);
157 return 0;
158}
159EXPORT_SYMBOL(at91_set_GPIO_periph);
160
161
162/*
163 * mux the pin to the "A" internal peripheral role.
164 */
165int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
166{
167 void __iomem *pio = pin_to_controller(pin);
168 unsigned mask = pin_to_mask(pin);
169
170 if (!pio)
171 return -EINVAL;
172
173 __raw_writel(mask, pio + PIO_IDR);
174 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
175 if (has_pio3()) {
176 __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask,
177 pio + PIO_ABCDSR1);
178 __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
179 pio + PIO_ABCDSR2);
180 } else {
181 __raw_writel(mask, pio + PIO_ASR);
182 }
183 __raw_writel(mask, pio + PIO_PDR);
184 return 0;
185}
186EXPORT_SYMBOL(at91_set_A_periph);
187
188
189/*
190 * mux the pin to the "B" internal peripheral role.
191 */
192int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
193{
194 void __iomem *pio = pin_to_controller(pin);
195 unsigned mask = pin_to_mask(pin);
196
197 if (!pio)
198 return -EINVAL;
199
200 __raw_writel(mask, pio + PIO_IDR);
201 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
202 if (has_pio3()) {
203 __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask,
204 pio + PIO_ABCDSR1);
205 __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
206 pio + PIO_ABCDSR2);
207 } else {
208 __raw_writel(mask, pio + PIO_BSR);
209 }
210 __raw_writel(mask, pio + PIO_PDR);
211 return 0;
212}
213EXPORT_SYMBOL(at91_set_B_periph);
214
215
216/*
217 * mux the pin to the "C" internal peripheral role.
218 */
219int __init_or_module at91_set_C_periph(unsigned pin, int use_pullup)
220{
221 void __iomem *pio = pin_to_controller(pin);
222 unsigned mask = pin_to_mask(pin);
223
224 if (!pio || !has_pio3())
225 return -EINVAL;
226
227 __raw_writel(mask, pio + PIO_IDR);
228 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
229 __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
230 __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
231 __raw_writel(mask, pio + PIO_PDR);
232 return 0;
233}
234EXPORT_SYMBOL(at91_set_C_periph);
235
236
237/*
238 * mux the pin to the "D" internal peripheral role.
239 */
240int __init_or_module at91_set_D_periph(unsigned pin, int use_pullup)
241{
242 void __iomem *pio = pin_to_controller(pin);
243 unsigned mask = pin_to_mask(pin);
244
245 if (!pio || !has_pio3())
246 return -EINVAL;
247
248 __raw_writel(mask, pio + PIO_IDR);
249 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
250 __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
251 __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
252 __raw_writel(mask, pio + PIO_PDR);
253 return 0;
254}
255EXPORT_SYMBOL(at91_set_D_periph);
256
257
258/*
259 * mux the pin to the gpio controller (instead of "A", "B", "C"
260 * or "D" peripheral), and configure it for an input.
261 */
262int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
263{
264 void __iomem *pio = pin_to_controller(pin);
265 unsigned mask = pin_to_mask(pin);
266
267 if (!pio)
268 return -EINVAL;
269
270 __raw_writel(mask, pio + PIO_IDR);
271 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
272 __raw_writel(mask, pio + PIO_ODR);
273 __raw_writel(mask, pio + PIO_PER);
274 return 0;
275}
276EXPORT_SYMBOL(at91_set_gpio_input);
277
278
279/*
280 * mux the pin to the gpio controller (instead of "A", "B", "C"
281 * or "D" peripheral), and configure it for an output.
282 */
283int __init_or_module at91_set_gpio_output(unsigned pin, int value)
284{
285 void __iomem *pio = pin_to_controller(pin);
286 unsigned mask = pin_to_mask(pin);
287
288 if (!pio)
289 return -EINVAL;
290
291 __raw_writel(mask, pio + PIO_IDR);
292 __raw_writel(mask, pio + PIO_PUDR);
293 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
294 __raw_writel(mask, pio + PIO_OER);
295 __raw_writel(mask, pio + PIO_PER);
296 return 0;
297}
298EXPORT_SYMBOL(at91_set_gpio_output);
299
300
301/*
302 * enable/disable the glitch filter; mostly used with IRQ handling.
303 */
304int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
305{
306 void __iomem *pio = pin_to_controller(pin);
307 unsigned mask = pin_to_mask(pin);
308
309 if (!pio)
310 return -EINVAL;
311
312 if (has_pio3() && is_on)
313 __raw_writel(mask, pio + PIO_IFSCDR);
314 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
315 return 0;
316}
317EXPORT_SYMBOL(at91_set_deglitch);
318
319/*
320 * enable/disable the debounce filter;
321 */
322int __init_or_module at91_set_debounce(unsigned pin, int is_on, int div)
323{
324 void __iomem *pio = pin_to_controller(pin);
325 unsigned mask = pin_to_mask(pin);
326
327 if (!pio || !has_pio3())
328 return -EINVAL;
329
330 if (is_on) {
331 __raw_writel(mask, pio + PIO_IFSCER);
332 __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
333 __raw_writel(mask, pio + PIO_IFER);
334 } else {
335 __raw_writel(mask, pio + PIO_IFDR);
336 }
337 return 0;
338}
339EXPORT_SYMBOL(at91_set_debounce);
340
341/*
342 * enable/disable the multi-driver; This is only valid for output and
343 * allows the output pin to run as an open collector output.
344 */
345int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
346{
347 void __iomem *pio = pin_to_controller(pin);
348 unsigned mask = pin_to_mask(pin);
349
350 if (!pio)
351 return -EINVAL;
352
353 __raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
354 return 0;
355}
356EXPORT_SYMBOL(at91_set_multi_drive);
357
358/*
359 * enable/disable the pull-down.
360 * If pull-up already enabled while calling the function, we disable it.
361 */
362int __init_or_module at91_set_pulldown(unsigned pin, int is_on)
363{
364 void __iomem *pio = pin_to_controller(pin);
365 unsigned mask = pin_to_mask(pin);
366
367 if (!pio || !has_pio3())
368 return -EINVAL;
369
370 /* Disable pull-up anyway */
371 __raw_writel(mask, pio + PIO_PUDR);
372 __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
373 return 0;
374}
375EXPORT_SYMBOL(at91_set_pulldown);
376
377/*
378 * disable Schmitt trigger
379 */
380int __init_or_module at91_disable_schmitt_trig(unsigned pin)
381{
382 void __iomem *pio = pin_to_controller(pin);
383 unsigned mask = pin_to_mask(pin);
384
385 if (!pio || !has_pio3())
386 return -EINVAL;
387
388 __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
389 return 0;
390}
391EXPORT_SYMBOL(at91_disable_schmitt_trig);
392
393/*
394 * assuming the pin is muxed as a gpio output, set its value.
395 */
396int at91_set_gpio_value(unsigned pin, int value)
397{
398 void __iomem *pio = pin_to_controller(pin);
399 unsigned mask = pin_to_mask(pin);
400
401 if (!pio)
402 return -EINVAL;
403 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
404 return 0;
405}
406EXPORT_SYMBOL(at91_set_gpio_value);
407
408
409/*
410 * read the pin's value (works even if it's not muxed as a gpio).
411 */
412int at91_get_gpio_value(unsigned pin)
413{
414 void __iomem *pio = pin_to_controller(pin);
415 unsigned mask = pin_to_mask(pin);
416 u32 pdsr;
417
418 if (!pio)
419 return -EINVAL;
420 pdsr = __raw_readl(pio + PIO_PDSR);
421 return (pdsr & mask) != 0;
422}
423EXPORT_SYMBOL(at91_get_gpio_value);
424
425/*--------------------------------------------------------------------------*/
426
427#ifdef CONFIG_PM
428
429static u32 wakeups[MAX_GPIO_BANKS];
430static u32 backups[MAX_GPIO_BANKS];
431
432static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
433{
434 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
435 unsigned mask = 1 << d->hwirq;
436 unsigned bank = at91_gpio->pioc_idx;
437
438 if (unlikely(bank >= MAX_GPIO_BANKS))
439 return -EINVAL;
440
441 if (state)
442 wakeups[bank] |= mask;
443 else
444 wakeups[bank] &= ~mask;
445
446 irq_set_irq_wake(at91_gpio->pioc_virq, state);
447
448 return 0;
449}
450
451void at91_gpio_suspend(void)
452{
453 int i;
454
455 for (i = 0; i < gpio_banks; i++) {
456 void __iomem *pio = gpio_chip[i].regbase;
457
458 backups[i] = __raw_readl(pio + PIO_IMR);
459 __raw_writel(backups[i], pio + PIO_IDR);
460 __raw_writel(wakeups[i], pio + PIO_IER);
461
462 if (!wakeups[i]) {
463 clk_unprepare(gpio_chip[i].clock);
464 clk_disable(gpio_chip[i].clock);
465 } else {
466#ifdef CONFIG_PM_DEBUG
467 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]);
468#endif
469 }
470 }
471}
472
473void at91_gpio_resume(void)
474{
475 int i;
476
477 for (i = 0; i < gpio_banks; i++) {
478 void __iomem *pio = gpio_chip[i].regbase;
479
480 if (!wakeups[i]) {
481 if (clk_prepare(gpio_chip[i].clock) == 0)
482 clk_enable(gpio_chip[i].clock);
483 }
484
485 __raw_writel(wakeups[i], pio + PIO_IDR);
486 __raw_writel(backups[i], pio + PIO_IER);
487 }
488}
489
490#else
491#define gpio_irq_set_wake NULL
492#endif
493
494
495/* Several AIC controller irqs are dispatched through this GPIO handler.
496 * To use any AT91_PIN_* as an externally triggered IRQ, first call
497 * at91_set_gpio_input() then maybe enable its glitch filter.
498 * Then just request_irq() with the pin ID; it works like any ARM IRQ
499 * handler.
500 * First implementation always triggers on rising and falling edges
501 * whereas the newer PIO3 can be additionally configured to trigger on
502 * level, edge with any polarity.
503 *
504 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
505 * configuring them with at91_set_a_periph() or at91_set_b_periph().
506 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
507 */
508
509static void gpio_irq_mask(struct irq_data *d)
510{
511 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
512 void __iomem *pio = at91_gpio->regbase;
513 unsigned mask = 1 << d->hwirq;
514
515 if (pio)
516 __raw_writel(mask, pio + PIO_IDR);
517}
518
519static void gpio_irq_unmask(struct irq_data *d)
520{
521 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
522 void __iomem *pio = at91_gpio->regbase;
523 unsigned mask = 1 << d->hwirq;
524
525 if (pio)
526 __raw_writel(mask, pio + PIO_IER);
527}
528
529static int gpio_irq_type(struct irq_data *d, unsigned type)
530{
531 switch (type) {
532 case IRQ_TYPE_NONE:
533 case IRQ_TYPE_EDGE_BOTH:
534 return 0;
535 default:
536 return -EINVAL;
537 }
538}
539
540/* Alternate irq type for PIO3 support */
541static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
542{
543 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
544 void __iomem *pio = at91_gpio->regbase;
545 unsigned mask = 1 << d->hwirq;
546
547 switch (type) {
548 case IRQ_TYPE_EDGE_RISING:
549 __raw_writel(mask, pio + PIO_ESR);
550 __raw_writel(mask, pio + PIO_REHLSR);
551 break;
552 case IRQ_TYPE_EDGE_FALLING:
553 __raw_writel(mask, pio + PIO_ESR);
554 __raw_writel(mask, pio + PIO_FELLSR);
555 break;
556 case IRQ_TYPE_LEVEL_LOW:
557 __raw_writel(mask, pio + PIO_LSR);
558 __raw_writel(mask, pio + PIO_FELLSR);
559 break;
560 case IRQ_TYPE_LEVEL_HIGH:
561 __raw_writel(mask, pio + PIO_LSR);
562 __raw_writel(mask, pio + PIO_REHLSR);
563 break;
564 case IRQ_TYPE_EDGE_BOTH:
565 /*
566 * disable additional interrupt modes:
567 * fall back to default behavior
568 */
569 __raw_writel(mask, pio + PIO_AIMDR);
570 return 0;
571 case IRQ_TYPE_NONE:
572 default:
573 pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
574 return -EINVAL;
575 }
576
577 /* enable additional interrupt modes */
578 __raw_writel(mask, pio + PIO_AIMER);
579
580 return 0;
581}
582
583static struct irq_chip gpio_irqchip = {
584 .name = "GPIO",
585 .irq_disable = gpio_irq_mask,
586 .irq_mask = gpio_irq_mask,
587 .irq_unmask = gpio_irq_unmask,
588 /* .irq_set_type is set dynamically */
589 .irq_set_wake = gpio_irq_set_wake,
590};
591
592static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
593{
594 struct irq_chip *chip = irq_desc_get_chip(desc);
595 struct irq_data *idata = irq_desc_get_irq_data(desc);
596 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
597 void __iomem *pio = at91_gpio->regbase;
598 unsigned long isr;
599 int n;
600
601 chained_irq_enter(chip, desc);
602 for (;;) {
603 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
604 * When there none are pending, we're finished unless we need
605 * to process multiple banks (like ID_PIOCDE on sam9263).
606 */
607 isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
608 if (!isr) {
609 if (!at91_gpio->next)
610 break;
611 at91_gpio = at91_gpio->next;
612 pio = at91_gpio->regbase;
613 continue;
614 }
615
616 n = find_first_bit(&isr, BITS_PER_LONG);
617 while (n < BITS_PER_LONG) {
618 generic_handle_irq(irq_find_mapping(at91_gpio->domain, n));
619 n = find_next_bit(&isr, BITS_PER_LONG, n + 1);
620 }
621 }
622 chained_irq_exit(chip, desc);
623 /* now it may re-trigger */
624}
625
626/*--------------------------------------------------------------------------*/
627
628#ifdef CONFIG_DEBUG_FS
629
630static void gpio_printf(struct seq_file *s, void __iomem *pio, unsigned mask)
631{
632 char *trigger = NULL;
633 char *polarity = NULL;
634
635 if (__raw_readl(pio + PIO_IMR) & mask) {
636 if (!has_pio3() || !(__raw_readl(pio + PIO_AIMMR) & mask )) {
637 trigger = "edge";
638 polarity = "both";
639 } else {
640 if (__raw_readl(pio + PIO_ELSR) & mask) {
641 trigger = "level";
642 polarity = __raw_readl(pio + PIO_FRLHSR) & mask ?
643 "high" : "low";
644 } else {
645 trigger = "edge";
646 polarity = __raw_readl(pio + PIO_FRLHSR) & mask ?
647 "rising" : "falling";
648 }
649 }
650 seq_printf(s, "IRQ:%s-%s\t", trigger, polarity);
651 } else {
652 seq_printf(s, "GPIO:%s\t\t",
653 __raw_readl(pio + PIO_PDSR) & mask ? "1" : "0");
654 }
655}
656
657static int at91_gpio_show(struct seq_file *s, void *unused)
658{
659 int bank, j;
660
661 /* print heading */
662 seq_printf(s, "Pin\t");
663 for (bank = 0; bank < gpio_banks; bank++) {
664 seq_printf(s, "PIO%c\t\t", 'A' + bank);
665 };
666 seq_printf(s, "\n\n");
667
668 /* print pin status */
669 for (j = 0; j < 32; j++) {
670 seq_printf(s, "%i:\t", j);
671
672 for (bank = 0; bank < gpio_banks; bank++) {
673 unsigned pin = (32 * bank) + j;
674 void __iomem *pio = pin_to_controller(pin);
675 unsigned mask = pin_to_mask(pin);
676
677 if (__raw_readl(pio + PIO_PSR) & mask)
678 gpio_printf(s, pio, mask);
679 else
680 seq_printf(s, "%c\t\t",
681 peripheral_function(pio, mask));
682 }
683
684 seq_printf(s, "\n");
685 }
686
687 return 0;
688}
689
690static int at91_gpio_open(struct inode *inode, struct file *file)
691{
692 return single_open(file, at91_gpio_show, NULL);
693}
694
695static const struct file_operations at91_gpio_operations = {
696 .open = at91_gpio_open,
697 .read = seq_read,
698 .llseek = seq_lseek,
699 .release = single_release,
700};
701
702static int __init at91_gpio_debugfs_init(void)
703{
704 /* /sys/kernel/debug/at91_gpio */
705 (void) debugfs_create_file("at91_gpio", S_IFREG | S_IRUGO, NULL, NULL, &at91_gpio_operations);
706 return 0;
707}
708postcore_initcall(at91_gpio_debugfs_init);
709
710#endif
711
712/*--------------------------------------------------------------------------*/
713
714/*
715 * This lock class tells lockdep that GPIO irqs are in a different
716 * category than their parents, so it won't report false recursion.
717 */
718static struct lock_class_key gpio_lock_class;
719
720/*
721 * irqdomain initialization: pile up irqdomains on top of AIC range
722 */
723static void __init at91_gpio_irqdomain(struct at91_gpio_chip *at91_gpio)
724{
725 int irq_base;
726
727 irq_base = irq_alloc_descs(-1, 0, at91_gpio->chip.ngpio, 0);
728 if (irq_base < 0)
729 panic("at91_gpio.%d: error %d: couldn't allocate IRQ numbers.\n",
730 at91_gpio->pioc_idx, irq_base);
731 at91_gpio->domain = irq_domain_add_legacy(NULL, at91_gpio->chip.ngpio,
732 irq_base, 0,
733 &irq_domain_simple_ops, NULL);
734 if (!at91_gpio->domain)
735 panic("at91_gpio.%d: couldn't allocate irq domain.\n",
736 at91_gpio->pioc_idx);
737}
738
739/*
740 * Called from the processor-specific init to enable GPIO interrupt support.
741 */
742void __init at91_gpio_irq_setup(void)
743{
744 unsigned pioc;
745 int gpio_irqnbr = 0;
746 struct at91_gpio_chip *this, *prev;
747
748 /* Setup proper .irq_set_type function */
749 if (has_pio3())
750 gpio_irqchip.irq_set_type = alt_gpio_irq_type;
751 else
752 gpio_irqchip.irq_set_type = gpio_irq_type;
753
754 for (pioc = 0, this = gpio_chip, prev = NULL;
755 pioc++ < gpio_banks;
756 prev = this, this++) {
757 int offset;
758
759 __raw_writel(~0, this->regbase + PIO_IDR);
760
761 /* setup irq domain for this GPIO controller */
762 at91_gpio_irqdomain(this);
763
764 for (offset = 0; offset < this->chip.ngpio; offset++) {
765 unsigned int virq = irq_find_mapping(this->domain, offset);
766 irq_set_lockdep_class(virq, &gpio_lock_class);
767
768 /*
769 * Can use the "simple" and not "edge" handler since it's
770 * shorter, and the AIC handles interrupts sanely.
771 */
772 irq_set_chip_and_handler(virq, &gpio_irqchip,
773 handle_simple_irq);
774 set_irq_flags(virq, IRQF_VALID);
775 irq_set_chip_data(virq, this);
776
777 gpio_irqnbr++;
778 }
779
780 /* The toplevel handler handles one bank of GPIOs, except
781 * on some SoC it can handles up to three...
782 * We only set up the handler for the first of the list.
783 */
784 if (prev && prev->next == this)
785 continue;
786
787 this->pioc_virq = irq_create_mapping(NULL, this->pioc_hwirq);
788 irq_set_chip_data(this->pioc_virq, this);
789 irq_set_chained_handler(this->pioc_virq, gpio_irq_handler);
790 }
791 pr_info("AT91: %d gpio irqs in %d banks\n", gpio_irqnbr, gpio_banks);
792}
793
794/* gpiolib support */
795static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset)
796{
797 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
798 void __iomem *pio = at91_gpio->regbase;
799 unsigned mask = 1 << offset;
800
801 __raw_writel(mask, pio + PIO_PER);
802 return 0;
803}
804
805static int at91_gpiolib_get_direction(struct gpio_chip *chip, unsigned offset)
806{
807 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
808 void __iomem *pio = at91_gpio->regbase;
809 unsigned mask = 1 << offset;
810 u32 osr;
811
812 osr = __raw_readl(pio + PIO_OSR);
813 return !(osr & mask);
814}
815
816static int at91_gpiolib_direction_input(struct gpio_chip *chip,
817 unsigned offset)
818{
819 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
820 void __iomem *pio = at91_gpio->regbase;
821 unsigned mask = 1 << offset;
822
823 __raw_writel(mask, pio + PIO_ODR);
824 return 0;
825}
826
827static int at91_gpiolib_direction_output(struct gpio_chip *chip,
828 unsigned offset, int val)
829{
830 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
831 void __iomem *pio = at91_gpio->regbase;
832 unsigned mask = 1 << offset;
833
834 __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
835 __raw_writel(mask, pio + PIO_OER);
836 return 0;
837}
838
839static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset)
840{
841 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
842 void __iomem *pio = at91_gpio->regbase;
843 unsigned mask = 1 << offset;
844 u32 pdsr;
845
846 pdsr = __raw_readl(pio + PIO_PDSR);
847 return (pdsr & mask) != 0;
848}
849
850static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
851{
852 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
853 void __iomem *pio = at91_gpio->regbase;
854 unsigned mask = 1 << offset;
855
856 __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
857}
858
859static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
860{
861 int i;
862
863 for (i = 0; i < chip->ngpio; i++) {
864 unsigned pin = chip->base + i;
865 void __iomem *pio = pin_to_controller(pin);
866 unsigned mask = pin_to_mask(pin);
867 const char *gpio_label;
868
869 gpio_label = gpiochip_is_requested(chip, i);
870 if (gpio_label) {
871 seq_printf(s, "[%s] GPIO%s%d: ",
872 gpio_label, chip->label, i);
873 if (__raw_readl(pio + PIO_PSR) & mask)
874 seq_printf(s, "[gpio] %s\n",
875 at91_get_gpio_value(pin) ?
876 "set" : "clear");
877 else
878 seq_printf(s, "[periph %c]\n",
879 peripheral_function(pio, mask));
880 }
881 }
882}
883
884static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset)
885{
886 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
887 int virq;
888
889 if (offset < chip->ngpio)
890 virq = irq_create_mapping(at91_gpio->domain, offset);
891 else
892 virq = -ENXIO;
893
894 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
895 chip->label, offset + chip->base, virq);
896 return virq;
897}
898
899static int __init at91_gpio_setup_clk(int idx)
900{
901 struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
902
903 /* retreive PIO controller's clock */
904 at91_gpio->clock = clk_get_sys(NULL, at91_gpio->chip.label);
905 if (IS_ERR(at91_gpio->clock)) {
906 pr_err("at91_gpio.%d, failed to get clock, ignoring.\n", idx);
907 goto err;
908 }
909
910 if (clk_prepare(at91_gpio->clock))
911 goto clk_prep_err;
912
913 /* enable PIO controller's clock */
914 if (clk_enable(at91_gpio->clock)) {
915 pr_err("at91_gpio.%d, failed to enable clock, ignoring.\n", idx);
916 goto clk_err;
917 }
918
919 return 0;
920
921clk_err:
922 clk_unprepare(at91_gpio->clock);
923clk_prep_err:
924 clk_put(at91_gpio->clock);
925err:
926 return -EINVAL;
927}
928
929static void __init at91_gpio_init_one(int idx, u32 regbase, int pioc_hwirq)
930{
931 struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
932
933 at91_gpio->chip.base = idx * MAX_NB_GPIO_PER_BANK;
934 at91_gpio->pioc_hwirq = pioc_hwirq;
935 at91_gpio->pioc_idx = idx;
936
937 at91_gpio->regbase = ioremap(regbase, 512);
938 if (!at91_gpio->regbase) {
939 pr_err("at91_gpio.%d, failed to map registers, ignoring.\n", idx);
940 return;
941 }
942
943 if (at91_gpio_setup_clk(idx))
944 goto ioremap_err;
945
946 gpio_banks = max(gpio_banks, idx + 1);
947 return;
948
949ioremap_err:
950 iounmap(at91_gpio->regbase);
951}
952
953/*
954 * Called from the processor-specific init to enable GPIO pin support.
955 */
956void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
957{
958 unsigned i;
959 struct at91_gpio_chip *at91_gpio, *last = NULL;
960
961 BUG_ON(nr_banks > MAX_GPIO_BANKS);
962
963 if (of_have_populated_dt())
964 return;
965
966 for (i = 0; i < nr_banks; i++)
967 at91_gpio_init_one(i, data[i].regbase, data[i].id);
968
969 for (i = 0; i < gpio_banks; i++) {
970 at91_gpio = &gpio_chip[i];
971
972 /*
973 * GPIO controller are grouped on some SoC:
974 * PIOC, PIOD and PIOE can share the same IRQ line
975 */
976 if (last && last->pioc_hwirq == at91_gpio->pioc_hwirq)
977 last->next = at91_gpio;
978 last = at91_gpio;
979
980 gpiochip_add(&at91_gpio->chip);
981 }
982}
diff --git a/arch/arm/mach-at91/gpio.h b/arch/arm/mach-at91/gpio.h
deleted file mode 100644
index eed465ab0dd7..000000000000
--- a/arch/arm/mach-at91/gpio.h
+++ /dev/null
@@ -1,214 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/gpio.h
3 *
4 * Copyright (C) 2005 HP Labs
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13#ifndef __ASM_ARCH_AT91RM9200_GPIO_H
14#define __ASM_ARCH_AT91RM9200_GPIO_H
15
16#include <linux/kernel.h>
17#include <asm/irq.h>
18
19#define MAX_GPIO_BANKS 5
20#define NR_BUILTIN_GPIO (MAX_GPIO_BANKS * 32)
21
22/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
23
24#define AT91_PIN_PA0 (0x00 + 0)
25#define AT91_PIN_PA1 (0x00 + 1)
26#define AT91_PIN_PA2 (0x00 + 2)
27#define AT91_PIN_PA3 (0x00 + 3)
28#define AT91_PIN_PA4 (0x00 + 4)
29#define AT91_PIN_PA5 (0x00 + 5)
30#define AT91_PIN_PA6 (0x00 + 6)
31#define AT91_PIN_PA7 (0x00 + 7)
32#define AT91_PIN_PA8 (0x00 + 8)
33#define AT91_PIN_PA9 (0x00 + 9)
34#define AT91_PIN_PA10 (0x00 + 10)
35#define AT91_PIN_PA11 (0x00 + 11)
36#define AT91_PIN_PA12 (0x00 + 12)
37#define AT91_PIN_PA13 (0x00 + 13)
38#define AT91_PIN_PA14 (0x00 + 14)
39#define AT91_PIN_PA15 (0x00 + 15)
40#define AT91_PIN_PA16 (0x00 + 16)
41#define AT91_PIN_PA17 (0x00 + 17)
42#define AT91_PIN_PA18 (0x00 + 18)
43#define AT91_PIN_PA19 (0x00 + 19)
44#define AT91_PIN_PA20 (0x00 + 20)
45#define AT91_PIN_PA21 (0x00 + 21)
46#define AT91_PIN_PA22 (0x00 + 22)
47#define AT91_PIN_PA23 (0x00 + 23)
48#define AT91_PIN_PA24 (0x00 + 24)
49#define AT91_PIN_PA25 (0x00 + 25)
50#define AT91_PIN_PA26 (0x00 + 26)
51#define AT91_PIN_PA27 (0x00 + 27)
52#define AT91_PIN_PA28 (0x00 + 28)
53#define AT91_PIN_PA29 (0x00 + 29)
54#define AT91_PIN_PA30 (0x00 + 30)
55#define AT91_PIN_PA31 (0x00 + 31)
56
57#define AT91_PIN_PB0 (0x20 + 0)
58#define AT91_PIN_PB1 (0x20 + 1)
59#define AT91_PIN_PB2 (0x20 + 2)
60#define AT91_PIN_PB3 (0x20 + 3)
61#define AT91_PIN_PB4 (0x20 + 4)
62#define AT91_PIN_PB5 (0x20 + 5)
63#define AT91_PIN_PB6 (0x20 + 6)
64#define AT91_PIN_PB7 (0x20 + 7)
65#define AT91_PIN_PB8 (0x20 + 8)
66#define AT91_PIN_PB9 (0x20 + 9)
67#define AT91_PIN_PB10 (0x20 + 10)
68#define AT91_PIN_PB11 (0x20 + 11)
69#define AT91_PIN_PB12 (0x20 + 12)
70#define AT91_PIN_PB13 (0x20 + 13)
71#define AT91_PIN_PB14 (0x20 + 14)
72#define AT91_PIN_PB15 (0x20 + 15)
73#define AT91_PIN_PB16 (0x20 + 16)
74#define AT91_PIN_PB17 (0x20 + 17)
75#define AT91_PIN_PB18 (0x20 + 18)
76#define AT91_PIN_PB19 (0x20 + 19)
77#define AT91_PIN_PB20 (0x20 + 20)
78#define AT91_PIN_PB21 (0x20 + 21)
79#define AT91_PIN_PB22 (0x20 + 22)
80#define AT91_PIN_PB23 (0x20 + 23)
81#define AT91_PIN_PB24 (0x20 + 24)
82#define AT91_PIN_PB25 (0x20 + 25)
83#define AT91_PIN_PB26 (0x20 + 26)
84#define AT91_PIN_PB27 (0x20 + 27)
85#define AT91_PIN_PB28 (0x20 + 28)
86#define AT91_PIN_PB29 (0x20 + 29)
87#define AT91_PIN_PB30 (0x20 + 30)
88#define AT91_PIN_PB31 (0x20 + 31)
89
90#define AT91_PIN_PC0 (0x40 + 0)
91#define AT91_PIN_PC1 (0x40 + 1)
92#define AT91_PIN_PC2 (0x40 + 2)
93#define AT91_PIN_PC3 (0x40 + 3)
94#define AT91_PIN_PC4 (0x40 + 4)
95#define AT91_PIN_PC5 (0x40 + 5)
96#define AT91_PIN_PC6 (0x40 + 6)
97#define AT91_PIN_PC7 (0x40 + 7)
98#define AT91_PIN_PC8 (0x40 + 8)
99#define AT91_PIN_PC9 (0x40 + 9)
100#define AT91_PIN_PC10 (0x40 + 10)
101#define AT91_PIN_PC11 (0x40 + 11)
102#define AT91_PIN_PC12 (0x40 + 12)
103#define AT91_PIN_PC13 (0x40 + 13)
104#define AT91_PIN_PC14 (0x40 + 14)
105#define AT91_PIN_PC15 (0x40 + 15)
106#define AT91_PIN_PC16 (0x40 + 16)
107#define AT91_PIN_PC17 (0x40 + 17)
108#define AT91_PIN_PC18 (0x40 + 18)
109#define AT91_PIN_PC19 (0x40 + 19)
110#define AT91_PIN_PC20 (0x40 + 20)
111#define AT91_PIN_PC21 (0x40 + 21)
112#define AT91_PIN_PC22 (0x40 + 22)
113#define AT91_PIN_PC23 (0x40 + 23)
114#define AT91_PIN_PC24 (0x40 + 24)
115#define AT91_PIN_PC25 (0x40 + 25)
116#define AT91_PIN_PC26 (0x40 + 26)
117#define AT91_PIN_PC27 (0x40 + 27)
118#define AT91_PIN_PC28 (0x40 + 28)
119#define AT91_PIN_PC29 (0x40 + 29)
120#define AT91_PIN_PC30 (0x40 + 30)
121#define AT91_PIN_PC31 (0x40 + 31)
122
123#define AT91_PIN_PD0 (0x60 + 0)
124#define AT91_PIN_PD1 (0x60 + 1)
125#define AT91_PIN_PD2 (0x60 + 2)
126#define AT91_PIN_PD3 (0x60 + 3)
127#define AT91_PIN_PD4 (0x60 + 4)
128#define AT91_PIN_PD5 (0x60 + 5)
129#define AT91_PIN_PD6 (0x60 + 6)
130#define AT91_PIN_PD7 (0x60 + 7)
131#define AT91_PIN_PD8 (0x60 + 8)
132#define AT91_PIN_PD9 (0x60 + 9)
133#define AT91_PIN_PD10 (0x60 + 10)
134#define AT91_PIN_PD11 (0x60 + 11)
135#define AT91_PIN_PD12 (0x60 + 12)
136#define AT91_PIN_PD13 (0x60 + 13)
137#define AT91_PIN_PD14 (0x60 + 14)
138#define AT91_PIN_PD15 (0x60 + 15)
139#define AT91_PIN_PD16 (0x60 + 16)
140#define AT91_PIN_PD17 (0x60 + 17)
141#define AT91_PIN_PD18 (0x60 + 18)
142#define AT91_PIN_PD19 (0x60 + 19)
143#define AT91_PIN_PD20 (0x60 + 20)
144#define AT91_PIN_PD21 (0x60 + 21)
145#define AT91_PIN_PD22 (0x60 + 22)
146#define AT91_PIN_PD23 (0x60 + 23)
147#define AT91_PIN_PD24 (0x60 + 24)
148#define AT91_PIN_PD25 (0x60 + 25)
149#define AT91_PIN_PD26 (0x60 + 26)
150#define AT91_PIN_PD27 (0x60 + 27)
151#define AT91_PIN_PD28 (0x60 + 28)
152#define AT91_PIN_PD29 (0x60 + 29)
153#define AT91_PIN_PD30 (0x60 + 30)
154#define AT91_PIN_PD31 (0x60 + 31)
155
156#define AT91_PIN_PE0 (0x80 + 0)
157#define AT91_PIN_PE1 (0x80 + 1)
158#define AT91_PIN_PE2 (0x80 + 2)
159#define AT91_PIN_PE3 (0x80 + 3)
160#define AT91_PIN_PE4 (0x80 + 4)
161#define AT91_PIN_PE5 (0x80 + 5)
162#define AT91_PIN_PE6 (0x80 + 6)
163#define AT91_PIN_PE7 (0x80 + 7)
164#define AT91_PIN_PE8 (0x80 + 8)
165#define AT91_PIN_PE9 (0x80 + 9)
166#define AT91_PIN_PE10 (0x80 + 10)
167#define AT91_PIN_PE11 (0x80 + 11)
168#define AT91_PIN_PE12 (0x80 + 12)
169#define AT91_PIN_PE13 (0x80 + 13)
170#define AT91_PIN_PE14 (0x80 + 14)
171#define AT91_PIN_PE15 (0x80 + 15)
172#define AT91_PIN_PE16 (0x80 + 16)
173#define AT91_PIN_PE17 (0x80 + 17)
174#define AT91_PIN_PE18 (0x80 + 18)
175#define AT91_PIN_PE19 (0x80 + 19)
176#define AT91_PIN_PE20 (0x80 + 20)
177#define AT91_PIN_PE21 (0x80 + 21)
178#define AT91_PIN_PE22 (0x80 + 22)
179#define AT91_PIN_PE23 (0x80 + 23)
180#define AT91_PIN_PE24 (0x80 + 24)
181#define AT91_PIN_PE25 (0x80 + 25)
182#define AT91_PIN_PE26 (0x80 + 26)
183#define AT91_PIN_PE27 (0x80 + 27)
184#define AT91_PIN_PE28 (0x80 + 28)
185#define AT91_PIN_PE29 (0x80 + 29)
186#define AT91_PIN_PE30 (0x80 + 30)
187#define AT91_PIN_PE31 (0x80 + 31)
188
189#ifndef __ASSEMBLY__
190/* setup setup routines, called from board init or driver probe() */
191extern int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup);
192extern int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup);
193extern int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup);
194extern int __init_or_module at91_set_C_periph(unsigned pin, int use_pullup);
195extern int __init_or_module at91_set_D_periph(unsigned pin, int use_pullup);
196extern int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup);
197extern int __init_or_module at91_set_gpio_output(unsigned pin, int value);
198extern int __init_or_module at91_set_deglitch(unsigned pin, int is_on);
199extern int __init_or_module at91_set_debounce(unsigned pin, int is_on, int div);
200extern int __init_or_module at91_set_multi_drive(unsigned pin, int is_on);
201extern int __init_or_module at91_set_pulldown(unsigned pin, int is_on);
202extern int __init_or_module at91_disable_schmitt_trig(unsigned pin);
203
204/* callable at any time */
205extern int at91_set_gpio_value(unsigned pin, int value);
206extern int at91_get_gpio_value(unsigned pin);
207
208/* callable only from core power-management code */
209extern void at91_gpio_suspend(void);
210extern void at91_gpio_resume(void);
211
212#endif /* __ASSEMBLY__ */
213
214#endif
diff --git a/arch/arm/mach-at91/gsia18s.h b/arch/arm/mach-at91/gsia18s.h
deleted file mode 100644
index 307c194926f9..000000000000
--- a/arch/arm/mach-at91/gsia18s.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/* Buttons */
2#define GPIO_TRIG_NET_IN AT91_PIN_PB21
3#define GPIO_CARD_UNMOUNT_0 AT91_PIN_PB13
4#define GPIO_CARD_UNMOUNT_1 AT91_PIN_PB12
5#define GPIO_KEY_POWER AT91_PIN_PA25
6
7/* PCF8574 0x20 GPIO - U1 on the GS_IA18-CB_V3 board */
8#define GS_IA18_S_PCF_GPIO_BASE0 NR_BUILTIN_GPIO
9#define PCF_GPIO_HDC_POWER (GS_IA18_S_PCF_GPIO_BASE0 + 0)
10#define PCF_GPIO_WIFI_SETUP (GS_IA18_S_PCF_GPIO_BASE0 + 1)
11#define PCF_GPIO_WIFI_ENABLE (GS_IA18_S_PCF_GPIO_BASE0 + 2)
12#define PCF_GPIO_WIFI_RESET (GS_IA18_S_PCF_GPIO_BASE0 + 3)
13#define PCF_GPIO_ETH_DETECT 4 /* this is a GPI */
14#define PCF_GPIO_GPS_SETUP (GS_IA18_S_PCF_GPIO_BASE0 + 5)
15#define PCF_GPIO_GPS_STANDBY (GS_IA18_S_PCF_GPIO_BASE0 + 6)
16#define PCF_GPIO_GPS_POWER (GS_IA18_S_PCF_GPIO_BASE0 + 7)
17
18/* PCF8574 0x22 GPIO - U1 on the GS_2G_OPT1-A_V0 board (Alarm) */
19#define GS_IA18_S_PCF_GPIO_BASE1 (GS_IA18_S_PCF_GPIO_BASE0 + 8)
20#define PCF_GPIO_ALARM1 (GS_IA18_S_PCF_GPIO_BASE1 + 0)
21#define PCF_GPIO_ALARM2 (GS_IA18_S_PCF_GPIO_BASE1 + 1)
22#define PCF_GPIO_ALARM3 (GS_IA18_S_PCF_GPIO_BASE1 + 2)
23#define PCF_GPIO_ALARM4 (GS_IA18_S_PCF_GPIO_BASE1 + 3)
24/* bits 4, 5, 6 not used */
25#define PCF_GPIO_ALARM_V_RELAY_ON (GS_IA18_S_PCF_GPIO_BASE1 + 7)
26
27/* PCF8574 0x24 GPIO U1 on the GS_2G-OPT23-A_V0 board (Modem) */
28#define GS_IA18_S_PCF_GPIO_BASE2 (GS_IA18_S_PCF_GPIO_BASE1 + 8)
29#define PCF_GPIO_MODEM_POWER (GS_IA18_S_PCF_GPIO_BASE2 + 0)
30#define PCF_GPIO_MODEM_RESET (GS_IA18_S_PCF_GPIO_BASE2 + 3)
31/* bits 1, 2, 4, 5 not used */
32#define PCF_GPIO_TRX_RESET (GS_IA18_S_PCF_GPIO_BASE2 + 6)
33/* bit 7 not used */
diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach/at91_dbgu.h
index 3b5948566e52..42925e8f78e4 100644
--- a/arch/arm/mach-at91/include/mach/at91_dbgu.h
+++ b/arch/arm/mach-at91/include/mach/at91_dbgu.h
@@ -16,7 +16,6 @@
16#ifndef AT91_DBGU_H 16#ifndef AT91_DBGU_H
17#define AT91_DBGU_H 17#define AT91_DBGU_H
18 18
19#if !defined(CONFIG_ARCH_AT91X40)
20#define AT91_DBGU_CR (0x00) /* Control Register */ 19#define AT91_DBGU_CR (0x00) /* Control Register */
21#define AT91_DBGU_MR (0x04) /* Mode Register */ 20#define AT91_DBGU_MR (0x04) /* Mode Register */
22#define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */ 21#define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */
@@ -34,8 +33,6 @@
34#define AT91_DBGU_FNR (0x48) /* Force NTRST Register [SAM9 only] */ 33#define AT91_DBGU_FNR (0x48) /* Force NTRST Register [SAM9 only] */
35#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ 34#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */
36 35
37#endif /* AT91_DBGU */
38
39/* 36/*
40 * Some AT91 parts that don't have full DEBUG units still support the ID 37 * Some AT91 parts that don't have full DEBUG units still support the ID
41 * and extensions register. 38 * and extensions register.
diff --git a/arch/arm/mach-at91/include/mach/at91_ramc.h b/arch/arm/mach-at91/include/mach/at91_ramc.h
index d8aeb278614e..e4492b151fee 100644
--- a/arch/arm/mach-at91/include/mach/at91_ramc.h
+++ b/arch/arm/mach-at91/include/mach/at91_ramc.h
@@ -25,8 +25,8 @@ extern void __iomem *at91_ramc_base[];
25#define AT91_MEMCTRL_SDRAMC 1 25#define AT91_MEMCTRL_SDRAMC 1
26#define AT91_MEMCTRL_DDRSDR 2 26#define AT91_MEMCTRL_DDRSDR 2
27 27
28#include <mach/at91rm9200_sdramc.h> 28#include <soc/at91/at91rm9200_sdramc.h>
29#include <mach/at91sam9_ddrsdr.h> 29#include <soc/at91/at91sam9_ddrsdr.h>
30#include <mach/at91sam9_sdramc.h> 30#include <soc/at91/at91sam9_sdramc.h>
31 31
32#endif /* __AT91_RAMC_H__ */ 32#endif /* __AT91_RAMC_H__ */
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h b/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
deleted file mode 100644
index aa047f458f1b..000000000000
--- a/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Memory Controllers (SDRAMC only) - System peripherals registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91RM9200_SDRAMC_H
17#define AT91RM9200_SDRAMC_H
18
19/* SDRAM Controller registers */
20#define AT91RM9200_SDRAMC_MR 0x90 /* Mode Register */
21#define AT91RM9200_SDRAMC_MODE (0xf << 0) /* Command Mode */
22#define AT91RM9200_SDRAMC_MODE_NORMAL (0 << 0)
23#define AT91RM9200_SDRAMC_MODE_NOP (1 << 0)
24#define AT91RM9200_SDRAMC_MODE_PRECHARGE (2 << 0)
25#define AT91RM9200_SDRAMC_MODE_LMR (3 << 0)
26#define AT91RM9200_SDRAMC_MODE_REFRESH (4 << 0)
27#define AT91RM9200_SDRAMC_DBW (1 << 4) /* Data Bus Width */
28#define AT91RM9200_SDRAMC_DBW_32 (0 << 4)
29#define AT91RM9200_SDRAMC_DBW_16 (1 << 4)
30
31#define AT91RM9200_SDRAMC_TR 0x94 /* Refresh Timer Register */
32#define AT91RM9200_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
33
34#define AT91RM9200_SDRAMC_CR 0x98 /* Configuration Register */
35#define AT91RM9200_SDRAMC_NC (3 << 0) /* Number of Column Bits */
36#define AT91RM9200_SDRAMC_NC_8 (0 << 0)
37#define AT91RM9200_SDRAMC_NC_9 (1 << 0)
38#define AT91RM9200_SDRAMC_NC_10 (2 << 0)
39#define AT91RM9200_SDRAMC_NC_11 (3 << 0)
40#define AT91RM9200_SDRAMC_NR (3 << 2) /* Number of Row Bits */
41#define AT91RM9200_SDRAMC_NR_11 (0 << 2)
42#define AT91RM9200_SDRAMC_NR_12 (1 << 2)
43#define AT91RM9200_SDRAMC_NR_13 (2 << 2)
44#define AT91RM9200_SDRAMC_NB (1 << 4) /* Number of Banks */
45#define AT91RM9200_SDRAMC_NB_2 (0 << 4)
46#define AT91RM9200_SDRAMC_NB_4 (1 << 4)
47#define AT91RM9200_SDRAMC_CAS (3 << 5) /* CAS Latency */
48#define AT91RM9200_SDRAMC_CAS_2 (2 << 5)
49#define AT91RM9200_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
50#define AT91RM9200_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
51#define AT91RM9200_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
52#define AT91RM9200_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
53#define AT91RM9200_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
54#define AT91RM9200_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
55
56#define AT91RM9200_SDRAMC_SRR 0x9c /* Self Refresh Register */
57#define AT91RM9200_SDRAMC_LPR 0xa0 /* Low Power Register */
58#define AT91RM9200_SDRAMC_IER 0xa4 /* Interrupt Enable Register */
59#define AT91RM9200_SDRAMC_IDR 0xa8 /* Interrupt Disable Register */
60#define AT91RM9200_SDRAMC_IMR 0xac /* Interrupt Mask Register */
61#define AT91RM9200_SDRAMC_ISR 0xb0 /* Interrupt Status Register */
62
63#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
deleted file mode 100644
index 0210797abf2e..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
+++ /dev/null
@@ -1,124 +0,0 @@
1/*
2 * Header file for the Atmel DDR/SDR SDRAM Controller
3 *
4 * Copyright (C) 2010 Atmel Corporation
5 * Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12#ifndef AT91SAM9_DDRSDR_H
13#define AT91SAM9_DDRSDR_H
14
15#define AT91_DDRSDRC_MR 0x00 /* Mode Register */
16#define AT91_DDRSDRC_MODE (0x7 << 0) /* Command Mode */
17#define AT91_DDRSDRC_MODE_NORMAL 0
18#define AT91_DDRSDRC_MODE_NOP 1
19#define AT91_DDRSDRC_MODE_PRECHARGE 2
20#define AT91_DDRSDRC_MODE_LMR 3
21#define AT91_DDRSDRC_MODE_REFRESH 4
22#define AT91_DDRSDRC_MODE_EXT_LMR 5
23#define AT91_DDRSDRC_MODE_DEEP 6
24
25#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
26#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
27
28#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */
29#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */
30#define AT91_DDRSDRC_NC_SDR8 (0 << 0)
31#define AT91_DDRSDRC_NC_SDR9 (1 << 0)
32#define AT91_DDRSDRC_NC_SDR10 (2 << 0)
33#define AT91_DDRSDRC_NC_SDR11 (3 << 0)
34#define AT91_DDRSDRC_NC_DDR9 (0 << 0)
35#define AT91_DDRSDRC_NC_DDR10 (1 << 0)
36#define AT91_DDRSDRC_NC_DDR11 (2 << 0)
37#define AT91_DDRSDRC_NC_DDR12 (3 << 0)
38#define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */
39#define AT91_DDRSDRC_NR_11 (0 << 2)
40#define AT91_DDRSDRC_NR_12 (1 << 2)
41#define AT91_DDRSDRC_NR_13 (2 << 2)
42#define AT91_DDRSDRC_NR_14 (3 << 2)
43#define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */
44#define AT91_DDRSDRC_CAS_2 (2 << 4)
45#define AT91_DDRSDRC_CAS_3 (3 << 4)
46#define AT91_DDRSDRC_CAS_25 (6 << 4)
47#define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */
48#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
49#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL [SAM9 Only] */
50#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
51#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared [SAM9 Only] */
52#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */
53
54#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
55#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
56#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
57#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
58#define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */
59#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
60#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
61#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
62#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
63#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
64
65#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
66#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */
67#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
68#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
69#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
70
71#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register [SAM9 Only] */
72#define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */
73#define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */
74#define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */
75#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */
76
77#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */
78#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
79#define AT91_DDRSDRC_LPCB_DISABLE 0
80#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
81#define AT91_DDRSDRC_LPCB_POWER_DOWN 2
82#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3
83#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */
84#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */
85#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
86#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */
87#define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
88#define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12)
89#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12)
90#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12)
91#define AT91_DDRSDRC_APDE (1 << 16) /* Active power down exit time */
92#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
93
94#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
95#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
96#define AT91_DDRSDRC_MD_SDR 0
97#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
98#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
99#define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */
100#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */
101#define AT91_DDRSDRC_DBW_32BITS (0 << 4)
102#define AT91_DDRSDRC_DBW_16BITS (1 << 4)
103
104#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */
105#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
106#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
107#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
108#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
109
110#define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */
111#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */
112
113#define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */
114
115#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register [SAM9 Only] */
116#define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */
117#define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */
118#define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */
119
120#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register [SAM9 Only] */
121#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */
122#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */
123
124#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
deleted file mode 100644
index 3d085a9a7450..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
+++ /dev/null
@@ -1,85 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
3 *
4 * Copyright (C) 2007 Andrew Victor
5 * Copyright (C) 2007 Atmel Corporation.
6 *
7 * SDRAM Controllers (SDRAMC) - System peripherals registers.
8 * Based on AT91SAM9261 datasheet revision D.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91SAM9_SDRAMC_H
17#define AT91SAM9_SDRAMC_H
18
19/* SDRAM Controller (SDRAMC) registers */
20#define AT91_SDRAMC_MR 0x00 /* SDRAM Controller Mode Register */
21#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
22#define AT91_SDRAMC_MODE_NORMAL 0
23#define AT91_SDRAMC_MODE_NOP 1
24#define AT91_SDRAMC_MODE_PRECHARGE 2
25#define AT91_SDRAMC_MODE_LMR 3
26#define AT91_SDRAMC_MODE_REFRESH 4
27#define AT91_SDRAMC_MODE_EXT_LMR 5
28#define AT91_SDRAMC_MODE_DEEP 6
29
30#define AT91_SDRAMC_TR 0x04 /* SDRAM Controller Refresh Timer Register */
31#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
32
33#define AT91_SDRAMC_CR 0x08 /* SDRAM Controller Configuration Register */
34#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
35#define AT91_SDRAMC_NC_8 (0 << 0)
36#define AT91_SDRAMC_NC_9 (1 << 0)
37#define AT91_SDRAMC_NC_10 (2 << 0)
38#define AT91_SDRAMC_NC_11 (3 << 0)
39#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
40#define AT91_SDRAMC_NR_11 (0 << 2)
41#define AT91_SDRAMC_NR_12 (1 << 2)
42#define AT91_SDRAMC_NR_13 (2 << 2)
43#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
44#define AT91_SDRAMC_NB_2 (0 << 4)
45#define AT91_SDRAMC_NB_4 (1 << 4)
46#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
47#define AT91_SDRAMC_CAS_1 (1 << 5)
48#define AT91_SDRAMC_CAS_2 (2 << 5)
49#define AT91_SDRAMC_CAS_3 (3 << 5)
50#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */
51#define AT91_SDRAMC_DBW_32 (0 << 7)
52#define AT91_SDRAMC_DBW_16 (1 << 7)
53#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */
54#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */
55#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */
56#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */
57#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
58#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
59
60#define AT91_SDRAMC_LPR 0x10 /* SDRAM Controller Low Power Register */
61#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
62#define AT91_SDRAMC_LPCB_DISABLE 0
63#define AT91_SDRAMC_LPCB_SELF_REFRESH 1
64#define AT91_SDRAMC_LPCB_POWER_DOWN 2
65#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
66#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
67#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
68#define AT91_SDRAMC_DS (3 << 10) /* Drive Strength */
69#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
70#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12)
71#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
72#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
73
74#define AT91_SDRAMC_IER 0x14 /* SDRAM Controller Interrupt Enable Register */
75#define AT91_SDRAMC_IDR 0x18 /* SDRAM Controller Interrupt Disable Register */
76#define AT91_SDRAMC_IMR 0x1C /* SDRAM Controller Interrupt Mask Register */
77#define AT91_SDRAMC_ISR 0x20 /* SDRAM Controller Interrupt Status Register */
78#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
79
80#define AT91_SDRAMC_MDR 0x24 /* SDRAM Memory Device Register */
81#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */
82#define AT91_SDRAMC_MD_SDRAM 0
83#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
84
85#endif
diff --git a/arch/arm/mach-at91/include/mach/at91x40.h b/arch/arm/mach-at91/include/mach/at91x40.h
deleted file mode 100644
index 38dca2bb027f..000000000000
--- a/arch/arm/mach-at91/include/mach/at91x40.h
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91x40.h
3 *
4 * (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#ifndef AT91X40_H
13#define AT91X40_H
14
15/*
16 * IRQ list.
17 */
18#define AT91X40_ID_USART0 2 /* USART port 0 */
19#define AT91X40_ID_USART1 3 /* USART port 1 */
20#define AT91X40_ID_TC0 4 /* Timer/Counter 0 */
21#define AT91X40_ID_TC1 5 /* Timer/Counter 1*/
22#define AT91X40_ID_TC2 6 /* Timer/Counter 2*/
23#define AT91X40_ID_WD 7 /* Watchdog? */
24#define AT91X40_ID_PIOA 8 /* Parallel IO Controller A */
25
26#define AT91X40_ID_IRQ0 16 /* External IRQ 0 */
27#define AT91X40_ID_IRQ1 17 /* External IRQ 1 */
28#define AT91X40_ID_IRQ2 18 /* External IRQ 2 */
29
30/*
31 * System Peripherals
32 */
33#define AT91_BASE_SYS 0xffc00000
34
35#define AT91_EBI 0xffe00000 /* External Bus Interface */
36#define AT91_SF 0xfff00000 /* Special Function */
37#define AT91_USART1 0xfffcc000 /* USART 1 */
38#define AT91_USART0 0xfffd0000 /* USART 0 */
39#define AT91_TC 0xfffe0000 /* Timer Counter */
40#define AT91_PIOA 0xffff0000 /* PIO Controller A */
41#define AT91_PS 0xffff4000 /* Power Save */
42#define AT91_WD 0xffff8000 /* Watchdog Timer */
43
44/*
45 * The AT91x40 series doesn't have a debug unit like the other AT91 parts.
46 * But it does have a chip identify register and extension ID, so define at
47 * least these here.
48 */
49#define AT91_DBGU_CIDR (AT91_SF + 0) /* CIDR in PS segment */
50#define AT91_DBGU_EXID (AT91_SF + 4) /* EXID in PS segment */
51
52/*
53 * Support defines for the simple Power Controller module.
54 */
55#define AT91_PS_CR (AT91_PS + 0) /* PS Control register */
56#define AT91_PS_CR_CPU (1 << 0) /* CPU clock disable bit */
57
58#define AT91X40_MASTER_CLOCK 40000000
59
60#endif /* AT91X40_H */
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index b27e9ca65653..61914fb35f5d 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -62,7 +62,6 @@
62#define ARCH_EXID_SAMA5D43 0x00000003 62#define ARCH_EXID_SAMA5D43 0x00000003
63#define ARCH_EXID_SAMA5D44 0x00000004 63#define ARCH_EXID_SAMA5D44 0x00000004
64 64
65#define ARCH_FAMILY_AT91X92 0x09200000
66#define ARCH_FAMILY_AT91SAM9 0x01900000 65#define ARCH_FAMILY_AT91SAM9 0x01900000
67#define ARCH_FAMILY_AT91SAM9XE 0x02900000 66#define ARCH_FAMILY_AT91SAM9XE 0x02900000
68 67
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index c13797352688..cacbaa52418f 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -24,9 +24,6 @@
24/* sama5d4 */ 24/* sama5d4 */
25#define AT91_BASE_DBGU2 0xfc069000 25#define AT91_BASE_DBGU2 0xfc069000
26 26
27#if defined(CONFIG_ARCH_AT91X40)
28#include <mach/at91x40.h>
29#else
30#include <mach/at91rm9200.h> 27#include <mach/at91rm9200.h>
31#include <mach/at91sam9260.h> 28#include <mach/at91sam9260.h>
32#include <mach/at91sam9261.h> 29#include <mach/at91sam9261.h>
@@ -51,8 +48,6 @@
51 */ 48 */
52#define AT91_BASE_SYS 0xffffc000 49#define AT91_BASE_SYS 0xffffc000
53 50
54#endif
55
56/* 51/*
57 * On sama5d4 there is no system controller, we map some needed peripherals 52 * On sama5d4 there is no system controller, we map some needed peripherals
58 */ 53 */
@@ -132,13 +127,8 @@
132 * called as part of the generic suspend/resume path. 127 * called as part of the generic suspend/resume path.
133 */ 128 */
134#ifndef __ASSEMBLY__ 129#ifndef __ASSEMBLY__
135#ifdef CONFIG_PINCTRL_AT91
136extern void at91_pinctrl_gpio_suspend(void); 130extern void at91_pinctrl_gpio_suspend(void);
137extern void at91_pinctrl_gpio_resume(void); 131extern void at91_pinctrl_gpio_resume(void);
138#else
139static inline void at91_pinctrl_gpio_suspend(void) {}
140static inline void at91_pinctrl_gpio_resume(void) {}
141#endif
142#endif 132#endif
143 133
144#endif 134#endif
diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h
index acb2d890ad7e..4ebb609369e3 100644
--- a/arch/arm/mach-at91/include/mach/uncompress.h
+++ b/arch/arm/mach-at91/include/mach/uncompress.h
@@ -31,7 +31,6 @@
31 31
32void __iomem *at91_uart; 32void __iomem *at91_uart;
33 33
34#if !defined(CONFIG_ARCH_AT91X40)
35static const u32 uarts_rm9200[] = { 34static const u32 uarts_rm9200[] = {
36 AT91_BASE_DBGU0, 35 AT91_BASE_DBGU0,
37 AT91RM9200_BASE_US0, 36 AT91RM9200_BASE_US0,
@@ -188,12 +187,6 @@ static inline void arch_decomp_setup(void)
188 187
189 at91_uart = NULL; 188 at91_uart = NULL;
190} 189}
191#else
192static inline void arch_decomp_setup(void)
193{
194 at91_uart = NULL;
195}
196#endif
197 190
198/* 191/*
199 * The following code assumes the serial port has already been 192 * The following code assumes the serial port has already been
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
deleted file mode 100644
index cdb3ec9efd2b..000000000000
--- a/arch/arm/mach-at91/irq.c
+++ /dev/null
@@ -1,296 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/irq.c
3 *
4 * Copyright (C) 2004 SAN People
5 * Copyright (C) 2004 ATMEL
6 * Copyright (C) Rick Bronson
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/init.h>
24#include <linux/module.h>
25#include <linux/mm.h>
26#include <linux/bitmap.h>
27#include <linux/types.h>
28#include <linux/irq.h>
29#include <linux/of.h>
30#include <linux/of_address.h>
31#include <linux/of_irq.h>
32#include <linux/irqdomain.h>
33#include <linux/err.h>
34#include <linux/slab.h>
35
36#include <mach/hardware.h>
37#include <asm/irq.h>
38#include <asm/setup.h>
39
40#include <asm/exception.h>
41#include <asm/mach/arch.h>
42#include <asm/mach/irq.h>
43#include <asm/mach/map.h>
44
45#include "at91_aic.h"
46
47void __iomem *at91_aic_base;
48static struct irq_domain *at91_aic_domain;
49static struct device_node *at91_aic_np;
50static unsigned int n_irqs = NR_AIC_IRQS;
51
52#ifdef CONFIG_PM
53
54static unsigned long *wakeups;
55static unsigned long *backups;
56
57#define set_backup(bit) set_bit(bit, backups)
58#define clear_backup(bit) clear_bit(bit, backups)
59
60static int at91_aic_pm_init(void)
61{
62 backups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL);
63 if (!backups)
64 return -ENOMEM;
65
66 wakeups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL);
67 if (!wakeups) {
68 kfree(backups);
69 return -ENOMEM;
70 }
71
72 return 0;
73}
74
75static int at91_aic_set_wake(struct irq_data *d, unsigned value)
76{
77 if (unlikely(d->hwirq >= n_irqs))
78 return -EINVAL;
79
80 if (value)
81 set_bit(d->hwirq, wakeups);
82 else
83 clear_bit(d->hwirq, wakeups);
84
85 return 0;
86}
87
88void at91_irq_suspend(void)
89{
90 at91_aic_write(AT91_AIC_IDCR, *backups);
91 at91_aic_write(AT91_AIC_IECR, *wakeups);
92}
93
94void at91_irq_resume(void)
95{
96 at91_aic_write(AT91_AIC_IDCR, *wakeups);
97 at91_aic_write(AT91_AIC_IECR, *backups);
98}
99
100#else
101static inline int at91_aic_pm_init(void)
102{
103 return 0;
104}
105
106#define set_backup(bit)
107#define clear_backup(bit)
108#define at91_aic_set_wake NULL
109
110#endif /* CONFIG_PM */
111
112asmlinkage void __exception_irq_entry
113at91_aic_handle_irq(struct pt_regs *regs)
114{
115 u32 irqnr;
116 u32 irqstat;
117
118 irqnr = at91_aic_read(AT91_AIC_IVR);
119 irqstat = at91_aic_read(AT91_AIC_ISR);
120
121 /*
122 * ISR value is 0 when there is no current interrupt or when there is
123 * a spurious interrupt
124 */
125 if (!irqstat)
126 at91_aic_write(AT91_AIC_EOICR, 0);
127 else
128 handle_IRQ(irqnr, regs);
129}
130
131static void at91_aic_mask_irq(struct irq_data *d)
132{
133 /* Disable interrupt on AIC */
134 at91_aic_write(AT91_AIC_IDCR, 1 << d->hwirq);
135 /* Update ISR cache */
136 clear_backup(d->hwirq);
137}
138
139static void at91_aic_unmask_irq(struct irq_data *d)
140{
141 /* Enable interrupt on AIC */
142 at91_aic_write(AT91_AIC_IECR, 1 << d->hwirq);
143 /* Update ISR cache */
144 set_backup(d->hwirq);
145}
146
147static void at91_aic_eoi(struct irq_data *d)
148{
149 /*
150 * Mark end-of-interrupt on AIC, the controller doesn't care about
151 * the value written. Moreover it's a write-only register.
152 */
153 at91_aic_write(AT91_AIC_EOICR, 0);
154}
155
156static unsigned long *at91_extern_irq;
157
158u32 at91_get_extern_irq(void)
159{
160 if (!at91_extern_irq)
161 return 0;
162 return *at91_extern_irq;
163}
164
165#define is_extern_irq(hwirq) test_bit(hwirq, at91_extern_irq)
166
167static int at91_aic_compute_srctype(struct irq_data *d, unsigned type)
168{
169 int srctype;
170
171 switch (type) {
172 case IRQ_TYPE_LEVEL_HIGH:
173 srctype = AT91_AIC_SRCTYPE_HIGH;
174 break;
175 case IRQ_TYPE_EDGE_RISING:
176 srctype = AT91_AIC_SRCTYPE_RISING;
177 break;
178 case IRQ_TYPE_LEVEL_LOW:
179 if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */
180 srctype = AT91_AIC_SRCTYPE_LOW;
181 else
182 srctype = -EINVAL;
183 break;
184 case IRQ_TYPE_EDGE_FALLING:
185 if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */
186 srctype = AT91_AIC_SRCTYPE_FALLING;
187 else
188 srctype = -EINVAL;
189 break;
190 default:
191 srctype = -EINVAL;
192 }
193
194 return srctype;
195}
196
197static int at91_aic_set_type(struct irq_data *d, unsigned type)
198{
199 unsigned int smr;
200 int srctype;
201
202 srctype = at91_aic_compute_srctype(d, type);
203 if (srctype < 0)
204 return srctype;
205
206 smr = at91_aic_read(AT91_AIC_SMR(d->hwirq)) & ~AT91_AIC_SRCTYPE;
207 at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
208
209 return 0;
210}
211
212static struct irq_chip at91_aic_chip = {
213 .name = "AIC",
214 .irq_mask = at91_aic_mask_irq,
215 .irq_unmask = at91_aic_unmask_irq,
216 .irq_set_type = at91_aic_set_type,
217 .irq_set_wake = at91_aic_set_wake,
218 .irq_eoi = at91_aic_eoi,
219};
220
221static void __init at91_aic_hw_init(unsigned int spu_vector)
222{
223 int i;
224
225 /*
226 * Perform 8 End Of Interrupt Command to make sure AIC
227 * will not Lock out nIRQ
228 */
229 for (i = 0; i < 8; i++)
230 at91_aic_write(AT91_AIC_EOICR, 0);
231
232 /*
233 * Spurious Interrupt ID in Spurious Vector Register.
234 * When there is no current interrupt, the IRQ Vector Register
235 * reads the value stored in AIC_SPU
236 */
237 at91_aic_write(AT91_AIC_SPU, spu_vector);
238
239 /* No debugging in AIC: Debug (Protect) Control Register */
240 at91_aic_write(AT91_AIC_DCR, 0);
241
242 /* Disable and clear all interrupts initially */
243 at91_aic_write(AT91_AIC_IDCR, 0xFFFFFFFF);
244 at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);
245}
246
247/*
248 * Initialize the AIC interrupt controller.
249 */
250void __init at91_aic_init(unsigned int *priority, unsigned int ext_irq_mask)
251{
252 unsigned int i;
253 int irq_base;
254
255 at91_extern_irq = kzalloc(BITS_TO_LONGS(n_irqs)
256 * sizeof(*at91_extern_irq), GFP_KERNEL);
257
258 if (at91_aic_pm_init() || at91_extern_irq == NULL)
259 panic("Unable to allocate bit maps\n");
260
261 *at91_extern_irq = ext_irq_mask;
262
263 at91_aic_base = ioremap(AT91_AIC, 512);
264 if (!at91_aic_base)
265 panic("Unable to ioremap AIC registers\n");
266
267 /* Add irq domain for AIC */
268 irq_base = irq_alloc_descs(-1, 0, n_irqs, 0);
269 if (irq_base < 0) {
270 WARN(1, "Cannot allocate irq_descs, assuming pre-allocated\n");
271 irq_base = 0;
272 }
273 at91_aic_domain = irq_domain_add_legacy(at91_aic_np, n_irqs,
274 irq_base, 0,
275 &irq_domain_simple_ops, NULL);
276
277 if (!at91_aic_domain)
278 panic("Unable to add AIC irq domain\n");
279
280 irq_set_default_host(at91_aic_domain);
281
282 /*
283 * The IVR is used by macro get_irqnr_and_base to read and verify.
284 * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
285 */
286 for (i = 0; i < n_irqs; i++) {
287 /* Put hardware irq number in Source Vector Register: */
288 at91_aic_write(AT91_AIC_SVR(i), NR_IRQS_LEGACY + i);
289 /* Active Low interrupt, with the specified priority */
290 at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
291 irq_set_chip_and_handler(NR_IRQS_LEGACY + i, &at91_aic_chip, handle_fasteoi_irq);
292 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
293 }
294
295 at91_aic_hw_init(n_irqs);
296}
diff --git a/arch/arm/mach-at91/leds.c b/arch/arm/mach-at91/leds.c
deleted file mode 100644
index eb22e3357e87..000000000000
--- a/arch/arm/mach-at91/leds.c
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * LED driver for Atmel AT91-based boards.
3 *
4 * Copyright (C) SAN People (Pty) Ltd
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10*/
11
12#include <linux/gpio.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/platform_device.h>
17
18#include "board.h"
19#include "gpio.h"
20
21
22/* ------------------------------------------------------------------------- */
23
24#if defined(CONFIG_NEW_LEDS)
25
26/*
27 * New cross-platform LED support.
28 */
29
30static struct gpio_led_platform_data led_data;
31
32static struct platform_device at91_gpio_leds_device = {
33 .name = "leds-gpio",
34 .id = -1,
35 .dev.platform_data = &led_data,
36};
37
38void __init at91_gpio_leds(struct gpio_led *leds, int nr)
39{
40 int i;
41
42 if (!nr)
43 return;
44
45 for (i = 0; i < nr; i++)
46 at91_set_gpio_output(leds[i].gpio, leds[i].active_low);
47
48 led_data.leds = leds;
49 led_data.num_leds = nr;
50 platform_device_register(&at91_gpio_leds_device);
51}
52
53#else
54void __init at91_gpio_leds(struct gpio_led *leds, int nr) {}
55#endif
56
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 4073ab7f38f3..9b15169a1c62 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -29,10 +29,8 @@
29#include <mach/cpu.h> 29#include <mach/cpu.h>
30#include <mach/hardware.h> 30#include <mach/hardware.h>
31 31
32#include "at91_aic.h"
33#include "generic.h" 32#include "generic.h"
34#include "pm.h" 33#include "pm.h"
35#include "gpio.h"
36 34
37static void (*at91_pm_standby)(void); 35static void (*at91_pm_standby)(void);
38 36
@@ -131,23 +129,7 @@ extern u32 at91_slow_clock_sz;
131 129
132static int at91_pm_enter(suspend_state_t state) 130static int at91_pm_enter(suspend_state_t state)
133{ 131{
134 if (of_have_populated_dt()) 132 at91_pinctrl_gpio_suspend();
135 at91_pinctrl_gpio_suspend();
136 else
137 at91_gpio_suspend();
138
139 if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base) {
140 at91_irq_suspend();
141
142 pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
143 /* remember all the always-wake irqs */
144 (at91_pmc_read(AT91_PMC_PCSR)
145 | (1 << AT91_ID_FIQ)
146 | (1 << AT91_ID_SYS)
147 | (at91_get_extern_irq()))
148 & at91_aic_read(AT91_AIC_IMR),
149 state);
150 }
151 133
152 switch (state) { 134 switch (state) {
153 /* 135 /*
@@ -212,21 +194,10 @@ static int at91_pm_enter(suspend_state_t state)
212 goto error; 194 goto error;
213 } 195 }
214 196
215 if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base)
216 pr_debug("AT91: PM - wakeup %08x\n",
217 at91_aic_read(AT91_AIC_IPR) &
218 at91_aic_read(AT91_AIC_IMR));
219
220error: 197error:
221 target_state = PM_SUSPEND_ON; 198 target_state = PM_SUSPEND_ON;
222 199
223 if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base) 200 at91_pinctrl_gpio_resume();
224 at91_irq_resume();
225
226 if (of_have_populated_dt())
227 at91_pinctrl_gpio_resume();
228 else
229 at91_gpio_resume();
230 return 0; 201 return 0;
231} 202}
232 203
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index c5101dcb4fb0..d2c89963af2d 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -14,7 +14,6 @@
14#include <asm/proc-fns.h> 14#include <asm/proc-fns.h>
15 15
16#include <mach/at91_ramc.h> 16#include <mach/at91_ramc.h>
17#include <mach/at91rm9200_sdramc.h>
18 17
19#ifdef CONFIG_PM 18#ifdef CONFIG_PM
20extern void at91_pm_set_standby(void (*at91_standby)(void)); 19extern void at91_pm_set_standby(void (*at91_standby)(void));
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 961079250b83..ce25e85720fb 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -42,35 +42,9 @@ void __init at91rm9200_set_type(int type)
42 at91_get_soc_subtype(&at91_soc_initdata)); 42 at91_get_soc_subtype(&at91_soc_initdata));
43} 43}
44 44
45void __init at91_init_irq_default(void)
46{
47 at91_init_interrupts(at91_boot_soc.default_irq_priority);
48}
49
50void __init at91_init_interrupts(unsigned int *priority)
51{
52 /* Initialize the AIC interrupt controller */
53 if (IS_ENABLED(CONFIG_OLD_IRQ_AT91))
54 at91_aic_init(priority, at91_boot_soc.extern_irq);
55
56 /* Enable GPIO interrupts */
57 at91_gpio_irq_setup();
58}
59
60void __iomem *at91_ramc_base[2]; 45void __iomem *at91_ramc_base[2];
61EXPORT_SYMBOL_GPL(at91_ramc_base); 46EXPORT_SYMBOL_GPL(at91_ramc_base);
62 47
63void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
64{
65 if (id < 0 || id > 1) {
66 pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
67 BUG();
68 }
69 at91_ramc_base[id] = ioremap(addr, size);
70 if (!at91_ramc_base[id])
71 panic(pr_fmt("Impossible to ioremap ramc.%d 0x%x\n"), id, addr);
72}
73
74static struct map_desc sram_desc[2] __initdata; 48static struct map_desc sram_desc[2] __initdata;
75 49
76void __init at91_init_sram(int bank, unsigned long base, unsigned int length) 50void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
@@ -418,7 +392,6 @@ void __init at91_ioremap_matrix(u32 base_addr)
418 panic(pr_fmt("Impossible to ioremap at91_matrix_base\n")); 392 panic(pr_fmt("Impossible to ioremap at91_matrix_base\n"));
419} 393}
420 394
421#if defined(CONFIG_OF) && !defined(CONFIG_ARCH_AT91X40)
422static struct of_device_id ramc_ids[] = { 395static struct of_device_id ramc_ids[] = {
423 { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby }, 396 { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
424 { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby }, 397 { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
@@ -460,13 +433,6 @@ void __init at91rm9200_dt_initialize(void)
460{ 433{
461 at91_dt_ramc(); 434 at91_dt_ramc();
462 435
463 /* Init clock subsystem */
464 at91_dt_clock_init();
465
466 /* Register the processor-specific clocks */
467 if (at91_boot_soc.register_clocks)
468 at91_boot_soc.register_clocks();
469
470 at91_boot_soc.init(); 436 at91_boot_soc.init();
471} 437}
472 438
@@ -474,39 +440,6 @@ void __init at91_dt_initialize(void)
474{ 440{
475 at91_dt_ramc(); 441 at91_dt_ramc();
476 442
477 /* Init clock subsystem */
478 at91_dt_clock_init();
479
480 /* Register the processor-specific clocks */
481 if (at91_boot_soc.register_clocks)
482 at91_boot_soc.register_clocks();
483
484 if (at91_boot_soc.init) 443 if (at91_boot_soc.init)
485 at91_boot_soc.init(); 444 at91_boot_soc.init();
486} 445}
487#endif
488
489void __init at91_initialize(unsigned long main_clock)
490{
491 at91_boot_soc.ioremap_registers();
492
493 /* Init clock subsystem */
494 at91_clock_init(main_clock);
495
496 /* Register the processor-specific clocks */
497 at91_boot_soc.register_clocks();
498
499 at91_boot_soc.init();
500
501 pinctrl_provide_dummies();
502}
503
504void __init at91_register_devices(void)
505{
506 at91_boot_soc.register_devices();
507}
508
509void __init at91_init_time(void)
510{
511 at91_boot_soc.init_time();
512}
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h
index 9a8fd97a8bef..ae6c0b2f1146 100644
--- a/arch/arm/mach-at91/soc.h
+++ b/arch/arm/mach-at91/soc.h
@@ -6,14 +6,8 @@
6 6
7struct at91_init_soc { 7struct at91_init_soc {
8 int builtin; 8 int builtin;
9 u32 extern_irq;
10 unsigned int *default_irq_priority;
11 void (*map_io)(void); 9 void (*map_io)(void);
12 void (*ioremap_registers)(void);
13 void (*register_clocks)(void);
14 void (*register_devices)(void);
15 void (*init)(void); 10 void (*init)(void);
16 void (*init_time)(void);
17}; 11};
18 12
19extern struct at91_init_soc at91_boot_soc; 13extern struct at91_init_soc at91_boot_soc;
diff --git a/arch/arm/mach-at91/stamp9g20.h b/arch/arm/mach-at91/stamp9g20.h
deleted file mode 100644
index f62c0abca4b4..000000000000
--- a/arch/arm/mach-at91/stamp9g20.h
+++ /dev/null
@@ -1,7 +0,0 @@
1#ifndef __MACH_STAMP9G20_H
2#define __MACH_STAMP9G20_H
3
4void stamp9g20_init_early(void);
5void stamp9g20_board_init(void);
6
7#endif