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-rw-r--r--arch/arm64/kernel/cpu_errata.c33
1 files changed, 32 insertions, 1 deletions
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 9332cf7c0826..e107ed2d66dc 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -23,6 +23,8 @@
23#include <asm/cputype.h> 23#include <asm/cputype.h>
24#include <asm/cpufeature.h> 24#include <asm/cpufeature.h>
25 25
26#define MIDR_CORTEX_A53 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
27
26/* 28/*
27 * Add a struct or another datatype to the union below if you need 29 * Add a struct or another datatype to the union below if you need
28 * different means to detect an affected CPU. 30 * different means to detect an affected CPU.
@@ -39,8 +41,37 @@ struct arm64_cpu_capabilities {
39 }; 41 };
40}; 42};
41 43
44#define CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \
45 MIDR_ARCHITECTURE_MASK)
46
47static bool __maybe_unused
48is_affected_midr_range(struct arm64_cpu_capabilities *entry)
49{
50 u32 midr = read_cpuid_id();
51
52 if ((midr & CPU_MODEL_MASK) != entry->midr_model)
53 return false;
54
55 midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;
56
57 return (midr >= entry->midr_range_min && midr <= entry->midr_range_max);
58}
59
60#define MIDR_RANGE(model, min, max) \
61 .is_affected = is_affected_midr_range, \
62 .midr_model = model, \
63 .midr_range_min = min, \
64 .midr_range_max = max
65
42struct arm64_cpu_capabilities arm64_errata[] = { 66struct arm64_cpu_capabilities arm64_errata[] = {
43 {} 67 {
68 /* Cortex-A53 r0p[012] */
69 .desc = "ARM errata 826319, 827319, 824069",
70 .capability = ARM64_WORKAROUND_CLEAN_CACHE,
71 MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x02),
72 },
73 {
74 }
44}; 75};
45 76
46void check_local_cpu_errata(void) 77void check_local_cpu_errata(void)