13 files changed, 230 insertions, 144 deletions

diff --git a/arch/arm64/include/asm/Kbuild b/arch/arm64/include/asm/Kbuild
index 14a9d5a2b85b..e5fe4f99fe10 100644
--- a/arch/arm64/include/asm/Kbuild
+++ b/arch/arm64/include/asm/Kbuild
@@ -19,6 +19,7 @@ generic-y += ipcbuf.h
 generic-y += irq_regs.h
 generic-y += kdebug.h
 generic-y += kmap_types.h
+generic-y += kvm_para.h
 generic-y += local.h
 generic-y += local64.h
 generic-y += mman.h
@@ -48,3 +49,4 @@ generic-y += trace_clock.h
 generic-y += types.h
 generic-y += unaligned.h
 generic-y += user.h
+generic-y += xor.h
diff --git a/arch/arm64/include/asm/atomic.h b/arch/arm64/include/asm/atomic.h
index 407717ba060e..836364468571 100644
--- a/arch/arm64/include/asm/atomic.h
+++ b/arch/arm64/include/asm/atomic.h
@@ -49,12 +49,12 @@ static inline void atomic_add(int i, atomic_t *v)
         int result;
 
         asm volatile("// atomic_add\n"
-"1:     ldxr    %w0, [%3]\n"
-"       add     %w0, %w0, %w4\n"
-"       stxr    %w1, %w0, [%3]\n"
+"1:     ldxr    %w0, %2\n"
+"       add     %w0, %w0, %w3\n"
+"       stxr    %w1, %w0, %2\n"
 "       cbnz    %w1, 1b"
-        : "=&r" (result), "=&r" (tmp), "+o" (v->counter)
-        : "r" (&v->counter), "Ir" (i)
+        : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
+        : "Ir" (i)
         : "cc");
 }
 
@@ -64,13 +64,13 @@ static inline int atomic_add_return(int i, atomic_t *v)
         int result;
 
         asm volatile("// atomic_add_return\n"
-"1:     ldaxr   %w0, [%3]\n"
-"       add     %w0, %w0, %w4\n"
-"       stlxr   %w1, %w0, [%3]\n"
+"1:     ldaxr   %w0, %2\n"
+"       add     %w0, %w0, %w3\n"
+"       stlxr   %w1, %w0, %2\n"
 "       cbnz    %w1, 1b"
-        : "=&r" (result), "=&r" (tmp), "+o" (v->counter)
-        : "r" (&v->counter), "Ir" (i)
-        : "cc");
+        : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
+        : "Ir" (i)
+        : "cc", "memory");
 
         return result;
 }
@@ -81,12 +81,12 @@ static inline void atomic_sub(int i, atomic_t *v)
         int result;
 
         asm volatile("// atomic_sub\n"
-"1:     ldxr    %w0, [%3]\n"
-"       sub     %w0, %w0, %w4\n"
-"       stxr    %w1, %w0, [%3]\n"
+"1:     ldxr    %w0, %2\n"
+"       sub     %w0, %w0, %w3\n"
+"       stxr    %w1, %w0, %2\n"
 "       cbnz    %w1, 1b"
-        : "=&r" (result), "=&r" (tmp), "+o" (v->counter)
-        : "r" (&v->counter), "Ir" (i)
+        : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
+        : "Ir" (i)
         : "cc");
 }
 
@@ -96,13 +96,13 @@ static inline int atomic_sub_return(int i, atomic_t *v)
         int result;
 
         asm volatile("// atomic_sub_return\n"
-"1:     ldaxr   %w0, [%3]\n"
-"       sub     %w0, %w0, %w4\n"
-"       stlxr   %w1, %w0, [%3]\n"
+"1:     ldaxr   %w0, %2\n"
+"       sub     %w0, %w0, %w3\n"
+"       stlxr   %w1, %w0, %2\n"
 "       cbnz    %w1, 1b"
-        : "=&r" (result), "=&r" (tmp), "+o" (v->counter)
-        : "r" (&v->counter), "Ir" (i)
-        : "cc");
+        : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
+        : "Ir" (i)
+        : "cc", "memory");
 
         return result;
 }
@@ -113,15 +113,15 @@ static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
         int oldval;
 
         asm volatile("// atomic_cmpxchg\n"
-"1:     ldaxr   %w1, [%3]\n"
-"       cmp     %w1, %w4\n"
+"1:     ldaxr   %w1, %2\n"
+"       cmp     %w1, %w3\n"
 "       b.ne    2f\n"
-"       stlxr   %w0, %w5, [%3]\n"
+"       stlxr   %w0, %w4, %2\n"
 "       cbnz    %w0, 1b\n"
 "2:"
-        : "=&r" (tmp), "=&r" (oldval), "+o" (ptr->counter)
-        : "r" (&ptr->counter), "Ir" (old), "r" (new)
-        : "cc");
+        : "=&r" (tmp), "=&r" (oldval), "+Q" (ptr->counter)
+        : "Ir" (old), "r" (new)
+        : "cc", "memory");
 
         return oldval;
 }
@@ -131,12 +131,12 @@ static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
         unsigned long tmp, tmp2;
 
         asm volatile("// atomic_clear_mask\n"
-"1:     ldxr    %0, [%3]\n"
-"       bic     %0, %0, %4\n"
-"       stxr    %w1, %0, [%3]\n"
+"1:     ldxr    %0, %2\n"
+"       bic     %0, %0, %3\n"
+"       stxr    %w1, %0, %2\n"
 "       cbnz    %w1, 1b"
-        : "=&r" (tmp), "=&r" (tmp2), "+o" (*addr)
-        : "r" (addr), "Ir" (mask)
+        : "=&r" (tmp), "=&r" (tmp2), "+Q" (*addr)
+        : "Ir" (mask)
         : "cc");
 }
 
@@ -182,12 +182,12 @@ static inline void atomic64_add(u64 i, atomic64_t *v)
         unsigned long tmp;
 
         asm volatile("// atomic64_add\n"
-"1:     ldxr    %0, [%3]\n"
-"       add     %0, %0, %4\n"
-"       stxr    %w1, %0, [%3]\n"
+"1:     ldxr    %0, %2\n"
+"       add     %0, %0, %3\n"
+"       stxr    %w1, %0, %2\n"
 "       cbnz    %w1, 1b"
-        : "=&r" (result), "=&r" (tmp), "+o" (v->counter)
-        : "r" (&v->counter), "Ir" (i)
+        : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
+        : "Ir" (i)
         : "cc");
 }
 
@@ -197,13 +197,13 @@ static inline long atomic64_add_return(long i, atomic64_t *v)
         unsigned long tmp;
 
         asm volatile("// atomic64_add_return\n"
-"1:     ldaxr   %0, [%3]\n"
-"       add     %0, %0, %4\n"
-"       stlxr   %w1, %0, [%3]\n"
+"1:     ldaxr   %0, %2\n"
+"       add     %0, %0, %3\n"
+"       stlxr   %w1, %0, %2\n"
 "       cbnz    %w1, 1b"
-        : "=&r" (result), "=&r" (tmp), "+o" (v->counter)
-        : "r" (&v->counter), "Ir" (i)
-        : "cc");
+        : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
+        : "Ir" (i)
+        : "cc", "memory");
 
         return result;
 }
@@ -214,12 +214,12 @@ static inline void atomic64_sub(u64 i, atomic64_t *v)
         unsigned long tmp;
 
         asm volatile("// atomic64_sub\n"
-"1:     ldxr    %0, [%3]\n"
-"       sub     %0, %0, %4\n"
-"       stxr    %w1, %0, [%3]\n"
+"1:     ldxr    %0, %2\n"
+"       sub     %0, %0, %3\n"
+"       stxr    %w1, %0, %2\n"
 "       cbnz    %w1, 1b"
-        : "=&r" (result), "=&r" (tmp), "+o" (v->counter)
-        : "r" (&v->counter), "Ir" (i)
+        : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
+        : "Ir" (i)
         : "cc");
 }
 
@@ -229,13 +229,13 @@ static inline long atomic64_sub_return(long i, atomic64_t *v)
         unsigned long tmp;
 
         asm volatile("// atomic64_sub_return\n"
-"1:     ldaxr   %0, [%3]\n"
-"       sub     %0, %0, %4\n"
-"       stlxr   %w1, %0, [%3]\n"
+"1:     ldaxr   %0, %2\n"
+"       sub     %0, %0, %3\n"
+"       stlxr   %w1, %0, %2\n"
 "       cbnz    %w1, 1b"
-        : "=&r" (result), "=&r" (tmp), "+o" (v->counter)
-        : "r" (&v->counter), "Ir" (i)
-        : "cc");
+        : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
+        : "Ir" (i)
+        : "cc", "memory");
 
         return result;
 }
@@ -246,15 +246,15 @@ static inline long atomic64_cmpxchg(atomic64_t *ptr, long old, long new)
         unsigned long res;
 
         asm volatile("// atomic64_cmpxchg\n"
-"1:     ldaxr   %1, [%3]\n"
-"       cmp     %1, %4\n"
+"1:     ldaxr   %1, %2\n"
+"       cmp     %1, %3\n"
 "       b.ne    2f\n"
-"       stlxr   %w0, %5, [%3]\n"
+"       stlxr   %w0, %4, %2\n"
 "       cbnz    %w0, 1b\n"
 "2:"
-        : "=&r" (res), "=&r" (oldval), "+o" (ptr->counter)
-        : "r" (&ptr->counter), "Ir" (old), "r" (new)
-        : "cc");
+        : "=&r" (res), "=&r" (oldval), "+Q" (ptr->counter)
+        : "Ir" (old), "r" (new)
+        : "cc", "memory");
 
         return oldval;
 }
@@ -267,15 +267,15 @@ static inline long atomic64_dec_if_positive(atomic64_t *v)
         unsigned long tmp;
 
         asm volatile("// atomic64_dec_if_positive\n"
-"1:     ldaxr   %0, [%3]\n"
+"1:     ldaxr   %0, %2\n"
 "       subs    %0, %0, #1\n"
 "       b.mi    2f\n"
-"       stlxr   %w1, %0, [%3]\n"
+"       stlxr   %w1, %0, %2\n"
 "       cbnz    %w1, 1b\n"
 "2:"
-        : "=&r" (result), "=&r" (tmp), "+o" (v->counter)
-        : "r" (&v->counter)
-        : "cc");
+        : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
+        :
+        : "cc", "memory");
 
         return result;
 }
diff --git a/arch/arm64/include/asm/cmpxchg.h b/arch/arm64/include/asm/cmpxchg.h
index e0e65b069d9e..968b5cbfc260 100644
--- a/arch/arm64/include/asm/cmpxchg.h
+++ b/arch/arm64/include/asm/cmpxchg.h
@@ -29,39 +29,39 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
         switch (size) {
         case 1:
                 asm volatile("//        __xchg1\n"
-                "1:     ldaxrb  %w0, [%3]\n"
-                "       stlxrb  %w1, %w2, [%3]\n"
+                "1:     ldaxrb  %w0, %2\n"
+                "       stlxrb  %w1, %w3, %2\n"
                 "       cbnz    %w1, 1b\n"
-                        : "=&r" (ret), "=&r" (tmp)
-                        : "r" (x), "r" (ptr)
-                        : "memory", "cc");
+                        : "=&r" (ret), "=&r" (tmp), "+Q" (*(u8 *)ptr)
+                        : "r" (x)
+                        : "cc", "memory");
                 break;
         case 2:
                 asm volatile("//        __xchg2\n"
-                "1:     ldaxrh  %w0, [%3]\n"
-                "       stlxrh  %w1, %w2, [%3]\n"
+                "1:     ldaxrh  %w0, %2\n"
+                "       stlxrh  %w1, %w3, %2\n"
                 "       cbnz    %w1, 1b\n"
-                        : "=&r" (ret), "=&r" (tmp)
-                        : "r" (x), "r" (ptr)
-                        : "memory", "cc");
+                        : "=&r" (ret), "=&r" (tmp), "+Q" (*(u16 *)ptr)
+                        : "r" (x)
+                        : "cc", "memory");
                 break;
         case 4:
                 asm volatile("//        __xchg4\n"
-                "1:     ldaxr   %w0, [%3]\n"
-                "       stlxr   %w1, %w2, [%3]\n"
+                "1:     ldaxr   %w0, %2\n"
+                "       stlxr   %w1, %w3, %2\n"
                 "       cbnz    %w1, 1b\n"
-                        : "=&r" (ret), "=&r" (tmp)
-                        : "r" (x), "r" (ptr)
-                        : "memory", "cc");
+                        : "=&r" (ret), "=&r" (tmp), "+Q" (*(u32 *)ptr)
+                        : "r" (x)
+                        : "cc", "memory");
                 break;
         case 8:
                 asm volatile("//        __xchg8\n"
-                "1:     ldaxr   %0, [%3]\n"
-                "       stlxr   %w1, %2, [%3]\n"
+                "1:     ldaxr   %0, %2\n"
+                "       stlxr   %w1, %3, %2\n"
                 "       cbnz    %w1, 1b\n"
-                        : "=&r" (ret), "=&r" (tmp)
-                        : "r" (x), "r" (ptr)
-                        : "memory", "cc");
+                        : "=&r" (ret), "=&r" (tmp), "+Q" (*(u64 *)ptr)
+                        : "r" (x)
+                        : "cc", "memory");
                 break;
         default:
                 BUILD_BUG();
@@ -82,14 +82,14 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
         case 1:
                 do {
                         asm volatile("// __cmpxchg1\n"
-                        "       ldxrb   %w1, [%2]\n"
+                        "       ldxrb   %w1, %2\n"
                         "       mov     %w0, #0\n"
                         "       cmp     %w1, %w3\n"
                         "       b.ne    1f\n"
-                        "       stxrb   %w0, %w4, [%2]\n"
+                        "       stxrb   %w0, %w4, %2\n"
                         "1:\n"
-                                : "=&r" (res), "=&r" (oldval)
-                                : "r" (ptr), "Ir" (old), "r" (new)
+                                : "=&r" (res), "=&r" (oldval), "+Q" (*(u8 *)ptr)
+                                : "Ir" (old), "r" (new)
                                 : "cc");
                 } while (res);
                 break;
@@ -97,29 +97,29 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
         case 2:
                 do {
                         asm volatile("// __cmpxchg2\n"
-                        "       ldxrh   %w1, [%2]\n"
+                        "       ldxrh   %w1, %2\n"
                         "       mov     %w0, #0\n"
                         "       cmp     %w1, %w3\n"
                         "       b.ne    1f\n"
-                        "       stxrh   %w0, %w4, [%2]\n"
+                        "       stxrh   %w0, %w4, %2\n"
                         "1:\n"
-                                : "=&r" (res), "=&r" (oldval)
-                                : "r" (ptr), "Ir" (old), "r" (new)
-                                : "memory", "cc");
+                                : "=&r" (res), "=&r" (oldval), "+Q" (*(u16 *)ptr)
+                                : "Ir" (old), "r" (new)
+                                : "cc");
                 } while (res);
                 break;
 
         case 4:
                 do {
                         asm volatile("// __cmpxchg4\n"
-                        "       ldxr    %w1, [%2]\n"
+                        "       ldxr    %w1, %2\n"
                         "       mov     %w0, #0\n"
                         "       cmp     %w1, %w3\n"
                         "       b.ne    1f\n"
-                        "       stxr    %w0, %w4, [%2]\n"
+                        "       stxr    %w0, %w4, %2\n"
                         "1:\n"
-                                : "=&r" (res), "=&r" (oldval)
-                                : "r" (ptr), "Ir" (old), "r" (new)
+                                : "=&r" (res), "=&r" (oldval), "+Q" (*(u32 *)ptr)
+                                : "Ir" (old), "r" (new)
                                 : "cc");
                 } while (res);
                 break;
@@ -127,14 +127,14 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
         case 8:
                 do {
                         asm volatile("// __cmpxchg8\n"
-                        "       ldxr    %1, [%2]\n"
+                        "       ldxr    %1, %2\n"
                         "       mov     %w0, #0\n"
                         "       cmp     %1, %3\n"
                         "       b.ne    1f\n"
-                        "       stxr    %w0, %4, [%2]\n"
+                        "       stxr    %w0, %4, %2\n"
                         "1:\n"
-                                : "=&r" (res), "=&r" (oldval)
-                                : "r" (ptr), "Ir" (old), "r" (new)
+                                : "=&r" (res), "=&r" (oldval), "+Q" (*(u64 *)ptr)
+                                : "Ir" (old), "r" (new)
                                 : "cc");
                 } while (res);
                 break;
diff --git a/arch/arm64/include/asm/futex.h b/arch/arm64/include/asm/futex.h
index 3468ae8439fa..c582fa316366 100644
--- a/arch/arm64/include/asm/futex.h
+++ b/arch/arm64/include/asm/futex.h
@@ -39,7 +39,7 @@
 "       .popsection\n"                                                  \
         : "=&r" (ret), "=&r" (oldval), "+Q" (*uaddr), "=&r" (tmp)       \
         : "r" (oparg), "Ir" (-EFAULT)                                   \
-        : "cc")
+        : "cc", "memory")
 
 static inline int
 futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h
index d2f05a608274..57f12c991de2 100644
--- a/arch/arm64/include/asm/io.h
+++ b/arch/arm64/include/asm/io.h
@@ -230,6 +230,9 @@ extern void __iounmap(volatile void __iomem *addr);
 #define ioremap_wc(addr, size)          __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
 #define iounmap                         __iounmap
 
+#define PROT_SECT_DEFAULT       (PMD_TYPE_SECT | PMD_SECT_AF)
+#define PROT_SECT_DEVICE_nGnRE  (PROT_SECT_DEFAULT | PTE_PXN | PTE_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
+
 #define ARCH_HAS_IOREMAP_WC
 #include <asm-generic/iomap.h>
 
diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
index 1cac16a001cb..381f556b664e 100644
--- a/arch/arm64/include/asm/memory.h
+++ b/arch/arm64/include/asm/memory.h
@@ -43,6 +43,7 @@
 #define PAGE_OFFSET             UL(0xffffffc000000000)
 #define MODULES_END             (PAGE_OFFSET)
 #define MODULES_VADDR           (MODULES_END - SZ_64M)
+#define EARLYCON_IOBASE         (MODULES_VADDR - SZ_4M)
 #define VA_BITS                 (39)
 #define TASK_SIZE_64            (UL(1) << VA_BITS)
 
diff --git a/arch/arm64/include/asm/mmu.h b/arch/arm64/include/asm/mmu.h
index d4f7fd5b9e33..2494fc01896a 100644
--- a/arch/arm64/include/asm/mmu.h
+++ b/arch/arm64/include/asm/mmu.h
@@ -26,5 +26,6 @@ typedef struct {
 
 extern void paging_init(void);
 extern void setup_mm_for_reboot(void);
+extern void __iomem *early_io_map(phys_addr_t phys, unsigned long virt);
 
 #endif
diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h
index f68465dee026..e2bc385adb6b 100644
--- a/arch/arm64/include/asm/mmu_context.h
+++ b/arch/arm64/include/asm/mmu_context.h
@@ -35,6 +35,21 @@ extern unsigned int cpu_last_asid;
 void __init_new_context(struct task_struct *tsk, struct mm_struct *mm);
 void __new_context(struct mm_struct *mm);
 
+#ifdef CONFIG_PID_IN_CONTEXTIDR
+static inline void contextidr_thread_switch(struct task_struct *next)
+{
+        asm(
+        "       msr     contextidr_el1, %0\n"
+        "       isb"
+        :
+        : "r" (task_pid_nr(next)));
+}
+#else
+static inline void contextidr_thread_switch(struct task_struct *next)
+{
+}
+#endif
+
 /*
  * Set TTBR0 to empty_zero_page. No translations will be possible via TTBR0.
  */
diff --git a/arch/arm64/include/asm/perf_event.h b/arch/arm64/include/asm/perf_event.h
index a6fffd511c5e..d26d1d53c0d7 100644
--- a/arch/arm64/include/asm/perf_event.h
+++ b/arch/arm64/include/asm/perf_event.h
@@ -17,6 +17,11 @@
 #ifndef __ASM_PERF_EVENT_H
 #define __ASM_PERF_EVENT_H
 
-/* It's quiet around here... */
+#ifdef CONFIG_HW_PERF_EVENTS
+struct pt_regs;
+extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
+extern unsigned long perf_misc_flags(struct pt_regs *regs);
+#define perf_misc_flags(regs)   perf_misc_flags(regs)
+#endif
 
 #endif
diff --git a/arch/arm64/include/asm/psci.h b/arch/arm64/include/asm/psci.h
new file mode 100644
index 000000000000..0604237ecd99
--- /dev/null
+++ b/arch/arm64/include/asm/psci.h
@@ -0,0 +1,38 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2013 ARM Limited
+ */
+
+#ifndef __ASM_PSCI_H
+#define __ASM_PSCI_H
+
+#define PSCI_POWER_STATE_TYPE_STANDBY           0
+#define PSCI_POWER_STATE_TYPE_POWER_DOWN        1
+
+struct psci_power_state {
+        u16     id;
+        u8      type;
+        u8      affinity_level;
+};
+
+struct psci_operations {
+        int (*cpu_suspend)(struct psci_power_state state,
+                           unsigned long entry_point);
+        int (*cpu_off)(struct psci_power_state state);
+        int (*cpu_on)(unsigned long cpuid, unsigned long entry_point);
+        int (*migrate)(unsigned long cpuid);
+};
+
+extern struct psci_operations psci_ops;
+
+int psci_init(void);
+
+#endif /* __ASM_PSCI_H */
diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h
index 4ce845f8ee1c..41a71ee4c3df 100644
--- a/arch/arm64/include/asm/ptrace.h
+++ b/arch/arm64/include/asm/ptrace.h
@@ -42,6 +42,16 @@
 #define COMPAT_PSR_MODE_UND     0x0000001b
 #define COMPAT_PSR_MODE_SYS     0x0000001f
 #define COMPAT_PSR_T_BIT        0x00000020
+#define COMPAT_PSR_F_BIT        0x00000040
+#define COMPAT_PSR_I_BIT        0x00000080
+#define COMPAT_PSR_A_BIT        0x00000100
+#define COMPAT_PSR_E_BIT        0x00000200
+#define COMPAT_PSR_J_BIT        0x01000000
+#define COMPAT_PSR_Q_BIT        0x08000000
+#define COMPAT_PSR_V_BIT        0x10000000
+#define COMPAT_PSR_C_BIT        0x20000000
+#define COMPAT_PSR_Z_BIT        0x40000000
+#define COMPAT_PSR_N_BIT        0x80000000
 #define COMPAT_PSR_IT_MASK      0x0600fc00      /* If-Then execution state mask */
 /*
  * These are 'magic' values for PTRACE_PEEKUSR that return info about where a
diff --git a/arch/arm64/include/asm/smp.h b/arch/arm64/include/asm/smp.h
index 7e34295f78e3..4b8023c5d146 100644
--- a/arch/arm64/include/asm/smp.h
+++ b/arch/arm64/include/asm/smp.h
@@ -66,4 +66,15 @@ extern volatile unsigned long secondary_holding_pen_release;
 extern void arch_send_call_function_single_ipi(int cpu);
 extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
 
+struct device_node;
+
+struct smp_enable_ops {
+        const char      *name;
+        int             (*init_cpu)(struct device_node *, int);
+        int             (*prepare_cpu)(int);
+};
+
+extern const struct smp_enable_ops smp_spin_table_ops;
+extern const struct smp_enable_ops smp_psci_ops;
+
 #endif /* ifndef __ASM_SMP_H */
diff --git a/arch/arm64/include/asm/spinlock.h b/arch/arm64/include/asm/spinlock.h
index 41112fe2f8b1..7065e920149d 100644
--- a/arch/arm64/include/asm/spinlock.h
+++ b/arch/arm64/include/asm/spinlock.h
@@ -45,13 +45,13 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
         asm volatile(
         "       sevl\n"
         "1:     wfe\n"
-        "2:     ldaxr   %w0, [%1]\n"
+        "2:     ldaxr   %w0, %1\n"
         "       cbnz    %w0, 1b\n"
-        "       stxr    %w0, %w2, [%1]\n"
+        "       stxr    %w0, %w2, %1\n"
         "       cbnz    %w0, 2b\n"
-        : "=&r" (tmp)
-        : "r" (&lock->lock), "r" (1)
-        : "memory");
+        : "=&r" (tmp), "+Q" (lock->lock)
+        : "r" (1)
+        : "cc", "memory");
 }
 
 static inline int arch_spin_trylock(arch_spinlock_t *lock)
@@ -59,13 +59,13 @@ static inline int arch_spin_trylock(arch_spinlock_t *lock)
         unsigned int tmp;
 
         asm volatile(
-        "       ldaxr   %w0, [%1]\n"
+        "       ldaxr   %w0, %1\n"
         "       cbnz    %w0, 1f\n"
-        "       stxr    %w0, %w2, [%1]\n"
+        "       stxr    %w0, %w2, %1\n"
         "1:\n"
-        : "=&r" (tmp)
-        : "r" (&lock->lock), "r" (1)
-        : "memory");
+        : "=&r" (tmp), "+Q" (lock->lock)
+        : "r" (1)
+        : "cc", "memory");
 
         return !tmp;
 }
@@ -73,8 +73,8 @@ static inline int arch_spin_trylock(arch_spinlock_t *lock)
 static inline void arch_spin_unlock(arch_spinlock_t *lock)
 {
         asm volatile(
-        "       stlr    %w1, [%0]\n"
-        : : "r" (&lock->lock), "r" (0) : "memory");
+        "       stlr    %w1, %0\n"
+        : "=Q" (lock->lock) : "r" (0) : "memory");
 }
 
 /*
@@ -94,13 +94,13 @@ static inline void arch_write_lock(arch_rwlock_t *rw)
         asm volatile(
         "       sevl\n"
         "1:     wfe\n"
-        "2:     ldaxr   %w0, [%1]\n"
+        "2:     ldaxr   %w0, %1\n"
         "       cbnz    %w0, 1b\n"
-        "       stxr    %w0, %w2, [%1]\n"
+        "       stxr    %w0, %w2, %1\n"
         "       cbnz    %w0, 2b\n"
-        : "=&r" (tmp)
-        : "r" (&rw->lock), "r" (0x80000000)
-        : "memory");
+        : "=&r" (tmp), "+Q" (rw->lock)
+        : "r" (0x80000000)
+        : "cc", "memory");
 }
 
 static inline int arch_write_trylock(arch_rwlock_t *rw)
@@ -108,13 +108,13 @@ static inline int arch_write_trylock(arch_rwlock_t *rw)
         unsigned int tmp;
 
         asm volatile(
-        "       ldaxr   %w0, [%1]\n"
+        "       ldaxr   %w0, %1\n"
         "       cbnz    %w0, 1f\n"
-        "       stxr    %w0, %w2, [%1]\n"
+        "       stxr    %w0, %w2, %1\n"
         "1:\n"
-        : "=&r" (tmp)
-        : "r" (&rw->lock), "r" (0x80000000)
-        : "memory");
+        : "=&r" (tmp), "+Q" (rw->lock)
+        : "r" (0x80000000)
+        : "cc", "memory");
 
         return !tmp;
 }
@@ -122,8 +122,8 @@ static inline int arch_write_trylock(arch_rwlock_t *rw)
 static inline void arch_write_unlock(arch_rwlock_t *rw)
 {
         asm volatile(
-        "       stlr    %w1, [%0]\n"
-        : : "r" (&rw->lock), "r" (0) : "memory");
+        "       stlr    %w1, %0\n"
+        : "=Q" (rw->lock) : "r" (0) : "memory");
 }
 
 /* write_can_lock - would write_trylock() succeed? */
@@ -148,14 +148,14 @@ static inline void arch_read_lock(arch_rwlock_t *rw)
         asm volatile(
         "       sevl\n"
         "1:     wfe\n"
-        "2:     ldaxr   %w0, [%2]\n"
+        "2:     ldaxr   %w0, %2\n"
         "       add     %w0, %w0, #1\n"
         "       tbnz    %w0, #31, 1b\n"
-        "       stxr    %w1, %w0, [%2]\n"
+        "       stxr    %w1, %w0, %2\n"
         "       cbnz    %w1, 2b\n"
-        : "=&r" (tmp), "=&r" (tmp2)
-        : "r" (&rw->lock)
-        : "memory");
+        : "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock)
+        :
+        : "cc", "memory");
 }
 
 static inline void arch_read_unlock(arch_rwlock_t *rw)
@@ -163,13 +163,13 @@ static inline void arch_read_unlock(arch_rwlock_t *rw)
         unsigned int tmp, tmp2;
 
         asm volatile(
-        "1:     ldxr    %w0, [%2]\n"
+        "1:     ldxr    %w0, %2\n"
         "       sub     %w0, %w0, #1\n"
-        "       stlxr   %w1, %w0, [%2]\n"
+        "       stlxr   %w1, %w0, %2\n"
         "       cbnz    %w1, 1b\n"
-        : "=&r" (tmp), "=&r" (tmp2)
-        : "r" (&rw->lock)
-        : "memory");
+        : "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock)
+        :
+        : "cc", "memory");
 }
 
 static inline int arch_read_trylock(arch_rwlock_t *rw)
@@ -177,14 +177,14 @@ static inline int arch_read_trylock(arch_rwlock_t *rw)
         unsigned int tmp, tmp2 = 1;
 
         asm volatile(
-        "       ldaxr   %w0, [%2]\n"
+        "       ldaxr   %w0, %2\n"
         "       add     %w0, %w0, #1\n"
         "       tbnz    %w0, #31, 1f\n"
-        "       stxr    %w1, %w0, [%2]\n"
+        "       stxr    %w1, %w0, %2\n"
         "1:\n"
-        : "=&r" (tmp), "+r" (tmp2)
-        : "r" (&rw->lock)
-        : "memory");
+        : "=&r" (tmp), "+r" (tmp2), "+Q" (rw->lock)
+        :
+        : "cc", "memory");
 
         return !tmp2;
 }