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-rw-r--r--arch/arm/plat-samsung/Kconfig15
-rw-r--r--arch/arm/plat-samsung/Makefile6
-rw-r--r--arch/arm/plat-samsung/dma-ops.c146
-rw-r--r--arch/arm/plat-samsung/dma.c84
-rw-r--r--arch/arm/plat-samsung/include/plat/dma-core.h22
-rw-r--r--arch/arm/plat-samsung/include/plat/dma-ops.h69
-rw-r--r--arch/arm/plat-samsung/include/plat/dma-pl330.h121
-rw-r--r--arch/arm/plat-samsung/include/plat/dma-s3c24xx.h73
-rw-r--r--arch/arm/plat-samsung/include/plat/dma.h130
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-dma.h151
-rw-r--r--arch/arm/plat-samsung/s3c-dma-ops.c146
11 files changed, 0 insertions, 963 deletions
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 9bd2776e7d05..cb8e3d655d1a 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -236,13 +236,6 @@ config S3C_SETUP_CAMIF
236 help 236 help
237 Compile in common setup code for S3C CAMIF devices 237 Compile in common setup code for S3C CAMIF devices
238 238
239# DMA
240
241config S3C_DMA
242 bool
243 help
244 Internal configuration for S3C DMA core
245
246config SAMSUNG_PM_GPIO 239config SAMSUNG_PM_GPIO
247 bool 240 bool
248 default y if GPIO_SAMSUNG && PM 241 default y if GPIO_SAMSUNG && PM
@@ -250,14 +243,6 @@ config SAMSUNG_PM_GPIO
250 Include legacy GPIO power management code for platforms not using 243 Include legacy GPIO power management code for platforms not using
251 pinctrl-samsung driver. 244 pinctrl-samsung driver.
252 245
253config SAMSUNG_DMADEV
254 bool "Use legacy Samsung DMA abstraction"
255 depends on CPU_S5PV210 || ARCH_S3C64XX
256 select DMADEVICES
257 default y
258 help
259 Use DMA device engine for PL330 DMAC.
260
261endif 246endif
262 247
263config S5P_DEV_MFC 248config S5P_DEV_MFC
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 87746c37f030..1a29ab1f446d 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -26,12 +26,6 @@ obj-$(CONFIG_SAMSUNG_DEV_BACKLIGHT) += dev-backlight.o
26 26
27obj-$(CONFIG_S3C_SETUP_CAMIF) += setup-camif.o 27obj-$(CONFIG_S3C_SETUP_CAMIF) += setup-camif.o
28 28
29# DMA support
30
31obj-$(CONFIG_S3C_DMA) += dma.o s3c-dma-ops.o
32
33obj-$(CONFIG_SAMSUNG_DMADEV) += dma-ops.o
34
35# PM support 29# PM support
36 30
37obj-$(CONFIG_PM_SLEEP) += pm-common.o 31obj-$(CONFIG_PM_SLEEP) += pm-common.o
diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
deleted file mode 100644
index 886326ee6f6c..000000000000
--- a/arch/arm/plat-samsung/dma-ops.c
+++ /dev/null
@@ -1,146 +0,0 @@
1/* linux/arch/arm/plat-samsung/dma-ops.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Samsung DMA Operations
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
14#include <linux/errno.h>
15#include <linux/amba/pl330.h>
16#include <linux/scatterlist.h>
17#include <linux/export.h>
18
19#include <mach/dma.h>
20
21#if defined(CONFIG_PL330_DMA)
22#define dma_filter pl330_filter
23#elif defined(CONFIG_S3C64XX_PL080)
24#define dma_filter pl08x_filter_id
25#endif
26
27static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
28 struct samsung_dma_req *param,
29 struct device *dev, char *ch_name)
30{
31 dma_cap_mask_t mask;
32
33 dma_cap_zero(mask);
34 dma_cap_set(param->cap, mask);
35
36 if (dev->of_node)
37 return (unsigned)dma_request_slave_channel(dev, ch_name);
38 else
39 return (unsigned)dma_request_channel(mask, dma_filter,
40 (void *)dma_ch);
41}
42
43static int samsung_dmadev_release(unsigned ch, void *param)
44{
45 dma_release_channel((struct dma_chan *)ch);
46
47 return 0;
48}
49
50static int samsung_dmadev_config(unsigned ch,
51 struct samsung_dma_config *param)
52{
53 struct dma_chan *chan = (struct dma_chan *)ch;
54 struct dma_slave_config slave_config;
55
56 if (param->direction == DMA_DEV_TO_MEM) {
57 memset(&slave_config, 0, sizeof(struct dma_slave_config));
58 slave_config.direction = param->direction;
59 slave_config.src_addr = param->fifo;
60 slave_config.src_addr_width = param->width;
61 slave_config.src_maxburst = 1;
62 dmaengine_slave_config(chan, &slave_config);
63 } else if (param->direction == DMA_MEM_TO_DEV) {
64 memset(&slave_config, 0, sizeof(struct dma_slave_config));
65 slave_config.direction = param->direction;
66 slave_config.dst_addr = param->fifo;
67 slave_config.dst_addr_width = param->width;
68 slave_config.dst_maxburst = 1;
69 dmaengine_slave_config(chan, &slave_config);
70 } else {
71 pr_warn("unsupported direction\n");
72 return -EINVAL;
73 }
74
75 return 0;
76}
77
78static int samsung_dmadev_prepare(unsigned ch,
79 struct samsung_dma_prep *param)
80{
81 struct scatterlist sg;
82 struct dma_chan *chan = (struct dma_chan *)ch;
83 struct dma_async_tx_descriptor *desc;
84
85 switch (param->cap) {
86 case DMA_SLAVE:
87 sg_init_table(&sg, 1);
88 sg_dma_len(&sg) = param->len;
89 sg_set_page(&sg, pfn_to_page(PFN_DOWN(param->buf)),
90 param->len, offset_in_page(param->buf));
91 sg_dma_address(&sg) = param->buf;
92
93 desc = dmaengine_prep_slave_sg(chan,
94 &sg, 1, param->direction, DMA_PREP_INTERRUPT);
95 break;
96 case DMA_CYCLIC:
97 desc = dmaengine_prep_dma_cyclic(chan, param->buf,
98 param->len, param->period, param->direction,
99 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
100 break;
101 default:
102 dev_err(&chan->dev->device, "unsupported format\n");
103 return -EFAULT;
104 }
105
106 if (!desc) {
107 dev_err(&chan->dev->device, "cannot prepare cyclic dma\n");
108 return -EFAULT;
109 }
110
111 desc->callback = param->fp;
112 desc->callback_param = param->fp_param;
113
114 dmaengine_submit((struct dma_async_tx_descriptor *)desc);
115
116 return 0;
117}
118
119static inline int samsung_dmadev_trigger(unsigned ch)
120{
121 dma_async_issue_pending((struct dma_chan *)ch);
122
123 return 0;
124}
125
126static inline int samsung_dmadev_flush(unsigned ch)
127{
128 return dmaengine_terminate_all((struct dma_chan *)ch);
129}
130
131static struct samsung_dma_ops dmadev_ops = {
132 .request = samsung_dmadev_request,
133 .release = samsung_dmadev_release,
134 .config = samsung_dmadev_config,
135 .prepare = samsung_dmadev_prepare,
136 .trigger = samsung_dmadev_trigger,
137 .started = NULL,
138 .flush = samsung_dmadev_flush,
139 .stop = samsung_dmadev_flush,
140};
141
142void *samsung_dmadev_get_ops(void)
143{
144 return &dmadev_ops;
145}
146EXPORT_SYMBOL(samsung_dmadev_get_ops);
diff --git a/arch/arm/plat-samsung/dma.c b/arch/arm/plat-samsung/dma.c
deleted file mode 100644
index 6143aa147688..000000000000
--- a/arch/arm/plat-samsung/dma.c
+++ /dev/null
@@ -1,84 +0,0 @@
1/* linux/arch/arm/plat-samsung/dma.c
2 *
3 * Copyright (c) 2003-2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C DMA core
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14struct s3c2410_dma_buf;
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/errno.h>
19
20#include <mach/dma.h>
21#include <mach/irqs.h>
22
23/* dma channel state information */
24struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
25struct s3c2410_dma_chan *s3c_dma_chan_map[DMACH_MAX];
26
27/* s3c_dma_lookup_channel
28 *
29 * change the dma channel number given into a real dma channel id
30*/
31
32struct s3c2410_dma_chan *s3c_dma_lookup_channel(unsigned int channel)
33{
34 if (channel & DMACH_LOW_LEVEL)
35 return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL];
36 else
37 return s3c_dma_chan_map[channel];
38}
39
40/* do we need to protect the settings of the fields from
41 * irq?
42*/
43
44int s3c2410_dma_set_opfn(enum dma_ch channel, s3c2410_dma_opfn_t rtn)
45{
46 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
47
48 if (chan == NULL)
49 return -EINVAL;
50
51 pr_debug("%s: chan=%p, op rtn=%p\n", __func__, chan, rtn);
52
53 chan->op_fn = rtn;
54
55 return 0;
56}
57EXPORT_SYMBOL(s3c2410_dma_set_opfn);
58
59int s3c2410_dma_set_buffdone_fn(enum dma_ch channel, s3c2410_dma_cbfn_t rtn)
60{
61 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
62
63 if (chan == NULL)
64 return -EINVAL;
65
66 pr_debug("%s: chan=%p, callback rtn=%p\n", __func__, chan, rtn);
67
68 chan->callback_fn = rtn;
69
70 return 0;
71}
72EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
73
74int s3c2410_dma_setflags(enum dma_ch channel, unsigned int flags)
75{
76 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
77
78 if (chan == NULL)
79 return -EINVAL;
80
81 chan->flags = flags;
82 return 0;
83}
84EXPORT_SYMBOL(s3c2410_dma_setflags);
diff --git a/arch/arm/plat-samsung/include/plat/dma-core.h b/arch/arm/plat-samsung/include/plat/dma-core.h
deleted file mode 100644
index 32ff2a92cb3c..000000000000
--- a/arch/arm/plat-samsung/include/plat/dma-core.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/* arch/arm/plat-s3c/include/plat/dma.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * Samsung S3C DMA core support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15extern struct s3c2410_dma_chan *s3c_dma_lookup_channel(unsigned int channel);
16
17extern struct s3c2410_dma_chan *s3c_dma_chan_map[];
18
19/* the currently allocated channel information */
20extern struct s3c2410_dma_chan s3c2410_chans[];
21
22
diff --git a/arch/arm/plat-samsung/include/plat/dma-ops.h b/arch/arm/plat-samsung/include/plat/dma-ops.h
deleted file mode 100644
index ce6d7634b6cb..000000000000
--- a/arch/arm/plat-samsung/include/plat/dma-ops.h
+++ /dev/null
@@ -1,69 +0,0 @@
1/* arch/arm/plat-samsung/include/plat/dma-ops.h
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Samsung DMA support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __SAMSUNG_DMA_OPS_H_
14#define __SAMSUNG_DMA_OPS_H_ __FILE__
15
16#include <linux/dmaengine.h>
17#include <mach/dma.h>
18
19struct samsung_dma_req {
20 enum dma_transaction_type cap;
21 struct s3c2410_dma_client *client;
22};
23
24struct samsung_dma_prep {
25 enum dma_transaction_type cap;
26 enum dma_transfer_direction direction;
27 dma_addr_t buf;
28 unsigned long period;
29 unsigned long len;
30 void (*fp)(void *data);
31 void *fp_param;
32};
33
34struct samsung_dma_config {
35 enum dma_transfer_direction direction;
36 enum dma_slave_buswidth width;
37 dma_addr_t fifo;
38};
39
40struct samsung_dma_ops {
41 unsigned (*request)(enum dma_ch ch, struct samsung_dma_req *param,
42 struct device *dev, char *ch_name);
43 int (*release)(unsigned ch, void *param);
44 int (*config)(unsigned ch, struct samsung_dma_config *param);
45 int (*prepare)(unsigned ch, struct samsung_dma_prep *param);
46 int (*trigger)(unsigned ch);
47 int (*started)(unsigned ch);
48 int (*flush)(unsigned ch);
49 int (*stop)(unsigned ch);
50};
51
52extern void *samsung_dmadev_get_ops(void);
53extern void *s3c_dma_get_ops(void);
54
55static inline void *__samsung_dma_get_ops(void)
56{
57 if (samsung_dma_is_dmadev())
58 return samsung_dmadev_get_ops();
59 else
60 return s3c_dma_get_ops();
61}
62
63/*
64 * samsung_dma_get_ops
65 * get the set of samsung dma operations
66 */
67#define samsung_dma_get_ops() __samsung_dma_get_ops()
68
69#endif /* __SAMSUNG_DMA_OPS_H_ */
diff --git a/arch/arm/plat-samsung/include/plat/dma-pl330.h b/arch/arm/plat-samsung/include/plat/dma-pl330.h
deleted file mode 100644
index abe07fae71db..000000000000
--- a/arch/arm/plat-samsung/include/plat/dma-pl330.h
+++ /dev/null
@@ -1,121 +0,0 @@
1/*
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10
11#ifndef __DMA_PL330_H_
12#define __DMA_PL330_H_ __FILE__
13
14/*
15 * PL330 can assign any channel to communicate with
16 * any of the peripherals attched to the DMAC.
17 * For the sake of consistency across client drivers,
18 * We keep the channel names unchanged and only add
19 * missing peripherals are added.
20 * Order is not important since DMA PL330 API driver
21 * use these just as IDs.
22 */
23enum dma_ch {
24 DMACH_UART0_RX = 0,
25 DMACH_UART0_TX,
26 DMACH_UART1_RX,
27 DMACH_UART1_TX,
28 DMACH_UART2_RX,
29 DMACH_UART2_TX,
30 DMACH_UART3_RX,
31 DMACH_UART3_TX,
32 DMACH_UART4_RX,
33 DMACH_UART4_TX,
34 DMACH_UART5_RX,
35 DMACH_UART5_TX,
36 DMACH_USI_RX,
37 DMACH_USI_TX,
38 DMACH_IRDA,
39 DMACH_I2S0_RX,
40 DMACH_I2S0_TX,
41 DMACH_I2S0S_TX,
42 DMACH_I2S1_RX,
43 DMACH_I2S1_TX,
44 DMACH_I2S2_RX,
45 DMACH_I2S2_TX,
46 DMACH_SPI0_RX,
47 DMACH_SPI0_TX,
48 DMACH_SPI1_RX,
49 DMACH_SPI1_TX,
50 DMACH_SPI2_RX,
51 DMACH_SPI2_TX,
52 DMACH_AC97_MICIN,
53 DMACH_AC97_PCMIN,
54 DMACH_AC97_PCMOUT,
55 DMACH_EXTERNAL,
56 DMACH_PWM,
57 DMACH_SPDIF,
58 DMACH_HSI_RX,
59 DMACH_HSI_TX,
60 DMACH_PCM0_TX,
61 DMACH_PCM0_RX,
62 DMACH_PCM1_TX,
63 DMACH_PCM1_RX,
64 DMACH_PCM2_TX,
65 DMACH_PCM2_RX,
66 DMACH_MSM_REQ3,
67 DMACH_MSM_REQ2,
68 DMACH_MSM_REQ1,
69 DMACH_MSM_REQ0,
70 DMACH_SLIMBUS0_RX,
71 DMACH_SLIMBUS0_TX,
72 DMACH_SLIMBUS0AUX_RX,
73 DMACH_SLIMBUS0AUX_TX,
74 DMACH_SLIMBUS1_RX,
75 DMACH_SLIMBUS1_TX,
76 DMACH_SLIMBUS2_RX,
77 DMACH_SLIMBUS2_TX,
78 DMACH_SLIMBUS3_RX,
79 DMACH_SLIMBUS3_TX,
80 DMACH_SLIMBUS4_RX,
81 DMACH_SLIMBUS4_TX,
82 DMACH_SLIMBUS5_RX,
83 DMACH_SLIMBUS5_TX,
84 DMACH_MIPI_HSI0,
85 DMACH_MIPI_HSI1,
86 DMACH_MIPI_HSI2,
87 DMACH_MIPI_HSI3,
88 DMACH_MIPI_HSI4,
89 DMACH_MIPI_HSI5,
90 DMACH_MIPI_HSI6,
91 DMACH_MIPI_HSI7,
92 DMACH_DISP1,
93 DMACH_MTOM_0,
94 DMACH_MTOM_1,
95 DMACH_MTOM_2,
96 DMACH_MTOM_3,
97 DMACH_MTOM_4,
98 DMACH_MTOM_5,
99 DMACH_MTOM_6,
100 DMACH_MTOM_7,
101 /* END Marker, also used to denote a reserved channel */
102 DMACH_MAX,
103};
104
105struct s3c2410_dma_client {
106 char *name;
107};
108
109static inline bool samsung_dma_has_circular(void)
110{
111 return true;
112}
113
114static inline bool samsung_dma_is_dmadev(void)
115{
116 return true;
117}
118
119#include <plat/dma-ops.h>
120
121#endif /* __DMA_PL330_H_ */
diff --git a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
deleted file mode 100644
index bd3a6db14cbb..000000000000
--- a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
+++ /dev/null
@@ -1,73 +0,0 @@
1/* linux/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
2 *
3 * Copyright (C) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C24XX DMA support - per SoC functions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <plat/dma-core.h>
14
15extern struct bus_type dma_subsys;
16extern struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
17
18#define DMA_CH_VALID (1<<31)
19#define DMA_CH_NEVER (1<<30)
20
21/* struct s3c24xx_dma_map
22 *
23 * this holds the mapping information for the channel selected
24 * to be connected to the specified device
25*/
26
27struct s3c24xx_dma_map {
28 const char *name;
29
30 unsigned long channels[S3C_DMA_CHANNELS];
31};
32
33struct s3c24xx_dma_selection {
34 struct s3c24xx_dma_map *map;
35 unsigned long map_size;
36 unsigned long dcon_mask;
37
38 void (*select)(struct s3c2410_dma_chan *chan,
39 struct s3c24xx_dma_map *map);
40};
41
42extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
43
44/* struct s3c24xx_dma_order_ch
45 *
46 * channel map for one of the `enum dma_ch` dma channels. the list
47 * entry contains a set of low-level channel numbers, orred with
48 * DMA_CH_VALID, which are checked in the order in the array.
49*/
50
51struct s3c24xx_dma_order_ch {
52 unsigned int list[S3C_DMA_CHANNELS]; /* list of channels */
53 unsigned int flags; /* flags */
54};
55
56/* struct s3c24xx_dma_order
57 *
58 * information provided by either the core or the board to give the
59 * dma system a hint on how to allocate channels
60*/
61
62struct s3c24xx_dma_order {
63 struct s3c24xx_dma_order_ch channels[DMACH_MAX];
64};
65
66extern int s3c24xx_dma_order_set(struct s3c24xx_dma_order *map);
67
68/* DMA init code, called from the cpu support code */
69
70extern int s3c2410_dma_init(void);
71
72extern int s3c24xx_dma_init(unsigned int channels, unsigned int irq,
73 unsigned int stride);
diff --git a/arch/arm/plat-samsung/include/plat/dma.h b/arch/arm/plat-samsung/include/plat/dma.h
deleted file mode 100644
index 7b02143ccd9a..000000000000
--- a/arch/arm/plat-samsung/include/plat/dma.h
+++ /dev/null
@@ -1,130 +0,0 @@
1/* arch/arm/plat-samsung/include/plat/dma.h
2 *
3 * Copyright (C) 2003-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C DMA support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __PLAT_DMA_H
14#define __PLAT_DMA_H
15
16#include <linux/dma-mapping.h>
17
18enum s3c2410_dma_buffresult {
19 S3C2410_RES_OK,
20 S3C2410_RES_ERR,
21 S3C2410_RES_ABORT
22};
23
24/* enum s3c2410_chan_op
25 *
26 * operation codes passed to the DMA code by the user, and also used
27 * to inform the current channel owner of any changes to the system state
28*/
29
30enum s3c2410_chan_op {
31 S3C2410_DMAOP_START,
32 S3C2410_DMAOP_STOP,
33 S3C2410_DMAOP_PAUSE,
34 S3C2410_DMAOP_RESUME,
35 S3C2410_DMAOP_FLUSH,
36 S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */
37 S3C2410_DMAOP_STARTED, /* indicate channel started */
38};
39
40struct s3c2410_dma_client {
41 char *name;
42};
43
44struct s3c2410_dma_chan;
45enum dma_ch;
46
47/* s3c2410_dma_cbfn_t
48 *
49 * buffer callback routine type
50*/
51
52typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
53 void *buf, int size,
54 enum s3c2410_dma_buffresult result);
55
56typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
57 enum s3c2410_chan_op );
58
59
60
61/* s3c2410_dma_request
62 *
63 * request a dma channel exclusivley
64*/
65
66extern int s3c2410_dma_request(enum dma_ch channel,
67 struct s3c2410_dma_client *, void *dev);
68
69
70/* s3c2410_dma_ctrl
71 *
72 * change the state of the dma channel
73*/
74
75extern int s3c2410_dma_ctrl(enum dma_ch channel, enum s3c2410_chan_op op);
76
77/* s3c2410_dma_setflags
78 *
79 * set the channel's flags to a given state
80*/
81
82extern int s3c2410_dma_setflags(enum dma_ch channel,
83 unsigned int flags);
84
85/* s3c2410_dma_free
86 *
87 * free the dma channel (will also abort any outstanding operations)
88*/
89
90extern int s3c2410_dma_free(enum dma_ch channel, struct s3c2410_dma_client *);
91
92/* s3c2410_dma_enqueue
93 *
94 * place the given buffer onto the queue of operations for the channel.
95 * The buffer must be allocated from dma coherent memory, or the Dcache/WB
96 * drained before the buffer is given to the DMA system.
97*/
98
99extern int s3c2410_dma_enqueue(enum dma_ch channel, void *id,
100 dma_addr_t data, int size);
101
102/* s3c2410_dma_config
103 *
104 * configure the dma channel
105*/
106
107extern int s3c2410_dma_config(enum dma_ch channel, int xferunit);
108
109/* s3c2410_dma_devconfig
110 *
111 * configure the device we're talking to
112*/
113
114extern int s3c2410_dma_devconfig(enum dma_ch channel,
115 enum dma_data_direction source, unsigned long devaddr);
116
117/* s3c2410_dma_getposition
118 *
119 * get the position that the dma transfer is currently at
120*/
121
122extern int s3c2410_dma_getposition(enum dma_ch channel,
123 dma_addr_t *src, dma_addr_t *dest);
124
125extern int s3c2410_dma_set_opfn(enum dma_ch, s3c2410_dma_opfn_t rtn);
126extern int s3c2410_dma_set_buffdone_fn(enum dma_ch, s3c2410_dma_cbfn_t rtn);
127
128#include <plat/dma-ops.h>
129
130#endif
diff --git a/arch/arm/plat-samsung/include/plat/regs-dma.h b/arch/arm/plat-samsung/include/plat/regs-dma.h
deleted file mode 100644
index a7d622ef16af..000000000000
--- a/arch/arm/plat-samsung/include/plat/regs-dma.h
+++ /dev/null
@@ -1,151 +0,0 @@
1/* arch/arm/plat-samsung/include/plat/regs-dma.h
2 *
3 * Copyright (C) 2003-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C24XX DMA support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_PLAT_REGS_DMA_H
14#define __ASM_PLAT_REGS_DMA_H __FILE__
15
16#define S3C2410_DMA_DISRC (0x00)
17#define S3C2410_DMA_DISRCC (0x04)
18#define S3C2410_DMA_DIDST (0x08)
19#define S3C2410_DMA_DIDSTC (0x0C)
20#define S3C2410_DMA_DCON (0x10)
21#define S3C2410_DMA_DSTAT (0x14)
22#define S3C2410_DMA_DCSRC (0x18)
23#define S3C2410_DMA_DCDST (0x1C)
24#define S3C2410_DMA_DMASKTRIG (0x20)
25#define S3C2412_DMA_DMAREQSEL (0x24)
26#define S3C2443_DMA_DMAREQSEL (0x24)
27
28#define S3C2410_DISRCC_INC (1 << 0)
29#define S3C2410_DISRCC_APB (1 << 1)
30
31#define S3C2410_DMASKTRIG_STOP (1 << 2)
32#define S3C2410_DMASKTRIG_ON (1 << 1)
33#define S3C2410_DMASKTRIG_SWTRIG (1 << 0)
34
35#define S3C2410_DCON_DEMAND (0 << 31)
36#define S3C2410_DCON_HANDSHAKE (1 << 31)
37#define S3C2410_DCON_SYNC_PCLK (0 << 30)
38#define S3C2410_DCON_SYNC_HCLK (1 << 30)
39
40#define S3C2410_DCON_INTREQ (1 << 29)
41
42#define S3C2410_DCON_CH0_XDREQ0 (0 << 24)
43#define S3C2410_DCON_CH0_UART0 (1 << 24)
44#define S3C2410_DCON_CH0_SDI (2 << 24)
45#define S3C2410_DCON_CH0_TIMER (3 << 24)
46#define S3C2410_DCON_CH0_USBEP1 (4 << 24)
47
48#define S3C2410_DCON_CH1_XDREQ1 (0 << 24)
49#define S3C2410_DCON_CH1_UART1 (1 << 24)
50#define S3C2410_DCON_CH1_I2SSDI (2 << 24)
51#define S3C2410_DCON_CH1_SPI (3 << 24)
52#define S3C2410_DCON_CH1_USBEP2 (4 << 24)
53
54#define S3C2410_DCON_CH2_I2SSDO (0 << 24)
55#define S3C2410_DCON_CH2_I2SSDI (1 << 24)
56#define S3C2410_DCON_CH2_SDI (2 << 24)
57#define S3C2410_DCON_CH2_TIMER (3 << 24)
58#define S3C2410_DCON_CH2_USBEP3 (4 << 24)
59
60#define S3C2410_DCON_CH3_UART2 (0 << 24)
61#define S3C2410_DCON_CH3_SDI (1 << 24)
62#define S3C2410_DCON_CH3_SPI (2 << 24)
63#define S3C2410_DCON_CH3_TIMER (3 << 24)
64#define S3C2410_DCON_CH3_USBEP4 (4 << 24)
65
66#define S3C2410_DCON_SRCSHIFT (24)
67#define S3C2410_DCON_SRCMASK (7 << 24)
68
69#define S3C2410_DCON_BYTE (0 << 20)
70#define S3C2410_DCON_HALFWORD (1 << 20)
71#define S3C2410_DCON_WORD (2 << 20)
72
73#define S3C2410_DCON_AUTORELOAD (0 << 22)
74#define S3C2410_DCON_NORELOAD (1 << 22)
75#define S3C2410_DCON_HWTRIG (1 << 23)
76
77#ifdef CONFIG_CPU_S3C2440
78
79#define S3C2440_DIDSTC_CHKINT (1 << 2)
80
81#define S3C2440_DCON_CH0_I2SSDO (5 << 24)
82#define S3C2440_DCON_CH0_PCMIN (6 << 24)
83
84#define S3C2440_DCON_CH1_PCMOUT (5 << 24)
85#define S3C2440_DCON_CH1_SDI (6 << 24)
86
87#define S3C2440_DCON_CH2_PCMIN (5 << 24)
88#define S3C2440_DCON_CH2_MICIN (6 << 24)
89
90#define S3C2440_DCON_CH3_MICIN (5 << 24)
91#define S3C2440_DCON_CH3_PCMOUT (6 << 24)
92#endif /* CONFIG_CPU_S3C2440 */
93
94#ifdef CONFIG_CPU_S3C2412
95
96#define S3C2412_DMAREQSEL_SRC(x) ((x) << 1)
97
98#define S3C2412_DMAREQSEL_HW (1)
99
100#define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0)
101#define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1)
102#define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2)
103#define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3)
104#define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4)
105#define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5)
106#define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9)
107#define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10)
108#define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13)
109#define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14)
110#define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15)
111#define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16)
112#define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17)
113#define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18)
114#define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19)
115#define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20)
116#define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21)
117#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22)
118#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23)
119#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24)
120#endif /* CONFIG_CPU_S3C2412 */
121
122#if defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2443)
123
124#define S3C2443_DMAREQSEL_SRC(x) ((x) << 1)
125
126#define S3C2443_DMAREQSEL_HW (1)
127
128#define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0)
129#define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1)
130#define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2)
131#define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3)
132#define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4)
133#define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5)
134#define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9)
135#define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10)
136#define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17)
137#define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18)
138#define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19)
139#define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20)
140#define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21)
141#define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22)
142#define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23)
143#define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24)
144#define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25)
145#define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26)
146#define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27)
147#define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28)
148#define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29)
149#endif /* CONFIG_CPU_S3C2443 */
150
151#endif /* __ASM_PLAT_REGS_DMA_H */
diff --git a/arch/arm/plat-samsung/s3c-dma-ops.c b/arch/arm/plat-samsung/s3c-dma-ops.c
deleted file mode 100644
index 98b10ba67dc7..000000000000
--- a/arch/arm/plat-samsung/s3c-dma-ops.c
+++ /dev/null
@@ -1,146 +0,0 @@
1/* linux/arch/arm/plat-samsung/s3c-dma-ops.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Samsung S3C-DMA Operations
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
14#include <linux/errno.h>
15#include <linux/slab.h>
16#include <linux/types.h>
17#include <linux/export.h>
18
19#include <mach/dma.h>
20
21struct cb_data {
22 void (*fp) (void *);
23 void *fp_param;
24 unsigned ch;
25 struct list_head node;
26};
27
28static LIST_HEAD(dma_list);
29
30static void s3c_dma_cb(struct s3c2410_dma_chan *channel, void *param,
31 int size, enum s3c2410_dma_buffresult res)
32{
33 struct cb_data *data = param;
34
35 data->fp(data->fp_param);
36}
37
38static unsigned s3c_dma_request(enum dma_ch dma_ch,
39 struct samsung_dma_req *param,
40 struct device *dev, char *ch_name)
41{
42 struct cb_data *data;
43
44 if (s3c2410_dma_request(dma_ch, param->client, NULL) < 0) {
45 s3c2410_dma_free(dma_ch, param->client);
46 return 0;
47 }
48
49 if (param->cap == DMA_CYCLIC)
50 s3c2410_dma_setflags(dma_ch, S3C2410_DMAF_CIRCULAR);
51
52 data = kzalloc(sizeof(struct cb_data), GFP_KERNEL);
53 data->ch = dma_ch;
54 list_add_tail(&data->node, &dma_list);
55
56 return (unsigned)dma_ch;
57}
58
59static int s3c_dma_release(unsigned ch, void *param)
60{
61 struct cb_data *data;
62
63 list_for_each_entry(data, &dma_list, node)
64 if (data->ch == ch)
65 break;
66 list_del(&data->node);
67
68 s3c2410_dma_free(ch, param);
69 kfree(data);
70
71 return 0;
72}
73
74static int s3c_dma_config(unsigned ch, struct samsung_dma_config *param)
75{
76 s3c2410_dma_devconfig(ch, param->direction, param->fifo);
77 s3c2410_dma_config(ch, param->width);
78
79 return 0;
80}
81
82static int s3c_dma_prepare(unsigned ch, struct samsung_dma_prep *param)
83{
84 struct cb_data *data;
85 dma_addr_t pos = param->buf;
86 dma_addr_t end = param->buf + param->len;
87
88 list_for_each_entry(data, &dma_list, node)
89 if (data->ch == ch)
90 break;
91
92 if (!data->fp) {
93 s3c2410_dma_set_buffdone_fn(ch, s3c_dma_cb);
94 data->fp = param->fp;
95 data->fp_param = param->fp_param;
96 }
97
98 if (param->cap != DMA_CYCLIC) {
99 s3c2410_dma_enqueue(ch, (void *)data, param->buf, param->len);
100 return 0;
101 }
102
103 while (pos < end) {
104 s3c2410_dma_enqueue(ch, (void *)data, pos, param->period);
105 pos += param->period;
106 }
107
108 return 0;
109}
110
111static inline int s3c_dma_trigger(unsigned ch)
112{
113 return s3c2410_dma_ctrl(ch, S3C2410_DMAOP_START);
114}
115
116static inline int s3c_dma_started(unsigned ch)
117{
118 return s3c2410_dma_ctrl(ch, S3C2410_DMAOP_STARTED);
119}
120
121static inline int s3c_dma_flush(unsigned ch)
122{
123 return s3c2410_dma_ctrl(ch, S3C2410_DMAOP_FLUSH);
124}
125
126static inline int s3c_dma_stop(unsigned ch)
127{
128 return s3c2410_dma_ctrl(ch, S3C2410_DMAOP_STOP);
129}
130
131static struct samsung_dma_ops s3c_dma_ops = {
132 .request = s3c_dma_request,
133 .release = s3c_dma_release,
134 .config = s3c_dma_config,
135 .prepare = s3c_dma_prepare,
136 .trigger = s3c_dma_trigger,
137 .started = s3c_dma_started,
138 .flush = s3c_dma_flush,
139 .stop = s3c_dma_stop,
140};
141
142void *s3c_dma_get_ops(void)
143{
144 return &s3c_dma_ops;
145}
146EXPORT_SYMBOL(s3c_dma_get_ops);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 01:20:20 -0500