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-rw-r--r--arch/arm/plat-samsung/include/plat/adc.h35
-rw-r--r--arch/arm/plat-samsung/include/plat/audio.h25
-rw-r--r--arch/arm/plat-samsung/include/plat/clock-clksrc.h83
-rw-r--r--arch/arm/plat-samsung/include/plat/clock.h115
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu-freq.h145
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu.h84
-rw-r--r--arch/arm/plat-samsung/include/plat/debug-macro.S87
-rw-r--r--arch/arm/plat-samsung/include/plat/devs.h74
-rw-r--r--arch/arm/plat-samsung/include/plat/dma-core.h22
-rw-r--r--arch/arm/plat-samsung/include/plat/dma-s3c24xx.h84
-rw-r--r--arch/arm/plat-samsung/include/plat/dma.h127
-rw-r--r--arch/arm/plat-samsung/include/plat/fb.h80
-rw-r--r--arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h176
-rw-r--r--arch/arm/plat-samsung/include/plat/gpio-cfg.h110
-rw-r--r--arch/arm/plat-samsung/include/plat/gpio-core.h137
-rw-r--r--arch/arm/plat-samsung/include/plat/hwmon.h41
-rw-r--r--arch/arm/plat-samsung/include/plat/iic-core.h35
-rw-r--r--arch/arm/plat-samsung/include/plat/iic.h62
-rw-r--r--arch/arm/plat-samsung/include/plat/irq-uart.h20
-rw-r--r--arch/arm/plat-samsung/include/plat/irq-vic-timer.h13
-rw-r--r--arch/arm/plat-samsung/include/plat/map-base.h46
-rw-r--r--arch/arm/plat-samsung/include/plat/nand.h67
-rw-r--r--arch/arm/plat-samsung/include/plat/pm.h189
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-ac97.h67
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-adc.h64
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-fb-v4.h235
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-fb.h366
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-iic.h56
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-irqtype.h21
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-nand.h123
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-rtc.h61
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-s3c2412-iis.h82
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-sdhci.h87
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-serial.h281
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-timer.h124
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h50
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h377
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-watchdog.h41
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c64xx-spi.h67
-rw-r--r--arch/arm/plat-samsung/include/plat/sdhci.h221
-rw-r--r--arch/arm/plat-samsung/include/plat/udc-hs.h29
-rw-r--r--arch/arm/plat-samsung/include/plat/uncompress.h186
-rw-r--r--arch/arm/plat-samsung/include/plat/usb-control.h43
-rw-r--r--arch/arm/plat-samsung/include/plat/watchdog-reset.h49
44 files changed, 4487 insertions, 0 deletions
diff --git a/arch/arm/plat-samsung/include/plat/adc.h b/arch/arm/plat-samsung/include/plat/adc.h
new file mode 100644
index 000000000000..e8382c7be10b
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/adc.h
@@ -0,0 +1,35 @@
1/* arch/arm/plat-samsung/include/plat/adc.h
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * http://armlinux.simnte.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C ADC driver information
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_PLAT_ADC_H
15#define __ASM_PLAT_ADC_H __FILE__
16
17struct s3c_adc_client;
18
19extern int s3c_adc_start(struct s3c_adc_client *client,
20 unsigned int channel, unsigned int nr_samples);
21
22extern int s3c_adc_read(struct s3c_adc_client *client, unsigned int ch);
23
24extern struct s3c_adc_client *
25 s3c_adc_register(struct platform_device *pdev,
26 void (*select)(struct s3c_adc_client *client,
27 unsigned selected),
28 void (*conv)(struct s3c_adc_client *client,
29 unsigned d0, unsigned d1,
30 unsigned *samples_left),
31 unsigned int is_ts);
32
33extern void s3c_adc_release(struct s3c_adc_client *client);
34
35#endif /* __ASM_PLAT_ADC_H */
diff --git a/arch/arm/plat-samsung/include/plat/audio.h b/arch/arm/plat-samsung/include/plat/audio.h
new file mode 100644
index 000000000000..e32f9edfd4b7
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/audio.h
@@ -0,0 +1,25 @@
1/* arch/arm/plat-samsung/include/plat/audio.h
2 *
3 * Copyright (c) 2009 Samsung Electronics Co. Ltd
4 * Author: Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11/* The machine init code calls s3c*_ac97_setup_gpio with
12 * one of these defines in order to select appropriate bank
13 * of GPIO for AC97 pins
14 */
15#define S3C64XX_AC97_GPD 0
16#define S3C64XX_AC97_GPE 1
17extern void s3c64xx_ac97_setup_gpio(int);
18
19/**
20 * struct s3c_audio_pdata - common platform data for audio device drivers
21 * @cfg_gpio: Callback function to setup mux'ed pins in I2S/PCM/AC97 mode
22 */
23struct s3c_audio_pdata {
24 int (*cfg_gpio)(struct platform_device *);
25};
diff --git a/arch/arm/plat-samsung/include/plat/clock-clksrc.h b/arch/arm/plat-samsung/include/plat/clock-clksrc.h
new file mode 100644
index 000000000000..50a8ca7c3760
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/clock-clksrc.h
@@ -0,0 +1,83 @@
1/* linux/arch/arm/plat-samsung/include/plat/clock-clksrc.h
2 *
3 * Parts taken from arch/arm/plat-s3c64xx/clock.c
4 * Copyright 2008 Openmoko, Inc.
5 * Copyright 2008 Simtec Electronics
6 * Ben Dooks <ben@simtec.co.uk>
7 * http://armlinux.simtec.co.uk/
8 *
9 * Copyright 2009 Ben Dooks <ben-linux@fluff.org>
10 * Copyright 2009 Harald Welte
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15*/
16
17/**
18 * struct clksrc_sources - list of sources for a given clock
19 * @sources: array of pointers to clocks
20 * @nr_sources: The size of @sources
21 */
22struct clksrc_sources {
23 unsigned int nr_sources;
24 struct clk **sources;
25};
26
27/**
28 * struct clksrc_reg - register definition for clock control bits
29 * @reg: pointer to the register in virtual memory.
30 * @shift: the shift in bits to where the bitfield is.
31 * @size: the size in bits of the bitfield.
32 *
33 * This specifies the size and position of the bits we are interested
34 * in within the register specified by @reg.
35 */
36struct clksrc_reg {
37 void __iomem *reg;
38 unsigned short shift;
39 unsigned short size;
40};
41
42/**
43 * struct clksrc_clk - class of clock for newer style samsung devices.
44 * @clk: the standard clock representation
45 * @sources: the sources for this clock
46 * @reg_src: the register definition for selecting the clock's source
47 * @reg_div: the register definition for the clock's output divisor
48 *
49 * This clock implements the features required by the newer SoCs where
50 * the standard clock block provides an input mux and a post-mux divisor
51 * to provide the periperhal's clock.
52 *
53 * The array of @sources provides the mapping of mux position to the
54 * clock, and @reg_src shows the code where to modify to change the mux
55 * position. The @reg_div defines how to change the divider settings on
56 * the output.
57 */
58struct clksrc_clk {
59 struct clk clk;
60 struct clksrc_sources *sources;
61
62 struct clksrc_reg reg_src;
63 struct clksrc_reg reg_div;
64};
65
66/**
67 * s3c_set_clksrc() - setup the clock from the register settings
68 * @clk: The clock to setup.
69 * @announce: true to announce the setting to printk().
70 *
71 * Setup the clock from the current register settings, for when the
72 * kernel boots or if it is resuming from a possibly unknown state.
73 */
74extern void s3c_set_clksrc(struct clksrc_clk *clk, bool announce);
75
76/**
77 * s3c_register_clksrc() register clocks from an array of clksrc clocks
78 * @srcs: The array of clocks to register
79 * @size: The size of the @srcs array.
80 *
81 * Initialise and register the array of clocks described by @srcs.
82 */
83extern void s3c_register_clksrc(struct clksrc_clk *srcs, int size);
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
new file mode 100644
index 000000000000..60b62692ac7a
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -0,0 +1,115 @@
1/* linux/arch/arm/plat-s3c/include/plat/clock.h
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/SWLINUX/
5 * Written by Ben Dooks, <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/spinlock.h>
13
14struct clk;
15
16/**
17 * struct clk_ops - standard clock operations
18 * @set_rate: set the clock rate, see clk_set_rate().
19 * @get_rate: get the clock rate, see clk_get_rate().
20 * @round_rate: round a given clock rate, see clk_round_rate().
21 * @set_parent: set the clock's parent, see clk_set_parent().
22 *
23 * Group the common clock implementations together so that we
24 * don't have to keep setting the same fiels again. We leave
25 * enable in struct clk.
26 *
27 * Adding an extra layer of indirection into the process should
28 * not be a problem as it is unlikely these operations are going
29 * to need to be called quickly.
30 */
31struct clk_ops {
32 int (*set_rate)(struct clk *c, unsigned long rate);
33 unsigned long (*get_rate)(struct clk *c);
34 unsigned long (*round_rate)(struct clk *c, unsigned long rate);
35 int (*set_parent)(struct clk *c, struct clk *parent);
36};
37
38struct clk {
39 struct list_head list;
40 struct module *owner;
41 struct clk *parent;
42 const char *name;
43 int id;
44 int usage;
45 unsigned long rate;
46 unsigned long ctrlbit;
47
48 struct clk_ops *ops;
49 int (*enable)(struct clk *, int enable);
50};
51
52/* other clocks which may be registered by board support */
53
54extern struct clk s3c24xx_dclk0;
55extern struct clk s3c24xx_dclk1;
56extern struct clk s3c24xx_clkout0;
57extern struct clk s3c24xx_clkout1;
58extern struct clk s3c24xx_uclk;
59
60extern struct clk clk_usb_bus;
61
62/* core clock support */
63
64extern struct clk clk_f;
65extern struct clk clk_h;
66extern struct clk clk_p;
67extern struct clk clk_mpll;
68extern struct clk clk_upll;
69extern struct clk clk_epll;
70extern struct clk clk_xtal;
71extern struct clk clk_ext;
72
73/* S3C64XX specific clocks */
74extern struct clk clk_h2;
75extern struct clk clk_27m;
76extern struct clk clk_48m;
77
78extern int clk_default_setrate(struct clk *clk, unsigned long rate);
79extern struct clk_ops clk_ops_def_setrate;
80
81/* exports for arch/arm/mach-s3c2410
82 *
83 * Please DO NOT use these outside of arch/arm/mach-s3c2410
84*/
85
86extern spinlock_t clocks_lock;
87
88extern int s3c2410_clkcon_enable(struct clk *clk, int enable);
89
90extern int s3c24xx_register_clock(struct clk *clk);
91extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
92
93extern void s3c_register_clocks(struct clk *clk, int nr_clks);
94
95extern int s3c24xx_register_baseclocks(unsigned long xtal);
96
97extern void s5p_register_clocks(unsigned long xtal_freq);
98
99extern void s3c24xx_setup_clocks(unsigned long fclk,
100 unsigned long hclk,
101 unsigned long pclk);
102
103extern void s3c2410_setup_clocks(void);
104extern void s3c2412_setup_clocks(void);
105extern void s3c244x_setup_clocks(void);
106extern void s3c2443_setup_clocks(void);
107
108/* S3C64XX specific functions and clocks */
109
110extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable);
111
112/* Init for pwm clock code */
113
114extern void s3c_pwmclk_init(void);
115
diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq.h b/arch/arm/plat-samsung/include/plat/cpu-freq.h
new file mode 100644
index 000000000000..80c4a809c721
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/cpu-freq.h
@@ -0,0 +1,145 @@
1/* arch/arm/plat-samsung/include/plat/cpu-freq.h
2 *
3 * Copyright (c) 2006-2007 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C CPU frequency scaling support - driver and board
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/cpufreq.h>
15
16struct s3c_cpufreq_info;
17struct s3c_cpufreq_board;
18struct s3c_iotimings;
19
20/**
21 * struct s3c_freq - frequency information (mainly for core drivers)
22 * @fclk: The FCLK frequency in Hz.
23 * @armclk: The ARMCLK frequency in Hz.
24 * @hclk_tns: HCLK cycle time in 10ths of nano-seconds.
25 * @hclk: The HCLK frequency in Hz.
26 * @pclk: The PCLK frequency in Hz.
27 *
28 * This contains the frequency information about the current configuration
29 * mainly for the core drivers to ensure we do not end up passing about
30 * a large number of parameters.
31 *
32 * The @hclk_tns field is a useful cache for the parts of the drivers that
33 * need to calculate IO timings and suchlike.
34 */
35struct s3c_freq {
36 unsigned long fclk;
37 unsigned long armclk;
38 unsigned long hclk_tns; /* in 10ths of ns */
39 unsigned long hclk;
40 unsigned long pclk;
41};
42
43/**
44 * struct s3c_cpufreq_freqs - s3c cpufreq notification information.
45 * @freqs: The cpufreq setting information.
46 * @old: The old clock settings.
47 * @new: The new clock settings.
48 * @pll_changing: Set if the PLL is changing.
49 *
50 * Wrapper 'struct cpufreq_freqs' so that any drivers receiving the
51 * notification can use this information that is not provided by just
52 * having the core frequency alone.
53 *
54 * The pll_changing flag is used to indicate if the PLL itself is
55 * being set during this change. This is important as the clocks
56 * will temporarily be set to the XTAL clock during this time, so
57 * drivers may want to close down their output during this time.
58 *
59 * Note, this is not being used by any current drivers and therefore
60 * may be removed in the future.
61 */
62struct s3c_cpufreq_freqs {
63 struct cpufreq_freqs freqs;
64 struct s3c_freq old;
65 struct s3c_freq new;
66
67 unsigned int pll_changing:1;
68};
69
70#define to_s3c_cpufreq(_cf) container_of(_cf, struct s3c_cpufreq_freqs, freqs)
71
72/**
73 * struct s3c_clkdivs - clock divisor information
74 * @p_divisor: Divisor from FCLK to PCLK.
75 * @h_divisor: Divisor from FCLK to HCLK.
76 * @arm_divisor: Divisor from FCLK to ARMCLK (not all CPUs).
77 * @dvs: Non-zero if using DVS mode for ARMCLK.
78 *
79 * Divisor settings for the core clocks.
80 */
81struct s3c_clkdivs {
82 int p_divisor;
83 int h_divisor;
84 int arm_divisor;
85 unsigned char dvs;
86};
87
88#define PLLVAL(_m, _p, _s) (((_m) << 12) | ((_p) << 4) | (_s))
89
90/**
91 * struct s3c_pllval - PLL value entry.
92 * @freq: The frequency for this entry in Hz.
93 * @pll_reg: The PLL register setting for this PLL value.
94 */
95struct s3c_pllval {
96 unsigned long freq;
97 unsigned long pll_reg;
98};
99
100/**
101 * struct s3c_cpufreq_board - per-board cpu frequency informatin
102 * @refresh: The SDRAM refresh period in nanoseconds.
103 * @auto_io: Set if the IO timing settings should be generated from the
104 * initialisation time hardware registers.
105 * @need_io: Set if the board has external IO on any of the chipselect
106 * lines that will require the hardware timing registers to be
107 * updated on a clock change.
108 * @max: The maxium frequency limits for the system. Any field that
109 * is left at zero will use the CPU's settings.
110 *
111 * This contains the board specific settings that affect how the CPU
112 * drivers chose settings. These include the memory refresh and IO
113 * timing information.
114 *
115 * Registration depends on the driver being used, the ARMCLK only
116 * implementation does not currently need this but the older style
117 * driver requires this to be available.
118 */
119struct s3c_cpufreq_board {
120 unsigned int refresh;
121 unsigned int auto_io:1; /* automatically init io timings. */
122 unsigned int need_io:1; /* set if needs io timing support. */
123
124 /* any non-zero field in here is taken as an upper limit. */
125 struct s3c_freq max; /* frequency limits */
126};
127
128/* Things depending on frequency scaling. */
129#ifdef CONFIG_CPU_FREQ_S3C
130#define __init_or_cpufreq
131#else
132#define __init_or_cpufreq __init
133#endif
134
135/* Board functions */
136
137#ifdef CONFIG_CPU_FREQ_S3C
138extern int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board);
139#else
140
141static inline int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board)
142{
143 return 0;
144}
145#endif /* CONFIG_CPU_FREQ_S3C */
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
new file mode 100644
index 000000000000..d316b4a579f4
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -0,0 +1,84 @@
1/* linux/arch/arm/plat-samsung/include/plat/cpu.h
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for S3C24XX CPU support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* todo - fix when rmk changes iodescs to use `void __iomem *` */
14
15#ifndef __SAMSUNG_PLAT_CPU_H
16#define __SAMSUNG_PLAT_CPU_H
17
18#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
19
20#ifndef MHZ
21#define MHZ (1000*1000)
22#endif
23
24#define print_mhz(m) ((m) / MHZ), (((m) / 1000) % 1000)
25
26/* forward declaration */
27struct s3c24xx_uart_resources;
28struct platform_device;
29struct s3c2410_uartcfg;
30struct map_desc;
31
32/* per-cpu initialisation function table. */
33
34struct cpu_table {
35 unsigned long idcode;
36 unsigned long idmask;
37 void (*map_io)(void);
38 void (*init_uarts)(struct s3c2410_uartcfg *cfg, int no);
39 void (*init_clocks)(int xtal);
40 int (*init)(void);
41 const char *name;
42};
43
44extern void s3c_init_cpu(unsigned long idcode,
45 struct cpu_table *cpus, unsigned int cputab_size);
46
47/* core initialisation functions */
48
49extern void s3c24xx_init_irq(void);
50extern void s3c64xx_init_irq(u32 vic0, u32 vic1);
51extern void s5p_init_irq(u32 *vic, u32 num_vic);
52
53extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
54extern void s3c64xx_init_io(struct map_desc *mach_desc, int size);
55extern void s5p_init_io(struct map_desc *mach_desc,
56 int size, void __iomem *cpuid_addr);
57
58extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no);
59
60extern void s3c24xx_init_clocks(int xtal);
61
62extern void s3c24xx_init_uartdevs(char *name,
63 struct s3c24xx_uart_resources *res,
64 struct s3c2410_uartcfg *cfg, int no);
65
66/* timer for 2410/2440 */
67
68struct sys_timer;
69extern struct sys_timer s3c24xx_timer;
70
71/* system device classes */
72
73extern struct sysdev_class s3c2410_sysclass;
74extern struct sysdev_class s3c2410a_sysclass;
75extern struct sysdev_class s3c2412_sysclass;
76extern struct sysdev_class s3c2440_sysclass;
77extern struct sysdev_class s3c2442_sysclass;
78extern struct sysdev_class s3c2443_sysclass;
79extern struct sysdev_class s3c6410_sysclass;
80extern struct sysdev_class s3c64xx_sysclass;
81
82extern void (*s5pc1xx_idle)(void);
83
84#endif
diff --git a/arch/arm/plat-samsung/include/plat/debug-macro.S b/arch/arm/plat-samsung/include/plat/debug-macro.S
new file mode 100644
index 000000000000..dc6efd90e8ff
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/debug-macro.S
@@ -0,0 +1,87 @@
1/* arch/arm/plat-samsung/include/plat/debug-macro.S
2 *
3 * Copyright 2005, 2007 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <plat/regs-serial.h>
13
14/* The S5PV210/S5PC110 and S5P6442 implementations are as belows. */
15
16 .macro fifo_level_s5pv210 rd, rx
17 ldr \rd, [ \rx, # S3C2410_UFSTAT ]
18 and \rd, \rd, #S5PV210_UFSTAT_TXMASK
19 .endm
20
21 .macro fifo_full_s5pv210 rd, rx
22 ldr \rd, [ \rx, # S3C2410_UFSTAT ]
23 tst \rd, #S5PV210_UFSTAT_TXFULL
24 .endm
25
26/* The S3C2440 implementations are used by default as they are the
27 * most widely re-used */
28
29 .macro fifo_level_s3c2440 rd, rx
30 ldr \rd, [ \rx, # S3C2410_UFSTAT ]
31 and \rd, \rd, #S3C2440_UFSTAT_TXMASK
32 .endm
33
34#ifndef fifo_level
35#define fifo_level fifo_level_s3c2440
36#endif
37
38 .macro fifo_full_s3c2440 rd, rx
39 ldr \rd, [ \rx, # S3C2410_UFSTAT ]
40 tst \rd, #S3C2440_UFSTAT_TXFULL
41 .endm
42
43#ifndef fifo_full
44#define fifo_full fifo_full_s3c2440
45#endif
46
47 .macro senduart,rd,rx
48 strb \rd, [\rx, # S3C2410_UTXH ]
49 .endm
50
51 .macro busyuart, rd, rx
52 ldr \rd, [ \rx, # S3C2410_UFCON ]
53 tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
54 beq 1001f @
55 @ FIFO enabled...
561003:
57 fifo_full \rd, \rx
58 bne 1003b
59 b 1002f
60
611001:
62 @ busy waiting for non fifo
63 ldr \rd, [ \rx, # S3C2410_UTRSTAT ]
64 tst \rd, #S3C2410_UTRSTAT_TXFE
65 beq 1001b
66
671002: @ exit busyuart
68 .endm
69
70 .macro waituart,rd,rx
71 ldr \rd, [ \rx, # S3C2410_UFCON ]
72 tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
73 beq 1001f @
74 @ FIFO enabled...
751003:
76 fifo_level \rd, \rx
77 teq \rd, #0
78 bne 1003b
79 b 1002f
801001:
81 @ idle waiting for non fifo
82 ldr \rd, [ \rx, # S3C2410_UTRSTAT ]
83 tst \rd, #S3C2410_UTRSTAT_TXFE
84 beq 1001b
85
861002: @ exit busyuart
87 .endm
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
new file mode 100644
index 000000000000..796d24258313
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -0,0 +1,74 @@
1/* arch/arm/plat-samsung/include/plat/devs.h
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for s3c2410 standard platform devices
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12#include <linux/platform_device.h>
13
14struct s3c24xx_uart_resources {
15 struct resource *resources;
16 unsigned long nr_resources;
17};
18
19extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
20extern struct s3c24xx_uart_resources s3c64xx_uart_resources[];
21extern struct s3c24xx_uart_resources s5p_uart_resources[];
22
23extern struct platform_device *s3c24xx_uart_devs[];
24extern struct platform_device *s3c24xx_uart_src[];
25
26extern struct platform_device s3c_device_timer[];
27
28extern struct platform_device s3c64xx_device_iis0;
29extern struct platform_device s3c64xx_device_iis1;
30extern struct platform_device s3c64xx_device_iisv4;
31
32extern struct platform_device s3c64xx_device_spi0;
33extern struct platform_device s3c64xx_device_spi1;
34
35extern struct platform_device s3c64xx_device_pcm0;
36extern struct platform_device s3c64xx_device_pcm1;
37
38extern struct platform_device s3c64xx_device_ac97;
39
40extern struct platform_device s3c_device_ts;
41
42extern struct platform_device s3c_device_fb;
43extern struct platform_device s3c_device_ohci;
44extern struct platform_device s3c_device_lcd;
45extern struct platform_device s3c_device_wdt;
46extern struct platform_device s3c_device_i2c0;
47extern struct platform_device s3c_device_i2c1;
48extern struct platform_device s3c_device_rtc;
49extern struct platform_device s3c_device_adc;
50extern struct platform_device s3c_device_sdi;
51extern struct platform_device s3c_device_iis;
52extern struct platform_device s3c_device_hwmon;
53extern struct platform_device s3c_device_hsmmc0;
54extern struct platform_device s3c_device_hsmmc1;
55extern struct platform_device s3c_device_hsmmc2;
56
57extern struct platform_device s3c_device_spi0;
58extern struct platform_device s3c_device_spi1;
59
60extern struct platform_device s3c_device_hwmon;
61
62extern struct platform_device s3c_device_nand;
63
64extern struct platform_device s3c_device_usbgadget;
65extern struct platform_device s3c_device_usb_hsotg;
66
67/* s3c2440 specific devices */
68
69#ifdef CONFIG_CPU_S3C2440
70
71extern struct platform_device s3c_device_camif;
72extern struct platform_device s3c_device_ac97;
73
74#endif
diff --git a/arch/arm/plat-samsung/include/plat/dma-core.h b/arch/arm/plat-samsung/include/plat/dma-core.h
new file mode 100644
index 000000000000..32ff2a92cb3c
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/dma-core.h
@@ -0,0 +1,22 @@
1/* arch/arm/plat-s3c/include/plat/dma.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * Samsung S3C DMA core support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15extern struct s3c2410_dma_chan *s3c_dma_lookup_channel(unsigned int channel);
16
17extern struct s3c2410_dma_chan *s3c_dma_chan_map[];
18
19/* the currently allocated channel information */
20extern struct s3c2410_dma_chan s3c2410_chans[];
21
22
diff --git a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
new file mode 100644
index 000000000000..336d5ac02035
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
@@ -0,0 +1,84 @@
1/* linux/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
2 *
3 * Copyright (C) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C24XX DMA support - per SoC functions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <plat/dma-core.h>
14
15extern struct sysdev_class dma_sysclass;
16extern struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
17
18#define DMA_CH_VALID (1<<31)
19#define DMA_CH_NEVER (1<<30)
20
21struct s3c24xx_dma_addr {
22 unsigned long from;
23 unsigned long to;
24};
25
26/* struct s3c24xx_dma_map
27 *
28 * this holds the mapping information for the channel selected
29 * to be connected to the specified device
30*/
31
32struct s3c24xx_dma_map {
33 const char *name;
34 struct s3c24xx_dma_addr hw_addr;
35
36 unsigned long channels[S3C_DMA_CHANNELS];
37 unsigned long channels_rx[S3C_DMA_CHANNELS];
38};
39
40struct s3c24xx_dma_selection {
41 struct s3c24xx_dma_map *map;
42 unsigned long map_size;
43 unsigned long dcon_mask;
44
45 void (*select)(struct s3c2410_dma_chan *chan,
46 struct s3c24xx_dma_map *map);
47
48 void (*direction)(struct s3c2410_dma_chan *chan,
49 struct s3c24xx_dma_map *map,
50 enum s3c2410_dmasrc dir);
51};
52
53extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
54
55/* struct s3c24xx_dma_order_ch
56 *
57 * channel map for one of the `enum dma_ch` dma channels. the list
58 * entry contains a set of low-level channel numbers, orred with
59 * DMA_CH_VALID, which are checked in the order in the array.
60*/
61
62struct s3c24xx_dma_order_ch {
63 unsigned int list[S3C_DMA_CHANNELS]; /* list of channels */
64 unsigned int flags; /* flags */
65};
66
67/* struct s3c24xx_dma_order
68 *
69 * information provided by either the core or the board to give the
70 * dma system a hint on how to allocate channels
71*/
72
73struct s3c24xx_dma_order {
74 struct s3c24xx_dma_order_ch channels[DMACH_MAX];
75};
76
77extern int s3c24xx_dma_order_set(struct s3c24xx_dma_order *map);
78
79/* DMA init code, called from the cpu support code */
80
81extern int s3c2410_dma_init(void);
82
83extern int s3c24xx_dma_init(unsigned int channels, unsigned int irq,
84 unsigned int stride);
diff --git a/arch/arm/plat-samsung/include/plat/dma.h b/arch/arm/plat-samsung/include/plat/dma.h
new file mode 100644
index 000000000000..7584d751ed51
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/dma.h
@@ -0,0 +1,127 @@
1/* arch/arm/plat-samsung/include/plat/dma.h
2 *
3 * Copyright (C) 2003-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C DMA support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13enum s3c2410_dma_buffresult {
14 S3C2410_RES_OK,
15 S3C2410_RES_ERR,
16 S3C2410_RES_ABORT
17};
18
19enum s3c2410_dmasrc {
20 S3C2410_DMASRC_HW, /* source is memory */
21 S3C2410_DMASRC_MEM /* source is hardware */
22};
23
24/* enum s3c2410_chan_op
25 *
26 * operation codes passed to the DMA code by the user, and also used
27 * to inform the current channel owner of any changes to the system state
28*/
29
30enum s3c2410_chan_op {
31 S3C2410_DMAOP_START,
32 S3C2410_DMAOP_STOP,
33 S3C2410_DMAOP_PAUSE,
34 S3C2410_DMAOP_RESUME,
35 S3C2410_DMAOP_FLUSH,
36 S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */
37 S3C2410_DMAOP_STARTED, /* indicate channel started */
38};
39
40struct s3c2410_dma_client {
41 char *name;
42};
43
44struct s3c2410_dma_chan;
45
46/* s3c2410_dma_cbfn_t
47 *
48 * buffer callback routine type
49*/
50
51typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
52 void *buf, int size,
53 enum s3c2410_dma_buffresult result);
54
55typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
56 enum s3c2410_chan_op );
57
58
59
60/* s3c2410_dma_request
61 *
62 * request a dma channel exclusivley
63*/
64
65extern int s3c2410_dma_request(unsigned int channel,
66 struct s3c2410_dma_client *, void *dev);
67
68
69/* s3c2410_dma_ctrl
70 *
71 * change the state of the dma channel
72*/
73
74extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op);
75
76/* s3c2410_dma_setflags
77 *
78 * set the channel's flags to a given state
79*/
80
81extern int s3c2410_dma_setflags(unsigned int channel,
82 unsigned int flags);
83
84/* s3c2410_dma_free
85 *
86 * free the dma channel (will also abort any outstanding operations)
87*/
88
89extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *);
90
91/* s3c2410_dma_enqueue
92 *
93 * place the given buffer onto the queue of operations for the channel.
94 * The buffer must be allocated from dma coherent memory, or the Dcache/WB
95 * drained before the buffer is given to the DMA system.
96*/
97
98extern int s3c2410_dma_enqueue(unsigned int channel, void *id,
99 dma_addr_t data, int size);
100
101/* s3c2410_dma_config
102 *
103 * configure the dma channel
104*/
105
106extern int s3c2410_dma_config(unsigned int channel, int xferunit);
107
108/* s3c2410_dma_devconfig
109 *
110 * configure the device we're talking to
111*/
112
113extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
114 unsigned long devaddr);
115
116/* s3c2410_dma_getposition
117 *
118 * get the position that the dma transfer is currently at
119*/
120
121extern int s3c2410_dma_getposition(unsigned int channel,
122 dma_addr_t *src, dma_addr_t *dest);
123
124extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn);
125extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn);
126
127
diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h
new file mode 100644
index 000000000000..ffc01a76b7ce
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/fb.h
@@ -0,0 +1,80 @@
1/* arch/arm/plat-samsung/include/plat/fb.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C - FB platform data definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __PLAT_S3C_FB_H
16#define __PLAT_S3C_FB_H __FILE__
17
18/**
19 * struct s3c_fb_pd_win - per window setup data
20 * @win_mode: The display parameters to initialise (not for window 0)
21 * @virtual_x: The virtual X size.
22 * @virtual_y: The virtual Y size.
23 */
24struct s3c_fb_pd_win {
25 struct fb_videomode win_mode;
26
27 unsigned short default_bpp;
28 unsigned short max_bpp;
29 unsigned short virtual_x;
30 unsigned short virtual_y;
31};
32
33/**
34 * struct s3c_fb_platdata - S3C driver platform specific information
35 * @setup_gpio: Setup the external GPIO pins to the right state to transfer
36 * the data from the display system to the connected display
37 * device.
38 * @vidcon0: The base vidcon0 values to control the panel data format.
39 * @vidcon1: The base vidcon1 values to control the panel data output.
40 * @win: The setup data for each hardware window, or NULL for unused.
41 * @display_mode: The LCD output display mode.
42 *
43 * The platform data supplies the video driver with all the information
44 * it requires to work with the display(s) attached to the machine. It
45 * controls the initial mode, the number of display windows (0 is always
46 * the base framebuffer) that are initialised etc.
47 *
48 */
49struct s3c_fb_platdata {
50 void (*setup_gpio)(void);
51
52 struct s3c_fb_pd_win *win[S3C_FB_MAX_WIN];
53
54 u32 vidcon0;
55 u32 vidcon1;
56};
57
58/**
59 * s3c_fb_set_platdata() - Setup the FB device with platform data.
60 * @pd: The platform data to set. The data is copied from the passed structure
61 * so the machine data can mark the data __initdata so that any unused
62 * machines will end up dumping their data at runtime.
63 */
64extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd);
65
66/**
67 * s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD
68 *
69 * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
70 */
71extern void s3c64xx_fb_gpio_setup_24bpp(void);
72
73/**
74 * s5pc100_fb_gpio_setup_24bpp() - S5PC100 setup function for 24bpp LCD
75 *
76 * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
77 */
78extern void s5pc100_fb_gpio_setup_24bpp(void);
79
80#endif /* __PLAT_S3C_FB_H */
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
new file mode 100644
index 000000000000..652e2bbdaa20
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
@@ -0,0 +1,176 @@
1/* linux/arch/arm/plat-s3c/include/plat/gpio-cfg-helper.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C Platform - GPIO pin configuration helper definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/* This is meant for core cpu support, machine or other driver files
16 * should not be including this header.
17 */
18
19#ifndef __PLAT_GPIO_CFG_HELPERS_H
20#define __PLAT_GPIO_CFG_HELPERS_H __FILE__
21
22/* As a note, all gpio configuration functions are entered exclusively, either
23 * with the relevant lock held or the system prevented from doing anything else
24 * by disabling interrupts.
25*/
26
27static inline int s3c_gpio_do_setcfg(struct s3c_gpio_chip *chip,
28 unsigned int off, unsigned int config)
29{
30 return (chip->config->set_config)(chip, off, config);
31}
32
33static inline int s3c_gpio_do_setpull(struct s3c_gpio_chip *chip,
34 unsigned int off, s3c_gpio_pull_t pull)
35{
36 return (chip->config->set_pull)(chip, off, pull);
37}
38
39/**
40 * s3c_gpio_setcfg_s3c24xx - S3C24XX style GPIO configuration.
41 * @chip: The gpio chip that is being configured.
42 * @off: The offset for the GPIO being configured.
43 * @cfg: The configuration value to set.
44 *
45 * This helper deal with the GPIO cases where the control register
46 * has two bits of configuration per gpio, which have the following
47 * functions:
48 * 00 = input
49 * 01 = output
50 * 1x = special function
51*/
52extern int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
53 unsigned int off, unsigned int cfg);
54
55/**
56 * s3c_gpio_setcfg_s3c24xx_a - S3C24XX style GPIO configuration (Bank A)
57 * @chip: The gpio chip that is being configured.
58 * @off: The offset for the GPIO being configured.
59 * @cfg: The configuration value to set.
60 *
61 * This helper deal with the GPIO cases where the control register
62 * has one bit of configuration for the gpio, where setting the bit
63 * means the pin is in special function mode and unset means output.
64*/
65extern int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
66 unsigned int off, unsigned int cfg);
67
68/**
69 * s3c_gpio_setcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config.
70 * @chip: The gpio chip that is being configured.
71 * @off: The offset for the GPIO being configured.
72 * @cfg: The configuration value to set.
73 *
74 * This helper deal with the GPIO cases where the control register has 4 bits
75 * of control per GPIO, generally in the form of:
76 * 0000 = Input
77 * 0001 = Output
78 * others = Special functions (dependant on bank)
79 *
80 * Note, since the code to deal with the case where there are two control
81 * registers instead of one, we do not have a seperate set of functions for
82 * each case.
83*/
84extern int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
85 unsigned int off, unsigned int cfg);
86
87
88/* Pull-{up,down} resistor controls.
89 *
90 * S3C2410,S3C2440,S3C24A0 = Pull-UP,
91 * S3C2412,S3C2413 = Pull-Down
92 * S3C6400,S3C6410 = Pull-Both [None,Down,Up,Undef]
93 * S3C2443 = Pull-Both [not same as S3C6400]
94 */
95
96/**
97 * s3c_gpio_setpull_1up() - Pull configuration for choice of up or none.
98 * @chip: The gpio chip that is being configured.
99 * @off: The offset for the GPIO being configured.
100 * @param: pull: The pull mode being requested.
101 *
102 * This is a helper function for the case where we have GPIOs with one
103 * bit configuring the presence of a pull-up resistor.
104 */
105extern int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,
106 unsigned int off, s3c_gpio_pull_t pull);
107
108/**
109 * s3c_gpio_setpull_1down() - Pull configuration for choice of down or none
110 * @chip: The gpio chip that is being configured
111 * @off: The offset for the GPIO being configured
112 * @param: pull: The pull mode being requested
113 *
114 * This is a helper function for the case where we have GPIOs with one
115 * bit configuring the presence of a pull-down resistor.
116 */
117extern int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip,
118 unsigned int off, s3c_gpio_pull_t pull);
119
120/**
121 * s3c_gpio_setpull_upown() - Pull configuration for choice of up, down or none
122 * @chip: The gpio chip that is being configured.
123 * @off: The offset for the GPIO being configured.
124 * @param: pull: The pull mode being requested.
125 *
126 * This is a helper function for the case where we have GPIOs with two
127 * bits configuring the presence of a pull resistor, in the following
128 * order:
129 * 00 = No pull resistor connected
130 * 01 = Pull-up resistor connected
131 * 10 = Pull-down resistor connected
132 */
133extern int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip,
134 unsigned int off, s3c_gpio_pull_t pull);
135
136
137/**
138 * s3c_gpio_getpull_updown() - Get configuration for choice of up, down or none
139 * @chip: The gpio chip that the GPIO pin belongs to
140 * @off: The offset to the pin to get the configuration of.
141 *
142 * This helper function reads the state of the pull-{up,down} resistor for the
143 * given GPIO in the same case as s3c_gpio_setpull_upown.
144*/
145extern s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
146 unsigned int off);
147
148/**
149 * s3c_gpio_setpull_s3c2443() - Pull configuration for s3c2443.
150 * @chip: The gpio chip that is being configured.
151 * @off: The offset for the GPIO being configured.
152 * @param: pull: The pull mode being requested.
153 *
154 * This is a helper function for the case where we have GPIOs with two
155 * bits configuring the presence of a pull resistor, in the following
156 * order:
157 * 00 = Pull-up resistor connected
158 * 10 = Pull-down resistor connected
159 * x1 = No pull up resistor
160 */
161extern int s3c_gpio_setpull_s3c2443(struct s3c_gpio_chip *chip,
162 unsigned int off, s3c_gpio_pull_t pull);
163
164/**
165 * s3c_gpio_getpull_s3c2443() - Get configuration for s3c2443 pull resistors
166 * @chip: The gpio chip that the GPIO pin belongs to.
167 * @off: The offset to the pin to get the configuration of.
168 *
169 * This helper function reads the state of the pull-{up,down} resistor for the
170 * given GPIO in the same case as s3c_gpio_setpull_upown.
171*/
172extern s3c_gpio_pull_t s3c_gpio_getpull_s3c24xx(struct s3c_gpio_chip *chip,
173 unsigned int off);
174
175#endif /* __PLAT_GPIO_CFG_HELPERS_H */
176
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
new file mode 100644
index 000000000000..29cd6a86cade
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
@@ -0,0 +1,110 @@
1/* linux/arch/arm/plat-s3c/include/plat/gpio-cfg.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C Platform - GPIO pin configuration
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/* This file contains the necessary definitions to get the basic gpio
16 * pin configuration done such as setting a pin to input or output or
17 * changing the pull-{up,down} configurations.
18 */
19
20/* Note, this interface is being added to the s3c64xx arch first and will
21 * be added to the s3c24xx systems later.
22 */
23
24#ifndef __PLAT_GPIO_CFG_H
25#define __PLAT_GPIO_CFG_H __FILE__
26
27typedef unsigned int __bitwise__ s3c_gpio_pull_t;
28
29/* forward declaration if gpio-core.h hasn't been included */
30struct s3c_gpio_chip;
31
32/**
33 * struct s3c_gpio_cfg GPIO configuration
34 * @cfg_eint: Configuration setting when used for external interrupt source
35 * @get_pull: Read the current pull configuration for the GPIO
36 * @set_pull: Set the current pull configuraiton for the GPIO
37 * @set_config: Set the current configuration for the GPIO
38 * @get_config: Read the current configuration for the GPIO
39 *
40 * Each chip can have more than one type of GPIO bank available and some
41 * have different capabilites even when they have the same control register
42 * layouts. Provide an point to vector control routine and provide any
43 * per-bank configuration information that other systems such as the
44 * external interrupt code will need.
45 */
46struct s3c_gpio_cfg {
47 unsigned int cfg_eint;
48
49 s3c_gpio_pull_t (*get_pull)(struct s3c_gpio_chip *chip, unsigned offs);
50 int (*set_pull)(struct s3c_gpio_chip *chip, unsigned offs,
51 s3c_gpio_pull_t pull);
52
53 unsigned (*get_config)(struct s3c_gpio_chip *chip, unsigned offs);
54 int (*set_config)(struct s3c_gpio_chip *chip, unsigned offs,
55 unsigned config);
56};
57
58#define S3C_GPIO_SPECIAL_MARK (0xfffffff0)
59#define S3C_GPIO_SPECIAL(x) (S3C_GPIO_SPECIAL_MARK | (x))
60
61/* Defines for generic pin configurations */
62#define S3C_GPIO_INPUT (S3C_GPIO_SPECIAL(0))
63#define S3C_GPIO_OUTPUT (S3C_GPIO_SPECIAL(1))
64#define S3C_GPIO_SFN(x) (S3C_GPIO_SPECIAL(x))
65
66#define s3c_gpio_is_cfg_special(_cfg) \
67 (((_cfg) & S3C_GPIO_SPECIAL_MARK) == S3C_GPIO_SPECIAL_MARK)
68
69/**
70 * s3c_gpio_cfgpin() - Change the GPIO function of a pin.
71 * @pin pin The pin number to configure.
72 * @pin to The configuration for the pin's function.
73 *
74 * Configure which function is actually connected to the external
75 * pin, such as an gpio input, output or some form of special function
76 * connected to an internal peripheral block.
77 */
78extern int s3c_gpio_cfgpin(unsigned int pin, unsigned int to);
79
80/* Define values for the pull-{up,down} available for each gpio pin.
81 *
82 * These values control the state of the weak pull-{up,down} resistors
83 * available on most pins on the S3C series. Not all chips support both
84 * up or down settings, and it may be dependant on the chip that is being
85 * used to whether the particular mode is available.
86 */
87#define S3C_GPIO_PULL_NONE ((__force s3c_gpio_pull_t)0x00)
88#define S3C_GPIO_PULL_DOWN ((__force s3c_gpio_pull_t)0x01)
89#define S3C_GPIO_PULL_UP ((__force s3c_gpio_pull_t)0x02)
90
91/**
92 * s3c_gpio_setpull() - set the state of a gpio pin pull resistor
93 * @pin: The pin number to configure the pull resistor.
94 * @pull: The configuration for the pull resistor.
95 *
96 * This function sets the state of the pull-{up,down} resistor for the
97 * specified pin. It will return 0 if successfull, or a negative error
98 * code if the pin cannot support the requested pull setting.
99*/
100extern int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull);
101
102/**
103 * s3c_gpio_getpull() - get the pull resistor state of a gpio pin
104 * @pin: The pin number to get the settings for
105 *
106 * Read the pull resistor value for the specified pin.
107*/
108extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin);
109
110#endif /* __PLAT_GPIO_CFG_H */
diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h
new file mode 100644
index 000000000000..49ff406a7066
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/gpio-core.h
@@ -0,0 +1,137 @@
1/* linux/arch/arm/plat-s3c/include/plat/gpio-core.h
2 *
3 * Copyright 2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C Platform - GPIO core
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#define GPIOCON_OFF (0x00)
15#define GPIODAT_OFF (0x04)
16
17#define con_4bit_shift(__off) ((__off) * 4)
18
19/* Define the core gpiolib support functions that the s3c platforms may
20 * need to extend or change depending on the hardware and the s3c chip
21 * selected at build or found at run time.
22 *
23 * These definitions are not intended for driver inclusion, there is
24 * nothing here that should not live outside the platform and core
25 * specific code.
26*/
27
28struct s3c_gpio_chip;
29
30/**
31 * struct s3c_gpio_pm - power management (suspend/resume) information
32 * @save: Routine to save the state of the GPIO block
33 * @resume: Routine to resume the GPIO block.
34 */
35struct s3c_gpio_pm {
36 void (*save)(struct s3c_gpio_chip *chip);
37 void (*resume)(struct s3c_gpio_chip *chip);
38};
39
40struct s3c_gpio_cfg;
41
42/**
43 * struct s3c_gpio_chip - wrapper for specific implementation of gpio
44 * @chip: The chip structure to be exported via gpiolib.
45 * @base: The base pointer to the gpio configuration registers.
46 * @config: special function and pull-resistor control information.
47 * @pm_save: Save information for suspend/resume support.
48 *
49 * This wrapper provides the necessary information for the Samsung
50 * specific gpios being registered with gpiolib.
51 */
52struct s3c_gpio_chip {
53 struct gpio_chip chip;
54 struct s3c_gpio_cfg *config;
55 struct s3c_gpio_pm *pm;
56 void __iomem *base;
57#ifdef CONFIG_PM
58 u32 pm_save[4];
59#endif
60};
61
62static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc)
63{
64 return container_of(gpc, struct s3c_gpio_chip, chip);
65}
66
67/** s3c_gpiolib_add() - add the s3c specific version of a gpio_chip.
68 * @chip: The chip to register
69 *
70 * This is a wrapper to gpiochip_add() that takes our specific gpio chip
71 * information and makes the necessary alterations for the platform and
72 * notes the information for use with the configuration systems and any
73 * other parts of the system.
74 */
75extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip);
76
77/* CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
78 * for use with the configuration calls, and other parts of the s3c gpiolib
79 * support code.
80 *
81 * Not all s3c support code will need this, as some configurations of cpu
82 * may only support one or two different configuration options and have an
83 * easy gpio to s3c_gpio_chip mapping function. If this is the case, then
84 * the machine support file should provide its own s3c_gpiolib_getchip()
85 * and any other necessary functions.
86 */
87
88/**
89 * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
90 * @chip: The gpio chip that is being configured.
91 * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
92 *
93 * This helper deal with the GPIO cases where the control register has 4 bits
94 * of control per GPIO, generally in the form of:
95 * 0000 = Input
96 * 0001 = Output
97 * others = Special functions (dependant on bank)
98 *
99 * Note, since the code to deal with the case where there are two control
100 * registers instead of one, we do not have a seperate set of function
101 * (samsung_gpiolib_add_4bit2_chips)for each case.
102 */
103extern void samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip,
104 int nr_chips);
105extern void samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip,
106 int nr_chips);
107
108extern void samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip);
109extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip);
110
111#ifdef CONFIG_S3C_GPIO_TRACK
112extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
113
114static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip)
115{
116 return (chip < S3C_GPIO_END) ? s3c_gpios[chip] : NULL;
117}
118#else
119/* machine specific code should provide s3c_gpiolib_getchip */
120
121#include <mach/gpio-track.h>
122
123static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { }
124#endif
125
126#ifdef CONFIG_PM
127extern struct s3c_gpio_pm s3c_gpio_pm_1bit;
128extern struct s3c_gpio_pm s3c_gpio_pm_2bit;
129extern struct s3c_gpio_pm s3c_gpio_pm_4bit;
130#define __gpio_pm(x) x
131#else
132#define s3c_gpio_pm_1bit NULL
133#define s3c_gpio_pm_2bit NULL
134#define s3c_gpio_pm_4bit NULL
135#define __gpio_pm(x) NULL
136
137#endif /* CONFIG_PM */
diff --git a/arch/arm/plat-samsung/include/plat/hwmon.h b/arch/arm/plat-samsung/include/plat/hwmon.h
new file mode 100644
index 000000000000..1ba88ea0aa31
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/hwmon.h
@@ -0,0 +1,41 @@
1/* linux/arch/arm/plat-s3c/include/plat/hwmon.h
2 *
3 * Copyright 2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C - HWMon interface for ADC
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_ARCH_ADC_HWMON_H
15#define __ASM_ARCH_ADC_HWMON_H __FILE__
16
17/**
18 * s3c_hwmon_chcfg - channel configuration
19 * @name: The name to give this channel.
20 * @mult: Multiply the ADC value read by this.
21 * @div: Divide the value from the ADC by this.
22 *
23 * The value read from the ADC is converted to a value that
24 * hwmon expects (mV) by result = (value_read * @mult) / @div.
25 */
26struct s3c_hwmon_chcfg {
27 const char *name;
28 unsigned int mult;
29 unsigned int div;
30};
31
32/**
33 * s3c_hwmon_pdata - HWMON platform data
34 * @in: One configuration for each possible channel used.
35 */
36struct s3c_hwmon_pdata {
37 struct s3c_hwmon_chcfg *in[8];
38};
39
40#endif /* __ASM_ARCH_ADC_HWMON_H */
41
diff --git a/arch/arm/plat-samsung/include/plat/iic-core.h b/arch/arm/plat-samsung/include/plat/iic-core.h
new file mode 100644
index 000000000000..36397ca20962
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/iic-core.h
@@ -0,0 +1,35 @@
1/* arch/arm/mach-s3c2410/include/mach/iic-core.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C - I2C Controller core functions
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_ARCH_IIC_CORE_H
15#define __ASM_ARCH_IIC_CORE_H __FILE__
16
17/* These functions are only for use with the core support code, such as
18 * the cpu specific initialisation code
19 */
20
21/* re-define device name depending on support. */
22static inline void s3c_i2c0_setname(char *name)
23{
24 /* currently this device is always compiled in */
25 s3c_device_i2c0.name = name;
26}
27
28static inline void s3c_i2c1_setname(char *name)
29{
30#ifdef CONFIG_S3C_DEV_I2C1
31 s3c_device_i2c1.name = name;
32#endif
33}
34
35#endif /* __ASM_ARCH_IIC_H */
diff --git a/arch/arm/plat-samsung/include/plat/iic.h b/arch/arm/plat-samsung/include/plat/iic.h
new file mode 100644
index 000000000000..3083df00dee6
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/iic.h
@@ -0,0 +1,62 @@
1/* arch/arm/plat-s3c/include/plat/iic.h
2 *
3 * Copyright 2004-2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C - I2C Controller platform_device info
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_IIC_H
14#define __ASM_ARCH_IIC_H __FILE__
15
16#define S3C_IICFLG_FILTER (1<<0) /* enable s3c2440 filter */
17
18/**
19 * struct s3c2410_platform_i2c - Platform data for s3c I2C.
20 * @bus_num: The bus number to use (if possible).
21 * @flags: Any flags for the I2C bus (E.g. S3C_IICFLK_FILTER).
22 * @slave_addr: The I2C address for the slave device (if enabled).
23 * @frequency: The desired frequency in Hz of the bus. This is
24 * guaranteed to not be exceeded. If the caller does
25 * not care, use zero and the driver will select a
26 * useful default.
27 * @sda_delay: The delay (in ns) applied to SDA edges.
28 * @cfg_gpio: A callback to configure the pins for I2C operation.
29 */
30struct s3c2410_platform_i2c {
31 int bus_num;
32 unsigned int flags;
33 unsigned int slave_addr;
34 unsigned long frequency;
35 unsigned int sda_delay;
36
37 void (*cfg_gpio)(struct platform_device *dev);
38};
39
40/**
41 * s3c_i2c0_set_platdata - set platform data for i2c0 device
42 * @i2c: The platform data to set, or NULL for default data.
43 *
44 * Register the given platform data for use with the i2c0 device. This
45 * call copies the platform data, so the caller can use __initdata for
46 * their copy.
47 *
48 * This call will set cfg_gpio if is null to the default platform
49 * implementation.
50 *
51 * Any user of s3c_device_i2c0 should call this, even if it is with
52 * NULL to ensure that the device is given the default platform data
53 * as the driver will no longer carry defaults.
54 */
55extern void s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *i2c);
56extern void s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *i2c);
57
58/* defined by architecture to configure gpio */
59extern void s3c_i2c0_cfg_gpio(struct platform_device *dev);
60extern void s3c_i2c1_cfg_gpio(struct platform_device *dev);
61
62#endif /* __ASM_ARCH_IIC_H */
diff --git a/arch/arm/plat-samsung/include/plat/irq-uart.h b/arch/arm/plat-samsung/include/plat/irq-uart.h
new file mode 100644
index 000000000000..a9331e49bea3
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/irq-uart.h
@@ -0,0 +1,20 @@
1/* arch/arm/plat-samsung/include/plat/irq-uart.h
2 *
3 * Copyright (c) 2010 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for Samsung SoC UART IRQ demux for S3C64XX and later
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13struct s3c_uart_irq {
14 void __iomem *regs;
15 unsigned int base_irq;
16 unsigned int parent_irq;
17};
18
19extern void s3c_init_uart_irqs(struct s3c_uart_irq *irq, unsigned int nr_irqs);
20
diff --git a/arch/arm/plat-samsung/include/plat/irq-vic-timer.h b/arch/arm/plat-samsung/include/plat/irq-vic-timer.h
new file mode 100644
index 000000000000..a90b53431b5b
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/irq-vic-timer.h
@@ -0,0 +1,13 @@
1/* arch/arm/plat-samsung/include/plat/irq-vic-timer.h
2 *
3 * Copyright (c) 2010 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for Samsung SoC IRQ VIC timer
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13extern void s3c_init_vic_timer_irq(unsigned int vic, unsigned int timer);
diff --git a/arch/arm/plat-samsung/include/plat/map-base.h b/arch/arm/plat-samsung/include/plat/map-base.h
new file mode 100644
index 000000000000..250be311c85b
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/map-base.h
@@ -0,0 +1,46 @@
1/* linux/include/asm-arm/plat-s3c/map.h
2 *
3 * Copyright 2003, 2007 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C - Memory map definitions (virtual addresses)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_PLAT_MAP_H
15#define __ASM_PLAT_MAP_H __FILE__
16
17/* Fit all our registers in at 0xF4000000 upwards, trying to use as
18 * little of the VA space as possible so vmalloc and friends have a
19 * better chance of getting memory.
20 *
21 * we try to ensure stuff like the IRQ registers are available for
22 * an single MOVS instruction (ie, only 8 bits of set data)
23 */
24
25#define S3C_ADDR_BASE (0xF4000000)
26
27#ifndef __ASSEMBLY__
28#define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x))
29#else
30#define S3C_ADDR(x) (S3C_ADDR_BASE + (x))
31#endif
32
33#define S3C_VA_IRQ S3C_ADDR(0x00000000) /* irq controller(s) */
34#define S3C_VA_SYS S3C_ADDR(0x00100000) /* system control */
35#define S3C_VA_MEM S3C_ADDR(0x00200000) /* memory control */
36#define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */
37#define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */
38#define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */
39
40/* This is used for the CPU specific mappings that may be needed, so that
41 * they do not need to directly used S3C_ADDR() and thus make it easier to
42 * modify the space for mapping.
43 */
44#define S3C_ADDR_CPU(x) S3C_ADDR(0x00500000 + (x))
45
46#endif /* __ASM_PLAT_MAP_H */
diff --git a/arch/arm/plat-samsung/include/plat/nand.h b/arch/arm/plat-samsung/include/plat/nand.h
new file mode 100644
index 000000000000..226147b7e026
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/nand.h
@@ -0,0 +1,67 @@
1/* arch/arm/mach-s3c2410/include/mach/nand.h
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - NAND device controller platfrom_device info
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/**
14 * struct s3c2410_nand_set - define a set of one or more nand chips
15 * @disable_ecc: Entirely disable ECC - Dangerous
16 * @flash_bbt: Openmoko u-boot can create a Bad Block Table
17 * Setting this flag will allow the kernel to
18 * look for it at boot time and also skip the NAND
19 * scan.
20 * @options: Default value to set into 'struct nand_chip' options.
21 * @nr_chips: Number of chips in this set
22 * @nr_partitions: Number of partitions pointed to by @partitions
23 * @name: Name of set (optional)
24 * @nr_map: Map for low-layer logical to physical chip numbers (option)
25 * @partitions: The mtd partition list
26 *
27 * define a set of one or more nand chips registered with an unique mtd. Also
28 * allows to pass flag to the underlying NAND layer. 'disable_ecc' will trigger
29 * a warning at boot time.
30 */
31struct s3c2410_nand_set {
32 unsigned int disable_ecc:1;
33 unsigned int flash_bbt:1;
34
35 unsigned int options;
36 int nr_chips;
37 int nr_partitions;
38 char *name;
39 int *nr_map;
40 struct mtd_partition *partitions;
41 struct nand_ecclayout *ecc_layout;
42};
43
44struct s3c2410_platform_nand {
45 /* timing information for controller, all times in nanoseconds */
46
47 int tacls; /* time for active CLE/ALE to nWE/nOE */
48 int twrph0; /* active time for nWE/nOE */
49 int twrph1; /* time for release CLE/ALE from nWE/nOE inactive */
50
51 unsigned int ignore_unset_ecc:1;
52
53 int nr_sets;
54 struct s3c2410_nand_set *sets;
55
56 void (*select_chip)(struct s3c2410_nand_set *,
57 int chip);
58};
59
60/**
61 * s3c_nand_set_platdata() - register NAND platform data.
62 * @nand: The NAND platform data to register with s3c_device_nand.
63 *
64 * This function copies the given NAND platform data, @nand and registers
65 * it with the s3c_device_nand. This allows @nand to be __initdata.
66*/
67extern void s3c_nand_set_platdata(struct s3c2410_platform_nand *nand);
diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h
new file mode 100644
index 000000000000..245836d91931
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/pm.h
@@ -0,0 +1,189 @@
1/* arch/arm/plat-samsung/include/plat/pm.h
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Written by Ben Dooks, <ben@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/* s3c_pm_init
13 *
14 * called from board at initialisation time to setup the power
15 * management
16*/
17
18#ifdef CONFIG_PM
19
20extern __init int s3c_pm_init(void);
21
22#else
23
24static inline int s3c_pm_init(void)
25{
26 return 0;
27}
28#endif
29
30/* configuration for the IRQ mask over sleep */
31extern unsigned long s3c_irqwake_intmask;
32extern unsigned long s3c_irqwake_eintmask;
33
34/* IRQ masks for IRQs allowed to go to sleep (see irq.c) */
35extern unsigned long s3c_irqwake_intallow;
36extern unsigned long s3c_irqwake_eintallow;
37
38/* per-cpu sleep functions */
39
40extern void (*pm_cpu_prep)(void);
41extern void (*pm_cpu_sleep)(void);
42
43/* Flags for PM Control */
44
45extern unsigned long s3c_pm_flags;
46
47extern unsigned char pm_uart_udivslot; /* true to save UART UDIVSLOT */
48
49/* from sleep.S */
50
51extern int s3c_cpu_save(unsigned long *saveblk);
52extern void s3c_cpu_resume(void);
53
54extern void s3c2410_cpu_suspend(void);
55
56extern unsigned long s3c_sleep_save_phys;
57
58/* sleep save info */
59
60/**
61 * struct sleep_save - save information for shared peripherals.
62 * @reg: Pointer to the register to save.
63 * @val: Holder for the value saved from reg.
64 *
65 * This describes a list of registers which is used by the pm core and
66 * other subsystem to save and restore register values over suspend.
67 */
68struct sleep_save {
69 void __iomem *reg;
70 unsigned long val;
71};
72
73#define SAVE_ITEM(x) \
74 { .reg = (x) }
75
76/**
77 * struct pm_uart_save - save block for core UART
78 * @ulcon: Save value for S3C2410_ULCON
79 * @ucon: Save value for S3C2410_UCON
80 * @ufcon: Save value for S3C2410_UFCON
81 * @umcon: Save value for S3C2410_UMCON
82 * @ubrdiv: Save value for S3C2410_UBRDIV
83 *
84 * Save block for UART registers to be held over sleep and restored if they
85 * are needed (say by debug).
86*/
87struct pm_uart_save {
88 u32 ulcon;
89 u32 ucon;
90 u32 ufcon;
91 u32 umcon;
92 u32 ubrdiv;
93 u32 udivslot;
94};
95
96/* helper functions to save/restore lists of registers. */
97
98extern void s3c_pm_do_save(struct sleep_save *ptr, int count);
99extern void s3c_pm_do_restore(struct sleep_save *ptr, int count);
100extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count);
101
102#ifdef CONFIG_PM
103extern int s3c_irqext_wake(unsigned int irqno, unsigned int state);
104extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state);
105extern int s3c24xx_irq_resume(struct sys_device *dev);
106#else
107#define s3c_irqext_wake NULL
108#define s3c24xx_irq_suspend NULL
109#define s3c24xx_irq_resume NULL
110#endif
111
112/* PM debug functions */
113
114#ifdef CONFIG_SAMSUNG_PM_DEBUG
115/**
116 * s3c_pm_dbg() - low level debug function for use in suspend/resume.
117 * @msg: The message to print.
118 *
119 * This function is used mainly to debug the resume process before the system
120 * can rely on printk/console output. It uses the low-level debugging output
121 * routine printascii() to do its work.
122 */
123extern void s3c_pm_dbg(const char *msg, ...);
124
125#define S3C_PMDBG(fmt...) s3c_pm_dbg(fmt)
126#else
127#define S3C_PMDBG(fmt...) printk(KERN_DEBUG fmt)
128#endif
129
130#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
131/**
132 * s3c_pm_debug_smdkled() - Debug PM suspend/resume via SMDK Board LEDs
133 * @set: set bits for the state of the LEDs
134 * @clear: clear bits for the state of the LEDs.
135 */
136extern void s3c_pm_debug_smdkled(u32 set, u32 clear);
137
138#else
139static inline void s3c_pm_debug_smdkled(u32 set, u32 clear) { }
140#endif /* CONFIG_S3C_PM_DEBUG_LED_SMDK */
141
142/* suspend memory checking */
143
144#ifdef CONFIG_SAMSUNG_PM_CHECK
145extern void s3c_pm_check_prepare(void);
146extern void s3c_pm_check_restore(void);
147extern void s3c_pm_check_cleanup(void);
148extern void s3c_pm_check_store(void);
149#else
150#define s3c_pm_check_prepare() do { } while(0)
151#define s3c_pm_check_restore() do { } while(0)
152#define s3c_pm_check_cleanup() do { } while(0)
153#define s3c_pm_check_store() do { } while(0)
154#endif
155
156/**
157 * s3c_pm_configure_extint() - ensure pins are correctly set for IRQ
158 *
159 * Setup all the necessary GPIO pins for waking the system on external
160 * interrupt.
161 */
162extern void s3c_pm_configure_extint(void);
163
164/**
165 * s3c_pm_restore_gpios() - restore the state of the gpios after sleep.
166 *
167 * Restore the state of the GPIO pins after sleep, which may involve ensuring
168 * that we do not glitch the state of the pins from that the bootloader's
169 * resume code has done.
170*/
171extern void s3c_pm_restore_gpios(void);
172
173/**
174 * s3c_pm_save_gpios() - save the state of the GPIOs for restoring after sleep.
175 *
176 * Save the GPIO states for resotration on resume. See s3c_pm_restore_gpios().
177 */
178extern void s3c_pm_save_gpios(void);
179
180/**
181 * s3c_pm_cb_flushcache - callback for assembly code
182 *
183 * Callback to issue flush_cache_all() as this call is
184 * not a directly callable object.
185 */
186extern void s3c_pm_cb_flushcache(void);
187
188extern void s3c_pm_save_core(void);
189extern void s3c_pm_restore_core(void);
diff --git a/arch/arm/plat-samsung/include/plat/regs-ac97.h b/arch/arm/plat-samsung/include/plat/regs-ac97.h
new file mode 100644
index 000000000000..c3878f7acb83
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-ac97.h
@@ -0,0 +1,67 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-ac97.h
2 *
3 * Copyright (c) 2006 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2440 AC97 Controller
11*/
12
13#ifndef __ASM_ARCH_REGS_AC97_H
14#define __ASM_ARCH_REGS_AC97_H __FILE__
15
16#define S3C_AC97_GLBCTRL (0x00)
17
18#define S3C_AC97_GLBCTRL_CODECREADYIE (1<<22)
19#define S3C_AC97_GLBCTRL_PCMOUTURIE (1<<21)
20#define S3C_AC97_GLBCTRL_PCMINORIE (1<<20)
21#define S3C_AC97_GLBCTRL_MICINORIE (1<<19)
22#define S3C_AC97_GLBCTRL_PCMOUTTIE (1<<18)
23#define S3C_AC97_GLBCTRL_PCMINTIE (1<<17)
24#define S3C_AC97_GLBCTRL_MICINTIE (1<<16)
25#define S3C_AC97_GLBCTRL_PCMOUTTM_OFF (0<<12)
26#define S3C_AC97_GLBCTRL_PCMOUTTM_PIO (1<<12)
27#define S3C_AC97_GLBCTRL_PCMOUTTM_DMA (2<<12)
28#define S3C_AC97_GLBCTRL_PCMOUTTM_MASK (3<<12)
29#define S3C_AC97_GLBCTRL_PCMINTM_OFF (0<<10)
30#define S3C_AC97_GLBCTRL_PCMINTM_PIO (1<<10)
31#define S3C_AC97_GLBCTRL_PCMINTM_DMA (2<<10)
32#define S3C_AC97_GLBCTRL_PCMINTM_MASK (3<<10)
33#define S3C_AC97_GLBCTRL_MICINTM_OFF (0<<8)
34#define S3C_AC97_GLBCTRL_MICINTM_PIO (1<<8)
35#define S3C_AC97_GLBCTRL_MICINTM_DMA (2<<8)
36#define S3C_AC97_GLBCTRL_MICINTM_MASK (3<<8)
37#define S3C_AC97_GLBCTRL_TRANSFERDATAENABLE (1<<3)
38#define S3C_AC97_GLBCTRL_ACLINKON (1<<2)
39#define S3C_AC97_GLBCTRL_WARMRESET (1<<1)
40#define S3C_AC97_GLBCTRL_COLDRESET (1<<0)
41
42#define S3C_AC97_GLBSTAT (0x04)
43
44#define S3C_AC97_GLBSTAT_CODECREADY (1<<22)
45#define S3C_AC97_GLBSTAT_PCMOUTUR (1<<21)
46#define S3C_AC97_GLBSTAT_PCMINORI (1<<20)
47#define S3C_AC97_GLBSTAT_MICINORI (1<<19)
48#define S3C_AC97_GLBSTAT_PCMOUTTI (1<<18)
49#define S3C_AC97_GLBSTAT_PCMINTI (1<<17)
50#define S3C_AC97_GLBSTAT_MICINTI (1<<16)
51#define S3C_AC97_GLBSTAT_MAINSTATE_IDLE (0<<0)
52#define S3C_AC97_GLBSTAT_MAINSTATE_INIT (1<<0)
53#define S3C_AC97_GLBSTAT_MAINSTATE_READY (2<<0)
54#define S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE (3<<0)
55#define S3C_AC97_GLBSTAT_MAINSTATE_LP (4<<0)
56#define S3C_AC97_GLBSTAT_MAINSTATE_WARM (5<<0)
57
58#define S3C_AC97_CODEC_CMD (0x08)
59
60#define S3C_AC97_CODEC_CMD_READ (1<<23)
61
62#define S3C_AC97_STAT (0x0c)
63#define S3C_AC97_PCM_ADDR (0x10)
64#define S3C_AC97_PCM_DATA (0x18)
65#define S3C_AC97_MIC_DATA (0x1C)
66
67#endif /* __ASM_ARCH_REGS_AC97_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-adc.h b/arch/arm/plat-samsung/include/plat/regs-adc.h
new file mode 100644
index 000000000000..7554c4fcddb9
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-adc.h
@@ -0,0 +1,64 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-adc.h
2 *
3 * Copyright (c) 2004 Shannon Holland <holland@loser.net>
4 *
5 * This program is free software; yosu can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * S3C2410 ADC registers
10*/
11
12#ifndef __ASM_ARCH_REGS_ADC_H
13#define __ASM_ARCH_REGS_ADC_H "regs-adc.h"
14
15#define S3C2410_ADCREG(x) (x)
16
17#define S3C2410_ADCCON S3C2410_ADCREG(0x00)
18#define S3C2410_ADCTSC S3C2410_ADCREG(0x04)
19#define S3C2410_ADCDLY S3C2410_ADCREG(0x08)
20#define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C)
21#define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10)
22#define S3C64XX_ADCUPDN S3C2410_ADCREG(0x14)
23#define S3C64XX_ADCCLRINT S3C2410_ADCREG(0x18)
24#define S3C64XX_ADCCLRINTPNDNUP S3C2410_ADCREG(0x20)
25
26
27/* ADCCON Register Bits */
28#define S3C64XX_ADCCON_RESSEL (1<<16)
29#define S3C2410_ADCCON_ECFLG (1<<15)
30#define S3C2410_ADCCON_PRSCEN (1<<14)
31#define S3C2410_ADCCON_PRSCVL(x) (((x)&0xFF)<<6)
32#define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6)
33#define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3)
34#define S3C2410_ADCCON_MUXMASK (0x7<<3)
35#define S3C2410_ADCCON_STDBM (1<<2)
36#define S3C2410_ADCCON_READ_START (1<<1)
37#define S3C2410_ADCCON_ENABLE_START (1<<0)
38#define S3C2410_ADCCON_STARTMASK (0x3<<0)
39
40
41/* ADCTSC Register Bits */
42#define S3C2410_ADCTSC_YM_SEN (1<<7)
43#define S3C2410_ADCTSC_YP_SEN (1<<6)
44#define S3C2410_ADCTSC_XM_SEN (1<<5)
45#define S3C2410_ADCTSC_XP_SEN (1<<4)
46#define S3C2410_ADCTSC_PULL_UP_DISABLE (1<<3)
47#define S3C2410_ADCTSC_AUTO_PST (1<<2)
48#define S3C2410_ADCTSC_XY_PST(x) (((x)&0x3)<<0)
49
50/* ADCDAT0 Bits */
51#define S3C2410_ADCDAT0_UPDOWN (1<<15)
52#define S3C2410_ADCDAT0_AUTO_PST (1<<14)
53#define S3C2410_ADCDAT0_XY_PST (0x3<<12)
54#define S3C2410_ADCDAT0_XPDATA_MASK (0x03FF)
55
56/* ADCDAT1 Bits */
57#define S3C2410_ADCDAT1_UPDOWN (1<<15)
58#define S3C2410_ADCDAT1_AUTO_PST (1<<14)
59#define S3C2410_ADCDAT1_XY_PST (0x3<<12)
60#define S3C2410_ADCDAT1_YPDATA_MASK (0x03FF)
61
62#endif /* __ASM_ARCH_REGS_ADC_H */
63
64
diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
new file mode 100644
index 000000000000..0f43599248ad
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
@@ -0,0 +1,235 @@
1/* arch/arm/plat-samsung/include/plat/regs-fb-v4.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C64XX - new-style framebuffer register definitions
9 *
10 * This is the register set for the new style framebuffer interface
11 * found from the S3C2443 onwards and specifically the S3C64XX series
12 * S3C6400 and S3C6410.
13 *
14 * The file contains the cpu specific items which change between whichever
15 * architecture is selected. See <plat/regs-fb.h> for the core definitions
16 * that are the same.
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21*/
22
23/* include the core definitions here, in case we really do need to
24 * override them at a later date.
25*/
26
27#include <plat/regs-fb.h>
28
29#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */
30#define VIDCON1_FSTATUS_EVEN (1 << 15)
31
32/* Video timing controls */
33#define VIDTCON0 (0x10)
34#define VIDTCON1 (0x14)
35#define VIDTCON2 (0x18)
36
37/* Window position controls */
38
39#define WINCON(_win) (0x20 + ((_win) * 4))
40
41/* OSD1 and OSD4 do not have register D */
42
43#define VIDOSD_A(_win) (0x40 + ((_win) * 16))
44#define VIDOSD_B(_win) (0x44 + ((_win) * 16))
45#define VIDOSD_C(_win) (0x48 + ((_win) * 16))
46#define VIDOSD_D(_win) (0x4C + ((_win) * 16))
47
48
49#define VIDINTCON0 (0x130)
50
51#define WxKEYCONy(_win, _con) ((0x140 + ((_win) * 8)) + ((_con) * 4))
52
53/* WINCONx */
54
55#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
56#define WINCONx_CSCWIDTH_SHIFT (26)
57#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
58#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
59
60#define WINCONx_ENLOCAL (1 << 22)
61#define WINCONx_BUFSTATUS (1 << 21)
62#define WINCONx_BUFSEL (1 << 20)
63#define WINCONx_BUFAUTOEN (1 << 19)
64#define WINCONx_YCbCr (1 << 13)
65
66#define WINCON1_LOCALSEL_CAMIF (1 << 23)
67
68#define WINCON2_LOCALSEL_CAMIF (1 << 23)
69#define WINCON2_BLD_PIX (1 << 6)
70
71#define WINCON2_ALPHA_SEL (1 << 1)
72#define WINCON2_BPPMODE_MASK (0xf << 2)
73#define WINCON2_BPPMODE_SHIFT (2)
74#define WINCON2_BPPMODE_1BPP (0x0 << 2)
75#define WINCON2_BPPMODE_2BPP (0x1 << 2)
76#define WINCON2_BPPMODE_4BPP (0x2 << 2)
77#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2)
78#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2)
79#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2)
80#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2)
81#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2)
82#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2)
83#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2)
84#define WINCON2_BPPMODE_24BPP_888 (0xb << 2)
85#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2)
86#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2)
87#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2)
88
89#define WINCON3_BLD_PIX (1 << 6)
90
91#define WINCON3_ALPHA_SEL (1 << 1)
92#define WINCON3_BPPMODE_MASK (0xf << 2)
93#define WINCON3_BPPMODE_SHIFT (2)
94#define WINCON3_BPPMODE_1BPP (0x0 << 2)
95#define WINCON3_BPPMODE_2BPP (0x1 << 2)
96#define WINCON3_BPPMODE_4BPP (0x2 << 2)
97#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2)
98#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2)
99#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2)
100#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2)
101#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2)
102#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2)
103#define WINCON3_BPPMODE_24BPP_888 (0xb << 2)
104#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2)
105#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2)
106#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2)
107
108#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
109#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
110#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
111
112#define DITHMODE (0x170)
113#define WINxMAP(_win) (0x180 + ((_win) * 4))
114
115
116#define DITHMODE_R_POS_MASK (0x3 << 5)
117#define DITHMODE_R_POS_SHIFT (5)
118#define DITHMODE_R_POS_8BIT (0x0 << 5)
119#define DITHMODE_R_POS_6BIT (0x1 << 5)
120#define DITHMODE_R_POS_5BIT (0x2 << 5)
121
122#define DITHMODE_G_POS_MASK (0x3 << 3)
123#define DITHMODE_G_POS_SHIFT (3)
124#define DITHMODE_G_POS_8BIT (0x0 << 3)
125#define DITHMODE_G_POS_6BIT (0x1 << 3)
126#define DITHMODE_G_POS_5BIT (0x2 << 3)
127
128#define DITHMODE_B_POS_MASK (0x3 << 1)
129#define DITHMODE_B_POS_SHIFT (1)
130#define DITHMODE_B_POS_8BIT (0x0 << 1)
131#define DITHMODE_B_POS_6BIT (0x1 << 1)
132#define DITHMODE_B_POS_5BIT (0x2 << 1)
133
134#define DITHMODE_DITH_EN (1 << 0)
135
136#define WPALCON (0x1A0)
137
138/* Palette control */
139/* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L),
140 * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */
141#define WPALCON_W4PAL_16BPP_A555 (1 << 8)
142#define WPALCON_W3PAL_16BPP_A555 (1 << 7)
143#define WPALCON_W2PAL_16BPP_A555 (1 << 6)
144
145
146/* system specific implementation code for palette sizes, and other
147 * information that changes depending on which architecture is being
148 * compiled.
149*/
150
151/* return true if window _win has OSD register D */
152#define s3c_fb_has_osd_d(_win) ((_win) != 4 && (_win) != 0)
153
154static inline unsigned int s3c_fb_win_pal_size(unsigned int win)
155{
156 if (win < 2)
157 return 256;
158 if (win < 4)
159 return 16;
160 if (win == 4)
161 return 4;
162
163 BUG(); /* shouldn't get here */
164}
165
166static inline int s3c_fb_validate_win_bpp(unsigned int win, unsigned int bpp)
167{
168 /* all windows can do 1/2 bpp */
169
170 if ((bpp == 25 || bpp == 19) && win == 0)
171 return 0; /* win 0 does not have 19 or 25bpp modes */
172
173 if (bpp == 4 && win == 4)
174 return 0;
175
176 if (bpp == 8 && (win >= 3))
177 return 0; /* win 3/4 cannot do 8bpp in any mode */
178
179 return 1;
180}
181
182static inline int s3c_fb_pal_is16(unsigned int window)
183{
184 return window > 1;
185}
186
187struct s3c_fb_palette {
188 struct fb_bitfield r;
189 struct fb_bitfield g;
190 struct fb_bitfield b;
191 struct fb_bitfield a;
192};
193
194static inline void s3c_fb_init_palette(unsigned int window,
195 struct s3c_fb_palette *palette)
196{
197 if (window < 2) {
198 /* Windows 0/1 are 8/8/8 or A/8/8/8 */
199 palette->r.offset = 16;
200 palette->r.length = 8;
201 palette->g.offset = 8;
202 palette->g.length = 8;
203 palette->b.offset = 0;
204 palette->b.length = 8;
205 } else {
206 /* currently we assume RGB 5/6/5 */
207 palette->r.offset = 11;
208 palette->r.length = 5;
209 palette->g.offset = 5;
210 palette->g.length = 6;
211 palette->b.offset = 0;
212 palette->b.length = 5;
213 }
214}
215
216/* Notes on per-window bpp settings
217 *
218 * Value Win0 Win1 Win2 Win3 Win 4
219 * 0000 1(P) 1(P) 1(P) 1(P) 1(P)
220 * 0001 2(P) 2(P) 2(P) 2(P) 2(P)
221 * 0010 4(P) 4(P) 4(P) 4(P) -none-
222 * 0011 8(P) 8(P) -none- -none- -none-
223 * 0100 -none- 8(A232) 8(A232) -none- -none-
224 * 0101 16(565) 16(565) 16(565) 16(565) 16(565)
225 * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555)
226 * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555)
227 * 1000 18(666) 18(666) 18(666) 18(666) 18(666)
228 * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665)
229 * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666)
230 * 1011 24(888) 24(888) 24(888) 24(888) 24(888)
231 * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887)
232 * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888)
233 * 1110 -none- -none- -none- -none- -none-
234 * 1111 -none- -none- -none- -none- -none-
235*/
diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h
new file mode 100644
index 000000000000..0ef806e50344
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
@@ -0,0 +1,366 @@
1/* arch/arm/plat-samsung/include/plat/regs-fb.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C Platform - new-style framebuffer register definitions
9 *
10 * This is the register set for the new style framebuffer interface
11 * found from the S3C2443 onwards into the S3C2416, S3C2450 and the
12 * S3C64XX series such as the S3C6400 and S3C6410.
13 *
14 * The file does not contain the cpu specific items which are based on
15 * whichever architecture is selected, it only contains the core of the
16 * register set. See <mach/regs-fb.h> to get the specifics.
17 *
18 * Note, we changed to using regs-fb.h as it avoids any clashes with
19 * the original regs-lcd.h so out of the way of regs-lcd.h as well as
20 * indicating the newer block is much more than just an LCD interface.
21 *
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License version 2 as
24 * published by the Free Software Foundation.
25*/
26
27/* Please do not include this file directly, use <mach/regs-fb.h> to
28 * ensure all the localised SoC support is included as necessary.
29*/
30
31/* VIDCON0 */
32
33#define VIDCON0 (0x00)
34#define VIDCON0_INTERLACE (1 << 29)
35#define VIDCON0_VIDOUT_MASK (0x3 << 26)
36#define VIDCON0_VIDOUT_SHIFT (26)
37#define VIDCON0_VIDOUT_RGB (0x0 << 26)
38#define VIDCON0_VIDOUT_TV (0x1 << 26)
39#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
40#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
41
42#define VIDCON0_L1_DATA_MASK (0x7 << 23)
43#define VIDCON0_L1_DATA_SHIFT (23)
44#define VIDCON0_L1_DATA_16BPP (0x0 << 23)
45#define VIDCON0_L1_DATA_18BPP16 (0x1 << 23)
46#define VIDCON0_L1_DATA_18BPP9 (0x2 << 23)
47#define VIDCON0_L1_DATA_24BPP (0x3 << 23)
48#define VIDCON0_L1_DATA_18BPP (0x4 << 23)
49#define VIDCON0_L1_DATA_16BPP8 (0x5 << 23)
50
51#define VIDCON0_L0_DATA_MASK (0x7 << 20)
52#define VIDCON0_L0_DATA_SHIFT (20)
53#define VIDCON0_L0_DATA_16BPP (0x0 << 20)
54#define VIDCON0_L0_DATA_18BPP16 (0x1 << 20)
55#define VIDCON0_L0_DATA_18BPP9 (0x2 << 20)
56#define VIDCON0_L0_DATA_24BPP (0x3 << 20)
57#define VIDCON0_L0_DATA_18BPP (0x4 << 20)
58#define VIDCON0_L0_DATA_16BPP8 (0x5 << 20)
59
60#define VIDCON0_PNRMODE_MASK (0x3 << 17)
61#define VIDCON0_PNRMODE_SHIFT (17)
62#define VIDCON0_PNRMODE_RGB (0x0 << 17)
63#define VIDCON0_PNRMODE_BGR (0x1 << 17)
64#define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17)
65#define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17)
66
67#define VIDCON0_CLKVALUP (1 << 16)
68#define VIDCON0_CLKVAL_F_MASK (0xff << 6)
69#define VIDCON0_CLKVAL_F_SHIFT (6)
70#define VIDCON0_CLKVAL_F_LIMIT (0xff)
71#define VIDCON0_CLKVAL_F(_x) ((_x) << 6)
72#define VIDCON0_VLCKFREE (1 << 5)
73#define VIDCON0_CLKDIR (1 << 4)
74
75#define VIDCON0_CLKSEL_MASK (0x3 << 2)
76#define VIDCON0_CLKSEL_SHIFT (2)
77#define VIDCON0_CLKSEL_HCLK (0x0 << 2)
78#define VIDCON0_CLKSEL_LCD (0x1 << 2)
79#define VIDCON0_CLKSEL_27M (0x3 << 2)
80
81#define VIDCON0_ENVID (1 << 1)
82#define VIDCON0_ENVID_F (1 << 0)
83
84#define VIDCON1 (0x04)
85#define VIDCON1_LINECNT_MASK (0x7ff << 16)
86#define VIDCON1_LINECNT_SHIFT (16)
87#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
88#define VIDCON1_VSTATUS_MASK (0x3 << 13)
89#define VIDCON1_VSTATUS_SHIFT (13)
90#define VIDCON1_VSTATUS_VSYNC (0x0 << 13)
91#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13)
92#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)
93#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13)
94
95#define VIDCON1_INV_VCLK (1 << 7)
96#define VIDCON1_INV_HSYNC (1 << 6)
97#define VIDCON1_INV_VSYNC (1 << 5)
98#define VIDCON1_INV_VDEN (1 << 4)
99
100/* VIDCON2 */
101
102#define VIDCON2 (0x08)
103#define VIDCON2_EN601 (1 << 23)
104#define VIDCON2_TVFMTSEL_SW (1 << 14)
105
106#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
107#define VIDCON2_TVFMTSEL1_SHIFT (12)
108#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
109#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
110#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
111
112#define VIDCON2_ORGYCbCr (1 << 8)
113#define VIDCON2_YUVORDCrCb (1 << 7)
114
115/* VIDTCON0 */
116
117#define VIDTCON0_VBPDE_MASK (0xff << 24)
118#define VIDTCON0_VBPDE_SHIFT (24)
119#define VIDTCON0_VBPDE_LIMIT (0xff)
120#define VIDTCON0_VBPDE(_x) ((_x) << 24)
121
122#define VIDTCON0_VBPD_MASK (0xff << 16)
123#define VIDTCON0_VBPD_SHIFT (16)
124#define VIDTCON0_VBPD_LIMIT (0xff)
125#define VIDTCON0_VBPD(_x) ((_x) << 16)
126
127#define VIDTCON0_VFPD_MASK (0xff << 8)
128#define VIDTCON0_VFPD_SHIFT (8)
129#define VIDTCON0_VFPD_LIMIT (0xff)
130#define VIDTCON0_VFPD(_x) ((_x) << 8)
131
132#define VIDTCON0_VSPW_MASK (0xff << 0)
133#define VIDTCON0_VSPW_SHIFT (0)
134#define VIDTCON0_VSPW_LIMIT (0xff)
135#define VIDTCON0_VSPW(_x) ((_x) << 0)
136
137/* VIDTCON1 */
138
139#define VIDTCON1_VFPDE_MASK (0xff << 24)
140#define VIDTCON1_VFPDE_SHIFT (24)
141#define VIDTCON1_VFPDE_LIMIT (0xff)
142#define VIDTCON1_VFPDE(_x) ((_x) << 24)
143
144#define VIDTCON1_HBPD_MASK (0xff << 16)
145#define VIDTCON1_HBPD_SHIFT (16)
146#define VIDTCON1_HBPD_LIMIT (0xff)
147#define VIDTCON1_HBPD(_x) ((_x) << 16)
148
149#define VIDTCON1_HFPD_MASK (0xff << 8)
150#define VIDTCON1_HFPD_SHIFT (8)
151#define VIDTCON1_HFPD_LIMIT (0xff)
152#define VIDTCON1_HFPD(_x) ((_x) << 8)
153
154#define VIDTCON1_HSPW_MASK (0xff << 0)
155#define VIDTCON1_HSPW_SHIFT (0)
156#define VIDTCON1_HSPW_LIMIT (0xff)
157#define VIDTCON1_HSPW(_x) ((_x) << 0)
158
159#define VIDTCON2 (0x18)
160#define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
161#define VIDTCON2_LINEVAL_SHIFT (11)
162#define VIDTCON2_LINEVAL_LIMIT (0x7ff)
163#define VIDTCON2_LINEVAL(_x) ((_x) << 11)
164
165#define VIDTCON2_HOZVAL_MASK (0x7ff << 0)
166#define VIDTCON2_HOZVAL_SHIFT (0)
167#define VIDTCON2_HOZVAL_LIMIT (0x7ff)
168#define VIDTCON2_HOZVAL(_x) ((_x) << 0)
169
170/* WINCONx */
171
172
173#define WINCONx_BITSWP (1 << 18)
174#define WINCONx_BYTSWP (1 << 17)
175#define WINCONx_HAWSWP (1 << 16)
176#define WINCONx_BURSTLEN_MASK (0x3 << 9)
177#define WINCONx_BURSTLEN_SHIFT (9)
178#define WINCONx_BURSTLEN_16WORD (0x0 << 9)
179#define WINCONx_BURSTLEN_8WORD (0x1 << 9)
180#define WINCONx_BURSTLEN_4WORD (0x2 << 9)
181
182#define WINCONx_ENWIN (1 << 0)
183#define WINCON0_BPPMODE_MASK (0xf << 2)
184#define WINCON0_BPPMODE_SHIFT (2)
185#define WINCON0_BPPMODE_1BPP (0x0 << 2)
186#define WINCON0_BPPMODE_2BPP (0x1 << 2)
187#define WINCON0_BPPMODE_4BPP (0x2 << 2)
188#define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2)
189#define WINCON0_BPPMODE_16BPP_565 (0x5 << 2)
190#define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2)
191#define WINCON0_BPPMODE_18BPP_666 (0x8 << 2)
192#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
193
194#define WINCON1_BLD_PIX (1 << 6)
195
196#define WINCON1_ALPHA_SEL (1 << 1)
197#define WINCON1_BPPMODE_MASK (0xf << 2)
198#define WINCON1_BPPMODE_SHIFT (2)
199#define WINCON1_BPPMODE_1BPP (0x0 << 2)
200#define WINCON1_BPPMODE_2BPP (0x1 << 2)
201#define WINCON1_BPPMODE_4BPP (0x2 << 2)
202#define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2)
203#define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2)
204#define WINCON1_BPPMODE_16BPP_565 (0x5 << 2)
205#define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2)
206#define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2)
207#define WINCON1_BPPMODE_18BPP_666 (0x8 << 2)
208#define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2)
209#define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2)
210#define WINCON1_BPPMODE_24BPP_888 (0xb << 2)
211#define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2)
212#define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2)
213#define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2)
214
215
216#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11)
217#define VIDOSDxA_TOPLEFT_X_SHIFT (11)
218#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff)
219#define VIDOSDxA_TOPLEFT_X(_x) ((_x) << 11)
220
221#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0)
222#define VIDOSDxA_TOPLEFT_Y_SHIFT (0)
223#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff)
224#define VIDOSDxA_TOPLEFT_Y(_x) ((_x) << 0)
225
226#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11)
227#define VIDOSDxB_BOTRIGHT_X_SHIFT (11)
228#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff)
229#define VIDOSDxB_BOTRIGHT_X(_x) ((_x) << 11)
230
231#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0)
232#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0)
233#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff)
234#define VIDOSDxB_BOTRIGHT_Y(_x) ((_x) << 0)
235
236/* For VIDOSD[1..4]C */
237#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20)
238#define VIDISD14C_ALPHA0_G_MASK (0xf << 16)
239#define VIDISD14C_ALPHA0_G_SHIFT (16)
240#define VIDISD14C_ALPHA0_G_LIMIT (0xf)
241#define VIDISD14C_ALPHA0_G(_x) ((_x) << 16)
242#define VIDISD14C_ALPHA0_B_MASK (0xf << 12)
243#define VIDISD14C_ALPHA0_B_SHIFT (12)
244#define VIDISD14C_ALPHA0_B_LIMIT (0xf)
245#define VIDISD14C_ALPHA0_B(_x) ((_x) << 12)
246#define VIDISD14C_ALPHA1_R_MASK (0xf << 8)
247#define VIDISD14C_ALPHA1_R_SHIFT (8)
248#define VIDISD14C_ALPHA1_R_LIMIT (0xf)
249#define VIDISD14C_ALPHA1_R(_x) ((_x) << 8)
250#define VIDISD14C_ALPHA1_G_MASK (0xf << 4)
251#define VIDISD14C_ALPHA1_G_SHIFT (4)
252#define VIDISD14C_ALPHA1_G_LIMIT (0xf)
253#define VIDISD14C_ALPHA1_G(_x) ((_x) << 4)
254#define VIDISD14C_ALPHA1_B_MASK (0xf << 0)
255#define VIDISD14C_ALPHA1_B_SHIFT (0)
256#define VIDISD14C_ALPHA1_B_LIMIT (0xf)
257#define VIDISD14C_ALPHA1_B(_x) ((_x) << 0)
258
259/* Video buffer addresses */
260#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))
261#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))
262#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8))
263#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
264#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))
265
266#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13)
267#define VIDW_BUF_SIZE_OFFSET_SHIFT (13)
268#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff)
269#define VIDW_BUF_SIZE_OFFSET(_x) ((_x) << 13)
270
271#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0)
272#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0)
273#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff)
274#define VIDW_BUF_SIZE_PAGEWIDTH(_x) ((_x) << 0)
275
276/* Interrupt controls and status */
277
278#define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20)
279#define VIDINTCON0_FIFOINTERVAL_SHIFT (20)
280#define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f)
281#define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20)
282
283#define VIDINTCON0_INT_SYSMAINCON (1 << 19)
284#define VIDINTCON0_INT_SYSSUBCON (1 << 18)
285#define VIDINTCON0_INT_I80IFDONE (1 << 17)
286
287#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15)
288#define VIDINTCON0_FRAMESEL0_SHIFT (15)
289#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15)
290#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15)
291#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)
292#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15)
293
294#define VIDINTCON0_FRAMESEL1 (1 << 14)
295#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 14)
296#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 14)
297#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 14)
298#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 14)
299
300#define VIDINTCON0_INT_FRAME (1 << 12)
301#define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5)
302#define VIDINTCON0_FIFIOSEL_SHIFT (5)
303#define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5)
304#define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5)
305
306#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2)
307#define VIDINTCON0_FIFOLEVEL_SHIFT (2)
308#define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2)
309#define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2)
310#define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2)
311#define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2)
312#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2)
313
314#define VIDINTCON0_INT_FIFO_MASK (0x3 << 0)
315#define VIDINTCON0_INT_FIFO_SHIFT (0)
316#define VIDINTCON0_INT_ENABLE (1 << 0)
317
318#define VIDINTCON1 (0x134)
319#define VIDINTCON1_INT_I180 (1 << 2)
320#define VIDINTCON1_INT_FRAME (1 << 1)
321#define VIDINTCON1_INT_FIFO (1 << 0)
322
323/* Window colour-key control registers */
324
325#define WxKEYCON0_KEYBL_EN (1 << 26)
326#define WxKEYCON0_KEYEN_F (1 << 25)
327#define WxKEYCON0_DIRCON (1 << 24)
328#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0)
329#define WxKEYCON0_COMPKEY_SHIFT (0)
330#define WxKEYCON0_COMPKEY_LIMIT (0xffffff)
331#define WxKEYCON0_COMPKEY(_x) ((_x) << 0)
332#define WxKEYCON1_COLVAL_MASK (0xffffff << 0)
333#define WxKEYCON1_COLVAL_SHIFT (0)
334#define WxKEYCON1_COLVAL_LIMIT (0xffffff)
335#define WxKEYCON1_COLVAL(_x) ((_x) << 0)
336
337
338/* Window blanking (MAP) */
339
340#define WINxMAP_MAP (1 << 24)
341#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0)
342#define WINxMAP_MAP_COLOUR_SHIFT (0)
343#define WINxMAP_MAP_COLOUR_LIMIT (0xffffff)
344#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0)
345
346#define WPALCON_PAL_UPDATE (1 << 9)
347#define WPALCON_W1PAL_MASK (0x7 << 3)
348#define WPALCON_W1PAL_SHIFT (3)
349#define WPALCON_W1PAL_25BPP_A888 (0x0 << 3)
350#define WPALCON_W1PAL_24BPP (0x1 << 3)
351#define WPALCON_W1PAL_19BPP_A666 (0x2 << 3)
352#define WPALCON_W1PAL_18BPP_A665 (0x3 << 3)
353#define WPALCON_W1PAL_18BPP (0x4 << 3)
354#define WPALCON_W1PAL_16BPP_A555 (0x5 << 3)
355#define WPALCON_W1PAL_16BPP_565 (0x6 << 3)
356
357#define WPALCON_W0PAL_MASK (0x7 << 0)
358#define WPALCON_W0PAL_SHIFT (0)
359#define WPALCON_W0PAL_25BPP_A888 (0x0 << 0)
360#define WPALCON_W0PAL_24BPP (0x1 << 0)
361#define WPALCON_W0PAL_19BPP_A666 (0x2 << 0)
362#define WPALCON_W0PAL_18BPP_A665 (0x3 << 0)
363#define WPALCON_W0PAL_18BPP (0x4 << 0)
364#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
365#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
366
diff --git a/arch/arm/plat-samsung/include/plat/regs-iic.h b/arch/arm/plat-samsung/include/plat/regs-iic.h
new file mode 100644
index 000000000000..2f7c17de8ac8
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-iic.h
@@ -0,0 +1,56 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-iic.h
2 *
3 * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 I2C Controller
11*/
12
13#ifndef __ASM_ARCH_REGS_IIC_H
14#define __ASM_ARCH_REGS_IIC_H __FILE__
15
16/* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
17
18#define S3C2410_IICREG(x) (x)
19
20#define S3C2410_IICCON S3C2410_IICREG(0x00)
21#define S3C2410_IICSTAT S3C2410_IICREG(0x04)
22#define S3C2410_IICADD S3C2410_IICREG(0x08)
23#define S3C2410_IICDS S3C2410_IICREG(0x0C)
24#define S3C2440_IICLC S3C2410_IICREG(0x10)
25
26#define S3C2410_IICCON_ACKEN (1<<7)
27#define S3C2410_IICCON_TXDIV_16 (0<<6)
28#define S3C2410_IICCON_TXDIV_512 (1<<6)
29#define S3C2410_IICCON_IRQEN (1<<5)
30#define S3C2410_IICCON_IRQPEND (1<<4)
31#define S3C2410_IICCON_SCALE(x) ((x)&15)
32#define S3C2410_IICCON_SCALEMASK (0xf)
33
34#define S3C2410_IICSTAT_MASTER_RX (2<<6)
35#define S3C2410_IICSTAT_MASTER_TX (3<<6)
36#define S3C2410_IICSTAT_SLAVE_RX (0<<6)
37#define S3C2410_IICSTAT_SLAVE_TX (1<<6)
38#define S3C2410_IICSTAT_MODEMASK (3<<6)
39
40#define S3C2410_IICSTAT_START (1<<5)
41#define S3C2410_IICSTAT_BUSBUSY (1<<5)
42#define S3C2410_IICSTAT_TXRXEN (1<<4)
43#define S3C2410_IICSTAT_ARBITR (1<<3)
44#define S3C2410_IICSTAT_ASSLAVE (1<<2)
45#define S3C2410_IICSTAT_ADDR0 (1<<1)
46#define S3C2410_IICSTAT_LASTBIT (1<<0)
47
48#define S3C2410_IICLC_SDA_DELAY0 (0 << 0)
49#define S3C2410_IICLC_SDA_DELAY5 (1 << 0)
50#define S3C2410_IICLC_SDA_DELAY10 (2 << 0)
51#define S3C2410_IICLC_SDA_DELAY15 (3 << 0)
52#define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0)
53
54#define S3C2410_IICLC_FILTER_ON (1<<2)
55
56#endif /* __ASM_ARCH_REGS_IIC_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-irqtype.h b/arch/arm/plat-samsung/include/plat/regs-irqtype.h
new file mode 100644
index 000000000000..c63cd3fc5ad3
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-irqtype.h
@@ -0,0 +1,21 @@
1/* arch/arm/plat-s3c/include/plat/regs-irqtype.h
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C - IRQ detection types.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14/* values for S3C2410_EXTINT0/1/2 and other cpus in the series, including
15 * the S3C64XX
16*/
17#define S3C2410_EXTINT_LOWLEV (0x00)
18#define S3C2410_EXTINT_HILEV (0x01)
19#define S3C2410_EXTINT_FALLEDGE (0x02)
20#define S3C2410_EXTINT_RISEEDGE (0x04)
21#define S3C2410_EXTINT_BOTHEDGE (0x06)
diff --git a/arch/arm/plat-samsung/include/plat/regs-nand.h b/arch/arm/plat-samsung/include/plat/regs-nand.h
new file mode 100644
index 000000000000..238efea7b9e4
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-nand.h
@@ -0,0 +1,123 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-nand.h
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 NAND register definitions
11*/
12
13#ifndef __ASM_ARM_REGS_NAND
14#define __ASM_ARM_REGS_NAND
15
16
17#define S3C2410_NFREG(x) (x)
18
19#define S3C2410_NFCONF S3C2410_NFREG(0x00)
20#define S3C2410_NFCMD S3C2410_NFREG(0x04)
21#define S3C2410_NFADDR S3C2410_NFREG(0x08)
22#define S3C2410_NFDATA S3C2410_NFREG(0x0C)
23#define S3C2410_NFSTAT S3C2410_NFREG(0x10)
24#define S3C2410_NFECC S3C2410_NFREG(0x14)
25
26#define S3C2440_NFCONT S3C2410_NFREG(0x04)
27#define S3C2440_NFCMD S3C2410_NFREG(0x08)
28#define S3C2440_NFADDR S3C2410_NFREG(0x0C)
29#define S3C2440_NFDATA S3C2410_NFREG(0x10)
30#define S3C2440_NFECCD0 S3C2410_NFREG(0x14)
31#define S3C2440_NFECCD1 S3C2410_NFREG(0x18)
32#define S3C2440_NFECCD S3C2410_NFREG(0x1C)
33#define S3C2440_NFSTAT S3C2410_NFREG(0x20)
34#define S3C2440_NFESTAT0 S3C2410_NFREG(0x24)
35#define S3C2440_NFESTAT1 S3C2410_NFREG(0x28)
36#define S3C2440_NFMECC0 S3C2410_NFREG(0x2C)
37#define S3C2440_NFMECC1 S3C2410_NFREG(0x30)
38#define S3C2440_NFSECC S3C2410_NFREG(0x34)
39#define S3C2440_NFSBLK S3C2410_NFREG(0x38)
40#define S3C2440_NFEBLK S3C2410_NFREG(0x3C)
41
42#define S3C2412_NFSBLK S3C2410_NFREG(0x20)
43#define S3C2412_NFEBLK S3C2410_NFREG(0x24)
44#define S3C2412_NFSTAT S3C2410_NFREG(0x28)
45#define S3C2412_NFMECC_ERR0 S3C2410_NFREG(0x2C)
46#define S3C2412_NFMECC_ERR1 S3C2410_NFREG(0x30)
47#define S3C2412_NFMECC0 S3C2410_NFREG(0x34)
48#define S3C2412_NFMECC1 S3C2410_NFREG(0x38)
49#define S3C2412_NFSECC S3C2410_NFREG(0x3C)
50
51#define S3C2410_NFCONF_EN (1<<15)
52#define S3C2410_NFCONF_512BYTE (1<<14)
53#define S3C2410_NFCONF_4STEP (1<<13)
54#define S3C2410_NFCONF_INITECC (1<<12)
55#define S3C2410_NFCONF_nFCE (1<<11)
56#define S3C2410_NFCONF_TACLS(x) ((x)<<8)
57#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4)
58#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0)
59
60#define S3C2410_NFSTAT_BUSY (1<<0)
61
62#define S3C2440_NFCONF_BUSWIDTH_8 (0<<0)
63#define S3C2440_NFCONF_BUSWIDTH_16 (1<<0)
64#define S3C2440_NFCONF_ADVFLASH (1<<3)
65#define S3C2440_NFCONF_TACLS(x) ((x)<<12)
66#define S3C2440_NFCONF_TWRPH0(x) ((x)<<8)
67#define S3C2440_NFCONF_TWRPH1(x) ((x)<<4)
68
69#define S3C2440_NFCONT_LOCKTIGHT (1<<13)
70#define S3C2440_NFCONT_SOFTLOCK (1<<12)
71#define S3C2440_NFCONT_ILLEGALACC_EN (1<<10)
72#define S3C2440_NFCONT_RNBINT_EN (1<<9)
73#define S3C2440_NFCONT_RN_FALLING (1<<8)
74#define S3C2440_NFCONT_SPARE_ECCLOCK (1<<6)
75#define S3C2440_NFCONT_MAIN_ECCLOCK (1<<5)
76#define S3C2440_NFCONT_INITECC (1<<4)
77#define S3C2440_NFCONT_nFCE (1<<1)
78#define S3C2440_NFCONT_ENABLE (1<<0)
79
80#define S3C2440_NFSTAT_READY (1<<0)
81#define S3C2440_NFSTAT_nCE (1<<1)
82#define S3C2440_NFSTAT_RnB_CHANGE (1<<2)
83#define S3C2440_NFSTAT_ILLEGAL_ACCESS (1<<3)
84
85#define S3C2412_NFCONF_NANDBOOT (1<<31)
86#define S3C2412_NFCONF_ECCCLKCON (1<<30)
87#define S3C2412_NFCONF_ECC_MLC (1<<24)
88#define S3C2412_NFCONF_TACLS_MASK (7<<12) /* 1 extra bit of Tacls */
89
90#define S3C2412_NFCONT_ECC4_DIRWR (1<<18)
91#define S3C2412_NFCONT_LOCKTIGHT (1<<17)
92#define S3C2412_NFCONT_SOFTLOCK (1<<16)
93#define S3C2412_NFCONT_ECC4_ENCINT (1<<13)
94#define S3C2412_NFCONT_ECC4_DECINT (1<<12)
95#define S3C2412_NFCONT_MAIN_ECC_LOCK (1<<7)
96#define S3C2412_NFCONT_INIT_MAIN_ECC (1<<5)
97#define S3C2412_NFCONT_nFCE1 (1<<2)
98#define S3C2412_NFCONT_nFCE0 (1<<1)
99
100#define S3C2412_NFSTAT_ECC_ENCDONE (1<<7)
101#define S3C2412_NFSTAT_ECC_DECDONE (1<<6)
102#define S3C2412_NFSTAT_ILLEGAL_ACCESS (1<<5)
103#define S3C2412_NFSTAT_RnB_CHANGE (1<<4)
104#define S3C2412_NFSTAT_nFCE1 (1<<3)
105#define S3C2412_NFSTAT_nFCE0 (1<<2)
106#define S3C2412_NFSTAT_Res1 (1<<1)
107#define S3C2412_NFSTAT_READY (1<<0)
108
109#define S3C2412_NFECCERR_SERRDATA(x) (((x) >> 21) & 0xf)
110#define S3C2412_NFECCERR_SERRBIT(x) (((x) >> 18) & 0x7)
111#define S3C2412_NFECCERR_MERRDATA(x) (((x) >> 7) & 0x3ff)
112#define S3C2412_NFECCERR_MERRBIT(x) (((x) >> 4) & 0x7)
113#define S3C2412_NFECCERR_SPARE_ERR(x) (((x) >> 2) & 0x3)
114#define S3C2412_NFECCERR_MAIN_ERR(x) (((x) >> 2) & 0x3)
115#define S3C2412_NFECCERR_NONE (0)
116#define S3C2412_NFECCERR_1BIT (1)
117#define S3C2412_NFECCERR_MULTIBIT (2)
118#define S3C2412_NFECCERR_ECCAREA (3)
119
120
121
122#endif /* __ASM_ARM_REGS_NAND */
123
diff --git a/arch/arm/plat-samsung/include/plat/regs-rtc.h b/arch/arm/plat-samsung/include/plat/regs-rtc.h
new file mode 100644
index 000000000000..d5837cf8e402
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-rtc.h
@@ -0,0 +1,61 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-rtc.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 Internal RTC register definition
11*/
12
13#ifndef __ASM_ARCH_REGS_RTC_H
14#define __ASM_ARCH_REGS_RTC_H __FILE__
15
16#define S3C2410_RTCREG(x) (x)
17
18#define S3C2410_RTCCON S3C2410_RTCREG(0x40)
19#define S3C2410_RTCCON_RTCEN (1<<0)
20#define S3C2410_RTCCON_CLKSEL (1<<1)
21#define S3C2410_RTCCON_CNTSEL (1<<2)
22#define S3C2410_RTCCON_CLKRST (1<<3)
23
24#define S3C2410_TICNT S3C2410_RTCREG(0x44)
25#define S3C2410_TICNT_ENABLE (1<<7)
26
27#define S3C2410_RTCALM S3C2410_RTCREG(0x50)
28#define S3C2410_RTCALM_ALMEN (1<<6)
29#define S3C2410_RTCALM_YEAREN (1<<5)
30#define S3C2410_RTCALM_MONEN (1<<4)
31#define S3C2410_RTCALM_DAYEN (1<<3)
32#define S3C2410_RTCALM_HOUREN (1<<2)
33#define S3C2410_RTCALM_MINEN (1<<1)
34#define S3C2410_RTCALM_SECEN (1<<0)
35
36#define S3C2410_RTCALM_ALL \
37 S3C2410_RTCALM_ALMEN | S3C2410_RTCALM_YEAREN | S3C2410_RTCALM_MONEN |\
38 S3C2410_RTCALM_DAYEN | S3C2410_RTCALM_HOUREN | S3C2410_RTCALM_MINEN |\
39 S3C2410_RTCALM_SECEN
40
41
42#define S3C2410_ALMSEC S3C2410_RTCREG(0x54)
43#define S3C2410_ALMMIN S3C2410_RTCREG(0x58)
44#define S3C2410_ALMHOUR S3C2410_RTCREG(0x5c)
45
46#define S3C2410_ALMDATE S3C2410_RTCREG(0x60)
47#define S3C2410_ALMMON S3C2410_RTCREG(0x64)
48#define S3C2410_ALMYEAR S3C2410_RTCREG(0x68)
49
50#define S3C2410_RTCRST S3C2410_RTCREG(0x6c)
51
52#define S3C2410_RTCSEC S3C2410_RTCREG(0x70)
53#define S3C2410_RTCMIN S3C2410_RTCREG(0x74)
54#define S3C2410_RTCHOUR S3C2410_RTCREG(0x78)
55#define S3C2410_RTCDATE S3C2410_RTCREG(0x7c)
56#define S3C2410_RTCDAY S3C2410_RTCREG(0x80)
57#define S3C2410_RTCMON S3C2410_RTCREG(0x84)
58#define S3C2410_RTCYEAR S3C2410_RTCREG(0x88)
59
60
61#endif /* __ASM_ARCH_REGS_RTC_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-s3c2412-iis.h b/arch/arm/plat-samsung/include/plat/regs-s3c2412-iis.h
new file mode 100644
index 000000000000..abf2fbc2eb2f
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-s3c2412-iis.h
@@ -0,0 +1,82 @@
1/* linux/include/asm-arm/plat-s3c24xx/regs-s3c2412-iis.h
2 *
3 * Copyright 2007 Simtec Electronics <linux@simtec.co.uk>
4 * http://armlinux.simtec.co.uk/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2412 IIS register definition
11*/
12
13#ifndef __ASM_ARCH_REGS_S3C2412_IIS_H
14#define __ASM_ARCH_REGS_S3C2412_IIS_H
15
16#define S3C2412_IISCON (0x00)
17#define S3C2412_IISMOD (0x04)
18#define S3C2412_IISFIC (0x08)
19#define S3C2412_IISPSR (0x0C)
20#define S3C2412_IISTXD (0x10)
21#define S3C2412_IISRXD (0x14)
22
23#define S3C2412_IISCON_LRINDEX (1 << 11)
24#define S3C2412_IISCON_TXFIFO_EMPTY (1 << 10)
25#define S3C2412_IISCON_RXFIFO_EMPTY (1 << 9)
26#define S3C2412_IISCON_TXFIFO_FULL (1 << 8)
27#define S3C2412_IISCON_RXFIFO_FULL (1 << 7)
28#define S3C2412_IISCON_TXDMA_PAUSE (1 << 6)
29#define S3C2412_IISCON_RXDMA_PAUSE (1 << 5)
30#define S3C2412_IISCON_TXCH_PAUSE (1 << 4)
31#define S3C2412_IISCON_RXCH_PAUSE (1 << 3)
32#define S3C2412_IISCON_TXDMA_ACTIVE (1 << 2)
33#define S3C2412_IISCON_RXDMA_ACTIVE (1 << 1)
34#define S3C2412_IISCON_IIS_ACTIVE (1 << 0)
35
36#define S3C64XX_IISMOD_BLC_16BIT (0 << 13)
37#define S3C64XX_IISMOD_BLC_8BIT (1 << 13)
38#define S3C64XX_IISMOD_BLC_24BIT (2 << 13)
39#define S3C64XX_IISMOD_BLC_MASK (3 << 13)
40
41#define S3C64XX_IISMOD_IMS_PCLK (0 << 10)
42#define S3C64XX_IISMOD_IMS_SYSMUX (1 << 10)
43
44#define S3C2412_IISMOD_MASTER_INTERNAL (0 << 10)
45#define S3C2412_IISMOD_MASTER_EXTERNAL (1 << 10)
46#define S3C2412_IISMOD_SLAVE (2 << 10)
47#define S3C2412_IISMOD_MASTER_MASK (3 << 10)
48#define S3C2412_IISMOD_MODE_TXONLY (0 << 8)
49#define S3C2412_IISMOD_MODE_RXONLY (1 << 8)
50#define S3C2412_IISMOD_MODE_TXRX (2 << 8)
51#define S3C2412_IISMOD_MODE_MASK (3 << 8)
52#define S3C2412_IISMOD_LR_LLOW (0 << 7)
53#define S3C2412_IISMOD_LR_RLOW (1 << 7)
54#define S3C2412_IISMOD_SDF_IIS (0 << 5)
55#define S3C2412_IISMOD_SDF_MSB (1 << 5)
56#define S3C2412_IISMOD_SDF_LSB (2 << 5)
57#define S3C2412_IISMOD_SDF_MASK (3 << 5)
58#define S3C2412_IISMOD_RCLK_256FS (0 << 3)
59#define S3C2412_IISMOD_RCLK_512FS (1 << 3)
60#define S3C2412_IISMOD_RCLK_384FS (2 << 3)
61#define S3C2412_IISMOD_RCLK_768FS (3 << 3)
62#define S3C2412_IISMOD_RCLK_MASK (3 << 3)
63#define S3C2412_IISMOD_BCLK_32FS (0 << 1)
64#define S3C2412_IISMOD_BCLK_48FS (1 << 1)
65#define S3C2412_IISMOD_BCLK_16FS (2 << 1)
66#define S3C2412_IISMOD_BCLK_24FS (3 << 1)
67#define S3C2412_IISMOD_BCLK_MASK (3 << 1)
68#define S3C2412_IISMOD_8BIT (1 << 0)
69
70#define S3C64XX_IISMOD_CDCLKCON (1 << 12)
71
72#define S3C2412_IISPSR_PSREN (1 << 15)
73
74#define S3C2412_IISFIC_TXFLUSH (1 << 15)
75#define S3C2412_IISFIC_RXFLUSH (1 << 7)
76#define S3C2412_IISFIC_TXCOUNT(x) (((x) >> 8) & 0xf)
77#define S3C2412_IISFIC_RXCOUNT(x) (((x) >> 0) & 0xf)
78
79
80
81#endif /* __ASM_ARCH_REGS_S3C2412_IIS_H */
82
diff --git a/arch/arm/plat-samsung/include/plat/regs-sdhci.h b/arch/arm/plat-samsung/include/plat/regs-sdhci.h
new file mode 100644
index 000000000000..e34049ad44cc
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-sdhci.h
@@ -0,0 +1,87 @@
1/* linux/arch/arm/plat-s3c/include/plat/regs-sdhci.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C Platform - SDHCI (HSMMC) register definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __PLAT_S3C_SDHCI_REGS_H
16#define __PLAT_S3C_SDHCI_REGS_H __FILE__
17
18#define S3C_SDHCI_CONTROL2 (0x80)
19#define S3C_SDHCI_CONTROL3 (0x84)
20#define S3C64XX_SDHCI_CONTROL4 (0x8C)
21
22#define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31)
23#define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK (1 << 30)
24#define S3C_SDHCI_CTRL2_CDINVRXD3 (1 << 29)
25#define S3C_SDHCI_CTRL2_SLCARDOUT (1 << 28)
26
27#define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24)
28#define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT (24)
29#define S3C_SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24)
30
31#define S3C_SDHCI_CTRL2_LVLDAT_MASK (0xff << 16)
32#define S3C_SDHCI_CTRL2_LVLDAT_SHIFT (16)
33#define S3C_SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16)
34
35#define S3C_SDHCI_CTRL2_ENFBCLKTX (1 << 15)
36#define S3C_SDHCI_CTRL2_ENFBCLKRX (1 << 14)
37#define S3C_SDHCI_CTRL2_SDCDSEL (1 << 13)
38#define S3C_SDHCI_CTRL2_SDSIGPC (1 << 12)
39#define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11)
40
41#define S3C_SDHCI_CTRL2_DFCNT_MASK (0x3 << 9)
42#define S3C_SDHCI_CTRL2_DFCNT_SHIFT (9)
43#define S3C_SDHCI_CTRL2_DFCNT_NONE (0x0 << 9)
44#define S3C_SDHCI_CTRL2_DFCNT_4SDCLK (0x1 << 9)
45#define S3C_SDHCI_CTRL2_DFCNT_16SDCLK (0x2 << 9)
46#define S3C_SDHCI_CTRL2_DFCNT_64SDCLK (0x3 << 9)
47
48#define S3C_SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8)
49#define S3C_SDHCI_CTRL2_RWAITMODE (1 << 7)
50#define S3C_SDHCI_CTRL2_DISBUFRD (1 << 6)
51#define S3C_SDHCI_CTRL2_SELBASECLK_MASK (0x3 << 4)
52#define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT (4)
53#define S3C_SDHCI_CTRL2_PWRSYNC (1 << 3)
54#define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1)
55#define S3C_SDHCI_CTRL2_HWINITFIN (1 << 0)
56
57#define S3C_SDHCI_CTRL3_FCSEL3 (1 << 31)
58#define S3C_SDHCI_CTRL3_FCSEL2 (1 << 23)
59#define S3C_SDHCI_CTRL3_FCSEL1 (1 << 15)
60#define S3C_SDHCI_CTRL3_FCSEL0 (1 << 7)
61
62#define S3C_SDHCI_CTRL3_FIA3_MASK (0x7f << 24)
63#define S3C_SDHCI_CTRL3_FIA3_SHIFT (24)
64#define S3C_SDHCI_CTRL3_FIA3(_x) ((_x) << 24)
65
66#define S3C_SDHCI_CTRL3_FIA2_MASK (0x7f << 16)
67#define S3C_SDHCI_CTRL3_FIA2_SHIFT (16)
68#define S3C_SDHCI_CTRL3_FIA2(_x) ((_x) << 16)
69
70#define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8)
71#define S3C_SDHCI_CTRL3_FIA1_SHIFT (8)
72#define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8)
73
74#define S3C_SDHCI_CTRL3_FIA0_MASK (0x7f << 0)
75#define S3C_SDHCI_CTRL3_FIA0_SHIFT (0)
76#define S3C_SDHCI_CTRL3_FIA0(_x) ((_x) << 0)
77
78#define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK (0x3 << 16)
79#define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT (16)
80#define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA (0x0 << 16)
81#define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA (0x1 << 16)
82#define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA (0x2 << 16)
83#define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA (0x3 << 16)
84
85#define S3C64XX_SDHCI_CONTROL4_BUSY (1)
86
87#endif /* __PLAT_S3C_SDHCI_REGS_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-serial.h b/arch/arm/plat-samsung/include/plat/regs-serial.h
new file mode 100644
index 000000000000..a6eba8496b24
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-serial.h
@@ -0,0 +1,281 @@
1/* arch/arm/plat-samsung/include/plat/regs-serial.h
2 *
3 * From linux/include/asm-arm/hardware/serial_s3c2410.h
4 *
5 * Internal header file for Samsung S3C2410 serial ports (UART0-2)
6 *
7 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
8 *
9 * Additional defines, Copyright 2003 Simtec Electronics (linux@simtec.co.uk)
10 *
11 * Adapted from:
12 *
13 * Internal header file for MX1ADS serial ports (UART1 & 2)
14 *
15 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2 of the License, or
20 * (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30*/
31
32#ifndef __ASM_ARM_REGS_SERIAL_H
33#define __ASM_ARM_REGS_SERIAL_H
34
35#define S3C24XX_VA_UART0 (S3C_VA_UART)
36#define S3C24XX_VA_UART1 (S3C_VA_UART + 0x4000 )
37#define S3C24XX_VA_UART2 (S3C_VA_UART + 0x8000 )
38#define S3C24XX_VA_UART3 (S3C_VA_UART + 0xC000 )
39
40#define S3C2410_PA_UART0 (S3C24XX_PA_UART)
41#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 )
42#define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 )
43#define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 )
44
45#define S3C2410_URXH (0x24)
46#define S3C2410_UTXH (0x20)
47#define S3C2410_ULCON (0x00)
48#define S3C2410_UCON (0x04)
49#define S3C2410_UFCON (0x08)
50#define S3C2410_UMCON (0x0C)
51#define S3C2410_UBRDIV (0x28)
52#define S3C2410_UTRSTAT (0x10)
53#define S3C2410_UERSTAT (0x14)
54#define S3C2410_UFSTAT (0x18)
55#define S3C2410_UMSTAT (0x1C)
56
57#define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3))
58
59#define S3C2410_LCON_CS5 (0x0)
60#define S3C2410_LCON_CS6 (0x1)
61#define S3C2410_LCON_CS7 (0x2)
62#define S3C2410_LCON_CS8 (0x3)
63#define S3C2410_LCON_CSMASK (0x3)
64
65#define S3C2410_LCON_PNONE (0x0)
66#define S3C2410_LCON_PEVEN (0x5 << 3)
67#define S3C2410_LCON_PODD (0x4 << 3)
68#define S3C2410_LCON_PMASK (0x7 << 3)
69
70#define S3C2410_LCON_STOPB (1<<2)
71#define S3C2410_LCON_IRM (1<<6)
72
73#define S3C2440_UCON_CLKMASK (3<<10)
74#define S3C2440_UCON_PCLK (0<<10)
75#define S3C2440_UCON_UCLK (1<<10)
76#define S3C2440_UCON_PCLK2 (2<<10)
77#define S3C2440_UCON_FCLK (3<<10)
78#define S3C2443_UCON_EPLL (3<<10)
79
80#define S3C6400_UCON_CLKMASK (3<<10)
81#define S3C6400_UCON_PCLK (0<<10)
82#define S3C6400_UCON_PCLK2 (2<<10)
83#define S3C6400_UCON_UCLK0 (1<<10)
84#define S3C6400_UCON_UCLK1 (3<<10)
85
86#define S3C2440_UCON2_FCLK_EN (1<<15)
87#define S3C2440_UCON0_DIVMASK (15 << 12)
88#define S3C2440_UCON1_DIVMASK (15 << 12)
89#define S3C2440_UCON2_DIVMASK (7 << 12)
90#define S3C2440_UCON_DIVSHIFT (12)
91
92#define S3C2412_UCON_CLKMASK (3<<10)
93#define S3C2412_UCON_UCLK (1<<10)
94#define S3C2412_UCON_USYSCLK (3<<10)
95#define S3C2412_UCON_PCLK (0<<10)
96#define S3C2412_UCON_PCLK2 (2<<10)
97
98#define S3C2410_UCON_UCLK (1<<10)
99#define S3C2410_UCON_SBREAK (1<<4)
100
101#define S3C2410_UCON_TXILEVEL (1<<9)
102#define S3C2410_UCON_RXILEVEL (1<<8)
103#define S3C2410_UCON_TXIRQMODE (1<<2)
104#define S3C2410_UCON_RXIRQMODE (1<<0)
105#define S3C2410_UCON_RXFIFO_TOI (1<<7)
106#define S3C2443_UCON_RXERR_IRQEN (1<<6)
107#define S3C2443_UCON_LOOPBACK (1<<5)
108
109#define S3C2410_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
110 S3C2410_UCON_RXILEVEL | \
111 S3C2410_UCON_TXIRQMODE | \
112 S3C2410_UCON_RXIRQMODE | \
113 S3C2410_UCON_RXFIFO_TOI)
114
115#define S3C2410_UFCON_FIFOMODE (1<<0)
116#define S3C2410_UFCON_TXTRIG0 (0<<6)
117#define S3C2410_UFCON_RXTRIG8 (1<<4)
118#define S3C2410_UFCON_RXTRIG12 (2<<4)
119
120/* S3C2440 FIFO trigger levels */
121#define S3C2440_UFCON_RXTRIG1 (0<<4)
122#define S3C2440_UFCON_RXTRIG8 (1<<4)
123#define S3C2440_UFCON_RXTRIG16 (2<<4)
124#define S3C2440_UFCON_RXTRIG32 (3<<4)
125
126#define S3C2440_UFCON_TXTRIG0 (0<<6)
127#define S3C2440_UFCON_TXTRIG16 (1<<6)
128#define S3C2440_UFCON_TXTRIG32 (2<<6)
129#define S3C2440_UFCON_TXTRIG48 (3<<6)
130
131#define S3C2410_UFCON_RESETBOTH (3<<1)
132#define S3C2410_UFCON_RESETTX (1<<2)
133#define S3C2410_UFCON_RESETRX (1<<1)
134
135#define S3C2410_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
136 S3C2410_UFCON_TXTRIG0 | \
137 S3C2410_UFCON_RXTRIG8 )
138
139#define S3C2410_UMCOM_AFC (1<<4)
140#define S3C2410_UMCOM_RTS_LOW (1<<0)
141
142#define S3C2412_UMCON_AFC_63 (0<<5) /* same as s3c2443 */
143#define S3C2412_UMCON_AFC_56 (1<<5)
144#define S3C2412_UMCON_AFC_48 (2<<5)
145#define S3C2412_UMCON_AFC_40 (3<<5)
146#define S3C2412_UMCON_AFC_32 (4<<5)
147#define S3C2412_UMCON_AFC_24 (5<<5)
148#define S3C2412_UMCON_AFC_16 (6<<5)
149#define S3C2412_UMCON_AFC_8 (7<<5)
150
151#define S3C2410_UFSTAT_TXFULL (1<<9)
152#define S3C2410_UFSTAT_RXFULL (1<<8)
153#define S3C2410_UFSTAT_TXMASK (15<<4)
154#define S3C2410_UFSTAT_TXSHIFT (4)
155#define S3C2410_UFSTAT_RXMASK (15<<0)
156#define S3C2410_UFSTAT_RXSHIFT (0)
157
158/* UFSTAT S3C24A0 */
159#define S3C24A0_UFSTAT_TXFULL (1 << 14)
160#define S3C24A0_UFSTAT_RXFULL (1 << 6)
161#define S3C24A0_UFSTAT_TXMASK (63 << 8)
162#define S3C24A0_UFSTAT_TXSHIFT (8)
163#define S3C24A0_UFSTAT_RXMASK (63)
164#define S3C24A0_UFSTAT_RXSHIFT (0)
165
166/* UFSTAT S3C2443 same as S3C2440 */
167#define S3C2440_UFSTAT_TXFULL (1<<14)
168#define S3C2440_UFSTAT_RXFULL (1<<6)
169#define S3C2440_UFSTAT_TXSHIFT (8)
170#define S3C2440_UFSTAT_RXSHIFT (0)
171#define S3C2440_UFSTAT_TXMASK (63<<8)
172#define S3C2440_UFSTAT_RXMASK (63)
173
174#define S3C2410_UTRSTAT_TXE (1<<2)
175#define S3C2410_UTRSTAT_TXFE (1<<1)
176#define S3C2410_UTRSTAT_RXDR (1<<0)
177
178#define S3C2410_UERSTAT_OVERRUN (1<<0)
179#define S3C2410_UERSTAT_FRAME (1<<2)
180#define S3C2410_UERSTAT_BREAK (1<<3)
181#define S3C2443_UERSTAT_PARITY (1<<1)
182
183#define S3C2410_UERSTAT_ANY (S3C2410_UERSTAT_OVERRUN | \
184 S3C2410_UERSTAT_FRAME | \
185 S3C2410_UERSTAT_BREAK)
186
187#define S3C2410_UMSTAT_CTS (1<<0)
188#define S3C2410_UMSTAT_DeltaCTS (1<<2)
189
190#define S3C2443_DIVSLOT (0x2C)
191
192/* S3C64XX interrupt registers. */
193#define S3C64XX_UINTP 0x30
194#define S3C64XX_UINTSP 0x34
195#define S3C64XX_UINTM 0x38
196
197/* Following are specific to S5PV210 and S5P6442 */
198#define S5PV210_UCON_CLKMASK (1<<10)
199#define S5PV210_UCON_PCLK (0<<10)
200#define S5PV210_UCON_UCLK (1<<10)
201
202#define S5PV210_UFCON_TXTRIG0 (0<<8)
203#define S5PV210_UFCON_TXTRIG4 (1<<8)
204#define S5PV210_UFCON_TXTRIG8 (2<<8)
205#define S5PV210_UFCON_TXTRIG16 (3<<8)
206#define S5PV210_UFCON_TXTRIG32 (4<<8)
207#define S5PV210_UFCON_TXTRIG64 (5<<8)
208#define S5PV210_UFCON_TXTRIG128 (6<<8)
209#define S5PV210_UFCON_TXTRIG256 (7<<8)
210
211#define S5PV210_UFCON_RXTRIG1 (0<<4)
212#define S5PV210_UFCON_RXTRIG4 (1<<4)
213#define S5PV210_UFCON_RXTRIG8 (2<<4)
214#define S5PV210_UFCON_RXTRIG16 (3<<4)
215#define S5PV210_UFCON_RXTRIG32 (4<<4)
216#define S5PV210_UFCON_RXTRIG64 (5<<4)
217#define S5PV210_UFCON_RXTRIG128 (6<<4)
218#define S5PV210_UFCON_RXTRIG256 (7<<4)
219
220#define S5PV210_UFSTAT_TXFULL (1<<24)
221#define S5PV210_UFSTAT_RXFULL (1<<8)
222#define S5PV210_UFSTAT_TXMASK (255<<16)
223#define S5PV210_UFSTAT_TXSHIFT (16)
224#define S5PV210_UFSTAT_RXMASK (255<<0)
225#define S5PV210_UFSTAT_RXSHIFT (0)
226
227#ifndef __ASSEMBLY__
228
229/* struct s3c24xx_uart_clksrc
230 *
231 * this structure defines a named clock source that can be used for the
232 * uart, so that the best clock can be selected for the requested baud
233 * rate.
234 *
235 * min_baud and max_baud define the range of baud-rates this clock is
236 * acceptable for, if they are both zero, it is assumed any baud rate that
237 * can be generated from this clock will be used.
238 *
239 * divisor gives the divisor from the clock to the one seen by the uart
240*/
241
242struct s3c24xx_uart_clksrc {
243 const char *name;
244 unsigned int divisor;
245 unsigned int min_baud;
246 unsigned int max_baud;
247};
248
249/* configuration structure for per-machine configurations for the
250 * serial port
251 *
252 * the pointer is setup by the machine specific initialisation from the
253 * arch/arm/mach-s3c2410/ directory.
254*/
255
256struct s3c2410_uartcfg {
257 unsigned char hwport; /* hardware port number */
258 unsigned char unused;
259 unsigned short flags;
260 upf_t uart_flags; /* default uart flags */
261
262 unsigned long ucon; /* value of ucon for port */
263 unsigned long ulcon; /* value of ulcon for port */
264 unsigned long ufcon; /* value of ufcon for port */
265
266 struct s3c24xx_uart_clksrc *clocks;
267 unsigned int clocks_size;
268};
269
270/* s3c24xx_uart_devs
271 *
272 * this is exported from the core as we cannot use driver_register(),
273 * or platform_add_device() before the console_initcall()
274*/
275
276extern struct platform_device *s3c24xx_uart_devs[4];
277
278#endif /* __ASSEMBLY__ */
279
280#endif /* __ASM_ARM_REGS_SERIAL_H */
281
diff --git a/arch/arm/plat-samsung/include/plat/regs-timer.h b/arch/arm/plat-samsung/include/plat/regs-timer.h
new file mode 100644
index 000000000000..d097d92f8cc7
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-timer.h
@@ -0,0 +1,124 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-timer.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 Timer configuration
11*/
12
13#ifndef __ASM_ARCH_REGS_TIMER_H
14#define __ASM_ARCH_REGS_TIMER_H
15
16#define S3C_TIMERREG(x) (S3C_VA_TIMER + (x))
17#define S3C_TIMERREG2(tmr,reg) S3C_TIMERREG((reg)+0x0c+((tmr)*0x0c))
18
19#define S3C2410_TCFG0 S3C_TIMERREG(0x00)
20#define S3C2410_TCFG1 S3C_TIMERREG(0x04)
21#define S3C2410_TCON S3C_TIMERREG(0x08)
22
23#define S3C64XX_TINT_CSTAT S3C_TIMERREG(0x44)
24
25#define S3C2410_TCFG_PRESCALER0_MASK (255<<0)
26#define S3C2410_TCFG_PRESCALER1_MASK (255<<8)
27#define S3C2410_TCFG_PRESCALER1_SHIFT (8)
28#define S3C2410_TCFG_DEADZONE_MASK (255<<16)
29#define S3C2410_TCFG_DEADZONE_SHIFT (16)
30
31#define S3C2410_TCFG1_MUX4_DIV2 (0<<16)
32#define S3C2410_TCFG1_MUX4_DIV4 (1<<16)
33#define S3C2410_TCFG1_MUX4_DIV8 (2<<16)
34#define S3C2410_TCFG1_MUX4_DIV16 (3<<16)
35#define S3C2410_TCFG1_MUX4_TCLK1 (4<<16)
36#define S3C2410_TCFG1_MUX4_MASK (15<<16)
37#define S3C2410_TCFG1_MUX4_SHIFT (16)
38
39#define S3C2410_TCFG1_MUX3_DIV2 (0<<12)
40#define S3C2410_TCFG1_MUX3_DIV4 (1<<12)
41#define S3C2410_TCFG1_MUX3_DIV8 (2<<12)
42#define S3C2410_TCFG1_MUX3_DIV16 (3<<12)
43#define S3C2410_TCFG1_MUX3_TCLK1 (4<<12)
44#define S3C2410_TCFG1_MUX3_MASK (15<<12)
45
46
47#define S3C2410_TCFG1_MUX2_DIV2 (0<<8)
48#define S3C2410_TCFG1_MUX2_DIV4 (1<<8)
49#define S3C2410_TCFG1_MUX2_DIV8 (2<<8)
50#define S3C2410_TCFG1_MUX2_DIV16 (3<<8)
51#define S3C2410_TCFG1_MUX2_TCLK1 (4<<8)
52#define S3C2410_TCFG1_MUX2_MASK (15<<8)
53
54
55#define S3C2410_TCFG1_MUX1_DIV2 (0<<4)
56#define S3C2410_TCFG1_MUX1_DIV4 (1<<4)
57#define S3C2410_TCFG1_MUX1_DIV8 (2<<4)
58#define S3C2410_TCFG1_MUX1_DIV16 (3<<4)
59#define S3C2410_TCFG1_MUX1_TCLK0 (4<<4)
60#define S3C2410_TCFG1_MUX1_MASK (15<<4)
61
62#define S3C2410_TCFG1_MUX0_DIV2 (0<<0)
63#define S3C2410_TCFG1_MUX0_DIV4 (1<<0)
64#define S3C2410_TCFG1_MUX0_DIV8 (2<<0)
65#define S3C2410_TCFG1_MUX0_DIV16 (3<<0)
66#define S3C2410_TCFG1_MUX0_TCLK0 (4<<0)
67#define S3C2410_TCFG1_MUX0_MASK (15<<0)
68
69#define S3C2410_TCFG1_MUX_DIV2 (0<<0)
70#define S3C2410_TCFG1_MUX_DIV4 (1<<0)
71#define S3C2410_TCFG1_MUX_DIV8 (2<<0)
72#define S3C2410_TCFG1_MUX_DIV16 (3<<0)
73#define S3C2410_TCFG1_MUX_TCLK (4<<0)
74#define S3C2410_TCFG1_MUX_MASK (15<<0)
75
76#define S3C64XX_TCFG1_MUX_DIV1 (0<<0)
77#define S3C64XX_TCFG1_MUX_DIV2 (1<<0)
78#define S3C64XX_TCFG1_MUX_DIV4 (2<<0)
79#define S3C64XX_TCFG1_MUX_DIV8 (3<<0)
80#define S3C64XX_TCFG1_MUX_DIV16 (4<<0)
81#define S3C64XX_TCFG1_MUX_TCLK (5<<0) /* 3 sets of TCLK */
82#define S3C64XX_TCFG1_MUX_MASK (15<<0)
83
84#define S3C2410_TCFG1_SHIFT(x) ((x) * 4)
85
86/* for each timer, we have an count buffer, an compare buffer and
87 * an observation buffer
88*/
89
90/* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */
91
92#define S3C2410_TCNTB(tmr) S3C_TIMERREG2(tmr, 0x00)
93#define S3C2410_TCMPB(tmr) S3C_TIMERREG2(tmr, 0x04)
94#define S3C2410_TCNTO(tmr) S3C_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08))
95
96#define S3C2410_TCON_T4RELOAD (1<<22)
97#define S3C2410_TCON_T4MANUALUPD (1<<21)
98#define S3C2410_TCON_T4START (1<<20)
99
100#define S3C2410_TCON_T3RELOAD (1<<19)
101#define S3C2410_TCON_T3INVERT (1<<18)
102#define S3C2410_TCON_T3MANUALUPD (1<<17)
103#define S3C2410_TCON_T3START (1<<16)
104
105#define S3C2410_TCON_T2RELOAD (1<<15)
106#define S3C2410_TCON_T2INVERT (1<<14)
107#define S3C2410_TCON_T2MANUALUPD (1<<13)
108#define S3C2410_TCON_T2START (1<<12)
109
110#define S3C2410_TCON_T1RELOAD (1<<11)
111#define S3C2410_TCON_T1INVERT (1<<10)
112#define S3C2410_TCON_T1MANUALUPD (1<<9)
113#define S3C2410_TCON_T1START (1<<8)
114
115#define S3C2410_TCON_T0DEADZONE (1<<4)
116#define S3C2410_TCON_T0RELOAD (1<<3)
117#define S3C2410_TCON_T0INVERT (1<<2)
118#define S3C2410_TCON_T0MANUALUPD (1<<1)
119#define S3C2410_TCON_T0START (1<<0)
120
121#endif /* __ASM_ARCH_REGS_TIMER_H */
122
123
124
diff --git a/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h
new file mode 100644
index 000000000000..36a85f5000c8
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h
@@ -0,0 +1,50 @@
1/* arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C - USB2.0 Highspeed/OtG device PHY registers
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/* Note, this is a seperate header file as some of the clock framework
16 * needs to touch this if the clk_48m is used as the USB OHCI or other
17 * peripheral source.
18*/
19
20#ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H
21#define __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H __FILE__
22
23/* S3C64XX_PA_USB_HSPHY */
24
25#define S3C_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY)
26
27#define S3C_PHYPWR S3C_HSOTG_PHYREG(0x00)
28#define SRC_PHYPWR_OTG_DISABLE (1 << 4)
29#define SRC_PHYPWR_ANALOG_POWERDOWN (1 << 3)
30#define SRC_PHYPWR_FORCE_SUSPEND (1 << 1)
31
32#define S3C_PHYCLK S3C_HSOTG_PHYREG(0x04)
33#define S3C_PHYCLK_MODE_USB11 (1 << 6)
34#define S3C_PHYCLK_EXT_OSC (1 << 5)
35#define S3C_PHYCLK_CLK_FORCE (1 << 4)
36#define S3C_PHYCLK_ID_PULL (1 << 2)
37#define S3C_PHYCLK_CLKSEL_MASK (0x3 << 0)
38#define S3C_PHYCLK_CLKSEL_SHIFT (0)
39#define S3C_PHYCLK_CLKSEL_48M (0x0 << 0)
40#define S3C_PHYCLK_CLKSEL_12M (0x2 << 0)
41#define S3C_PHYCLK_CLKSEL_24M (0x3 << 0)
42
43#define S3C_RSTCON S3C_HSOTG_PHYREG(0x08)
44#define S3C_RSTCON_PHYCLK (1 << 2)
45#define S3C_RSTCON_HCLK (1 << 2)
46#define S3C_RSTCON_PHY (1 << 0)
47
48#define S3C_PHYTUNE S3C_HSOTG_PHYREG(0x20)
49
50#endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h
new file mode 100644
index 000000000000..8d18d9d4d148
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h
@@ -0,0 +1,377 @@
1/* arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C - USB2.0 Highspeed/OtG device block registers
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_H
16#define __PLAT_S3C64XX_REGS_USB_HSOTG_H __FILE__
17
18#define S3C_HSOTG_REG(x) (x)
19
20#define S3C_GOTGCTL S3C_HSOTG_REG(0x000)
21#define S3C_GOTGCTL_BSESVLD (1 << 19)
22#define S3C_GOTGCTL_ASESVLD (1 << 18)
23#define S3C_GOTGCTL_DBNC_SHORT (1 << 17)
24#define S3C_GOTGCTL_CONID_B (1 << 16)
25#define S3C_GOTGCTL_DEVHNPEN (1 << 11)
26#define S3C_GOTGCTL_HSSETHNPEN (1 << 10)
27#define S3C_GOTGCTL_HNPREQ (1 << 9)
28#define S3C_GOTGCTL_HSTNEGSCS (1 << 8)
29#define S3C_GOTGCTL_SESREQ (1 << 1)
30#define S3C_GOTGCTL_SESREQSCS (1 << 0)
31
32#define S3C_GOTGINT S3C_HSOTG_REG(0x004)
33#define S3C_GOTGINT_DbnceDone (1 << 19)
34#define S3C_GOTGINT_ADevTOUTChg (1 << 18)
35#define S3C_GOTGINT_HstNegDet (1 << 17)
36#define S3C_GOTGINT_HstnegSucStsChng (1 << 9)
37#define S3C_GOTGINT_SesReqSucStsChng (1 << 8)
38#define S3C_GOTGINT_SesEndDet (1 << 2)
39
40#define S3C_GAHBCFG S3C_HSOTG_REG(0x008)
41#define S3C_GAHBCFG_PTxFEmpLvl (1 << 8)
42#define S3C_GAHBCFG_NPTxFEmpLvl (1 << 7)
43#define S3C_GAHBCFG_DMAEn (1 << 5)
44#define S3C_GAHBCFG_HBstLen_MASK (0xf << 1)
45#define S3C_GAHBCFG_HBstLen_SHIFT (1)
46#define S3C_GAHBCFG_HBstLen_Single (0x0 << 1)
47#define S3C_GAHBCFG_HBstLen_Incr (0x1 << 1)
48#define S3C_GAHBCFG_HBstLen_Incr4 (0x3 << 1)
49#define S3C_GAHBCFG_HBstLen_Incr8 (0x5 << 1)
50#define S3C_GAHBCFG_HBstLen_Incr16 (0x7 << 1)
51#define S3C_GAHBCFG_GlblIntrEn (1 << 0)
52
53#define S3C_GUSBCFG S3C_HSOTG_REG(0x00C)
54#define S3C_GUSBCFG_PHYLPClkSel (1 << 15)
55#define S3C_GUSBCFG_HNPCap (1 << 9)
56#define S3C_GUSBCFG_SRPCap (1 << 8)
57#define S3C_GUSBCFG_PHYIf16 (1 << 3)
58#define S3C_GUSBCFG_TOutCal_MASK (0x7 << 0)
59#define S3C_GUSBCFG_TOutCal_SHIFT (0)
60#define S3C_GUSBCFG_TOutCal_LIMIT (0x7)
61#define S3C_GUSBCFG_TOutCal(_x) ((_x) << 0)
62
63#define S3C_GRSTCTL S3C_HSOTG_REG(0x010)
64
65#define S3C_GRSTCTL_AHBIdle (1 << 31)
66#define S3C_GRSTCTL_DMAReq (1 << 30)
67#define S3C_GRSTCTL_TxFNum_MASK (0x1f << 6)
68#define S3C_GRSTCTL_TxFNum_SHIFT (6)
69#define S3C_GRSTCTL_TxFNum_LIMIT (0x1f)
70#define S3C_GRSTCTL_TxFNum(_x) ((_x) << 6)
71#define S3C_GRSTCTL_TxFFlsh (1 << 5)
72#define S3C_GRSTCTL_RxFFlsh (1 << 4)
73#define S3C_GRSTCTL_INTknQFlsh (1 << 3)
74#define S3C_GRSTCTL_FrmCntrRst (1 << 2)
75#define S3C_GRSTCTL_HSftRst (1 << 1)
76#define S3C_GRSTCTL_CSftRst (1 << 0)
77
78#define S3C_GINTSTS S3C_HSOTG_REG(0x014)
79#define S3C_GINTMSK S3C_HSOTG_REG(0x018)
80
81#define S3C_GINTSTS_WkUpInt (1 << 31)
82#define S3C_GINTSTS_SessReqInt (1 << 30)
83#define S3C_GINTSTS_DisconnInt (1 << 29)
84#define S3C_GINTSTS_ConIDStsChng (1 << 28)
85#define S3C_GINTSTS_PTxFEmp (1 << 26)
86#define S3C_GINTSTS_HChInt (1 << 25)
87#define S3C_GINTSTS_PrtInt (1 << 24)
88#define S3C_GINTSTS_FetSusp (1 << 22)
89#define S3C_GINTSTS_incompIP (1 << 21)
90#define S3C_GINTSTS_IncomplSOIN (1 << 20)
91#define S3C_GINTSTS_OEPInt (1 << 19)
92#define S3C_GINTSTS_IEPInt (1 << 18)
93#define S3C_GINTSTS_EPMis (1 << 17)
94#define S3C_GINTSTS_EOPF (1 << 15)
95#define S3C_GINTSTS_ISOutDrop (1 << 14)
96#define S3C_GINTSTS_EnumDone (1 << 13)
97#define S3C_GINTSTS_USBRst (1 << 12)
98#define S3C_GINTSTS_USBSusp (1 << 11)
99#define S3C_GINTSTS_ErlySusp (1 << 10)
100#define S3C_GINTSTS_GOUTNakEff (1 << 7)
101#define S3C_GINTSTS_GINNakEff (1 << 6)
102#define S3C_GINTSTS_NPTxFEmp (1 << 5)
103#define S3C_GINTSTS_RxFLvl (1 << 4)
104#define S3C_GINTSTS_SOF (1 << 3)
105#define S3C_GINTSTS_OTGInt (1 << 2)
106#define S3C_GINTSTS_ModeMis (1 << 1)
107#define S3C_GINTSTS_CurMod_Host (1 << 0)
108
109#define S3C_GRXSTSR S3C_HSOTG_REG(0x01C)
110#define S3C_GRXSTSP S3C_HSOTG_REG(0x020)
111
112#define S3C_GRXSTS_FN_MASK (0x7f << 25)
113#define S3C_GRXSTS_FN_SHIFT (25)
114
115#define S3C_GRXSTS_PktSts_MASK (0xf << 17)
116#define S3C_GRXSTS_PktSts_SHIFT (17)
117#define S3C_GRXSTS_PktSts_GlobalOutNAK (0x1 << 17)
118#define S3C_GRXSTS_PktSts_OutRX (0x2 << 17)
119#define S3C_GRXSTS_PktSts_OutDone (0x3 << 17)
120#define S3C_GRXSTS_PktSts_SetupDone (0x4 << 17)
121#define S3C_GRXSTS_PktSts_SetupRX (0x6 << 17)
122
123#define S3C_GRXSTS_DPID_MASK (0x3 << 15)
124#define S3C_GRXSTS_DPID_SHIFT (15)
125#define S3C_GRXSTS_ByteCnt_MASK (0x7ff << 4)
126#define S3C_GRXSTS_ByteCnt_SHIFT (4)
127#define S3C_GRXSTS_EPNum_MASK (0xf << 0)
128#define S3C_GRXSTS_EPNum_SHIFT (0)
129
130#define S3C_GRXFSIZ S3C_HSOTG_REG(0x024)
131
132#define S3C_GNPTXFSIZ S3C_HSOTG_REG(0x028)
133
134#define S3C_GNPTXFSIZ_NPTxFDep_MASK (0xffff << 16)
135#define S3C_GNPTXFSIZ_NPTxFDep_SHIFT (16)
136#define S3C_GNPTXFSIZ_NPTxFDep_LIMIT (0xffff)
137#define S3C_GNPTXFSIZ_NPTxFDep(_x) ((_x) << 16)
138#define S3C_GNPTXFSIZ_NPTxFStAddr_MASK (0xffff << 0)
139#define S3C_GNPTXFSIZ_NPTxFStAddr_SHIFT (0)
140#define S3C_GNPTXFSIZ_NPTxFStAddr_LIMIT (0xffff)
141#define S3C_GNPTXFSIZ_NPTxFStAddr(_x) ((_x) << 0)
142
143#define S3C_GNPTXSTS S3C_HSOTG_REG(0x02C)
144
145#define S3C_GNPTXSTS_NPtxQTop_MASK (0x7f << 24)
146#define S3C_GNPTXSTS_NPtxQTop_SHIFT (24)
147
148#define S3C_GNPTXSTS_NPTxQSpcAvail_MASK (0xff << 16)
149#define S3C_GNPTXSTS_NPTxQSpcAvail_SHIFT (16)
150#define S3C_GNPTXSTS_NPTxQSpcAvail_GET(_v) (((_v) >> 16) & 0xff)
151
152#define S3C_GNPTXSTS_NPTxFSpcAvail_MASK (0xffff << 0)
153#define S3C_GNPTXSTS_NPTxFSpcAvail_SHIFT (0)
154#define S3C_GNPTXSTS_NPTxFSpcAvail_GET(_v) (((_v) >> 0) & 0xffff)
155
156
157#define S3C_HPTXFSIZ S3C_HSOTG_REG(0x100)
158
159#define S3C_DPTXFSIZn(_a) S3C_HSOTG_REG(0x104 + (((_a) - 1) * 4))
160
161#define S3C_DPTXFSIZn_DPTxFSize_MASK (0xffff << 16)
162#define S3C_DPTXFSIZn_DPTxFSize_SHIFT (16)
163#define S3C_DPTXFSIZn_DPTxFSize_GET(_v) (((_v) >> 16) & 0xffff)
164#define S3C_DPTXFSIZn_DPTxFSize_LIMIT (0xffff)
165#define S3C_DPTXFSIZn_DPTxFSize(_x) ((_x) << 16)
166
167#define S3C_DPTXFSIZn_DPTxFStAddr_MASK (0xffff << 0)
168#define S3C_DPTXFSIZn_DPTxFStAddr_SHIFT (0)
169
170/* Device mode registers */
171#define S3C_DCFG S3C_HSOTG_REG(0x800)
172
173#define S3C_DCFG_EPMisCnt_MASK (0x1f << 18)
174#define S3C_DCFG_EPMisCnt_SHIFT (18)
175#define S3C_DCFG_EPMisCnt_LIMIT (0x1f)
176#define S3C_DCFG_EPMisCnt(_x) ((_x) << 18)
177
178#define S3C_DCFG_PerFrInt_MASK (0x3 << 11)
179#define S3C_DCFG_PerFrInt_SHIFT (11)
180#define S3C_DCFG_PerFrInt_LIMIT (0x3)
181#define S3C_DCFG_PerFrInt(_x) ((_x) << 11)
182
183#define S3C_DCFG_DevAddr_MASK (0x7f << 4)
184#define S3C_DCFG_DevAddr_SHIFT (4)
185#define S3C_DCFG_DevAddr_LIMIT (0x7f)
186#define S3C_DCFG_DevAddr(_x) ((_x) << 4)
187
188#define S3C_DCFG_NZStsOUTHShk (1 << 2)
189
190#define S3C_DCFG_DevSpd_MASK (0x3 << 0)
191#define S3C_DCFG_DevSpd_SHIFT (0)
192#define S3C_DCFG_DevSpd_HS (0x0 << 0)
193#define S3C_DCFG_DevSpd_FS (0x1 << 0)
194#define S3C_DCFG_DevSpd_LS (0x2 << 0)
195#define S3C_DCFG_DevSpd_FS48 (0x3 << 0)
196
197#define S3C_DCTL S3C_HSOTG_REG(0x804)
198
199#define S3C_DCTL_PWROnPrgDone (1 << 11)
200#define S3C_DCTL_CGOUTNak (1 << 10)
201#define S3C_DCTL_SGOUTNak (1 << 9)
202#define S3C_DCTL_CGNPInNAK (1 << 8)
203#define S3C_DCTL_SGNPInNAK (1 << 7)
204#define S3C_DCTL_TstCtl_MASK (0x7 << 4)
205#define S3C_DCTL_TstCtl_SHIFT (4)
206#define S3C_DCTL_GOUTNakSts (1 << 3)
207#define S3C_DCTL_GNPINNakSts (1 << 2)
208#define S3C_DCTL_SftDiscon (1 << 1)
209#define S3C_DCTL_RmtWkUpSig (1 << 0)
210
211#define S3C_DSTS S3C_HSOTG_REG(0x808)
212
213#define S3C_DSTS_SOFFN_MASK (0x3fff << 8)
214#define S3C_DSTS_SOFFN_SHIFT (8)
215#define S3C_DSTS_SOFFN_LIMIT (0x3fff)
216#define S3C_DSTS_SOFFN(_x) ((_x) << 8)
217#define S3C_DSTS_ErraticErr (1 << 3)
218#define S3C_DSTS_EnumSpd_MASK (0x3 << 1)
219#define S3C_DSTS_EnumSpd_SHIFT (1)
220#define S3C_DSTS_EnumSpd_HS (0x0 << 1)
221#define S3C_DSTS_EnumSpd_FS (0x1 << 1)
222#define S3C_DSTS_EnumSpd_LS (0x2 << 1)
223#define S3C_DSTS_EnumSpd_FS48 (0x3 << 1)
224
225#define S3C_DSTS_SuspSts (1 << 0)
226
227#define S3C_DIEPMSK S3C_HSOTG_REG(0x810)
228
229#define S3C_DIEPMSK_INEPNakEffMsk (1 << 6)
230#define S3C_DIEPMSK_INTknEPMisMsk (1 << 5)
231#define S3C_DIEPMSK_INTknTXFEmpMsk (1 << 4)
232#define S3C_DIEPMSK_TimeOUTMsk (1 << 3)
233#define S3C_DIEPMSK_AHBErrMsk (1 << 2)
234#define S3C_DIEPMSK_EPDisbldMsk (1 << 1)
235#define S3C_DIEPMSK_XferComplMsk (1 << 0)
236
237#define S3C_DOEPMSK S3C_HSOTG_REG(0x814)
238
239#define S3C_DOEPMSK_Back2BackSetup (1 << 6)
240#define S3C_DOEPMSK_OUTTknEPdisMsk (1 << 4)
241#define S3C_DOEPMSK_SetupMsk (1 << 3)
242#define S3C_DOEPMSK_AHBErrMsk (1 << 2)
243#define S3C_DOEPMSK_EPDisbldMsk (1 << 1)
244#define S3C_DOEPMSK_XferComplMsk (1 << 0)
245
246#define S3C_DAINT S3C_HSOTG_REG(0x818)
247#define S3C_DAINTMSK S3C_HSOTG_REG(0x81C)
248
249#define S3C_DAINT_OutEP_SHIFT (16)
250#define S3C_DAINT_OutEP(x) (1 << ((x) + 16))
251#define S3C_DAINT_InEP(x) (1 << (x))
252
253#define S3C_DTKNQR1 S3C_HSOTG_REG(0x820)
254#define S3C_DTKNQR2 S3C_HSOTG_REG(0x824)
255#define S3C_DTKNQR3 S3C_HSOTG_REG(0x830)
256#define S3C_DTKNQR4 S3C_HSOTG_REG(0x834)
257
258#define S3C_DVBUSDIS S3C_HSOTG_REG(0x828)
259#define S3C_DVBUSPULSE S3C_HSOTG_REG(0x82C)
260
261#define S3C_DIEPCTL0 S3C_HSOTG_REG(0x900)
262#define S3C_DOEPCTL0 S3C_HSOTG_REG(0xB00)
263#define S3C_DIEPCTL(_a) S3C_HSOTG_REG(0x900 + ((_a) * 0x20))
264#define S3C_DOEPCTL(_a) S3C_HSOTG_REG(0xB00 + ((_a) * 0x20))
265
266/* EP0 specialness:
267 * bits[29..28] - reserved (no SetD0PID, SetD1PID)
268 * bits[25..22] - should always be zero, this isn't a periodic endpoint
269 * bits[10..0] - MPS setting differenct for EP0
270*/
271#define S3C_D0EPCTL_MPS_MASK (0x3 << 0)
272#define S3C_D0EPCTL_MPS_SHIFT (0)
273#define S3C_D0EPCTL_MPS_64 (0x0 << 0)
274#define S3C_D0EPCTL_MPS_32 (0x1 << 0)
275#define S3C_D0EPCTL_MPS_16 (0x2 << 0)
276#define S3C_D0EPCTL_MPS_8 (0x3 << 0)
277
278#define S3C_DxEPCTL_EPEna (1 << 31)
279#define S3C_DxEPCTL_EPDis (1 << 30)
280#define S3C_DxEPCTL_SetD1PID (1 << 29)
281#define S3C_DxEPCTL_SetOddFr (1 << 29)
282#define S3C_DxEPCTL_SetD0PID (1 << 28)
283#define S3C_DxEPCTL_SetEvenFr (1 << 28)
284#define S3C_DxEPCTL_SNAK (1 << 27)
285#define S3C_DxEPCTL_CNAK (1 << 26)
286#define S3C_DxEPCTL_TxFNum_MASK (0xf << 22)
287#define S3C_DxEPCTL_TxFNum_SHIFT (22)
288#define S3C_DxEPCTL_TxFNum_LIMIT (0xf)
289#define S3C_DxEPCTL_TxFNum(_x) ((_x) << 22)
290
291#define S3C_DxEPCTL_Stall (1 << 21)
292#define S3C_DxEPCTL_Snp (1 << 20)
293#define S3C_DxEPCTL_EPType_MASK (0x3 << 18)
294#define S3C_DxEPCTL_EPType_SHIFT (18)
295#define S3C_DxEPCTL_EPType_Control (0x0 << 18)
296#define S3C_DxEPCTL_EPType_Iso (0x1 << 18)
297#define S3C_DxEPCTL_EPType_Bulk (0x2 << 18)
298#define S3C_DxEPCTL_EPType_Intterupt (0x3 << 18)
299
300#define S3C_DxEPCTL_NAKsts (1 << 17)
301#define S3C_DxEPCTL_DPID (1 << 16)
302#define S3C_DxEPCTL_EOFrNum (1 << 16)
303#define S3C_DxEPCTL_USBActEp (1 << 15)
304#define S3C_DxEPCTL_NextEp_MASK (0xf << 11)
305#define S3C_DxEPCTL_NextEp_SHIFT (11)
306#define S3C_DxEPCTL_NextEp_LIMIT (0xf)
307#define S3C_DxEPCTL_NextEp(_x) ((_x) << 11)
308
309#define S3C_DxEPCTL_MPS_MASK (0x7ff << 0)
310#define S3C_DxEPCTL_MPS_SHIFT (0)
311#define S3C_DxEPCTL_MPS_LIMIT (0x7ff)
312#define S3C_DxEPCTL_MPS(_x) ((_x) << 0)
313
314#define S3C_DIEPINT(_a) S3C_HSOTG_REG(0x908 + ((_a) * 0x20))
315#define S3C_DOEPINT(_a) S3C_HSOTG_REG(0xB08 + ((_a) * 0x20))
316
317#define S3C_DxEPINT_INEPNakEff (1 << 6)
318#define S3C_DxEPINT_Back2BackSetup (1 << 6)
319#define S3C_DxEPINT_INTknEPMis (1 << 5)
320#define S3C_DxEPINT_INTknTXFEmp (1 << 4)
321#define S3C_DxEPINT_OUTTknEPdis (1 << 4)
322#define S3C_DxEPINT_Timeout (1 << 3)
323#define S3C_DxEPINT_Setup (1 << 3)
324#define S3C_DxEPINT_AHBErr (1 << 2)
325#define S3C_DxEPINT_EPDisbld (1 << 1)
326#define S3C_DxEPINT_XferCompl (1 << 0)
327
328#define S3C_DIEPTSIZ0 S3C_HSOTG_REG(0x910)
329
330#define S3C_DIEPTSIZ0_PktCnt_MASK (0x3 << 19)
331#define S3C_DIEPTSIZ0_PktCnt_SHIFT (19)
332#define S3C_DIEPTSIZ0_PktCnt_LIMIT (0x3)
333#define S3C_DIEPTSIZ0_PktCnt(_x) ((_x) << 19)
334
335#define S3C_DIEPTSIZ0_XferSize_MASK (0x7f << 0)
336#define S3C_DIEPTSIZ0_XferSize_SHIFT (0)
337#define S3C_DIEPTSIZ0_XferSize_LIMIT (0x7f)
338#define S3C_DIEPTSIZ0_XferSize(_x) ((_x) << 0)
339
340
341#define DOEPTSIZ0 S3C_HSOTG_REG(0xB10)
342#define S3C_DOEPTSIZ0_SUPCnt_MASK (0x3 << 29)
343#define S3C_DOEPTSIZ0_SUPCnt_SHIFT (29)
344#define S3C_DOEPTSIZ0_SUPCnt_LIMIT (0x3)
345#define S3C_DOEPTSIZ0_SUPCnt(_x) ((_x) << 29)
346
347#define S3C_DOEPTSIZ0_PktCnt (1 << 19)
348#define S3C_DOEPTSIZ0_XferSize_MASK (0x7f << 0)
349#define S3C_DOEPTSIZ0_XferSize_SHIFT (0)
350
351#define S3C_DIEPTSIZ(_a) S3C_HSOTG_REG(0x910 + ((_a) * 0x20))
352#define S3C_DOEPTSIZ(_a) S3C_HSOTG_REG(0xB10 + ((_a) * 0x20))
353
354#define S3C_DxEPTSIZ_MC_MASK (0x3 << 29)
355#define S3C_DxEPTSIZ_MC_SHIFT (29)
356#define S3C_DxEPTSIZ_MC_LIMIT (0x3)
357#define S3C_DxEPTSIZ_MC(_x) ((_x) << 29)
358
359#define S3C_DxEPTSIZ_PktCnt_MASK (0x3ff << 19)
360#define S3C_DxEPTSIZ_PktCnt_SHIFT (19)
361#define S3C_DxEPTSIZ_PktCnt_GET(_v) (((_v) >> 19) & 0x3ff)
362#define S3C_DxEPTSIZ_PktCnt_LIMIT (0x3ff)
363#define S3C_DxEPTSIZ_PktCnt(_x) ((_x) << 19)
364
365#define S3C_DxEPTSIZ_XferSize_MASK (0x7ffff << 0)
366#define S3C_DxEPTSIZ_XferSize_SHIFT (0)
367#define S3C_DxEPTSIZ_XferSize_GET(_v) (((_v) >> 0) & 0x7ffff)
368#define S3C_DxEPTSIZ_XferSize_LIMIT (0x7ffff)
369#define S3C_DxEPTSIZ_XferSize(_x) ((_x) << 0)
370
371
372#define S3C_DIEPDMA(_a) S3C_HSOTG_REG(0x914 + ((_a) * 0x20))
373#define S3C_DOEPDMA(_a) S3C_HSOTG_REG(0xB14 + ((_a) * 0x20))
374
375#define S3C_EPFIFO(_a) S3C_HSOTG_REG(0x1000 + ((_a) * 0x1000))
376
377#endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-watchdog.h b/arch/arm/plat-samsung/include/plat/regs-watchdog.h
new file mode 100644
index 000000000000..4938492470f7
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-watchdog.h
@@ -0,0 +1,41 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-watchdog.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 Watchdog timer control
11*/
12
13
14#ifndef __ASM_ARCH_REGS_WATCHDOG_H
15#define __ASM_ARCH_REGS_WATCHDOG_H
16
17#define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG)
18
19#define S3C2410_WTCON S3C_WDOGREG(0x00)
20#define S3C2410_WTDAT S3C_WDOGREG(0x04)
21#define S3C2410_WTCNT S3C_WDOGREG(0x08)
22
23/* the watchdog can either generate a reset pulse, or an
24 * interrupt.
25 */
26
27#define S3C2410_WTCON_RSTEN (0x01)
28#define S3C2410_WTCON_INTEN (1<<2)
29#define S3C2410_WTCON_ENABLE (1<<5)
30
31#define S3C2410_WTCON_DIV16 (0<<3)
32#define S3C2410_WTCON_DIV32 (1<<3)
33#define S3C2410_WTCON_DIV64 (2<<3)
34#define S3C2410_WTCON_DIV128 (3<<3)
35
36#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
37#define S3C2410_WTCON_PRESCALE_MASK (0xff00)
38
39#endif /* __ASM_ARCH_REGS_WATCHDOG_H */
40
41
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
new file mode 100644
index 000000000000..d17724149315
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -0,0 +1,67 @@
1/* linux/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
2 *
3 * Copyright (C) 2009 Samsung Electronics Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __S3C64XX_PLAT_SPI_H
12#define __S3C64XX_PLAT_SPI_H
13
14/**
15 * struct s3c64xx_spi_csinfo - ChipSelect description
16 * @fb_delay: Slave specific feedback delay.
17 * Refer to FB_CLK_SEL register definition in SPI chapter.
18 * @line: Custom 'identity' of the CS line.
19 * @set_level: CS line control.
20 *
21 * This is per SPI-Slave Chipselect information.
22 * Allocate and initialize one in machine init code and make the
23 * spi_board_info.controller_data point to it.
24 */
25struct s3c64xx_spi_csinfo {
26 u8 fb_delay;
27 unsigned line;
28 void (*set_level)(unsigned line_id, int lvl);
29};
30
31/**
32 * struct s3c64xx_spi_info - SPI Controller defining structure
33 * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
34 * @src_clk_name: Platform name of the corresponding clock.
35 * @num_cs: Number of CS this controller emulates.
36 * @cfg_gpio: Configure pins for this SPI controller.
37 * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6
38 * @rx_lvl_offset: Depends on tx fifo_lvl field and bus number
39 * @high_speed: If the controller supports HIGH_SPEED_EN bit
40 */
41struct s3c64xx_spi_info {
42 int src_clk_nr;
43 char *src_clk_name;
44
45 int num_cs;
46
47 int (*cfg_gpio)(struct platform_device *pdev);
48
49 /* Following two fields are for future compatibility */
50 int fifo_lvl_mask;
51 int rx_lvl_offset;
52 int high_speed;
53};
54
55/**
56 * s3c64xx_spi_set_info - SPI Controller configure callback by the board
57 * initialization code.
58 * @cntrlr: SPI controller number the configuration is for.
59 * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks.
60 * @num_cs: Number of elements in the 'cs' array.
61 *
62 * Call this from machine init code for each SPI Controller that
63 * has some chips attached to it.
64 */
65extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
66
67#endif /* __S3C64XX_PLAT_SPI_H */
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
new file mode 100644
index 000000000000..7d07cd7aa4f2
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -0,0 +1,221 @@
1/* linux/arch/arm/plat-s3c/include/plat/sdhci.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C Platform - SDHCI (HSMMC) platform data definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __PLAT_S3C_SDHCI_H
16#define __PLAT_S3C_SDHCI_H __FILE__
17
18struct platform_device;
19struct mmc_host;
20struct mmc_card;
21struct mmc_ios;
22
23/**
24 * struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI
25 * @max_width: The maximum number of data bits supported.
26 * @host_caps: Standard MMC host capabilities bit field.
27 * @cfg_gpio: Configure the GPIO for a specific card bit-width
28 * @cfg_card: Configure the interface for a specific card and speed. This
29 * is necessary the controllers and/or GPIO blocks require the
30 * changing of driver-strength and other controls dependant on
31 * the card and speed of operation.
32 *
33 * Initialisation data specific to either the machine or the platform
34 * for the device driver to use or call-back when configuring gpio or
35 * card speed information.
36*/
37struct s3c_sdhci_platdata {
38 unsigned int max_width;
39 unsigned int host_caps;
40
41 char **clocks; /* set of clock sources */
42
43 void (*cfg_gpio)(struct platform_device *dev, int width);
44 void (*cfg_card)(struct platform_device *dev,
45 void __iomem *regbase,
46 struct mmc_ios *ios,
47 struct mmc_card *card);
48};
49
50/**
51 * s3c_sdhci0_set_platdata - Set platform data for S3C SDHCI device.
52 * @pd: Platform data to register to device.
53 *
54 * Register the given platform data for use withe S3C SDHCI device.
55 * The call will copy the platform data, so the board definitions can
56 * make the structure itself __initdata.
57 */
58extern void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd);
59extern void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd);
60extern void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd);
61
62/* Default platform data, exported so that per-cpu initialisation can
63 * set the correct one when there are more than one cpu type selected.
64*/
65
66extern struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata;
67extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata;
68extern struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata;
69
70/* Helper function availablity */
71
72extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
73extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
74extern void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
75extern void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
76extern void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
77extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
78
79/* S3C6400 SDHCI setup */
80
81#ifdef CONFIG_S3C64XX_SETUP_SDHCI
82extern char *s3c64xx_hsmmc_clksrcs[4];
83
84#ifdef CONFIG_S3C_DEV_HSMMC
85extern void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,
86 void __iomem *r,
87 struct mmc_ios *ios,
88 struct mmc_card *card);
89
90static inline void s3c6400_default_sdhci0(void)
91{
92 s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
93 s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
94 s3c_hsmmc0_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
95}
96
97#else
98static inline void s3c6400_default_sdhci0(void) { }
99#endif /* CONFIG_S3C_DEV_HSMMC */
100
101#ifdef CONFIG_S3C_DEV_HSMMC1
102static inline void s3c6400_default_sdhci1(void)
103{
104 s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
105 s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
106 s3c_hsmmc1_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
107}
108#else
109static inline void s3c6400_default_sdhci1(void) { }
110#endif /* CONFIG_S3C_DEV_HSMMC1 */
111
112#ifdef CONFIG_S3C_DEV_HSMMC2
113static inline void s3c6400_default_sdhci2(void)
114{
115 s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
116 s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
117 s3c_hsmmc2_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
118}
119#else
120static inline void s3c6400_default_sdhci2(void) { }
121#endif /* CONFIG_S3C_DEV_HSMMC2 */
122
123/* S3C6410 SDHCI setup */
124
125extern void s3c6410_setup_sdhci_cfg_card(struct platform_device *dev,
126 void __iomem *r,
127 struct mmc_ios *ios,
128 struct mmc_card *card);
129
130#ifdef CONFIG_S3C_DEV_HSMMC
131static inline void s3c6410_default_sdhci0(void)
132{
133 s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
134 s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
135 s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card;
136}
137#else
138static inline void s3c6410_default_sdhci0(void) { }
139#endif /* CONFIG_S3C_DEV_HSMMC */
140
141#ifdef CONFIG_S3C_DEV_HSMMC1
142static inline void s3c6410_default_sdhci1(void)
143{
144 s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
145 s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
146 s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card;
147}
148#else
149static inline void s3c6410_default_sdhci1(void) { }
150#endif /* CONFIG_S3C_DEV_HSMMC1 */
151
152#ifdef CONFIG_S3C_DEV_HSMMC2
153static inline void s3c6410_default_sdhci2(void)
154{
155 s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
156 s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
157 s3c_hsmmc2_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card;
158}
159#else
160static inline void s3c6410_default_sdhci2(void) { }
161#endif /* CONFIG_S3C_DEV_HSMMC2 */
162
163#else
164static inline void s3c6410_default_sdhci0(void) { }
165static inline void s3c6410_default_sdhci1(void) { }
166static inline void s3c6400_default_sdhci0(void) { }
167static inline void s3c6400_default_sdhci1(void) { }
168
169#endif /* CONFIG_S3C64XX_SETUP_SDHCI */
170
171/* S5PC100 SDHCI setup */
172
173#ifdef CONFIG_S5PC100_SETUP_SDHCI
174extern char *s5pc100_hsmmc_clksrcs[4];
175
176extern void s5pc100_setup_sdhci0_cfg_card(struct platform_device *dev,
177 void __iomem *r,
178 struct mmc_ios *ios,
179 struct mmc_card *card);
180
181#ifdef CONFIG_S3C_DEV_HSMMC
182static inline void s5pc100_default_sdhci0(void)
183{
184 s3c_hsmmc0_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
185 s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio;
186 s3c_hsmmc0_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card;
187}
188#else
189static inline void s5pc100_default_sdhci0(void) { }
190#endif /* CONFIG_S3C_DEV_HSMMC */
191
192#ifdef CONFIG_S3C_DEV_HSMMC1
193static inline void s5pc100_default_sdhci1(void)
194{
195 s3c_hsmmc1_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
196 s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio;
197 s3c_hsmmc1_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card;
198}
199#else
200static inline void s5pc100_default_sdhci1(void) { }
201#endif /* CONFIG_S3C_DEV_HSMMC1 */
202
203#ifdef CONFIG_S3C_DEV_HSMMC2
204static inline void s5pc100_default_sdhci2(void)
205{
206 s3c_hsmmc2_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
207 s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio;
208 s3c_hsmmc2_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card;
209}
210#else
211static inline void s5pc100_default_sdhci2(void) { }
212#endif /* CONFIG_S3C_DEV_HSMMC1 */
213
214
215#else
216static inline void s5pc100_default_sdhci0(void) { }
217static inline void s5pc100_default_sdhci1(void) { }
218static inline void s5pc100_default_sdhci2(void) { }
219#endif /* CONFIG_S5PC100_SETUP_SDHCI */
220
221#endif /* __PLAT_S3C_SDHCI_H */
diff --git a/arch/arm/plat-samsung/include/plat/udc-hs.h b/arch/arm/plat-samsung/include/plat/udc-hs.h
new file mode 100644
index 000000000000..a22a4f2eea94
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/udc-hs.h
@@ -0,0 +1,29 @@
1/* arch/arm/plat-s3c/include/plat/udc-hs.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C USB2.0 High-speed / OtG platform information
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15enum s3c_hsotg_dmamode {
16 S3C_HSOTG_DMA_NONE, /* do not use DMA at-all */
17 S3C_HSOTG_DMA_ONLY, /* always use DMA */
18 S3C_HSOTG_DMA_DRV, /* DMA is chosen by driver */
19};
20
21/**
22 * struct s3c_hsotg_plat - platform data for high-speed otg/udc
23 * @dma: Whether to use DMA or not.
24 * @is_osc: The clock source is an oscillator, not a crystal
25 */
26struct s3c_hsotg_plat {
27 enum s3c_hsotg_dmamode dma;
28 unsigned int is_osc : 1;
29};
diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h
new file mode 100644
index 000000000000..e87ce8ffbbcd
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/uncompress.h
@@ -0,0 +1,186 @@
1/* arch/arm/plat-samsung/include/plat/uncompress.h
2 *
3 * Copyright 2003, 2007 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C - uncompress code
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_PLAT_UNCOMPRESS_H
15#define __ASM_PLAT_UNCOMPRESS_H
16
17typedef unsigned int upf_t; /* cannot include linux/serial_core.h */
18
19/* uart setup */
20
21static unsigned int fifo_mask;
22static unsigned int fifo_max;
23
24/* forward declerations */
25
26static void arch_detect_cpu(void);
27
28/* defines for UART registers */
29
30#include <plat/regs-serial.h>
31#include <plat/regs-watchdog.h>
32
33/* working in physical space... */
34#undef S3C2410_WDOGREG
35#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
36
37/* how many bytes we allow into the FIFO at a time in FIFO mode */
38#define FIFO_MAX (14)
39
40#define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT)
41
42static __inline__ void
43uart_wr(unsigned int reg, unsigned int val)
44{
45 volatile unsigned int *ptr;
46
47 ptr = (volatile unsigned int *)(reg + uart_base);
48 *ptr = val;
49}
50
51static __inline__ unsigned int
52uart_rd(unsigned int reg)
53{
54 volatile unsigned int *ptr;
55
56 ptr = (volatile unsigned int *)(reg + uart_base);
57 return *ptr;
58}
59
60/* we can deal with the case the UARTs are being run
61 * in FIFO mode, so that we don't hold up our execution
62 * waiting for tx to happen...
63*/
64
65static void putc(int ch)
66{
67 if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
68 int level;
69
70 while (1) {
71 level = uart_rd(S3C2410_UFSTAT);
72 level &= fifo_mask;
73
74 if (level < fifo_max)
75 break;
76 }
77
78 } else {
79 /* not using fifos */
80
81 while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
82 barrier();
83 }
84
85 /* write byte to transmission register */
86 uart_wr(S3C2410_UTXH, ch);
87}
88
89static inline void flush(void)
90{
91}
92
93#define __raw_writel(d, ad) \
94 do { \
95 *((volatile unsigned int __force *)(ad)) = (d); \
96 } while (0)
97
98/* CONFIG_S3C_BOOT_WATCHDOG
99 *
100 * Simple boot-time watchdog setup, to reboot the system if there is
101 * any problem with the boot process
102*/
103
104#ifdef CONFIG_S3C_BOOT_WATCHDOG
105
106#define WDOG_COUNT (0xff00)
107
108static inline void arch_decomp_wdog(void)
109{
110 __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
111}
112
113static void arch_decomp_wdog_start(void)
114{
115 __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
116 __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
117 __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
118}
119
120#else
121#define arch_decomp_wdog_start()
122#define arch_decomp_wdog()
123#endif
124
125#ifdef CONFIG_S3C_BOOT_ERROR_RESET
126
127static void arch_decomp_error(const char *x)
128{
129 putstr("\n\n");
130 putstr(x);
131 putstr("\n\n -- System resetting\n");
132
133 __raw_writel(0x4000, S3C2410_WTDAT);
134 __raw_writel(0x4000, S3C2410_WTCNT);
135 __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
136
137 while(1);
138}
139
140#define arch_error arch_decomp_error
141#endif
142
143static void error(char *err);
144
145#ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO
146static inline void arch_enable_uart_fifo(void)
147{
148 u32 fifocon = uart_rd(S3C2410_UFCON);
149
150 if (!(fifocon & S3C2410_UFCON_FIFOMODE)) {
151 fifocon |= S3C2410_UFCON_RESETBOTH;
152 uart_wr(S3C2410_UFCON, fifocon);
153
154 /* wait for fifo reset to complete */
155 while (1) {
156 fifocon = uart_rd(S3C2410_UFCON);
157 if (!(fifocon & S3C2410_UFCON_RESETBOTH))
158 break;
159 }
160 }
161}
162#else
163#define arch_enable_uart_fifo() do { } while(0)
164#endif
165
166
167static void
168arch_decomp_setup(void)
169{
170 /* we may need to setup the uart(s) here if we are not running
171 * on an BAST... the BAST will have left the uarts configured
172 * after calling linux.
173 */
174
175 arch_detect_cpu();
176 arch_decomp_wdog_start();
177
178 /* Enable the UART FIFOs if they where not enabled and our
179 * configuration says we should turn them on.
180 */
181
182 arch_enable_uart_fifo();
183}
184
185
186#endif /* __ASM_PLAT_UNCOMPRESS_H */
diff --git a/arch/arm/plat-samsung/include/plat/usb-control.h b/arch/arm/plat-samsung/include/plat/usb-control.h
new file mode 100644
index 000000000000..7fa1fbefc3f2
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/usb-control.h
@@ -0,0 +1,43 @@
1/* arch/arm/plat-samsung/include/plat/usb-control.h
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C - USB host port information
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_USBCONTROL_H
14#define __ASM_ARCH_USBCONTROL_H
15
16#define S3C_HCDFLG_USED (1)
17
18struct s3c2410_hcd_port {
19 unsigned char flags;
20 unsigned char power;
21 unsigned char oc_status;
22 unsigned char oc_changed;
23};
24
25struct s3c2410_hcd_info {
26 struct usb_hcd *hcd;
27 struct s3c2410_hcd_port port[2];
28
29 void (*power_control)(int port, int to);
30 void (*enable_oc)(struct s3c2410_hcd_info *, int on);
31 void (*report_oc)(struct s3c2410_hcd_info *, int ports);
32};
33
34static void inline s3c2410_usb_report_oc(struct s3c2410_hcd_info *info, int ports)
35{
36 if (info->report_oc != NULL) {
37 (info->report_oc)(info, ports);
38 }
39}
40
41extern void s3c_ohci_set_platdata(struct s3c2410_hcd_info *info);
42
43#endif /*__ASM_ARCH_USBCONTROL_H */
diff --git a/arch/arm/plat-samsung/include/plat/watchdog-reset.h b/arch/arm/plat-samsung/include/plat/watchdog-reset.h
new file mode 100644
index 000000000000..54b762acb5a0
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/watchdog-reset.h
@@ -0,0 +1,49 @@
1/* arch/arm/plat-s3c/include/plat/watchdog-reset.h
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - System define for arch_reset() function
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <plat/regs-watchdog.h>
14#include <mach/map.h>
15
16#include <linux/clk.h>
17#include <linux/err.h>
18#include <linux/io.h>
19
20static inline void arch_wdt_reset(void)
21{
22 struct clk *wdtclk;
23
24 printk("arch_reset: attempting watchdog reset\n");
25
26 __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */
27
28 wdtclk = clk_get(NULL, "watchdog");
29 if (!IS_ERR(wdtclk)) {
30 clk_enable(wdtclk);
31 } else
32 printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
33
34 /* put initial values into count and data */
35 __raw_writel(0x80, S3C2410_WTCNT);
36 __raw_writel(0x80, S3C2410_WTDAT);
37
38 /* set the watchdog to go and reset... */
39 __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
40 S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
41
42 /* wait for reset to assert... */
43 mdelay(500);
44
45 printk(KERN_ERR "Watchdog reset failed to assert reset\n");
46
47 /* delay to allow the serial port to show the message */
48 mdelay(50);
49}
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