diff options
Diffstat (limited to 'arch/arm/plat-samsung/include/plat/regs-rtc.h')
| -rw-r--r-- | arch/arm/plat-samsung/include/plat/regs-rtc.h | 71 |
1 files changed, 0 insertions, 71 deletions
diff --git a/arch/arm/plat-samsung/include/plat/regs-rtc.h b/arch/arm/plat-samsung/include/plat/regs-rtc.h deleted file mode 100644 index 0f8263e93eea..000000000000 --- a/arch/arm/plat-samsung/include/plat/regs-rtc.h +++ /dev/null | |||
| @@ -1,71 +0,0 @@ | |||
| 1 | /* arch/arm/mach-s3c2410/include/mach/regs-rtc.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> | ||
| 4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * S3C2410 Internal RTC register definition | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_REGS_RTC_H | ||
| 14 | #define __ASM_ARCH_REGS_RTC_H __FILE__ | ||
| 15 | |||
| 16 | #define S3C2410_RTCREG(x) (x) | ||
| 17 | #define S3C2410_INTP S3C2410_RTCREG(0x30) | ||
| 18 | #define S3C2410_INTP_ALM (1 << 1) | ||
| 19 | #define S3C2410_INTP_TIC (1 << 0) | ||
| 20 | |||
| 21 | #define S3C2410_RTCCON S3C2410_RTCREG(0x40) | ||
| 22 | #define S3C2410_RTCCON_RTCEN (1 << 0) | ||
| 23 | #define S3C2410_RTCCON_CNTSEL (1 << 2) | ||
| 24 | #define S3C2410_RTCCON_CLKRST (1 << 3) | ||
| 25 | #define S3C2443_RTCCON_TICSEL (1 << 4) | ||
| 26 | #define S3C64XX_RTCCON_TICEN (1 << 8) | ||
| 27 | |||
| 28 | #define S3C2410_TICNT S3C2410_RTCREG(0x44) | ||
| 29 | #define S3C2410_TICNT_ENABLE (1 << 7) | ||
| 30 | |||
| 31 | /* S3C2443: tick count is 15 bit wide | ||
| 32 | * TICNT[6:0] contains upper 7 bits | ||
| 33 | * TICNT1[7:0] contains lower 8 bits | ||
| 34 | */ | ||
| 35 | #define S3C2443_TICNT_PART(x) ((x & 0x7f00) >> 8) | ||
| 36 | #define S3C2443_TICNT1 S3C2410_RTCREG(0x4C) | ||
| 37 | #define S3C2443_TICNT1_PART(x) (x & 0xff) | ||
| 38 | |||
| 39 | /* S3C2416: tick count is 32 bit wide | ||
| 40 | * TICNT[6:0] contains bits [14:8] | ||
| 41 | * TICNT1[7:0] contains lower 8 bits | ||
| 42 | * TICNT2[16:0] contains upper 17 bits | ||
| 43 | */ | ||
| 44 | #define S3C2416_TICNT2 S3C2410_RTCREG(0x48) | ||
| 45 | #define S3C2416_TICNT2_PART(x) ((x & 0xffff8000) >> 15) | ||
| 46 | |||
| 47 | #define S3C2410_RTCALM S3C2410_RTCREG(0x50) | ||
| 48 | #define S3C2410_RTCALM_ALMEN (1 << 6) | ||
| 49 | #define S3C2410_RTCALM_YEAREN (1 << 5) | ||
| 50 | #define S3C2410_RTCALM_MONEN (1 << 4) | ||
| 51 | #define S3C2410_RTCALM_DAYEN (1 << 3) | ||
| 52 | #define S3C2410_RTCALM_HOUREN (1 << 2) | ||
| 53 | #define S3C2410_RTCALM_MINEN (1 << 1) | ||
| 54 | #define S3C2410_RTCALM_SECEN (1 << 0) | ||
| 55 | |||
| 56 | #define S3C2410_ALMSEC S3C2410_RTCREG(0x54) | ||
| 57 | #define S3C2410_ALMMIN S3C2410_RTCREG(0x58) | ||
| 58 | #define S3C2410_ALMHOUR S3C2410_RTCREG(0x5c) | ||
| 59 | |||
| 60 | #define S3C2410_ALMDATE S3C2410_RTCREG(0x60) | ||
| 61 | #define S3C2410_ALMMON S3C2410_RTCREG(0x64) | ||
| 62 | #define S3C2410_ALMYEAR S3C2410_RTCREG(0x68) | ||
| 63 | |||
| 64 | #define S3C2410_RTCSEC S3C2410_RTCREG(0x70) | ||
| 65 | #define S3C2410_RTCMIN S3C2410_RTCREG(0x74) | ||
| 66 | #define S3C2410_RTCHOUR S3C2410_RTCREG(0x78) | ||
| 67 | #define S3C2410_RTCDATE S3C2410_RTCREG(0x7c) | ||
| 68 | #define S3C2410_RTCMON S3C2410_RTCREG(0x84) | ||
| 69 | #define S3C2410_RTCYEAR S3C2410_RTCREG(0x88) | ||
| 70 | |||
| 71 | #endif /* __ASM_ARCH_REGS_RTC_H */ | ||