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-rw-r--r--arch/arm/plat-s5pc1xx/Kconfig18
-rw-r--r--arch/arm/plat-s5pc1xx/Makefile11
-rw-r--r--arch/arm/plat-s5pc1xx/clock.c728
-rw-r--r--arch/arm/plat-s5pc1xx/cpu.c10
-rw-r--r--arch/arm/plat-s5pc1xx/gpio-config.c62
-rw-r--r--arch/arm/plat-s5pc1xx/gpiolib.c503
-rw-r--r--arch/arm/plat-s5pc1xx/include/plat/gpio-cfg-s5pc1xx.h32
-rw-r--r--arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h44
-rw-r--r--arch/arm/plat-s5pc1xx/include/plat/irqs.h15
-rw-r--r--arch/arm/plat-s5pc1xx/include/plat/regs-clock.h212
-rw-r--r--arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h70
-rw-r--r--arch/arm/plat-s5pc1xx/include/plat/regs-power.h84
-rw-r--r--arch/arm/plat-s5pc1xx/include/plat/s5pc100.h5
-rw-r--r--arch/arm/plat-s5pc1xx/irq-eint.c281
-rw-r--r--arch/arm/plat-s5pc1xx/irq-gpio.c266
-rw-r--r--arch/arm/plat-s5pc1xx/irq.c2
-rw-r--r--arch/arm/plat-s5pc1xx/s5pc100-clock.c1555
-rw-r--r--arch/arm/plat-s5pc1xx/setup-fb-24bpp.c49
-rw-r--r--arch/arm/plat-s5pc1xx/setup-i2c0.c7
-rw-r--r--arch/arm/plat-s5pc1xx/setup-i2c1.c7
-rw-r--r--arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c86
21 files changed, 3121 insertions, 926 deletions
diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig
index a8a711c3c064..1608e62b0c9d 100644
--- a/arch/arm/plat-s5pc1xx/Kconfig
+++ b/arch/arm/plat-s5pc1xx/Kconfig
@@ -15,6 +15,9 @@ config PLAT_S5PC1XX
15 select ARCH_REQUIRE_GPIOLIB 15 select ARCH_REQUIRE_GPIOLIB
16 select S3C_GPIO_TRACK 16 select S3C_GPIO_TRACK
17 select S3C_GPIO_PULL_UPDOWN 17 select S3C_GPIO_PULL_UPDOWN
18 select S3C_GPIO_CFG_S3C24XX
19 select S3C_GPIO_CFG_S3C64XX
20 select S5P_GPIO_CFG_S5PC1XX
18 help 21 help
19 Base platform code for any Samsung S5PC1XX device 22 Base platform code for any Samsung S5PC1XX device
20 23
@@ -34,7 +37,12 @@ config CPU_S5PC100_CLOCK
34 37
35# platform specific device setup 38# platform specific device setup
36 39
37config S5PC100_SETUP_I2C0 40config S5PC1XX_SETUP_FB_24BPP
41 bool
42 help
43 Common setup code for S5PC1XX with an 24bpp RGB display helper.
44
45config S5PC1XX_SETUP_I2C0
38 bool 46 bool
39 default y 47 default y
40 help 48 help
@@ -43,8 +51,14 @@ config S5PC100_SETUP_I2C0
43 Note, currently since i2c0 is always compiled, this setup helper 51 Note, currently since i2c0 is always compiled, this setup helper
44 is always compiled with it. 52 is always compiled with it.
45 53
46config S5PC100_SETUP_I2C1 54config S5PC1XX_SETUP_I2C1
47 bool 55 bool
48 help 56 help
49 Common setup code for i2c bus 1. 57 Common setup code for i2c bus 1.
58
59config S5PC1XX_SETUP_SDHCI_GPIO
60 bool
61 help
62 Common setup code for SDHCI gpio.
63
50endif 64endif
diff --git a/arch/arm/plat-s5pc1xx/Makefile b/arch/arm/plat-s5pc1xx/Makefile
index f1ecb2c37ee2..278f26806089 100644
--- a/arch/arm/plat-s5pc1xx/Makefile
+++ b/arch/arm/plat-s5pc1xx/Makefile
@@ -13,7 +13,9 @@ obj- :=
13 13
14obj-y += dev-uart.o 14obj-y += dev-uart.o
15obj-y += cpu.o 15obj-y += cpu.o
16obj-y += irq.o 16obj-y += irq.o irq-gpio.o irq-eint.o
17obj-y += clock.o
18obj-y += gpiolib.o
17 19
18# CPU support 20# CPU support
19 21
@@ -22,5 +24,8 @@ obj-$(CONFIG_CPU_S5PC100_CLOCK) += s5pc100-clock.o
22 24
23# Device setup 25# Device setup
24 26
25obj-$(CONFIG_S5PC100_SETUP_I2C0) += setup-i2c0.o 27obj-$(CONFIG_S5P_GPIO_CFG_S5PC1XX) += gpio-config.o
26obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o 28obj-$(CONFIG_S5PC1XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
29obj-$(CONFIG_S5PC1XX_SETUP_I2C0) += setup-i2c0.o
30obj-$(CONFIG_S5PC1XX_SETUP_I2C1) += setup-i2c1.o
31obj-$(CONFIG_S5PC1XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
diff --git a/arch/arm/plat-s5pc1xx/clock.c b/arch/arm/plat-s5pc1xx/clock.c
new file mode 100644
index 000000000000..26c21d849790
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/clock.c
@@ -0,0 +1,728 @@
1/* linux/arch/arm/plat-s5pc1xx/clock.c
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 *
5 * S5PC1XX Base clock support
6 *
7 * Based on plat-s3c64xx/clock.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/ioport.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20
21#include <mach/hardware.h>
22#include <mach/map.h>
23
24#include <plat/regs-clock.h>
25#include <plat/devs.h>
26#include <plat/clock.h>
27
28struct clk clk_27m = {
29 .name = "clk_27m",
30 .id = -1,
31 .rate = 27000000,
32};
33
34static int clk_48m_ctrl(struct clk *clk, int enable)
35{
36 unsigned long flags;
37 u32 val;
38
39 /* can't rely on clock lock, this register has other usages */
40 local_irq_save(flags);
41
42 val = __raw_readl(S5PC100_CLKSRC1);
43 if (enable)
44 val |= S5PC100_CLKSRC1_CLK48M_MASK;
45 else
46 val &= ~S5PC100_CLKSRC1_CLK48M_MASK;
47
48 __raw_writel(val, S5PC100_CLKSRC1);
49 local_irq_restore(flags);
50
51 return 0;
52}
53
54struct clk clk_48m = {
55 .name = "clk_48m",
56 .id = -1,
57 .rate = 48000000,
58 .enable = clk_48m_ctrl,
59};
60
61struct clk clk_54m = {
62 .name = "clk_54m",
63 .id = -1,
64 .rate = 54000000,
65};
66
67static int clk_default_setrate(struct clk *clk, unsigned long rate)
68{
69 clk->rate = rate;
70 return 0;
71}
72
73static int clk_dummy_enable(struct clk *clk, int enable)
74{
75 return 0;
76}
77
78struct clk clk_hd0 = {
79 .name = "hclkd0",
80 .id = -1,
81 .rate = 0,
82 .parent = NULL,
83 .ctrlbit = 0,
84 .set_rate = clk_default_setrate,
85 .enable = clk_dummy_enable,
86};
87
88struct clk clk_pd0 = {
89 .name = "pclkd0",
90 .id = -1,
91 .rate = 0,
92 .parent = NULL,
93 .ctrlbit = 0,
94 .set_rate = clk_default_setrate,
95 .enable = clk_dummy_enable,
96};
97
98static int s5pc1xx_clk_gate(void __iomem *reg, struct clk *clk, int enable)
99{
100 unsigned int ctrlbit = clk->ctrlbit;
101 u32 con;
102
103 con = __raw_readl(reg);
104 if (enable)
105 con |= ctrlbit;
106 else
107 con &= ~ctrlbit;
108 __raw_writel(con, reg);
109
110 return 0;
111}
112
113static int s5pc100_clk_d00_ctrl(struct clk *clk, int enable)
114{
115 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D00, clk, enable);
116}
117
118static int s5pc100_clk_d01_ctrl(struct clk *clk, int enable)
119{
120 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D01, clk, enable);
121}
122
123static int s5pc100_clk_d02_ctrl(struct clk *clk, int enable)
124{
125 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D02, clk, enable);
126}
127
128static int s5pc100_clk_d10_ctrl(struct clk *clk, int enable)
129{
130 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D10, clk, enable);
131}
132
133static int s5pc100_clk_d11_ctrl(struct clk *clk, int enable)
134{
135 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D11, clk, enable);
136}
137
138static int s5pc100_clk_d12_ctrl(struct clk *clk, int enable)
139{
140 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D12, clk, enable);
141}
142
143static int s5pc100_clk_d13_ctrl(struct clk *clk, int enable)
144{
145 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D13, clk, enable);
146}
147
148static int s5pc100_clk_d14_ctrl(struct clk *clk, int enable)
149{
150 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D14, clk, enable);
151}
152
153static int s5pc100_clk_d15_ctrl(struct clk *clk, int enable)
154{
155 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D15, clk, enable);
156}
157
158static int s5pc100_clk_d20_ctrl(struct clk *clk, int enable)
159{
160 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D20, clk, enable);
161}
162
163int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
164{
165 return s5pc1xx_clk_gate(S5PC100_SCLKGATE0, clk, enable);
166}
167
168int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
169{
170 return s5pc1xx_clk_gate(S5PC100_SCLKGATE1, clk, enable);
171}
172
173static struct clk s5pc100_init_clocks_disable[] = {
174 {
175 .name = "dsi",
176 .id = -1,
177 .parent = &clk_p,
178 .enable = s5pc100_clk_d11_ctrl,
179 .ctrlbit = S5PC100_CLKGATE_D11_DSI,
180 }, {
181 .name = "csi",
182 .id = -1,
183 .parent = &clk_h,
184 .enable = s5pc100_clk_d11_ctrl,
185 .ctrlbit = S5PC100_CLKGATE_D11_CSI,
186 }, {
187 .name = "ccan",
188 .id = 0,
189 .parent = &clk_p,
190 .enable = s5pc100_clk_d14_ctrl,
191 .ctrlbit = S5PC100_CLKGATE_D14_CCAN0,
192 }, {
193 .name = "ccan",
194 .id = 1,
195 .parent = &clk_p,
196 .enable = s5pc100_clk_d14_ctrl,
197 .ctrlbit = S5PC100_CLKGATE_D14_CCAN1,
198 }, {
199 .name = "keypad",
200 .id = -1,
201 .parent = &clk_p,
202 .enable = s5pc100_clk_d15_ctrl,
203 .ctrlbit = S5PC100_CLKGATE_D15_KEYIF,
204 }, {
205 .name = "hclkd2",
206 .id = -1,
207 .parent = NULL,
208 .enable = s5pc100_clk_d20_ctrl,
209 .ctrlbit = S5PC100_CLKGATE_D20_HCLKD2,
210 }, {
211 .name = "iis-d2",
212 .id = -1,
213 .parent = NULL,
214 .enable = s5pc100_clk_d20_ctrl,
215 .ctrlbit = S5PC100_CLKGATE_D20_I2SD2,
216 },
217};
218
219static struct clk s5pc100_init_clocks[] = {
220 /* System1 (D0_0) devices */
221 {
222 .name = "intc",
223 .id = -1,
224 .parent = &clk_hd0,
225 .enable = s5pc100_clk_d00_ctrl,
226 .ctrlbit = S5PC100_CLKGATE_D00_INTC,
227 }, {
228 .name = "tzic",
229 .id = -1,
230 .parent = &clk_hd0,
231 .enable = s5pc100_clk_d00_ctrl,
232 .ctrlbit = S5PC100_CLKGATE_D00_TZIC,
233 }, {
234 .name = "cf-ata",
235 .id = -1,
236 .parent = &clk_hd0,
237 .enable = s5pc100_clk_d00_ctrl,
238 .ctrlbit = S5PC100_CLKGATE_D00_CFCON,
239 }, {
240 .name = "mdma",
241 .id = -1,
242 .parent = &clk_hd0,
243 .enable = s5pc100_clk_d00_ctrl,
244 .ctrlbit = S5PC100_CLKGATE_D00_MDMA,
245 }, {
246 .name = "g2d",
247 .id = -1,
248 .parent = &clk_hd0,
249 .enable = s5pc100_clk_d00_ctrl,
250 .ctrlbit = S5PC100_CLKGATE_D00_G2D,
251 }, {
252 .name = "secss",
253 .id = -1,
254 .parent = &clk_hd0,
255 .enable = s5pc100_clk_d00_ctrl,
256 .ctrlbit = S5PC100_CLKGATE_D00_SECSS,
257 }, {
258 .name = "cssys",
259 .id = -1,
260 .parent = &clk_hd0,
261 .enable = s5pc100_clk_d00_ctrl,
262 .ctrlbit = S5PC100_CLKGATE_D00_CSSYS,
263 },
264
265 /* Memory (D0_1) devices */
266 {
267 .name = "dmc",
268 .id = -1,
269 .parent = &clk_hd0,
270 .enable = s5pc100_clk_d01_ctrl,
271 .ctrlbit = S5PC100_CLKGATE_D01_DMC,
272 }, {
273 .name = "sromc",
274 .id = -1,
275 .parent = &clk_hd0,
276 .enable = s5pc100_clk_d01_ctrl,
277 .ctrlbit = S5PC100_CLKGATE_D01_SROMC,
278 }, {
279 .name = "onenand",
280 .id = -1,
281 .parent = &clk_hd0,
282 .enable = s5pc100_clk_d01_ctrl,
283 .ctrlbit = S5PC100_CLKGATE_D01_ONENAND,
284 }, {
285 .name = "nand",
286 .id = -1,
287 .parent = &clk_hd0,
288 .enable = s5pc100_clk_d01_ctrl,
289 .ctrlbit = S5PC100_CLKGATE_D01_NFCON,
290 }, {
291 .name = "intmem",
292 .id = -1,
293 .parent = &clk_hd0,
294 .enable = s5pc100_clk_d01_ctrl,
295 .ctrlbit = S5PC100_CLKGATE_D01_INTMEM,
296 }, {
297 .name = "ebi",
298 .id = -1,
299 .parent = &clk_hd0,
300 .enable = s5pc100_clk_d01_ctrl,
301 .ctrlbit = S5PC100_CLKGATE_D01_EBI,
302 },
303
304 /* System2 (D0_2) devices */
305 {
306 .name = "seckey",
307 .id = -1,
308 .parent = &clk_pd0,
309 .enable = s5pc100_clk_d02_ctrl,
310 .ctrlbit = S5PC100_CLKGATE_D02_SECKEY,
311 }, {
312 .name = "sdm",
313 .id = -1,
314 .parent = &clk_hd0,
315 .enable = s5pc100_clk_d02_ctrl,
316 .ctrlbit = S5PC100_CLKGATE_D02_SDM,
317 },
318
319 /* File (D1_0) devices */
320 {
321 .name = "pdma",
322 .id = 0,
323 .parent = &clk_h,
324 .enable = s5pc100_clk_d10_ctrl,
325 .ctrlbit = S5PC100_CLKGATE_D10_PDMA0,
326 }, {
327 .name = "pdma",
328 .id = 1,
329 .parent = &clk_h,
330 .enable = s5pc100_clk_d10_ctrl,
331 .ctrlbit = S5PC100_CLKGATE_D10_PDMA1,
332 }, {
333 .name = "usb-host",
334 .id = -1,
335 .parent = &clk_h,
336 .enable = s5pc100_clk_d10_ctrl,
337 .ctrlbit = S5PC100_CLKGATE_D10_USBHOST,
338 }, {
339 .name = "otg",
340 .id = -1,
341 .parent = &clk_h,
342 .enable = s5pc100_clk_d10_ctrl,
343 .ctrlbit = S5PC100_CLKGATE_D10_USBOTG,
344 }, {
345 .name = "modem",
346 .id = -1,
347 .parent = &clk_h,
348 .enable = s5pc100_clk_d10_ctrl,
349 .ctrlbit = S5PC100_CLKGATE_D10_MODEMIF,
350 }, {
351 .name = "hsmmc",
352 .id = 0,
353 .parent = &clk_48m,
354 .enable = s5pc100_clk_d10_ctrl,
355 .ctrlbit = S5PC100_CLKGATE_D10_HSMMC0,
356 }, {
357 .name = "hsmmc",
358 .id = 1,
359 .parent = &clk_48m,
360 .enable = s5pc100_clk_d10_ctrl,
361 .ctrlbit = S5PC100_CLKGATE_D10_HSMMC1,
362 }, {
363 .name = "hsmmc",
364 .id = 2,
365 .parent = &clk_48m,
366 .enable = s5pc100_clk_d10_ctrl,
367 .ctrlbit = S5PC100_CLKGATE_D10_HSMMC2,
368 },
369
370 /* Multimedia1 (D1_1) devices */
371 {
372 .name = "lcd",
373 .id = -1,
374 .parent = &clk_p,
375 .enable = s5pc100_clk_d11_ctrl,
376 .ctrlbit = S5PC100_CLKGATE_D11_LCD,
377 }, {
378 .name = "rotator",
379 .id = -1,
380 .parent = &clk_p,
381 .enable = s5pc100_clk_d11_ctrl,
382 .ctrlbit = S5PC100_CLKGATE_D11_ROTATOR,
383 }, {
384 .name = "fimc",
385 .id = -1,
386 .parent = &clk_p,
387 .enable = s5pc100_clk_d11_ctrl,
388 .ctrlbit = S5PC100_CLKGATE_D11_FIMC0,
389 }, {
390 .name = "fimc",
391 .id = -1,
392 .parent = &clk_p,
393 .enable = s5pc100_clk_d11_ctrl,
394 .ctrlbit = S5PC100_CLKGATE_D11_FIMC1,
395 }, {
396 .name = "fimc",
397 .id = -1,
398 .parent = &clk_p,
399 .enable = s5pc100_clk_d11_ctrl,
400 .ctrlbit = S5PC100_CLKGATE_D11_FIMC2,
401 }, {
402 .name = "jpeg",
403 .id = -1,
404 .parent = &clk_p,
405 .enable = s5pc100_clk_d11_ctrl,
406 .ctrlbit = S5PC100_CLKGATE_D11_JPEG,
407 }, {
408 .name = "g3d",
409 .id = -1,
410 .parent = &clk_p,
411 .enable = s5pc100_clk_d11_ctrl,
412 .ctrlbit = S5PC100_CLKGATE_D11_G3D,
413 },
414
415 /* Multimedia2 (D1_2) devices */
416 {
417 .name = "tv",
418 .id = -1,
419 .parent = &clk_p,
420 .enable = s5pc100_clk_d12_ctrl,
421 .ctrlbit = S5PC100_CLKGATE_D12_TV,
422 }, {
423 .name = "vp",
424 .id = -1,
425 .parent = &clk_p,
426 .enable = s5pc100_clk_d12_ctrl,
427 .ctrlbit = S5PC100_CLKGATE_D12_VP,
428 }, {
429 .name = "mixer",
430 .id = -1,
431 .parent = &clk_p,
432 .enable = s5pc100_clk_d12_ctrl,
433 .ctrlbit = S5PC100_CLKGATE_D12_MIXER,
434 }, {
435 .name = "hdmi",
436 .id = -1,
437 .parent = &clk_p,
438 .enable = s5pc100_clk_d12_ctrl,
439 .ctrlbit = S5PC100_CLKGATE_D12_HDMI,
440 }, {
441 .name = "mfc",
442 .id = -1,
443 .parent = &clk_p,
444 .enable = s5pc100_clk_d12_ctrl,
445 .ctrlbit = S5PC100_CLKGATE_D12_MFC,
446 },
447
448 /* System (D1_3) devices */
449 {
450 .name = "chipid",
451 .id = -1,
452 .parent = &clk_p,
453 .enable = s5pc100_clk_d13_ctrl,
454 .ctrlbit = S5PC100_CLKGATE_D13_CHIPID,
455 }, {
456 .name = "gpio",
457 .id = -1,
458 .parent = &clk_p,
459 .enable = s5pc100_clk_d13_ctrl,
460 .ctrlbit = S5PC100_CLKGATE_D13_GPIO,
461 }, {
462 .name = "apc",
463 .id = -1,
464 .parent = &clk_p,
465 .enable = s5pc100_clk_d13_ctrl,
466 .ctrlbit = S5PC100_CLKGATE_D13_APC,
467 }, {
468 .name = "iec",
469 .id = -1,
470 .parent = &clk_p,
471 .enable = s5pc100_clk_d13_ctrl,
472 .ctrlbit = S5PC100_CLKGATE_D13_IEC,
473 }, {
474 .name = "timers",
475 .id = -1,
476 .parent = &clk_p,
477 .enable = s5pc100_clk_d13_ctrl,
478 .ctrlbit = S5PC100_CLKGATE_D13_PWM,
479 }, {
480 .name = "systimer",
481 .id = -1,
482 .parent = &clk_p,
483 .enable = s5pc100_clk_d13_ctrl,
484 .ctrlbit = S5PC100_CLKGATE_D13_SYSTIMER,
485 }, {
486 .name = "watchdog",
487 .id = -1,
488 .parent = &clk_p,
489 .enable = s5pc100_clk_d13_ctrl,
490 .ctrlbit = S5PC100_CLKGATE_D13_WDT,
491 }, {
492 .name = "rtc",
493 .id = -1,
494 .parent = &clk_p,
495 .enable = s5pc100_clk_d13_ctrl,
496 .ctrlbit = S5PC100_CLKGATE_D13_RTC,
497 },
498
499 /* Connectivity (D1_4) devices */
500 {
501 .name = "uart",
502 .id = 0,
503 .parent = &clk_p,
504 .enable = s5pc100_clk_d14_ctrl,
505 .ctrlbit = S5PC100_CLKGATE_D14_UART0,
506 }, {
507 .name = "uart",
508 .id = 1,
509 .parent = &clk_p,
510 .enable = s5pc100_clk_d14_ctrl,
511 .ctrlbit = S5PC100_CLKGATE_D14_UART1,
512 }, {
513 .name = "uart",
514 .id = 2,
515 .parent = &clk_p,
516 .enable = s5pc100_clk_d14_ctrl,
517 .ctrlbit = S5PC100_CLKGATE_D14_UART2,
518 }, {
519 .name = "uart",
520 .id = 3,
521 .parent = &clk_p,
522 .enable = s5pc100_clk_d14_ctrl,
523 .ctrlbit = S5PC100_CLKGATE_D14_UART3,
524 }, {
525 .name = "i2c",
526 .id = -1,
527 .parent = &clk_p,
528 .enable = s5pc100_clk_d14_ctrl,
529 .ctrlbit = S5PC100_CLKGATE_D14_IIC,
530 }, {
531 .name = "hdmi-i2c",
532 .id = -1,
533 .parent = &clk_p,
534 .enable = s5pc100_clk_d14_ctrl,
535 .ctrlbit = S5PC100_CLKGATE_D14_HDMI_IIC,
536 }, {
537 .name = "spi",
538 .id = 0,
539 .parent = &clk_p,
540 .enable = s5pc100_clk_d14_ctrl,
541 .ctrlbit = S5PC100_CLKGATE_D14_SPI0,
542 }, {
543 .name = "spi",
544 .id = 1,
545 .parent = &clk_p,
546 .enable = s5pc100_clk_d14_ctrl,
547 .ctrlbit = S5PC100_CLKGATE_D14_SPI1,
548 }, {
549 .name = "spi",
550 .id = 2,
551 .parent = &clk_p,
552 .enable = s5pc100_clk_d14_ctrl,
553 .ctrlbit = S5PC100_CLKGATE_D14_SPI2,
554 }, {
555 .name = "irda",
556 .id = -1,
557 .parent = &clk_p,
558 .enable = s5pc100_clk_d14_ctrl,
559 .ctrlbit = S5PC100_CLKGATE_D14_IRDA,
560 }, {
561 .name = "hsitx",
562 .id = -1,
563 .parent = &clk_p,
564 .enable = s5pc100_clk_d14_ctrl,
565 .ctrlbit = S5PC100_CLKGATE_D14_HSITX,
566 }, {
567 .name = "hsirx",
568 .id = -1,
569 .parent = &clk_p,
570 .enable = s5pc100_clk_d14_ctrl,
571 .ctrlbit = S5PC100_CLKGATE_D14_HSIRX,
572 },
573
574 /* Audio (D1_5) devices */
575 {
576 .name = "iis",
577 .id = 0,
578 .parent = &clk_p,
579 .enable = s5pc100_clk_d15_ctrl,
580 .ctrlbit = S5PC100_CLKGATE_D15_IIS0,
581 }, {
582 .name = "iis",
583 .id = 1,
584 .parent = &clk_p,
585 .enable = s5pc100_clk_d15_ctrl,
586 .ctrlbit = S5PC100_CLKGATE_D15_IIS1,
587 }, {
588 .name = "iis",
589 .id = 2,
590 .parent = &clk_p,
591 .enable = s5pc100_clk_d15_ctrl,
592 .ctrlbit = S5PC100_CLKGATE_D15_IIS2,
593 }, {
594 .name = "ac97",
595 .id = -1,
596 .parent = &clk_p,
597 .enable = s5pc100_clk_d15_ctrl,
598 .ctrlbit = S5PC100_CLKGATE_D15_AC97,
599 }, {
600 .name = "pcm",
601 .id = 0,
602 .parent = &clk_p,
603 .enable = s5pc100_clk_d15_ctrl,
604 .ctrlbit = S5PC100_CLKGATE_D15_PCM0,
605 }, {
606 .name = "pcm",
607 .id = 1,
608 .parent = &clk_p,
609 .enable = s5pc100_clk_d15_ctrl,
610 .ctrlbit = S5PC100_CLKGATE_D15_PCM1,
611 }, {
612 .name = "spdif",
613 .id = -1,
614 .parent = &clk_p,
615 .enable = s5pc100_clk_d15_ctrl,
616 .ctrlbit = S5PC100_CLKGATE_D15_SPDIF,
617 }, {
618 .name = "adc",
619 .id = -1,
620 .parent = &clk_p,
621 .enable = s5pc100_clk_d15_ctrl,
622 .ctrlbit = S5PC100_CLKGATE_D15_TSADC,
623 }, {
624 .name = "cg",
625 .id = -1,
626 .parent = &clk_p,
627 .enable = s5pc100_clk_d15_ctrl,
628 .ctrlbit = S5PC100_CLKGATE_D15_CG,
629 },
630
631 /* Audio (D2_0) devices: all disabled */
632
633 /* Special Clocks 0 */
634 {
635 .name = "sclk_hpm",
636 .id = -1,
637 .parent = NULL,
638 .enable = s5pc100_sclk0_ctrl,
639 .ctrlbit = S5PC100_CLKGATE_SCLK0_HPM,
640 }, {
641 .name = "sclk_onenand",
642 .id = -1,
643 .parent = NULL,
644 .enable = s5pc100_sclk0_ctrl,
645 .ctrlbit = S5PC100_CLKGATE_SCLK0_ONENAND,
646 }, {
647 .name = "spi_48",
648 .id = 0,
649 .parent = &clk_48m,
650 .enable = s5pc100_sclk0_ctrl,
651 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0_48,
652 }, {
653 .name = "spi_48",
654 .id = 1,
655 .parent = &clk_48m,
656 .enable = s5pc100_sclk0_ctrl,
657 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1_48,
658 }, {
659 .name = "spi_48",
660 .id = 2,
661 .parent = &clk_48m,
662 .enable = s5pc100_sclk0_ctrl,
663 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2_48,
664 }, {
665 .name = "mmc_48",
666 .id = 0,
667 .parent = &clk_48m,
668 .enable = s5pc100_sclk0_ctrl,
669 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0_48,
670 }, {
671 .name = "mmc_48",
672 .id = 1,
673 .parent = &clk_48m,
674 .enable = s5pc100_sclk0_ctrl,
675 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1_48,
676 }, {
677 .name = "mmc_48",
678 .id = 2,
679 .parent = &clk_48m,
680 .enable = s5pc100_sclk0_ctrl,
681 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2_48,
682 },
683 /* Special Clocks 1 */
684};
685
686static struct clk *clks[] __initdata = {
687 &clk_ext,
688 &clk_epll,
689 &clk_27m,
690 &clk_48m,
691 &clk_54m,
692};
693
694void __init s5pc1xx_register_clocks(void)
695{
696 struct clk *clkp;
697 int ret;
698 int ptr;
699 int size;
700
701 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
702
703 clkp = s5pc100_init_clocks;
704 size = ARRAY_SIZE(s5pc100_init_clocks);
705
706 for (ptr = 0; ptr < size; ptr++, clkp++) {
707 ret = s3c24xx_register_clock(clkp);
708 if (ret < 0) {
709 printk(KERN_ERR "Failed to register clock %s (%d)\n",
710 clkp->name, ret);
711 }
712 }
713
714 clkp = s5pc100_init_clocks_disable;
715 size = ARRAY_SIZE(s5pc100_init_clocks_disable);
716
717 for (ptr = 0; ptr < size; ptr++, clkp++) {
718 ret = s3c24xx_register_clock(clkp);
719 if (ret < 0) {
720 printk(KERN_ERR "Failed to register clock %s (%d)\n",
721 clkp->name, ret);
722 }
723
724 (clkp->enable)(clkp, 0);
725 }
726
727 s3c_pwmclk_init();
728}
diff --git a/arch/arm/plat-s5pc1xx/cpu.c b/arch/arm/plat-s5pc1xx/cpu.c
index 715a7330794d..02baeaa2a121 100644
--- a/arch/arm/plat-s5pc1xx/cpu.c
+++ b/arch/arm/plat-s5pc1xx/cpu.c
@@ -55,6 +55,16 @@ static struct cpu_table cpu_ids[] __initdata = {
55 55
56static struct map_desc s5pc1xx_iodesc[] __initdata = { 56static struct map_desc s5pc1xx_iodesc[] __initdata = {
57 { 57 {
58 .virtual = (unsigned long)S5PC1XX_VA_CLK_OTHER,
59 .pfn = __phys_to_pfn(S5PC1XX_PA_CLK_OTHER),
60 .length = SZ_4K,
61 .type = MT_DEVICE,
62 }, {
63 .virtual = (unsigned long)S5PC1XX_VA_GPIO,
64 .pfn = __phys_to_pfn(S5PC100_PA_GPIO),
65 .length = SZ_4K,
66 .type = MT_DEVICE,
67 }, {
58 .virtual = (unsigned long)S5PC1XX_VA_CHIPID, 68 .virtual = (unsigned long)S5PC1XX_VA_CHIPID,
59 .pfn = __phys_to_pfn(S5PC1XX_PA_CHIPID), 69 .pfn = __phys_to_pfn(S5PC1XX_PA_CHIPID),
60 .length = SZ_16, 70 .length = SZ_16,
diff --git a/arch/arm/plat-s5pc1xx/gpio-config.c b/arch/arm/plat-s5pc1xx/gpio-config.c
new file mode 100644
index 000000000000..bba675df9c75
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/gpio-config.c
@@ -0,0 +1,62 @@
1/* linux/arch/arm/plat-s5pc1xx/gpio-config.c
2 *
3 * Copyright 2009 Samsung Electronics
4 *
5 * S5PC1XX GPIO Configuration.
6 *
7 * Based on plat-s3c64xx/gpio-config.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/gpio.h>
17#include <linux/io.h>
18
19#include <mach/gpio-core.h>
20#include <plat/gpio-cfg-s5pc1xx.h>
21
22s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin, unsigned int off)
23{
24 struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
25 void __iomem *reg;
26 int shift = off * 2;
27 u32 drvstr;
28
29 if (!chip)
30 return -EINVAL;
31
32 reg = chip->base + 0x0C;
33
34 drvstr = __raw_readl(reg);
35 drvstr = 0xffff & (0x3 << shift);
36 drvstr = drvstr >> shift;
37
38 return (__force s5p_gpio_drvstr_t)drvstr;
39}
40EXPORT_SYMBOL(s5p_gpio_get_drvstr);
41
42int s5p_gpio_set_drvstr(unsigned int pin, unsigned int off,
43 s5p_gpio_drvstr_t drvstr)
44{
45 struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
46 void __iomem *reg;
47 int shift = off * 2;
48 u32 tmp;
49
50 if (!chip)
51 return -EINVAL;
52
53 reg = chip->base + 0x0C;
54
55 tmp = __raw_readl(reg);
56 tmp |= drvstr << shift;
57
58 __raw_writel(tmp, reg);
59
60 return 0;
61}
62EXPORT_SYMBOL(s5p_gpio_set_drvstr);
diff --git a/arch/arm/plat-s5pc1xx/gpiolib.c b/arch/arm/plat-s5pc1xx/gpiolib.c
new file mode 100644
index 000000000000..facb410e7a71
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/gpiolib.c
@@ -0,0 +1,503 @@
1/*
2 * arch/arm/plat-s5pc1xx/gpiolib.c
3 *
4 * Copyright 2009 Samsung Electronics Co
5 * Kyungmin Park <kyungmin.park@samsung.com>
6 *
7 * S5PC1XX - GPIOlib support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17#include <linux/gpio.h>
18
19#include <mach/map.h>
20#include <mach/gpio-core.h>
21
22#include <plat/gpio-cfg.h>
23#include <plat/gpio-cfg-helpers.h>
24#include <plat/regs-gpio.h>
25
26/* S5PC100 GPIO bank summary:
27 *
28 * Bank GPIOs Style INT Type
29 * A0 8 4Bit GPIO_INT0
30 * A1 5 4Bit GPIO_INT1
31 * B 8 4Bit GPIO_INT2
32 * C 5 4Bit GPIO_INT3
33 * D 7 4Bit GPIO_INT4
34 * E0 8 4Bit GPIO_INT5
35 * E1 6 4Bit GPIO_INT6
36 * F0 8 4Bit GPIO_INT7
37 * F1 8 4Bit GPIO_INT8
38 * F2 8 4Bit GPIO_INT9
39 * F3 4 4Bit GPIO_INT10
40 * G0 8 4Bit GPIO_INT11
41 * G1 3 4Bit GPIO_INT12
42 * G2 7 4Bit GPIO_INT13
43 * G3 7 4Bit GPIO_INT14
44 * H0 8 4Bit WKUP_INT
45 * H1 8 4Bit WKUP_INT
46 * H2 8 4Bit WKUP_INT
47 * H3 8 4Bit WKUP_INT
48 * I 8 4Bit GPIO_INT15
49 * J0 8 4Bit GPIO_INT16
50 * J1 5 4Bit GPIO_INT17
51 * J2 8 4Bit GPIO_INT18
52 * J3 8 4Bit GPIO_INT19
53 * J4 4 4Bit GPIO_INT20
54 * K0 8 4Bit None
55 * K1 6 4Bit None
56 * K2 8 4Bit None
57 * K3 8 4Bit None
58 * L0 8 4Bit None
59 * L1 8 4Bit None
60 * L2 8 4Bit None
61 * L3 8 4Bit None
62 */
63
64#define OFF_GPCON (0x00)
65#define OFF_GPDAT (0x04)
66
67#define con_4bit_shift(__off) ((__off) * 4)
68
69#if 1
70#define gpio_dbg(x...) do { } while (0)
71#else
72#define gpio_dbg(x...) printk(KERN_DEBUG x)
73#endif
74
75/* The s5pc1xx_gpiolib routines are to control the gpio banks where
76 * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
77 * following example:
78 *
79 * base + 0x00: Control register, 4 bits per gpio
80 * gpio n: 4 bits starting at (4*n)
81 * 0000 = input, 0001 = output, others mean special-function
82 * base + 0x04: Data register, 1 bit per gpio
83 * bit n: data bit n
84 *
85 * Note, since the data register is one bit per gpio and is at base + 0x4
86 * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of
87 * the output.
88 */
89
90static int s5pc1xx_gpiolib_input(struct gpio_chip *chip, unsigned offset)
91{
92 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
93 void __iomem *base = ourchip->base;
94 unsigned long con;
95
96 con = __raw_readl(base + OFF_GPCON);
97 con &= ~(0xf << con_4bit_shift(offset));
98 __raw_writel(con, base + OFF_GPCON);
99
100 gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
101
102 return 0;
103}
104
105static int s5pc1xx_gpiolib_output(struct gpio_chip *chip,
106 unsigned offset, int value)
107{
108 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
109 void __iomem *base = ourchip->base;
110 unsigned long con;
111 unsigned long dat;
112
113 con = __raw_readl(base + OFF_GPCON);
114 con &= ~(0xf << con_4bit_shift(offset));
115 con |= 0x1 << con_4bit_shift(offset);
116
117 dat = __raw_readl(base + OFF_GPDAT);
118 if (value)
119 dat |= 1 << offset;
120 else
121 dat &= ~(1 << offset);
122
123 __raw_writel(dat, base + OFF_GPDAT);
124 __raw_writel(con, base + OFF_GPCON);
125 __raw_writel(dat, base + OFF_GPDAT);
126
127 gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
128
129 return 0;
130}
131
132static int s5pc1xx_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
133{
134 return S3C_IRQ_GPIO(chip->base + offset);
135}
136
137static int s5pc1xx_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
138{
139 int base;
140
141 base = chip->base - S5PC100_GPH0(0);
142 if (base == 0)
143 return IRQ_EINT(offset);
144 base = chip->base - S5PC100_GPH1(0);
145 if (base == 0)
146 return IRQ_EINT(8 + offset);
147 base = chip->base - S5PC100_GPH2(0);
148 if (base == 0)
149 return IRQ_EINT(16 + offset);
150 base = chip->base - S5PC100_GPH3(0);
151 if (base == 0)
152 return IRQ_EINT(24 + offset);
153 return -EINVAL;
154}
155
156static struct s3c_gpio_cfg gpio_cfg = {
157 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
158 .set_pull = s3c_gpio_setpull_updown,
159 .get_pull = s3c_gpio_getpull_updown,
160};
161
162static struct s3c_gpio_cfg gpio_cfg_eint = {
163 .cfg_eint = 0xf,
164 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
165 .set_pull = s3c_gpio_setpull_updown,
166 .get_pull = s3c_gpio_getpull_updown,
167};
168
169static struct s3c_gpio_cfg gpio_cfg_noint = {
170 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
171 .set_pull = s3c_gpio_setpull_updown,
172 .get_pull = s3c_gpio_getpull_updown,
173};
174
175static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
176 {
177 .base = S5PC100_GPA0_BASE,
178 .config = &gpio_cfg,
179 .chip = {
180 .base = S5PC100_GPA0(0),
181 .ngpio = S5PC100_GPIO_A0_NR,
182 .label = "GPA0",
183 },
184 }, {
185 .base = S5PC100_GPA1_BASE,
186 .config = &gpio_cfg,
187 .chip = {
188 .base = S5PC100_GPA1(0),
189 .ngpio = S5PC100_GPIO_A1_NR,
190 .label = "GPA1",
191 },
192 }, {
193 .base = S5PC100_GPB_BASE,
194 .config = &gpio_cfg,
195 .chip = {
196 .base = S5PC100_GPB(0),
197 .ngpio = S5PC100_GPIO_B_NR,
198 .label = "GPB",
199 },
200 }, {
201 .base = S5PC100_GPC_BASE,
202 .config = &gpio_cfg,
203 .chip = {
204 .base = S5PC100_GPC(0),
205 .ngpio = S5PC100_GPIO_C_NR,
206 .label = "GPC",
207 },
208 }, {
209 .base = S5PC100_GPD_BASE,
210 .config = &gpio_cfg,
211 .chip = {
212 .base = S5PC100_GPD(0),
213 .ngpio = S5PC100_GPIO_D_NR,
214 .label = "GPD",
215 },
216 }, {
217 .base = S5PC100_GPE0_BASE,
218 .config = &gpio_cfg,
219 .chip = {
220 .base = S5PC100_GPE0(0),
221 .ngpio = S5PC100_GPIO_E0_NR,
222 .label = "GPE0",
223 },
224 }, {
225 .base = S5PC100_GPE1_BASE,
226 .config = &gpio_cfg,
227 .chip = {
228 .base = S5PC100_GPE1(0),
229 .ngpio = S5PC100_GPIO_E1_NR,
230 .label = "GPE1",
231 },
232 }, {
233 .base = S5PC100_GPF0_BASE,
234 .config = &gpio_cfg,
235 .chip = {
236 .base = S5PC100_GPF0(0),
237 .ngpio = S5PC100_GPIO_F0_NR,
238 .label = "GPF0",
239 },
240 }, {
241 .base = S5PC100_GPF1_BASE,
242 .config = &gpio_cfg,
243 .chip = {
244 .base = S5PC100_GPF1(0),
245 .ngpio = S5PC100_GPIO_F1_NR,
246 .label = "GPF1",
247 },
248 }, {
249 .base = S5PC100_GPF2_BASE,
250 .config = &gpio_cfg,
251 .chip = {
252 .base = S5PC100_GPF2(0),
253 .ngpio = S5PC100_GPIO_F2_NR,
254 .label = "GPF2",
255 },
256 }, {
257 .base = S5PC100_GPF3_BASE,
258 .config = &gpio_cfg,
259 .chip = {
260 .base = S5PC100_GPF3(0),
261 .ngpio = S5PC100_GPIO_F3_NR,
262 .label = "GPF3",
263 },
264 }, {
265 .base = S5PC100_GPG0_BASE,
266 .config = &gpio_cfg,
267 .chip = {
268 .base = S5PC100_GPG0(0),
269 .ngpio = S5PC100_GPIO_G0_NR,
270 .label = "GPG0",
271 },
272 }, {
273 .base = S5PC100_GPG1_BASE,
274 .config = &gpio_cfg,
275 .chip = {
276 .base = S5PC100_GPG1(0),
277 .ngpio = S5PC100_GPIO_G1_NR,
278 .label = "GPG1",
279 },
280 }, {
281 .base = S5PC100_GPG2_BASE,
282 .config = &gpio_cfg,
283 .chip = {
284 .base = S5PC100_GPG2(0),
285 .ngpio = S5PC100_GPIO_G2_NR,
286 .label = "GPG2",
287 },
288 }, {
289 .base = S5PC100_GPG3_BASE,
290 .config = &gpio_cfg,
291 .chip = {
292 .base = S5PC100_GPG3(0),
293 .ngpio = S5PC100_GPIO_G3_NR,
294 .label = "GPG3",
295 },
296 }, {
297 .base = S5PC100_GPH0_BASE,
298 .config = &gpio_cfg_eint,
299 .chip = {
300 .base = S5PC100_GPH0(0),
301 .ngpio = S5PC100_GPIO_H0_NR,
302 .label = "GPH0",
303 },
304 }, {
305 .base = S5PC100_GPH1_BASE,
306 .config = &gpio_cfg_eint,
307 .chip = {
308 .base = S5PC100_GPH1(0),
309 .ngpio = S5PC100_GPIO_H1_NR,
310 .label = "GPH1",
311 },
312 }, {
313 .base = S5PC100_GPH2_BASE,
314 .config = &gpio_cfg_eint,
315 .chip = {
316 .base = S5PC100_GPH2(0),
317 .ngpio = S5PC100_GPIO_H2_NR,
318 .label = "GPH2",
319 },
320 }, {
321 .base = S5PC100_GPH3_BASE,
322 .config = &gpio_cfg_eint,
323 .chip = {
324 .base = S5PC100_GPH3(0),
325 .ngpio = S5PC100_GPIO_H3_NR,
326 .label = "GPH3",
327 },
328 }, {
329 .base = S5PC100_GPI_BASE,
330 .config = &gpio_cfg,
331 .chip = {
332 .base = S5PC100_GPI(0),
333 .ngpio = S5PC100_GPIO_I_NR,
334 .label = "GPI",
335 },
336 }, {
337 .base = S5PC100_GPJ0_BASE,
338 .config = &gpio_cfg,
339 .chip = {
340 .base = S5PC100_GPJ0(0),
341 .ngpio = S5PC100_GPIO_J0_NR,
342 .label = "GPJ0",
343 },
344 }, {
345 .base = S5PC100_GPJ1_BASE,
346 .config = &gpio_cfg,
347 .chip = {
348 .base = S5PC100_GPJ1(0),
349 .ngpio = S5PC100_GPIO_J1_NR,
350 .label = "GPJ1",
351 },
352 }, {
353 .base = S5PC100_GPJ2_BASE,
354 .config = &gpio_cfg,
355 .chip = {
356 .base = S5PC100_GPJ2(0),
357 .ngpio = S5PC100_GPIO_J2_NR,
358 .label = "GPJ2",
359 },
360 }, {
361 .base = S5PC100_GPJ3_BASE,
362 .config = &gpio_cfg,
363 .chip = {
364 .base = S5PC100_GPJ3(0),
365 .ngpio = S5PC100_GPIO_J3_NR,
366 .label = "GPJ3",
367 },
368 }, {
369 .base = S5PC100_GPJ4_BASE,
370 .config = &gpio_cfg,
371 .chip = {
372 .base = S5PC100_GPJ4(0),
373 .ngpio = S5PC100_GPIO_J4_NR,
374 .label = "GPJ4",
375 },
376 }, {
377 .base = S5PC100_GPK0_BASE,
378 .config = &gpio_cfg_noint,
379 .chip = {
380 .base = S5PC100_GPK0(0),
381 .ngpio = S5PC100_GPIO_K0_NR,
382 .label = "GPK0",
383 },
384 }, {
385 .base = S5PC100_GPK1_BASE,
386 .config = &gpio_cfg_noint,
387 .chip = {
388 .base = S5PC100_GPK1(0),
389 .ngpio = S5PC100_GPIO_K1_NR,
390 .label = "GPK1",
391 },
392 }, {
393 .base = S5PC100_GPK2_BASE,
394 .config = &gpio_cfg_noint,
395 .chip = {
396 .base = S5PC100_GPK2(0),
397 .ngpio = S5PC100_GPIO_K2_NR,
398 .label = "GPK2",
399 },
400 }, {
401 .base = S5PC100_GPK3_BASE,
402 .config = &gpio_cfg_noint,
403 .chip = {
404 .base = S5PC100_GPK3(0),
405 .ngpio = S5PC100_GPIO_K3_NR,
406 .label = "GPK3",
407 },
408 }, {
409 .base = S5PC100_GPL0_BASE,
410 .config = &gpio_cfg_noint,
411 .chip = {
412 .base = S5PC100_GPL0(0),
413 .ngpio = S5PC100_GPIO_L0_NR,
414 .label = "GPL0",
415 },
416 }, {
417 .base = S5PC100_GPL1_BASE,
418 .config = &gpio_cfg_noint,
419 .chip = {
420 .base = S5PC100_GPL1(0),
421 .ngpio = S5PC100_GPIO_L1_NR,
422 .label = "GPL1",
423 },
424 }, {
425 .base = S5PC100_GPL2_BASE,
426 .config = &gpio_cfg_noint,
427 .chip = {
428 .base = S5PC100_GPL2(0),
429 .ngpio = S5PC100_GPIO_L2_NR,
430 .label = "GPL2",
431 },
432 }, {
433 .base = S5PC100_GPL3_BASE,
434 .config = &gpio_cfg_noint,
435 .chip = {
436 .base = S5PC100_GPL3(0),
437 .ngpio = S5PC100_GPIO_L3_NR,
438 .label = "GPL3",
439 },
440 }, {
441 .base = S5PC100_GPL4_BASE,
442 .config = &gpio_cfg_noint,
443 .chip = {
444 .base = S5PC100_GPL4(0),
445 .ngpio = S5PC100_GPIO_L4_NR,
446 .label = "GPL4",
447 },
448 },
449};
450
451/* FIXME move from irq-gpio.c */
452extern struct irq_chip s5pc1xx_gpioint;
453extern void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc);
454
455static __init void s5pc1xx_gpiolib_link(struct s3c_gpio_chip *chip)
456{
457 chip->chip.direction_input = s5pc1xx_gpiolib_input;
458 chip->chip.direction_output = s5pc1xx_gpiolib_output;
459 chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
460
461 /* Interrupt */
462 if (chip->config == &gpio_cfg) {
463 int i, irq;
464
465 chip->chip.to_irq = s5pc1xx_gpiolib_to_irq;
466
467 for (i = 0; i < chip->chip.ngpio; i++) {
468 irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i;
469 set_irq_chip(irq, &s5pc1xx_gpioint);
470 set_irq_data(irq, &chip->chip);
471 set_irq_handler(irq, handle_level_irq);
472 set_irq_flags(irq, IRQF_VALID);
473 }
474 } else if (chip->config == &gpio_cfg_eint)
475 chip->chip.to_irq = s5pc1xx_gpiolib_to_eint;
476}
477
478static __init void s5pc1xx_gpiolib_add(struct s3c_gpio_chip *chips,
479 int nr_chips,
480 void (*fn)(struct s3c_gpio_chip *))
481{
482 for (; nr_chips > 0; nr_chips--, chips++) {
483 if (fn)
484 (fn)(chips);
485 s3c_gpiolib_add(chips);
486 }
487}
488
489static __init int s5pc1xx_gpiolib_init(void)
490{
491 struct s3c_gpio_chip *chips;
492 int nr_chips;
493
494 chips = s5pc100_gpio_chips;
495 nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
496
497 s5pc1xx_gpiolib_add(chips, nr_chips, s5pc1xx_gpiolib_link);
498 /* Interrupt */
499 set_irq_chained_handler(IRQ_GPIOINT, s5pc1xx_irq_gpioint_handler);
500
501 return 0;
502}
503core_initcall(s5pc1xx_gpiolib_init);
diff --git a/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg-s5pc1xx.h b/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg-s5pc1xx.h
new file mode 100644
index 000000000000..72ad59f61efc
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg-s5pc1xx.h
@@ -0,0 +1,32 @@
1/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg.h
2 *
3 * Copyright 2009 Samsung Electronic
4 *
5 * S5PC1XX Platform - GPIO pin configuration
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/* This file contains the necessary definitions to get the basic gpio
13 * pin configuration done such as setting a pin to input or output or
14 * changing the pull-{up,down} configurations.
15 */
16
17#ifndef __GPIO_CFG_S5PC1XX_H
18#define __GPIO_CFG_S5PC1XX_H __FILE__
19
20typedef unsigned int __bitwise__ s5p_gpio_drvstr_t;
21
22#define S5P_GPIO_DRVSTR_LV1 0x00
23#define S5P_GPIO_DRVSTR_LV2 0x01
24#define S5P_GPIO_DRVSTR_LV3 0x10
25#define S5P_GPIO_DRVSTR_LV4 0x11
26
27extern s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin, unsigned int off);
28
29extern int s5p_gpio_set_drvstr(unsigned int pin, unsigned int off,
30 s5p_gpio_drvstr_t drvstr);
31
32#endif /* __GPIO_CFG_S5PC1XX_H */
diff --git a/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h b/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h
new file mode 100644
index 000000000000..33ad267e8477
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h
@@ -0,0 +1,44 @@
1/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-eint.h
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 *
5 * External Interrupt (GPH0 ~ GPH3) control register definitions
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#define S5PC1XX_WKUP_INT_CON0_7 (S5PC1XX_EINT_BASE + 0x0)
13#define S5PC1XX_WKUP_INT_CON8_15 (S5PC1XX_EINT_BASE + 0x4)
14#define S5PC1XX_WKUP_INT_CON16_23 (S5PC1XX_EINT_BASE + 0x8)
15#define S5PC1XX_WKUP_INT_CON24_31 (S5PC1XX_EINT_BASE + 0xC)
16#define S5PC1XX_WKUP_INT_CON(x) (S5PC1XX_WKUP_INT_CON0_7 + (x * 0x4))
17
18#define S5PC1XX_WKUP_INT_FLTCON0_3 (S5PC1XX_EINT_BASE + 0x80)
19#define S5PC1XX_WKUP_INT_FLTCON4_7 (S5PC1XX_EINT_BASE + 0x84)
20#define S5PC1XX_WKUP_INT_FLTCON8_11 (S5PC1XX_EINT_BASE + 0x88)
21#define S5PC1XX_WKUP_INT_FLTCON12_15 (S5PC1XX_EINT_BASE + 0x8C)
22#define S5PC1XX_WKUP_INT_FLTCON16_19 (S5PC1XX_EINT_BASE + 0x90)
23#define S5PC1XX_WKUP_INT_FLTCON20_23 (S5PC1XX_EINT_BASE + 0x94)
24#define S5PC1XX_WKUP_INT_FLTCON24_27 (S5PC1XX_EINT_BASE + 0x98)
25#define S5PC1XX_WKUP_INT_FLTCON28_31 (S5PC1XX_EINT_BASE + 0x9C)
26#define S5PC1XX_WKUP_INT_FLTCON(x) (S5PC1XX_WKUP_INT_FLTCON0_3 + (x * 0x4))
27
28#define S5PC1XX_WKUP_INT_MASK0_7 (S5PC1XX_EINT_BASE + 0x100)
29#define S5PC1XX_WKUP_INT_MASK8_15 (S5PC1XX_EINT_BASE + 0x104)
30#define S5PC1XX_WKUP_INT_MASK16_23 (S5PC1XX_EINT_BASE + 0x108)
31#define S5PC1XX_WKUP_INT_MASK24_31 (S5PC1XX_EINT_BASE + 0x10C)
32#define S5PC1XX_WKUP_INT_MASK(x) (S5PC1XX_WKUP_INT_MASK0_7 + (x * 0x4))
33
34#define S5PC1XX_WKUP_INT_PEND0_7 (S5PC1XX_EINT_BASE + 0x140)
35#define S5PC1XX_WKUP_INT_PEND8_15 (S5PC1XX_EINT_BASE + 0x144)
36#define S5PC1XX_WKUP_INT_PEND16_23 (S5PC1XX_EINT_BASE + 0x148)
37#define S5PC1XX_WKUP_INT_PEND24_31 (S5PC1XX_EINT_BASE + 0x14C)
38#define S5PC1XX_WKUP_INT_PEND(x) (S5PC1XX_WKUP_INT_PEND0_7 + (x * 0x4))
39
40#define S5PC1XX_WKUP_INT_LOWLEV (0x00)
41#define S5PC1XX_WKUP_INT_HILEV (0x01)
42#define S5PC1XX_WKUP_INT_FALLEDGE (0x02)
43#define S5PC1XX_WKUP_INT_RISEEDGE (0x03)
44#define S5PC1XX_WKUP_INT_BOTHEDGE (0x04)
diff --git a/arch/arm/plat-s5pc1xx/include/plat/irqs.h b/arch/arm/plat-s5pc1xx/include/plat/irqs.h
index f07d8c3b25d6..ef8736366f0d 100644
--- a/arch/arm/plat-s5pc1xx/include/plat/irqs.h
+++ b/arch/arm/plat-s5pc1xx/include/plat/irqs.h
@@ -171,12 +171,21 @@
171#define IRQ_SDMIRQ S5PC1XX_IRQ_VIC2(30) 171#define IRQ_SDMIRQ S5PC1XX_IRQ_VIC2(30)
172#define IRQ_SDMFIQ S5PC1XX_IRQ_VIC2(31) 172#define IRQ_SDMFIQ S5PC1XX_IRQ_VIC2(31)
173 173
174/* External interrupt */
174#define S3C_IRQ_EINT_BASE (IRQ_SDMFIQ + 1) 175#define S3C_IRQ_EINT_BASE (IRQ_SDMFIQ + 1)
175 176
176#define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE) 177#define S3C_EINT(x) (S3C_IRQ_EINT_BASE + (x - 16))
177#define IRQ_EINT(x) S3C_EINT(x) 178#define IRQ_EINT(x) (x < 16 ? IRQ_EINT0 + x : S3C_EINT(x))
179#define IRQ_EINT_BIT(x) (x < IRQ_EINT16_31 ? x - IRQ_EINT0 : x - S3C_EINT(0))
178 180
179#define NR_IRQS (IRQ_EINT(31)+1) 181/* GPIO interrupt */
182#define S3C_IRQ_GPIO_BASE (IRQ_EINT(31) + 1)
183#define S3C_IRQ_GPIO(x) (S3C_IRQ_GPIO_BASE + (x))
184
185/*
186 * Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs
187 */
188#define NR_IRQS (S3C_IRQ_GPIO(320) + 1)
180 189
181#endif /* __ASM_PLAT_S5PC1XX_IRQS_H */ 190#endif /* __ASM_PLAT_S5PC1XX_IRQS_H */
182 191
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
index 75c8390cb827..c5cc86e92d65 100644
--- a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
+++ b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
@@ -13,68 +13,69 @@
13#ifndef __PLAT_REGS_CLOCK_H 13#ifndef __PLAT_REGS_CLOCK_H
14#define __PLAT_REGS_CLOCK_H __FILE__ 14#define __PLAT_REGS_CLOCK_H __FILE__
15 15
16#define S5PC1XX_CLKREG(x) (S5PC1XX_VA_CLK + (x)) 16#define S5PC100_CLKREG(x) (S5PC1XX_VA_CLK + (x))
17 17#define S5PC100_CLKREG_OTHER(x) (S5PC1XX_VA_CLK_OTHER + (x))
18#define S5PC1XX_APLL_LOCK S5PC1XX_CLKREG(0x00) 18
19#define S5PC1XX_MPLL_LOCK S5PC1XX_CLKREG(0x04) 19/* s5pc100 register for clock */
20#define S5PC1XX_EPLL_LOCK S5PC1XX_CLKREG(0x08) 20#define S5PC100_APLL_LOCK S5PC100_CLKREG(0x00)
21#define S5PC100_HPLL_LOCK S5PC1XX_CLKREG(0x0C) 21#define S5PC100_MPLL_LOCK S5PC100_CLKREG(0x04)
22 22#define S5PC100_EPLL_LOCK S5PC100_CLKREG(0x08)
23#define S5PC1XX_APLL_CON S5PC1XX_CLKREG(0x100) 23#define S5PC100_HPLL_LOCK S5PC100_CLKREG(0x0C)
24#define S5PC1XX_MPLL_CON S5PC1XX_CLKREG(0x104) 24
25#define S5PC1XX_EPLL_CON S5PC1XX_CLKREG(0x108) 25#define S5PC100_APLL_CON S5PC100_CLKREG(0x100)
26#define S5PC100_HPLL_CON S5PC1XX_CLKREG(0x10C) 26#define S5PC100_MPLL_CON S5PC100_CLKREG(0x104)
27 27#define S5PC100_EPLL_CON S5PC100_CLKREG(0x108)
28#define S5PC1XX_CLK_SRC0 S5PC1XX_CLKREG(0x200) 28#define S5PC100_HPLL_CON S5PC100_CLKREG(0x10C)
29#define S5PC1XX_CLK_SRC1 S5PC1XX_CLKREG(0x204) 29
30#define S5PC1XX_CLK_SRC2 S5PC1XX_CLKREG(0x208) 30#define S5PC100_CLKSRC0 S5PC100_CLKREG(0x200)
31#define S5PC1XX_CLK_SRC3 S5PC1XX_CLKREG(0x20C) 31#define S5PC100_CLKSRC1 S5PC100_CLKREG(0x204)
32 32#define S5PC100_CLKSRC2 S5PC100_CLKREG(0x208)
33#define S5PC1XX_CLK_DIV0 S5PC1XX_CLKREG(0x300) 33#define S5PC100_CLKSRC3 S5PC100_CLKREG(0x20C)
34#define S5PC1XX_CLK_DIV1 S5PC1XX_CLKREG(0x304) 34
35#define S5PC1XX_CLK_DIV2 S5PC1XX_CLKREG(0x308) 35#define S5PC100_CLKDIV0 S5PC100_CLKREG(0x300)
36#define S5PC1XX_CLK_DIV3 S5PC1XX_CLKREG(0x30C) 36#define S5PC100_CLKDIV1 S5PC100_CLKREG(0x304)
37#define S5PC1XX_CLK_DIV4 S5PC1XX_CLKREG(0x310) 37#define S5PC100_CLKDIV2 S5PC100_CLKREG(0x308)
38 38#define S5PC100_CLKDIV3 S5PC100_CLKREG(0x30C)
39#define S5PC100_CLK_OUT S5PC1XX_CLKREG(0x400) 39#define S5PC100_CLKDIV4 S5PC100_CLKREG(0x310)
40 40
41#define S5PC100_CLKGATE_D00 S5PC1XX_CLKREG(0x500) 41#define S5PC100_CLK_OUT S5PC100_CLKREG(0x400)
42#define S5PC100_CLKGATE_D01 S5PC1XX_CLKREG(0x504) 42
43#define S5PC100_CLKGATE_D02 S5PC1XX_CLKREG(0x508) 43#define S5PC100_CLKGATE_D00 S5PC100_CLKREG(0x500)
44 44#define S5PC100_CLKGATE_D01 S5PC100_CLKREG(0x504)
45#define S5PC100_CLKGATE_D10 S5PC1XX_CLKREG(0x520) 45#define S5PC100_CLKGATE_D02 S5PC100_CLKREG(0x508)
46#define S5PC100_CLKGATE_D11 S5PC1XX_CLKREG(0x524) 46
47#define S5PC100_CLKGATE_D12 S5PC1XX_CLKREG(0x528) 47#define S5PC100_CLKGATE_D10 S5PC100_CLKREG(0x520)
48#define S5PC100_CLKGATE_D13 S5PC1XX_CLKREG(0x52C) 48#define S5PC100_CLKGATE_D11 S5PC100_CLKREG(0x524)
49#define S5PC100_CLKGATE_D14 S5PC1XX_CLKREG(0x530) 49#define S5PC100_CLKGATE_D12 S5PC100_CLKREG(0x528)
50#define S5PC100_CLKGATE_D15 S5PC1XX_CLKREG(0x534) 50#define S5PC100_CLKGATE_D13 S5PC100_CLKREG(0x52C)
51 51#define S5PC100_CLKGATE_D14 S5PC100_CLKREG(0x530)
52#define S5PC100_CLKGATE_D20 S5PC1XX_CLKREG(0x540) 52#define S5PC100_CLKGATE_D15 S5PC100_CLKREG(0x534)
53 53
54#define S5PC100_SCLKGATE0 S5PC1XX_CLKREG(0x560) 54#define S5PC100_CLKGATE_D20 S5PC100_CLKREG(0x540)
55#define S5PC100_SCLKGATE1 S5PC1XX_CLKREG(0x564) 55
56 56#define S5PC100_SCLKGATE0 S5PC100_CLKREG(0x560)
57#define S5PC100_OTHERS S5PC1XX_CLKREG(0x8200) 57#define S5PC100_SCLKGATE1 S5PC100_CLKREG(0x564)
58 58
59#define S5PC1XX_EPLL_EN (1<<31) 59/* EPLL_CON */
60#define S5PC1XX_EPLL_MASK 0xffffffff 60#define S5PC100_EPLL_EN (1<<31)
61#define S5PC1XX_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s))) 61#define S5PC100_EPLL_MASK 0xffffffff
62#define S5PC100_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s)))
62 63
63/* CLKSRC0 */ 64/* CLKSRC0 */
64#define S5PC1XX_CLKSRC0_APLL_MASK (0x1<<0) 65#define S5PC100_CLKSRC0_APLL_MASK (0x1<<0)
65#define S5PC1XX_CLKSRC0_APLL_SHIFT (0) 66#define S5PC100_CLKSRC0_APLL_SHIFT (0)
66#define S5PC1XX_CLKSRC0_MPLL_MASK (0x1<<4) 67#define S5PC100_CLKSRC0_MPLL_MASK (0x1<<4)
67#define S5PC1XX_CLKSRC0_MPLL_SHIFT (4) 68#define S5PC100_CLKSRC0_MPLL_SHIFT (4)
68#define S5PC1XX_CLKSRC0_EPLL_MASK (0x1<<8) 69#define S5PC100_CLKSRC0_EPLL_MASK (0x1<<8)
69#define S5PC1XX_CLKSRC0_EPLL_SHIFT (8) 70#define S5PC100_CLKSRC0_EPLL_SHIFT (8)
70#define S5PC100_CLKSRC0_HPLL_MASK (0x1<<12) 71#define S5PC100_CLKSRC0_HPLL_MASK (0x1<<12)
71#define S5PC100_CLKSRC0_HPLL_SHIFT (12) 72#define S5PC100_CLKSRC0_HPLL_SHIFT (12)
72#define S5PC100_CLKSRC0_AMMUX_MASK (0x1<<16) 73#define S5PC100_CLKSRC0_AMMUX_MASK (0x1<<16)
73#define S5PC100_CLKSRC0_AMMUX_SHIFT (16) 74#define S5PC100_CLKSRC0_AMMUX_SHIFT (16)
74#define S5PC100_CLKSRC0_HREF_MASK (0x1<<20) 75#define S5PC100_CLKSRC0_HREF_MASK (0x1<<20)
75#define S5PC100_CLKSRC0_HREF_SHIFT (20) 76#define S5PC100_CLKSRC0_HREF_SHIFT (20)
76#define S5PC1XX_CLKSRC0_ONENAND_MASK (0x1<<24) 77#define S5PC100_CLKSRC0_ONENAND_MASK (0x1<<24)
77#define S5PC1XX_CLKSRC0_ONENAND_SHIFT (24) 78#define S5PC100_CLKSRC0_ONENAND_SHIFT (24)
78 79
79 80
80/* CLKSRC1 */ 81/* CLKSRC1 */
@@ -127,10 +128,9 @@
127#define S5PC100_CLKSRC3_SPDIF_MASK (0x3<<24) 128#define S5PC100_CLKSRC3_SPDIF_MASK (0x3<<24)
128#define S5PC100_CLKSRC3_SPDIF_SHIFT (24) 129#define S5PC100_CLKSRC3_SPDIF_SHIFT (24)
129 130
130
131/* CLKDIV0 */ 131/* CLKDIV0 */
132#define S5PC1XX_CLKDIV0_APLL_MASK (0x1<<0) 132#define S5PC100_CLKDIV0_APLL_MASK (0x1<<0)
133#define S5PC1XX_CLKDIV0_APLL_SHIFT (0) 133#define S5PC100_CLKDIV0_APLL_SHIFT (0)
134#define S5PC100_CLKDIV0_ARM_MASK (0x7<<4) 134#define S5PC100_CLKDIV0_ARM_MASK (0x7<<4)
135#define S5PC100_CLKDIV0_ARM_SHIFT (4) 135#define S5PC100_CLKDIV0_ARM_SHIFT (4)
136#define S5PC100_CLKDIV0_D0_MASK (0x7<<8) 136#define S5PC100_CLKDIV0_D0_MASK (0x7<<8)
@@ -141,8 +141,8 @@
141#define S5PC100_CLKDIV0_SECSS_SHIFT (16) 141#define S5PC100_CLKDIV0_SECSS_SHIFT (16)
142 142
143/* CLKDIV1 */ 143/* CLKDIV1 */
144#define S5PC100_CLKDIV1_AM_MASK (0x7<<0) 144#define S5PC100_CLKDIV1_APLL2_MASK (0x7<<0)
145#define S5PC100_CLKDIV1_AM_SHIFT (0) 145#define S5PC100_CLKDIV1_APLL2_SHIFT (0)
146#define S5PC100_CLKDIV1_MPLL_MASK (0x3<<4) 146#define S5PC100_CLKDIV1_MPLL_MASK (0x3<<4)
147#define S5PC100_CLKDIV1_MPLL_SHIFT (4) 147#define S5PC100_CLKDIV1_MPLL_SHIFT (4)
148#define S5PC100_CLKDIV1_MPLL2_MASK (0x1<<8) 148#define S5PC100_CLKDIV1_MPLL2_MASK (0x1<<8)
@@ -202,7 +202,6 @@
202#define S5PC100_CLKDIV4_AUDIO2_MASK (0xf<<20) 202#define S5PC100_CLKDIV4_AUDIO2_MASK (0xf<<20)
203#define S5PC100_CLKDIV4_AUDIO2_SHIFT (20) 203#define S5PC100_CLKDIV4_AUDIO2_SHIFT (20)
204 204
205
206/* HCLKD0/PCLKD0 Clock Gate 0 Registers */ 205/* HCLKD0/PCLKD0 Clock Gate 0 Registers */
207#define S5PC100_CLKGATE_D00_INTC (1<<0) 206#define S5PC100_CLKGATE_D00_INTC (1<<0)
208#define S5PC100_CLKGATE_D00_TZIC (1<<1) 207#define S5PC100_CLKGATE_D00_TZIC (1<<1)
@@ -295,8 +294,8 @@
295#define S5PC100_CLKGATE_D20_I2SD2 (1<<1) 294#define S5PC100_CLKGATE_D20_I2SD2 (1<<1)
296 295
297/* Special Clock Gate 0 Registers */ 296/* Special Clock Gate 0 Registers */
298#define S5PC1XX_CLKGATE_SCLK0_HPM (1<<0) 297#define S5PC100_CLKGATE_SCLK0_HPM (1<<0)
299#define S5PC1XX_CLKGATE_SCLK0_PWI (1<<1) 298#define S5PC100_CLKGATE_SCLK0_PWI (1<<1)
300#define S5PC100_CLKGATE_SCLK0_ONENAND (1<<2) 299#define S5PC100_CLKGATE_SCLK0_ONENAND (1<<2)
301#define S5PC100_CLKGATE_SCLK0_UART (1<<3) 300#define S5PC100_CLKGATE_SCLK0_UART (1<<3)
302#define S5PC100_CLKGATE_SCLK0_SPI0 (1<<4) 301#define S5PC100_CLKGATE_SCLK0_SPI0 (1<<4)
@@ -329,89 +328,28 @@
329#define S5PC100_CLKGATE_SCLK1_SPDIF (1<<11) 328#define S5PC100_CLKGATE_SCLK1_SPDIF (1<<11)
330#define S5PC100_CLKGATE_SCLK1_CAM (1<<12) 329#define S5PC100_CLKGATE_SCLK1_CAM (1<<12)
331 330
332/* register for power management */ 331#define S5PC100_SWRESET S5PC100_CLKREG_OTHER(0x000)
333#define S5PC100_PWR_CFG S5PC1XX_CLKREG(0x8000) 332#define S5PC100_OND_SWRESET S5PC100_CLKREG_OTHER(0x008)
334#define S5PC100_EINT_WAKEUP_MASK S5PC1XX_CLKREG(0x8004) 333#define S5PC100_GEN_CTRL S5PC100_CLKREG_OTHER(0x100)
335#define S5PC100_NORMAL_CFG S5PC1XX_CLKREG(0x8010) 334#define S5PC100_GEN_STATUS S5PC100_CLKREG_OTHER(0x104)
336#define S5PC100_STOP_CFG S5PC1XX_CLKREG(0x8014) 335#define S5PC100_MEM_SYS_CFG S5PC100_CLKREG_OTHER(0x200)
337#define S5PC100_SLEEP_CFG S5PC1XX_CLKREG(0x8018) 336#define S5PC100_CAM_MUX_SEL S5PC100_CLKREG_OTHER(0x300)
338#define S5PC100_STOP_MEM_CFG S5PC1XX_CLKREG(0x801C) 337#define S5PC100_MIXER_OUT_SEL S5PC100_CLKREG_OTHER(0x304)
339#define S5PC100_OSC_FREQ S5PC1XX_CLKREG(0x8100) 338#define S5PC100_LPMP_MODE_SEL S5PC100_CLKREG_OTHER(0x308)
340#define S5PC100_OSC_STABLE S5PC1XX_CLKREG(0x8104) 339#define S5PC100_MIPI_PHY_CON0 S5PC100_CLKREG_OTHER(0x400)
341#define S5PC100_PWR_STABLE S5PC1XX_CLKREG(0x8108) 340#define S5PC100_MIPI_PHY_CON1 S5PC100_CLKREG_OTHER(0x414)
342#define S5PC100_MTC_STABLE S5PC1XX_CLKREG(0x8110) 341#define S5PC100_HDMI_PHY_CON0 S5PC100_CLKREG_OTHER(0x420)
343#define S5PC100_CLAMP_STABLE S5PC1XX_CLKREG(0x8114) 342
344#define S5PC100_OTHERS S5PC1XX_CLKREG(0x8200) 343#define S5PC100_SWRESET_RESETVAL 0xc100
345#define S5PC100_RST_STAT S5PC1XX_CLKREG(0x8300)
346#define S5PC100_WAKEUP_STAT S5PC1XX_CLKREG(0x8304)
347#define S5PC100_BLK_PWR_STAT S5PC1XX_CLKREG(0x8308)
348#define S5PC100_INFORM0 S5PC1XX_CLKREG(0x8400)
349#define S5PC100_INFORM1 S5PC1XX_CLKREG(0x8404)
350#define S5PC100_INFORM2 S5PC1XX_CLKREG(0x8408)
351#define S5PC100_INFORM3 S5PC1XX_CLKREG(0x840C)
352#define S5PC100_INFORM4 S5PC1XX_CLKREG(0x8410)
353#define S5PC100_INFORM5 S5PC1XX_CLKREG(0x8414)
354#define S5PC100_INFORM6 S5PC1XX_CLKREG(0x8418)
355#define S5PC100_INFORM7 S5PC1XX_CLKREG(0x841C)
356#define S5PC100_DCGIDX_MAP0 S5PC1XX_CLKREG(0x8500)
357#define S5PC100_DCGIDX_MAP1 S5PC1XX_CLKREG(0x8504)
358#define S5PC100_DCGIDX_MAP2 S5PC1XX_CLKREG(0x8508)
359#define S5PC100_DCGPERF_MAP0 S5PC1XX_CLKREG(0x850C)
360#define S5PC100_DCGPERF_MAP1 S5PC1XX_CLKREG(0x8510)
361#define S5PC100_DVCIDX_MAP S5PC1XX_CLKREG(0x8514)
362#define S5PC100_FREQ_CPU S5PC1XX_CLKREG(0x8518)
363#define S5PC100_FREQ_DPM S5PC1XX_CLKREG(0x851C)
364#define S5PC100_DVSEMCLK_EN S5PC1XX_CLKREG(0x8520)
365#define S5PC100_APLL_CON_L8 S5PC1XX_CLKREG(0x8600)
366#define S5PC100_APLL_CON_L7 S5PC1XX_CLKREG(0x8604)
367#define S5PC100_APLL_CON_L6 S5PC1XX_CLKREG(0x8608)
368#define S5PC100_APLL_CON_L5 S5PC1XX_CLKREG(0x860C)
369#define S5PC100_APLL_CON_L4 S5PC1XX_CLKREG(0x8610)
370#define S5PC100_APLL_CON_L3 S5PC1XX_CLKREG(0x8614)
371#define S5PC100_APLL_CON_L2 S5PC1XX_CLKREG(0x8618)
372#define S5PC100_APLL_CON_L1 S5PC1XX_CLKREG(0x861C)
373#define S5PC100_IEM_CONTROL S5PC1XX_CLKREG(0x8620)
374#define S5PC100_CLKDIV_IEM_L8 S5PC1XX_CLKREG(0x8700)
375#define S5PC100_CLKDIV_IEM_L7 S5PC1XX_CLKREG(0x8704)
376#define S5PC100_CLKDIV_IEM_L6 S5PC1XX_CLKREG(0x8708)
377#define S5PC100_CLKDIV_IEM_L5 S5PC1XX_CLKREG(0x870C)
378#define S5PC100_CLKDIV_IEM_L4 S5PC1XX_CLKREG(0x8710)
379#define S5PC100_CLKDIV_IEM_L3 S5PC1XX_CLKREG(0x8714)
380#define S5PC100_CLKDIV_IEM_L2 S5PC1XX_CLKREG(0x8718)
381#define S5PC100_CLKDIV_IEM_L1 S5PC1XX_CLKREG(0x871C)
382#define S5PC100_IEM_HPMCLK_DIV S5PC1XX_CLKREG(0x8724)
383
384#define S5PC100_SWRESET S5PC1XX_CLKREG(0x100000)
385#define S5PC100_OND_SWRESET S5PC1XX_CLKREG(0x100008)
386#define S5PC100_GEN_CTRL S5PC1XX_CLKREG(0x100100)
387#define S5PC100_GEN_STATUS S5PC1XX_CLKREG(0x100104)
388#define S5PC100_MEM_SYS_CFG S5PC1XX_CLKREG(0x100200)
389#define S5PC100_CAM_MUX_SEL S5PC1XX_CLKREG(0x100300)
390#define S5PC100_MIXER_OUT_SEL S5PC1XX_CLKREG(0x100304)
391#define S5PC100_LPMP_MODE_SEL S5PC1XX_CLKREG(0x100308)
392#define S5PC100_MIPI_PHY_CON0 S5PC1XX_CLKREG(0x100400)
393#define S5PC100_MIPI_PHY_CON1 S5PC1XX_CLKREG(0x100414)
394#define S5PC100_HDMI_PHY_CON0 S5PC1XX_CLKREG(0x100420)
395
396#define S5PC100_CFG_WFI_CLEAN (~(3<<5))
397#define S5PC100_CFG_WFI_IDLE (1<<5)
398#define S5PC100_CFG_WFI_STOP (2<<5)
399#define S5PC100_CFG_WFI_SLEEP (3<<5)
400
401#define S5PC100_OTHER_SYS_INT 24 344#define S5PC100_OTHER_SYS_INT 24
402#define S5PC100_OTHER_STA_TYPE 23 345#define S5PC100_OTHER_STA_TYPE 23
403#define STA_TYPE_EXPON 0 346#define STA_TYPE_EXPON 0
404#define STA_TYPE_SFR 1 347#define STA_TYPE_SFR 1
405 348
406#define S5PC100_PWR_STA_EXP_SCALE 0
407#define S5PC100_PWR_STA_CNT 4
408
409#define S5PC100_PWR_STABLE_COUNT 85500
410
411#define S5PC100_SLEEP_CFG_OSC_EN 0 349#define S5PC100_SLEEP_CFG_OSC_EN 0
412 350
413/* OTHERS Resgister */ 351/* OTHERS Resgister */
414#define S5PC100_OTHERS_USB_SIG_MASK (1 << 16) 352#define S5PC100_OTHERS_USB_SIG_MASK (1 << 16)
415#define S5PC100_OTHERS_MIPI_DPHY_EN (1 << 28) 353#define S5PC100_OTHERS_MIPI_DPHY_EN (1 << 28)
416 354
417/* MIPI D-PHY Control Register 0 */ 355/* MIPI D-PHY Control Register 0 */
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h b/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h
new file mode 100644
index 000000000000..43c7bc8bf784
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h
@@ -0,0 +1,70 @@
1/* linux/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 * S5PC1XX - GPIO register definitions
7 */
8
9#ifndef __ASM_PLAT_S5PC1XX_REGS_GPIO_H
10#define __ASM_PLAT_S5PC1XX_REGS_GPIO_H __FILE__
11
12#include <mach/map.h>
13
14/* S5PC100 */
15#define S5PC100_GPIO_BASE S5PC1XX_VA_GPIO
16#define S5PC100_GPA0_BASE (S5PC100_GPIO_BASE + 0x0000)
17#define S5PC100_GPA1_BASE (S5PC100_GPIO_BASE + 0x0020)
18#define S5PC100_GPB_BASE (S5PC100_GPIO_BASE + 0x0040)
19#define S5PC100_GPC_BASE (S5PC100_GPIO_BASE + 0x0060)
20#define S5PC100_GPD_BASE (S5PC100_GPIO_BASE + 0x0080)
21#define S5PC100_GPE0_BASE (S5PC100_GPIO_BASE + 0x00A0)
22#define S5PC100_GPE1_BASE (S5PC100_GPIO_BASE + 0x00C0)
23#define S5PC100_GPF0_BASE (S5PC100_GPIO_BASE + 0x00E0)
24#define S5PC100_GPF1_BASE (S5PC100_GPIO_BASE + 0x0100)
25#define S5PC100_GPF2_BASE (S5PC100_GPIO_BASE + 0x0120)
26#define S5PC100_GPF3_BASE (S5PC100_GPIO_BASE + 0x0140)
27#define S5PC100_GPG0_BASE (S5PC100_GPIO_BASE + 0x0160)
28#define S5PC100_GPG1_BASE (S5PC100_GPIO_BASE + 0x0180)
29#define S5PC100_GPG2_BASE (S5PC100_GPIO_BASE + 0x01A0)
30#define S5PC100_GPG3_BASE (S5PC100_GPIO_BASE + 0x01C0)
31#define S5PC100_GPH0_BASE (S5PC100_GPIO_BASE + 0x0C00)
32#define S5PC100_GPH1_BASE (S5PC100_GPIO_BASE + 0x0C20)
33#define S5PC100_GPH2_BASE (S5PC100_GPIO_BASE + 0x0C40)
34#define S5PC100_GPH3_BASE (S5PC100_GPIO_BASE + 0x0C60)
35#define S5PC100_GPI_BASE (S5PC100_GPIO_BASE + 0x01E0)
36#define S5PC100_GPJ0_BASE (S5PC100_GPIO_BASE + 0x0200)
37#define S5PC100_GPJ1_BASE (S5PC100_GPIO_BASE + 0x0220)
38#define S5PC100_GPJ2_BASE (S5PC100_GPIO_BASE + 0x0240)
39#define S5PC100_GPJ3_BASE (S5PC100_GPIO_BASE + 0x0260)
40#define S5PC100_GPJ4_BASE (S5PC100_GPIO_BASE + 0x0280)
41#define S5PC100_GPK0_BASE (S5PC100_GPIO_BASE + 0x02A0)
42#define S5PC100_GPK1_BASE (S5PC100_GPIO_BASE + 0x02C0)
43#define S5PC100_GPK2_BASE (S5PC100_GPIO_BASE + 0x02E0)
44#define S5PC100_GPK3_BASE (S5PC100_GPIO_BASE + 0x0300)
45#define S5PC100_GPL0_BASE (S5PC100_GPIO_BASE + 0x0320)
46#define S5PC100_GPL1_BASE (S5PC100_GPIO_BASE + 0x0340)
47#define S5PC100_GPL2_BASE (S5PC100_GPIO_BASE + 0x0360)
48#define S5PC100_GPL3_BASE (S5PC100_GPIO_BASE + 0x0380)
49#define S5PC100_GPL4_BASE (S5PC100_GPIO_BASE + 0x03A0)
50#define S5PC100_EINT_BASE (S5PC100_GPIO_BASE + 0x0E00)
51
52#define S5PC100_UHOST (S5PC100_GPIO_BASE + 0x0B68)
53#define S5PC100_PDNEN (S5PC100_GPIO_BASE + 0x0F80)
54
55/* PDNEN */
56#define S5PC100_PDNEN_CFG_PDNEN (1 << 1)
57#define S5PC100_PDNEN_CFG_AUTO (0 << 1)
58#define S5PC100_PDNEN_POWERDOWN (1 << 0)
59#define S5PC100_PDNEN_NORMAL (0 << 0)
60
61/* Common part */
62/* External interrupt base is same at both s5pc100 and s5pc110 */
63#define S5PC1XX_EINT_BASE (S5PC100_EINT_BASE)
64
65#define S5PC100_GPx_INPUT(__gpio) (0x0 << ((__gpio) * 4))
66#define S5PC100_GPx_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
67#define S5PC100_GPx_CONMASK(__gpio) (0xf << ((__gpio) * 4))
68
69#endif /* __ASM_PLAT_S5PC1XX_REGS_GPIO_H */
70
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-power.h b/arch/arm/plat-s5pc1xx/include/plat/regs-power.h
new file mode 100644
index 000000000000..02ffa491b53a
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/include/plat/regs-power.h
@@ -0,0 +1,84 @@
1/* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Jongse Won <jongse.won@samsung.com>
5 *
6 * S5PC1XX clock register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARM_REGS_PWR
14#define __ASM_ARM_REGS_PWR __FILE__
15
16#define S5PC1XX_PWRREG(x) (S5PC1XX_VA_PWR + (x))
17
18/* s5pc100 (0xE0108000) register for power management */
19#define S5PC100_PWR_CFG S5PC1XX_PWRREG(0x0)
20#define S5PC100_EINT_WAKEUP_MASK S5PC1XX_PWRREG(0x4)
21#define S5PC100_NORMAL_CFG S5PC1XX_PWRREG(0x10)
22#define S5PC100_STOP_CFG S5PC1XX_PWRREG(0x14)
23#define S5PC100_SLEEP_CFG S5PC1XX_PWRREG(0x18)
24#define S5PC100_STOP_MEM_CFG S5PC1XX_PWRREG(0x1C)
25#define S5PC100_OSC_FREQ S5PC1XX_PWRREG(0x100)
26#define S5PC100_OSC_STABLE S5PC1XX_PWRREG(0x104)
27#define S5PC100_PWR_STABLE S5PC1XX_PWRREG(0x108)
28#define S5PC100_MTC_STABLE S5PC1XX_PWRREG(0x110)
29#define S5PC100_CLAMP_STABLE S5PC1XX_PWRREG(0x114)
30#define S5PC100_OTHERS S5PC1XX_PWRREG(0x200)
31#define S5PC100_RST_STAT S5PC1XX_PWRREG(0x300)
32#define S5PC100_WAKEUP_STAT S5PC1XX_PWRREG(0x304)
33#define S5PC100_BLK_PWR_STAT S5PC1XX_PWRREG(0x308)
34#define S5PC100_INFORM0 S5PC1XX_PWRREG(0x400)
35#define S5PC100_INFORM1 S5PC1XX_PWRREG(0x404)
36#define S5PC100_INFORM2 S5PC1XX_PWRREG(0x408)
37#define S5PC100_INFORM3 S5PC1XX_PWRREG(0x40C)
38#define S5PC100_INFORM4 S5PC1XX_PWRREG(0x410)
39#define S5PC100_INFORM5 S5PC1XX_PWRREG(0x414)
40#define S5PC100_INFORM6 S5PC1XX_PWRREG(0x418)
41#define S5PC100_INFORM7 S5PC1XX_PWRREG(0x41C)
42#define S5PC100_DCGIDX_MAP0 S5PC1XX_PWRREG(0x500)
43#define S5PC100_DCGIDX_MAP1 S5PC1XX_PWRREG(0x504)
44#define S5PC100_DCGIDX_MAP2 S5PC1XX_PWRREG(0x508)
45#define S5PC100_DCGPERF_MAP0 S5PC1XX_PWRREG(0x50C)
46#define S5PC100_DCGPERF_MAP1 S5PC1XX_PWRREG(0x510)
47#define S5PC100_DVCIDX_MAP S5PC1XX_PWRREG(0x514)
48#define S5PC100_FREQ_CPU S5PC1XX_PWRREG(0x518)
49#define S5PC100_FREQ_DPM S5PC1XX_PWRREG(0x51C)
50#define S5PC100_DVSEMCLK_EN S5PC1XX_PWRREG(0x520)
51#define S5PC100_APLL_CON_L8 S5PC1XX_PWRREG(0x600)
52#define S5PC100_APLL_CON_L7 S5PC1XX_PWRREG(0x604)
53#define S5PC100_APLL_CON_L6 S5PC1XX_PWRREG(0x608)
54#define S5PC100_APLL_CON_L5 S5PC1XX_PWRREG(0x60C)
55#define S5PC100_APLL_CON_L4 S5PC1XX_PWRREG(0x610)
56#define S5PC100_APLL_CON_L3 S5PC1XX_PWRREG(0x614)
57#define S5PC100_APLL_CON_L2 S5PC1XX_PWRREG(0x618)
58#define S5PC100_APLL_CON_L1 S5PC1XX_PWRREG(0x61C)
59#define S5PC100_IEM_CONTROL S5PC1XX_PWRREG(0x620)
60#define S5PC100_CLKDIV_IEM_L8 S5PC1XX_PWRREG(0x700)
61#define S5PC100_CLKDIV_IEM_L7 S5PC1XX_PWRREG(0x704)
62#define S5PC100_CLKDIV_IEM_L6 S5PC1XX_PWRREG(0x708)
63#define S5PC100_CLKDIV_IEM_L5 S5PC1XX_PWRREG(0x70C)
64#define S5PC100_CLKDIV_IEM_L4 S5PC1XX_PWRREG(0x710)
65#define S5PC100_CLKDIV_IEM_L3 S5PC1XX_PWRREG(0x714)
66#define S5PC100_CLKDIV_IEM_L2 S5PC1XX_PWRREG(0x718)
67#define S5PC100_CLKDIV_IEM_L1 S5PC1XX_PWRREG(0x71C)
68#define S5PC100_IEM_HPMCLK_DIV S5PC1XX_PWRREG(0x724)
69
70/* PWR_CFG */
71#define S5PC100_PWRCFG_CFG_DEEP_IDLE (1 << 31)
72#define S5PC100_PWRCFG_CFG_WFI_MASK (3 << 5)
73#define S5PC100_PWRCFG_CFG_WFI_IDLE (0 << 5)
74#define S5PC100_PWRCFG_CFG_WFI_DEEP_IDLE (1 << 5)
75#define S5PC100_PWRCFG_CFG_WFI_STOP (2 << 5)
76#define S5PC100_PWRCFG_CFG_WFI_SLEEP (3 << 5)
77
78/* SLEEP_CFG */
79#define S5PC100_SLEEP_OSC_EN_SLEEP (1 << 0)
80
81/* OTHERS */
82#define S5PC100_PMU_INT_DISABLE (1 << 24)
83
84#endif /* __ASM_ARM_REGS_PWR */
diff --git a/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h b/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
index 45e275131665..2531f34a56f3 100644
--- a/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
+++ b/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
@@ -35,10 +35,9 @@ extern struct clk clk_hpll;
35extern struct clk clk_hd0; 35extern struct clk clk_hd0;
36extern struct clk clk_pd0; 36extern struct clk clk_pd0;
37extern struct clk clk_54m; 37extern struct clk clk_54m;
38extern struct clk clk_dout_mpll2;
39extern void s5pc1xx_register_clocks(void); 38extern void s5pc1xx_register_clocks(void);
40extern int s5pc1xx_sclk0_ctrl(struct clk *clk, int enable); 39extern int s5pc100_sclk0_ctrl(struct clk *clk, int enable);
41extern int s5pc1xx_sclk1_ctrl(struct clk *clk, int enable); 40extern int s5pc100_sclk1_ctrl(struct clk *clk, int enable);
42 41
43/* Some day, belows will be moved to plat-s5pc/include/plat/devs.h */ 42/* Some day, belows will be moved to plat-s5pc/include/plat/devs.h */
44extern struct s3c24xx_uart_resources s5pc1xx_uart_resources[]; 43extern struct s3c24xx_uart_resources s5pc1xx_uart_resources[];
diff --git a/arch/arm/plat-s5pc1xx/irq-eint.c b/arch/arm/plat-s5pc1xx/irq-eint.c
new file mode 100644
index 000000000000..373122f57d56
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/irq-eint.c
@@ -0,0 +1,281 @@
1/*
2 * linux/arch/arm/plat-s5pc1xx/irq-eint.c
3 *
4 * Copyright 2009 Samsung Electronics Co.
5 * Byungho Min <bhmin@samsung.com>
6 * Kyungin Park <kyungmin.park@samsung.com>
7 *
8 * Based on plat-s3c64xx/irq-eint.c
9 *
10 * S5PC1XX - Interrupt handling for IRQ_EINT(x)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/kernel.h>
18#include <linux/interrupt.h>
19#include <linux/irq.h>
20#include <linux/io.h>
21#include <linux/sysdev.h>
22#include <linux/pm.h>
23#include <linux/gpio.h>
24
25#include <asm/hardware/vic.h>
26
27#include <mach/map.h>
28
29#include <plat/gpio-cfg.h>
30#include <plat/gpio-ext.h>
31#include <plat/pm.h>
32#include <plat/regs-gpio.h>
33#include <plat/regs-irqtype.h>
34
35/*
36 * bank is a group of external interrupt
37 * bank0 means EINT0 ... EINT7
38 * bank1 means EINT8 ... EINT15
39 * bank2 means EINT16 ... EINT23
40 * bank3 means EINT24 ... EINT31
41 */
42
43static inline int s3c_get_eint(unsigned int irq)
44{
45 int real;
46
47 if (irq < IRQ_EINT16_31)
48 real = (irq - IRQ_EINT0);
49 else
50 real = (irq - S3C_IRQ_EINT_BASE) + IRQ_EINT16_31 - IRQ_EINT0;
51
52 return real;
53}
54
55static inline int s3c_get_bank(unsigned int irq)
56{
57 return s3c_get_eint(irq) >> 3;
58}
59
60static inline int s3c_eint_to_bit(unsigned int irq)
61{
62 int real, bit;
63
64 real = s3c_get_eint(irq);
65 bit = 1 << (real & (8 - 1));
66
67 return bit;
68}
69
70static inline void s3c_irq_eint_mask(unsigned int irq)
71{
72 u32 mask;
73 u32 bank = s3c_get_bank(irq);
74
75 mask = __raw_readl(S5PC1XX_WKUP_INT_MASK(bank));
76 mask |= s3c_eint_to_bit(irq);
77 __raw_writel(mask, S5PC1XX_WKUP_INT_MASK(bank));
78}
79
80static void s3c_irq_eint_unmask(unsigned int irq)
81{
82 u32 mask;
83 u32 bank = s3c_get_bank(irq);
84
85 mask = __raw_readl(S5PC1XX_WKUP_INT_MASK(bank));
86 mask &= ~(s3c_eint_to_bit(irq));
87 __raw_writel(mask, S5PC1XX_WKUP_INT_MASK(bank));
88}
89
90static inline void s3c_irq_eint_ack(unsigned int irq)
91{
92 u32 bank = s3c_get_bank(irq);
93
94 __raw_writel(s3c_eint_to_bit(irq), S5PC1XX_WKUP_INT_PEND(bank));
95}
96
97static void s3c_irq_eint_maskack(unsigned int irq)
98{
99 /* compiler should in-line these */
100 s3c_irq_eint_mask(irq);
101 s3c_irq_eint_ack(irq);
102}
103
104static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
105{
106 u32 bank = s3c_get_bank(irq);
107 int real = s3c_get_eint(irq);
108 int gpio, shift, sfn;
109 u32 ctrl, con = 0;
110
111 switch (type) {
112 case IRQ_TYPE_NONE:
113 printk(KERN_WARNING "No edge setting!\n");
114 break;
115
116 case IRQ_TYPE_EDGE_RISING:
117 con = S5PC1XX_WKUP_INT_RISEEDGE;
118 break;
119
120 case IRQ_TYPE_EDGE_FALLING:
121 con = S5PC1XX_WKUP_INT_FALLEDGE;
122 break;
123
124 case IRQ_TYPE_EDGE_BOTH:
125 con = S5PC1XX_WKUP_INT_BOTHEDGE;
126 break;
127
128 case IRQ_TYPE_LEVEL_LOW:
129 con = S5PC1XX_WKUP_INT_LOWLEV;
130 break;
131
132 case IRQ_TYPE_LEVEL_HIGH:
133 con = S5PC1XX_WKUP_INT_HILEV;
134 break;
135
136 default:
137 printk(KERN_ERR "No such irq type %d", type);
138 return -EINVAL;
139 }
140
141 gpio = real & (8 - 1);
142 shift = gpio << 2;
143
144 ctrl = __raw_readl(S5PC1XX_WKUP_INT_CON(bank));
145 ctrl &= ~(0x7 << shift);
146 ctrl |= con << shift;
147 __raw_writel(ctrl, S5PC1XX_WKUP_INT_CON(bank));
148
149 switch (real) {
150 case 0 ... 7:
151 gpio = S5PC100_GPH0(gpio);
152 break;
153 case 8 ... 15:
154 gpio = S5PC100_GPH1(gpio);
155 break;
156 case 16 ... 23:
157 gpio = S5PC100_GPH2(gpio);
158 break;
159 case 24 ... 31:
160 gpio = S5PC100_GPH3(gpio);
161 break;
162 default:
163 return -EINVAL;
164 }
165
166 sfn = S3C_GPIO_SFN(0x2);
167 s3c_gpio_cfgpin(gpio, sfn);
168
169 return 0;
170}
171
172static struct irq_chip s3c_irq_eint = {
173 .name = "EINT",
174 .mask = s3c_irq_eint_mask,
175 .unmask = s3c_irq_eint_unmask,
176 .mask_ack = s3c_irq_eint_maskack,
177 .ack = s3c_irq_eint_ack,
178 .set_type = s3c_irq_eint_set_type,
179 .set_wake = s3c_irqext_wake,
180};
181
182/* s3c_irq_demux_eint
183 *
184 * This function demuxes the IRQ from external interrupts,
185 * from IRQ_EINT(16) to IRQ_EINT(31). It is designed to be inlined into
186 * the specific handlers s3c_irq_demux_eintX_Y.
187 */
188static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
189{
190 u32 status = __raw_readl(S5PC1XX_WKUP_INT_PEND((start >> 3)));
191 u32 mask = __raw_readl(S5PC1XX_WKUP_INT_MASK((start >> 3)));
192 unsigned int irq;
193
194 status &= ~mask;
195 status &= (1 << (end - start + 1)) - 1;
196
197 for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
198 if (status & 1)
199 generic_handle_irq(irq);
200
201 status >>= 1;
202 }
203}
204
205static void s3c_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
206{
207 s3c_irq_demux_eint(16, 23);
208 s3c_irq_demux_eint(24, 31);
209}
210
211/*
212 * Handle EINT0 ... EINT15 at VIC directly
213 */
214static void s3c_irq_vic_eint_mask(unsigned int irq)
215{
216 void __iomem *base = get_irq_chip_data(irq);
217 unsigned int real;
218
219 s3c_irq_eint_mask(irq);
220 real = s3c_get_eint(irq);
221 writel(1 << real, base + VIC_INT_ENABLE_CLEAR);
222}
223
224static void s3c_irq_vic_eint_unmask(unsigned int irq)
225{
226 void __iomem *base = get_irq_chip_data(irq);
227 unsigned int real;
228
229 s3c_irq_eint_unmask(irq);
230 real = s3c_get_eint(irq);
231 writel(1 << real, base + VIC_INT_ENABLE);
232}
233
234static inline void s3c_irq_vic_eint_ack(unsigned int irq)
235{
236 u32 bit;
237 u32 bank = s3c_get_bank(irq);
238
239 bit = s3c_eint_to_bit(irq);
240 __raw_writel(bit, S5PC1XX_WKUP_INT_PEND(bank));
241}
242
243static void s3c_irq_vic_eint_maskack(unsigned int irq)
244{
245 /* compiler should in-line these */
246 s3c_irq_vic_eint_mask(irq);
247 s3c_irq_vic_eint_ack(irq);
248}
249
250static struct irq_chip s3c_irq_vic_eint = {
251 .name = "EINT",
252 .mask = s3c_irq_vic_eint_mask,
253 .unmask = s3c_irq_vic_eint_unmask,
254 .mask_ack = s3c_irq_vic_eint_maskack,
255 .ack = s3c_irq_vic_eint_ack,
256 .set_type = s3c_irq_eint_set_type,
257 .set_wake = s3c_irqext_wake,
258};
259
260static int __init s5pc1xx_init_irq_eint(void)
261{
262 int irq;
263
264 for (irq = IRQ_EINT0; irq <= IRQ_EINT15; irq++) {
265 set_irq_chip(irq, &s3c_irq_vic_eint);
266 set_irq_handler(irq, handle_level_irq);
267 set_irq_flags(irq, IRQF_VALID);
268 }
269
270 for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) {
271 set_irq_chip(irq, &s3c_irq_eint);
272 set_irq_handler(irq, handle_level_irq);
273 set_irq_flags(irq, IRQF_VALID);
274 }
275
276 set_irq_chained_handler(IRQ_EINT16_31, s3c_irq_demux_eint16_31);
277
278 return 0;
279}
280
281arch_initcall(s5pc1xx_init_irq_eint);
diff --git a/arch/arm/plat-s5pc1xx/irq-gpio.c b/arch/arm/plat-s5pc1xx/irq-gpio.c
new file mode 100644
index 000000000000..fecca7a679b0
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/irq-gpio.c
@@ -0,0 +1,266 @@
1/*
2 * arch/arm/plat-s5pc1xx/irq-gpio.c
3 *
4 * Copyright (C) 2009 Samsung Electronics
5 *
6 * S5PC1XX - Interrupt handling for IRQ_GPIO${group}(x)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17#include <linux/gpio.h>
18
19#include <mach/map.h>
20#include <plat/gpio-cfg.h>
21
22#define S5PC1XX_GPIOREG(x) (S5PC1XX_VA_GPIO + (x))
23
24#define CON_OFFSET 0x700
25#define MASK_OFFSET 0x900
26#define PEND_OFFSET 0xA00
27#define CON_OFFSET_2 0xE00
28#define MASK_OFFSET_2 0xF00
29#define PEND_OFFSET_2 0xF40
30
31#define GPIOINT_LEVEL_LOW 0x0
32#define GPIOINT_LEVEL_HIGH 0x1
33#define GPIOINT_EDGE_FALLING 0x2
34#define GPIOINT_EDGE_RISING 0x3
35#define GPIOINT_EDGE_BOTH 0x4
36
37static int group_to_con_offset(int group)
38{
39 return group << 2;
40}
41
42static int group_to_mask_offset(int group)
43{
44 return group << 2;
45}
46
47static int group_to_pend_offset(int group)
48{
49 return group << 2;
50}
51
52static int s5pc1xx_get_start(unsigned int group)
53{
54 switch (group) {
55 case 0: return S5PC100_GPIO_A0_START;
56 case 1: return S5PC100_GPIO_A1_START;
57 case 2: return S5PC100_GPIO_B_START;
58 case 3: return S5PC100_GPIO_C_START;
59 case 4: return S5PC100_GPIO_D_START;
60 case 5: return S5PC100_GPIO_E0_START;
61 case 6: return S5PC100_GPIO_E1_START;
62 case 7: return S5PC100_GPIO_F0_START;
63 case 8: return S5PC100_GPIO_F1_START;
64 case 9: return S5PC100_GPIO_F2_START;
65 case 10: return S5PC100_GPIO_F3_START;
66 case 11: return S5PC100_GPIO_G0_START;
67 case 12: return S5PC100_GPIO_G1_START;
68 case 13: return S5PC100_GPIO_G2_START;
69 case 14: return S5PC100_GPIO_G3_START;
70 case 15: return S5PC100_GPIO_I_START;
71 case 16: return S5PC100_GPIO_J0_START;
72 case 17: return S5PC100_GPIO_J1_START;
73 case 18: return S5PC100_GPIO_J2_START;
74 case 19: return S5PC100_GPIO_J3_START;
75 case 20: return S5PC100_GPIO_J4_START;
76 default:
77 BUG();
78 }
79
80 return -EINVAL;
81}
82
83static int s5pc1xx_get_group(unsigned int irq)
84{
85 irq -= S3C_IRQ_GPIO(0);
86
87 switch (irq) {
88 case S5PC100_GPIO_A0_START ... S5PC100_GPIO_A1_START - 1:
89 return 0;
90 case S5PC100_GPIO_A1_START ... S5PC100_GPIO_B_START - 1:
91 return 1;
92 case S5PC100_GPIO_B_START ... S5PC100_GPIO_C_START - 1:
93 return 2;
94 case S5PC100_GPIO_C_START ... S5PC100_GPIO_D_START - 1:
95 return 3;
96 case S5PC100_GPIO_D_START ... S5PC100_GPIO_E0_START - 1:
97 return 4;
98 case S5PC100_GPIO_E0_START ... S5PC100_GPIO_E1_START - 1:
99 return 5;
100 case S5PC100_GPIO_E1_START ... S5PC100_GPIO_F0_START - 1:
101 return 6;
102 case S5PC100_GPIO_F0_START ... S5PC100_GPIO_F1_START - 1:
103 return 7;
104 case S5PC100_GPIO_F1_START ... S5PC100_GPIO_F2_START - 1:
105 return 8;
106 case S5PC100_GPIO_F2_START ... S5PC100_GPIO_F3_START - 1:
107 return 9;
108 case S5PC100_GPIO_F3_START ... S5PC100_GPIO_G0_START - 1:
109 return 10;
110 case S5PC100_GPIO_G0_START ... S5PC100_GPIO_G1_START - 1:
111 return 11;
112 case S5PC100_GPIO_G1_START ... S5PC100_GPIO_G2_START - 1:
113 return 12;
114 case S5PC100_GPIO_G2_START ... S5PC100_GPIO_G3_START - 1:
115 return 13;
116 case S5PC100_GPIO_G3_START ... S5PC100_GPIO_H0_START - 1:
117 return 14;
118 case S5PC100_GPIO_I_START ... S5PC100_GPIO_J0_START - 1:
119 return 15;
120 case S5PC100_GPIO_J0_START ... S5PC100_GPIO_J1_START - 1:
121 return 16;
122 case S5PC100_GPIO_J1_START ... S5PC100_GPIO_J2_START - 1:
123 return 17;
124 case S5PC100_GPIO_J2_START ... S5PC100_GPIO_J3_START - 1:
125 return 18;
126 case S5PC100_GPIO_J3_START ... S5PC100_GPIO_J4_START - 1:
127 return 19;
128 case S5PC100_GPIO_J4_START ... S5PC100_GPIO_K0_START - 1:
129 return 20;
130 default:
131 BUG();
132 }
133
134 return -EINVAL;
135}
136
137static int s5pc1xx_get_offset(unsigned int irq)
138{
139 struct gpio_chip *chip = get_irq_data(irq);
140 return irq - S3C_IRQ_GPIO(chip->base);
141}
142
143static void s5pc1xx_gpioint_ack(unsigned int irq)
144{
145 int group, offset, pend_offset;
146 unsigned int value;
147
148 group = s5pc1xx_get_group(irq);
149 offset = s5pc1xx_get_offset(irq);
150 pend_offset = group_to_pend_offset(group);
151
152 value = __raw_readl(S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset);
153 value |= 1 << offset;
154 __raw_writel(value, S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset);
155}
156
157static void s5pc1xx_gpioint_mask(unsigned int irq)
158{
159 int group, offset, mask_offset;
160 unsigned int value;
161
162 group = s5pc1xx_get_group(irq);
163 offset = s5pc1xx_get_offset(irq);
164 mask_offset = group_to_mask_offset(group);
165
166 value = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset);
167 value |= 1 << offset;
168 __raw_writel(value, S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset);
169}
170
171static void s5pc1xx_gpioint_unmask(unsigned int irq)
172{
173 int group, offset, mask_offset;
174 unsigned int value;
175
176 group = s5pc1xx_get_group(irq);
177 offset = s5pc1xx_get_offset(irq);
178 mask_offset = group_to_mask_offset(group);
179
180 value = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset);
181 value &= ~(1 << offset);
182 __raw_writel(value, S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset);
183}
184
185static void s5pc1xx_gpioint_mask_ack(unsigned int irq)
186{
187 s5pc1xx_gpioint_mask(irq);
188 s5pc1xx_gpioint_ack(irq);
189}
190
191static int s5pc1xx_gpioint_set_type(unsigned int irq, unsigned int type)
192{
193 int group, offset, con_offset;
194 unsigned int value;
195
196 group = s5pc1xx_get_group(irq);
197 offset = s5pc1xx_get_offset(irq);
198 con_offset = group_to_con_offset(group);
199
200 switch (type) {
201 case IRQ_TYPE_NONE:
202 printk(KERN_WARNING "No irq type\n");
203 return -EINVAL;
204 case IRQ_TYPE_EDGE_RISING:
205 type = GPIOINT_EDGE_RISING;
206 break;
207 case IRQ_TYPE_EDGE_FALLING:
208 type = GPIOINT_EDGE_FALLING;
209 break;
210 case IRQ_TYPE_EDGE_BOTH:
211 type = GPIOINT_EDGE_BOTH;
212 break;
213 case IRQ_TYPE_LEVEL_HIGH:
214 type = GPIOINT_LEVEL_HIGH;
215 break;
216 case IRQ_TYPE_LEVEL_LOW:
217 type = GPIOINT_LEVEL_LOW;
218 break;
219 default:
220 BUG();
221 }
222
223
224 value = __raw_readl(S5PC1XX_GPIOREG(CON_OFFSET) + con_offset);
225 value &= ~(0xf << (offset * 0x4));
226 value |= (type << (offset * 0x4));
227 __raw_writel(value, S5PC1XX_GPIOREG(CON_OFFSET) + con_offset);
228
229 return 0;
230}
231
232struct irq_chip s5pc1xx_gpioint = {
233 .name = "GPIO",
234 .ack = s5pc1xx_gpioint_ack,
235 .mask = s5pc1xx_gpioint_mask,
236 .mask_ack = s5pc1xx_gpioint_mask_ack,
237 .unmask = s5pc1xx_gpioint_unmask,
238 .set_type = s5pc1xx_gpioint_set_type,
239};
240
241void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc)
242{
243 int group, offset, pend_offset, mask_offset;
244 int real_irq, group_end;
245 unsigned int pend, mask;
246
247 group_end = 21;
248
249 for (group = 0; group < group_end; group++) {
250 pend_offset = group_to_pend_offset(group);
251 pend = __raw_readl(S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset);
252 if (!pend)
253 continue;
254
255 mask_offset = group_to_mask_offset(group);
256 mask = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset);
257 pend &= ~mask;
258
259 for (offset = 0; offset < 8; offset++) {
260 if (pend & (1 << offset)) {
261 real_irq = s5pc1xx_get_start(group) + offset;
262 generic_handle_irq(S3C_IRQ_GPIO(real_irq));
263 }
264 }
265 }
266}
diff --git a/arch/arm/plat-s5pc1xx/irq.c b/arch/arm/plat-s5pc1xx/irq.c
index 80d6dd942cb8..e44fd04ef333 100644
--- a/arch/arm/plat-s5pc1xx/irq.c
+++ b/arch/arm/plat-s5pc1xx/irq.c
@@ -79,7 +79,7 @@ static void s3c_irq_timer_ack(unsigned int irq)
79{ 79{
80 u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); 80 u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
81 81
82 reg &= 0x1f; 82 reg &= 0x1f; /* mask out pending interrupts */
83 reg |= (1 << 5) << (irq - IRQ_TIMER0); 83 reg |= (1 << 5) << (irq - IRQ_TIMER0);
84 __raw_writel(reg, S3C64XX_TINT_CSTAT); 84 __raw_writel(reg, S3C64XX_TINT_CSTAT);
85} 85}
diff --git a/arch/arm/plat-s5pc1xx/s5pc100-clock.c b/arch/arm/plat-s5pc1xx/s5pc100-clock.c
index 6b24035172fa..b436d44510c8 100644
--- a/arch/arm/plat-s5pc1xx/s5pc100-clock.c
+++ b/arch/arm/plat-s5pc1xx/s5pc100-clock.c
@@ -49,6 +49,7 @@ static struct clk clk_ext_xtal_mux = {
49#define clk_fin_hpll clk_ext_xtal_mux 49#define clk_fin_hpll clk_ext_xtal_mux
50 50
51#define clk_fout_mpll clk_mpll 51#define clk_fout_mpll clk_mpll
52#define clk_vclk_54m clk_54m
52 53
53struct clk_sources { 54struct clk_sources {
54 unsigned int nr_sources; 55 unsigned int nr_sources;
@@ -67,746 +68,327 @@ struct clksrc_clk {
67 void __iomem *reg_source; 68 void __iomem *reg_source;
68}; 69};
69 70
70static int clk_default_setrate(struct clk *clk, unsigned long rate) 71/* APLL */
71{ 72static struct clk clk_fout_apll = {
72 clk->rate = rate; 73 .name = "fout_apll",
73 return 1;
74}
75
76struct clk clk_27m = {
77 .name = "clk_27m",
78 .id = -1, 74 .id = -1,
79 .rate = 27000000, 75 .rate = 27000000,
80}; 76};
81 77
82static int clk_48m_ctrl(struct clk *clk, int enable) 78static struct clk *clk_src_apll_list[] = {
83{ 79 [0] = &clk_fin_apll,
84 unsigned long flags; 80 [1] = &clk_fout_apll,
85 u32 val; 81};
82
83static struct clk_sources clk_src_apll = {
84 .sources = clk_src_apll_list,
85 .nr_sources = ARRAY_SIZE(clk_src_apll_list),
86};
86 87
87 /* can't rely on clock lock, this register has other usages */ 88static struct clksrc_clk clk_mout_apll = {
88 local_irq_save(flags); 89 .clk = {
90 .name = "mout_apll",
91 .id = -1,
92 },
93 .shift = S5PC100_CLKSRC0_APLL_SHIFT,
94 .mask = S5PC100_CLKSRC0_APLL_MASK,
95 .sources = &clk_src_apll,
96 .reg_source = S5PC100_CLKSRC0,
97};
89 98
90 val = __raw_readl(S5PC1XX_CLK_SRC1); 99static unsigned long s5pc100_clk_dout_apll_get_rate(struct clk *clk)
91 if (enable) 100{
92 val |= S5PC100_CLKSRC1_CLK48M_MASK; 101 unsigned long rate = clk_get_rate(clk->parent);
93 else 102 unsigned int ratio;
94 val &= ~S5PC100_CLKSRC1_CLK48M_MASK;
95 103
96 __raw_writel(val, S5PC1XX_CLK_SRC1); 104 ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_APLL_MASK;
97 local_irq_restore(flags); 105 ratio >>= S5PC100_CLKDIV0_APLL_SHIFT;
98 106
99 return 0; 107 return rate / (ratio + 1);
100} 108}
101 109
102struct clk clk_48m = { 110static struct clk clk_dout_apll = {
103 .name = "clk_48m", 111 .name = "dout_apll",
104 .id = -1, 112 .id = -1,
105 .rate = 48000000, 113 .parent = &clk_mout_apll.clk,
106 .enable = clk_48m_ctrl, 114 .get_rate = s5pc100_clk_dout_apll_get_rate,
107}; 115};
108 116
109struct clk clk_54m = { 117static unsigned long s5pc100_clk_arm_get_rate(struct clk *clk)
110 .name = "clk_54m", 118{
111 .id = -1, 119 unsigned long rate = clk_get_rate(clk->parent);
112 .rate = 54000000, 120 unsigned int ratio;
113};
114
115struct clk clk_hpll = {
116 .name = "hpll",
117 .id = -1,
118};
119 121
120struct clk clk_hd0 = { 122 ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_ARM_MASK;
121 .name = "hclkd0", 123 ratio >>= S5PC100_CLKDIV0_ARM_SHIFT;
122 .id = -1,
123 .rate = 0,
124 .parent = NULL,
125 .ctrlbit = 0,
126 .set_rate = clk_default_setrate,
127};
128 124
129struct clk clk_pd0 = { 125 return rate / (ratio + 1);
130 .name = "pclkd0", 126}
131 .id = -1,
132 .rate = 0,
133 .parent = NULL,
134 .ctrlbit = 0,
135 .set_rate = clk_default_setrate,
136};
137 127
138static int s5pc1xx_clk_gate(void __iomem *reg, 128static unsigned long s5pc100_clk_arm_round_rate(struct clk *clk,
139 struct clk *clk, 129 unsigned long rate)
140 int enable)
141{ 130{
142 unsigned int ctrlbit = clk->ctrlbit; 131 unsigned long parent = clk_get_rate(clk->parent);
143 u32 con; 132 u32 div;
144 133
145 con = __raw_readl(reg); 134 if (parent < rate)
135 return rate;
146 136
147 if (enable) 137 div = (parent / rate) - 1;
148 con |= ctrlbit; 138 if (div > S5PC100_CLKDIV0_ARM_MASK)
149 else 139 div = S5PC100_CLKDIV0_ARM_MASK;
150 con &= ~ctrlbit;
151 140
152 __raw_writel(con, reg); 141 return parent / (div + 1);
153 return 0;
154} 142}
155 143
156static int s5pc1xx_clk_d00_ctrl(struct clk *clk, int enable) 144static int s5pc100_clk_arm_set_rate(struct clk *clk, unsigned long rate)
157{ 145{
158 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D00, clk, enable); 146 unsigned long parent = clk_get_rate(clk->parent);
159} 147 u32 div;
148 u32 val;
160 149
161static int s5pc1xx_clk_d01_ctrl(struct clk *clk, int enable) 150 if (rate < parent / (S5PC100_CLKDIV0_ARM_MASK + 1))
162{ 151 return -EINVAL;
163 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D01, clk, enable);
164}
165 152
166static int s5pc1xx_clk_d02_ctrl(struct clk *clk, int enable) 153 rate = clk_round_rate(clk, rate);
167{ 154 div = clk_get_rate(clk->parent) / rate;
168 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D02, clk, enable);
169}
170 155
171static int s5pc1xx_clk_d10_ctrl(struct clk *clk, int enable) 156 val = __raw_readl(S5PC100_CLKDIV0);
172{ 157 val &= S5PC100_CLKDIV0_ARM_MASK;
173 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D10, clk, enable); 158 val |= (div - 1);
174} 159 __raw_writel(val, S5PC100_CLKDIV0);
175 160
176static int s5pc1xx_clk_d11_ctrl(struct clk *clk, int enable) 161 return 0;
177{
178 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D11, clk, enable);
179} 162}
180 163
181static int s5pc1xx_clk_d12_ctrl(struct clk *clk, int enable) 164static struct clk clk_arm = {
182{ 165 .name = "armclk",
183 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D12, clk, enable); 166 .id = -1,
184} 167 .parent = &clk_dout_apll,
168 .get_rate = s5pc100_clk_arm_get_rate,
169 .set_rate = s5pc100_clk_arm_set_rate,
170 .round_rate = s5pc100_clk_arm_round_rate,
171};
185 172
186static int s5pc1xx_clk_d13_ctrl(struct clk *clk, int enable) 173static unsigned long s5pc100_clk_dout_d0_bus_get_rate(struct clk *clk)
187{ 174{
188 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D13, clk, enable); 175 unsigned long rate = clk_get_rate(clk->parent);
189} 176 unsigned int ratio;
190 177
191static int s5pc1xx_clk_d14_ctrl(struct clk *clk, int enable) 178 ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_D0_MASK;
192{ 179 ratio >>= S5PC100_CLKDIV0_D0_SHIFT;
193 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D14, clk, enable);
194}
195 180
196static int s5pc1xx_clk_d15_ctrl(struct clk *clk, int enable) 181 return rate / (ratio + 1);
197{
198 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D15, clk, enable);
199} 182}
200 183
201static int s5pc1xx_clk_d20_ctrl(struct clk *clk, int enable) 184static struct clk clk_dout_d0_bus = {
202{ 185 .name = "dout_d0_bus",
203 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D20, clk, enable); 186 .id = -1,
204} 187 .parent = &clk_arm,
188 .get_rate = s5pc100_clk_dout_d0_bus_get_rate,
189};
205 190
206int s5pc1xx_sclk0_ctrl(struct clk *clk, int enable) 191static unsigned long s5pc100_clk_dout_pclkd0_get_rate(struct clk *clk)
207{ 192{
208 return s5pc1xx_clk_gate(S5PC100_SCLKGATE0, clk, enable); 193 unsigned long rate = clk_get_rate(clk->parent);
194 unsigned int ratio;
195
196 ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_PCLKD0_MASK;
197 ratio >>= S5PC100_CLKDIV0_PCLKD0_SHIFT;
198
199 return rate / (ratio + 1);
209} 200}
210 201
211int s5pc1xx_sclk1_ctrl(struct clk *clk, int enable) 202static struct clk clk_dout_pclkd0 = {
203 .name = "dout_pclkd0",
204 .id = -1,
205 .parent = &clk_dout_d0_bus,
206 .get_rate = s5pc100_clk_dout_pclkd0_get_rate,
207};
208
209static unsigned long s5pc100_clk_dout_apll2_get_rate(struct clk *clk)
212{ 210{
213 return s5pc1xx_clk_gate(S5PC100_SCLKGATE1, clk, enable); 211 unsigned long rate = clk_get_rate(clk->parent);
212 unsigned int ratio;
213
214 ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_APLL2_MASK;
215 ratio >>= S5PC100_CLKDIV1_APLL2_SHIFT;
216
217 return rate / (ratio + 1);
214} 218}
215 219
216static struct clk init_clocks_disable[] = { 220static struct clk clk_dout_apll2 = {
217 { 221 .name = "dout_apll2",
218 .name = "dsi", 222 .id = -1,
219 .id = -1, 223 .parent = &clk_mout_apll.clk,
220 .parent = &clk_p, 224 .get_rate = s5pc100_clk_dout_apll2_get_rate,
221 .enable = s5pc1xx_clk_d11_ctrl,
222 .ctrlbit = S5PC100_CLKGATE_D11_DSI,
223 }, {
224 .name = "csi",
225 .id = -1,
226 .parent = &clk_h,
227 .enable = s5pc1xx_clk_d11_ctrl,
228 .ctrlbit = S5PC100_CLKGATE_D11_CSI,
229 }, {
230 .name = "ccan0",
231 .id = 0,
232 .parent = &clk_p,
233 .enable = s5pc1xx_clk_d14_ctrl,
234 .ctrlbit = S5PC100_CLKGATE_D14_CCAN0,
235 }, {
236 .name = "ccan1",
237 .id = 1,
238 .parent = &clk_p,
239 .enable = s5pc1xx_clk_d14_ctrl,
240 .ctrlbit = S5PC100_CLKGATE_D14_CCAN1,
241 }, {
242 .name = "keypad",
243 .id = -1,
244 .parent = &clk_p,
245 .enable = s5pc1xx_clk_d15_ctrl,
246 .ctrlbit = S5PC100_CLKGATE_D15_KEYIF,
247 }, {
248 .name = "hclkd2",
249 .id = -1,
250 .parent = NULL,
251 .enable = s5pc1xx_clk_d20_ctrl,
252 .ctrlbit = S5PC100_CLKGATE_D20_HCLKD2,
253 }, {
254 .name = "iis-d2",
255 .id = -1,
256 .parent = NULL,
257 .enable = s5pc1xx_clk_d20_ctrl,
258 .ctrlbit = S5PC100_CLKGATE_D20_I2SD2,
259 }, {
260 .name = "otg",
261 .id = -1,
262 .parent = &clk_h,
263 .enable = s5pc1xx_clk_d10_ctrl,
264 .ctrlbit = S5PC100_CLKGATE_D10_USBOTG,
265 },
266}; 225};
267 226
268static struct clk init_clocks[] = { 227/* MPLL */
269 /* System1 (D0_0) devices */ 228static struct clk *clk_src_mpll_list[] = {
270 { 229 [0] = &clk_fin_mpll,
271 .name = "intc", 230 [1] = &clk_fout_mpll,
272 .id = -1, 231};
273 .parent = &clk_hd0,
274 .enable = s5pc1xx_clk_d00_ctrl,
275 .ctrlbit = S5PC100_CLKGATE_D00_INTC,
276 }, {
277 .name = "tzic",
278 .id = -1,
279 .parent = &clk_hd0,
280 .enable = s5pc1xx_clk_d00_ctrl,
281 .ctrlbit = S5PC100_CLKGATE_D00_TZIC,
282 }, {
283 .name = "cf-ata",
284 .id = -1,
285 .parent = &clk_hd0,
286 .enable = s5pc1xx_clk_d00_ctrl,
287 .ctrlbit = S5PC100_CLKGATE_D00_CFCON,
288 }, {
289 .name = "mdma",
290 .id = -1,
291 .parent = &clk_hd0,
292 .enable = s5pc1xx_clk_d00_ctrl,
293 .ctrlbit = S5PC100_CLKGATE_D00_MDMA,
294 }, {
295 .name = "g2d",
296 .id = -1,
297 .parent = &clk_hd0,
298 .enable = s5pc1xx_clk_d00_ctrl,
299 .ctrlbit = S5PC100_CLKGATE_D00_G2D,
300 }, {
301 .name = "secss",
302 .id = -1,
303 .parent = &clk_hd0,
304 .enable = s5pc1xx_clk_d00_ctrl,
305 .ctrlbit = S5PC100_CLKGATE_D00_SECSS,
306 }, {
307 .name = "cssys",
308 .id = -1,
309 .parent = &clk_hd0,
310 .enable = s5pc1xx_clk_d00_ctrl,
311 .ctrlbit = S5PC100_CLKGATE_D00_CSSYS,
312 },
313 232
314 /* Memory (D0_1) devices */ 233static struct clk_sources clk_src_mpll = {
315 { 234 .sources = clk_src_mpll_list,
316 .name = "dmc", 235 .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
317 .id = -1, 236};
318 .parent = &clk_hd0,
319 .enable = s5pc1xx_clk_d01_ctrl,
320 .ctrlbit = S5PC100_CLKGATE_D01_DMC,
321 }, {
322 .name = "sromc",
323 .id = -1,
324 .parent = &clk_hd0,
325 .enable = s5pc1xx_clk_d01_ctrl,
326 .ctrlbit = S5PC100_CLKGATE_D01_SROMC,
327 }, {
328 .name = "onenand",
329 .id = -1,
330 .parent = &clk_hd0,
331 .enable = s5pc1xx_clk_d01_ctrl,
332 .ctrlbit = S5PC100_CLKGATE_D01_ONENAND,
333 }, {
334 .name = "nand",
335 .id = -1,
336 .parent = &clk_hd0,
337 .enable = s5pc1xx_clk_d01_ctrl,
338 .ctrlbit = S5PC100_CLKGATE_D01_NFCON,
339 }, {
340 .name = "intmem",
341 .id = -1,
342 .parent = &clk_hd0,
343 .enable = s5pc1xx_clk_d01_ctrl,
344 .ctrlbit = S5PC100_CLKGATE_D01_INTMEM,
345 }, {
346 .name = "ebi",
347 .id = -1,
348 .parent = &clk_hd0,
349 .enable = s5pc1xx_clk_d01_ctrl,
350 .ctrlbit = S5PC100_CLKGATE_D01_EBI,
351 },
352 237
353 /* System2 (D0_2) devices */ 238static struct clksrc_clk clk_mout_mpll = {
354 { 239 .clk = {
355 .name = "seckey", 240 .name = "mout_mpll",
356 .id = -1,
357 .parent = &clk_pd0,
358 .enable = s5pc1xx_clk_d02_ctrl,
359 .ctrlbit = S5PC100_CLKGATE_D02_SECKEY,
360 }, {
361 .name = "sdm",
362 .id = -1, 241 .id = -1,
363 .parent = &clk_hd0,
364 .enable = s5pc1xx_clk_d02_ctrl,
365 .ctrlbit = S5PC100_CLKGATE_D02_SDM,
366 }, 242 },
243 .shift = S5PC100_CLKSRC0_MPLL_SHIFT,
244 .mask = S5PC100_CLKSRC0_MPLL_MASK,
245 .sources = &clk_src_mpll,
246 .reg_source = S5PC100_CLKSRC0,
247};
367 248
368 /* File (D1_0) devices */ 249static struct clk *clkset_am_list[] = {
369 { 250 [0] = &clk_mout_mpll.clk,
370 .name = "pdma0", 251 [1] = &clk_dout_apll2,
371 .id = -1, 252};
372 .parent = &clk_h,
373 .enable = s5pc1xx_clk_d10_ctrl,
374 .ctrlbit = S5PC100_CLKGATE_D10_PDMA0,
375 }, {
376 .name = "pdma1",
377 .id = -1,
378 .parent = &clk_h,
379 .enable = s5pc1xx_clk_d10_ctrl,
380 .ctrlbit = S5PC100_CLKGATE_D10_PDMA1,
381 }, {
382 .name = "usb-host",
383 .id = -1,
384 .parent = &clk_h,
385 .enable = s5pc1xx_clk_d10_ctrl,
386 .ctrlbit = S5PC100_CLKGATE_D10_USBHOST,
387 }, {
388 .name = "modem",
389 .id = -1,
390 .parent = &clk_h,
391 .enable = s5pc1xx_clk_d10_ctrl,
392 .ctrlbit = S5PC100_CLKGATE_D10_MODEMIF,
393 }, {
394 .name = "hsmmc",
395 .id = 0,
396 .parent = &clk_h,
397 .enable = s5pc1xx_clk_d10_ctrl,
398 .ctrlbit = S5PC100_CLKGATE_D10_HSMMC0,
399 }, {
400 .name = "hsmmc",
401 .id = 1,
402 .parent = &clk_h,
403 .enable = s5pc1xx_clk_d10_ctrl,
404 .ctrlbit = S5PC100_CLKGATE_D10_HSMMC1,
405 }, {
406 .name = "hsmmc",
407 .id = 2,
408 .parent = &clk_h,
409 .enable = s5pc1xx_clk_d10_ctrl,
410 .ctrlbit = S5PC100_CLKGATE_D10_HSMMC2,
411 },
412 253
413 /* Multimedia1 (D1_1) devices */ 254static struct clk_sources clk_src_am = {
414 { 255 .sources = clkset_am_list,
415 .name = "lcd", 256 .nr_sources = ARRAY_SIZE(clkset_am_list),
416 .id = -1, 257};
417 .parent = &clk_h,
418 .enable = s5pc1xx_clk_d11_ctrl,
419 .ctrlbit = S5PC100_CLKGATE_D11_LCD,
420 }, {
421 .name = "rotator",
422 .id = -1,
423 .parent = &clk_h,
424 .enable = s5pc1xx_clk_d11_ctrl,
425 .ctrlbit = S5PC100_CLKGATE_D11_ROTATOR,
426 }, {
427 .name = "fimc",
428 .id = 0,
429 .parent = &clk_h,
430 .enable = s5pc1xx_clk_d11_ctrl,
431 .ctrlbit = S5PC100_CLKGATE_D11_FIMC0,
432 }, {
433 .name = "fimc",
434 .id = 1,
435 .parent = &clk_h,
436 .enable = s5pc1xx_clk_d11_ctrl,
437 .ctrlbit = S5PC100_CLKGATE_D11_FIMC1,
438 }, {
439 .name = "fimc",
440 .id = 2,
441 .parent = &clk_h,
442 .enable = s5pc1xx_clk_d11_ctrl,
443 .ctrlbit = S5PC100_CLKGATE_D11_FIMC2,
444 }, {
445 .name = "jpeg",
446 .id = -1,
447 .parent = &clk_h,
448 .enable = s5pc1xx_clk_d11_ctrl,
449 .ctrlbit = S5PC100_CLKGATE_D11_JPEG,
450 }, {
451 .name = "g3d",
452 .id = -1,
453 .parent = &clk_h,
454 .enable = s5pc1xx_clk_d11_ctrl,
455 .ctrlbit = S5PC100_CLKGATE_D11_G3D,
456 },
457 258
458 /* Multimedia2 (D1_2) devices */ 259static struct clksrc_clk clk_mout_am = {
459 { 260 .clk = {
460 .name = "tv", 261 .name = "mout_am",
461 .id = -1,
462 .parent = &clk_h,
463 .enable = s5pc1xx_clk_d12_ctrl,
464 .ctrlbit = S5PC100_CLKGATE_D12_TV,
465 }, {
466 .name = "vp",
467 .id = -1,
468 .parent = &clk_h,
469 .enable = s5pc1xx_clk_d12_ctrl,
470 .ctrlbit = S5PC100_CLKGATE_D12_VP,
471 }, {
472 .name = "mixer",
473 .id = -1,
474 .parent = &clk_h,
475 .enable = s5pc1xx_clk_d12_ctrl,
476 .ctrlbit = S5PC100_CLKGATE_D12_MIXER,
477 }, {
478 .name = "hdmi",
479 .id = -1,
480 .parent = &clk_h,
481 .enable = s5pc1xx_clk_d12_ctrl,
482 .ctrlbit = S5PC100_CLKGATE_D12_HDMI,
483 }, {
484 .name = "mfc",
485 .id = -1, 262 .id = -1,
486 .parent = &clk_h,
487 .enable = s5pc1xx_clk_d12_ctrl,
488 .ctrlbit = S5PC100_CLKGATE_D12_MFC,
489 }, 263 },
264 .shift = S5PC100_CLKSRC0_AMMUX_SHIFT,
265 .mask = S5PC100_CLKSRC0_AMMUX_MASK,
266 .sources = &clk_src_am,
267 .reg_source = S5PC100_CLKSRC0,
268};
490 269
491 /* System (D1_3) devices */ 270static unsigned long s5pc100_clk_dout_d1_bus_get_rate(struct clk *clk)
492 { 271{
493 .name = "chipid", 272 unsigned long rate = clk_get_rate(clk->parent);
494 .id = -1, 273 unsigned int ratio;
495 .parent = &clk_p,
496 .enable = s5pc1xx_clk_d13_ctrl,
497 .ctrlbit = S5PC100_CLKGATE_D13_CHIPID,
498 }, {
499 .name = "gpio",
500 .id = -1,
501 .parent = &clk_p,
502 .enable = s5pc1xx_clk_d13_ctrl,
503 .ctrlbit = S5PC100_CLKGATE_D13_GPIO,
504 }, {
505 .name = "apc",
506 .id = -1,
507 .parent = &clk_p,
508 .enable = s5pc1xx_clk_d13_ctrl,
509 .ctrlbit = S5PC100_CLKGATE_D13_APC,
510 }, {
511 .name = "iec",
512 .id = -1,
513 .parent = &clk_p,
514 .enable = s5pc1xx_clk_d13_ctrl,
515 .ctrlbit = S5PC100_CLKGATE_D13_IEC,
516 }, {
517 .name = "timers",
518 .id = -1,
519 .parent = &clk_p,
520 .enable = s5pc1xx_clk_d13_ctrl,
521 .ctrlbit = S5PC100_CLKGATE_D13_PWM,
522 }, {
523 .name = "systimer",
524 .id = -1,
525 .parent = &clk_p,
526 .enable = s5pc1xx_clk_d13_ctrl,
527 .ctrlbit = S5PC100_CLKGATE_D13_SYSTIMER,
528 }, {
529 .name = "watchdog",
530 .id = -1,
531 .parent = &clk_p,
532 .enable = s5pc1xx_clk_d13_ctrl,
533 .ctrlbit = S5PC100_CLKGATE_D13_WDT,
534 }, {
535 .name = "rtc",
536 .id = -1,
537 .parent = &clk_p,
538 .enable = s5pc1xx_clk_d13_ctrl,
539 .ctrlbit = S5PC100_CLKGATE_D13_RTC,
540 },
541 274
542 /* Connectivity (D1_4) devices */ 275 printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
543 {
544 .name = "uart",
545 .id = 0,
546 .parent = &clk_p,
547 .enable = s5pc1xx_clk_d14_ctrl,
548 .ctrlbit = S5PC100_CLKGATE_D14_UART0,
549 }, {
550 .name = "uart",
551 .id = 1,
552 .parent = &clk_p,
553 .enable = s5pc1xx_clk_d14_ctrl,
554 .ctrlbit = S5PC100_CLKGATE_D14_UART1,
555 }, {
556 .name = "uart",
557 .id = 2,
558 .parent = &clk_p,
559 .enable = s5pc1xx_clk_d14_ctrl,
560 .ctrlbit = S5PC100_CLKGATE_D14_UART2,
561 }, {
562 .name = "uart",
563 .id = 3,
564 .parent = &clk_p,
565 .enable = s5pc1xx_clk_d14_ctrl,
566 .ctrlbit = S5PC100_CLKGATE_D14_UART3,
567 }, {
568 .name = "i2c",
569 .id = -1,
570 .parent = &clk_p,
571 .enable = s5pc1xx_clk_d14_ctrl,
572 .ctrlbit = S5PC100_CLKGATE_D14_IIC,
573 }, {
574 .name = "hdmi-i2c",
575 .id = -1,
576 .parent = &clk_p,
577 .enable = s5pc1xx_clk_d14_ctrl,
578 .ctrlbit = S5PC100_CLKGATE_D14_HDMI_IIC,
579 }, {
580 .name = "spi",
581 .id = 0,
582 .parent = &clk_p,
583 .enable = s5pc1xx_clk_d14_ctrl,
584 .ctrlbit = S5PC100_CLKGATE_D14_SPI0,
585 }, {
586 .name = "spi",
587 .id = 1,
588 .parent = &clk_p,
589 .enable = s5pc1xx_clk_d14_ctrl,
590 .ctrlbit = S5PC100_CLKGATE_D14_SPI1,
591 }, {
592 .name = "spi",
593 .id = 2,
594 .parent = &clk_p,
595 .enable = s5pc1xx_clk_d14_ctrl,
596 .ctrlbit = S5PC100_CLKGATE_D14_SPI2,
597 }, {
598 .name = "irda",
599 .id = -1,
600 .parent = &clk_p,
601 .enable = s5pc1xx_clk_d14_ctrl,
602 .ctrlbit = S5PC100_CLKGATE_D14_IRDA,
603 }, {
604 .name = "hsitx",
605 .id = -1,
606 .parent = &clk_p,
607 .enable = s5pc1xx_clk_d14_ctrl,
608 .ctrlbit = S5PC100_CLKGATE_D14_HSITX,
609 }, {
610 .name = "hsirx",
611 .id = -1,
612 .parent = &clk_p,
613 .enable = s5pc1xx_clk_d14_ctrl,
614 .ctrlbit = S5PC100_CLKGATE_D14_HSIRX,
615 },
616 276
617 /* Audio (D1_5) devices */ 277 ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_D1_MASK;
618 { 278 ratio >>= S5PC100_CLKDIV1_D1_SHIFT;
619 .name = "iis",
620 .id = 0,
621 .parent = &clk_p,
622 .enable = s5pc1xx_clk_d15_ctrl,
623 .ctrlbit = S5PC100_CLKGATE_D15_IIS0,
624 }, {
625 .name = "iis",
626 .id = 1,
627 .parent = &clk_p,
628 .enable = s5pc1xx_clk_d15_ctrl,
629 .ctrlbit = S5PC100_CLKGATE_D15_IIS1,
630 }, {
631 .name = "iis",
632 .id = 2,
633 .parent = &clk_p,
634 .enable = s5pc1xx_clk_d15_ctrl,
635 .ctrlbit = S5PC100_CLKGATE_D15_IIS2,
636 }, {
637 .name = "ac97",
638 .id = -1,
639 .parent = &clk_p,
640 .enable = s5pc1xx_clk_d15_ctrl,
641 .ctrlbit = S5PC100_CLKGATE_D15_AC97,
642 }, {
643 .name = "pcm",
644 .id = 0,
645 .parent = &clk_p,
646 .enable = s5pc1xx_clk_d15_ctrl,
647 .ctrlbit = S5PC100_CLKGATE_D15_PCM0,
648 }, {
649 .name = "pcm",
650 .id = 1,
651 .parent = &clk_p,
652 .enable = s5pc1xx_clk_d15_ctrl,
653 .ctrlbit = S5PC100_CLKGATE_D15_PCM1,
654 }, {
655 .name = "spdif",
656 .id = -1,
657 .parent = &clk_p,
658 .enable = s5pc1xx_clk_d15_ctrl,
659 .ctrlbit = S5PC100_CLKGATE_D15_SPDIF,
660 }, {
661 .name = "adc",
662 .id = -1,
663 .parent = &clk_p,
664 .enable = s5pc1xx_clk_d15_ctrl,
665 .ctrlbit = S5PC100_CLKGATE_D15_TSADC,
666 }, {
667 .name = "keyif",
668 .id = -1,
669 .parent = &clk_p,
670 .enable = s5pc1xx_clk_d15_ctrl,
671 .ctrlbit = S5PC100_CLKGATE_D15_KEYIF,
672 }, {
673 .name = "cg",
674 .id = -1,
675 .parent = &clk_p,
676 .enable = s5pc1xx_clk_d15_ctrl,
677 .ctrlbit = S5PC100_CLKGATE_D15_CG,
678 },
679 279
680 /* Audio (D2_0) devices: all disabled */ 280 return rate / (ratio + 1);
281}
681 282
682 /* Special Clocks 1 */ 283static struct clk clk_dout_d1_bus = {
683 { 284 .name = "dout_d1_bus",
684 .name = "sclk_hpm", 285 .id = -1,
685 .id = -1, 286 .parent = &clk_mout_am.clk,
686 .parent = NULL, 287 .get_rate = s5pc100_clk_dout_d1_bus_get_rate,
687 .enable = s5pc1xx_sclk0_ctrl, 288};
688 .ctrlbit = S5PC1XX_CLKGATE_SCLK0_HPM,
689 }, {
690 .name = "sclk_onenand",
691 .id = -1,
692 .parent = NULL,
693 .enable = s5pc1xx_sclk0_ctrl,
694 .ctrlbit = S5PC100_CLKGATE_SCLK0_ONENAND,
695 }, {
696 .name = "sclk_spi_48",
697 .id = 0,
698 .parent = &clk_48m,
699 .enable = s5pc1xx_sclk0_ctrl,
700 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0_48,
701 }, {
702 .name = "sclk_spi_48",
703 .id = 1,
704 .parent = &clk_48m,
705 .enable = s5pc1xx_sclk0_ctrl,
706 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1_48,
707 }, {
708 .name = "sclk_spi_48",
709 .id = 2,
710 .parent = &clk_48m,
711 .enable = s5pc1xx_sclk0_ctrl,
712 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2_48,
713 }, {
714 .name = "sclk_mmc_48",
715 .id = 0,
716 .parent = &clk_48m,
717 .enable = s5pc1xx_sclk0_ctrl,
718 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0_48,
719 }, {
720 .name = "sclk_mmc_48",
721 .id = 1,
722 .parent = &clk_48m,
723 .enable = s5pc1xx_sclk0_ctrl,
724 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1_48,
725 }, {
726 .name = "sclk_mmc_48",
727 .id = 2,
728 .parent = &clk_48m,
729 .enable = s5pc1xx_sclk0_ctrl,
730 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2_48,
731 },
732 289
733 /* Special Clocks 2 */ 290static struct clk *clkset_onenand_list[] = {
734 { 291 [0] = &clk_dout_d0_bus,
735 .name = "sclk_tv_54", 292 [1] = &clk_dout_d1_bus,
736 .id = -1, 293};
737 .parent = &clk_54m, 294
738 .enable = s5pc1xx_sclk1_ctrl, 295static struct clk_sources clk_src_onenand = {
739 .ctrlbit = S5PC100_CLKGATE_SCLK1_TV54, 296 .sources = clkset_onenand_list,
740 }, { 297 .nr_sources = ARRAY_SIZE(clkset_onenand_list),
741 .name = "sclk_vdac_54", 298};
742 .id = -1, 299
743 .parent = &clk_54m, 300static struct clksrc_clk clk_mout_onenand = {
744 .enable = s5pc1xx_sclk1_ctrl, 301 .clk = {
745 .ctrlbit = S5PC100_CLKGATE_SCLK1_VDAC54, 302 .name = "mout_onenand",
746 }, {
747 .name = "sclk_spdif",
748 .id = -1, 303 .id = -1,
749 .parent = NULL,
750 .enable = s5pc1xx_sclk1_ctrl,
751 .ctrlbit = S5PC100_CLKGATE_SCLK1_SPDIF,
752 }, 304 },
305 .shift = S5PC100_CLKSRC0_ONENAND_SHIFT,
306 .mask = S5PC100_CLKSRC0_ONENAND_MASK,
307 .sources = &clk_src_onenand,
308 .reg_source = S5PC100_CLKSRC0,
753}; 309};
754 310
755void __init s5pc1xx_register_clocks(void) 311static unsigned long s5pc100_clk_dout_pclkd1_get_rate(struct clk *clk)
756{ 312{
757 struct clk *clkp; 313 unsigned long rate = clk_get_rate(clk->parent);
758 int ret; 314 unsigned int ratio;
759 int ptr;
760 315
761 clkp = init_clocks; 316 printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
762 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
763 ret = s3c24xx_register_clock(clkp);
764 if (ret < 0) {
765 printk(KERN_ERR "Failed to register clock %s (%d)\n",
766 clkp->name, ret);
767 }
768 }
769 317
770 clkp = init_clocks_disable; 318 ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_PCLKD1_MASK;
771 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { 319 ratio >>= S5PC100_CLKDIV1_PCLKD1_SHIFT;
772 320
773 ret = s3c24xx_register_clock(clkp); 321 return rate / (ratio + 1);
774 if (ret < 0) { 322}
775 printk(KERN_ERR "Failed to register clock %s (%d)\n",
776 clkp->name, ret);
777 }
778 323
779 (clkp->enable)(clkp, 0); 324static struct clk clk_dout_pclkd1 = {
780 } 325 .name = "dout_pclkd1",
326 .id = -1,
327 .parent = &clk_dout_d1_bus,
328 .get_rate = s5pc100_clk_dout_pclkd1_get_rate,
329};
330
331static unsigned long s5pc100_clk_dout_mpll2_get_rate(struct clk *clk)
332{
333 unsigned long rate = clk_get_rate(clk->parent);
334 unsigned int ratio;
335
336 printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
337
338 ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_MPLL2_MASK;
339 ratio >>= S5PC100_CLKDIV1_MPLL2_SHIFT;
781 340
782 s3c_pwmclk_init(); 341 return rate / (ratio + 1);
783} 342}
784static struct clk clk_fout_apll = { 343
785 .name = "fout_apll", 344static struct clk clk_dout_mpll2 = {
345 .name = "dout_mpll2",
786 .id = -1, 346 .id = -1,
347 .parent = &clk_mout_am.clk,
348 .get_rate = s5pc100_clk_dout_mpll2_get_rate,
787}; 349};
788 350
789static struct clk *clk_src_apll_list[] = { 351static unsigned long s5pc100_clk_dout_cam_get_rate(struct clk *clk)
790 [0] = &clk_fin_apll, 352{
791 [1] = &clk_fout_apll, 353 unsigned long rate = clk_get_rate(clk->parent);
792}; 354 unsigned int ratio;
793 355
794static struct clk_sources clk_src_apll = { 356 printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
795 .sources = clk_src_apll_list, 357
796 .nr_sources = ARRAY_SIZE(clk_src_apll_list), 358 ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_CAM_MASK;
359 ratio >>= S5PC100_CLKDIV1_CAM_SHIFT;
360
361 return rate / (ratio + 1);
362}
363
364static struct clk clk_dout_cam = {
365 .name = "dout_cam",
366 .id = -1,
367 .parent = &clk_dout_mpll2,
368 .get_rate = s5pc100_clk_dout_cam_get_rate,
797}; 369};
798 370
799static struct clksrc_clk clk_mout_apll = { 371static unsigned long s5pc100_clk_dout_mpll_get_rate(struct clk *clk)
800 .clk = { 372{
801 .name = "mout_apll", 373 unsigned long rate = clk_get_rate(clk->parent);
802 .id = -1, 374 unsigned int ratio;
803 }, 375
804 .shift = S5PC1XX_CLKSRC0_APLL_SHIFT, 376 printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
805 .mask = S5PC1XX_CLKSRC0_APLL_MASK, 377
806 .sources = &clk_src_apll, 378 ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_MPLL_MASK;
807 .reg_source = S5PC1XX_CLK_SRC0, 379 ratio >>= S5PC100_CLKDIV1_MPLL_SHIFT;
380
381 return rate / (ratio + 1);
382}
383
384static struct clk clk_dout_mpll = {
385 .name = "dout_mpll",
386 .id = -1,
387 .parent = &clk_mout_am.clk,
388 .get_rate = s5pc100_clk_dout_mpll_get_rate,
808}; 389};
809 390
391/* EPLL */
810static struct clk clk_fout_epll = { 392static struct clk clk_fout_epll = {
811 .name = "fout_epll", 393 .name = "fout_epll",
812 .id = -1, 394 .id = -1,
@@ -827,91 +409,57 @@ static struct clksrc_clk clk_mout_epll = {
827 .name = "mout_epll", 409 .name = "mout_epll",
828 .id = -1, 410 .id = -1,
829 }, 411 },
830 .shift = S5PC1XX_CLKSRC0_EPLL_SHIFT, 412 .shift = S5PC100_CLKSRC0_EPLL_SHIFT,
831 .mask = S5PC1XX_CLKSRC0_EPLL_MASK, 413 .mask = S5PC100_CLKSRC0_EPLL_MASK,
832 .sources = &clk_src_epll, 414 .sources = &clk_src_epll,
833 .reg_source = S5PC1XX_CLK_SRC0, 415 .reg_source = S5PC100_CLKSRC0,
834}; 416};
835 417
836static struct clk *clk_src_mpll_list[] = { 418/* HPLL */
837 [0] = &clk_fin_mpll, 419static struct clk clk_fout_hpll = {
838 [1] = &clk_fout_mpll, 420 .name = "fout_hpll",
839};
840
841static struct clk_sources clk_src_mpll = {
842 .sources = clk_src_mpll_list,
843 .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
844};
845
846static struct clksrc_clk clk_mout_mpll = {
847 .clk = {
848 .name = "mout_mpll",
849 .id = -1,
850 },
851 .shift = S5PC1XX_CLKSRC0_MPLL_SHIFT,
852 .mask = S5PC1XX_CLKSRC0_MPLL_MASK,
853 .sources = &clk_src_mpll,
854 .reg_source = S5PC1XX_CLK_SRC0,
855};
856
857static unsigned long s5pc1xx_clk_doutmpll_get_rate(struct clk *clk)
858{
859 unsigned long rate = clk_get_rate(clk->parent);
860 unsigned long clkdiv;
861
862 printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
863
864 clkdiv = __raw_readl(S5PC1XX_CLK_DIV1) & S5PC100_CLKDIV1_MPLL_MASK;
865 rate /= (clkdiv >> S5PC100_CLKDIV1_MPLL_SHIFT) + 1;
866
867 return rate;
868}
869
870static struct clk clk_dout_mpll = {
871 .name = "dout_mpll",
872 .id = -1, 421 .id = -1,
873 .parent = &clk_mout_mpll.clk,
874 .get_rate = s5pc1xx_clk_doutmpll_get_rate,
875}; 422};
876 423
877static unsigned long s5pc1xx_clk_doutmpll2_get_rate(struct clk *clk) 424static struct clk *clk_src_hpll_list[] = {
878{ 425 [0] = &clk_27m,
879 unsigned long rate = clk_get_rate(clk->parent); 426 [1] = &clk_fout_hpll,
880 unsigned long clkdiv;
881
882 printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
883
884 clkdiv = __raw_readl(S5PC1XX_CLK_DIV1) & S5PC100_CLKDIV1_MPLL2_MASK;
885 rate /= (clkdiv >> S5PC100_CLKDIV1_MPLL2_SHIFT) + 1;
886
887 return rate;
888}
889
890struct clk clk_dout_mpll2 = {
891 .name = "dout_mpll2",
892 .id = -1,
893 .parent = &clk_mout_mpll.clk,
894 .get_rate = s5pc1xx_clk_doutmpll2_get_rate,
895}; 427};
896 428
897static struct clk *clkset_uart_list[] = { 429static struct clk_sources clk_src_hpll = {
898 &clk_mout_epll.clk, 430 .sources = clk_src_hpll_list,
899 &clk_dout_mpll, 431 .nr_sources = ARRAY_SIZE(clk_src_hpll_list),
900 NULL,
901 NULL
902}; 432};
903 433
904static struct clk_sources clkset_uart = { 434static struct clksrc_clk clk_mout_hpll = {
905 .sources = clkset_uart_list, 435 .clk = {
906 .nr_sources = ARRAY_SIZE(clkset_uart_list), 436 .name = "mout_hpll",
437 .id = -1,
438 },
439 .shift = S5PC100_CLKSRC0_HPLL_SHIFT,
440 .mask = S5PC100_CLKSRC0_HPLL_MASK,
441 .sources = &clk_src_hpll,
442 .reg_source = S5PC100_CLKSRC0,
907}; 443};
908 444
445/* Peripherals */
446/*
447 * The peripheral clocks are all controlled via clocksource followed
448 * by an optional divider and gate stage. We currently roll this into
449 * one clock which hides the intermediate clock from the mux.
450 *
451 * Note, the JPEG clock can only be an even divider...
452 *
453 * The scaler and LCD clocks depend on the S5PC100 version, and also
454 * have a common parent divisor so are not included here.
455 */
456
909static inline struct clksrc_clk *to_clksrc(struct clk *clk) 457static inline struct clksrc_clk *to_clksrc(struct clk *clk)
910{ 458{
911 return container_of(clk, struct clksrc_clk, clk); 459 return container_of(clk, struct clksrc_clk, clk);
912} 460}
913 461
914static unsigned long s5pc1xx_getrate_clksrc(struct clk *clk) 462static unsigned long s5pc100_getrate_clksrc(struct clk *clk)
915{ 463{
916 struct clksrc_clk *sclk = to_clksrc(clk); 464 struct clksrc_clk *sclk = to_clksrc(clk);
917 unsigned long rate = clk_get_rate(clk->parent); 465 unsigned long rate = clk_get_rate(clk->parent);
@@ -925,7 +473,7 @@ static unsigned long s5pc1xx_getrate_clksrc(struct clk *clk)
925 return rate; 473 return rate;
926} 474}
927 475
928static int s5pc1xx_setrate_clksrc(struct clk *clk, unsigned long rate) 476static int s5pc100_setrate_clksrc(struct clk *clk, unsigned long rate)
929{ 477{
930 struct clksrc_clk *sclk = to_clksrc(clk); 478 struct clksrc_clk *sclk = to_clksrc(clk);
931 void __iomem *reg = sclk->reg_divider; 479 void __iomem *reg = sclk->reg_divider;
@@ -938,14 +486,14 @@ static int s5pc1xx_setrate_clksrc(struct clk *clk, unsigned long rate)
938 return -EINVAL; 486 return -EINVAL;
939 487
940 val = __raw_readl(reg); 488 val = __raw_readl(reg);
941 val &= ~(0xf << sclk->shift); 489 val &= ~(0xf << sclk->divider_shift);
942 val |= (div - 1) << sclk->shift; 490 val |= (div - 1) << sclk->divider_shift;
943 __raw_writel(val, reg); 491 __raw_writel(val, reg);
944 492
945 return 0; 493 return 0;
946} 494}
947 495
948static int s5pc1xx_setparent_clksrc(struct clk *clk, struct clk *parent) 496static int s5pc100_setparent_clksrc(struct clk *clk, struct clk *parent)
949{ 497{
950 struct clksrc_clk *sclk = to_clksrc(clk); 498 struct clksrc_clk *sclk = to_clksrc(clk);
951 struct clk_sources *srcs = sclk->sources; 499 struct clk_sources *srcs = sclk->sources;
@@ -970,7 +518,7 @@ static int s5pc1xx_setparent_clksrc(struct clk *clk, struct clk *parent)
970 return -EINVAL; 518 return -EINVAL;
971} 519}
972 520
973static unsigned long s5pc1xx_roundrate_clksrc(struct clk *clk, 521static unsigned long s5pc100_roundrate_clksrc(struct clk *clk,
974 unsigned long rate) 522 unsigned long rate)
975{ 523{
976 unsigned long parent_rate = clk_get_rate(clk->parent); 524 unsigned long parent_rate = clk_get_rate(clk->parent);
@@ -992,35 +540,466 @@ static unsigned long s5pc1xx_roundrate_clksrc(struct clk *clk,
992 return rate; 540 return rate;
993} 541}
994 542
543static struct clk *clkset_spi_list[] = {
544 &clk_mout_epll.clk,
545 &clk_dout_mpll2,
546 &clk_fin_epll,
547 &clk_mout_hpll.clk,
548};
549
550static struct clk_sources clkset_spi = {
551 .sources = clkset_spi_list,
552 .nr_sources = ARRAY_SIZE(clkset_spi_list),
553};
554
555static struct clksrc_clk clk_spi0 = {
556 .clk = {
557 .name = "spi_bus",
558 .id = 0,
559 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0,
560 .enable = s5pc100_sclk0_ctrl,
561 .set_parent = s5pc100_setparent_clksrc,
562 .get_rate = s5pc100_getrate_clksrc,
563 .set_rate = s5pc100_setrate_clksrc,
564 .round_rate = s5pc100_roundrate_clksrc,
565 },
566 .shift = S5PC100_CLKSRC1_SPI0_SHIFT,
567 .mask = S5PC100_CLKSRC1_SPI0_MASK,
568 .sources = &clkset_spi,
569 .divider_shift = S5PC100_CLKDIV2_SPI0_SHIFT,
570 .reg_divider = S5PC100_CLKDIV2,
571 .reg_source = S5PC100_CLKSRC1,
572};
573
574static struct clksrc_clk clk_spi1 = {
575 .clk = {
576 .name = "spi_bus",
577 .id = 1,
578 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1,
579 .enable = s5pc100_sclk0_ctrl,
580 .set_parent = s5pc100_setparent_clksrc,
581 .get_rate = s5pc100_getrate_clksrc,
582 .set_rate = s5pc100_setrate_clksrc,
583 .round_rate = s5pc100_roundrate_clksrc,
584 },
585 .shift = S5PC100_CLKSRC1_SPI1_SHIFT,
586 .mask = S5PC100_CLKSRC1_SPI1_MASK,
587 .sources = &clkset_spi,
588 .divider_shift = S5PC100_CLKDIV2_SPI1_SHIFT,
589 .reg_divider = S5PC100_CLKDIV2,
590 .reg_source = S5PC100_CLKSRC1,
591};
592
593static struct clksrc_clk clk_spi2 = {
594 .clk = {
595 .name = "spi_bus",
596 .id = 2,
597 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2,
598 .enable = s5pc100_sclk0_ctrl,
599 .set_parent = s5pc100_setparent_clksrc,
600 .get_rate = s5pc100_getrate_clksrc,
601 .set_rate = s5pc100_setrate_clksrc,
602 .round_rate = s5pc100_roundrate_clksrc,
603 },
604 .shift = S5PC100_CLKSRC1_SPI2_SHIFT,
605 .mask = S5PC100_CLKSRC1_SPI2_MASK,
606 .sources = &clkset_spi,
607 .divider_shift = S5PC100_CLKDIV2_SPI2_SHIFT,
608 .reg_divider = S5PC100_CLKDIV2,
609 .reg_source = S5PC100_CLKSRC1,
610};
611
612static struct clk *clkset_uart_list[] = {
613 &clk_mout_epll.clk,
614 &clk_dout_mpll,
615};
616
617static struct clk_sources clkset_uart = {
618 .sources = clkset_uart_list,
619 .nr_sources = ARRAY_SIZE(clkset_uart_list),
620};
621
995static struct clksrc_clk clk_uart_uclk1 = { 622static struct clksrc_clk clk_uart_uclk1 = {
996 .clk = { 623 .clk = {
997 .name = "uclk1", 624 .name = "uclk1",
998 .id = -1, 625 .id = -1,
999 .ctrlbit = S5PC100_CLKGATE_SCLK0_UART, 626 .ctrlbit = S5PC100_CLKGATE_SCLK0_UART,
1000 .enable = s5pc1xx_sclk0_ctrl, 627 .enable = s5pc100_sclk0_ctrl,
1001 .set_parent = s5pc1xx_setparent_clksrc, 628 .set_parent = s5pc100_setparent_clksrc,
1002 .get_rate = s5pc1xx_getrate_clksrc, 629 .get_rate = s5pc100_getrate_clksrc,
1003 .set_rate = s5pc1xx_setrate_clksrc, 630 .set_rate = s5pc100_setrate_clksrc,
1004 .round_rate = s5pc1xx_roundrate_clksrc, 631 .round_rate = s5pc100_roundrate_clksrc,
1005 }, 632 },
1006 .shift = S5PC100_CLKSRC1_UART_SHIFT, 633 .shift = S5PC100_CLKSRC1_UART_SHIFT,
1007 .mask = S5PC100_CLKSRC1_UART_MASK, 634 .mask = S5PC100_CLKSRC1_UART_MASK,
1008 .sources = &clkset_uart, 635 .sources = &clkset_uart,
1009 .divider_shift = S5PC100_CLKDIV2_UART_SHIFT, 636 .divider_shift = S5PC100_CLKDIV2_UART_SHIFT,
1010 .reg_divider = S5PC1XX_CLK_DIV2, 637 .reg_divider = S5PC100_CLKDIV2,
1011 .reg_source = S5PC1XX_CLK_SRC1, 638 .reg_source = S5PC100_CLKSRC1,
639};
640
641static struct clk clk_iis_cd0 = {
642 .name = "iis_cdclk0",
643 .id = -1,
644};
645
646static struct clk clk_iis_cd1 = {
647 .name = "iis_cdclk1",
648 .id = -1,
649};
650
651static struct clk clk_iis_cd2 = {
652 .name = "iis_cdclk2",
653 .id = -1,
654};
655
656static struct clk clk_pcm_cd0 = {
657 .name = "pcm_cdclk0",
658 .id = -1,
659};
660
661static struct clk clk_pcm_cd1 = {
662 .name = "pcm_cdclk1",
663 .id = -1,
664};
665
666static struct clk *clkset_audio0_list[] = {
667 &clk_mout_epll.clk,
668 &clk_dout_mpll,
669 &clk_fin_epll,
670 &clk_iis_cd0,
671 &clk_pcm_cd0,
672 &clk_mout_hpll.clk,
673};
674
675static struct clk_sources clkset_audio0 = {
676 .sources = clkset_audio0_list,
677 .nr_sources = ARRAY_SIZE(clkset_audio0_list),
678};
679
680static struct clksrc_clk clk_audio0 = {
681 .clk = {
682 .name = "audio-bus",
683 .id = 0,
684 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO0,
685 .enable = s5pc100_sclk1_ctrl,
686 .set_parent = s5pc100_setparent_clksrc,
687 .get_rate = s5pc100_getrate_clksrc,
688 .set_rate = s5pc100_setrate_clksrc,
689 .round_rate = s5pc100_roundrate_clksrc,
690 },
691 .shift = S5PC100_CLKSRC3_AUDIO0_SHIFT,
692 .mask = S5PC100_CLKSRC3_AUDIO0_MASK,
693 .sources = &clkset_audio0,
694 .divider_shift = S5PC100_CLKDIV4_AUDIO0_SHIFT,
695 .reg_divider = S5PC100_CLKDIV4,
696 .reg_source = S5PC100_CLKSRC3,
697};
698
699static struct clk *clkset_audio1_list[] = {
700 &clk_mout_epll.clk,
701 &clk_dout_mpll,
702 &clk_fin_epll,
703 &clk_iis_cd1,
704 &clk_pcm_cd1,
705 &clk_mout_hpll.clk,
706};
707
708static struct clk_sources clkset_audio1 = {
709 .sources = clkset_audio1_list,
710 .nr_sources = ARRAY_SIZE(clkset_audio1_list),
711};
712
713static struct clksrc_clk clk_audio1 = {
714 .clk = {
715 .name = "audio-bus",
716 .id = 1,
717 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO1,
718 .enable = s5pc100_sclk1_ctrl,
719 .set_parent = s5pc100_setparent_clksrc,
720 .get_rate = s5pc100_getrate_clksrc,
721 .set_rate = s5pc100_setrate_clksrc,
722 .round_rate = s5pc100_roundrate_clksrc,
723 },
724 .shift = S5PC100_CLKSRC3_AUDIO1_SHIFT,
725 .mask = S5PC100_CLKSRC3_AUDIO1_MASK,
726 .sources = &clkset_audio1,
727 .divider_shift = S5PC100_CLKDIV4_AUDIO1_SHIFT,
728 .reg_divider = S5PC100_CLKDIV4,
729 .reg_source = S5PC100_CLKSRC3,
730};
731
732static struct clk *clkset_audio2_list[] = {
733 &clk_mout_epll.clk,
734 &clk_dout_mpll,
735 &clk_fin_epll,
736 &clk_iis_cd2,
737 &clk_mout_hpll.clk,
738};
739
740static struct clk_sources clkset_audio2 = {
741 .sources = clkset_audio2_list,
742 .nr_sources = ARRAY_SIZE(clkset_audio2_list),
743};
744
745static struct clksrc_clk clk_audio2 = {
746 .clk = {
747 .name = "audio-bus",
748 .id = 2,
749 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO2,
750 .enable = s5pc100_sclk1_ctrl,
751 .set_parent = s5pc100_setparent_clksrc,
752 .get_rate = s5pc100_getrate_clksrc,
753 .set_rate = s5pc100_setrate_clksrc,
754 .round_rate = s5pc100_roundrate_clksrc,
755 },
756 .shift = S5PC100_CLKSRC3_AUDIO2_SHIFT,
757 .mask = S5PC100_CLKSRC3_AUDIO2_MASK,
758 .sources = &clkset_audio2,
759 .divider_shift = S5PC100_CLKDIV4_AUDIO2_SHIFT,
760 .reg_divider = S5PC100_CLKDIV4,
761 .reg_source = S5PC100_CLKSRC3,
762};
763
764static struct clk *clkset_spdif_list[] = {
765 &clk_audio0.clk,
766 &clk_audio1.clk,
767 &clk_audio2.clk,
768};
769
770static struct clk_sources clkset_spdif = {
771 .sources = clkset_spdif_list,
772 .nr_sources = ARRAY_SIZE(clkset_spdif_list),
773};
774
775static struct clksrc_clk clk_spdif = {
776 .clk = {
777 .name = "spdif",
778 .id = -1,
779 },
780 .shift = S5PC100_CLKSRC3_SPDIF_SHIFT,
781 .mask = S5PC100_CLKSRC3_SPDIF_MASK,
782 .sources = &clkset_spdif,
783 .reg_source = S5PC100_CLKSRC3,
784};
785
786static struct clk *clkset_lcd_fimc_list[] = {
787 &clk_mout_epll.clk,
788 &clk_dout_mpll,
789 &clk_mout_hpll.clk,
790 &clk_vclk_54m,
791};
792
793static struct clk_sources clkset_lcd_fimc = {
794 .sources = clkset_lcd_fimc_list,
795 .nr_sources = ARRAY_SIZE(clkset_lcd_fimc_list),
796};
797
798static struct clksrc_clk clk_lcd = {
799 .clk = {
800 .name = "lcd",
801 .id = -1,
802 .ctrlbit = S5PC100_CLKGATE_SCLK1_LCD,
803 .enable = s5pc100_sclk1_ctrl,
804 .set_parent = s5pc100_setparent_clksrc,
805 .get_rate = s5pc100_getrate_clksrc,
806 .set_rate = s5pc100_setrate_clksrc,
807 .round_rate = s5pc100_roundrate_clksrc,
808 },
809 .shift = S5PC100_CLKSRC2_LCD_SHIFT,
810 .mask = S5PC100_CLKSRC2_LCD_MASK,
811 .sources = &clkset_lcd_fimc,
812 .divider_shift = S5PC100_CLKDIV3_LCD_SHIFT,
813 .reg_divider = S5PC100_CLKDIV3,
814 .reg_source = S5PC100_CLKSRC2,
815};
816
817static struct clksrc_clk clk_fimc0 = {
818 .clk = {
819 .name = "fimc",
820 .id = 0,
821 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC0,
822 .enable = s5pc100_sclk1_ctrl,
823 .set_parent = s5pc100_setparent_clksrc,
824 .get_rate = s5pc100_getrate_clksrc,
825 .set_rate = s5pc100_setrate_clksrc,
826 .round_rate = s5pc100_roundrate_clksrc,
827 },
828 .shift = S5PC100_CLKSRC2_FIMC0_SHIFT,
829 .mask = S5PC100_CLKSRC2_FIMC0_MASK,
830 .sources = &clkset_lcd_fimc,
831 .divider_shift = S5PC100_CLKDIV3_FIMC0_SHIFT,
832 .reg_divider = S5PC100_CLKDIV3,
833 .reg_source = S5PC100_CLKSRC2,
834};
835
836static struct clksrc_clk clk_fimc1 = {
837 .clk = {
838 .name = "fimc",
839 .id = 1,
840 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC1,
841 .enable = s5pc100_sclk1_ctrl,
842 .set_parent = s5pc100_setparent_clksrc,
843 .get_rate = s5pc100_getrate_clksrc,
844 .set_rate = s5pc100_setrate_clksrc,
845 .round_rate = s5pc100_roundrate_clksrc,
846 },
847 .shift = S5PC100_CLKSRC2_FIMC1_SHIFT,
848 .mask = S5PC100_CLKSRC2_FIMC1_MASK,
849 .sources = &clkset_lcd_fimc,
850 .divider_shift = S5PC100_CLKDIV3_FIMC1_SHIFT,
851 .reg_divider = S5PC100_CLKDIV3,
852 .reg_source = S5PC100_CLKSRC2,
853};
854
855static struct clksrc_clk clk_fimc2 = {
856 .clk = {
857 .name = "fimc",
858 .id = 2,
859 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC2,
860 .enable = s5pc100_sclk1_ctrl,
861 .set_parent = s5pc100_setparent_clksrc,
862 .get_rate = s5pc100_getrate_clksrc,
863 .set_rate = s5pc100_setrate_clksrc,
864 .round_rate = s5pc100_roundrate_clksrc,
865 },
866 .shift = S5PC100_CLKSRC2_FIMC2_SHIFT,
867 .mask = S5PC100_CLKSRC2_FIMC2_MASK,
868 .sources = &clkset_lcd_fimc,
869 .divider_shift = S5PC100_CLKDIV3_FIMC2_SHIFT,
870 .reg_divider = S5PC100_CLKDIV3,
871 .reg_source = S5PC100_CLKSRC2,
872};
873
874static struct clk *clkset_mmc_list[] = {
875 &clk_mout_epll.clk,
876 &clk_dout_mpll,
877 &clk_fin_epll,
878 &clk_mout_hpll.clk ,
879};
880
881static struct clk_sources clkset_mmc = {
882 .sources = clkset_mmc_list,
883 .nr_sources = ARRAY_SIZE(clkset_mmc_list),
884};
885
886static struct clksrc_clk clk_mmc0 = {
887 .clk = {
888 .name = "mmc_bus",
889 .id = 0,
890 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0,
891 .enable = s5pc100_sclk0_ctrl,
892 .set_parent = s5pc100_setparent_clksrc,
893 .get_rate = s5pc100_getrate_clksrc,
894 .set_rate = s5pc100_setrate_clksrc,
895 .round_rate = s5pc100_roundrate_clksrc,
896 },
897 .shift = S5PC100_CLKSRC2_MMC0_SHIFT,
898 .mask = S5PC100_CLKSRC2_MMC0_MASK,
899 .sources = &clkset_mmc,
900 .divider_shift = S5PC100_CLKDIV3_MMC0_SHIFT,
901 .reg_divider = S5PC100_CLKDIV3,
902 .reg_source = S5PC100_CLKSRC2,
903};
904
905static struct clksrc_clk clk_mmc1 = {
906 .clk = {
907 .name = "mmc_bus",
908 .id = 1,
909 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1,
910 .enable = s5pc100_sclk0_ctrl,
911 .set_parent = s5pc100_setparent_clksrc,
912 .get_rate = s5pc100_getrate_clksrc,
913 .set_rate = s5pc100_setrate_clksrc,
914 .round_rate = s5pc100_roundrate_clksrc,
915 },
916 .shift = S5PC100_CLKSRC2_MMC1_SHIFT,
917 .mask = S5PC100_CLKSRC2_MMC1_MASK,
918 .sources = &clkset_mmc,
919 .divider_shift = S5PC100_CLKDIV3_MMC1_SHIFT,
920 .reg_divider = S5PC100_CLKDIV3,
921 .reg_source = S5PC100_CLKSRC2,
922};
923
924static struct clksrc_clk clk_mmc2 = {
925 .clk = {
926 .name = "mmc_bus",
927 .id = 2,
928 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2,
929 .enable = s5pc100_sclk0_ctrl,
930 .set_parent = s5pc100_setparent_clksrc,
931 .get_rate = s5pc100_getrate_clksrc,
932 .set_rate = s5pc100_setrate_clksrc,
933 .round_rate = s5pc100_roundrate_clksrc,
934 },
935 .shift = S5PC100_CLKSRC2_MMC2_SHIFT,
936 .mask = S5PC100_CLKSRC2_MMC2_MASK,
937 .sources = &clkset_mmc,
938 .divider_shift = S5PC100_CLKDIV3_MMC2_SHIFT,
939 .reg_divider = S5PC100_CLKDIV3,
940 .reg_source = S5PC100_CLKSRC2,
941};
942
943
944static struct clk *clkset_usbhost_list[] = {
945 &clk_mout_epll.clk,
946 &clk_dout_mpll,
947 &clk_mout_hpll.clk,
948 &clk_48m,
949};
950
951static struct clk_sources clkset_usbhost = {
952 .sources = clkset_usbhost_list,
953 .nr_sources = ARRAY_SIZE(clkset_usbhost_list),
954};
955
956static struct clksrc_clk clk_usbhost = {
957 .clk = {
958 .name = "usbhost",
959 .id = -1,
960 .ctrlbit = S5PC100_CLKGATE_SCLK0_USBHOST,
961 .enable = s5pc100_sclk0_ctrl,
962 .set_parent = s5pc100_setparent_clksrc,
963 .get_rate = s5pc100_getrate_clksrc,
964 .set_rate = s5pc100_setrate_clksrc,
965 .round_rate = s5pc100_roundrate_clksrc,
966 },
967 .shift = S5PC100_CLKSRC1_UHOST_SHIFT,
968 .mask = S5PC100_CLKSRC1_UHOST_MASK,
969 .sources = &clkset_usbhost,
970 .divider_shift = S5PC100_CLKDIV2_UHOST_SHIFT,
971 .reg_divider = S5PC100_CLKDIV2,
972 .reg_source = S5PC100_CLKSRC1,
1012}; 973};
1013 974
1014/* Clock initialisation code */ 975/* Clock initialisation code */
1015 976
1016static struct clksrc_clk *init_parents[] = { 977static struct clksrc_clk *init_parents[] = {
1017 &clk_mout_apll, 978 &clk_mout_apll,
1018 &clk_mout_epll,
1019 &clk_mout_mpll, 979 &clk_mout_mpll,
980 &clk_mout_am,
981 &clk_mout_onenand,
982 &clk_mout_epll,
983 &clk_mout_hpll,
984 &clk_spi0,
985 &clk_spi1,
986 &clk_spi2,
1020 &clk_uart_uclk1, 987 &clk_uart_uclk1,
988 &clk_audio0,
989 &clk_audio1,
990 &clk_audio2,
991 &clk_spdif,
992 &clk_lcd,
993 &clk_fimc0,
994 &clk_fimc1,
995 &clk_fimc2,
996 &clk_mmc0,
997 &clk_mmc1,
998 &clk_mmc2,
999 &clk_usbhost,
1021}; 1000};
1022 1001
1023static void __init_or_cpufreq s5pc1xx_set_clksrc(struct clksrc_clk *clk) 1002static void __init_or_cpufreq s5pc100_set_clksrc(struct clksrc_clk *clk)
1024{ 1003{
1025 struct clk_sources *srcs = clk->sources; 1004 struct clk_sources *srcs = clk->sources;
1026 u32 clksrc = __raw_readl(clk->reg_source); 1005 u32 clksrc = __raw_readl(clk->reg_source);
@@ -1036,9 +1015,9 @@ static void __init_or_cpufreq s5pc1xx_set_clksrc(struct clksrc_clk *clk)
1036 1015
1037 clk->clk.parent = srcs->sources[clksrc]; 1016 clk->clk.parent = srcs->sources[clksrc];
1038 1017
1039 printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n", 1018 printk(KERN_INFO "%s: source is %s (%d), rate is %ld.%03ld MHz\n",
1040 clk->clk.name, clk->clk.parent->name, clksrc, 1019 clk->clk.name, clk->clk.parent->name, clksrc,
1041 clk_get_rate(&clk->clk)); 1020 print_mhz(clk_get_rate(&clk->clk)));
1042} 1021}
1043 1022
1044#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) 1023#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
@@ -1052,20 +1031,16 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
1052 unsigned long hclk; 1031 unsigned long hclk;
1053 unsigned long pclkd0; 1032 unsigned long pclkd0;
1054 unsigned long pclk; 1033 unsigned long pclk;
1055 unsigned long apll; 1034 unsigned long apll, mpll, epll, hpll;
1056 unsigned long mpll;
1057 unsigned long hpll;
1058 unsigned long epll;
1059 unsigned int ptr; 1035 unsigned int ptr;
1060 u32 clkdiv0, clkdiv1; 1036 u32 clkdiv0, clkdiv1;
1061 1037
1062 printk(KERN_DEBUG "%s: registering clocks\n", __func__); 1038 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1063 1039
1064 clkdiv0 = __raw_readl(S5PC1XX_CLK_DIV0); 1040 clkdiv0 = __raw_readl(S5PC100_CLKDIV0);
1065 clkdiv1 = __raw_readl(S5PC1XX_CLK_DIV1); 1041 clkdiv1 = __raw_readl(S5PC100_CLKDIV1);
1066 1042
1067 printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n", 1043 printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n", __func__, clkdiv0, clkdiv1);
1068 __func__, clkdiv0, clkdiv1);
1069 1044
1070 xtal_clk = clk_get(NULL, "xtal"); 1045 xtal_clk = clk_get(NULL, "xtal");
1071 BUG_ON(IS_ERR(xtal_clk)); 1046 BUG_ON(IS_ERR(xtal_clk));
@@ -1075,48 +1050,81 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
1075 1050
1076 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); 1051 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1077 1052
1078 apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_APLL_CON)); 1053 apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_APLL_CON));
1079 mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_MPLL_CON)); 1054 mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_MPLL_CON));
1080 epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_EPLL_CON)); 1055 epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_EPLL_CON));
1081 hpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_HPLL_CON)); 1056 hpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_HPLL_CON));
1082 1057
1083 printk(KERN_INFO "S5PC100: PLL settings, A=%ld, M=%ld, E=%ld, H=%ld\n", 1058 printk(KERN_INFO "S5PC100: Apll=%ld.%03ld Mhz, Mpll=%ld.%03ld Mhz"
1084 apll, mpll, epll, hpll); 1059 ", Epll=%ld.%03ld Mhz, Hpll=%ld.%03ld Mhz\n",
1060 print_mhz(apll), print_mhz(mpll),
1061 print_mhz(epll), print_mhz(hpll));
1085 1062
1086 armclk = apll / GET_DIV(clkdiv0, S5PC1XX_CLKDIV0_APLL); 1063 armclk = apll / GET_DIV(clkdiv0, S5PC100_CLKDIV0_APLL);
1087 armclk = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_ARM); 1064 armclk = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_ARM);
1088 hclkd0 = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_D0); 1065 hclkd0 = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_D0);
1089 pclkd0 = hclkd0 / GET_DIV(clkdiv0, S5PC100_CLKDIV0_PCLKD0); 1066 pclkd0 = hclkd0 / GET_DIV(clkdiv0, S5PC100_CLKDIV0_PCLKD0);
1090 hclk = mpll / GET_DIV(clkdiv1, S5PC100_CLKDIV1_D1); 1067 hclk = mpll / GET_DIV(clkdiv1, S5PC100_CLKDIV1_D1);
1091 pclk = hclk / GET_DIV(clkdiv1, S5PC100_CLKDIV1_PCLKD1); 1068 pclk = hclk / GET_DIV(clkdiv1, S5PC100_CLKDIV1_PCLKD1);
1092 1069
1093 printk(KERN_INFO "S5PC100: ARMCLK=%ld, HCLKD0=%ld, PCLKD0=%ld, HCLK=%ld, PCLK=%ld\n", 1070 printk(KERN_INFO "S5PC100: ARMCLK=%ld.%03ld MHz, HCLKD0=%ld.%03ld MHz,"
1094 armclk, hclkd0, pclkd0, hclk, pclk); 1071 " PCLKD0=%ld.%03ld MHz\n, HCLK=%ld.%03ld MHz,"
1072 " PCLK=%ld.%03ld MHz\n",
1073 print_mhz(armclk), print_mhz(hclkd0),
1074 print_mhz(pclkd0), print_mhz(hclk), print_mhz(pclk));
1095 1075
1096 clk_fout_apll.rate = apll; 1076 clk_fout_apll.rate = apll;
1097 clk_fout_mpll.rate = mpll; 1077 clk_fout_mpll.rate = mpll;
1098 clk_fout_epll.rate = epll; 1078 clk_fout_epll.rate = epll;
1099 clk_fout_apll.rate = apll; 1079 clk_fout_hpll.rate = hpll;
1100 1080
1101 clk_h.rate = hclk; 1081 clk_h.rate = hclk;
1102 clk_p.rate = pclk; 1082 clk_p.rate = pclk;
1083 clk_f.rate = armclk;
1103 1084
1104 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) 1085 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
1105 s5pc1xx_set_clksrc(init_parents[ptr]); 1086 s5pc100_set_clksrc(init_parents[ptr]);
1106} 1087}
1107 1088
1108static struct clk *clks[] __initdata = { 1089static struct clk *clks[] __initdata = {
1109 &clk_ext_xtal_mux, 1090 &clk_ext_xtal_mux,
1110 &clk_mout_epll.clk, 1091 &clk_mout_apll.clk,
1111 &clk_fout_epll, 1092 &clk_dout_apll,
1093 &clk_dout_d0_bus,
1094 &clk_dout_pclkd0,
1095 &clk_dout_apll2,
1112 &clk_mout_mpll.clk, 1096 &clk_mout_mpll.clk,
1097 &clk_mout_am.clk,
1098 &clk_dout_d1_bus,
1099 &clk_mout_onenand.clk,
1100 &clk_dout_pclkd1,
1101 &clk_dout_mpll2,
1102 &clk_dout_cam,
1113 &clk_dout_mpll, 1103 &clk_dout_mpll,
1104 &clk_mout_epll.clk,
1105 &clk_fout_epll,
1106 &clk_iis_cd0,
1107 &clk_iis_cd1,
1108 &clk_iis_cd2,
1109 &clk_pcm_cd0,
1110 &clk_pcm_cd1,
1111 &clk_spi0.clk,
1112 &clk_spi1.clk,
1113 &clk_spi2.clk,
1114 &clk_uart_uclk1.clk, 1114 &clk_uart_uclk1.clk,
1115 &clk_ext, 1115 &clk_audio0.clk,
1116 &clk_epll, 1116 &clk_audio1.clk,
1117 &clk_27m, 1117 &clk_audio2.clk,
1118 &clk_48m, 1118 &clk_spdif.clk,
1119 &clk_54m, 1119 &clk_lcd.clk,
1120 &clk_fimc0.clk,
1121 &clk_fimc1.clk,
1122 &clk_fimc2.clk,
1123 &clk_mmc0.clk,
1124 &clk_mmc1.clk,
1125 &clk_mmc2.clk,
1126 &clk_usbhost.clk,
1127 &clk_arm,
1120}; 1128};
1121 1129
1122void __init s5pc100_register_clocks(void) 1130void __init s5pc100_register_clocks(void)
@@ -1133,7 +1141,4 @@ void __init s5pc100_register_clocks(void)
1133 clkp->name, ret); 1141 clkp->name, ret);
1134 } 1142 }
1135 } 1143 }
1136
1137 clk_mpll.parent = &clk_mout_mpll.clk;
1138 clk_epll.parent = &clk_mout_epll.clk;
1139} 1144}
diff --git a/arch/arm/plat-s5pc1xx/setup-fb-24bpp.c b/arch/arm/plat-s5pc1xx/setup-fb-24bpp.c
new file mode 100644
index 000000000000..1a63768a9a2e
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/setup-fb-24bpp.c
@@ -0,0 +1,49 @@
1/*
2 * linux/arch/arm/plat-s5pc100/setup-fb-24bpp.c
3 *
4 * Copyright 2009 Samsung Electronics
5 *
6 * Base S5PC1XX setup information for 24bpp LCD framebuffer
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/fb.h>
16#include <linux/gpio.h>
17
18#include <mach/regs-fb.h>
19#include <mach/map.h>
20#include <plat/fb.h>
21#include <plat/gpio-cfg.h>
22#include <plat/gpio-cfg-s5pc1xx.h>
23
24#define DISR_OFFSET 0x7008
25
26void s5pc100_fb_gpio_setup_24bpp(void)
27{
28 unsigned int gpio = 0;
29
30 for (gpio = S5PC100_GPF0(0); gpio <= S5PC100_GPF0(7); gpio++) {
31 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
32 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
33 }
34
35 for (gpio = S5PC100_GPF1(0); gpio <= S5PC100_GPF1(7); gpio++) {
36 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
37 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
38 }
39
40 for (gpio = S5PC100_GPF2(0); gpio <= S5PC100_GPF2(7); gpio++) {
41 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
42 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
43 }
44
45 for (gpio = S5PC100_GPF3(0); gpio <= S5PC100_GPF3(3); gpio++) {
46 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
47 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
48 }
49}
diff --git a/arch/arm/plat-s5pc1xx/setup-i2c0.c b/arch/arm/plat-s5pc1xx/setup-i2c0.c
index 3d00c025fffb..5e4a7c3a231e 100644
--- a/arch/arm/plat-s5pc1xx/setup-i2c0.c
+++ b/arch/arm/plat-s5pc1xx/setup-i2c0.c
@@ -17,9 +17,14 @@
17 17
18struct platform_device; /* don't need the contents */ 18struct platform_device; /* don't need the contents */
19 19
20#include <linux/gpio.h>
20#include <plat/iic.h> 21#include <plat/iic.h>
22#include <plat/gpio-cfg.h>
21 23
22void s3c_i2c0_cfg_gpio(struct platform_device *dev) 24void s3c_i2c0_cfg_gpio(struct platform_device *dev)
23{ 25{
24 /* Pin configuration would be needed */ 26 s3c_gpio_cfgpin(S5PC100_GPD(3), S3C_GPIO_SFN(2));
27 s3c_gpio_setpull(S5PC100_GPD(3), S3C_GPIO_PULL_UP);
28 s3c_gpio_cfgpin(S5PC100_GPD(4), S3C_GPIO_SFN(2));
29 s3c_gpio_setpull(S5PC100_GPD(4), S3C_GPIO_PULL_UP);
25} 30}
diff --git a/arch/arm/plat-s5pc1xx/setup-i2c1.c b/arch/arm/plat-s5pc1xx/setup-i2c1.c
index c8f3ca42f51d..a0a8b4ae6ad8 100644
--- a/arch/arm/plat-s5pc1xx/setup-i2c1.c
+++ b/arch/arm/plat-s5pc1xx/setup-i2c1.c
@@ -17,9 +17,14 @@
17 17
18struct platform_device; /* don't need the contents */ 18struct platform_device; /* don't need the contents */
19 19
20#include <linux/gpio.h>
20#include <plat/iic.h> 21#include <plat/iic.h>
22#include <plat/gpio-cfg.h>
21 23
22void s3c_i2c1_cfg_gpio(struct platform_device *dev) 24void s3c_i2c1_cfg_gpio(struct platform_device *dev)
23{ 25{
24 /* Pin configuration would be needed */ 26 s3c_gpio_cfgpin(S5PC100_GPD(5), S3C_GPIO_SFN(2));
27 s3c_gpio_setpull(S5PC100_GPD(5), S3C_GPIO_PULL_UP);
28 s3c_gpio_cfgpin(S5PC100_GPD(6), S3C_GPIO_SFN(2));
29 s3c_gpio_setpull(S5PC100_GPD(6), S3C_GPIO_PULL_UP);
25} 30}
diff --git a/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c b/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c
new file mode 100644
index 000000000000..185c8941e644
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c
@@ -0,0 +1,86 @@
1/* linux/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c
2 *
3 * Copyright 2009 Samsung Eletronics
4 *
5 * S5PC1XX - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/platform_device.h>
16#include <linux/io.h>
17#include <linux/gpio.h>
18#include <linux/mmc/host.h>
19#include <linux/mmc/card.h>
20
21#include <plat/gpio-cfg.h>
22#include <plat/regs-sdhci.h>
23
24void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
25{
26 unsigned int gpio;
27 unsigned int end;
28 unsigned int num;
29
30 num = width;
31 /* In case of 8 width, we should decrease the 2 */
32 if (width == 8)
33 num = width - 2;
34
35 end = S5PC100_GPG0(2 + num);
36
37 /* Set all the necessary GPG0/GPG1 pins to special-function 0 */
38 for (gpio = S5PC100_GPG0(0); gpio < end; gpio++) {
39 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
40 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
41 }
42
43 if (width == 8) {
44 for (gpio = S5PC100_GPG1(0); gpio <= S5PC100_GPG1(1); gpio++) {
45 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
46 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
47 }
48 }
49
50 s3c_gpio_setpull(S5PC100_GPG1(2), S3C_GPIO_PULL_UP);
51 s3c_gpio_cfgpin(S5PC100_GPG1(2), S3C_GPIO_SFN(2));
52}
53
54void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
55{
56 unsigned int gpio;
57 unsigned int end;
58
59 end = S5PC100_GPG2(2 + width);
60
61 /* Set all the necessary GPG2 pins to special-function 2 */
62 for (gpio = S5PC100_GPG2(0); gpio < end; gpio++) {
63 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
64 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
65 }
66
67 s3c_gpio_setpull(S5PC100_GPG2(6), S3C_GPIO_PULL_UP);
68 s3c_gpio_cfgpin(S5PC100_GPG2(6), S3C_GPIO_SFN(2));
69}
70
71void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
72{
73 unsigned int gpio;
74 unsigned int end;
75
76 end = S5PC100_GPG3(2 + width);
77
78 /* Set all the necessary GPG3 pins to special-function 2 */
79 for (gpio = S5PC100_GPG3(0); gpio < end; gpio++) {
80 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
81 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
82 }
83
84 s3c_gpio_setpull(S5PC100_GPG3(6), S3C_GPIO_PULL_UP);
85 s3c_gpio_cfgpin(S5PC100_GPG3(6), S3C_GPIO_SFN(2));
86}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 12:36:17 -0500