diff options
Diffstat (limited to 'arch/arm/plat-s5pc1xx/include')
-rw-r--r-- | arch/arm/plat-s5pc1xx/include/plat/gpio-cfg-s5pc1xx.h | 32 | ||||
-rw-r--r-- | arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h | 44 | ||||
-rw-r--r-- | arch/arm/plat-s5pc1xx/include/plat/irqs.h | 15 | ||||
-rw-r--r-- | arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h | 70 |
4 files changed, 158 insertions, 3 deletions
diff --git a/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg-s5pc1xx.h b/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg-s5pc1xx.h new file mode 100644 index 000000000000..72ad59f61efc --- /dev/null +++ b/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg-s5pc1xx.h | |||
@@ -0,0 +1,32 @@ | |||
1 | /* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg.h | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronic | ||
4 | * | ||
5 | * S5PC1XX Platform - GPIO pin configuration | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | |||
12 | /* This file contains the necessary definitions to get the basic gpio | ||
13 | * pin configuration done such as setting a pin to input or output or | ||
14 | * changing the pull-{up,down} configurations. | ||
15 | */ | ||
16 | |||
17 | #ifndef __GPIO_CFG_S5PC1XX_H | ||
18 | #define __GPIO_CFG_S5PC1XX_H __FILE__ | ||
19 | |||
20 | typedef unsigned int __bitwise__ s5p_gpio_drvstr_t; | ||
21 | |||
22 | #define S5P_GPIO_DRVSTR_LV1 0x00 | ||
23 | #define S5P_GPIO_DRVSTR_LV2 0x01 | ||
24 | #define S5P_GPIO_DRVSTR_LV3 0x10 | ||
25 | #define S5P_GPIO_DRVSTR_LV4 0x11 | ||
26 | |||
27 | extern s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin, unsigned int off); | ||
28 | |||
29 | extern int s5p_gpio_set_drvstr(unsigned int pin, unsigned int off, | ||
30 | s5p_gpio_drvstr_t drvstr); | ||
31 | |||
32 | #endif /* __GPIO_CFG_S5PC1XX_H */ | ||
diff --git a/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h b/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h new file mode 100644 index 000000000000..33ad267e8477 --- /dev/null +++ b/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h | |||
@@ -0,0 +1,44 @@ | |||
1 | /* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-eint.h | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * | ||
5 | * External Interrupt (GPH0 ~ GPH3) control register definitions | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | |||
12 | #define S5PC1XX_WKUP_INT_CON0_7 (S5PC1XX_EINT_BASE + 0x0) | ||
13 | #define S5PC1XX_WKUP_INT_CON8_15 (S5PC1XX_EINT_BASE + 0x4) | ||
14 | #define S5PC1XX_WKUP_INT_CON16_23 (S5PC1XX_EINT_BASE + 0x8) | ||
15 | #define S5PC1XX_WKUP_INT_CON24_31 (S5PC1XX_EINT_BASE + 0xC) | ||
16 | #define S5PC1XX_WKUP_INT_CON(x) (S5PC1XX_WKUP_INT_CON0_7 + (x * 0x4)) | ||
17 | |||
18 | #define S5PC1XX_WKUP_INT_FLTCON0_3 (S5PC1XX_EINT_BASE + 0x80) | ||
19 | #define S5PC1XX_WKUP_INT_FLTCON4_7 (S5PC1XX_EINT_BASE + 0x84) | ||
20 | #define S5PC1XX_WKUP_INT_FLTCON8_11 (S5PC1XX_EINT_BASE + 0x88) | ||
21 | #define S5PC1XX_WKUP_INT_FLTCON12_15 (S5PC1XX_EINT_BASE + 0x8C) | ||
22 | #define S5PC1XX_WKUP_INT_FLTCON16_19 (S5PC1XX_EINT_BASE + 0x90) | ||
23 | #define S5PC1XX_WKUP_INT_FLTCON20_23 (S5PC1XX_EINT_BASE + 0x94) | ||
24 | #define S5PC1XX_WKUP_INT_FLTCON24_27 (S5PC1XX_EINT_BASE + 0x98) | ||
25 | #define S5PC1XX_WKUP_INT_FLTCON28_31 (S5PC1XX_EINT_BASE + 0x9C) | ||
26 | #define S5PC1XX_WKUP_INT_FLTCON(x) (S5PC1XX_WKUP_INT_FLTCON0_3 + (x * 0x4)) | ||
27 | |||
28 | #define S5PC1XX_WKUP_INT_MASK0_7 (S5PC1XX_EINT_BASE + 0x100) | ||
29 | #define S5PC1XX_WKUP_INT_MASK8_15 (S5PC1XX_EINT_BASE + 0x104) | ||
30 | #define S5PC1XX_WKUP_INT_MASK16_23 (S5PC1XX_EINT_BASE + 0x108) | ||
31 | #define S5PC1XX_WKUP_INT_MASK24_31 (S5PC1XX_EINT_BASE + 0x10C) | ||
32 | #define S5PC1XX_WKUP_INT_MASK(x) (S5PC1XX_WKUP_INT_MASK0_7 + (x * 0x4)) | ||
33 | |||
34 | #define S5PC1XX_WKUP_INT_PEND0_7 (S5PC1XX_EINT_BASE + 0x140) | ||
35 | #define S5PC1XX_WKUP_INT_PEND8_15 (S5PC1XX_EINT_BASE + 0x144) | ||
36 | #define S5PC1XX_WKUP_INT_PEND16_23 (S5PC1XX_EINT_BASE + 0x148) | ||
37 | #define S5PC1XX_WKUP_INT_PEND24_31 (S5PC1XX_EINT_BASE + 0x14C) | ||
38 | #define S5PC1XX_WKUP_INT_PEND(x) (S5PC1XX_WKUP_INT_PEND0_7 + (x * 0x4)) | ||
39 | |||
40 | #define S5PC1XX_WKUP_INT_LOWLEV (0x00) | ||
41 | #define S5PC1XX_WKUP_INT_HILEV (0x01) | ||
42 | #define S5PC1XX_WKUP_INT_FALLEDGE (0x02) | ||
43 | #define S5PC1XX_WKUP_INT_RISEEDGE (0x03) | ||
44 | #define S5PC1XX_WKUP_INT_BOTHEDGE (0x04) | ||
diff --git a/arch/arm/plat-s5pc1xx/include/plat/irqs.h b/arch/arm/plat-s5pc1xx/include/plat/irqs.h index f07d8c3b25d6..ef8736366f0d 100644 --- a/arch/arm/plat-s5pc1xx/include/plat/irqs.h +++ b/arch/arm/plat-s5pc1xx/include/plat/irqs.h | |||
@@ -171,12 +171,21 @@ | |||
171 | #define IRQ_SDMIRQ S5PC1XX_IRQ_VIC2(30) | 171 | #define IRQ_SDMIRQ S5PC1XX_IRQ_VIC2(30) |
172 | #define IRQ_SDMFIQ S5PC1XX_IRQ_VIC2(31) | 172 | #define IRQ_SDMFIQ S5PC1XX_IRQ_VIC2(31) |
173 | 173 | ||
174 | /* External interrupt */ | ||
174 | #define S3C_IRQ_EINT_BASE (IRQ_SDMFIQ + 1) | 175 | #define S3C_IRQ_EINT_BASE (IRQ_SDMFIQ + 1) |
175 | 176 | ||
176 | #define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE) | 177 | #define S3C_EINT(x) (S3C_IRQ_EINT_BASE + (x - 16)) |
177 | #define IRQ_EINT(x) S3C_EINT(x) | 178 | #define IRQ_EINT(x) (x < 16 ? IRQ_EINT0 + x : S3C_EINT(x)) |
179 | #define IRQ_EINT_BIT(x) (x < IRQ_EINT16_31 ? x - IRQ_EINT0 : x - S3C_EINT(0)) | ||
178 | 180 | ||
179 | #define NR_IRQS (IRQ_EINT(31)+1) | 181 | /* GPIO interrupt */ |
182 | #define S3C_IRQ_GPIO_BASE (IRQ_EINT(31) + 1) | ||
183 | #define S3C_IRQ_GPIO(x) (S3C_IRQ_GPIO_BASE + (x)) | ||
184 | |||
185 | /* | ||
186 | * Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs | ||
187 | */ | ||
188 | #define NR_IRQS (S3C_IRQ_GPIO(320) + 1) | ||
180 | 189 | ||
181 | #endif /* __ASM_PLAT_S5PC1XX_IRQS_H */ | 190 | #endif /* __ASM_PLAT_S5PC1XX_IRQS_H */ |
182 | 191 | ||
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h b/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h new file mode 100644 index 000000000000..43c7bc8bf784 --- /dev/null +++ b/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h | |||
@@ -0,0 +1,70 @@ | |||
1 | /* linux/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * S5PC1XX - GPIO register definitions | ||
7 | */ | ||
8 | |||
9 | #ifndef __ASM_PLAT_S5PC1XX_REGS_GPIO_H | ||
10 | #define __ASM_PLAT_S5PC1XX_REGS_GPIO_H __FILE__ | ||
11 | |||
12 | #include <mach/map.h> | ||
13 | |||
14 | /* S5PC100 */ | ||
15 | #define S5PC100_GPIO_BASE S5PC1XX_VA_GPIO | ||
16 | #define S5PC100_GPA0_BASE (S5PC100_GPIO_BASE + 0x0000) | ||
17 | #define S5PC100_GPA1_BASE (S5PC100_GPIO_BASE + 0x0020) | ||
18 | #define S5PC100_GPB_BASE (S5PC100_GPIO_BASE + 0x0040) | ||
19 | #define S5PC100_GPC_BASE (S5PC100_GPIO_BASE + 0x0060) | ||
20 | #define S5PC100_GPD_BASE (S5PC100_GPIO_BASE + 0x0080) | ||
21 | #define S5PC100_GPE0_BASE (S5PC100_GPIO_BASE + 0x00A0) | ||
22 | #define S5PC100_GPE1_BASE (S5PC100_GPIO_BASE + 0x00C0) | ||
23 | #define S5PC100_GPF0_BASE (S5PC100_GPIO_BASE + 0x00E0) | ||
24 | #define S5PC100_GPF1_BASE (S5PC100_GPIO_BASE + 0x0100) | ||
25 | #define S5PC100_GPF2_BASE (S5PC100_GPIO_BASE + 0x0120) | ||
26 | #define S5PC100_GPF3_BASE (S5PC100_GPIO_BASE + 0x0140) | ||
27 | #define S5PC100_GPG0_BASE (S5PC100_GPIO_BASE + 0x0160) | ||
28 | #define S5PC100_GPG1_BASE (S5PC100_GPIO_BASE + 0x0180) | ||
29 | #define S5PC100_GPG2_BASE (S5PC100_GPIO_BASE + 0x01A0) | ||
30 | #define S5PC100_GPG3_BASE (S5PC100_GPIO_BASE + 0x01C0) | ||
31 | #define S5PC100_GPH0_BASE (S5PC100_GPIO_BASE + 0x0C00) | ||
32 | #define S5PC100_GPH1_BASE (S5PC100_GPIO_BASE + 0x0C20) | ||
33 | #define S5PC100_GPH2_BASE (S5PC100_GPIO_BASE + 0x0C40) | ||
34 | #define S5PC100_GPH3_BASE (S5PC100_GPIO_BASE + 0x0C60) | ||
35 | #define S5PC100_GPI_BASE (S5PC100_GPIO_BASE + 0x01E0) | ||
36 | #define S5PC100_GPJ0_BASE (S5PC100_GPIO_BASE + 0x0200) | ||
37 | #define S5PC100_GPJ1_BASE (S5PC100_GPIO_BASE + 0x0220) | ||
38 | #define S5PC100_GPJ2_BASE (S5PC100_GPIO_BASE + 0x0240) | ||
39 | #define S5PC100_GPJ3_BASE (S5PC100_GPIO_BASE + 0x0260) | ||
40 | #define S5PC100_GPJ4_BASE (S5PC100_GPIO_BASE + 0x0280) | ||
41 | #define S5PC100_GPK0_BASE (S5PC100_GPIO_BASE + 0x02A0) | ||
42 | #define S5PC100_GPK1_BASE (S5PC100_GPIO_BASE + 0x02C0) | ||
43 | #define S5PC100_GPK2_BASE (S5PC100_GPIO_BASE + 0x02E0) | ||
44 | #define S5PC100_GPK3_BASE (S5PC100_GPIO_BASE + 0x0300) | ||
45 | #define S5PC100_GPL0_BASE (S5PC100_GPIO_BASE + 0x0320) | ||
46 | #define S5PC100_GPL1_BASE (S5PC100_GPIO_BASE + 0x0340) | ||
47 | #define S5PC100_GPL2_BASE (S5PC100_GPIO_BASE + 0x0360) | ||
48 | #define S5PC100_GPL3_BASE (S5PC100_GPIO_BASE + 0x0380) | ||
49 | #define S5PC100_GPL4_BASE (S5PC100_GPIO_BASE + 0x03A0) | ||
50 | #define S5PC100_EINT_BASE (S5PC100_GPIO_BASE + 0x0E00) | ||
51 | |||
52 | #define S5PC100_UHOST (S5PC100_GPIO_BASE + 0x0B68) | ||
53 | #define S5PC100_PDNEN (S5PC100_GPIO_BASE + 0x0F80) | ||
54 | |||
55 | /* PDNEN */ | ||
56 | #define S5PC100_PDNEN_CFG_PDNEN (1 << 1) | ||
57 | #define S5PC100_PDNEN_CFG_AUTO (0 << 1) | ||
58 | #define S5PC100_PDNEN_POWERDOWN (1 << 0) | ||
59 | #define S5PC100_PDNEN_NORMAL (0 << 0) | ||
60 | |||
61 | /* Common part */ | ||
62 | /* External interrupt base is same at both s5pc100 and s5pc110 */ | ||
63 | #define S5PC1XX_EINT_BASE (S5PC100_EINT_BASE) | ||
64 | |||
65 | #define S5PC100_GPx_INPUT(__gpio) (0x0 << ((__gpio) * 4)) | ||
66 | #define S5PC100_GPx_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) | ||
67 | #define S5PC100_GPx_CONMASK(__gpio) (0xf << ((__gpio) * 4)) | ||
68 | |||
69 | #endif /* __ASM_PLAT_S5PC1XX_REGS_GPIO_H */ | ||
70 | |||