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-rw-r--r--arch/arm/plat-s5p/Kconfig7
-rw-r--r--arch/arm/plat-s5p/Makefile2
-rw-r--r--arch/arm/plat-s5p/cpu.c10
-rw-r--r--arch/arm/plat-s5p/include/plat/s5pc100.h33
-rw-r--r--arch/arm/plat-s5p/irq-eint.c213
5 files changed, 264 insertions, 1 deletions
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 92bd75607b43..5cb2dd1da632 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -7,7 +7,7 @@
7 7
8config PLAT_S5P 8config PLAT_S5P
9 bool 9 bool
10 depends on (ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PV210) 10 depends on (ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210)
11 default y 11 default y
12 select ARM_VIC 12 select ARM_VIC
13 select NO_IOPORT 13 select NO_IOPORT
@@ -24,3 +24,8 @@ config PLAT_S5P
24 select SAMSUNG_IRQ_UART 24 select SAMSUNG_IRQ_UART
25 help 25 help
26 Base platform code for Samsung's S5P series SoC. 26 Base platform code for Samsung's S5P series SoC.
27
28config S5P_EXT_INT
29 bool
30 help
31 Use the external interrupts (other than GPIO interrupts.)
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index 0ec09a9c36bd..39c242bb9d58 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -16,3 +16,5 @@ obj-y += dev-uart.o
16obj-y += cpu.o 16obj-y += cpu.o
17obj-y += clock.o 17obj-y += clock.o
18obj-y += irq.o 18obj-y += irq.o
19obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o
20
diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
index f92e5de3a755..75cb8c37ca2c 100644
--- a/arch/arm/plat-s5p/cpu.c
+++ b/arch/arm/plat-s5p/cpu.c
@@ -19,12 +19,14 @@
19#include <plat/cpu.h> 19#include <plat/cpu.h>
20#include <plat/s5p6440.h> 20#include <plat/s5p6440.h>
21#include <plat/s5p6442.h> 21#include <plat/s5p6442.h>
22#include <plat/s5pc100.h>
22#include <plat/s5pv210.h> 23#include <plat/s5pv210.h>
23 24
24/* table of supported CPUs */ 25/* table of supported CPUs */
25 26
26static const char name_s5p6440[] = "S5P6440"; 27static const char name_s5p6440[] = "S5P6440";
27static const char name_s5p6442[] = "S5P6442"; 28static const char name_s5p6442[] = "S5P6442";
29static const char name_s5pc100[] = "S5PC100";
28static const char name_s5pv210[] = "S5PV210/S5PC110"; 30static const char name_s5pv210[] = "S5PV210/S5PC110";
29 31
30static struct cpu_table cpu_ids[] __initdata = { 32static struct cpu_table cpu_ids[] __initdata = {
@@ -45,6 +47,14 @@ static struct cpu_table cpu_ids[] __initdata = {
45 .init = s5p6442_init, 47 .init = s5p6442_init,
46 .name = name_s5p6442, 48 .name = name_s5p6442,
47 }, { 49 }, {
50 .idcode = 0x43100000,
51 .idmask = 0xfffff000,
52 .map_io = s5pc100_map_io,
53 .init_clocks = s5pc100_init_clocks,
54 .init_uarts = s5pc100_init_uarts,
55 .init = s5pc100_init,
56 .name = name_s5pc100,
57 }, {
48 .idcode = 0x43110000, 58 .idcode = 0x43110000,
49 .idmask = 0xfffff000, 59 .idmask = 0xfffff000,
50 .map_io = s5pv210_map_io, 60 .map_io = s5pv210_map_io,
diff --git a/arch/arm/plat-s5p/include/plat/s5pc100.h b/arch/arm/plat-s5p/include/plat/s5pc100.h
new file mode 100644
index 000000000000..5f6099dd7cad
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/s5pc100.h
@@ -0,0 +1,33 @@
1/* arch/arm/plat-s5p/include/plat/s5pc100.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Header file for s5pc100 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* Common init code for S5PC100 related SoCs */
14
15extern void s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
16extern void s5pc100_register_clocks(void);
17extern void s5pc100_setup_clocks(void);
18
19#ifdef CONFIG_CPU_S5PC100
20
21extern int s5pc100_init(void);
22extern void s5pc100_init_irq(void);
23extern void s5pc100_map_io(void);
24extern void s5pc100_init_clocks(int xtal);
25
26#define s5pc100_init_uarts s5pc100_common_init_uarts
27
28#else
29#define s5pc100_init_clocks NULL
30#define s5pc100_init_uarts NULL
31#define s5pc100_map_io NULL
32#define s5pc100_init NULL
33#endif
diff --git a/arch/arm/plat-s5p/irq-eint.c b/arch/arm/plat-s5p/irq-eint.c
new file mode 100644
index 000000000000..eaa70aa0127b
--- /dev/null
+++ b/arch/arm/plat-s5p/irq-eint.c
@@ -0,0 +1,213 @@
1/* linux/arch/arm/plat-s5p/irq-eint.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P - IRQ EINT support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17#include <linux/sysdev.h>
18#include <linux/gpio.h>
19
20#include <asm/hardware/vic.h>
21
22#include <plat/regs-irqtype.h>
23
24#include <mach/map.h>
25#include <plat/cpu.h>
26#include <plat/pm.h>
27
28#include <plat/gpio-cfg.h>
29#include <mach/regs-gpio.h>
30
31static inline void s5p_irq_eint_mask(unsigned int irq)
32{
33 u32 mask;
34
35 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq)));
36 mask |= eint_irq_to_bit(irq);
37 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq)));
38}
39
40static void s5p_irq_eint_unmask(unsigned int irq)
41{
42 u32 mask;
43
44 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq)));
45 mask &= ~(eint_irq_to_bit(irq));
46 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq)));
47}
48
49static inline void s5p_irq_eint_ack(unsigned int irq)
50{
51 __raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq)));
52}
53
54static void s5p_irq_eint_maskack(unsigned int irq)
55{
56 /* compiler should in-line these */
57 s5p_irq_eint_mask(irq);
58 s5p_irq_eint_ack(irq);
59}
60
61static int s5p_irq_eint_set_type(unsigned int irq, unsigned int type)
62{
63 int offs = eint_offset(irq);
64 int shift;
65 u32 ctrl, mask;
66 u32 newvalue = 0;
67
68 switch (type) {
69 case IRQ_TYPE_EDGE_RISING:
70 newvalue = S5P_EXTINT_RISEEDGE;
71 break;
72
73 case IRQ_TYPE_EDGE_FALLING:
74 newvalue = S5P_EXTINT_RISEEDGE;
75 break;
76
77 case IRQ_TYPE_EDGE_BOTH:
78 newvalue = S5P_EXTINT_BOTHEDGE;
79 break;
80
81 case IRQ_TYPE_LEVEL_LOW:
82 newvalue = S5P_EXTINT_LOWLEV;
83 break;
84
85 case IRQ_TYPE_LEVEL_HIGH:
86 newvalue = S5P_EXTINT_HILEV;
87 break;
88
89 default:
90 printk(KERN_ERR "No such irq type %d", type);
91 return -EINVAL;
92 }
93
94 shift = (offs & 0x7) * 4;
95 mask = 0x7 << shift;
96
97 ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(irq)));
98 ctrl &= ~mask;
99 ctrl |= newvalue << shift;
100 __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(irq)));
101
102 if ((0 <= offs) && (offs < 8))
103 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
104
105 else if ((8 <= offs) && (offs < 16))
106 s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
107
108 else if ((16 <= offs) && (offs < 24))
109 s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
110
111 else if ((24 <= offs) && (offs < 32))
112 s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
113
114 else
115 printk(KERN_ERR "No such irq number %d", offs);
116
117 return 0;
118}
119
120static struct irq_chip s5p_irq_eint = {
121 .name = "s5p-eint",
122 .mask = s5p_irq_eint_mask,
123 .unmask = s5p_irq_eint_unmask,
124 .mask_ack = s5p_irq_eint_maskack,
125 .ack = s5p_irq_eint_ack,
126 .set_type = s5p_irq_eint_set_type,
127#ifdef CONFIG_PM
128 .set_wake = s3c_irqext_wake,
129#endif
130};
131
132/* s5p_irq_demux_eint
133 *
134 * This function demuxes the IRQ from the group0 external interrupts,
135 * from EINTs 16 to 31. It is designed to be inlined into the specific
136 * handler s5p_irq_demux_eintX_Y.
137 *
138 * Each EINT pend/mask registers handle eight of them.
139 */
140static inline void s5p_irq_demux_eint(unsigned int start)
141{
142 u32 status;
143 u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
144 unsigned int irq;
145
146 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
147 status &= ~mask;
148 status &= 0xff;
149
150 while (status) {
151 irq = fls(status);
152 generic_handle_irq(irq - 1 + start);
153 status &= ~(1 << irq);
154 }
155}
156
157static void s5p_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
158{
159 s5p_irq_demux_eint(IRQ_EINT(16));
160 s5p_irq_demux_eint(IRQ_EINT(24));
161}
162
163static inline void s5p_irq_vic_eint_mask(unsigned int irq)
164{
165 s5p_irq_eint_mask(irq);
166}
167
168static void s5p_irq_vic_eint_unmask(unsigned int irq)
169{
170 s5p_irq_eint_unmask(irq);
171}
172
173static inline void s5p_irq_vic_eint_ack(unsigned int irq)
174{
175 __raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq)));
176}
177
178static void s5p_irq_vic_eint_maskack(unsigned int irq)
179{
180 s5p_irq_vic_eint_mask(irq);
181 s5p_irq_vic_eint_ack(irq);
182}
183
184static struct irq_chip s5p_irq_vic_eint = {
185 .name = "s5p_vic_eint",
186 .mask = s5p_irq_vic_eint_mask,
187 .unmask = s5p_irq_vic_eint_unmask,
188 .mask_ack = s5p_irq_vic_eint_maskack,
189 .ack = s5p_irq_vic_eint_ack,
190 .set_type = s5p_irq_eint_set_type,
191#ifdef CONFIG_PM
192 .set_wake = s3c_irqext_wake,
193#endif
194};
195
196int __init s5p_init_irq_eint(void)
197{
198 int irq;
199
200 for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++)
201 set_irq_chip(irq, &s5p_irq_vic_eint);
202
203 for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) {
204 set_irq_chip(irq, &s5p_irq_eint);
205 set_irq_handler(irq, handle_level_irq);
206 set_irq_flags(irq, IRQF_VALID);
207 }
208
209 set_irq_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31);
210 return 0;
211}
212
213arch_initcall(s5p_init_irq_eint);
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-24 20:40:23 -0400