10 files changed, 288 insertions, 23 deletions

diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index e98f5c5c7879..9843c954c042 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -39,6 +39,7 @@ config S5P_GPIO_INT
 
 config S5P_HRT
         bool
+        select SAMSUNG_DEV_PWM
         help
           Use the High Resolution timer support
 
@@ -70,6 +71,16 @@ config S5P_DEV_FIMC3
         help
           Compile in platform device definitions for FIMC controller 3
 
+config S5P_DEV_FIMD0
+        bool
+        help
+          Compile in platform device definitions for FIMD controller 0
+
+config S5P_DEV_MFC
+        bool
+        help
+          Compile in platform device definitions for MFC
+
 config S5P_DEV_ONENAND
         bool
         help
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index e234cc4d49a0..4b53e04eeca4 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -25,11 +25,12 @@ obj-$(CONFIG_PM)		+= irq-pm.o
 obj-$(CONFIG_S5P_HRT)           += s5p-time.o
 
 # devices
-
+obj-$(CONFIG_S5P_DEV_MFC)       += dev-mfc.o
 obj-$(CONFIG_S5P_DEV_FIMC0)     += dev-fimc0.o
 obj-$(CONFIG_S5P_DEV_FIMC1)     += dev-fimc1.o
 obj-$(CONFIG_S5P_DEV_FIMC2)     += dev-fimc2.o
 obj-$(CONFIG_S5P_DEV_FIMC3)     += dev-fimc3.o
+obj-$(CONFIG_S5P_DEV_FIMD0)     += dev-fimd0.o
 obj-$(CONFIG_S5P_DEV_ONENAND)   += dev-onenand.o
 obj-$(CONFIG_S5P_DEV_CSIS0)     += dev-csis0.o
 obj-$(CONFIG_S5P_DEV_CSIS1)     += dev-csis1.o
diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c
index 8d081d968c58..02af235298e2 100644
--- a/arch/arm/plat-s5p/clock.c
+++ b/arch/arm/plat-s5p/clock.c
@@ -168,6 +168,41 @@ unsigned long s5p_epll_get_rate(struct clk *clk)
         return clk->rate;
 }
 
+int s5p_spdif_set_rate(struct clk *clk, unsigned long rate)
+{
+        struct clk *pclk;
+        int ret;
+
+        pclk = clk_get_parent(clk);
+        if (IS_ERR(pclk))
+                return -EINVAL;
+
+        ret = pclk->ops->set_rate(pclk, rate);
+        clk_put(pclk);
+
+        return ret;
+}
+
+unsigned long s5p_spdif_get_rate(struct clk *clk)
+{
+        struct clk *pclk;
+        int rate;
+
+        pclk = clk_get_parent(clk);
+        if (IS_ERR(pclk))
+                return -EINVAL;
+
+        rate = pclk->ops->get_rate(clk);
+        clk_put(pclk);
+
+        return rate;
+}
+
+struct clk_ops s5p_sclk_spdif_ops = {
+        .set_rate       = s5p_spdif_set_rate,
+        .get_rate       = s5p_spdif_get_rate,
+};
+
 static struct clk *s5p_clks[] __initdata = {
         &clk_ext_xtal_mux,
         &clk_48m,
diff --git a/arch/arm/plat-s5p/dev-fimd0.c b/arch/arm/plat-s5p/dev-fimd0.c
new file mode 100644
index 000000000000..f728bb5abcef
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-fimd0.c
@@ -0,0 +1,67 @@
+/* linux/arch/arm/plat-s5p/dev-fimd0.c
+ *
+ * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Core file for Samsung Display Controller (FIMD) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+#include <linux/fb.h>
+#include <linux/gfp.h>
+#include <linux/dma-mapping.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include <plat/fb.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+static struct resource s5p_fimd0_resource[] = {
+        [0] = {
+                .start  = S5P_PA_FIMD0,
+                .end    = S5P_PA_FIMD0 + SZ_32K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_FIMD0_VSYNC,
+                .end    = IRQ_FIMD0_VSYNC,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = IRQ_FIMD0_FIFO,
+                .end    = IRQ_FIMD0_FIFO,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = IRQ_FIMD0_SYSTEM,
+                .end    = IRQ_FIMD0_SYSTEM,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 fimd0_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device s5p_device_fimd0 = {
+        .name           = "s5p-fb",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(s5p_fimd0_resource),
+        .resource       = s5p_fimd0_resource,
+        .dev            = {
+                .dma_mask               = &fimd0_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+void __init s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd)
+{
+        s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
+                        &s5p_device_fimd0);
+}
diff --git a/arch/arm/plat-s5p/dev-mfc.c b/arch/arm/plat-s5p/dev-mfc.c
new file mode 100644
index 000000000000..94226a0010f7
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-mfc.c
@@ -0,0 +1,123 @@
+/* linux/arch/arm/plat-s5p/dev-mfc.c
+ *
+ * Copyright (C) 2010-2011 Samsung Electronics Co.Ltd
+ *
+ * Base S5P MFC resource and device definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/memblock.h>
+#include <linux/ioport.h>
+
+#include <mach/map.h>
+#include <plat/devs.h>
+#include <plat/irqs.h>
+#include <plat/mfc.h>
+
+static struct resource s5p_mfc_resource[] = {
+        [0] = {
+                .start  = S5P_PA_MFC,
+                .end    = S5P_PA_MFC + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_MFC,
+                .end    = IRQ_MFC,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device s5p_device_mfc = {
+        .name           = "s5p-mfc",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(s5p_mfc_resource),
+        .resource       = s5p_mfc_resource,
+};
+
+/*
+ * MFC hardware has 2 memory interfaces which are modelled as two separate
+ * platform devices to let dma-mapping distinguish between them.
+ *
+ * MFC parent device (s5p_device_mfc) must be registered before memory
+ * interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r).
+ */
+
+static u64 s5p_mfc_dma_mask = DMA_BIT_MASK(32);
+
+struct platform_device s5p_device_mfc_l = {
+        .name           = "s5p-mfc-l",
+        .id             = -1,
+        .dev            = {
+                .parent                 = &s5p_device_mfc.dev,
+                .dma_mask               = &s5p_mfc_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+struct platform_device s5p_device_mfc_r = {
+        .name           = "s5p-mfc-r",
+        .id             = -1,
+        .dev            = {
+                .parent                 = &s5p_device_mfc.dev,
+                .dma_mask               = &s5p_mfc_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+struct s5p_mfc_reserved_mem {
+        phys_addr_t     base;
+        unsigned long   size;
+        struct device   *dev;
+};
+
+static struct s5p_mfc_reserved_mem s5p_mfc_mem[2] __initdata;
+
+void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
+                                phys_addr_t lbase, unsigned int lsize)
+{
+        int i;
+
+        s5p_mfc_mem[0].dev = &s5p_device_mfc_r.dev;
+        s5p_mfc_mem[0].base = rbase;
+        s5p_mfc_mem[0].size = rsize;
+
+        s5p_mfc_mem[1].dev = &s5p_device_mfc_l.dev;
+        s5p_mfc_mem[1].base = lbase;
+        s5p_mfc_mem[1].size = lsize;
+
+        for (i = 0; i < ARRAY_SIZE(s5p_mfc_mem); i++) {
+                struct s5p_mfc_reserved_mem *area = &s5p_mfc_mem[i];
+                if (memblock_remove(area->base, area->size)) {
+                        printk(KERN_ERR "Failed to reserve memory for MFC device (%ld bytes at 0x%08lx)\n",
+                               area->size, (unsigned long) area->base);
+                        area->base = 0;
+                }
+        }
+}
+
+static int __init s5p_mfc_memory_init(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(s5p_mfc_mem); i++) {
+                struct s5p_mfc_reserved_mem *area = &s5p_mfc_mem[i];
+                if (!area->base)
+                        continue;
+
+                if (dma_declare_coherent_memory(area->dev, area->base,
+                                area->base, area->size,
+                                DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0)
+                        printk(KERN_ERR "Failed to declare coherent memory for MFC device (%ld bytes at 0x%08lx)\n",
+                               area->size, (unsigned long) area->base);
+        }
+        return 0;
+}
+device_initcall(s5p_mfc_memory_init);
diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-s5p/include/plat/map-s5p.h
index d973d39666a3..36d3551173b2 100644
--- a/arch/arm/plat-s5p/include/plat/map-s5p.h
+++ b/arch/arm/plat-s5p/include/plat/map-s5p.h
@@ -35,9 +35,10 @@
 #define S5P_VA_COREPERI_BASE    S3C_ADDR(0x02800000)
 #define S5P_VA_COREPERI(x)      (S5P_VA_COREPERI_BASE + (x))
 #define S5P_VA_SCU              S5P_VA_COREPERI(0x0)
-#define S5P_VA_GIC_CPU          S5P_VA_COREPERI(0x100)
 #define S5P_VA_TWD              S5P_VA_COREPERI(0x600)
-#define S5P_VA_GIC_DIST         S5P_VA_COREPERI(0x1000)
+
+#define S5P_VA_GIC_CPU          S3C_ADDR(0x02810000)
+#define S5P_VA_GIC_DIST         S3C_ADDR(0x02820000)
 
 #define S3C_VA_USB_HSPHY        S3C_ADDR(0x02900000)
 
diff --git a/arch/arm/plat-s5p/include/plat/mfc.h b/arch/arm/plat-s5p/include/plat/mfc.h
new file mode 100644
index 000000000000..6697f8cb2949
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/mfc.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co.Ltd
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __PLAT_S5P_MFC_H
+#define __PLAT_S5P_MFC_H
+
+/**
+ * s5p_mfc_reserve_mem - function to early reserve memory for MFC driver
+ * @rbase:      base address for MFC 'right' memory interface
+ * @rsize:      size of the memory reserved for MFC 'right' interface
+ * @lbase:      base address for MFC 'left' memory interface
+ * @lsize:      size of the memory reserved for MFC 'left' interface
+ *
+ * This function reserves system memory for both MFC device memory
+ * interfaces and registers it to respective struct device entries as
+ * coherent memory.
+ */
+void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
+                                phys_addr_t lbase, unsigned int lsize);
+
+#endif /* __PLAT_S5P_MFC_H */
diff --git a/arch/arm/plat-s5p/include/plat/s5p-clock.h b/arch/arm/plat-s5p/include/plat/s5p-clock.h
index 2b6dcff8ab2b..769b5bdfb046 100644
--- a/arch/arm/plat-s5p/include/plat/s5p-clock.h
+++ b/arch/arm/plat-s5p/include/plat/s5p-clock.h
@@ -47,4 +47,9 @@ extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable);
 extern int s5p_epll_enable(struct clk *clk, int enable);
 extern unsigned long s5p_epll_get_rate(struct clk *clk);
 
+/* SPDIF clk operations common for S5PC100/V210/C110 and Exynos4 */
+extern int s5p_spdif_set_rate(struct clk *clk, unsigned long rate);
+extern unsigned long s5p_spdif_get_rate(struct clk *clk);
+
+extern struct clk_ops s5p_sclk_spdif_ops;
 #endif /* __ASM_PLAT_S5P_CLOCK_H */
diff --git a/arch/arm/plat-s5p/s5p-time.c b/arch/arm/plat-s5p/s5p-time.c
index 612934c48b0d..c833e7b57599 100644
--- a/arch/arm/plat-s5p/s5p-time.c
+++ b/arch/arm/plat-s5p/s5p-time.c
@@ -314,13 +314,6 @@ static void __iomem *s5p_timer_reg(void)
         return S3C_TIMERREG(offset);
 }
 
-static cycle_t s5p_timer_read(struct clocksource *cs)
-{
-        void __iomem *reg = s5p_timer_reg();
-
-        return (cycle_t) (reg ? ~__raw_readl(reg) : 0);
-}
-
 /*
  * Override the global weak sched_clock symbol with this
  * local implementation which uses the clocksource to get some
@@ -350,14 +343,6 @@ static void notrace s5p_update_sched_clock(void)
         update_sched_clock(&cd, ~__raw_readl(reg), (u32)~0);
 }
 
-struct clocksource time_clocksource = {
-        .name           = "s5p_clocksource_timer",
-        .rating         = 250,
-        .read           = s5p_timer_read,
-        .mask           = CLOCKSOURCE_MASK(32),
-        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
 static void __init s5p_clocksource_init(void)
 {
         unsigned long pclk;
@@ -375,8 +360,9 @@ static void __init s5p_clocksource_init(void)
 
         init_sched_clock(&cd, s5p_update_sched_clock, 32, clock_rate);
 
-        if (clocksource_register_hz(&time_clocksource, clock_rate))
-                panic("%s: can't register clocksource\n", time_clocksource.name);
+        if (clocksource_mmio_init(s5p_timer_reg(), "s5p_clocksource_timer",
+                        clock_rate, 250, 32, clocksource_mmio_readl_down))
+                panic("s5p_clocksource_timer: can't register clocksource\n");
 }
 
 static void __init s5p_timer_resources(void)
@@ -384,6 +370,7 @@ static void __init s5p_timer_resources(void)
 
         unsigned long event_id = timer_source.event_id;
         unsigned long source_id = timer_source.source_id;
+        char devname[15];
 
         timerclk = clk_get(NULL, "timers");
         if (IS_ERR(timerclk))
@@ -391,6 +378,10 @@ static void __init s5p_timer_resources(void)
 
         clk_enable(timerclk);
 
+        sprintf(devname, "s3c24xx-pwm.%lu", event_id);
+        s3c_device_timer[event_id].id = event_id;
+        s3c_device_timer[event_id].dev.init_name = devname;
+
         tin_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tin");
         if (IS_ERR(tin_event))
                 panic("failed to get pwm-tin clock for event timer");
@@ -401,6 +392,10 @@ static void __init s5p_timer_resources(void)
 
         clk_enable(tin_event);
 
+        sprintf(devname, "s3c24xx-pwm.%lu", source_id);
+        s3c_device_timer[source_id].id = source_id;
+        s3c_device_timer[source_id].dev.init_name = devname;
+
         tin_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tin");
         if (IS_ERR(tin_source))
                 panic("failed to get pwm-tin clock for source timer");
diff --git a/arch/arm/plat-s5p/sysmmu.c b/arch/arm/plat-s5p/sysmmu.c
index 54f5eddc921d..e1cbc728c775 100644
--- a/arch/arm/plat-s5p/sysmmu.c
+++ b/arch/arm/plat-s5p/sysmmu.c
@@ -232,8 +232,8 @@ static int s5p_sysmmu_probe(struct platform_device *pdev)
                         goto err_res;
                 }
 
-                mem = request_mem_region(res->start,
-                                ((res->end) - (res->start)) + 1, pdev->name);
+                mem = request_mem_region(res->start, resource_size(res),
+                                         pdev->name);
                 if (!mem) {
                         dev_err(dev, "Failed to request the memory region of %s.\n",
                                                         sysmmu_ips_name[i]);
@@ -241,7 +241,7 @@ static int s5p_sysmmu_probe(struct platform_device *pdev)
                         goto err_res;
                 }
 
-                sysmmusfrs[i] = ioremap(res->start, res->end - res->start + 1);
+                sysmmusfrs[i] = ioremap(res->start, resource_size(res));
                 if (!sysmmusfrs[i]) {
                         dev_err(dev, "Failed to ioremap() for %s.\n",
                                                         sysmmu_ips_name[i]);