7 files changed, 277 insertions, 10 deletions

diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile
index 2ed5df34f9ea..3c8882cd6268 100644
--- a/arch/arm/plat-s3c64xx/Makefile
+++ b/arch/arm/plat-s3c64xx/Makefile
@@ -23,6 +23,7 @@ obj-y				+= gpiolib.o
 
 obj-$(CONFIG_CPU_S3C6400_INIT)  += s3c6400-init.o
 obj-$(CONFIG_CPU_S3C6400_CLOCK) += s3c6400-clock.o
+obj-$(CONFIG_CPU_FREQ_S3C64XX)  += cpufreq.o
 
 # PM support
 
diff --git a/arch/arm/plat-s3c64xx/clock.c b/arch/arm/plat-s3c64xx/clock.c
index 0bc2fa1dfc40..7a36e899360d 100644
--- a/arch/arm/plat-s3c64xx/clock.c
+++ b/arch/arm/plat-s3c64xx/clock.c
@@ -191,7 +191,7 @@ static struct clk init_clocks[] = {
                 .id             = -1,
                 .parent         = &clk_h,
                 .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_SCLK_UHOST,
+                .ctrlbit        = S3C_CLKCON_HCLK_UHOST,
         }, {
                 .name           = "hsmmc",
                 .id             = 0,
diff --git a/arch/arm/plat-s3c64xx/cpufreq.c b/arch/arm/plat-s3c64xx/cpufreq.c
new file mode 100644
index 000000000000..e6e0843215df
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/cpufreq.c
@@ -0,0 +1,262 @@
+/* linux/arch/arm/plat-s3c64xx/cpufreq.c
+ *
+ * Copyright 2009 Wolfson Microelectronics plc
+ *
+ * S3C64xx CPUfreq Support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/cpufreq.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/regulator/consumer.h>
+
+static struct clk *armclk;
+static struct regulator *vddarm;
+
+#ifdef CONFIG_CPU_S3C6410
+struct s3c64xx_dvfs {
+        unsigned int vddarm_min;
+        unsigned int vddarm_max;
+};
+
+static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = {
+        [0] = { 1000000, 1000000 },
+        [1] = { 1000000, 1050000 },
+        [2] = { 1050000, 1100000 },
+        [3] = { 1050000, 1150000 },
+        [4] = { 1250000, 1350000 },
+};
+
+static struct cpufreq_frequency_table s3c64xx_freq_table[] = {
+        { 0,  66000 },
+        { 0, 133000 },
+        { 1, 222000 },
+        { 1, 266000 },
+        { 2, 333000 },
+        { 2, 400000 },
+        { 3, 532000 },
+        { 3, 533000 },
+        { 4, 667000 },
+        { 0, CPUFREQ_TABLE_END },
+};
+#endif
+
+static int s3c64xx_cpufreq_verify_speed(struct cpufreq_policy *policy)
+{
+        if (policy->cpu != 0)
+                return -EINVAL;
+
+        return cpufreq_frequency_table_verify(policy, s3c64xx_freq_table);
+}
+
+static unsigned int s3c64xx_cpufreq_get_speed(unsigned int cpu)
+{
+        if (cpu != 0)
+                return 0;
+
+        return clk_get_rate(armclk) / 1000;
+}
+
+static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy,
+                                      unsigned int target_freq,
+                                      unsigned int relation)
+{
+        int ret;
+        unsigned int i;
+        struct cpufreq_freqs freqs;
+        struct s3c64xx_dvfs *dvfs;
+
+        ret = cpufreq_frequency_table_target(policy, s3c64xx_freq_table,
+                                             target_freq, relation, &i);
+        if (ret != 0)
+                return ret;
+
+        freqs.cpu = 0;
+        freqs.old = clk_get_rate(armclk) / 1000;
+        freqs.new = s3c64xx_freq_table[i].frequency;
+        freqs.flags = 0;
+        dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[i].index];
+
+        if (freqs.old == freqs.new)
+                return 0;
+
+        pr_debug("cpufreq: Transition %d-%dkHz\n", freqs.old, freqs.new);
+
+        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+#ifdef CONFIG_REGULATOR
+        if (vddarm && freqs.new > freqs.old) {
+                ret = regulator_set_voltage(vddarm,
+                                            dvfs->vddarm_min,
+                                            dvfs->vddarm_max);
+                if (ret != 0) {
+                        pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n",
+                               freqs.new, ret);
+                        goto err;
+                }
+        }
+#endif
+
+        ret = clk_set_rate(armclk, freqs.new * 1000);
+        if (ret < 0) {
+                pr_err("cpufreq: Failed to set rate %dkHz: %d\n",
+                       freqs.new, ret);
+                goto err;
+        }
+
+#ifdef CONFIG_REGULATOR
+        if (vddarm && freqs.new < freqs.old) {
+                ret = regulator_set_voltage(vddarm,
+                                            dvfs->vddarm_min,
+                                            dvfs->vddarm_max);
+                if (ret != 0) {
+                        pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n",
+                               freqs.new, ret);
+                        goto err_clk;
+                }
+        }
+#endif
+
+        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+
+        pr_debug("cpufreq: Set actual frequency %lukHz\n",
+                 clk_get_rate(armclk) / 1000);
+
+        return 0;
+
+err_clk:
+        if (clk_set_rate(armclk, freqs.old * 1000) < 0)
+                pr_err("Failed to restore original clock rate\n");
+err:
+        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+
+        return ret;
+}
+
+#ifdef CONFIG_REGULATOR
+static void __init s3c64xx_cpufreq_constrain_voltages(void)
+{
+        int count, v, i, found;
+        struct cpufreq_frequency_table *freq;
+        struct s3c64xx_dvfs *dvfs;
+
+        count = regulator_count_voltages(vddarm);
+        if (count < 0) {
+                pr_err("cpufreq: Unable to check supported voltages\n");
+                return;
+        }
+
+        freq = s3c64xx_freq_table;
+        while (freq->frequency != CPUFREQ_TABLE_END) {
+                if (freq->frequency == CPUFREQ_ENTRY_INVALID)
+                        continue;
+
+                dvfs = &s3c64xx_dvfs_table[freq->index];
+                found = 0;
+
+                for (i = 0; i < count; i++) {
+                        v = regulator_list_voltage(vddarm, i);
+                        if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max)
+                                found = 1;
+                }
+
+                if (!found) {
+                        pr_debug("cpufreq: %dkHz unsupported by regulator\n",
+                                 freq->frequency);
+                        freq->frequency = CPUFREQ_ENTRY_INVALID;
+                }
+
+                freq++;
+        }
+}
+#endif
+
+static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
+{
+        int ret;
+        struct cpufreq_frequency_table *freq;
+
+        if (policy->cpu != 0)
+                return -EINVAL;
+
+        if (s3c64xx_freq_table == NULL) {
+                pr_err("cpufreq: No frequency information for this CPU\n");
+                return -ENODEV;
+        }
+
+        armclk = clk_get(NULL, "armclk");
+        if (IS_ERR(armclk)) {
+                pr_err("cpufreq: Unable to obtain ARMCLK: %ld\n",
+                       PTR_ERR(armclk));
+                return PTR_ERR(armclk);
+        }
+
+#ifdef CONFIG_REGULATOR
+        vddarm = regulator_get(NULL, "vddarm");
+        if (IS_ERR(vddarm)) {
+                ret = PTR_ERR(vddarm);
+                pr_err("cpufreq: Failed to obtain VDDARM: %d\n", ret);
+                pr_err("cpufreq: Only frequency scaling available\n");
+                vddarm = NULL;
+        } else {
+                s3c64xx_cpufreq_constrain_voltages();
+        }
+#endif
+
+        freq = s3c64xx_freq_table;
+        while (freq->frequency != CPUFREQ_TABLE_END) {
+                unsigned long r;
+
+                /* Check for frequencies we can generate */
+                r = clk_round_rate(armclk, freq->frequency * 1000);
+                r /= 1000;
+                if (r != freq->frequency)
+                        freq->frequency = CPUFREQ_ENTRY_INVALID;
+
+                /* If we have no regulator then assume startup
+                 * frequency is the maximum we can support. */
+                if (!vddarm && freq->frequency > s3c64xx_cpufreq_get_speed(0))
+                        freq->frequency = CPUFREQ_ENTRY_INVALID;
+
+                freq++;
+        }
+
+        policy->cur = clk_get_rate(armclk) / 1000;
+
+        /* Pick a conservative guess in ns: we'll need ~1 I2C/SPI
+         * write plus clock reprogramming. */
+        policy->cpuinfo.transition_latency = 2 * 1000 * 1000;
+
+        ret = cpufreq_frequency_table_cpuinfo(policy, s3c64xx_freq_table);
+        if (ret != 0) {
+                pr_err("cpufreq: Failed to configure frequency table: %d\n",
+                       ret);
+                regulator_put(vddarm);
+                clk_put(armclk);
+        }
+
+        return ret;
+}
+
+static struct cpufreq_driver s3c64xx_cpufreq_driver = {
+        .owner          = THIS_MODULE,
+        .flags          = 0,
+        .verify         = s3c64xx_cpufreq_verify_speed,
+        .target         = s3c64xx_cpufreq_set_target,
+        .get            = s3c64xx_cpufreq_get_speed,
+        .init           = s3c64xx_cpufreq_driver_init,
+        .name           = "s3c",
+};
+
+static int __init s3c64xx_cpufreq_init(void)
+{
+        return cpufreq_register_driver(&s3c64xx_cpufreq_driver);
+}
+module_init(s3c64xx_cpufreq_init);
diff --git a/arch/arm/plat-s3c64xx/gpiolib.c b/arch/arm/plat-s3c64xx/gpiolib.c
index da7b60ee5e67..92859290ea33 100644
--- a/arch/arm/plat-s3c64xx/gpiolib.c
+++ b/arch/arm/plat-s3c64xx/gpiolib.c
@@ -321,6 +321,11 @@ static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
         .get_pull       = s3c_gpio_getpull_updown,
 };
 
+int s3c64xx_gpio2int_gpn(struct gpio_chip *chip, unsigned pin)
+{
+        return IRQ_EINT(0) + pin;
+}
+
 static struct s3c_gpio_chip gpio_2bit[] = {
         {
                 .base   = S3C64XX_GPF_BASE,
@@ -353,6 +358,7 @@ static struct s3c_gpio_chip gpio_2bit[] = {
                         .base   = S3C64XX_GPN(0),
                         .ngpio  = S3C64XX_GPIO_N_NR,
                         .label  = "GPN",
+                        .to_irq = s3c64xx_gpio2int_gpn,
                 },
         }, {
                 .base   = S3C64XX_GPO_BASE,
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
index 52836d41e333..a8777a755dfa 100644
--- a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
@@ -88,11 +88,11 @@
 #define S3C6400_CLKDIV2_SPI0_SHIFT      (0)
 
 /* HCLK GATE Registers */
-#define S3C_CLKCON_HCLK_BUS     (1<<30)
-#define S3C_CLKCON_HCLK_SECUR   (1<<29)
-#define S3C_CLKCON_HCLK_SDMA1   (1<<28)
-#define S3C_CLKCON_HCLK_SDMA2   (1<<27)
-#define S3C_CLKCON_HCLK_UHOST   (1<<26)
+#define S3C_CLKCON_HCLK_3DSE    (1<<31)
+#define S3C_CLKCON_HCLK_UHOST   (1<<29)
+#define S3C_CLKCON_HCLK_SECUR   (1<<28)
+#define S3C_CLKCON_HCLK_SDMA1   (1<<27)
+#define S3C_CLKCON_HCLK_SDMA0   (1<<26)
 #define S3C_CLKCON_HCLK_IROM    (1<<25)
 #define S3C_CLKCON_HCLK_DDR1    (1<<24)
 #define S3C_CLKCON_HCLK_DDR0    (1<<23)
diff --git a/arch/arm/plat-s3c64xx/pm.c b/arch/arm/plat-s3c64xx/pm.c
index 07a6516a4f3c..47632fc7eb66 100644
--- a/arch/arm/plat-s3c64xx/pm.c
+++ b/arch/arm/plat-s3c64xx/pm.c
@@ -117,8 +117,6 @@ void s3c_pm_save_core(void)
  * this.
  */
 
-#include <plat/regs-gpio.h>
-
 static void s3c64xx_cpu_suspend(void)
 {
         unsigned long tmp;
diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c
index 1debc1f9f987..febac1950d8e 100644
--- a/arch/arm/plat-s3c64xx/s3c6400-clock.c
+++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c
@@ -153,7 +153,7 @@ static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk,
         u32 div;
 
         if (parent < rate)
-                return rate;
+                return parent;
 
         div = (parent / rate) - 1;
         if (div > armclk_mask)
@@ -175,7 +175,7 @@ static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
         div = clk_get_rate(clk->parent) / rate;
 
         val = __raw_readl(S3C_CLK_DIV0);
-        val &= armclk_mask;
+        val &= ~armclk_mask;
         val |= (div - 1);
         __raw_writel(val, S3C_CLK_DIV0);