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-rw-r--r--arch/arm/plat-s3c64xx/Kconfig36
-rw-r--r--arch/arm/plat-s3c64xx/Makefile24
-rw-r--r--arch/arm/plat-s3c64xx/clock.c282
-rw-r--r--arch/arm/plat-s3c64xx/cpu.c115
-rw-r--r--arch/arm/plat-s3c64xx/dev-uart.c176
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/irqs.h196
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/pll.h74
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/regs-clock.h224
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/regs-sys.h24
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/s3c6400.h35
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/s3c6410.h29
-rw-r--r--arch/arm/plat-s3c64xx/irq-eint.c202
-rw-r--r--arch/arm/plat-s3c64xx/irq.c257
-rw-r--r--arch/arm/plat-s3c64xx/s3c6400-clock.c655
-rw-r--r--arch/arm/plat-s3c64xx/s3c6400-init.c29
15 files changed, 2358 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c64xx/Kconfig b/arch/arm/plat-s3c64xx/Kconfig
new file mode 100644
index 000000000000..bd832ba0cf77
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/Kconfig
@@ -0,0 +1,36 @@
1# arch/arm/plat-s3c64xx/Kconfig
2#
3# Copyright 2008 Openmoko, Inc.
4# Copyright 2008 Simtec Electronics
5# Ben Dooks <ben@simtec.co.uk>
6#
7# Licensed under GPLv2
8
9config PLAT_S3C64XX
10 bool
11 depends on ARCH_S3C64XX
12 select PLAT_S3C
13 select ARM_VIC
14 default y
15 select NO_IOPORT
16 select ARCH_REQUIRE_GPIOLIB
17 help
18 Base platform code for any Samsung S3C64XX device
19
20if PLAT_S3C64XX
21
22# Configuration options shared by all S3C64XX implementations
23
24config CPU_S3C6400_INIT
25 bool
26 help
27 Common initialisation code for the S3C6400 that is shared
28 by other CPUs in the series, such as the S3C6410.
29
30config CPU_S3C6400_CLOCK
31 bool
32 help
33 Common clock support code for the S3C6400 that is shared
34 by other CPUs in the series, such as the S3C6410.
35
36endif
diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile
new file mode 100644
index 000000000000..9c09b0819805
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/Makefile
@@ -0,0 +1,24 @@
1# arch/arm/plat-s3c64xx/Makefile
2#
3# Copyright 2008 Openmoko, Inc.
4# Copyright 2008 Simtec Electronics
5#
6# Licensed under GPLv2
7
8obj-y :=
9obj-m :=
10obj-n := dummy.o
11obj- :=
12
13# Core files
14
15obj-y += dev-uart.o
16obj-y += cpu.o
17obj-y += irq.o
18obj-y += irq-eint.o
19obj-y += clock.o
20
21# CPU support
22
23obj-$(CONFIG_CPU_S3C6400_INIT) += s3c6400-init.o
24obj-$(CONFIG_CPU_S3C6400_CLOCK) += s3c6400-clock.o
diff --git a/arch/arm/plat-s3c64xx/clock.c b/arch/arm/plat-s3c64xx/clock.c
new file mode 100644
index 000000000000..5a1e97e1f8f6
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/clock.c
@@ -0,0 +1,282 @@
1/* linux/arch/arm/plat-s3c64xx/clock.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX Base clock support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/interrupt.h>
18#include <linux/ioport.h>
19#include <linux/delay.h>
20#include <linux/io.h>
21
22#include <mach/hardware.h>
23#include <mach/map.h>
24
25#include <plat/regs-sys.h>
26#include <plat/regs-clock.h>
27#include <plat/cpu.h>
28#include <plat/devs.h>
29#include <plat/clock.h>
30
31struct clk clk_27m = {
32 .name = "clk_27m",
33 .id = -1,
34 .rate = 27000000,
35};
36
37static int clk_48m_ctrl(struct clk *clk, int enable)
38{
39 unsigned long flags;
40 u32 val;
41
42 /* can't rely on clock lock, this register has other usages */
43 local_irq_save(flags);
44
45 val = __raw_readl(S3C64XX_OTHERS);
46 if (enable)
47 val |= S3C64XX_OTHERS_USBMASK;
48 else
49 val &= ~S3C64XX_OTHERS_USBMASK;
50
51 __raw_writel(val, S3C64XX_OTHERS);
52 local_irq_restore(flags);
53
54 return 0;
55}
56
57struct clk clk_48m = {
58 .name = "clk_48m",
59 .id = -1,
60 .rate = 48000000,
61 .enable = clk_48m_ctrl,
62};
63
64static int inline s3c64xx_gate(void __iomem *reg,
65 struct clk *clk,
66 int enable)
67{
68 unsigned int ctrlbit = clk->ctrlbit;
69 u32 con;
70
71 con = __raw_readl(reg);
72
73 if (enable)
74 con |= ctrlbit;
75 else
76 con &= ~ctrlbit;
77
78 __raw_writel(con, reg);
79 return 0;
80}
81
82static int s3c64xx_pclk_ctrl(struct clk *clk, int enable)
83{
84 return s3c64xx_gate(S3C_PCLK_GATE, clk, enable);
85}
86
87static int s3c64xx_hclk_ctrl(struct clk *clk, int enable)
88{
89 return s3c64xx_gate(S3C_HCLK_GATE, clk, enable);
90}
91
92int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
93{
94 return s3c64xx_gate(S3C_SCLK_GATE, clk, enable);
95}
96
97static struct clk init_clocks_disable[] = {
98 {
99 .name = "nand",
100 .id = -1,
101 .parent = &clk_h,
102 }, {
103 .name = "adc",
104 .id = -1,
105 .parent = &clk_p,
106 .enable = s3c64xx_pclk_ctrl,
107 .ctrlbit = S3C_CLKCON_PCLK_TSADC,
108 }, {
109 .name = "i2c",
110 .id = -1,
111 .parent = &clk_p,
112 .enable = s3c64xx_pclk_ctrl,
113 .ctrlbit = S3C_CLKCON_PCLK_IIC,
114 }, {
115 .name = "iis",
116 .id = 0,
117 .parent = &clk_p,
118 .enable = s3c64xx_pclk_ctrl,
119 .ctrlbit = S3C_CLKCON_PCLK_IIS0,
120 }, {
121 .name = "iis",
122 .id = 1,
123 .parent = &clk_p,
124 .enable = s3c64xx_pclk_ctrl,
125 .ctrlbit = S3C_CLKCON_PCLK_IIS1,
126 }, {
127 .name = "spi",
128 .id = 0,
129 .parent = &clk_p,
130 .enable = s3c64xx_pclk_ctrl,
131 .ctrlbit = S3C_CLKCON_PCLK_SPI0,
132 }, {
133 .name = "spi",
134 .id = 1,
135 .parent = &clk_p,
136 .enable = s3c64xx_pclk_ctrl,
137 .ctrlbit = S3C_CLKCON_PCLK_SPI1,
138 }, {
139 .name = "48m",
140 .id = 0,
141 .parent = &clk_48m,
142 .enable = s3c64xx_sclk_ctrl,
143 .ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
144 }, {
145 .name = "48m",
146 .id = 1,
147 .parent = &clk_48m,
148 .enable = s3c64xx_sclk_ctrl,
149 .ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
150 }, {
151 .name = "48m",
152 .id = 2,
153 .parent = &clk_48m,
154 .enable = s3c64xx_sclk_ctrl,
155 .ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
156 },
157};
158
159static struct clk init_clocks[] = {
160 {
161 .name = "lcd",
162 .id = -1,
163 .parent = &clk_h,
164 .enable = s3c64xx_hclk_ctrl,
165 .ctrlbit = S3C_CLKCON_HCLK_LCD,
166 }, {
167 .name = "gpio",
168 .id = -1,
169 .parent = &clk_p,
170 .enable = s3c64xx_pclk_ctrl,
171 .ctrlbit = S3C_CLKCON_PCLK_GPIO,
172 }, {
173 .name = "usb-host",
174 .id = -1,
175 .parent = &clk_h,
176 .enable = s3c64xx_hclk_ctrl,
177 .ctrlbit = S3C_CLKCON_SCLK_UHOST,
178 }, {
179 .name = "hsmmc",
180 .id = 0,
181 .parent = &clk_h,
182 .enable = s3c64xx_hclk_ctrl,
183 .ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
184 }, {
185 .name = "hsmmc",
186 .id = 1,
187 .parent = &clk_h,
188 .enable = s3c64xx_hclk_ctrl,
189 .ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
190 }, {
191 .name = "hsmmc",
192 .id = 2,
193 .parent = &clk_h,
194 .enable = s3c64xx_hclk_ctrl,
195 .ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
196 }, {
197 .name = "timers",
198 .id = -1,
199 .parent = &clk_p,
200 .enable = s3c64xx_pclk_ctrl,
201 .ctrlbit = S3C_CLKCON_PCLK_PWM,
202 }, {
203 .name = "uart",
204 .id = 0,
205 .parent = &clk_p,
206 .enable = s3c64xx_pclk_ctrl,
207 .ctrlbit = S3C_CLKCON_PCLK_UART0,
208 }, {
209 .name = "uart",
210 .id = 1,
211 .parent = &clk_p,
212 .enable = s3c64xx_pclk_ctrl,
213 .ctrlbit = S3C_CLKCON_PCLK_UART1,
214 }, {
215 .name = "uart",
216 .id = 2,
217 .parent = &clk_p,
218 .enable = s3c64xx_pclk_ctrl,
219 .ctrlbit = S3C_CLKCON_PCLK_UART2,
220 }, {
221 .name = "uart",
222 .id = 3,
223 .parent = &clk_p,
224 .enable = s3c64xx_pclk_ctrl,
225 .ctrlbit = S3C_CLKCON_PCLK_UART3,
226 }, {
227 .name = "rtc",
228 .id = -1,
229 .parent = &clk_p,
230 .enable = s3c64xx_pclk_ctrl,
231 .ctrlbit = S3C_CLKCON_PCLK_RTC,
232 }, {
233 .name = "watchdog",
234 .id = -1,
235 .parent = &clk_p,
236 .ctrlbit = S3C_CLKCON_PCLK_WDT,
237 }, {
238 .name = "ac97",
239 .id = -1,
240 .parent = &clk_p,
241 .ctrlbit = S3C_CLKCON_PCLK_AC97,
242 }
243};
244
245static struct clk *clks[] __initdata = {
246 &clk_ext,
247 &clk_epll,
248 &clk_27m,
249 &clk_48m,
250};
251
252void s3c64xx_register_clocks(void)
253{
254 struct clk *clkp;
255 int ret;
256 int ptr;
257
258 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
259
260 clkp = init_clocks;
261 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
262 ret = s3c24xx_register_clock(clkp);
263 if (ret < 0) {
264 printk(KERN_ERR "Failed to register clock %s (%d)\n",
265 clkp->name, ret);
266 }
267 }
268
269 clkp = init_clocks_disable;
270 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
271
272 ret = s3c24xx_register_clock(clkp);
273 if (ret < 0) {
274 printk(KERN_ERR "Failed to register clock %s (%d)\n",
275 clkp->name, ret);
276 }
277
278 (clkp->enable)(clkp, 0);
279 }
280
281 s3c_pwmclk_init();
282}
diff --git a/arch/arm/plat-s3c64xx/cpu.c b/arch/arm/plat-s3c64xx/cpu.c
new file mode 100644
index 000000000000..36182fcfaebc
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/cpu.c
@@ -0,0 +1,115 @@
1/* linux/arch/arm/plat-s3c64xx/cpu.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX CPU Support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/interrupt.h>
18#include <linux/ioport.h>
19#include <linux/serial_core.h>
20#include <linux/platform_device.h>
21#include <linux/delay.h>
22#include <linux/io.h>
23
24#include <mach/hardware.h>
25#include <mach/map.h>
26
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29
30#include <plat/regs-serial.h>
31
32#include <plat/cpu.h>
33#include <plat/devs.h>
34#include <plat/clock.h>
35
36#include <plat/s3c6400.h>
37#include <plat/s3c6410.h>
38
39/* table of supported CPUs */
40
41static const char name_s3c6400[] = "S3C6400";
42static const char name_s3c6410[] = "S3C6410";
43
44static struct cpu_table cpu_ids[] __initdata = {
45 {
46 .idcode = 0x36400000,
47 .idmask = 0xfffff000,
48 .map_io = s3c6400_map_io,
49 .init_clocks = s3c6400_init_clocks,
50 .init_uarts = s3c6400_init_uarts,
51 .init = s3c6400_init,
52 .name = name_s3c6400,
53 }, {
54 .idcode = 0x36410100,
55 .idmask = 0xffffff00,
56 .map_io = s3c6410_map_io,
57 .init_clocks = s3c6410_init_clocks,
58 .init_uarts = s3c6410_init_uarts,
59 .init = s3c6410_init,
60 .name = name_s3c6410,
61 },
62};
63
64/* minimal IO mapping */
65
66/* see notes on uart map in arch/arm/mach-s3c6400/include/mach/debug-macro.S */
67#define UART_OFFS (S3C_PA_UART & 0xfffff)
68
69static struct map_desc s3c_iodesc[] __initdata = {
70 {
71 .virtual = (unsigned long)S3C_VA_SYS,
72 .pfn = __phys_to_pfn(S3C64XX_PA_SYSCON),
73 .length = SZ_4K,
74 .type = MT_DEVICE,
75 }, {
76 .virtual = (unsigned long)(S3C_VA_UART + UART_OFFS),
77 .pfn = __phys_to_pfn(S3C_PA_UART),
78 .length = SZ_4K,
79 .type = MT_DEVICE,
80 }, {
81 .virtual = (unsigned long)S3C_VA_VIC0,
82 .pfn = __phys_to_pfn(S3C64XX_PA_VIC0),
83 .length = SZ_16K,
84 .type = MT_DEVICE,
85 }, {
86 .virtual = (unsigned long)S3C_VA_VIC1,
87 .pfn = __phys_to_pfn(S3C64XX_PA_VIC1),
88 .length = SZ_16K,
89 .type = MT_DEVICE,
90 }, {
91 .virtual = (unsigned long)S3C_VA_TIMER,
92 .pfn = __phys_to_pfn(S3C_PA_TIMER),
93 .length = SZ_16K,
94 .type = MT_DEVICE,
95 }, {
96 .virtual = (unsigned long)S3C64XX_VA_GPIO,
97 .pfn = __phys_to_pfn(S3C64XX_PA_GPIO),
98 .length = SZ_4K,
99 .type = MT_DEVICE,
100 },
101};
102
103/* read cpu identification code */
104
105void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
106{
107 unsigned long idcode;
108
109 /* initialise the io descriptors we need for initialisation */
110 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
111 iotable_init(mach_desc, size);
112
113 idcode = __raw_readl(S3C_VA_SYS + 0x118);
114 s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
115}
diff --git a/arch/arm/plat-s3c64xx/dev-uart.c b/arch/arm/plat-s3c64xx/dev-uart.c
new file mode 100644
index 000000000000..62c11a6fc7ba
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/dev-uart.c
@@ -0,0 +1,176 @@
1/* linux/arch/arm/plat-s3c64xx/dev-uart.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * Base S3C64XX UART resource and device definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14*/
15
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/interrupt.h>
19#include <linux/list.h>
20#include <linux/platform_device.h>
21
22#include <asm/mach/arch.h>
23#include <asm/mach/irq.h>
24#include <mach/hardware.h>
25#include <mach/map.h>
26
27#include <plat/devs.h>
28
29/* Serial port registrations */
30
31/* 64xx uarts are closer together */
32
33static struct resource s3c64xx_uart0_resource[] = {
34 [0] = {
35 .start = S3C_PA_UART0,
36 .end = S3C_PA_UART0 + 0x100,
37 .flags = IORESOURCE_MEM,
38 },
39 [1] = {
40 .start = IRQ_S3CUART_RX0,
41 .end = IRQ_S3CUART_RX0,
42 .flags = IORESOURCE_IRQ,
43 },
44 [2] = {
45 .start = IRQ_S3CUART_TX0,
46 .end = IRQ_S3CUART_TX0,
47 .flags = IORESOURCE_IRQ,
48
49 },
50 [3] = {
51 .start = IRQ_S3CUART_ERR0,
52 .end = IRQ_S3CUART_ERR0,
53 .flags = IORESOURCE_IRQ,
54 }
55};
56
57static struct resource s3c64xx_uart1_resource[] = {
58 [0] = {
59 .start = S3C_PA_UART1,
60 .end = S3C_PA_UART1 + 0x100,
61 .flags = IORESOURCE_MEM,
62 },
63 [1] = {
64 .start = IRQ_S3CUART_RX1,
65 .end = IRQ_S3CUART_RX1,
66 .flags = IORESOURCE_IRQ,
67 },
68 [2] = {
69 .start = IRQ_S3CUART_TX1,
70 .end = IRQ_S3CUART_TX1,
71 .flags = IORESOURCE_IRQ,
72
73 },
74 [3] = {
75 .start = IRQ_S3CUART_ERR1,
76 .end = IRQ_S3CUART_ERR1,
77 .flags = IORESOURCE_IRQ,
78 },
79};
80
81static struct resource s3c6xx_uart2_resource[] = {
82 [0] = {
83 .start = S3C_PA_UART2,
84 .end = S3C_PA_UART2 + 0x100,
85 .flags = IORESOURCE_MEM,
86 },
87 [1] = {
88 .start = IRQ_S3CUART_RX2,
89 .end = IRQ_S3CUART_RX2,
90 .flags = IORESOURCE_IRQ,
91 },
92 [2] = {
93 .start = IRQ_S3CUART_TX2,
94 .end = IRQ_S3CUART_TX2,
95 .flags = IORESOURCE_IRQ,
96
97 },
98 [3] = {
99 .start = IRQ_S3CUART_ERR2,
100 .end = IRQ_S3CUART_ERR2,
101 .flags = IORESOURCE_IRQ,
102 },
103};
104
105static struct resource s3c64xx_uart3_resource[] = {
106 [0] = {
107 .start = S3C_PA_UART3,
108 .end = S3C_PA_UART3 + 0x100,
109 .flags = IORESOURCE_MEM,
110 },
111 [1] = {
112 .start = IRQ_S3CUART_RX3,
113 .end = IRQ_S3CUART_RX3,
114 .flags = IORESOURCE_IRQ,
115 },
116 [2] = {
117 .start = IRQ_S3CUART_TX3,
118 .end = IRQ_S3CUART_TX3,
119 .flags = IORESOURCE_IRQ,
120
121 },
122 [3] = {
123 .start = IRQ_S3CUART_ERR3,
124 .end = IRQ_S3CUART_ERR3,
125 .flags = IORESOURCE_IRQ,
126 },
127};
128
129
130struct s3c24xx_uart_resources s3c64xx_uart_resources[] __initdata = {
131 [0] = {
132 .resources = s3c64xx_uart0_resource,
133 .nr_resources = ARRAY_SIZE(s3c64xx_uart0_resource),
134 },
135 [1] = {
136 .resources = s3c64xx_uart1_resource,
137 .nr_resources = ARRAY_SIZE(s3c64xx_uart1_resource),
138 },
139 [2] = {
140 .resources = s3c6xx_uart2_resource,
141 .nr_resources = ARRAY_SIZE(s3c6xx_uart2_resource),
142 },
143 [3] = {
144 .resources = s3c64xx_uart3_resource,
145 .nr_resources = ARRAY_SIZE(s3c64xx_uart3_resource),
146 },
147};
148
149/* uart devices */
150
151static struct platform_device s3c24xx_uart_device0 = {
152 .id = 0,
153};
154
155static struct platform_device s3c24xx_uart_device1 = {
156 .id = 1,
157};
158
159static struct platform_device s3c24xx_uart_device2 = {
160 .id = 2,
161};
162
163static struct platform_device s3c24xx_uart_device3 = {
164 .id = 3,
165};
166
167struct platform_device *s3c24xx_uart_src[4] = {
168 &s3c24xx_uart_device0,
169 &s3c24xx_uart_device1,
170 &s3c24xx_uart_device2,
171 &s3c24xx_uart_device3,
172};
173
174struct platform_device *s3c24xx_uart_devs[4] = {
175};
176
diff --git a/arch/arm/plat-s3c64xx/include/plat/irqs.h b/arch/arm/plat-s3c64xx/include/plat/irqs.h
new file mode 100644
index 000000000000..bc25689c3f83
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/irqs.h
@@ -0,0 +1,196 @@
1/* linux/arch/arm/plat-s3c64xx/include/mach/irqs.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX - Common IRQ support
9 */
10
11#ifndef __ASM_PLAT_S3C64XX_IRQS_H
12#define __ASM_PLAT_S3C64XX_IRQS_H __FILE__
13
14/* we keep the first set of CPU IRQs out of the range of
15 * the ISA space, so that the PC104 has them to itself
16 * and we don't end up having to do horrible things to the
17 * standard ISA drivers....
18 *
19 * note, since we're using the VICs, our start must be a
20 * mulitple of 32 to allow the common code to work
21 */
22
23#define S3C_IRQ_OFFSET (32)
24
25#define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET)
26
27#define S3C_VIC0_BASE S3C_IRQ(0)
28#define S3C_VIC1_BASE S3C_IRQ(32)
29
30/* UART interrupts, each UART has 4 intterupts per channel so
31 * use the space between the ISA and S3C main interrupts. Note, these
32 * are not in the same order as the S3C24XX series! */
33
34#define IRQ_S3CUART_BASE0 (16)
35#define IRQ_S3CUART_BASE1 (20)
36#define IRQ_S3CUART_BASE2 (24)
37#define IRQ_S3CUART_BASE3 (28)
38
39#define UART_IRQ_RXD (0)
40#define UART_IRQ_ERR (1)
41#define UART_IRQ_TXD (2)
42#define UART_IRQ_MODEM (3)
43
44#define IRQ_S3CUART_RX0 (IRQ_S3CUART_BASE0 + UART_IRQ_RXD)
45#define IRQ_S3CUART_TX0 (IRQ_S3CUART_BASE0 + UART_IRQ_TXD)
46#define IRQ_S3CUART_ERR0 (IRQ_S3CUART_BASE0 + UART_IRQ_ERR)
47
48#define IRQ_S3CUART_RX1 (IRQ_S3CUART_BASE1 + UART_IRQ_RXD)
49#define IRQ_S3CUART_TX1 (IRQ_S3CUART_BASE1 + UART_IRQ_TXD)
50#define IRQ_S3CUART_ERR1 (IRQ_S3CUART_BASE1 + UART_IRQ_ERR)
51
52#define IRQ_S3CUART_RX2 (IRQ_S3CUART_BASE2 + UART_IRQ_RXD)
53#define IRQ_S3CUART_TX2 (IRQ_S3CUART_BASE2 + UART_IRQ_TXD)
54#define IRQ_S3CUART_ERR2 (IRQ_S3CUART_BASE2 + UART_IRQ_ERR)
55
56#define IRQ_S3CUART_RX3 (IRQ_S3CUART_BASE3 + UART_IRQ_RXD)
57#define IRQ_S3CUART_TX3 (IRQ_S3CUART_BASE3 + UART_IRQ_TXD)
58#define IRQ_S3CUART_ERR3 (IRQ_S3CUART_BASE3 + UART_IRQ_ERR)
59
60/* VIC based IRQs */
61
62#define S3C64XX_IRQ_VIC0(x) (S3C_VIC0_BASE + (x))
63#define S3C64XX_IRQ_VIC1(x) (S3C_VIC1_BASE + (x))
64
65/* VIC0 */
66
67#define IRQ_EINT0_3 S3C64XX_IRQ_VIC0(0)
68#define IRQ_EINT4_11 S3C64XX_IRQ_VIC0(1)
69#define IRQ_RTC_TIC S3C64XX_IRQ_VIC0(2)
70#define IRQ_CAMIF_C S3C64XX_IRQ_VIC0(3)
71#define IRQ_CAMIF_P S3C64XX_IRQ_VIC0(4)
72#define IRQ_CAMIF_MC S3C64XX_IRQ_VIC0(5)
73#define IRQ_S3C6410_IIS S3C64XX_IRQ_VIC0(6)
74#define IRQ_S3C6400_CAMIF_MP S3C64XX_IRQ_VIC0(6)
75#define IRQ_CAMIF_WE_C S3C64XX_IRQ_VIC0(7)
76#define IRQ_S3C6410_G3D S3C64XX_IRQ_VIC0(8)
77#define IRQ_S3C6400_CAMIF_WE_P S3C64XX_IRQ_VIC0(8)
78#define IRQ_POST0 S3C64XX_IRQ_VIC0(9)
79#define IRQ_ROTATOR S3C64XX_IRQ_VIC0(10)
80#define IRQ_2D S3C64XX_IRQ_VIC0(11)
81#define IRQ_TVENC S3C64XX_IRQ_VIC0(12)
82#define IRQ_SCALER S3C64XX_IRQ_VIC0(13)
83#define IRQ_BATF S3C64XX_IRQ_VIC0(14)
84#define IRQ_JPEG S3C64XX_IRQ_VIC0(15)
85#define IRQ_MFC S3C64XX_IRQ_VIC0(16)
86#define IRQ_SDMA0 S3C64XX_IRQ_VIC0(17)
87#define IRQ_SDMA1 S3C64XX_IRQ_VIC0(18)
88#define IRQ_ARM_DMAERR S3C64XX_IRQ_VIC0(19)
89#define IRQ_ARM_DMA S3C64XX_IRQ_VIC0(20)
90#define IRQ_ARM_DMAS S3C64XX_IRQ_VIC0(21)
91#define IRQ_KEYPAD S3C64XX_IRQ_VIC0(22)
92#define IRQ_TIMER0_VIC S3C64XX_IRQ_VIC0(23)
93#define IRQ_TIMER1_VIC S3C64XX_IRQ_VIC0(24)
94#define IRQ_TIMER2_VIC S3C64XX_IRQ_VIC0(25)
95#define IRQ_WDT S3C64XX_IRQ_VIC0(26)
96#define IRQ_TIMER3_VIC S3C64XX_IRQ_VIC0(27)
97#define IRQ_TIMER4_VIC S3C64XX_IRQ_VIC0(28)
98#define IRQ_LCD_FIFO S3C64XX_IRQ_VIC0(29)
99#define IRQ_LCD_VSYNC S3C64XX_IRQ_VIC0(30)
100#define IRQ_LCD_SYSTEM S3C64XX_IRQ_VIC0(31)
101
102/* VIC1 */
103
104#define IRQ_EINT12_19 S3C64XX_IRQ_VIC1(0)
105#define IRQ_EINT20_27 S3C64XX_IRQ_VIC1(1)
106#define IRQ_PCM0 S3C64XX_IRQ_VIC1(2)
107#define IRQ_PCM1 S3C64XX_IRQ_VIC1(3)
108#define IRQ_AC97 S3C64XX_IRQ_VIC1(4)
109#define IRQ_UART0 S3C64XX_IRQ_VIC1(5)
110#define IRQ_UART1 S3C64XX_IRQ_VIC1(6)
111#define IRQ_UART2 S3C64XX_IRQ_VIC1(7)
112#define IRQ_UART3 S3C64XX_IRQ_VIC1(8)
113#define IRQ_DMA0 S3C64XX_IRQ_VIC1(9)
114#define IRQ_DMA1 S3C64XX_IRQ_VIC1(10)
115#define IRQ_ONENAND0 S3C64XX_IRQ_VIC1(11)
116#define IRQ_ONENAND1 S3C64XX_IRQ_VIC1(12)
117#define IRQ_NFC S3C64XX_IRQ_VIC1(13)
118#define IRQ_CFCON S3C64XX_IRQ_VIC1(14)
119#define IRQ_UHOST S3C64XX_IRQ_VIC1(15)
120#define IRQ_SPI0 S3C64XX_IRQ_VIC1(16)
121#define IRQ_SPI1 S3C64XX_IRQ_VIC1(17)
122#define IRQ_IIC S3C64XX_IRQ_VIC1(18)
123#define IRQ_HSItx S3C64XX_IRQ_VIC1(19)
124#define IRQ_HSIrx S3C64XX_IRQ_VIC1(20)
125#define IRQ_RESERVED S3C64XX_IRQ_VIC1(21)
126#define IRQ_MSM S3C64XX_IRQ_VIC1(22)
127#define IRQ_HOSTIF S3C64XX_IRQ_VIC1(23)
128#define IRQ_HSMMC0 S3C64XX_IRQ_VIC1(24)
129#define IRQ_HSMMC1 S3C64XX_IRQ_VIC1(25)
130#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */
131#define IRQ_OTG S3C64XX_IRQ_VIC1(26)
132#define IRQ_IRDA S3C64XX_IRQ_VIC1(27)
133#define IRQ_RTC_ALARM S3C64XX_IRQ_VIC1(28)
134#define IRQ_SEC S3C64XX_IRQ_VIC1(29)
135#define IRQ_PENDN S3C64XX_IRQ_VIC1(30)
136#define IRQ_TC IRQ_PENDN
137#define IRQ_ADC S3C64XX_IRQ_VIC1(31)
138
139#define S3C64XX_TIMER_IRQ(x) S3C_IRQ(64 + (x))
140
141#define IRQ_TIMER0 S3C64XX_TIMER_IRQ(0)
142#define IRQ_TIMER1 S3C64XX_TIMER_IRQ(1)
143#define IRQ_TIMER2 S3C64XX_TIMER_IRQ(2)
144#define IRQ_TIMER3 S3C64XX_TIMER_IRQ(3)
145#define IRQ_TIMER4 S3C64XX_TIMER_IRQ(4)
146
147/* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series
148 * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE
149 * which we place after the pair of VICs. */
150
151#define S3C_IRQ_EINT_BASE S3C_IRQ(64+5)
152
153#define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE)
154#define IRQ_EINT(x) S3C_EINT(x)
155
156/* Next the external interrupt groups. These are similar to the IRQ_EINT(x)
157 * that they are sourced from the GPIO pins but with a different scheme for
158 * priority and source indication.
159 *
160 * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO
161 * interrupts, but for historical reasons they are kept apart from these
162 * next interrupts.
163 *
164 * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the
165 * machine specific support files.
166 */
167
168#define IRQ_EINT_GROUP1_NR (15)
169#define IRQ_EINT_GROUP2_NR (8)
170#define IRQ_EINT_GROUP3_NR (5)
171#define IRQ_EINT_GROUP4_NR (14)
172#define IRQ_EINT_GROUP5_NR (7)
173#define IRQ_EINT_GROUP6_NR (10)
174#define IRQ_EINT_GROUP7_NR (16)
175#define IRQ_EINT_GROUP8_NR (15)
176#define IRQ_EINT_GROUP9_NR (9)
177
178#define IRQ_EINT_GROUP_BASE S3C_EINT(28)
179#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0x00)
180#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR)
181#define IRQ_EINT_GROUP3_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR)
182#define IRQ_EINT_GROUP4_BASE (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR)
183#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR)
184#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR)
185#define IRQ_EINT_GROUP7_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR)
186#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR)
187#define IRQ_EINT_GROUP9_BASE (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR)
188
189#define IRQ_EINT_GROUP(group, no) (IRQ_EINT_GROUP##group##__BASE + (x))
190
191/* Set the default NR_IRQS */
192
193#define NR_IRQS (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1)
194
195#endif /* __ASM_PLAT_S3C64XX_IRQS_H */
196
diff --git a/arch/arm/plat-s3c64xx/include/plat/pll.h b/arch/arm/plat-s3c64xx/include/plat/pll.h
new file mode 100644
index 000000000000..90bbd72fdc4e
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/pll.h
@@ -0,0 +1,74 @@
1/* arch/arm/plat-s3c64xx/include/plat/pll.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX PLL code
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C6400_PLL_MDIV_MASK ((1 << (25-16+1)) - 1)
16#define S3C6400_PLL_PDIV_MASK ((1 << (13-8+1)) - 1)
17#define S3C6400_PLL_SDIV_MASK ((1 << (2-0+1)) - 1)
18#define S3C6400_PLL_MDIV_SHIFT (16)
19#define S3C6400_PLL_PDIV_SHIFT (8)
20#define S3C6400_PLL_SDIV_SHIFT (0)
21
22#include <asm/div64.h>
23
24static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
25 u32 pllcon)
26{
27 u32 mdiv, pdiv, sdiv;
28 u64 fvco = baseclk;
29
30 mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK;
31 pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK;
32 sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK;
33
34 fvco *= mdiv;
35 do_div(fvco, (pdiv << sdiv));
36
37 return (unsigned long)fvco;
38}
39
40#define S3C6400_EPLL_MDIV_MASK ((1 << (23-16)) - 1)
41#define S3C6400_EPLL_PDIV_MASK ((1 << (13-8)) - 1)
42#define S3C6400_EPLL_SDIV_MASK ((1 << (2-0)) - 1)
43#define S3C6400_EPLL_MDIV_SHIFT (16)
44#define S3C6400_EPLL_PDIV_SHIFT (8)
45#define S3C6400_EPLL_SDIV_SHIFT (0)
46#define S3C6400_EPLL_KDIV_MASK (0xffff)
47
48static inline unsigned long s3c6400_get_epll(unsigned long baseclk)
49{
50 unsigned long result;
51 u32 epll0 = __raw_readl(S3C_EPLL_CON0);
52 u32 epll1 = __raw_readl(S3C_EPLL_CON1);
53 u32 mdiv, pdiv, sdiv, kdiv;
54 u64 tmp;
55
56 mdiv = (epll0 >> S3C6400_EPLL_MDIV_SHIFT) & S3C6400_EPLL_MDIV_MASK;
57 pdiv = (epll0 >> S3C6400_EPLL_PDIV_SHIFT) & S3C6400_EPLL_PDIV_MASK;
58 sdiv = (epll0 >> S3C6400_EPLL_SDIV_SHIFT) & S3C6400_EPLL_SDIV_MASK;
59 kdiv = epll1 & S3C6400_EPLL_KDIV_MASK;
60
61 /* We need to multiple baseclk by mdiv (the integer part) and kdiv
62 * which is in 2^16ths, so shift mdiv up (does not overflow) and
63 * add kdiv before multiplying. The use of tmp is to avoid any
64 * overflows before shifting bac down into result when multipling
65 * by the mdiv and kdiv pair.
66 */
67
68 tmp = baseclk;
69 tmp *= (mdiv << 16) + kdiv;
70 do_div(tmp, (pdiv << sdiv));
71 result = tmp >> 16;
72
73 return result;
74}
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
new file mode 100644
index 000000000000..b1082c163247
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
@@ -0,0 +1,224 @@
1/* arch/arm/plat-s3c64xx/include/plat/regs-clock.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX clock register definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __PLAT_REGS_CLOCK_H
16#define __PLAT_REGS_CLOCK_H __FILE__
17
18#define S3C_CLKREG(x) (S3C_VA_SYS + (x))
19
20#define S3C_APLL_LOCK S3C_CLKREG(0x00)
21#define S3C_MPLL_LOCK S3C_CLKREG(0x04)
22#define S3C_EPLL_LOCK S3C_CLKREG(0x08)
23#define S3C_APLL_CON S3C_CLKREG(0x0C)
24#define S3C_MPLL_CON S3C_CLKREG(0x10)
25#define S3C_EPLL_CON0 S3C_CLKREG(0x14)
26#define S3C_EPLL_CON1 S3C_CLKREG(0x18)
27#define S3C_CLK_SRC S3C_CLKREG(0x1C)
28#define S3C_CLK_DIV0 S3C_CLKREG(0x20)
29#define S3C_CLK_DIV1 S3C_CLKREG(0x24)
30#define S3C_CLK_DIV2 S3C_CLKREG(0x28)
31#define S3C_CLK_OUT S3C_CLKREG(0x2C)
32#define S3C_HCLK_GATE S3C_CLKREG(0x30)
33#define S3C_PCLK_GATE S3C_CLKREG(0x34)
34#define S3C_SCLK_GATE S3C_CLKREG(0x38)
35
36/* CLKDIV0 */
37#define S3C6400_CLKDIV0_MFC_MASK (0xf << 28)
38#define S3C6400_CLKDIV0_MFC_SHIFT (28)
39#define S3C6400_CLKDIV0_JPEG_MASK (0xf << 24)
40#define S3C6400_CLKDIV0_JPEG_SHIFT (24)
41#define S3C6400_CLKDIV0_CAM_MASK (0xf << 20)
42#define S3C6400_CLKDIV0_CAM_SHIFT (20)
43#define S3C6400_CLKDIV0_SECURITY_MASK (0x3 << 18)
44#define S3C6400_CLKDIV0_SECURITY_SHIFT (18)
45#define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12)
46#define S3C6400_CLKDIV0_PCLK_SHIFT (12)
47#define S3C6400_CLKDIV0_HCLK2_MASK (0x7 << 9)
48#define S3C6400_CLKDIV0_HCLK2_SHIFT (9)
49#define S3C6400_CLKDIV0_HCLK_MASK (0x1 << 8)
50#define S3C6400_CLKDIV0_HCLK_SHIFT (8)
51#define S3C6400_CLKDIV0_MPLL_MASK (0x1 << 4)
52#define S3C6400_CLKDIV0_MPLL_SHIFT (4)
53#define S3C6400_CLKDIV0_ARM_MASK (0x3 << 0)
54#define S3C6410_CLKDIV0_ARM_MASK (0x7 << 0)
55#define S3C6400_CLKDIV0_ARM_SHIFT (0)
56
57/* CLKDIV1 */
58#define S3C6410_CLKDIV1_FIMC_MASK (0xf << 24)
59#define S3C6410_CLKDIV1_FIMC_SHIFT (24)
60#define S3C6400_CLKDIV1_UHOST_MASK (0xf << 20)
61#define S3C6400_CLKDIV1_UHOST_SHIFT (20)
62#define S3C6400_CLKDIV1_SCALER_MASK (0xf << 16)
63#define S3C6400_CLKDIV1_SCALER_SHIFT (16)
64#define S3C6400_CLKDIV1_LCD_MASK (0xf << 12)
65#define S3C6400_CLKDIV1_LCD_SHIFT (12)
66#define S3C6400_CLKDIV1_MMC2_MASK (0xf << 8)
67#define S3C6400_CLKDIV1_MMC2_SHIFT (8)
68#define S3C6400_CLKDIV1_MMC1_MASK (0xf << 4)
69#define S3C6400_CLKDIV1_MMC1_SHIFT (4)
70#define S3C6400_CLKDIV1_MMC0_MASK (0xf << 0)
71#define S3C6400_CLKDIV1_MMC0_SHIFT (0)
72
73/* CLKDIV2 */
74#define S3C6410_CLKDIV2_AUDIO2_MASK (0xf << 24)
75#define S3C6410_CLKDIV2_AUDIO2_SHIFT (24)
76#define S3C6400_CLKDIV2_IRDA_MASK (0xf << 20)
77#define S3C6400_CLKDIV2_IRDA_SHIFT (20)
78#define S3C6400_CLKDIV2_UART_MASK (0xf << 16)
79#define S3C6400_CLKDIV2_UART_SHIFT (16)
80#define S3C6400_CLKDIV2_AUDIO1_MASK (0xf << 12)
81#define S3C6400_CLKDIV2_AUDIO1_SHIFT (12)
82#define S3C6400_CLKDIV2_AUDIO0_MASK (0xf << 8)
83#define S3C6400_CLKDIV2_AUDIO0_SHIFT (8)
84#define S3C6400_CLKDIV2_SPI1_MASK (0xf << 4)
85#define S3C6400_CLKDIV2_SPI1_SHIFT (4)
86#define S3C6400_CLKDIV2_SPI0_MASK (0xf << 0)
87#define S3C6400_CLKDIV2_SPI0_SHIFT (0)
88
89/* HCLK GATE Registers */
90#define S3C_CLKCON_HCLK_BUS (1<<30)
91#define S3C_CLKCON_HCLK_SECUR (1<<29)
92#define S3C_CLKCON_HCLK_SDMA1 (1<<28)
93#define S3C_CLKCON_HCLK_SDMA2 (1<<27)
94#define S3C_CLKCON_HCLK_UHOST (1<<26)
95#define S3C_CLKCON_HCLK_IROM (1<<25)
96#define S3C_CLKCON_HCLK_DDR1 (1<<24)
97#define S3C_CLKCON_HCLK_DDR0 (1<<23)
98#define S3C_CLKCON_HCLK_MEM1 (1<<22)
99#define S3C_CLKCON_HCLK_MEM0 (1<<21)
100#define S3C_CLKCON_HCLK_USB (1<<20)
101#define S3C_CLKCON_HCLK_HSMMC2 (1<<19)
102#define S3C_CLKCON_HCLK_HSMMC1 (1<<18)
103#define S3C_CLKCON_HCLK_HSMMC0 (1<<17)
104#define S3C_CLKCON_HCLK_MDP (1<<16)
105#define S3C_CLKCON_HCLK_DHOST (1<<15)
106#define S3C_CLKCON_HCLK_IHOST (1<<14)
107#define S3C_CLKCON_HCLK_DMA1 (1<<13)
108#define S3C_CLKCON_HCLK_DMA0 (1<<12)
109#define S3C_CLKCON_HCLK_JPEG (1<<11)
110#define S3C_CLKCON_HCLK_CAMIF (1<<10)
111#define S3C_CLKCON_HCLK_SCALER (1<<9)
112#define S3C_CLKCON_HCLK_2D (1<<8)
113#define S3C_CLKCON_HCLK_TV (1<<7)
114#define S3C_CLKCON_HCLK_POST0 (1<<5)
115#define S3C_CLKCON_HCLK_ROT (1<<4)
116#define S3C_CLKCON_HCLK_LCD (1<<3)
117#define S3C_CLKCON_HCLK_TZIC (1<<2)
118#define S3C_CLKCON_HCLK_INTC (1<<1)
119#define S3C_CLKCON_HCLK_MFC (1<<0)
120
121/* PCLK GATE Registers */
122#define S3C6410_CLKCON_PCLK_I2C1 (1<<27)
123#define S3C6410_CLKCON_PCLK_IIS2 (1<<26)
124#define S3C_CLKCON_PCLK_SKEY (1<<24)
125#define S3C_CLKCON_PCLK_CHIPID (1<<23)
126#define S3C_CLKCON_PCLK_SPI1 (1<<22)
127#define S3C_CLKCON_PCLK_SPI0 (1<<21)
128#define S3C_CLKCON_PCLK_HSIRX (1<<20)
129#define S3C_CLKCON_PCLK_HSITX (1<<19)
130#define S3C_CLKCON_PCLK_GPIO (1<<18)
131#define S3C_CLKCON_PCLK_IIC (1<<17)
132#define S3C_CLKCON_PCLK_IIS1 (1<<16)
133#define S3C_CLKCON_PCLK_IIS0 (1<<15)
134#define S3C_CLKCON_PCLK_AC97 (1<<14)
135#define S3C_CLKCON_PCLK_TZPC (1<<13)
136#define S3C_CLKCON_PCLK_TSADC (1<<12)
137#define S3C_CLKCON_PCLK_KEYPAD (1<<11)
138#define S3C_CLKCON_PCLK_IRDA (1<<10)
139#define S3C_CLKCON_PCLK_PCM1 (1<<9)
140#define S3C_CLKCON_PCLK_PCM0 (1<<8)
141#define S3C_CLKCON_PCLK_PWM (1<<7)
142#define S3C_CLKCON_PCLK_RTC (1<<6)
143#define S3C_CLKCON_PCLK_WDT (1<<5)
144#define S3C_CLKCON_PCLK_UART3 (1<<4)
145#define S3C_CLKCON_PCLK_UART2 (1<<3)
146#define S3C_CLKCON_PCLK_UART1 (1<<2)
147#define S3C_CLKCON_PCLK_UART0 (1<<1)
148#define S3C_CLKCON_PCLK_MFC (1<<0)
149
150/* SCLK GATE Registers */
151#define S3C_CLKCON_SCLK_UHOST (1<<30)
152#define S3C_CLKCON_SCLK_MMC2_48 (1<<29)
153#define S3C_CLKCON_SCLK_MMC1_48 (1<<28)
154#define S3C_CLKCON_SCLK_MMC0_48 (1<<27)
155#define S3C_CLKCON_SCLK_MMC2 (1<<26)
156#define S3C_CLKCON_SCLK_MMC1 (1<<25)
157#define S3C_CLKCON_SCLK_MMC0 (1<<24)
158#define S3C_CLKCON_SCLK_SPI1_48 (1<<23)
159#define S3C_CLKCON_SCLK_SPI0_48 (1<<22)
160#define S3C_CLKCON_SCLK_SPI1 (1<<21)
161#define S3C_CLKCON_SCLK_SPI0 (1<<20)
162#define S3C_CLKCON_SCLK_DAC27 (1<<19)
163#define S3C_CLKCON_SCLK_TV27 (1<<18)
164#define S3C_CLKCON_SCLK_SCALER27 (1<<17)
165#define S3C_CLKCON_SCLK_SCALER (1<<16)
166#define S3C_CLKCON_SCLK_LCD27 (1<<15)
167#define S3C_CLKCON_SCLK_LCD (1<<14)
168#define S3C6400_CLKCON_SCLK_POST1_27 (1<<13)
169#define S3C6410_CLKCON_FIMC (1<<13)
170#define S3C_CLKCON_SCLK_POST0_27 (1<<12)
171#define S3C6400_CLKCON_SCLK_POST1 (1<<11)
172#define S3C6410_CLKCON_SCLK_AUDIO2 (1<<11)
173#define S3C_CLKCON_SCLK_POST0 (1<<10)
174#define S3C_CLKCON_SCLK_AUDIO1 (1<<9)
175#define S3C_CLKCON_SCLK_AUDIO0 (1<<8)
176#define S3C_CLKCON_SCLK_SECUR (1<<7)
177#define S3C_CLKCON_SCLK_IRDA (1<<6)
178#define S3C_CLKCON_SCLK_UART (1<<5)
179#define S3C_CLKCON_SCLK_ONENAND (1<<4)
180#define S3C_CLKCON_SCLK_MFC (1<<3)
181#define S3C_CLKCON_SCLK_CAM (1<<2)
182#define S3C_CLKCON_SCLK_JPEG (1<<1)
183
184/* CLKSRC */
185
186#define S3C6400_CLKSRC_APLL_MOUT (1 << 0)
187#define S3C6400_CLKSRC_MPLL_MOUT (1 << 1)
188#define S3C6400_CLKSRC_EPLL_MOUT (1 << 2)
189#define S3C6400_CLKSRC_APLL_MOUT_SHIFT (0)
190#define S3C6400_CLKSRC_MPLL_MOUT_SHIFT (1)
191#define S3C6400_CLKSRC_EPLL_MOUT_SHIFT (2)
192#define S3C6400_CLKSRC_MFC (1 << 4)
193
194#define S3C6410_CLKSRC_TV27_MASK (0x1 << 31)
195#define S3C6410_CLKSRC_TV27_SHIFT (31)
196#define S3C6410_CLKSRC_DAC27_MASK (0x1 << 30)
197#define S3C6410_CLKSRC_DAC27_SHIFT (30)
198#define S3C6400_CLKSRC_SCALER_MASK (0x3 << 28)
199#define S3C6400_CLKSRC_SCALER_SHIFT (28)
200#define S3C6400_CLKSRC_LCD_MASK (0x3 << 26)
201#define S3C6400_CLKSRC_LCD_SHIFT (26)
202#define S3C6400_CLKSRC_IRDA_MASK (0x3 << 24)
203#define S3C6400_CLKSRC_IRDA_SHIFT (24)
204#define S3C6400_CLKSRC_MMC2_MASK (0x3 << 22)
205#define S3C6400_CLKSRC_MMC2_SHIFT (22)
206#define S3C6400_CLKSRC_MMC1_MASK (0x3 << 20)
207#define S3C6400_CLKSRC_MMC1_SHIFT (20)
208#define S3C6400_CLKSRC_MMC0_MASK (0x3 << 18)
209#define S3C6400_CLKSRC_MMC0_SHIFT (18)
210#define S3C6400_CLKSRC_SPI1_MASK (0x3 << 16)
211#define S3C6400_CLKSRC_SPI1_SHIFT (16)
212#define S3C6400_CLKSRC_SPI0_MASK (0x3 << 14)
213#define S3C6400_CLKSRC_SPI0_SHIFT (14)
214#define S3C6400_CLKSRC_UART_MASK (0x1 << 13)
215#define S3C6400_CLKSRC_UART_SHIFT (13)
216#define S3C6400_CLKSRC_AUDIO1_MASK (0x7 << 10)
217#define S3C6400_CLKSRC_AUDIO1_SHIFT (10)
218#define S3C6400_CLKSRC_AUDIO0_MASK (0x7 << 7)
219#define S3C6400_CLKSRC_AUDIO0_SHIFT (7)
220#define S3C6400_CLKSRC_UHOST_MASK (0x3 << 5)
221#define S3C6400_CLKSRC_UHOST_SHIFT (5)
222
223
224#endif /* _PLAT_REGS_CLOCK_H */
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-sys.h b/arch/arm/plat-s3c64xx/include/plat/regs-sys.h
new file mode 100644
index 000000000000..d8ed82917096
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-sys.h
@@ -0,0 +1,24 @@
1/* arch/arm/plat-s3c64xx/include/plat/regs-sys.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX system register definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __PLAT_REGS_SYS_H
16#define __PLAT_REGS_SYS_H __FILE__
17
18#define S3C_SYSREG(x) (S3C_VA_SYS + (x))
19
20#define S3C64XX_OTHERS S3C_SYSREG(0x900)
21
22#define S3C64XX_OTHERS_USBMASK (1 << 16)
23
24#endif /* _PLAT_REGS_SYS_H */
diff --git a/arch/arm/plat-s3c64xx/include/plat/s3c6400.h b/arch/arm/plat-s3c64xx/include/plat/s3c6400.h
new file mode 100644
index 000000000000..571eaa2e54f1
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/s3c6400.h
@@ -0,0 +1,35 @@
1/* arch/arm/plat-s3c64xx/include/plat/s3c6400.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * Header file for s3c6400 cpu support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/* Common init code for S3C6400 related SoCs */
16
17extern void s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
18extern void s3c6400_register_clocks(void);
19extern void s3c6400_setup_clocks(void);
20
21#ifdef CONFIG_CPU_S3C6400
22
23extern int s3c6400_init(void);
24extern void s3c6400_map_io(void);
25extern void s3c6400_init_clocks(int xtal);
26
27#define s3c6400_init_uarts s3c6400_common_init_uarts
28
29#else
30#define s3c6400_init_clocks NULL
31#define s3c6400_init_uarts NULL
32#define s3c6400_map_io NULL
33#define s3c6400_init NULL
34#endif
35
diff --git a/arch/arm/plat-s3c64xx/include/plat/s3c6410.h b/arch/arm/plat-s3c64xx/include/plat/s3c6410.h
new file mode 100644
index 000000000000..50dcdd6f6800
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/s3c6410.h
@@ -0,0 +1,29 @@
1/* arch/arm/plat-s3c64xx/include/plat/s3c6410.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * Header file for s3c6410 cpu support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifdef CONFIG_CPU_S3C6410
16
17extern int s3c6410_init(void);
18extern void s3c6410_init_irq(void);
19extern void s3c6410_map_io(void);
20extern void s3c6410_init_clocks(int xtal);
21
22#define s3c6410_init_uarts s3c6400_common_init_uarts
23
24#else
25#define s3c6410_init_clocks NULL
26#define s3c6410_init_uarts NULL
27#define s3c6410_map_io NULL
28#define s3c6410_init NULL
29#endif
diff --git a/arch/arm/plat-s3c64xx/irq-eint.c b/arch/arm/plat-s3c64xx/irq-eint.c
new file mode 100644
index 000000000000..1f7cc0067f5c
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/irq-eint.c
@@ -0,0 +1,202 @@
1/* arch/arm/plat-s3c64xx/irq-eint.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX - Interrupt handling for IRQ_EINT(x)
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/interrupt.h>
17#include <linux/irq.h>
18#include <linux/io.h>
19
20#include <asm/hardware/vic.h>
21
22#include <plat/regs-irqtype.h>
23
24#include <mach/map.h>
25#include <plat/cpu.h>
26
27/* GPIO is 0x7F008xxx, */
28#define S3C64XX_GPIOREG(x) (S3C64XX_VA_GPIO + (x))
29
30#define S3C64XX_EINT0CON0 S3C64XX_GPIOREG(0x900)
31#define S3C64XX_EINT0CON1 S3C64XX_GPIOREG(0x904)
32#define S3C64XX_EINT0FLTCON0 S3C64XX_GPIOREG(0x910)
33#define S3C64XX_EINT0FLTCON1 S3C64XX_GPIOREG(0x914)
34#define S3C64XX_EINT0FLTCON2 S3C64XX_GPIOREG(0x918)
35#define S3C64XX_EINT0FLTCON3 S3C64XX_GPIOREG(0x91C)
36
37#define S3C64XX_EINT0MASK S3C64XX_GPIOREG(0x920)
38#define S3C64XX_EINT0PEND S3C64XX_GPIOREG(0x924)
39
40
41#define eint_offset(irq) ((irq) - IRQ_EINT(0))
42#define eint_irq_to_bit(irq) (1 << eint_offset(irq))
43
44static inline void s3c_irq_eint_mask(unsigned int irq)
45{
46 u32 mask;
47
48 mask = __raw_readl(S3C64XX_EINT0MASK);
49 mask |= eint_irq_to_bit(irq);
50 __raw_writel(mask, S3C64XX_EINT0MASK);
51}
52
53static void s3c_irq_eint_unmask(unsigned int irq)
54{
55 u32 mask;
56
57 mask = __raw_readl(S3C64XX_EINT0MASK);
58 mask |= eint_irq_to_bit(irq);
59 __raw_writel(mask, S3C64XX_EINT0MASK);
60}
61
62static inline void s3c_irq_eint_ack(unsigned int irq)
63{
64 __raw_writel(eint_irq_to_bit(irq), S3C64XX_EINT0PEND);
65}
66
67static void s3c_irq_eint_maskack(unsigned int irq)
68{
69 /* compiler should in-line these */
70 s3c_irq_eint_mask(irq);
71 s3c_irq_eint_ack(irq);
72}
73
74static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
75{
76 int offs = eint_offset(irq);
77 int shift;
78 u32 ctrl, mask;
79 u32 newvalue = 0;
80 void __iomem *reg;
81
82 if (offs > 27)
83 return -EINVAL;
84
85 if (offs <= 15)
86 reg = S3C64XX_EINT0CON0;
87 else
88 reg = S3C64XX_EINT0CON1;
89
90 switch (type) {
91 case IRQ_TYPE_NONE:
92 printk(KERN_WARNING "No edge setting!\n");
93 break;
94
95 case IRQ_TYPE_EDGE_RISING:
96 newvalue = S3C2410_EXTINT_RISEEDGE;
97 break;
98
99 case IRQ_TYPE_EDGE_FALLING:
100 newvalue = S3C2410_EXTINT_FALLEDGE;
101 break;
102
103 case IRQ_TYPE_EDGE_BOTH:
104 newvalue = S3C2410_EXTINT_BOTHEDGE;
105 break;
106
107 case IRQ_TYPE_LEVEL_LOW:
108 newvalue = S3C2410_EXTINT_LOWLEV;
109 break;
110
111 case IRQ_TYPE_LEVEL_HIGH:
112 newvalue = S3C2410_EXTINT_HILEV;
113 break;
114
115 default:
116 printk(KERN_ERR "No such irq type %d", type);
117 return -1;
118 }
119
120 shift = (offs / 2) * 4;
121 mask = 0x7 << shift;
122
123 ctrl = __raw_readl(reg);
124 ctrl &= ~mask;
125 ctrl |= newvalue << shift;
126 __raw_writel(ctrl, reg);
127
128 return 0;
129}
130
131static struct irq_chip s3c_irq_eint = {
132 .name = "s3c-eint",
133 .mask = s3c_irq_eint_mask,
134 .unmask = s3c_irq_eint_unmask,
135 .mask_ack = s3c_irq_eint_maskack,
136 .ack = s3c_irq_eint_ack,
137 .set_type = s3c_irq_eint_set_type,
138};
139
140/* s3c_irq_demux_eint
141 *
142 * This function demuxes the IRQ from the group0 external interrupts,
143 * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
144 * the specific handlers s3c_irq_demux_eintX_Y.
145 */
146static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
147{
148 u32 status = __raw_readl(S3C64XX_EINT0PEND);
149 u32 mask = __raw_readl(S3C64XX_EINT0MASK);
150 unsigned int irq;
151
152 status &= ~mask;
153 status >>= start;
154 status &= (1 << (end - start + 1)) - 1;
155
156 for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
157 if (status & 1)
158 generic_handle_irq(irq);
159
160 status >>= 1;
161 }
162}
163
164static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
165{
166 s3c_irq_demux_eint(0, 3);
167}
168
169static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
170{
171 s3c_irq_demux_eint(4, 11);
172}
173
174static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
175{
176 s3c_irq_demux_eint(12, 19);
177}
178
179static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
180{
181 s3c_irq_demux_eint(20, 27);
182}
183
184int __init s3c64xx_init_irq_eint(void)
185{
186 int irq;
187
188 for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
189 set_irq_chip(irq, &s3c_irq_eint);
190 set_irq_handler(irq, handle_level_irq);
191 set_irq_flags(irq, IRQF_VALID);
192 }
193
194 set_irq_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
195 set_irq_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
196 set_irq_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
197 set_irq_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
198
199 return 0;
200}
201
202arch_initcall(s3c64xx_init_irq_eint);
diff --git a/arch/arm/plat-s3c64xx/irq.c b/arch/arm/plat-s3c64xx/irq.c
new file mode 100644
index 000000000000..a94f1d5e819d
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/irq.c
@@ -0,0 +1,257 @@
1/* arch/arm/plat-s3c64xx/irq.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX - Interrupt handling
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/interrupt.h>
17#include <linux/irq.h>
18#include <linux/io.h>
19
20#include <asm/hardware/vic.h>
21
22#include <mach/map.h>
23#include <plat/regs-timer.h>
24#include <plat/cpu.h>
25
26/* Timer interrupt handling */
27
28static void s3c_irq_demux_timer(unsigned int base_irq, unsigned int sub_irq)
29{
30 generic_handle_irq(sub_irq);
31}
32
33static void s3c_irq_demux_timer0(unsigned int irq, struct irq_desc *desc)
34{
35 s3c_irq_demux_timer(irq, IRQ_TIMER0);
36}
37
38static void s3c_irq_demux_timer1(unsigned int irq, struct irq_desc *desc)
39{
40 s3c_irq_demux_timer(irq, IRQ_TIMER1);
41}
42
43static void s3c_irq_demux_timer2(unsigned int irq, struct irq_desc *desc)
44{
45 s3c_irq_demux_timer(irq, IRQ_TIMER2);
46}
47
48static void s3c_irq_demux_timer3(unsigned int irq, struct irq_desc *desc)
49{
50 s3c_irq_demux_timer(irq, IRQ_TIMER3);
51}
52
53static void s3c_irq_demux_timer4(unsigned int irq, struct irq_desc *desc)
54{
55 s3c_irq_demux_timer(irq, IRQ_TIMER4);
56}
57
58/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
59
60static void s3c_irq_timer_mask(unsigned int irq)
61{
62 u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
63
64 reg &= 0x1f; /* mask out pending interrupts */
65 reg &= ~(1 << (irq - IRQ_TIMER0));
66 __raw_writel(reg, S3C64XX_TINT_CSTAT);
67}
68
69static void s3c_irq_timer_unmask(unsigned int irq)
70{
71 u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
72
73 reg &= 0x1f; /* mask out pending interrupts */
74 reg |= 1 << (irq - IRQ_TIMER0);
75 __raw_writel(reg, S3C64XX_TINT_CSTAT);
76}
77
78static void s3c_irq_timer_ack(unsigned int irq)
79{
80 u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
81
82 reg &= 0x1f;
83 reg |= (1 << 5) << (irq - IRQ_TIMER0);
84 __raw_writel(reg, S3C64XX_TINT_CSTAT);
85}
86
87static struct irq_chip s3c_irq_timer = {
88 .name = "s3c-timer",
89 .mask = s3c_irq_timer_mask,
90 .unmask = s3c_irq_timer_unmask,
91 .ack = s3c_irq_timer_ack,
92};
93
94struct uart_irq {
95 void __iomem *regs;
96 unsigned int base_irq;
97 unsigned int parent_irq;
98};
99
100/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
101 * are consecutive when looking up the interrupt in the demux routines.
102 */
103static struct uart_irq uart_irqs[] = {
104 [0] = {
105 .regs = S3C_VA_UART0,
106 .base_irq = IRQ_S3CUART_BASE0,
107 .parent_irq = IRQ_UART0,
108 },
109 [1] = {
110 .regs = S3C_VA_UART1,
111 .base_irq = IRQ_S3CUART_BASE1,
112 .parent_irq = IRQ_UART1,
113 },
114 [2] = {
115 .regs = S3C_VA_UART2,
116 .base_irq = IRQ_S3CUART_BASE2,
117 .parent_irq = IRQ_UART2,
118 },
119 [3] = {
120 .regs = S3C_VA_UART3,
121 .base_irq = IRQ_S3CUART_BASE3,
122 .parent_irq = IRQ_UART3,
123 },
124};
125
126static inline void __iomem *s3c_irq_uart_base(unsigned int irq)
127{
128 struct uart_irq *uirq = get_irq_chip_data(irq);
129 return uirq->regs;
130}
131
132static inline unsigned int s3c_irq_uart_bit(unsigned int irq)
133{
134 return irq & 3;
135}
136
137/* UART interrupt registers, not worth adding to seperate include header */
138#define S3C64XX_UINTP 0x30
139#define S3C64XX_UINTSP 0x34
140#define S3C64XX_UINTM 0x38
141
142static void s3c_irq_uart_mask(unsigned int irq)
143{
144 void __iomem *regs = s3c_irq_uart_base(irq);
145 unsigned int bit = s3c_irq_uart_bit(irq);
146 u32 reg;
147
148 reg = __raw_readl(regs + S3C64XX_UINTM);
149 reg |= (1 << bit);
150 __raw_writel(reg, regs + S3C64XX_UINTM);
151}
152
153static void s3c_irq_uart_maskack(unsigned int irq)
154{
155 void __iomem *regs = s3c_irq_uart_base(irq);
156 unsigned int bit = s3c_irq_uart_bit(irq);
157 u32 reg;
158
159 reg = __raw_readl(regs + S3C64XX_UINTM);
160 reg |= (1 << bit);
161 __raw_writel(reg, regs + S3C64XX_UINTM);
162 __raw_writel(1 << bit, regs + S3C64XX_UINTP);
163}
164
165static void s3c_irq_uart_unmask(unsigned int irq)
166{
167 void __iomem *regs = s3c_irq_uart_base(irq);
168 unsigned int bit = s3c_irq_uart_bit(irq);
169 u32 reg;
170
171 reg = __raw_readl(regs + S3C64XX_UINTM);
172 reg &= ~(1 << bit);
173 __raw_writel(reg, regs + S3C64XX_UINTM);
174}
175
176static void s3c_irq_uart_ack(unsigned int irq)
177{
178 void __iomem *regs = s3c_irq_uart_base(irq);
179 unsigned int bit = s3c_irq_uart_bit(irq);
180
181 __raw_writel(1 << bit, regs + S3C64XX_UINTP);
182}
183
184static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
185{
186 struct uart_irq *uirq = &uart_irqs[irq - IRQ_UART0];
187 u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP);
188 int base = uirq->base_irq;
189
190 if (pend & (1 << 0))
191 generic_handle_irq(base);
192 if (pend & (1 << 1))
193 generic_handle_irq(base + 1);
194 if (pend & (1 << 2))
195 generic_handle_irq(base + 2);
196 if (pend & (1 << 3))
197 generic_handle_irq(base + 3);
198}
199
200static struct irq_chip s3c_irq_uart = {
201 .name = "s3c-uart",
202 .mask = s3c_irq_uart_mask,
203 .unmask = s3c_irq_uart_unmask,
204 .mask_ack = s3c_irq_uart_maskack,
205 .ack = s3c_irq_uart_ack,
206};
207
208static void __init s3c64xx_uart_irq(struct uart_irq *uirq)
209{
210 void *reg_base = uirq->regs;
211 unsigned int irq;
212 int offs;
213
214 /* mask all interrupts at the start. */
215 __raw_writel(0xf, reg_base + S3C64XX_UINTM);
216
217 for (offs = 0; offs < 3; offs++) {
218 irq = uirq->base_irq + offs;
219
220 set_irq_chip(irq, &s3c_irq_uart);
221 set_irq_chip_data(irq, uirq);
222 set_irq_handler(irq, handle_level_irq);
223 set_irq_flags(irq, IRQF_VALID);
224 }
225
226 set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
227}
228
229void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
230{
231 int uart, irq;
232
233 printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
234
235 /* initialise the pair of VICs */
236 vic_init(S3C_VA_VIC0, S3C_VIC0_BASE, vic0_valid);
237 vic_init(S3C_VA_VIC1, S3C_VIC1_BASE, vic1_valid);
238
239 /* add the timer sub-irqs */
240
241 set_irq_chained_handler(IRQ_TIMER0_VIC, s3c_irq_demux_timer0);
242 set_irq_chained_handler(IRQ_TIMER1_VIC, s3c_irq_demux_timer1);
243 set_irq_chained_handler(IRQ_TIMER2_VIC, s3c_irq_demux_timer2);
244 set_irq_chained_handler(IRQ_TIMER3_VIC, s3c_irq_demux_timer3);
245 set_irq_chained_handler(IRQ_TIMER4_VIC, s3c_irq_demux_timer4);
246
247 for (irq = IRQ_TIMER0; irq <= IRQ_TIMER4; irq++) {
248 set_irq_chip(irq, &s3c_irq_timer);
249 set_irq_handler(irq, handle_level_irq);
250 set_irq_flags(irq, IRQF_VALID);
251 }
252
253 for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++)
254 s3c64xx_uart_irq(&uart_irqs[uart]);
255}
256
257
diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c
new file mode 100644
index 000000000000..8d9a0cada668
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c
@@ -0,0 +1,655 @@
1/* linux/arch/arm/plat-s3c64xx/s3c6400-clock.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C6400 based common clock support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/list.h>
19#include <linux/errno.h>
20#include <linux/err.h>
21#include <linux/clk.h>
22#include <linux/sysdev.h>
23#include <linux/io.h>
24
25#include <mach/hardware.h>
26#include <mach/map.h>
27
28#include <plat/cpu-freq.h>
29
30#include <plat/regs-clock.h>
31#include <plat/clock.h>
32#include <plat/cpu.h>
33#include <plat/pll.h>
34
35/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
36 * ext_xtal_mux for want of an actual name from the manual.
37*/
38
39struct clk clk_ext_xtal_mux = {
40 .name = "ext_xtal",
41 .id = -1,
42};
43
44#define clk_fin_apll clk_ext_xtal_mux
45#define clk_fin_mpll clk_ext_xtal_mux
46#define clk_fin_epll clk_ext_xtal_mux
47
48#define clk_fout_mpll clk_mpll
49
50struct clk_sources {
51 unsigned int nr_sources;
52 struct clk **sources;
53};
54
55struct clksrc_clk {
56 struct clk clk;
57 unsigned int mask;
58 unsigned int shift;
59
60 struct clk_sources *sources;
61
62 unsigned int divider_shift;
63 void __iomem *reg_divider;
64};
65
66struct clk clk_fout_apll = {
67 .name = "fout_apll",
68 .id = -1,
69};
70
71static struct clk *clk_src_apll_list[] = {
72 [0] = &clk_fin_apll,
73 [1] = &clk_fout_apll,
74};
75
76static struct clk_sources clk_src_apll = {
77 .sources = clk_src_apll_list,
78 .nr_sources = ARRAY_SIZE(clk_src_apll_list),
79};
80
81struct clksrc_clk clk_mout_apll = {
82 .clk = {
83 .name = "mout_apll",
84 .id = -1,
85 },
86 .shift = S3C6400_CLKSRC_APLL_MOUT_SHIFT,
87 .mask = S3C6400_CLKSRC_APLL_MOUT,
88 .sources = &clk_src_apll,
89};
90
91struct clk clk_fout_epll = {
92 .name = "fout_epll",
93 .id = -1,
94};
95
96static struct clk *clk_src_epll_list[] = {
97 [0] = &clk_fin_epll,
98 [1] = &clk_fout_epll,
99};
100
101static struct clk_sources clk_src_epll = {
102 .sources = clk_src_epll_list,
103 .nr_sources = ARRAY_SIZE(clk_src_epll_list),
104};
105
106struct clksrc_clk clk_mout_epll = {
107 .clk = {
108 .name = "mout_epll",
109 .id = -1,
110 },
111 .shift = S3C6400_CLKSRC_EPLL_MOUT_SHIFT,
112 .mask = S3C6400_CLKSRC_EPLL_MOUT,
113 .sources = &clk_src_epll,
114};
115
116static struct clk *clk_src_mpll_list[] = {
117 [0] = &clk_fin_mpll,
118 [1] = &clk_fout_mpll,
119};
120
121static struct clk_sources clk_src_mpll = {
122 .sources = clk_src_mpll_list,
123 .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
124};
125
126struct clksrc_clk clk_mout_mpll = {
127 .clk = {
128 .name = "mout_mpll",
129 .id = -1,
130 },
131 .shift = S3C6400_CLKSRC_MPLL_MOUT_SHIFT,
132 .mask = S3C6400_CLKSRC_MPLL_MOUT,
133 .sources = &clk_src_mpll,
134};
135
136static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
137{
138 unsigned long rate = clk_get_rate(clk->parent);
139
140 printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
141
142 if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
143 rate /= 2;
144
145 return rate;
146}
147
148struct clk clk_dout_mpll = {
149 .name = "dout_mpll",
150 .id = -1,
151 .parent = &clk_mout_mpll.clk,
152 .get_rate = s3c64xx_clk_doutmpll_get_rate,
153};
154
155static struct clk *clkset_spi_mmc_list[] = {
156 &clk_mout_epll.clk,
157 &clk_dout_mpll,
158 &clk_fin_epll,
159 &clk_27m,
160};
161
162static struct clk_sources clkset_spi_mmc = {
163 .sources = clkset_spi_mmc_list,
164 .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list),
165};
166
167static struct clk *clkset_irda_list[] = {
168 &clk_mout_epll.clk,
169 &clk_dout_mpll,
170 NULL,
171 &clk_27m,
172};
173
174static struct clk_sources clkset_irda = {
175 .sources = clkset_irda_list,
176 .nr_sources = ARRAY_SIZE(clkset_irda_list),
177};
178
179static struct clk *clkset_uart_list[] = {
180 &clk_mout_epll.clk,
181 &clk_dout_mpll,
182 NULL,
183 NULL
184};
185
186static struct clk_sources clkset_uart = {
187 .sources = clkset_uart_list,
188 .nr_sources = ARRAY_SIZE(clkset_uart_list),
189};
190
191static struct clk *clkset_uhost_list[] = {
192 &clk_mout_epll.clk,
193 &clk_dout_mpll,
194 &clk_fin_epll,
195 &clk_48m,
196};
197
198static struct clk_sources clkset_uhost = {
199 .sources = clkset_uhost_list,
200 .nr_sources = ARRAY_SIZE(clkset_uhost_list),
201};
202
203
204/* The peripheral clocks are all controlled via clocksource followed
205 * by an optional divider and gate stage. We currently roll this into
206 * one clock which hides the intermediate clock from the mux.
207 *
208 * Note, the JPEG clock can only be an even divider...
209 *
210 * The scaler and LCD clocks depend on the S3C64XX version, and also
211 * have a common parent divisor so are not included here.
212 */
213
214static inline struct clksrc_clk *to_clksrc(struct clk *clk)
215{
216 return container_of(clk, struct clksrc_clk, clk);
217}
218
219static unsigned long s3c64xx_getrate_clksrc(struct clk *clk)
220{
221 struct clksrc_clk *sclk = to_clksrc(clk);
222 unsigned long rate = clk_get_rate(clk->parent);
223 u32 clkdiv = __raw_readl(sclk->reg_divider);
224
225 clkdiv >>= sclk->divider_shift;
226 clkdiv &= 0xf;
227 clkdiv++;
228
229 rate /= clkdiv;
230 return rate;
231}
232
233static int s3c64xx_setrate_clksrc(struct clk *clk, unsigned long rate)
234{
235 struct clksrc_clk *sclk = to_clksrc(clk);
236 void __iomem *reg = sclk->reg_divider;
237 unsigned int div;
238 u32 val;
239
240 rate = clk_round_rate(clk, rate);
241 div = clk_get_rate(clk->parent) / rate;
242
243 val = __raw_readl(reg);
244 val &= ~sclk->mask;
245 val |= (rate - 1) << sclk->shift;
246 __raw_writel(val, reg);
247
248 return 0;
249}
250
251static int s3c64xx_setparent_clksrc(struct clk *clk, struct clk *parent)
252{
253 struct clksrc_clk *sclk = to_clksrc(clk);
254 struct clk_sources *srcs = sclk->sources;
255 u32 clksrc = __raw_readl(S3C_CLK_SRC);
256 int src_nr = -1;
257 int ptr;
258
259 for (ptr = 0; ptr < srcs->nr_sources; ptr++)
260 if (srcs->sources[ptr] == parent) {
261 src_nr = ptr;
262 break;
263 }
264
265 if (src_nr >= 0) {
266 clksrc &= ~sclk->mask;
267 clksrc |= src_nr << sclk->shift;
268
269 __raw_writel(clksrc, S3C_CLK_SRC);
270 return 0;
271 }
272
273 return -EINVAL;
274}
275
276static unsigned long s3c64xx_roundrate_clksrc(struct clk *clk,
277 unsigned long rate)
278{
279 unsigned long parent_rate = clk_get_rate(clk->parent);
280 int div;
281
282 if (rate > parent_rate)
283 rate = parent_rate;
284 else {
285 div = rate / parent_rate;
286
287 if (div == 0)
288 div = 1;
289 if (div > 16)
290 div = 16;
291
292 rate = parent_rate / div;
293 }
294
295 return rate;
296}
297
298static struct clksrc_clk clk_mmc0 = {
299 .clk = {
300 .name = "mmc_bus",
301 .id = 0,
302 .ctrlbit = S3C_CLKCON_SCLK_MMC0,
303 .enable = s3c64xx_sclk_ctrl,
304 .set_parent = s3c64xx_setparent_clksrc,
305 .get_rate = s3c64xx_getrate_clksrc,
306 .set_rate = s3c64xx_setrate_clksrc,
307 .round_rate = s3c64xx_roundrate_clksrc,
308 },
309 .shift = S3C6400_CLKSRC_MMC0_SHIFT,
310 .mask = S3C6400_CLKSRC_MMC0_MASK,
311 .sources = &clkset_spi_mmc,
312 .divider_shift = S3C6400_CLKDIV1_MMC0_SHIFT,
313 .reg_divider = S3C_CLK_DIV1,
314};
315
316static struct clksrc_clk clk_mmc1 = {
317 .clk = {
318 .name = "mmc_bus",
319 .id = 1,
320 .ctrlbit = S3C_CLKCON_SCLK_MMC1,
321 .enable = s3c64xx_sclk_ctrl,
322 .get_rate = s3c64xx_getrate_clksrc,
323 .set_rate = s3c64xx_setrate_clksrc,
324 .set_parent = s3c64xx_setparent_clksrc,
325 .round_rate = s3c64xx_roundrate_clksrc,
326 },
327 .shift = S3C6400_CLKSRC_MMC1_SHIFT,
328 .mask = S3C6400_CLKSRC_MMC1_MASK,
329 .sources = &clkset_spi_mmc,
330 .divider_shift = S3C6400_CLKDIV1_MMC1_SHIFT,
331 .reg_divider = S3C_CLK_DIV1,
332};
333
334static struct clksrc_clk clk_mmc2 = {
335 .clk = {
336 .name = "mmc_bus",
337 .id = 2,
338 .ctrlbit = S3C_CLKCON_SCLK_MMC2,
339 .enable = s3c64xx_sclk_ctrl,
340 .get_rate = s3c64xx_getrate_clksrc,
341 .set_rate = s3c64xx_setrate_clksrc,
342 .set_parent = s3c64xx_setparent_clksrc,
343 .round_rate = s3c64xx_roundrate_clksrc,
344 },
345 .shift = S3C6400_CLKSRC_MMC2_SHIFT,
346 .mask = S3C6400_CLKSRC_MMC2_MASK,
347 .sources = &clkset_spi_mmc,
348 .divider_shift = S3C6400_CLKDIV1_MMC2_SHIFT,
349 .reg_divider = S3C_CLK_DIV1,
350};
351
352static struct clksrc_clk clk_usbhost = {
353 .clk = {
354 .name = "usb-host-bus",
355 .id = -1,
356 .ctrlbit = S3C_CLKCON_SCLK_UHOST,
357 .enable = s3c64xx_sclk_ctrl,
358 .set_parent = s3c64xx_setparent_clksrc,
359 .get_rate = s3c64xx_getrate_clksrc,
360 .set_rate = s3c64xx_setrate_clksrc,
361 .round_rate = s3c64xx_roundrate_clksrc,
362 },
363 .shift = S3C6400_CLKSRC_UHOST_SHIFT,
364 .mask = S3C6400_CLKSRC_UHOST_MASK,
365 .sources = &clkset_uhost,
366 .divider_shift = S3C6400_CLKDIV1_UHOST_SHIFT,
367 .reg_divider = S3C_CLK_DIV1,
368};
369
370static struct clksrc_clk clk_uart_uclk1 = {
371 .clk = {
372 .name = "uclk1",
373 .id = -1,
374 .ctrlbit = S3C_CLKCON_SCLK_UART,
375 .enable = s3c64xx_sclk_ctrl,
376 .set_parent = s3c64xx_setparent_clksrc,
377 .get_rate = s3c64xx_getrate_clksrc,
378 .set_rate = s3c64xx_setrate_clksrc,
379 .round_rate = s3c64xx_roundrate_clksrc,
380 },
381 .shift = S3C6400_CLKSRC_UART_SHIFT,
382 .mask = S3C6400_CLKSRC_UART_MASK,
383 .sources = &clkset_uart,
384 .divider_shift = S3C6400_CLKDIV2_UART_SHIFT,
385 .reg_divider = S3C_CLK_DIV2,
386};
387
388/* Where does UCLK0 come from? */
389
390static struct clksrc_clk clk_spi0 = {
391 .clk = {
392 .name = "spi-bus",
393 .id = 0,
394 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
395 .enable = s3c64xx_sclk_ctrl,
396 .set_parent = s3c64xx_setparent_clksrc,
397 .get_rate = s3c64xx_getrate_clksrc,
398 .set_rate = s3c64xx_setrate_clksrc,
399 .round_rate = s3c64xx_roundrate_clksrc,
400 },
401 .shift = S3C6400_CLKSRC_SPI0_SHIFT,
402 .mask = S3C6400_CLKSRC_SPI0_MASK,
403 .sources = &clkset_spi_mmc,
404 .divider_shift = S3C6400_CLKDIV2_SPI0_SHIFT,
405 .reg_divider = S3C_CLK_DIV2,
406};
407
408static struct clksrc_clk clk_spi1 = {
409 .clk = {
410 .name = "spi-bus",
411 .id = 1,
412 .ctrlbit = S3C_CLKCON_SCLK_SPI1,
413 .enable = s3c64xx_sclk_ctrl,
414 .set_parent = s3c64xx_setparent_clksrc,
415 .get_rate = s3c64xx_getrate_clksrc,
416 .set_rate = s3c64xx_setrate_clksrc,
417 .round_rate = s3c64xx_roundrate_clksrc,
418 },
419 .shift = S3C6400_CLKSRC_SPI1_SHIFT,
420 .mask = S3C6400_CLKSRC_SPI1_MASK,
421 .sources = &clkset_spi_mmc,
422 .divider_shift = S3C6400_CLKDIV2_SPI1_SHIFT,
423 .reg_divider = S3C_CLK_DIV2,
424};
425
426static struct clk clk_iis_cd0 = {
427 .name = "iis_cdclk0",
428 .id = -1,
429};
430
431static struct clk clk_iis_cd1 = {
432 .name = "iis_cdclk1",
433 .id = -1,
434};
435
436static struct clk clk_pcm_cd = {
437 .name = "pcm_cdclk",
438 .id = -1,
439};
440
441static struct clk *clkset_audio0_list[] = {
442 [0] = &clk_mout_epll.clk,
443 [1] = &clk_dout_mpll,
444 [2] = &clk_fin_epll,
445 [3] = &clk_iis_cd0,
446 [4] = &clk_pcm_cd,
447};
448
449static struct clk_sources clkset_audio0 = {
450 .sources = clkset_audio0_list,
451 .nr_sources = ARRAY_SIZE(clkset_audio0_list),
452};
453
454static struct clksrc_clk clk_audio0 = {
455 .clk = {
456 .name = "audio-bus",
457 .id = 0,
458 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
459 .enable = s3c64xx_sclk_ctrl,
460 .set_parent = s3c64xx_setparent_clksrc,
461 .get_rate = s3c64xx_getrate_clksrc,
462 .set_rate = s3c64xx_setrate_clksrc,
463 .round_rate = s3c64xx_roundrate_clksrc,
464 },
465 .shift = S3C6400_CLKSRC_AUDIO0_SHIFT,
466 .mask = S3C6400_CLKSRC_AUDIO0_MASK,
467 .sources = &clkset_audio0,
468 .divider_shift = S3C6400_CLKDIV2_AUDIO0_SHIFT,
469 .reg_divider = S3C_CLK_DIV2,
470};
471
472static struct clk *clkset_audio1_list[] = {
473 [0] = &clk_mout_epll.clk,
474 [1] = &clk_dout_mpll,
475 [2] = &clk_fin_epll,
476 [3] = &clk_iis_cd1,
477 [4] = &clk_pcm_cd,
478};
479
480static struct clk_sources clkset_audio1 = {
481 .sources = clkset_audio1_list,
482 .nr_sources = ARRAY_SIZE(clkset_audio1_list),
483};
484
485static struct clksrc_clk clk_audio1 = {
486 .clk = {
487 .name = "audio-bus",
488 .id = 1,
489 .ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
490 .enable = s3c64xx_sclk_ctrl,
491 .set_parent = s3c64xx_setparent_clksrc,
492 .get_rate = s3c64xx_getrate_clksrc,
493 .set_rate = s3c64xx_setrate_clksrc,
494 .round_rate = s3c64xx_roundrate_clksrc,
495 },
496 .shift = S3C6400_CLKSRC_AUDIO1_SHIFT,
497 .mask = S3C6400_CLKSRC_AUDIO1_MASK,
498 .sources = &clkset_audio1,
499 .divider_shift = S3C6400_CLKDIV2_AUDIO1_SHIFT,
500 .reg_divider = S3C_CLK_DIV2,
501};
502
503static struct clksrc_clk clk_irda = {
504 .clk = {
505 .name = "irda-bus",
506 .id = 0,
507 .ctrlbit = S3C_CLKCON_SCLK_IRDA,
508 .enable = s3c64xx_sclk_ctrl,
509 .set_parent = s3c64xx_setparent_clksrc,
510 .get_rate = s3c64xx_getrate_clksrc,
511 .set_rate = s3c64xx_setrate_clksrc,
512 .round_rate = s3c64xx_roundrate_clksrc,
513 },
514 .shift = S3C6400_CLKSRC_IRDA_SHIFT,
515 .mask = S3C6400_CLKSRC_IRDA_MASK,
516 .sources = &clkset_irda,
517 .divider_shift = S3C6400_CLKDIV2_IRDA_SHIFT,
518 .reg_divider = S3C_CLK_DIV2,
519};
520
521/* Clock initialisation code */
522
523static struct clksrc_clk *init_parents[] = {
524 &clk_mout_apll,
525 &clk_mout_epll,
526 &clk_mout_mpll,
527 &clk_mmc0,
528 &clk_mmc1,
529 &clk_mmc2,
530 &clk_usbhost,
531 &clk_uart_uclk1,
532 &clk_spi0,
533 &clk_spi1,
534 &clk_audio0,
535 &clk_audio1,
536 &clk_irda,
537};
538
539static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk)
540{
541 struct clk_sources *srcs = clk->sources;
542 u32 clksrc = __raw_readl(S3C_CLK_SRC);
543
544 clksrc &= clk->mask;
545 clksrc >>= clk->shift;
546
547 if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {
548 printk(KERN_ERR "%s: bad source %d\n",
549 clk->clk.name, clksrc);
550 return;
551 }
552
553 clk->clk.parent = srcs->sources[clksrc];
554
555 printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
556 clk->clk.name, clk->clk.parent->name, clksrc,
557 clk_get_rate(&clk->clk));
558}
559
560#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
561
562void __init_or_cpufreq s3c6400_setup_clocks(void)
563{
564 struct clk *xtal_clk;
565 unsigned long xtal;
566 unsigned long fclk;
567 unsigned long hclk;
568 unsigned long hclk2;
569 unsigned long pclk;
570 unsigned long epll;
571 unsigned long apll;
572 unsigned long mpll;
573 unsigned int ptr;
574 u32 clkdiv0;
575
576 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
577
578 clkdiv0 = __raw_readl(S3C_CLK_DIV0);
579 printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
580
581 xtal_clk = clk_get(NULL, "xtal");
582 BUG_ON(IS_ERR(xtal_clk));
583
584 xtal = clk_get_rate(xtal_clk);
585 clk_put(xtal_clk);
586
587 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
588
589 epll = s3c6400_get_epll(xtal);
590 mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
591 apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
592
593 fclk = mpll;
594
595 printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
596 apll, mpll, epll);
597
598 hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
599 hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
600 pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
601
602 printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
603 hclk2, hclk, pclk);
604
605 clk_fout_mpll.rate = mpll;
606 clk_fout_epll.rate = epll;
607 clk_fout_apll.rate = apll;
608
609 clk_h.rate = hclk;
610 clk_p.rate = pclk;
611 clk_f.rate = fclk;
612
613 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
614 s3c6400_set_clksrc(init_parents[ptr]);
615}
616
617static struct clk *clks[] __initdata = {
618 &clk_ext_xtal_mux,
619 &clk_iis_cd0,
620 &clk_iis_cd1,
621 &clk_pcm_cd,
622 &clk_mout_epll.clk,
623 &clk_fout_epll,
624 &clk_mout_mpll.clk,
625 &clk_dout_mpll,
626 &clk_mmc0.clk,
627 &clk_mmc1.clk,
628 &clk_mmc2.clk,
629 &clk_usbhost.clk,
630 &clk_uart_uclk1.clk,
631 &clk_spi0.clk,
632 &clk_spi1.clk,
633 &clk_audio0.clk,
634 &clk_audio1.clk,
635 &clk_irda.clk,
636};
637
638void __init s3c6400_register_clocks(void)
639{
640 struct clk *clkp;
641 int ret;
642 int ptr;
643
644 for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
645 clkp = clks[ptr];
646 ret = s3c24xx_register_clock(clkp);
647 if (ret < 0) {
648 printk(KERN_ERR "Failed to register clock %s (%d)\n",
649 clkp->name, ret);
650 }
651 }
652
653 clk_mpll.parent = &clk_mout_mpll.clk;
654 clk_epll.parent = &clk_mout_epll.clk;
655}
diff --git a/arch/arm/plat-s3c64xx/s3c6400-init.c b/arch/arm/plat-s3c64xx/s3c6400-init.c
new file mode 100644
index 000000000000..6c28f39df097
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/s3c6400-init.c
@@ -0,0 +1,29 @@
1/* linux/arch/arm/plat-s3c64xx/s3c6400-init.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C6400 - CPU initialisation (common with other S3C64XX chips)
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/init.h>
18
19#include <plat/cpu.h>
20#include <plat/devs.h>
21#include <plat/s3c6400.h>
22#include <plat/s3c6410.h>
23
24/* uart registration process */
25
26void __init s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
27{
28 s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
29}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-22 09:50:58 -0500